1993_Cypress_High Performance_Data_book 1993 Cypress High Performance Data Book
User Manual: 1993_Cypress_High-Performance_Data_book
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CYPRESS
SEMICONDUCTOR
CYPRESS
SEMICONDUCTOR
High Performance
Data Book
Cypress Semiconductor is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor, 3901 North First St., San Jose, CA 95134 (408) 943-2600
Telex: 821032 CYPRESS SNJ UD, TWX: 910 997 0753, FAX: (408) 943-2741
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CYPRESS
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~:
~_
SEMlCONDUcrOR
How To Use This Book
Key to Waveform Diagrams
Overall Organization
This book has been organized by product type, beginning with Product Information. The products are
next, starting with SRAMs, then PROMs, EPLDs,
FIFOs, Logic, RISC, Modules, ECL, and bus interface products. A section containing military information is next, followed by the Design and Programming
Tools section. Quality and Reliability aspects are
next, then Thermal Data and Packages. Within each
section, data sheets are arranged in order of part
number.
Rising edge of signal will
occur during this time.
falling edge of signal will
occur during this time.
Signal may transition
during this time (don't
care condition).
Recommended Search Paths
To search by:
Use:
Product line
Table of Contents or flip
through the book u~ing the
tabs on the right-hand pages.
Size
The Product Selector Guide
in section 1.
Signal changes from highimpedance state to valid
logic level during this time.
Signal changes from valid
logic level to high-impedance
. state during this time.
Numeric part number Numeric Device Index in
section 1. The book is also
arranged in order of part
number.
Other manufacturer's The Cross Reference Guide
part number
in section 1.
Military part number
The Military Selector Guide
in section 11.
Abbreviations
TBD = To Be Determined
N/A = Not Applicable
Published August 1, 1993
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it conveyor imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure of the product may reasonably be expected to result in significant
injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies thatthe manufacturer assumes all risk of such use and in so doing indemnifies
Cypress Semiconductor against all damages.
•
~
Table of Contents
.: CYPRESS
SEMICONDUCIOR
General Product Information
Page Number
Cypress Semiconductor Background and Technology ........................................................... 1-1
Ordering Information ..................................................................................... 1-4
Datasheets Available Upon Request ......................................................................... 1-6
Cypress Semiconductor Bulletin Board System ................................................................ 1-8
Application Notes Listing .................................................................................. 1-9
Product Selector Guide ................................................................................... 1-11
Product Line Cross Reference ............................................................................. 1-19
Static RAMs (Random Access Memory)
Device Number
CY7C101A
CY7C102A
CY7CI06A
CY7C107A
CY7CI09A
CY7C123
CY7C128A
CY7C130
CY7C131
CY7C140
CY7C141
CY7C132
CY7C136
CY7C142
CY7C146
CY7B134
CY7B135
CY7B1342
CY7B138
CY7B139
CY7B144
CY7B145
CY7C148
CY7C149
CY7C150
::Y7B161
::Y7B162
CY7C161
CY7C162
CY7C161A
:::Y7C162A
:::Y7B164
:::Y7B166
:::Y7C164
CY7C166
CY7Cl64A
CY7C166A
:::Y7C167A
:::Y7C168A
:::Y7C169A
::Y7C170A
CY7Cl71A
Description
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
256Kx4StaticRAM .......................................................... 2-9
1Mx1StaticRAM ........................................................... 2-17
128Kx 8 Static RAM ......................................................... 2-24
256Kx 4 Static R/W RAM ..................................................... 2-32
2Kx8StaticR/WRAM ....................................................... 2-38
1K x 8 Dual-Port Static RAM .................................................. 2-45
2-45
1K x 8 Dual-Port Static RAM
2-45
1Kx 8 Dual-Port Static RAM
2-45
1Kx 8 Dual-Port Static RAM
2-58
2K x 8 Dual-Port Static RAM
2-58
2Kx 8 Dual-Port Static RAM
2-58
2K x 8 Dual-Port Static RAM
2-58
2K x 8 Dual-Port Static RAM
2-71
4Kx 8 Dual-Port Static RAM
2-71
4K x 8 Dual-Port Static RAM
4K x 8 Dual-Port Static RAM with Semaphores ................................... 2-71
4K x 8 Dual-Port Static RAM with Semaphores, INT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-83
4K x 9 Dual-Port Static RAM with Semaphores, lNT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-83
8Kx 8 Dual-Port Static RAM with Semaphores, lNT, and BUSY ....... ' ............. 2-99
8Kx 9 Dual-Port Static RAM with Semaphores, INT, and BUSY ..................... 2-99
1Kx 4 Static RAM .......................................................... 2-115
1Kx4 Static RAM .......................................................... 2-115
lK x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-122
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-130
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-130
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-137
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-137
16Kx4 Static RAM Separate I/O .............................................. 2-145
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2-145
16K x 4 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-154
16K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-154
16K x 4 Static RAM ......................................................... 2-160
16K x 4 Static RAM with Output Enable ..... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-160
16K x 4 Static RAM ......................................................... 2-167
16K x 4 Static RAM with Output Enable .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-167
16Kx 1 Static RAM ......................................................... 2-175
4Kx4 R/WRAM ........................................................... 2-182
4Kx 4 R/W RAM ........................................................... 2-182
4K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-190
4K x 4 Static R/W RAM Separate I/O .......................................... 2-195
iii
~PRFSS
'
WTsCJwCONDUCTOR
Table of Contents
Page Number
Static RAMs (Random Access Memory) (continued)
Device Number
Description
CY7CI72A
CY7B173
CY7B174
CY7B173A
CY7B174A
CY7B175
CY7C178
CY7C179
CY7B180
CY7B181
CY7C182
CY7B185
CY7C185
CY7C185A
CY7C187
CY7C187A
CY7C188
CY7B191
CY7B192
CY7C191
CY7C192
CY7B194
CY7B195
CY7B196
CY7C194
CY7C195
CY7C196
CY7C197
CY7B199
CY7C199
CY7ClOOI
CY7ClO02
CY7CI006
CY7CI007
CY7CI009
CY7CI031
CY7C1032
CY7BI051
CY7BI061
CY7BI055
CY7BI065
CY7BI094
CY7BI095
CY7BI096
CY7BI099
CY7C1331
CY7C1332
CY7C1378
CY7C1379
CY7C1388
CY7C1399
4K x 4 Static RJW RAM Separate I/O ..........................................
32Kx 9 Synchronous Cache RJW RAM ................... ; .....................
32K x 9 Synchronous Cache RJW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
32Kx 9 Synchronous Cache RJW RAM .........................................
32Kx 9 Synchronous Cache RJW RAM .........................................
32Kx 9 Synchronous Pentium CPU Cache RJW RAM ............................
32Kx 18 Synchronous Cache RAM ............................................
32K x 18 Synchronous Cache RAM ............................................
4Kx 18 Cache Tag ...........................................................
4Kx 18 Cache Tag ...........................................................
8K x 9 Static RJW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8Kx8 Static RAM ..........................................................
8Kx8StaticRAM ..........................................................
8K x 8 Static RAM ..........................................................
64Kx 1 Static RAM .........................................................
64Kx 1 Static RJW RAM .....................................................
32Kx9StaticRAM .........................................................
64Kx 4 Static R!W RAM with Separate I/O .....................................
64K x 4 Static R!W RAM with Separate I/O .....................................
64K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K x 4 Static R!W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K x 4 Static R!W RAM with Output Enable ...................................
64Kx 4 Static R!W RAM with Output Enable ...................................
64Kx4StaticRAM .........................................................
64Kx 4 Static R!W RAM with Output Enable ...................................
64K x 4 Static R!W RAM with Output Enable ...................................
256K x 1 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
32K x 8 Static RAM .................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
32Kx 8 Static RAM .........................................................
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
256K x 4 Static RAM with Separate I/O .........................................
256K x 4 Static RAM ........................................................
1M x 1 Static RAM ..........................................................
128K x 8 Static RAM ........................................................
64Kx 18 Synchronous Cache RAM ............................................
64Kx 18 Synchronous Cache RAM ............................................
64Kx 18 Synchronous Pipelined Cache R!W RAM ...............................
128K x 18 Synchronous Pipelined Cache RJW RAM ..............................
32K x 36 Synchronous Pipelined Cache R!W RAM ...............................
64Kx 36 Synchronous Pipelined Cache RJW RAM ...............................
64K x 4 Static R!W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K x 4 Static RJW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64Kx 4 Static R!W RAM ................... ; .................................
32K x 8 Static R!W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K x 18 Synchronous Cache 3.3V RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64Kx 18 Synchronous Cache 3.3V RAM ........................................
32K x 18 Synchronous Cache 3.3V RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
32Kx 18 Synchronous Cache 3.3V RAM ........................................
3.3V 32K x 9 Static RAM ...........................,. . . . . . . . . . . . . . . . . . . . . . . . ..
3.3V 32K x 8 Static RAM ................... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iv
2-195
2-203
2-203
2-212
2-212
2-224
2-236
2- 236
2-248
2-248
2-268
2-273
2-278
2- 287
2-295
2-302
2-310
2-317
2- 317
2-323
2-323
2- 331
2- 331
2-331
2-339
2-339
2- 339
2-348
2-356
2-362
2-371
2-371
2-378
2-385
2- 391
2-398
2-398
2-410
2-410
2-411
2-411
2-412
2-412
2-412
2-419
2-425
2-425
2-437
2 .... 437
2-438
2-444
Table of Contents
PROMs (Programmable Read Only Memory)
Page Number
Introduction to CMOS PROMs ............................................................................. 3-1
Device Number
Description
CY7C225
512 x 8 Registered PROM ...................................................... 3-3
CY7C225A
512 x 8 Registered PROM ..................................................... 3-10
CY7C235
1K x 8 Registered PROM ..................................................... 3 -17
CY7C235A
1Kx 8 Registered PROM ..................................................... 3-24
CY7C245
2K x 8 Reprogrammable Registered PROM ............................... . . . . . .. 3 - 31
CY7C245A
2K x 8 Reprogrammable Registered PROM ...................................... 3 - 32
CY7C251
16K x 8 Power-Switched and Reprogrammable PROM ...................... . . . . . .. 3-40
CY7C254
16Kx 8 Reprogrammable PROM ............................................... 3-40
CY7C256
32K x 8 Power-Switched and Reprogrammable PROM ............................. 3-47
2Kx 16 Reprogrammable State Machine PROM .................................. 3-52
CY7C258
CY7C259
2Kx 16 Reprogrammable State Machine PROM .................................. 3-52
CY7C261
8K x 8 Power-Switched and Reprogrammable PROM .... . . . . . . . . . . . . . . . . . . . . . . . . .. 3-64
CY7C263
8Kx 8 Reprogrammable PROM .............................................. ,. 3-64
CY7C264
8Kx 8 Reprogrammable PROM ................................................ 3-64
CY7C265
8Kx 8 Registered PROM ..................................................... 3-74
CY7C266
8Kx 8 Power-Switched and Reprogrammable PROM .............................. 3-82
CY7C269
8K x 8 Registered Diagnostic PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-89
CY7C270
16Kx 16 Reprogrammable Processor-Intelligent PROM .......................... 3-100
CY7C271
32Kx8 Power Switched and Reprogrammable PROM ......................... '" 3-111
CY7C274
32K x 8 Reprogrammable PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -111
CY7C276
16Kx 16 Reprogrammable PROM ............................................. 3-120
CY7C277
32K x 8 Reprogrammable Registered PROM .................................... 3-126
CY7C279
32K x 8 Reprogrammable Registered PROM .................................... 3-133
CY7C281
1Kx 8 PROM .............................................................. 3-140
CY7C282
1Kx8PROM .............................................................. 3-140
CY7C281A
1Kx 8 PROM .............................................................. 3-146
CY7C282A
1K x 8 PROM .............................................................. 3-146
CY7C285
64K x 8 Reprogrammable Fast Column Access PROM ............................ 3 -152
CY7C286
64Kx 8 Reprogrammable, AsynchronouslRegistered PROM ...................... , 3-157
CY7C287
64K x 8 Reprogrammable, AsynchronouslRegistered PROM . . . . . . . . . . . . . . . . . . . . . .. 3 -157
CY7C291
2Kx 8 Reprogrammable PROM ............................................... 3-165
CY7C292
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -165
CY7C291A
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-166
CY7C292A
2K x 8 Reprogrammable PROM .............................................. , 3 -166
CY7C293A
2K x 8 Reprogrammable PROM .............................................. , 3-166
PROM Programming Information ......................................................................... 3-175
PLDs (Programmable Logic Devices)
Introduction to Cypress PLDs
4-1
Device Number
Description
CY7C258
CY7C259
PLDC18G8
PALC20 Series
PAL20 Series
PLDC20G10
PLDC20G10B
PLDC20GlOC
2Kx 16 Reprogrammable State Machine PROM ................................... 4-6
2Kx 16 Reprogrammable State Machine PROM ................................ '" 4-6
CMOS Generic 20-Pin Programmable Logic Device ................................ 4-7
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 ........................... 4-14
4.5-ns, Industry-Standard, PLDs ............................................... , 4-18
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 4-28
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 4-28
Generic 24-Pin PAL Device .................................................... 4-36
v
Table of Contents
PLDs (Programmable Logic Devices) (continued)
Device Number
PLDC20RA10
PALC22V10
PALC22V10B
PAL22V10C
PAL22VP10C
PAL22V10CF
PAL22VP10CF
PALC22V10D
PAL22V10G
PAL22VP10G
CY7C330
CY7C331
CY7C332
CY7C335
CY7C340 EPLD Family
CY7C341
CY7C341B
CY7C342
CY7C342B
CY7C343
CY7C344
CY7C361
FLASH370 PLD Family
CY7C371
CY7C372
CY7C373
CY7C374
CY7C375
CY7C376
CY7C377
pASIC380 Family
CY7C381
CY7C382
CY7C383
CY7C384
CY7C385A
CY7C386A
PLD Programming Information
Page Number
Description
Reprogrammable Asynchronous CMOS Logic Device ............................ . 4-46
Reprogrammable CMOS PAL Device .......................................... . 4-57
Reprogrammable CMOS PAL Device .......................................... . 4-67
Universal PAL Device ....................................................... . 4-76
Universal PAL Device
4-76
Universal PAL Device ........................................................ 4-87
Universal PAL Device ........................................................ 4-87
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-97
Universal PAL Device ....................................................... 4-105
Universal PAL Device ....................................................... 4-105
CMOS Programmable Synchronous State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-114
Asynchronous Registered EPLD .............................................. 4-115
Registered Combinatorial EPLD .............................................. 4-129
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-130
Multiple Array Matrix High-Density EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-145
192-Macrocell MAX EPLD .................................................. , 4-150
192-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-150
128-Macrocell MAX EPLD ................................................... 4-166
128-Macrocell MAX EPLD .................................................. , 4-166
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-182
32-Macrocell MAX EPLD .................................................... 4-194
Ultra High Speed State Machine EPLD ........................................ 4-204
High-DensityFlashPLDs .................................................... 4-217
32-Macrocell Flash PLD ..................................................... 4-224
64-Macrocell Flash PLD ..................................................... 4-232
64-Macrocell Flash PLD ..................................................... 4-240
128-Macrocell Flash PLD .................................................... 4-248
4-256
128-Macrocell Flash PLD
4-265
256-Macrocell Flash PLD
256-Macrocell Flash PLD .................................................... 4-266
Very High Speed CMOS FPGAs .............................................. 4-267
Very High Speed 1K (3K) Gate CMOS FPGA .................................. , 4-274
Very High Speed 1K (3K) Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-274
Very High Speed 2K (6K) Gate CMOS FPGA .................................. , 4-281
Very High Speed 2K (6K) Gate CMOS FPGA . .. .. . . .. .. .. . . .. . . .. . .. .. . .. . . .... 4-281
Very High Speed 4K (12K) Gate CMOS FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-288
Very High Speed 4K (12K) Gate CMOS FPGA .................................. 4-288
........................................................................... 4-289
FIFOs
Device Number
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C424
CY7C425
Description
64 x 4 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 5 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 4 Cascadable FIFO with Output Enable ...................................... 5-1
64 x 5 Cascadable FIFO with Output Enable ...................................... 5-1
64 x 8 Cascadable FIFO ..................................................... " 5 -12
64 x 9 Cascadable FIFO ................... '" ......... , ....................... 5-12
512 x 9 Cascadable FIFO ..................................................... 5-26
512 x 9 Cascadable FIFO ..................................................... 5-26
5-26
1K x 9 Cascadable FIFO
5-26
1K x 9 Cascadable FIFO
vi
tr.:?:
Table of Contents
CiPRFSS
~, SEMICONDUCTOR
FIFOs (continued)
Device Number
CY7C428
CY7C429
CY7C421A
CY7C425A
CY7C429A
CY7C433A
CY7C432
CY7C433
CY7C439
CY7C441
CY7C443
CY7C445
CY7C446
CY7C447
CY7C455
CY7C456
CY7C457
CY7C451
CY7C453
CY7C460
CY7C462
CY7C464
CY7C470
CY7C472
CY7C474
Page Number
Description
2K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
2K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
512 x 9 High-Speed Cascadable FIFO ........................................... 5-44
1K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-44
2K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 53
4Kx 9 High-Speed Cascadable FIFO ............................................ 5-53
4Kx 9 Cascadable FIFO ...................................................... 5-62
4Kx 9 Cascadable FIFO ...................................................... 5-62
2K x 9 Bidirectional FIFO ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -76
512 x 9 Clocked FIFO ........................................................ 5-89
2K x 9 Oocked FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-89
Cascadable Clocked 512 x 18 FIFO wi Programniable Flags. . . . . . . . . . . . . . . . . . . . . . .. 5-105
Cascadable Clocked 1K x 18 FIFO wi Programmable Flags ........................ 5 -105
Cascadable Clocked 2Kx 18 FIFO wi Programmable Flags ........................ 5-105
Cascadable Clocked 512 x 18 FIFO wi Programmable Flags .. . . . . . . . . . . . . . . . . . . . . .. 5 -105
Cascadable Clocked 1K x 18 FIFO wi Programmable Flags ........................ 5 -105
Cascadable Clocked 2K x 18 FIFO wi Programmable Flags ........................ 5 -105
512 x 9 Cascadable Oocked FIFO wi Programmable Flags . . . . . . . . . . . . . . . . . . . . . . . .. 5 -127
2K x 9 Cascadable Clocked FIFO wi Programmable Flags ......................... 5 -127
8K x 9 Cascadable FIFO ..................................................... 5 -150
16K x 9 Cascadable FIFO .................................................... 5 -150
32K x 9 Cascadable FIFO .................................................... 5-150
8Kx 9 FIFO wi Programmable Flags ........................................... 5-163
16Kx 9 FIFO wi Programmable Flags .......................................... 5-163
32K x 9 FIFO wi Programmable Flags .......................................... 5 -163
Logic
Device Number
CY7C611A
CY7C915
CY7B991
CY7B992
CY7C9101
Description
32-Bit RISC Controller ........................................................ 6-1
1Kx42SmartCAM ........................................................... 6-8
Programmable Skew Clock Buffer (PSCB) ........................................ 6-11
Programmable Skew Oock Buffer (PSCB) ....................................... 6-11
CMOS 16-Bit Slice ........ . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-22
Data Communications Products
Device Number
CY7B923
CY7B933
CY9266-C
CY9266-F
Description
HOTLink TI-ansmitterlReceiver ................................................. 7-1
HOTLink TI-ansmitterlReceiver ................................................. 7-1
H01Link Evaluation Board ................................................... 7-26
H01Link Evaluation Board ................................................... 7-26
Modules
,Custom Module Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
Device Number
CYM1420
CYMl441
CYMl464
CYMI465
CYM1471
Description
128Kx 8 Static RAM Module ................................................... 8-5
256K x 8 Static RAM Module .................................................. 8-11
512K x 8 Static RAM Module .................................................. 8-16
512K x 8 Static RAM Module ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8- 22
1024Kx 8 Static RAM Module ............................................... " 8-28
vii
~~CYPRFSS
Table of Contents
~, SEMlCONDUCIOR
Modules (continued)
Device Number
CYM1481
CYM1560
CYM1622
CYM1720
CYM1730
CYM1821
CYM1828
CYM1831
CYM1832
CYM1836
CYM1838
CYM1840
CYM1841
CYM1851
CYM4208
CYM4209
CYM7232
CYM7264
CYM7485
CYM7490
CYM7491
CYM7492
Page Number
Description
2048K x 8 Static RAM Module ................................................. 8-28
1024Kx 9 Buffered Static RAM Module with Separate I/O ......................... 8-34
64Kx 16 Static RAM Module .................................................. 8-39
32K x 24 Static RAM Module .................................................. 8-44
64Kx 24 Static RAM Module .................................................. 8-49
16K x 32 Static RAM Module .................................................. 8-54
32Kx32 Static RAM Module .................................................. 8-61
64Kx 32 Static RAM Module .................................................. 8-68
64Kx 32 Static RAM Module .................................................. 8-73
128K x 32 Static RAM Module ................................................. 8-78
128K x 32 Static RAM Module ................................................. 8- 83
256K x 32 Static RAM Module ................................................. 8-88
256K x 32 Static RAM Module ................................................. 8-94
1024Kx 32 Static RAM Module ............................................... 8-100
Cascadable 64Kx 9 FIFO .................................................... 8-105
Cascadable 128K x 9 FIFO ................................................... 8-105
DRAM Accelerator Module .................................................. 8-114
DRAM Accelerator Module .................................................. 8-114
128K Write-Through Secondary Cache Module .................................. 8-194
i486 Level II Cache Module Family ............................................ 8-211
i486 Level II Cache Module Family ............................................ 8-211
i486 Level II Cache Module Family ............................................ 8-211
EeL
Device Number
CYlOE383
CY101E383
CY10E384L
CY10E422
CY100E422
CY10E470
CY100E470
CYlOE474
CY100E474
CY10E484
CY100E484
CY101E484
Description
ECL/TTL/ECL Translator and High-Speed Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
ECI./ITL/ECL Translator and High-Speed Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
ECL/TTL/ECL Translator ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9 - 8
256 x 4 ECL Static RAM ...................................................... 9-13
256 x 4 ECL Static RAM ...................................................... 9-13
4Kx 1 ECL Static RAM ....................................................... 9-20
4Kx 1 ECLStatic RAM ....................................................... 9-20
1Kx 4 ECL Static RAM ....................................................... 9-25
1K x 4 ECL Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-25
4Kx 4 ECL Static RAM ....................................................... 9-32
4Kx 4 ECL Static RAM ....................................................... 9-32
4K x 4 ECL Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-32
Bus Interface Products
Device Number
VIC64
VIC068A
VAC068A
CY7C964
Description
VMEbus Interface Controller with D64 Functionality ... . . . . . . . . . . . . . . . . . . . . . . . . . ..
VMEbus Interface Controller ..................................................
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus Interface Logic Circuit ...................................................
10-1
10-6
10-14
10-20
Military Information
Military Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1
Military Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2
Military Ordering Information ............................................................................. 11-7
viii
~~
Table of Contents
~...\rCYPRESS
_ , SEMICONDUCTOR
Design and Programming Tools
Device Number
CY3120
CY3130
CY3200
CY3210
CY3220
CY3300
Page Number
Description
Wa1p2 VHDL Compiler for PLDs .............................................. 12-1
Wa1p3 VHDL Development System for PLDs and FPGAs .......................... 12-6
PLDS-MAX+PLUS Design System ............................................. 12-7
PLS- EDIF Bidirectional Netlist Interface ...................................... 12-12
MAX+PLUS II Design System ................................................ 12-19
QuickPro II ............................................................... , 12-24
Quality and Reliability
Quality, Reliability, and Process Flows ...................................................................... 13-1
Tape and Reel Specifications ............................................................................. , 13 -16
Packages
Thermal Management and Component Reliability ............................................................ 14-1
Package Diagrams ...................................................................................... 14 -11
Module Package Diagrams ............................................................................... 14-66
Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors
ix
~
~~~~uaoR,~~~~~~~~~~~~~~u~flB~e~r~ic~l)~e~v~I~·c~e~I~n~d~e~x==
Page Number
Device Number
Description
10E383
lOE384L
lOE422
10E470
10E474
10E484
100E422
100E470
100E474
100E484
101E383
101E484
3120
3130
3200
3210
3220
3300
7B134
7B135
7B138
7B139
7B144
7B145
7B161
7B162
7B164
7B166
7B173
7B173A
7B174
7B174A
7B175
7B180
7B181
7B185
7B191
7B192
7B194
7B195
7B196
7B199
7B923
7B933
7B991
7B992
ECLnTL/ECL Translator and High-Speed Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
ECLmL/ECLTranslator ...................................................... 9-8
256 x 4ECL Static RAM ...................................................... 9-13
4K x 1 ECL Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9;-20
1K x 4 ECL Static RAM ..................................................... " 9 - 25
4K x 4 ECL Static RAM ..................................................... " 9-32
256 x 4 ECL Static RAM ...................................................... 9 -13
4Kx 1 ECL Static RAM .. " ................................................. " 9-20
1K x 4 ECL Static RAM ..................................................... " 9-25
4Kx4 ECL Static RAM ................................................ ; ...... 9-32
ECLnTL/ECL Translator and High-Speed Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
4K x 4 ECL Static RAM ....................................................... 9-32
Wmp2 VHDL Compiler for PLDs .............................................. 12-1
Wmp3 VHDL Development System for PLDs and FPGAs .......................... 12-6
PLDS-MAX+PLUS Design System ............................................. 12-7
PLS-EDIF Bidirectional Netlist Interface ...................................... 12-12
MAX+PLUS II Design System ................................................ 12-19
QuickPro II ............ '" ...................... " ........ , ................ 12-24
4K x 8 Dual-Port Static RAM .................................................. 2-71
4Kx 8 Dual-Port Static RAM .................................................. 2-71
4Kx 8 Dual-Port Static RAM with Semaphores, INT, and BUSY. '" ................. 2-83
4K x 9 Dual-Port Static RAM with Semaphores, INT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-83
8K x 8 Dual-Port Static RAM with Semaphores, INT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-99
8K x 9 Dual-Port Static RAM with Semaphores, INT, and BUSY ................... " 2-99
16K x 4 Static RAM Separate I/O . .. . .. . . .. .. .. . .. . . . .. .. . . . .. . . .. . .. .. .. . . . ... 2-130
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-130
16K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-154
16K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-154
32Kx 9 Synchronous Cache R/W RAM ......................................... 2-203
32K x 9 Synchronous Cache R!W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-212
32K x 9 Synchronous Cache R!W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-203
32K x 9 Synchronous Cache R!W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-212
32Kx 9 Synchronous Pentium CPU Cache R/W RAM ............................ 2-224
4Kx 18 Cache Tag ... , ................. " ............. " ., .................. , 2-248
4Kx 18 Cache Tag ........................................................... 2-248
8K x 8 Static RAM .......................................................... 2-273
64K x 4 Static R!W RAM with Separate I/O ..................................... 2-317
64Kx 4 Static R!W RAM with Separate I/O ..................................... 2-317
64Kx4 Static R/W RAM ..................................................... 2-331
64K x 4 Static R!W RAM with Output Enable ................................... 2-331
64Kx4 Static R/W RAM with Output Enable ................................... 2-331
32Kx 8 Static RAM ......................................................... 2-356
HOTLink TransmitterlReceiver ................................................. 7-1
HOTLink TransmitterlReceiver ................................................. 7-1
Programmable Skew Clock Buffer (PSCB) ....................................... 6-11
Programmable Skew Clock Buffer (PSCB) ....................................... 6-11
x
Numeric Device Index
Page Number
Device Number
Description
7B1051
7B1055
7B1061
7B1065
7B1094
7B1095
7B1096
7B1099
7B1342
7C101A
7C102A
7C106A
7C107A
7C109A
7C123
7C128A
7C130
7C131
7C132
7C136
7C140
7C141
7C142
7C146
7C148
7C149
7C150
7C161
7C161A
7C162
7C162A
7C164
7C164A
7C166
7C166A
7C167A
7C168A
7C169A
7C170A
7C171A
7C172A
7C178
7C179
7C182
7C185
7C185A
64K x 18 Synchronous Pipelined Cache RIW RAM
2-410
2-411
32K x 36 Synchronous Pipelined Cache R/W RAM
128K x 18 Synchronous Pipelined Cache RIW RAM .............................. 2-410
64K x 36 Synchronous Pipelined Cache RIW RAM ............................... 2-411
64K x 4 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-412
64K x 4 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-412
64K x 4 Static R/W RAM ................................................... " 2-412
32K x 8 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-419
4Kx 8 Dual-Port Static RAM with Semaphores ................................... 2-71
256K x 4 Static RAM with Separate I/O .......................................... , 2-1
256K x 4 Static RAM with Separate I/O .......................................... , 2-1
256Kx 4 Static RAM .......................................................... 2-9
1M x 1 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17
128Kx 8 Static RAM ......................................................... 2-24
256K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-32
2Kx 8 Static RIW RAM ....................................................... 2-38
1K x 8 Dual-Port Static RAM
2-45
2-45
1K x 8 Dual-Port Static RAM
2K x 8 Dual-Port Static RAM
2-58
2Kx 8 Dual-Port Static RAM
2-58
1Kx 8 Dual-Port Static RAM
2-45
2-45
1K x 8 Dual-Port Static RAM
2-58
2K x 8 Dual-Port Static RAM
2Kx 8 Dual-Port Static RAM
2-58
1Kx 4 Static RAM .......................................................... 2-115
1Kx4StaticRAM .......................................................... 2-115
1K x 4 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-122
16K x 4 Static RAM Separate I/O ............................................ " 2-137
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 2-145
16K x 4 Static RAM Separate I/O ............................................ " 2-137
16Kx 4 Static RAM Separate I/O .............................................. 2-145
16K x 4 Static RAM ......................................................... 2-160
16K x 4 Static RAM ......................................................... 2-167
16K x 4 Static RAM with Output Enable ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-160
16K x 4 Static RAM with Output Enable .. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. .. 2-167
16Kx 1 Static RAM ......................................................... 2-175
4Kx4 R/W RAM ........................................................... 2-182
4Kx4 RlWRAM ........................................................... 2-182
4K x 4 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-190
4Kx 4 Static R/W RAM Separate I/O .......................................... 2-195
4K x 4 Static RIW RAM Separate I/O .......................................... 2-195
32Kx 18 Synchronous Cache RAM ............................................ 2-236
32Kx 18 Synchronous Cache RAM ............................................ 2-236
8K x 9 Static RIW RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2- 268
8K x 8 Static RAM .......................................................... 2- 278
8K x 8 Static RAM .......................................................... 2-287
xi
~PRFSS
Numeric Device Index
.nEMICONDUCTOR
Page Number
Device Number
Description
7C187
7C187A
7C188
7C191
7C192
7C194
7C195
7C196
7C197
7C199
7C225
7C225A
7C235
7C235A
7C245
7C245A
7C251
7C254
7C256
7C258
7C259
7C261
7C263
7C264
7C265
7C266
7C269
7C270
7C271
7C274
7C276
7C277
7C279
7C281
7C281A
7C282
7C282A
7C285
7C286
7C287
7C291
7C291A
7C292
7C292A
7C293A
64Kx 1 Static RAM' ......................................................... 2-295
64Kx 1 Static R/W RAM ..................................................... 2-302
32Kx 9 Static RAM ......................................................... 2-310
64Kx 4 Static RAM with Separate I/O ................................. '" ...... 2-323
64K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-323
64Kx 4 Static RAM ......................................................... 2-339
64K x 4 Static R/W RAM with Output Enable ................................... 2-339
64K x 4 Static R/W RAM with Output Enable .................................... 2-339
256K x 1 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2- 348
32Kx 8 Static RAM ......................................................... 2-362
512 x 8 Registered PROM ...................................................... 3-3
512 x 8 Registered PROM ................. , ................. , . " ..... " ..... " 3-10
1Kx8 Registered PROM ..................................................... 3-17
1Kx 8 Registered PROM ..................................................... 3-24
2Kx 8 Reprogrammable Registered PROM ...................................... 3-31
2Kx 8 Reprogrammable Registered PROM ...................................... 3-32
16K x 8 Power-Switched and Reprogrammable PROM ........................... " 3-40
16Kx 8 Reprogrammable PROM ............................................... 3-40
32Kx 8 Power-Switched and Reprogrammable PROM ............................. 3-47
2Kx 16 Reprogrammable State Machine PROM .............................. 3-52,4-6
2Kx 16 Reprogrammable State Machine PROM .............................. 3-52,4-6
8Kx 8 Power-Switched and Reprogrammable PROM ............................ " 3-64
8K x 8 Reprogrammable PROM .............................................. " 3-64
8Kx 8 Reprogrammable PROM ................................................ 3-64
8Kx 8 Registered PROM ..................................................... 3-74
8Kx 8 Power-Switched and Reprogrammable PROM .............................. 3-82
8Kx 8 Registered Diagnostic PROM ............................................ 3-89
16Kx 16 Reprogrammable Processor-Intelligent PROM .......................... 3-100
32Kx 8 Power Switched and Reprogrammable PROM ............................ 3-111
32K x 8 Reprogrammable PROM ............................................. , 3-111
16K x 16 Reprogrammable PROM ............................................ , 3-120
32K x 8 Reprogrammable Registered PROM .................................... 3-126
32Kx 8 Reprogrammable Registered PROM ....•............................... 3-133
1Kx 8 PROM .............................................................. 3-140
1Kx 8 PROM .. , .............. '" ................ " ................ '" ..... 3-146
1Kx8PROM .............................................................. 3-140
1Kx8PROM .............................................................. 3-146
64K x 8 Reprogrammable Fast Column Access PROM ....•........................ 3-152
64K x 8 Reprogrammable, Asynchronous/Registered PROM. . . . . . . . . . . . . . . . . . . . . .. 3-157
64K x 8 Reprogrammable, Asynchronous/Registered PROM. . . . . . . . . . . . . . . . . . . . . .. 3-157
2Kx 8 Reprogrammable PROM ............................................... 3-165
2K x 8 Reprogrammable PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -166
2Kx 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-165
2Kx 8 Reprogrammable PROM ............................................... 3-166
2K x 8 Reprogrammable PROM. . . . . . . . . . . . .. . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 3 -166
xii
,§7!==
~
Numeric Device Index
SEMICONDUCTOR
Device Number
Description
7C330
7C331
7C332
7C335
7C340 EPLD Family
7C341
7C341B
7C342
7C342B
7C343
7C344
7C361
7C371
7C372
7C373
7C374
7C375
7C376
7C377
7C381
7C382
7C383
7C384
7C385A
7C386A
7C401
7C402
7C403
7C404
7C408A
7C409A
7C420
7C421
7C421A
7C424
7C425
7C425A
7C428
7C429
7C429A
7C432
7C433
7C433A
7C439
7C441
CMOS Programmable Synchronous State Machine ............................... 4-114
Asynchronous Registered EPLD .............................................. 4-115
Registered Combinatorial EPLD ................ ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-129
Universal Synchronous EPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-130
Multiple Array Matrix High-Density EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-145
192-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-150
192-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-150
128-Macrocell MAX EPLD ... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-166
128-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-166
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-182
32-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-194
Ultra High Speed State Machine EPW ........................................ 4- 204
32-Macrocell Flash PLD ..................................................... 4-224
64-Macrocell Flash PLD ..................................................... 4- 232
64-Macrocell Flash PLD ..................................................... 4- 240
128-Macrocell Flash PLD .................................................... 4- 248
128-Macrocell Flash PLD
4-256
256-Macrocell Flash PLD
4-265
256-Macrocell Flash PLD .................................................... 4- 266
Very High Speed lK(3K) Gate CMOS FPGA ................................... 4-274
Very High Speed lK (3K) Gate CMOS FPGA ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-274
Very High Speed 2K (6K) Gate CMOS FPGA ......... . . . . . . . . . . . . . . . . . . . . . . . . .. 4-281
Very High Speed 2K (6K) Gate CMOS FPGA ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4- 281
Very High Speed 4K (12K) Gate CMOS FPGA ......................... . . . . . . . .. 4- 288
Very High Speed 4K(12K) Gate CMOS FPGA .................................. 4-288
64 x 4 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 5 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 4 Cascadable FIFO with Output Enable ...................................... 5-1
64 x 5 Cascadable FIFO with Output Enable ...................................... 5-1
64 x 8 Cascadable FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-12
64 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
512 x 9 Cascadable FIFO ..................................................... 5 - 26
512x 9 Cascadable FIFO ..................................................... 5-26
512 x 9 High-Speed Cascadable FIFO ........................................... 5-44
lKx 9 Cascadable FIFO ...................................................... 5-26
lK x 9 Cascadable FIFO ...................................................... 5 - 26
lKx 9 High-Speed Cascadable FIFO ............................................ 5-44
2K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
2K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 26
2K x 9 High-Speed Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 - 53
4Kx9 Cascadable FIFO ...................................................... 5-62
4Kx 9 Cascadable FIFO ...................................................... 5-62
4Kx 9 High-Speed Cascadable FIFO ............................................ 5-53
2K x 9 Bidirectional FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -76
512 x 9 Cocked FIFO ........................................................ 5-89
Page Number
xiii
~PR£SS
_rs~CONDUcrOR
Numeric Device Index
Page Number
Device Number
Description
7C443
7C445
7C446
7C447
7C451
7C453
7C455
7C456
7C457
7C460
7C462
7C464
7C470
7C472
7C474
7C611A
7C915
7C964
7ClO01
7C1002
7C1006
7C1007
7C1009
7C1031
7C1032
7C1331
7C1332
7C1378
7C1379
7C1388
7C1399
7C9101
9266-C
9266-F
FLASH370 PLD Family
M1420
M1441
M1464
M1465
M1471
M1481
M1560
M1622
Ml720
M1730
M1821
2K x 9 Clocked FIFO ......................................................... 5 - 89
Cascadable Clocked 512 x 18 FIFO wi Programmable Flags . . . . . . . . . . . . . . . . . . . . . . .. 5 -105
Cascadable Clocked 1K x 18 FIFO wi Programmable Flags ........................ 5 -105
Cascadable Clocked 2K x 18 FIFO wi Programmable Flags ........................ 5 -105
512 x 9 Cascadable Clocked FIFO wi Programmable Flags . . . . . . . . . . . . . . . . . . . . . . . .. 5 -127
2K x 9 Cascadable Clocked FIFO wi Programmable Flags ......................... 5 -127
Cascadable Clocked 512 x 18 FIFO wi Programmable Flags . . . . . . . . . . . . . . . . . . . . . . .. 5 -105
Cascadable Clocked 1K x 18 FIFO wi Programmable Flags ........................ 5 -105
Cascadable Clocked 2K x 18 FIFO wi Programmable Flags ........................ 5 -105
8K x 9 Cascadable FIFO ..................................................... 5 -150
16K x 9 Cascadable FIFO .................................................... 5 -150
32K x 9 Cascadable FIFO .................................................... 5 -150
8K x 9 FIFO wi Programmable Flags ........................................... 5-163
16K x 9 FIFO wi Programmable Flags .......................................... 5 -163
32K x 9 FIFO wi Programmable Flags .......................................... 5 -163
32-Bit RISC Controller ......................................... ... . . . . . . . . . . . .. 6-1
1Kx42SmartCAM ........................................................... 6-8
Bus Interface Logic Circuit ................................................... 10-20
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-371
256K x 4 Static RAM with Separate 1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-371
256Kx 4 Static RAM ........................................................ 2-378
1M x 1 Static RAM .......................................................... 2-385
128Kx 8 Static RAM ........................................................ 2-391
64Kx 18 Synchronous Cache RAM ............................................ 2-398
64Kx 18 Synchronous Cache RAM ............................................ 2-398
64Kx 18 Synchronous Cache 3.3V RAM ........................................ 2-425
64K x 18 Synchronous Cache 3.3V RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-425
32K x 18 Synchronous Cache 3.3V RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-437
32K x 18 Synchronous Cache 3.3V RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-437
3.3V 32K x 9 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-438
3.3V 32K x 8 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-444
CMOS 16-Bit Slice .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-22
HOTLink Evaluation Board ................................................... 7-26
HOTLink Evaluation Board ................................................... 7-26
High-Density Flash PLDs .................................................... 4-217
128Kx 8 Static RAM Module ................................................... 8-5
256K x 8 Static RAM Module .................................................. 8-11
512K x 8 Static RAM Module ........................................ . . . . . . . . .. 8-16
512Kx 8 Static RAM Module .................................................. 8-22
1024K x 8 Static RAM Module ................... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-28
2048K x 8 Static RAM Module ................................................. 8-28
1024K x 9 Buffered Static RAM Module with Separate 1/0 ......................... 8-34
64Kx 16 Static RAM Module .................................................. 8-39
32K x 24 Static RAM Module .................................................. 8-44
64K x 24 Static RAM Module ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-49
16Kx 32 Static RAM Module .................................................. 8-54
xiv
·
~PRFSS
_?
Numeric Device Index
SEMICONDUCTOR
Page Number
Device Number
Description
M1828
M1831
M1832
M1836
M1838
M1840
M1841
M1851
M4208
M4209
M7232
M7264
M7485
M7490
M7491
M7492
PAL20 Series
PALC20 Series
PAL22VI0C
PAL22VP10C
PAL22VlOCF
PAL22VPlOCF
PAL22VlOG
PAL22VPlOG
PALC22VlO
PALC22VlOB
PALC22VlOD
pASIC380 Family
PLDC18G8
PLDC20GlO
PLDC20GlOB
PLDC20G10C
PLDC20RAlO
VAC068A
VIC64
VIC068A
32K x 32 Static RAM Module .................................................. 8-61
64K x 32 Static RAM Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-68
64K x 32 Static RAM Module .................................................. 8-73
128K x 32 Static RAM Module ................................................. 8-78
128Kx 32 Static RAM Module ................................................. 8-83
256K x 32 Static RAM Module ................................................. 8-88
256K x 32 Static RAM Module ................................................. 8-94
1024K x 32 Static RAM Module ............................................... 8-100
Cascadable 64Kx 9 FIFO .................................................... 8-105
Cascadable 128K x 9 FIFO ................................................... 8 -105
DRAM Accelerator Module .................................................. 8-114
DRAM Accelerator Module .................................................. 8 -114
128K Write-Through Secondary Cache Module .................................. 8-194
i486 Level II Cache Module Family ......... , ................ , ................ , 8-211
i486 Level II Cache Module Family ............................................ 8-211
i486 Level II Cache Module Family ............................................ 8-211
4.5-ns, Industry-Standard, PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-18
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 ........................... 4-14
Universal PAL Device
4-76
Universal PAL Device
4-76
Universal PAL Device
4-87
4-87
Universal PAL Device
Universal PAL Device
4-105
Universal PAL Device ....................................................... 4-105
Reprogrammable CMOS PAL Device ........................................... 4-57
Reprogrammable CMOS PAL Device ........................................... 4-67
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-97
Very High Speed CMOS FPGAs .............................................. 4-267
CMOS Generic 20-Pin Programmable Logic Device ................................ 4-7
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 4-28
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 4-28
Generic 24-Pin PAL Device ................ , ................ , .................. 4-36
Reprogrammable Asynchronous CMOS Logic Device ............................. 4-46
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-14
VMEbus Interface Controller with D64 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1
VMEbus Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6
xv
INFO
'i
SRAMs
Ij
PROMs
PlDs
•
I'
FIFOs
"
lOGIC
II
DATACOM
MODULES
.:1
ECl
Ii
BUS
,Ie,
MiliTARY
'ii
TOOLS
It)
QUALITY
Ii'
PACKAGES
'"
~PRESS
_rs~CONDUcrOR
General Product Information
Section Contents
Page Number
Cypress Semiconductor Background and Technology ........................................................... 1-1
Ordering Information ...................................................................................... 1-4
Datasheets Available Upon Request ......................................................................... 1-6
Cypress Semiconductor Bulletin Board System ................................................................ 1-8
Application Notes Listing .................................................................................. 1-9
Product Selector Guide ......................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-11
Product Line Cross Reference ............................................................................. 1-19
~aPRRSS
Background
~, SEMICONDUCTOR
II
Cypress Semiconductor Background
I
sign entry synthesis and simulation tool for PLDs and state machine PROMs. Wafp2 uses the IEEE-standard (1076) VHDL
design language, which is rapidly emerging as the standard language of choice for behavioral design description. Use of the
VHDL language allows users the freedom to also use tools from
other vendors for design simulation and synthesis. Cypress is the
only programmable logic vendor offering VHDL-based design
tools.
Logic products include circuits such as 4-bit and 16-bit slices, 16
x 16 multipliers and 16-bit microprogrammable ALUs, a family
of 1K/2K x 8 and 4K/8K x 8 dual-port SRAMs, as well as a family
of FlFOs that range from 64 x 4 to 32K x 9. Cypress also offers
application-specific FlFOs such as the 2Kx 9 bidirectional FIFO
and the 512/2K x 9 clocked FIFO. FlFOs provide the interface
between digital information paths of widely varying speeds. This
allows the information source to operate at its own intrinsic
speed, while the results may be processed or distributed at a
speed commensurate with need.
Cypress's Datacom group has developed a family of 300-MHz
point-to-point transmitter/receivers. HOTLink@J is compliant
with the IBM ESCON@) and Fibre Channel computer network
standards, and will also have applications in military, graphics,
and instrumentation systems. The Datacom group is also responsible for the Programmable Skew Clock Buffer, which allows designers to compensate for trace delays and load capacitance in
high performance systems.
As a result of the acquisition of VTC's manufacturing facility in
Minnesota, Cypress has created a VME Bus Interface Products
group. Cypress will continue to manufacture VTC's VIC and
VAC VME devices on the 0.8-micron CMOS process.
Until 1988, all Cypress products were TTL I/O-compatible. In
1989, Cypress introduced ECL products having access times
(propagation delays) of less than 3.5 ns in either of the popular
I/O configurations, lOOK or lOK/lOKH. ECL RAMs include 256
x 4, 1K x 4, and 4K x 4 families with balanced read/write cycles.
The ECL PLDs are combinatorial 16P8 and 16P4 devices that
can be programmed on QuickPro and other commercially available programming tools. Both the RAMs and Pills are offered
in low-power versions, reducing operating power by 30 percent
while achieving 5-ns access times (RAM) and 4-ns tpD (PLD).
The module family consists of both standard and custom modules incorporating circuits from the other six product families.
This capability provides a fast, low-risk solution for designs requiring the ultimate in system performance and density. SRAM
and FIFO module configurations are available depending on
height and board real estate constraints. Modules include SingleIn-Line, Dual-In-Line, Dual Single-In-line, Vertical Dual-InLine, Quad-In-Line, and (Staggered) Zig-Zag-In-Line packages.
Situated in California's Silicon Valley (San Jose), Round Rock
(Austin), Thxas, and Bloomington, Minnesota, Cypress houses
R&D, design, wafer fabrication, and administration. The facilities are designed to the most demanding technical and environmental specifications in the industry. At the Texas and Minnesota facilities, the entire wafer fabrication area is specified to be a
Class 1 environment. This means that the ambient air has less
than 1 particle of greater than 0.2 microns in diameter per cubic
foot of air. Other environmental considerations are carefully insured: temperature is controlled to a ±0.1 degree Fahrenheit
Cypress Semiconductor was founded in April 1983 with the
stated goal of serving the high-performance semiconductor market. This market is served by producing the highest-performance
integrated circuits using state-of-the-art processes and circuit design. Cypress is a complete semiconductor manufacturer, performing its own process development, circuit design, wafer fabrication, assembly, and test. The company went public in May
1986 and was listed on the New York Stock Exchange in October
1988.
The initial semiconductor process, a CMOS process employing
1.2-micron geometries, was introduced in March 1984. This process is used in the manufacturing of Static RAMs and Logic circuits. In the third quarter of 1984, a 1.2-micron CMOS EPROM
process was introduced for the production of programmable
products. At the time of introduction, these processes were the
most advanced production processes in the industry. Following
the 1.2-micron processes, a 0.8-micron CMOS SRAM process
was implemented in the first quarter of 1986, and a 0.8-micron
EPROM process in the third quarter of 1987.
In keeping with the strategy of serving the high-performance
markets with state-of-the-art integrated circuits, Cypress introduced two new processes in 1989. These were a bipolar submicron process, targeted for ECL circuits, and a BiCMOS process
to be used for most types of TTL and ECL circuits.
The circuit design technology used by Cypress is also state of the
art. This design technology, along with advanced process technology, allows Cypress to introduce the fastest, highest-performance circuits in the industry. Cypress's products fall into six
families: high-speed Static RAMs, PROMS, Programmable
Logic Devices, Logic, ECL SRAMs and PLDs, and module
products. Members of the CMOS Static RAM family include
devices in densities of 64 bits to 256K, and performance from 7
ns to 35 ns. The various organizations-xl, x4, x8, and x9-provide optimal solutions for applications such as large mainframes,
high-speed controllers, communications, and graphics display.
Cypress's BiCMOS family of 64K and 256K SRAMs in x4 and x8
configurations offers speeds as fast as 6 ns. Cypress's cache
RAMs include a 4K x 18 cache tag RAM at lO-ns match, a 32K x
9 cache RAM with a 14-ns access time, and an 64K x 18 cache
RAM with a 10-ns access time.
Cypress's programmable products consist of high-speed CMOS
PROMs employing an EPROM programming element and Programmable Logic Devices (PLDs) based onCMOS EPROM,
CMOS FLASH, and BiCMOS Fuse technology. Like the highspeed Static RAM family, these products are the natural choice
to replace older devices because they provide superior performance at one half of the power consumption. PROM densities
range from 4 kilobits to 512K in byte-wide and x 16 organizations. PLD products range from 20 pins to 84 pins with performance as fast as 5-ns propagation delay and 156-MHz operational
frequency. To provide immediate support for new programmable
products, Cypress offers our QuickPro II@) programmer
(CY3300). QuickPro II is capable of programming all of Cypress's PLDs and PROMs. It uses an IBM PC's® CPU to implement the silicon programming algorithms and interfaces to the
PC via the parallel port. The use of an IBM PC as a host allows
updating of the programming software using either floppy disk
or modem, thereby providing instantaneous support of all new
devices. Cypress also offers Wafp2@) (CY3120), a powerful de-
1-1
;;:~
~
Background
SEMICONDUCTOR
tolerance; filtered air is completely exchanged more than 10
times each minute throughout the fab; and critical equipment is
situated on isolated slabs to minimize vibration.
Attention to assembly is equally critical. Cypress manufactures
100 percent of our wafers in the United States, at our front-end
fabrication sites in California (San Jose), Minnesota (Bloomington), and Texas (Round Rock). Cypress Texas, our largest fab,
and Cypress Minnesota, our newest fab, are both Class 1 facilities.
To improve our global competitiveness, we chose to move most
of our back-end assembly, test, and mark operations to a facility
in Thailand. Be assured that Cypress's total quality commitment
extends to the new site-Cypress Bangkok.
The move to Bangkok consummated an intense search by Cypress for a world-class, environmentally sophisticated facility
that we could bring on line quickly. The Cypress search team
scrutinized fifteen manufacturing facilities in five countries and
chose a site managed by Alphatec Electronics Co., Ltd., a privately owned, entrepreneurial company promoted by the Thailand Board of Investment. Cypress Bangkok occupies almost
25,000 square feet-a significant portion of the manufacturing
floor space available within the facility. The full facility at Bangkok occupies more than 85,000 square feet on a site that encompasses 25 acres-sufficient room for expansion to a number of
buildings in a campus-like setting.
Manufacturing at the site since 1990 with a charter to specialize
in IC packaging, the Alphatec facility has almost a century of
person-years experience working for U.S. semiconductor suppliers. Thoroughly modem, MIL 883-certified, and with fully developed administrative, logistic, and manufacturing systems in
place, the facility has earned an exceptional reputation for hermetic assembly and out-going quality.
Cypress San Jose maintains complete management control of
Cypress Bangkok's assembly, test, mark, and ship operations
within the facility, thus assuring complete continuity of San
Jose's back-end operations and quality.
Cypress ~as added Tape Automated Bonding (TAB) to it packa~e offenng. TAB, a surface-mount packaging technology, proVIdes the densest lead and package footprint available for fully
tested die.
As a result of the acquisition of VTC's manufacturing facility in
Minnesota, Cypress has created a VME Bus Interface Products
group. Cypress will continue to manufacture VTC's VIC and
VAC VME devices on the 0.8 micron CMOS process.
The Cypress motto has always been "only the best-the best facilities, the best equipment, the best employees ... all striving to
make the best CMOS, BiCMOS, and bipolar products.
Cypress Process Technology
In the last decade, there has been a tremendous need for highperformance semiconductor products manufactured with a balance of SPEED, RELIABILITY, and POWER. Cypress Semiconductor overcame the classically held perceptions that CMOS
was a moderate-performance technology.
Cypress initially introduced a 1.2-micron. "N" well technology
with double-layer poly and a single-layer metal. The process
employed lightly doped extensions of the heavily doped source
and drain regions for both "N" and "P" channel transistors for
significant improvement in gate delays. Further improvements in
performance, through the use of substrate bias techniques, have
added the benefit of eliminating the input and output latch-up
characteristics associated with older CMOS technologies.
Cypress pushed process development to new limits in the areas
of PROMs (Programmable Read Only Memory) and EPLDs
(Eraseable. Programmable Logic Devices). Both PROMs and
EPLDs have existed since the early 1970s in a bipolar process
that employed various fuse technologies and was the only viable
high-speed nonvolatile process available. Cypress PROMs and
EPLDs use EPROM technology, which has been in use in MOS
(Metal Oxide Silicon) since the early 1970s. EPROM technology
has traditionally emphasized density while forsaking performance. Through improved technology, Cypress produced the first
high-performance CMOS PROMs and EPLDs, replacing their
bipolar counterparts.
To m~intain our leadership position in CMOS technology, Cypress Introduced a sub-micron technology in 1987. This 0.8 micron breakthrough made Cypress's CMOS one of the most advanced production processes in the world. The drive to maintain
leadership in process technology has not stopped with the
0.8-micron devices. Cypress introduced a 0.65-micron process in
1991. A O.5-micron process is currently in the works.
Although not a requirement in the high-performance arena,
CMOS technology substantially reduces the power consumption
for any device. This improves reliability by allowing the device to
operate at a lower die temperature. Now higher levels of integration are possible without trading performance for power. For instance, devices may now be delivered in plastic packages without
any impact on reliability.
While addressing the performance issues of CMOS technology,
Cypress has not ignored the quality and reliability aspects of
technology development. Rather, the traditional failure mechanisms of electrostatic discharge (ESD) and latch-up have been
addressed and solved through process and design technology innovation.
ESD-induced failure has been a generic problem for many highperformance MOS and bipolar products. Although in its earliest
years, MOS technology experienced oxide reliability failures, this
problem has largely been eliminated through improved oxide
growth techniques and a better understanding of the ESD problem. The effort to adequately protect against ESD failures is perturbed by circuit delays associated with ESD protection circuits.
Focusing on these constraints, Cypress has developed ESD protection circuitry specific to 1.2-, 0.8-, 0.65-, and O.5-micron
CMOS process technology. Cypress products are designed to
withstand voltage and energy levels in excess of 2001 volts and
0.4 milli-joules.
Latch-up, a traditional problem with CMOS technologies, has
been eliminated through the use of substrate bias generation
techniques, the elimination of the "P" MOS pull-ups in the output drivers, the use of guardring structures and care in the physical layout of the products.
Cypress has also developed additional process innovations and
enhancements: multilayer metal interconnections, advanced
metal deposition techniques, silicides, exclusive use of plasma for
etching, and 100-percent stepper technology with the world's
most advanced equipment.
A wholly owned subsidiary of Cypress, Aspen Semiconductor,
has developed a BiCMOS technology to augment the capabilities of the Cypress CMOS processes. The new BiCMOS technology is based on the Cypress 0.8-micron CMOS process for enhanced manufacturability. Like CMOS, the process is scalable,
to take advantage of finer line lithography. Where speed is critical, Cypress BiCMOS allows increased transistor performance.
It also allows reduced power in the non-speed critical sections of
the design to optimize the speed/power balance. The BiCMOS
1-2
a:a:'~PRESS
==p=.
Background
-:
II
SEMICONDUCTOR
Cypress technologies have been carefully designed, creating
products that are "only the best" in high-speed, excellent reli~
ability, and low power.
process makes memories and logic operating up to 400 MHz
possible.
iE
IBM PC and IBM ESCON are registered trademarks of International Business Corporation.
QuickPro II, HOTLink, and Warp2 are trademarks of Cypress Semiconductor Corporation.
1-3
~PR&SS
Ordering Information
.nEMICONDUcrOR
In general, the valid ordering codes for all products (except modules and VMEbus products) follow the format below; e.g.,
CY7C128-45DMB, PALC16R8L-35PC
PAL & PLD
PREFIX DEVICE
SUFFIX
IpALC I rt6R8I I -25 P C I
16R8
L-35 P C
PALC
-25 WC
22VlO
PALC
20mo
-25 WC
PLDC
-33 P C
7C330
CY
FAMILY
PAL 20
LOW POWER PAL 20
PAL 24 VARIABLE PRODUcr TERMS
GENERIC PLD 24
PLD SYNCHRONOUS STATE MACHINE
RAM, PROM, FIFO, !lp' ECL
PREFIX
DEVICE
rcY"1
I 7C128 I I
CY
CY
CY
CY
CY
r7B185
7C245
7C404
7C9101
1OE422
100E422
B = BiCMOS
C = CMOS
SUFFIX
-45DMB I
-15V C
L-35P C
-25DMB
-30P C
FAMILY
CMOSSRAM
BiCMOSSRAM
PROM
FIFO
ftKECLSRAM
lOOK ECL SRAM
-3 K C
-3 K C
L
PROCESSING
B = MIL-STD-883C FOR MILITARY PRODUcr
= LEVEL 2 PROCESSING FOR COMMERCIAL PRODUcr
T = SURFACE-MOUNTED DEVICES TO BE TAPE AND REELED
R = LEVEL 2 PROCESSING ON TAPE AND REELED DEVICES
TEMPERATURE RANGE
C = COMMERCIALWCTO +70°C)
I = INDUSTRIAL (-40°C TO +85°C)
M = MILITARY (-55°C TO + 125°C)
PACKAGE
B = PLASTIC PIN GRID ARRAY (PPGA)
D = CERAMIC DUAL IN-LINE PACKAGE (CERDIP)IBRAZED DIP
E = TAPE AUTOMATED BONDING (TAB)
F = FLATPACK (SOLDER-SEALED FLAT PACKAGE)
G = PIN GRID ARRAY (PGA)
H = WINDOWED LEADED CHIP CARRIER
J = PLASTIC LEADED CHIP CARRIER (PLCC)
K = CERPACK (GLASS-SEALED FLAT PACKAGE)
L = LEAD LESS CHIP CARRIER (LCC)
N = PLASTIC QUAD FLATPACK (PQFP)
P = PLASTIC DUAL IN-LINE (PDIP)
Q = WINDOWED LEADLESS tHIP CARRIER (LCC)
R = WINDOWED PIN GRID ARRAY (PGA)
S = SOIC (GULL WING)
T = WINDOWED CERPACK
U = CERAMIC QUAD FLATPACK (CQFP)
V = SOIC (J LEAD)
W = WINDOWED CERAMIC DUAL IN-LINE PACKAGE (CERDIP)
X = DICE (WAFFLE PACK)
Y = CERAMIC LEADED CHIP CARRIER
SPEED (ns or MHz)
L = LOW-POWER OPTION
~ B, C = REVISION LEVEL
Cypress FSCM #65786
1-4
=n'- :~
Ordering Information
==-= CYPRESS
SEMICONDUcrOR
~,
The codes for module and VMEbus products follow the the formats below.
Modules
PREFIX
I CYM I
DEVICE
SUFFIX
~ I L HD-30 MBI
PROCESSING
B = MIL-STD-883C
= STANDARD
TEMPERATURE RANGE
C = O°CTO +70°C
I = -40°C TO +85°C
M = -55°C TO + 125°C
SPEED
CONFIGURATION
D=
F =
G=
M=
N=
S =
V=
Z =
DUAL-IN-LINE
FLAT SINGLE-IN-LINE
PIN GRID ARRAY
SINGLE-IN-LINE MEMORY MODULE (SIMM)
SIMM FOR ANGLED SOCKETS
SINGLE-IN-LINE
VERTICAL DIP
ZIGZAG-IN-LINE
TYPE
H= HERMETIC
P = PLASTIC
DATA RETENTION
L = 2.0V DATA RETENTION GUARANTEED
= 2.0V DATA RETENTION NOT GUARANTEED
VMEbus Products
PREFIX
rviC1
DEVICE SUFFIX
I 068A I I BCB I
t
PROCESSING
B = MIL-STD-883C
= STANDARD
TEMPERATURE RANGE
C = O°CTO +70°C
I = -40°C TO +85°C
M = -55°C TO +125°C
PACKAGE
B
G
N
U
= PLASTIC PIN GRID ARRAY (PPGA)
= PIN GRID ARRAY (PGA)
= PLASTIC QUAD FLATPACK (PQFP)
= CERAMIC QUAD FLATPAcK (CQFP)
A, B, C = REVISION LEVEL
Cypress FSCM #65786
1-5
II
~
~~PRFSS
~, SEMICONDUCTOR
Datasheets Available Upon Request
Datasheets listed here are not in this catalog but can be obtained from a Cypress representative.
Static RAMs (Random Access Memory)
Device Number
CY2147
CY2148/CY21lA8/CY2149/CY21lA9
CY6116
CY6116NCY6117A
CY7C122
CY7C128
CY7C147
CY7C167
CY7C168/CY7C169
CY7C170
CY7C1711CY7Cl72
CY7C183/CY7C184
CY7C186
CY7C189/CY7C190
CY7C198
CY74S189/CY27V303/CY27S03/CY27S07
CY93lA22NCY93422/CY93lA22
Description
4096 x 1 Static RIW RAM
1024 x 4 Static R/W RAM
2048 x 8 Static RIW RAM
2048 x 8 Static RIW RAM
256 x 4 Static RIW RAM Separate I/O
2048 x 8 Static RIW RAM
4096 x 1 Static RAM
16,384 x 1 Static RIW RAM
4096 x 4 Static RAM
4096 x 4 Static RIW RAM
4096 x 4 Static RIW RAM Separate I/O
2 x 4096 x 16 Cache RAM
8K x 8 Static RAM
16 x4 Static RIW RAM
32K x 8 Static RIW RAM
16 x 4 Static RIW RAM
256 x 4 Static RIW RAM
FIFOs
Device Number
CY3341
Description
64 x 4 Serial Memory FIFO
Logic
Device Number
CY2901C
CY2909/11
CY2910
CY7C510
CY7C516/7
CY7C901
CY7C909/11
CY7C91O
Description
CMOS 4-Bit Slice
CMOS Microprogram Sequencers
CMOS Microprogram Controller
16 x 16 Multiplier Accumulator
16 x 16 Multiplier
CMOS 4-Bit Slice
CMOS Microprogram Sequencers
CMOS Microprogram Controller
Modules
Device Number
CYM1240
CYM1422
CYM1423
CYM1460
CYM1461
CYM1466
CYM1540
CYM1610
CYM1611
CYM1620
CYM1621
CYM1624
CYM1641
CYM1822
Description
256K x 4 Static RAM Module
128K x 8 Static RAM Module
128K x 8 Static RAM Module
512K x 8 Static RAM Module
512K x 8 Static RAM Module
512K x 8 Static RAM Module
256K x 9 Buffered Static RAM Module with Separate I/O
16Kx 16 Static RAM Module
16Kx 16 Static RAM Module
64Kx 16 Static RAM Module
64K x 16 Static RAM Module
64Kx 16 Static RAM Module
256Kx 16 Static RAM Module
16K x 32 Static RAM Module with Separate I/O
1-6
·
·~PRFSS
-iF
Datasheets Available Upon Request
SEMICONDUCTOR
II
o
Modules
(continued)
Device Number
CYM1830
CYM1841
CYM1843
CYM1910
CYM1911
CYM421O/CYM4220
CYM4241
CY7M194
CY7M199
Description
64K x 32 Static RAM Module
256K x 32 Static RAM Module
256K x 32 Static RAM Module
16K x 68 Stati~ RAM Module
16Kx 68 Static RAM Module
Cascadeable 8K x 9 FIFO
64Kx9FIFO
64K x 4 Static RAM Module
32K x 8 Static RAM Module
1-7
LL.
~
11Yl~
~
SEMICONDUcrOR
Cypress Semiconductor Bulletin Board System (BBS)
Cypress Semiconductor supports a 24-hour electronic Bulletin Board System (BBS) that allows Cypress
Applications to better serve our customers by allowing them to transfer files to and from the BBS.
The BBS is set up to serve in multiple ways. One· of its purposes is to allow customers to receive the most
recent versions of the QuickPro programming software. Another is to allow the customers to send PLD programming files that they are having trouble with to the BBS. Cypress Applications can then find the errors
in the files, correct them, and place them back on the BBS for the customer to download. The customer may
also ask questions in our open forum message area. The sysop (system operator) will forward these questions
to the appropriate applications engineer for an answer. The answers then get posted back into the forum.
The BBS also allows the customer to communicate with their local FAE electronically, and to download both
application notes and the latest versions of selected datasheets.
Communications Set-Up
The BBS is attached to a USRobotics HST Dual Standard modem capable of 14.4-Kbaud rates without compression and rates upwards of 19.2-Kbaud with compression. It is compatible with CCITT Y.32 bis, Y.32, Y.22
(2400-baud), Bell 212A (1200-baud), CCITT Y.42, and CCnT Y.42 bis. It also handles MNP levels 2, 3, 4,
and 5.
To call the BBS, set your communication package parameters as follows:
Baud Rate:
1200 baud to 19.2 Kbaud. Max. is determined by your modem.
Data Bits: 8
Parity: None (N)
Stop Bits: 1
In the U.S. the phone number for the BBS is (408) 943-2954. In Japan the BBS number is
81-423-69-8220. In Europe the BBS number is 49-810-62-2675. These numbers are for transmitting
data only.
If the line is busy, please retry at a later time. When you access the BBS, an initial screen with the following
statement will appear:
Rybbs Bulletin Board
Mter you choose the graphics format you want to use, the system will ask for your first and last name. If you
are a first-time user, you will be asked a few questions for the purposes of registration. Otherwise you will be
asked for your password, and then you will be logged onto the BBS, which is menu driven.
Downloading Application Notes and Datasheets
A complete listing of files that may be downloaded is included on the BBS. Application notes and selected
datasheets are available for downloading in two formats, PCL and Postscript. An "hp" in front of the file
name indicates it is a PCL file and can be downloaded to Hewlett-Packard LaserJets. Files without the hp
preceding them are in Postscript and can be downloaded to any Postscript printer.
If you have any problems or questions regarding the BBS, please contact Cypress Applications at (408)
943-28~1 (voice).
1-8
~
--.-====
. . JF·a.PRESS
Application Notes
SEMICONDUcrOR
Contact a Cypress representative or use the Cypress Bulletin Board System to get copies of the application notes listed here.
•
f2
~
General Information
I/O Characteristics of Cypress Products
Power Characteristics of Cypress Products
Protection and Decoupling of Cypress CMOS Circuits
System Design Considerations when Using Cypress CMOS
Circuits
Tips for High-Speed Logic Design
Modules
Multichip Family of JEDEC ZIP/SIMM Modules
Packages in High-Density Module Designs
ECL and TTL BiCMOS
A New Generation of BiCMOS High-Speed TTL SRAMs
Access Time vs. Load Capacitance for High-Speed TTL SRAMS
BiCMOS TTL & ECL SRAMs Improve High-Performance
Systems
BiCMOS TTL SRAMs Improve R3000 and R3000A Systems
Combining SRAMs Without an External Decoder
Memory and Support for Next-Generation ECL Systems
Noise Considerations in High-Speed Logic Systems
PLCC/CLCC Packaging for High-Speed Parts
Using ECL in Single +5V TTL Systems
SRAMs
Cypress RAM I/O Characteristics
Second-Level Cache and Main Memory Systems for the 80486
Understanding Dual-Port RAMS
Using Dual-Port RAMS Without Arbitration
Using Cypress SRAMs to Implement 386 Cache
Using the CY7C180/181 Cache Tag RAM
PROMs
Generating PROM Programming Files
Interfacing the CY7C289 to the AM29000
Interfacing the CY7C289 to the CY7C601
Introduction to Diagnostic PROMs
Introduction to the Processor-Intelligent PROM
Introduction to the State Machine PROM
Pinout Compatibility Considerations of SRAMs and PROMs
Using C to Design with the CY7C258/9 State Machine PROM
CMOS PAL Basics
Creating AHDL Text Design Files for MAX EPLDs
CY7C330 as a Multi-Channel Mbus Arbiter
CY7C331 Asynchronous Self-Timed VMEbus Requestor
CY7C344 as a Second-Level Cache Controller for the 80486
Design Tips for Advanced Max Users
Designing a Multiprocessor Interrupt Distribution Unit with
MAX
Designing Counters with the CY7C361 EPLD
DMA Control Using the CY7C342 MAX EPLD
Dual-Port Memory Design Using SRAMs and the CY7C361
FDDI Physical Connection Management Using the CY7C330
FIFO RAM Controller with Programmable Flags
IEEE-488 to RS-232 Converter in a CY7C361 Using Wmp
Interfacing PROMs and RAMs to DSP Using Cypress
MAX Products
Introduction to Programmable Logic
PAL Design Example: A GCR EncoderlDecoder
pASIC380 Power vs. Operating Frequency
PLD-Based Data Path For SCSI-2
State Machine Design Considerations and Methodologies
T2 Framing Circuitry
TMS320C30NME Signal Conditioner Using the CY7C361
Understanding the CY7C330 Synchronous EPLD
Understanding the CY7C361
Using ABEL to Program the Cypress 22VlO
Using ABEL to Program the CY7C330
Using ABEL 3.2 to Program the CY7C331
Using CUPL with Cypress PLDs
Using LogllC to Program the CY7C330
Using One-Hot-State Coding to Accelerate a MAX
State Machine
Using the CY7C330 in Closed-Loop Servo Control
Using the CY7C331 as a Waveform Generator
Using the CY7C344 with the PLD ToolKit
Using the CY7C361 as a High-Performance DRAM Controller
Using the CY7C361 as a VMEbus Arbiter
Using the CY7C361 as an Mbus Arbiter
Using the CY7C361 with the PLD ToolKit
VHDL Techniques for Optimal Design
Describing State Machines with Wmp2
PLDs
A Programmable Event Generator using the CY7C361
A Rotational Priority Generator Example Using the CY7C332 as
a Mealy State Machine
ABEL 4.0/4.1 and the CY7C330, CY7C331, and CY7C332
Are Your PLDs Metastable?
Bus-Oriented Maskable Interrupt Controller
1-9
~
~~PRESS
~, SEMICONDUcrOR
Application Notes
Logic
CYlOE383/101383 1tanslator
Designing with the CY7C439 BIFO
Microcoded System Performance
Systems with CMOS 16-Bit uP ALUs
Understanding Large FIFOs
Understanding Small FIFOs
Understanding Clocked FIFOs
Interfacing HOTLink to Clocked FIFOs
. Interfacing HOTLink to Wide Data FIFOs
The CY7C42X/46X Interface to HOTLink
Everything You Always Wanted to Know About RoboClock
Using CY7C991 with the 80486 Cache Module and the
40-MHz R3000
Robo Clock Test Mode
CY7C611A Design for High-Performance Embedded Control
Discrete Cache System Design for the CY7C611A Embedded
RISC Processor
Getting Started with Real-Time Embedded-System Development
Memory Protection and Address Exception Logic for the
CY7C611
Memory System Design for CY7C601 SPARC
Memory System Design for the CY7C611A
Bus Products
Interfacing the CY7C611A to the VIC64
Interfacing the VIC068 to the MC68020
Software Considerations for the VIC64
Using the CY7C361 and VIC068 to Interface a T801 Processor
to the VMEbus
Using VIC Without a Processor
VIC068 Special Features and Tips
Glossary - '91
Glossary - '93
1-10
Product Selector Guide
II
tatic RAMs
'tize
Organization
Pins
Part Number
Speed (ns)
(mA@ns)
IccflsB
Packages
Availability
16 x 4-lnverting
16 x 4-Non-Inverting
16 x 4-lnverting
16x4-lnverting
16 x 4-Non-Inverting
16x 4-lnverting Low Power
256x4
256x4
256x4
256x4
4Kx1-CSPower-Down
4Kx l-CS Power-Down
lKx 4-CS Power-Down
1Kx4-CS Power-Down
lKx4
lKx4
lKx 4-Separate I/O, Reset
lKx 8-Dual Port Master
lKx 8-DualPort Slave
lKx 8-DualPort Master
lKx 8-Dual Port Slave
2Kx 8-CS Power-Down
2Kx8-CS Power-Down
2Kx8-CSPower-Down
16Kx1-CSPower-Down
4Kx4-CSPower-Down
4Kx4
4Kx 4-0utput Enable
4Kx 4-Separate I/O
4Kx 4-Separate I/O
2Kx 8-DualPort Master
2Kx 8-Dual Port Slave
2Kx 8-Dual Port Master
2Kx 8-Dual Port Slave
4Kx 8-DuaIPort, No Arbitration
4Kx 8-Dual Port, w/Semaph
4Kx 8-Dual Port, No Arbitration
4Kx 8-DualPort, w/ Semaph, Busy, Int
4Kx9-DuaIPort,w/Semaph, Busy, Int
8Kx 8-Dual Port, w/ Semaph, Busy, Int
8Kx 9-DuaIPort, w/ Semaph, Busy, Int
8Kx8-CSPower-Down
8Kx8-CS Power-Down
8Kx 8-CS Power-Down
8Kx8-CS Power-Down
8Kx8-CS Power-Down
64Kx 1-CS Power-Down
64Kx 1-CS Power-Down
16Kx4-CSPower-Down
16Kx4-CSPower-Down
16Kx 4-OutputEnabie
16Kx 4-0utputEnable
16Kx 4-Separate I/O, Transparent
Write
16Kx 4-Separate I/O
16Kx4-SeparateI/0, Transparent
Write
16
16
16
16
16
16
22
24S
22
22
18
18
18
18
18
18
24S
48
48
52
52
24
24
32
20
20
20
22S
24S
24S
48
48
52
52
48
52
52
68
68
68
68
28S
28S
28S
28
28
22S
22S
22S
22S
24S
24S
28S
CY7C189
CY7C190
CY74S189
CY27S03A
CY27S07A
CY27LS03M
CY7C122
CY7C123
CY9122/91L22
CY93422N93L422A
CY7C147
CY2147/21L47
CY7C148
CY2148/21L48
CY7C149
CY2149/21L49
CY7C150
CY7C130
CY7C140
CY7C131
CY7C141
CY7C128A
CY6116A
CY6117A
CY7C167A
CY7C168A
CY7C169A
CY7C170A
CY7Cl71A
CY7CI72A
CY7C132
CY7C142
CY7C136
CY7C146
CY7B134
CY7B1342
CY7B135
CY7B138
CY7B139
CY7B144
CY7B145
CY7B185
CY7C185
CY7C185A
CY7C186A
CY7C186
CY7C187A
CY7C187
CY7Bl64
CY7Cl64
CY7B166
CY7C166
CY7B161
tAA = 15, 25
tAA = 15,25
tAA=35
tAA =25,35
tAA =25,35
tAA= 65
tAA = 15,25,35
tAA = 7,9,10,12,15
tAA = 25,35,45
tAA = 35,45,60
tAA = 25,35,45
tAA=35,45,55
tAA = 25,35,45
tAA = 35,45,55
tAA = 25,35,45
tAA = 35,45,55
tAA = 10, 12,15,25,35
tAA = 25,30,35,45,55
tAA = 25,30,35,45,55
tAA = 25,30,35,45,55
tAA = 25,30,35,45,55
tAA = 15,20,25,35,45,55
tAA = 20,25,35,45,55
tAA = 20,25,35,45,55
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
t.~ = 15,20,25,35,45
tAA = 25,30,35,45,55
tAA = 25,30,35,45,55
tAA = 25, 30, 35, 45, 55
tAA = 25,30,35,45,55
tAA = 20,25,35
tAA = 20,25,35
tAA = 20,25,35
tAA = 15,25,35
tAA = 15,25,35
tAA = 15,25,35
tAA = 15,25,35
tAA = 9, 10, 12, 15
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 8,10,12
tAA = 15,20,25,35,45
tAA = 8, 10, 12
tAA = 15,20,25,35,45
tAA = 8, 10, 12
55@25
55@25
90@35
90@25
90@25
38@65
60@25
120@7
120@25
80@45
80/1O@35
125/25@35
80/1O@35
120/20@35
80@35
120@35
90@12
170@25
170@25
170@25
170@25
90/20@55
80/20@55
80/20@55
50!15@45
70/15@45
70@45
90@45
90@45
90@45
170@25
170@25
170@25
170@25
240
240
240
260
260
260
260
150/50@9
120/20@15
125/40@25
125/40@25
120/20@15
80/40@25
90/40@15
140/50@8
115/40@15
140/50@8
115/40@15
140/50@8
D,P
L,P
D,P
D,P
D,P
D,
D,L,p,S
D,L,p,V
D,P
D,L,P
D,P
D,P
D,P
D,P
D,L,P
D,P
D,p,S
D,L,P
D,L,P
J,L,N
J,L,N
D,L,p,V
D,L
L
D,P,V
D,P,V
p,V
D,P,V
D,L,P,V
D,L,p,V
D,L,P
D,L,P
J,L,N
J,L,N
D,L,P
J,L
J,L
G,J,L
G,J,L
G,J,L
G,J,L
D,P,V
P,V
D,L
D,L
P
D,L
p,V
D,P,V
p,V
D,P,V
p,V
D,P,V
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
28S
28S
CY7B162
CY7C161
tAA = 8,10,12
tAA = 15,20,25,35,45
140/50@8
115/40@15
D,P,V
P,V
Now
Now
!
14
14
14
;4
;4
;4
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
6K
2K
2K
2K
2K
2K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
1-11
.r~a=roR
Static RAMs
Product Selector Guide ,
(continued)
Organization
Pins
64K
64K
16Kx4-Separate I/O
16Kx4-Separate I/O, 'ftansparent
Write
16Kx 4-Separate I/O
16Kx4-CS Power-Down
16Kx4-0utputEnable
8Kx9
4Kx IS-Cache Thg, Multiprocessing
4Kx 18-Cache Tag, Uniprocessing
8Kx 16-Addresses Latched except A12
8Kx 16-Addresses Latched
16Kx 16-SPARCCache RAM
32KxS-CS Power-Down
32KxS-CS Power-Down
32KxS-CS Power-Down
32Kx 8-CS Power-Down (3.3V)
64Kx 4-CS Power-Down
64Kx 4-CS Power Down with OE
64Kx 4-Separate I/O, Transparent
Write
64Kx 4-Separate I/O
64Kx 4-Separate I/O, 'ftansparent
Write
64Kx4-Separate I/O
64Kx4-CSPower-Down
64Kx4-CSPower-Downw/OE
64Kx4-CSPower-Downw/OE,Second
28S
28S
CY7C162
CY7C161A
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
28S
22S
24S
28S
68
68
52
52
52
28
28S
28S
28S
24S
28S
28S
CY7C162A
CY7Cl64A
CY7C166A
CY7C182
CY7B180
CY7B181
CY7C183
CY7C184
CY7C157
CY7C198
CY7C199
CY7B199
CY7C1399
CY7C194
CY7C196
CY7C191
28S
28S
64K
64K
64K
72K
72K
72K
128K
128K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
Part Number
IccflsB
Size
Speed (ns)
Packages
AvailabilitY
115/40@15
100/40@20
P,V
D,L
Now
Now
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 15,20,25,35,45
tAA = 25,35,45,55
tMATCH = 10,12,15,20
tMATCH = 10,12,15,20
tAA = 25,35,45
tAA = 25,35,45
tAA = 18,20,24,33
tAA = 25,35,45
tAA = 12,15,20,25,35,45,55
tAA = 10,12
tAA = 20,25,35
tAA = 12,15,20,25,35,45
tAA = 12,15,20,25,35,45
tAA = 12,15,20,25,35,45
100/40@20
100/40@20
100/40@20
140/35@25
340@10
340@10
220@25
220@25
250
160/35@25
170/30@25
185/30@10
60/25@20
160/30@25
160/30@25
120/30@25
D,L
D,L
D,L
p,V
J,N
J,N
J
J
J
D,L,P
D,L,p,V
D,p,V
p,V
D,L,p,V
D,L,P,V
D,P,V
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Q393
Now
Now
Now
CY7C192
CY7B191
tAA = 12,15,20,25,35,45
tAA = 10,12
120/30@25
170/30@10
D,L,p,V
D,p,V
Now
Now
28S
24S
28S
28S
CY7B192
CY7B194
CY7B195
CY7B196
tAA =
tAA =
tAA =
tAA =
170/30@10
170/30@1O
170/30@10
170/30@10
D,p,V
D,P,V
D,P,V
D,p,V
Now
Now
Now
Now
28S
24S
24S
32S
32S
52
52
52
52
32
32
28
28
32
CY7C195
CY7B197
CY7C197
CY7C188
CY7C1388
CY7C1031
CY7C1032
CY7C1331
CY7C1332
CY7C1009
CY7C109A
CY7C1006
CY7C106A
CY7CI001
tAA = 12,15,20,25,35
tAA = 10,12
tAA = 12,15,20,25,35,45
tAA = 12,15,20,25,35
tAA = 20,25,35
tAA = 10,12,14(@85pF)
tAA = 10,12, 14(@85pF)
tAA = 14,18,21 (@85pF)
tAA = 14,18,21(@85pF)
tAA = 12,15,20,25
tAA = 12,15,20,25,35
tAA = 12,15,20,25
tAA = 12,15,20, 25,35
tAA = 12,15,20,25
160/30@25
140/30@1O
105/30@25
160/40@12
60/40@20
265@10
265@10
180@14
180@14
185@12
185@12
165@12
165@12
165@12
D,L,p,V
D,p,V
D,P,V
p,V
p,V
J
J
J
J
D,L,p,V
D,L,p,V
D,p,V
D,p,V
D,p,V
Now
Now
Now
Q194
Q194
Q393
Q393
Q493
Q493
Q493
Q194
Q493
Q493
Q493
32
CY7CI01A
tAA = 12, 15,20,25,35
165@12
D,L,p,V
Q493
32
32
28
28
CY7CI002
CY7C102A
CY7C1007
CY7C107A
tAA = 12,15,20,25
tAA = 12,15,20,25,35
tAA = 12,15,20,25
tAA =12, 15,20,25,35
165@12
165@12
150@12
150@12
D,L,p,V
D,L,p,V
D,L,P,V
D,L,P, V
Q493
Q493
Q493
Q493
(mA@ns)
10,12
10,12
10,12
10,12
CS
256K
256K
256K
288K
288K
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
64Kx 4-CS Power-Down w/ OE
256Kx 1-CS Power-Down
256Kx 1-CS Power-Down
32Kx 9-CS Power-Down
32Kx9-CS Power-Down (3.3V)
64Kx IS-Burst
64Kx IS-Burst
64Kx 18-Burst (3.3V)
64Kx IS-Burst (3.3V)
128Kx S-CS Power-Down
128Kx S-CS Power-Down
256Kx 4-CS Power-Down
256Kx4-CSPower-Downw/OE
256Kx 4-Separate I/O, 'ftansparent
Write
256Kx 4-Separate I/O, 'ftansparent
Write
256Kx 4-Separate I/O
256Kx 4-Separate I/O
IMx l-CS Power-Down
1Mx1-CSPower-Down
ECLSRAMs
Size
1K
1K
1K
1K
Organization
256 x 4-lOKllO KH
256x4-lOKl10KH
256x4-100K
256 x 4-100K
Pins
24.4
24.4
24.4
24.4
Speed (ns)
Part Number
CYlOE422
CYlOE422L
CY100E422
CY100E422L
tAA =4,5
tAA =5,7
tAA =3.5,5
tAA=5,7
1-12
lEE
220
150
220
150
Packages
D,K,L
D,J,K,L
D,K,L
D,J,K,L
Availability
Now
Now
Now
Now
!
I
'
~4
CYPRESS
-=-.,
Product Selector Guide
_'jE
SEMICONDUCTOR
l,eL SRAMs (continued)
lize
'~K
~K
~K
,K
K
K
6K
6K
6K
6K
6K
6K
Organization
Part Number
Pins
4Kxl-lOK
4Kxl-100K
1024 x 4-1OK/I0 KH
1024x4-1OK/I0KH
1024 x 4-100K
1024 x 4-100K
4Kx4-10K/lOKH
4Kx4-1OK/lOKH
4Kx4-100K
4Kx4-100K
4Kx4-100K
4Kx4-100K
18,3
18.3
24.4
24.4
24.4
24.4
28.4
28.4
28.4
28.4
28.4
28.4
Speed (ns)
CYlOE470
CYlOOE470
CYlOE474
CYlOE474L
CYlOOE474
CYlOOE474L
CYlOE484
CYlOE484L
CYlOOE484
CYlOOE484L
CYlO1E484
CYlO1E484L
tAA=5,7
tAA=5,7
tAA =4,5
tAA=5,7
tAA=3,5,5
tAA=5,7
tAA =4,5
tAA=7,10
tAA=4,5
tAA=7,1O
tAA=4,5
tAA=7,1O
Packages
lEE
200
200
275
190
275
190
320
200
320
200
320
200
D
D
D,K,L
D,J,K,L
D,K,L
D,J,K,L
D,K,Y
D,J,K, V
D,K, Y,Y
D,J,K, V
D,K,Y
D,J,K, V
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
~Modules
Size
Organization
Pins
Part Number
12K
16Kx32-JEDEC
64
CYM1821
68K
M
M
M
,5M
M
M
M
M
M
M
M
M
M
M
M
M
6M
2M
32Kx24
32Kx32
64Kx16
i486 Secondary Cache
64Kx24
256Kx8-JEDEC
64Kx32
64Kx32-JEDEC
64Kx32
512Kx8-JEDEC
512Kx8-JEDEC
128Kx32
128Kx32
256Kx32
256Kx32-JEDEC
IMx8
1Mx9
2Mx8
1Mx32
56
66
40
128
56
60
60
64
60
32
32
64
66
60
64
36
44
36
72
CYMl720
CYM1828
CYM1622
CYM7485
CYM1730
CYM1441
CYM1830
CYM1831
CYM1832
CYM1464
CYM1465
CYM1836
CYM1838
CYM1840
CYM1841
CYM1471
CYM1560
CYM1481
CYM1851
Speed (ns)
tAA = 12, 15
tAA = 20,25,30,35,45
tAA = 15,20,25,30,35
tAA = 25,30,35,45,55,70
tAA = 25,30,35,45
tfreq = 33 MHz
tAA = 25,30,35
tAA = 25,35,45
tAA = 25,30,35,45,55
tAA = 20,25,30,35,45
tAA = 25,35,45,55
tAA = 20,25,30,35,45,55,70
tAA = 70,85, 100, 120,150
tAA = 20,25,30,35,45
tAA = 25,30,35
tAA = 20, 25,30,35,45,55
tAA = 20,25,30,35,45,55
tAA = 85, 100, 120
tAA = 30,35,45
tAA = 85, 100, 120
tAA = 25,30,35
IccflsBflcCDR
Packages
(mA@ns)
960@12
720@25
330@25
400@45
400@25
1500
510@25
960@25
880@25
720@20
980@25
300@35
1l0@85
480@20
720@25
1120@25
960@25
1l0@85
1200@30
11O@85
1250@30
PM,PZ
PM,PZ
PZ
HG
PV
PM
PZ
PZ
HD
PM,PN,PZ
PZ
PD
PD
PM,PZ
HG
PD
PM,PN,PZ
PS
PS
PF,PS
PM,PN,PZ
IccflsB
Packages
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
lOMs
Organization
Speed (ns)
Pins
Part Number
512x8-Registered
512 x 8 -Registered
1024 x8-Registered
1024 x 8-Registered
1Kx8
24S
24S
24S
24S
24S
CY7C225
CY7C225A
CY7C235
CY7C235A
CY7C281
tSNCO = 25/12,30/15,35/20,40/25
K
lKx8
24S
CY7C281A
tAA =30,45
K
lKx8
24
CY7C282
tAA =30,45
K
1Kx8
24
CY7C282A
tAA =30,45
6K
'6K
2Kx8-Registered
2Kx8-Registered
24S
24S
CY7C245/L
CY7C245A/L
tSNcO = 25/12,35/15,45/25
tSNcO = 15/10,25/12,35/15
6K
2Kx8
24S
CY7C291/L
45/25
tAA =35,50
aze
K
K
K
K
K
tSNcO = 25/12,30/15,35/20,40/25
tSNcO = 25/12,30/15,40/20
tSNcO = 25/12,30/15,40/20
tAA =30,45
1-13
(mA@ns)
90
90
90
90
90@45,
100@30
90@45,
100@30
90@45,
100@30
90@45,
100@30
90,60
120@15,
90,60@25
90,60
Availability
D,J,L,P
D,J,L,P
D,J,K,L,P
D,J,K,L,P
D,J,K,P
Now
Q393
Now
Q393
Now
D,J,K,P
Q393
D,P
Now
D,P
Q393
D,J,L,P,Q,S;:r;W
D,J,L,P,Q,S,T,W
Now
Now
D,J,L,P,Q,S,T,W
Now
II
o
u.
~
Product Selector Guide
I
PROMs (continued)
Size
Organization
Pins
Part Number
Speed (ns)
IccflsB
(mA@ns)
Packages
Availabili~
D,J,L,P,Q,S,T,W
Now
D,P
D,P
Now
Now
D,L,Q,P,W
Now
tAA = 10, 12, 15
120@20,
90,60@25
90,60
120@20,
90@25,
90,60@35
120/40@20,
90/30@25
60/15@35
170
H,J,L,P,Q,W
Now
CY7C259
tAA = 10,12,15
170
H,J,L,Q
Now
24S
CY7C261
tAA = 20,25, 35,45,55
D,J,L,P,Q, T, W
Now
8Kx8
24S
CY7C263
tAA = 20,25, 35,45,55
D,J,L,P,Q, T,W
Now
64K
8Kx8
24
CY7C264
tAA = 20,25, 35,45,55
D,p,W
Now
64K
8Kx 8-Registered
28S
CY7C265
120/40@20,
100/30@35
120@20,
100@35
120@20,
100@35
120@15,
100@40
80@50
D,J,L,P,Q,W
Now
16K
2Kx8
24S
CY7C291A/L
16K
16K
2Kx8
2Kx8
24
24
CY7C292(L
CY7C292A/L
tAA =35,50
tAA = 20,25,35,50
16K
2Kx 8-CS Power-Down
24S
CY7C293A/L
tAA = 20,25,35,50
32K
2Kx 16--R~rogrammable
State achine Prom
28S
CY7C258
32K
2Kx 1~Rr.1a~hfn~~::le
44
64K
8Kx8-CS Power-Down
64K
tAA = 20,25,35,50
tSNCO = 15/12,25/15,40/20
50/25
64K
8Kx 8-EPROM Pinout
28
CY7C266
tAA = 20,25,35,45
64K
8Kx8-Registered,
Diagnostic
28S
CY7C269
tSNCO = 15/12,25/15,
28S
28
28
44
CY7C251
CY7C254
CY7C256
CY7C270
tAA = 45,55,65
tAA = 45,55,65
tAA =45,55
tANCKB = 25/11,28/12,35/15
256K
256K
256K
256K
256K
512K
16Kx8-CS Power-Down
16Kx8
32Kx8-Asynchronous
Processor-Intelligent
PROM
32Kx8-CS Power-Down
32Kx8-EPROMPinout
32Kx 8-Registered
16Kx16
32Kx8-Register(Latch
64Kx8
28S
28
28S
44
28S
28
CY7C271
CY7C274
CY7C277
CY7C276
CY7C279
CY7C286
tAA = 30,35, 45,55
tAA = 30,35, 45, 55
tSNco = 30/15, 40/20, 50/25
tAA = 25,30,35
tAA=35,45,55
tAA = 50,60,70, 80
512K
512K
64Kx8-Registered
64Kx 8 with ALE
28S
28S
CY7C287
CY7C285
tAS/CO = 45/15,55/20,65/25
tAA = 65/20,75/25,85/35
128K
128K
256K
256K
40/20,50/25
120/15@20,
100/15@35
120@15,
100@40,
80@50
100/30
100/30
95
175
120/30
120/30
120
175
120
120/40@50,
90/30@70
120
180
D,L,P'Q,W
Now
D,J,L,P,Q,W
Now
D,L,P,Q,W
D,P,Q,W
D,J,p,W
H,J,Q
Now
Now
Q493
Now
D,J,K,L,P,Q,T,W
D,J,KL,P,Q,T,W
D, J, KL, P, Q, T,W
H,J,Q
J,W
D,L,P'Q,W
Now
Now
Now
Now
Now
Now
D,L,P,Q,W
D,L,P,Q,W
Now
Now
PLDs
Size
Organization
Pins
Part Number
PAL20
PAL20
PAL20
16L8
16R8
16R6
20
20
20
PAL16L8
PAL16R8
PAL16R6
PAL20
16R4
20
PAL16R4
PAL20
PAL20
PAL20
PAL20
PLD20
16L8
16R8
16R6
16R4
18G8-Generic
20
20
20
20
20
PALC16L8(L
PALC16R8(L
PALC16R6(L
PALC16R4(L
PLDC18G8
Speed (ns)
tpD =:' 4.5/5/7
ts/co = 2.5/4.5,2.5/5,3.5/6
tpD/S/CO = 4.5/2.5/4.5,5/2.5/5,
7/3.5/6
tPD/S/CO = 4.5/2.5/4.5,5/2.5/5,
7/3.5/6
tpD=20
ts/co = 15/12
tPD/S/CO = 20/20/15
tPD/S/CO = 20/20/15
tPD/S/CO = l2/8/10
1-14
ICc/ISB
(mA@ns)
Packages
AvaiiabilU
180
180
180
D,J,P
D,J,P
D,J,P
Now
Now
Now
180
D,J,P
Now
70,45
70,45
70,45
70,45
90/70
D,L,P,Q,V,W
D,L,P,Q, YoW
D,L,P,Q,V,W
D,L,P,Q,V,W
D,J,L,P,Q,V,W
Now
Now
Now
Now
Now
,~
'~'
~I
Product Selector Guide
'iE CYPRESS
!'
II _
iF
SEMICONDUCTOR
ILDs (continued)
Organization
IcdlsB
(mA@ns)
Speed (ns)
Pins
Part Number
'LD24
'LD24
22V10-Macrocell
22V10-Macrocell
24S
24S
PALC22VlO/L
PALC22VIOB
tPDlSlCO =
25/15/15,20/12/12
tpDISlCO = 15/10/10
90,55
90
'LD24
22V10-Macrocell
24S
PAL22V10C
tpDISlCO =6/3/5.5,7.5/3/6,
'LD24
22VP10-Macrocell
24S
PAL22VPlOC
f\L24
LD24
LD24
LDB24
LD24
LD24
LD28
22V10-Macrocell
20G10-Generic
20G10-Generic
20G10-Generic
20RA10-Asynchronous
7B326-16 Macrocell
7C330-State Machine
24
24S
24S
24S
24S
24S
28S
PALC22V10D
PLDC20GlO
PLDCZOGlOB
PLD20GlOC
PLD20RAlO
PLD610
CY7C330
10/3.6/7.5
tpD/S/CO = 6/3/5.5,7.5/3/6,
10/3.6/7.5
tpD = 7.5, 10, 15
tpDlSlCO = 25/15/15
tpDISICO = 15/12/10
tPDlSlCO = 7.5/3/6.5, 10/3.6/7.5
tpDlSlCO = 15/10/15
tpD= 10
fMAX., tIS, teo = 66 MHz/3ns/12ns
LD28
7C331-Asynchronous,
Registered
7C332-lnput Registered,
Combinatorial
7B333B--16 Macrocell
7C335-Universal
Synchronous
7C361-32-MacrocellState
Machine
7C344-32 Macrocell
7C343-64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
7C371-32-Macrocell
FlashCPLD
7C372-64-Macrocell
FlashCPLD
7C373-64-Macrocell
FlashCPLD
7C374-128-Macrocell
FlashCPLD
7C375-128-Macrocell
FlashCPLD
CMOS1KGateFPGA
CMOS 2KGate FPGA
CMOS 4KGate FPGA
CMOS 4KGate FPGA
28S
CY7C331
tpD/S/CO =
28S
CY7C332
28S
28S
CY7B333B
CY7C335
28S
CY7C361
28S
44
68
84
44S
CY7C344
CY7C343
CY7C342/B
CY7C341/B
CY7C371
44S
Size
LD28
LD28
LD28
LD28
1AX28
1AX44
1AX68
IAX84
lX-44
lX-44
lX-84
lX-84
lX-l64
I\SIC-1
I\SIC-2
I\SIC-4
I\SIC-4
Packages
Availability
190
D,J,K,L,P'Q,W
D,H,J,K,L,
P,Q,W
D,J,L,P
Now
190
D,J,L,P
Now
130/90/90
55
70
190
80
130
130@50
MHz
120@25ns
D,J,L,P
D, J, L, P, Q, W
D,H,J,L,P,Q,W
D,J,L,P
D,H,J,L,P'Q,W
D,J,K,L,p,Y
D,H,J,L,P,Q,W
Now
Now
Now
Now
Now
Now
Now
D,H,J,L,P,Q,W
Now
tPD= 15
120@20ns
D,H,J,L,P,Q,W
Now
tpDlSlCO =
10/8/8
fMAX/tIS = 100 MHz/2ns,
83MHz/2ns
fMAX = 125 MHz
130
140
D,J,K,L,p,Y
D,H,J,L,P,Q,W
Now
Now
140
D,H,J,L,P,Q,W
Now
tpDlSlCO =
20/12/12
20/12/12
tpD/SICO = 25/15/14,15/10/10
tPD/s/CO = 25/20/16,15/10/10
iMAx/tslteo= 100 MHz/7.5 nsn.5 ns
200/150
135/125
250/225
380/360
150{fBD
D,H,J,L,P,Q,W
H,J
G,H,J,L,R
H,J
J
Now
Now
Now
Now
Q393
CY7C372
fMAX/tsitco = 100MHz/9ns/9ns
180{fBD
J
Q493
84S
CY7C373
fMAX/tsitco = 100 MHz/9 ns/9 ns
180{fBD
J
Q493
84S
CY7C374
fMAX/tsitco = 100 MHz/9 ns/9 ns
300{fBD
J
Q393
164S
CY7C375
fMAX/tsitco = 100 MHz/9 ns/9 ns
300(fBD
N
Q393
68S
84S
84S
144S
CY7C382
CY7C384
CY7C385
CY7C386
-0,-1,-2
-0, -1,-2
-0, -1,-2
-0,-1,-2
ISB= 10
ISB= 10
ISB= 10
ISB = 10
J
J
J
N
Q293
Q293
Q493
Q293
20/12/20
tpDISlCO =
Now
Now
CLPLDs
Organization
,6P8-10KH
6P8-lOKH
6P8-100K
6P8-100K
6P4-10KH
6P4-10KH
6P4-100K
6P4-100K
Pins
24
24
24
24
24
24
24
24
Part Number
CYlOE301
CY10E301L
CY100E301
CY100E301L
CY10E302
CYlOE302L
CYlOOE302
CYlOOE302L
Speed (ns)
tpD=4
tpD=6
tpD=4
tpD=6
tpD=3,4
tpD=4
tPD=3,4
tPD=4
1-15
lEE
Packages
(mA@ns)
240
170
240
170
220
170
220
170
D,Y
J,P
D,Y
J,P
D,Y
J,P
D,Y
J,P
Availability
Now
Now
Now
Now
Now
Now
Now
Now
II
o
u.
2!:
·
.
fin
Product Selector GUide'
• CYPRESS
SEMICONDUCTOR
FIFOs
Organization
Pins
64x4
64x4
64x4-w/OE
64x5
64x5-w/OE
64xS-w/OE and Almost Flags
64 x 9-w/Almost Flags
512 x 9-wlHalf Full Flag
512x 9-wlHalfFuli Flag
512x9-wlHalfFuli Flag
512 x 9-Clocked
512 x 9-Clockedw/Prog.Flags
512x 18-Clocked w/Prog. Flags
512 x IS-Clocked w/prog.Flags
1Kx9-w/HalfFuliFlag
1Kx 9-w/HalfFuli Flag
1Kx9-w/HalfFuliFlag
1Kx 18-Clocked w/Prog. Flags
1Kx IS-Clocked w/Prog. Flags
2Kx 9-w/HalfFuli Flag
2Kx9-w/HalfFuliFlag
2Kx 9-w/HalfFuli Flag
2Kx9-Bidirectional
2K x 9-Clocked
2K x 9-Clockedw/Prog. Flags
2Kx 18-Clocked w/Prog. Flags
2Kx IS-Clocked w/Prog. Flags
4Kx9-w/HalfFuliFlag
4Kx 9-wlHalfFuli Flag
4Kx9-wlHalfFuli Flag
8K x 9-Module
8Kx 9-w/HalfFullFlag
8K x 9-w/Prog. Flags
16Kx 9-w/HalfFuliFlag
16K x 9-w/Prog. Flags
16K x 9-Module
32K x 9-w/HalfFuli Flag
32Kx 9-w/Prog. Flags
64Kx 9-Module
128K x 9-Module
Part Number
16
16
16
18
18
28S
28S
28
28S
28S
28S
32
48
52
28
28S
28S
48
52
28
28S
28S
28S
28S
32
48
52
28
28S
28S
28
28
28
28
28
28
28
28
28
28
CY3341
CY7C401
CY7C403
CY7C402
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C421A
CY7C441
CY7C451
CY7C445
CY7C455
CY7C424
CY7C425
CY7C425A
CY7C446
CY7C456
CY7C428
CY7C429
CY7C429A
CY7C439
CY7C443
CY7C453
CY7C447
CY7C457
CY7C432
CY7C433
CY7C433A
CYM4210
CY7C460
CY7C470
CY7C462
CY7C472
CYM4220
CY7C464
CY7C474
CYM4208
CYM4209
Speed
1.2, 2 MHz
5,10,15,25 MHz
10,15,25 MHz
5,10,15,25 MHz
10,15,25 MHz
15,25,35 MHz
15,25,35 MHz
20, 25,30,40,65
20,25,30,40,65
10,15
14,20,30·
14,20;30*
14,20,30·
14,20,30'
20, 25,30,40,65
20, 25,30,40,65
10,15
14,20,30'
14,20,30·
20, 25,30,40,65
20, 25,30,40,65
10,15
30,40,65
14,20,30*
14,20,30*
14,20,30'
14,20,30'
25,30,40,65
25,30,40,65
10,15
30, 40, 50, 65
15,25,40
15,25,40
15,25,40
15,25,40
30, 40, 50, 65
15,25,40
15,25,40
25,30,40
25,30,40
IccfIsB
(mA@ns)
45
75
75
75
75
120
120
142/30
142/30
180
180
180
120
120
142/30
142/30
180
120
120
142/30
142/30
180
140/40
180
180
120
120
142/25
142/25
180
540/120
180
180
180
180
540/120
180
180
640/120
640/120
Packages
D,P
D,L,P
D,L,P
D,L,P
D,L,P
D,L,p,V
D,L,P,V
D,P
D,J,L,p,V
J,P
D,J,L,p, V
D,J,L
P,D
J,L
D,P
D,J,L,P
J,P
D,P
J,L
D,P
D,J,L,p,V
J,P
D,J,L,p,V
D,J;L,p,V
D,J,L
D,P
J,L
D,P
D,J,L,p,V
J,P
HD
D,J,L,P
D,J,L,P
D,J,L,P
D,J,L,P
HD
D,J,L,P
D,J,L,P
HD
HD
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Q194
Now
Now
Now
Now
Q194
Now
Now
Now
Now
Now
Now
Now
6194
Now
Now
Now
Now
Now
. Now
Now
Now
Now
Now
Now
Now
Now
Now
r
• Clocked FIFO [CY7C44x145x] times are cycle times.
Logic
Organization
P~ammable Skew Clock Buffer
(
Output)
PrWcammable Skew Clock Buffer
(C OS Output)
2901-4-Bit Slice
2901-4-BitSlice
4x2901-16-BitSlice
2909-Sequencer
2911-Sequencer
ECL{ITL Translator-lOKH
ECL{ITL Translator-lOOK
ECL{ITL Translator-10KH
2909-Sequencer
IccfIsB
Pins
Part Number
Speed
32
CY7B991
15-80 MHz
65
J,L
Now
32
CY7B992
15-80 MHz
65
J,L
Now
40
40
64
28
20
84
84
28S
28
CY7C901
CY2901
CY7C9101
CY7C909
CY7C911
CYlOE383
CY101E383
CYlOE384L
CY2909
tCLK = 23,31ns
C
tCLK = 30,40ns
tCLK = 30,40 ns
tCLK = 30,40 ns
tpD = 2.5/3 ns
tpD = 2.5/3 ns
tpD=3ns
A
70
140
60
55
55
270
270
110
70
D,J,L,P
D,P
D,J,L,P
D,J,L,P
D,J,L,P
J,N
J,N
V
D,P
Now
Now
Now
Now
Now
Now
Now
Now
Now
1-16
(mA@ns)
Packages
Availability
I
-
. ===-===r
-. :4
j; CYPRESS
Product Selector Guide
'I
I - - = - , SEMICONDUCTOR
Logic (continued)
Organization
Pins
2911-Sequencer
2910-Controller (17-word Stack)
2910-Controller (9-word Stack)
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier/Accumulator
CY2911
CY7C91O
CY2910
CY7C516
CY7C517
CY7C51O
20
40
40
64
64
64
IcdIsB
(mA@ns)
Speed
Part Number
A
tCLK = 40,50, 93 ns
A
tMC = 38,45,55,75 ns
tMC =38,45,55,75 ns
tMC =45, 55, 65, 75 ns
70
100
170
100@lOMHz
100@lOMHz
100@10MHz
Packages
Availability
D,P
D,J,L,P
D,J,L,P
D,G,J,L,P
D,G,J,L,P
D,G,J,L,P
Now
Now
Now
Now
Now
Now
l>esign and Programming Tools
Part Name
Part Number
1Ype
QuickProII
MAX+PLUSAL20LlOAC
>AL20LlOAM
>AL20LlOC
'AL20LlOM
'AL20L2C
'AL20L2M
'AL20LSA - 2C
'AL20LSA - 2M
'AL20LSAC
'AL20LSAM
'AL20LSC
'AL20LSM
'AL20R4A-2C
'AL20R4A-2M
'AL20R4AC
'AL20R4AM
'AL20R4C
'AL20R4M
'AL20R6A - 2C
'AL20R6A - 2M
'AL20R6AC
'AL20R6AM
'AL20R6C
M20R6M
M20R8A - 2C
M20R8A - 2M
M20R8AC
M20R8AM
M20R8C
M20R8M
ALC22VlO/A
CYPRESS
PALC16R8-40M
PALC16R8-20M
PALC16R8-35C
PALC1648L- 25C
PALC16R8-40M
PLDC20GlO-35C
PLDC20G10-40M
PLDC20GlO-35C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO- 35C
PLDC20GlO-40M
PLDC20GlO-35C
PLDC20G 1O-40M
PLDC20GlO-25C
PLDC20G10-30M
PLDC20GlO-35C
PLDC20G 1O-40M
PLDC20G 10-35C
PLDC20G 1O-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20G 1O-40M
PLDC20GlO-35C
PLDC20G 1O-40M
PLDC20G10-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20G10-35C
PLDC20G 10-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20G 1O-40M
PALC22VlO- 35C
'lOSAIC
REFIX:MS
128SC-100
128SC-100
128SC-45
128SC-55
128SC-70
128SC-70
CYPRESS
PREFIX:SYM
1420HD-85C
1421HD-85C
1420HD-45C
1420HD-55C
1420HD-70C
1421HD-70C
[OTOROLA
REFIX:MCM
UFFIX:BXAJC
UFFIX:P
UFFIX:S
UFFIX:Z
0422-10C
423-45
J16H-45
016H-55
316H-70
018-35
J18-45
167H-35
CYPRESS
PREFIX:CY
SUFFIX:MB
SUFFIX:P
SUFFIX:D
SUFFIX:L
lOE422-7C
7C168A-45C+
6116A-45C
6116A-55C
6116A-55C
7C128A-35C
7C128A-45C
7C167A-35C
MOTOROLA
2167H-45
2167H-55
6164-45
6168-35
6168-45
61L64-45
6205C
6206C-15
6206C-20
6206C-25
6206C-35
6207C-15
6207C-20
6207C-25
6207C-35
6208C-20
6208C-25
6208C-25
6208C-35
62486FN14
62486FN19
62486FN24
6264-15C
6264-25
6264-25
6264-30
6264-30
6264-35
6264-35
6264-45
6264-45
6268P20
6268P25
6268P35
6268P40
6268P45
6268P45
6269P20
6269P25
6269P35
6270-20
6270-25
6270-35
6270-45
6287-15
6287-20
6287-25
6287-35
6288-12
6288-15
6288-25
6288-30
6288-35
6290-12
6290-15
6290-20
6290-25
6290-35
62940FN14
62940FN19
62940FN24
62V06D-20
CYPRESS
7C167A-45C
7C167A-45C
7C186-45C
7C168A-35C+
7C168A-45C+
7C186-45C
7C188
7C199-15
7C199-20
7C199-25
7C199-35C
7C197-15
7C197-20
7C197-25
7C197-35
7C194-20
7C194-25
7C194-25C
7C194-35
7B173-14C
7B173-18C
7B173-21C
7B185-15C
7C185-25C
7C186-25C
7C185-25C
7C186-25C
7C185-35C
7C186-35C
7C185-45C
7C186-45C
7C168A-20C
7C168A-25C
7C168A-35C
7C168A-40C
7C168A-45
7C168A-45C
7C169A-20C
7C169A-25C
7C169A-35C
7C170A-20C
7C170A-25C
7C170A-35C
7C170A-45C
7C187-15C
7C187-20C
7C187-25C
7C187-35C
7B164-12C
7C164-15C
7C164-25C
7C164-25C
7C164-35C
7B166-12C
7C166-15C
7C166-20C
7C166-25C
7C166-35C
7B174-14C
7B174-18C
7B174-21C
7C1399-20C
1-31
MOTOROLA
6706C-12
6708C-12
6709C-12
CYPRESS
7C199-12C
7C194-12C
7C195-12C
NATIONAL
PREFIX:DM
PREFIX:GAL
PREIFX:IDM
PREFIX:NM
PREFIX:NMC
SUFFIX:]
SUFFIX:N
100422-10C
100422-5C
100422A-7C
100422AC
100474A-lOC
100474A-8C
10422-lOC
10422-5C
10422A-7C
10422AC
10474A-8C
1047A-10C
12LlOC
14LSC
14LSM
16L6C
16L6M
16V8A-12LC
16V8A-12C
16V8A-15LC
16V8A-15C
16V8A-15LM
16V8A-15M
16V8A-20LM
16V8A-20M
18lAC
18lAM
20L2M
2147H
2147H
2147H-1
2147H-2
2147H-3
2147H-3
2147H-3L
2148H
2148H
2148H
2148H
2148H-2
2148H-3
2148H-3L
2148HL
2901A-1C
2901A-1M
2901A-2C
2901A-2M
2901AC
2901AM
2909AC
CYPRESS
PREFIX:CY
PREFIX:None
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:D
SUFFIX:P
100E422L-7C
100E422-5C
100E422L-7C
100E422L-7C
100E474L-7C
lOOE474L-7C
lOE422L-7C
lOE422-5C
lOE422L-7C
lOE422L-7C
lOE474L-7C
lOE474L-7C
PLDC20GlO-35C
PLDC20GlO-35C
PLDC20G10-40M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC18G8-12C
PLDC18G8-12C
PLDC18G8-15C
PLDC18G8-15C
PLDC18G8-15MB
PLDC18G8-15MB
PLDC18G8-20MB
PLDC18G8-20MB
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-40M
2147-55C
2147-55M
2147-35C
2147-45C
2147-55C
2147-55M
7C147-45C
2148-55C
7C148-C
2148-C
21lA8-C
2148-45C
2148-55C
21lA8-55C
21lA8-55C
7C901-31C
7C901-32M
7C901-31C
7C901-32M
7C901-31C
7C901-32M
2909AC
•
0
U.
~
~
~~PRESS
~., SEMICONDUcrOR
NATIONAL
2909AM
2911AC
2911AM
54S189
54S189
54S189
54S189
54S189A
54S189A
54S189A
74S189
74S189A
74S289A
75S07
77LS181
77S181
77S181A
77S281
77S281A
77S401
77S401A
77S402
77S402A
77SR181
77SR476B
77SR476
85S07A
87LS181
87S181
87S281
87S281A
87S401
87S401A
87S402
87S402A
87SR181
87SR476
87SR476B
93IA22A
NMF512X9-15
NMF512X9-25
NMF2048X9-20
NMF4096X9A - 25
PAL10016P4-4C
PALIOO16P4-6C
PAL10016P8-4C
PALIOO16P8-6C
PAL1016P4-4C
PAL1016P4-6C
PAL1016P8-4C
PAL1016P8.,...6C
PAL164A2M
PAL16LSA2C
PAL16LSA2M
PAL16LSAC
PAL16LSAM
PAL16LSB2C
PAL16LSB2M
PAL16LSB4C
PAL16LSB4M
PAL16LSBM
PAL16LSC
CYPRESS
2909M
2911AC
2911M
74S189M
7C189-M
27S03A-M
27LS03A-M
74S189M
7C189-25M
7C189-M
7C189-C
7C189-C
7C189-C
7C190-25M
7C282-45M
7C282-45M
7C282-45M
7C281-45M
7C281-45M
7C401-10M
7C401-10M
7C402-10M
7C402-10M
7C235-40M
7C225-40M7C225-40M7C128-45C+
7C282-45C
7C282-45C
7C281-45C
7C281-45C
7C401-10C
7C401-15C
7C402-10C
7C402-15C
7C235-40C
7C225-40C
7C225-30C
7C122-C
7C421A-15
7C421-25
7C429-20
7C433-25
100E302L-4C
100E302L-4C
100E301-4C
100E301L-6C
lOE302L-4C
lOE302L-4C
lOE301-4C
10E301L-6C
PALC16R4-40M
PALC16LS-35C
PALC16LS-40M
PALC16LS-25C
PALC16LS-30M
PALC16LS- 25C
PALC16LS- 30M
PALC16LSL- 35C
PALC16LS-40M
PALC16LS-20M
PALC16LS- 35C
Product Liue Cross Reference
NATIONAL
PAL16LSM
PAL16R4A2C
PAL16R4AC
PAL16R4AM
PAL16R4B2C
PAL16R4B2M
PAL16R4B4C
PAL16R4B4M
PAL16R4BM
PAL16R4C
PAL16R4M
PAL16R6A2C
PAL16R6A2M
PAL16R6AC
PAL16R6AM
PAL16R6B2C
PAL16R6B2M
PAL16R6B4C
PAL16R6B4M
PAL16R6BM
PAL16R6C
PAL16R6M
PAL16R8A2C
PAL16R8A2M
PAL16R8AC
PAL16R8AM
PAL16R8inc
PAL16R8B2M
PAL16R8B4C
PAL16R8B4M
PAL16R8BM
PAL16R8C
PAL16R8M
PAL20LlOB2C
PAL20LlOB2M
PAL20LlOC
PAL20LlOM
PAL20L2C
PAL20LSAC
PAL20LSAM
PAL20LSBC
PAL20LSBM
PAL20LSC
PAL20LSM
PAL20R4AC
PAL20R4AM
PAL20R4BC
PAL20R4BM
PAL20R4C
PAL20R4M
PAL20R6AC
PAL20R6AM
PAL20R6BC
PAL20R6BM
PAL20R6C
PAL20R6M
PAL20R8AC
PAL20R8AM
PAL20R8BC
PAL20R8BM
PAL20R8C
PAL20R8M
CYPRESS
PALC16LS-40M
PALC16R4-35C
PALC16R4-25C
PALC16R4-30M
PALC16R4-25C
PALC16R4-30M
PALC16R4L- 35C
PALC16R4-40M
PALC16R4-20M
PALC16R4-35C
PALC16R4-40M
PALC16R6- 35C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-30M
PALC16R6L- 35C
PALC16R6-40M
PALC16R6-20M
PALC16R6-35C
PALC16R6-40M
PALC16R8-35C
PALC16R8-40M
PALC16R8-25C
PALC16R8- 30M
PALC16R8-25C
PALC16R8-30M
PALC16R8L-35C
PALC16R8-40M
PALC16R8-20M
PALC16R8-35C
PALC16R8-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO- 35C
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20G10-25C
PLDC20GlO- 30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20G10-25C
PLDC20G10-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20G10-30M
PLDC20GlO- 35C
PLDC20GlO-40M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-25C
PLDC20GlO-30M
PLDC20GlO-35C
PLDC20G 1O-40M
NEC
PREFIX:uPD
SUFFIX:C
SUFFIX:D
SUFFIX:K
SUFFIX:L
100422-lOC
lOO422-7C
100470-lOC
100470-15C
100474-lOC
100474-4.5
100474-6
100474-8C
100474A-5
100474A-6
100474E-4
100484-10
100484-15
100A484-5
100A484-7
10422-10C
10422-7C
10470-10C
10470-15C
10474-10C
10474-8C
10474A-5
10474A-6
10474E-4
10484-10
10484-15
lOA484-5
lOA484-7
2147-2
2147-3
2147A-25
2147A-35
2147A-45
2149
2149-1
2149-2
2167-2
2167-3
27HC65-25
27HC65-35
27HC65-45
4311-45
4311-55
43254C-35
43254C-45
4361-40
4361-45
4361-55
4361-70
4362-45
4362-55
4362-70
4363-45
4363-55
4363-70
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* = meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t
SOIConly
:j: = 32-pin LCC crosses to the 7C198M
1-32
CYPRESS
PREFIX:CY
SUFFIX:P
SUFFIX:D
SUFFIX:L
SUFFIX:F
lOOE422L-7C
100E422L-7C
100E470-'-7C
100E470-7C
100E474L-7C
100E474-3.5C
100E474-5C
100E474L-7C
100E474L-5C
100E474L-5C
100E474-3.5C
100E484L-7C
100E484L-7C
100E484-5C
100E484L-7C
10E422L-7C
10E422L-7C
lOE470-7C
1OE470-7C
l0E474L-7C
lOE474L-7C
lOE474L-5C
lOE474L-5C
10E474-4C
lOE484L-7C
lOE484L-7C
lOE484-5C
1OE484L-7C
2147-55C
2147-55C
7C147-25C
2147-35C
2147-45C
2149-55C
2149-45C
2149-35C
7C167A-45C
7C167A-45C
7C263/4- 25C
7C263/4-35C
7C263/4-45C
7C167A-45C
7C167A-45C
7C194-35
7C194-45
7C187-35C
7C187-45C
7C187-45C
7C187-45C
7C164-45C
7C164-45C
7C164-45C
7C166-45C
7C166-45C
7C166-45C
I
I'
.
:~PRESS
Product Line Cross Reference
, _ , SEMICONDUCTOR
l1256SB
·1258L
·1258LB
·1258S
-1258SB
CYPRESS
PREFIX:CY
7C191-C
7CI91-MB*
7C19l-C
7C19l-MB
7C192-C
7CI92-MB*
7C192-C
7C192-MB
7C199/8-C*
7C199/8-MB*
7C199/8-C
7C199/8-MB
7C194-C*
7C194-B*
7C194-C
7C194-B
'ERFORMANCE
'REFIX:P
UFFIX:L
UFFIX:S
1256-35
1256-45
C1256-25
C1256-35
C1256-45
C1257-25
C1257-35
C1257-45
C1258-25
C1258-35
C1258-45
C150-l2C
C150-l5C
C150-15M
C150-20C
C150-20M
C150-25C
C150-25M
C150-35M
C164DW-20C
C164DW-25C
C164DW-25M
Cl64DW-35C
C164DW-35M
C164DW-45C
C164DW-45M
C164DW-55C
C164DW-55M
C164P-20C
C164P-25C
Cl64P-25M
C164P-35C
C164P-35M
Cl64P-45C
;C164P-45M
C164P-55C
b64P-55M
C168l-25C
C168l-35C
r'C168l-35M
CYPRESS
PREFIX:CY
SUFFIX:L
SUFFIX:S
7C199-35
7C199-45
7C199-25
7C199-35
7C198-45
7C197-25
7C197-35
7C197-45
7C194-25
7C194-35
7C194-45
7C150-l2C
7C150-l5C
7C150-l5M
7C150-l5C
7C150-l5M
7C150-25C
7C150-25M
7C150-35M
7C186-20C
7C186-25C
7C186A-25M
7C186-35C
7C186A-35M
7C186-45C
7C186A-45M
7C186-55C
7C186A-55M
7C185-20C
7C185-25C
7C185A-25M
7C185-35C
7C185A-35M
7C185-45C
7C185A-45M
7C185-55C
7C185A-55M
7C17lA-25C
7C17lA-35C
7C17lA-35M
PARADIGM
PREFIX:PDM
H251L
H251LB
H251S
n251SB
n252L
n252LB
~1252S
~1252SB
~1256L
n256LB
~1256S
PERFORMANCE
4C168l-45C
4C168l-45M
4C1682-25C
4C1682-35C
4C1682-35M
4C1682-45C
4C1682-45M
4C169-25C
4C169-30C
4C169-35C
4C169-35M
4C169-45M
4C187-20C
4C187-25C
4C187-25M
4C187-35M
4C188-20C
4C188-25C
4C188-25M
4C188-35C
4C188-35M
4C188-45M
4C198-20C
4C198-25C
4C198-25M
4C198-35C
4C198-35M
4C198-45M
4C198l-20C
4C198l-25C
4C198l-25M
4C198l-35C
4C198l-35M
4C1981-45M
4C198l-55M
4C1982-20C
4C1982-25C
4C1982-25M
4C1982-35C
4C1982-35M
4C1982-45M
4C1982-55M
93U422-35C
93U422-35C
93U422-35C
93U422-35M
93U422-35M
CYPRESS
7C17lA-45C
7Cl71A-45M
7Cl72A-25C
7Cl72A-35C
7Cl72A-35M
7Cl72A-45C
7Cl72A-45M
7C169A-25C
7C169A-25C
7C169A-35C
7C169A-35M
7C169A-45M
7C187-20C
7C187-25C
7C187A-25M
7C187A-35M
7C164-20C
7C164-25C
7Cl64A-25M
7C164-35C
7C164A-35M
7C164A-45M
7C166-20C
7C166-25C
7C166A-25M
7C166-35C
7C166A-35M
7C166A-45M
7C16l-20C
7C16l-25C
7C16lA-25M
7C16l-35C
7C16lA-35M
QUICKLOGIC
PREFIX:QL
l2X16-0XX68C
l2X16-0XX68I
l2X16-0XX84C
12X16-0XX84I
12X16-lXX68C
12X16-lXX68I
12X16-lXX84C
12X16-lXX84I
12X16-2XX68C
l2X16-2XX84C
8X12-0XX44C
8X12-0XX44I
CYPRESS
PREFIX:CY
7C383-0C
7C383-OI
7C384-0C
7C384-01
7C383-lC
7C383-1I
7C384-lC
7C384-1I
7C383-2C
7C384-2C
7C381-0C
7C381-OI
7C16lA~45M
7C16lA-55M
7C162-20C
7C162-25C
7C162A-25M
7C162-35C
7C162A-35M
7C162A-45M
7C162A-55M
7C122-l5C
7C122-25C
7C122-35C
7C122-25M
7C122-35M
1-33
QUICKLOGIC
8X12-0XX68C
8X12-0XX681
8X12-lXX44C
8X12-1XX441
8X12-lXX68C
8X12-lXX68I
8X12-2XX44C
8X12-2XX68C
CYPRESS
7C382-0C
7C382-OI
7C381-1C
7C38l-ll
7C382-lC
7C382-1I
7C38l-2C
7C382-2C
SAM SUNG
PREFIX:KM
6l257A-25
61257A-35
6l257A-45
64257A-25
64257A-35
64257A-45
75COlA-15
75COlA-20
75COlA-25
75COlA-35
75COlA-50
75COlA-80
75COlAP-20
75C01AP-25
75COIAP-35
75COlAP-50
75COlAP-80
75C02A-15
75C02A-20
75C02A-25
75C02A-35
75C02A-50
75C02A-80
75C02AP-20
75C02AP-25
75C02AP-35
75C02AP-50
75C02AP-80
75C03A-15
75C03A-20
75C03A-25
75C03A-35
75C03A-50
75C03A-80
75C03AP-20
75C03AP-25
75C03AP-35
75C03AP-50
75C03AP-80
75C102A-20
75C102A-25
75C102A-35
75C102A-80
CYPRESS
PREFIX:CY
7C197-25C
7C197-35C
7C197-45C
7C194-25C
7C194-35C
7C194-45C
7C421A-15
7C421-20C
7C421-25C
7C42l-30C
7C42l-40C
7C42l-65C
7C420-20C
7C420-25C
7C420-35C
7C420-50C
7C420-80C
7C425A-15
7C425-20C
7C425-25C
7C425-30C
7C425-40C
7C425-65C
7C424-20C
7C424-25C
7C424-30C
7C424-40C
7C424-65C
7C429A-15
7C429-20C
7C429-25C
7C429-30C
7C429-40C
7C429-65C
7C428-20C
7C428-25C
7C428-30C
7C428-40C
7C428-65C
7C425-20C
7C425-25C
7C425-25C
7C425-65C
SHARP
PREFIX:LH
52251-35
52251-45
52252-35
52252-45
52254D-25
CYPRESS
PREFIX:CY
7C197-35C
7C197-45C
7C194-35C
7C194-45C
7C199-25C
II
o
LL
~
••
;~PR&SS
~;
SHARP
52254D-35
52254D-45
52259
5481-15
5481-25
5481-35
5491-15
5491-25
5491-35
5496-20
5496-35
5496-50
5496D-15
5496D-20
5496D-35
5496D-50
5497-20
5497-35
5497-50
5497D-15
5497D-20
5497D-35
5497D-50
5498-20
5498-35
5498-50
5498D-15
5498D-20
5498D-35
5498D-50
5499-35
5499-50
5499D-15
5499D-35
5499D-50
5749/J-55
5749/J-70
CYPRESS
7C199-35C
7C199-45C
7C188
7C408A-15C
7C408A-25C
7C408A-35C
7C409A-15C
7C409A-25C
7C409A-35C
7C420-20C
7C420-30C
7C420-40C
7C421A-15
7C421-20C
7C421-30C
7C421-40C
7C424-20C
7C424-30C
7C424-40C
7C425A-15
7C425-20C
7C425-30C
7C425-40C
7C428-20C
7C428-30C
7C428-40C
7C429A-15
7C429-20C
7C429-30C
7C429-40C
7C432-30C
7C432-40C
7C433A-15
7C433-30C
7C433-40C
7C263/4-55C
7C263/4-55C
SIGNETICS
SUFFIX:G
SUFFIX:N
SUFFIX:R
100422BC
100422CC
100474AC
10422BC
10422CC
10474AC
27HC641-45C
27HC641-55C
N74S189
N82HS641
N82HS641A
N82HS641B
N82HS641C
N82LHS191-3
N82LHS191-6
N82S181
N82S181A
N82S181C
N82S191-3
N82S191-6
CYPRESS
SUFFIX:L
SUFFIX:P
SUFFIX:F
100E422-7C
100E422-7C
100E474-7C
lOE422-7C
lOE422-7C
lOE474-7C
7C263/4-45C
7C263/4-55C
74S189C
7C263/4-55C
7C263/4-45C
7C263/4-35C
7C263/4-25C
7C291A-35C
7CZ92A-35C
7CZ81/2-45C
7C281/2-45C
7C281/2-30C
7C291A-50C
7C292A-50C
I
Product Line Cross Reference
SEMICONDUCTOR
SIGNETICS
N82S191A-3
N82S191A-6
N82S191C-3
N82S191C-6
S82HS641
S82LS181
S82S181
S82S181A
S82S191-3
S82S191-6
S82S191A-3
S82S191A-6
S82S19IB-3
S82S19IB-6
CYPRESS
7C291A-50C
7C292A-50C
7C291A-35C
7C292A-35C
7C263/4-55M
7C282-45M
7C282-45M
7C282-45M
7C291A-50M
7C292A-50M
7C291A-50M
7C292A-50M
7CZ91A-50M
7C292A-50M
SONY
PREFIX:CXK
51256P-35
51256P-45
54256P-35
54256P-45
58255AJ-25
58255AP-25
58258P-35
58258P-45
58258SP-35
58258SP-45
CYPRESS
PREFIX:CY
7C197-35
7C197-45
7C194-35
7C194-45
7C199-25
7C199-25
7C198-35
7C198-45
7C199-35
7C199-45
TI
PREFIX:JBP
PREFIX:PAL
PREFIX:SM
PREFIX:SMJ
PREFIX:SN
PREFIX:TBP
PREFIX:TIB
PREFIX:TMS
SUFFIX:F
SUFFIX:J
SUFFIX:N
10016P8-6C
lOH16P8-6C
22V10AC
22VlOAM
54HC189
54HCT189
54LS189A
54LS219A
54S189A
61CD256-35
61CD256-45
64C256-35
64C256-45
68CE256-35
68CE256-45
7489
74ACT29116
74ACT29116-1
CYPRESS
PREFIX:CY
SUFFIX:P
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:F
SUFFIX:L
SUFFIX:D
100E301L-6C
10E301L-6C
PALC22VlO-25C
PALC22VlO-30M
7C189-25M
7C189-25M
27LS03M
7C190-25M+
74S189M
7C197-35M
7C197-45M
7C194-35M
7C194-45M
7C198-35M
7C198-45M
7C189-25C
7C9116AC
7C9116AC
7C189-25C
7C190-25C
7C189-25C
27LS03C
74HC1~9
74HC219
74HCT189
74LS189A
TI
74LS219A
74S189A
74S189B
HCT9510E
HCT951OE-10
HCT9510M
PAL16L8-20M
PAL16L8-25C
PAL16L8-30M
PAL16L8A-2C
PAL16L8A-2M
PAL16L8AC
PAL16L8AM
PAL16R4-20M
PAL16R4-25C
PAL16R4-30M
PAL16R4A-2C
PAL16R4A-2M
PAL16R4AC
PAL16R4AM
PAL16R6-20M
PAL16R6-25C
PAL16R6-30M
PAL16R6A - 2C
PAL16R6A-2M
PAL16R6AC
PAL16R6AM
PAL16R8-20M
PAL16R8-25C
PAL16R8-30M
PAL16R8A-2C
PAL16R8A-2M
PAL16R8AC
PAL16R8AM
PAL20LlOA - 2C
PAL20LlOA-2M
PAL20LlOAC
PAL20LlOAM
PAL20L8A - 2C
PAL20L8A-2M
PAL20L8AC
PAL20L8AM
PAL20R4A-2C
PAL20R4A-2M
PAL20R4AC
PAL20R4AM
PAL20R6A-2C
PAL20R6A -2M
PAL20R6AC
PAL20R6AM
PAL20R8A - 2C
PAL20R8A-2M
PAL20R8AC
PAL20R8AM
PAL22V10-7C
PAL22VlO-7C
PAL22VlO-15C
PAL22VlO-20M
PAL22VIOAC
PAL22V10AC
PAL22VIOAM
PAL22V10AM
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* - meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t
SOIConly
:j: = 32-pin LCC crosses to the 7C198M
1-34
CYPRESS
27S07C+
74S189C
7C189-25C
7C510-75C+
7C510-75C+
7C510-75M+
PALC16L8-20M
PALC16L8-25C
PALC16L8-30M
PALC16L8-35C
PALC16L8-40M
PALC16L8-25C
PALC16L8-30M
PALC16R4-20M
PALC16R4-25C
PALC16R4-30M
PALC16R4-25C
PALC16R4-40M
PALC16R4-25C
PALC16R4-30M
PALC16R6-20M
PALC16R6-25C
PALC16R6-30M
PALC16R6-25C
PALC16R6-40M
PALC16R6-25C
PALC16R6-30M
PALC16R8-20M
PALC16R8-25C
PALC16R8-30M
PALC16R8-25C
PALC16R8-40M
PALC16R8-25C
PALC16R8-30M
PLDCZOGlO-25C
PLDC20GlO-30M
PLDC20G10-35C
PLDC20G10- 30M
PLDC20GlO-25C'
PLDC20GlO-30M
PLDC20GlO-25C'
PLDC20GlO-30M
PLDCZOGlO-25C'
PLDC20G 10-30M
PLDC20GlO-25C'
PLDC20GlO-30M
PLDCZOGlO-25C'
PLDC20GlO-30M
PLDC20G10-25C'
PLDC20GlO-30M
PLDC20G 10-25C
PLDC20G10-30M
PLDC20GlO-25C
PLDC20GIO-30M
PALC22V10D-7C'
PAL22VlOC-7C "
PALC22VlOB-15C I ,
PALC22V10B-20N'
PALC22V10-25C i'
PALC22V10L-25CI
PALC22VlO-25M],
PALC22V10-30M]
I
,-
·~PRESS
iii . .
,
,
TI
PAL22VlOC
PAL22VlOC
SN74ACT7201LA15
SN74ACT7201LA25
SN74ACT7202LA15
SN74ACT7202LA25
SN74ACT7203L15
SN74ACT7203L25
SN74ACT7204L15
SN74ACT7204L25
rOSHIBA
PREFIX:P
PREFIX:TC
PREFIX:TMM
mFFIX:D
W15A-1O
W15A-12
W15A-15
W15A-90
W18-25
W18-35
W18-45
!018-55
!018AP-35
!018AP-45
!068-25
!O68-35
~068-45
~068-55
~069-35
~078-35
~078-45
~078-55
~088-35
~088-45
~088-55
,15
:15-1
:5187T-25
:5187T-30
:5188T-25
:5188T-30
:5257-10
:5257-12
:5257-70
:5257-85
:5328-17
:5328-20
:5328-25
:5328-35
:5328P/J-25
:5328P/J-35
:5329P/J
:5416-35
:5416-45
:5417-25
:5417-35
:5417-45
:5417P/J-15
:5417P/J-20
:5417P/J-25
Product Line Cross Reference
SEMICONDUCTOR
CYPRESS
PALC22VI0-35C
PALC22VI0L- 35C
7C421A-15
7C421-25
7C425A-15
7C425-25
7C429A-15
7C429-25
7C433A-15
7C433-25
CYPRESS
SUFFIX:P
PREFIX:CY
PREFIX:CY
SUFFIX:D
7C128A-55C+
7C128A-55C+
7C128A-55C+
7C128A-55C+
7C128A-25C
7C128A-35C
7C128A-45C
7C128A-55C+
7C128A-35C
7C128A-45C
7C168A-25C
7C168A-35C
7C168A-45C
7C168A-45C
7C169A-35C
7C170A-35C
7C170A-45C
7C170A-45C
7C186-35C
7C186-45C
7C186-55C
2147-55C
2147-55C
7C183-25C
7C183-25C
7C184-25C
7C184-25C
7C199-55C
7C199-55C
7C199-55C
7C199-55C
7C199-15C
7C199-20C
7C199-25C
7C199-35C
7C199-25C
7C199-35C
7C188
7C164-35C
7C164-45C
7C166-25C
7C166-35C
7C166-45C
7C166-15C
7C166-20C
7C166-25C
TOSHIBA
55417P/J-35
55464-17
55464-20
55464-25
55464-35
55464P/J-25
55464P/J-35
55465-17
55465-20
55465-25
55465-35
55465P/J - 25
55465PIJ - 35
5561-45
5561-55
5561-70
5561P/J-45
5561P/J-55
5561P/J-70
5562-35
5562-45
5562-55
5562P/J-35
5562P/J-45
5562P/J-55
5563-10
5563-12
5563-15
5565-10
5565-12
5565-15
5588P/J-20
5588P/J-25
5589P/J-25
55B328-12
55B328-15
55B464-12
55B464-15
55B465-12
55B465-15
CYPRESS
7C166-35C
7B194-15C
7C194-20C
7C194-25C
7C194-35C
7C194-25C
7C194-35C
7B196-15C
7C196-20C
7C196-25C
7C196-35C
7C195-25C
7C195-35C
7C187-45C+
7C187-45C+
7C187-45C+
7C187-45C
7C187-35C
7C187-45C
7C187-35C
7C187-45C
7C187-45C
7C187-45C
7C187-45C
7C187-45C
7C185-55C
7C185-55C
7C185-55C
7C186-55C
7C186-55C
7C186-55C
7C185-20C
7C185-25C
7C182-25C
7B199-12C
7B199-15C
7B194-12C
7B194-15C
7B196-12C
7B196-15C
VTI (VLSI)
PREFIX:VL
PREFIX:VT
2010-65
2010-70
2010-90
2130-lOC
2130-12C
2130-15C
7132-55
7132-55C
7132-70
7132-70C
7132-90C
7132A-25C
7132A-30C
7132A-35
7132A-35C
7132A-45
7132A-45C
7142-55
CYPRESS
PREFIX:CY
PREFIX:CY
7C510-65C
7C51O-65C
7C510-75C
7C130-55C
7C130-55C
7C130-55C
7C132-55C
7C132-55C
7C132-55C
7C132-55C
7C132-55C
7C132-25C
7C132-25C
7C132-35C
7C132-35C
7C132-45C
7C132-45C
7C142-55C
1-35
VTI (VLSI)
7142-55C
7142-70
7142-70C
7142-90C
7142A-25C
7142A-30C
7142A-35
7142A-35C
7142A-45
7142A-45C
CYPRESS
7C142-55C
7C142-55C
7C142-55C
7C142-55C
7C142-25C
7C142-25C
7C142-35C
7C142-35C
7C142-45C
7C142-45C
WSI
PREFIX:WS
SUFFIX:C
SUFFIX:D
SUFFIX:M
SUFFIX:P
29COIC
57C45-25C
57C45-25M
57C45-35C
57C45-35M
57C45-45C
57C45-45M
57C49B-35C
57C49B-45C
57C49B-45M
57C49B-55C
57C49B-55M
57C49B-70C
57C49B-70M
57C49C-25C
57C49C-35C
57C49C-45C
57C49C-45M
57C49C-55C
57C49C-55M
57C49C-70C
57C49C-70M
57C51C-45C
57C51C-45M
57C51C-55C
57C51C-55M
57C51C-70C
57C51C-70M
57C71C-35C
57C71C-45C
57C71C-55C
57C71C-55M
57C71C-70C
57C71C-70M
57C191B-35C
57C191B-35M
57C191B-45C
57C191B-45M
57C191B-50M
57C191B-55C
57C191B-55M
57C191C-25C
57C191C-35C
57C191C-45C
57C191C-45M
CYPRESS
PREFIX:CY
PREFIX:CY
PREFIX:CY
SUFFIX:P
PREFIX:CY
7C901-31C
7C245A-25C
7C245A-25M
7C245A-35C
7C245A-35M
7C245A-45C
7C245A-45M
7C263/4-35C
7C263/4-45C
7C263/4-45C
7C263/4-55C
7C263/4-55C
7C263/4-55C
7C263/4-55C
7C263/4-25C
7C263/4-35C
7C263/4-45C
7C263/4-45C
7C263/4-55C
7C263/4-55C
7C263/4-55C
7C263/4-55C
7C251/4-45C
7C251/4-45M
7C251/4-55C
7C251/4-55M
7C251/4-55M
7C251/4-55M
7C271-35C
7C271-45C
7C271-55C
7C271-55M
7C271-55M
7C271-55M
7C292-35C
7C292-35M
7C292-35C
7C292-35M
7C292A-50M
7C292A-50C
7C292A-50M
7C292A-25C
7C292A-35C
7C292-35C
7C292-35M
II
0
u..
~
ZO i~PRFSS
Product Liue Cross Reference
~.iF' SEMlCONDUcrOR
WSI
57C191C-55C
57C191C-55M
57C256F-35C
57C256F-45C
57C256F-55C
57C256F-55M
57C29IB-35C
57C29IB-35M
57C29IB-45C
57C29IB-45M
57C29IB-50M
57C29IB-55C
57C29IB-55M
57C291C-25C
57C291C-35C
57C291C-45C
57C291C-45M
57C291C-55C
57C291C-55M
57C64F-55C
5901C
5901M
5910AC
5910AM
59510
59516
59517
CYPRESS
7C292-50C
7C292-50M
7C274-35C
7C274-45C
7C274-55C
7C274-55M
7C291-35C
7C291-35M
7C291-35C
7C291-35M
7C291-50M
7C291-50C
7C291-50M
7C291A-25C
7C291A-35C
7C291-35C
7C291-35M
7C291-50C
7C291-50M
7C266-55C
2901CC+
2901CM+
7C91O-40C
7C910-46M
7C510
7C516-45C
7C517-45C
Document # 38-00238
Note: Unless otherwise noted, product meets all performance specs and is within 10 rnA on Icc and 5 rnA on ISB
+ = meets all performance specs but may not meet Icc or ISB
* - meets all performance specs except 2V data retention-may not meet Icc or ISB
functionally equivalent
t
SOIConly
:j: = 32-pin LCC crosses to the 7C198M
1-36
~
INFO
Ii
SRAMs
Ij
PROMs
PlDs
I
Ii
FIFOs
Ii
lOGIC
II
DATACOM
Ii
MODULES
':i
ECl
EI
BUS
lin
MiliTARY
Iii
TOOLS
It1'
QUALITY
Ii'
PACKAGES
I"
~~PRFSS
~_,
Section Contents
SEMICONDUcrOR
Static RAMs (Random Access Memory)
Device Number
CY7C101A
CY7CI02A
CY7C106A
CY7CI07A
CY7CI09A
CY7C123
CY7C128A
CY7C130
CY7C131
CY7C140
CY7C141
CY7C132
CY7C136
CY7C142
CY7C146
CY7B134
CY7B135
CY7B1342
CY7B138
CY7B139
CY7B144
CY7B145
CY7C148
CY7C149
CY7C150
CY7B161
CY7B162
CY7C161
CY7C162
CY7C161A
CY7C162A
CY7BI64
CY7B166
CY7C164
CY7C166
CY7C164A
CY7C166A
CY7C167A
CY7C168A
CY7C169A
CY7C170A
CY7CI71A
CY7CI72A
CY7B173
CY7B174
CY7B173A
CY7B174A
CY7B175
CY7C178
CY7C179
CY7B180
Page Number
Description
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
256K x 4 Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
256K x 4 Static RAM .......................................................... 2-9
IMx 1 Static RAM ........................................................... 2-17
128Kx 8 Static RAM ......................................................... 2-24
256K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-32
2K x 8 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-38
lKx 8 Dual-Port Static RAM .................................................. 2-45
2-45
lK x 8 Dual-Port Static RAM
2-45
lK x 8 Dual-Port Static RAM
2-45
lKx 8 Dual-Port Static RAM
2-58
2K x 8 Dual-Port Static RAM
2-58
2K x 8 Dual-Port Static RAM
2-58
2Kx 8 Dual-Port Static RAM
2-58
2Kx 8 Dual-Port Static RAM
2-71
4K x 8 Dual-Port Static RAM
2-71
4Kx 8 Dual-Port Static RAM
4K x 8 Dual-Port Static RAM with Semaphores ................................... 2-71
4K x 8 Dual-Port Static RAM with Semaphores, INT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-83
4K x 9 Dual-Port Static RAM with Semaphores, INT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-83
8Kx 8 Dual-Port Static RAM with Semaphores, INT, and BUSy ..................... 2-99
8K x 9 Dual-Port Static RAM with Semaphores, INT, and BUSY. . . . . . . . . . . . . . . . . . . .. 2-99
lKx 4 Static RAM .......................................................... 2-115
lKx 4 Static RAM .......................................................... 2-115
lK x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-122
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-130
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 -130
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-137
16K x 4 Static RAM Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-137
16Kx4 Static RAM Separate I/O .............................................. 2-145
16Kx 4 Static RAM Separate I/O .............................................. 2-145
16Kx4 Static R/W RAM ..................................................... 2-154
16K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-154
16K x 4 Static RAM ......................................................... 2-160
16K x 4 Static RAM with Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-160
16K x 4 Static RAM ........ ;................................................ 2-167
16K x 4 Static RAM with Output Enable ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-167
16KxlStaticRAM ......................................................... 2-175
4Kx4R/WRAM ........................................................... 2-182
4Kx 4 R/W RAM ........................................................... 2-182
4K x 4 Static R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-190
4K x 4 Static R/W RAM Separate I/O .......................................... 2-195
4K x 4 Static R/W RAM Separate I/O .......................................... 2-195
32K x 9 Synchronous Cache R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2- 203
32Kx 9 Synchronous Cache R/W RAM ......................................... 2-203
32K x 9 Synchronous Cache R/W RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-212
32Kx 9 Synchronous Cache R/W RAM ......................................... 2-212
32Kx 9 Synchronous Pentium CPU Cache R/W RAM ............................ 2-224
32Kx 18 Synchronous Cache RAM ............................................ 2-236
32K x 18 Synchronous Cache RAM ............................................ 2-236
4Kx 18 Cache Tag ........................................................... 2-248
Section Contents
Static RAMs (Random Access Memory) (continued)
Page Number
Device Number
Description
CY7B181
CY7C182
CY7B185
CY7C185
CY7C185A
CY7C187
CY7C187A
CY7C188
CY7B191
CY7B192
CY7C191
CY7C192
CY7B194
CY7B195
CY7B196
CY7C194
CY7C195
CY7C196
CY7C197
CY7B199
CY7C199
CY7CI001
CY7C1002
CY7C1006
CY7C1007
CY7C1009
CY7C1031
CY7C1032
CY7BI051
CY7B1061
CY7B1055
CY7BI065
CY7BI094
CY7B1095
CY7BI096
CY7BI099
CY7C1331
CY7C1332
CY7C1378
CY7C1379
CY7C1388
CY7C1399
4K x 18 Cache Thg .......................................................... .
8K x 9 Static R/W RAM ..................................................... .
8K x 8 Static RAM ......................................................... .
8K x 8 Static RAM ......................................................... .
8K x 8 Static RAM ......................................................... .
64K x 1 Static RAM ........................................................ .
64K x 1 Static RIW RAM .................................................... .
32K x 9 Static RAM ........................................................ .
64K x 4 Static RIW RAM with Separate I/O .................................... .
64K x 4 Static R/W RAM with Separate I/O .................................... .
64K x 4 Static RAM with Separate I/O ......................................... .
64K x 4 Static RAM with Separate I/O ......................................... .
64K x 4 Static RIW RAM .................................................... .
64K x 4 Static R/W RAM with Output Enable .................................. .
64K x 4 Static RIW RAM with Output Enable .................................. .
64K x 4 Static RAM ........................................................ .
64K x 4 Static R/W RAM with Output Enable .................................. .
64K x 4 Static RIW RAM with Output Enable .................................. .
256K x 1 Static R/W RAM ................................................... .
32K x 8 Static RAM ........................................................ .
32K x 8 Static RAM ........................................................ .
256K x 4 Static RAM with Separate I/O ........................................ .
256K x 4 Static RAM with Separate I/O ........................................ .
256K x 4 Static RAM ....................................................... .
1M x 1 Static RAM ......................................................... .
128K x 8 Static RAM ....................................................... .
64K x 18 Synchronous Cache RAM ........................................... .
64K x 18 Synchronous Cache RAM ........................................... .
64Kx 18 Synchronous Pipelined Cache RIW RAM .............................. .
128K x 18 Synchronous Pipelined Cache R/W RAM ............................. .
32K x 36 Synchronous Pipelined Cache R/W RAM .............................. .
64K x 36 Synchronous Pipelined Cache R/W RAM .............................. .
64K x 4 Static R/W RAM .................................................... .
64K x 4 Static R/W RAM .................................................... .
64Kx 4 Static RIW RAM .................................................... .
32K x 8 Static R/W RAM .................................................... .
64K x 18 Synchronous Cache 3.3V RAM ....................................... .
64K x 18 Synchronous Cache 3.3V RAM ....................................... .
32K x 18 Synchronous Cache 3.3V RAM ....................................... .
32K x 18 Synchronous Cache 3.3V RAM ....................................... .
3.3V 32K x 9 Static RAM .................................................... .
3.3V 32K x 8 Static RAM .................................................... .
2-248
2-268
2-273
2-278
2-287
2-295
2-302
2-310
2-317
2-317
2-323
2-323
2-331
2-331
2-331
2-339
2-339
2-339
2-348
2-356
2-362
2-371
2-371
2-378
2-385
2-391
2-398
2-398
2-410
2-410
2-411
2-411
2-412
2-412
2-412
2-419
2-425
2-425
2-437
2-437
2-438
2-444
II
U)
:E
ct
a::
en
CY7CIOIA
CY7CI02A
PRELIMINARY
CYPRESS
SEMICONDUCTOR
256K X 4 Static RAM
with Separate I/O
Features
Functional Description
• High speed
- tAA = 12 ns
The CY7C101A and CY7CI02A are highperformance CMOS static RAMs organized as 262,144 x 4 bits with separate I/O.
Easy memory expansion is provided by active LOW chip enable (CE) and threestate drivers. Both devices have an automatic power-down feature, reducing the
power consumption by more than 65%
when deselected.
Writing to the device is accomplished by
taking both chip enable (CE) and write enable (WE) inputs LOW Data on the four
input pins (10 through 13) is written into the
memory location specified on the address
pins (Ao through A17)'
Reading the device is accomplished by taking chip enable (CE) LOW while write en-
• Transparent write (7CIOIA)
• CMOS for optimum speed/power
• Low active power
- 910mW
• Low standby power
- 275mW
• 2.0V data retention
- 100llW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
able (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the four data output pins (00
through 03).
The data output pins on the CY7C101A
and the CY7CI02A are placed in a highimpedance state when the device is deselected (CE HIGH). The CY7C102~s outputs are also placed in a high~edance
state during a write operation (CE and WE
LOW). In a write operation on the
CY7C101A, the output pins will carry the
same data as the inputs after a specified
delay.
The CY7CI0IAand CY7CI02Aare available in standard 400-mil-wide DIPs and
SOJs.
Pin Configuration
Logic Block Diagram
DIP/SOJ
Top View
C101A-2
ISelection Guide
Maximum Access Time (ns)
Maximum O~erating
Current (rnA
Maximum Standby
Current (rnA)
Commercial
Military
Commercial
Military
7CIOIA-12
7CI02A-12
12
165
50
2-1
7CIOIA-15
7CI02A-15
15
155
165
40
40
7CIOIA-20
7CI02A-20
20
140
150
30
30
7CI01A-25
7CI02A-25
25
130
140
30
30
7CIOIA-35
7CI02A-35
35
125
135
25
25
•
CY7CIOlA
CY7CI02A
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage on Vee Relative to GND[1] - 0.5V to + 7.0V
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto + 70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
DC Voltage ApBlied to Outputs
in High Z State 1] ............... ,. - O.5V to Vee + O.5V
DC Input Voltagd1] ............... - O.5V to Vee + O.5V
Current into Outputs (LOW) ..................... 20 rnA
Commercial
Military[2]
Electrical Characteristics Over the Operating Range[3]
7CIOIA-12
7CI02A-12
Parameter
VOH
VOL
VIR
VIL
IIX
loz
los
lee
ISB1
ISB2
Description
Min.
Test Conditions
Output HIGH
Vee = Min.,
Voltage
IOH = - 4.0 rnA
Output LOW Voltage Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
Input LOWVoltage[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Currend4]
VeeOperatingSupply
Current
GND.s VI.s Vee
GND.s VI.s Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
Com'l
Max.
2.4
Min.
Max.
2.4
Unit
V
V
V
V
JAA
JAA
-300
-300
-300
rnA
165
155
140
rnA
165
150
40
30
40
30
2
2
2
2
50
Automatic CE Power- Max. Vee,
Down Current
CE ~ Vee - 0.3v,
- CMOS Inputs
VIN ~ Vee - 0.3V
or VIN .s 0.3v, f=O
2
2-2
Max.
7CIOIA-20
7CI02A-20
0.4
0.4
0.4
2.2 Vee + 0.3 2.2 Vee + 0.3 2.2 Vee + 0.3
-0.3
-0.3
-0.3
0.8
0.8
0.8
-1
-1
-1
+1
+1
+1
-5
-5
-5
+5
+5
+5
Mil
Mil
Min.
2.4
Automatic CE Power- Max. Vee,
Com'l
Down Current
CE~ VIR,
-TTL Inputs
VIN~ VIR or
Mil
VIN .s VIL, f = fMAX
Com'l
7CIOIA-15
7CI02A-15
rnA
rnA
PRELIMINARY
CY7CIOIA
CY7CI02A
Electrical Characteristics Over the Operating Rangef3] (continued)
7CIOIA-35
7CI02A-35
7CIOIA-25
7CI02A-25
Parameter
Description
Min.
Test Conditions
VOH
Output HIGH
Voltage
Vee = Min.,
IOH = - 4.0 rnA
VOL
VIH
Output LOW Voltage
Vee
= Min., IOL = 8.0 rnA
Input HIGH Voltage
Input LOW Voltagefl]
VIL
Max.
Min.
2.4
Max.
Unit
2.4
0.4
V
0.4
V
2.2
-0.3
Vee+ 0 .3
0.8
2.2
-0.3
Vee + 0.3
0.8
V
V
IIX
Input Load Current
GND~VI~Vee
-1
+1
-1
+1
Ioz
Output Leakage
Current
GND ~ VI~ Vee,
Output Disabled
-5
+5
-5
+5
!1A
!1A
los
Output Short
Circuit Current[4]
Vee
-300
-300
rnA
IcC
Vee Operating Supply
Current
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
Com'l
130
125
rnA
Mil
140
135
ISBl
Automatic CE PowerDown Current
-TIL Inputs
Com'l
30
25
Mil
30
25
Com'l
2
2
Mil
2
2
Max. Vee,
CE~ VIH,
VIN~ VIHor
VIN ~ VIL, f = fMAX
Automatic CE PowerDown Current
- CMOS Inputs
ISB2
= Max., VOUT = GND
Max. Vee,
CE~ Vee - 0.3v,
VIN ~ Vee - O.3V
or VIN ~ 0.3V, f=O
rnA
rnA
Capacitance[5]
Parameter
CIN: Addresses
Max.
Test Conditions
Description
Input Capacitance
TA
= 25°C, f = 1 MHz,
= 5.0V
Vee
CIN: Controls
Output Capacitance
COUT
Unit
7
pF
10
pF
10
pF
Notes:
1.
2.
3.
VIdmin.) = -2.0V for pulse durations of less than 20 ns.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
TI
AC Test Loads and Waveforms
R1 4800
OUTP~~
~~
INCLUDING
JIG AND
SCOPE
I-
~
2550
OUTP~~
5~
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
5.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
ALL INPUT PULSES
R1 4800
-
-
sn
4.
I-
3.0V---90%
~
2550
-
-
(b)
C101A-3
THEVENIN EQUIVALENT
OUTPUT~
1.73V
2-3
GND
C101A-4
•
CY7CIOIA
CY7CI02A
PRELIMINARY
Switching Characteristics Over the Operating Range[3, 6]
Parameter
Description
7CIOIA-12
7CI02A-12
Min. Max.
7CIOIA-15
7CI02A-15
Min. Max.
7CIOIA-20
7CI02A-20
Min. Max.
7CIOIA-25
7CI02A-25
Min. Max.
7CIOIA-35
7CI02A-35
Min. Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address
Change
tACE
CE LOW to Data Valid
tLzCE
CE LOW to Low Z[7]
tHZCE
tpu
CE HIGH to High Z[7,8]
CE LOW to Power-Up
12
15
20
15
12
3
3
3
12
3
0
3
0
10
20
35
ns
10
ns
ns
ns
0
25
ns
ns
3
0
0
15
12
25
8
7
35
3
3
3
ns
35
25
20
15
3
6
CE HIGH to Power-Down
tpD
WRITE CYCLE[9]
25
20
35
ns
twc
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write
End
10
12
15
20
25
ns
tHA
Address Hold from Write
End
0
0
0
0
0
ns
tSA
Address Set-Up to Write
Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLzWE
WE HIGH to Low Z[7]
3
3
3
3
3
tHZWE
WE LOW to High Z[7,8]
6
7
8
10
10
ns
tDWE
WE LOW to Data Valid
(7C101A)
12
15
20
25
35
ns
tDCE
CE LOW to Data Valid
(7C101A)
12
15
20
25
35
ns
tADV
Data Valid to Output Valid
(7C101A)
12
15
20
25
35
ns
Notes:
6. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLzWE for any given device.
8. tHzCE, and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 m V from
steady-state voltage.
9.
2-4
ns
The internal write time of the memory is defined by the overlap of CE
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of any of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
CY7CIOIA
CY7CI02A
.....::::=-a...
ge ..,,~
CYPRESS
PRELIMINARY
~ iF SEMICONDUCIOR
Data Retention Characteristics Over the Operating Range
Commercial
Parameter
Conditions [10]
Description
Max.
2.0
V cc for Retention Data
VDR
Min.
YC.c =
ICCDR
Data Retention Current
tCDR[5]
Chip Deselect to Data Retention Time
tR[5]
Operation Recovery Time
VDR = 2.0V,
CE ~ Vcc - 0.3V,
VIN ~ Vcc - 0.3 or
VIN .sO.3V
Military
Min.
Max.
Unit
2.0
V
50
70
J.IA
0
0
ns
tRC
tRC
ns
Note:
10. No input may exceed Vee
+ o.sY.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR~2V
f~DR-
&\~
C101A-S
Switching Waveforms
Read Cycle No.lfll, 12]
*-
~v:: JXX1
tRC
ADDRESS
--~
DATA OUT
tAA
PREVIOUS DATA
*================DA=I=A=V=A=L=ID===========
C101A-6
Read Cycle No. 2(12, 13]
)K
ADDRESS
tRC
~~
/'?
tACE
HIGH IMPEDANCE
DATA OUT
tLZCE
~OO%
-tHZCE-
////1 V
'''''''''-r'\.
I+--tpu
VCC
SUPPLY _____________
CURRENT
"
DATA VALID
HIGH
IMPEDAN CE
/
-tpD
~ CC
I
50%
ISB
C101A-7
2-5
•
IDJ~=
-=-" ,
PRELIMINARY
CY7CIOIA
CY7CI02A
SEMICONDUCI'OR
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[9, 14]
twc
tSCE
tAW
tHA
tpWE
tSD
DATA VALID
DATA IN
DATA OUT
(7C102A)
DATA OUT
(7C101A)
HIGH IMPEDANCE
----------------+----1{",,'--.:..L..~'--~
C101A-8
Write Cycle No.2 (WE Controlled)[9]
~-----------------------------twc----------------------------~
ADDRESS
~-----------------tSCE--------------------~
-----------------~~------tHA
DATA IN
DATA OUT
(7C1 02A)
~"";:'''-~~'--~~:....-1~~'''';:'''-~4'--~~~
DATA OUT
(7C101A)
"-~~'--~~:...._1~~....;:."--~~~~~:....-1~~~"-~~
~-------tADV--------~
C101A-9
Notes:
11. Device is continuously selected, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition Law.
14. If CE goes HIGH simultaneously with WE going HIGH, the output
remains in a high-impedance state (7CI02A only).
2-6
~~
~'.:~
PRELIMINARY
~., ~ONDucrOR
Truth Table
Power
CE
WE
H
X
HighZ
Power-Down
Mode
Standby (ISB)
L
H
Data Out
Read
Active (Icc)
L
L
HighZ
7CI02A: Standard Write
Active (Icc)
L
L
Input Tracking
7C101A: Transparent Writel 15 ]
Active (Icc)
00 - 03
Note:
15. Outputs track inputs after specified delay.
o r d ermg
. I nIiormation
Speed
(ns)
12
15
20
25
35
Speed
(ns)
12
15
20
25
35
Ordering Code
Package
Name
Operating
Range
.,: ,Package'fYpe
Commercial
CY7C101A -12PC
P43
32-Lead (400-Mil) Molded DIP
CY7C101A -12VC
V33
32-Lead (400-Mil) Molded SOJ
CY7CI0IA-15PC
P43
32-Lead (400-Mil) Molded DIP
CY7CI0IA -15VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C101A -15DMB
D44
32-Lead (400-Mil) CerDIP
Military
CY7C101A - 20PC
P43
32-Lead (400-Mil) Molded DIP
Commercial
CY7C101A - 20VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C101A - 20DMB
D44
32-Lead (400-Mil) CerDIP
Military
CY7C101A - 25PC
P43
32-Lead (400-Mil) Molded DIP
Commercial
CY7C101A - 25VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C101A-25DMB
D44
32-Lead (400-Mil) CerDIP
Military
CY7C101A - 35PC
P43
32-Lead (400-Mil) Molded DIP
Commercial
CY7C101A-35VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C101A-35DMB
D44
32-Lead (400-Mil) CerDIP
Ordering Code
Package
Name
Commercial
Military
Package 'fYpe
Operating
Range
Commercial
CY7C102A -12PC
P43
32-Lead (400-Mil) Molded DIP
CY7C102A -12VC
V33
32-Lead (400-Mil) Molded SOJ
Commercial
CY7C102A -15PC
P43
32-Lead (400-Mil) Molded DIP
CY7C102A -15VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C102A-15DMB
D44
32-Lead (400-Mil) CerDIP
Military
CY7C102A - 20PC
P43
32-Lead (400-Mil) Molded DIP
Commercial
CY7C102A - 20VC
V33
32-Lead (400-Mil) Mol~ed SOJ
CY7C102A-20DMB
D44
32-Lead (40Q-Mil) CerDIP
Military
CY7C102A - 25PC
P43
32-Lead (400-Mil) Molded DIP
Commercial
CY7C102A - 25VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C102A-25DMB
D44
32-Lead (400-Mil) CerDIP
CY7C102A - 35PC
P43
32-Lead (400-Mil)
CY7C102A - 35VC
V33
32-Lead (400-Mil) Molded SOJ
CY7C102A - 35DMB
D44
32-Lead (400-Mil) CerDIP
2-7
~olded
Military
DIP
Commercial
Military
CY7CIOIA
CY7CI02A
•
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1; 2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Switching Characteristics
Subgroups
Parameter
READ CYCLE
7, 8, 9, 10, 11
tRC
tAA
7, 8,9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7,8,9,10,11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
. 7, 8, 9, 10, 11
tHA
tSA
7, 8, 9, 10, 11
tpWE
7,8,9,10,11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
tDWE[16]
7, 8, 9, 10, 11
tADV[16]
7, 8, 9, 10, 11
Note:
16. 7C101A only.
Document #: 38-00231
2-8
CY7CIOIA
CY7CI02A
PRELIMINARY
CY7CI06A
256K X 4 Static RAM
Features
Functional Description
• High speed
- tAA= 12ns
The CY7CI06A is a high-performance
CMOS static RAM organized as 262,144
words by 4 bits. Easy memory expansion is
provided by an active LOW chip enable
(CE), an active LOW output enable (OE),
and three-state drivers. The device has an
automatic power-down feature that reduces power consumption by more than
65% when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW Data on the four I/O
pins (1/00 through 1/03) is then written
into the location specified on the address
pins (Ao through A17).
• CMOS for optimum speed/power
• Low active power
- 910mW
• Low standby power
- 275mW
• 2.0V data retention
- 100 IlW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
Logic Block Diagram
Reading from the device is accomplished
by ta~ chip enable (CE) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the
contents of the memory location specified
by the address pins will appear on the four
I/O pins.
The four input/output pins (1/00 through 1/
03) are placed in a high-impedance state
when the device is deselect~CE HIGH),
the outputs are disabled (OE HIGH), or
during a write operation (CE and WE
LOW).
The CY7C106A is available in standard
400-mil-wide DIPs and SOJs.
Pin Configuration
DIP/SOJ
Top View
Ao
A1
A2
A3
~
A5
As
A1
A2
A3
~
~
A7
As
Ag
A7
As
Ag
a::
W
Cl
1/03
0
1/°2
~
DE
0
w
GND
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Cl
Vee
An
A16
A15
A14
A13
A12
~B
1/°3
1/°2
1/01
!LQp
WE
C106A-2
3:
1/°1
0
a::
1/°0
CE
WE
DE
C106A-1
Selection Guide
Maximum Access Time (ns)
7C106A-12
7C106A-15
7C106A-20
7C106A-25
7C106A-35
12
15
25
155
20
140
35
125
165
40
40
Maximum 0serating
Current (rnA
Commercial
Military
165
Maximum Standby
Current (rnA)
Commercial
50
Military
2-9
150
130
140
135
30
30
25
30
30
25
•
PRELIMINARY
CY7CI06A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage.Thmperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage on Vee Relative to GND[1]
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
- O.5V to +7.0V
Ambient
Temperatnre[2]
Vee
OOeto +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
DC Voltage ApBlied to Outputs
in High Z State 1] ................. - 0.5V to Vee + 0.5V
DC Input Voltagd 1] ............... - 0.5V to Vee + O.5V
Commercial
Military
Current into Outputs (LOW) ..................... 20 rnA
Electrical Characteristics Over the Operating Rangd 3]
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltagd 1]
IIX
Input Load Current
GND.s VI.s Vee
Ioz
Output Leakage Current
GND.s VI.s Vee,
Output Disabled
los
Output Short
Circuit Currentl4]
Vee Operating
SupplyCurrent
Vee = Max., VOUT = GND
lee
7CI06A-12
7CI06A-15
7CI06A-20
Min.
Min.
Min.
Max.
2.4
2.4
0.4
2.2
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
Com'l
Com'l
- 0.3
Vee
+ 0.3
0.8
-1
+1
-5
+5
Automatic CE
Power-Down Current
-TTL Inputs
Max. Vee, CE~ VIH,
VIN ~ VIH or VIN .s VIL,
f = fMAX
ISB2
Automatic CE
Power-Down Current
- CMOS Inputs
Max. Vee,
CE ~ Vee - 0.3v,
VIN ~ Vee - 0.3V
or VIN .s 0.3v, f=O
Mil
Unit
V
0.4
V
V
2.2
Vee
+ 0.3
- 0.3
Vee
+ 0.3
0.8
- 0.3
0.8
V
-1
+1
-1
+1
!-tA
-5
+5
-5
+5
IlA
-300
-300
rnA
165
155
140
rnA
165
150
40
30
40
30
2
2
2
2
50
Mil
Com'l
2.4
0.4
2.2
Max.
-300
Mil
ISB1
Max.
2
rnA
rnA
Notes:
1.
2.
3.
VIL (min.) = - 2.0V for pulse durations of less than 20 ns.
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing information.
4.
2-10
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
PRELIMINARY
CY7CI06A
Electrical Characteristics Over the Operating Rangd 3]
7CI06A-25
Parameter
Description
Test Conditions
VOH
VOL
VIR
VIL
IIX
loz
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagd 1]
Input Load Current
Output Leakage Current
los
Output Short
Circuit Current[4]
Vee Operating
SupplyCurrent
lee
ISBI
ISB2
Min.
7CI06A-35
Max.
Min.
Max.
0.4
0.4
2.2
-0.3
-1
-5
GND~VI~Vee
GND~ VI~ Vee,
Output Disabled
Vee = Max., VOUT = GND
Unit
2.4
2.4
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
2.2
- 0.3
-1
-5
Vee + 0.3
0.8
+1
+5
Vee + 0.3
0.8
V
V
V
V
+5
JlA
JlA
-300
-300
rnA
rnA
+1
Vee = Max.,
lOUT = ornA,
f = fMAX = l/tRe
Com'l
130
125
Mil
140
135
Automatic CE
Power-Down Current
-TIL Inputs
Max. Vee, CE~ VIR,
VIN ~ VIR or VIN ~ VIL,
f= fMAX
Com'l
30
25
Mil
30
25
Automatic CE
Power-Down Current
- CMOS Inputs
Max. Vee.
CE ~ Vee - 0.3v,
VIN ~ Vee - O.3V
or VIN ~ 0.3v, f=O
Com'l
2
2
Mil
2
2
rnA
rnA
Capacitance[5]
Parameter
Description
CIN: Addresses
Test Conditions
Input Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
CIN: Controls
Output Capacitance
COUT
Max.
Unit
7
pF
10
pF
10
pF
Note:
5.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
TI TI
R1480Q
OUTP~~
30 pF
INCLUDING
JIG AND
SCOPE
I-=
-=
R2
255Q
OUTP~~
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
R1480Q
I-
-
(b)
3.0V---90%
R2
255Q
Cl06A-3
THEVENIN EQUIVALENT
OUTPUT~
GND
-
1.73V
2-11
Cl0SA-4
•
~
wrCYPR£§
_
_
PRELIMINARY
SEMICONDUCTOR
CY7CI06A
Switching Characteristics Over the Operating Rangd3,6]
Parameter
Description
7CI06A-12
7CI06A-15
7CI06A-20
7CI06A-25
7CI06A-35
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
12
15
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
20
25
35
ns
tDOE
OE LOW to Data Valid
6
7
8
10
10
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7, 8]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
12
20
3
3
3
0
0
6
3
6
8
0
8
12
3
0
25
ns
ns
10
10
0
20
15
ns
10
10
ns
ns
0
3
0
ns
35
3
0
3
7
0
35
25
3
0
7
3
25
20
15
ns
ns
35
ns
WRITE CYCLE[9,1O]
twc
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write End
10
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
2
tHZWE
WE LOW to High Z[7,8]
3
3
6
7
Notes:
6. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOUIOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF
as in part (b) of AC Test Loads. Transition is measured ±500 mV from
steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLzOE, and tHZWE is less than tLZWE for any
given device.
9.
3
8
3
10
ns
10
ns
The internal write time of the memory is defined by the overlap of CE
and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE LOW) is the sum of tHZWE and tso.
2-12
PRELIMINARY
CY7CI06A
Data Retention Characteristics Over the Operating Range
Commercial
Parameter
Conditions[ll]
Description
VDR
Vee for Data Retention
IeeDR
tCDR[S]
Data Retention Current
tR[S]
Operation Recovery Time
Min.
Max.
2.0
Max.
2.0
CE ~ Vee - 0.3V,
VIN ~ Vee - O.3Vor
VIN ~O.3V
Unit
V
70
50
YC.C = VDR = 2.0V,
Chip Deselect to Data Retention Time
Military
Min.
!JA
0
0
ns
tRe
tRe
ns
Note:
11. No input may exceed Vee +O.SY.
Data Retention Waveform
DATA RETENTION MODE
4.5V
Vcc
VOR 2>. 2V
f~DRC106A-5
Switching Waveforms
Read Cycle No. 1[12, 13]
~v:~ =lxx
*-
tRC
ADDRESS
--~
DATA OUT
tAA
PREVIOUS DATA
+1
*===============D=A=TA=V=A=L=ID===========
C106A-6
Read Cycle No.2 (OE Controlled)[13, 14]
)(
ADDRESS
tRC
~~
)~
tACE
~~
/'rf:
tOOE
f4- t HZCE -
~tLZOE-
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
I+-tpu
...J.
t~ZOE
/////v
DATA VALID
""'r"\.
HIGH
IMPEDAN CE
/"'"
~tpo-
50%~
{ ' 50%
ICC
'----- ISS
C106A-7
2-13
II
PRELIMINARY
CY7CI06A
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[15, 16]
~---------------------------twc----------------------------~
ADDRESS
----~--------------------------~~------tSCE------~~--------_+----------~-----------tSA------------~
~---------------------
tAW -----------------------+ot---
~r:~--------tSD--------~
DATA I/O
----------------IC:~-----D-A-I-A-V-A-Ll-D---C106A-8
Write Cycle No.2 (WE Controlled, OE HIGH During Write) [15, 16]
~--------------------------twc------------------------~~
ADDRESS
~~~~~~~-----------------tSCE------------------~
~-------tpWE----------~
-------------~~~
,------------------
~----------tSD----------__~~~
DATAI/O
tHO
DATA VALID
C106A-9
Notes:
12. Device is continuously selected, OE and CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. IfCE goes HIGH simultaneously with WE going HIGH, the outputremains in a high-impedance state.
16. Data I/O is high impedance if OE = VIH.
2-14
~
Y~CYPRFSS
SEMICONDUCTOR
•
PRELIMINARY
F
CY7CI06A
Switching Waveforms
Write Cycle No.3 (WE Controlled, OE LOW)[lO, 16]
II
ADDRESS
~------tSD------~'-~
DATAI/O
DATA VALID
C106A-10
Truth Table
CE
OE
WE
H
X
X
HighZ
L
L
H
Data Out
Read
Active (Icc)
L
X
L
Data In
Write
Active (Icc)
L
H
H
HighZ
Selected, Outputs Disabled
Active (Icc)
Input/Output
Mode
Power-Down
Power
Standby (ISB)
or d ermg
. I norma
Ii
f Ion
Speed
(ns)
12
15
20
25
35
Package
Name
Package 1YPe
Operating
Range
CY7C106A -12PC
P41
28-Lead (400-Mil) Molded DIP
Commercial
CY7CI06A-12VC
V28
28-Lead (400-Mil) Molded SOJ
Ordering Code
CY7C106A -15PC
P41
28-Lead (400-Mil) Molded DIP
CY7C106A -15VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C106A -15DMB
D42
28-Lead (400-Mil) CerDIP
Military
Commercial
Commercial
CY7C106A - 20PC
P41
28-Lead (400-Mil) Molded DIP
CY7C106A - 20VC
V28
28-Lead (400-Mil) Molded SOJ
CY7CI06A-20DMB
D42
28-Lead (400-Mil) CerDIP
Military
CY7C106A - 25PC
P41
28-Lead (400-Mil) Molded DIP
Commercial
CY7CI06A-25VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C106A-25DMB
D42
28-Lead (400-Mil) CerDIP
Military
CY7C106A - 35PC
P41
28-Lead (400-Mil) Molded DIP
Commercial
CY7C106A - 35VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C106A-35DMB
D42
28-Lead (400-Mil) CerDIP
2-15
Military
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBI
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00230
2-16
CY7CI06A
CY7CI07A
PRELIMINARY
1M X 1 Static RAM
Features
Functional Description
• High speed
- tAA = 12ns
• CMOS for optimum speed/power
• Low active power
The CY7C107A is a high-performance
CMOS static RAM organized as 1,048,576
words by 1 bit. Easy memory expansion is
provided by an active LOW chip enable
(CE) and three-state drivers. The device
has an automatic power-down feature that
reduces power consumption by more than
65% when deselected.
-
825mW
• Low standby power
- 275mW
• 2.0V data retention
- IOOIlW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs Law. Data on the input pin
(DIN) is written into the memory location
specified on1:he address pins (Ao through
A19).
Logic Block Diagram
Reading from the device is accomplished
by taking chip enable (CE) LOW while
write enable (WE) remains HIGH. Under
these conditions, the contents of the
memory location specified by the address
pins will appear on the data output
(DOUT) pin.
The output pin (DOUT) is placed in a highimpedance state when the device is deselected(CEHIGH)orduringawriteoperation (CE and WE LOW).
The CY7CI07A is available in standard
400-mil-wide DIPs and SOJs.
Pin Configuration
DIP/SOJ
Top View
vee
A10
A11
A12
A 13
A14
A1S
A9
As
A7
As
As
NC
~
A16
A17
A 18
A 19
A3
A2
A1
Ao
DOUT
WE
GND
DIN
CE
107A-2
107A-1
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Commercial
Maximum Standby
Current (rnA)
Commercial
7CI07A-12
7CI07A-15
7CI07A-20
7CI07A-25
12
15
20
25
35
150
135
125
120
110
145
135
130
120
40
30
25
40
30
30
30
Military
50
Military
2-17
7CI07A-35
25
•
-Y~
~, SEMICONDUCTOR
PRELIMINARY
CY7CI07A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage on Vee Relative to GND[l) - O.5V to +7.0V
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200rnA
Operating Range
Range
DC Voltage APBlied to Outputs
in High Z State 1) ................. - O.5V to Vee + 0.5V
DC Input Voltagel 1) ............... - O.5V to Vee + O.5V
Current into Outputs (LOW) ..................... 20 rnA
Commercial
Military
Ambient
Temperature[2)
Vee
ooe to +70°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics[3) Over the Operating Range
7CI07A-12
Parameter
VOH
VOL
VIH
VIL
IIX
loz
los
lee
ISB1
ISB2
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltagel 1)
Input Load Current
Output Leakage
Current
Output Short
Circuit Currentl4)
Vee Operating
Supply Current
Test Conditions
Min.
Vee = Min., IOH = - 4.0 rnA
0.4
2.2
Vee = Max., VOUT = GND
Vee = Max.,
lOUT = OrnA,
f = fMAX = litRe
Automatic CE
Power-Down
Current
- TTL Inputs
Max.. Vee,
CELVIH,
VINLVIHOr
VINS VIL,
f=fMAX
Automatic CE
Power-Down
Current
- CMOS Inputs
Max. Vee,
CE L Vee - 0.3v,
VIN L Vee -:- O.3Vor
VIN S 0.3v, f=O
Com'l
- 0.3
Vee +
0.3
0.8
-1
-5
+1
+5
Mil
2-18
7CI07A-20
Min.
2.4
0.4
2.2
Max.
2.2
Unit
V
0.4
V
V
V
- 0.3
Vee+
0.3
0.8
- 0.3
Vee +
0.3
0.8
-1
-5
+1
+5
-1
-5
+1
+5
!tA
!tA
- 300
- 300
rnA
150
135
125
rnA
145
135
40
30
40
30
2
2
2
2
50
Mil
Com'l
Max.
-300
Mil
Com'l
7CI07A-15
Min.
2.4
2.4
Vee = Min., IOL = 8.0 rnA
GNDsVIsVee
GNDs VIS Vee,
Output Disabled
Max.
2
rnA
rnA
PRELIMINARY
CY7CI07A
Electrical Characteristics[3] Over the Operating Range (continued)
7CI07A-35
7CI07A-25
Parameter
Description
Test Conditions
Output HIGH
Voltage
Output LOW Voltage
VOR
VOL
VIR
Min.
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating
Supply Current
loz
los
lee
0.4
Vee = Min., IOL = 8.0 rnA
ISBl
ISB2
Unit
Max.
V
2.2
0.4
V
V
2.2
- 0.3
-1
Vee+ 0.3
0.8
+1
- 0.3
-1
Vee+ 0.3
0.8
+1
-5
+5
-5
+5
JlA
JlA
- 300
- 300
rnA
Com'l
120
110
rnA
GND.5VI.5Vee
GND.5 VI.5 Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.,
lOUT = OrnA,
f = fMAX = litRe
Min.
2.4
2.4
Vee = Min., lOR = - 4.0 rnA
Input HIGH Voltage
Input LOW Voltagefl]
VIL
IIX
Max.
Mil
130
120
Automatic CE
Power-Down
Current
- TIL Inputs
Max.. Vee,
CE~ VIR,
VIN ~VIRor
VIN.5 VIL,
f = fMAX
Com'l
30
25
Mil
30
25
Automatic CE
Power-Down
Current
- CMOS Inputs
Max. Vee,
CE~ Vee - 0.3v,
VIN ~ Vee - O.3Vor
VIN.5 0.3v, f=O
Com'l
2
2
Mil
2
2
V
rnA
rnA
Capacitance[5]
Parameter
CIN: Addresses
Description
Input Capacitance
Vee = 5.0V
CIN: Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Output Capacitance
Notes:
1. V IL (min.) = - 2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
4.
5.
2-19
Max.
Unit
7
pF
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
•
1r~
PRELIMINARY
CY7CI07A
AC Test Loads and Waveforms
R1480Q
OUTP:T51
I
30pF
INCLUDING _
JIG AND
SCOPE
(a)
Equivalent to:
R1480Q
R2
2550
OUTP:TI
I
_
-
5pF
INCLUDING _
JIG AND
SCOPE
(b)
ALL INPUT PULSES
3.0V ----_.Ir"=----~
GND
R2
2550
_
-
107A-4
107A-3
THEVENIN EQUIVALENT
OUTPUT ---'11>1'''''''
().O
167Q
- - - - 0 0 1.73V
Switching Characteristics[3,6] Over the Operating Range
Parameter
READ CYCLE
Description
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address
Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
7CI07A-12
7CI07A-15
7CI07A-20
7CI07A-25
7CI07A-35
Min.
Min.
Min.
Min.
Min.
Max.
12
Max.
15
20
12
3
15
3
15
3
0
CE HIGH to Power-Down
tpD
WRITE CYCLE[9]
20
0
0
12
25
15
0
20
35
ns
10
ns
35
ns
ns
0
25
ns
ns
3
10
Unit
ns
35
3
3
8
7
Max.
35
25
3
3
6
Max.
25
20
3
12
3
Max.
ns
twc
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAw
Address Set-Up to Write
End
10
12
15
20
25
ns
tHA
Address Hold from Write
End
0
0
0
0
0
ns
tSA
Address Set-Up to Write
Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
3
3
tHzWE
WE LOW to High Z[7, 8]
6
7
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IorJ10H and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHzCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 mV from
steady-state voltage.
9.
2-20
8
10
ns
10
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and
the transition of any of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
PRELIMINARY
CY7CI07A
Data Retention Characteristics Over the Operating Range
Commercial
Conditions[lO]
Description
Parameter
Vee for Data Retention
IeeDR
Data Retention Current
teDR[S]
Chip Deselect to Data Retention Time
Vee = VDR = 2.0Y,
CE L Vee - 0.3Y,
VIN L Vee - 0.3 or
VIN~O.3V
Operation Recovery Time
Note:
10. No input may exceed Vee
Max.
Military
Min.
Max.
Unit
2.0
2.0
VDR
tR[S]
Min.
V
50
70
!lA
0
0
ns
tRe
tRe
ns
+ O.SY.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR~2V
f~DR-
t\~~
107A-5
Switching Waveforms
Read Cycle No. 1[11, 12]
§
ADDRESS
--DATA OUT
tRC
·1
~ to"'~
PREVIOUS DATA VALID Jxxx)k================DA=:r=A=V=A=L=ID===========
107A-6
Read Cycle No. 2[12, 13]
)(
ADDRESS
~
tRC
/~
~
_tH~Ed
tACE
tLZCE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
//////
DATA VALID
""",,1\.
HIGH
IMPEDANCE
/
-tpD_
-tpu-
}~ 50%
50%~
- I CC
' - - - - I S8
107A-7
Notes:
11. Device is continuously selected, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
2-21
II
PRELIMINARY
CY7CI07A
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[14]
~--------------------------twc------------------------~~
ADDRESS
------~.------------tSCE----------~~
~--------------~------~w------------------~~~~~~~~-~~------------tpWE------------------~
------------------
DATA IN
~--------------------tSD------~~
DATA VALID
HIGH IMPEDANCE
DATA OUT
107A-8
Write Cycle No.2 (WE Controlled)[14]
~-------------------------twc--------------------------~
~----------------tSCE--------------------~
______~------------------~-~w------------------~4--~~:::::::_tS_A_-_-_-_-.:_-_-_-_~~.,J,"~l'"\.. 1oIf----- tpWE -------.I ,.-___________________
DATA IN
DATA VALID
t
HZWE
=!
-J)
DATA OUT ________________D_A_TA
__
U_N_D_EF_I_NE_D______________
<,-------
tLZWE ----I
HIGH IMPEDANCE
107A-9
Note:
14. IfCEgoesHIGHsimuitaneousiywith WE going HIGH, theoutputremains in a high-impedance state.
Truth Table
CE
WE
H
X
HighZ
Power-Down
Standby (ISH)
L
H
Data Out
Read
Active (Icc)
L
L
HighZ
Write
Active (Icc)
DOUT
Mode
Power
2-22
PRELIMINARY
Ordering Information
Speed
(ns)
12
15
20
25
35
Ordering Code
Package
Name
Package 1Ype
Operating
Range
Commercial
CY7ClO7A -12PC
P41
28-Lead (400-Mil) Molded DIP
CY7C107A -12VC
V28
28-Lead (400-Mil) Molded SOJ
CY7ClO7A -15PC
P41
28-Lead (400-Mil) Molded DIP
CY7ClO7A -15VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C107A-15DMB
D42
28-Lead (400-Mil).CerDIP
Military
Commercial
Commercial
CY7C107A - 20PC
P41
28-Lead (400-Mil) Molded DIP
CY7ClO7A-20VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C107A-20DMB
D42
28-Lead (400-Mil) CerDIP
Military
CY7ClO7A -25PC
P41
28-Lead (400-Mil) Molded DIP
Commercial
CY7C107A-25VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C107A-25DMB
D42
28-Lead (400-Mil) CerDIP
Military
CY7ClO7A - 35PC
P41
28-Lead (400-Mil) Molded DIP
Commercial
CY7C107A - 35VC
V28
28-Lead (400-Mil) Molded SOJ
CY7C107A-35DMB
D42
28-Lead (400-Mil) CerDIP
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, lO, 11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, lO, 11
IIX
1,2,3
tACE
7, 8, 9, lO, 11
Ioz
1,2,3
Icc
1,2,3
ISBl
ISB2
Parameter
Subgroups
READ CYCLE
WRITE CYCLE
twc
7, 8, 9, lO, 11
1,2,3
tSCE
7,8,9,lO,11
1,2,3
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, lO, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, lO, 11
tHD
7,8, 9, lO, 11
Document #: 38-00232
2-23
CY7CI07A
•
PRELIMINARY
CY7CI09A
128K X 8 Static RAM
Features
Functional Description
• High speed
- tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
- 1020mW
The CY7CI09A is a high-performance
CMOS static RAM organized as 131,072
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
• Low standby power
- 250mW
• 2.0V data retention
- 100~W
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
• Easy mem~ expansion with CE.,
CE2, and OE options
Reading from the device is accomplished
by taking ch~nable one (CEl) and output enab~OE) LOW while forcing write
enable (WE) and chip enable two (CE2)
HIGH. Under these conditions, the contents of the memory location specified by
the address pins will appear on the I/O
pins.
(CEl),anactiveHIGHchipena~CE2),
an active LOW output enable (OE), and
three-state drivers. This device has an automaticpower-down feature that reduces
power consumption by more than 75%
when deselected.
Writing to the device is accomplished by
taking~ enable one (CEl) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the eight
I/O pins (1/00 through 1/07) is then written
into the location specified on the address
pins (An through Al6).
The eight input/output pins (1/00 through
1/07) are placed in a high-impedance state
when the device is deselected (CEl HIGH
or CE2 LOW), the outputs are disabled
(OE HIGH), or during a wri~eration
(CEl LOW, CE2 HIGH, and WE LOW).
The CY7C109 is available in standard
400-mil-wide DIPs and SOJs and a leadless
chip carrier.
Logic Block Diagram
Pin Configurations
LCC
DIP/SOJ
Top View
Top View
Vee
A16
A14
A12
2
3
4
A7
1/01
Ao
1/00
1/°1
1/°2
GND
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
As
As
~
As
A2
A1
WE
A13
As
As
1/00
A15
CE2
A9
A11
As
~
A10
A2
A1
m:
CE1
1/0 7
1/°6
I/Os
1/04
1/°3
As
Ao
1/°0
1/°1
1/°2
GND
109A-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
324
314
304
294
284
274
264
25
24
234
22
21
20
19C
18C
17
109A-3
1/05
1/°6
109A-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Commercial
Current (rnA)
Military
Commercial
Maximum Standby
Current (rnA)
Military
7CI09A-12
12
185
45
7CI09A-15
15
170
180
40
40
2-24
7CI09A-20
20
155
170
30
30
7CI09A-25
25
145
160
30
30
7CI09A-35
35
140
150
25
25
.
';~CYPRESS
.
,
CY7CI09A
PRELIMINARY
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55°C to + 125°C
Supply Voltage on Vee to Relative GND[l] . - O.5V to +7.0V
DC Voltage ApBlied to Outputs
in High Z State 1] .................. - 0.5V to Vee + 0.5V
DC Input Voltagel 1] ................ - O.5V to Vee + 0.5V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[2]
Range
Commercial
Military
O°C to +70°C
Vee
5V ± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[3]
7CI09A-12
Parameter
VOH
VOL
VIR
VIL
IIX
loz
los
lee
ISBl
ISB2
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
VOltagel 1]
Input Load
Current
Output Leakage
Current
Output Short
Circuit Currentl 4]
Vee Operating
Supply Current
Min.
Test Conditions
Vee = Min., IOH = - 4.0 rnA
Max.
2.4
2.2
-0.3
GND~ VI~ Vee
-1
GND~ VI~ Vee,
Output Disabled
Vee = Max., VOUT = GND
-5
Automatic CE
Power-Down
Current
-TTL Inputs
Max. Vee, CE1 ~ VIR
or CE2~ VIL,
VIN ~ VIR or
VIN ~ VIL, f = fMAX
Com'l
Automatic CE
Power-Down
Current
- CMOS Inputs
Max. Vee,
CE1 ~ Vee - 0.3v,
or CE2 ~ 0.3v,
VIN ~ Vee - 0.3v,
or VIN ~ 0.3V, f=O
Com'l
Min.
0.4
2.2
Max.
2.4
2.2
Unit
V
0.4
V
V
-0.3
-0.3
Vee +
0.3
0.8
+1
-1
+1
-1
+1
f.lA
+5
-5
+5
-5
+5
f.lA
V
-300
-300
-300
rnA
185
170
155
rnA
180
170
40
30
40
30
2
2
2
2
45
Mil
2-25
7CI09A-20
Vee +
0.3
0.8
Mil
Mil
Max.
2.4
Vee +
0.3
0.8
Com'l
Min.
0.4
Vee = Min., IOL = 8.0 rnA
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
7CI09A-15
2
rnA
rnA
II
PRELIMINARY
CY7CI09A
Electrical Characteristics Over the Operating Range[3] (continued)
7CI09A-25
Parameter
Description
VOH
VOL
VIR
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VIL
IIX
loz
Input LOW Voltage[lj
los
lee
ISBl
ISB2
Test Conditions
Min.
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
7CI09A-35
Max.
Min.
2.4
0.4
2.2
Max.
Unit
0.4
V
V
V
2.4
2.2
Vee +
0.3
0.8
+1
+5
!!A
!!A
-300
-300
rnA
Com'I
145
140
rnA
-0.3
-1
-5
Vee +
0.3
0.8
+1
+5
-0.3
-1
-5
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating
Supply Current
GND5VI5 V ee
GND5 VI5 Vee,
Output Disabled
Vee = Max., VOUT = GND
Mil
160
150
Automatic CE
Power-Down
Current
-TIL Inputs
Max. Vee, CE1~ VIR
or CE25 VIL,
VIN ~ VIR or
VIN 5 VIL, f = fMAX
Com'l
30
25
Mil
30
25
Automatic CE
Power-Down
Current
- CMOS Inputs
Max. Vee,
CEl ~ Vee - 0.3v,
or CE2 5 0.3v,
VIN ~ Vee - 0.3v,
or VIN 5 0.3v, f=O
Com'l
2
2
Mil
2
2
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
V
rnA
rnA
Capacitance[5]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Max.
Unit
7
pF
10
pF
10
pF
Notes:
1.
2.
3.
VIL (min.) = -2.0V for pulse durations of less than 20 ns.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing
information.
4.
5.
2-26
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
PRELIMINARY
CY7CI09A
AC Test Loads and Waveforms
OllTP~~ ~
1 1_
.~~.~~F
INCLUDING J
JIG AND
SCOPE
Equivalent to:
(a)
OllTP:
~
1 1_
.~ .•~~F
INCLUDING J
R2
255Q
-
JIG AND
SCOPE
(b)
ALL INPUT PULSES
3.0V---90%
10%
GND
R2
~3
255Q
109A-4
109A-5
THEVENIN EQUIVALENT
OUTPUT~
ns
-
1.73V
Switching Characteristics[3,6] Over the Operating Range
Description
Parameter
READ CYCLE
Read Cycle Time
tRC
Address to Data Valid
tAA
tOHA
Data Hold from Address Change
tACE
CElLOWtoDataValid,CE2HIGH
to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7, 8]
tLZCE
CEI LOW to Low Z, CE2 HIGH to
LowZ[8]
tHZCE
CEI HIGH to High Z, CE2 LOW to
High Z[7,8]
tpu
CElLOWtoPower-Up,CE2HIGH
to Power-Up
7CI09A-12
Min. Max.
7CI09A-15
Min. Max.
15
12
12
3
12
0
3
3
0
8
12
10
8
15
10
ns
10
ns
10
ns
ns
ns
ns
10
0
25
20
35
3
0
0
ns
ns
0
3
3
0
10
0
Unit
35
3
25
8
7
6
35
3
0
7CI09A-35
Min. Min.
25
20
7
6
25
3
7
6
7CI09A-25
Min. Max.
20
15
0
CEI HIGH to Power-Down,
CE2 LOW to PowerDown
WRITE CYCLEl9,lOj
20
15
3
tpD
7CI09A-20
Min. Max.
ns
ns
35
ns
twc
Write Cycle Time
12
15
20
25
35
ns
tSCE
CEI LOW to Write End, CE2 HIGH
to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write End
10
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
3
3
3
3
3
ns
tHZWE
WE LOW to High Z[7,8]
7
6
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHzWE are specified with a load capacitance of 5
pF as in part (b) of AC Test Loads. Transition is measured ±500 m V
from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
8
10
10
ns
The internal write time of the memo~ defined by the overlap of CEl
LOW, CE2 HIGH, and WE LOW. CEl and WE must be LOW and
CE2 HI GH to initiate a write, and the transition of any of these signals
can terminate the write. The input data set-up and hold timing should
be referenced to the leading edge of the signal that terminates the
write.
10. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE LOW) is the sum of tHZWE and tSD.
9.
2-27
•
Ih
:E
200 rnA
65°C to +150°C
Operating Range
55°C to +125°C
Range
Commercial
Military[2]
- 0.5V to +7.OV
- 0.5V to +7.OV
- 0.5V to +7.OV
Ambient
Temperature
Vee
O°Cto + 70°C
SV ± 10%
- 55°C to + 125°C
SV ± 10%
Electrical Characteristics Over the Operating Rangel 3]
Parameter
VOR
VOL
VIR
VIL
IIX
Ioz
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel1]
Input Load Current
Output Current
(High Z)
Test Conditions
= Min., lOR = - 5.2 rnA
Vee = Min., IOL = 8.0 rnA
Vee
VSSS VIS Vee
Vss S VOUT s Vee,
Output Disabled
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
Power Supply
Current
Icc
7C123-7
7C123-9
Min. Max.
2.4
0.4
2.2
Vee
- 0.8 +0.8
-10 +10
-10 +10
I Commercial
7C123-10
7C123-15
Min. Max.
2.4
0.4
2.2
Vee
- 0.8 +0.8
-10 +10
- 10 +10
7C123-12
Min. Max.
2.4
0.4
2.2
Vee
- 0.8 +0.8
- 10 +10
- 10 +10
120
IMilitary
150
Unit
V
V
V
V
IlA
IlA
120
rnA
150
rnA
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f
Vee = 5.0V
Max.
= 1 MHz,
Unit
pF
8
8
pF
Logic Table[5]
Input
OE
CSt
CS2
WE
Do - D3
X
H
X
X
X
HighZ
Not Selected
X
X
L
X
X
HighZ
Not Selected
L
L
H
H
X
00 - 03
Read Stored Data
X
L
H
L
L
HighZ
Write "0"
Outputs
Mode
X
L
H
L
H
HighZ
Write "1"
H
L
H
H
X
HighZ
Output Disabled
Notes:
1. Vldmin.) = -3.0Vfor pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing
information.
4.
5.
2-33
Tested initially and after any design or process changes that may affect
these parameters.
H = High Voltage, L = Low Voltage, X = Don't Care, and
High Z = High Impedance.
II
~
~~PRESS
~, ~EMICONDUcrOR
CY7C123
AC Test Loads and Waveforms
R1470Q
OUTP~~~
20 PF
INCLUDING r
JIGAND =
SCOPE (a)
OUTP~~31R1
470Q
R2
224Q
=
5PFr
INCLUDING
JIGAND
SCOPE (b)
=
ALL INPUT PULSES
3.0V - - - -.J..,------""!IL
R2
224Q
GND
=
C123-3
C123-4
THEvENIN EQUIVALENT
Equivalent to:
152Q
OUTPUT O'O--....J¥,'III
.. _ - - 4 0 1.62V
Switching Characteristics Over the Operating Range[3]
7C123-9
7C123-7
Parameter
Description
Min.
Max.
Min.
Max.
7C123-10
Min.
Max.
7C123-12
Min.
Max.
7C123-15
Min.
Max.
Unit
READ CYCLE
12
ns
tRe
Read Cycle Time
tAA
Address to Data Valid
7
9
10
12
15
ns
tACS
Chip Select to Data Valid
7
8
8
8
10
ns
tOOE
OE LOW to Data Valid
7
8
8
8
10
ns
tHzes
Chip Select to High Z[6,7]
5
6
6
6.5
8
ns
tHzOE
OE HIGH to High Z[6]
5
6
6
6.5
8
ns
tLzes
Chip Select to Low Z[7]
2
2
2
2
2
ns
tLZOE
OE LOW to Low Z
2
2
2
2
2
ns
7
10
9
15
WRITE CYCLE
12
10
9
ns
15
twe
Write Cycle Time
tHZWE
WE LOW to High Z[6]
tLzWE
WE HIGH to Low Z
2
2
2
2
2
ns
tpWE
WE Pulse Width
5
6.5
7
8
11
ns
tso
Data Set-Up to Write End
5
6
7
8
11
ns
tHO
Data Hold from Write End
1
1
1
1
1
ns
tSA
Address Set-Up to Write Start
0.5
1
1
2
2
ns
tRA
Address Hold from Write End
1.5
1.5
2
2
2
ns
tses
CS LOW to Write End
5
6.5
7
8
11
ns
tAW
Address Set-Up to Write End
5.5
7.5
8
10
13
ns
7
Notes:
6. Transition is measured at steady-state HIGH level - 500 mV or
steady-state LOW level +500 mV on the output from 1.5V level on
the input with load shown in part (b) of AC Test Loads.
7.
2-34
8
7
6
6
5.5
ns
At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
:~PRESS
·
CY7C123
.F SEMICONDUcrOR
Switching Waveforms
===*_
Read Cycle [8, 9]
_wl4----_-=-t
t
RC
ADDRESS
tAA
------I.~I
tHZOE - - - - - - - . . 1
DATA OUT
C123-5
Write Cycle [7, 8]
twc
ADDRESS
)(
)(
tHA - - .
tAW
I
tscs
:*
)K
tpWE
tSA
}~
'\K
I
DATA IN
f
tSD
~tHZWE
DATA OUT
tHD
I+- tLZWE
~~~i---
C123-6
Notes:
8.
Measurements are referenced to l.5V unless otherwise stated.
9.
2-35
Timing diagram represents one solution that results in an optimum
cycle time. Timing may be changed in varous applications as long as
the worst case limits are not violated.
'ir~PRKSO
~t-
CY7C123
SEMICONDUCTOR
lYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
3l1.2
ii 1.0
Icc
V
o
~ 0.8
::J
~
V
0.6
1.2
/
V
m
~ 1.0
~
o8 0.8
~
-
ISB -
0.0
4.0
4.5
5.0
0.2
0.0
6.0
5.5
I-
1.4
75
5
Vee = 5.0V
TA = 25°C
"'"
a:
a:
45
30
I-
25
125
AMBIENT TEMPERATURE (0G)
I
~
::> 60
g
1rI-
Vee = 5.0V
VIN = 5.0V
ISB
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.6 , - - - - - - , - - - - - - - ,
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
!zw
w
-55
M
SUPPLY VOLTAGE
90
~
::>
~ 0.4
z
0.2
1
()
~
~ 0.6
:::i!:
a:
~ 0.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
'"
15
0
o
1.0
2.0
1.3
0
w 1.2
N
::J
a:
Ci5
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 240
6.0
180
I-
120
5o
20~~~-r-~~-~-~
N
5
a:
z 1.0
~ 10 ~~~~~-+--+--~
w
::J
0.6 L -_ _ _----I_ _ _ _ _.....J
-55
25
125
M
O
V
a.
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
0.5
300
()
oz
3.0
0
w
::J
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to + 70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
Military[l]
Electrical Characteristics Over the Operating Rangel 2]
Parameter
Description
Test Conditions
7C128A-15
7C128A-20
7C128A-25
7C128A·35, 45
Min.
Min.
Min.
Min.
Max.
Max.
Max.
VOH
Output HIGH
Voltage
Vee = Min.,
IOH= -4.0 rnA
VOL
Output LOW
Voltage
Vee = Min., IOL = 8.0 rnA
VIR
Input HIGH
Voltage
2.2
Vee
2.2
Vee
2.2
Vee
VIL
Input LOW
Voltage[3]
-0.5
0.8
-0.5
0.8
-0.5
IIX
Input Load
Current
GND~VI~Vee
-10
+10
-10
+10
loz
Output Leakage
Current
GND~ VI~ Vee
Output Disabled
-10
+10
-10
+10
los
Output Short
Circuit Current[4]
Vee = Max.,
VOUT = GND
lee
Vee Operating
Supply Current
Vee = Max.
lOUT = o rnA
Automatic CE
Power-Down
Current
Max. Vee,
CE~ VIR,
Min. Duty Cycle
= 100%
Automatic CE
Power-Down
Current
Max. Vee,
CEl ?..Yee - 0.3v,
VIN?" Vee -O.3V
or VIN ~ O.3V
ISBl
ISB2
2.4
2.4
0.4
0.4
-300
Com'l
120
Mil
Com'l
40
Mil
Com'l
2.4
40
Mil
-300
Max.
2.4
0.4
Unit
V
0.4
V
2.2
Vee
V
0.8
-0.5
0.8
V
-10
+10
-10
+10
IlA
-10
+10
-10
+10
IlA
-300
-300
rnA
rnA
100
100
100
125
125
100
40
20
20
40
40
20
20
20
20
20
20
20
rnA
rnA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes.
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3. VIL (min.) = -3.0V for pulse durations less than 30 ns.
4.
5.
2-39
= 1 MHz,
Max.
Unit
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
II
·r~
CY7C128A
AC Test Loads and Waveforms
OUTP~~31R1
481Q
30 pF
OUTP~~~R1481Q
R2
I _
255Q
INCLUDING
JIG AND SCOPE (a)
Equivalent to:
-
5pF
.
INCLUDING
JIG AND SCOPE (b)
ALL INPUT PULSES
3.0V ----_~~----~
R2
GND
I _
255Q
-
THEVENIN EQUIVALENT
C128A-5
C128A-4
167Q
OUTPUT OO---"J'V\/\,,}' _ _--OO 1.73V
Switching Characteristics Over the Operating Rangel 2,6]
7C128A-15
Parameter
Description
Min.
7C128A-20
Max.
Min.
Max.
7C128A-25
Min.
Max.
7C128A-35
Min.
Max.
7C128A-45
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACE
CE LOW to Data Valid
15
20
25
35
45
ns
tDOE
OE LOW to Data Valid
10
10
12
15
20
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7]
tLZCE
CE LOW to ~ow Z[8]
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
20
15
25
20
15
5
5
3
5
3
5
5
5
0
0
15
5
20
20
15
ns
ns
0
20
ns
ns
5
0
0
ns
15
15
ns
ns
3
12
10
ns
45
5
3
10
8
8
45
35
5
3
8
8
35
25
25
ns
WRITE CYCLE[9]
twc
Write Cycle Time
15
20
20
25
40
ns
tSCE
CE LOW to Write End
12
15
20
25
30
ns
tAW
Address Set-Up to Write End
12
15
20
25
30
ns
tRA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tHzWE
WE LOW to High Z[7]
tLZWE
WE HIGH to Low Z
7
7
5
5
Note:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOrJIOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 m V from steady state
voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
9.
2-40
10
7
5
5
15
5
ns
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
·
::~
-'iE
===='..,
CY7C128A
CYPRESS
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. ~[1O,11]
€v:: J
ADDRESS
------
DATA OUT
~
*-
tRC
1
tAA
XX *:::::::::::::::D:AT:A:V:A:L:ID::::::::::::
PREVIOUS DATA
C128A-6
Read Cycle No. 2[10, 12]
tRC
~~
~~
tACE
~~
~~
tHZOE-tHZCE-
tOOE
-tUOEDATA OUT
HIGH IMPEDANCE
VCC
_tpu
___________
"'
DATA VALID
~"""'"
tUCE
SUPPLY
CURRENT
~/////
HIGH
IMPEDAN CE
~
_tpo
;ft50%
~
CC
I
50%
ISS
C128A-7
Write Cycle No.1 (WE Controlled)[9, 13]
~---------------------------twc----------------------------~
ADDRESS
~------------------tSCE----------------------~
~-----------------------~w--------------------~----
____~~~~~~~~~~_tS_A_-_-_-_-_-_-~_-_-~~~~~
________________
~
~~----tpWE------~~~_ _ _ _ _ _ _ _ _ ___
~~~------tso--------~
DATA IN
DATA-IN VALID
tHZWEj
....,,>
DATA I/O _ _ _ _ _ _ _ _
DA_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _
tlZWE ---I
HIGH IMPEDANCE
~'----C128A-8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected. OE, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter high-impedance state, as shown, when OE is held
LOW during write.
14. IfCE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-41
I
&;~PRFSS
~,
CY7C128A
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[9, 12, 14]
-----~---- tSCE - - - . - I
1 4 - - - - tpWE - - - - - - . I
~~~~~~~~~~~~~~~
________________________~
~~~~~~~~~~~
~~------tSD
---~.
DATA-IN VALID
tHZWE
---.I
~_J~>-I--H-I-G-H-IM-P-E-D-A-N-C-E
______________
/
DAT'AI/O _ _______________________________________
DATA UNDEFINED
C128A-9
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
~ 1.2
..B
Icc
1.0
V
o
~ 0.8
::::i
~ 0.6
V
V
:/
1.2
!Xl
..::: 1.0
g
ow 0.8
15
z
4.5
5.0
5.5
0.4
SUPPLY VOLTAGE (V)
80
Vcc = 5.0V
VIN = 5.0V
ISB
25
125
AMBIENT TEMPERATURE (0C)
:::>
~ 40
~ 20
a..
o~
1.6
J,
1.3
J,1.4
In
1.2
o
'"
0
0.0
~ r-...
'"
1.0
2.0
1.1
II:
~ 1.0
~
0.9
0.8
4.0
4.5
TA = 25°C
--.....i'---
5.0
5.5
SUPPLY VOLTAGE (V)
6.0
~
II:
oz
'"
4.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
,.......-r-
I-
z
/
~ 100
~ 1.21--------if----~<---I
...............
3.0
:(' 140
§.. 120
!::::!
Vcc = 5.0V
TA = 25°C)
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.4
:E
100
II:
0.0
-55
6.0
:::>
~ 60
0.2
ISB - ~
ifi
II:
II:
()
~ 0.6
0.2
2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ................ - 65 ° C to + 150 ° C
Latch-Up Current ........................... >200 rnA
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ...................... - O.5V to +7.0V
Operating Range
Vee
O°Cto +70°C
5V ± 10%
Industrial
- 40°C to +85°C
5V ± 10%
Military[4]
- 55°C to +125°C
5V ± 10%
Commercial
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.5V to +7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Notes:
3. 25-ns version available only in PLCCILCC packages.
Ambient
Temperature
Range
4.
2-46
TA is the "instant on" case temperature
CY7C130/CY7C131
CY7C140/CY7C141
=='
:~
_'il!CYPRESS
===
jF SEMlCONDUcrOR
Electrical Characteristics Over the Operating Rangd5]
7C130-25,30[3]
7C131-25,30
7C140-25,30
7C141-25,30
Description
Parameter
Min.
Test Conditions
= Min., IOH = = 4.0 rnA
IOL = 16.0 rnA[6]
VOH
Output HIGH Voltage Vee
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
0.4
InputLeakageCurrent GND~ VI~ Vee
Output Leakage
Current
Vee,
Output Disabled
los
Output Short
Circuit Currend7, 8]
Vee = Max.,
VOUT = GND
lee
Vee Operating
Supply Current
CE = VIL,
Outputs 0c?en,
f = fMAX[
ISB2
ISB3
ISB4
GND~ VO~
CEL or CER L VIH,
Active Port Outputs Open,
f = fMAX[9]
Com'l
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER L Vee - 0.2V,
VIN L Vee - 0.2Vor
VIN ~ 0.2V, f = 0
Com'l
Standby Current
One Port,
CMOS Inputs
One Port CEL or
CERL Vee - 0.2V,
VIN L Vee - 0.2Vor
VIN ~0.2V,
Active Port Outputs Open,
f = fMAX[9]
V
V
\l.5
0.5
2.2
0.8
V
0.8
V
+5
-5
+5
-5
+5
!J.A
+5
-5
+5
-5
+5
!J.A
- 350
rnA
rnA
Com'l
Standby Current
One Port,
TIL Inputs
0.4
-5
Com' I
CEL and CER L VIH,
f = fMAX[9]
Unit
-5
- 350
- 350
170
120
90
170
120
Mil
Standby Current
Both Ports,
TIL Inputs
Max.
2.4
2.2
0.8
IIX
Min.
Max.
0.4
0.5
2.2
Ioz
ISBl
Min.
7C130-45,55
7C131-45,55
7C140-45,55
7C141-45,55
2.4
2.4
4.0 rnA
IOL
Input LOW Voltage
VIL
Max.
7C130-35
7C131-35
7C140-35
7C141-35
65
Mil
115
Mil
15
Mil
Com'l
105
Mil
45
35
65
45
90
75
115
90
15
15
15
15
85
70
105
85
rnA
rnA
rnA
rnA
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
= 1 MHz,
15
pF
10
pF
TA = 25°C, f
Vee = 5.0V
Notes:
5. See the last page of this specification for Group A subgroup testing
information.
6. BUSY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. Tested initially and after any design or process changes that may affect
these parameters.
9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of lItRC and using AC Test Waveforms input levels of GND to 3Y.
10. AC Test conditions use VOH = 1.6V and VOL = 1.4Y.
11. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IorJIOH, and 30-pF load capacitance.
12. AC Test Conditions use VOH = 1.6V and VOL = 1.4Y.
13. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL =
5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV
from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS
LOW and R/W LOW. Both signals must be low to initiate a write and
either signal can terminate a write by going high. The data input set-up
and hold timing should be referencd to the rising edge of the signal
that terminates the write.
2-47
II
CY7C130/CY7C131
CY7C140/CY7C141
1vk~
AC Test Loads and Waveforms
i
OUT':': pF r ',"2
O
INCLUDING
JIG AND
SCOPE
~
OUT.:': 5pF rI"
34m
-=
-=
(a)
SV
I3OS'i'--1
347Q
INCLUDING
JIG AND
SCOPE
_
-
281,a
OR
rnT
IaOPF
_
C130-S
(b)
BUSY Output Load
(CY7C130/CY7C131 ONLy)
C130-6
ALL INPUT PULSES
Equivalent to:
3.0V ----...1r------"'"lI....
THEVENIN EQUIVALENT
2SO.\1
OUTPUT 0-0- - " "
• .,...---oOlAOV
GND
Switching Characteristics Over the Operating Rangd5,1l]
7C130-2S[3]
7C131-2S
7C140-2S
7C141-2S
Parameter
Description
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
7C130-3S
7C131-3S
7C140-3S
7C141-3S
Min.
Max.
7C130-4S
7C131-4S
7C140-4S
7C141-4S
Min.
Max.
7C130-S5
7C131-SS
7C140-SS
7C141-SS
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid[12]
tOHA
Data Hold from
Address Change
25
35
30
25
0
30
0
45
35
0
55
45
0
ns
55
0
ns
ns
tACE
CE LOW to Data Valid[12]
25
30
35
45
55
ns
tDOE
OE LOW to Data Valid[12]
15
20
20
25
25
ns
tLzOE
OE LOW to Low Z[13]
tHZOE
OE HIGH to High Z[13, 14]
25
ns
tLZCE
CE LOW to Low Z[13, 14]
tHZCE
CE HIGH to High Z[13, 14]
tpu
CE LOW to Power-Up
3
3
15
5
5
0
5
15
0
5
0
ns
5
20
0
25
ns
35
ns
ns
0
35
35
ns
3
20
20
25
25
3
20
15
15
CE HIGH to Power-Down
tpD
WRITE CYCLE[15]
3
twc
Write Cycle Time
25
30
35
45
55
tSCE
CE LOW to Write End
20
25
30
35
40
ns
tAW
Address Set-Up to Write End
20
25
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
R/W Pulse Width
15
25
25
30
30
ns
tSD
Data Set-Up to Write End
15
15
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
tHZWE
R/W LOW to High Z
R/W HIGH to Low Z
tLzWE
15
0
20
15
0
2-48
0
ns
25
20
0
ns
0
ns
ns
.F
CY7C130/CY7C131
CY7C140/CY7C141
.~
~=CYPRESS
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 5,1l] (continued)
7C130-2Sl3 J
7C131-2S
7C140-25
7C141-25
Parameter
Description
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
7C130-3S
7C131-3S
7C140-35
7C141-35
Min.
Max.
7C130-4S
7C131-45
7C140-45
7C141-45
Min.
Max.
7C130-SS
7C131-55
7C140-55
7C141-55
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
tBHA
BUSY LOW from Address Match
BUSY HIGH from
20
20
20
20
25
30
20
20
25
30
ns
ns
20
20
20
25
30
ns
20
20
20
25
30
Address Mismatch[16]
tBLC
tBHC
tps
tWBl17J
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[16]
Port Set Up for Priority
R/W LOW after BUSY LOW
5
0
0
0
0
0
tWH
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
20
30
30
35
35
tBDD
tDDD
tWDD
Write Data Valid to
Read Data Valid
Write Pulse to Data Delay
5
5
5
ns
ns
ns
5
ns
ns
25
30
35
45
45
Note
18
Note
18
Note
18
Note
18
Note
18
ns
Note
18
Note
18
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
25
25
25
35
45
25
25
25
35
45
ns
ns
Address to INTERRUPT
Set Time
OE to INTERRUPT
Reset Timd 16]
25
25
25
35
45
ns
25
25
25
35
45
ns
tEINR
CE to INTERRUPT
Reset Timd 16]
25
25
25
35
45
ns
tINR
Address to INTERRUPT
Reset Timd 16]
25
25
25
35
45
ns
tWINS
tEINS
tINS
tOlNR
Notes:
16. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on PortA, where Port A has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
following:
A. BUSY on Port B goes HIGH.
B. Port B's address is toggled.
C. CE for Port B is toggled.
D. R!W for Port B is toggled during valid read.
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
21. Address valid prior to or coincident with CE transition LOW.
22. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or tHZWE + tSD to allow the data I/O
pins to enter high impedance and for data to·be placed on the bus for
the required tSD.
23. If the CE LOW transition occurs simultaneously with or after the R!
W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms
Read Cycle No. tf19, 20]
ADDRESS
DATA OUT
=f=---tRc--lLloHA~
tAA~l
PREVIOUS DATA
Either Port Address Access
vAlID4'xxX~===============D=A=TA==V=AL=I=D==============
C130-7
2-49
I
CY7C130/CY7C131
CY7C140/CY7C141
;;~~
,..
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No. 2[19,21]
Either Port CE/OE Access
DATA OUT
_tPD~
ICC~
ISB
-./'
C130-B
Read Cycle No. 3[20]
Read with BUSY, Master: CY7C130 and CY7C131
tRC
)K
)K
ADDRESS MATCH
~r\.
tpWE
)(
)(
ADDRESSL
---..
tps
.,~
./14---
tHD
)K
VALID
ADDRESS MATCH
+-... tBHA
BUSYL
+--tBLA
tBDD .......
)~
DOUTL
tDDD
tWDD
~
C130 -9
Write Cycle No.1 (00 Tri-States Data IIOs - Either Port) [15,22]
Either Port
~--------------------~--~C------------------------~
ADDRESS
"'P""'('_~
R/W
14---------------- tSCE ------------------~ ,..,~~'7'"7'..,..,,...,..~'7'"7'..,..,~
____....
~_-_-_-_-_-_-~_t_sA_-__:..-_-_-_-_-_~1~~ 1 4 - - - tPWE
-----~ ~---__+-----
1 4 - - - - - t S D ------~...
DATAIN
DATA VALID
~ZDEe
Dour
»»»
HIGH IMPEDANCE
C130-10
2-50
CY7C130/CY7C131
CY7C140/CY7C141
.
~-~
'iE CYPRESS
~,
SEMICONDUcrOR
Switching Waveforms (continued)
Write Cycle No. 2 (R/WTri-StatesDataI/Os - EitherPort)[15,23]
Either Port
I
~------------------twc ----------------------~
ADDRESS
~~~~~-
R/W
1 4 - - - - tSCE ----------------~~~~~~~~~~~
_ _ _..:..-_....;;;.~_-+-.............. ..,.;..;...----
tpWE
------.1,._--------
DATAIN
tH~~
DATAoUT
>) ) ) ) ) ) ) ) ) ) ) ) )
tLZWE~ ~
HIGH IMPEDANCE
~""'7<..,(..,(..,(....,<..,(
C130-11
Busy Timiug Diagram No.1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
X
~tPSb
CEL
CER
X
ADDRESS MATCH
~LC-q
BUSYR
t~HC1
C130-12
CER Valid First:
ADDRESSL,R
CER
CE L
X
X
ADDRESS MATCH
~~Sb
tB~-q
BUSYL
tt~C1
C130-13
2-51
CY7C130/CY7C131
CY7C140/CY7C141
~
~PRFSS
~, SEMICONDUCTOR
Switching Waveforms (continued)
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
ADDRESSL _ _ _oJ
ADDRESS MISMATCH
ADDRESSR _ _ _ _ _ _ _J
BUSYR
C130-14
Right Address Valid First:
ADDRESS MISMATCH
ADDRESSR _ _ _J
ADDRESSL _ _ _ _ _ _ _J
BUSYL
C130-15
Busy Timing Diagram No.3
Write with BUSY (Slave: CY7C140/CY7C141)
CE~
R!W
----------------------------------------------------~~~------------tPWE ------------~~~
-->t_tWB
-1_ _;,," -1
C130-16
2-52
CY7C130/CY7C131
CY7C140/CY7C141
==e="-~
_"1=
CYPRESS
- , SEMICONDUCTOR
Switching Waveforms (continued)
Interrupt Timing Diagrams
II
Left Side Sets INTR
i---
Right Side Clears !NTR
ADDRR
---~~ ~
C130-17
xXxXXXXXXXXXXX __REA_D~3F_F_~
tHA
tRC
_ __
-
---------
GER
C130-18
Right Side Sets INTL
" "- f
Left Side Clears INTL
ADDRR
XXXXXXXXXXXXXX __
C130-19
tRC
-----l~~ ~
_~_ __
RE_AD_3F_E
tHA---~
GEL
C130-20
2-53
CY7C130/CY7C131
CY7C140/CY7C141
;~=
~__
SEMICONDUCTOR
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ffi 1.2
13 1.0
In 0.8
N
:J
~ 0.6
1.2
/
m
(J)
lee/
()
/
/
1.0 ~
..9 0.8
w
0.6
z
0.2
0.0
4.0
4.5
0.2
I---
1883
5.0
5.5
SUPPLY VOLTAGE (V)
25
125
AMBIENT TEMPERATURE (0C)
o~
0
« 140
J.1.4
~
o
w 1.2 r--------4------~~~
aa:
80
Z
60
Oa:Ql«'O
°
7 6 5 4 3 2,1, 52 51 50 49 48 47
A2l
A3l
Ail
9
10
11
40
39
38
37
36
35
34
33
32
ASl
Ael
A7l
ASl
A9l
IIOol
I/O'l
1/0 2l
II03l
7C132
7C142
7C136
7C146
16
17
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
C132-4
C132-3
Selection Guide
7C132-25[3]
7C136-25
7C142-25
7C146-25
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current (rnA)
Com'l/Ind
7C132-30
7C136-30
7C142-30
7C146-30
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
55
25
30
35
45
170
170
120
90
90
170
120
120
45
35
35
65
45
45
Military
Com'l/Ind
65
65
Military
Maximum Ratings
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) .............. : ....... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Notes:
3. 25-ns version available in LCC and PLCC packages only.
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Industrial
- 40°C to +85°C
5V ± 10%
Military[4]
- 55°C to + 125°C
5V ± 10%
Range
Commercial
4.
2-59
TA is the "instant on" case temperature
CY7C132/CY7C136
CY7C142/CY7C146
~
~~pRF.SS
~, SEMICONDUCTOR
Electrical Characteristics Over the Operating Range[S)
7C132-25,30[3]
7C136-25,30
7C142-25,30
7C146-25,30
Parameter
Description
Min.
Test Conditions
= Min., IOH = IOL = 4.0 rnA
IOL = 16.0 rnA[6]
VOH
Output HIGH Voltage Vee
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
Input Load Current
GNDS VIS Vee
Ioz
Output Leakage
Current
GNDs Vos Vee,
Output Disabled
-5
los
Output Short
Circuit Current[7]
Vee = Max.,
VOUT = GND
lee
Vee Operating
Supply Current
CE = VIL,
Outputs 0sfen,
f
ISB3
ISB4
Com'l
= fMAX[
0.5
0.5
2.2
+5
-5
+5
-5
+5
-5
+5
-5
V
V
+5
JlA.
+5
IlA
- 350
rnA
rnA
- 350
170
120
90
170
120
45
35
65
45
Com'l
CEL or CER ~ VIR,
Active Port Outputs Open,
Mil
f = fMAX[8]
115
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER~ Vee - 0.2V,
VIN ~ Vee - 0.2Vor
V IN s 0.2V, f = 0
15
Standby Current
One Port,
CMOS Inputs
One Port CEL or
CER ~ Vee - 0.2V,
VIN ~ Vee - 0.2Vor
VIN sO.2V,
Active Port Outputs Open,
Com'l
65
Mil
Com'l
Mil
105
Mil
V
0.8
- 350
Standby Current
One Port,
TIL Inputs
f
2.2
0.8
Unit
V
0.5
CEL and CER ~ VIR,
Com'l
Max.
2.4
0.4
Mil
= fMAX[8]
Min.
0.4
Standby Current
Both Ports,
TIL Inputs
f
Max.
0.4
0.8
IIX
ISB2
Min.
7C132-45,55
7C136-45,55
7C142-45,55
7C146-45,55
2.4
2.2
-5
ISB!
Max.
2.4
4.0 rnA
7C132-35
7C136-35
7C142-35
7C146-35
rnA
rnA
90
75
115
90
15
15
15
15
85
70
105
85
rnA
rnA
= fMAX[8]
Capacitance[9]
Parameter
Description
Test Conditions
= 25°C, f = 1 MHz,
= 5.0V
CIN
Input Capacitanc~
TA
COUT
Output Capacitance
Vee
Notes:
S. See the last page of this specification for Group A subgroup testing information.
6. BUSY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of litre and using AC Test Waveforms input levels
ofGNDto 3Y.
9. Tested initially and after any design or process changes that may affect
these parameters.
10. Test conditions assume signal transition times of S ns or less, timing
reference levels of 1.Sv, input pulse levels of 0 to 3.0V and output
loading of the specified IOl)lOH, and 30-pF load capacitance.
Max.
Unit
15
pF
10
pF
11. AC test conditions use VOH = 1.6V and VOL = lAY.
12. At any given temperature and voltage condition for any given device,
tHZCE is less than tLzCE and tHzOE is less than tLZOE.
13. tLZCE, tLZWE, tHZOE, tLzOE, tHZCE, and tHzWE are tested with CL =
SpF as in part (b) of AC Test Loads. Transition is measured ± SOO m V
from steady-state voltage.
14. The internal write time of the memory is defined by the overlap of CE
LOW and R!W LOW. Both signals must be LOW to initiate a write
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referencd to the rising edge of the
signal that terminates the write.
2-60
CY7C 132/CY7C136
CY7C142/CY7C146
. :'~PRE&S
iF
SEMICONDUcrOR
AC Test Loads and Waveforms
R1893Q
5Vo----fIN'¥....,
R1893Q
5Vo----fIN'¥....,
0---_-"'"
OUTPUTo-----~
OUTPUT
FI
5PFI
R2
347Q
30 P
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
BOS'i'
~5V
•
281Q
OR
R2
34m
1m
I 3 0 PF
-=
C132-5
(b)
C132-6
BUSY Output Load
(CY7C132/CY7C136 ONLy)
ALL INPUT PULSES
THEVENIN EQUIVALENT
3.0V
250Q
OUTPUT 00---'·11\0.·......- - - 0 0 1.4V
----l_-----'_
GND
Switching Characteristics Over the Operating Range[5,1O]
7C132-25[3]
7C136-25
7C142-25
7C146-25
Description
Parameter
Min.
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
Max.
7C132-35
7C136-35
7C142-35
7C146-35
Min.
Max.
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid[11]
taRA
Data Hold from
Address Change
tACE
CE LOW to Data Valid[ll]
tOOE
OE LOW to Data Valid[ll]
tLZOE
OE LOW to Low Z[12]
tHZOE
OE HIGH to High Z[12, 13]
tLzCE
CE LOW to Low Z[12]
tHZCE
CE HIGH to High Z[12, 13]
tpu
CE LOW to Power-Up
25
0
30
45
55
45
35
0
0
ns
55
0
0
ns
ns
25
30
35
45
55
ns
15
20
20
25
25
ns
25
ns
3
3
3
15
15
5
5
0
5
25
25
20
20
0
35
ns
5
5
20
0
0
3
3
20
15
15
CE HIGH to Power-Down
tpo
WRITE CYCLE[14]
35
30
25
ns
25
35
ns
ns
0
35
ns
ns
twc
Write Cycle Time
25
30
35
45
55
tSCE
CE LOW to Write End
20
25
30
35
40
ns
tAw
Address Set-Up to Write End
20
25
30
35
40
ns
tRA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
R!W Pulse Width
15
25
25
30
30
ns
tso
Data Set-Up to Write End
15
15
15
20
20
ns
tHO
Data Hold from Write End
0
0
0
0
0
ns
tHZWE
R!W LOW to High Z
R!W HIGH to Low Z
0
tLzWE
15
20
15
0
2-61
0
20
0
25
0
ns
ns
CY7C132/CY7C136
CY7C142/CY7C146
~
:~PRESS
.
~, SEMICONDUCTOR
Switching Characteristics Over the Operating RangelS,lO] (continued)
7C132-25LJJ
7C136-25
7C142-25
7C146-25
Parameter
Description
Min.
7C132-30
7C136-30
7C142-30
7C146-30
Max.
Min.
Max.
7C132-35
7C136-35
7C142-35
7C146-35
Min.
Max.
7C132-45
7C136-45
7C142-45
7C146-45
Min.
Max.
7C132-55
7C136-55
7C142-55
7C146-55
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
tBHA
BUSY LOW from Address Match
BUSY HIGH from
Address Mismatch[lS]
tBLC
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH!1 5J
tBHC
tps
tWB[16]
20
20
20
25
30
ns
20
20
20
25
30
ns
20
20
20
25
30
ns
20
20
20
25
30
Port Set Up for Priority
5
5
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
0
20
0
0
tWH
30
30
tBDD
BUSY HIGH to Valid Data
tDDD
Write Data Valid to
Read Data Valid
Write Pulse to Data Delay
tWDD
ns
5
ns
0
0
35
35
ns
ns
5
5
25
30
35
45
Note
17
Note
17
Note
17
Note
17
45
Note
17
ns
ns
Note
17
Note
17
Note
17
Note
17
Note
17
ns
INTERRUPT TIMING[18]
tWINS
tEiNS
R/W to INTERRUPT Set Time
25
25
25
35
45
ns
CE to INTERRUPT Set Time
25
25
25
35
45
ns
tINS
Address to INTERRUPT
Set Time
OE to INTERRUPT
Reset Timel 1S ]
25
25
25
35
45
ns
25
25
25
35
45
ns
tEINR
CE to INTERRUPT
Reset Time[lS]
25
25
25
35
45
ns
tINR
Address to INTERRUPT
Reset Time[lS]
25
25
25
35
45
ns
tOINR
Notes:
15. These parameters are measured from the input signal changing, until
the output pin goes to a high-impedance state.
16. CY7C142/CY7C146 only.
17. A write operation on Port A, where Port A has priority, leaves the data
on Port B's outputs undisturbed until one access time after one of the
following:
A. BUSY on Port B goes HIGH.
B. Port B's address toggled.
C. CE for Port B is toggled.
D. R/W for Port B is toggled during valid read.
18.
19.
20.
21.
22.
52-pin LCC/PLCC versions only.
R/W is HIGH for read cycle.
Device is continuously selected, CE = VIL and OE = VIL.
Address valid prior to or coincident with CE transition LOW.
If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or tHZWE + tSD to allow the data I/O
pins to enter high impedance and for data to be placed on the bus for
the required tSD.
23. If the CE LOW transition occurs simuitaneouslywith or after the R/W
LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access) [19, 20]
ADDRESS
DATA OUT
1;=
~tOHA~
PREVIOUS DATA
tRe
"'.=:::::1,
vALID/f\:xxX~===============D=A=TA==VA=L=ID===============
C132-7
2-62
=-:
-==,;
=n
CY7C 132/CY7C136
CY7C142/CY7C146
.~
1= CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No.2 (Either Port-CE/OE Access)[19, 21]
II
DATA OUT
_ _ _~~
____________________
._ tPD~
_
lee~
Iss - - - . /
C132-8
Read Cycle No.3 (Read with BUSY Master: CY7C132 and 7C136)[20]
tRe
)~
tpWE
~~
ADDRESSL
-
)~
ADDRESS MATCH
/
)(
VALID
tps j4-
)~
ADDRESS MATCH
14- tSHA
BU$YL
I4--t LA
tSDD-
)E
DOUTL
tDDD
tWDD
C132 -9
Write Cycle No.1 (OE Three-States Data I/Os-Either Port) [14,22]
~-----------------------twe------------------------~
ADDRESS
14--------- tSCE ----------~ ""'~....,..'7"'7'..,..,""""",..,.'7"'7'.,...,."'7'
R/W
___':.~:.:.:.:.:.:.:._tS_A::~~~~.:_-_--'C'~~~~ ~--- tPWE -------+I
_------If------
14----- tSD - - - -......~
DATA VALID
HIGH IMPEDANCE
DOUT
C132-10
2-63
•
~
CY7C132/CY7C136
CY7C 142/CY7C146
.
~
II CYPRESS
, . SEMICONDUCTOR
Switching Waveforms (continued)
(RJW Three-States Data I/Os-Either Port)[14,23)
Write Cycle No.2
~---------~c ----------------------~
ADDRESS
--"'"'"""'--
1 4 - - - - tSCE
.......
_
Rm
_
.....;._ _ _.....;;,;.~.......~~~ 1 o I f - - - - - tpWE ----~
)
)
,----------------
tLZWE4
HIGH IMPEDANCE
DOUT
)
)
)
)
)
)
)
)
)
)
)
)
4~(r-(-r-(-r(-r(-r<
C132-11
Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First:
2-64
.
CY7C 132/CY7C136
CY7C142/CY7C146
;~
====;;:: CYPRESS
,
SEMICONDUCTOR
Switching Waveforms (continued)
•
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
ADDRESSL
ADDRESS MISMATCH
ADDRESSR
C132-14
Right Address Valid First:
ADDRESSR
ADDRESS MISMATCH
ADDRESSL
BUSYL
C132-15
Busy Timing Diagram No.3 (Write with BUSY, Slave: CY7C142/CY7C146)
~~------------------------------------------~I-'II--------
tPWE
-------t~
: ~_4Y8
-! _ _f4YH -1
C132-16
2-65
CY7C132/CY7C136
CY7C 142/CY7C146
&;~
_'~NDUcrOR
Interrupt Timing Diagrams[18]
Left Side Sets INTR
ADDRESSL
CEL
---,===:-:-
*____
C132-17
Right Side Clears INTR
ADDRESSR
I---- tRC - - - -
~
XXxXxxxxxXxxx~ ~__
tHA ---~I--
"CE
R
rnTR==============-------------------~
C132-18
Right Side Sets INTL
~------------~C ---------~~
ADDRESSR
WRITE 7FE
C132 19
Left Side Clears INTL
ADDRESS L
GEL
xxxxxxxxxxxxxx ~___¥.;
---
tHA
tRC
-
-----j~
.;--_::::::::::.:
ffiITL __________________________- - J
C132-20
2-66
CY7C132/CY7C136
CY7C142/CY7C146
==--~~~
fiE CYPRESS
_ , SEMICONDUCIOR
'iYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
./
gJ 1.2
j
lee/
1.0
w 0.8
N
:J
« 0.6
V
0
z
i]
100
::l
80
I------I-------==~
o
w
~ 0.6 1 - - - - - - I -- - -=-5-.0-V---l
Ve e
~ 0.4 1-_ _ _--I----=V..!lIN:!...=-=.5:.,:.0..:..V_--1
oZ
0.4
IS83 I - - -
0.2
0.0
4.0
:[ 120
.2 0.8
::::E
a:
1.2
1.01-----...:::!111....."......:....:...------1
u
V
0
~
4.5
5.0
5.5
SUPPLY VOLTAGE
0.21------1- IS8
0.6 L...-_ _ _---1_
-55
25
125
AMBIENT TEMPERATURE (0G)
6.0
M
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
J.
g
Iir
I-
20
6
0
'"'"
o
1.0
« 140
!z
a:
:J
~
«
::::E
r--......
0.8
4.0
TA = 25°C
-r---
4.5
~
-
5.0
5.5
SUPPLY VOLTAGE
0.8 h " c . . . - - - - I - - - - - - - 1
~ 40
6.0
25.0
5.20.0
:a:
~ 15.0
w 2.0
1.5
o
1.0
2.0
--
3.0
SUPPLY VOLTAGE
4.0
M
/
:...J
~ 10.0
v
5.0
5.0
V
/
1.0
Vee = 5.0V _
TA = 25°C
I
I
2.0
3.0
4.0
OUTPUT VOLTAGE
NORMALIZED
M
Icc vs. CYCLE TIME
1.25
en
0
N
~
0.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
2.5
4.0
M
.. v
20
AMBIENT TEMPERATURE (0G)
..9-
3.0
/
/
'/
o
6
0.6 L...-_ _ _---1_ _ _ _ _.....J
-55
25
125
30.0
0.5
60
0I-
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
a:
z 1.0
80
Z
en
3.0
0
a
~
M
'"'"
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 100
1.0 1--_ _ _~.tC-----_I
Z
Vee = 5.0V
TA = 25°C
OUTPUT VOLTAGE
o
w 1.2 ~----4---~~~
N
0.0
40
.s 120
0.9
::::E
a:
::l
J.1.4
a:
0 1.0
z
«
o
~ 60
1.3
::::E
:J
a:
a:
1.6
w 1.2
N
:J
« 1.1 I....
C,)
l-
1.4
0
•
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
~
V
o
o
V
V
t..---
u
..J:l
@
Vee = 5.0V
TA = 25°C
VIN = 0.5V
1.0 I----+---f----~
N
:J
~
a:
/
~ 0.75/-----+:,.,,;£=---f------I
Vee = 4.5V TA = 25°C
I
I
200 400 600 800 1000
CAPACITANCE (PF)
2-67
0.50 i:-------=2'="'0------=3l:-0-----J
10
40
CYCLE FREQUENCY (MHZ)
CY7C132/CY7C136
CY7C142/CY7C146
~
~~PRESS
~, SEMICONDUCTOR
Ordering Information
Speed
(ns)
30
35
45
55
Speed
(ns)
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
CY7C132-30PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C132-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C132-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C132-35FMB
F78
48-Lead Quad Flatpack
CY7C132-35LMB
L68
48-Square Leadless Chip Carrier
CY7C132-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C132-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C132-45FMB
F78
48-Lead Quad Flatpack
CY7C132-45LMB
L68
48-Square Leadless Chip Carrier
CY7C132-55PC
P25
48-Lead (600-Mil) Molded DIP
CY7C132-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C132-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C132-55FMB
F78
48-Lead Quad Flatpack
CY7C132-55LMB
L68
48-Square Leadless Chip Carrier
Ordering Code
Package
Name
Commercial
Package 'JYpe
Operating
Range
25
CY7C136-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
30
CY7C136-30JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
Commercial
Industrial
35
45
55
J69
52-Lead Plastic Leaded Chip Carrier
CY7C136-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C136-35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C136-45JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-45JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C136-45LMB
L69
52-Square Leadless Chip Carrier
Military
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C136-55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C136-55LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C136-35JC
CY7C136-55JC
2-68
·'
CY7C132/CY7C136
CY7C142/CY7C146
:~pRF.SS
-=',
SEMICONDUCTOR
Ordering Information
Speed
(ns)
30
35
45
55
Speed
(ns)
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
CY7C142-30PC
P25
48-Lead (600-Mil) Molded DIP
CY7C142-30PI
P25
48-Lead (600-Mil) Molded DIP
Commercial
Industrial
CY7C142-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C142-35FMB
F78
48-Lead Quad Flatpack
CY7C142-35LMB
L68
48-Square Leadless Chip Carrier
CY7C142-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C142-45FMB
F78
48-Lead Quad Flatpack
CY7C142-45LMB
L68
48-Square Leadless Chip Carrier
CY7C142-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C142-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C142-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C142-55FMB
F78
48-Lead Quad Flatpack
CY7C142-55LMB
L68
48-Square Leadless Chip Carrier
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
25
CY7C146-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
30
CY7C146-3OJC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-35LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C146-45JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-45JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-45LMB
L69
52-Square Leadless Chip Carrier
Military
CY7C146-55JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C146-55JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C146-55LMB
L69
52-Square Leadless Chip Carrier
Military
35
45
55
2-69
•
-
CY7C 132/CY7C136
CY7C142/CY7C146
4
-==:=,;= CYPRESS
SEMICONDUcrOR
=-.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
IIX
1,2,3
loz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
ISB3
1,2,3
ISB4
1,2,3
Switching Characteristics
Parameter
Subgroups
Parameter
READ CYCLE
Subgroups
BUSY/INTERRUPT TIMING
tRC
7,8,9, 10, 11
tBLA
tAA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
tps
7, 8, 9,,10, 11
7, 8,9, 10, 11
WRITE CYCLE
7,8,9,10,11
twc
7, 8, 9, 10, 11
tWINS
tSCE
7, 8, 9, 10, 11
tEINS
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tINS
7,8,9,10,11
tHA
7, 8, 9, 10, 11
tOINR
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tEINR
7,8,9, 10, 11
tpWE
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
BUSY TIMING
tHD
7, 8, 9, 10, 11
tWB[24]
7, 8, 9, 10, 11
tWH
7,8,9,10,11
tBDD
7, 8, 9, 10, 11
Note:
24. CY7C142/CY7C146 only.
Document
2-70
#: 38-00061-H
Features
Functional Description
• 0.8-micron BiCMOS for high
performance
• High-speed access
-20 ns (commercial)
-25 ns (military)
The
CY7B134,
CY7B135,
and
CY7B1342 are high-speed BiCMOS 4Kx
8 dual-port static RAMs. The CY7B1342
includes semaphores that provide a
means to allocate portions of the dualport RAM or any shared resource. Two
ports are provided permitting independent, asynchronous access for reads and
writes to any location in memory. Application areas include interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics
memory.
•
•
•
•
Automatic power-down
Fully asynchronous operation
7B1342 includes semaphores
7B134 available in 48-pin DIP, 48-pin
LCC
• 7B135/7B1342 available in 52-pin
LCCIPLCC
Each port has independent control pi~:
chip enable (CE), read or write enable (R!
W), and output enable (OE). The
CY7B134/135 are suited for those systems
that do not require on-chip arbitration or
are intolerant of wait states. Therefore, the
user must be aware that simultaneous access to a location is possible. Semaphores
are offered on the CY7B1342 to assist in
arbitrating between ports. The semaphore
logic is comprised of eight shared latches.
Only one side can control the latch (semaphore) at any time. Control of a se~~
phore indicates that a shared resource IS 10
use. An automatic power-down feature is
controlled independently on each port by a
chip enable (CE) pin or SEM pin
(CY7B1342 only).
The CY7B134 is available in 48-pin DIP
and 48-pin LCe. The CY7B135 and
CY7B1342 are available in 52-pin LCC/
PLCC.
Logic Block Diagram
RJWL
-----0
R!WR
CER
OER
A11L _____-+-__---,
A10L
A11R
A10R
---+----,
.
II0 7R
IIOoL - - - - · - L . . J - - L_ _ _ _---l
IIOOR
··
··
MEMORY
ARRAY
AoL ------~_ _ _ _~
A9R
AoR
SEMAPHORE
ARBITRATION
(7B1342 only)
(7B1342 only)
(7B1342 only)
~L ~--~~-------------~
SEJifR
1342-1
Selection Guide
I
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)
Commercial
Military
Commercial
Military
7B134 20
7B135-20
7B1342-20
20
240
80
2-71
7B134 25
7B135-25
7B1342-25
25
220
260
75
80
7B134 35
7B135-35
7B1342-35
35
210
250
70
75
•
CY7B134
CY7B135
CY7B1342
~
"~PRESS
~, SEMICONDUcrOR
Pin Configurations
LCC/PLCC
DIP
Top View
Top View
7 6 5 4 3 2,1,5251 50494847
46
A3l
A.!l
ASl
Asl
A7l
ASl
Ael
I/OOl
IIO ll
I/0 2l
I/0 3l
10
11
78135
14
15
17
18
19
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
1342-3
LCC/PLCC
Top View
...J
cr:
cr:~I:::;;
cr:cr:
alw...J...J0 ...JI:::;;~...JU
~ W IW U IW
W
~ 0
"" o U
rn 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
MilitarylLJ
Ambient
Temperature
O°Cto +70°C
5V ± 10%
-40°C to +8S o C
SV ± 10%
-55°C to + 125°C
5V ± 10%
Vee
Electrical Characteristics Over the Operating Rangd 3]
7B134-20
7B135-20
7B1342-20
Parameter
Description
Min.
Test Conditions
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 4.0 rnA
7B134-25
7B135-25
7B1342-25
Max. Min.
2.4
Max.
2.. 4
7B134-35
7B135-35
7B1342-35
Min. Max.
2.. 4
Unit
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND:::; VI:::; Vee
-10
+10
-10
+10
-10
+10
Ioz
Output Leakage Current
Outputs Disabled,
GND:::;Vo:::;Vee
-10
+10
-10
+10
-10
+10
ftA
ftA
lee
Operating Current
Vee = Max.,
lOUT = ornA
220
210
rnA
260
250
ISBl
ISB2
ISB3
ISB4
Vee
0.4
0.4
2.2
2.2
2.2
0.8
Com'l
240
Mil
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIH,
f = fMAX[4]
Standby Current
(One Port TTL Level)
CEL and CER ~ VIH,
f = fMAX[4]
Standby Current
(Both Ports CMOS Levels)
Both Ports
Com'l
CE and CER ~ Vee - 0.2v,
VIN ~ Vee - O.2V
Mil
or VIN S 0.2V, f = 0[4]
25
Com'l
One Port
CEL or CER ~ Vee - 0.2V,
VIN ~ Vee - 0.2Vor
Mil
VIN S 0.2V, Active
Port Outputs, f = fMAX[4]
130
Standby Current
(One Port CMOS Level)
Com'l
80
Mil
Com'l
150
Mil
V
0.4
0.8
V
V
75
70
80
75
140
130
170
160
25
25
30
30
120
110
150
130
rnA
rnA
rnA
rnA
Capacitance[5]
Parameter
I
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Notes:
1. Pulse width < 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
4. fMAX = 1/tRC = All inputs cycling at f = lItRC (except output enable).
f = 0 meas no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
5.
6.
2-73
= 1 MHz,
Max.lbJ
Unit
10
pF
10
pF
Tested initially and after any design or process changes that may affect
these parameters.
For all packages except DIP and cerDIP (D26, P25), which have maximums of CrN = 15 pF, COUT = 15 pF.
CY7B134
CY7B135
CY7B1342
·r~=
AC Test Loads and Waveforms
O~~:=:ri : ~::
-=
=-rI
I 1
RTH
OUTPUT
= 250.0.
c=5 PF
C=30pF
-=
VTH
(a) Normal Load (Load 1)
= l.4V
1-=
· 1
Vx
(c) Three-State Delay (Load 3)
(b) Thevenin Equivalent (Load 1)
1342-6
=rI.
RTH = 250.0.
OUTPUT
1342-7
1342-6
ALL INPUT PULSES
3.0V - - - -...1,.-------s..
GND
1342-9
Switching Characteristics Over the Operating Rangd 7,8j
Parameter
Description
7B134-20
7B135-20
7B1342-20
Min. Max.
7B134-25
7B135-25
7B1342-25
Min. Max.
7B134-35
7B135-35
7B1342-35
Min. Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
20
25
20
35
25
3
3
ns
35
3
ns
ns
tACE
CE LOW to Data Valid
20
25
35
ns
tOOE
tLZOEl9, lUJ
tHZOEl9, lUJ
OE LOW to Data Valid
13
15
20
ns
tLZCEl9, lUJ
CE LOW to Low Z
tHZCEl9, lUJ
CE HIGH to HighZ
tpu
CE LOW to Power Up
tpo
CE HIGH to Power Down
OE Low to Low Z
3
3
OE HIGH to High Z
13
13
15
0
0
20
3
3
3
20
ns
3
15
ns
20
ns
35
ns
ns
0
25
ns
WRITE CYCLE
twc
Write Cycle Time
20
25
35
ns
tSCE
CE LOW to Write End
15
20
30
ns
tAW
Address Set-Up to Write End
15
20
30
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
15
20
25
ns
tso
Data Set-Up to Write End
13
15
15
ns
tHO
Data Hold from Write End
0
0
0
tHZWE LlOJ
R/W LOW to High Z
tLZWE LlOJ
R/W HIGH to Low Z
13
3
2-74
15
3
ns
20
3
ns
ns
CY7B134
CY7B135
CY7B1342
~
'~PRESS
-
)F
SEMUCONDUCTOR
Switching Characteristics Over the Operating Rangd 7,8] (continued)
Parameter
Description
7B134-20
7B135-20
7B1342-20
7B134-25
7B135-25
7B1342-25
7B134-35
7B135-35
7B1342-35
Min.
Min.
Min.
Max.
Max.
Max.
Unit
WRITE CYCLE (continued)
tWDDlllJ
Write Pulse to Data Delay
40
50
60
ns
tDDDlllJ
Write Data Valid to Read Data Valid
30
30
35
ns
SEMAPHORE TIMING[12]
tsop
SEM Flag Update Pulse (OE or SEM)
10
10
15
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tsps
SEM Flag Contention Window
5
5
5
ns
ns
Switching Waveforms
Read Cycle No. 1[13,14]
Either Port Address Access
ADDRESS
~-toHA~-tAA-;;-,-*-
DATA OUT
PREVIOUS DATA
V~XXX~================DA=I='A=V='A=L=ID===============
1342-10
Read Cycle No. 2[13,15]
SEM(20)
or CE
Either Port CE/OE Access
~,
~I('
~
~tHZCE-
tACE
~tL.ZOE-
tHZOE
tOOE-
tLZCE
DATA OUT
ICC
---
r/I
-'....
DATA VALID
""'l'-// / / / / /J
tpu
....."'"' "'"' "'"' "'
...,
_tpo
ISB~'
Notes:
7. See the last page of this specification for Group A subgroup testing information.
8. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance
9. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3.
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-toPort Delay
waveform.
12. Semaphore timing applies only to CY7B1342.
13. RJW is HIGH for read cycle.
14. Device is continuously selected, CE = VIL and OE = VIL.
15. Address valid prior to or coincident with CE transition Law.
2-75
•
CY7B134
CY7B135
CY7B1342
~
.
;~PRESS
~,
SEMICONDUCTOR
Switching Waveforms
Read Timing with Port-to-Port Delay[16]
twc
)K
ADDRESSR
)K
MATCH
tpWE
~~
/
V
~t
,---tSD
)K
DATAINR
ADDRESSL
VALID
MATCH
tDDD
~
)k
DATAOUTL
tWDD
VALID
~
1342-12
Write Cycle No.1: OE Three-States Data I/Os (Either Port)[17,18,19]
~--------------------------twc--------------------------~
ADDRESS
SEti,1(20)
ORCE
R!W
----+----
0..
20
o
0
~
SUPPLY VOLTAGE
0.91----;1'-----+-------1
~
0 0.75
w
N
::i
~0.50
/
a:
oz
o
-'v
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE M
I
1
60
50
0.0
~
1/
1.0
Vee = 5.0V 1 TA = 25°C
I
I
2.0
3.0
OUTPUT VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0
5.0
M
NORMALIZED Icc vs. CYCLE TIME
1.25
20.0
./
Cil15.0
I--
V
.s
/V
~
;C 10.0
!:i
w
o
V
N
~
a:
Vee = 4.5V
TA = 25°C
I
o
o
Vee = 5.0V
TA=25°C
...9
VIN = 0.5V
fa 1.01---+--+----1--,1
()
~ 0.751---t---+-----::;",c....-I---I
5.0
5.0
J
::::>
AMBIENT TEMPERATURE (0C)
/
0.25
0.0
I
/
70
0.8 '---_ _ _---J_ _ _ _ _ _ _.....J
-55
25
125
5.0
V
z
0..
I-
"- to--
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
80
I-
M
17
r\
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE M
~
Ci5
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.0
o
z 90
w
a:
a:
::::>
0
0.95 '--_--'-_ _-'-_---JL...-_.....J
4.5
5.0
5.5
6.0
4.0
Vee = 5.0V
TA = 25°C
I-
()
1.01---------1!C-------1
a:
~ 1.00 1---~--~----J----1
1\
\
60
::::>
N
~
80
.s
1- 1.1 I------+--~----I
J.
~
()
§
oCJ)
« 100
1.2
1.10
~
\
I-
0.2
0.6 '--_ _ _---l_ _ _ _ _.....J
25
125
-55
AMBIENT TEMPERATURE (0C)
6.0
\
::::>
ISB3
~ 0.61--------+-V- -=-5-.0-V---1
ee
~ 0.4 1-_ _ _---J----.:V..!!:IN!...=--::.5:..;;.0..:,.V_-I
a:
oZ
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
w
~ 100
()
ow
0.4
z
g140
~ 120
.2 0.8
~
~
-
I
200 400 600 800 1000
CAPACITANCE (pF)
2-80
20
30
40
CYCLE FREQUENCY (MHz)
50
.
CY7B134
CY7B135
CY7B1342
·~PRFSS
.r
SEMICONDUCTOR
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1YPe
Operating
Range
20
CY7B134- 20PC
P25
48-Lead (600-Mil) Molded DIP
25
CY7B134- 25PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7B134- 25PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7B134- 25DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7B134- 25LMB
L68
48-Square Leadless Chip Carrier
CY7B134 - 35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7B134-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7B134-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7B134-35LMB
L68
48-Square Leadless Chip Carrier
35
Commercial
Speed
(ns)
Ordering Code
Package
Name
Package 1YPe
Operating
Range
Commercial
20
CY7B135-20JC
J69
52-Lead Plastic Leaded Chip Carrier
25
CY7B135-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B135-25JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B135 - 25LMB
L69
52-Square Leadless Chip Carrier
Military
CY7B135-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B135-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B135-35LMB
L69
52-Square Leadless Chip Carrier
Military
35
Speed
(ns)
Ordering Code
Package
1YPe
Package 1YPe
Operating
Range
20
CY7B1342-20JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
25
CY7B1342-25JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B1342-25JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B1342-25LMB
L69
52-Square Leadless Chip Carrier
Military
CY7B1342-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7B1342-35JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7B1342-35LMB
L69
52-Square Leadless Chip Carrier
Military
35
2-81
•
CY7B134
CY7B135
CY7B1342
-=¥-=,
:'~PRFSS
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
IIX
1,2,3
loz
los
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
ISB3
1,2,3
ISB4
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7,8,9,10,11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
SEMAPHORE CYCLE
tSOD
7, 8, 9, 10, 11
tSWRD
7, 8, 9, 10, 11
tsps
7,8,9,10,11
Document #: 38-00161-B
2-82
CY7B138
CY7B139
4K X 8/9 Dual-Port Static RAM
Ea,:i~~ ~s~!~~~~~~~~~:
Features
Functional Description
• O.8-micron BiCMOS for high performance
• High-speed access
-15 ns (com'l)
-25 ns (mil)
• Automatic power-down
• Fully asynchronous operation
• Master/Slave select pin allows bus
width expansion to 16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Available in 68-pin LCC/PLCC/PGA
• TTL compatible
The CY7B138 and CY7B139 are highspeed BiCMOS 4K x 8 and 4K x 9 dualport static RAMs. Various arbitration
schemes are included on the CY7B138/9
to handle situations when multiple processors access the same piece of data. Two
ports are provided permitting independent, asynchronous access for reads and
writes to any location in memory. The
CY7B138/9 can be utilized as a standalone 64-Kbit dual-port static RAM or
multiple devices can be combined in order
to function as a 16/18-bit or wider master/
slave dual-port static RAM. An MIS pin is
provided for implementing 16/18-bit or
wider memory applications without the
need for separate master and slave devices
or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
chiE....enable (CE), read or write enable
(R/W), and output enable (OE). Tho flags
are provided on each port (BUSY and
INT). BUSY signals that the port is trying
to access the same location currently being
accessed by the other port. The interrupt
flag (INT) permits communication between ports or systems by means of a mail
box. The semaphores are used to pass a
flag, or token, from one port to the other to
indicate that a shared resource is in use.
The semaphore logic is comprised of eight
shared latches. Only one side can control
the latch (semaphore) at any time. Control
of a semaphore indicates that a shared resource is in use. An automatic power-down
feature is controlled independently on
each port by a chip enable (CE) pin or
SEMpin.
The CY7B138 and CY7B139 are available
in 68-pin LCCs, PLCCs, and PGAs.
Logic Block Diagram
R/WL _ _ _ _.(1
R/WR
CER
OER
A11L
A10L
(7B139)
:~g~~
----4---.....,
----4--.....,
A11R
A10R
___J_~~~I..l.----I~-1
I/OsR (7B139)
I/0 7R
I/L_ _ _~"
:
1I0 oL _-_ _ _ _+1
I
I/OOR
BUS"i'R[1,2J
BOSYL[1,2J - . . . . . . - - - - - - - - _....
~L-!_--~~------~
--
--
MEMORY
ARRAY
AoL-t---~~______--1
AoL
AoR
A11R
A11L
CE L
A9R
INTERRUPT
SEMAPHORE
ARBITRATION
OE L
AoR
CER
OER
R/WL
R/WR
~L ---------------------~
IJIITL[2J - - - - - - - - - - - - - - - - - - - '
8138-1
MIS
Notes:
1.
BUSY is an output in master mode and an input in slave mode.
2.
2-83
Master: push-pull output and requires no pull-up resistor.
II
en
:::E
c:c
a::
tJ)
CY7B138
CY7B139
·4
~ICYPRESS
"'""'=IIIIr ~
SEMICONDUCTOR
Pin Configurations
68-PinPGA
68-Pin LCC/PLCC
Top View
51
50
AaL
~L
48
A2L
46
44
AoL !roSYL
53
52
49
47
45
A7L
AeL
A3L
A1L
IlilTL
42
MIS
43
41
GND !roSYA
40
IlilTR
~ a~
AaR
39
37
35
34
AoR
A2R
~R
AaR
55
54
32
33
A9L
ASL
A7R
AeR
57
56
30
31
A11L
A10L
AeR
AsR
59
58
NC
28
29
Vee
A11R
A10R
61
NC
60
NC
26
GND
27
NC
63
smL
62
CEL
24
NC
25
NC
65
64
R/WL
22
23
smR
CER
67
66
I/OOL NC[4]
20
OER
21
R/WR
18
19
OEL
78138/9
68
1
3
1/0 1L
1/0 2L
1/0 4L
5
GND
2
4
I/OSL
6
I/OeL
1/0 3L
7
1/0 7L
9
GND
1/0 1R
8
10
12
11
13
15
...J
Top View
u...J
~...J...J
...J
gg ~I~~I~I~ ~ ~~~.j;.f>"I/>
36
38
A1R
Vee 1/0 4R 1/0 7R NC[3]
14
16
8138-3
17
Vee I/OOR 1/0 2R 1/0 3R I/OSR I/0eR
8138-2
Notes:
3. I/OSR on the CY7B139.
4. I/OSL on the CY7B139.
Pin Definitions
Left Port
Right Port
Description
I/00L-7L(BL)
I/00R-7R(BR)
Data Bus Input/Output
AoL-llL
CEL
AoR-llR
CER
Address Lines
OEL
OER
Output Enable
R/WL
SEML
RIWR
ReadIWrite Enable
SEMR
Semaphore Enable. When asserted LOW, allows access to eight semaphores.
The three least significant bits of the address lines will determine which semaphore to write or read. The 1/00 pin is used when writing to a semaphore.
Semaphores are requested by writing a 0 into the respective location.
INTL
INTR
Interrupt Flag. INTL is set when rig.h!.£ort writes location FFE and is cleared
when left port reads location FFE. INTR is set when left port writes location
FFF and is cleared when right port reads location FFF.
BUSYL
BUSYR
Busy Flag
Chip Enable
M/S
Master or Slave Select
Vee
GND
Power
Ground
Selection Guide
Maximum Access Time (ns)
Maximum 00erating
Current (rnA
Maximum Standby
Current for ISB1(rnA)
Commercial
7B138-15
7B139-15
15
7B138-25
7B139-25
25
7B138-35
7B139-35
35
260
220
210
280
250
75
70
80
75
Military
90
commercial
Military
2-84
CY7B138
CY7B139
·~PRFSS
·
,
SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................ - 65 ° C to + 150 ° C
0
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential ....... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to + 7.0V
DC Input Voltage[5] .................... - O.5V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto + 70°C
5V ± 10%
Industrial
-40°C to + 85°C
5V ± 10%
Military[6]
- 55°C to + 125°C
5V ± 10%
Range
Commercial
Electrical Characteristics Over the Operating Range[7]
Parameter
Description
VOH
Output HIGH Voltage
VOL
VIR
Output LOW Voltage
VIL
Input HIGH Voltage
Input LOW Voltage
7B138-25
7B138-15
7B139-15
7B139-25
Min. Max. Min. Max.
Test Conditions
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 4.0 rnA
2 ..4
2.4
Vee
0.4
IIX
Input Leakage Current
GND~VI~Vee
-10
loz
Output Leakage Current
-10
lee
Operating Current
Output Disabled, GND ~ Va ~ Vee
Com'l
Vee = Max.,
lOUT = ornA,
MilJInd
Outputs Disabled
ISBl
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIR,
f = fMAX[8]
Standby Current
(One Port TTL Level)
CEL and CER ~ VIR,
f = fMAX[8]
Standby Current
(Both Ports CMOS Levels)
Both Ports
CE and CER ~ Vee - 0.2y,
VIN ~ Vee - 0.2V
MilJInd
or V IN ~ 0.2Y, f = 0[8]
25
Com'l
One Port
CEL or CER ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
MilJInd
VIN ~ 0.2Y, Active
Port Outputs, f = fMAX[8]
140
ISB2
ISB3
ISB4
0.4
0.8
Standby Current
(One Port CMOS Level)
Com'l
MilJInd
Com'l
MilJInd
Com'l
2 ..4
2.2
2.2
+10
+10
260
7B138-35
7B139-35
Min. Max.
0.4
V
V
0.8
V
V
+10
+10
210
!J.A
!J.A
rnA
2.2
0.8
-10
+10
-10
-10
+10
220
-10
Unit
280
250
90
75
70
75
160
80
140
rnA
130
rnA
25
160
25
rnA
30
30
120
110
150
130
180
rnA
Capacitance[9]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
5. Pulse width < 20 ns.
6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing information.
8.
9.
2-85
= 1 MHz,
Max.
Unit
10
15
pF
pF
fMAX = lItRC = All inputs cycling at f = lItRC (except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby ISB3.
Tested initially and after any design or process changes that may affect
these parameters.
~
CY7B138
CY7B139
ti ;~PRFSS
. , SEMICONDUCTOR
AC Test Loads and Waveforms
5V
OUTPUT
:rl
C = 30 pF
I
--
5V
R1 = 893.\1
RTH = 250.\1
~==TI
~
1
R2 = 347.\1
--
OUTPUT
(b) Thevenin Equivalent (Load 1)
B138-4
I
-=
VTH= 1.4V
(a) Normal Load (Load 1)
:rl
C = 5 pF
R1 = 893.\1
R2 = 347.\1
-=
(c) Three-State Delay (Load 3)
B138-5
B138-6
ALL INPUT PULSES
OUTPUT~
I
3.0V - - - -...1r-------s...
C=30pF
Load (Load 2)
GND
B138-7
B138-8
Switching Characteristics Over the Operating RangdlO,ll]
Parameter
Description
7B138-15
7B139-15
Min. Max.
7B138-25
7B139-25
Min.
Max.
7B138-35
7B139-35
Min.
Max.
Unit
READ CYCLE
15
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE
CE LOW to Data Valid
tOOE
tLZOE[12. 13]
OE LOW to Data Valid
tHzOE[12, 13]
OE HIGH to High Z
tLZCE[12, 13]
CE LOW to Low Z
tHZCE[12, 13]
CE HIGH to High Z
tpu
CE LOW to Power-Up
tpo
WRITE CYCLE
CE HIGH to Power-Down
twc
Write Cycle Time
tSCE
CE LOW to Write End
15
12
tAW
Address Set-Up to Write End
12
tHA
Address·Hold From Write End
tSA
tpWE
Address Set-Up to Write Start
tso
Data Set-Up to Write End
tHO
tHZWE[13]
Data Hold From Write End
2
0
12
10
0
3
tDDn[14]
Write Data Valid to Read Data Valid
3
3
0
3
0
15
0
25
20
20
2
0
20
15
0
10
3
35
30
30
2
0
25
15
0
3
30
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
3
50
30
ns
ns
35
15
ns
ns
20
25
ns
ns
20
15
ns
ns
35
20
15
10
2-86
3
3
3
ns
35
25
15
10
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
3
3
Write Pulse Width
35
25
15
10
OE Low to Low Z
tLZWE[13]
twoO[14]
25
15
ns
ns
60
35
ns
ns
~
.
CY7B138
CY7B139
'~PRESS
===='..'
SEMlCONDUcrOR
Switching Characteristics Over the Operating Range[lO, 11] (continued)
Parameter
BUSY TIMING[15]
7B138-15
7B139-15
Min.
Max.
Description
7B138-25
7B139-25
Min.
Max.
7B138-35
7B139-35
Max.
Min.
Unit
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
tBHC
tps
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
15
15
20
20
20
20
ns
ns
Port Set-Up for Priority
5
WE LOW after BUSY LOW
5
0
5
tWB
0
0
ns
ns
WE HIGH after BUSY HIGH
tWH
BUSY HIGH to Data Valid
tBDD
INTERRUPT TIMING[15]
13
15
20
30
ns
25
35
ns
INTSetTime
tINS
INT Reset Time
tINR
SEMAPHORE TIMING
SEM Flag Update Pulse (OE or SEM)
tsop
SEM Flag Write to Read Time
tSWRD
15
25
25
ns
15
25
25
ns
tsps
SEM Flag Contention Window
Notes:
10. See the last page of this specification for Group A subgroup testing information.
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOIlIoH and 30-pF load capacitance.
12. At any given temperature and voltage condition for any given device,
tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10
5
10
5
15
5
ns
ns
5
5
5
ns
13. Test conditions used are Load 3.
14. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port -to-Port Delay
waveform.
15. Test conditions used are Load 2.
2-87
II
CY7B138
CY7B139
S;;:=
-==-' ~
SEMICONDUCTOR
*_
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access)[16, 17]
----t=_ _ _
tRC
ADDRESS
DATA OUT
_ _
--t= ~HA:::::i
~
1
vALID%xxxxx
)k.,.._-_-_-_-_-_-_-_-_-_-_-_-_-_-D_A-I~A~V~A~L_I-D~~~~~~~~~~~~~~
..
PREVIOUS DATA
8138-9
Read Cycle No.2 (Either Port-CE/OE Access)[16, 18, 19]
SEMorCE
~,
~~
~
-tHZCE-
tACE
~tLZOE----"
tHZOE
tDOE-'
tLZCE
...,c...////////
DATA OUT
ICC
ISB
---
tpu
r-
..3 ....
,
DATA VALID
-'r-'\.'\.'\.'\.'\.'\.'\."
....
4--tpD
/I
--./
.
Read Timing with Port-to-Port Delay (MiS = L)[20, 21]
twc
ADDRESSR
)K
)(
MATCH
tpWE
~~
/'
~tSD
DATA INR
ADDRESSL
)K
)(
VALID
~t
MATCH
..
tDDD
)(
DATAoUTL
)E
tWDD
8138-11
Notes:
16. R/W is HIGH for read cycle.
17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
18. Address valid prior to or coincident with ~E transition LOW.
19. CEL = L, SEM = H when accessing RAM. CE
accessing semaphores.
20. BUSY = HIGH for the writing port.
21. CEL = CER = LOW.
2-88
= H, SEM = L when
.
CY7B138
CY7B139
:~PRESS
-==::t:::Ir,
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1: OE Three-States Data IJOs (Either Port)[22, 23, 24]
I
~--------------------------------------------------------twc------------------------------------------------------------~
ADDRESS
SEMORCE
R/W ---+---_~-_ 14-------tpwE --------.1
.'. tHD~
j;==tSD
DATA IN ----------------------------------------------------~
HIGH IMPEDANCE
,,--_________
DATA VALID
~--------
~
B138-12
Write Cycle No.2:
R/W Three-States Data I/Os (Either Port)[22, 24, 25]
~----------------------------------twc----------------------------~~
ADDRESS
SEMORCE
R/W
DATA IN
DATA OUT
B138-13
Notes:
22. The internal write tim~f the memory is defined by the overlap of CE
or SEM LOW and R/W Law. Both signals must be LOW to initiate
a write, and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
23. If OE is LOW during a R!W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHZWE + tso) to allow the I/O
drivers-.!Q. turn off and data to ~ placed on the bus for the required
tso.1f OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tpWE.
24. R!W must be HIGH during all address transitions.
25. Data I/O pins enter high impedance when OE is held LOW during
write.
2-89
,;;?~
_~
CY7B138
CY7B139
SEMICONDUCIOR
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[26]
1/00
DATAouT VALID
---~---tDOE --~
Bl38-14
Timing Diagram of Semaphore Contention[27, 28, 29]
AoL -A2L
RiWL
S"EML
AOR- A2R
MATCH
-------------------------------><-------------
E~psMATCH
R/WR
;~
~R
;~
B138-15
Notes:
26. CE = HIGH for the duration of the above timing (both write and read
cycle).
rn
27. I/OOR = I/OOL = LOW (request semaphore);
R = eEL = HIGH
28. Semaphores are reset (available to both ports) at cycle start.
29. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
2-90
.
CY7B138
CY7B139
J~
~=CYPRESS
-:::;;;;;;;iF
SEMICONDUcrOR
Switching Waveforms (continued)
•
Timing Diagram of Read with BUSY (M/S=HIGH)[21j
twc
)~
ADDRESSR
)(
MATCH
tPWE
}~
"\,
.....--tSD
)(
DATAINR
tps
ADDRESS L
)(
VALID
I+---.
)(
~t
MATCH
tBLA
J tBHA
BOSYL
tBDD_
tDDD
)~
DATAOUTL
)E
tWDD
B138-16
Write Timing with Busy Input (M!S=LOW)
R/W
-J-
tPWE
-i
-t-tW"~ f_~H:1_B138-17
2-91
f~PR&SS
~~
CY7B138
CY7B139
S8MUCONDUCTOR
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[30]
CEL Valid First:
______)xC~______________A_D_D_R_ES_S_M_A_J_C_H________________J)x(~______________
ADDRESSL,R
CER Valid First:
______J)xC~______________A_D_D_R_E_S_S_M_A_J_C_H_________________')xC~_______________
ADDRESSL,R
Busy Timing Diagram No.2 (Address Arbitration)[30]
Left Address Valid First:
1 + - - - - tRG or tWG
-----1~
ADDRESSL ------~
,-----------------,
ADDRESS MISMATCH
ADDRESSR
BUSYR
8138-20
Right Address Valid First:
------,
ADDRESS R
1 + - - - - tRG or tWG
-----1~
~----------------,
ADDRESS MISMATCH
ADDRESSL
BUSYL
8138-21
Note:
30. If tps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
2-92
.
CY7B138
CY7B139
:~
======
= CYPRESS
-:::;;;;;;F SEMICONDUCTOR
Switching Waveforms (continued)
•
Interrupt Timing Diagrams
Left Side Sets INTR:
~---------------twc ----------~~
ADDRESSL
WRITE FFF
CEL
fl---XXXXXXXXXXXxXX ______
---_1'-_______________________
tINS[32]
Right Side Clears OOR!
ADDRESSR
tRC
-----lj-t ~
6138-22
_~
RE_AD_FF_F
______
~---------------
CER
14------ tINR[32]
--------------.t
OER
MR
6138-23
Right Side Sets INTL!
.....- - - - - - - twc
ADDRESS R
-------~
WRITEFFE
1 4 - - - tINS[32]
-----1'------------------------
6138-24
Left Side Clears INTL
ADDRESS R
~"'I-----
XXXXXXXXXXXXX21'______
tRC
----~~ ~
_~_ __
REA_D_FF_E
GEL
.....- - - - - - - tINR[32]
---------~
DEL
6138-25
Notes:
31. tHA depends on which enable pin (CEL or RiWL) is deasserted first.
32. tINS or tINR depends on which enable pin (CEL orRiWL) is asserted
last.
2-93
&:L~PRFSS
~,
CY7B138
CY7B139
SEMICONDUCTOR
Architecture
The CY7B138/9 consists of an array of 4K words of 8/9 bits each of
dual-~t ~M cells, I/O and address lines, and control signals
(CE,OE, R/W). These control pins permit independent access for
reads or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port. Two interrupt (INT) pins can be utilized forport-to-port communication. 1Wo semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7B138/9 can
function as a master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B138/9 has an automatic power-down
feature controlled by CEo Each port is provided with its own output
enable control (OE), which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No.1 waveform) or
the R/W pin (see Write Cycle No.2 waveform). Data can be written
to the device tHZOE after the OE is deasserted or tHZWE after the
falling edge of RiW. Required inputs for non-contention operations are summarized in Table 1.
It a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port wishing
to read the location tDDD after the data is presented on the other
port.
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tDOE after OE is asserted. It the user of the CY7B138/9 wishes to access a se~hore
flag, then the SEM pin must be asserted instead of theCE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports. When the left port writes to location FFF, the right port's interrupt flag (INTR) is set. This flag is cleared when the ri~ort
reads that same location. Setting the left port's interrupt flag (INTL) is
accomplished when the right port writes to location FFE. This flag
is cleared when the left port reads loc~tion FFE. The message at
FFF or FFE is user-defined. See Table 2 for input requirements for
INT. INTRand Il'ffLare push-pull outputs and do not require pullup resistors to operate. BUSYL and BUSYR in master mode are
push-pull outputs and do not require pull-up resistors to operate.
HIGH input, the M/S pin allows the device to be used as a master
and therefore the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave.
Semaphore Operation
The CY7B138/9 provides eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to
reserve resources that are shared between the two ports. The state
of the semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its
success in settin.£!!le latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tsop before attempting
to read the semaphore. The semaphore value will be available
tSWRD + tDOE after the rising edge of the semaphore write. It the
left port was successful (reads a zero), it assumes control over the
shared resource, otherwise (reads a one) it assumes the right port
has control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a one),
the left side will succeed in gaining control of the a semaphore.!f
the left side no longer requires the semaphore, a one is written to
cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). Ao-2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. It a zero is written to the left port of an unused semaphore, a one will appear at the
same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). It the left port now relinquishes control by writing a one to
the semaphore, the semaphore will be set to one for both sides.
However, ifthe right port had requested the semapho're (written a
zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table
3 shows sample semaphore operations.
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Table 1. Non-Contending ReadIWrite
Busy
Outputs
Inputs
The CY7B138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). It both ports' CEs are
asserted and an address match occurs within tps of each other the
Busy logic will determine which port has access. It tps is violated,
one port will definitely gain pymission to the location, but it is not
guaranteed which one. BUS will be asserted tBLA after an address match or tBLC after CE is taken LOW.
.
Master/Slave
CE
2-94
~EM
1/0 0-7
Operation
H
X
X
H
HighZ
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
X
X
H
X
HighZ
I/O Lines Disabled
X
L
Data In
Write to Semaphore
H
L
H
Data Out
Read
L
L
X
H
Data In
T
v
v
T
H
A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will
allow the device to interface to a master device with no external
components.\l/riting of slave devices must be delayed until after
the BUSY input has settled. Otherwise, the slave chip may begin a
write cycle during a contention situation. When presented as a
RIW OE
L
S
Write
I
Tll ............... 1,-... .... _....J! ... ! .... _
J.llv~'ll vUllUlUUll
CY7B138
CY7B139
~
CYPRFSS
--=-,
o
_olE
SEMICONDUcrOR
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Function
R/W
X
X
L
X
Set Left INT
Reset Left INT
Set Right INT
Reset Right INT
CE
X
L
L
X
Left Port
OE Ao-ll
X
X
L
FFE
FFF
X
X
X
Table 3. Semaphore Operation Example
Function
No action
Left port writes
semaphore
Right port writes 0
to semaphore
Left port writes 1 to
semaphore
Left port writes 0 to
semaphore
Right port writes 1
to semaphore
Left port writes 1 to
semaphore
Rig!).t port writes 0
to semaphore
Right port writes 1
to semaphore
Left port writes 0 to
semaphore
Left port writes 1 to
semaphore
1/00
Left
1
0
1/00
Right
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
1
1
Status
Semaphore free
Left port obtains
semaphore
Right side is denied
access
Right port is granted
access to semaphore
No change. Left port
is denied access
Left port obtains
semaphore
No port accessing
semaphore address
Right port obtains
semaphore
No port accessing
semaphore
Left port obtains
semaphore
No port accessing
semaphore
2-95
INT
L
H
X
X
R/W
L
X
X
X
CE
L
X
X
L
Right Port
OE Ao-ll
X
FFE
X
X
X
X
L
FFF
INT
X
X
L
H
II
~
CY7B138
CY7B139
.11L~NDUcrOR
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
ll1.2
j
1.0
8
0.8
N
::J
~ 0.6
lee~
-'
~
II
1.0 I-----=-t.~=-----l
.2 0.8
ISB3
~ 0.61------+-- -=-5-.0-V--l
5.0
5.5
SUPPLY VOLTAGE
80
0.21------+------1
~
c..
40
0~575----725~----~125
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
N
::J
1.1
Cl
~
a::
~ 1.0
W
, I"-......
N
::J
~
4.5
-----TA = 25°C
0.9
0.8
4.0
5.0
5.5
SUPPLY VOLTAGE
a:: 1.0
0
z
0.8
0.6
-55
6.0
M
1.00
/
!r
0 0.75
w
N
::J
~0.50
a::
oz
0.0
o
-
I--
1.0
/
2.0
25
60
enZ
~ 40
c..
I-
20
~
o
5.0
4.0
M
-
I
/
V
0.0
1 .0
2.0
Vee = 5.( V _
TA = 25° P
I
3.0
4.0 5.0
OUTPUT VOLTAGE
M
NORMALIZED Icc vs. CYCLE TIME
1.25
25.0
(,)
en
~
~ 15.0
~
:..J
~ 10.0
5.0
3.0
If
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
5.0
2.0
/
80
:lC::
125
5.20.0
SUPPLY VOLTAGE M
a
30.0
V
4.0
~ 100
AMBIENT TEMPERATURE (0C)
I
/
3.0
V--
Vee = 5.0V
"
.......
1.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
a::
o
TYPICAL POWER·ON CURRENT
vs. SUPPLY VOLTAGE
0.25
--
1.2
«
,
Vee = S.OV
TA = 25°C
120
~
J1.4
r-....
o
1\\
OUTPUT VOLTAGE
5..
1.3
1.2
0
« 140
1.6
1.4
«
o~
AMBIENT TEMPERATURE (0C)
M
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
J
u
§
oC/)
oz
~
w
~
VIN = 5.0V
a:: 0.4 I------+-"'-'------l
0.2
4.5
~ 160 \..
~
Vee
0.0
4.0
I-
u 120
w
a::
0.4
z
8
ISB3
Cl
o
g 200
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
a::
a::
(,)
...- ,..,~
~
V
i-""'"
---
Vee = 4.5V
TA = 2SoC
o 1/
o
I
8
Vee = 5.0V
TA=25°C
VIN = O.sv
1.01------t------ir---":OII
N
~
a::
~ 0.751------t-""7"!::------ir----l
-
I
200 400 600 800 1000
CAPACITANCE (pF)
2-96
...9
0.50 ":-----:'-:------'":-----'
10
28
40
66
CYCLE FREQUENCY (MHz)
_
-..
,
CY7B138
CY7B139
~
~.iE
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
15
25
35
Speed
(ns)
15
25
35
Ordering Code
CY7B138-15GC
Package
Name
G68
Package 'lYpe
68-Pin Grid Array (Cavity Down)
Operating
Range
Commercial
CY7B138-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B138-25GC
G68
68-Pin Grid Array (Cavity Down)
CY7B138-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B138-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B138-25LMB
LS1
68-Square Leadless Chip Carrier
Military
CY7B138-35GC
G68
68-Pin Grid Array (Cavity Down)
Commercial
CY7B138-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B138-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B138-35LMB
L81
68-Square Leadless Chip Carrier
Military
Ordering Code
Package
'lYpe
Package 1YPe
Commercial
Operating
Range
Commercial
CY7B139-15GC
G68
68-Pin Grid Array (Cavity Down)
CY7B139-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B139-25GC
G68
68-Pin Grid Array (Cavity Down)
CY7B139-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B139-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B139-25LMB
LS1
68-Square Leadless Chip Carrier
Military
CY7B139-35GC
G68
68-Pin Grid Array (Cavity Down)
Commercial
CY7B139-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7B139-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B139-35LMB
LS1
68-Square Leadless Chip Carrier
Military
2-97
•
·=§.;rlPR£§
CY7B138
CY7B139
~, SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7,8,9,10,11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
loz
los
1,2,3
tDOE
7, 8, 9, 10, 11
1,2,3
WRITE CYCLE
Icc
1,2,3
twc
7,8,9, 10, 11
ISBI
1,2,3
tSCE
7,8,9, 10, 11
ISB2
1,2,3
tAW
7,8,9,10,11
ISB3
1,2,3
tHA
7,8,9, 10, 11
ISB4
1,2,3
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
READ CYCLE
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
tps
7,8,9, 10, 11
tINS
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
BUSY TIMING
tWB
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBDD
7, 8, 9, 10, 11
tDDD
7, 8, 9, 10, 11
tWDD
7, 8, 9, 10, 11
Document #: 38-00162-E
2-98
CY7B144
CY7B145
CYPRESS
SEMICONDUCTOR
8K X 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
Functional Description
• O.8-micron BiCMOS for high performance
• High-speed access
-15 ns (commercial)
- 25 ns (military)
The CY7B144 and CY7B145 are highspeed BiCMOS 8K x 8 and 8K x 9 dualport static RAMs. Various arbitration
schemes are included on the CY7B144/5
tohandlesituationswhenmultipleprocessors access the same piece of data. Two
ports are provided permitting independent, asynchronous access for reads and
writes to any location in memory. The
CY7B144/5 can be utilized as a standalone
64-Kbit dual-port static RAM or multiple
devices can be combined in order to function as a 16/18-bit or wider master/slave
dual-port static RAM. An Mis pin is provided for implementing 16/18-bit or wider
memory applications without the need for
separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering,
and dual-port video/graphics memory.
• Automatic power-down
• Fully asynchronous operation
• Master/Slave select pin allows bus
width expansion to 16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Available in 68-pin LCC/PLCC/PGA
• TTL compatible
Each port has independent control pins:
chiE....enable (CE), read or write enable
(RIW), and~utenable (OE). Two flags,
BUSY and INT, are provided on each port.
BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag
(INT) permits communication between
ports or systems by means of a mail box.
The semaphores are used to pass a flag, or
token, from one port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight
shared latches. Only one side can control
the latch (semaphore) at any time. Control
of a semaphore indicates that a shared resource is in use. An automatic power-down
feature is controlled independently on
each port by a chip enable (CE) pin or
SEMpin.
The CY7B144 and CY7B145 are available
in 68-pin LCCs, PLCCs, and PGAs.
Logic Block Diagram
R/WR
CER
GER
(7B145)
A12L
A10L
----1---...,
:j~~
___.J._~~c--lI.L~-lr~..J
I/OOL
A12R
Al0R
----"---1----.
-
IIOaR (7B145)
1/0 7R
I/L----',\I
------~
IIOOR
BOS'i'L1l: , : : , 2 : ; , . 1 _ . _ - - - - - - - -....
A9L
AoL
BOS'i'R1l ,2]
--1----./------,
--
.--
MEMORY
ARRAY
-t---~----~
GEL
INTERRUPT
SEMAPHORE
ARBITRATION
GEL
AoR
GER
GER
R/WR
RtWL
~L --------------------~
JfilTL[21
AoR
A12R
A12L
AoL
A9R
-.-------------1
B144-1
MIS
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2.
2-99
Master: push-pull output and requires no pull-up resistor.
•
CY7B144
CY7B145
~~PRFSS
~,
SEMICONDUCTOR
Pin Configurations
68·PinPGA
Top View
51
50
~L
ASL
52
53
A7L
55
AaL
43
45
rnTR
41
GND BUS'i'F
rnTL
40
42
MIS
39
AoR
38
A1R
37
A2R
56
59
76144/5
NC
10
11
AsR
1I0 4L
1I0 5L
12
13
31
GND
AaR
1/0 6L
33
62
A11R
A10R
GND
26
27
IIOOR
19
A12R
1I0 1R
29
24
NC
RiWL
SEMR
CER
67
66
20
21
I/OOL
NC[4]
OER
R/WR
68
1
3
5
7
9
11
18
19
1I0 1L
1/0 2L
1/0 4L
GND
1/0 7L
GND
1/0 1R
2
4
6
1I0 3L
IIOSL
1/0 6L
10
8
Vee
IIOOR
Vee
12
15
1/0 4R
23
14
16
17
1/0 5R
1I0 6R
60
59
58
57
56
55
54
53
52
51
50
49
48
76144/5
1I0 5R
1I0 6R
26
AsL
~L
~L
A2L
A1L
AoL
rnTL
BUS'i'L
GND
MIS
BUS'i'R
rnTR
AoR
47
46
A1R
45
44
~R
A2R
~R
V~~~~~.34~~~~~~MG~
II:-
II:
II: II: 1I:t)t) 0
g ~1t'5~ § Ilf z z
1I0 7R NC[3]
1/0 2R 1I0 3R
5 4 3 2 1 68 676665 64 63 62 61
1I0 2R
Vee
1I0 3R
1I0 4R
25
22
13
Vee
NC
64
OEL
1/0 7L
16
17
18
GND
CEL
65
1/0 2L
1/0 3L
28
60
9 8 7 6
34
AsR
30
A9R
A12L
63
35
~R
32
58
61
36
A3R
A7R
A10L
SElYfL
BUS'i'L
AaL
57
NC
47
A1L
44
46
AoL
54
A11L
Vee
49
~L
AsL
48
A2L
II: II: II:
II: II:
II: II: II:
~;;:;.f'.f'J:-l'.t'
6144-3
61 44-2
Notes:
3. I/OSR on the CY7B145.
4. I/OSL on the CY7B145.
Pin Definitions
Left Port
I/OOL-7L(8L)
AoL-12L
CEL
OEL
Right Port
RlWL
SEML
I/OOR-7R(8R)
AoR-12R
CER
OER
RIWR
SEMR
INTL
INTR
BUSYL
M/S
BUSYR
Description
Data bus Input/Output
Address Lines
Chip Enable
Output Enable
ReadlWrite Enable
Semaphore Enable. WhenassertedLOW,allowsaccess toeightsemaphores.
The three least significant bits of the address lines will determine which
semaphore to write or read. The lIOo pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INTL is set when right port writes location IFFE and is
cleared when left port reads location IFFE. INTR is set when left port writes
location IFFF and is cleared when right port reads location IFFF.
Busy Flag
Master or Slave Select
Power
Ground
Vee
GND
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current for ISBl (rnA)
Commercial
7B144-15
7B145-15
15
7B144-25
7B145-25
25
7B144-35
7B145-35
35
260
220
210
280
250
Military
Commercial
90
Military
2-100
75
70
80
75
CY7B144
CY7B145
;@!:~
~.a CYPRESS
F
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input VoltagelS] .•.........••.•...... - 0.5V to +7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage... .... . . . . ... . . . .... . .. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
Commercial
Industrial
Military[6]
-40°C to +85°C
5V ± 10%
-55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[7]
Description
Parameter
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
7B144-15
7B144-25
7B145-15
7B145-25
Min. Max. Min. Max.
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 4.0 rnA
2.4
Vee
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND~VI~Vee
Ioz
Output Leakage Current
Outputs Disabled, GND ~ Vo ~ Vee
lee
Operating Current
Vee = Max.,
lOUT = ornA
Outputs Disabled
Com'l
ISBl
Standby Current
(Both Ports TTL Levels)
CEL and CER ~ VIR,
f = fMAX[8]
Com'l
Standby Current
(One Port TTL Level)
CEL or CEr ~ VIR,
f = fMAX[8
Com'l
Standby Current
(Both Ports CMOS Levels)
Both Ports
CE and CER ~ Vee - 0.2y,
VIN ~ Vee - 0.2V
or VIN ~ 0.2Y, f = 0[8]
Com'l
One Port
Com'l
CELorCER~ Vee-0.2Y,
VIN ~ Vee - 0.2Vor
VIN ~ 0.2Y, Active
Mil/lnd
ISB3
ISB4
2 .. 4
0.4
VIR
ISB2
2.. 4
2.2
0.8
Standby Current
(One Port CMOS Level)
0.8
V
V
IlA
+10
-10
+10
-10
+10
-10
+10
-10
+10
-10
Mil/lnd
+10
!lA
220
210
rnA
280
250
75
70
80
75
90
Mil/lnd
160
Mil/lnd
140
130
180
160
25
25
30
30
120
110
150
130
25
Mil/lnd
140
V
0.8
-10
260
Unit
V
0.4
0.4
2.2
2.2
7B144-35
7B145-35
Min. Max.
rnA
rnA
rnA
rnA
Port Outputs, f = fMAX[8]
Capacitance[9]
Parameter
CIN
COUT
Test Conditions
Description
Input Capacitance
Output Capacitance
TA = 25°C, f
Vee = 5.0V
Notes:
5. Pulse width < 20 ns.
6. TA is the "instant on" case temperature.
7. See the last page of this specification for Group A subgroup testing information.
8.
9.
2-101
= 1 MHz,
Max.
10
15
Unit
pF
pF
fMAX = lItRC = All inputs cycling at f = lltRC (except output enable).
f = 0 means no address or control lines change. This applies only to
inputs at CMOS level standby ISB3.
Tested initially and after any design or process changes that may affect
these parameters.
II
CY7B144
CY7B145
~~PRFSS
~, SEMICONDUCTOR
AC Test Loads and Waveforms
O":~T:Opj 1::~::
RTH = 250Q
OUTPUT~
C = 30pF
1
VTH = 1.4V
(a) Normal Load (Load 1)
I
i ::~:
(c) Three-State Delay (Load 3)
(b) Thevenin Equivalent (Load 1)
8144-4
8144-5
8144-6
ALL INPUT PULSES
3.0V - - - - ~_ _ _ _-~
OUTPUT~
I
OUr:U::PF
1
C=30pF
Load (Load 2)
GND
8144-7
8144-8
Switching Characteristics Over the Operating RangellO,ll]
Parameter
READ CYCLE
Description
7B144-15
7B145-15
Min. Max.
25
7B144-35
7B145-35
Min. Max.
Unit
ns
tRe
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold From Address Change
tACE
CE LOW to Data Valid
15
25
35
ns
tOOE
tLzOE[12, 13]
OE LOW to Data Valid
10
15
20
ns
tHZOE[12, 13]
OE HIGH to High Z
tLZCE[12, 13]
CE LOW to Low Z
tHZCE[12, 13]
CE HIGH to High Z
tpu
CE LOW to Power-Up
tpo
WRITE CYCLE
CE HIGH to Power-Down
OE Low to Low Z
15
7B144-25
7B145-25
Min. Max.
15
35
25
3
3
3
15
10
15
10
15
ns
ns
35
25
ns
ns
20
0
0
0
ns
20
3
3
3
ns
ns
3
3
3
35
ns
twc
Write Cycle Time
15
25
35
ns
tSCE
CE LOW to Write End
12
20
30
ns
tAW
Address Set-Up to Write End
12
20
30
ns
tRA
Address Hold From Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
Write Pulse Width
12
20
25
ns
tso
Data Set-Up to Write End
1p
15
15
ns
tHO
tHZWE[13]
Data Hold From Write End
0
0
0
ns
tLZWE[13]
R/W LOW to High Z
R/W HIGH to Low Z
3
twoO[14]
Write Pulse to Data Delay
30
50
60
ns
toOO[14]
Write Data Valid to Read Data Valid
25
30
35
ns
2-102
20
15
10
3
3
ns
ns
~
CY7B144
CY7B145
:~pRF.SS
--=-,
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd10,1l] (continued)
Parameter
BUSY TIMINGl:>j
7B144-15
7B145-15
Min. Max.
Description
7B144-25
7B145-25
Min. Max.
7B144-35
7B145-35
Min. Max.
Unit
tBLA
BUSY LOW from Address Match
15
20
20
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
tBHC
tps
BUSY HIGH from CE HIGH
15
20
20
ns
Port Set-Up for Priority
5
5
5
ns
tWB
WE LOW after BUSY LOW
0
0
0
ns
tWH
WE HIGH after BUSY HIGH
13
20
30
ns
15
25
35
ns
BUSY HIGH to Data Valid
tBDD
INTERRUPT TIMlNGll5j
INTSetTime
tINS
INT Reset Time
tINR
SEMAPHORE TIMING
SEM Flag Update Pulse (OE or SEM)
tsop
SEM Flag Write to Read Time
tSWRD
SEM Flag Contention Window
tsps
ns
15
25
25
ns
15
25
25
ns
10
10
15
5
5
5
ns
ns
5
5
5
ns
Notes:
10. See the last page ofthis specification for Group A subgroup testing information.
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of l.Sv, input pulse levels ofOto 3.0V, and output loading
of the specified IOIlIoH and 30-pF load capacitance.
12. At any given temperature and voltage condition for any given device,
tHzCE is less than tLZCE and tHZOE is less than tLZOE.
13. Test conditions used are Load 3.
14. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay
waveform.
15. Test conditions used are Load 2.
2-103
I
CY7B144
CY7B145
,~~
*____
Switching Waveforms
Read Cycle No.1 (Either Port-Address Access)[16, 17]
~
_________
~c _ _ _ _ _ _ _
ADDRESS
--t=DA~:v;;Xxxxx*,--_-:'-:'-:'-:'-_-:'-:'-:'-:'-:'-_D-A_J-:'A-:'V-A:L_ID-:'-:'-:'-:'-_-:'-:'-:'-:'-:'-_-=_
~
1
DATA OUT
.R""DUS
B144-9
Read Cycle No.2 (Either Port-CEtOE Access)[16, 18, 19]
SEQ or'CE'
DATA VALID
DATA OUT ---I---------4I+H+4~H
tpu
~~~~~~-------------------+------~
~
Icc
ISB~
Read Timing with Port-to-Port Delay (MIS
= L)[20, 21]
twc
ADDRESSR
, R/WR
DATAINR
ADDRESSL
MATCH
)(
)(
tPWE
~"
,/
~D
~tSD
)(
)(
,
VALID
MATCH
tODD
DATAouTL
)
)E
tWDD
B144 - 11
Notes:
16. RiW is lllGH for read cycle.
17. Device is continuously selected CE = LOW and OE = LOW. This
waveform ~annot be used for semaphore reads.
18. Address valid prior to or coincident with rn transition LOW.
19. CEL = L, SEM = Hwhen accessing RAM. CE = H, SEM
accessing semaphores.
20. BO'SY = HIGH for the writing port.
21. CEL = CER = LOW.
2-104
= Lwhen
CY7B144
CY7B145
--..=.
~
~b CYPRESS
------_~
SEMUCONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1: OE Three-State Data I/Os (Either Port) [22, 23,24]
I
~-------------------------------twc------------------------------~
ADDRESS
SEMORCE
~-------------------------tAW---------------------'*-----
R/W
............... .....__..... __.....
DATA IN
~
~
..............................__.....__.....__
~~-------------tpWE----------------~ ~
E
-------------------
~:t
~~OE
=====) ) =--
HIGH IMPEDANCE
DATA OUT
.1. tH0;t
tso
DATA VALID
*-------
~
6144-12
Write Cycle No.2:
RJW Three-State Data I/Os (Either Port) [22, 24, 25,]
~-----------------------twc------------------------------~
ADDRESS
SEMORCE
R/W
DATA IN
DATA OUT
6144-13
Notes:
22. The internal write tim~f the memory is defined by the overlap of CE
or SEM LOW and R/W Law. Both signals must be LOW to initiate
a write, and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
23. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tpWE or (tHZWE + tSD) to allow the I/O
drivers to turn off and data to be placed on the bus for the required
tSD.1f OE is HIGH during a RiW controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as
short as the specified tpWE.
24. R/W must be HIGH during all address transitions.
25. Data I/O pins enter high impedance when OE is held LOW during
write.
2-105
CY7B144
CY7B145
:tC_~PRFSS
~,
SEMICONDUCTOR
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[26]
1/°0
DATA-OUT VALID
R!W
------~~---tDOE----~~
B144-14
Semaphore Contention[27, 28, 29]
~L-A2L _____________________M_A_T_C_H____________________--J)xC~
E
R!WL
SBML
____________________
-------------------------------------------------
-
tsps
SBMR __________________________
J
B144-15
Notes:
26. CE = HIGH for the duration ofthe above timing (both write and read
cycle).
27. I/OOR = I/OOL = LOW (request semaphore); CER = CEL = HIGH
28. Semaphores are reset (available to both ports) at cycle start.
29. If tsps is violated, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control the
semaphore.
2-106
CY7B144
CY7B145
~
-.
:~
==-=
---=-JF=
CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
•
Read with BUSY (M!S=HIGH)[21]
twc
)K
ADDRESSR
)K
MATCH
tPWE
~~
;',.!
~tSD
)K
DATAINR
tps
ADDRESSL
VALID
~
)~
~
~t
MATCH
~~~
I
BUSYL
tODD
DATAOUTL
tSHA
JZ~DD~
)k
VALID
tWDD
Bl44-16
Write Timing with Busy Input (M!S=LOW)
2-107
CY7B144
CY7B145
~
.aPRESS
_
IF
SEMICONDUCTOR
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration) [30]
CEL Valid First:
X
ADDRESSL,R
~tPSb
eEL
eER
X
ADDRESS MATCH
~LC=).
BUSYR
ttBHC1
8144-18
CER Valid First:
X
ADDRESSL,R
~tPSb
eER
GEL
X
ADDRESS MATCH
tB~=1
BUSYL
ttBHCl
8144-19
Busy Timing Diagram No.2 (Address Arbitration) [30]
Left Address Valid First:
\ + - - - tRC or twc - - - - + I
ADDRESS L
------~
,-----------------~
ADDRESS MISMATCH
ADDRESS R
BUSYR - - - - - - - - - - -
8144-20
Right Address Valid First:
\ + - - - tRC or twc - - - - + I
ADDRESS R
------~
,-----------------~
ADDRESS MISMATCH
ADDRESSL
BUSYL
8144-21
Note:
30. If tps is violated, the busy signal ,vill be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
31. tHA depends on which enable pin (eEL or RlWL) is deasserted first.
32. tINS or tINR depends on which enable pin (eEL or R/WL) is asserted
last.
2-108
-
CY7B144
CY7B145
~~
_ ' j E CYPRF.SS
-
JF
SEMICONDUCTOR
Switching Waveforms (continued)
•
Interrupt Timing Diagrams
Left Side Sets INTR :
~------------~G --------------~
ADDRESSl
WRITE 1FFF
U)
:IE
c(
a::
(/)
------1>1''-______________________
f----XXXXXXXXXxXXXX __
1cI---- tINS[32]
Right Side Clears ooR:
ADDRESSR
tRG
------j~ ~
6144-22
~----
RE_AD_1F_FF_......
CER
~,
tINR[32]
L////£
INTR
""""""""~K.
/'rE
6144-23
Right Side Sets INTL:
~-----------~G -------------~
ADDRESSR
WRITE 1FFE
1 4 - - - tINS[32]
-----+1''"-______________________
6144-24
J;,...I-----
Left Side Clears INTL
ADDRESSR
XXXXXXXXXXXXXXf__
tRG
------~~ ~
0¥:____
RE_AD_1F_FE_ _
GEL
~-------------
tINR[32]
-----------------+t
OEl
6144-25
2-109
CY7B144
CY7B145
~~PRESS
~_, SEMICONDUCTOR
Architecture
The CY7B144/5 consists of a an array of 8K words of 8/9 bits each
of du~ort ~M cells, I/O and address lines, and control signals
(CE,OE, R/W). These control pins permit independent access for
reads or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each
port. Two interrupt (INT) pins can be utilized forport-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the Mis pin, the CY7B144/5 can
function as a Master (BUSY pins are outputs) or as a slave (BUSY
pins are inputs). The CY7B144/5 has an automatic power-down
feature controlled by CEo Each port is provided with its own output
enable control (OE), which allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge of
RiW in order to guarantee a valid write. A write operation is con-
trolled by either the OE pin (see Write Cycle No.1 waveform) or
the R/W pin (see Write Cycle No.2 waveform). Data can be written
to the device tHZOE after the OE is deasserted or tHZWE after the
falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port wishing
to read the location tDDD after the data is presented on the other
port.
Read Operation
When reading the device, the user must assert both the OE and CE
pins. Data will be available tACE after CE or tOOE after OE are asserted. If the user of the CY7B 144/5 wishes to access a semaphore
flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location IFFF, the right port's interrupt flag (INTR) is set. This flag is cleared when the rig!!!port
reads that same location. Setting the left port's interrupt flag (INTd is
accomplished when the right port writes to location IFFE. This
flag is cleared when the left port reads location IFFE. The message
at IFFF or IFFE is user-defined. See Table 2 for input requirements for INT. INTR and INTL are push-pull outputs and do not
require pull-up resistors to operate.
Busy
write cycle during a contention situation. When presented a HIGH
input, the M/S pin allows the device to be used as a master and
therefore the BUSY line is an output. BUSY can then be used to
send the arbitration outcome to a slave.
Semaphore Operation
The CY7B144/5 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used to
reserve resources that are shared between the two ports. The state
of the semaphore indicates that a resource isin use. For example, if
the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be de asserted for tsop before attempting
to read the semaphore. The semaphore value will be available
tSWRD + tDOE after the rising edge of the semaphore write. If the
left port was successful (reads a 0), it assumes control over the
shared resource, otherwise (reads a 1) it assumes the right port has
control and continues to poll the semaphore.When the right side
has relinquished control ofthe semaphore (by writing a 1), the left
side will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a 1 is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM pin
functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). Ao-2 represents the semaphore
address. OE and RiW are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only 1/00 is used. If a 0 is written
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the
left port now relinquishes control by writing a 1 to the semaphore,
the semaphore will be set to 1 for both sides. However, ifthe right
port had requested the semaphore (written a 0) while the left port
had control, the dght port would immediately own the semaphore
as soon as the left port released it. Table 3 shows sample semaphore
operations.
When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the
other port. If both ports attempt to access the semaphore within
tsps of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
The CY7B144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports' CEs are
asserted and an address match occurs within tps of each other the
Busy logic will determine which port has access. If tps is violated,
one port will definitely gain permission to the location, but it is not
guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYLand BUSYR
in master mode are push-pull outputs and do not require pull-up
resistors to operate.
Master/Slave
An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will
allow the device to interface to a master device with no external
components.Writing of slave devices must be delayed until after
the BUSY input has settled. Otherwise, the slave chip may begin a
2-110
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
SEM
H
X
X
H
HighZ
Power-Down
H
H
L
L
Data Out
Read Data in
Semaphore
X
X
H
X
HighZ
I/O Lines Disabled
X
L
Data In
Write to Semaphore
H
S
1/0 0-7
Operation
L
H
L
H
Data Out
Read
L
L
H
Data In
Write
T
v
X
v
T
Tlla~ol r~~rI;.;~~
CY7B144
CY7B145
.;~
~~CYPRESS
~JF SEMICONDUcrOR
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Function
Set Left INT
Reset Left INT
Set Right INT
Reset Right INT
Left Port
OE
Ao-12
R/W
X
L
1FFE
H
X
CE
L
L
X
1FFF
X
X
X
X
X
L
X
X
X
X
L
L
1FFF
H
CE
X
X
X
L
L
L
X
X
Table 3. Semaphore Operation Example
Function
No action
Left port writes
semaphore
Right port writes 0
to semaphore
Left port writes 1 to
semaphore
Left port writes 0 to
semaphore
Right port writes 1
to semaphore
Left port writes 1 to
semaphore
Right port writes 0
to semaphore
Right port writes 1
to semaphore
Left port writes 0 to
semaphore
Left port writes 1 to
semaphore
1/00
Left
1
0
1/0 0
Right
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
1
1
Right Port
OE
Ao-12
INT
L
R/W
X
Status
Semaphore free
Left port obtains
semaphore
Right side is denied
access
Right port is granted
access to semaphore
No change. Left port
is denied access
Left port obtains
semaphore
No port accessing
semaphore address
Right port obtains
semaphore
No port accessing
semaphore
Left port obtains
semaphore
No port accessing
semaphore
2-111
L
INT
X
1FFE
X
L
X
X
I
CY7B144
CY7B145
'.;riPRKSS
~.... SEMICONDUCTOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
Jl1.2
lee~
13 1.0
fil
0.8
N
I--"'"
::::i
~ 0.6
~
---
I--"'"
---
oZ
0.2
4.0
4.5
ISB3
w
~ 0.6 1 - - - - - - I -- - -=-5-.0-V---l
Ve e
~ 0.4 1-_ _ _--I_V.!!.IN!...=---..:,.5-=..0_V_--1
z
0.0
ifiex:
()
Cl
ex:
o 0.4
5.0
5.5
0.21-------+------1
0.6 '--_ _ _---'_ _ _ _ _.....J
-55
25
125
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.4
1.6
1.3
J,1.4
Cl
N
N
w 1.2
«
::2:
1.1
W
r-...
::::i
"
ex:
0
z 1.0
\
1\\
()
§
oen
80
~
a..
40
o~
0
Vee = 5.0V
TA = 25°C
t\.
"
i'o..
o
1.0
2.0
3.0
4.0
5.0
OUTPUT VOLTAGE (V)
« 140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
I-
z
~ 100
~
TA = 25°C
r---r---
::2:
ex: 1.0
0
z
.----
V--
Vee = 5.0V
5
80
~
60
Z
Ci5
~ 40
a..
0.8
~ 20
o
0.8
4.0
4.5
5.0
5.5
0.6
-55
6.0
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.00
I
~
0 0 .75
w
N
::::i
~0.50
ex:
oz
0.25
o
-
~
1.0
V
2.0
25.0
SUPPLY VOLTAGE (V)
P
2.0
NORMALIZED Icc vs. CYCLE TIME
()
.J)
fil
5.20.0
~
~ 15.0
Vee = 5.0V
TA=25°C
VIN = 0.5V
1.01----+---1---...,,1
N
I--
:oJ
~ 10.0
5.0
1.0
Vee = 5,( V _
TA = 25°
I
3.0
4.0
5.0
1.25
(jj'
5.0
7
/
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
V
4.0
0.0
125
30.0
/
II
3.0
25
1/
oV
AMBIENT TEMPERATURE (0G)
SUPPLY VOLTAGE (V)
/
ex:
1.2
«
0.9
0.0
~
.s 120
Cl
::::i
160
ex:
~
() 120
w
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (0G)
SUPPLY VOLTAGE (V)
J,
g 200
I-
.2 0.8
ISB3
~
V
V "
::::i
«
::2:
ex:
~ 0.751----+-7"~-1__---1
-
Vee = 4.5V
TA = 25°C
I
I
200 400 600 800 1000
CAPACITANCE (pF)
o1/
o
2-112
0.50 '=-__--:l-::_ _~:------..J
10
28
40
66
CYCLE FREQUENCY (MHz)
CY7B144
CY7B145
~
~.a
====,
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
15
25
35
Speed
(ns)
15
25
35
Ordering Code
Package
Name
Package 1Ype
CY7B144-15GC
G68
68-Pin Grid Array (Cavity Down)
CY7B144-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B144-25GC
G68
68-Pin Grid Array (Cavity Down)
CY7B144-25JC
J81
68-Lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
en
Commercial
J81
68-Lead Plastic Leaded Chip Carrier
L81
68-Square Leadless Chip Carrier
Military
CY7B144-35GC
G68
68-Pin Grid Array (Cavity Down)
Commercial
CY7B144-35JC
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B144-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B144-35LMB
L81
68-Square Leadless Chip Carrier
Military
Package 'JYpe
G68
68-Pin Grid Array (Cavity Down)
CY7B145-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B145-25GC
G68
68-Pin Grid Array (Cavity Down)
CY7B145-25JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B145-15GC
Operating
Range
Commercial
Commercial
CY7B145-25JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B145 - 25LMB
L81
68-Square Leadless Chip Carrier
Military
CY7B145-35GC
G68
68-Pin Grid Array (Cavity Down)
Commercial
CY7B145-35JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B145-35JI
J81
68-Lead Plastic Leaded Chip Carrier
Industrial
CY7B145 - 35LMB
L81
68-Square Leadless Chip Carrier
Military
2-113
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
- O.5V to + 7.OV
Range
Commercial
Military[l]
- O.5V to +7.OV
- 3.0V to + 7.OV
Ambient
Temperature
O°C to + 70°C
Vee
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[2]
Parameter
VOH
VOL
VIR
VIL
IIX
Ioz
lee
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Vee Operating
Supply Current
ISH
Automatic CS
Power-Down Current
Ipo
Peak Power-On
Current[3]
los
Output Short
Circuit Current[4]
Test Conditions
Vee
Vee
= Min., IOH = -4.0 rnA
= Min., IOL = 8.0 rnA
GND.s VI.s Vee
GND .s V0 .s Vee Output Disabled
Com'l
Max. Veo CS .s VIL,
Output Open
Mil
Com'l
Max. Vee, CS ~ VIH 7C148
Only
Mil
Com'l
Max. Vee, CS~ VIR 7C148
Only
Mil
Com'l
GND.s Vo.s Vee
Mil
7C148/9-25
Min.
Max.
2.4
0.4
2.0
6.0
-3.0
0.8
-10
10
-50
50
90
15
15
±275
7C148/9-35,45
Min.
Max.
2.4
0.4
2.0
6.0
-3.0
0.8
-10
10
-50
50
80
110
10
10
10
10
±275
±350
Unit
V
V
V
V
fAA
IlA
rnA
rnA
rnA
rnA
Capacitance[5]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. TA is the "instant on" case temperature.
2.
3.
4.
See the last page of this specification for Group A subgroup testing
information.
A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up. Otherwise current will exceed
values given (CY7C148 only).
5.
2-116
= 1 MHz,
Max.
8
8
Unit
pF
pF
For test purposes, not more than 1 output should be shorted at one
time. Duration of the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect these parameters.
CY7C148
CY7C149
'~PRESS
.
~,
SEMICONDUCTOR
AC Test Loads and Waveforms
R14B111
R14B111
5Vo----~........
5 V o - - - - J W........
OUTPUTo---......----t
FI
30 P
OUTPUT
5PFI
R2
25511
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
0---"",,---+
3.0V
R2
25511
-------:U------"!IIL
GND
Cl48-5
Cl48-4
(b)
THEVENIN EQUIVALENT
16711
OUTPUT O'O---'\..N
..•.........--OO 1.73V
Switching Characteristics Over the Operating Rangel 2]
7C148-25
7C149-25
Min.
Description
Parameter
Max.
7C148-35
7C149-35
Min.
Max.
7C148·45
7C149·45
Min.
Max.
Unit
READ CYCLE
tRC
Address Valid to Address Do Not Care Time
(Read Cycle Time)
25
tAA
Address Valid to Data Out Valid Delay
(Address Access Time)
tACSl
tACS2
Chip Select LOW to Data Out Valid (7C148 only)
tACS
Chip Select LOW to Data Out Valid (7C149 only)
tLZ[8]
Chip Select LOW to Data Out On
I 7C148
I 7C149
35
45
25[6]
35
45
ns
35
45
ns
15
15
20
ns
10
10
5
5
Chip Select HIGH to Data Out Off
0
Address Unknown to Data Out Unknown Time
0
tpD
Chip Select HIGH to Power-Down Delay
tpu
Chip Select LOW to Power-Up Delay
I 7C148
ns
30[7]
8
tHZ[8]
ns
25
5
tOH
I 7C148
45
35
15
0
20
0
20
5
0
30
20
ns
ns
ns
30
ns
0
0
0
ns
Address Valid to Address Do Not Care
(Write Cycle Time)
25
35
45
ns
twp[9]
Write Enable LOW to Write Enable HIGH
20
30
35
ns
tWR
Address Hold from Write End
5
5
5
ns
WRITE CYCLE
twc
twZ[8]
Write Enable to Output in High Z
0
tDW
Data in Valid to Write Enable HIGH
12
20
20
ns
tDH
Data Hold Time
0
0
0
ns
tAS
Address Valid to Write Enable LOW
0
0
0
ns
tcW[9]
Chip Select LOW to Write Enable HIGH
20
30
40
ns
tOW[8]
Write Enable HIGH to Output in Low Z
0
0
0
ns
tAW
Adqress V(llid to End of Write
20
30
35
ns
Notes:
6. Chip deselected greater than 25 ns prior to selection.
7. Chip deselected less than 25 ns prior to selection.
8. At any given temperature and voltage condition, tHZ is less than tLZ
for all devices. Transition is measured ±500 mV from steady-state
voltage with specified loading in part (b) of AC Test Loads.
9.
2-117
8
0
8
0
8
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to intiate a write and
either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
•
CY7C148
CY7C149
~
--.
:~PRESS
. ' SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[10,11]
tRC
)(
)(
ADDRESS
-tOH
DATA OUT
PREVIOUS DATA VALID
tAA .1
*XX) (
DATA VALID
C148·6
Read Cycle No. 2[10, 12]
tRC
~~
~~
tACS
tLZ
DATA OUT
HIGH IMPEDANCE
-L/////
_tHZj
'-.'\.'\.'\.'\.r\.
tpu
VCC
~
DATA VALID
f
~tpD-
50%~
~~ 50%
SUPPLY
CURRENT
HIGH
IMPEDAN CE
- ICC
' - - - - I SB
C148-7
Write Cycle No.1 (WE Controlled)
~------------------------twc --------------------------~
~-----------------tcw --------------------~
~---------------------~w ------------------~.--
___'-..1-_-_-_-_-_-_-_-_t.;.;A.;;.S:_-_-_-_-_-.:-_-'...~~~~ ~-----
DATA IN
twp ------~ ~----------
DATA-IN VALID
twz
j
--'>
DATAOUT _ _ _ _ _ _ _ _D_A_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _
tow~
HIGH IMPEDANCE
~,.----C148-8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CS = VIL.
12. Address valid prior to or coincident with CS transition LOW.
2-118
"
---=-
CY7C148
CY7C149
~~
_ ' i l l CYPRESS
JF SEMICONDUcrOR
Switching Waveforms (continued)
•
Write Cycle No.2 (CS Controlled)[13]
~----------------------
_____________________________
~~----
tow
------~~
DATA-IN VALID
twz
--l
~-,~I----------H-IG-H-I-M-PE-D-A-N-e-E___________
DATA OUT _____________________________________
DATA UNDEFINED
~
C148·9
Notes:
13. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
~
~ 1.2
~
Icc
1.0
o
~ O.B
:::::i
~ 0.6
~
V
~
VIN = 5.0V
TA = 25°e
~
1.0
~
o8 O.B
w
-
Vee = 5.0V
VIN = 5.0V
z
0.2
ISB
ISB
5.5
SUPPLY VOLTAGE
0.0
-55
6.0
M
120
di
100
~
=> BO
()
25
125
AMBIENT TEMPERATURE (ee)
@
o~
J.1.4
!z
1.2 I\.
oW
II:
«
1.1
:2!
0 1.0
z
II:
0.9
O.B
4.0
" '"
3.0
.s 120
1.3
:::::i
2.0
'" '"
4.5
N
~ 100
1.21--------1--~---I
:::::i
«
~
TA = 25°e
~ 1.0
r---t---
Ci5
z
~ 40
Z
O.BI"7'''''''-------if-------I
SUPPLY VOLTAGE
M
6.0
0.6 '--------''------~
-55
25
125
AMBIENT TEMPERATURE (0C)
2-119
/
60
0..
~
o
5.5
/~
B BO
:2!
5.0
4.0
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
J.
N
0
0.0
'"
OUTPUT VOLTAGE
0
w
40
20
Vee = 5.0V
TA = 25°e
~ 140
1.6
1.4
~
~
ir
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
'" "
II:
II:
II:
~ 0.4
5.0
1
~ 60
=>
~ 0.6
:2!
II:
4.5
~ .......
N
~ 0.4
0.0
4.0
Icc
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
20
o l.7
0.0
.... ~
Vee = 5.0V
TA = 25°e
j
/
I
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C148
CY7C149
trr~t=R
1Ypical DC and AC Characteristics
lYPICAL POWER-ON CURRENT
VS. SUPPLY VOLTAGE (7C148)
lYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
0
2 .5
TA = 25°C
1K Q CS PULL-UP
RESISTOR TO Vee
...B-
e
w 2.0
N
:J
---+--- 0 1
03
C1S0-2
C1S0-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Commercial
Military
Commercial
Military
7C150-10
7C150-12
7C150-15
7C150-25
10
12
12
90
100
15
15
90
100
25
25
90
2-122
90
100
7C150-35
35
90
100
~
:~PRF5S
.
CY7C150
- , SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ...................... - 0.5V to +7.OV
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.OV
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.OV
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to + 70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
Military[l]
Electrical Characteristics Over the Operating Rangd 2]
Parameter
Description
Test Conditions
= Min., IOH = - 0.4 rnA
Vee = Min., IOL = 12 rnA
VOH
Output HIGH Voltage
VOL
VIR
Output LOW Current
VIL
Input LOW Level
IIX
Input Load Current
GND~VI~Vee
loz
Output Current (High Z)
VOL~ VOUT~ VOH,
Vee
7C150
Min.
Max.
Output Disabled
V
V
- 3.0
Vee
0.8
-10
+10
JAA
-50
+50
JAA
-300
rnA
90
rnA
100
rnA
= Max., VOUT = GND
los
Output Short Circuit Current[3]
Vee
Icc
Vee Operating Supply Current
Vee = Max.,
lOUT = ornA
V
0.4
2.0
Input HIGH Level
Unit
2.4
I Commercial
rMilitary
V
Capacitance[4]
Parameter
Description
Test Conditions
TA = 25°C, f
Vee = 5.0V
Input Capacitance
Output Capacitance
CIN
COUT
= 1 MHz,
Max.
Unit
10
pF
10
pF
AC Test Loads and Waveforms
R1329Q
R1329Q
SVo----..JV\.......,
SVo----..JV\.......,
30pF
R2
202Q
I
INCLUDING
JIGAND SCOPE -
=
SpF
3.0V - - - - ' - - - - - -...L
R2
202Q
I
GND
INCLUDING
JIGAND SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUT' 0 - - -.......----1
OUTPUT' 0 - - -.......----1
=
(b)
C1S0-3
C1S0-4
THEvENIN EQUIVALENT
125Q
OUTPUT ().O- - _ '
..VI
...__----OO 1.9V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3.
4.
2-123
Not more than 1 output should be shorted at a time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
I
~
~~PRESS
~, SEMICONDUCTOR
CY7C150
Switching Characteristics Over the Operating Rangd 2, 5]
7C150-10
Description
Parameter
READ CYCLE
Read Cycle Time
tRC
Min.
Max.
10
7C150-12
7C150-15
Min.
Min.
Max.
12
15
Min.
Max.
25
15
12
10
Max.
7C150-25
7C150-35
Min.
Max.
35
25
Unit
ns
35
ns
tAA
Address to Data Valid
tOHA
Output Hold fromAddress Change
tACS
CS LOW to Data Valid
tLzCS
CS LOW to Low Zl6J
tHZCS
CS HIGH to High Z16, 7J
6
8
11
20
25
ns
tDOE
OE LOW to Data Valid
6
8
10
15
20
ns
tLZOE
OE LOW to Low Z[6]
2
2
8
0
0
0
8
6
0
20
ns
ns
0
0
9
ns
20
15
0
0
0
2
2
12
10
0
OE HIGH to High Z16, 7J
tHZOE
WRITE CYCLEl!!J
2
ns
25
ns
twc
Write Cycle Time
10
12
15
25
35
ns
tscs
CS LOW to Write End
6
8
11
15
20
ns
tAW
Address Set-Up to Write End
8
10
13
20
30
ns
tHA
Address Hold from Write End
2
2
2
5
5
ns
tSA
Address Set-Up to Write Start
2
2
2
5
5
ns
tpWE
WE Pulse Width
6
8
11
15
20
ns
tSD
Data Set-Up to Write End
6
8
11
15
20
ns
tHD
Data Hold from Write End
2
2
2
5
5
ns
tLzWE
WE HIGH to Low Zlbj
0
tHZWE
WE LOW to High Zlb, 7j
0
0
8
6
0
0
20
12
ns
25
ns
RESET CYCLE
tRRC
Reset Cycle Time
20
24
30
50
70
ns
tSAR
Address Valid to Beginning of
Reset
0
0
0
0
0
ns
tSWER
Write Enable HIGH to Beginning
of Reset
0
0
0
0
0
ns
tSCSR
Chip Select LOW to Beginning of
Reset
0
0
0
0
0
ns
tpRS
Reset Pulse Width
10
12
15
20
30
ns
tHCSR
Chip Select Hold After End of
Reset
0
0
0
0
0
ns
tHWER
Write Enable Hold After End of
Reset
8
12
15
30
40
ns
tHAR
Address Hold After End of Reset
10
12
15
30
40
ns
tLZRS
Reset HIGH to Output in LowZlbj
0
0
0
0
0
ns
tHZRS
Reset LOW to Output in
High Z[6, 7]
8
6
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOIJIOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tLzfor
any given device.
7. tHZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part
(b) of AC Test Loads. Transition is measured ±500 m V from steadystate voltage.
8.
2-124
12
20
25
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be reference to the rising edge of the signal
that terminates the write.
.
:~PRESS
~,
CY7C150
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. If9, 10]
I
tRC
)(
)(
ADDRESS
en
:I
C
tAA
a:
-tOHA~
DATA OUT
(/)
'*XX)(
PREVIOUS DATA VALID
DATA VALID
C150-5
Read Cycle No. 2[10, 11]
~
tRC
~~
~
tACS
~~
r--DATA OUT
~~
tDOE
tUOE -
HIGH IMPEDANCE
tucs
~~~
I+- tHZCS
~/////
DATA VALID
~:""
HIGH
IMPEDANC E
/
C150-6
Write Cycle No.1 (WE Controlled)[8]
~-------------------------twc --------------------------~
ADDRESS
)4----------------
tscs
----------------I~
14-----------------------~w --------------------~_ _ _~~:.:.:.:.:.:.:._tS_A_-_-_-_:.:.:.:.:;~~~, I0Il1---- tpWE - - - - - . J , -_ _ _ _ _ _ _ _ __
WE
DATA IN
--------------------------,
14-+---- tSD
-----+10.
DATA-IN VALID
tHZWE
j
>
DATA I/O _ _ _ _ _ _ _ _
DA_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _ _
tlZWE
HIGH IMPEDANCE
<:'------
-..j
C150-7
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CS and OE = VIL.
11. Address prior to or coincident with CS transition Law.
2-125
~
~~PRESS
~, SEMICONDUcrOR
CY7C150
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[8, 12]
ADDRESS
- - - - - - - I - t 4 - - - - tscs
1 + - - - - tPWE
---~
-----+I
~~~~~~~~~~~~~~~
~~~~~~~~~~~
1 + - ' - - + - - - - - tSD - - - - . . ....
DATA IN ----------------------~
DATA-IN VALID
tHZWE
-.l
~I
DATA I/O ______________D_A_TA
__
U_ND_E_F_IN_E_D______________---.J
/
HIGH IMPEDANCE
).---------------------------
C150-B
Reset Cycle[13]
14--------
tRRC ------------~
OUTPUT VALID ZERO
C150-9
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a highimpedance state.
13. Reset cycle is defined by the overlap ofRS and CS for the minimum reset pulse width.
2-126
.~
.
~i=
CY7C150
CYPRESS
~F SEMICONDUcrOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
III
en 1.2
./
./
o
~ 0.8
:::i
V
0.6
~ 1.0
0
.2 0.8
~
w
N
z
0.2
-
ISB -
4.5
5.0
SUPPLY VOLTAGE
0.4
g
Vee = 5.0V
VIN = 5.0V
ir
25
o~
125
"'"
20
0
0.0
1.0
1.4
1.6
1.3
j1.4
2.0
« 150
0
0
N
N
w 1.2
:::i
«
:a:
a:
W
:::i
1.1
...............
0
z 1.0
~
...............
0.9
0
I---
1.0
z
0.8
,
/
f€
100
u
~
z
75
:::>
/
«
:a:
a:
D
TA = 25 C
Vee = 5.0V
Ci5
~
50
a.
~
25
o
0.8
4.0
0.6
4.5
5.0
5.5
SUPPLY VOLTAGE
-55
6.0
M
25
125
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
/
/
o 1/
0.0
AMBIENT TEMPERATURE (DC)
1.0
I
TA = 25 DC
2.0
3.0
OUTPUT VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
VIVee = 5.0V
I
z
w
./
'"
4.0
M
..".-
;:- 125
1.2
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
E
j
"-,
OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
Vee = 5.0V
~A=25DC
10
AMBIENT TEMPERATURE (DC)
M
•
"
I-
ISB
0.0
-55
6.0
50
:::>
0.2
5.5
~
~ 30
a:
«
0
60
a:
a:
:::> 40
u
:::i 0.6
:a:
a:
.s«
I-
0
a:
~ 0.4
0.0
4.0
~
III
lee
111.0
~
1.2
./
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
4.0
-
5.0
M
NORMALIZED Icc vs. CYCLE TIME
30r---r---r---~--'---~
1.1
Vee = 5.0V
0
~
2 .5
en
w 2.0
5
:::i
j
0
N
«
:a:
a:
1.5
~
~
0
z 1.0
0.5
0.0
0.0
1.0
---
2.0
~
3.0
SUPPLY VOLTAGE
/
4.0
M
5.0
20r-~r---+---~--;---~
~
o
W
TA = 25 D C
Vee = 0.5V
N
:::i
«
:a:
a:
oz
10 r-~~r-.+-
200
400
600
800 1000
CAPACITANCE (pF)
2-127
0.8 L..-_ _ _ _- - ' -_ _ _ _ _ _' - -_ _ _ _- - '
10
20
30
40
CYCLE FREQUENCY (MHz)
;"~CYPRFSS
~
CY7C150
SEMICONDUCTOR
Truth Table
Inputs
CS
WE
OE
RS
H
X
X
X
HighZ
Outputs
Mode
Not Selected
L
H
X
L
HighZ
Reset
L
L
X
H
HighZ
Write
L
H
L
H
00- 0 3
Read
L
X
H
H
HighZ
Output Disable
Ordering Information
Speed
(ns)
10
12
15
25
35
Ordering Code
CY7C150-lOPC
Package
Name
P13A
CY7C150-lOSC
S13
CY7C150-12PC
P13A
Package 1Ype
Operating
Range
24-Lead (300-Mil) Molded DIP Commercial
24-Lead Molded SOIC
24-Lead (300-Mil) Molded DIP Commercial
CY7C150-12SC
S13
CY7C150-12DMB
D14
24-Lead Molded SOIC
24-Lead (300-Mil) CerDIP
CY7C150-15PC
P13A
24-Lead (300-Mil) Molded DIP Commercial
CY7C150-15SC
S13
24-Lead Molded SOIC
CY7C150-15DMB
D14
24-Lead (300-Mil) CerDIP
Military
Military
CY7C150-25PC
P13A
CY7C150-25SC
S13
24-Lead Molded SOIC
CY7C150-25DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C150-35DMB
D14
24-Lead (300-Mil) CerDIP
Military
24-Lead (300-Mil) Molded DIP Commercial
2-128
.. ~
CY7C150
======
-===,-= CYPRESS
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
•
DC Characteristics
Parameter
VOH
Subgroups
en
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
Ilx
Ioz
Icc
1,2,3
:E
CE2) is HIGH, or OE is HIGH.
Pin Configurations
DIP/SOJ
Top View
LCe
Vee
Top View
AI
u
~
~:e.)['-? 200 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Operating Range
55°C to + 125°C
- O.5V to + 7.0V
Range
- O.5V to +7.0V
- 3.0V to +7.0V
Commercial
Militaryl2J
Ambient
Temperature
Vee
-8
I -10, -12
5V ± 5% 5V ± 10%
O°C to +70°C
5V ± 10%
- 55°C to +125°C
I
Electrical Characteristics Over the Operating Rangd 3]
Parameter
Description
Output HIGH Voltage
VOH
Test Conditions
I IOH = - 4.0 rnA
IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee = Min.
I
Com'l
Mil
VOL
VIR
VIL
IIX
loz
lee
Output LOW Voltage
Input HIGH Level
Input LOW Voltagd 1]
Input Load Current
GND~VI~Vee
Output Leakage Current GND ~ VI ~ Vee, Output Disabled
Com'l
Vee Operating
Vee = Max.,
Supply Current
lOUT = 0 rnA, f = fmax.
Mil
ISB
Automatic CE
Power-Down Current
CE L 3 V, lOUT = 0 rnA,
Other Inputs = < 0.8 or > 3V,
Vee = Max.
Com'l
7B161-8
7B162-8
Max.
Min.
2.4
2.4
0.4
2.2
Vee
- 0.5
0.8
-10
+10
-10
+10
140
50
7B161-10
7B162-10
Min. Max.
2.4
2.4
0.4
2.2
Vee
- 0.5
0.8
-10
+10
-10
+10
130
145
40
Unit
V
V
V
V
IlA
!lA
rnA
rnA
60
Mil
Shaded area contains preliminary information.
Description
Output HIGH Voltage
Parameter
VOH
Test Conditions
IOH = - 4.0 rnA
I lOll = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee = Min.
I
Com'l
Mil
VOL
VIR
VIL
IIX
Ioz
lee
Output LOW Voltage
Input HIGH Level
Input LOW Voitage l1J
Input Load Current
GND~VI~Vee
Output Leakage Current GND ~ VI ~ Vee, Output Disabled
Com'l
Vee Operating
Vee = Max.,
Supply Current
lOUT = 0 rnA, f = fmax.
Mil
ISB
Automatic CE
Power-Down Current
CE L 3V, IOUT=OrnA,
Other Inputs = < 0.8 or > 3V,
Vee=Max.
Com'l
Mil
7B161-12
7B162-12
Min.
Max.
2.4
2.4
0.4
2.2
Vee
- 0.5
0.8
-10
+10
-10
+10
120
140
40
55
7B161-15
7B162-15
Min. Max.
2.4
2.4
0.4
2.2
Vee
- 0.5
0.8
-10
+10
-10
+10
Unit
V
V
V
V
/lA
!lA
rnA
135
rnA
50
Capacitance[4]
Parameter
CIN
COUT
Notes:
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
1. VrL (min.) = - 3.0V for pulse width < 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
4.
5.
2-131
MaxJ5]
6
6
Unit
pF
pF
Tested initially and after any design or process changes that may affect
these parameters.
For all packages except CerDIP (D22), which has maximums of
CrN = 9.5 pF and COUT = 9 pF.
I
CY7B161
CY7B162
~
~~
~, ~~NDUcrOR
AC Test Loads and Waveforms
R1481.o,
R1481.o,
5V
5V
OUTPUT
OUTPUT
3.OV
CLI
INCLUDING
JIG AND
SCOPE
-=
R2
255.0,
-=
5 pF
INCLUDING I
JIG AND
SCOPE
-=
GND
-=
8161-4
(b)
(a)
Equivalent to:
R2
255.0,
ALL INPUT PULSES
----.11""------.1-
8161-5
THE'vENIN EQUIVALENT
167.0,
OUTPUT OO--__"Y..\I\""_---oO 1.73V
Switching Characteristics Over the Operating Rangd3, 6, 7]
7B161-8
7B162-8
Parameter
Description
Min.
Max.
7B161-10
7B162-10
Min.
Max.
7B161-12
7B162-12
Min.
Max.
7B161-15
7B162-15
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Zl!!j
tHZOE
OE HIGH to High Zl!!, lJj
CE LOW to Low Zl!!j
tLZCE
CE HIGH to High Zl!!, 9j
tHZCE
WRITE CYCLEllUj
8
12
10
8
10
3
3
25
8
10
4.2
1.5
4
2
6
4
5
15
ns
8
ns
ns
ns
7
6
3
2
2
ns
3
2
5
15
3
12
5
2
ns
15
12
6
ns
ns
7
ns
twc
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
8
8
10
ns
tAW
Address Set-Up to Write End
7
8
8
10
ns
tRA
Address Hold from Write End
0
0
0
0
ns
ns
0
0
0
0
65
8
8
10
ns
Data Set-Up to Write End
4
5
6
7
ns
tHD
Data Hold from Write End
d
0
0
0
ns
tLZWE
WE HIGH to Low Z[8] (7BI62)
2
2
2
3
tHZWE
WE LOW to High ZllS, lJj (7BI62)
4
5
6
7
ns
tAWE
WE LOW to Data Valid (7BI61)
8
10
12
15
ns
tADV
Data Valid to Output Valid (7BI61)
8
10
12
15
ns
tSA
Address Set-Up to Write Start
tpWE
WE Pulse Width
tSD
Notes:
6. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOIJlOH and CL = 20 pF.
7. Both CEl and CE2 are represented by CE in the Switching Characteristics and Waveforms section.
8. At any given temperature and voltage condition, tHZ is less than tLZ for
any given device. This parameter is guaranteed and not 100% tested.
9.
ns
tHzCE, tHZOE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Thansition is measured ± 200 mV from steady state
voltage. This parameter is guaranteed and not 100% tested.
10. The internal write time of the memory is defined by the overlap of CEl
LOW, CE2 LOW, and WE LOW. Both signals must be LOW to initiate
a write and either signal can terminate a write by going HIGH. The data
input set-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
2-132
CY7B161
CY7B162
~
=:::- ;~PRESS
- , SEMICONDUCTOR
Switching Waveforms[7]
Read Cycle No. 1[11, 12]
ADDRESS
~
--~IoHA~
DATA OUT
PREVIOUS DATA VALID
*-
tRC
J
~I
xX)I(===============D=A=:r=A=V=A=L=ID============
B161-6
Read Cycle No. 2[11, 13]
CE
RC
~~
/I?
tACE
/~
~~
I-DATA OUT
tHZOE ---
tDOE
tLZOE-
I---
HIGH IMPEDANCE
/////v
tLZCE
'''''''''~
,
tHZCE ---
DATA VALID
HIGH
IMPEDAN CE
./
B161-7
Write Cycle No.1 (WE Controlled)[10]
~-------------------------twc --------------------------~
ADDRESS
~--------tSCE --------------------~
~----------------------~w --------------------~~------- tSA ----~
1 4 - - - tpWE - - - - - + I
WE-------------~~~~
,-----------
_________________________......;~ ~_f_--- tSD ----~...
DATA IN
DATA OUT
(78162)
DATA UNDEFINED
---------------1------:-""
DATA
OUT _ _ _ _ _ _ _DATA
(78161)
_ _UNDEFINED
_ _ _ _ _ _ __
DATA VALID
B161-8
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected, CEl, CE2 ~ VIL. OE ~ VIL also.
13. Address valid prior to or coincident with CEl and CE2 transition LOW.
2-133
I
-====-.
CY7B161
CY7B162
~~
====e
iE CYPRESS
~_,J SEMICONDUCTOR
Switching Waveforms[7] (continued)
Write Cycle No.2 (CE Controlled)[lO,14]
~------------------------twc --------------------------~
ADDRESS
1+------
tSA
------1+----
DATA IN ---~--------~
DATA OUT
14----+------
tSCE
------t
HIGH IMPEDANCE
DATA UNDEFINED
:1:)I(___
DATAOUT _________D_AT_A__
U_ND_E_F_IN_E_D______________________________
(78161)
Note:
14. IfCEgoes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state (7B162 only).
7B161 Truth Table
L
CE2 WE
X
X
H
X
L
H
OE
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
Input
Output
HighZ
X
HighZ
X
Data Out
X
Data In
Data In
HighZ
Data In
HighZ
X
Mode
DeselectlPower-Down
DeselectlPower-Down
Read
Write
Write
Deselect
Input
Output
HighZ
X
HighZ
X
Data Out
X
HighZ
Data In
HighZ
X
Mode
DeselectlPower-Down
DeselectlPower-Down
Read
Write
Deselect
7B162 Truth Table
eEl
H
X
L
CE2 WE
X
X
H
X
L
H
L
L
L
L
L
H
OE
X
X
L
X
H
,--------+---------
tSD --------1~
(78162) ___~-----------+-----
CEI
H
X
,-----
2-134
_V_A_L_ID__________
D_AT_A
~
8161-9
CY7B161
CY7B162
'~PRESS
.
- , SEMICONDUCTOR
Ordering Information
Speed
(ns)
Package
Name
Ordering Code
Package 'JYpe
8
CY7B161-8VC
V21
28-Lead Molded SO]
10
CY7B161-10DC
D22
28-Lead (300-Mil) CerDIP
CY7B161-10PC
P21
28-Lead (300-Mil) Molded DIP
CY7B161-10VC
V21
28-Lead Molded SO]
CY7B161-lODMB
D22
28-Lead (300-Mil) CerDIP
CY7B161-10LMB
1.54
28-Pin Rectangular Leadless Chip Carrier
CY7B161-12DC
D22
28-Lead (300-Mil) CerDIP
CY7B161-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B161-12VC
V21
28-Lead Molded SO]
CY7B161-12DMB
D22
28-Lead (300-Mil) CerDIP
CY7B161-12LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7B161-15DMB
D22
28-Lead (300-Mil) CerDIP
CY7B161-15LMB
L54
28-Pin Rectangular Leadless Chip Carrier
12
15
..
Operating
Range
Commercial
Military
Commercial
Military
Military
Shaded area con tams prelimmary mformatlOn.
Speed
(ns)
Package
Name
Ordering Code
Package 'JYpe
Operating
Range
8
CY7B162-8VC
V21
28-Lead Molded SO]
10
CY7BI62-1ODC
D22
28-Lead (300-Mil) CerDIP
CY7B162-1OPC
P21
28-Lead (300-Mil) Molded DIP
CY7B162-lOVC
V21
28-Lead Molded SO]
~7B162-10D~fB
D22
28-Lead (3~Mil) CerDIP
Military
L54
28-Pin .Rectangular Leadless Chip Carrier
D22
28-Lead (300-Mil) CerDIP
".
Commercial
CY7B162-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B162-12VC
V21
28-Lead Molded SO]
CY7B162-12DMB
D22
28-Lead (300-Mil) CerDIP
CY7BI62-12LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7B162-15DMB
D22
28-Lead (300-Mil) CerDIP
CY7BI62-15LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7B162-10LMB
12
15
CY7B162-12DC
,
..
Shaded area contams prelimmary mformatlOn.
2-135
Commercial
Military
Military
CY7B161
CY7B162
tC :;~PRK§
-====,
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISB
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tAA
7,8, 9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7,8,9, 10, 11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
tSCE
7,8, 9, 10, 11
tAW
7, 8, 9, 10,,11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7,8,9, 10, 11
tSD
7,8,9,10,11
tHD
7, 8, 9, 10, 11
tAWE[15]
7,8,9, 10, 11
tADV[15]
7, 8, 9, 10, 11
Note:
15. 7B161 only.
Document #: 38-A-00014-E
2-136
CY7C161
CY7C162
16K X 4 Static RAM
Separate I/O
Features
Functional Description
• High speed
- 15-ns
• Transparent write (7CI61)
• CMOS for optimum speed/power
• Low active power
- 633mW
• Low standby power
- 220mW
• TTL compatible inputs and outputs
• Automatic power-down when
deselected
The CY7C161 and CY7C162 are high-performance CMOS static RAMs organized
as 16,384 by 4 bits with separate I/O. Easy
memory expansion ~rovided by active
LOW chip enables (CEb CEz) and threestate drivers. They have an automatic power-down feature, reducing the power consumption by 65% when deselected.
Writing to the device is accomplished when
the ch~nable (CEb CEz) and write enable (WE) inputs are both LOW Data on
the four input pins (10 through 13) is written
Logic Block Diagram
into the memory location specified on the
address pins (Ao through A13).
Reading the device is accomplished bytaking the chip enabl~CEl, CEz) LOW
while write enable (WE) remains HIGH.
Under these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The output pins stay in a hi~mpedance
state when write enable (WE) is LOW
(7C162 only), or one of the chip enables
(CEl, CEz) are HIGH.
A die coat is used to insure alpha immunity.
Pin Configurations
DIP
Top View
A5
1
A6
A7
As
Ag
A10
6
An
A12
A13
10
11
Ci:1
ITE
GND
C162-2
C162-1
Selection Guide[l]
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
7C161-12
7C162-12
7C161-15
7C162-15
7C161-20
7C162-20
7C161-25
7C162-25
7C161-35
7C162-35
12
15
20
25
35
160
115
80
70
70
40/20
40/20
40/20
20/20
20/20
Shaded areas mdIcate advanced mformatIOn.
Note:
1. For military specifications, see the CY7C161NCY7C162Adatasheet.
2-137
•
.
CY7C161
CY7C162
~PR£§
-====:l1lI", .
SEMICONDUcrOR
Maximum Ratings
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. Ambient Temperature with
Power Applied ...................... Supply Voltage to Ground Potential
(Pm 24 to Pin 12) ......................
DC Voltage ApBlied to Outputs
in High Z State 2] . . . . . . . . . . . . . . . . . . . . . .
DC Input Voltagd 2] ....................
65°C to +150°C
55°C to +125°C
Operating Range
Ambient
Temperature
Vee
O°Cto + 70°C
5V ± 10%
- O.5V to + 7.0V
Range
Commercial
0.5V to + 7.0V
- 0.5V to + 7.0V
-
I
Electrical Characteristics Over the Operating Range
7C161-12
7C162-12
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
Vee = Min.,
IOH = - 4.0 rnA
"
7C161-15
7C162-15
Min.
Max.
2.4
Max.
2.4
Unit
V
,,'
Vee = Min.,
IOL = 8.0 rnA
0.4
0.4
V
V
!
2.~
Vee
2.2
Vee
-0.5
0.8
-0.5
0.8
V
GNDsVIsVee
-10
+10
-10
+10
f,tA
Output Leakage
Current
GNDs VIS Vee,
Output Disabled
-10
+10
-10
+10
f,tA
los
Output Short
Circuit Currentl3]
Vee = Max.,
VOUT = GND
-350
- 350
rnA
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
160
115
rnA
40
rnA
20
rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltagd 2]
IIX
Input Load Current
Ioz
ISBl
ISB2
Automatic CEI
Power-Down Current
Automatic CEI
Power-Down Current
I""
Max. Vee,
CEIL VIH
Min. Duty Cycle
~,'
I
~
(I"
i
= 100%
Max. Vee,
CEI L Vee - 0.3v,
VIN L Vee - 0.3Vor
VINSO.3V
Shaded areas mdlCate advanced mformatlOn.
2-138
40
l
"
,
",,
20
..:.
',;
., i"Y
I
CY7C161
CY7C162
=-=. ~~PRESS
-=:=,
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range (continued)
7C161-20
7C162-20
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min.,
IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min.,
IOL = 8.0 rnA
VIH
Input HIGH Voltage
Input LOW Voltagel 2]
VIL
Min.
7C161-25,35
7C162-25,35
Max.
Min.
Max.
Unit
2.4
2.4
0.4
V
0.4
V
2.2
Vee
2.2
Vee
V
-0.5
0.8
-0.5
0.8
V
IIX
Input Load Current
GND.s VI.s Vee
-10
+10
-10
+10
loz
Output Leakage
Current
GND.s VI.s Vee,
Output Disabled
-10
+10
-10
+10
!LA
!LA
los
Output Short
Circuit Current[3]
Vee = Max.,
VOUT = GND
- 350
- 350
rnA
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
80
70
rnA
ISBl
Automatic CEI
Power-Down Current
Max. Vee,
CElLVIH
Min. Duty Cycle
40
20
rnA
Automatic CEI
Power-Down Current
Max. Vee,
CEI L Vee - 0.3v,
VIN L Vee - O.3Vor
VIN .sO.3V
20
20
rnA
ISB2
= 100%
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
2. Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4.
= 1 MHz,
Max.
Unit
10
pF
10
pF
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481,(L
R1481,(L
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
30pF
INCLUDING
JIGAND
SCOPE
I=
5 pF
R2
255,(L
=
3.0V ----_~~----s..
INCLUDING
JIGAND
SCOPE
(a)
Equivalent to:
I=
(b)
R2
255,(L
GND
=
C162-3
THEVENIN EQUIVALENT
167,(L
OUTPUT C)O--_,IIIY",",""--.QO 1.73V
2-139
C162-4
I
CY7C161
CY7C162
~
.
:~
~=CYPRESS
-=;;;;;JF
SEMICONDUcrOR
Switching Characteristics Over the Operatiog RaogelS, 6]
7CI61-12
7C162-12
Parameter
Description
~ax~ .
7C161-15
7C162-15
Min.
Max.
7C161-20
7C162-20
Min.
Max.
7C161-25
7C162-25
Min.
Max.
7C161-35
7C162-35
Min.
Max.
Unit
35
os
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
12
...
12
15
20
25
20
15
os
35
25
Output Hold from Address Chaoge
tACE
CE LOW to Data Valid
12
15
20
25
35
os
tDOE
OE LOW to Data Valid
12
10
10
12
15
os
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Dowo
3
5
3
0
3
7
3
8
5
0
0
10
12
10
os
os
15
os
os
0
20
20
20
os
5
0
0
15
12
3
5
8
8
7
5
3
3
8
3
5
os
tORA
os
WRITE CYCLE[9]
twc
Write Cycle Time
12
15
20
20
25
os
tSCE
CE LOW to Write Eod
8
12
15
20
25
os
tAW
Address Set-Up to Write Eod
8
12
15
20
25
os
tRA
Address Hold from Write Eod
0
0
0
0
0
os
tSA
Address Set-Up to Write Start
0
0
0
0
0
os
tpwE
WE Pulse Width
:s
12
15
15
20
os
tSD
Data Set-Up to Write Eod
6
10
10
10
15
os
tHD
Data Hold from Write Eod
0
0
0
0
0
os
tLZWE
WE HIGH to Low Z[7] (7CI62)
~
5
5
5
5
tHZWE
WE LOW to High Z[7,8] (7CI62)
6
7
7
7
10
os
tAWE
WE LOW to Data Valid (7CI61)
12
15
20
25
30
os
tAOV
Data Valid to Output Valid (7CI61)
12
15
20
20
30
os
tDCE
CE LOW to Data Valid
12
15
20
25
35
os
'.
I·
os
Shaded areas mdicate advanced mformatlOn.
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and outputloading
of the specified Ior./IOH and 30-pF load capacitance.
6. Both CEl and CE2 are represented by CE in the Switching Characteristics and Waveforms sections.
7. At any given temperature and voltage condition, tHZ is less than tLZ for
any given device.
8.
9.
2-140
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads. Transition is measured ±500 mY from steady-state voltage.
The internal write time of the memory is defined by the overlap of CEl
LOW, CE2 LOW, and WE LOW. Both signals must be LOW to initiate
awrite and either signal can terminate awritebygoingHIGH. The data
input set-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
CY7C161
CY7C162
~
-.
:~
====a=i iii CYPRESS
-=-?
SE11ICONDUcrOR
Switching Waveforms[8)
•
*-
Read Cycle No. 1[10, 11)
€
ADDRESS
tRC
--~
DATA OUT
PREVIOUS DATA
V:~:
1
tAA
-----mXXX*===============D=A=:r=A=V=A=L=ID============
C162-5
Read Cycle No. 2[10, 12)
tRC
~~
}~
tACE
~~
/~
tDOE
14-DATA OUT
f4----
tLZOE-
HIGH IMPEDANCE
tLZCE
1//////
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDAN CE
DATA VALID
,,-"''\r'\.
I---
--- f_tpu
VCC
tHWE~
tpD
~
CC
I
50%
ISB
C162-6
Write Cycle No.1 (WE Controlled)[9)
~------------------------- twc --------------------------~
ADDRESS
~----------------tSCE --------------------~
_ _ _~I-_-_-_-_:.:.:.:._tS_A_-_-_-_-_-_:.:.~~~~"" i00i;...--- tpWE ------~ , -_ _ _ _ _ _ _ _ __
DATA IN
DATA
OUT
UNDEFINED
(7C162) _ _ _ _ _ _ _DATA
__
_ _ _ _---1_ _ _ _-+_'
DATA
OUT _ _ _ _ _ _ _DATA
UNDEFINED
(7C161)
__
_ _ _ _ _ _ _ _ _"
DATA VALID
C162-7
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CEl, CE2 = VIL.
12. Address valid prior to or coincident with CEl, CE2 transition LOW.
2-141
CY7C161
CY7C162
a=; "j?;.
C'lPRFSS
SEMICONDUCTOR
,
Switching Waveforms[8] (continued)
Write Cycle No.2 (CE Controlled) [9,13]
~------------------------twe --------------------------~
ADDRESS
DATA IN
DATA OUT __________
H_IG_H_I_M_P_ED_A_N_C_E__________i;===t~~========~~----------_r--------(7C162)
tDeE
DATA OUT - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
--<
""'-~~~~
(7C161)
C162-8
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state (7C162 only).
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
~ 1.2
lee
13 1.0
Cl
~ 0.8
~
:2 0.6
V
V
1.2
7
V
ID
~
1.0
~
o8 0.8
w
0.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
J.
J.
z
«
"-
0.9
no
v·
4.0
..............
~ 1.0
t---
z
0.6--5.0
5.5
SUPPLY VOLTAGE (V)
6.0
1.0
-55
25
125
AMBIENT TEMPERATURE (0C)
2-142
~r-..
2.0
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
'"
4.0
140
~v
a::
a
80
Z
Ci5
60
/
0..
~ 20
o
4.5
0
0.0
~ 40
0.8 I--~:::....------f----------_I
I'..
OUTPUT VOLTAGE (V)
~
:2
TA = 25°C
Vee = 5.0V
TA = 25°C
20
~ 100
~ 1.2 I----------I--------,:,;£~
...............
"-
40
!z
1.4
::J
.....
~
..s 120
Cl
Cl
5
0.0
-55
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
::>
g
Iir
I-
Vee = 5.0V
VIN = 5.0V
0.2 t - IS8
6.0
100
a::
a::
~ 60
a::
:2
IS8 - I - - -
(5
()
~ 0.4
z
4.0
~
~ 0.6
0.2
1 120
I-
N
a::
~ 0.4
:-..
o
/
L7
0.0
7
Vee = 5.0V
TA = 25°C
/
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
CY7C161
CY7C162
:~
.
====
-= CYPRESS
~.iF'
SEMlCONDUcrOR
'iYpical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
0
~
enc:
J
2.5
Cl
::E
::E
a:
0
z
..!:?
W
N
::J
«
15.0
::E
a:
a:
0
1.0
0.5
0.0
0.0
~
~
1.0
2.0
3.0
SUPPLY VOLTAGE
z
/
4.0
Vee = 5.0V
TA = 25°C
Vee = 0.5V
Cl
N
::J
«
1.5
NORMALIZED Icc vs. CYCLE TIME
1.25
()
w 20.0
N
::J
25.0
Cl
w 2.0
«
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0 ,...---,...---..---""T"""--r---,
oz
10.0
5.0
5.0
M
200
400
600
800
CAPACITANCE (pF)
Address Designators
Address
Name
Address
Function
Pin
Number
AS
X3
1
A6
X4
2
A7
X5
3
A8
X6
4
A9
X7
YO
5
AlO
All
Y1
7
8
6
A12
Y5
A13
AO
Y4
9
Y3
23
A1
Y2
24
A2
XO
25
A3
Xl
26
A4
X2
27
2-143
0.50 L - -_ _........_ _ _~_ _- - '
10
20
30
40
CYCLE FREQUENCY (MHz)
•
##:~
. . CYPRESS
_
-===-,
SEMICONDUcrOR·
CY7C161
CY7C162
==============================
Ordering Information
Speed
(ns)
12
15
20
25
35
Speed
(ns)
Ordering Code
Package
Nsme
Operating
Range
Package 1Ype
. ·CY,'7C161.....:12PC
P2i
.28.Lead:(¥OO~Mil}Mo1ged
cY:7C161-12~f
V21
'2?-Lea~ Mc:>ld~.<1~9J
orr "Comme.rcial·
...•. .,.f,.
CY7C161-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C161-15VC
V21
28-Lead Molded SOJ
CY7C161-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C161- 20VC
V21
28-Lead Molded SOJ
CY7C161-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C161-25VC
V21
28-Lead Molded SOJ
CY7C161-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C161-35VC
V21
28-Lead Molded SOJ
Ordering Code
Package
Name
Package 1YPe
Commercial
Commercial
Commercial
Commercial
Operating
Range
12
CY7C162-12PC
P21
28·Lead (300 Mil) Molded DIP Commercial
CY7C162-12VC
V21
28-Lead Molded SO.t
15
CY7C162-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C162-15VC
V21
28-Lead Molded SOJ
CY7C162-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C162-20VC
V21
28-Lead Molded SOJ
CY7C162-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C162-25VC
V21
28-Lead Molded SOJ
CY7C162-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C162-35VC
V21
28-Lead Molded SOJ
20
25
35
w
Shaded areas mdlcate advanced mformatlOn.
Document #: 38-00029- H
2-144
Commercial
Commercial
Commercial
Commercial
CY7C161A
CY7C162A
CYPRESS
SEMICONDUCTOR
16K X 4 Static RAM
Separate I/O
Features
Functional Description
• High speed
- 20 ns tAA
• CMOS for optimum speed/power
• Transparent write (7C161A)
• Low active power
- 550mW
• Low standby power
- 220mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The CY7C161A and CY7C162A are highperformance CMOS static RAMs organizes as 16,384 by 4 bits with separate I/O.
Easy memory expansion is..E!9vided by active LOW chip enables (CEl> CE2) and
three-state drivers. They have an automatic power-down feature, reducing the power
consumption by 60% when deselected.
Writing to the device is accomplished when
the c~nable (CEl> CE2) and write enable (WE) inputs are both LOW. Data on
the fourinpllt pins (10 through 13) is written
Logic Block Diagram
into the memory location specified on the
address pins (Ao through A13).
Reading the device is accomplished bytaking the chip enabl~CEl' CE2) LOW
while write enable (WE) remains HIGH.
Under these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The output pins stay in high-impedance
state when write enable (WE) is LOW
(7C162A only), or one ofthe chip enables
(CEl, CE2) are HIGH.
A die coat is used to insure alpha immunity.
Pin Configurations
10
DIP
Top View
12
13
00
As
Vee
Aa
At.
A3
A,o
Ao
At.
A"
A'2
13
12
03
02
0,
00
Aa
I,
IT,
OE
03
tJ",
~<~-?~
~
A2
A,
0,
02
LCC
Top View
GND
As
A7
As
10
I,
IT,
WE
CE2
4
5
3 2,1,2827
26
25
6
24
7
23
8 7C161A 22
9 7C162A 21
10
20
11
19
12
18
1314151617
I~ ~1~I~oO
C161A·3
C161A·2
CE,
IT2
WE
OE
C161A·1
Selection Guide[l]
Maximum Operating
Current (rnA)
Military
7C161A-15
7C162A-15
15
160':
Maximum Standby
Current (rnA)
Military
40/20
Maximum Access Time (ns)
Shaded area contams advanced mformatlOn.
Note:
1. For commercial specifications, see the CY7C161/CY7C162datasheet.
2-145
7C161A-20
7C162A-20
20
100
7C161A-25
7C162A-25
25
7C161A-35
7C162A-35
35
100
100
40/20
40/20
30/20
•
U)
::::E
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
- 55°C to + 125°C
5V ± 10%
- 0.5V to +7.0V
Range
Military[3]
- O.5V to +7.0V
- O.5V to + 7.0V
Electrical Characteristics Over the Operating Rangd4]
7C161A.... 1S"
7C162A'- is .
Parameter
Description
Test Conditions
Max.
Min.
VOH
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltage[2]
,...0.5
0.8
IIX
Input Load Current
GND~ VI~Vee
'-10
+10
loz
Output Leakage
Current
GND ~ VI~ Vee,
Output Disabled
-'-10
+10
los
Output Short
Circuit Currentl5]
Vee = Max., VOUT = GND
Icc
Vee Operating
Supply Current
Vee = Max.
lOUT = ornA
Military
ISBl
Automatic CE
Power-Down Current
Max. Vee, CE L VIH,
Min. Duty Cycle =100%
Military
Automatic CE
Power-Down Current
Max. Vee,
CEl L Vee - 0.3v,
VIN L Vee - 0.3V
orVIN ~O.3V
Military
ISB2
Min.
Max.
2.4
Output HIGH Voltage
2.4
Vee = Min., IOH = - 4.0 rnA
7C161A-20
7C162A-20
i
V
0.4
V
2.2
Vee
V
-0.5
0.8
V
-10
+10
-10
+10
!LA
!LA
-350·
-350
rnA
160
100
rnA
40
40
rnA
20
20
rnA
0.4
Vee = Min., IOL = 8.0 rnA
Unit
"":
Shaded area contams advanced mformatlOn.
Notes:
2. Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
1
;
.
'"
0,,
I'
"
5.
2-146
.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
CY7C161A
CY7C162A
.~
·
- -ill
,
CYPRESS
SEMICONDUcrOR
Electrical Characteristics Over the Operating Rangd 4] (continued)
7C161A-25
7C162A-25
Description
Parameter
VOH
Output HIGfJ Voltage
VOL
Output LOW Voltage
Test Conditions
Min.
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Min.
Max.
Unit
2.4
2.4
Vee
7C16IA-35
7C162A-35
V
0.4
0.4
V
VIR
Input HIGH Voltage
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltagd 2]
-0.5
0.8
-0.5
0.8
V
!1A
IIX
Input Load Current
GND~ VI~ Vee
-10
+10
-10
+10
loz
Output Leakage Current
GND ~ VI ~ Vee. Output Disabled
-10
+10
-10
+10
!1A
los
Output Short
Circuit Currentl5]
Vee
= Max., VOUT = GND
-350
-350
rnA
lee
Vee Operating
Supply Current
Vee
= Max., lOUT = 0 rnA
Military
100
100
rnA
ISBl
Automatic CE
Power-Down Current
Max. Vee. CE~ VIH,
Min. Duty Cycle = 100%
Military
40
30
rnA
ISB2
Automatic CE
Power-Down Current
Max. Vee,
CEl ~ V CC - 0.3v,
VIN ~ Vee - 0.3V
orVIN ~O.3V
Military
20
20
rnA
-
Capacitance[6]
Parameter
Description
Test Conditions
CIN
Input Capacitance
COUT
Output Capacitance
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
Unit
10
pF
10
pF
Note:
6. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
OUTP~~~R1
4810
30 pF
I
-=
R1481Q
OUTPUT~
R2
2550
INCLUDING
JIG AND -=
SCOPE (a)
Equivalent to:
5V
5 pF
I
INCLUDING
JIG AND -=
SCOPE (b)
ALL INPUT PULSES
3.0V ----...Jr~~--~
R2
2550
GND
-=
C161A-4
THEVENIN EQUIVALENT
1670
OUTPUT o-O------AJ"J'''''
........_---oo 1.73V
2-147
C161A-5
I
=-:~PRFSS
CY7C161A
CY7C162A
. , SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 2, 7, 8]
7C161A-15
7C162A-15
Parameter
Description
Min.
Max.
7C161A-20
7C162A-20
Min.
Max.
7C161A-25
7C162A-25
Min.
Max.
7C161A-35
7C162A-35
Min.
Max.
Unit
READ CYCLE
tRC
tAA
'15'
Read Cycle Time
3
tACE
tOOE
OE LOW to Data Valid
tLZOE
OE LOW to LOW Z
0
tHZOE
OE mGH to mGH Z
CE LOW to Low Z[9]
3
tLZCE
tHZCE
tpu
5
"
20
25
35
10
12
15
8
8
0
CEmGHto
Power-Down
WRITE CYCLELll J
10
0
20
15
12
10
ns
ns
ns
15
0
20
ns
ns
5
5
8
'0
3
3
ns
ns
7 "
5
tpo
ns
35
5
5
3
CE mGH to High Z[9, 10]
35
25
15
8
CE LOW to Power-Up
25
20
15
Output Hold from
Address Change
CE LOW to Data Valid
tOHA
20
"
Address to Data Valid
ns
ns
20
ns
twc
Write Cycle Time
15
20
20
25
ns
tSCE
tAW
CE LOW to Write End
10
15
20
25
ns
Address Set-Up to
Write End
10
15
20
25
ns
tHA
Address Hold from
Write End
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
10
15
15
20
ns
tso
Data Set-Up to
Write End
Data Hold from
Write End
7
10
10
15
ns
0
0
0
0
ns
WEmGHto
Low Z[9] (7C162A)
3
5
5
5
ns
tHO
tLZWE
tHZWE
WE LOW to
tOWE
WE LOW to
Data Valid (7C161A)
tADV
Data Valid to Output Valid
(7C161A)
CE LOW to Data Valid
(7C161A)
tOCE
7
7
7
10
ns
15
20
25
30
ns
15
20
20
30
ns
15
20
25
35
ns
High Z[9, 10] (7C162A)
,
,;'",
'(
"
Shaded area contams advanced mformatIOn.
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
8. Both CEl and CE2 are represented by CE in the Switching Characteristics and Waveforms sections.
9. At any given temperature and voltage condition, tHZ is less than tLZ for
any given device.
10. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ± 500 m V from steadystate voltage.
11. The internal write time of the memory is defined by the overlap of CEl
LOW, CE2 LOW, and WE LOW: Both signals must be LOW to initiate
a write and either signal can terminate a write by going HIGH. The data
input set -up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
2-148
-
CY7C161A
CY7C162A
~~PRFSS
SEMICONDUCTOR
--=-,
Switching Waveforms[8]
•
Read Cycle No. 1[12, 13]
~-----------------------tRC ------------------------~
ADDRESS
en
:::i
0.6'---------'-------'
-55
25
125
3.0
0.0
0.0
60
Cl..
I-
o
M
BO
~ 40
O.BI-:7"""-----t-------1
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
0.5
a::
3
•
/~
~ 100
z
6.0
120
z
I:!:l 1.21--------+------:::::orl"=--I
::J
....
0
1
I-
o
w 1.2
0
::J
« 140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
4.0
M
NORMALIZED Icc vs. CYCLE TIME
1.25
~
o
Vee = 5.0V
TA = 25°C
Vee = 0.5V
W
N
15.0 1------11---+7"''----+--_1_---1
10.0 1------11---7~+-
::J
«
:a:
a::
oz
5.01--+11---+5.0
M
0.0 0~----J20L..0--4J...00--6..1.0-0-....IBO-0-1....J000
CAPACITANCE (pF)
Address Designators
Address
Name
Address
Function
Pin
Number
AS
X3
1
A6
X4
2
A7
X5
3
A8
X6
4
A9
X7
5
A10
All
YO
Y1
6
7
8
A12
Y5
A13
Y4
9
AO
Y3
23
A1
A2
Y2
XO
24
25
A3
Xl
26
A4
X2
27
2-151
0.50'-------'----'---_--'
10
20
30
40
CYCLE FREQUENCY (MHz)
CY7C161A
CY7C162A
~
·~PRFSS
==.
~,
SEMICONDUcrOR
Ordering Information
Speed
(ns)
J~5,
20
25
35
CY7C161A -15DNfB'
(ns)
15
20
25
35
.::
Package '!ype
9~2"'0 i~8i~~,at! ~~qo;~il). dei-DIP
,
:. !
,<::Y7C!61A-,!~L~13~~ J
CY7C161A - 20DMB
D22
28-Lead (300-Mil) CerDIP
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C161A -25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C161A-25LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C161A - 35DMB
D22
28-Lead (300-Mil) CerDIP
CY7C161A-35LMB
L54
28-Pin Rectangular Leadless Chip Carrier
Ordering Code
Package
Name
Package '!ype
28-Le~d (3()O~Mil)CerDIP
CY7C162A -15DMB
D22
:' <;:,¥7C~(ifA -l~LMB,
L54
CY7C162A-20DMB
D22
28-Lead (300-Mil) CerDIP
CY7C162A-20LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C162A-25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C162A - 25LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C162A-35DMB
D22
28-Lead (300-Mil) CerDIP
CY7C162A-35LMB
L54
28-Pin Rectangular Leadless Chip Carrier
' <:.
Operating
Range
Military >
.~
.,.,~
,
28-PinRectangular Leadless ~hip Carrier
CY7C161A-20LMB
Speed
"
Package
Name
Ordering Code
Military
Miljtary
Military
Operating
Range
Military
28;:Pili~eR~~lar J.,e~d,le~$ Chip Carrier
Shaded areas con tam advanced mformatIOn.
2-152
Military
Military
Military
--.
-4
_·iECYPRESS
CY7C161A
CY7C162A
- , SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
II
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
los
1,2,3
Icc
1,2,3
ISBI
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7,8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tOHA
7, 8, 9, 10, 11
tACE
7,8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7,8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7,8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7,8, 9, 10, 11
tDWE[16]
7, 8, 9, 10, 11
tADV
7, 8, 9, 10, 11
Notes:
16. 7C161A only.
Document #: 38-00116-B
2-153
CY7B164
CY7B166
CYPRESS
SEMICONDUCTOR
16K X 4 Static R/W RAM
Features
Functional Description
• Ultra high speed
- tAA = 8ns
• Low active power
- 700mW
• Low standby power
- 250mW
• BiCMOS for optimum speed/power
• Output enable (OE) feature (7B166)
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7B164 and CY7B166 are highperformance BiCMOS static RAMs organized as 16,384 x 4 bits. Easy memory expansion is provided by an active LOW
chip enable (CE) and three-state drivers.
The CY7B166 has an active LOW output
enable (OE) feature. Both devices have an
automatic power-down feature, reducing
the power consumption by 67% when deselected.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the
four input/output pins (1/00 through 1/03)
Logic Block Diagram
is written into the memory location specified
on the address pins (Ao through A13).
Reading the device is accomplished by taking
chip enable (CE) LOW (and OE LOW for
7B166) while write enable (WE) remains
HIGH. Under these conditions the contents
of the memory location specified on the address pins will appear on the four data I/O
pins.
The I/O pins stay in high-impedance state
when~ enable (CE) is HIGH, or write enable (WE) is LOW (or output enable (DE) is
HIGH for 7BI66).
Pin Configurations
Ag
Al0
All
A12
A13
CE
GND
Vee
As
Vee
A,j
As
A,j
~
A7
A2
Al
As
A3
A2
Al
Ag
A10
All
A12
A13
Ao
15
9
14
13
10
12
11
1...-_
_
-'
DlP/SOJ
Top View
SOJ
Top View
DIP
Top View
1/°3
1/02
1/01
1/00
A,j
NC
CE
NC
GND
WE
Bl64-5
~
A2
Al
Ao
NC
1/°3
1/°2
1/°1
1/°0
CE
OE
WE
GND
Bl64-3
Bl64-6
Lee
LCe
Top View
Top View
~~~~
()
:t ~ -9<1::"
4
5
6
7
8
9
10
11
12
As
1/°0
A7
As
As
'---J...-----
A7
As
Ag
Al0
All
A12
A13
Ao
1/°3
1/°2
1/°1
1/°0
WE
Vee
Al0
All
A12
A13
WE
CE
(OE)
'"
(7B166 ONLy)
3 2,1,2827
26 NC
25 A,j
24 ~
23 A2
22 Al
7B166
21 Ao
20 1/°3
19 1/°2
18 1/°1
~151.61?/
I~~~I~ ~
Bl64-4
Bl64-1
Bl64-2
Selection Guide
7B164-8
7B166-8
7B164-10
7B166-10
Commercial
8
140
Military
Commercial
50
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum 03erating
Current (rnA
7B164-12
7B166-12
7B164-15
7B166-15
10
12
15
130
120
::;'{ .Fj 145
Military
Shaded area contains preliminary information_
2-154
,.....
140
40
40
'.. : 60
55
135
50
CY7B164
CY7B166
· -4
----....;
-= CYPRESS
.!!IF' SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended penods may affect
device reliability. For user guidelines, not tested.)
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential ....... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to + 7.0V
DC Input Voltagel 1] .................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Operating Range
Range
Ambient
Temperature
Commercial
O°C to + 70°C
Vee
-8
-10, -12
Military[2]
I 5V ±5%
I 5V ±1O%
5V ±10%
- 55°C to + 125°C
Electrical Characteristics Over the Operating Rangel 3]
7B164-8
7B166-8
Parameters
Test Conditions
Description
I lOR = - 4.0 rnA
I lOR = -: 2.0 rnA
VOR
Output HIGH Voltage
Vee = Min.
VOL
VIR
VIL
IIX
loz
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel 1]
Input Load Current
Output Leakage
Current
Vee Operating Supply
Current
Vee = Min., IOL = 8.0 rnA
lee
ISB
CEPower-Down Current
GND.s VI.s Vee
GND.s Vo.s Vee,
Output Disabled
Vee = Max., lOUT = 0 rnA,
f=fmax.
CE L 3V, lOUT = 0 rnA
Other Inputs::;; 0.8V or > 3V,
Vee = Max.
Min.
Com'l
Mil
Max.
2.4
Com'l
Mil
Com'l
I lOR = -4.0 rnA
I lOR = - 2.0 rnA
Output HIGH Voltage
Vee = Min.
Vee
0.8
+10
+10
VOL
VIR
VIL
IIX
loz
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagel 1]
Input Load Current
Output Leakage
Current
Vee Operating Supply
Current
Vee = Min., IOL = 8.0 rnA
lee
ISB
CEPower-Down Current
GND.s VI.s Vee
GND.s Vo.s Vee,
Output Disabled
Vee = Max., lOUT = 0 rnA,
f=fmax.
CE L 3V, lOUT = 0 rnA
Other Inputs::;; 0.8V or > 3V,
Vee = Max.
2.2
-0.5
-10
-10
140
50
Units
V
Vee
0.8
+10
+10
130
.145
40
Mil
V
V
V
!LA
!LA
rnA
rnA
60
Min.
Com'l
Mil
Max.
0.4
0.4
2.2
-0.5
-10
-10
Test Conditions
Description
VOR
Min.
2.4
7Bl64-12
7B166-12
Parameters
7B164-10
7B166-10
Max.
7B164-15
7B166-15
Min.
0.4
2.2
-0.5
-10
-10
Max.
2.4
2.4
Vee
0.8
+10
+10
V
0.4
2.2
-0.5
-10
-10
Units
Vee
0.8
+10
+10
Com'l
Mil
Com'l
120
140
40
135
Mil
55
50
V
V
V
!lA
!lA
rnA
rnA
Shaded area contains preliminary information.
Notes:
1. VIL (min.) = -3.0V for pulse width <20 ns.
2. TA is the "instant on" case temperature.
3.
2-155
See the last page ofthis specification for Group A subgroup testing information.
I
CY7B164
CY7B166
~
:~
-#
E:!!!!!!!IiJ ill CYPRESS
~,
SEMICONDUCTOR
Capacitance[4]
Parameters
Description
Input Capacitance
Output CapacItance
CIN
COUT
Max.P]
Test Conditions
TA = 25°C, f
VCC = 5.0V
= 1 MHz,
Units
pF
pF
6
6
AC Test Loads and Waveforms
R1481Sl
R1481Sl
5V O - - - - . . J W.........
5V O - - - - . . J W ' "
OUTPUTO---..---t
OUTPUTO---..---t
ClI
5PFI
R2
255Sl
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
ALL INPUT PULSES
3.0V - - - - ...Ir~~---~
R2
255Sl
(b)
GND
8164·7
8164·8
THEVENIN EQUIVALENT
Equivalent to:
167Sl
OUTPUT ().O----L<..\I\O
..~,.,.--__OO 1.73V
Switching Characteristics Over the Operating Rangd3, 6]
7B164-8
7B166-8
Parameters
Description
Min.
Max.
7B164-10
7B166-10
Min.
Max.
7B164-12
7B166-12
Min.
Max.
7B164-15
7B166-15
Min.
Max.
Units
15
ns
ns
READ CYCLE
tRC
tAA
tORA
tACE
tDOE
tLZOE
tHZOE
tLZCE
Read Cycle Time
Address to Data Valid
8
Output Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Zl7j
10
8
7B166
7B166
3
2.5
8
4.2
4
2
twc
tSCE
tAW
tHA
Write Cycle Time
CE LOW to Write End
8
7
Address Set-Up to Write End
7
Address Hold from Write End
0
0
tSA
tpWE
Address Set-Up to Write Start
tSD
Data Set-Up to Write End
tHD
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High ZL7]
tLZWE
tHZWE
WE Pulse Width
3
2
2
6.5
4
0
2
4
3
12
5
5
4
tHzCE
WRITE CYCLEL~J
15
12
10
5
2
1.5
7B166
CE LOW to Low ZLI:S]
CE HIGH to High ZL7, I:S]
12
10
ns
ns
7
ns
7
ns
ns
2
6
2
5
ns
15
6
ns
3
6
10
12
15
ns
8
8
0
0
8
5
0
2
0
8
8
0
0
8
6
0
2
0
10
ns
10
ns
0
0
ns
ns
ns
5
10
7
6
0
3
0
ns
ns
7
ns
ns
Notes:
4.
5.
6.
I.
Tested initially and after any design or process changes that may affect
these parameters.
For all packages except cerDIP (D10, D14), which has maximums of
CIN = 9.5 pF, COUT = 8 pR
Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH, and CL = 20 pR
tHzCE, tHzWE, and tHZOE are specified with CL = 5 pF as in part (b)
in AC Test Loads. Transition is measured ± 200 m V from steady state
voltage. This parameter is guaranteed and not 100% tested.
8.
9.
2-156
At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. These parameters are guaranteed and not
100% tested.
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
CY7B164
CY7B166
-~
. :j;; CYPRESS
- , SEMICONDUcrOR
Switching Waveforms
Read Cycle No. 1[10,11]
~------------ tRC ------------~
ADDRESS
)(
)(
-------------------------------- -----
DATA OUT
PREVIOUS DATA VALID
*X X )(-------------------DATA VALID
8164-9
Read Cycle No. 2[10, 12]
tRC
~~
/~
tACE
OE
78166
DATA OUT
/~
~,
tDOE
-tLZOEHIGH IMPEDANCE
//////
tLZCE
-
"",'\..
tHroE
tHZCE
~
DATA VALID
HIGH
IMPEDAN CE
/
8164-10
Write Cycle No.1 (WE Controlled)[9, 13, 14]
~-------------------------twc --------------------------~
ADDRESS
~----------------tSCE --------------------~
~----------------------~w --------------------~--
_ _ _~":.:..:..:.._:_::.:._t_SA_-_-_-_:..:.._::.~~~~""" I0Il1----- tpWE - - - - - - + I _ - - - - - - - - - -
14--+------DATA IN
HIGH IMPEDANCE
---------------<
tSD -----~..
HIGH IMPEDANCE
DATA-IN VALID
tHZWE
j
DATAOUT------------~(~__________N_O_T_E_1_5__________J)
tLZWE
HIGH IMPEDANCE
----.j
1(~N-0-T-E-1-5....>___
8164-11
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL. (7BI66: OE = VIL also).
12. Address valid prior to or coincident with CE transition LOW.
13. 7B166 only: Data I/O will be high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
15. During this period the I/O pins are in the output state, and input signals
should not be applied.
2-157
II
CY7B164
CY7B166
~
R'T
~~
iiiJ# CYPRESS
~, SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[9, 13, 14, 16]
~------------------------twc --------------------------~
ADDRESS
-----~I------------ tSCE ----------~
~--------------~------ ~w -----------------~~
1+-------------------- tSD
DATA IN
--------------~
- - - - - -.......
DATA-IN VALID
HIGH IMPEDANCE
DATA OUT ------------------------------------------------------------------------Bl64-12
Note:
16_ If the CE LOW transition occurs after the WE transition, the output
remains in a high-impedance state_
7B164 'fruth Table
CE
WE
H
X
HighZ
L
H
L
L
7B166 'fruth Table
Mode
CE
WE
OE
DeselectlPower-Down
H
X
X
HighZ
Data Out
Read
L
H
L
Data Out
Read
Data In
Write
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Outputs
Inputs/Outputs
Mode
DeselectlPower-Down
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Operating
Range
Package 1Ype
8
CY7B164-'8VC
V13
32-Lead (400-Mil) Molded SO]
Commercial
10
CY7B164-lODC
DlO
22-Lead (300-Mil) CerDIP
Commercial
CY7Bl64-lOPC
P9
CY7B164-lOVC
V13
12
15
CY;1B164-10~1vf13 (~t~Pto'
, q~164:'-1~~~4f[' :: J.;52
CY7B164-12DC
D10
CY7B164-12PC
P9
CY7B164-12VC
V13
22-Lead (300-Mil) Molded DIP
32-Lead (400-Mil) Molded SOl
~
~~~Lead (~OO.~) tefDlp
"?~~>,
2~:-fli.n R2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
en
- O.5V to + 7.0V
- O.5V to + 7.0V
:E
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
Commercial
c(
Electrical Characteristics Over the Operating Range
7Cl64-12
7Cl66-12
Parameter
Description
Test Conditions
VOH
Output HIGH
Voltage
Vee = Min.,
IOH = - 4.0 rnA
VOL
Output LOW
Voltage
Vee = Min.,
IOL = 8.0 rnA
VIR
Input HIGH Voltage
VIL
Input LOW
Voltagd 2]
IIX
Input Load Current
GND~ VI~
Ioz
Output Leakage
Current
GND~ Vo~
Vee,
Output Disabled
los
Output Short
Circuit Current[3]
Vee = Max.,
VOUT = GND
7C164-15
7C166-15
Min. Max. Min.
2.4
Vee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
ISBI
Automatic CE
Power-Down
Current[4]
Max. Vee, CE L VIR,
Min. Duty Cycle = 100%
ISB2
Automatic CE
Power-Down
Current[4]
Max. Vee,
CE L Vee - 0.3\1,
VIN L Vee - O.3V
or VIN ~ O.3V
7C164-20
7C166-20
Min.
Max.
Min.
Max.
2.4
2.4
0.4
7C164-25,35
7C166-25,35
0.4
Unit
V
0.4
V
2.2
Vee
2.2
Vee
2.2
Vee
2.2
Vee
V
-0.5
0.8
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
-10
+10
-10
+10
-10
+10
-10
+10
~
-10
+10
-10
+10
-10
+10
-10
+10
[.lA
,
lee
Max.
2.4
0.4
'h
".
.'
-350
-350
-350
-350
rnA
160
115
80
70
rnA
40
40
40
20
rnA
20
20
20
20
rnA
Shaded area con tams advanced mformatlOn.
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
10
pF
10
pF
Notes:
2.
3.
4.
Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
A pull-up resistor to Vee on the CE input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
5.
2-161
I
Tested initially and after any design or process changes that may affect
these parameters.
a:
CJ)
CY7C164
CY7C166
~~CYPRF.SS
~.a
~,
SEMICONDUCTOR
AC Test Loads and Waveforms
R148H1
5V o----.JVIJII-,
Rl481n
5V o----.JVIJII-,
OUTPUT 0 - - - . . - - - - - .
30
FI
P
OUTPUT
ALL INPUT PULSES
0---..-----.
3.0V ----_u------~
5PFI
R2
255.11
INCLUDING
JIGAND _
SCOPE -
R2
255.11
INCLUDING
JIGAND _
SCOPE -
(a)
GND
C164·6
Cl64·5
(b)
THEVENIN EQUIVALENT
Equivalent to:
167.11
OUTPUT 00---"1·
..111.
.. _ _--00 1.73V
Switching Characteristics Over the Operating Rangel6)
7C164-15
7C166-15
7C164-U'
7~166-12
Parameter
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Mm. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Description
READ CYCLE
1+
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from
Change
tACE
CE LOW to Data Valid
tOOE
OE LOW to Data Valid 7C166
tLZOE
OE LOW to Low Z
7C166
tHZOE
OE HIGH to High Z
7C166
tLZCE
CE LOW to Low Z[7)
tHZCE
CE HIGH to High Z[7, 8)
tpu
CE LOW to Power-Up
15
'If
Address
.!
3.
20
3
25
20
15
5
35
25
5
ns
35
5
ns
ns
';
12
15
20
25
35
ns
&
10
10
12
15
ns
.;
.
,~wQ'
,
3
1
..'
:,),.;
·3
.
8
7
0
','
,
'"
12
twc
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tpWE
WE Pulse Width
tso
Data Set-Up to Write End
tHO
Data Hold from Write End
tLZWE
WE HIGH to Low Z[7)
; 3, :i ,.
tHZWE
WE LOW to High Z[7, 8)
1;,10
i6~"
10
20
ns
15
0
0
20
ns
ns
ns
20
ns
15
20
20
25
ns
15
20
25
ns
12
15
20
25
ns
0
0
0
0
ns
0
0
0
0
ns
, .:<
12
15
15
20
ns
~:
10
10
10
15
ns
0
0
0
0
ns
5
5
5
5
ns·
9
8
5
5
0
ns
12
12
'8< :
. O.;,}."
O':r
3
10
8
15
12
3
8
5
3
0
CE HIGH to Power-Down
tpo
WRITE CYCLE[9]
3
8
"
0"
'~
6 ,•...•
Shaded area contams advanced mformatIOn.
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHzCE is less than
tLZCE for any given device. These parameters are guaranteed and not
100% tested.
7
8.
9.
2-162
7
7
10
ns
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Thst
Loads. ltansition is measured ±500 m V from steady-state voltage.
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
-
CY7C164
CY7C166
===---.~
'lE CYPRESS
- , SEM]CONDUCTOR
Switching Waveforms
Read Cycle No. IlI0, 11]
~
ADDRESS
1
---~toHA~
DATA OUT
*-
tRC
PREVIOUS DATA VALID
JXx
*===============D=A=T=A=V=A=L=ID============
C164-7
Read Cycle No. 2[10, 12]
tRC
~~
/1{:
tACE
OE
~~
7C166
14-DATA OUT
/f':
tOOE
tLZOE-
HIGH IMPEDANCE
___ f
tLZCE
VCC
SUPPLY
CURRENT
I---
I+/////v
"",1\..
~ZOE
tHZCE
3
""
DATA VALID
I+--
tpu
tpo
HIGH
IMPEDAN CE
~
CC
I
50%
50%
ISB
C164-B
Write Cycle No.1 (WE Controlled)[9, 13]
~-------------------------twc --------------------------~
ADDRESS
~----------------tSCE ------------------~~
~----------------------~w --------------------~--
____":..I-_-_-_-_-_-_-_-:._tS_A_-_-_-_-::.:.-:~=~~~ I0Il1----- tpWE -------.t _ - - - - - - - - - -
DATA IN
DATA-IN VALID
j
tHZWE
.....,,>
DATA I/O _ _ _ _ _ _ _ _D_A_TA_UN_D_E_F_IN_E_D_ _ _ _ _ _ _
tLZWE
HIGH IMPEDANCE
<,------
--I
C164-9
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = VIL. (7CI66: DE = VIL also).
12. Address valid prior to or coincident with CE transition LOW.
13. 7C166 only: Data I/O will be high impedance if DE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-163
II
CY7C164
CY7C166
~
;~PRESS
.
,
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[9,13,14j
twc - - - - - - - - - - - - -....
ADDRESS
1 4 - - - tSA - - - . - - - - - - tSCE - - - - - - . 1
tAW - - - - - - - - -....1 - -
~~~----------tSD
DATAIN
---------1'
,I,
tHO
DATA-INVAUD
*______
DATAI/O ____________________________________________
H_IG_H_I_M_P~ED_A_N~C~E~_____________
C164-10
typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ffi
1.2
..B
1.0
Icc
o
~ 0.8
:J
~ 0.6
./"
V
l7
1.2
/
III
~
6
..5:? 0.8
0
0.0
5.0
5.5
-55
6.0
1.4
j. 1.3
«
1.1
::iE
a:
0 1.0
z
I-
125
4.5
5.0
~
-.......... r--5.5
SUPPLY VOLTAGE
M
6.0
« 140
..s 120
I-
"""
2.0
3.0
a:
5
~
1.01------:::I",c..-----I
enZ
80
0.8/--:::,,,,c..----I-------l
0.6 ~-------J------I
-55
25
125
AMBIENT TEMPERATURE (0C)
2-164
g:
:::l
o
'j
60
~ 40
"
4.0
M
.JV
~ 100
~ 1.21------I----,:7£---l
oZ
1.0
z
«
TA = 25°C
0
0.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
:J
r----
20
......
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.6 , - - - - - - - , - - - - - - - ,
j.1.4
..............
6
'" "
OUTPUT VOLTAGE
o
0.9
0.8
4.0
ir
IS8
25
40
I-
Vcc = 5.0V
TA = 25°C
AMBIENT TEMPERATURE (0C)
M
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
£
Vcc = 5.0V
VIN = 5.0V
z
SUPPLY VOLTAGE
:J
a:
a: 0.4
0.2
80
:::l
0
4.5
a:
a:
:::l
~ 60
«
IS8 - I - -
1iJ 100
()
::iE
0.0
4.0
1.2
~
:J 0.6
0.2
1 120
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
UJ
N
a:
~ 0.4
0
UJ
N
1.0 ~
~
7
II
o
/
Vcc = 5.0V
TA = 25°C
J
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C164
CY7C166
~
~~
---==-_'
'lE
CYPRESS
SEMICONDUcrOR
1Ypical DC and AC Characteristics (continued)
TYPICAL POWER·ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0 ,----,,--,--,...--.,---,
3.0
.J. 2.5
25.01----1---+--+--"..'---1
J13
0
w 2.0
:J
«
::2:
a:
w
o 10.0 1--__1--7'---1-
z 1.0
0.5
0.0
0.0
1 .0
----
2.0
~
3.0
SUPPLY VOLTAGE
/
4.0
WE
H
X
HighZ
L
H
Data Out
L
L
Data In
0.50 '-0---2.1..- - -'-0------'40
1
0
3
5.0
M
CYCLE FREQUENCY (MHz)
CY7C166 Truth Table
Mode
CE
WE
OE
DeselectlPower·Down
H
X
X
Read
L
H
L
Data Out
Read
Write
L
L
H
Data In
Write
L
H
H
HighZ
Write
Input/Output
Address
Name
Address
Function
CY7C164 Pin
Number
CY7C166 Pin
Number
AS
X3
X4
X5
X6
X7
Y5
Y4
YO
Y1
Y2
Y3
XO
Xl
X2
1
2
3
4
5
6
7
8
9
17
18
19
20
21
1
2
3
4
5
6
7
8
9
19
20
21
22
23
A2
A3
A4
«
::2:
a:
~ 0.751-----+----~~1------1
Address Designators
A6
A7
A8
A9
A10
All
A12
Al3
AO
A1
:J
5.01---+-1----1-
CY7C164 Truth Table
CE
Vee = 5.0V
TA = 25°C
V1N = 0.5V
1.001-----+---1------1
N
15.01----1---+7"-+---t---I
1.5
0
~
fa
20.0
N
NORMALIZED Icc vs. CYCLE TIME
1.25
2-165
Input/Output
HighZ
Mode
DeselectlPower-Down
II
CY7C164
CY7C166
~
~~PRESS
SEMICONDUcrOR
~,.
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package lYpe
Operating
Range
~2
CY7Cl64~~2PC "
P9
22-Lead (300-Mil) Molded DIP
Commerditl
f
,CY7Cf64-12Y'C
15
20
;'
V13
CY7C164-15PC
P9
CY7C164-15VC
V13
'.
24-Lead MolCled SOl
22-Lead (300-Mil) Molded DIP
CY7C164-20PC
P9
CY7C164-20VC
V13
25
CY7C164-25PC
P9
22-Lead (300-Mil) Molded DIP
CY7C164-25VC
V13
24-Lead Molded SOJ
35
CY7C164-35PC
P9
CY7C164-35VC
V13
Speed
(ns)
12.
Ordering Code
.CY7C166-12EC
CY7C166-12VC
15
20
25
35
..
Commercial
24-Lead Molded SOJ
22-Lead (300-Mil) Molded DIP
Commercial
24-Lead Molded SOJ
22-Lead (300-Mil) Molded DIP
Commercial
Commercial
24-Lead Molded SOJ
Package
Name
Package lYpe
Operating
Range
P13
: 24-Leaq (300-Mil) Molded DIP
Commercial
....
VI3
24-Lead Molded SOl
CY7C166-15PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-15VC
V13
24-Lead Molded SOJ
CY7C166-20PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-20VC
V13
24-Lead Molded SOJ
CY7C166-25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-25VC
V13
24-Lead Molded SOJ
CY7C166-35PC
P13
24-Lead (300-Mil) Molded DIP
CY7C166-35VC
V13
24-Lead Molded SOJ
Shaded areas con tam advanced mformatIOn.
Document #: 38-00032- H
2-166
Commercial
Commercial
Commercial
Commercial
CY7C164A
CY7C166A
CYPRESS
SEMICONDUCTOR
16Kx 4 Static RAM
Features
Functional Description
• High speed
-20ns
• Output enable (OE) feature (7C166A)
• CMOS for optimum speed/power
• Low active power
-550mW
• Low standby power
-220mW
• TTL-compatible inputs and outputs
• Automatic power-down when
deselected
The CY7Cl64A and CY7C166A are highperformance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion ~rovided by an active LOW chip
enable (CE) and three-state drivers. The
CY7C166A has an active low output enable
(OE) feature. Both devices have an automatic power-down feature, reducing the
power consumption by 60% when deselected.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW (and the output
enable (OE) is LOW for the 7C166A).
Data on the four input/output pins (1/00
Logic Block Diagram
through I/03) is written into the memory
location specified on the address pins (An
through A13).
Reading the device is accomplished by taking chip enable (CE) LOW (and OE LOW
for 7C166A), while write enable (WE) remains HIGH. Under these conditions the
contents of the memory location specified
on the address pins will appear on the four
data I/O pins.
The I/O pins stay in high-impedance state
when ch~nable (CE) is HIGH, or output
enable (OE) is HIGH for 7C166A).
A die coat is used to insure alpha immunity.
Pin Configurations
DIP
Top View
DIP
Top View
AS
As
A7
As
Ag
A10
An
A'2
A'3
cr
GND
Vee
1
22
2
21
3
20
4
19
5
18
6 7C164A 17
16
15
14
9
13
10
11
12
At
As
A2
A,
I/Oa
1/°2
cr
I/O,
1/°0
OE
WE.
GND
C164A-3
Lee
Top View
A5
A7
As
Top View
u
I/O,
AS
11
C164A-2
Lee
1/0 2
A4
A"
A12
A13
Ao
I/Oa
A1
A2
A3
Ag
A,o
)f~~~
:t)f -9<....
1/°0
A7
As
Ag
A10
A"
A'2
A'3
cr
WE.
(OE)
(7C166A ONLy)
3 2
J, 22 21 20
4
19
5
18
6 7C164A 17
7
16
8
15
9
14
10111213
As
A2
A,
As
NC
A7
At
As
I/Oa
1/02
I/O,
Ao
I/Oa
1/02
cr
1~~I~g
I/O,
I~ ~ ~ I~
C164A-4
C164A-1
Aa
A2
A1
Ag
A10
An
A'2
A1a
Ao
g
C164A-5
Selection Guide[l]
7Cj:~4A -15> ...
7Cl(j6A-lS· -:;,,'
Maximum Access Time (ns)
15
Maximum 03erating
Current (rnA
Military
r~60
Maximum Standby
Current (rnA)
Military
40/20
,
....•...
Shaded area contams advanced mformatlOn.
Note:
1. For commercial specifications, see the CY7C164/CY7C166 datasheet.
2-167
7C164A-20
7C164A-20
7C164A-25
7C166A-25
7C164A-35
7C166A-35
20
25
35
100
100
100
40/20
40/20
30/20
•
CY7C164A
CY7C166A
t!;r~N=
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150 oo C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Output Current into Outputs (Low) ................ 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current ............................. >200 rnA
Operating Range
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage APBlied to Outputs
in High Z State 2] ....................... - O.5V to +7.0V
DC Input Voltagel 2] ..................... - O.5V to + 7.0V
Range
Military[3]
Ambient
Temperature
Vee
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangel 4]
'7Cl64A.-15"
7C166A-15
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Test Conditions
Max.
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
2.4
Vee
7C164A-20
7C166A-20
Min.
Max.
2.4
0.4,
2.2
Vee:"'
2.2
Unit
V
0.4
V
Vee
V
VIL
Input LOW Voltagel2]
-3.0
0.8
-3.0
0.8
V
IIX
Input Load Current
GNDs VIS Vee
-10
+10
-10
+10
IlA
Ioz
Output Leakage
Current
GNDs Vas Vee,
Output Disabled
-10
+10
-10
+10
!lA
los
Output Short
Circuit Current[5]
Vee
-350
-350
rnA
lee
Vee Operating Supply
Current
Vee = Max.,
lOUT = ornA
Military
100
100
rnA
ISBl
Automatic CE[6]
Power Down Current
Max. Vee, CE L VIH
Min. Duty Cycle = 100%
Military
40
40
rnA
ISB2
Automatic CE[6]
Power Down Current
Max. Vee,
CE L VIH - O.3V
VIN L Vee - 0.3Vor
VINSO.3V
Military
20
20
rnA
= Max., VOUT = GND
"
1
Shaded area containS advanced informatIOn.
Notes:
2. Minimum voltage is equal to - 3.0V for pulse durations less than
30ns.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing
information.;
5.
6.
2-168
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
A pull-up resistor to V cc on the CE input is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
CY7C164A
CY7C166A
~
CYPRESS
- , SEMICONDUcrOR
---,...
'1=
Electrical Characteristics Over the Operating Range [4](continued)
7C164A-25
7C166A-25
Parameter
Description
Min.
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
VIL
Input HIGH Voltage
Input LOW Voltagd 2]
IIX
Input Load Current
loz
Output Leakage Current
los
Output Short
Circuit Currentl5]
Vee
= Max., VOUT = GND
Icc
Vee Operating Supply
Current
Vee
= Max., lOUT = 0 rnA
ISBl
Automatic CE [6]
Power Down Current
ISB2
Automatic CE[6]
Power Down Current
7C164A-35
7C166A-35
Min.
Max.
Max.
Unit
2.4
2.4
Vee
0.4
V
0.4
V
Vee
2.2
Vee
V
0.8
-3.0
0.8
V
-10
+10
-10
+10
-10
+10
-10
+10
ftA
ftA
-350
-350
rnA
Military
100
100
rnA
Max. V co CE L VIR
Min. Duty Cycle = 100%
Military
40
30
rnA
Max. Veo
CE L VIR - 0.3V
VIN L Vee - O.3Vor
Military
20
20
rnA
2.2
-3.0
GND~VI~Vee
GND ~ Va ~ Vee, Output Disabled
VIN~0.3V
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
10
pF
10
pF
Note:
7. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
R1481Q
5V
0--------""""...,
OUTP~~ill
OUTPUTO---~~-~
30pF
I-=
INCLUDING
JIG AND
SCOPE (a)
Equivalent to:
5 pF
R2
255Q
I-=
INCLUDING
JIG AND
SCOPE (b)
-=
ALL INPUT PULSES
3.0V - - - -~_-----..L
R2
255Q
GND
-=
C164A-6
THEVENIN EQUIVALENT
1670
OUTPUT 00----111.,..""
.. _ - - - 0 0 1.73V
2-169
C164A-7
I
CY7C164A
CY7C166A
~
-..a'eyPRESS
~,
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd4, 8]
7C164A-20
7C166A-20
7C164A-15
7C166A-15
Description
Parameter
~
Min.
Min.
Max.
7C164A-25
7C166A-25
Min.
Max.
7C164A-35
7C166A-35
Min.
Max.
Unit
35
ns
READ CYCLE
:1:5 "
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from
Address Change
CE LOW to Data Valid
tOOE
OE LOW
(7C166A)
tLZOE
OE LOW to Low Z
(7C166A)
to
20
.,;
~;"
tACE
Data
tHZOE
OE HIGH to High Z
(7C166A)
tLZCE
CE LOW to Low Z[9]
tHZCE
CE HIGH to
High Z[9, 10]
tpu
CE LOW to Power-Up
tpo
CE HIGH to
Power-Down
...
Valid
()
, ' ~ ~
".
25
20
15
3
3
ns
35
25
3
ns
15
20
25
35
ns
t
10
12
15
ns
3
~"
3
3
ns
~<
8~.
~(
.~ '.
8
"
5
5
8
8
0
0
15
12
10
5
0
20
ns
15
10
ns
ns
0
20
20
ns
ns
WRITE CYCLE llJ
twc
Write Cycle Time
15.
20
20
25
ns
tSCE
CE LOW to Write End
10
15
20
25
ns
tAW
Address Set-Up to
Write End
10
15
20
25
ns
tHA
Address Hold from
Write End
0
0
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
10
15
15
20
ns
tso
Data Set-Up to
Write End
7
10
10
15
ns
tHO
Data Hold from
Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[9]
I.
tHzWE
WE LOW to High Z[9, 10]
V
3
5
5
/'
:.h'7
7
ns
5
7
10
ns
Shaded area contains advanced information.
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IorJIOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. These parameters are guaranteed and not
100% tested.
10. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test
Loads. Transition is measured ±500 m V from steady-state voltage.
11. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
2-170
CY7C164A
CY7C166A
~
.
:~PRESS
-0'
SEMICONDUcrOR
Switching Waveforms
•
*-
Read Cycle No. 1[12, 13]
~
ADDRESS
tRC
1
--~toHA~
DATA OUT
PREVIOUS DATA VALID
JxX
*================DA=T=A=V=A=L=ID============
C164A-8
Read Cycle No. 2[12, 14]
tRC
~~
}~
tACE
OE
7C166
~~
}Z
tDOE
DATA OUT
-
~tLZOE - HIGH IMPEDANCE
V////V
tLZCE
VCC
tHzCE
DATA VALID
~""""[\.
I+---
--- f~%
_tpu
SUPPLY
CURRENT
t~OE~
tpD
HIGH
IMPEDAN CE
~
CC
I
50%
ISS
C164A-9
Write Cycle No.1 (WE Controlled)[ll, 15]
~--------------------------twc ---------------------~
ADDRESS
14---------- tSCE ------------------.t
~--------------------~w -------------------~-
_ _ _':.I-_-_-_-_-:-:-::._tS_A_-_-_-_-::.:.:.:=~~~ l0iii.......- - tPWE
DATA IN
-----.t ~----------
DATA-IN VALID
tHZWE
j
>
DATA I/O _ _ _ _ _ _ _ _D_A_TA_UN_D_E_F_IN_E_D_ _ _ _ _ _ _ _
tLZWE
HIGH IMPEDANCE
---.j
<~----C164A-10
Notes:
12. WE is HIGH for read cycle.
13. Device is continuously selected, CE = VIL. (7C166A OE = VIL also).
14. Address valid prior to or coincident with CE transition LOW.
15. 7C166A only: Data I/O will be high impedance if OE = Vm.
2-171
CY7C164A
CY7C166A
B
~~PRESS
~_;; SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[ll, 15, 16]
~------------------------~e --------------------------~
ADDRESS
----~------ ~seE
---------+1
----~---------------
,--------~--------tAW ---------------..,..--~;--
~~~~~~~~
__
14------------
tpWE
-----------.1
~
~~~~rr~~~~~
WE
~----------
~
DATA IN
~I..
tSD - - - - - - - 1..
tHO
DATA-IN VALID
~ ' _____________
)j<.
HIGH IMPEDANCE
DATA I/O
C164A-11
Note:
16. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
gj 1.2
~
lee
1.0
/
o
~ 0.8
::J
~ 0.6
a:
~
V
./
./
1.2
~
~ 1.0
CD
8
o 0.8
4.5
5.5
5.0
SUPPLY VOLTAGE
80
~ 0.6
::!
~ 0.4
~
a:
60
0.0
-55
6.0
0
1.2
w
ir
I-
25
125
5
1.1
«
:E
a:
0 1.0
z
::J
-............
0.8
4.5
5.0
5.5
SUPPLY VOLTAGE
M
~
~
«
6.0
3.0
enZ
a:
oz
80
60
~ 40
0...
~
o
L...-_ _ _ _ _ _----'_ _ _ _ _ _ _ _ _ _--.J
-55
25
125
AMBIENT TEMPERATURE (0C)
2-172
/
r7
o
/
/
'"
4.0
M
-
...V
a:
0.6
'"""
120
~ 100
:E
r--
2.0
«' 140
N
TA = 25°C)
1.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
o
W
0.9
0
0.0
OUTPUT VOLTAGE
§.
Iz
...............
20
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
::J
Vee = 5.0V
~ r--... TA = 25°C
I-
AMBIENT TEMPERATURE (OC)
M
N
4.0
@ 40
Vee = 5.0V
VIN = 5.0V
1.6
...............
~
:::>
0.2 t - ISB
1.4
1.3
a:
:::>
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
J.
m
100
a:
()
ISB - I - -
0.0
4.0
~
w
z
0.2
g120
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
N
0.4
~
Vee = 5.0V
TA = 25°C
/
20
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
CY7C164A
CY7C166A
:~PRESS
--=-,
·
SEMICONDUCTOR
1Ypical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
j
3.0
30.0 ,...--,...--.----...,--..,----,
2.5
25.01---1---+--+--..;,.c:.....---l
(j)
J
c
0
w 2.0
N
:::J
«
1.5
:::2:
~
w
0
z 1.0
0.5
0.0
0.0
1.0
-~
2.0
~
3.0
o
/
4.0
Vee = 5.0V
TA = 25°C
VIN = 0.5V
~
@
20.0
a:
NORMALIZED Icc vs. CYCLE TIME
1.25
1.00 t - - - - - t - - - - \ - - - - - : : ; j
N
15.01---1---t7":.....-+---+----l
200
SUPPLY VOLTAGE (V)
«
:::2:
a:
~
10.0 I---~!L--+
5.0
:::J
400
600
800 1000
0.75 t-----t:~:.....--\------i
0.50 L...-_ _-..L.._ _ _L...-_ _....J
10
20
30
40
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
CY7C164A Truth Table
CY7C166A Truth Table
WE Inputs/Outputs
Mode
CE
WE
OE
X
HighZ
DeselectlPower-Down
H
X
X
HighZ
DeselectlPower-Down
L
H
Data Out
Read
L
H
L
Data Out
Read
L
L
Data In
Write
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
CE
H
Address Designators
Address
Name
Address
Function
CY7C164A
Pin Number
CY7C166A
Pin Number
AS
X3
1
1
A6
X4
2
2
A7
X5
3
3
A8
X6
4
4
A9
X7
5
5
AlO
Y5
6
6
A11
Y4
7
7
A12
YO
8
8
A13
Y1
9
9
AO
Y2
17
19
Al
Y3
18
20
A2
XO
19
21
A3
Xl
20
22
A4
X2
21
23
2-173
Inputs/Outputs
Mode
II
CY7C164A
CY7C166A
~
~~
~
'lE
IF
CYPRESS
SEMICONDUcrOR
Ordering Information
Speed
(ns)
Ordering Code
15 .
CY7C164A::;"'15DMB;
Package
'lYPe
D10 ;
Operating
Range
Package
1Ype
22·Lead (300-MiI) CerDIP'
Military
CY7Cl64A -15LMB
L52
22~Pin RectangJ,lliu ~adless Chip Carrier
CY7Cl64A-20DMB
D10
22-Lead (300-Mil) CerDIP
CY7Cl64A-20LMB
L52
22-Pin Rectangular'Leadless Chip Carrier
CY7C164A-25DMB
D10
22-Lead (300-Mil) CerDIP
CY7C164A - 25LMB
L52
22-Pin Rectangular Leadless Chip Carrier
CY7Cl64A-35DMB
DlO
22-Lead (300-Mil) CerDIP
CY7C164A-35LMB
L52
22-Pin Rectangular Leadless Chip Carrier
Speed
(ns)
Ordering Code
Package
1Ype
Package
1Ype
15
CY7C166A -15DMB
D14
24-Lead (300-Mil)CerDIP
CY7C166A-15LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C166A - 20DMB
D14
24-Lead (300-Mil) CerDIP
CY7C166A-20LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C166A-25DMB
D14
24-Lead (300-Mil) CerDIP
CY7C166A - 25LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C166A - 35DMB
D14
24-Lead (300-Mil) CerDIP
CY7C166A - 35LMB
L54
28-Pin Rectangular Leadless Chip Carrier
20
25
35
20
25
35
;
Military
Military
Military
Operating
Range
Military
Military
Military
Military
Shaded area contams advanced mformatlon.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIR
1,2,3
tAA
7,8,9, 10, 11
VILMax.
1,2,3
tOHA
7,8,9,10,11
IIX
1,2,3
7,8, 9, 10, 11
Ioz
1,2,3
tACE
tDOE[l7]
los
1,2,3
WRITE CYCLE
Icc
1,2,3
twc
7,8,9,10,11
ISBl
1,2,3
tSCE
7,8,9, 10, 11
ISBl
1,2,3
tAW
7,8,9, 10, 11
tHA
7,8,9, 10, 11
tSA
7, 8, 9, 10, 11
READ CYCLE
Document #: 38-00113-C
tpWE
7, 8, 9, 10, 11
tSD
7,8,9, 10, 11
tHD
7,8,9, 10, 11
Note:
17. 7C166A only.
2-174
7,8, 9, 10, 11
CY7C167A
16K X 1 Static RAM
Features
Functional Description
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
-15ns
• Low active power
-275mW
• Low standby power
-83mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7C167A is a high-performance
CMOS static RAM organized as 16,384
words by 1 bit. Easy memory expansion is
provided by an active LOW chip enable
(CE) and three-state drivers. The
CY7C167A has an automatic power-down
feature, reducing the power consumption
by 67% when deselected.
Writing to the device is accomplished when
the chip select (CE) and write enable (WE)
inputs are both LOW Data on the input
pin (DI) is written into the memory location specified on the address pins (A.o
through A13).
Reading the device is accomplished by taki~he chip enable (CE) LOW, while
(WE) remains HIGH. Under these condintions, the contents ofthelocation specified on the address pins will appear on the
data output (DO) pin.
The output pin remains in a high-impedance state when chip enable is HIGH, or
write enable (WE) is LOW.
A die coat is used to insure alpha immunity.
• VIHof2.2V
Logic Block Diagram
Pin Configuration
DIP
Top View
Vee
A 13
A12
A11
A 10
A9
As
Ay
DI
CE
C167A-2
C167A-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
I Commercial
I
7C167A-15
7C167A-20
7C167A-25
7C167A-35
7C167A-45
15
20
25
35
45
90
80
60
60
80
70
60
Military
2-175
50
•
·
.~
CY7C167A
~ICYPRESS
~~
SEMICONDUCTOR
Maximum Ratings
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. Ambient Temperature with
Power Applied ...................... Supply Voltage to Ground Potential
(Pm 20 to Pin 10) ......................
DC Voltage Applied to Outputs
in High Z State •.......................
DC Input Voltage. . . . . . . . . . . . . . . . . . . . ..
6SoC to + 1S0°C
SSoC to + 12SoC
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage[3]
IIX
Input Load Current
loz
Vee
O°C to +70°C
SV ± 10%
- SSoC to +12SoC
SV ± 10%
Range
Commercial
- 0.5V to +7.0V
- 3.0V to + 7.0V
Military[l]
Rangd2]
7C167A-15
7C167A-20
7C167A-25
Test Conditions
Min.
Min.
Min.
= Min., IOH = -4.0 rnA
Vee = Min.,
IOL = 12.0 rnA, 8.0 rnA Mil
2 .. 4
Description
VOH
Ambient
Temperature
- O.5V to +7.0V
Electrical Characteristics Over the Operating
Parameter
Operating Range
Vee
Max.
Max.
2.. 4
2.2
2.2
Unit
V
0.4
0.4
2.2
Max.
2.. 4
0.4
V
V
- O.S
Vee
0.8
- 0.5
Vee
0.8
- 0.5
Vee
0.8
GND.::;, VI'::;' Vee
-10
+10
-10
+10
-10
+10
fAA
Output Leakage
Current
GND.::;, Vo'::;' Vee
Output Disabled
-10
+10
-10
+10
-10
+10
ftA
los
Output Short
Circuit Current[4]
Vee
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
Automatic CE
Power-Down Current[5]
Max. Vee,
CEL VIH
ISB
= Max., VOUT = GND
Com'l
-3S0
-3S0
-3S0
rnA
90
80
60
rnA
80
70
Mil
Com'l
40
Mil
7C167A-35
Parameter
Test Conditions
Min.
= Min., IOH = -4.0 rnA
Vee = Min.,
IOL = 12.0 rnA, 8.0 rnA Mil
2..4
Description
VOH
Output High Voltage
VOL
Output Low Voltage
Vee
Max.
40
20
40
20
rnA
7C167A-45
Min.
Max.
Unit
0.4
V
V
2.. 4
0.4
2.2
V
Vee
0.8
- O.S
Vee
0.8
V
- 0.5
GND,::;,VI,::;,Vee
-10
+10
-10
+10
ftA
Output Leakage
Current
GND.::;, Vo'::;' Vee
Output Disabled
-10
+10
-10
+10
fAA
los
Output Short
Circuit Currend 4]
Vee
-3S0
-3S0
rnA
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
Coni'l
60
SO
rnA
Mil
60
SO
Automatic CE
Power-Down Current[5]
Max. Vee,
CELVIH
Com'l
20
Mil
20
VIH
Input High Voltage
VIL
Input Low Voltage[3]
IIX
Input Load Current
Ioz
ISB
= Max., VOUT = GND
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. VIL min. = - 3.0V for pulse durations less than 30 ns.
4.
2-176
2.2
V
rnA
20
Duration of the short circuit should not exceed 30 seconds.
A pull-up resistor to Vee on the CE input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
.~
=-
CY7C167A
~b CYPRESS
.SF SEMICONDUCTOR
Capacitance[6]
Parameter
Description
Test Conditions
TA = 25°C, f
VCC = 5.0V
COUT
Input Capacitance
Output Capacitance
CCE
Chip Enable Capacitance
CIN
Max.
Unit
10
pF
10
pF
6
pF
= 1 MHz,
II
U)
:E
----OO 1.9V
167Q
OUTPUT c)'0-----'\,&/\1",\>----00 1.73V
Military
Commercial
Switching Characteristics Over the Operating Rangef2, 7]
Parameter
Description
7C167A-15
7C167A-20
Min.
Min.
Max.
Max.
7C167A-25
7C167A-35
7C167A-45
Min.
Min.
Min.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
Com'l
15
Mil
tAA
Address to Data Valid
Com'l
20
25
30
20
25
35
15
Mil
tORA
Data Hold from Address Change
tACE
CE LOW to Data Valid
CE LOW to Low Z[8]
CE HIGH to High Z[8, 9]
5
CE LOW to Power-Up
0
tLZCE
tHZCE
tpu
25
30
20
25
35
5
8
8
0
15
ns
ns
0
20
20
ns
ns
5
0
ns
ns
45
15
10
0
20
15
5
5
ns
40
35
25
ns
5
5
5
20
15
CE HIGH to Power-Down
tpo
WRITE CYCLE[lO]
20
5
5
ns
40
25
ns
twc
Write Cycle Time
15
20
20
25
40
tSCE
CE LOW to Write End
12
15
20
25
30
ns
ns
tAW
Address Set-Up to Write End
12
15
20
25
30
ns
tRA
Address Hold from Write End
0
0
0
0
0
ns
tSA
tpWE
Address Set-Up to Write Start
0
0
0
0
0
ns
WE Pulse Width
12
15
15
20
20
ns
tso
Data Set-Up to Write End
10
10
10
15
15
ns
tHO
0
0
0
0
0
tHZWE
Data Hold from Write End
WE LOW to High Z[8, 9]
tLZWE
WE HIGH to Low Z[8]
5
7
7
5
Notes:
6. Tested initially and after any design or process changes that may affect
these parameters.
7. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
S. At any given temperature and voltage condition, tHZ is less than tLZ
for any given device.
7
5
5
ns
15
10
5
ns
ns
tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test
Loads. Transition is measured ±500 mV from steady state voltage.
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signal must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
9.
2-177
.-~
~=CYPRESS
CY7C167A
*
~, SEMICONDUcrOR
Switching Waveforms
Read Cycle No. 1[11,12]
~
tRC
~
ADDRESS
------
- - - - - - - - - . t ____
•
~
tAA
,
------~
..
~I
~==:~I~X~.X'-~- .~.::::::::::::::::::::::::::::::::::::
_
DAIAOUT __________________
PREVIOUS DATA.tO.H.A
VALID
______ ~ _
_
DATA VALID
C167A-5
Read Cycle No. 2[11, 13]
_____. 1+------------
tRC -----------~ ~---------------
CE
14-----
tACE
----~
HIGH
IMPEDANCE
DATA VALID
DATA OUT -------+--------------~~~~
VCC
SUPPLY
CURRENT
ICC
50%
ISS
C167A-6
Write Cycle No.1 (WE Controlled)[lO]
~------------------------twc -----------------------~
ADDRESS
~----------------tSCE -----------------~~
~------------------- tAW ------------------.~--...
-i~to+-_ _ 1+------ tPWE - - - - . / ~---------------------
_____':~::::::=__tS.A.-.-.-.-.-.-.-.-.
DATA IN
DATA-IN VALID
tHZWE
----'1
-">
tLZWE
HIGH IMPEDANCE
---I
('-----
DATA I/O _ _ _ _ _ _ _ _ _
DA.I.A.U.N.D.E.F.IN.E.D_ _ _ _ _ _ _
C167A-7
Notes:
11. WE is high for read cycle.
12. Device is continuously selected, CE = VIL.
13. Address valid prior to or coincident with CE transition LOW.
14. IfCEgoes HIGH simultaneously with WE HIGH, the output remain s
in a high-impedance state.
2-178
-
--=-F:~PRESS
CY7C167A
SEMICONDUCIOR
Switching Waveforms (continued)
•
Write Cycle No.2 (CE Controlled)[lO, 14]
~------------------------ ~c --------------------------~
ADDRESS
--------+-1---------
___________________
tSD
~I--~---------
DATA IN
DATA I/O
tSCE -------------i~
---------~~
DATA-IN VALID
tHZWE --.I
------------------------------------)I
)0--------------------------------
DATA UNDEFINED
HIGH IMPEDANCE
C167A-8
1YPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
gJ 1.2
~
Icc
1.0
~
Q
~ 0.8
::J
~ 0.6
1.2
7
V
aJ
~
<3
-2 0.8
Q
w
a::
0
z
0.2
a::
a::
:::>
4.5
5.0
5.5
1.6
1.3
j1.4
~ 10
I-
25
125
6
w 1.2
W
N
::J
::J
« 150
0.8
4.0
I-
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
1.2 I----------I---------::~-I
1.0
6.0
z
I-
Ci5
:::>
0.6 L -_ _ _ _ _ _---1_ _ _ _ _ _ _ _ _-.J
-55
25
125
AMBIENT TEMPERATURE (DC)
2-179
3.0
'"
4.0
i"'"
V
~ 100
:::>
«
0.81-7.o.,c.------+----------I
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
125
u
~
75
z
:::2:
~ 1.0
TA = 25°C
0.9
o
OUTPUT VOLTAGE (V)
z
w
Q
Q
N
........ r---.
0
= 25°C
'f\.
I-
Iss
S
"-.. ...........
Vce = 5.0V
~ 20
Vcc = 5.0V
V1N = 5.0V
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
« 1.1
a::
0 1.0
z
"'""'' -A
AMBIENT TEMPERATURE (DC)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
:::2:
'"
a::
:::>
0.0
-55
6.0
40
~ 30
0.2
Iss
«
60
S
Im 50
u
0.4
SUPPLY VOLTAGE (V)
J
~
::J 0.6
«
:::2:
0.4
0.0
4.0
Icc
N
./'
a::
~
1.0 ~
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
7
II
50
Q..
~
o
25
o
/
0.0
Vce = 5.0V
TA = 25°C
/
1.0
2.0
I
I
3.0
4.0
OUTPUT VOLTAGE (V)
5.0
¥4
CY7C167A
.... CYPRESS
. , SEMICONDUCTOR
1Ypical DC and AC Characteristics (continued)
ITPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
ITPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0 . - - - - - , ; - - - , - - , - - , - - .
3.0
0
2 .5
t)
.2
..E-
o 2.0
w
@
N
::J
«
::2
NORMALIZED Icc vs. CYCLE TIME
1.1.----,-------,----.,
Vee = 5.0V
TA = 25°C
VIH = 0.5V
1.0 I----+-----t--~
N
::J
~
1.5
«
::2
w
a:
a:
o
0
z 1.0
0.5
~
0.0
0.0
1.0
~
2.0
3.0
~ 0.91----+---,.rI'---t-----t
/
4.0
5.0
20
SUPPLY VOLTAGE (V)
Ordering Information
Speed Icc
(ns) (rnA)
15
20
25
35
45
80
80
60
60
50
Ordering Code
30
CYCLE FREQUENCY (MHz)
Package
Name
Package lYpe
Operating
Range
CY7C167A -15PC
P5
20-Lead (300-Mil) Molded DIP
CY7C167A -15VC
V5
20-Lead Molded SOJ
CY7CI67A-20PC
P5
20-Lead (300-Mil) Molded DIP
CY7C167A - 20VC
V5
20-Lead Molded SOJ
CY7CI67A-20DMB
D6
20-Lead (300-Mil) CerDIP
Military
CY7CI67A-25PC
P5
20-Lead (300-Mil) Molded DIP
Commercial
CY7CI67A-25VC
V5
20-Lead Molded SOJ
CY7CI67A-25DMB
D6
20-Lead (300-Mil) CerDIP
Military
CY7CI67A-35PC
P5
20-Lead (300-Mil) Molded DIP
Commercial
CY7CI67A-35VC
V5
20-Lead Molded SOJ
CY7CI67A-35DMB
D6
20-Lead (300-Mil) CerDIP
Military
CY7C167A -45DMB
D6
20-Lead (300-Mil) CerDIP
Military
2-180
Commercial
Commercial
40
·
~~
~li
CY7C167A
CYPRESS
~.F SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Switching Characteristics
Subgroups
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7,8,9,10,11
VIR
1,2,3
tAA
7,8,9,10,11
VILMax.
1,2,3
tORA
7,8,9,10,11
IIX
1,2,3
tACE
7,8,9,10,11
READ CYCLE
WRITE CYCLE
Ioz
1,2,3
Icc
1,2,3
twc
7,8,9,10,11
ISB
1,2,3
tSCE
7,8,9,10,11
tAW
7,8,9,10,11
tRA
7,8,9,10,11
tSA
7,8,9,10,11
tPWE
7,8,9,10,11
tSD
7,8,9,10,11
tHD
7,8,9,10,11
Document #: 38-00093-C
2-181
II
CY7C168A
CY7C169A
4Kx4RIWRAM
Features
• Automatic power-down when deselected (7CI68A)
• CMOS for optimum speed/power
• High speed
-tAA = 15 ns
- tACE = 10 ns (7CI69A)
• Low active power
-385mW
• Low standby power (7CI68)
-83mW
• TTL-compatible inputs and outputs
• VIH of2.2V
• Capable of withstanding greater than
2001V electrostatic discharge
is written into the memory location specified on the address pins (Ao through All).
Reading the device is accomplished by taki~he chip enable (CE) LOW, while
(WE) remains HIGH. Under these conditions, the contents ofthe location specified
on the address pins will appear on the four
data input/output pins (1100 through 1103).
The input/output pins remain in a high-impedance state when chip enable is HIGH
or write enable (WE) is LOW
A die coat is used to insure alpha immunity.
Functional Description
The CY7C168A and CY7C169A are highperformance CMOS static RAMs organized as 4096 by 4 bits. Easy memory expansion ~rovided by an active LOW chip
enable (CE) and three-state drivers. The
CY7C168A has an automatic power-down
feature, reducing the power consumption
by 77% when deselected.
Writing to the device is accomplished when
the chip select (CE) and write enable (WE)
inputs are both LOW. Data on the four
data input/output pins (1100 through 1/03)
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
~
Vee
As
A3
As
A2
A7
Al
As
Ao
Ag
1/0 0
Al0
1/01
All
1/00
1/01
1/°2
CE
1/°3
GND
WE
C168A-2
1/02
1/0 3
CE
WE
C168A-1
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
l Commercial
I
7C168A-15
7C169A-15
15
115
7C168A-20
7C169A-20
20
7C168A-25
7C169A-25
25
90
70
80
Military
90
2-182
7C168A-35
7C169A-35
35
70
70
7C168A-45
45
70
CY7C168A
CY7C169A
~
-.
:4
_'iECYPRESS
--=-,
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. Ambient Temperature with
Power Applied ...................... Supply Voltage to Ground Potential
(Pin 20 to Pin 10) ......................
DC Voltage Applied to Outputs
in High Z State ........................
DC Input Voltage ......................
65°C to + 150°C
55 ° C to + 125 ° C
Output Current into Outputs (Low) ............... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
- O.5V to +7.0V
- 0.5V to +7.0V
- 3.0V to + 7.0V
Ambient
Temperature
Range
Commercial
O°C to +70°C
Vee
5V ± 10%
Military[1]
- 55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangel 2]
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[3]
Test Conditions
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
Input Load Current
Output Leakage
Current
GND~ VI~ Vee
GND ~ Va ~ Vee,
Output Disabled
los
Output Short
Circuit Currentf4]
Vee
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
ISBl
Automatic CS
Power-Down Current
Max. Veo
CE~ VIH
ISB2
Automatic CE
Power-Down Current
Max. Vee,
CE~ VCC -0.3 V
= Max., VOUT = GND
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3.
4.
2-183
Com'l
Mil
Com'l
Mil
Com'l
Mil
7C168A-15
7C169A-15
Min.
Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
+10
-10
+10
7C168A-20
7C169A-20
Min.
Max.
2.4
+10
+10
Unit
V
V
V
V
[lA
[lA
-350
-350
rnA
115
90
90
40
40
20
20
rnA
40
20
0.4
2.2
-0.5
-10
-10
Vee
0.8
rnA
rnA
VIL min. = -3.0V for pulse durations less than 30 ns.
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
•
CY7C168A
CY7C169A
~
7fi~
;;'CYPRESS
~, SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangd 2) (continued)
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltagd 3]
Input Load Current
VIL
Ilx
Test Conditions
= Min., IOH = -4.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
GND~ VI~
Vee
loz
Output Leakage
Current
GND~ Vo~ Vee
Output Disabled
los
Output Short
Circuit Currentl4)
Vee
Icc
V cc Operating
Supply Current
Vcc=Max.,
lOUT = ornA
Automatic CS
Power-Down Current
Max. Vee,
CELVIH
Automatic CE
Power-Down Current
Max. Vee,
CE L VCC -0.3 V
ISBI
ISB2
= Max., VOUT = GND
7C168A-25
7C169A-25
Min. Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
+10
7C168A-35
7C169A-35
Min. Max.
2.4
0.4
2.2
Vee
-0.5
0.8
-10
10
-10
-50
+10
50
-350
-350
70
80
20
20
20
20
70
70
20
20
20
20
Com'l
Mil
Com'l
Mil
Com'l
Mil
7C168A-45
Min. Max.
2.4
Unit
V
V
V
0.4
2.2
-0.5
-10
Vee
0.8
10
!!A
-50
50
!!A
-350
rnA
V
rnA
70
rnA
20
rnA
20
Capacitance[5)
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
R1481Q
5Vo----JW......,
R1481Q
5Vo----...IW"""""'
OUTPUTo---....----t
OUTPUTo---....----t
FI
P
30
INCLUDING
JIGAND _
SCOPE -
R2
255Q
5PFI
R2
255Q
GND
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ----_J.r-...."...----~
90%
(b)
C168A-3
C168A-4
THEVENIN EQUIVALENT
167Q
OUTPUT (),O---N'''I110''---oO 1.73V
Notes:
5. Tested initially and after any design or process changes that may affect
these parameters.
6.
2-184
Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrllOH and 30-pF load capacitance.
CY7C168A
CY7C169A
=
·4
_ ' l E CYPRESS
- , SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel 3, 6)
7C168A-15
7C169A-15
Parameter
Description
Min.
Max.
7C168A-20
7C169A-20
Min.
Max.
7C168A-25
7C169A-25
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
Power Supply Current
20
15
5
I 7C168A
I 7C169A
25
20
ns
25
5
5
ns
ns
15
20
25
ns
10
12
15
ns
tLZCE
CE LOW to Low Z[7, 8)
tHZCE
CE HIGH to High Z[7, 9)
tpu
CE LOW to Power Up (7CI68)
tpD
CE HIGH to Power-Down (7CI68)
tRCS
Read Command Set-Up
0
0
0
ns
tRCH
Read Command Hold
0
0
0
ns
twc
Write Cycle Time
15
20
20
ns
tSCE
CE LOW to Write End
12
15
20
ns
tAW
Address Set-Up to Write End
12
15
20
ns
tRA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
ns
5
5
5
8
0
8
0
0
15
ns
10
20
ns
ns
20
ns
WRITE CYCLE[lO)
tSD
Data Set-Up to Write End
10
10
10
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[7)
7
tHZWE
WE LOW to High Z[7, 9)
Notes:
7. At any given temperature and voltage condition, THZ is less than tLZ
for all devices. Transition is measured ±500 m V from steady state
voltage with specified loading in part (b) of AC Test Loads and Waveforms.
8. 3-ns minimum for the CY7C169A.
9. tHZCE and tHZWE are tested with CL = 5 pF as in part (a) of Test
Loads and Waveforms. Transition is measured ± 500 m V from steady
state voltage.
7
7
5
5
ns
5
ns
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signal must be LOW to initiate a write and
either signal can terminate a write by going high. The data input setup
and hold timing should be referenced to the rising edge of the signal
that terminates the write.
11. WE is HIGH for read cycle.
12. Device is continuously selected, CE = VIL.
13. Address valid prior to or coincident with CE transition low.
14. IfCEgoes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-185
•
CY7C168A
CY7C169A
~
?J. _ .iFi~PRFSS
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel3, 6] (continued)
7C168A-35
7C169A-35
Description
Parameter
Min.
7C168A-45
Max.
Min.
Max.
Unit
45
ns
READ CYCLE
35
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
Power Supply Current
45
ns
35
I
I
5
5
7C168A
35
7C169A
25
ns
45
ns
ns
tLZCE
CE LOW to Low Z[7, 8]
tHZCE
CE HIGH to High Z[7, 9]
tpu
CE LOW to Power Up (7CI68)
tpo
CE HIGH to Power-Down (7CI68)
tRCS
Read Command Set-Up
0
0
ns
tRCH
Read Command Hold
0
0
ns
Write Cycle Time
25
40
ns
tSCE
CE LOW to Write End
25
30
ns
tAW
Address Set-Up to Write End
25
30
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
20
20
ns
tso
Data Set-Up to Write End
15
15
ns
tHO
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[7]
5
5
tHZWE
WE LOW to High Z[7, 9]
5
5
ns
15
15
0
ns
ns
0
20
25
ns
WRITE CYCLE[lO]
twc
ns
15
10
ns
Switching Waveforms
Read Cycle No. 1[11, 12]
~---------------------tRC ----------------------~
ADDRESS
'V
~IL'
-----')'I\.'-----------------')'~--~----------tAA-I------~
~tOHA
DATA OUT
PREVIOUS DATA VALID
*XX )('-_____
DA_I_AV_A_Ll_D_ _ __
C168A-5
2-186
·
CY7C168A
CY7C169A
~~
-=-.'
_'1=
CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle[ll, 13]
CE _ _ _" j o o I f - - - - - - - - - - - tRC
DATA OUT
- - - - - - - - - - - - . t , ________
II
HIGH
IMPEDANCE
---~~--------t~~!-+-{
DATA VALID
ICC
VCC
SUPPLY
CURRENT
50%
ISS
Write Cycle No.1 (WE Controlled)[lO]
~-------------twc --------------~
ADDRESS
~---------tSCE -----------~
~-----------tAW ---------~.--
___
~I-_-_-_-_-_-_-_-_t_S_A_-_-_-_-_-_-_-_-~~~~~ \+----- tPWE - - - - + I _ - - - - - - - - - -
14--+----DATA IN
-----------------~
tSD ""'-------+10..
DATA-IN VALID
j
tHZWE
>
tLZWE ----../
HIGH IMPEDANCE
DATA I/O _ _ _ _ _ _ _ _D_A_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _ _
(r--------C168A-7
Write Cycle No.2 (CS Controlled) [10, 14]
~-------------twc -------------~
ADDRESS
----.,..1--------- tSCE
--------,~
--~---------
,--------~---------
~----- tpWE -----~
~~~~~~~~~~~
,~~~~~TrTrTr~
1+-~----------tSD ---------~~
DATA IN ----------------~
DATA-IN VALID
tHZWE
DATAI/O
--I
-------------------~)>_I------H-IG-H-IM-P-E-D-A-N-C-E---_____
DATA UNDEFINED
•
C168A-8
2-187
CY7C168A
CY7C169A
~
~~PRESS
~_iF SEMICONDUCTOR
TYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
gJ 1.2
lee
111.0
Cl
~ O.B
::J
~ 0.6
~
V
./
./
VIN = 5.0V
TA = 25°C
a:
~ 0.4
1.2
CD
~ 1.0
8
Ci O.B
-
N
-
::2:
5.5
~ 20
ISB
I-
25
B
125
0
" "'"
""~
r--...
1.0
0.0
1.6
1.3
1.1.4
2.0
140
z
~ 100
Cl
::J
............
«
i'.......
-
~
4.5
5.0
5.5
SUPPLY VOLTAGE
:::r:::
::2:
TA = 25°C
0.9
O.B
4.0
Z
Ci.i
60
z
~
40
I::l
20
o
0~5~5----~25~----~125
6.0
01)
2.5
25.0
Iii'
Cl
..s
./
20.0
/
~ 15.0
0.5
l.---' ~
0.0
1.0
2.0
3.0
SUPPLY VOLTAGE
./
4.0
M
5.0
Cl
/
Vee = 5.0V
TA = 25°C
/
I
1.0
2.0
3.0
4.0
NORMALIZED Icc vs. CYCLE TIME
1.1 , - - - - , - - - - r - - - - - ,
i/
200
1.01-----+----+-----:::1
N
«
::2:
a:
Vee = 4.5V TA = 25°C
/
Jl
fa
::J
/1'
10.0
5.0
V
~
~
w
-
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
o/
0.0
AMBIENT TEMPERATURE (0C)
TYPICAL POWER· ON CURRENT
vs. SUPPLY VOLTAGE
w 2.0
N
::J
« 1.5
::2:
a:
0 1.0
z
a.
O.BI-7,c.....-----1------I
~
BO
~ 1.0
3.0
0.0
5
.--r-
/
a:
~ 1.21-------1---""7"0::.....-1
1.0
)~
I-
"
4.0
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current ............................ >200 rnA
Storage Temperature ................. - 65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 22 to Pin 21) ...................... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .. " .................... - 0.5V to +7.0V
Ambient
Temperature
Vee
Commercial
O°C to +70°C
5V ± 10%
Military[l]
- 55°C to +125°C
5V ± 10%
Range
DC Input Voltage " . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Electrical Characteristics Over the Operating Rangel 2]
7C170A-15
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
2.4
VOL
Output LOW Voltage
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
-3.0
Vee
0.8
IIX
Input Load Current
GND,::;,VI,::;,Vee
-10
loz
Output Leakage
Current
GND.::;, Vo'::;' Vee,
Output Disabled
-10
los
Output Short
Circuit Currend3]
Vee Operating Supply
Current
Vee
lee
Vee
Max.
Min.
Max.
Unit
0.4
V
2.2
-3.0
Vee
0.8
V
+10
-10
+10
V
[AA
+10
-10
+10
~A
-350
rnA
90
rnA
120
rnA
2.4
V
0.4
= Max., VOUT = GND
-350
I Com'l
Vee = Max.
lOUT = OmA
7C170A-20, 25, 35, 45
115
I Mil
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing
information.
3.
4.
= 1 MHz,
Max.
Unit
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
5V
R1481Q
o----.JVII'-1
5V
OUTPUTo---.....----t
FI
P
30
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
o----.JVII'-1
ALL INPUT PULSES
OUTPUTo---.....----t
R2
255Q
5PFI
3.0V ----_~-----'!!iI...
R2
255Q
GND
INCLUDING
JIG AND _
SCOPE -
(a)
THEVENIN EQUIVALENT
(b)
C170A-4
167Q
OUTPUT O()._ _--'\O.fllyll__--OO 1.73V
2-191
C170A-5
•
~~
CY7C170A
~"CYPRESS
~_'J SEMICONDUCIOR
Switching Characteristics Over the Operating Rangel!, 5]
Parameter
Description
7C170A-15
7C170A-20
7C170A-25
7C170A-35
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Unit
Max.
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
10
15
15
25
tDOE
OE LOW to Data Valid
10
10
12
15
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6]
tLZCS
CS LOW to Low Z[7]
15
20
15
5
25
5
3
5
3
8
5
ns
ns
ns
ns
3
10
8
8
ns
35
5
3
5
CS HIGH to High Z[6,7]
tHZCS
WRITE CYCLEL~J
35
25
20
ns
12
ns
5
5
8
10
ns
15
ns
twc
Write Cycle Time
15
20
20
25
tscs
CS LOW to Write End
12
15
20
25
ns
tAW
Address Set-Up to Write End
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
12
15
15
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
tHZWE
WE HIGH to High Z
tLZWE
WE HIGH to Low Z
7
7
7
5
5
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of I.5V, input pulse levels of 0 to 3.0V and output
loading of the specified 100/loH, and 30-pF load capacitance.
6. tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test
Loads. Transition is measured ±500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are sampled and not
100% tested.
8. The internal write time of the memory is defined by the overlap of CS
LOW and WE Law. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
9.
10.
11.
12.
13.
DATA OUT
ns
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL and OE = VIL.
Data I/O will be high-impedance ifOE = VlH.
Address valid prior to or coincident with CS transition Law.
If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Switching Waveforms
----..1;=
ns
ns
10
5
5
Read Cycle No. 1[9, 10]
ADDRESS
ns
tRC
*___
~~~==tOHA==~====::::::tt::'::-::AA~::::::::::;r-~--PREVIOUS DATA VALlD4"xXx
XX>!<________
D_A_TA_V_AL_I_D_ _ _ _ _ __
C170A·6
2-192
o
~
CY7C170A
_ o j ; CYPRESS
- , SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No. 2[9, 11]
II
DATA VALID
DATA OUT
HIGH
IMPEDANCE
tucs - - - - - . /
C170A-7
Write Cycle No. 1[8, 12]
twc
ADDRESS
tscs
CS
tSA
tPWE
WE
tSD
DATA IN
DATA I/O
DATA UNDEFINED
C170A-8
Write Cycle No. 2[8, 12, 13]
twc
ADDRESS
tscs
CS
tAW
tPWE
WE
tSD
DATA IN
DATA-IN VALID
tHZWE
DATA I/O
DATA UNDEFINED
9
HIGH IMPEDANCE
C170A-9
2-193
~~
~CYPRESS
~_, SEMICONDUCTOR
or d
.
erm~
I n Iiormation
Speed
(ns)
15
20
25
35
CY7C170A
Ordering Code
Package
Name
CY7C170A -15PC
P9
CY7C170A -15VC
V13
CY7C170A - 20PC
P9
CY7C170A - 20VC
V13
Package 1Ype
22-Lead (300-Mil) Molded DIP
Operating
Range
Commercial
24-Lead Molded SOJ
22-Lead (300-Mil) Molded DIP
Commercial
24-Lead Molded SOJ
CY7C170A - 25PC
P9
CY7C170A - 25VC
V13
24-Lead Molded SOJ
CY7C170A - 25DMB
DlO
22-Lead (300-Mil) CerDIP
Military
22-Lead (300-Mil) Molded DIP
Commercial
CY7C170A - 35PC
P9
CY7C170A - 35VC
V13
22-Lead (300-Mil) Molded DIP
Commercial
24-Lead Molded SOJ
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
READ CYCLE
VOL
1,2,3
tRC
7,8,9, 10, 11
VIR
1,2,3
tAA
7,8, 9, 10, 11
VILMax.
1,2,3
tOHA
7,8,9,10,11
IIX
1,2,3
tACS
7, 8, 9, 10, 11
Ioz
1,2,3
tOOE
7, 8, 9, 10, 11
Icc
1,2,3
WRITE CYCLE
twc
Document #: 38-00096-C
2-194
7, 8, 9, 10, 11
tscs
7, 8, 9, 10, 11
tAW
7,8, 9, 10, 11
tHA
7,8,9,10,11
tSA
7,8, 9, 10, 11
tPWE
7,8,9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7,8,9,10,11
CY7C171A
CY7C172A
CYPRESS
SEMICONDUCTOR
4K X 4 Static R/W RAM
Separate I/O
Features
Functional Description
• Automatic power-down when
deselected
• CMOS for optimum speed/power
• High speed
tAA = 15 ns
• Transparent write (7C171A)
• Low active power
- 375mW
• Low standby power
- 93mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7Cl71A and CY7CI72A are highperformance CMOS static RAMs organized as 4096 by 4 bits with separate I/O.
Easy memory expansion is~ovided by an
active LOW chip enable (CE) and threestate drivers. They have an automatic power-down feature, reducing the power consumption by 77% when deselected.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW Data on the
four input/output pins (10 through 13) is
written into the memory location specified
on the address pins (Ao through A11)'
Logic Block Diagram
Reading the device is accomplished by taking
c~ enable (CE) LOW, while write enable
(WE) remains HIGH. Under these conditions the contents of the memory location
specified on the address pins will appear on
the four data output pins.
The output pins remain in a h~impedance
state when write enable (WE) is LOW
(7CI72A only), or chip enable is HIGH.
A die coat is used to insure alpha immunity.
Pin Configurations
DIP/SOJ
Top View
10
11
00
01
00
12
02
cr
03
WE
GND
C171A-2
LCC
Top View
()
~)f~~-y~ ~
r-"I
.•
II ...
5
6
7
8
9
10
11
WE
4 3 2c1, 282726
25
24
23
7C171A
22
7C172A
21
20
19
12131415161718
A1
An
10
NC
NC
11
00
~1~~1~88o
C171A-3
C171A-1
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
I
I
Commercial
7Cl71A-35
7Cl72A-35
7Cl71A-45
7Cl72A-45
25
35
45
70
70
7C171A-15
7Cl72A-15
7Cl71A-20
7Cl72A-20
15
20
115
80
90
80
70
Military
2-195
7C171A-25
7Cl72A-25
70
CY7C171A
CY7C172A
~y:crPRES>
~J
SEMICONDUCfOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................. - 65°C to + 150°C
Ambient Thmperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential. . . . . .. - O.5V to
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - O.SV to
DC Input Voltage. . . . . . . . . . . . . . . . . . . . .. - 3.0V to
Output Current into Outputs (LOW) ..............
Static Discharge Voltage ....................... > 2001 V
(per MIL-SID-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
+7 .OV
Range
Ambient
Temperature
Vee
+ 7.0V
+ 7.0V
20 rnA
Commercial
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Military!l]
Electrical Characteristics Over the Operating Range!2]
Parameter
Test Conditions
Description
Output lllGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
= Min., IOH = - 4.0 rnA
V cc = Min., IoL = 8.0 rnA
Ioz
Output Leakage
Current
los
Output Short
Circuit Currentl3]
lee
Vee Operating
Supply Current
Vee = Max.,
V'OUT=GND
Vee = Max.
lOUT = OmA
Automatic CE
Power-Down Current
Max. Vee, CE~ VIH
Min. Duty Cycle =100%
Mil
Automatic CE
Power-Down Current
CE ~ VIH - 0.3Y,
Max. Vee,
Com'l
VIN ~ Vee - O.3Vor
Mil
VOH
VOL
VIH
VIL
IIX
ISBl
ISB2
Vee
7Cl71A-15
7Cl72A-lS
7Cl71A-20
7Cl72A-20
7Cl71A-25
7Cl72A-2S
Min.
Min.
Min.
Max.
2.4
Max.
2.4
0.4
0.4
Vee
0.8
GND~VI~Vee
2.2
-3.0
-10
+10
2.2
-3.0
-10
GND~ Vo~ Vee,
-10
+10
-10
Max.
Unit
0.4
V
V
2.4
Vee
0.8
2.2
-3.0
Vee
0.8
V
V
+10
+10
-10
-10
+10
+10
!1A
!1A
":"350
rnA
Output Disabled
Com'l
-350
-350
115
80
70
rnA
90
80
rnA
40
20
rnA
40
20
20
20
20
20
Mil
VIN~0.3V
Com'l
40
20
rnA
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3.
2-196
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
-
CY7C171A
CY7C172A
-:-~PRESS
.
- , SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangd 2] (continued)
7C171A-35
7Cl72A-35
Parameter
Description
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
2.4
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[3]
Vee
Vee
Vee Operating
Supply Current
Vee = Max.
lOUT = ornA
ISBl
Automatic CE
Power-Down Current
Max. Vee, CE L VIR
Min. Duty Cycle = 100%
ISB2
Automatic CE
Power-Down Current
Max. Vee,
CE L VIR - 0.3Y,
VIN L Vee - 0.3Vor
VOH
VOL
VIR
VIL
IIX
loz
los
lee
Max.
7Cl71A-45
7Cl72A-45
Min.
0.4
2.2
-3.0
-10
-10
GND~ VI~ Vee
GND ~ Vo~ Vee,
Output Disabled
Vee = Max.,
VOUT = GND
Unit
Vee
0.8
+10
+10
Com'l
Mil
Com'l
Mil
Com'l
70
70
20
20
20
Mil
20
V
V
V
V
0.4
2.2
-3.0
-10
-10
-350
VIN~0.3V
Max.
2.4
Vee
0.8
+10
+10
fAA
fAA
-350
rnA
rnA
rnA
70
rnA
20
rnA
20
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
Unit
10
pF
10
pF
Note:
4.
Tested initially and after any design or process changes that may affect
these parameters
AC Test Loads and Waveforms
R14810
R14810
5V O - - - - J l N I . - - ,
5 V O - - - -__........
OUTPUT 0---"",,----,
OUTPUT 0---...---4
30
FI
P
INCLUDING
JIGAND _
SCOPE -
R2
2550
5PFI
R2
2550
GND
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ----_II------~
(b)
C171A-4
THE'VENIN EQUIVALENT
1670
OUTPUT o-O-----'\.N
..·\I----OOO 1.73V
2-197
C171A-5
•
·
CY7C171A
CY7C172A
:~
_ ' . I E CYPRESS
~,
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel2,5]
Parameter
Description
7Cl71A-15
7Cl72A-15
7Cl71A-20
7Cl72A-20
7C171A-25
7Cl72A-25
7C171A-35
7Cl72A-35
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
7Cl71A-45
7Cl72A-45
Min.
Max.
Unit
READ CYCLE
Read Cycle Time
tRC
tAA
15
Address to Data Valid
tORA
Output Hold from
Address Change
tACE
CE LOW to Data Valid
CE LOW to LOW Zl6J
tLzCE
20
25
20
15
5
5
20
15
5
5
ns
ns
5
35
25
5
5
45
35
5
5
ns
45
35
25
45
ns
15
ns
ns
5
tHZCE
tpu
tpD
CE HIGH to HIGH Zl6,7J
tRCS
Read Command Set-Up
0
0
0
0
0
ns
tRCH
WRITE
Read Command Hold
0
0
0
0
0
ns
ns
CE LOW to Power Up
8
8
0
0
CE HIGH to Power Down
0
20
15
15
10
0
20
ns
0
25
20
ns
CYCLEl~J
twc
Write Cycle Time
15
20
20
25
40
tSCE
CE LOW to Write End
12
15
20
25
30
ns
tAw
tRA
Address Set-Up to Write End
12
15
20
25
30
ns
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low ZL6J (7C172A)
5
5
5
5
5
tHZWE
WE LOW to High ZL6,7J (7CI72A)
7
7
7
10
15
ns
tAWE
WE LOW to Data Valid (7CI71A)
15
20
25
30
35
ns
tADV
Data Valid to Output Valid
(7CI71A)
15
20
25
30
35
ns
Notes:
5. Test conditions assume signal transition times of S ns or less, timing reference levels of I.Sv, input pulse levels of 0 to 3.0V and output loading
of the specified IOIlIoH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tLZ for
any given device.
7. tHZCE and tHzWE are tested with CL = SpF as in part (b) of AC Test
Loads. Transition is measured ±SOO m V from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
ns
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referencd to the rising edge of the signal
that terminates the write.
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL.
11. Address valid prior to or coincident with CE transition LOW.
12. IfCE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state (7Cl72A).
Switching Waveforms
Read Cycle No.
tl 9,1O]
€v:: 3xx
tRC
ADDRESS
------
DATA OUT
~
PREVIOUS DATA
tAA
1
*-
*:::::::::::::::D:AT:A:V:A:L:ID:::::::::::
2-198
C171A·6
CY7C171A
CY7C172A
........... ~
====iii
,
CYPRF.SS
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 2[9, 11]
II
DATA OUT ----+-------~~~~
DATA VALID
VCC
SUPPLY
CURRENT
ICC
'----ISB
Write Cycle No.1 (WE ControlIed)[8]
~------------------------ ~c --------------------------~
ADDRESS
..................._ 1011-----------------
tSCE --------------------~ '"'?"'7...,.-:~.,....,+~_"7"'7'"'?"'7~
CE
_
_ _=~~~~~~~~......;tS,;.;.A_-_-_-_-_-_-_-_-......
~~~ I 0 I l - - - tPWE - - - - - -......
WE
,-----------------________________
~~-------tSD
------~.
DATA IN
DATA OUT
(7C172A)
---------------1------.. . .' ) - - - - - - - - - - r '
DATA UNDEFINED
'---------
DATA OUT ----------------~--(7C171A) _ _ _ _ _ _ _ _ _D_A_TA_U_N_DE_F_IN_E_D_ _ _ __
DATA VALID
C171A-8
Write Cycle No.2 (CE ControlIed)[8, 12]
~------------------------~C --------------------------~
ADDRESS
1 4 - - - tSA --------+01------------ tSCE
---------.1
,-------~---------
~--------------------- ~W --------------------~--
~~~~~~~~~~~I~-----------tpWE ----------~~~~~~~~~~~~
WE
___~------_ 1011--+--------
tSD
DATA IN
------------~~
DATA-IN VALID
DATA OUT
(7C172A) ___--i___D_A_TA
__
U_ND_E_F_IN_E_D__i;:========~~
__
HIGH IMPEDANCE
-------1*. .
'.
tAWE
DATA OUT
(7C171A) _______
DA_T_A_U_N_D_E_F_IN_E_D____________________--..J
,----------DA_T_A_V_A_L1_D_____
' - -_ _ _ _
C171A-9
2-199
CY7C171A
CY7C172A
~
=~~
~j; CYPRESS
F
SEMICONDUCTOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ffi
1.2
lee
13 1.0
V
o
~ 0.8
~
:2
0.6
V
./
V
~
1.0 ~
0
II:
II:
::J
w
o
::J 0.6
:2
II:
0 0.4
::J
0.2
Iss 4.5
5.0
-
g
Vee = 5.0V
VIN = 5.0V
0.0
-55
6.0
25
1.6
1.3
J1.4
5o
125
0
o
N
N
w 1.2
~
...............
--.......
0.9
0.8
4.0
~5
~O
Z
en
II:
----
oZ
5c.
5o
0~\~5--------~2~5--------~125
ao
~5
~
:2
TA = 25°C
TYPICAL POWER·ON CURRENT
vs. SUPPLY VOLTAGE
0
30.0
2 .5
25.0
.E-
N
«
:2
0
z
~
20.0
/
::::
1.5
II:
1.0
0.5
0.0
0.0
1.0
---
2.0
~
3.0
./
4.0
SUPPLY VOLTAGE (V)
5.0
« 15.0
!j
~ 10.0
5.0
0.0
~4.0
/
60
o
Vee = 5.0V
TA = 25°C
I
40
20
/
....-r-
/
0.0
/
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED Icc vs. CYCLE TIME
1.1
u;-
.s
w 2.0
3.0
/'
80
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
o
::J
120
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE (V)
2.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 100
6
«
~
1.0
II:
::J
1.1
:2
0 1.0
z
0
0.0
« 140
W
::J
"-
OUTPUT VOLTAGE (V)
5
«
'"
= 5.0V
Vee
~ ..... TA = 25°C
~ 20
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.4
II:
40
I-
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE (V)
J
80
II:
0.2
5.5
100
~ 60
«
z
0.0
4.0
ro
~
N
0.4
120
I-
6
.2 0.8
II:
~
g
1.2
til
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
/
V
o
V
/
13
@
Vee = 5.0V
TA = 25°C
VIN = 0.5V
1.01-------+------1------7\
N
::J
«
:2
/
II:
Vee = 4.5V TA = 25°C
~
0.91-------+---::;JII"=---I-------i
1 1-
200
400
600
800 1000
CAPACITANCE (pF)
2-200
20
30
CYCLE FREQUENCY (MHz)
40
CY7C171A
CY7C172A
-4
'--:1=
CYPRESS
====='..;
SEMICONDUCTOR
Ordering Information
Speed
(ns)
15
20
25
35
45
Speed
(ns)
Ordering Code
Package
Name
Package 'IYpe
CY7C171A -15PC
P13
24-Lead (300-Mil) Molded DIP
CY7C171A -15VC
V13
24-Lead Molded SOl
CY7C171A - 20PC
P13
24-Lead (300-Mil) Molded DIP
CY7C171A-20VC
V13
24-Lead Molded SOl
CY7C171A - DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C171A - 25PC
P13
24-Lead (300-Mil) Molded DIP
Commercial
CY7C171A - 25VC
V13
24-Lead Molded SOl
CY7C171A-25DMB
D14
24-Lead (300-Mil) CerDIP
CY7C171A - 25LMB
L64
28-Square Leadless Chip Carrier
CY7C171A - 35PC
P13
24-Lead (300-Mil) Molded DIP
CY7C171A-35VC
V13
24-Lead Molded SOl
CY7C171A - 35DMB
D14
24-Lead (300-Mil) CerDIP
CY7C171A - 35LMB
L64
28-Square Leadless Chip Carrier
CY7C171A-45DMB
D14
24-Lead (300-Mil) CerDIP
CY7C171A -45LMB
L64
28-Square Leadless Chip Carrier
Ordering Code
Package
Name
Package 'IYpe
15
CY7C172A-5PC
P13
24-Lead (300-Mil) Molded DIP
CY7C172A -15VC
V13
24-Lead Molded SOl
20
CY7C172A - 20PC
P13
24-Lead (300-Mil) Molded DIP
CY7C172A-20VC
V13
24-Lead Molded SOl
25
35
45
Operating
Range
Commercial
:E
c:r:
a:
(/)
Military
Commercial
Military
Military
Operating
Range
Commercial
Commercial
CY7C172A - 20DMB
D14
24-Lead (300-Mil) CerDIP
CY7C172A - 20LMB
L64
28-Square Leadless Chip Carrier
CY7C172A - 25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C172A-25VC
V13
24-Lead Molded SOl
CY7C172A-25DMB
D14
24-Lead (300-Mil) CerDIP
CY7C172A - 25LMB
L64
28-Square Leadless Chip Carrier
CY7C172A - 35PC
P13
24-Lead (300-Mil) Molded DIP
Commercial
CY7C172A-35DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C172A - 35LMB
L64
28-Square Leadless Chip Carrier
CY7C172A -45DMB
D14
24-Lead (300-Mil) CerDIP
2-201
•
en
Commercial
Military
Commercial
Military
Military
-
CY7C171A
CY7C172A
=-----~
_'1= CYPRESS
-:::;;;;;;IF
SEMICONDUcrOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VILMax.
1,2,3
IIX
1,2,3
loz
los
1,2,3
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISBl
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7,8,9, 10, 11
tAA
7,8,9,10,11
tOHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tRCS
7, 8, 9, 10, 11
tRCH
7, 8, 9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAw
7, 8, 9, 10, 11
tHA
7,8,9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9, 10, 11
tHD
7,8,9,10,11
tAWE[13]
7, 8, 9, 10, 11
tADy[13]
7,8,9, 10, 11
Note:
13. 7C171A only.
Document #: 38-00l04-C
2-202
CY7B173
CY7B174
32K X 9 Synchronous
Cache R/W RAM
Features
•
•
•
•
•
•
•
•
•
Supports SO-MHz cache systems
32K by 9 common I/O
BiCMOS for optimum speed/power
14-os access delay (clock to output)
1\vo-bit wraparound counter supporting the 486 burst sequence (7BI73)
1\vo-bit wraparound counter supporting the linear burst sequence (7BI74)
Separate address strobes from processor and from cache controller
Synchronous self-timed write
Direct interface with the processor
and external cache controller
• 1\vo complementary synchronous chip
selects
• Asynchronous output enable
is architected for other processors with linear burst sequences. Burst accesses can be
initiated with the processor address strobe
(ADSP) or the cache controller address
strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
Functional Description
The CY7B173 and CY7B174 are 32K by 9
synchronous cache RAMs designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access
delay from clock rise is 14 ns. A 2-bit onchip counter captures the first address in a
burst and increments the address automatically for the rest of the burst access.
The CY7B173 is designed for Intel
i486-based systems; its counter follows the
burst sequence of the i486. The CY7B174
A synchronous self-timed write mechanism is provided to simplify the write interface. Two complementary synchronous
chip select inputs are provided to support
two banks of memory (256 Kbytes) with no
external logic. These signals, in conjunction with the asynchronous output enable
(OE) signal, greatly simplify memory bank
selection.
Logic Block Diagram
Pin Configurations
l
r
ADDRESS
REGISTER
f->
A0- A,
'--r-
ClK
ADV.
lOGIC
ADV
-'"Jv
-fr-f-
LCC/PLCC
Top View
~
BUFFER
~
I
WE
ADSP
ADSC
~:
10
11
12
13
Do
D'I 14
15
Vssa
Vcca
16
l
D21 17
A6
32Kx 9
VSS
RAM
CORE
1
1
1
1
-
•I
J
0
10> 1~lg;
0
0
~
I'
l<: 0
.....J 0
0>
I"--
co m
0
,...
« « « «
6 5 4 3 2 '1' 44 43 42 41 40
39
!
1
TIMING
CONTROL
CSo
A~
A3
"-
CS,
~
« « « « «
38
37
36
35
7B173
34
7B174
33
32
31
30
29
18 192021 22232425262728
All
A'2
A'3
A'4
Vss
D7
D6
Vssa
Vcca
Ds
D4
B173-2
DO - D8
OE - - - - - - - - - - - - '
B173-1
Selector Guide
7B173-14
7B174-14
Maximum Access Time (ns)
Maximum Operating Current (rnA)
I
Commercial
I Military
2-203
7B173-18
7B174-18
7B173-21
7B174-21
14
18
21
210
210
210
230
230
•
en
:E
c(
a:
en
-
CY7B173
CY7B174
~~PRESS
_ , SE11ICONDUcrOR
Functional Description (continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at
clock rise: (1) CSo = 1 and CSI = 0 and (2) ADSP is Law. ADSPtriggered write cycles are completed in two clock periods. The address
at Ao through A14 is loaded into the address advancement logic and
delivered to the RAM core. The write signal is ignored in this cycle
because the cache tag or other extemallogic use this clock period to
perform address comparisons or protection checks. If the write is allowed to proceed, the write input to the CY7B 173 and CY7B 174 will
be pulled LOW before the next clock rise.
If WE is LOW at the next clock rise, information presented at Do
through Os will be stored into the location specified by the address
advancement logic. Because the CY7B173 and CY7B174 are common I/O devices, the output enable signal (OE) must be de asserted
before data from the CPU is delivered to Do through Os. As a safety precaution, the data lines (Do through Os) are three-stated in
the cycle where WE is sampled Law, regardless of the state of the
OEinput.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1) CSo = 1 and CSI = 0, (2)
ADSC is LOW, and (3) WE is Law. ADSC trigger accesses are
completed in a single clock cycle.
The address at Ao through A 14 is loaded into the address advancement logic and delivered to the RAM core. Information presented
at Do through Os will be stored into the location specified by the
address advancement logic. Since the CY7B173 and CY7B 174 are
common I/O devices, the output enable signal (OE) must be deasserted before data from the cache controller is delivered to Do
through Os. As a safety precaution, the data lines (Do through
Ds) are three-stated in the cycle where WEissampledLOW regardless of the state of the OE input.
stored into the address advancement logic and delivered to the
RAM core. If the output enable (OE) signal is asserted (LOW),
data will be available at Do through Os a maximum of 14 ns after
clock rise.
Burst Sequences
The CY7B173 provides a 2-bitwraparound counter implementing
the Intel 80486 sequence (see Table 1). Note that the burst sequence depends on the location of the first burst address.
Thble I. Counter Implementation for the Intel 80486 Sequence
Second
Address
Ax
AX+l
1
0
0
0
1
1
1
0
First
Address
Ax
Ax+ 1
0
0
1
0
0
1
1
1
Fourth
Address
Ax
Ax + 1
1
1
1
0
1
0
0
0
Third
Address
Ax
Ax + 1
1
0
1
1
0
0
0
1
The CY7B 174 provides a two-bit wraparound counter implementing a linear sequence (see Table 2).
Table 2. Counter Implementation for a Linear Sequence
First
Address
Ax+ 1 Ax
0
0
1
0
1
0
1
1
Second
Address
Ax
Ax+ 1
1
0
1
0
1
1
0
0
Third
Address
Ax
Ax + 1
1
0
1
1
0
0
0
1
Fourth
Address
Ax
Ax+ 1
1
1
0
0
1
0
1
0
Application Example
Figure 1 shows a 128-Kbyte secondary cache for the i486 using four
Single Read Accesses
A single read access is initiated when the following conditions are
satisfied at clock rise: (1) CSo = 1 and CSI = 0, (2) ADSP or ADSC
is LOW, and (3) WE is HIGH. The address at Ao through A14 is
I
osc
ClK
CY7B173 cache RAMs and a CY7B181 cache tag. Address from
the i486 is checked by the cache tag at the beginning of each access.
Match reset is delivered to the cache controller after 12 ns.
r-
128K8
-'
_
.--
ClK
ADR
DATA
1-----tH--------I-t
14-....-- ClK
ADR
CD
78181
78173
....----~ ADSC
i486
1- I
14"-'
ADV
OE
I
ADSC
Af5V
OE WEo
WEl
WE2 YVE3
ADR
DATA
~-----~~
DATA~
CACHE
CONTROllER
INTERFACE TO
MAIN MEMORY
MATCH I--------~ MATCH
DIRTY
DIRTY
VALID •
.. VALID
8173-3
Figure 1. Cache Using Four CY7BI73s
2-204
·
CY7B173
CY7B174
.~
~i= CYPRESS
- , SEMICONDUCTOR
Pin Definitions
Signal Name
I/O
Ao -A14
I
Address Inputs
CLK
I
Clock
WE
I
Write Enable
Output Enable
Description
II
OE
I
CSo, CSI
I
Chip Select
ADV
I
Address Advance
ADSP
I
Processor Address Strobe
ADSC
I
Cache Controller Address Strobe
I/O
Do - Ds
Data I/O
Vee
-
+ 5V Power Supply
Vss
-
Ground
VeeQ
-
Output Buffer (Driver) Power Supply
VSSQ
RESV
-
Output Buffer (Driver) Ground
-
Reserved
Pin Descriptions
Input Signals
CLK
Clock signal used as the reference for most on-chip operations.
ADSP
Address strobe signal from the processor: ADSP is asserted when the processor address is valid. If ADSP is LOW at
clock rise, the address at Ao through A14 will be loaded into the address register and the address advancement logic.
The write signal, WE, is ignored in the clock cycle where ADSP is asserted. If both ADSP or ADSC are active at clock
rise, only ADSP will be recognized.
ADSC
Address strobe signal from the cache controller: ADSC is asserted when a new address generated by the cache controller is ready to be strobed into the CY7B173/4. The write signal, WE, is recognized in the clock cycle where ADSC
is asserted. If both ADSP and ADSC are active at clock rise, only ADSP will be recognized.
Ao - A14
Address lines: These address inputs are loaded into the address register and the address advancement logic at clock
rise if ADSP or ADSC is LOW They are used to select one of the 32K locations.
WE
Write Enable: This signal is sampled at the rising edge ofthe clock signal. If WE = 0, a self-timed write operation will
be initiated and data on Do - Ds will be stored into the selected memory location. The only exception occurs if both
ADSP and WE are LOW at clock rise. In this case, the write signal is ignored.
ADV
Address Advance input: ADV is sampled at the rising edge of the clock. In the case of the CY7B173, LOW at this
input will advance the address in the advancement logic according to the Intel 80486 burst seguence. In the case of
the CY7B174, the addresses will be advanced linearly. This input is ignored if ADSP or ADSC is active (LOW).
CSo - CSI
Chip Select inputs: CSo is active HIGH and CSI is active LOW Both inputs are sampled at clock rise if ADSP or
ADSC is LOW The RAM is selected if CSo = 1 and CSI = O.
OE
Output Enable: OE is an asynchronous signal that disables all output drivers (Do - Ds) when it is deasserted. OE
should be de asserted during write cycles because the CY7B173/4 is a common I/O device and three-state conflict may
occur at the data pins.
NC
No Connect: This input can be left floating or tied to V ss or Vee.
Bidirectional Signals
Do - Ds
Data I/O lines: During a read cycle, if OE is asserted, data in the selected location will appear at these pins. Du.!fug a
write cycle, data presented at these pins is captured at clock rise and stored into the selected RAM location if WE is
LOW All nine outputs will be placed in a three-state condition when OE is de asserted, when the RAM is deselected
via the chip select inputs, or during a write cycle.
2-205
CY7B173
CY7B174
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Storage Temperature .................. - 65 ° C to + 150° C
Ambient Temperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage on Vee Relative to GND ... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . .. - 0.5V to Vee + 0.5V
DC Input Voltagd 1] .•.............. - O.5V to Vee + 0.5V
Current into Outputs (LOW) ...................... 20 rnA
Operating Range
Range
Commercial
Military
Ambient
Temperature[2]
Vee
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7B173-14
7B174-14
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Description
Test Conditions
Vee
Vee
Input Load Current
GND~ VI~
2.2
-0.5
-10
GND~
-100
Vee
= 0 rnA,
Min.
I Com'l
I Mil
Max.
Unit
2.4
0.4
= Max., VOUT = GND
Vee = Max. , lOUT
f = fMAX = litRe
Vee Operating
Supply Current
Icc
Max.
2.4
Vee
VIS Vee,
Output Disabled
Output Leakage
Current
Output Short
Circuit Current[3]
los
Min.
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[l]
7B173 -18, 21
7BI74-18,21
V
V
V
V
0.4
2.2
-0.5
-10
-100
Vee
0.8
+10
+100
Vee
0.8
+10
+100
itA
itA
-300
-300
rnA
210
210
230
rnA
Capacitance[4]
Parameter
Description
CIN: Addresses
Test Conditions
TA = 25°C, f
Vee = 5.0V
Input Capacitance
CIN: Other Inputs
Max.
Unit
4.5
pF
6
pF
13
pF
Output Capacitance
COUT
Notes:
1. V IL (min.) = - 1.5V for pulse durations of less than 20 ns.
2.
3.
= 1 MHz,
4. Tested initially and after any design or process changes that may affect
TA is the "instant on" case temperature.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
these parameters (PLCC package).
AC Test Loads and Waveforms
R1481Q
OUTP~~31
5V31R1481Q
OUTPUT
85 pF
R2
255Q
I _
INCLUDING
JIG AND SCOPE
-
5 PF
R2
255Q
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
ALL INPUT PULSES
3.0V ----~-----~
GND
_
8173-4
8173-5
(b)
THEVENIN EQUIVALENT
167Q
OUTPUT Oo---III¥\I\,."_ _--OO 1.73V
2-206
-=...
==.
CY7B173
CY7B174
~~
-=-_'
=====' iE
CYPRESS
SEMICONDUCTOR
Switching Characteristics
Over the Operating Rangel S)
7B173-14
7B174-14
Parameter
Description
Min.
Max.
20
7B173-18
7B174-18
Min.
Max.
25
7B173-21
7B173-21
Min.
Max.
Unit
ns
tCYC
Clock Cycle Time
30
fMAX
Maximum Frequency
tCH
Clock HIGH
8
10
12
ns
tCL
Clock LOW
8
10
12
ns
ns
40
50
33
tAS
Address Set-Up Before CLK Rise
2
4
5
tAR
Address Hold After CLK Rise
2
3
4
MHz
ns
tCDv
tDOH
Data Output Hold After CLK Rise
3
3
3
ns
tADS
ADSp, ADSC Set-Up Before CLK Rise
3
4
5
ns
tADH
ADSp, ADSC Hold After CLK Rise
2
3
4
ns
tWES
WE Set-Up Before CLK Rise
3
4
5
ns
tWEH
WE Hold After CLK Rise
2
3
4
ns
tADVS
ADV Set-Up Before CLK Rise
3
4
5
ns
tADVH
ADV Hold After CLK Rise
2
3
4
ns
14
21
ns
Data Output Valid After CLK Rise
18
tDS
Data Input Set-Up Before CLK Rise
3
4
5
ns
tDH
Data Input Hold After CLK Rise
2
3
4
ns
tcss
Chip Select Set-Up
3
4
5
ns
tCSH
Chip Select Hold After CLK Rise
2
3
4
ns
tcsoz
Chip Select Sampled to Output High Z[6, 7)
tcsov
Chip Select Sampled to Output Valid
tEoz
OE HIGH to Output High Z[6)
7
9
11
tEOV
OE LOW to Output Valid
7
9
11
ns
tWEOZ
WE Sampled LOW to Output High Z[6)
10
12
14
ns
tWEOV
WE Sampled HIGH to Output Valid
21
ns
12
10
3
3
Notes:
5. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOlJ10H and 85-pF load capacitance.
6. tcsoz, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF
as in part (b) of AC Test Loads. Transition is measured ± 500 m V from
steady state voltage.
7.
2-207
14
14
3
3
18
18
3
3
14
ns
21
ns
ns
At any given voltage and temperature, tcsoz (tWEOZ) min. is less than
tcsov (tWEOV) min.
II
CY7B173
CY7B174
·'4
~ICYPRESS
~ P'
SEMICONDUCTOR
Switching Waveforms
Single Read
ClK
CHIP
SELECTS
'7"'::----,""""~....,.~~.....,--
----~~~~~~~~
ADDRESS
ADSPor-----------------------ADSC
WE-------------jr-~-+~~~----------~-----DATA OUT
B173 7
Single 486 Write
ClK
CHIP
SELECTS ___'"'-~
ADDRESS ....~~,.I ",_ _+-_....J
DATA IN
DATA OUT
B173-6
2-~08
CY7B173
CY7B174
-~i=
4
CYPRESS
~, SEMICONDUCTOR
Switching Waveforms (continued)
•
Single Cache Controller Write
ClK
en
:E
CHIP
SELECTS
.:(
a:
CJ)
ADDRESS
ADSC
WE
DATA IN
DATA OUT
OE
B173-8
Burst Read Sequence with Four Accesses
ClK
CHIP
SELECTS
ADDRESS
ADSP or
ADSC
tADVS
ADV
tWES
tWEH
WE
OE
DATA OUT
B173-9
2-209
CY7B173
CY7B174
~
~.~
===r,
_'lE
CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Cache Controller Burst Write Sequence with Four Accesses Followed by a Single Read Cycle
ClK
CHIP
SELECTS
ADDRESS
ADSC
tADVS
ADV
WE
DATA IN
OE
DATA OUT
8173-10
Output (Controlled by OE)
_r~m~ t_tEov=f_ __
DATAO:_>
l&llfu ~ ()
..£ «0 I~ ~ ~ d ~ .t' ---4.....I-I~
TIMING
CONTROL
0
<"
g ~ I~ 8 gJ Igj uJ'luJ ocog
:Jf
»
()
()~:Jf
a:
if
Do - 08
B173A-2
~
---'-1L_-.J
OE _ _ _ _ _ _ _ _ _---1
B173A-1
Selector Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
!
Commercial
Military
7B173A-9
7B174A-9
7.5
7B173A-IO
7B174A-IO
8.5
210
210
7B173A-14
7B174A-14
11.5
180
250
Pentium is a trademark of Intel Corporation.
2-212
· ~~
_'i!lCYPRESS
--=-,
CY7B173A
CY7B174A
PRELIMINARY
SEMICONDUCTOR
Functional Description (continued)
Single-Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at
clock rise: (1) CEo = 1 and CEI = 0 and (2) ADSP is LOW ADSPtriggered write cycles are completed in two clock periods. The address
at Ao through Al4 is loaded into the address advancement logic and
delivered to the RAM core. The write signal is ignored in this cycle
because the cache tag or other external logic use this clock period to
perform address comparisons or protection checks. If the write is allowed to proceed, the write input to the CY7B173A and CY7B174A
will be pulled LOW before the next clock rise.
If WE is LOW at the next clock rise, information presented at Do
through Ds will be stored into the location specified by the address
advancement logic. Because the CY7B173A and CY7B174A are
common I/O devices, the output enable signal (OE) must be deasserted before data from the CPU is delivered to Do through Ds. As
a safety precaution, the data lines (Do through Ds) are three-stated
in the cycle where WE is sampled LOW, regardless of the state of
the OE input.
Single-Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at the rising edge of the clock: (1) CEo = 1 and CEI = 0, (2)
ADSC is Law, and (3) WE is LOW ADSC-triggered accesses are
completed in a single clock cycle.
The address at Ao through Al4 is loaded into the address advancement logic and delivered to the RAM core. Information presented
at Do through Ds will be stored into the location specified by the
address advancement logic. Since the CY7B173A and CY7B174A
are common I/O devices, the output enable signal (OE) must be
deasserted before data from the cache controller is delivered to Do
through Ds. As a safety precaution, the data lines (Do through
Ds) are three-stated in the cycle where WEissampledLOW regardless of the state of the OE input.
Single-Read Accesses
A single read access is initiated when the following conditions are
satisfied at clock rise: Q.lSEo = 1 and CEI = 0, (2) ADSP or
ADSC is Law, and (3) WE is HIGH. The address at Ao through
Al4 is stored into the address advancement logic and delivered to
l
the RAM core. If the output enable (OE) signal is asserted
(LOW), data will be available at Do through Ds a maximum of 14
ns after clock rise.
Burst Sequences
The CY7B173A provides a two-bit wraparound counter implementing the Intel80486/Pentium sequence (see Table 1). Note that
the burst sequence depends on the location of the first burst address.
Table 1. Counter Implementation for the
Intel 80486/Pentium Sequence
First
Address
Ax
Ax+ 1
0
0
1
0
1
0
1
1
Application Example
Figure 1 shows a 128-Kbyte secondary cache for the i486 using four
CY7B173A cache RAMs and a CY7B181 cache tag. Address from
the i486 is checked by the cache tag at the beginning of each access.
Match reset is delivered to the cache controller after 10 ns. This
same arrangement can be used with the Pentium processor.
128 KB
~
---
ADR
DATA
DATA
ADS I
ADSP
7B173A
ADSC
i486/Pentium
ADV
r
ClK
CD
7B181
-'
ClK
ADR
DATA
MATCH
DIRTY
VALID
Fourth
Address
Ax
Ax+ 1
1
1
1
0
0
1
0
0
Table 2. Counter Implementation for a Linear Sequence
First
Second
Third
Fourth
Address
Address
Address
Address
Ax
Ax
Ax
Ax
Ax+ 1
Ax+ 1
Ax+ 1
Ax+ 1
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
0
ClK
ADR
Third
Address
Ax
Ax + 1
1
0
1
1
0
0
0
1
The CY7B174A provides a two-bit wraparound counter implementing a linear sequence (see Table 2).
r
OSC
Second
Address
Ax
Ax+ 1
0
1
0
0
1
1
0
1
I
ClK
~
-
WE
DE
ADR
DATA
ADSP
ADSC
,lii~
ADV DE WEo
CACHE
CONTROllER
MATCH
DIRTY
VALID
Figure 1. Cache Using Four CY7B173As
2-213
WE,
WE2 WE3
~
INTERFACE TO
MAIN MEMORY
B173A-3
I
en
:E
III(
a:
(J)
~
S: ;~PRFSS
PRELIMINARY
CY7B173A
CY7B174A
. , SEMICONDUCTOR
Pin Definitions
Signal Name
I/O
Au -A14
I
Description
Address Inputs
CLK
I
Clock
WE
I
Write Enable
OE
I
Output Enable
CEO, CEI
I
Chip Enables
ADV
I
Address Advance
ADSP
I
Processor Address Strobe
ADSC
I
I/O
Do - D8
-
Vee
Vss
VeeQ
VSSQ
NC
-
Cache Controller Address Strobe
Data I/O
+5V Power Supply
Ground
Output Buffer (Driver) Power Supply
Output Buffer (Driver) Ground
Not Connected Internally
Pin Descriptions
Input Signals
CLK
Clock signal used as the reference for most ?n-chip operations.
ADSP
Address strobe signal from the processor: ADSP is asserted when the processor address is valid. If ADSP is LOW at
clock rise, the address at Au through A14 will be loaded into the address register and the address advancement logic.
The write signal, WE, is ignored in the clock cycle where ADSP is asserted. If both ADSP or ADSC are active at clock
rise, only ADSP will be recognized.
ADSC
Address strobe signal from the cache controller: ADSC is asserted whe~ew address generated by the cache controller is ready to be strobed into the CY7B173N4A. The write signal, WE, is recognized in the clock cycle where
ADSC is asserted. If both ADSP and ADSC are active at clock rise, only ADSP will be recognized.
Au - A14
Address lines: These address inputs are loaded into the address register and the address advancement logic at clock
rise if ADSP or ADSC is LOW They are used to select one of the 32K locations.
WE
Write Enable: This signal is sampled at the rising edge of the clock signal. If WE = 0, a self-timed write operation will
be initiated and data on Do - D8 will be stored into the selected memory location. The only exception occurs if both
ADSP and WE are LOW at clock rise. In this case, the write signal is ignored.
ADV
Address Advance input: ADV is sampled at the rising edge of the clock. In the case of the CY7B173A, LOW at this
input will advance the address in the advancement logic according to the Intel 80486 burst sequence. In the case of
the CY7B174A, the addresses will be advanced linearly. This input is ignored if ADSP or ADSC is active (LOW).
CEo - CEI
Chip Enable inputs: CEo is active HIGH and CEI is active LOW Both inputs are sampled at clock rise if ADSP or
ADSC is LOW The RAM is selected if CEo = 1 and CEI = O.
OE
Output Enable: OE is an asynchronous signal that disabl~s all output drivers (Do - D8) when it is deasserted. OE
should be de asserted during write cycles because the CY7B173N4A is a common I/O device and three-state conflict
may occur at the data pins.
NC
Not connected internally: Can be left open or tied to VSS or Vee.
Bidirectional Signals
Do - D8
Data I/O lines: During a read cycle, if OE is asserted, data in the selected location will appear at these pins. Du1l!!g a
write cycle, data presented at these pins is captured at clock rise and stored into the selected RAM location if WE is
LOW All nine outputs will be placed in a three-state condition when OE is de asserted, when the RAM is deselected
via the chip select inputs, or during a write cycle.
2-214
.-
·~PRESS
CY7B173A
CY7B174A
PRELIMINARY
- , SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage on Vee Relative to GND ... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . .. - 0.5V to Vee + 0.5V
DC Input Voltagel l ] ................ - 0.5V to Vee + O.5V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Military
Ambient
Temperatnre[2]
Vee
O°C to +70°C
5V±5%
- 55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIR
VIL
IIX
loz
los
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW
Voltagel l ]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[3]
7BI73A-9,10
7BI74A-9,10
Min.
Max.
Test Conditions
2.4
Vee = Min., IOH = - 4.0 rnA
2.4
0.4
Vee = Min., IOL = 8.0 rnA
GND~ VI~
7B173A-14
7B174A-14
Min.
Max.
Vee
GND~ VI~ Vee.
Output Disabled
Vee = Max., VOUT = GND
I Com'l
I Mil
Unit
V
0.4
V
2.2
-0.5
Vee
0.8
2.2
-0.5
Vee
0.8
V
V
-1
-10
+1
+10
-1
-10
+1
+10
f,lA
f,lA
-300
-300
rnA
210
180
250
rnA
Icc
Vee Operating
Supply Current
Vee = Max. , lOUT = 0 rnA,
f = fMAX = litRe
ISBl
AC Standby Current
CEo, CEI = VIR, lOUT = 0 rnA, All Inputs=
VILor VIR, VIL =O.OVand VIR 2 3.0V, Cycle
Time 2 teye Min.
50
40
rnA
ISB2
CMOS Standby
Current
CEo, CE12 Vee -0.2V,
All Inputs=Vee -O.2V or S 0.2V, Cycle
Time 2 teye Min.
40
30
rnA
Capacitance[4]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Other Inputs
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Notes:
1. VIL (min.) = - l.5V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4.
2-215
Max.
Unit
3.5
pF
4
pF
5.5
pF
Tested initially and after any design or process changes that may affect
these parameters (PLCC package).
II
CY7B173A
CY7B174A
PRELIMINARY
AC Test Loads and Waveforms
OUTP~~31R1
481Q
85 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R1481Q
OUTP~~31
R2
255Q
I-=
5 PF
I
INCLUDING _
JIG AND SCOPE
-=
(a)
ALL INPUT PULSES
3.0V - - - -...1o~----_s...
GND
R2
255Q
(b)
_
B173A-4
B173A-5
THEVENIN EQUIVALENT
167Q
OUTPUT 000----'1°."'
...""---00 1.73V
Switching Characteristics Over the Operating RangelS]
7B173A-9
7B174A-9
Description
Parameter
Min.
Max.
15
7B173A-IO
7B174A-IO
Min.
Max.
16.6
7B173A-14
7B173A-14
Min.
Max.
Unit
50
MHz
tCYC
Clock Cycle Time
fMAX
Maximum Frequency
tCH
Clock HIGH
4
5
7
ns
tCL
Clock LOW
4
5
7
ns
tAS
Address Set-Up Before CLK Rise
2.5
2.5
3
ns
0.5
0.5
1
ns
66
20
60
ns
tAH
Address Hold After CLK Rise
tCDVl
Data Output Valid After CLK Rise (O-pF Load)
7.5
8.5
11.5
ns
tCDv2
Data Output Valid After CLK Rise (85-pF Load)
9
6
13.5
ns
tDOH
Data Output Hold After CLK Rise
tADS
3
3
3
ns
ADSp, ADSC Set-Up Before CLK Rise
2.5
2.5
3
ns
tADH
ADSp, ADSC Hold After CLK Rise
0.5
0.5
1
ns
tWES
WE Set-Up Before CLK Rise
2.5
2.5
3
ns
tWEH
WE Hold After CLK Rise
0.5
0.5
1
ns
tADVS
ADV Set-Up Before CLK Rise
2.5
2.5
3
ns
tADvH
ADV Hold After CLK Rise
0.5
0.5
1
ns
tDS
Data Input Set-Up Before CLK Rise
2.5
2.5
3
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
1
ns
tCES
Chip Enable Set-Up
2.5
2.5
3
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
tCEOZ
Chip Enable Sampled to Output High Z[6, 7]
2
6
2
6
2
7
ns
tEOZ
OE HIGH to Output High Z[6]
2
6
2
6
2
7
ns
tEOV
OE LOW to Output Valid
6
6
7
ns
tWEOZ
WE Sampled LOW to Output High Z[6]
6
6
7
ns
tWEOV
WE Sampled HIGH to Output Valid
9
9
13.5
ns
Notes:
5. Unless otherwise noted, test conditions assume signal transition time
of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V, and output loading of the specified IOrJIOH and 85-pF load capacitance.
6.
7.
2-216
1
0.5
ns
tcsoz, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF
as in part (b) of AC Test Loads. Transition is measured ± 500 m V from
steady state voltage.
At anv Il:iven vo)tall:e and temnerature. tr~"7 (h""'''7) min. is less than
tcso~ (tWEOV) rrtin.
•
' ~~~~, ,,~~~,
·
.~
='iECYPRESS
---=-,
PRELIMINARY
CY7B173A
CY7B174A
SEMICONDUCTOR
Input/Output ESD and Clamp Diode Protection
vee
Vee
en
:E
.L...~
ADDRESS ....."'"""-~
WE
DATA IN
DATA OUT
B173A-8
Single Cache Controller Write
ClK
CHIP
ENABLES ~.....;:""-~~"'--;v
ADDRESS
WE
DATA IN
DATA OUT
B173A-9
2-218
~
.
-
·~PRESS
F
PRELIMINARY
CY7B173A
CY7B174A
SEMICONDUCTOR
Switching Waveforms (continued)
Burst Read Sequence with Four Accesses
II
ClK
CHIP
ENABLES
ADDRESS
ADSP or
ADSC
DATA OUT
B173A-10
2-219
_
tk.:.~
--=-,
.~
PRELIMINARY
CYPRESS
CY7B173A
CY7B174A
SEMICONDUCTOR
Switching Waveforms (continued)
Write Burst Timing: Write Initiated by ADSC
ClK
CHIP
ENABLES
Output (Controlled by OE)
F
DATAO:_>L-~
DATA OUT
B173A-14
Output Timing (Controlled by WE)
ClK
ADSCand
ADSP
DATA OUT
B173A-15
Synchronous Truth TabIe[S, 9, 10, 11]
Inputs
E
ADSP ADSC
F
F
T
T
T
X
X
X
X
L
X
L
H
H
H
H
H
H
X
L
X
L
L
H
H
H
H
ADV
W
K
X
X
X
X
X
L
L
H
H
X
X
X
L
H
L
H
L
H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L~H
Address
Mode
N/A
N/A
External Address
External Address
External Address
Next Address
Next Address
Current Address
Current Address
Deselected
Deselected
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
Asynch ronous Tr u th T:a bIe[S' 12]
EInput
Input/Output
Mode
L
H
X
X
Data Out (DOo - DOs)
HighZ
High Z, Data In (DOo .".. DOs)
HighZ
Read
Read
Write
Deselected
Notes:
8.
9.
X means Don't Care.
Allinputs except E must meet set-up and hold times for the low-to-high
transiiion of dock (K).
10. E represents CEo and CEl. T inplies CEl = L and CEo = H; F implies
CEl = H or CEo =L.
11. Wait states are inserted by suspending burst.
12. For a write operation following a read operation, OE must be HIGH
before the input data required set-up time and held HIGH through the
input data hold time.
2-222
·
-~
PRELIMINARY
~~CYPRESS
CY7B173A
CY7B174A
- , SEMICONDUCTOR
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
9
CY7BI73A-9JC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
10
CY7B173A -10JC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
14
CY7BI73A-14JC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
CY7BI73A-14LC
L67
44-Square Leadless Chip Carrier
CY7BI73A-14LMB
L67
44-Square Leadless Chip Carrier
Speed
(ns)
Ordering Code
Military
Package
Name
Package 1Ype
Operating
Range
9
CY7B174A-9JC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
10
CY7B174A -lOlC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
14
CY7BI74A-14JC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
CY7BI74A-14LC
L67
44-Square Leadless Chip Carrier
CY7BI74A-14LMB
L67
44-Square Leadless Chip Carrier
Document #: 38-00042-B
2-223
Military
I
PRELIMINARY
CYPRESS
SEMICONDUCTOR
CY7B175
32K x 9 Synchronous
Pentium@) CPU Cache R/W RAM
Features
• Supports 66-MHz Pentium CPU cache
systems
• Supports zero-wait-state performance
• 7.5-ns access delay (clock to output)
with 0 pF
• 9-ns access delay (clock to output)
with 85 pF
• Allows Pentium CPU address pipelining
• Available in PQFP with 25-Millead
pitch and standard PLCC/LCC
• BiCMOS for optimum speed/power
• 1\vo-bit wraparound counter supporting the Pentium microprocessor burst
sequence
• Separate address strobes from processor and from cache controller
• Synchronous self-timed write
• Internal clamp diodes
• Direct ip.terface with the processor
and external cache controller
• 1\vo complementary synchronous chip
enables
• Asynchronous output enable
• JEDEC-standard 44-pin PLCC pinout
Functional Description
The CY7B175 is a 32K by 9 synchronous
cache RAM designed to interface with
high-speed microprocessors with minimum glue logic. A two-bit on-chip counter
captures the first address in a burst and increments the address automatically for the
rest of the burst access.
The CY7B175 is designed for Intel Pentium microprocessor-based systems; its
counter follows the burst sequence of the
Pentium microprocessor. Burst accesses
can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. Two complementary synchronous
chip select inputs are provided to support
two banks of memory (256 Kbytes) with no
external logic. These signals, in conjunction with the asynchronous output enable
(OE) signal, greatly simplify memory bank
selection. The I/O and ADDR pins have
internal clamp diodes to prevent overshoot
and undershoot. The part is available in
the very small outline plastic quad flat pack
(PQFP) and PLCC/LCC packages.
Logic Block Diagram
Pin Configuration
LCC/PLCC/PQFP
Top View
Ao -A14--+-H
c[" <0
>
l&llfu
I~ ~ ~ 0 ~ ~ «cc «m
><:: U
0
.,£
ADDRESS
REGISTER
32Kx9
RAM
CORE
Vss
Do
D,
ClK - - - a - I C >
ADV
---+-I
ADV.
Vssa
Vcca
lOGIC
12
13
14
15
16
78175
D2
WE ----'1-+--1
TIMING
CONTROL
CEO
CE:,
ADS!'
DE
------------1
8175-1
Selector Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
I Commercial
I
7B175-7
7B175-8
7B17S-11
7.5
210
8.5
210
11.5
210
250
Military
Pentium is a trademark of Intel Corporation.
2-224
'~PRESS
PRELIMINARY
..:=::iiIi":
- , SEMICONDUCTOR
Single-Read Accesses
A single read access is initiated when the following conditions are
satisfied at clock rise: Q.2SEo = 1 and CEI = 0, (2) ADSP or
ADSC is LOW, and (3) WE is HIGH. The address at Ao through
Al4 is stored into the address advancement logic and delivered to
the RAM core. If the output enable (OE) signal is asserted
(LOW), data will be available at Do through Ds a maximum of 14
ns after clock rise. ADSP is ignored if CEo = 0 or CEI = 1.
Functional Description (continued)
Single-Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at
clock rise: (1) CEo = 1 and CEI = 0 and (2) ADSP is LOW ADSPtriggered write cycles are completed in two clock periods. The address
at Ao through Al4 is loaded into the address advancement logic and
delivered to the RAM core. The write signal is ignored in this cycle
because the cache tag or other extemallogic use this clock period to
perform address comparisons or protection checks. If the write is allowed to proceed, the write input to the CY7B175 will be pulled
LOW before the next clock rise. ADSP is ignored if CEo = 0 or CEI
=1.
If WE is LOW at the next clock rise, information presented at Do
through Ds will be stored into the location specified by the address
advancement logic. Because the CY7B175 is a common I/O device,
the output enable signal (OE) must be de asserted before data from
the CPU is delivered to Do through Ds. As a safety precaution, the
data lines (Do through Ds) are three-stated in the cycle where WE
is sampled LOW, regardless of the state of the OE input.
Single-Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at the rising edge of the clock: (1) CEo = 1 and CEI = 0, (2)
ADSC is Law, and (3) WE is LOW ADSC-triggered accesses are
completed in a single clock cycle.
The address atAo throughAl4 is loaded into the address advancement logic and delivered to the RAM core. Information presented
at Do through Ds will be stored into the location specified by the
address advancement logic. Since the CY7B175 is a common I/O
devices, the output enable signal (OE) must be deasserted before
data from the cache controller is delivered to Do through Ds. As a
safety precaution, the data lines (Do through Ds) are threestated in the cycle where WE is sampled LOW regardless ofthe
state of the OE input.
I
osc
DATA
ADS I
ADS!'
ADSC
......
ClK
MATCH
DIRTY
VALID
Fourth
Address
Ax
Ax+ 1
1
1
1
0
0
1
0
0
Application Example
Figure 1 shows a 256-Kbyte secondary cache for the Pentium microprocessor using eight CY7B175 cache RAMs and a CY7B181
cache tag. Address from the Pentium CPU is checked by the cache
tag at the beginning of each access. Match reset is delivered to the
cache controller after 10 ns.
~
~
......
......
WE
WE
WE
,lii~
DE
I
ClK
......
......
......
7B175
ADV
r
CD
Third
Address
Ax
Ax+ 1
1
0
1
1
0
0
0
1
ClK
DATA
DATA
Second
Address
Ax
Ax+ 1
0
1
0
0
1
1
1
0
ADR
Pentium
7B181
First
Address
Ax+ 1 Ax
0
0
0
1
1
0
1
1
=-
ADR
ADS'C AD'J
DE WEo
WE1
WE
t---
WE2 WE3
~t-r-
WE 4 WE5 WE6
t-r-
WE7
ADR
DATA
ADS!'
I
en
~
Burst Sequences
"
The CY7B 175 provides a two-bit wraparound counter implement _ en
ing the Intel Pentium sequence (see Table 1). Note that the burst
sequence depends on the location of the first burst address.
Table 1. Counter Implementation for the
Intel Pentium Sequence
}-
ClK
ADR
CY7B175
CACHE
CONTROllER
MATCH
DIRTY
VALID
14--
INTERFACE TO
MAIN MEMORY
B1 75-3
Figure 1. Cache Using Eight CY7B175s
2-225
.~
==au
-===.'
PRELIMINARY
_'ilICYPRESS
CY7B175
SEMICONDUCTOR
Pin Definitions
Signal Name
I/O
Ao -Al4
I
Description
Address Inputs
CLK
I
Clock
WE
I
Write Enable
OE
I
Output Enable
CEo, CEl
I
Chip Enables
ADV
I
Address Advance
ADSP
I
Processor Address Strobe
ADSC
I
Cache Controller Address Strobe
I/O
Data I/O
Vss
-
Ground
VeeQ
-
Output Buffer (Driver) Power Supply
VSSQ
NC
-
Output Buffer (Driver) Ground
-
Not Connected Internally
Do - Ds
Vee
+5V Power Supply
Pin Descriptions
Input Signals
eLK
Clock signal used as the reference for most on-chip operations.
ADSP
Address strobe signal from the processor: ADSP is asserted when the processor address is valid. If ADSP is LOW at
clock rise, the address at Ao through Al4 will be loaded into the address register and the address advancement logic.
The write signal, WE, is ignored in the clock cycle where ADSP is asserted. If both ADSP or ADSC are active at clock
rise, only ADSP will be recognized. ADSP is ignored when CEo = 0 or CEl = 1.
ADSC
Address strobe signal from the cache controller: ADSC is asserted when a new address generated by the cache controller is ready to be strobed into the CY7B175/4A. The write signal, WE, is recognized in the clock cycle where
ADSC is asserted. If both ADSP and ADSC are active at clock rise, only ADSP will be recognized.
Ao -
Address lines: These address inputs are loaded into the address register and the address advancement logic at clock
rise if ADSP or ADSC is LOW. They are used to select one of the 32K locations.
Al4
WE
Write Enable: This signal is sampled at the rising edge of the clock signal. If WE = 0, a self-timed write operation will
be initiated and data on Do - Ds will be stored into the selected memory location. The only exception occurs if both
ADSP and WE are LOW at clock rise. In this case, the write signal is ignored.
ADV
Address Advance input: ADV is sampled at the rising edge of the clock. In the case of the CY7B175, LOW at this
input will advance the address in the advancement logic according to the Intel 80486 burst sequence. In the case of
the CY7B174A, the addresses will be advanced linearly. This input is ignored if ADSP or ADSC is active (LOW).
CEo - CEl
Chip Enable inputs: CEo is active HIGH and CEl is active LOW. If CEo = 0, CEl = 1 and ADSC is LOW, the
SRAM is deselected. If CEo = 1, CEl = 0 and ADSC or ADSP is LOW, a new address is captured by the address
register. If CEo = 0 or CEo = 1, ADSP is ignored.
OE
Output Enable: OE is an asynchronous signal that disables all output drivers (Do - Ds) when it is deasserted. OE
should be de asserted during write cycles because the CY7B175/4A is a common I/O device and three-state conflict
may occur at the data pins.
NC
Not connected internally: Can be left open or tied to VSS or Vee.
Bidirectional Signals
Do - Ds
Data I/O lines: During a read cycle, if OE is asserted, data in the selected location will appear at these pins. Du.!i!!g a
write cycle, data presented at these pins is captured at clock rise and stored into the selected RAM location if WE is
LOW. All nine outputs will be placed in a three-state condition when OE is de asserted, when the RAM is deselected
via the chip select inputs, or during a write cycle.
2-226
g. .. -~
Eiiiiiiiiil CYPRESS
-=-
PRELIMINARY
CY7B175
jF SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage on Vee Relative to GND ... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . .. - 0.5V to Vee + 0.5V
DC Input Voltage[1] ............. . .. - O.5V to Vee + 0.5V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Military
Ambient
Temperature[2]
Vee
O°C to +70°C
5V±5%
- 55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
IIX
loz
los
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW
Voltagd l ]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[3]
7BI75-7,8
Min.
Max.
2.4
Test Conditions
Vee = Min., IOH = - 4.0 rnA
7BI75-11
Min.
Max.
2.4
0.4
Vee = Min., IOL = 8.0 rnA
GND~VI~Vce
GND ~ VI~ Vee,
Output Disabled
Vee = Max., VOUT = GND
I Com'l
I Mil
Unit
V
0.4
V
2.2
-0.5
Vee
0.8
2.2
-0.5
Vee
0.8
V
V
-1.0
-10
+1.0
+10
-1.0
-10
+1.0
+10
[.lA
[.lA
-300
-300
rnA
210
210
250
rnA
Icc
Vee Operating
Supply Current
Vec = Max., lOUT = 0 rnA,
f = fMAX = litRe
ISBl
AC Standby Current
CEo, CEl = VIH, lOUT = 0 rnA, All Inputs=
VILor VIH, VIL =O.OVandVIH~ 3.0Y,Cycle
Time 2: tcye Min.
50
50
rnA
ISB2
CMOS Standby
Current
CEo, CEl 2: Vee -0.2Y,
All Inputs=Vee -0.2V or :::; 0.2Y, Cycle
Time 2: teye Min.
40
40
rnA
Capacitance[4]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Other Inputs
COUT
Notes:
1.
2.
3.
Test Conditions
TA = 25°C, f = 1 MHz,
Vce = 5.0V
Output Capacitance
VIL (min.) = - 1.5V for pulse durations of less than 20 ns.
TA is the "instant on" case temperature.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4.
2-227
Max.
Unit
3.5
pF
4
pF
5.5
pF
Tested initially and after any design or process changes that may affect
these parameters (PLCC package).
I
SF
;~
=====
-= CYPRESS
~,
PRELIMINARY
CY7B175
SEMICONDUCTOR
AC Test Loads and Waveforms
OUTP~~31R1
OUTP~~31R1
481Q
85
PFI
INCLUDING
JIG AND
SCOPE
Equivalent to:
-=
R2
255Q
(a)
ALL INPUT PULSES
3.0V ----..JI~~---~
481Q
5
PFI
INCLUDING _
JIG AND SCOPE
-=
GND
R2
255Q
_
-
8175-4
(b)
8175-5
THEVENIN EQUIVALENT
1670
OUTPUT~1.73V
Switching Characteristics Over the Operating RangdS]
7B175-7
Parameter
Description
Min.
Max.
7B175-8
Min.
Max.
7BI75-11
Min.
Max.
Unit
tCYC
Clock Cycle Time
fMAX
Maximum Frequency
tCH
Clock HIGH
4
5
7
ns
tCL
Clock LOW
4
5
7
ns
tAS
Address Set-Up Before CLK Rise
2.5
2.5
3
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
tCDVl
Data Output Valid After CLK Rise (O-pF Load)
15
16.6
60
66
tCDV2
Data Output Valid After CLK Rise (85-pF Load)
tDOH
Data Output Hold After CLK Rise
tADS
20
7.5
50
8.5
10
9
ns
MHz
ns
11.5
ns
13.5
ns
3
3
3
ns
ADSp, ADSC Set-Up Before CLK Rise
2.5
2.5
3
ns
tADH
ADSp, ADSC Hold After CLK Rise
0.5
0.5
1
ns
tWES
WE Set-Up Before CLK Rise
2.5
2.5
3
ns
tWEH
WE Hold After CLK Rise
0.5
0.5
1
ns
tADVS
ADV Set-Up Before CLK Rise
2.5
2.5
3
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
1
ns
tDS
Data Input Set-Up Before CLK Rise
2.5
2.5
3
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
1
ns
tCES
Chip Enable Set-Up
2.5
2.5
3
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
1
ns
tCEOZ
Chip Enable Sampled to Output High Z[6, 7]
2
6
2
6
2
7
tEOZ
OE HIGH to Output High Z[6]
2
6
2
6
2
7
ns
tEOV
OE LOW to Output Valid
6
6
ns
tWEOZ
WE Sampled LOW to Output High Z[6]
6
6
7
ns
tWEOV
WE Sampled HIGH to Output Valid
9
10
13.5
ns
Notes:
5. Unless otherwise noted, test conditions assume signal transition time
of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V, and output loading of the specified IorJIOH and 85-pF load capacitance.
6.
7.
2-228
6
ns
tcsoz, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF
as in part (b) of AC Test Loads. Transition is measured ± 500 m V from
steady state voltage.
At any given voltage and temperature, tcsoz (tWEOZ) min. is less than
tcsov (tWEOV) min.
~
. :aPRESS
PRELIMINARY
- , SEMICONDUCTOR
CY7B175
Input/Output ESD and Clamp Diode Protection
vee
II
Vee
ADDR/CONTROl
INPUT
~ _ _r ___
TO DEVICE
TO DEVICE
(a) Input ESD and Clamp Diode
DATA
INPUT/OUTPUT
PIN
(b) Input/Output ESD and Clamp Diode
8175-6
Switching Waveforms
Single Read
ClK
CHIP
ENABLES ......._~~___......~'--~~'--~
ADDRESS
ADSP[8] or
ADSC
DATA OUT
8175-7
Note:
8. If ADSP is asserted while CEo
= 0 or CEo = 1, ADSP will be ignored.
2-229
-~
~j,
~IF
PRELIMINARY
CYPRESS
CY7B175
SEMICONDUCTOR
Switching Waveforms (continued)
ADSPWrite
CLK
CHIP
.--~-",.
ENABLES '--::..L-~
ADDRESS """-~;......;.,
DATA IN
DATA OUT
B175-8
Single Cache Controller Write
CLK
CHIP
~~~~~~~
ENABLES ~~lIo.L..~~~~
ADDRESS
DATA IN
DATA OUT
B175-9
2-230
~
·~PRFSS
PRELIMINARY
.
- , SEMICONDUcrOR
CY7B175
Switching Waveforms (continued)
•
Burst Read Sequence with Four Accesses
ClK
CHIP
ENABLES
ADDRESS
ADSP[8] or
ADSC
DATA OUT
2-231
9iFt .~
~~CYPRESS
-::Jf!!!I!!!IT,
PRELIMINARY
CY7B175
SEMICONDUCTOR
Switching Waveforms (continued)
Write Burst Timing: Write Initiated by ADSC
ClK
CHIP
ENABLES
Output (Controlled by OE)
F~oz ~
DATAO:_>L-...:.I
DATA OUT
CHIP ENABLES
ASSERTED
8175-14
2-233
-
~~PRESS
-::fJi!!!!!!IT., SEMICONDUcrOR
PRELIMINARY
CY7B175
Switching Waveforms (continued)
Output Timing (Controlled by WE)
8175-15
Synchronous Truth Table[9, 10, 11, 12]
Inputs
E
ADSP
ADSC
ADV
W
K
F
X
L
X
X
L-H
N/A
Deselected
F
L
H
H
H
L-H
Same address as previous cycle
Read cycle (ADSP ignored)
F
L
H
L
H
L-H
Incremented burst address
Read cycle, in burst sequence (ADSP
ignored)
F
L
H
H
L
L-H
Same address as previous cycle
Write cycle (ADSP ignored)
F
L
H
L
L
L-H
Incremented burst address
Write cycle, in burst sequence (ADSP
ignored)
Mode
Address
T
L
X
X
X
L-H
External address
Read cycle, begin burst
T
H
L
X
L
L-H
External address
Write cycle, begin burst
T
H
L
X
H
L-H
External address
Read cycle, begin burst
X
H
H
L
L
L-H
Next address
Write cycle, continue burst
X
H
H
L
H
L-H
Next address
Read cycle, continue burst
X
H
H
H
L
L-H
Current address
Write cycle, suspend burst
X
H
H
H
H
L-H
Current address
Read cycle, suspend burst
Asynchronous Truth Table[9, 11, 13]
E
Input/Output
Mode
T
Data Out (DOo - DOs)
F
HighZ
Read
X
High Z, Data In (DOo - DOs)
Write
X
HighZ
Deselected
Read
Notes:
9. X means Don't Care.
10. All inputs except Emust meet set-up and hold times for the low-to-high
transition of clock (K).
11. ErepresentsCEo and CEl. TinpliesCEl = Land CEo =H; Fimplies
CEl = H or CEo =L.
12. Wait states are inserted by suspending burst.
13. For a write operation following a read operation, OE must be HIGH
before the input data required set-up time and held high through the
input data hold time.
2-234
.
-
:~PRESS
F
PRELIMINARY
Ordering Information
Speed
(ns)
7.5
8.5
11.5
CY7B175
SEMICONDUcrOR
Ordering Code
Package
Name
Package 1)rpe
Operating
Range
Commercial
CY7B175-7JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7B175-7NC
N67
TBD
CY7B175-8JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7B175-8NC
N67
TBD
CY7B175-11JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7B175-11NC
N67
TBD
CY7B175 -llLC
L67
44-Square Leadless Chip Carrier
CY7B175 -llLMB
L67
44-Square Leadless Chip Carrier
Document #: 38-A-00043
2-235
Commercial
Commercial
Military
•
CY7C178
CY7C179
PRELIMINARY
32K X 18 Synchronous
Cache RAM
Features
• Supports 66-MHz Pentium@) microprocessor cache systems with zero
wait states
• 32K by 18 common I/O
• Fast c1ock-to-output times
- 8.5 ns with O-pF load
- 10 ns with 85-pF load
• 1\vo-bit wraparound counter supporting Pentium and 486 burst sequence
(7CI78)
• 1\vo-bit wraparound counter supporting linear burst sequence (7CI79)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor
and external cache controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• Industry-standard pinout
• 52-pin PLCC and PQFP
Functional Description
The CY7C178 and CY7C179 are 32K by
18 synchronous cache RAMs designed to
in terface with high -speed microprocessors
with minimum glue logic. Maximum access
delay from clock rise is 8.5 ns. A 2-bit onchip counter captures the first address in a
burst and increments the address automatically for the rest of the burst access.
The CY7C178 is designed for Intel Pentium and i486 CPU - based systems; its
counter follows the burst sequence of the
Pentium and the i486 processors. The
CY7C179 is architected for processors
with linear burst sequences. Burst accesses
can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for bank selection and
output three-state control.
Pin Configuration
Logic Block Diagram
PLCC
Top View
.f.tIBI~I~I~I~I~ d I~
ADSP
ADSC 4-----t..
cs ....- -.....
TIMING
CONTROL
- - - - - - t..
wc------t..L -_ _----I
VSSO
VCCO
16
17
D014
D015
DP1 [1]
18
19
20
WH
DOs
D04
D0 13
CLK--4.....- - - i
DPO[l]
D03
D02
VSSO
veco
34
DOl
DOo
21 22 23 24 25 26 27 28 29 30 31 32 33
18
178-1
D0 1S - DOo
DPl - DPo
'OE------------O
178-2
Selector Guide
7C178-8
7C179-8
7C178-10
7C179-10
7C178-12
7C179-12
8.5
10.5
12.5
295
265
Maximum Access Time (ns) (O-pF Load)
Maximum Operating Current (rnA)
I Commercial
I M~litary .,. /':
Shaded area con tams advanced mformatlon.
Pentium is a trademark of Intel Corporation.
Note:
1. DPo and DP! are functionally equivalent to DQx'
2-236
'
..'/
/
215
..
>
220,
.
-
;;~pRF.SS
JF
CY7C178
CY7C179
PRELIMINARY
SEMICONDUCTOR
Functional Description (continued)
Single Write Accesses Initiated by ADSP
This access is initi51ted when the following conditions are satisfied at
clock rise: (1) CS is LOW and (2) ADSP is LOW. ADSP-triggered
write cycles are completed in two clock periods. The address at Ao
through Al4 is loaded into the address register and address advancement logic and delivered to the RAM core. The write signal is ignored
in this cycle because the cache tag or other external logic uses this
clock period to perfonn address comparisons or protection checks. If
the write is allowed to proceed, the write input to the CY7C178 and
CY7C179 will be pulled LOW before the next clock rise. ADSP is
ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information
presented at DOo - DOl5 and DPo - DPl will be written into the
location specified by the address advancement logic. WL controls
the writing ofDOo - D07 and DPo while WH controls the writing
ofD08 - DOl5 and DPl. Because the CY7C178 and CY7C179
are common-I/O devices, the output enable signal (OE) must be
de asserted before data from the CPU is delivered to DOo - DOl5
and DPo - DPl. As a safety precaution, the appropriate data lines
are three-stated in the cycle where WH, WL, or both are sampled
LOW, regardless of the state of the OE input.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1) CS is Law, (2) ADSC is
LOW, and (3) WH or WL are Law. ADSC triggered accesses are
completed in a single clock cycle.
The address at Ao through Al4 is loaded into the address register
and address advancement logic and delivered to the RAM core. Information presented at DOo - DO l 5 and DPo - DPl will be written into the location specified by the address advancement logic.
Since the CY7C178 and the CY7C179 are common-I/O devices,
the output enable signal (OE) must be deasserted before data from
the cache controller is delivered to the data and parity lines. As a
safety precaution, the appropriate data and parity lines are
three-stated in the cycle where WH and WLare sampled LOW
regardless of the state of the OE input.
Single Read Accesses
A single read access is initiated when the following conditions are
satisfied at clock rise: (1) CS is Law, (2) ADSP or ADSC is Law,
I
66·MHz osc
r--
Burst Sequences
U)
The CY7C178 provides a 2-bitwraparound counter, fed by pins Ao
- A I, that implements the Intel 80486 and Pentium processor's ad- CC
dress burst sequence (see Table 1). Note that the burst sequence
depends on the first burst address.
(/)
==
a::
Table 1. Counter Implementation for the Intel
Pentium/80486 Processor's Sequence
Fourth
Address
Ax + 1, Ax
11
11
11
10
00
01
10
01
00
11
Table 2. Counter Implementation for a Linear Sequence
First
Address
Ax+ hAx
00
01
10
Second
Address
Ax + 1, Ax
01
10
Third
Address
Ax+ hAx
10
Fourth
Address
Ax + 1, Ax
11
11
00
01
00
01
10
11
00
Application Example
microprocessor using four CY7C178 cache RAMs.
ClK
ADR
DATA
ADSP
ADSC
PENTIUM
PROCESSOR
OE
I
ClK ADSC
ClK
~
7C178
ADV
r
11
Figure 1 shows a 256-Kbyte secondary cache for the Pentium
DATA
ADR
DATA
ADSP
DATA
MATCH
DIRTY
VALID
Third
Address
Ax + 1, Ax
10
The CY7C179 provides a two-bit wraparound counter, fed by pins
Ao - AI, that implements a linear address burst sequence (see
Table 2).
ADS
CD
Second
Address
Ax+ hAx
01
00
256~
ADR
ADR
First
Address
Ax+ hAx
00
01
10
"..-
ClK
CACHE
TAG
and (3) WH and WL are HIGH. The address atAo through Al4 is
stored into the address advancement logic and delivered to the
RAM core. If the output enable (OE) signal is asserted (LOW),
data will be available at the data outputs a maximum of 8.5 ns after •
clock rise. ADSP is ignored if CS is HIGH.
WR~l
~,W[~~
Ar5V OE ~,
WLo
WA 1,
W[1
CACHE
CONTROllER
MATCH
DIRTY
VALID
Figure 1. Cache Usin2 Four CY7C178s
2-237
1
2
WH2,
W[2
2
WA3,
W[3
1---1 NTERFACETO
MAIN MEMORY
178-3
~~PRESS
-=-.F
CY7C178
CY7C179
PRELIMINARY
SEMICONDUCTOR
Pin Definitions
Signal Name
1Ype
# of Pins
VCC
Input
1
Description
+5VPower
VCCQ
Input
4
+5V or 3.3V (Outputs)
GND
Input
1
Ground
VSSQ
Input
4
Ground (Outputs)
CLK
Input
1
Clock
A14 - Ao
Input
15
Address
ADSP
Input
1
Address Strobe from Processor
ADSC
Input
1
Address Strobe from Cache Controller
WH
Input
1
Write Enable - High Byte
WL
Input
1
Write Enable - Low Byte
ADV
Input
1
Advance
Output Enable
OE
Input
1
CS
Input
1
Chip Select
DQlS-DQo
Input/Output
16
Regular Data
DPI-DPO
Input/Output
2
Parity Data
Pin Descriptions
Signal
Name
I/O
Input Signals
WH
CLK
Clock signal. It is used to capture the address, the
data to be written, and the following control sig·
nals: ADSP, ADSC, CS, WH, WL, and ADY. It is
also used to advance the on-chip auto-address-increment logic (when the appropriate control signals have been set).
A 14-AO
Fifteen address lines used to select one of 32K
locations. They are captured in an on-chip register
on the rising edge of CLK if ADSP or ADSC is
LOW. The rising edge of the clock also loads the
lower two address lines, Al - Ao, into the on-chip
auto-address-increment logic if ADSP or ADSC is
LOW.
ADSP
ADSC
Signal
Name
Description
I/O
Description
Write signal for the high-order half of the RAM
array. This signal is sampled by the rising edge of
CLK. If WH is sampled as LOW, i.e., asserted, the
control logic will perform a self-timed write of
DQI5 - DQ8 and DPI from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WH, is ignored. Note that ADSP has no
effect on WH if CS is HIGH.
Write signal for the low-order half of the RAM
array. This signal is sampled by the rising edge of
CLK. If WL is sampled as LOW, i.e., asserted, the
control logic will perform a self-timed write of
DQ7 - DQo and DPo from the on-chip data register
into the selected RAM location. There is one exception to this. If ADSP , WL, and CS are asserted
(LOW) at the rising edge of CLK, the write signal,
WL, is ignored. Note that ADSP has no effect of
WL if CS is HIGH.
Address strobe from processor. This signal is
sampled at the rising edge of CLK. When this input
and/or ADSC is asserted, Ao-AI4 will be captured
in the on-chip address register. It also allows the
lower two address bits to be loaded into the onchip auto-address-increment logic. If both ADSP
and ADSC are asserted at the rising edge of CLK,
only ADSP will be recognized. The ADSP input
should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH.
Advance. This signal is sampled by the rising edge
of CLK. When it is asserted, it automatically increments the 2-bit on-chip auto-address-increment
counter. In the CY7C179, the address will be in·
cremented linearly. In the CY7C178, the address
will be incremented according to the Pentium/486
burst sequence. This signal is ignored if ADSP or
ADSC is asserted concurrently with CS .. Note that
ADSP has no effect on ADV if CS is HIGH.
Address strobe from cache controller. This signal is
sampled at the rising edge of CLK. When this input
and/or ADSP is asserted, Ao-AI4 will be captured
in the on-chip address register. It also allows the
lower two address bits to be loaded into the onchip auto·address-increment logic. The ADSC input should not be connected to the ADS output of
the processor.
Chip select. This signal is sampled by the rising
edge of eLK. If CS is HIGH and ADSC is LOW,
the SRAM is deselected .. If CS is LOW and ADSC
or ADSP is LOW, a new address is captured by the
address register. If CS is HIGH, ADSP is ignored.
2-238
·
::~
_·=CYPRESS
~;F
CY7C178
CY7C179
PRELIMINARY
SEMUCONDUCTOR
Pin Descriptions (continued)
Signal
Name
I/O
Signal
Name
Description
Output enable. This signal is an asynchronous input that controls the direction of the data I/O pins.
If DE is asserted (LOW), the data pins are outputs,
and the SRAM can be read (as long as CS was asserted when it was sampled at the beginning of the
cycle). If DE is deasserted (HIGH), the data I/O
pins will be three-stated, functioning as inputs, and
the SRAM can be written.
DE
I/O
Description
I/O
Two bidirectional data I/O lines. These operate in
exactly the same manner as DQJ5 - DQo, but are
named differently because their primary purpose is
to store parity bits, while the DQs' primary purpose is to store ordinary data bits. DP1 is an input
to and an output from the high-order half of the
RAM array, while DPo is an input to and an output
from the lower-order half of the RAM array.
Bidirectional Signals
DQJs-DQo
I/O
Sixteen bidirectional data I/O lines. DQJS - DQs
are inputs to and outputs from the high-order half
of the RAM array, while DQ7 - DQo are inputs to
and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK.
As outputs, they carry the data read from the selected location in the RAM array. The direction of
the data pins is controlled by DE: when DE is high,
the data pins are three-stated and can be used as
inputs; when DE is low, the data pins are driven by
the output buffers and are outputs. DQJS - DQs
and DQ7 - DQo are also three-stated when WH
and WL, respectively, is sampled LOW at clock
rise.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65 ° C to + 150° C
Ambient Temperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage on Vee Relative to GND ... - O.5V to + 7.0V
DC Voltage Ap8lied to Outputs
in High Z State 2] .................. - 0.5V to Vee + 0.5V
DC Input Voltagel 2] .•.. . . . . . . . . . . .. - O.5V to Vee + O.5V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage. . . . . . . .. . . . . . . . .. . . . . .. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Ambient
Temperatnre[3]
Vee
VeeQ
Com'l
O°C to +70°C
5V ±5%
3.0V - 5.5V
- 55°C to +125°C
5V±5%
5V±5%
Mil
Electrical Characteristics Over the Operating Rangel 4]
7C178-8
7C179-8
Min.
Max.
Description
Test Conditions
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Vce = Min., IOH= -4.0 rnA
VIL
Ix
Input LOW Voltagel 2]
Input Load Current
Output Leakage
Current
Parameter
Ioz
2.4
Vee = Min, IOL=8.0 rnA
2.2
-0.3
GND:::;;VI:::;;Vee
GND:::;; VI:::;; Vee,
Output Disabled
Notes:
2. Minimum voltage equals - 2.0V for pulse durations ofless than 20 ns.
3. TA is the "instant on" case temperature.
4.
2-239
VeCQ
0.4
7C178-10
7C179-10
Min.
Max.
2.4
2.2
Vee
+O.3V
-0.3
0.8
-1
1
-1
-5
5
-5
VeeQ
0.4
7C178-12
7C179-12
Min.
Max.
2.4
2.2
Vee
+O.3V
-0.3
0.8
-1
1
5
-5
VeeQ
0.4
Vee
+O.3V
0.8
1
5
See the last page for Group A subgroup testing information.
Unit
V
V
V
V
fAA
fAA
II
CY7C178
CY7C179
~
.
;~PRESS
~,
PRELIMINARY
SEMICONDUCTOR
Electrical Characteristics (continued)
Parameter
Description
Test Conditions
los
Output Short Circuit
Current [5]
Vee=Max., VouT=GND
Icc
Vee Operating Supply
Current
Vee = Max.,
lout = OrnA,
f=fMAX =l/tRe
ISBl
ISB2
7C178-8
7C179-8
Min.
Max.
7C178-10
7C179-10
Min.
Max.
7C178-12
7C179-12
Min.
Max.
Unit
-300
-300
-300
rnA
295
265
215
rnA
Com'l
Mil
250
"i
Automatic CE PowerDown Current-TIL
Inputs
Max. Vee, CS ~
VIH, VIN ~ VIH or
VINSVIL,
f=fMAX
Com'l
Automatic CE PowerDown CurrentCMOS Inputs
Max. Vee, CS ~
Yee - O.3Y, YIN ~
Vee -O.3V or VIN
S 0.3v, f=0[6]
Com'l
60
50
40
Mil
,:
20
rnA
50
20
20
rnA
20
Mil
"
Shaded areas contain advanced information
Capacitance [7]
Parameter
Description
Test Conditions
Input Capacitance
CIN: Addresses
TA = 25°C, f = 1 MHz,
Vee = 5.0V
CIN: Other Inputs
Output Capacltance
COUT
Max.
Com'l
Mil
Com'l
Mil
Com'l
Mil
4
6
6
Unit
pF
,:'
pF
8
6
i8
pF
;
Shaded areas contam advanced mformatlOn
Notes:
5. Not more than one output should be shortened at one time. Duration
of the short circuit should not exceed 30 seconds.
6. Clock signal allowed to run at speed.
7.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
OUTP~~31
85
PFI
5V31R1481Q
ALL INPUT PULSES
3.0V ----...u~----:!L
OUTPUT
5 pF
R2
255Q
R2
255Q
I _
INCLUDING _
_
INCLUDING
JIG AND JIG AND SCOPE
(a)
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
-
178-4
(b)
178-5
167Q
OUTPUT
00--.1--"1. ----00
85pF
\1\0
..
GND
1.73V
I
2-240
...........
~
'1= CYPRESS
CY7C178
CY7C179
PRELIMINARY
- . I F SEMICONDUCTOR
Switching Characteristics
Over the Operating Ranger 8]
Parameter
tCYC
Description
Clock Cycle Time
tCH
Clock HIGH
7C178-8
7C179-8
Min.
Max.
12.5
5
7C178-10
7C179-10
Min.
Max.
15
6
7C178-12
7C179-12
Min.
Max.
20
Unit
ns
8
ns
tCL
Clock LOW
5
6
8
ns
tAS
Address Set-Up Before CLK Rise
2.5
2.5
3
ns
tAH
Address Hold After CLK Rise
0.5
0.5
1
tCDVl
Data Output Valid After CLK Rise, O-pF Load
8.5
10.5
12.5
ns
tCDV2
Data Output Valid After CLK Rise, 85-pF Load
10
12
14
ns
tDOH
Data Output Hold After CLK Rise
tADS
ADSp, ADSC Set-Up Before CLK Rise
tADSH
ADSp, ADSC Hold After CLK Rise
tWES
WH, WL Set-Up Before CLK Rise
tWEH
ns
3
3
ns
2.5
2.5
3
ns
0.5
0.5
1
ns
2.5
2.5
3
ns
WH, WL Hold After CLK Rise
0.5
0.5
1
ns
tADVS
ADV Set-Up Before CLK Rise
2.5
2.5
3
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
1
ns
3
tDS
Data Input Set-Up Before CLK Rise
2.5
2.5
3
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
1
ns
tcss
Chip Select Set-Up
2.5
2.5
3
ns
tCSH
Chip Select Hold After CLK Rise
0.5
0.5
1
tcsoz
Chip Select Sampled to Output High Z[9]
2
6
2
6
2
7
ns
tEoz
OE HIGH to Output High Z[9]
2
6
2
6
2
7
ns
ns
tEOV
OE LOW to Output Valid
5
5
6
ns
tWEOZ
WH or WLSampled LOW to Output High Z[9, 10]
6
6
7
ns
tWEOV
WH or WL Sampled HIGH to Output Valid[lO]
10
12
14
ns
Notes:
8. Unless otherwise noted, test conditions assume signal transition time
of 3 ns or less, timing reference levels of l.Sv, input pulse levels of 0 to
3.0V, and output loading of the specified IOrJIOH and 8S-pF load capacitance.
9.
tcsoz, tEOZ, and tWEOZ are specified with a load capacitance of S pF
as in part (b) of AC Test Loads. Transition is measured ± SOO m V from
steady state voltage.
10. At any given voltage and temperature, tWEOZ min. is less than tWEOV
min.
2-241
II
~
=;;
;.~
=====-,
PRELIMINARY
~ CYPRF.SS
CY7C178
CY7C179
SEMICONDUCTOR
Switching Waveforms
Single Read[ll]
elK
ADDRESS
ADSP or
ADSC[12]
WH,WU 13]
DATA OUT
178-7
Single Write Timing: Write Initiated by ADSP
Notes:
11. OE is LOW throughout this operation.
12. If ADSP is asserted while CS is HIGH, ADSP will be ignored.
13. ADSP has no effect on ADV, WH, and WL if CS is HIGH.
2-242
·
--==-
.~
_'lE
JF
PRELIMINARY
CYPRESS
CY7C178
CY7C179
SEMICONDUCTOR
Switching Waveforms (continued)
Single Write Timing: Write Initiated by ADSC
II
ClK
ADDRESS .............~..-;~~..-;v
WH,Wl
DATA IN
DATA OUT
Burst Read Sequence with Four Accesses
ClK
ADDRESS
ADSP[12] or
ADSC
ADV[13]
WR,W[[13]
DATA OUT
178-9
2-243
&:~PRFSS
PRELIMINARY
~, SEMICONDUCTOR
CY7C178
CY7C179
Switching Waveforms (continued)
Output (Controlled by OE)
F~oz ~
DATAO:><
_X_X_X_X___
:f_____
t_tEO_V
178-10
Write Burst Timing: Write Initiated by ADSC
elK
WH, WU 13j
OE ~------r---------------~----------------~----------------r------
2-244
.
.~PRF.SS
PRELIMINARY
CY7C178
CY7C179
- , SEMICONDUCTOR
Switching Waveforms (continued)
•
Write Burst Timing: Write Initiated by ADSP
elK
WH, WLl13]
ADSP[12]
ADDR
ADV[13]
DATA
178-12
2-245
.~
·
--=-JF
CY7C178
CY7C179
PRELIMINARY
~jg CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Output Timing (Controlled by CS)
178-13
Output Timing (Controlled by WH/ WLr:o~_ _ __
ClK
ADSC and
ADSP
WH,Wl
DATA OUT
178-14
Truth Table
Input
Operation
CS
ADSP
ADSC
ADV
WHorWL
CLK
H
L
H
H
H
L-+H
Same address as
previous cycle
ADSP ignored, read cycle
H
L
H
L
H
L-+H
Incremented burst
address
ADSP ignored, read cycle in burst
sequence
H
L
H
H
L
L-+H
Same address as
previous cycle
ADSP ignored, write cycle
H
L
H
L
L
L-+H
Incremented burst
address
ADSP ignored, write cycle in burst
sequence
H
X
L
X
X
L-+H
N/A
Chip deselected
L
L
X
X
X
L-+H
External
Read cycle, begin burst
L
H
L
X
H
L-+H
External
Read cycle, begin burst
L
H
L
X
L
L-+H
External
Write cycle, begin burst
X
H
H
L
L
L-+H
Incremented burst
address
Write cycle, in burst sequence
X
H
H
L
H
L-+H
Incremented burst
address
Read cycle, in burst sequence
X
H
H
H
L
L-+H
Same address as
previous cycle
Write cycle
X
H
H
H
H
L-+H
Same address as
previous cycle
Read cycle
2-246
Address
'~PRESS
--=-_'
.
PRELIMINARY
SEMICONDUcrOR
Ordering Information
Speed
(ns)
8
10
12
Speed
(ns)
8
10
12
CY7C178
CY7C179
Package
Name
Package 'IYpe
Operating
Range
CY7C178-8JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C178-8NC
TBD
CY7C178-lOJC
J69
CY7C178-lONC
TBD
Ordering Code
52-Lead Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
CY7C178-12JC
J69
CY7C178-10NC
TBD
52-Lead Plastic Quad Flatpack
CY7C178-12YMB·
Y59
52-Pin Ceramic Leaded Chip Carrier
Package
Name
Package 'IYpe
Operating
Range
CY7C179-8JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C179-8NC
TBD
Ordering Code
CY7C179-10JC
J69
CY7C179-lONC
TBD
Military
52-Lead Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
Commercial
52-Lead Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
CY7C179 -12JC
J69
CY7C179-12NC
TBD
52-Lead Plastic Quad Flatpack
CY7C179~ 12YMB
Y59
52-Pin Ceramic Leaqed Chip Carrier
Shaded areas contain advanced information.
Document #: 38-00243
2-247
o
:IE
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[2]
Vee
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
Military
Electrical Characteristics Over the Operating Range
7B180-10
7B181-10
Parameter
VOH
Description
Min.
Test Conditions
Output HIGH Volt- Vee = Min., IOH = - 2.0 rnA
age
VOL
Output LOW Voltage Vee = Min., IOL = 4.0 rnA
VIH
Input HIGH Voltage
Max.
2.4
7BI80-12
7B181-12
Min.
Max.
2.4
Min.
Max.
2.4
0.4
0.4
2.2
7BI80-15, 20
7BI81-15, 20
2.2
Unit
V
0.4
2.2
V
V
VIL
Input LOW Voltage[1]
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
IIX
Input Load Current
GND.::;, VI'::;' Vee
-10
+10
-10
+10
-10
+10
[tA
IOH
Output HIGH
Current
Vee = Min., VOH = 2.4V
-2.0
IOL
Output LOW Current Vee = Max., VOL = O.4V
4.0
loz
Output Leakage
Current
GND .::;, VI'::;' Vee, Output Disabled
-10
los
Output Short Circuit
Current[3]
Vee = Max, VOUT = GND
Icc
Com'l
Vee Operating Supply Vee = Max.,
Currentl 4]
lOUT MATCH= 0 rnA,
OE HIGH, f = fMAX = l/teye Mil
-2.0
-2.0
4.0
+10
-10
rnA
4.0
+10
-10
rnA
+10
[tA
-300
-300
-300
rnA
340
325
315
rnA
390
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 4.5V
Notes:
1. VIL (min.) = - 1.5V for pulse durations of less than 20 ns.
2. Commercial grade is specified as ambient temperature with transverse
air flow greater than 500 linear feet per minute. Military grade is specified as case temperature.
3. Not more than one output should be shorted at a time. Duration of the
short circuit should not exceed 30 seconds.
4.
5.
2-255
Max.
Unit
6.5
pF
10
pF
Assumes 67% read cycles and 33% write cycles (50% cache hit rate).
Tested initially and after any design or process changes that may affect
these parameters.
•
CY7B180
CY7B181
~
~~
~=CYPRESS
~, SEMICONDUCTOR
AC Test Loads and Waveforms
5V~R1962Q
333Q
OUTPUT()oO--....
I~·""·v- VX
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
510Q
I _
-
-
7B180-8
I
GND
INCLUDING
JIG AND
SCOPE
7B180-9
7B180-10
(b) Three-State Delay Load
(a)
Equivalent to:
5pF
ALL INPUT PULSES
3.0V -----1o~~----s..
THEVENIN EQUIVALENT
333Q
OUTPUT 0 0 - - - _
.....,.,.·- - - 0 0 1. 73V
Switching Characteristics Over the Operating Rangel 6]
7B180-12
7B181-12
7B180-10
7B181-10
Parameter
Description
Min.· Max.
Min.
Max.
7B180-15
7B181-15
Min.
Max.
7B180-20
7B181-20
Min.
Max.
Unit
tCYC
Clock Cycle Time
15
20
24
33
ns
tCH
Clock HIGH
7
8
10
13
ns
tCL
Clock LOW
7
8
10
13
tOEOZ
OE HIGH to Output High Z[7]
6
7
9
12
ns
tOEOV
OE LOW to Output Valid[8]
8
9
11
13
ns
20
ns
ns
CLOCK MODE (RE = Rising Edge, FE = Falling Edge) .
tMCH
Match Valid After CLK RE
tMHLO
Match Hold After CLK RE
tcso
Status Valid After CLK RE
tSHLO
Status Hold After CLK RE
tTWRWO
Write Output Valid After TWR LOW
·8
9
11
13
ns
two
Write Output Valid After CLK RE
'1'0
12
15
20
ns
tWOHLO
Write Match Hold After CLK RE
tAD
Access Delay from CLK RE
tOOH
Output Data Hold After CLK RE
tOIS
Input Data Set-Up Before CLK FE
2
l·.,
10
12
.'
>.c, .'
2
Input Data Hold After CLK FE
2
tTSS
TS Set-Up Before CLK RE
3
tTSH
TS Hold After CLK RE
I:
3
;:':>;;;;','
..
,
1
2
15
2
2
·1~~;I~.
3 ;.i
A 'H'I'>~
tOIH
2
12
...
2
15
12
10
:4
2
2
ns
ns
2
18
15
ns
20
ns
25
ns
3
3
3
ns
4
5
6
ns
2
3
4
ns
3
4
5
ns
3
4
5
ns
ns
tAS
Address Set-Up Before CLK RE
3
3
4
5
tAR
Address Hold After CLK RE
3
3
4
5
ns
tcos
Compare Data Set-Up Before CLK RE
3
3
4
5
ns
tCOH
Compare Data Hold After CLK RE
3
3
4
5
ns
tcss
Chip Select Set-Up Before CLK RE
.•. . 3
3
3
4
5
ns
3
4
5
TIS
I trcu
~uu
Chin Select Hold After CLK RE
Shaded area contains preliminary information.
2-256
CY7B180
CY7B181
Switching Characteristics Over the Operating Rangd 6] (continued)
Parameter
Description
7B180-10
7B181-10
Min. Max.
7B180-12
7B181-12
Min. Max.
7B180-15
7B181-15
Min. Max.
7B180-20
7B181-20
Min.
Max.
Unit
13
ns
tCSHZ
Output High Z After CLK RE
(chip deselected via CS inputs)[7, 9]
tCSLZ
Output Low Z After CLK RE
(chip deselected via CS inputs)[8, 9]
2
2
2
2
ns
tWRS
WR Set-Up Before CLK FE
3
3
4
5
ns
tWRH
WR Hold After CLK FE
3
3
4
5
ns
tINVSl
INVAL Set-Up Before CLK RE
3
3
4
5
ns
tINVHl
INVAL Hold After CLK RE
3
tMCHLl
MATCH LOW After CLK RE
Due to INVAL LOW
7
9
11
13
ns
tWOHl
WO HIGH After CLK RE
Due to INVAL LOW
7
9
11
13
ns
tVALLl
VALID LOW After CLK RE
Due to INVAL LOW
7
9
11
13
ns
8
3
"
11
9
5
4
ns
LATCH MODE
tLRLR
LE Rise to Next LE Rise
15
20
24
33
ns
tLW
Width of LE Pulse
5
5
6
8
ns
tLFLR
LE Fall to LE Rise
8
8
10
13
ns
tASLC
Address Set-Up Before Latch Close
3
3
4
5
ns
tAHLC
Address Hold After Latch Close
3
3
4
5
ns
tCSLC
Chip Select Set-Up Before Latch Close
."!
3
4
5
ns
tCHLC
Chip Select Hold After Latch Close
3
I"
3
4
5
ns
tTSLC
Tag Select Set-Up Before Latch Close
3
3
4
5
ns
tTHLC
Tag Select Hold After Latch Close
3
3
4
5
ns
tWSLC
Write Set-Up Before Latch Close
3
3
4
5
ns
tWHLC
Write Hold After Latch Close
3
3
4
5
ns
tCDSLC
Comp Data Set-Up Before Latch Close
31
3
4
5
ns
tCDHLC
Comp Data Hold After Latch Close
'3'·
3
4
5
ns
tDSLC
Data In Set-Up Before Latch Close
4
4
5
6
ns
tDHLC
Data In Hold After Latch Close
2
2
3
4
tCDMCH
Comp Data Valid to Match Valid
10
12
15
20
ns
tTSMCH
Tag Select Valid to Match Valid
10
12
15
20
ns
tCSMCH
Chip Select Valid to Match Valid
10
12
15
20
ns
tAMCH
Address Valid to Match Valid
10
12
15
20
ns
tLOMCH
Latch Open to Match Valid
10
12
15
20
ns
tLOMX
Latch Open to Match Change
tTSSV
Tag Select Valid to Status Valid
tcssv
tASV
'"
::t
:,.
,
:2
2
2
ns
2
ns
,to
12
15
20
ns
Chip Select Valid to Status Valid
10
12
15
20
ns
Address Valid to Status Valid
10
12
15
20
ns
Shaded area contains preliminary information.
2-257
•
CY7B180
CY7B181
~
~~PRESS
~_, SEMICONDUcrOR
Switching Characteristics Over the Operating Rangef6) (continued)
7B180'-:-lO
7B180-12
7B181-12
7B181-:;,!O
Parameter
Description
tLOSV
Latch Open to Status Valid
tLOSX
Latch Open to Status Change
tTWRWO
TWR VALID to WO Valid
tCDWO
Comp Data Valid to WO Valid
tTSWO
tcswo
1\fin. M.~~
Min.
10
Max.
7B180-15
7B181-15
Min.
12
2' ,
2
Max.
7B180-20
7B181-20
Min.
15
Max.
Units
20
ns
2
2
ns
~
9
11
13
ns
10
12
15
20
ns
Tag Select Valid.to WO Valid
1(;)
12
15
20
ns
Chip Select Valid to WO Valid
HI
12
15
20
ns
tAWO
Address Valid to WO Valid
10
12
15
20
ns
tLOWO
Latch Open to WO Valid
10
12
15
20
ns
tLOWOX
Latch Open to WO Change
tCSDV
Chip Select Valid to Data Out Valid
13
15
18
25
ns
tADV
Address Valid to Data Out Valid
13
15
18
25
ns
tLODV
Latch Open to Data Out Valid
25
ns
tLODX
Latch Open to Data Out Change
tTSLMH
Tag Select LOW to Match HIGH
8
9
11
13
ns
tTSLWOH
Tag Select LOW to WO HIGH
8
9
11
13
ns
tCSHZ
Output High Z After the Tag is
Deselected via Chip Select Inputs[7, 9)
8
9
11
13
ns
tCSLZ
Output Low Z After the Tag is Selected
via Chip Select Inputs[8, 9)
2
tINVS2
INVAL Set-Up Before LE RE
3
tINVH2
INVAL Hold After LE RE
3
tMCHL2
MATCH LOW After LE RE
Due to INVALLOW
1;
8
10
13
ns
tWOH2
WO HIGH After LE RE
Due to INVAL LOW
7
8
10
13
ns
tVALL2
VALID LOW After LE RE
Due to INVAL LOW
7 ....
8
10
13
ns
2
2
13
2
-«
15
18
ns
~,""
2
2
,
;'.
N
2
2
~0.
ns
2
2
2
ns
3
4
5
ns
4
3
L..
2
5
ns
'c
Shaded area contains preliminary information.
Notes:
6. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V and output loading ofthe specified IOrJIOH and
35-pF load capacitance, as in part (a) of AC Test Loads and Waveforms, unless otherwise specified.
7. tOEDZ and tCSHZ are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured at ±500 mV from
steady-state voltage. This parameter is sampled and not 100% tested.
8.
9.
2-258
tOEDV and tCSLZ are tested using part (a) of AC Test Loads and Waveforms. This parameter is sampled and not 100% tested.
At any voltage and temperature combination, tCSHZ max. is guaranteed to be smaller than tCSLZ min. for a given device.
CY7B180
CY7B181
~
.
!?~pRF.SS
-====,
SEMICONDUcrOR
Switching Waveforms
•
Tag Match Timing in Clock Mode (Showing a Hit)
~----------- tCYC ----------~
tCH
-------11014-----
tCl
ClK
CSo, CS1
CS 2, cS 3
CD15 - CDo
MATCH
So, S1 (7B 180)
V, D (7B181)
7B180-11
2-259
CY7B180
CY7B181
~
f~PRESS
-=-,
.
SEMICONDUCTOR
Switching Waveforms (continued)
Tag Read Timing in Clock Mode
1+----------- tCYC -------------.1
tWRS ----l. .-
tWRH
D15 - Do
So, S1 (7B180)
V, D (7B181)
MATCH
7B180·12
2-260
CY7B180
CY7B181
~
·
_.1=
CYPRESS
- . ' SEMICONDUCTOR
Switching Waveforms (continued)
•
Tag Write Timing in Clock Mode
~--------------------
tCYC
--------------------~
ClK
D15
-
Do
8 0 ,8 1 (7B180)
V, D (7B181)
MATCH
DE
////7
76180·13
2-261
.
CY7B180
CY7B181
i~PRESS
-==-:t::'_,
SEMICONDUCTOR
Switching Waveforms (continued)
Output Enable Timing
~~J
WO,
015 - Do
So, Sl (78180)
V, D (78181)
)>--------
~-~
---------L '
76180-14
Chip Select Timing in Clock Mode
CLK
Chip Selects
Selecting
78180/78181
WO,
015 - Do
MATCH
So, Sl (78180)
V, 0 (78181)
Chip Deselect Timing in Clock Mode
CLK
Chip Selects
Deselecting
78180/78181
WO,
0 15 - Do
MATCH
So, Sl (78180)
V, D (78181)
tCSHZ
::::::j
_____-J»----------------------------7-61-80-.1-6---
7B181 Tag Invalidation in Clock Mode
CLK
MATCH
tWOHLO
tOOH
VALID
76180-17
2-262
CY7B180
CY7B181
·:~
7j; CYPRESS
--=-
JF
SEMICONDUCTOR
Switching Waveforms (continued)
•
Tag Match Timing in Latch Mode (Showing a Hit)
tLRLR
tLW
LE
tLFLR
~K.
:;;;V
tASLC
:;;;~
tAHLC -
)rJ<"X'X X'XXXX
XXX ~r
tCSLC
tCHLC -
XXXX K~~
3KXXX KXXXX
tTSLC
tTHLC -
I;~
~"
14----
CD15 - CDo
tCDSLC
tCDHLC
XXX> KJ> ~~K
I
*XX KXXXX
tCDMCH
tTSMCH
tCSMCH
tLOMX
tAMCH
~
tLOMCH
MATCH
XXX) Kj < > (XXX:;~
~,XX
tTSSV
tcssv
tASV
tLOsx
tLOSV
So, S1 (78180)
V, D (78181)
~
XXXj I~ ~~ [X~K
)~XX
J
XX KXXX t><2<:XXXXXXXX>O~
~xx
7B180-18
2-263
s;z
CY7B180
CY7B181
~~PRESS
.
----:::;;;;;;;;, SEMICONDUcrOR
Switching Waveforms (continued)
Tag Read Timing in Latch Mode
-----I~----- tLFLR ------I~
LE
An -
,--------------------
,------------
Ao
tLODX
D15 - Do,
So, 81 (78180)
V, D (78181)
MATCH
7B180-19
2-264
CY7B180
CY7B181
Z ·4
iiE CYPRESS
-::;;;;;;;;;;;EiF SEMICONDUCTOR
Switching Waveforms (continued)
•
Tag Write Timing in Latch Mode
- - - - - 1....- - - - - - - tLFLR --------I~
LE
D15 - Do
So, S1 (78180)
V, D (78181)
MATCH
~LWOH
-*
xxx~~XXXXXXXX
78180·20
2-265
CY7B180
CY7B181
~
-.
~~pRF.SS
-==r JF
SEMICONDUCTOR
Switching Waveforms (continued)
Chip Select Timing in Latch Mode
LE
Chip Selects
Selecting
78180/78181
00, D15 - Do
MATCH
So, Sl (78180)
V, D (78181)
76180-21
Chip Deselect Timing in Latch Mode
LE
Chip Selects
Deselecting
78180/78181
00, D15 - Do
MATCH
So, Sl (78180)
V, D (78181)
76180-22
7B181 Tag Invalidation in Latch Mode
LE
MATCH
VALID
76180-23
2-266
=t
CY7B180
CY7B181
.~
- j J ! CYPRESS
--:='.'
SEMICONDUCTOR
Ordering Information
Speed
(ns)
10
12
15
20
Speed
(ns)
10
12
15
20
Ordering Code
Package
1Ype
Package 1Ype
Operating
Range
Commercial
CY7BI80-lOJC
J81
68-Lead Plastic Lpaded Chip Carrier
CY7B180-10NC
N80
80-Lead PlaStic Quad Flatpack
CY7B180-12JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B180-12NC
N80
80-Lead Plastic Quad Flatpack
CY7B180-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B180-15NC
N80
80-Lead Plastic Quad Flatpack
CY7BI80-15LMB
L81
68-Square Leadless Chip Carrier
Military
CY7B180- 20LMB
L81
68-Square Leadless Chip Carrier
Military
Ordering Code
> CY7BI81-10JC" .
CY7B181-10NC
Commercial
Commercial
Package 1Ype
Operating
Range
J81
68-Lead,Plastic Leaded C~ip,Carrier
Commercial
N80
80-Lead Plastic Quad Flatpack
Package
1Ype
CY7B181-12JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B181-12NC
N80
80-Lead Plastic Quad Flatpack
Commercial
CY7B181-15JC
J81
68-Lead Plastic Leaded Chip Carrier
CY7B181-15NC
N80
80-Lead Plastic Quad Flatpack
CY7BI81-15LMB
L81
68-Square Leadless Chip Carrier
Military
CY7BI81-20LMB
L81
68-Square Leadless Chip Carrier
Military
Shaded area contains preliminary information.
Document #: 38-00155-D
2-267
Commercial
•
CY7C182
CYPRESS
SEMICONDUCTOR
8K X 9 Static R/W RAM
Features
Functional Description
• High speed
-tAA = 25 ns
• x9 organization is ideal for cache
memory applications
• CMOS for optimum speed/power
• Low active power
-770mW
The CY7C182 is a high-speed CMOS static
RAM organized as 8,192 by 9 bits and it is
manufactured using Cypress's high-performance CMOS technology. Access times as
fast as 25 ns are available with maximum
power consumption of only 770 m W.
The CY7C182, which is oriented toward
cache memory applications, features fully
static operation requiring no external
clocks or timing strobes. The automatic
power-down feature reduces the power
consumption by more than 70% when the
circuit is deselected. Easy memory expansion is2!9vided by an active-LOW chip enable (CE1), an active HIGH chip enable
(CE2) , an active-LOW output enable (OE),
and three-state drivers.
• Low standby power
-195mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Easy memory expansion with CEh
CE2, OE options
An active-LOW write enable signal (WE)
controls the writi!!g/read~peration of the
memory. When CEl and WE inputs are both
LOW, data on the nine data input/output
pins (1/00 through lias) is written into the
memory location addressed by the address
present on the address pins (Ao through
A12). Reading the device is accomplished by
selecting the device and enabling the outputs,
(CEl and OE active LOW and CE2 active
HIGH), while (WE) remains inactive or
HIGH. Under these conditions, the contents
of the location addressed by the information
on address pins is present on the nine data input/output pins.
The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is
HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
DIP/SOJ
Top View
Vee
WE
1/00
6
CE2
Aa
A2
Al
9
CE'1
1/0 1
1/03
A9
Al0
All
A12
1/0 0
1/04
1/0 1
1/0 2
I/Oa
1/02
OE
Ao
I/Os
1/0 7
1/0 6
1/0 5
1/0 4
GND
1/05
C182-2
1/0 6
CE1
~
1/07
.....--2001V
(per MIL-STD-883, Method 3015.2)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature
Range
Commercial
- O.5V to +7.0V
- O.5V to +7.0V
Vee
5V ± 10%
Electrical Characteristics Over the Operating Range
7C182:-20
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
Input HIGH Voltage
Input LOW Voltage l1J
IIX
Input Load Current
loz
los
Min.
= - 4.0 rnA.
Vee Min., IOL = 8.0 rnA
7C182-25, 35, 45
Min.
Max.
Max.
Unit
204
204
Vee Min., IOH
004
2.2
2.2
V
004
V
V
V
-0.5
Vee
0.8
-0.5
Vee
0.8
GND ~ VIN ~ Vee,
GND < VOUT < Vee,
Output Disabled
-10
+10
-10
+10
fAA
Output Leakage Current
Vee = Max., VOUT
-10
Vee = Max., VOUT
+10
-300
-10
Output Short Circuit
Current[2]
+10
-300
f.lA
rnA
Icc
Vee Operating Circuit
Current
Vee Max., Output Current = 0 rnA,
f = Max., VIN = Vee or GND
150
140
rnA
ISBl
Automatic Power-Down
Current - TTL Inputs
35
35
rnA
ISB2
Automatic Power-Down
Current - CMOS Inputs
Max Vee, CE1 L VIH, CE2 ~ VIL,
VIN L VIH or VIN ~ VIL, f = fMAX
Max Vee, CE1 L Vee - 0.3y, CE2 ~ 0.3y,
VIN L Vee - 0.3V or VIN ~ 0.3y, f = 0
'20
20
rnA
= GND
= GND
,',
Shaded area contams advanced mformatlOn.
Capacitance[3]
Parameter
Description
COUT
Output Capacitance
CIN
Input Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (min.) = - 3.0V for pulse durations of less than 20 ns.
2. Duration of the short circuit should not exceed 30 seconds. Not more
than one output should be shorted at one time.
3.
= 1 MHz,
Max.
Unit
10
pF
10
pF
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R14810
R14810
OUTP~~31
OUTPUT
5V31
30 pF
INCLUDING
JIG AND
SCOPE
R2
255Q
I _
-
-
5pF
R2
255Q
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
ALL INPUT PULSES
3.0V - - - -.J..~----_s..
C182-3
(b)
THEVENIN EQUIVALENT
167Q
OUTPUT~
GND
_
-
1.73V
2-269
C182-4
•
~
;~pRF.SS
.
,
CY7C182
SEMICONDUCTOR
Switching Characteristics Over the Operating Range
;,:,,7C182;"'2;Q
Parameter
Description
.~!J,1~
7C182-25
Max;
Min.
Max.
7C182-35
Min.
Max.
7C182-45
Min.
Max.
Unit
READ CYCLE[4]
tRC
Read Cycle Time
tAA
Address to Data Valid
~.""'" '1'1 ~,
20
r----------+-----------------------------tORA
Data Hold from Address Change
~
3
ns
45
35
25
,'ft,
45
35
25
3
3
ns
ns
20 ,:
25
35
45
ns
20
25
35
45
ns
tACEl
CEI Access T i m e " ' ' ' '
tACE2
CE2 Access Time
tLZCEl
CEI LOW to Low Z
5
5
5
ns
tLZCE2
CE2 HIGH to Low Z
5
5
5
ns
tHZCEl
CEI HIGH to High Z[5]
tHZCE2
CE2 LOW to High Z[5]
tpu
CEI LOW to Power-Up
tpD
CEI HIGH to Power-Down
20
20
25
tDOE
OE Access Time
18
20
20
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[5]
\
'0,
15
18
20
25
18
20
25
o
c.
3;~
','
o
3
15
o
3
18
ns
3
ns
ns
ns
25
20
ns
ns
WRITE CYCLE[6]
.-,
,;
25
35
45
ns
o
o
ns
Address Valid to End of Write
30
40
ns
tSD
Data Set-Up Time
20
25
ns
tSCEl
CEI LOW to Write End
30
40
ns
tSCE2
CE2 HIGH to Write End
15;
20
30
40
ns
WE Pulse Width
15'~:
20
25
30
ns
o
o
ns
Data Hold Time
o
o
Write HIGH to Low Z[7]
3
3
ns
twc
Write Cycle Time
tSA
Address Set-Up Time
o
Address Hold from End of Write
Write LOW to High Z[5,7,8]
13
15
ns
20
ns
Shaded area contams advanced mformatlOn.
Notes:
4.
5.
6.
WE is HIGH for read cycle.
tHZCE and tHZWE are specified with CL = 5 pR Transition is measured
± 500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CEl
LOW, CE2 HIGH, and WE LOW. All three signals must be asserted
to initiate a write and any signal can terminate a write by being deas-
7.
8.
2-270
serted. The data input set-up and hold timing should be referenced to
the rising edge of the signal that terminates the write.
At any given temperature and voltage condition, tLZWE is less than
tHZWE for any given device. These parameters are sampled and not
100% tested.
Address valid prior to or coincident with CE transition LOW and CE2
transition HIGH.
==-.-~
--=-_'
_·il
CY7C182
CYPRESS
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[4,9]
~
ADDRESS
tRC
DATA OUT
PREVIOUS DATA VALID
J
II
1
---~tOHA~
X
x)l(================DA=T=A=V=A=L=ID===========
C182-5
Read Cycle No. 2[4, 10]
CE1
tRC
~~
}I{:
J~
~K
tACE1
tACE2
~I{:
~~
tHZOE
tDOE
i+- tHZCE -
-tLZOE-
DATA OUT
HIGH IMPEDANCE
=1
//////
"-'\.'\.'\.'\.I'\.
"'
DATA VALID
~
tLZCE
_tpu
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
-
HIGH
IMPEDAN CE
I--50%
tpD
~
50%
ICC
ISB
C182-6
Write Cycle No.1 (WE Controlled)[6]
~--------------------------twc ----------------------~
ADDRESS
.... 141------
~~~~~
CS1
tSCE1
tSCE2 ---------------------~ "'7""'l,..,.....,...,""""'.,..,~~..,...,,..,.....,...,
...
~------------------- ~w ---------------------~~
1 4 - - - - tSA -------'~
WE
1-11------- tPWE
------------~~~
---------i~
,--------------
1+--1-------- tSD ----------+10_--+1
DATA IN
DATA I/O
----------------------~
~-------------
DATA UNDEFINED
C182·7
Notes:
9. Device is continuously selected. OE, CEl
= VIL. CE2 = VIH.
10. If CEl goes HIGH and CE2 goes LOW simultaneously with WE
HIGH, the output remains in a high-impedance state.
2-271
:~PRESS
·
CY7C182
- , SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled)[6, 10]
~------------------------twc --------------------------~
ADDRESS
CE1-----+------------------~
tSCE1
tSCE2
CE2-----+~-~-----------------------------------'--r_--~W
______________~~--
~-+---------- tSD -----------I~
DATA IN --------------------~
DATA VALID
tHZWE )
-
DATA I/O
.....___________________________________
HIGH IMPEDANCE
K
DATA UNDEFINED
C182-8
Truth Table
CEl
CE2
OE
WE
Data In
Data Out
H
X
X
X
Z
Z
L
H
L
H
Z
Valid
Read
L
H
X
L
Valid
Z
Write
L
H
H
H
Z
Z
Output Disable
X
L
X
X
Z
Z
Deselect
Mode
DeselectlPower-Down
Ordering Information
Speed
(ns)
20
25
35
45
Ordering Code
Package
Name
CY7C182~20VC
P21·
'V21
CY7C182- 25PC
CY7C182-25VC
CY7C182-35PC
CY7C182-35VC
CY7C182-45PC
CY7C182-45VC
P21
V21
P21
V21
P21
V21
" /:C:Y7C182-20PC
Package 'lYpe
28.bead(300. Mil)-'Molded DIP
28-Lead Molded, SOJ" \
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP
28-Lead Molded SO]
28-Lead (300-Mil) Molded DIP
28-Lead Molded SO]
Shaded area contams advanced mformatIOn.
Document #: 38-00110-E
2-272
Operating
Range
Commercial
Commercial
Commercial
Commercial
CY7B185
CYPRESS
SEMICONDUCTOR
8K X 8 Static RAM
An active LOW write enable signal (WE)
Features
Functional Description
• BiCMOS for optimum speed/power
• Ultra high speed
-9ns
• Low active power
-750mW
• Low standby power
-250mW
• TTL-compatible inputs and outputs
• Capable of withstanding greater than
2001V electrostatic discharge
The CY7B185 is a high-performance
BiCMOS static RAM organized as 8K
words by 8 bits. These RAMs are developed by Aspen Semiconductor Corporation, a subsidiary of Cypress Semiconductor. Easy memory expansion i~ovided by
an active LOW chip enable (CEl), an active HIGH chip enab~iCE2)' and active
LOW output enable (OE) and three-state
drivers. Both devices have a power-down
feature (CEl) that reduces the power consumption by 67% when deselected. The
CY7B185 is in the space saving 300-milwide DIP and SOJ package and leadless
chip carrier.
controls the writing/reading o~tion of
the memory. When CEI and WE inputs
are both LOW, data on the eight data input/output pins (1/00 through 1/07) is written into the memory location addressed by
(Ao through A12). Reading the device is
accomplished by selec~ the device and
enabling the outputs, CEI and OE active
LOW, CE2 active HIGH, while WE remains HIGH. Under these conditions, the
contents of the location addressed by the
information on the address pins is present
on the eight data input/output pins.
The input/output pins remain in ahigh-impedance state unless the chip is selected,
o~uts are enabled, and write enable
(WE) is HIGH.
Pin Configurations
Logic Block Diagram
DIP/SOJ
Top View
Vee
WE
CE2
A3
A2
A1
A7
As
1/00
Ag
A10
A11
A12
1/°0
1/°1
1/0 2
GND
1/01
1/02
OE
Ao
CE1
9
15
1/03
1/0 7
1/0 6
1/05
1/0 4
1/0 3
8185-2
LCC
Top View
1/04
~ ..:e.l>81~
1/05
NC
A7
1/06
CE2
A3
A2
A1
As
Ag
A10
An
A12
1/0 0
1/0 1
1/07
8185-1
m:
Ao
C"E1
1/0 7
1/0 6
g~§:~~
8185-3
SIt'
°d
e ec Ion Gme
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current (rnA)
Commercial
Military
Commercial
Military
7B185-9
7B185 10
9
10
145
150
:
50
155
45
6()
Shaded area contains preliminary information.
2-273
,ii,,'"
7B185 12
12
140
150
40
55
7B185-15
15
135
145
40
50
II
~~pRF.SS
·
~,
CY7B185
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended penods may affect
device reliability. For user guidelines, not tested.)
Storage Temperature ................. Ambient Temperature with
Power Applied ...................... Supply Voltage to Ground Potential .......
DC Voltage Applied to Outputs
in High Z State ........................
Input Voltagd l ] .......................
65°C to + 150°C
55 ° C to + 125 ° C
- 0.5V to +7.0V
Output Current into Outputs (Low) ............... 20 rnA
Static Discharge Voltage ....................... > 2001 V
(Per MIL-STD-883 Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
- 0.5V to +7.0V
- 3.0V to +7.0V
Range
Commercial
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Military[2]
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[3]
Parameter
VOH
VOL
VIR
VIL
IIX
loz
lee
Description
Output HIGH Voltage
Parameter
Description
Output HIGH Voltage
VOH
VOL
VIR
VIL
IIX
loz
lee
Output LOW Voltage
Input HIGH Level
Input LOW Voltage llJ
Com'l
Mil
CEl ~ 3Y, IOUT=OrnA,
Other Inputs = < 0.8V or > 3V,
Vee = Max.
I IOH =
I IOH =
- 4.0 rnA
- 2.0 rnA
Vee = Min., IOL = 8.0 rnA
CEl 2 3V, IOUT=OmA,
Other Inputs = < 0.8V or > 3V,
Vee=Max
7B185-10
Max.
Min.
2.4
2.4
0.4
2.2
- 0.5
-10
-10
Vee
0.8
+10
+10
150
0.4
2.2
- 0.5
-10
-10
50
7B185-12
Max.
Com'l
Mil
Vee
0.8
+10
+10
145
Min.
2.4
2.4
flA
rnA
rnA
Vee
0.8
+10
+10
140
Com'l
150
40
Mil
55
45
rnA
60
rnA
7B185-15
Max.
Min.
2.4
2.4
0.4
2.2
- 0.5
-10
-10
0.4
2.2
- 0.5
-10
-10
Unit
V
V
V
V
V
JAA
" 155
Mil
Test Conditions
Vee = Min.
Min.
2.4
2.4
Com'l
Input Load Current
GND~VI~Vee
Output Leakage Current GND ~ VI ~ Vee, Output Disabled
Com'l
Vee Operating
Vee = Max., lOUT = 0 rnA
Supply Current
f = fmax.
Mil
CEl Power-Down
Current
ISB
7B185-9
Max.
Output LOW Voltage
Input HIGH Level
Input LOW Voltagel l J
Input Load Current
GND~ VI~ Vee
Output Leakage Current GND ~ VI ~ Vee, Output Disabled
Com'l
Vee Operating
Vee = Max., lOUT = 0 rnA
Supply Current
f = fmax.
Mil
CEl Power-Down
Current
ISB
Test Conditions
Vee = Min. I IOH = - 4.0 rnA
I IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
0.8
+10
+10
135
145
Unit
V
V
V
V
V
JAA
JAA
rnA
rnA
40
rnA
50
rnA
Shaded area contains preliminary information.
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
1. Vrdmin.) = - 3.0V for pulse width < 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group i~a.· subgroup testing information.
4.
5.
2-274
MaxJ5]
Unit
6
pF
6
pF
Thsted initially and after any design or process changes that may affect
these parameters.
For all packages except CERDIP (D22), which has maximums of C!M
= 9.5 pF, COUT = 9 pR
.~
·
--=-,)1=
CY7B185
CYPRESS
SEMICONDUCTOR
AC Test Loads and Waveforms
R1481Q
5V
OUTPUT
o-----"N""""'
5V
0---..----.
CLI
OUTPUT
ALL INPUT PULSES
0---..----.
5PFI
R2
255Q
INCLUDING
JIG AND _
SCOPE -
Equivalent to:
o-----"N""""'
II
3.0V -----::Jr-----~
R2
255Q
GND
INCLUDING
JIGAND _
SCOPE -
(a)
THEvENIN EQUIVALENT
8185-4
(b)
8185-5
167Q
OUTPUT
o-O----'l.N
.........---oO 1.73V
Switching Characteristics Over the Operating Rangd 3,6j
7B185-9
Parameter
Description
Min.
7B185-10
Max.
Min.
Max.
7B185-12
Min.
Max.
7B185-15
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACEl
CEI LOW to Data Valid
9
10
12
15
ns
tACE2
CE2 HIGH to Data Valid
9
10
12
15
ns
8
ns
9
12
10
9
3
2.5
15
12
10
3
3
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Zl7j
tLZCEl
CEI LOW to Low Zl8j
2
2
2
3
tLZCE2
CE2 HIGH to Low Zl8j
2
2
2
3
tHZCE
CEI HIGH to High Zl7, 8j
CE2 LOW to High Z
4.5
1.5
5
2
4
6
4
6
5
ns
7
6
ns
ns
3
2
5
ns
15
ns
ns
ns
7
ns
WRITE CYCLEl9j
twc
Write Cycle Time
9
10
12
15
tSCEl
CEI LOW to Write End
8
8
8
10
ns
tSCE2
CE2 HIGH to Write End
8
8
8
10
ns
ns
tAW
Address Set-Up to Write End
8
8
8
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
7
8
8
10
ns
tSD
Data Set-Up to Write End
4.5
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
0
tHZWE
WE LOW to High Zl7j
0
tLZWE
WE HIGH to Low Z
2
4
0
2
Notes:
6. Test conditions assume signal transition times of 3 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V and output
loading of the specified IOrJ!OH, and CL = 20 pR
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ± 200 m V from steady-state
voltage. This parameter is guaranteed and not 100% tested.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device. This parameter is guaranteed and not
100% tested.
9.
2-275
5
0
2
6
0
3
ns
7
ns
ns
The internal write time of the memory is defined by the overlap of CEl
LOW, CE2 HIGH, and WE LOW. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. All three signals must be active to initiate a write, and
either signal can terminate a write by going inactive.
=-:
.~
CY7B185
~=CYPRESS
_, SEMICONDUcrOR
Switching Waveforms
Read Cycle No.1 [10,11]
~------------ADDRESS
_ _ _ _ _ _ _ _ _ _J
)
j I(, _________
, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-J
14------- tM
I----
DATA OUT
------------~
tRC
K'
tOHA
~
-----~
DATA VALID
)KXXX) I(
'-------------------------------
PREVIOUS DATA VALID
9185-7
Read Cycle No.2 [10, 11, 12]
CEl
tRC
~~
) It'
~~
---./If.
tACE
)~
~"
I+--
tOOE
DATA OUT
t~E~
I---tHZCE
tLZOE-
HIGH IMPEDANCE
I/////V
"-.'\.'\.'\.'\.I\..
DATA VALID
HIGH
IMPEDAN CE
/
tLZCE
9185-8
Write Cycle No.1 (WE Controlled) [8, 13, 14]
~-------------twc ------------~
ADDRESS
1+----------- tSCEl
CEl
tSCE2 - - - - - - - - - - - -
1+----
WE
1oIt----- tPWE
tSA - - - - . I
~--------------
~-+-----
DATA IN
-----+
----------------------~~~_
------------------------~
tso - - - - -....- - . 1
DATA VALID
tH~E1
DATAI/O
NOTE 15
,---------------
tLZWE
HIGH IMPEDANCE
)
---j
I
(NOTE 15
9185-6
Notes:
10. Device is continuously selected: DE, CEl = VIL. CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is IIIGI! impedance if OE = \llHo
14. When data input is applied to the device I/O, the device output should
be in the high-impedance state.
15. During this period, the I/Os are in the output state and input signals
should not be applied.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-276
· ~~
_'iilCYPRESS
--=-F
CY7B185
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [8,12,14,16]
II
twc
ADDRESS
U)
:!E
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
Fn~~~t~g:t~~fz~ie.~ ~~ ~~~~~~s...........
DC Input Voltagd 2]
Range
Commercial
_ O.5V to +7.0V
••......•.........•• -
Ambient
Temperature
Vee
5V ± 10%
0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C185-15
7Cl85-12
Parameter
Description
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIR
Input HIGH Voltage
2.2
VIL
Input LOW Voltagd2]
-0:5
IIX
Input Load Current
GND~VI~Vee
loz
Output Leakage
Current
GND~ VI~
Vee,
Output Disabled
los
Output Short
Circuit Current[3]
Vee = Max.,
VOUT= GND
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
140
ISBl
Automatic CEI
Power-Down Current
Max. Vee, CEI ~ VIR,
Min. Duty Cycle = 100%
4Q
ISB2
Automatic CEI
Power-Down Current
Max. Vee, CEI ~ Vee - 0.3v,
VIN ~ Vee - O.3V or VIN ~ 0.3V
Icc
2.4
Max.
2.4
~:o·t<
:5:;
Vcc
0.8
+5
:<+5
-5
,:,'"
V
V
-0.5
Vee
0.8
V
-5
+5
-5
+5
f.tA.
f.tA.
-300
rnA
130
rnA
40
rnA
15
rnA
2.2
.
,;;:
;'{,' '7300
,j~
Unit
0.4
0.4
;';
';
Min.
V
,
,,:
Shaded areas contain advanced information.
Notes:
2. Minimum voltage is equal to - 3.0V for pulse durations less than 30 ns.
3.
2-279
" 15
"''''
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
•
.~
·
--=-
D
CY7C185
ijE CYPRESS
JF
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range (continued)
7C185-20
Parameter
Description
Min.
Test Conditions
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIH
VIL
Input HIGH Voltage
Input LOW Voltagel 2]
Ilx
Input Load Current
Ioz
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
Max.
2.4
7C185 - 25, 35
Min.
Max.
2.4
V
0.4
2.2
Unit
2.2
0.4
V
Vee
0.8
-0.5
Vee
0.8
V
-0.5
GNDs VIS Vee
-5
+5
-5
+5
!lA
Output Leakage
Current
GND S VIS Vee.
Output Disabled
-5
+5
-5
+5
IlA
los
Output Short
Circuit Currentl3]
Vee = Max.,
VOUT = GND
-300
-300
rnA
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
110
100
rnA
ISBl
Automatic CEI
Power-Down Current
Max. Vee, CEI L VIH,
Min. Duty Cycle = 100%
20
20
rnA
ISB2
Automatic CEI
Power-Down Current
Max. Vee, CEI L Vee - 0.3V,
VIN L Vee - O.3V or VIN S O.3V
15
15
rnA
V
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
= 25°C, f = 1 MHz,
Vee = 5.0V
TA
Max.
7
7
Unit
pF
pF
Notes:
4. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
R1481Q
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
30 pF
INCLUDING
JIGAND
SCOPE
I=
3.0V ----_u------~
5pF
R2
255Q
INCLUDING
JIGAND
SCOPE
=
(a)
Equivalent to:
I=
(b)
R2
255Q
C185-3
THEVENIN EQUIVALENT
167Q
OUTPUT
()'O--~.·II\v"_---OO
GND
=
1.73V
2-280
C185-4
===:
c~
====ill
=====-..'
CY7C185
CYPRESS
SEMICONDUCTOR
Switching Characteristics Over the Operating RangelS]
7C185-12
Parameter
Description
7C185-15
Max'~1
Min.
Min.
Max.
7C185-20
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from
Address Change
tACEl
eEl LOW to Data Valid
tACEZ
eEz HIGH to Data Valid
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z[6]
tLZCEl
eEl LOW to Low Z[7]
3
tLZCEZ
eEz HIGH to Low Z
3
tHZCE
eEl HIGH to High Z[6, 7]
eEz LOW to High Z
eEl LOW to Power-Up
tpD
eEl HIGH to Power-Down
20
15
12
3
tDOE
tpu
15
12
3
20
5
ns
ns
12
15
20
ns
12
15
20
ns
6
8
9
ns
"
'.
2
ns
3
6
3
7
,<
ns
8
ns
3
5
ns
3
3
ns
6
7
8
ns
:it;'
0
0
0
12
15
i
ns
20
ns
WRITE CYCLE[8]
twc
Write Cycle Time
12
tSCEl
eEl LOW to Write End
8
',i';
tSCEZ
eEz HIGH to Write End
8
:"
tAW
Address Set-Up to
Write End
tRA
Address Hold from
Write End
tSA
Address Set-Up to
Write Start
tpWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
Data Hold from Write End
tHZWE
WE LOW to High Z[6]
tLzWE
WE HIGH to Low Z
I
9
:i:~i;
!
:
ti"o
20
ns
15
ns
12
15
ns
12
15
ns
0
0
ns
0
0
ns
,
i/
0
15
12
8,
12
15
ns
~,:{;~
8
10
ns
.":;'
:
0
"\/
Ji:
tJt·
3
Shaded areas contain advanced information.
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 m V from steady state
voltage.
7.
8.
2-281
0
0
7
3
ns
7
5
ns
ns
At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
The internal write time of the memory is defined by the overlap of CEl
LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
II
$ ;;~PRFSS
~ IF
CY7C185
SEMICONDUCTOR
Switching Characteristics Over the Operating RangelS] (continued)
7C185-25
Parameter
Description
Min.
7C185-35
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
25
ns
tOHA
Data Hold from
Address Change
tACEl
CEI LOW to Data Valid
25
35
ns
tACE2
CE2 HIGH to Data Valid
25
35
ns
tDOE
OE LOW to Data Valid
12
15
ns
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z[6]
tLzCEl
CEI LOW to Low Z[7]
5
5
ns
tLZCE2
CE2 HIGH to Low Z
3
3
ns
tHZCE
CEI HIGH to High Z[6,7]
CE2 LOW to High Z
tpu
CEI LOW to Power-Up
tpD
CEI HIGH to Power-Down
35
25
5
35
5
3
ns
3
10
0
ns
10
10
10
0
20
ns
ns
ns
ns
20
ns
WRITE CYCLE[8]
twc
Write Cycle Time
25
35
ns
tSCEl
CEI LOW to Write End
20
20
ns
tSCE2
CE2 HIGH to Write End
20
20
ns
tAW
Address Set-Up to
Write End
20
25
ns
tHA
Address Hold from
Write End
0
0
ns
tSA
Address Set-Up to
Write Start
0
0
ns
tpWE
WE Pulse Width
15
20
ns
tSD
Data Set-Up to Write End
10
12
ns
tHD
Data Hold from Write End
0
0
tHZWE
WE LOW to High Z[6]
tLZWE
WE HIGH to Low Z
7
5
2-282
ns
8
5
ns
ns
~
............
~
CY7C185
_ ' j ; ; CYPRESS
-IF
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[9, 10]
ADDRESS
€
1
---~toHA~
DATA OUT
*-
tRC
PREVIOUS DATA VALID
II
~XXXX*===============D=A=TA==VA=L=ID===========
C185-5
Read Cycle No. 2[11, 12]
tRC
),
}I{
..J~
~~
tACE
~,
/1{
tDOE
-tLZOEDATA OUT
HIGH IMPEDANCE
tLZCE
I+----tpu
~
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
-
t>ZOE~
-tHzCE
1//////
1'.."",
DATA VALID
HIGH
IMPEDAN CE
/
_tpD
50%
~
50%
ICC
ISB
C185-6
Write Cycle No.1 (WE Controlled)[lO, 12]
~--------------twc---------------~
ADDRESS
~-----------
tSCE1 -------------~ ,.,...,...,....,...,...jh-.,..,...~...,...,....,...,...
~------tSCE2--------------~
~---tSA ---~
/4----tpwE - - - - - - . ,
-------------------~~~
,------------------
~~-----tSD------~~~
DATA IN
----------------------~
DATA-IN VALID
tHZWE
---I
~I
,--------------
tLZWE
--l
I/r-----
..J'Y>-------------<,'-.______
DATA I/O _ _ _ _ _ _ _ _ _D_A_TA_U_ND_E_F_IN_E_D_ _ _ _ _ _
HIGH IMPEDANCE
C185-7
Notes:
9. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
10. Address valid prior to or coincident with CE transition LOW.
11. WE is HIGH for read cycle.
12. DataI/O is High ZifOE = VIH, CEI = VIH, or WE = VIL.
2-283
...0:::::11IIII
~~PRESS
F SEMICONDUCTOR
CY7C185
~
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [10, 12, 13]
~--------------------------twc --------------------------~
ADDRESS
CE1
----~------------------~ ~--------tscE1 --------~~,--------~~---------
____
~--------------------------J
jooI--- tscE2
-----I~ ,,________~~---------
DATA-IN VALID
DATA IN
tHZWE ~
,I
HIGH IMPEDANCE
DATA I/O _ _ _ _ _ _ _ _ _D_A_TA_U_N_DE_F_IN_E_D_ _ _ _ _ _ _....J/~-------.....("
______
C185-8
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1111.2
~
Ice
1.0
0
w 0.8
N
::J
«
::1: 0.6
V
V
./
./
z
~
'~
I-
..5!! 1.0
6
..9 0.8
0
w
::1:
a: 0.4
0
ISB -
0.0
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
Vee = 5.0V
VIN = 5.0V
0.2
ISB
0.0
-55
6.0
100
~
z
~
120
~ 60
a:
«
0.2
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
a:
a:
~ 80
o
N
0.4
g
ffi
~
::J 0.6
a:
0
1.2
tIl
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
25
125
@
40
~
Il.
20
o~
"
0
0.0
1.0
AMBIENT TEMPERATURE (0C)
M
1.4
1.6
J-
1.3
11.4
0
1.2
o
« 140
...............
~ 100
«
~
-...........
0.9
Ci5
4.5
5.0
5.5
SUPPLY VOLTAGE
M
6.0
rl
60
~ 40
z
0.8 I-:::::r""'-------+------------I
Il.
~
o
0.8 ,-'-----'-,-----'-,-----'-,-----',
4.0
G 80
Z
~ 1.0
t---
a:
~
::1:
TA = 25°C
0.6
-55
,
25
2-284
'
125
AMBIENT TEMPERATURE (0C)
3.0
20
n
v
'"
4.0
M
~/
z
~ 1.21----------+--------~~
a:
0 1.0
z
"r-..
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
I-
::J
~
'"
2.0
,g 120
w
N
::J
1.1
«
::1:
Vee = 5.0V
TA = 25°C
OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
SUPPLY VOLTAGE
VS.
~
/
V
0.0
/
Vee = 5.0V
TA = 25°C
J
,
,
,
,
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE
M
.-
,~PRFSS
CY7C185
- , SEMICONDUcrOR
1Ypical DC and AC Characteristics (continued)
lYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1
lYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0 .-------,.----~-,._--r--..,
25
.
25.01-----i1---+--+--....y:'---i
Cl
en
.s
N
::l:
w 2.0
::J
«
a:
w
0
z 1.0
J
0.5
,/
0.0
0.0
1 .0
2.0
-------M
3.0
4.0
Cl
OE
«
a:
5.0 1---+-11---+_
5.0
1000
Input/Output
Mode
X
X
X
X
X
HighZ
DeselectlPower-Down
L
HighZ
Deselect
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
HighZ
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
X4
X5
3
4
A8
A9
AlO
All
Al2
AO
X6
X7
YI
Y4
2
5
6
7
8
Y3
YO
10
A2
Y2
XO
Xl
21
23
24
A3
X2
25
A1
0.50'---_ _-'-_ _ _'---_ _--'
10
20
30
40
CYCLE FREQUENCY (MHz)
X
A6
A7
oz
10.0 1-----i1--7'"--+_
H
AS
w
::2!
Truth Table
CE2 WE
Cl
N
SUPPLY VOLTAGE
CEI
13
Vee = 5.0V
TA = 25°C
Vee = 0.5V
::J
~ 15.0
1.5
::2!
20.0 1------11---+--~-+---l
NORMALIZED Icc vs. CYCLE TIME
1.25
9
2-285
II
~
:~PRFSS
CY7C185
_ , SEMICONDUcrOR
Ordering Information
Speed
(ns)
12
Ordering Code
20
25
35
Package 'tYpe
Operating
Range
P21
28~Lea9(300~M~I)~olded DIP:}
Commercial
CY7,;G185-12PC
>
15
Package
Name
/'
CY1C18S"': l@;Y.C ;t<
V21 . . . . f 'f8~J-eM Mol4~d $01
P21
..•..
A
28-Lead (300-Mil) Molded DIP
...
CY7C185 -15PC
Commercial
CY7C185 -15VC
V21
28-Lead Molded SO]
CY7C185-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C185 - 20VC
V21
28-Lead Molded SO]
CY7C185 - 25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C185-25VC
V21
28-Lead Molded SO]
CY7C185 - 35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C185 - 35VC
V21
28-Lead Molded SO]
Shaded areas con tam advanced mformation.
Document #: 38-00037-1
2-286
"~1'
Commercial
Commercial
Commercial
CY7C185A
CYPRESS
SEMICONDUCTOR
Features
• High speed
- 20ns
• CMOS for optimum speed/power
• Low active power
- 743mW
• Low standby Power
- 220mW
• TTL-compatible inputs and outputs
• Easy mel!!Q!Y expansion with CEh
CE2 and OE features
• Automatic power-down when
deselected
Functional Description
The CY7C185A is a high-performance
8K X 8 Static RAM
CMOS static RAM organized as 8192
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2),
an active LOW output enable (DE), and
three-state drivers. The device has an automaticpower-downfeature (CE1),reducing
the power consumption by over 70% when
deselected. The CY7C185A is in the standard 300-mil-wide DIP package and leadless chip carrier.
Writing to the device is accomplished when
the chip enable one (CE1) and write enable (WE) inputs are both LOW, and the
chip enable two (CE2) input is HIGH.
Data on the eight I/O pins (l/Oo through
Logic Block Diagram
1/07 ) is written into the memory location
specified on the address pins (Ao through
A12).
Reading the device is accomplished by taking ch~nable one (CEl) and output enable (OE) LOW, while taking write enable
(WE) and chip enable two (CE2) HIGH.
Under these conditions, the contents ofthe
memory location specified on the address
pins will appear on the I/O pins.
The I/O pins remain in a high-impedance
state when ~ enable one (CE1) or output enable (OE) is HIGH, or write enable
(WE) or chip enable two (CE2) is Law.
A die coat is used to insure alpha immunity.
Pin Configurations
LCC
DIP
Top View
Top View
Vee
WE
CE2
Aa
A2
A,
1/00
1/01
1/02
1/03
rn:
Aa
A10
A"
A'2
1{00
I/O,
1/02
GND
Ao
9
CE,
1{07
1/0 6
1/05
1{04
I{Oa
.f.r.l~I~
3 2,1,2827
26 CE2
25Aa
6
24 A2
7
23 A,
8
22 OE
9
21 Ao
10
20 CE,
11
19 1/07
12
18 1/06
1314151617
NC 4
A75
As
Ag
A,o
A"
A'2
1/00
I/O,
g~~~g'
C185A-3
C185A-2
1/04
1/05
1/06
eEl
CE2
1/07
rt-I_ _-<1-J
WE
DE
C185A-1
Selection Guide[l]
Maximum Access Time (ns)
Military
Maximum ~rating
Current (rnA
Maximum Standby
Military
Current (rnA)
7C185A-15
15
170
7C185A-20
20
135
7C185A-25
25
125
7C185A-35
35
125
7C185A-45
45
125
40/20
40/20
40/20
30/20
30/20
Shaded area contams advanced mformatIOn.
Note:
1. For commercial specifications, see the CY7C185 datasheet.
2-287
I
-
.
.::~
CY7C185A
~=CYPRESS
_ F SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ....................... - O.5V to +7.0V
DC Voltage ApBlied to Outputs
in High Z State 4] . . . . . . . . . . . . . . . . . . . . . . .
DC Input Voltagd4] ••••.••••••..•••••.••
-
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage... ... . . .. ... . .. . . . ..... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Military[2]
O.5V to +7.0V
O.5V to + 7.0V
Ambient
Temperature
Vee
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangd3]
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
Vee = Min.,
IOH = - 4.0 rnA
7C185A-15
7C185A-20
Min.
Min.
Max.
Max.
2.4
2.4
Unit
V
_n
Vee = Min.,
IOL = 8.0 rnA
VOL
Output LOW Voltage
0.4
V
VIH
Input HIGH Voltage
2.2
VIL
Input LOW Voltagd4]
:"'0.5
Vee
0.8
2.2
Vee
V
-0.5
0.8
IIX
Input Load Current
GND~ VI~
-10
+10
-10
V
+10
!!A
loz
los
Output Leakage Current
GND ~ VI~ Vee, Output Disabled
-10 . +10
-10
Output Short
Circuit Currentl5]
Vee
= Max., VOUT = GND
lee
Vee Operating
Supply Current
Vee
= Max. lOUT = 0 rnA
ISBl
Automatic CEl
Power-Down Current
ISB2
Automatic CEl
Power-Down Current
0.4.
Vee
+10
!!A
-350
-300
rnA
Military
170
135
rnA
Max. Vee, CEl ~ VIH,
Min. Duty Cycle = 100%
Military
40
40
rnA
Max. Vee,
CEl L Vee -O.3V
VINL Vee- O.3V
orVI NL O.3V
Military
20
20
rnA
'.,
Shaded area con tams advanced mformatlOn.
Notes:
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
S.
2-288
V (min~) = - 3.0V for pulse durations less than 30 ns.
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
~
-~
F SEMICONDUCTOR
--=-
mF
CY7C185A
~ilI CYPRESS
Electrical Characteristics Over the Operating Rangel3] (continued)
Parameter
Description
Test Conditions
VOR
Output HIGH Voltage
VOL
Output LOW Voltage
= Min., lOR = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
7C185A-25
7C185A-35,45
Min.
Min.
Max.
2.4
Vee
Unit
Max.
2.4
V
0.4
0.4
V
V
Vm
Input HIGH Voltage
2.2
Vee
2.2
Vee
VIL
Input LOW Voltagel4]
-0.5
0.8
-0.5
0.8
V
IIX
Input Load Current
GND~VI~Vee
-10
+10
-10
+10
itA
-10
+10
-10
Ioz
Output Leakage Current
GND ~ VI~ Vee, Output Disabled
los
Output Short
Circuit Current[5]
Vee
= Max., VOUT = GND
Icc
Vee Operating Supply
Current
Vee
= Max., lOUT = 0 rnA
ISBI
Automatic CEI
Power-Down Current
ISB2
Automatic CEI
Power-Down Current
+10
ItA
-300
-300
rnA
Military
125
125
rnA
Max. Vee, CEl L Vm,
Min. Duty Cycle = 100%
Military
40
30
rnA
Max. Vee
CEI L Vee -O.3V
VINL Vee- O.3V
orVIN L O.3V
Military
20
20
rnA
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA
= 25°C, f = 1 MHz,
= 5.0V
Vee
Max.
Unit
10
pF
10
pF
Note:
6. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1481Q
R1481Q
5V
OUTPUT
0-------,.,.,......,
5V
0------..----.
30 PF
INCLUDING
JIG AND
SCOPE
r=
R2
255Q
5PFr
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ----:...J..!__
OUTPUTo------~-~
R2
255Q
=
0-------,.,.,.....,
=
----:L
GND
=
C185A-4
(b)
THEVENIN EQUIVALENT
167Q
OUTPUT O'O--....JII
...VI
.. _ - - - o O 1.73V
2-289
C185A-5
I
.
..
~~
iilI
CY7C185A
CYPRESS
_ , SEMICONDUCTOR
Switching Characteristics Over the Operating Raogd Z, 7]
7<';185;\-15
Description
Parameter
MaX.'
Min.
7C185A-20
7C185A-25
7C185A-35
7C185A-45
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
15,'
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Chaoge
tACEl
CEI LOW to Data Valid
tACEZ
CEz HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[8]
'"
.. 0
'
,
tLZCEl
CEI LOW to Low Z[9]
tLZCEZ
CEz HIGH to Low Z
3,
tHZCE
CEI HIGH to High Z[8, 9]
CEz LOW to High Z
CEI HIGH to Power-Down
~~
,
25
35
os
45
os
3
3
os
20
25
35
45
os
20
25
35
30
os
10
12
15
20
os
N!',
15
l'
3
3
3
3
os
"
8
3 ;,
CEI LOW to Power-Up
,
45
35
3
3
15
;'"
25
20
3
,
tpD
20
15
,
"
tpu
f
,i,
""",
12
10
8
15
os
5
5
5
5
os
3
3
3
3
os
8
8
15
10
15
os
"
0
0
0
20
15
0
0
20
os
25
20
os
WRITE CYCLE(10]
twc
Write Cycle Time
, 15
20
20
25
40
os
tSCEl
CEI LOW to Write Eod
10
15
20
25
30
os
tSCEZ
CEz HIGH to Write Eod
Ie,
15
20
25
30
os
tAW
Address Set-Up to Write Eod
10
15
20
25
30
os
tRA
Address Hold from Write Eod
0
0
0
0
0
os
tSA
Address Set-Up to Write Start
0
0
0
0
0
os
tPWE
WE Pulse Width
10
15
15
20
20
os
10
10
15
15
os
0
0
0
0
os
3
5
5
5
os
tSD
Data Set-Up to Write Eod
7
tHD
Data Hold from Write Eod
.' O·
tLZWE
WE HIGH to Low Z
tHzWE
WE LOW to High Z[8]
';3
,"
':'
7
7
7
10
15
os
Shaded area contams advanced mformatlOn.
Notes:
7. Test conditions assume signal transition time ofS ns orless, timing reference levels of 1.SV, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrllOH and 30-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with CL = S pF as in part (b)
of AC Test Loads. ltansition is measured ±SOO m V from steady-state
voltage.
9.
At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
10. Device is continuously selected. DE, CE = VIL. CE2 = VIR.
2-290
~
. :~PRESS
~
CY7C185A
S8MITCONDUCTOR
Switching Waveforms
Read Cycle No.1 [9,11]
~----------------------tRC ------------------------~
ADDRESS
)~
_ _ _ _ _ _ _ _ _ _- J
II
)(
' -________________________________________________- '
' -_ _ _ _ _ __ _
~-----------tAA --------~~
I---tOHA~
DATA OUT
)I( XX) ('
PREVIOUS DATA VALID
DATA VALID
'------------------------------------
C185A-6
Read Cycle No.2 [11, 12]
14------------
tACE
-------------.!
HIGH
IMPEDANCE
DATA OUT -_+-----------------""'*~E_++_{
DATA VALID
ICC
VCC
SUPPLY
CURRENT - - - - - - - - - - -
ISS
C185A-7
Write Cycle No.1 (WE Controlled) [13,14]
~--------------------------twc ------------------------~
ADDRESS
14--------------------
14-------
tSCE1
tSCE2
~-----+--------------~~~
-------------------------.!
1 + - - - - tPWE
14-----DATA IN ------+-------------------~
-------l~
,-------------
tSD -----------.lI+---I~
DATA-IN VALID
~-----------------
HIGH IMPEDANCE
DATAI/O
C185A-8
Notes:
11. Address valid prior to or coincident with CE transition LOW
12. WE is HIGH for read cycle.
13. The internal write time ofthe memory is defined by the overlap of CEl
LOW, CE,z HIGH, and WE LOW Both signals must be LOW to initi-
ate a write and either signal can terminate a write by going HIGH. The
data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
14. Data I/O is high impedance if OE = VIH.
2-291
.~
~.CYPRESS
~, SEMICONDUCTOR
CY7C185A
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [13, 14, 15]
~-------------------------twc --------------------------~
ADDRESS
CE1
--~---------- 1011--------- tscE1 -----~
,------+------
__-+____________-/14----- tSCE2
,,-----+-----
tSD
DATA IN
----t-'
------t....'••
><0
DATA-IN VALID
-j .....______
.if'
HIGH IMPEDANCE
DATA I/O - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . . . ( " '_ _ _ __
C185A-9
Note:
15. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
~ 1.2
.13
Icc
1.0
/
Cl
~ 0.8
:J
~ 0.6
V
1.2
V
V
m
.!!.' 1.0
U
.2
Cl
~
0.8
5.0
5.5
a:
a:
::>
80
:J 0.6
VCC = 5.0V
VIN = 5.0V
0.2 I- ISB
0.0
4.5
~ 100
w
ISB - I - - -
4.0
~
()
z
0.2
1
120
I-
N
a:
~ 0.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
a..
::>
o
20
/
V
o
0.0
/
VCC = 5.0V
TA = 25°C
J
1.0
2.0
OUTPUT VOLTAGE (V)
4.0
C185A-10
.;:~
_'=
CYPRFSS
CY7C185A
- , SEMICONDUCTOR
1Ypical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
30.0 .---...--....---r---r--~
2 .5
25.0 I----I--+---I-----I.II~-I
ow 2.0
~ 20.0 I--I---+--~~-I--~
:::i
~
.... 15.01----I--..j..."II'---I---4---I
0
()
.EN
«
1.5
:::i:
NORMALIZED Icc vs. CYCLE TIME
1.25
~
a:
0
z 1.0
0.5
0.0
0.0
1 .0
---
2.0
~
3.0
./
4.0
200
SUPPLY VOLTAGE (V)
400
w
N
:::i
~
~ 0.751----+"7""~-1_-----i
~ 10.01---+---'~+
5.0
-g
Vee = 5.0V
TA = 25°C
Vee = 0.5V
1.00 I - - - - + - - - I _ - - - - j
z
600
800 1000
CAPACITANCE (pF)
0.50 L--_ _....J...._ _ _L..-_ _.....J
10
20
30
40
CYCLE FREQUENCY (MHz)
C185A-11
'fruth Table
CEl CE2 WE
OE
Mode
H
X
X
X
HighZ
DeselectlPower-Down
X
L
X
X
HighZ
Deselect
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
HighZ
Deselect
Input/Output
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
2
AS
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Yl
7
AID
Y4
8
All
Y3
9
A12
YD
10
AD
Y2
21
Al
XO
23
A2
Xl
24
2-293
=C:::Z
==,'il:
CY7C185A
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
15
CY7C185A-15DMB
D22
28-Lead (300-Mil) CerDIP
CY7CI85A':"'15LMB
L54
28-Pin Rectangular LeadlessChip. Carrier
CY7C185A-20DMB
D22
28-Lead (300-¥il) CerDIP
CY7C185A - 20LMB
L54
28-Pin Rectangular Leadless Chip Carrier
cy7C185A-25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C185A - 25LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C185A - 35DMB
D22
28-Lead (300-Mil) CerDIP
CY7C185A-35LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7C185A -45DMB
D22
28-Lead (300-Mil) CerDIP
CY7C185A -45LMB
L54
28-Pin Rectangular Leadless Chip Carrier
20
25
35
45
Operating
Range
Package 'JYpe
:
Military .
Military
Military
Military
Military
Shaded area contams advanced mformatIon,
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
Parameter
Subgroups
READ CYCLE
tRC
1,2,3
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
IIX
1,2,3
tACEl
7,8,9, 10, 11
loz
los
1,2,3
tACE2
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
WRITE CYCLE
1,2,3
twc
7, 8, 9, 10, 11
tSCEl
7,8,9, 10,11
tSCE2
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHO
7, 8, 9, 10, 11
Document #: 38-00114-B
2-294
CY7C187
64Kx 1 Static RAM
Features
Functional Description
• High speed
-15ns
• CMOS for optimum speed/power
• Low active power
- 495mW
• Low standby power
- 220mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
The CY7C187 is a high-performance
CMOS static RAM organized as 65,536
words x 1 bit. Easy memory expansion is
provided by an active LOW chip enable
(CE) and three-state drivers. The
CY7C187 has an automatic power-down
feature, reducing the power consumption
by 56% when deselected.
Reading the device is accomplished by taking the c~enable (CE) Law, while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the data output (~O) pin.
The output pin stays in !!gh-impedance
state when ch~nable (CE) is HIGH or
write enable (WE) is LOW.
The 7C187 utilizes a die coat to insure
alpha immunity.
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both Law. Data on the
input pin (01) is written into the memory
location specified on the address pins (Au
through AlS).
Logic Block Diagram
Pin Configurations
DIP
SOJ
Top View
Top View
Vee
Vee
A15
A15
A14
A14
Al
A2
A3
3
~
A5
NC
6
22
21
20
19
18
A13
A12
A13
A12
NC
All
All
AlO
Ag
As
Al0
A7
Ag
DOUT
As
~
GND
As
DIN
CE
DIN
CE
C187·3
C187-2
Selection Guide[l]
, ;:\7Cl87 -,'1:2
Maximum Access Time (ns)
Maximum Operating Current (rnA)
"',,'
',;\'
Maximum Standby Current (rnA)
7C187-15
7C187-20
7C187-25
7C187-35
'/'
15
20
25
35
\160 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
_ O.5V to + 7.0V
- O.5V to + 7.0V
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C187-1~
Description
Parameter
Test Conditions
VOH
Output HIGH Voltage Vee = Min.,
IOH = - 4.0 rnA
VOL
Output LOW Voltage
MinI" 'Max.
7C187-15
Min.
Max.
Vee = Min.,
IOL = 12.0 rnA
Max.
2.4
2.4
2.4
7C187-20
Min.
0.4
0.4
7C187-25,35
Min.
Max.
2.4
0.4
Unit
V
0.4
V
V
VIH
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
2.2
Vee
VIL
Input LOW Voltagel 2)
- 0.5
0.8
- 0.5
0.8
-3.0
0.8
-3.0
0.8
V
IIX
Input Load Current
GND.s VI.s Vee
-10
+10
-10
+10
-10
+10
-10
+10
/!A
loz
Output Leakage
Current
GND.s Vo.s Vee,
Output Disabled
-10
+10
-10
+10
-10
+10
-10
+10
!!A
los
Output Short
Circuit Currend3)
Vee = Max.,
VOUT = GND
-350
-350
-350
-350
rnA
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = ornA
160
90
80
70
rnA
ISBI
Automatic CE PowerDown Current[4)
Max. Vee, CE L VIH
40
40
40
20
rnA
ISB2
Automatic CE
Power-Down Current
Max. Vee,
CE L Vee - 0.3v,
VIN L Vee - 0.3V
or VIN .s O.3V
20
20
20
20
rnA
Shaded area mdlcates advanced mformatlOn.
Capacitance[S)
Parameters
CIN
COUT
Test Conditions
Description
Input Capacitance
Output Capacitance
TA = 25°C, f
Vee = 5.0V
Notes:
2. VIL (min.) = -3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
4. A pull-up resistor to Vee on the CE input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
5.
= 1 MHz,
Max.
Units
10
pF
10
pF
Thsted initially and after any design or process changes that may affect
these parameters.
~
a·~
.iE CYPRF.SS
~,
CY7C187
SEMICONDUCTOR
AC Test Loads and Waveforms
R1329.o.
(480.o.MIL)
5V
R2
202.0.
(R1 255.0. MIL)
I
INCLUDING
JIGAND SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
....
OUTPUTD---......- - - t
OUTPUTD---......- - - - .
30pF
•
R1329.o.
(480.0. MIL)
5V
=
5 PF
INCLUDING
JIG AND
SCOPE
1=
(b)
3.0V ----.~'""'!"----
R2
202.0.
(R1 255.0. MIL)
GND
=
C187-5
C187-4
THE'vENIN EQUIVALENT
167.0.
..N*
..II----OO 1.73V
OUTPUT O'O---'\
OUTPUT
OO----'\o."".~--OO
Military
1.90V
Commercial
Switching Characteristics Over the Operating Range[6]
7C187-15
1C187-iz
Description
Parameters
Min.
MU.
12,"
r,~,; 'IK!,;
Min.
Max.
7C187-20
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
1\, '1~jj!
"~I
15
3=I,'"
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power Up
:i: (J"
tpD
CE HIGH to Power Down
. . " j,·tJ."t ig,'12.,.
......
"4,<~~
7~, I
3
i,'.-,\i
,t >;
ns
20
5
3
\ }Z'\
·\~3,,:;
20
15
15
ns
20
5
8
8
15
ns
ns
0
0
ns
ns
ns
20
ns
WRITE CYCLE[9]
twc
Write Cycle Time
~~;12~;
tSCE
CE LOW to Write End
\;8,~
tAW
Address Set-up to Write End
tHA
Address Hold from Write End
;
.'c,
15
20
ns
",cf;;:
12
15
ns
12
15
ns
0
0
ns
tSA
Address Set-up to Write Start
'
.~~
j~gr
5J \ ".4 +~,
tJ'i. 1;~.J;t;<.
0
0
ns
tpWE
WE Pulse Width
'8\
12
15
ns
tSD
Data Set-up to Write End
10
ns
Data Hold from Write End
Tl1i Ii}. ';~:
":a; :' I~t:k
10
tHD
0
0
ns
tLzWE
WE HIGH to Low Z[9]
5
5
tHzWE
WE LOW to High Z[9, 10]
"
li~'
f;'~t
>'.
u.
tl;> ",,; """i 6 "
.~
Shaded area mdlcates advanced mformatlOn.
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
8. tHzCE and tHZWE are specified with CL = 5 pF as in part (b) of AC
Test Loads. Transition is measured ±500 mV from steady-state
voltage.
9.
.....•
7
ns
7
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HI GH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
10. WE is HIGH for read cycle.
2-297
~
--~PRESS
~,
CY7C187
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 6] (continued)
7C187-25
Description
Parameters
Min.
Max.
7C187-35
Min.
Max.
Units
READ CYCLE
25
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power Up
tpD
CE HIGH to Power Down
ns
35
25
5
35
ns
35
ns
ns
5
25
5
ns
5
15
10
0
20
20
ns
ns
0
ns
WRITE CYCLE[9]
twc
Write Cycle Time
20
25
ns
tSCE
CE LOW to Write End
20
25
ns
ns
tAW
Address Set-Up to Write End
20
25
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tpWE
WE Pulse Width
15
20
ns
tSD
Data Set-Up to Write End
10
15
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low[9]
5
tHzWE
WE LOW to High Z[9, 10]
ns
5
7
10
ns
Switching Waveforms
Read Cycle No. 1[10, 11]
~--------------------tRC----------------------~
ADDRESS
tOHA
DATA OUT
DATA VALID
PREVIOUS DATA VALID
C187-6
Note:
11. Device is continuously selected, CE = VIL.
2-298
--=-_':rtPRESS
CY7C187
.....-=:
SEMICONDUcrOR
Switching Waveforms
Read Cycle No. 2[10, 12]
I
tRC
~~
/~
tACE
.~
tLZCE
HIGH IMPEDANCE
DATA OUT
--- f-
/////v
SUPPLY
CURRENT
=:I
DATA VALID
'''''''''-'''-
14---
i + - - tpu
Vce
tHZCE
tpD
HIGH
IMPEDAN CE
~
CC
I
50%
ISS
C187-7
Write Cycle No.1 (WE Controlled)[l1]
~-------------------------twc --------------------------~
ADDRESS
~--------
tSCE
-----------.t
~---------------------tAW --------------------~-
_ _ _l::::::::::::::_tS_A_-_-_----------~~-O:-~, I0Il1---- tpWE - - - - - . I
J-'----------
DATA IN
DATA OUT
DATA UNDEFINED
C187-8
Write Cycle No.2 (CE Controlled) [11, 13]
~--------------twc -------------~
ADDRESS
- - -....1------- tSCE
---------'~
----~------------~
,-------~----------
~-------------~W ---------~----
DATA IN
-f
tSD
--------*,,,111-
DATA VALID
\<0
'L"--______
~
DATA OUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _H_I_G_H_IM_PE_D_A_N_C_E_ _ _ _ _ _ __
C187-9
Note:
12. Address valid prior to or coincident with CE transition LOW.
13. IfCE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-299
~~
~.CYPRESS
~, . SEMICONDUCTOR
CY7C187
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLYVOLTAGE
1.4
~
lee
1.0
/
c
~ 0.8
:J
~ 0.6
/"
1.2
V
CD
en 1.2
V
CD
.::: 1.0
8
ow 0.8
II:
II:
::::l
~ 60
0.0
4.0
4.5
5.0
SUPPLY VOLTAGE
M
J
1.3
J1.4
~
1.2
c
W
N
N
..............
~ 1.0
...............
0.9
0.8
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
0.8
"
0.6
-55
6.0
/"
/
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
~
Vee = 5.0V
~ 2.5
J
c
w 20.0
N
:J
0
0
«
::2
II:
z 1.0
z 10.0
SUPPLY VOLTAGE
./
4.0
/
/
o II
0.0
/
4.0
Vee = 5.0V
TA = 25°C
/
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
NORMALIZED Icc vs. CYCLE TIME
~
1.25 r - - - - - - , - - - r - - - - - ,
Vee = 5.0V
TA = 25°C
Vee = 0.5V
1.001-----+---1------::1
N
:J
«
::2
15.0
II:
3.0
20
fa
N
:J
« 1.5
::2
2.0
::::l
125
25.0
1.0
60
~ 40
~
o
25
80
enZ
30.0 r--r--,.--.,.----.-----,
c 2.0
w
l...---' ~
5
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
en
c
0.5
II:
AMBIENT TEMPERATURE (0C)
M
3.0
0.0
0.0
./
z
'"
M
-
//'
~ 100
~ 1.0
----
3.0
120
z
::2
TA = 25°C
2.0
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
- O.5V to +7.0V
Range
Military[3]
- O.5V to +7.0V
-
- 55°C to + 125°C
Vee
5V ± 10%
O.5V to +7.0V
Electrical Characteristics Over the Operating Rangel4]
7C187A-20
7C187.!-15
Parameter
VOH
VOL
VIR
VIL
IIX
loz
los
Icc
ISBl
ISB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW VoltagelLJ
Input Load Current
Output Leakage
Current
Output Short
Circuit Currentf5]
Vee Operating
Supply Current
Automatic CE PowerDown Current[6]
Automatic CE PowerDown Current[6]
t~fitL
Test Conditions
Vee - Min., IOH - - 4.0 rnA
Vee = Min., IOL = 12.0 rnA
2.4
Mil
"i
-J):5
GND~ Vo~
~-JO
-'-10
Vee, Output Disabled
,,if;,
","
Vee
= Max., VOUT = GND
)
Vee
= Max., lOUT = 0 rnA
Mil
,u'
<'i,
Mil
Max. Vee, CE ~ Vee - 0.3V,
VIN ~ Vee - O.3Vor
VIN~O.3V
Mil
fr
t
%!
';'i;,
f~:.,'~
~p.8;;
;-+:10
+rIO"
-35&:
ey"
Max. Vee, CE~ VIR
0.4
:,Vcii
i'i',;
160
: )f
iih
Max.
2.4
Ct",
0.4 ,
-,2.2
GND~VI~Vee
Min.
MllJ.
;,
':'
2.2
- 0.5
-10
-10
Unit
V
V
V
V
IlA
Vee
0.8
+10
+10
!lA
-350
rnA
90
rnA
40
rnA
20
rnA
,~
",
.'C:
:;""
Shaded area contains advanced information.
Notes:
2.
3.
4.
VIL (min.) = -3.0V for pulse durations less than 30 ns.
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing information.
5.
6.
2-303
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
A pull-up resistor to Vee on the CE input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
•
Rf
~~
iE CYPRESS
,
CY7C187A
SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangd 4] (continued)
7C187A-25
Parameter
Description
Test Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage LlJ
Input Load Current
Output Leakage Current
Output Short
Circuit Current[5]
Vee Operating
Supply Current
VOH
VOL
VIH
VIL
IIX
loz
los
Icc
Vee
Vee
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
Min.
2.4
= Max., lOUT = 0 rnA
CE~
ISBI
Automatic CE
Power Down Currentl6]
Max. Vee,
ISB2
Automatic CE
Power Down Currentl6]
Max. Vee, CE ~ Vee - 0.3v,
VIN ~ Vee - O.3Vor
VIH
Min.
Max.
Unit
2.4
-350
-350
V
V
V
V
f,tA
f,tA
rnA
Mil
80
80
rnA
Mil
40
30
rnA
Mil
20
20
rnA
0.4
Mil
GND~ VI~ Vee
GND ~ Vos:..Vee, Output Disabled
Vee = Max., VOUT = GND
Vee
7C187A-35
Max.
0.4
2.2
-3.0
Vee
0.8
-10
-10
+10
+10
2.2
-3.0
-10
-10
Vee
0.8
+10
+10
VIN~0.3V
Capacitance[7]
Parameter
Description
Test Conditions
TA = 25°C, f
Vee = 5.0V
Input Capacitance
Output Capacitance
CIN
COUT
= 1 MHz,
Max.
Unit
10
pF
10
pF
Note:
7. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R148Hl
R1481Sl
5V o - - - - - " N........
5 V o - - - - - " " '........
OUTPUT
0---""",,--,
30 pF
OUTPUT
R2
255Sl
I
INCLUDING
JIGAND SCOPE -
(a)
Equivalent to:
5 PF
INCLUDING
JIGAND
SCOPE
=
ALL INPUT PULSES
0---""",,--,
1=
(b)
R2
255Sl
3.0V ----_lr'"-----~
GND
=
C187A-4
THEvENIN EQUIVALENT
167Sl
OUTPUT 00-----'1."'
....'1.---00 1.73V
2-304
C187A-5
-=-=-
~~
CY7C187A
~= CYPRF.SS
~,
SEMICONDUCTOR
Switching Characteristics Over the Operating Range[4, 8]
7C187A-20
7C187A-15
Parameter
Description
Min.
Min.
Max.
Max.
7C187A-25
Min.
Max.
7C187A-35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from
Address Change
tACE
CE LOW to Data Valid
tLzCE
CE LOW to Low Z[9]
tHZCE
CEHIGHto
High Z[9, 10]
tpu
CE LOW to Power-Up
tpD
CEHIGHto
Power-Down
20
15
~5
3
3
,
8
3
5
8
35
ns
15
ns
ns
5
10
ns
ns
..
0'
0
';;j~;'
35
25
20
5
,';'
ns
35
25
3
3
,;,
; 'r;
1'5.
,;,',
25
20
0
0
20
20
15 '>
ns
20
ns
WRITE CYCLE[ll]
twc
Write Cycle Time
15
tSCE
CE LOW to Write End
10
tAW
Address Set-Up to
Write End
10
tHA
Address Hold from
Write End
0
Address Set-Up to
Write Start
tpWE
WE Pulse Width
tSD
Data Set-Up to
Write End
j
Data Hold from
Write End
;~l:~:
tLZWE
WE HIGH to Low Z[9]
tHZWE
WE LOW to
High Z[9, 10]
;:',
,
'l'
l~;'
"
,I~:
25
ns
15
20
25
ns
15
20
25
ns
0
0
0
ns
0
0
0
ns
15
15
20
ns
t,
10
10
15
ns
0
0
0
ns
,
I;,·~%t\~(;
20
,11;,'"
7
,3';'
20
,Co
'"
tSA
tHD
i'.'
,~
;
:.
5
5
",
7
7'.:A,
Shaded area contams advanced mformatlOn.
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLzCE for any given device.
10. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC
Test Loads. Transition is measured ±500 mV from steady-state
voltage.
ns
5
7
10
ns
11. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
2-305
;1U:cre=
~
CY7C187A
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[12,13]
~---------------------tRC ----------------------~
ADDRESS
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ J ' -_ _ _ _ _ __
)(
) (
_ _ _ _ _ _ _ _ _ _,
~----------tAA --------~
tOHA ~
I-----
DATA OUT
}I( XX) (
PREVIOUS DATA VALID
DATA VALID
'--------------------------------
C187A·6
Read Cycle No. 2[12, 14]
tRC
~~
)~
tACE
tLZCE
DATA OUT
Vec
SUPPLY
CURRENT
HIGH IMPEDANCE
-
1/////1'
HIGH
IMPEDAN CE
DATA VALID
~""",,'\.
I----
tHZCE
~tpD
tpu
___ fso%
~
50%
ICC
ISB
C187A·7
Write Cycle No.1 (WE Controlled)[ll]
~------------------------twc --------------------------~
~----------------tSCE --------------------~
___1'1_"""_-_-_-_-_-_-_-_t_SA_-:.-:.-:.:.:.:.:.~=~~,
,..r-----
tPWE
------~ _ - - - " " ' - - - - - - -
DATA IN
DATA OUT
DATA UNDEFINED
C187A·8
Notes:
12. WE is HIGH for read cycle.
13. Device is continuously selected, CE = VIL.
14. Address valid prior to or coincident with CE transition LOW.
2-306
-----.~
_·lE
CY7C187A
CYPRESS
~iF
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CE Controlled) [11, 15]
~--------------------------twe --------------------------~
I
ADDRESS
----"*'1-------- tseE
----~------------
-----------~
,-------~--------
~----------------~=-=-~~L~~W~:::::::::::::::::l~
................................................._ .............. 1 + - - - - - - - tPWE - - - - - - + 1 """..,..7"'7'~~-.,...,..7"'7'"'7""l,...,..7"'7'
~""I---------------
DATAIN
---------1'
tSD
,I,
tHO
~'""""-
__________
DATA-INVAUD
DATA OUT _____________________________
H_IG_H_I_M_P_E_DA_N_C_E________________________________
C187A-9
Note:
15. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
lee
..B 1.0
V
o
~ 0.8
:J
~ 0.6
c:
V
1.2
/
Cl
en 1.2
V
Cl
en
~
1.0
<3
.2 0.8
0
w
0.0
4.5
5.0
5.5
SUPPLY VOLTAGE
0
z
J.
1.0
w
~
~
0.9
0.8
4.0
IS6
--...t---
25
125
B
5.0
5.5
M
6.0
"
0
0.0
1.0
1.4 t---------+------------l
« 140
.s 120
f-
z
ac:
80
Z
60
~
a..
40
::)
20
~
en
~ 1.0
z
0.8 ~,.c;...------+---------__I
0.6 '::---------..L.-------------'
-55
25
125
AMBIENT TEMPERATURE (0C)
2-307
3.0
f-
"
4.0
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 100
1.2 1---------+--------7""~
2.0
"'~
OUTPUT VOLTAGE
o
4.5
Vee = 5.0V
TA = 25°C
f-
::2:
TA = 25°C
SUPPLY VOLTAGE
40
~ 20
o
N
...............
"- ~
f-
1.6
1.3
c:
55
Vee = 5.0V
VIN = 5.0V
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
0 1.2
w
N
:J
« 1.1
::2:
80
AMBIENT TEMPERATURE (0C)
M
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
J
::)
c:
-55
6.0
100
::)
0.2
IS6 - ~
ifi
c:
c:
~ 60
z
0.0
4.0
~
()
:J 0.6
«
::2:
c: 0.4
0
0.2
g120
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
f-
N
~ 0.4
~
/
of7
0.0
7
-
. . .v
Vee = 5.0V
TA = 25°C
V
/
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
@.:~
•
CY7C187A
'J; CYPRESS
IF
SEMICONDUcrOR
'iYpical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
J
25.0 1---!---4--+--~~__
2.5
(j)
,s 20.0 1---!---4---!P"=~-t--__
Cl
w 2.0
N
::J
«
~
NORMALIZED Icc vs. CYCLE TIME
30.0 .----,---....--~--.----
~
-
1.5
~
a:
z 1.0
0
0.5
0.0
0.0
1.0
2.0
-
~
3.0
SUPPLY VOLTAGE
V
15.0 I---~-~~-+---+----
5.0
200
400
Address Designators
AO
X3
1
A1
X4
2
A2
X5
3
A3
A4
X6
X7
4
5
AS
Y7
6
A6
Y6
7
A7
Y2
8
A8
Y3
Y1
14
15
AlO
YO
16
All
Y4
17
A12
A13
Y5
XO
18
A14
Xl
20
A15
X2
21
A9
Truth Table
CE
WE
600
Pin
Number
19
Input/Output
Mode
H
X
HighZ
L
H
Data Out
Read
L
L
Data In
Write
DeselectlPower-Down
2-308
___
800 1000
CAPACITANCE (pF)
Address
Function
W
~
oz
~_I...-_..L-_..J...._...L..
o
M
Address
Name
Cl
a:
0.0
4.0
~
Vee = 5.0V
TA = 25°C
Vee = 0.5V
N
~ 10.01---~~+
/
1.25
0.501·L::-0---2~0:----3l..0-----40
CYCLE FREQUENCY (MHz)
:~
.
-=-,
-''=
CY7C187A
CYPRFSS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
Ordering Code
15
CY7C187A-15DMB
1
'DIO
35
24-Lead (3001Mtl;)CerDIP
.
22-PinRect(l~~1it: ~adless Cb~p Carrier
Dl0
24-Lead (300-Mil) CerDIP
CY7C187A - 20LMB
L52
22-Pin Rectangular Leadless Chip Carrier
CY7C187A-25DMB
DlO
24-Lead (300-Mil) CerDlP
CY7C187A - 25LMB
L52
22-Pin Rectangular Leadless Chip Carrier
CY7C187A - 35DMB
Dl0
24-Lead (300-Mil) CerDlP
CY7C187A-35LMB
L52
22-Pin Rectangular Leadless Chip Carrier
,0
CY7C187A-20DMB
25
Operating
Range
Package lYpe
1.52
CY7C187A -15LMB
20
Package
Name
Military
Military
Military
Military
Shaded area contams advanced mformatlOn.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Switching Characteristics
Subgroups
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
READ CYCLE
tRC
7,8,9, 10, 11
VIR
1,2,3
tAA
7,8,9, 10, 11
VILMax.
1,2,3
taRA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
WRITE CYCLE
los
1,2,3
twc
Icc
1,2,3
tSCE
7, 8, 9, 10, 11
ISBl
1,2,3
tAW
7, 8, 9, 10, 11
ISB2
1,2,3
tRA
7, 8, 9, 10, 11
tSA
7,8,9,10,11
tpWE
7,8, 9, 10, 11
Document #: 38-00115-C
2-309
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
•
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• High speed
-12ns
• Automatic power. down when
deselected
• Low active power
-965mW
• Low standby power
-220mW
• CMOS for optimum speed/power
• TTL·compatible inputs and outputs
• Easy mem...Q!Y expansion with CEl.
CE2, and OE features
Functional Description
The CY7C188 is a high-performance
CY7C188
32K x 9 Static RAM
CMOS static RAM organized as 32,768
words by 9 bits. Easy memory expansion is
provided by an active-LOW chip enable
(CIh),anactive-HIGHchipenable(CE2),
an active-LOW output enable (OE), and
three-state drivers. The device has an automatic power-down feature that reduces
power consumption by more than 75%
when deselected.
Writing to the device is accomplished by
taking CEI and write enable (WE) inputs
LOW and CE2 input HIGH. Data on the
nine I/O pins (1/0 0 - 1I0g) is then written
into the location specified on the address
pins (Ao - A14).
Logic Block Diagram
Reading from the device is accomplished
and OE LOW while forcing
WE and CE2 HIGH. Under these conditions, the contents of the memory location
specified by the address pins will appear on
the I/O pins.
~aking eEl
The nine input/output pins (1/00 - I/Og)
are placed in a high-impedance state when
the device is deselected (CEI HIGH or
CE2 LOW), the outputs are disabled (@
HIGH), or during a wri~eration (CEI
LOW, CE2 HIGH, and WE LOW).
The CY7C188 is available in standard
300-mil-wide DIPs and SOJs.
A die coat is used to ensure alpha immunity.
Pin Configuration
DIP/SOJ
Top View
Vee
A14
CE2
WE
A13
Ag
Al0
All
1/00
m:
1/01
Al
A12
CE1
I/Oa
1/07
1/0 6
1/05
1/0 4
Ao
1/02
1/0 0
1/01
I/Q2
1/03
GND
1/0 3
1/04
C188-2
1/0 5
1/06
eEl
CE2
1/07
WE
DE
I/Oa
C188-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
I Commercial
I.•. ~qitarf4f
Maximum Standby Current (rnA)
"
7C188-12
7C188-15
7C188-20
12
15
20
25
175
165
155
145
~¥(Ilf
185
40
40
Shaded area contains advanced information.
2-310
....
;;:.,;:.
l.i.lJ1(Y:'
40
7C188-25
,/j
l~~~Jji
35
PRELIMINARY
CY7C188
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature .................. - 65°C to + 150°C
Latch-Up Current ............................ >200 rnA
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Operating Range
Supply Voltage on Vee Relative to GND
(Pin 32 to Pin 16) ....................... - 0.5V to + 7.0V
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
DC Voltage Apglied to Outputs
in High Z State 1] .................. - O.5V to Vee + O.5V
DC Input Voltagd 1] ................ - O.5V to Vee + 0.5V
Military[Z]
II
Output Current into Outputs (LOW) ............... 20 rnA
Electrical Characteristics Over the Operating Rangd3]
7C188-12
Parameter
7C188-15
7C188-20
Max.
Description
Test Conditions
Min.
VOH
Output HIGH
Voltage
Vee = Min., IOH = - 4.0 rnA
2.4
VOL
Output LOW
Voltage
Vee = Min., IOL = 8.0 rnA
VIR
Input HIGH
Voltage
2.2
Vee
+ 0.3
2.2
Vee
+ 0.3
2.2
Vee
+ 0.3
VIL
Input LOW
Voltagd 1]
- 0.3
0.8
- 0.3
0.8
- 0.3
IIX
Input Load
Current
GND~VI~Vee
-1
+1
-1
+1
loz
Output
Leakage
Current
GND~ VI~ Vee,
Output Disabled
-5
+5
-5
+5
los
Output Short
Circuit
Current[4]
Vee = Max., VOUT = GND
lee
Vee Operating Supply
Current
Vee = Max.,
lOUT = 0mA,
f = fMAX = litRe
Automatic CE
Power-Down
Current
-TTL Inputs
Max. Vee, CE1.2=: VIR
orCEz~ VIL,
VIN .2=: VIR or VIN ~
VIL,f= fMAX
Com'l
Max. Vee, CE1 .2=: Vee
-O.3V or CEz ~ 0.3y,
VIN.2=: Vee - O.3V
or VIN ~ 0.3Y, f = 0
Com'l
ISBI
ISBZ
Automatic CE
Power-Down
Current
-CMOS
Inputs
Max.
Min.
Max.
2.4
2.4
0.4
Com'l
CC
Mil
c;c
- 300
175
165
'
};c:"
10
:
V
170
~?,·
25
CY7C188-25PC
CY7C188-25YC
CY7Cl$~(~~5J;l.MB
Package
Name
P31
Y32
P31
Y32
D32
P31
Y32
.D32
P31
Y32
D32
Package 'JYpe
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
32·:eead (lQ'O.;MH) CerDIP
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
32·~ad (4ruk¥i1) CerDll~.i,
Operating
Range
Commercial
Commercial
, '¥\U~ary;.j
,',
Commercial
...Military;.
,~
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
Commercial
34-Lead(300ctviil) CerDIP
Military;"
,
Shaded areas contain advanced informatIOn.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
DC Characteristics
Subgroups
READ CYCLE
Parameter
Subgroups
tRC
YOH
1,2,3
tAA
7, 8, 9, 10, 11
VOL
1,2,3
tOHA
7,8,9,10,11
YIR
1,2,3
tACE
7, 8, 9, 10, 11
YILMax.
1,2,3
tDOE
7,8,9,10,11
IIX
1,2,3
Ioz
1,2,3
twc
Icc
1,2,3
tSCE
7, 8, 9, 10, 11
ISBl
1,2,3
tAw
7,8,9,10,11
ISB2
1,2,3
tHA
7, 8, 9, 10, 11
tSA
7,8,9,10,11
7,8,9,10,11
WRITE CYCLE
7,8,9,10,11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9,10,11
tHD
7, 8, 9, 10, 11
Document #: 38-00220-B
2-316
CY7B191
CY7B192
64K X 4 Static R/W RAM
with Separate I/O
Features
Functional Description
• High speed
- 10 ns tAA
• Automatic power-down when
deselected
• Transparent write (7BI91)
• BiCMOS for optimum speed/power
• Low active power
- 850mW
• Low standby power
- 200mW
• TTL-compatible inputs and outputs
The CY7B191 and CY7B192 are high-performance BiCMOS static RAMs organized
as 64K words by 4 bits with separate I/O.
Easy memory expansion is.E!..0vided by an
active LOW chip enable (CE) and threestate drivers. Both devices have an automatic power-down feature, reducing the
power consumption by more than 60%
when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW Data on the four input
pins (10 through 13) is written into the
memory location specified on the address
pins (Ao through AlS).
Reading the device is accomplished by taking
chip enable (CE) LOW while the write enable (WE) remains HIGH. Under these conditions, the contents of the location specified
on the address pins will appear on the four
data output pins.
The four output pins (00 through 03) are in
a high-impedance state when the device is
deselected (CE HIGH). During a write operation (WE and CE LOW), the outputs of the
7B192 are in a high-impedance state and the
outputs of the 7B191 track the inputs after a
specified delay.
The CY7B191 and CY7B192 are available in
space-saving 300-mil-wide DIPs and SOJs.
Logic Block Diagram
Pin Configuration
DIP/SOJ
Top View
12
As
13
A3
A7
As
As
A10
A11
A12
A13
A14
A15
10
11
00
~
As
As
01
A7
As
O2
As
A.!
Ao
13
12
03
02
01
00
WE
GND
03
Vee
A3
A2
A1
ce-
Ag
A10
28
27
26
8191-2
8191-1
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current (rnA)
Commercial
Military
Commercial
Military
7B191-10
7B192-10
10
170
40
2-317
7B191-12
7B192-12
12
160
170
35
40
7B191-15
7B192-15
15
150
160
30
40
7B191-20
7B192-20
20
160
40
II
CY7B191
CY7B192
=:... . ~
~~ CYPRESS
,
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage on Vee Relative to GND(1] - O.5V to +7.0V
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperatnre
Vee
O°C to +70°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Range
DC Voltage Ap8lied to Outputs
in High Z State 1] . . . . . . . . . . . . . . . . . . . . . . - 0.5V to +7.0V
DC Input Voltagel 1] .................... - 0.5V to +7.0V
Current into Outputs (LOW) ..................... 20 rnA
Commercial
Military[2]
Electrical Characteristics Over the Operating Rangel 3]
.7BI91-10
7B192-10
Parameter
Description
Output HIGH Voltage Vee
Output LOW Voltage Vee
Input HIGH Voltage
Input LOW Voltage[1]
VOH
VOL
VIH
VIL
IIX
loz
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating Supply
Current
los
lee
Automatic CE
Power-Down Current
- CMOS Inputs
ISB
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
2.4
Max.
7B191-12
7B192-12
Min.
0.4
2.2
- 0.3
-10
-10
GND.s VI.s Vee
GND.s VI.s Vee,
OutP1.1t Disabled
= Max., VOUT = GND
Max.
2.4
Vee
0.8
+10
+10
7BI91-15, 20
7BI92-15,20
Min.
0.4
2.2
- 0.3
-10
-10
Max.
2.4
Vee
0.8
+10
+10
0.4
2.2
- 0.3
-10
-10
Unit
V
V
V
V
Vee
0.8
+10
+10
f.tA.
f.tA.
-300
-300
-300
rnA
Com'l
170
40
160
170
35
150
160
30
rnA
Mil
Max. Vee, CE ~ Vee - 0.3v, Com'l
VIN ~ Vee - O.3Vor
Mil
VIN.s 0.3v, f = 0
40
40
Vee
Vee = Max., lOUT
f = fMAX = litRe
= 0 rnA
rnA
Capacitance[S]
Parameter
Description
CIN
Input Capacitance
COU1;CIIO
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (min.) = - 2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
2-318
= 1 MHz,
MaxJ6]
Unit
6
pF
8
pF
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
For PDIP (P21) and CDIP (D22), CIN=COUT=10pR
CY7B191
CY7B192
~ .~PRF.SS
- ; F SEMICONDUCTOR
AC Test Loads and Wavefo~ms
R1481.rr
5Vo----""""""""""'
R1481.rr
5Vo----""""""""""'
OUTPUTo---........- - t
OUTPUTo---........- - t
FI
20 P
R2
255.rr
INCLUDING
JIGAND _
SCOPE -
5PFI
R2
I
GND
255.rr
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ----_.Ir"~----s..
(b)
8191-4
8191-3
THEVENIN EQUIVALENT
167.rr
OUTPUT (),O--...JVyll'l.·_ _--oo 1.73V
Switching Characteristics[3,7] Over the Operating Range
7B191-10
7B192-10
Parameter
Description
Min.
7B191-12
7BI92-12
Max.
Min.
Max.
7B191-15
7B192-15
Min.
Max.
7B191-20
7B191-20
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
15
12
10
12
10
3
3
3
20
ns
20
15
ns
ns
3
20
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[8,9]
6
7
8
10
ns
tpu
CE LOW to Power-Up
0
0
0
0
ns
tpD
CE HIGH to Power-Down
10
12
15
20
ns
12
10
3
3
15
3
ns
ns
3
WRITE CYCLEllUj
twc
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
15
ns
tAW
Address Set-Up to Write End
8
9
10
15
ns
tRA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpwE
WE Pulse Width
8
9
10
15
ns
tSD
Data Set-Up to Write End
6
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLzWE
WE HIGH to Low Z[8]
2
2
2
2
tHZWE
WE LOW to High Z[8,9]
6
7
7
10
ns
ns
tDWE
WE LOW to Data Valid (7B191)
10
12
15
20
ns
tDCE
CE LOW to Data Valid (7B191)
10
12
15
20
ns
tADV
Data Valid to Output Valid (7B191)
10
12
15
20
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IorJIOH and 20-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLZWE.
9. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 mV from
steady state voltage.
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal will terminate a write by going HIGH. The input data setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
2-319
CY7B191
CY7B192
~
~PRFSS
~_" SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[11,12]
~V~: 3ZZ 1
*-
tRC
ADDRESS
--~
DATA OlIT
tAA
PREVIOUS DATA
*================DA=:r=A=V=A=L=ID===========
6191-5
Read Cycle No. 2[12,13]
x
ADDRESS ) (
tRC
~~
)E
tACE
DATA OUT
HIGH IMPEDANCE
tpu
=1
VCC _ _ _ _ _ _ _ _
SUPPLY
CURRENT
-
//////
tHZCE
d
HIGH
IMPEDANC E
DATA VALID
"'~"""'\'\.
tLZCE
14---
-
-tpD
~cc
)0%~IS8
I
50%
6191-6
Write Cycle No.1 (CE Controlled)[14]
~--~-----------------------twc ------------------------------~
ADDRESS
-----------~----- tSCE -----~
~-----------------------~w ~--~-------------.~----- tHA ---~~
WE
____________________________
~~-r-------
DATA IN
DATA OUT
(78192)
tSD
------~~
DATA VALID
HIGH IMPEDANCE
DATA OUT
(78191)
6191-7
Notes:
11. Device is continuously selected. CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. IfCE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-320
-
CY7B191
CY7B192
- ... ~
~ilI
CYPRESS
~, SEMICONDUCIOR
Switching Waveforms
Write Cycle No.2 (WE Controlled)[14]
I
twc
en
::::E
ADDRESS
c:t
a:
(/)
CE
tHA
tAW
WE
DATA IN
DATA OUT
(78192)
DATA OUT
(78191)
tADV
8191-8
Truth Table
CE
WE
H
X
HighZ
Power-Down
Standby (ISB)
L
H
Data Out
Read
Active (Icc)
L
L
HighZ
7B192: Standard Write
Active (Icc)
L
L
Data In
7B191: Transparent Writd 15 ]
Active (Icc)
Power
Mode
00- 03
Notes:
15. Outputs track inputs after specified delay.
Ordering Information
Speed
(os)
10
12
15
20
Ordering Code
CY7B191-10PC
Package
Name
Package 1YPe
Operating
Range
Commercial
P21
28-Lead (300-Mil) Molded DIP
CY7BI91-lOVC
V21
28-Lead Molded SO]
CY7B191-12DC
D22
28-Lead (300-Mil) CerDIP
CY7B191-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B191-12VC
V21
28-Lead Molded SO]
CY7BI91-12DMB
D22
28-Lead (300-Mil) CerDIP
Military
Commercial
CY7B191-15DC
D22
28-Lead (300-Mil) CerDIP
CY7B191-15PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7B191-15VC
V21
28-Lead Molded SO]
CY7BI91-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B191- 20DMB
D22
28-Lead (300-Mil) CerDIP
Military
2-321
CY7B191
CY7B192
#€.;~
~, ~~NDUcrOR
Ordering Information (continued)
Speed
(ns)
10
12
15
20
Ordering Code
Package
Name
Package 'lYPe
Operating
Range
CY7B192-10PC
P21
28-Lead (300-Mil) Molded DIP
CY7BI92-1OVC
V21
28-Lead Molded SOJ
CY7BI92-12DC
D22
28-Lead (300-Mil) CerDIP
CY7B192-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B192-12VC
V21
28-Lead Molded SOJ
CY7BI92-12DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B192-15DC
D22
28-Lead (300-Mil) CerDIP
Commercial
CY7B192-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7B192-15VC
V21
28-Lead Molded SOJ
CY7BI92-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7BI92-20DMB
D22
28-Lead (300-Mil) CerDIP
Military
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIR
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tORA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
loz
1,2,3
Icc
1,2,3
ISBl
1,2,3
twc
7, 8, 9, 10, 11
ISBZ
1,2,3
tSCE
7, 8, 9, 10, 11
Parameter
Subgroups
READ CYCLE
tDOE
WRITE CYCLE
Document #: 38-00156-C
tAW
7, 8, 9, 10, 11
tRA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7,8,9, 10, 11
tHD
tDWE[16]
7, 8, 9, 10, 11
tADV
7, 8, 9, 10, 11
Note:
16. 7B191 only.
2-322
7,8,9, 10, 11
7, 8, 9, 10, 11
CY7C191
CY7C192
PRELIMINARY
CYPRESS
SEMICONDUCTOR
64Kx 4 Static RAM
with Separate I/O
Features
Functional Description
• High speed
- 12ns
• 1hlnsparent write (7C191)
• CMOS for optimum speed/power
• Low active power
- 880mW
• Low standby power
- 220mW
• TTL-compatible inputs and outputs
• Automatic power-down wheu
deselected
The CY7C191 and CY7C192 are highperformance CMOS static RAMs organized as 65,536 x 4 bits with separate I/O.
Easy memory expansion i~l!!ovided byactive LOW chip enable (CE) and threestate drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected. ,
Writing to the device is accomplished when
the chip enable (CE) and write enable
(WE) inputs are both LOW.
Data on the four input pins (10 through 13)
is written into the memory location specified on the address pins (Ao throughA1S).
Reading the device is accomplished bytaking the chip enable (CE) LOW while the
write enable (WE) remains mGH. Under
these conditions the contents of the
memory location specified on the address
pins will appear on the four data output
pins.
The output pins stay in hi8!!:!mpedance
state when write enable (WE) is LOW
(CY7C192 only), or chip enable (rn) is
HIGH.
A die coat is used to insure alpha
immunity.
Pin Configurations
Logic Block Diagram
10
As
~
~
~
~
A7
~
u
~~~:9~
As
A7
~
Top View
Vee
13
A2
LCC
DIP/SOJ
ThpView
12
A10
A11
A12
00
A13
A14
A15
01
10
11
02
'CE
GND
03
A3
6 7C191
7 7C192
8
9
10
11
12
13
14
24
23
22
21
A2
A1
20
12
03
02
19
18
Ao
13
17
01
16
15
00
WE
C191·2
C191·1
Selection Guide
Shaded area contains advanced infonnation.
2-323
3 2Ll,282~c
4
~
5
25c Aa
6
24C A2
7
23c A1
8 7Cl92 22cAo
9
214 13
10
20c 12
11
19C 03
12
18C 02
~
A10
A11
A12
A13
A14
A15
10
11
,
13~!:!.6!?./
1~~1~80
C191-3
II
U)
:::I
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ...................... - O.5V to +7.0V
DC Voltage ApRlied to Outputs
in High Z State 1] ................. - O.SV to Vee + O.SV
DC Input Voltage[1] ............... - O.SV to Vee + O.SV
Output Current into Outputs (LOW) .............. 20 rnA
Range
Commercial
Military[2]
Ambient
Temperature
Vee
O°Cto +70°C
SV ± 10%
- SSOCto +12SoC
SV ± 10%
Electrical Characteristics Over the Operating Range[3]
GND~Vo~Vcc,
Output Disabled
los
Output Short
Circuit Currentl4]
Icc
Vee Operating
Supply Current
Vee
= Max., VOUT = GND
ISB1
ISB2
Shaded area contains advanced information.
Notes:
1.
Minimum voltage is equal to - 2.0V for pulse durations of less than
20ns.
2. TA is the "instant on" case temperature.
3.
4.
2-324
See the last page of this specification for Group A subgroup testing information.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
~PR&SS
_rs~CONDucrOR
CY7C191
CY7C192
PRELIMINARY
Electrical Characteristics Over the Operating Range[3] (continued)
7C191-20
7C192-20
II
7C191-25, 35, 45
7C192-25, 35,45
t----t------f------+----+---+----+------+------f
tn
~----~~--~~~----~~--~~--~~----~----+----+----+---~~~~
~-----+----------------~--------------------~~---+----~----+-----+-~~
a:
tJ)
GND~ Vo~ Vee,
Output Disabled
lOS
Output Short
Circuit Current[4]
ICC
Vee Operating
Supply Current
Vee
-5
= Max., VOUT = GND
-300
+5
I-tA
-300
rnA
rnA
rnA
ISBl
Current
15
ISB2
rnA
15
Shaded area contains advanced information.
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
8
pF
10
pF
AC Test Loads and Waveforms[6]
R1481.o.
R1481.o.
0----""""-,
OUTPUT 0---""",--+
5Vo----JW~
5V
30
FI
P
OUTPUT
R2
255.0.
5PFI
INCLUDING
JIGAND _
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
0---",,--,
(b)
3.0V ----_.w-~----~
R2
255.0.
C191-5
C191-4
THEVENIN EQUIVALENT
167.0.
OUTPUT (),O- - - - J l..N·I'\o----.()O 1.73V
Notes:
5.
6.
GND
Tested initially and after any design or process changes that may affect
these parameters.
tr = .s 3 ns for the -12 and -15 speeds. tr = .s 5 ns for the - 20 and
slower speeds.
2-325
"7~
Switching Characteristics
CY7C191
CY7C192
PRELIMINARY
Over the Operatiog Raoge[3,7j
3
tOHA
20
tACE
3
tLZCE
25
3
0
tpu
0
3
15
15
35
os
os
0
0
25
20
tpD
3
os
45
35
11
9
tHZCE
3
os
os
45
os
20
25
35
os
tRA
o
o
o
os
tSA
o
o
o
os.
tHD
0
0
os
tLZWE
3
os
tHzWE
10
11
15
15
os
tDWE
20
25
30
35
os
tADY
20
20
30
35
os
35
45
os
tDCE
Shaded area contains advanced information.
Notes:
7.
8.
Test conditions assume signal transition time of 3 ns or less for -12
and -15 speeds and 5 ns or less for - 20 through -45 speeds, timing
reference levels of 1.5Y, input pulse levels of 0 to 3.0Y, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
At any given temperature and voltage condition, tHZCE is less than
tHZCE and tHzWE are specified with CL = 5 pF as in part (b) of AC
Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
9.
tLZCE, tHZWh is less than tLZ\VE for any given device. These parame-
either signa! can terminate a write by going HI GR. The data input set-
ters are guaranteed and not 100% tested.
up and hold timing should be referenced to the rising edge of the signal
that terminates the write.
2-326
.'
·~PRFSS
-====,
CY7C191
CY7C192
PRELIMINARY
SEMICONDUcrOR
Switching Waveforms
•
*-
Read Cycle No. 1[11, 12)
~
ADDRESS
tRC
1
---~toHA~
DATA OUT
PREVIOUS DATA VALID
en
~xx *===============D=A=T=A=V=A=L=ID============
C191-6
Read Cycle No. 2[11, 13)
tRC
~,
/1{.
tACE
DATA OUT
//////
tLZCE
'''''''''-''-
--I+---tpu
VCC
SUPPLY
CURRENT
~tHZCE-
HIGH IMPEDANCE
"'
DATA VALID
HIGH
IMPEDAN CE
,/
~tpo
f5~
9=
ICC
50%
ISB
C191-7
Write Cycle No.1 (WE Controlled)[10)
twc
ADDRESS
~(
)~
tSCE
}W////// ~
~~ ~ "tAW
tHA-
tSA
tPWE
~""~ t\..
/~
DATA VALID
I+-- tHZWE
DATA OUT
(7C192)
tHO ....
tSD
)(
DATA IN
DATA UNDEFINED
:::j
,
,/
)(
4-tLZWE-
HIGH IMPEDANCE
,/
"-
~tOWE
-tADv
DATA OUT
(7C191)
.:::I
------------------4---------------DATA UNDEF'NED
DATA VAUD
C191·B
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected, CE = VIL.
13. Address valid prior to or coincident with CE transition LOW.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state (7C192 only).
2-327
:t
()
::>
a:
~ 0.4
0.2
4.5
~ 100
~ 0.6
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
N
::J
~
11~
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
::J
SUPPLY VOLTAGE (V)
.J.
Icc
I...........
6
...!:? 1.0
ISB
0.0
4.0
1.2
Cl
~ 0.4
0.2
./
~
enZ
!3a...
60
::>
20
I-
o
40
/
oV
J
/
/
Vcc = 5.0V
TA = 25°C
I
0.0
OUTPUT VOLTAGE (V)
4.0
~PRFSS
_~CONDucroR
CY7C191
CY7C192
PRELIMINARY
1YPical DC and AC Characteristics (continued)
typICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1YPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
g
~
2.5
(/)
N
/"
w
~ 1.0
0.5
1.0
----
2.0
~
3.0
./
4.0
SUPPLY VOLTAGE M
5.0
o 10.0
5.0
fil1.00
/
~ 15.0
~ 1.5
II:
~
/
~ 20.0
:::J
V
1/
200
N
:::J
~
II:
Vee = 4.5V TA = 25°C
400
600
~ 0.751---+-....,'-+----l
800 1000
CAPACITANCE (pF)
20
35
~~~--------~~----~----~~--~------------~
~~------------~----_P------~--~------------~
2-329
30
CYCLE FREQUENCY (MHz)
Ordering Information
25
Icc vs. CYCLE TIME
~
25.0
.s
fil 2.0
O. 0
0.0
NORMALIZED
1.25 r-----r----~--....,
30.0
Commercial
Commercial
40
II
~PRFSS
_rs~CONDUCTOR
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
toHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBI
ISB2
Parameter
Subgroups
READ CYCLE
WRITE CYCLE
twc
1,2,3
1,2,3
Document #: 38-00076- I
7, 8, 9, 10, 11
tAw
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpwE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7,8,9, 10, 11
tAWE[15]
7, 8, 9, 10, 11
tADV[15]
7, 8, 9, 10, 11
Note:
15. CY7C191 only
2-330
7, 8, 9, 10, 11
tSCE
CY7C191
CY7C192
CY7B194
CY7B195
CY7B196
CYPRESS
SEMICONDUCTOR
Features
• High speed
-tAA = IOns
• BiCMOS for optimum speed/power
• Low active power
-850mW
• Low standby power
-160mW
• Automatic power-down when
deselected
• Output enable (OE) feature
(CY7B195 and CY7B196 only)
• TTL-compatible inputs and outputs
Functional Description
64K x 4 Static R/W RAM
RAMs organized as 65,536 words by 4 bits.
Easy memory expansion is..£!:.ovided by an
active LOW chip enable (CEl), an active
LOW chip enable (CEz, CY7B196 o~,
an active LOW output enable (OE,
CY7B195 and CY7B196 only), and threestate drivers. Both devices have an automatic power-down feature that reduces
power consumption by more than 75%
when deselected.
Writing to the device is accomplished by
taking~ enable one (CEl) and write enable ~) inputs LOW and chip enable
two (CEz, CY7B196 only) input LOW.
Data on the I/O pin (1/00 through 1/03) is
then written into the location specified on
the address pins (Ao through AlS).
able two (CEz, CY7B1960nly), and output
enabl~E) LOW, while forcing write enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address pins will appear on the
I/O pins.
The four input/output pins (1/00 through
1/03) are placed in a high-impedance state
when the device is deselected (CEI HIGH,
or CEz HIGH, CY7B196 only), the outputs are disabledlQE HIGH), or during a
writ~eration (CEb CEz CY7B196 only,
and WE LOW).
The CY7B194, CY7B195, and CY7B196
are available in 300-mil-wide DIPs and
SOJs.
The CY7B194, CY7B195, and CY7B196
are high-performance BiCMOS static
Logic Block Diagram
SOJ
Top View
DIP
Top View
A2
A3
~
A5
~
As
1/°3
II:
w
0
0
As
Vee
NC
Vee
A7
As
As
As
As
As
~
A7
~
As
A,o
A"
A'2
A'3
A'4
A,s
A2
A,
A3
A2
A,
eE,
GND
WE
DIP/SOJ
Top View
I/O,
0
II:
A9
vee
As
As
~ (7B196 ONLy)
WE
B194-1
(OE) (7B195 and
7B196 only)
U,
OE
GND
NC
NC
1/°3
1/°2
I/O,
1/°0
NC
GND
WE
~
As
As
A,o
A"
A'2
A'3
A'4
A,s
Ao
eE,
B194-3
NC
A7
1/°0
Ag
A,o
A"
A'2
A'3
A'4
A,s
Ao
1/0 3
1/°2
I/O,
1/0 0
1/02
fa0
3:
As
As
A2
A,
Ao
~ U 2 {7B196)
10
11
12
13
14
1/03
1/02
I/O,
1/0 0
WE
NC (7B195)
B194-4
Selection Guide
7B194-10
7B195-10
7B196-10
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)
Commercial
2-331
7B194-20
7B195-20
7B196-20
20
10
12
15
160
150
170
160
35
30
40
40
40
Military
7B194-15
7B195-15
7B196-15
170
Military
Commercial
7B194-12
7B195-12
7B196-12
160
40
•
en
:&
c(
a:
en
CY7B194
CY7B195
CY7B196
~PRR§
~
SEMICONDUCTOR
Maximum Ratings·
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55°C to + 125°C
Supply Voltage on Vee Relative to GND[1]
- O.5V to + 7.0V
DC Voltage ApBlied to Outputs
in High Z State 1] ....................... - O.5V to +7.0V
DC Input Voltagel 1] ..................... - 0.5V to +7.0V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage. . . . ..... . . .... . . . . . .... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[2]
Range
O°Cto +70°C
Vee
5V ± 10%
- 55°C to +125°C
5V ± 10%
Commercial
Military
Electrical Characteristics Over the Operating Rangel3]
7B194-10
7B195-10
7B196-10
Parameter
Description
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
VOH
Output HIGH Voltage Vee
VOL
Output LOW Voltage
VlH
VIL
Input HIGH Voltage
Input LOW Voltagd 1]
Ilx
Input Load Current
loz
Output Leakage
Current
los
Output Short
Circuit Current[4]
Vee
Icc
Vee Operating
Supply Current
Vee = Max., lOUT
f = fMAX = litRe
Automatic CE
Power-Down Current
Max. Vee, CE~ Vee0.3v, VIN ~ Vee - O.3V
or VIN ~ 0.3v, f = 0
ISB
Min.
Max.
2.4
7B194-12
7B195-12
7B196-12
Min.
Max.
2.4
0.4
7BI94-15, 20
7BI95-15,20
7BI96-15, 20
Min.
Max.
2.4
V
0.4
0.4
Unit
V
2.2
Vee
2.2
Vee
2.2
Vee
V
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
GND~VI~Vee
- 10
+10
-10
+10
-10
+10
JlA
GND ~ V I ~ Vee, Output Disabled
-10
+10
-10
+10
-10
+10
f.tA
- 300
- 300
rnA
rnA
= Max., VOUT = GND
- 300
= 0 rnA,
Com'l
170
Mil
Com'l
Mil
40
160
150
170
160
35
30
40
40
rnA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT,CI/O
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
VIL (min.) = - 3.0V for pulse durations of less than 20 ns.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing infonnation.
1.
2.
3.
4.
5.
6.
2-332
= 1 MHz,
MaxJ6]
Unit
6
pF
8
pF
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
For PDIP (P13, P21) AND CDIP (014, D22), CIN = COUT = 10 pF.
CY7B194
CY7B195
CY7B196
·
.~
_ ' j E CYPRESS
---=-_'
SEMICONDUCTOR
AC Test Loads and Waveforms
TI TI
R14810
OUTP~~
20 pF
R14810
R2
I
INCLUDING
JIG AND
SCOPE
OUTP~~
2550
-
-
5 pF
INCLUDING
JIG AND
SCOPE
-
II
90%
R2
2550
GND
~3ns ~
ct
-
a::
8194-5
(b)
(a)
Equivalent to:
I
ALL INPUT PULSES
3.0V----
8194-6
THEVENIN EQUIVALENT
OUTPUT
1670
o-------wv-----
1.73V
Switching Characteristics Over the Operating Rangel3, 7]
7B194-10
7B195-10
7B196-10
Parameter
Description
Min.
Max.
7B194-12
7.8195-12
7B196-12
Min.
Max.
7B194-15
7B195-15
7B196-15
Min.
Max.
7.8194-20
7.8195-20
7B196-20
Min.
Max.
Unit
READ CYCLE
20
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
12
15
20
tDOE
OE LOW to Data Valid
6
6
7
10
tLZOE
OE LOW to Low Z[8]
10
15
12
12
10
3
2
3
3
3
2
2
ns
20
15
ns
ns
2
ns
ns
ns
tHZOE
OE HIGH to High Z[8, 9]
tLzCE
CE LOW to Low Z[8]
tiIZCE
CE HIGH to High Z[8, 9]
6
7
8
10
ns
tpu
CE LOW to Power-Up
0
0
0
0
ns
10
12
15
20
ns
3
3
CE HIGH to Power-Down
tpD
WRITE CYCLE[lO, 11]
8
7
6
3
10
3
ns
ns
twc
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
15
ns
tAW
Address Set-Up to Write End
8
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
8
9
10
15
ns
tSD
Data Set-Up to Write End
6
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLzWE
WE HIGH to Low Z[8]
2
2
2
2
tHzWE
WE LOW to High Z[8, 9]
6
Notes:
7. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 20-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLzOE, and tHZWE is less than tLzWE for any
given device.
9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5
pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
7
7
ns
10
ns
10. The internal write time of the memory is defined by the overlap of CEl
Law, CE2 LOW, and WE Law. Both signals must be LOW to initiate
a write and either signal will terminate a write by going HIGH. The input data set -up and hold timing should be referenced to the rising edge
of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No.3 (WE Controlled,
OE LOW) is the sum of tHZWE and tSD.
2-333
(/)
CY7B194
CY7B195
CY7B196
Switching Waveforms
Read Cycle No. !lIZ, 13]
-t==
~
ADDRESS------'LLHA
DATA OUT
*-
~
I
PREVIOUS DATA VAUD 3XXX*================D=AT=A=V=A=L=ID===========
8194-7
Read Cycle No. 2[13, 14]
)K
ADDRESS
tRC
GE1 ~,
GE2 (78196)
}'?
tACE
OE (78195 and
78196 only)
,{
~,
HIGH IMPEDANCE
DATA I/O
tLZCE
_tpu
tHZOEI--tl-iZCE-
I
tDOE
-tLZOE1//////
"'
DATA VALID
I"""
HIGH
IMPEDANCE
/
I----tpD
~ CC
I
50%
IS8
8194-8
Write Cycle No.1 (CEI or CE2 Controlled)[15, 16]
~--------------------------twc--------------------------~
ADDRESS
----+-------------~ ~~-----tSCE----~~
,-----+-----
~----------tsA-----------.1'--------/
~----------------------~w------------------~~--
~---------tSD-------.~
DATA I/O
HIGH IMPEDANCE
DATA VALID
HIGH IMPEDANCE
8194-9
Notes:
12. Device is continuously selected. eEl (OE: 7B195 and 7B196, eE2:
7B196 only) = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with eEl and eE2 transition
15. Data I/O is HIGH impedance if DE = Vm.
16. If eEl (eEl or eE2 on the 7B196) goes HIGH simultaneously with
WE HIGH, the output remains in a high-impedance state.
Law.
2-334
CY7B194
CY7B195
CY7B196
i~PRESS
·
_ ; ; SEMICONDUCIOR
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE HIGH During Write for 7B195 and 7B196 only)[15, 16]
II
~------------------------twc----------------------~
ADDRESS
CE:1
CE:2(78196)
~~~~~~~--------------------------------------~~~~~~-'~~
14----- tSA --_.-I
____________________
-,~~~
~~------tpwE--------~
,-___________________
OE (78195 and
78196 only) """,-",,,,",",,,__",,,,,-",
14----------tSD----------~~~
DATA VALID
DATAI/O
B194-10
Write Cycle No.3 (WE Controlled, OE LOW)[ll, 16]
ADDRESS
14------tSD-----..t~-..t
DATA I/O
DATA VALID
Note:
17. During this period, the l/Os are in the output state and input signals
should not be applied.
2-335
CY7B194
CY7B195
CY7B196
-:;7~
78194 'fruth Thble
.CEl
WE
H
X
HighZ
L
H
L
L
Power
Mode
1100 - 110 3
Power-Down
Standby (ISB)
Data Out
Read
Active (Icc)
Data In
Write
Active (Icc)
78195 'fruth Thble
CEl
WE
OE
H
X
X
HighZ
Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (Icc)
L
L
X
Data In
Write
Active (Icc)
H
H
HighZ
Selected, Output Disabled
Active (Icc)
L
1100 - 1/0 3
Mode
Power
78196 'fruth Table
CEl
c~
WE
OE
H
X
X
X
HighZ
Power-Down
Standby (ISB)
X
H
X
X
HighZ
Power-Down
Standby (ISB)
L
L
H
L
Data Out
Read
Active (Icc)
L
L
L
X
Data In
Write
Active (Icc)
L
L
H
H
HighZ
Selected, Output Disabled
Active (Icc)
Input/Output
Mode
2-336
Power
CY7B194
CY7B195
CY7B196
ffi~~
Ordering Information
Speed
(ns)
10
12
15
20
Speed
(ns)
10
12
15
20
Ordering Code
Package
Name
Package lYPe
Operating
Range
Commercial
CY7BI94-lOPC
P13
24-Lead (300-Mil) Molded DIP
CY7BI94-lOVC
V21
28-Lead (300-Mil) Molded SOJ
CY7B194-12DC
D14
24-Lead (300-Mil) CerDIP
CY7B194-12PC
P13
24-Lead (300-Mil) Molded DIP
CY7B194-12VC
V21
28-Lead (300-Mil) Molded SOJ
CY7B194-12DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7B194-15DC
D14
24-Lead (300-Mil) CerDIP
Commercial
CY7B194-15PC
P13
24-Lead (300-Mil) Molded DIP
CY7B194-15VC
V21
28-Lead (300-Mil) Molded SOJ
Commercial
CY7B194-15DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7B194-20DMB
D14
24-Lead (300-Mil) CerDIP
Military
Ordering Code
CY7B196-lOPC
Package
Name
Package lYPe
Operating
Range
P21
28-Lead (300-Mil) Molded DIP
CY7B196-10VC
V21
28-Lead (300-Mil) Molded SOJ
CY7B196-12DC
D22
28-Lead (300-Mil) CerDIP
CY7B196-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B196-12VC
V21
28-Lead (300-Mil) Molded SOJ
CY7B196-12DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7BI96-15DC
D22
28-Lead (300-Mil) CerDIP
Commercial
CY7B196-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7B196-15VC
V21
28-Lead (300-Mil) Molded SOJ
CY7B196-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B196-20DMB
D22
28-Lead (300-Mil) CerDIP
Military
2-337
Commercial
Commercial
II
CY7B194
CY7B195
CY7B196
£ffJi1!II'
i~PRESS
.
"':!!ffi!!III'
SEMICONDUCTOR
Ordering Information (continued)
Speed
(ns)
10
12
15
20
Ordering Code
Package
Name
Package
1Ype
Operating
Range
CY7BI95-lOPC
P21
28-Lead (300-Mil) Molded DIP
CY7B195-10VC
V21
28-Lead (300-Mil) Molded SOJ
Commercial
CY7B195-12DC
D22
28-Lead (300-Mil)CerDIP
CY7B195-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B195-12VC
V21
28-Lead (300-Mil) Molded SOJ
CY7B195 -12DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B195-15DC
D22
28-Lead (300-Mil) CerDIP
Commercial
CY7B195-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7B195-15VC
V21
28-Lead (300-Mil) Molded SOJ
CY7B195 -15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B195 - 20DMB
D22
28-Lead (300-Mil) CerDIP
Military
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIR
1,2,3
tAA
7,8,9,10,11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDOE
7, 8,9, 10, 11
Icc
1,2,3
ISB
1,2,3
READ CYCLE
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-0015B-D
2-338
CY7C194
CY7C195
CY7C196
64K X 4 Static RAM
Features
Functional Description
• High speed
- 12ns
• Output enable (OE) feature (7C195
and 7C196)
• CMOS for optimum speed/power
• Low active power
- 880mW
• Low standby power
- 220mW
• TTL-compatible inputs and outputs
• Automatic power-down when
deselected
The CY7C194, CY7C195, and CY7C196
are high-performance CMOS static RAMs
organized as 65,536 by 4 bits. Easy
memory expansion is---.£!ovided by active
LOW chip enable(s2JfE on the CY7C194
and CY7C195, eEl, CE2 on the
CY7C196) and three-state drivers. They
have an automatic power-down feature, reducing the power consumption by 75%
when deselected.
write enable (WE) inputs are both WW.
Data on the four input pins (1/00 through
1/03) is written into the memory location,
specified on the address pins (Ao through
AlS)·
Reading the device is accomplished by taking the chip enable(s)~CE on the
CY7C194 and CY7C195, CEl, CE2 on the
CY7C196) LOW, while write enable (WE)
remains HIGH. Under these conditions
the contents ofthe memory location specified on the address pins will appear on the
four data output pins.
Writing to the device is accomplished when
the chip enable(s2..{gE on the CY7C194 and
CY7C195, CEl, CE2 on the CY7C196) and
Logic Block Diagram
A die coat is used to ensure alpha immunity.
Pin Configurations
DIP/SOJ
Top View
DIP/SOJ
Top View
As
1
As
Ag
Ala
A11
A12
A13
A14
A1S
As
As
A7
As
~
22
21
4
Vee
Vee
24
23
A7
As
Ala
All
Ao
CE
1/03
1/0 2
1/01
1/0 0
GND
WIO
~
A3
A2
Al
As
A2
Al
Ao
CE2
NC
- [ (7C196)
1/03
1/0 2
A14
A1S
CE1
OE
1/00
GND
WIO
NC
(7C195)
1/0 1
Cl94-2
Lee
Lee
Top View
()
1/00
As
~ (7C196 only)
WIO
'--JP----
(01:)
(7C195 and
7Cl96 ONLy)
Ag
Ala
All
A12
A13
A14
A1S
CE
C194-1
4
5
6
7
8
9
10
11
12
()
.t~~~
'3 2~:2827
7Cl94
.t~~~~
26 As
25 ~
24 A3
23 A2
22 Al
21 Ao
20 1/03
19 1/02
18 1/01
'- 13~!:1.617
~~~I~
C194-3
Top View
As
Ag
A10
A11
A12
A13
A14
A1S
CE1
32,1,2827
26
4
5
25
6
24
7
23
8
7C196 22
21
9
10
20
11
19
12
18
1314151617
~
As
A2
Al
Ao
NC
CE2
1/03
1/02
I~~I~§~
g
C194-4
C194-5
Selection Guide
7C194-20
7C195-20
7C196-20
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Commercial
Military
Maximum Standby Current (rnA)
30
Shaded area contains preliminary information.
2-339
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
45
20
25
35
135
115
115
150
125
125
125
30
30
30
30
•
CY7C194
CY7C195
CY7C196
_.
~
~~
~=CYPRESS
~, SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Operating Range
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Range
DC Voltage Apglied to Outputs
in High Z State 1] . . . . . . . . . . . . . . . . . - O.5V to Vee + 0.5V
DC Input Voltagel 1] ............... - O.5V to Vee + 0.5V
Commercial
Military[2]
Output Current into Outputs (LOW) .............. 20 rnA
Electrical Characteristics Over the Operating Rangel 3]
Parameter
VOH
VOL
VIR
VILLI]
IIX
loz
los
Icc
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating
Supply Current
tgt;~:~~
7C194-12
7C195-12
7C196-12
Min.
Max.
Test Conditions
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
'. 2.4"
2.4
0.4
2.2-
Vee
+0.3V
.....:0.5
0.8
; +5
-15
. 45' '" +5
GND~ Vo~ Vee,
Output Disabled
Vee = Max.,
VOUT = GND
Vee = Max., lOUT = 0 rnA,
f =fMAX =l/tRe
>"0'
0.4
'2.2
GND~VI~Vee
ISBI
Automatic CE
Power-Down Current
-TTL Inputs[5]
Max. Vee, CEl,2~ VIR,
VIN ~ VIR or VIN ~ VIL, f
ISB2
Automatic CE
Power-Down Current
-CMOS Inputs[5]
Max. V ee, CEl,2~ Vee - 0.3y, Com'l
VIN ~ Vee - 0.3Vor
Mil
VIN ~ 0.3y, f = 0
Vee
+0.3V
0.8
+5
+5
~0.5
...,5
"':'5
j"
.....;390
Com'l
Mil
":160
j
3d
c'
7C196-1'5
Min.
l\;1!'x.
.'
.
Unit
V
V
V
V
IlA
IlA
-300
rnA
145
160
.30
rnA
10
15
rnA
rnA
= fMAX
10
Shaded area contains preliminary information.
Notes:
1. Minimum voltage is equal to - 2.0V for pulse durations ofless than 20
ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
2-340
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
A pull-up resistor to Vee on the CE input is required to keep the device
deselected during Vee power-up, otherwise ISB will exceed values given.
CY7C194
CY7C195
CY7C196
Electrical Characteristics Over the Operating Range[3] (continued)
Parameter
VOH
VOL
VIR
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current[4]
Vee Operating
Supply Current
VIL
IIX
loz
los
Icc
7C194-20
7C195-20
7C196-20
Min. Max.
2.4
0.4
2.2
Vee
+ O.3V
-0.5
0.8
-5
+5
-5
+5
GND~VI~Vee
GND~ Vo~ Veo
Output Disabled
Vee = Max.,
VOUT= GND
Vee = Max., lOUT = 0 rnA,
f =fMAX =1/tRe
ISBl
Automatic CE
Power-Down Current
-TIL Inputs[S]
ISB2
Automatic CE
Power-Down Current
-CMOS Inputs[S]
ICom'l
I Mil
Max. Vee, CEl,2L VIR,
VINL VIR or
VIN ~ VIL, f = fMAX
Max. Vee, CEl,2 L Vee - 0.3v,
VIN L Vee - 0.3Vor
VIN ~ 0.3v, f = 0
7C194-25,35,45
7C195-25,35
7C196-25,35,45
Min.
Max.
2.4
0.4
2.2
Vee
+O.3V
-0.5
0.8
-5
+5
-5
+5
Unit
V
V
V
V
ItA
ItA
-300
-300
rnA
135
150
30
115
125
30
rnA
15
15
rnA
rnA
Shaded area contains preliminary information.
Capacitance[6]
Parameter
Max.
Unit
TA = 25°C, f = 1 MHz,
8
pF
Vee = 5.0V
10
pF
Description
Test Conditions
Input Capacitance
Output Capacitance
CIN
COUT
AC Test Loads and Waveforms[7]
R1481{l
R1481{l
0----.....,........,
OUTPUT 0---""",----,
0----.....,.........
OUTPUT 0---""",---,
5V
30
FI
P
5V
5PFI
R2
255{l
INCLUDING
JIGAND _
SCOPE -
R2
255{l
ALL INPUT PULSES
----_u-___
----~
GND
INCLUDING
JIGAND _
SCOPE -
C194-6
(b)
(a)
Equivalent to:
3.0V
THEVENIN EQUIVALENT
167{l
OUTPUT O'O----'l'.NV'I.----OO 1.73V
Notes:
6. Tested initially and after any design or process changes that may affect
these parameters.
7. tr = ~ 3 ns for the -12 and -15 speeds. tr = ~ 5 ns for the -20 and
slower speeds.
2-341
C194-7
_..
-=r
CY7C194
CY7C195
CY7C196
~
~ill CYPRESS
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 3,8]
7C194t 1Z
7C194-15
7C19s-1S
7C196-15,
.Ji~1l
.t-.1Z
Parameter
.~~~
Description
READ CYCLE
Read Cycle Time
tRC
l~l,j:",'j
tLZCEb
tLZCE2
tHZCEl,
tHZCE2
CE HIGH to
High Z[9,1O]
tOHA
tACEl,
tACE2
tDOE
tLZOE
tHZOE
12
12
9
tHD
'7 ..
.'
ns
ns
ns
3
3
20
25
35
45
ns
9
10
16
16
ns
3
0
. . 0 ::
.. '
tel 7
...
3
3
ns
", ..
i ;,
9
3
11
3
3
. :;7
I
CE LOW to Write
End
Address Set-Up to
Write End
Address Hold from
Write End
Address Set-Up to
Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
45
.c· "
,
9
I,·m.~
.: 0
Write Cycle Time
tSD
35
Unit
15
15
3
11
3
ns
15
15
ns
ns
.
tSCE
tpWE
45
35
25
3
3
... ,l~ .~
5
twc
tSA
7C194-35
7C195-35
7C196-35
:,::::,
;
CE LOW to
Power-Up
CE HIGH to
tpD
Power-Down
WRITE CYCLEl11]
tHA
20
.. :.:.
3
25
20
15
..
tpu
tAW
.,:",~
15
7C194-25
7C195-25
7C196-25
7C194-45
7C196-45
Min. Max. Min. Max. Min. Max. Min. Max.
Max.
Min.
Fi'
;'f,>
Address to Data Valid
,;';l~:
,:
3;
Output Hold from
Address Change
;' '.
::~.
CELOWto
12
"'1
Data Valid
.....
OELOWto 7C195,
5
Data Valid
7C196
OELOWto 7C195,
0
LowZ
7C196
OElllGH
7C195,
5
to High Z[lO] 7C196
CELOWto
13
LowZ[9]
tAA
7C194-20
7C195-20
7C196-20
0
0
0
0
ns
,,'
1\:'
I~'
20
15
.;,
15
25
45
35
ns
20
15
25
ns
18
35
22
45
10
22
ns
10
15
20
25
35
ns
::
0
0
0
0
0
ns
..
0
0
0
0
0
ns
15
18
10
22
22
10
15
15
ns
ns
0
0
0
0
ns
3
3
3
3
ns
.. ':'.~,:.,:..;
9
.',
~O
:';
I,LO
{
1<.;:;.
i'~<
8
1.
9
'.
j
:;.
::.
9 ':':
1~)f8
;
,:;
I~~'~
0
;
.;
•
tLZWE
WE HIGH to
Low Z[9]
tHzWE
WE LOW to
HighZ[9,8]
;5
3
':3
;2'
7
.,~.
:~
·'t
10
0
13
0
15
0
20
ns
J
Shaded area contains preliminary information.
Notes:
8.
Test conditions assume signal transition time of 3 ns or less for -12
and -15 speeds and 5 ns or less for - 20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, and tHZWE are specified w"ith CL = 5 pF as in part (b)
of AC Test Loads. 'fransition is measured ±500 m V from steady-state
voltage.
11. The internal write time of the memory is defined by the overlap of CEI
LOW, CE2 LOW, and WE LOW. All signals must be LOW to initiate
a write and any signal can terminate a write by going HIGH. The data
input set-up and hold timing should be referenced to the rising edge of
the signal that terminates the write.
2-342
CY7C194
CY7C195
CY7C196
· ~~
= ' i / I CYPRFSS
SEMICONDUCTOR
-=-,
Switching Waveforms
Read Cycle No. 1[12, 13]
II
~---------------------- tRC ------------------------~
ADDRESS
jK
------"------------------------) (
'-----
~----------tAA --------~
-tOHA-4
DATA OUT
PREVIOUS DATA VALID
PI< X X ) (
DATA VALID
'-----------------
C194-B
Read Cycle No. 2[12, 14]
tRC
~~
j?
tACE
OE
~~
(7C195 and
7C196)
)'?
tDOE
I+-DATA OUT
tLZCE
VCC
SUPPLY
CURRENT
14--
tLZOE-
HIGH IMPEDANCE
I/////V
tHZCE
~
DATA VALID
"'-""""1'\
I+---
---1I+--
.=E3
tpu
tpD
HIGH
IMPEDAN CE
9=
ICC
50%
ISS
C194-9
Write Cycle No.1 (CE Controlled)[ll, 15, 16]
~------------------------- twc --------------------------~
ADDRESS
CE 1
CE2
--+-------------__...
~----- tSCE -------.I
_----+-----
(7C196)
~--------------------~w --------------------~~--
1'111;1------
DATA I/O
tSD ----~..
-------------~~-----D-AT-A-V-A-L-ID----- ~------C194-10
Notes:
12. WE is HIGH for read cycle.
13. Device is continuously selected: CEI = VIL, CE2 = VIL (7CI96), and
OE = VIL (7C195 and 7CI96).
14. Address valid prior to or coincident with CEI and CE2 transition
Law.
15. Data I/O will be high impedance if OE = VIH (7C195 and 7CI96).
16. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE LOW) is the sum of tHZWE and tSD'
2-343
CY7C194
CY7C195
CY7C196
~~
~ICYPRESS
SEMICONDUCTOR
~._
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE HIGH During Write for 7C195 and 7C196 only)[ll, 15, 16]
~------------------------twe ----------------------~
ADDRESS
GEl
GE2(7C196)~~~p..;~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~~~:.£..J.~~~
WE--------------------__~____ ~~-----tpwE --------~,_------------------14-------- tSD - - - - - - - - - -....~-.I tHD
DATA I/O
DATA VALID
C194-l2
Write Cycle No.3 (WE Controlled. OE LOW)[16, 17]
ADDRESS
GEl
GE2(7C196) ......~~~.....,;:~I11....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....;.......J.""""''"''''~~~'"''''~~~
, . . . - - - - - tSD -------+-~
DATAI/O
DATA VALID
C194-ll
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ffi
.13
1.2
lee
1.0
Cl
~ 0.8
::J
~ 0.6
./"
V
Il:
In
.::: 1.2
.13
1.0
--
~ 0.6
5.0
5.5
6.0
-55
=> 80
()
~
Vee = 5.0V VIN = 5.0V
ISB
25
125
AMBiENT TEMPERATURE (oGj
2-344
100
Il:
Il:
Il:
0.0
4.5
~
::J
0.2
SUPPLY VOLTAGE (V)
r5
~ 0.4
ISB
1. 120
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
I-
~
~ 0.8
0.0
4.0
lee
.............
Cl
VIN = 5.0V
TA = 25°C
~ 0.4
0.2
V
1.4
V
~
~ 60
=>
~
Il:
g
5a.
5o
40
20
0
0.0
Vee = 5.0V
TA = 25°C
"'" '"
1.0
2.0
3.0
'"
OUTPUT VOLTAGE (V)
4.0
CY7C194
CY7C195
CY7C196
--. ~~
-=-,
~
_ ' i i I CYPRESS
SEMICONDUCTOR
1:ypical DC and AC Characteristics
(continued)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
J.
w 1.2
1.1
:2:
ex::
a
80
Z
Ci5
60
Z
~ 40
N
N
«
.............
TA = 25°C
---
...............
0
z 1.0
0.9
0.8
4.0
4.5
5.0
r--
0.81--------4------1
a.
I-
::>
0.6 '--_ _ _--'_ _ _ _ _....J
-55
25
125
6.0
M
o
TYPICAL POWER· ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
~
2 .5
/
..s
o 2.0
w
~ 20.0
N
:::i
~ 15.0
--
0.5
1.0
2.0
~
3.0
5.0
4.0
5.0
/'
1.0
2.0
3.0
t)
/
200
1.00
N
:::i
«
400
600
:2:
ex::
~ 0.751-----!--",c.-!-----I
800 1000
20
30
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
7C194 Truth Table
CE
WE
H
X
HighZ
L
H
L
L
Data 110
Mode
Power
DeselectlPower-Down
Standby (ISB)
Data Out
Read
Active (Icc)
Data In
Write
Active (Icd
7C195 Truth Table
CEI
H
WE
OE
X
X
Data 110
HighZ
Mode
Power
DeselectlPower-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (Icd
L
L
X
Data In
Write
Active (Icd
L
H
H
HighZ
Deselect
Active (Icd
7C196 Truth Table
WE
OE
X
X
H
X
X
L
H
L
L
L
L
X
L
L
H
H
CEI
H
CE2
X
X
L
Data 110
HighZ
4.0
M
NORMALIZED Icc vs. CYCLE TIME
1.25 r----""'T'"---r----...,
fa
Vee = 4.5V TA = 25°C
/
M
SUPPLY VOLTAGE
I
.2
/
w
o 10.0
/
Vee = 5.0V
TA = 25°C
~
25.0
en
.E-
/
OUTPUT VOLTAGE
30.0
« 1.5
:2:
ex::
0 1.0
z
/
V
o
0.0
I
/
20
AMBIENT TEMPERATURE (0C)
3.0
0.0
0.0
~
0
5.5
SUPPLY VOLTAGE
0
ex::
1.2
:::i
~
•
/
~ 100
:2:
ex:: 1.0
W
.,-
120
z
0
0
«
S
I-
J.1.4
1.3
:::i
« 140
1.6
1.4
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
Mode
Power
DeselectlPower·Down
Standby (ISB)
Data Out
Read
Active (Icd
Data In
Write
Active (Icd
HighZ
Deselect
Active (Icd
2-345
40
CY7C194
CY7C195
CY7C196
~
"'~PRF.SS
~, SEMICONDUCTOR
Ordering Information
Speed
(ns)
I':
Package
Name
Ordering Code
.
:qy7C194"':1~Vq . '
; CY7Cl9:4-'15DM:s,'
t
!
; 5CY7~1~:::.;i5L~'·i:·
I
20
CY7C194-20PC
':~:lza$Th~!cle,d$~d!i?J;;;,
CY7C194-20VC
V13
45
Speed
(ns)
12
•. •
J
,.
'\~L~.
i
Commercial
24-Lead Molded SOJ
}~.L~~d(300-MjItCerD~p: .;;;1:,
t
;;:28~Pin Rectang:u1ar Learllesselrlp Carrier
24-Lead (300-Mil) Molded DIP
~m~ary.,
CY7C194-25PC
D14'
L54
P13
CY7C194-25VC
V13
24-Lead Molded SOJ
CY7CI94-25DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7CI94-25LMB
CY7C194-35PC
L54
P13
28-Pin Rectangular Leadless Chip Carrier
24-Lead (300-Mil) Molded DIP
Commercial
CY7C194-35VC
V13
24-Lead Molded SOJ
CY7CI94-35DMB
D14
24-Lead (300-Mil) CerDIP
CY7CI94-35LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7CI94-45DMB
CY7CI94-45LMB
D14
L54
24-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
Package
Name
Package 1YPe
r-------------~r_----~----~----~------------~
35
I
r;Y,
11
. ·~~~1;\g~(SOO-~l) ~rDIP .,;::; "(:j:Military
. ~ L54" .t; ·28.:PinRectan~lat;;~~dless:C:hillCarrier
P13
24-Lead (SOO-Mil) Molded DIP
CY7C!~4-20DMB
CY7G194-20L~B
25
Vl£
,ff Dl~
Operating
Range
Package. 'JYpe
Ordering Code
i' cyZc;;!fl?;-: 12p,C . ,
' CY7Q19~ -12V<:«W*,
'P2f
V21
15.: . if: CY1.C195 ,J5Pa!~*i';;; .
28;;Ii;~~: Q(Jp:Nn:~~QldediDIP
....
28.IJ~d;Moldect:~O.J
'
i
.,i
Commercial
Military
Military
Operating
Range
€Qnnnercili(l
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ...................... - O.5V to +7.0V
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
DC Voltage Apglied to Outputs
in High Z State 1] ................. - O.5V to Vee + O.5V
DC Input Voltagel 1] ............... - O.5V to Vee + O.5V
Output Current into Outputs (LOW) .............. 20 rnA
Military[Z]
Electrical Characteristics Over the Operating Rangel 3]
,eC197-::12
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH
VOL
Output LOW Voltage
Vee
VIR
= Min.
=-
2~i
4.0 rnA
IIOL = 12.0 rnA
IIOL = 8.0 rnA
Mil
VIL
Input LOW Voltagel 1]
IIX
Input Load Current
loz
Output Leakage Current
GND S Vo s Vee, Output Disabled ",,-5
los
Output Short
Circuit Current[4]
Vee
Icc
Vee Operating
Supply Current
Vee = Max., lOUT
f = fMAX = litRe
Automatic CE Power-Down
Current-TTL Inputs[5j
Max. Vee, CE L VIR, VIN L VIR or
VIN S VIL, f = fMAX
Max. Vee, CE L Vee - 0.3V, Com'l
VIN L Vee - O.3Vor
VIN < O.3V
Mil
ISBl
ISBZ
Automatic CE Power-Down
Current-CMOS Inputs[5]
n
2.~;
VC;.;;
GNDsVIsVec
.
Mil
';,
V
0.4
V
\r~e
V
+'O:~V
"
-0.5
0.8
V
+5,'i:
-5,
:";5
!1A
+5
-5"
'\;
{':i,> 30
,~
+5
-300
":!'
I '>,
", ~}'~1'60 /:~ '"
~~~
V
"
F~;'4
0.8
-300
';~+,
",,:, Iii., "j.,17
Com'l
,
.:.
,
+0;3\'
-OS
= 0 rnA,
.,
'1:v'
2.2((t;,~
= Max., VOUT = GND
,' fA
'0
"~,~
Input HIGH Voltage
Unit
,",
g:,U
Com'l
"!Max.
Min.
'~ax:.
Min.
7C19'l-15
LOY
"i
l;t " , ,','
,ii,
10
:
}
!
5
,.'
150
+
!J.A
rnA
rnA
160
,/ 30
;;r
10
rnA
rnA
;15
Shaded area contains preliminary information.
Notes:
1. V(min.) = -2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
2-349
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds,
A pull-up resistor to Vee on the CE input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
II
,~~
CY7C197
Electrical Characteristics Over the Operating Range[3] (continued)
Capacitance[6]
Parameter
Description
eIN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
Max.
TA ::::: 25°C, f ::::: 1 MHz,
Vee::::: 5.0V
Unit
8
pF
10
pF
AC Test Loads and Waveforms[7]
R1329.n.
(480.n. MIL)
R1329.n.
(480.n. MIL)
SV
5V
30PFI
INCLUDING
JIG AND _
ALL INPUT PULSES
OUTPUTo-----~--_.
OUTPUTo---+---t
R2
202.n.
(255.n.MIL)
SCOPE -
INCLUDING
JIGAND _
255.n.
(25S.n.MIL)
GND
.s.I,
SCOPE -
(b)
(a)
Equivalent to:
'W~_
10%
R2
SpF
THEVENIN EQUIVALENT
125.n.
167.n.
OUTPUT OO----~.N."'"""----OO 1.73V
Commercial
Military
Notes:
6. Thsted initially and after any design or process changes that may affect
these parameters.
7. tr = oS. 3 ns for the -12 and -15 speeds. tr = oS. 5 ns for the - 20 and
slower speeds.
2-350
10%
.s.t,.
C197-S
C197-4
OUTPUT OO----~.Nu"'"""----'OO 1.90V
Je
.
~~
_'lE
-IF
CY7C197
CYPRESS
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel 3,8]
7C197-12
Parameter
7C197-20
7C197-15
Min. Max.
Description
7C197-25
7C197-35
7C197-45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to
Data Valid
tOHA
Output Hold from
Address Change
tACE
CELOWto
Data Valid
12
cC
'
20
15
-,
12
20
15
3
3
3
12
25
35
25
ns
45
3
3
20
15
35
25
45
3
35
ns
ns
45
ns
"
tLZCE
CE LOW to
Low Z[9]
tHZCE
CE HIGH to
High Z[9, 10]
3
3
7
5
CE LOW to
Power-Up
tpD
CE HIGH to
Power-Down
0
3
9
0
3
11
0
3
15
0
ns
15
ns
,
"
tpu
3
0
0
0
20
15
12
0
0
0
25
20
ns
30
ns
~,
WRITE CYCLE[llJ
twc
Write Cycle Time
12
15'
20
25
35
45
ns
tSCE
CELOWto
Write End
9
10
15
20
30
40
ns
tAW
Address Set-Up to
Write End
9
15
20
30
40
ns
0
0
0
0
ns
0
0
0
0
ns
15
20
25
30
ns
10
15
17
20
ns
0
0
0
0
ns
3
3
3
3
ns
tHA
10
Address Hold from
Write End
,
a
0
','
"
,
Address Set-Up to
Write Start
0
,0
tpWE
WE Pulse Width
S·
9
tSD
Data Set-Up to
Write End
tHD
Data Hold from
Write End
tSA
tLZWE
tHZWE
WE HIGH to
LowZ[9]
WE LOW to
High Z[9, 10]
"
1
' !
~,9
<
',!;'
0
cO
Co"
",~,:~;..
:,
I~"·
I
,"'v
,:::,
1
ecce
1
0
Shaded area contains preliminary information.
Notes:
8. Test conditions assume signal transition time of 3 ns or less for -12
and -15 speeds and 5 ns or less for - 20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IoIfloH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHzWE is less than tLzWE for any given device.
10. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC
Test Loads and Waveforms. Transition is measured ±500 mV from
steady-state voltage.
10
0
11
0
15
0
15
ns
11. The internal write time ofthe memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
2-351
•
~
~~
~=CYPRESS
~, SEMICONDUCTOR
CY7C197
Switching Waveforms
Read Cycle No. !l12, 13]
~----------------------tRC------------------------~
ADDRESS
)K'
__________J
)(
, __________________________________________- J
' -_ _ _ _ _ __
~-----------tAA--------~~
I4---tOHA~
DATA OUT
*XX ) (
PREVIOUS DATA VALID
DATA VALID
'-------------------------------C197-6
Read Cycle No. 2[13]
tRC
~~
)~
tACE
~tHZCE-
tL2CE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
//////
"
DATA VALID
''''''''''
/
I+--tpD
foI--tpu
HIGH
IMPEDAN CE
- - - fSO%
~
50%
CC
I
ISB
C197-7
Write Cycle No.1 (WE Controlled)[12]
~--------------------------twc------------~------------~~
ADDRESS
~-----------------tSCE--------------------~
______~~_~~~~:::_tS_A_-_-_-_-_-_-___
-~~~~~~~
~-----tpWE------~,-___________________
DATA IN
DATA OUT
DATA UNDEFINED
C197-8
Notes:
12. WE is HIGH for read cycle.
13. Device is continuously selected, CE = VIL.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-352
g
~
CY7C197
_ . , i E CYPRESS
JF SEMICONDUCTOR
Switching Waveforms (continued)
•
Write Cycle No.2 (CE Controlled) [12, 14]
---------------------------
~------------------------twc
ADDRESS
----*-'-------
tSCE
--------+1
~-------------~------ ~w -----------------~~
*
~.
tSD - - - - - - - !..
DATA IN _ _ _ _ _ _ _ _ _
tHD
~/
_ _ _ _ _ __
~
DATA VALID
DATA OUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
H_IG_H_I_M_P_ED_A_N_C_E_ _ _ _ _ ____
C197-9
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
gJ 1.2
Icc
..B 1.0
V
o
~ 0.8
~ 0.6
::2:
~
V
~
-
5.0
5.5
6.0
~ 80
()
"
~ 60
g
ir
I-
40
I-
125
5
20
0
0.0
1.6
1.3
J1.4
1.0
2.0
« 140
.....
II:
~ 1.0
~
~
II:
r--
oZ
0.81----------4---------1
0.9
4.0
80
Z
Ci.i
60
~
::2:
TA = 25°C
a
II:
::J
.............
~ 40
a..
~ 20
o
4.5
5.0
5.5
SUPPLY VOLTAGE
M
6.0
~
~ 100
«
0.6'------------'-----------1
-55
25
125
AMBIENT TEMPERATURE (0C)
2-353
4.0
M
v
z
o
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
I-
W
N
'" '"
OUTPUT VOLTAGE
.s 120
@ 1.2
Vcc = 5.0V
TA = 25°C
~
:::>
IS8
25
~
II:
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
0.8
100
AMBIENT TEMPERATURE (0C)
M
NORMALIZED ACCESS TIME
SUPPLY VOLTAGE
~ 1.1
~
Vcc = 5.0V VIN = 5.0V
0.0
-55
VS.
::J
ifi
II:
0.6
0.2
4.5
I-
II:
IS8
SUPPLY VOLTAGE
N
~
~ 0.4
0.0
J
Icc
I............
~ 0.8
II:
4.0
1.2
<3
.2 1.0
VIN = 5.0V
TA = 25°C
1120
1.4
2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperatore[2]
Vee
O°Cto +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
Military
Electrical Characteristics Over the Operating Range[3]
7B199-10
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Max.
2.4
2.4
Vee
7B199-12
Min.
7B199-15,20
Min.
Max.
Unit
0.4
V
2.4
0.4
0.4
V
VIR
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltagd 1]
- 0.3
0.8
- 0.3
0.8
- 0.3
0.8
V
IIX
Input Load Current
GND~Vl~Vee
-10
+10
-10
+10
- 10
+10
flA
loz
Output Leakage
Current
GND ~ VI~ Vee, Output
Disabled
-10
+10
- 10
+10
-10
+10
flA
los
Output Short Circuit
Current[4]
Vee
lee
Vee Operating
Supply Current
Vee = Max., lOUT
f = fMAX = litRe
Automatic CE
Power-Down Current
- CMOS Inputs
Max. Vee, CE~ Vee0.3v, VIN ~ Vee - O.3Vor
VIN ~ 0.3v, f = 0
ISB
= Max., VOUT = GND
= 0 rnA,
Com'}
- 300
- 300
- 300
rnA
185
170
170
rnA
170
170
35
30
40
40
Mil
Com'l
40
Mil
rnA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
Com; CliO
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (min.) = - 2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
2-357
= 1 MHz,
MaxJ6]
Unit
6
pF
8
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
For PDIP (P21) and CDIP (D22), CIN=COUT=lO pF.
~~
~~CYPRESS
CY7B199
, . SEMICONDUCTOR
AC Test Loads and Waveforms
TI TI
R1481Q
OUTP~~
20 pF
R1481Q
R2
255Q
I
INCLUDING
JIG AND
SCOPE
-=
OUTP~~
-=
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
I
-
ALL INPUT PULSES
3.0V---R2
255Q
GND
B199-3
(b)
B199-4
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics Over the Operating Rangel 3, 7]
7B199-10
Parameter
Description
Min.
Max.
7B199-12
Min.
Max.
7B199-15
Min.
Max.
7B199-20
Min.
Max.
Unit
READ CYCLE
12
15
20
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
12
15
20
ns
tDOE
OE LOW to Data Valid
6
6
7
10
ns
tLZOE
OE LOW to Low Z[8]
tHzOE
OE HIGH to High Z[8, 9]
10
ns
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[8,9]
10
ns
tpu
CE LOW to Power-Up
0
0
0
0
ns
tpD
CE HIGH to Power-Down
10
12
15
20
ns
10
10
3
12
3
3
2
2
3
ns
3
3
8
ns
ns
2
8
7
6
ns
20
3
2
7
6
3
15
ns
WRITE CYCLE[lO, 11]
twc
Write Cycle Time
10
12
15
20
ns
tSCE
CE LOW to Write End
8
9
10
15
ns
tAw
Address Set-Up to Write End
8
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
8
9
10
15
ns
tSD
Data Set-Up to Write End
6
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
2
2
2
2
tHZWE
WE LOW to High Z[8, 9]
6
Notes:
7. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IorJIOH and 20-pF load capacitance.
8_ At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLzWE for any
given device.
9. tHzOE, tHZCE, and tHzWE are specified with a load capacitance of 5
pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
7
7
ns
10
ns
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal will terminate a write by going HIGH. The input data setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
11. The minimum write cycle time for Write Cycle No.3 (WE Controlled,
Vb LOW) is the sum of tHZWE and tSD.
2-358
·
·~PRKSS
.~
CY7B199
SEMITCONDUCTOR
Switching Waveforms
Read Cycle No. tl 12,13]
}=
1M
rLi~HA
ADDRESS-----....
DATA OUT
PREVIOUS DATA VAUD
II
IRe
1
3XXX*================DA=:r:=A=V=A=L=ID===========
6199-5
Read Cycle No. 2[13, 14]
)~
ADDRESS
tRC
~"
}~
tACE
,k
~,
tHZOE-
I
tDOE
-tHZCE-
-tLZOE-
HIGH IMPEDANCE
DATA I/O
tLZCE
1//////
DATA VALID
1'\..'\..'\..'\..""",
HIGH
'\ IMPEDANCE
/
_tpD
I---tpu
~
CC
I
50%
ISS
6199·6
Write Cycle No.1 (CE Controlled)[15, 16]
~--------------------------twc--------------------------~
ADDRESS
---+-------------'"'
141------- tSCE -----;~
,-----+------
~----------------------tAw------------------~~--
~---------tSD--------~
HIGH IMPEDANCE
DATA I/O - - - - - - - - - - - - - - - - - ( "
HIGH IMPEDANCE
DATAIN VALID
6199-7
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition Law.
15. Data I/O is HIGH impedance if OE = Vm.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-359
••
;!~PRE§
~_,
CY7B199
SEMICONDUcrOR
Switching Waveforms (continued)
Write Cycle No.2 (WE Controlled, OE HIGH During Write) [15, 16]
~-------------------------twc------------------------~
ADDRESS
______::::::~_t_S_A:~~_-_-_-~~~~~ ~~-------tpwE--------~ ,-___________________
14---------- tSD ----------......-~
DATAIN VALID
DATA I/O
8199-8
Write Cycle No.3 (WE Controlled, OE LOW)[ll, 16]
ADDRESS
/+-------
tSD
---------I~--.,
DATAIN VALID
DATA I/O
8199-9
Truth Table
CE
WE
OE
H
X
X
HighZ
Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (Icc)
L
L
X
Data In
Write
Active (Icc)
L
H
H
HighZ
Selected, Output Disabled
Active (Icc)
Input/Output
Mode
Notes:
17_ During this period, the I/Os are in the output state and input signals
should not be applied_
2-360
Power
D
·
~
CY7B199
;jE CYPRFSS
~.JF SEMICONDUcrOR
Ordering Information
Speed
(ns)
10
12
15
20
Ordering Code
Package
Name
Package 'JYpe
CY7B199-10PC
P21
28-Lead (300-Mil) Molded DIP
CY7B199-10VC
V21
28-Lead Molded SOJ
CY7B199-12DC
D22
28-Lead (300-Mil) CerDIP
Operating
Range
Commercial
Commercial
CY7B199-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7B199-12VC
V21
28-Lead Molded SOJ
CY7BI99-12DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B199-15DC
D22
28-Lead (300-Mil) CerDIP
Commercial
CY7B199-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7B199-15VC
V21
28-Lead Molded SOJ
CY7B199-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7B199-20DMB
D22
28-Lead (300-Mil) CerDIP
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
Parameter
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
VIR
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDOE
7, 8, 9, 10, 11
Icc
1,2,3
ISB
1,2,3
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8,9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00160-D
2-361
II
CY7C199
CYPRESS
SEMICONDUCTOR
32K x 8 Static RAM
Features
Functional Description
• High speed
- 12ns
The CY7C199 is a high-performance
CMOS static RAM organized as 32,768
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
(CE).and active LOW output enable (DE)
and three-state drivers. This device has an
automatic power-down feature, reducing
the power consumption by 81 % when deselected. The CY7C199 is in the standard
300-mil-wide DIP, SO] and LCC packages.
An active LOW write enable signal (WE)
controls the writing!readin~eration of
the memory. When CE and WE inputs are
both LOW, data on the eight data input/
output pins (1/00 through 1/07) is written
• Fast tDOE
• CMOS for optimum speed/power
• Low active power
- 880mW
• Low standby power
- 165mW
• Easy memory expansion with CE and
OE features
• TTL-compatible inputs and outputs
• Automatic power-down when
deselected
Logic Block Diagram
into the memory location addressed by the
address present on the address pins (Ao
through A14). Reading the device is accomplished byselectiI.!8.!he device and ~n
abling the ou~s, CE and OE actIve
LOW, while WE remains inactive or
HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless the chip is selected,
o~uts are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
Pin Configurations
DIP/SOJ
Top View
A5
As
A7
As
As
A10
An
A12
A13
A14
1/0 0
1/00
1/0 1
1/0 2
1/0 1
GND
1/0 2
1
2
3
4
9
10
11
12
13
14
Vee
28
27
26
25
24
23
22
21
20
19
18
17
16
15
wr:.
~
~
A2
A1
m:
Ao
CE
1/07
1/0 6
1/0 5
1/0 4
1/0 3
C199-2
LCC
1/0 3
Top View
.tif.'R~I~
1/04
~
~
A2
A1
As
As
AlO
A11
A12
A13
A14
1/0 5
1/0 6
1/07
m:
Ao
IT
1/07
1/0 6
1/0 0
1/0 1
C199-1
C199-3
g~~~g
Selection Guide
7C199-20
7C199-25
7C199-35
7C199-45
Maximum Access Time (ns)
20
25
35
45
Maximum 0l?erating
Current (mA)
150
150
140
170
150
150
150
30
30
25
25
Shaded area contains preliminary information.
2-362
--=-,~~PRESS
·
CY7C199
SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65 ° C to + 150 ° C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ....................... - O.5V to +7.OV
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
DC Voltage ApBlied to Outputs
in High Z State 1] . . . . . . . . . . . . . . . . . . - O.SV to Vee + O.5V
Military[2]
DC Input Voltagd 1] ................ - 0.5V to Vee + 0.5V
Output Current into Outputs (LOW) ............... 20 rnA
Electrical Characteristics Over the Operating Range[3]
7Cl~=-!2
Parameter
Description
~n.
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIR
Input HIGH Voltage
IIX
Input Load Current
GND~ VI~ Vee
loz
Output Leakage Current
GND~ Vo~ Vee,
Output Disabled
ISBl
ISB2
\>,
'!
OA~ij
2.2'
Input LOW Voltage
Icc
' !\fax. Min. MaL:
, 2.~
Vee
L
1::t5 \
-5
m.
Output Short Circuit
Current[4]
Vee = Max., VOUT = GND
Vee Operating Supply
Current
Vee = Max., lOUT = 0 rnA, Com'l
"'t"
f = fMAX = litRe
Mil
Automatic CE
Power-Down CurrentTTL Inputs
Max. Vee, CE ~ VIR,
VIN ~ VIR or VIN ~ VIL,
f= fMAX
Automatic CE
Power-Down CurrentCMOS Inputs
Max. Vee,
CE~ Vee - O.3V
VIN ~ Vee - O.3V
or VIN ~ 0.3V, f = 0
A,
"
1t·:
.vcd,
2.2
t
I"
\:
.
111':, l*:
"'\;
.1O
4.
2-363
~.,it
V
-0.5
0.8
V
-5
+5
+5
-5
+5
fAA
fAA
-300
rnA
:
150
rnA
18!}•.;
'''.'170
>-;3;?:
1~3:'
)0
30
30
rnA
15
rnA
;
,I,
>:jt ;'%,
Mil
Vee
+O.3V
+5 "
"\'.
1
2.2
V
I
',!:
,.,1,
?;t.30
V
'.';
II~ li'?!t 'dl.r i
":
Com'l
Shaded area con tams prehmmary mformatlOn.
Notes:
1. VIL(min.) = - 2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
-5~;,
y''-3~,
·t~ '.
0.4
iiQ.4 l
I,
"I:::-5~
I
4:5
,'I
Unit
2.4
II
-5"
Max.
Min.
:;:
2::4
f,\; t;0:3V· ~~~'\,. +O:3V'
1.,:-0:5' 0$ ;:2-t1;5: '~{~ "
VIL
los
7C199-20
'1C19?,-15
"~
w
:c.
"
<\10" ,
;
'15
I',
<
."
'.,~,
~;l5
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
I
~
~~PRESS
~, SEMICONDUCTOR
CY7C199
Electrical Characteristics Over the Operating Range[3] (continued)
7C199-25
Description
Parameter
Min.
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Min.
2.4
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GND~ VI~ Vee
loz
los
Output Leakage Current
GND ~ VI~ Vee, Output Disabled
Output Short
Circuit Currend 4]
Vee
Vee Operating Supply
Current
Vee = Max., lOUT = 0 rnA,
f = fMAX = litRe
ISBI
Automatic CE
Power-Down CurrentTIL Inputs
ISB2
Automatic CE
Power-Down CurrentCMOS Inputs
Icc
7C199-35,45
Max.
Max.
Unit
0.4
V
2.4
V
0.4
2.2
Vee
+O.3V
2.2
Vee
+O.3V
V
-3.0
0.8
-3.0
0.8
V
-5
+5
-5
+5
-5
+5
-5
+5
J.tA
J.tA
-300
-300
rnA
ICom'l
150
140
rnA
IMil
150
150
Max. Vee, CE~ VIR, VIN ~ VIR
orVIN ~ VIL, f = fMAX
30
25
rnA
Max. Vee, CE ~ Vee - O.3V
VIN ~ Vee - O.3V or VIN ~ 0.3v, f=O
15
15
rnA
= Max., VOUT =
GND
Capacitance[S]
Parameter
Description
Test Conditions
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
COUT
Output Capacitance
Vee = 5.0V
Max.
Unit
8
pF
8
pF
Note:
5. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms[6]
R1481Q
R1481Q
OUTP~~31
OUTPUT
5V31
30 pF
INCLUDING
JIG AND
SCOPE
R2
2550
I _
-
-
5pF
R2
2550
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
ALL INPUT PULSES
3.0V -----1r~---~
GND
_
C199-4
(b)
THEvENIN EQUIVALENT
1670
OUTPUT O'O---"J........_---oo 1.73V
Note:
6. tr.s 3 ns for the -12 and -15 speeds. tr.s 5 ns for the - 20 and slower
speeds.
2-364
C199-5
.
::~
_ ' j ; CYPRESS
- , SEMICONDUCTOR
CY7C199
Switching Characteristics Over the Operating Rangel 3, 7]
Description
Min.
7C199-20
7C199-15
7C199-12
Parameter
Max.
Min.
Min.
Max.
Max.
Unit
READ CYCLE
12
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
tDOE
OE LOW to Data Valid
5
tLZOE
OE LOW to Low Z[8]
tHzOE
OE HIGH to High Z[8, 9]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[8, 9]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
w,'
15
,:,1
.,
«p',
20
15
12
ns
20
ns
20
ns
,
3
3
3
,
;f
15
7
ns
9
ns
W'
;;,'
0
0
5
3
7
,;
3
,"
;
,
5
7
0
,
12
ns
9
ns
9
ns
3
\'
,:10
0
ns
0
n
15
)<);
ns
20
ns
WRITE CYCLE[lO, 11]
twc
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tpWE
WE Pulse Width
tSD
Data Set-Up to Write End
12
';,
9
\
0
ns
15
ns
16
15
ns
0
0
ns
,Ji;,O';;
0
ns
','
15
ns
;.)
10
ns
la,
,,'
.,'.
.,;
~9;
.,~
"
::
X,
t
;{~g;li
15
20
..
,"
,9
•
J;
",
9,;""
< 9 \.
"
tHD
Data Hold from Write End
tHZWE
WE LOW to High Z[9]
tLzWE
WE HIGH to Low Z[8]
-0
?;4".
"
$
,5';,
,;:
Ii:;
(J~i:~
17
"7,,,
.;iL
,;';;
,,', 3
"'
,';,
',>,
ns
0
';
10
3
ns
ns
Shaded area contains preliminary information.
Notes:
7.
8.
9.
Test conditions assume signal transition time of3 ns or less for -12 and
-15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
At any given temperature and voltage condition, tHzCE is less than
tLZCE, tHZOE is less than tLzOE, and tHzWE is less than tLzWE for any
given device.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 m V from steady-state
voltage.
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE Law. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE
LOW) is the sum of tHZWE and tSD.
2-365
II
·
7~PRESS
~,
CY7C199
SEMICONDUCTOR
Switching Characteristics Over the Operating Range[3, 7] (continued)
7C199-25
Parameter
Description
Min.
Max.
7C199-35
Min.
Max.
7C199-45
Min.
Max.
Unit
45
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
25
35
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[8]
tHZOE
OE HIGH to High Z[8, 9]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[8, 9]
tpu
CE LOW to Power-Up
tpD
CE HIGH to Power-Down
3
45
35
25
3
ns
3
ns
25
35
45
ns
10
16
16
ns
15
ns
3
3
11
3
3
11
0
ns
3
15
0
15
ns
ns
0
20
20
ns
3
15
25
ns
WRITE CYCLE 10, 11]
twc
Write Cycle Time
25
35
45
ns
tSCE
CE LOW to Write End
18
22
22
ns
tAW
Address Set-Up to Write End
20
30
40
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Adqress Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
18
22
22
ns
tSD
Data Set-Up to Write End
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z[9]
tLzwE
WE HIGH to Low Z[8]
11
3
15
3
15
3
ns
ns
Switching Waveforms
Read Cycle No.
ADDRESS
1[12, 13]
~
--~
DATA OUT
PREVIOUS DATA
tRC
1
tAA
v:: =lxx
*===============D=A=JA==VA=L=ID============
Notes:
12. Device is continuously selected. DE, CE = VIL.
13. WE is HIGH for read cycle.
2-366
*-
C199-6
·
,~PRESS
-iF
CY7C199
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No. 2[13, 14]
CE
II
tRC
~~
}'t
tACE
~~
DATA OUT
/1{
tDOE
14--- tLZOE HIGH IMPEDANCE
VCC
SUPPLY ____________
CURRENT
/////v
DATA VALID
"'\."'"
tLZCE
I---tpu
~
tHWE~
I+--tHZCE
~tpD
HIGH
IMPEDAN CE
~CC
I
50%
50%1'-IS8
C199·7
Write Cycle No.1 (WE Controlled)[lO, 15, 16]
~-------------------------twc------------------------~
ADDRESS
~------tpWE----------~
WE
----------------------~~~,
,---------------------
~---------tSD----------~~~tHD
DATAI/O
DATA-IN VALID
C199·8
Write Cycle No.2 (CE Controlled)[lO, 15, 16]
~--------------------------twc--------------------------~~
ADDRESS
-----+--------------------------~~~----tSCE------~ ,---------~----------
~---------------------~w---------------------.~---
~~~--------tSD-------.~
DATA I/O ------------------------------KKr---D-A-r-A--IN-V-A-L-ID----C199·9
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIR.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-367
.~
CY7C199
~CYPRESS
~;. SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[ll, 16]
ADDRESS
WE -------------P~~_
~------tSD------~--~
DATAI/O
DATA-IN VALID
C199-10
'tYPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
ffi 1.2
Icc
111.0
/"
Cl
~ O.B
:J
~ 0.6
~
V
1.4
CD
~
--
~ O.B
::J
~ 0.6
5.5
6.0
1.3
:::>
1=
ISB
25
125
w
W
N
:J
< 1.1
::2
«
0.9
O.B
4.0
4.5
::J
::2
TA = 25°C
-...........
5.0
II:
-----
5.5
SUPPLY VOLTAGE (V)
5
40
"
20
0
0.0
6.0
0
1.0
2.0
«'
140
5
120
5
~
/
BO
Z
60
1=
:::>
o
20
U5
~ 40
O.BI--------t--------l
0~575-------2~5~------~125
AMBIENT TEMPERATURE (0C)
2-368
'"
4.0
~
~ 100
1.0
3.0
jV
a:
z
'"
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
z
1.2
Vce = 5.0V
TA = 25°C
~
OUTPUT VOLTAGE (V)
I-
0
Cl 1.2
~
60
I-
j,1.4
'" ..............
~
a:
55
1.6
1.0
BO
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
N
z
~
:::>
u
AMBIENT TEMPERATURE (0C)
1.4
0
II:
II:
Vcc = 5.0V VIN = 5.0V
-55
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
II:
~
:::>
0.2
5.0
120
ij] 100
II:
0.0
1
I-
~ 0.4
SUPPLY VOLTAGE (V)
j.
~
U
ISB
4.5
Icc
I..........
.!:? 1.0
VIN = 5.0V
TA = 25°C
II:
0.0
4.0
1.2
o
~ 0.4
0.2
./
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
/
If
o
0.0
[7
Vcc = 5.0V
TA = 25°C
/
I
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
~::z.
CY7C199
~.CYPRESS
~, SEMICONDUCTOR
lYpical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
~
2 .5
0
rn
o 2.0
w
~ 20.0
N
::::i
a:::
0
z 1.0
0.5
0.0
0.0
---
1 .0
2.0
~
3.0
SUPPLY VOLTAGE
/
4.0
5.0
5.0
0.0
u
/
/
~ 15.0
w
o 10.0
1.5
~
.,--
25.0
.s
..E-
«
NORMALIZED Icc vs. CYCLE TIME
1.25 .-----,----~-----,
30.0
..9
fij1.00
N
::::i
~
/~
= 4.5V
TA = 25°C
Vee
/
1/
o
M
200
400
600
a:::
~ 0.751-----+----::;JIIC---+-----I
-
800 1000
20
CAPACITANCE (pF)
Truth Table
CE
WE
OE
H
X
X
HighZ
L
H
L
L
L
X
L
H
H
Inputs/Outputs
Power
Mode
DeselectlPower-Down
Standby (ISB)
Data Out
Read
Active (Icc)
Data In
Write
Active (Icc)
HighZ
Deselect, Output Disabled
Active (Icc)
Ordering Information
Speed
(ns)
1>7ns "
20
25
Ordering Code
C~'1C19.9t::: 15PQ
Package
Name
Operating
Range
Package 'JYpe
'. ,":1 P21
~·28±L.eadq3fXt.;.~~) Mo~ded~Dlf.
G'f7C199'~lSVC;~.V21.5~ 2~;"l:1-~d&Jol~a~OJ'>X
....
CflC199j';15D;:tyIB 1~~~D22Y 1 28:Jt,~ad{~~Mn)CerIlIP
~o~erci~.
o·
~::. ..;/....*
'/"i!!filita~
""jt
Q;'7C199;~ 15L:tyIBL54..
~.:fih ReC~Le~less{Jliip Camer
CY7C199-20PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C199-25PC
CY7C199-25VC
P21
V21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
~C~Y~7~C-19~9--~2~OV~C~--+--V~2~1--+-2-8-~L-e-ad~M~o~ld~ed~SO~J~----------~
;:'\.':t.
~C~Y"."7~C_19~9_-~2...."5D,,...,.....,M,,,..B__+-_D_2~2__+-2_8-___L-e-ad......(..:...3-00--_M_il.:..)_C_er_D_I_P______---.,-~ Military
35
45
CY7C199- 25LMB
CY7C199-35PC
CY7C199-35VC
CY7C199-35DMB
CY7C199- 35LMB
CY7C199-45DMB
CY7C199-45LMB
L54
P21
V21
D22
L54
D22
L54
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
Shaded area contains preliminary information.
2-369
30
CYCLE FREQUENCY (MHz)
Commercial
Military
Military
40
II
«
.~
~.a CYPRESS
~_.IF
CY7C199
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBI
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7,8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tORA
7,8,9, 10, 11
tACE
7, 8, 9, 10, 11
tOOE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tRA
7,8,9,10,11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7, 8, 9, 10, 11
Document #: 38-00239-A
2-370
CY7CIOOl
CY7CI002
PRELIMINARY
256K X 4 Static RAM
with Separate I/O
Features
Functional Description
• Highspeed
- tAA= 12ns
The CY7ClOOI and CY7ClO02 are highperformance CMOS static RAMs organized as 262,144 x 4 bits with separate I/O.
Easy memory expansion i~,£!,ovided by active LOW chip enable (CE) and threestate drivers. Both devices have an automatic power-down feature, reducing the
power consumption by more than 65%
when deselected.
Writing to the device is accomplished by
taking both chip enable (CE) and write enable (WE) inputs LOW. Data on the four
input pins (10 through 13) is written into the
memory location specified on the address
pins (Ao through A17)'
Reading the device is accomplished by taking chip enable (CE) LOW while write en-
• Transparent write (7C1001)
• CMOS for optimum speed/power
• Low active power
- 910mW
• Low standby power
- 275mW
• 2.0V data retention
- 100llW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
Logic Block Diagram
able (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the four data output pins (00
through 0 3).
The data output pins on the CY7CI001
and the CY7ClO02 are placed in a highimpedance state when the device is deselected (CE HIGH). The CY7CI002's outputs are also placed in a high::i!!Pedance
state during a write operation (CE and WE
LOW). In a write operation on the
CY7ClOOl, the output pins will carry the
same data as the inputs after a specified
delay.
The CY7CI00l and CY7ClO02 are available in standard 300-mil-wide DIPs and
SOJs.
Pin Configuration
10
DIP/SOJ
Top View
11
12
13
Ao
00
~
01
Ai,
O2
A7
A8
03
A5
Vee
A15
A3
Al
A2
A10
All
A12
A13
A14
As
13
Ao
Al
A2
NC
A16
A17
~
GND
~
~
A7
As
NC
10
11
12
13
14
15
16
23
22
21
20
19
18
17
10
30
01
02
~
WE
C1001-2
C1001-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current
Maximum Standby Current (rnA)
Commercial
Military
Commercial
Military
7C1001-12
7C1002-12
12
165
50
2-371
7C1001-15
7C1002-15
15
155
165
40
40
7C1001-20
7C1002-20
20
140
150
30
30
7C1001-25
7C1002-25
25
130
140
30
30
PRELIMINARY
CY7CIOOl
CY7CI002
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage on Vee Relative to GND[1]
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
- O.5V to +7.0V
Ambient
Temperature[2]
Vee
O°C to + 70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
DC Voltage ApBlied to Outputs
in High Z State 1] ................. - O.5V to Vee + 0.5V
DC Input Voltage[1] ............... - O.5V to Vee + O.5V
Commercial
Military
Current into Outputs (LOW) ..................... 20 rnA
Electrical Characteristics Over the Operating Rangd 3]
7CIOOl-12
7CIOO2-12
Parameter
Description
Test Conditions
Min.
VOH
Vee = Min.,
IOH = - 4.0 rnA
VOL
Output LOW
Voltage
Input HIGH
Voltage
Vee = Min:, IOL = 8.0 rnA
VIH
Input LOW
Voltagd 1]
VIL
IIX
Input Load Current GND~VI~Vee
Ioz
Output Leakage
Current
Vee,
Output Disabled
los
Output Short
Circuit Current[4]
lee
Vee Operating
Supply Current
Vee = Max.,
VOUT = GND
Vee = Max.,
lOUT = ornA,
f = fMAX = litRe
Com'l
Max. Vee,
Com'l
CE~VIH,
VIN ~ VIHor
VIN~VIL,
Mil
Automatic CE
Power-Down
Current
-TTL Inputs
ISB1
Max.
GND~ VI~
7CIOOl-20
7CIOO2-20
7CIOOl-25
7CIOO2-25
Min.
Min.
Min.
Max.
2.4
2.4
Output HIGH
Voltage
7CIOOl-15
7CIOO2-15
0.4
Max.
0.4
Max.
Unit
2.4
2.4
V
0.4
0.4
V
2.2
Vee
+0.3
2.2
Vee
+0.3
2.2
Vee
+0.3
2.2
Vee
+0.3
V
-0.3
0.8
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
-1
-5
+1
-1
+1
-1
+1
-1
+1
+5
-5
+5
-5
+5
-5
+5
fAA
fAA
-300
-300
-300
-300
rnA
165
155
140
130
rnA
165
150
140
40
30
30
40
30
30
2
2
2
2
2
2
Mil
50
rnA
f = fMAX
Automatic CE
Power-Down
Current
- CMOS Inputs
ISB2
Com'l
Max. Vee.
CE ~ Vee - 0.3v,
VIN ~ Vee - O.3V Mil
or VIN ~ 0.3Y, f=O
2
rnA
Capacitance[5]
Parameter
CIN: Addresses
Test Conditions
Description
Input Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
CiN: Controls
COUT
Output Capacitance
Max.
Unit
7
pF
10
pF
10
pF
Notes:
1. VIL (min.) = - 2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last oage ofthis soecification for GrollO A snhp'rol1n t",stinp' information.' _ .
• - -r -- 0- -
-
4.
5.
----0 ---
2-372
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or orocess chan!!es thllt mav l'Iff",r.t
these parameters.
-.
0
J
- -- - - -
CY7CIOOl
CY7CI002
PRELIMINARY
AC Test Loads and Waveforms
TI TI
R1480Q
OUTP~~
30 pF
INCLUDING
JIG AND
SCOPE
R2
I-
OUTP~~
5 pF
255Q
-
-
INCLUDING
JIG AND
SCOPE
I-
(a)
Equivalent to:
•
ALL INPUT PULSES
R1480Q
3.0V---90%
GND
R2
255Q
-
-
(b)
C1001-3
~3ns ~
CC
a:
C1001-4
THEVENIN EQUIVALENT
167Q
OUTPUT~
1.73V
Switching Characteristics Over the Operating Rangel3, 6]
Parameter
Description
READ CYCLE
Read Cycle Time
tRC
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
tpu
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
7ClOOl-12
7ClOO2-12
Min. Max.
12
7ClOOl-15
7ClOO2-l5
Min. Max.
15
12
3
20
15
12
15
CE HIGH to Power-Down
tpD
WRITE CYCLE[9]
15
12
25
10
ns
25
ns
0
20
ns
ns
3
8
ns
ns
3
0
0
Unit
ns
25
20
7
6
0
25
3
3
7ClOOl-25
7ClOO2-25
Min. Max.
20
3
3
3
7ClOOl-20
7ClOO2-20
Min. Max.
ns
twc
Write Cycle Time
12
15
20
25
ns
tSCE
CE LOW to Write End
10
12
15
20
ns
tAw
Address Set-Up to Write End
10
12
15
20
ns
tRA
Address Hold from Write End
0
0
0
0
ns
ns
tSA
Address Set-Up to Write Start
0
0
0
0
tpWE
WE Pulse Width
10
12
15
20
ns
tSD
Data Set-Up to Write End
7
8
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
3
3
3
3
tLZWE
WE HIGH to Low Z[7]
tHZWE
WE LOW to High Z[7, 8]
tDWE
WE LOW to Data Valid (7CI00l)
tDCE
CE LOW to Data Valid (7C1001)
tADY
Data Valid to Output Valid (7CI00l)
12
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHzWE is less than tLzWE for any given device.
8. tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 mV from
steady-state voltage.
9.
2-373
ns
7
8
12
15
20
25
ns
12
15
20
25
ns
15
20
25
ns
6
10
ns
The internal write time of the memory is defined by the overlap of CE
and WE LOW: CE and WE must be LOW to initiate a write, and the
transition of any of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
(J)
CY7CIOOI
CY7CI002
PRELIMINARY
Data Retention Characteristics Over the Operating Range
Commercial
Conditions[lO)
Description
Parameters
Vee for Retention Data
IeeDR
Data Retention Current
teDR(5)
Chip Deselect to Data Retention Time
tR(5)
Operation Recovery Time
Note:
10. No input may exceed Vee
Min.
Max.
2.0
VDR
Min.
Max.
Units
70
!lA
V
2.0
50
Vee = VDR = 2.0V,
CE~ Vee - 0.3V,
VIN ~ Vee - O.3Vor
VIN~O.3V
Military
0
0
ns
tRe
tRe
ns
+ O.SY.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
f~DR-
~~
Cl001-5
Switching Waveforms
Read Cycle No. tl ll , 12)
~v~: =lxx 1
tRC
ADDRESS
--~
DATA OUT
tAA
PREVIOUS DATA
*===============D=AT=A=V=A=L=ID===========
Cl001-6
Read Cycle No. 2[12, 13]
)K
ADDRESS
tRC
~,
~I{
tACE
I--tHZCE-
HIGH IMPEDANCE
DATA OUT
J
~"""""
tLZCE
~tpu
VCC _ _ _ _ _ _ _ _
SUPPLY
CURRENT
-
////JI'
50%
DATA VALID
HIGH
IMPEDAN CE
"'
I
~CC
50%'LISB
/
I-----tpD
Cl001-7
2-374
~
.
:;~
CYPRF.SS
PRELIMINARY
- , SEMICONDUCTOR
CY7CIOOI
CY7CI002
Switching Waveforms (continued)
•
Write Cycle No.1 (CE Controlled)[9, 14]
twc
tn
::liE
CC
tSCE
a:
(J)
tHA
tPWE
tSD
DATA IN
__________________________J
DATA VALID
DATA OUT __H_IG
__
H_IM_P_E_D_A_N_C_E________________~~------------------~--------~---------(7C1002)
DATA OUT
(7C1001)
-------------------------------+-------K:"";.......;~~......;:".
C1001-8
Write Cycle No.2 (WE Controlled)[9]
~-----------------------------twc----------------------------~
ADDRESS
~-----------------tSCE--------------------~
~----------------------~W------------------~~------tHA
DATA IN
DATA OUT
(7C1002)
DATA OUT
(7C1001)
\+-----
tADV --------~
C1001-9
Notes:
11. Device is continuously selected, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. If CE goes HIGH simultaneously with WE going HIGH, the output
remains in a high-impedance state (7C1002 only).
2-375
PRELIMINARY
Truth Thble
CE
WE
H
X
L
H
L
L
L
L
Power
Mode
00 - 03
HighZ
Power-Down
Standby (ISB)
Data Out
Read
Active (Icc)
HighZ
7ClO02: Standard Write
Input Tracking
7ClO01: Transparent
Writd 15 ]
Active (Icc)
Active (Icc)
Note:
15. Outputs track inputs after specified delay.
or d ermg
. I nIiormatIOn
Speed
(ns)
12
15
20
25
Speed
(ns)
12
15
20
25
Ordering Code
Package
Name
Package 1Ype
CY7C1001-12PC
P31
32-Lead (400-Mil) Molded DIP
CY7ClO01-12VC
V32
32-Lead (300-Mil) Molded SO]
Operating
Range
Commercial
CY7ClO01-15PC
P31
32-Lead (400-Mil) Molded DIP
CY7C1001-15VC
V32
32-Lead (300-Mil) Molded SO]
CY7ClO01-15DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7ClO01- 20PC
P31
32-Lead (400-Mil) Molded DIP
Commercial
CY7CIOOl- 20VC
V32
:32-Lead (300-Mil) Molded SO]
CY7C1001-20DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C1001-25DC
P31
32-Lead (400-Mil) Molded DIP
Commercial
CY7C1001-25VC
V32
32-Lead (300-Mil) Molded SO]
CY7C1001-25DMB
D32
32-Lead (300-Mil) CerDIP
Ordering Code
Package
Name
Package 1Ype
CY7ClO02-12PC
P31
32-Lead (400-Mil) Molded DIP
CY7ClO02-12VC
V32
32-Lead (300-Mil) Molded SO]
Commercial
Military
Operating
Range
Commercial
CY7C1002-15PC
P31
32-Lead (400-Mil) Molded DIP
CY7ClO02-15VC
V32
32-Lead (300-Mil) Molded SO]
CY7ClO02-15DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C1002-20PC
P31
32-Lead (400-Mil) Molded DIP
Commercial
CY7ClO02-20VC
V32
32-Lead (300-Mil) Molded SO]
CY7C1002- 20DMB
D32
32-Lead (300-Mil) CerDIP
Military
CY7C1002-25PC
P31
32-Lead (400-Mil) Molded DIP
Commercial
CY7C1002- 25VC
V32
32-Lead (300-Mil) Molded SO]
CY7ClO02- 25DMB
D32
32-Lead (300-Mil) CerDIP
2-376
Commercial
Military
CY7CIOOI
CY7CI002
·
-:!~
PRELIMINARY
= CYPRESS
===="
--::== F
CY7CIOOl
CY7CI002
SEMICONDUCfOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
I
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
hx
1,2,3
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
ISB2
1,2,3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
taRA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tRA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
tDWE[16]
7, 8, 9, 10, 11
tADV[16]
7, 8, 9, 10, 11
Note:
16. 7ClO01 only.
Document #: 38-00200-A
2-377
CY7CI006
PRELIMINARY
256K X 4 Static RAM
Features
Functional Description
• High speed
- tAA= 12ns
The CY7ClO06 is a high-performance
CMOS static RAM organized as 262,144
words by 4 bits. Easy memory expansion is
provided by an active LOW chip enable
(CE), an active LOW output enable (OE),
and three-state drivers. The device has an
automatic power-down feature that reduces power consumption by more than
65% when deselected.
• CMOS for optimum speed/power
• Low active power
- 910mW
• Low standby power
- 275mW
• 2.0V data retention
- lOOIlW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
Reading from the device is accomplished
by taki!!g chip enable (CE) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the
contents of the memory location specified
by the address pins will appear on the four
I/O pins.
The four input/output pins (1/00 through
1/03) are placed in a high-impedance state
when the device is deselect~CE HIGH),
the outputs are disabled (OE HIGH), or
during a write operation (CE and WE
LOW).
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the four I/O
pins (1/00 through 1/03) is then written
into the location specified on the address
pins (Ao through A17).
The CY7CI006 is available in standard
300-mil-wide DIPs and SOJs.
Pin Configuration
Logic Block Diagram
DIP/SOJ
Top View
Ao
Vee
~
A17
A16
A1S
A14
A13
A12
A11
A1
A2
A3
As
6
As
A7
A1
A2
A3
~
~
A7
A8
Ag
As
As
a:
~
1/0 3
w
OE
0
0
()
W
GND
1/°2
NC
9
10
11
12
13
14
19
18
17
16
15
0
1/°3
1/02
1/°1
~
C1006-2
;:
1/°1
0
a:
1/00
CE
WE
OE
C1006-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Commercial
7CIOO6-12
7CIOO6-15
7CIOO6-20
12
15
20
25
165
155
140
130
165
150
140
40
30
30
40
30
30
Military
Maximum Standby Current (rnA)
Commercial
-_
....
MIlItary
50
2-378
7CIOO6-25
PRELIMINARY
CY7CI006
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65 ° C to + 150° C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage on Vee Relative to GND[1]
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
- O.5V to + 7.0V
Ambient
Temperature[2]
Vee
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
DC Voltage Apglied to Outputs
in High Z State 1] ................. - 0.5V to Vee + 0.5V
DC Input Voltagel 1] ............... - O.5V to Vee + 0.5V
Current into Outputs (LOW) ..................... 20 rnA
Commercial
Military
Electrical Characteristics Over the Operating Rangel3]
Parameter
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
VOH
VOL
VIH
7CIOO6-12
7CIOO6-15
7CIOO6-20
7CIOO6-25
Test Conditions
Min.
Min.
Min.
Min.
Vee = Min.,
IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
2.4
VIL
Input LOW
Voltagel 1]
IIX
InputLoad Current GNDs VIS Vee
GNDs VIS Vee,
Output Disabled
Output Short
Vee = Max.,
Circuit Current[4]
VOUT = GND
Vee Operating
Com'l
Vee = Max.,
Supply Current
lOUT = ornA,
f = fMAX = litRe Mil
los
lee
ISBl
ISB2
Automatic CE
Power-Down
Current
-TTL Inputs
Max. Vee,
CELVIH,
VINL VIHor
VINS VIL,
f= fMAX
Automatic CE
Power-Down
Current
- CMOS Inputs
Com'l
Max. Vee,
CE L Vee - 0.3v,
VINL Vee - 0.3V Mil
orVINsO.3V,f=O
Max.
Max.
2.4
2.4
0.4
Output Leakage
Current
loz
Max.
Unit
V
2.4
0.4
0.4
Max.
0.4
V
2.2
Vee
+ 0.3
2.2
Vee
+ 0.3
2.2
Vee
+ 0.3
2.2
Vee
+ 0.3
V
- 0.3
0.8
- 0.3
0.8
- 0.3
0.8
- 0.3
0.8
V
-1
+1
-1
+1
-1
+1
- 1
+1
f,lA
-5
+5
-5
+5
-5
+5
-5
+5
[lA
-300
165
Com'l
50
Mil
2
-300
-300
-300
rnA
rnA
155
140
130
165
150
140
40
30
30
40
30
30
2
2
2
2
2
2
rnA
rnA
Capacitance[5]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN: Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Max.
Unit
7
pF
10
pF
10
pF
Notes:
1.
2.
3.
VIL (min.) = - 2.0V for pulse durations of less than 20 ns.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
4.
5.
2-379
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
II
PRELIMINARY
TI TI
CY7CI006
AC Test Loads and Waveforms
R1480Q
OUTP~~
30 pF
R2
I
OUTP~~
5 pF
255Q
~78~~~NG -=
ALL INPUT PULSES
R1480Q
I
~78~~~NG -=
-=
SCOPE
3.0V---90%
R2
GND
255Q
-=
SCOPE
(b)
(a)
Equivalent to:
C1OO6-3
C1006-4
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics Over the Operating Rangef3, 6]
Parameter
Description
7CIOO6-12
7CIOO6-15
7CIOO6-20
7CIOO6-25
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to' Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
12
15
20
25
ns
tDOE
OE LOW to Data Valid
6
7
8
10
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7, 8]
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[7, 8]
tpu
CE LOW to Power-Up
12
15
12
3
20
3
0
3
0
3
3
6
0
0
CE HIGH to Power-Down
tpD
WRITE CYCLE[9, 10]
12
8
20
ns
ns
10
0
0
15
ns
10
3
3
ns
ns
0
8
7
ns
25
3
0
7
6
25
20
15
ns
ns
25
ns
twc
Write Cycle Time
12
15
20
25
ns
tSCE
CE LOW to Write End
10
12
15
20
ns
tAW
Address Set-Up to Write End
10
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
ns
tSD
Data Set-Up to Write End
7
8
10
15
ns
ns
tHD
Data Hold from Write End
0
0
0
0
tLZWE
WE HIGH to Low Z[8]
3
3
3
3
tHZWE
WE LOW to High Z[7, 8]
6
Notes:
6. Jest conditions assume signal transition time of3 ns or less, timing reference levels of l.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. tHzOE, tHZCE, and tHzWE are specified with a load capacitance of 5 pF
as in part (b) of AC Test Loads. 1fansition is measured ±SOO m V from
steady-state voltage.
8. At any given temperature and voltage condition, tHzCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
9.
7
8
ns
10
ns
The internal write time of the memory is defined by the overlap of CE
and WE Law. CE and WE must be LOW to initiate a write, and the
transition of either of these signals can terminate the write. The input
data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE LOW) is the sum of tHZWE and tSD'
2-380
PRELIMINARY
CY7CI006
Data Retention Characteristics Over the Operating Range
Commercial
Parameter
Conditions [11]
Description
Min.
V cc for Data Retention
VDR
2.0
ICCDR
Data Retention Current
tCDR[5]
Chip Deselect to Data Retention Time
YC.c = VDR = 2.0V,
CE L Vcc - 0.3V,
VIN L Vcc - O.3Vor
tR[5]
Operation Recovery Time
VIN~O.3V
Notes:
11. No input may exceed Vee
Max.
Military
Min.
Max.
Unit
2.0
V
50
70
!1A
0
0
ns
tRC
tRC
ns
+ O.SY.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR~2V
f~DRC1006-5
Switching Waveforms
Read Cycle No. 1[12,13]
~V:~~~ =lxx 1
*-
tRC
ADDRESS
--~
DATA OUT
tAA
PREVIOUS DATA
*===============D=A=I=A=V=A=L=ID===========
C1006-6
Read Cycle No.2 (OE Controlled)[13, 14]
)(
ADDRESS
tRC
~,
}~
tACE
~I'\.
;1{:
t~ZOE
tDOE
:.-tHZCE-
~tLZOE-
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
1//////
tLZCE
~""",,'\.
_tpu
..J..
DATA VALID
"
HIGH
IMPEDANC E
/
-tpD-
50%'\
{50%
-
ICC
'------
ISB
C1006-7
2-381
II
PRELIMINARY
CY7CI006
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[15, 16]
~--------------------------twc----------------------------~
ADDRESS
---~--------------------------~ ~------tSCE------~ ~--------_+-----------
..~--
~-----------------------~w----------------------
~1:~--------tSD-------'~
DATA I/O
---------------~~...-----D-A-:r-A-V-A-L-ID----C1006-8
Write Cycle No.2 (WE Controlled, OE HIGH During Write) [15, 16]
~--------------------------twc--------------------------~
ADDRESS
~~~~~~~-----------------tSCE------------------~
~--------------------~w-----------------------.~--1 4 - - - - tSA - - - - - - . I
~-------tpwE----------~
-------------------~~~
,------------------
1+---------- tSD -----------.....--.-.1 tHD
DATAI/O
DATA VALID
C1006-9
Notes:
12. Device is continuously selected, OE and CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. IfCEgoes HIGH simultaneouslywith WE going HIGH, the output remains in a high-impedance state.
16. Data I/O is high impedance if OE = VIH.
2-382
-===-a...
.
-:!~
CYPRF.SS
iF
PRELIMINARY
CY7CI006
SEMICONDUCIDR
Switching Waveforms
•
Write Cycle No.3 (WE Controlled, OE LOW)[lO, 16]
ADDRESS
U)
:E
CC
a:
(J)
~------tSD------~'-~
DATA I/O
DATA VALID
C1006-10
Truth Table
1/00 -1/0 3
Power
CE
OE
WE
H
X
X
HighZ
Power-Down
Standby (ISB)
L
Active (Icc)
Mode
L
H
Data Out
Read
L
X
L
Data In
Write
Active (Icc)
L
H
H
HighZ
Selected, Outputs Disabled
Active (Icc)
2-383
PRELIMINARY
or d
.
erll1~~
I norma
ti
f Ion
Speed
(ns)
12
15
20
25
Ordering Code
Package
Name
Package 1Ype
Operating
Range
CY7C1006-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7C1006-12VC
V21
28-Lead Molded SO]
Commercial
CY7C1006-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C1006-15VC
V21
28-Lead Molded SO]
CY7C1006-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C1006- 20PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C1006- 20VC
V21
28-Lead Molded SO]
CY7C1006- 20DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C1006-25PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C1006- 25VC
V21
28-Lead Molded SO]
CY7C1006-25DMB
D22
28-Lead (300-Mil) CerDIP
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
Parameter
Subgroups
READ CYCLE
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIR
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tORA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
Ioz
1,2,3
Icc
1,2,3
ISBl
1,2,3
twc
7, 8, 9, 10, 11
ISB2
1,2,3
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tRA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
WRITE CYCLE
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00201-A
2-384
CY7CI006
PRELIMINARY
CY7CI007
1M X 1 Static RAM
Features
Functional Description
• High speed
- tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
- 825mW
• Low standby power
- 275mW
• 2.0V data retention
- 100 flW
• Automatic power-down when
deselected
• TTL-compatible inputs and outputs
The CY7ClO07 is a high-performance
CMOS static RAM organized as
1,048,576 words by 1 bit. Easy memory
expansion is ~vided by an active LOW
chip enable (CE) and three-state drivers.
The device has an automatic power-down
feature that reduces power consumption
by more than 65% when deselected.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location
specified on the address pins (Ao through
A19).
Reading from the device is accomplished
by taking chip enable (CE) LOW while
write enable (WE) remains HIGH. Under these conditions, the contents of the
memory location specified by the address
pins will appear on the data output
(DOUT) pin.
The output pin (DOUT) is placed in a
high-impedance state when the device is
deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7ClO07 is available in standard
300-mil-wide DIPs and SOJs.
Pin Configuration
Logic Block Diagram
DlP/SOJ
Top View
A10
A11
A12
A 13
A14
A15
NC
A16
A17
Ala
A19
DOUT
DOUT
WE
GND
vee
A9
Aa
A7
As
A5
~
A3
A2
Al
AD
DIN
CE
1007-2
'--Jt"-1--
WE
1007-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
Commercial
Military
Commercial
Military
7CI007-12
12
150
50
2-385
7CI007-15
15
135
145
40
40
7CI007-20
20
125
135
30
30
7CI007-25
25
120
130
30
30
II
en
:E
c(
a:
(J)
PRELIMINARY
CY7CI007
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ........... ,...... - 65 ° C to + 150 ° C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage on Vee Relative to GND[1] - O.5V to + 7.OV
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature[2]
Vee
O°Cto +70°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Range
DC Voltage ApBlied to Outputs
in High Z State 1] ................. - 0.5V to Vee + O.5V
DC Input Voltagd1] ............... - 0.5V to Vee + O.5V
Current into Outputs (LOW) ..................... 20 rnA
Commercial
Military
Electrical Characteristics[3] Over the Operating Range
7CIOO7-12
Parameter
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
VOH
VOL
VIH
VIL
Input LOW
Voltage[1]
IIX
Input Load
Current
Output Leakage
Current
Output Short
CircuitCurrentf4]
Vee Operating
Supply Current
loz
los
lee
Automatic CE
Power-Down
Current
- TTL Inputs
ISBl
Automatic CE
Power-Down
Current
- CMOS Inputs
ISB2
Test Conditions
Min.
Vee = Min., 10H = - 4.0 rnA
2.4
Max.
2.2
- 0.3
GNDsVIsVee
-1
GND S VIS Vee.
Output Disabled
-5
Vee = Max., VOUT = GND
Max.. Vee,
CE~ VIH,
Com'l
VIN~VIHor
VINS VIL,
f = fMAX
7CIOO7-25
Min.
2.2
Max.
0.4
2.2
Max.
2.4
2.4
0.4
2.2
Unit
V
0.4
V
V
V
- 0.3
Vee
+ 0.3
0.8
- 0.3
Vee
+ 0.3
0.8
+1
-1
+1
-1
+1
itA
+5
-5
+5
-5
+5
ItA
- 0.3
Vee
+ 0.3
0.8
+1
-1
+5
-5
-300
- 300
- 300
- 300
rnA
150
135
125
120
rnA
145
135
130
40
30
30
40
30
30
2
2
2
2
2
2
Mil
50
Mil
Com'l
Max. Vee,
CE~ Vee - 0.3v,
VIN~ Vee- O.3Vor Mil
VIN S 0.3v, f=O
Max.
2.4
Vee
+ 0.3
0.8
Com'l
7CIOO7-20
Min.
0.4
Vee = Min., 10L = 8.0 rnA
Vee = Max.,
lOUT = OrnA,
f = fMAX = litRe
7CIOO7-15
Min.
2
rnA
rnA
Capacitance[5]
Parameter
CIN: Addresses
CIN: Controls
COUT
Test Conditions
Description
Input Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Notes:
1. VIL (min.) = - 2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
-
4.
5.
2-386
Max.
Unit
7
pF
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
~
. -:;~
PRELIMINARY
'~ONDucrOR
CY7CI007
AC Test Loads and Waveforms
rIA11 ~ OUTP~:PF rIAl A2
OUTP:;':pF
255Q
INCLUDING _
JIG AND
SCOPE
(a)
Equivalent to:
----_11------,.,....
II
GND
255Q
INCLUDING _
JIG AND
SCOPE
(b)
_
-
ALL INPUT PULSES
3.0V
_
-
1007-4
1007-3
THEVENIN EQUIVALENT
167Q
..f\J
..'\,o---oo 1.73V
OUTPUT 0-0- - - - "
Switching Characteristics[3, 6] Over the Operating Range
7CIOO7-12
Parameter
Description
Min.
Max.
7CIOO7-15
7CIOO7-20
Min.
Min.
Max.
Max.
7CIOO7-25
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7,8]
tpu
CE LOW to Power-Up
12
15
20
15
12
3
3
3
3
6
20
3
7
0
0
CE HIGH to Power-Down
tpD
WRITE CYCLE[9]
12
25
3
3
15
12
0
ns
ns
10
ns
ns
ns
0
20
ns
25
3
8
15
ns
25
20
25
ns
twc
Write Cycle Time
12
15
20
25
ns
tSCE
CE LOW to Write End
10
12
15
20
ns
tAW
Address Set-Up to Write End
10
12
15
20
ns
tRA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpwE
WE Pulse Width
10
12
15
20
ns
tSD
Data Set-Up to Write End
7
8
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
3
tHZWE
WE LOW to High Z[7, 8]
6
Notes:
6. Test conditions assume signal transition time of3 ns or less, timing reference levels of L5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±SOO mV from
steady-state voltage.
9.
2-387
7
8
ns
10
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and
the transition of any of these signals can terminate the write. The input
data set~up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
PRELIMINARY
CY7CI007
Data Retention Characteristics Over the Operating Range
Commercial
Parameter
Conditions[lO]
Description
VOR
Vee for Data Retention
IeeoR
Data Retention Current
teoR[5]
Chip Deselect to Data Retention Time
tR[5)
Operation Recovery Time
Note:
10. No input may exceed Vee
Min.
Max.
2.0
Yc.e = VOR = 2.0Y,
CE~ Vee - 0.3Y,
VIN ~ Vee - O.3Vor
VIN .sO.3V
Military
Min.
Max.
Unit
70
fAA
2.0
50
V
0
0
ns
tRe
tRe
ns
+ 0.sY.
Data Retention Waveform
DATA RETENTION MODE
Vee
4.5V
VDR~2V
f~DR-
~w
1007-5
Switching Waveforms
Read Cycle No. 1[11, 12]
F=
,§~HA 1M
*-
IRe
I
PREVIOUS DATA VALID 3SSS*===============D=A=TA==VA=L=ID==========~~
ADDRESS _____....
DATA OUT
1007-6
Read Cycle No. 2[12, 13]
ADDRESS
~-----------------------tRe----------------------~,--------------
~--------~eE----------~
~----t~eE------~
HIGH IMPEDANCE
DATAOUT-----+----------------~~~~
Vee
SUPPLY
CURRENT
DATA VALID
HIGH
IMPEDANCE
,-------------------------------------------~+-----ICC
-----+---------'
50%
IS8
1007-7
Notes:
11. Device is continuously selected, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
2-388
~--...
.
-:;,~
PRELIMINARY
'~ucrOR
CY7CI007
Switching Waveforms (continued)
•
Write Cycle No.1 (CE Controlled)[14]
~-------------------------twc------------------------~
ADDRESS
------......- - - - - - - - - - tSCE
-----~
~--------------~------~W------------------~~~~~~~~~
100II1------------- tPWE
------------------~
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
1007-8
Write Cycle No.2 (WE Controlled)[14]
~-------------------------twc--------------------------~
ADDRESS
~---------------tSCE--------------------~
~----------------------~W------------------~~--
_ _ _~':.:.:.:::::_t_SA_-.:--------------....."f!:.+-O::~~
.
i00i1---- tPWE - - - - - . ! ,.._ _ _ _ _ _ _ _ __
~4-------tSD------~~
DATA IN --------------------------~
DATA VALID
tHZWE
:::l
--J)
DATA OUT _ _ _ _ _ _ _ _ _
D_AT_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _
'<,.---------
tLZWE ---..j
HIGH IMPEDANCE
1007-9
Note:
14. IfCEgoes HIGH simultaneously with WE going HIGH, theoutputremains in a high-impedance state.
Truth Table
CE
WE
H
X
HighZ
Power-Down
L
H
Data Out
Read
Active (Icc)
L
L
HighZ
Write
Active (Icd
DOUT
Mode
Power
Standby (ISB)
2-389
PRELIMINARY
Ordering Information
Speed
(ns)
12
15
20
25
Ordering Code
Package
Name
Package 'lYPe
CY7C1007-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7C1007 -12VC
V21
28-Lead Molded SO]
Operating
Range
Commercial
CY7C1007-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C1007-15VC
V21
28-Lead Molded SO]
Commercial
CY7C1007-15DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C1007 - 20PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C1007-20VC
V21
28-Lead Molded SO]
CY7C1007-20DMB
D22
28-Lead (300-Mil) CerDIP
Military
CY7C1007 - 25PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C1007 - 25VC
V21
28-Lead Molded SO]
CY7C1007-25DMB
D22
28-Lead (300-Mil) CerDIP
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIR
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
Parameter
Subgroups
READ CYCLE
IIx
1,2,3
Ioz
1,2,3
Icc
1,2,3
twc
7, 8, 9, 10, 11
ISB!
1,2,3
tSCE
7, 8, 9, 10, 11
ISB2
1,2,3
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
WRITE CYCLE
Document #: 38-00198-A
2-390
CY7CI007
-~
~
is CYPRESS
,
SEMICONDUCTOR
PRELIMINARY
~~;.~"~G.
128K X 8 Static RAM
Features
Functional Description
• High speed
tAA = 12 ns
• CMOS for optimum speed/power
The CY7ClO09 is a high-performance
CMOS static RAM organized as 131,072
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
(CEl), an active HIGH chip ena~CE2),
an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down feature that reduces
power consumption by more than 75%
when deselected.
Writing to the device is accomplished by
taking~ enable one (CEl) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the eight
I/O pins (1/00 through 1/07) is then written
into the location specified on the address
pins (Ao through Al6)'
• Low active power
- 1020mW
• Low standby power
- 250mW
• 2.0V data retention
- 100/-lW
• Available in 450 x 550-mil LCC
• Automatic power-down when
deselected
• Easy mem~ expansion with CEt.
CE2, and OE options
CY7CI009
Logic Block Diagram
Reading from the device is accomplished
by taking ch~nable one (eEl) and output enab~OE) LOW while forcing write
enable (WE) and chip enable two (CE2)
HIGH. Under these conditions, the contents of the memory location specified by
the address pins will appear on the I/O
pins.
The eight input/output pins (1/00 through
1/07) are placed in a high-impedance state
whenthe device is deselected (CEl HIGH
or CE2 LOW), the outputs are disabled
(OE HIGH), or during a wri~eration
(CEl LOW, CE2 HIGH, and WE LOW).
The CY7ClO09 is available in standard
300-mil-wide DIPs, SOls and a small footprint 450 x 550-milleadless chip carrier.
Pin Configurations
DIP/SOJ
Top View
LCC
Top View
; i 1~ >8 .fl~r
Vee
1/0 0
1/0 1
Ao
A16
A14
A12
A7
As
A5
A1
A2
A3
1/02
~
1/0 3
~
A3
A2
A1
Ao
A5
As
1/04
A7
As
1/0 5
6
7
1/0 0
1/0 1
1/0 2
GND
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A15
CE 2
WE
A13
As
As
An
m:
A7
5
As
6
A5
~
A3
A2
A1
7
A10
Ao
CE1
1/00
1/0 7
1/0 6
1/0 5
1/04
1/0 3
8
9
10
11
12
13
21
14151617181920
1009-3
1009-2
1/0 6
CE1
CE2
1/07
WE
1009-1
m:
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Maximum Standby Current (rnA)
Commercial
Military
Commercial
Military
7CI009-12
12
185
45
2-391
7CI009-15
15
170
180
40
40
7CI009-20
20
155
170
30
30
7CI009-25
25
145
160
30
30
•
PRELIMINARY
CY7CI009
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage on Vee to Relative GND[l] . - O.5V to + 7.0V
DC Voltage ApBlied to Outputs
in High Z State 1] .................. - O.5V to Vee + O.5V
DC Input Voltage[1) ................ - O.5V to Vee + O.5V
Current into Outputs (LOW) ...................... 20 rnA
Eh~ctrical
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
VOL
VIR
VIL
Input LOW
Voltagef1]
IIX
Input Load
Current
Output Leakage
Current
Output Short
CircuitCurrent[4]
Vee Operating
Supply Current
loz
los
lee
ISB1
ISB2
Operating Range
Ambient
Temperature[2]
Vee
O°C to +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Range
Commercial
Military
Characteristics Over the Operating Rangef3]
Parameter
VOH
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
7CIOO9-12
7CIOO9-15
7CI009-20
7ClOO9-25
Test Conditions
Min.
Min.
Min.
Min.
Vee = Min., IOH = - 4.0 rnA
2.4
2.2
Vee
GND~ VI~ Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee = Max.,
lOUT = ornA,
f = fMAX = l/tRe
-0.3
Vee
+ 0.3
0.8
-1
-5
Com'l
Max.
2.2
Max.
2.4
0.4
0.4
2.2
Max.
2.4
2.4
0.4
Vee = Min., IOL = 8.0 rnA
GND~ VI~
Max.
2.2
Unit
V
0.4
V
V
-0.3
Vee
+ 0.3
0.8
-0.3
Vee
+ 0.3
0.8
+1
-1
+1
-1
+1
IlA
+5
-5
+5
-5
+5
IlA
-0.3
Vee
+ 0.3
0.8
+1
-1
+5
-5
V
-300
-300
-300
-300
rnA
185
170
155
145
rnA
180
170
160
40
30
30
40
30
30
2
2
2
2
2
2
Mil
Automatic CE
Power-Down
Current
-TTL Inputs
Max. V eo CE1~ VIR Com'l
or CE2~ VIL,
VIN~ VIR or
Mil
VIN ~ VIL, f = fMAX
45
Automatic CE
Power-Down
Current
- CMOS Inputs
Max. Vee,
CE1 ~ Vee - 0.3V,
or CE2 ~ 0.3V,
VIN ~ Vee - 0.3v,
or VIN ~ 0.3V, f=O
Com'l
2
Mil
rnA
rnA
Capacitance[5]
Parameter
CIN: Address
CIN: Controls
COUT
Test Conditions
Description
Input Capacitance
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
Notes:
1. VIdmin.) = -2.0V for pulse durations of less than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing
information.
4.
5.
2-392
Max.
Unit
7
pF
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
.
-:;~
PRELIMINARY
'~~NDucrOR
CY7CI009
AC Test Loads and Waveforms
R1 480Q
OUTP~~ ~
,~~.~~F1
J 1
_
INCLUDING
JIG AND
SCOPE
-
R1 480Q
R2
255Q
-
OUTP~~ ~
,~,.~~F1
J 1
_
INCLUDING
JIG AND
SCOPE
R2
255Q
GND
-
(b)
(a)
Equivalent to:
-
•
ALL INPUT PULSES
3.0V----
1009-4
1009-5
THEVENIN EQUIVALENT
OUTPUT
167Q
o--------vw---o
Switching Characteristics[3, 6]
Parameter
1.73V
Over the Operating Range
Description
7CIOO9-12
7CIOO9-15
7C1009-20
7CIOO9-25
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
12
15
12
20
15
3
3
25
20
3
ns
25
3
tACE
CEl LOW to Data Valid, CE2 HIGH to Data Valid
12
15
20
25
tDOE
OE LOW to Data Valid
6
7
8
10
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7, 8]
0
0
6
tLZCE
CEl LOW to Low Z, CE2 HIGH to Low Z[8]
tHZCE
CEl HIGH to High Z, CE2 LOW to High Z[7, 8]
tpu
CEl LOW to Power-Up, CE2 HIGH to Power-Up
7
3
3
0
12
CEl HIGH to Power-Down,
CE2 LOW to PowerDown
WRITE CYCLE[9, 10]
tpD
8
10
8
15
20
ns
ns
ns
10
ns
25
ns
ns
0
0
ns
ns
3
3
7
6
0
0
0
ns
ns
twc
Write Cycle Time
12
15
20
25
ns
tSCE
CEl LOW to Write End, CE2 HIGH to Write End
10
12
15
20
ns
tAW
Address Set-Up to Write End
10
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tpWE
WE Pulse Width
10
12
15
20
ns
tSD
Data Set-Up to Write End
7
8
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
3
3
3
3
tHZWE
WE LOW to High Z[7, 8]
6
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOlJIOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5
pF as in part (b) of AC Test Loads. Transition is measured ± 500 m V
from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
7
8
ns
10
ns
The internal write time of the memo~ defined by the overlap of CEl
LOW, CEz HIGH, and WE LOW. CEl and WE must be LOW and
CEz HIGH to initiate a write, and the transition of any ofthese signals
can terminate the write. The input data set-up and hold timing should
be referenced to the leading edge of the signal that terminates the
write.
10. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE LOW) is the sum of tHZWE and tso.
9.
2-393
==--.
-~~
CYPRESS
CY7CI009
PRELIMINARY
_ , SEMICONDUCTOR
Data Retention Characteristics Over the Operating Range
Commercial
Parameter
Conditions[ll]
Description
VDR
IeeDR
Data Retention Current
teDR[S]
Chip Deselect to Data Retention Time
tR[S]
Operation Recovery Time
11. No input may exceed Vee
:f=
+ O.SY.
_
?ZZZZZZ#
:~
4.5V
~DR
DATA RETENTION MODE
VDR ~ 2V
Military
Min.
Max.
2.0
Unit
V
50
Yc.e =VDR = 2.0V,
CE1;;::: Vee - O.3Vor
CE2~ 0.3V,
VIN;;::: Vee - O.3Vor
VIN~O.3V
Data Retention Waveform
vcc
Max.
2.0
Vee for Data Retention
Note:
Min.
70
f.tA
0
0
ns
tRe
tRe
ns
~
_
4.5V
~~
~//._,
-
Switching Waveforms
Read Cycle No. 1[12, 13]
ADDRESS
}=
------li
DATA OUT
*-
~c
to".
PREVIOUS DATA VALID
~
I
3XXX*================D_A-I=A=V=A=L=ID==========~_
1009-7
Read Cycle No.2 (OE Controlled)[13, 14]
)(
ADDRESS
tRC
~~
)~
--.J~
~~
tACE
~,
DATA OUT
:;I?
tDOE
-tLZOEHIGH IMPEDANCE
/////v
VCC
SUPPLY
CURRENT
I+--tpu
i+-tHZCE - DATA VALID
''''''''\~
tLZCE
"'
HIGH
IMPEDANC E
/
~tpD-
l.
;f'
tfZOE
50%~
50%
-
ICC
'-- ISS
1009-8
Notes;
12. Device is continuously selected. OE, CEI
13. WE is HIGH for read cycle.
= VIL, CE2 = VIR.
14. Address valid prior to or coincident with CEI transition LOW and
CE2 transition HIGH.
2-394
~~
=.=CYPRESS
-iF
PRELIMINARY
CY7CI009
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1 (CEI or CE2 Controlled)[15, 16]
II
~--------------------------twc--------------------------~~
ADDRESS
-----+--------------------------~~~----tSCE------~,_--------~----------
~-----------tSA----------~,_--------------~
----+--------------------------"" ~I------- tSCE -------i~ ,----------1---------~--------------------~w----------------------~-~------------tpWE------------~
~r:~--------~D--------~
DATA I/O
-------------------------------(~_----D-A-JA-V-AL-I-D------
:11---------1009-9
Write Cycle No.2 (WE Controlled, OE HIGH During Write)[15, 16]
~-------------------------twc------------------------~
ADDRESS
~------
-----------------~~~~
tpwE
----------~
,----------------
~---------tSD----------~--~
DATA I/O
DATAIN VALID
1009-10
Notes:
15. Data I/O is high impedance if OE = VIH.
16. If CEI goes HIGH or CE2 goes LOW simultaneously with WE going
HIGH, the output remains in a high-impedance state.
2-395
~
irr~UCTOR
PRELIMINARY
CY7CI009
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW) [10, 16]
ADDRESS
1 4 - - - - t 80 ----..-~
DATA I/O
DATA VALID
1009-11
Truth Table
CE1
CE2
OE
WE
H
X
X
X
HighZ
Power-Down
X
L
X
X
HighZ
Power-Down
Standby (ISB)
L
H
L
H
Data Out
Read
Active (Icc)
L
H
X
L
Data In
Write
Active (Icc)
L
H
H
H
HighZ
Selected, Outputs Disabled
Active (Icc)
Mode
1/00 - 1/07
Power
Standby (ISB)
2-396
¥~CYPRFSS
·
,
PRELIMINARY
SEMICONDUCTOR
CY7CI009
Ordering Information
Speed
(ns)
12
15
20
25
Ordering Code
Package
Name
Package lYpe
CY7C1009-12PC
P31
32-Lead (400-Mil) Molded DIP
CY7C1009-12VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C1009-15PC
P31
32-Lead (400-Mil) Molded DIP
CY7C1009-15VC
V32
32-Lead (3qO-Mil) Molded SOJ
CY7C1009-15DMB
D32
32-Lead (300-Mil) CerDIP
CY7C1009-15LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C1009-20PC
P31
32-Lead (400-Mil) Molded DIP
CY7C1009-20VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C1009-20DMB
D32
32-Lead (300-Mil) CerDIP
CY7C1009- 20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C1009-25PC
P31
32-Lead (400-Mil) Molded DIP
CY7C1009-25VC
V32
32-Lead (300-Mil) Molded SOJ
CY7C1009- 25DMB
D32
32-Lead (300-Mil) CerDIP
CY7C1009-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
Parameter
Subgroups
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7,8,9,10,11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDOE
7, 8, 9, 10, 11
Icc
1,2,3
ISBl
1,2,3
twc
ISB2
1,2,3
tSCE
7, 8, 9, 10, 11
tAw
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
READ CYCLE
WRITE CYCLE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00199-A
2-397
II
CY7CI031
CY7CI032
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Supports 66-MHz Pentium microprocessor cache systems with zero
wait states
• 64K by 18 common I/O
• Fast clock-to-output times
- 8.5 ns with O-pF load
- 10 ns with 85-pF load
• 1Wo-bit wraparound counter supporting Pentium microprocessor and 486
burst sequence (7CI031)
• 1Wo-bit wraparound counter supporting linear burst sequence (7CI032)
• Separate processor and controller
address strobes
• Synchronous self-timed write
1M
64K X 18 Synchronous
Cache RAM
• Direct interface with the processor
and external cache controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC and PQFP packaging
Functional Description
The CY7CI031 and CY7CI032 are 64K
by 18 synchronous cache RAMs designed
to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5
ns. A 2-bit on-chip counter captures the
first address in a burst and increments
the address automatically for the rest of
the burst access.
The CY7CI031 is designed for Intel Pentium and i486 CPU - based systems; its
counter follows the burst sequence of the
Pentium and the i486 processors. The
CY7CI032 is architected for processors
with linear burst sequences. Burst accesses
can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for bank selection and
output three-state control.
Logic Block Diagram
Pin Configuration
PLCC
Top View
~.tI~I~I~I~I~ I~ d It'.l -. ._
L....______________
1031-1
0015 - 000
OP1 - oP
o
OE----------------------~L_~
1031-2
Selection Guide
Maximum Access Time (ns) (O-pF load)
Maximum Operating Current (rnA)
I Commercial
1':M'it~t}r
Shaded area contams advanced mformatlOn.
Pentium is a trademark of Intel Corporation.
Note:
1. DPo and DPI are functionally equivalent to DQx.
2~398
7CI031-8
7CI032-8
7CI031-10
7CI032-10
7CI031-12
7CI032-12
8.5
10.5
12.5
295
265
16 :
215
t\,
....
,"
220
~
:~PRESS
--=-,
.
CY7CI031
CY7CI032
PRELIMINARY
SEMICONDUCTOR
Functional Description (continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at
clock rise: (1) CS is WW and (2) ADSP is Ww. ADSP-triggered
write cycles are completed in two clock periods. The address at Ao
through AIS is loaded into the address register and address advancement logic and delivered to the RAM core. The write signal is ignored
in this cycle because the cache tag or other external logic uses this
clock period to perform address comparisons or protection checks. If
the write is allowed to proceed, the write input to the CY7C1031 and
CY7C1032 will be pulled WW before the next clock rise. ADSP is
ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information
presented at DOo - DOIS and DPo - DPI will be written into the
location specified by the address advancement logic. WL controls
the writing ofDOo - D07 and DPo while WH controls the writing
of DOs - DOISandDPI. BecausetheCY7C1031 andCY7C1032
are common-I/O devices, the output enable signal (OE) must be
deasserted before data from the CPU is delivered to DOo - DO IS
and DPo - DPI. As a safety precaution, the appropriate data lines
are three-stated in the cycle where WH, WL, or both are sampled
LOW, regardless of the state of the OE input.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC is
Law, and (3) WH or WL are Law. ADSC triggered accesses are
completed in a single clock cycle.
The address at Ao through AIS is loaded into the address register
and address advancement logic and delivered to the RAM core. Information presented at DOo - DOIS and DPo - DPI will be written into the location specified by the address advancement logic.
Since the CY7C1031 and the CY7C1032 are common-I/O devices,
the output enable signal (OE) must be deasserted before data from
the cache controller is delivered to the data and parity lines. As a
safety precaution, the appropriate data and parity lines are
three-stated in the cydewhere WH and WLare sampled LOW
regardless of the state of the OE input.
Single Read Accesses
A single read access is initiated when the following conditions are
satisfied at clock rise: (1) CS is Law, (2) ADSP or ADSC is Law,
I
66·MHz OSC
I---
Burst Sequences
en
The CY7C1031 provides a 2-bit wraparound counter, fed by pins :E
Ao - AI, that implements the Intel 80486 and Pentium processor's c:r:
address burst sequence (see Table 1). Note that the burst sequence
depends on the first burst address.
(/)
Thble 1. Counter Implementation for the Intel
Pentium/80486 Processor's Sequence
a::
First
Address
Ax+ t.Ax
00
01
10
11
Table 2. Counter Implementation for a Linear Sequence
First
Address
Ax+ t.Ax
00
01
10
11
Second
Address
Ax+ t.Ax
01
10
11
00
Third
Address
Ax+ t.Ax
10
11
00
01
Fourth
Address
Ax+ t.Ax
11
00
01
10
Application Example
Figure 1 shows a 512-Kbyte secondary cache for the Pentium microprocessor using four CY7C1031 cache RAMs.
ADR
DATA
DATA
ADS!'
7C1031
ADSC
PENTIUM
PROCESSOR
r
ClK
ArJIJ
WH~1
WR'W[~
I
I
ADSC
ClK
~
--IWH,W[
OE
ADV
2
2
2
112
OE W~
WH 1,
W[1
WH2 ,
WH 3 ,
W[3
ADR
W[2
DATA
ADS!'
cO~t~Sa.ER
DATA
MATCH
DIRTY
VALID
Fourth
Address
Ax+ t.Ax
11
10
01
00
The CY7C1032 provides a two-bit wraparound counter, fed by
pins Ao - AI, that implements a linear address burst sequence (see
Table 2).
ADS
CD
Third
Address
Ax+ t.Ax
10
11
00
01
ClK
ADR
ADR
Second
Address
Ax+ t.Ax
01
00
11
10
~
ClK
CACHE
TAG
and (3) WH and WLare HIGH. The addressatAo throughAIS is
stored into the address advancement logic and delivered to the
RAM core. If the output enable (OE) signal is asserted (LOW),
data will be available at the data outputs a maximum of 8.5 ns after •
clock rise. ADSP is ignored if CS is HIGH.
MATCH
DIRTY
VALID
Figure 1. Cache Using Four CY7CI031s
2-399
~I NTERFACETO
MAIN MEMORY
CY7CI031
CY7CI032
~
~rlPRF.SS
-:::;;;;;;? SEMICONDUCTOR
PRELIMINARY
Pin Definitions
Signal Name
# of Pins
1)rpe
Description
vec
Input
1
VCCQ
Input
4
+SV or 3.3V (Outputs)
GND
Input
1
Ground
VSSQ
Input
4
Ground (Outputs)
CLK
Input
1
Clock
A15 - Ao
ADSP
Input
16
Address
Input
1
Address Strobe from Processor
ADSC
Input
1
Address Strobe from Cache Controller
WH
Input
1
Write Enable - High Byte
+SVPower
WL
Input
1
Write Enable - Low Byte
ADV
Input
1
Advance
OE·
Input
1
Output Enable
CS
Input
1
Chip Select
DQ1S- DQO
Input/Output
16
Regular Data
DP1-DPO
Input/Output
2
Parity Data
Pin Descriptions
Signal
Name
I/O
Input Signals
CLK
A15-AO
I
Signal
Name
Description
WH
Clock signal. It is used to capture the address, the
data to be written, and the following control signals: ADSP, ADSC, CS, WH, WL, and ADV. It is
also used to advance the on-chip auto-address-increment logic (when the appropriate control signals have been set).
Sixteen address lines used to select one of 64K
locations. They are captured in an on-chip register
on the rising edge of CLK if ADSP or ADSC is
LOW. The rising edge of the clock also loads the
lower two address lines, A! - Ao, into the on-chip
auto-address-increment logic if ADSP or ADSC is
LOW.
I/O
Description
Write signal for the high-order half of the RAM
array. This signal is sampled by the rising edge of
CLK. If WH is sampled as LOW, i.e., asserted, the
control logic will perform a self-timed write of
DQ!5 - DQs and DP! from the on-chip data register into the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write
signal, WH, is ignored. Note that ADSP has no
effect on WH if CS is HIGH.
Write signal for the low-order half of the RAM
array.. This signal is sampled by the rising edge of
CLK. IfWL is sampled as LOW, i.e., asserted, the
control logic will perform a self-timed write of
DQ7 - DQo and DPo from the on-chip data register
into the selected RAM location. There is one exception to this. If ADSP, WL, and CS are asserted
(LOW) at the rising edge of CLK, the write signal,
WL, is ignored. Note that ADSP has no effect on
WL if CS is HIGH.
Address strobe from processor. This signal is
sampled at the rising edge of CLK. When this input
and/or ADSC is asserted, AO-A!5 will be captured
in the on-chip address register. It also allows the
lower two address bits to be loaded into the onchip auto-address-increment logic. If both ADSP
and ADSC are asserted at the rising edge of CLK,
only ADSP will be recognized. The ADSP input
should b~nected to the ADS output of the processor. ADSP is ignored when CS is HIGH.
Advance. This signal is sampled by the rising edge
of CLK. When it is asserted, it automatically increments the 2-bit on-chip auto-address-increment
counter. In the CY7C1032, the address will be incremented linearly. In the CY7CI031, the address
will be incremented according to the Pentium/486
burst sequence. This signal is ignored if ADSP or
ADSC is asserted concurrently with CS. Note that
ADSP has no effect on ADV if CS is HIGH.
Address strobe from cache controller. This signal is
sampled at the rising edge of CLK. When this input
and/or ADSP is asserted, Ao-A15 will be captured
in the on-chip address register. It also allows the
lower two address bits to be loaded into the onchip auto-address-increment logic. The ADSC input should not be connected to the ADS output of
the processor.
Chip select. This signal is sampled by the rising
edge of CLK. If CS is HIGH and ADSC is LOW,
the SRAM is deselected. If CS is LOW and ADSC
or ADSP is LOW, a new address is captured by the
address register. If CS is HIGH, ADSP is ignored.
2-400
CY7CI031
CY7CI032
PRELIMINARY
Pin Descriptions
Signal
Name
(continued)
Signal
I/O
OE
Description
Output enable. This signal is an asynchronous input that controls the direction of the data I/O pins.
If OE is asserted (LOW), the data pins are outputs,
and the SRAM can be read (as long as es was asserted when it was sampled at the beginning of the
cycle). If OE is deasserted (HIGH), the data I/O
pins will be three-stated, functioning as inputs, and
the SRAM can be written.
Name
I/O
Description
DPI-DPO
I/O
Two bidirectional data I/O lines. These operate in
exactly the same manner as DQ!5 - DQo, but are
named differently because their primary purpose is
to store parity bits, while the DQs' primary purpose is to store ordinary data bits. DP! is an input
to and an output from the high-order half of the
RAM array, while DPo is an input to and an output
from the lower-order half of the RAM array.
Bidirectional Signals
DQ15-DQO
I/O
Sixteen bidirectional data I/O lines. DQ!5 - DQ8
are inputs to and outputs from the high-order half
of the RAM array, while DQ7 - DQo are inputs to
and outputs from the low-order half of the RAM
array. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of eLK.
As outputs, they carry the data read from the selected location in the RAM array. The direction of
the data pins is controlled by OE: when OE is high,
the data pins are three-stated and can be used as
inputs; when OE is low, the data pins are driven by
the output buffers and are outputs. DQ!5 - DQ8
and DQ7 - DQo are also three-stated when WH
and WL, respectively, is sampled LOW at clock
rise.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 301S)
Storage Temperature .................. - 6S ° C to + 1S0° C
Latch-Up Current ............................ >200 rnA
Ambient Temperature with
Power Applied ....................... - SSoC to +12SoC
Operating Range
Range
Ambient
Temperature[3]
Vee
DC Voltage ApBlied to Outputs
in High Z State 2] .................. - O.5V to Vee + O.5V
VCCQ
Com'l
O°Cto +70°C
SV±S%
3.0V - S.5V
DC Input Voltagd 2] . . . . . . . . . . . . . . . . - O.SV to Vee + 0.5V
Mil
- 5SoC to +12SoC
SV±S%
SV±S%
Supply Voltage on Vee Relative to GND ... - O.5V to +7.0V
Current into Outputs (LOW) ...................... 20 rnA
Electrical Characteristics Over the Operating Rangd4]
7CI031-8
7CI032-8
Parameter
7CI031-12
7CI032-12
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
Vee = Min., IOH= -4.0 rnA
2.4
VeeQ
2.4
VeeQ
2.4
VeeQ
V
VOL
Output LOW Voltage
Vee = Min, IOL =8.0 rnA
VIR
Input HIGH Voltage
VIL
Input LOW Voltagd2j
Ix
Input Load Current
GND2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[Z]
Range
Commercial
Military
O°C to +70°C
Vee
5V ± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangel3]
7BI094-6
7BI095-6
7BI096-6
Description
Parameter
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
VOHl4J
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
Input HIGH Voltage
Input LOW Voitage l1J
IIX
Input Load Current
GND~VI~Vee
loz
Output Leakage
Current
GND ~ VI ~ Vee, Output Disabled
los
Output Short
Circuit Current[5]
Vee
lee
Vee Operating
Supply Current
Vee = Max., lOUT
f = fMAX = litRe
Automatic CE
Power-Down Current
Max. Vee, CE L VIH
f = fMAX = litRe
Mil
Automatic CE
Power-Down Current
Max. Vee, CE L Vee0.2V, VIN L Vee - 0.2V
or VIN ~ 0.2v, f = 0
Mil
ISB!
ISBZl4J
Vee
7BI094-8,9
7BI095-8,9
7BI096-8,9
Min.
Max.
Min.
Max.
Unit
2.4
3.3
2.4
3.3
V
0.4
2.2
= Max., VOUT = GND
2.2
Com'l
-0.3
-0.3
Vee
0.8
-10
+10
-10
+10
f.lA
- 10
+10
-10
+10
f.lA
- 300
rnA
180
rnA
180
Mil
Com'l
Com'l
V
V
Vee
0.8
- 300
= 0 rnA,
0.4
V
180
70
70
rnA
80
20
20
rnA
30
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (min.) = - 3.0V for pulse durations ofless than 20 ns.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. VOH maximum is limited by internal temperature-compensated bandgap reference. The output will not go above 3.3V unless externally
pulled to above 3.3Y.
5.
6.
2-413
= 1 MHz,
Max.
Unit
5
pF
6
pF
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
•
~
-. .~
~=CYPRESS
PRELIMINARY
~, SEMICONDUCTOR
AC Test Loads and Waveforms
R1481Q
30 pF
I
INCLUDING
JIG AND
SCOPE
-
TI
R2
255Q
OUTP~~
5 pF
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
R1481Q
OUTP~~ ~
CY7BI094
CY7BI095
CY7BI096
I
-
3.0V---R2
255Q
GND
1094-4
(b)
1094-5
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics Over the Operating Rangel 3, 7)
7BI094-6
7BI095-6
7BI096-6
Parameter
Description
Min.
Max.
7BI094-8
7BI095-8
7BI096-8
Min.
Max.
7BI094-9
7BI095-9
7BI096-9
Min.
Max.
Unit
READ CYCLE
6
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
6
8
9
tDOE
OE LOW to Data Valid
3.5
4
5
tLZOE
OE LOW to Low Z[8)
tHZOE
OE HIGH to High Z[8, 9)
tLzCE
CE LOW to Low Z[8)
tHzCE
CE HIGH to High Z[8, 9)
3
4
4.5
ns
tpu
CE LOW to Power-Up
0
0
0
ns
6
10
12
ns
9.
9
8
6
2.5
2.5
0
2.5
0
0
ns
ns
ns
ns
ns
0
4
3
0
9
4.5
ns
ns
0
twc
Write Cycle Time
6
8
9
ns
tSCE
CE LOW to Write End
5
6
7
ns
tAW
Address Set-Up to Write End
'4
6
7
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
4
P
7
ns
tSD
Data Set-Up to Write End
3
4
5
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[8)
0
WE LOW to High Z[8, 9)
0
tHZWE
Notes:
S.
ns
Read Cycle Time
Address to Data Valid
CE HIGH to Power-Down
tpD
WRITE CYCLE 10, 11J
7.
8
tRC
tAA
'lest conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5
pF as in part (b) of AC Test Loads and Waveforms. ltansition is measured ±500 mV from steady-state voltage.
0
3
0
ns
0
4
0
4.5
ns
10. The internal write time ofthe memory is defined by the overlap of CEl
LOW, CE2 LOW, and WE LOW. Both signals must be LOW to initiate
a write and either signal will terminate a write by going HIGH. The input data set -up and hold timing should be referenced to the rising edge
of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No.3 (WE controlled,
OE LOW) is the sum of tHZWE and tSD.
2-414
·
~
--=-,·lE
CY7BI094
CY7BI095
CY7BI096
PRELIMINARY
CYPRESS
SEMICONDUcrOR
Input/Output ESD and Clamp Diode Protection
•
VCC
VCC
ADDR/CONTROL
INPUT
TO DEVICE
DATA
INPUT/OUTPUT
PIN
TO DEVICE
1094-6
Switching Waveforms
Read Cycle No.
1[12, 13]
§
ADDRESS
tRC
~ tOHA~
I
PREVIOUS DATA VALID ~XXX*================DA=T=A=V=A=L=ID===========
-----'
DATA OUT
1094-7
Read Cycle No. 2[13, 14]
)K
ADDRESS
CE1
CE 2 (781096)
tRC
~K
}~
tACE
OE (781095
and 781096
only)
*
~K
I
tDOE
~tL20E-
HIGH IMPEDANCE
1//////
DATA I/O
tL2CE
~tpu
J}
VCC _ _ _ _ _ _ _ _ _
SUPPLY
_
CURRENT
tHZOE-tHZCE"
/
DATA VALID
I'" " " " "
-tpD
HIGH
IMPEDANCE
~ CC
I
50%
50%
Notes:
12. Device is continuously selected. CE and OE = VIL.
13. WE is HIGH for read cycle.
IS8
1094-8
14. Address valid prior to or coincident with CE transition LOW.
2-415
CY7BI094
CY7BI095..
CY7BI096
~
i~PRESS
z·
~JF
PRELIMINARY
SEMICONDUcrOR
Switching Waveforms (continued)
Write Cycle No.1 (CEI or CE2 Controlled)[15, 16]
~--------------------------twc--------------------------~~
ADDRESS
CE1
CE2
-----+--------------------------~ ~~-----tSCE----~~
(7B1096)
~---------------------tAw
,---------+----------
--------------.....--
_____________________________~~r:~~-~------~~------tS-D------------_-~~~____
K
DATA I/O
DATA VALID
1094-9
Write Cycle No.2 (WE Controlled, OE HIGH During Write for CY7BI095 and CY7BI096 only)[15, 16]
~-------------------------twc------------------------~
ADDRESS
CE1 .............'"'-jl....
(7B1096)
CE
....lIo..~
2
_____________________
"__""'"'+-'--"--"-'""'-"--
______::::::~_t_S_A::~_-_-_~~~~~~ ~~-----tpwE-----~ ,-____________________
0E(7B1095 """T'..,..,....,....-r-r'~,......----------------_+---------and 7B1096
only) ""'-"'"-'--"-....."
~----------tSD----------~.-~
DATA VALID
DATA I/O
1094-10
Write Cycle No.3 (WE Controlled, OE LOW)[ll, 16]
ADDRESS
CE1
CE2 (7B1096)
.........-P-....lIo..~----~----------------"--"-_+_-'--"-'""'-.-...~
14-------
DATA I/O
tSD -------....
-~
DATA VALID
Notes:
15. Data I/O is high impedance if DE = VIR.
16. IfeE I!oes HIGH simultllnp.olls1vwith WF HIGH thp. ()ntnnt rpm"in~
in a high-impedance st-ai:~:- - ---., ----. -------, ---- ---r------------
17. During this time the I/Os are in the output mode and input signals
must be applied.
2-416
~
~~PRESS
~_;F SEMICONDUCTOR
CY7BI094
CY7BI095
CY7BI096
PRELIMINARY
7BI094 'fruth Table
Input/Output
Power
CEI
WE
H
X
HighZ
Power-Down
Mode
Standby (ISB)
L
H
Data Out
Read
Active (Icc)
L
L
Data In
Write
Active (Icc)
I
7BI095 'fruth Table
CEI
WE
OE
H
X
X
HighZ
L
H
L
Data Out
Read
Active (Icd
L
L
X
Data In
Write
Active (Icd
L
H
H
HighZ
Selected, Output Disabled
Active (Icd
Input/Output
Mode
Power
Power-Down
Standby (ISB)
7BI096 'fruth Table
CEI
CE2
WE
OE
H
X
X
X
Input/Output
HighZ
Power-Down
Mode
Power
X
H
X
X
HighZ
Power-Down
Standby (ISB)
L
L
H
L
Data Out
Read
Active (Icd
Standby (ISB)
L
L
L
X
Data In
Write
Active (Icd
L
L
H
H
HighZ
Selected, Output Disabled
Active (Icc)
Ordering Information
Speed
(ns)
Ordering Code
6
CY7B1094-6VC
8
CY7B1094-8PC
CY7B1094-8VC
9
Speed
(ns)
Package
Name
V21
Package 1YPe
28-Lead Molded SO]
Commercial
P21
28-Lead (300-Mil) Molded DIP
Commercial
V21
28-Lead Molded SO]
CY7B1094-8DMB
D22
28-Lead (300-Mil) CerDIP
CY7B1094-8LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7B1094-9DMB
D22
28-Lead (300-Mil) CerDIP
CY7B1094-9LMB
L54
28-Pin Rectangular Leadless Chip Carrier
Package
Name
Package 1YPe
Ordering Code
Operating
Range
Military
Military
Operating
Range
6
CY7B1095-6VC
V21
28-Lead Molded SO]
Commercial
8
CY7B1095 - 8PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
9
CY7B1095-8VC
V21
28-Lead Molded SO]
CY7B1095 -8DMB
D22
28-Lead (300-Mil) CerDIP
CY7B1095-8LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7B1095-9DMB
D22
28-Lead (300-Mil) CerDIP
CY7B1095 -9LMB
L54
28-Pin Rectangular Leadless Chip Carrier
2-417
Military
Military
~
TJVl~ucroR
PRELIMINARY
Ordering Information (continued)
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
6
CY7BI096-6VC
V21
28-Lead Molded SOJ
Commercial
8
CY7B1096-8PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
28-Lead Molded SOJ
9
CY7B1096-8VC
V21
CY7B1096-8DMB
D22
28~Lead
CY7B1096-8LMB
L54
28-Pin Rectangular Leadless Chip Carrier
CY7B1096-9DMB
D22
28-Lead (300-Mil) CerDIP
CY7B1096-9LMB
L54
28-Pin Rectangular Leadless Chip Carrier
(300-Mil) CerDIP
Military
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
tRC
7, 8, 9, 10, 11
VIH
1,2,3
tAA
7, 8, 9, 10, 11
VILMax.
1,2,3
tOHA
7, 8, 9, 10, 11
IIX
1,2,3
tACE
7, 8, 9, 10, 11
Ioz
1,2,3
tDOE
7, 8, 9, 10, 11
Icc
1,2,3
ISB
1,2,3
READ CYCLE
WRITE CYCLE
twc
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7,8,9,10,11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9,10, 11
tSD
7,8,9,10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-A-00040-A
2-418
CY7BI094
CY7BI095
CY7BI096
CY7BI099
PRELIMINARY
32K X 8 Static R/W RAM
Features
Functional Description
• High speed
-tAA = 6 ns
• BiCMOS for optimum speed/power
• Low active power
-900mW
• Low standby power
-350mW
• Automatic power-down when
deselected
• Output enable (OE) feature
• Both 5V and 3.3V TTL-compatible
inputs and outputs
The CY7BI099 is a high-performance
BiCMOS static RAM organized as 32,768
words by 8bits. The CY7B1099 has arevolutionary center power/ground configuration. Easy memory expansion ~rovided
by an active LOW chip enable (CE), an active LOW output enable (OE), and threestate drivers. The device has an automatic
power-down feature that reduces power
consumption by more than 56% when deselected. Also, for 3.3V systems, V OR is
limited to 3.3V max.
Writing to the device is accomplished by
taking chip enable (CE) and write enable
(WE) inputs LOW Data on the I/O pins
(1/00 through 1/07) is then written into the
location specified on the address pins (Ao
through A14).
Logic Block Diagram
Reading from the device is accomplished
by ta~ chip enable (CE) and output enable (OE) LOW, whileforcingwriteenable
(WE) HIGH. Under these conditions, the
contents of the memory location specified
by the address pins will appear on the I/O
pins.
The eight input/output pins (1/00 through
1/07) are placed in a high-impedance state
when the device is deselect~CE HIGH),
the outputs are disabled (OE HIGH), or
during a write operation (CE and WE
LOW).
The CY7B1099 is available in leadless
chip carriers, and 300-mil-wide center
power/ground SOJs.
Pin Configurations
SOJ
Top View
NC
A11
A12
A 13
A14
A10
Ag
As
CE
OE
1/00
1/01
1/07
1/06
GND
Vee
1/0 0
GND
I/O,
1/02
1/°3
WE
Ao
1/0 2
A1
A2
A3
1/0 3
Vee
10
11
12
13
14
15
16
22
21
20
19
18
17
1/05
1/04
A7
Aa
A5
A!
NC
81099-2
LCC
1/04
Top View
~~~;::t>om
1/05
««
z«
CE
1/0 6
As
OE
1/0 7
I/Os
1/0 0
I/O,
Vee
1/07
GND
GND
1/0 2
1/0 3
Vee
1/0 5
1/0 4
WE
81099-1
A7
Ao
.[ ~~~~~~
81099-3
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)
7BI099-6
6
180
Commercial
Military
Commercial
Military
70
2-419
7BI099-8
8
180
180
70
80
7BI099-9
9
180
80
II
i~
•
~
PRELIMINARY
: CYPRESS
SEMICONDUCTOR
CY7BI099
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55°C to + 125°C
Supply Voltage on Vee Relative to GND[l)
- O.5V to + 7.0V
yoltage Apfllied to Outputs
III High Z State ) ....................... - O.5V to + 7.0V
DC Input Voltagefl) ..................... - O.5V to +7.0V
Current into Outputs (LOW) ...................... 20 rnA
Static Discharge Voltage ..... , ....... " ..... ;... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[Z)
Range
Commercial
pC
Military
O°C to +70°C
Vee
5V ± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangel3)
7BI099-8,9
7BI099-6
Parameter
VOR[4)
Description
Test Conditions
Output HIGH Voltage
VOL
Output LOW Voltage
Unit
Min.
Max.
Min.
Max.
2.4
3.3
2.4
3.3
V
0.4
V
= Min., lOR = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
0.4
VIR
Input HIGH Voltage
2.2
VIL
Input LOW Voltagefl)
-0.3
Vee
0.8
-0.3
Vee
0.8
V
-10
+10
-10
+10
fAA
-10
+10
-10
+10
fAA
- 300
rnA
180
rnA
IIX
Input Load Current
GND~ VI~
loz
Output Leakage
Current
GND ~ VI ~ Veo Output Disabled
los
Output Short
Circuit Currend5)
Vee
lee
Vee Operating
Supply Current
Vee = Max., lOUT
f = fMAX = litRe
Automatic CE
Power-Down Current
Max. Vee, CE L VIR
f = fMAX = litRe
Com'l
Automatic CE
Power-Down Current
Max. Vee, CE L Vee0.2V, VIN L Vee - 0.2V
or VIN ~ O.2V, f = 0
Com'l
ISBl
ISBZ l4J
Vee
= Max., VOUT = GND
2.2
- 300
= 0 rnA,
Com'l
180
Mil
V
180
70
70
Mil
rnA
80
20
20
Mil
rnA
30
Capacitance[6)
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (min.) = - 3.0V for pulse durations of less than ZO ns.
2. TAis the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. V OR maximum is limited by internal temperature-compensated bandgap reference. The output will not go above 3.3V unless externally
pulled to above 3.3Y.
5.
6.
2-420
= 1 MHz,
Max.
Unit
5
pF
6
pF
Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
.~
.
------1~
IF
PRELIMINARY
CYPRESS
SEMICONDUCTOR
AC Test Loads and Waveforms
R1481Q
OUTP~~ ~
30 pF
I
INCLUDING
JIG AND
SCOPE
-
TI
R1481Q
R2
255Q
OUTP~~
5 pF
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
I
-
CY7BI099
ALL INPUT PULSES
3.0V----
I
90%
R2
255Q
GND
B1099-4
(b)
B1099-5
THEVENIN EQUIVALENT
167Q
OUTPUT~
1.73V
Switching Characteristics Over the Operating Rangel 3, 7]
Parameter
7BI099-6
Max.
Description
Min.
7BI099-8
Max.
Min.
7BI099-9
Min.
Max.
Unit
9
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACE
CE LOW to Data Valid
6
8
9
ns
tDOE
OE LOW to Data Valid
3.5
4
5
ns
tLZOE
OE LOW to Low Z[8]
tHzOE
OE HIGH to High Z[8, 9]
4.5
ns
tLZCE
CE LOW to Low Z[8]
tHZCE
CE HIGH to High Z[8, 9]
3
4
4.5
ns
tpu
CE LOW to Power-Up
0
0
0
ns
6
10
12
ns
8
6
2.5
2.5
0
0
ns
2.5
ns
0
0
3
CE HIGH to Power-Down
tpD
WRITE CYCLE 10,11]
9
8
6
4
0
ns
ns
0
twc
Write Cycle Time
6
8
9
tSCE
CE LOW to Write End
5
6
7
ns
tAW
Address Set-Up to Write End
4
6
7
ns
tRA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
4
6
7
ns
tSD
Data Set-Up to Write End
3
4
5
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[8]
0
0
0
tHzWE
WE LOW to High Z[8, 9]
0
Notes:
7. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.Sv, input pulse levels of 0 to 3.0V, and output loading
of the specified IOr.fIOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHzOE is less than tLzOE, and tHZWE is less than tLZWE for any
given device.
9. tHZOE, tHZCE, and tHzWE are specified with a load capacitance of S
pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±SOO mV from steady-state voltage.
3
0
4
0
ns
ns
4.5
ns
10. The internal write time ofthe memory is defined by the overlap of CEl
LOW, CE2 LOW, and WE LOW. Both signals must be LOW to initiate
a write and either signal will terminate a write by going HIGH. The input data set -up and hold timing should be referenced to the rising edge
of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No.3 (WE Controlled,
OE LOW) is the sum of tHzWE and tSD.
2-421
$E:.~
~.a
~,
PRELIMINARY
CYPRESS
CY7BI099
SEMICONDUCTOR
Input/Output ESD and Clamp Diode Protection
VCC
VCC
ADDR/CONTROL
INPUT
TO DEVICE
DATA
INPUT/OUTPUT
PIN
TO DEVICE
B1099-6
Switching Waveforms
Read Cycle No. 1[12, 13]
F
ADDRESS------'LLHA
DATA our
*-
IRC
~
I
PREVIOUS DATA VAUD 3XXX*================D=AT=A=V=A=L=ID===========
B1099-7
Read Cycle No. 2[13, 14]
)~
ADDRESS
tRC
~,
/~
tACE
,{
~~
tOOE
f4--tLZOEHIGH IMPEDANCE
DATA I/O
tLZCE
I
tHZOE ---+
-tHzCE-
/////v
HIGH
" IMPEDANCE
DATA VALID
'''''''''1'\.
/
~tpo
I----tpu
~
50%
.
CC
I
ISB
B1099-8
Notes:
12. Device is continuously selected. CE and OE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition Law.
2-422
PRELIMINARY
CY7BI099
Switching Waveforms (continued)
Write Cycle No.1 (CE Controlled)[15, 16]
~--------------------------twc--------------------------~~
ADDRESS
-----+--------------------------~ ~~-----tSCE----~~
,---------+----------
~----------------------~w------------------~~--..
~~~--------tSD-------.~
DATA I/O -------------------(K..------D-A-JA-V-A-L-ID--.;.....-81099-9
Write Cycle No.2 (WE Controlled, OE HIGH)[15, 16]
~-------------------------twc------------------------~
ADDRESS
14------ tSA
______________________
----~
~~~~------tpwE-----~,---
__----------------
~----------tSD----------~.-~
DATA VALID
DATA I/O
81099-10
Write Cycle No.3 (WE Controlled, OE LOW)[ll, 16]
ADDRESS
.....------ tSD
DATA I/O
------~014_--~
DATA VALID
Notes:
15. Data I/O is high impedance if OE = VIH.
16. IfCEgoes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
17. During this time the IIOs are in the output mode and input signals
must not be applied.
2-423
•
~2
PRELIMINARY
~IQyPRF.SS
_,
SEMICONDUCTOR
Truth Table
CE
WE
OE
H
X
X
Input/Output
HighZ
Power
Mode
Power-Down
Standby (ISH)
Active (Icc)
L
H
L
Data Out
Read
L
L
X
Data In
Write
Active (Icc)
L
H
H
HighZ
Selected, Output Disabled
Active (Icc)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
6
CY7B1099-6VC
V32
32-Lead Molded SO]
Commercial
8
CY7B1099-8VC
V32
32-Lead Molded SO]
Commercial
CY7B1099-8LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Military
CY7B1099-9LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Military
9
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
READ CYCLE
DC Characteristics
Subgroups
tRC
7,8,9,10,11
VOH
1,2,3
tAA
7, 8, 9, 10, 11
VOL
1,2,3
tORA
7, 8, 9, 10, 11
VIH
1,2,3
tACE
7,8,9, 10, 11
VILMax.
1,2,3
tOOE
7, 8, 9, 10, 11
IIX
1,2,3
Ioz
1,2,3
twc
7, 8, 9, 10, 11
Icc
1,2,3
tSCE
7, 8, 9, 10, 11
ISH
1,2,3
tAW
7, 8, 9, 10, 11
Parameter
WRITE CYCLE
tRA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tpWE
7, 8, 9, 10, 11
tso
7, 8, 9, 10, 11
tHO
7,8,9,10,11
Document #: 38-A-00041-A
2-424
CY7BI099
CY7C1331
CY7C1332
ADVANCED INFORMATION
64K X 18 Synchronous
Cache 3.3V RAM
Features
• Supports 50-MHz Pentium@) processor cache systems with zero wait
states
• 64K by 18 common I/O
• Fast clock-to-ontput times
- 12.5 ns with O-pF load
- 14 ns with 85-pF load
• 1Wo-bit wraparound counter supporting the Pentium and 486 burst sequence (7CI331)
• 1Wo-bit wraparound counter supporting linear burst sequence (7CI332)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor
and external cache controller
• Asynchronous ontpnt enable
• JEDEC-standard pinout
• 52-pin PLCC and PQFP packaging
Functional Description
The CY7C1331 and CY7C1332 are 3.3V
64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 12.5
ns. A 2-bit on-chip counter captures the
first address in a burst and increments the
address automatically for the rest of the
burst access.
The CY7C1331 is designed for Intel Pentium and i486 CPU -based systems; its
counter follows the burst sequence of the
Pentium and the i486 processors. The
CY7C1332 is architected for processors
with linear burst sequences. Burst accesses
can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for bank selection and
output three-state control.
Pin Configuration
Logic Block Diagram
PLCC
Top View
:f
A1S -
Ao
DOs
DOg
veeo
vsso
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature[3]
Range
Com'l
Mil
O°C to +70°C
VCC,VCCQ
3.3V ± O.3V
- 55°C to +125°C
3.3V ± O.3V
Over the Operating Rangd 4]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Vce = Min., IOH=-2.0 rnA
Vee = Min, IOL=2.0 rnA
7C1331-12
7C1332-12
Max.
Min.
2.4
0.4
2.0
Vee
7C1331-16
7C1332-16
Min.
Max.
2.4
0.4
2.0
Vee
+O.3V
VIL
Ix
loz
los
Icc
Input LOW Voltagel 2J
Input Load Current
Output Leakage
Current
Output Short Ciruit
Current[5]
V ce Operating Supply
Current
-0.3
-1
-5
GND~VI~Vee
GND ~VI~Vee,
Output Disabled
Vee = Max., VOUT = GND
Vee=Max.,
Iout=OrnA,
f=fMAX = litRe
I Com'l
I Mil
0.8
+1
+5
7C1331-19
7C1332-19
Min.
Min.
2.4
0.4
2.0
Vee
+O.3V
-0.3
-1
-5
0.8
+1
+5
Unit
V
V
V
+O.3V
-0.3
-1
-5
0.8
+1
+5
!tA
V
fAA
-300
-300
-300
rnA
180
160
150
rnA
170
Notes:
2. Minimum voltage equals - 2.0V for pulse durations of less than 20 ns.
3. TAis the "instant on" case temperature.
Sec the last page of this specification for Group A subgruup testing information.
5.
2-428
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
CY7C1331
CY7C1332
~
;~PRESS
.
~,
ADVANCED INFORMATION
SEMICONDUCTOR
Electrical Charaterictics (continued)
Parameter
ISBl
ISB2
Description
7C1331-12
7C1332-12
Min.
Max.
Test Conditions
Automatic CE
Power~Down Current
- TTL Inputs
Max. Vee, CS :2::
VIR, VIN :2:: VIR or
VIN:::;VIL,f=fMAX
Automatic CE
Power-Down Current
-CMOS Inputs
Max. Vee, CS :2::
Vee -0.3v, VIN:2::
Vee -O.3V or VIN
:::; 0.3V, f=O [6]
Com'l
7C1331-16
7C1332-16
Min.
Max.
30
7C1331-19
7C1332-19
Min.
Min.
30
Unit
rnA
30
Mil
30
Com'l
10
10
10
Mil
rnA
10
Capacitance[7]
Parameter
Description
CIN: Addresses
Input Capacitance
CIN: Other Inputs
Input Capacitance
COUT
Output Capacitance
AC Test Loads and Waveforms
3'3V~R11179Q
85 PF
Equivalent to:
31
OUTPUT
3.
I
Com'l
Mil
Com'l
Mil
Com'l
Mil
Max.
Unit
4
6
6
8
pF
6
8
pF
pF
R11179Q
3V
OUTPUT
5 PF
R2
868Q
INCLUDING _
JIG AND SCOPE
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 3.3V
_
-
I
INCLUDING _
JIG AND SCOPE
(a)
ALL INPUT PULSES
3.0V - - - -..Lor--__---~
R2
868Q
GND
_
1331-3
(b)
THEVENIN EQUIVALENT
1331-4
500Q
OUTPUT~ 1.40V
85pF
I
Notes:
6.
Clock signal allowed to run at speed.
7.
2-429
Tested initially and after any design or process changes that may affect
these parameters.
II
CY7C1331
CY7C1332
~
"~PRFSS
IF
~
ADVANCED INFORMATION
SEMICONDUCTOR
Switching Characteristics Over the Operating Range!S]
7C1331-12
7C1331-12
Min.
Max.
20
7C1331-16
7C1331-16
Min.
Max.
25
7C1331-19
7C1332-19
Min.
Max.
30
Parameter
tCYC
Description
Clock Cycle Time
tCH
Clock HIGH
8
9
12
tCL
Clock LOW
8
9
12
ns
tAS
Address Set-Up Before CLK Rise
3
4
5
ns
tAH
Address Hold After CLK Rise
1
tCDVl
Data Output Valid After CLK Rise, <*__
1331-6
Single Write Timing: Write Initiated by ADSP
ClK
ADDRESS ""'-~~.,
DATA IN
DATA OUT
Notes:
11. OE is LOW throughout.
12. If ADSP is asserted while CS is HIGH, ADSP will be ignored.
13. ADSP has no effect on ADV, WH, and WL if CS is HIGH.
2-431
-
;~pRF.SS
RT
,
ADVANCED INFORMATION
SEMICONDUcrOR
CY7C1331
CY7C1332
Switching Waveforms (continued)
Single Write Timing: Write Initiated by ADSC
Burst Read Sequence with Four Accesses
elK
ADDRESS
ADSP[12] or
ADSC
ADV[13]
WH, WLl13]
DATA OUT
1331-8
2-432
~
~~
~ l!l CYPRESS
ADVANCED INFORMATION
~JF' SEMICONDUCTOR
CY7C1331
CY7C1332
Switching Waveforms (continued)
Output (Controlled by OE)
F~oz ~
DATAO:_>
....
VGCO
DO'4
DO'5
DP1[']
-+------.,..
cs ....- - - . f
WH
we
ADSC
===:::L__.-1
16
17
18
19
20
7 6 5 4 3 2,1, 52 51 50 49 48 47
46
45
44
43
42
41
7G1378
7C1379
40
39
38
37
36
35
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DPOI']
DO?
DOs
VCGO
VSSO
DOs
D04
D03
D02
VSSO
VCGO
DO,
DOo
18
1378-1
00,5 - 000
' - - - - - - - - - - - 1 > - + - DP, - DPo
OE------------{..L-.J
1378-2
Selection Guide
Maximum Access Time (ns) (O-pF Load)
Maximum Operating Current (rnA)
I Commercial
I Military
Pentium is a trademark of Intel Corporation.
Note:
1.
DPo and DPI are functionally equivalent to DQx'
2-437
7C1378-12
7C1379-12
7C1378-16
7C1379-16
7C1378-19
7C1379-19
12.5
16.5
19.5
180
160
150
170
•
ADVANCED INFORMATION
.CYPRESS
SEMICONDUCTOR
Features
• Single 3.3 ± 0.3V power supply
• High speed
- 20ns
• Low active power
- 235mW
• Low standby power
- 90mW
• 2.0V data retention
- 100/lW
• Ideal for low-voltage cache memory
applications
• Easy me~ expansion with CElt
CE2 and OE features
• CMOS for optimum speed/power
CY7C1388
3.3V 32K X 9 Static RAM
• Automatic power-down when
desel~ted
Functional Description
The CY7C1388 is a high-performance
3.3V CMOS static RAM organized as
32,768 words by 9 bits. Easy memory expansionl!l!rovided by an active LOW chip
enable(CEl),anactiveHIGHchipenable
(2), an active-LOW output enable
(OE), and three-state drivers. This device
has an automatic power-down feature that
reduces power consumption by more than
60% when deselected.
Writing to the device is accomplished by
takine enable one (CEl) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the nine
I/O pins (I/Oo through I/Os) is then written
into the location specified on the address
pins (Ao through A14).
Reading from the device is accomplished
by takinmChienable one CCEl) and output enable E) LOW while forcing write
enable
E and chip enable two (CE2)
HIGH. Under these conditions, the contents of the memory location specified by
the address pins will appear on the I/O
pins.
The nine input/output pins (IIOo through
I/Os) are placed in a high-impedance state
when the device is deselected (CEl HIGH
or CE2 LOW), the outputs are disabled
(UE HIGH), or during a wri~eration
(rnl WW, CE2 HIGH, and WE LOW).
THe CY7C1388 is available in standard
300-mil-wide DIPs and SOJs. Adiecoatis
used to ensure alpha immunity.
Logic Block Diagram
Pin Configuration
DIP/SOJ
Top View
NC
NC
As
3
A7
1/0 0
As
As
1/01
~
6
7
Aa
1/°2
A2
Al
I/Oa
Ao
1/°0
1/°1
1/04
I/~
1/°5
I/Oa
GND
1/°6
10
11
.12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vee
A14
CE2
WE:
A13
As
Al0
Au
rn;
A12
'CE01
I/Os
1/07
1/°6
1/05
1/04
Cl38B·2
'CE01
CE2
I/Cr
WE
OJ:
1/°8
C138S-1.
Selection Guide
7C1388-20
7C1388-25
Maximum Access Time (ns)
20
25
35
Maximum Operating Current (rnA)
65
60
55
Maximum Standby Current (rnA)
25
25
25
2-438
7C1388-35
-~
.. ~
ADVANCED INFORMATION
~=CYPRESS
~? SEMICONDUCTOR
CI7C1388
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
.
Storage Temperature .................. - 65 ° C to + 150 ° C
Ambient Temperature with
Power Applied ....................... - 55°C to +125°C
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Supply Voltage on Vee to Relative GND '" - 0.5V to +3.6V
DC Voltage Apglied to Outputs
in High Z State 1] .................. - 0.5V to Vee + O.3V
DC Input Voltagd 1] .... . . . . . . . . . . .. - 0.5V to Vee + 0.3V
Range
Commercial
Ambient
Temperature
Vee
O°C to +70°C
3.3V ± O.3V
Electrical Characteristics Over the Operating Rangd2]
7C1388-20
Parameter
Description
Test Conditions
Min.
2.4
Max.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 2.0 rnA
VIR
Input HIGH Voltage
VIL
Input LOW Voltagd1]
IIX
Input Load Current
GND:::;;VI:::;;Vee
loz
Output Leakage Current GND:::;; VI:::;; Vee,
Output Disabled
los
Output Short Circuit
Current[3]
Vee=Max., VouT=GND
-300
lee
Vee Operating Supply
Current
Vee=Max.,loUT=OrnA,
f=fMAX=1/tRe
ISBl
Automatic CE
Power-Down Current
-TTL Inputs
ISB2
Automatic CE
Power-Down Current
- CMOS Inputs
7C1388-25
Min.
Max.
Max.
Unit
0.4
V
V
2.4
2.4
0.4
7C1388-35
Min.
0.4
V
2.0
Vee
+O.3V
2.0
Vee
+O.3V
2.0
Vee
+O.3V
-0.3
0.8
-0,3
0.8
-0.3
0.8
V
-1
+1
-1
+1
-1
+1
!lA
-2
+2
-2
+2
-2
+2
!lA
-300
-300
rnA
65
60
55
rnA
Max. Vee. CE1 ~ VIR or
CE2 :::;; VIL, VIN ~ VIR or
VIN :::;; VIL, f = fMAX
25
25
25
rnA
Max. Vee, CE1 ~ Vee -0.3V
or CE2:::;; 0.3v, VIN ~ Vee
-O.3V or VIN :::;; 0.3v, f=O
500
500
500
!lA
Capacitance[4]
Parameter
CIN: Addresses
Description
Input Capacitance
CIN : Controls
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 3.3V
Output Capacitance
Notes:
1. Minimum voltage is equal to - 2.0 for pulse durations of less than 20
ns.
2. See the last page of this specification for Group A subgroup testing information.
3.
4.
2-439
Max.
Unit
6
pF
8
pF
8
pF
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
~
il~NDUcroR
ADVANCED INFORMATION
..
31
CY7C1388
AC Test Loads and Waveforms[5, 6]
R111790
3V
ALL INPUT PULSES
OUTPUT
3.
I
CL
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V
------1I!__----:IL
GND
::80
_
C1388-3
C1388-4
THEVENIN EQUIVALENT
5000
OUTPUT 0
W
0
1.40V
Switching Characteristics Over the Operating Rangef Z, 5]
7C1388-20
Parameter
Description
Min.
Max.
7C1388-25
Min.
Max.
7C1388-35
Min.
Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
20
3
CEI LOW or CEz HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Zl7j
OE HIGH to High Zl6, Ij
25
ns
35
ns
ns
ns
ns
3
3
20
25
35
8
9
10
0
3
7
3
8
0
7
3
8
0
8
ns
ns
ns
ns
0
25
20
ns
0
0
7
tHzOE
CEI LOW or CEz HIGH to Low Zl7j
tLZCE
CEI HIGH or CEz LOW to High Zl6, 7j
tHZCE
CEI LOW or CEz HIGH to Power-Up
tpu
CEI HIGH or CEz LOW to Power-Down
tpD
WRITE CYCLE[8, 9]
35
25
20
35
ns
twc
Write Cycle Time
CEI LOW or CEz HIGH to Write End
20
12
25
15
35
20
ns
tSCE
tAW
tHA
Address Set-Up to Write End
12
15
20
ns
0
0
0
ns
tSA
Address Hold from Write End
Address Set-Up to Write Start
tPWE
WE Pulse Width
0
12
0
15
0
20
ns
ns
tSD
Data Set-Up to Write End
10
11
12
tHD
0
0
0
ns
ns
tHZWE
Data Hold from Write End
WE LOW to High Zl6j
tLzWE
WE HIGH to Low ZL7j
3
7
Notes:
5. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and load capacitance CL = 30 pF.
6. tHZOE, tHZCE, and tHzWE are specified with CL = 5 pF of AC Test
Loads. nansition is measured ±500 m V from steady-state voltage.
7. At any given temperature and voltage condition, tHzCE is less than
tLZCE, tHZOE is less than tLZOE, and tHzWE is less than tLZWE for any
given device.
8. The internal write time of the memory is defined by the overlap of CE1
LOW, CE2 HIGH, and WE LOW All three signals must be asserted
to initiate a write and any signal can terminate a write by being deas-
9.
2-440
7
3
ns
7
3
ns
ns
serted. The data input set-up and hold timing should be referenced to
the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE
LOW) is the sum of tHzWE and tso.
=;:
::~
ADVANCED INFORMATION
~=CYPRESS
-?
CY7C1388
SEMICONDUCTOR
Data Retention Characteristics Over the Operating Range
Conditions [10]
Description
Parameter
VDR
Vee for Data Retention
IeeDR
Data Retention Current
teDR[4]
Chip Deselect to Data
Retention Time
tR[4]
Operation Recovery Time
Min.
Max.
Unit
50
!lA
2.0
Vee=VDR=2.0V,
CE1 ~ Vee -0.3V or
CE2 ~ 0.3V, VIN ~ Vee0.3V or VIN ~ 0.3V
II
V
0
ns
tRe
ns
Data Retention Waveform
Vcc
------------------------------~I
DATA RETENTION MODE
VDR
3.0V
r--
tCDR
~
2V
-
=
*-
C1388·5
Switching Waveforms
Read Cycle No. 1[11, 12]
~v:: =lxx
tRC
ADDRESS
--~
DATA OUT
tM
PREVIOUS DATA
+1
*===============D=A=TA=_V-A=L=ID============
C1388·6
Read Cycle No.2 (Chip Enable Controlled)[12, 13, 14]
CE1
tRC
~f'\.
;Il
tACE
~I'\.
;Il
tDOE
DATA OUT
tLZCE
~WE~
I+-- tHZCE
~tLZOE-
HIGH IMPEDANCE
v/r//v
DATA VALID
"""""1'\.
/
i---tpD
I+---tpu
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
~
50%
ICC
ISS
C1388·7
Notes:
10. No input may exceed Vee +0.3Y.
11. Device is continuously selected. OE, eE = VIL.
12. WE is HIGH for read cycle.
13. Timing parameters are the same for all chip-enable signals (CEl and
CEz). Only the timing for CEl is shown.
14. Address valid prior to or coincident with CE transition Law.
2-441
~
.~~NDUcrOR
ADVANCED INFORMATION
CY7C1388
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled)[8, 13, 15, 16)
~------------------------twc ----------------------~
ADDRESS
~------ tpWE - - - - - - - + I
--------------------~~~
14-----
,------------------
tso ----------......f----+I tHO
DATA-IN VALID
C13BB-B
Write Cycle No.2 (CE Controlled) [8, 13, 15, 16]
~------------------------twc --------------------------~
ADDRESS
---+------------_ 14------
tSCE
---~
,-----+-----
~-------------------~W --------------------~~-
rf'llr--------- tso
DATA I/O
------~..
----------------ICK"--____D_AT_A_-I_N_V_A_L_ID_ _ _ _........ )0-------
C13BB-9
Write Cycle No.3 (WE Controlled, OE LOW)[9, 16]
ADDRESS
WE ------~~~~
14-----
DATAI/O
Notes:
15_ Data I/O is high impedance if OE
tso -----..._--.1
DATA-IN VALID
= VIH-
16_ IfCE goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
2-442
~
i~PRESS
~?
ADVANCED INFORMATION
'fiuth Table
CE
WE
OE
H
X
X
HighZ
DeselectlPower-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (Icc)
L
L
X
Data In
Write
Active (Icc)
L
H
H
HighZ
Deselect, Output Disabled
Active (Icc)
Input/Output
Mode
Power
Ordering Information
Speed
(ns)
20
25
35
CY7C1388
SEMICONDUCTOR
Ordering Code
CY7C1388 - 20PC
CY7C1388-20VC
CY7C1388 - 25PC
CY7C1388-25VC
CY7C1388-35PC
CY7C1388-35VC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Package
Name
P31
V32
P31
V32
P31
V32
Package 1YPe
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
32-Lead (300-Mil) Molded DIP
32-Lead (300-Mil) Molded SOJ
Operating
Range
Commercial
Commercial
Commercial
Switching Characteristics
Parameter
DC Characteristics
Subgroups
READ CYCLE
Parameter
Subgroups
VOH
1,2,3
tRC
7, 8, 9, 10, 11
VOL
1,2,3
tAA
7, 8,9, 10, 11
VIR
1,2,3
tOHA
7, 8, 9, 10, 11
VILMax.
1,2,3
tACE
7, 8, 9, 10, 11
IIX
1,2,3
tDOE
7, 8, 9, 10, 11
Ioz
1,2,3
Icc
1,2,3
twc
7, 8, 9, 10, 11
ISB!
1,2,3
tSCE
7,8,9, 10, 11
ISB2
1,2,3
tAW
7,8,9, 10, 11
tHA
7, 8, 9, 10, 11
WRITE CYCLE
tSA
7, 8, 9, 10, 11
tpWE
7,8,9,10,11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
Document #: 38-00221-A
2-443
•
CY7C1399
PRELIMINARY
3.3V 32K X 8 Static RAM
Features
• Single 3.3 ± O.3V power supply
• High speed
- 15ns
• Low active power
- 255mW
• Low standby power
- 90mW
• 2.0V data retention
- 100~W
• Ideal for low-voltage cache memory
applications
• Easy memory expansion with CE and
OE features
• CMOS for optimum speed/power
• Automatic power-down when
deselected
Functional Description
The CY7C1399 is a high-performance
3.3V CMOS static RAM organized as
32,768 words by 8 bits. Easy memory ex~
pansion ~rovided by an active LOW chip
enabl~CE) and active LOW output enable (OE) and three-state drivers. The device has an automatic power-down feature,
reducing the power consumption by more
than 60% when deselected.
An active LOW write enable signal (WE)
controls the writing!readin~eration of
the memory. When CE and WE inputs are
both LOW, data on the eight data input/
output pins (1/00 through 1/07) is written
Logic Block Diagram
into the memory location addressed by the
address present on the address pins (Ao
through A14)' Reading the device is accomplished by selecti~he device and enabling the ou~s, CE and OE active
LOW, while WE remains inactive or
HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless the chip is selected,
o~uts are enabled, and write enable
(WE) is HIGH. The CY7C1399 is available in standard 300-mil-wide DIP and
SO] packages. A die coat is used to ensure
alpha immunity.
Pin Configuration
DIP/SOJ
Top View
1/00
1/01
1/°2
1/°3
1/0 4
C1399-2
1/05
I/Os
1/07
C1399-1
Selection Guide
~~l
T,ki'
Maximum Access Time (ns)
7f(
.·~t·
Maximum Operating Current (rnA)
1;l{.A ..~lr
Maximum Standby Current (rnA)
I/\l~
~~:.;
;iJ'
'l;
iii,
Shaded area contams advanced mformatlon.
2-444
7C1399-20
7C1399 25
20
25
7C1399 35
35
65
60
55
25
25
25
~.4
'j; CYPRESS
~,
PRELIMINARY
CY7C1399
SEMICONDUCTOR
Maximum Ratings
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Output Current into Outputs (LOW) ............... 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage on Vee to Relative GND[l] . - O.5V to +3.6V
Range
Commercial
c(
a:
Ambient
Temperature
Vee
O°C to +70°C
3.3 ± O.3V
(/)
Electrical Characteristics Over the Operating Rangd Z]
7C1399-15
Parameter
VOH
Description
Output HIGH
Voltage
Test Conditions
2.~~ i
Vee = Min.,
IOH = - 2.0 rnA
VOL
Output LOW Voltage Vee = Min.,
IOL = 2.0 rnA
VIR
Input HIGH
Voltage
Max.
2.4
7C1399-25
Min.
Max.
2.4
0.4
. IU·1:'.
"
2.0 ; (,'Vcr;
7C1399-35
Min.
Max.
2.4
Unit
V
0.4
0.4
V
2.0
Vee
+O.3V
2.0
Vee
+O.3V
2.0
Vee
+O.3V
V
(1 O.S
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
-1
+1
-1
+1
-1
+1
-1
+1
ILA
4F;~'
~if.
-5
+5
-5
+5
-5
+5
ILA
to:3v
.;
;J~~3
Input LOW
Voltagel Z]
IIX
Input Load Current
loz
Output Leakage
Current
GND ~ VI~ Vee,
Output Disabled
Output Short
Circuit Currentl3]
Vee = Max.,
VOUT = GND
lee
Vee Operating
Supply Current
Vee = Max.,
lOUT = 0mA,
f = fMAX = litRe
ISBl
Automatic CE
Power-Down
CurrentTTL Inputs
Max. Vee, CE1 L VIR,
or CEz ~ VIL, VIN L
VIR, or VIN ~ VIL,
,"
f = fMAX
p;.
Automatic CE
Power-Down
CurrentTTL Inputs
Max. Vee, CE1 LVee,
O.3V or CEz ~ 0.3v,
VIN L Vee - 0.3v, or
VIN ~ 0.3V, f=O
ISBZ
7C1399-20
Min.
.C
VIL
los
M~
Min.
i;
F~:
. :.
~ ;~~~ .
- 300
- 300
-300
rnA
:;,
10
65
60
55
rnA
25
25
25
rnA
500
500
500
!LA
I
v'
K}·
+
, : 25
F
·r'·;
<;';.~
Shaded area con tams advanced mformatlOn.
)
.'] ~;
•....
~~?,OO
~
Capacitance[4]
Parameter
CIN: Addresses
Description
Test Conditions
Input Capacitance
TA = 25°C, f = 1 MHz,
Vee = 3.3V
CIN : Controls
COUT
Output Capacitance
Max.
Unit
6
pF
8
pF
8
pF
Notes:
1.
2.
Minimum voltage is equal to - 2.0V for pulse durations of less
than 20 ns.
See the last page of this specification for Group A subgroup testing information.
3.
4.
2-445
en
:E
Operating Range
DC Voltage APRlied to Outputs
in High Z State 1] .................. - O.5V to Vee + O.3V
DC Input Voltagd1] ................ - 0.5V to Vee + O.3V
I
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
.---:~
PRELIMINARY
'= CYPRESS
CY7C1399
_ , SEMICONDUCTOR
AC Test Loads and Waveforms
R11179Q
3'3V~
ALL INPUT PULSES
3.0V ----...Lo~----_s..
OUTPUT
CL
I
INCLUDING _
JIG AND SCOPE
Equivalent to:
GND
R2
868Q
_
-
C1399-3
THEVENIN EQUIVALENT
500Q
OUTPUT Oo---IIJ..""
.. _---QO 1.40V
Switching Characteristics Over the Operating Rangel 2,5]
7C1399-20
7C;1399-15
Parameter
Description
l\fi~~
Min.
Max.
Max.
7C1399-25
Min.
Max.
7C1399-35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
15,(
t'
3
OE LOW to Data Valid
" llt-'
tLZOE
OE LOW to Low Zl7J
OE HIGH to High Z[6, 7]
01:;
tHZOE
CE LOW to Low Zl7J
CE HIGH to High Zlb, 7J
'1
""
'; ;:s
tAW
tHA
Address Set-Up to Write End
!10.l
Address Hold from Write End
tSA
tpWE
Address Set-Up to Write Start
~;il
'0:4
tSD
WE Pulse Width
Data Set-Up to Write End
tHZWE
Data Hold from Write End
WE LOW to High ZlbJ
tLzWE
WE HIGH to Low Z[7j
tHD
'1'5
C',
15
c:~:O
:;,
"',
:
,,0
:;;<;;i'>
.
:':. ,t"
,~
:,:t
~it,
·····r
:lt9
Shaded area contains advanced information.
Notes:
5. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and capacitance CL = 30 pF.
6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in AC lest
Loads. 1fansition is measured ±500 mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE, tHzOE is less than tLzOE, and tHzWE is less than tLzWE for any
given device.
8. The internal write time of the memory is defined by the overlap of CE
LOVI and ',-'VB LO"V. Both signals illUSt be LOW to Initiate a write and
either signal can terminate a write by going HIGH. The data input set-
N';~'
9.
2-446
ns
7
8
ns
ns
8
ns
35
ns
0
25
ns
ns
ns
20
25
35
ns
12
15
20
ns
12
15
20
ns
0
0
0
ns
0
0
0
ns
12
15
20
ns
10
11
12
ns
0
J~;i
't
ns
3
0
20
35
10
7
8
0
ns
0
3
3
0
I",;"
9
0
7
.'!
10:
tSCE
8
ns
35
3
25
20
,1
35
25
3
0
Write Cycle Time
CE LOW to Write End
twc
"""~5,,
1":3
CE LOW to Power-Up
CE HIGH to Power-Down
tpD
WRITE CYCLE[S, 9]
20
3'
tDOE
tLZCE
tHzCE
tpu
25
20
15,
3
8
3
ns
0
0
8
8
3
ns
ns
up and hold timing should be referenced to the rising edge of the signal
that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE
LOW) is the sum of tHzWE and tSD.
-
~~PRESS
PRELIMINARY
.
- , SEMICONDUCTOR
CY7C1399
Data Retention Characteristics (Over the Operating Range)
Parameter
Conditions[lO]
Description
VDR
IeeDR
Data Retention Current
teDR[4]
Chip Deselect to Data
Retention Time
tR[4]
Operation Recovery Time
Data Retention Waveform
VCC
3.0V
~ tCOR -
Min.
Max.
Unit
50
!!A
2.0
Vee for Data Retention
Vee = VDR = 2.0V,
CE L Vee - 0.3V,
VIN L Vee - O.3Vor
VIN sO.3V
:f=
_
DATA RETEN. TION MODE
OR 2:.
V 2V
V
0
ns
tRe
ns
=lC
_
3.0V
tR
-----l
C1399·4
Switching Waveforms
Read Cycle No. 1[11,12]
~
ADDRESS
--~
DATA OUT
PREVIOUS DATA
*-
tRC
1
tAA
V~: =lxx *===============D=A=:r=A=V=A=L=ID============
C1399-5
Read Cycle No. 2[12,13]
CE
tRC
~"
}~
tACE
}~
~\.
tOOE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
1//////
tLZCE
""""""
DATA VALID
HIGH
IMPEDAN CE
/
_tpo
I+--tpu
___________
~ZOE~
-tHZCE
---tLZOE-
~cc
I
;ftsO%
.50%~ISB
C1399-6
Notes:
10. No input may exceed Vee + O.3Y.
11. Device is continuously selected. OE, CE = VIL-
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
2-447
I
-.;
==~
PRELIMINARY
CY7C1399
' . CYPRF.SS
~,
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled)[8, 14, 15]
twc
ADDRESS
CE
tpWE
tSA
OE
tSD
DATAI/O
tHD
DATA-IN VALID
C1399-7
Write Cycle No.2 (CE Controlled)[8, 14, 15]
twc
ADDRESS
CE
tSCE
~---------tSD--------~
DATA I/O - - - - - - - - - - - - - - - - <
DATA-IN VALID
Write Cycle No.3 (WE Controlled, OE LOW)[9, 15]
ADDRESS
WE ----------~~~~.
1 4 - - - - tSD - - - - - - -.....-~
DATAI/O
DATA-IN VALID
C1399-9
Notes:
14. Data I/O is high impedance if OE = VIH.
15. IfCEgoesHIGHsimultaneouslywithWEHIGH,theoutputremains
in a high-impedance state.
2-448
.
~::Z
--=-_'
PRELIMINARY
-'i!lCYPRESS
Truth Table
CE
WE
OE
H
X
X
HighZ
DeselectIPower-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (Icc)
L
L
X
Data In
Write
Active (Icc)
L
H
H
HighZ
Deselect, Output Disabled
Active (Icc)
Input/Output
•
Power
Mode
Ordering Information
Speed
(ns)
15
20
25
35
CY7C1399
SEMICONDUcrOR
Ordering Code
CY7C1399-15PC
CY7C1399-15VC
CY7C1399- 20PC
CY7C1399 - 20VC
CY7C1399 - 25PC
CY7C1399 - 25VC
CY7C1399 - 35PC
CY7C1399-35VC
Package
'JYpe
P21
V21
P21
V21
P21
V21
P21
V21
Operating
Range
Commercial
Commercial
Commercial
Commercial
Shaded area contams advanced mformatlon.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
DC Characteristics
Subgroups
READ CYCLE
Parameter
Snbgroups
VOH
1,2,3
tRC
7,8,9, 10, 11
VOL
1,2,3
tAA
7, 8, 9, 10, 11
VIH
1,2,3
tOHA
7, 8, 9, 10, 11
VILMax.
1,2,3
tACE
7,8,9,10,11
Irx
1,2,3
tDOE
7,8,9,10,11
Ioz
1,2,3
Icc
1,2,3
WRITE CYCLE
twc
7, 8, 9, 10, 11
ISBl
1,2,3
tSCE
7,8,9,10,11
ISB2
1,2,3
tAW
7,8,9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7,8,9,10,11
tpwE
7,8,9, 10, 11
tSD
7,8,9,10,11
tHD
7, 8, 9, 10, 11
Document #: 38-00222- B
2-449
.:rlPRFSS
~, SEMICONDUCTOR
PROMs (Programmable Read Only Memory)
Section Contents
Page Number
Introduction to CMOS PROMs ................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Device Number
Description
CY7C225
512 x 8 Registered PROM .................. , ....... , ................ , .......... 3-3
CY7C225A
512 x 8 Registered PROM .................................................... , 3-10
CY7C235
1K x 8 Registered PROM ..................................................... 3 -17
CY7C235A
1K x 8 Registered PROM . ~ .................................................. , 3 - 24
CY7C245
2Kx 8 Reprogrammable Registered PROM .................... , ....... , ......... 3-31
CY7C245A
2Kx 8 Reprogrammable Registered PROM ...................................... 3-32
CY7C251
16Kx 8 Power-Switched and Reprogrammable PROM ............................. 3-40
CY7C254
16K x 8 Reprogrammable PROM .............................................. , 3-40
CY7C256
32K x 8 Power-Switched and Reprogrammable PROM ............................ , 3-47
CY7C258
2Kx 16 Reprogrammable State Machine PROM .................................. 3-52
CY7C259
2Kx 16 Reprogrammable State Machine PROM .................................. 3-52
CY7C261
8Kx 8 Power-Switched and Reprogrammable PROM .............................. 3-64
CY7C263
8Kx 8 Reprogrammable PROM ................................................ 3-64
CY7C264
8Kx8 Reprogrammable PROM ................................................ 3-64
CY7C265
8K x 8 Registered PROM ..................................................... 3-74
CY7C266
8K x 8 Power-Switched and Reprogrammable PROM ............................. , 3-82
CY7C269
8K x 8 Registered Diagnostic PROM ........................................... , 3 -89
CY7C270
16K x 16 Reprogrammable Processor-Intelligent PROM .......................... 3-100
CY7C271
32Kx 8 Power Switched and Reprogrammable PROM ............................ 3-111
CY7C274
32Kx 8 Reprogrammable PROM .............................................. 3-111
CY7C276
16K x 16 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-120
CY7C277
32K x 8 Reprogrammable Registered PROM .................................... 3 -126
CY7C279
32K x 8 Reprogrammable Registered PROM ....................... . . . . . . . . . . . .. 3 -133
CY7C281
1Kx8PROM .............................................................. 3-140
CY7C282
1Kx8PROM .............................................................. 3-140
CY7C281A
1Kx8PROM .............................................................. 3-146
CY7C282A
1Kx8PROM .............................................................. 3-146
CY7C285
64K x 8 Reprogrammable Fast Column Access PROM ............................ 3-152
CY7C286
64Kx 8 Reprogrammable, AsynchronouslRegistered PROM ....................... 3-157
CY7C287
64K x 8 Reprogrammable, Asynchronous/Registered PROM . . . . . . . . . . . . . . . . . . . . . .. 3 -157
CY7C291
2K x 8 Reprogrammable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-165
CY7C292
2Kx 8 Reprogrammable PROM ............................................... 3-165
CY7C291A
2Kx8 Reprogrammable PROM ............................................... 3-166
CY7C292A
2Kx 8 Reprogrammable PROM ............................................... 3-166
CY7C293A
2K x 8 Reprogrammable PROM. . . .. . .. .. .. .. .. .. . .. . .. . . .. . .. . . . . . . . .. .. .. . .. 3-166
PROM Programming Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 -175
Introduction to CMOS PROMs
CYPRESS
SEMICONDUCTOR
Product Line Overview
The Cypress CMOS family of high-performance byte-wide and
word-wide (x16) PROMs spans 4-kilobit to 512-kilobit densities
and three functional configurations. Products are typically available as EPROMs (Erasable, Programmable ROMs) in 300- and
600-mil windowed cerDIP packages, leadless chip carriers
(LCCs), leaded chip carriers (CLCC, PLCe) and flatpacks. They
are also available as PROMs in similarly configured plastic and
opaque hermetic packages. With the exception of the 4K PROMs
(registered only), all densities are available in both registered and
non-registered versions. The registered devices operate in either
synchronous or asynchronous modes and may have an INITIALIZATION feature to preload the pipeline register, which allows the pipeline register to be loaded or examined via a serial
path.
Cypress PROMs perform at or above the speed level oftheir bipolar counterparts with the advantage of lower power consumption
inherent in CMOS technology. They operate with 10% power
supply tolerances and can withstand 2000 volts of electrostatic discharge.
Technology Introduction
Cypress PROMs are executed in N-well CMOS EPROM processes that provide basic gate delays of 235 picoseconds for a fanout of one with a power consumption of 45 fern to-joules. These
processes provide the basis for the development of Cypress LSI
products, which outperform the fastest bipolar equivalents.
Historically, CMOS static RAMs have challenged bipolar RAMs
for speed, while CMOS PROMs have been slower than the fused
bipolar devices because (1) the typical single transistor CMOS
cell is slow compared to any "fuse," and (2) CMOS technologies
were optimized for programmability and density at the expense of
speed. Innovative Cypress EPROM technology overcomes both
of these historical limitations. A substrate bias generator is
employed in an EPROM technology to improve performance and
raise latch-up immunity to greater than 200 mAo The result is a
CMOS EPROM technology that outperforms bipolar fuse technology for both density and speed, particularly at higher densities.
Limitations of devices implemented in the bipolar fuse technology
such as programming yield, power dissipation and higher-density
performance are eliminated or greatly reduced using Cypress
CMOS EPROM technology.
Programming
against a fixed reference, which allows distinction of a programmed
or unprogrammed cell. A MARGIN mode is also provided to monitor the thresholds of the individual bits allowing the monitoring of
the quality of programming during the manufacturing operation.
Single-Ended Memory Cells
a::
Erasability
This is available for devices in windowed packages, both registered
and non-registered. Wavelengths oflight less than 4000 Angstroms
begin to erase Cypress PROMs. For this reason, an opaque label
should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm 2 . For an ultraviolet lamp
with a 12 mV/cm2 power rating, the exposure time would be approximately 35 minutes.
The PROM needs to be within 1 inch of the lamp during erasure.
Permanent damage may result ifthe PROM is exposed to high intensity light for an extended period of time. The recommended
maximum dosage is 7258 Wsec/cm2 .
Some devices are sensitive to photo-electric effects during programming. Cypress recommends covering the windows of reprogrammable devices during programming.
Reliability
The CMOS EPROM approach to PROMs has some significant
benefits to the user in the area of programming and functional
yield. Since a cell may be programmed an erased multiple times,
CMOS PROMs from Cypress can be tested 100% for programmability during the manufacturing process. Because each CMOS
PROM contains a PHANTOM array, both the functionality and
performance of the devices may be tested after they are packaged,
thus assuring the user that not only will every cell program, but that
the product performs to the specification.
General Testing Information
Differential Memory Cells
Cypress PROMs are programmed a byte at a time by applying Vpp
( -12V) to the programming pin and the desired logic levels to input pins. Both logic 1 and logic 0 are programmed into the differential cell. A bit is programmed by applying Vpp on the control gate
and 9 volts on the drain of the floating-gate write transistor. This
causes hot electrons from the channel to be injected onto the floating gate, thereby raising the threshold voltage. Because the read
transistor shares a common floating gate with the program transistor, the threshold of the read transistor is raised from about 1 volt
to greater than 5 volts, resulting in a transistor that is turned
"OFF" when selected in a read mode of operation. Since both sides
of the differential cell are at equal potential before programming,
a threshold shift of 100 m V is the corrected logic state. Because an
unprogrammed cell has neither a 1 nor a 0 in it before programming, a special BLANK CHECK mode of operation is implemented. In this mode the output of each half of the cell is compared
•
The programming mechanism of the EPROM transistor in a
single-ended memory cell is the same as its counterpart in a
double-ended memory cell. The difference is that only 1s are pro- en
grammed in a single-ended cell. A 1 applied to the I/O pin during :liE
programming causes an erased EPROM transistor to be pro- 0
grammed, while a 0 allows the EPROM transistor to remain unprogrammed.
Q.
Incoming test procedures on these devices should be carefully
planned, taking into account the high-performance and output
drive capabilities of the parts. The following notes may be useful:
• Ensure that adequate decoupling capac:itance is eJ.?1ployed .
across the device Vee and ground termmals. MultIple capacItors are recommended, including a 0.1 !J.F or larger capacitor
and a 0.01 !J.F or smaller capacitor placed as close to the device
terminals as possible. Inadequate decoupling may result in
large variations of power supply voltage, creating erroneous
function or transient performance failures.
• All device test loads should be located within 2" of device
outputs.
• Do not leave any inputs disconnected (floating) during any
tests.
• Do not attempt to perform threshold tests under.AC conditions. Large amplitude, fast ground current tranSIents normally occur as the device outputs discharge the load capaci-
3-1
Introduction to CMOS PROMs
tances. These transients flowing through the parasitic
inductance between the device ground pin and the test system ground can create significant reductions in observable
input noise immunity.
• V OH and VOL are absolute voltages with respect to device
ground pin and include all overshoots due to system and/or
tester noise. Do not attempt to test these values without suitable equipment.
• Capacitance is tested initially and after any design or process
changes that may affect these parameters.
• The CMOS process does not provide a clamp diode. However,
the Cypress PROM Products are insensitive to - 3V dc input
levels and - 5V undershoot pulses of less than 10 ns (measured at50%).
Switching Tests
5VS19 5V5f1
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
R1
OUTPUT
3.0V---90%
OUTPUT
CL
INCLUDING
JIG AND
SCOPE
J
-
-
-
R2
5 pF
INCLUDING
JIG AND
SCOPE
(a) Normal Load
J
-
-
R2
GND
-
(b) High Z Load
INTRO-1
Equivalent to:
INTRO-2
THEVENIN EQUIVALENT
OUTPUT~VTH
Load circuit (a) is used to test all switching characteristics except
High Z parameters. Load circuit (b) is used to test High Z parameters. Rl is a resistor connected from the output to Vee and R2 is
connected between the output and ground for testing purposes.
Values of Rl and R2 are given in the individual datasheet for each
product. Speed is measured at 1.5V reference levels except for
delay to output High Z.
Document #: 38-00234
3-2
CY7C225
512 X 8 Registered PROM
• Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or 28-pin
PLCC
• SV ± 10% Vee, commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
1500V static discharge
Features
• CMOS for optimum speed/power
• High speed
- 25 ns max set-up
-12 ns clock to output
• Lowpower
-495 mW (commercial)
-660 mW (military)
• Synchronous and asynchronons output enables
• On-chip edge-triggered registers
• ButTered common PRESET and
CLEAR inputs
• EPROM technology, 100%
programmable
Functional Description
The CY7C225 is a high-performance 512
word by 8 bit electrically programmable
read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin
leadless chip carrier, and 28-pin PLCC.
The memory cells utilize proven EPROM
Pin Configurations
Logic Block Diagram
An
07
A1
06
A2
floating gate technology and byte-wide intelligent programming algorithms.
The CY7C225 replaces bipolar devices
and offers the advantages oflower power,
superior performance, and high programming yield. The EPROM cell requires
only 13.5V for the supervoltage and low
current requirements allow for gang programming. The EPROM cells allow for
each memory location to be tested 100%,
as each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that after customer programming the product will meet
AC specification limits.
PROGRAMMABLE
ARRAY
05
A3
8-BIT
EDGETRIGGERED
REGISTER
A!
A5
04
03
As
A7
02
As
01
DIP
Top View
A7
Vee
As
As
A!
PS
As
E
A3
em
A2
Es
A1
CP
An
07
00
06
01
05
02
GND
03
04
C225-2
LCC/PLCC
Top View
00
PS
.r~.t~J5~I~
lXR
A!
CP
A3
A2
A1
ES
An
C225-1
1:::
NC
00
432;1:282726"
25
24
23
22
21
20
10
19
11
12131415161718
E
ern
Es
CP
NC
07
06
o8'~~6'o8
C)
C225-3
Selection Guide
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum 03erating
Current (rnA
I
I
Commercial
Military
7C225-25
25
12
90
3-3
7C225-30
30
15
90
120
7C225-35
35
20
120
7C225-40
40
25
90
120
•
U)
:e
o
a:
D.
.:.~
CY7C225
~ICYPRESS
~_~
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ......... " ...... - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ...................... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
DC Program Voltage (Pins 7,18,20) ................ 14.0V
Static Discharge Voltage ........................ > 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Ambient
Temperature
Commercial
O°C to +70°C
Vee
5V ± 10%
Industrial[l]
- 40°C to +85°C
5V ± 10%
Military[2j
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangel3, 4]
Parameter
Description
Min.
Test Conditions
V OH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VIN = VIH or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = VIH or VIL
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs
IIX
Input Leakage Current
GND ~ VIN ~ Vee
VeD
Input Clamp Diode Voltage
Note 4
Output Leakage Current
GND ~ Vo ~ Veo Output Disabled[S]
Output Short Circuit Current
Vee = Max., VOUT
lee
Power Supply Current
IOUT=O~
Vee = Max.l
Programming Supply Voltage
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
V
= 0.OV[6]
V
2.0
V
-10
los
Ipp
Unit
0.4
loz
Vpp
Max.
2.4
0.8
V
+10
!-lA
- 40
+40
!-lA
- 20
- 90
rnA
90
rnA
I Commercial
IMilitary
120
13
14
V
50
rnA
3.0
V
0.4
V
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee =5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
5.
6.
7.
3-4
Max.
Unit
10
pF
10
pF
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Due to the design of the differential cell in this device, Icc can only be
accurately measured on a programmed array.
TJ~~
'IE CYPRESS
CY7C225
.IF SEMICONDUCTOR
AC Test Loads and Waveforms[4]
OUTP~~31R1
250Q
50PFI
INCLUDING _
JIG AND SCOPE
R2
_ 167Q
-
5PFI
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
5V31R1250Q
OUTPUT
_
-
3.0V - - - -...1~----~
R2
167Q
C225-4
GND
C225-5
•
en
:IS
(b) High Z Load
o
a:
THEVENIN EQUIVALENT
a..
100Q
OUTPUT Q.O---Al,.."'
.. _ _--oo 2.0V
C225-6
Operating Modes
The CY7C225 incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
~chronous CEs) and asynchronous (E) output enables and
LEAR and PRESET inputs.
Upon power-up, the synchronous enable (Es) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. Data is read by applying the memory 10cation-.!o the address inputs (Ao - As) and a logic LOW to the enable (Es) input. The stored data is accessed and loaded into the
masterflip-flopsofthedataregisterduringtheaddressset-uptime.
At the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output buffers,
and the accessed data will appear at the outputs (00 - 07) provided the asynchronous enable (E) is also Law.
The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active
state by switching the enable to a logic Law.
Regardless of the condition ofE, the outputs will go to the OFF or
high-impedance state upon the next positive clock edge after the
synchronous enable (Es) input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW, the subsequent
positive clock edge will return the output to the active state ifE is
Law. Following a positive clock edge, the address and synchro-
nous enable inputs are free to change since no change in the output
will occur until the next LOW-to-HIGH transition of the clock.
This unique feature allows the CY7C225 decoders and sense amplifiers to access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system
clock without introducing race conditions. The on-chip register
timing requirements are similar to those of discrete registers available in the market.
The CY7C225 has buffered asynchronous CLEAR and PRESET
inputs. Applying a LOW to the PRESET input causes an immediate load of all ones into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). Applying a LOW to the CLEAR input, resets the flip-flops to all
zeros. The initialize data will appear at the device outputs after the
outputs are enabled by bringing the asynchronous enable (E)
LOW.
When power is applied, the (internal) synchronous enable flip-flop
will be in a state such that the outputs will be in the high-impedance
state. In order to enable the outputs, a clock must occur and the Es
input pin must be LOW at least a set-up time prior to the clock
LOW-to-HIGHtransition.TheEinputmaythenbeusedtoenable
the outputs.
3-5
£~CYPRF.SS
CY7C225
~6il6
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd3, 4)
7C225;...25
Parameter
Description
Min.
Max.
7C225-30
Min.
Max.
7C225-35
Min.
Max.
7C225-40
Min.
tSA
Address Set-Up to Clock HIGH
25
30
35
40
tRA
Address Hold from Clock HIGH
0
0
0
0
teo
Clock HIGH to Valid Output
12
15
20
Max.
Unit
ns
ns
25
ns
tpwe
Clock Pulse Width
10
15
20
20
ns
tSES
Es Setup to Clock HIGH
10
10
10
10
ns
tHES
Es Hold from Clock HIGH
0
5
5
5
tOB toe
Delay from PRESET or CLEAR to Valid Output
tRB tRe
PRESET or CLEAR Recovery to Clock HIGH
15
20
20
20
ns
tpWB tpwe
PRESET or CLEAR Pulse Width
15
20
20
20
ns
teas
Valid Output from Clock HIGH[S)
20
20
25
30
ns
tHze
Inactive Output from Clock HIGH[S)
20
20
25
30
ns
tOOE
Valid Output from E LOW
20
20
25
30
ns
tHZE
Inactive Output from E HIGH
20
20
25
30
ns
20
20
20
ns
20
ns
Switching Waveforms[4)
Es
_ _ _ _..1..1..11
CP
E
PSorCLR
C22S-7
Note:
8. Applies only when the synchronous ('Es) function is used.
3-6
.......···4
CY7C225
_'iECYPRESS
-=;;;;,
SEMICONDUCIOR
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programminginformation, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[9]
Read or Output Disable
Mode
Other
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As -Ao
As-Ao
As-Ao
As -Ao
Read
Output Disable
Output Disable
Clear
Preset
Program
Program Verify
Program Inhibit
Intelligent Program
Blank Check Ones
Blank Check Zeros
CP
Es
CLR
E
PS
PGM
VFY
Vpp
E
PS
D, - Do
X
VIL
VIH
VIL
VIH
07 - 00
X
VIH
VIH
X
VIH
HighZ
X
X
VIH
VIH
VIH
HighZ
X
VIL
VIL
VIL
VIH
Zeros
X
VIL
VIH
VIL
VIL
Ones
VILP
VIHP
Vpp
VIHP
VIHP
D7- D O
VIHP
VILP
Vpp
VIHP
VIHP
07 - 00
VIHP
VIHP
Vpp
VIHP
VIHP
HighZ
VILP
VIHP
Vpp
VIHP
VIHP
D7- D O
Vpp
VILP
VILP
VILP
VIHP
Ones
VIHP
Zeros
Vpp
VIHP
VILP
VILP
X = "don't care" but not to exceed Vee ±S%.
DIP
LCC/PLCC
Top View
Top View
.r ~.t~~.f~
As
vee
As
As
PS
A-.
A-.
E
A3
A2
A,
A3
A2
VF'?
PWii1
A7
Ao
Do
0,
02
GNO
•
U)
Note:
9.
0, - 00
Vpp
NC
4 3 2,1,282726
25
24
23
8
22
9
21
10
20
Do
111213141516171~9
A,
Ao
07
06
5
6
7
.,.. C\lo
05
04
03
00 Z
C!l
C225-8
Figure 1. Programming Pinouts
3-7
C,.) (') V
E
Vpp
VFY
PWii1
NC
07
06
10
ZOO 0
C225-9
:E
oa::
Q.
=-: .~
~=CYPRESS
CY7C225
~, SEMICONDUcrOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
j::::
I:::l
1.6
~1.1
o
!:;
1.4
~
1.2 ~
a..
u1.4
.2
Q
UJ
N
:J
«
:::2:
II:
0
1.2
/~
/
z
0.8
/
0.6
4.0
Q
W
N
:J 1.0
I:::l
I~
-
4.5
5.0
5.5
~
j:::: 1.0
1.4
tti
rn 0.8
Q
w
N
:J
«
~
II:
0.6
0
0.4
4.0
125
OUTPUT SOURCE CURRENT
vs.VOLTAGE
~ 50
25.0
~
o
~ 30
II:
:::l
g
"
20
I-
~
I:::l
o
10
0
o
5.0
1.0
~
" '"
2.0
OUTPUT VOLTAGE
+"
~
~4.0
M
I
4.5
5.5
6.0
M
5.5
.IV
z 0.8
M
600
25
125
AMBIENT TEMPERATURE (0C)
« 175
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
.s 150
I-
z
".
~ 125
II:
B 100
TA = 25°C _
Vee = 4.5V
400
-
0.6
- 55
6.0
~
I
200
---
1.2
N
:J
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Ambient
Temperature
Commercial
O°C to +70°C
Vee
5V ± 10%
Industrial [1]
- 40°C to +85°C
5V ± 10%
Military[2]
- 55°C to +125°C
5V ± 10%
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VIN = VIH or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = VIH or VIL
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs
Max.
Unit
V
2.4
V
0.4
2.0
V
0.8
V
+10
flA
IIX
Input Leakage Current
GND~ VIN~ Vee
VeD
Input Clamp Diode Voltage
Note 4
loz
Output Leakage Current
GND ~ VOUT ~ Veo Output Disabled[5]
-10
+10
flA
los
Output Short Circuit Current
Vee = Max., VOUT = 0.OV[6]
- 20
- 90
rnA
lee
Power Supply Current
lOUT = ornA
Vee = Max.
90
rnA
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
- 10
ICommercial
IMilitary
120
12
13
V
50
rnA
3.0
V
0.4
V
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee =5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
en
:t
o
a::
D.
Electrical Characteristics Over the Operating Rangel3, 4]
Parameter
I
4.
5.
6.
3-11
= 1 MHz,
Max.
Unit
10
pF
10
pF
See the "Introduction to CMOS PROMs" section ofthe Cypress Data
Book for general information on testing.
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
iiSP-
-0'~~PRESS
PRELIMINARY
.
CY7C225A
SEMICONDUcrOR
AC Test Loads and Waveforms[4]
OUTP~~~R1
R1250Q
OUTP~~31
50PFI
INCLUDING _
JIG AND SCOPE
R2
5PFI
_ 167Q
-
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
250Q
3.0V - - -....Jr-----s...
90%
GND
R2
_
-
167Q
C225A-4
C225A-5
(b) High Z Load
THEVENIN EQUIVALENT
100Q
OUTPUT~2.0V
C225A-6
Operating Modes
The CY7C225A incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
synchronous CBs) and asynchronous (E) output enables and
CLEAR and PRESET inputs.
Upon power-up, the synchronous enable (Es) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. Data is read by applying the memory location to the address inputs (Ao - As) and a logic LOW to the
enable (Es) input. The stored data is accessed and loaded into the
master flip-flops of the data register during the address set-up
time. At the next LOW-to-HIGH transition of the clock (CP),
data is transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs (00 07) provided the asynchronous enable (E) is also Law.
The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active
state by switching the enable to a logic Law.
Regardless of the condition ofE, the outputs will go to the OFF or
high-impedance state upon the next positive clock edge after the
synchronous enable (Es) input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic Law, the subsequent
positive clock edge will return the output to the active state ifE is
LOW. Following a positive clock edge, the address and synchro-
nous enable inputs are free to change since no change in the output
will occur until the next LOW-to-HIGH transition of the clock.
This unique feature allows the CY7C225A decoders and sense amplifiers to access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system
clock without introducing race conditions. The on-chip register
timing requirements are similar to those of discrete registers available in the market.
The CY7C225A has buffered asynchronous CLEAR and PRESET inputs. Applying a LOW to the PRESET input causes an immediate load of all ones into the master and slave flip-flops of the
register, independent of all other inputs, including the clock (CP).
Applying a LOW to the CLEAR input, resets the flip-flops to all
zeros. The initialize data will appear at the device outputs after the
outputs are enabled by bringing the asynchronous enable (E)
Law.
When power is applied, the (internal) synchronous enable flip-flop
will be in a state such that the outputs will be in the high-impedance
state. In order to enable the outputs, a clock must occur and the Es
input pin must be LOW at least a set-up time prior to the clock
LOW-to-HIGH transition. The Einput may then be used to enable
the outputs.
3-12
=--
.~
~=
CYPRF.SS
~, SEMICONDUCTOR
PRELIMINARY
CY7C225A
Switching Characteristics Over the Operating Rangel 3, 4)
Parameter
Description
7C225A-18
7C225A-25
7C225A-30
7C225A-35
7C225A-40
Min.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Unit
tSA
Address Set-Up to Clock HIGH
18
tHA
Address Hold from Clock HIGH
0
teo
Clock HIGH to Valid Output
tpwe
Clock Pulse Width
10
10
15
20
20
ns
tSES
Es Set-Up to Clock HIGH
10
10
10
10
10
ns
tHES
Es Hold from Clock HIGH
0
0
5
5
5
ns
tDP, tDe
Delay from PRESET or CLEAR to
Valid Output
tRP, tRe
PRESET or CLEAR Recovery to
Clock HIGH
15
tpwp, tpwe
PRESET or CLEAR Pulse Width
15
teas
Valid Output from Clock HIGH[7)
15
20
20
25
30
ns
tHze
Inactive Output
HIGH[7)
15
20
20
25
30
ns
tDOE
Valid Output from E LOW
15
20
20
25
30
ns
tHzE
Inactive Output from E HIGH
15
20
20
25
30
ns
from
25
0
12
0
15
20
15
ns
25
20
20
20
ns
0
20
20
20
15
40
35
0
12
20
Clock
30
20
20
ns
ns
20
20
ns
ns
Switching Waveforms[4)
~ -A10 __________________________~--~~~~--~---A~~~~~l-------------
Es
------'...,1
CP
00
-
0 7 ---+---------'1'---+-----'-'-'1
E
-------------r--+-------------------------------------J
1
J5S or ern
C225A-7
Note:
7. Applies only when the synchronous (Es) function is used.
3-13
•
~
.
~~PRESS
~,
PRELIMINARY
CY7C225A
SEMICONDUcrOR
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[S]
Read or Output Disable
Mode
Other
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
As-Ao
Read
Output Disable
Output Disable
Clear
Preset
Program
Program Verify
Program Inhibit
Intelligent Program
Blank Check
CP
Es
CLR
E
PS
PGM
VFY
Vpp
E
PS
D7 - Do
X
VIL
VIR
VIL
VIR
07 - 00
X
VIR
VIR
X
VIR
HighZ
X
X
VIR
VIH
VIR
HighZ
X
VIL
VIL
VIL
VIR
Zeros
X
VIL
VIR
VIL
VIL
Ones
VILP
VIRP
Vpp
VIRP
VIRP
D7- D O
VIRP
VILP
Vpp
VIRP
VIRP
07 - 00
VIRP
Vpp
VIRP
VIRP
HighZ
VILP
VIRP
Vpp
VIRP
VIRP
D7 - Do
VIRP
VILP
Vpp
VIHP
VIHP
Zeros
VIRP
Note:
8. X = "don't care" but not to exceed Vee ±5%.
Lee/PLee
Top View
DIP
Top View
A7
~ ~.t~ Jl.f ~
vee
As
As
As
J5S
At.
At.
E
A3
A2
Vpp
A3
A2
A1
VF'(
A1
J5GM
Ao
07
06
Do
D1
D2
GNO
Ao
NC
Do
4 3 2 1,282726
c
25
24
23
22
21
20
10
19
11
12131415161718
I:
Vpp
'iJF'(
J5GM
NC
D7
D6
T"""
NO C,.) (') -.:t Ll)
Cl Cl Z ZCl Cl Cl
Os
04
03
(!)
C225A-8
Figure 1. Programming Pinouts
3-14
C225A-9
07 - 00
-
~~PRESS
.
~~
PRELIMINARY
CY7C225A
SENUCONDUCTOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
VS. SUPPLY VOLTAGE
1.2
1.6
CLOCK TO OUTPUT TIME
~
VS. Vee
i= 1.6
I-
::>
a.
~1.4
o
gj
1.2
::J
/'
«
~
~ 1.0
z
0.8
1/
0.6
4.0
V
/
~
o
~
-
5.0
5.5
0.91-----+----....".,;;::----(
0~5~5----2~5~----~125
6.0
AMBIENT TEMPERATURE (0G)
~
~ 1.41------+-------1
i= 1.0
a..
o
~
o
9
N
oW
«
::J
a:
0
o
~
«
AMBIENT TEMPERATURE (0C)
§
40
o
~ 30
a:
::>
w
::J
«
~ 20
'"'""
o
1.0
-
~
~
"" ""
2.0
OUTPUT VOLTAGE
3.0
M
0.6
-55
6.0
5.5
4.0
125
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
«' 175
/
20.0
:::.::
z
Ci5
TA = 25°C _
Vee = 4.5V
400
600
v
a 100
I
200
z
~
//
V
I-
~ 125
/f'
~ 10.0
.s 150
a:
/
15.0
5.0
25
AMBIENT TEMPERATURE (0G)
...--
25.0
"
10
I-
0
5.0
I-
z 0.8
I
4.5
1.0
TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING
f
6.0
M
---
1.2
N
30.0
I-
o
0
SUPPLY VOLTAGE (V)
60
50
::>
rn
~
TA = 25°C
OUTPUT SOURCE CURRENT
vS.VOLTAGE
5.5
a..
::2:
a:
0
0.4
4.0
125
5.0
SUPPLY VOLTAGE
::> 1.4
f-!.
w
0.6
z
~
a: 0.6 L...-_ _ _- - ' -_ _ _ _ _- '
4.5
NORMALIZED SET·UP TIME
vs. TEMPERATURE
::J
N
ir
'"
...
w
rn 0.8
0
w
:::.::
a:
4.0
I
800 1000
CAPACITANCE (pF)
a.
I-
::>
o
50
25
o/
0.0
.." ~
/
75
Vee = 5.0V
TA = 25°C -
j
/
I
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
C225A-10
3-15
en
:::t
oa:
D.
I
1.6
-............ r--......
::>
f-!.
!zw
oz
---
r---
TA = 25°C
::2:
a: 0.6
1.2
w
::>
.s«'
W
NORMALIZED SET·UP TIME
VS. SUPPLY VOLTAGE
a..
25
o
NO.8
M
I-
- 55
~
«
w
CLOCK TO OUTPUT TIME
~
VS. TEMPERATURE
i= 1.6 . - - - - - - - , - - - - - - . . . . . ,
oz
...........
u
9 1.0
u
1.0
II
.......
1.2
::J
I
4.5
:::.::
::2:
a:
oz
o
f:?
w
N
TA = 25°C
f = fMAX
SUPPLY VOLTAGE
1.1 1 - - - - - + - - - - - - - - (
~ 1.4
~
~~~NDUCTOR
PRELIMINARY
CY7C225A
Ordering Information[9]
Speed
(ns)
tSA
teo
18
12
25
Ordering
Code
CY7C225A -18DC
CY7C225A -18JC
12
15
30
Package
'fYpe
Package
'fYpe
Operating
Range
D14
24-Lead (300-Mil) CerDIP
J64
Commercial
CY7C225A -18PC
P13
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
CY7C225A - 25DC
CY7C225A-25JC
D14
J64
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
CY7C225A - 25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C225A-25DMB
D14
L64
24-Lead (300-Mil) CerDIP
Military
D14
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
Commercial
J64
P13
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
CY7C225A - 25LMB
CY7C225A - 30DC
CY7C225A-3OJC
CY7C225A - 30PC
CY7C225A-30DMB
D14
L64
24-Lead (300-Mil) CerDIP
D14
L64
35
20
CY7C225A - 30LMB
CY7C225A-35DMB
CY7C225A - 35LMB
40
25
CY7C225A -40DC
D14
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
CY7C225A -40JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
Military
28-Square Leadless Chip Carrier
CY7C225A -40PC
P13
24-Lead (300-Mil) Molded DIP
CY7C225A -40DMB
CY7C225A -40LMB
D14
L64
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
Military
Commercial
Military
Note:
9.
Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
SMD Cross Reference
SMD
Number
DC Characteristics
Parameter
VOH
VOL
VIR
V1L
I1X
Ioz
lee
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Subgroups
tSA
tHA
7, 8, 9, 10, 11
teo
tDP
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
3-16
Cypress
Number
5962-88518
01LX
CY7C225A - 30DMB
5962-88518
013X
CY7C225A - 30LMB
5962-88518
02LX
CY7C225A - 35DMB
5962-88518
023X
CY7C225A - 35LMB
5962-88518
03LX
CY7C225A -40DMB
5962-88518
033X
CY7C225A -40LMB
Document #: 38-00228-A
Switching Characteristics
Parameter
Suffix
CY7C235
lK X 8 Registered PROM
Features
lize proven EPROM floating gate technology and byte-wide intelligent programming algorithms.
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin LCC and PLCC
• SV ± 10% Vee, commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
1500V static discharge
• CMOS for optimum speed/power
• High speed
- 25 ns max set-up
-12 ns clock to output
• Lowpower
-495 mW (commercial)
- 660 mW (military)
• Synchronous and asynchronous
output enables
• On-chip edge-triggered registers
• Programmable asynchronous
registers (INIT)
• EPROM technology, 100%
programmable
Functional Description
The CY7C23S is a high-performance 1024
word by 8 bit electrically programmable
read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin
leadless chip carrier, or 28-pin plastic
leaded chip carrier. The memory cells uti-
Logic Block Diagram
The CY7C23S replaces bipolar devices pin
for pin and offers the advantages of lower
power, superior performance, and high
programming yield. The EPROM cell requires only 13.SV for the supervoltage, and
low current requirements allow for gang
programming. The EPROM cells allow for
each memory location to be tested 100%,
as each location is written into, erased, and
repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that the product
will meet AC specification limits after customer programming.
Pin Configurations
m------~ ~----------------------------~
07
Ag
06
As
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
A7
Os
~
As
8-BIT
EDGETRIGGERED
REGISTER
ADDRESS
DECODER
04
Vee
~
As
As
Ag
~
E
A3
m
A2
Es
A1
CP
Ao
07
06
00
~
03
A3
A2
A1
A7
01
Os
02
04
GND
03
02
COLUMN
ADDRESS
C235-2
LCCIPLCC
01
Top View
Ao
:R~ 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
55 ° C to + 125 ° C
- 0.5V to + 7.0V
- 0.5V to +7.0V
- 3.0V to + 7.0V
......... 14.0V
Range
Ambient
Temperature
Vee
Commercial
O°Cto +70°C
5V ±10%
Industrial[l]
-40°C to +85°C
5V ±10%
Military[2]
-55°Cto +125°C
5V ±10%
Electrical Characteristics Over Operating Rangel 3]
Parameter
Description
Test Conditions
Min.
Max.
Unit
2.4
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VIN = VIR or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = VIR or VIL
VIR
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs[4]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs[4]
V
0.4
IIX
Input Leakage Current
GND ~ VIN ~ Vee
VCD
Input Clamp Diode Voltage
Note 5
loz
Output Leakage Current
GND ~ Va ~ Vee Output Disabled[5]
los
Output Short Circuit Current
Vee = Max., VOUT
Icc
Power Supply Current[7]
Vee = Max.,
lOUT = ornA
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIRP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
2.0
-10
= 0.OV[6]
V
V
0.8
V
+10
ftA
-40
+40
ftA
-20
-90
rnA
90
rnA
I Commercial
IMilitary
120
13
14
V
50
rnA
0.4
V
3.0
V
Capacitance[5]
Parameter
Test Conditions
Description
CIN
Input Capacitance
CO UT
Output Capacitance
TA = 25°C, f
= 1 MHz, Vee =5.0V
Max.
Unit
10
pF
10
pF
Notes:
Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
1.
5.
6.
7.
3-18
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Due to the design of the differential cell in this device, Icc can only be
accurately measured on a programmed array.
.~
--=-,'iE
CY7C235
CYPRESS
SEMICONDUCTOR
AC Test Loads and Waveforms[5]
R12500
OUTP~~31
50 P
FI
INCLUDING _
JIG AND SCOPE
R2
R12500
OUTP~~31
5 PF
1670
_
-
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
I
ALL INPUT PULSES
3.0V - - - -~..-----...",.,.,
R2
1670
GND
_
C235-4
C235-5
(b) High Z Load
THEVENIN EQUIVALENT
1000
OUTPUT OO---IV
........---oo 2.0V
C235-6
Operating Modes
The CY7C235 incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
synchronous (Es) and asynchronous (E) output enables and
asynchronous initialization (INIT).
Upon power-up, the synchronous enable (Es) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high -impedance state. Data is read by applying the memory location to the address input (Ao - A9) and a logic LOW to the enable (Es) input. The stored data is accessed and loaded into the
master flip-flops of the data register during the address set-up time.
At the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output buffers,
and the accessed data will appear at the outputs (00 - 07), provided the asynchronous enable (E) is also LOW.
The outputs may be disabled at any time by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active
state by switching the enable to a logic LOW.
Regardless of the condition ofE, the outputs will go to the OFF or
high-impedance state upon the next positive clock edge after the
synchronous enable (Es) input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW, the subsequent
positive clock edge will return the output to the active state ifE is
LOW. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output
will occur until the next LOW-to-HIGH transition of the clock.
This unique feature allows the CY7C235 decoders and sense amplifiers to access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system
clock without introducing race conditions. The on-chip register
timing requirements are similar to those of discrete registers available in the market.
The CY7C235 has an asynchronous initialize input (INIT). The
initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated
functions such as a built-in "jump start" address. When activated
the initialize control input causes the contents of a user programmed 1025th 8-bit word to be loaded into the on-chip register.
Each bit is programmable and the initialize function can be used to
load any desired combination of Is and Os into the register. In the
unprogrammed state, activating INIT will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize word are
programmed, activating INIT performs a register PRESET (all
outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the master and slave flip-flops
of the register, independent of all other inputs, including the clock
(CP). The initialize data will appear at the device outputs after the
outputs are enabled by bringing the asynchronous enable (E)
LOW.
When power is applied the (internal) synchronous enable flip-flop
will be in a state such that the outputs will be in the high-impedance
state. In order to enable the outputs, a clock must occur and the Es
input pin must be LOW at least a set-up time prior to the clock
LOW-to-HIGH transition. The Einput may then be used to enable
the outputs.
When the asynchronous initialize input, INIT, is LOW, the data in
the initialize byte will be asynchronously loaded into the output
register. It will not, however, appear on the output pins until they
are enabled, as described in the preceding paragraph.
3-19
I
_
&l:.~
CY7C235
'= CYPRESS
~F
SEMICONDUCTOR
Switching Characteristics Over Operating Range[3, 5]
7C235-25
Parameter
Description
Min.
tSA
Address Set-Up to Clock HIGH
25
0
Max.
7C235-30
Min.
Max.
30
7C235-40
Min.
Max.
40
Unit
ns
tHA
Address Hold from Clock HIGH
teo
Clock HIGH to Valid Output
tpwc
Clock Pulse Width
12
15
20
tSES
Es Set-Up to Clock HIGH
10
10
15
ns
tHES
Es Hold from Clock HIGH
5
5
5
ns
0
12
0
15
ns
20
ns
ns
tDI
Delay from INIT to Valid Output
tRI
INIT Recovery to Clock HIGH
20
20
20
tPWI
INIT Pulse Width
20
20
25
teas
Inactive to Valid Output from Clock HIGH[8]
20
20
25
ns
tHze
Inactive Output from Clock HIGH[8]
20
20
25
ns
tDaE
Valid Output from E LOW
20
20
25
ns
tHZE
Inactive Output from E HIGH
20
20
25
ns
25
Note:
8. Applies only when the synchronous (Es) function is used.
Switching Waveforms[5]
3-20
25
35
ns
ns
ns
~~
~.CYPRESS
CY7C235
~_, SEMICONDUCTOR
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function[9]
Read or Output Disable
Ao,A3 - A9
Al
A2
CP
Es
E
INIT
07 - 00
Other
Ao,A3 - A9
Al
A2
PGM
VFY
E
Vpp
D7 - Do
I
Read
Ao,A3 - A9
Al
A2
X
VIL
VIL
VIH
07 - 00
:E
Output Disable
Ao,A3 - A9
Al
A2
X
VIH
X
VIH
HighZ
Output Disable
Ao,A3 - A9
Al
A2
X
X
VIH
VIH
HighZ
Initialize
Ao,A3 - A9
Al
A2
X
X
VIL
VIL
Init Byte
Mode
Program
Ao,A3 - A9
Al
A2
VILP
VIHP
VIHP
Vpp
D7- D O
Program Verify
Ao,A3 - A9
Al
A2
VIHP
VILP
VIHP
Vpp
07 - 00
Program Inhibit
Ao,A3 -A9
Al
A2
VIHP
VIHP
VIHP
Vpp
HighZ
Intelligent Program
Ao,A3 - A9
Al
A2
VILP
VIHP
VIHP
Vpp
D7 - Do
Program Initialize Byte
Ao,A3 - A9
Vpp
VILP
VILP
VIHP
VIHP
Vpp
D7 - Do
VILP
VILP
VILP
Ones
VIHP
VILP
VILP
Zeros
Blank Check Ones
Ao,A3 - A9
Al
A2
Vpp
Blank Check Zeros
Ao,A3 - A9
Al
A2
Vpp
Note:
9. X = "don't care" but not to exceed Vee ±5%.
DIP
Top View
LCCIPLCC
Top View
if:t8
22
Ao >9
21
NC>10
20
Do >11
19
, 1213141516!?]!l
~
As
E
A3
A2
Vpp
VFY
PGM
D7
D6
D5
5
>6
>7
Q [j' ~ S). ~ ~
D4
C)
D3
C235-8
Figure 1. Programming Pinouts
3-21
cr
E
Vpp
'VFY
PGM
NC
D7
D6
C235-9
en
oa:
Q.
~
==- .~
~ ill CYPRESS
CY7C235
~, SEMICONDUCTOR
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
w
NORMALIZED CLOCK TO
OUTPUT TIME vs. Vee
~
I::l
1.6
a.
I-
() 1.4
.2
0
w
N 1.2
/v
::J
«
::2
a: 1.0
0
z
0.8
0.6
1/
~o
/
V
N
t)
«
::2
() 1.0
0
W
~
w
::J 1.0
TA = 25°C
~o
ao
~5
1.4
a.
en
0
a:
«
::2
50
gj
40
a:
()
t5a:
30
@
20
0.4
4.0
I-
~
o
10
a
a
5.0
5.5
SUPPLY VOLTAGE
1.0
'"
-
:l:
~
'"
2.0
OUTPUT VOLTAGE
~4.0
M
1.2
::J
«
1.0
Z
0.8
::2
a:
0
0.6
-55
6.0
--
15.0
/~
5.0
0.0
/
,,/
V
a
400
600
I
800 1000
CAPACITANCE (pF)
125
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
7
COLUMN
ADDRESS
C235A-2
LCC/PLCC
01
'ThpView
Ao
~~<~~:t~
00
4 3 2,1,282726"'
~ >~
CP
Es
A2
A1
7
8
NC
9
10
11
Ao
00
E
-
~~
23
22
21
20
19
12131415161718
C235A-1
C235A-3
Selection Guide
Maximum Set-Up Time (us)
Maximum Clock to Output (us)
i Commercial
Maximum ~erating
Current (rnA
I Military
7C235A-18
18
12
7C235A-25
25
12
7C235A-30
30
15
90
nn
nn
::IV
90
120
120
120
::IV
3-24
7C235A-40
40
20
-.-
~~
--=-,
PRELIMINARY
_'iECYPRESS
CY7C235A
SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. Ambient Temperature with
Power Applied ...................... Supply Voltage to Ground Potential
(Pin 24 to Pin 12 for DIP) ...............
DC Voltage Applied to Outputs
in High Z State ........................
DC Input Voltage ......................
DC Program Voltage (Pins 7, 18, 20 for DIP)
65°C to +150°C
55 ° C to + 125 ° C
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ±10%
Industrial[l]
-40°C to +85°C
5V ±1O%
Military[2]
- 55°C to + 125°C
5V ±1O%
Range
Commercial
- 0.5V to +7.0V
- 0.5V to +7.0V
- 3.0V to +7.0V
......... 13.0V
Electrical Characteristics Over Operating Rangel 3]
Description
Parameter
Min.
Test Conditions
Max.
Unit
2.4
V
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VIN = VIR or VIL
VOL
Output LOW Voltage
Vee = Min., IOL = 16 rnA
VIN = VIR or VIL
VIR
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs[4]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for
All Inputs[4]
IIX
Input Leakage Current
GND S VIN S Vee
VeD
Input Clamp Diode Voltage
Note 5
loz
Output Leakage Current
GND s VOUT s Vee Output Disabled[4]
-10
+10
f.tA
los
Output Short Circuit Current
Vee = Max., VOUT = 0.OV[6]
-20
-90
rnA
Icc
Power Supply Current
lOUT = ornA,
Vee = Max.
90
rnA
Vpp
Programming Supply Current
VIRP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
2.0
-10
I Commercial
rMilitary
V
0.8
V
+10
f.tA
120
12
Programming Supply Voltage
Ipp
V
0.4
13
V
50
rnA
3.0
V
0.4
V
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, Vee =5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
3-25
Max.
Unit
10
pF
10
pF
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
•
en
:t
o
a:
Q.
SF4
=:s
;iE CYPRESS
_
JF
PRELIMINARY
CY7C235A
SEMICONDUcrOR
AC Test Loads and Waveforms[5]
R1250Q
OUTP~~~
FI
50 P
INCLUDING _
JIG AND SCOPE
_
-
R2
16m
R1250Q
OUTP~~31
5
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
PFI
ALL INPUT PULSES
R2
16m
3.0V - - - -~-----~
90%
GND
_
C235A-4
C235A-5
(b) High Z Load
THEVENIN EQUIVALENT
100Q
OUTPUT O'O---'II
...""J'.....----oo 2.0V
C235A-6
Operating Modes
The CY7C235A incorporates a D-type, master-slave register on
chip, reducing the cost and size of pipelined microprogrammed
systems and applications where accessed PROM data is stored
temporarily in a register. Additional flexibility is provided with
synchronous (Es) and asynchronous (E) output enables and
asynchronous initialization (INIT).
Upon power-up, the synchronous enable (Es) flip-flop will be in
the set condition causing the outputs (00 - 07) to be in the OFF
or high-impedance state. Data is read by applying the memory location to the address input (Ao - A9) and a logic LOW to the enable (Es) input. The stored data is accessed and loaded into the
master flip-flops of the data register during the address set-up ti me.
At the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output buffers,
and the accessed data will appear at the outputs (00 - 07), provided the asynchronous enable (E) is also Law.
The outputs may be disabled at anytime by switching the asynchronous enable (E) to a logic HIGH, and may be returned to the active
state by switching the enable to a logic Law.
Regardless of the condition ofE, the outputs will go to the OFF or
high-impedance state upon the next positive clock edge after the
synchronous enable (Es) input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic Law, the subsequent
positive clock edge will return the output to the active state ifE is
Law. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output
will occur until the next LOW-to-HIGH transition of the clock.
This unique feature allows the CY7C235Adecoders and sense amplifiers to access the next location while previously addressed data
remains stable on the outputs.
System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system
clock without introducing race conditions. The on-chip register
timing requirements are similar to those of discrete registers available in the market.
The CY7C235A has an asynchronous initialize input (INIT). The
initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophisticated
functions such as a built-in "jump start" address. When activated
the initialize control input causes the contents of a user programmed 1025th 8-bit word to be loaded into the on-chip register.
Each bit is programmable and the initialize function can be used to
load any desired combination of Is and Os into the register. In the
unprogrammed state, activating INIT will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize word are
programmed, activating INIT performs a register PRESET (all
outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the master and slave flip-flops
of the register, independent of all other inputs, including the clock
(CP). The initialize data will appear at the device outputs after the
outputs are enabled by bringing the asynchronous enable (E)
Law.
When power is applied the (internal) synchronous enable flip-flop
will be in a state such that the outputs will be in the high-impedance
state. In order to enable the outputs, a clock must occur and the Es
input pin must be LOW at least a set-up time prior to the clock
LOW-to-HIGH transition. The E input may then be used to enable
the outputs.
When the asynchronous initialize input, INIT; is Law, the data in
the initialize byte will be asynchronously loaded into the output
register. It will not, however, appear on the output pins until they
are enabled, as described in the preceding paragraph.
3-26
--=-F,~PRFSS
PRELIMINARY
.
CY7C235A
SEMICONDUCTOR
Switching Characteristics Over Operating Range[3, 5]
Parameter
Description
7C235A-18
7C235A-25
7C235A-30
7C235A-40
Min.
Min.
Min.
Min.
Max.
Max.
Max.
tSA
Address Set-Up to Clock HIGH
18
25
30
40
tRA
Address Hold from Clock HIGH
0
0
0
0
teo
Clock HIGH to Valid Output
12
12
15
Max.
Unit
ns
ns
20
ns
tpwe
Clock Pulse Width
12
12
15
20
tSES
Es Set-Up to Clock HIGH
10
10
10
15
ns
tHES
Es Hold from Clock HIGH
5
5
5
5
ns
t01
Delay from INIT to Valid Output
25
20
25
ns
35
ns
tRI
INIT Recovery to Clock HIGH
15
20
20
20
ns
tpWI
INIT Pulse Width
15
20
20
25
ns
teas
Inactive to Valid Output from Clock HIGH[?]
15
20
20
25
ns
tHze
Inactive Output from Clock HIGH[7]
15
20
20
25
ns
tDOE
Valid Output from E LOW
15
20
20
25
ns
tHZE
Inactive Output from E HIGH
15
20
20
25
ns
Note:
7. Applies only when the synchronous (Es) function is used.
Switching Waveforms[5]
+-__~~~l---_+----~QQ~~~QQ£l--------------
AD -A10 ______________________________
CP
00
-
07
3-27
•
en
:is
o
a::
D.
~
.
_
;~PRESS
PRELIMINARY
CY7C235A
. , SEMICONDUCTOR
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function[8)
A2
CP
Es
E
INIT
Al
A2
PGM
VFY
E
Vpp
D7 - Do
Ao,A3 - A9
Al
Az
X
VIL
VIL
VIH
07 - 00
Output Disable
Ao,A3 - A9
Al
Az
X
VIH
X
VIH
HighZ
Output Disable
Ao,A3 - A9
Al
Az
X
X
VIH
VIH
HighZ
Initialize
Ao,A3 - A9
Al
Az
X
X
VIL
VIL
Init Byte
Program
Ao,A3 - A9
Al
Az
VILP
VIHP
VIHP
Vpp
D7 - DO
07- 00
Read or Ontput Disable
Ao,A3 - A9
Al
Other
Ao,A3 - A9
Read
Mode
07 - 00
Program Verify
Ao,A3 - A9
Al
Az
VIHP
VILP
VIHP
Vpp
Program Inhibit
Ao,A3 -A9
Al
Az
VIHP
VIHP
VIHP
Vpp
HighZ
Intelligent Program
Ao,A3 - A9
Al
Az
VILP
VIHP
VIHP
Vpp
D7- D O
Program Initialize Byte
Ao,A3 - A9
Vpp
VILP
VILP
VIHP
VIHP
Vpp
D7- D O
Blank Check
Ao,A3 - A9
Al
Az
VIHP
VILP
VIHP
Vpp
Zeros
Note:
8. X = "don't care" but not to exceed Vee ±S%.
DIP
Top View
LCC/pLCC
Top View
)f:e<~ ~:R~
At
~
A2
Vpp
A1
VFY
rsGM
Ao
NC
Do
D7
D6
Ds
D4
D3
4 3 2,-1,282726
25
24
23
22
21
20
10
19
11
12131415161718
..... (\Ie (.) (").q- L()
oOzzooo
(!)
C235A-8
Figure 1. Programming Pinouts
3-28
E
Vpp
\lr'(
r>miA
NC
D7
D6
C235A-9
~::z.
PRELIMINARY
~=CYPRESS
~_, SEMICONDUcrOR
CY7C235A
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
w
NORMALIZED CLOCK TO
OUTPUT TIME vs. Vee
~
f-
1.6
::J
c..
u1.4
.2
0
w 1.2
~
/1'
...J
«
::E
/
0
z
0.8
/
0.6
~o
V
:::J 1.0
«
~5
~o
a:
0
z 0.9
-
I
oW
25
i= 1.0
c..
1.4
C/)
0
1.0
::E 0.6
«
0
a:
0.4
4.0
125
AMBIENT TEMPERATURE (OC)
20
"'"
10
f-
o
o
o
5.0
5.5
:::J
~
1.0
-
~
g
«
::E
'"'"
2.0
OUTPUT VOLTAGE
3.0
M
1.0
a:
0
z
4.0
M
25
125
AMBIENT TEMPERATURE (0C)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
<",175
/
~
~
z
en
TA = 25°C _
Vee = 4.5V
I
200
400
600
".. ~
125
75
I
800 1000
CAPACITANCE (pF)
c..
f-
::J
o
//
~
100
~ 50
//
V
o
f-
Ii!
a:
6
/
~ 10.0
.s 150
z
/
15.0
0.0
-
0.8
0.6
- 55
6.0
".-
20.0
5.0
6.0
M
----
1.2
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
25.0
f-
~
w
30.0
"'-
::J
0
I
4.5
SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~ 30
a:
::J
SUPPLY VOLTAGE
N
TA = 25°C
z
a: 0.6
55
""
«
:::J 0.8
5.5
::J 1.4
0.8
N
5.0
~
W
N
C,)
4.5
C/)
:::J
,
I
0.6
4.0
NORMALIZED SET-UP TIME
vs. TEMPERATURE
"'~
w
w
~ 40
z
a.
c..
~
w
1.2
50
oa:
1.6
~ r---.....
::J
a:
§
1.2
0
!zw
125
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
W
25
en
::I
TA = 25°C
AMBIENT TEMPERATURE (0C)
::E
::E
0 - 55
z
'"'"
:::J 0.8
M
f-
60
1.0
N
0.8
-55
ao
~5
c..
.s~
9
u
.......
«
::J
~
~
u
9
u
1.2
::E
i= 1.6
f-
1.4
~
u
NORMALIZED CLOCK TO
OUTPUT TIME vs. TEMPERATURE
w
0
~
W
N
TA = 25°C
f = fMAX
SUPPLY VOLTAGE
::J
g
~1.1
0
::E
a: 1.0
::E
----- •
f-
25
o/
0.0
Vee = 5.0V
TA = 25°C -
I
/
J
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
C235A-10
3-29
.;~PRFSS
PRELIMINARY
~, SEMICONDUcrOR
CY7C23SA
Ordering Information[9)
Speed
(ns)
tSA
tco
Ordering Code
Package
Name
18
12
CY7C235A -18DC
D14
24-Lead (300-Mil) CerDIP
CY7C235A -18JC
J64
24-Lead Plastic Leaded Chip Carrier
CY7C235A -18PC
P13
24-Lead (300-Mil) Molded DIP
CY7C235A - 25DC
D14
24-Lead (300-Mil) CerDIP
CY7C235A-25JC
J64
24-Lead Plastic Leaded Chip Carrier
CY7C235A - 25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C235A-25DMB
D14
24-Lead (300-Mil) CerDIP
CY7C235A - 25LMB
L64
28-Square Leadless Chip Carrier
CY7C235A -30DC
D14
24-Lead (300-Mil) CerDIP
CY7C235A-30JC
J64
24-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
25
30
40
12
15
20
Package 'JYpe
CY7C235A - 30PC
P13
CY7C235A-30DMB
D14
24-Lead (300-Mil) CerDIP
CY7C235A - 30LMB
L64
28-Square Leadless Chip Carrier
CY7C235A-40DC
D14
24-Lead (300-Mil) CerDIP
CY7C235A -40JC
J64
24-Lead Plastic Leaded Chip Carrier
CY7C235A -40PC
P13
24-Lead (300-Mil) Molded DIP
CY7C235A -40DMB
D14
24-Lead (300-Mil) CerDIP
CY7C235A-40LMB
L64
28-Square Leadless Chip Carrier
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Note.
9. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
SMD Cross Reference
DC Characteristics
Parameter
Subgroups
Cypress
Number
SMD
Number
Suffix
5962-88636
01KX
CY7C235A -40KMB
5962-88636
01LX
CY7C235A -40DMB
5962-88636
013X
CY7C235A -40LMB
5962-88636
02KX
CY7C235A - 30KMB
VOH
1,2,3
VOL
VIR
1,2,3
1,2,3
VIL
1,2,3
5962-88636
02LX
CY7C235A-30DMB
5962-88636
023X
CY7C235A - 30LMB
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
Document #: 38-00229-A
Switching Characteristics
Parameter
Subgroups
tSA
tHA
7, 8, 9, 10, 11
tco
7, 8, 9, 10, 11
7, 8, 9, 10, 11
3-30
This is an abbreviated datasheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the CY7C245A.
CY7C245
Reprogrammable 2K X 8
Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
- 25 ns max set-up
-12 ns clock to output
• Lowpower
-330 mW (commercial) for -35 ns,
-45 ns
-660 mW (military)
• Programmable synchronous or
asynchronous output enable
• On-chip edge-triggered registers
• P~ammable asynchronous register
(lNIT)
• EPROM technology, 100%
programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V ±10% Vee, commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
2001V static discharge .
Product Characteristics
The CY7C245 is a high-performance
2048-word by 8-bit electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP. The
ceramic package may be equipped with an
erasure window; when exposed to UV
light the PROM is erased and can then be
reprogrammed. The memory cells utilize
proven EPROM floating-gate technology
andbyte-wideintelligentprogrammingalgorithms.
Logic Block Diagram
The CY7C245 replaces bipolar devices
and offers the advantages of lower power,
reprogrammability,superiorperformance,
and high programming yield. The
EPROM cell requires only 12.5V for the
supervoltage and low current requirements allow for gang programming. The
EPROM cells allow each memory location
to be tested 100% because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to
guarantee that after customer programming the product will meet AC specification limits.
The CY7C245 has an asynchronous initialize function (INIT). This function acts as a
2049th 8-bit word loaded into the on-chip
register. It is user programmable with any
desired word, or may be used as a PRESET
or CLEAR function on the outputs. INIT
is triggered by a LOW level, not an edge.
Pin Configurations
DIP
m
----I
")0-----------------,
ROW
DECODER
1 OF 128
128 x 128
PROGRAMMABLE
ARRAY
8·BIT
EDGE·
TRIGGERED
REGISTER
A7
Vee
Aa
Aa
As
As
~
A10
A3
INIT
A2
E/Es
A1
CP
Ao
07
00
06
01
Os
02
04
GND
03
C245-2
A3 _ _
LCC
A2 - - COLUMN 1--_ _ _ _ _ _ _ _---'
A1 _ _ D~~~~~R 1-_ _ _ _ _ _ _ _ _---1
00
;f.'f!iz:J;'.'f~
A o -L -_ _.J
E/---~-I
Es
CP
C245-1
T"""
C\JO U
('I')
oq- LO
0 0 Z zO 0 0
C!J
C245-3
Selection Guide
Maximum Set-up Time (ns)
Maximum Clock to Output (ns)
Maximum 03erating
Current (rnA
STD
L
Commercial
Military
Commercial
3-31
7C245-25
25
12
90
7C245-35
35
15
90
120
60
7C245-45
40
25
90
120
60
•
en
:E
oa::
D..
CY7C245A
Reprogrammable 2K X 8
Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
- l5-ns max set-up
- lOons clock to output
• Lowpower
-330 mW (commercial) for -25 ns
- 660 mW (military)
• Programmable synchronous or
asynchronous output enable
• On-chip edge-triggered registers
• Programmable asynchronous
register (lNIT)
• EPROM technology, 100%
programmable
• Slim, 300-mil, 24-pin plastic or
hermetic DIP
• 5V ±10% Vee, commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
2001V static discharge
Functional Description
The CY7C245A is a high-performance
2048-word by 8-bit electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP. The
ceramic package may be equipped with an
erasure window; when exposed to UV
light the PROM is erased and can then be
reprogrammed. The memory cells utilize
proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices
and offers the advantages of lower power,
reprogrammability, superior performance
and high programming yield. The
EPROM cell requires only 12.5V for the
supervoltage, and low current requirements allow gang programming. The
EPROM cells allow each memory location
to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming
the product will meetAC specification limits.
The CY7C245A has an asynchronous initialize function (INIT). This function acts
as a 2049th 8-bit word loaded into the onchip register. It is user programmable with
any desired word, or may be used as a
PRESET or ClEAR function on the outputs. INIT is triggered by a low level, not an
edge.
Logic Block Diagram
Pin Configurations
DIP
Top View
INlT
Vee
As
07
Ao
Ag
A1
A10
Os
A2
A.J
ROW
ADDRESS
PROGRAMMABLE
ARRAY
05
At.
~
CD
«
A5
As
:::;
ADDRESS
DECODER
:::;
~
A7
Cl
As
!l.
8-BIT
EDGETRIGGERED
REGISTER
04
Oa
0
II:
Ag
02
COLUMN
ADDRESS
A2
INlT
EfEs
A1
CP
Ao
07
00
Os
01
05
A3
02
04
GND
Oa
UU
)f ~J(z-9~ ~
01
A10
00
At.
lUEs
Aa
A2
A1
CP
NC
Ao
00
C245A-1
C245A-2
LCC(PLCC (Opaque only)
Top View
432 1,282726
c
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12131415161718
0
o6"~ ~6'c3'"cf
Cl
A10
INlT
ElEs
CP
NC
07
Os
C245A-3
Selection Guide
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Standard
Maximum 03erating
Current (rnA
L
7C245A-15
15
10
commerciai
Military
Commercial
12U
3-32
7C245A-25
7C245AL-25
25
12
90
120
60
7C245A-35
7C245AL-35
35
15
90
120
60
7C245A-45
7C245AL-45
45
25
90
120
60
.~
--=-.•'
CY7C245A
_ ' j ; ; CYPRESS
,
SEMICONDUcrOR
Maximum Ratings
Static Discharge Voltage ............... , ........ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................... " ..... >200 rnA
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 24 to Pin 12) ...................... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
DC Program Voltage (Pins 7,18,20) ................ 13.0V
UV Erasure ............................. 7258 Wsec/cm 2
Electrical Characteristics
Operating Range
Range
Ambient
Temperature
Commercial
O°C to +70°C
Vee
5V ±1O%
IndustriaIll]
- 40°C to +85°C
5V ±1O%
Military[2]
-55°C to +125°C
5V ±1O%
Description
Test Conditions
Min.
Vee = Min.,IOH = - 4.0 rnA
VIN = VIH or VIL
Vee = Min., IOL = 16 rnA
VIN = VIH or VIL
Guaranteed Input Logical
HIGH Voltage for All Inputs
2.4
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Level
VIL
Input LOW Level
Guaranteed Input Logical
LOW Voltage for All Inputs
IIX
VeD
Ioz
Input Leakage Current
Input Clamp Diode Voltage
Output Leakage Current
GND ~ VIN ~ Vee
los
lee
Output Short Circuit Current Vee = Max., VOUT =0.OVl6J
Power Supply Current
ICom'l
Vee = Max.,
lOUT = 0 rnA
I Mil
Programming Supply Voltage
Programming Supply Current
Input HIGH
Programming Voltage
VIHP
VILP
oa:
a.
VOH
Vpp
Ipp
en
:IE
Over the Operating Rangel 3, 4]
7C245A-15
Parameter
I
Max.
r
7C245AL-25
7C245AL-35
7C245AL-45
Min.
Min.
Vee
2.0
0.8
Max.
2.4
0.4
0.4
2.0
Max.
2.4
Vee
2.0
0.8
Unit
V
0.4
V
Vee
V
0.8
V
+10
Note 4
-10
+10
-10
+10
-10
+10
!JA
-10
+10
-10
+10
!JA
-20
-20
-90
90
120
13
50
-20
-90
60
rnA
rnA
12
13
50
V
rnA
V
0.4
V
-10
GND~ Vo~ Ve
Output Disabled[5
7C245A-25
7C245A-35
7C245A-45
12
-90
120
120
13
50
3.0
3.0
Input LOW
Programming Voltage
12
0.4
3.0
0.4
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
3-33
Max.
Unit
10
pF
10
pF
See the "Introduction to CMOS PROMs" section ofthe Cypress Data
Book for general information on testing.
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
'~~PRFSS
CY7C245A
~, SEMICONDUcrOR
AC Test Loads and Waveforms[3, 4]
R1250Q
R1250Q
OUTPUT
5V31
50 pF
R2
16m
I _
INCLUDING
JIG AND SCOPE
-
OUTP~~31
I
5 PF
INCLUDING _
JIG AND SCOPE
(a) Normal Load
ALL INPUT PULSES
3.0V - - - -..J.,j~9~0~%----s,.;
R2
167Q
GND
_
C245A-5
C245A-4
(b) High Z Load
Equivalent to:
THE'vENIN EQUIVALENT
100Q
OUTPUT OO--_.NY......--.()O 2.0V
C245A-6
Switching Characteristics Over Operating Rangd3, 4]
Description
Parameter
7C245A-15
7C245A-25
7C245AL-25
Min.
Min.
Max.
Max.
7C245A-35
7C245AL-35
7C245A-45
7C245AL-45
Min.
Min.
Max.
Max.
Unit
tSA
Address Set-Up to Clock HIGH
15
25
35
45
tHA
Address Hold from Clock HIGH
0
0
0
0
teo
Clock HIGH to Valid Output
tpwc
Clock Pulse Width
10
15
20
20
ns
tSES
Es Set-Up to Clock HIGH
10
12
15
15
ns
tHES
Es Hold from Clock HIGH
5
5
5
5
tm
Delay from INIT to Valid Output
tRI
INIT Recovery to Clock HIGH
10
15
20
20
tPWI
INIT Pulse Width
10
15
20
25
teas
Valid Output from Clock HIGH[7]
15
15
20
30
ns
tHze
Inactive Output from Clock HIGH[7]
15
15
20
30
ns
tDOE
Valid Output from E LOW[8]
12
15
20
30
ns
tHZE
Inactive Output from E HIGH[8]
15
15
20
30
ns
12
10
15
20
15
ns
ns
25
20
ns
ns
35
ns
ns
ns
Notes:
8.
7. Applies only when the synchronous (Es) function is used.
Applies only when the asynchronous (E) function is used.
Operating Modes
The CY7C245A is a CMOS electrically programmable read only
memory organized as 2048 words x 8 bits and is a pin-for-pin replacement for bipolar TIL fusible link PROMs. The CY7C245A
incorporates a D-type, master-slave register on chip, reducing the
cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with a programmable synchronous (Es) or asynchronous (E) output enable and
asynchronous initialization (INIT).
Upon power-up the state of the outPtEs wi!!. depend on the programmed state ofthe enable function (Es or E). If the synchronous
enable (Es) has been programmed, the register will be in the set
condition causing the outputs (00 - 07) to bein the OFF or highimpedance state. If the asynchronous enable (E) is being used, the
outputs will come up in the OFF or high-impedance state only if
the enable (E) input is at a HIGH logic level. Data is read by applying the memory location to the address inputs (Ao - AlO) and a
logic LOW to the enable input. The stored data is accessed and
loaded into the master flip-flops of the data register during the ad-
dress set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which drive
the output buffers, and the accessed data will appear at the outputs
(00 - 07)'
If the asynchronous enable (E) is being used, the outputs may be
disabled at any time by switching the enable to a logic HIGH, and
may be returned to the active state by switching the enable to a logicLOW.
If the synchronous enable (Es) is being used, the outputs will go to
the OFF or high-impedance state upon the next positive clock edge
after the synchronous enable input is switched to a HIGH level. If
the synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the output to the active state.
Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This
unique feature allows the CY7C245A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
3-34
-
.
::~:
CY7C245A
'iIi CYPRESS
- , SEMICONDUCTOR
Operating Modes (continued)
System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be derived directly from the system
clock without introducing race conditions. The on-chip register
timing requirements are similar to those of discrete registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT). The
initialize function is useful during power-up and time-out sequences and can facilitate implementation of other sophis~icated
functions such as a built-in "jump start" address. When actIvated,
the initialize control input causes the contents of a user-programmed 2049th 8-bit word to be loaded into the on-chip register.
Each bit is programmable and the initialize function can be used to
load any desired combination of Is and Os into the register. In the
unprogrammed state, activating INIT will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize word are
programmed, activating INIT performs a register PRESET (all
outputs HIGH).
Applying a LOW to the INIT input causes an immediate .toad of
the programmed initialize word into the master and slave fhp-flops
of the register, independent of all other inputs, including the clock
(CP). The initialize data will appear at the device outputs after t~e
outputs are enabled by bringing the asynchronous enable (E)
LOW.
I
en
:i
oa::
Switching Waveforms[4]
~
+-__
~-A1O __________________________
~~~--_+--~~~~~~~-----------
CP
E __________~_+------------------------------JI
C245A-7
Erasure Characteristics
BitMap Data
Wavelengths of light less than 4000 Angstroms begin to erase the
7C245A. For this reason, an opaque label should be placed over
the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a wavelength of 2537 Angstroms for a minimum dose (UV inte.nsity multiplied by exposure time) of 2? Wsec/cm2. For aJ?- ultraVIOlet lamp
with a 12 m W/cm2 power ratmg the exposure tIme would be approximately 35 minutes. The 7C245A needs to be within 1 i~ch of
the lamp during erasure. Permanent damage may result If th~
PROM is exposed to high-intensity UV light for an extended penod oftime. 7258 Wsec/cm2 is the recommended maximum dosage.
Programming Information
Programmer Address
RAM Data
Decimal
Hex
Contents
0
0
Data
2047
7FF
Data
2048
800
Init Byte
2049
801
Control Byte
Control Byte
Programming support is available from Cypress as well as from
a number of third-party software vendors. For detailed programming information, including alisting of software packages,
please see the PROM Programming Information located a~ the
end of this section. Programming algorithms can be obtamed
from any Cypress representative.
3-35
00 Asynchronous output enable (default state)
01 Synchronous output enable
~~
~=CYPRESS
CY7C245A
~_, SEMICONDUCTOR
Table 1. Mode Selection
Pin Function[9)
A4
A4
A3
A3
A2 -AI
Read
AlO-~
A3
Az -AI
Read or Output Disable
Mode
Other
AIO AIO -
Ao
Ao
An
An
An
An
An
An
An
A2 -AI
Output Disable
AlO-~
A3
Az - Al
Initialize
AlO-~
A3
Az - Al
CP
E,Es
INIT
07 - 00
PGM
VFY
Vpp
D7 - Do
VnJVIH
VIL
VIH
07 - 00
X
VIH
VIH
HighZ
X
VIL
VIL
Init. Byte
VILP
VIHP
Vpp
D7- D O
VIHP
VILP
Vpp
07 - 00
VIHP
VIHP
Vpp
HighZ
VILP
VIHP
Vpp
D7- Do
Program
AlO-~
A3
Az-AI
Program Verify
AlO-~
A3
Az - Al
Program Inhibit
AlO-~
A3
Az-AI
Intelligent Program
AlO-~
A3
Az - Al
Program Synchronous Enable
AlO-~
VIHP
Az -AI
Vpp
VILP
VIHP
Vpp
HighZ
Program Initialization Byte
AlO-~
VILP
Az - Al
Vpp
VILP
VIHP
Vpp
D7 - Do
Blank Check Zeros
AlO-~
A3
Az -AI
An
VIHP
VILP
Vpp
Zeros
Note:
9. X = "don't care" but not to exceed Vee +5%.
LCCIPLCC (Opaque Only)
Top View
DIP
Top View
)f:t!/i~~~
Vcc
21
As
Ag
AlO
Vpp
'i/F'Y
~
4 3 2,1, 282726
25 A10
24 Vpp
023'i/F'Y
22 J5GJ.il
21
NC
20 D7
19
1112131415161718
D6
5
A3 6
A27
A1 8
Ao 9
NC 10
J5m.:f
Do
D7
D6
Ds
D4
D3
o8
~ ~ ~6
CJ
C245A-8
Figure 1. Programming Pinouts
3-36
cr
C245A-9
~
•
,
;~PRFSS
SEMICONDUCTOR
CY7C245A
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
N
::J
i= 1.6
~
a..
()1.4
.2
aw
/
1.2
~
a: 1.0
z
~
0
0.8
,/'
0.6
4.0
4.5
~ 1.2
N
::J 1.0
()
~
9 1.0
()
«
a:
z 0.9
aw
0
TA = 25°C
f = fMAX
5.0
SUPPLY VOLTAGE
-
I
5.5
NO.8
0.8
-55
6.0
~
i= 1.6
:::>
1.2
a..
w
:::> 1.4
i= 1.0
a..
:::>
f-!.
w
en
a 0.8
w
~
I-
9
0
1.2
()
9
1.0
«
~
N
a:
::J 0.8
«
- 55
25
125
~
"
TA = 25°C
() 0.98
..9
I
5.0
5.5
\
0.96
""r---
N
~ 0.94
~
~ 0.92
z
-
10....
0.90
o
25
50
75
CLOCK PERIOD (ns)
100
~
~
5.0
/'/
« 175
§.. 150
I-
~
enz
600
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
3 100
TA = 25°C _
Vee = 4.5V
400
AMBIENT TEMPERATURE (0C)
~ 125
I
200
0.6L-.._ _ _..L..._ _ _ _ _.....
-55
25
125
z
//
V
«
~
a:
oz
a:
/
15.0
1.41------+-------1
M
/
20.0
~ 10.0
6.0
M
N
6.0
".-
25.0
~
5.5
::J
1
4.5
30.0
Vee = 5.5V TA= 25°C _
5.0
w
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
I
4.5
SUPPLY VOLTAGE
g,
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
\
I
en
a
SUPPLY VOLTAGE
1.00
a.
TA = 25°C
0.6
~
4.0
f-!.
w
0.6
0.4
4.0
oa:
NORMALIZED SET·UP TIME
vs. TEMPERATURE
AMBIENT TEMPERATURE (0C)
1.02
0.88
'"
z
~
fi1
"
0
a: 0.6
en
:::E
~
1.6 r - - - - - - , - - - - - - - - ,
::J
w
z
~
N
a
0
125
~
~
NORMALIZED SET·UP TIME
vs. SUPPLY VOLTAGE
I-
()
25
----
AMBIENT TEMPERATURE (0C)
M
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
w
•
~ 1.4
o
6
Jl1.1
aw
~~
«
~
CLOCK TO OUTPUT TIME
vs. Vee
~
I
800 1000
CAPACITANCE (pF)
75
~
50
~
25
a..
o
/
oV
0.0
J
/
/
~
Vee = 5.0V
TA = 25°C -
I
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
C245A-10
3-37
:S:~PRE§
~,
CY7C245A
SEMICONDUcroR
Ordering Information[lO]
Speed (ns)
Icc
tSA
teo
(mA)
15
10
120
25
15
60
90
120
35
20
60
90
120
45
25
60
90
120
Ordering
Code
CY7C245A-15JC
CY7C245A....: 15PC
CY7C245A -15WC
CY7C245A-15DMB
CY7C245A -15LMB
CY7C245A -150MB
CY7C245A -15TMB
CY7C245A -15WMB
CY7C245AL-25PC
CY7C245AL-25WC
CY7C245A-25JC
CY7C245A - 25PC
CY7C245A - 25SC
CY7C245A - 25WC
CY7C245A-25DMB
CY7C245A - 25LMB
CY7C245A - 250MB
CY7C245A - 25TMB
CY7C245A - 25WMB
CY7C245AL-35PC
CY7C245AL- 35WC
CY7C245A-35JC
CY7C245A -35PC
CY7C245A -35SC
CY7C245A -35WC
CY7C245A - 35DMB
CY7C245A - 35LMB
CY7C245A -350MB
CY7C245A -35TMB
CY7C245A-35WMB
CY7C245A -45JC
CY7C245A -45PC
CY7C245A -45JC
CY7C245A-45PC
CY7C245A -45SC
CY7C245A -45WC
CY7C245A -45DMB
CY7C245A -45LMB
CY7C245A -450MB
CY7C245A -45TMB
CY7C245A -45WMB
Package
'JYpe
J64
P13
W14
D14
L64
064
T73
W14
P13
W14
J64
P13
S13
W14
D14
L64
064
T73
W14
P13
W14
J64
P13
S13
W14
D14
L64
064
T73
W14
J64
P13
J64
P13
S13
W14
D14
L64
064
T73
W14
Package 1Ype
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless·Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack T73
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack T73
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack T73
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack T73
24-Lead (300-Mil) Windowed CerDIP
Note:
10. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-38
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
~
~aPRESS
~_? SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
CY7C245A
SMD Cross Reference
SMD
Number
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
V IH
VIL
IIX
Ioz
Iec
Switching Characteristics
Parameter
tSA
tHA
teo
Subgroups
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
SuffIX
CY7C245A-45KMB
5962-88735
01KX
5962-88735
OlLX
CY7C245A -45DMB
5962-88735
013X
CY7C245A -45LMB
5962-88735
02KX
CY7C245A - 35KMB
5962-88735
02LX
CY7C245A - 35DMB
5962-88735
023X
CY7C245A - 35LMB
5962-88735
03KX
CY7C245A - 35KMB
5962-88735
03LX
CY7C245A-35DMB
5962-88735
033X
CY7C245A - 25LMB
5962-88735
04KX
CY7C245A - 25KMB
5962-88735
04LX
CY7C245A-25DMB
5962-88735
043X
CY7C245A - 25LMB
5962-87529
01KX
CY7C245A -45TMB
5962-87529
01 LX
CY7C245A-45WMB
5962-87529
013X
CY7C245A-450MB
5962-87529
02KX
CY7C245A - 35TMB
5962-87529
02LX
CY7C245A - 35WMB
5962-87529
023X
CY7C245A - 350MB
5962-89815
01LX
CY7C245A-35WMB
5962-89815
OlKX
CY7C245A-35TMB
5962-89815
013X
CY7C245A - 350MB
5962-89815
02LX
CY7C245A-25WMB
5962-89815
02KX
CY7C245A-25TMB
5962-89815
023X
CY7C245A - 250MB
5962-89815
03LX
CY7C245A -18WMB
5962-89815
03KX
CY7C245A-18TMB
5962-89815
033X
CY7C245A -180MB
Document #: 38-00074-F
3-39
Cypress
Number
•
en
:E
oa::
Q.
CY7C251
CY7C254
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-45ns
• Lowpower
-550 mW (commercial)
- 660 mW (military)
• Super low standby power (7C251)
-Less than 165 mWwhen
deselected
- Fast access: 50 ns
• EPROM technology 100%
programmable
• Slim 300-mil or standard 600-mil
packaging available
• 5V ± 10% Vee, commercial and
military
16K X 8 PROM Power
Switched and Reprogrammable
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding > 2001V static discharge
Functional Description
The CY7C251 and CY7C254 are highperformance 16,384-word by 8-bit CMOS
PROMs. When deselected, the CY7C251
automatically powers down into a lowpower stand-by mode. It is packaged in a
300-mil-wide package. The 7C254 is packaged in a 600-mil-wide package and does
not power down when deselected. The
7C251 and 7C254 are available in reprogrammable packages equipped with an
erasure window; when exposed to UV
light, these PROMs are erased and can
then be reprogrammed. The memory cells
utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms.
The CY7C251 and CY7C254 are plug-in
replacements for bipolar devices and offer
the advantages of lower power, superior performance, and high programming yield. The
EPROM cell requires only 12.5V for the
super voltage, and low current requirements allow for gang programming. The
EPROM cells allow each memory location
to be tested 100% because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming,
the product will meet DC and AC specification limits.
Reading is accomplished by placing all
four chip selects in their active states. The
contents of the memory location addressed by the address lines (Ao - A13)
will become available on the output lines
(00 - 07)·
Pin Configurations
Logic Block Diagram
DIPlFlatpack
Vee
07
A10
An
As
~
A3
A2
A,
Os
As_
~~A2-
A'2
A'3
C"S,
Os
8x10F32
MULTIPLEXER
Ao
04
ADDRESS
DECODER
C"S2
CS3
C"S4
07
Os
Os
04
00
0,
02
GND
03
COLUMN
ADDRESS
03
C251-2
LCC
if~::t:9l~
02
As
~
A3
A2
A,
0,
Ao
00
NC
00
0,
C"S,
C"S2
CS3---""'-J
5
6
7C251
7
8
9
10
7C254
11
12
13
14151617181920
0
C\I()
C"S4
0
A'2
A'3
C"S,
C"S2
CS3
C"S4
NC
07
Os
M() .... l()
OzzOzoo
C251-1
C251-3
C!l
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Standby Current (rnA)
(7C251 only)
Commercial
Military
Commercial
Military
7C251-45, 7C254-45
45
100
7C251-55, 7C254-55
55
100
7C251-65, 7C254-65
65
100
120
120
120
30
35
30
35
30
35
3-40
CY7C251
CY7C254
~
;~PRESS
--=-,
.
SEMICONDUCTOR
Maximum Ratings
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 28 to Pin 14) ...................... - 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State. . . . . . . . . . . .. . . . . . . . .. .. - 0.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage (Pin 22) ...................... 13.5V
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
UV Exposure ........................... 7258 Wsec/cm2
Operating Range
Ambient
Temperature
Range
Commercial
O°C to +70°C
Vee
5V ±1O%
Industrial[l]
-40°C to +85°C
5V ±10%
Military[2]
- 55°C to + 125°C
5V ±1O%
Electrical Characteristics Over the Operating Rangel 3, 4]
7C251-45, 55,65
7C254-45, 55, 65
Parameter
Description
Test Conditions
Min.
Unit
Max.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 16.0 rnA
2.4
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
IIX
Input Current
GND~ VIN~ Vee
VeD
Input Diode Clamp Voltage
loz
los
Output Leakage Current
GND ~ VOUT ~ Vee, Output Disabled
- 40
+40
f.lA.
Output Short Circuit CurrendS]
Vee
- 20
- 90
rnA
Icc
Power Supply Current
= Max., VOUT = GND
Vee = Max., lOUT = 0 rnA
rnA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
ISB
Standby Supply Current
(7C251)
Vpp
Programming Supply Voltage
lpp
Programming Supply Current
V IRP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
Vee
V
0.5
V
V
- 10
0.8
V
+10
f.lA.
Note 4
Yce = Max.,
CSI = VIR, lOUT = 0 rnA
Com'l
100
Mil
120
Com'l
30
Mil
rnA
35
12
13
V
50
rnA
V
3.0
0.4
V
Capacitance[4]
Parameter
C1N
COUT
Description
Input Capacitance
Output CapacItance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
10
10
Unit
pF
pF
Notes:
1.
2.
3.
Contact a Cypress representative regarding industrial temperature
range specification.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
4.
5.
3-41
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
•
en
::i
oa:
Q.
CY7C251
CY7C254
. ::~
_'=CYPRESS
--=-,
SEMICONDUcrOR
AC Test Loads and Waveforms[4]
OUTP~~,~R1
5V31R1235Q
OUTPUT
30 pF
R2
159Q
I _
INCLUDING
JIG AND SCOPE
5 PF
I
-
GND
R2
159Q
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
3.0V - - - -..L~~---~
235Q
_
C251-5
C251-4
(b) High Z Load
THEVENIN EQUIVALENT
95Q
OUTPUT O'O-_....I·""
...•....- - - Q O 2.02V
C251-6
Switching Characteristics Over the Operating Rangd 2, 4]
7C251-45
7C254-45
Parameter
Description
Min.
Max.
7C251-55
7C254-55
Min.
Max.
7C251-65
7C254-65
Min.
Max.
Unit
tAA
Address to Output Valid
45
55
65
ns
tHZCSl
Chip Select Inactive to High Z[6]
25
30
35
ns
tHZCS2
Chip Select Inactive to High Z (7C251, CSl Only)
50
60
70
ns
tACSl
Chip Select Active to Output Valid[6]
25
30
35
ns
tACS2
Chip Select Active to Output Valid (7C251, CSl Only)
50
60
70
ns
tpu
Chip Select Active to Power Up (7C251)
tpD
Chip Select Inactive to Power Down (7C251)[7]
0
0
50
ns
0
60
70
ns
Switching Waveform[4, 7]
tpu
tpD
VCG
SUPPLY
CURRENT
Ao - A13
ADDRESS
50%
:}SO%
)(
)K
)r
-tAA
-
-tAGS
tHZGS
C251-7
Notes:
6. tHZCSl and tACSl refers to 7C254 (all chip selects); and 7C251 (CS2,
CS3 and CS4 only).
7.
3-42
Power-down controlled by 7C251 CSl only.
-.
CY7C251
CY7C254
'l~
---=-,
====' IE
CYPRF.SS
SEMICONDUCTOR
Erasure Characteristics
Blankcheck
Wavelengths of light less than 4000 angstroms begin to erase the
7C251 and 7C254 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of
time.
Blankcheck is accomplished by performing a verify cycle (VFY
toggles on each address), sequencing through all memory address
locations, where all the data read will be zeros.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity x exposure time) of 25 Wsec/cm 2. For an ultraviolet lamp with a 12
mW/cm 2 power rating, the exposure time would be approximately
35 minutes. The 7C251 or 7C254 needs to be within 1 inch of the
lamp during erasure. Permanent damage may result if the PROM
is exposed to high-intensity UV light for an extended period of
time. 7258 Wsec/cm2 is the recommended maximum dosage.
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end ofthis
section. Programming algorithms can be obtained from any Cypress representative.
Programming Information
Table 1. Mode Selection
Pin Function[8]
1\0
A13 - 1\0
A13 - Ao
AI3 - Ao
A13 - Ao
A13 - Ao
A13 - Ao
AI3 - Ao
A13 - Ao
AI3 - Ao
AI3 - Ao
Read or Output Disable
Mode
Al3 -
Other
Read
Output Disable
Output Disable
Output Disable
Output Disable
Program
Program Verify
Program Inhibit
Blank Check
CS4
CS3
CS2
CSl
NA
VFY
Vpp
PGM
D7 - Do
VIL
VIH
VIL
VIL
07 - 00
X
X
X
VIH
HighZ
X
X
VIH
X
HighZ
X
VIL
X
X
HighZ
VIH
X
X
X
HighZ
X
VIHP
Vpp
VILP
D7- D O
X
VILP
Vpp
VIHP
07 - 00
X
VIHP
Vpp
VIHP
HighZ
VILP
Vpp
VIHP
07 - 00
X
Note:
8.
X = "don't care" but not to exceed Vee ±5%.
PLCC
DIP/Flatpack
Top View
Top View
A5
Vee
AlO
A11
A12
A1a
A.!
PGM
Aa
A2
A1
I>-{J
vpp
Ag
Aa
A7
Aa
Do
D1
D2
GND
A5
5
A.!
6
Aa
7
~
VFY
NA
D7
D6
D5
D4
Da
07 - 00
NC
Do
D1
7C251
t0
11
7C254
12
13
14151617181920
NU 0 MU .... ."
Z zo zoo
o
C251-S
Figure 1. Programming Pinout
3-43
CJ
C251-9
•
en
:E
o
a:
a..
CY7C251
CY7C254
-c:,~
~=CYPRESS
......... ,
SEMICONDUCIOR
lYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.2
w
~
~1.4
o
~ 1.2
./
V
:::i
<
~
15
1.0
z
0.8
./
V
TA
I
4.5
5.0
<
N
:::i
0.9
I-----+----..:::!II~---l
0.8 '--_ _ _.J.--_ _ _ _ _.....J
-55
25
125
oz
I-
z
w
TA = 25°C
0.4
4.0
1.2
(.)
w
(.)
a::
0
CJ)
I-
::>
a:: 0.8
0
~
30
'" ~
20
10
::>
o
0
1.0
~
2.0
~
M
5.0
""
4.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~ 175
.s 150
I-
~~
z
~ 125
a::
/
B 100
~
z
Ci5
75
~ 50
a.
I-
5
25
/
oV
0.0
I
V
/
Vee = 5.0V
TA = 25°C -
I
1.0
2.0
3.0
OUTPUT VOLTAGE
3-44
/
~ 10.0
3.0
OUTPUT VOLTAGE
AMBIENT TEMPERATURE (0C)
/
=::
"'
o
20.0
.... 15.0
""- .........
a.
125
5.5
6.0
M
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
~
I-
Z
5.0
25.0
50
::>
1.0
<
~
1
4.5
30.0
a::
a::
::> 40
25
0.6
SUPPLY VOLTAGE
.s
1.4
0.6
- 55
~
~
OUTPUT SOURCE CURRENT
vs. VOLTAGE
~ 60
0
w
0.8
w
AMBIENT TEMPERATURE (0C)
1.6
---r--
I--...
N
M
w
(.)
(.)
~
o
a::
6.0
5.5
~
CJ)
CJ)
1.0 I-------::~-----~
~
oz
r----
(.)
w
a::
NORMALIZED ACCESS TIME
vs. TEMPERATURE
i=
w
~
= 25°C -
SUPPLY VOLTAGE
w
o
f = fMAX
,/'
0.6
4.0
~ 1.0
N
./
i=
~ 1.1 I-~--+-------I
M
4.0
0.0
/
...v
/'
/V
o
/'
Vee = 4.5V _
TA = 25°C
I
I
200
400
600
800 1000
CAPACITANCE (pF)
CY7C251
CY7C254
L~PRFSS
~I
SEMICONDUCTOR
Ordering Information[9]
Speed
(ns)
45
55
65
Speed
(ns)
45
55
65
Ordering Code
CY7C25I-45PC
CY7C25I-45WC
CY7C25I-45DMB
CY7C25I-45WMB
CY7C25I-55PC
CY7C25I-55WC
CY7C25I-55DMB
CY7C25I-55LMB
CY7C25I-55QMB
CY7C25I-55WMB
CY7C25I-65PC
CY7C25I-65WC
CY7C25I-65DMB
CY7C25I-65LMB
CY7C25I-65QMB
CY7C25I-65WMB
Ordering Code
CY7C254-45PC
CY7C254-45WC
CY7C254-45DMB
CY7C254-45WMB
CY7C254 - 55PC
CY7C254-55WC
CY7C254-55DMB
CY7C254-55QMB
CY7C254-55WMB
CY7C254-65PC
CY7C254-65WC
CY7C254-65DMB
CY7C254-65QMB
CY7C254-65WMB
Package
Name
P2I
W22
D22
W22
P2I
W22
D22
L55
Q55
W22
P2I
W22
D22
L55
Q55
W22
Package
Name
PI5
WI6
DI6
WI6
PI5
WI6
DI6
Q55
WI6
PI5
WI6
DI6
Q55
WI6
Package 1Ype
28-Lead (3OO-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
Package 1YPe
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) Molded DIP
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
Note:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-45
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Military
•
CY7C251
CY7C254
~
-.
~~NDUcroR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
VIR
1,2,3
1,2,3
VIL
Ilx
1,2,3
Ioz
Icc
ISB[lO]
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
tAA
tACSl[ll]
tACS2[1O]
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
SMD Cross Reference
SMD
Number
Cypress
Number
Suffix
5962-8953701
YX
CY7C251-65WMB
5962-8953701
ZX
CY7C251-65TMB
5962-8953701
VX
CY7C251-65QMB
5962-8953702
YX
CY7C251-55WMB
5962-8953702
ZX
CY7C251-55TMB
5962-8953702
VX
CY7C251-55QMB
5962-8953801
XX
CY7C254-65WMB
5962-8953801
ZX
CY7C254-65TMB
5962-8953801
VX
CY7C254-65QMB
5962-8953802
XX
CY7C254-55WMB
5962-8953802
ZX
CY7C254-55TMB
5962-8953802
VX
CY7C254-55QMB
Notes:
10. 7C251 (CSl only).
11. 7C254 and 7C251 (CS2, CS3 and CS4 only).
Document #: 38-00056-G
3-46
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-45 ns (commercial)
- 55 ns (military)
• Lowpower
- 250 mW (commercial)
- 300 mW (military)
• Super low standby power
-Less than 75 mWwhen
deselected
• EPROM technology 100%
programmable
• Direct replacement for bipolar
PROMs
CY7C256
32K X 8 PROM Power
Switched and Reprogrammable
• Capable of withstanding >2001V
static discharge
Functional Description
The CY7C256 is a high-performance
32,768-word by 8-bit CMOS PROM.
When disabled (CE HIGH), the
CY7C256 automatically powers down
into a low-power stand-by mode. The
CY7C256 is packaged in the industry
standard 600-mil package. The CY7C256
is available in a cerDIP package equipped
with an erasure window to provide for reprogrammability. When exposed to UV
light, the PROM is erased and can be reprogrammed. The memory cells utilize
proven EPROM floating gate technology
and byte-wide intelligent programming algorithms.
Logic Block Diagram
The CY7C256 offers the advantage of lower power and superior performance and
programming yield. The EPROM cell requires only 12.5V for the super voltage, •
and low current requirements allow for
gang programming. The EPROM cells allow each memory location to be tested U)
100% because each location is written :E
into, erased, and repeatedly exercised 0
prior to encapsulation. Each PROM is a::
also tested for AC performance to guar- Q.
antee that after customer programming,
the product will meet DC and AC specification limits.
Reading the CY7C256 is accomplished by
~cing active LOW signals on OE and
CEo The contents of the memory location
addressed by the address lines (Ao - A14)
will become available on the output lines
(00 - 07)·
Pin Configurations
A14
A 13
A10
06
ROW
ADDRES
8x10F128
MULTIPLEXER
Ag
Os
As
A7
As
ADD RES
DECODE
04
As
~
A3
A2
LCC/PLCC (Opaque Only)!!]
DIP/Flatpack
A12
A11
03
COLUMN
ADDRES
02
A1
Vpp
Vee
A12
A7
A13
As
As
As
As
~
A3
A2
OE
~~J~J31;
A14
An
A10
A1
CE
Ao
07
06
00
01
O2
Os
GND
03
432:'.1,323130
As
29
5
28
7C256
6
27
7
26
8
25
9
24
10
23
Ao 11
22
NC 12
21
00 13
'" 14151617181920
As
~
A3
A2
A1
0
T"""
NQt)
('I')
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
UV Exposure ........................... 7258 Wsec/cm2
Operating Range
Ambient
Temperature
Range
Commercial
O°Cto +70°C
Vee
5V ±1O%
Industrial[3]
-40°C to +85°C
5V ±1O%
Military[4]
- 55°C to + 125°C
5V ±1O%
Electrical Characteristics Over the Operating RangerS]
7C256- 45, 55
Parameter
Description
Min.
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 rnA[6]
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs
VIL
Input LOW Level
Max.
Unit
V
2.4
0.4
V
2.0
Vee
V
Guaranteed Input Logical LOW Voltage for All
Inputs
-0.3
0.8
V
IIX
Input Current
GND ~ VIN ~ Vee
-10
+10
~
Ioz
Output Leakage Current
GND ~ VOUT ~ V co Output Disabled
-40
+40
~
los
Output Short Circuit Current[7]
Vee = Max., VOUT = GND
-20
-90
rnA
Icc
Power Supply Current[2]
Vee = Max., VIN = 2.0V,
lOUT = 0 rnA, CE=VIL,
OE= VIH
Commercial
50
rnA
Military
60
ISB
Standby Supply Current
Vee = Max., CE = VIH,
lOUT = ornA
Commercial
15
Military
20
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
12
rnA
13
V
50
rnA
3.0
V
V
0.4
Capacitance[8]
Parameter
eIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
10
10
Unit
pF
pF
Notes:
3;
Contact a Cypress representative for information on industrial temperature range specifications.
4. TA is the "instant on" case temperature.
5. See the last page of this specification for Group A subgroup testing information.
6.
7.
8.
3-48
IOL = 12.0 rnA for military devices.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
.=:-:~
-.
-=
.• CYPRESS
IF
~
PRELIMINARY
CY7C256
SEMICONDUCTOR
AC Test Loads and Waveforms[8]
OUTP~~31R1
250Q
30
PFI
INCLUDING _
JIG AND SCOPE
OUTP~~31R1
R2167Q
_
-
5
PFI
GND
R2167Q
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
3.0V - - - --.l..o!~~--~~
250Q
_
-
C256-5
C256-4
(b) High Z Load
THEVENIN EQUIVALENT
100Q
OUTPUT 0.0- -_ ....
__ - - - 0 0 2.00V
C256-6
Switching Characteristics Over the Operating RangelS, 8]
7C256-45
Min.
7C256-55
Max.
Unit
tAA
Address to Output Valid
45
55
ns
tHZOE
Output Enable Inactive to High Z
15
20
ns
tOE
Output Enable Active to Output Valid
15
20
ns
tHzCE
Chip Enable Inactive to High Z
45
55
ns
45
55
ns
Parameter
Description
tACE
Chip Enable Active to Output Valid
tpu
Chip Enable Active to Power Up
tpD
Chip Enable Inactive to Power Down
tOH
Output Hold from Address Change
Max.
0
Min.
0
45
0
0
ns
55
ns
ns
Switching Waveform
ICC _ _ _ _ _ _ _ _ _ _ _ _ _
tpD
Ao -
POWER-DOWN CONTROLLED BY CE
-+-_~
SUPPLY
CURRENT
50%
A14
ADDRESS
HIGHZ
C256-7
3-49
II
~~pRF.SS
·
-===:::::t:,
PRELIMINARY
CY7C256
SEMICONDUCTOR
Erasure Characteristics
the PROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
Wavelengths of light less than 4000 angstroms begin to erase the
7C256 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity
multiplied by exposure time) of 25 Wsec/cm2 . For an ultraviolet
lamp with a 12 mW/cm2 power rating, the exposure time would
be approximately 35 minutes. The 7C256 needs to be within 1
inch of the lamp during erasure. Permanent damage may result if
Table 1. CY7C256 Mode Selection
Pin Function[9]
Mode
Read or Output Disable
A14 -
Other
A14 -
Read
A14 -
Output Disable
A14 -
Power Down
A14 -
Program
A14 -
Program Verify
A14 -
Program Inhibit
A14 -
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
OE
CE
Vpp
07 - 00
VFY
PGM
Vpp
D7 - Do
07 - 00
HighZ
VIL
VIL
Note 10
VIH
X
X
X
VIH
X
HighZ
VIHP
VILP
Vpp
D7 - Do
VILP
VIHP
Vpp
07 - 00
VIHP
Vpp
HighZ
VIHP
Notes:
10. Vpp should not exceed Vee in read mode.
9. X can be VIL (VILP) or VIH (VIHP).
LCC/PLCC[l]
Top View
DIP
Top View
vpp
vee
A14
A'3
As
As
~
As
A"
A3
VFY
A2
A,
J5GM
A;,
Do
D,
D2
GND
A10
D7
Ds
Ds
D4
D3
C256-8
Figure 1. Programming Pinouts
3-50
~
..
-='.
~
~,
PRELIMINARY
CYPRESS
SEMICONDUcrOR
CY7C256
Ordering Information[11]
Speed
(ns)
45
55
Ordering Code
Package
Name
Package 'JYpe
CY7C256-45JC
J65
32-Pin Rectangular Plastic Leaded Chip Carrier
CY7C256 - 45PC
P15
28-Lead (600-Mil) Molded DIP
CY7C256-45WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C256-45DMB
D16
28-Lead (600-Mil) CerDIP
CY7C256-45LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C256-45QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C256-45WMB
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C256-55JC
J65
32-Pin Rectangular Plastic Leaded Chip Carrier
P15
28-Lead (600-Mil) Molded DIP
CY7C256-55WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C256-55DMB
D16
28-Lead (600-Mil) CerDIP
CY7C256-55LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C256-55QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C256-55WMB
W16
28-Lead (600-Mil) Windowed CerDIP
Note:
11. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
IIX
Ioz
Icc
ISB
Switching Characteristics
Parameter
Subgroups
tAA
7, 8, 9, 10, 11
tOE
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
Commercial
Military
•
U)
CY7C256-55PC
VOH
VOL
VIR
VIL
Operating
Range
Document #: 38-00245
3-51
Commercial
Military
:E
oa:
Q.
CY7C258
CY7C259
2Kx 16 Reprogrammable
State Machine PROM
Features
Functional Description
• High speed: 100-MHz operation
-tcp = 10 ns
-tCKO = 8 ns
-tAS = 2 ns
• 16-bit-wide state word
• Can be programmed as asynchronous
PROM tAA = 18 ns
• Optimum speed/ power
• Individually bypassable input and
output registers
• Individually programmable address/
feedback muxes
• Synchronous and asynchronous chip
select
• Synchronous and asynchronous INIT
and programmable initialize word
• 16 outputs (CY7C259)
• Software support
• CY7C258 available in 28-pin, 300-mil
plastic and ceramic DIP, LCC, PLCC
• CY7C259 available in 44-pin LCC and
PLCC
• Reprogrammable in windowed
packages
• Capable of withstanding greater than
2001V static discharge
The CY7C258 and CY7C259 are 2K x 16
CMOS PROMs specifically designed for
use in state machine applications.
State machines are one of the most common applications for registered PROMs.
The CY7C258 and CY7C259 feature internal state feedback and a variety of programmable features to support 100-MHz
state machines with as many as 2,048 distinct states.
It is easy to use a PROM as a state machine. Each array location contains output data as well as information fed back
to select the next state. Note that a
PROM is only limited by the number of
array inputs. If a given state machine can
be implemented in the number of inputs/
feedbacks available (11 on the
CY7C258/259), then it will always fit in
the device. No software minimization is
required.
Among the programmable features of the
CY7C258/CY7C259 are individually bypassable input and output registers. The
registers run off the same clock for pipeline
capability. Each individual register can be
programmed to capture data at the rising
edge of the clock or to be transparent.
The registers at the inputs are useful for
signals that require short set-up times
(tAS = 2 ns). The input register does
introduce a cycle of latency, however. For
signals that directly affect the next state of
the machine, each input register can be
bypassed. Note that the cycle time remains the same (lO-ns min.), even if the
inputs are bypassed.
Registers at the output are used to hold
both state information and output data.
These registers -are also bypassable for
maximum flexibility. Occasionally, an individual output cannot wait for the next
clock edge. These outputs are sometimes
called Mealy outputs, and can be created
by bypassing the appropriate output register.
Since the CY7C258 and CY7C259 contain a 2K array, they each require 11 inputs. Each of these inputs can come from
an input pin or from internal output register feedback. Eleven individually programmable address muxes allow the user
to select the ratio of pin input and state
feedback.
These devices have both an asynchronous
output (OE) and a synchronous chip select (CS). The CS input is polarity programmable and registered twice. Each of
Logic Block Diagram
Pin Configurations
All REGISTERS
ARE BYPASSABlE
INPUT
REGISTERS
~
Ao
OUTPUT
REGISTERS
DIP
Top View
ADDRESS
~ES
rn:
I~'
A1
2Kx 16
A2
A3
PROGRAMMABLE
ARRAY
A..
CS
ClK
Do
D1
D2
Vee
Vss
Vss
Vee
As
As
Vss
As
D3
D4
Ds
Ag
D6
AlO
D7
A7
C25B-2
CS
0E ____~------r_1
C25B-1
3-52
•
CY7C258
CY7C259
::2:~
...... CYPRESS
,
SEMICONDUcrOR
Functional Description (continued)
the CS registers can be bypassed in the same manner as the address input and output registers.
A separately controllable INIT input is included for user resets. If
INIT is sampled LOW on the rising edge of CLK, the user programmable initialization word will appear at the outputs after the
next CLK cycle. Each of the INIT registers can be bypassed in
the same manner as the address input and output registers.
The difference between the CY7C258 and CY7C259 is in the
packaging. The CY7C258 has three different types of outputs. D4
- Do are dedicated outputs that do not feed back to the input
muxes. Ds - D7 appear on the output pins and are fed back to
the input muxes. Finally, D8 - DIS are dedicated feedback lines
that do not appear at the output pins. The dedicated feedback allows the CY7C258 to be packaged in 28-pin packages. The
CY7C258 is available in 28-pin LCC, PLCC, and slim 300-mil
DIP packages.
On the CY7C259, all 16 array outputs are available at the pins.
Outputs D4 - Do remain as dedicated outputs while Ds - DIS appear at the pins and are also fed back to the input muxes. This
organization allows the user maximum flexibility in selecting the
ratio of outputs to state feedback. The availability of state information at pins also improves testability. The CY7C259 is
packaged in 44-pin LCC and PLCC packages.
Several third-party programmers will feature support for PROMs
3
as state machines, including Data I/O (ABEL), ISDATA
(LOG/ie), and CUPL. The devices are also supported on the
(I)
Cypress Warp2 development software.
The CY7C258 and CY7C259 offer the advantage of low power, :::ill
superior performance, and programming yield. The EPROM 0
cells allow for each memory location to be 100% tested, with a:
each location being written into, erased, and repeatedly exercised A.
prior to encapsulation. Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming.
Pin Configurations (continued)
LCC/pLCC (Opaque Only)
Top View
LCC/PLCC(Opaque Only)
Top View
D3
A3
7C258
A.,
0
Vee
Vss
A5
As
10
A7
~~
Vee
A3
Do
D1
D2
Vss
Vee
Vss
D3
A.,
Vee
Vss
A5
Vss
As
A7
As
J o(f8~
D4
9
10
11
12
13
14
15
16
17
D5
vss
vee
Ds
D7
7C259
0
De
D9
29
18192021 22232425262728
Vee
Vss
C258-3
C258-4
Selection Guide
Commercial
7C258-12
7C259-12
7C258-15
7C259-15
Unit
10
12
15
ns
2/2 or 5/0
3/3 or 7/0
4/4 or 8/1
ns
10/0
12/0
15/0
ns
8
9
11
ns
Minimum Cycle Time
Registered Input Set-UpJHold[lj
Commercial and Military
7C258-10
7C259-10
Bypassed Input Set-UpJHold
Clock-to-Output
Note:
1. This parameter is programmable.
3-53
CY7C258
CY7C259
.:.~
'j; CYPRESS
~SF SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ................. '..... - 55°C to +125°C
Supply Voltage to Ground Potential ....... - 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
UV Exposure ........................... 7258 Wsec/cm2
Operating Range
Range
Commercial
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Industrial [2]
- 40°C to +85°C
5V ± 10%
Military[3]
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangd4, 5]
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH =- 2 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8 rnA
Min.
Max.
2.4
V
I Commercial
I Military
Vee = Min., IOL = 6 rnA
Unit
0.4
V
0.4
V
6.0
V
VIR
Input HIGH Voltage
Guaranteed Input Logical HIGHVoltagefor all Inputs
2.0
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all Inputs
- 3.0
0.8
V
IIX
Input Load Current
GND S VIN S Vee
-10
+10
f,tA
loz
Output Leakage Current
GND S VOUT s Vee, Output Disabled
- 40
+40
f.tA
los
Output Short Circuit Currend6]
Vee = Max., VOUT = GND
- 20
- 90
rnA
Icc
Active Current [7J
Vee = Max., lOUT = 0 rnA
I Commercial
70
rnA
Vee = Max., lOUT = 0 rnA
I Military
90
rnA
Capacitance[5]
Parameter
Description
Test Conditions
Input Capacitance
CIN
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Output Capacitance
COUT
Notes:
2. Contact a Cypress representative for industrial temperature range
specification.
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5.
6,
7.
Max.
Unit
10
pF
pF
10
See Introduction to CMOS PROMs in this Data Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Add 1 mNMHz for AC power component.
AC Test Loads and Waveforms[4]
soon
soon
sv §=l(6S80MiI)
OUTPUT'
OUTPUT
3330
(403 0 Mil)
I
SO pF
INCLUDING
JIG AND
SCOPE
-
-
GND
3330
(4030 Mil)
I
INCLUDING
JIG AND
SCOPE
-
-
(b) High Z Load
THEVENIN EQUIVALENT
2000
(2S00 Mil)
OUTPUT
90%
.
S pF
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
3,OV----
SV 5f1(6S80MiI)
o-----vw---o
2,OV
(1.9V Mil)
3-54
C258-5
C258-6
CY7C258
CY7C259
.~
k
-=-F'lE
CYPRESS
SEMICONDUcrOR
Switching Characteristics Over the Operating Rangd 3,4]
Commercial
7C258-10
7C259-10
Parameter
Description
Min.
Min.
Max.
7C258-15
7C259-15
Min.
Max.
Unit
tcp
Clock Period
10
12
15
ns
tCH
Clock HIGH
4
5
6.5
ns
tCL
Clock LOW
4
5
6.5
ns
tAs/tAH
Register Input Set-Up/Hold
2/2 or 5/0
3/3 or 7/0
4/4 or 8/1
ns
tABS
Address Set-Up to CLK with Input Bypassed
10
12
15
ns
tABH
Address Hold from CLK with Input Bypassed
0
0
0
ns
tCSs/tCSH
Chip Select Set-Up/Hold
tIPD
Asynchronous INIT to Output Valid with
Output Bypassed
tCKOl
Output CLK to Registered Output Valid
8
tCK02
Output CLK to Output Valid with Output
Bypassed
18
2/2 or 5/0
3/3 or 7/0
21
4/4 or 8/1
21
ns
25
ns
9
11
ns
18
21
ns
tDH
Data Hold from CLK
tcov
CLK to Output Valid[8]
8
9
11
ns
tcoz
CLK to High Z Outputl8]
8
9
11
ns
tcsv
CS to Output Valid with Input Bypassed[8]
10
12
15
ns
tcsz
CS to High Z Output with Input Bypassed [8]
10
12
15
ns
tOEV
OE to Output Valid[8]
8
9
11
ns
tOEZ
OE to High Z Outputl8]
8
9
11
ns
2
2
2
ns
tIs/tIH
INIT Set-Up/Hold
2/2 or 5/0
3/3 or 7/0
4/4 or 8/1
ns
tlBS
INIT Set-Up to CLK with Input Bypassed
10
12
15
ns
tlBH
INIT Hold from CLK with Input Bypassed
0
tpD
Propagation Delay with Input and Output
Bypassed
tICO
CLK to Output Valid with Output Bypassed
tIW
Asynchronous INIT Pulse Width
tlDV
Asynchronous INIT to Data Valid
tICR
Asynchronous INIT Recovery to Clock
18
18
18
12
10
10
10
See Output Waveform-Measurement Level.
3-55
0
0
18
Note:
8.
Max.
Commercial and Military
7C258-12
7C259-12
ns
21
ns
15
ns
15
12
12
ns
21
15
ns
ns
I
en
~
oa:
a.
CY7C258
CY7C259
~~~UC1CO
Output Waveform-Measurement Level
O.SV
HigbZ
Output
Vou
~
Rtb
\~x=O.OV
P i n o - - w r - - o Vx
CL = 5pF
o,SV
VOL
HigbZ
Output
t
Rtb
7~x=2.6V
Pin~ Vx
CL = 5pF
333Q
7~VOU
Vx = O.OV
~:!~f:
Pin~ Vx
CL = 50pF
500Q
~:!~f:
\~
l.SV
VOL
Vx = 2.6V
Pin
o---'\IV'v---O Vx
CL = 50pF
C258-7
Switching Waveforms
Registered Input and Output (combined with INIT)
ClK
Ao -
Al0 _ _ _ _ _ _~~-.J
'---t--- '--_ _ _J
--+________
"'_ _ _ _ _ _
DO - 0 7 (015) _ _ _ _ _ _~-----I_-----J '--_ _ _J
"'_ _ _--J ' - -_ _ _- ' '-_ _ __
m
CS,
tiS
tlH
tlBS
tlBH
OE ASSUMED ACTIVE
(BYPASSED INIT REG.)
C258-8
Bypassed Address and INIT Registers
ClK
Ao -
_ _ _ _ _ _ _ _ _J
AlO
------------4---J "' ___
DO - 07 (015)_
--J '"-_ _ _..I "'_ _ _ _ _ _ _ __
CS, OE ASSUMED ACTIVE
3-56
C258-9
CY7C258
CY7C259
. :rtpRF.SS
- , SEMICONDUCIOR
Switching Waveforms (continued)
Asynchronous INIT and OE
•
ClK
en
:E
oa:
D.
HIGHZ
CS ASSUMED ACTIVE
C258-10
Single- and Double-Registered Chip Select
ClK
CS
(ACTIVE HIGH) _ _ _ _ _ _ _ _---'"--_ _ _....J
Do - D7 (D ) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- (
15
HIGHZ
HIGHZ
(DOUBLE REGISTERED)
DE ASSUMED ACTIVE
C258-11
Bypassed Output Register[9]
ClK
Ao -
A10 _ _ _ _ _ _ _+-_....J '------l--J '-_ _ _ _ _ '-_-1-_ _ _ _ _ _ _ _ _ _ _ __
TNIT
\___---J!
CS,
DE ASSUMED ACTIVE
C258-12
Note:
9.
Even though the register is bypassed, INIT continues to set the output
register (for feedback purposes).
3-57
=
CY7C258
CY7C259
~~
;~
CYPRF.SS
_ , SEMICONDUCTOR
Switching Waveforms
Bypassed Input and Output Register (CS and Address)
Ao -
~
A10
I·
J
CS
(ACTIVE HIGH)
L
Do - 0 7 (D15)
tcsv
ADDRESS
tpD
-------j
<
HIGHZ
VALID
*
1
DATA1
~
tloSZ:j
~
>
VALID
HIGHZ
OE ASSUMED ACTIVE
C258-13
Asynchronous INIT and Bypassed Output Register[lO]
ClK
r---
DATA 1
DATA 2
tlPD - - - - - - -
--~\
1-------------------------------CS, OE ASSUMED ACTIVE
C258-14
Note:
10. Output registers configured as feedback to the array and bypassed with
respect to the output.
Mode Table
LAT
(7C258-CLK)
VPP
(INIT)
PGM
(CS)
VFY
(OE)
Do- DIS (259)
Do-D7 (258)
Latch High Byte
VIHP
Vpp
VIHP
VIHP
VIHPNILP
Program Inhibit
VILP
Vpp
VIHP
VIHP
HI-Z
Program Enable
VILP
Vpp
VILP
VIHP
VIHPNILP
Program Verify
VILP
Vpp
VIHP
VILP
VOHPNoLP
Mode
3-58
CY7C258
CY7C259
.::::r:-- .~
lie CYPRESS
~,
SEMICONDUcrOR
Programming Pinouts
DIP
LCC/PLCC (Opaque Only)
Vpp
VFY
Ao
J5GIV{
Al
LAT
Do
A2
8: gJ~ gJ
«~ «0 > I~
0..> > >
Ii::
A2
DO
Dl
D2
Aa
At.
Vss
21
Vss
Da
D4
Ds
As
A7
Aa
Ag
Vee
Vss
Da
As
A7
Aa
C258-17
Ds
Al0
Vee
Aa
A4
Vee
Vss
As
Vss
Dl
D2
Vss
Vee
Vee
Vss
A5
LCC/PLCC (Opaque Only)
D7
0
0
0
~ 0N
6 5 4 3 2 ,1,4443424140
39
38
37
9
10
36
11
35
12
34
13
33
32
14
7C259
15
31
16
30
29
17
1819202122232425262728
0
mO<.,)LO(,)oc;:tC"')Nr-OW
C258-15
Da
D4
Ds
Vss
Vee
Ds
D7
Da
Dg
Vee
Vss
C258-16
« ~~i5 ~i5i5oi5i5:'f
Programming Information
This datasheet provides some but not all the of programming information necessary for on-board programming of the CY7C258
and CY7C259. For more information about on-board programming of Cypress PROMs contact your local Cypress Field Sales
Engineer or Field Applications Engineer.
7C258 Bitmap[llJ
Programmer
Address
Decimal
Programmer
Address
Hex
Programmer
Memory
7C258
0
0
Data
Bit Breakdown
DIS DI4 D13 D12 Dll DlO D9 Ds D7 D6 Ds D4 D3 Dz DI Do
Array Data
2047
7FF
Data
2048
800
Address Register Select
(1 = Bypassed Register)
2049
801
Array Input Select
(1= Feedback)
2050
802
Output Register Select
(1= Bypassed Register)
2051
803
INITWORD
(1= INIT Bit 1)
2052
804
Architecture
A9 As A7 ~ As Az Al
Ao
AlOX
X
X
X
X
~ A3
X
X
X
X
~ A3
A9
As
A7 ~ As Az Al
Ao
AlOX
X
X
X
X
D7 D6 Ds D4 D3 Dz DI Do
X
X
X
X
DIS D14 D13 D12 Dll DlO D9 Ds D7 D6 Ds D4 D3 Dz DI Do
X
X
X
Note:
11. All eonfigurable bits default to O.
3-59
X
X
X
X
X
SH CI Cz CP IE IA X
X
•
en
::ill
0
a:
Q.
CY7C258
CY7C259
Programmer
Address
Decimal
Programmer
Address
Hex
Programmer
Memory
7C259
0
0
Data
Bit Breakdown
DIS DI4 D13 D12 Dl1 DlO D9 Dg D7 D6 Ds D4 D3 Dz DI Do
Array Data
2047
7FF
Data
2048
800
Address Register Select
(1 = Bypassed Register)
AlO A 9
As A7
~ As X
X
X
X
X
A4
A3 Az Al
Ao
2049
801
Array Input Select
(1 = Feedback)
AlO A 9
As A7
~ As X
X
X
X
X
A4
A3 Az Al
Ao
2050
802
Output Register Select
(1 = Bypassed Register)
DIS DI4 D13 D12 Dl1 DlO D9 Dg D7 D6 Ds D4 D3 Dz DI Do
2051
803
INITWORD
(1 = INIT Bit 1)
DIS DI4 D13 D12 Dl1 DlO D9 Dg D7 D6 Ds D4 D3 Dz DI Do
2052
804
Architecture
SH CI Cz CP IB IA X
X
X
X
X
X
X
Architecture Word
Control Word
Control Option
Bit (258)
Bit (259)
IA
(INIT Async)
Dz
DlO
0= Default
1 = Programmed
Synchronous INIT
Asynchronous INIT
IB
(INIT Bypass)
D3
Dl1
0= Default
1 = Programmed
INIT Registered
Bypass INIT Register
CP
(CS Polarity)
D4
D12
0= Default
1 = Programmed
CS Active LOW
CS Active HIGH
C2
(CS Bypass)
(Buried Register)
Ds
D13
0= Default
1 = Programmed
CS Input Registered
Bypass CS Register
C1
(CS Bypass)
(Input Register)
D6
DI4
0= Default
1 = Programmed
CS Input Registered
Bypass CS Register
SH
(Set-Up/Hold)
D7
DIS
0= Default
1 = Programmed
Set-Up/Hold = 2/2 ns
Set-Up/Hold = 5/0 ns
Programmed level
3-60
Function
X
X
X
=-:
CY7C258
CY7C259
.~
~=CYPRESS
~, SEMICONDUcrOR
1Ypical DC and AC Characteristics
NORMALIZED Icc vs.
AMBIENT TEMPERATURE
1.2
1.6
~ee =~.OV,
f=B3.3 MHz
o
...
UJ
~ 1.0
--...
«
:::i!:
a:
~
0.9
b,
- -----
u
0
UJ
::J
«
~
1.0
.,./
:::i!:
a: O.B
./
i-"""
o
z
-50
0
50
100
~ O.B
4
4.5
5
5.5
SUPPLY VOLTAGE M
TEMPERATURE (C)
01.1
~
..9 1.0
I
I
TA = 25°C ~
o
~ 0.9
::J
30
-
~ O.B
a:
o
z
Cii"
£
~
S2
~
UJ
0.7
0
0.6
25
10
5
/
0
4.5
5.0
5.5
SUPPLY VOLTAGE
o
6.0
1.1
Cl
..9- 1.0
o
~ 0.9
::J
~ o.B
a:
o
z
200
M
--- ------
~
30.0
25.0
Cii"
£20.0
./
/V
-
0
UJ
::J
«
:::i!:
400
1.0
5.5
SUPPLY VOLTAGE
M
..... ~
-50
6.0
- -
200
u
.9
0
1.0
0.9
UJ
N
::J O.B
«
:::i!:
\
0.6
600
BOO 1000
CAPACITANCE (pF)
3-61
150
0.4
\
\
'-...... --..
r---
0.5
400
100
1\
a: 0.7
0
z
/'
o
50
1.1
I
/
10.0
0
TEMPERATURE (0C)
/
:..J
o
5.0
~
.."..,.
NORMALIZED Icc VS.
CLOCK PERIOD
Vee = 4.5V
TA = 25°C
15.0
5.0
150
...
1.2
0.4
-100
BOO 1000
600
/V
0.5
100
0.6
Q.
~
50
1.4
a:
z O.B
/
0.6
4.5
!r
0
I
-
0
N
/
Cl
~
0.7
0.4
4.0
I.
DELTA tpD vs.
OUTPUT LOADING
TA ='25°C
D.
NORMALIZED tpD VS.
AMBIENT TEMPERATURE
CAPACITANCE (pF)
NORMALIZED tpD VS.
SUPPLY VOLTAGE
1.2
/
a:
TEMPERATURE (C)
V
15
o
1.6
Vee = 4.5V,
TA=25°C
20
0.5
0.4
4.0
1
r-- -
U)
::&
0.6
TYPICAL tCKOl CHANGE vs.
OUTPUT LOADING
NORMALIZED tCKOl VS.
SUPPLY VOLTAGE
1.2
6
~
~
0.4
- 100 - 50
0.4
150
--
«
0.6
O.B
-100
....... ~
~ 1.0
oz
•
Vee = 5.0V
UJ
""
0
1.4
_u 1.2
.;
.9 1.2
N
1.6
I TA=25 o
f=B3.3MHz -
1.4
u 1.1
.9
NORMALIZED tcKOl vs.
AMBIENT TEMPERATURE
NORMALIZED Icc vs.
SUPPLY VOLTAGE
o
25
50
75
CLOCK PERIOD
100
=s
CY7C258
CY7C259
.~
_ _ _ 'j; CYPRESS
~, SEMICONDUCTOR
Ordering Information[12]
Speed
(ns)
10
12
15
Speed
(ns)
10
12
15
Package
Name
Package 1Ype
Operating
Range
CY7C258-10HC
H64
28-Pin Windowed Leaded Chip Carrier
Commercial
CY7C258-10JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C258-1OPC
P21
28-Lead (300-Mil) Molded DIP
CY7C258-1OWC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C258-12HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C258-12JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C258-12PC
P21
28-Lead (300-Mil) Molded DIP
CY7C258-12WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C258-12HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C258-12LMB
CY7C258-12QMB
L64
Q64
28-Square Leadless Chip Carrier
CY7C258-12WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C258-15HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C258-15JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C258-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C258-15WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C258-15HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C258-15LMB
28-Square Leadless Chip Carrier
CY7C258-15QMB
L64
Q64
28-Pin Windowed Leadless Chip Carrier
CY7C258-15WMB
W22
28-Lead (300-Mil) Windowed CerDIP
Ordering Code
Package
Name
Package 'fYpe
Operating
Range
CY7C259-1OHC
H67
44-Pin Windowed Leaded Chip Carrier
Commercial
CY7C259-1OJC
J67
44-Lead Plastic Leaded Chip Carrier
Ordering Code
Commercial
Military
28-Pin Windowed Leadless Chip Carrier
CY7C259-12HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C259-12JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C259-12HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C259-12LMB
L67
44-Square Leadless Chip Carrier
CY7C259-12QMB
Q67
44-Pin Windowed Leadless Chip Carrier
CY7C259-15HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C259-15JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C259-15HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C259-15LMB
L67
44-Square Leadless Chip Carrier
CY7C259-15QMB
Q67
44-Pin Windowed Leadless Chip Carrier
Note:
12. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-62
Commercial
Military
Commercial
Military
Commercial
Military
CY7C258
CY7C259
~
~aPRFSS
~JF SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3,
VOL
1,2,3,
VIH
VIL
1,2,3,
1,2,3,
hx
1,2,3,
Ioz
1,2,3,
1,2,3,
Icc
•
en
:!
o
a:
Q.
Switching Characteristics
Parameter
Subgroups
tcp
7, 8, 9, 10, 11
tCH
7, 8, 9, 10, 11
tCL
tAS
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tABS
7, 8, 9, 10, 11
tcss
7, 8, 9, 10, 11
tCSH
7, 8, 9, 10, 11
tlPD
tCKOl
7, 8, 9, 10, 11
7,8, 9, 10, 11
tCK02
7, 8, 9, 10, 11
tDH
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tcov
tcsv
7, 8, 9, 10, 11
tOEV
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tIS
tIBS
7,8, 9, 10, 11
7, 8, 9, 10, 11
tIBH
7, 8, 9, 10, 11
tpD
7, 8, 9, 10, 11
tIH
tlCO
7, 8, 9, 10, 11
tlW
7, 8, 9, 10, 11
tIDY
7, 8, 9, 10, 11
tlCR
7, 8, 9, 10, 11
Document #: 38-00173-E
3-63
CY7C261
CY7C263/CY7C264
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-20 ns (commercial)
-25 ns (military)
• Lowpower
-660 mW (commercial)
-770 mW (military)
• Super low standby power (7C261)
- Less than 220 mW when deselected
- Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil
packaging available
• 5V ± 10% Vee, commercial and
military
8K X 8 Power-Switched and
Reprogrammable PROM
• Capable of withstanding greater than
2001V static discharge
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264
are high-performance 8192-word by 8-bit
CMOS PROMs. When deselected, the
7C261 automatically powers down into a
low-power standby mode. It is packaged in
a 300-mil-wide package. The 7C263 and
7C264 are packaged in 300-mil-wide and
600-mil-wide packages respectively, and
do not power down when deselected. The
reprogrammable packages are equipped
with an erasure window; when exposed to
UV light, these PROMs are erased and can
then be reprogrammed. The memory cells
utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms.
Pin Configurations
Logic Block Diagram
Ao
07
DIPlFlatpack
Top View
A1
A2
A3
ROW
ADDRESS
PROGRAMMABLE
ARRAY
Vee
As
24
23
22
A..
21
A10
A7
As
As
Os
As
As
A3
A2
A1
Ag
Ao
A10
An
LCCIPLCC (Opaque Only
Top View
Os
A..
A7
The CY7C261, CY7C263, and CY7C264
are plug-in replacements for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The EPROM cellrequires only 12.5V for the supervoltage and
low current requirements allow for gang
programming. The EPROM cells allow for
each memory location to be tested 100%,
as each location is written into, erased, and
repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that after customer programming the product will meet
DC and AC specification limits.
Read is accomplished by placing an active
LOW signal on CS. The contents of the
memory location addressed by the address
line (An - A12) will become available on
the output lines (00 - 07).
ADDRESS
DECODER
04
03
CS
A11
A12
07
Os
Os
04
03
00
01
COLUMN
ADDRESS
02
GND
02
iR~2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
UV Exposure ........................... 7258 Wsec/cm 2
Operating Range
Ambient
Temperature
Vee
Commercial
O°Cto + 70°C
5V ± 10%
I
Industrial[l)
- 40°C to + 85°C
5V ± 10%
:E
Military[2)
- 55°C to + 125°C
5V ± 10%
Range
en
oa::
Q.
Electrical Characteristics Over the Operating Rangel 3, 4)
7C261-20,25
7C263-20,25
7C264-20,25
Test Conditions
Min.
2.4
VOL
Output LOW Voltage
= Min., IOH = - 2.0 rnA
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8 rnA
VOL
Output LOW Voltage
Vee
VIR
Input HIGH Level
Parameter
Description
VOH
Output HIGH Voltage
VOH
Output HIGH Voltage
Vee
7C261-35, 45, 55
7C263-35, 45, 55
7C264-35, 45, 55
Max.
Min.
Max.
Unit
V
2.4
V
0.4
V
(6 rnA Mil)
= Min., IOL = 16 rnA
0.4
VIL
Input LOW Level
IIX
Input Current
VeD
Input Diode Clamp Voltage
loz
Output Leakage Current
V
2.0
2.0
V
0.8
V
+10
f!A
- 40
+40
f!A
- 20
- 90
rnA
rnA
0.8
GND ~ VIN ~ Vee
-10
VOL~ VOUT~ VOH,
- 40
+40
- 20
- 90
-10
+10
Note 4
Note 4
Output Disabled
los
Output Short Circuit Currentl5)
Vee = Max.,
VOUT = GND
lee
Power Supply Current
Vee = Max.,
VIN = 2.0V
Com'l
120
100
Mil
140
120
= Max.,
VIR
lOUT = ornA
Com'l
40
30
ISB
Standby Supply Current (7C261)
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIRP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
Yce
CS~
30
40
Mil
12
rnA
13
12
50
3.0
13
V
50
rnA
0.4
V
3.0
0.4
V
Capacitance(4)
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. See the Ordering Information section regarding industrial tempera-
ture range specification.
2.
3.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
= 1 MHz,
Max.
Unit
10
pF
10
pF
4. See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
5. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
3-65
CY7C261
CY7C263/CY7C264
.~.
~~ CYPRESS
·
-====F
SEMICONDUCTOR
AC Test Loads and Waveforms[4]
Test Load for -20 through -30 speeds
R1 SOO
R1 SOOQ
sv
SV 3 1 ( 6 S 8MIL)
Q
OUTPUT
(6S8Q MIL)
31
3.0V ----..u----~~
OUTPUT
30
pF I
INCLUDING _
JIG AND SCOPE
R2 333Q
(403Q MIL)
_
-
S
pF I
INCLUDING _
JIG AND SCOPE
(a) Normal Load
GND
R2 333Q
(403Q MIL)
_
-
C261-S
C261-4
(b) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
RTH200Q
OUTPUT ~ 2SOI1 MIL
Test Load for - 35 through - 55 speeds
R12S0Q
R12S0Q
SV~
OUTPUT
30
pF I·
INCLUDING
JIG AND
SCOPE
_
-
31
SV
OUTPUT
R2167Q
_
-
S
PFI
INCLUDING _
JIG AND SCOPE
R2167Q
_
-
C261-6
(c) Normal Load
(d) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
RTH 100Q
OUTPUT ~ 2.0V
Switching Characteristics Over the Operating Rangd2, 3, 4]
7C261-20
7C263-20
7C264-20
Parameter
Description
Min.
Max.
7C261-25
7C263-25
7C264-25
Min.
Max.
7C261-35
7C263-35
7C264-35
Min.
Max.
7C261-45
7C263-45
7C264-45
Min.
Max.
7C261-55
7C263-55
7C264-55
Min.
Max.
Unit
tAA
Address to Output Valid
20
25
35
45
55
ns
tHZCS1
Chip Select Inactive to High Z
12
12
20
30
35
ns
tHZCS2
Chip Select Inactive to High Z
(7C261)
20
25
35
45
55
ns
tACS1
Chip Select Active to Output Valid
12
12
20
30
35
ns
tACS2
Chip Select Active to Output Valid
(7C261)
20
25
35
45
55
ns
tpu
Chip Select Active to Power-Up
(7C261)
tpD
Chip Select Inactive to Power-Down
(7C261)
0
0
20
25
3-66
0
0
35
ns
0
45
55
ns
.
CY7C261
CY7C263/CY7C264
;~PRESS
-=:!!!!!!:,
SEMICONDUCTOR
Switching Waveforms[4]
Vee
SUPPLY
CURRENT
Ao -
•
A12
ADDRESS
C261-7
Erasure Characteristics
Operating Modes
Wavelengths of light less than 4000 angstroms begin to erase the
devices in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm2 power rating, the exposure time would be approximately 45 minutes. The 7C261 or 7C263 needs to be within 1
inch of the lamp during erasure. Permanent damage may result if
the PROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
Read
Read is the normal operating mode for a programmed device. In
this mode, all signals are normal TTL levels. The PROM is addressed with a 13-bit field, a chip select, (active LOW), is applied to
the CS pin, and the contents of the addressed location appear on
the data out pins.
Program, Program Inhibit, Program Verify
These modes are entered by placing a high voltage Vpp on pin 19,
with pins 18 and 20 set to V ILF In this state, pin 21 becomes a latch
signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW~ram (PGM)
signal and pin 23 becomes an active LOW verify (VFY) signal. Pins
22 and 23 should never be active LOW at the same time. The PROGRAM mode exists when PGM is Law, and VFY is HIGH. The
verify mode exists when the reverse is true, PGM HIGH and VFY
LOW and the program inhibit mode is entered with both PGM and
VFY HIGH. Program inhibit is specifically provided to allow data
to be placed on and removed from the data pins without conflict.
3-67
CY7C261
CY7C263/CY7C264
_
J.:~
.ill CYPRESS
~,
SEMICONDUcrOR
Table 1. Mode Selection
Pin Fnnction[6,7]
Read or Output Disable
A12
An
AIO
A9
As
CS
Program
NA
Vpp
LATCH
PGM
VFY
CS
D7 - Do
A12
A12
A11
A11
AlO
AlO
A9
A9
As
VIL
07 - 00
As
VIH
HighZ
Program
VILP
Vpp
VILP
VILP
VIHP
VILP
D7- D O
Program Inhibit
VILP
Vpp
VILP
VIHP
VIHP
VILP
HighZ
Program Verify
VILP
Vpp
VILP
VIHP
VILP
VILP
07 - 00
Blank Check
VILP
Vpp
VILP
VIHP
VILP
VILP
0 7 - 00
Mode
Read
Output Disable
07 - 00
Notes:
6. X = "don't care" but not to exceed Vee ±5%.
7.
Addresses As - A 12 must be latched through lines Ao- AI in programmingmodes.
LCC/PLCC (Opaque only)
Top View
DIPlFlatpack
Top View
81~1~
Vee
'IlF'I
'" <
"'"'U
«
z > >0.
J5GM
4 3 2,1, 28 27 26
25
24
7C261
23
22
21
7C263
LATCH
CS
Vpp
0
NA
D7
D6
Do
LATCH
CS
Vpp
NA
NC
D7
D6
D5
D4
C261-9
D3
C261-8
Figure 1. Programming Pinouts
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end ofthis
section. Programming algorithms can be obtained from any Cypress representative.
3-68
CY7C261
CY7C263/CY7C264
~
--.
:~
- - -ill CYPRESS
JF
SEMICONDUCTOR
1Ypical DC and AC Characteristics
NORMAUZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMAUZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.2
1.6
w
~
~1.4
~
Cl
/
~ 1.2
V
:::;
«
~
~
1.0
z
0.8
./
~
-
5.0
~
5.5
6.0
0.91-----1-------"...,....--1
«
S
~
a:
oz
=:I
w
30
a:
()
w
=:I
N
:::; 1.0
0
en 20
«
~
I=:I
D..
I=:I
a: 0.8
0
Z
0
25
125
o
S
I-
aa:
~
z
Ci5
r--....
2.0
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
/
75
25
/
V
o
0.0
5.0
/
1.00
25
~
20
~
15
Cl
10
5
..9 0.95
V
"
/
/~
Cl
w 0.90
«
~
Vee = 5.0V
TA = 25°C -
/
Vee = 4.5V
TA = 25°C -
[7
I
200
400
I
3.0
OUTPUT VOLTAGE
Vee = 5.5V
TA = 25°C
~
"-
0.85
a:
0 0.80
z
I
~ r--
0.75
0.70
4.0
o
M
25
50
75
CYCLE PERIOD (ns)
3-69
V
600
I
800 1000
CAPACITANCE (pF)
N
:::;
2.0
6.0
M
/
o0
4.0
\
()
/
1 .0
5.5
... V
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
"... ~
100
o
4.5
1.05
125
50
M
en
.s
w
""
150
5
D..
5
'""
OUTPUT VOLTAGE
z
Ii!
'"
1.0
AMBIENT TEMPERATURE (0G)
« 175
I
0.4
4.0
30
10
o
A.
TA = 25°C
35
()
1.2
oa:
0.6
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
60
•
(I)
OUTPUT SOURCE CURRENT
vs. VOLTAGE
z 50
w
a:
a: 40 ~
Cl
r---
:E
SUPPLY VOLTAGE
I-
i=
---
i--.
0.8
AMBIENT TEMPERATURE (0G)
M
1.6
0.6
- 55
r---
w
N
:::;
0.8 '--_ _ _-'--_ _ _ _ _....J
-55
25
125
en 1.4
en
w
«
Cl
oz
~
()
()
:::; 1.01------'''Ir-------I
~
NORMALIZED ACCESS TIME
vs. TEMPERATURE
w
w
w
()
I
4.5
~ 1.0
a:
TA = 25°C
f = fMAX
SUPPLY VOLTAGE
i=
t--~--+-------I
N
./
V
0.6
4.0
1.1
Cl
100
CY7C261
CY7C263/CY7C264
G:i;~
Ordering Information[8]
Speed
(os)
20
25
35
45
55
Ordering Code
CY7C261-20JC
CY7C261-20PC
CY7C261-20WC
CY7C261-25JC
CY7C261-25PC
CY7C261-25WC
CY7C261-25DMB
CY7C261-25LMB
CY7C261-250MB
CY7C261-25TMB
CY7C261-25WMB
CY7C261-35JC
CY7C261-35PC
CY7C261-35WC
CY7C261-35DMB
CY7C261-35LMB
CY7C261-350MB
CY7C261- 35TMB
CY7C261-35WMB
CY7C261-45JC
CY7C261-45PC
CY7C261-45WC
CY7C261-45DMB
CY7C261-45LMB
CY7C261-450MB
CY7C261-45TMB
CY7C261-45WMB
' CY7C261-55JC
CY7C261-55PC
CY7C261-55WC
CY7C261-55DMB
CY7C261-55LMB
CY7C261-550MB
CY7C261-55TMB
CY7C261-55WMB
Package
Name
J64
P13
W14
J64
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
064
T73
W14
Package 'tYPe
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpa.ck
24-Lead (300-Mil) Windowed CerDIP
Note:
8.
Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-70
Operating
Raoge
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
CY7C261
CY7C263/CY7C264
z'·
-=--.-~PRESS
o
SEMICONDUCTOR
Ordering Information[8] (continued)
Speed
(ns)
20
25
35
45
55
Ordering Code
CY7C263 - 20JC
CY7C263- 20PC
CY7C263-20WC
CY7C263-25JC
CY7C263-25PC
CY7C263 - 25WC
CY7C263-25DMB
CY7C263- 25LMB
CY7C263 - 250MB
CY7C263- 25TMB
CY7C263- 25WMB
CY7C263 - 35JC
CY7C263-35PC
CY7C263 - 35WC
CY7C263-35DMB
CY7C263-35LMB
CY7C263-350MB
CY7C263-35TMB
CY7C263-35WMB
CY7C263-45JC
CY7C263-45PC
CY7C263-45WC
CY7C263-45DMB
CY7C263-45LMB
CY7C263 -450MB
CY7C263-45TMB
CY7C263-45WMB
CY7C263 - 55JC
CY7C263-55PC
CY7C263 - 55WC
CY7C263-55DMB
CY7C263-55LMB
CY7C263-550MB
CY7C263-55TMB
CY7C263-55WMB
Package
Name
J64
P13
W14
J64
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
D14
L64
064
T73
W14
Package
'JYpe
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
3-71
Operating
Range
Commercial
Commercial
II
Military
:E
en
oa:
Q.
Commercial
Military
Commercial
Military
Commercial
Military
*'
CY7C261
CY7C263/CY7C264
.~SEMICONDUcroR
~.a CYPRESS
,
Ordering Information (continued) [8]
Speed
(ns)
20
25
35
45
55
Ordering Code
CY7C264-20DC
CY7C264- 20PC
CY7C264- 20WC
CY7C264-25DC
CY7C264-25PC
CY7C264- 25WC
CY7C264- 25DMB
CY7C264-25WMB
CY7C264-35DC
CY7C264-35PC
CY7C264-35WC
CY7C264- 35DMB
CY7C264-35WMB
CY7C264-45DC
CY7C264-45PC
CY7C264-45WC
CY7C264-45DMB
CY7C264-45WMB
CY7C264-55DC
CY7C264-55PC
CY7C264-55WC
CY7C264-55DMB
CY7C264-55WMB
Package
Name
D12
P11
W12
D12
P11
W12
D12
W12
D12
P11
W12
D12
W12
D12
P11
W12
D12
W12
D12
P11
W12
D12
W12
Package 'J.Ype
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600;Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Molded DIP
24-Lead (600-Mil) Windowed CerDIP
24-Lead (600-Mil) CerDIP
24-Lead (600-Mil) Windowed CerDIP
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
Commercial
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
VIR
1,2,3
VIL
1,2,3
IIX
1,2,3
1,2,3
Ioz
1,2,3
Icc
ISB[9]
1,2,3
Parameter
Subgroups
tAA
tACSl[lO]
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tACS2[1O]
7, 8, 9, 10, 11
Notes:
9. 7C261 only.
10. 7C263 and 7C264 only.
1,2,3
3-72
·
CY7C261
CY7C263/CY7C264
~
~.a
CYPRESS
_ , SEMICONDUCTOR
SMD Cross Reference
SMD
Number
Suffix
Cypress
Number
5962-87515
05KX
CY7C261-45TMB
5962-87515
05LX
CY7C261-45WMB
5962-87515
053X
CY7C261-45QMB
5962-87515
06KX
CY7C261-55TMB
5962-87515
06LX
CY7C261-55WMB
5962-87515
063X
CY7C261-55QMB
5962-90803
01MKX
CY7C261-55KMB
•
5962-90803
01MLX
CY7C261-55DMB
Q.
5962-90803
01M3X
CY7C261-55LMB
5962-90803
02MKX
CY7C261-45KMB
5962-90803
02MLX
CY7C261-45DMB
5962-90803
02M3X
CY7C261-45LMB
5962-90803
03MKX
CY7C261-35KMB
5962-90803
03MLX
CY7C261-35DMB
5962-90803
03M3X
CY7C261-35LMB
5962-90803
04MKX
CY7C261-25KMB
5962-90803
04MLX
CY7C261-25DMB
5962-90803
04M3X
CY7C261-25LMB
5962-90803
05MJX
CY7C264-55DMB
5962-90803
05MKX
CY7C263-55KMB
5962-90803
05MLX
CY7C263-55DMB
5962-90803
05M3X
CY7C263-55LMB
5962-90803
06MJX
CY7C264-45DMB
5962-90803
06MKX
CY7C263-45KMB
5962-90803
06MLX
CY7C263-45DMB
5962-90803
06M3X
CY7C263-45LMB
5962-90803
07MJX
CY7C264-35DMB
5962-90803
07MKX
CY7C263-35KMB
5962-90803
07MLX
CY7C263-35DMB
5962-90803
07M3X
CY7C263-35LMB
5962-90803
08MJX
CY7C264-25DMB
5962-90803
08MKX
CY7C263-25KMB
5962-90803
08MLX
CY7C263-25DMB
5962-90803
08M3X
CY7C263-25LMB
U)
::E
oa::
Document #: 38-00005-1
3-73
CY7C265
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• High speed (commercial and military)
-15 ns max. set-up
- 12 ns clock to output
• Lowpower
-660 mW (commercial)
-770 mW (military)
• On-chip edge-triggered registers
- Ideal for pipelined microprogrammed systems
• EPROM technology
- 100% programmable
- Reprogrammable (7C265W)
• 5V ± 10% Vee, commercial and
military
• Capable of withstanding >2001V static discharge
• Slim 28-pin, 300-mil plastic or hermeticDIP
8K X 8 Registered PROM
PROM. It is organized as 8,192 words by
8 bits wide, and has a pipeline output register. In addition, the device features a
programmable initialize byte that may be
loaded into the pipeline register with the
initialize signal. The programmable initialize byte is the 8,193rd byte in the
PROM and its value is programmed at
the time of use.
Packaged in 28 pins, the PROM has 13
address signals (Ao through ~iJ, 8 data
out signals (00 through 07), Ell (enable
or initialize), and CLOCK.
CLOCK functions as a pipeline clock,
loading the contents of the addressed
memory location into the pipeline register
on each rising edge. The data will appear
on the outputs if they are enabled. One
pin on the CY7C265 is programmed to
perform either the enable or the initialize
function.
Functional Description
If the asynchronous enable (E) is being
The CY7C265 is a 8192 x 8 registered
used, the outputs may be disabled at any
time by switching the enable to a logic
HIGH, and may be returned to the active
state by switching the enable to a logic
LOW.
If the synchronous enable (Es) is being
used, the outputs will go to the OFF or
high-impedance state upon the next
positive clock edge after the synchronous enable input is switched to a
HIGH level. If the synchronous enable
pin is switched to a logic LOW, the subsequent positive clock edge will return
the output to the active state. Following
a positive clock edge, the address and
synchronous enable inputs are free to
change since no change in the output
will occur until the next LOW-to-HIGH
transition of the clock. This unique feature allows the CY7C265 decoders and
sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
Pin Configurations
Logic Block Diagram
DIP/Flatpack
Top View
A12
A7
Vee
A11
As
A5
As
As
~
A10
A10
ROW
ADDRESS
Ag
As
PROGRAMMABLE
ARRAY
COLUMN
MULTIPLEXER
':1 0
A7
As
ADDRESS
DECODER
A5
~~
::;:s:
::;:w
~N
::::;
C!l<
As
Oi=
g:~
~
A3
COLUMN
ADDRESS
A2
As
All
A2
A12
GND
EiEs,l
ClK
GND
A1
GND
Ao
07
00
Os
01
05
02
GND
04
03
A1
C265-3
Ao
00
lNlTiEf~s
LCC/PLCC (Opaque Only)
Top View
~ A5
- - - -....--t
4
3
As A7VceAs
ClK
7C265
C265-1
Ag
2'1'282726
0
25
A10
24
23
A11
A12
22
EiEs,l
21
GND
20
GND
07
19
1516 17 18
01 02GND 0 3 04 05 Os
C265-2
3-74
.-
==--=- .~
CY7C265
~iE CYPRESS
iF
SEMICONDUcrOR
Functional Description (continued)
If the Ell pin is used for INIT ( asynchronous), then the outputs
are permanently enabled. The initialize function is useful during
power-up and time-out sequences, and can facilitate implementation of other sophisticated functions such as a built-in "jump
start" address. When activated, the initialize control input causes
the contents of a user programmed 8193rd 8-bit word to be
loaded into the on-chip register. Each bit is programmable and
the initialize function can be used to load any desired combina-
tion of Is and Os into the register. In the unprogrammed state,
activating INIT will generate a register clear (all outputs LOW).
If all the bits of the initialize word are programmed to be a 1, activating INIT performs a register preset (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of
the programmed initialize word into the pipeline register and
onto the outputs. The INIT LOW disables clock and must return
HIGH to enable clock independent of all other inputs, including
the clock.
Selection Guides
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current (rnA)
7C265-15
15
12
120
140
I Com'l
I
Mil
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
DC Program Voltage ............................. 13.0V
7C265-25
25
15
120
140
7C265-40
40
20
100
7C265-50
50
25
80
120
UV Exposure ........................... 7258 Wsec/cm2
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
IndustriaIll J
Militaryl2J
Ambient
Temperature
O°C to +70°C
Vee
5V ±1O%
- 40°C to +85°C
5V ±1O%
- 55°C to + 125°C
5V ±1O%
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
Description
Output HIGH Voltage
VOH
VOL
Output LOW Voltage
VIH
VIL
IIX
loz
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
losl4J
Icc
Vpp
Ipp
VIHP
VILP
Test Conditions
Vee = Min., IOH = - 2.0 rnA
Vee = Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA Com'l
Vee = Min., IOL = 12.0 rnA
Vee = Min., IOL = 6.0 rnA Mil
Vee = Min., IOL = 8.0 rnA
GND~ VIN~
Vee
GND~ VOUT~ Vee,
Output Disabled
Output Short Circuit Current Vee = Max., VOUT = GND
Vee Operating Supply
Vee = Max., lOUT = 0 rnA Com'l
Current
Mil
Programming Supply Voltage
Programming Supply Current
Input HIGH Programming
Voltage
Input LOW Programming
Voltage
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3.
4.
3-75
7C265-15,25 7C265-40 7C265-50
Min. Max. Min. Max. Min. Max.
2.4
2.4
2.4
0.4
0.4
0.4
0.4
0.4
0.4
2.0
2.0
2.0
0.8
0.8
0.8
-10
+10 -10 +10 -10 +10
-40 +40 -40 +40
- 40
+40
12
90
120
140
13
50
3.0
90
100
12
13
50
3.0
0.4
12
V
V
V
!lA
!lA
90
80
120
13
50
rnA
rnA
0.4
V
3.0
0.4
Unit
V
V
rnA
V
See the last page ofthis specification for Group A subgroup testing information.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
II
=-
:~PRFSS
•
CY7C265
" . SEMICONDUCTOR
Capacitance[S]
Parameter
Description
qN
Test Conditions
TA = 25°C, f
Vee = 5.0V
Input Capacitance
Output Capacitance
COUT
= 1 MHz,
Max.
Unit
10
pF
10
pF
Note:
5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
AC Test Loads and Waveforms
Test Load for -15 through - 25 speeds
R1500Q
R1500
5v~(658QMil)
5v:n(658QMil)
om~T
3.0V - - - -...1r-------s.,.
ou~m
30 pF
I
R2 333Q
(403Q Mil)
INCLUDING _
JIG AND SCOPE
5 pF
_
-
INCLUDING _
JIG AND SCOPE
R2 333Q
(403Q Mil)
C265-4
THEVENIN EQUIVALENT
RTH 200Q (250Q Mil)
OUTPUT
o-------vvv----
2.0V
Test Load for -40 through -50 speeds
R1250Q
R1250Q
OUTP~~~
30 pF
I
INCLUDING _
JIG AND SCOPE
OUTP~~~
R2 167Q
_
-
5 pF
(c) Normal Load
Equivalent to:
OUTPUT
I
INCLUDING _
JIG AND SCOPE
R2 16m
_
-
(d) High Z Load
THEVENIN EQUIVALENT
~
GND
_
-
(b) High Z Load
(a) Normal Load
Equivalent to:
I
2.0V
3-76
C265-6
C265-5
· ~~
'iE CYPRESS
_ IF SEMICONDUCTOR
CY7C265
Switching Characteristics Over the Operating Rangel 3, 5]
7C265-15
Parameter
Description
Min.
7C265-25
Max.
Min.
Max.
7C265-40
Min.
Max.
7C265-50
Min.
Max.
Unit
tAS
Address Set-Up to Clock
15
25
40
50
tHA
Address Hold from Clock
0
0
0
0
teo
Clock to Output Valid
tpw
Clock Pulse Width
12
15
15
20
ns
tSES
Es Set-Up to Clock (Sync. Enable Only)
12
15
15
15
ns
5
12
15
20
ns
ns
25
ns
tHES
Es Hold from Clock
tm
INIT to Output Valid
tRI
INIT Recovery to Clock
12
15
20
25
ns
tpWI
INIT Pulse Width
12
15
25
35
ns
teas
Output Valid from Clock (Sync. Mode)
12
15
20
25
ns
tHze
Output Inactive from Clock (Sync. Mode)
12
15
20
25
ns
tDOE
Output Valid from E LOW (Async. Mode)
12
15
20
25
ns
tHZE
Output Inactive from E HIGH (Async. Mode)
12
15
20
25
ns
5
15
5
18
ns
5
25
35
ns
Switching Waveform
ADDRESS
SYNCHRONOUS
ENABLE
(PROGRAMMABLE)
CLOCK
OUTPUT
tOOE
ASYNCHRONOUS INIT
(PROGRAMMABLE)
ASYNCHRONOUS
ENABLE
C265-7
Erasure Characteristics
BitMap Data
Wavelengths of light less than 4000 angstroms begin to erase the
7C265 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to
sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity· exposure time) of 25 Wsec/cm2 • For an ultraviolet lamp with a 12
m W/cm 2 power rating the exposure time would be approximately
45 minutes. The 7C265 needs to be within one inch of the lamp
during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Programmer Address (Hex.)
RAM Data
Decimal
Hex
Contents
0
0
Data
8191
8192
8193
1FFF
2000
2001
Data
INITByte
Control Byte
Control Byte
3-77
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
I
£i
I'~PRFSS
,
CY7C265
SEMICONDUCTOR
Programming Modes
The 7C265 offers a limited selection of programmed architectures. Programming these features should be done with a single
lO-ms-wide pulse in place of the intelligent algorithm, mainly because these features are verified operationally, not with the VFY
pin. Architecture programming is implemented by applying the
supervoltage to two additional pins during programming. In programming the 7C265 architecture, Vpp is applied to pins 3,9, and
22. The choice of a particular mode depends on the states of the
other pins during programming, so it is important that the condi-
tion of the other pins be met as set forth in the mode table. The
considerations that apply with respect to power-up and powerdown during intelligent programming also apply during architecture programming. Once the supervoltages have been established
and the correct logic states exist on the other device pins, programming may begin. Programming is accomplished by pulling
PGM from HIGH to LOW and then back to HIGH with a pulse
width equal to 10 ms.
Table 1. Mode Selection
Pin Function
Read or Output Disable
Mode
Other
Asynchronous Enable Read
Al2
Al2
An
An
AIO - A,
AIO - A,
A()
A()
As
As
At- A3
At -A3
A2
A2
A6
As
~-A3
Az
AIZ
A11
AlO - A,
Synchronous Enable Read
A12
A11
AlO - A7
~
As
~-A3
Az
Asynchronous Initialization Read
A12
All
AlO - A7
~
As
~-A3
Az
Program Memory
A12
All
AlO - A7
~
As
~-A3
Az
Program Verify
A12
All
AlO - A7
~
As
~-A3
Az
A12
All
AlO - A7
~
As
~-A3
Az
Program Synchronous Enable
VIHP
VIHP
AlO - A7
VIHP
Vpp
~-A3
VIHP
Program Initialize
VILP
VIHP
AlO - A7
VIHP
Vpp
~-A3
VILP
Program Initial Byte
A12
VILP
AlO - A7
VIHP
Vpp
~-A3
VILP
Program Inhibit
Pin Function
Read or Output Disable
Synchronous Enable Read
Al
Asynchronous Initialization Read
Al
Program Memory
Al
Program Verify
Al
Program Inhibit
Al
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Program Synchronous Enable
Vpp
Program Initialize
Vpp
Program Initial Byte
Vpp
Mode
Other
Asynchronous Enable Read
Al
Al
Al
GND
E,I
PGM
CLK
CLK
VFY
Vpp
D,- Do
V IL
VIL
GND
VIL
07 - 00
V IL
VUJVIH
GND
V IL
07 - 00
VIL
VIL
GND
VIL
07 - 00
VILP
VILP
VIHP
Vpp
D7 - Do
07 - 00
GND
0, - 00
VIHP
VILP
VILP
Vpp
VIHP
VILP
VIHP
Vpp
HighZ
VILP
VILP
VILP
VIHP
Vpp
D7- D O
VILP
VILP
VILP
VIHP
Vpp
D7- D O
VIHP
VILP
VILP
VIHP
Vpp
D7- D O
3-78
s:: :;~
~i.. CYPRF.SS
CY7C265
~, SEMICONDUCTOR
DIP/Flatpack
LCC/PLCC (Opaque Only)
A7
Vee
As
As
u
:t}f]f ~:9]f~
4 3 2,1,282726
25
24
23
22
21
10
20
Ag
AlO
An
Aa
A2
ClK
A12
Vpp
NA
A1
IJF'(
Ao
D7
Ds
D5
D4
Da
JSGM
Do
D1
D2
GND
O
111213141516171~9
A10
An
A12
Vpp
NA
I
IJF'(
D7
en
:E
oa:
C265-9
Q.
C265-8
Figure 1. Programming Pinout
Programming Information
ming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed program-
TYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
60
Z
50
t-
u1.4
.2
Cl
w
N 1.2
::J
40
Cl
W
U
::J
N
~
ex:
@
oz
5.5
.........
"-"-
20
t-
"
t-
0.8'------001..------.....
-55
25
125
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.6
« 175
~
.st- 150
C/)
~ 125
~ 1.41-----+-------1
w
5 100
Cl
~
~
~
ex: 0.81--""7""'----+-------1
oz
0.6 L...-_ _ _ _"---_ _ _ _- - I
-55
25
125
AMBIENT TEMPERATURE (0C)
1.0
2.0
" '""
3.0
4.0
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
35
30
ex:
1.01------+::.,c;...-----I
0
0.0
/
z
U
~
5
AMBIENT TEMPERATURE (0 C)
SUPPLY VOLTAGE (V)
w
"-
~ 10
TA = 25°C
f= MAX.
4.5
w
ex:
ex:
u
/
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
«
.s
enz
75
~ 50
0..
t-
o=>
/
1/
o
0.0
"iil
./
.s
.".,.-
0
~
~
/
20
/~
15
Vee = 5.0V
TA = 25°C
2.0
3.0
OUTPUT VOLTAGE (V)
3-79
5
4.0
/
/"
w 10
Cl
25
1.0
25
LV
/
Vee = 4.5V
TA=25°C I
200
400
600
I
800 1000
CAPACITANCE (pF)
«
~
:~
_r SEMICONDUCTOR
CY7C265
~i. CYPRESS
~
1Ypical DC and AC Characteristics (continued)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
1.05
1.00
I
Vee = 5.5V
TA = 25°C
1
\
~0.95
@0.90
~
N
~0.85
ex:
~0.80
0.75
0.70
o
25
"'" --50
75
100
CLOCK PERIOD (ns)
Ordering Information[6]
Speed Icc
(ns)
(rnA)
15
120
140
25
120
140
40
50
100
SO
120
Package
Name
J64
Ordering Code
CY7C265-15JC
Package 1:ype
28-Lead Plastic Leaded Chip Carrier
CY7C265 -15PC
P21
CY7C265-15WC
W22
2S-Lead (300-Mil) Windowed CerDIP
CY7C265-15DMB
D22
2S-Lead (300-Mil) CerDIP
CY7C265 -15LMB
L64
2S-Square Leadless Chip Carrier
CY7C265 -150MB
064
2S-Pin Windowed Leadless Chip Carrier
CY7C265 -15WMB
W22
2S-Lead (300-Mil) Windowed CerDIP
CY7C265-25JC
J64
2S-Lead Plastic Leaded Chip Carrier
CY7C265 - 25PC
P21
2S-Lead (300-Mil) Molded DIP
CY7C265-25WC
W22
2S-Lead (300-Mil) Windowed CerDIP
CY7C265-25DMB
D22
2S-Lead (300-Mil) CerDIP
CY7C265 - 25LMB
L64
2S-Square Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
CY7C265 - 250MB
064
2S-Pin Windowed Leadless Chip Carrier
CY7C265 - 25WMB
W22
2S-Lead (300-Mil) Windowed CerDIP
CY7C265 -4OJC
J64
2S-Lead Plastic Leaded Chip Carrier
CY7C265-40PC
P21
2S-Lead (300-Mil) Molded DIP
CY7C265-40WC
W22
2S-Lead (300-Mil) Windowed CerDIP
CY7C265 - 50JC
J64
2S-Lead Plastic Leaded Chip Carrier
CY7C265-50PC
P21
2S-Lead (300-Mil) Molded DIP
CY7C265-50WC
W22
2S-Lead (300-Mil) Windowed CerDIP
CY7C265-50DMB
D22
2S-Lead (300-Mil) CerDIP
CY7C265-50LMB
L64
2S-Square Leadless Chip Carrier
CY7C265 - 500MB
064
2S-Pin Windowed Leadless Chip Carrier
CY7C265-50WMB
W22
2S-Lead (300-Mil) Windowed CerDIP
Notes:
6.
Most of these products are available in industrial temperature range.
Cont:oJr.t :oJ Omress reoresentative for soecifications and oroduct avail-
abiiit;;:---
-H---
,
•
Operating
Range
Commercial
•
3-S0
Military
Commercial
Military
Commercial
Commercial
Military
==. ~~
======
j; CYPRESS
,
SEMICONDUCTOR
CY7C265
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIR
VIL
IIX
Ioz
lee
ISB
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
I
en
:t
oa:
a..
Switching Characteristics
Parameter
Subgroups
tAS
7, 8, 9, 10, 11
tHA
teo
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tpw
7, 8, 9, 10, 11
tSES
tHES
7, 8, 9, 10, 11
7, 8, 9, 10, 11
teos
7,8, 9, 10, 11
Document #: 38-00084-E
3-81
CY7C266
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-20 ns (commercial)
- 25 ns (military)
• Lowpower
-660 mW (commercial)
-770 mW (military)
• Super low standby power
-Less than 85 mWwhen deselected
• EPROM technology 100%
programmable
• 5V ±10% Vee. commercial and
military
8K X 8 PROM PowerSwitched and Reprogrammable
• TTL-compatible I/O
• Direct replacement for 27C64
EPROMs
Functional Description
The CY7C266 is a high-performance
8192 word by 8 bit CMOS PROM. When
deselected, the CY7C266 automatically
powers down into a low-power standby
mode. It is packaged in a 600-mil-wide
package. The reprogrammable packages
are equipped with an erasure window;
when exposed to UV light, these PROMs
are erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and
byte-wide intelligent programming algorithms.
The CY7C266 is a plug-in replacement for
EPROM devices. The EPROM cell requires only 12.5V for the super voltage
and low-current requirements allow for
gang programming. The EPROM cells allow for each memory location to be tested
100%, as each location is written into,
erased, and repeatedly exercised prior to
encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer programming, the product
will meet DC and AC specification limits.
Reading is accomplished by pla~ an active LOW signal on OE and CEo The
contents of the memory location addressed by the address lines (Ao through
A12) will become available on the output
lines (00 through 07).
Logic Block Diagram
Pin Configurations
CerDIP
07
Top View
Vee
PROGRAMMABLE
ARRAY
Vee
Vee
Os
NC
MULTIPLEXER
As
Os
As
~
A9
As
OE
A2
A1
cr
A11
A10
Ao
04
07
06
Os
04
03
00
01
02
GND
03
Lec
C266-2
Top View
'" tltl tl tl
.t..r:!>,z~~~
02
As
01
As
~
A3
A2
A1
Ao
00
C266-1
NC
00
4 3 2 ~1. 323130 "
29
5
28
6
27
7
26
8
25
9
24
10
23
11
7C266
22
12
21
13
14151617181920
0
6" &'~~6'od'
C!l
As
A9
A11
NC
OE
A10
cr
07
06
C266-3
Selection Guide
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current (rnA)
Commercial
Military
Commercial
Military
7C266-20
20
120
15
3-82
7C266-25
25
120
140
15
15
7C266-35
35
100
15
7C266-45
45
100
120
15
15
A~
CY7C266
_'=CYPRESS
=:!!!!!!!!:JF
SEMICONDUCTOR
Maximum Ratings
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
UV Exposure ........................... 7258 Wsec/cm2
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential
(Pm 28 to Pin 14) ...................... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
Operating Range
Ambient
Temperature
Range
Commercial
O°C to +70°C
Vee
5V ± 10%
Industrial[1]
-40°Cto +85°C
5V ± 10%
- 55°Cto +125°C
5V ± 10%
Military[2]
Electrical Characteristics Over the Operating Rangel3, 4]
7C266-20
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Vee = Min.,
IOH = - 2.0 rnA
Vee
Vee
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
Com'l
7C266-25
Max.
Min.
Com'l
0.4
Ioz
Output Leakage Current
los
Output Short
Circuit Currentl5]
Vee
Icc
Power Supply Current
Vee = Max., VIN
lOUT = ornA
2.0
+10
-10
V
0.8
V
+10
ItA
Note 4
VOL~ VOUT.5 VOH,
- 40
+40
- 40
+40
ItA
- 20
- 90
- 20
- 90
rnA
120
rnA
Output Disabled
Standby Supply Current
V
0.4
-10
GND ~ VIN ~ Vee
Input Diode
Clamp Voltage
V
0.4
Mil
0.8
Input Current
Unit
2.4
2.0
VeD
Max.
2.4
2.4
Mil
= Min., IOL = 8.0 rnA
= Min., IOL = 6.0 rnA
IIX
ISH
Min.
Test Conditions
= Max., VOUT = GND
= 2.0V,
120
Mil
Chip Enable Inactive,
CE L VIR, lOUT = 0 rnA
Notes:
1. Contact a Cypress representative regarding industrial temperature
range specification.
2. TA is the "instant on" case temperature.
3. See the last page ofthis specification for Group A subgroup testing information.
Com'l
4.
5.
3-83
Com'l
Mil
140
15
15
rnA
15
See the "Introduction to CMOS PROMs" section of the Cypress Data
Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
•
en
:E
oa:
a.
~
~.a
CYPRESS
CY7C266
~, SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangd3, 4] (continued)
7C266-35
Parameter
Description
lest Conditions
VOH
Output HIGH Voltage
Vee
=, Min., IOH = -
VOL
Output LOW Voltage
Vee
= Min., IOL = 16.0 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Current
VeD
Input Diode Clamp
Voltage
loz
Output Leakage Current
Min.
Max.
2.4
4.0 rnA
7C266-45
Min.
0.4
2.0
GND ~ VIN ~ Vee
Unit
0.4
V
V
2.0
0.8
-10
Max.
2.4
+10
-10
V
0.8
V
+10
fAA
Note 4
VOL~ VOUT~ VOH,
-10
+10
-10
+10
fAA
- 20
- 90
- 20
- 90
rnA
100
rnA
Output Disabled
= Max., VOUT = GND
los
Output Short
Circuit Current[5]
Vee
Icc
Power Supply Current
Vee = Max., VIN
lOUT = ornA
ISB
Standby Supply Current
= 2.0V,
Com'l
100
Mil
Chip Enable Inactive,
CE ~ VIR, lOUT = 0 rnA
Com'l
120
15
Mil
15
rnA
15
Capacitance[4]
Parameter
Description
qN
Input Capacitance
COUT
Output Capacitance
lest Conditions
TA = 25°C, f
Vee = 5.0V
3..:...84
= 1 MHz,
Max.
Unit
10
pF
10
pF
-
.~~PRF.SS
F
CY7C266
SEMICONDUcrOR
AC Test Loads and Waveforms
Test Load for -20 through -25 speeds
R1 SOO
R1 SOOQ
OUTP~~~(6S8Q
MIL)
30 pF
I
INCLUDING _
JIG AND SCOPE
OUTP~~~(6S8Q
MIL)
R2 333Q
(403Q MIL)
-=
S pF
I
INCLUDING _
JIG AND SCOPE
(a) Normal Load
3.OV - - - -..J..__----~
II
GND
R2 333Q
(403Q MIL)
_
-
C266-5
(b) High Z Load
C266-4
I
Equivalent to:
THEVENIN EQUIVALENT
RTH 200Q
OUTPUT ~ 2SOIl MIL
Test Load for -35 through - 55 speeds
R12S0Q
R12S0Q
SV~
OUTPUT
SV31
30 pF
I
INCLUDING _
JIG AND SCOPE
OUTPUT
R2 167Q
_
-
S pF
I
INCLUDING _
JIG AND SCOPE
(c) Normal Load
R2 167Q
_
-
C266-6
(d) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
RTH 100Q
OUTPUT ~ 2.0V
Switching Characteristics Over the Operating Rangel l , 2, 4]
7C266-20
7C266-25
Max.
Unit
20
25
35
45
ns
tHzCE
Chip Enable Inactive to High Z
25
30
40
45
ns
tHzOE
Output Enable Inactive to High Z
12
12
20
25
ns
tAOE
Output Enable Active to Output Valid
12
12
20
25
ns
tACE
Chip Enable Active to Output Valid
25
30
40
45
ns
tORA
Data Hold from Address Change
tpu
Chip Enable Active to Power-Up
25
30
40
45
ns
tpD
Chip Enable Inactive to Power-Down
25
30
40
45
ns
Min.
Max.
3
Max.
3
3-85
Min.
7C266-45
Address to Output Valid
Description
Min.
7C266-35
tAA
Parameter
Max.
Min.
3
3
ns
&:~PRFSS
~_,
CY7C266
SEMICONDUCTOR
Erasure Characteristics
EPROM is exposed to high-intensity UV light for an extended
period of time.
7258 Wsec/cm2 is the recommended maximum dosage.
Wavelengths of light less than 4000 angstroms begin to erase the
devices in the windowed package. For this reason, an opaque label should be placed over the window if the EPROM is exposed
to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of25 Wsec/cm 2. For an ultraviolet lamp
with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The CY7C266 needs to be within 1 inch
of the lamp during erasure. Permanent damage may result if the
Programming Modes
Programming support is available from Cypress as well as from a
number of third party software vendors. For.detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[6, 7]
As
A9
AIO
An
A12
CE
OE
VFY
PGM
LAT
NA
NA
CE
Vpp
D7 - Do
Read
As
A9
AlO
A11
A12
VIL
VIL
07 - 00
Standby
X
X
X
X
X
VIH
X
Three-Stated
Normal Operation
Mode
Program
D7 - Do
As
A9
AlO
A11
A12
VIL
VIH
Three-Stated
Program
VIHP
VILP
VILP
VILP
VILP
VILP
Vpp
07- 0 0
Program Verify
VILP
VIHP
VILP
VILP
VILP
VILP
Vpp
07 - 00
Program Inhibit
VIHP
VIHP
VILP
VILP
VILP
VILP
Vpp
Three-Stated
Blank Check
VILP
VIHP
VILP
VILP
VILP
VILP
Vpp
07- 0 0
Output Disable
Notes:
6. X
= "don't care" but must not exceed Vee + 5%.
7.
AddressAg - A12 must be latched throughlinesAo - At in Programmingmodes.
CerDIP
Top View
NC
NA
LCC/PLCC
Top View
Vpp
NC
NC
As
'i/FY
A5
A./A12
AalA11
A2/A1
A1/Ag
J5Gf.if
NA
AoIAs
NC
DO
5
6
7C266
7
8
9
10
11
12
13
14151617181920
0
'i/FY
PGM
NA
NC
Vpp
LAT
CE
07
06
cc5":W~O'O'd'
C266-8
C266-7
Figure 1. Programming Pinout
3-86
~
:~PRESS
::::::::t:.
~,
CY7C266
SEMICONDUCTOR
'lYpical DC and AC Characteristics
1.2
1.2
1.6
u1.4
w
::iE
i=
~1.1
.2
0
w
./
N 1.2
::J
V
«
::iE
a: 1.0
0
z
0.8
./
V
0
«
~
o
1.0
a:
z
N
~
0.9
..::: 0.6
a:
f = fMAX
I
4.5
5.0
0.8
_ _ _-:!-::-_ _ _ _ _....J
-55
25
125
~
5.5
6.0
NORMALIZED ACCESS TIME
vs. TEMPERATURE
«
en
en
w
1.4
~ 50
w
a:
~
«
1.2
.s
gs
w
N 1.0
::J
«
::iE
~
~
~
a:
40
~
0
30
,
20
10
-55
::>
25
125
o
0
o
1.0
"''- "-
.,.,.
z
~ 125
a:
z
./
100
75
U5
~ 50
c..
~
o
25
o
:l:
20
~
15
./
/
/
3.0
10
5
"
/"
Vee = 4.5V
TA = 25°C -
/
00
4.0
/
I
1.00
400
/'
0
/
0.90
«
0.85
N
::J
::iE
Vee = 5.0V
TA = 25°C -
a:
0
z
I
T
Vee = 5.5V
TA = 25°C
""---..
0.80
r--
0.75
V
0.0
w
0.70
1.0
2.0
3.0
4.0
o
OUTPUT VOLTAGE (V)
25
50
75
CYCLE PERIOD (ns)
3-87
600
800 1000
CAPACITANCE (pF)
\
u
.2 0.95
I
I
200
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
~
/
V
1.05
I-
~
25
w
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
.s 150
6
2.0
en
.s
o
~
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (0C)
« 175
6.0
/
30
I-
z
5.5
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
.........
::>
g
5.0
35
I-
a: 0.8
0.6
I
4.5
SUPPLY VOLTAGE (V)
60
U
0
TA = 25°C
0.4
4.0
OUTPUT SOURCE CURRENT
vs.VOLTAGE
1.6
u
u
oz
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE (V)
w
0.8
w
::iE
= 25°C -
---r---
u
W
0
TA
r--- I--.
~ 1.0
w
N
::J
./
V
0.6
4.0
::iE
i=
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
100
•
=.
~
i~PRFSS
~,
CY7C266
SEMICONDUCTOR
Ordering Information[8]
Speed
(ns)
20
25
35
45
Ordering Code
Package
Name
Package 1Ype
CY7C266-20PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C266-20WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C266-25PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C266-25WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C266- 25DMB
D16
28-Lead (600-Mil) CerDIP
CY7C266-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C266- 25QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C266-25WMB
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C266-35PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C266-35WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C266-45PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C266-45WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C266-45DMB
D16
28-Lead (600-Mil) CerDIP
CY7C266-45LMB
32-Pin Rectangular Leadless Chip Carrier
CY7C266-45QMB
L55
Q55
CY7C266-45WMB
W16
28-Lead (600-Mil) Windowed CerDIP
32-Pin Windowed Rectangular Leadless Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIR
VIL
IIx
Ioz
Icc
ISB
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tAOE
tACE
Note:
8. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
Document #: 38-00086-D
3-88
Operating
Range
Commercial
Commercial
Military
Commercial
Commercial
Military
CY7C269
CYPRESS
SEMICONDUCTOR
Features
• CMOS for optimum speed/power
• High speed (commercial and military)
-15-ns max set-up
-12-ns clock to output
• Lowpower
-660 mW (commercial)
-770 mW (military)
• On-chip edge-triggered registers
- Ideal for pipelined microprogrammed systems
8K X 8 Registered
Diagnostic PROM
• On-chip diagnostic shift register
- For serial observability and controllability of the output register
• EPROM technology
-100% programmable
- Reprogrammable (7C269W)
• 5V ± 10% Vee, commercial and
military
• Capable of withstanding >2001V
static discharge
• Slim 300-mil, 28-pin plastic or hermetic DIP
Logic Block Diagram
Functional Description
The CY7C269 is a 8K x 8 registered diagnostic PROM. It is organized as 8,192
words by 8 bits wide, and has both a pipeline output register and an onboard diagnostic shift register. The device features a
programmable initialize byte that may be
loaded into the pipeline register with the
initialize signal. The programmable initialize byte is the 8,193rd byte in the
PROM, and may be programmed to any
desired value.
Pin Configurations
CerDIPlFlatpack
Top View
A7
Vee
As
As
A5
As
""
A10
A11
Aa
A2
MODE
CLOCK
A1
A12
E/l:s. j
SDI
SDO
07
06
05
04
03
Ao
00
01
02
GND
C269-2
SDI
LCC/PLCC (Opaque Only)
SDO
TopVi~w
~ )f:tJt~:e ~
As
A2
MODE
CLOCK
A1
Ao
00
4 3 2,1,282726
25
24
7
23
8
22
9
21
10
20
11
19
12131415161718/
5
0
>6
o8'~80'88
C!)
C269-3
C269-1
Selection Guide
Maximum Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating Current
(rnA)
I Commercial
I Military
7C269-15
15
12
120
140
3-89
7C269-25
7C269-40
7C269-50
25
15
120
140
40
20
100
50
25
80
120
I
en
:::!E
oa:
a..
#4
~=
~_,
CY7C269
CYPRF.SS
SEMICONDUCTOR
Functional Description (continued)
The CY7C269 is optimized for applications that require diagnostics in a minimum amount of board area. Packaged in 28 pins, it has
13 address signals (Ao throughA12), 8 data out signals (00 through
07), Ell (Enable or Initialize), and CLOCK (pipeline and diagnostic clock). Additional diagnostic signals consist of MODE, SDI
(shift in), and SDO (shift out). Normal pipelined operation and
diagnostic operation are mutually exclusive.
When the MODE signal is Law, the 7C269 operates in a normal
pipelined mode. CLOCK functions as a pipeline clock, loading the
contents of the addressed memory location into the pipeline register on each rising edge. The data will appear on the outputs if they
are enabled. One pin on the 7C269 is programmed to perform either the Enable or the Initialize function. If the EJI pin is used for
a INIT (asynchronous initialize) function, the outputs are permanently enabled and the initialize word is loaded into the pipeline
register on a HIGH to LOW transition of the INIT signal. The
INIT LOW disables CLOCK and must return high to re-enable
CLOCK. If the Ell pin is used for an enable signal, it may be programmed for either synchronous or asynchronous operation.
When' the MODE~ignal is HIGH, the 7C269 operates in the diagnostic mode. The Ell signal becomes a secondary mode signal designating whether to shift the diagnostic shift register or to load either the diagnostic register or the pipeline register. IfEll is HIGH,
it shifts SDI into the least-significant location of the diagnostic register and all bits one location toward the most-significant location
on each rising edge. The contents of the most-significant location
in the diagnostic register are available on the SDO pin.
If the EJI signal is Law, SDI becomes a direction signal, transferring the contents of the diagnostic register into the pipeline register
when SDI is Law. When SDI is HIGH, the contents of the output
pins are transferred into the diagnostic register. Both transfers occur on a LOW to HIGH transition ofthe CLOCK. If the outputs
are enabled, the contents of the pipeline register are transferred
into the diagnostic register. If the outputs are disabled, an external
source of data may be loaded into the diagnostic register. In this
condition, the SDO signal is internally driven to be the same as the
SDI signal, thus propagating the "direction of transfer information" to the next device in the string.
Maximum Ratings
Latch-Up Current ........................... >200 rnA
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Operating Range
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .... : . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
DC Program Voltage ............................. 13.0V
UVExposure ........................... 7258 Wsec/cm 2
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Industrial[1]
- 40°C to +85°C
5V ± 10%
Military[2]
- 55°C to +125°C
5V ± 10%
Range
Commercial
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3-90
=-_
~~PRESS
"
CY7C269
~kCONDUCfOR
Electrical Characteristics Over the Operating Rangel 3,4]
Parameter
VOH
VOL
7C269-15,25
Min. Max.
Test Conditions
Description
= Min., IoH = - 20 rnA
Va::, = Min., IoH = - 4.0 rnA
Vee = Min., 10L = 8.0 rnA Com'l
Vee = Min., 10L = 6.0 rnA Mil
Output mGH Voltage Va::,
Output LOW Voltage
7C269-40
Min. Max.
2.4
VIH
= Min., 10L = 8.0 rnA
VIL
Input LOW Voltage
Input Load Current
GND oS VIN oS Vee
loz
Output Leakage
Current
GND oS VOUT oS Vee,
Output Disabled
los[5]
Output Short Circuit
Current
Icc
Vee Operating Supply Va::,
Current
V
Vpp
Programming Supply
Voltage
Ipp
Programming Supply
Current
VIHP
InputmGH
Programming Voltage
VILP
Input LOW
Programming Voltage
0.4
0.4
0.4
0.4
2.0
2.0
0.8
0.8
-10
-40
= Max., lOUT = 0 rnA
V
0.4
2.0
Irx
2.4
0.4
Mil
Input mGH Voltage
Unit
V
2.4
Vee = Min., 10L = 12.0 rnA Com'l
Vee
7C269-50
Min. Max.
V
0.8
V
-10
+10
-10
+10
+40
-40
+40
-40
+40
!-lA
!-lA
90
rnA
80
rnA
90
Com'l
120
100
Mil
140
13
120
12
50
3.0
13
50
3.0
0.4
12
13
V
50
rnA
3.0
0.4
V
0.4
V
Capacitance[4,6]
Parameter
Description
CIN
Input Capacitance
CoUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Notes:
3. Seethe last page of this specification for Group A subgroup testing information.
4. See Introduction to CMOS PROMs in this Data Book for general information on testing.
5.
6.
3-91
= 1 MHz,
Max.
Unit
10
pF
10
pF
II
U)
:Ii
+10
90
12
V
For test pUIposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
oa:
Q.
&¥.~PRKSS
~,
CY7C269
SEMICONDUCTOR
AC Test Loads and Waveforms
Test Load for-IS through -2S,speeds
R1 500
R1 5000
OUTP~~31(6580 ':'IJTPS;~.
MIL) R2
30 pF
I .
INCLUDING _
JIG AND SCOPE
(a)
(6511!l MIL) R2
(4030 MIL)
_
-
Norm~1
5 pF
I
INCLUDING _
JIG AND SCOPE
Load
mc
3.0V -------..u-----~
GND
(4030 MIL)
_
C269-5
C269-4
(b) High Z Load
Equivalent to:
THEVENIN EQUIVALENT
RTH2000
OUTPUT ~ 2501l MIL
Test Load for -40 through -50 speeds
R12500
R12500
OUTP~~31
30
PFI
INCLUDING _
JIG AND SCOPE
OUTP~~~
R2167Q
. 5
_
-
PF I
INCLUDING _
JIG AND SCOPE
(c) Normal Load
R21670
_
-
C269-6
(d) High Z Load
I
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
~
2.0V
Switching Characteristics Over the OperatinR Rangd3,4j
7C269-I5
Parameter
Description
Min.
Max.
7C269-25
Min.
Max.
7C269-40
Min.
Max.
7C269-50
Min.
tAS
Address Set-Up to Clock
15
25
40
50
tAH
Addres~
0
0
0
0
teo
Clock to Output Valid
Hold from Clock
12
20
15
Max.
Unit
ns
ns
25
ns
tpw
Clock Pulse Width
12
15
15
20
ns
tSES
Es Set-Up to Clock (Sync Enable Only)
12
15
15
15
ns
tHES
Es Hold from Clock
5
5
5
5
tm
INIT to Out Valid
tRI
INIT Recovery to Clock
12
15
20
25
ns
tpWI
INIT Pulse Width
12
15
25
35
ns
teas
Output Valid from Clock (Sync. Mode)
12
15
20
25
ns
tHze
Output Inactive from Clock (Sync. Mode)
12
15
20
25
ns
tDOE
Output Valid from E LOW (Asynch. Mode)
12
15
20
25
ns
tHZE
Output Inactive from E HIGH (Async. Mode)
12
15
20
25
ns
15
3-92
25
18
ns
35
ns
~.~
--=-
CY7C269
~i= CYPRESS
iF
SEMICONDUcrOR
Diagnostic Mode Switching Characteristics Over the Operating Range[3,4]
7C269-1S
Parameter
Description
Min.
Max.
7C269-2S
Min. Max.
7C269-40,SO
Min.
Max.
tssm
Set-Up SOl to Clock
Com'l
20
25
30
Mil
25
30
35
tHsm
SOl Hold from Clock
Com'l
0
0
0
Mil
0
0
0
tDSDO
tDCL
tDCH
tSM
tHM
tMS
tss
tso
tHO
SDO Delay from Clock
Minimum Clock LOW
Minimum Clock HIGH
Set-Up to Mode Change
Hold from Mode Change
Mode to SDO
SDI to SDO
Data Set-Up to DCLK
Data Hold from DCLK
ns
Com'l
20
25
30
Mil
25
30
40
Com'l
20
25
25
Mil
25
25
25
Com'l
20
25
25
Mil
25
25
25
Com'l
20
25
25
Mil
25
30
30
Com'l
0
0
0
Mil
0
0
0
ns
ns
ns
20
25
25
Mil
25
30
30
Com'l
30
40
40
Mil
35
40
45
20
25
25
Mil
25
30
30
Com'l
10
10
10
Mil
13
13
15
ns
ns
Com'l
Com'l
Unit
ns
ns
ns
ns
ns
Switching Waveforms[3,4]
Pipeline Operation (Mode = 0)
ADDDRESS
SYNCHRONOUS
ENABLE
PROGRAMMABLE _ _ _oJ
PCLKlCLOCK
OUTPUT
tOOE
ASYNCHRONOUS
ENABLE _ _ _ _ _ _-'
C269-7
3-93
•
en
::t
oa:
D.
dC;~~PRESS
~,
CY7C269
SEMICONDUCTOR
Diagnostic Application (Shifting the Shadow Register(71)
CLOCK
MODE
SDO
SDI
C269-B
Diagnostic Application (Parallel Data 1ransfer)
CLOCK
MODE
SDI
SDO
E/I
Notes:
7. Diagnostic register = shadow register = shift register.
8. Asynchronous enable mode only.
9.
3-94
The mode transition to HIGH latches the asynchronous enable state.
If the enable state is changed and held before leaving the diagnostic
mode (mode H • L) then the output impedance change delay is tMS.
~-~
CY7C269
'j; CYPRF.SS
SEMICONDUcrOR
~ IF
BitMap Data
Programmer Address (Hex.)
RAM Data
Decimal
Hex
Contents
0
0
Data
8191
8192
8193
1FFF
2000
2001
Data
Init Byte
Control Byte
•
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
CerDIP/Flatpack
A7
As
AsfVpp
~
~
A2
PGM
NA
Al
Ao
Do
01
02
GNO
LCC/PLCC (Opaque Only)
Il.
Il.
vee
As
.t~:e.t~.f~
Ag/Vpp
Al0
All
A12
Vpp
NA
VFY
07
06
05
04
03
Il.
Il.
4 3 2~ 282726
25
24
23
NA
22
21
Al
20
Ao 10
19
00 11
\. 12131415161718
~
~
0
AlO
All
A12
Vpp
NA
VFY
07
o8'~;M'd"86"
C)
C269-11
C269-10
Figure 1. Programming Pinouts
3-95
s.~CYPRESS
~,
CY7C269
SEMICONDUcrOR
Mode Selection
Pin FunctionllOJ
Read or Output Disable
A12
Au
AIO - A,
At;
As
Other
A12
Au
AIO - A,
At;
As
Ai -A3
Ai -A3
A2
Al
Read
A12
All
AlO - A7
As
~-A3
A2
Al
LoadSR toPR
A12
All
AlO - A7
As
~-A3
A2
Al
Load Output to SR
A12
All
AlO - A7
As
~-A3
A2
Al
Mode
Shift SR
A12
All
AlO - A7
Asynchronous Enable Read
A12
All
AlO - A7
Synchronous Enable Read
A12
All
AlO - A7
Asynchronous Initialization Read
A12
All
AlO - A7
Program Memory
A12
All
AlO - A7
Program Verify
A12
All
AlO - A7
Program Inhibit
A12
All
AlO - A7
Ati
Ati
Ati
Ati
Ati
Ati
Ati
Ati
Ati
Ati
Program Synchronous Enable
VIHP
VIHP
AlO - A7
Program Initialize
VILP
VIHP
AlO - A7
Program Initial Byte
A12
VILP
AlO - A7
A2
Al
As
~-A3
A2
Al
As
~-A3
A2
Al
As
~-A3
A2
Al
As
~-A3
A2
Al
As
~-A3
A2
Al
As
~-A3
A2
Al
As
~-A3
A2
Al
VIHP
Vpp
~-A3
VIHP
Al
VIHP
Vpp
~-A3
VILP
Al
VIHP
Vpp
~-A3
VILP
Al
Pin FunctionllUJ
Read or Output Disable
Mode
Other
Read
LoadSR toPR
Load Output to SR
ShiftSR
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
Program Verify
Program Inhibit
Program Synchronous Enable
CLK
CLK
sm
SDO
E,l
PGM
NA
VFY
Vpp
D, - Do
VIL
VnjVIH
X
HighZ
VIL
07 - 00
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
MODE
VILP
0,- 00
VIH
VnJVIH
VIL
SDI
VIL
07 - 00
VIH
VUjVIH
VIH
SDI
VIL
07 - 00
VIH
VnJVIH
DIN
SDO
VIH
07 - 00
VIL
VIL
X
HighZ
VIL
07 - 00
VIL
VnjVIH
X
HighZ
VIL
07 - 00
07 - 00
VIL
VIL
X
HighZ
VIL
VILP
VILP
X
VIHP
Vpp
D7- D O
VIHP
VILP
X
VILP
Vpp
07 - 00
VIHP
VILP
X
VIHP
Vpp
HighZ
VILP
VILP
X
VIHP
Vpp
D7- D O
Program Initialize
VILP
VILP
VILP
X
VIHP
Vpp
D7 - Do
Program Initial Byte
VIHP
VILP
VILP
X
VIHP
Vpp
D7 - Do
Note:
10. X = "don't care" but not to exceed Vee + 5%.
3-96
· -4
CY7C269
_'iECYPRESS
-====;;
SEMICONDUcrOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
l
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
60
I-
u1.4
.2
Cl
w
N 1.2
::J
«
lee
::2:
cc 1.0
0
z
O.B
V
0.6
4.0
/V
V
TA
f
4.5
5.0
./
::2:
~ 20
~ 10
= MAX.
O.BL-------1---_ _--J
-55
25
125
6.0
/~
::J
«
z
Ci5
~ 50
5
0.6
-55
25
o
25
1/
0.0
125
AMBIENT TEMPERATURE (0C)
.s
0
:l
~
w
/
/
a..
u;
-
~
/
75
I-
V
Cl
Vee = 5.0V
TA = 25°C
1.0
2.0
3.0
4.0
1.05
1.00
Cl
w 0.90
Vee = 5.5V
TA = 25°C
~
N
«
::2:
I
\
\
0.B5
"
cc
0 O.BO
z
0.75
0.70
o
25
'"
50
~
75
CLOCK PERIOD (ns)
3-97
/'
20
/
15
10
o/
o
/'"
/V
Vee = 4.5V
TA = 25°C I
200
400
600
I
BOO 1000
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
~ 0.95
/
25
5
OUTPUT VOLTAGE (V)
::J
4.0
30
B 100
~
'"
3.0
35
cc
z
2.0
r-....
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
~ 125
/
1.0
'""'-
I
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
/""
1.2
0
0.0
AMBIENT TEMPERATURE (0C)
en
::2:
cc O.B
0
5
I-
w
N 1.0
'""'"
I-
lz :::
Cl
"
I-
= 25°C
1.6
w
~
:::>
cc
oz
i= 1.4
en
«
40
~ 30
cc
::J
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
()
()
:::>
()
W
N
SUPPLY VOLTAGE (V)
w
::2:
50
cc
cc
~
Cl
«
5.5
r5
100
~~
~~CYPRESS
CY7C269
~, SEMICONDUcrOR
Ordering Information[ll]
Speed Icc
(ns) (rnA)
15
120
140
25
140
40
100
50
80
120
Ordering Code
CY7C269-15JC
CY7C269-15PC
CY7C269-15WC
CY7C269-15DMB
CY7C269-15LMB
CY7C269-150MB
CY7C269--15WMB
CY7C269-25JC
CY7C269-25PC
CY7C269-25WC
CY7C269-25DMB
CY7C269- 25LMB
CY7C269- 250MB
CY7C269-25WMB
CY7C269-40JC
CY7C269-40PC
CY7C269-40WC
CY7C269-5OJC
CY7C269-50PC
CY7C269-50WC
CY7C269-50DMB
c'Y7C269-50LMB
CY7C269-500MB
CY7C269-50WMB
Package
Name
J64
P21
W22
D22
L64
064
W22
J64
P21
W22
D22
L64
064
W22
J64
P21
W22
J64
P21
W22
D22
L64
064
W22
Package tYpe
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Commercial
Military
Switching Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOH
VOL
VIR
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tAS
tHA
7, 8,9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
7, 8, 9,
VIL
IIX
Ioz
Icc
ISB
teo
tpw
tSES
tHES
teas
Note:
11. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-98
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
.
:~PRESS
CY7C269
_ , SEMICONDUcrOR
Diagnostic Mode Switching Characteristics
Parameters
Subgroups
tssm
7, 8, 9, 10, 11
tHsm
7, 8, 9, 10, 11
tDSDO
7, 8, 9, 10, 11
tDCL
7, 8, 9, 10, 11
tDCH
tHM
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tMS
7, 8, 9, 10, 11
tss
7, 8, 9, 10, 11
II
Document #: 38-00069-G
3-99
CY7C270
CYPRESS
SEMICONDUCTOR
Features
Reprogrammable 16K X 16
Processor-Intelligent PROM
• 100% reprogrammable in windowed
packages
• TTL-compatible I/O
• Capable of withstanding greater than
2001V static discharge
• O.S-micron CMOS for optimum
speed/power
• High speed (for commercial and
military)
- 25-ns single access time
-11-ns burst access time
Functional Description
The CY7C270 is a 16K-word by 16-bit
PROM designed to support a number of
popular microprocessors with little or no
"glue" logic. This PROM is packaged in a
44-pin PLCC package and a 44-pin LCC
package. The CY7C270 is available in windowed packages for 100% reprogrammability. The memory cells utilize proven
EPROM floating-gate technology.
The CY7C270 offers a number of programmable features that allow the user to
configure the PROM for use with their
• 16-bit-wide words
• Input address registered, latched, or
transparent
• On-chip programmable burst logic
• Programmable compatibility with
many common microprocessors
• Three programmable chip selects
• Programmable output enable
• 44-pin PLCC and 44-pin LCC
packages
REGISTER 1 - - - - - - - - - - - 1
LATCH
chosen microprocessor. The programmable features include a choice between
registered and latched modes of operation. The CY7C270 also has an on-board
programmable counter for burst reads.
The user may select a 2-bit, 4-bit, or 8-bit
linear counter, or program the PROM to
use the Intel 80486 burst pattern (Table
2). A separate control input (ADV) is
used to choose between single reads and
bursts. In addition, the burst counter and
latch may be bypassed for asynchronous
operation to be used with nsp processors.
The CY7C270 allows the user to independently program the polarity of each chip
select (CS2 - CSo). This provides on-chip
decoding of up to eight banks of PROM.
The polarity of the asynchronous output
enable pin (OE) is also programmable.
16Kx 16
PROGRAMMABLE
ARRAY
ClK
CS
REGISTER
LATCH
CS
DECODE
C270-1
Selection Guide
Minimum Clock Period (ns)
~~~:~(~~erating
I
I
Commercial
Military
3-100
CY7C270-15
CY7C270-20
15
20
30
175
200
175
175
200
200
CY7C270-30
.~
·
CY7C270
i j;; CYPRESS
~? SEMICONDUCTOR
Pin Configuration
Single Read Access in Latched Mode
In latched mode, the CY7C270 can take advantage of situations
where the address is available well before the rising edge of CLK.
A read is initiated when the latch is opened (on the falling edge of
LE). The address is sent directly to the PROM core and to the
counter. The contents of the memory location addressed by the
original address are delivered to the outputs. The latch is closed
when LE is de asserted.
LCC/PLCC (Opaque Only)
Top View
012
011
010
D9
6 5 4 3 2,1,4443424140
39
De
D5
9
10
11
12
13
14
15
16
D4
17
De
Vss
Vee
D7
Burst Sequence
o
During a burst, the first read is initiated as a single access read. After the initial read, the LE input is held inactive. The advance enable input (ADY) controls the address sequencing starting with the
second read. ADV is sampled on the rising edge of the CLK input.
If ADV is sampled LOW, the address is incremented to the next 10cation. The number of address bits incremented by the counter is
programmed by the user. The counter wraps around after reaching
the maximum count without affecting other bits in the address.
31
29
18192021 22232425262728
MC\lT"""OWC/)O .....
o
0
0
0
0
C\I('I)~
>00« « « « «
Special burst advancement logic is included in the CY7C270 to
support the Intel 80486 burst operation. The 80486 bursts in the
non-sequential pattern shown in Table 2.
C270-2
Operating Modes
The CY7C270 can be specifically configured for use with many
popular microprocessors. The PROM configuration for some of
these processors is detailed in Table 1. Note that many of the processors can use either registered or latched mode depending on
their speed.
Some processors have the capability to suspend a burst. In order to
suspend a burst in the CY7C270 the processor must simply deassert the ADV input. When the ADV input is reasserted the burst
will continue from where it left off. It is not necessary for the processor to send a new address to the PROM.
Table 2. Look-Up Table for Use with Intel 486
Table 1. Processor-Intelligent PROM Configuration
Processor
Registered/Latched
SPARC
Registered
Intel 486
Latched
80386
Latched
Motorola 68040
Latched
First
Address
Burst Counter
Second
Address
Third
Address
Fourth
Address
Ax
Ax+ 1
Ax
Ax+ 1
Ax
Ax+ 1
Ax
Ax+ 1
-
0
0
0
1
1
0
1
1
Table Logid1J
0
1
0
0
1
1
1
0
-
1
0
1
1
0
0
0
1
2-Bit Counter
1
1
1
0
0
1
0
0
Motorola 68030
Latched
2-Bit Counter
Intel80960KB
Registered
2-Bit Counter
Intel 80960CA
Latched
2-Bit Counter
AMD29000
Latched
8-Bit Counter
MIPS R3000
Registered
-
MIPS R2000
Registered
-
Motorola 88000
Registered
-
Application Example 1
CLK
eLK
Note:
1. The Intel 486 uses a non-sequential burst. The CY7C270 is equipped
with a look-up table (described in Table 2) for use with this processor.
Single Read Access in Registered Mode
Intel
486
IT
ADS
DATA
ADR
DATA
A29
Aao
A31
ADR
eso
eS1
eS2
CY7C270
ADV
A read access is initiated in registered mode on the rising edge of
CLK if all three chip selects are asserted and LE is sampled LOW.
The address applied to the input is stored in a register and is delivered to both the PROM core and the counter. The contents of the
memory location accessed by the original address are delivered to
the outputs. When LE is asserted the system ignores the advance
enable (ADY) input.
3-101
m:
-=
C270-3
80486 Instruction Memory Using 1\'1'0 CY7C270s
I
en
:E
0
a:
a..
;,r~
CY7C270
Application Example 2
Pin Definitions
Signal Name
A13
PCLK
,
00- 0 31
,
/14
I
80960CA
,
I
Clock
00- 0 31
LE
I
Latch Enable
ADV
I
Advance Enable
CS2 - CSo
I
Programmable Chip Selects
CSo. CS1. CS2
F
Address Inputs
CLK
Ao-A13
/3
I
ClK
[E
ADS
ADR
/32
-Ao
Description
I/O
CY7C270
(16K x 16)
7fJ5V (2 PROMs)
OE
I
Programmable Output Enable
DIS - Do
0
Data Outputs
OE
Vee
-
Power Supply
Vss
-
Ground
Intel80960CA Using 1\vo CY7C270s
Pin Descriptions
Input Signals
A13 - Ao (Address lines). The address inputs are stored in a register at the rising edge of CLK if the device is programmed in registered mode. If the device is programmed in latched mode, the address inputs flow into the PROM while LE is active and are
captured at the rising edge of LE. For asynchronous operation, the
device should be programmed in the latch mode with LE tied
LOW.
CLK (Clock line). The clock is used to sample the ADV input. In
registered mode, the clock is also used to sample LE, CS2 - CSo,
and the address.
LE (Latch Enable). In registered mode, this input is sampled on
the rising edge of CLK. If it is active, the address and chip selects
are stored in a register. In latched mode, the address and chip selects are latched on the rising edge of this signal.
ADV (Advance Enable). This signal is used for burst reads. IfLE is
inactive, ADV is sampled on the rising edge of CLK. If ADV is
Maximum Ratings
LOW, the counter will be incremented and the next address will be
delivered to the PROM core. ADV should be tied HIGH, and in
the programming mode, the burst enable (BE) should be disabled
for asynchronous operation.
CS2 - CSo (Synchronous Chip Selects). The polarity of each chip
select is programmed by the user. The inputs from these pins are
stored in a register on the rising edge of CLK in registered mode. In
latched mode, the inputs are latched on the rising edge ofLE. All
three chip selects must be active in order to select the device.
OE (Asynchronous Output Enable) . The polarity of this pin is programmable. The outputs are active when OE is asserted and tristated when OE is deasserted.
Output Signals
DIS - Do (Data Outputs). Data from the array location addressed
on inputs A 13 - Ao will appear on these pins. The outputs will be
tri-stated if OE is deasserted or if the chip is not selected.
Operating Range
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
UV Erasure ............................. 7258 Wsec/cm2
Ambient
Temperature
Vee
O°C to +70°C
5V ±1O%
Industrial[2]
- 40°C to +85°C
5V ±1O%
Military[3]
- 55°C to +125°C
5V ±10%
Range
Commercial
Notes:
2.
3.
Static Discharge Voltage ........................ > 2001 V '
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
3-102
Contact a Cypress representative for industrial temperature range
specifications.
TA is the "instant on" case temperature.
~
~.~
CY7C270
~ill CYPRF.SS
~, SEMICONDUCTOR
Electrical Characteristics[4, 5]
Parameter
Description
Test Conditions
Min.
Max.
Unit
Vee
Output LOW Voltage
= Min., IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA (6.0 rnA Mil)
2.4
0.4
V
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
2.0
Vee
V
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
-3.0
0.8
V
IIX
Input Leakage Current
GND.5. VIN.5. Vee
-10
+10
VeD
Input Clamp Diode
Voltage
!lA
!lA
loz
Output Leakage
Current
Vee = Max., VOL.5. VOUT .5. V OH,
Output Disabled
- 40
+40
!lA
los
Output Short Circuit
Current
Vee
= Max., VOUT = 0.OV[6]
- 20
-90
rnA
Icc
Power Supply Current
Vee
= Max., lOUT = 0.0 rnA
ICom'l
175
rnA
I Military
200
rnA
VOH
Output HIGH Voltage
VOL
VIH
V
Note 4
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
10
pF
10
pF
Notes:
4.
5.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
See the last page of this specification for Group A subgroup testing information.
6.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
AC Test Loads and Waveforms
R1 SOOn
R1 SOOn
5V T I ( 6 5 s
MIL)
n
OUTPUT
R2
OUTPUT
333rr
(403 n MIL)
I
50 pF
~~8~~~NG
-=
-=
SCOPE
ALL INPUT PULSES
5V 5 F i ( 6 5MIL)
sn
-=
90%
R2
GND
333rr
(403 n MIL)
I
5 pF
~~8~~~NG
3.0V----
-=
SCOPE
C270-5
(a) Normal Load
(b) High Z Load
C270-4
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
200n (250n MIL)
2.0V
(1.9V MIL)
o---vw--o
C270-6
3-103
I
=
~
~~
~CYPRESS
CY7C270
~, SEMICONDUCTOR
Switching Characteristics Over the Operating RangerS)
Commercial and Military
Parameter
Description
Clock Period
CY7C270-15
CY7C270-20
CY7C270-30
Min.
Min.
Min.
Max.
Max.
Max.
Unit
15
20
30
ns
. Clock HIGH Pulse Width
6
8
13
ns
tCL
Clock LOW Pulse Width
6
8
13
ns
tAS
Address Set-Up to CLK Rise
3
4
4
ns
tAR
Address Hold from CLK Rise
2
3
4
ns
tLES
LE Set-Up to CLK Rise
3
4
4
ns
tLEH
LE Hold from CLK Rise
2
3
4
ns
tLW
Latch Pulse Width
7
10
12
ns
tADVS
ADV Set-Up to CLK Rise
3
4
4
ns
tADVH
ADV Hold from CLK Rise
2
3
4
ns
tASL
Address Set-Up to Latch Close
3
4
4
ns
tARL
Address Hold from Latch Close
2
3
4
ns
tDH
Data Hold
3
3
3
ns
tAA
Address to Data for Single Read
25
28
35
ns
tLEA
LE Low to Data Valid for Single Read
25
28
35
ns
tCKA
Clock to Data for Single Read
25
28
35
ns
tCKB
CLK Rise to Data for Burst Read
11
12
15
ns
tcss
CS Set-Up to CLK Rise
3
4
4
ns
tCSH
CS Hold from CLK Rise
2
3
4
ns
tcov
CLK Rise to Output Valid
11
12
tcoz
CLK Rise to High Z Output
11
tcsov
CS Asserted to Output Valid
13
tcsoz
CS Deasserted to High Z Output
13
tCSSL
CS Set-Up to Latch Close
3
4
4
ns
tCSHL
CS Hold from Latch Close
2
3
4
ns
tLOV
Latch Open to Output Valid
13
15
18
ns
tLOZ
Latch Open to High Z Output
13
15
18
ns
tOEV
OE Asserted to Output Valid
11
12
15
ns
tOEZ
OE Deasserted to High Z Output
11
12
15
ns
tcp
tCH
3-104
15
ns
12
15
ns
15
18
ns
15
18
ns
·
.~
~iE
IF
--=-
CY7C270
CYPRESS
SEMICONDUcrOR
Switching Waveforms
Single Reads - Registered Mode[?' 8]
I
o
:E
o
a:
Q.
C270-7
Single Reads - Latched Mode[8]
--------~~---------------tLW------------------·I~
LE
,------+------------~
XXXXXX
~----------~SL----------__.~~
VAUD to"
,-----------------
~AAxxl----V-ALI-D- - - C270·8
4-Word Burst Followed by Single Read - Registered Mode[8]
C270·9
Notes:
7. ADV is assumed HIGH.
8.
3-105
CS2 - CSo, OE are assumed active.
z·
i~PRESS
?
CY7C270
SEMICONDUCTOR
Switching Waveforms (continued)
4·Word Burst Followed by Single Read - Latched Mode[8]
C270-10
Suspended Bursd8, 9]
C270-11
Output Controlled by CS and CLK - Registered Mode[lO]
ClK
tcss--~---
INACTIVE
__________________
tc_o_z~
__~~_
_ ____________________________________tc_o_v_--=:t
---K.
D15 - Do
HIGH Z
VALID
- - - - - - - - - - - - - - - - - - - - - - - - ' HIGH Z
C270-12
Notes:
9. Burst in progress.
10. OE assumed active.
3-106
====.- .4
--=-,
_'ill
CY7C270
CYPRF.SS
SEMICONDUCTOR
Switching Waveforms
(continued)
Outputs Controlled by CS and LE - Latched Mode
IT - - - - - ,
CS 2 - CSo
D15 - Do
•
INACTIVE
en
:E
oa:
-----------fC
HIGHZ
A.
HIGHZ
C270-13
t
Outputs Controlled by OE[lI]
OE
ACTIVE
LOW[12]
--------------1=
toEV
HIGH Z
j
to" ~
HIGH Z
D15-Do------------------l-~(~_ _ _ _ _V_A_L_ID___________~
__ ~------C270-14
Notes:
11. CS2 - CSo are assumed active.
12. OE active HIGH is a programmable option.
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the is exposed to high intensity UV light for an extended period of
CY7C270. For this reason, an opaque label should be placed over time. 7258 Wsec/cm2 is the recommended maximum dosage.
the window if the PROM is exposed to sunlight or fluorescent light- Architecture Configuration Bits
ing for extended periods of time.
The CY7C270 is configured by programming the Control Word loThe recommended dose for erasure of ultraviolet light is a wave- cated at the end of the programmable array (4000H). Table 3 gives
length of 2537 Angstroms for a minimum dose (UV intensity mul- the specific information for configuring the architecture.
tiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm 2 power rating the exposure time would be ap- To use the CY7C270 as a purely asynchronous PROM, tie the ADV
proximately 35 minutes. The 7C270 needs to be within 1 inch of the signal to Vco the CLKand I.E signal to V ss, and program the control
lamp during erasure. Permanent damage may result if the PROM word for No Burst and Latched mode of operation (D3 = 1 ,Dl5 =0).
Table 3. Control Word for Architecture Configuration
Control Word
Programmed Level
Control Option
Bit
OE
Output Enable
Do
Cl Co
(Counter Configuration)
D2Dl
RIL
RegisteredlLatched
D3
0= Default
1 = Programmed
Registered Mode
Latched Mode
CSo
Chip Select 0
D12
0= Default
1 = Programmed
CSo Active LOW
CSo Active HIGH
CSl
Chip Select 1
D13
0= Default
1 = Programmed
CSl Active LOW
CSl Active HIGH
CS2
Chip Select 2
Dl4
0= Default
1 = Programmed
CS2 Active LOW
CS2 Active HIGH
BE
(Burst Enable)
Dl5
0= Default
1 = Programmed
No Burst
Burst (follow Cl Co)
Function
0= Default
1 = Programmed
OE Active LOW
OE Active HIGH
00
01
10
11
486 2-Bit Counter
Linear 2-Bit Counter
Linear 4-Bit Counter
Linear 8-Bit Counter
=
=
=
=
Default
Programmed
Programmed
Programmed
3-107
:=S==~PRE§
~,
CY7C270
SEMICONDUCTOR
Bit Map
Table 4. Program Mode Table
Programmer Address (Hex)
0000
RAM Data
Data
3FFF
Data
4000
Control Word
BE CS2 CSI CSo X X X X X X X X R!L
c\
PGM
VFY
Do - DIS
Vpp
VIHP
VIHP
HighZ
Program Enable
Vpp
VILP
VIHP
Data
Program Verify
Vpp
VIHP
VILP
Data
Table 5. Configuration Mode Table
Vpp
PGM
VFY
A2
Program Inhibit
Vpp
VIHP
VIHP
Vpp
HighZ
Program Control
Word
Vpp
VILP
VlHP
Vpp
Control Word
Verify Control
Word
Vpp
VIHP
VILP
Vpp
Control Word
Mode
Control Word (4000H - default state is OOH)
D~
Vpp
Program Inhibit
Mode
Do
Co OE
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, induding a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
Table 6. Signature Mode Table
Signature Mode
Ao
A9
Cypress Code
VILP
Vpp
0034H
Device Code
VIHP
Vpp
0013H
C') ~
6 5 4 3
0 12
011
0 10
09
08
Vss
Vee
07
Os
Os
04
10
11
12
13
14
15
16
17
0
A13
A12
All
Al.0
As
Vss
Vss
As
A7
As
29
18 19 20 21 2223 24 25 26 27 28
o
C\I
(f)
0
0
,.... 0
w
0
0
Do - DIS
en 0,.... C\I (I') "It
>00< < < < <
Figure 1. Programming Pinout
3-108
As
C270-15
Do - DIS
~
;~
.
--=-,
CY7C270
_ · i l I CYPRESS
SEMICONDUCTOR
'iYpical DC and AC Characteristics
NORMALIZED Icc vs.
tCKACYCLE
1.2
«
E-
1.1
TA ~ 25°C I
Vee=5.5V -
o 1.0
..!:?
0
w
~
o
~
\
:::i O.B
«
\
~
a: 0.7
0
z
~r--
0.6
100
-
300
400
N
~
:::i
0.6
~_--1._
4
1.0
.s
N
~
~
a:
0.9
o
z 0.9
4.0
w
'"
4.5
Tl 1
= 25 c
20 ~ Vee=4.5V
en 15
en
w
()
()
«
TA = 90°C
0
~
w
I
5.5
SUPPLY VOLTAGE
6.0
10
/
5
o
/'
w
N
~
z 0.901-----+----------1
/
o
200
M
400
600
0.B5~------'---------'
- 55
BOO 1000
25
tOEV CHANGE vs. OUTPUT
LOADING
35
30
iii 1.1
..9
o
i-----+-----:::I"c.....---1
Iii
.s
25
>
w
20
~
15
0
10
0
1.0 I----~~----___l
/
/
w
0.91-7'1<...----+---------1
5
o/
o
0'--_ _ _--1._ _ _ _ _- - - '
- 55
25
125
AMBIENT TEMPERATURE (0G)
OUTPUT LOAD (pF)
Iii
~
0.95
a:
o
.s
a:
~
~
o 1.01---.....::::!Io-.d-------1
:::i
NORMALIZED tOEV vs.
TEMPERATURE
W
Vee=5.6V
V
1.2.----------.----------,
N
AMBIENT TEMPERATURE (0G)
NORMALIZED Icc vs.
AMBIENT TEMPERATURE
/v
~
i=
I'"I'--
5.0
6
1.1 ,..------,----------,
25
Iii
w
0.6'--------'---------'
-55
25
125
__'__ _- ' - _ - - - '
4.5
5
5.5
OUTPUT VOLTAGE M
tCKACHANGE
vs. OUTPUT LOADING
w
o~
a:
oz
500
~
"
~ O.B~---_t_-----___l
z
NORMALIZED tCKA
vs. SUPPLY VOLTAGE
()
o 1.0 t----~"------___l
w
~ O.B t-~~--_t_---t--___l
1.2
1.1
~
I---+--~::.....--+--___l
:::i
--
200
()
1.0
ACCESS TIME (ns)
i=
1.4.--------r----------,
w
Vee=4.5V
~
i=
~ 1.2 t----_t_-------::;JI'-___l
w
l1.2
0.9
N
en
en
w
NORMALIZED tCKA
vs. TEMPERATURE
NORMALIZED Icc vs. OUTPUT
VOLTAGE
1.4 .--------.----r----.-------,
125
TEMPERATURE (0G)
400
I I
600 800
OUTPUT LOAD (pF)
3-109
/
Vee = 4.5V TA = 25°C
/'
200
/
-
1000
C270·16
I
~
~~~NDUCTOR
CY7C270
Ordering Information[13]
Speed
(ns)
15
20
30
Ordering Code
Package
Name
Operating
Range
Package 'JYpe
CY7C270-15HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C270-15JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C270-15HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C270-150MB
067
44-Pin Windowed Leadless Chip Carrier
CY7C270-20HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C270-2OJC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C270- 20HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C270-200MB
067
44-Pin Windowed Leadless Chip Carrier
CY7C270-30HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C270-30JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C270-30HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C270- 300MB
067
44-Pin Windowed Leadless Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Commercial
Military
Commercial
Military
Commercial
Military
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
tAS
7, 8, 9, 10, 11
VOL
1,2,3
tAH
7, 8, 9, 10, 11
VIR
1,2,3
tLES
7, 8, 9, 10, 11
VIL
1,2,3
tLEH
7, 8, 9, 10, 11
IIX
1,2,3
tADVS
7, 8, 9, 10, 11
Ioz
1,2,3
tADVH
7, 8, 9, 10, 11
Icc
1,2,3
tDH
7, 8, 9, 10, 11
tCKA
7, 8, 9, 10, 11
tcss
7, 8, 9, 10, 11
tCSH
7, 8, 9, 10, 11
Note:
13. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
tAA
7, 8, 9, 10, 11
tCKB
7,8, 9, 10, 11
tLEA
7, 8, 9, 10, 11
tOEV
7, 8, 9, 10, 11
tLW
7, 8, 9, 10, 11
tASL
7, 8, 9, 10, 11
tCSSL
7, 8, 9, 10, 11
tAHL
7, 8, 9, 10, 11
tCSHL
7, 8, 9, 10, 11
tcsov
7, 8, 9, 10, 11
tLOV
7, 8, 9, 10, 11
tcov
7, 8, 9, 10, 11
Document #: 38-00179-E
3-110
CY7C271
CY7C274
CYPRESS
SEMICONDUCTOR
32K X 8 PROM PowerSwitched and Reprogrammable
Features
Functional Description
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-30 ns (commercial)
- 35 ns (military)
• Lowpower
- 660 mW (commercial)
-715 mW (military)
• Super low standby power
-Less than 165 mWwhen
deselected
• EPROM technology 100%
programmable
• Slim 300-mil pac~ge (7C271)
• Direct replacement for bipolar
PROMs
• Capable of withstanding >2001V
static discharge
The CY7C271 and CY7C274 are highperformance 32,768-word by 8-bit CMOS
PROMs. When disabled (CE HIGH),
the 7C271!7C274 automatically powers
down into a low-power stand-by mode.
The CY7C271 is packaged in the 300-mil
slim package. The CY7C274 is packaged
in the industry standard 600-mil package.
Both the 7C271 and 7C274 are available
in a cerDIP package equipped with an
erasure window to provide for reprogrammability. When exposed to UV light, the
PROM is erased and can be reprogrammed. The memory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY7C271 and CY7C274 offer the advantage of lower power, superior perform-
Pin Configurations
Logic Block Diagram
DIP/Flatpack
07
S
256 x 1024
PROGRAMABLE
ARRAY
ance, and programming yield. The EPROM
cell requires only 12.5V for the super voltage, and low current requirements allow
for gang programming. The EPROM cells
allow each memory location to be tested
100% because each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each PROM is
also tested for AC performance to guarantee that after customer programming,
the product will meet DC and AC specification limits.
Reading the 7C271 is accomplished by
~cing active LOW signals on CSI and
CE, and an active HIGH on CS2. Reading
the 7C274 is accomplished by placing active LOW signals on OE and CE. The
contents of the memory location addressed by the address lines (Ao - A14)
will become available on the output lines
(00 - 07)·
Vee
Vee
As
A7
AlO
Al1
A12
A13
A14
A14
A13
As
06
8x10F128
MULTIPLEXER
DIP/Flatpack
Ag
As
Os
04
03
As
As
~
A3
A2
CS1
A1
CE
Ao
07
06
All
CS2
00
01
Os
04
03
02
GND
A3
A2
Al
OE
Ao
07
06
A10
CE
Os
04
03
O2
GND
C271-2
LCCIPLCC (Opaque Only)
02
01
00
CE--o.--..r-...,..
(7C271) CS1
(7C271) CS2
(7C274)
m:
.t:':~?~~
4 3 2 c1,3231 30
29
5
28
7C271
6
27
7
26
B- 25
9
24
10
23
11
22
12
21
13
14151617181920
-0--
-"""'1..._"'/
,... C\lOt)
C271-1
C271-4
LCCIPLCC (Opaque Only)
C")
<£!J:~?~.f
4 3 2 c1,323130
A12
A13
A14
NC
CS1
CS2
IT
07
06
vLO
oozzooo
Cl
As
As
~
As
A2
Al
Ao
NC
00
29
5
28
7C274
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617181920
0
..- NOO
C271-3
00
('I')
Maximum Access Time (ns)
Maximum Operating Com'l
Current (rnA)
Military
Standby Current (rnA) Com'l
Military
30
7C271-35
7C274-35
35
120
130
30
40
3-111
7C271-45
7C274-45
45
120
130
30
40
A10
07
06
C271-5
Selection Guide
7C271-30
7C274-30
30
120
m:
IT
~U.)
zzooo
Cl
Ag
As
A11
NC
7C271-55
7C274-55
55
120
130
30
40
•
en
::IE
o0:
a..
CY7C271
CY7C274
~
~.~
~iE CYPRESS
~.F SElv1ICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - O.sV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.sV to +7.0V
DC Input Voltage. . . . . . . . . . . . . . . . . . . . .. - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
UV Exposure ........................... 7258 Wsec/cm2
Operating Range
Ambient
Temperature
Vee
O°Cto +70°C
5V ±10%
Industrial[l]
- 40°C to +85°C
5V ±10%
Military[2]
-55°Cto +125°C
5V ±1O%
Range
. Commercial
Electrical Characteristics Over the Operating Range[3]
7C271-30, 35, 45, 55
7C274-30, 35, 45, 55
Description
Parameter
Min.
Test Conditions
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA[4]
VIR
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for
All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs
IIX
Input Current
GND.s VIN.s Vee
Ioz
Output Leakage Current
GND .s V OUT.s Vee, Output Disabled
los
Output Short Circuit Currentl5]
Vee = Max., VOUT = GND
Icc
Power Supply Current
ISB
Standby Supply Current
VOH
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIRP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
Max.
Unit
2.4
V
0.4
V
Vee
V
0.8
V
-10
+10
-40
+40
!lA
!lA
-20
2.0
-90
rnA
Vee = Max., VIN = 2.0V,
lOUT = 0 rnA, CE=VIL
Commercial
120
rnA
Military
130
Vee = Max., CE = VIR,
lOUT = ornA
Commercial
30
Military
40
12
rnA
13
V
SO
rnA
V
3.0
0.4
V
Capacitance[6]
Parameter
CrN
COUT
Description
Input Capacitance
Uutput CapacItance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Max.
10
10
Unit
pF
pF
Notes:
Contact a Cypress representative for information on industrial temperature range specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
1.
4.
5.
6.
3-112
6.0 rnA military
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
See Introduction to CMOS PROMs in this Data Book for general information on testing.
=;;;:::::..
-~
~ ill CYPRESS
CY7C271
CY7C274
====~.$' SEMICONDUCTOR
AC Test Loads and Waveforms[6]
R1 5000
OUTP~~31658Q
MIL
PI
30 F
INCLUDING _
JIG AND SCOPE
R1 5000
OUTP~~316580
MIL
PI,
R2 3330
5 F
(4030 MIL).
_
INCLUDING _
JIG AND SCOPE
(a) Normal Load
ALL INPUT PULSES
3.0V
GND
R2 3330
(4030 MIL)
_
-
C271-7
C271-6
en
0
a:
D.
THEVENIN EQUIVALENT
Equivalent to:
2000
OUTPUT Q.O---"""H'I.----oO 2.00V COMMERCIAL
2500
A'"
OUTPUToo.--~~--~
o
1.90V MILITARY
C271-8
Switching Characteristics Over the Operating Rangd 3, 6]
7C271-30
7C274-30
Parameter
Description
Min.
7C271-35
7C274-35
Max. Min.
Max.
7C271-45
7C274-45
Min.
7C271-55
7C274-55
Max. Min.
Max.
Unit
tAA
Address to Output Valid
30
35
45
55
ns
tHZCS
Chip Select Inactive to High Z (CSl and CS2, 7C271
Only)
20
25
30
30
ns
tACS
Chip Select Active to Output Valid (CSl and CS2,
7C271 Only)
20
25
30
30
ns
tHZOE
Output Enable Inactive to High Z (DE, 7C274 Only)
20
20
25
25
ns
tOE
Output Enable Active to Output Valid (OE, 7C274
Only)
20
20
25
25
ns
tHzCE
Chip Enable Inactive to High Z (CE Only)
35
40
50
60
ns
tACE
Chip Enable Active to Output Valid (CE Only)
35
40
50
60
ns
tpu
Chip Enable Active to Power Up
tpD
Chip Enable Inactive to Power Down
tOH
Output Hold from Address Change
0
0
0
40
0
0
50
0
ns
60
0
ns
ns
~
-
-
POWER-DOWN CONTROLLED BY CE
SUPPLY
CURRENT
Ao -
0
35
~
Switching Waveform
Vee __________________________
50%
A14
ADDRESS __________1
DE, CE, CSCS.2
[7J
•
:E
(b) High Z Load
_ _ _ _ _ _ _-+-_________
1
(tOE)
tACS(E)
HIGHZ
C271-9
Note:
7. CS2andCSl are used on the7C271 only. OE is used on the7C274 only.
3-113
CY7C271
CY7C274
~
-
.. ~
~=CYPRESS
_ , SEMICONDUCTOR
lamp during erasure. Permanent damage may result if the PROM
is exposed to high-intensity UV light for an extended period of
time. 7258 Wsec/cm2 is the recommended maximum dosage.
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase the
7C271 and 7C274 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM is
exposed to sunlight or fluorescent lighting for extended periods
of time.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity X
exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12
m W/cm 2 power rating, the exposure time would be approximately
35 minutes. The 7C271 or 7C274 needs to be within 1 inch of the
Table 1. CY7C271 Mode Selection
Pin Function[8]
Read or Output Disable
Mode
Other
A14 A14 -
Read
A14 -
Power Down
A14 -
Output Disable
A14 -
Output Disable
A14 -
Program
A14 -
Program Verify
A14 -
Program Inhibit
A14 -
Blank Check
A14 -
Ao
Ao
An
An
An
An
An
An
An
An
CE
CS2
CSI
VFY
PGM
Vpp
D7 - Do
VIL
VIH
VIL
07 - 00
VIH
X
X
HighZ
X
VIL
X
HighZ
X
X
VIH
HighZ
VIHP
VILP
Vpp
D7 - Do
VILP
VIHPNILP
Vpp
07- 00
VIHP
VIHP
Vpp
HighZ
VILP
VIHPNILP
Vpp
07 - 00
Vpp
07 - 00
07 - 00
Table 2. CY7C274 Mode Selection
Pin Function[8]
Read or Output Disable
Mode
Other
A14 A14 -
Read
A14 -
Output Disable
A14 -
Power Down
A14 -
Program
A14 -
Program Verify
A14 -
Program Inhibit
A14 -
Blank Check
A14 -
Notes:
8. X can be VIL (VILP) or VIH (VIHP).
Ao
Ao
An
An
An
An
An
An'
An
OE
CE
VFY
PGM
Vpp
D7 - Do
VIL
VIL
Note 9
07 - 00
VIH
X
X
HighZ
X
VIH
X
HighZ
VIHP
VILP
Vpp
D7- D O
VILP
VIHPNILP
Vpp
07 - 00
VIHP
VIHP
Vpp
HighZ
VILP
VIHPNILP
Vpp
07 - 00
9.
3-114
Vpp should be tied to Vee ±S% in read mode.
==:
CY7C271
CY7C274
:~
'iii CYPRESS
_ , SEMICONDUcrOR
Lee
DIP
Top View
As
Top View
As
Vee
A10
A7
A11
As
A12
A 13
A14
Vpp
As
At.
~.f~~J3~..t
As
As
At.
A3
A2
A1
A3
A2
A1
J5GM
VFY
NC
Ao
07
00
01
O2
GNO
06
Os
04
00
Ao
5
6
7
8
9
10
11
12
7C271
0
A12
A13
A14
NC
Vpp
J5GM
'VFY
07
06
o8'~~8d'~
C271-11
03
C271-10
Lee
DIP
Top View
vpp
A12
A7
As
Top View
As
As
As
At.
A11
A3
A2
A1
A10
Ao
00
01
02
GNO
",~t)"'M
vee
A14
A 13
~<~::9«
As
As
At.
A3
A2
A1
'VFY
Ao
J5GM
NC
07
06
Os
04
00
432,-1,323130
29
5
6
7C274
7
0
8
9
10
11
12
21
13
14151617181920
As
As
A11
NC
VFY
A10
J5GM
07
06
o8'~~8d'~
03
C271-13
C271-12
Figure 1. Programming Pinouts
3-115
•
In
::e
oa:
Q.
CY7C271
CY7C274
#f ::~
=
55!!!i!!!IIr
~,
CYPRESS
SEMICONDUcrOR
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6,.------r---,------,r-----,
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.2
w
::E
i=
~ 1.0
w
~ 1.1
Cl
W
N
Cl
w
()
N
:J
«
S:i
Cl
::i 1.0
«
:'i!
a:
0.8
w
::E
oz
- --- r---
r----
N
II:
::i
0
z 0.9
~ 0.6
II:
4.5
5.0
6.0
5.5
SUPPLY VOLTAGE
M
NORMALIZED ACCESS TIME
vs. TEMPERATURE
w
0.8 L--_ _ _...L..._ _ _ _ _.....J
-55
25
125
AMBIENT TEMPERATURE (0C)
l
1.6
§
w
N
:J
«
40
()
1.2
1.0
"'"
II:
~ 30
-
Cl
~
:::>
~ 20
5a..
0.6
- 55
10
~
:::>
25
125
o
0
o
1.0
« 175
S
I-
2.0
3.0
OUTPUT VOLTAGE
AMBIENT TEMPERATURE (0C)
1.0
~
~
75
50
I-
5
J.
20
Cl
V~
10
V
/
I/
'"
4.0
V
L
Vee = 4.5V
TA = 25°C
I
200
/
400
600
I
800 1000
CAPACITANCE (pF)
NORMALIZED SUPPLY CURRENT
vs. CYCLE PERIOD
tl
II:
5a..
30
1.1
5 100
z
6.0
M
150
~ 125
CiS
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
z
~
Cii"
~
w
'-...~
I-
z
5.5
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
.s
"-
II:
:'i!
a: 0.8
0
5.0
40
w
«
I
4.5
SUPPLY VOLTAGE
60
!zw 50 I'\.
()
()
TA = 25°C
0.4
4.0
OUTPUT SOURCE CURRENT
vs.VOLTAGE
:'i!
i=
en 1.4
en
oZ
/
/1,1'
o/
0.0
1.0
::i
«
I
2.0
3.0
OUTPUT VOLTAGE
Cl 0.9
w
N
Vee = 5.0V
TA = 25°C -
25
..9
4.0
M
::E 0.8
II:
0
z
0.7
0.6 0
\\
~
"50
~
100
. . . r-..150
200
250
CYCLE PERIOD (ns)
C271-14
3-116
CY7C271
CY7C274
~
-.~
-:=,- . CYPRESS
SEMICONDUCTOR
Ordering Information[lOJ
Speed
(ns)
30
35
45
55
Ordering Code
Package
Name
Package 'JYpe
CY7C271-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C271-30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C271-30WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C271-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C271- 35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C271-35WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C271- 35DMB
D22
28-Lead (300-Mil) CerDIP
CY7C271-35KMB
K74
28-Lead Rectangular Cerpack
CY7C271- 35LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C271-350MB
055
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C271- 35WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C271-45JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C271-45PC
P21
28-Lead (300-Mil) Molded DIP
CY7C271-45WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C271-45DMB
D22
28-Lead (300-Mil) CerDIP
CY7C271-45KMB
K74
28-Lead Rectangular Cerpack
CY7C271-45LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C271-450MB
055
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C271-45TMB
T74
28-Lead Windowed Cerpack
CY7C271-45WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C271-55JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C271-55PC
P21
28-Lead (300-Mil) Molded DIP
CY7C271-55WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C271-55DMB
D22
28-Lead (300-Mil) CerDIP
CY7C271-55KMB
K74
28-Lead Rectangular Cerpack
CY7C271-55LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C271-550MB
055
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C271-55TMB
T74
28-Lead Windowed Cerpack
CY7C271-55WMB
W22
28-Lead (300-Mil) Windowed CerDIP
Note:
10. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-117
Operating
Range
Commercial
Commercial
•
en
::E
Military
oa::
Q.
Commercial
Military
Commercial
Military
CY7C271
CY7C274
~
~~NDUcroR
Z
Ordering Information(10] (continued)
Speed
(ns)
30
35
45
55
Ordering Code
Package
Name
Package lYPe
CY7C274-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C274-30PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C274-30WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY7C274-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C274-35PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C274-35WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY7C274-35DMB
DI6
28-Lead (600-Mil) CerDIP
CY7C274-35KMB
K74
28-Lead Rectangular Cerpack
CY7C274-35LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C274-35QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C274-35TMB
T74
28-Lead Windowed Cerpack
CY7C274-35WMB
WI6
28-Lead (600-Mil) Windowed CerDIP
CY7C274-45JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C274-45PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C274-45WC
W16
28-Lead (600-Mil) Windowed CerDIP
CY7C274-45DMB
DI6
28-Lead (600-Mil) CerDIP
CY7C274-45KMB
K74
28-Lead Rectangular Cerpack
CY7C274-45LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C274-45QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C274-45TMB
T74
28-Lead Windowed Cerpack
CY7C274-45WMB
WI6
28-Lead (600-Mil) Windowed CerDIP
CY7C274-55JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C274-55PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C274-55WC
WI6
28-Lead (600-Mil) Windowed CerDIP
CY7C274-55DMB
DI6
28-Lead (600-Mil) CerDIP
CY7C274-55KMB
K74
28-Lead Rectangular Cerpack
CY7C274-55LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C274-55QMB
Q55
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C274-55TMB
T74
28-Lead Windowed Cerpack
CY7C274-55WMB
WI6
28-Lead (600-Mil) Windowed CerDIP
3-118
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Commercial
Military
-
-.
CY7C271
CY7C274
:~
-=-,
~iE CYPRESS
SEMICONDUcrOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
IIX
Ioz
Icc
ISB
1,2,3
1,2,3
II
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
7,8,9, 10, 11
tACSl[ll]
7, 8, 9, 10, 11
tOE[12]
7,8,9, 10, 11
tACE
7, 8, 9, 10, 11
Notes:
11. 7C274 and 7C271 (CS2, CS3 and CS4 only).
12. 7C271 only.
SMD Cross Reference
SMD
Number
SUff'1X
Cypress
Number
5962-89817
01XX
5962-89817
OlYX
CY7C271-55WMB
CY7C271-55TMB
5962-89817
01ZX
CY7C271-55QMB
5962-89817
02XX
CY7C271-45WMB
5962-89817
02YX
CY7C271-45TMB
5962-89817
02ZX
CY7C271-45QMB
Document #: 38-00068-G
3-119
CY7C276
CYPRESS
SEMICONDUCTOR
16Kx 16
Reprogrammable PROM
Features
• 100% reprogrammable in windowed
• 0.8-micron CMOS for optimum speed!
power
• High speed (for commercial and
military)
packages
• TTL-compatible I/O
• Capable of withstanding greater than
2001V static discharge
•
•
•
•
- 25-ns access time
Functional Description
16-bit-wide words
Three programmable chip selects
Programmable output enable
44-pin PLCC and 44-pin LCC
packages
The CY7C276 is a high-performance 16Kword by 16-bit CMOS PROM. It is available in a 44-pin PLCC/CLCC and a 44-pin
LCC packages, and is 100% reprogrammabIe in windowed packages. The memory
cells utilize proven EPROM floating gate
technology and word-wide programming
algorithms.
Logic Block Diagram
The CY7C276 allows the user to independently program the polarity of each chip
select (CS2-CSO). This provides on-chip
decoding of up to eight banks of PROM.
The polarity of the asynchronous output
enable pin (OE) is also programmable.
In order to read the CY7C276, all three
chip selects must be active and OE must be
asserted. The contents of the memory location addressed by the address lines (A13 Ao) will become available on the output
lines (DIS - Do). The data will remain on
the outputs until the address changes or
the outputs are disabled.
Pin Configuration
LCC/PLCC/CLCC
Top View
16Kx 16
PROGRAMMABLE 1 - - - - - - - - - - ,
ARRAY
5J5~~JlJ3Jl ~~13
6 5 4 3
012
0 11
A13
A12
010
Os
08
Vss
Vee
07
Os
Os
04
All
10
11
12
13
14
15
16
AlO
As
0
Vss
Vss
As
A7
As
As
0
C\I,....
('I)
o
0
0
0
w en
0
0,.... C\I
(I)
q-
>cn« « « « «
C276·2
CS
DECODE
D1
Do
OE-------I
C276·1
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
I Commercial
r Military
3-120
CY7C276-25
CY7C276-30
CY7C276-35
25
175
30
175
35
175
200
200
200
.~
-=::::::1=
--===,
·
CY7C276
CYPRESS
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .... . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
UV Erasure ............................. 7258 Wsec/cm2
Operating Range
Range
Commercial
Industria}[l]
Military[2]
Ambient
Temperature
Vee
O°Cto +70°C
5V ±10%
- 40°C to +85°C
5V ±10%
- 55°C to +125°C
5V ±10%
CY7C276-25
CY7C276-30
CY7C276-35
Description
Test Conditions
Min.
2.4
Output LOW Voltage
= Min., IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA (6.0 rnA Mil)
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
IIX
Input Leakage Current
VeD
Input Clamp Diode Voltage
loz
VOH
Output HIGH Voltage
VOL
Vee
Unit
Max.
V
0.4
V
V
- 3.0
Vee
0.8
GND ~ VIN ~ Vee
-10
+10
ftA
Output Leakage Current
Vee = Max., VOL~ VOUT ~ VOH,
Output Disabled
- 40
+40
los
Output Short Circuit Current
Vee
- 20
lee
Power Supply Current
Vee
V
ftA
ftA
Note 3
= Max., VOUT = O.OVl:J J
= Max., lOUT = 0.0 rnA
- 90
rnA
I Com'l
175
rnA
JMilitary
200
rnA
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f
Vee = 5.0V
Input Capacitance
CIN
C OUT
Output Capacitance
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature
3. See Introduction to CMOS PROMs in this Data Book for general information on testing.
4.
= 1 MHz,
Max.
Unit
10
pF
10
pF
See the last page ofthis specification for Group A subgroup testing information.
5. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
AC Test Loads and Waveforms
R1500n
R1500n
5V § = t ( 6 5 s
Mil)
n
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
J
ALL INPUT PULSES
3.0V----
5V T I ( 6 5 sMil)
n
R2
OUTPUT
333rl
(403rl
5 pF
Mil)
INCLUDING
JIG AND
SCOPE
_
(a) Normal Load
J
_
90%
R2
333rl
(403rl
Mil)
GND
- C276-3
(b) High Z Load
C276-4
I
Equivalent to: THEVENIN EQUIVALENT
200n (250n Mil)
OUTPUT
2.0V (1 .9V Mil)
o-------wv----o
tn
:::E
oa:
0..
Electrical Characteristics[3,4]
Parameter
II
C276-5
3-121
~~
~=CYPRESS
CY7C276
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel3,4]
CY7C276-25
Parameter
Description
Max.
Min.
CY7C276-30
Min.
Max.
CY7C276-35
Min.
Max.
Unit
tAA
Address to Output Data Valid
25
30
35
ns
tcsov
CS Active to Output Valid
13
15
18
ns
tcsoz
CS Inactive to High Z Output
13
15
18
ns
tOEV
OE Active to Output Valid
11
12
15
ns
tOEZ
OE Inactive to High Z Output
11
12
15
ns
Erasure Characteristics
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm 2. For an ultraviolet lamp
with a 12 mW/cm 2 power rating the exposure time would be approximately 35 minutes. The 7C276 needs to be within 1 inch of the
lamp during erasure. Permanent damage may result if the
EPROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm 2 is the recommended maximum
dosage.
Wavelengths of light less than 4000 Angstroms begin to erase the
7C276 in the windowed package. For this reason, an opaque label
should be placed over the window if the EPROM is exposed to sunlight or fluorescent lighting for extended periods of time.
Switching Waveforms
Read Operation Timing Diagram[6]
XXXX
1=
tM
=1
~-:~--
ADDRA
__
XXXXXXXXD<....-o-AT-AA----~X~X~X~~O_AT_AB
C276-6
Chip Select and Output Enable Timing Diagrams
CS2 -CSo INACTIVE
ACTIVE HIGH
OE
015 -
Do
C276-7
Notes:
6. CS2 - CSo, OE assumed active.
3-122
---..'=
--=-,
~
CY7C276
CYPRESS
SEMICONDUCTOR
Architecture Configuration Bits
Programming Information
The CY7C276 has four user-programmable options in addition to Programming support is available from Cypress as well as from a
the reprogrammable data array. For detailed programming infor- number of third-party software vendors. For detailed programmation contact your local Cypress representative.
ming information, induding a listing of software packages, please
The programmable options determine the active polarity for the three see the PROM Programming Information located at the end of this
chip selects (CSz - CSo) and OE. When these control bits are pro- section. Programming algorithms can be obtained from any Cygrammed with a 0 the inputs are active Ww. When these control bits press representative.
are programmed with a 1 the inputs are active HIGH.
Table 1. Control Word for Architecture Configuration
:e
o
Function
Control Option
Bit
OE
Do
O=Default
1 = Programmed
OE Active LOW
OE Active HIGH
CSo
D12
O=Default
1 = Programmed
CSo Active LOW
CSo Active HIGH
CSl
D13
O=Default
1 = Programmed
CSl Active LOW
CSl Active HIGH
CSz
Dl4
O=Default
1 = Programmed
CSz Active LOW
CSz Active HIGH
Programmed Level
a:
a..
Table 2. Program Mode Table
BitMap
Programmer Address (Hex)
0000
Vpp
PGM
VFY
Do - DIS
Program Inhibit
Vpp
VIHP
VIHP
HighZ
Program Enable
Vpp
VILP
VIHP
Data
Program Verify
Vpp
VIHP
VILP
Data
Mode
RAM Data
Data
3FFF
Data
4000
Control Word
Control Word (4000H)
D~
Do
XCSz CSlCSOXXXXXXXX 1 XXOE
Table 3. Configuration Mode Table
Vpp
PGM
VFY
A2
Program Inhibit
Vpp
VIHP
VIHP
Vpp
HighZ
Program Control Word
Vpp
VILP
VIHP
Vpp
Control Word
Verify Control Word
Vpp
VIHP
VILP
Vpp
Control Word
Mode
D12
D11
D10
Dg
D8
Vss
Vee
D7
D6
D5
D4
6 5 4 3 2,1, 44 43 42 41 40
39
9
10
11
12
13
14
15
16
17
CY7C276
o
29
18 192021 222324 25 26 27 28
A13
A12
A11
A10
Ag
Vss
Vss
As
A5
C276·8
Figure 1. Programming Pinout
3-123
•
II)
Control Word
Do - DIS
:~PRE.§
----.
~IF
CY7C276
SEMICONDUCTOR
'lYpical DC and AC Characteristics
NORMALIZED Icc vs.
tCKACYCLE
1.4
1.2
<{ 1.1
.s
t)
I
..9
Cl
w
«
::2
\
a: 0.7
0
'I--
0.6
100
·w
::2.
i=
~
o
en
ffi
1.0
~
z
oz
::J
0.6
400
4.5
5
5.5
OUTPUT VOLTAGE (V)
1.2
~
Cl
w
1.0
..s
"~
N
::J
~ 0.9
a:
w
en 15
en
w
~ '-TA = 90°C
0
0
«
10
w
~
5
4.5
5.0
5.5
/
0
I
z 0.9
4.0
AMBIENT TEMPERATURE (0C)
NORMALIZED Icc vs.
AMBIENT TEMPERATURE
1.1...-------.--------,
T~ = 2S!C
20 r-- Vee=4.5V
6.0
o
.s 1.05
/'
~
o
L
200
SUPPLY VOLTAGE (V)
1.0'1------+-------'~---1
W
N
::J
~ 0.95
a:
o
z 0.90'1------+----------1
/
o
Vee=5.6V
<{
/
::2
i=
o
0.8 ~----r-----~
0~5~5-----~2~5--------~1~25
6
25
Cil
w
1.0 1-----2"~----~
tCKACHANGE
vs. OUTPUT LOADING
w
o
a:
L . . - _ - - - L . . _ - , - L ._ _- ' - _ - - - I
4
500
::2
1.1
~
r---
NORMALIZED tCKA
vs. SUPPLY VOLTAGE
CJ)
CJ)
w
N
ACCESS TIME (ns)
i=
~
o
1---+--2"''--+--~
~ 0.8 1--2fI'4---+---+--~
300
1.21---'--r----~~~
o
::J
--
200
r----.---~--.__-__,
.s 1.2
-
~
\
::J 0.8
z
I
0.9
N
1.4 , - - - - - - - . - - - - - - - - - ,
<{
TA = 25°C
Vee=5.5V
1.0
NORMALIZED tcKA
vs. TEMPERATURE
NORMALIZED Icc vs. OUTPUT
VOLTAGE
400
600
0.85'----------'-----------...J
- 55
25
125
800 1000
AMBIENT TEMPERATURE (0C)
OUTPUT LOAD (pF)
NORMALIZED toEV vs.
TEMPERATURE
tOEV CHANGE vs. OUTPUT
LOADING
1.2 r------.------__,
35
30
(;j
..9
w
1.11-----+----7'~~
25
o
~
«
::2
a:
~
1.0 I----~~----~
(;j
o
20
~
15
o
10
/
/
w
0.91-7"~---+-----~
o1/
o
- 55
25
125
TEMPERATURE (0C)
200
400
I I
600 800
OUTPUT LOAD (pF)
3-124
/
Vee = 4.5V TA = 25°C
/~
5
OL..-_ _ _---L.._ _ _ _ _---I
/"
-
1000
C276-9
~-'.~
=====
-==r'
CY7C276
1= CYPRESS
SEMICONDUCTOR
Ordering Information[7]
Speed
Ordering Code
(ns)
25
30
35
Package
Name
Package 'JYpe
CY7C276-25HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-25JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C276-25HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276- 250MB
067
44-Pin Windowed Leadless Chip Carrier
CY7C276-30HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-3OJC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C276-30HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-300MB
067
44-Pin Windowed Leadless Chip Carrier
CY7C276-35HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-35JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C276-35HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276- 350MB
067
44-Pin Windowed Leadless Chip Carrier
Note:
7.
Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
Ilx
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Ioz
Icc
Switching Characteristics
Parameter
Subgroups
tAA
7, 8, 9, 10, 11
tcsov
tOEV
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Document #: 38-00183-D
3-125
Operating
Range
Commercial
Military
Commercial
•
II)
::e
Military
Commercial
Military
o
a:
Q.
CY7C277
CYPRESS
SEMICONDUCTOR
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
- 30-ns max. set-up
-IS-ns clock to output
• Lowpower
-660 mW (commercial)
-715 mW (military)
Reprogrammable 32K X 8
.. Registered PROM
• Programmable address latch enable
input
• Programmable synchronous or
asynchronous .output enable
• On-chip edge~triggered output
registers
• EPROM technology, 100%
programmable
• Slim 300-mil, 28-pin plastic or
hermetic DIP
Logic Block Diagram
• 5V ±10% Vcc, commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
2001V static discharge
Pin Configurations
DIP/Flatpack
Top View
07
ADDRESS
256 x 1024
PROGRAMMABLE
ARRAY
06
05
8-BIT
EDGETRIGGERED
REGISTER
15-BIT
ADDRESS
TRANSPARENTI
LATCH
VCC
A7
All
As
A12
Al0
A5
04
A13
~
03
As
A14
ALE
A2
CP
E/Es
Al
02
Ao
01
~~~~~~============~
1 OF 32
As
As
00
CP
07
00
06
01
05
02
04
GND
03
C277-2
LCCIPLCC (Opaque Only)
Top View
ALE
E~s-----l==rs::::~~j:;;;;;;'~I~~--~
.t~~~~.f~
CP~;- .. ~~~____~
As
A5
~
A3
Ag
Al
C277-1
Ao
NC
00
5
6
7
8
9
10
11
12
13
14151617181920
0
o 6"~~6'otcf
Cl
A12
A13
A14
NC
ALE
CP
E~s
07
06
C277-3
Selection Guides
7C277-30
7C277-40
7C277-S0
Maximum Setup Time (ns)
30
40
50
Maximum Clock to Output (ns)
15
20
25
120
120
120
130
130
Maximum 0serating
Current (rnA
I Com'l
I Mil
3-126
~
.
;~PRESS
CY7C277
""=' JF SEMICONDUCTOR
Functional Description
The CY7C277 is a high-performance 32K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package. The
ceramic package may be equipped with an erasure window; when
exposed to UV light, the PROM is erased and can then be
reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide algorithms.
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.SV for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for
each memory location to be 100% tested, as each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee
that the product will meet DC and AC specification limits after
customer programming.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 6SoC to + lS0°C
Ambient Temperature with
Power Applied ...................... - S5°C to + 12SoC
Supply Voltage to Ground Potential. . . . . .. - O.SV to + 7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ................ 13.0V
UV Erasure ............................. 72S8 Wsec/cm2
On the 7C277, the outputs are pipelined through a master-slave
register. On the rising edge ofCp, data is loaded into the 8-bit edge
triggered output register. The E!Es input provides a programmable bit to select between asynchronous and synchronous
operation. The default condition is asynchronous. When the
asynchronous mode is selected, the E!Es pin operates as an
asynchronous output enable. If the synchronous mode is selected,
the E!Es pin is sampled on the rising edge of CP to enable and
disable the outputs. The 7C277 also provides a programmable bit •
to enable the Address Latch input. If this bit is not programmed,
the device will ignore the ALE pin and the address will enter the
device asynchronously. If the ALE function is selected, the address CI)
enters the PROM while the ALE pin is active, and is captured ::E
when ALE is deasserted. The user may define the polarity of the 0
ALE signal, with the default being active HIGH.
f
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 301S)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Range
Commercial
O°C to +70°C
Vee
SV ±1O%
Industrial[l]
- 40°C to +8SoC
SV ±1O%
Military[2]
- SSoC to + 12SoC
SV ±1O%
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
Electrical Characteristics Over the Operating Rangef3,4]
7C277-30
Parameter
Description
Test Conditions
Min. Max.
7C277 -40, 50
Min.
Max.
Unit
0.4
V
Vee
V
0.8
V
+10
fAA
= Min., IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
2.4
Input HIGH Level
GuarallteedlnputLogicalHIGHVoltage
for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
IIX
Input Leakage Current
GND~VIN~Vee
VeD
Input Clamp Diode Voltage
loz
Output Leakage Current
o~ VOUT ~ Vee, Output Disabled[5]
-40
+40
-40
+40
fAA
los
Output Short Circuit Current
Vee
-20
-90
-20
-90
rnA
Icc
Power Supply Current
= Max., VOUT = 0.OV[6]
Vee = Max., CS~ VIH I Commercial
lOUT = ornA
120
rnA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Vee
2.4
0.4
Vee
2.0
0.8
-10
+10
-10
Note 4
120
I Military
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
V
130
12
13
12
SO
3.0
V
rnA
3.0
0.4
3-127
13
SO
V
0.4
V
ii=~
CYPRESS
§Ii
=r
CY7C277
_ , SEMICONDUcrOR
Capacitance[4]
Parameter
Test Conditions
Description
CIN
Input Capacitance
COUT
Output Capacitance
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
10
pF
10
pF
AC Test Loads and Waveforms[4]
R1500n
R1500n
(658.0. MIL)
(658.0. MIL)
5V
5V
OUTPUTo----.----t
30
FI
P
INCLUDING
JIGAND _
SCOPE -
R2
333.0.
(403D. MIL)
(a) Normal Load
Equivalent to:
ALL INPUT PULSES
OUTPUTo---......- - - t
5PFI
INCLUDING
JIGAND _
SCOPE -
C277-4
3.0V ----_JI""~----~
R2
333.0.
(403D. MIL)
(b) High Z Load
GND
C277-6
C277-5
THEvENIN EQUIVALENT
250n
OUTPUT 0.0----'1
..",
..•........- - 0 0 1.9V
200n
OUTPUT OO----'l·.N
...........--OO 2.0V
Military
Commercial
C277-7
Notes:
3.
4.
See the last page of this specification for Group A subgroup testing information.
See "Introduction to CMOS PROMs" in this Book for general information on testing.
5.
6.
For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
CY7C277 Switching Characteristics Over the Operating Rangd 3,4]
7C277-30
Parameter
Description
Min.
Max.
7C277-40
Min.
Max.
7C277-50
Min.
Max.
Address Set-Up to ALE Inactive
5
10
10
ns
tLA
Address Hold from ALE Inactive
10
10
15
ns
tLL
ALE Pulse Width
10
10
15
ns
tSA
Address Set-Up to Clock HIGH
30
40
50
ns
tHA
Address Hold from Clock HIGH
0
0
0
ns
tSES
Es Set-Up to Clock HIGH
12
15
15
ns
tHES
Es Hold from Clock HIGH
5
10
10
teo
Clock HIGH to Output Valid
tpwe
Clock Pulse Width
tLzd 7]
Output Valid from Clock HIGH
15
20
30
tHzC
Output High Z from Clock HIGH
15
20
30
ns
tLZE[8]
Output Valid from E LOW
15
20
30
ns
tHZE[8]
Output High Z from E HIGH
15
20
30
ns
20
15
15
20
ns
25
Applies only when the synchronous (ES) function is used.
8.
3-128
ns
ns
20
Notes:
7.
Unit
tAL
Applies only when the asynchronous (E) function is used.
ns
.~
CYPRESS
==p=.
CY7C277
~iE
JF
SEMICONDUCTOR
Architecture Configuration Bits
Architecture
Bit
ALE
Dl
ALEP
D2
E/Es
Do
Architecture Verify
D7 - Do
a = DEFAULT
1 = PGMED
0= DEFAULT
1 = PGMED
a = DEFAULT
1 = PGMED
Function
Input Transparent
Input Latched
ALE = Active HIGH
ALE = Active LOW
Asynchronous Output Enable (E)
Synchronous Output Enable (Es)
•
(I)
:IE
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
7FFF
8000
Data
Control Byte
oa:
Architecture Byte (8000)
Q.
D7
Do
C7 C6 C5 C4 C3 C2 Cl Co
Timing Diagram (Input Latched) [9]
ALE
ES
(SYNC H)
CP
0
0
-
0
7
----"
t_HZ~~_tU_E
Es ___________________________________________________
_ __
(ASYNCH)
C277-8
Timing Diagram (Input Transparent)
Ao -
A14
-----'
ES
(SYNCH)
CP
00
-
07
------'
Es
~SYNCH)
-------------------------'
C277-9
Note:
9. ALE is shown with positive polarity.
3-129
rr ,-:~PRESS
SEMICONDUcrOR
CY7C277
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programminginformation, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[lO]
Read or Output Disable
Mode
Other
A14 A14 -
Read
A14 -
Output Disable
A14 -
Program
A14 -
Program Verify
A14 -
Program Inhibit
A14 -
Blank Check
A14 -
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
E,Es
CP
ALE
07- 0 0
VFY
PGM
Vpp
D7- Do
07- 00
VIL
VIH
VIL
VIH
X
X
HighZ
VIHP
VILP
Vpp
D7- D O
VILP
VIHPNILP
Vpp
07- 00
VIHP
VIHP
Vpp
HighZ
VIHPNILP
Vpp
07- 00
VILP
Note:
10. X = "don't care" but not to exceed Vee ±S%.
Lee/PLee (Opaque Only)
DIP
Top View
Top View
~
~
~
As
~~
NC
~
Ao
'VF'Y
NC
Do
D7
D6
C277-10
Figure 1. Programming Pinouts
3-130
Ag
Ag
Au
•
to
~~PRESS
CY7C277
- . ' SEMICONDUCTOR
lYpical DC and AC Characteristics
NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
VS. SUPPLY VOLTAGE
1.6
1.2
w
1.2
~
i=
u1.4
...!:?
0
w
N
~
1.2
/v
-
~
~
o
~ 10.0
l-
0.6
-55
/
,,/
I-
z
25
125
o=>
0
o
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (0C)
25
o
o
/'
~
/V
1/
0.0
1.0
Vee = 5.0V
TA = 25°C -
I
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
C277-12
3-131
6.0
/
/
~
10
5.5
20.0
~
..... 15.0
@ 20
ir
5.0
TYPICAL ACCESS TIME CHANGE
VS. OUTPUT LOADING
a:
w
CJ) 1.2
I
4.5
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vS.VOLTAGE
~
f-!.
0.4
4.0
AMBIENT TEMPERATURE (0C)
w
=>
TA = 25°C
Z
0.8 L...-_ _ _...L...._ _ _ _ _....l
-55
25
125
NORMALIZED SET-UP TIME
VS. TEMPERATURE
i= 1.4
Il..
0.6
0
SUPPLY VOLTAGE (V)
N
~
a:
f = fMAX
5.0
-
1.0
w
a:
V
4.5
CJ)
CJ)
1.1 1 - - - - 4 - - - - - - - - 1
•
-.-
-~
CY7C277
_·=CYPRESS
~, SEMICONDUCTOR
Ordering Information[ll]
Speed
(ns)
30
40
50
Ordering Code
Package
Name
Package 'fYpe
CY7C277-30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C277 - 30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C277 - 30WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C277 -40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C277 -40PC
P21
28-Lead (300-Mil) Molded DIP
CY7C277-40WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C277 -40DMB
D22
28-Lead (300-Mil) CerDIP
CY7C277-40KMB
K74
28-Lead Rectangular Cerpack
CY7C277 -40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C277 -400MB
055
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C277 -40TMB
T74
28-Lead Windowed Cerpack T74
CY7C277 -40WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C277-50JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C277 - 50PC
P21
28-Lead (300-Mil) Molded DIP
CY7C277-50WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C277-50DMB
D22
28-Lead (300-Mil) CerDIP
CY7C277 -50KMB
K74
28-Lead Rectangular Cerpack
CY7C277 - 50LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C277 - 500MB
055
32-Pin Windowed Rectangular Leadless Chip Carrier
CY7C277 -50TMB
T74
28-Lead Windowed Cerpack T74
CY7C277 -50WMB
W22
28-Lead (300-Mil) Windowed CerDIP
Note:
11. Most of the above products are available in industrial temperature
range. Contact a Cypress representative for specifications and product
availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
Vm
1,2,3
VIL
1,2,3
IIX
1,2,3
1,2,3
1,2,3
Ioz
Icc
1,2,3
Switching Characteristics
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSA
tHA
I
teo
I
7, 8, 9, 10, 11
I
Document #: 38-00085-E
3-132
Operating
Range
Commercial
Commercial
Military
Commercial
Military
CY7C279
Reprogrammable 32K X 8
Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
- 3 ns max. set-up
- 35 ns clock to output
• Lowpower
- 660 mW (commercial)
-715 mW (military)
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
• Capable of withstanding greater than
2001V static discharge
• Programmable address latch enable
input
• Optional registered/latched address
inputs
• EPROM technology, 100%
programmable
• Slim 300-mil, 28-pin plastic or
hermetic DIP
• 5V ±10% Vee, commercial and
military
Logic Block Diagram
D.
Pin Configurations
DIP
As
A7
As
As
07
ADDRESS
06
A7
05
As
04
A.
As
03
1S-BIT
ADDRESS
REGISTER!
LATCH
A2
A1
02
As
01
A.
00
A3
A2
Ao
COLUMN
CE
Ao
07
06
05
04
00
01
02
GND
DDRESS
A1
VCC
A10
A11
A12
A13
A14
CP/ALE
CS
As
As
256 x 1024
PROGRAMMABLE
ARRAY
03
~=::j:====::J
C279-2
LCC/PLCC (Opaque Only)
Top View
~~~~~.r.r
CPt
ALE
4 3 2,J323130
As
As
A.
A3
A2
A1
Ao
NC
00
C279-1
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617181920
0
A12
A 13
A14
NC
CP/ALE
CS
CE
07
06
"I"'"
C\lOOM v LO
0 0 zzO 0 0
C)
C279-3
Selection Guides
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current (rnA)
Commercial
7C279-35
7C279-45
35
45
55
120
120
120
130
130
30
30
40
40
Military
Commercial
Military
3-133
30
en
:!
oa:
Top View
A14
A 13
A12
A11
A10
As
•
7C279-55
=e.
~~NDUCIOR
CY7C279
Functional Description
The CY7C279 is a high-performance 32K word by 8-bit CMOS
PROM. When deselected, the CY7C279 automatically powers
dow into a low power standby mode. It is packaged in the slim
28-pin 300-mil package. The ceramic package may be equipped
with an erasure window; when exposed to UV light, the PROM is
erased and can then be reprogrammed. The memory cells utilize
proven EPROM floating-gate technology and byte-wide algorithms.
The CY7C279 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
location is written into, erased, and repeatedly exercised prior to
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
nottested. )
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ................ 13.0V
encapsulation. Each PROM is also tested for AC performance to
guarantee that the product will meet DC and AC specification
limits after customer programming.
On the 7C279, address registers are provided to easily interface
with microprocessors that deliver addresses around a rising clock
edge. A programmable bit is provided to select between latched
and registered address inputs. The default is registered inputs,
which will sample the address on the RISING EDGE of CP and
load the address register. The latched address option will
recognize any address changes while the ALE pin is active and load
the address into the address latches on the deactiviating edge of
ALE. If the latched address option is selected, another programmable bit is provided for the user to select the polarity that will
define ALE active, with the default being active HIGH.
UV Erasure ............................. 7258 Wsec/cm 2
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperatnre
O°C to +70°C
Vee
5V ±10%
Industrial[l]
- 40°C to +85°C
5V ±1O%
Military[2]
- 55°C to + 125°C
5V ±1O%
Range
Commercial
Electrical Characteristics Over the Operating Range[3,4]
Parameter
Description
Test Conditions
7C279-35
7C279-45, 55
Min. Max.
Min.
= Min., IOH = - 2.0 rnA
Vee = Min.,IoL = 8.0 rnA
2.4
Input HIGH Level
Guaranteed Input Logical HIGH Voltage
for All Inputs
2.0
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
Irx
Input Leakage Current
GND.5.. VIN.5.. Vee
VeD
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
VIH
Output LOW Voltage
VrL
Vee
0.4
Vee
2.0
0.8
-10
Max.
2.4
+10
-10
Unit
V
0.4
V
Vee
V
0.8
V
+10
!lA
Note 4
Ioz
Output Leakage Current
o.5.. VOUT.5.. Vee, Output DisabledI5T
-40
+40
-40
+40
!lA
los
Output Short Circuit Current
Vee
-20
-90
-20
-90
rnA
Ice
Power Supply Current
= Max., VOUT = O.OVlbJ
Commercial
Vee = Max., CS ~ VIR
lOUT = ornA
Military
Commercial
Vee = Max., CE~ VIR
lOUT = ornA
Military
120
rnA
ISB
Standby Supply Current
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VrLP
Input LOW Programming Voltage
120
130
30
30
12
13
12
50
3.0
3.
4.
3-134
13
V
50
rnA
0.4
V
3.0
0.4
Notes:
.to
Contact a Cypress representative for industrial teniperature range
specifications.
2. TA is the "instant on" case temperature.
rnA
40
V
See the last page of this specification for Group A subgroup testing information.
See "Introduction to CMOS PROMs" in this DataBookfor generalinformation on testing.
~~PRESS
~,
CY7C279
SEMICONDUCTOR
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vcc = 5.0V
Max.
= 1 MHz,
Unit
10
pF
10
pF
AC Test Loads and Waveforms[4]
R1500Sl
(65SSl MIL)
5V o----..AN1Io--,
OUTPUTo---,,--~
FI
30 P
INCLUDING
JIG AND _
SCOPE -
ALL INPUT PULSES
OUTPUTo---..----t
5PFI
R2
333Sl
(403Sl MIL)
(a) Normal Load
Equivalent to:
II
R1500Sl
(65SSl MIL)
5V
INCLUDING
JIGAND _
SCOPE -
C279-4
3.0V
R2
en
:Ii
o
a:
A.
GND
333Sl
(403Sl MIL)
(b) High Z Load
----_u------'!IL
C279-6
C279-5
THEVENIN EQUIVALENT
200Sl
OUTPUT OO----'l.N
..·I.----.()O 2.0V
250Sl
OUTPUT OO----'l.N
....I.----.()O 1.9V
Military
Commercial
C279-7
Switching Characteristics Over the Operating Rangef3,4]
7C279-35
Parameter
Description
Min.
Max.
7C279-45
Min.
7C279-55
Max.
Unit
tAA
Address to Data Valid (Latched Mode)
35
45
55
ns
tco
Clock to Output Valid (Registered Mode)
35
45
55
ns
tHZCS
Chip Select Inactive to High Z
15
20
20
ns
20
ns
15
Max.
Min.
tACS
Chip Select Active to Output Valid
tAR
AddressSet-upto ClockRise (Registered Mode)
3
10
20
10
ns
tRA
Address Hold from Clock Rise (Registered
Mode)
6
10
10
ns
tADH
Data Hold from Clock Rise (Registered Mode)
5
5
5
ns
tsu
Address Set-up to ALE Inactive (Latched Mode )
5
10
10
ns
tHD
Address Hold from ALE Inactive (Latched
Mode)
10
10
10
ns
tpu
Chip Enable Active to Power Up
0
0
0
ns
tpD
Chip Enable Inactive to Power Down
tOH[7]
Output Hold from Address Change (Latched
Mode)
0
0
0
ns
tpwA
ALE Pulse Width
10
20
30
ns
tCESC
Chip Enable Set-up to Clock Rise
10
10
10
ns
tCESL
Chip Enable Set-up to Latch Close (Latch Mode)
10
10
10
tLV
Output Valid from ALE Active (Latched Mode)
40
Notes:
5. For devices using the synchronous enable, the device must be clocked
after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
40
7.
3-135
50
50
60
ns
ns
60
tAA and tOH apply only when the latched mode is selected.
ns
~
~~~
--=-,
CY7C279
_ ' j ; CYPRESS
SEMICONDUCTOR
Architecture Configuration Bits
Architecture
Bit
ALE
Dl
ALEP
D2
Architecture Verify
D7 -Do
0= DEFAULT
1 = PGMED
0= DEFAULT
1 = PGMED
Function
Input Registered
Input Latched
ALE = Active HIGH
ALE = Active LOW
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
7FFF
8000
Data
Control Byte
Architecture Byte (8000)
D7
Do
C7 C6 Cs C4 C3 C2 Cl Co
Timing Diagram (Registered)[8]
Vee
SUPPLY - - - "
CURRENT
CE
CS
Ao -
A14
----"
CP
C279-8
Timing Diagram (ALE)
Vee
SUPPLY _ _ _J
CURRENT
CE
CS _ _ __
Ao -
--+ ___
A14 _ _ _
-J
ALE[8]
C279-9
Note:
8, ALE is shown with positive polarity,
3-136
=;: :-::Z
.'" CYPRF.SS
CY7C279
~
~.,
SEMICONDUCTOR
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[9]
Mode
Read or Output Disable
A14 -
Other
A14 -
Read
A14 -
Output Disable
A14 -
Program
A14 -
Program Verify
A14 -
Program Inhibit
A14 -
Blank Check
A14 -
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
CE
CS
CP/ALE
VFY
PGM
Vpp
D7 - Do
VIL
VIH
VIL
07 - 00
VIH
X
X
HighZ
VIHP
VILP
Vpp
D7 - Do
07 - 00
07 - 00
VILP
VIHPNILP
Vpp
VIHP
VIHP
Vpp
HighZ
VILP
VIHPNILP
Vpp
07 - 00
Note:
9. X = "don't care" but not to exceed Vee ±5%.
DIP
Top View
LCC/PLCC (Opaque Only)
Top View
~::~~~~
4 3 2,1,323130
As
A5
A.,
A3
A2
A,
Ao
NC
Do
29
5
6
7
8
9
10
11
12
13
14151617181920
0
08~~c5'66"
C279-10
Figure 1. Programming Pinouts
3-137
A'2
A'3
A'4
NC
~
'iJF'(
07
06
C279-11
•
en
::E
oa:
a.
~~
27
CY7C279
~iE CYPRESS
_ , SEMICONDUCTOR
1Ypical DC and AC Characteristics
1.6
1.2
Jl1.4
Cl
~ 1.2
/v
::J
::J 1.0
1500V
static discharge
Functional Description
The CY7C281 and CY7C282 are highperformance 1024-word by ~-bit CMOS
PROMs. They are functionally identical, but are packaged in 300-mil and
600-mil-wide packages respectively.
The CY7C281 is also available in a
28-pin leadless chip carrier. The
memory cells utilize proven EPROM
floating-gate technology and byte-wide
intelligent programming algorithms.
The CY7C281 and CY7C282 are plug-in
replacements for bipolar devices and offer the advantages of lower power, superior performance, and programming yield.
Logic Block Diagram
The EPROM cell requires only 13.SV for
the super voltage, and low current requirements allow for gang programming.
The EPRO M cells allow each memory location to be tested 100% because each location is written into, erased, and repeatedly exercised prior to encapsulation.
Each PROM is also tested for AC performance to guarantee that after customer programming, the product will meet
DC and AC specification limits.
Reading is accomplished by placing an
active LOW signal on CSl and CS2, and
active HIGH signals on CS3 and CS4.
The contents of the memory location
addressed by the address lines (Ao Ag) will become available on the output
lines (00 - 07)'
Pin Configurations
DIP
Top View
AS
Os
ROW
DECODER
PROGRAMMABLE
ARRAY
MULTIPLEXER
05
COLUMN
DECODER
04
1----------1
1-_ _ _ _ _ _ _ _ _-'
03
02
C281-2
LCC/PLCC
Top View
)f;f 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Range
Commercial
Industrial[l]
O°Cto +70°C
Vee
5V ±10%
- 40°C to +85°C
5V ±10%
Military[2]
-55°C to +125°C
5V ±1O%
Electrical Characteristics Over the Operating Rangel 3, 4]
7C281-30
7C282-30
Description
Parameter
Test Conditions
Min.
Max.
Vee
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 16.0 rnA
2.4
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
IIX
Input Current
GND ~ VIN ~ Vee
-10
+10
loz
Output Leakage Current
GND ~ VOUT ~ Vee, Output
Disabled
- 40
+40
los
Output Short Circuit Currentl5]
Vee
- 20
- 90
lee
Power Supply Currentl6]
Vee = Max.,
lOUT = ornA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
= Max., VOUT = GND
7C281-45
7C282-45
Min.
0.4
I
I Military
Unit
V
0.4
2.0
0.8
V
V
0.8
V
-10
+10
- 40
+40
fAA
fAA
- 20
- 90
rnA
90
rnA
100
Commercial
Max.
2.4
120
14
14
Vpp
Program Voltage
13
VIRP
Program HIGH Voltage
3.0
VILP
Program LOW Voltage
0.4
0.4
V
Ipp
Program Supply Current
50
50
rnA
13
V
V
3.0
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output CapacItance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4.
5.
6.
3-141
= 1 MHz,
Max.
10
10
Unit
pF
pF
See "Introduction to CMOS PROMs" in this Data Book for generalinformation on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Due to the design of the differential cell in this device, Icc can only be
accurately measured on a programmed array.
II
CY7C281
CY7C282
a;.;riPRFSS
~!F SEMICONDUCTOR
AC Test Loads and Waveforms[4]
OUTP~~31R1
2500
30 pF
R2
1670
I _
INCLUDING
JIG AND SCOPE
-
OlJTP~~:
Ii'1~
1670
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
5 pF
3.0V - - - -
1._----__
ALL INPUT PULSES
GND
_
C281-5
C281-4
(b) High Z Load
THEVENIN EQUIVALENT
1000
OUTPUT O'O---'·'I!I.
........---oo 2.0V
C281-6
Switching Waveforms
Ao - A9
ADDRESS _ _ _ _--'
CS s, CS 4
CS1 , CS2
------+0-------..
------+0------C281-7
Switching Characteristics Over the Operating
Rangd 2
,4]
7C281-30
7C282-30
7C281-45
7C282-45
Max.
Unit
Address to Output Valid
30
45
ns
tHZCS
Chip Select Inactive to High Z
20
25
ns
tACS
Chip Select Active to Output Valid
20
25
ns
Parameter
tAA
Description
Min.
3-142
Max.
Min.
.:::r:
CY7C281
CY7C282
.~
~"CYPRESS
~, SEMICONDUCTOR
Programming Information
Programming support is available from Cypress as well as from a
number of third party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of
this section. Programming algorithms can be obtained from any
Cypress representative.
Table 1. Mode Selection
Pin Function[7]
Read or Output Disable
A9 -Ao
CS4
CS3
CS2
CSl
07 - 00
Other
A9 -Ao
PGM
VFY
Vpp
CSl
D7 - Do
Read
A7 -Ao
VIH
VIH
VIL
VIL
07 - 00
Output Disable
A7 -Ao
X
X
VIH
X
HighZ
Output Disable
A7-Ao
X
VIL
X
X
HighZ
Output Disable
A7-Ao
VIL
X
X
X
HighZ
Output Disable
A7-Ao
X
X
X
VIH
HighZ
Program
A7-Ao
VILP
VIHP
Vpp
VILP
D7- D O
Program Verify
A7-Ao
VIHP
VILP
Vpp
VILP
07 - 00
Program Inhibit
A7-Ao
VIHP
VIHP
Vpp
VILP
HighZ
Intelligent Program
A7 -Ao
VILP
VIHP
Vpp
VILP
D7 - Do
Blank Check Ones
A7 -Ao
Vpp
VILP
VILP
VILP
Ones
Blank Check Zeros
A7 -Ao
Vpp
VIHP
VILP
VILP
Zeros
Mode
Note:
7. X = "don't care" but not to exceed Vee ±5%.
DIP
Top View
LCC/PLCC
Top View
!R:R<"i?1f ~
A-.
A3
A2
A1
Ao
NC
Do
4 32,1,282726
25
24
23
7C281
22
21
10
20
11
19C
,
12131415161718
...... NO ()
C') ~
CS 1
Vpp
IIr'Y
PGM
NC
D7
D6
1.0
OOZZOOO
~
z
::>
25
125
o
........
~
-
"."
10
o
« 175
1.0
2.0
~
~
'"
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
20.0
/
15.0
//
4.0
5.0
7
.-'" ~
~ 125
...... V
a 100
z
75
5a..
50
::>
25
o
o
/
0.0
/
J
V
Vee = 5.0V
TA = 25°C -
I
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
3-144
V
Vee = 4.5V _
TA = 25°C
I
200
400
600
I
800 1000
CAPACITANCE (pF)
150
II:
I-
-
/
~ 10.0
'"
!z
Ci5
6.0
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
~
5.5
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
~
20
AMBIENT TEMPERATURE (0C)
g
5.0
25.0
"-
30
0
I
4.5
30.0
::>
g
I-
0.8
0.6
- 55
TA = 25°C
0.4
4.0
OUTPUT SOURCE CURRENT
vs. VOLTAGE
II:
w
u
0.6
AMBIENT TEMPERATURE (0C)
SUPPLY VOLTAGE (V)
w
oz
0.8 ' -_ _ _...1.-_ _ _ _ _.....1
-55
25
125
6.0
""
w
:::::i
a:
I
~
u
W
N
TA = 25°C
f = fMAX
5.0
~ 1.0
w
0
4.5
i=
4.0
e281-10
CY7C281
CY7C282
~
_'~NDUcrOR
Ordering Information
Speed
(ns)
30
45
Ordering Code
Package
. Name
CY7C281-30DC
D14
24-Lead (300-MiI) CerDIP
CY7C281- 30JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C281-30PC
P13
24-Lead (300-MiI) Molded DIP
CY7C281-45DC
D14
24-Lead (300-MiI) CerDIP
CY7C281-45JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C281-45PC
P13
24-Lead (300-MiI) Molded DIP
CY7C281-45DMB
D14
24-Lead (300-Mil) CerDIP
CY7C281-45KMB
K73
24-Lead Rectangular Cerpack
Speed
(ns)
Ordering Code
Package
Name
CY7C282-30PC
P11
24-Lead (600-MiI) Molded DIP
P11
24-Lead (600-MiI) Molded DIP
CY7C282-45DMB
D12
24-Lead (600-MiI) CerDIP
VOH
VOL
VIR
VIL
IIX
Ioz
Icc
SMD
Number
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
tAA
tACS
•
Commercial
en
:t
oa:
Military
D.
Operating
Range
Commercial
Military
SMD Cross Reference
DC Characteristics
Parameter
Commercial
Package 1YPe
CY7C282-45PC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Operating
Range
Package 1YPe
Subgroups
7, 8, 9, 10, 11
7,8,9, 10, 11
Document #: 38-00006-F
3-145
SuffIX
Cypress
Number
5962-87651
01JX
CY7C282-45DMB
5962-87651
01KX
CY7C281-45KMB
5962-87651
01LX
CY7C281-45DMB
5962-87651
013X
CY7C281-45LMB
CY7C281A
CY7C282A
PRELIMINARY
CYPRESS
SEMICONDUCTOR
lK x 8 PROM
• Capable of withstanding >2001V
static discharge
Features
• CMOS for optimum speed/power
• High speed
- 25 ns (commercial)
- 30 ns (military)
Functional Description
• Lowpower
-495 mW (commercial)
- 660 mW (military)
• EPROM technology 100%
programmable
• Slim 300-mil or standard 600-mil DIP
or 28-pin LCC
• 5V ±10% Vee, commercial and
military
• TTL-compatible I/O
• Direct replacement for bipolar
PROMs
The CY7C281A and CY7C282A are
high-performance 1024-word by 8-bit
CMOS PROMs. They are functionally
identical, but are packaged in 300-mil and
600-mil-wide packages respectively. The
CY7C281A is also available in a 28-pin
leadless chip carrier. The memory cells
utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
The CY7C281A and CY7C282A are
plug-in replacements for bipolar devices
and offer the advantages of lower power,
superior performance, and programming
yield. The EPROM cell requires only
12.5V for the super voltage, and low current requirements allow for gang programming. The EPROM cells allow each
memory location to be tested 100% because each location is written into, erased,
and repeatedly exercised prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after
customer programming, the product will
meet DC and AC specification limits.
Reading is accomplished by placing an active LOW signal on CSI and CSz, and active HIGH signals on CS3 and CS4. The
contents of the memory location addressed by the address lines (Ao - A9)
will become available on the output lines
(00 - 07)·
Pin Configurations
Logic Block Diagram
DIP
Top View
07
A7
Vcc
As
As
At.
A9
CS1
Aa
A2
A1
CS2
CSa
CS4
~
07
Os
05
02
GND
04
Oa
A9
As
A7
As
As
At.
Os
ROW
DECODER
PROGRAMMABLE
ARRAY
MULTIPLEXER
05
As
Aa
A2
A1
04
COLUMN
DECODER
~
Oa
C281A-2
LCC/PLCC
Top View
02
01
:R:tJi"i.~!f~
At.
Aa
A2
A1
00
~
NC
00
4 3 2,-1,282726
25
24
23
7C281 A
22
7C282A
21
20
10
19
11
12131415161718
,....C\loo
('I') 2001V
(per MIL-STD-883, Method 301S)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Vee
O°Cto +70°C
SV ±1O%
Range
Commercial
Industrial[l]
- 40°C to +8SoC
SV ±1O%
Military[2]
-SSoC to +12SoC
SV ±1O%
•
U)
:::i
oa:
Q.
Electrical Characteristics Over the Operating Rangel 3,4]
Parameter
Description
Test Conditions
7C281A-25
7C282A-25
7C281A-30
7C282A-30
7C281A-45
7C282A-45
Min.
Min.
Min.
Max.
Max.
Max.
Unit
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 16.0 rnA
2.4
VIH
Input HIGH Level
Guaranteed Input Logical HIGH
Voltage for All Inputs
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW
Voltage for All Inputs
IIX
Input Current
GND ~ VIN ~ Vee
-10
+10
-10
+10
- 10
+10
fAA
loz
Output Leakage Current
Vo ~ VOUT ~ Vee, Output Disabled
-10
+10
-10
+10
- 10
+10
!lA
los
Output Short Circuit
Current[S]
Vee
- 20
- 90
- 20
- 90
- 20
- 90
rnA
lee
Power Supply Current
Vee = Max.,
lOUT = ornA
100
90
rnA
120
120
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Vee
2.4
0.4
0.4
2.0
I Commercial
100
IMilitary
Vpp
Program Voltage
12
VIHP
Program HIGH Voltage
3.0
13
V
0.4
2.0
0.8
0.8
= Max., VOUT = GND
2.4
12
13
3.0
V
0.8
12
V
13
3.0
V
V
V
VILP
Program LOW Voltage
0.4
0.4
0.4
V
Ipp
Program Supply Current
SO
SO
SO
rnA
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output CapacItance
Test Conditions
TA = 2SoC, f
Vee = S.OV
= 1 MHz,
Max.
10
10
Unit
pF
pF
Notes:
1.
2.
3.
Contact a Cypress representative for industrial temperature range
specifications.
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing information.
4.
5.
3-147
See "Introduction to CMOS PROMs" in this DataBookfor generalinformation on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
. am:ss
~
~,
CY7C281A
CY7C282A
PRELIMINARY
SEMICONDUCTOR
AC Test Loads and Waveforms[4j
OUTP~~31R1
250Q
30 pF
INCLUDING
JIG AND
SCOPE
R2
167Q
I _
~
-
OUTP~:
5 pF
GND
167Q
INCLUDING _
JIG AND SCOPE
(a) Normal Load
Equivalent to:
It}~
ALL INPUT PULSES
3.0V ---·..Jr~90::::"%:----~
_
C281A-5
C281A-4
(b) High Z Load
THEvENIN EQUIVALENT
100Q
OUTPUT O'O-_.J·\I\j
...•.....---oo 2.0V
C281A-6
Switching Waveforms
Ao - Ag
ADDRESS _ _ _ _--'
CS3 • CS4 ------+---S-E-LE-C-T-E-D-......
CS1. CS2 _ _ _ _ _-+-______-'
DESELECTED
t~CSJ
00- 0 7
DATA
C281A-7
Switching Characteristics Over the Operating Range[2,4j
Parameter
Description
7C281A-25
7C282A-25
7C28IA-30
7C282A-30
7C281A-45
7C282A-45
Min.
Min.
Min.
Max.
Unit
tAA
Address to Output Valid
25
30
45
ns
tHzCS
Chip Select Inactive to High Z
15
20
25
ns
tACS
Chip Select Active to Output Valid
15
20
25
ns
3-148
Max.
Max.
it
--=-;F:~PRFSS
CY7C281A
CY7C282A
PRELIMINARY
SEMICONDUCTOR
Programming Information
Programming support is available from Cypress as well as from a
number of third party software vendors. For detailed programming
information, including a listing of software packages, please see the
PROM Programming Information located at the end of this section.
Programming algorithms can be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function[6]
Read or Output Disable
A9 -Ao
CS4
CS3
CS2
CSt
07 - 00
Other
A9 -Ao
PGM
VFY
Vpp
CSt
D7 - Do
I
Read
A9-Ao
VIH
VIH
VIL
VIL
07 - 00
:::i
Output Disable
A9 - Ao
X
X
VIH
X
HighZ
Output Disable
A9 -Ao
X
VIL
X
X
HighZ
Output Disable
A9 -Ao
VIL
X
X
X
HighZ
Output Disable
A9-Ao
X
X
X
VIH
HighZ
Mode
U)
Program
A9 - Ao
VILP
VIHP
Vpp
VILP
D7- DO
Program Verify
A9 -Ao
VIHP
VILP
Vpp
VILP
07 - 00
Program Inhibit
A9-Ao
VIHP
VIHP
Vpp
VILP
HighZ
Intelligent Program
A9-Ao
VILP
VIHP
Vpp
VILP
D7- Do
Blank Check
A9-Ao
VIHP
V1LP
Vpp
VILP
Zeros
Note:
6. X = "don't care" but not to exceed Vee ±S%.
DIP
Top View
4
PGM
NC
432,1,282726
25
24
23
7C281 A
22
21
10
20
07
Os
Os
04
03
Do
111213141516171819
Ag
~
CS1
Aa
Aa
Vpp
A2
A1
VFY
Ao
DO
01
O2
GNO
~~.t~~.f ~
vcc
As
A7
As
As
~
LCC/pLCC
Top View
9
A2
A1
Ao
,.... Ne
t)
('I')
v
CS1
Vpp
VFY
PGM
NC
07
Os
l()
oOzzooo
C)
C281A-9
C281A-8
Figure 1. Programming Pinouts
3-149
oa::
a..
=*~~PRFSS
CY7C281A
CY7C282A
PRELIMINARY
~, SEMICONDUCTOR
TYPical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.2
~
w
::E
01.4
..!:?
0
w
N 1.2
:::i
«
::E
a:: 1.0
z
0
0.8
1/
0.6
4.0
V
/
/
«
()
()
«
N
:::i
«
~
a::
-
TA = 25°C
0.4
4.0
30.0
!zw
50
25.0
~ 20
::E
~
'""'~
~ 10
a.
a:: 0.8
z
0
~
125
o
0
o
1.0
2.0
-
""
« 175
g
I-
a::
a 100
z
Ci5
~ 50
I::::l
/
75
a.
o
/
~ 10.0
5.0
V
25
/
o
0.0
/
/
V
-'
~
V
Vee = 5.0V
TA = 25°C -
I
1.0
2.0
3.0
OUTPUT VOLTAGE
3-150
M
6.0
M
-
V
V
/
Vee = 4.5V _
TA = 25°C
I
J
200
400
600
800 1000
CAPACITANCE (pF)
150
~ 125
~
4.0
15.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
z
5.5
/
20.0
M
OUTPUT VOLTAGE
AMBIENT TEMPERATURE (0C)
~
~
3.0
5.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
60
::::l
I
4.5
SUPPLY VOLTAGE
l
~ 30
a::
'"
0.6
OUTPUT SOURCE CURRENT
vs. VOLTAGE
()
25
oz
0.8 L..-_ _ _...I-._ _ _ _ _--l
-55
25
125
§ 40 ~ ........
1.2
0.6
- 55
:::i
a::
1.0 ~
0.8
AMBIENT TEMPERATURE (0C)
1.4
~
N
M
1.6
0
w
a::
0
z 0.9
6.0
5.5
~
w
::E
= 25°C f = fMAX
5.0
~
o
:::i 1.0
::E
en
en
w
w
()
w
NORMALIZED ACCESS TIME
vs. TEMPERATURE
i=
0
N
TA
SUPPLY VOLTAGE
w
~ 1.0
I
4.5
i=
~ 1.1
4.0
C281A-10
CY7C281A
CY7C282A
~
.
:~PRESS
PRELIMINARY
_ , SEMICONDUcrOR
Ordering Information
Speed
(ns)
25
30
45
Ordering Code
Package
Name
Operating
Range
Package 'JYpe
CY7C281A - 25DC
D14
24-Lead (300-Mil) CerDIP
CY7C281A-25JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
CY7C281A - 25PC
P13
24-Lead (300-Mil) Molded DIP
CY7C281A - 30DC
D14
24-Lead (300-Mil) CerDIP
CY7C281A-30JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C281A-30PC
P13
24-Lead (300-Mil) Molded DIP
CY7C281A-30DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C281A -45DC
D14
24-Lead (300-Mil) CerDIP
Commercial
CY7C281A -45JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C281A -45PC
P13
24-Lead (300-Mil) Molded DIP
CY7C281A -45DMB
D14
24-Lead (300-Mil) CerDIP
CY7C281A -45KMB
K73
24-Lead Rectangular Cerpack
Ordering Code
Package
Name
Speed
(ns)
Military
Operating
Range
Package 'lYpe
25
CY7C282A - 25PC
P11
24-Lead (600-Mil) Molded DIP
30
CY7C282A - 30PC
P11
24-Lead (600-Mil) Molded DIP
Commercial
CY7C282A - 30DMB
D12
24-Lead (600-Mil) CerDIP
Military
45
Commercial
CY7C282A -45PC
P11
24-Lead (600-Mil) Molded DIP
Commercial
CY7C282A -45DMB
D12
24-Lead (600-Mil) CerDIP
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
SMD Cross Reference
SMD
Nnmber
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
VIR
1,2,3
VIL
IIX
1,2,3
1,2,3
Ioz
1,2,3
Icc
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tAA
7, 8, 9, 10, 11
tACS
7, 8, 9, 10, 11
I
Commercial
Document #: 38-00227-A
3-151
Snffix
Cypress
Nnmber
5962-87651
OUX
CY7C282A -45DMB
5962-87651
01KX
CY7C281A -45KMB
5962-87651
01LX
CY7C281A -45DMB
5962-87651
013X
CY7C281A -45LMB
CY7C285
CYPRESS
SEMICONDUCTOR
64K x 8 Reprogrammable
Fast Column Access PROM
Features
Functional Description
• CMOS for optimum speed/power
• Windowed for reprogrammability
• Unique fast column access
-tAA = 20 ns (commercial)
-tAA = 25 ns (military)
The CY7C285 is a high-performance
65,536 by 8-bit CMOS PROM. It is available in a 28-pin 300-mil package and features a unique fast column access feature
that allow access times as fast as 20 ns for
each byte in a 64-byte page. There are 1024
pages in the device. The access time when
changing pages is 65 ns. In order to easily
facilitate the use of the fast column access
feature, a WAIT signal is generated to advise the processor of a page change.
The CY7C285 offers the advantage of low
power, superior performance, and program-
• WAIT signal
• EPROM technology, 100% programmable
• 5V ± 10% Vee, commercial and military
• TTL-compatible I/O
• Slim 300-mil package
• Capable of withstanding >2001V
static discharge
ming yield. The EPROM cell requires only
12.5V for the super voltage, allowing for
each memory location to be 100% tested,
with each location being written into,
erased, and repeatedly exercised prior to
encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer programming the product
will meet DC and AC specification limits.
Reading the CY7C285 is accomplished~
placing an active LOW signal on the CS
pin. The contents of the memory location
addressed by the address lines (Ao - A1S)
will become available on the output lines
(00 - 07)·
Pin Configurations
Logic Block Diagram
CerDiP
Top View
As
Vee
As
A7
AlO
A'5
A'4
As
A'2
Os
A"
AlO
02
GND
04
8
OUTPUT
BUFFERS
As
A5
07
Os
05
04
00
0,
As
A7
C"S
WAIT
Ao
05
As
A"
A'2
A'3
A14
A'5
As
~
~
A2
A,
07
A'3
03
C285-2
03
LCC
Top View
~
02
~
()o~
:t:z:t~;},:(:(
A2
0,
A,
As
~
Ao
A3
NC
A2
A,
00
Ao
GND
00
5
6
7
8
9
10
11
12
13
14151617181920
0
ocS"~O'O'cfO"
C285-1
(!)
A'2
A'3
A'4
A'5
NC
C"S
WAiT
07
GND
C285-3
Selection Guide
Description
Maximum Access Time (ns)
f\.A"<;lvlTnlln"1 ()npT"gtlnct r11rrpnt {Tn A '\
7C285-65
65
I Page Access Time
I Column Access Time
20
180
I Commercia!
3-152
\
7C285-75
75
7C285-85
85
25
180
35
180
200
200
.:::aro: .~
~.a CYPRESS
CY7C285
.11' SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ...................... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State '" . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
DC Program Voltage (Pin 22) ...................... 13.0V
UV Exposure ........................... 7258 Wsec/cm2
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
I
Vee
5V ± 10%
O°C to +70°C
Industrial[l]
- 40°C to +85°C
5V ± 10%
Military[2]
- 55°C t6 +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[3,4]
7C285
Parameter
Description
Test Conditions
Min.
= Min., IOH = - 2.0 mA
Vee = Min., IOL = 8.0 mA[S]
2.4
2.0
Max.
Unit
0.4
V
Vee
V
0.8
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
Input HIGH Level
Guaranteed Input Logical HIGH Voltage
for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage
for All Inputs
VeD
Input Diode Clamp Voltage
IIX
Input Load Current
GND ~ VIN ~ Vee
-10
+10
fAA
Ioz
Output Leakage Current
GND ~ VOUT ~ Vee, Output Disabled
- 40
+40
!LA
- 20
- 90
mA
180
mA
200
mA
Vee
V
Note 4
los
Output Short Circuit Current[6]
Vee
Icc
Vee Operating Supply Current
Vee
= Max., VOUT = GND
= Max., lOUT = 0 mA
I Com'l
I Mil
V
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
10
10
Unit
pF
pF
Notes:
1.
2.
3.
Contact a Cypress representative for industrial temperature range
specification.
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing information.
4.
5.
6.
3-153
See Introduction to CMOS PROMs in this Data Book for general information on testing.
IOL = 6.0 rnA for military.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
~
~~PRESS
_ , SEMICONDUcrOR
CY7C285
AC Test Loads and Waveform[4]
R15000
(Rl 6580 Mil)
5V o-----'INY-...,
R15000
(R16580 Mil)
5V O - - _........INY--,
OUTPUTo-----1~-...
FI
30 P
INCLUDING
JIGAND _
ALL INPUT PULSES
OUTPUTO---P---....
R2
3330
(4030 Mil)
5PFI
3.0V -----:::Lr------~
R2
3330
(4030 Mil)
INCLUDING
JIGAND _
SCOPE -
SCOPE -
(b) High Z Load
(a) Normal Load
C285-4
THEVENIN EQUIVALENT
Equivalent to:
GND
C285-5
2500
2000
OUTPUT (),O---"1.''011
.. _ _--00 1.9V
OUTPUT ().0---"I..y,.6_---o0 2.0V
Military
Commercial
Switching Characteristics Over the Operating Range[3, 4]
7C285-75
7C285-65
Parameter
Min,
Description
Max.
Min.
7C285-85
Max.
Min.
Max.
Unit
tRAC
Slow Address Access Time (Ati - AlS)
65
75
85
ns
tCAA
Fast Address Access Time (An - As)
20
25
35
ns
tHZCS
Output High Z from CS
15
20
25
ns
tACS
Output Valid from CS
15
20
25
ns
tWD
WAIT Delay from First Slow Address Change
20
25
35
ns
tDW
WAIT Hold from Data Valid
tww
WAIT Recovery from Last Address Change
tPWD
WAIT Pulse Width
0
0
ns
0
110
90
120
12
10
15
ns
ns
Switching Waveform
cs_--t
)K
}:tACS
tHZCS -
VALID
"
/
HIGHZ
---I
"-
VALID
tRAC
)K
~ tCAA----
Ao -
)(
A5
---t""'---~""-----C285_6
I.
~two
•
tow
tww
tpwo
3-154
~
==-.::;z
CY7C285
======1=
CYPRESS
~F SEMICONDUcrOR
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase the
7C285 in the windowed package. For this reason, an opaque label
should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multipled by exposure time) of 25 Wsec/cm 2. For an ultraviolet lamp
with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The 7C285 needs to be within linch ofthe
lamp during erasure. Permanent damage may result if the PROM
is exposed to hi~h- intensity UV light for an extended period oftime.
7258 Wsec/cm is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, induding a listing of software packages, please
see the PROM Programming Information located at the end of •
this section. Programming algorithms can be obtained from any
Cypress representative.
fI)
::IE
Mode Selection
o
a:
a..
Pin Number
22
Mode: Read or Output Disable
23
21
20
19-15,13-11
CS
WAIT
07 - 00
A15
A14
Read (within a page: ~ - A15 stable)
A15
A14
VIL
VOH
0 7 - 00
Read (page break: ~ - A 15 transition)
A15
A14
VIL
Pulse LOW
0 7 - 00
Output Disable
A15
A14
Output
HighZ
Vpp
LATCH
VIH
PGM
VFY
D7 - Do
Program
Vpp
VILP
VILP
VIHP
D7 - Do
Program Inhibit
Vpp
VILP
VIHP
VIHP
HighZ
Program Verify
Vpp
VILP
VIHP
VILP
07 - 00
Blank Check
Vpp
VILP
VIHP
VILP
Zeros
Mode: Other
DIP
Ag
As
A7
As
As
A4
A3
A2
A1
Ao
Do
D1
D2
GND
LCC
:e~::~~~
Vee
A10
An
A12/A14
A12001V
static discharge
• CMOS for optimum speed/power
• Windowed for reprogrammability
Functional Description
The CY7C286 and the CY7C287 are
high-performance 65,536 by 8-bit
CMOS PROMs. The CY7C286 is configured in the lEDEC-standard 512K
EPROM pinout and is available in a
28-pin, 600-mil package. Power consumption is 120 rnA in the active mode
and 40 rnA in the standby mode. Access
time is 50 ns. The CY7C287 has registered outputs and operates in the synchronous mode. E can also be pro~ammed into the synchronous mode,
Es. It is available in a 28-pin, 300-mil
package. The address set-up time is 45
ns and the time from clock HIGH to
output valid is 15 ns.
• High speed
- tSA = 45 ns (7C287)
- tco = 15 ns (7C287)
- tACC = 50 ns (7C286)
• Lowpower
-120 rnA active
- 40 rnA standby (7C286)
• On-chip, edge-triggered output
registers (7C287)
• Programmable synchronous (7C287
only) or asynchronous output enable
• EPROM technology, 100%
programmable
Both the CY7C286 and the CY7C287 are
available in a cerDIP package equipped
with an erasure window to provide reprogrammability. When exposed to UV light,
the PROM is erased and can be repro-
• 5V ± 10% VCC, commercial and
military
• TTL-compatible I/O
• Slim 300-mil package (7C287)
grammed. The memory cells utilize proven
EPROM floating-gate technology and bytewide intelligent programming algorithms.
The CY7C286 and the CY7C287 offer the
advantage oflowpower, superior performance, and programming yield. The
EPROM cell requires only 12.5V for the
supervoltage and low current requirements allow for gang programming. The
EPROM cells allow for each memory
location to be 100% tested with each
location being written into, erased, and
repeatedly exercised prior to encapsulation. Each PROM is also tested for AC
performance to guarantee that the product will meet DC and AC specification
limits after customer programming.
Reading the CY7C286 is accomplished by
~cing active LOW signals on the OE and
CE pins. Reading the CY7C287 is accomE).isbed by placing an active LOW signal on
ElEs. The contents of the memory location
addressed by the address lines (Ao - AlS)
will become available on the output lines
(00 - 07) on the next rising of CPo
Logic Block Diagram
Pin Configurations
CerDIP
Top View
A 1S ' "
07
A14 ' "
A13 . . .
A12 ' "
x
8-BIT
EDGE·
TRIGGERED
REGISTER
(7C287
ONLy)
ROW
ADDRESS
A11 ' "
A10 ' "
Ag ...
As'"
06
Os
04
03
A7 ' "
As'"
As'"
O2
A., ...
A3...
01
A2 ' "
A1 ' "
.- - - - - - - - - - - - - - - - - - - - - - --
Ao'"
CerDIP
Top View
A1S
Vce
As
A12
A7
A14
A 13
As
AlO
A7
A11
As
As
As
As
As
A12
A 13
As
A.,
OE
A3
A 10
CE
A2
A1
00
07
06
00
E/Es
07
06
01
Os
01
Os
02
04
02
GND
03
GND
04
03
Ao
Ao
LCC
Top View
OE--~...../
()o~
<;1Sl»1~
CP
As
As
A.,
(7C287 ONLy)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C286-1
_1-
A3
A2
A1
Ao
NC
00
5
6
7C286
7
8
9
10
11
12
13
14151617181920
0
C286-5
LCC
Top View
;f<~~:9«
E/ES
-
CP
C286-2
(7C286 ONLY)
CE
A14
A 1s
A3
A2
A1
00
,..----------------------------------I
A.,
A11
I.-......!_--I POWER.DOWN I--_....J
I
Vcc
As
As
A11
As
A.,
A3
NC
NC
DE
A2
A1
AlO
CE
07
06
Ao
GND
00
4 3 2: 1, 323130
29
5
6
7C287
7
8
9
10
11
12
21
13
14151617181920
0
A12
A13
A14
A1S
NC
CP
E/Es
07
GND
o8~c5'ac5'2001V
(per MIL-STD-883, Method 3015.2)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
IndustriaIll J
MilitaryLZJ
Ambient
Temperature
O°C to +70°C
- 40°C to +85°C
- 55°C to +125°C
Vee
5V ± 10%
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Ranger3]
7C286-50
7C286-60
7C287-45
7C287-55
Parameter
Description
Test Conditions
Min. Max. Min. Max.
Output HIGH Voltage
2.4
2.4
Vee = Min., IOH = - 2.0 rnA
VOH
Output LOW Voltage
0.4
0.4
Vee = Min., IOL = 8.0 rnA Com'l
VOL
0.4
Vee = Min., IOL = 6.0 rnA Mil
Input HIGH Voltage
Guaranteed Input Logical HIGH 2.0
VIR
Vee
Vee 2.0
Voltage for Inputs
Input LOW Voltage
Guaranteed Input Logical LOW
0.8
0.8
VIL
Voltage for Inputs
Input Load Current
-10 +10 -10 +10
IIX
GND ~ VIN ~ Vee
Input Diode Clamp Voltage
Note 4
VCD
Output Leakage Current
- 40 +40 - 40 +40
loz
GND~ VOUT~ Vee,
Output Disabled
Output Short Circuit Current Vee = Max., VOUT = GNDl5]
- 20 - 90 - 20 - 90
los
Com'l
Vee Operating
120
120
Vee = Max.,
Icc
(7C286)
Supply Current
lOUT = ornA
Mil
150
Com'l
120
Vee Operating
120
Vee = Max.,
lee
(7C287)
Supply Current
lOUT = ornA
150
Mil
ISBl6]
Standby Supply Current
40
40
Vee = Max., CE = HIGH Com'l
Mil
50
Notes:
1.
2.
3.
Contact a Cypress representative for industrial termperature range
specifications.
TA is the "instant on" case temperature.
See the last page of this spt:dfication for Group A subgroup testing information.
4.
5.
6.
3-158
7C286-70,80
7C287-65
Min.
Max. Unit
2.4
V
V
0.4
0.4
2.0
V
Vee
0.8
V
-10
+10
!lA
- 40
+40
JlA
- 20
- 90
90
120
120
150
30
40
rnA
rnA
rnA
rnA
See Introduction to CMOS PROMs for general information on
testing.
Short circuit test should not exceed 30 seconds.
Only the CY7C286 has a standby mode.
CY7C286
CY7C287
~~
.¥~
~iF SEMICONDUCTOR
Capacitance[4]
Parameter
Description
Input Capacitance
Output CapacItance
CIN
COUT
Unit
pF
pF
Max.
10
10
Test Conditions
TA = 25°C, f = 1 MHz,
Vcc = 5.0V
•
AC Test Loads and Waveform[4]
R1500Sl
(R1 658Sl MIL)
R1500Sl
(R1 658Sl MIL)
OUTPUT
ALL INPUT PULSES
5V
5V
0---..--""
FI
30 P
INCLUDING
JIGAND _
SCOPE -
OUTPUT
R2
333Sl
(403Sl MIL)
0---..--'"
5PFI
INCLUDING
JIG AND _
SCOPE -
3.0V - - - - _ . - - - - - _
90%
R2
333Sl
(403Sl MIL)
GND
(b) High Z Load
(a) Normal Load
C286-7
C286-6
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT 0
200Sl
......
250Sl
OUTPUT~1.9V
0 2.0V
Military
Commercial
7C286 Switching Characteristics Over the Operating Rangel3, 4]
7C286-50
7C286-70
7C286-60
Max.
Unit
tACC
Address Access Time
50
60
70
80
ns
tCE
Output Valid from CE
50
60
70
80
ns
tOE
Output Valid from OE
18
20
25
25
ns
tDF
Output Tri-State from CE/OE
18
20
25
25
ns
tpu
Chip Enable to Power-Up
tpD
Chip Disable to Power-Down
Parameter
Description
Min.
Max.
0
Min.
Max.
Max.
Min.
0
0
40
Min.
7C286-80
0
50
ns
60
60
ns
7C287 Switching Characteristics Over the Operating Rangel3, 4]
7C287-45
Parameter
Description
Min.
Max.
7C287-55
Min.
Max.
7C287-65
Min.
Max.
Unit
ns
tSA
Address Set-Up to Clock HIGH
45
55
65
tRA
Address Hold from Clock HIGH
0
0
0
tco
Clock HIGH to Output Valid
15
20
25
ns
tHZE
Output High Z from E
15
20
25
ns
tDOE
Output Valid from E
15
20
25
ns
ns
tpwc
Clock Pulse Width
15
20
25
ns
tSEs[7]
Es Set-Up to Clock HIGH
12
15
18
ns
5
tHEs[7]
Es Hold from Clock HIGH
tHZC[7]
Output High Z from CLK/Es
20
25
30
ns
tCOP]
Output Valid from CLK/Es
20
25
30
ns
Note:
7. Parameters with synchronous Es option.
3-159
ns
10
8
CY7C286
CY7C287
Architecture Configuration Bits
Architecture
Bit
Architecture Verify
Do
Device
7C287
E/Es
Do
Function
I 0 = Erased
I 1 = PGMED
= E)
= Es)
Asynchronous Output Enable (Pin 20
Synchronous Output Enable (Pin 20
BitMap
Programmer Address (Hex.)
RAM Data
0000
Data
FFFF
10000
Data
Control Byte
Architecture Byte (10000H)
D7
Do
C7 C6 Cs C4 C3 Cz Cl Co
Switching Waveform for the 7C286
14---tDF
C286-8
Switching Waveform for the 7C287
--tHA~I....oo---~~-
'HAF
..- , .
CP
HIGHZ
~_ _~_ _ _ _ _ _ _ _ _ _~_tHZ_E_ _ _ _{:_tDO_E_ __ _
C286-9
3-160
CY7C286
CY7C287
~~
~,~
'~ONDucrOR
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
7C286 and 7C287 in the windowed package. For this reason, an
opaque label should be placed over the window ifthe PROM is exposed to sunlight or fluorescent lighting for extended periods of
time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of25 Wsec/cm 2 . For an ultraviolet lamp with a 12 m W /cm 2 power rating, the exposure time
would be approximately 35 minutes. The 7C286 or 7C287
needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/
cm 2 is the recommended maximum dosage.
Programming Modes
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end of this
section. Programming algorithms can be obtained from any Cypress representative.
a..
Pin Number[8]
Mode: Read or Output Disable
23
20
22
19-15,13-11
AIO
All
CE
OE
07 - 00
Read
AlO
All
VIL
VIL
07 - 00
Output Disable
AlO
A11
X
VIH
HighZ
Output Disable & Power Down
AlO
A11
VIH
X
HighZ
PGM
LATCH
VFY
Vpp
D7 - Do
VILP
VILP
VIHP
Vpp
D7 - Do
07 - 00
Mode: Other
Program
Program Verify
VIHP
VILP
VILP
Vpp
Program Inhibit
VIHP
VILP
VIHP
Vpp
HighZ
Blank Check
VIHP
VILP
VILP
Vpp
Zeros
19-15,13-11
Table 2. CY7C287 Mode Selection
Pin Function[8]
Mode: Read or Output Disable
Synchronous Read
Output Disable - Asychronous
Output Disable - Synchronous
21
23
20
22
CP
A14
E,Es
A15
07 - 00
VIVVIH
A14
VIL
A15
07 - 00
X
A14
VIH
A15
HighZ
VIH
A15
HighZ
D7 - Do
VIVVIH
A14
Mode: Other
PGM
LATCH
VFY
Vpp
Program
VILP
VILP
VIHP
Vpp
D7 - Do
Program Verify
VIHP
VILP
VILP
Vpp
07 - 00
Program Inhibit
VIHP
VILP
VIHP
Vpp
HighZ
Blank Check
VIHP
VILP
VILP
Vpp
Zeros
Note:
8.
X = "don't care" but not to exceed Vee ±5%.
3-161
U)
:I
oa::
Table 1. CY7C286 Mode Selection
21
I
CY7C286
CY7C287
Lee
DIP
vee
A15
A12
A7
As
A5
A14
A13
AsIAn
Ag/A10
~
LATCH
As
A3
A2
A1
Vpp
J5GM
A2
A1
As
Ao
Do
01
02
GNO
A5
~
Ao
'VF'/
NC
07
06
05
04
03
Do
5
6
7C286
7
8
9
10
11
12
13
14151617181920
0
A5
~
LATCH
NC
A3
A2
A1
Vpp
Ao
GNO
zzooo
(!)
C286-11
:f!i::~~~~
Vee
A10
A11
A12/A14
A1a1A15
Do
D1
O2
07
06
Lee
Ag
As
Vpp
J5GM
'VF'/
C286-10
As
As
LATCH
NC
..... C\lOU C'?"i'U')
00
DIP
A7
AslA11
AslA10
~
As
A2
A1
rsm;l
Ao
'VF'/
07
06
D5
04
03
GNO
Do
5
6
7C287
7
8
9
10
11
12
13
14151617181920
0
A12/A14
A13IA15
LATCH
Vpp
NC
J5GM
'VF'/
07
GNO
,....C\l0 (').q-U')co
00
C286-12
Figure 1. Programming Pinouts
3-162
zoooo
(!)
C286-13
=="":'
CY7C286
CY7C287
'i~
-=- =
====="
F
CYPRFSS
SEMICONDUCTOR
Ordering Information[9]
Speed
(ns)
Ordering Code
Package
Name
Package 'lYpe
Operating
Range
50
CY7C286-50PC
P15
28-Lead (600-Mil) Molded DIP
Commercial
60
CY7C286-50WC
CY7C286-60PC
W16
P15
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) Molded DIP
Commercial
70
CY7C286-60WC
CY7C286-60DMB
CY7C286-60LMB
CY7C286-600MB
CY7C286-60WMB
CY7C286-70PC
W16
D16
L55
055
W16
P15
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) Molded DIP
80
CY7C286-70WC
CY7C286-70DMB
CY7C286-70LMB
CY7C286-700MB
CY7C286-70WMB
CY7C286-80WMB
W16
D16
L55
055
W16
W16
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (600-Mil) Windowed CerDIP
28-Lead (600-Mil) Windowed CerDIP
CY7C286-800MB
055
32-Pin Windowed Rectangular Leadless Chip Carrier
Ordering Code
Package
Name
Package 'lYpe
Speed
(ns)
Military
Commercial
Military
Military
Operating
Range
45
CY7C287 -45PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
55
CY7C287 -45WC
CY7C287 - 55PC
W22
P21
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Molded DIP
Commercial
65
CY7C287-55WC
CY7C287-55DMB
CY7C287-55LMB
CY7C287 - 550MB
CY7C287 - 55WMB
CY7C287-65PC
W22
D22
L55
055
W22
P21
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Molded DIP
CY7C287-65WC
CY7C287-65DMB
CY7C287-65LMB
CY7C287 -650MB
CY7C287 -65WMB
W22
D22
L55
055
W22
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
32-Pin Windowed Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Windowed CerDIP
Note:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-163
Military
Commercial
Military
•
•
CY7C286
CY7C287
~~
'16 CYPRESS
_
IF
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
IIX
1,2,3
1,2,3
1,2,3
Ioz
1,2,3
Icc
ISB[lO)
1,2,3
VIL
1,2,3
Switching Characteristics
Device
Parameter
7C286
tACC
7, 8, 9, 10, 11
tCE
7, 8, 9, 10, 11
tOE
7,8,9, 10, 11
7,8,9, 10, 11
7C287
tSA
Subgroups
tHA
7, 8, 9, 10, 11
tco
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
tpwc
7, 8, 9, 10, 11
Note:
10. CY7C286 only.
Document #: 38-00103-G
3-164
This is an abbreviated data sheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the CY7C291A12A.
CYPRESS
SEMICONDUCTOR
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
-35 ns (commercial)
- 35 ns (military)
• Lowpower
-330 mW (commercial)
-660 mW (military)
• EPROM technology 100%
programmable
• Slim 300-mil or standard 600-mil
packaging available
• 5V ± 10% Vee, commercial and
military
• TTL-compatible I/O
Reprogrammable 2K X 8
PROM
• Direct replacement for bipolar
PROMs
• Capable of withstanding > 2000V
static discharge
Features
CY7C291
CY7C292
Functional Description
The CY7C291 and CY7C292 are highperformance 2048-word by 8-bit CMOS
PROMs. They are functionally identical,
but are packaged in 300-mil and 600-mil
wide plastic and hermetic DIP packages
respectively. The 300-mil ceramic DIP
package is equipped with an erasure window; when exposed to UV light the
PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY7C291 and CY7C292 are plug-in
replacements for bipolar devices and offer
the advantages of lower power, superior
performance, and programming yield. The
EPROM cell requires only 12.5V for the super voltage, and low current requirements
allow for gang programming. The
EPROM cells allow each memory location
to be tested 100% because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming,
the product will meet DC and AC specification limits.
Reading is accomplished by placing an active LOW signal on CSt, and active HIGH
signals on CS2 and CS3. The contents ofthe
memory location addressed by the address
lines (An - AlO) will become available on
the output lines (00 - 07).
Logic Block Diagram
Pin Configurations
DIP
DECODER
128 x 128
PROGRAMABLE
ARRAY
8x10F16
MULTIPLEXER
A7
Vee
As
Os
As
As
At.
CS,
05
Aa
A2
A,
Ag
A10
18
AI;,
00
0,
04
02
GND
CS2
CSa
07
Os
05
04
Oa
Oa
LCe
~~~~,U5~~
02
At.
As
0,
A2
A,
AI;,
NC
00
00
432,-1,282726
25
24
23
22
21
20
10
19
11
12131415161718
0
o8'~~c5'O'"cf
C291-1
C291-2
A10
CS,
CS2
CSa
NC
07
Os
C291-3
Window available on 300-mil cerdip only.
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
STD
L
Commercial
Military
Commercial
Note:
1. 7C291 only.
3-165
7C291-35
7C292-35
35
90
120[1J
60
7C291-50
7C292-50
50
90
120
60
•
tn
:E
oa:
Il.
CY7C291A
CY7C292A/CY7C293A
CYPRESS
SEMICONDUCTOR
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
- 20 os (commercial)
-25 ns (military)
• Lowpower
-660 mW(commercial and military)
• Low standby power
-220 mW (commercial and military)
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil
packaging available
• 5V ±10% Vee, commercial and
military
• TTL-compatible I/O
Reprogrammable 2Kx·8PROM
• Direct replacement for bipolar
PROMs
• Capable of withstanding >2001V static discharge
Functional Description
The CY7C291A, CY7C292A, and
CY7C293A are high-performance 2Kword by 8-bit CMOS PROMs. They are
functionally identical, but are packaged in
300-mil (7C291A, 7C293A) and 600-mil
wide plastic and hermetic DIP packages
(7C292A). The CY7C293A has an automatic power down feature which reduces
the power consumption by over 70% when
deselected. The 300-mil ceramic package
may be equipped with an erasure window;
when exposed to UV light the PROM is
erased and can then be reprogrammed.
The memory cells utilize proven EPROM
floating-gate technology and byte-wide intelligent programming algorithms.
Logic Block Diagram
The CY7C291A, CY7C292A, and
CY7C293A are plug-in replacements for
bipolar devices and offer the advantages of
lower power, reprogrammability, superior
performance and programming yield. The
EPROM cell requires only 12.5V for the
supervoltage and low current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested 100%, as each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM
is also tested for AC performance to guarantee that after customer programming
the product will meet DC and AC specification limits.
A read is accomplished by placing an active LOW signal on CSl, and active HIGH
signals on CS2 and CS3. The contents of
the memory location addressed by the address line (An - AlO) will become available on the output lines (00 - 07).
Pin Configurations
DIP
Top View
07
06
LCC/PLCC (Opaqe Only)
Top View
Vee
A7
As
As
As
A.t
A9
Al0
04
A3
A2
Al
CS1
CS2
CS3
03
Ao
07
06
Os
04
03
Os
00
02
01
02
GND
:R :t !/~. ~ Jf ~
A.t
Aa
A2
Al
Ao
NC
00
4 3 2 ..1,282726
25
24
7C291 A
23
22
21
7C293A
20
10
19
11
12131415161718
0
A10
CS1
CS2
CS3
NC
07
06
o8~':i.BCc5'
Cl
C291A-3
01
C291A-2
Window available on
7C291A and 7C293A
only.
00
C291A-1
Selection Guide
Maximum Access Time (ns)
Standard
Maximum 03erating
Current (rnA
L
Standby Current (rnA)
7C293AOnly
Commercial
Military
Commercial
Commercial
Military
7C29IA-20
7C292A-20
7C293A-20
20
120
40
3-166
7C29IA-25
7C292A-25
7C293A-25
7C29IAL-25
7C292AL-25
7C293AL-25
25
90
120
60
30
40
7C291A-35
7C292A-35
7C293A-35
7C291AL-35
7C292AL-35
7C293AL-35
35
90
90
60
30
40
7C291A-50
7C292A-50
7C293A-50
7C291AL-50
7C292AL-50
7C293AL-50
50
90
90
60
30
40
CY7C291A
CY7C292A/CY7C293A
~
~~PRFSS
::::u:u' SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential ....... - 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
DC Program Voltage ............................. 13.0V
UV Exposure ........................... 7258 WsecICm 2
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Range
Commercial
Industrial[l]
O°Cto + 70°C
Vee
5V ±10%
- 40°C to + 85°C
5V ±10%
Military[2]
- 55°C to + 125°C
5V ±10%
•
Electrical Characteristics Over the Operating Rangel3, 4]
Parameter
Description
7C291A-20
7C292A-20
7C293A-20
7C29IA-25
7C292A-25
7C293A-25
7C291AL-25
7C292AL-25
7C293AL-25
Min.
Min.
Test Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
2.4
VOL
Output LOW Voltage
Vee = Min.,
IOL = 16.0 rnA
VIH
Input HIGH Voltage
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Voltage
Guaranteed Input Logical
LOW Voltage for All Inputs
GND~VIN~Vee
Max.
0.4
2.0
Vee
Max.
Unit
0.4
V
Vee
V
0.8
V
-10
+10
!lA
2.4
0.4
2.0
0.8
Vee
2.0
0.8
IIX
Input Load Current
Input Diode Clamp Voltage
loz
Output Leakage Current
GND ~ VOUT ~ Vee.
Output Disabled
-10
+10
-10
+10
-10
+10
!lA
los
Output Short Circuit
CurrentlS]
Vee = Max., VOUT = GND
- 20
- 90
- 20
- 90
- 20
- 90
rnA
lee
Vee Operating Supply
Current
Vee = Max.,
lOUT = ornA
60
rnA
Standby Supply Current
(7C293A Only)
Ycc =
30
rnA
Vpp
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming
Voltage
VILP
Input LOW Programming
Voltage
+10
-10
V
VeD
ISB
-10
Max.
2.4
+10
Note 4
Com'l
120
90
Mil
120
Com'l
Max.,
CSl=VIH
40
30
Mil
40
12
13
12
3.0
4.
5.
3-167
12
13
V
50
rnA
3.0
3.0
0.4
Notes:
1. Contact a Cypress representative for industrial temperature range
specifications.
2. TA is the "instant on" case temperature.
3. See the last page of this specification for Group A subgroup testing information.
13
50
50
0.4
V
0.4
V
See the "Introduction to eMOS PROMs" section of the Cypress Data
Book for general information on testing.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
---
CY7C291A
CY7C292A/CY7C293A
==---.~
iE CYPRESS
====
,
SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangel 3, 4) (continued)
7C291AL-35, 50
7C292AL-35, 50
7C293AL-35, 50
Description
Parameter
Test Conditions
Min.
2.4
Max.
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 16.0 rnA
VIH
Input HIGH Voltage
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Voltage
Guaranteed Input Logical
LOW Voltage for All Inputs
IIX
Input Load Current
GND.5. VIN.5. Vee
VeD
Input Diode Clamp Voltage
loz
Output Leakage Current
GND .5. VOUT .5. Vce,
Output Disabled
-10
+10
los
Output Short Circuit Current(5)
- 90
Vee Operating Supply Current
Vee = Max., VOUT = GND
Vee = Max., Commercial
VIN = 2.0V
Military
IOUT=OrnA
- 20
Icc
ISB
Standby Supply Current
(7C293A Only)
Vce = Max.,
CSl =VIH
Programming Supply Voltage
Ipp
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
Min.
0.4
Unit
V
0.4
2.0
V
2.0
V
+10
flA
- 10
+10
flA
- 20
-10
+10
V
0.8
0.8
-10
Max.
2.4
VOH
Vpp
7C291A-35,50
7C292A-35,50
7C293A-35,50
Note 4
- 90
rnA
60
90
rnA
30
30
90
Commercial
rnA
40
Military
12
12
13
50
13
V
50
rnA
3.0
3.0
V
0.4
0.4
V
Capacitance(4)
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
3-168
Max.
Unit
10
pF
10
pF
CY7C291A
CY7C292A/CY7C293A
~
~~PRESS
~~ SEMUCONDUCTOR
AC Test Loads and Waveforms[4]
OUTP~~~R1
2500
FI
30 P
INCLUDING _
JIG AND SCOPE
OUTP~~~R1
2500
5 PF
R2
1670
_
-
GND
R2
1670
INCLUDING _
JIG AND SCOPE
_
C291A-5
C291A-4
(b) High Z Load
(a) Normal Load
Equivalent to:
I
ALL INPUT PULSES
3.0V -----.-U~~--~!IL
THEVENIN EQUIVALENT
1000
OUTPUT Oo---.NV""-----oO 2.0V
C291A-6
Vee
SUPPLY
CURRENT
Ao - A10
ADDRESS
C291A-7
Switching Characteristics
Parameter
Over the Operating Rangd3, 4]
Description
7C291A-20
7C292A-20
7C293A-20
7C291A-25
7C292A-25
7C293A-25
7C291AL-25
7C292AL-25
7C293AL-25
7C291A-35
7C292A-35
7C293A-35
7C291AL-35
7C292AL-35
7C293AL-35
7C291A-50
7C292A-50
7C293A-50
7C291AL-50
7C292AL-50
7C293AL-50
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
tAA
Address to Output Valid
20
25
35
50
ns
tHZCSl
Chip Select Inactive to High Z
15
15
20
20
ns
tACSl
Chip Select Active to Output Valid
15
15
20
20
ns
tHZCS2
Chip Select Inactive to High Z
(7C293A CSI Only)[6]
22
27
35
45
ns
tACS2
Chip Select Active to Output Valid
(7C293A CSI Only)[6]
22
27
35
45
ns
tpu
Chip Select Active to Power-Up
(7C293A CSI Only)
tpD
Chip Select Inactive to Power-Down
(7C293A CSI Only)
0
0
22
Notes:
6. tHZCS2 and tACS2 refer to 7C293A CSl only.
3-169
0
27
ns
0
35
45
ns
•
CY7C291A
CY7C292NCY7C293A
:~
~=CYPRESS
·
~,
SEMICONDUCTOR
Erasure Characteristics
Wavelengths oflight less than 4000 Angstroms begin to erase these
PROMs. For this reason, an opaque label should be placed over
the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time.
The recommended dose of ultraviolet light for erasure is a wavelength of 2537 Angstroms for a minimum dose (UV intensity x exposure time) of 25 Wsec/cm 2 • For an ultraviolet lamp with a 12
mW/cm 2 power rating, the exposure time would be approximately
35 minutes.
These PROMs need to be within 1 inch ofthe lamp during erasure.
Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is
the recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as from a
number of third-party software vendors. For detailed programming information, including a listing of software packages, please
see the PROM Programming Information located at the end ofthis
section. Programming algorithms can be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function(7)
Mode
Ao
Read or Output Disable
AIO -
Other
AIO - Ao
Read
AlO -
Output Disablel8)
AlO -
Output Disable
AlO -
Output Disable
AlO -
Program
AlO -
Program Verify
AlO -
Program Inhibit
AlO -
Intelligent Program
AlO -
Blank Check Zeros
AlO -
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Notes:
7. X = "don't care" but not to exceed Vee +5%.
CS3
CS2
CSI
PGM
VFY
Vpp
D7 - Do
VIH
VIH
VIL
07 - 00
X
X
VIH
HighZ
HighZ
07 - 00
X
VIL
X
VIL
X
X
HighZ
VILP
VIHP
Vpp
D7 - Do
VIHP
VILP
Vpp
07 - 00
VIHP
VIHP
Vpp
HighZ
VILP
VIHP
Vpp
D7 - Do
VIHP
VILP
Vpp
Zeros
8.
The power-down mode for the CY7C293A is activated by deselecting
CSl·
DIP
Top View
LCC/PLCC (Opaqe Only)
Top View
)f;f<~ ?;f~
Vce
As
As
A10
Vpp
:I
32,"1: 282726"
5
25 A10
A3 6
7C291 A
24 Vpp
A27
023VF?
A1 8
22 PGM
Ao 9
21
NC
NC 10
7C293A
20 07
Do 11
19 0 6
"
12131415161718
~
VFV
PGM
07
06
05
04
,... NO t)
M
~
It)
OOzzOOO
Cl
03
C291A-9
C291A-8
Figure 1. Programming Pinouts
3-170
CY7C291A
CY7C292NCY7C293A
. . ~~
,
SEMICONDUCTOR
1Ypical DC and AC Characteristics
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.2
1.2
w
:::2:
u1.4
.2
/
Cl
w
N
::J
1.2
/
«
:::2:
a: 1.0
0
z
0.8
1/
0.6
4.0
V
~ 1.0
Cl
w
w
«
a:
z
SUPPLY VOLTAGE
•
~
0.8
en
::E
o
a::
::J
~
0.9
a:
I
5.5
~
N
0
5.0
~
w
:::2:
= 25°C f = fMAX
~
()
~
Cl
N
::J 1.0
TA
4.5
i=
~ 1.1
oz
0~5~5------~25~--------~125
6.0
0.6
TA = 25°C
I
0.4
4.0
4.5
AMBIENT TEMPERATURE (0C)
M
D.
5.0
5.5
6.0
M
SUPPLY VOLTAGE
C291A-10
NORMALIZED ACCESS TIME
vs. TEMPERATURE
w
1.6
S
:::2:
i=
(J)
(J)
I-
zw
1.4
«
N
::J
50
25.0
"'-
" "-
w
30
a:
()
Cl
w
30.0
()
1.2
::>
0
1.0
«
I-
0
I-
a: 0.8
~
:::
::>
a.. 10
z
::>
0
0.6
- 55
o
125
25
o
1.0
S
I-
'/
75
~ 50
a..
I-
25
o
5.0
4.0
.,V
/V
1/
= 4.5V
= 25°C
Vee
TA
I
200
M
1.00
I..---
a:
5
V
./
400
600
_
I
800 1000
CAPACITANCE (pF)
Icc vs. CYCLE PERIOD
150
5 100
z
15.0
v
1.02
~ 125
Ci5
3.0
20.0
~ 10.0
'"'"
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
z
~
2.0
~
OUTPUT VOLTAGE
AMBIENT TEMPERATURE (OC)
« 175
-
,,~
20
(J)
:::2:
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
60
a:
a:
::> 40
w
()
()
OUTPUT SOURCE CURRENT
vs.VOLTAGE
«
/
./
V
----
Cl
w
N
::J
J
Vee = 5.0V
TA = 25°C -
1.0
2.0
3.0
OUTPUT VOLTAGE
0.92
z
I
Vee = 5.5V
TA = 25°C
~
0.90
[7
0.0
0.94
0
a:
r\
'\.
0.96
«
:::2:
1
\
u
.2 0.98
-
0.88
4.0
o
M
25
50
75
CYCLE PERIOD (ns)
3-171
100
C291A-11
CY7C291A
CY7C292A/CY7C293A
=*==,:7~PRE§
SEMICONDUCfOR
Ordering Information[9]
Speed Icc
(ns)
(rnA)
Ordering Code
Package
Name
20
120
25
60
CY7C291A-2OJC
CY7C291A - 20PC
CY7C291A - 20SC
CY7C291A - 20WC
CY7C291AL- 25JC
CY7C291AL- 25PC
CY7C291AL- 25WC
CY7C291A:"'" 25JC
CY7C291A - 25PC
CY7C291A - 25SC
CY7C291A - 25WC
CY7C291A-25DMB
CY7C291A - 25LMB
CY7C291A - 250MB
CY7C29iA - 25TMB
CY7C291A - 25WMB
CY7C291A-30DMB
CY7C291A - 30LMB
CY7C291A -300MB
CY7C291A - 30TMB
CY7C291A - 30WMB
CY7C29iAL-35JC
CY7C291AL-35PC
CY7C291AL-35WC
CY7C291A - 35SC
CY7C291A - 35PC
CY7C291A - 35WC
CY7C291A - 35DMB
CY7C291A - 35LMB
CY7C291A - 350MB
CY7C291A - 35TMB
CY7C291A - 35WMB
CY7C291AL-50JC
CY7C291AL-50PC
CY7C291AL-50WC
CY7C291A -50SC
CY7C291A-50PC
CY7C291A -50WC
CY7C291A-50DMB
CY7C291A -50LMB
CY7C291A-500MB
CY7C291A - 50TMB
CY7C291A -50WMB
J64
P13
S13
W14
J64
P13
W14
J64
P13
S13
W14
D14
L64
064
T73
W14
D14
L64
064
T73
W14
J64
P13
W14
S13
P13
W14
D14
L64
064
T73
W14
J64
P13
W14
S13
P13
W14
D14
L64
064
T73
W14
90
120
30
120
35
60
90
120
50
60
90
90
Package 1Ype
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOIC
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead Windowed Cerpack
24-Lead (300-Mil) Windowed CerDIP
Note:
9. Most of these products are available in industrial temperature range.
Contact a Cypress representative for specifications and product availability.
3-172
Operating
Range
Commercial
Commercial
Military
Military
Commercial
Commercial
Military
Commercial
Commercial
Military
"
CY7C291A
CY7C292A/CY7C293A
::~
_ " . i l l CYPRESS
-iF
SEMICONDUcrOR
Ordering Information[9] (continued)
Speed Icc
(ns) (rnA)
20
25
30
35
50
120
Package
Name
Package 1YPe
CY7C292A -20DC
D12
24-Lead (600-Mil) CerDIP
CY7C292A - 20PC
PH
24-Lead (600-Mil) Molded DIP
CY7C292A -25DC
D12
24-Lead (600-Mil) CerDIP
CY7C292A - 25PC
PH
24-Lead (600-Mil) Molded DIP
Operating
Range
Commercial
CY7C292A-25DMB
D12
24-Lead (600-Mil) CerDIP
Military
120
CY7C292A - 30DMB
D12
24-Lead (600-Mil) CerDIP
Military
60
CY7C292AL-35PC
PH
24-Lead (600-Mil) Molded DIP
Commercial
•
90
CY7C292A - 35DC
D12
24-Lead (600-Mil) CerDIP
Commercial
Q.
CY7C292A - 35PC
PH
24-Lead (600-Mil) Molded DIP
120
CY7C292A - 35DMB
D12
24-Lead (600-Mil) CerDIP
Military
60
CY7C292AL-50PC
PH
24-Lead (600-Mil) Molded DIP
Commercial
Commercial
120
90
120
Speed Icc
(ns) (rnA)
20
120
25
120
30
120
35
60
90
90
50
Ordering Code
60
90
90
CY7C292A - 50DC
D12
24-Lead (600-Mil) CerDIP
CY7C292A - 50PC
PH
24-Lead (600-Mil) Molded DIP
CY7C292A-50DMB
D12
24-Lead (600-Mil) CerDIP
Ordering Code
Package
Name
CY7C293A - 20PC
CY7C293A -20WC
CY7C293A -25PC
CY7C293A -25WC
CY7C293A-25DMB
CY7C293A -25LMB
CY7C293A -250MB
CY7C293A -25WMB
CY7C293A - 30DMB
CY7C293A - 30LMB
CY7C293A - 300MB
CY7C293A - 30WMB
CY7C293AL-35PC
CY7C293AL-35WC
CY7C293A - 35PC
CY7C293A - 35WC
CY7C293A - 35DMB
CY7C293A - 35LMB
CY7C293A - 350MB
CY7C293A - 35WMB
CY7C293AL- 50PC
CY7C293AL-50WC
CY7C293A - 50PC
CY7C293A - 50WC
CY7C293A - 50DMB
CY7C293A - 50LMB
CY7C293A - 500MB
CY7C293A - 50WMB
P13
W14
P13
W14
D14
L64
064
W14
D14
L64
064
W14
P13
W14
P13
W14
D14
L64
064
W14
P13
W14
P13
W14
D14
L64
064
W14
Package lYpe
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
28-Pin Windowed Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
3-173
Commercial
Military
Operating
Range
Commercial
Commercial
Military
Military
Commercial
Commercial
Military
Commercial
Commercial
Military
o
:=E
oa:
CY7C291A
CY7C292A/CY7C293A
fW!cYPRfSS
~
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
IIX
Ioz
Icc
ISB[lO]
Switching Characteristics
Parameter
Subgroups
tAA
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tACSl[ll]
tACS2[lO]
Notes:
10. 7C293A only.
11. 7C291A and 7C292A only.
Document #: 38-00075-G
SMD Cross Reference
SMD
Number
5962-87650
5962-87650
5962-87650
5962-87650
5962-87650
5962-87650
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88680
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
5962-88734
3-174
Suffix
01KX
01LX
013X
03KX
03LX
033X
01LX
01KX
013X
02LX
02KX
023X
03LX
03KX
033X
04LX
04KX
043X
02JX
02KX
02LX
023X
03JX
03KX
03LX
033X
04JX
04KX
04LX
043X
Cypress
Number
CY7C291-50TMB
CY7C291-50WMB
CY7C291-500MB
CY7C291- 35TMB
CY7C291-35WMB
CY7C291-350MB
CY7C293A - 50WMB
CY7C293A - 50TMB
CY7C293A - 500MB
CY7C293A - 35WMB
CY7C293A - 35TMB
CY7C293A - 350MB
CY7C293A - 30WMB
CY7C293A - 30TMB
CY7C293A - 300MB
CY7C293A - 25WMB
CY7C293A - 25TMB
CY7C293A - 250MB
CY7C292A-45DMB
CY7C291A -45KMB
CY7C291A -45DMB
CY7C291A-45LMB
CY7C292A - 35DMB
CY7C291A - 35KMB
CY7C291A - 35DMB
CY7C291A - 35LMB
CY7C292A-25DMB
CY7C291A - 25KMB
CY7C291A-25DMB
CY7C291A - 25LMB
PROM Programming Information
CYPRESS
SEMICONDUCTOR
Introduction
PROMs or Programmable Read Only Memories have existed
since the early 1970s and continue to provide the highest-speed
non-volatile form of semiconductor memory available. Until the
introduction of CMOS PROMs from Cypress, all PROMs were
produced in bipolar technology, because bipolar technology provided the highest possible performance at an acceptable cost level. All bipolar PROMs use a fuse for the programming element.
The fuses are intact when the product is delivered to the user,
and may be programmed or written once with a pattern and used
or read infinitely. The fuses are literally blown using a high current supplied by a programming system. Since the fuses may only
be blown or programmed once, they may not be programmed
during test. In addition, since they may not be programmed until
the user determines the pattern, they may not be completely
tested prior to shipment from the supplier. The result of this inability to completely test is less than 100% yield during programming by the customer for two reasons. First, some percentage of
the product fails to program. These devices fall out during the
programming operation. Additional yield is lost because the device fails to perform even though it programs correctly. This failure is normally due to the device being too slow. This is a more
subtle failure, and can only be found by 100% post program AC
testing, or by trouble shooting an assembled board or system.
Cypress CMOS PROMs use an EPROM programming mechanism. This technology has been in use in MOS technologies
since the late 1970s. However, as with most MOS technologies
the emphasis has been on density, not performance. CMOS at
Cypress is as fast as or faster than bipolar and, coupled with
EPROM, becomes a viable alternative to bipolar PROMs
from a performance point of view. In the arena of programming, EPROM has some significant advantages over fuse technology. EPROM cells are programmed by injecting charge on
an isolated gate, which permanently turns off the transistor.
This mechanism can be reversed by irradiating the device with
ultraviolet light. The fact that programming can be erased totally changes the testing and programming situation and philosophy. All cells can be programmed during the manufacturing process and then erased prior to packaging and subsequent
shipment. When these cells are programmed, the performance
of each cell in the memory can be tested, ensuring that we ship
devices that program every time and will perform as specified
when programmed. In addition, when these devices are
supplied in a windowed package they can be programmed and
erased indefinitely providing the designer a reprogrammable
PROM for development.
Programmable Technology
EPROM Process Technology
EPROM technology employs a floating or isolated gate between
the normal control gate and the source/drain region of a transistor. This gate may be charged with electrons during the programming operation and when charged with electrons, the transistor is
permanently turned off. When uncharged (the transistor is unprogrammed) the device may be turned on and off normally with
the control gate. The state of the floating gate, charged or uncharged, is permanent because the gate is isolated in an extremely pure oxide. The charge may be removed if the device is irradiated with ultraviolet energy in the form of light. This ultraviolet
light allows the electrons on the gate to recombine and discharge
the the gate. This process is repeatable and therefore can be used
during the processing of the device repeatedly if necessary to assure programming function and performance.
Programming Algorithm
Byte Addressing and Programming
•
All Cypress CMOS PROMs are addressed and programmed on a
byte basis, unlike the bipolar products that they replace. The address lines used to access the memory in a read mode are the U)
same for programming, and the address map is identical. The in- ::E
formation to be programmed into each byte is presented on the 0
data-out pins during the programming operation, and the data is a::
read from these same pins for verification that the byte has been D.
programmed.
Blank Check for Differential Cells
Since a differential cell contains neither a 1 not a 0 before it is
programmed, the conventional blank check is not valid. For this
reason, Cypress CMOS PROMs that use differential cells contain
a special blank check mode of operation. Blank check is performed by separately examining the 0 and 1 sides of the differential memory cell to determine whether either side has been independently programmed. This is accomplished in two passes: one
comparing the 0 side of the differential cell against a reference
voltage applied to the opposite side of the sense amplifier, and
then repeating this operation for the 1 side of the cell. The modes
are called blank check ones and blank check zeros. These modes
are entered by applying a supervoltage to the device.
Blank Check for Single-Ended Cells
Single-ended cells blank check in a conventional manner. An
erased device contains all Os and a programmed cell will contain a
1. Cypress PROMs that use the single-ended approach provide a
specific mode to perform the blank check, which also provides
the verify function. This makes the need to switch high voltages
unnecessary during the program verify operation. See specific datasheets for details.
Programming the Data Array
Programming is accomplished by applying a supervoltage to one
pin of the device causing it to enter the programming mode of
operation. This also provides the programming voltage for the
cells to be programmed. In this mode of operation, the address
lines of the device are used to address each location to be programmed, and the data is presented on the pins normally used for
reading the contents of the device. Each device has a read and
write pin in the programming mode. These are active-LOW signals and cause the data on the output pins to be written into the
addressed memory location in the case of the write signal or read
out of the device in the case of the read signal. When both the
read and write signals are HIGH, the outputs are disabled and in
a high-impedance state. Programming therefore is accomplished
by placing data on the output pins, and writing it into the addressed location with the write signal. Verification of data is accomplished by reading the information on the output pins while
the read signal is active.
The timing for actual programming is supplied in the unique programming specifications for each device.
Special Features
Depending on the specific CMOS PROM in question, additional
features that require programming may be available to the designer. Two of these features are a Programmable Initial Byte
3-175
PROM Programming Information
and Programmable Synchronous/Asynchronous Enable available
in some of the registered devices. Like programming the array,
these features make use of EPROM cells and are programmed in
a similar manner using supervoltages. The specific timing and
programming requirements are specified in the data sheet of the
device employing the feature.
Programming Support
Programming support for Cypress CMOS PROMs is available on
Cypress's QuickPro II. Support is also available from a number
of programmer manufacturers, some of which are listed below.
AVAL Data Corp.
M. K. Bldg. 2F 4-8 Nakaitabashi,
Itabashi - ku
Tokyo, Japan 173
03 (5375) -7321
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054
(408) 988-1118
System General
510 S. Park Victoria
Milpitas, CA 95035
(408) 263-6667
Document #: 38-00235
BP Microsystems
10681 Haddington, Ste. #190
Houston, TX 77043
(800) 225-2102
Cypress Semiconductor, Inc.
3901 North First St.
San Jose, CA 95134
(408) 943-2600
Data I/O
Customer Resource Center
10525 Willows Rd. NE
P.O. Box 97046
Redmond, WA 98073-9746
(800) 247-5700
(206) 881-6444
Logical Devices Inc.
692 South Military Trail
Deerfield, FL 33442
(305) 428-6868
Micropross
Parc d'Activite des Pres
5, rue Denis-Papin
59650 Villenueve-d'Ascq. France
(20) 47.90.40
Minato Electronics
4105, Minami Yamada-cho
Kohoku-ku
Yokohama, Japan 223
(045) 591-5611
SMS Mikrocomputersystem GmbH
1m Grund 15
D - 7988 Wangen im Allgeau
BRD
(49) 7522-5018
SMS Microcomputer
P.O. Box 1348
Lawrence,MA 01842
(508) 683-4659
3-176
INFO
Ii
SRAMs
fl
PROMs
"
PlDs
FIFOs
I'
'i
lOGIC
II
DATACOM
Ii
MODULES
.:1
ECl
MiliTARY
I
I
I
TOOLS
1&
QUALITY
IE
II
BUS
PACKAGES
Section Contents
PLDs (Programmable Logic Devices)
Page Number
Introduction to Cypress PLDs .............................................................................. 4-1
Device Number
CY7C258
CY7C259
PLDC18G8
PALC20 Series
PAL20 Series
PLDC20G10
PLDC20GlOB
PLDC20GlOC
PLDC20RA10
PALC22VlO
PALC22VlOB
PAL22V10C
PAL22VPlOC
PAL22VlOCF
PAL22VPlOCF
PALC22VlOD
PAL22VlOG
PAL22VPlOG
CY7C330
CY7C331
CY7C332
CY7C335
CY7C340 EPLD Family
CY7C341
CY7C341B
CY7C342
CY7C342B
CY7C343
CY7C344
CY7C361
FLASH370 PLD Family
CY7C371
CY7C372
CY7C373
CY7C374
CY7C375
CY7C376
CY7C377
pASIC380 Family
CY7C381
CY7C382
CY7C383
CY7C384
CY7C385A
CY7C386A
PLD Programming Information
Description
2Kx 16 Reprogrammable State Machine PROM ................................... 4-6
2Kx 16 Reprogrammable State Machine PROM ................................... 4-6
CMOS Generic 20-Pin Programmable Logic Device ................................ 4-7
Reprogrammable CMOS PALC 16L8, 16R8, 16R6, 16R4 . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
4.5-ns, Industry-Standard, PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-18
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 4-28
CMOS Generic 24-Pin Reprogrammable Logic Device ............................. 4-28
Generic 24-Pin PAL Device .................................................... 4-36
Reprogrammable Asynchronous CMOS Logic Device ............................. 4-46
Reprogrammable CMOS PAL Device ........................................... 4-57
Reprogrammable CMOS PAL Device ........................................... 4-67
Universal PAL Device ........................................................ 4-76
4-76
Universal PAL Device
4-87
Universal PAL Device
Universal PAL Device ........................................................ 4-87
Flash Erasable, Reprogrammable CMOS PAL Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-97
Universal PAL Device ....................................................... 4-105
Universal PAL Device ....................................................... 4-105
CMOS Programmable Synchronous State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-114
Asynchronous Registered EPLD .............................................. 4-115
Registered Combinatorial EPLD .............................................. 4-129
Universal Synchronous EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-130
Multiple Array Matrix High-Density EPLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-145
192-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-150
192-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-150
128-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-166
128-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-166
64-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-182
32-Macrocell MAX EPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-194
Ultra High Speed State Machine EPLD ........................................ 4-204
High-Density Flash PLDs .................................................... 4-217
32-Macrocell Flash PLD ..................................................... 4-224
64-Macrocell Flash PLD ..................................................... 4-232
64-Macrocell Flash PLD ..................................................... 4-240
4-248
128-Macrocell Flash PLD
4-256
128-Macrocell Flash PLD
4-265
256-Macrocell Flash PLD
256-Macrocell Flash PLD .................................................... 4-266
Very High Speed CMOS FPGAs .............................................. 4-267
Very High Speed 1K (3K) Gate CMOS FPGA ................................... 4-274
Very High Speed 1K (3K) Gate CMOS FPGA ................................... 4-274
Very High Speed 2K (6K) Gate CMOS FPGA ................................... 4-281
Very High Speed 2K (6K) Gate CMOS FPGA ................................... 4-281
Very High Speed 4K (12K) Gate CMOS FPGA .................................. 4-288
Very High Speed 4K (12K) Gate CMOS FPGA .................................. 4-288
......................................................... , ................... 4-289
Introduction to Cypress PLDs
Cypress PLD Family Features
Cypress Semiconductor's PLD family offers the user a wide range
of programmable logic solutions that incorporate leading-edge circuit design techniques as well as diverse process technology capabilities. This allows Cypress PLD users to select PLDs that best suit
the needs of their particular high-performance system, regardless
of whether speed, power consumption, density, or device flexibility
are the critical requirements imposed by the system.
Cypress offers enhanced-performance industry-standard 20- and
24-pin device architectures, proprietary 2S-pin application-tailored architectures and highly flexible 2S- to S4-pin universal device architectures. The range of technologies offered includes leading-edge O.S-micron CMOS EPROM for high speed, low power,
and high density, O.S-micron bipolar for the highest-speed ECLdevices, O.S-micron BiCMOS for high-speed, power-sensitive applications, and O.65-micron FLASH technology for high speed, low
power and electrical alterability.
The reprogrammable memory cells used by Cypress serve the same
purpose as the fuse used in most bipolar PLD devices. Before programming, the AND gates or product terms are connected via the
reprogrammable memory cell to both the true and complement inputs. When the reprogrammable memory cell is programmed, the
inputs from a gate orproduct term are disconnected. Programming
alters the transistor threshold of each cell so that no conduction
can occur, which is equivalent to disconnecting the input from the
gate or product term. This is similar to "blowing" the fuses of BiCMOS or bipolar fusible devices, which disconnects the input gate
from the product term. Selective programming of each of these reprogrammable memory cells enables the specific logic function to
be implemented by the user.
The programmability of Cypress's PLDs allows the users to customize every device in a number of ways to implement their unique
logic requirements. Using PLDs in place of SSI or MSI components results in more effective utilization of board space, reduced
cost and increased reliability. The flexibility afforded by these
PLDs allows the designer to quickly and effectively implement a
number oflogic functions ranging from random logic gate replacement to complex combinatorial logic functions.
The PLD family implements the familiar "sum of products" logic
by using a programmable AND array whose output terms feed a
fixed OR array. The sum of these can be expressed in a Boolean
transfer function and is limited only by the number of product
terms available in the AND-OR array. A variety of different sizes
and architectures are available. This allows for more efficient logic
optimization by matching input, output, and product terms to the
desired application.
PLD Notation
To reduce confusion and to have an orderly way of representing the
complex logic networks, logic diagrams are provided for the various part types. In order to be useful, Cypress logic diagrams
employ a common logic convention that is easy to use. Figure 1
shows the adopted convention. In part ( a), an " x" represents an
unprogrammed EPROM cell or intact fuse link that is used to perform the logical AND operation upon the inputterms. The convention adopted does not imply that the input terms are connected on
the common line that is indicated. A further extension of this convention is shown in part (b), which shows the implementation of a
simple transfer function. The normal logic representation of the
transfer function logic convention is shown in part (c).
PLD Circuit Configurations
Cypress PLDs have several different output configurations that
cover a wide spectrum of applications. The available outputconfigurations offer the user the benefits of both lower package counts
and reduced costs when used. This approach allows designers to select PLDs that best fit their applications. An example of some of
the configurations that are available are listed below.
Programmable I/O
Figure 2 illustrates the programmable I/O offered in the Cypress
PLD family that allows product terms to directly control the outputs of the device. One product term is used to directly control the
three-state output buffer, which then gates the summation of the
remaining terms to the output pin. The output of this summation
can be fed back into the PLD as an input to the array. This programmable I/O feature allows the PLD to drive the output pin
when the three-state output is enabled or, when the three-state
output is disabled, the I/O pin can be used as an input to the array.
INTRO-1
(a)
INTRO-2
(b)
INTRO-3
(c)
Figure 1. Logic Diagram Conventions
4-1
II
~
..J
Q.
-===: :~
Introduction to Cypress PLDs
~=CYPRESS
~, SE,MICONDUcrOR
INPUTS FEEDBACK, AND /0
1--111
!I!lIIIIIIIIIIIIIIIIIII~Jl/o
INTRO-4
Figure 2. Programmable I/O
INPUTS, FEEDBACK, AND I/O
CLOCK
-.
~
>-
r-----
I-
D
QI--
~
o--Q
~~1
......
INTRO-5
Figure 3. Registered Outputs with Feedback
Registered Outputs with Feedback
Figure 3 illustrates the registered outputs of!ere.d on a nUI?ber of
the Cypress PLDs which allow any 0f these CIrcUIts to f~nctIon as. a
state sequencer. The summation of the product terms IS stored m
the D-type output flip-flop on the rising edge of the system clock.
The Q output of the flip-flop can then be gated to the outpu~ pin by
enabling the three-state output buffer. The output of the flIp-flop
can also be fed back into the array as an input term. The output,
feedback feature allows the PLD to remember and then alter its
function based upon that state. This circuit can be used to execute
such functions as counting, skip, shift, and branch.
Programmable Macrocell
The programmable macrocell, illustrated in Figure 4,.pro~i.des the
capability of defining the architecture of e~c~ output !~dI':Iduall~;
Each of the potential outputs may be specIfIed to be ~egI~t~red
or "combinatorial." Polarity of each output may also be mdividually selected allowing complete flexibility of output configuration.
Further configurability is provided through "array" configurable
"output enable" for each potential output. This feature allows the
outputs to be reconfigured as inputs on an individual basis or alternately used as a bidirectional I/O controlled by the programmable
array (see Figure 5).
Buried Register Feedback
The CY7C330 and CY7C331 PLDs provide registers that may be
"buried" or "hidden" by electing feedback of the register output.
These buried registers, which are useful in state machines, may be
implemented without sacrificing the use of the associated devic~
pin as an input. In previous PLDs, when the feedback path was actIvated, the input pin-path to the logic array was blocked. The p~o
prietary CY7C330 reprogram~able sync~ronous st~te mac~llle
macrocell illustrates the shared mput multIplexer, WhICh provIdes
an alternative input path for the I/O oin associated with a buried
macrocell register (Figure 6). Each pair of macrocells shares an in-
put multiplexer, and as long a~ alternate macr~cells ~re buried, up
to six of the twelve output regIsters can be buned WIthout the loss
of any I/O pins as inputs. The CY7C330 also contains four dedicated hidden macrocells with no external output that are used as
additional state registers for creating high-performance state machines (Figure 7).
Asynchronous Register Control
Cypress also offers PLDs that may be used in asynchronous systems in which register clock, set, and reset are controlled by the
outputs of the product term array. Th.e clock signal is created byt~e
processing of external inputs and/or mternal feedback by the lOgIC
ofthe product term array, which is then routed to the register clock.
The register set and reset are similar!y c~ntrolled by product te~
outputs and can be triggered at any tIme mdepen?ent of the regISter clock in response to external and/or feedback mputs process~d
by the logic array. The proprietary CY7C.3~ 1 Asynchr~)llo~s RegI~
tered PLD, for which the I/O macrocellis Illustrated lllFzgure 8, IS
an example of such a device. The register clock, set, and reset functions of the CY7C331 are all controlled by product terms and are
dependent only on input signal timing and combinatorial delay
through the device logic array to enable theit respective functions.
Input Register Cell
Other Cypress PLDs provide input re~ister cells to capture. short
duration inputs thatwould not otherwIse be present at the mputs
long enough to allow the device to respond. Both the proprietary
CY7C330 Reprogrammable Synchronous State Machine and the
proprietary CY7C332 Combinatorial ~LD pro~ide these input
register cells (Figure 9). The clock for the mput regIster may be provided from one of two external clock input pins selectable by a configuration bit, C4, dedicated for this purpose !or each input register. This choice of input register clock allows sIgnals to be captured
and processed from two independent system sources, each controlled by its own independent clock. These inpu~ regist~r cells ~re
provided within I/O macrocells, as well as for dedIcated mput pms.
4-2
Introduction to Cypress PLDs
CLOCK AR
"'"""'
OE
a
I
r-
~>- I-
e~ ...
-f)1
I
.-LL
MACROCELL
~
f-
V
b
SP
I/O
INTRO-6
II
Figure 4. Programmable Macrocell
en
C
..J
~
PIN 14OUTPUT ENBLE (OE)
GLOBAL
SYNCHRONOUS SET
I/O
PIN
GLOBAL
SYNCHRONOUS RESET
MACRO CELL
INPUT REGISTER
INPUT OR FEEDBACK TO LOGIC ARRAY
C1
Q
D~-----l
FEEDBACK
MUX
MACRO CELL
INPUT CLOCK C2
MUX
TO SHARED
MACRO CELL
INPUTMUX
GLOBAL STATE
REGISTER CLOCK
CLK(PIN 1)
Figure 5. CY7C330 I/O Macrocell
4-3
INPUT
CLOCKS CK2
CK1
(PIN 3) (PIN 2)
INTRO-7
.::r:~
~if CYPRESS
Introduction to Cypress PLDs
~, SEMICONDUCTOR
FROM
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
INPUT TO
LOGIC
ARRAY
FEEDBACK
TO LOGIC
ARRAY
FROM
LOGIC
ARRAY
INTRo-a
Figure 6. CY7C330 I/O Macrocell Pair Shared Input MUX
GLOBAL SYNCHRONOUS SET
GLOBAL SYNCHRONOUS RESET
FEEDBACK TO LOGIC ARRAY
GLOBAL STATE
REGISTER CLOCK
CLK(PIN 1)
Figure 7. CY7C330 Hidden State Register Macrocell
4-4
INTRO-9
-
~o
..
~
CYPRESS
_olE
-==:::tII!ttrIF
Introduction to Cypress PLDs
SEMICONDUCTOR
PIN 14 - - - - - /
OE
MUX
SET PRODUCT TERM
S
D
Q
•
~------~
OUTPUT
REGISTER
U)
C
..I
Q.
CLOCK PRODUCT TERM
R
RESET PRODUCT TERM
~
--~,
_ _ _ _ _ _ _~FEEDBACK
MUX
S
Q
D
INPUT
REGISTER
R
INTRO-10
TO SHARED
INPUTMUX
Figure 8. CY7C331 Registered Asynchronous Macrocell
INPUT ~+--------ID
PIN
o
INPUT
CLOCK
MUX
C4
Q
INPUT
REGISTER
INPUT TO
LOGIC
ARRAY
REGISTER INITIALIZED ON POWERUP TO Q EQUAL TO LOGIC LOW
INTRO-11
CK1
(PIN 2)
CK2
(PIN 3)
Figure 9. CY7C330 Dedicated Input Cell
Document #: 38-00165-A
4-5
This is an abbreviated datasheet. The complete
CY7C258/9 data sheet is listed in the PROM
section of this Data Book.
CYPRESS
SEMICONDUCTOR
2K X 16 Reprogrammable
State Machine PROM
Features
Functional Description
• High speed: 100-MHz operation
-tcp = 10 ns
-tCKO = 8 ns
-tAS = 2 ns
• 16-bit-wide state word
• Can be programmed as asynchronous
PROM tAA = 18 ns
• Optimum speed! power
• Individually bypassable input and
output registers
• Individually programmable address/
feedback muxes
• Synchronous and asynchronous chip
select
• Synchronous and asynchronous INIT
and programmable initialize word
• 16 outputs (CY7C259)
• Software support
• CY7C258 available in 28-pin, 300-mil
plastic and ceramic DIP, LCC, PLCC
• CY7C259 available in 44-pin LCC and
PLCC
• Reprogrammable in windowed
packages
• Capable of withstanding greater than
2001V static discharge
The CY7C258 and CY7C259 are 2K x 16
CMOS PROMs specifically designed for
use in state machine applications.
State machines are one of the most common applications for registered PROMs.
The CY7C258 and CY7C259 feature internal state feedback and a variety of programmable features to support lOa-MHz
state machines with as many as 2,048 distinct states.
It is easy to use a PROM as a state machine. Each array location contains output data as well as information fed back
to select the next state. Note that a
PROM is only limited by the number of
array inputs. If a given state machine can
be implemented in the number of inputs/
feedbacks
available (11
on the
CY7C258/259), then it will always fit in
the device. No software minimization is
required.
Among the programmable features of the
CY7C258/CY7C259 are individually bypassable input and output registers. The
registers run off the same clock for pipeline
capability. Each individual register can be
programmed to capture data at the rising
edge of the clock or to be transparent.
The registers at the inputs are useful for
signals that require short set-up times
(tAS = 2 ns). The input register does
introduce a cycle of latency, however. For
signals that directly affect the next state of
the machine, each input register can be
bypassed. Note that the cycle time remains the same (lO-ns min.), even if the
inputs are bypassed.
Registers at the output are used to hold
both state information and output data.
These registers are also bypassable for
maximum flexibility. Occasionally, an
individual output cannot wait for the
next clock edge. These outputs are
sometimes called Mealy outputs, and
can be created by bypassing the appropriate output register.
Since the CY7C258 and CY7C259 contain a 2K array, they each require 11 inputs. Each of these inputs can come from
an input pin or from internal output register feedback. Eleven individually programmable address muxes allow the user
to select the ratio of pin input and state
feedback.
These devices have both an asynchronous
output (OE) and a synchronous chip select (CS).
Logic Block Diagram
Pin Configurations
All REGISTERS
ARE BYPASSABlE
INPUT
REGISTERS
~
CY7C258
CY7C259
OUTPUT
REGISTERS
DIP
Top View
ADDRESS
M~ES
" I~'
lI'Jjf
m:
cs
elK
2Kx 16
PROGRAMMABLE
ARRAY
Do
D1
1,1\
Vee
Vss
A
D2
Vss
Vee
Vss
D3
D4
A19
D5
A20
A21
D6
D7
C258-2
cs
(JE _ _-+_ _ _+-
C2S8-
4-6
PLDC18G8
CYPRESS
SEMICONDUCTOR
Features
Functional Description
• Generic architecture to replace standard logic functions including: 10H8,
12H6, 14H4, 16H2, 101..8, 12L6, 14L4,
16L2, 10P8, 12P6, 14P4, 16P2, 16H8,
161..8, 16P8, 16R8, 16R6, 16R4,
16RP8, 16RP6, 16RP4, 18P8, 16V8
• Fast
- Commercial: tpD = 12 ns,
teo = 10 ns, ts = 10 ns
- Military/lndustrial: tpD = 15 ns,
teo 12 ns, ts 12 ns
=
CMOS Generic 20-Pin
Programmable Logic Device
=
Cypress PLD devices are high-speed electricallyprogrammable logic devices. These
devices utilize thesum-of-products (ANDOR) structure, providing users with the
ability to program custom logic functions
for unique requirements.
In an unprogrammed state, the AND
gates are connected via EPROM cells to
both the true and complement of every
input. By selectively programming the
EPROM cells, AND gates may be connected to either the true or complement
or disconnected from both true and complement inputs.
Cypress PLD C18G8 uses an advanced
D.8-micron CMOS technology and a proven EPROM cell as the programmable
• Eight product terms and one OE
product term per output
• Lowpower
- Icc max. of 110 rnA
• CMOS EPROM technology for
reprogrammability
• Commercial, industrial, and military
temperature range
• User-programmable output cells
- Selectable for registered or
combinatorial operation
- Output polarity control
- Output enable source selectable
from pin 11 or product term
• Highly reliable
- Uses proven EPROM technology
- Fully AC and DC tested
- Security feature prevents logic
pattern duplication
- >2000V input protection for
electrostatic discharge
Logic Block Diagram, DIP and SOJ Pinout
Vss
I/OE
CP/I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Vee
Pin Configurations
18G8-1
PLCC
LCC
Top View
Top View
--~~~
--~~~
I/O
I/O
I/O
I/O
I/O
I/O
1/
lib
1/
III
0
- ~Ig~~
18G8-3
- $Ig ~ ~
4-7
18G8-2
•
1/1
C
...I
Q.
·
.~
~.a CYPRESS
==- 0'
PLDC18G8
SEMICONDUCTOR
Selection Guide
Generic
Part Number
18G8-12
Com'l
90
18G8-15
90
18G8-15L
70
Icc (rnA)
Mil/Ind
18G8-20
tpD
110
(ns)
ts
Com'l
12
MillInd
15
15
tco
Com'l
10
Mil/Ind
Com'l
Mil/Ind
12
12
10
12
12
15
12
110
12
Functional Description (continued)
element. This technology and the inherent advantage of being able
to program and erase each cell enhances the reliability and testability of the circuit, reducing the customer's need to test and to handle
rejects.
A preload function allows the registered outputs to be preset to any
pattern during testing. Preload is important for testing the functionality of the Cypress PLD device.
18G8 Functional Description
The PLDC18G8 is a generic 20-pin device that can be programmed to logic functions which include but are not limited to:
1OR8, 12H6, 14H4, 16H2, 10LS, 12L6, 14L4, 16L2, 10P8, 12P6,
14P4, 16P2, 16H8, 16LS, 16P8, 16R8, 16R6, 16R4, 16RP8, 16RP6,
16RP4, 18P8, 16V8. Thus, the PLDC18G8 provides significant design, inventory, and programming flexibility over dedicated 20-pin
devices. It is executed in a 20-pin, 300:mil molded DIP and a
300-mil windowed cerDIP. It provides up to 18 inputs and 8 outputs. When the windowed cerDIP is exposed to UV light, the 18G8
is erased and can then be reprogrammed.
The programmable output cell provides the capability of defining
the architecture of each output individually. Each ofthe 10 output
cells may be configured with registered or combinatorial outputs,
active HIGH or active LOW outputs, and product term or Pin 11
generated output enables. Four architecture bits determine the
15
15
20
configurations as shown in the Configuration Thble. A total of sixteen different configurations are possible. The default or unprogrammed state is registered/active LOW/Pin 11 OE. The entire
programmable output cell is shown in Figure 1.
Architecture bit C1 controls the registered/combinatorial option.
In either combinatorial or registered configuration, the output can
serve as an I/O pin, or if the output is disabled, as an input only.
Any unused inputs should be tied to ground. In either registered or
combinatorial configuration, the output of the register may be fed
back to the array. This allows the creation of state machines by providing storage and feedback of the current system state. The register is clocked by the signal from Pin 1. The register is initialized
upon power-up to Q output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen with
architecture bit C2. The OE signal may be generated within the
array or from the external OE (Pin 11). Pin 11 allows direct control
of the outputs, hence having faster enable/disable times.
Each output cell can be configured for output polarity. The output
can be either active HIGH or active LOW. This option is controlled
by architecture bit CO.
Along with this increase in functional density, the Cypress
PLDC18G8 provides lower-power operation through the use of
CMOS technology and increased testability with a register preload
feature.
00
1------1
OUTPUT
SELECT
I-t---t---+i
MUX
01
CP
INPUT/
FEEDBACK
MUX
I
I
I
- - - - -I
PIN 11
Figure 1. Programmable Output Cell
4-8
18G8-4
"- -~CYPRF.SS
_"=
F
PLDC18G8
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65 ° C to + 150 ° C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .. . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Output Current into Outputs (LOW) .............. 24 rnA
DC Programming Voltage ......................... 13.0V
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883 Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Ambient
Temperature
Range
O°C to +7SoC
Vee
5V±5%
Industrial
- 40°C to +85°C
5V ±1O%
Military[l]
- S5°C to + 125°C
5V ±1O%
Commercial
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)
Description
Parameters
In
Min.
Test Conditions
= - 3.2 rnA
= - 2 rnA
IOL = 24 rnA
IOL = 12 rnA
VOH
Output HIGH Voltage
IOH
Vee = Min.,
VIN = VIH or VIL
IOH
Commercial
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIH or VIL
Commercial
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[2j
Guaranteed Input Logical LOW Voltage for All Inputs[2]
IIX
Input Leakage Current
= 50 rnA Max.
= Max., VOUT = 0.5V[3]
VIN = 0, Vee = Max., lOUT = 0 rnA
Icc
Power Supply Current
0.5
V
0.8
V
-10
+10
[.lA
12.0
13.0
V
- 30
- 90
rnA
70
rnA
90
rnA
110
rnA
+40
[1A
2.0
Vss ~ VIN ~ Vee
Output Short Circuit Current Vee
Commercial -15L
Commercial
-15
-12,
Military/Industrial
Output Leakage Current
Ioz
Vee
V
Military/lndustrial
Input LOW Level
Ise
Units
Military/Industrial
VIH
Programming Voltage @ Ipp
Max.
2.4
VIL
Vpp
= Max., V ss ~ VOUT ~ Vee
- 40
V
Capacitance[4]
Parameters
Input Capacitance
COUT
Output Capacitance
Max.
10
pF
10
pF
TA
Notes:
1. TA is the "instant on" case temperature.
2. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. V OUT = O.SV has
Units
Test Conditions
= 25°C, f = 1 MHz
VIN = 2.0Y, Vee = S.OV
Description
CIN
4.
4-9
II
been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.
C
..J
c..
74
=,s.
PLDC18G8
IE CYPRESS
~, Sa1ICONDUcrOR
AC Test Loads and Waveforms
R1 160n
R1 1600
OUTP~~ ~1~~
j~8~~~NG
I-=
50 pF
5V:F1(31
MIIjIND)
9n
R2
OUTPUT
124n
(236n
-=
j~8~~~NG
MIIjIND)
SCOPE
SCOPE
I
MIIjIND)
18G8·S
I
THEVENIN EQUIVALENT (Commercial)
Equivalent to:
70,0.
OUTPUT ~ 2.18V
-=
(b)
(a)
Equivalent to:
J.
R2
124n
(236n
5 F
p
THEVENIN EQUIVALENT (Military/Industrial)
136,0.
OUTPUT ~ 2.13V
18G8·S
18G8.7
Configuration Table[5]
Configuration
C3
C2
Cl
Co
0
0
0
0
0
0
0
1
Active HIGH, Registered Mode, Registered Feedback, Pin 11 OE
0
0
1
0
Active LOW, Combinatorial Mode, Registered Feedback, Pin 11 OE
0
0
1
1
Active HIGH, Combinatorial Mode, Registered Feedback, Pin 11 OE
0
1
0
0
Active LOW, Registered Mode, Registered Feedback, Product Term OE
0
1
0
1
Active HIGH, Registered Mode, Registered Feedback, Product Term OE
0
1
1
0
Active LOW, Combinatorial Mode, Registered Feedback, Product Term OE
Active LOW, Registered Mode, Registered Feedback, Pin 11 OE
0
1
1
1
Active HIGH, Combinatorial Mode, Registered Feedback, Product Term OE
1
0
0
0
Active LOW, Registered Mode, Pin Feedback, Pin 11 OE
1
0
0
1
Active HIGH, Registered Mode, Pin Feedback, Pin 11 OE
1
0
1
0
Active LOW, Combinatorial Mode, Pin Feedback, Pin 11 OE
1
0
1
1
Active HIGH, Combinatorial Mode, Pin Feedback, Pin 11 OE
1
1
0
0
Active LOW, Registered Mode, Pin Feedback, Product Term OE
1
1
0
1
Active HIGH, Registered Mode, Pin Feedback, Product Term OE
1
1
1
0
Active LOW, Combinatorial Mode, Pin Feedback, Product Term OE
1
1
1
1
Active HIGH, Combinatorial Mode, Pin Feedback, Product Term OE
Notes:
5. In the virgin or unprogrammed state, a configuration bit is in the "0"
state.
4-10
-,-
.~
_'.CYPRESS
--=-
F
PLDC18G8
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel l , 6, 7]
Commercial
Parameters
Description
Min.
Military/Industrial
-15, ..,..15L
-12
Max.
Min.
Max.
-20
-15
Min.
Max.
Min.
Max. Units
tpD
Input or Feedback to Non-Registered Output
12
15
15
20
ns
tEA
Input to Output Enable
12
15
15
20
ns
tER
Input to Output Disable
12
15
15
20
ns
tpzx
Pin 11 to Output Enable
10
12
12
15
ns
tpxz
Pin 11 to Output Disable
10
10
10
15
ns
teo
Clock to Output
10
12
12
15
ns
ts
Input or Feedback Set-Up Time
tH
tp[8]
Hold Time
0
0
Clock Period
22
24
tWH
Clock High Time
7
8
9
10
ns
tWL
Clock Low Time
8
9
10
11
ns
fMAX[9]
Maximum Frequency
50.0
41.6
41.6
33.3
MHz
12
10
Notes:
6. Part (a) of AC Test Loads and Waveforms is used for all parameters
except tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms
is used for tER, tpzx, and tpxz.
7, The parameters tER and tpxz are measured as the delay from the input disable logic threshold transition to VOH - O.SV for an enabled
HIGH output or VOL + O.5V for an enabled LOW input.
8. ts or minimum guaranteed clock period, is the clock period guaranteed for state machine operation and is calculated from tp = ts + teo.
9.
15
ns
0
0
ns
27
35
ns
12
The minimum guaranteed period for registered data path operation
(no feedback) can be calculated as the greater of (tWH + tWL) or (ts
+ tH).
fMAX, or minimum guaranteed operating frequency, is the operating
frequency guaranteed for state machine operation and is calculated
from fMAX = 1/(ts + teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower
of l/(tWH + twd or l/(ts + tH)'
Switching Waveform
INPUTS I/O,
REGISTERED
FEEDBACK
K"'7'1""ft'"""7'l""""-
~"'-K....v...v
CP
REGISTERED
OUTPUTS _ _ _ _ _ _""-1<""""'__
tEA
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _--"~~~
18G8,8
4-11
II
In
C
..J
a..
~PRFSS
~;
PLDC18G8
SEMICONDUCTOR
Functional Logic Diagram
INPUT LINES
-ri>
0
4
6
12
16
20
24
26
32
r---
DE
0
··
")-
~
~ I-
··
~7
>- I>
OUTPUT l -
:2
a:::
w
I-
4
b::>
Cl
··
~7
>- I>
0..
5
··
~7
OUTPUT l -
)---
l-
~ I-
")-
OUTPUT ICELL
t>
<1..........
··
~7
t-
~ I-
IJ---- I>OUTPUT
CELL t-
<1~""
DE
0
---J')
OUTPUT I-
~ CELL
<.:1-
DE
0
9
l-
~ I-
--f)7
8
CELL
<1-
·
---f')7
··
---t:>7
l-
>- I>
·
7
l-
CELL
~ I-
DE
0
6
OUTPUT
<1-
DE
0
oa:::
l-
~ I-
DE
0
CJ)
CELL
<1-
DE
0
3
f-
19
OUTPUT
CELL I-
<1~
~
~
18
17
~,
~,
~,
~,
~,
6
5
4
3
2
~~
11
18G8-9
4-12
===,~~PRESS
PLDC18G8
.
SEMICONDUCTOR
Ordering Information
(rnA)
ICC
Speed
(ns)
90
12
70
90
110
110
110
110
15
15
15
15
20
20
Ordering Code
Operating
Range
Package lYPe
PLDC18G8-12JC
J61
20-Lead Plastic Leaded Chip Carrier
PLDC18G8-12PC
P5
20-Lead (300-Mil) Molded DIP
PLDC18G8-12VC
V5
20-Lead (300-Mil) Molded SOJ
PLDC18G8-12WC
W6
20-Lead (300-Mil) Windowed CerDIP
PLDC18G8L-15JC
J61
20-Lead Plastic Leaded Chip Carrier
PLDC18G8L-15PC
P5
20-Lead (300-Mil) Molded DIP
PLDC18G8L-15VC
V5
20-Lead (300-Mil) Molded SOJ
PLDC18G8L-15WC
W6
20-Lead (300-Mil) Windowed CerDIP
PLDC18G8-15JC
J61
20-Lead Plastic Leaded Chip Carrier
PLDC18G8-15PC
P5
20-Lead (300-Mil) Molded DIP
PLDC18G8-15VC
V5
20-Lead (300-Mil) Molded SOJ
W6
20-Lead (300-Mil) Windowed CerDIP
J61
20-Lead Plastic Leaded Chip Carrier
PLDC18G8-15PI
P5
20-Lead (300-Mil) Molded DIP
PLDC18G8-15WI
W6
20-Lead (300-Mil) Windowed CerDIP
PLDC18G8-15DMB
D6
20-Lead (300-Mil) CerDIP
PLDC18G8-15LMB
L61
20-Pin Square Leadless Chip Carrier
PLDC18G8-15QMB
Q61
20-Pin WindowedSquareLeadlessChipCarrier
PLDC18G8-15WMB
W6
20-Lead (300-Mil) Windowed CerDIP
PLDC18G8 - 20JI
J61
20-Lead Plastic Leaded Chip Carrier
PLDC18G8 - 20PI
P5
20-Lead (300-Mil) Molded DIP
PLDC18G8- 20WI
W6
20-Lead (300-Mil) Windowed CerDIP
PLDC18G8- 20DMB
D6
20-Lead (300-Mil) CerDIP
PLDC18G8- 20LMB
L61
20-Pin Square Leadless Chip Carrier
PLDC18G8-20QMB
Q61
20-Pin WindowedSquareLeadless Chip Carrier
PLDC18G8- 20WMB
W6
20-Lead (300-Mil) Windowed CerDIP
Subgroups
VOH
tpD
9,10,11
VOL
1,2,3
tpzx
9,10,11
Vm
1,2,3
teo
9,10,11
VIL
1,2,3
ts
9,10,11
IIX
1,2,3
tH
9,10,11
Ioz
1,2,3
Icc
1,2,3
4-13
Industrial
Industrial
Military
1,2,3
Document #: 38-00080-E
Commercial
Military
AC Characteristics
Parameters
Commercial
•
U)
C
~
PLDC18G8-15JI
Subgroups
Commercial
..J
PLDC18G8-15WC
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Package
Name
This is an abbreviated data sheet. Contact a
Cypress representative for complete specifications.
PAL®C20 Series
CYPRESS
SEMICONDUCTOR
Features
• CMOS EPROM technology for reprogrammability
• High performance at quarter power
-tpD = 25 ns
-ts = 20ns
-tco = 15 ns
-Icc = 45mA
• High performance at military
temperature
-tpD = 20 ns
-ts = 20ns
-tco = 15 ns
-Icc = 70mA
• Commercial and military temperature
range
Reprogrammable CMOS
PALC 16L8, 16R8, 16R6, 16R4
• High reliability
- Proven EPROM technology
- > 1500V input protection from electrostatic discharge
-100% AC and DC tested
-10% power supply tolerances
- High noise immunity
- Security feature prevents pattern
duplication
-100% programming and functional
testing
Functional Description
Cypress PALC20 Series devices are highspeed electrically programmable and UVerasable logic devices produced in a proprietary N-well CMOS EPROM process.
These devices utilize a sum-of-products
(AND-OR) structure providing users with
the ability to program custom logic functions serving unique requirements.
PALs are offered in 20-pin plastic and ceramic DIP, plastic SOJ, and ceramic LCC
packages. The ceramic package can be
equipped with an erasure window; when
exposed to UV light, the PAL is erased
and can then be reprogrammed.
Before programming, AND gates or
product terms are connected via EPROM
cells to both true and complement inputs.
Programming an EPROM cell disconnects an input term from a product term.
Selective programming of these cells allows a specific logic function to be implemented in a PALC device. PALC devices are supplied in four functional configurations designated 16R8, 16R6, 16R4,
and 16L8. These 8 devices have potentially 16 inputs and 8 outputs configurable by
the user. Output configurations of 8 registers, 8 combinatorial, 6 registers and 2
combinatorial as well as 4 registers and 4
combinatorial are provided by the 4 functional variations of the product family.
Logic Symbols and DIP and SOJ Pinouts
16R8
16R6
16R4
16L8
Vee
Vee
vee
vee
o
o
o
o
o
o
o
o
I/O
I/O
0
o
o
o
o
o
o
I/O
0
0
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
C20-2
I/O
C20-3
C20-4
LCC Pinouts
u
8
___ :3>0
D..
__ u
:>0
o
o
o
o
o
- $Il!:l- -
C20-5
o
o
o
o
o
- $1l!:l~0
;>4
)5
)6
;>7
;>8
C20-6
PAL is a registered trademark of Monolithic Memories Inc.
4-14
32,1,2019
18
17
16
15
14
910111213
I/O
I/o
I/O
I/O
I/O
-$ -O~
C20-8
·
~~
CYPRF.SS
PALC20 Series
~_
~,
SEMICONDUCTOR
EPROM technology is the basis for a superior product with inherent advantages in reliability, testability, programming, and
functional yield. EPROM technology has the inherent advantage
that all programmable elements may be programmed, tested, and
erased during the manufacturing process. This also allows the device to be 100% functionally tested during manufacturing. An
ability to preload the registers of registered devices during the
testing operation makes the testing easier and more efficient.
Combining these inherent and designed-in features provides an
extremely high degree of functionality, programmability and assured AC performance, and testing becomes an easy task.
The register preload allows the user to initialize the registered devices to a known state prior to testing the device, significantly simplifying and shortening the testing procedure.
Functional Description (continued)
All combinatorial outputs on the 16R6 and 16R4 as well as 6 of
the combinatorial outputs on the 16L8 may be used as optional
inputs. All registered outputs have the Q bar side of the register
fed back into the main array. The registers are automatically initialized upon power-up to Q output LOW and Q output HIGH.
All unused inputs should be tied to ground.
All PALC devices feature a security function that provides the
user with protection for the implementation of proprietary logic.
When invoked, the contents of the normal array may no longer be
accessed in the verify mode. Because EPROM technology is used
as a storage mechanism, the content of the array is not visible under a microscope.
Cypress PALC products are produced in an advanced 1.2-micron
N-well CMOS EPROM technology. The use of this proven
II
U)
Q
..J
a.
Commercial and Industrial Selection Guide
Generic
Part
Number
16L8
16R8
16R6
16R4
Output
Enable
Logic
(8) 7-wide
AND-OR-Invert
(8) 8-wide AND-OR
(6) 8-wideAND-OR
(2) 7-wide
AND-OR-Invert
(4) 8-wideAND-OR
(4) 7-wide
AND-OR-Invert
tpD (ns)
Icc (rnA)
t8 (ns)
teo (ns)
L
Com'l/lnd
-25
-35
-25
-35
-25
-35
45
70
25
35
-
-
-
-
2 Dedicated
Dedicated
Registered Inverting 45
Dedicated
Registered Inverting 45
Programmable Bidirectional
70
70
25
35
20
20
30
30
15
15
25
25
70
25
35
20
30
15
25
Programmable
Outputs
~ 6~ Bidirectional
Dedicated
Registered Inverting 45
Programmable Bidirectional
Military Selection Guide
Generic
Part
Number
16L8
16R8
16R6
16R4
tpD (ns)
Logic
(8) 7-wide
AND-OR-Invert
(8) 8-wide
AND-OR
(6) 8-wide
AND-OR
(2) 7-wide
AND-OR-Invert
(4) 8-wide
AND-OR
(4) 7-wide
AND-OR-Invert
Output
Enable
Icc
t8 (ns)
(rnA)
-20
-30
-40
Programmable ~ 6~ Bidirectional
2 Dedicated
Dedicated
Registered
Inverting
Dedicated
Registered
Inverting
Programmable Bidirectional
70
20
30
40
-
-
-
-
-
-
70
-
-
-
20
25
35
15
20
25
70
20
30
40
20
25
35
15
20
25
Dedicated
70
20
30
40
20
25
35
15
20
25
Outputs
Registered
Inverting
Programmable Bidirectional
4-15
-20
-30
teo (ns)
-40 -20
-30
-40
·
:~
======
iIi CYPRESS
? SEMICONDUCTOR
PALC20 Series
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage to Ground Potential
(Pm 20 to Pin 10) ...................... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 24 mA
DC Programming Voltage ......................... 14.0V
UV Exposure ........................... 7258 Wsec/cm2
Static Discharge Voltage ........................ > 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 mA
Operating Range
Ambient
Temperature
Range
Commercial
Military[l]
O°C to +75°C
Vee
5V ±1O%
- 55°C to + 125°C
5V ±1O%
Industrial
- 40°C to +85°C
Electrical Characteristics Over the Operating Range (unless otherwise noted)[2]
Parameter
VOH
VOL
Test Conditions
Description
Output HIGH Voltage
Output LOW Voltage
= - 3.2mA
IOH = - 2mA
IOL = 24mA
IOL = 12mA
Vee = Min.,
VIN = VIH or VIL
IOH
Vee = Min.,
VIN = VIH or VIL
Min.
Com'l/Ind
2.0
VIL
Input LOW Level
Guaranteed Input Logical LOW[3] Voltage for All Inputs
IIX
Input Leakage Current
Vss~ VIN~ Vee
-10
Vpp
Programming Voltage
Output Short Circuit Current
Ice
Power Supply Current
= 50 mA Max.
= Max., VOUT = O.5V[4]
All Inputs = GND, Vee = Max.,
lOUT = 0 mA[S]
13.0
Ise
V
0.8
V
10
~A
14.0
V
- 300
rnA
"~'
45
mA
Com'IJInd
70
mA
70
mA
100
~
Ipp
Vee
Military
= Max;, Vss~ VOUT~ Vee
V
Military
Guaranteed Input Logical HIGH[3] Voltage for All Inputs
Vee
V
0.4
Com'IJInd
Input HIGH Level
Output Leakage Current
Unit
Military
VIH
loz
Max.
2.4
-100
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
5.
4-16
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5V has
been chosen to avoid test problems caused by tester ground degradation.
ICC(AC) = (0.6 mNMHz)· X (Operating Frequency in MHz) +
IcC(oq. IcC(oC) is measured with an unprogrammed device.
~~~
PALC20 Series
_'=CYPRESS
~.F SEMICONDUcrOR
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[2] (continued)
Parameter
tpxz (-)
Vx
1.5V
tpxz (+)
2.6V
tpzx (+)
Vthc
tpzx (-)
Vthc
tER (-)
1.5V
Output Waveform-Measurement Level
VOH 0.5V
VOL
Vx
Vx
2.6V
tEA (+)
Vthc
tEA (-)
0.5V
VOH
O.5V
O.5V
Vx
0.5V
Vx
C20-9
VX
VOL
Vthc
VX
0.5V
VOH O.5V
tER (+)
t ~
I ~
I ~
t ~
t t:
I ~
I ~
t ~
0.5V
C20-10
C20-11
VOL
C20-12
VX
C20-13
•
en
C
VX
...I
a..
C20-14
VOH
C20-15
VOL
C20-16
Capacitance[6]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
= 25°C, f = 1 MHz
VIN = 0, Vee = 5.0V
TA
Max.
10
Unit
pF
10
pF
Switching Characteristics Over Operating Rangel 2, 7, 8]
Commercial/Industrial
-25
Parameter
Description
Max.
Unit
35
20
30
40
ns
tEA
Input to Output Enable 16L8, 16R6,
16R4
25
35
20
30
40
ns
tER
Input to Output Disable Delay 16L8,
16R6,16R4
25
35
20
30
40
ns
tpzx
Pin 11 to Output Enable 16R8, 16R6,
16R4
20
25
20
25
25
ns
tpxz
Pin 11 to Output Disable 16R8, 16R6,
16R4
20
25
20
25
25
ns
25
ns
15
Max. Min.
25
20
30
Max. Min.
-40
25
Clock to Output 16R8, 16R6, 16R4
Min.
-30
Input or Feedback to Non-Registered
Output 16L8, 16R6, 16R4
Input or Feedback Set-Up Time
16R8, 16R6, 16R4
Max.
-20
tpD
teo
ts
Min.
Military
-35
15
Max. Min.
20
20
25
35
ns
0
ns
tH
tp
Hold Time 16R8, 16R6, 16R4
0
0
0
Clock Period
35
55
35
0
45
60
ns
tw
Clock Width
15
20
12
20
25
fMAX
Maximum Frequency
ns
MHz
28.5
Notes:
6. Tested initially and after any design or process changes that may affect
these parameters.
7. Part (a) (part (c) for military) of AC Test Loads and Waveforms is used
for all parameters except tEA, tER, tpzx and tpxz. Part (b) (part (d) for
military) of AC Test Loads and Waveforms is used for tEA, tER, tpzx
and tpxz.
18
8.
4-17
28.5
22
16.5
The parameters tER and tpxz are measured as the delay from the input
disable logic threshold transition to V OH - O.5V for an enabled HI GH
output or VOL + O.5V for an enabled LOW output. Please see Electrical Characteristics for waveforms and measurement reference levels.
PAL®20 Series
16L8/16R8
16R6/16R4
CYPRESS
SEMICONDUCTOR
4.5-ns, Industry-Standard PLDs
Features
Functional Description
• Ultra high speed supports today's aod
tomorrow's fastest microprocessors
-tpD = 4.5 os
-ts = 2.5 os
-fMAX = 142.9 MHz (external)
• Popular industry standard architectures
• Power-up RESET
• High reliability
- Proven Ti-W fuses
- AC and DC tested at the factory
• Security fuse
Cypress PAL20 Series devices consist of
the PAL16L8, PAL16R8, PAL16R6, and
PAL16R4. Using BiCMOS process and
Ti-W fuses, these devicesimplementthe familiar sum-of-products (AND-OR) logic
structure.
The PAL device is a programmable AND
array driving a fixed OR array. The AND
array is programmed to create custom
product terms while the OR array sums selected terms at the outputs.
The register Q output is set to a logic LOW
when power is applied to the devices.
A security fuse is provided on all the devices to prevent copying of the device fuse
pattern.
Programming
The PAL20 Series devices can be programmed using the QuickPro II programmer available from Cypress Semiconductor and also with Data I/O, Logical Devices, BP Microsystems, Advin, B&C Microsystems, and other programmers.
Please contact your local Cypress representative for further information.
The product selector guide details all the
different options available. All the registered devices feature power-up RESET.
Logic Symbols and DIP Pinouts
16R4
16R6
16R8
16L8
Vee
Vee
vee
o
o
I/O
0
o
o
o
o
o
o
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
o
o
o
o
o
Vss
110E
20-4
20-2
20-Pin PLCC/LCC Pinouts
0
__ _ .Jlo
o
o
o
o
I/O
o
o
o
o
o
o
20-6
20-7
o
o
o
20-5
1/0
1/0
1/0
1/0
1/0
o
-Jl-og
20-8
28-Pin PLCC (-4 Speed Bin Only) Pinouts
o __ _
___ .Jl
Vss
I
CP
OJ:
Vee
0
0
Vss
Vss
0
0
Vss
Vss
o~o~o~o
---~---
0
___ .Jl
___
Vss
OE
I
CP
Vss
I
CP
Vee
OJ:
Vee
I/O
1/0
1/0
I
0
Vee
1/0
Vss
Vss
Vss
Vss
Vss
Vss
1/0
1/0
1/0
1/0
Vss
Vss
Vss
Vss
0
0
Vss
Vss
o~o~o~o
20-10
o rno rno rno
~
PAL is a registered trademark of Monolithic Memories Inc.
4-18
~
.g>
20-11
Vss
o
PAL20 Series
16L8/16R8
16R6/16R4
.. ~
-='=
--=-,
CYPRESS
SEMICONDUCTOR
Function Selection Guide
Enable
Device
Dedicated Inputs
Outputs
Product Terms/Outputs
Feedback
PALI6L8
10
6 comb.
2 comb.
7
7
I/O
-
prog.
prog.
PAL16R8
8
8 reg.
8
reg.
pin
PAL16R6
8
6 reg.
2 comb.
8
7
reg.
I/O
pin
prog.
PAL16R4
8
4 reg.
4 comb.
8
7
reg.
I/O
pin
prog.
•
Speed Selection Guide (Commercial -4/-S/-7, Military -7/-10)
Speed Bin
tpD (ns)
ts (ns)
teo (ns)
fMAX (MHz)
Icc (rnA)
-4
4.S
2.5
4.5
142.9
180
-S
S
2.5
S
133.3
180
-7
7
3.S
6
lOS.3
180
-10
10
4.S
7
87.0
180
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 6SoC to + IS0°C
Ambient Temperature with
Power Applied ....................... - SsoC to + 12SoC
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . .. - O.5V to Vee + O.5V
DC Input Voltage . . . . . . . . . . . . . . . . .. - 1.2V to Vee + O.5V
en
C
...I
~
DC Input Current
(except during programming) ........... - 30 rnA to + S rnA
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
SV±S%
- SsoC to + 12SOC
SV ±10%
Range
Commercial
Military[l]
DC Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Min.
Test Conditions
Description
= - 3.2 rnA
= - 2 rnA
IOL = 24 rnA
IOL = 12 rnA
Vee = Min.,
VIN = VIR or VIL
Vee = Min.,
VIN = VIR or VIL
IOH
Commercial
IOH
Military
Guaranteed Input Logical HIGH Voltage for All Inputs[2]
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for All Inputs[2]
IIX
Input Leakage Current
OAV ~ VIN ~ 2.7V, Vee
II
Maximum Input Current
VIN
Ioz
Output Leakage Current
Output Short Circuit Current
Icc
Power Supply Current
Unit
V
O.S
V
Military
Input HIGH Voltage
Ise
2.4
Commercial
VIR
= MaxJ3]
= S.Sv, Vee = Max.
Vee = Max., Vss ~ VOUT ~ Vee[3]
Vee = Max., VOUT = 0.SV[4]
Vee = Max., VIN = GND, Outputs Open
Max.
2.0
V
0.8
-2S0
V
SO
!lA
1
rnA
-100
+100
!lA
-30
-130
rnA
180
rnA
Notes:
1.
2.
3.
TA is the "instant on" case temperature.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
I/O pin leakage is the worse case of IlL and IOZL (or IIH and IOZH).
4.
4-19
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
PAL20 Series
16L8/16R8
16R6/16R4
~
~~PRESS
~_IF SEMICONDUCTOR
Capacitance[5]
Parameter
Test Conditions
1YPical
Unit
TA = 25°C, f = 1 MHz,
VIN = 0, Vee = 5.0V
8
pF
5
pF
8
pF
Description
Input Capacitance
CIN
I Cp, OE
I 11 -
18
Output Capacitance
COUT
Switching Characteristics Over the Operating Rangel 6]
-5
-4
-10
-7
Description
Min.
Max.
Min.
Max.
tpD
Input or Feedback to Non-Registered Output 16L8,
16R6,16R4
1
4.5
1
5
2
7
tEA
Input to Output Enable 16L8, 16R6, 16R4
2
6.5
2
6.5
2
tER
Input to Output Disable Delay 16L8, 16R6, 16R4
2
5.5
2
5.5
2
tpzx
Pin 11 to Output Enable 16R8, 16R6, 16R4
1
6
1
6
tpxz
Pin 11 to Output Disable 16R8, 16R6, 16R4
1
5
1
teo
Clock to Output 16R8, 16R6, 16R4
1
4.5
1
tSKEWR
Skew Between Registered Outputs 16R8, 16R6,
16R4[5]
ts
Input or Feedback Set-Up Time 16R8, 16R6, 16R4
2.5
2.5
3.5
4.5
ns
tH
tp
Hold Time 16R8, 16R6, 16R4
0
0
0
0
ns
Clock Period (teo + ts)
7
7.5
9.5
11.5
ns
tw
Clock Width
3
3
3.5
5
ns
fMAX
Maximum
Frequency
Parameter
I Internal Feedback[5, 8]
Unit
2
10
ns
7
2
10
ns
7
2
10
ns
2
7
2
10
ns
5
2
7
2
10
ns
5
2
6
2
7
ns
1
ns
1
0.75
I External Feedback (1/tp)[7]
Min. Max. Min. Max.
1
142.9
133.3
105.3
87
175
175
150
133
MHz
Notes:
5. Tested initially and after any design or process changes that may affect
these parameters.
6. See the last page of this specification for Group A subgroup testing information.
7. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
8.
This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal-only feedback can
operate.
AC Test Loads and Waveforms
5V
ls1
f--F
1
OUTPUT
R2
I
-=
TEST POINT
CL
-=
Military
Commercial
Specification
S1
tPD, teo
Closed
tpzx, tEA
Z, H: Open
Z, L: Closed
tpxz, tER
H,
Z: Open
CL
R1
R2
R1
R2
Measured Output Value
50pF
200Q
390Q
390Q
750Q
1.5V
1.5V
H,
5pF
Z: VOH - O.5V
L, Z: VOL + O.5V
L, Z: Closed
4-20
PAL20 Series
16L8/16R8
16R6/16R4
~
-.
1~
---=-,
~=CYPRESS
SEMICONDUCTOR
Switching Waveforms[9]
INPUTS I/O,
REGISTERED
FEEDBACK
~T""ft'''''I''I''''''''
.K...olo~...I."-V
CP
•
U)
REGISTERED ------t"".ft.-,.!'""'!I"..,...
OUTPUTS
--------~~~~
C
..J
Q.
tEA
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _~~~
REGISTERED _ __________t_s_KE_W!lR
f-------OUTPUT 1
REGISTERED
OUTPUT 2
20·13
Note:
9. Input rise and fall time is 2-ns typical.
Power-Up Reset
The power-up reset feature ensures that all flip-flops will be reset
to LOW after the device has been powered up. The output state
will be HIGH due to the inverting output buffer. This feature is
valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways
Parameter Symbol
Vee can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are:
1. The Vee must be monotonic.
2. Following reset, the clock input must not be driven from LOW
to HIGH until all applicable input and feedback set-up times
are met.
Parameter Description
tpR
Power-up Reset Time
ts
Input or Feedback Set-Up Time
tWL
Clock Width LOW
Max.
I
Unit
1000
I
ns
See Switching Characteristics
Power-Up Reset Waveform
POWER
Jt~------------------------- Vee
~
_ _ _ _ _ _ _ _4_V..., ..- - - - - - - - tpR _ _ _ _ _ _ _
~.!
REGISTERED
ACTIVE LOW
OUTPUT
CLOCK
20·14
4-21
PAL20 Series
16L8/16R8
16R6/16R4
~
~4
_'j;
~,
CYPRESS
SEMICONDUCTOR
16L8 Logic Diagram 20-Pin DIPIPLCCILCC (28-Pin PLCC) Pinouts
10
§]
1
0
(24)
3
4
7
8
11
12
15
16
19
20
23 24
27 28
31
0
··
·
.-
~
(25)
Vee
(1,23
rJ
19
08
(22)
<;.1-~
256
··
·
480
3
r
(26)
L
~
512
··
·
736
4
iJ
iJ
18
(20)
L
17
1/0 6
(18)
~
(27)
768
··
·
1---\
'-~
r-.,992
5
r
..?
1024
(28)
··
·
iJ
~248
15
6
..?
r
(2)
1280
-b-J
··
·
'-~
~504
7
(3)
~
1536
iJ
··
·
1760
8
(4)
~
L
1792
rJ
··
·
2016
18
9
A
.....
L
f1Ol-.
1/05
(16)
15
(14)
14
1/03
(12)
13
(10)
12
(8)
11
19
(7)
(5)
Vss
16
3
4
7
8
11
12
15 16
19 20
L....l.J,.
23 24
27 28
31
20-15
(6,9,11,13,15,17,19,21)
4-22
PAL20 Series
16L8/16R8
16R6/16R4
~
--~4
_-=
CYPRESS
--=-
iF
SEMICONDUcrOR
16R8 Logic Diagram 20-Pin DIP/PLCC/LCC (28-Pin PLCC) Pinouts
elK
§] Vee
1
0
(24)
3
4
7
8
11
12
15
16
19
20
23
24
27 28
31
(1,23
0
··
·
L./
0---ti::
(25)
.A
'"
···
~
L/
......480
~
(26)
512
o
.A
So
···
~
L/
736
13
4
(27)
A
."'>.
768
r-:L
···
'""'
92
5
(28)
..A
.... -
So
1024
~
··
·
6
......
2
.... -
.A
So
1280
""\
··
·
(3)
..A
~
So
~
1536
···
(4)
.A
~
So
1792
···
L./
2016
18
9
a.
~
06
(18)
~
=Dl
~
=Dl
~
=Dl
~
=Dl
(16)
03
~
=Dl~
l--
·
··
~16
la
9
~
.
riOL
L......J~
,
~
~
~
~
~
~
~J
,
(5)
Vss
~
~
1536
··
(4)
~
~
1024
··
·
15
(20)
<)..
···
(28)
I/Oa
(22)
~~
··
·
(26)
19
~J
~
(25)
Vee
(1,23
3
4
7
8
11
12
15 16
19
20
23
24
27 28
(18)
(16)
(14)
(12)
(10)
12
(8)
--~-\D>-------i~Q ~
(1
1504
16
7
(3)
--++++-++++-~++_+-H+--HHH~HHH--HH-~rrrr~~
1536
(12)
03
.A
M:tt~tt~======~~r-----~
L
--t+++_+++-i-++++_+~+-~-H~~+-+-IHH~-HH----C)-----.
l~=Utt::ttt::t=U:t:t::t::t:t::t::t:t~~~::t::::t:1~~I:tt:t:::::E~~::t~-<;.A>Jo-..----+---t(~~)
2
1/0
~
'J~~~E~tt~t~~tt~il~~t~il~1~~i3~13~~3~33~3E~3S~S3~~~~SE~EE~3E~EE~E~~~~~~~~~-'~~A~J~----+----1: I/~
18
9
(5)
Vss
~
~
~
'"
-'"
~OE
~~
(7)
34
7
8
11 12
15 16
19 20
23 24
27 28
31
20-18
(6,9,11,13,15,17,19,21)
4-25
•
..J
_ '"
-
PAL20 Series
16L8/16R8
16R6/16R4
~,
~pRF.SS
=='": 7
~., SEMICONDUCTOR
Ordering Information
Package
Name
Package
1YPe
(rnA)
tpD
(ns)
ISO
4.5
PALI6L8-4JC
J64
2S-Lead Plastic Leaded Chip Carrier
5
PALI6L8-5DC
D6
20-Lead (300-Mil) CerDIP
PALI6L8-5JC
J61
20-Lead Plastic Leaded Chip Carrier
PALI6L8-5PC
P5
20-Lead (300-Mil) Molded DIP
PALI6L8-7DC
D6
20-Lead (300-Mil) CerDIP
PALI6L8-7JC
J61
20-Lead Plastic Leaded Chip Carrier
PALI6L8-7PC
P5
20-Lead (300-Mil) Molded DIP
PALI6L8-7DMB
D6
20-Lead (3~0-Mil) CerDIP
ICC
7
10
Icc
Ordering Code
PALI6L8-7LMB
L61
PALI6L8-lODMB
D6
20-Lead (300-Mil) CerDIP
PALI6L8-lOLMB
L61
20-Pin Square Leadless Chip Carrier
Package
1YPe
Package
Name
fMAX
(MHz)
ISO
142.9
PALI6RS-4JC
J64
2S-Lead Plastic Leaded Chip Carrier
133.3
PALI6RS-5DC
D6
20-Lead (300-Mil) CerDIP
PALI6RS-5JC
J61
20-Lead Plastic Leaded Chip Carrier
PALI6RS-5PC
P5
20-Lead (300-Mil) Molded DIP
PALI6RS-7DC
D6
20-Lead (300-Mil) CerDIP
PALI6RS-7JC
J61
20-Lead Plastic Leaded Chip Carrier
PALI6RS-7PC
P5
20-Lead (300-Mil) Molded DIP
PALI6RS-7DMB
D6
20-Lead (300-Mil) CerDIP
PALI6RS-7LMB
L61
20-Pin Square Leadless Chip Carrier
PALI6RS-lODMB
D6
20-Lead (300-Mil) CerDIP
PALI6RS-lOLMB
L61
20-Pin Square Leadless Chip Carrier
105.3
S7
(rnA)
tpD
(ns)
fMAX
(MHz)
ISO
4.5
142.9
PALI6R6-4JC
5
133.3
ICC
7
10
105.3
S7
Ordering Code
Commercial
Military
.)0-Pin Square Leadless Chip Carrier
(rnA)
Ordering Code
Operating
Range
Package
Name
Package
1YPe
J64
2S-Lead Plastic Leaded Chip Carrier
PALI6R6-5DC
D6
20-Lead (300-Mil) CerDIP
PALI6R6-5JC
J61
20-Lead Plastic Leaded Chip Carrier
PALI6R6-5PC
P5
20-Lead (300-Mil) Molded DIP
PALI6R6-7DC
D6
20-Lead (300-Mil) CerDIP
PALI6R6-7JC
J61
20-Lead Plastic Leaded Chip Carrier
PALI6R6-7PC
P5
20-Lead (300-Mil) Molded DIP
PALI6R6-7DMB
D6
20-Lead (300-Mil) CerDIP
PALI6R6-7LMB
L61
20-Pin Square Leadless Chip Carrier
PALI6R6-lODMB
D6
20-Lead (300-Mil) CerDIP
PALI6R6-lOLMB
L61
20-Pin Square Leadless Chip Carrier
4-26
Operating
Range
Commercial
Military
Operating
Range
Commercial
Military
PAL20 Series
16L8/16R8
16R6/16R4
~
.
-=-,.~pRF.SS
SEMlCONDUcrOR
Ordering Information (continued)
Package
Name
Package
1Ype
(rnA)
Icc
tpD
(ns)
180
4.5
142.9
PAL16R4-4JC
J64
28-Lead Plastic Leaded Chip Carrier
5
133.3
PAL16R4-5DC
D6
20-Lead (300-Mil) CerDIP
PAL16R4-5JC
J61
20-Lead Plastic Leaded Chip Carrier
PAL16R4-5PC
P5
20-Lead (300-Mil) Molded DIP
PAL16R4-7DC
D6
20-Lead (300-Mil) CerDIP
PAL16R4-7JC
J61
20-Lead Plastic Leaded Chip Carrier
PAL16R4-7PC
P5
20-Lead (300-Mil) Molded DIP
PAL16R4-7DMB
D6
20-Lead (300-Mil) CerDIP
PAL16R4-7LMB
L61
20-Pin Square Leadless Chip Carrier
PAL16R4-lODMB
D6
20-Lead (300-Mil) CerDIP
PAL16R4-lOLMB
L61
20-Pin Square Leadless Chip Carrier
7
10
fMAX
(MHz)
105.5
87
Ordering Code
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VIL
1,2,3
Irx
1,2,3
Vpp
1,2,3
Icc
1,2,3
Ioz
1,2,3
Switching Characteristics
Parameters
Subgroups
tpD
9,10,11
tpzx
9,10,11
teo
9,10,11
ts
9,10,11
tH
9,10,11
Document #: 38-A-00025-C
4-27
Operating
Range
Commercial
Military
II
U)
C
..J
D.
PLDC20G lOB/PLDC20GIO
CYPRESS
SEMICONDUCTOR
Features
• Fast
- Commercial: tpD = 15 ns, tco = 10
ns, ts 12 ns
- Military: tpD 20 ns, tco 15 ns,
ts=ISns
=
=
=
• Lowpower
- Icc max.: 70 rnA, commercial
- Icc max.: 100 rnA, military
• Commercial and military temperature
range
• User-programmable output cells
- Selectable for registered or combinatorial operation
- Output polarity control
- Output enable source selectable
from pin 13 or product term
CMOS Generic 24-Pin
Reprogrammable Logic Device
• Generic architecture to replace standard logic functions including: 20LI0,
20LS,20R8,20R6,20R4, 12LI0, 14LS,
16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE
product term per output
• CMOS EPROM technology for
reprogrammability
• Highly reliable
- Uses proven EPROM technology
- Fully AC and DC tested
- Security feature prevents logic pattern duplication
- ±10% power supply voltage and
higher noise immunity
Functional Description
Cypress PLD devices are high-speed electrically programmable logic devices. These
devices utilize the sum-of-products (ANDOR) structure providing users the ability
to program custom logic functions for
unique requirements.
In an unprogrammed state the AND
gates are connected via EPROM cells to
both the true and complement of every
input. By selectively programming the
EPROM cells, AND gates may be connected to either the true or complement
or disconnected from both true and complement inputs.
Cypress PLDC20G10 uses an advanced
O.8-micron CMOS technology and a proven EPROM cell as the programmable element. This technology and the inherent
Logic Block Diagram
1/0 9
IJOE
1/07
I/Os
1/0 6
1/03
1/04
1/05
1/02
1/01
Vee
1/00
20G10-1
Pin Configurations
LCC
Top View
--~~~g'~
080
___ Ii:
o§;;;:,;;:,
°z __ Ii: 880'
0;:> :::::-:::::-
NC
1/02
1/03
1/04
1/05
1/0 6
1/0 7
NC
JEDEC PLCC[l)
Top View
STDPLCC
Top View
--Jl~~~~
1/0 2
1/0 3
1/04
1/05
1/0 6
1/0 7
NC
I
NC
I
I
1/0 2
1/0 3
1/04
I
NC
NC
1/0 5
1/0 6
1/07
NC
NC
---Jl~~~
20G10-2
Note:
1. The CG7C323 is the PLDC20GlO packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for
4-28
20G10-4
- - Jl ~~ g g
20G1D-3
both PLCC pinouts. The difference is in the location of the "no connect" or NC pins.
·
.~
~iE CYPRESS
-=-,
PLDC20G 10B/PLDC20G10
SEMICONDUcrOR
Selection Guide
Icc (rnA)
Geoeric
Part Number
Com/lod
20GlOB-15
20GlOB-20
70
70
tpD (os)
Mil
100
20G10B-25
20G10-25
20GlO-30
20GlO-35
ts (os)
Mil
Com/lnd
15
20
12
20
25
12
40
Functional Description (continued)
advantage of being able to program and erase each cell enhances
the reliability and testability of the circuit. This reduces the burden
on the customer to test and to handle rejects.
A preload function allows the registered outputs to be preset to any
pattern during testing. Preload is important for testing the functionality of the Cypress PLD device.
20GIO Functional Description
The PLDC20G10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to:
20LlO, 20LB, 20R8, 20R6, 20R4, 12LlO, 14L8, 16L6, 18L4, 20L2,
and 20V8. Thus, the PLDC20G10 provides significant design, inventory and programming flexibility over dedicated 24-pin devices.
It is executed in a 24-pin 300-mil molded DIP and a 300-mil windowed cerDIP. It provides up to 22 inputs and 10 outputs. When
the windowed cerDIP is exposed to UV light, the 20GlO is erased
and then can be reprogrammed.
The programmable output cell provides the capability of defining
the architecture of each output individually. Each ofthe 10 output
cells may be configured with registered or combinatorial outputs,
active HIGH or active LOW outputs, and product term or Pin 13
generated output enables. Three architecture bits determine the
configurations as shown in the Configuration Table and in Figures
1 through 8. A total of eight different configurations are possible,
15
15
20
20
30
80
Mil
15
15
30
35
20GlO-40
15
teo (os)
Com/lnd
10
18
25
80
55
Mil
12
100
55
Com/lnd
25
35
25
with the two most common shown in Figure 3 and Figure 5. The default or unprogrammed state is registered/active/LOW/pin 11 OE.
The entire programmable output cell is shown in the next section.
The architecture bit 'C1' controls the registered/combinatorial option. In either combinatorial or registered configuration, the output can serve as an I/O pin, or if the output is disabled, as an input
only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register is
fed back to the array. This allows the creation of control-state machines by providing the next state. The register is clocked by the signal from Pin 1. The register is initialized on power up to Q output
LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen with
architecture bit 'C2'. The OE signal maybe generated within the
array, or from the external OE (Pin 13). The Pin 13 allows direct
control of the outputs, hence having faster enable/disable times.
Each output cell can be configured for output polarity. The output
can be either active HIGH or active Law. This option is controlled
by architecture bit 'CO'.
Along with this increase in functional density, the Cypress
PLDC20G 10 provides lower-power operation through the use of
CMOS technology and increased testabilitywith a register preload
feature.
Programmable Output Cell
r---------------------I
I
OE PRODUCT TERM
OUTPUT I
ENABLE
MUX
00
t------I
OUTPUT
SELECT
MUX
""""'1---+--..-1
01
CP
C1
Co
INPUT!
FEEDBACK
MUX
C3
I
I
_ _ _ ..JI
PIN 13
4-29
20G10·5
II
U)
Q
..J
a.
:~
_'=
CYPRESS
_ F
·
PLDC20G10B/PLDC20G10
SEMICONDUcrOR
Configuration Table
Configuration
Figure
C2
Cl
Co
1
0
0
0
Product Term OE/Registered/Active LOW
Product Thrm OE/Registered/Active HIGH
2
0
0
1
5
0
1
0
Product Term OE/CombinatoriallActive LOW
6
0
1
1
Product Term OE/CombinatoriallActive HIGH
3
1
0
0
Pin 13 OE/Registered/Active LOW
4
1
0
1
Pin 13 OE/Registered/Active HIGH
7
1
1
0
Pin 13 OE/CombinatoriallActive LOW
8
1
1
1
Pin 13 OE/CombinatoriallActive HIGH
Registered Output Configurations
D
Cz = 0
Cl = 0
Co = 0
Q
D
Cz = 0
Cl = 0
Co = 1
Q
20G10·6
20G10·7
Figure 1. Product Term OE/Active LOW
Figure 2. Product Term OE/Active HIGH
=1
=0
Co = 1
Cz = 1
Cl = 0
Co = 0
Cz
Cl
Figure 4. Pin 13 OE/Active HIGH
Figure 3. Pin 13 OE/Active LOW
Combinatorial Output Configurations[Z]
Cz = 0
Cl = 1
Co = 1
Cz = 0
Cl = 1
Co= 0
20G10-10
20G10-11
Figure 5. Product Term OE/Active LOW
Figure 6. Product Term OE/Active HIGH
Cz = 1
Cl = 1
Co = 0
Cz = 1
Cl = 1
Co = 1
Figure 8. Pin 13 OE/Active HIGH
Figure 7. Pin 13 OE/Active LOW
Note:
2. Bidirectional 110 configurations are possible only when the combinatorial output option is selected
4-30
--.
~
--=-,
'; iI:
PLDC20G10B/PLDC20G10
CYPRESS
SEMlCONDUClOR
Maximum Ratings
Latch-Up Current ........................... >200 rnA
Static Discharge Voltage ......................... > 500V
(per MIL-STD-883, Method 8015)
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage
PLDC20G10B and CG7C323B-A ................ 13.0V
PLDC20GlO and CG7C323-A ................... 14.0V
Operating Range
Ambient
Temperature
O°Cto +75°C
Vee
5V ±1O%
Militaryl3J
- 55°C to +125°C
5V ±1O%
Industrial
- 40°C to +85°C
5V ±1O%
Range
Commercial
•
en
Q
...J
Q.
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[4]
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
VIH
Input HIGH Level
VIL
Input LOW Level
IIX
Input Leakage Current
= - 3.2 rnA
IOH = - 2 rnA
IOL = 24 rnA
IOL = 12 rnA
IOH
Vee = Min.,
VIN = VIH or VIL
Ise
lee
Power Supply Current
Output Leakage Current
Com'IJInd
Vee
V
Com'IJInd
0.5
V
0.8
V
Military
2.0
-10
O~VIN~Vee
Unit
Military
= 0.5Vl6,7j
Vee = Max.,
lOUT = ornA
Unprogrammed Device
Max.
2.4
Guaranteed Input Logical HIGH Voltage for All Inputs l5J
Guaranteed Input Logical LOW Voltage for All Inputs l5j
Vss ~ VIN ~ Vee
Output Short Circuit Current Vee = Max., VOUT
loz
Min.
Test Conditions
Vee = Min.,
VIN = VIH or VIL
V
+10
ftA
- 90
rnA
Com'IJInd -15, - 20
70
rnA
Com'IJInd-25, -35
55
rnA
Military-20, -25
100
rnA
Military-30, -40
80
rnA
100
J-lA
= Max., Vss~ VOUT ~ Vee
-100
Capacitance[7]
Parameter
CIN
Description
Input Capacitance
COUT
Output Capacitance
Test Conditions
= 25°C, f = 1 MHz
VIN = 2.0V, Vee = 5.0V
TA
Notes:
3. TA is the "instant on" case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
6.
7.
4-31
Max.
10
Unit
pF
10
pF
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.
-====,:~PRESS
PLDC20G10B/PLDC20G10
·
SEMICONDUCTOR
AC Test Loads and Waveforms (Commercial)
R1 2300
R1 238il
5V5:?i(31
MIL)
9il
OUTPUT
.
INCLUDING
JIG AND
SCOPE
1.
-=
5 V : = F i ( 3 1MIL)
9il
OUTPUT
R2
50 pF
170il
236il MIL
-=
(
)
INCLUDING
JIG AND
SCOPE
(a)
1.
-=
-=
20G10-14
I
THEVENIN EQUIVALENT (Commercial)
OUTPUT
5 pF
(b)
I
Equivalent to:
R2
170il
(236il MIL)
99n
o-----vw:---o
Equivalent to:
THEVENIN EQUIVALENT (Military/Industrial)
136n
2.08V = Vthc
OUTPUT
o----------wv-- 2.13V = Vthm
20G10-15
20G10-16
Switching Characteristics Over Operating Range[3, 8, 9]
Commercial
B-15
Parameter
Description
B-20
-25
-35
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
tpD
Input or Feedback to Non-Registered Output
15
20
25
35
ns
tEA
Input to Output Enable
15
20
25
35
ns
tER
Input to Output Disable
15
20
25
35
ns
tpzx
Pin 11 to Output Enable
12
15
20
25
ns
tpxz
Pin 11 to Output Disable
12
15
20
25
ns
teo
Clock to Output
10
12
15
25
ns
ts
Input or Feedback Set-Up Time
12
12
15
30
ns
tH
Hold Time
0
0
0
0
ns
tp[10]
Clock Period
22
24
30
55
ns
tWH
Clock High Time
8
10
12
17
ns
tWL
Clock Low Time
8
10
12
17
ns
fMAX[ll]
Maximum Frequency
45.4
41.6
33.3
18.1
MHz
Notes:
Part (it) of AC Test Loads and Waveforms used for all parameters except tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms
used for tER, tpzx, and tpxz.
9. The parameters tER and tpxz are measured as the delay from the input
disable logic threshold transition to VOH - O.SV for an enabled HIGH
output or VOL + O.5V for an enabled LOW input.
10. tB millimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tp = ts + teo. The minimum
8.
guaranteed period for registered data path operation (no feedback)
can be calculated as the greater of (tWH + twd or (ts + tH).
11. fMAX, minimum guaranteed operating frequency, is that guaranteed
for state machine operation and is calculated from fMAX = 1/(ts +
teo). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of 1/(tWH + twd or
1/(ts + tH)'
4-32
==
.. ~
_'ilICYPRESS
~JF
PLDC20G 10B/PLDC20G10
SEMICONDUCTOR
Switching Characteristics Over Operating Range (continued)
Military/lndustrial
B-20
Parameter
Description
-30
B-25
-40
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
tpD
Input or Feedback to Non-Registered Output
20
25
30
40
ns
tEA
Input to Output Enable
20
25
30
40
ns
tER
Input to Output Disable
20
25
30
40
ns
tpzx
Pin 11 to Output Enable
17
20
25
25
ns
tpxz
Pin 11 to Output Disable
17
20
25
25
ns
teo
Clock to Output
15
15
20
25
ns
ts
Input or Feedback Set-Up Time
tH
tp[lO]
Hold Time
0
0
0
0
ns
Clock Period
30
33
40
60
ns
tWH
Clock High Time
12
14
16
22
ns
tWL
Clock Low Time
12
14
16
22
ns
fMAX[ll]
Maximum Frequency
33.3
30.3
25.0
16.6
MHz
15
18
20
35
ns
Switching Waveform
INPUTS I/O,
REGISTERED
FEEDBACK
Jr-I'~""IT'"""
~""'-K...I."-V
CP
REGISTERED
OUTPUTS _ _ _ _ _ _~I_l{,.,.y
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _~~~
20G10·17
4-33
•
en
C
..J
D.
~~
CYPRESS
~.
~,
PLDC20GIOB/PLDC20GIO
SEMICONDUCTOR
===========~=~==
Functional Logic Diagram
-ri>
0
4
8
12
16
20
24
28
32
36
40
W<1- =~
OE
··
0
CELL
~7
OE
0
--.
··
2
W
-D7
OE
OUTPUT
I> CELL
(1.--
1r
~
~
~
~
··
0
1P<1-----
7
3
OUTPU
I> CELL
OE
0
~
·
7
I:B
4
OE
<1-----
OUTPUl
~CELL
~
·
7
0
iP<1-----
5
OUTPU
I> CELL
OE
·
0
6
W<1-
--1"':;7
ogJr~T
I>
1r
OE
·
7
0
7
~
OE
~
~
0
·
8
OUTPUl
I> CELL
~
---1'::7
~
<1-----
ogJr~l
I>
OE
0
9
·
-D7
1P<1-----
OUTPUT
I> CELL
OE
·
0
10
11
1P<1-----
---1'::7
~
11111111111111111111111111111111111111111111
UTPUT
CELL
~
~
~
~
b:J1---T...L.--20G10-18
4-34
23
22
21
20
19
18
17
16
15
14
13
·--:~PRESS
F
-
PLDC20G 10B/PLDC20G10
SEMICONDUcrOR
Ordering Information
tpD
(ns)
ts
(ns)
teo
(ns)
(rnA)
Ordering Code
Package
Name
Package 1Ype
15
12
10
70
20
12
12
70
20
15
15
100
PLDC20G lOB -15PC/pI
PLDC20G10B-15WC
PLDC20G lOB -15JC/JI
CG7C323B- A15JC/JILllj
PLDC20G lOB - 20PC/PI
PLDC20G lOB- 20WC
PLDC20G lOB - 20JC/JI
CG7C323B- A20JC/JILllj
PLDC20G10B-20DMB
PLDC20G lOB- 20WMB
PLDC20G10B- 20LMB
PLDC20G10-25PC/PI
PLDC20G 10-25WC
PLDC20G 10 - 25JC/JI
CG7C323-A25JC/JILlLj
PLDC20G10B-25DMB
PLDC20G10B-25LMB
PLDC20GlOB-25WMB
PLDC20G10-30DMB
PLDC20G 10-30LMB
PLDC20G 10-30WMB
PLDC20G 10 - 35PC/pI
PLDC20G 10-35WC
PLDC20G10-35JC/JI
CG7C323-A35JC/JILllj
PLDC20G10-40DMB
PLDC20G 10-40LMB
PLDC20G10-40WMB
Pl3
W14
J64
J64
P13
W14
J64
J64
D14
W14
L64
P13
W14
J64
J64
D14
L64
W14
D14
L64
W14
P13
W14
J64
J64
D14
L64
W14
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24cLead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead (300-Mil) Windowed CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) Windowed CerDIP
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Square Leadless Chip Carrier
24-Lead (300-Mil) Windowed CerDIP
Icc
25
15
15
55
25
18
15
100
30
20
20
80
35
30
25
55
40
35
25
80
Note:
12. The CG7C323 is the PLD20G 10 packaged in the JEDEC-compatible
28-pin PLCC pinout. Pin function and pin order is identical for both
PLeC pinouts. The principle difference is in the location of the "no
connect" (NC) pins.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
tpD
9,10,11
VOL
VIR
1,2,3
1,2,3
tpzx
9,10,11
9,10,11
VIL
IIX
1,2,3
Ioz
1,2,3
1,2,3
Icc
1,2,3
teo
ts
9,10,11
9,10,11
tH
Document #: 38-00019-G
4-35
Operating
Range
Commercial!
Industrial
Commercial!
Industrial
Military
•
en
C
Commercial!
Industrial
Military
Military
Commercial!
Industrial
Military
...J
D.
PLD20GIOC
CYPRESS
SEMICONDUCTOR
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD = 7.5ns
-tsu = 3 ns
- fMAX = 105 MHz
• Reduced ground bounce and under- .
shoot
• PLCC and LCC packages with additional Vee and Vss pins for lowest
ground bounce
• Generic architecture to replace standard logic functions including: 20L10,
20LS, 20R8, 20R6, 20R4, 12L10, 14LS,
16L6, 18L4, 20L2, and 20V8
• Up to 22 inputs and 10 outputs for
more logic power
Generic 24-Pin PAL® Device
• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
- Pin or product term output enable
control
• Preload capability for flexible design
and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse
Functional Description
The PLD20G10C is a generic 24-pin device that can be used in place of 24 PAL
devices. Thus, the PLD20G10Cprovides
significant design, inventory, and programming flexibility over dedicated
24-pin devices.
Using BiCMOS process and Ti-W fuses,
the PLD20G10C implements the familiar
sum~of-products (AND-OR) logic structure. It provides 12 dedicated input pins
and 10 I/O pins (seeLogicBlockDiagram).
By selecting each I/O pin as permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O or a common pin controlled OE
function allows this selection.
The PLD20G lOC automatically resets on
power-up. The Q output of all intern~ registers is set to a logic LOW and the Q outputto a logic HIGH. In addition, the PRELOAD capability allows the registers to be
set to any desired state during testing.
A security fuse is provided to prevent copying of the device fuse pattern.
Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration
G10C-1
Pin Configurations
PLCC (J)
Top View
LCC(L)
Top View
0080
__ If
099::::::::
I
Vss
I
I
4 3 2:1: 282726
- •
25
24
7
23
8 PLD20G10C 22
9
21
10
20
11
19
4321282726
1/0 2
1/03
1/04
vss
1/05
1/06
1/07
I
Vss
PLD20G10C
I
I
I
1112131415161718 19
uuuuuuu
- - $$Ig§, ~
G10C-2
PAL is a registered trademark of Monolithic Memories Inc.
4-36
I
G10C-3
~~
~~;~
_";iE
PLD20GIOC
CYPRESS
- , SEMICONDUCTOR
Selection Guide
20GIOC-7
190
Commercial
Icc (rnA)
Commercial
ts (ns)
Commercial
20GIOC-12
190
20GIOC-15
190
190
190
7.5
10
10
12
12
15
3.0
3.6
3.6
4.5
4.5
7.5
Military
tpD (ns)
20GIOC-IO
190
Military
Military
teo (ns)
Commercial
6.5
7.5
9.5
Military
Commercial
105
7.5
90
9.5
71
10
fMAX (MHz)
90
71
57
Military
Programming
The PLD20GlOC has 10 programmable I/O macrocells (see Macrocell). Two fuses (Cl and Co) can be programmed to configure
output in one offourways. Accordingly, each output can be registered or combinatorial with an active HIGH or active LOW polarity. The feedback to the array is also from this output. An additional fuse (Cz) determines the source of the output enable
signal. The signal can be generated either from the individual OE
product term or from a common external OE pin.
The PLD20G10C can be programmed using the QuickPro II@)
programmer available from Cypress Semiconductor and also with
Data I/O, Logical Devices, STAG, and other programmers. Please
contact your local Cypress representative for further information.
Macrocell
r--------------------l--i--_...;O:.:E;.;.P..:..:R.::.OD:.:U:..:C:.:..T..:..:TE::.R;;,;.M~_ _ _ _ _ _ _ _ _-i ~~l~~~
MUX
10
OUTPUT 1-I1---+---r-I
00
SELECT
I----~
MUX
CP
INPUT!
FEEDBACK
MUX
C1
~ ----~-~~----------+-~-~-~
C1
----~--------------~
_ _ _ ..J
OEPIN
QuickPro II is a trademark of Cypress Semiconductor Corporation.
4-37
tI)
C
...I
D.
Programmable Macrocell
Co
a
G10C-4
~
=n
_
;rlf>RESS
IF
PLD20GIOC
SEMICONDUcrOR
Configuration Table
Figure
C2
Cl
Co
1
0
0
0
Product Term OE/Registered/Active LOW
Configuration
2
0
0
1
Product Term OE/Registered/Active HIGH
5
0
1
0
Product Term OE/CombinatoriaVActive LOW
6
0
1
1
Product Term OE/Combinatorial/Active HIGH
3
1
0
0
Pin OE/Registered/Active LOW
4
1
0
1
Pin OE/Registered/Active HIGH
7
1
1
0
Pin OE/Combinatorial/Active LOW
8
1
1
1
Pin OE/CombinatoriaVActive HIGH
Registered Output Configurations
Cz = 0
Cl = 0
Co = 0
o
Q
G10C-5
G10C-6
Figure 1. Product Term OE/Active LOW
Figure 2. Product Term OE/Active HIGH
Cz = 1
Cl = 0
Co= 0
Figure 3. Pin OE/Active LOW
Figure 4. Pin OE/Active HIGH
Combinatorial Output Configurations[l]
Cz= 0
Cl = 1
Co = a
G10C-9
G10C-10
Figure 6. Product Term OE/Active HIGH
Figure 5. Product Term OE/Active LOW
~G"C_"
Cz = 1
Cl = 1
Cz = 1
Cl = 1
Co = 1
Co = 0
PINOE
Figure 7. Pin OE/Active LOW
Figure 8. Pin OE/Active HIGH
Note:
1. Bidirectional I/O configurations are possible only when the combinatorial output option is selected.
4-38
~
-=,:~PRFSS
PLD20GIOC
RT
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to Vee
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to Vee
DC Input Current .................... - 30 rnA to +5 rnA
(except during programming)
DC Program Voltage .............................. 10V
Operating Range
Range
Commercial
Military[2]
Ambient
Temperature
Vee
O°C to +70°C
5V±5%
- 55°C to +125°C
4.75V to 5.5V
DC Electrical Characteristics Over the Operating Range
Parameter
VOH
Test Conditions
Description
Output HIGH Voltage
Min.
Vee = Min.,
VIN = VIR or VIL
IOH = - 3.2 rnA
Com'l
IOH = - 2 rnA
Mil
IOL = 16 rnA
Com'l
IOL = 12 rnA
Mil
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIR or VIL
VIR
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for All Inputs[3]
IIX
Input Leakage Current
Vss ~ VIN ~ 2.7V, Vee = Max.
II
Maximum Input Current
VIN = Vee, Vee = Max.
Max.
2.4
Unit
V
0.5
2.0
V
V
0.8
V
50
~
Com'l
100
~
Mil
250
- 250
Ioz
Output Leakage Current
Vee = Max., V ss ~ VOUT ~ Vee
-100
100
~
Ise
Output Short Circuit Current
Vee = Max., VOUT = 0.5V[4]
- 30
- 120
rnA
lee
Power Supply Current
Vee = Max., VIN = GND, Outputs Open
Com'l
190
rnA
Mil
190
Notes:
2. TA is the "instant on" case temperature.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
4-39
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
•
tn
Q
..J
Q.
.. ::~PRFSS
$'
~
PLD20GIOC
SEMICONDUCTOR
Switching Characteristics PLD20GIOc[S]
Parameter
Description
20GIOC-7
20GIOC-IO 20GIOC-12 20GIOC-15
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
2
7.5
2
10
2
12
2
15
ns
tpD
Input to Output Propagation Delay[6]
tEA
Input to Output Enable Delay
2
7.5
2
10
2
12
2
15
ns
tER
Input to Output Disable Delay[7]
2
7.5
2
10
2
12
2
15
ns
tpzx
OE Input to Output Enable Delay
2
7.5
2
10
2
12
2
15
ns
tpxz
OE Input to Output Disable Delay
2
7.5
2
10
2
12
2
15
ns
tco
Clock to Output Delay[6]
1
6.5
1
7.5
1
9.5
1
10
ts
Input or Feedback Set-Up Time
3
0
0
9
11.1
3
3
3
tH
Input Hold Time
tp
External Clock Period (tco
tWH
Clock Width HIGH[8]
+ ts)
tWL
Clock Width LOW[8]
fMAXI
External Maximum Frequency (l!(tco
fMAX2
fMAX3
4.5
3.6
ns
7.5
ns
0
0
ns
14
17.5
ns
6
ns
3
3
3
6
ns
105
90
71
57
MHz
Data Path Maximum Frequency
(l!(tWH + twd)[8, 10]
166
166
166
83
MHz
Internal Feedback Maximum Frequency
(l!(tCF + tS))[ll]
133
100
83
66
MHz
tCF
Register Clock to Feedback Input[12]
tpR
Power-Up Reset Timd13]
+ tS))[9]
4.5
1
6.4
1
7.5
1
7.5
1
ns
~s
Capacitance[8]
Max.
Unit
CIN
Parameter
Input Capacitance
Description
8
pF
COUT
Output Capacitance
10
pF
Notes:
5. AC test load used for all parameters except where noted.
6. This specification is guaranteed for all device outputs changing state in
a given access cycle.
7. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max.
8. Tested initially and after any design or process changes that may affect
these parameters.
9. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
10. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
12. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see Note 11) minus ts.
13. The registers in the PLD20G lOC have been designed with the capability to reset during system power-up. Following power-up, all registers
will be reset to a logic LOW state. The output state will depend on the
polarity of the output buffer. This feature is useful in establishing state
machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in power-up reset waveforms must be satisfied.
4-40
--=-,~~PRFSS
PLD20GIOC
·
SEMICONDUCTOR
AC Test Loads and Waveforms
R1 238n
5V
~(319nMIL)
OUTPUT
INCLUDING
JIG AND
SCOPE
I-=
CL
-=
CL[14]
R2
0
V3 fn MIL
(
)
15 pF
PID
50pF
J/K/L
G10C-13
I
Equivalent to:
Package
THEVENIN EQUIVALENT
99n
OUTPUT ~ 2.08V = Vthc
Commercial
Parameter
Output Waveform-Measuremeut Level
Vth
tER (-), tPHZ 1.5V
tER (+), tpLZ 2.6V
VOH O.5V
t
VOL
O.5V
1.5V
O.5V
~
I
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
136n
o------wv----o
2.13V = Vthm
Military
tEA (+), tpZH 1.5V
tEA ( -), tpZL 1.5V
1.5V
O.5V
t
~
~
~
~
~
1.5V
G10C-14
G10C-15
G10C-16
VOL
G1OC-17
Switching Waveform
_'I""'W''''7'I'"","
~l...K.~V
CP
REGISTERED
OUTPUTS: _ _ _ _ _---'~K..V
COMBINATORIAL
OUTPUTS: ___________________
~~~
G10C-18
4-41
Q
..J
Q.
VOH
Note:
14. CL = 5 pF for tER and tpxz measurements for all packages.
INPUTS 1/0,
REGISTERED
FEEDBACK
I
en
2.6V
~
~~PRESS
~_, SEMICONDUCTOR
PLD20GIOC
Power-Up Reset Waveform[13]
,~--------------------------------------------------------VCC
POWER _________________4.....
V,
REGISTERED
ACTIVE LOW
OUTPUT
~1oIt---------
tpR
--------t.-t'
---------------------------------------------------~~------------------------------------------------------------------~~
CLOCK
G10C-19
Preload Waveform[15]
PIN 13 (16)
Vpp
-k
\
t OPR1
~
PIN 2 (3)
PIN 3 (4)
I
PIN 6 (7)
r\
I
PINS (10)
\
J
\
'I
PINg (11)
PRELOAD DATA
PINS 14-23
(17-21,23-27)
/
"'
If.-
1
tOPR1~
t OPR2
tDPR2
t OPR1
1
I
I
~
t OPR1
\
"'
t OPR2
t OPR1
I\V>-i'-
t OPR2
/
t OPR2
CLOCK PIN 1 (2)
tO PR2
t OPR1
L
t OP R1
OUTPUTS
DISABLED
\
.~ t OPR1
1
t OPR1 1\
I
PRELOAD
REGISTE RS
DATA
PRELOADED,
CLOCKED
OUTPUT
IN
ENABLE D
PRELOAD
PRELOAD DATA
DATA
V'LP or V'HP[ 161
REMOVED
G10C-20
Notes:
15. Pins 4 (5), 5 (6), 7 (9) at VILP; Pins 10 (12) and 11 (13) at VIHP; Vee
(Pin 24 (1 and 28)) at Veep
16. Pins 2-8 (3-7, 9,10),10 (12),11 (13) can be set at VIHP or VILP to
insure asynchronous reset is not active.
4-42
~
=---~~
----.,; jJl CYPRESS
? SEMICONDUCTOR
PLD20GIOC
D/K/P (J/L) Pinouts
Forced level on register pin
during preload
Register Q output state
after preload
VIHP
HIGH
VILP
LOW
Name
Description
Min.
Max.
Unit
Vpp
Programming Voltage
9.25
9.75
V
tDPRl
Delay for Preload
1
tDPR2
Delay for Preload
0.5
VILP
Input LOW Voltage
0
0.4
V
VIHP
Input HIGH Voltage
3
4.75
V
Vccp
V cc for Preload
4.75
5.25
V
fls
II
fls
o
C
...I
C.
4-43
~ ;~PRFSS
PLD20GIOC
_, SEMICONDUCTOR
==================
Functional Logic Diagram for PLD20GIOC
1
(2)
-ri)
0
4
8
12
16
20
24
28
32
DE
36
40
=1-
~
··
0
~
~7
-...r
>
("\--
cell
DE
0
·
~("\--
7
2
Macrocell
I>
~
(3)
DE
0
~
·
3
Macrocell
r--I
D--'
-f)7
("\--
I>
(4)
DE
·
0
K
W
7
(5)
4
Macrocell
("\--
DE
·
0
5
R=D
a=r
-D7
Macrocell
("1....--
(6)
DE
0
·
6
~6-
~7
(7)
Macrocell
DE
··
0
W d--
7
7
(9)
Macrocell
>
DE
··
0
8
ID
ts=:J
Macrocell
("\--
-1)7
(10)
DE
·
0
9
(11)
ID
D--'
-f)7
DE
Macrocell
>
11-
~
~16-1-1>
0
·
10
("\--
111111-
cell
~7
: :~, ~: : mt: : lI I Im: : mt: 1 1 1 1~1 1 1 1 ~lIl lmt=: I:I#:l l l l
::Utt:::::::ItllllllllfI::::::::Ullltt=11:::::=::::S-b1t---"t-,---
D/K/P (JIL) Pinouts
4-44
G10C-21
23
(27)
22
(26)
21
(25)
20
(24)
19
(23)
18
(21)
17
(20)
16
(19)
15
(18)
14
(17)
;1~)
·
:~
PLD20GIOC
~=CYPRESS
_ , SEMICONDUCTOR
Ordering Information
Icc
fMAX
tpD (ns)
7.5
(MHz)
105
10
90
(rnA)
190
12
15
71
57
Ordering Code
PLD20G lOC-7DC
PLD20G lOC-71C
PLD20GI0C-7PC
PLD20G10C-I0DC
PLD20GlOC-I01C
PLD20G lOC-lOPC
PLD20GI0C-lODMB
PLD20G lOC-I0KMB
PLD20G lOC-lOLMB
PLD20GI0C-12DC
PLD20G10C-121C
PLD20G lOC-12PC
PLD20G lOC-12DMB
PLD20G10C-12KMB
PLD20GI0C-12LMB
PLD20GI0C-15DMB
PLD20G lOC-15KMB
PLD20GlOC-15LMB
Package
Name
D14
164
P13
D14
164
P13
D14
K73
L64
D14
164
P13
D14
K73
L64
D14
K73
L64
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Parameter
Subgroups
VOH
VOL
VIR
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VIL
IIX
Ioz
Icc
Switching Characteristics
Parameter
Subgroups
tpD
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
teo
ts
tH
Document #: 38-A-00027-A
4-45
Package Type
24-Lead (300-MiI) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
Operating
Range
Commercial
Commercial
Military
Commercial
II
en
C
..J
Q.
Military
Military
PLDC20RAIO
CYPRESS
SEMICONDUCTOR
Features
• Advanced-user programmable macrocell
• CMOS EPROM technology for reprogrammability
• Up to 20 input terms
• 10 programmable I/O macrocells
• Output macrocell programmable as
combinatorial or asynchronous Dtype registered output
• Product-term control of register
clock, reset and set and output enable
• Register preload and power-up reset
• Four data product terms per output
macrocell
Reprogrammable
Asynchronous CMOS
Logic Device
- Military/Industrial
tpD = 20 ns
teo = 20ns
tsu = 10 ns
• Lowpower
- Icc max - 80 rnA (Commercial)
- Icc max = 85 rnA (Military)
• High reliability
- Proven EPROM technology
- >2001Vinput protection
-100% programming and functional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, PLCC available
Functional Description
The Cypress PLDC20RAlO is a high-performance, second-generation program-
• Fast
- Commercial
tpD = 15 ns
teo = 15 ns
tsu = 7 ns
mabIe logic device employing a flexible
macrocell structure that allows anyindividual output to be configured independently
as a combinatorial output or as a fully
asynchronous D-type registered output.
The Cypress PLDC20RAI0 provides lower-power operation with superior speed
performance than functionally equivalent
bipolar devices through the use of highperformance O.8-micron CMOS manufacturing technology.
The PLDC20RAlO is packaged in a 24 pin
300-mil molded DIP, a 300-mil windowed
cerDIp, and a 28-lead square leadless chip
carrier, providing up to 20 inputs and 10
outputs. When the windowed device is exposed to UV light, the 20RAI0 is erased
and can then be reprogrammed.
Logic Block Diagram
I/O g
I/Os
1/05
I/OS
1/01
1/00
Vee
RA10-1
Selection Guide
Generic Part
Number
Com'l
20RAIO-15
15
20RAlO-20
20
tpDns
MiI/lnd
Com'l
tsu ns
MiI/lnd
10
teo ns
Mil/lnd
15
7
20
Com'l
10
20
Com'l
lee ns
Mil/lnd
80
20
80
85
20RAlO-25
25
15
25
85
20RAI0-35
35
20
35
85
4-46
·
~
~ CYPRESS
- , SEMICONDUCTOR
i=
PLDC20RAIO
Pin Configurations
LCC
STD PLCC/HLCC
Top View
Top View
JEDEC PLCC/HLCC [1]
Top View
~ .z-.5'I~~gg
12
13
14
15
16
17
NC
5
6
4 3 2 ~1: 282726
25
NC
1/°2
1/°3
1/04
1/0 5
1/°6
9
10
11
1/0 7
12131415161718
_CXl_m$l~ ~g~
RA10-2
RA10-4
Macrocell Architecture
Figure 1 illustrates the architecture ofthe 20RAlO macrocell. The
cell dedicates three product terms for fully asynchronous control of
the register set, reset, and clock functions, as well as, one term for
control of the output enable function.
The output enable product term output is ANDed with the input from pin 13 to allow either product term or hardwired external control of the output or a combination of control from
both sources. Ifproduct-term-only control is selected, it is automatically chosen for all outputs since, for this case, the external output enable pin must be tied LOW. The active polarity
of each output may be programmed independently for each
output cell and is subsequently fixed. Figure 2 illustrates the
output enable options available.
When an I/O cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term
outputs to be HIGH under all input conditions. This is achieved by
programming all input term programming cells for these two product terms. Figure 3 illustrates the available output configuration
options.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-defined
logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input, the device input configuration programmed by the user may vary from a
total of nine programmable plus ten dedicated inputs (a total of
nineteen inputs) and one output down to a ten-input, ten-output
configuration with all ten programmable I/O cells configured as
outputs. Each input pin available in a given configuration is available as an input to the four control product terms and four uncommitted product terms of each programmable I/O macrocell that has
been configured as an output.
An I/O cell is programmed as an input by tying the output enable
pin (pin 13) HIGH or by programming the output enable product
term to provide a LOW, thereby disabling the output buffer, for all
possible input combinations.
When utilizing the I/O macrocell as an output, the input path functions as a feedback path allowing the output signal to befed back as
an input to the product term array. When the output cell is configured as a registered output, this feedback path may be used to feed
back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each
register to be set by loading each register from an external source
prior to exercising the device. Testing of complex state machine designs is simplified by the ability to load an arbitrary state without
cycling through long test vector sequences to reach the desired
state. Recovery from illegal states can be verified by loading illegal
states and observing recovery. Preload of a particular register is accomplished by impressing the desired state on the register output
pin and lowering the signal level on the preload control pin (pin!)
to a logic LOW level. If the specified preload set-up, hold and
pulse width minimums have been observed, the desired state is
loaded into the register. To insure predictable system initialization,
all registers are preset to a logic LOW state upon power-up, thereby setting the active LOW outputs to a logic HIGH.
Note:
1. The CG7C324 is the PLDC20RAIO packaged in the JEDEC-compat-
ible 28-pin PLCC pinout. Pin fuction and pin order is identical for
both PLCC pinouts. The principle differencd is in the location ofthe
"no connect" (NC) pins.
4-47
•
==7~
==-. -: ~
CYPRESS
~, SEMICONDUcrOR
PLDC20RAIO
OUTPUT ENABLE
(FROM PIN 13)
PRELOAD
(FROM PIN 1)
TO I/O PIN
RA10-5
Figure 1. PLDC20RAI0 Macrocell
Output Always Enabled
Programmable
~r---RA1O-?
RA10-6
Combination of
Programmable and Hardwired
External Pin
RA1O-8
RA1O-9
Figure 2. Four Possible Output Enable Alternatives for the PLDC20RAI0
4-48
PLDC20RAIO
Registered/Active LOW
Combinatorial/Active LOW
II
tn
C
RA10-10
RA10-11
Combinatorial/Active HIGH
Registered/Active HIGH
RA10-12
Figure 3. Four Possible Macrocell Configurations for the PLDC20RAIO
4-49
RA10-13
..J
D.
~
~~PRFSS
- . , ~CONDUcroR
PLDC20RAIO
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 24 to Pin 12) ....................... - 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ , - O.5V to + 7.0V
DC Input Voltage ........ " ............ -3.0 V to + 7.0 V
Output Current into Outputs (LOW) ............... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
DC Program Voltage .............................. 13.0V
Operating Range
Electrical Characteristics Over the Operating Rangel 3]
Parameter
Description
VOH
Output HIGH Voltage
Ambient
Temperature
Range
Commercial
O°C to +75°C
Vee
5V ± 10%
Industrial
-40°C to +85°C
5V ± 10%
Military[2]
- 55°C to +125°C
5V ± 10%
Min.
Test Conditions
Vee = Min.,
VIN = VIH or VIL
10H = -3.2rnA
Com'l
IOH = -2 rnA
Mil/lnd
Vee = Min.,
VIN = VIH or VIL
10L = 8 rnA
Max.
Unit
2.4
V
VOL
Output LOW Voltage
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[4]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs[4]
IIX
Input Leakage Current
Vss:::;; VIN:::;; Vee. Vee = Max
Ioz
Output Leakage Current
Vee = Max., Vss:::;; VOUT:::;; Vee
-40
+40
!1A
Ise
Output Short Circuit Current[5]
Vee = Max., VOUT = 0.5V[6]
-30
-90
rnA
IecI
Standby Power Supply Current
Vee= Max., VIN = GND Outputs Open
Com'l
75
rnA
Mil/Ind
80
rnA
Com'l
80
rnA
Mil/Ind
85
rnA
lec2
B7
Power SUP Current at
Frequency 5
Vee = Max., Outputs Disabled (In High Z State)
Device Operating af fMAX
0.5
2.0
V
-10
0.8
V
+10
/lA
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 2.0 V @ f = 1 MHz
10
pF
COUT
Output Capacitance
VOUT = 2.0 V @ f = 1 MHz
10
pF
Notes:
2.
3.
4.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
5. Tested initially and after any design or process changes that may affect
these parameters.
6. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5 V has
been chosen to avoid test problems caused by tester ground degradation.
4-50
V
·
~~
PLDC20RAIO
'ill CYPRESS
-IF
SEMICONDUcrOR
Switching Characteristics Over the Operating Rangd 3, 7, 8]
Commercial
-15
Parameter
tpD
Description
Min.
Input or Feedback to
Non-Registered Output
Military/Industrial
-20
-20
Max.
Min.
Max.
Min.
-25
Max.
Min.
-35
Max.
Min.
Max.
Unit
15
20
20
25
35
ns
tEA
Input to Output Enable
15
20
20
30
35
ns
tER
Input to Output
Disable
15
20
20
30
35
ns
tpzx
Pin 13 to Output
Enable
12
15
15
20
25
ns
tpxz
Pin 13 to Output
Disable
12
15
15
20
25
ns
teo
Clock to Output
15
tsu
Input or Feedback
Set-UpTime
tH
Hold Time
tp
Clock Period
(tsu + teO)
tWH
Clock Width HIGH[5]
tWL
Clock Width LOW[5]
fMAX
Maximum Frequency
(l/tp )[5]
45.5
ts
Input of Asynchronous
Set to Registered
Output
15
20
20
25
40
ns
tR
Input of Asynchronous
Reset to Registered
Output
15
20
20
25
40
ns
tARw
Asynchronous Reset
Width[5]
15
20
20
25
25
ns
tASW
Asynchronous Set
Width[5]
15
20
20
25
25
ns
tAR
Asynchronous Set/
Reset Recovery Time
10
12
12
15
20
ns
a
U)
C
...I
7
20
20
25
35
ns
20
ns
5
5
ns
30
40
55
ns
13
12
18
25
ns
13
12
18
25
ns
33.3
33.3
25.0
18.1
MHz
10
10
3
5
3
22
30
10
10
15
twp
Preload Pulse Width
15
15
15
15
15
ns
tsup
Preload Set-Up Time
15
15
15
15
15
ns
tHP
Preload Hold Time
15
15
15
15
15
ns
Notes:
7. Part (a) of AC Test Loads was used for all parameters except tEA, tER,
tpzx and tpxz, which use part (b).
8. The parameters tER and tpxz are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled
4-51
HIGH output or VOL +0.5V for an enabled LOW output. Please see
part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
a.
~
•
~2
PLDC20RAIO
~gPRF.SS
_
I'
SEMICONDUCTOR
AC Test Loads and Waveforms (Commercial)
R1 4570
(4700 mil)
R1 4570
(4700 mil)
5V~ R2
OUTPUT
50 pF
I
~~8~~~NG
5V
OUTPUT
2700
(3190 Mil)
-=
-=
SCOPE
TI
5 pF
~~8~~~NG
OUTPUT
I
-=
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
3.0V---90%
R2
GND
2700
(3190 Mil)
-=
RAlO-15
RA10-14
(b)
THEVENIN EQUIVALENT (Commercial)
~
Equivalent to:
1.86V=Vt hc
OUTPUT
RA10-16
Parameter
tpxz(-)
tpxz(+)
1.5V
2.6V
t
VOH O.5V
O.5V
VX
tpzx(-)
Vthc
Vx
tER(- )
1.5V
VOH O.5V
tER(+ )
2.6V
VOL
Vthc
Vx
Vthc
Vx
~
O.5V
VOL
Vthc
tEA(- )
~
2.02V=Vthc
Output Waveform-Measurement Level
Vth
tpzx(+)
tEA(+)
THEVENIN EQUIVALENT (Military/Industrial)
O.5V
t
,
O.5V
O.5V
O.5V
(c)
4-52
~
t
t
,
~
~
~
~
~
~
~
~
VX
RA10-1B
Vx
RA10-19
VOH
RA10-20
VOL
RA10-21
VX
RA10-22
Vx
RA10-23
VOH
RA10-24
VOL
RA10-25
RA10-17
·
---.-:
,
~PRfSS
SEM]CONDUCTOR
PLDC20RAIO
Switching Waveform
INPUTS. REGISTERED
FEEDBACK
CP
ASYNCHRONOUS
RESET
ASYNCHRONOUS
SET
•
tPD
en
OUTPUTS
(HIGH ASSERTED)
C
..J
Q.
OUTPUT ENABLE
INPUT PIN
RA10-26
Preload Switching Waveform
PIN 13
OUTPUT
ENABLE
REGISTER
OUTPUTS
PIN 1
PRELOAD
CLOCK
RA10-27
Asynchronous Reset
ASYNCHRONOUS
RESET
OUTPUT
RA10-28
Asynchronous Set
ASYNCHRONOUS
SET
OUTPUT
RA10-29
4-53
Functional Logic Diagram
1
....
-v
1111
0
~
1111
I'-
~~
7
~
•
D~
It '
- -
3 ....
h
to~
-..->~
... .... !,..;;:;;
••
---
3 .....
I.
I
as
22
It '
~
~n
~
4 ....
23
~~
21
It ~
~
20
31
5 ....
-
u
~[j ~
~
20
......
~'
lJ
~
...,
-
II
9
It '
6-t-..
~
OIl
...,
n
~~
[J~r
-?>'~ [J
~r
~~[j ~r
-
..
7 .....
-A
......
8
It"
...,
5t
It ,.
A
8t-...
I-
-y-.
......
,.:::
:~
u
t-.
6
• p
..
9 ....
I
71
10
.....
...
'L
It P
...
.....
72
L..
-v_
PL
....
o
S
4
7
11111
un 1
. " 12.. " It 20 U
.' ~1
~0
7t
11
-?>rrD~r
20 27 D 31 32 H
4-54
31
4
lo(J-13
-="":' :~PRESS
~JF SEMICONDUcrOR
PLDC20RAIO
Ordering Information
tpD
tsu
teo
ICC2
(ns)
(ns)
(ns)
80
15
7
15
80
85
85
85
20
20
25
35
10
10
15
20
20
20
25
35
Ordering Code
Package
Name
Package lYpe
Operating
Range
PLDC20RAlO-15HC
H64
28-Pin Windowed Leaded Chip Carrier
Commercial
PLDC20RAlO-15JC
J64
28-Lead Plastic Leaded Chip Carrier
PLDC20RAlO-15PC
P13
24-Lead (300-Mil) Molded DIP
PLDC20RA10-15WC
W14
24-Lead (300-Mil) Windowed CerDIP
CG7C324-A15HC
H64
28-Pin Windowed Leaded Chip Carrier
CG7C324-A15JC
J64
28-Lead Plastic Leaded Chip Carrier
PLDC20RAIO- 20HC
H64
28-Pin Windowed Leaded Chip Carrier
PLDC20RAlO- 20JC
J64
28-Lead Plastic Leaded Chip Carrier
PLDC20RAlO- 20PC
P13
24-Lead (300-Mil) Molded DIP
PLDC20RAlO-20WC
W14
24-Lead (300-Mil) Windowed CerDIP
CG7C324-A20HC
H64
28-Pin Windowed Leaded Chip Carrier
CG7C324-A20JC
J64
28-Lead Plastic Leaded Chip Carrier
PLDC20RAlO-20DI
D14
24-Lead (300-Mil) CerDIP
PLDC20RA10 - 20JI
J64
28-Lead Plastic Leaded Chip Carrier
PLDC20RAlO- 20PI
P13
24-Lead (300-Mil) Molded DIP
PLDC20RA10- 20WI
W14
24-Lead (300-Mil) Windowed CerDIP
PLDC20RAlO- 20DMB
D14
24-Lead (300-Mil) CerDIP
PLDC20RAIO- 20HMB
H64
28-Pin Windowed Leaded Chip Carrier
PLDC20RA10- 20LMB
L64
28-Square Leadless Chip Carrier
PLDC20RAlO-20MB
064
28-Pin Windowed Leadless Chip Carrier
PLDC20RA10- 20WMB
W14
24-Lead (300-Mil) Windowed CerDIP
PLDC20RA10-25DI
D14
24-Lead (300-Mil) CerDIP
PLDC20RA10-25JI
J64
28-Lead Plastic Leaded Chip Carrier
PLDC20RAlO- 25PI
P13
24-Lead (300-Mil) Molded DIP
PLDC20RAlO- 25WI
W14
24-Lead (300-Mil) Windowed CerDIP
PLDC20RAlO- 25DMB
D14
24-Lead (300-Mil) CerDIP
PLDC20RAlO- 25HMB
H64
28-Pin Windowed Leaded Chip Carrier
PLDC20RA10- 25LMB
L64
28-Square Leadless Chip Carrier
PLDC20RAlO-250MB
28-Pin Windowed Leadless Chip Carrier
PLDC20RA10- 25WMB
064
W14
PLDC20RAlO-35DI
D14
24-Lead (300-Mil) CerDIP
PLDC20RA10-311
J64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
PLDC20RAlO- 35PI
P13
W14
24-Lead (300-Mil) Windowed CerDIP
PLDC20RA10-35DMB
D14
24-Lead (300-Mil) CerDIP
PLDC20RA10-35HMB
H64
28-Pin Windowed Leaded Chip Carrier
PLDC20RA10- 35LMB
L64
28-Square Leadless Chip Carrier
PLDC20RAlO- 350MB
064
28-Pin Windowed Leadless Chip Carrier
PLDC20RA10-35WMB
W14
24-Lead (300-Mil) Windowed CerDIP
a
In
C
..J
D.
Industrial
Military
Industrial
Military
24-Lead (300-Mil) Windowed CerDIP
PLDC20RAlO-35WI
4-55
Commercial
Industrial
Military
.....:::::==:::
.:~
~'''CYPRESS
~_. , SEMICONDUcrOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VIL
1,2,3
IIX
1,2,3
Ioz
1,2,3
Icc
1,2,3
Switching Characteristics
Parameter
Subgroups
tpD
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tpzx
teo
tsu
tH
Document #: 38-00073- E
PLDC20RAIO
=
~
,
PALC22VIO
CYPRESS
SEMICONDUCTOR
Features
• Advanced second-generation PAL
architecture
• Lowpower
- 55 rnA max. "E'
- 90 rnA max. standard
-120 rnA max. military
• CMOS EPROM technology for
reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• 20, 25, 35 ns commercial and industrial
• 25, 30, 40 ns military
Reprogrammable CMOS
PAL® Device
• Up to 22 input terms and 10 outputs
• High reliability
- Proven EPROM technology
-100% programming and functional
testing
• Windowed DIP, windowed LCC, DIP,
LCC, and PLCC available
Functional Description
The Cypress PALC22V10 is a CMOS second-generation programmable logic
array device. It is implemented with the familiar sum-of-products (AND-OR) logic
structure and a new concept, the "programmable macrocell."
The PALC22VlO is available in 24-pin
300-mil molded DIPs, 300-mil windowed
cerDIPs, 28-lead square ceramic leadless
chip carriers, 28-lead square plastic leaded
chip carriers, and provides up to 22 inputs
and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22V10 is
erased and can then be reprogrammed.
The programmable macrocell provides
the capability of defining the architecture
of each output individually. Each of the
10 potential outputs may be specified as
registered or combinatorial. Polarity of
each output may also be individually selected, allowing complete flexibility of
output configuration. Further configurability is provided through array-configurable output enable for each potential output. This feature allows the 10 outputs to
be reconfigured as inputs on an individual
basis, or alternately used as a combination I/O controlled by the programmable
array.
Logic Block Diagram (PDIP/CDIP)
Vss
CP/I
11°5
11°4
11°3
11°2
1/°1
11°0
Vcc
V10-1
Pin Configuration
LCCIPLCC
Top View
~t,)8oo
__ uz::>:::::-:::::1/0 2
1/0 3
1/0 4
NC
1/0 5
1/0 6
1/0 7
I
NC
- - CIlt,)-f!lZ
PAL is a registered trademark of Monolithic Memories Inc.
4-57
",co
gg
V10-2
•
tn
C
...I
D.
i~~=
PALC22VIO
Functional Description (continued)
PALC22VlO features a variable product term architecture.
There are five pairs of product terms beginning at 8 product
terms per output and incrementing by 2 to 16 product terms per
output. By providing this variable structure, the PALC22VlO is
optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance.
Additional features of the Cypress PALC22V10 include a synchronous preset and an asYnchronous reset product term. These product terms are common to all inacrocells, eliminating the need to
dedicate standard product terms for initialization function. The device automatically resets on power-up.
For testing of programmed functions, a preload feature allows any
or all of the registers to be loaded with an initial value for testing.
This is accomplished by raising pin 8 to a supervoltage V pp , which
puts the output drivers in a high-impedance state. The data to be
loaded is then placed on the I/O pins of the device and is loaded
into the registers on the positive edge of the clock on pin 1. A 0 on
the I/O pin preloads the register with a 0, and a 1 preloads the registerwith a 1. The actual signal on the output pin will be the inversion of the input data. The data on the I/O pins is then removed
and pin 8 is returned to a normal TTL voltage. Again, care should
be exercised to power sequence the device properly.
The PALC22VlO featuring programmable macrocells and variable product terms provides a device with the flexibility to implement logic functions in the 500 to 800 gate array complexity.
Since each of the 10 output pins may be individually configured
as inputs on a temporary or permanent basis, functions requiring
up to 21 inputs and only a single output and down to 12 inputs
and 10 outputs are possible. The 10 potential outputs are enabled
using product terms. Any output pin may be permanently se-
lected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved
through an individual programmable macrocell. These macrocells
are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is
available for establishing the next result in applications such as
control state machines. In a combinatorial configuration, the
combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility
provided by both programmable macrocell product term control
of the outputs and variable product terms allows a significant
gain in functional density through the use of a programmable logic.
Along with this increase in functional density, the Cypress
PALC22VlO provides lower-power operation through the use of
CMOS technology and increased testability with a register preload
feature. Preload facilitates testing programmed devices by loading
initial values into the registers.
Configuration Table
Registered/Combinatorial
Configuration
Cl
Co
0
0
Registered/Active LOW
0
1
Registered/Active HIGH
1
0
Combinatorial/Active LOW
1
1
Combinatorial/Active HIGH
Macrocell
~----------------------,
I
'
I
I
I
AR
I
I
>--+-----~-I
OUTPUT
SELECT
D
I
MUX
Q
Ot--.....- - - - I
CP
SP
INPUT/
FEEDBACK
MUX
Sl
C1
Co ----------r---------------------------------------~
~
~~~~~~
_________
4-58
I
I
I
_______ J
V10-3
-
. :aPRESS
--=-.'
PALC22VIO
SEMICONDUcrOR
Selection Guide
Geueric
Part Number
22VlO-20
"C'
22VlO-25
55
Ieel (rnA)
Com/Iud
Mil
tpD (us)
Com/Iud
Mil
90
90
22VlO-30
ts (us)
Com/Iud
20
100
12
25
25
100
15
18
30
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ...................... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .. . . . . . . . . . . . . . . . . . . . . .. - O.SV to + 7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
UV Exposure ........................... 7258 Wsec/cm2
teo (us)
Com/lud
Mil
12
Mil
15
15
20
20
DC Programming Voltage ......................... 14.0V
Latch-Up Current ........................... >200 rnA
Static Discharge Voltage ......................... > 500V
(per MIL-STD-883, Method 8015)
C
..J
Ambieut
Temperature
Range
O°C to +75°C
Vee
5V ±10%
Industrial
- 40°C to +85°C
5V ±10%
Military[l]
- 55°C to + 125°C
5V ±10%
Commercial
Electrical Characteristics Over the Operating Rangef2]
Parameter
Description
Test Conditions
Min.
Vee = Min.,
VIN = VIR or VIL
lOR
==-
3.2 rnA
Com'l/lnd
lOR
2 rnA
Mil
VOR2
HIGH Level CMOS Output Vee = Min.,
Voltagef31
VIN = VIR or VIL
lOR
=-
100 fAA
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIR or VIL
IOL
= 16 rnA
= 12 rnA
VOHl
Output HIGH Voltage
IOL
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputsl4J
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs l4 ]
IIX
Input Leakage Current
Vss'::;' VIN'::;' Vee, Vee
loz
Output Leakage Current
Ise
lee2
Standby Power Supply
Current
Operating Power Supply
Current
Unit
2.4
V
Vee-1.0V
V
Com'l/lnd
VIR
IcC!
Max.
0.5
V
0.8
V
fAA
fAA
Mil
VIL
Vee
Output Short Circuit Current Vee
2.0
V
= Max.
= Max., Vss'::;' VOUT'::;' Vee
-10
+10
- 40
+40
= Max., VOUT = 0.5Vl3,SJ
- 30
- 90
rnA
55
rnA
Vee = Max., VIN = GND Outputs Open "C'
for Unprogrammed Device
Com'l/lnd
ftoggle
= FMAX[3]
90
rnA
Mil
100
rnA
"1.:'
65
rnA
Capacitance[3]
Parameter
CIN
COUT
Description
Test Conditions
Input Capacitance
Output Capacitance
= 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
VIN
Notes:
1. tA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Tested initially and after any design or process changes that may affect
these parameters.
4.
S.
4-59
•
(I)
Operating Range
Min.
Max.
10
Unit
pF
10
pF
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
a.
ITJ i~PRESS
,
PALC22VIO
SEMICONDUCTOR
Commercial and Industrial Switching Characteristics PALC22VIO[2,6]
-25
-20
Max.
Unit
tPD
Input to Output Propagation Delay[7]
20
25
ns
tEA
Input to Output Enable Delay
20
25
ns
tER
Input to Output Disable Delay[8]
20
25
ns
tco
Clock to Output Delay[9]
12
15
ns
Description
Parameter
Min.
Max.
Min.
ts
Input or Feedback Set-Up Time
12
15
ns
tH
Input Hold Time
0
0
ns
tp
External Clock Period (teo
24
30
ns
tWH
Clock Width HIGH[3]
10
12
ns
tWL
Clock Width LOW[3]
fMAX1
External Maximum Frequency (l/(teo
fMAX2
fMAX3
+ ts)
10
12
ns
41.6
33.3
MHz
Data Path Maximum Frequency
(l/(tWH + twd)[3, 11]
50.0
41.6
MHz
Internal Feedback Maximum Frequency
(l/(tCF + tS»[12]
45.4
35.7
MHz
+ tS»[10]
tCF
Register Clock to Feedback Input[13]
tAW
Asynchronous Reset Width
20
25
tAR
Asynchronous Reset Recovery Time
20
25
tAP
Asynchronous Reset to Registered Output Delay
tSPR
Synchronous Preset Recovery Time
Power-Up Reset Timd 14]
tpR
13
10
Notes:
6. Part (a) of AC Test Loads and Waveforms used for all parameters except tEA, tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms used for tEA, tER, tpzx, and tpxz.
7. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of AC Test Loads and Waveforms for
the minimum guaranteed negative correction which may be subtracted
from tpD for cases in which fewer outputs are changing state per access
cycle.
8. This parameter is specified as the time after output disable input duringwhich the previous output data state remains stable on the output.
This delay is measured to the point at which a previous HIGH level has
fallen to O.5V below V OH min. or a previous LOW level has risen to
O.5V above VOL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of AC Thst Loads and Waveforms for
the minimum guaranteed negative correction that may be subtracted
from teo for cases in which fewer outputs are changing state per access
cycle.
25
ns
ns
ns
25
ns
20
25
ns
1.0
1.0
""S
10. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.
11. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
13. This parameter is calculated from the clock period at fMAX internal
(1/fMAX3) as measured (see Note 12 above) minus ts.
14. The registers in the PALC22VlO have been designed with the capability to reset during system power-up. Following power-up, all registers
will be reset to a logic LOW state. The output state will depend on the
polarity ofthe output buffer. This feature is useful in establishing state
machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.
4-60
~
=--. -:i;~
CYPRESS
--=-,
PALC22VIO
SEMICONDUCTOR
Military Switching Characteristics PALC22VIO[2,6]
-25
Parameter
Description
Min.
-30
Max.
Min.
Max.
Unit
tpD
Input to Output Propagation Delay[7]
25
30
ns
tEA
Input to Output Enable Delay
25
25
ns
tER
Input to Output Disable Delay[8]
25
25
ns
tco
Clock to Output Delay[9]
20
ns
ts
Input or Feedback Set-Up Time
18
20
tH
Input Hold Time
0
0
ns
tp
External Clock Period (tco
33
40
ns
tWH
Clock Width HIGH[3]
14
16
ns
tWL
Clock Width LOW[3]
14
16
ns
fMAX1
External Maximum Frequency (1/(tco
30.3
25.0
MHz
fMAX2
Data Path Maximum Frequency
(1/(twH + twd)[3, 11]
35.7
31.2
MHz
fMAX3
Internal Feedback Maximum Frequency
(1/(tCF + tS»[12]
32.2
28.5
MHz
15
+ ts)
+ tS»[lO]
tCF
Register Clock to Feedback Input[13]
tAW
Asynchronous Reset Width
25
30
tAR
Asynchronous Reset Recovery Time
25
30
tAP
Asynchronous Reset to Registered Output Delay
tSPR
Synchronous Preset Recovery Time
Power-Up Reset Timd 14]
tpR
ns
15
13
25
ns
ns
ns
30
ns
25
30
ns
1.0
1.0
!!S
AC Test Loads and Waveforms
R1 238 Sl
R1 238 Sl
OUTP~~:F1(31.
n MIL) R2 OUTP~~ : = F i (n3MIL)
1 . R2
ALL INPUT PULSES
3.0V----
90%
50 pF
~7g~~NG I-=
-=
SCOPE
170Sl
(236Sl
MIL)
~7g~~~NG
I
50 pF
-=
-=
SCOPE
170Sl
(236Sl
GND
MIL)
V10-4
I
Equivalent to:
V10-5
(c)
(b)
(a)
I
THEVENIN EQUIVALENT (Commercial)
Equivalent to:
99n
OUTPUT ~ 2.08V = Vthc
OUTPUT
THEVENIN EQUIVALENT (Military)
136n
o------vw---o
2.13V = Vthm
V10-7
V10-6
4-61
a
tn
C
..J
D.
·-:~PRESS
-=-,
PALC22VIO
SEMICONDUCTOR
AC Test Loads and Waveforms (continued)
Minimum Negative Correction to tpD and teo
vs. Number of Outputs Switching
z
o
~
W
o
./
en -0.2
~r::::
~ ()
~ ~ -0.6
V;'
(!)O
-0.8
::2:-
~ ~ -1.0
Vx
tER(-)
1.5V
Output Waveform-Measurement Level
VOH
O.5V
...V
OZ
() -0 -0.4
~ ~
/
Parameter
/
V
2.6V
tER(+)
VOL
Vthc
tEA(+)
/
Vx
-1
1 2 3 4 5 6 7 8 9 10
NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE
Vthc
tEA(-)
Vx
~ ,~
Vx
~
,~
VOH
~ ~~
VOL
O.5V
O.5V
Z
~
~ ~~
Vx
O.5V
V10-8
V10-9
V10-10
V10-11
V10-12
(e) Test Waveforms
(d)
Switching Waveform
R~~MJ~~k%
----""
FEEDBACK
SYNCHRONOUS ----~
PRESET
CP
ASYNCHRONOUS
RESET ______________~--------~-JI
REGISTERED
OUTPUTS _ _ _ _ _ _ _~"'*'
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _""""'_
V10-13
Power-Up Reset Waveform[14, 15]
0..,-~~~---------------------------------------------------------Vcc
POWER ________
100l
SUPPLY VOLTAGE
"....
tpR--------------~~
REGISTERED -------+-+----------------~----------ACTIVE LOW
OUTPUTS ___________~~------------~~~~~~~~~v
CLOCK
tpR MAX = 1 !-Is
Note:
15. The clock signal input must be in a valid LOW state (VIN less than
O.8V) or a valid HIGH state (VIN greater than 2.4V) prior to occurrence of the 10% level on the monotonically rising power supply voltage as shown in Power-Up Reset Waveform. In addition, the clock inpui signal must remain stabie in that vaiid state as indicated until the
4-62
V10-14
90% level on the power supply voltage has beenreached. The clock signal may transition LOW to HIGH to clock in new data or to execute
a synchronous preset after the indicated delay (tPR + ts) has been observed.
~~
===-=
--=-,=
PALC22VIO
CYPRESS
SEMICONDUCTOR
Functional Logic Diagram for PALC22VIO
-rf)
pPl>P3
0
4
8
12
16
20
24
28
32
36
40
AR
OE
··
0
/'
~7
~
:=[b
cell
OE
~[b
0
·
2
"
9
I>
<1-
=~
n=~
IT
0
8-J"
cell
~~
11
3
OE
0
"
·
4
i---,
0
..........
·
5
cell
::tb
Jr"
15
OE
j-
0
cell
·
6
19
cell
18
I>
Jr- n-
15
OE
0
··
7
20
IT
qb
"""
cell
~~
~
13
OE
0
j-
··
=~
IT
~tb
~
8
OE
~
0
·
/
<1-
9
OE
cell
=[b
cell
·
<1---
7
10
15
TT
) =[b
0
16
n-
I>
9
17
I>
I>
11
cell
14
~
SP
./1
11
13
VQ-5
11
4-63
C
..J
Q.
I>
I--
•
en
21
I>
~frJt=
13
OE
22
~
OE
·
cell
23
·
.~
======
j; CYPRESS
,
SEMICONDUCTOR
PALC22V10
1Ypical DC and AC Characteristics
NORMALIZED STANDBY
SUPPLY CURRENT (ICC!)
vs. AMBIENT TEMPERATURE
NORMALIZED STANDBY
SUPPLY CURRENT (IcC!)
vs. SUPPLY VOLTAGE
1.4 ,...-----r--..,-----,,--""2
(.)
..2
1.21---+---+-----::j~--1
Cl
w
::J
«
~
1.6.-----,.------...,
(.) 1 . 4 1 - - " r - - - ; - - - - - - - I
..2
Cl
~
N
1.01----+--ir---t---I
a:
0.81---*--+- TA = 25°C
f = fMAX
0.6 L...-_---L._ _...l.-_
4.0
4.5
5.0
-
«
oZ
M
NORMALIZED PROPAGATION
DELAY vs. TEMPERATURE
1.3 , . . . - - - -......- - - - - . . . . . ,
~ 1.2l------+-----~-1
w
N
::J 1.1
«
t-----t---~---I
~
a:
o
z 1.0 t - - - - " I I I i ' - - - - - - 1
25
1.01------''Ir-------I
0.81-----;-----'''''''''''''':::::----1
~ 1.1 +-----+---+----1
«
~
a:
o
z 1.0 + - - - - - - . . 1 ' - - - - - - 1
~.~L5------J2L...5-----1....J25
AMBIENT TEMPERATURE (0C)
~
a:
z 0.9
0.8
4.0
Cl
".,
V
/"
10
5
~5
'"
5n
"""
5~
SUPPLY VOLTAGE
6n
M
...,.
15
~
w
~
1.2
'iii'
o
~
""'"
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
V
o
o
1.1
w
~
N
::J 1.0
«
/
200
~
Cl
~
~
a:
0
z 0.9
400
600
0.8
4.0
800 1000
CAPACITANCE (pF)
a
(.)
4.5
,
'"
5.0
5.5
SUPPLY VOLTAGE
NORMALIZED CLOCK-TO-OUTPUT
TIME vs. SUPPLY VOLTAGE
1.1 ,....----,---.,.-----,---,
"""
6.0
M
NORMALIZED CLOCK-TOOUTPUT TIME vs. TEMPERATURE
8
Cl
w
«
20
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.3 , - - - - - , - - - - - - - ,
Cl
N
DELTA PROPAGATION TIME
vs. OUTPUT LOADING
125
1.2l------+-----~-1
1.1
w
0
AMBIENT TEMPERATURE (0C)
:!!
~
Cl
::J 1.0
E-
Cl
1.2
0.6L....-_ _ _..L...._ _ _ _ _...J
-55
25
125
AMBIENT TEMPERATURE (0C)
___JL....-_....J
5.5
6.0
SUPPLY VOLTAGE
1.21---00T-;-------I
::J
~
oz
NORMALIZED
PROPAGATION DELAY
vs. SUPPLY VOLTAGE
Cl
W
N
~
~ 1.0
a:
::J
«
~
oz
1.11-----+--~----I
oz
0.9'--_--'-_ _-'--_-"_ _.......
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
M
25
125
AMBIENT TEMPERATURE (0C)
V10-16
4-64
- :~
-.
~ICYPRESS
PALC22VIO
~iF SEMICONDUCTOR
'lYpical DC and AC Characteristics (continued)
DELTA CLOCK-TO-OUTPUT TIME
vs. OUTPUT LOADING
20.0
15.0
V~
Iii
.s
o
~ 10.0
V
~
w
Cl
5.0
0.0
V
o
200
-
1./
400
« 120
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
.s 105
./
I-
~
90
~ 75
=>
~
z
Ci5
/
60
~
30
o
15
600
800 1000
/
0.0
60
w
~
C/)
Vee = 5.0V TA = 25°C
I
1.0
2.0
3.0
OUTPUT VOLTAGE
CAPACITANCE (pF)
!Z
.s
§
o
/
oV
OUTPUT SOURCE CURRENT
70 vs. VOLTAGE
=>
(,)
w
(,)
I
45
I-
~
/
---
«
Erasure Characteristics
Wavelengths of light less than 4000A begin to erase the
PALC22VlO. For this reason, an opaque label should be placed
over the window if the device is exposed to sunlight or fluorescent
lighting for extended periods of time. In addition, high-ambient
light levels can create hole-electron pairs that may cause blank
check failures or verify errors when programming windowed parts.
This phenomenon can be avoided by placing an opaque label over
the window during programming in high-ambient light environments.
-
4.0
~
~
=>
o
~
50
'\.
40
',,-
30
"'-
20
10
0
0.0
M
1.0
"'""
2.0
~
3.0
OUTPUT VOLTAGE
"'
M
4.0
V10-17
The recommended dose for erasure is ultraviolet light with a wavelength of 2537A for a minimum dose (UV intensity multiplied by
exposure time) of 25 Wsec /cm2. For an ultraviolet lamp with a 12
mW/cm2 power rating, the exposure would be approximately 35
minutes. The PALC22V10 needs to be placed within one inch of
the lamp during erasure. Permanent damage may result if the device is exposed to high-intensity UV light for an extended period of
time. 7258 Wsec/cm2 is the recommended maximum dosage.
Ordering Information 22VIO
teo
(rnA)
tpD
(ns)
ts
(ns)
(ns)
90
20
12
12
IcC
55
90
100
25
25
25
15
15
18
15
15
15
Ordering Code
Package
Name
Package 'JYpe
PALC22V1O- 20HC
H64
28-Pin Windowed Leaded Chip Carrier
PALC22V10- 2OJC/JI
J64
28-Lead Plastic Leaded Chip Carrier
PALC22V1O- 20PCIPI
P13
24-Lead (300-Mil) Molded DIP
PALC22V1O- 20WC/WI
W14
24-Lead (300-Mil) Windowed CerDIP
PALC22V1OL- 25HC
H64
28-Pin Windowed Leaded Chip Carrier
PALC22V1OL- 25JC
J64
28-Lead Plastic Leaded Chip Carrier
PALC22V10L- 25PC
P13
24-Lead (300-Mil) Molded DIP
PALC22V1OL- 25WC
W14
24-Lead (300-Mil) Windowed CerDIP
PALC22V10- 25HC
H64
28-Pin Windowed Leaded Chip Carrier
PALC22V10- 25JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
PALC22V10 - 25PCIPI
P13
24-Lead (300-Mil) Molded DIP
PALC22V1O- 25WC/WI
W14
24-Lead (300-Mil) Windowed CerDIP
PALC22V10- 25DMB
D14
24-Lead (300-Mil) CerDIP
PALC22VlO- 25KMB
K73
24-Lead Rectangular Cerpack
PALC22V10- 25LMB
L64
28-Square Leadless Chip Carrier
PALC22V10- 25QMB
Q64
24-Pin Windowed Leadless Chip Carrier
PALC22V10- 25WMB
W14
24-Lead (300-Mil) Windowed CerDIP
4-65
Operating
Range
Commercial!
Industrial
Commercial
Commercial!
Industrial
Military
II
en
C
..J
D.
.:;z
oj; CYPRESS
•
~
,
PALC22VIO
SEMICONDUCTOR
Ordering Information 22VIO (continued)
(rnA)
Icc
tpD
(ns)
ts
(ns)
tco
(ns)
100
30
20
20
Ordering Code
Package
Name
PALC22V10-30DMB
D14
24-Lead (300-Mil) CerDIP
PALC22V10- 30KMB
K73
24-Lead Rectangular Cerpack
PALC22V10-30LMB
L64
28-Square Leadless Chip Carrier
PALC22V10-30QMB
Q64
24-Pin Windowed Leadless Chip Carrier
PALC22V10-30WMB
W14
24-Lead (300-Mil) Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
VIL
IIX
Ioz
Icc
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Subgroups
tpD
9,10,11
9,10,11
9,10,11
9,10,11
teo
ts
tH
Package 'fYpe
Document #: 38-00020-G
4-66
Operating
Range
Military
PALC22VIOB
Reprogrammable CMOS
PAL® Device
Features
• Advanced second generation PAL architecture
• Lowpower
- 90 rnA max. standard
-100 rnA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
- "15" commercial and industrial
10 ns teo
10 ns t8
15 ns tpD
50 MHz
•
•
•
•
Functional Description
- "IS" and "20" military
10/15 ns teo
10/17 ns t8
15/20 ns tpD
50/31 MHz
Up to 22 input terms and 10 outputs
Enhanced test features
- Phantom array
-Top test
- Bottom test
-Preload
High reliability
- Proven EPROM technology
-100% programming and functional
testing
Windowed DIP, windowed LCC, DIP,
LCC, PLCC available
The Cypress PALC22VlOB is a CMOS second-generation programmable logic
array device. It is implemented with the familiar sum-of-products (AND-OR) logic
structure and a new concept, the "Programmable Macrocell."
The PALC22VlOB is executed in a 24-pin
300-mil molded DIP, a 300-mil windowed
cerDIP, a 28-lead square ceramic leadless
chip carrier, a 28-lead square plastic
leaded chip carrier, and provides up to 22
inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the
22VlOB is erased and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each output individually.
Each of the 10 potential outputs may be
specified as "registered" or "combinatorial." Polarity of each output may also be
Logic Block Diagram (PDIP/CDIP)
1/°5
1/°3
1/°4
1/°2
1/°1
V108-1
Pin Configurations
LCC
PLCC
Top View
Top View
ti:&?886
--~~~g'~
I
N/C
_ _ c.JZ:>:::O:::O
1/°2
1/0 3
1/°4
I
I
N/C
N/C
1/0 5
I/Os
1/°7
-
PAL is a registered trademark of Monolithic Memories Inc.
4-67
-
(/)()-
:spz
CD
o:J
gg
V108-3
II
o
C
..J
a..
,?=
_,
PALC22VIOB
SEMICONDUCTOR
Functional Description (continued)
individually selected, allowing complete flexibility of output configuration. Further configurability is provided through "array"
configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by
the programmable array.
PALC22V10B features a "variable product term" architecture.
There are 5 pairs of product terms beginning at 8 product terms
per output and incrementing by 2 to 16 product terms per output.
By providing this variable structure, the PALC22VlOB is optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALC22V10B include a synchronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the need
to dedicate standard product terms for initialization function. The
device automatically resets upon power-up.
For testing of programmed functions, a preload feature allows any
or all of the registers to be loaded with an initial value for testing.
This is accomplished by raising pin 8 to a supervoltage V pp, which
puts the output drivers in a high-impedance state. The data to be
loaded is then placed on the I/O pins of the device and is loaded
into the registers on the positive edge ofthe clock on pin 1. A 0 on
the I/O pin preloads the register with a 0 and a 1 preloads the registerwith a 1. The actual signal on the output pin will be the inversion
of the input data. The data on the I/O pins is then removed, and pin
8 returned to a normal TTL voltage. Care should be exercised to
power sequence the device properly.
The PALC22VIOB featuring programmable macrocells and variable product terms provides a device with the flexibility to implement logic functions in the 500 to 800 gate array complexity. Since
each of the 10 output pins may be individually configured as inputs
on a temporary or permanent basis, functions requiring up to 21
inputs and only a single output and down to 12 inputs and 10 outputs are possible. The 10 potential outputs are enabled using product terms. Any output pin may be permanently selected as an out-
put or arbitrarily enabled as an output and an input through the
selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to
provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information
to the array. This information is available for establishing the next
result in applications such as control-state-machines. In a combinatorial configuration, the combinatorial output or, if the output is
disabled, the signal present on the I/O pin is made available to the
array. The flexibility provided by both programmable macrocell
product term control of the outputs and variable product terms allows a significant gain in functional density through the use of a
programmable logic.
Along with this increase in functional density, the Cypress
PALC22VlOB provides lower-power operation through the use of
CMOS technology, increased testability with a register preload
feature, and guaranteed AC performance through the use of a
phantom array. This phantom array (Po - P3) and the "top test"
and "bottom test" features allow the 22VlOB to be programmed
with a test pattern and tested prior to shipment for full AC specifications without using any of the functionality of the device specified for the product application. In addition, this same phantom
array may be used to test the PALC22VlOB at incoming inspection before committing the device to a specific function through
programming. Preload facilitates testing programmed devices by
loading initial values into the registers.
Configuration Table 2
Registered/Combinatorial
Cl
Co
0
0
Configuration
Registered/Active LOW
0
1
Registered/Active HIGH
1
0
Combinatorial/Active LOW
1
1
Combinatorial/Active HIGH
Macrocell
OE
r---------------------,
I
I
I
I
I
I
I
AR
r-~---------4~
D
Qf----------t
OUTPUT
SELECT
MUX
O~..----I
CP
SP
INPUT/
FEEDBACK
MUX
S1
I
I
I
I
___________ I
IL _ _ _ _ _ _ _ _ _ _MACROCELL
~
4-68
V10B·4
PALC22VIOB
Selection Guide
Generic
Part Number
22V10B-15
-
22VlOB-20
tpo ns
Com/lnd
15
ICClmA
Com/lnd
Mil
100
90
-
100
ts ns
Com/lnd
10
Mil
15
-
20
tcons
Com/lnd
10
Mil
10
Mil
10
-
17
15
Maximum Rating
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ...................... - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Output Current into Outputs (Low) ............... 16 rnA
UV Exposure ........................... 7258 Wsec/cm2
DC Programming Voltage ......................... 13.0V
Latch-Up Current ........................... >200 rnA
Static Discharge Voltage
(per MIL-STD 883 Method 3015) ............... >2001V
Operating Range
Ambient
Temperature
Range
Commercial
O°Cto +75°C
Vcc
5V ±1O%
Military[l]
- 55°C to +125°C
5V ±1O%
Industrial
-40°C to +85°C
5V ±10%
Electrical Characteristics Over the Operating Rangd 2]
Description
Parameters
VORl
Output HIGH Voltage
Min.
Test Conditions
Vee = Min.,
VIN = VIR or VIL
VOR2
HIGH Level CMOS Output Vee = Min.,
Voltagd3]
VIN = VIR or VIL
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIR or VIL
= -3.2 rnA
lOR = -2 rnA
lOR = -100 !JA
lOR
= 16 rnA
IOL = 12 rnA
V
Mil
Vec1.0V
Com'l/Ind
IOL
Max. Units
2.4
Com'l/Ind
0.5
V
0.8
V
Mil
VIR
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[4]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs[4]
IIX
Input Leakage Current
Vss.s VIN.s Vee, Vee
-10
10
!JA
Ioz
Output Leakage Current
Vee
-40
40
!lA
-30
Ise
Output Short Circuit Current
IeC!
Standby Power Supply
Current
Iee2
Operating Power Supply
Current
= Max.
= Max., Vss.s VOUT.s Vee
Vee = Max., VOUT = 0.5V[3,5]
Vee = Max., VIN = GND Outputs Open
for Unprogrammed Device
ftoggle
= FMAX[3]
2.0
V
-90
rnA
Com'l/Ind
90
rnA
Mil
100
rnA
Com'l/Ind
90
rnA
100
rnA
Device Programmed with Worst Case Pat- Mil
tern, Outputs Three-Stated
Notes:
1. tA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Tested initially and after any design or process changes that may affect
these parameters.
4.
5.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground degradation.
Capacitance[3]
CIN
Parameters
Description
Input Capacitance
COUT
Output Capacitance
1YPicaJ
11
9
4-69
Max.
Units
pF
pF
II
~
-~
PALC22VIOB
====-'
-=- JF-= CYPRFSS
SEMICONDUCTOR
Switching Characteristics PALC22VIO[2,6]
Commercial & Industrial
Military
Military
B-15
B-15
B-20
Max.
Units
tpD
Input to Output Propagation Delay[7]
15
15
20
ns
tEA
Input to Output Enable Delay
15
15
20
ns
tER
Input to Output Disable Delay[8]
15
15
20
ns
tco
Clock to Output Delay[9]
10
10
15
ts
Input or Feedback Set-Up Time
Parameters
Min.
Description
tH
Input Hold Time
tp
External Clock Period (tco
Max.
10
+ ts)
Min.
Max.
Min.
17
10
ns
ns
0
0
0
ns
20
20
32
ns
ns
tWH
Clock Width HIGH[3]
6
6
12
tWL
Clock Width LOW[3]
6
6
12
ns
fMAXI
External Maximum Frequency
(l/(tco + tS»[IO]
50.0
50
31.2
MHz
fMAX2
Data Path Maximum Frequency
(l/(tWH + twd)[3, 11]
83.3
83.3
41.6
MHz
fMAX3
Internal Feedback Maximum Frequency
(l/(tCF + tS»[12]
80.0
80
33.3
MHz
tCF
Register Clock to Feedback Input[13]
tAw
Asynchronous Reset Width
15
15
20
tAR
Asynchronous Reset Recovery Time
10
12
20
tAP
Asynchronous Reset to Registered Output
Delay
tSPR
Synchronous Preset Recovery Time
10
20
20
ns
tpR
Power-Up Reset Timel l4 ]
1.0
1.0
1.0
fts
2.5
ns
ns
ns
25
20
20
Notes:
6. Part (a) of AC Test Loads and Waveforms used for all parameters except tEA, tER, tpzx, and tpxz. Part (b) of AC Test Loads and Waveforms used for tEA, tER, tpzx and tpxz.
7. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of AC Test Loads and Waveforms for
the minimum guaranteed negative correction which may be subtracted
from tpo for cases in which fewer outputs are changing state per access
cycle.
8. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5
volts above VOL max. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle. See part (d) of AC Test Loads and Waveforms for
the minimum guaranteed negative correction which may be subtracted
from teo for cases in which fewer outputs are changing state per access
cycle.
13
2.5
ns
10. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
13. This parameter is calculated from the clock period at fMAX internal
(lIfMAX3) as measured (see Note 12 above) minus ts.
14. The registers in the PALC22V10B has been designed with the capability to reset during system power-up. Following power-up, all registers
will be reset to a logic LOW state. The output state will depend on the
polarity of the output buffer. This feature is useful in establishing state
machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.
4-70
PALC22VIOB
AC Test Loads and Waveforms (Commercial)
R1 23sn
5V 1--_ _(3_1-'<9"'n.A,...-M_IL.;...,)
R1 23sn
OUTPUTO---+-----.. R2
INCLUDING
JIG AND
SCOPE
50 pF
I-=
-=
OUTP:~ :=FI("."
MIL)
170n
(236n
j78~~~NG
MIL)
I
5 pF
-=
-=
SCOPE
(a)
ALL INPUT PULSES
A2
3.0V---90%
170n
(236n
GND
MIL)
V10B-9
I
Equivalent to:
V10B-1O
(c)
(b)
Equivalent to:
99Sl
THEVENIN EQUIVALENT (Military)
In
136Sl
OUTPUT ~ 2.0SV = Vthc
OUTPUT~
2.13V=Vthm
V10B-11
o
/
~ ~ -0.2
o~
()
~.8
~ II:
C)O
z
j
:i:O
~
I-
-0.4
Vi'"
"""V
VV
-0.6
-O.S
-1.0
V
1/
V
Z
~
V10B-12
Minimum Negative Correction to tpD and teo
vs. Number of Outputs Switching
z
o
~
w
II
I
THEVENIN EQUIVALENT (Commercial)
-1
Parameter
Vx
tER(-)
l.SV
tER(+)
2.6V
tEA(+)
Vthc
tEA(-)
Vthc
1 2 3 4 5 6 7 S 9 10
NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE
Output Waveform-Measuremeut Level
VOH O.SV
VOL
Vx
Vx
t
t
t
t
O-SV
O-SV
O-SV
~
~
~
~
VX
V10B-5
Vx
V10B-6
VOH
V10B-7
VOL
V10B-8
(e) Test Waveforms
V10B-13
(d)
Switching Waveform
R~~Mi~~k'6
----.. .
FEEDBACK
SYNCHRONOUS _ _ _""""'-v
PRESET
14-~----.t
CP
ASYNCHRONOUS
RESET _ _ _ _ _ _ _+-:--____1-"1
REGISTERED
OUTPUTS _ _ _ _ _ _ _"""-II..¥
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _-'-~
V10B-14
4-71
C
~
PALC22VIOB
Power-Up Reset Waveform[14]
4V ~,.....-------------------------- Vee
POWER
SUPPLY VOLTAGE ------.....:;;'("""
~------------- tpR----------------~
REGISTERED ---------------~~--------------~~~~~~~~~~~---------------------
ACTIVE LOW
OUTPUTS -------+-+-------~~~~~~~~~
CLOCK
tpR MAX = 1 fls
V10B-15
Functional Logic Diagram for PALC22VIOB
_-()
P Pa
AR F
0
4
8
12
16
20
24
28
32
-f::/
·
L 6b.
o~
21
11
o~
=i
:::J
·
4
~
~
=!
~~
13
o~
~~
~
15
::::
::::
::::
::::jf~r>-
::::
~
15
t::
t::
~r>-t::~
::::~
t::
13
o~
o~
:
9
0
~.
17
16
11
9
~
18
L 6b
~c1-Bb
··
8
19
~
·
7
20
...
~
·
6
~
:::J
·
5
23
22
9
:
3
40
;1--
o~
2
36
1>-&r.
J(1-8b
o~
8
·:
~-Bb
7
--
SP
15
14
13
1
V10B 16
4-72
PALC22VIOB
lYpical DC and AC Characteristics
NORMALIZED STANDBY
SUPPLY CURRENT (ICCl)
vs. SUPPLY VOLTAGE
NORMALIZED
PROPAGATION DELAY
vs. SUPPLY VOLTAGE
NORMALIZED STANDBY
SUPPLY CURRENT (ICCl)
vs. AMBIENT TEMPERATURE
1.6...-----r---------,
1.4 r-----,---"""T""--~-~
15 1.21----+---+---7flC---1 15
o
o
w
~
N
::::i
«
:2
ex:
oz
1.01----+---#---+---1
~
O.st---~--+
TA = 25°C
-
oZ
f = fMAX
O.sl-----+-----.;::.....:::-----1
Z
15.0
o
w
~ 1.1 +-----+---71''----1
«
:2
ex:
4.0
L
~ 10.0
0.9 '--_ _ _--L._ _ _ _ _----l
- 55
25
125
0.0
AMBIENT TEMPERATURE (0C)
",.
/
V
o
200
400
~
1.2 t-----+-------:~I
::::i 1.0
«
:2
ex:
0
Z
600
~ 1.1 t-----+--~:.-..--I
8
'"
4.5
~
5.0
"
5.5
SUPPLY VOLTAGE
.......
6.0
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
8
W
N
::::i
ex:
o
z 1 . 0 + - - - -........< - - - - - - - 1
z
::::i
«
:2
AMBIENT TEMPERATURE (0C)
6.0
M
o
W
N
«
125
5.5
1.1
«
:2
0.9
O.S
4.0
SOO 1000
o
ow
~
N
NORMALIZED CLOCK TO OUTPUT
TIME vs. SUPPLY VOLTAGE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.1
w
CAPACITANCE (pF)
1.3,..------r--------,
5.0
SUPPLY VOLTAGE
0
V
~
5.0
4.5
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
./
w
1 . 0 + - - - -........< - - - - - - - 1
'"
O.s
.......
1.2
o
o
~
0.9
DELTA PROPAGATION TIME
vs. OUTPUT LOADING
~ 1.2r-----+----~~1
~
ex:
AMBIENT TEMPERATURE (0C)
M
20.0
25
~ 1.0
:2
o
NORMALIZED PROPAGATION
DELAYvs. TEMPERATURE
(J)
~
N
1.0 I-----~--------I
1.3,..------r--------,
oz
1.1
w
1.2
0~~~5-----2~5-------~125
0.6 ~----:-L:----::'-:----:~----:"'
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
~
o
::::i
«
1.2
~
ex:
o
1.11------t--+------I
oZ
0.9'--_......L___-'-_ _........._---'
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
M
25
125
AMBIENT TEMPERATURE (0C)
V108-17
4-73
II
In
Q
...I
0..
PALC22VIOB
1Ypical DC and AC Characteristics (continued)
DELTA CLOCK TO OUTPUT TIME
vs. OUTPUT LOADING
15.0
(jj'
.S-
'/
o
!"
~w
Cl
10.0
5.0
0.0
---
~ 120
20.0
V
V
o
200
400
V '"
-
.s 105
!z
w
./
90
/v
~ 75
~
60
Ci5
45
ir
I-
::::>
o
800 1000
30
15
/
0.0
~
Z
Vee = 5.0V TA = 25°C
I
1.0
2.0
3.0
OUTPUT VOLTAGE
CAPACITANCE (pF)
~
Ci5
/
o fl
!z
70
60
r\.
50
B 40
I
I-
~
.s
a:
7
::::>
z
600
OUTPUT SOURCE CURRENT
vs.VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase the
PALC22V10B. For this reason, an opaque label should be placed
over the window if the device is exposed to sunlight or fluorescent
lighting for extended periods of time. In addition, high ambient
light levels can create hole-electron pairs that may cause "blank"
check failures or "verify errors" when programming windowed
parts. This phenomenon can be avoided by use of an opaque label
over the window during programming in high ambient light environments.
-
4.0
"-'~
30
~ 20
D..
I-
5
"""" ~
10
o
0.0
M
"r":
1.0
2.0
.........
3.0
OUTPUT VOLTAGE
M
4.0
Vl08-18
The recommended dose for erasure is ultraviolet light with a
wavelength of2537 Angstroms for a minimum dose (UVintensity multiplied by exposure time) of 25 Wsec /cm 2 • For an ultraviolet lamp with a 12 m W /cm 2 power rating, the exposure would
be approximately 35 minutes. ThePALC22V10B needs to be
placed within 1 inch of the lamp during erasure. Permanent
damage may result ifthe device is exposed to high-intensity UV
light for an extended period of time. 7258 Wsec/cm 2 is the recommended maximum dosage.
Ordering Information
ICC
(rnA)
tpD
(ns)
ts
(ns)
tco
(ns)
90
15
10
10
100
100
15
20
10
17
10
15
Ordering Code
Package
Name
Package 1Ype
PALC22VlOB-15PCIPI
P13
24-Lead (300-Mil) Molded DIP
PALC22V10B-15WC/WI
W14
24-Lead (300-Mil) Windowed CerDIP
PALC22VlOB-15JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOB-15HC
H64
28-Pin Windowed Leaded Chip Carrier
PALC22VlOB-15DMB
D14
24-Lead (300-Mil) CerDIP
PALC22VlOB-15WMB
W14
24-Lead (300-Mil) Windowed CerDIP
PALC22V10B-15HMB
H64
28-Pin Windowed Leaded Chip Carrier
PALC22VlOB-15LMB
L64
28-Square Leadless Chip Carrier
PALC22V10B-150MB
064
28-Pin Windowed Leadless Chip Carrier
PALC22V10B-15KMB
K73
24-Lead Rectangular Cerpack
PALC22VlOB- 20DMB
D14
24-Lead (300-Mil) CerDIP
PALC22V10B- 20WMB
W14
24-Lead (300-Mil) Windowed CerDIP
PALC22VlOB- 20HMB
H64
28-Pin Windowed Leaded Chip Carrier
PALC22V10B- 20LMB
L64
28-Square Leadless Chip Carrier
PALC22V10B-200MB
064
28-Pin Windowed Leadless Chip Carrier
PALC22VlOB- 20KMB
K73
24-Lead Rectangular Cerpack
4-74
Operating
Range
Commercial!
Industrial
Military
Military
-~~
-
PALC22VIOB
:="= CYPRESS
-iF
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIR
VIL
IIX
Ioz
Icc
II
en
C
..J
D.
Switching Characteristics
Parameters
Subgroups
tpD
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8, 9, 10, 11
7, 8, 9, 10, 11
teo
ts
tH
Document #: 38-00195
4-75
PAL22VIOC
PAL22VPIOC
CYPRESS
SEMICONDUCTOR
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tPD = 6ns
-tsu = 3 ns
-fMAX = 117 MHz
• Reduced ground bounce and undershoot
• PLCC and LCC packages with additional Vee and Vss pins for lowest
ground bounce
• Up to 22 inputs and 10 outputs for
more logic power
• Variable product terms
- 8 to 16 per output
Universal PAL® Device
• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operatiou
- 2 new feedback paths
(PAL22VPI0C)
• Synchronous PRESET, asynchronous
RESET, and PRELOAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse
Functional Description
The Cypress PAI22VlOC and PAI22VPlOC
are second-generation programmable
array logic devices. Using BiCMOS
process and Ti-W fuses, the PAL22VIOC
and PAL22VPIOC use the familiar sumof-products (AND-OR) logic structure
and a new concept, the programmable
macrocell.
Both the PAL22V10C and PAL22VPlOC
provide 12 dedicated input pins and 10 I/O
pins (see Logic Block Diagram). By selecting each I/O pin as either permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O allows this selection.
The PAL22V10C and PAL22VPlOC
feature
variable
product
term
architecture, where 8 to 16 product terms
are allocated to each output. This
structure permits more applications to be
Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration
1/0 5
1/04
1/0 3
1/02
v10c-1
Pin Configurations
LCC{L)
Top View
PLCC (J)/CLCC (y)
Top View
0086
__ Ii:
099"",,,,,,
--~yyg'~
I
I
1/02
1/°3
1/0 4
Vss
Vss
I
1/05
1/06
1/°7
I
Vss
I
- - en en- '" co
-ff)fJl QQ
PAL is a registered trademark of Monolithic Memories Inc.
4-76
v10c-3
PAL22VIOC
PAL22VPIOC
7~PRESS
·
- _ , SEMICONDUCTOR
Functional Description (continued)
Programmable Macrocell
implemented with these devices than with other PAL devices that
have fixed number of product terms for each output.
Additional features include common synchronous preset and
asynchronous reset product terms. They eliminate the need to use
standard product terms for initialization functions
The PAL22V1OC and PAL22VPIOC each has 10 programmable
output macrocells (see Macrocell figure). On the PAL22VIOC
two fuses (C1 and Co) can be programmed to configure output in
one of four ways. Accordingly, each output can be registered or
combinatorial with an active HIGH or active LOW polarity.
The feedback to the array is also from this output (see Figure 1).
An additional fuse (C 2 ) in the PAL22VPlOC provides for two
feedback paths (see Figure 2).
Both the PAL22V1OC and PAL22VPIOC automatically reset on
power-up. In addition, the preload capability allows the output registers to be set to any desired state during testing.
A security fuse is provided on each of these two devices to prevent
copying of the device fuse pattern.
Programming
The PAL22VIOC and PAL22VP1OC can be programmed using the
QuickPro II programmer available from Cypress Semiconductor
and also with Data 110, Logical Devices, STAG and other programmers. Please contact your local Cypress representative for
further information.
With the programmable macrocells and variable product term architecture, the PAI22V1OC and PAI22VP1OC can implement logic
functions in the 700 to 800 gate array complexity, with the inherent advantages of programmable logic.
II
tI)
Q
..J
Q.
Macrocell
OE
r----------------------,
I
I
I
I
I
I
I
I
I
I
AR
r--+----------4-~
OUTPUT
SELECT
Q 1-------1
MUX
D
Q
CP
...-.-----1
Key:
AR =
SP =
OE =
CP =
SP
INPUT/
FEEDBACK
MUX
S1
~
L _ _ _ _ _ _ _ _ _ _MACROCELL
____________
I
I
I
I
~
v10c-4
Output Macrocell Configuration
C2[1]
Cl
Co
Output 'JYpe
0
0
0
Registered
Active LOW
0
0
1
Registered
Active HIGH
Registered
X
1
0
Combinatorial
Active LOW
I/O
Polarity
Feedback
Registered
X
1
1
Combinatorial
Active HIGH
I/O
1
0
0
Registered
Active LOW
1/0[1]
1
0
1
Registered
Active HIGH
1/0[1]
Notes:
1. PAL22VPlOC only.
4-77
Asynchronous RESET
Synchronous PRESET
Output Enable
Clock Pulse
~
PAL22VIOC
PAL22VPIOC
:;~
'jE
~?
CYPRESS
SEMICONDUCTOR
AR
AR
C2(1]= 0
C2[1]=
C1 =0
C1 = 0
Co = 1
Co = 0
0
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
C2 (1]= X
C1 = 1
Co = 0
C2(1] = X
C1 = 1
Co = 1
v10c-8
v10c-7
I/O FEEDBACK, COMBINATORIAL, ACTIVE-LOW OUTPUT
I/O FEEDBACK, COMBINATORIAL, ACTIVE-HIGH OUTPUT
Figure 1. PAL22VI0C and PAL22VPI0C Macrocell Configurations
AR
SP
SP
v10c-10
v10c-9
I/O FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
I/O FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
Figure 2. Additional Macrocell Configurations for the PAL22VPI0C
4-78
PAL22VIOC
PAL22VPIOC
.~
:~ CYPRESS
,
SEMlCONDUcrOR
Selection Guide
Commercial
lee (rnA)
22VIOC-6
22VPIOC-6
190
22VIOC-7
22VPIOC-7
190
22VIOC-IO
22VPIOC-IO
190
Military
22VIOC-12
22VPIOC-12
22VIOC-15
22VPIOC-15
190
190
190
190
12
tpD (ns)
Commercial
Military
6.0
7.5
10
10
12
15
ts (ns)
Commercial
Military
3.0
3.0
3.6
3.6
4.5
4.5
7.5
teo (ns)
Commercial
Military
5.5
6.0
7.5
9.5
Commercial
117
111
7.5
90
9.5
fMAX (MHz)
90
71
Military
a
10
71
t/)
Q
57
..J
a..
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to Vee
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to Vee
DC Input Current .................... - 30 rnA to +5 rnA
(except during programming)
DC Program Voltage .............................. 10V
Operating Range
Ambient
Temperature
Range
Commercial
Military[2]
O°C to +70°C
Vee
5V±5%
- 55°C to +125°C
5V±5%
DC Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
= - 3.2 rnA
IOH = - 2 rnA
IOL = 16 rnA
IOL = 12 rnA
IOH
Vee = Min.,
VIN = VIR or VIL
Vee = Min.,
VIN = VIR or VIL
Min.
Com'l
V
Com'l
0.5
V
Mil
VIR
Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for All Inputs [3]
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for All Inputs[3]
IIX
Input Leakage Current
Vss S VIN S 2.7V, Vee
II
Maximum Input Current
VIN
= Max.
= Max., Vsss VOUTS Vee
= Max., VOUT = 0.5V[4J
Vee = Max., VIN = GND, Outputs Open
Units
Mil
VIL
= Vee, Vee = Max.
Max.
2.4
2.0
- 250
V
0.8
V
50
fAA
fAA
Com'l
100
Mil
250
Ioz
Output Leakage Current
Vee
-'- 100
100
fAA
Ise
Output Short Circuit Current
Vee
-30
- 120
rnA
lee
Power Supply Current
Com'l'
190
rnA
Mil
190
Notes:
2. tA is the "instant on" case temperature.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
4-79
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground
degradation.
PAL22VIOC
PAL22VPIOC
~
.
7~PRESS
-===:,
SEMlCONDUcrOR
Switching Characteristics[S]
22VIOC-6
22VIOC-7
22VIOC-IO
22VIOC-12
22VIOC-15
22VPIOC-6 22VPIOC-7 22VPIOC-IO 22VPIOC-12 22VPIOC-15
Parameters
Description
Min. Max. Min. Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
2
10
2
12
2
15
ns
2
12
2
15
ns
2
12
2
15
ns
9.5
1
10
ns
tPD
Input to Output Propagation
Delay[6]
1
6
2
7.5
tEA
Input to Output Enable Delay
1
6
2
7.5
2
10
tER
Input to
Delay[7J
1
6
2
7.5
2
10
5.5
1
6.0
1
7.5
1
Output
Disable
tco
Clock to Output Delay[6]
1
ts
Input or Feedback Set-Up Time
3
3
3.6
4.5
7.5
ns
tH
Input Hold Time
0
0
0
0
0
ns
tp
External Clock Period
(teo + ts)
8.5
9
11.1
14
17.5
ns
tWH
Clock Width HIGH[8]
3
3
3
3
6
ns
tWL
Clock Width LOW[8]
3
3
3
3
6
ns
fMAXl
External Maximum Frequency
(l/(tco + tS))[9]
117
111
90
71
57
MHz
fMAX2
Data Path Maximum Frequency
(l/(tWH + twL))[8,1O]
166
166
166
166
83
MHz
fMAX3
Internal Feedback Maximum
Frequency (l/(tCF + tS))[ll]
142
133
100
83
66
MHz
tCF
Register Clock to Feedback
Inputl12J
tAW
Asynchronous Reset Width
7.5
8.5
10
12
15
ns
tAR
Asynchronous Reset Recovery
Time
4
5
6
7
10
ns
tAP
Asynchronous Reset to
Registered Output Delay
2
tSPR
Synchronous Preset Recovery
Time
4
5
6
7
10
ns
tpR
Power-Up Reset Timel13]
1
1
1
1
1
f.ts
4
4.5
11
2
12
6.4
2
12
7.5
2
14
7.5
2
20
ns
ns
Capacitance[8]
Parameters
Description
Max.
C1N
Input Capacitance
8
CoUT
Output Capacitance
10
Notes:
5. AC test loadused for all parameters except where noted.
6. This specification is guaranteed for all device outputs changing state in
a given access cycle.
7. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max.
8. Tested initially and after any design or process changes that may affect
these parameters.
9. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
10. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
Units
pF
pF
11. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
12. This parameter is calculated from the clock period at fMAX internal
(fMAX3) as measured (see Note 11) minus ts.
13. The registers in the PAL22VlOC/PAL22VPlOC have been designed
with the capability to reset during system power-up. Following powerup, all registers will be reset to a logic LOW state. The output state will
depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the
rise in Vee must be monotonic and the timing constraints depicted in
power-up reset waveforms must be satisfied.
4-80
PAL22VIOC
PAL22VPIOC
";~
_'iECYPRESS
--::=-?
SEMICONDUCIOR
AC Test Loads and Waveforms
R1238.1l
ALL INPUT PULSES
3.0V----
5V:Fl(319.1lMIL)
OUTPUT
90%
R2
INCLUDING
JIG AND
SCOPE
I-=
GND
V3~.Il.ll MIL
CL
-=
(
)
THEVENIN EQUIVALENT
99.1l
OUTPUT ~ 2_08V = Vthc
Commercial
Parameter
Vx
tER(-)
1.5V
P/D
50pF
J!K!L/Y
2.6V
tER(+)
Output Waveform-Measurement Level
VOH O.5V
t
VOL
O.5V
Vx
O.5V
I
Equivalent to:
Package
15 pF[15]
vl0c-16
vl0c-ll
I
Equivalent to:
CL[14]
THEVENIN EQUIVALENT
1.5V
tEA(+)
136.1l
OUTPUT ~ 2.13V = Vthm
1.5V
tEA(-)
Military
Vx
O.5V
~
~
t
~
~
~
~
Vx
vl0c-12
vl0c-13
VOH
vl0c-14
VOL
vl0c-15
Switching Waveform
R~~Mi~~~'B
---.. . . . . . .
FEEDBACK
SYNCHRONOUS -----~~
PRESET
~~~~
CP -------------"1
ASYNCHRO~E~~¥ ______________~~--------~JI
REGISTERED
OUTPUTS _____________L.J/.~
COMBINATORIAL
OUTPUTS _______________________L.J/.~
vl0c-17
Power-Up Reset Waveform[13]
-------------------------------------------------------1
POWER ________________
4V
..,.1--______
VCC
tpR -------....,.~I
-
REGISTERED
ACTIVE LOW
OUTPUT
-------------------------------------------------~f7-----------------------------------------------------------------~~
CLOCK
vl0c-18
Notes:
14. CL = 5 pF for tER measurement for all packages_
15. For high-capacitive load applications (CL = 50pF), usePAL22VlOCF/
PAL22VPI0CF.
4-81
•
U)
Vx
Q
..J
c..
PAL22VIOC
PAL22VPIOC
=g.;t~PRFSS
~,
SEMICONDUcrOR
Preload Waveform[16]
Vpp
PIN 13 (16)
--h
\
t DPRl
~
PIN 2 (3)
PIN 3 (4)
'I
PIN 6 (7)
PIN 8 (10)
~
\
J
\
,
PIN 9 (11)
PRELOAD DATA
PINS 14-23
(17-21,23-27)
t DPR2
t DPR2
t DPR2
_J
Il.
CLOCK PIN 1 (2)
t DPR1
t DPR2
t DP R2
I,
t DPR1
7
."
I
_\I
t DPR1
-'"
"'
t DPR2
t DPR1
) -V~
/
"
/
~
t DPR1
IL
t DPR1
~
~
7
I
OUTPUTS
DISABLED
t DPR1
PRELOAD
DATA
CLOCKED
IN
PRELOAD DATA
VILP or VIHP(17)
tDpFll.
I"
REGISTE RS
PRELOAOED,
OUTPUT
ENABLE o
PRELOAD
DATA
REMOVED
vl0c-19
Notes:
16. Pins 4 (5), 5 (6), 7 (9) at VILP; Pins 10 (12) and 11 (13) at VIHP; Vee (Pin 24 (1 and 28)) at VeeI'
17. Pins 2-8 (3-7, 9, 10), 10 (12), 11 (13) can be set at VIHP or VILP to insure asynchronous reset is not active.
D/K/P (J/LIY) Pinouts
Forced Level on Register Pin
During Preload
Register Q Output State
After Preload
VIHP
HIGH
VILP
LOW
Name
Description
Min.
Max.
Unit
Vpp
Programming Voltage
9.25
9.75
V
tDPRl
Delay for Preload
1
tDPR2
Delay for Preload
0.5
VILP
Input LOW Voltage
0
0.4
VIHP
Input HIGH Voltage
3
4.75
Vecp
Vcc for Preload
..•
4.75
Ils
Ils
-
,-
-
5.2)
V
V
. .
v
4-82
PAL22VIOC
PAL22VPIOC
Functional Logic Diagram for PAL22VIOC/PAL22VPIOC
1--t>>--o--------------------------------------------------~
ARIII1I411i181i1l12~1116I1i21°~124Iii218I1i312~136Iii41°1l~1I~~~~~~:t~
I~;
gp~C :';1~(27)
I 23
"'-i~
OE
(2)
I---
OE
~
o
2
=tb22
...L.....L..tb
~ cell
~L....,........,
OE
(3)
o
;::'
>-_r-....>----1-1 Macro-
21
a~
(25)
~~
11
3
(4)
(26)
cell
OE
o
::tb
=th
TT
20
cell
(5)
'.-<1-
~~I
13
4
OE
o
(24)
TT'
>-____-1-1
15
5
(6)
OE
~
19
(23)
cell
::rJ"
e::r
~TT
o
~
cell
(21)
15
6
(7)
OE
::
o
7
,...L-l-tb
~
=tb
~)----I-I~~
13
(9)
3-
OE
o
~
8
(10)
-f':;
11
O~
cell
~TT
~
~
9
(11)
10
9
~
0:11111111111111111111
:
IP
~
7
'-'
(12)
('1...--
~)
16
(19)
=~r15
=n
I) cell
'-rT"
cell
(18)
14
~(17)
"" SP
11
(13)
~~;~~~~m==mF=~~#=~~~=ffi~~~~~====~~~----------D/K/P (JIUY> Pinouts
4-83
v10c-20
13
(16)
•
o
Q
..J
0..
PAL22VIOC
PAL22VPIOC
iwr~
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.4
~ 1.2
o
N
:«:J 1 0
::E •
0.8
1.2
u 1.4
w
a:
oz
V
V"'
~
~
----
.2
0
w
N
::J
1.2
«
::E
a: 1.0
0
z
1----
0.8
TA = 25°C
0.6
4.0
I
4.5
5.0
SUPPLY VOLTAGE
5.5
0.6
-55
6.0
M
NORMALIZED PROPAGATION
DELAYvs. TEMPERATURE
1.2...------r------.....,
z
o
o
i=
.s
~
~ 1.1~---~-----~
a:
J/K/I../Y
-0.2
0
w
~ 1.0 ~---~:::;;""..----~
«
~ 0 -0.6
~ c
(!).!'
0.91'-----;--------i
0.8'-------'-----_--'
- 55
25
125
~
f2 -0.8
-J.
()
-1.0
~
00 1.1~---~---~~~
81.1
~ 1.0
::E
«
o
0
a:
z 0.9 t-~'----;--------i
0.8L....._ _ _...L.._ _ _ _ _- l
- 55
25
125
AMBIENT TEMPERATURE (0C)
/
2
5.0
5.5
6.0
M
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
1.2
~
1.1
w
N
~ 1.0
V
4.5
SUPPLY VOLTAGE
-~
"-.
~
::E
a:
o
DIP PACKAGES
3 4 5
I
I
6
7
Z
0.9
0.8
4.0
8 9 10
4.5
5.0
5.5
SUPPLY VOLTAGE
NORMALIZED CLOCK TO OUTPUT
TIME vs. SUPPLY VOLTAGE
w
N
::J 1.0
::E
w
0.9
0.8
4.0
6.0
M
NORMALIZED CLOCK TO
OUTPUT TIME vs. TEMPERATURE
1.2
0
N
Z
NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2...------r------.....,
o
a:
o
'" ------~
~ 1.0
::E
o
/"
/
/
-1.2 1
AMBIENT TEMPERATURE (0C)
w
.., ~ ......... /
wa:
\
N
."" ~ ~
,
PACKAGES
o
a:
1.1
TYPICAL CORRECTION TO tpD
AND teo vs. NUMBER OF
OUTPUTS SWITCHING
8 ~-0.4 ."" ..-
::E
~
o
25
125
AMBIENT TEMPERATURE (0C)
()~
~
NORMALIZED PROPAGATION
DELAYvs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT vs.
AMBIENT TEMPERATURE
1.4.------.-------,
"
"-~
a:
0
~
w 1.2
-............
N
::J
...............
«
::E
a: 1.1
0
Z
z 0.9
0.8
4.0
1.3
0
,
4.5
5.0
SUPPLY VOLTAGE
5.5
M
6.0
25
125
AMBIENT TEMPERATURE (0C)
v10c-21
4-84
PAL22VIOC
PAL22VPIOC
~
_~PRFSS
~,
SEMICONDUCTOR
1Ypical DC and AC Characteristics (continued)
DELTA tpn, teo vs.
OUTPUT LOADING
« 120
8.0,-----r----.----r----,
en
.s
8
.s 105
~
~
6.01---t-----\---+-7"''---I
90
~ 75
J
::>
~
z
4.01----+----17'<---+----1
Ci5
w
o
/
I-
6
Il.
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
60
45
I-
2.01-----j,o'<-----\--:::::;oo""""'r----I
25
50
75
ir
30
o
15 1/
~
100
/
/
60
,~
'"",
w
1/
/
~
50
::>
()
40
w
~
~ 30
"' \
::>
o
Vee = 5.0V TA = 25°C -
I
o
0.0
I-
z
II
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
70
.s
/
OUTPUT SOURCE CURRENT
vs.VOLTAGE
«
4.0
en
I-
::>
20
~
10
6
0
0.0
1.0
2.0
II
\
\
3.0
4.0
OUTPUT VOLTAGE (V)
v10c-22
Ordering Information
tpD
fMAX
Icc
(mA)
190
(ns)
6
7.5
(MHz)
117
111
10
90
12
15
71
57
Ordering Code
PAL22VI0C-6JC
PAL22VlOC-7DC
PAL22VI0C-7JC
PAL22VI0C-7PC
PAL22VI0C-7YC
PAL22VlOC-I0DC
PAL22VlOC-lOJC
PAL22VlOC-lOPC
PAL22VlOC-I0YC
PAL22VlOCM -lODMB
PAL22VlOCM -lOKMB
PAL22VlOCM -lOLMB
PAL22VlOCM -lOYMB
PAL22VlOC-12DC
PAL22VlOC-I2JC
PAL22VlOC-12PC
PAL22VlOC-12YC
PAL22VI0CM -12DMB
PAL22VlOCM -12KMB
PAL22VlOCM -12LMB
PAL22VI0CM -12YMB
PAL22VlOCM -15DMB
PAL22VlOCM -15KMB
PAL22VlOCM -15LMB
PAL22VlOCM -15YMB
Package
Name
J64
D14
J64
P13
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
K73
L64
Y64
4-85
Package 'JYpe
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Commercial
Military
Commercial
Military
Military
PAL22VIOC
PAL22VPIOC
~
~~pRF.SS
~, SEMICONDUCTOR
Ordering Information (continued)
ICC
(rnA)
190
tpD
(ns)
6
7.5
fMAX
(MHz)
117
111
10
90
12
15
71
57
Ordering Code
PAL22VPlOC-6JC
PAL22VPlOC-7DC
PAL22VPlOC-7JC
PAL22VPlOC-7PC
PAL22VPlOC-7YC
PAL22VP10C-lODC
PAL22VPlOC-lOJC
PAL22VPlOC-lOPC
PAL22VP10C-10YC
PAL22VPlOCM -lODMB
PAL22VPlOCM -lOKMB
PAL22VPlOCM -10LMB
PAL22VPlOCM -10YMB
PAL22VPlOC-12DC
PAL22VPlOC-12JC
PAL22VPlOC-12PC
PAL22VPlOC-12YC
PAL22VPlOCM -12DMB
PAL22VPlOCM -12KMB
PAL22VP10CM -12LMB
PAL22VPlOCM -12YMB
PAL22VPlOCM -15DMB
PAL22VPlOCM -15KMB
PAL22VPlOCM -15LMB
PAL22VPlOCM -15YMB
Package
Name
J64
D14
J64
P13
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
J64
P13
Y64
D14
K73
L64
Y64
D14
K73
L64
Y64
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Parameters
Subgroups
VOH
1,2,3
VOL
VIH
1,2,3
1,2,3
VIL
IIX
1,2,3
1,2,3
Ioz
1,2,3
Icc
1,2,3
Switching Characteristics
Parameters
Subgroups
tpD
7, 8, 9, 10, 11
teo
7, 8, 9, 10, 11
ts
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tH
Document #: 38-A-00020-D
4-86
Package 'IYPe
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Chip Carrier
24-Lead (300-Mil) CerDIP
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Pin Ceramic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Commercial
Military
Commercial
Military
Military
PAL22VIOCF
PAL22VPIOCF
CYPRESS
SEMICONDUCTOR
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD = 7.5 ns
-tsu = 3 ns
- fMAX = 100 MHz
- Drives SO-pF load (Cd
• "No Connect" PLCC pinout
• Up to 22 inputs and 10 outputs for
more logic power
• Variable product terms
- 8 to 16 per output
• 10 user-programmable output
macrocells
- Output polarity control
- Registered or combinatorial
operation
Universal PAL® Device
- 2 new feedback paths
(PAL22VPI0CF)
• Synchronous PRESET, asynchronous
RESET, and PRELOAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse
Functional Description
The
Cypress
PAl22VlOCF
and
PAl22VPlOCF are second-generation
programmable array logic devices. Using
BiCMOS process and Ti-W fuses, the
PAL22V10CF and PAL22VP1OCF use the
familiar sum-of-products (AND-OR) logic structure and a new concept, the programmable macrocell.
Both the PAl22VlOCF and PAl22VP1OCF
provide 12 dedicated input pins and 10 I/O
pins (see Logic Block Diagram). By selecting each I/O pin as either permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O allows this selection.
The PAL22V10CF and PAL22VP10CF
feature variable product-term architecture, where 8 to 16 product terms are
allocated to each output. This structure
permits more applications to be implemented with these devices than with other
PAL devices that have fixed number of
product terms for each output.
Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration
Vss
CP/I
10cl·l
Pin Configuration
PLCC(J)
Top View
__ ~~9g'~
I
NC
- - :$ ~-
gg
PAL is a registered trademark of Monolithic Memories Inc.
QuickProII is a trademark of Cypress Semiconductor Corporation.
4-87
10cl-2
•
en
C
..J
Q.
.=r:
PAL22VIOCF
PAL22VPIOCF
~
oj; CYPRESS
~,
SEMICONDUCTOR
Functional Description (continued)
Programmable Macrocell
Additional features include common synchronous preset and
asynchronous reset product terms. They eliminate the need to use
standard product terms for initialization functions
The PAL22VIOCF and PAL22VPlOCF each has 10 programmable output macrocells (see Macrocell figure). On the
PAL22VlOCF two fuses (C1 and Co) can be programmed to configure output in one offourways. Accordingly, each output can be
registered or combinatorial with an active HI G H or active LOW
polarity. The feedback to the array is also from this output (see
Figure 1). An additional fuse (Cz) in the PAL22VPIOCF provides for two feedback paths (see Figure 2).
Both the PAL22VlOCF and PAL22VPlOCF automatically reset
on power-up. In addition, the preload capability allows the output
registers to be set to any desired state during testing.
A security fuse is provided on each of these two devices to prevent
copying of the device fuse pattern.
With the programmable macrocells and variable product term
architecture, the PAL22VlOCF and PAL22VPIOCF can implement logic functions in the 700 to 800 gate array complexity,
with the inherent advantages of programmable logic.
Programming
The PAL22VIOCF and PAL22VPIOCF can be programmed using
the QuickPro II programmer available from Cypress SemiconductorandalsowithDataI/O,LogicaIDevices,STAGandotherprogrammers. Please contact your local Cypress representative for further information.
1M
Macrocell
OE
r----------------------,
I
I
I
I
I
I
I
I
I
I
AR
r--4----------~~
D
QI--------~
OUTPUT
SELECT
MUX
Q 1--....----1
CP
Key:
AR =
SP =
OE =
CP =
SP
INPUT!
FEEDBACK
MUX
S1
~
I
C1
Co --------~------+_--------------------------~
C2 [1] _ _ _ _ _ _-+L_____
.....J_ _ _ _ _ _ _MACROCELL
___
____________
I
I
I
~
10cl·3
Output Macrocell Configuration
C2[1]
Cl
Co
0
0
0
0
0
1
Registered
Active HIGH
Registered
X
1
0
Combinatorial
Active LOW
I/O
Output1Ype
Registered
Polarity
Active LOW
Feedback
Registered
X
1
1
Combinatorial
Active HIGH
I/O
1
0
0
Registered
Active LOW
1/0[1]
1
0
1
Registered
Active HIGH
110[1]
Notes:
1. PAL22VPlOCF only.
4-88
Asynchronous RESET
Synchronous PRESET
Output Enable
Clock Pulse
--.
PAL22VIOCF
PAL22VPIOCF
~
--=-,
'Iii;
CYPRESS
SEMICONDUCTOR
AR
AR
C 2 [11= 0
C1 = 0
C 2 [11= 0
C1 =0
Co = 1
Co = 0
1Ocf-4
10cf-5
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
II
tn
C
...I
a.
C2[11= X
C1 = 1
Co = 0
C2[11= X
C1 = 1
Co = 1
10cf-6
10cf-7
I/O FEEDBACK, COMBINATORIAL, ACTIVE-LOW OUTPUT
I/O FEEDBACK, COMBINATORIAL, ACTIVE-HIGH OUTPUT
Figure 1. PAL22VI0CF aud PAL22VPI0CF Macrocell Configurations
AR
AR
SP
SP
10cf-a
10cf-9
I/O FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
I/O FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
Figure 2. Additional Macrocell Configurations for the PAL22VPI0CF
4-89
PAL22VIOCF
PAL22VPIOCF
~
:::::z,.
~pRF.SS
--=' ,
SEMICONDUcrOR
Selection Guide
22VIOCF-7
22VPIOCF-7
22VIOCF-IO
22VPIOCF-IO
lee (rnA)
tpD (ns)
190
190
7.S
10
ts (ns)
3.0
3.6
teo (ns)
7.0
7.5
fMAX(MHz)
100
90
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 6SoC to + lS0°C
Ambient Temperature with
Power Applied ...................... - SSoC to +12SoC
Supply Voltage to Ground Potential ....... - O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . .. - O.SV to Vee
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . .. - O.SV to Vee
DC Input Current. . . . . . . . . . . . . . . . . . .. - 30 rnA to + S rnA
(except during programming)
DC Program Voltage .............................. lOV
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
SV±S%
Range
Commercial
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
I IOH = -
VOH
Output HIGH Voltage
Vee = Min., VIN = VIH or VIL
VOL
Output LOW Voltage
Vee = Min., VIN = VIH or VIL
VIH
Input HIGH Voltage
GuaranteedInputLogicalHIGHVoltageforAlIInputs[2j
3.2 rnA
I IOL = 16 rnA
VIL
Input LOW Voltage
Guaranteed Input Logical LOW Voltage for All Inputs[2j
IIX
Input Leakage Current
Vss ~ VIN ~ 2.7V, Vee = Max.
Max.
2.4
V
0.5
2.0
- 2S0
Units
V
V
0.8
V
SO
!lA
100
!lA
II
Maximum Input Current
VIN = Veo Vee = Max.
Ioz
Output Leakage Current
Vee = Max., Vss~ VOUT~ Vee
-100
100
!lA
Isc
Output Short Circuit Current
Vee = Max., VOUT = 0.SV[3j
- 30
- 120
rnA
lee
Power Supply Current
Vee = Max., VIN = GND, Outputs Open
190
rnA
Notes:
2. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
3.
4-90
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.5V has
been chosen to avoid test problems caused by tester ground
degradation.
PAL22VIOCF
PAL22VPIOCF
. .~
~~CYPRESS
~, SEMICONDUCTOR
Switching Characteristics[4]
22VIOCF-7
22VPIOCF-7
22VIOCF-IO
22VPIOCF-IO
Min.
Max.
Min.
Max.
Units
tpD
Input to Output Propagation Delay[5]
2
7.5
2
10
ns
tEA
Input to Output Enable Delay
2
7.5
2
10
ns
tER
Input to Output Disable Delay[6]
2
7.5
2
10
ns
tco
Clock to Output Delay[5]
1
7.0
1
7.5
ns
ts
Input or Feedback Set-Up Time
3
3.6
ns
tH
Input Hold Time
0
0
ns
tp
External Clock Period (tco
10
11.1
ns
tWH
Clock Width HIGH[7]
3
3
ns
tWL
Clock Width LOW[7]
3
3
ns
fMAXl
External Maximum Frequency
(l/(tco + tS))[8]
100
90
MHz
fMAX2
Data Path Maximum Frequency
(l/(tWH + twL))[7,9]
166
166
MHz
fMAX3
Internal Feedback Maximum Frequency
(l/(tCF + tS))[lO]
133
100
MHz
Parameters
Description
+ ts)
tCF
Register Clock to Feedback Input[ll]
tAW
Asynchronous Reset Width
tAR
4.5
6.4
ns
8.5
10
Asynchronous Reset Recovery Time
5
6
tAP
Asynchronous Reset to Registered
Output Delay
2
tSPR
Synchronous Preset Recovery Time
5
6
ns
1
1
f.,ts
Power-Up Reset
tpR
Timd 12]
12
2
ns
ns
ns
12
Capacitance[7]
Parameters
Description
Max.
Units
CIN
Input Capacitance
8
pF
COUT
Output Capacitance
10
pF
Notes:
4. AC test load used for all parameters except where noted.
5. This specification is guaranteed for all device outputs changing state in
a given access cycle.
6. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max.
7. Tested initially and after any design or process changes that may affect
these parameters.
8. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
9. This specification indicates the guaranteed maximum frequency at
which an individual output register can be cycled.
10. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate. This parameter is tested periodically by sampling production
product.
11. This parameter is calculated from the clock period at fMAX internal
(fMAX]) as measured (see Note 10) minus ts.
12. The registers in the PAL22VlOCF/PAL22VPlOCFhave been designed
with the capability to reset during system power-up. Following powerup, all registers will be reset to a logic LOW state. The output state will
depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper operation, the
rise in Vee must be monotonic and the timing constraints depicted in
power-up reset waveforms must be satisfied.
4-91
•
U)
Q
...I
~
PAL22VIOCF
PAL22VPIOCF
C-jy:CYPR&SS
"""=IIIr'
SEMICONDUcrOR
AC Test Loads and Waveforms
OUTP:
;::g
~
INCLUDING
JIG AND
SCOPE
I-=
ALL INPUT PULSES
3.0V----
A2l7OQ
-=
GND
10cf-15
1Ocf-1 0
I
Equivalent to:
THEVENIN EQUIVALENT
.990
OUTPUT
o------vw-----o
Parameter
Vx
tER(-)
1.5V
tER(+)
2.6V
tEA(+)
1.5V
tEA(-)
1.5V
2.08V = Vthc
Commercial
Output Waveform-Measurement Level
VOH O.5V
t F;
VOL
O.5V
~
Vx
O.5V
~
Vx
O.5V
~
~
t F;
Vx
10cf-11
Vx
10cf-12
VOH
10cf-13
VOL
10cf-14
Switching Waveform
R~~~i€~~9J
----..--
FEEDBACK
SYNCHRONOUS _ _ _....I..V
PRESET
I+-~'----.I
CP------....II
ASYNCHRONOUS _ _ _ _ _ _ _~~----~JI
RESET
REGISTERED
OUTPUTS _ _ _ _ _ _ _'-lL.~
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _ _'-lL.~
10cf-16
Power-Up Reset Waveform[13]
,~~----------------------------------------------------Vcc
POWER __________________
4V,
REGISTERED
ACTIVE LOW
OUTPUT
~~.~-----__ tpR------------~.1
-------------------------r~---------
------------------------~~
CLOCK
10cl-17
Notes:
13. CL = 5 pF for tER measurement for all packages.
4-92
PAL22VIOCF
PAL22VPIOCF
:~PRESS
==:=.
~ ~
SEMUCONDUCTOR
Preload Waveform[14]
PIN 13 (16)
V pp
-k
t OPR1
......\
V1LP
V 1HP
PIN 2 (3)
V1LP
V1HP
PIN 3 (4)
V1LP
V1HPm
If
PIN 6 (7)
\
If
PIN8 (10)
V1LP
VIHP~
..I
~
V1LP Q.
Vpp
\
If
PIN9(11)
PRELOAD DATA
PINS 14-23
(17-21,23-27)
t OPR2
I
CLOCK PIN 1 (2)
J
t OPR1
_\I
\
'"
t OPR1
I,
7
t OPR1
~.. \
t OPR1
'"
t OPR1
L
t OPR1
V1HP
Vi'-
/
/
t OPR2 t OPR2
t OPR2
">-
t OPR2 t OPR2
\
7
r---:.
tOPR1
t OPR1
1\
I
OUTPUTS
DISABLED
PRELOAD
DATA
CLOCKED
IN
PRELOAD DATA
VILP or VIHP[15]
REGISTE RS
PRELOAOED,
OUTPUT
ENABLED
PRELOAD
DATA
REMOVED
10cl-18
Notes:
14. Pins 4 (5), 5 (6), 7 (9) at VILP; Pins 10 (12) and 11 (13) at VIHP; Vee (Pin 24 (1 and 28» at VeeI'
15. Pins 2-8 (3-7, 9, 10), 10 (12), 11 (13) can be set at VIHP or VILP to insure asynchronous reset is not active.
DIP (J) Pinouts
Forced Level on Register Pin
During Preload
Register Q Output State
After Preload
VIHP
HIGH
VILP
LOW
Name
Description
Min.
Max.
Vpp
Programming Voltage
9.25
9.75
Unit
V
tDPRl
Delay for Preload
1
tDPR2
Delay for Preload
0.5
VILP
Input LOW Voltage
0
0.4
V
VIHP
Input HIGH Voltage
3
4.75
V
Vccp
V cc for Preload
4.75
5.25
V
!ls
!ls
4-93
PAL22VIOCF
PAL22VPIOCF
~-:;z,
~=CYPRESS
~, SEMICONDUCTOR
Functional Logic Diagram for PAL22VIOCF/PAL22VPIOCF
1
(2)
--1)
0
4
8
12
16
20
24
28
40
~(1...-
OE
0
~CI-
·
9
2
OE
0
(3)
··
:3-..
3-"
3~
~11
(4)
OE
0
cell
=th
~ cell
23
(27)
22
(26)
L.....--.-
::±r
21
cell
~
(25)
TT
::~
~~
~~
~
cell
I>
~
13
4
=bb
~
··
(5)
36
;....,.
·
Lt::7·
3
32
AR
OE
0
OE
0
20
(24)
IT
=~
~
~
~
:::::
·
cell
I>
~
(6)
OE
0
6
(7)
-r::
:::::
= ....
·
~
2
~13
~
a~
B:..../
~~
11
8
::~
~
cell
16
(19)
II
J>CI- =th
OE
0
··
15
(18)
cell
9
'rr
OE
0
·
10
(12)
18
(21)
17
(20)
cell
~
·
9
(11)
~
~
OE
0
(10)
cell
¥- IT
::±r
¥- IT
15
·
7
::=~
~
=l
OE
0
(9)
IT
~
15
5
19
(23)
~<1--
~7
=bb
cell
14
(17)
~
~SP
.A
11
13
(13)
DIP (J) Pinouts
4-94
(16)
10cf·19
.
PAL22VIOCF
PAL22VPIOCF
:~PRESS
~,
SEMICONDUcrOR
lYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
()
Cl
W
N
«
~
1.0
II:
oZ
0.8
~
V
~
2
V
Cl
W
1.2
N
::J
II:
0
SUPPLY VOLTAGE
"
------Cl
W
II:
M
r----~-----~
Cl
z
o
o
J
«
r----~~----~
a
;:-0.4
8
V
:::: 0 -0.6
!;;(
jo£----~-----~
0
li:~
-1.0
0.8 '--_ _ _....L..._ _ _ _ _...J ~
- 55
25
125
/'
r-----~---~~~
81.1
W
~ 1.0 r-----¥-'------~
~ 1.0
~
~
II:
o
II:
z 0.9
I--~'----~-----~
0.8 L -_ _ _ _....L..._ _ _ _ _...J
-55
25
125
AMBIENT TEMPERATURE (0C)
W
~ 1.0
Z
0.9
0.8
4.0
'"
6.0
M
i'.....
-~
~
~
II:
o
I
I
3 4 5
I
I
6
7
Z
8
0.9
0.8
4.0
9 10
\.
N
5.5
1.1
N
/
DIP PACKAGES
I
2
~
Cl
4.5
5.0
5.5
SUPPLY VOLTAGE
6.0
M
NORMALIZED CLOCK TO
OUTPUT TIME vs. TEMPERATURE
1.4 ; - - - - - - , - - - - - - - - ,
1.2
W
«
vV'
"/'
a 1.3
~
"
4.5
--......~
Cl
W
N
1.2
::J
«
~
II:
1.1
0
Z
5.0
SUPPLY VOLTAGE
5.5
M
6.0
25
125
AMBIENT TEMPERATURE (0C)
10cf-20
4-95
•
f/)
5.0
1.2
~~
NORMALIZED CLOCK TO OUTPUT
TIME vs. SUPPLY VOLTAGE
Cl
Cl
V
i"""
---
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
NUMBER OF DEVICE OUTPUTS
CHANGING STATE PER ACCESS CYCLE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2 ; - - - - - - , - - - - - - - - ,
1.1
l/
-1.2 1
AMBIENT TEMPERATURE (0C)
...... ~
10'"
~ ~ -0.8
z 0.9
o
.......
(!)~
~
II:
o
00
PACKAGES
4.5
SUPPLY VOLTAGE
OUTPUTSS~TCHING
II:~
II:
WII:
W
N
::J 1.0
0.8
4.0
25
125
AMBIENT TEMPERATURE (0C)
~ ~ -0.2
1.1
0.9
TYPICAL CORRECTION TO tpD
AND teo vs. NUMBER OF
F
~
----
~
0.6
-55
6.0
NORMALIZED PROPAGATION
DELAY vs. TEMPERATURE
1.2 ; - - - - - - , - - - - - - - - ,
~
N
Z
I
5.5
1\
0
z
5.0
1.1
«
1.0
TA = 25°C
4.5
~
::J 1.0
«
~
0.8
0.6
4.0
1.2
1.4
()
21.2
::J
NORMALIZED PROPAGATION
DELAY vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT vs.
AMBIENT TEMPERATURE
1.6
C
...J
B.
PAL22VIOCF
PAL22VPIOCF
~
.
9~PRESS
~, SEMICONDUCTOR
1Ypical DC and AC Characteristics (continued)
DELTA tpo. teo vs.
OUTPUT LOADING
2.0 r - - - - , - - - , - - - - - r - - - - - ,
.§.. 105
en
..s
I-
a]
0
(5
g
,/
90
~ 75
=>
::
~
« 120
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
z
0.0
Ci5
w
a.
l-
o=>
25
50
75
15
100
I-
Z
~
cc
:x::
Z
Ci5
/
Vee = 5.0V TA = 25°C -
I
I
o
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
CAPACITANCE (pF)
50
B 40
1
45
70
.§.. 60
/
60
~ 30
Cl
«
/
OUTPUT SOURCE CURRENT
vs.VOLTAGE
4.0
"
'"
'~
'"
30
"" \
~ 20
g:
o=>
10
o
0.0
1.0
2.0
\
3.0
\
4.0
OUTPUT VOLTAGE (V)
10cl-21
Ordering Information
ICC
(mA)
190
(ns)
7.5
fMAX
(MHz)
100
10
90
tAA
Ordering Code
PAL22VlOCF -7DC
PAL22VlOCF -7JC
PAL22V10CF -7PC
PAL22VPlOCF -7DC
PAL22VPlOCF -7JC
PAL22VP10CF -7PC
PAL22VlOCF-10DC
PAL22VlOCF -lOJC
PAL22VlOCF -IOPC
PAL22VP10CF -IODC
PAL22VP10CF -lOJC
PAL22VPlOCF -10PC
Package
'IYpe
D14
J64
P13
D14
J64
P13
D14
J64
P13
D14
J64
P13
Document #: 38-A -00020
4-96
Package
'JYpe
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
Operating
Range
Commercial
Commercial
PALC22VIOD
CYPRESS
SEMICONDUCTOR
Flash Erasable,
Reprogrammable CMOS PAL@ Device
Features
• Advanced second-generation PAL architecture
• Lowpower
- 90 rnA max. commercial (10 ns)
-130 rnA max. commercial (7.5 ns)
• CMOS Flash EPROM technology for
electrical erasability and reprogrammability
• Variable product terms
- 2 x (8 through 16) product terms
• User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
~ 7.5 ns commercial version
5 ns teo
5 ns ts
7.5 ns tpD
133-MHz state machine
-10 ns military and industrial versions
6 ns teo
6 ns ts
10 ns tpD
nO-MHz state machine
-15-ns commercial and military
versions
- 25-ns commercial and military
versions
• High reliability
- Proven Flash EPROM technology
-100% programming and functional
testing
Functional Description
The Cypress PALC22VlOD is a CMOS
Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the
programmable macrocell.
The PALC22VlOD is executed in a 24-pin
300-mil molded DIP, a 300-mil cerDIp, a
28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier' and provides up to 22 inputs and 10
outputs. The 22VIOD can be electrically
Logic Block Diagram (PDIP/CDIP)
I/Og
1/°7
1/°8
1/°5
1/°6
1/°4
I/~
I/Oa
V10D-1
Pin Configuration
LCC
PLCC
Top View
Top View
__ c;:u885
uz;>:;:,:;:,
4 3 2 ~1: 282726
25
NC
I
7
8
885
__ C;:U
uz;>:;:,:;:,
1/°2
1/°3
1/04
I
NC
I
I
N/C
9
1/05
1/°6
1/°7
10
11
4 3 2~1: 282726
25
24
23
22
1/02
1/°3
1/04
N/C
1/05
1/06
1/0 7
12131415161718
- - cnu:!J'Z
Ol
co
V10D-2
- - cnu~z
~~
PAL is a registered trademark of Monolithic Memories Inc.
4-97
Ol
co
gg
V10D-3
II
tn
C
..J
Q.
g~-4
PALC22VIOD
~ ill CYPRESS
~!F SEMICONDUCTOR
Functional Description (continued)
erased and reprogrammed. The programmablemacrocell provides
the capability of defining the architecture of each output individually. Each of the 10 potential outputs may be specified as "re~is
tered" or "combinatorial." Polarity of each output may also be Individually selected, allowing complete flexibility of output
configuration. Further configurability is provided through "array"
configurable "output enable" for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by
the programmable array.
PALC22V10D features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms p~r
output. By providing this variable structure, the PALC22VlOD IS
optimized to the configurations found in a majority of applications
without creating devices that burden the product term structures
with unusable product terms and lower performance.
Additional features of the Cypress PALC22VlOD include a syn~
chronous preset and an asynchronous reset product term. These
product terms are common to all macrocells, eliminating the need
to dedicate standard product terms forinitializationfunctions. The
device automatically resets upon power-up.
The PALC22VlOD featuring programmable macrocells and variable product terms provides a device with the flexibility to im~le
ment logic functions in the 500- to 800-gate-array compleXity.
Since each of the 10 output pins may be individually configured as
inputs on a temporary or permanent basis, functions requiring up
to 21 inputs and only a single output and down to 12 inputs and 10
olitputs are possible. The 10 potential outputs are enabled using
product terms. Any output pin may be permanently selected as an
output or arbitrarily enabled as an output and an input through the
selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual programmable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information
to the array. This information is available for establishing the next
result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is
disabled, the signal present on the I/O pin is made available to the
array. The flexibility provided by both programmable product term
control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable
logic.
Along with this increase in functional density, the Cypress
PALC22VlOD provides lower-power operation through the use of
CMOS technology, and increased testability with Flash reprogrammability.
Configuration Table 1
Registered/Combinatorial
Configuration
C.
Co
0
0
1
Registered/Active LOW
0
1
Combinatorial/Active LOW
Combinatorial/Active HIGH
0
1
"1
Registered/Active HIGH
Macrocell
~----------------------I
AR
>-~-----------.-;
D
Q 1--------1
OUTPUT
SELECT
MUX
CP
SP
INPUT/
FEEDBACK
MUX
C1
Co -------+-----------~~~~~----~
MACROCELL
I
I
I
I
~----------------------~
4-98
Vl0D-4
~
~~PRESS
~_, SEMICONDUCTOR
PALC22VIOD
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 24 to Pin 12) ...................... - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to +7.0V
DC Input Voltage ............ " ........ - O.5V to +7.0V
Output Current into Outputs (LOW) .............. 16 rnA
DC Programming Voltage ......................... 12.5V
Latch-Up Current ............ -;--;--.. . . . . . . . . . .. >200 rnA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............. >2001V
Operating Range
Range
Commercial
Ambient
Temperature
O°C to +75°C
Vee
5V±5%
Military[l]
- 55°C to +125°C
5V ±10%
Industrial
- 40°Cto +85°C
5V ±10%
II
U)
C
Electrical Characteristics Over the Operating Rangel 2]
Description
Parameter
VOH
..J
Output HIGH Voltage
Min.
Test Conditions
Vee = Min.,
VIN = VIR or VIL
IOH = - 3.2 rnA
Com'l
IOH = - 2 rnA
Mil/lnd
IOL = 16 rnA
Com'l
IOL = 12 rnA
Mil/lnd
Max.
Unit
2.4
V
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIR or VIL
VIR
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
2.0
VIL[4]
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs[3]
-0.5
0.8
V
IIX
Input Leakage Current
Vss~ VIN ~ Vee,
-10
10
!!A
Ioz
Output Leakage Current
Vee = Max., Vss~ VOUT~ Vee
Ise
Output Short Circuit Current Vee = Max., VOUT = 0.5V[5,6]
IeC!
Standby Power Supply
Current
Iee2 lo ]
Operating Power Supply
Current
Vee = Max.
10,15,25 ns
Vee = Max.,
VIN=GND,
Outputs Open in 7.5 ns
Unprogrammed
15,25 ns
Device
10 ns
Vee = Max., VIL =
Ov, VIR = 3V,
Output Open, Device Programmed as
a lO-Bit Counter,
f=25MHz
10,15,25 ns
0.5
V
-40
40
f.!A
- 30
- 90
rnA
rnA .
Com'l
90
130
rnA
Mil/lnd
120
rnA
120
rnA
110
rnA
140
rnA
130
rnA
130
rnA
Com'l
7.5 ns
15,25 ns
V
Mil/lnd
10 ns
Capacitance[6]
Parameter
C IN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
Min.
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
Max.
10
10
Unit
pF
pF
Endurance Characteristics[6]
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.
5.
6.
4-99
Not more than one output should be tested at a time. Duration of the short
circuit should not be more than one second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.
Q.
tii~~
PALC22VIOD
Commercial Switching Characteristics PALC22VIOD[2,7]
22VIOD-7
Parameter
Description
22VIOD-IO
22VIOD-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
3
7.5
3
10
3
15
ns
tpD
Input to Output
Propagation Delay[8, 9]
tEA
Input to Outp'ut
Enable Delay[lO]
8
10
15
ns
tER
Input to Output
Disable Delay[11)
8
10
15
ns
tco
tSI
Clock to Output Delayl~, ~J
Input or Feedback
Set-UpTime
Synchronous Preset Set-Up Time
Input Hold Time
External Clock
Period (tco + ts)
Clock Width HIGHlbJ
Clock Width LOWL6J
External Maximum
Frequency (l/(tco + tS»[12]
Data Path Maximum
Frequency
(l/(tWH + twd)[6, 13)
Internal Feedback
Maximum Fre~uency
(l/(tCF + ts»[ ,14]
Register Clock to
Feedback Input[6, 15]
8
ns
ns
tS2
tH
tp
tWH
tWL
fMAX1
fMAX2
fMAX3
tCF
tAW
tAR
tAP
tSPR
tpR
Asynchronous Reset Width
Asynchronous Reset
Recovery Time
Asynchronous Reset to
Registered Output Delay
Synchronous Preset
Recovery Time
Power-Up
Reset Timel6, 16)
2
5
5
2
6
7
2
10
6
0
10
7
0
12
10
0
20
ns
ns
ns
3
3
100
3
3
76.9
6
6
55.5
ns
ns
MHz
166
142
83.3
MHz
133
111
68.9
MHz
2.5
8
5
4.5
3
15
10
10
6
12
ns
ns
20
13
ns
ns
6
8
10
ns
1
1
1
IlS
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters excepttER and tEA ( +). Part (b) of AC Test Loads and Waveforms is used
for tER. Part (c) of AC Test Loads and Waveforms is used for tEA ( +).
8. Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.
10. The test load of part (a) of AC Test Loads and Waveforms is used for
measuring tEA ( -). The test load of part (c) of AC Thst Loads and
Waveforms is used for measuring tEA + only. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and
measurement reference levels.
11. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOR min. Or a previous LOW level has risen to 0.5 volts
above VOL max. Please see part (e) of AC Test Loads and Waveforms
for enable and disable test waveforms and measurement reference
levels.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can operate.
13. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
14. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
15. This parameter is calculated from the clock period at fMAX internal
(lIfMAX3) as measured (see Note 11 above) minus ts.
16. The registers in the PALC22VlOD have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a logic LOW state. The output state will depend on
the polarity of the output buffer. This feature is useful in establishing
state machine initialization. To insure proper operation, the rise in Vee
must be monotonic and the timing constraints depicted in Power-Up
Reset Waveform must be satisfied.
4-100
~
~.~
;1=
==e.
PALC22VIOD
CYPRESS
-:::;;;;, SEMICONDUcrOR
Military and Industrial Switching Characteristics PALC22VIOD[2, 7]
22VIOD-IO
Parameter
Description
Min.
22VIOD-15
Max.
Min.
Max.
22VIOD-25
Min.
Max.
Unit
tpD
Input to Output
Propagation Delay[9]
10
15
25
ns
tEA
Input to Output Enable Delay[ll]
10
15
25
ns
tER
Input to Output Disable Delay[ll]
10
15
25
ns
tco
Clock to Output Delay[9]
7
8
15
ns
tS1
Input or Feedback Set-Up Time
6
10
18
tS2
Synchronous Preset Set-Up Time
7
10
18
ns
tH
Input Hold Time
0
0
0
ns
tp
External Clock Period (tco
12
20
33
ns
tWH
Clock Width HIGH[6]
3
6
14
ns
+ ts)
ns
tWL
Clock Width LOW[6]
3
6
14
ns
fMAX1
External Maximum Frequency
(l/(tco + tS))[12]
76.9
50.0
30.3
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + twL))[6,13]
142
83.3
35.7
MHz
fMAX3
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6, 14]
111
68.9
32.2
MHz
tCF
Register Clock to
Feedback Inputl6, 14]
tAW
Asynchronous Reset Width
10
15
25
ns
tAR
Asynchronous Reset
Recovery Time
6
12
25
ns
tAP
Asynchronous Reset to
Registered Output Delay
tSPR
Synchronous Preset
Recovery Time
8
20
25
ns
tpR
Power-Up Reset Timd6, 16]
1
1
1
f-ts
3
13
4.5
12
20
ns
25
ns
AC Test Loads and Waveforms
R1 238il
R1 238il
OUTP~~TI~19nMI~
~78~~~NG I-=
CL
-=
SCOPE
5V : = F l ( 3
il MIL)
19
R2
OUTPUT
170il
(236il
MIL)
~78~~~NG
SCOPE
(a)
R2
J.
5 pF
-=
170il
(236il
MIL)
}50n
OUTPUT Of----+-------
1
r
CL
-=
(1.2Kil
MIL)
V10D·5
(b)
4-101
(c)
I
(I)
Q
..J
a..
~
~~PRF.SS
~, ~CONDUcrOR
PALC22VIOD
AC Test Loads and Waveforms (continued)
ALL INPUT PULSES
3.0V---90%
GND
V10D-6
(d)
I
Equivalent to:
I
THEVENIN EQUIVALENT (Commercial)
Equivalent to:
99n
THEVENIN EQUIVALENT (Military)
136n
OUTPUT ~ 2.08V = Vthc
OUTPUT
o-----wv------o
2.13V = Vthm
V10D-7
CL
Load Speed
7.5, 10, 15,
25 ns
50pF
V10D-8
Package
Parameter
Vx
PDIp,CDIp,
PLCC,LCC
tER(-)
1.5V
tER(+)
2.6V
tEA(+)
OV
tEA(-)
Vthc
Output Waveform-Measurement Level
VOH O.5V
VOL
Vx
Vx
t
O.5V
~
1.5V
~
O.5V
t
~
~
~
~
VX
V10D-9
Vx
V10D-10
VOH
V10D-11
VOL
V10D-12
(e) Test Waveforms
Switching Waveform
R~~Mi~~~'6
----"'"
FEEDBACK
SYNCHRONOUS _ _ _-'-v
PRESET
14-_14--.1
CP
ASYNCHRONOUS
RESET _ _ _ _ _ _ _~~---~I-.I1
REGISTERED
OUTPUTS _ _ _ _ _ _ _""--II..¥
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _~.¥
V10D-13
Power-Up Reset Waveform[16]
CLOCK
t
~---------------------------VCC
90%
R
POWER
10%0
SUPPLY VOLTAGE - - - - - - . . ; - .
t~
V10D-14
4-102
. .~
CYPRESS
SEMICONDUCTOR
PALC22VIOD
---=-,':J.
Functional Logic Diagram for PALC22VIOD
-rf)
4
1
1
20
4
~8
3
36
40
AR
DE
~(1- ;:~
·
0
-D7
cell
1>(1- ::b
DE
0
2
··
::b
::b
::b
Jrr""T""""""r-
~
0
··
~
=t-'"
:3~
11
DE
0
=r--..
~
=t-..
~
15
IT
::±r
=r
=
IT
::±r
IT
::±r
.......;
0
··
=r--.
cell
18
cell
17
cell
16
~
15
DE
a
0
:::r--.
=~
==
··
13
DE
:::
0
:::r--.
·
>
~ TT
11
OE
~~
0
·
9
9
DE
::b
15
> cell
Tr
1>6-;~
0
10
19
cell
==
DE
8
TT
=l
·
7
20
cell
=~
==
13
0
6
TT
::;f--"
DE
5
21
cell
::l
·
4
22
cell
9
DE
3
23
7·
cell
14
-"T""
SP
./I
1
13
V10D-15
4-103
•
en
C
..J
0..
-
~~
PALC22VIOD
~1= CYPRESS
,
SEMICONDUCIOR
Ordering Information
(rnA)
tpD
(ns)
ts
(ns)
tco
(ns)
130
7.5
5
5
ICC
10
90
150
10
15
90
120
15
25
6
6
7.5
7.5
15
7
7
10
Ordering Code
Package
Name
PALC22VlOD-7JC
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOD-7PC
P13
24-Lead (300-Mil) Molded DIP
PALC22VlOD-10JC
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOD -lOPC
P13
24-Lead (300-Mil) Molded DIP
PALC22VlOD-lODMB
D14
24-Lead (300-Mil) CerDIP
PALC22VlOD-10JI
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOD-10KMB
K73
24-Lead Rectangular Cerpack
PALC22V10D-lOLMB
L64
28-Square Leadless Chip Carrier
PALC22VlOD-lOPI
P13
24-Lead (300-Mil) Molded DIP
PALC22VlOD-15JC
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOD -15PC
P13
24-Lead (300-Mil) Molded DIP
PALC22VlOD-15DMB
D14
24-Lead (300-Mil) CerDIP
PALC22VlOD-15JI
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOD-15KMB
K73
24-Lead Rectangular Cerpack
PALC22VlOD-15LMB
L64
28-Square Leadless Chip Carrier
10
PALC22V10D-15PI
P13
24-Lead (300-Mil) Molded DIP
PALC22V10D-25DMB
D14
24-Lead (300-Mil) CerDIP
PALC22VlOD - 25JI
J64
28-Lead Plastic Leaded Chip Carrier
PALC22VlOD - 25KMB
K73
24-Lead Rectangular Cerpack
PALC22VlOD- 25LMB
L64
28-Square Leadless Chip Carrier
PALC22V10D-25PI
P13
24-Lead (300-Mil) Molded DIP
15
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIR
VIL
IIX
Ioz
Icc
Switching Characteristics
Parameter
Subgroups
tpD
9,10,11
9,10,11
9,10,11
9,10,11
teo
ts
tH
Package 1Ype
Document #: 38-00185-F
4-104
Operating
Range
Commercial
Commercial
Military/
Industrial
Commercial
Military/
Industrial
PAL22VIOG
PAL22VPIOG
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Ultra high speed supports today's and
tomorrow's fastest microprocessors
-tpD = 5ns
-tsu = 2.5 ns
- fMAX 153.8 MHz
• Reduced ground bounce and undershoot
• PLCC and LCC packages with additional Vee and Vss pins for lowest
ground bounce
• Up to 22 inputs and 10 outputs for
more logic power
• Variable product terms
- 8 to 16 per output
• 10 user-programmable output
macrocells
- Output polarity control
=
Universal PAL® Device
- Registered or combinatorial
operation
- 2 new feedback paths
(PAL22VP10G)
• Synchronous PRESET, asynchronous
RESET, and PRELOAD capability for
flexible design and testability
• High reliability
- Proven Ti-W fuse technology
- AC and DC tested at the factory
• Security Fuse
Functional Description
The
Cypress
PAL22VlOG
and
PAL22VPlOG are second-generation programmable array logic devices. Using BiCMOS process and Ti-W fuses, the
PAL22VlOG and PAL22VPlOG use the familiar sum-of-products (AND-OR) logic
structure and a new concept, the programmable macrocell.
Both the PAL22VlOG and PAL22VPlOG
provide 12 dedicated input pins and 10 I/O
pins (see Logic Block Diagram). By selecting each I/O pin as either permanent or
temporary input, up to 22 inputs can be
achieved. Applications requiring up to 21
inputs and a single output, down to 12 inputs and 10 outputs can be realized. The
output enable product term available on
each I/O allows this selection.
The PAL22VlOG and PAL22VPlOG
feature variable product term architecture,
where 8 to 16 productterms are allocated to
each output. This structure permits more
applications to be implemented with these
devices than with other PAL devices that
have fixed number of product terms for
each output.
Logic Block Diagram and PDIP (P)/CDIP (D) Pin Configuration
Vss
CP/I
1/°9
I/0a
1/°7
1/06
1/03
1/°4
1/°5
1/02
1/°1
VCC
1/°0
Pin Configurations
v10g-1
LCC{L)
Top View
DIP (P, D)
Top View
CP/I
uu 86
__ lE
u:Y~""""
--~yyg'g
vee
1/0 0
1/0 1
1/0 2
1/0 3
1/0 4
1105
1/0 6
1/0 7
II0a
I/Og
Vss
PLCC(J)
Top View
1/0 2
1/0 3
1/0 4
I
vss
vss
I
1/0 5
1/°6
1/0 7
-
I
v10g-2
-
U)
00-
~~
PAL is a registered trademark of Monolithic Memories Inc.
4-105
m co
gg
I
1/°2
1/°3
1/0 4
vss
vss
I
1105
1/°6
1/°7
-
v10g-3
-
00 00-
:§!l:§!l
m
>--o----------------------------------------------~
(2) ~:AR~1141181112111161120112141281132113161140111~~~~~~Q
§~ ~ .;;'11
OE
c
OE
~
o
2
=tb22
(26)
L....,.........
,...L-I-tb
o
b.......
::=
~L../
21
Macrocell
~~~
(25)
~ "=~20
3~11
O~
(4)
23
(27)
~ cell
~
OE
(3)
~
I----
cell
(5)
r-~1T
13
4
OE
(24)
~>-------I-I:;tb19
sa
TT
~, =tb
o
~rr- >
15
5
(6)
OE
o
~
I>
cell
~~Tr
15
6
(7)
./
(23)
OE
o
~
,...L-I-tb
~~~
TT
~ ,)-----+-1 M~~rt
7
--f':::
§-'...-<1---- ~
13
o~
(9)
8
(10)
---r::
~
=~16(19)
S""'}------I-I,...L-I-tb
cell
O~
~
15
(18)
~
:::::bb14
W ...
OE
o
,.....7
(12) -
M~~f10-
~
9
10
17
(20)
~~
11
1=
(11)
~~)
,vcell
---1~
~=t~~fI:::::tm:::JIm:~;tt:::=tttt=:tttt:=tm=::::W~~~~wt:======:::s~~~
11
(13)
DIP (J/L) Pinouts
4-112
(17)
~
.
~~PRESS
-.F
PRELIMINARY
PAL22VIOG
PAL22VPIOG
SEMICONDUCTOR
Ordering Information
Icc
(rnA)
190
tpD
(ns)
5
5.5
6
fMAX
(MHz)
153.8
142.8
117
7.5
111
10
90
76
90
Icc
(rnA)
190
tpD
(ns)
5
5.5
6
fMAX
(MHz)
153.8
142.8
117
7.5
111
10
90
76
90
Ordering Code
PAL22V10G- 5JC
PAL22V10G-5PC
PAL22V10G-6JC
PAL22VlOG-6PC
PAL22V10G-7DC
PAL22VlOG-7JC
PAL22V10G-7PC
PAL22V10G-7LMB
PAL22VlOG-lODC
PAL22V10G-10JC
PAL22VlOG-10PC
PAL22VlOG-lODMB
PAL22V10G-lOLMB
Ordering Code
PAL22VPlOG-5JC
PAL22VP10G- 5PC
PAL22VPlOG-6JC
PAL22VPlOG-6PC
PAL22VP10G-7DC
PAL22VPlOG-7JC
PAL22VPlOG-7PC
PAL22VPlOG-7LMB
PAL22VPlOG-lODC
PAL22VPlOG-lOJC
PAL22VP10G-lOPC
PAL22VPlOG-lODMB
PAL22VP10G-lOLMB
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristerics
Package
Name
J64
P13
J64
P13
D14
J64
P13
L64
D14
J64
P13
D14
L64
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDiP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Square Leadless Chip Carrier
24-Lead (300-Mil) CerDiP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDiP
28-Pin Square Leadless Chip Carrier
Package
1YPe
J64
P13
J64
P13
D14
J64
P13
L64
D14
J64
P13
D14
L64
Package
1Ype
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDiP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Pin Square Leadless Chip Carrier
24-Lead (300-Mil) CerDiP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDiP
28-Pin Square Leadless Chip Carrier
Package 1Ype
Switching Characteristics
Parameters
Subgroups
Parameters
Subgroups
VOH
1,2,3
tpD
7, 8, 9, 10, 11
VOL
VIR
1,2,3
teo
ts
7,8,9, 10, 11
VIL
IIX
1,2,3
1,2,3
tH
7,8,9,10,11
Ioz
1,2,3
IcC
1,2,3
1,2,3
7, 8, 9, 10, 11
Document #: 38-A-00044
4-113
Operating
Range
Commercial
Commercial
Commercial
Commercial
Military
Commercial
•
en
C
Military
Operating
Range
Commercial
Commercial
Commercial
Commercial
Military
Commercial
Military
..oJ
D.
This is an abbreviated datasheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the CY7C335.
CY7C330
CYPRESS
SEMICONDUCTOR
Features
• 1\velve I/O macrocells each having:
- registered, three-state I/O pins
- input register clock select multiplexer
- feed back multiplexer
- output enable (OE) multiplexer
• All twelve macrocell state registers
can be hidden
• User-contigurable state registersJK, RS, T, or D
• One input multiplexer per pair of I/O
macrocells allows I/O pin associated
with a hidden macrocell state register
to be saved for use as an input
• Four dedicated hidden registers
• Eleven dedicated, registered inputs
CMOS Programmable
Synchronous State Machine
• Three separate clocks-two inputs,
one output
• Common (pin 14-controlled) or
product term-controlled output enable for each I/O pin
• 256 product terms-32 per pair of
macrocells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
• 66-MHz operation
- 3-ns input set-up and 12-ns clock to
output
-15-ns input register clock to state
register clock
• Lowpower
- 130mAIcc
• 28-pin, 300-mil DIP, LCC
• Erasable and reprogrammable
Functional Description
The CY7C330 is a high-performance, erasable, programmable, logic device (EPLD)
whose architecture has been optimized to
enable the user to easily and efficiently
construct very high performance synchronous state machines.
The unique architecture of the CY7C330,
consisting of the user-configurable output
macrocell, bidirectional I/O capability, input registers, and three separate clocks, enables the user to design high-performance
state machines that can communicate either with each other or with microprocessors over bidirectional parallel buses of
user-definable widths.
Logic Block Diagram
0E/l1O
19
18
17
1/0 9
1/0 8
10/CK2
16
I/Os
Vss
Vee
CKl
ClK
1/0 0
1/°3
c330-1
Selection Guide
Maximum Operating Frequency,
fMAX (MHz)
Commercial
Power Supply Current IcC! (rnA)
Commercial
7C330-66
66.6
Military
140
7C330-50
50.0
7C330-40
50.0
40.0
Document #: 38-00064-E
4-114
7C330-28
28.5
130
130
160
Military
7C330-33
33.3
150
150
==:..- --.~~
CY7C331
':lE~ CYPRESS
,
SEMICONDUCTOR Asynchronous Registered EPLD
Features
• 1Welve I/O macrocells each having:
- One state flip-flop with an XOR
sum-of-products input
- One feedback flip-flop with input
coming from the I/O pin
- Independent (product term) set,
reset, and clock inputs on all
registers
- Asynchronous bypass capability on
all registers under product term
control (r = s = 1)
- Global or local output enable on
three-state I/O
- Feedback from either register to
the array
• 192 product terms with variable distribution to macrocells
• 13 inputs, 12 feedback I/O pins, plus 6
shared I/O macrocell feedbacks for a
total of 31 true and complementary
inputs
• High speed: 20 ns maximum tpD
• Security bit
• Space-saving 28-pin slim-line DIP
package; also available in 28-pin
PLCC
• Lowpower
- 90 rnA typical Icc quiescent
-180 rnA Icc maximum
- UV-erasable and reprogrammable
- Programming and operation 100%
testable
Functional Description
The CY7C331 is the most versatile PLD
available for asynchronous designs. Central resources include twelve full D-type
flip-flops with separate set, reset, and clock
capability. For increased utility, XOR
gates are provided at the D-inputs and the
product term allocation per flip-flop is
variably distributed.
I/O Resources
Pins 1 through 7 and 9 through 14 serve as
array inputs; pin 14 may also be used as a
global output enable for the I/O macrocell
three-state outputs. Pins 15 through 20 and
23 through 28 are connected to I/O macrocells and may be managed as inputs or outputs depending on the configuration and
the macrocell OE terms.
Logic Block Diagram
Ig
I/Og
I/Os
GND
Is
10
Vee
GND
1/°6
1/00
1/0 5
C331-1
Selection Guide
Generic Part
Number
CY7C331-20
CY7C331-25
CY7C331-30
CY7C331-40
ICCI (rnA)
Com'l
Mil
130
120
160
150
150
tpD (ns)
Com'l
20
25
ts (ns)
Mil
25
30
40
4-115
tco (ns)
Com'l
12
Mil
Com'l
12
15
20
25
Mil
25
15
30
20
40
II
en
C
..J
~
~PRESS
_~CONDUcrOR
Pin Configuration
CY7C331
The D-type flip-flop that is fed from the array (Le., the state flipflop) has a logical XOR function on its input that combines a single
product term with a sum(OR) of a number of product terms. The
single product term is used to set the polarity of the output or to
implement toggling (by including the current output in the product
term).
The Rand S inputs to the flip-flops override the current setting of
the '0' output. The Sinput sets '0' true and the R input resets '0'
(sets it false). If both Rand S are asserted (true) at once, then the
output will follow the input ('0' :::: 'D') (see Table 1).
PLCC
Top View
'£>~-='p~gg
O,....C\I,....ocnco
~~~~~oo
Table 1. RS Truth Table
C331-2
--~gg",,,,
s
o
Q
1
1
1
1
1
D
R
I/O Resources (continued)
o
It should be noted that there are two ground connections (pins 8
and 21) which, together with Vee (pin 22) are located centrally on
the package. The reason for this placement and dual-ground structure is to minimize the ground-loop noise when the outputs are
driving simultaneously into a heavy capacitive load.
The CY7C331 has twelve I/O macrocells (see Figure 1 ). Each macrocell has two D-type flip-flops. One is fed from the array, and one from
the I/O pin. For each flip-flop there are three dedicated product terms
driving the R, S, and clock inputs, respectively. Each macrocell has
one input to the array and for each pair of macrocells there is one
shared input to the array. The macrocell input to the array may be
configured to come from the '0' output of either flip-flop.
o
Shared Input Multiplexer
The input associated with each pair of macrocells may be configured by the shared input multiplexer to come from either macrocell; the '0' output ofthe flip-flop coming from the I/O pin is used
as the input signal source (see Figure 2).
Product Term Distribution
The product terms are distributed to the macrocells such that 32
product terms are distributed between two adjacent macrocells.
TO PIN 14 (INVERTED)
OE PTERM
OUT SET PTERM
TO I/O PIN
OUT ClK PTERM
OUT RESET PTERM
IN ClKPTERM
IN SETPTERM
IN RESET PTERM
XOR PTERM
OR PTERMS
TO INPUT BUFFER
INPUT FLIP-FLOP
TO SHARED
INPUTMUX
C331-3
TO PIN 14 (INVERTED)
Figure 1. I/O Macrocell
4-116
.~.
~~PRF.SS
~., SEMICONDUCTOR
CY7C331
Product Term Distribution (continued)
The pairing of macro cells is the same as it is for the shared inputs.
Eight of the product terms are used in each macrocell for set, reset,
clock, output enable, and the upper part of the XOR gate. This
leaves 16 product terms per pair of macrocells to be divided between the sum-of-products inputs to the two state registers. The
following table shows the I/O pin pairing for shared inputs, and the
product term (PT) allocation to macrocells associated with the I/O
pins (see Table 2).
The CY7C331 is configured by three arrays of configuration bits
(CO, C1, C2). For each macrocell, there is one CO bit and one C1
bit. For each pair of macrocells there is one C2 bit.
Table 2. Product Term Distribution
Macrocell
Pin Number
Product Terms
0
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
20
19
18
4
12
6
10
8
8
8
8
10
6
12
4
17
16
15
11
There are six C2 bits, providing one C2 bit for each pair of macrocells. The C2 bit controls the shared input multiplexer; if the C2 bit
is not programmed, then the input to the product term array comes
from the upper macrocell (A). If the C2 bit is programmed, then
the input comes from the lower macrocell (B).
The timing diagrams for the CY7C331 cover state register, input
register, and various combinational delays. Since internal clocks
are the outputs of product terms, all timing is from the transition of
the inputs causing the clock transition.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 28 to Pin 8 or 21) ................... - O.5V to +7.0V
DC Input Voltage ....................... - 3.0V to +7.0V
Output Current into Outputs (LOW) ............... 12 rnA
Static Discharge Voltage ........................ > 1500V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
DC Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . .. 13.0 V
OUTPUT FROM
LOGIC ARRAY
MACROCELLA
FEEDBACK TO
LOGIC ARRAY
INPUT TO ---~
LOGIC ARRAY ---0-...1
There are twelve CO bits, one for each macrocell. If CO is programmed for a macrocell, then the three-state enable (DE) will be
controlled by pin 14 (the global DE). If CO is not programmed,
then the DE product term for that macrocell will be used.
Thereare twelve C1 bits, one for each macrocelL The C1 bit selects
inputs for the product term (PT) array from either the state register
(if the bit is unprogrammed) or the input register (if the bit is programmed).
Q-OUTPUT FROM
INPUT REGISTER OF
I/O MACROCELL A
Operating Range
Range
Commercial
Q-OUTPUT FROM
INPUT REGISTER OF
I/O MACROCELL B
,--___....L..-_....,
OUTPUT FROM
LOGIC ARRAY
O°C to +70°C
Vee
5V ± 10%
- 55°C to +125°C
5V ± 10%
Note:
1.
MACROCELL B
FEEDBACK TO
LOGIC ARRAY
Military[l]
Ambient
Temperature
---O-...J
C331-4
Figure 2. Shared Input Multiplexer
4-117
TA is the "instant on" case temperature.
II
f·~=
~
CY7C331
SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangef2]
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., VIN = VIH or VIL
IOH = - 3.2 rnA (Com'l), IOH = - 2 rnA (Mil)
VOL
Output LOW Voltage
Vee = Min., VIN = VIHor VIL
IOL = 12 rnA (Com'l), IOL = 8 rnA (Mil)
VIR
Input HIGH Voltage
Guaranteed HIGH Input, all Inputs[3]
VIL
Input LOW Voltage
GuaraI).teed LOW Input, all Inputs[3]
IIX
Input Leakage Current
Vss < VIN < Vee, Vee
Ioz
Output Leakage Current
IsC
Output Short Circuit
Current[4]
Vss < VOUT < Vee, Vee = Max.
Vee = Max., VOUT = 0.5V[5]
Iecl
Standby Power Supply
Current
IeC2
Power Sup~ly. Current at
Frequency 4, 6]
Vee = Max., VIN
Outputs Open
Min. Max.
2.4
= GND,
Vee = Max., Outputs Disabled
(in High Z State)
Device Operating at fMAX External (fMAXI)
V
0.5
V
0.8
V
2.2
= Max.
Unit
V
-10
+10
IlA
-40
+40
!lA
-30
-90
rnA
Com'I-20
130
rnA
Com'l -25, -35
120
Mil-25
160
Mil-30, -40
150
Com'l
180
Mil
200
rnA
rnA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
= 1 MHz
VOUT = 2.0Vat f = 1 MHz
VIN = 2.0V at f
Notes:
2. See the last page ofthis specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
4. Tested initially and after any design or process changes that may affect
these parameters.
S.
6.
4-118
Max.
Unit
10
pF
10
pF
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
Because these input signals are controlled by product terms, active input polarity may be of either polarity. Internal active input polarity has
been shown for clarity.
~
.
--=-.:
~iE
CY7C331
CYPRESS
SEMICONDUCTOR
AC Test Loads and Waveforms
R13130
OUTP~~
R13130
§=l(4700
I
R2 2080
(3190 Mil)
50 pF
INCLUDING _
JIG AND
SCOPE
_
-
3.0V
1
_
-
(b)
..:5. 5 ns
C331-5
THEVENIN EQUIVALENT (Commercial)
OUTPUT
~
90%
R2 2080
(3190 Mil) GND
5 PF
INCLUDING _
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
OUTP~~ T I ( 4 7 0Mil)0
Mil)
C331-6
Equivalent to:
OUTPUT
2.00V = Vthc
II
THEvENIN EQUIVALENT (Military)
~
2.02V = Vthm
C331-7
C331-8
In
C
...I
a.
Parameter
tpXZ(-)
tPXZ(+)
Vx
1.5V
Output Waveform-Measurement Level
VOH
O.5V~
O.5V~
2.6V
VOL
tpZX(+)
0.5V~
Vthc
Vx
tpZX(-)
tER(-)
tER(+)
Vthc
1.5V
Vx
VOH
O.5V~
O.5V~
O.5V~
2.6V
VOL
tEA(+)
O.5V~
Vthc
Vx
tEA(-)
Vthc
Vx
o.sJ
~~
VX
~~
C331-9
Vx
C331-10
~~
VOH
C331-11
~~
VOL
C331-12
~~
Vx
C331-13
~~
Vx
C331-14
~~
VOH
C331-15
~~
VOL
C331-16
(c) Test Waveforms and Measurement Levels
Switching Characteristics Over the Operating Rangel2]
Commercial
-20
-25
Max.
Unit
tpD
Input to Output Propagation Delay[7]
20
25
ns
tleo
Input Register Clock to Output Delay[8]
35
40
ns
tIOH
Output Data Stable Time from Input Clock[8]
5
5
ns
tIS
Input or Feedback Set-Up Time to Input Register Clock[8]
2
2
ns
tIH
Input Register Hold Time from Input Clock[8]
11
13
ns
Parameter
Description
Min.
4-119
Max.
Min.
=nz :~
-===.,
CY7C331
'': CYPRESS
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 2) (continued)
Commercial
-20
Parameter
Description
Min.
tIAR
Input to Input Register Asynchronous Reset Delay[8)
tIRW
Input Register Reset Width[4, 8)
35
Input Register Reset Recovery Timd 4, 8)
35
tIRR
tIAS
tISW
tISR
tWH
tWL
Input to Input Register Asynchronous Set Delay[8)
Input Register Set Width[4, 8)
Input Register Set Recovery Timd4, 8)
Input and Output Clock Width HIGH[8, 9, 10)
Input and Output Clock Width LOW[8, 9, 10)
-25
Max.
Min.
35
Max.
40
40
ns
ns
40
35
Unit
ns
40
35
40
ns
ns
35
40
ns
12
12
15
ns
15
fMAXI
Maximum Frequency with Feedback in Input Registered Mode
(l/(tlca + tIS»[l1)
27.0
23.8
ns
MHz
fMAX2
Maximum Frequency Data Path in Input Registered Mode (Lowest
of 1/tlca, 1/(tWH + twL), or 1/(tIS + tIH)[8)
28.5
25.0
MHz
tIOH-tIH33X
Output Data Stable from Input Clock Minus Input Register Input
Hold Time for 7C330 and 7C332[12, 13)
0
0
ns
tca
tOH
ts
Output Register Clock to Output Delay[9)
Output Data Stable Time from Output Clock[9)
3
Output Register Input Set-Up Time to Output Clock[9)
12
3
12
tH
Output Register Input Hold Time from Output Clock[9)
8
8
tOAR
Input to Output Register Asynchronous Reset Delay[9)
tORW
tORR
Output Register Reset Width[9)
tOAS
tosw
tOSR
tEA
25
20
Output Register Reset Recovery Timd9)
Input to Output Register Asynchronous Set Delay[9)
Output Register Set Width[9)
Output Register Set Recovery Timd9)
20
ns
ns
25
ns
25
ns
ns
ns
25
25
20
20
20
20
20
ns
ns
ns
25
25
ns
tER
tpzx
Input to Output Enable Delay[14, 15)
Input to Output Disable Delay[14, 15)
25
25
25
25
ns
ns
Pin 14 to Output Enable Delay[14, 15)
20
20
ns
tpxz
Pin 14 to Output Disable Delay[14, 15)
20
20
fMAX3
Maximum Fre~uen9' with Feedback in Output Registered Mode
(1/(tca + ts»[ 6,17)
31.2
27.0
MHz
fMAX4
Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/tca, 1/(tWH + twL), or 1/(ts + tH»[9)
41.6
33.3
MHz
tOH-tIH33X
Output Data Stable from Output Clock Minus In~ut
Register Input Hold Time for 7C330 and 7C332[1 ,18)
0
0
ns
fMAX5
Maximum Frequency Pipelined Modd 1O, 17)
35.0
30.0
MHz
Notes:
7. Refer to Figure 3, configuration 1.
8. Refer to Figure 3, configuration 2.
9. Refer to Figure 3, configuration 3.
10. Refer to Figure 3, configuration 6.
11. Refer to Figure 3, configuration 7.
12. Refer to Figure 3, configuration 9.
13. This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C331. This
specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by samp1i~g of production product.
ns
14. Part (a) of AC Test Loads and Waveforms used for all parameters except tpzxI, tpxzI, tpzx, and tpxz, which use part (b). Part (c) shows
the test waveforms and measurement levels.
15. Refer to Figure 3, configuration 4.
16. Refer to Figure 3, configuration 8.
17. This specification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated
with output register and input register clocks controlled by the same
source. These parameters are tested by periodic sampling of production product.
18. Refer to Figure 3. configuration 10.
4-120
. ·aPRFSS
-=-,
CY7C331
SEMICONDUcrOR
Switching Characteristics Over the Operating Rangel 2] (continued)
Military
-25
Parameter
Description
Min.
-40
-30
Max.
Min.
Max.
Min.
Max.
Unit
tpD
Input to Output Propagation Delay[7]
25
30
40
ns
tICO
Input Register Clock to Output Delay[4, 8]
45
50
65
ns
tIOH
Output Data Stable Time from Input Clock[4, 8]
5
5
5
tIS
Input or Feedback Set-Up Time to Input Register Clock[8]
5
5
5
ns
tIH
Input Register Hold Time from Input Clock[4, 8]
13
15
20
ns
ns
tIAR
Input to Input Register Asynchronous Reset Delay[4, 8]
tIRW
Input Register Reset Width[8]
45
50
65
ns
tIRR
Input Register Reset Recovery Timel8]
45
50
65
ns
45
50
50
Input to Input Register Asynchronous Set Delay[8]
tlSW
Input Register Set Width[8]
45
50
65
ns
tlSR
tWH
Input Register Set Recovery Timel8]
Input and Output Clock Width High[8, 9, 10]
45
50
65
ns
15
20
25
ns
tWL
Input and Output Clock Width Low[8, 9, 10]
15
25
ns
fMAXI
Maximum frequency with Feedback in Input Registered
Mode (1I(tlco + tIS»[l1]
20.0
20
18.1
14.2
MHz
fMAX2
Maximum frequency Data Path in Input Registered Mode
(Lowest of 1ItICO, 1/(tWH + tWL), or 1I(tls + tIH)[8]
22.2
20.0
15.3
MHz
tIOH-tIH33X
Output Data Stable from Input Clock Minus Input Register
Input Hold Time for 7C330 and 7C332[12, 13]
0
0
0
ns
tco
Output Register Clock to Output Delay[9]
tOH
Output Data Stable Time from Output Clock[9]
3
3
3
ns
ts
Output Register Input Set- Up Time to Output Clock[9]
15
15
20
ns
tH
Output Register Input Hold Time from Output Clock[9]
10
10
12
tOAR
tORR
Input to Output Register Asynchronous Reset Delay[9]
Output Register Reset Width[9]
Output Register Reset Recovery Timel9]
tOAS
Input to Output Register Asynchronous Set Delay[9]
tosw
Output Register Set Width[9]
25
30
40
ns
tOSR
tEA
Output Register Set Recovery Timel9]
Input to Output Enable Delay[14, 15]
25
30
40
ns
25
30
40
ns
tER
Input to Output Disable Delay[14, 15]
25
30
40
ns
tpzx
Pin 14 to Output Enable Delay[14, 15]
20
25
35
ns
tpxz
Pin 14 to Output Disable Delay[14, 15]
20
25
35
ns
fMAX3
Maximum FrequenJr with Feedback in Output Registered
Mode )1I(tco + ts)[ 6,17]
25.0
22.2
16.6
MHz
fMAX4
Maximum Frequency Data Path in Output Registered Mode
(Lowest of l/tco, 1/(tWH + tWL), or 1I(ts + tH)[9]
33.3
25.0
20.0
MHz
tOH-tIH33X
Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C330 and 7C332[13, 18]
0
0
0
ns
fMAX5
Maximum Frequency Pipelined ModellO, 17]
28.0
23.5
18.5
MHz
25
4-121
65
ns
tlAS
tORW
45
65
40
30
25
25
30
40
25
30
40
25
ns
ns
ns
40
30
ns
ns
40
30
ns
ns
•
U)
C
..J
D.
.;~
i6 CYPRESS
_ ? SEMICONDUCTOR
CY7C331
Switching Waveforms
INPUT OR
I/O PIN
I/O INPUT
REGISTER
CLOCK[6]
OUTPUT
REGISTER
CLOCK[6]
OUTPUT
SET AND
RESET
INPUTS[6]
I _ - - - . l . - - - tpO[21]
-------.1
C331-17
QEPRODUCT
TERM INPUT[6, 15]
PIN 14 AS m:[24]
OUTPUT
--+--"""""".."
OUTPUT
REGISTER
RESET INPUT[6, 9] _ _ _ _ _ _ _ _ _ _ _ _- '
OUTPUT
REGISTER
CLOCK[6, 9] ------------------r""7:'~i.;:=::;:1_-_:_~
OUTPUT
REGISTER
SET INPUT[6, 9] -------------------4----J
I/O INPUT
REGISTER RESET
INPUT[6,8] _ _ _ _ _ _ _ _.....;_ _ _ __
tOSR
I/O INPUT
REGISTER
CLOCK[6,8] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--11I/O INPUT
REGISTER
SET INPUT[6, 8] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
C331-18
Notes:
19. Output register is set in Transparent mode. Output register set and reset inputs are in a HIGH state.
20. Dedicated input or input register set in Transparent mode. Input register set and reset inputs are in a HIGH state.
21. Combinatorial Mode. Reset and set inputs of the input and output registers should remain in a HIGH state at least until the output responds
at tpD' When returning set and reset inputs to a LOW state, one of
22. When entering the Combinatorial mode, input and output register set
and reset inputs must be stable in a HIGH state a minimum of tISR or
tIRR and tOSR or tORR respectively prior to application of logic input
signals.
23. When returning to the input and/or output Registered mode, register
set and reset inputs must be stable in a LOW state a minimum of tISR
or tIRR and tOSR or tORR respectively prior to the application of the
register clock input.
these signals should go LO\V a il1iniiuUfil of iOSR (s~i inpui) or tORR
(reset input) prior to the other. This guarantees predictable register
states upon exit from Combinatorial mode.
24. Refer to Figure 3, configuration 5.
4-122
~
-
.::~
CY7C331
'jE CYPRESS
~, SEMICONDUcrOR
CONFIGURATION 1
PIN
J----------{~==:::1
INPUT OR I/O PIN
PIN
~
_ _ _~C~LO~C~~~S~/R~_~~==~
INPUT
PRODUCT
TERM
UNREGISTERED
CONFIGURATION 2
INPUT OR I/O PIN
INPUT REGISTER
ARRAY
a
o
Q
..J
a..
OUTPUT REGISTER
PIN
CONFIGURATION 3
PRODUCT
TERM
UNREGISTERED
INPUT OR I/O PIN
PIN
ARRAY
CLOC~S/R
INPUT
UNREGISTERED
INPUT OR I/O PIN
PIN
CONFIGURATION 4
PRODUCT
TERM
INPUT OR I/O PIN
ARRAY
PIN
INPUT OR I/O PIN
I/O PIN
PIN
14
CONFIGURATION 5
INPUT OR I/O PIN
PIN
INPUT OR I/O PIN
INPUT REGISTER
CONFIGURATION 6
UNREGISTERED
INPUT OR I/O PIN
OUTPUT REGISTER
PRODUCT
TERM
CLOCK
ARRAY
PIN
C33H9
CLOCK INPUT
Figure 3. Timing Configurations
4-123
~
CY7C331
.: CYPRESS
. . . SEMICONDUCTOR
DATA INPUT
INPUT REGISTER
CONFIGURATION 7
PIN
l-.2~~~:!:....-t~==~
OUTPUT REGISTER
CONFIGURATION 8
C331-20
CONFIGURATION 9
CONFIGURATION 10
C331-21
CLOCK
Figure 3. Timing Configurations (continued)
4-124
5=
r~CQID!X;la<
CY7C331
CY7C331 Logic Diagram (Upper Half)
o
.c---
•
'6
24
...
32
.. LO
LI t904 (CO •• l)
HE
"
...
L
"ode 34
LI190S (C2)
~(CO•• ,)
en
C
Irt:: ......
..J
[1l~1
...,
D.
L2852
U968I1_or-L..
~(CO •• ,).
s-o-fFrL... .
node 32
..
""
L49fSO
III ttl (C2)
~(CO•• ,)
TO LOWER SECTION
4-125
a
CY7C331
CY7C331 Logic Diagram (Lower Half)
TO UPPER SECTION
I
1.5152
...
LSloU
a.rJr=
-...
U052
_-,I-I-
node 2t
L11t31 (C2)
....
t11eo
~
~.
~
-...
L.
4-o-ff:::
....
[
~--------------------------------------------~
4-126
~(CO_1)
.
:~PRESS
-====:::t'.'
CY7C331
SEMICONDUCTOR
Ordering Information
(rnA)
IcC!
tpD
(ns)
ts
(ns)
tco
(ns)
130
20
12
20
160
120
150
150
25
25
30
40
15
12
15
20
25
25
30
40
Ordering Code
Package
Name
Package 1Ype
CY7C331-20HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C331-2OJC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C331- 20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C331-20WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C331-25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C331-25HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C331- 25LMB
L64
28-Square Leadless Chip Carrier
CY7C331-250MB
064
28-Pin Windowed Leadless Chip Carrier
CY7C331-25TMB
T74
28-Lead Windowed Cerpack
CY7C331-25WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C331-25HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C331-25JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C331-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C331-25WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C331-30DMB
D22
28-Lead (300-Mil) CerDIP
CY7C331-30HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C331-30LMB
L64
28-Square Leadless Chip Carrier
CY7C331-300MB
064
28-Pin Windowed Leadless Chip Carrier
CY7C331-30TMB
T74
28-Lead Windowed Cerpack
CY7C331-30WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C331-40DMB
D22
28-Lead (300-Mil) CerDIP
CY7C331-40HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C331-40LMB
L64
28-Square Leadless Chip Carrier
CY7C331-400MB
28-Pin Windowed Leadless Chip Carrier
CY7C331-40TMB
064
T74
CY7C331-40WMB
W22
28-Lead (300-Mil) Windowed CerDIP
28-Lead Windowed Cerpack
4-127
Operating
Range
Commercial
Military
•
In
C
..J
Q.
Commercial
Military
Military
- ~
-~=
= 0'
..
CY7C331
CYPRESS
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VIL
1,2,3
Ilx
1,2,3
Ioz
1,2,3
ICCl
1,2,3
Switching Characteristics
Parameter
Subgroups
tIS
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tlH
tWH
tWL
tco
tpD
tlAR
tlAS
tpxz
tpzx
tER
tEA
ts
tH
Document #: 38-00066-C
4-128
This is an abbreviated data sheet. Contact a
Cypress representative for complete specifications.
For new designs, please refer to the CY7C335.
CY7C332
Registered Combinatorial
EPLD
Features
• 12 I/O macrocells each having:
- Registered, latched, or transparent
array inpnt
- A choice of two clock sources
- Global or local output enable (OE)
- Up to 19 product terms (PTs) per
output
- Product term (PT) output polarity
control
• 192 product terms with variable
distribution to macrocells
- An average of 14 PTs per macrocell
sum node
• 1\vo clock inputs with contigurable
polarity control
• 13 input macrocells, each having:
- Complementary input
- Register, latch, or transparent
access
-1\vo clock sources
• 15 ns tPD max.
• Lowpower
-120 rnA typical Icc quiescent
-180 rnA max.
- Power-saving "Miser Bit" feature
• Security fuse
• 28-pin slim-line package; also available in 28-pin PLCC
• UV-erasable and reprogrammable
• Programming and operation 100%
testable
Functional Description
The CY7C332 is a versatile combinatorial
PLD with I/O registers on-board. There
are 25 array inputs; each has a macrocell
that may be configured as a register, latch,
or simple buffer. Outputs have polarity and
three-state control product terms. The allocation of product terms to I/O macrocells
is varied so that functions of up to 19 product terms can be accommodated.
I/O Resources
Logic Block Diagram
Selection Guide
Generic Part Number
ICCl (rnA)
Commercial
Military
tICO/tpD (ns)
Commercial
Military
tIS (ns)
Commercial
Military
7C332-15
130
7C332-20
120
160
20
23/20
3
4
7C332-25
120
150
25
25
3
4
7C332-30
18/15
150
3
30
Document #: 38-00067-E
4-129
•
U)
Pins 1 through 7 and 9 through 14 function
as dedicated array inputs. Pins 1 and 2
function as input clocks as well as normal
inputs. Pin 14 functions as a global output
enable as well as a normal input.
4
C
....I
Q.
CY7C335
CYPRESS
SEMICONDUCTOR
Features
• lOO-MHz output registered
operation
• 1\velve I/O macrocells, each having:
- Registered, three-state I/O pins
- Input and output register clock select multiplexer
- Feed back multiplexer
- Output enable (OE) multiplexer
• Bypass on input and output registers
• All twelve macrocell state registers
can be hidden
• User configurable I/O macrocells to
implement JK or RS flip-flops and T
or D registers
• Input multiplexer per pair of I/O macrocells allows I/O pin associated with
a hidden macrocell state register to be
saved for use as an input
• Four dedicated hidden registers
• 1Welve dedicated registered inputs
with individually programmable bypass option
Universal Synchronous EPLD
• Three separate clocks-two input
clocks, two output clocks
• Common (pin 14-controlled) or
product term-controlled output enable for eacti I/O pin
• 256 product terms-32 per pair of
macrocells, variable distribution
• Global, synchronous, product termcontrolled, state register set and reset-inputs to product term are
clocked by input clock
- 2-ns input set-up and 9-ns output
register clock to output
-lOons input register clock to state
register clock
• 28-pin, 300-mil DIP, LCC, PLCC
• Erasable and reprogrammable
• Programmable security bit
Functional Description
The CY7C335 is a high-performance, erasable, programmable logic device (EPLD)
whose architecture has been optimized to
enable the user to easily and efficiently
construct very high performance state machines.
The architecture ofthe CY7C335, consisting ofthe user-configurable output macrocell, bidirectional I/O capability, input registers, and three separate clocks, enables
the user to design high-performance state
machines that can communicate either
with each other or with microprocessors
over bidirectional parallel buses of userdefinable widths.
The four clocks permit independent, synchronous state machines to be synchronized to each other.
The user-configurable macroceIIs enable
the designer to designate JK-, RS-, T-, or
D-type devices so that the number of product terms required to implement the logic
is minimized.
The CY7C335 is available in a wide variety
of packages including 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and LCCs.
Logic Block Diagram
Ig
Is
16
Vss
15
IIOg
I/Os
1/06
Vss
Vee
4-130
11/CLK3
1/0 5
1/0 3
loICLK2
CLK1
1/0 0
C335-1
.~PR£§
,
CY7C335
SEMICONDUCTOR
Pin Configurations
LCC
PLCC
Top View
Top View
~~
c3d~
C\l
~~:9dg'gg
13
14
15
Vss
16
17
18
7
8
9
10
11
II
C335-2
en
C
..J
Q.
Selection Guide
Maximum Operating
Frequency (MHz)
leCl (rnA)
CY7C33S-100
CY7C33S-83
CY7C33S-66
Commercial
100
83.3
66.6
Military
Commercial
83.3
140
66.6
140
Military
140
160
160
CY7C33S-S0
50
CY7C33S-40
50
140
40.0
160
160
Architecture Configuration Bits
The architecture configuration bits are used to program the multiplexers. The function of the architecture bits is outlined in Table 1.
Table 1. Architecture Configuration Bits
Architecture
Configuration Bit
Number of Bits
Value
Function
CO
Output Enable
SelectMUX
12 Bits, 1 Per
I/O Macrocell
0-Virgin State
I-Programmed
Output Enable Controlled by Pin 14
Cl
State Register
Feed Back MUX
12 Bits, 1 Per
I/O Macrocell
0-Virgin State
State Register Output is Fed Back to Input Array
I-Programmed
I/O Macrocell is Configured as an Input and
Output of Input Path is Fed to Array
I/O Macrocell
Input Register
Clock Select
MUX
12 Bits, 1 Per
I/O Macrocell
0-Virgin State
ICLKI Controls the Input Register I/O Macrocell
Input Register Clock Input
I-Programmed
ICLK2 Controls the Input Register I/O Macrocell
Input Register Clock Input
C3
Input Register
Bypass MUXI/O Macrocell
12 Bits, 1 Per
I/O Macrocell
0-Virgin State
Selects Input to Feedback MUX from Input
Register
I-Programmed
Selects Input to Feedback MUX from I/O pin
C4
Output Register
Bypass MUX
12 Bits, 1 Per
I/O Macrocell
O-Virgin State
Selects Output from the State Register
I-Programmed
Selects Output from the Array, Bypassing the State
Register
State Clock MUX
16 Bits, 1 Per I/O
Macrocell and 1 Per
Hidden Macrocell
0-Virgin State
State Clock 1 Controls the State Register
I-Programmed
State Clock 2 Controls the State Register
12 Bits, 1 Per
Dedicated Input
Cell
0-Virgin State
ICLKI Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
I-Programmed
ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
C2
C5
C6
Dedicated Input
Register Clock
SelectMUX
4-131
Output Enable Controlled by Product Term
•
42.:~
7.
CY7C335
CYPRESS
SEMICONDUCTOR
Table 1. Architecture Configuration Bits (continued)
Architecture
Configuration Bit
Number of Bits
Value
Function
C7
Input Register
Bypass MUXInput Cell
12 Bits, 1 Per
Dedicated Input
Cell
0-Virgin State
Selects Input to Array from Input Register
I-Programmed
Selects Input to Array from Input Pin
C8
ICLK2 Select
MUX
1 Bit
0-Virgin State
Input Clock 2 Controlled by Pin 2
I-Programmed
Input Clock 2 Controlled by Pin 3
C9
ICLKI Select
MUX
1 Bit
0-Virgin State
Input Clock 1 Controlled by Pin 2
ClO
SCLK2 Select
MUX
CX
(11-16)
I/O Macrocell
Pair Input
Select MUX
I-Programmed
Input Clock 1 Controlled by Pin 1
1 Bit
0-Virgin State
State Clock 2 Grounded
I-Programmed
State Clock 2 Controlled by Pin 3
6 Bits, 1 Per
I/O Macrocell
Pair
0-Virgin State
Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair
I-Programmed
Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair
1
-
INPUT REGISTER
INPUT
PIN
ICLK1
ICLK2
D
Or-INPUT
CLOCK
1 MUX
Q
0
INPUT
REG
BYPASS
MUX
r-
TOARRAY
::?
d7
-
>
C6
C335-4
Figure 1. CY7C335 Input Macrocell
4-132
CY7C335
co
OUTPUT REG
BYPASS MUX
OUTPUT
ENABLE I----+__.
~O_U_T_P_UT
__
EN_A_B_L_E_P_R_O_D_U_CT
__
TE_R_M____________~O MUX
PIN 14: OE
•
SET PRODUCT TERM
U)
C
..J
Q.
i
SCLK1
SCLK2
RESET PRODUCT TERM
TO ARRAY
o
FEED
BACK
MUX
C1
ICLK1
INPUT REGISTER
C2
o
D
o
ICLK2
C335-5
TO ARRAY
CX(11 -16)
FROM ADJACENT MACROCELL
Figure 2. CY7C335 Input/Output Macrocell
4-133
~PRESS
CY7C335
wnlCONDUcrOR
SET PRODUCT TERM
S
.
D
Q
:
SCLK1
SCLK2
RESET PRODUCT TERM
C335-6
Figure 3. CY7C335 Hidden Macrocell
SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS
PIN 1
ICLK1
ICLK2
SCLK1 TO OUTPUT MACROCELLS AND HIDDEN
MACROCELLS
PIN 2
C8
PIN3
C335-7
Figure 4. CY7C335 Input Clocking Scheme
4-134
· .-;::z
CYPRESS
CY7C335
'j;
~, SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65 ° C to + 150 ° C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(Pm 22 to Pins 8 and 21) ................ - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Output Current into Outputs (Low) ............... 12 mA
Electrical Characteristics Over the Operating Rangd2]
Parameter
Description
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 mA
DC Programming Voltage ......................... 13.0V
Operating Range
Ambient
Temperature
Range
Commercial
Industrial
Military[l]
O°C to +75°C
Vee
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
en
Test Conditions
VOR
Output HIGH Voltage
Vee = Min.,
VIN = VIR or VIL
VOL
Output LOW Voltage
Vee = Min.,
VIN = VIR or VIL
Min.
= - 3.2mA
lOR = - 2mA
IOL = 12mA
IOL = 8mA
lOR
Com'l
V
Com'l
0.5
V
0.8
V
~
Mil/lnd
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs[3]
V
2.2
Vss~ VIN ~ Vee,
-10
10
-40
40
~
Output Short Circuit Current
Vee
Vee
- 30
- 90
mA
Standby Power
Supply Current
Com'l
140
mA
Outputs Open
Mil/lnd
160
mA
Com'l
180
mA
Mil/lnd
200
mA
IIX
Input Leakage Current
Output Leakage Current
Ise
leCl
Iee2
Unit
Mil/lnd
VIL
Vee = Max.
= Max., Vss~ VOUT~ Vee
= Max., VOUT = 0.5V[4,S]
Vee = Max., VIN = GND
Max.
2.4
VIR
loz
Power Supply Current
at Frequency[S]
Vee = Max.,
Outputs Disabled (in High Z State),
Device Operating at fMAX External (fMAXS)
Capacitance[S]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
a
Test Conditions
Min.
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
Notes:
1. tA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
4.
5.
4-135
Max.
10
10
Unit
pF
pF
Not more than one output should be tested at a time. Duration ofthe
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by ground degradation.
Tested initially and after any design or process changes that may affect
these parameters.
C
..J
~
·
.~
CY7C335
":~ CYPRESS
~JF SEMICONDUCTOR
AC Test Loads and Waveforms (Commercial)
R1313Q
(470 Q Mil/lnd)
OUTP:~:F1
INCLUDING
JIG AND
SCOPE
I-=
50 pF
ALL INPUT PULSES
3.0V---90%
R2208Q
(319Q Mil/lnd)
GND
-=
C335-8
(a)
R = 125Q (190Q Mil)
T
__ _1-
OV
I
J...
OV
OUTPUTO
VTH = 2.00V
(2.02V Mil)
C = 5pF
tpxz (-)
tpxz( +)
VOH
O.SV
Vx
tCER(-)
l.SV
tCER(+)
2.6V
tCEA(+)
Vth
tCEA(-)
Vx
VOH
O.5V
~
~
O.SV
O.5V
Vx
Vx
~
~
O.5V
VOL
Vth
~
~
O.5V
Vth
Vth
~
O.5V
2.6V
tpzx (-)
C335-10
(d) Three-state Delay Load (Load 2)
VOL
tpzx (+)
OV
Output Waveform-Measurement Level
Vx
l.5V
T
OV
C335-9
(c) Thevenin Equivalent (Load 1)
Parameter
I
R = 125Q (190Q Mil)
OUTPUT~
C = 50 pF
C335-11
(b)
O.5V
~
Figure 5. Test Waveforms
4-136
~
~
~
~
~
~
~
~
Vx
C335-12
Vx
C335-13
VOH
C335-14
VOL
C335-15
Vx
C335-16
Vx
C335-17
VOH
C335-18
VOL
C335-19
'~PRESS
CY7C335
.
- , SEMICONDUCIOR
Commercial AC Characteristics
7C335·100
Min. Max.
Parameter
Description
Combinatorial Mode Parameters
15
Input to Output Propagation Delay
tpD
15
Input to Output Enable
tEA
Input to Output Disable
15
tER
Input Registered Mode Parameters
Input and Output Clock Width HIGHL:JJ
4
tWH
Input and Output Clock Width LOWL:JJ
4
tWL
Input or Feedback Set·Up Time to Input Clock
2
tIS
2
Input Register Hold Time from Input Oock
tIH
18
Input Register Oock to Output Delay
tlCO
Output Data Stable Time from Input Oock
3
tIOH
0
tIOH - tIH Output Data Stable from Input Oock Minus Influt Register Hold Time for 7C330, 7C332, and 7C335 [ ]
33x
12
Pin 14 Enable to Output Enabled
tpzx
12
Pin 14 Disable to Output Disabled
tpxz
Maximum Frequency of (2) CY7C335s in Input Registered 50
fMAXI
Mode (Lowest of lJ(tlCO+tIS) & l/(tWL +tWH))[5]
Maximum Frequency Data Path in Input Registered Mode 55.5
fMAX2
(Lowest of (lJ(tlCO), lJ(tWH+tWL), 1J(tIS+tIH»)[5]
17
Input Oock to Output Enabled
tlCEA
Input Oock to Output Disabled
15
tlCER
Output Registered Mode Parameters
Output Clock to Output EnabledL5J
17
tCEA
15
Output Oock to Output DisabledP J
tCER
Output Register Input Set-Up Time from Output Clock
8
ts
Output Register Input Hold Time from Output Oock
0
tH
9
Output Register Clock to Output Delay
tco
17
Input Output Register Clock or Latcha Enable to
tC02
Combinatorial Output Delay (Through Logic Array)[5]
Output Data Stable Time from Output Clock
2
tOH
Output Data Stable Time From Output Clock (Through
3
tOH2
Memory Array) [5]
tOH2- t IH
fMAX3
fMAX4
fMAX5
tOH - tIH
33x
Output Data Clock Stable Time From Output Clock Minus Input Register Hold Time [5]
Maximum Frequency with Internal Feedback in Output
Registered ModelS]
Maximum Frequency of (2) CY7C335s in Output Refstered
Mode (Lowest of l/(tco + ts) & lJ(tWL + tWH))[5
Maximum Frequency Data Path in Output Registered
Mode (Lowest of 1I(tco), lJ(tWL + tWH), l/(ts + tH))[5]
Output Data Stable from Output Clock Minus Infut Register Hold Time for 7C330, 7C332, and 7C335[6
4-137
7C335·83
Min. Max.
7C335·66
Min. Max.
20
20
20
15
15
15
6
6
5
5
2
2
25
25
25
8
8
3
3
2
2
25
20
18
3
0
3
0
7C335·50
Min. Max.
3
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
45.4
35.7
ns
ns
MHz
55.5
50
40
MHz
12
15
15
12
20
20
17
15
20
20
25
25
ns
ns
17
15
20
20
25
25
ns
ns
ns
ns
ns
ns
9
0
15
0
12
0
12
23
10
18
15
30
2
3
2
3
2
3
ns
ns
0
0
0
0
ns
100
83.3
66.6
50
MHz
58.8
50
41.6
33.3
MHz
111
100
83.3
62.5
MHz
0
0
0
0
ns
•
U)
Q
...I
a..
.~PRESS
s;:
,
CY7C335
SEMICONDUCTOR
Commercial AC Characteristics (continued)
7C33S-100
Description
Min. Max.
Parameter
Pipelined Mode Parameters
Input Clock to Output Clock
10
tcos
Maximum Frequency Pipelined Mode (Lowest of 100
fMAX6
l/(tcos), l/(tco), 1/(tWL + tWH», 1/(tIS + tlH)[5]
Maximum Frequency of (2) CY7C335s in Pipelined Mode 90.9
fMAX7
(Lowest of 1/(tco + tIS) or 1/tcOS)
Power-Up Reset Parameters
Power-Up Reset TimeF', IJ
1
tpOR .
7C33S-83
Min. Max.
7C33S-66
Min. Max.
12
83.3
15
66.6
20
50
ns
MHz
83.3
66.6
50
MHz
1
7C33S-S0
Min. Max.
Unit
1
1
itS
Military/Industrial AC Characteristics
7C33S-83
7C33S-66
7C33S-S0
7C33S-40
Min. Max. Min. Max. Min. Max. Min. Max.
Parameter
Description
Combinatorial Mode Parameters
tpD
tEA
Input to Output Propagation Delay
Input to Output Enable
Input to Output Disable
tER
Input Registered Mode Parameters
Input and Output Clock Width HIGH[5]
tWH
20
20
20
20
25
25
30
30
ns
ns
20
20
25
30
ns
5
6
8
tWL
Input and Output Clock Width LOW[5]
5
6
tIS
tlH
Input or Feedback Set-Up Time to Input Oock
3
3
3
3
8
3
3
Input Register Hold Time from Input Oock
Input Register Clock to Output Delay
tlCO
Output Data Stable Time from Input Oock
tIOH
tIOH - tlH Output Data Stable from Input Clock Minus Inp.ut
Register Hold Time for 7C330, 7C332, and 7C335[6]
33x
tpzx
tpxz
23
23
30
ns
3
ns
0
0
0
0
ns
15
15
15
20
30
30
38.4
38.4
35.7
29.4
43.4
43.4
40
33.3
MHz
20
20
20
20
ns
ns
MHz
20
20
20
25
30
ns
25
30
ns
20
25
25
30
30
ns
ns
ns
20
Output Register Input Set-Up Time to Output Clock
10
12
15
Output Register Input Hold Time from Output Clock
Output Register Clock to Output Delay
0
0
0
11
22
Output Register Oockor Latch Enable to Combinatorial
Output Delay (Through Logic Array)[5]
ns
ns
ns
4
25
tH
tC02
4
3
ts
tco
ns
3
15
Maximum Frequency of (2) CY7C335s in Input
Registered Mode (Lowest of 1/(tICO + tIS) &
1/(tWL + tWH»[5]
Maximum Frequency Data Path in Input Registered
fMAX2
Mode (Lowest of (l/(tICO)' 1/(tWH + twL),
1/(tIS + tlH»[5]
Input Clock to Output Enabled
tlCEA
Input Clock to Output Disabled
tlCER
Output Registered Mode Parameters
Output Clock to Output Enabled [5]
tCEA
Output Clock to Output Disabled [5]
tCER
10
10
3
Pin 14 Enable to Output Enabled
Pin 14 Disable to Output Disabled
fMAXI
Unit
12
23
20
15
0
20
ns
ns
30
35
ns
Notes:
6.
This specification is intended to guarantee interface compatibility of
the other members of the CY7C330 family with the CY7C335. This
specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
'7
4-138
This part has been designed with the capability to reset during syslt:m
power-up. Following power-up, the input and output registers will be
reset to a logic LOW state. The output state will depend on how the
array is programmed.
·
::~
CY7C335
~=CYPRESS
~_., SEMICONDUCTOR
Military/Industrial AC Characteristics (continued)
Parameter
7C335-83
Min. Max.
Description
7C335-66
Min. Max.
7C335-50
7C335-40
Min. Max. Min. Max.
Unit
tOR
Output Data Stable Time from Output Clock
2
2
2
2
ns
tOH2
Output Data Stable Time From Output Clock
(Through Memory Array) [S]
3
3
3
3
ns
tOH2- t lH
Output Data Clock Stable Time From Output Clock
Minus Input Register Hold Time [S]
0
0
0
0
ns
fMAX3
Maximum Frequency with Internal Feedback in Output Registered ModelS]
83.3
66.6
50
40
MHz
fMAX4
Maximum Frequency of (2) CY7C335s in Output RegtsteredMode (Lower of 1/(teo + ts) & 1/(tWL + tWH))[S]
47.6
41.6
33.3
25
MHz
fMAXS
Maximum Frequency Data Path in Output Registered
Mode (Lowest of 1/(teo), 1/(tWL + tWH), 1/(ts + tR))[S]
90.9
83.3
62.5
50
MHz
tOR - tlH Output Data Stable from Output Clock Minus InRut
Register Hold Time for 7C330, 7C332, and 7C335[6]
33x
Pipelined Mode Parameters
Input Clock to Output Clock
Maximum Frequency Pipelined Mode
(Lowest of 1/(teos), 1/(tIS), or 1/(teo)), 1/(tIS + tlH)[S]
Maximum Frequency of (2) CY7C335s in Pipelined
fMAX7
Mode (Lowest of 1/(teo + tiS) or 1/teos)
Power-Up Reset Parameters
Power-Up Reset TimelS, 7]
tpOR
teas
fMAX6
4-139
0
0
0
ns
0
12
15
20
25
ns
83.3
66.6
50
40
MHz
71.4
66.6
50
40
MHz
1
1
1
1
!1s
II
tn
C
..I
D.
~PR£SS
_Ts~CONDUcrOR
CY7C335
Switching Waveform
INPUT OR
I/O PIN
INPUT REG.
CLOCK
OUTPUT
REG. CLOCK
OUTPUT
1 4 - - - - tpD - - - . . - I
I.
14------PIN 14
ASOE
tlCER - - - -..
tER
------.t
C
_ _J-----..tpxz
Ip"
C335-20
Power-Up Reset Waveform[7]
VCC
OUTPUT
CLOCK
C335-21
4-140
CY7C335
Block Diagram (Page 1 of 2)
II
en
Q
..I
a.
TO LOWER SECTION
C335-22
4-141
LJ¢
•
J.-4
,
CY7C335
CYPRESS
SEMICONDUCTOR
Block Diagram (Page 2 of 2)
TO UPPER SECTION
C335-23
4-142
:~PRESS
.
JF
CY7C335
SEMICONDUCTOR
Ordering Information
fMAX
(MHz)
(rnA)
100
140
83.3
83.3
66.6
66.6
SO
leCl
160
140
160
140
140
Ordering Code
Package
Name
Package 'JYpe
CY7C33S -'-100HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-lOOJC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C33S -100PC
P21
28-Lead (300-Mil) Molded DIP
CY7C33S-100WC
W22
28-Lead (300-Mil) Wmdowed CerDIP
CY7C335-83DI
D22
28-Lead (300-Mil) CerDIP
CY7C335-83HI
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-83PI
P21
28-Lead (300-Mil) Molded DIP
CY7C33S-83WI
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C335 -83DMB
D22
28-Lead (300-Mil) CerDIP
CY7C335-83HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-83LMB
L64
28-Square Leadless Chip Carrier
CY7C33S -830MB
064
28-Pin Windowed Leadless Chip Carrier
CY7C33S -83WMB
W22
28-Lead (300-Mil) Wmdowed CerDIP
CY7C33S-83HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-83JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C33S-83PC
P21
28-Lead (300-Mil) Molded DIP
CY7C33S -83WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C33S-66DI
D22
28-Lead (300-Mil) CerDIP
CY7C33S-66HI
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S - 66PI
P21
28-Lead (300-Mil) Molded DIP
CY7C33S-66WI
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C33S-66DMB
D22
28-Lead (300-Mil) CerDIP
CY7C33S -66HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-66LMB
L64
28-Square Leadless Chip Carrier
CY7C33S -660MB
064
28-Pin Windowed Leadless Chip Carrier
CY7C33S -66WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C33S-66HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-66JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C33S-66PC
P21
28-Lead (300-Mil) Molded DIP
CY7C33S-66WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C33S-S0HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C33S-S0JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C33S - SOPC
P21
28-Lead (300-Mil) Molded DIP
CY7C33S-S0WC
W22
28-Lead (300-Mil) Windowed CerDIP
4-143
Operating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Commercial
•
U)
....0..Q
~
.
:~pRF.SS
,
CY7C335
SEMICONDUCTOR
Ordering Information (continued)
fMAX
(MHz)
(rnA)
50
160
40
leCl
Ordering Code
160
Package
Name
CY7C335 - 50DI
D22
28-Lead (300-Mil) CerDIP
CY7C335-50HI
H64
28-Pin Windowed Leaded Chip Carrier
CY7C335 - 50PI
P21
28-Lead (300-Mil) Molded DIP
CY7C335 - 50WI
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C335-50DMB
D22
28-Lead (300-Mil) CerDIP
CY7C335 - 50HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C335 - 50LMB
L64
28-Square Leadless Chip Carrier
CY7C335 - 500MB
064
28-Pin Windowed Leadless Chip Carrier
CY7C335-50WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C335-40DI
D22
28-Lead (300-Mil) CerDIP
CY7C335-40Hl
H64
28-Pin Windowed Leaded Chip Carrier
CY7C335-40PI
P21
28-Lead (300-Mil) Molded DIP
CY7C335-40WI
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C335 -40DMB
D22
28-Lead (300-Mil) CerDIP
CY7C335 -40HMB
H64
28-Pin Windowed Leaded Chip Carrier
CY7C335-40LMB
L64
28-Square Leadless Chip Carrier
CY7C335 -400MB
Q64
28-Pin Windowed Leadless Chip Carrier
CY7C335 -40WMB
W22
28-Lead (300-Mil) Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
VOL
VIH
1,2,3
1,2,3
VIL
IIx
1,2,3
1,2,3
Iaz
lee
1,2,3
1,2,3
1,2,3
Switching Characteristics
Parameter
Package 'tYPe
Subgroups
tpD
9,10,11
tIea
tIS
9,10,11
teo
9,10,11
ts
9,10,11
tH
9,10,11
teas
9,10,11
9,10,11
Document #: 38-00186-C
4-144
Operating
Range
Industrial
Military
Industrial
Military
CY7C340 EPLD Family
CYPRESS
SEMICONDUCTOR
- VHDL simulation (ViewSim)
- Available on PC and Sun platforms
Features
• Erasable, user-configurable CMOS
EPLDs capable of implementing highdensity custom logic functions
• O.S-micron double-metal CMOS
EPROM technology (CY7C34X)
• Advanced O.65-micron CMOS
technology to increase performance
(CY7C34XB)
• Multiple Array Matrix architecture
optimized for speed, density, and
straightfonvard design implementation
- Programmable Interconnect Array
(PIA) simplifies routing
- Flexible macrocells increase utilization
- Programmable clock control
- Expander product terms implement complex logic functions
• Wa1p2
- Low-cost VHDL compiler for PLDs
- IEEE l076-compliant VHDL
- Available on PC and Sun platforms
• Wa1p3
- VHDL synthesis
- ViewLogic graphical user interface
- Schematic capture (ViewDraw)
Multiple Array Matrix
High-Density EPLDs
LAB is a group of additional product terms
called expander product terms. These expanders are used and shared by the macrocells, allowing complex functions of up to
35 product terms to be easily implemented
in a single macrocell. A Programmable Interconnect Array (PIA) globally routes all
signals within devices containing more
than one LAB. This architecture is fabricated on the Cypress O.8-micron, doublelayer-metal CMOS EPROM process,
yielding devices with significantly higher
integration, density and system clock speed
than the largest of previous generation
EPLDs. The CY7C34XB devices are
0.65-micron shrinks ofthe original 0.8-micron family. The CY7C34XBs offer faster
speed bins for each device in the Cypress
MAX family.
The density and performance of the
CY7C340 family is accessed using Cypress's Warp2 and Warp3 design software. Warp2 provides state-of-the-art
VHDL synthesis for MAX at a very low
cost. Warp3 is a sophisticated CAE tool
that includes schematic capture (ViewDraw) and timing simulation (ViewSim)
in addition to VHDLsynthesis. Consult
the Warp2 and Warp3 datasheets for
more information about the development tools.
General Description
The Cypress Multiple Array Matrix
(MAX®) family of EPLDs provides a
user-configurable, high-density solution
to general-purpose logic integration requirements. With the combination of innovative architecture and state-of-theart process, the MAX EPLDs offer LSI
density without sacrificing speed.
The MAX architecture makes it ideal for
replacing large amounts of TTL SSI and
MSI logic. For example, a 74161 counter
utilizes only 3% of the 128 macrocells
available in the CY7C342. Similarly, a
74151 8-to-1 multiplexer consumes less
than 1% of the over 1,000 product terms in
the CY7C342. This allows the designer to
replace 50 or more TTL packages with just
one MAX EPLD. The family comes in a
range of densities, shown below. By standardizing on a few MAX building blocks,
the designer can replace hundreds of different 7400 series part numbers currently
used in most digital systems.
The family is based on an architecture of
flexible macrocells grouped together into
Logic Array Blocks (LABs). Within the
Max Family Members
CY7C344 (B)
CY7C343 (B)
CY7C342 (B)
CY7C341(B)
Macrocells
32
64
128
192
MAX Flip-Flops
32
64
128
192
MAX Latches[l]
64
128
256
384
MAX Inputs[2]
23
35
59
71
MAX Outputs
16
28
52
64
28H,J,W,D
44H,J
68H,J,R,G
84H,J,R,G
Feature
Packages
Key: D-DIP; G-Pin Grid Array; H-Windowed Ceramic Leaded Chip Carrier; J-J-Lead Chip Carrier; R-Windowed Pin Grid Array;
W-Windowed Ceramic DIP
Notes:
1. When all expander product terms are used to implement latches.
2. With one output.
PAL is a registered trademark of Monolithic Memories Inc.
MAX is a registered trademark of Ahera Corporation.
IBM and IBM PC/AT are registered trademarks of International Business Machines Corporation.
Wa1p2 and Wa1p3 are trademarks of Cypress Semiconductor Corporation.
ViewDraw and ViewSim are registered trademarks of ViewLogic Corporation.
4-145
•
en
C
...I
Q.
.-:r=:
~
CY7C340 EPLD Family
_ ' j ; ; CYPRESS
- , SEMICONDUCIOR
DEDICATED INPUTS
/\
~%
V~~V
t-
-
t-
-
V
tr>-O,
'~
t>
LOGIC
BLOCK -I'--.
ARRAY
(LAB)
r-- r-.
MULTIPLE
ARRAYS
(LABS)
H>
-
-
-
- DUAL
I/O
FEEDBACK
V
EXPANDE RV
PRODUCTTERMS
t-
,
-
I
t- \
~
~
MACROCELLS
~
PROGRAMMABLE
INTERCONNECT
ARRAY (PIA)
Figure 1. Key MAX Feaiures
4-146
~
V
C340-1
aT
-~
CY7C340 EPLD Family
~=CYPRESS
~, SEMICONDUCTOR
Functional Description
The Logic Array Block
The logic array block, shown in Figure 2, is the heart of the MAX
architecture. It consists of a macrocell array, expander product
term array, and an I/O block. The number of macrocells, expanders, and I/O vary, depending upon the device used. Global feedback of all signals is provided within a LAB, giving each functional
block complete access to the LAB resources. The LAB itself is fed
by the programmable interconnect array and dedicated input bus.
The feedbacks of the macrocells and I/O pins feed the PIA, providing access to them through other LABs in the device. The members
of the CY7C340 family of EPLDs that have a single LAB use a
global bus, so a PIA is not needed (see Figure 3).
The MAX Macrocell
Traditionally, PLDs have been divided into either PLA (programmableAND, programmable OR), or PAL® (programmable AND,
fixed OR) architectures. PLDs of the latter type provide faster input-to-output delays, but can be inefficient due to fixed allocation
of product terms. Statistical analysis of PLD logic designs has
shown that 70% of alllogicfunctions (per macrocell) require three
product terms or less.
The macrocell structure of MAX has been optimized to handle
variable product term requirements. As shown in Figure 4, each
macrocellconsists of a product term array and a configurable register. In the macrocell, combinatorial logic is implemented with
three product terms ORed together, which then feeds an XOR
gate. The second input to the XOR gate is also controlled by a
product term, providing the ability to control active HIGH or active LOW logic and to implement T- and JK-type flip-flops.
If more product terms are required to implement a given function,
they may be added to the macrocell from the expander product
term array. These additional product terms may be added to any
macrocell, allowing the designer to build gate-intensive logic, such
as address decoders, adders, comparators, and complex state machines, without using extra macrocells.
The register within the macrocell may be programmed for either
D, T, JK, or RS operation. It may alternately be configured as a
flow-through latch for minimum input-to-output delays, or bypassed entirely for purely combinatorial logic. In addition, e~ch
register supports both asynchronous pr~set a~d clear, allowll~g
asynchronous loading of counters of shift registers, as found III
many standard TTL functions. These registers may be clocked with
a synchronous system clock, or clocked independently from the
logic array.
I/O Block
Separate from the macrocell array is the I/O control block of the
LAB. Figure 6 shows the I/O block diagram. The three-state buffer
is controlled by a macrocell product term and the drives the I/O
pad. The input of this buffer comes from a macrocell within the
r----------------,
r----------------,
I
I/O I
PINS I
I
N
P
U
T
S
II
Expander Product Terms
The expander product terms, as shown in Figure 5, are fed by the
dedicated input bus, the programmable interconnect array, the In
macrocell feedback, the expanders themselves, and the I/O pin Q
feedbacks. The outputs of the expanders then go to each and every ..J
product term in the macrocell array. This allows expanders to be D.
"shared" by the product terms in the logic array block. One expander may feed all macrocells in the LAB, or even multiple product
terms in the same macrocell. Since these expanders feed the secondary product terms (preset, clear, clock, and output enable ~ of
each macrocell, complexlogicfunctions maybe implemented Without utilizing another macrocell. Likewise, expanders may feed and
be shared by other expanders, to implement complex multilevel
logic and input latches.
MACROCELL
ARRAY
I/O
PINS
I
N
P
P
I
A
U
T
S
I
I
I
I
I
IL
________________ J
PROGRAMMABLE
INTERCONNECT
_______________ _
C340-3
C340-2
ARRAY
Figure 2. 1YPical LAB Block Diagram
Figure 3. 7C344 LAB Block Diagram
4-147
I
I
~CYPRESS
~itliI
~ iT SEMICONDUCTOR
16
MACROCELL
FEEDBACKS
(32 FOR 7C344)
PROGRAMMABLE
INTERCONNECT
SIGNALS
I
II
II
I
II
II
I
II
I
~
I
I
CY7C340 EPLD Family
JI'
1/0 OUTPUT
ENABLE
"-
PRESET
I
PROGRAMMABLE FLIP-FLOP
(0, T, JK, SR)
•
•
REGISTERED OR FLOWTHROUGH-LATCH OPERATION
PROGRAMMABLE CLOCK
•
7
I
•
ASYNC CLEAR AND PRESET
I
I
I
I
I
I
I
I
I
I
....
I
Q
~
I
I
I
~
ARRAY
CLOCK
I
I
I
I
TO
;---
-
I
I
P
~I -
I
-
I/OCONTROL
-
.
f.-.-
C
I
I
I
I
I
II
I
II
CLEAR
I
I
II
I
II
I
II
I
II
I
II
I
II
I
II
I
II
II
I
II
II
8
DEDICATED
INPUTS
MACROCELL
~
<
1 FEEDBACK
TO
,
32
EXPANDER
PRODUCT
TERMS
(64 FOR 7C344)
NOTE: ONE SYSTEM CLOCK PER LAB
PIA
111
C340-4
Figure 4. Macrocell Block Diagram
MACROCELL
P-TERMS
FROM
MACROCELL
IN LAB
THREE-STATE
BUFFER
•
•
EXPANDER
P-TERMS
TO PIA (LAB FOR 7C344)
C340-5
Figure 6, I/O BlQck Diagram
Figure 5. Expander Prodnci Terms
4-148
C340-6
.- ·aPR£§
,
CY7C340 EPLD Family
SEMICONDUCTOR
Functional Description (continued)
associated LAB. The feedback path from the I/O pin may feed other blocks within the LAB, as well as the PIA. By decoupling the I/O
pins from the flip-flops, all the registers in the LAB are "buried,"
allowing the I/O pins to be used as dedicated outputs, bidirectional
outputs, or as additional dedicated inputs. Therefore, applications
requiring many buried flip-flops, such as counters, shift registers,
and state machines, no longer consume both the macrocell register
and the associated I/O pin, as in earlier devices.
The Programmable Interconnect Array
PLD density and speed has traditionally been limited by signal
routing; i.e., getting signals from one macrocell to another. For
smaller devices, a single array is used and all signals are available to
all macrocells. But as the devices increase in density, the number of
signals being routed becomes very large, increasing the amount of
silicon used for interconnections. Also, because the signal must be
global, the added loading on the internal connection path reduces
the overall speed performance of the device. The MAX architecture solves these problems. It is based on the concept of small, flexible logic array blocks that, in the larger devices, are interconnected by a PIA.
The PIA solves interconnect limitations by routing only the signals
needed by each LAB. The architecture is designed so that every
sig~al on the chip is within the PIA. The PIA is then programmed
to gIve each LAB access to the signals that it requires. Consequent1y' each LAB receives only the signals needed. This effectively
solves any routing problems that may arise in a design without degrading the performance of the device. Unlike masked or programmabIe gate arrays, which induce variable delays dependent on
routing, the PIA has a fixed delay from point to point. This eliminates undesired skews among logic signals, which may cause
glitches in internal or external logic.
sign entry. VHDL provides a number of significant benefits for the
design entry process. Warp2 accepts VHDLinput, synthesizes and
optimizes the entered design, and outputs a JEDEC map for the
desired device. For simulation, Warp2 provides the graphical
waveform simulator from the PLD ToolKit.
VHDL (VHSIC Hardware Description Language) is an open,
powerful, non-proprietary language that is a standard for behavioral design entry and simulation. It is already mandated for use by
the Department of Defense, and supported by every major vendor
of CAE tools. VHDL allows designers to learn a single language
that is useful for all facets of the design process.
Wary3
Warp3 is a sophisticated design tool that is based on the latest version of ViewLogic's CAE design environment. Warp3 features
schematic capture (ViewDraw®), VHDL waveform simulation
(ViewSim®), a VHDL debugger, and VHDL synthesis, all integrated in a graphical design environment. Warp3 is available on
PCs using Windows 3.1 or subsequent versions, and on Sun
workstations.
For further information on Warp software, see the Wmp2 and
Walp3 Datasheets contained in this data book.
Ordering Information
Device Adapters
CY3340
Adapter for CY7C341 in PLCC packages.
CY3340F
Adapter for CY7C341 in PGA packages.
CY3342
Adapter for CY7C342 in PLCC packages.
CY3342F
Adapter for CY7C342 in Flatpack
packages.
Development Software Support
CY3342R
Adapter for CY7C342 in PGA packages.
Wary2
CY3344
Adapter for CY7C344 in DIP and PLCC
packages.
Walp2 is a state-of-the-art VHDL compiler for designing with Cypress PLDs and PROMs. Warp2 utilizes a proper subset of IEEE
1076 VHDL as its Hardware Description Language (HDL) for de-
CY33435
Adapter for CY7C343 in PLCC packages.
Document #: 38-00087-C
4-149
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CY7C341
CY7C341B
192-Macrocell MAX® EPLD
Features
• 192 macrocells in 12 LABs
• 8 dedicated inputs, 64 bidirectional
I/O pins
• Programmable interconnect array
• 384 expander product terms
• Available in 84-pin HLee, PLee, and
PGA packages
Functional Description
TheCY7C341andCY7C341BareErasabie
Programmable Logic Devices (EPLD) in
which CMOS EPROM cells are used to configure logic functions within the device. The
MAX architecture is 100% userconfigurable
allowing the devices to accommodate a variety of independent logic functions.
The 192 macrocells in the CY7C341 and
CY7C341B are divided into 12 Logic Array
Blocks (LABs), 16 per LAB. There are 384
expander product terms, 32 per LAB, to be
used and shared by the macrocells within
each LAB. Each LAB is interconnected
with a programmable interconnect array,
allowing all signals to be routed throughout
the chip.
The speed and density of the CY7C341
and CY7C341B allows them to be used
in a wide range of applications, from replacement oflarge amounts of7400 series
TTL logic, to complex controllers and multifunction chips. With greater than 37 times
the functionality of 20-pin PLDs, the
CY7C341 and CY7C341B allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the
CY7C341 and CY7C341B reduces board
space, part count, and increases system
reliability.
Each LAB contains 16 macrocells. In
LABs A, F, G, and L, 8 macrocells are connected to I/O pins and 8 are buried, while
for LABs B, C, D, E, H, I, J, and K, 4 macrocells are connected to I/O pins and 12 are
buried. Moreover, in addition to the I/O
and buried macrocells, there are 32 single
product term logic expanders in each LAB.
Theiruse greatly enhances the capability of
the macrocells without increasing the number of product terms in each macrocell.
ing WafP software or by the model shown
in Figure 1. The CY7C341
and
There are 12 logic array blocks in the
CY7C341B have fixed internal delays, alCY7C341 and CY7C341B. Each LAB conlowing the user to determine the worst
sists of a macrocell array containing 16 macase timing delays. for any design. For
crocelis, an expander product term array concomplete timing information, the WafP
taining 32 expanders, and an I/O block. The
software provides a timing simulator.
LAB is fed by the programmable interconnect array and the dedicated input bus. All Design Recommendations
macrocell feedbacks go to the macrocell For proper operation, input and output
array, the expander array, and the program- pins must be constrained to the range GND
mable interconnect array. Expanders feed ~ (VIN or VOUT) ~ Vee- Unused inputs
themselves and the macrocell array. All I/O . must always be tied to an appropriate logic
feedbacks go to the programmable intercon- level (either Vee or GND). Each set of
nect aITay so that they may be accessed by Vee and GND pins must be connected tomacrocells in other LABs as well as the ma- gether directly at the device. Power supply
crocells in the LAB in which they are situated. decoupling capacitors of at least 0.2 IlF
Externally, the CY7C341 and CY7C341B must be connected between Vee and
provide 8 dedicated inputs, one ofwhich may GND. For the most effective decoupling,
be used as a system clock. There are 64 I/O each Vee pin should be separately depins that may be individually configured for coupled toGND, directly atthe device. Decoupling capacitors should have good freinput, output, or bidirectional data flow.
quency response, such as monolithic ceProgrammable Interconnect Array ramic types.
The Programmable Interconnect Array Design Security
(PIA) solves interconnect limitations by The CY7C341 and CY7C341B contain a
routing only the signals needed by each log- programmable design security feature that
ic array block. The inputs to the PIA are controls the access to the data prothe outputs of every macrocell within the grammed into the device. If this programdevice and the I/O pin feedback of every mable feature is used, a proprietary design
pin on the device.
implemented in the device cannot be coUnlike masked or programmable gate ar- pied or retrieved. This enables a high levrays, which induce variable delay depen- el of design control to be obtained since
dent on routing, the PIA has a fixed delay. programmed data within EPROM cells is
This eliminates undesired skews among invisible. The bit that controls this funclogic signals, which may cause glitches in in- tion, along with all other program data,
ternal or externallogic. The fixed delay, re- may be reset simply by erasing the device.
gardless of programmable interconnect The CY7C341 and CY7C341B is fully funcarray configuration, simplifies design by as- tionallytested and guaranteed through comsuring that internal signal skews or races plete testing of each programmable
are avoided. The result is ease of design im- EPROM bit and all internal logic elements
plementation, often in a single pass, with- thus ensuring 100% programming yield.
out the multiple internal logic placement
and routing iterations required for a pro- The erasable nature of these devices algrammable gate aITay to achieve design lows test programs to be used and erased
during early stages of the production flow.
timing objectives.
The devices also contain on-board logic
Timing Delays
test circuitry to allow verification of funcTiming delays within the CY7C341 and tion and AC specification once encapsuCY7C341B may be easily determined us- lated in non-windowed packages.
Logic Array Blocks
Selection Guide
WafP is a trademark of Cypress Semiconductor Corporation.
4-150
CY7C341
CY7C341B
~
~.~
;ill
~F
CYPRESS
SEMICONDUCTOR
Logic Block Diagram
1 (A6)
INPUT/CLK
-
=
=:=.
2 (A5)
INPUT ......
41 (K6)
INPUT
42 (J6)
INPUT
~~
LAB A
(C5)
(A4)
(B4)
(A3)
(A2)
10
11
(B3)
(A1)
(B2)
8=
~
D--
MACROCELL 1
MACROCELL2
MACROCELL3
MA RDCELL4
'Ar.Rnr.~
"
IACROCEl.n
IAr.ROr.F. 7
IAr.Rnr.F. R
MACROCELL 9 - 16
12
13
14
15
(C2)
(B1)
(C1)
(02)
g:::
g:=
LABSJ
......
;::.
~k
SYSTEM CLOCK
(01)
(E3)
(F2)
(F3)
§:::
D--
22 (G3)
23
25
26
(G1)
(F1)
(H1)
8=
g::
-
~ ~~
LABO
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
~ ~j,.
27
28
29
30
(H2)
(J1)
(K1)
(J2)
§:::
B-
LABE
MACROCELL 65
MACROCELL 66
MACROCELL 67
MACROCELL 68
-.il
J1..-
----1\
(L1)
(K2)
(K3)
(L2)
~
~
(L3)
~
(K4)
(L4)
(J5)
~
~
=rD---
'Ar.Rnr.~
R7
IACROCEl . RR
MACROCELL 89 - 96
~
(L6)
(L8)
(K8)
(L9)
(L10)
(K9)
(L11)
(K10)
•
In
C
..J
0..
~
54
55
56
57
(J10)
(K11)
(J11)
(H10)
~
r--o
58
59
62
63
(H11)
(F10)
(G9)
(F9)
~
64 (F11)
~
r---o
69
70
71
72
t:§
73
74
75
76
77
78
79
~
"\r"""--
P
I
~
A
~
~~ ~
----l\
LAB I
MACROCELL 129
MACROCELL 130
MACROCELL 131
MACROCELL 132
--V
;1----
r--v
MACROCELL 133 - 144
"\r"""--
~~ ~
JL-
---l\
LABJ
MACROCELL 145
MACROCELL 146
MACROCELL 147
MACROCELL 148
--V
~
;1----
r--v
~
-
65 (E11)
67 (E9)
68 (011)
MACROCELL 149 - 160
"\r"""--
~j,. ~
----l\
1J1..-
y
~
JL-'\r-
LABK
MACROCELL 161
MACROCELL 162
MACROCELL 163
MACROCELL 164
.J\.
J1..-
--V
"
It...--
r----1'
r--v
'\rC>C>-
Vee
GNO
4-151
(010)
(C11)
(B11)
(C10)
MACROCELL 165 - 176
~> ~
3,24,45,66 (B5, G2, K7, E10)
18,19,39,40,60,61,81,82 (E1, E2, K5, L5, G10, G11, A7, B7)
~
46
47
48
49
50
51
52
53
;1----
r--v
~ ~>
LABF
MACROCELL 81
MACROCELL 82
MACROCELL 83
MACROCELL 84
MACROCELL 85
MACROCELL 86
~
MACROCELL 117 - 128
r----v
31
32
33
34
35
36
37
38
.~
LABH
MACROCELL 113
MACROCELL 114
MA ROC ELL 115
MACROCEL.116
Y
'If
MACROCELL 69 - 80
LABG
'\r-
'If
MACROCELL 53 - 64
(J7) 43
~
--v
'If
MACROCELL 37 - 48
(L7) 44
INPUT
MACROCELL 105 - 112
'If
~
16
17
20
21
INPUT
;1----
..I\.
'If
~ ~~
(C7) 83
r----1'
J1..-
MACROCELL 21 - 32
LABC
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 3R
(C6) 84
INPUT
MACROCELL 97
MACROCELL 98
MACROCELL 99
MACROCELL 100
MACROCEL . 101
MACROCEl . 102
MAr.ROr.F. 1m
MAr.Rnr.F. 10d
~~
MACROCELL 17
MACROCELL 18
MA ROC ELL 19
MA ROCEl.20
--
INPUT
LABL
MACROCELL 177
MACROCELL 178
MACROCELL 179
MACROCELL 180
MACROCELL 181
MACROCELL 182
MACROCEL .183
MACROCEL . 184
MACROCELL 185 - 192
~
(A11)
(B10)
(B9)
(A10)
(A9)
(B8)
(A8)
80 (B6)
() - PERTAIN TO 84-PIN PGA PACKAGE
C341-1
CY7C341
CY7C341B
dBF~~
.J'
~=CYPRESS
~_
SEMICONDUCTOR
Pin Configurations
PGA
PLCCIHLCC
Top View
Bottom View
:5
Q.
(.)5 55 5
0
I/O
31
I/O
34
I/O
35
I/O
37
GND
40
I/O
46
INPUT
44
I/O
47
I/O
49
I/O
50
I/O
52
I/O
29
I/O
32
I/O
33
I/O
36
GND
39
INPUT
41
Vee
I/O
48
I/O
51
I/O
53
I/O
55
I/O
28
I/O
30
I/O
54
I/O
56
H
I/O
26
I/O
27
I/O
57
I/O
58
G
I/O
23
Vee
24
I/O
22
I/O
62
GND
60
GND
61
I/O
25
I/O
20
I/O
21
I/O
I/O
59
I/O
64
GND
19
GND
18
I/O
17
Vee
66
I/O
65
I/O
16
I/O
15
I/O
69
I/O
68
I/O
14
I/O
12
•
I/O
72
I/O
70
I/O
13
I/O
11
I/O
9
I/O
6
I/O
10
I/O
8
I/O
7
I/O
5
0
gggggggg?~~~~~~gggggg
2
J
K
84 B3 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
I/O
I/O
I/O
I/O
I/O
I/O
GND
12
13
14
15
16
17
18
GND
19
I/O' 20
I/O
21
I/O
22
I/O 23
Vee 24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7C341
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
38
INPUT INPUT
43
42
Vee
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
45
7C341
63
I/O
67
I/O
4
INPUT INPUT
84
83
Vee
GND
I/O
81
80
INPUT/
GND
INPUT ClK
2
1
82
3
I/O
78
I/O
75
I/O
74
I/O
71
I/O
79
I/O
77
I/O
76
I/O
73
C341-2
10
11
C341-3
::J
.:.t
~
EXPANDER~
DELAY
tEXP
REGISTER
LOGIC ARRAY~h
] CONTROL DELA
tClR
r--!I
IN
~
INPUT
DELAY
~
tiN
H
H
~
J
tLAC
.:.t
~
LOGIC ARRAY
DELAY
tLAD
I
I
~
tplA
~
~
tRSU
tRH
f.------iI
I
CLOCK
DELAY
..
tpRE
SYSTEM CLOCK DELAY tiCS
PIA
DELAY
~,
OUTPUT
DELAY
tRD
tCOMS
tLATCH
...
r-~
too
txz
tzx
INPUTI
OUT PUT
-~
...
...
I
tiC
I LOGIC
ARRAY l
DELAY
tFD
1
I
I
I/O DELAY
tlO
I"
L
I
Figure 1. CY7C341 Internal Timing Model
4-152
C341-4
CY7C341
CY7C341B
.~pRF.SS
·
- . ' SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ........................... O°C to +70°C
Maximum Junction Temperature
(Under Bias) .................................... 150°C
Supply Voltage to Ground Potential. . . . . . .. - 2.0V to + 7.0V
Maximum Power Dissipation .................... 2500 mW
DC Vee or GND Current ........................ 500 rnA
DC Output Current, per Pin ... . . . . . . .. - 25 rnA to + 25 rnA
DC Input Voltage[1] ..................... - 3.0V to + 7.0V
DC Program Voltage .............................. 13.5V
Static Discharge Voltage ........................ > 1100V
(per MIL-STD-883, method 3015)
Operating Range
Ambient
Temperature
Range
Commercial
Industrial
Military
Vee
5V±5%
O°C to +70°C
- 40°C to +85°C
5V ± 10%
- 55°C to + 125°C (Case)
5V ± 10%
Electrical Characteristics Over the Operating Rangel 2]
a
(I)
C
...I
Description
Parameters
Test Conditions
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
VOH
VOL
VIR
VIL
IIX
Vee
Vee
= Min., IOH = - 4.0 rnA
= Min., IOL = 8 rnA
GND ~ VIN ~ Vee
Vo = Vee or GND
Vee = Max., VOUT = GND[3,4]
loz
los
Output Leakage Current
Output Short
Circuit Current
lee!
Power Supply
Current (Standby)
VI = Vee or GND
(No Load)
Power SUfply
Currend5
VI = Vee or GND (No Load)
f = 1.0 MHz[3, 5]
lee2
tR (Recommended)
tF (Recommended)
Min.
2.4
Max.
Units
V
0.45
2.2
-0.3
-10
Vee+ O.3
0.8
+10
V
V
V
f..I.A
-40
-30
+40
-90
f..I.A
rnA
360
435
380
480
rnA
100
100
ns
ns
Com'l
Mil/lnd
Com'l
Mil/lnd
Input Rise Time
Input Fall Time
rnA
rnA
rnA
Capacitance[6]
Parameters
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. Minimum DC input is - 0.3Y. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns.
2. Typical values are for TA = 25 0 C and Vee = 5Y.
3. Guaranteed but not 100% tested.
4. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5V has
been chosen to avoid test problems caused by tester ground degradation.
5.
6.
= 1 MHz,
Max.
10
20
Units
pF
pF
This parameter is measured with device programmed as a 16-bitcounter in each LAB and is tested periodically by sampling production
material.
Part (a) in AC Test Load and Waveforms is used for all parameters except tER and txz, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
AC Test Loads and Waveforms
R1464Sl
5Vo----_'W......,
5V~R1464Sl
OUTPUT 0 - - - " " , - - - " ,
FI
50 P
ALL INPUT PULSES
OUTPUT
R2
250Sl
5pF
3.0V ----.u------~
I
R2
250Sl
(b)
C341-5
GND
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
THEVENIN EQUIVALENT (commercial/military)
163Sl
OUTPUT ().O-----'.II'I
..'Y·- - - - 0 0 1.75V
4-153
C341-6
a.
CY7C341
CY7C341B
~
.
:~PRESS
-:::;;;;;;, SEMICONDUCTOR
External Synchronous Switching Characteristics Over the Operating Rangd 6)
7C341B;L'20 '
7C~41B-lS
Parameter
tpDl
tpD2
tpD3
tpD4
tEA
tER
Description
Dedicated Input to
Combinatorial Output Delay[7)
Com'l
I/O Input to Combinatorial
Output Delay[B)
Com'l
Dedicated Input to
Combinatorial Output Delay with
Expander Delay(9)
Com'l
I/O Input to Combinatorial Output Delal< with Expander
Delay[3, 0)
Com'l
Input to Outp'ut
Enable Delay[3, 7)
Input to Output Disable DelayloJ
(
Max.
15
,
Mil
Min.
Max.
Mill.
,
Mil
tC02
tSI
tS2
tH
tWH
tWL
tRW
tRR
tRO
tpw
Com'l
Dedicated Input or Feedback SetupTime to Synchronous Clock
Outputf6,12)
I/O Input Set-up Time to
Synchronous Clock InputfB)
Input Hold Time from
Synchronous Clock Inputf6)
Synchronous Clock Input
High Time
Synchronous Clock Input
Low Time
Asynchronous Clear WidthlJ , OJ
,
15
Asynchronous Preset WidthlJ , OJ
I'.."'
,
,
Asynchronous Preset
Recovery Timd3, 6)
,
,
'
25
ns
25
14
ns
14
20
30
ns
20
"
:
..
,·,17;;,
.. U'
;,
Mil
.";-' .
,":
Com'l
X.i ~(j{
Mil
t(~;
r:':;·: 22
r " ,:22
,.,
1.
!:~~;,~i!
:
.1::
I
4-154
,I
20
.,
Ii> ~~f'
.;
ns
rw '
.'.:'
ns
~
"
ns
251+4;'
25
ns
'~25\:~ ~.
,,::
25
".,
ns
15F-=
r~lq.;
20
15
•
I,.?
I':
v;.;.";';'
25
1 ',:
~J "20'v
l,Q" 'I;
'"
8'
I'~;
25
.,
Com'l
I>
.J
Mil
I
h
,:,,;'
\
I'
I": . ,ii
25
'.i5;;·j:
'i
Com'l
.'
I')
22
::1
8.
8
T
i7,.
M:
Mil
ns
8
<,'.,
'j]''';
. '.',1
w
ns
.
0
,.
'. . . ?,.,
5
ns
,
0
0
Mil
Com'l
30
30
0
;:
'
5,
Com'l
,
24
,
,
,
ns
15
24
0
Mil
15
12
20
Com'l
30
12
10
Mil
Mil
ns
25
8
..
17
Mil
tpR
25
8
1
{
Com'l
Com'l
ns
52
20
7
Com'l
Asynchronous Clear to Registered
Output Delay(5)
52
20
Mil
Com'l
ns
20
, .'
Mil
Asynchronous Clear
Recovery[3, 7)
'40
.37
20
'-''''
Com'l
Synchronous Clock to Local Feedback to Combinatorial
Output[3, 11)
ns
,
37
43
15
Com'l
Mil
,
43
Mil
Com'l
'
'
e.
,
Mil
Synchronous Clock Input to
Output Delay
40
30
Mil
ns
""',
"
33
23
Unit
2,'( "
33
Mil
tcO!
i,
20
,25
33
l\!aX.
Mi~.;~'
Max.
25
20
'\
7C3~lB'~!25
7C341-25
Min.
!.
25:
'
I
ns
, I
CY7C341
CY7C341B
. .~
~~CYPRESS
,
SEMICONDUCTOR
External Synchronous Switching Characteristics Over the Operating Rangel6](continued)
Parameter
tpo
Description
Asynchronous Preset to Registered
Output Delay[6]
7041B-15
7C341B-20
Min.
Min.
Max.
Synchronous Clock to Local
Feedback Input[3, 13]
3
Com'l
fMAXl
fMAX2
fMAX3
fMAX4
tOR
External S~nchronous Clock Period
(lIfMAX3) ]
External Feedback Maximum
Frequency (l/(tCOl + tSl»[3, 14]
Internal Local Feedback Maximum
Frequency, lesser of (l/(tSl + tcF»
or (l/teOlP' 15]
Data Path Maximum Frequency, least of
1/(tWL + tW,V6 1/(tSl + tR),
or (l/teOl) , ]
Maximum Register Toggle Frequency
(lI(tWL + tWR»[3, 17]
Output Data Stable Time from
Synchronous Clock Input[3, 18]
25
Max~
25
3
;
.
3
12
Com'l
16
ns
14
'50;
58.8
Com'l
16
.
..
34.5
50
Mil
76.9
Com'l
1<
Mil
Com'l
100
66.6
".
Com'l
100
71.4
0
62.5
Com'l
3
3
3
Mil
MHz
...
62.5
MHz
625.,,- .
3
'.'
ns
.3;.;1':'
Shaded areas contain preliminary informatIOn.
Notes:
7.
This specification is a measure of the delay from input signal applied
to a dedicated input to combinatorial output on any output pin. This
delay assumes no expander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates
that the signal (data, asynchronous clock, asynchronous clear, and/or
asynchronous preset) is applied to a dedicated input only and no signal
path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin an additional delay equal to
tpIA should be added to the comparable delay for a dedicated input.
If expanders are used, add the maximum expander delay tEXP to the
overall delay for the comparable delay without expanders.
8. This specification is a measure of the delay from input signal applied
to an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
9. This specification is a measure of the delay from an input signal appli ed
to a dedicated input to combinatorial output on any output pin. This
delay assumes expander terms are used to form the logic functions and
includes the worst-case expander logic delay for one pass through the
expander logic.
10. This specification is a measure ofthe delay from an input signal applied
to an I/O macrocell pin to any output. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clock to internal feedback of the register output signal to the input of
the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all
feedback is within the same LAB. This parameter is tested periodically
by sampling production material.
12. If data is applied to an I/O input for capture by a macrocell register, the
I/O pin set-up time minimums should be observed. These parameters
are tS2 for synchronous operation and tAS2 for asynchronous operation.
13. This specification is a measure ofthe delay associated with the internal
register feedback path. This is the delay from synchronous clock to
LAB logic array input. This delay plus the register set-up time, tSl, is
the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB.
This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed
to be local originating within the same LAB.
15. This specification indicates the guaranteed maximum frequency at
which a state machine, with internal-only feedback, can operate. Ifregister output states must also control external points, this frequency can
still be observed as long as this frequency is less than lIteOl.
16. This frequency indicates the maximum frequency at which the device
may operate in data path mode (dedicated input pin to output pin).
This assumes data input signals are applied to dedicated input pins and
no expander logic is used. If any of the data inputs are I/O pins, tS2 is
the appropriate ts for calculation.
17. This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which an individual output or buried register can
be cycle by a clock signal applied to the dedicated clock input pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on
the output pin.
4-155
en
C
MHz
62.5
•
..J
55.5
71.4
Mil
MHz
55.5
71.4
Mil
..
34.5
.....66.6
71.4
ns
3
14
Mil
Unit
ns
"
...........
3
Mil
tp
.7C341B-25
Max. Min.
20
Mil
tCF
Min.
. 20
15
Com'l
7C341-25
Max.
£L
CY7C341
CY7C341B
~
.
;~PRESS
~,
SEMICONDUcrOR
External Synchronous Switching Characteristics Over the Operating Rangd6] (continued)
7C341-30
Parameter
tpDl
Description
Min.
Dedicated Inp.ut to Combinatorial
Output Delay[7]
Max.
7C341-35
Min.
Max.
Com'l
30
35
Mil
30
35
tPD2
I/O Input to Combinatorial
Output Delay[8]
Com'l
45
55
Mil
45
55
tPD3
Dedicated Input to Combinatorial
Output Delay with Expander Delay[9]
Com'l
44
55
Mil
44
55
tpD4
I/O Input to Combinatorial Output Delay with
Expander Delay[3, 10]
tEA
Input to Outp'ut
Enable Delay[3, 7]
tER
Input to Output Disable DelayLO]
tcOl
tC02
tS1
tS2
tH
tWH
tWL
tRW
tRR
tRO
tpw
tpR
Com'l
59
75
Mil
59
75
Com'l
30
35
Mil
30
35
Com'l
30
35
Mil
30
35
Synchronous Clock Input to
Output Delay
Com'l
16
20
Mil
16
20
Synchronous Clock to Local Feedback
to Combinatorial Output[3, 11]
Com'l
35
42
35
42
Dedicated Input or Feedback Set-upTime to
Synchronous Clock Outputl6,12]
Com'l
20
25
Mil
20
25
I/O Input Set-up Time to
Synchronous Clock Input[8]
Com'l
39
45
Mil
39
45
Input Hold Time from
Synchronous Clock Inputl6]
Com'l
0
0
Mil
0
0
Com'l
10
12.5
Mil
10
12.5
Synchronous Clock Input
High Time
Synchronous Clock Input
Low Time
Asynchronous Clear WidthLJ, OJ
Asynchronous Clear
Recovery[3, 7]
Asynchronous Clear to Registered
Output Delay[S]
Asynchronous Preset WidthLJ, OJ
Asynchronous Preset
Recovery Timd3, 6]
Mil
Com'l
10
12.5
Mil
10
12.5
Com'l
30
35
Mil
30
35
Com'l
30
35
Mil
30
35
Com'l
30
35
Mil
30
35
4-156
ns
65
ns
90
ns
40
ns
40
ns
23
ns
48
ns
ns
15
ns
15
ns
40
ns
40
35
35
65
0
35
35
ns
ns
30
30
ns
40
52
30
30
Unit
ns
Com'l
Com'l
Max.
28
Mil
Mil
7C341-40
Min.
ns
40
ns
40
ns
40
CY7C341
CY7C341B
=~
_ ' I E CYPRESS
-:::;;, SEMICONDUCTOR
External Synchronous Switching Characteristics Over the Operating Rangd6](continued)
7C341-30
Parameter
Description
Min.
Max.
7C341-35
Min.
Max.
Asynchronous Preset to Registered
Output Delay[6]
Com'l
30
35
Mil
30
35
tCF
Synchronous Clock to Local
Feedback Input[3, 13]
Com'l
3
5
tp
External S~nchronous Clock Period
(l/fMAX3) ]
tpo
fMAXI
External Feedback Maximum
Frequency (l/(tCOl + tSl))[3, 14]
fMAX2
Internal Local Feedback Maximum
Frequency, lesser of (l/(tSI + tcF))
or (l/tCOlP' 15]
fMAX3
Data Path Maximum Frequency, least of
l/(tWL + t~6 1/(tSI + tH),
or (l/tCOl)' ]
fMAX4
Maximum Register Toggle Frequency
(l/(tWL + tWH))[3, 17]
tOH
Output Data Stable Time from
Synchronous Clock Inputl3, 18]
Mil
20
25
Mil
20
25
Com'l
27.7
22.2
Mil
27.7
22.2
Com'l
43
Mil
43
33
Com'l
50
40.0
Mil
50
40.0
Com'l
50
40.0
Mil
50
40.0
3
3
Mil
3
3
Unit
ns
ns
7
ns
MHz
a
MHz
..J
D.
30
19.6
33
Com'l
Max.
40
5
3
Com'l
4-157
7C341-40
Min.
28.5
MHz
33.3
MHz
33.3
ns
3
tn
C
CY7C341
CY7C341B
~~
~ ill CYPRESS
~, SEMICONDUCTOR
External Asynchronous Switching Characteristics Over the Operating Rangel6] (continued)
Parameter
tACOl
tAC02
tASI
tAS2
tAR
tAWH
tAWL
tACF
tAP
fMAXAI
fMAXA2
fMAXA3
fMAXA4
tAOH
l~~~~~'";;~~ 7C34l1J-1O
"Nlin:« ~NlQ: ~t, Max.
Description
Dedicated Asynchronous Clock Input
to Output Delay[6]
Asynchronous Clock Input to Local
Feedback to Combinatorial Output [19]
Dedicated Input or Feedback Set-up
Time to Asynchronous Clock Input[6]
I/O Input Set-Up Time to
Asynchronous Clock Input[6]
Input Hold Time from Asynchronous
Clock Input[6]
Asynchronous Clock Input
HIGH Timel 6]
Asynchronous Clock Input
LOW Timel 6, 20]
Com'l '7t',,,,;
:i\>"",,;;'
Mil
Com'l
":'
, ,,7 , ',},,20
I;:·,
Max.
'>4
Iii;;:,,'
:.
Mil
6
Com'l
14
18
40
5
Com'l
5
Com'l
"
Mil
Com'l
External Asynchronous Clock Period
(l/fMAX4)
Com'l
'
ns
Mil
40
ns
11
ns
11
'1;'
76.9
58
66.6
58
50
Com'l
Data Path Maximum Frequency in
Asynchronous Model24]
Com'l
Maximum Asynchronous Register
Toggle Frequency l/(tAWH + tAWL)[25]
Com'l
Output Data Stable Time from
Asynchronous Clock Inputl 26 ]
Com'l
15
Mil
:.","
Mil
Mil
';, ,
77
' ·1,: .:.
Mil
.....
9
50
58
58
15
15
ns
<
9
15
ns
,L •.
::\
1
20
15
ns
'fOy
~
Maximum Internal Asynchronous
Frequency[23]
~,~<
6
13
13" ,
14
14
ns
ns
6
10
12.,
...
2Qr
Mil
Mil
:
20
7
7
..
...•...........
5
7
Mil
ns
25
5
6
6
7;
5
Com'l
Mil
Unit
40
18
Mil
Max,
.
32
'32
6
7C341B-15
Min.
25
20
5· ":
'n
Com'l
Asynchronous Clock to Local
Feedback Inpud 21 J
External Feedback Maximum
Frequency in Asy'nchronous Mode
l/(tACOl + tASl)[22]
.;:.
Mil
1;;:J;~y
7C341-25
Min.
33.3
MHz
33.3
..
I:
50
50
40
.,
MHz
I'
MHz
40.
:;
50
MHz
50
15
ns
15
Shaded areas contam prelimm ary mformatlOn.
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the
input of the LAB logic array and then to a combinatorial output. This
delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the
dedicated clock input pin and all feedback is within a single LAB. This
parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggered clock at the
register. For negative-edge triggering, the tAwH and tAwLparameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL·
21. This specification is a measure of the delay associated with the internal
register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS!. is the
minimum internal period for an internal asynchronously clocked state
machine configuration. This delay is for feedback within the same
LAB, and assumes there is no expander logic in the clock path and the
clock input signal is applied to a dedicated input pin. This parameter
is tested oeriodicallv bv samolin!!: oroduction material.
22. This spe~ification i~d;cates 'the ~g~aranteed maximum frequency at
which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock in-
23.
24.
25.
26.
4-158
puts, and feedback signals are applied to dedicated inputs, and that no
expander logic is employed in the clock signal path or data path.
This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. This parameter is determined by the lesser of
(l/tACF + tASl)) or (lI(tAwH +tAwd). If register output states must
also control external points, this frequency can still be observed as long
as this frequency is less than l/tACOl.
This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification
is determined by the least of l/(tAWH + tAwd, lI(tAsl + tAH) or
1/tACOl. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
This specification indicates the guaranteed maximum frequency at
which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated
input pin.
This parameter indicates the minimum time that the previous register
output data is maintained on the output after an asynchronous register
clock input applied to an external dedicated input pin.
_
·
-
CY7C341
CY7C341B
-~
. .= CYPRESS
JF
SEMICONDUCTOR
External Asynchronous Switching Characteristics Over the Operating Rangel6] (continued)
7C341-30
Parameter
tACO 1
tAC02
tASl
tAS2
tAH
Description
Dedicated Asynchronous Clock Input
to Output Delay[6]
7C341-35
Min.
Max.
30
35
Mil
Com'l
30
46
35
55
Mil
Dedicated Input or Feedback Set-up Time to Com'l
Asynchronous Clock Input[6]
Mil
Com'l
I/O Input Set-Up Time to
Asynchronous Clock Input[6]
Mil
Input Hold Time from Asynchronous
Com'l
Clock Inputl6]
Mil
46
55
Asynchronous Clock Input to Local
Feedback to Combinatorial Output [19]
Asynchronous Clock Input
HIGH Timel6]
tAWL
Asynchronous Clock Input
LOW Timel6, 20]
tAP
Max.
Com'l
tAWH
tACF
Min.
Asynchronous Clock to Local
Feedback Input[21]
External Asynchronous Clock Period
(l!fMAX4)
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
7C341-40
Min.
ns
ns
64
8
6
6
27
ns
8
10
ns
30
27
8
8
14
30
10
33
10
12
ns
ns
14
16
20
11
11
14
14
20
ns
22
22
25
30
25
30
27
23
ns
26
ns
40
MHz
External Feedback Maximum
Frequency in Asynchronous Mode
l!(tACOl + tASl)[22]
Mil
27
23
18
fMAXA2
Maximum Internal Asynchronous
Frequency[23]
Com'l
40
Mil
40
33.3
33.3
25
Data Path Maximum Frequency in
Asynchronous Model 24]
Com'l
33.3
33.3
40
28.5
33.3
22.2
25
15
fMAXA4
tAOH
Maximum Asynchronous Register
Toggle Frequency 1/(tAWH + tAWL)[25]
Output Data Stable Time from
Asynchronous Clock Input[26]
Mil
Com'l
Mil
Com'l
40
15
33.3
15
Mil
15
15
4-159
MHz
28.5
a
tn
C
...J
16
18
18
Unit
45
fMAXAl
fMAXA3
Max.
MHz
MHz
ns
c..
CY7C341
CY7C341B
.::~
~ICYPRESS
-==- ,
SEMICONDUCTOR
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT _ _ _ _ __
~
tpD1[7]~PD2[8[ ~_ _ _ _ _ _ _ __
COMBINATORIAL
OUTPUT
I---
=1----------4
COMBINATORIAL - - - - - - - - - tER(6)
REGISTERED OUTPUT _ _ _ _ _ _- : - _ _ _ _
j..--
tEA!3,7)
•
HIGH IMP~~tT~~~ - - - - - - - - - - - -
HIGH-IMPEDANCE
3-STATE
VALID OUTPUT
----------
C341-7
External Synchronous
DEDICATED INPUT/
I/O INPUT(7)
~._ _-:-_ _
tS1
SYNCHRONOUS
CLOCK - - - - - - '
tOH
ASYNCHRONOUS
CLEAR/PRESET(7) _ _ _ _ _ _+-+-_+-J
REGISTERED
OUTPUTS _ _ _ _ _--:--I~~
"I.~----
tC02
-------i~
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK(10)
- - - - - - - -
""'""----C341-a
External Asynchronous
DEDICATED INPUT/
I/O INPUT(7)
~._ _~_ _
tAS1
ASYNCHRONOUS
CLOCK INPUT - - - - - - '
ASYNCHRONOUS
CLEAR/PRESET(7)
------+-+--+-"'
ASYNCHRONOUS REGISTERED
OUTPUTS _ _ _ _ _--:---1~~
1-1-----..
tAC02
------l~
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED FEEDBACK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ __
C341-9
4-160
CY7C341
CY7C341B
,ap-
=:?
:~PRESS
- , SEMICONDUcrOR
Internal Switching Characteristics Over the Operating Rangel 1]
Parameter
tIN
Description
Dedicated Input Pad and
Buffer Delay
tlO
I/O Input Pad and
Buffer Delay
tEXP
tLAD
tLAC
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
too
Output Buffer and Pad Delay
tzx
Output Buffer Enable DeiaylL/J
txz
tRSU
tRH
Output Buffer Disable Delay
Register Set-Up Time Relative to
Clock Signal at Register
Register Hold Time Relative to
Clock Signal at Register
7C341B-15
7041B-20
Min.
Min.
Max.
Max.
4
4
4
4
10
10
10
10
5
5'
Com'l
3
:.
Mil
Com'l
3
,
Mil
Com'l
8
Mil
Com'l
8
Mil
..:.
Com'l
5
Mil
"
:.
Com'l
3
3
'i"
Mil
3
Com'l
5
5""
,
Mil
5
;
:'>'
Com'l .j'
5
'5
:.
,5
Mil
.'
Com'l
;'L.
5
Mil
;5 I·
.'''''.
Com'l
:;
4
5
Mil
5
,-:,;:
:1
1
Com'l
Mil
1
..
,",
1 ..
Com'l
f,· , ,.'.{..
.".,'C.
;1
Mil
it
Com'l
"1
+,~,
'tii'
'I"~
Mil
.iV<
.; 1
:;!
'6
Com'l
~.j, •.
Mil
~(;
6
,),;f;'
L
Com'l
4
6
';>.
V
Mil
6
. ".
j~,:
Com'l
i
8
:L·.,·
Mil
.
. ....
:.:~8
;'~>;;;;
,:#~:(•. ,
Com'l
0
.,
, 1
Mil
'dO
1:
Com'l
1
·.f~l\;·
1\."
Mil
1
ii:l~
<,;"
3,
Com'l
;;;#;
3,.:,
.;:}i
:~: 3
.3,';
Mil
:.
./.
Com'l
3
:. 'IV'
~f
,,'
Mil
3,;:j.,.
' i,i%¥ ....:.. ~.
3;
:~:
Com'l
{'~ ..... 4: .."
4:
Mil
"1~:1;
:;;;is
::(
Com'l
3,'s .' ':f:~ 4;;
4';
.':'
Mil
Com'l
.i~g:;:
1Qf
1'3
';: ,"
Mil
13··
:."l".J
7C341-25
Min.
7041B-25
Min. . MaL
Max.
5
,.:....
5
....
6
tRO
tCOMB
tCH
tCL
tIC
tICS
tpo
tpRE
tCLR
tpcw
tpCR
Flow-Through Latch Delay
Register Delay
Transparent Mode DeiaylLIIJ
Clock High Time
Clock Low Time
Asynchronous Clock Logic Delay
12
ns
12
12
ns
Feedback Delay
Asynchronous Register Preset
Time
Asynchronous Register Clear Time
Asynchronous Preset and
Clear Pulse Width
Asynchronous Preset and
Clear Recovery Time
Programmable Interconnect
Array Delay Time
Shaded areas contam prelimmary mtormation
tPIA
12
.;
.:'
10
ns
10
,
ns
5
10
:.
.'..
ns
'"
',:
6
10
.•...
ns
~.
'6
6
·.'if>
ns
,;:;
ns
6
3
I,
3
.
1
......
I '..
3
}~,;
I.:
8
ns
,.
':.f
ns
ns
·'ii.
8
14
ns
3
fj:::8
..
8
.
1
••;i:
ns
I'
<14
2
l;"
ns
.;,/~
:.
1
·Y.::r'?
..
ns
1
5
i:r#'
ns
.
5
5
>Ii
'·Y
5
ns
,:/
5
:;
.Tf;~f
ns
",'
.;;;;:\
5
ns
:$
14
.'
.!
.:.
14
ns
~.
Notes:
27. Sample tested only for an output change of 500 mY.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-161
C
..J
Q.
ns
10
10
II
en
,
5
.
Synchronous Clock Delay
ns
>;
6
'
tLATCH
Unit
ns
,'
CY7C341
CY7C341B
;~PRESS
--=-,
.-
SEMICONDUCTOR
Internal Switching Characteristics Over the Operating Rangel l ]
Parameter
tIN
Description
Dedicated Input Pad and
Buffer Delay
tlO
I/O Input Pad and
Buffer Delay
tEXP
tLAD
tLAC
taD
tzx
txz
tRSU
tRH
tLATCH
tRD
tCOMB
tCH
tCL
tIC
tICS
tpD
tpRE
tCLR
tpcw
tpCR
tPIA
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delayl.t'lJ
Output Buffer Disable Delay
Register Set-Up Time Relative to
Clock Signal at Register
Register Hold Time Relative to
Clock Signal at Register
Flow-Through Latch Delay
Register Delay
'Itansparent Mode DelayPuJ
Clock High Time
Clock Low Time
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Asynchronous Preset and
Clear Pulse Width·
Asynchronous Preset and
Clear Recovery Time
Programmable Interconnect
Array Delay Time
7C341-30
Max.
7
7
6
6
14
14
14
14
12
12
5
5
11
11
11
11
8
8
8
8
4
4
2
2
4
4
10
10
10
10
16
16
2
2
1
1
6
6
6
6
6
6
6
6
16
16
Min.
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
4-162
7C341-35
Max.
9
9
9
9
20
20
16
16
13
13
6
6
13
13
13
13
10
10
10
10
4
4
2
2
4
4
12.5
12.5
12.5
12.5
18
18
3
3
2
2
7
7
7
7
7
7
7
7
20
·20
Min.
7C341-40
Max.
Min.
Unit
ns
11
ns
12
ns
25
ns
18
ns
14
ns
7
ns
15
ns
15
ns
12
ns
12
ns
4
ns
2
ns
4
ns
15
ns
15
ns
20
ns
4
ns
3
ns
8
ns
8
ns
8
ns
8
ns
24
=.
CY7C341
CY7C341B
~~
CYPRESS
•
,g
~,
SEMICONDUCTOR
Switching Waveforms (continued)
Internal Combinatorial
tlN-
*
INPUT PIN
tlO
.~tPIAI
1/0 PIN
~tEXP-
a
3K
EXPANDER
ARRAY DELAY
I+-LOGIC ARRAY
INPUT
tLAC, tLAD -
tn
Q
)K
..J
Q.
)K
LOGIC ARRAY
OUTPUT
C341-10
}_tF-J,'{..-,...-----------r
Internal Asynchronous
tR
C
"i-
~I:= lAWH ~,
CLOCK PIN
tiN
1V
r.--
CLOCK INTO
LOGIC ARRAY
CLOCK FROM
~
LOGIC ARRAY
tiC
lAWL
~
~
"''-____/
*t
_
tRSU
tRH
DATAARRAY
FROM
LOGIC
tRD,tLATCH
-+-
,,""--_____
"''-_ _ _ _''''/
_ _ _ _ _ __
t
tFD
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY - - - - - - - - - - - - - - - REGISTER OUTPUT
TO ANOTHER LAB
tClR,tpRE
~IA
-+
tFD
*=
=*____________
C341-11
Internal Synchronous
}=
SYSTEM CLOCK PIN ____""
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
4
tCH
~r.
t'Hlt,cs
~
tCl
-1 /
~
=* -
"''''-_ _ _ _
tRSU
tRH _
•
..J/
"'------
"''-----
----------------------_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
C341-12
4-163
CY7C341
CY7C341B
=t==,
:~PRFSS
SEMICONDUcrOR
Switching Waveforms (continued)
Internal Synchronous
,,'------
CLOCK FROM _ _ _ _ _"/1
LOGIC ARRAY
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C341-13
Ordering Information
Speed
(ns)
15
20
25
30
35
40
Ordering Code
Package
Name
Package 1Ype
Operating
Range
CY7C34IB-15HC
H84
84-Lead Windowed Leaded Chip Carrier Commercial! Industrial
CY7C34IB-15JC/JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C34IB-15RC/RI
R84
84-Lead Windowed Pin Grid Array
CY7C341B - 20HC/HI
H84
84-Lead Windowed Leaded Chip Carrier Commercial/ Industrial
CY7C341B - 20JC/JI
J83
84-Lead Plastic Leaded Chip Carrier
CY7C341B-20RC/RI
R84
84-Lead Windowed Pin Grid Array
CY7C341B-20HMB
H84
84-Lead Windowed Leaded Chip Carrier Military
CY7C341B-20RMB
R84
84-Lead Windowed Pin Grid Array
CY7C341-25GC
G84
84-Pin Pin Grid Array (Cavity Up)
CY7C341-25HC
H84
84-Lead Windowed Leaded Chip Carrier
CY7C341-25JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C341-25RC
R84
84-Lead Windowed Pin Grid Array
CY7C34IB-25HMB
H84
84-Lead Windowed Leaded Chip Carrier Military
CY7C34IB- 25RMB
R84
84-Lead Windowed Pin Grid Array
CY7C341-30GC
G84
84-Pin Pin Grid Array (Cavity Up)
CY7C341-30HC
H84
84-Lead Windowed Leaded Chip Carrier
CY7C341-3OJC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C341-30RC
R84
84-Lead Windowed Pin Grid Array
CY7C341-30HMB
H84
84-Lead Windowed Leaded Chip Carrier Military
CY7C341-30RMB
R84
84-Lead Windowed Pin Grid Array
CY7C341-35GC
G84
84-Pin Pin Grid Array (Cavity Up)
CY7C341-35HC
H84
84-Lead Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Commercial
CY7C341-35JC
J83
CY7C341-35RC
R84
84-Lead Windowed Pin Grid Array
CY7C341-35HMB
H84
84-Lead Windowed Leaded Chip Carrier Military
CY7C341-35RMB
R84
84-Lead Windowed Pin Grid Array
CY7C341-40HMB
H84
84-Lead Windowed Leaded Chip Carrier Military
CY7C341-40RMB
R84
84-Lead Windowed Pin Grid Array
4-164
CY7C341
CY7C341B
~~PRESS
--=-,
·
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VIL
1,2,3
IIX
1,2,3
Ioz
1,2,3
a
IcC!
1,2,3
C
U)
..J
D.
Switching Characteristics
Parameter
Subgroups
tpDl
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
tpD2
tPD3
tCOl
tSl
tH
tACOl
tAC02
tASl
-
tAR
Document #: 38-00137-E
4-165
CY7C342
CY7C342B
128-Macrocell MAX® EPLDs
Features
Functional Description
• 128 macrocells in 8 LABs
• 8 dedicated inputs, S2 bidirectional
I/O pins
• Programmable interconnect array
• Available in 68-pin HLCC, PLCC,
PGA, and Flatpack
The CY7C342/CY7C342B is an Erasable
Programmable Logic Device (EPLD) in
which CMOS EPROM cells are used to
configure logic functions within the device.
The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic
functions.
Each LAB is interconnected with a programmable interconnect array, allowing all
signals to be routed throughout the chip.
The speed and density of the
CY7C342/CY7C342B allows it to be used
in a wide range of applications, from replacement oflarge amounts of740D-series
TTL logic, to complex controllers and multifunction chips. With greater than 25
times the functionality of2D-pin PLDs, the
CY7C342/CY7C342B allows the replacement of over 50 TIL devices. By replacing
large
amounts
of
logic,
the
CY7C342/CY7C342B reduces board
space, part count, and increases system reliability.
The 128 macrocells in the CY7C342/
CY7C342B are divided into 8 Logic Array
Blocks (LABs), 16 per LAB. There are 256
expander product terms, 32 per LAB, to be
used and shared by the macrocells within
each LAB.
Logic Block Diagram
r-
1 (B6)
INPUT/CLK
INPUT
(A7)
68
2 (A6)
INPUT
INPUT
(A8)
66
32 (L4)
INPUT
INPUT
(L6)
36
34 (L5)
INPUT
INPUT
(K6)
35
(A5)
(B4)
(A4)
(B3)
(A3)
9 (A2)
10 (B2)
11 (B1)
4
5
6
7
8
-
- --
LABA
,
b-h
MACROCELL 1
MACROCELL3
MA\.iHU\.it _4
MA(;HU(;I::L 5
MACROCELL6
MACROCEl 7
MACROCELL8
MACROCELL 9-16
12
13
14
15
17
(C2)
(C1)
(02)
(01)
(E1)
---
LABB
!
MAr.ROr.FI
~J.
(F2)
(F1)
(G1)
(H2)
(H1)
--
(J2)
(J1)
(K1)
(K2)
(L2)
(K3)
(L3)
(K4)
---
A
r--v
IV--
A
I\.
'\r-
I--v'
~
litIv-
----v
P
I
A
-
I"V
Vt--
~
----v
Iv-
U
MACROCELL 57-64
MA R
EL
ELL
MACRO ELL
MACROCELL
MA~\..
17
116
115
114
113
it
...
'If
r--v
.J\.
Jl
y
1'1(
3,20,37,54 (B5, G2, K7, E10)
16, 33, 50, 67 (E2, K5, G10, B7)
D-D--
Vec
!
LABG
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
r---
~
~
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
---
(011) 57
(010) 56
(E11) 55
(F11) 53
(F10) 52
--I--
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
-
MACROCELL 102-112
.J.J. !
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86-96
U
~
LABE
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MA ROC ELL.£fi
MACROCEL ,65
~
r---
t--~
r--r---
t---
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
MACROCELL 73-80
( ) - PERTAIN TO 68-PIN PGA PACKAGE
GNO
MAX is a registered trademark of Altera Corporation. Wmp is a trademark of Cypress Semiconductor.
4-166
~
~
~
~
~
MACROCELL 121-128
M~ELL84
I\.
LABO
MA ROC ELL 49
MACROCELL 50
MA(;HUl;I::LL 54
~l. ;~
LAB F
MACROCELL 85
'\f
~
MACROCELL 120
MA(;Hl ;I::L~
MA\.iHl. ;t:LL HI
~>
A
-
-
...
! .J.J.
-
-
r-v
IV--
LAB C
MACROCELL 33
MACROCELL 34
MACROCELL 38-48
24
25
26
27
28
29
30
31
...
A
l'
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22-32
18
19
21
22
23
Jh~"
SYSTEM CLOCK
C342-1
CY7C342
CY7C342B
===-~
.
~;. CYPRESS
- , SEMICONDUCTOR
Selection Guide
250
7C342B-20
20
250
7C342-25
25
250
Commercial
320
225
320
320
--225
Military
Industrial
275
275
275
320
320
225
275
275
7C342B-'15
15'
Maximum Access Time (ns)
Commercial
Maximum Operating
Current (rnA)
Military
Industrial
Maximum Static
Current (rnA)
7C342-30
30
250
320
7C342-35
35
250
320
320
225
275
275
320
225
275
275
II
Shaded area contains preliminary information.
Pin Configurations
II)
C
PLCC/Flatpack
I/O
60J I/O
I/O
59J I/O
I/O
I/O
I/O
58 J I/O
57 J I/O
56J I/O
I/O
GND
55J I/O
0
7C342
7C342B
Vee
I/O
I/O
I/O
54J Vee
53
I/O
INPUT INPUT INPUT
I/O
I/O
I/O
I/O
GND
Vee
1/0
I/O
1/0
I/O
I/O
I/O
1/0
I/O
I/O
I/O
I/O
I/O
Vee
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
Vee
I/O
D
I/O
I/O
I/O
I/O
C
I/O
I/O
I/O
I/O
I/O
46J I/O
I/O
I/O
45J I/O
~~~~~~~~M~E~M~~~~~« J I/O
UUUUUUUUUUUUUUUUU
~~~~~~~~~~~~~~~~~
~
I/O
I/O
I/O
I/O
I/O
G
52J I/O
51 J I/O
50 J GND
49J I/O
48J I/O
47J I/O
~
Q.
Bottom View
K
I/O
I/O
I/O
..J
PGA
Top View
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
7C342
7C342B
B
I/O
I/O
I/O
I/O
Vee
INPUT/
GND
CLK
A
•
I/O
I/O
I/O
I/O
INPUT INPUT INPUT
~ ~
C342-2
I/O
I/O
10
11
C342-3
4-167
CY7C342
CY7C342B
~
¥~PRF.SS
.
-::;;;;;;F
SEM]CONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied .......................... O°C to +70°C
Maximum Junction Temperature
(under bias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150 ° C
Supply Voltage to Ground Potential ....... - 3.0V to +7.0V
Maximum Power Dissipation ................... 2500 m W
DC V cc or GND Current ....................... 500 rnA
DC Output Current per Pin .......... - 25 rnA to + 25 rnA
Electrical Characteristics Over the Operating Rangd 2]
Parameter
Description
DC Input Voltagd 1] .................... - 3.0V to + 7.0V
DC Program Voltage ............................. 13.5V
Static Discharge Voltage ....................... > 1l00V
(per MIL-STD-883, Method 3015)
Operating Range
Ambient
Temperature
O°C to +70°C
5V±5%
- 40°C to +85°C
5V ± 10%
- 55°C to +125°C (Case)
5V ± 10%
Range
Commercial
Industrial
Military
Test Conditions
Min.
= Min., IOH = -4.0 rnA
= Min., IOL = 8.0 rnA
VOH
VOL
VIR
VIL
IIX
loz
los
IcC!
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Output Leakage Current
Output Short Circuit Current
Power Supply Current (Static)
V cc
V cc
ICC2
Power Supply Currentl5]
VI = Vcc or GND (No Load)
f = 1.0 MHz[4]
tR
tp
Recommended Input Rise Time
Recommended Input Fall Time
GND ~ VIN ~ Vcc
Vo = VccorGND
V cc = Max., VOUT = 0.5Vl3,4]
VI = GND (No Load)
Vee
Max.
Unit
2.4
V
V
V
V
0.45
2.2
- 0.3
-10
- 40
- 30
Com'l
Mil/Ind
Com'l
Mil/lnd
Vcc +0.3
0.8
+10
+40
- 90
225
275
250
320
100
100
~
flA
rnA
rnA
rnA
ns
ns
Capacitance[6]
CIN
Parameter
Description
Input Capacitance
COUT
Output Capacitance
Test Conditions
= 2V, f = 1.0 MHz
VOUT = 2V, f = 1.0 MHz
VIN
Notes:
1. Minimum DC input is - 0.3Y. During transitions, the inputs may undershoot to - 3.0V for periods less than 20 ns.
2. 'JYpical values are for TA = 25 0 C and Vee = SY.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground
degradation.
4.
S.
6.
Max.
10
10
Unit
pF
pF
Guaranteed but not 100% tested.
This parameter is measured with device programmed as a 16-bit counter in each LAB.
Part (a) in AC Test Load and Waveforms is used for all parameters except tER and txz, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
AC Test Loads and Waveforms[4]
R1464Q
5V
OUTPUT
R1464Q
31
I _
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
250Q
-
-
OUTP~~31
5pF
I
R2
250Q
INCLUDING _
JIG AND SCOPE
(a)
ALL INPUT PULSES
3.0V - - - --1I~----_s...
GND
_
C342-4
(b)
THEVENIN EQUIVALENT (commercial/military)
163Q
OUTPUT 00---111..111.
.. - - - - 0 0 1.75V
4-168
C342-5
,
CY7C342
CY7C342B
~~
~iE CYPRESS
.
---=-,
SEMICONDUCIOR
Logic Array Blocks
Timing Delays
There are 8 logic array blocks in the CY7C342/CY7C342B. Each
LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O
block. The LAB is fed by the programmable interconnect array and
the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect
array. Expanders feed themselves and the macrocell array. All I/O
feedbacks go to the programmable interconnect array so that they
may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated.
Externally, the CY7C342/CY7C342B provides eight dedicated inputs, one of which may be used as a system clock. There are 52 I/O
pins that may be individually configured for input, output, or bidirectional data flow.
Timing delays within the CY7C342/CY7C342B may be easily determined using Warp@) software or by the model shown in Figure 1.
The CY7C342/CY7C342B has fixed internal delays, allowing the
user to determine the worst case timing delays for any design. For
complete timing information the Wmp@) software provides a timing simulator.
Programmable Interconnect Array
The Programmable InterconnectArray(PIA) solves interconnect limitations by routing only the signals needed by each logic array block.
The inputs to the PIA are the outputs of every macrocell within the
device and the I/O pin feedback of every pin on the device.
Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This
eliminates undesired skews among logic signals that may cause
glitches in internal or external logic. The fixed delay, regardless of
programmable interconnect array configuration, simplifies design
by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a signal pass, without
the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under "Maximum Ra tings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions •
above those indicated in the operational sections of this data~
sheet is not implied. Exposure to absolute maximum ratings
conditions for extended periods oftime may affect device reli- tn
~~~:~~. ~~~ ~:~~f:~/s~~icC:oi;~g~~~~a!r:c~~~~~~~~!~b~tO~~~~ ~
mal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
For proper operation, input and output pins must be constrained to
the range GND ~ (VIN or VOUT) ~ Vec- Unused inputs must always be tied to an appropriate logic level (either Vee or GND).
Each set of V ee and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2
ftF must be connected between Vee and GND. For the most effective decoupling, each Vee pin should be separately decoupled to
GND directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types have.
REGISTER
LOGIC ARRAY
1---+-+-4-I--~ CONTROL DELAY
tlJ\C
1--"""'-'--"
INPUT
OUTPUT
DELAY
OUTPUT
INPUT
DELAY
tiN
tOD
LOGIC ARRAY
DELAY
txz
tzx
tlJ\D
SYSTEM CLOCK DELAY tiCS
CLOCK
DELAY
tiC
C342-6
Figure 1. CY7C342/CY7C342B Internal Timing Model
4-169
,
CY7C342
CY7C342B
==r-:- :~
~.a
::::s;'
CYPRESS
SEMICONDUCTOR
Design Security
Timing Considerations
The CY7C342/CY7C342B contains a programmable design security feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This
enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset
simply by erasing the entire device.
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay
tE)(P to the overall delay. Similarly, there is an additional tPIA delay
for an input from an I/O pin when compared to a signal from
straight input pin.
The CY7C342/CY7C342B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100% programming
yield.
The erasable nature of these devices allows test programs to be
used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification
of function and AC specification once encapsulated in non-windowed packages.
lYpical IcC vs. fMAX
400
ci
~
Vee =5.0V
Room Temp.
.s
ill
>
The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold
times, which is controlled by the same synchronous clock. If tOH is
greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst -case
environmental and supply voltage conditions.
200 -
i=
()
«
()
..2
100 -
o~--~--~----~--~~--~--~
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
..J
1i:
100
IOL
~
«
.s
80
zw
60
I-
The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold
time and using the same asynchronous clock as the
CY7C342.CY7C342B
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or asynchronous)
then the devices are guaranteed to function properly under worstcase environmental and supply voltage conditions, provided the
clock signalsource is the same. This also applies if expander logic
is used in the clock signal path of the driving device, but not for the
driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP) causing
the output data from the preceding device to change prior to the
arrival of the clock signal at the following device's register.
Output Drive Current
«
()
When calculating external asynchronous frequencies, use tASI if all
inputs are on the dedicated input pins. If any data is applied to an
I/O pin, tAS2must be used as the required set-up time. If (tAS2 +
tAR) is greater than tACOl, 1/(tAS2 + tAR) becomes the limiting
frequency in the data path mode unless 1/(tAWH + tAWL) is less
than 1/(tAS2 + tAR),
When expander logic is used in the data path, add the appropriate
maximum expander delay, tEXP to tASI' Determine which of
1/(tAWH + tAwd, 1/tACOl, or 1/(tEXP + tASl) is the lowest frequency. The lowest ofthese frequencies is the maximum data path
frequency for the asynchronous configuration .
300 -
«
When calculating synchronous frequencies, use t81 if all inputs are
on dedicated input pins. The parameter t82 should be used if data .
is applied at an I/O pin. If t82 is greater than tCOl, 1/t82 becomes
the limiting frequency in the data path mode unless 1/(tWH + twd
is less than 1/t82'
When expander logic is used in the data path, add the appropriate
maximum expander delay, tEXP to t81. Determine which of 1/(tWH
+ twd, l/tCOl, or 1/(tEXP + t81) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for
the synchronous configuration.
a:
a:
::l
()
40
I::l
c..
I::l
20
0
..9
o 0.45
2
3
4
5
Va OUTPUT VOLTAGE (V)
4-170
CY7C342
CY7C342B
~.~
~=CYPRESS
~_., SEMICONDUCTOR
Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range
Parameter
1C342B.,..lS 7CJ42B"'20 7C342-25
7C342-30
7C342-35
Min. Max. Min,'; Max. Min. Max. Min. Max. Min. Max.
Description
Unit
tpDl
Dedicated InRut to Combinatorial
Output Delay[7]
15
20:,
25
30
35
ns
tPD2
I/O Input to Combinatorial
Output Delay[8]
.25
~.2
39
46
55
ns
tPD3
Dedicated Input to Combinatorial
Output Delay with
Expander Delay[9]
23
~O
37
44
55
ns
tpD4
I/O Input to Combinatorial
Output Delay with
Expande~ Delay[4, 10]
33
42
51
60
75
ns
" 15
20
25
30
35
ns
20
25
30
35
ns
8
14
16
20
ns
20
30
35
42
ns
tEA
Input to Output Enable
Delay[4,7]
tER
Input to Output Disable
Delay[4,7]
tCOl
Synchronous Clock Input to
Output Delay
J
7
·
Synchronous Clock to Local
Feedback to Combinatorial
Outputl 4,11]
tS1
Dedicated Input or Feedback
Set-Up Time to
Synchronous Clock Input[7, 12]
10
I/O Input Set-Up Time to
Synchronous Clock Input[7]
20
Input Hold Time from
Synchronous Clock Input[7]
0
tH
tWH
tWL
':
:
17
....
12
<.
24
i..
'D
..
I.. ,
Synchronous Clock Input
LOW Time
5' :
.
7'
t
tRW
Asynchronous Clear Width[4, 7]
16 '
22
Asynchronous Clear Recovery
Timel 4,7]
16 :
22
tRO
Asynchronous Clear to Registered
Output Delay[7]
tpR
tpo
..
:
Asynchronous Preset Width[4, 7]
15
Asynchronous Preset Recovery
Timel4,7]
"
15 .
tp
fMAX1
fMAX2
External Synchronous Clock
Period (l/(fMAX3»[4]
20
25
ns
29
36
45
ns
0
0
0
ns
8
10
12.5
ns
8
10
12.5
ns
25
30
35
ns
25
30
35
ns
"
,
.,:
'
..
"'.
' 20
, ,,'
20
'.
;.
20
30
35
ns
25
30
35
ns
25
30
35
ns
20
25
30
35
ns
3
3
6
ns
"
3~
3
.,"
.i
'"
58.8
.,.'
Internal Local Feedback
Maximum Frequency, lesser of
(l/(tS1 + tCF» or (l/tcOl)[4, 15]
100 ,
,
25
,
.:'
······12
<.
., .;
15
External Feedback Maximum
Frequency (l/(tCOl + tS1»[4, 14]
Shaded area contams prehmmary informatIOn.
,
;
Asynchronous Preset to Registered
Output Delay[7]
Synchronous Clock to Local
Feedback Input[4, 13]
'
15
"
tCF
,
7;: '
"i'.
<'
i····
,
0,
,.
·
Synchronous Clock Input
HIGH Time
.
,
tRR
tpw
15
I,
.
,
,"
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. 71.4:
;
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{ .....
."
:.
."
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'
.......
4-171
"'.,
16
20
25
ns
34.5
27.7
22.2
MHz
55.5
43.4
32.2
MHz
"
:
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:
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CY7C342
CY7C342B
~~
~..tECYPRESS
~.' SEMICONDUCTOR
Parameter
Min.
Description
Max. Min.
Max. Min.
Max.
Unit
fMAX3
Data Path Maximum Frequency,
lesser of (1/(tWL + tWH»
4, 16]
(1/(tSI + tH» or ( 1/t
62.5
50
40
MHz
fMAX4
Maximum Register Toggle
Frequency (1/(tWL + twlli)[4, 17]
62.5
50
40
MHz
tOH
Output Data Stable Time from
Synchronous Clock Input[4, 18]
3
3
3
ns
cod
Shaded area contains preliminary information.
Notes:
7. This specification is a measure of the delay from input signal applied
to a dedicated input (68-pin PLee input pin 1,2,32, 34, 35, 66, or 68)
to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates
that the signal (data, asynchronous clock, asynchronous clear, and/or
asynchronous preset) is applied to a dedicated input only and no signal
path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin an additional delay equal to
tpIA should be added to the comparable delay for a dedicated input. If
expanders are used, add the maximum expander delay tEXP to the
overall delay for the comparable delay without expanders.
8. This specification is a measure of the delay from input signal applied
to an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
9. This specification is a measure of the delay from an input signal
applied to a dedicated input (68-pin PLee input pin 1, 2, 32, 34, 35,
36,66, or 68) to combinatorial output on any output pin. This delay
assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the
expander logic.
10. This specification is a measure of the delay from an input signal applied
to an I/O macrocell pin to any output. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clock to internal feedback of the register output signal to the input of
the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all
feedback is within the same LAB. This parameter is tested periodically
by sampling production material.
12. If data is applied to an I/O input for capture by a macrocell register, the
I/O pin input set -up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation.
13. This specification is a measure of the delay associated with the internal
register feedback path. This is the delay from synchronous clock to
LAB logic array input. This delay plus the register set-up time, tSb is
the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same lAB.
This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed
to be local originating within the same lAB.
15. This specification indicates the guaranteed maximum frequency at
which a state machine with internal-only feedback can operate. Ifregister output states must also control external points, this frequency can
still be observed as long as this frequency is less than lIteOl.
16. This frequency indicates the maximum frequency at which the device
may operate in data path mode (dedicated input pin to output pin).
This assumes data input signals are applied to dedicated input pins and
no expander logic is used. If any of the data inputs are I/O pins, tS2 is
the appropriate ts for calculation.
17. This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which an individual output or buried register can
be cycled by a clock signal applied to the dedicated clock input pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on
the output pin.
4-172
.....:::::::==.
CY7C342
CY7C342B
~
fi; CYPRESS
==
,
SEMICONDUcrOR
Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
7C342B~lS;
Parameter
Description
i7C342B·20 7C342-25
Min. Max: Milt'> Maxi Min. Max.
tACOl
Asynchronous Clock Input to
Output Delay[7]
15
tAC02
Asynchronous Clock Input to
Local Feedback to Combinatorial
Output[19]
25
tASl
Dedicated Input or Feedback
Set-Up Time to Asynchronous
Clock Input[7]
I/O Input Set-Up Time to
Asynchronous Clock Input[7]
tAS2
tAR
tAWH
Asynchronous Clock Input
Low Timd?, 20]
tACF
Asynchronous Clock to Local
Feedback Inputl 4, 21]
fMAXAl
fMAXAZ
fMAXA3
fMAXA4
tAOH
j,
External Asynchronous Clock
Period (l/(fMAXA4»[4]
External Feedback Maximum
Frequency in Asynchronous
Mode (1/(tACOl + tASl))[4,22]
Maximum Internal Asynchronous
Frequency[4,23]
'
14 f
;:'
18
Ic,f,;,
A
,
Input Hold Time from
Asynchronous Clock Input[7]
Asynchronous Clock Input
High Time[7]
tAWL
tAP
j
7C342-30
Min. Max.
,
4
4
::
5'
,
'1'
"
5
'7
I
11
12.5
15
ns
11
12.5
15
ns
13
1/,10
15
22
18
ns
L";
14
12" I'
I""A:""
,,"
51.3
40
20
25
30
ns
33.3
27.7
23.2
MHz
50
40
33.3
MHz
40
33.3
28.5
MHz
50
40
33.3
MHz
15
15
15
ns
,"
.>,,,"
71:4
""1:
55.5
"
;'
Data Path Maximum Fre~ency
in Asynchronous Modd4, 4]
66.6
Maximum Asynchronous
Register Toggle Fre~uency
l/(tAWH + tAWL) [4, 5]
Output Data Stable Time from
Asynchronous Clock Input[4, 26]
100'
': L
,
SO'
";
71., j3]
,~
c,;;
15
, l:r~1~,
,,ill':
f!;f'
r '
':
:<
Shaded area contains preliminary information.
Notes:
19. This specification is a measure ofthe delay from an asynchronous register clock input to internal feedback of the register output signal to the
input of the LAB logic array and then to a combinatorial output. This
delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the
dedicated clock input pin and all feedback is within a single LAB. This
parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge triggered clock at the
register. For negative edge triggering, the tAWH and tAWLparameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL.
21. This specification is a measure of the delay associated with the internal
register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tASb is the
minimum internal period for an internal asynchronously clocked state
machine configuration. This delay is for feedback within the same
LAB, assumes no expander logic in the clock path, and assumes that the
clock input signal is applied to a dedicated input pin. This parameter
is tested periodically by sampling production material.
22. This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no
expander logic is employed in the clock signal path or data path.
23. This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. This parameter is determined by the lesser of
(l/(tACF + tASl)) or (l/(tAWH + tAWL)). If register output states must
also control external points, this frequency can still be observed as long
as this frequency is less than 1/tACOl'
This specification assumes no expander logic is utilized, all data inputs
and clock inputs are applied to dedicated inputs, and all state feedback
is within a single LAB. This parameter is tested periodically by sampling production material.
24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification
is determined by the lesser of l/(tAWH + tAWL), 1/(tASl + tAH) or
1/tACOl' It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
25. This specification indicates the guaranteed maximum frequency at
which an individual output or buried register can be cycledin asynchronously clocked mode by a clock signal applied to an external dedicated
input pin.
26. This parameter indicates the minimum time that the previous register
output data is maintained on the output after an asynchronous register
clock input applied to an external dedicated input pin.
4-173
I
tn
Q
...I
D.
CY7C342
CY7C342B
~
.ill CYPRESS
--J~~
,
SEMICONDUCTOR
Commercial and Industrial1YPical Internal Switching Characteristics Over Operating Range
f{;I'1C3i12B~i~j: :~1(;342B~ 2t
Parameter
tIN
Description
;;-:t:,
3, ~:~ 1(,\'
Dedicated Input Pad and
Buffer Delay
t10
I/O Input Pad and Buffer
Delay
tEXP
tLAD
tLAC
tOD
tzx
. ;:;, ..
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay L
Output Buffer and Pad Delay IT
I.; ..•.......
Output Buffer Enable
Delay[27]
.,l
txz
tRSU
Output Buffer Disable Delay
Register Set-Up TimeRelative
to Clock Signal at Register
tRH
Register Hold Time Relative
to Clock Signal at Register
tLATCH
tRD
tCOMB
tCH
tCL
tIC
Flow Through Latch Delay
Register Delay
Transparent Mode Delayl2!SJ
tICS
tFD
tPRE
tCLR
tpcw
tpCR
tPIA
I'Lf, ;
)
Clock HIGH Time
Clock LOW Time
Asynchronous Clock Logic
Delay
,8
f
:';
10
. lz 10,
5
.y ........
3
5
".J;.
,.:::d;l
,">
1:('5,
3 .
'5
::'
7C342-30
Min.
Max.
7C342-35
Min.
Max.
Unit
5
7
9
ns
6
6
9
ns
12
12
10
14
14
12
20
16
13
6
13
ns
ns
ns
ns
ns
13
5
5
10
11
10
5
11
6
8
10
ns
ns
6
8
10
ns
5
41
:
~4
'. ! ti\;;:
•
Max.
j'
,t };1
I" u~
Min.
4
5
k.
,.+ ,"':
4'.;'
~;\:~
~~(
uw
,i'
~
""II
: ~:tt~;~;r
6';
; :'i,
I
~/
r
.
'i
.3\;~
Asynchronous Register Clear
Time
Asynchronous Preset and
Clear Pulse Width
3
Asynchronous Preset and
Clear Recovery Time
3
:SJ;
i
3
14
16
18
2
1
5
2
1
6
2
7
ns
ns
ns
5
6
7
ns
3
:
4
';
1
4
5
6
7
ns
5
6
7
ns
.:
::;5'1
1()~Y
:;i.·'
12.5
12.5
;
3'
I
•
10
10
ns
ns
ns
ns
ns
ns
;"
;, . ~tQJ'i:A
t
•... :
· :t~;
8
8
4
2
4
4
2
4
1
3
"J
6'
6'
•
" ~L '1;!'~
3
tJ
;'
.<
...
i,;}~ ~."
;n~'
1:,; 1';
I"'J
·)."'
>',
'ie,
3
Output Data Stable Time from
Synchronous Clock Inputf4, 18]
,
~';
Shaded area contaInS prehmInary InformatIOn.
Military External Asynchronous Switching Characteristics[6] Over Operating Range
",' 7C342B-25
7C342B-20
Parameter
Min.
Max.
7C342-30
Max.
Max.
Unit
tACOI
20
25
30
35
ns
tAC02
Asynchronous Clock Input to
Local Feedback to Combinatorial Output[19]
32
39
46
55
ns
tASl
Dedicated Input or Feedback
Set-Up Time to Asynchronous
Clock Input[7]
I/O Input Set-Up Time to
Asynchronous Clock Inputf7]
Min.
ns
19
22
28
ns
4
6
8
10
ns
11
12.5
15
ns
11
12.5
15
ns
,
;'
,;,
Input Hold Time from
Asynchronous Clock Input[7]
tAwH
Asynchronous Clock Input
High Timd7]
7
tAWL
Asynchronous Clock Input
Low Timd7, 20]
7
tACF
Asynchronous Clock to Local
Feedback Input[4, 21]
fMAXAI
fMAXA2
External Asynchronous Clock
Period (1/(fMAXA4»[4]
External Feedback Maximum
Frequency in Asynchronous
Mode (1/(tACOI + tASl»[4,22]
Maximum Internal Asynchronous
Frequency[4,23]
15
13 ;'
<,
40
18
22
ns
.:
..
,
Maximum Asynchronous
Register Toggle Fre~uency
1/(tAWH + tAWL) [4, 5]
Output Data Stable Time from
Asynchronous Clock Inputf 4, 26]
71.';
15
30
ns
33.3
27.7
23.2
MHz
40
33.3
MHz
33.3
28.5
MHz
40
33.3
MHz
15
15
ns
;tl~'
~
>'
fMAXA4
25
.(
55.5
71.4
l,'{;;
20
1,:;14
Data Path Maximum Fre~ency
in Asynchronous Modd4, ]
..
Shaded area contaInS prehmInary InformatIOn.
'1'.:'
..'
fMAXA3
tAOH
;
":
:
Min.
8
,', 18
,
,;,
Max.
6
5
tAH
tAP
;; 5
ie"~
Min.
7C342-35
Asynchronous Clock Input to
Output Delay[7]
tAS2
Description
: >.
~j
~I~
it
4-176
'jJ
, ;;:
50
[');
40
"'"'"''
50
'
, \ &/<"',
,.,',
15
7
i;;;
l
·
CY7C342
CY7C342B
.~
_ ' i I CYPRESS
- . ' SEMICONDUCTOR
Military 1Ypical Internal Switching Characteristics Over Operating Range
Parameter
tIN
Description
7C342B-20
Max.
Min.
Dedicated Input Pad and
Buffer Delay
7C342B-25
Max.
Min.
:
4
7C342-30
Max.
Min.
5
7C342-35
Max.
Min.
7
9
Unit
ns
tro
I/O Input Pad and Buffer Delay
4
6
6
9
ns
tEXP
Expander Array Delay
.10
12
14
20
ns
tLAD
Logic Array Data Delay
10
12
14
16
ns
tLAC
Logic Array Control Delay
5
10
12
13
ns
tOD
Output Buffer and Pad Delay
3
5
5
6
ns
tzx
Output Buffer Enable Delay[27]
5
10
11
13
ns
txz
Output Buffer Disable Delay
5
10
11
13
ns
tRSU
Register Set-Up Time Relative
to Clock Signal at Register
5
6
tRH
Register Hold Time Relative
to Clock Signal at Register
5
6
8
10
ns
8
10
ns
"
.'
f.
tLATCH
Flow Through Latch Delay
1
3
4
4
ns
tRD
Register Delay
1
2
2
ns
tCOMB
Transparent Mode Delay[28]
1
I .. 1
3
4
4
ns
tCH
Clock HIGH Time
tCL
Clock LOW Time
tIC
Asynchronous Clock Logic Delay
6
."
8
6
12.5
10
8
ns
12.5
10
ns
8
14
16
18
ns
0
2
2
3
ns
1
~
1
2
ns
3
5
6
7
ns
,3
5
6
7
ns
tICS
Synchronous Clock Delay
tpD
Feedback Delay
tpRE
Asynchronous Register Preset Time
tCLR
Asynchronous Register Clear Time
tpcw
Asynchronous Preset and
Clear Pulse Width
4
5
6
7
ns
tpCR
Asynchronous Preset and
Clear Recovery Time
4
5
6
7
ns
tpIA
Programmable Interconnect
Array Delay Time
....
13
i
_.
Shaded area contams prehmmary mformatlOn.
4-177
14
--
16
20
ns
I
In
C
...I
a..
CY7C342
CY7C342B
~
.
¥~PRESS
~ JF
SEMICONDUCTOR
Switching Waveforms
External Combinatorial
DEDICATED
I/OINPUT/
INPUT _ _ _ _ __
~
lpo,[7]~pD2'8' ) , . . . -_ _ _ _ _ _ __
COMBINATORIAL
OUTPUT
~
=1----------=4
COMBINATORIAL OR - - - - - - - - - - - •
tER[7]
REGISTERED OUTPUT _ _ _ _ _ _ _~---EA 1
t [7
HIG1-~~~~~t,.1~~ - - - - - - - - - - - - -
~,
-----------
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
C342-7
External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK[71
~
'--_"""':"'"_ _
tS1
SYNCHRONOUS
CLOCK------J
ASYNCHRONOUS
t
CLEAR/PRESETl71 _ _ _ _
OH
_ _ _+-_+-""
REGISTERED
OUTPUTS _ _ _ _ _ _---I~~
I~-~-------
tC02
----------~~
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK[111
---------------- ,
"""'-------C-342-a
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
~
_ _ _- tAS1
ASYNCHRONOUS
CLOCK INPUT _ _ _ _ __
ASYNCHRONOUS
tAOH
CLEAR/PRESET _ _ _ _ _ _ _+-_+-""
ASYNCHRONOUS REGISTERED
OUTPUTS _ _ _ _ _ _---1~v
I-f--------...
tAC02
----------l~~
COMBINATORIAL OUTPUT FROM
ASYNCHRONOUS REGISTERED
FEEDBACK - - - - - - - - . . . - - - - - - - - - - - . . . .
4-178
--------C3-42-9
.
CY7C342
CY7C342B
.~
--=-?
~~CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Internal Combinatorial
I
tlN-
*
INPUT PIN
14-
I+-
tlO
I/O PIN
tplA---
f4--
tEXP -
II
)K
EXPANDER
ARRAY DELAY
I+-
tLAC, tLAO -
U)
)K
LOGIC ARRAY
INPUT
C
..J
Q.
)K
LOGIC ARRAY
OUTPUT
C342-10
Internal Asynchronous
tR
C
~I:= 'AWH ~.
CLOCK PIN
tiN
CLOCK INTO
LOGIC ARRAY
~
1V
~
~~ffi~
LOGIC ARRAY
~~
LOGIC ARRAY
------
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
'AWL }
~
tiC
~
~
tRSU
'-
tRH
tR.O,tLATCH
/
""" _ _ _ _J
l
-+-
tFD
'-
/
"
%
,-----
'------01
-
~
tClR,tpRE
-
'P~
REGISTER OUTPUT
TO ANOTHER LAB
--+-
*=
.
tFO
-
J<,.....-----------C342-11
Internal Synchronous
I:::: ==1 r- ----j /
JT
~~
4
:E =*
tCH
SYSTEM CLOCK PIN _ _ _
SYSTEM CLOCK
AT REGISTER
=i
tICS
tiN
--~----~
DATAARRAY
FROM
LOGIC
,------
tCl
tRSU
"
/
~----~
tRH
,----
,
._
._
..
._
-_
--_
-_
-_
--_
-_
--_
-_
-_
......
_
__
__-_
__-_
C342-12
4-179
CY7C342
CY7C342B
~
~~PRESS
~, SEMICONDUCTOR
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
------1
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C342-13
Ordering Information
Speed
(ns)
25
30
35
Ordering Code
CY7C342-25HC/HI
15
20
25
Package lYpe
68-Pin Windowed Leaded Chip Carrier
CY7C342-25JC/JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C342 - 25 RC/RI
CY7C342- 30HC/HI
R68
H81
68-Pin Windowed Ceramic Pin Grid Array
68-Pin Windowed Leaded Chip Carrier
CY7C342- 3OJC/JI
J81
CY7C342- 30RC/RI
CY7C342-30HMB
R68
H81
68-Lead Plastic Leaded Chip Carrier
68-Pin Windowed Ceramic Pin Grid Array
CY7C342- 30RMB
CY7C342-30TMB
R68
T91
68-Pin Windowed Ceramic Pin Grid Array
68-Lead Windowed Cerquad Flatpack
CY7C342- 35HC/HI
H81
68-Pin Windowed Leaded Chip Carrier
CY7C342- 35JC/JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C342- 35 RC/RI
CY7C342-35HMB
CY7C342-35RMB
R68
68-Pin Windowed Ceramic Pin Grid Array
H81
R68
CY7C342-35TMB
T91
68-Pin Windowed Leaded Chip Carrier
68-Pin Windowed Ceramic Pin Grid Array
68-Lead Windowed Cerquad Flatpack
Speed
(os)
Package
Name
H81
68-Pin Windowed Leaded Chip Carrier
CY7C342B-15RC/RI
Package
Name
H81
J81
R68
CY7C342B-20HC/HI
H81
68-Pin Windowed Leaded Chip Carrier
CY7C342B-20JC/JI
J81
68-Lead Plastic Leaded Chip Carrier
CY7C342B- 20RC/RI
CY7C342B-20HMB
R68
H81
68-Pin Windowed Ceramic Pin Grid Array
68-Pin Windowed Leaded Chip Carrier
CY7C342B- 20RMB
R68
68-Pin Windowed Ceramic Pin Grid Array
CY7C342B- 20TMB
CY7C342B-25HMB
T91
R81
68-Lead Windowed Cerquad Flatpack
68-Pin Windowed Leaded Chip Carrier
CY7C342B-25RMB
CY7C342B- 25TMB
R68
T91
68-Pin Windowed Ceramic Pin Grid Array
68-Lead Windowed Cerquad Flatpack
Ordering Code
CY7C342B-15HC/HI
CY7C342B-15JC/JI
Package lYpe
68-Pin Windowed Leaded Chip Carrier
68-Lead Plastic Leaded Chip Carrier
68-Pin Windowed Ceramic Pin Grid Array
4-180
Operating
Range
Commercial/
Industrial
Commercial/
Industrial
Military
Commercial!
Industrial
Military
Operating
Range
Commercial!
Industrial
Commercial!
Industrial
Military
Military
CY7C342
CY7C342B
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIR
VIL
IIX
Ioz
IcC!
Parameter
Document #: 38-00119-E
4-181
Subgroups
tpDl
7, 8, 9, 10, 11 .
tpD2
7, 8, 9, 10, 11
tpD3
7, 8, 9, 10, 11
tcO!
7, 8, 9, 10, 11
tSI
7, 8, 9, 10, 11
tS2
7, 8, 9, 10, 11
tH
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tWL
7, 8, 9, 10, 11
tRO
7, 8, 9, 10, 11
tpo
7, 8, 9, 10, 11
tACO 1
7, 8, 9, 10, 11
tASI
7, 8, 9, 10, 11
tAR
7, 8, 9, 10, 11
tAWH
7, 8, 9, 10, 11
tAWL
7, 8, 9, 10, 11
I
en
C
..I
0..
CY7C343
CYPRESS
SEMICONDUCTOR
64-Macrocell MAX ®
EPLD
Features
Functional Description
• 64 MAX macrocells in 4 LABs
• 8 dedicated inputs, 24 bidirectional
I/O pins
• Programmable interconnect array
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
The CY7C343 is a high-performance,
high-density erasable programmable logic
device, available in 44-pin PLCC and
HLCC packages.
The CY7C343 contains 64 highly flexible
macrocells and 128 expander product
terms. These resources are divided into
four Logic Array Blocks (LABs) connected through the Programmable Inter-
connect Array (PIA). There are 8 input
pins, one of which doubles as a clock pin if
needed. The CY7C343 also has 28 I/O
pins, each connected to a macrocell (6 for
LABs A and C, and 8 for LABs B and D).
The remaining 36 macrocells are used for
embedded logic.
The CY7C343 is excellent for a wide range
of both synchronous and asynchronous
applications.
Logic Block Diagram
91NPUT
r-
n
11 INPUT
::::::=-
121NPUT
n
-:::::!
-:::::!
131NPUT ::::
LAB A
~
f--
I
MACROCELLS 7 - 16
LABB
I/O PINS
~
I
~ ~
SYSTEM CLOCK
7
::f-f-=f-f--
15
16
17
18
19
20
22
23
INPUT33
C1 INPUT 31
t-1/0 PINS
INPUT35
~ INPUT/ClK 34
A
...I\.
'If
--v
~
_i=
_i=
-~
-~
-'-
'r-
P
~>
=~
'If
'''''''''nt'I='
~
I
A
~
:;;;~
7
I
~~
~;;;;;
~;::
~i=
v
~C
MACROCELLS 25 - 32
,.A--'\r-
-,.I
(3,14,25,36)
(10, 21, 32, 43)
C>C>-
I/O PINS
LABC
---1\
~
44
42
41
40
39
38
37
~
~
r-r--
-,....
-;::
-~
JI
-,.I
.II--
LABD
30
29
28
27
26
24
1/0 PINS
MACROCELLS 39 - 48
Vee
GND
C343-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
Maximum Standby
Current (rnA)
Commercial
7C343-20
7C343-25
7C343-30
7C343-35
20
135
25
135
30
135
135
35
225
225
225
Industrial
225
225
225
225
Commercial
125
125
125
125
200
200
200
200
200
200
Military
Military
Industrial
200
MAX@ and MA_X + PLUS@ are registered trademarks of .AJtera Corporation.
4-182
.~
IF SEMICONDUCTOR
-=-
CY7C343
_'i6CYPRESS
HLCC
Top View
Pin Configuration
~~~J~~~~§~~~
I/O
I/O
I/O
I/O
INPUT
GND
INPUT
INPUT
INPUT
Vee
I/O
I/O
Vee
0
INPUT
a
INPUT/elK
INPUT
GND
7C343
31
INPUT
I/O
I/O
I/O
I/O
In
C
...I
a..
C343-2
Maximum Ratings
DC Input Voltagel 1] ..................... -3.0V to +7.0V
DC Program Voltage ............................. 13.5V
Static Discharge Voltage ........................ > 1100V
(per MIL-STD-883, method 3015)
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied .......................... 0 ° C to + 70 ° C
Maximum Junction Temperature
(Under Bias) ................................... 150°C
Supply Voltage to Ground Potential. . . . . .. - 2.0V to + 7.0V
Maximum Power Dissipation ................... 2500 m W
DC Vee or GND Current ....................... 500 rnA
DC Output Current, per Pin . . . . . . . . .. - 25 rnA to + 25 rnA
Operating Range
Range
Commercial
Industrial
Military
Ambient
Temperature
O°C to +70°C
Vee
5V±5%
- 40°C to +85°C
5V ±10%
- 55°C to + 125°C (Case)
5V ±1O%
Electrical Characteristics Over the Operating Rangel 2]
VOH
Parameter
Description
Output HIGH Voltage
VOL
VIH
Input HIGH Level
Output LOW Voltage
VIL
Ilx
Input LOW Level
Ioz
Output Leakage Current
los
Input Current
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8 rnA
Vee
GND~VIN~Vee
Vo = VeeorGND
Output Short Circuit Current Vee = Max., V OUT
Power Supply Current
(Standby)
VI = Vee or GND
(No Load)
Iee2
Power Supply Currentl)J
tR
Recommended Input Rise
Time
tF
Recommended Input Fall
Time
Ieel
= O.5v[3, 4]
Min.
2.4
Max.
0.45
V
2.2
V
- 0.3
Vee+ O.3
0.8
- 10
+10
f-lA
- 40
+40
- 90
f-lA
rnA
rnA
- 30
Unit
V
V
Commercial
125
Military/lndustrial
200
rnA
VI = VeeorGND (No Load) Commercial
f = 1.0 MHz[4, 5]
Military/Industrial
135
225
100
rnA
rnA
100
ns
Notes:
1. Minimum DC input is -0.3Y. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns.
2. Typical values are for TA = 25 0 C and Vee = 5Y.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = 0.5V has
4.
5.
4-183
ns
been chosen to avoid test problems caused by tester ground degradation.
Guaranteed but not 100% tested.
Measured with device programmed as a 16-bit counter in each LAB.
This parameter is tested periodically by sampling production material.
.~
=n · iii
CYPRESS
CY7C343
- , SEMICONDUCTOR
Capacitance[6]
Description
Parameter
Test Conditions
Input Capacitance
CIN
VIN = 2V, f = 1.0 MHz
Max.
Unit
10
pF
Output Capacitance
10
V OUT = 2.0V, f = 1.0 MHz
pF
COUT
Notes:
6. Part (a) in AC Test Load and Waveforms is used for all parameters exforms. All external timing parameters are measured referenced to except tER and txz, which is used for part (b) in AC Test Load and Waveternal pins of the device.
AC Test Loads and Waveforms[6]
R1464Q
R1464Q
OUTP~~31
OUTPUT
5V31
SO pF
R2
I _
SpF
2S0Q
INCLUDING
JIG AND
SCOPE
-
-
GND
R2
2S0Q
INCLUDING _
JIG AND SCOPE
(a)
Equivalent to:
I
ALL INPUT PULSES
3.0V ----...Lo!~----s...
_
C343-3
C343-4
(b)
THEVENIN EQUIVALENT (commercial/military)
163Q
OUTPUT 00----'\;.'."
....__---00 1.7SV
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect
limitations by routing only the signals needed by each logic array
block. The inputs to the PIA are the outputs of every macrocell
within the device and the I/O pin feedback of every pin on the
device.
Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This
eliminates undesired skews among logic signals, which may cause
glitches in internal or external logic. The fixed delay, regardless of
programmable interconnect array configuration, simplifies design
by ensuring that internal signal skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing
objectives.
Timing Delays
Timing delays within the CY7C343 may be easily determined using
MAX +PLUS® software or by the model shown in Figure 1. The
CY7C343 has fixed internal delays, allowing the user to determine
the worst case timing delays for any design. For complete timing information, the MAX + PLUS software provides a timing simulator.
For proper operation, input and output pins must be constrained to
the range GND ~ (VIN or VOUT) ~ V co Unused inputs must always be tied to an appropriate logic level (either Vcc or GND).
Each set of V cc and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2
!IF must be connected between V cc and GND. For the most effective decoupling, each V cc pin should be separately decoupled to
GND, directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types.
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay
tEXP to the overall delay. Similarly, thereis an additional tpIA delay
for an input from an I/O pin when compared to a signal from a
straight input pin.
When calculating synchronous frequencies, use tSI if all inputs are
on the input pins. tsz should be used if data is applied at an I/O pin.
Iftsz is greater than tCOl, 1/tsz becomes the limiting frequency in
the data path mode unless 1/(tWH + tWL) is less than 1/tsz.
Design Recommendations
When expander logic is used in the data path, add the appropriate
maximum expander delay, tEXP to tSI' Determine which of 1/(tWH
+ tWL), 1/tCOl, or 1/(tEXP + tSI) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for
the synchronous configuration.
Operation of the devices described herein with conditions above
those listed under'~bsoluteMaximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this data sheet is not
implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability.The CY7C343
contains circuitry to protect device pins from high static voltages or
electric fields; however, normal precautions should be taken to
avoid applying any voltage higher than maximum rated voltages.
When calculating external asynchronous frequencies, use tASI ifall
inputs are on dedicated input pins. If any data is applied to an I/O
pin, tASz must be used as the required set-up time. If (tASZ + tAH)
is greater than tACOI, 1/(tASZ + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAH) is less than
1/(tASZ + tAH).
When expander logic is used in the data path, add the appropriate
maximum expander delay, tEXP to tASI' Determine which of
1/(tAWH + tAWL), 1/tACOI, or l!(tEXP + tASI) is the lowest fre-
4-184
N~
_'=
-0'
CY7C343
•
CYPRFSS
SEMICONDUCTOR
quency. The lowest ofthese frequencies is the maximum data path
frequency for the asynchronous configuration.
The parameter tOH indicates the system compatibility of this dev.ice when. dri~ing other synchronous logic with positive input hold
tImes, WhICh IS controlled by the same synchronous clock. If tOH is
greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst -case
environmental and supply voltage conditions.
The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C343.
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or asynchronous),
then the devices are guaranteed to function properly under worstcase environmental and supply voltage conditions, provided the
~lock signal source is the same. This also applies if expander logic
IS used in the clock signal path of the driving device, but not for the
driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tE)(p), causing
the. output data from the preceding device to change prior to the
arnval of the clock signal at the following device's register.
II
tn
C
...I
Q.
REGISTER
LOGIC ARRAY
DELAY
1---1-+-+-1--... CONTROL
tLAC
INPUT
INPUT
DELAY
tiN
I--'><.!::W'--~
OUTPUT
DELAY
INPUT/
OUTPUT
too
txz
tzx
LOGIC ARRAY
DELAY
tLAD
SYSTEM CLOCK DELAY tiCS
CLOCK
DELAY
tiC
C343-5
Figure 1. CY7C343 Internal Timing Model
4-185
g: ;~PRESS
CY7C343
- , SEMICONDUCTOR
External Synchronous Switching Characteristics[6] Over Operating Range
Parameter
tpDl
tpD2
tPD3
tpD4
tEA
tER
tcO!
tc02
tSI
tS2
tH
tWH
tWL
tRW
tRR
tRO
tpR
tpo
Description
CY7C343-20
CY7C343-25
CY7C343-30
CY7C343-35
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
25
30
35
ns
25
30
35
Dedicated Input to Com- Com'l& Ind
binatorial Output
Mil
Delay[7]
20
I/O Input to Combinato- Com'l& Ind
rial Output Delay[8]
Mil
Dedicated Input to Com- Com'l &Ind
binatorial Output DelaT'
Mil
with Expander Delay[9
32
39
44
53
ns
44
30
39
37
44
53
55
ns
37
44
55
I/O Input to Combinato- Com'l& Ind
rial Output Dela~ with
Mil
Expander Delay ~, 10]
42
Input to Output Enable
Delay[4,7]
Com'l &Ind
20
Input to Output Disable
Delay[4,7]
Com'I&Ind
Mil
20
Mil
Synchronous Clock Input Com'l &Ind
to Output Delay
Mil
12
Synchronous Clock to
Local Feedback to
Combinatorial
Outpud4, 11]
25
Com'I&Ind
Mil
Dedicated Input or Feed- Com'l& Ind
back Set-Up Time to
Synchronous Clock
Mil
Input[7]
12
I/O Input Set-Up Time
to Synchronous Clock
Inpud 7,12]
Com'l &Ind
24
Input Hold Time from
Synchronous Clock
Input[7]
Com'l& Ind
Mil
0
Mil
Synchronous Clock Input Com'l& Ind
HIGH Time
Mil
6
Synchronous Clock
Input LOW Time
Com'I&Ind
6
Asynchronous Clear
Width[4,7]
Com'I&Ind
Asynchronous Clear Recovery Timel 4, 7]
Com'l& Ind
Asynchronous Clear to
Registered Output
Delay[7]
Com'l& Ind
Mil
20
Mil
Com'l& Ind
20
Mil
4-186
73
58
73
25
30
35
25
30
35
25
30
35
25
30
35
14
16
20
14
16
20
30
35
42
30
35
42
20
25
15
20
25
30
35
42
30
35
42
0
0
0
0
0
0
8
10
12.5
8
10
12.5
8
10
12.5
8
10
12.5
25
30
35
25
30
35
25
30
35
25
30
35
20
20
58
15
Mil
Asynchronous Preset Re- Com'l& Ind
covery Timel4, 7]
Mil
Asynchronous Preset to
Registered Output
Delay[7]
20
Mil
51
51
ns
ns
ns
35
35
35
35
ns
ns
30
30
ns
ns
30
30
ns
ns
25
25
ns
ns
25
25
ns
ns
ns
25
30
35
25
30
35
ns
9
~~
CY7C343
'jE CYPRESS
~, SEMlCONDUcrOR
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
Parameter
Description
tCF
Synchronous Clock to
Local Feedback
Inputf4, 13]
tp
External Synchronous
Clock Period
(l/fMAX3)[4]
Com'l &Ind
fMAX2
Internal Local Feedback
Maximum Frequency,
lesser of (l/~t~5 + tCF»
or (l/tCOl)[' ]
Com'l& Ind
fMAX4
tOH
tpw
6]
3
3
Com'l& Ind
Output Data Stable
Time from S~chronous
Clock Input[ , 18]
Mil
Com'l& Ind
Com'l& Ind
3
25
16
20
25
41.6
34
27
22.2
34
27
22.2
66.7
55
43
33
55
43
33
62.5
50
40
62.5
50
40
83.3
83.3
3
20
Mil
Notes:
7. This specification is a measure of the delay from input signal applied
to a dedicated input (44-pin PLCC input pin 9,11,12,13,31,33,34, or
35) to combinatorial output on any output pin. This delay assumes no
expander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates
that the signal (data, asynchronous clock, asynchronous clear, and/or
asynchronous preset) is applied to a dedicated input only and no signal
path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin, an additional delay equal to
tPIA should be added to the comparable delay for a dedicated input.
If expanders are used, add the maximum expander delay tE)(P to the
overall delay for the comparable delay without expanders.
8. This specification is a measure of the delay from input signal applied
to an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
9. This specification is a measure of the delay from an input signal applied
to a dedicated input (44-pin PLCC input pin 9,11,12,13,31,33,34, or
35) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the
worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
10. This specification is a measure of the delay from an input signal app lied
to an I/O macrocell pin to any output. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from synchronous register
clock to internal feedback of the register output signal to the input of
the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all
12.
13.
14.
15.
16.
17.
18.
4-187
Max.
Unit
5
ns
5
20
Mil
Mil
Max.
3
3
Mil
Com'l& Ind
Max.
16
12
Mil
Maximum Register
Toggle Frequenrr
(lI(twL +tWH»[ , 17]
Asynchronous Preset
Width[4,7]
CY7C343-35
Min.
Mil
Com'l& Ind
(litem) 4,
CY7C343-30
Min.
Mil
External Maximum Frequency
(l/(tCOl + tSl»[4, 14]
Data Path Maximum Frequency, least of lI(tWL +
tWH), lIf.ts } + tH), or
CY7C343-25
Min.
Max.
Com'l &Ind
fMAXI
fMAX3
CY7C343-20
Min.
62.5
50
40
62.5
50
40
3
3
3
3
3
3
25
30
35
25
30
35
ns
MHz
MHz
a
tn
Q
..J
0..
MHz
MHz
ns
ns
feedback is within the same LAB. This parameter is tested periodically
by sampling production material.
If data is applied to an I/O input for capture by a macrocell register, the
I/O pin set-up time minimums should be observed. These parameters
are tS2 for synchronous operation and tAS2 for asynchronous operation.
This specification is a measure of the delay associated with the internal
register feedback path. This is the delay from synchronous clock to
LAB logic array input. This delay plus the register set-up time, tS1, is
the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB.
This parameter is tested periodically by sampling production material.
This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs.
This specification indicates the guaranteed maximum frequency at
which a state machine, with internal-only feedback, can operate. If register output states must also control external points, this frequency can
still be observed as long as this frequency is less than l/teOl. All feedback is assumed to be local, originating within the same LAB.
This frequency indicates the maximum frequency at which the device
may operate in data path mode. This delay assumes data input signals
are applied to dedicated inputs and no expander logic is used.
This specification indicates the guaranteed maximum frequency, in
synchronous mode, at which an individual output or buried register can
be cycled.
This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on
the output pin.
.~
=::::
==I::
,
~~NDUcroR
CY7C343
External Asynchronous Switching Characteristics Over Operating Rangel6]
CY7C343-20
Parameter
Description
Asynchronous Clock In- Com'l& Ind
put to Output Delay[7]
Mil
Asynchronous Clock In- Com'I&Ind
put to Local Feedback to
Combinatorial OutMil
putl l9 ]
Min.
Dedicated Input or Feed- Com'l& Ind
back Set-Up Time to
Asy.nchronous Clock In- Mil
put[7]
4
I/O Input Set-Up Time
to Astnchronous Clock
Input 7]
Com'l & In:d
15
tAH
Input Hold Time from
ASY.I.!chronous Clock Input[7]
Com'l& Ind
tAWH
Asynchronous Clock Input HIGH Time[7]
tAWL
Asynchronous Clock Input LOW Timel 7, 20]
tACF
Asynchronous Clock to
Local Feedback Input[4,
21]
Com'l& Ind
Mil
Com'l &Ind
Mil
Com'l& Ind
tAP
External Asynchronous
Clock Period
(l/fMAXA4) [4]
Com'l& Ind
External Maximum Frequency in Asynchronous
Mode
l!(tACOl + tAS1)[4,22]
Com'l& Ind
tACOl
tAC02
tASl
tAS2
fMAXA1
fMAXA2
Maximum Internal
Frequen-
As~nchronous
CY7C343-25
CY7C343-30
CY7C343-35
Min.
Min.
Min.
32
6
8
5
6
8
25
30
25
30
5
6
8
10
6
8
10
9
11
11
9
9
14
14
11
11
16
16
14
14
7
13
15
41.6
Mil
Data Path Maximum
Frequency in Asynchronous Model 4, 24]
Com'l& Ind
fMAXA4
Maximum Asynchronous
Register Toggle Fre~uency l!(tAWH + tAwd 4,25]
Output Data Stable Time
from Asynchronous
Clock Input[4, 26]
62.5
50
Mil
Com'I&Ind
62.5
Mil
Com'l& Ind
15
Mil
Notes:
19. This specification is a measl,lre of the delay from an asynchronous register clock input to internal feedback of the register output signal to the
input of the LAB logic array and then to a combinatorial output. This
delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to a
dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge triggered clock at the
register. For negative edge triggering, the tAWH and tAWL parameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL·
Unit
ns
ns
ns
ns
ns
ns
ns
22
18
15
16
Max.
35
35
55
55
20
Mil
fMAXA3
46
5
Mil
Com'l& Ind
Max.
30
30
46
20
Mil
Mil
Max.
25
25
40
40
Mil
cy'l,23]
tAOH
Max.
20
ns
22
18
20
25
30
20
25
30
33
27
23
33
27
23
50
40
33
50
40
33
40
33
28
40
33
28
50
40
33
50
40
33
15
15
15
15
15
15
ns
MHz
MHz
MHz
MHz
ns
21. This specification is a measure ofthe delay associated with the internal
register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tASl, is the
minimum internal period for an internal asynchronously clocked state
machine configuration. This delay is for feedback within the same
LAB, assumes no expander logic in the clock path, and assumes that the
clock input signal is applied to a dedicated input pin. This parameter
is tested periodically by sampling production material.
22. This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no
expander logic is employed in the clock signal path or data path.
4-188
.g:~
====
F=
CY7C343
CYPRESS
SEMICONDUCTOR
Internal Switching Characteristics Over Operating Rangel!]
Parameter
tIN
tIO
tEXP
tLAD
tLAC
taD
tzx
txz
tRSU
tRH
tLATCH
tRD
tCOMB
tCH
tCL
tIC
tICS
tpD
tpRE
tCLR
tpcw
tpCR
tPIA
Description
Dedicated Input Pad and Com'l &Ind
Buffer Delay
Mil
I/O Input Pad and Buffer Com'l &Ind
Delay
Mil
Expander Array Delay
Com'l &Ind
Mil
Logic Array Data Delay Com'l &Ind
Mil
Logic Array Control
Com'l &Ind
Delay
Mil
Output Buffer and Pad
Com'l &Ind
Delay
Mil
Output Buffer Enable
Com'l & Ind
Delay[27]
Mil
Output Buffer Disable
Com'l & Ind
Delay
Mil
Register Set-Up Time
Com'l &Ind
Relative to Clock Signal
Mil
at Register
Register Hold Time Relative to Clock Signal at
Register
Flow-Through Latch
Delay
Com'I&Ind
CY7C343-20
Min. Max.
4
4
10
10
8
4
8
8
4
4
Mil
Com'l& Ind
Mil
Register Delay
Com'l& Ind
Mil
Com'l & Ind
Trans~arent Mode
Delay 28]
Mil
Clock HIGH Time
Com'l& Ind
Mil
Clock LOW Time
Com'l & Ind
Mil
Asynchronous Clock
Com'l& Ind
Logic Delay
Mil
Synchronous Clock
Com'1& Ind
Delay
Mil
Feedback Delay
Com'l& Ind
Mil
Com'I&Ind
Asynchronous Register
Preset Time
Mil
Asynchronous Register
Com'l& Ind
Clear Time
Mil
Asynchronous Preset and Com'I&Ind
Clear Pulse Width
Mil
Asynchronous Preset and Com'l& Ind
Clear Recovery Time
Mil
Programmable Intercon- Com'l& Ind
nect Array Delay Time
Mil
CY7C343-25
Min. Max.
5
5
5
5
12
12
12
12
10
10
5
5
10
10
10
10
6
8
10
6
8
12
6
8
12
2
14
14
2
2
1
1
5
5
5
5
12
2
1
4
4
4
12
4-189
16
16
2
2
1
1
6
6
6
6
14
14
16
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
C
..J
Q.
ns
ns
18
18
3
3
2
2
7
7
7
7
•
In
ns
ns
7
7
7
7
6
6
6
6
5
5
5
5
4
12.5
12.5
12.5
12.5
10
10
10
10
8
8
8
8
Unit
ns
ns
4
4
2
2
4
4
4
4
2
2
4
4
3
3
1
1
3
3
1
6
CY7C343-35
Min. Max.
9
9
7
7
20
20
16
16
13
13
6
6
13
13
13
13
10
6
2
6
CY7C343-30
Min. Max.
7
7
5
5
14
14
14
14
12
12
5
5
11
11
11
11
8
ns
~
;-'~PRF5S
~, ~ICONDUcrOR
CY7C343
Switching Waveforms
External Combinatorial·
DEDICATED
I/OINPUT/
INPUT _ _ _ _ __
~
tPD,ul/tpD2'"
COMBINATORIAL
OUTPUT
~.-_ _ _ _ _ _ _ __
=1----------=4
COMBINATORIAL OR - - - - - - - j.-- - -tER(7)
-REGISTERED OUTPUT _ _ _ _ _ _ _ _ _ _ _
j.--
tEA[7)
•
HIG~-~~~~~t,-~¥~ - - - - - - - - - - - External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK(7)
=i
-------------
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
C343-7
_ _-:-__
tS1
SYNCHRONOUS
CLOCK------'
ASYNCHRONOUS
t
CLEAR/PRESET(7) _ _ _ _O_H_-t__I - - I - "
REGISTERED
OUTPUTS - - - - - - . - o 1 ! ' - - v
tC02
-------i~~
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK(11)
------------------
Notes:
23. This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. This parameter is determined by the lesser of
(l/tACF + tASl» or (l/(tAWH +tAWL». If register output states must
also control external points, this frequency can still be observed as long
as this frequency is less than 1/tACOl.
24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification
is determined by the least of l/(tAWH + tAWL), l/(tASl + tAH) or
l/tACOl. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
""--------C-343-6
25. This specification indicates the guaranteed maximum frequency at
which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated
input pin.
26. This parameter indicates the minimum time that the previous register
output data is maintained on the output after an asynchronous register
clock input.
27. Sample tested only for an output change of 500 mY.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-190
=:~
'j; CYPRESS
,
CY7C343
SEMICONDUCTOR
4
Switching Waveforms (continued)
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK[71
_ _-:--_ _
tAS1
ASYNCHRONOUS
CLOCK INPUT _ _ _ _ __
ASYNCHRONOUS
~OH
CLEAR/PRESEWI _ _ _ _ _ _+-+-_+-'"
a
ASYNCHRONOUS REGISTERED
OUTPUTS _ _ _ _ _~~~v
en
C
------I*~
1.....- - - - - tAC02
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED FEEDBACK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
...J
D.
......._ _ _ _ _ __
C343-10
Internal Combinatorial
I
*
INPUT PIN
tlN-
~tpIA-
tlO
I/O PIN
I--
-tEXP-
)(
EXPANDER
ARRAY DELAY
I+--
tLAC, tLAD -
)K
LOGIC ARRAY
INPUT
)K
LOGIC ARRAY
OUTPUT
Internal Asynchronous
tR
~I:=
CLOCK PIN
tiN
CLOCK INTO
LOGIC ARRAY
tAWH
1v \ . . /
I+-
CLOCK FROM
LOGIC ARRAY
DATAARRAY
FROM _ _ _ _ __
LOGIC
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
I,l"'tC ~~ }_
~
tlC;l(,
,,'-_ _ _ _J
\..
/
" .
tRSU
tRD.tLATCH
tRH"*
-+-
tFD
t
%
C343-8
,,'------
-----
-
-
tClR,tpRE
-+
tFD
t=
-
___________________
tP_IA_]( _ _ _ _ _ _ _ _ _ _ _ __
REGISTER OUTPUT
TO ANOTHER LAB
C343-9
4-191
~
~~PRF.SS
.
~
iF
CY7C343
SEMICONDUCTOR
Switching Waveforms (continued)
Internal Synchronous
1:=
,.,r
tCH
SYSTEM CLOCK PIN _ _ _
SYSTEM
CLOCK
AT REGISTER
=£
~r~~
t'Nlt'CS
,
1
--J
/
~
, ' "
--~----~
DATA FROM
LOGIC ARRAY
tCl
tRSU
tRH
/
~------'
"'-----"'----
----------------------_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
C343-12
Output Mode
CLOCK FROM
LOGIC ARRAY _ _ _ _ _ _1
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C343-11
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
20
CY7C343-20HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
CommerciallIndustrial
CY7C343-20JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343-25HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
CY7C343-25JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343- 25HMB
H67
44-Pin Windowed Leaded Chip Carrier
Military
CY7C343-30HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
Commercial/Industrial
CY7C343-30JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
25
30
35
CommerciallIndustrial
CY7C343 - 30HMB
H67
44-Pin Windowed Leaded Chip Carrier
Military
CY7C343-35HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
CommerciallIndustrial
CY7C343-35JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343-35HMB
H67
44-Pin Windowed Leaded Chip Carrier
4-192
Military
s; :;::z
~~
CY7C343
CYPRESS
~ iF SEMICONDUcrOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIR
VIL
IIX
Ioz
ICCl
•
tn
Q
...J
Switching Characteristics
Parameters
Ill.
Subgroups
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tpD3
7,8,9, 10, 11
tCOl
7, 8, 9, 10, 11
ts
7,8,9, 10, 11
tH
7, 8, 9, 10, 11
tACOl
7, 8, 9, 10, 11
tAC02
7, 8, 9, 10, 11
tAS
7,8,9, 10, 11
tAB
Document #: 38-00128-E
tpDl
tpD2
4-193
CY7C344
CYPRESS
SEMICONDUCTOR
32-Macrocell MAX® EPLD
Features
Functional Description
• High-performance, high-density replacement for TTL, 74HC, and custom
logic
• 32 macrocells, 64 expander product
terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 2S-pin 300-mil DIP, cerDIP or 28-pin
HLCC, PLCC package
Available in a 28-pin 300-mil DIP or windowed J-Ieaded ceramic chip carrier
(HLCC) , the CY7C344 represents the
densest EPLD of this size. Eight dedicated
inputs and 16 bidirectional I/O pins communicate to one logic array block. In the
CY7C344 LAB there are 32 macrocells
and 64 expander product terms. When an
I/O macrocell is used as an input, two expanders are used to create an input path.
Even if all of the I/O pins are driven by macrocell registers, there are still 16 "buried"
Logic Block Diagram[l]
registers av:ailable. All inputs, macrocells,
and I/O pins are interconnected within the
LAB.
The speed and density of the CY7C344
makes it a natural for all types of applications. With just this one device, the designer can implement complex state machines,
registered logic, and combinatorial "glue"
logic, without using multiple chips. Thisarchitectural flexibility allows the CY7C344
to replacemultichip TTL solutions, whether they. are synchronous, asynchronous,
combinatorial, or all three.
Pin Configurations
HLCC
15(22)
INPUT
INPUT
15(23)
INPUT
INPUT/ClK
27(6)
INPUT
INPUT
13(20)
INPUT
INPUT
14(21)
28(7)
Top View
1(8)
ggg9~gg
2(9)
MACROCEll2
I/O
3(10)
MACROCEll4
I/O
4(11)
MACROCEll6
I/O
5(12)
MACROCEll8
I/O
6(13)
MACROCEll 10
I/O
9(16)
MACROCEll 12
I/O
10(17)
MACROCEll 14
I/O
11(18)
MACROCEll 16
I/O
12(19)
MACROCEll 18
I/O
17(24)
MACROCEll20
I/O
18(25)
MACROCEll 22
I/O
19(26)
MACROCEll24
I/O
20(27)
MACROCEll26
I/O
23(2)
MACROCEll28
I/O
24(3)
MACROCEll 30
I/O
25(4)
MACROCEll32
I/O
26(5)
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
I/O
INPUT
INPUT
INPUT
INPUT/ClK
I/O
I/O
gg~~ggg
C344-2
CerDIP
Top View
INPUT
INPUT/ClK
I/O
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
Vee
Vee
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
9
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
C344-3
Selection Guide
7C344-20
7C344-25
7C344-35
20
200
25
200
35
200
220
Maximum Access Time (ns)
Maximum 03erating
Current (rnA
Maximum Standby
Current (rnA)
Commercial
220
Military
Industrial
220
220
Commercial
Military
150
150
170
Industrial
170
170
Note:
1. Figures in 0 are for J-leaded packages.
MAX and MAX + PLUS are registered trademarks of Altera Corporation.
4-194
150
170
~:~
.
'jE
CY7C344
CYPRESS
_ , SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied .......................... O°C to +70°C
Maximum Junction Temperature
(Under Bias) ................................... 150°C
Supply Voltage to Ground Potential ....... - 2.0V to +7.0V
Maximum Power Dissipation ................... 1500 mW
DC Vee or GND Current ....................... 500 rnA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............. >2001V
DC Output Current, per Pin . . . . . . . . .. - 25 rnA to + 25 rnA
DC Input Voltagef2] .................... - 3.0V to +7.0V
DC Program Voltage ........................... -13.5V
Operating Range
Ambient
Temperature
O°C to +70°C
Range
Commercial
Industrial
Military
Vee
5V±5%
- 40°C to +85°C
5V ±10%
- 55°C to +125°C (Case)
5V ±1O%
Electrical Characteristics Over the Operating Rangef3]
Parameter
IIX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Current
Ioz
Output Leakage Current
los
Output Short
Circuit Current
IeCI
Power Supply
Current (Standby)
VI = Vee or GND (No Load)
f = 1.0 MHz[4, 6]
Iee2
Power Supply Current
VI = Vee or GND (No Load)
f = 1.0 MHz[4, 6]
tR
tp
Recommended Input Rise Time
VOH
VOL
VIH
VIL
Test Conditions
Vee
= Min., IOH = -
Vee
= Min., IOL = 8 rnA
Min.
2.4
Max.
- 0.3
Vee+ O.3
0.8
Unit
V
V
V
V
-10
+10
!-LA
- 40
+40
- 90
rnA
Commercial
150
rnA
Military/lndustrial
Commercial
Military/lndustrial
170
rnA
200
220
rnA
100
100
ns
4.0 rnA
0.45
2.2
GND ~ VIN ~ Vee
Va = Vee or GND
Vee = Max., VOUT = 0.5V[4,5]
- 30
Recommended Input Fall Time
!-LA
rnA
ns
Capacitance
CIN
Parameter
Description
Input Capacitance
COUT
Output Capacitance
1
AC Test Loads and Waveforms[7]
OUTP~~: Ii'
50 pF
Equivalent to:
:f1R1
SpF
I
Unit
pF
pF
3.0V ----:::lot"'::"::~---~
R2
2S0n.
_
-
(a)
Max.
10
10
ALL INPUT PULSES
464n.
OUTPUT
R2
2S0n.
INCLUDING _
JIG AND SCOPE
5V
Test Conditions
= 2V, f = 1.0 MHz
VOUT = 2.0V, f = 1.0 MHz
VIN
GND
tp
(b)
C344-4
C344-5
THEVENIN EQUIVALENT (commerCial/military)
163n.
OUTPUT ().o---Al"'\I\~_--oO 1.7SV
C344-6
Notes:
2. Minimum DC input is -0.3\1. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
3. Typical values areforTA = 2SoC and Vee = S\1.
4. Guaranteed but not 100% tested.
S. Not more than one output should be tested at a time. Duration ofthe
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
6.
7.
4-195
Measured with device programmed as a 16-bit counter.
Part (a) in AC Test Load and Waveforms is used for all parameters except tER and txz, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
a
en
Q
..J
D.
&
_~PRFSS
~,
CY7C344
SEMICONDUCTOR
Timing Delays
Timing delays within the CY7C344 may be easily determined using
MAX +PLUS® software or by the model shown in Figure 1. The
CY7C344 has fixed internal delays, allowing the user to determine'
the worst case timing delays for any design. For complete timing information, the MAX + PLUS software provides a timing simulator.
Design Recommendations
Operation of the devices described herein with ~onditions above
those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this datasheet
is not implied. Exposure to absolute maximum ratings conditions
for extended periods of time may affect device reliability. The
CY7C344 contains circuitry to protect device pins from high-static
voltages or electric fields; however, normal precautions should be
taken to avoid applying any voltage higher than maximum rated
voltages.
When expander logic is used in the data path, add the appropriate
maximum expander delay, tExP to tS1' Determine which of 1/(tWH
+ twd, 1/tC01, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use tAS1 ifall
inputsiare on dedicated input pins. If any data is applied to an I/O'
pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH)
is greater than tAt01, 1/(tAS2 + tAH) becomes the limiting frequency in the data-path mode unless 1/(tAWH + tAwd is less than
1/(tAS2 + tAH).
When expander logic is used in the data path, add the appropriate
maximum expander delay, tEXP to tAS1' Determine which of
1/(tAwH + tAWL), 1/tAeo1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest ofthese frequencies is the maximum data-path
frequency for the asynchronous configuration.
The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold
times, which is controlled by the same synchronous clock. If tOH is
greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case
environmental and supply voltage conditions.
For proper operation, input and output pins must be constrained to
the range GND ~ (VIN or V OUT) ~ V CO Unused inputs must always be tied to an appropriate logic level (either Vee or GND).
Each set of V ee and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2
JA.F must be connected between Vee and GND. For the most effective decoupling, each Vee pin should be separately decoupled.
The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344.
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay
tExP to the overall delay.
When calculating synchronous frequencies, use tS1 if all inputs are
on the input pins. tS2 should be used if data is applied at an I/Opin.
If tS2 is greater than teOh 1/tS2 becomes the limiting frequency in
the data-path mode unless 1/(tWH + twd is less than 1/tS2'
In general, if tAOH is greater than the minimum required input
hold,time of the subsequent logic (synchronous or asynchronous),
then the devices are guaranteed to function properly under worstcase environmental and supply voltage conditions, provided the
clock signal source is the same. This also applies if expander logic
is used in the clock signal path of the driving device, but not for the
driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP), causing
the output data from the preceding device to change prior to the
arrival of the clock signal at the following device's register.
REGISTER
LOGIC ARRAY
I---I-.......~I--~CONTROL DELAY
INPUT
tLAC
I---'.............,~
OUTPUT
DELAY
OUTPUT
INPUT
DELAY
tiN
taD
LOGIC ARRAY
DELAY
txz
tzx
tLAD
SYSTEM CLOCK DELAY tiCS
I/O
CLOCK
DELAY
tiC
C344-7
Figure 1. CY7C344 Timing Model
4-196
.
.~
_'liE
CY7C344
CYPRESS
- , SEMICONDUCTOR
External Synchronous Switching Characteristics[7] Over Operating Range
Parameter
Description
tpDl
Dedicated InRut to Combinatorial
Output Delay[8]
tPD2
I/O In~ut to Combinatorial Output
Delay]
tPD3
tpD4
tEA
Dedicated Input to Combinatorial
Output Delay with Expander Delay[lO]
CY7C344-20
CY7C344-25
CY7C344-35
Min.
Min.
Min.
Com'l &Ind
Max.
20
Mil
20
Com'l& Ind
30
Input to Output Enable Delay[4]
20
In
25
20
Com'l& Ind
Com'l& Ind
Synchronous Clock to Local Feedback to Com'l &Ind
Combinatorial Outpud4, 12]
Mil
15
22
29
Mil
Com'l & Ind
12
Com'l& Ind
Synchronous Clock Input HIGH Timd4] Com'l &Ind
0
ns
8
10
8
7
ns
8
Mil
Asynchronous Clear Width[4]
Com'l& Ind
tRR
Asynchronous Clear Recovery Timd4]
Com'l& Ind
20
10
25
Mil
ns
25
20
35
25
Mil
ns
25
20
Com'l& Ind
35
25
Mil
ns
25
Com'l & Ind
20
ns
25
Com'l & Ind
Mil
20
35
25
25
4-197
35
25
Mil
Asynchronous Preset Recovery Timd4]
ns
8
7
Mil
tpR
ns
21
0
tRW
ns
37
0
0
Mil
Synchronous Clock Input LOW Timd4] Com'l & Ind
20
15
15
tWH
Asynchronous Preset Width[4]
ns
29
Mil
Input Hold Time from Synchronous
Clock Inpud 7]
tpw
ns
35
15
tH
Asynchronous Clear to Registered
Output Delay[4]
ns
25
12
..J
35
25
tC02
•
C
55
25
Synchronous Clock Input to Output
Delay
tRO
ns
40
40
Com'l & Ind
tcO!
tWL
55
40
30
Dedicated Input or Feedback Set-Up
Time to Synchronous Clock Input
ns
40
Mil
Mil
ts
ns
35
25
I/O Input to Combinatorial Output Delay Com'l &Ind
with Expander Delay[4, 11]
Mil
Input to Output Disable Delay[4]
35
25
Mil
Unit
ns
25
Com'l & Ind
Max.
25
Mil
tER
Max.
ns
35
c..
~
~~PRESS
~, SEMICONDUCTOR
CY7C344
External Synchronous Switching Characteristics[7) Over Operating Range (continued)
Parameter
tpo
Description
Asynchronous Preset to Registered
Output Delay[4)
tCF
Synchronous Clock to Local Feedback
Input[4, 13)
tp
External S~nchronous Clock Period
(lJfMAX3) 1I]
CY7C344-20
CY7C344-25
CY7C344-35
Min.
Min.
Min.
Com'l& Ind
Max.
20
4
External Maximum Frequency
(l/(tCOl + tSl»[4, 14]
. ',".,
14
Com'l& Ind
41.6
Mil
13
62.5
fMAX3
Data Path Maximum Frequency, least of Com'l& Ind
lJ(tWL + tWH), lJ(ts + tH), or (lJtcOl)[4, 16)
Mil
71.4
Maximum Register Toggle Frequency
lJ(tWL + tWH)[4, 17]
Com'l & Ind
71.4
Output Data Stable Time from
Synchronous Clock Input[4, 18)
Com'l & Ind
29.4
MHz
47.6
MHz
62.5
50.0
ns
3
3
Mil
MHz
62.5
62.5
Notes:
8. This parameter is the delay from an input signal applied to a dedicated
input pin to a combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to
an I/O macrocell pin to any output. This delay assumes no expander
terms are used to form the logic function.
10. This parameter is the delay associated with an input signal applied to
a dedicated input pin to combinatorial output on any output pin. This
delay assumes expander terms are used to form the logic function and
includes the worst-case expander logic delay for one pass through the
expander logic. This parameter is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to
an I/O macrocell pin to any output pin. This delay assumes expander
terms are used to form the logic function and includes the worst-case
expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.
12. This specification is a measure of the delay from synchronous register
clock input to internal feedback of the register output signal to a combinatorial output for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the
combinatorial output and the register is synchronously clocked. This
parameter is tested periodically by sampling production material.
MHz
24.3
45.4
62.5
3
20
33.3
45.4
Mil
ns
16
33.3
Maximum Frequency with Internal Only Com'I&Ind
Feedback (lJ(tcF + tS»[4, 15]
Mil
tOH
ns
7
16
Mil
fMAX2
fMAX4
35
7
Com'l& Ind
Unit
ns
25
Mil
Com'I&Ind
Max.
25
Mil
fMAXl
Max.
3
13. This specification is a measure of the delay associated with the internal
register feedback path. This delay plus the register set-up time, ts, is the
minimum internal period for an internal state machine configuration.
This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external only feedback can
operate.
15. This specification indicates the guaranteed maximum frequency at
which a state machine with internal-only feedback can operate. Ifregister output states must also control external points, this frequency can
still be observed as long as it is less than litem. This specification assumes no expander logic is used. This parameter is tested periodically
by sampling production material.
16. This frequency indicates the maximum frequency at which the device
may operate in data-path mode (dedicated input pin to output pin).
This assumes that no expander logic is used.
17. This specification indicates the guaranteed maximum frequency insynchronous mode, at which an individual output or buried register can be
cycled by a clock signal applied to either a dedicated input pin or an I/O
pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on
the output pin.
4-198
·
.~
_'1=
CY7C344
CYPRESS
- _ F SEMICONDUCTOR
External Asynchronous Switching Characteristics Over Operating Range[7]
CY7C344-20
Parameter
tACO 1
tAC02
tAS
tAH
Description
Min.
Asynchronous Clock Input to Output
Delay
Asynchronous Clock Input to Local
Feedback to Combinatorial Output[19]
Com'l &Ind
20
Com'l& Ind
Input Hold Time from Asynchronous
Clock Input
Com'l &Ind
30
9
9
11
Mil
Data Path Maximum Fre uency in
Asynchronous Modd4,24
fMAXA4
1
MaximumAsynchronousRe~isterThggle
Frequency l!(tAWH
tAOH
Com'l &Ind
+ tAWL) 4,25]
Output Data Stable Time from
Asynchronous Clock Inpud4, 26]
18
ns
15
ns
21
16
34.4
37
Mil
62.5
Mil
Com'l &Ind
15
MHz
28.5
MHz
33.3
15
15
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to
a combinatorial output for which·the registered output signal is used
as an input. Assumes no expanders are used in logic of combinatorial
output or the asynchronous clock input. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggered clock at the
register. For negative edge triggering, the tAWH and tAWL parameters
must be swapped. If a given input is used to clock multiple registers
with both positive and negative polarity, tAWH should be used for both
tAWH and tAWL.
21. This specification is a measure of the delay associated with the internal
register feedback path for an asynchronously clocked register. This
delay plus the asynchronous register set-up time, tAS, is the minimum
internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic in the asynchronous clock
path. This parameteris tested periodically by sampling production material.
22. This parameter indicates the guaranteed maximum frequency at which
an asynchronously clocked state machine configuration with external
feedback can operate. It is assumed that no expander logic is employed
in the clock signal path or data path.
23.8
50
50
Mil
MHz
40
40
Com'l& Ind
MHz
20
30.3
30.3
50
ns
30
27
27
Mil
Com'l &Ind
ns
27
20
20
Com'l& Ind
15
21
Mil
External Maximum Frequency in
Com'l &Ind
Asynchronous Mode l!(tACOl + tAS)[4, 22]
Mil
fMAXA3
ns
17.5
11
Asynchronous Clock to Local Feedback Com'l& Ind
Input[4,21]
Mil
Maximum Internal Asynchronous
Frequency l!(tAC~ + ttS) or
l!(tAWH + t AWL) 4,23
ns
49
ns
9
Mil
fMAXA2
ns
15
12
7
Unit
35
12
9
Mil
tAWL
Max.
37
12
Asynchronous Clock Input LOW Time l4J Com'l &Ind
fMAXA1
Min.
12
9
Mil
HIGH Com'l& Ind
External ASynchronous Clock Period
(l!fMAX4)[4
CY7C344-35
37
Asynchronous
Timd4,20]
tAP
Max.
25
Mil
tAWH
tACF
Min.
25
Com'l &Ind
Input
CY7C344-25
Mil
Dedicated Input or Feedback Set-Up
Time to Asynchronous Clock Input
Clock
Max.
ns
15
23. This specification indicates the guaranteed maximum frequency at
which an asynchronously clocked state machine with internal-only
feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency
is less than l/tACOl. This specification assumes no expander logic is utilized. This parameter is tested periodically by sampling production material.
24. This specification indicates the guaranteed maximum frequency at
which an individual output or buried register can be cycled in asynchronously clocked mode. This frequency is least of 1/(tAWH + tAwd,
1/(tAS + tAH), or 1/tACOl' It also indicates the maximum frequency at
which the device may operate in the asynchronously clocked data-path
mode. Assumes no expander logic is used.
25. This specification indicates the guaranteed maximum frequency at
which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated
input or an I/O pin.
26. This parameter indicates the minimum time that the previous register
output data is maintained on the output pin after an asynchronous register clock input to an external dedicated input or I/O pin.
4-199
II
en
C
...J
D.
-~
. 'iii CYPRESS
---=-?
CY7C344
SEMICONDUCTOR
1Ypical Internal Switching Characteristics Over Operating Range[7]
Parameter
tIN
Description
Dedicated Input Pad and Buffer Delay
tIO
I/O Input Pad and Buffer Delay
tEXP
tLAD
tLAC
tOD
tzx
txz
tRSU
tRH
tLATCH
tRD
tCOMB
tCH
tCL
tIC
tICS
tpD
tpRE
tCLR
tpcw
tpCR
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable DelaylUJ
Output Buffer Disable Delay
Register Set-Up Time Relative to
Clock Signal at Register
Register Hold Time Relative to
Clock Signal at Register
Flow-Through Latch Delay
Register Delay
Transparent Mode DelayL":llJ
Clock HIGH Time
Clock LOW Time
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Asynchronous Preset and Clear
Pulse Width
Asynchronous Preset and Clear
Recovery Time
Notes:
27. Sample tested only for an output change of 500 mV
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'I&Ind
Mil
Com'l &Ind
Mil
Com'l &Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
Com'l & Ind
Mil
Com'l& Ind
Mil
CY7C344-20
Min.
Max.
5
5
10
9
7
5
8
8
5
9
1
1
1
7
7
8
2
1
CY7C344-25
Max.
Min.
7
7
7
7
15
15
10
10
7
7
5
5
11
11
11
11
8
8
12
12
3
3
1
1
3
3
8
8
8
8
10
10
3
3
1
1
6
5
7
7
7
7
Unit
ns
11
ns
11
ns
20
ns
11
ns
7
ns
8
ns
12
ns
12
ns
11
ns
15
ns
5
ns
1
ns
5
ns
9
ns
9
ns
12
ns
5
ns
1
ns
9
9
9
9
6
5
CY7C344-35
Min.
Max.
12
ns
12
ns
9
ns
9
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
4-200
27
.~
CY7C344
- - - ' j ; CYPRESS
,
SEMICONDUcrOR
Switching Waveforms
r
External Combinatorial
DEDICATED INPUT/
I/O INPUT
COMBINATORIAL
OUTPUT
COMBINATORIAL OR
REGISTERED OUTPUT
------~ ~
tpD1/t pD2
=:l..----------
_______~
___tE_R=l__________
•
~tEA~
HIG't~~~~~tT1~~ - - - - - - - - - - - -
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
--------------------
C344-8
~
_ _~_
ts
SYNCHRONOUS
CLOCK _ _ _ _ _ _J
ASYNCHRONOUS
CLEAR/PRESET _ _ _ _t_OH_ _+-+-_+-J
-----*
REGISTERED
OUTPUTS _ _ _ _ _~.......j~v
1
....1 - - - - - - - tC02
COMBINATORIAL OUTPUT FROM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
REGISTERED FEEDBACK[12]
.
._______________
C344-9
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
~_ _-:-_ _
tAS
ASYNCHRONOUS
CLOCK INPUT ___________
ASYNCHRONOUS
tAOH
CLEAR/PRESET _ _ _ _ _
--+--+_-+-J
ASYNCHRONOUS REGISTERED
OUTPUTS ______________+_~
(0011-.------
------i*
tAC02
COMBINATORIAL OUTPUT FROM _________________________________
ASYNCH. REGISTERED
FEEDBACK[19]
_ ____________
C344-10
4-201
o
Q
..J
D.
External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
•
=r
~~PRESS
CY7C344
~, SEMICONDUCTOR
Switching Waveforms (continued)
Internal Combinatorial
I
tlN-
*
INPUT PIN
I--I--
tlO
I/O PIN
tplA-
-tEXP-
)(
EXPANDER
ARRAY DELAY
-
tLAC, tLAD -
)(
LOGIC ARRAY
INPUT
)K
LOGIC ARRAY
OUTPUT
C344-11
Internal Asynchronous
CLOCKP:
CLOCK INTO
-1 ;= ~WH ~{
~t'NlV
:;;;;; -
__
tF
\..
/
\..
~~.. ::U~~H'*"'---"-~____J/r--""'==============
~~
LOGIC ARRAY _ _ _ _ __
tRD,tLATCH
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
--I-{l--____
'AWL }
-+-
tFD
%t
-
-
tClR,tpRE --+-,tFD
t
-
--------------------tP-IA-J<
------------______________________
C344-12
Internal Synchronous (Input Path)
SYSTEM CLOCK PIN
,
}=
~
tCH
~r--
~~
tIN:EtICS
SYSTEM C L O C K ,
AT REGISTER
--~----~
DATAARRAY
FROM
LOGIC
tRSU
tRH
=*
tCl
----J ./
--{'
-------
'\.
,'---------
/
-_
--_
--_
--_
--_
--_
--_
-_
--_""'_-_
_-_
_
_-_
_
_-_
_
_
C344-13
4-202
. .~
CYPRESS
~ SEMlCONDUcrOR
CY7C344
~.a
Switching Waveforins (continued)
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
DATA FROM
LOGIC ARRAY
OUTPUT PIN
C344-14
Speed
(ns)
20
25
35
Ordering Code
C
Package
Name
Operating
Range
Package 'JYpe
CY7C344- 20HCIHI
H64
28-Lead Windowed Leaded Chip Carrier CommerciallIndustrial
CY7C344-20JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344- 20PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344-20WC/WI
W22
28-Lead Windowed CerDIP
CY7C344- 25HCIHI
H64
28-Lead Windowed Leaded Chip Carrier CommerciallIndustrial
CY7C344- 25JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344- 25PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344-25WC/WI
W22
28-Lead Windowed CerDIP
CY7C344-25HMB
H64
28-Lead Windowed Leaded Chip Carrier Military
CY7C344- 25WMB
W22
28-Lead Windowed CerDIP
CY7C344- 35HMB
H64
28-Lead Windowed Leaded Chip Carrier Military
CY7C344-35WMB
W22
28-Lead Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
•
o
Ordering Information
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
VOL
VIR
VIL
IIX
Ioz
ICCl
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
tpDl
7, 8, 9, 10, 11
tPD2
tPD3
7, 8, 9, 10, 11
7,8,9,10,11
tCOl
ts
7, 8, 9, 10, 11
tH
7, 8, 9, 10, 11
tACOl
tACOl
7, 8, 9, 10, 11
7,8,9,10,11
tAS
tAR
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Document #: 38-00l27-C
4-203
..J
D.
CY7C361
CYPRESS
SEMICONDUCTOR
Features
• High speed: 12S-MHz state machine
output generation
- Token passing
- Multiple, concurrent processes
- Multiway branch or join
• One clock with programmable clock
doubler
• Programmable miser bits for power
savings
• 8 to 12 inputs with input macro cells
- Metastability hardened: 10-year
MBTF
- 0, 1, or 2 input registers
- 3 programmable clock enables
• 32 synchronous state macrocells
• 10 to 14 outputs
Ultra High Speed
State Machine EPLD
- Skew-controlled OR output array
- Outputs are sum of states like PLA
Security fuse
Available in 28-pinslimline DIP and
28-pinHLCC
UV-erasable and reprogrammable
Programming and operation 100%
-testable
A programmable on-board clock doubler
allows the device to operate at 125 MHz internally based on a 62.5-MHz input clock
•
reference. The clock doubler is not a
•
phase-locked loop. It produces an internal
pulse on each edge of the external clock.
•
The length of each internal pulse is determined by the intrinsic delays within the
•
CY7C361. When the doubler is enabled,
all macrocells in the CY7C361 are referProduct Characteristics
enced to the doubled clock. If the clock
The CY7C361 is a CMOS erasable, pro- doubler is disabled, a 125-MHz input.clock
grammable logic device (EPLD) with very can be connected to pin 4, and it will be
used as a clock to all macrocells.
high speed sequencing capabilities.
Applications include high-speed cache and The CY7C361 has two arrays, similar to
I/O sUbsystems control, control of high- those in a PLA except that the registers are
speed numeric processors, and high-speed - placed between the two arrays so that the
arbitration between synchronous or long feedback path of the PLA is eliminated.
asynchronous systems.
Logic BlockDiagram
Pin Configurations
HLCC
Top View
dS'riJrffrf'~rl'
11
M3
12
M2
Vee
GND
GND
13
Vee
GND
14
Is
M1
-L.;.,,;,,:,:;.....,.,n,:.:n;.::;.,:.:,.,:.;.......r
co,.... C\I
0,.... C\J
,('I')
CONDITION DECODER ARRAY
Mo
0361-2
--coma..a..a..
DIP
Top View
STATE REGISTERS
OUTPUT ARRAY
0361-1
0361-3
Selection Guide
Icc rnA at fMAX
Generic Part Number
CY7C361-125
CY7C361-100
CY7C361-83
Com
200
200
Mil
fMAXMHz
Com
Mil
200
125.0
100.0
100.0
3
3
19
19
83.3
83.3
5
5
23
23
4-204
tIS ns
Com
teons
Mil
2
Com
Mil
15
.
. _
:~pRE.SS
JF
CY7C361
SEMICONDUCTOR
Product Characteristics (continued)
In the CY7C361, the state information is contained in 32 state macrocells sandwiched between the input and output arrays. The current state information is fed back fast enough to achieve the
125-MHz operating frequency. These state macrocells also have
serial connections that allow state machines to be built using a token-passing methodology similar to one hot encoding, but with the
ability to support multiple active states at any given time.
The output array performs an OR function over the state macrocell
outputs, allowing the control signals of the state machine to be produced directly. The signals from the output array are connected to
the 14 device outputs (4 of which are bidirectional). In addition
there are 3 sum terms that act as clock enables to the 3 groups of
input macrocells. There are also 4 sum term output enables for the
4 bidirectional pins.
Input Macrocells
The CY7C361 has 12 input macrocells, shown in Figure 1. Each
macrocell can be configured to have 0, 1, or 2 registers in the path
of the input data. In the configuration where there is no input register, the set-up time required is the longest, because it includes the
propagation delay through the input array plus the state register
set-up time. In the single-registered configuration the set-up time
is less than half of the unregistered case. The double-registered
configuration is used to synchronize asynchronous inputs without
causing metastable events.
00
01
TO
INPUT
ARRAY
1X
DATA
CLOCK
C1
ENABLE - - - - - 4 - - - - - '
CO
0361-4
more information on metastability, refer to the ''Are Your PLDs
Metastable?" application note in the Cypress Applications Handbook.
Input Array
The input array is based on the condition decoder, shown in Figure
2. In a conventional PLA or PLD device, only PRODUCTl would
be present in thefirst array and the output and the feedback would
be encoded by a second programmable orfixed or array. The speed
of state machines is limited mainly by the feedback path.
PRODUCT 1
PRODUCT 2
(I)
C
....I
MISER
Figure 2. Condition Decoder
The condition decoder of the CY7C361 forms a product of a product and a sum over the input field. (The sum term is obtained by
inverting the inputs to PRODUCT2.) Since there is immediate
feedback information in the input field, multiway fork and join operations can be performed using this type of condition decoder. In
other words, the condition decoder is used to control or gate the
token being passed from macrocell to macrocell. In contrast, a
traditional PLD or PLA requires more logic because the array is
used to encode the states. In the CY7C361, state transitions can be
made in half the time because there is no "state encoding" delay.
Each condition decoder has a miser bit in its sum term path. If the
term is not used, the miser bit is automatically programmed. The
miser bit completely disconnects the product term and replaces it
with a logic HIGH. This results in a power savings.
The input array has 41 condition decoders: one global reset decoder, 8 local reset decoders, and 32 macro cell decoders. The array has
44 true/complement input pairs, 88 inputs total.
Figure 1. Input Macrocell
Input Register Enables
The input macrocells are divided into 3 groups of 4 macrocells
each. Each of these groups has a register clock enable coming from
the output array. The assignment of enable signal node numbers to
input macrocells is as follows:
Input Nodes
3,5,6,9
10, 11, 12, 13
1,2, 14, 15
Enable Node
29
30
31
When the enable node is true, data is clocked into the registers of
the input macrocells on the rising edge of the internal global clock.
Metastability Immunity
A high level of metastable immunity is afforded in the double-registered configuration. The CY7C361 registers are done in fast
CMOS and they resolve inputs in a minimal amount of time. With
all inputs switching at maximum frequency, one metastable event
capable of violating the set-up time of a subsequent register occurs
every 10 years. The probability of failure in a configured state machine is much lower than this calculation suggests, because there
are more registers in the device and thus more decision time is allowed. No state machine failures due to metastable phenomena
will be observed ifthe maximum frequency and double-registered
operation frequency are used. This makes the CY7C361 ideally
suited for constructing state machines requiring arbitration. For
•
For speed reasons, the feedback signals are segmented. This means
that for each group of 8 macrocells, 2 have global feedback, 2 have
intermediate feedback to 16 of the 32 macrocells, and 4 have local
feedback within their group of 8 macrocells only. Segmenting the
feedback reduces the number of inputs per decoder to 56. Because
the CY7C361 utilizes token passing, a large state machine will be
effectively broken down into several smaller machines using 4 or
less macrocells. The global and intermediate feedback is used to
communicate between these smaller machines, and the local feedback is used within the smaller machines. For more information on
the hot state encoding or token-passing design methodology, refer
to the application notes titled "State Machine Design Considerations and Methodologies" and "Understanding the CY7C361" in
the Cypress Applications Handbook.
State Machine Macrocells
The CY7C361 has 32 state macrocells. The state macrocells each
have a single condition decode and share a common clock and
global reset condition. The global reset is synchronous, and it lasts
for two internal clock cycles. For each group of four state macrocells, there is a synchronous local reset condition.
All 32 ofthe macrocells are "daisy-chained." Each has a C_IN input that is connected to the C _OUT output ofthe previous macro-
4-205
Q.
~
~~PRFSS
~, SEMICONDUCTOR
CY7C361
cell, as shown in Figure 3. Configuration bit C2 is used in all state
macrocells to select C _IN to be active (C2=0) orinactive (C2= 1).
CONDo
DECOD~
::1
The TERMINATE macrocell (see Figure 5) captures a token via
the C_IN path. The token is then held in the state register until the
condition decoder fires, which causes the token to be terminated.
Another way of saying this is that the TERMINATE macrocell is
like a synchronous SR flip-flop. It is set by C_IN and reset by the
condition decoder. Local resets have no effect on this configuration.
STATE
INPUT
LOCAL
RESET
GLOBAL
RESET
CLOCK
0361-6
Figure 3. CY7C361 Macrocell
For the topmost macrocell (node 32), the C2 bit is used to specify
a reset option. If the bit is 0, then the C_IN for this macrocell will
be true (1). If the C2 bit is 1, then the C_IN for the macrocell will
be false (0).
There are three state macrocell configurations: START,
TOGGLE, and TERMINATE. The purpose of the STARTconfiguration is to create a "token" based on the condition decode_ The
TOGGLE configuration is used for building counters. The TERMINATE configuration is used to insert wait states in a process. It
captures a token and holds it until a condition tells it to terminate
the token_
Figure 4 shows a state macrocell in the START configuration. This
configuration synchronously creates a token if C_IN or tl).e condition decode is a logic HIGH. The token is represented by a true
output on the macrocell register going to the output array and back
as feedback to the input array. A machine implemented in the
CY7C361 will consist of multiple machines or processes running
concurrently, each with zero, one or more tokens active at any given time. Put another way, each state macrocell in the CY7C361 can
be thought of as a line of microcode that can execute concurrently.
0361-8
Cl,CO
= 0,1: TERMINATE
Figure 5. Terminate Configuration
The TOGGLE macrocell (see Figure 6) operates like a T-type flipflop. If C_IN or the condition decode is asserted, the state register
will toggle on every rising edge of the internal clock. If neither the
C_IN nor the condition decoder are asserted, the state register will
retain its current state. The TOGGLE configuration is used to
build counters. A local reset condition will synchronously reset the
state register in this configuration_
OUTPUT
ARRAY
Cl,CO = 1,0: TOGGLE
Figure 6. Toggle Configuration
0361-7
The Output Array
Cl,CO = 0,0: START
Figure 4. Start Configuration
In addition to the main register going to the array, there is an R-S
latch in the feedback path that is used to convert the input condition to a pulse.
In operation, the START macrocell starts from a reset condition
(output array input = FALSE). When a condition decode "fires" or
a token is carried in (C_IN), the register output (0 going to the
array) goes true for exactly one cycle. The OR of the condition decode and the C_IN must go FALSE before the START configuration can fire again_ Local resets have no effect on this configuration.
The output array is an OR-based array. The array inputs are the
LOW-asserted outputs of the 32 state macrocells. There are five
types of array outputs. The first type is the three clock enables for
the input macrocells. Each enable is a programmable OR of asserted state macrocells; when one of the connected macrocells is
asserted, the clock is enabled. Next are the four output enables of
the bidirectional I/O pins. Again, the output enables are a programmable OR of the connected asserted state macrocells; when
one of the connected macrocells is asserted, the output is enabled.
The third type of array output is the "pure" device output. These
six outputs are a functional OR ofthe Low-asserted outputs ofthe
state registers_ Nextis the output path ofthe four bidirectional I/O
pins, which is identical to that of the "pure" outputs. The last type
of array output is the Mealy output macrocell. The CY7C361 has
four of these outputs; they can be used as a fast combinatorial out-
4-206
==:tz;:~
CY7C361
_'iECYPRESS
_ , SEMICONDUcrOR
put. The three device outputs are pictured in Figure 7, Note that the
Mealy output is the only one that is configurable.
~NORMAL
~OUTPUT
OR TERM
~
OR TERM
BIDIRECTIONAL
OUTPUT
-:PUT
C1 CO
C2
•
MEALY
OUTPUT
L-----I11
user. The architecture is thus "horizontally divisible" and offers advantages in coding efficiency and event response time over the nondivisible architectures found in most PLA and sequencer implementations.
An output pin is normally LOW-asserted. The output gate performs an OR function over the flip-flop outputs ofthe state macrocells. The OR function includes only the outputs that are programmed to be connected to the OR line in the output array. When
none of the connected state macrocell flip-flops are in the true or
set condition, the output is HIGH, or deasserted. If any connected
macrocell flip-flop is asserted (true) then the OR gate function is
true and the output pin is Law.
Forcing a false condition is easily accomplished by disconnecting
all of the state macrocells from the OR line. To force a true condition, the OR line is connected only to node 73, which is labeled as
Vee in the block diagram. Any OR line connected to this node will en
be forced permanently true, which will cause any normal output to
always be Law.
D.
The bidirectional outputs are I/O pins that may be used as either
inputs or outputs. Under state machine control, these pins may be
three-stated and used as inputs or outputs depending on how the
OE term is programmed. If the OE is connected to node 73, the pin
will always function as an output.
The Mealy outputs are designed to implement the fastest possible
path between a device input and an output. Functions are available that combine the OR term and a specific input signal. These
functions, XOR, AND, and OR, coupled with output polarity
control are useful for data strobes and semaphore operations
where signaling occurs based on the current state, but independent of a signal transition.
9
0361-10
FUNCTION
Figure 7. Output Configurations
In order to reduce output skew, the CY7C361 output array contains a set of self-timed latches in the output array path. These
latches are controlled by an internal clock that has a delay equal to
the worst-case path through the output array. While this delayed
internal clock is Law, the output array data is latched. When the
delayed internal clock is HIGH, the latches become transparent,
and the outputs change. These latches are the reason why the
teo max is 15 ns with respect to the state registers, but the part can
change its outputs every 7.5 ns. Since these latches cannot be accessed by the user, they have been left off of the block diagram.
The normal output signal from the device is a boolean sum of a subset of the state macrocell outputs. The subset selection is programmed into the output array. The number of state machines in
the device, and the output mappings of each are determined by the
The AND and OR functions can be used to gate data strobe signals
by the state. The XOR function can be used to implement twocycle signaling, which is used in self-timed systems to minimize
signaling delays. If these functions are not needed, then the Mealy
outputs can be configured as normal outputs.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential
(DIP Pins 7 or 22 to Pins 8, 21, or 23) ...... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
During Programming . . . . . . . . . . . . . . . . . . . . .. O.OV to + 7.0V
DC Input Voltage ....................... - 3.0V to +7.0V
DC Programming Voltage . , , ... __ ... _, ............. 13.0V
Output Current into Outputs (LOW) ................ 8 rnA
UV Exposure ...................... , ..... 7258 Wsec/cm2
Latch-Up Current ............................ >200 rnA
Static Discharge Voltage ............. ,.......... > 1500V
(per MIL-STD-883, Method 3015)
Operating Range
4-207
Range
Commercial
Military
Ambient
Temperature
O°C to +70°C
Vee
5V ± 10%
- 55°C to +125°C
5V ± 10%
~~PR£SS
-=;;;;;, SEMICONDUCTOR
CY7C361
Electrical Characteristics Over the Operating Range
Description
Parameter
Min.
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
= Min., VIN = VIR or VIL 1 IOH = -4.0 rnA
Vee = Min., VIN = VIR or VIL I IOL = 8.0 rnA
VIR
Input HIGH Level
Guaranteed HIGH Input, All Inputs[lj
VIL
Input LOW Level
Guaranteed LOW Input, All Inputs[lj
IIX
Input Leakage Current
loz
Output Leakage Current
Iscl2j
lecl2,4j
Output Short Circuit Current
= Max.
= Max., Vss < VOUT < Vee
Vee = Max., VOUT = 0.5V[3j
Vee = Max., VIN = GND,
1 Commercial
Outputs Open,
Operating at f = fMAX
I Military
Vee
Power Supply Current
TI
R1 481 Q
OUTP~~
I
30 pF
INCLUDING
JIG AND
SCOPE
-
OUTP~~
2.2
V
V
0.8
V
Vss < V IN < Vee, Vee
IlA
Vee
-40
+40
IlA
-30
-110
rnA
200
rnA
3.
sn
5 pF
-
4.
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second. VOUT = O.SV has
been chosen to avoid test problems caused by tester ground degradation.
Tested with device programmed as an 8-bit counter.
ALL INPUT PULSES
I
3.0V---90%
R2
255Q
GND
- -0361-11
(a)
Equivalent to:
V
0.4
+10
R1 4810
R2
255Q
Unit
-10
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. Tested initially and after any design or process changes that may affect
this parameter.
AC Test Loads and Waveforms
Max.
2.4
c361-12
(b)
THEVENIN EQUIVALENT
1670
OUTPUT
o------vvv-----
1.73V = Vth
0361-13
Test Waveforms
Parameter
teER(-)
teER(+)
Vx
O.OV
Output Waveform-Measurement Level
VOH
2.6V
VOL
teEA(+)
Vth
Vx
teEA(-)
Vth
Vx
0.5V~
O.5V~
O.5V~
0.5V~
4-208
~~
7r
7r
~~
Vx
c361-14
Vx
c361-15
VOH
c361-16
VOL
c361-17
SZ:.-.~
--=-,
CY7C361
~=CYPRESS
SEMICONDUCTOR
Commercial Switching Characteristics Over the Operating Rangd5, 6]
-125
Parameter
Description
-100
-83
Min.
Max.
Min.
Max.
Min.
Max.
Unit
2
9
2
11
2
12
ns
tpD
Input to Mealy Output Delay
tco l7J
tCM PJ
Clock to Output Delay
15
19
23
ns
Clock to Mealy Output Delay
17
20
25
ns
tOH
Output Stable Time
5
5
5
ns
tIS
Input Register Input Set-Up Time
2
3
5
ns
tlH
Input Register Input Hold Time
3
4
5
ns
tsl~J
State Register Input Set-Up Time
7
9
12
ns
tHl~J
State Register Input Hold Time
0
0
0
ns
tDWHl2, 9, 10J
Input Clock Pulse Width HIGH
(Doubler Enabled)
6
7
9
ns
tDWL[2, 9, 10]
Input Clock Pulse Width LOW
(Doubler Enabled)
6
7
9
ns
tDP l2 ,1OJ
Input Clock Period (Doubler Enabled)
15
20
24
ns
tWHl2, 9, 11]
Input Clock Pulse Width HIGH
2
3
4
ns
tWLl2, 9,11]
Input Clock Pulse Width LOW
2
3
4
ns
t p l2,I1J
Input Clock Period
7.5
10
12
tsol12J
tSM l13J
Output Skew
2
2
2
ns
Mealy Output Skew
3
3
3
ns
fMAXIl2,I1J
Input Maximum Frequency
(Doubler Enabled)
62.5
fMAX[2,4J
Output Maximum Frequency
125.0
tCER l2,6J
tCEAl2, 14, 15J
Clock to Output Disable Delay
16
20
22
ns
Clock to Output Enable Delay
16
20
22
ns
•
en
C
..J
D.
Notes:
5. Output reference point on AC measurements is 1.Sv, except as noted
in Test Waveforms:
tCER( -) negative going is measured at VOH - O.SY.
tCER( + ) positive going is measured at VOL + O.5V
6. Part (a) of AC Test Loads and Waveforms is used for all parameters
except tCEA and tCER. Part (b) of AC Test Loads and Waveforms is
used for tCEA and tCER.
7. This specification is guaranteed for the worst-case programmed pattern for which all device outputs are changing state on a given access or
clock cycle.
8. Input register bypassed.
9. The clock input is tested to accommodate a 60/40 duty cycle waveform
at the maximum frequency.
10. This applies to the input clock when the doubler is enabled.
50.0
ns
41.7
100.0
MHz
83.3
MHz
11. This applies to the input clock when the doubler is disabled.
12. This parameter specifies the maximum allowable tco clock to output
delay difference, or skew, between any two outputs on the same device
triggered by the same clock edge with all other device outputs changing state within the same clock cycle.
13. This parameter specifies the maximum allowable tpD difference between any two Mealy outputs on the same device triggered by the same
or simultaneous input signals with all other device outputs changing
state within the same access or clock cycle.
14. Rl is disconnected for tCEA(+) positive going (open circuited). See
part (b) of AC Test Loads and Waveforms.
15. R2 is disconnected for tCEA( _) negative going (open circuited). See
part (b) of AC Test Loads and Waveforms.
4-209
&: :~
CY7C361
~1~pRF.SS
~.L
SEMICONDUcroR
Military Switching Characteristics Over the Operating Range[S, 6]
Military
-83
-100
Description
Parameter
Min.
Max.
Min.
Max.
Unit
1.5
11
1.5
13
ns
tpD
tCO[7]
Input to Mealy Output Delay
Clock to Output Delay
19
23
ns
tCM[7]
Clock to Mealy Output Delay
21
25
ns
tOH
Output Stable Time
5
5
ns
tIS
Input Register Input Set-Up Time
3
5
ns
tlH
ts l8 ]
tH l8 ]
Input Register Input Hold Time
4
5
ns
State Register Input Set-Up Time
9
12
ns
State Register Input Hold Time
0
0
ns
tDWHL2, 9, 1UJ
Input Clock Pulse Width HIGH
(Doubler Enabled)
7
9
ns
tDWLI2, 9, 10j
Input Clock Pulse Width LOW
(Doubler Enabled)
7
9
ns
tDP[2,1O]
Input Clock Period (Doubler Enabled)
20
Input Clock Pulse Width HIGH
3
24
,4
ns
tWH[2, 9,11]
tWLl2, 9, 11J
Input Clock Pulse Width LOW
3
4
ns
tp[2,11J
Input Clock Period
10
12
tsol12J
tSM l13J
Output Skew
3
3
Mealy Output Skew
4
4
ns
ns
ns
ns
fMAXI l2 ,I1J
Input Maximum Frequency
(Doubler Enabled)
fMAX L2,4j
Output Maximum Frequency
tCERI()j
tCEAI2, 14, 1:Jj
Clock to Output Disable Delay
20
22
ns
Clock to Output Enable Delay
20
22
ns
41.7
50
100.0
4-210
MHz
MHz
83.3
-
~~PRFSS
=====-..,
CY7C361
27
SEMICONDUCTOR
Switching Waveforms
Clock Doubler Inactive (Virgin State).
Nonregistered Input (Virgin State - CI,CO = 0,0).
EXTERNAL (INPUT) CLOCK
,
.~ts
NONREGISTERED INPUT
tWL
\.
tWH
tp_
\.
'\.
X
MEALY INPUT
•
X
tco
tco
ANY Po - P5
I
II
xx XXXXXXXI
-tOH-
X
I.-
tso.,
xXXXXXXXXI
ANY OTHER Po - P5
I--
tCM
tpo (MAX) -
MEALY OUTPUT A
xxxxxxx
tpo
(MIN)
r--
-tOH-
XXXXXXl[
MEALY OUTPUT 8
tSM ....1
1 ...
....
xxxxxxxxxxxx
...
xxxxxxxxxxx
tSM
tCEA
tCER
I
-I
OUTPUT 8 0 - 8 3
0361-18
Clock Doubler Enabled (CO = I)
Nonregistered Input (Virgin State - CI,CO = 0,0)
tOWL ~ tOWH~
EXTERNAL (INPUT) CLOCK
NONREGISTERED INPUT
"
l..
r--
I-----
ts
;
top
l..
J
I
-
X
X
MEALY INPUT
_tcOI
I--tco-
ANY Po - P5
X
I+--
tOH - ~
:x
ANY OTHER Po - P5
~tpo-
MEALY OUTPUT A
14---
.-.j
tOH ~ tSM
XXX
I--
OUTPUT 80 - 83
XX
-tCMtCM.---t
XXX
f4---
MEALY OUTPUT 8
~I
XXX
i+" tso
-
Xx.
XX
X
XX
I
tCER ----.j
-tCEA
____________~r-=1~===========
0361-19
4-211
1iiiir.~~DUC1CO
CY7C361
Switching Waveforms (continued)
Clock Doubler Inactive (Virgin State).
Single·Registered Input (Cl,CO = 0,1).
,
tp~
EXTERNAL (INPUT) CLOCK
l\..
I tl5
.I
REGISTERED INPUT
~tWL"'" I---
tlH I
](
-
~
1..
tWH
x
](
~
MEALY INPUT
tco
teo
xxxxxxx
ANY Po - Ps
I-t--
toH-
xxxxxx
ANY OTHER Po - Ps
_
..
~xxxxxx
tpo
(MIN) ~
MEALY OUTPUT B
t5M
t50
XXXXXXXXX
-I
xxxxx
AXXXXXXX
tCM
t5M ~
~
,xxxxxxxx
~xxxxxxx
xxxxxxxxx
tCEA
..
j ..
tCM
tpo(MAX)-
MEALY OUTPUT A
xxxx
XXXX
t5011..-
tCER
-+l
II
~ t5M
II
OUTPUT Bo - B3
0361-20
Clock Doubler Enabled (CO = 1)
Single-Registered Input (Cl,CO = 0,1)
I---EXTERNAL (INPUT) CLOCK ".1
REGISTERED INPUT
X
/
"'
I
X
_tco
~tco_-=1
-tOH-
r-
X
XXX
H~
ANY OTHER Po - Ps
t50
:X
XXX
......... toH ~
XX
I-tCM-tCM_-!
~tpo-
XX
XX
X
XX
f-
-'1 ..
i4- t5M
XXX
---------9
~tCER
OUTPUT Bo - B3
"J
_top
ANY Po - Ps
MEALY OUTPUT B
tOWH ~
X
MEALY INPUT
MEALY OUTPUT A
t
f
"'J" tlH
tl5
tOWL
te"
t5M
=1----0361-21
4-212
~~
_rs~CONDUcrOR
CY7C361
Switching Waveforms (continued)
Clock Doubler Inactive (Virgin State)
Double-Registered Input (Ct, Co = I,X)
EXTERNAL (INPUT) CLOCK
~
~~
~:3-tiS
2-REGISTERED INPUT
tlH
tWL··tWH
x
--x
x
MEALY INPUT
X.
.
tco
•
tco
-tOH-
tSOjl.-
tso
--11+-
ANY OTHER Po - P5
-
tpD (MAX) -
.. I
tCM
i
MEALY OUTPUT A
tpD
(MIN)
...-
tSM
1l
tSM
1
.....1--_ _ _ _
t~:R
--,.1J
tCM
MEALY OUTPUT B
OUTPUTBo -B3
•
(I)
ANY Po - P5
--I j..
tSM
r_____
____
tc~!j - - - -....
::::::::::::::::::::::::::::::::::::::::::~~-------~~:::::::::
c361-22
4-213
...
Q
A.
1Ii~~ ~~~~~~~~~~~~~~~~CY~7~C~36~1~
CY7C361 Block Diagram (Upper Half)
o I; i8~~ ~~~;
II
j!~
~~ ~~ ~~ ~~ If ~f ~1 J~ ;~ ~1 ~1. ~~
.r:;:
! J
!E :E
rf
!B tE3 it: Et:
Et:::pI!3 IEliE
ir rr
4-214
.il~
CY7C361
CY7C361 Block Diagram (Lower Half)
.-
~~
-.:"
~
~
~
""i ~
~1
~~
~~
~ a:
~2
~;
L.:.
! :;:
N
..
-i
~
~
,
"
7
rr
4-215
II
en
C
..J
Q.
5·~
'= CYPRFSS
CY7C361
_ , SEMICONDUcrOR
Ordering Information
Icc rnA
fMAX
MHz
200
125.0
100.0
Ordering Code
Package 1)rpe
H64
28-Pin Windowed Leaded Chip Carrier
Commercial
CY7C361-125WC
W22
28-Lead (300-Mil) Windowed CerDIP
28-Pin Windowed Leaded Chip Carrier
Commercial
CY7C361-100HC
H64
CY7C361-100WC
W22
H64
Q64
28-Pin Windowed Leaded Chip Carrier
28-Pin Windowed Leadless Chip Carrier
CY7C361-100WMB
CY7C361-83HC '
W22
28-Lead (300-Mil) Windowed CerDIP
H64
28-Pin Windowed Leaded Chip Carrier
CY7C361-83WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C361-83HMB
CY7C361-83QMB
H64
Q64
28-Pin Windowed Leaded Chip Carrier
28-Pin Windowed Leadless Chip Carrier
CY7C361-83WMB
W22
28-Lead (300-Mil) Windowed CerDIP
28-Lead (300-Mil) Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIH
1,2,3
VIL
1,2,3
Irx
1,2,3
Ioz
1,2,3
Switching Characteristics
Parameter
Subgroups
tpD
7, 8, 9, 10, 11
tco
7, 8, 9, 10, 11
tCM
7,8,9, 10, 11
7, 8, 9, 10, 11
tOH
trs
tIH
Operating
Range
CY7C361-125HC
CY7C361-100HMB
CY7C361-100QMB
83.3
Package
Name
7,8,9,10,11
7,8,9,10,11
ts
7, 8, 9, 10, 11
tH
7, 8, 9, 10, 11
Document #: 38-00106-C
4-216
Military
Commercial
Military
FLASH370
PLD Family
PRELIMINARY
High-Density Flash PLDs
Features
• Warp2'"
- Low-cost, text-based design tool,
PLDcompiIer
- IEEE 1076-compliant VHDL
- Available on PC and Sun platforms
• Warp3'" CAE development system
-VHDLinput
- ViewLogic graphical user interface
- Schematic capture (ViewDraw)
- VHDL simulation (ViewSim)
- Available on PC and Sun platforms
• Flash erasable CMOS PLDs
• High density
-32-256 macrocells
- 32 - 256 I/O pins
- Multiple clock pins
• High speed
-tpo = 10-15 ns
-ts = 7.5-12 ns
-teo = 7.5 ns-12 ns
• Fast Programmable Interconnect Matrix (PIM)
- Uniform predictable delay, independent of routing
- No penalty for traversing PIM
• Intelligent product term allocator
- 0-16 product terms to any macrocell
- Provides product term steering on
an individual basis
- Provides product term sharing
among local macrocells
- Prevents wasting and stealing of
neighboring product terms
• Simple timing model
- No fanout delays
- No expander delays
-No dedicated vs.I/O pin delays
- No additional delay through PIM
- No penalty for using full 16 product terms
- No delay for steering or sharing
product terms
• Flexible clocking
- 2 -4 clock pins per device
- Clock polarity control
• Packages
-44-288 pins
- PLCC, LCC, PGA, and QFP
packages
General Description
The FLASH370 family of CMOS PLDs
provides a range of high-density programmable logic solutions with unparalleled
performance. Each member of the family
is designed with Cypress's state-of-the-art
0.65-micron Flash technology. All of the
devices are electrically erasable and reprogrammable, simplifying product inventory
and reducing costs.
The FLASH370 family is designed to bring
the flexibility, ease of use and performance
of the 22VlO to high-density PLDs. The
architecture is based on a number of logic
blocks that are connected by a Programmable Interconnect Matrix (PIM). Each
logic block features its own product term
array, product term allocator array, and 16
macrocells. The PIM distributes signals
from one logic block to another as well as
all inputs from pins.
The family features a wide variety of densities and pin counts to choose from. At each
density there are two packaging options to
choose from-one that is I/O intensive and
another that is register intensive. For example, the CY7C374 and CY7C375 both
feature 128 macrocells. On the CY7C374
half of the macrocells are buried and the
device is available in 84-pin packages. On
the CY7C375 all of the macrocells are fed
to I/O pins and the device is available in
164-pin packages. Figure 1 shows a block
diagram of the CY7C374/5.
Functional Description
Programmable Interconnect Matrix
The Programmable Interconnect Matrix
(PIM) consists of a completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM
is an extremely robust interconnect that
avoids fitting and densi ty limitations which
plague competing high-density solutions.
Routing is automatically accomplished by
software and the propagation delay
through the PIM is transparent to the user.
Signals from any pin or any logic block can
be routed to any or all logic blocks.
The inputs to the PIM consist of all I/O
and dedicated input pins and all macrocell feedbacks from within the logic
blocks. The number of PIM inputs increases with pincount and the number of
logic blocks. The outputs from the PIM
are signals routed to the appropriate logic
block(s). Each logic block receives 36 inputs from the PIM and their complements, allowing for 32-bit operations' to
be implemented in a single pass through
the device. The wide PIM-to-Iogic block
interface also improves the routing capacity of the FLASH370 family.
An important feature of the PIM involves
timing. The propagation delay through the
PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM.
In fact all inputs travel through the PIM.
Likewise, there are no route-dependent
timing parameters on the FLASH370 devices. The worst -case PIM delays are incorporated in all appropriate FLASH370
specifications.
FLASH370 Selection Guide
Device
Pins
44
Macrocells
32
Dedicated Inputs
I/O Pins
32
Flip-Flops
Speed (tpo)
6
44
10
44
64
6
32
76
84
64
6
64
76
12
12
374
84
375
160
128
128
6
6
64
128
140
140
12
12
371
372
373
"31'6 ",!*!
J'll!7 1, ,TV
16t"
',"
'28~
,\,:'
,"" 1,.
,.2S~'
t:
',,6 "
',;' ,I,
' i," !Jii,;/'t6"
'" .c.25?'. '
4-217
p; ,,:~q~'i
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v,
' $\
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(;n
PRELIMINARY
• CYPRESS
SEMICONDUCTOR
FLASH370
CLOCK
INPUTS
4
INPUT
MACROCELLS
36
36
16
16
36
16
36
PIM
16
36
36
16
16
36
36
16
16
flash370·1
Figure 1. CY7C374/5 Block Diagram
Functional Description (continued)
Finally, routing signals through the PIM is completely invisible to
the user. All routing is accomplished 100% by software-no hand
routing is necessary. Wa1p2 and third-party development packages
automatically route designs for the FLASH370 family in a matter
of minutes.
Logic Block
The logic block is the basic building block of the FLASH370 architecture.1t consists of a product term array, an intelligent productterm allocator, 16macrocells, and a number ofI/O cells. The number of I/O cells varies depending on the device used.
There are two types oflogic blocks in the FLASH370 family. The
first type features an equal number (16) ofI/O cells and macrocells
and is shown in Figure 2. This architecture is best for I/O-intensive
applications. The second type oflogic block features a buried macrocell along with each I/O macrocell. In other words, in each logic
block, there are eight macrocells that are connected to I/O cells
and eight macrocells that are internally fed back to the PIM only.
This organization is designed for register-intensive applications
and is displayed in Figure 3. Note that at each FLASH370 density
(except the smallest), an I/O intensive and a register-intensive device is available.
Product Term Array
Each logic block features an x 86 programmable product term
array. This array is fed with 36 inputs from the PIM, which originate from macrocell feedbacks and ihputpins. Active LOW and ac-
tive HIGH versions of each ofthese inputs are generated to create
the full n-input field. The 86 product terms in the array can be
created from any of the
inputs.
n
Of the 86 product terms, 80 are for general-purpose use for the 16
macrocells in the logic block. Four of the remaining six product
terms in the logic block are output enable (OE) product terms. The
OE product terms control 8 ofthe 16 macrocells alld are selectable
on an individual macrocell basis. In other words, each I/O cell can
select between one of two OE product terms to control the output
buffer. The final two product terms in each logic block are dedicated set and reset product terms.
Product Term Allocator
Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block
as needed. A total of 80 product terms are available from the local
product term array. The product term allocator provides two important capabilities without affecting performance: product term
steering and product term sharing.
Product Term Steering
Product term steering is the process of steering product terms to
macrocells as needed. For example, if one matrocell requires ten
product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to
the other. On FLASH370 devices, product terms are steered on an
individual basis, Anv number between 0 and 16 product terms can
be steered to any IIl-~crocell. Note that 0 product terms is useful in
4-218
~
. :r&PRESS
PRELIMINARY
~;;r SEMICONDUCTOR
FLASH370
0-16
PRODUCT
TERMS
0-16
PRODUCT
TERMS
FROM
PIM
I
36
72x86
PRODUCT TERM
ARRAY
86
•
PRODUCT
TERM
ALLOCATOR
U)
Q
..J
0-16
~
0-16
16
TO
PIM
16
flash370-2
Figure 2. Logic Block for CY7C371, CY7C373, CY7C375, and CY7C377 (I/O Intensive)
.-I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --,
I
.1
I
I
l
0-16
PRODUCT
TERMS
I
I
I
I
I
I
0-16
PRODUCT
TERMS
I
I
I
I
FROM
PIM
I
I
I
I
36
72x86
PRODUCT TERM
ARRAY
"I
PRODUCT
TERM
ALLOCATOR
86
I
I
I
0-16
I
I
LtJ
I
I
I
I
··
··
··
··
C~~L
I/O
CELL
8
1
I
I
I
I
I
I
I
I
I
I
··
··
I
I
I
I
I
I
0-16
I
I
4MACRO~
1
CELL
16
I
I
I
I
I
I
I
TO
PIM
I
I
CELL
2
r MACRO=!
1
I
C~LL r
4 MACRO-~
I
I/O
MACRO-I
16
I
I
I
I
I
I
I
I
I
I
I
1-
8
_____________________________________________________________
I
_
flash37D-3
Figure 3. Logic Block for CY7C372, CY7C374, and CY7C376 (Register Intensive)
4-219
:iJJ:~
~;
PRELIMINARY
FLASH370
SEMICONDUcrOR
cases where a particular macrocell is unused or used as an input
register.
Product Term Sharing
Product term sharing is the process of using the same product term
among multiple macrocells. For example, if more than one output
has one or more product terms in its equation that are common to
other outputs, those product terms are only programmed once.
The FLASH370 product term allocator allows sharing across
groups of four output macrocells in a variable fashion. The software automatically takes advantage of this capability-the user
does not have to intervene. Note that greater usable density can
often be achieved if the user "floats" the pin assignment. This allows the compiler to group macrocells that have common product
terms adjacently.
One last thing to reiterate is that neither product term sharing nor
product term steering have any effect on the speed of the product.
All worst -case steering and sharing configurations have been incorporated in the timing specifications for the FLASH370 devices.
FLASH370Macroceil
I/O Macrocell
Within each logic block there are 8 or 16 I/O macrocells depending
on the device used. Figure 4 illustrates the architecture of the I/O
macrocell. The macrocell features a register that can be configured
as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered
latch.
The register can be asynchronously set or reset on a logic block basis with the separate set and reset product terms. Each of these
product terms features programmable polarity. This allows the
registers to be set or reset based on a single product term or sum
term.
Clocking of the register is very flexible. Depending on the device,
either two or four global synchronous clocks are available to clock
the register. Furthermore, each clock features programmable polarity so that registers can be triggered off falling as well as rising
edges (see the Dedicated/Clock Inputs section).
At the output of the macrocell, a polarity control mux is available
to select active LOW or active HIGH signals. This has the added
advantage of allowing significant logic reduction to occur in many
applications.
One last thing to note about the I/O macrocell on the FLASH370
family concerns feedback. The macrocell features a feedback path
to the PIM separate from the I/O pin input path. This means that if
the macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Buried Macrocell
Some of the devices in the FLASH370 family feature additional
macrocells that do not feed individual I/O pins. Figure 5 displays
the architecture of the I/O and buried macrocells for these devices.
The I/O macrocell is identical to the one on devices without buried
macrocells.
The buried macrocell is very similar to the I/O macrocell. Again, it
includes a register that can be configured as combinatorial, as aD
flip-flop, aT flip-flop, or a latch. The clock for this register has the
same options as described for the I/O macrocell. The primary difference between the I/O macrocell and the buried macrocell is that
the buried macrocell does not have the ability to output data directly to an I/O pin.
One additional difference on the buried macrocell is the addition
of input register capability. The user can program the buried macrocell to act as an input register whose input comes from the I/O
pin associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its configuration.
FLASH370 I/O Cell
The I/O cell on the FLASH370 devices is illustrated along with the
I/O macrocell in Figures 4 and 5. The user can program the I/O cell
to change the way the three-state output buffer is enabled and/or
disabled. Each output can be set permanently on (output only),
permanently off (input only), or dynamically controlled by one of
two OE product terms.
Dedicated/Clock Inputs
A number of pins on each member of the FLASH370 family are
designated as input-only. There are two types of dedicated inputs
on FLASH370 devices: input pins and input/clock pins. Figure 6 il-
I/O MACROCELL
i - I/O CELL
r - - -
- - - - - - - - - - - - - -.
I "0"
1"1"
C5_ _
C6_ _ _ _ _ _ _ _ _ J
__
_____________________________________ J
FEEDBACK TO PIM
FEEDBACK TO PIM
flash370·4
BLOCK RESET .
BLOCK PRESET
2 BANK OE TERMS
4 SYSTEM CLOCKS
Figure 4. I/O Macrocell
4-220
~~CYPRF.SS
~AJ
~,
PRELIMINARY
FLASH370
SEMICONDUCTOR
lustrates the architecture for input pins. Four input options are
available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any
one of the input clocks can be selected for control. On double-registered inputs, a 10-year MTBF is guaranteed when sampling
asynchronous signals.
Figure 7 illustrates the architecture of input/clock pins. There are
either two or four input/clock pins available, depending on the device selected. Like the input pins, input/clock pins can be combinatorial, registered, double registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The clock
path at the input is user-configurable in polarity. The polarity of
the clock signal can also be controlled by the user. Note that this
I/O MACROCELL
i - -
I
FROM PTM
1/0 CELL
r - - -
en
C
..J
~
I
I
"0"
"1" -,--"--"---------'
C5_ _
C6_ _ _ _ _ _ _ _ _ J
__
---------------------------
,
---------.
BURIED MACROCELL
i - -
FROM PTM
0-16 PRODUCT
TERMS
--------_.,
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
flash370-5
BLOCK RESET
BLOCK PRESET
4 SYSTEM CLOCKS
2 BANK OE TERMS
Figure 5.1/0 and Buried Macrocells
INPUT PIN
TOPIM
FROM CLOCK
POLARITY MUXES
Figure 6. Input Pins
4-221
~~
: . CYPRESS
~
PRELIMINARY
FLASH370
SEMICONDUcroR
TO CLOCK MUX ON
ALL INPUT MACROCELLS
INPUT/CLOCK PIN
... -
-
~~----------~~--------------~I~
-
-
-
-
-
-
---
-
-
-
-..,
I
0
TO CLOCK MUX
I
I
2~tkM~LLS I
L___ ~~~~~~~ _____ J
TOPIM
FROM CLOCK
POLARITY INPUT
CLOCK PINS
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
flash370-7
Figure 7. Input/Clock Pins
polarity is separately controlled for input registers and output registers.
Timing Model
One of the most important features of the FLASH370 family is the
simplicity of its timing. All delays are worst case and system performance is unaffected by the features used or not used on the parts.
Figure 8 illustrates the true timing model for the lOons devices_ For
combinatorial paths, any input to any output incurs a 10-ns worstcase delay regardless ofthe amount oflogic used. For synchronous
systems, the input set-up time to the output macrocells for any input is 7.5 ns and the clock to output time is also 7.5 ns. Again, these
measurements are for any output and clock, regardless of the logic
used.
Stated another way, the FLASH370 features:
•
•
•
•
•
•
•
•
•
no fanout delays
no expander delays
no dedicated vs. I/O pin delays
no additional delay through PIM
no penalty for using 0-16 product terms
no added delay for steering product terms
no added delay for sharing product terms
no routing delays
no output bypass delays
c=J~
Development Software Support
Warp2
Watp2 is a state-of-the-art VHDL compiler for designing with Cypress PLDs and PROMs. Watp2 utilizes a proper subset of IEEE
1076 VHDL as its Hardware Description Language (HDL) for design entry. VHDL provides a number of significant benefits for the
design entry_ VHDL provides a number of significant benefits for
the design engineer. Warp2 accepts VHDL input, synthesizes and
optimizes the entered design, and outputs a JEDEC map for the
desired device. For simulation, Warp2 provides the graphical waveform simulator from the PLD ToolKit.
VHDL (VHSIC Hardware Description Language) is an open,
powerful, non-proprietary language that is astandardfor behavioral design entry and simulation. It is already mandated for use by
the Department of Defense and supported by every major vendor
of CAE tools. VHDL allows designers to learn a signle language
that is useful for all facets of the design process.
Warp3
_________C_O_M_B_IN_A_T_O_R_IA_L_S_IG_N_A_L________
tpD=
The simple timing model of the FLASH370 family eliminates unexpected performance penalties common in other high-density
PLDs.
~c=J
10 ns
REGISTERED SIGNAL
D~--,F1I--------------c=J
~
.u",,,,.,
Warp3 is a sophisticated design tool that is based on the latest version of ViewLogic's CAE design environment. Warp3 features
schematic capture (ViewDraw"'), VHDL waveform simulation
(ViewSim"'), a VHDL debugger, and VHDL synthesis, all integrated in a graphical design environment. Warp3 is available on
PCs using Windows 3.1 or subsequent versions and on Sun workstations.
Third-Party Software
Cypress maintains a very strong commitment to third-party design
software vendors. All major third-party software vendors (indudingABEL'" ,LOG/iC ,CUPL '" ,andMinc)willprovidesupport
for the FLASH370 family of devices. To expedite this support, Cypress supplies vendors with all pertinent architectural information
as well as design fitters for our products_
Th1
Programming
CLOCK
t8 = 7_5 ns
tco = 7.5 ns
Figure 8. Timing Model for CY7C371
QuickPro II
The Wa:p2 package includes the QuickPro II device programmer
from Cypress. QuickPro II will program all Cypress PROMs and
4-222
~
~~PRESS
~, SEMICONDUCTOR
PRELIMINARY
PLDs. QuickPro II is a standalone programmer that connects to
any IBM-compatible PC via the printer port.
FLASH370
Data I/O, Logical Devices, Minato, SMS, and Stag) will support
the FLASH370 family.
Third-Party Programmers
As with development software, Cypress strongly supports thirdparty programmers. Allmajorthird-partyprogrammers (including
Document #: 38-0021S-A
Wmp2, Watp3, FLASH370, and QuickPro II are trademarks of Cypress Semiconductor Corporation.
ViewDraw and ViewSim are trademarks of ViewLogic Corporation.
ABEL is a trademark of Data I/O.
LOG/iC is a trademark of Isdata.
CUPL is a trademark of Logical Devices Inc.
4-223
•
CY7C371
PRELIMINARY
CYPRESS
SEMICONDUCTOR
32-Macrocell Flash PLD
Features
Functional Description
• 32 macrocells in two logic blocks
• 321/0 pins
• 6 dedicated inputs including 2 clock
pins
• No hidden delays
• High speed
-fMAX = 100 MHz
-tpD= 10ns
-ts = 7.5 ns
-teo = 7.5ns
• Electrically alterable Flash
technology
• Available in 44-pin PLCC, CLCC, and
LeC packages
• Pin compatible with the CY7C372
The CY7C371 is a Flash Erasable Programmable Logic Device (EPLD) and is
part of the FLASH37O' family of high-density, high-speed PLDs. Like all members of
the FLASH37O' family, the CY7C371 is designed to bring the ease of use and high
performance of the 22V1O' to high-density
PLDs.
The 32 macrocells in the CY7C371 are divided between two logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH37O' architecture are connected with an extremely
fast and predictable routing resource-the
Programmable Interconnect Matrix
(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH37O' family, the CY7C371 is rich in I/O resources.
Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins
on the CY7C371. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C371 features a very simple timing model. Unlike other high-density PLD architectures, there are no hidden
speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used
or the type of application, the timing parameters on the CY7C371 remain the
same.
Logic Block Diagram
CLOCK
INPUTS
2
INPUT
MACROCELLS
2
PIM
72
72
16
16
16
16
7c371-1
Selection Guide
Maximum Propagation Delay, tpD (ns)
Maximum Operating
Current, ICC2 (rnA)
Maximum Standby
Current, ICCl (rnA)
I
I
Shaded area contams advanced mformation.
Commercial
Military
~t~C3~-l,99c
10 ",;,"
'1\\
;;:, ?
240''''
I::d
•.. ,FY[
..
'
~;
;
7C371-66
7C371-S0
12
15
20'
240'
240'
Ii'::; .",;:260;
"",~;;. ~()O "<:;"r
Commercial
Military
/~;
h.
7C371-83
20'0'
",'
I
4-224
260'
~y:
'w
I
220
260'
200'
220'
I
220'
.
·~PRFSS
SEMICONDUcrOR
PRELIMINARY
_?
Pin Configuration
1/0 5
1/°6
1/0 7
10
11
65432,1,4443424140
39
9
10
CLK1/15
GND
GND
CLKO/1 2
I/Oa
1/09
1/010
1/011
1/027
1/0 26
1/°25
1/°24
13
14
13
31
16
17
29
1819202122232425262728
1/°23
1/°22
1/°21
7c371-2
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370 family. The CY7C371 includes two logic blocks. Each
logic block is constructed of a product term array, a product term
allocator, and 16 macrocells.
Product Term AlTay
The product term array in the FLASH370 logic block includes 36
inputs from the PIM and outputs 86 product terms to the product
term allocator. The 36 inputs from the PIM are available in both
positive and negative polarity, making the overall array size 72x 86.
This large array in each logic block allows for very complex functions to be implemented in a single pass through the device.
CY7C371
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to
increase the effective density of the FLASH370 PLDs. Note that
product term allocation is handled by software and is invisible to
the user.
I/O Macrocell
Each of the macrocells on the CY7C371 has a separate associated
I/O pin. The input to the macrocell is the sum of between 0 and 16
product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the two
logic blocks on the CY7C371 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Design Tools
Development software for the CY7C371 is available from Cypress's Wmp2 TM and Wa1]J3 TM software packages. Both of thse
products are based on the IEEE-standard VHDL language. Cypress also actively supports third-party design tools such as
ABEL 1M, CUPL TM, MINC, and LOG/iC™. Please contact your
local Cypress representative for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - 0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Program Voltage .............................. 12.5V
Output Current into Outputs (LOW) ............... 16 rnA
Static Discharge Voltage. . . . . .. . . . .. .. . ..... .. .. >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Military[l]
Ambient
Temperature
O°Cto +70°C
5V±5%
- 55°C to + 125°C
5V ± 10%
Vee
Electrical Characteristics Over the Operating Rangd 2]
Parameter
Description
Test Conditions
= -3.2 rnA (Com'l/lnd)
IOL = -2.0 rnA (Mil)
IOH = 16 rnA (Com'l/lnd)
IOL = 12 rnA (Mil)
Min.
Max.
Unit
VOH
Output HIGH Voltage
Vee = Min.
VOL
Output LOW Voltage
Vee = Min.
VIR
Input HIGH Voltage
2.0
7.0
V
VIL
Input LOW Voltage
- 0.5
0.8
V
IOH
4-225
2.4
V
V
0.5
V
V
a
en
Q
~
4
.;rl
.-==-,
r
PRELIMINARY
.: CYPREss
CY7C371
SEMICONDUCTOR
Electrical Characteristics Over the Operating Rang~[2] (continued)
Parameter
Min.
Max.
Unit
IIX
Input Load Current
Description
GND~VI~VCC
Test Conditions
-10
+10
loz
Output Leakage Current
GND ~ Vo ~ Vcc, Output Disabled
-50
+50
!LA
!LA
los
Output Short
Circuit Currentl3]
Vcc = Max., VOUT = 0.5V
-30
-90
rnA
ICC2
Power Supply Current
VI = Vcc or GND, f = 40 MHz
Com'l
240
rnA
Mil
260
Com'l
200
Mil
220
Power Supply Current
(Standby)
Icc!
V CC = Max., lOUT = 0 rnA,
f = 0 mHz, VIN = GND, Vcc
rnA
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 2.0Vat f=1 MHz
10
pF
COUT
Output Capacitance
VOUT = 2.0V at f = 1 MHz
12
pF
Notes:
1. TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. VOUT = O.SV has been chosen to avoid test problems caused by tester ground degradation.
4.
2.
AC Test Loads and Waveforms
238Q (GOM'L)
OUTP:~
;n3191
(MIL)
1
35 pF
INCLUDING
JIG AND
SCOPE
I_
-
_
-
OUTP~
TI
238Q (GOM'L)
31
I
170Q (GOM'L)
5 pF
236Q (MIL)
INGLUDING _
JIG AND
SGOPE
(a)
(b)
Tested initially and after any design or process changes that may affect
these parameters.
(COM~~~
. " (MILJ O<~d?-JK=========
J
tWH
t
tWL
}
7c371-6
Latched Output
INPUT
ts
tH
LATCH ENABLE
LATCHED
OUTPUT
~*=
> 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Military[1]
Ambient
Temperature
O°C to +70°C
Vee
5V±5%
- 55°C to + 125°C
5V ± 10%
Note:
1. TA is the "instant on" case temperature.
4-233
II
U)
C
....I
Q.
,:~
• CYPRESS
PRELIMINARY
"'=5!5F ~ SEMICONDUCfOR
CY7C372
Electrical Characteristics Over the Operating Rangel2]
7C372
Parameter
Description
Test Conditions
Output HIGH Voltage
VOH
Min.
Unit
Max.
2.4
IOH = -3.2 rnA (Com'l/Ind)
Vee = Min.
V
IOL = -2.0 rnA (Mil)
Output LOW Voltage
VOL
V
IOH = 16 rnA (Com'l/lnd)
Vee = Min.
0.5
V
IOL = 12 rnA (Mil)
V
7.0
VIH
Input HIGH Voltage
2.0
-0.5
0.8
V
GND~VI~Vee
-10
+10
V
VIL
Input LOW Voltage
IIX
Input Load Current
loz
Output Leakage Current
GND ~ Va ~ Vee, Output Disabled
-50
+50
JAA
JAA
los
Output Short
Circuit Current[3]
Vee = Max., VOUT = 0.5V
-30
-90
rnA
ICC!
Power Supply Current
(Standby)
Vee = Max., lOUT = 0 rnA,
f = 0 mHz, Vn~· = GND, Vee
Com'l
250
rnA
Mil
300
Power Supply Current
VI = Vee or GND, f = 40 MHz
Com'l
280
Mil
330
leC2
rnA
Capacitance[4]
Max.
Unit
CIN
Parameter
Input Capacitance
Description
VIN = 2.0V at f=1 MHz
Test Conditions
10
pF
COUT
Output Capacitance
VOUT = 2.0Vat f = 1 MHz
12
pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation,.
4.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
OUTP~~
TI OUT~: TI
2380 (com'l)
319Q
2380 (com'l)
319Cl
Q
(mU)
35 pF
INCLUDING
JIG AND
SCOPE
I_
_
-
-
1700 (c~m I) ....
5 pF
2360 (mil)
INCLUDING _
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
ALL INPUT PULSES
<~~~)k==========
_JI+----tW---..H-tt4--_____tW_L~}.....---
7c372-6
Latched Output
INPUT
LATCH ENABLE
LATCHED
OUTPUT
vlp~;1
tco~
A
A~--------------~y~~
( )( " I '
,
><
4-236
}II'---
7c372-7
5
;~PRESS
PRELIMINARY
CY7C372
-::::;;;;;;;, SEMICONDUCTOR
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
tlH
tiS
INPUT REGISTER
CLOCK
':1
CLOCK
a
XX~
COMBINATORIAL
OUTPUT
J
tWH
t
tWL
0
Q
}
...I
D.
7c372-8
Input Clock to Output Clock
REGISTERED
INPUT
X
t=,cs~
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
7c372-9
Latched Input
LATCHED INPUT
tlH
tiS
LATCH ENABLE
t1
XX
J
t
tit
XX
P
COMBINATORIAL
OUTPUT
:
tWH
LATCH ENABLE
4-237
tWL
}
7c372-10
~
~~PRE&S
~_., SEMICONDUCTOR
PRELIMINARY
CY7C372
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
LATCHED
OUTPUT
tHL
INPUT LATCH
ENABLE
tiCS
OUTPUT LATCH
ENABLE
LATCH ENABLE
J
tWH
t
tWL
}
70372·11
Asynchronous Reset
tRW
INPUT
REGISTERED
OUTPUT
~RJ
CLOCK
70372·12
Asynchronous Preset
tpw
INPUT
REGISTERED
OUTPUT
'PRJ
CLOCK
70372-13
4-238
~~
g
-==-.,
-
~
PRELIMINARY
CYPRESS
CY7C372
SEMICONDUcroR
Switching Waveforms (continued)
Output EnablelDisable
INPUT
OUTPUTS
7c372·14
I
Ordering Information
Speed
(MHz)
Ordering Code
Package
Name
Package lYPe
Operating
Range
,;J67
44-Lead Plastic Leaded Chip Carrier
Commercial
100
CY1C372-100JC
83
CY7C372-83JC
J67
44-Lead Plastic Leaded Chip Carrier
;eY7a3n::7~LMj
L67
44-Square LeadU~ss Ch~~ ~er
CY7C372-66JC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
CY7C372-66LM
L67
44-Square Leadless Chip Carrier
Military
66
:f \
:, .
Commercial
Military
Shaded areas contam advanced mformatlOn.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VaH
1,2,3
tpD
7, 8, 9, 10, 11
VaL
1,2,3
tpDL
7, 8, 9, 10, 11
VIR
1,2,3
tpDLL
7, 8, 9, 10, 11
VIL
1,2,3
tca
7, 8, 9, 10, 11
IIX
1,2,3
tlca
7, 8, 9, 10, 11
Iaz
1,2,3
tIcaL
7, 8, 9, 10, 11
ICCl
1,2,3
ts
7, 8, 9, 10, 11
ICC2
1,2,3
tSL
7,8,9,10,11
tH
7, 8, 9, 10, 11
tHL
7, 8, 9, 10, 11
tIS
7, 8, 9, 10, 11
tIR
7,8,9,10,11
tICS
7, 8, 9, 10, 11
tEA
7, 8, 9, 10, 11
tER
7, 8, 9, 10, 11
Document #: 38-00213-A
Wa1]J2 and Wa1]J3 are trademarks of Cypress Semiconductor Corporation.
ABEL is a trademark of Data I/O Corporation.
CUPL is a trademark of Logical Devices.
LOG/iC is a trademark of Isdata Corporation.
4-239
en
C
..J
Q.
PRELIMINARY
CYPRESS
SEMICONDUCTOR
64-Macrocell Flash PLD
signed to bring the ease of use and high
performance of the 22V10 to high-density
PLDs.
Features
• 64 macrocells in four logic blocks
• 641/0 pins
• 6 dedicated inputs including 4 clock
pins
• No hidden delays
• High speed
- fMAX = 100 MHz
-tPD = 12 ns
-ts = 9ns
-teo = 9ns
• Electrically alterable Flash
technology
• Available in 84-pin PLCC, CLCC, and
CPGA packages
• Pin compatible with the CY7C374
The 64 macrocells in the CY7C373 are divided between four logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecture are connected with an extremely
fast and predictable routing resource-the
Programmable
Interconnect Matrix
(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH370 family, the CY7C373 is rich in I/O resources.
Every macrocell in the device features an
associated I/O pin, resulting in 64 I/O pins
on the CY7C373. In addition, there are
four dedicated inputs and two input/clock
pins.
Functional Description
The CY7C373 is a Flash Erasable Programmable Logic Device (EPLD) and is
part of the FLASH370 family of high-density, high-speed PLDs. Like all members of
the FLASH370 family, the CY7C373 is de-
CY7C373
Finally, the CY7C373 features a very simple timing model. Unlike other high-density PLD architectures, there are no hidden
speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used
or the type of application, the timing parameters on the CY7C373 remain the
same.
Logic Block
The number of logic blocks distinguishes
the members of the FLASH370 family.
The CY7C373 includes four logic blocks.
Each logic block is constructed of a product term array, a product term allocator,
and 16 macrocells.
Product Term Array
The product term array in the FLASH370
logic block includes 36 inputs from the
PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from
the PIM are available in both positive and
negative polarity, making the overall array
size 72 x 86. This large array in each logic
block allows for very complex functions to
be implemented in single passes through
the device.
CLOCK
INPUTS
Logic Block Diagram
INPUT
MACROCELLS
72
PIM
72
16
16
72
72
16
16
32
32
7C373-1
Selection Guide
7C373-66
Maximum Propagation Delay tpD (ns)
20
Maximum Standby
Current, ICCl (rnA)
Commercial
Military
300
Maximum Operating
Current, ICC2 (mA)
Commercial
280
Military
330
250
Shaded area contains advanced information.
4-240
PRELIMINARY
CY7C373
Pin Configuration
PLCC/CLCC/CQFP
ThpView
1110 9 8 7 6 5 4 3 2
1/°8
1/°9
1/°10
1/°11
1/012
1/013
1/014
1/°15
CLKO/Io
t2.
84838281 80797877 76 75
74
73
72
71
70
69
68
67
66
16
17
18
Vee
GND
GND
1/055
1/054
1/053
1/°52
1/°51
1/050
1/0 49
1/048
CLK3/14
I
GND
Vee
CLK1/11
1/°16
1/°17
1/°18
1/°19
1/0 20
1/021
In
C
CLK2/13
1/047
1/046
1/045
1/044
1/043
1/042
1/041
1/°40
1/°22
1/023
GND
..J
Q.
7C373-2
Functional Description (continued)
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product term resources to macrocells that require them.
Any number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macro cells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to
increase the effective density of the FLASH370 PLDs. Note that
the product term allocator is handled by software and is invisible to
the user.
I/O Macrocell
Each of the macrocells on the CY7C373 has a separate I/O pin assoicated with it. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16
product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed, polarity control
over the input sum-term, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the
PIM so that the register can be buried if the I/O pin is used as an
input.
Programmable Interconnect Matrix
products are based on the IEEE standard VHDL language_
Cypress also supports third-party vendors such as ABEL TM ,
CUPL TM, and LOG/iC™. Please contact your local Cypress
representative for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . .. . .. - 0.5V to + 7.0V
DC Program Voltage .............................. '12.5V
Output Current into Outputs ...................... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ > 200 rnA
Operating Range
Range
Commercial
The Programmable Interconnect Matrix (PIM) connects the four
logic blocks on the CY7C373 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Development Tools
Development software for the CY7C373 is available from Cypress's Warp2™ and Warp3™ software packages. Both of these
Military[lj
Ambient
Temperature
O°C to +70°C
5V±5%
- 55°C to +125°C
5V ± 10%
Note:
1. TA is the "instant on" case temperature.
4-241
Vee
~
~=CYPRESS
PRELIMINARY
~, SEMICONDUCTOR
CY7C373
Electrical Characteristics Over the Operating Rangel2]
7C373
Parameter
Description
Test Conditions
Output HIGH Voltage
VOH
Min.
IOH = -3.2 mA (Com'l/lnd)
Vee = Min.
Max.
Unit
2.4
V
IOL = -2.0 mA (Mil)
V
IOH = 16 mA (Com'l/lnd)
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
2.0
7.0
V
VIL
Input LOW Voltage
-0.5
0.8
V
Vee = Min.
0.5
V
IOL = 12 mA (Mil)
V
IIX
Input Load Current
GND.$. VI.$. Vee
-10
+10
loz
Output Leakage Current
GND .$. V O.$. Vee, Output Disabled
-50
+50
J.I.A
J.I.A
los
Output Short
Circuit Currentl3]
Vee = Max., VOUT = O.SV
-30
-90
mA
leel
Power Supply Current
(Standby)
Vee = Max., lOUT = 0 mA,
f = 0 mHz, VIN = GND, Vee
mA
Power Supply Current
VI = Vee or GND, f = 40 MHz
lecz
Com'l
250
Mil
300
Com'l
280
Mil
330
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
VIN = 2.0V at f= 1 MHz
10
pF
VOUT = 2.0Vat f = 1 MHz
12
pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be tested at a time. Duration ofthe
short circuit should not exceed 1 second. VOUT = O.SV has been chosen to avoid test problems caused by tester ground degradation.
4.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
2380 (COM'L)
5VTI3190(MIL)
OUTPUT
35 pF
OUTPUT
1700 (COM'L)
2360 (MIL)
I
j78~~~NG -=
SCOPE
2380 (COM'L)
5VTI3190(MIL)
-=
ALL INPUT PULSES
3.0V---90%
5 pF
j78~~~NG -=
SCOPE
(a)
GND
I
-= 1700 (COM'L)
2360 (MIL)
(b)
7C373-3
Equivalent to:
THEVENIN EQUIVALENT
990 (COM'L)
1360 (MIL) 2.08V (COM'L)
OUTPUT o-----vw----o 2.13V (MIL)
4-242
7C3734
¥5:~
PRELIMINARY
~~CYPRESS
F SEMICONDUCTOR
CY7C373
Switching Characteristics Over the Operating Range[5]
7073-100
Parameter
7C373-83
7C373-66
,l\1in"" MJlx; Min. Max. Min. Max.
Description
Unit
Combinatorial Mode Parameters
tpD
Input to Combinatorial Output
tpDL
Input to Output Through Transparent Input or Output Latch
'"
ti
:
12
15
20
ns
14 ,.
17
22
ns
ns
tpDLL
Input to Output Through Transparent Input and Output Latches
16
19
24
tEA
Input to Output Enable
16
19
24
ns
16
19
24
ns
Input to Output Disable
tER
Input RegisteredlLatched Mode Parameters
tWL
Clock or Latch Enable Input LOW Time
5
6
8
ns
tWH
Clock or Latch Enable Input HIGH Time
5
6
8
ns
tIS
Input Register or Latch Set-Up Time
2
3
4
ns
tlH
Input Register or Latch Hold Time
2
tlCO
Input Register Clock or Latch Enable to Combinatorial Output
, ;'f ,,,~6
19
24
ns
tlCOL
Input Register Clock or Latch Enable to Output Through 1i"ansparent Output Latch
18
21
26
ns
'
fMAXl
Maximum Frequency of (2) CY7C373s in Input Registered Mode
(Lesser of l/(tICO + tIS) and l/(tWL + tWH»
55.5
fMAX2
Maximum Frequency Data Path in Input Registered/Latched
Mode (Least of l/tICO, l/(tWL + tWH), l/(tIS + tlH»
62.5
4
3
,.:
ns
.. ,::
,..
45.5
35.7
MHz
52.6
41.7
MHz
Output Registered/Latched Mode Parameters
9~
tco
Clock or Latch Enable to Output
ts
Set-Up Time from Input to Clock or Latch Enable
9
tH
Register or Latch Data Hold Time
0
tC02
Output Clock or Latch Enable to Output Delay (Through
Memory Array)
tscs
Output Clock or Latch Enable to Output Clock or Latch Enable
(Through Memory Array)
"
"
12
Set-Up Time from Input Through Transparent Latch to Output
Register Clock or Latch Enable
tHL
Hold Time for Input Through Transparent Latch from Output
Register Clock or Latch Enable
15
12
15
0
0
ns
ns
ns
24
19
16
tSL
ns
12
15
ns
.,' "
1"
~L
15
20
ns
0
0
0
ns
41.7
33.3
MHz
83.3
(j2.5
MHz
83
66
MHz
10
..
;
fMAX3
Maximum Frequency of (2) CY7C373s in Output Registered
Mode (Lesser of l/(tco + ts) and l/(tWL + tWH»
55.5
fMAX4
Maximum Frequency Data Path in Output RegisteredlLatched
Mode (Lesser of l/(tWL + tWH), l/(ts + tH), or l/tco)
100
Maximum Frequency with Internal Feedback in Outfut Registered Mode (Least of l/tscs, l/(ts + tH), or l/tcO)[4
100
fMAX5
J.(,
2'i
i~~, ..,
;
:
Pipelined Mode Parameters
tICS
Input Register Clock to Output Register Clock
fMAX6
Maximum Frequency in Pipelined Mode (Least of l/(tco
l/tICS, l/(tWL + tWH), l/(tIS + tlH), or l/tscs)
12
Shaded area contams advanced mformatlOn.
Note:
5. All AC parameters are measured with 16 outputs switching.
4-243
+ tIS), 83.3
','
15
20
ns
66.6
50.0
MHz
II
U)
Q
..J
a.
~PRRSS
PRELIMINARY
CY7C373
.nEMICONDUcrOR
Switching Characteristics Over the Operating RangelS] (continued) .
7C373-100
Parameter
7C373-83
Min) Max. Min. Max.
Description
7C373-66
Min. Max.
Unit
·W
Reset/Preset Parameters
tRW
Asynchronous Reset Width
12
15
20
tRR
Asynchronous Reset Recovery Time
~~;>,
17
22
tRO
tpw
Asynchronous Reset to Output
Asynchronous Preset Width
tpR
Asynchronous Preset Recovery Time
tpo
Asynchronous Preset to Output
....
12
14
:~8
21
...
26
15
17
;
18
ns
20
ns
22
26
21
ns
ns
ns
ns
Shaded area contams advanced mformatlOn.
Switching Waveforms
Combinatorial Output
INPUT
COMBINATORIAL
OUTPUT
7C373·5
Registered Output
E~ t_Hr______,,--
INPUT
CLOCK
REGISTERED
OUTPUT
CLOCK
1.-:~
--------------------~><~2)k=========
_JI+---.---tW-----.H-t~
______tW_L~}7C373·6
Latched Output
INPUT
LATCH ENABLE
LATCHED
VUlrul
tpDL -..J
teo -1
.
------\(~\(-~----------------~~~~~
()/ "I'
( '(
4-244
)II~
7C373·7
~~
.;CYPRESS
PRELIMINARY
CY7C373
SEMICONDUCTOR
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
tiS
tlH
INPUT REGISTER
CLOCK
':1
CLOCK
a
XX
COMBINATORIAL
OUTPUT
J
tWH
t
tWL
U)
Q
}
..J
£L
7C373-8
Input Clock to Output Clock
REGISTERED
INPUT
X
c,~}
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
7C373-9
Latched Input
LATCHED INPUT
tiS
tlH
LATCH ENABLE
COMBINATORIAL
OUTPUT
LATCH ENABLE
xXt':1
J
tl:~
XX
tWH
t
4-245
tWL
}
7C373-10
~
. :~PRESS
~
PRELIMINARY
SEMITCONDUCTOR
CY7C373
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
LATCHED
OUTPUT
tHL
INPUT LATCH
ENABLE
tiCS
OUTPUT LATCH
ENABLE
LATCH ENABLE
J
tWH
t
Asynchronous Reset
tRw
tWL
}
7C373·11
.
INPUT
REGISTERED
OUTPUT
t RR
CLOCK
J
7C373·12
Asynchronous Preset
tpw
..
INPUT
REGISTERED
OUTPUT
~J
CLOCK
7C373-13
4-246
~PRRSS
_rs~CONDUcrOR
PRELIMINARY
CY7C373
Switching Waveforms (continued)
Output EnablelDisable
INPUT
OUTPUTS
7C373·14
Ordering Information
Speed
(MHz)
Ordering Code
·CY7C373'"t;tt1~C
100
,
Package
1Ype
r
83
66
CY7~73;lOOJC
084
,
Package
1Ype
Operating
Rauge
,
....
' 84-:-POA (Cavity Up)
Commercial
84.Le,a4 Plastic Le~~e~ Chip Carrier
r.J83
CY7C373-83GC
G84
84-PGA (Cavity Up)
CY7C373-83JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7q;~73':"':"83YMB,
,y84
CY7C373-66GC
G84
84-PGA (Cavity Up)
CY7C373-66JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C373-66YMB
Y84
84-Pin Ceramic Leaded Chip Carrier
i
Commercial
84-'~i~ CerariIiC:1.:eaded Chip
Carrier '
Military
Commercial
Military
Shaded areas con tam advanced mformatlOn.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Switching Characteristics
Subgroups
Parameter
Subgroups
VOH
.. 1,2,3
tpD
7, 8, 9, 10, 11
VOL
1,2,3
tpDL
7, 8, 9, 10, 11
VIH
1,2,3
tpDLL
7, 8, 9, 10, 11
VIL
1,2,3
tco
7, 8, 9, 10, 11
Ilx
1,2,3
tlCO
7,8,9,10,11
Ioz
1,2,3
tlCOL
7, 8, 9, 10, 11
ICC!
1,2,3
ts
7, 8, 9, 10, 11
ICC2
1,2,3
tSL
7, 8, 9, 10, 11
tH
7, 8, 9, 10, 11
tHL
7, 8, 9, 10, 11
tIS
7,8,9,10,11
tIH
7, 8, 9, 10, 11
tICS
7, 8, 9, 10, 11
tEA
7,8,9,10, 11
tER
7, 8, 9, 10, 11
Document #: 38-00216-A
Walp2 and Wa1p3 are trademarks of Cypress Semiconductor Corporation.
ABEL is a trademark of Data IJOCorporation.
LOG/iC is a trademark of Isdata Corporation.
CUPL is a trademark of Logical Devices, Inc.
4-247
I
CY7C374
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• 128 macrocells in eight logic blocks
• 641/0 pins
• 6 dedicated inputs including 4 clock
pins
• No hidden delays
• High speed
- fMAX = 100 MHz
-tpD = 12 ns
-ts = 9ns
-teo = 9ns
• Electrically Alterable Flash
technology
• Available in 84-pin PLCC, CLCC, and
CPGA packages
• Pin compatible with the CY7C373
Functional Description
The CY7C374 is a Flash Erasable Programmable Logic Device (EPLD) and is
part of the FLASH370 family of high-density, high-speed PLDs. Like all members of
the FLASH370 family, the CY7C374 is de-
128-Macrocell Flash PLD
signed to bring the ease of use and high
performance of the 22VlO to high-density
PLDs.
The 128 macrocells in the CY7C374 are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86
product· term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecture are connected with an extremely
fast and predictable routing resource-the
Programmable Interconnect Matrix
(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH370 family, the CY7C374 is rich in I/O resources.
Every two macrocells in the device feature
an associated I/O pin, resulting in 64 I/O
pins on.the CY7C374. In addition, there
are four dedicated inputs and two input/
clock pins.
Finally, the CY7C374 features a very simple timing model. Unlike other high-density PLD architectures, there are no hidden
speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used
or the type of application, the timing parameters on the CY7C374 remain the
same.
Logic Block
The number of logic blocks distinguishes
the members of the FLASH370 family.
The CY7C374 includes eight logic blocks.
Each logic block is constructed of a product term array, a product term allocator,
and 16 macrocells.
Product Term Array
The product term array in the FLASH370
logic block includes 36 inputs from the
PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from
the PIM are available in both positive and
negative polarity, making the overall array
size 72 x 86. This large array in each logic
block allows for very complex functions to
be implemented in single passes through
the device.
Logic Block Diagram
81/0s
72
16
PIM
72
16
81/0s
81/0s
72
16
81/0s
81/0s
72
16
7C374-1
32
32
Selection Guide
:
Maximum Propagation Delay tpD (ns)
Maximum Standby
Current, ICCl (rnA)
Maximum Operating
Current, ICC2 (rnA)
7C374-1QO.
l '. ,.
"
15
20
300
300
370
370
330
iA;t\ .MIA'.
,-.., .i"-
330
.......
-.t
400
T' iFi~PRESS
SEMlCONDUcrOR
PRELIMINARY
~
Pin Configurations
PGA
Bottom View
PLCC/CLCC
Top View
K
I/O
I/O
I/O
I/O
I/O
I/O
23
25
26
28
31
33
I/O
GND
12
21
1/08
1/°9
1/°10
1/°11
1/°12
1/°13
1/°14
1/0 15
ClKO/lo
Vee
GND
ClK1/11
1/°16
1/°17
1/0 18
1/°19
1/020
1/0 21
1/°22
1/°23
CY7C374
12
13
14
15
16
17
18
19
20
21
22
23
GND
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
GND
I/O
20
1/055
1/054
1/053
H I/O
18
1/052
1/°51
ClK1
1/050
G
/11
1/0 49
1/048
ClK3/1 4 F I/O
17
GND
I/O
I/O
I/O
24
27
30
I/O
I/O
22
29
Vee
Vee
I/O
I/O
I/O
I/O
34
36
37
39
GND
I/O
I/O
I/O
I/O
I/O
I/O
32
35
38
GND
I/O
19
41
40
42
I/O
I/O
43
44
GND
ClK2
/13
I/O
I/O
46
47
ClKO
/10
Vee
Vee
I/O
45
GND
I/O
I/O
I/O
14
15
13
49
Vee
48
ClK3
/14
I/O
I/O
I/O
I/O
I/O
16
U)
Vee
ClK2/13 E
1/047
1/048
1/045
D
1/044
1/043
C
1/042
1/041
1/°40
I/O
12
11
I/O
I/O
10
8
I/O
GND
9
A
•
I/O
Vee
15
1
52
I/O
56
53
I/O
I/O
I/O
I/O
I/O
6
3
0
61
63
59
I/O
I/O
I/O
I/O
7
5
4
2
Vee
GND
50
I/O
54
I/O
7C374·3
51
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/o
62
60
58
57
55
10
11
7C374·2
Functional Description (continued)
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to
increase the effective density of the FLASH370 PLDs. Note that
product term allocation is handled by software and is invisible to
the user.
I/O Macrocell
Half of the macrocells on the CY7C374 have I/O pins associated
with them. The input to the macrocell is the sum of between 0 and
16 product terms from the product term allocator. The I/O macrocell includes a register that can be optionally bypassed, polarity
control over the input sum-term, and two global clocks to trigger
the register. The macrocell also features a separate feedback path
to the PIM so that the register can be buried if the I/O pin is used
as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell. Again, it
includes a register that can be configured as combinatorial as a D
flip-flop, a T flip-flop, or a latch. The clock for this register has the
same options as described for the I/O macrocell. One difference on
the buried macrocell is the addition of input register capability.
The user can program the buried macrocell to act as an input register whose input comes from the I/O pin associated with the neigh-
boring macrocell. The ouptut of all buried macrocells is sent directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the eight
logic blocks on the CY7C374 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Development Tools
Development software for the CY7C374 is available from Cypress's Wmp21M and Wmp3 1M software packages. Both of these
products are based on the IEEE standard VHDL language. Cypress also supports third-party vendors such as ABEL 1M, CUPL 1M ,
and LOG/iC 1M. Please contact your local Cypress representative
for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential ..... , .. - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Program Voltage .............................. 12.5V
Output Current into Outputs ...................... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
4-249
a
Q
..J
D.
·
j~pRF.SS
PRELIMINARY
~IF SEMICONDUCTOR
CY7C374
Operating Range
Range
Commercial
Military[l]
Ambient
Temperature
O°Cto +70°C
SV±S%
- SsoC to + 12SoC
SV ± 10%
Vee
Electrical Characteristics Over the Operating Range[2]
7C374
Description
Parameter
Output HIGH Voltage
VOH
Min.
Test Conditions
Unit
Max.
2.4
IOH = -3.2 rnA (Com'l/lnd)
Vee = Min.
V
IOL = -2.0 rnA (Mil)
Output LOW Voltage
VOL
V
O.S
IOH = 16 rnA (Com'l/Ind)
Vee = Min.
V
V
IOL = 12 rnA (Mil)
VIH
Input HIGH Voltage
2.0
7.0
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND5VI5 V ee
-0.5
-10
+10
!lA
loz
Output Leakage Current
GND 5 Vo 5 Vee, Output Disabled
-SO
+SO
!!A
los
Output Short
Circuit Current[3]
Vee:::;; Max., VOUT = O.5V
-30
-90
rnA
leCl
Power Supply Current
(Standby)
Vee = Max., lOUT = 0 rnA,
f = 0 mHz, VIN = GND, Vee
Com'l
300
rnA
Mil
370
Power Supply Current
VI = Vee or GND, f = 40 MHz
leC2
Com'l
330
Mil
400
V
rnA
Capacitance[4]
Max.
Unit
CIN
Input Capacitance
VIN = 2.0V at f=1 MHz
10
pF
COUT
Output Capacitance
VOUT = 2.0Vat f = 1 MHz
12
pF
Description
Parameter
Test Conditions
Notes:
1.
2.
3.
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. VOUT = O.5V has been chosen to avoid test problems caused by tester ground degradation.
AC Test Loads and Waveforms
238Q (COM'L)
OUTP~~ ~319Q
(MIL)
35 pF
INCLUDING
JIG AND
SCOPE
I-=
Tested initially and after any design or process changes that may affect
these parameters.
238Q (COM'L)
OUTP~~
170Q (COM'L)
-=
sn
4.
31
9<~~~Jk==========
J
tWH
t
tWL
}
7C374-7
Latched Output
INPUT
t8
tH
LATCH ENABLE
tPOL
L~TCHED
OUTPUT
;j
~i-
<::;<:: ; , /
)\)\If\
\7\:/
A A
4-252
A--
7C374-8
fbn~
_
PRELIMINARY
CY7C374
SEMICONDUCTOR
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
tiS
tlH
INPUT REGISTER
CLOCK
1':1
CLOCK
I
XX~
COMBINATORIAL
OUTPUT
J
tWH
t
tWL
U)
c
}
...J
D.
7C374-9
Input Clock to Output Clock
REGISTERED
INPUT
X
t=I'CS~
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
7C374-10
Latched Input
LATCHED INPUT
tlH
tiS
LATCH ENABLE
COMBINATORIAL
OUTPUT
LATCH ENABLE
1':1=
xX~1
J
XX
tWH
t
4-253
tWL
}
7C374-11
PRELIMINARY
CY7C374
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
LATCHED
OUTPUT
tHL
INPUT LATCH
ENABLE
tiCS
OUTPUT LATCH
ENABLE
LATCH ENABLE
J
tWH
t
tWL
}
7C374-12
Asynchronous Reset
tRW
II
INPUT
REGISTERED
OUTPUT
'RR J
CLOCK
7C374-13
Asynchronous Preset
tpw
.
INPUT
REGISTERED
OUTPUT
~RJ
CLOCK
7C374-14
4-254
~
~~PRESS
. . .'
PRELIMINARY
~ICONDUcrOR
CY7C374
Switching Waveforms (contimied)
Output Enable/Disable
INPUT
OUTPUTS
7C374-15
Ordering Information
Speed
(MHz)
100
!
83
66
Package
Name
Ordering Code
CY7C374'7'" iOOGC
.~; Cr7C37f~\1!10JC
084
....•. ~
Package 'JYpe
84-POA (Cavity J)p)
Operating
Range
Commercial
J$3,,: • '.: 84~~.~ad Plasii~Leaded ~pC1:lrri~r
(.
';n
CY7C374-83GC
G84
84-PGA (Cavity Up)
CY7C374-83JC
J83
84-Lead Plastic Leaded Chip Carrier
Commercial
CY7C374-'83y¥~
'Y84
,84-Pin CerilmicLeaaedChip Carrier
Military
CY7C374-66GC
G84
84-PGA (Cavity Up)
Commercial
CY7C374-66JC
J83
84-Lead Plastic Leaded Chip Carrier
CY7C374-66YMB
Y84
84-Pin Ceramic Leaded Chip Carrier
Military
Shaded areas contam advanced mformatlon.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
tpD
7, 8, 9, 10, 11
VOL
1,2,3
tpDL
7, 8, 9, 10, 11
VIH
1,2,3
tpDLL
7, 8, 9, 10,11
VIL
1,2,3
tco
7,8,9,10,11
7, 8, 9, 10, 11
IIX
1,2,3
tICO
Ioz
1,2,3
tICOL
7, 8, 9, 10, 11
ICCl
1,2,3
ts
7,8,9,10,11
ICC2
1,2,3
tSL
7, 8, 9, 10, 11
tH
7, 8, 9, 10, 11
tHL
7, 8, 9, 10, 11
tIS
7, 8, 9, 10, 11
tIH
7, 8, 9, 10, 11
tICS
7, 8, 9, 10, 11
tEA
7, 8, 9, 10, 11
tER
7, 8, 9, 10, 11
Document #: 38-00214-A
Wa1]J2 and Wa1]J3 are trademarks of Cypress Semiconductor Corporation.
ABEL is a trademark of Data I/O Corporation.
LOG/iC is a trademark of Isdata Corporation.
CUPL is a trademark of Logical Devices, Inc.
4-255
•
II)
Q
..J
D.
PRELIMINARY
CY7C375
128-Macrocell Flash PLD
(PIM). The PIM brings flexibility, routFunctional Description
ability, speed, and a uniform delay to the
The CY7C375 is a Flash Erasable Pro- interconnect.
grammable Logic Device (EPLD) and is
part of the FLASH370 family of high-den- Like all members of the FLASH370 famisity, high-speed PLDs. Like all members of ly, the CY7C375 is rich in I/O resources.
the FLASH370 family, the CY7C375 is de- Every macrocell in the device features an
signed to bring the ease of use and high associated I/O pin, resulting in 128 I/O
performance of the 22V10 to high-density pins on the CY7C375. In addition, there
are four dedicated inputs and two input/
PLDs.
clock pins.
The 128macrocellsintheCY7C375aredivided between eight logic blocks. Each log- Finally, the CY7C375 features a very simic block includes 16 macrocells, a 72 x 86 ple timing model. Unlike other high-densiproduct term array, and an intelligent ty PLD architectures, there are no hidden
speed delays such as fanout effects, interproduct term allocator.
connect delays, or expander delays. ReThe logic blocks in the FLASH370 archi- gardless of the number of resources used
tecture are connected with an extremely . or the type of application, the timing pafast and predictable routing resource-the rameters. on the CY7C375 remain the
Programmable
Interconnect Matrix same.
Features
• 128 macrocells in eight logic blocks
• 128 I/O pins
• 6 dedicated inputs including 4 clock
pins
• No hidden delays
• High speed
-fMAX = 100 MHz
-tpD = 12 ns
-ts = 9 ns
-tco = 9ns
• Electrically alterable FLASH
technology
• Available in 160-pin PQFP and CPGA
packages
Logic Block Diagram
CLOCK
INPUTS
72
72
16
PIM
16
72
72
16
16
72
72
16
16
72
72
16
16
64
64
7C375-1
Selection Guide
7C375-66
Maximum Propagation Delay (ns)
Maximum Standby
Current, ICCl (rnA)
20
Commercial
300
Military
370
Commercial
330
Military
400
Shaded area contains advanced information.
4-256
ppz
;~PRESS
PRELIMINARY
CY7C375
_ , SEMICONDUCTOR
Pin Configuration
Ceramic Quad Flatpack (CQFP)
Top View
a
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
en
C
...I
Q.
101
7C375-2
4-257
-=-,
~
~::~PRESS
PRELIMINARY
~kCONDUcrOR.
Functional Description (continued)
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370 family. The CY7C375 includes eight logic blocks.
Each logic block is constructed of a product term array, a product
term allocator, and 16 macrocells.
CY7C375
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Development Tools
Development software for the CY7C375 is available from Cypress's Wa7p2 1M and Warp3 1M software packages. Both of these
products are based on the IEEE standard VHDL language. Cypress also supports third-party vendors such as ABEL CUPL
and LOG/iC
Please contact your local Cypress representative
for further information.
1M,
Product Term AlTay
1M ,
1M.
The product term array in the FLASH370 logic block includes 36
inputs from the PIM and outputs 86 product terms to the product
term allocator. The 36 inputs from the PIM are available in both
positive and negative polarity, making the overall array size 72 x 86.
This large array in each logic block allows for very complex functions to be implemented in single passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Prqduct term steering and product term sharing help to
increase the effective density of the FLASH370 PLDs. Note that
product term allocation is handled by software and is invisible to
the user.
I/O Macrocell
Each of the macrocells on the CY7C375 has a separate I/O pin
associated with it. The input to the macrocell is the sum of between
oand 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed, polarity
control over the input sum-term, and four global clocks to trigger
the register. The macrocell also features a separate feedback path
to the PIM so that the register can be buried if the I/O pin is used
as an input.
Programmable Interconnect Matrix
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... - 55°C to + 125°C
Supply Voltage to Ground Potential ........ - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage ....................... - O.5V to +7.0V
DC Program Voltage .............................. 12.5V
Output Current into Outputs ...................... 16 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Range
Commercial
Military[l]
Ambient
Temperature
O°C to +70°C
5V±5%
- 55°C to + 125°C
5V ± 10%
Note:
1. TA is the "instant on" case temperature.
The Programmable Interconnect Matrix (PIM) connects the eight
logic blocks on the CY7C375 to the inputs and to each other. All
4-258
Vee
-=m:~
'jE
PRELIMINARY
CYPRESS
CY7C375
_ . ' SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangd 2)
7C375
Parameter
Description
Test Conditions
Output HIGH Voltage
VOH
Vee
= Min.
Min.
Max.
Unit
2.4
IOH = -3.2 rnA (Com'l/lnd)
V
V
IOL = -2.0 rnA (Mil)
Output LOW Voltage
VOL
IOH = 16 rnA (Com'l/lnd)
Vee = Min.
0.5
V
V
IOL = 12 rnA (Mil)
VIH
Input HIGH Voltage
2.0
7.0
VIL
Input LOW Voltage
-0.5
0.8
V
Ilx
Input Load Current
GND~VI~Vee
-10
+10
!-lA
I
loz
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
-50
+50
(..lA
C
los
Output Short
Circuit Current[3)
Vee = Max., VOUT = 0.5V
-30
-90
rnA
Q.
leC!
Power Supply Current
(Standby)
Vee = Max., lOUT = 0 rnA,
f = 0 mHz, VIN = GND, Vee
Com'l
300
rnA
Mil
370
Power Supply Current
VI = Vee or GND, f = 40 MHz
lee2
Com'l
330
Mil
400
V
rnA
Capacitance[4)
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 2.0V at f=1 MHz
10
pF
COUT
Output Capacitance
VOUT = 2.0Vat f = 1 MHz
12
pF
Notes:
2.
3.
See the last page ofthis specification for Group A subgroup testing information.
Not more than one output should be tested at a time. Duration of the
short circuit should not exceed 1 second. VOUT = O.SV has been chosen to avoid test problems caused by tester ground degradation.
AC Test Loads and Waveforms
238Q (COM'L)
5V
~319Q
(MIL)
OUTPUT
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
J
-
(a)
170Q (COM'L)
_
sn
238Q (COM'L)
319Q
(MIL)
Tested initially and after any design or process changes that may affect
these parameters.
3.0V
J
INCLUDING JIG AND
SCOPE
(b)
ALL INPUT PULSES
90%
170Q (COM'L)
5 pF
236Q (MIL)
-
4.
236Q (MIL) GND
_
.$. 2 ns
-
7C375·3
Equivalent to:
THEVENIN EQUIVALENT
99Q (COM'L)
136Q (MIL) 2.08V (COM'L)
OUTPUT o--------vvv--- 2.13V (MIL)
4-259
7C375-4
en
....I
~
~~PRESS
~, SEMICONDUcrOR
PRELIMINARY
CY7C375
Switching Characteristics Over the Operating Range[S]
7C375~100
7C37S-83
7C37S-66
Min. Max. Min. Max. Min. Max.
Description
Parameter
Unit
Combinatorial Mode Parameters
tpD
Input to Combinatorial Output
tPDL
Input to Output Through Transparent Input or Output Latch
tpDLL
Input to Output Through Transparent Input and Output Latches
tEA
Input to Output Enable
; 12
,l'
ns
22
ns
1.6
19
24
ns
1'6:",
19
24
ns
16,
19
24
ns
SiX T;~~!,
"f\;~
I'
~:
'5"r"
,$,
tWH
Clock or Latch Enable Input HIGH Time
tIS
Input Register or Latch Set-Up Time
tIH
Input Register or Latch Hold Time
1,'2:;fi,I"
tlCO
Input Register Clock or Latch Enable to Combinatorial Output
i
tICaL
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
fMAX!
Maximum Frequency of (2) CY7C375s in In~ut Registered Mode }5.5. I~
(Lesser of 1/(tlco + tIS) and l/(tWL + tWH)
',"
Maximum Frequency Data Path in Inf,ut Registered/Latched
62.5
!
I>
Mode (Least of l/tICO, l/(tWL + tWH , 1/(tIS + tIH»
'
fMAX2
20
';,)
I
Input to Output Disable
tER
Input Registered/Latched Mode Parameters
Clock or Latch Enable Input LOW Time
tWL
15
17
,&,,"",ce',,
2,;1
,:;
":P,
6
8
ns
6
8
ns
3
4
ns
3
4
ns
'\ lij
19
24
ns
"18'
21
26
ns
\,
45.5
35.7
MHz
52.6
41.7
MHz
"
Output Registered/Latched Mode Parameters
tco
Clock or Latch Enable to Output
ts
Set-Up Time from Input to Clock or Latch Enable
tH
Register or Latch Data Hold Time
tC02
Output Clock or Latch Enable to Output Delay (Through
Memory Array)
tscs
Output Clock or Latch Enable to Output Clock or Latch Enable
(Through Memory Array)
I;'
I,::~:~
0
I"'k':
'"
i)~;(k:
Hold Time for Input Through Transparent Latch from Output
Register Clock or Latch Enable
:;9 ; I,ii:t;~,
Maximum Frequency of (2) CY7C375s in Output Registered
Mode (Lesser of l/(tco + ts) and l/(tWL + tWH»
55.5
fMAX4
Maximum Frequency Data Path in Output Registered/Latched
Mode (Lesser of l/(twL + tWH), l/(ts + tH), or l/tco)
IJ~~~4
fMAXS
Maximum Frequency with Internal Feedback in Outfut Registered Mode (Least of 1/tscs, l/(ts + tH), or 1/tco)[4
100
fMAX3
Pipelined Mode Parameters
Input Register Clock to Output Register Clock
tICS
fMAX6
Shaded area contams advanced mformatlOn.
Note:
5. All AC parameters are measured with 16 outputs switching.
4-260
0
ns
ns
24
ns
12
15
ns
15
20
ns
0
0
ns
41.7
33.3
MHz
83.3
62.5
MHz
83
66
MHz
"
~;"A
,:i;;«
t;~;:;
)}i:
"S'(,{~
)21,\\,
Maximum Frequency in Pipelined Mode (Least of l/(tco
l/tICS, 1/(tWL + tWH), l/(tIS + tIH), or l/tscs)
0
ns
,:
12
tHL
15
19
It:
"
15
12
16
\';:\,
Set-Up Time from Input Through Transparent Latch to Output
Register Clock or Latch Enable
tSL
12
'I'> 9'
,94
+ tIS), ,ff!3.3~1 f~
"cecece
;;;
15
20
ns
66.6
50.0
MHz
R&
;~PRFSS
-====r'
PRELIMINARY
CY7C375
SEMICONDUCTOR
Switching Characteristics Over the Operating RangdS] (continued)
7C37S-100
Parameter
Min.
Description
Reset/Preset Parameters
Asynchronous Reset Width
tRW
Asynchronous Reset Recovery Time
tRR
Asynchronous Reset to Output
tRO
Asynchronous Preset Width
tpw
Asynchronous Preset Recovery Time
tpR
Asynchronous Preset to Output
tpo
7C37S-83
12
14
15
20
17
22
.~
<,
15
22
21
18
ns
20
17
14
Unit
ns
26
21
18
12··
7C37S-66
Max. Min. Max. Min. Max.
ns
ns
ns
26
ns
Shaded area contams advanced mformatlOn.
en
Switching Waveforms
Q
..J
D.
Combinatorial Output
INPUT
COMBINATORIAL
OUTPUT
______t~~x~x~zx~xi-----
7C37S-S
Registered Output
E~ t_Hr---.....,,---
INPUT
CLOCK
REGISTERED
OUTPUT
CLOCK
1-:~
---------------------->e~~~Jk==========
J
tWH
t
tWL
}
7C37S-6
Latched Output
INPUT
ts
tH
t:*=
LATCH ENABLE
LATCHED
OUTPUT
a
>eX
~:*
>eX
4-261
7C37S-7
~
I
~~PRFSS
PRELIMINARY
.S' SEMICONDUcrOR
CY7C375
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
tlH
tiS
INPUT REGISTER
CLOCK
1':1
XX
COMBINATORIAL
OUTPUT
CLOCK
J
tWH
t
tWL
}
7C375-8
Input Clock to Output Clock
REGISTERED
INPUT
X
t=I'~J
INPUT REGISTER
CLOCK
OUTPUT
REGISTER CLOCK
7C375-9
Latched Input
LATCHED INPUT
tiS
tlH
LATCH ENABLE
COMBINATORIAL
OUTPUT
LATCH ENABLE
1':1
't
XX
J
XX
tWH
t
4-262
tWL
}
7C375-10
5~PRFSS
PRELIMINARY
_ , SEMICONDUCTOR
CY7C375
Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
LATCHED
OUTPUT
I
tHL
INPUT LATCH
ENABLE
en
Q
tiCS
..J
a.
OUTPUT LATCH
ENABLE
LATCH ENABLE
J
tWH
t
tWL
}
7C375-11
Asynchronous Reset
tRW
II
INPUT
REGISTERED
OUTPUT
'""J
CLOCK
7C375-12
Asynchronous Preset
tpw
II
INPUT
REGISTERED
OUTPUT
'PRJ
CLOCK
7C375-13
4-263
~
= .. . ~
PRELIMINARY
~"CYPRESS
~, SEMICONDUCTOR
CY7C375
Switching Waveforms (continued)
Output EnableIDisable
INPUT
OUTPUTS
7C375-14
Ordering Information
Speed
(MHz)
Ordering Code
Package
Name
Operating
Range
Package 1YPe
100
CY7C375 -loqNC
N160
160·Lead PQFP
Commercial
83
CY7C375-83NC
N160
160-Lead PQFP
Commercial
CY7C375 -83GMB
G160
160:-Pll1:pG~ ,.
CY7C375-66NC
N160
160-Lead PQFP
Commercial
CY7C375 -660MB
0160
160-PinPOA
Military
66
0·"
:.
i,' ~litary
Shaded areas contam advanced mformatlOn.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1,2,3
tpD
7,8,9,10,11
VOL
1,2,3
tpDL
7, 8, 9, 10, 11
VIH
1,2,3
tpDLL
7, 8, 9, 10, 11
VIL
1,2,3
tco
7,8,9, 10, 11
IIX
1,2,3
tICO
7, 8, 9, 10, 11
Ioz
1,2,3
tICOL
7,8, 9, 10, 11
ICCl
1,2,3
ts
7, 8, 9, 10, 11
ICC2
1,2,3
tSL
7, 8, 9, 10, 11
tH
7, 8, 9, 10, 11
Document #: 38-00217-A
4-264
tHL
7, 8, 9, 10, 11
tIS
7,8,9, 10, 11
tIH
7, 8, 9, 10, 11
tICS
7,8,9,10,11
tEA
7,8,9,10,11
tER
7,8, 9, 10, 11
CY7C376
ADVANCED INFORMATION
256-Macrocell Flash PLD
Features
Functional Description
• 256 macrocells in 16 logic blocks
• 128 I/O pins
• 6 dedicated inpnts including 4 clock
pins
• No hidden delays
• High speed
-tpD = 15 ns
-ts = 12 ns
-teo = 12ns
• Electrically alterable Flash
technology
• Available in 160-pin PGA and PQFP
packages
• Pin compatible with the CY7C375
The CY7C376 is a Flash Erasable Programmable Logic Device (EPLD) and is
part of the FLASH370 family of high-density, high-speed PLDs. Like all members of
the FLASH370 family, the CY7C376 is designed to bring the ease of use and high
performance of the 22V10 to high-density
PLDs.
The 256 macrocells in the CY7C376 are divided between sixteen logic blocks. Each
logic block includes 16 macro cells, a 72 x
86 product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecture are connected with an extremely
fast and predictable routing resourcethe Programmable Interconnect Matrix
Logic Block Diagram
(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH370 family, the CY7C376 is rich in I/O resources.
Every two macrocells in the device feature
an associated I/O pin, resulting in 128 I/O
pins on the CY7C376. In addition, there
are two dedicated inputs and four input/
clock pins.
Finally, the CY7C376 features a very simple timing model. Unlike other high-density PLD architectures, there are no hidden
speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used
or the type of application, the timing parameters on the CY7C376 remain the
same.
CLOCK
INPUTS
72
16
72
16
72
16
72
16
72
PIM
16
72
16
72
16
161/05
72
16
64
64
Document #: 38-00225
4-265
7C376-1
4
In
C
..J
Q.
ADVANCED INFORMATION
CY7C377
256-Macrocell Flash PLD
Features
Functional DeSCription
• 256 macrocells in 16 logic blocks
• 256 I/O pins
• 6 dedicated inpnts inclnding 4 clock
pins
• No hidden delays
• High speed
-tpD = 15 ns
-ts = 12ns
-teo = 12 ns
• Electrically alterable Flash
technology
• Available in 288-pin PGA and PQFP
packages
The CY7C377 is a Flash Erasable Programmable Logic Device (EPLD) and is
part of the FLASH370 family of high-density, high-speed PLDs.Like all members of
the FLASH370 family, the CY7C377 is designed to bring the ease of use and high
performance ofthe 22VlO to high-density
PLDs.
The 256 macrocells in the CY7C377 are divided between sixteen logic blocks. Each
logic block includes 16 macrocells, a 72 x
86 product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecture are connected with an extremely
fast and predictable routing'resource-the
Programmable Interconnect Matrix
(PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH370 family, the CY7C377 is rich in I/O resources.
Every macrocell in the device features an
associated I/O pin, resulting in 256 I/O
pins on the CY7C377. In addition, there
are two dedicated inputs and four input/
clock pins.
Finally, the CY7C377 features a very simple timing model. Unlike other high-density PLD architectures, there are no hidden
speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used
or the type of application, the timing parameters on the CY7C377 remain the
same.
Logic Block Diagram
72
16
72
16
72
16
72
16
72
16
PIM
72
16
72
16
72
16
128
128
Document #: 38-00226
4-266
7C377-1
PRELIMINARY
pASIC380®
Family
Very High Speed
CMOS FPGAs
Features
• Very high speed
- Loadable counter frequencies
greater than 100 MHz
- Chip-to-chip operating frequencies
up to 85 MHz
- Input + logic cell + output delays
under 9 ns
• High usable density
- Up to 4,000 "gate array" gates,
equivalent to 12,000 EPLD or LCA
gates
- Technology migration path to
20,000 gates and above
• Low power, high output drive
- Standby current typically 2 rnA
-16-bit counter operating at 100
MHz consumes 50 rnA
- Minimum IOL and IOH of 8 rnA
• Flexible FPGA architecture
- Wide fan-in (up to 14 input gates)
- Multiple outputs in each cell
- Very low cell propagation delay
(3.4 ns)
• Low-cost, easy-to-use design tools
- Designs entered in VHDL, schematics, or both
- Fast, fully automatic place and
route
- Waveform simulation with back
annotated net delays
- PC and workstation platforms
• Robust routing resources
- Fully automatic place and route of
designs using up to 100 percent of
logic resources
• Input hysteresis provides high noise
immunity
• Thorough testability
- Built-in scan path permits 100 percent factory testing of logic and I/O
cells
- Automatic Test Vector Generation
(ATVG) software supports user
testing after programming
• CMOS process with ViaLink@) programming technology
- High-speed metal-to-metallink
- Non-volatile antifuse technology
consuming a fraction of the power and
board area of PALs@), GALs@), and discrete logic elements.
pASIC380 Family devices range in density
from 1000 "gate array" gates (3,000
EPLDILCA gates) in 44- and 68-pin packages to 4,000 (12,000) gates in 84- and 144pin packages.
All devices share a common architecture and CAE design software to allow
easy transfer of designs from one product
The pASIC380 family of very high speed
CMOS user-programmable ASIC devices
is based on the first FPGA technology to
combine high speed, high density, and low
power in a single architecture.
All pASIC380 family devices are based on
an array of highly flexible logic cells that
have been optimized for efficient implementation of high-speed arithmetic,
counter, data path, state machine, and
glue logic functions. Logic cells are configured and interconnected by rows and
columns of routing metal lines and ViaLink metal-to-metal programmable-via interconnect elements.
ViaLink technology provides a non-volatile, permanently programmed custom logic function capable of operating at speeds
of over 100 MHz. Internal logic cell delays
are under 4 ns and total input to output
combinatorial logic delays are under 10 ns.
This permits high-density programmable
devices to be used with today's fastest
CISC and RISC microprocessors, while
Designs are entered into the pASIC380
Family devices on PC or workstation platforms using third-party, general-purpose
design-entry and simulation CAE packages, together with Cypress device-specific
place and route and programming tools.
Sufficient on-chip routing channels are
provided to allow fully automatic place and
route of desings using up to 100 percent of
the available logic cells.
All the necessary hardware, software, documentation and accessories required to
complete a design, from entering a schematic to programming a device are included in Wa1p3@), available from Cypress.
Warp3 includes a schematic capture system
together with a waveform-based timing
simulator. In addition to schematic entry,
users can describe designs using VHDL.
All applications run under Microsoft Windows@) graphical user interface to insure a
highly productive and easy-to-use design
environment. Sun workstation and other
UNIX platforms will also be available.
pASIC380 Family Members
Gate Count ~~
(in thousands)
12
4
-I-
9
3
-I-
6
2
-f-
3
EPLD Gate
LeA Array
CY7C385A CY7C386A
CY7C383
-f-
•
•
CY7C384
• •
CY7C~81 • CY7C382
I
40
I
I
I
80
120
160
Number of Package Pins
4-267
(I)
~~;;~~:i~h:r:::::~t ~~:u~!;~~e~~~~~~ ~
gy migration path to devices of 20,000
gates or more.
Functional Description
•
.-
0380-1
~.
-~
PRELIMINARY
: CYPRESS
_
.
pASIC380
Family
SEMICONDUCTOR
0380-3
0380-2
Figure 1. Unprogrammed ViaLink Element
Figure 2. Programmed ViaLink Element
ViaLink Programming Element
Programmable devices implement customer-defined logic functions by interconnecting user-configurable logic cells through a variety of semiconductor switching elements. The maximum speed of
operation is determined by the effective impedance ofthe switch in
both programmed, ON, and unprogrammed, OFF, states.
In pASIC380 devices, the switch is called a ViaLink element. The
ViaLink element is an antifuse formed in a via between the two layers of metal of a standard CMOS process. The direct metal-to-metallink created as a result of programming achieves a connection
with resistance values as a low as 50 ohms. This is less than 5 percent of the resistance of an EPROM or SRAM switch and 10 percent of that of a dielectric antifuse. The capacitance of an unprogrammed ViaLink site is also lower than these alternative
approaches. The resulting low RC time constant provides speeds
two to three times faster than older generation technologies.
Figure 1 shows an unprogrammed ViaLink site. In a custom metal
masked ASIC, such as a gate array, the top and bottom layers of
metal make direct contact through the via. In a ViaLink programmable ASIC device, the two layers of metal are intially separated
by an insulating semiconductor layer with resistence in excess of 1
gigaohm.
technology is a I-micron, n-well CMOS technology with a single
polysilicon layer and two layers of metal interconnect. The only
deviation from the standard process flow occurs when the ViaLink
module is inserted between the metal deposition steps.
As the size of a ViaLink is identical to that of a standard metal interconnect via, programmable elements can be packed very densely. The microphotograph in Figure 4 shows an array of Via Link elements. The density is limited only by the minimum dimensions of
the metal-line pitch. Migration of the current process from I-micron to Cypress's 0.65-micron process will allow the development
of pASIC380 devices with tens of thousands of usable gates.
25,---------------------------~
l
20
~
zw 15
:::>
0 10
w
a:
LL
A programming pulse of 10 to 11 volts applied across the via forms
a bidirectional conductive link connecting the top and bottom metallayers, as shown in Figure 2. The tight distribution of link resistance is shown in Figure 3.
5
0
0
50
100
PROGRAMMED ViaLink RESISTANCE (Ohms)
Standard CMOS Process
0380-4
pASIC380 devices are the first FPGA devices to be fabricated on a
conventional high-volume CMOS process. Initially, the base
Figure 3. Distribution of Programmed Link Resistance
c3Su-5
Figure 4. An Array of ViaLink Elements
4-268
pASIC380
Family
PRELIMINARY
55
r
54
53
-
&-
52
1
~
J.
II
-I
11
I
en
Q
....I
0.
51
~II
1l
i
oJ-
1
I
50
c380-6
Figure 5. A Matrix of Logic Cells and Wiring Channels
The pASIC380 device architecture consists of an array of user-configurable logic building blocks, called logic cells. Figure 5 shows a
section of a pASIC380 device containing intemallogic cells, input/
output cells, and dual-layer vertical and horizontal metal routing
channels. Through ViaLink elements located at the wire intersections, the output of any cell may be programmed to connect to the
input of any other cell.
The regularity and orthogonality of this interconnect, together
with the capability to achieve 100 percent routability of logic cells
makes the pASIC380 architecture closer in structure and performance to a metal-masked gate array than any other FPGA family.
It also makes system operating speed far less sensitive to partitioning and placement decisions, thus minor revisions to a logic design
usually result in only small changes in performance.
Organization
The pASIC380 Family of very high speed FPGAs contains devices
covering a wide spectrum of I/O and density requirements. Four
members, ranging from 1000 gates in 44- and 68-lead packages to
4,000 gates in 84- and 144-lead packages, are shown in Figure 6.
The single lines between logic cells represent channels containing
up to twenty-two wires.
The key features of all five pASIC380 devices are listed in Table 1.
See the individual product datasheets for more specific information on each device.
Individual part numbers indicate unique logic cell and I/O cell
combinations. For example, the CY7C383 contains 192 logic cells
and 56 I/O cells in a 68-pin package. The CY7C384 also contains
192 logic cells, but it has 68 I/O cells and is packaged in 84- and
100-pin packages. Note that at each pASIC380 density there is a
density upgrade available in the same package. In other words, the
CY7C383 features 2,000 gates in the same pinout as the 1,000-gate
CY7C382. The same applies to the CY7C385A and CY7C384.
Gate counts for pASIC380 devices are based on the number of usable or "gate array" gates. Each of the internallogic cells has a total
logic capacity of up to 30 gates. As a typical application will use 10
to 12 ofthese gates, the usable gate count is significantly lower than
the total number of available gates. On the pASIC380 product
family, Cypress uses the more conservative usable (gate array) gate
method of specifying density. Total available gate densities may
also be specified as EPLD/LCA gates.
4-269
pASIC380
Family
~
;~PRESS
.
_
,
PRELIMINARY
SEMICONDUCTOR
CY7C381, 382
o
0 0
000
000
0 0 0
0 0 0
0 0 0
o 0 o
o 0 o
0 0
0
0
0 0
o 0
0 0
0 o
0 o
o
o
0 0
o 0
o 0
0 0
o 0
0 0
0 0
0 0
0 0 0
0 0 0
o 0 0
0 0 0
o 0 0
0 0 0
o 0 0
o 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
. ....... ....
.o . .o . .o . .o . . . . . . . . .
•
I/O/HIGH-DRIVE INPUT/
CLOCK CELLS
CY7C383, 384
0
0 0 o
0 0 0
o 0 0
0
0 0 0
0
0 0 0
0
0 0 0
o 0 0 0
0 0 0
0
0 o 0 0 0
0 0 0 o 0
0 o 0 o 0
o
o
o
0
0
0
0
0
0
0
0
0
0
0 o
00
0 0
0 0
o 0
o 0
0 0
o 0
0 0
0 0
o 0
0 0 0 0
0 0 0 o
o 0 0 0
0 0 0 0
0 0 0 0
0 0 o 0
0 0 o 0
o 0 00
0 0 o 0
o 0 0 0
0 0 0 0
o 0 o 0
0 0 0
0 0 o
o 0 0
o 0 o
o 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 00
0 o 0
0 o 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
. . . . . . . . . .o. . . . . . . . . . . . . . . . . . .
CY7C385A, 386A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
o 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o 0
0
0
0
0
0
0
0
0
0 o 0
0 0 0
0 0 0
0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
o
0
0
0
0
0
0 0
0
0 0
0 0
0 0
. . . . . . . . . .o. . . . . . . . . . . . . . . .
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
c380~7
Figure 6. pASIC380 Family Members
4-270
=~
. ;iE CYPRESS
~,
pASIC380
Family
PRELIMINARY
SEMICONDUcrOR
Table 1. Key Features of pASIC380 Devices
Device
Logic Cells
I/O Cells
Dedicated Inputs
Usable Gates
EPLD/LCA Gates
Packages
7C381
96
32
8
1000
3000
44-Pin PLCC
7C382
96
56
8
1000
3000
68-Pin PLCC, PGA
100-Pin TQFP
68-Pin PLCC, PGA
7C383
192
56
8
2000
6000
7C384
192
68
8
2000
6000
7C385A
384
68
8
4000
12000
7C386A
384
114
8
4000
12000
84-Pin PLCC, PGA
100-Pin TQFP
84-Pin PLCC, PGA
100-Pin TQFP
144-Pin TQFP
145-PinPGA
I
U)
QS - - - - - - - - - - - - - - - ,
A1
A2
A3
A4
A5
A6
) - - - - - - -....- - - _ + - -
AZ
...----.,1----
OZ
B1
B2
C1
C2
QZ
D1
D2
E1
E2
R
' - - - - - _ 1 _ - _ + - - NZ
F1
F2
F3
)--~~-----_I_-_+--
F4
F5
F6
QC _ _ _ _ _ _ _ _ _ _ _...J
QR - - - - - - - - - - - - - - - '
FZ
0380·8
Figure 7. pASIC380 Internal Logic Cell
pASIC380 Internal Logic Cell
The pASIC380 internal logic cell, shown in Figure 7, is a generalpurpose building block that can implement most TTL and gate
array macro library functions. It has been optimized to maintain
the inherent speed advantage of the ViaLink technology while insuring maximum logic flexibility.
The logic cell consists of two 6-inputAND gates, four 2-input AND
gates, three 2-to-1 multiplexers and a D flip-flop. As noted above,
each cell represents approximately 30 gate-equivalents oflogic capability. The pASIC380 logic cell is unique among FPGA architectures in that it offers up to 14-input-wide gating functions. It can
implement all possible Boolean transfer functions of up to three
variables as well as many functions of up to 14 variables.
Glitch-free switching of the multiplexer is insured because the internal capacitance of the circuit maintains enough charge to hold
the output in a steady state during input transitions. The multiplexer output feeds the D-type flip-flop, which can also be configured
to provide JK-, SR-, or T-type functions as well as count with carry-
in. Tho independent SET and RESET inputs can be used to Q
asynchronously control the output condition. The combination of ..J
wide gating capability and a built-in register makes the pASIC380 a.
logic cell particularly well suited to the design of high-speed state
machines, shift registers, encoders, decoders, arbitration and arithmetic logic, as well as a wide variety of counters.
Each pASIC380 logic cell features five separate outputs. The existance of multiple outputs makes it easier to pack in dependant functions into a single logic cell. For example, if one function requires
a single register, both 6-input AND gates (A and F) are available
for other uses. Logic packing is accomplished automatically by
Warp3 software.
The function of a logic cell is determined by the logic levels applied
to the inputs of the AND gates. ViaLink sites located on signal
wires tied to the gate inputs perform the dual role of configuring
the logic function of a cell and establishing connections between
cells.
The pASIC380 macro library contains more than 200 of the most
frequently used logic funcitons already optimized to fit the logic
cell architecture. A detailed understanding of the logic cell is therefore not necessary to successfully design with pASIC380 devices.
CAE tools will automatically translate a conventional logic schematic and/or VHDL source code into a device and provide excellent performance and utilization.
Three types of input and output structures are provided on pASI C380 devices to configure buffering functions at the external pads.
They are called the Bidirectional Input/Output (I/O) cell, the Dedicated Input (I) cell, and the ClocklDedicated Input (CLK/I) cell.
The bidirectional I/O cell, shown in Figure 8, consists of a 2-input
OR gate connected to a pin buffer driver. The buffer output is controlled by a three-state enable line to allow the pad to also act as an
input. The output may be configured as active HIGH, active LOW,
or as an open drain inverting buffer.
I/O~~
0380·9
Figure 8. BidirectionalI/O Cell
The Dedicated Input cell, shown in Figure 9, conveys true and complement signals from the input pads into the array oflogic cells. As
these pads have nearly twice the current drive capability of the I/O
4-271
~Ap=
~,
pASIC380
Family
PRELIMINARY
SEMICONDUCTOR
pads, they are useful for distributing high fanout signals across the
device.
~11
1~12
c380·10
Figure 9. Dedicated Input High-Drive Cell
The ClocklDedicated Input cell (Figure 10) drives a low-skew, fanout-independent clock tree that can connect to the clock, set, orreset inputs of the logic cell flip-flops. The CY7C384, for example,
has 68 I/O cells, 6 I cells, and 2 I/CLK cells.
~1
CLKlI~2CLK
Figure 10. ClocklDedicated Iuput Cell
pASIC380 Interconnect Structure
Multiple logic cells are joined together to form a complex logic
function by interconnectiop through the routing channels. To describe the organization of these routing channels, a hypothetical
14-pin device consisting of two logic cells is shown inFigure 11. This
device contains the same architectural features as the members of
the pASIC380 family.
Active logic functions are performed by the internal logic cells, the
I/O cells (pins 2, 3, 7, 9, 10, and 14) and the I cells (pins 4, 6, 11, and
12
1
Horizontal wiring channels, called rows, provide connections, via
cross links, to other columns of logic cells and to the periphery of
the chip. Appropriate programming of ViaLink elements allows
electrical connection to be made from any logic cell output to the
input of any other logic or I/O cell. Ample wires are provided in the
channels to permit automatic place and route of many designs using up to 100 percent of the device logic cells. Designs can be com-
11
Vee
~
r.
Three types ofsignal wires are employed: segmented wires, express
wires, and clock wires. Segmented wires are predominantly used
for local connections and have ViaLink elements known as a Cross
Link (denoted by the open box symbol), at every crossover point.
They may also be connected to the segmented wires of cells above
and below through ViaLink elements, called Pass Links (denoted
by the X symbol). Express lines are similar to segmented wires except that they are not divided by Pass Links. Dedicated clock wires
are lightly loaded with only three links per cell to distribute highspeed clock edges to the flip-flop CLK, SET, and RESET inputs.
Express wires may also be used to deliver clock signals into the
multiplexer region of the cell for combinatorial gating. The automatic place and route software allocates signals to the appropriate
wires to insure the optimum speed/density combination.
Vertical Vee and GND wires are located close to the logic cell gate
inputs to allow any input that is not driven by the output of another
cell to be automatically tied to either Vee or GND. All of the vertical wires (segmented, express, clock, and power) considered as a
group are called vertical channels. These channels span the full
height ofthe device and run to the left of each column oflogic cells.
0380-11
1
13). These cells are connected with vertical and horizontal wiring
channels.
1
R
r.
~
I.-X
9
~
i
jly
f)
~
f4
0
1
I~
...
2
]
II ;tt
~
III II
'~
4
JJee
6
,~
Figure 11. pASIC380 Device Features
4-272
c380-12
~
~
PRELIMINARY
pASIC380
Family
pleted automatically even with a high percentage of fIxed user
placement of internal cells and pin locations.
This information is presented to provide the user with inisght into
how a logic function is implemented in pASIC380 devices. However, it is not necessary to develop a detailed understanding of the architecture in order to achieve efficient designs. All routine tasks
are f~lly automatic. No manual wire routing is necessary, nor is it
permItted by the software. Fully automatic placement oflogicfunctions is also offered. But if it is necessary to achieve a specific pin
configuration or register alignment, for example, manual placement is supported.
c380·13
Power Consumption
Figure 12. Internal Serial Scan Path
Typical standby power supply current consumption, ICCl, of a pASIC380 device is 2 rnA. The worst-case limit for standby current
(ICCI) over the full operating range of the pASIC380 devices is 10
rnA. Formulas for calculating Icc under AC conditions (ICC2) are
pr~)Vi~ed in the "pASIC380 Power vs. Operating Frequency" applIcatIon note. As an example of the low-power consumption of
pASIC380 devices, the 16-bit counter example detailed in the application note consumes just 50 rnA at 100 MHz.
Programming and Testing
pASIC380 devices may be programmed and functionally tested on
the Cypress Programmer supplied with the Warp3 software. The
unit is completely self contained. No add-in boards are required.
Programming signals are donwloaded from the PC over an RS232
link. Third-party programmers are being qualified.
All pASIC380 device have a built-in serial scan path linking the
logic cell register functions (Figure 12). This is provided to improve
factory test coverage and to permit testing by the user with auto~aticallygeneratedtestvectorsfollowingprogramming.Automat
IC Test Vector Generation software is included in Warp3. The Programmer permits a high degree of test coverage to be achieved
conveniently and rapidly using test vectors optimized for the pASIC380 architecture.
•
technology inserted between the metal deposition steps. The base
CMOS process has been qualified to meet the requirements of ~
MIL-STD-883B, Revision C.
..J
The ViaLink element exists in one of two states: a highly resistive
unprogrammed state, OFF, and the low-impedance, conductive
state, ON. It is connected between the output of one logic cell and
the inputs of other logic cells directly or through other links. No
DC current flows through either a programmed or an unprogrammed link during operation as a logic device. An unprogrammed link sees a worst-case voltage equal to V CC biased across
its terminals. A programmed link carries AC current caused by
charging and discharging of device and interconnect capacitances
during switching.
Study oftest structures and complete pASIC380 devices has shown
that an unprogrammed link under V cc bias remains in the unprogrammed state over time. Similary tests on programmed links under current bias exhibit the same stability. The long-term reliability
of the combined CMOS and ViaLink structure is similar to that of
the base gate array process. For further details, see the pASIC380
Family Reliability Report.
Reliability
The pASIC380 Family is based on a 1-micron high-volume CMOS
fabrication process with the VIALink programmable-via antifuse
Document #: 38-0021O-A
pASI~380 and Warp3 are trademar~s of Cypress Semiconductor Corp.
PAL IS a trademark of Advanced MICro Devices Corp.
GAL is a trademark of Lattice Semiconductor Corp.
ViaLink is a trademark of QuickLogic Corp.
Microsoft Windows is a trademark of Microsoft Corp.
4-273
c..
PRELIMINARY
CY7C381
CY7C382
Very High Speed
lK (3K) Gate CMOS FPGA
Features
• Very high speed
- Loadable counter frequencies
greater than 100 MHz
- Chip-to-chip operating frequencies
up to 85 MHz
- Input + logic cell + output delays
under 9 ns
• Unparalleled FPGA performance for
counters, data path, state machines,
arithmetic, and random logic
• High usable density
- 8 x 12 array of 96 logic cells provides 3,000 total available gates
- 1,000 typically usable "gate array"
gates in 44- and 68-pin PLCC/
CPGA packages
• Low power, high output drive
- Standby current typically 2 rnA
-16-bit counter operating at 100
MHz consumes 50 rnA
- Minimum IOL and IOH of 8 rnA
• Flexible logic cell architecture
- Wide fan-in (up to 14 input gates)
- Multiple outputs in each cell
- Very low cell propagation delay
(3.4 ns)
• Low-cost, powerful design tools
- Designs entered in VHDL, schematics, or both
- Fast, fully automatic place and
route
•
•
•
•
•
- Waveform simulation with back
annotated net delays
- PC and workstation platforms
Robust routing resources
- Fully automatic place and route of
designs using up to 100 percent of
logic resources
- No hand routing required
32 (CY7C381) to 56 (CY7C382) bidirectional input/output pins
6 dedicated input/high-drive pins
2 clock/dedicated input pins with fanout-independent, low-skew nets
- Clock skew < 1 ns
Input hysteresis provides high noise
immunity
• Thorough testability
- Built-in scan path permits 100 percent factory testing of logic and I/O
cells
- Automatic Test Vector Generation
(ATVG) software supports user
testing after programming
• CMOS process with ViaLink® programming technology
- High-speed metal-to-metallink
- Non-volatile antifuse technology
• 68-pin PLCC is compatible with
EPLD 1800 and LCA 2064 industrystandard pinouts
Functional Description
The CY7C381 and CY7C382 are members of the pASIC380 family of very high
speed CMOS user-programmable ASIC
(pASIC) devices. The 96 logic cell fieldprogrammable gate array (FPGA) offers
1,000 typically usable "gate array" gates.
This is equivalent to 3,000 EPLD or LCA
gates. The CY7C381 is available in a
44-pin PLCC. The CY7C382 is available in
a 68-pin PLCC and CPGA.
Low-impedance, metal-to-metal ViaLink
interconnect technology provides non-volatile custom logic capable of operating at
speeds above 100 MHz with input and output delays under 4 ns. This permits highdensity programmable devices to be used
with today's fastest CISC and RISC microprocessors.
Designs are entered into the CY7C381
and CY7C382 using Cypress Warp3 software or one of several third-party tools.
Warp3 is a sophisticated CAE package that
features schematic entry, waveform-based
timing simulation, and VHDL design synthesis. The CY7C381 and CY7C382 feature ample on-chip routing channels for
fast, fully automatic place and route of high
gate utilization designs.
For detailed information about the
pASIC380 architecture, see the pASIC380
Family datasheet.
Logic Block D'mgra m
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • • • • • • • •
0 0 0 0 0 0 0 0
0 0 0 0 o q 0 0
13: ·I~
0 0 0 0
~
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 01
0 0 0 0 0 0 0 0 0 01 0 10
0
0
0
0
I
0
0
0
0
~'~~
>----+-t--
1
1.
• • • • • • • • • • • •
•
I/O/HIGH-DRIVE INPUT CLOCK CELLS
44 or 68 PINS, INCLUDING 56 I/O CELLS, 6 INPUT HIGH-DRIVE CELLS, 2 INPUT/CLK (HIGH-DRIVE) CELLS
ViaLink is a trademark of QuickLogic Corporation.
4-274
c381-1
= .. ~
CY7C381
CY7C382
PRELIMINARY
~=CYPRESS
_ , SEMICONDUCTOR
PLCC
Pin Configurations
Top View
PLCC
Top View
o
gggggi5ggggg
110
110
liD
liD
liD
liD
I
I
Vee
IICLK
Vee
I
I
I
110
liD
liD
liD
liD
110
110
liD
liD
liD
IICLK
Vee
I
I
110
liD
liD
liD
liD
110
110
59
58
15
16
17
18
19
20
21
22
23
24
25
57
56
liD
liD
55
110
I
54
53
52
51
50
49
48
47
7C382
I
Vee
IICLK
II
I
liD
liD
liD
liD
110
liD
liD
Maximum Ratings
110
110
Operating Range
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature
Ceramic ........................... - 65°C to + 150°C
Plastic .............................. -40°C to + 125°C
Lead Temperature ............................... 300°C
Supply Voltage ......................... - O.5V to + 7.0V
Input Voltage ...................... - O.5V to Vee +0.5V
ESD Pad Protection . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±2000 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Latch-Up Current ............................ ±100 rnA
Range
Commercial
Ambient
Temperature
O°C to +70°C
Vee
5V±5%
Industrial
-40° to +S5°C
5V± 10%
Delay Factor (K)
Speed
Grade
-0
-1
Industrial
Min.
Max.
Commercial
Min.
Max.
0.4
1.67
0.46
1.55
0.4
1.43
0.46
1.33
0.46
1.25
-:-:-2
Shaded area contains advanced information.
Electrical Characteristics Over the Operating Range
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
Min.
Max.
Unit
IOH = - 4.0 rnA
3.7
V
IOH = - S.OrnA
2.4
V
IOH = - 1O.0!!A-
Vec - 0.1
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
II
Input Leakage Current
VIN = Vee or GND
-10
IOL = S.OrnA
IOL = 10.0 itA
V
0.4
V
0.1
V
2.0
V
O.S
V
+10
!!A!!ArnA
Ioz
Output Leakage Current
VIN = Vee or GND
-10
+10
los
Output Short Circuit Current
VOUT = GND
-10
-SO
30
140
rnA
IeCl
Standby Supply Current
Supply Current(1, 2]
VIN, VI/O = Vee or GND
10
rnA
f = 1.0 MHz, VI = Vee or GND
20
rnA
VOUT =Vee
Iee2
4-275
EC.:~PREss
~,.
CY7C381
CY7C382
PRELIMINARY
SEMICONDUCTOR
Capacitance
Parameter
Description
CIN
Input Capacitancef3]
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vcc = 5.0V
Max.
Unit
10
pF
20
pF
= 1 MHz,
Switching Characteristics Over the Operating Range
Propagation Delays[4]
with Fanout of
Parameter
LOGIC CELLS
Description
1
2
3
4
8
Unit
tpD
Combinatorial Delay[5]
3.4
3.8
4.2
4.8
8.1
ns
tsu
Set-Up Time[5]
3.7
3.7
3.7
3.7
3.7
ns
tH
Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tCLK
Clock to Q Delay
3.0
3.3
3.8
4.3
4.9
ns
tSET
Set Delay
2.7
3.1
3.5
4.1
7.4
ns
tRESET
Reset Delay
2.9
3.2
3.6
4.2
7.5
ns
tCWHI
Clock HIGH Time
2.0
2.0
2.0
2.0
2.0
ns
tCWLO
Clock LOW Time
3.6
3.6
3.6
3.6
3.6
ns
tsw
Set Width
2.1
2.1
2.1
2.1
2.1
ns
tRW
INPUT CELLS
Reset Width
1.9
1.9
1.9
1.9
1.9
ns
tIN
Input Delay (HIGH Drive)
3.7
3.8
4.2
4.6
6.4
ns
tINr
Input, Inverting Delay (HIGH Drive)
3.5
3.6
4.0
4.4
6.2
ns
tlO
Input Delay (Bidirectional Pad)
2.3
2.6
3.2
4.1
5.5
ns
tGCK
Clock Buffer Delay [6]
4.4
4.5
4.6
4.6
5.0
ns
Propagation Delaysl4j
with Output Load Capacitance (pF) of
30
SO
75
100
150
tOUTLH
Output Delay LOW to HIGH
3.1
3.8
4.6
5.5
7.2
tOUTHL
Output Delay HIGH to LOW
3.1
3.9
5.0
6.1
8.3
ns
tPZH
Output Delay Three-State to HIGH
4.4
5.3
6.5
7.7
10.1
ns
tpZL
Output Delay Three-State to LOW
4.0
4.6
5.4
6.2
7.7
ns
tpHZ
Output Delay HIGH to Three-State[7]
3.3
3.3
3.3
3.3
3.3
ns
tpLZ
Output Delay LOW to Three-State[7]
3.7
3.7
3.7
3.7
3.7
ns
OUTPUT CELLS
ns
Notes:
1.
Measured with six 16-bit counters configl.\red internally and all outputs driving. To calculate power for your application, see the "pASIC380 Power vs. Operating Frequency" application note.
2. Guaranteed but not 100% tested.
3. CI = 20pF max. on pin 32 (7C381) or pin 50 (7C382).
4. Worst-case propagation delay times over process variation at Vee =
5.0Vand TA = 25°c' Mulitplybythe appropriate delay factor, K, for
speed grade to get worst-case parameters over full Vee and tempera- ture range as specified in the operating range. All inputs are TTL with
3-ns linear transition time between 0 and 3 volts.
5. These limits are derived from worst-case values for a representative
selection of the slowest paths through the pASIC logic cell including
net delays. Guaranteed delay values for specific paths should be determined from simulation results.
6.
7.
4-276
Clock buffer fanout refers to the maximum number of flip-flops per
half column. The number of half columns used does not affect clock
buffer delay.
The following loads are used for tpxz:
:ll..5PF
,~. -l 1
tpHZ
~
.
-~
CYPRESS
•
_
CY7C381
CY7C382
PRELIMINARY
<2
. , SEMICONDUCTOR
High Drive Buffer
# High Drives
Parameter
Description
High Drive Input Delay
tIN
Propagation Delays[4j with Fanout of
Wired
Together
12
24
1
7.9
1L2
48
8.6
4
High Drive Input, Inverting Delay
1
7.5
ns
10.4
11.8
9.4
10.8
10.8
ns
ns
ns
7.5
2
Unit
ns
3
tINI
96
9.7
8.0
2
72
9.3
3
8.2
4
II
ns
10.0
11.8
ns
9.0
10.8
ns
III
C
..J
Switching Waveforms
Q.
Combinatorial Delay
INPUT
OUTPUT
= = = = =f_I_.= = = = = tP=D=:,-=-=:,- =-=~=-:~ "-I-= = = = = = = = = = = = = =
0381-2
CLOCK
FtH;j~HI_:"I._,~-_tc_wLO-_~1~
------{'- ~~
;k.--_____l'_____________1__
Q
0381-4
Set and Reset Delays
~
SET
tsw
tSET
Q
RESET
tRW
tRESET
i
Q
t
~
0381-3
Output Delay
tOUTLH
OUTPUT
tOUTHL
------'~----~
4-277
0381-5
-
=:.. .
4
CY7C381
CY7C382
PRELIMINARY
~=CYPRESS
~, SEMICONDUcrOR
Switching Waveforms (continued)
Three-State Delay
OUTPUT
BUFFER
ENABLE
----'(IP~
THREE-STATE
OUTPUT
THREE-STATE
c381·6
1:ypical AC Characteristics
Factor table. The effects of voltage and temperature variation are
illustrated in the graphs below. Wafp3 incorporates datasheet AC
Characteristics into the design database for pre-place-and-route
simulations. The Warp3 Delay Modeler extracts specific timing parameters for precise simulation results following place and route.
Propagation delays depend on routing, fan-out, load capacitance,
supply voltage, junction temperature, and process variation. The
AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst-case estimates are obtained
when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified by the speed grade in the Delay
VOLTAGE FACTOR (Kv) VERSUS SUPPLY VOLTAGE (Vee)
1.10
1.08
--....
1.06
~
1.04
~
1.02
>
~
~
1.00
~
~
0.98
0.96
~
0.94
0.92
4.50
5.00
4.75
~
...............
5.25
5.50
0381-7
SUPPLY VOLTAGE, Vee (Volts)
TEMPERATURE FACTOR (KT) VERSUS TEMPERATURE
1.30
1.25
./
1.20
1.15
/~
1.10
~
~
1.05
1.00
0.95
0.90
0.85
~
~
~
~
~
"r
~ """"
~
-I"'"'"
0.80
-60
-40
-20
o
20
40
60
JUNCTION TEMPERATURE (OC)
*THETAJA = 45 °C/WATT FOR PLCC
4-278
80
100
120
140
0381-8
EC~PRE§
~,
CY7C381
CY7C382
PRELIMINARY
SEMICONDUCIOR
Combinatorial Delay Example (Load = 30 pF)
tlO
j..---
2.3 ns
..
I.
~D
~~
3.4 ns - - - - - - .....
.1---- 3.1 ns
IN1 t - - - - - - - - I
---I
>-------1 OUT
IN2 t - - - - - - - - I
INPUT DELAY
+ COMBINATORIAL DELAY + OUTPUT DELAY
= 8.8 ns
c381-9
Sequential Delay Example (Load = 30 pF)
tlO
j..---
2.3ns
..
I.
3.7ns
tCLK
----i..~I~----
IN1 1 - - - - - - - - 1
C
tOUT
...I
1.;.---- 3.1 ns ---I
a..
3.0ns - -......
/'------1
OUT
tGCK
j..---
4.4 ns - - - - .
CLKI--------I
+ REG SET-UP + CLOCK TO OUTPUT + OUTPUT DELAY = 12.1
INPUT DELAY
ns
c381-10
High-Drive Delay Example
tiN
j..---
I-
tpD
3.7ns - - - -......
.. - - - - - - 3.4ns
- - - - - - - - i...~I••- - -
IN1 t - - - - - - - - - I
tOUT
3.1 ns
---I
. > - - - - - - 1 OUT
tlNI
j..---
3.5 ns
- - - - - - !..
~I
IN21--------I
INPUT DELAY
•
en
tsu
+ COMBINATORIAL DELAY + OUTPUT DELAY = 10.2 ns
4-279
0381-11
PRELIMINARY
Ordering Information
Speed
Grade
Ordering Code
Package
Name
Package 1Ype
Operating
Range
2
CY7C381-2JC
J67
44-Lead Plastic UMet3, Cbip~~arrier
Commercial
1
CY7C381-lJC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
CY7C381-1JI
J67
44-Lead Plastic Leaded Chip Carrier
Industrial
CY7C381-OJC
J67
44-Lead Plastic Leaded Chip Carrier
Commercial
CY7C381-0JI
J67
44-Lead Plastic Leaded Chip Carrier
Industrial
Package
Name
Package 'JYpe
G68
J81
G68
J81
G68
J81
G68
J81
G68
J81
68-Pin Grid Array (Cavity Down)
68~~ad Plastic Leaded Chip O!qier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
0
Speed
Grade
2
1
0
Ordering Code
,c
CY7C382-2GC
CY7C382-2JC
CY7C382-1GC
CY7C382-lJC
CY7C382-1GI
CY7C382-1JI
CY7C382-0GC
CY7C382-0JC
CY7C382-0GI
CY7C382-0JI
Shaded areas contam advanced mformatlOn.
Document #: 38-00207
4-280
Operating
Range
Commercial
,
Commercial
Industrial
Commercial
Industrial
CY7C381
CY7C382
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• Very high speed
- Loadable counter frequencies
greater than 100 MHz
- Chip-to-chip operating frequencies
up to 85 MHz
- Input + logic cell + output delays
under 9 ns
• Unparalleled FPGA performance for
counters, data path, state machines,
arithmetic, and random logic
• High usable density
-12 x 16 array of 192 logic cells provides 6,000 total available gates
- 2,000 typically usable "gate array"
gates in 68- and 84-pin PLCC/
CPGA packages
• Low power, high output drive
- Standby current typically 2 rnA
-16-bit counter operating at 100
MHz consumes 50 rnA
- Minimum IOL and Iou of 8 rnA
• Flexible logic cell architecture
- Wide fan-in (up to 14 input gates)
- Multiple outputs in each cell
- Very low cell propagation delay
(3.4 ns)
• Low-cost, powerful design tools
- Designs entered in VHDL, schematics, or both
- Fast, fully automatic place and
route
•
•
•
•
•
•
•
•
•
CY7C383
CY7C384
Very High Speed
2K (6K) Gate CMOS FPGA
- Waveform simulation with back
annotated net delays
- PC and workstation platforms
Robust routing resources
- Fully automatic place and route of
designs using up to 100 percent of
logic resources
- No hand routing required
56 (CY7C383) to 68 (CY7C384)
bidirectional input/output pins
6 dedicated input/high-drive pins
2 clock/dedicated input pins with fanout-independent, low-skew nets
- Clock skew < 1 ns
Input hysteresis provides high noise
immunity
Thorough testability
- Built-in scan path permits 100 percent factory testing of logic and I/O
cells
- Automatic Test Vector Generation
(ATVG) software supports user
testing after programming
CMOS process with ViaLink@l programming technology
- High-speed metal-to-metallink
- Non-volatile antifuse technology
68-pin PLCC is compatible with
CY7C382 footprint for easy upgrade
84-pin PLCC is compatible with
ACTI020 power supply and ground
pinouts
........ .....
Functional Description
The CY7C383 and CY7C384 are members of the pASIC380 family of very high
speed CMOS user-programmable ASIC
(pASIC) devices. The 192 logic cell fieldprogrammable gate array (FPGA) offers
2,000 typically usable "gate array" gates.
This is equivalent to 6,000 EPLD or LCA
gates. The CY7C383 is available in a
68-pin PLCe. The CY7C384 is available in
an 84-pin PLCC and CPGA.
Low-impedance, metal-to-metal ViaLink
interconnect technology provides non -volatile custom logic capable of operating at
speeds above 100 MHz with input and output delays under 4 ns. This permits highdensity programmable devices to be used
with today's fastest eISC and RISC microprocessors.
Designs are entered into the CY7C383
and CY7C384 using Cypress Warp3 software or one of several third-party tools.
Warp3 is a sophisticated CAE package that
features schematic entry, waveform-based
timing simulation, and VHDL design synthesis. The CY7C383 and CY7C384 feature ample on-chip routing channels for
fast, fully automatic place and route of high
gate utilization designs.
For detailed information about the
pASIC380 architecture, see the pASIC380
Family datasheet.
Logic Block Diagram
000000000000 0 0 0 o •
qDDDDDDDDDDD 0 0 0 0 ••
000000000000 0 0 0
000000000000 0 0 0 0 •
0000000000000000:
o 0 0 0 0 0 0 0 0 0 0 0 0 0
Di.-0 0 0 0 0 0 0 0 0 0 0 0 0 D~ I--0000000000000000:
0000000000000000:
0000000000000000:
0000000000000000:
0000000000000000.
•
I/O/HIGH-DRIVE INPUT/CLOCK CELLS
° :·
°
°
.... ...
1
~~~~©~~
py~:-
1
.. ..
68 or 84 PINS, INCLUDING 68 I/O CELLS, 6 INPUT HIGH-DRIVE CELLS, 2 INPUT/CLK (HIGH-DRIVE) CELLS
ViaLink is a trademark of QuickLogic Corporation.
4-281
c383-1
II
U)
Q
..J
c..
=~PRFSS
CY7C383
CY7C384
PRELIMINARY
~, SEMICONDUCTOR
PLCC
Pin Configurations
Top View
()
PLCC
0
ggggggg?ggggg~ggggggg
Top View
o
gggggggg~gggggggg
I/O
I/O
I/O
I/O
I/O
I/O
I
I/ClK
Vee
I
I
I/O
I/O
I/O
I/O
I/O
I/O
11
17
7C383
18
19
20
21
22
23
24
25
58
57
56
55
54
53
52
51
50
49
48
47
46
45
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GND
I/O
I
I/ClK
I
I
Vee
I/ClK
I
I/O
I/O
I/O
I/O
I/O
I/O
Vee
I/O
I/O
I/O
I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
72
71
70
69
68
67
66
65
64
63
7C384
62
61
60
59
58
57
56
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Vee
I
I
I/ClK
I
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Operating Range
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature
Ceramic ........................... - 65°C to + 150°C
Plastic .............................. -40°C to +125°C
Lead Temperature ............................... 300°C
Supply Voltage ......................... - 0.5V to +7.0V
Input Voltage ...................... - 0.5V to Vee +O.5V
ESD Pad Protection ............................ ±2000 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±20 rnA
Latch-Up Current ............................ ±100 rnA
Range
Commercial
Ambient
Temperature
O°C to +70°C
Vee
5V±5%
Industrial
-40° to +85°C
5V±10%
Delay Factor (K)
Speed
Grade
-0
-1
Industrial
Min.
Max.
0.4
1.67
0.4
1.43
~2
'"
,
Commercial
Min.
Max.
1.55
0.46
,,'
0.46
1.33
O,~(j
ItZ5
Shaded area contains advanced information.
Electrical Characteristics Over the Operating Range
Parameter
VOR
Description
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
II
Input Leakage Current
loz
loS
Test Conditions
Min.
Max.
Unit
lOR = - 4.0 rnA
3.7
V
lOR = - 8.0 rnA
2.4
V
lOR = - 10.0 JAA
Vee - 0.1
IOL = 8.0 rnA
IOL = 10.0 JAA
V
0.4
V
0.1
V
V
2.0
0.8
V
+10
VIN = Vee or GND
-10
Output Leakage Current
VIN = Vee or GND
-10
+10
JAA
fAA.
Output Short Circuit Current
VOUT= GND
-10
-80
rnA
30
140
rnA
Ieel
Standby Supply Current
VouT=Vee
VIN, VIIO = Vee or GND
10
rnA
lee2
Supply Currentl 1, 2]
f = 1.0 MHz, VI = Vee or GND
25
rnA
4-282
~.
:~
~.
------iii CYPRESS
,
CY7C383
CY7C384
PRELIMINARY
SEMICONDUCTOR
Capacitance
Parameter
Description
CIN
Input Capacitance[3]
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vcc = 5.0V
Max.
Unit
10
pF
20
pF
= 1 MHz,
Switching Characteristics Over the Operating Range
Propagation Deiaysl4J
with Fanout of
3.4
3.8
4.2
4.8
8.1
ns
a
tsu
Combinatorial Delay[S]
Set-Up TimdS]
3.7
3.7
3.7
3.7
3.7
ns
Q
..J
tH
Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tCLK
Clock to Q Delay
3.0
3.3
3.8
4.3
4.9
ns
tSET
Set Delay
2.7
3.1
3.5
4.1
7.4
ns
tRESET
Reset Delay
2.9
3.2
3.6
4.2
7.5
ns
tCWHI
Clock HIGH Time
2.0
2.0
2.0
2.0
2.0
ns
Parameter
LOGIC CELLS
tpD
Description
1
2
3
4
8
Unit
tCWLO
Clock LOW Time
3.6
3.6
3.6
3.6
3.6
ns
tsw
Set Width
2.1
2.1
2.1
2.1
2.1
ns
tRW
INPUT CELLS
Reset Width
1.9
1.9
1.9
1.9
1.9
ns
ns
tIN
Input Delay (HIGH Drive)
3.7
3.8
4.2
4.6
6.4
tINI
Input, Inverting Delay (HIGH Drive)
3.5
3.6
4.0
4.4
6.2
ns
tlO
Input Delay (Bidirectional Pad)
2.3
2.6
3.2
4.1
5.5
ns
tGCK
Clock Buffer Delay [6]
4.4
4.5
4.6
4.6
5.0
ns
Propagation DeiaysL4J
with Output Load Capacitance (pF) of
OUTPUT CELLS
tOUTLH
Output Delay LOW to HIGH
30
50
75
100
150
3.1
3.8
4.6
5.5
7.2
ns
tOUTHL
Output Delay HIGH to LOW
3.1
3.9
5.0
6.1
8.3
ns
tPZH
Output Delay Three-State to HIGH
4.4
5.3
6.5
7.7
10.1
ns
tpZL
Output Delay Three-State to LOW
4.0
4.6
5.4
6.2
7.7
ns
tpHZ
Output Delay HIGH to Three-State[7]
3.3
3.3
3.3
3.3
3.3
ns
tPLZ
Output Delay LOW to Three-Statd7]
3.7
3.7
3.7
3.7
3.7
ns
Notes:
1. Measured with twelve 16-bit counters configured internally and all
outputs driving. 1b calculate power for your application, see the "pASIC380 Power vs. Operating Frequency" application note.
2. Guaranteed but not 100% tested.
3. CI = 20 pF max. on pin 50 (7C383) or pin 63 (7C384.).
4. Worst-case propagation delay times over process variation at Vee =
5.0Vand TA = 25°C. Mulitplybythe appropriate delay factor, K, for
speed grade to get worst-case parameters over full Vee and temperature range as specified in the operating range. All inputs are TIL with
3-ns linear transition time between 0 and 3 volts.
5. These limits are derived from worst-case values for a representative
selection of the slowest paths through the pASIC logic cell including
net delays. Guaranteed delayvalues for specific paths should be determined from simulation results.
6.
7.
4-283
Clock buffer fanout refers to the maximum number of flip-flops per
half column. The number of half columns used does not affect clock
buffer delay.
The following loads are used for tpxz:
~5PF
,no0.r. I tpHZ
o
Q.
~
_~PRFSS
"""'=::IIr'
CY7C383
CY7C384
PRELIMINARY
SEMICONDUcrOR
High Drive Buffer
# High Drives
Parameter
Description
12
24
1
7.9
11.2
High Drive Input Delay
tIN
Propagation Delays[4j with Fanout of
Wired
Together
48
High Drive Input, Inverting Delay
8.6
7.5
1
ns
9.7
3
4
tINI
10.4
11.8
ns
9.4
10.8
ns
ns
10.8
7.5
2
Unit
ns
8.0
2
96
72
ns
9.3
3
4
8.2
10.0
11.8
ns
9.0
10.8
ns
SWltchmg Waveforms
Combinatorial Delay
INPUT
OUTPUT
set-UP:d H~'~u
~
tpD
*
§~~
~
tCWHI
CLOCK
~*
Q
Set and Reset Delays
SET
Q
RESET
t
~
0383-2
0383-3
~
tsw
tSET
tRW
tRESET
i
OUTPUT
t
h
.
Q
Output Delay
}
tcwLO
tOUTLH
...,..
tOUTHL
~
~
4-284
c383~5
i~PRFSS
CY7C383
CY7C384
PRELIMINARY
•~, SEMICONDUCTOR
Switching Waveforms (continued)
Three-State Delay
OUTPUT
BUFFER
ENABLE
1--tPHZ- { ~ZL
THREE-STATE
OUTPUT
THREE-STATE
THREE-STATE
c383-6
lYPical AC Characteristics
Propagation delays depend on routing, fan-out, load capacitance,
supply voltage, junction temperature, and process variation. The
AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst-case estimates are obtained
when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified by the speed grade in the Delay
1.10
1.08
""'- ~
1.02
>
~
1.00
~
0.98
~
0.96
~
0.94
0.92
4.50
4.75
5.00
~
-.........
5.25
5.50
0383-7
SUPPLY VOLTAGE, Vee (Volts)
1.30
TEMPERATURE FACTOR (KT) VERSUS TEMPERATURE
1.25
./
1.20
1.15
~~
1.10
I~
1.05
1.00
0.95
~
0.90
0.85
~
~
~
~
.....,-
I"'"
~'""
V
-+"""'"
0.80
-60
-40
-20
o
20
tn
Q
Q.
~
1.06
4
....I
VOLTAGE FACTOR (Kv) VERSUS SUPPLY VOLTAGE (Vrr)
1.04
~
Factor table. The effects of voltage and temperature variation are
illustrated in the graphs below. Warp3 incorporates datasheet AC
Characteristics into the design database for pre-place-and-route
simulations. The Warp3 Delay Modeler extracts specific timing parameters for precise simulation results following place and route.
40
60
80
100
120
140
JUNCTION TEMPERATURE (0C)
0383-8
*THETA JA = 45 °CIWATI FOR PLCC
4-285
~~PRESS
iF SEMICONDUCTOR
.
~
Combinatorial Delay Example (Load = 30 pF)
f.---
tlO
2.3 ns
CY7C383
CY7C384
PRELIMINARY
.1.
~D
3.4 ns
~~
---------1•.,....- - - 3.1 ns ----I
IN11--------I
>----------1 OUT
IN21--------I
INPUT DELAY
+ COMBINATORIAL DELAY + OUTPUT DELAY = 8.8 ns
0383-9
Sequential Delay Example (Load = 30 pF)
f.---
tlO
2.3ns
.1.
tsu
tCLK
IN11--------I
f.---
tOUT
*1...--- 3.1 ns ----I
3.7ns ----;.~I~.--- 3.0ns - - -.....
> - - - - - - 1 OUT
tGCK
4.4 ns - - - -••1
CLK~------~
INPUT DELAY + REG SET-UP + CLOCK TO OUTPUT + OUTPUT DELAY
= 12.1
ns
0383-10
High-Drive Delay Example
f.--IN1
tiN
~D
3.7 ns - - - -......- - - - - - - 3.4ns
-I.
~~
-----------1_.,.1...--- 3.1 ns----l
I-------~
f.---
; : - - - - - - 1 OUT
tlNI
3.5 ns -----;-~I
IN21--------I
INPUT DELAY
+ COMBINATORIAL DELAY + OUTPUT DELAY = 10.2 ns
0383-11
4-286
4:~
•
6i1i:
,
CY7C383
CY7C384
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
Grade
2
,
0
Speed
Grade
2 ;
;1,
1
0
(
068'
"", J81
'
Ordering Code
CJ7C384;';"2GC'
CY7C~~:r-2JC;, .
CY7C384-1GC
CY7C384-lJC
CY7C384-1GI
CY7C384-lJI
CY7C384-0GC
CY7C384-OJC
CY7C384-0GI
CY7C384-0JI
Package
'JYpe
~~~!.'in Qcid Arr~ (Cavitypown)
G68
J81
G68
J81
G68
J81
G68
J81
68-LeadPlastic t.eaded,Qmp Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
68-Pin Grid Array (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
Package
Name
Package
'JYpe
CY7C383-1GC
CY7C383-lJC
CY7C383-1GI
CY7C383 -lJI
CY7C383-0GC
CY7C383-0JC
CY7C383-0GI
CY7C383-0JI
1
"
CY7C3&fl:::;}Gc; :
<;)',1C3&3;;;;'2J~<
,"
Package
Name
Ordering Code
G84
S4-Pin Grid Arr~Y:'(Cavi~ Up)~~$;: , ',
J83
G84
J83
G84
J83
G84
J83
G84
J83
~t.ea~Plast~cLeaded Qhip .9irrier
84-Pin Grid Array (Cavity Up)
84-Lead Plastic Leaded Chip Carrier
84-Pin Grid Array (Cavity Up)
84-Lead Plastic Leaded Chip Carrier
84-Pin Grid Array (Cavity Up)
84-Lead Plastic Leaded Chip Carrier
84-Pin Grid Array (Cavity Up)
84-Lead Plastic Leaded Chip Carrier
Shaded area contams advanced mformatlOn.
Document #: 38-00208-A
4-287
Operating
Range
"Commercial
Commercial
Industrial
II
Commercial
Industrial
en
C
..J
a..
Operating
Range
COmmercial
,
~,"
:'
Commercial
Industrial
Commercial
Industrial
"
CY7C385A
CY7C386A
ADVANCED INFORMATION
Very High Speed
4K (12K) Gate CMOS FPGA
Features
• Very high speed
- Loadable couuter frequeucies
greater than 100 MHz
- Chip-to-chip operating frequencies
up to 85 MHz
- Input + logic cell + output delays
under 9 ns
• Unparalleled FPGA performance for
counters, data path, state machines,
arithmetic, and random logic
• High usable density
-16 x 24 array of 384 logic cells provides 12,000 total available gates
- 4,000 typically usable "gate array"
gates in 84-pin PLCC/CLCC and
144-pin PQFP packages
• Low power, high output drive
- Standby current typically 2 rnA
- 16-bit counter operating at 100
MHz consumes 50 rnA
- Minimum IOL and lOB of 8 rnA
• Flexible logic cell architecture
- Wide fan-in (up to 14 input gates)
- Multiple outputs in each cell
- Very low cell propagation delay
(3.4 ns)
• Low-cost, powerful design tools
- Designs entered in VHDL, schematics, or both
- Fast, fully automatic place and
route
•
•
•
•
•
•
•
•
- Waveform simulation with back annotated net delays
- PC and workstation platforms
Robust routing resources
- Fully automatic place and route of
designs using up to 100 percent of
logic resources
- No hand routing required
68 (7C385A) to 114 (7C386A) bidirectional input/output pins
6 dedicated input/high-drive pins
2 clock/dedicated input pins with fanout-independent, low-skew nets
- Clock skew < 1 ns
Input hysteresis provides high noise
immunity
Thorough testability
- Built-in scan path permits 100 percent factory testing of logic and I/O
cells
- Automatic Test Vector Generation
(ATVG) software supports user
testing after programming
0.65!t CMOS process with ViaLink®
programming technology
- High-speed metal-to-metallink
- Non-volatile antifuse technology
84-pin PLCC is compatible with the
CY7C384 footprint for easy upgrade
Functional Description
The CY7C385A and CY7C386A are
members of the pASIC380 family of very
high speed CMOS user-programmable
ASIC (pASIC) devices. The 384 logic cell
field-programmable gate array (FPGA) offers 4,000 typically usable "gate array"
gates. This is equivalent to 12,000 EPLD
or LCA gates. The CY7C385A is available
in a 84-pin PLCC and CLCC. The
CY7C386A is available in 144-pin PQFP
and PGA packages.
Low-impedance, metal-to-metal ViaLink
interconnect technology provides non-volatile custom logic capable of operating at
speeds above 100 MHz with input and output delays under 4 ns. This permits highdensity programmable devices to be used
with today's fastest CISC and RISC microprocessors.
Designs are entered into the CY7C385A
and CY7C386A using Cypress Wa1p3 software or one of several third-party tools.
Wa1p3 is a sophisticated CAE package that
features schematic entry, waveform-based
timing simulation, and VHDL design synthesis. The CY7C385A and CY7C386A
feature ample on-chip routing channels for
fast, fully automatic place and route of high
gate utilization designs.
For detailed information about the
pASIC380 architecture, see the pASIC380
Family datasheet.
LoglC
. BIOCkD'13gram
. . . . . . . . . .. ... . . . . . .. . . .
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO DO:
DO DO:
DO DO:
DO o O-'L---DO 10:
DO o D r - DO DO
DO DO
DO DO
DO DO
DO DO
DO DO
DO DO
DO DO
DO DO
DO DO
•
~
w~~
~
Vialink is a trademark of QuickLogic Corporation.
4-288
R
r----r--
I
I/O/HIGH-DRIVE INPUT/
CLOCK CEllS
144 PINS, 114 I/O CEllS, 6 INPUT HIGH DRIVE CELLS, 2 INPUT/ClK (HIGH DRIVE) CEllS
Document #: 38-00209-A
j
c386-1
~
,
=
PLD Programming Information
CYPRESS
SEMICONDUCTOR
Introduction
PLDs, or programmable logic devices, provide an attractive alternative to logic implemented with discrete devices. Cypress Semiconductor is in the enviable position of being able to offer PLDs in
several different process technologies, thus assuring our customers
of a wide range of options for leading-edge speed as well as very
low power consumption. Cypress optimizes the mix of technology
and device architecture to insure that the programmable logic requirementsoftoday'shighest-performanceelectronicssystemscan
be fully supported by a single PLD vendor.
Cypress offers a wide variety of PLDs based on our leading-edge
CMOS EPROM process technology. This technology facilitates
the lowest power consumption and the highest logic density of any
nonvolatile PLD technology on the market today, at speeds that
are nearly as fast as state-of-the-art bipolar technology would provide. Futhermore, these devices offer the user the option of device
erasure and reprogrammability in windowed packages. Cypress
also offers a number of PLDs based on our state-of-the-art BiCMOS and bipolar technologies. These PLDs are targeted at applications where power consumption and density are not as critical
as leading-edge speed. And in, 1992 Cypress introduced PLDs
based on CMOS Flash technology. Thus Cypress offers solutions
for state-of-the-art systems regardless of what the optimal balance
is between speed, power, and density for any particular system.
Programmable Technology
EPROM Process Technology
EPROM technology employs a floating or isolated gate between
the normal control gate and the source/drain region of a transistor.
This gate may be charged with electrons during the programming
operation,permanently turning off the transistor. The state ofthe
floating gate, charged or uncharged, is permanent because the gate
is isolated in an extremely pure oxide. The charge may be removed
if the device is irradiated with ultraviolet energy in the form of
light. This ultraviolet light allows the electrons on the gate to recombine and discharge the gate. This process is repeatable and
therefore can be used during the processing of the device, repeatedly if necessary, to assure programming function and performance.
1\vo 'fransistor Cells
first PLDs based on CMOS Flash technology in 1992. The Flash
cell is programmed in the same manner as the EPROM cell, and is
electrically erased via Fowler-Nordheim tunneling. This next-generation PLD technology will combine a number of key advantages
for wture Cypress PLDs. The principal advantages will be leadingedge speed, low CMOS power consumption, and electrical alterability for simplified inventory management. In addition, Flash
technology offers two inherent advantages for PLDs over the commonlyused full-features EE CMOS technology. One is its superior
migratability to higher logic densities, due to the smaller Flash cell
size. The second is superior reliability, due to the Flash cell's higher
immunity to voltage transients and the accompanying risk of data
corruption.
Programming Algorithm
Byte Addressing and Programming
Most Cypress programmable logic devices are addressed and programmed on a byte or extended byte basis where an extended byte
is a filed that is as wide as the output path ofthe device. Each device
or family of devices has a unique address map that is available in
the product datasheet. Each byte or extended byte is written into
the addressed location from the pins that serve as the output pins in
normal operation. To program a cell, a 1 or HIGH is placed on the
input pin and a 0 or LOW is placed on pins corresponding to cells
that are not to be programmed. Data is also read from these pins in
parallel for verification after programming. A 1 or HIGH during
program verify operation indicates an unprogrammed cell, while a
oor LOW indicates that the cell accessed has been programmed.
Blank Check
Before programming, all programmable logic devices may be
checked in a conventional manner to determine that they have not
been previously programmed. This is accomplished in a program
verify mode of operation by reading the contents of the array. Duringthisoperation, a 1 or HIGH output indicates thatthe addressed
cell is unprogrammed, while a 0 or LOW indicates a programmed
cell.
Programming the Data Array
In addition to CMOS, Cypress offers BiCMOS TTL and bipolar
ECLI/O-compatible PLDs. The BiCMOS devices offer the advantages of CMOS (high density and low power) and bipolar (high
speed). Both the BiCMOS and bipolar devices are one-time fuse
programmable. The fuses are Ti-W and are connected directly to
first metal. First metal is a reliable composite of Ti-TiW-AlSi-Ti to
ensure excellent electromigration resistance, eliminate contact
spiking, and minimize hillocking.
Flash Process Technology
Programming is accomplished by applying a supervoltage to one
pin of the device causing it to enter the programming mode of operation. This also provides the programming voltage for the cells to
be programmed. In this mode of operation (except for the
CY7C361), the address lines ofthe device are used to address each
location to be programmed, and the data is presented on the pins
normally used for reading the contents of the device. Each device
has a read/write pin in the programming mode. This signal causes
a write operation when switched to a supervoltage and a read operation when switched to a logic 0 or LOW. In the logic HIGH or 1
state, the device is in a program inhibit condition and the output
pins are in a high-impedance state. During a write operation, the
data on the output pins is written into the addressed array location.
In a read operation, the contents of the addressed location are
present on the output pins and may be verified. Programming
therefore is accomplished by placing data on the output pins and
writing it into the addressed location. Verification of data is accomplished by examining the information on the output pins during a
read operation.
In addition to offering PLDs based on EPROM, BiCMOS and
high-performance bipolar technologies, Cypress introduced our
The timing for actual programming is supplied in the unique programming specification for each device.
Cypress uses a two-transistor EPROM cell. One transistor is optimized for reliable programming, and one transistor is optimized
for high speed. The floating gates are connected such that charge
injected on the floating gate of the programming transistor is conducted to the read transistor biasing it off.
BiCMOS and Bipolar Process Technology
4-289
I
~
en
Q
~
~;iiPRE§
PLD Programming Information
~; SEMICONDUCTOR
Phantom Operating Modes
All Cypress programmable logic devices except for the Flash PLDs
contain a Phantom array for post assembly testing. This array is accessed, programmed, and operated in a special Phantom mode of
operation. In this mode, the normal array is disconnected from
control of the logic, and in its place the Phantom array is connected. In normal operation the Phantom array is disconnected
and control is only via the normal array. This special feature allows
every device to be tested for both functionality and performance
after packaging and, if desired, by the user before programming
and use. The Phantom modes are entered through the use of supervoltages and are unique for each device or family of devices. See
specific datasheets for details.
Special Features
Cypress programmable logic devices, depending on the device,
have several special features. For example, the security mechanism
defeats the verify operation and therefore secures the contents of
the device against unauthorized tampering or access. In advanced
devices such as the PALC22V10, PLDC20G 10, and CY7C330, the
macrocells are programmable through the use of the architecture
bits. This allows users to more effectively tailor the device architecture to their unique system requirements. Specific programming is
detailed in the device datasheet.
Programming Support
Programming support for Cypress programmable logic devices is
available from a number of programmer manufacturers, some of
which are listed here. They can be contacted directly for information regarding programming support of Cypress devices. Alternatively, all Cypress sales representatives and distributors have access
to this information.
Cypress Semiconductor Inc.
3901 North First Street
San Jose, CA 95134
(408) 943-2600
Data I/O Corporation
10525 Willows Rd., N.E.
P.O. Box 97046
Redmond, WA 98073-9746
(206) 881-6444
Digelec Corporation
1602 Lawrence Ave.
Document #: 38-00164-A
Suite 113
Ocean, NJ 07712
(201) 493-2420
Kontron Electronics
1230 Charleston Road
Mountain View, CA 94039-7230
(415) 965 -7020
Logical Devices Inc.
1201 N.W. 65th Place
Ft. Lauderdale, FL 33309
(305) 974-0975
SMS Mikrocomputersysteme GmbH
1m Morgental13, D-8994 Hergatz
Germany 5018
(49) 7522-5018 (phone)
(49) 7522-8929 (fax)
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054
(408) 988-1118
STAG ZL32 Rev. 30A03
Third·Party Development Software
ABEL@)
Data I/O Corporation
10525 Willows Rd. N.E.
P.O. Box 97046
Redmond, WA 98073-9764
(206) 881-6444
CUPL@)
Logical Devices Inc.
1201 N.W. 65th Place
Ft. Lauderdale, FL 33309
(305) 974-0975
LOG/iC@)
ISDATAGmbH
Haid-und-Neu-Strasse 7
D-7500 Karlsruhe 1
Germany
(0721) 69 30 92
ABEL is a trademark of Data I/O Corporation.
CUPL is a trademark of Assisted Technology.
ISDATA is a registered trademark of ISDATA GmbH.
LOG/iC is a trademark of ISDATA GmbH.
4-290
INFO
II
SRAMs
I
I
I'
'i
PROMs
PlDs
FIFOs
lOGIC
'1
DATACOM
MODULES
.:1
ECl
,.
BUS
lin
MiliTARY
Ii'
ItJ
IN
I'i
TOOLS
QUALITY
PACKAGES
1:i7~
FIFOs
Device Number
CY7C401
CY7C402
CY7C403
CY7C404
CY7C408A
CY7C409A
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
CY7C421A
CY7C425A
CY7C429A
CY7C433A
CY7C432
CY7C433
CY7C439
CY7C441
CY7C443
CY7C445
CY7C446
CY7C447
CY7C455
CY7C456
CY7C457
CY7C451
CY7C453
CY7C460
CY7C462
CY7C464
CY7C470
CY7C472
CY7C474
Section Contents
Page Number
Description
64 x 4 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 5 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
64 x 4 Cascadable FIFO with Output Enable ...................................... 5-1
64 x 5 Cascadable FIFO with Output Enable ...................................... 5-1
64 x 8 Cascadable FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-12
64 x 9 Cascadable FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -12
512x 9 Cascadable FIFO ..................................................... 5-26
512x 9 Cascadable FIFO ..................................................... 5-26
1Kx 9 Cascadable FIFO ...................................................... 5-26
1Kx 9 Cascadable FIFO ...................................................... 5-26
2K x 9 High-Speed Cascadable FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-26
2Kx 9 High-Speed Cascadable FIFO ............................................ 5-26
512 x 9 High-Speed Cascadable FIFO ........................................... 5-44
1Kx 9 High-Speed Cascadable FIFO ............................................ 5-44
2Kx 9 High-Speed Cascadable FIFO ............................................ 5-53
4Kx 9 High-Speed Cascadable FIFO ............................................ 5-53
4K x 9 Cascadable FIFO ...................................................... 5-62
4Kx 9 Cascadable FIFO ...................................................... 5-62
2K x 9 Bidirectional FIFO ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 -76
512x9ClockedFIFO ........................................................ 5-89
2K x 9 Clocked FIFO ........................................................ , 5 -89
Cascadable Clocked 512 x 18 FIFO wi Programmable Flags . . . . . . . . . . . . . . . . . . . . . . .. 5 -105
Cascadable Clocked 1K x 18 FIFO wi Programmable Flags ........................ 5-105
Cascadable Clocked 2K x 18 FIFO wi Programmable Flags ........................ 5 -105
Cascadable Clocked 512 x 18 FIFO wi Programmable Flags. . . . . . .. . . . . . . . . . . . . . . .. 5-105
Cascadable Clocked 1Kx 18 FIFO wi Programmable Flags ........................ 5-105
Cascadable Clocked 2Kx 18 FIFO wi Programmable Flags ........................ 5-105
512 x 9 Cascadable Clocked FIFO wi Programmable Flags. . . . . . . . . . . . . . . . . . . . . . . .. 5-127
2K x 9 Cascadable Clocked FIFO wi Programmable Flags ......................... 5 -127
8K x 9 Cascadable FIFO ..................................................... 5 -150
16K x 9 Cascadable FIFO .................................................... 5 -150
32K x 9 Cascadable FIFO .................................................... 5 -150
8K x 9 FIFO wi Programmable Flags ........................................... 5 -163
16K x 9 FIFO wi Programmable Flags .......................................... 5 -163
32K x 9 FIFO wi Programmable Flags .......................................... 5 -163
CY7C401/CY7C403
CY7C402/CY7C404
CYPRESS
SEMICONDUCTOR
Cascadable 64 X 4 FIFO and
64x5 FIFO
Features
Functional Description
• 64 x 4 (CY7C401 and CY7C403)
64 x 5 (CY7C402 and CY7C404)
High-speed first-in first-out memory
(FIFO)
• Processed with high-speed CMOS for
optimum speed/power
• 25-MHz data rates
• 50-ns bubble-through time-25 MHz
• Expandable in word width and/or
length
• 5-volt power supply ±10% tolerance,
both commercial and military
• Independent asynchronous inputs
and outputs
• TTL-compatible interface
• Output enable function available on
CY7C403 and CY7C404
• Capable of withstanding greater than
2001V electrostatic discharge
• Pin compatible with MMI
67401A/67402A
The CY7C401 and CY7C403 are asynchronous first-in first-out memories (FIFOs)
organized as 64 four-bit words. The
CY7C402 and CY7C404 are similar FIFOs organized as 64 five-bit words. Both
the CY7C403 and CY7C404 have an output enable (OE) function.
The devices accept 4- or 5-bit words at the
data input (DIo - DIn) under the control
of the shift in (SI) input. The stored words
stack up at the output (DOo - DOn) in the
order they were entered. A read command
on the shift out (SO) input causes the next
to last word to move to the output and all
data shifts down once in the stack. The input ready (IR) signal acts as a flag to indicate when the input is ready to accept new
data (HIGH), to indicate when the FIFO is
full (LOW), and to provide a signal for cascading. The output ready (OR) signal is a
flag to indicate the output contains valid
data (HIGH), to indicate the FIFO is
empty (LOW), and to provide a signal for
cascading.
Parallel expansion for wider words is accomplished by logically ANDing the IR
and OR signals to form composite signals.
Serial expansion is accomplished by tying
the data inputs of one device to the data
outputs of the previous device. The IR pin
of the receiving device is connected to the
SO pin of the sending device, and the OR
pin of the sending device is connected to
the SI pin of the receiving device.
Reading and writing operations are completely asynchronous, allowing the FIFO
to be used as a buffer between two digital
machines of widely differing operating frequencies. The 25-MHz operation makes
these FIFOs ideal for high-speed communication and controller applications.
Pin Configurations
Logic Block Diagram
DIP
(CY7C401) NC
(CY7C403) OE
IR
SI
IR
WRITE POINTER
WRITE MULTIPLEXER
1
2
DIP
15
m:
01 0
11
10
01 3
01 0
01 1
01 2
01 3
01 4
000
001
002
003
MR
GNO
01 1
(CY7C402) NC
Vee (CY7C404) OE
IR
SO
OR
51
000
01 2
MEMORY
ARRAY
013
GNO
4
5
6
18
17
16
003
(004)
000
001
002
003
004
14
13
12
11
10
9
MR
C401-4
Lee
IQ t.l
002
Vee
SO
OR
g~~g:g~15
C401-2
001
(014)
3
Lee
~~~}lg
REAO MULTIPLEXER
MR
SI
REAO POINTER
SO
OR
C401-1
3 2,1: 2019
18
01 0
01 1
01 2
CY7C401 17
CY7C403 ~~
NC
14
910111213
NC
OR
OR
SI
000
001
002
003
01 0
01 1
012
01 3
000
001
002
B~I~g~
c5~ 1~8'~
C401-3
C401-5
Selection Guide
7C401/2-5
7C40X-IO
7C40X-15
7C40X-25
5
75
10
75
90
15
25
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
I
I
Commercial
Military
5-1
75
75
90
90
•
en
ou.
Ii:
CY7C40l/CY7C403
CY7C402/CY7C404
Maximum ~atings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Static Discharge Voltage ....................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Supply Voltage to Ground Potential. " .... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to +7.0V
DC Input Voltage ...................... - 3.OV to +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Output Current, into Outputs (LOW) .. . . . . . . . . . . .. 20 rnA
Operating Range
Ambient
Temperature
Range
Commercial
Military[l]
O°C to +70°C
Vee
5V ±1O%
- 55°C to +125°C
5V ±1O%
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[2]
7C40X -10, 15, 25
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Voltage
Min.
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
2.4
2.0
VIL
Input LOW Voltage
IIX
Input Leakage Current
VeD[3]
Input Diode Clamp Voltagel 3]
loz
Output Leakage Current
los
Output Short Circuit Currend 4]
Vee
lee
Power Supply Current
Vee
Units
Max.
V
0.4
V
6.0
V
- 3.0
0.8
V
GND~ VI.s Vee
-10
+10
!!A
GND.s VOUT.s Vee, Vee = 5.5V
Output Disabled (CY7C403 and CY7C404)
- 50
+50
f!A
- 90
rnA
75
rnA
90
rnA
= Max., VOUT = GND
= Max., lOUT = ornA I Commercial
I
Military
Capacitance[S]
Parameters
Description
Test Conditions
TA = 25°C, f
Vee = 4.5V
Input Capacitance
CIN
Output Capacitance
COUT
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. The CMOS process does not provide a clamp diode. However, the
FIFO is insensitive to - 3V dc input levels and - 5V undershoot pulses
of less than 10 ns (measured at 50% output).
5V
4.
5.
OUTPUT
INCLUDING
JIG AND
SCOPE
J
-
-
R2
272n
5VSfl
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
J
-
(b)
-
pF
7
pF
ALL INPUT PULSES
R1437n
TI
30 pF
Units
5
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1437n
Max.
= 1 MHz,
3.0V---90%
R2
272n
GND
-
C401-6
I
Equivalent to:
THEVENIN EQUIVALENT
167n
OUTPUT ~ 1.73V
C401-8
5-2
C401-7
CY7C401/CY7C403
CY7C402/CY7C404
~
.
~CYPRFS5
,
SEMICONDUCTOR
Switching Characteristics Over the Operating Range[2, 6]
Parameters
Description
7C401-5
7C40X-IO 7C40X-15 7C40X-25[7]
7C402-5
Test
Conditions Min. Max. Min. Max. Min. Max. Min. Max.
Operating Frequency
tpHSI
SIHIGHTime
20
20
20
11
ns
tpLSI
SO LOW Time
45
30
25
20
ns
tSSI
Data Set-Up to SI
Note 9
0
0
0
0
ns
tHSI
Data Hold from SI
Note 9
60
tDLIR
Delay, SI HIGH to IR LOW
75
40
35
21/22
ns
tDHIR
Delay, SI LOW to IR HIGH
75
45
40
28/30
ns
tpHSO
SO HIGH Time
20
20
20
11
ns
tpLSO
SO LOW Time
45
25
25
20
ns
tDLOR
Delay, SO HIGH to OR LOW
tDHOR
Delay, SO LOW to OR HIGH
tSOR
Data Set-Up to OR HIGH
0
0
0
0
ns
tHSO
Data Hold from SO LOW
5
5
5
5
ns
tBT
Bubble-Through Time
tSIR
Data Set-Up to IR
Note 10
5
5
5
5
ns
tHIR
Data Hold from IR
Note 10
30
30
30
20
ns
tpIR
Input Ready Pulse HIGH
20
20
20
15
ns
tpOR
Output Ready Pulse HIGH
20
20
20
15
ns
tpMR
MR Pulse Width
40
30
25
25
ns
tDSI
MR HIGH to SI HIGH
40
35
25
10
ns
10
5
Note 8
15
Units
fo
40
25
20
30
MHz
ns
75
40
35
19/21
ns
80
55
40
34/37
ns
200
10
95
10
65
10
50/60
ns
tDOR
MR LOW to OR LOW
85
40
35
35
ns
tDIR
MR LOW to IR HIGH
85
40
35
35
ns
tLZMR
MR LOW to Output LOW
tOOE
Output Valid from OE LOW
tHZOE
Output High Z from OE HIGH
Note 11
Note 12
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOrJIOH and
30-pF load capacitance, as in part (a) of AC Test Loads and Waveforms.
7. Commercial/Military
8. IIfo > tpHSI + tDHIR, IIfo > tpHSO + tDHOR
9. tSSI and tHSI apply when memory is not full.
50
40
35
25
ns
-
35
30
20
ns
-
30
25
15
ns
10. tSIR and tHIR apply when memory is full, SI is high and minimum
bubble-through (tBT) conditions exist.
11. All data outputs will be at LOW level after reset goes HIGH until data
is entered into the FIFO.
12. HIGH-Z transitions are referenced to the steady-state VOH - 500 m V
and VOL +500 m V levels on the output. tHzOE is tested with 5-pFload
capacitance as in part (b) of AC Test Loads and Waveforms.
5-3
•
CY7C401/CY7C403
CY7C402/CY7C404
,~
-== F= SEMICONDUCTOR
====="
CYPRESS
Operational Description
Concept
Unlike traditional FIFOs, these devices are designed using adualport memory, read and write pointer, and control logic. The read
and write pointers are incremented by the SO and SI respectively.
The availability of an empty space to shift in data is indicated by the
IR signal, while the presence of data at the output is indicated by
the OR signal. The conventional concept of bubble-through is absent. Instead, the delay for input data to appear at the output is the
time required to move a pointer and propagate an OR signal. The
output enable (OE) signal provides the capability to OR tie multiple FIFOs together on a common bus.
Resetting the FIFO
Upon powe-up, the FIFO must be reset with a master reset (MR)
signal. This causes the FIFO to enter an empty condition signified
by the OR signal being LOW at the same time the IR signal is
HI GH. In this condition, the data outputs (DOo - DOn) will be in
a LOW state.
Shifting Data In
Data is shifted in on the rising edge of the SI signal. This loads input data into the first word location of the FIFO. On the falling
edge of the SI signal, the write pointer is moved to the next word
position and the IR signal goes HIGH, indicating the readiness to
accept new data. If the FIFO is full, the IR will remain LOW until
a word of data is shifted out.
Shifting Data Out
Data is shifted out of the FIFO on the falling edge of the SO signal.
This causes the internal read pointer to be advanced to the next
word location. If data is present, valid data will appear on the outputs and the OR signal will go HIGH. If data is not present, the OR
signal will stay LOW indicating the FIFO is empty. Upon the rising
edge of SO, the OR signal goes LOW. The data outputs of the
FIFO should be sampled with edge-sensitive type D flip-flops (or
equivalent), using the SO signal as the clock input to the flip-flop.
Bubble-Through
Two bubble-through conditions exist. The first is when the device is
empty. After a word is shifted into an empty device, the data propagates to the output. After a delay, the OR flag goes HIGH, indicating valid data at the output.
The second bubble-through condition occurs when the device is
full. Shifting data out creates an empty location that propagates to
the input. After a delay, the IR flag goes HIGH. If the SI signal is
HIGH at this time, data on the input will be shifted in.
Possible Minimum Pulse Width Violation at the Boundary Conditions
If the handshaking signals IR and OR are not properly used to generate the SI and SO signals, it is possible to violate the minimum
(effective) SI and SO positive pulse widths at the full and empty
boundaries.
be aware of a window oftime which follows the initial rising edge of
the OR signal, during which time the SO signal is not recognized.
This condition exists only at high-speed operation where more than
one SO may be generated inside the prohibited window. This condition does not inhibit the operation ofthe FIFO at full-frequency
operation, but rather delays the full 25-MHz operation until after
the window has passed.
There are several implementation techniques for managing the
window so that all SO signals are recognized:
1. The first involves delaying SO operation such that it does not
occur in the critical window. This can be accomplished by causing a fixed delay of 40 ns "initiated by the SI signal only when
the FIFO is empty" to inhibit or gate the SO activity. However,
this requires that the SO operation be at least temporarily synchronized with the input SI operation. In synchronous applications this may well be possible and a valid solution.
2. Another solution not uncommon in synchronous applications
is to only begin shifting data out of the FIFO when it is more
than half full. This is a common method of FIFO application,
as earlier FIFOs could not be operated at maximum frequency
when nearfull or empty. Although Cypress FIFOs do not have
this limitation, any system designed in this manner will not encounter the window condition described above.
3. The window may also be managed by not allowing the first SO
signal to occur until the window in question has passed. This
can be accomplished by delaying the SO 40 ns from the rising
edge of the initial OR signal. This however involves the requirement that this only occurs on the first occurrence of data
being loaded into the FIFO from an empty condition and
therefore requires the knowledge of IR and SI conditions as
well as SO.
4. Handshaking with the OR signal is a third method of avoiding
the window in question. With this technique the rising edge of
SO, or the fact that SO signal is HIGH, will cause the OR signal
to go LOW. The SO signal is not taken LOW again, advancing
the internal pointer to the next data, until the OR signal goes
LOW. This ensures thatthe SO pulse that is initiated in the window will be automatically extended long enough to be recognized.
5. There remains the decision as to what signal will be used to
latch the data from the output of the FIFO into the receiving
source. The leading edge of the SO signal is most appropriate
because data is guaranteed to be stable prior to and after the
SO leading edge for each FIFO. This is a solution for any number of FIFOs in parallel.
Any of the above solutions will ensure the correct operation of a
Cypress FIFO at 25 MHz. The specific implementation is left to
the designer and is dependent on the specific application needs.
When this violation occurs, the operation ofthe FIFO is unpredictable. It must then be reset, and all data is lost.
Application of the 7C403-25/7C404-25 at 25 MHz
Application of the CY7C403 or CY7C404 Cypress CMOS FIFOs
requires knowledge of characteristics that are not easily specified
in adatasheet, but which are necesS'ary for reliable operation under
all conditions, so we will specify them here.
When an empty FIFO is filled with initial information at maximum
"shift in" SI frequency, followed by immediate shifting out of the
data also at maximum "shift out" SO frequency, the designer must
5-4
CY7C40l/CY7C403
CY7C402/CY7C404
~
~~CYPRESS
iF
SEMICONDUCTOR
Switching Waveforms
Data In Timing Diagram
SHIFT IN
INPUT READY
DATA IN
C401-9
I
en
oLL
Data Out Timing Diagram
u:::
SHIFT OUT
OUTPUT READY
DATA OUT
C401-10
Bubble Through, Data Out To Data In Diagram
SHI80UT~
SHIFT IN
INPUT READY
t
tBT
.. I
,,-----
DATA IN
tSIR - - - " - - - - tHIR ----I~
C401-11
5-5
CY7C401/CY7C403
CY7C402/CY7C404
Switching Waveforms (continued)
Bubble Through, Data In To Data Out Diagram
SHIFT IN
/
_-J
SHIFT OUT
J
1 4 - - - - tBr - - -.....- - -
OUTPUT READY
~---------------
____________________________~tSOR
DATA OUT
----------------------~
C401-12
Master Reset Timing Diagram
I--MASTER RESET
~~
tpMR---
,)1{
tOIR
~
jrt:
INPUT READY
tOOR
~,
OUTPUT READY
tOSI
SHIFT IN
I
}
~1.~_-t~MR---}~
DATA OUT
----------------------~--------------------------C401-13
Output Enable Timing Diagram
OUTPUT ENABLE
DATA OUT
C401-14
5-6
CY7C401/CY7C403
CY7C402/CY7C404
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
..s
1.4
1.2
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
8f:lij 1il
4 3 2: 1, 2B 27 26
25
5
6
24
7
23
7C40BA
8
22
7C409A
9
21
10
20
11
19
12131415161718
OR
DOo
D0 1
GND
D02
D0 3
D04
C40BA-2
5-12
CY7C408A
CY7C409A
'~PRESS
--=-F
·
SEMICONDUCTOR
Selection Guide
7C408A-15
7C409A-15
Maximum Shift Rate (MHz)
Maximum Operating
Current (rnA)[l]
7C408A-25
7C409A-25
7C408A-35
7C409A-35
15
25
35
I Commercial
115
125
135
I Military
140
150
N/A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Output Current, into Outputs (Low) ............... 20 rnA
Static Discharge Voltage ........................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................. - 65 ° C to + 150 ° C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State (7C408A) . . . . . . . . . . . . . .. - O.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.OW
Operating Range
Ambient
Temperature
Range
Commercial
Military[2]
O°Cto +70°C
Vee
5V ±1O%
- 55°C to + 125°C
5V ±1O%
Description
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIR
Input HIGH Voltage
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
VIL
Input LOW Voltage
Input Leakage Current
los
Output Short Circuit Currentl 4 J
Vee
leeQ
Quiescent Power Supply Current
Vee = Max., lOUT = 0 rnA
VIN ~ VIL, VIN L VIR
GND~VI~Vee
Power Supply Current
= Max., VOUT = GND
Max.
Units
2.4
2.2
Ilx
Icc
u:::
Min.
Test Conditions
VOH
V
0.4
V
Vee
V
- 3.0
0.8
V
-10
+10
f.tA
- 90
rnA
100
rnA
125
rnA
I Commercial
I Military
Icc = ICCQ + 1 mA/MHz X (fsl + fso)/2
Capacitance[5]
Parameters
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
Max.
5
TA = 25°C, f = 1 MHz,
Vcc = 4.5V
7
Units
pF
pF
Notes:
1.
2.
3.
4.
Icc = ICCQ + 1 mAlMHz X (fSI + fso)/2
TA is the "instant on" case temperature.
See the last page ofthis specification for Group A subgroup testing information.
5VSF1 5V39
5.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1482[1
R1482n
OUTPUT
CL
I
INCLUDING
JIG AND
SCOPE
R2
256[1
30 pF
-
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
-
J
-
ALL INPUT PULSES
3.0V---90%
R2
256[1
_
-
(b)
C40BA-5
I
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT
GND
C40BA·4
(a)
167[1
o------vw---o
1.73V
C40BA·6
5-13
en
oLL.
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[3]
Parameters
I
CY7C408A
CY7C409A
EiflII"
~~PRF.SS
~, SEMICONDUcrOR
Switching Characteristics Over the Operating Rangd 2,6]
Parameters
Description
7C408A-15
7C409A-15
Test
Conditions
Min.
Max.
7C408A-25
7C409A-25
Min.
Max.
7C408A-35
7C409A-35
Min.
25
15
Max.
Units
35
MHz
fo
Operating Frequency
Note 7
tpHSI
SIHIGHTime
Note 7
23
11
9
ns
tpLSI
SILOWTime
Note 7
25
24
17
ns
tSSI
Data Set-Up to SI
Note 8
0
0
0
ns
tHSI
Data Hold from SI
Note 8
30
20
12
tDUR
Delay, SI HIGH to IR LOW
35
21
15
ns
tDHIR
Delay, SI LOW to IR HIGH
40
23
16
ns
tpHSO
SO HIGH Time
Note 7
23
11
9
tpLSO
SO LOW Time
Note 7
25
24
17
tDLOR
Delay, SO HIGH to OR LOW
35
21
15
ns
tDHOR
Delay, SO LOW to OR HIGH
40
23
16
ns
tSOR
Data Set-Up to OR HIGH
0
0
0
tHSO
Data Hold from SO LOW
0
0
0
tBT
Fall-through, Bubble-back Time
10
tSIR
Data Set-Up to IR
Note 9
65
10
60
10
ns
ns
ns
ns
ns
50
ns
5
5
5
ns
20
ns
ns
tHIR
Data Hold from IR
Note 9
30
20
tpIR
Input Ready Pulse HIGH
Note 10
6
6
6
tpOR
Output Ready Pulse HIGH
Note 11
6
6
6
tDLZOE
OE LOW to LOW Z (7C408A)
Note 12
35
30
25
ns
tDHZOE
OE HIGH to HIGH Z (7C408A)
Note 12
35
30
25
ns
tDHHF
SI LOW to HF HIGH
65
55
45
ns
tDLHF
SO LOW to HF LOW
65
55
45
ns
tDLAFE
SO or SI LOW to AFE LOW
65
55
45
ns
tDHAFE
SO or SI LOW to AFE HIGH
65
55
45
ns
tpMR
MR Pulse Width
55
45
35
tDSI
MR HIGH to SI HIGH
25
10
10
tDOR
MR LOW to OR LOW
55
45
35
ns
tmR
MR LOW to IR HIGH
55
45
35
ns
tLZMR
MR LOW to Output LOW
55
45
35
ns
tAFE
MR LOW to AFE HIGH
55
45
35
ns
tHF
MR LOW to HF LOW
55
45
35
ns
tOD
SO LOW to Next Data Out Valid
28
20
16
ns
Note 13
ns
ns
ns
Notes:
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOrlIOH and
30-pF load capacitance, as in parts (a) and (b) of AC Test Loads and
Waveforms.
7. l/fo ~ (tPHSI + tPLSI), l/fo ~ (tpHSO + tpLSO)·
8. tSSI and tHSI apply when memory is not full.
9. tSIR and tHIR apply when memory is full, SI is high and minimum
bubble-through (tBT) conditions exist.
10. At any given operating condition tplR L (tpHSO required).
11. At any given operating condition tpOR ~ (tPHSI required).
12. tDHZOE and tDLZOE are specified with CL = 5 pF as in part (b) of AC
Test Loads and Waveforms. tDHZOE transition is measured ±500 m V
from steady-state voltage. tDLZOE transition is measured ± 100 m V
from steady-state voltage. These parameters are guaranteed and not
100% tested.
13. All data outputs will be at LOW level after reset goes HIGH until data
is entered into the FIFO.
5-14
CY7C408A
CY7C409A
~~
---=-,'=
CYPRF.SS
SEMICONDUCTOR
Switching Waveforms
Data In Timing Diagram
SHIFT IN
INPUT READY
•
DATA IN
en
AFE
oLL
u:::
HF
(LOW)
C40SA-7
Data Out Timing Diagram
1 . . - - - - - I/fo
-----++_----
I/fo - - - - - + I
SHIFT OUT
OUTPUT READY
DATA OUT
HF
(LOW)
AFE ________________________________________
~_tD_H__AF:fr=------------------------C40SA-S
Notes:
14. FIFO contains 8 words.
15. FIFO contains 9 words.
5-15
CY7C408A
CY7C409A
~
.n~NDucrOR
Switching Waveforms (continued)
Data In Timing Diagram
1 4 - - - - - - lIfo - - - - -....- - - - - lIfo
-----~
SHIFT IN
INPUT READY
DATA IN
AFE
(LOW)
IDHH';____________
HF
C40BA-9
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
HF
(LOW)
AFE
C40BA-10
Output Enable (CY7C408A only)
~
OU!PUTENABLE
~
!.=
_ _ _ _ _ _ _ _ _t_D_HZ_OE
DATA OUT
-----______
NOTE 12
IoLZOE
~-------------
C4DBA-11
Notes:
16. FIFO contains 31 words.
17. FIFO contains 32 words.
5-16
CY7C408A
CY7C409A
~:~
~.aCYPRESS
~,
SEMICONDUCTOR
Switching Waveforms (continued)
Data In Timing Diagram
SHIFT IN
INPUT READY
DATA IN
HF
AFE
Data Out Timing Diagram
SHIFT OUT
OUTPUT READY
DATA OUT
AFE
HF
(HIGH)
Bubble-Back, Data Out To Data In Diagram
SHIFTOUT:;OTE20
SHIFT IN
t
C40BA-13
------+------------------,'-_______
1 4 - - - - tBT
-----+I.'
"-
INPUTREADY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
J
DATA IN
tSIR
Notes:
18. FIFO contains 55 words.
19. FIFO contains 56 words.
•
U)
C40BA-12
_014----
20. FIFO contains 64 words.
5-17
C40BA-14
oLL.
u::
CY7C408A
CY7C409A
~
=-...
~
_ ' j ; ; CYPRESS
- , SEMICONDUcrOR
Switching Waveforms (continued)
Fall-Through, Data In to Data Out Diagram
SHIFT IN
NOTE 21
SHIFT OUT
/
J
~--- tBT
---""*If---
OUTPUT READY
______
~tSOR
DATA OUT
--------------------------~
C408A-15
Master Reset Timing Diagram
MASTER RESET
.
I+--
tpMR-
~K
/1{:
tOIR
}~
INPUT READY
tOOR
~K
OUTPUT READY
tOSI
SHIFT IN
}-
tLZMR
~,
DATA OUT
HF
AFE
~tHF
I---
tAFE
'\
"
,
,I
C408A-16
Note:
21. FIFO is empty.
5-18
4: =::z
-.
CY7C408A
CY7C409A
' . CYPRESS
~,
SEMICONDUCTOR
Architecture of the CY7C408A and CY7C409A
Shifting Data Into the FIFO
The CY7C408A and CY7C409A FIFOs consist of an array of 64
words of 8 or 9 bits each (which are implemented using a dual-port
RAM cell), a write pointer, a read pointer, and the control logic
necessary to generate the handshaking (SIIIR, SO/OR) signals as
well as the almost full/almost empty (AFE) and half full (HF) flags.
The handshaking signals operate in a manner identical to those of
the industry standard CY7C40l/402/403/404 FIFOs.
The availability of an empty location is indicated by the HIGH
state ofthe input ready (IR) signal. When IR is HIGH a LOW to
HIGH transition on the shift in (SI) pin will clock the data on the
DIa - DIg inputs into the FIFO. Data propagates through the device at the falling edge of SI.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve
truly asynchronous operation of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
to propagate through the memory, which it would have to do if the
memory were implemented using the conventional register array
architecture.
Fall-Through and Bubble-Back
The time required for data to propagate from the input to the output of an initially empty FIFO is defined as the fall-through time.
The time required for an empty location to propagate from the output to the input of an initially full FIFO is defined as the bubbleback time.
The maximum rate at which data can be passed through the FIFO
(called the throughput) is limited by the fall-through time when it
is empty (ornear empty) and by the bubble-back time when it is full
(or near full).
The conventional definitions of fall-through and bubble-back do
not apply to the CY7C408A and CY7C409A FIFOs because the
data is not physically propagated through the memory. The read
and write pointers are incremented instead of moving the data.
However, the parameter is specified because it does represent the
worst-case propagation delay for the control signals. That is, the
time required to increment the write pointer and propagate a signal from the SI input to the OR output of an empty FIFO or the
time required to increment the read pointer and propagate a signal
from the SO input to the IR output of a full FIFO.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset (MR)
signal. This causes the device to enter the empty conditi()n, which
is signified by the OR signal being LOW at the same time that the
IR signal is HIGH. In this condition, the data outputs (DOa DOg) will be LOW. The AFE flag will be HIGH and the HF flag
wiIlbeLOW.
EMPTY
128
SHIFT IN
SLSl...•..
9
10
The IR output will then go LOW, indicating that the data has been
sampled. The HIGH-to-LOW transition ofthe SI signal initiates
the LOW-to-HIGH transition ofthe IR signal ifthe FIFO is not
full. If the FIFO is full, IR will remain LOW.
Shifting Data Out of the FIFO
The availability of data at the outputs of the FIFO is indicated by
the HIGH state of the output ready (OR) signal. After the FIFO is
reset all data outputs (DOa - DOg) will be in the LOW state. As
long as the FIFO remains empty, the OR signal will be LOW and
all SO pulses applied to it will be ignored. After data is shifted into 5
the FIFO, the OR signal will go HIGH. The external control logic
(designed by the user) should use the HIGH state ofthe OR signal
to generate a SO pulse. The data outputs of the FIFO should be en
sampled with edge-sensitive type D flip-flops (or equivalent), using 0
the SO signal as the clock input to the flip-flop.
U.
Ii:
AFE and HF Flags
Tho flags, almost full/almost empty (AFE) and half full (HF), describe how many words are stored in the FIFO. AFE is HIGH
when there are 8 or fewer or 56 or more words stored in the FIFO.
Otherwise the AFE flag is LOW. HF is HIGH when there are 32 or
more words stored in the FIFO, otherwise the HF flag is LOW.
Flag transitions occur relative to the falling edges of SI and SO
(Figures 1 and 2).
Due to the asynchronous nature of the SI and SO signals, it is possible to encounter specific timing relationships which may cause
short pulses on the AFE and HF flags. These pulses are entirely
due to the dynamic relationship of the SI and SO signals. The flags,
however, will always settle to their correct state after the appropriate delay (tOHAFE, tOLAFE, tOHHR or tOLHF). Therefore, use of
level-sensitive rather than edge-sensitive flag detection devices is
recommended to avoid false flag encoding.
Possible Minimum Pulse Width Violation at the Boundary
Conditions
If the handshaking signals IR and 0 R are not properly used to generate the SI and SO signals, it is possible to violate the minimum
(effective) SI and SO positive pulse widths at the full and empty
boundaries.
31
32
33
55
56
57
FULL
64
...~_..._~o::o..-._..Sl..._
HF
AFE
C408A·17
Figure 1. Shifting Words In
5-19
=~PRESS
CY7C408A
CY7C409A
~
_
~
SEMICONDUCTOR
fore, the first device has its data shifted in faster than it is shifted
out, and eventually this device becomes momentarily full. When
this occurs, the maximum sustainable external clock frequency
changes from 35 MHz to the cascade interface frequencyJ28j
Cascading the 7C408/9A-35 Above 25 MHz
First, the capacity ofN cascaded FIFOs is decreased from N X 64
to (N X 63) + l.
If cascaded FIFOs are to be operated with an external clock rate
greater than 25 MHz, the interface IR signal must be inverted before being fed back to the interface SO pin (Figure 3 ). Two things
should be noted when this configuration is implemented.
When data packets[29] are transmitted, this phenomenon does not
occur unless more than three FIFOs are depth cascaded. For example, if two FIFOs are cascaded, a packet of 127 (= 2 X 63 + 1)
words may be shifted in at up to 35 MHz and then the entire packet
may be shifted out at up to 35 MHz.
Secondly, the frequency at the cascade interface is less than the
35 MHz rate at which the external clocks may operate. ThereFULL
64
SHIFT OUT
EMPTY
63
55
56
54
32
nIL ...
31
9
30
8
1
7
... JL
• ••
HF
AFE
C408A-18
Figure 2. Shifting Words Out
A
IR
IRx
SI
SiX
c
B
IR
SO
SI
OR
r--
C420·2
08
03
O2
01
00
Xl
FF
00
01
02
03
08
GNO
Vee
04
05
06
07
FLJRT
MR
EF
XO/RF
07
06
05
04
R
C42o-3
I---I--__ a:
L _ _J--t---~
I~
L==-j---... XO"~
C420·1
5-26
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
1.Vl~
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum ~erating
Current(mA
20
I Commercial
I
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
25
30
125
140
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
28.5
25
132
147
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
33.3
142
Military/Industrial
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
20
40
115
130
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
12.5
65
100
115
Maximum Rating
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ...................... - 55°Cto +125°C
Supply Voltage to Ground Potential. . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
inHighZState ........................ - O.5Vto +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.OW
Output Current, into Outputs (LOW) . . . . . . . . . . . . .. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-S'ID-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Temperature[l]
Range
Commercial
O°Cto + 70°C
Vee
5V± 10%
Industrial
- 40°C to +85°C
5V± 10%
Military
- 55°C to +125°C
5V± 10%
Electrical Characteristics Over the Operating Range!2]
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
Parameter
Description
VOH
Output mGH Voltage
VOL
VIH
Output LOW Voltage
Test Conditions
Min.
= Min., IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
Com'l
Input mGH Voltage
2..4
0.4
2.0
Input LOW Voltage
Input Leakage Current
loz
Output Leakage Current
lee
Operating Current
ISBI
Standby Current
All Inputs = VIH Min.
ISB2
Power-Down Current
MillInd
AIlInputs~ Vee - 0.2V Com'l
Mil/Ind
los
Output Short
Circuit Current£5]
Vee = Max., VOUT
GND.s. VI.s. Vee
R~ VIH,GND.s. Vo.s. Vee
Com'I[3]
Vee = Max.,
lOUT = ornA
MiI/Ind[4]
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Icc (commercial) = 100 mA + [(f - 12.5) • 2 mA/MHz]
for 1~ 12.5 MHz
where 1 = the larger of the write or read operating frequency.
2.4
0.4
Unit
V
0.4
V
V
Vee
2.0
Vee
2.0
Vee
-3.0
0.8
2.2
-3.0
Vee
0.8
Vee
0.8
V
-10
+10
+10
142
-10
-10
+10
+10
2.2
-3.0
-10
-10
+10
!AA
+10
125
rnA
-10
Com'l
=GND
Notes:
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
Max. Min. Max. Min. Max.
2.4
MillInd
VIL
IIX
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
132
147
!LA
140
30
25
30
25
30
rnA
25
20
25
20
25
rnA
-90
-90
- 90
rnA
= 115_mA + [(f - 12.5) * 2 mA/MHz]
for f ~ 12.5 MHz
where f = the larger of the write or read operating frequency.
5. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. Icc (military)
5-27
•
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
13~~~
Electrical Characteristics Over the Operating Range£2J (continued)
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
Parameter
Test Conditions
Description
Min.
VOH
Output mGH Voltage
Vee = Min.,IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee
VIH
Input mGH Voltage
=Min., IOL = 8.0 rnA
2.0
Vee
Vee
Vee
-3.0
0.8
- 3.0
0.8
V
-10
+10
-10
+10
-10
+10
- 10
Output Leakage Current
R~ VIH,GND.s. Vo.s. Vee
lec
Operating Current
Vee =Max.,
lOUT ='omt\
+10
f.I.A
f.I.A
Com'I[3]
115
100
rnA
Mil!Ind[4]
130
115
Com'l
25
25
Mil
30
30
20
20
25
25
- 90
-90
0.2V Com'l
Mil
Vee = Max., VOUT
Output Short
Circuit Currend5]
los
V
V
2.2
loz
AlIInputs~ Vee-
V
Vee
GND.s. VI.s. Vee
Power-Down Current
0.4
0.4
2.0
Input Leakage Current
ISB2
Unit
2.2
IIX
All Inputs = VIH Min.
Max.
2.4
Com'l
Input LOW Voltage
Standby Current
Min.
MillInd
VIL
ISBl
Max.
2..4
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
=GND
rnA
mA
rnA
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
=
=
TA 25°C, f
Vee 4.5V
= 1 MHz,
Max.
8
10
Unit
pF
pF
Note:
6. Thsted initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
R1500Q
R1500Q
5Vo----JV\I\o--,
5Vo---~"","",
OUTPUTo--~~-"
FI
R2
3330
30 P
INCLUDING
JIGAND _
-=
SCOPE -
5pFI
R2
3330
INCLUDING
JIGAND _
C420-4
(a)
Equivalent to:
ALL INPUT PULSES
OUTPUTo---+---1
SCOPE -
C42~
(b)
THEvENIN EQUIVALENT
2000
OUTPUT OoD--..JWIo-----oO 2V
5-28
C420-6
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
...::::::==t...
---=v
;;~PRFSS
-===r"
SEMICONDUCTOR
Switching Characteristics Over the Operating Range[7, 8]
7C420-20
7C421-20
7C424-20
7C425-20
7C428-20
7C429-20
Min.
Min.
Max.
7C420-30
7C421-30
7C424-30
7C425-30
7C428-30
7C429-30
Min.
Max.
7C420-40
7C421-40
7C424-40
7C425-40
7C428-40
7C429-40
Min.
tRe
Description
Read Cycle TIme
tA
Access Time
tRR
tpR
Read Recovery Time
10
10
10
10
Read Pulse Width
20
3
3
25
3
3
30
3
3
40
3
3
Parameter
tLZRL9 ]
tDVR l9 ,lOj
Read LOW to Low Z
Data Valid Mer Read mOH
tHZRl'J,lUj
Read mOH to High Z
twc
tpw
tHWZL'Jj
Write Cycle Time
Max.
7C420-25
7C421-25
7C424-25
7C425-25
7C428-25
7C429-25
30
25
20
35
Write Pulse Width
25
40
30
Write mOH to Low Z
10
10
10
10
18
0
25
10
30
10
10
25
30
30
40
40
40
50
25
30
40
10
10
10
Write Recovery Time
10
10
Data Set-Up Time
tHD
Data Hold Time
tMRSC
tpMR
MR Cycle Time
MR Pulse Width
MR Recovery Time
12
0
30
20
15
0
35
10
tRTC
tpRT
Retransmit Pulse Width
20
20
30
20
tRTR
Retransmit Recovery Time
10
tEFL
MRtoEFLOW
tHFH
MRtoHFmOH
tFFH
MRtoFFmOH
tREF
Read LOW to EF LOW
tRFF
Read mOH to FF mOH
tWEF
tWFF
Write mOH to EF mOH
tRPW
twpw
Read mOH to MR mOH
Write mOH to MR:mOH
Retransmit Cycle Tune
40
25
35
ns
ns
ns
ns
ns
30
ns
80
65
ns
10
ns
15
30
ns
10
ns
80
65
15
65
65
80
65
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWHF
Write LOW to HF LOW
tRHF
Read mOH to HF mOH
tRAE
Effective Read from
WritemOH
20
tRPE
Effective Read Pulse Width
MerEFmOH
tWAF
Effective Write from
ReadmOH
tWPF
Effective Write Pulse Width
MerFFmOH
tXOL
Expansion Out LOW
Delay from Clock
20
25
30
40
65
ns
tXOH
Expansion Out mOH
Delay from Clock
20
25
30
40
65
ns
20
25
65
15
65
3
3
Unit
ns
30
30
30
25
25
25
25
30
30
Write LOW to FF LOW
35
35
35
25
25
25
25
35
35
Max.
80
25
50
40
10
10
20
0
50
40
tSD
Min.
40
20
18
15
Max.
50
30
30
20
tWR
tRMR
40
35
7C420-65
7C421-65
7C424-65
7C425-65
7C428-65
7C429-65
20
30
35
60
40
30
30
30
30
40
25
25
5-29
80
80
80
60
60
60
60
80
80
30
25
20
40
50
50
50
35
35
35
35
50
50
40
40
40
30
30
65
35
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
65
ns
ns
II
(I)
oLL.
u:::
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~
tufir~
Switching Waveforms
Asynchronous Read and Write
I
r::
QO-Qo------------~·~~I~___________J·~~NI'~___________'
W
Do-Do
-{14-_-_
~R ~""'---
-_tPW
__
-------------te:K-
tso
_ _- ' / - - - - -
ttio ~
DATA VALID
~Jo------------o«,,---D-AT.-A--V.-A-Ll-D--J>)o----
C420·7
Master Reset
....- - - - tMRSC(12) ---------~
__________
~~-------
tpMR
----------~~----~------------------
'R, W(11)
C420-B
Half·Full Flag
HALF FULL
W
HALF FULL
HALF FULL +1
.
-
tRHF
~
IC
... tWHF ..
~
"'r
C420-9
Notes:
7. lest conditions assume signal transition time of5 ns or less, timing reference levels of 1.5V and output loading of the specified IorJIoH and
30 pFload capacitance, as in part (a) ofAC lest Load and Waveforms,
unless otherwise specified.
8. See the last page of this specification for Group A subgroup testinginformation.
9.
tHZR transitionismeasured at +500mVfrom VOLand -500mVfrom
VOH· tDVR transition is measured at the 1.5V level tHWZ and tLZR
transition is measured at± 100 mV from the steady state.
10. tHZR and tDVR use capacitance loading as in part (b) ofAC lest Load
and Waveforms.
11. Wand I{,~ VIH around the rising edge ofKm:.
12.
5-30
[MRSC
= [PMR + [RMR·
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~
""'='·~PRFSS
.,
g
SEMICONDUCTOR
Switching Waveforms (continued)
Last Write to First Read Full Flag
LAST WRITE
R ---P--------------~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
C420-10
Last Read to First Write Empty Flag
•
U)
LAST READ
W
---P--------------+_
'EF
---+--+-,1
ADDITIONAL
WRITES
FIRST WRITE
oLL.
FIRST READ
u:::
DATA OUT --1---..(
C420-11
Retransmid 13 ]
tRTC[14]
I+--
tpRT
'R',W
"[
j4- tRTRC420-12
Notes:
13. EF,BFandFFmaychangestateduringretransmitasaresultoftheoffset of the read and write pointers, but flags will be valid at tRTC'
14. tlITC
5-31
= tPlIT + tRfR.
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
$A
~:
~
CYPRESS
SEMlCONDUCI'OR
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
DATAIN
W
--~~--------------------------~------------------------------11-----
~--~------------~--~
DATAO~ --~~--------------~
C420-13
FuU Flag and Write Data Flow-Through Mode
w
FF---+--------J.--/I
DATAIN---;------------------------~
DATA O~
t~~
----~~,....-D-AT-A-V.-A-U-D-)@-------------------------------C420-14
5-32
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
" '):crPRfSS
~
SEMIcamucrOR
Switching Waveforms (continued)
Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
w---__,.
tSD
_N-t..:.::HD~
C42(H5
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
iHZR
00- 0 8
---+-----1
C420-16
Note:
15. Expansion Out of device 1 (XOl) is connected to Expansion In of device 2 (XI2).
5-33
•
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
$2 :;~PRESS
--=-,
SEMICONDUCTOR
Architecture
The CY7C420/421/424/425/428/429 FIFOs consist of an array of
512/1024/2048 words of 9 bits each (implemented by an array of
dual-22rt RAM cells). a read....J?2!nter. a write pointer. control signals (w, R. Xi. XD. PL. lIT, MR). and Full, Half Full. and Empty
flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operationsto be independent ofeach other. whichisnecessarytoachieve
truly asynchronous operation of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
propagation through the memory. which would be the case if the
memory were implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power-up. the FIFO must be reset with a Master Reset (MR)
cycle. This causes the FIFO to enter the empty condition signifi.ed
by the Empty ~ (EF) being LOW. and both the Half Full (HF)
and Full flags (FF) being HIGH Read (R) and write (W) must be
HIGH tRPw/tWPW before and tRMR after the rising edge of MR
for a valid reset cycle. If reading from the FIFO after a reset cycle
is attempted. the outputs will all be in the high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FE The falling edge ofWinitiates a write cycle. Data appearing!!.the inputs (Do - Ds) tSD before and tHD after the rising
edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-lflGHtransition ofWfor an empty FIFO. HF goes LOW
tWHF after the falling ed~fW following the FIFO actually being
HalfFull. Therefore. the HFis active once the FIFO is filled to half
its capacity plus one word. HFwillremainLOWwhile less than one
half of total memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the ri~ edge of R when the
FIFO goes from half full + 1 to half full. HF is available in standalone and width expansion modes. FF goes LOW tWFF after the
falling edge of'w, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO.
Writes to a full FIFO are ignored and the write pointer is not incremented. FP goes HIGH tREF after a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (00 -Os) are in a high-impedance condition between
read operations (R HIGH) when the FIFO is empty. or when the
FIFO is not the active device in the depth expansion mode.
When one word is in the FIFO. the falling edge of R initiates a
lflGH-to-LOW transition of BE When the FIFO is empty. the
outputs are in a high-impedance state. Reads to an empty FIFO are
ignored and do not increment the read pointer. From the empty
condition, the FIFO can be read tWEF after a valid write.
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary.
The Retransmit (lU) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a
number of writes equal to or less than the depth of the FIFO have
occurred since the last MR cycle. A LOW pulse on RT resets the
inteI.!!...al read pointer to the first physical location of the FIFO. R
and W must both be HIGH while and tRTR after retransmit is
LOW. With every read cycle after retransmit. previously accessed
data is read and the read pointer is incremented until it is equal to
the write pointer. Full, Half Full, and Empty flags are governed by
the relative locations of the read and write pointers and are updated d~ retransmit cycle. Data written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly transmitted.
StandalonelWidth Expansion Modes
Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (PI:) to Vee. FIFOs can be
expanded in width to provide word widths greater than nine in increments ofnine. Duringwidth expansion mode. all control line inputs are common to all devices, and flag outputs from any device
can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansionmodeisenteredwhen, dUringaMRCYcle~an
sion Out (XO) of one device is connected to Expansion In
of
the next device. with XO of the last device connected to
of the
first device. In the depth expansion mode the First Load (PI:) input. when grounded. indicates thatthis part is the first to be loaded.
All other devices must have this pin HIGH To enable the correct
FIFO. XO is pulsed LOW when the last physical location of the
previous FIFO is written to and pulsed LOW again when the last
physical location is read. Only one FIFO is enabled for read and
one for write at any given time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently. any depth or width FIFO can be created of word
widths in increments of 9. When e!.Q...anding in depth, a composite
FF must be created by ORing the FFs together. Likewise. a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode.
5-34
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
,.~~
~,
SEMICONDUCTOR
1m
w
~
9~
D
9~-""
,/
7v:
~
R
EF
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
T
T
9~
,/
!=[
~
Vee
XI
....
FOIT
m
~
9,,,,,
/ "7,/
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
EF
""""
!=[
.... -
EF
-
mF'TY
U)
ou.
u::
XI
m
- -
*
~
9~1\.
7"
ml
'v
CY7C420
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
XI
n
• RRST DEVICE
C42D-17
Figure 1. Depth Expansion
5-35
II
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~
-=
ii~PRF.SS
~" ~lwCONDUClOR
1)rpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
SUPPLY VOLTAGE
VB.
VII.
1.2
1.4
~ 1.0
~ 1.2
o
0
~ 0.81----+-7f'1----+-----I
::J 1.0
w
~
o
w
N
u
25
NORMALIZED tA CHANGE
OUTPUT LOADING
1.5
V
)
~
1.2
1.0
o
./
40
l'l
7
20
o 1/
0.0
1.1
/
0
w 0.9
N
::J
0.0
VB.
50
~ 30
Vee = 5.5V
VIN = 5.0V
f=20MHz
Z 0.8
0.4 1.-_-'-_ _"--_--'-_---1
6.0
4.0
4.5
5.0
5.5
!zw
U
-
~
~
Z 0.6 .........
60
II:
II:
II:
OUTPUT SOURCE CURRENT
OUTPUT VOLTAGE
VII.
.s«
40
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
;~PRESS
==
-===:::::::::,
SEMICONDUCTOR
Ordering Information
Speed
(ns)
20
25
30
40
65
Ordering Code
Package
'JYpe
Package 'JYpe
Operating
Range
CY7C420-20DC
DI6
28-Lead (600-Mil) CerDIP
CY7C420-20PC
PI5
28-Lead (600-Mil) Molded DIP
Commercial
CY7C420-25DC
DI6
28-Lead (600-Mil) CerDIP
CY7C420-25PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C420-25PI
PI5
28-Lead (600-Mil) Molded DIP
Industrial
CY7C420-25DMB
DI6
28-Lead (600-Mil) CerDIP
Military
CY7C420-30DC
DI6
28-Lead (600-Mil) CerDIP
Commercial
CY7C420-30PC
PI5
28-Lead (600-Mil) Molded DIP
Commercial
CY7C420-30PI
PI5
28-Lead (600-Mil) Molded DIP
Industrial
CY7C420-30DMB
DI6
28-Lead (600-Mil) CerDIP
Military
CY7C420-40DC
DI6
28-Lead (600-Mil) CerDIP
Commercial
CY7C420-40PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C420-40PI
PI5
28-Lead (600-Mil) Molded DIP
IndusUy
CY7C420-40DMB
CY7C420-65DC
CY7C420-65PC
DI6
D16
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) CerDIP
Military
PI5
28-Lead (600-Mil) Molded DIP
CY7C420-65PI
PI5
28-Lead (600-Mil) Molded DIP
Industrial
CY7C420-65DMB
DI6
28-Lead (600-Mil) CerDIP
Military
5-37
•
en
Commercial
oLL.
u::
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
it1r~
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
CY7C421-20DC
CY7C421-2OJC
CY7C421-20PC
CY7C421-20VC
CY7C421-25DC
CY7C421-25JC
CY7C421-25PC
CY7C421-25VC
CY7C421- 25JI
CY7C421-25PI
CY7C421- 25DMB
CY7C421-25KMB
CY7C421-25LMB
CY7C421-30DC
CY7C421-30JC
CY7C421-30PC
CY7C421-30VC
CY7C421-30JI
CY7C421-30PI
CY7C421-30DMB
CY7C421-30KMB
CY7C421-30LMB
CY7C421-40DC
CY7C421-4OJC
CY7C421-40PC
CY7C421-40VC
CY7C421-4OJI
CY7C421-40PI
CY7C421-40DMB
CY7C421-40KMB
CY7C421-40LMB
CY7C421-65DC
CY7C421-65JC
CY7C421-65PC
CY7C421-65VC
CY7C421-65JI
CY7C421-65PI
CY7C421-65DMB
CY7C421-65KMB
CY7C421-65LMB
Package
1)pe
D22
J65
P21
V21
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
Package 1YPe
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
5-38
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
== -~riPRESS
==,
SEMICONDUCIDR
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
Package
'J.Ype
Package Iype
Operating
Range
Commercial
CY7C424-20DC
DI6
28-Lead (600-Mil) CerDIP
CY7C424-20PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C424-25DC
DI6
28-Lead (600-Mil) CerDIP
CY7C424- 25PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C424-25PI
PI5
28-Lead (600-Mil) Molded DIP
Industrial
CY7C424- 25DMB
DI6
28-Lead (600-Mil) CerDIP
Military
CY7C424-30DC
DI6
28-Lead (600-Mil) CerDIP
Commercial
CY7C424-30PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C424-30PI
PIS
28-Lead (600-Mil) Molded DIP
CY7C424-30DMB
DI6
28-Lead (600-Mil) CerDIP
Military
CY7C424-40DC
DI6
28-Lead (600-Mil) CerDIP
Commercial
CY7C424-40PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C424-40PI
PI5
28-Lead (600-~il) Molded DIP
Industrial
CY7C424-40DMB
CY7C424-65DC
DI6
D16
28-Lead (600-Mil) CerDIP
28-Lead (600-Mil) CerDIP
Military
Commercial
Commercial
Industrial
fI)
CY7C424-65PC
PI5
28-Lead (600-Mil) Molded DIP
CY7C424-65PI
PI5
28-Lead (600-Mil) Molded DIP
Industrial
CY7C424-65DMB
DI6
28-Lead (600-Mil) CerDIP
Military
5-39
•
ou..
LL:
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
Ordering Information (continued)
Ordering Code
Package
'JYpe
Package 'JYpe
Operating
Rallge
CY7C425-20DC
CY7C425-2OJC
CY7C425 - 20PC
CY7C425 - 20VC
CY7C425 - 25DC
CY7C425-25JC
CY7C425-25PC
CY7C425 - 25VC
CY7C425 - 25JI
CY7C425 - 25PI
CY7C425-25DMB
CY7C425 - 25KMB
CY7C425 - 25LMB
CY7C425 -30DC
CY7C425-3OJC
CY7C425 -30PC
CY7C425-30VC
CY7C425-3OJI
CY7C425-30PI
CY7C425-30DMB
CY7C425-30KMB
CY7C425-30LMB
CY7C425 -40DC
CY7C425-4OJC
CY7C425 -40PC
CY7C425-40VC
CY7C425 -4OJI
CY7C425 -40PI
CY7C425 -40DMB
CY7C425 -40KMB
CY7C425-40LMB
CY7C425-65DC
CY7C425-65JC
CY7C425-65PC
CY7C425 -65VC
CY7C425 -65JI
CY7C425-65PI
CY7C425 -65DMB
CY7C425-65KMB
CY7C425 -65LMB
D22
J65
P21
V21
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
Commercial
Speed
(ns)
20
25
30
40
65
5-40
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C420, CY7C421, CY7C424
CY7C42S, CY7C428, CY7C429
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
CY7C428-20DC
Package
lYPe
D16
CY7C428-20PC
PIS
CY7C428-2SDC
D16
28-Lead (600-Mil) CerDIP
CY7C428-25PC
PIS
28-Lead (600-Mil) Molded DIP
Ordering Code
Package 'JYpe
28-Lead (600-Mil) CerDIP
Operating
Range
Commercial
28-Lead (600-Mil) Molded DIP
Commercial
CY7C428-25PI
PIS
28-Lead (600-Mil) Molded DIP
CY7C428-2SDMB
D16
28-Lead (600-Mil) CerDIP
Industrial
Military
CY7C428-30DC
D16
28-Lead (600-Mil) CerDIP
Commercial
28-Lead (600-Mil) Molded DIP
CY7C428-30PC
PIS
CY7C428-30PI
PIS
28-Lead (600-Mil) Molded DIP
CY7C428-30DMB
D16
28-Lead (600-Mil) CerDIP
Military
CY7C428-40DC
D16
28-Lead (600-Mil) CerDIP
Commercial
Industrial
CY7C428-40PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C428-40PI
PIS
28-Lead (600-Mil) Molded DIP
Industrial
CY7C428-40DMB
D16
28-Lead (600-Mil) CerDIP
Military
CY7C428-6SDC
D16
28-Lead (600-Mil) CerDIP
Commercial
CY7C428-65PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C428-65PI
PIS
28-Lead (600-Mil) Molded DIP
Industrial
CY7C428-6SDMB
D16
28-Lead (600-Mil) CerDIP
Military
5-41
•
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~
9~PRF.SS
g
~, SEMICONDUCIOR
Ordering Information (continued)
Speed
(ns)
20
25
30
40
65
Ordering Code
Package
'JYpe
Package 'JYpe
Operating
Range
CY7C429-20DC
CY7C429-20JC
CY7C429-20PC
CY7C429-20VC
CY7C429-25DC
CY7C429-25JC
CY7C429-25PC
CY7C429-25VC
CY7C429 - 25JI
CY7C429-25PI
CY7C429-25DMB
CY7C429-25KMB
CY7C429-25LMB
CY7C429-30DC
CY7C429-30JC
CY7C429-30PC
CY7C429-30VC
CY7C429-3OJI
CY7C429-30PI
CY7C429-30DMB
CY7C429-30KMB
CY7C429-30LMB
CY7C429-40DC
CY7C429-40JC
CY7C429-40PC
CY7C429-40VC
CY7C429-40JI
CY7C429-40PI
CY7C429 -40DMB
CY7C429-40KMB
CY7C429-40LMB
CY7C429-65DC
CY7C429-65JC
CY7C429-65PC
CY7C429-65VC
CY7C429-65JI
CY7C429-65PI
CY7C429-65DMB
CY7C429-65KMB
CY7C429-65LMB
D22
J65
P21
V21
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
D22
J65
P21
V21
J65
P21
D22
K74
L55
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) Molded SOJ
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead (300-Mil) CerDIP
28-Lead Rectangular Cerpack
32-Pin Rectangular Leadless Chip Carrier
Commercial
5-42
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C420, CY7C421, CY7C424
CY7C425, CY7C428, CY7C429
~~
~,.
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VOL
VIH
VILMax.
IIX
Icc
ISBI
ISB2
los
Switching Characteristics
Parameters
Subgroups
9,10,11
tRC
9,10,11
tA
9,10,11
tRR
9,10,11
tpR
9,10,11
tLZR
9,10,11
tDVR
9,10,11
tHZR
9,10,11
twc
9,10,11
tpw
9,10,11
tHWZ
9,10,11
tWR
9,10,11
tSD
9,10,11
tHO
9,10,11
tMRsc
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPW
9,10,11
twpw
9,10,11
tRTC
9,10,11
tpRT
9,10,11
tRTR
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRi-IF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document#: 38-00079-1
5-43
•
en
oLL.
u::
CY7C421A
CY7C425A
PRELIMINARY
High-Speed Cascad~ble
512x9 FIFO
lKx9 FIFO
Features
• 512 x 9 and 1K x 9 FIFO buffer
memory
• Dual-port RAM cell
Functional Description
• Asynchronous read/write
• IDgb-speed 66.(i-MHz read/write
independent of deptblwidth
The CY7C421A and CY7C425A are firstin first-out (FIFO) memories. Theyare,respectively, 512 and 1,024 words by 9-bits
wide. Each FIFO memory is organized
such that the data is read in the same sequential order that it was written. Full and
Empty flags are provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one device to another in
parallel, thus eliminating the serial addition of propagation delays, so that
throughput is not reduced. Data is steered
in a similar manner.
• 10-ns access time
• Half Full flag in standalone
Empty and Full flags
Retransmit in standalone mode
Expandable in width and depth
Parallel cascade minimizes
bubble-through
•
•
•
•
The read and write operatipns may be
asynchronous; each can occur at a rate of
66.6 MHz. The write operation occurs
when the write (VI) signal is LOW. Read
occurs whenread(R) goes LOW. The nine
data outputs go to the high-impedance
state when R is mGR
• TTL compatible
• Three-state outputs
• Pin compatible and functional
equivalent to IDT7201 and IDT7202
• SV ± 10% supply
• 300-mll 28-pin DIP and 32-pin PLCC
packaging
Logic Block Diagram
A Half Full (HF) output flag is provided
that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides
the expansion out (XO)information that is
used to tell the next FIFO that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable
(W) must both be mGH during retransmit, and then R is used to access the data.
Pin Configurations
DATA INPUTS
PLCC
(Do-Del
DIP
Top View
d"
W
oeDl:!:
Top View
~ )l o 2001 V
(per MIL-SID-883, Method 3015)
Latch-Up Current ........................... >200 mA
Operating Range
- O.SY to + 7.0V
- O.SY to +7.0V
Ambient
Temperature[l]
Range
Commercial
Vee
5V± 10%
O°Cto + 70°C
Electrical Characteristics Over the Operating Range[2]
Description
Parameter
Test Conditions
= Min., IOH = - 20mA
Vee = Min.,IOL = 8.0 mA
VOH
Output IDGH Voltage
VOL
Output LOW Voltage
VIH
Input IDGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND .s. VI .s. Vee, Vee = Max.
loz
Output Leakage Current
R~ VIH, GND.s. Vo.s. Vee, Vee =
lee
Operating Current
Vee = Max.,
loUT = OmA
7C421A-IO
7C425A-IO
7C421A-15
7C425A-15
Min.
Min.
2.0
-0.5
= VIH Min.
Standby Current
All Inputs
IsB2
Power-Down Current
All Inputs ~ Vee - 0.2V
los
Output Short
Qrcuit Currentl3]
Vee = Max., VOUT = GND
Max.
Max.
Unit
0.4
V
Vee
0.8
V
2..4
0.4
Com'l
ISBI
Max.
24
Vee
Vee
0.8
2.0
-0.5
V
V
-1
+1
- 1
+1
-10
+10
-10
+10
JAA
JAA
mA
Com'l
180
120
Com'l
15
15
mA
Com'l
5
5
mA
-90
- 90
mA
Capacitance[4]
Parameter
CIN
CoUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA
= 25°C,f = 1 MHz
Max.
5
Unit
pF
7
pF
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for GroupA subgroup testing information.
3.
4.
5-45
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Thsted initially and after any design or process changes that may affect
these parameters.
•
m;
:i~PRFSS
-===r'
CY7C421A
CY7C425A
PRELIMINARY
SEMICONDUCTOR
AC Test Loads and Waveforms
R1470Q
ALL INPUT PULSES
5Vo----"IMI...,
~
OUTPUTo------t--...
30 P
FI
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
10%
R2
3000
-=
THEvENIN EQUIVALENT
1830
OUTPUT OCl--...JII.IIII
.. ----oCi 2V
.s.3ns
421A-5
421A-4
Switching Characteristics Over the Operating Range[5,6)
Description
Parameter
tRC
tA
tRR
tpR
tDVR l7 ]
tHZR l7 ]
twc
tpw
tWR
tSD
tHO
tMRSC
tpMR
tRMR
tRTC
tpRT
tRTR
tEFL
tHFH
tFFH
tREF
tRFF
tWEF
tWFF
tWHF
tRHF
tXOL
txoH
tLZR
tHWZ
tRPW
twpw
7C421A-IO
7C425A-IO
Min.
Max.
15
Read Cycle Time
10
Access Time
Read Recovery Time
Read Pulse Width
Data Valid After Read IDGH
Read IDGH to High Z
Write Cycle Time
Write Pulse Width
5
10
5
Write Recovery Time
Data Set-Up Time
Data Hold Time
MR Cycle Time
MR Pulse Width
MR Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EFLOW
15
5
15
15
10
25
15
5
8
0
15
10
10
0
25
15
10
25
15
10
10
5
15
10
5
10
Read LOW to EF LOW
Read IDGH to FF IDGH
10
10
Write IDGH to EF IDGH
Write WW to FF LOW
Write WW to lIP LOW
Read IDGH to HF IDGH
Expansion Out LOW Delay from Oock
Expansion Out IDGH Delay from Oock
Read WW to Low Z
Write IDGH to Low Z
10
10
15
15
15
15
15
15
15
10
10
12
12
1
tWPF
Effective Read Pulse Width After FF IDGH
5-46
15
1
5
10
5
15
15
10
10
10
15
15
15
10
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns .
ns
ns
ns
ns
ns
ns
15
15
15
10
10
MRtoHFIDGH
MRtoFFIDGH
tWAF
tRAE
15
10
15
Read IDGH to MR IDGH
Write IDGH to MR IDGH
Effective Read from Write IDGH
Effective Read Pulse Width After FF IDGH
Effective Write from Read HIGH
tRPE
7C421A-15
7C425A-15
Min.
Max.
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
·7l~
CY7C421A
CY7C425A
PRELIMINARY
Switching Waveforms
Asynchronous Read and Write
---e- ~
QO-Q8--------------~~~rl'_____________'-~~WI'_ _ _ _ _ _ _ _ _ _ _ __
W
00-08
T ~R =1-------'1----
r; Iso :L ::1
--------ICI'-
,"0
DATA VALID
JI~--------«
>~---
DATA VALID
421A-6
•
U)
ou..
u::
Master Reset
......- - - - tMRse[9]
_ _ _ _ _- . l J . - - - - -
tpMR
--------~
------~v_----_+--------------
'R. W[8]
R'F'
FF
vzzzzzzvzzZl&zm
421A-7
Half·FuIl Flag
w
HALF FULL
HALFFULL +1
HALF FULL
- -
..1~
tRHF
C
I-
tWHF ..
.,~
~
421A-8
Notes:
5_ Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOrJIOH and
30 pF load capacitance, as in AC Test Load and Waveforms, unless
otherwise specified.
6. See the last page of this specification for GroupA subgroup testing information.
7.
tHZR transitionismeasuredat +500mVfrom VOLand -500mVfrom
VOH. tOVR transition is measured at the l.5V level- tHWZ and tLZR
transition is measured at ± 100 mV from the steady state.
s. W and lt~. VIH around the rising edge ofW.
9. tMRSC tpMR + tRMR·
5-47
=
Switching Waveforms (continued)
Last Write to First Read FoB nag
LAST WRITE
~ --~------------~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
421A-9
Last Read to First Write Empty nag
ADDITIONAL
WRITES
FIRST WRITE
LAST READ
FIRST READ
w --~-------------+-
DATA OUT
--+----<
421A-l0
Retransmit[lO]
tRTC[11]
10---k-
tpRT
~~
R",W
14-
iRTR
Notes:
10. EF,HFandFFmaychange state during retransmit as aresult ofthe offset of the read and write pointers, but flags will be valid at tRTC.
-
-
11. tRrC
5-48
421A-ll
=tPRr + tRTR.
t!,~CYPRESS
~
PRELIMINARY
CY7C421A
CY7C42SA
SEMICONDUC1'OR
Swiiching Waveforms (continued)
Empty nag and Empty Boundary Timing Diagram
DATA IN
W
--1---_
II
EF----+---------------4---J
DATA OUT
U)
oLL.
---.f----------I-It
421A-12
Full nag and Full Boundary Timing Diagram
w
~
___
~
________
~_J'
DATAIN----r------------------r
t~L
DATA OUT
------Q.M
.
3ATA VAUD
)@~----------------------421A-13
5-49
u:
.~~PRFSS
-==-r'
PRELIMINARY
CY7C421A
CY7C425A
SEMICONDUCI'OR
Switching Waveforms (continued)
Expansion Timing Diagrams
w---_
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
Do-Os ~~~~~~~~~~~~_ _ _ _~~~~~~~~__DA_I_A_V_A_U_D_~~_ _
421A-14
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
421A-15
Note:
12. Expansion Out of device 1 (XOl) is connected to Expansion In of device 2 (XI2).
5-50
~
~~
_
' -= CYPRESS
_ , SEMICONDUcrOR
CY7C421A
CY7C42SA
PRELIMINARY
Architecture
The CY7C421N425A FIFOs consist of an array of 512/1024
words of 9 bits each (implemented by an array of dual-I)(>rt RAM
cells), a read pointer, a write pointer, control signals (w, H, XI, m,
Fr, lIT, KlR:), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent of each other, which isnecessaryto achieve
truly asynchronous operation of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
propagation through the memory, which would be the case if the
memory were implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset (MR)
cycle. This causes the FIFO to enter the empty condition signified
by the Empty ~ (EF) being LOW, and both the Half Full (HF)
and Full flags (FF) being HIGH. Read (R) and write (W) must be
HIGH tRPw/tWPW before and tRMR after the rising edge of MR
for a valid reset cycle. If reading from the FIFO after a reset cycle
is attempted, the outputs will all be in the high-impedance state.
Writing Data to the FIFO
The availability of at least on~mpty location is indicated by a
HIGH FE The falling edge of W initiates a write cycle. Data appearing ~the inputs (Do - Ds) tSD before and tHD after the rising
edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGHtransitionof~foranemptyFIFO.HFgoesLOW
tWHF after the falling ed~fW following the FIFO actually being
Half Full. Therefore, the HFis active once the FIFO is filled to half
its capacity plus one word. HFwillremain LOWwhile less than one
half of total memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the ri~ edge of R when the
FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW tWFF after the
falling edge of\v, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO.
Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tREF after a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (00 - Os) are in a high-impedance condition between
read operations (R HIGH) when the FIFO is empty, or when the
FIFO is not the active device in the depth expansion mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty FIFO are
ignored and do not increment the read pointer. From the empty
condition, the FIFO can be read tWEF after a valid write.
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary.
The Retransmit (lIT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a
number of writes equal to or less than the depth of the FIFO have
occurred since the last MR cycle. A LOW pulse on RT resets the
inteI.!!...al read pointer to the first physical location of the FIFO. R
and W must both be HIGH while and tRTR after retransmit is
LOW. With every read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to
the write pointer. Full, Half Full, and Empty flags are governed by
the relative locations of the read and write pointers and are updated durin.,.&! retransmit cycle. Data written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly transmitted.
StandalonelWidth Expansion Modes
Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (F[) to Vee. FIFOs can be
expanded in width to provide word widths greater than nine in increments of nine. Duringwidth expansion mode, all control1ine inputs are common to all devices, and flag outputs from any device
can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, duringaMRcycle,~an
sion Out (XO) of one device is connected to Expansion I.!!jXI) of
the next device, with
of the last device connected to XI of the
first device. In the depth expansion mode the First Load (F[) input, when grounded, indicates that this part is the first to be loaded.
All other devices must have this pin HIGH To enable the correct
FIFO, XO is pulsed LOW when the last physical location of the
previous FIFO is written to and pulsed LOW again when the last
physical location is read. Only one FIFO is enabled for read and
one for write at any given time. All other devices are in standby.
m
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When e~anding in depth, a composite
FF must be created by ORing the FFs together. Ukewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode.
5-51
II
0
0~
u:::
CY7C421A
CY7C425A
PRELIMINARY
m
w
J:t
FF
9J
D
~
9JI\..
"-
/
,/
,V
I
CY7C421A
CY7C425A
9
,/
J:[
r----
~
Vee
XI
m
.....
J:lJ[[
~
FF
9""
/ ",V
EW'TV
~
CY7C421A
CY7C425A
J:[
1--
XI
m
*
---
~
FF
"---
/ "-
,V
~
~
9 , .....
CY7C421A
CY7C425A
J.m
XI
~
• FIRST DEVICE
421A-16
Figure 1. Depth Expansion
Ordering Information
Speed
(as)
10
15
Speed
(as)
10
15
Package
'JYpe
Operating
Range
CY7C42lA-lOJC
J65
Commercial
CY7C42lA -lOPC
P2l
Ordering Code
CY7C42IA-15JC
J65
CY7C42lA -15PC
P21
Ordering Code
CY7C425A -IOJC
CY7C425A-IOPC
CY7C425A-15JC
CY7C425A-15PC
Commercial
Package
lYPe
Operating
Range
J65
P21
J65
P21
Commercial
Commercial
Document #: 38-00248
5-52
4
,
=
CY7C429A
CY7C433A
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• 2,048 x 9 and 4,096 x 9 FIFO buffer
memory
• Dual-port RAM cell
High-Speed Cascadable
2Kx9 FIFO
4Kx9 FIFO
The read and write operations may be
asynchronous; each can occur at a rate of
66.6 MHz. The write operation occurs
when the write (Wl signal is LOW Read
occurs when read (R) goes LOW The nine
data outputs go to the high-impedance
state when R is HIGH.
• TTL compatible
• Three-state outputs
• Pin compatible and functional
equivalent to IDT7203 and IDT7204
Functional Description
• Asynchronous read/write
• High-speed 66.6-MHz read/write
independent of depth/width
• 10-ns access time
• Half Full flag in standalone
• Empty and Full flags
• Retransmit in standalone mode
• Expandable in width and depth
• Parallel cascade minimizes
bubble-through
• 5V ± 10% supply
• 300-mil 28-pin DIP and 32-pin PLCC
packaging
The CY7C429A and CY7C433A are firstin first-out (FIFO) memories. They are, respectively, 2,048 and 4,096 words by 9-bits
wide. Each FIFO memory is organized
such that the data is read in the same sequential order that it was written. Full and
Empty flags are provided to prevent overrun and underrun. Three additional pins
are also provided to facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one device to another in
parallel, thus eliminating the serial addition of propagation delays, so that
throughput is not reduced. Data is steered
in a similar manner.
Logic Block Diagram
A Half Full (HF) output flag is provided
that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides
the expansion out (XO) information that is
used to tell the next FIFO that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the FIFOs to retransmit
the data. Read enable (R) and write enable
(W) must both be HIGH during retransmit, and then R is used to access the data.
Pin Configurations
DATA INPUTS
(Do-Da)
PLCC
DIP
Top View
Top View
06
07
NC
FI:!Rf
MR
EF
DATA OUTPUTS
(Oo-Oa)
429A-2
W
Vee
Da
D3
D2
D4
Ds
D6
D7
D1
Do
Xi
FDRT
MR
ro/RF
FF
EF
Qo
)(O/RF
07
Q1
06
Q2
Q3
Qa
Q7
Q6
Qs
Q4
GND
R
429A-3
~-+----i~~
L _ _J--t--- FF
~-------~~::=-Jr-----roffiF
429A-l
5-53
5
en
0
LL.
u:::
- :~PRESS
===-.,
CY7C429A
CY7C433A
PRELIMINARY
.
SEMICONDUCTOR
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
I
7C429A-IO
7C433A-IO
66
10
7C429A-15
7C433A-15
40
15
180
120
Commercial
Maximum Rating
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. Ambient Temperature with
Power Applied ...................... Supply Voltage to Ground Potential. . . . . ..
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . ..
DC Input Voltage . . . . . . . . . . . . . . . . . . . . ..
65°C to +150°C
55 ° C to + 125 ° C
- O.5V to + 7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.OW
Output Current, into Outputs (LOW) . . . . . . . . . . . . .. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
- O.5V to + 7.0V
- O.5V to + 7.0V
Range
Commercial
Ambient
Temperature[l]
Vee
O°C to + 70°C
5V ± 10%
I
J
Electrical Characteristics Over the Operating Rangd 2]
7C429A-IO
7C433A-IO
Parameter
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
VIL
Input HIGH Voltage
IIX
Input Leakage Current
loz
Output Leakage Current
Icc
Operating Current
Vee = Max.,
lOUT = ornA
ISBI
Standby Current
All Inputs = VIH Min.
ISB2
Power-Down Current
All Inputs L Vee - 0.2V
los
Output Short
Circuit Currentl3]
Vee = Max., VOUT = GND
Max.
2.4
7C429A-15
7C433A-15
Min.
0.4
Com'l
2.0
Max.
2..4
2.0
V
0.4
V
V
JlA
-0.5
Vee
0.8
-0.5
Vee
0.8
GND S VIS Vee, Vee = Max.
-1
+1
-10
+10
RL VIH, GND S Vos Vee, Vee = Max.
Com'l
-10
+10
-10
Input LOW Voltage
Unit
V
+10
JlA
180
120
rnA
Com'l
15
15
rnA
Com'l
5
5
rnA
- 50
- 50
rnA
Capacitance[4]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = Ov, TA = 25°C, f = 1 MHz
VOUT= OV,TA =25°C,f= 1 MHz
Max.
5
7
Unit
pF
pF
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect
these parameters.
5-54
~
-.
;~
===== -=
CYPRESS
SEMICONDUCTOR
,
CY7C429A
CY7C433A
PRELIMINARY
AC Test Loads and Waveforms
R1470Q
5V
ALL INPUT PULSES
o------'''N¥-....,
3.0V -----.I.ot------~
90%
OUTPUTO---P---....
30
FI
R2
300Q
P
INCLUDING
JIGAND _
SCOPE -
-=
Equivalent to:
THEVENIN EQUIVALENT
183Q
GND
OUTPUT O().---JoJ
..II'I
.. _---QO 2V
429A-5
429A-4
Switching Characteristics Over the Operating Range[5,6]
Parameter
tRC
tA
tRR
tpR
tDVR[7j
tHZR l7j
Description
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width
Data Valid Mter Read HIGH
Read HIGH to High Z
twc
tpw
Write Cycle Time
Write Pulse Width
tWR
tSD
Write Recovery Time
Data Set-Up Time
tHD
Data Hold Time
tMRSC
tpMR
MR Cycle Time
MR Pulse Width
tRMR
tRTC
tpRT
MR Recovery Time
Retransmit Cycle Time
Retransmit Pulse Width
tHFH
Retransmit Recovery Time
MR to EFLOW
MR to HFHIGH
tFFH
MRtoFFHIGH
tREF
Read LOW to EF LOW
tRFF
tWEF
tWFF
Read HIGH to FF HIGH
Write HIGH to EF HIGH
Write LOW to FF LOW
tWHF
Write LOW to HF LOW
tRHF
Read HIGH to HF HIGH
tXOL
Expansion Out LOW Delay from Clock
tXOH
tLZR
tHWz
Expansion Out HIGH Delay from Clock
tRTR
tEFL
tRPW
twpw
Read LOW to Low Z
Write HIGH to Low Z
Read HIGH to MR HIGH
Write HIGH to MR HIGH
tRPE
Effective Read from Write HIGH
Effective Read Pulse Width Mter FF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Read Pulse Width Mter FF HIGH
tRAE
5-55
7C429A-IO
7C433A-IO
Min.
Max.
15
10
5
10
5
15
15
10
5
8
0
15
10
5
15
10
5
10
10
10
10
10
10
10
10
10
12
12
1
5
10
10
10
10
10
10
7C429A-15
7C433A-15
Min.
Max.
25
15
10
15
5
15
25
15
10
10
0
25
15
10
25
15
10
15
15
15
15
15
15
15
15
15
15
15
1
5
15
15
15
15
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
en
oLL.
u:
~CYPRF.SS
~iJ
~,
CY7C429A
CY7C433A
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms
Asynchronous Read and Write
______1
Do-Os
--------1( . ._____---' »-------«
DATA VALID
)>----
429A·6
Master Reset
1 + - - - - - tMRSC[9)
_ _ _ _ _ _~~-------tpMR
--------------~---+------------
R,W[S)
429A·7
Half-Full Flag
HALF FULL
W
HALF FULL +1
HALF FULL
-
03
tRHF
~
.,
... tWHF •
.
r429A·8
Notes:
5.
6.
Test condi~ions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOrJIOH and
30 pF load capacitance, as in AC Test Load and Waveforms, unless
otherwise specified.
See the last page of this specification for Group A subgroup testing information.
7., tHzRtransitionismeasuredat+500mVfromVOLand-500mVfrom
VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR
transition is measured at ± 100 m V from the steady state.
8. Wand R ~ VIR around the rising edge of MR.
9. tMRSC = tpMR + tRMR·
5-56
-~.irCYPRfSS
~
. .~
~ JF
CY7C429A
CY7C433A
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms (continued)
Last Write to First Read Full Flag
LAST WRITE
R ---+--------------~~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
w
429A-9
Last Read to First Write Empty Flag
I
U)
LAST READ
w ---+--------------~~
DATA OUT
ADDITIONAL
WRITES
FIRST WRITE
ou.
FIRST READ
i!
---+--(
429A-10
Retransmit[lO)
tRTC(11)
I+--
tpRT
r-
R,w
~
-tRTR429A-11
Notes:
10. EF, HFand FF may change state during retransmit as a result oft he offset of the read and write pointers, but flags will be valid at tRTCo
11. tRTC = tpRT
5-57
+ tRTR·
~
~~
======
= CYPRESS
~, SEMICONDUCTOR
PRELIMINARY
CY7C429A
CY7C433A
Switching Waveforms (continued)
Empty Flag and Empty Boundary Timing Diagram
DATA IN
\fii--+---""
EF--+----------+----J
DATA OUT ---+---------~
429A-12
Full Flag and Full Boundary Timing Diagram
FF _ _+-________-I-_--J'
DATA IN
--+---------------1:
t~J
DATAOUT--------~~D-A-TA--V-AL-ID--~~-----------------429A-13
5-58
.-
-
·~PRFSS
F
CY7C429A
CY7C433A
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms (continued)
Expansion Timing Diagrams
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
W -----'"\
DATA VALID
429A-14
I
en
oLL.
u:::
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
Note:
12 Expansi2!I Out of device 1 (XOI) is connected to Expansion In of device 2 (XI2)'
5-59
~~
~=CYPRESS
~, SEMICONDUCTOR
PRELIMINARY
Architecture
The CY7C429N433A FIFOs consist of an array of 1024/2048
words of 9 bits each (implemented by an array of dual-29rt RAM
cells~ read pointer, a write pointer, control signals (w, R, XI, XO,
FL, RT, MR), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve
truly asynchronous operation of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
propagation through the memory, which would be the case if the
memory were implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset (MR)
cycle. This causes the FIFO to enter the empty condition signified
by the Empty ~ (EF) being LOW, and both the Half Full (HF)
and Full flags (FF) being HIGH. Read (R) and write (W) must be
HIGH tRPW/tWpw before and tRMR after the rising edge of MR
for a valid reset cycle. If reading from the FIFO after a reset cycle
is attempted, the outputs will all be in the high-impedance state.
Writing Data to the FIFO
The availability of at least on~mpty location is indicated by a
HIGH FE The falling edge of W initiates a write cycle. Data appearing ~ the inputs (Do - Ds) tSD before and tHD after the rising
edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs tWEF after the first
LOW-to-HIGHtransitionof~foranemptyFIFO.HFgoesLOW
tWHF after the falling edge ofW following the FIFO actually being
Half Full. Therefore, the HF is active once the FIFO is filled to half
its capacity plus one word. HFwill remain LOW while less than one
half of total memory is available for writing. The LOW-to-HIGH
transition of HF occurs tRHF after the rising edge of R when the
FIFO goes from half full + 1 to half full. HF is available in standalone and widt.!!..expansion modes. FF goes LOW tWFF after the
falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO.
Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tREF after a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW
Data outputs (Qo :.9s) are in a high-impedance condition between
read operations (R HIGH) when the FIFO is empty, or when the
FIFO is not the active device in the depth expansion mode.
CY7C429A
CY7C433A
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EE When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty FIFO are
ignored and do not increment the read pointer. From the empty
condition, the FIFO can be read tWEF after a valid write.
'
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a
number of writes equal to or less than the depth of the FIFO have
occurred since the last MR cycle. A LOW pulse on RT resets the
inter~l read pointer to the first physical location of the FIFO. R
and W must both be HIGH while and tRTR after retransmit is
LOW. With every read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to
the write pointer. Full, Half Full, and Empty flags are governed by
the relative locations of the read and write pointers and are updated durin~ retransmit cycle. Data written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly transmitted.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to Vee. FIFOs can be
expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device
can be monitored.
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR cycle, E..!Eansion Out (XO) of one device is connected to Expansion I~XI) of
the next device, with XO of the last device connected to XI of the
first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded.
All other devices must have this pin HIGH. To enable the correct
FIFO, XO is pulsed LOW when the last physical location of the
previous FIFO is written to and pulsed LOW again when the last
physical location is read. Only one FIFO is enabled for read and
one for write at any given time. All other devices are in standby.
FIFOs can also be expanded simultaneously in depth and width.
Consequently, any depth or width FIFO can be created of word
widths in increments of 9. When e~nding in depth, a composite
FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode.
5-60
=;;-:~
~j,
~F
CY7C429A
CY7C433A
PRELIMINARY
CYPRESS
SEMICONDUCTOR
lID
FI
W
FI'
9,
9,1\.
/ "-
/
D
'V
-
EF
9,
CY7C429A
CY7C433A
,/
Fe
a
Vee
j([
lID
~
RJ[[
1--4
FI'
9J~
/V
EMJ5T'i'
"EF
I
CY7C429A
CY7C433A
FL
r-i-
j([
XO
-
*
"--
R'
EF
f0-
f---
9,~
/V
m
CY7C429A
CY7C433A
~
XI
• FIRST DEVICE
429A-16
Figure 1. Depth Expansion
Ordering Information
Speed
(ns)
10
15
Ordering Code
Package
Name
Package 1YPe
CY7C429A -lOJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C429A-I0PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433A -lOJC
CY7C433A -lOPC
CY7C429A-15JC
J65
P21
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
CY7C429A-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433A -15JC
CY7C433A -15PC
J65
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
Document #: 38-00249
5-61
Operating
Range
Commercial
Commercial
CY7C432
CY7C433
Cascadable 4Kx 9 FIFO
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
A Half Full (HF) output flag is provided
that is valid in the standalone and width expansion configurations. In the depth expansion configuration, this pin provides
the expansion out (XO) information that is
used to tell the next FIFO that it will be activated.
In the standalone and width expansion
configurations, a LOW on the retransmit
(RT) input causes the F..!FOs to retransmit
the data. Read enable (R) and write enable
(W) must both be HlGH during a retransmit cycle, and then R is used to access the
data.
The CY7C432 and CY7C433 are fabricated using advanced 0.8-micron N-well
CMOS technology. Input ESD protection
is greater than 2000V and latch-up is prevented by careful layout, guard rings, and a
substrate bias generator.
Functional Description
4096 x 9 FIFO buffer memory
Dual-port RAM cell
Asynchronous read/write
High-speed 28.5-MHz read/write
independent of depth/width
25-ns access time
Low operating power
- Icc (max.) = 142 rnA commercial
- Icc (max.) = 155 rnA military
Half Full flag in standalone
Empty and Full flags
Expandable in width and depth
Retransmit in standalone
Parallel cascade minimizes
bubble-through
5V ± 10% supply
300-mil DIP packaging
300-mil SOJ packaging
TTL compatible
Three-state outputs
Pin compatible and functionally
equivalent to IDT7204
e
•
•
•
The CY7C432 and CY7C433 are first-in
first-out (FIFO) memories offered in
600-mil-wide and 300-mil-wide packages,
respectively. They are 4096 words by 9 bits
wide. Each FIFO memory is organized so
that the data is read in the same sequential
order that it was written. Full and Empty
flags are provided to prevent overrun and
underrun. Three additional pins are also
provided to facilitate unlimited expansion
in width, depth, or both. The depth expansion technique steers the control signals
from one device to another in parallel, thus
eliminating the serial addition of propagation delays so that throughput is not reduced. Data is steered in a similar manner.
The read and write operations may be
asynchronous; each can occur at a rate of
28.5 MHz. The write operation occurs
when the write (W) signal is LOW. Read
occurs when read (R) goes LOW. The 9
data outputs go to the high-impedance
state when R is HIGH.
Logic Block Diagram
Pin Configurations
DATA INPUTS
(Do-Os)
PLCCILCC
Top View
0'" 0'''1:5: ~
DIP
Top View
()
>()
c"
CID
W
06
07
NC
FLJRi
03
04
Os
02
06
01
07
DO
FLIRT
MR
Xi
~
FF
MR
ff
01
NC
i 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Industrial
- 40°C to +85°C
5V ± 10%
Military[l]
- 55°C to +125°C
5V ± 10%
Range
Commercial
Electrical Characteristics Over the Operating Rangel 2]
7C432-25
7C433-25
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Test Conditions
Min.
= Min., IOH = - 2.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Max.
Unit
0.4
V
2.0
Vee
V
2.2
Vee
0.8
-3.0
0.8
V
f.tA.
2.4
Vee
0.4
Com'l
2.0
Vee
-3.0
V
VIL
Input LOW Voltage
Irx
Input Leakage Current
GND~VI~Vee
-10
+10
-10
+10
loz
Output Leakage Current
RL VIR, GND~ Vo~ Vee
-10
+10
-10
+10
!lA
lee
Operating Current
Vee = Max.,
lOUT = ornA
135
rnA
ISBI
Standby Current
All Inputs
Com'I[3]
140
Mil/Ind[4]
= VIR Min.
Com'l
155
25
Mil/Ind
ISB2
Power-Down Current
All Inputs L Vee - 0.2V Com'l
los
Output Short
Circuit Current[5]
Vee
= Max., VOUT = GND
Notes:
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
Icc (commercial) = 110 rnA + [(f - 12.5) • 2 mNMHz] for
f~ 12.5 MHz
where f = the larger of the write or read operating frequency.
4.
5.
5-63
Icc (military) =
25
rnA
30
20
Mil/Ind
3.
Min.
2..4
Mil/Ind
1.
2.
7C432-30
7C433-30
20
rnA
25
-90
-90
rnA
130 rnA + [(f - 12.5) • 2 mA/MHz] for
f~12.5 MHz
where f = the larger of the write or read operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
I
en
oLL.
u:
CY7C432
CY7C433
~
~~PRESS
~, SEMICONDUcrOR
Electrical Characteristics Over the Operating Rangel2] (continued)
77C432-40
77C433-40
Parameter
Test Conditions
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
Min.
= Min., lOR = - 2rnA
Vee == Min., IOL = 8.0 rnA
77C432-65
77C433-65
Max.
Min.
Unit
Max.
2..4
2.4
Vee
V
0.4
0.4
V
Com'l
2.0
Vee
2.0
Vee
V
Mil/lnd
2.2
Vee
2.2
Vee
V
-3.0
0.8
-3.0
0.8
V
VIL
Input LOW Voltage
IIX
Input Leakage Current
GNDsVIsVee
-10
+10
-10
+10
!LA
Ioz
Output Leakage Current
R~
-10
+10
-10
+10
!-tA
rnA
Operating Current
lee
Vee = Max.,
lOUT = ornA
Standby Current
ISBI
All Inputs
= VIR Min.
Com'l[3]
125
110
Mil/lnd[4]
145
130
Com'l
25
25
Mil/lnd
30
30
20
20
25
25
-90
-90
All Inputs ~ Vee - O.2V Com'l
Power-Down Current
ISB2
VIR,GNDs Vas Vee
Mil/lnd
Output Short Circuit
Current[5]
los
Vee
= Max., VOUT = GND
rnA
rnA
rnA
Capacitance[6]
.Description
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 4.5V
= 1 MHz,
Max.
Unit
8
pF
10
pF
Note:
6. Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveforms
OUTP~~~R1
500Q
30pF
I
5 pF
R2
333Q
INCLUDING _
JIG AND SCOPE
_
- C432-4
R2
333Q
I _
INCLUDING
JIG AND SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ----..u-~':"'"""--~
5V31R1500Q
OUTPUT
-
C432-5
(b)
THEVENIN EQUIVALENT
200Q
OUTPUToo----~y~~__--__OO
2V
5-64
GND
C432-6
CY7C432
CY7C433
~
~
.::Z
~.aCYPRESS
=-,
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 7,8]
7C432-25
7C433-25
Description
Parameter
Max.
Min.
7C432-30
7C433-30
Min.
Max.
40
35
7C432-40
7C433-40
Min.
Max.
7C432-65
7C433-65
Min.
Max.
80
ns
Read Cycle Time
tA
Access Time
tRR
tpR
Read Recovery Time
10
10
10
15
ns
Read Pulse Width
25
30
40
65
ns
tLZR l9j
tDvR l9 ,lOj
tHZR l9 ,lUj
Read LOW to Low Z
3
3
3
3
ns
Read HIGH to Data Valid
3
3
3
3
ns
twc
tpw
tHWzl9j
Write Cycle Time
35
40
50
80
ns
Write Pulse Width
25
30
40
65
ns
Write HIGH to Low Z
10
10
10
10
ns
tWR
Write Recovery Time
10
10
10
15
ns
ns
25
Read HIGH to High Z
50
Unit
tRC
18
65
40
30
25
20
30
ns
ns
tSD
Data Set-Up Time
15
18
20
30
tHO
Data Hold Time
0
0
0
10
ns
tMRSC
MR Cycle Time
35
40
50
80
ns
tpMR
MR Pulse Width
25
30
40
65
ns
tRMR
MR Recovery Time
10
10
10
15
ns
tRPw
Read HIGH to MR HIGH
25
30
40
65
ns
twpw
Write HIGH to MR HIGH
25
30
40
65
ns
tRTC
Retransmit Cycle Time
35
40
50
80
ns
tpRT
Retransmit Pulse Width
25
30
40
65
ns
tRTR
Retransmit Recovery Time
10
10
10
15
tEFL
MRtoEFLOW
35
40
50
80
ns
tHFH
MR to HFHIGH
35
40
50
80
ns
tFFH
MR toFFHIGH
35
40
50
80
ns
tREF
Read LOW to EF LOW
25
30
35
60
ns
tRFF
Read HIGH to FF HIGH
25
30
35
60
ns
tWEF
Write HIGH to EF HIGH
25
30
35
60
ns
tWFF
Write LOW to FF LOW
25
30
35
60
ns
tWHF
Write LOW to HF LOW
35
40
50
80
ns
tRHF
Read HIGH to HF HIGH
35
40
50
80
ns
tRAE
Effective Read from Write HIGH
25
30
35
60
tRPE
Effective Read Pulse Width after EF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width after FF HIGH
tXOL
Expansion Out LOW Delay from Clock
25
30
40
65
ns
tXOH
Expansion Out HIGH Delay from Clock
25
30
40
65
ns
25
30
Notes:
7. Test conditions assume signal transition time of S ns or less, timing reference levels of l.5V and output loading of the specified IOrJIOH and
30-pF load capacitance, as in part (a) of AC Test Loads, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
40
30
9.
ns
ns
65
35
30
25
25
40
ns
60
65
ns
ns
tHzRtransitionismeasuredat+SOOmVfromVOLand-SOOmVfrom
VOH. tnvR transition is measured at the l.5V level. tHWZ and tLZR
transition is measured at ± 100 m V from the steady state.
10. tHZR and tnvR use capacitance loading as in part (a) of AC Test Loads.
5-65
I
en
oLI.
u::
CY7C432
CY7C433
-~
~... CYPRESS
·
~,
SEMICONDUCTOR
Switching Waveforms
Asynchronous Read and Write
""""-____..,,1
------f( '--_____ l - - - - - - - «
Master Reset
~--- tMRSC[11]
MR __________~~----tpMR
)>----
DATA VALID
:432-7
--------.-1
--------~~----~-----------------
R,Vi7[12]
FF
l/lfl/l//ZIZj////11a
C432-8
Half·FuIl Flag
HALF-FULL + 1
HALF-FULL
HALF-FULL
-
;:J~
tRHF
~
~
I-
tWHF ...
:r--
~
C432-9
Notes:
11. tMRSC = tpMR + tRMR·
12. WaIldR~ VIII for at least t\VP\V or tRPR before the rising edge ofMRo
5-66
.
CY7C432
CY7C433
:~
'iIi CYPRESS
~,
SEMICONDUCTOR
Switching Waveforms (continued)
Last Write to First Read Full Flag
LAST WRITE
R --~--------------~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
w
IT
--~----'\I
C432-10
Last Read to First Write Empty Flag
•
U)
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
oLL.
FIRST READ
u:::
w---r--------------~~
EF
--+--+--'11
DATA OUT
C432-11
Retransmid 13 ]
tRTcl 14I
I+---
tpRT
-' ...
R,w
~
I+-
tRTR-
C432-12
Notes:
13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC.
14. tRTC = tpRT + tRTR·
5-67
CY7C432
CY7C433
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
DATA IN
w--+---"\.
ff--+---------~-J
DATA OUT
C432-13
Full Flag and Write Data Flow-Through Mode
w
IT - - + - - - - - - - - - - - 1 - - - '
DATAIN --~-------------_[
t~J
DATA OUT
---~~-D-A-JA-VA-L-ID---')@-------------------
C432-14
5-68
CY7C432
CY7C433
~
.
_
i~PRESS
JF
SEMICONDUCTOR
Switching Waveforms (continued)
Expansion
WRITE TO FIRST PHYSICAL
LOCATION OF DEVICE 2
WRITE TO LAST PHYSICAL
LOCATION OF DEVICE 1
II
C432-15
READ FROM FIRST PHYSICAL
LOCATION OF DEVICE 2
READ FROM LAST PHYSICAL
LOCATION OF DEVICE 1
C432-16
Note:
15. Expansi2!t Out of device 1 (XOI) is connected to Expansion In of device 2 (XIz).
5-69
.
CY7C432
CY7C433
:~pRF.SS
-::::;;;;;;,
SEMICONDUCTOR
Architecture
The CY77C432/33 FIFOs consist of an array of 4096 words of 9
bits each (implemented by an array of dual-~~RAM cells ~ read
~ter, a write pointer, control signals (W, R, XI, XO, FL, RT,
MR), and Full, Half Full, and Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell
used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve
truly asynchronous operations of the inputs and outputs. A second
benefit is that the time required to increment the read and write
pointers is much less than the time that would be required for data
to propagate through the memory, which would be the case if the
memory were implemented using the conventional register array
architecture.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset (MR)
cycle. This causes the FIFO to enter the empty condition signified
by the empty fl~ (EF) being LOW, and both t~ Half Full (H~)
and Full flag (FF) resetting to HIGH. Read (R) and write (W)
must be HIGH tRPW/tWpw nanoseconds before and tRMR nanoseconds after the rising edge of MR for a valid reset cycle.
Writing Data to the FIFO
The availability of an~pty location is indicated ~ the HIGH
state of the Full flag (FF). A falling edge of write (W) initiates a
write cycle. Data appearing at the inputs (Do- Ds) tSD before and
tHD after the rising edge of W will be stored sequentially in the
FIFO.
The Empty flag (EF) LOW-to-HIGH transition occurs tWEF
nanoseconds after the first LOW-to-HIGH transition on the write
clock of an empty FIFO. The Half Full flag (HF) will go LOW on
the falling edge of the write clock following the occurrence of half
full. HF will remain LOW while less than one half of the total
memory ofthis device is available for writing. The LOW-to-HIGH
transition of the HF flag occurs on the rising edge of rea
g:
125
~ 1.21------4-------l
«
0.9
4.5
5.0
r--
5.5
SUPPLY VOLTAGE
z
~
0.6 l....-_ _ _---l_ _ _ _ _.....l
-55
125
25
a..
4.0
M
~
100
/'
60
/
40
/
o r7
/
Vee = 5.0V
TA = 25°C
~ 20
o
0.0
AMBIENT TEMPERATURE (0C)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
'"
3.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
()
c;;
M
2.0
:::>
~ 1.0
0.81-------+-------1
6.0
1.0
w
a:
a: 80
~
::2:
TA = 25°C
...............
0
0.0
OUTPUT VOLTAGE
!z
::J
~
5
~
.s
o
w
.........
20
« 120
,.$-1.4
..............
40
Vee = 5.0V
TA = 25°C
~ "-
~
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
N
0.8
4.0
g
1.6
1.3
::2:
a:
0 1.0
z
80
AMBIENT TEMPERATURE (0C)
..$
0 1.2
1.1
Vee = 5.5V
VIN = 5.0V
P=20 MHz
-55
1.4
«
:::>
~ 60
a:
0.0
M
100
a:
a:
:::>
0.2
6.0
a:i
()
z
-
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
::J
~
..!:? 0.8
0
w
N
::J 0.6
«
::2:
a: 0.4
0
VIN = 5.0V
TA = 25°C
0.2
§. 120
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
~
u
V
N
::J 0.6
«
::2:
a: 0.4
0
r----1.0
/
1.0
~
1.0
2.0
3.0
OUTPUT VOLTAGE
4.0
M
NORMALIZED Icc vs. CYCLE TIME
1.6
1.5
Vee = 5.0V
TA = 25°C
/
..$
0 1.4
w
N
::J
«
::2:
a:
0 1.2
u
..!:?
o 1.01----+---:JJII'II!::....-+-----l
w
N
z
1.0
o
./
V
200
::J
"V
V
«
::2:
~ 0.51-~--+---+-----l
Z
Vee = 5.0V
TA = 25°C
400
600
0.0
800 1000
l....-_ _--L_ _ _l....-_ _.....l
10
20
30
40
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
e432-18
5-72
CY7C432
CY7C433
~
~
== , ~PRffiSNDUcrOR
Ordering Information
Speed
(ns)
25
30
40
65
Ordering Code
Package
Name
Package 1Ype
Operating
Range
CY7C432-2SDC
DI6
28-Lead (600-Mil) CerDIP
CY7C432-2SPC
PIS
28-Lead (600-Mil) Molded DIP
Commercial
CY7C432-30DC
DI6
28-Lead (600-Mil) CerDIP
CY7C432-30PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C432-30PI
PIS
28-Lead (600-Mil) Molded DIP
Industrial
CY7C432-30DMB
DI6
28-Lead (600-Mil) CerDIP
Military
CY7C432-40DC
DI6
28-Lead (600-Mil) CerDIP
Commercial
CY7C432-40PC
PIS
28-Lead (600-Mil) Molded DIP
Commercial
CY7C432-40PI
PIS
28-Lead (600-Mil) Molded DIP
Industrial
CY7C432-40DMB
DI6
28-Lead (600-Mil) CerDIP
Military
CY7C432-6SDC
DI6
28-Lead (600-Mil) CerDIP
Commercial
CY7C432 - 6SPC
PIS
28-Lead (600-Mil) Molded DIP
en
CY7C432-6SPI
PIS
28-Lead (600-Mil) Molded DIP
Industrial
CY7C432-6SDMB
DI6
28-Lead (600-Mil) CerDIP
Military
5-73
•
ou.
LL:
CY7C432
CY7C433
~
~.CYPRESS
~, SEMICONDUCTOR
Ordering Information (continued)
Speed
(ns)
25
30
40
65
Ordering Code
Package
Name
Package 1Ype
CY7C433-25DC
D22
28-Lead (300-Mil) CerDIP
CY7C433 - 25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433 - 25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433-25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C433-30DC
D22
28-Lead (300-Mil) CerDIP
CY7C433 - 30JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433-30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C433 - 30VC
V21
28-Lead (300-MiI) Molded SOJ
CY7C433-30JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433-30PI
P21
28-Lead (300-Mil) Molded DIP
CY7C433...;.30DMB
D22
28-Lead (300-Mil) CerDIP
CY7C433 - 30KMB
K74
28-Lead Rectangular Cerpack
CY7C433- 30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C433-40DC
D22
28-Lead (300-Mil) CerDIP
CY7C433-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433-40PC
P21
28-Lead (300-MiI) Molded DIP
CY7C433-40VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C433-40JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433-40PI
P21
28-Lead (300-MiI) Molded DIP
CY7C433 -40DMB
D22
28-Lead (300-Mil) CerDIP
CY7C433-40KMB
K74
28-Lead Rectangular Cerpack
CY7C433 -40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C433-65DC
D22
28-Lead (300-Mil) CerDIP
CY7C433-65JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433-65PC
P21
28-Lead (300-MiI) Molded DIP
CY7C433-65VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C433-65JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C433 - 65PI
P21
28-Lead (300-Mil) Molded DIP
CY7C433-65DMB
D22
28-Lead (300-MiI) CerDIP
CY7C433-65KMB
K74
28-Lead Rectangular Cerpack
CY7C433 -65LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-74
Operating
Range
Commercial
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
.::::or:
.~PRFSS
-
JF
CY7C432
CY7C433
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VIR
VILMax.
IIX
Icc
ISBl
ISB2
los
Switching Characteristics
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Parameters
Subgroups
9,10,11
9,10,11
9,10,11
tRR
9,10,11
tpR
9,10,11
tLZR
9,10,11
tDVR
9,10,11
tHZR
9,10,11
twc
9,10,11
tpw
9,10,11
tHwz
9,10,11
tWR
9,10,11
tSD
9,10,11
tHD
9,10,11
tMRSC
9,10,11
tpMR
9,10,11
tRMR
9,10,11
tRPW
9,10,11
twpw
9,10,11
tRTC
9,10,11
tpRT
9,10,11
tRTR
9,10,11
tEFL
9,10,11
tHFH
9,10,11
tFFH
9,10,11
tREF
9,10,11
tRFF
9,10,11
tWEF
9,10,11
tWFF
9,10,11
tWHF
9,10,11
tRHF
9,10,11
tRAE
9,10,11
tRPE
9,10,11
tWAF
9,10,11
tWPF
9,10,11
tXOL
9,10,11
tXOH
Document #: 38-00109-C
tRC
tA
5-75
II
en
oLL.
u::
CY7C439
CYPRESS
SEMICONDUCTOR
Bidirectional 2K x 9 FIFO
Features
Functional Description
• 2048 x 9 FIFO buffer memory
• Bidirectional operation
• High-speed 28.S-MHz asynchronous
reads and writes
• Simple control interface
• Registered and transparent bypass
modes
• Flags indicate Empty, Full, and Half
Full conditions
The CY7C439 is a 2048 x 9 FIFO memory
capable of bidirectional operation. As the
term first -in first -out (FIFO) implies, data
becomes available to the output port in the
same order that it was presented to the input port. There are two pins that indicate
the amount of data contained within the
FIFO block-ElF (Empty/Full) and HF
(Half Full). These pins can be decoded to
determine one of four states. Two 9-bit
data ports are provided. The direction selected for the FIFO determines the input
and output ports. The FIFO direction can
be programmed by the user at ~ time
through the use of the rese~MR) and
the bypass/direction pin (BYPA). There
are no control or status registers on the
CY7C439, making the part simple to use
• 5V ± 10% supply
• Available in 300-mil DIP, PLCC, LCC,
and SOJ packages
• TTL compatible
while meeting the needs of the majority of
bidirectional FIFO applications.
FIFO read and write operations may occur
simultaneously, and each can occur at up
to 28.5 MHz. The port designated as the
write port drives its strobe pin (STBX, X =
A or B) LOW to initiate the write operation. The port designated as the read port
drives its strobe pin LOW to initiate the
read operation. Output port pins go to a
high-impedance state when the associated
strobe pin is HIGH. All normal FIFO operations require the bypass control pin
(BYPX, X = A or B) to remain HIGH.
In addtion to the FIFO, two other data
paths are provided; registered bypass and
transparent bypass. Registeredbypasscan
beconsideredasasingle-wordFIFO in the
reverse direction to the main FIFO. The
Logic Block Diagram
Pin Configurations
PLCC/LCC
Top View
A2
A,
Ao
8YI5A
GND
B?J5Ej
IIDA
Bo
NC
B,
TRANSPARENT
BYPASS
A:J A.!NCA5 As A7
4 3 2: 1,32 31 30
29
5
6
7
8
7C439
9
10
11
12
13
14151617181920
As
1':11'
NC
STElA
Vss
MIl
STIID
RF
Be
B2 BaB4 NC B5 B6 B7
C439-2
DIP
Top View
FLAG
As
As
A.!
Aa
A2
A,
I---HH~ CONTROL
A7
As
Ao
EiF
aYJ5A
STBA
GND
Vee
MR
Silm
RF
Ii'i'PB
I30A
2048 x9
FIFO
Bo
B,
Be
B7
B2
C439-1
B6
Ba
B4
B5
C439-3
Selection Guide
7C439-2S
28.5
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating
Current (rnA)
; Commercial
I Military
5-76
7C439-30
25
7C439-40
20
7C439-6S
12.5
25
30
40
65
1 A '"7
pt/
.l .... u
LJV
115
170
160
145
1At"'
.--
;~PRESS
~,
CY7C439
SEMICONDUCTOR
Functional Description (continued)
bypass register provides a means of sending a 9-bit status or control
word to the FIFO-write port. The bypass data available pin (BDA)
indicates whether the bypass registeris full or empty. The direction
of the bypass register is always opposite to that of the main FIFO.
The port designated to write to the bypass register drives its bypass
control pin (BYPX) LOW. The other port detects the presence of
data by ~onitoring BDA and reads the data by driving its bypass
control pm (BYPX) LOW. Register~ass operations require
~hat the associated FIFO strobe pin (STBX) remains HIGH. Reg1stered bypass operations do not affect data residing in the FIFO,
or FIFO operations at the other port.
Transparent bypass provides a means of transferring a single word
(9 bits) of data immediately in either direction. This feature allows
the device to act as a simple 9-bit bidirectional buffer. This is useful
for allowing the controlling circuitry to access a dumb peripheral
for control/programming information.
For transparent bypass, the port wishing to send immediate data to
the other side drives both its bypass and its strobe pins LOW simultaneously. This causes the buffered data to be driven out of the other port. On-chip circuitry detects conflicting use of the control pins
and causes both data ports to enter a high-impedance state until
the conflict is resolved.
Additionally, a Test mode is offered on the CY7C439. This mode
allows the user to load data into the FIFO and then read it back out
of the same port. Built-In Self Test (BIST) and diagnostic functions
can take advantage of these features.
The CY7C439 is fabricated using an advanced 0.811 N-well CMOS
technology. Input ESD protection is greater than 2000V and latchup is prevented by reliable layout techniques, guard rings, and a
substrate bias generator.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 0 C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current .......................... ; > 200 rnA
Operating Range
I/O
Description
A(S-O)
I/O
Data Port Associated with BYPA and STBA
B(S-O)
I/O
Data Port Associated with BYPB and STBB
BYPA
I
Registered Bypass Mode Select for A Side
BYPB
I
Registered Bypass Mode Selectr for B Side
BDA
0
Bypass Data Available Flag
STBA
I
Data Strobe for A Side
STBB
I
Data Strobe for B Side
ElF
0
Encoded EmptylFull Flag
HF
0
Half Full Flag
MR
I
Master Reset
Ambient
Temperature
Vee
Commercial
O°C to +70°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Military[lj
Note:
1.
Pin Definitions
Signal
Name
Range
5-77
TA is the "instant on" case temperature.
I
en
oII.
u:::
~
~~PRESS
~, SEMICONDUCIOR
CY7C439
Electrical Characteristics Over the Operating Rangel2)
Parameter
VOH
Description
Output HIGH
Voltage
Vee
rnA
Output LOW
Voltage
Input HIGH
Voltage
VOL
VIH
7C439-25
Min. Max.
2.4
Test Conditions
Vee
= Min., 10H = -
2.0
= Min., 10L = 8.0 rnA
7C439-30
Min. Max.
2.4
0.4
0.4
Com'l
Mil
7C439-40
Min. Max.
2.4
7C439-65
Min. Max.
2.4
0.4
Unit
V
0.4
V
0.8
2.2
2.2
- 3.0
Vee
Vee
0.8
2.2
2.2
- 3.0
Vee
Vee
0.8
2.2
2.2
- 3.0
Vee
Vee
0.8
V
V
V
2.2
Vee
- 3.0
VIL
Input LOW
Voltage
IIX
Input Leakage
Current
GND~ VI5....Vee
-10
+10
-10
+10
-10
+10
-10
+10
!!A
loz
Output Leakage
Current
STBX~
-10
+10
-10
+10
-10
+10
-10
+10
!!A
rnA
VIH,
GND~ Vo~
Icc
Vee
Com'I[3)
Operating Current Vee = Max.,
lOUT = ornA
Mil[4)
ISBI
Standby Current
AllInputs = VIH
Min.
ISB2
Power-Down
Current
All Inputs
Vee - 0.2V
los
Output Short
Circuit Current[5)
Vee = Max., VOUT = GND
147
Com'l
Mil
Com'l
Mil
40
20
- 90
140
130
115
170
160
145
40
45
20
25
- 90
40
45
20
25
40
45
20
25
- 90
- 90
rnA
rnA
rnA
Capacitance[6)
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f
Vee = 4.5V
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Icc (commercial} = 115 rnA + [(f - 12.5)' 2 mA/MHz] for
f~ 12.5 MHz
where f = the larger of the write or read
operating frequency.
4.
Unit
pF
pF
+ [(f - 12.5) . 2 mA/MHz] for
12.5 MHz
where f = the larger of the write or read
operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
Icc (military)
= 145 rnA
f~
5.
6.
5V31
I _
Max.
8
10
= 1 MHz,
AC Test Loads and Waveform
R1500Q
OUTPUT
30 pF
R1500Q
OUTP~~~
R2
5 PF
333Q
INCLUDING
JIG AND SCOPE
I
R2
-
GND
333Q
INCLUDING _
JIG AND SCOPE
_
C439-4
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.0V -----.:t.~----~
90%
THEVENIN EQUIVALENT
200Q
OUTPUT~o--~Y~~__--~o2V
5-78
C439-5
=.
-~
JF SEMICONDUCTOR
--=-
CY7C439
_ ' j E CYPRESS
Switching Characteristics Over the Operating Rangel 7,8j
7C439-25
Description
Parameter
Min.
Max.
Min.
Max.
Max.
Max.
Unit
ns
Read Cycle Time
Access Time
tRR
Read Recovery Time
10
10
10
15
ns
tpR
Read Pulse Width
25
30
40
65
ns
tLZR[9,lOj
Read LOW to Low Z
3
3
3
3
ns
3
3
ns
25
50
7C439-65
Min.
tRC
Data Valid from Read HIGH
40
7C439-40
Min.
tA
tDVR[9,lOj
35
7C439-30
3
3
80
40
30
65
ns
tHZR[9,lOj
Read HIGH to High Z
twc
Write Cycle Time
35
40
50
80
ns
tpw
Write Pulse Width
25
30
40
65
ns
tHWZ[9,lOj
Write HIGH to Low Z
10
10
10
10
ns
tWR
Write Recovery Time
10
10
10
15
ns
tSD
Data Set-Up Time
15
18
20
30
ns
tHD
Data Hold Time
0
0
0
10
ns
18
20
25
30
ns
tMRSC
MR Cycle Time
35
40
50
80
ns
tpMR
MR Pulse Width
25
30
40
65
ns
tRMR
MR Recovery Time
10
10
10
15
ns
tRPS
STBX HIGH to MR HIGH
25
30
40
65
ns
tRPBS
BYPA to MR HIGH
10
10
15
20
ns
tRPBH
BYPA Hold after MR HIGH
0
tBDH
MR LOW to BDA HIGH
tBSR
STBX HIGH to BYPA LOW
tEFL
MR to ElF LOW
35
40
50
80
tHFH
MR to HFHIGH
35
40
50
80
10
40
10
10
0
0
0
35
10
ns
80
50
15
ns
15
10
ns
ns
ns
ns
tBRS
BYPX HIGH to STBX LOW
tREF
STBX LOW to ElF LOW (Read)
25
30
35
60
ns
tRFF
STBX HIGH to ElF HIGH (Read)
25
30
35
60
ns
tWEF
STBX HIGH to ElF HIGH (Write)
25
30
35
60
ns
tWFF
STBX LOW to ElF LOW (Write)
25
30
35
60
ns
tBDA
BYPX HIGH to BDA LOW (Write)
25
30
35
60
ns
tBDB
BYPX HIGH to BDA HIGH (Read)
25
30
35
60
ns
10
tBA
BYPX LOW to Data Valid (Read)
30
30
40
60
ns
tBHZ[9,lOj
BYPX HIGH to High Z (Read)
18
20
25
30
ns
tTSB
STBX HIGH to BYPX LOW Set-Up
10
tTBS
STBX LOW after BYPX LOW
0
tTSN
tTSD[9,lOj
STBX HIGH Recovery Time
10
tTBN
BYPX HIGH Recovery Time
tTBD
BYPX HIGH to Data High Z
STBX HIGH to Data High Z
10
0
10
10
10
ns
10
15
10
20
0
25
20
10
18
0
15
10
10
18
5-79
10
10
ns
30
15
25
ns
ns
ns
30
ns
•
rn
ou.
u:::
~
;i~PRFSS
•
CY7C439
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Range[7,8j (continued)
7C439-25
7C439-30
7C439-40
7C439-65
Max;
Unit
tTPo[9,lOj
STBX LOW to Data Valid
20
20
30
55
ns
tOL
Transparent Propagation Delay
20
25
30
ns
tESO[9,lOj
STBX LOW to High Z
20
18 .
20
25
30
ns
tEBO[9,lOj
BYPX LOW to High Z
18
20
25
30
ns
tEDS
STBX HIGH to Low Z
18
20
25
30
ns
30
ns
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
tEDB
BYPX HIGH to Low Z
tBPW
BYPX Pulse Width (Trans.)
25
30
40
65
ns
tTSP
STBX Pulse Width (1fans.)
20
20
30
55
ns
tBLZ[9,lOj
BYPX LOW to Low Z (Read)
10
10
10
10
ns
tBDV
BYPX HIGH to Data Invalid (Read)
3
3
3
3
tWHF
STBX LOW to HF LOW (Write)
35
tRHF
STBX HIGH to HF HIGH (Read)
tRAE
Effective Read from Write HIGH
tRPE
Effective Read Pulse Width after ElF
HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width after ElF
HIGH
25
30
40
65
ns
tBSU
Bypass Data Set-Up Time
15
18
20
30
ns
tBHL
Bypass Data Hold Time
0
0
0
10
ns
18
20
ns
40
50
80
ns
35
40
50
80
ns
25
30
35
60
ns
25
30
25
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, and output loading of the specified IOlfIoH and
30-pF load capacitance as in part (a) of AC Test Loads, unless otherwise specified.
8. See the last page of this specification for Group A subgroup testing information.
25
40
30
65
35
ns
60
ns
tOVR, tBOV, tHZR, tTBO, tBHZ, tEBO, tESO, tTSO, tLZR, tHWZ, and tBLZ
use capacitance loading as in part (b) of AC Test Loads.
10. tHZR, tTBO, tBHZ, tEBO, tESO, and tTSO transition is measured at +500
mV from VOL and - 500 mV from VOH. tovR and tBov transition is
measured at the 1.5V level. tLZR, tHWZ, and tBLZ transition is measured at ± 100 mV from the steady state.
9.
Switching Waveforms
Asynchronous Read and Write Timing Diagram
READ
STBB[ll)
i!--------~B[111
~ ~O =t ~
--------1(1<=
PORT B
WRITE
--------l(
twc
-------~
----_/
tHO
PORT A
DATA VALID.
--------«"'___D_A_TA_V_A_L1_D___>---:39_6
=>Ill-,
5-80
~
==.
;~PRESS
~,
CY7C439
SEMICONDUCTOR
Switching Waveforms (continued)
Master Reset Timing Diagram
MR
STBA/STBB
BYPA
•
BYPB
en
0
BDA
II.
u:::
ElF
HF
C439-7
Half-Full Flag Timing Diagram[12]
HALF FULL
HALF FULL
+1
~K.
HALF FULL
I--
tRHF -
;~
~ tWHF ....
~,
/
r-C439-8
Last Write to First Read EmptylFuli Flag Timing Diagram[12]
LAST WRITE
ADDITIONAL READS
FIRST READ
FIRST WRITE
C439-9
Notes:
11. Direction selected Port A to Port B.
12. Direction selected as A to B.
5-81
·
~~PRFSS
CY7C439
~IF SEMICONDUCTOR
Switching Waveforms (continued)
Last Read to First Write Empty/Full Flag Timing Diagram[12]
LAST READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
ElF
DATA OUT
C439-10
Empty/Full Flag and Read Bubble-Through Mode Timing Diagram[12]
DATA IN
(PORTA)
ElF
EMPTY
DATA OUT
(PORT B)
DATA VALID
C439-11
Empty/Full Flag and Write Bubble-Through Mode Timing Diagram[12]
,,-----ElF
FULL
DATA IN
(PORTA)
DATA VALID
DATA OUT
(PORT B)
C439-12
5-82
. ~~
~~= CYPRESS
- , SEMICONDUCI'OR
CY7C439
Switching Waveforms (continued)
Registered Bypass Read Timing Diagram[13]
tBSR
---_014---
PORTS
C439-13
tn
u:::
PORTA
tBPW
---------t·+I·... ~~
t-------C439-14
Transparent Bypass Read Timing Diagram[15]
1 4 - - - - - - - tTSP ------~----- tBSR - - - - - - - . !
~~~~--------~
-------~~-~-------tBPW ----~--~.~----------~
rPORTA
•
oLL.
Registered Bypass Write Timing Diagram[14]
tTPD
VALID INPUT 1
PORTS
VALID OUTPUT 2
C439-15
Notes:
13. Port B selected to read bypass register (FIFO direction Port B to
PortA).
14. Port A selected to write bypass register (FIFO direction Port B to
PortA.
15. Diagram shows transparent bypass initiated by PortA. Times are identical if initiated by Port B.
5-83
~
~~PRF.SS
~_IF SEMICONDUcrOR
CY7C439
Switching Waveforms (continued)
Test Mode Timing Diagram
C439-16
Exception Condition Timing Diagram[15j
~
________________________________
~;I
--------------------------~/'
DATAB
VALID OUTPUT
,~------H-IG-H-Z----__1(V
----------------/
VALID OUTPUT
I~'--------------------C439-17
Architecture
The CY7C439 consists of a 2048 by 9-bit dual-ported RAM array,
a read pointer, a write pointer, data switching circuitry, buffers, a
bypassreg~~,controlsignals(STBA,STBB,BYPA,BYPB,MR),
and flags (ElF, HF, BOA).
Operation at Power-On
~n
power,up, the FIFO must be reset wi.t~ ~ ~aster Re~et
(MR) cycle. During an MR cycle, the user can Imtlahze the devl~e
by choosing the direction of FIFO operation (see Table 1). There IS
a minimum LOW period for MR, but no maximum time. The state
of BYPA is latched internally by the rising edge of MR and used to
determine the direction of subsequent data operations.
Resetting the FIFO
During the reset condition (see Table 1), the FIFO three-states
the data ports, sets BOA and HF HIGH, ElF LOW, and ignores
the state of BYPA/B and STBAJB. The bypass registers are initialized to zero. During this time the user is expected to set the direction of the FIFO by driving BYPA HIGH or LOW, and BYPB,
STBA, and STBB HIGH. If BYPA is LOW (selecting direction
B>A), the FIFO will then remain in a reset condition until the
user terminates the reset operstion by driving BYPA HIGH. If
BYPAis HIGH (selecting direction A> B), the reset condition ter-
minates after the rising edge of MR. The entire reset phase can be
accomplished in one cycle time of tRe.
FIFO Operation
The operation of the FIFO requires only one control pin per port
(STBX). The user determines the direction of the FIFO data flow
by initiating an MR cycle (see Table 1), which clears the FIFO and
bypass register and sets the data path and control signal multiplexers. The bypass register is configured in the opposite direction to
the FIFO data flow. The FIFO direction can be reversed at any
time by initiating another MR cycle. Data is written into the FIFO
on the rising edge of the input, STBX, and read from the FIFO by
a low level at the output, STBX. The two ports are asynchronous
and independent. If the user attempts to read the FIFO when it is
empty, no action takes place (the read pointer is not incremented)
until the other port writes to the FIFO. Then a bubble-through
read takes place, in which the read strobe is generated internally
and the data becomes available at the read port shortly thereafter
if the read strobe (STBX) is still LOW. Similarly, for an attempted
write operation when the FIFO is full, no internal operation takes
place until the other port performs a read operation, at which time
the bubble-through write is performed if the write strobe (STBX)
is still LOW.
5-84
-
- ·j;4
======:d
CYPRESS
-===IF
CY7C439
SEMICONDUCIOR
Registered Bypass Operation
The registered bypass feature provides a means of transferring one
9-bit word of data in the opposite direction to normal data flow
without affecting either the FIFO contents or the FIFO write operations at the other port. The bypass register is configured during
reset to provide a data path in the opposite direction to that of the
FIFO (see Table 1). For example, if port A is writing data to the
FIFO (hence port B is reading data from the FIFO) then BYPB is
used to write to the bypass register at port B, and BYPA is used to
read a single word from the bypass register at port A. The bypass
data available flag (BDA) is generated to notify port A that bypass
data is available. BDA goes true on the trailing edge of the BYPX
write operation and false upon the trailing edge of the BYPX read
operation.
Data is written on the rising edge of BYPX into the bypass register
for later retrieval by the other port, regardless of the state ofBDA.
The bypass register is read by a low level at BYPX, regardless of the
state of BDA.
Transparent Bypass Operation
The transparent bypass feature provides a means of sendingimmediate data "around" the FIFO in either direction. The FIFO contents are not affected by the use of transparent bypass, but the control signals for transparent bypass are shared with those of the
normal FIFO operation. Hence there are limitations on the use of
transparent bypass to ensure that data integrity and ease of use are
preserved. The port wishing to send immediate data must ensure
that the other port will not attempt a FIFO read or write during the
transparent bypass cycle. If this is not possible, registered bypass or
external circuitry should be used.
Transparent bypass mode is initiated by bringing both BYPA and
STBA LOW together. Care should be taken to observe the following constraints on the timing relationships. Since STBA is used for
normal FIFO operations, it must follow BYPA falling edge by tTBS
to prevent erroneous FIFO read or write operations. Since BYPA
is used alone to initiate registered bypass read and write, it is internally delayed before initiating registered bypass. If STBA falls during this time, delay registered bypass is averted, and transparent
bypass is initiated. Identical arguments apply to BYPB and STBB.
If a transparent bypass sequence is successfully accomplished,
data presented to the initiating port (port A in the above discussion) will be buffered to the other (port B) after tDL' Either port
can initiate a trasspare,!!t ~s operation at any time, but if the
control signals ( TBA/B, BYPAJB) are in conflict (exception condition), internal circuitry will switch both ports to high-impedance
until the conflict is resolved.
Test Mode Operation
The Test mode feature provides a means of reading the FIFO contents from the same port that the data was written to the FIFO.
5
This feature is useful for Built-In Self Test (BIST) and diagnostic
functions. To utilize this capability, initialize FIFO direction A to B
and load data into the FIFO using normal write timing. In order to en
read data back out of the same port (port A), initiate a MR cycle 0
with both BYPA and BYPB LOW (see Test Mode Timing dia- U.
gram). After completing the cycle, the data can be read out of port ii:
A in FIFO order. Data will be inverted when read out of the device.
Also, flags are not valid when reading data.
Flag Operation
There are two flags, Empty/Full (ElF') and Half Full (HF), which
are used to decode four FIFO states (see Table 4). The states are
empty, 1-1024 locations full, 1025 - 2047 locations full, and full.
Note that two conditions cause the ElF pin to go LOW, Empty
and Full, hence both flag pins must be used to resolve the two
conditions.
Table 1. FIFO Direction Select Truth Table
MR
BYPA
BYPB
STBA
STBB
1
X
X
X
X
Normal Operation
FIFO Direction A to B, Registered Bypass Direction B to A
S
S
0
Action
1
1
1
1
0
1
1
1
FIFO Direction B to A, Registered Bypass Direction A to B
X
X
X
X
Reset Condition
Table 2. Bypass Operation Truth Table
Direction
STBA
BYPA
~B
U
1
A.B
1
U
A.B
B.A
STBB
BYPB
Action
U
U
1
Normal FIFO Operations, Write at A, Read at B
1
Normal FIFO Read at B, Bypass Register Read at A
U
U
1
1
U
1
1
Normal FIFO Operations, Write at B, Read at A
B.A
1
U
U
U
1
Normal FIFO Write at B, Bypass Register Write at A
B.A
1
U
Normal FIFO Read at A, Bypass Register Read at B
Normal FIFO Write at A, Bypass Register Write at B
U
1
X
0
0
1
1
No FIFO Operations, Transparent Data A to B
X
1
1
0
0
No FIFO Operations, Transparent Data B to A
5-85
~
~.~
CY7C439
======lfl CYPRESS
~.F
SEMICONDUCTOR
Table 3. Exception Conditions: Operation Not Defined
Action
Direction
STBA
BYPA
STBB
BYBP
X
0
1
0
0
Data Buses High Impedance
X
1
0
0
0
Data Buses High Impedance
X
0
0
0
0
Data Buses High Impedance
X
0
0
1
0
Data Buses High Impedance
X
0
0
0
1
Data Buses High Impedance
Table 4. Flag Truth Table
ElF
HF
0
1
Empty
1
1
1-1024 Locations Full
1
0
1025-2047 Locations Full
0
0
Full
State
'JYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.2 .....----,----,---.,..----,
1.4
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
«
.s
60
r5
50
~
()
40
I-
~ 1.0
~
c
w
N
:J 1.0
:2
:2
o
0
Z
a:
Z
«
0.4 '--_-'-_ _...J...._ _- ' - - _ - - '
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE
~
M
1.6
1.2
N
1.0
a:
0
0.9
Z
25
125
AMBIENT TEMPERATURE (0C)
NORMALIZED tA
vs. AMBIENT TEMPERATURE
:J
4.5
SUPPLY VOLTAGE
M
6.0
B
~
"'~
Vee = 5.0V
TA = 25°C
I
0
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE
«E 140
li!a:
100
()
80
~
~
oZ
I-
~ 1.01---------::1.....= - - - - - 1
TA = 25°C
I
5.0
5.5
~ 10
I-
«
0.8 t - - - - - t - - - - - - - I
0.8
0.7
4.0
~ 1.21-----~-------I
........
20
I-
0.6 '---_ _ _ _L..-_ _ _ _- - '
-55
25
125
AMBIENT TEMPERATURE (0C)
5-86
/
~ 60
~
j
40
I-
B 20
o
'"
4.0
M
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
Z
c
" --
g
;:: 120
,.$1.4
,.$
cw 1.1
«
a:
Vee = 5.5V
VIN = 5.0V
f=20MHz
0.0
-55
1.3
:2
~ 30
0.8
NORMALIZED tA
vs. SUPPLY VOLTAGE
:J
I"----
a:
0.6 t - - - + - -
.......
---- '"'"
c
w
~ 0.8 t----+----:~+--+----t
«
a:
a:
1.2
/
0.0
/
",
/
/
--
Vee = 5.0V
TA = 25°C
I
1.0
2.0
3.0
OUTPUT VOLTAGE
M
4.0
---"....;~
-='=
CYPRESS
JF
~
CY7C439
SEMICONDUCTOR
1Ypical DC and AC Characteristics (continued)
NORMALIZED tA CHANGE
vs. OUTPUT LOADING
1.3
1.5
1.1
.;!0 1.4
w
:::i
~
a:
0
z
1.2 r- Vee = 5.0V
TA = 25°C
1.0
o
I
J
I
~
200
400
V
0
w 0.9
N
:::i
/
/'
I........
«
V
~
a: 0.7
0
/
600
..,../
..!:?
/
1.3
1.1
()
I
N
«
NORMALIZED Icc
vs. CYCLE FREQUENCY
1.6
z
0.5
Vee = 5.0V
TA = 25°C
0.0
800 1000
10
CAPACITANCE (pF)
20
30
40
CYCLE FREQUENCY (MHz)
Ordering Information
Speed
(ns)
25
30
40
Ordering Code
P21
J65
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
CY7C439-25VC
V21
D22
28-Lead (300-Mil) Molded SOJ
CY7C439-25DC
CY7C439-30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C439-30JC
CY7C439-30VC
J65
V21
32-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded SO
CY7C439-30DC
CY7C439-30DMB
D22
D22
28-Lead (300-Mil) CerDIP
28-Lead (300-Mil) CerDIP
CY7C439- 30LMB
L55
32-PinRectangular Leadless Chip Carrier
CY7C439-40PC
CY7C439-40JC
P21
J65
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
CY7C439-40VC
V21
D22
28-Lead (300-Mil) CerDIP
CY7C439-40DMB
CY7C439-40LMB
65
Package 1Ype
CY7C439-25PC
CY7C439-25JC
CY7C439-40DC
CY7C439 - 65PC
CY7C439-65JC
CY7C439-65VC
CY7C439-65DC
CY7C439-65DMB
CY7C439-65LMB
•
tn
Package
Name
D22
L55
P21
Commercial
28-Lead (300-Mil) CerDIP
Commercial
Military
Commercial
28-Lead (300-Mil) Molded SOJ
Military
28-Lead (300-Mil) CerDIP
32-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
Commercial
J65
V21
32-Lead Plastic Leaded Chip Carrier
D22
D22
28-Lead (300-Mil) CerDIP
L55
Operating
Range
28-Lead (300-Mil) Molded SOJ
28-Lead (300-Mil) CerDIP
Military
32-PinRectangular Leadless Chip Carrier
5-87
ou.
u::
~
~itiPRF.SS
SEMICONDUCTOR
CY7C439
~"
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
VOH
VOL
VIH
VILMax.
IIX
Icc
ISBl
ISB2
los
loz
Subgroups
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Switching Characteristics
tRHF
Subgroups
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
[RAE
':J, lU, 11
Parameters
tRC
tA
tRR
tpR
tLZR
tDVR
tHzR
twc
tpw
tHWZ
tWR
tSD
tHD
tMRSC
tpMR
tRMR
tRPS
tRPBS
tRPBH
tBDH
tBSR
tEFL
tHFH
tBRS
tREF
tRFF
tWEF
tWFF
tWHF
".
tWAF
tWPF
tBSU
tBHL
tBDA
tBDB
tBA
tBHZ
tTSB
tTBS
tTSN
tTSD
tTBN
tTBD
tTPD
tDL
tESD
tEBD
tEDS
tEDB
tBPW
tTSP
tBLZ
tBDV
9,10,11
9,10,11
9,10,11
9,10,11
Q, 10, 11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
Document #: 38-00126-C
................
9,10,11
5-88
CY7C441
CY7C443
Clocked 512 x 9, 2K x 9 FIFOs
Features
Functional Description
• 512 x 9 (CY7C441) and 2,048 x 9
(CY7C443) FIFO buffer memory
• High-speed 70-MHz operation
• Supports free-running 50% duty cycle
clock inputs
• Empty, Almost Empty, and Almost
Full status flags
• Fully asynchronous and simultaneous
read and write operation
• Width expandable
• Independent read and write enable
pins
• Center power and ground pins for
reduced noise
• Available in 300-mil 28-pin DIP,
PLCC, LCC, and SOJ packages
The CY7C441 and CY7C443 are highspeed, low-power, first-in first-out (FIFO)
memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The
CY7C441 has a 512 word by 9 bit memory
array, while the CY7C443 has a 2048 word
by 9 bit memory array. These devices provide solutions for a wide variety of data
buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and
communications buffering.
Both FIFOs have 9-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running clock (CKW) and
a write enable pin (ENW). When ENW is
asserted, data is written into the FIFO on
the rising edge of the CKW signal. While
ENW is held active, data is continually
written into the FIFO on each CKW cycle.
The output port is controlled in a similar
manner by a free-running read clock
(CKR) and a read enable pin (ENR). The
read (CKR) and write (CKW) clocks may
be tied together for single-clock operation
• Proprietary O.8!! CMOS technology
• TTL compatible
• Low power - Icc=70 rnA
or the two clocks may be run independently
for asynchronous read/write applications.
Clock frequencies up to 71.4 MHz are acceptable.
The CY7C441 and CY7C443 clocked
FIFOs provide two status flag pins (F1 and
F2). These flags are decoded to determine
one of four states: Empty, Almost Empty,
Intermediate, and Almost Full (Table 1).
The flags are synchronous, i.e., they change
state relative to either the read clock
(CKR) or the write clock (CKW). The
Empty and Almost Empty states are updated exclusively by the CKR while Almost
Full is updated exclusively by CKW. The
synchronous flag architecture guarantees
that the flags maintain their status for some
minimum time.
The CY7C441 and the CY7C443 use center power and ground for reduced noise.
Both configurations are fabricated using an
advanced 0.8!! N-well CMOS technology.
Input ESD protection is greater than
2001 V, and latch-up is prevented by reliable layout techniques, guard rings, and a
substrate bias generator.
.
Pin Configurations
Logic Block Diagram
PLCC/LCC
Top View
C'rWV
DO-8
D1 D2 D3 NCD4 D5 D6
4 3 2: 1, 32 31 30
Do
ENW
C'rWV
Vee
Vss
F1
F2
F1
F2
NC
00
D7
D8
NC
29
5
28
6
27
7
26
8
7C441
25
9
7C443
24
10
23
11
22
12
21
13
14151617181920
MR
Vss
CKR
ENR
08
07
01 0203 NC 04 0 5 06
C441-2
DIP/SOJ
Top View
-------.I
Ml'!
RESET
~L.._ _L_O_G_IC_....J
D3
D4
D2
D1
D5
Do
ENR
00-8
C441-1
D7
D8
C'rWV
MR
Vss
Vee
Vss
CKR
D6
ENW
F1
CKR
Eiirn
F2
08
00
01
07
06
02
03
05
04
C441-34
5-89
•
U)
ou.
u::
CY7C441
CY7C443
·-.~
~.iJ
CYPRESS
~, SEMICONDUCTOR
Selection Guide
7C441-14
7C443-14
71.4
10
7C441-30
7C443-30
33.3
' 20
30
12
12
12
0
20
I Commercial
10
140
7C441-20
7C443-20
50
15
20
9
9
9
0
15
120
I MilitarylIndustrial
150
130
110
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
14
Minimum Clock HIGH Time (ns)
6.5
Minimum Clock LOW Time (ns)
Minimum Data or Enable Set-Up (ns)
6.5
7
Minimum Data or Enable Hold (ns)
0
Maximum Flag Delay (ns)
Maximum Current (rnA)
100
Maximum Ratings
(Above which the usefullife maybe impaired. Foruserguidelines,
not tested.)
.
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
DC Input Voltage ...................... - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
Military[lj
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Pin Definitions
I/O
Description
Do-s
I
Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge)
writes data (Do - DS) into the FIFO's memory
Oo-s
0
Data Outputs: when the FIFO isnot empty andENRis active, CKR (rising edge)
reads data (00 - Qs) out of the FIFO's memory
ENW
I
Enable Write: enables the CKW input
ENR
I
Enable Read: enables the CKR input
CKW
I
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and
updates the Almost Full flag state
CKR
I
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW and
updates the Almost Empty and Empty flag states
Fl
0
Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in
(see Table 1)
F2
0
Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in
(see Table 1)
MR
I
Master Reset: resets the device to an empty condition
Signal Name
Note:
1.
TA is the "instant on" case temperature.
5-90
CY7C441
CY7C443
'~PRESS
.
- , SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangel 2]
Description
Parameter
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., 10H = - 2.0 rnA
VOL
VIH
Output LOW Voltage
Vee = Min., 10L = 8.0 rnA
VIL
Input LOW Voltage
IIX
Input Leakage
Current
Vee = Max.,
GNDsVIsVee
loS[3]
Output Short
Circuit Current
Vee = Max., VOUT = GND
leel[4]
Operating Current
Vee = Max., lOUT = 0 rnA
Input HIGH Voltage
lee2[5]
Operating Current
ISB[6]
Vee = Max., lOUT = 0 rnA
Standby Current
Vee = Max., lOUT = 0 rnA
7C441-14
7C443-14
Min. Max.
2.4
0.4
2.2
Vee
- 3.0 0.8
-10 +10
7C441-20
7C443-20
Min. Max.
2.4
0.4
2.2
Vee
- 3.0 0.8
-10 +10
7C441-30
7C443-30
Min. Max.
2.4
0.4
2.2
Vee
- 3.0 0.8
-10 +10
Unit
V
V
V
V
- 90
- 90
- 90
rnA
I-tA
Com'l
140
120
100
rnA
Mil/lnd
150
130
110
rnA
Com'l
70
70
70
rnA
Mil/lnd
80
80
80
rnA
Com'l
30
30
30
rnA
Mil/lnd
30
30
30
rnA
Capacitance[7]
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Vee = 5.0V
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Test no more than one output at a time and do not test any output for
more than one second.
4. Input signals switch from OV to 3V with a rise/fall time of 3 ns or less,
clocks and clock enables switch at maximum frequency (fMAX), while
data inputs switch at fMAX/2. Outputs are unloaded.
5.
6.
7.
Max.
10
Unit
pF
Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
All inputs signals are connected to Vee. All outputs are unloaded.
Read and write clocks switch at maximum frequency (fMAX).
Tested initially and after any design or process changes that may affect
these parameters.
AC Test Loads and Waveform[S,9]
R1500Q
OUTP~~31
CL
I
INCLUDING _
JIG AND SCOPE
Equivalent to:
ALL INPUT PULSES
3.0V -----:::Lr-------s,..
GND
R2
333Q
_
C441-5
C441-6
THEVENIN EQUIVALENT
200Q
OUTPUT ().O--....JV..\I\
.. _---oo 2V
5-91
•
fI)
oLL.
u::
CY7C441
CY7C443.
~CYPRESS
~
ill
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel 2,lOj
7C441-14
7C443-14
Parameter
Description
Min.
Max.
7C441-20
7C443-20
Min.
Max.
7C441-30
7C443-30
Min.
Max.
Unit
tCKW
Write Clock Cycle
14
20
30
ns
tCKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
tA[llj
Clock LOW
6.5
9
12
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tpH
Previous Flag Hold After Read/Write HIGH
0
0
0
ns
tSD
Data Set-Up
7
9
12
ns
tHD
Data Hold
0
0
0
ns
tSEN
Enable Set-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
ns
tpD
Flag Delay
tSKEWl[12j
Opposite Clock After Clock
0
0
0
ns
tSKEW2[13j
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width (MR LOW)
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery (MR HIGH Set-Up to First
Enabled Write/Read)
14
20
30
ns
tMRP
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
10
15
10
ns
20
15
20
ns
ns
Notes:
CL = 30 pF for all AC parameters.
All AC measurements are referenced to I.Sy.
10. Test conditions assume signal transition time of3 ns or less, timing reference levels of I.SY, and output loading as shown in the ACTest Loads
and Waveforms and capacitance as in note 6, unless otherwise specified.
11. Access time includes all data outputs switching simultaneously.
12. tSKEWl is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEWl
after the clock, the decision of whether or not to include the opposite
8.
9.
clock in the current clock cycle is arbitrary. Note: The opposite clock
i~ the signal to which a flag is not synchronized; i.e., CKW is the oppoSIte clock for Empty and Almost Empty flags, CKR is the the opposite
clock for !he ~most Ful~ flag. The clock is the signal to which a flag is
synchromzed; I.e., CKW IS the clockforthe Almost Full flag, CKR is the
clock for Empty and Almost Empty flags.
13. tSKEW2 is the minimum time an opposite clock can occur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock oCCurs less than tSKEW2
befor~ the clock, the decision of whether or not to include the opposite
clock In the current clock cycle is abritrary. See Note 12 for definition
of clock and opposite clock.
5-92
aT
CY7C441
CY7C443
:~
~=CYPRESS
~, SEMICONDUCTOR
Switching Waveforms
Write Clock Timing Diagram
CKW
DO - 8
•
U)
o
u.
Read Clock Timing Diagram
u::
CKR
00-8
C441-B
Master Reset Timing Diagram[14,15,16,17]
14------ tpMR
-----~
CKW
CKFi
00-8
ALL DATA
OUTPUTS LOW
VALID DATA
~~Zl
,
40
f-
u
'"'"
w
a:?
:::>
@
S
~
:::>
o
30
20
~
o
o
1
f----
I
~
10.0
~
z
~
..,V
o1/
o
200 400 600 800 1000
CAPACITANCE (pF)
I
I'\.
2
OUTPUT VOLTAGE
3
M
60
40
:::>
a.
"
S
o
4
20
o
J
/
/
--
-
2
3
1
OUTPUT VOLTAGE
5-101
-
/
II
o
----
5.0
TA = 25°C,
Vee=5.0V
z
w
a: 80
a:
V
- r-----
/V
OUTPUT SINK CURRENT vs.
OUTPUT VOLTAGE
f-
~
100
I
L
:..J
1~
1:::
75
I- TA = 25°C
g:20.0
<
~ 15.0
---- ------:::>
10
50
Vee = 5.0V
-
AMBIENT TEMPERATURE (0C)
60
a:
a:
25
TYPICAL tA CHANGE vs.
OUTPUT LOADING
25.0
OUTPUT SOURCE CURRENT vs.
OUTPUT VOLTAGE
«
I
o
30.0
M
Vee = 5.0V
TA=25°C
V'N=3.0V
•
en
oLL.
u:::
NORMALIZED tA vs.
AMBIENT TEMPERATURE
-~
6.0
/
FREQUENCY (MHz)
~ 1.2
«
~
/'fI"
o
w
~
5.5
SUPPLY VOLTAGE
0.5
25
125
AMBIENT TEMPERATURE (0C)
Q
~ 1.0
z
5.0
.s
~
.:J.1.4
~
0.7
«
0.9
0.8
4.5
~
Vee = 5.0V
0.9
o
W
~
1.6
w
N
::J
~ 1.0
V
Q
oC I
.
51.1
Q
/
0.9
a:
0.8
-55
NORMALIZED tA vs.
SUPPLY VOLTAGE
TA
~
M
SUPPLY VOLTAGE
1.2
1.0
~
.2
a:
0.6 ~_-:-'-::__-~------''__--l~
4
4.5
5
5.5
6
oz
Vee=5.0V
V'N=3.0V _
f=50 MHz
Q
W
NORMALIZED SUPPLY
CURRENT vs. FREQUENCY
1.1
M
4
.
CY7C441
CY7C443
~~PRF.SS
_.iF SEMICONDUCTOR
Ordering Information
Speed
(ns)
14
20
30
Ordering Code
Package
Name
Package 1:ype
CY7C441-14PC
P21
28-Lead (300-Mil) Molded DIP
CY7C441-14JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-14VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C441-14DC
D22
28-Lead (300-Mil) CerDIP
CY7C441-14PI
P21
28-Lead (300-Mil) Molded DIP
CY7C441-14JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-14DMB
D22
28-Lead (300-Mil) CerDIP
CY7C441-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C441-14KMB
K74
28-Lead Rectangular Cerpack
CY7C441-20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C441-20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-20VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C441-20DC
D22
28-Lead (300-Mil) CerDIP
CY7C441-20PI
P21
28-Lead (300-Mil) Molded DIP
CY7C441-20JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-20DMB
D22
28"Lead (300-Mil) CerDIP
CY7C441-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C441-20KMB
K74
28-Lead Rectangular Cerpack
CY7C441-30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C441-3OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-30VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C441-30DC
D22
28-Lead (300-Mil) CerDIP
CY7C441-30PI
P21
28-Lead (300-Mil) Molded DIP
CY7C441-30JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C441-30DMB
D22
28-Lead (300-Mil) CerDIP
CY7C441-30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C441-30KMB
K74
28-Lead Rectangular Cerpack
5-102
Operating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
_
CY7C441
CY7C443
-~
.
. • CYPRESS
iF
SEMICONDUCTOR
Ordering Information (continued)
Speed
(ns)
14
20
30
Ordering Code
Package
Name
Package 'JYpe
CY7C443-14PC
P21
28-Lead (300-Mil) Molded DIP
CY7C443-14JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C443-14YC
Y21
28-Lead (300-Mil) Molded SOJ
CY7C443-14DC
D22
28-Lead (300-Mil) CerDIP
CY7C443-14PI
P21
28-Lead (300-Mil) Molded DIP
CY7C443-14JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C443-14DMB
D22
28-Lead (300-Mil) CerDIP
CY7C443-14LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C443-14KMB
K74
28-Lead Rectangular Cerpack
CY7C443 - 20PC
P21
28-Lead (300-Mil) Molded DIP
CY7C443-20JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C443 - 20YC
Y21
28-Lead (300-Mil) Molded SOJ
CY7C443-20DC
D22
28-Lead (300-Mil) CerDIP
CY7C443 - 20PI
P21
28-Lead (300-Mil) Molded DIP
CY7C443 - 20JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C443-20DMB
D22
28-Lead (300-Mil) CerDIP
CY7C443 - 20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
28-Lead Rectangular Cerpack
CY7C443- 20KMB
K74
CY7C443 - 30PC
P21
28-Lead (300-Mil) Molded DIP
CY7C443-3OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C443-30YC
Y21
28-Lead (300-Mil) Molded SOJ
CY7C443 - 30DC
D22
28-Lead (300-Mil) CerDIP
CY7C443-30PI
P21
28-Lead (300-Mil) Molded DIP
CY7C443 - 30JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C443-30DMB
D22
28-Lead (300-Mil) CerDIP
CY7C443 - 30LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C443 - 30KMB
K74
28-Lead Rectangular Cerpack
5-103
Operating
Range
Commercial
Industrial
Military
Commercial
•
U)
Industrial
Military
Commercial
Industrial
Military
oLL.
u::
CY7C441
CY7C443
1.;rlPRRSS
~_, SEMICONDUcrOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3'
1,2,3
1,2,3
1,2,3
VOL
VIH
VIL
IIX
ICCI
ICC2
ISB
los
Switching Characteristics
Parameter
Subgroups
tCKR
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tCKW
tCKH
tCKL
tA
tOH
tFH
tso
tHo
tSEN
tHEN
tHENR
tFO
tSKEWl
tSKEW2
tpMR
tSCMR
tOHMR
tMRR
tMRF
tAMR
Document #: 38-00124-E
5-104
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• 512 x 18 (CY 7C445and CY7C455),
1,024 x 18 (CY7C446 and CY7C456),
2,048 x 18 (CY7C447 and CY7C457)
FIFO butTer memory
• Expandable in width
• CY7C455, CY7C456, and CY7C457
expandable in depth
• High-speed 70-MHz standalone;
50-MHz cascaded
• Supports free-running 50% duty cycle
clock inputs
• Empty, Full, Half Full, and programmable Almost Empty and Almost Full
status flags
• Parity generation/checking
• Fully asynchronous and simultaneous
read and write operation
• Output Enable (OE) pin on CY7C455,
CY7C456, and CY7C457
• Independent read and write enable
pins
• Center power and ground pins for reduced noise
• 52-pin PLCC (CY7C45X) or 48-pin
Logic Block Diagram
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
Cascadable Clocked 512 x 18,
lK x 18, and 2K x 18 FIFOs
with Programmable Flags
trolled by a free-running clock (CKW) and
a write enable pin (ENW).
600-mil DIP (CY7C44X)
• Proprietary 0.8fl CMOS technology
• TTL compatible
Functional Description
The CY7C445, CY7C446, CY7C447,
CY7C455, CY7C456, and CY7C457 are
high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and
write interfaces. All are 18 bits wide. The
CY7C445 and CY7C455 have a 512-word
memory array, the CY7C446 and
CY7C456 have a 1,024-word memory
array, and the CY7C447 and CY7C457
have a 2,048-word memory array. The
CY7C455, CY7C456, and CY7C457 can
be cascaded to increase FIFO depth. Programmable features include Almost Full/
Empty flags and generation/checking of parity. These FIFOs provide solutions for a
wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications
buffering.
These FIFOs have 18-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is con-
DO-17
When ENW is asserted, data is written
into the FIFO on the rising edge of the
CKW signal. While ENW is held active,
data is continually written into the FIFO
on each CKW cycle. The output port is
controlled in a similar manner by a freerunning read clock (CKR) and a read enable pin (ENR).
In addition, the
CY7C455, CY7C456, and CY7C457 have
an output enable pin (OE). The read
(CKR) and write (CKW) clocks may be
tied together for single-clock operation or
the two clocks may be run independently
for asynchronous read/write applications.
Clock frequencies up to 71.4 MHz are
achievable in the standalone configuration, and up to 50 MHz is achievable when
FIFOs are cascaded for depth expansion.
Depth expansion is possible usinB...!!!e cascade input (-'0., cascade ou~t (XO), and
First Load (Fl::) pins. The XO pin is connected to the XI pin of the next device, and
the XO pin of the last device should be
connected to the XI pin of the first device.
The FL pin of the first device is tied to V ss.
Pin Configurations
48-PinDIP
Top View
CIWV
Ef\IW
HF
CIWV
ElF
J5AFE
Ef\IW
00
01
02
03
04
RF
E'IF
,"--_-.-_.....f'-J5AFE/XO
05
06
07
D10
D11
011
D12
D1S
D14
D15
017/PG 2/PE2
EfifF!
5-105
De
09
010
016
c445-1
D7
Vss
Vee
015
EfifF!
D5
D6
OalPG1f15E1
Vss
Vss
012
013
014
CKR
Do
D1
D2
Ds
D4
D9
D16
D17
MR
CKR
c445-2
•
en
oLL.
u:::
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
~
. JF:rtPRESS
~
PRELIMINARY
SEMICONDUCTOR
Pin Configurations (continued)
LCC/PLCC
Top View
g
(flOO
O
.....
C\J
82'i8l3b~g:'~~1Hi 00
7 6 5 4 3 2 '1' 52 51 50 49 48 47
02
01
DO
013
014
015
016
017
10
Xi 11
EfJW
CI2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Industrial
- 40°C to +85°C
5V ± 10%
Military[2]
- 55°C to +125°C
5V ± 10%
Range
Commercial
Pin Definitions
Signal Name
DO-17
I/O
Description
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do -17) into the
FIFO's memory. IfMR is asserted at the rising edge of CKw, data is written into the FIFO's programming register. Ds, 17 are ignored if the device is configured for parity generation.
QO-7
Q9 -16
0
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Qo - 7, Q9 - 16)
out of the FIFO's memory. If MR is active at the rising edge of CKR, data is read from the programming
register.
Qg/PGl/PR
Q17/PG2/PE2
0
Function varies according to mode:
Parity disabled - same function as Qo - 7 and Q9 - 16
Parity enabled, generation - parity generation bit (PGx)
Parity enabled, check - Parity Error Flag (PEx)
ENW
I
Enable Write: Enables the CKW input (for both non-program and program modes).
ENR
I
Enable Read: Enables the CKR input (for both non-program and program modes).
CKW
I
Write Clock: The risin~e clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and
Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: The rising e~locks data out of the FIFO when ENR is LOW; updates the Empty and Almost
Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
0
Half Full Flag: Synchronized to CKW.
ElF
0
Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKw.
PAFE/XO
0
Dual-Mode Pin:
Not Cascaded - programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR.
Cascaded - expansion out signal, connected to XI of next device.
XI
I
Expansion-In Pin-=-Not Cascaded - XI is tied to Vss.
Cascaded - expansion Input, connected to XO of previous device.
FL
I
First Load Pin:
Cascaded - the first device in the daisy chain will have FL tied to V ss; all other devices will have FL tied to Vee
(Figure 1).
Not Cascaded - tied to Vee.
MR
I
__
Master Reset: Resets device to empty condition.
Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at 16 or
less locations from Full/Empty.
Programming Mode: Data present on Do _ s is written into the programmable register on the rising edge of
CKW. Program register contents appear on Qo _ S after the rising edge of CKR.
OE
I
Output Enable for Qo - 7, Q9 - 16, Qg/PGl/PEl and Q17/PG2/PE2 pins.
Note:
2. TA is the "instant on" case temperature.
5-107
•
en
ou..
ii:
:"Jz~
~...
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
PRELIMINARY
SEMICONDUCTOR
Electrical Characteristics Over the Operating Rangel3]
Parameter
Description
7C44X-14
7C45X-14
Min. Max.
Test Conditions
= Min., 10H = - 2.0 rnA
Vee = Min., 10L = 8.0 rnA
7C44X-20
7C45X-20
Min. Max.
2.4
VOH
Output HIGH Voltage Vee
2.4
VOL
VIH[4]
Output LOW Voltage
Input HIGH Voltage
2.2
VIL[4]
Input LOW Voltage
- 3.0
Vee
0.8
IIX
Input Leakage
Current
Vee = Max.
-10
+10
los[5]
Output Short
Circuit Current
Vee
10ZL
10ZH
led6]
Output OFF, High Z
Current
OE~ VIH,
Operating Current
Vee = Max., lOUT
0.4
= Max., VOUT = GND
-10
Vss < Vo < Vee
= 0 rnA ICom'l
1Mil/lnd
0.4
2.2
- 3.0
-10
+10
-10
2.2
Unit
V
2.4
0.4
V
Vee
0.8
Vee
0.8
V
- 3.0
+10
-10
+10
itA
- 90
- 90
7C44X-30
7C45X-30
Min. Max.
- 90
+ 10
-10
V
rnA
+10
ItA
160
140
120
rnA
180
160
140
rnA
Capacitance[7]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
= 1 MHz,
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms[8, 9, 10, 11, 12]
R1500Q
ALL INPUT PULSES
OUTP~~j1
Cl
I
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V ---~----~~
90%
GND
R2
333Q
_
c445-4
c445-5
THEVENIN EQUIVALENT
200Q
OUTPUT OoO---A;YI/\.·_ _--oo 2V
Notes:
3.
See the last page of this specification for Group A subgroup testing information.
4. The Ym and VIL specifications apply for all inputs exc~XI and FL.
The XI pin is not a TIL input. It is connected to either XO of the previous device or Vss. FL must be connected to either V ss or Vee.
5. Test no more than one output at a time for not more than one second.
6. Input signals switch from OV to 3V with a rise/fall time of less than 3
ns, clocks and clock enables switch at maximum frequency (fMAX),
while data inputs switch at fMAXl2. Outputs are unloaded.
7.
Tested initially and after any design or process changes that may affect
these parameters.
8. CL = 30 pF for all AC parameters except for tOHZ.
9. CL = 5 pF for tOHZ.
10. All AC measurements are referenced to 1.5V except tOE, tOLZ, and
tOHZ·
11. tOE and tOLZ are measured at ± 100 mV from the steady state.
12. tOHZ is measured at +500 mV from VOL and - 500 mV from VOH.
5-108
~
•
,
i~PRFSS
SEMICONDUCTOR
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
PRELIMINARY
Switching Characteristics Over the Operating Rangel3, 13]
Parameter
Description
7C44X-14
7C45X-14
7C44X-20
7C45X-20
7C44X-30
7C45X-30
Min.
Min.
Min.
Max.
Max.
Max.
Unit
tCKW
Write Clock Cycle
14
20
30
ns
tCIm
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
Clock LOW
6.5
9
12
tA
Data Access Time
tOH
Previous Output Data Hold After Read HIGH
0
0
0
tpH
Previous Flag Hold After ReadlWrite HIGH
0
0
0
ns
tso
Data Set-Up
5
7
9
ns
ns
15
10
ns
20
ns
ns
tHO
Data Hold
1
1
1
tSEN
Enable Set-Up
5
7
9
ns
tHEN
Enable Hold
1
1
1
ns
tOE
tOLZ[7,14]
OE LOW to Output Data Valid
tOHZ[7,14]
OE HIGH to Output Data in High Z
10
15
20
ns
tpG
Read HIGH to Parity Generation
10
15
20
ns
tpE
Read HIGH to Parity Error Flag
10
15
20
ns
tpo
Flag Delay
10
15
20
ns
10
OE LOW to Output Data in Low Z
0
20
15
0
0
ns
ns
tSKEW1[15]
Opposite Clock After Clock
0
0
0
ns
tSKEW2[16]
Opposite Clock Before Clock
14
20
30
ns
tpMR
Master Reset Pulse Width (MR LOW)
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery
(MR HIGH Set-Up to First Enabled Write/Read)
14
20
30
ns
tMRP
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
tSMRP
Program Mode-MR LOW Set-Up
14
20
30
ns
tHMRP
Program Mode-MR LOW Hold
10
15
20
ns
tFfP
Program Mode-Write HIGH to Read HIGH
14
tAP
Program Mode-Data Access Time
tOHP
Program Mode-Data Hold Time from MR HIGH
20
14
0
30
20
0
ns
30
0
ns
ns
Notes:
13. Test conditions assume signal transition time of3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads
and Waveforms and capacitance as in notes 5 and 9, unless otherwise
specified.
14. At any given temperature and voltage condition, tOLZ is greater than
tOHZ for any given device.
15. tSKEWl is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEWl
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock is
the signal to which a flag is not synchronized; i.e., CKW is the opposite
clock for Empty and Almost Empty flags, and CKR is the the opposite
clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Half
Full, Almost Full, and Full flags, and CKR is the clock for Empty and
Almost Empty flags.
16. tSKEW2 is the minimum time an opposite clock can occur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. See Note 15 for definition
of clock and opposite clock.
5-109
•
g :;~PRFSS
PRELIMINARY
CY7C445/CY7C455
CY7C446/CY7C4S6
CY7C447/CY7C4S7
_" SEMICONDUcrOR
Switching Waveforms
Write Clock Timing Diagram
CtO (Le., PAFE does not
transition at Empty or Full).
23. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after
empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still
appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
24. CKR is clock and CKW is opposite clock.
25. R3 updates the flag to the Empty state by asserting ElF. Because WI
occurs greater than tSKEWl after R3, R3 does not recognize WI when
updating flag status. But because WI occurs tSKEW2 before R4, R4 includes WI in the flag update and, therefore, updates FIFO to Almost
Empty state. It is important to note that R4 is a late~e; Le., it only
updates the flag status regardless of the state of ENR. It does not
change the count or the FIFO's data outputs.
5-112
~
:~
-.
-=-
PRELIMINARY
~=CYPRESS
iF
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
SEMICONDUCTOR
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[21, 24, 26]
COUNT
17
16
17
16
17
18
15
CKR
CKW
•
HIGH
U)
oLa.
i!
HIGH
---t-"1
c445-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle with Free-Running Clocks[21, 24, 26, 27, 28]
18 (no change)
COUNT
17
17
16
FLAG UPDATE CYCLE
18
17
16
15
CKR
ENR
CKW
ENW
HF
HIGH
ElF
HIGH
PAFE
Im1
c445-13
Notes:
26. The FIFO in this example is assumed to be programmed to its default
flag values. Almost Empty is 16 words from Empty; Almost Full is 16
locations from Full.
27. R4 only updates the flag status. It does not affect the count because
ENRisHIGH.
28. When making the transition from Almost Empty to Intermediate, the
count must increase by two (16 .18; two enabled writes: W2, W3) before a read (R4) can update flags to the Less Than Half Full state.
5:-113
~~
~.CYPRESS
~, SEMICONDUCTOR
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
PRELIMINARY
Switching Waveforms (continued)
Write to Half Full Timing Diagram with Free-Running Clocks[21, 29, 30, 31]
1024
COUNT
f~~~l
1024
1025
1023
f~~~l
f~~~l
1024
f~~~l
1025
f~~~l
1026
f~~~l
f~~~l
Ct
CKR
8 LSBs OF
WORDM+2
c445-23
Output Enable Timing[41, 42]
CKR
--------------~/
READ M+1
LOW
QO- 17
VALID DATA
WORDM
,,-----------VALID DATA
WORDM+1
c445-24
Notes:
40. In this example, the FIFO is assumed to be programmed to check for
even parity. The QO-7 word is shown_
41. This example assumes that the time from the CKR rising edge to valid
word M + 1 ~ tAo The QO-7 word is shown.
42. IfENR was HIGH around the rising edge of CKR (Le., read disabled),
the valid data at the far right would once again be word M instead of
wordM+l.
5-118
L,j:~
___
PRELIMINARY
SEMICONDUCTOR
Architecture
The CY7C44X and CY7C45X consist of an array of 512,1024, or
2,048 words of 18 bits each (implemented by a dual-port array of
SRAMCells),areadPointer,awritepOinter,con.!!~s5·
nals(CKR,
CKW, ENR, ENW, and MR), and flags HF
1
1
0
494
1006
2030
>HF
1
1
0
495
1007
2031
Current State
of FIFO
AF
"EfF
Number of
Words in FIFO
7C446
1008
Number of
Words in FIFO
7C447
2032
Operation
Read
(ENR = 0)
Read
(ENR = 0)
Write
(ENW = 1)
Write
(ENW=O)
Write
(ENW =0)
II
Status After Operation
Next State of
FIFO
AF
AF
>HF
>HF
AF
"EfF
PAFE
1
1
1
0
0
1
HF
0
0
0
1
1
1
0
0
0
Number of
Words in FIFO
7C445
495
494
494
Number of
Words in FIFO
7C446
1007
1006
1006
Number of
Words in FIFO
7C447
2031
2030
2030
495
496
1007
1008
2031
2032
Table 5. Programmable Parity Options
D17
0
1
1
1
1
D16
X
0
0
1
1
D15
X
0
1
0
1
Condition
Parity disabled.
Generate even parity on PG output pin.
Generate odd parity on PG output pin.
Check for even parity. Indicate error on PE output pin.
Check for odd parity. Indicate error on PE output pin.
Note:
47. Default condition or programmed so that Almost Full becomes active
when the FIFO contains 16 or less empty locations.
5-123
en
Comments
Read
Read
Flag Update
Write
Write (transition from
>HF to AF)
oL&.
ii:
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
~
~PRESS
~J,. SElvfICONDUcrOR
PRELIMINARY
Ordering Information
Speed
(ns)
14
20
30
Ordering Code
14
20
30
14
20
30
Operating
Range
Commercial
D26
48-Lead (600-Mil) Sidebraze DIP
CY7C445-14PC
P25
48-Lead (600-Mil) Molded DIP
CY7C445-14PI
P25
48-Lead (600-Mil) Molded DIP
CY7C445~ 14DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C445 - 20DC
D26
48-Lead (600-Mil) Sidebraze DIP
Commercial
CY7C445 - 20PC
P25
48-Lead (600-Mil) Molded DIP
CY7C445-20PI
P25
48-Lead (600-Mil) Molded DIP
CY7C445-20DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C445-30DC
D26
48-Lead (600-Mil) Sidebraze DIP
Commercial
CY7C445-30PC
P25
48-Lead (600-Mil) Molded DIP
CY7C445 - 30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C445 - 30DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Ordering Code
Package
Name
Package 1YPe
Industrial
Industrial
Operating
Range
Commercial
CY7C446-14DC
D26
48-Lead (600-Mil) Sidebraze DIP
CY7C446-14PC
P25
48-Lead (600-Mil) Molded DIP
CY7C446-14PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C446-14DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C446-20DC
D26
48-Lead (600-Mil) Sidebraze DIP
Commercial
CY7C446-20PC
P25
48-Lead (600-Mil) Molded DIP
CY7C446-20PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C446-20DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C446-30DC
D26
48-Lead (600-Mil) Sidebraze DIP
Commercial
CY7C446-30PC
P25
48-Lead (600-Mil) Molded DIP
CY7C446-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C446-30DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
Speed
(ns)
Package 1YPe
CY7C445-14DC
Speed
(ns)
Package
Name
Ordering Code
Package
Name
Package 1YPe
Operating
Range
Commercial
CY7C447 -14DC
D26
48-Lead (600-Mil) Sidebraze DIP
CY7C447-14PC
P25
48-Lead (600-Mil) Molded DIP
CY7C447-14PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C447-14DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C447-20DC
D26
48-Lead (600-Mil) Sidebraze DIP
Commercial
CY7C447-20PC
P25
48-Lead (600-Mil) Molded DIP
CY7C447-20PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C447-20DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C447 - 30DC
D26
48-Lead (600-Mil) Sidebraze DIP
Commercial
CY7C447-30PC
P25
48-Lead (600-Mil) Molded DIP
CY7C447 - 30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C447-30DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
5-124
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
PRELIMINARY
Ordering Information (continued)
Speed
(ns)
14
20
30
Speed
(ns)
14
20
30
Speed
(ns)
14
20
30
Ordering Code
Package
Name
Package
'JYpe
Operating
Range
CY7C455-14JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C455 -1411
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C455-14LMB
L69
52-Square Leadless Chip Carrier
CY7C455-2OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C455 - 2011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C455 - 20LMB
L69
52-Square Leadless Chip Carrier
CY7C455-30JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C455 - 3011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C455 - 30LMB
L69
52-Square Leadless Chip Carrier
Ordering Code
Package
Name
Package
'JYpe
Military
Military
Military
Operating
Range
CY7C456-14JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C456-1411
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C456-14LMB
L69
52-Square Leadless Chip Carrier
CY7C456-2OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
52-Lead Plastic Leaded Chip Carrier Industrial
Military
CY7C456-201l
J69
CY7C456-20LMB
L69
52-Square Leadless Chip Carrier
CY7C456-3OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C456-301l
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C456- 30LMB
L69
52-Square Leadless Chip Carrier
Ordering Code
Package
Name
Package
'JYpe
Military
Military
Operating
Range
CY7C457-14JC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C457-14LC
L69
52-Square Leadless Chip Carrier
CY7C457 -1411
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C457-14LMB
L69
52-Square Leadless Chip Carrier
CY7C457-2OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C457 - 2011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C457 - 20LMB
L69
52-Square Leadless Chip Carrier
CY7C457-3OJC
J69
52-Lead Plastic Leaded Chip Carrier Commercial
CY7C457 - 3011
J69
52-Lead Plastic Leaded Chip Carrier Industrial
CY7C457 - 30LMB
L69
52-Square Leadless Chip Carrier
5-125
Military
Military
Military
•
~
~~
==tiJiI/IIIIiIIi
CYPRESS
~, SEMICONDUCTOR
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
VOL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
VIH
VIL
IIX
Icc
los
Ioz
Switching Characteristics
Parameters
Subgroups
tCKW
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
tCKR
tCKH
tCKL
tA
tOH
tFH
tSD
tHD
tSEN
tHEN
tOE
tpG
tpE
tFD
tSKEWl
tSKEW2
tpMR
tSCMR
tOHMR
tMRR
tMRF
tAMR
tSMRP
tHMRP
tFfP
tAP
tOHP
Document #: 38-00211-A
5-126
CY7C445/CY7C455
CY7C446/CY7C456
CY7C447/CY7C457
CY7C451
CY7C453
CYPRESS
SEMICONDUCTOR
Cascadable Clocked 512 x 9
and Cascadable Clocked 2K x 9
FIFOs with Programmable Flags
Features
Functional Description
• 512 x 9 (CY7C451) and 2,048 x 9
(CY7C453) FIFO buffer memory
• Expandable in width and depth
• High-speed 70-MHz standalone;
50-MHz cascaded
• Supports free-running 50% duty cycle
clock inputs
• Empty, Almost Empty, Half Full,
Almost Full, and Full status flags
• Programmable Almost Full/Empty
flags
• Parity generation/checking
• Fully asynchronous and simultaneous
read and write operation
• Output Enable (OE)
• Independent read and write enable
pins
• Center power and ground pins for reduced noise
• Available in 300-mil 32-pin DIP,
PLCC, and LCC packages
• Proprietary 0.8!l CMOS technology
• Lowpower
-Icc=70mA
The CY7C451 and CY7C453 are highspeed, low-power, first-in first-out (FIFO)
memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The
CY7C451 has a 512-word by 9-bit memory
array, while the CY7C453 has a
2,048-word by 9-bit memory array. Devices can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Empty flags and generation!
checking of parity. These FIFOs provide solutions for a wide variety of data buffering
needs, including high-speed data acquisition, mUltiprocessor interfaces, and communications buffering.
Both FIFOs have 9-bit input and output
ports that are controlled by separate clock
and enable signals. The input port is controlled by a free-running clock (CKW) and
a write enable pin (ENW). When ENW is
asserted, data is written into the FIFO on
the rising edge of the CKW signal. While
ENW is held active, data is continually
written into the FIFO on each CKW cycle.
The output port is controlled in a similar
Logic Block Diagram
manner by a free-running read clock
(CKR) and a read enable pin (ENR). The
read (CKR) and write (CKW) clocks may
be tied together for single-clock operation
or the two clocks may be run independently
for asynchronous read/write applications.
Clock frequencies up to 71.4 MHz are acceptable in the standalone configuration,
and up to 50 MHz is acceptable when FIFOs are cascaded for depth expansion.
Depth expansion is possible using the cascadeJ!!put (XI) and cascade output (XO).
The XO signal is connected to the XI of the
next device, and the XO of the last device
should be connected to the XI of the first
device. In standalone mode, the input (XI)
pin is simply tied to Vss.
The CY7C451 and CY7C453 provide three
status pins to the user. These pins are decoded to detennine one of six states: Empty,
Almost Empty, Less than or Equal to Half
Full, Greater than Half Full, Almost Full,
and Full (see Table 1). The Almost Empty/
Full flag (PAFE) and XO functions share
the same pin. The Almost EmptyIFull flag is
valid in the standalone and width
Pin Configurations
Do -8
PLCC/LCC
Top View
Do 0, 02 0 3 0 4 05 0 6
Xl
ENW
07
08
5
6
CKW
7
Vee
8
7C451
9
7C453
10
11
12
13
14151617 181920
Vss
RF
ElF
l'AFEiXO
00
A:
MR
Vss
CKR
ENF!
OE
OalPG/PE
RF
C451-2
Elf
L...-_-r-_...r-t~
J5AItiXO
03
04
O2
Os
06
07
01
Do
Xl
M"R--1 RESET
A: --I. . ._L_O_G_IC_.....
ENW
CKW
MR
Vee
Vss
Vss
RF
ElF
PAFEiXO
0 0 - 7. OalPG/PE
00
01
CKR
C451-1
5-127
08
A:
O2
03
CKR
ENF!
OE
OalPG!PE
07
06
Os
04
C451-3
•
CY7C451
CY7C453
~
~~PRESS
~_,. SEMICONDUCTOR
Functional Description (continued)
expansion configurations. In the depth expansion, this pin provides the expansion out (XO) information that is used to signal the
next FIFO when it will be activated.
The flags are synchronous, i.e., they change state relative to either
the read clock (CKR) or the write clock (CKW). When entering or
exiting the Empty and Almost Empty states, the flags are updated
exclusively by the CKR. The flags denoting Half Full, Almost Full,
and Full states are updated exclusively by CKW The synchronous
flag architecture guarantees that the flags maintain their status for
some minimum time.
The CY7C451 and the CY7C453 use center power and ground for
reduced noise. Both configurations are fabricated using an advanced 0.8"" N-well CMOS technology. Input ESD protection is
greater than 2001 V, and latch-up is prevented by the use of reliable
layout techniques, guard rings, and a substrate bias generator.
Selection Guide
7C451-14
7C453-14
7C451-20
7C453-20
7C451-30
7C453-30
Maximum Frequency (MHz)
71.4[1]
50
33.3
Maximum Cascadable Frequency
N/A[2]
50
33.3
Maximum Access Time (ns)
10
15
20
Minimum Cycle Time (ns)
14
20
30
Minimum Clock HIGH Time (ns)
6.5
9
12
Minimum Clock LOW Time (ns)
6.5
9
12
Minimum Data or Enable Set-Up (ns)
7
9
12
Minimum Data or Enable Hold (ns)
0
0
0
Maximum Flag Delay (ns)
10
15
20
140
120
100
150
130
110
Maximum Current (rnA)
I Commercial
1 Military/Industrial
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Thmperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55°C to +125°C
Supply Voltage to Ground Potential. . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . .. - 3.0V to + 7.0V
Output Current into Outputs (LOW) .............. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
Operating Range
Range
Commercial
Industrial
Military[3]
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Notes:
1. 71.4-MHz operation is available only in the standalone configuration.
2. The -14 device cannot be cascaded.
3.
5-128
TA is the "instant on" case temperature.
CY7C451
CY7C453
.:iiSP
~~
-=-,
~i!CYPRESS
SEMICONDUCTOR
Pin Definitions
I/O
Description
Do-s
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (Do _ s) into the
FIFO's memory. IfMR is asserted at the rising edge ofCKW then data is written into the FIFO's programming
register. Ds is ignored if the device is configured for parity generation.
00-7
0
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (00 _ 7) out ofthe
FIFO's memory. If MR is active at the rising edge of CKR then data is read from the programming register.
Og/PGJPE
0
Function varies according to mode:
Parity disabled - same function as Qo - 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Flag (PE)
ENW
I
Enable Write: enables the CKW input (for both non-program and program modes)
ENR
I
Enable Read: enables the CKR input (for both non-program and program modes)
CKW
I
Write Clock: the rising ~e clocks data into the FIFO when ENW is LOW; updates Half Full, Almost Full, and
Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: the rising ed~locks data out of the FIFO when ENR is LOW; updates the Empty and Almost
Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
0
Half Full Flag - synchronized to CKW.
Signal Name
ElF
0
Empty or Full Flag - E is synchronized to CKR; F is synchronized to CKW
PAFE/XO
0
Dual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
XI
I
Not Cascaded - XI is tied to Vss
Cascaded - Expansion Input, connected to XO of previous device
FL
I
First Load Pin:
Cascaded - the first device in the daisy chain will have FL tied to V ss; all other devices will have FL tied to Vee
(Figure2)
Not Cascaded - tied to Vee
MR
I
Master Reset: resets device to empty condition.
__
Non-Programming Mode: program register is reset to default condition of no parity andPAFE active at 16 or
less locations from Full/Empty.
Programming Mode: Data present on Do _ s is written into the programmable register on the rising edge of
CKW. Program register contents appear on 00 _ S after the rising edge of CKR.
OE
I
Output Enable for 00 - 7 and Og/PGJPE pins
5-129
•
CY7C451
CY7C453
§i ;IF·riPRFSS
~
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range[4]
Parameter
Description
7C451-14
7C453-14
Min. Max.
Test Conditions
VOH
Output HIGH Voltage Vee = Min., lOR = ..... 2.0 rnA
VOL
VIR[S]
Output LOW Voltage
Input HIGH Voltage
VrL[5]
Input LOW Voltage
Irx
Input Leakage
Current
Vee = Max.
loS[6]
Output Short
Circuit Current
Vee = Max., VOUT = GND
- 90
10ZL
10ZH
Icel[7]
Output OFF, High Z OE~ VIR, Vss < Va < Vee
Current
Operating Current
Ice2[8]
Operating Current
Standby Current
ISB[9]
2.4
7C451-20
7C453-20
Min. Max.
2.2
2.4
2.4
0.4
Vee = Min., IOL = 8.0 rnA
0.4
2.2
- 3.0
Vee
0.8
- 3.0
yee
0.8
-10
+10
-10
+10
-10
- 90
+10
7C451-30
7C453-30
Min. Max.
-10
2.2
- 3.0
-10
V
0.4
V
Vee
0.8
V
+10
JJA
-10
V
rnA
- 90
+10
Unit
+10
JJA
Vee = Max., lOUT = 0 rnA Com'l
MillInd
140
120
100
rnA
ISO
130
110
rnA
Vee = Max., lOUT = 0 rnA Com'l
MillInd
Vee = Max., lOUT = 0 rnA Com'l
70
70
70
rnA
80
80
80
rnA
30
30
30
rnA
MillInd
30
30
30
rnA
Capacitance[lO]
Parameter
CrN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA= 25°C, f = 1 MHz,
Vee = S.OV
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms[ll, 12, 13, 14, 15]
R1500Q
ALL INPUT PULSES
OUTP~~31
CLI
INCLUDING _
JIG AND SCOPE
Equivalent to:
3.0V ----::u----~:!IL
90%
GND
R2
333Q
_
C451-4
C451-5
THEVENIN EQUIVALENT
200Q
OUTPUT~o----~~~~__--~o2V
Notes:
4. See the last page of this specification for Group A subgroup testing information.
5. The Yrn and VIL specifications apply for all inputs exc~XI and FL.
The XI pin is not a TIL input. It is connected to either XO ofthe previous device or V ss. FL must be connected to either V ss or Vee.
6. Test no more than one output at a time for not more than one second.
7. Input signals switch from OV to 3V with a rise/fall time of 3 ns or less,
clocks and clock enables switch at maximum frequency (fMAX), while
data inputs switch at fMAX/2. Outputs are unloaded.
8. Input signals switch from OV to 3V with a rise/fall time less than 3 ns,
clocks and clock enables switch at 20 MHz, while the data inputs switch
at 10 MHz. Outputs are unloaded.
9.
10.
11.
12.
13.
14.
15.
5-130
All inputs signals are connected to Vee. All outputs are unloaded.
Read and write clocks switch at maximum frequency (fMAX).
Tested initially and after any design or process changes that may affect
these parameters.
CL = 30 pF for all AC parameters except for tOHZ.
CL = 5 pF for tOHZ.
All AC measurements are referenced to 1.SV except tOE, tOLZ, and
tOHZ'
tOE and tOLZ are measured at ± 100 mV from the steady state.
tOHZ is measured at +500 m V from VOL and - 500 m V from VOH.
i
_
CY7C451
CY7C453
·~PRFSS
SEMICONDUCTOR
JF
Switching Characteristics Over the Operating Range[2, 16]
Parameter
Description
7C451-14
7C453-14
7C451-20
7C453-20
7C451-30
7C453-30
Min.
Min.
Min.
Max.
Max.
Max.
Unit
tCKw
Write Clock Cycle
14
20
30
tCKR
Read Clock Cycle
14
20
30
ns
tCKH
Clock HIGH
6.5
9
12
ns
tCKL
tA[17]
Clock LOW
6.5
Data Access Time
toH
Previous Output Data Hold After Read HIGH
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH
0
0
0
ns
9
10
ns
12
15
ns
20
ns
tso
Data Set-Up
7
9
12
ns
tHO
Data Hold
0
0
0
ns
tSEN
Enable Set-Up
7
9
12
ns
tHEN
Enable Hold
0
0
0
ns
tOE
tOLZ[6]
OE LOW to Output Data Valid
10
OE LOW to Output Data in Low Z
0
15
0
20
0
ns
ns
tOHZ[6]
OE HIGH to Output Data in High Z
10
15
20
tpG
Read HIGH to Parity Generation
10
15
20
ns
tPE
Read HIGH to Parity Error Flag
10
15
20
ns
tFO
tSKEWl[18]
Opposite Clock After Clock
tSKEW2[19]
tpMR
Flag Delay
10
15
20
0
ns
ns
0
0
Opposite Clock Before Clock
14
20
30
ns
Master Reset Pulse Width (MR LOW)
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
ns
tMRR
Master Reset Recovery
(MR HIGH Set-Up to First Enabled Write/Read)
14
20
30
ns
tMRF
MR HIGH to Flags Valid
14
20
30
ns
tAMR
MR HIGH to Data Outputs LOW
14
20
30
ns
ns
tSMRP
Program Mode-MR LOW Set-Up
14
20
30
ns
tHMRP
Program Mode-MR LOW Hold
10
15
25
ns
tFTP
Program Mode-Write HIGH to Read HIGH
14
tAP
Program Mode-Data Access Time
tOHP
Notes:
20
14
Program Mode-Data Hold Time from MR HIGH
16. Test conditions assume signal transition time of3 ns or less, timing reference levels of l.Sv, and output loading as shown in AC Test Loads
and Waveforms and capacitance as in notes 6 and 12, unless otherwise
specified.
17. Access time includes all data outputs switching simultaneously.
18. tSKEWl is the minimum time an opposite clock can occur after a clock
and still be guaranteed not to be included in the current clock cycle (for
purposes of flag update ).If the opposite clock occurs less than tSKEWl
after the clock, the decision of whether or not to include the opposite
clock in the current clock cycle is arbitrary. Note: The opposite clock is
the signal to which a flag is not synchronized; i.e., CKW is the opposite
0
30
20
0
ns
30
0
ns
ns
clock for Empty and Almost Empty flags, CKR is the the opposite clock
for the Almost Full, Half Full, and Full flags. The clock is the signal to
which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost
Empty flags.
19. tSKEW2 is the minimum time an opposite clock can occur before a clock
and still be guaranteed to be included in the current clock cycle (for
purposes of flag update). If the opposite clock occurs less than tSKEW2
before the clock, the decision ofwhether or not to include the opposite
clock in the current clock cycle is arbitrary. See Note 18 for definition
of clock and opposite clock.
5-131
•
In
o
u.
u::
CY7C451
CY7C453
;;~PRF$
~
SEMICONDUCTOR
Switching Waveforms
Write Clock Timing Diagram
CKW
Do -
8
Read Clock Timing Diagram
CKR
00 - 8
ElF. PAFE
*'"---
tFD ---~
C451-7
Master Reset (Default with Free-Running Clocks) Timing Diagram[20, 21, 22, 23)
__________________~
~------ tpMR --------~ ~---------------------------
CKW
CKR
00-8
ALL DATA
OUTPUTS LOW
VALID DATA
HF
C451-B
5-132
CY7C451
CY7C453
~
.
~~PRESS
_ , SEMICONDUcrOR
Switching Waveforms (continued)
Master Reset (Programming Mode) Timing Diagram[22, 23]
CKW
DO- 8
•
CKR
en
ou.
LOW
ii:
00-8
ALL DATA
OUTPUTS LOW
VALID DATA
C451-9
Master Reset (Programming Mode with Free-Running Clocks) Timing Diagram[22, 23]
tHMRP
MR
CKW
ENW
DO-8
CKR
ENR
ALL DATA
OUTPUTS LOW
00-8
C451-10
Notes:
20. To only perform reset (no programming), the following criteria must
be met: ENW or CKW must be inactive while MR is LOW.
21. To only ~rm reset (no programming), the following criteria must
be met: ENR or CKR must be inactive while MR is LOW.
22. All data outputs (Qo _ 8) go LOW as a result ofthe rising edge of MR
aftertAMR·
23. In this example, Qo - 8 will remain valid until tOHMR if either the first
read shown did not occur or if the read occurred soon enough such that
the valid data was caused by it.
5-133
CY7C451
CY7C453
.g: :~~PRFSS
_ , SEMICONDUCTOR
Switching Waveforms (continued)
Read to Empty Timing Diagram[24, 27, 28)
1 (NO CHANGE)
COUNT
LATENT CYCLE
CKR
CtO(Le.,PAFEdoesnot
transition at Empty or Full).
26. R2 is ignored because the FIFO is empty (count = 0). It is important
to note that R3 is also ignored because W3, the first enabled write after
empty, occurs less than tSKEW2 before R3. Therefore, the FIFO still
appears empty when R3 occurs. Because W3 occurs greater than
tSKEW2 before R4, R4 includes W3 in the flag update.
27. CKR is clock; CKW is opposite clock.
28'. R3 updates the flag to the Empty state by asserting ElF. Because WI
occurs greater than tSKEWl after R3, R3 does not recogni2e WI when
updating flag status. But because WI occurs greater than tSKEW2 before R4, R4 includes WI in the flag update and, therefore, updates
FIFO to Almost Empty state. It is important to note that R4 is a latent
cycle; i.e., it only updates the flag status regardless ofthe state ofENR.
It does not change the count or the FIFO's data outputs.
5-134
CY7C451
CY7C453
~.~
~~CYPRESS
- , SEMICONDUCTOR
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Free-Running Clocks[24, 27, 29]
COUNT
17
16
17
18
17
16
15
CKR
ENR
CKW
ENW
I
HIGH
HF
HIGH
ElF
C451-14
Read to Almost Empty Timing Diagram with Read Flag Update Cycle and Free-Running Clocks[24, 27, 29, 30, 31]
18 (no change)
COUNT
17
HF
HIGH
ElF
HIGH
16
17
FLAG UPDATE CYCLE
18
17
16
15
C451-13
Notes:
29. The FIFO in this example is assumed to be programmed to its default
flag values. Almost Empty is 16 words from Empty; Almost Full is 16
locations from Full.
30. R4 only updates the flag status. It does not affect the count because
ENRisHIGH.
31. When making the transition from Almost Empty to Intermediate, the
count must increase by two (16 .18; two enabled writes: W2, W3) before a read (R4) can update flags to the Less Than Half Full state.
5-135
CY7C45 1
CY7C453
:::rz:;~
~~CYPRESS
~JF SEMICONDUCTOR
Switching Waveforms (continued)
Write to Half Foil Timing Diagram with Free-Running Clocks[24, 32, 33, 34]
COUNT
1024
[256]
1025
[257]
1024
[256]
1023
[255]
1024
[256]
1025
[257]
1026
[258]
CKW
ENW
CKR
ENR
------/
RF'
ElF
PAFE
HIGH
HIGH
C451-15
Write to Half Foil Timing Diagram with Write Flag Update Cycle with Free-Running Clocks[24, 32, 33, 34, 35, 36]
1023 (no change)
[255]
COUNT
1024
[256]
1025
[257]
FLAG UPDATE CYCLE
1024
[256]
CKW
ENW
CKR
ENR
trn1
HF
ElF
PAFE
HIGH
HIGH
C451-16
Notes:
32. CKW is clock and CKR is opposite clock.
.
33. Count = 1,025 indicates Half Full for the CY7C453 and count = 257
indicates Half Full for the CY7C451. Values for CY7C451 count are
shown in brackets.
34. When the FIFO contains 1,024 [256] words, the rising edge of the next
enabled write causes the HF to be true (LOW).
35. The HFwrite flag update ~e does not affect the count because ENW
is HIGH. It only updates HF to HIGH.
36. When making the transition from Half Full to Less Than Half Full, the
count must decrease by two (1,025 ,1,023; two enabled reads: R2 and
R3) before a write (W4) can update flags to less than Half Full.
5-136
CY7C451
CY7C453
5- ;~PRESS
SEMICONDUCTOR
~,
Switching Waveforms
(continued)
Write to Almost Full Timing Diagram[24, 29, 32, 37, 38]
COUNT
2030
[494]
2031
[495]
2032
[496]
2031
[495]
2030
[494]
2031
[495]
i 2030- :
:
J4~4! J
2032
[496]
i 2031- :
:
J4~5! J
2033
[497]
i 2032- :
: 14~6!
J
CION
•
CKR
U)
o
u.
ii:
LOW
ElF
HIGH
C451-18
Write to Almost Full Timing Diagram with Free-Running Clocks[24, 29, 32]
COUNT
2031
[495]
2032
[496]
2031
[495]
2030
[494]
2031
[495]
2032
[496]
2033
[497]
CION
ENW
CKR
ENR
HF
LOW
ElF
HIGH
PAFE
tFD1
tFD~_
C451-17
Notes:
37. W2 updates the flag to the Almost Full state by asserting PAFE. Because Rl occurs greater than tSKEWl after W2, W2 does not recognize
Rl when updating the flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does
not have to be enabled to update flags.
38. The dashed lines showW3 as a flag update write rather than an enabled
write because ENW is deasserted.
5-137
CY7C451
CY7C453
~
.~WNDUcrQR
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[24, 29, 32)
2030 (no change)
[494)
COUNT 2031
[495)
2032
[496)
FLAG UPDATE CYCLE
2031
[495)
CKW
ENW
CKR
Em
LOW
HF
HIGH
ElF
tFD1
PAFE
C451-19
Write to Full Flag Timing Diagram with Free-Running Clocks[24, 25, 32, 39]
LATENT CYCLE
COUNT
CKW
CKR
ENR
HF
LOW
tFDi
ElF
PAFE
LOW
C451-20
Notes:
39. W2 is ignored because th~ FIFO is full (count = 2,048 [512]). It is important to note that W3 is also ignored because R3, the first enabled
read after full, occurs less than tSKEW2 before W3. Therefore, the
5-138
FIFO still appears full when W3 occurs. Because R3 occurs greater
than tSKEW2 before W4, W4 includes R3 in the flag update.
CY7C451
CY7C453
.
~~PRESS
~, SEMICONDUCTOR
Switching Waveforms (continued)
Even Parity Generation Timing Diagram[40, 41]
CKR
Oa/PG;PE
0 0-
7
-1
ENABLED READ
"'----~/
DISABLED READ ' "......_ _ _ _ __
tpG - - - - + I
PREVIOUS WORD:
EVEN NUMBER OF 15
NEW WORD
ODD NUMBER OF 15
;(XXXXy
'
CKR
~f------------+----------+~
O~PGf'----------------------------------~~~~------------------PE
Oo-HF
1
1
0
494
2030
Flag Update
1
0
494
2030
Write
(ENW= 0)
>HF
1
1
0
495
2031
Write
1
0
495
2031
Write
AF
(ENW =0)
1
0
0
496
2032
Write (,fransition from
>HF to AF)
AF
1
0
AF
1
AF
0
496
0
0
1
0
>HF
1
>HF
1
Table 5. Programmable Almost Full/Almost Empty Options - CY7C451/CY7C453[49]
PAFE Active when CY7C451/453 is:
p[50]
D5
D4
D3
D2
Dl
DO
0
0
0
0
0
0
Completely Full and Empty.
0
0
0
0
0
1
16 or less locations from Empty/Full (default)
1
0
0
0
0
1
0
32 or less locations from Empty/Full
2
0
0
0
0
1
1
48 or less locations from Empty/Full
3
224 or less locations from Empty/Full
240 or less locations from Empty/Full
992 or less locations from Empty/Full
1008 or less locations from Empty/Full
5-145
•
(I)
Status Before Operation
0
CY7C451
CY7C453
&;rlPRR§
~, SEMICONDUCTOR
Table 6..Programmable Parity Options
Condition
D8
D7
D6
0
X
X
1
0
0
Generate even parity on PG output pin.
1
0
1
Generate odd parity on PG output pin.
1
1
0
Check for even parity. Indicate error on PE output pin.
1
1
1
Check for odd parity. Indicate error on PE output pin.
Parity disabled.
Notes:
47. Applies to both CY7C451 and CY7C453 operations when devices are
programmed so that Almost Empty becomes active when the FIFO
contains 32 or fewer words.
48. Programmed so that Almost Full becomes active when the FIFO contains 16 or less empty locations.
49. D4 and D5 are don't care for CY7C451.
50. Referenced in Table 1.
5-146
CY7C451
CY7C453
.~
CYPRESS
-====-IF SEMICONDUCTOR
'lE
1Ypical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.4
C,.)
1.2
C,.)
.2
o
w
~ 1.0
w
~ 1.0 1---+-----::o"F---I---~
«
«
:2
1.1
I~
0.6 L:----:-'-:---1.--___L.....---i
4
4.5
5
5.5
6
w
~ 0.7
~
SUPPLY VOLTAGE (V)
NORMALIZED tA vs.
SUPPLY VOLTAGE
I
1.6
I
o
NORMALIZED tA vs.
AMBIENT TEMPERATURE
oW
c:
o
w
~
~ 1.2
«
:2
V-
~ 1.0
z
0.9
o
4.0
~
O.s
4.5
5.0
5.5
0.6
-55
6.0
SUPPLY VOLTAGE (V)
.s
60
I
50
TA = 25°C,
Vee=5.0V
I-
15
c:
c:
3
w
a?
30
~
20
=>
40
"I'"
l-
g:=>
=>
o
10
o
o
1
1~::
z
~
5.0
"~
40
~
20
60
=>
a.
'\
3
~
z
~
o
4
OUTPUT VOLTAGE (V)
o
V
1/
o
200
400
1
/
I---
-
~
2
3
OUTPUT VOLTAGE (V)
5-147
600
SOO 1000
CAPACITANCE (pF)
/
II
o
V
~V
I
so
I---
L..--
//
10.0
TA = 25°C,
Vee=5.0V
I-
I
./
15.0
:...J
OUTPUT SINK CURRENT vs.
OUTPUT VOLTAGE
c:
c:
=>
2
..:
~
o
f---
100
4
I
rn
ou.
i!:
~~~=;i~~V -
~20.0
25
125
AMBIENT TEMPERATURE (0C)
W
'"
I
25.0 >-- ~
-----
OUTPUT SOURCE CURRENT vs.
OUTPUT VOLTAGE
8 c.... clL>
W
O2
06
07
NC
mAT
!OF
~
Xl
FI../Rf
MR
06
~
R
Do
FF
02
cf'
l(O/RF
C460-1
5-150
C460-2
De
MR
EF
07
0 ....
Ds
D2
D7
l(O/RF
(!)
D4
D3
D1
NC
cf' d" ~ ~ Ie::
Vee
FDRT
00
0,
DATA OUTPUTS
(Oo-Os)
W
Ds
XI
EF
Qo
XO/RF
Q1
Q2
Q7
Qe
Q3
Qs
Qs
GND
Q4
R
C460-3
CY7C460
CY7C462
CY7C464
~
PI
,
iaPRESS
PRELIMINARY
SEM:JCONDUCTOR
Selection Guide
7C460-15
7C462-15
7C464-15
33.3
15
160
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating
I Commercial
Current (rnA)
I Military
7C460-25
7C462-25
7C464-25
28.5
25
145
165
7C460-20
7C462-20
7C464-20
33.3
20
165
7C460-40
7C462-40
7C464-40
20
40
125
145
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... -55°Cto+125°C
Supply Voltage to Ground Potential ....... - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - 0.5V to +7.0V
DC Input Voltage ...................... - 3.0V to +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.OW
Output Current, into Outputs (LOW) .............. 20 rnA
Electrical Characteristics Over the Operating Rangd Z]
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Industrial
Military[l]
7C460-15
7C462·15
7C464·15
Parameter
VOH
VOL
VIH
VIL
IIX
loz
Icc
Test Conditions
Vee = Min.,IOH= - 2.0rnA
2.4
Vee = Min., IOL = 8.0 rnA
Com'l
Mil/Ind
2.0
R~ VIH, GND ~ Vo ~ Vee
-10
+10
Vee = Max.,
lOUT = ornA
Com'I[3]
Mil/Ind[4]
160
Com'l
25
ISBZ
Power-Down Current
All Inputs
Vee- 0.2V
los
Output Short
Circuit CurrendS]
3.
5V ± 10%
7C460-25
7C462·25
7C464·25
TA is the "instant on" case temperature.
See the last page of this specification for Group A subgroup testing information.
Icc (commercial) = 125 rnA + [(f - 20) * 2.5 mA/MHz]
2.4
7C460-40
7C462·40
7C464-40
Unit
V
0.4
2.0
2.2
V
V
-10
0.8
+10
-10
0.8
+10
-10
0.8
+10
f.IA
-10
+10
-10
+10
-10
+10
f.IA
145
165
25
125
145
25
rnA
30
20
25
-90
30
20
25
-90
25
-90
-90
Icc (military)
0.4
2.0
2.2
20
4.
2.4
0.4
30
Mil/Ind
Com'l
Mil/Ind
Vee = Max., VOUT = GND
=
V
rnA
rnA
rnA
130 rnA + [(f - 20) • 2.5 mA/MHz]
forf~20MHz
5.
forf~20MHz
where f = the larger of the write or read operating frequency.
- 55°C to +125°C
165
Notes:
1.
2.
5V ± 10%
2.2
-10
All Inputs =
VIHMin.
- 40°C to +85°C
7C460-20
7C462·20
7C464·20
0.4
GND~VI~Vee
Standby Current
Vee
5V ± 10%
2.4
0.8
+10
ISBl
O°Cto + 70°C
Min. Max. Min. Max. Min. Max. Min. Max.
Description
Output HIGH
Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
Operating Current
Ambient
Temperature
Range
Commercial
6.
5-151
where f = the larger of the write or read operating frequency.
For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 1 second.
Tested initially and after any design or process changes that may affect
these parameters.
•
en
ou..
u:::
~
~~PRESS
~_. , SEMICONDUCTOR
CY7C460
CY7C462
CY7C464
PRELIMINARY
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f
Vee = 5.0V
Max.
= 1 MHz,
Unit
pF
8
10
pF
AC Test Loads and Waveforms
00-------..,.,.,. . .
R1500n
5V
OUTPUT O o - - - f - - - - t
FI
-=-
C460-4
5PFI
90%
GND
R2
333n
INCLUDING
JIGAND _
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ----...J..r-""----~
OUTPUT O o - - - f - - -....
R2
333n
30 P
INCLUDING
JIGAND _
SCOPE -
00------..,.,.,..,
R1500n
5V
C460-6
C460-5
(b)
THEVENIN EQUIVALENT
20of1
OUTPUT 00------".>III
..........---o02V
Switching Characteristics Over the Operating Rangd 2,7]
7C460-15
7C462-15
7C464-15
Parameter
I
Description
Min.
Max.
7C460-20
7C462-20
7C464-20
Min.
Max.
7C460-25
7C462-25
7C464-25
Min.
Max.
7C460-40
7C462-40
7C464-40
Min.
Max.
Unit
tRe
Read Cycle Time
tA
Access Time
tRR
Read Recovery Time
10
10
10
10
ns
tpR
Read Pulse Width
15
20
25
40
ns
tLZR
Read LOW to Low Z
3
3
3
3
ns
tDVR[8]
Data Valid After Read HIGH
3
3
3
3
tHZR[8]
Read HIGH to High Z
twe
Write Cycle Time
30
30
35
50
tpw
Write Pulse Width
15
20
25
40
ns
tHWZ
Write HIGH to Low Z
5
5
5
5
ns
tWR
Write Recovery Time
10
10
10
10
ns
tSD
Data Set-Up Time
11
12
15
20
ns
tHD
Data Hold Time
0
0
0
0
ns
tMRse
MR Cycle Time
30
30
35
50
ns
tpMR
MR Pulse Width
15
20
25
40
ns
tRMR
MR Recovery Time
10
10
10
10
ns
tRPW
Read HIGH to MR HIGH
15
20
25
40
ns
twpw
Write HIGH to MR HIGH
15
20
25
40
ns
30
35
30
15
20
15
50
25
15
ns
40
18
ns
ns
25
ns
ns
tRTe
Retansmit Cycle Time
30
30
35
50
ns
tpRT
Retransmit Pulse Width
15
20
25
40
ns
tRTR
Retransmit Recovery Time
10
10
10
10
ns
tEFL
MR to EF LOW
25
30
35
50
ns
tHFH
MRtoHFHIGH
25
30
35
50
ns
MR to FF HIGH
25
30
35
50
ns
tFFH
I
5-152
·:~
====::==:1=
CYPRESS
. _ iF SEMICONDUCTOR
CY7C460
CY7C462
CY7C464
PRELIMINARY
Switching Characteristics Over the Operating Rangel 2,7] (continued)
7C460-20
7C462-20
7C464-20
7C460-15
7C462-15
7C464-15
Description
Parameter
Min.
Max.
Min.
7C460-25
7C462-25
7C464-25
Max.
Min.
7C460-40
7C462-40
7C464-40
Max.
Unit
25
40
ns
25
25
40
ns
ns
Max.
Min.
tREF
Read LOW to EF LOW
15
20
tRFF
tWEF
Read HIGH to FF HIGH
15
20
Write HIGH to EF HIGH
Write LOW to FF LOW
15
15
20
20
tWHF
tRHF
tRAE
Write LOW to HF LOW
Read HIGH to HF HIGH
25
25
30
30
35
35
50
ns
ns
50
ns
Effective Read from Write HIGH
15
20
25
40
tRPE
tWAF
Effective Read Pulse Width After EF HIGH
Effective Write from Read HIGH
15
ns
ns
40
tWPF
Effective Write Pulse Width After FF HIGH
15
ns
ns
I
tXOL
Expansion Out LOW Delay from Clock
15
20
25
40
tXOH
Expansion Out HIGH Delay from Clock
30
35
35
50
ns
ns
ou..
tWFF
25
20
15
40
40
40
25
20
25
20
40
25
Switching Waveforms[9]
Asynchronous Read and Write
QO-Q8--------------~
""--_ _ _----'f
»-------c(
Master Reset
DATA VALID
)>----
C460-7
1 + - - - - - tMRSC[11] ---------~
MR ____________~~----
~
tpMR
------~,~------+_-------------------
XXXxxxxxxxXXXXX
C460-8
Notes:
7. Test conditions assume signal transmission time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified IOrJIOH
and 30-pF load capacitance, as in part (a) of AC Test Load, unless
otherwise specified.
8. tHZR and tDvR use capacitance loading as in part (b) of AC Test Load.
9.
A HIGH-to-LOW transition of either the write or read strobe causes
a HIGH-to-LOW transition ofthe responding flag. Correspondingly,
alow-to-high strobe transition causes aLOW-to-HIGH flag transition.
10. Wand R = V IH around the rising edge of MR.
11. tMRSC = tpMR + tRMR.
5-153
en
u:::
~~
~'''CYPRESS
~,
CY7C460
CY7C462
CY7C464
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms
Half Full Flag
w
HALF FULL
HALF FULL +1
HALF FULL
-
J
tRHF
~
.,
1+
tWHF . ,
~
~
C460-9
Last Write to First Read Full Flag
LAST WRITE
R---+--------------~
ADDITIONAL
READS
FIRST READ
FIRST WRITE
W--___ I
FF---+----... I
C460-10
Last READ to First WRITE Empty Flag
LAST READ
w--+---------------+-
ADDITIONAL
WRITES
FIRST WRITE
FIRST READ
EF--+--I-""Ii
DATA OUT
-~I----(
C460-11
Retransmid12, 13]
1 + - - - - - tRTC -----~
FLIRT
--+-----.. .
1
R,w
C460-12
Notes:
12_ tRTC = tPRT
+ tRTR'
13. EF, HF and FFmay change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC.
5-154
;~
_'=
--=-F CYPRESS
.
PRELIMINARY
CY7C460
CY7C462
CY7C464
SEMICONDUCTOR
Switching Waveforms (continued)
Empty Flag and Read Data Flow-Through Mode
DATA IN
W ---1---"",
•
EF--+---------~--'I
DATA OUT
C460·13
Full Flag and Write Data Flow-Through Mode
ff--+---------+--J
DATAIN
--+---------------r
I.-~L
DATA OUT ~~D-A-TA--V-AL-ID---~~-------------------C460-14
5-155
=-- :;
~PRESS
PRELIMINARY
~, SEMICONDUCTOR
CY7C460
CY7C462
CY7C464
Switching Waveforms (continued)
Expansion Timing Diagrams
w---~
X01 (Xh)[14]
---------------+--
DATA VALID
C460-15
Note:
14_ Expansion out of device 1 (X01) is connected to expansion in of device 2 (Xl2)'
5-156
~~
PRELIMINARY
~=CYPRESS
~_,
CY7C460
CY7C462
CY7C464
SEMICONDUCTOR
Architecture
Retransmit
Resetting the FIFO
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit (RT) input is
active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes
equal-to-or-less-than the depth of the FIFO have occurred since
the last MR cycle. A LOW pulse on RT resets th~nter~ read
pointer to the first physical location of the FI~8
Top View
0 "" 0'"
02
01
J5AIt
00
01
NC
R
AT
w
02
~
cf' d" ~ ~ Itt:
(!l
0""
c:!'
7C47D-2
04
05
03
07
O2
01
00
AT
~
Vee
06
NC
Do
W
08
MR
ElF
MARK
PAFE
HF
00
07
Q1
06
Q2
Q3
Q8
GNO
06
07
RT
MR
ElF
HF
Q7
Q6
Q5
Q4
R
7C47D-3
DATA OUTPUTS
(00- 0 8)
7C470·1
5-163
II
en
o
LL.
Ii:
CY7C470
CY7C472
CY7C474
~
=-:
i~PRESS
PRELIMINARY
_ . , SEMICONDUCTOR
Selection Guide
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating Current (rnA)
7C470-15
7C472-15
7C474-15
7C470-20
7C472-20
7C474-20
7C470-25
7C472-25
7C474-25
7C470-40
7C472-40
7C474-40
33.3
15
160
33.3
20
28.5
25
145
165
20
40
125
145
I Commercial
I
165
Military/Industrial
Maximum Ratings
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage to Ground Potential . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ........................ - O.5V to +7.0V
DC Input Voltage ...................... - 3.0Vto +7.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Output Current, into Outputs (LOW) .... . . . . . . . . .. 20 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Industrial
Military[l]
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Rangd2J
7C470-15
7C472-15
7C474-15
Parameter
VOH
VOL
VIH
VIL
Ilx
laz
Icc
ISBI
ISB2
Description
Standby Current
Power-Down Current All Inputs =
Vee -O.2V
las LS ]
Output Short Circuit
Current
2.4
2.4
0.4
0.4
7C470-40
7C472-40
7C474-40
-10
0.4
V
0.4
V
V
2.0
2.2
-10
0.8
+10
-10
0.8
+10
-10
0.8
+10
V
f,LA
+10
-10
+10
-10
+10
-10
+10
f,LA
125
145
25
30
20
25
-90
rnA
160
165
30
20
-90
4.
Unit
0.8
+10
25
Vee = Max.,
VouT=GND
2.4
2.0
2.2
2.2
Com'l
Mil/Ind
Com'l
Mil/Ind
Notes:
1. TA is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. Icc (commercial) = 125 rnA + (f - 20) • 2.5 mNMHz for
2.4
2.0
-10
R~ VIH,
GND.5 Vo.5 Vee
Com'I13]
Vee = Max.,
lOUT = ornA
Mil[4]/Ind
All Inputs =
VIHMin.
7C470-25
7C472-25
7C474-25
Min. Max. Min. Max. Min. Max. Min. Max.
Test Conditions
Output HIGH
Vee = Min.,
Voltage
IOH = - 2.0 rnA
Output LOW Voltage Vee = Min., IOL = 8.0 rnA
Input HIGH Voltage
Com'l
Mil/Ind
Input LOW Voltage
Input Leakage
GND.5 VI.5 Vee
Current
Output Leakage
Current
Operating Current
7C470-20
7C472-20
7C474-20
Icc (military)
25
-90
= 130 rnA
145
165
25
30
20
25
-90
rnA
rnA
rnA
+ (f - 20) • 2.5 mNMHz for
f~20MHz
5.
f~20MHz
where f = the larger of the write or read operating frequency.
5-164
where f = the larger of the write or read operating frequency.
Not more than one output should be tested at a time. Duration of the
short circuit should not be more than one second.
· :4
=.=
--=-F
CY7C470
CY7C472
CY7C474
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Capacitance[6]
Parameter
Description
Test Conditions
TA = 25°C, f
Vee = 4.5V
Input Capacitance
Output Capacitance
CIN
COUT
Max.
10
12
= 1 MHz,
Unit
pF
pF
AC Test Loads and Waveforms
R1500n.
5V o----..IW"--,
R1500n.
5V o----..IW"--,
OUTPUTo---......----t
OUTPUTo---.......----t
30
FI
R2
P
333n.
INCLUDING
JIGAND _
-=
SCOPE -
5PFI
GND
R2
333n.
INCLUDING
JIG AND _
7C470-4
7C470-6
SCOPE -
(a)
Equivalent to:
ALL INPUT PULSES
3.0V ------::.Jr-----~
7C470-5
(b)
I
THEVENIN EQUIVALENT
20oD.
(I)
OUTPUT OO--_.NY,O------OO 2V
ou..
ii:
Switching Characteristics Over the Operating Range[7,8]
7C470-15
7C472-15
7C474-15
Parameter
Description
Min.
7C470-20
7C472-20
7C474-20
Max.
Min.
Max.
30
7C470-25
7C472-25
7C474-25
Min.
Max.
7C470-40
7C472-40
7C474-40
Min.
Max.
tCY
tA
Access Time
tRY
Recovery Time
10
10
10
10
ns
tpw
Pulse Width
15
20
25
40
ns
30
15
50
Unit
Cycle Time
35
20
25
ns
40
ns
tLZR
Read LOW to Low Z
3
3
3
3
ns
tDVR[9]
Valid Data from Read HIGH
3
3
3
3
ns
tHZR[9]
Read HIGH to High Z
15
18
15
25
ns
tHWZ
Write HIGH to Low Z
5
5
5
5
ns
tSD
Data Set-Up Time
11
12
15
20
ns
tHD
Data Hold Time
0
tEFD
ElF Delay
15
20
25
40
tEFL
MRto ElF LOW
25
30
35
50
ns
tHFD
HFDelay
25
30
35
50
os
50
ns
0
25
0
0
os
tAFED
PAFEDelay
tRAE
Effective Read from Write HIGH
15
20
25
40
ns
tWAF
Effective Write from Read HIGH
15
20
25
40
os
Notes:
6. Tested initially and after any design or process changes that may affect
these parameters.
7. Test conditions assume signal transmission time of 5 ns or less, timing
reference levels of 1.5V and output loading of the specified IorJIOH
and 30-pF load capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified.
8.
9.
5-165
35
ns
30
See the last page of this specification for Group A subgroup testing information.
tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads.
tHZR transition is measured at +500 mV from VOL and - 500 mV
from VOH. tDVR transition is measured at the 1.5V level. tHWZ and
tLZR transition is measured at ±100 mV from the steady state.
~
. .~
~.CYPRESS
-
PRELIMINARY
~, SEMICONDUcrOR
CY7C470
CY7C472
CY7C474
Switching Waveforms
Asynchronous Read and Write
R
---,I
-e--- ~
Qo-Qs----~-~
w
Do-Os
I"-~I'~
=i.------i
___________ J '
~ ~
l- -
r;: !so ::L "'0 J
---------1(1'JI).------~("'__
DATA VALID
DA_T_A_V_A_L_ID_..J»------
7C470·7
Master Reset (No Write to Programmable Flag Register)
1+------- tCY
--------~
R,W
RF
ElF
7C470·8
Master Reset (Write to Programmable Flag Register) [10]
tRY --~
1'IW(R)
tpw -
I--
tCY
~
~
tRY - - ~k:
tHD
tSD
II
"
VALID
7C470-9
Note:
10. Waveform labels in parentheses pertain to writing the programmable
flag register from the output port (00 - 08).
5-166
CY7C470
CY7C472
CY7C474
~
.
::~
-----116
iF
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Ell" Flag (Last Write to First Read Full Flag)
W
/
tEf i 1
R
ElF
HF
FULL-1
FULL
FULL-1
\
t'Effij-
LOW
7C470-10
ElF Flag (Last Read to First Write Empty Flag)
II
U)
0
R
EMPTY +1
w
ElF
HF
t~1
LI.
EMPTY
u::
EMPTY +1
/
\
t'Effij-
HIGH
7C470-11
Half Full Flag
W
HALF-FULL
R
HF
HALF-FULL
HALF-FULL +1
~ ~ffi
1
\
:-~FDj7C470-12
5-167
CY7C470
CY7C472
CY7C474
~
~~
PRELIMINARY
-~ CYPRESS
7
SEMICONDUcrOR
Switching Waveforms (continued)
PAFE Flag (Almost Full)
t~FED 1
W
/
R
PAFE
HF
~tAFEDi-
\
LOW
7C470-13
PAFE Flag (Almost Empty)
t.A~1
R
w
PAFE
HF
/
~t~EDi-
\
HIGH
7C470-14
Retransmit
tCY
tCY
W,R
-
-'~
~
.- tRV" f4-- t p w - I+- tRV ..
tCY
Qo-Qa
-
I
tA--'
>z,
'YXV
\-1\
DATA VALID
7C470-15
5-168
~
=-..
~
CYPRESS
~.a
IF
CY7C470
CY7C472
CY7C474
PRELIMINARY
SEN]CONDUCI'OR
Switching Waveforms (continued)
Mark
tCY
tCY
W,R
~
-1\
.,
I-
~
tRY .- : . . - t p w - ... tRV ....
7C470-16
II
en
oLL.
i!
Empty Flag and Read Data Flow-Through Mode
DATA IN
w--~---
,----Elf ---r------~==~
DATA OUT
----+---------1---1(
7C470-17
5-169
~
=::-
.~
PRELIMINARY
~i= CYPRESS
~F
CY7C470
CY7C472
CY7C474
SEMICONDUCTOR
Switching Waveforms (continued)
Full Flag and Write Data Flow-Through Mode
w
ElF
tSD -
DATA IN
.....--+1
----t--------------C
DATA OUT - - - 0 (
DATA VALID
7C470-18
Architecture
Retransmit
TheCY7C470,CY7C472,andCY7C474FIFOsconsistofanarray
of 8, 192, 16,384, and 32,768 words of 9 bits each, respectively. The
control consists of a read pointer, a write pointer, a retransmit
pointer, control signals (i.e., write, read, mark, retransmit, and master reset), and flags (i.e., Empty/Full, Half Full, and Programmable
Almost Full/Empty).
Resetting the FIFO
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the receiver and resent if necessary. Retransmission can start from anywhere in the FIFO and be repeated without limitation.
The retransmit methodology is as follows: mark the current value
of the read pointer, after an error in subsequent read operations
return to that location and resume reading. This effectively resends all of the data from the mark point. When MARK is LOW,
the current value of the read pointer is stored. Thi~eration
marks the beginning of the packet to be resent. When RT is LOW,
the read pointer is updated with the mark location. During each
subsequent read cycle, data is read and the read pointer incremented.
Care must be taken when using the retransmit feature. Use the
mark function such that the write pointer does not pass the mark
pointer, because further write operations will overwrite data.
Programmable Almost Full/Empty Flag
Upon power up, the FIFO must be reset with a master reset (MR)
cycle. This causes the FIFO to enter the empty condition signified
by the Empty flag (ElF) and Almost Full/Empty flag (PAPE) being
LOW, and Half Full flag (HF) being HIGH. The read pointer, write
pointer, and retransmit pointer are reset to zero. For a valid reset,
read (R:) and write (W) must be HIGH tRPW/tWpw before the falling edge and tRMR after the rising edge of MR.
Writing Data to the FIFO
Data can be written to the FIFO when it is not FULLllll. A falling
edge of W initiates a write cycle. Data appearing at the inputs
(Do- Ds) tSD before and tHD after the rising edge of W will be
stored sequentially in the FIFO.
Reading Data from the FIFO
Data can be read from the FIFO when it is not empty[ 121. A falling
edge of R initiates a read cycle. Data outputs (Oo-Os) are in a
high-impedance ~ndition when the FIFO is em.E.ty and between
read operations (R HIGH). The falling edge of R during the last
read cycle before the empty condition triggers a high-to-Iow transition ofEiF, prohibiting any further read operations until tRFF after a valid write.
Notes:
11. When the FIFO is less than half full, the flags make a LOW-to-HIGH
transition on the rising ed~ ofW and make the HIGH-to-LOW transition on the falling edge ofR.1f the FIFO is more than half full, th~ flags
make the LOW-to-HIGH transition on the ris!!!g edge of Rand
HIGH-to-LOW transition on the falling edge of W.
The CY7C470/2/4 offer a variable offset for the Almost Empty and
the Almost Full condition. The offset is loaded into the pro~m
mabIe flag register (PFR) during a master reset cycle. While MR is
LOW, the PFR can be loaded from Os - 00 by pulsing R: LOW or
from Ds - Do by pulsing W LOW. The offset options are listed in
Table 2. See Table 1 for a description of the six FIFO states. If the
PFR is not loaded during master reset (R andW HIGH) the default
offset will be 256 words from Full and Empty.
12. Full and em2!Y_states can be decoded from the Half-Full (HF) and
EmptyIFull (ElF) flags.
5-170
---..
~
CY7C470
CY7C472
CY7C474
PRELIMINARY
_'.CYPRESS
- . I F SEMICONDUcrOR
Table 1. Flag Truth Table[13]
CY77C470
(8Kx 9)
Number of Words in
FIFO
HF
EtF
PAFE
1
0
0
Empty
1
1
0
Almost Empty
1
1
1
Less than Half Full
0
1
1
Greater than Half Full
State
CY77C472
(16K x 9)
Number of Words in
FIFO
0
0
1
0
Almost Full
0
0
0
Full
1
~
(P - 1)
P~
4097
~
0
0
1 ~ (P - 1)
1 ~ (P - 1)
4096
P
(8192 - P)
(8192 - P+1)
~
8191
CY77C474
(32Kx 9)
Number of Words in
FIFO
8193
~
~
8192
P
(16384 - P)
(16384 - P+1)
~
16383
16384
8192
~
16384
16385 ~ (32768 - P)
(32768 - P+ 1)
~
32767
32768
Table 2. Programmable Almost Full/Empty Empty Options[14]
D3
D2
Dl
DO
0
0
0
0
256 or less locations from Empty/Full (default)
256
0
0
0
1
16 or less locations from Empty/Full
16
PAFE Active when:
P
0
0
1
0
32 or less locations from Empty/Full
32
0
0
1
1
64 or less locations from Empty/Full
64
0
1
0
0
128 or less locations from Empty/Full
128
0
1
0
1
256 or less locations from Empty/Full (default)
256
0
1
1
0
512 or less locations from Empty/Full
512
0
1
1
1
1024 or less locations from Empty/Full
1024
1
0
0
0
2048 or less locations from Empty/Full
2048
1
0
0
1
4098 or less locations from Empty/Full[15]
4098
1
0
1
0
8192 or less locations from Empty/Full[16]
8192
Notes:
13. See Table 2 for P values.
14. Almost flags default to 256 locations from Empty/Full.
15. Only for CY7C472 and CY7C474.
16. Only for CY7C470.
5-171
•
en
o
u::
~
~
5~~
.J'
~~
~_
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
15
20
25
40
Ordering Code
Package
Name
Package 'JYpe
CY7C470-15DC
D16
28-Lead (600-Mil) CerDIP
CY7C470-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-15PC
P15
28-Lead (600-Mil) Molded DIP
CY7C470-15DI
D16
28-Lead (600-Mil) CerDIP
CY7C470-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-15PI
P15
28-Lead (600-Mil) Molded DIP
CY7C470-20DMB
D16
28-Lead (600-Mil) CerDIP
CY7C470-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C470-25DC
D16
28-Lead (600-Mil) CerDIP
CY7C470-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-25PC
P15
28-Lead (600-Mil) Molded DIP
CY7C470-25DI
D16
28-Lead (600-Mil) CerDIP
CY7C470-25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-25PI
P15
28-Lead (600-Mil) Molded DIP
CY7C470-25DMB
D16
28-Lead (600-Mil) CerDIP
CY7C470-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C470-40DC
D16
28-Lead (600-Mil) CerDIP
CY7C470-4OJC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-40PC
P15
28-Lead (600-Mil) Molded DIP
CY7C470-40DI
D16
28-Lead (600-Mil) CerDIP
CY7C470-40JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C470-40PI
P15
28-Lead (600-Mil) Molded DIP
CY7C470-40DMB
D16
28-Lead (600-Mil) CerDIP
CY7C470-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-172
Operating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C470
CY7C472
CY7C474
~
--.
~~
=====;; CYPRESS
$' SEMICONDUCTOR
PRELIMINARY
CY7C470
CY7C472
CY7C474
Ordering Information (continued)
Speed
(ns)
15
20
25
40
Ordering Code
Package
Name
Package 1Ype
CY7C472-15DC
D16
28-Lead (600-Mil) CerDlP
CY7C472-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-15PC
P15
28-Lead (600-Mil) Molded DIP
CY7C472-15D1
D16
28-Lead (600-Mil) CerDlP
CY7C472-15JI
J65
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
CY7C472-15PI
P15
CY7C472-20DMB
D16
28-Lead (600-Mil) CerDIP
CY7C472-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C472-25DC
D16
28-Lead (600-Mil) CerDlP
CY7C472-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-25PC
P15
28-Lead (600-Mil) Molded DIP
CY7C472-25D1
D16
28-Lead (600-Mil) CerDlP
CY7C472-25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-25PI
P15
28-Lead (600-Mil) Molded DIP
CY7C472-25DMB
D16
28-Lead (600-Mil) CerDIP
CY7C472-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C472-40DC
D16
28-Lead (600-Mil) CerDIP
CY7C472-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-40PC
P15
28-Lead (600-Mil) Molded DIP
CY7C472-40Dl
D16
28-Lead (600-Mil) CerDlP
CY7C472-40JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C472-40PI
P15
28-Lead (600-Mil) Molded DIP
CY7C472-40DMB
D16
28-Lead (600-Mil) CerDlP
CY7C472-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
5-173
Operating
Range
Commercial
Industrial
Military
Commercial
I
Industrial
Military
Commercial
Industrial
Military
~
~~PRESS
~, SEMICONDUCTOR
PRELIMINARY
Ordering Information (continued)
Speed
(ns)
15
20
25
40
Ordering Code
Package
Name
Package lYpe
CY7C474-15DC
D16
28-Lead (600-Mil) CerDIP
CY7C474-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474-15PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C474-15DI
D16
28-Lead (600-Mil) CerDIP
CY7C474-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474-15PI
PIS
28-Lead (600-Mil) Molded DIP
CY7C474-20DMB
D16
28-Lead (600-Mil) CerDIP
CY7C474-20LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C474-25DC
D16
28-Lead (600-Mil) CerDIP
CY7C474-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474-25PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C474-25DI
D16
28-Lead (600-Mil) CerDIP
CY7C474-25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474-25PI
PIS
28-Lead (600-Mil) Molded DIP
CY7C474-25DMB
D16
28-Lead (600-Mil) CerDIP
CY7C474-25LMB
L55
32-Pin Rectangular Leadless Chip Carrier
CY7C474-40DC
D16
28-Lead (600-Mil) CerDIP
CY7C474-40JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474-40PC
PIS
28-Lead (600-Mil) Molded DIP
CY7C474-40Dl
D16
28-Lead (600-Mil) CerDIP
CY7C474-40JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C474-40PI
PIS
28-Lead (600-Mil) Molded DIP
CY7C474-40DMB
D16
28-Lead (600-Mil) CerDIP
CY7C474-40LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Operating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
CY7C470
CY7C472
CY7C474
·
:~
PRELIMINARY
=====
-= CYPRESS
~# SEMICONDUCTOR
CY7C470
CY7C472
CY7C474
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1,2,3
VOL
1,2,3
VIR
1,2,3
VILMax.
1,2,3
IIX
1,2,3
los
1,2,3
Icc
1,2,3
I
Switching Characteristics
Parameter
Subgroups
tCY
9,10,11
tA
9,10,11
tRY
9,10,11
tpw
9,10,11
tLZR
9,10,11
tDVR
9,10,11
tHZR
9,10,11
tHWZ
9,10,11
tSD
9,10,11
tHD
9,10,11
tEFD
9,10,11
tHFD
9,10,11
tAFED
9,10,11
tRAE
9,10,11
tWAF
9,10,11
Document #: 38-00142-E
5-175
-=-;;~PRESS
.' i
Section Contents
SEMICONDUCTOR
Logic
Device Number
CY7C611A
CY7C915
CY7B991
CY7B992
CY7C9101
Page Number
Description
32-Bit RISC Controller ........................................................ 6-1
1Kx 42 SmartCAM ........................................................... 6-8
Programmable Skew Clock Buffer (PSCB) ....................................... 6-11
Programmable Skew Clock Buffer (PSCB) ....................................... 6-11
CMOS 16-Bit Slice .... .. . . .. .. .. .. .. .. . . . . . .. . . .. . . . . . . . .. .. .. . .. . .. . . .. .. ... 6-22
CY7C611A
32-Bit RISe Controller
Features
• SPARC® processor optimized for embedded control applications
• Reduced Instruction Set Computer
(RISC) architecture
- Simple format instructions
- Most instructions execute in a
single cycle
• Very high performance
- 40-ns instruction cycle with 4-stage
pipeline
-18 sustained MIPS at 25 MHz
- 240-ns worst-case interrupt response
• 136 32-bit registers
- Eight overlapping windows of 24
registers each
- Dividing registers into seperate
register banks allows fast context
switching
- 8 global registers
• Hardware pipeline interlocks
• 16 prioritized interrupts levels
• Large address space
- 24-bit address space
- 3-bit address space indentifier
- Privileged instructions
• Artificial intelligence support
• Multiprocessing support
• High-performance floating-point processor interface
- Concurrent execution of floating-point instructions
• O.8-micron 2-layer metal CMOS technology
• 160-pin quad flat package
• Power
- 3 watts maximum
• Multitasking support
- User/supervisor modes
•
Pin Configuration
Logic Block Diagram
DESTINATION
Fl5
A(23:0)
REGISTER FilE
136 x32
FROIJ)
ASI(2:0)
FEl2001V
(per MIL-STD-883, Method 301S)
Latch-Up Current ............................ >200 rnA
SsoC to + 12SoC
Operating Range
Ambient
Temperature
O°C to +70°C
SV ± 10%
- SSOCto + 12SoC
SV ± 10%
Range
Commercial
- O.5V to + 7.0V
- O.SV to + 7.0V
- O.5V to +7.0V
Military[l]
Vee
Electrical Characteristics Over the Operating Rangd2]
CY7C915
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
loz
los
Icc
ISB
Min.
= Min., IOH = - 3.0 rnA
= Min., IOL = 6.0 rnA
Max.
Units
2.4
V
0.4
V
2.2
Vcc
+0.3
V
- 0.5
0.8
V
GND ~ VIN ~ Vee
-1
+1
Output Leakage Current
GND ~ VOUT ~ Vee, Output Disabled
-S
Output Short
Circuit Currentl3]
Vee
= Max., VOUT = GND
Vee Operating
Supply Current
Vee
= Max., lOUT = 0 rnA
Automatic CE
Power-Down Current
Max. Vee,
Com'l
+S
!JA
!JA
TBD
rnA
TBD
rnA
TBD
rnA
Mil
CE~
Com'l
Vm
Mil
Capacitance[4]
Parameters
Description
qN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 2SoC, f
Vee = S.OV
Notes:
TA is the "instant on" case temperature.
1.
2.
See the last page of this specification for Group A subgroup testing
information.
3.
4.
Document #: 38-00206
6-10
= 1 MHz,
Max.
Units
TBD
pF
TBD
pF
Duration of the short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
CY7B991
CY7B992
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Programmable Skew
Clock Buffer (PSCB)
Features
Functional Description
• Output pair skew < 100 ps typical
(250 max.)
• All outputs skew <250 ps typical
(500 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
- Selectable skew to 18 ns
- Inverted and non-inverted
- Operation at V2 and % input
frequency
- Operation at 2x and 4x input
frequency (input as low as 3.75
The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer
user-selectable control over system clock
functions. These multiple-output clock
drivers provide the system integrator with
functions necessary to optimize the timing
of high-performance computer systems.
Eight individual drivers, arranged as four
pairs of user-controllable outputs, can
each drive terminated transmission lines
with impedances as low as 50Q while delivering minimal and specified output
skews and full-swing logic levels
(CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of
nine delay or function configurations.
Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with
MHz)
•
•
•
•
•
•
•
Zero input to output delay
50% duty-cycle outputs
Outputs drive SOQ terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 0.5% peak to peak
Compatible with the Pentium@) processor
outputs able to skew up to ±6 time units
from their nominal "zero" skew position.
The completely integrated PLL allows externalload and transmission line delay effects to be canceled. When this "zero
delay" capability of the PSCB is combined
with the selectable output skew functions,
the user can create output-to-output delays of up to ± 12 time units.
Divide-by-two and divide-by-four output
functions are provided for additional flexibility in designing complex clock systems.
When combined with the internal PLL,
these divide functions allow distribution
of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.
C;
o
..J
Logic Block Diagram
Pin Configuration
TEST
PLCC/LCC
FB
VCOAND
TIME UNIT
GENERATOR
REF
4FO
4F1
3FO
3F1
SELECT
INPUTS
(THREE
LEVEL)
0
LL
C')
[>
400
t)
t)
~
0
LL
w z
a: Cl
I-
CJ)
w
I-
u:
C\I
3F1
2FO
4FO
GND
4F1
1F1
401
SKEW
300
1FO
CY7B991
CY7B992
VCCN
VCCN
401
301
SELECT
2FO
2F1
0
CJ)
LL
Vcca
[>
Iu
200
MATRIX
100
400
101
GND
GND
GND
GND
201
100
1FO
1F1
0
C')
0
0C')
z
t)
t)
>
co
LL
z
t)
t)
>
0
C\I
0
0
C\I
76991-2
101
78991-1
Pentium is a trademark of Intel Corporation.
6-11
~tijj~~
CY7B991
CY7B992
PRELIMINARY
Pin Definitions
Description
I/O
Signal Name
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
REF
FB
PLL feedback input (typically connected to one of the eight outputs).
FS
Three-level frequency range select. See Table 1.
1FO, 1F1
Three-level function select inputs for output pair 1 (100, 101). See Table 2.
2FO,2F1
Three-level function select inputs for output pair 2 (200, 201). See Table 2.
3FO,3F1
Three-level function select inputs for output pair 3 (300,301). See Table 2.
Three-level function select inputs for output pair 4 (400, 401). See Table 2.
4FO,4F1
TEST
I
Three-level select. See test mode section under the block diagram descriptions.
100,101
o
o
o
o
Output pair 1. See Table 2.
200,201
300,301
400,401
Output pair 2. See Table 2.
Output pair 3. ~ee Table 2.
Output pair 4. See Table 2.
VCCN
PWR
Power supply for output drivers.
VCCQ
PWR
Power supply for internal circuitry.
GND
PWR
Ground.
times are measured with respect to the REF input assuming that
the output connected to the FB input has Otu selected.
Block Diagram Description
Phase Frequency Detector and Filter
Table 2. Programmable Skew Configurations[l]
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming REF
signal.
.
IFO,2FO,
3FO,4FO
LOW
LOW
- 4tu
LOW
MID
- 3tu
- 6tu
LOW
HIGH
- 2tu
- 4tu
MID
MID
MID
LOW
-ltu
- 2tu
MID
Otu
Otu
Otu
HIGH
+ltu
+ 2t u
+ 2tu
HIGH
LOW
+ 2tu
+ 4t u
+ 4tu
HIGH
MID
+ 3tu
+ 6tu
+ 6tu
HIGH
HIGH
+ 4tu
Divideby4
Inverted
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator
to create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (tu) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table1.
.
Table 1. Frequency Range Select and tu Calculation[l]
fNOM
(MHz)
FS[2]
LOW
Min. Max.
15
tv
1
Approximate
f NOM x N Frequency (MHz) At
where N =
Which tu = 1.0 ns
=
30
44
22.7
MID
25
50
26
38.5
HIGH
40
80
16
62.5
Output Functions
Function Selects
IFl,2Fl,
3Fl,4Fl
lQO,IQl,
2QO,2Ql
3QO,3Ql
4QO,4Ql
Divide by2 Divide by2
- 6tu
.
- 4tu
- 2tu
Note:
1.
For all three-state inputs, HIGH indicates a connection to Vee, LOW
indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry ho~ds an unconnected input to
2.
The level to be set on FS is determined by the "normal" operating frequency (fNOM) of the V co and Time Unit Generator (see Logic Block
Diagram). Nominal frequehcy (fNOM) always appears at lQO and the
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be
fNOM when the output connected to FB is undivided. The frequency
of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is
configured for a frequency multiplication by using a divided output as
the FB input.
Vcd2.
Skew Select MatriX
The skew select matrix is comprised of four independent sections.
Each section has two low-skew, high-fanout drivers (xOO, x01),
and two corresponding three-level. function select (xFO, xF1) inputs. Table 2 below shows the nine possible output functions for
each section as d~termined by the function select inputs. All
6-12
CY7B991
CY7B992
PRELIMINARY
....;J
....;J
co
l!)
I
I
....0
_0
....;J
'2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... >200 rnA
Operating Range
Range
Commercial
Industrial
Militaryl'lJ
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Notes:
3 FB connected to an output selected for "zero" skew (Le., xFl
4.
Indicates case temperature.
= xFO = MID).
6-13
Ambient
Temperature
O°C to +70°C
- 40°C to +85°C
- 55°C to +125°C
Vee
5V ± 10%
5V ± 10%
5V ± 10%
CY7B991
CY7B992
~
-.~
PRELIMINARY
~;;1ICYPRESS
~, SEMICONDUcrOR
Electrical Characteristics Over the Operating Rangd5]
Parameter
VOH
Description
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
Vee = Min.,loH = -16rnA
CY7B991
Max.
Min.
2.4
Vee = Min.,loH=- 40rnA
CY7B992
Max.
Min.
Unit
V
Vee- 0.75
0.45
Vee = Min., IOL = 46 rnA
V
0.45
Vee = Min., IOL =46 rnA
VIR
Input HIGH Voltage
(REF and FB inputs only)
2.0
Vee
Vee
- 1.35
Vee
V
VIL
Input LOW Voltage
(REF and FB inputs only)
- 0.5
0.8
- O.S
1.35
V
VIRH
Three-Level Input HIGH
Voltage (Test, FS, xFn)[6]
Min.
Vee
-IV
Vee
Vee
-IV
Vee
V
VIMM
Three-Level Input MID
Voltage (Test, FS, xFn)[6]
Min. ~ Vee ~ Max.
Ved2500mV
Ved2+
SOOmV
Ved2SOOmV
Ved2+
SOOmV
V
VILL
Three-Level Input LOW
Voltage (Test, FS, xFn)[6]
Min. ~ V ee ~ Max.
0.0
1.0
0.0
1.0
V
IIH
Input HIGH Leakage Current
(REF and FB inputs only)
Vee = Max., VIN = Max.
10
!JA
IlL
Input LOW Leakage Current
(REF and FB inputs only)
Vee = Max., VIN = O.4V
IIHH
Input HIGH Current
(Test, FS, xFn)
VIN = Vee
IIMM
Input MID Current
(Test, FS, xFn)
VIN = Ved2
IILL
Input LOW Current
(Test, FS, xFn)
VIN= GND
- 200
los
Output Short Circuit
Current[7]
Vee = Max., VOUT
= GND (25°C only)
- 250
lecQ
Operating Current Used by
Internal Circuitry
VeeN = V ceQ = Max.,
All Input Selects Open
80
80
rnA
ICCN
Output Buffer Current per
Output Pairl8]
VeCN = VceQ = Max.,
C = SO pf, Z = SOg,
Input Selects Open, fMAX
45
57
rnA
PD
Power Dissiftation per
Output Pair 9]
VeeN = V ceQ = Max.,
C = 50 pf, Z = 50Q,
Input Selects Open, fMAX
171
148[lOJ
mW
~
V ee ~ Max.
10
- 500
- 500
200
- 50
50
- 50
!JA
200
itA
50
!JA
- 200
!JA
rnA
Capacitance[11]
Parameter
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, Vee = 5.0V
Notes:
5. See the last page of this specification for Group A subgroup testing information.
6. These inputs are normally wired to V cc , GND, or left unconnected
(actual threshold voltages vary as a percentage of V cd. Internal termination resistors hold unconnected inputs at V cd2. If these inputs
are switched, the function and timing of the outputs may glitch and the
PLL may require an additional tLOCK time before all datasheet limits
are achieved.
7. Tested one output at a time, output shorted for less than one second,
less than 10% duty cycle. Room temperature only.
8. ICCN can be approximated by the following expressions:
CY7B991:
ICCN = (2 + O.l1F) + [«835 - 3F)/Z) + (.0022FC)]N
CY7B992:
ICCN = (1.5+ 1.7F) + [«1160 - 2.8F)/Z) + (.0025FC)JN
Where
Unit
pF
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC=F * C
9. Power dissipation can be approximated by the following expressions:
CY7B991:
PD = (11 + 0.61F) + [«1550 - 2.7F)/Z) + (.0125FC)]N
CY7B992:
PD = (8.25+ 0.94F) + [«700 + 6F)/Z) + (.017FC)]N
See note 8 for variable definition.
10. CMOS output buffer current and power dissipation specified at
50-MHz reference frequency.
.
11. Applies to REF and FB inputs only. Tested initially and after any design
or process changes that may affect these parameters.
6-14
CY7B991
CY7B992
PRELIMINARY
AC Test Loads and Waveforms
5V
I
~
CL
-=-
R1
R1 = 130
R2 = 91
CL = 50 pF (CL = 30pF for -5 devices)
(Includes fixture and probe capacitance)
R2
-=-
78991-4
78991-5
TTL Input Test Waveform (CY7B991)
TTL AC Test Load (CY7B991)
Vee
~
I
CL
-=-
R1
R1 = 100
R2 = 100
CL = 50 pF (CL = 30pF for -5 devices)
(Includes fixture and probe capacitance)
R2
78991-6
78991-7
CMOS Input Test Waveform (CY7B992)
CMOS AC Test Load (CY7B992)
Switching Characteristics Over the Operating Rangel2, 12]
CY7B992-S
CY7B991-S
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
Max.
Min.
Max.
Unit
15
30
15
30
MHz
25
50
25
40
80
40
50
80l13]
Min.
= LOWll,2J
= MID[I,2]
FS = HIGH[I,2]
FS
FS
'!Yp.
'!Yp.
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
tu
REF Pulse Width LOW
5.0
5.0
ns
Programmable Skew Unit
tUE
Programmable Skew Unit Error l14 ]
tSKEWPR
Zero Output
XQ1)[15,16
tSKEWO
Zero Output Skew (All Outputs)lI5, 17]
tSKEWI
Output Skew ~Rise-Rise, Fall-Fall, Same Class
Outputs)[15,18
tSKEW2
See Table 1
0.0
±0.5
0.0
±0.5
ns
0.1
0.25
0.1
0.25
ns
0.25
0.5
0.25
0.5
ns
0.6
0.7
0.6
0.7
ns
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[15, 18]
0.6
1.2
0.6
1.2
ns
tSKEW3
Output Skew &Rise-Rise, Fall-Fall, Different
Class Outputs) 5,18]
0.6
1.0
0.6
1.0
ns
tSKEW4
Output Skew (Rise-Fall Nominal-Divided,
Divided-Inverted)[15,18 j
0.6
1.3
0.6
1.3
ns
tSKEW5
tpD
Device-to-Device Skew[19]
0.2
ns
- 0.5
0.0
+0.5
- 0.5
0.0
+0.5
ns
- 1.0
0.0
+1.0
- 1.0
0.0
+1.0
ns
ns
tODCV
tpWH
tpWL
tORISE
tOFALL
tLOCK
tJR
Matched-Pair
Skew
(XQO,
0.2
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation l2O ]
Output HIGH Time Deviation from 50%[21,24]
2.5
3.5
Output LOW Time Deviation from 50%[21, 24]
Output Rise Timel 21 , 25]
3
3.5
ns
2.5
ns
Output Fall TimelL1 , 25]
PLL Lock Time l22]
0.15
1.0
0.15
1.0
Cycle-to-Cycle Output Jitter, Peak to Peak[23]
6-15
1.5
0.5
2.0
1.5
0.5
2.0
2.5
ns
0.5
0.5
ms
0.5
0.5
%
•
t€~i~PRFSS
CY7B991
CY7B992
PRELIMINARY
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel 2, 12] (continued)
CY7B991-7
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
= LOWll,:lJ
FS = MIDll,:lJ
FS = HlGHll,2J
FS
1YP.
CY7B992-7
Max.
Min.
Max.
Unit
15
30
15
30
MHz
25
50
.25
50
40
80
40
50
Min.
'tYp.
tRPWH
tRPWL
REF Pulse Width HIGH
5.0
5.0
ns
REF Pulse Width LOW
5.0
5.0
ns
tu
Programmable Skew Unit
tUE
Programmable Skew Unit Error l14J
0.0
±0.7
0.0
±0.7
ns
tSKEWPR
Zero Ouwut Matched-Pair Skew (XQO,
XQ1)[15,1 J
.
0.1
0.25
0.1
0.25
ns
tSKEWO
Zero Output Skew (All Outputs)lIS, 17J
0.3
0.75
0.3
Output Skew ~Rise- Rise, Fall-Fall, Same Class
Outputs )[15, 1 ]
0.6
1.0
0.6
0.75
1.0
ns
tSKEWI
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [15, 18]
1.0
1.5
1.0
1.5
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs )[15, 18]
0.7
1.2
0.7
1.2
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [15, 18] .
Device-to-Device Skewl 19J
1.2
1.7
1.2
1.7
ns
- 0.7
0.0
+0.7
- 0.7
0.0
+0.7
ns
- 1.2
0.0
+1.2
- 1.2
0.0
+1.2
ns
5.5
ns
tSKEW5
tpo
toocv
tpWH
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variationl:lUJ ;
See Table 1
0.2
Output HIGH Time Deviation from 50%l21, 24 J
ns
0.2
3
ns
Output LOW Time Deviation from 50%l:lI,:l4J
Output Rise Timel 21 , 25J
5.5
ns
tORISE
0.15
1.5
2.5
0.5
3.0
5.0
ns
tOFALL
Output Fall Timel 21 , 25J
0.15
1.5
2.5
0.5
3.0
5.0
tLOCK
tJR
PLL Lock TimeluJ
tPWL
3.5
0.5
Cycle-to-Cycle OutputJitter, Peak to Peakl:l3J
0.5
Notes:
12. Test measurement levels for the CY7B991 are TTL levels (1.5V to
1.5V). Test measurement levels for the CY7B992 are CMOS levels
(Ved2 to Ved2). Test conditions assume signal transition times of 2
ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
13. Except as noted, all CY7B992-5 timing parameters are specified to
SO-MHz with a 30-pF load.
14. tUE is a measure of the timing error from tu as calculated in Table 1.
The major contributors to this error include output edge variations,
cross talk, and load-induced variations between package pins and between signal lines external to the chip. tUE is not cumulative across
multiple tu delays.
15. SKEW is defined as the time between the earliest and the latest output
transition among all outputs for which the same tu delay has been selectedwhenallareloadedwith50pFandterminatedwith50Qt02.06V
(CY7B991) or Ved2 (CY7B992).
16. tSKEWPR is defined as the skew between a pair of outputs (XQO and
XQ1) when all eight outputs are selected for Otu.
17. tSKEWO is defined as the skew between outputs when they are selected
for Otu. Other outputs are divided or inverted but not shifted.
IS. There are three classes of outputs: Nominal (multiple oftu delay), Inverted (4QO lind 4Q1 only with 4FO = 4F1 = HIGH), an.d Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
19. tSKEW5 is the output-to-output skew between the outputs used as the
FB input of two or more devices operating under the same conditions
20.
21.
22.
23.
24.
25.
6-16
0.5
0.5
ns
.
ms
%
(Vee, ambient temperature, air flow, etc.). The maximum variation
between two pins on different parts is tSKEW5 plus the skews associated
with each part.
tODeY is the deviation of the output from a 50% duty cycle. Output
pulse width variations are included in tSKEW2 and tSKEW4 specifications.
Specified with outputs loaded with 30 pF for the CY7B99X - 5 devices
and 50 pF for the CY7B99X -7 devices. Devices are terminated
through 50Q to 2.06V (CY7B991) or Ved2 (CY7B992).
tLoeK is the time that is required before synchronization is achieved.
This specification is valid only after Vee is stable and within normal operating limits. This parameter is measured from the application of a
new signal or frequency at REF or FB until tpD is within specified limits.
Tested initially and after any design or process changes that may affect
these parameters.
tpWH is measured at 2.0V for the CY7B991 and O.S Vee for the
CY7B992. tpWLis measured at O.SV for. the CY7B991 and 0.2 Vee for
the CY7B992.
.
tORISEand tOFALLmeaSured between O.SV and2.0V for the CY7B991
or O.SVee and 0.2Vee for the CY7B992.
_
E:.~
PRELIMINARY
..... CYPRESS
~.,
CY7B991
CY7B992
SEMICONDUcrOR
AC Timing Diagrams
REF
FB
Q
OTHERQ
Iu
a
9
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
N*tu
~
Q
:J.
N*tu
-
~~
tUE ~
~~tUE
tUE -~ ~
-
~
t--
¥~ tUE
II
OTHER Q (Ntul
1\
tUE l-
-
6-17
t--
foil-
78991-8
_
df.:~
. •v
~.,
CY7B991
CY7B992
PRELIMINARY
CYPRF.SS
SEMICONDUCTOR
Operational Mode Descriptions
REFJt...hJL
I
I
I
SySTEM _ _- - - i
CLOCK
LOAD
4FO
4F1
3FO
3F1
2FO
2F1
300
301
1FO
1F1
100
101-
200
201
TEST
~~'-I--LO-A-D----I
LENGTH L1 = L2 = L3 = L4
Zo
78991-9
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
Figure 2 shows the PSCB configured as a zero-skew clock buffer.
In this mode the 7B991/992 can be used as the basis for a lowskew clock distribution tree. When all of the function select inputs (xFO, xFl) are left open, the outputs are aligned and may
each drive a terminated transmission line to an independent load.
SYSTEM
CLOCK
The FB input can be tied to any output in this configuration and
the operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design.
LOAD
4FO
4F1
3FO
3F1
'-_------1 2FO
2F1
~--__I1FO
1F1
300
301
LOAD
200
201
100
".. ,.L, "..
101 __ ::.I:U:U:L...
_____ L4
TEST
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
~
LOAD
f z~'-------'
78991-10
Figure 3. Programmable-Skew Clock Driver
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between outputs, the PSCB can be programmed to stagger the timing of its
outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted
over a wide range in small increments with the appropriate strapping ofthe function select pins. In this configuration the 4QO output is fed back to FB and configured for zero skew. The other
three pairs of outputs are programmed to yield different skews
relative to the feedback. By advancing the clock signal on the
longer traces or retarding the clock signal on shorter traces, all
loads can receive the clock pulse at the same time.
In this illustration the FB input is connected to an output with
O-ns skew (xFl, xFO = MID) selected. The internal PLL synchro-
nizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (tv) when using
an output selected for zero skew as the feedback. A wider range
of delays is possible if the output connected to FB is also skewed.
Since "Zero Skew", +tv, and - tv are defined relative to output
groups, and since the PLL aligns the rising edges of REF and FB,
it is possible to create wider output skews by proper selection of
the xFn inputs. For example a + 10 tv between REF and 3Qx can
be achieved by connecting 1QO to FB and setting IFO = IFI =
GND, 3FO = MID, and 3Fl = High. (Since FB aligns at - 4 tv
and 3Qx skews to +6 tv, a total of + 10 tv skew is realized.)
Many other configurations can be realized by skewing both the
output used as the FB input and skewing the other outputs.
6-18
CY7B991
CY7B992
PRELIMINARY
REF~
, , ,
FB
REF
FS
4FO
4F1
400
401
3FO
3F1
1J1..I1..r
, , ,
2FO
2F1
300
301
200
201
1FO
1F1
100
101
i.Ii..rt.r
, , ,
TEST
' , ,
l.nIV
, , ,
,
78991-11
Figure 4. Iuverted Output Connections
Figure 4 shows an example of the invert function of the PSCB. In
this example the 400 output used as the FB input is programmed
for invert (4FO = 4F1 = HIGH) while the other three pairs of
outputs are programmed for zero skew. When 4FO and 4F1 are
tied high, 400 and 401 become inverted zero phase outputs. The
PLL aligns the rising edge of the FB input with the rising edge of
the REF. This causes the 10, 20, and 30 outputs to become the
"inverted" outputs with respect to the REF input. By selecting
which output is connect to FB, it is possible to have 2 inverted
and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need
for more (or fewer) inverted outputs. 10,20, and 30 outputs
can also be skewed to compensate for varying trace delays independent of inversion on 40.
Figure 5 illustrates the PSCB configured as a clock multiplier. The
300 output is programmed to divide by four and is fed back to
FB. This causes the PLL to increase its frequency until the 300
and 301 outputs are locked at 20 MHz while the lOx and 20x
outputs run at 80 MHz. The 400 and 401 outputs are programmed to divide by two, which results in a 40-MHz waveform
at these outputs. Note that the 20- and 40-MHz clocks fall simultaneously and are out of phase on their rising edge. This will al-
low the designer to use the rising edges of the V2 frequency and V4
frequency outputs without concern for rising-edge skew. The
200,201,100, and 101 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80-MHz operation because that is the frequency
of the fastest output.
Figure 6 demonstrates the PSCB in a clock divider application.
200 is fed back to the FB input and programmed for zero skew.
30x is programmed to divide by four. 40x is programmed to divide by two. Note that the falling edges of the 40x and 30x outputs are aligned. This allows use of the rising edges of the Vz frequency and Y4 frequency without concern for skew mismatch. The
lOx outputs are programmed to zero skew and are aligned with
the 20x outputs. In this example, the FS input is grounded to
configure the device in the 15- to 30-MHz range since the highest
frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the
30x and 40x outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output allows the system designer to clock different subsystems
on opposite edges, without suffering from the pulse asymmetry
typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be
aligned within the skew spec.
The divided outputs offer a zero-delay divider for portions of the 0
system that need the clock to be divided by either two or four,
and still remain within a narrow skew of the "lX" clock. Without 0
.....
this feature, an external divider would need to be added, and the
propagation delay of the divider would add to the skew between
the different clock signals.
These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute
a low-frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the
clock driver. The PSCB can perform all of the functions described above at the same time. It can multiply by two and four or
divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs.
I
C3
REF~
20 MHz
20 MHz
FB
REF
FS
4FO
4F1
3FO
3F1
2FO
2F1
1FO
1F1
TEST
400
401
300
301
200
201
100
101
FB
REF
FS
~
1---rl-fI......
2FO
2F1
1FO
1F1
100
101
..flIL[l..f1.I1
3FO
3F1
'20 MHz
~
J1..rLrtJ1JUL
,
' ,
'10MHz
400
401
300
301
200
201
4FO
4F1
'40 MHz
'
,
,
,
'5 WlHz
I
I
:20)'.1Hz
,
I
,
, ,
,
TEST
'78991.12
78991-13
Figure S. Frequency Multiplier with Skew Connections
Figure 6. Frequency Divider Connections
6-19
CY7B991
CY7B992
PRELIMINARY
REF~
,
'
SO-MHz
20-MHz
DISTRIBUTION
CLOCK
4FO
4F1
3FO
3F1
2FO
2F1
___- - - t 1FO
1F1
TEST
400
401
300
301
200
201
100
101
,
,
,
'
,
I
I
I
I
•
~INVERTED
LOAD
~
-flIt1'll1-I1J1------:
'
:
'
.,
,
",
I
I
,
,
I
:
2Q-MHz
SO-MHz
ZERO SKEW
Zo
~========~
f--11....---...1
LOAD
Zo
I
~---, , , , "
aO-M"HZ---------,I
,
,
:'
SKEWED 4 ns
LOAD
f~"'-----'
78991-14
Figure 7. Multi-Function Clock Driver
REF
LOAD
SYSTEM
CLOCK
4001-...L..-+
401
3001---+
301
LOAD
200 t-"--+201
1001---_"101
Figure 8. Board-to-Board Clock Distribution
Figure 8 shows the CY7B991/992 connected in series to construct
a zero-skew clock distribution tree between boards. Delays of the
downstream clock buffers can be programmed to compensate for
the wire length (Le., select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approxi-
78991-15
mating a zero-delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering
characteristics of the PLL filter. It is not recommended that more
than two clock buffers be connected in series.
6-20
~
~~
PRELIMINARY
~=CYPRESS
~, SEMICONDUcrOR
CY7B991
CY7B992
Ordering Information
Accuracy
(ps)
500
Ordering Code
J65
32-Lead Plastic Leaded Chip Carrier
CY7B991-5LC
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package 1Ype
Ordering Code
CY7B991-7JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7B991-7LC
L55
32-Pin Rectangular Leadless Chip Carrier
CY7B991-7JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7B991-7L1
L55
32-Pin Rectangular Leadless Chip Carrier
CY7B991-7LMB
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package 1Ype
Accuracy
(ps)
500
Ordering Code
CY7B992-5JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7B992-5LC
L55
32-Pin Rectangular Leadless Chip Carrier
Package
Name
Package 1Ype
Accuracy
(ps)
750
Package 1Ype
CY7B991-5JC
Accuracy
(ps)
750
Package
Name
Ordering Code
32-Lead Plastic Leaded Chip Carrier
CY7B992-7JC
J65
CY7B992-7LC
L55
32-Pin Rectangular Leadless Chip Carrier
CY7B992-7JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7B992 -7L1
L55
32-Pin Rectangular Leadless Chip Carrier
CY7B992-7LMB
L55
32-Pin Rectangular Leadless Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
1,2,3
VOL
VIH
1,2,3
VIL
VIHH
1,2,3
1,2,3
VIMM
VILL
IIH
Commercial
Operating
Range
Commercial
Industrial
Military
Operating
Range
Commercial
Operating
Range
Commercial
Industrial
Military
Switching Characteristics
Subgroups
VOH
Operating
Range
Parameter
Subgroups
tREF
9,10,11
tRPWH
9,10,11
tRPWL
tu
9,10,11
tUE
9,10,11
9,10,11
1,2,3
tSKEWPR
tSKEWO
9,10,11
9,10,11
1,2,3
tSKEWl
9,10,11
1,2,3
tSKEW2
IlL
IIHH
1,2,3
1,2,3
tSKEW3
tSKEW4
9,10,11
9,10,11
IIMM
1,2,3
IILL
lOS
1,2,3
tSKEW5
tpD
ICCQ
ICCN
PD
1,2,3
1
1,2,3
1,2,3
tODCY
tpWH
9,10,11
tpWL
9,10,11
9,10,11
tQRISE
1,2,3
tQFALL
Document #: 38-00188-B
tLOCK
6-21
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
•
(,)
C;
o...I
CY7C9101
CYPRESS
SEMICONDUCTOR
Features
• Fast
- CY7C9101-30 has a 30-ns (max.)
clock cycle (commercial)
- CY7C9101-35 has a 35-ns (max.)
clock cycle (military)
• Low power
- Icc (max. at 10 MHz) = 60 rnA
(commercial)
- Icc (max. at 10 MHz) = 85 rnA
(military)
• Vee margin of 5V ±10%
• All parameters guaranteed over
commercial and military operating
temperature range
• Replaces four 2901s with carry lookahead logic
• Eight-function ALU performs three
arithmetic and five logical operations
on two 16-bit operands
CMOS 16-Bit Slice
• Infinitely expandable in 16-bit increments
• Four status flags: carry, overflow, negative, zero
• Capable of withstanding greater than
2001V static discharge voltage
• Pin compatible and functional equivalent to AM29CIOl
Functional Description
The CY7C9101 is a high-speed, expandable, 16-bit-wide ALU slice that can be
used to implement the arithmetic section
of a CPU, peripheral controller, or programmable controller. The instruction set
of the CY7C9101 is basic, yet so versatile
that it can emulate the ALU of almost any
digital computer.
The CY7C9101, as shown in the logic
block diagram, consists of a 16-word by
16-bit dual-port RAM register file, a 16-bit
Logic Block Diagram
ALU, and the necessary data manipulation
and control logic.
The function performed is determined by
9-bit instruction word (18 to 10), which is
usually input via a micro-instruction register.
The CY7C9101 is expandable in 16-bit increments, has three-state data outputs as
well as flag outputs, and can implement either a full look-ahead carry or a ripple
carry.
The CY7C9101 is a pin-compatible, functional equivalent for the Am29C101 with
improved performance. The 7C9101 replaces four 2901s and includes on-chip
carry look-ahead logic.
Fabricated in an advanced 1.2-micron
CMOS process, the CY7C9101 eliminates
latch-up, has ESD protection greater than
2000Y, and achieves superior performance
with low power dissipation.
Pin Configurations
Top View
14
15
00
A (READ)
ADDRESS
B (READIWRITE)
ADDRESS
D15-0
(DIRECT
DATA-IN)
J5
13
Q15
RAM15
G
Aa
Cn +IS
OVR
A2
F15
Y15
Ao
AI
Y14
Y13
Y12
Yll
DIs
D14
D13
D12
Dll
Yl0
Yg
D10
Dg
Ya
GND
Vee
or:
Y7
Ys
Ys
Y4
Y3
Y2
Yl
Yo
F=O
CIN
12
11
10
la
17
Da
D7
Ds
Ds
D4
D3
D2
Dl
Do
Bo
Bl
B2
Sa
CP
RAMo
00
Is
7C9101-1
7C91 01-2
Y15 -0
DATA OUT
6-22
5f?:~
CY7C9101
Pin Configurations (continued)
PGA
Top View
51
Y1
53
F=O
52
Yo
55
12
Vss
39
Yg
36
38
Y10
Y12
Y13
30
31
OVR
28
26
13
22
Aa
23
RAM15
20
66
Al
Bl
70
25
24
64
~
27
15
015
Ba
•
'G:
14
62
69
29
"P
RAMo
01
33
Y15
Gn +1!
60
68
Y14
32
F15
Is
00
34
35
37
Yl1
58
67
So
41
43
Vss
40
Ys
Is
65
B:!
NG
56
63
GP
45
Y7
42
44
rn:
11
61
00
47
Y5
46
Ys
54
59
17
49
Y3
48
Y4
Gn
57
10
50
Y2
71
Da
72
04
73
05
74
Os
75
07
77
79
NG
76
DS
78
80
Og
Vee
Vee
81
010
82
011
83
D12
84
013
19
18
015
Io
21
~
An
(;
17
9
014
7G9101-3
LCC/PLCC
Top View
68 6766 65 64 63 62 61
60
59
68
Y12
57
Yl1
56
Yl0
Yg
55
54
53
52
Vee
51
Y14
Y13
YS
GNO
GND
or:
50
49
Y7
48
Y6
Ys
Y4
Y3
Y2
Yl
7G9101-4
Selection Guide
Minimum Clock Cycle (ns)
Commercial
Military
Maximum Operating Current
at 10 MHz (rnA)
Commercial
Military
CY7C9101-30
CY7C9101-35
30
35
60
85
6-23
CY7C9101-40
CY7C9101-45
40
45
60
85
~ :;~PRESS
~.,
CY7C9101
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 65°C to +150°C
Ambient Thmperature with
Power Applied ....................... - 55°C to +125°C
Supply Voltage to Ground Potential . . . . . . .. - O.5V to + 7.0V.
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to +7.0V
DC Input Voltage ....................... - 3.0V to +7.0V
Output Current into Outputs (LOW) ............... 30 rnA
Static Discharge Voltage ........................ > 2001 V
(Per MIL-STD-883 Method 3015)
Latch-Up Current (Outputs) .................... >200 rnA
Operating Range
Range
Ambient
Temperature
Vee
Commercial
O°Cto +70°C
5V ±1O%
- 55°C to +125°C
5V ±1O%
Military[lj
Note:
1. TA is the "instant on" case temperature.
Pin Definitions
Description
Signal
Name
Ao
RAM Address A. This 4-bit address word selects one of the 16 registers in the register file
for output on the (internal) A port.
015
RAM15
(cont.)
B3 - Bo
RAM Address B. This 4-bit address word selects one of the 16 registers in the register file
for output on the (internal) B port. When data
is written back to the register file, this is the
destination address.
Signal
Name
A3 -
I/O
18 - 10
DI5- D O
Y15- Yo
OE
CP
015
RAM 15
0
I/O
Description
I/O Output Mode: When the destination code on
lines 16, 7, 8 indicates a left shift (UP) operation, the three-state outputs are enabled and
the MSB of the 0 register is output on the 015
pin and likewise, the MSB of the ALU output
(FIS) is output on the RAM15 pin.
Input Mode: When the destination code indicates a right shift (DOWN), the pins are the
data inputs to the MSB of the 0 register and
the MSB of the RAM, respectively.
Instruction Word. This 9-bit word is decoded to
determine the ALU data sources (10, 1, 2), the
ALU operation (13,4,5), and the data to be written to the 0 register or register file (16, 7, 8)'
00
RAMo
Direct Data Input. This 16-bit data word may
be selected by the 10,1, 2 lines a,s an input to
theALU.
Cn
I
Carry In. The carry in to the internal ALU.
C n + 16
0
Carry Out. The carry out from the internal
a,I>
0
Carry Generate, Carry Propagate. Outputs
from the ALU that may be used to perform a
carry look-ahead operation over the 16 bits of
theALU.
OVR
0
Overflow. This signal is the logical exclusiveOR of the carry in and the carry out ofthe
MSB of the ALU. This indicates when the resuIt of the ALU operation has exceeded the
capacity of the ALU's two's complement number range.
F=O
0
Zero Detect. Open drain output that goes
HIGH when the data on outputs (F15 - Fo) are
all Ww. It indicates that the result of an ALU
operation is zero (positive logic assumed).
F15
0
Sign. The MSB of the ALU output.
Data Output. These are three-state data output lines that, when enabled, output either the
output of the ALU or the data in the A latch,
as determined by the code on the 16, 7, 8 lines.
I/O These two lines are bidirectional and function
similarly to the 015 and RAM 15 lines. The 00
and RAMo lines are the LSB of the 0 register
and the RAM.
ALU.
Output Enable. This is an active LOW input
that controls the Y15 - Yo outputs. A HIGH
level on this signal places the output drivers at
the high-impedance state.
Clock. The LOW level of CP is used to write
data to the RAM register file. A HIGH level
of CP writes data from the dual-port RAM to
the A and B latches. The operation of the 0
register is similar; data is entered into the master latch on the LOW level of CP and transferred from master to slave during CP =
HIGH.
I/O These two lines are bidirectional and are controlled by 16, 7, 8. They are three-state output
drivers connected to the TTL-compatible
CMOS inputs.
6-24
~
_~PRFSS
~,
CY7C9101
SEMICONDUCTOR
Description of Architecture
General Description
The CY7C9101 general block diagram is shown on the first page of
this datasheet, in the Logic Block Diagram section. Detailed block
diagrams (Figures 1 through 3) show the operation of specific sections as described below. The device is a 16-bit slice consisting of a
register file (16-word by 16-bit dual-port RAM), the ALU, the Q
register, and the necessary control logic. It is expandable in 16-bit
increments.
Register File
The dual-port RAM is addressed by two 4-bit address fields (A3 Bo) that cause the data to simultaneously appear at the A
or B (internal) ports. If the A and B addresses are the same, the
data at the A and B ports will be identical.
Data to be written to RAM is applied to the D inputs ofthe 7C9101
and is passed (unchanged) through the ALU to the RAM location
Ao, B3 -
specifiedbytheB-addressword. New data is written into the RAM
by specifying a B address while RAM write enable (RAM EN) is
active and the clock input is LOW. RAM EN is an internal signal
decoded from the signals 16, 7, 8. As shown in Figure 1, each of the
16 RAM inputs is driven by a three-input multiplexer that allows
theALU output (F15 - Fo) to be shifted one bit position to the left
or right, or not shifted at all. The RAM 15 and RAMo I/O pins are
also inputs to the 16-bit, 3-input multiplexer.
During the left-shift (upshift) operation, the RAM 15 output buffer
and RAMo input multiplexer are enabled. For the right-shift
(downshift) operation, the RAMo output buffer and the RAM15
input multiplexer are enabled.
The A and B outputs ofthe RAM drive separate 16-bit latches that
are enabled when the clock is HIGH. The outputs of the A latch go
to the three multiplexers that feed the two ALU inputs (R 15 - Ro
and SIS - So) and the chip output (Y 15 - Yo). The B latch outputs
are directed to the multiplexer that feeds the S input to the ALU.
I
(,)
ao
•
...I
18
17
•••
I
RAM SHIFTER
(16x3-IN MUX)
16
•••
D2
D1
Do
B3 }
B2
B1
WE
B15 -
So
BADDRESS
Bo
7C91 01-5
Figure 1. Register File
6-25
=:: ;~PRFSS
~
,
CY7C9101
SEMICONDUCTOR
to a source operand consisting of all zeros. The Rand S ALU
source multiplexers are configured to allow eight pairs of combinations of A, B, D, 0, and "0" to be selected as ALU input operands.
Description of Architecture (continued)
Q Register
The Q register is mainly intended foruse as a separate working register for multiplication and division routines. It may also function
as an accumulator or temporary storage register. Sixteen masterslave latches are used to implement the register. As shown in Figure 2, the O-registerinputs are driven by the outputs ofthe a shifter (sixteen 3-input multiplexers, under the control of 16, 7, 8). The
function of the register input multiplexers is to allow the register to be shifted either left or right, or loaded with the ALU output
(FlS - Fo). The 015 and 00 pins (I/O) function similarly to the
RAM 15 and RAMo pins described earlier. Data is entered into the
master latches when the clock is LOW and is transferred to the
slave (output) at the clock LOW-to-HIGH transition.
The ALU input functions, which are controlled by 13, 4, 5, are
shown in Table 2. Carry look-ahead logic is resident on the 7C9101,
using the ALU carry in (Cn ) input and the ALU carry propagate
(P), carry generate (G), carry out (Cn + 16), and overflow outputs
to implement carry look-ahead arithmetic and determine if arithmetic overflow has occurred. Note that the carry in (Cn) signal affects the arithmetic result and internal flags only; it has no effect on
the logical operations.
ALU (Arithmetic Logic Unit)
o
a
a
a
The ALU can perform three arithmetic and five logical operations
on the two 16-bit input operands, Rand S. The R input multiplexer
selects between data from the RAM A port and data at the external
data input, DIS - Do. The S input multiplexer selects between data
from the RAM A port, the RAM B port, and the register. The R
and S multiplexers are controlled by the 10, 1,2 inputs as shown in
Table 1. The Rand S input multiplexers each have an "inhibit capability," offering a state where no data is passed. This is equivalent
a
a
The ALU source operands and ALU function matrix are summarized in Table 4 and separated by logic operation or arithmetic operation in Tables 5 and 6, respectively. The 10, h 2 lines select eight
pairs of source operands and the 13, 4, slines select the operation to
be performed.
• ••
o
,,~
......
Control signals 16,7,8 route the ALU data output (F15 - "!'o) to the
RAM, the register inputs, and the Y outputs as shown III Table 3.
The ALU result MSB (FlS) is output so the user may examine the
sign bit without needing to enable the three-state outputs. The F =
output, used for zero detection, is HIGH when all bits of the F
output are LOW. It is an open drain output that may be wire OR~d
across multiple 7C91 01 processor slices. Figure 3 shows a block diagram of the ALU.
Fo
L~
.....00
~
>-
..
ALU
DESTINATION
DECODE
o SHIFTER
-- - - - - - - -
------- - -
~•••
I'
~-0~
~-0~
--
~~ "
'-
~-0~ MUX MUX
!--- ---- ---- ---------- - - - - - - - I
~-0~
- - - -~-:
3-IN
3-IN
I
I
(16 x 3-IN MUX)
D 15
QEN
CP
D14
D 13
>- t>
015
• ••
D2
D1
Do
Q REGISTER
Q14
013
012
• ••
03
Q2
01
00
...........--
·..
Figure 2. Q Register
6-26
7C9101-6
---=-,~PRFSS
CY7C9101
·
SEMICONDUCTOR
Description of Architecture (continued)
Conventional Addition and Pass-Increment/Decrement
Subtraction
When the carry in is HIGH and either a conventional addition or a
PASS operation is performed, one (1) is added to the result. If the
DECREMENT operation is performed when the carry in is LOW,
the value of the operand is reduced by one. However, when the
same operation is performed when the carry in is HIGH, it nullifies
the DECREMENT operation so that the result is equivalent to the
PASS operation. In logical operations, the carry in (Cn) will not affect the ALU output.
Recall that in two's complement integer coding - 1 is equal to all
ones, and that in one's complement integer coding zero is equal to
all ones. To convert a positive integer to its two's complement (negative) equivalent, invert (complement) the number and add 1 to it;
i.e., TWC = ONC + 1. In Table 6 the symbol - 0 represents the
two's complement of 0, so the one's complement of 0 is then - 0
Table 1. ALU Source Operand Control
Table 2. ALU Function Control
ALU Source
Operands
Micro Code
Mnemonic
12
11
AO
AB
ZO
ZB
ZA
DA
DO
DZ
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
10
L
H
L
H
L
H
L
H
-1.
Octal
Code
0
1
2
3
4
5
6
7
MicroCode
Mnemonic
R
S
A
A
0
B
0
0
0
0
B
A
A
D
D
D
ADD
SUBR
SUBS
OR
AND
NOTRS
XOR
XNOR
0
Is
L
L
L
L
H
H
H
H
14
L
L
H
H
L
L
H
H
13
L
H
L
H
L
H
L
H
Octal
Code
0
1
2
3
4
5
6
7
ALU
Function
Symbol
RPlus S
SMinusR
RMinusS
RORS
RANDS
RANDS
RXORS
RXNORS
R+S
S-R
R-S
RVS
RJ\S
RJ\S
R¥S
R¥S
0
Table 3. ALU Destination Control
Micro Code
RAM Function
RAM Shifter
Q-Reg. Function
Q Shifter
y
17
16
Octal
Code
L
L
0
L
L
H
1
X
None
X
F.O
None
F
X
X
X
X
L
H
L
2
None
F.B
X
None
A
X
X
X
X
RAMF
L
H
H
3
None
F.B
X
None
F
X
X
X
X
RAMOD
H
L
L
4
DOWN
F/2.B
DOWN
0/2.0
F
Fo
IN15
00
IN 15
RAMD
H
L
H
F/2.B
X
None
F
Fo
IN 15
00
X
H
H
L
5
6
DOWN
RAMOU
UP
2F.B
UP
20.0
F
INo
F15
INo
015
RAMU
H
H
H
7
UP
2F.B
X
None
F
INo
F15
X
015
Mnemonic
OREG
Is
L
NOP
RAMA
Shift
Load
Shift
Load
Output
RAMo
X
None
None
F
X
RAMlS
X
Qo
QlS
X
X
x = Don't care,. Electrically, the input shift pin is a TIL input internally connected to a three-state output that is in the high-impedance state.
A = Register addressed by A inputs.
B = Register addressed by B inputs.
UP is toward MSB, DOWN is toward LSB.
6-27
II
(.)
ao
...I
&;~PRFSS
~,
CY7C9101
SEMICONDUCTOR
Description of Architecture (continued)
•••
•••
Do
80
, . . . . . - - t _ - - - - _ t _ - - + _ - - - - - - 015
A15-1_~--+_-----_r---~_.----~-_4_rr------~---------++----~---t---------- 014
•
A14-._r-~-_4------+__.~~~--_4_r-~+_--~
A1
•
•
•
-._t_t_-+--~~~--~-+__r_4~--_t_t_,
~-.~~--+-~-+--~-----+~~+-~--~
12
11
10
R1
Ro
S14
S15
16-81T ARITHMETIC lOGIC UNIT (AlU)
F15
F14
• ••
•••
S1
Fo
F1
Cn
18
AlU
DESTINATION
DECODE
17
Ie
• ••
DE
Y15
Y14
7C91 01-7
• ••
Y1
Yo
Figure 3. ALU
Table 4. Source Operand and ALU Function Matrix
1210 Octal
ALU Source
Octal
1543 ALU Function
0
Cn = L
Rplus S
Cn=H
1
Cn = L
SminusR
Cn=H
2
3
Cn=L
Rminus S
Cn=H
RORS
4
RANDS
5
RANDS
6
REX-ORS
7
REX-NORS
0
1
A
3
0
2
0
4
5
6
7
D
D
D
0
Q
B
Q
B
0
A
A
Q
A+Q
A+B
Q
B
A
D+A
D+Q
D
D+Q+ 1
Q-D-l
D+1
-D -1
A
A+Q+ 1
Q-A-l
A+B+l
B-A-l
Q+1
Q-l
B+l
B-1
A+ 1
A-I
D+A+ 1
A-D-l
Q-A
A-Q-l
B-A
A-B-l
Q
-Q-l
B
-B-1
A
-A-l
A-D
D-A-l
Q-D
D-Q-l
-D
D -1
A-Q
AVQ
A/l.Q
A/l.Q
A¥Q
A¥Q
A-B
AVB
A/l.B
A/l.B
A¥B
A¥B
-Q
Q
-B
B
-A
A
D-A
DVA
D/l.A
D/l.A
D¥A
D¥A
D-Q
DVQ
D/l.Q
D/l.Q
D¥Q
D¥Q
D
D
0
0
0
Q
Q
Q
B
B
B
A
A
A
+ = Plus; - = Minus; V = OR; 1\ = AND; ¥ = EX-OR
6-28
0
0
D
D
e:~
=-=
-=
~.F'
CY7C9101
CYPRESS
SElvnCONDUcrOR
Description of Architecture (continued)
Table 5. ALU Logic Mode Functions
Table 6. ALU Arithmetic Mode Functions
Octal
1543,1210
Group
Function
40
41
45
46
AND
AI\Q
AI\B
DI\A
DI\Q
30
31
35
36
OR
AVQ
AVB
DVA
DVQ
60
61
65
66
XOR
A¥Q
A¥B
D¥A
D¥Q
70
71
75
76
XNOR
A¥Q
A¥B
D¥A
D¥Q
72
73
74
77
INVERT
62
63
64
67
PASS
32
33
34
37
PASS
42
43
44
47
"ZERO"
0
0
0
0
50
51
55
56
MASK
AI\Q
AI\B
DI\A
DI\Q
Octal
1543,1210
Q
B
A
D
Q
B
A
D
Q
B
A
D
6-29
Cn
= 0 (LOW)
Group
Cn
= 1 (HIGH)
Function
Group
Function
00
01
05
06
ADD
A+Q
A+B
D+A
D+Q
ADD plus
one
A+Q+1
A+B+l
D+A+ 1
D+Q + 1
02
03
04
07
PASS
Q
B
A
D
Increment
Q+1
B+1
A+ 1
D+1
12
13
14
27
Decrement
Q -1
B-1
A-1
D -1
22
23
24
17
1's Compo
-Q-1
-B-1
-A-1
-D -1
10
11
15
16
20
21
25
26
Subtract
Q-A-1 Subtract
(1's Comp.) B-A-1 (2'sComp.)
A-D-1
Q-D -1
A-Q-1
A-B-1
D-A-1
D -Q-1
PASS
2'sComp.
(Negate)
Q
B
A
D
-Q
-B
-A
-D
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
Io
ao
..J
~
~PRFSS
~_~
CY7C9101
SEMICONDUcrOR
Electrical Characteristics Over Commercial and Military Operating Rangd2]
Vee Min.
= 4.5V, Vee Max. = 5.5V
Parameter
"Description
Test Conditions
,
VOH
Output HIGH Voltage
Vee = Min., IOH = - 3,4 rnA
All Outputs Except F = 0
VOL
Output LOW Voltage
Vee = Min., IOL
VIH
Input HIGH Voltage
VIL
IIX
IOH
Input LOW Voltage
Input Leakage Current
Output HIGH Current
IOL
Output LOW Current
Vee
loz
Output Leakage Current
Vee
Min.
= 16 rnA
2.0
-3.0
-10
Vss ~ VIN ~ Vee, Vee = Max.
Vee = Min., VOH = 2,4V
All Outputs Except F = 0
Ise
Output Short Circuit Currentl3]
lec(Ql)[4]
Supply Current (Quiescent)
0,4
V
Vee
0.8
10
V
rnA
+40
fAA
fAA
-85
rnA
- 40
Iec(Q2)[4]
Supply Current (Quiescent)
Vss~ VIN~O,4Vor_
3.85V ~ VIN ~ Vee; OE
Iec(Max. )[4]
Supply Current
Ycc = Max., feLK = 10 MHz;
OE = HIGH
30
rnA
rnA
Commercial
Military
35
25
30
Commercial
60
rnA
Military
85
rnA
Commercial
Military
= HIGH
V
fAA
rnA
16
= HIGH
Unit
V
-3.4
= Min., VOL = O,4V
= Max.
VOUT = Vss to Vee
Vee = Max., VOUT = OV
All Outputs Except F = 0
Vss ~ VIN ~ VIL or
VIH~ VIN~ Vee; OE
Max.
2,4
rnA
rnA
Capacitance[S]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
8
pF
10
pF
Output Loads Used for AC Performance Characteristics[6, 7]
+5V
vo~O
fCl
f::
7C91 01-6
7C9101-9
Open Drain (F = 0)
All Outputs Except Open Drain
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than one output should be shorted at a time. Duration of the
short circuit should not be more than one second.
4. Two quiescent figures are given for different input voltage ranges. To
calculate Icc at any given frequency, use ICc(Ql) + Icc(AC) where
IcC(Ql) is shown above and Icc(AC) = (3 mA/MHz) X Clock Fre-
5.
6.
7.
6-30
quency for the commercial temperature. Icc(AC) = (5 mA/MHz) X
Clock Frequency for military temperature range.
Tested initially and after any design or process changes that may affect
these parameters.
CL = 50 pF includes scope probe, wiring, and stray capacitance.
CL = 5 pF for output disable tests.
. .::Z
CY7C9101
~jr CYPRESS
~ IF SEMICONDUCTOR
Table 7. Logic Functions for CARRY and OVERFLOW Conditions
1543
Function
P
G
Cn + 16
OVR
0
R+S
Po - PIS
GIS + PlSG14 + PlSP14G13 + ... + PI - PlSGO
C16
C16¥ClS
1
S- R
2
R-S
3
R VS
4
RJ\S
5
RJ\S
6
R¥S
7
R¥S
•
•
Same as R + S equations, but substitute Rj for Rj in definitions
Same as R + S equations, but substitute Sj for Sj in definitions
HIGH
HIGH
Definitions (+ = OR)
Po - PIS = PlSP14P13P12PllPlOP9PSP7P6PSP4P3P2PlPO
Po = Ro + So
PI = Rl + Sl
P2 = R2 + S2
P3 = R3 + S3, etc.
LOW
•
•
LOW
Go - GIS = GlSG14G13G12GllGlOG9GSG7G6GSG4G3G2GlGO
Go = RoSo
Gl = RlSl
G2 = R2 S2
G3 = R3S3, etc.
C16 = GIS + PlSG14 + PlS P 14G 13 + ... + Po - PlSCn
CIS = G14 + P14 G 13 + P14 P 13 G 12 + ... + Po - P14 C n
CY7C9101-30 and CY7C9101-40 Guaranteed
Commercial Range AC Performance Characteristics
S
Cycle Time and Clock Characteristics
The tables below specify the guaranteed AC performance of
these devices over the commercial (O°C to 70°C) operating
temperature range with Vee varying from 4.5V to 5.5V. All
times are in nanoseconds and are measured between the 1.5V
signal levels. The inputs switch between OV and 3V with signal
transition rates of 1V per nanosecond. All outputs have maximum DC current loads. See the Electrical Characteristics section for loading circuit information.
CY7C9101
-30
-40
Read-Modify-Write Cycle (from selection
of A, B registers to end of cycle)
30 ns
40ns
Maximum Clock Frequency to shift Q
(50% duty cycle, I = 432 or 632)
This data applies to parts with the following numbers:
CY7C9101-30PC
CY7C9101-3OJC
CY7C9101-30GC
CY7C9101-40GC
33 MHz 25 MHz
Minimum Clock LOW Time
20ns
Minimum Clock HIGH Time
10 ns
15 ns
Minimum Clock Period
30 ns
40 ns
CY7C9101-40PC
25 ns
CY7C9101-40JC
Combinatorial Propagation Delays (CL = 50 pF)[S]
To Output
Y
F15
C n + 16
From Input
Y
F15
30
40
30
40
30
40
30
40
30
40
32
41
35
46
32
42
32
40
-
-
F=O
OVR
RAMo
Qo
F=O
OVR
RAM15
Q15
Speed (ns)
30
40
30
40
C n + 16
30
40
A, BAddress
37
47
36
47
35
44
D
29
34
28
34
25
32
25
30
29
36
21
26
27
33
Cn
22
27
22
27
20
25
-
-
22
26
22
26
24
30
1012
32
40
32
40
30
38
28
36
34
42
26
32
27
35
-
I34S
34
43
33
42
33
42
27
35
34
40
32
42
29
38
-
-
I67S
A Bypass ALU (I
= 2XX)
Clock (LOW to HIGH)
-
19
22
-
-
-
22
26
22
26
-
-
-
-
-
-
-
-
30
-
-
25
-
-
-
-
-
-
31
40
30
39
30
38
27
34
28
37
34
34
27
35
20
23
Note:
8.
G,P
G,P
A dash indicates a propagation delay path or set-up time constraint
does not exist.
6-31
Io
o...J
~
~~PRESS
~, SEMICONDUCTOR
CY7C9101
Set-Up and Hold Times Relative to Clock (CP) Input[8]
~~
CP:
Set-UpTime
Before H. L
Speed (ns)
30
40
A, B Source Address
10
15
B Destination Address
10
15
Data
-
-
Cn
10,1,2
13,4,5
Hold Time
MterH.L
30
3l'lJ
•
-
-
-
-
-
-
16,7,8
10
12
RAMo, RAM15, Qo, Q15
-
-
-- --
40
3l'lJ
-
Hold Time
MterL.H
Set-UpTime
BeforeL. H
30
30l lUJ
Do Not Change lllJ
40
30
4Ol 1UJ
0
0
0
0
•
40
-
22
28
0
0
16
22
0
0
26
35
0
0
37
0
0
0
0
-
11
0
0
29
Do Not Change lllJ
•
7 r
14
•
Output Enable/Disable Times
Output disable tests performed with CL
= 5 pF and measured to O.5V change of output voltage level.
Device
Inpnt
Outpnt
Enable
CY7C9101-30
OE
Y
18
16
CY7C9101-40
OE
Y
22
19
Disable
Notes:
9. Source addresses must be stable prior to the clock HIGH-to-LOW
transition to allow time to access the source data before the latches
close. The A address may then be changed. The B address could be
changed if it is not a destination; i.e., if data is not being written back
into the RAM. Normally A and B are not changed during the clock
LOW time.
10. Theset-uptimepriortotheclockLOW-to-HIGHtransitionistoallow
time for data to be accessed, passed through the ALU, and returned to
the RAM. It includes all the time from stable A and B addresses to the
clock LOW-to-HIGH transition, regardless of when the clock HIGHto-LOW transition occurs.
11. Certain signals must be stable during the entire clock LOW time to
avoid erroneous operation. This is indicated by the phrase "do not
change."
6-32
CY7C9101
Cycle Time and Clock Characteristics[2]
CY7C9101-35 and CY7C9101-45 Guaranteed
Military Range AC Performance Characteristics
The tables below specify the guaranteed AC performance of
these devices over the military ( - 55 0 C to + 125 0 C) operating
temperature range with Vee varying from 4.5V to 5.5Y. All
times are in nanoseconds and are measured between the 1.5V
signal levels. The inputs switch between OV and 3V with signal
transition rates of 1V per nanosecond. All outputs have maximum DC current loads. See the Electrical Characteristics section for loading circuit information.
This data applies to parts with the following numbers:
CY7C9101-35DMB CY7C9101-35LMB CY7C9101-35GMB
CY7C9101-45DMB CY7C9101-45LMB CY7C9101-45GMB
CY7C9101
-35
-45
Read-Modify-Write Cycle (from selection
of A, B registers to end of cycle)
35 ns
45 ns
Maximum Clock Frequency to shift 0
(50% duty cycle, I = 432 or 632)
28 MHz 22 MHz
Minimum Clock LOW Time
Minimum Clock HIGH Time
Minimum Clock Period
28 ns
23 ns
12 ns
35 ns
17 ns
45 ns
Combinatorial Propagation Delays (CL = 50 pF)[2, 8]
To Output
y
F15
From Input
Speed (ns)
A, BAddress
D
Y
F15
Cn
1012
1345
1678
A Bypass ALU (I = 2XX)
Clock (LOW to HIGH)
35
41
31
25
36
38
21
28
35
45
52
37
30
44
48
24
33
44
35
40
31
24
35
37
34
G,P
G,P
35
45
37
45
32
28
Cn + 16
Cn + 16
35
45
48
38
45
51
36
29
43
47
29
23
33
37
34
-
43
36
27
41
46
-
31
31
30
-
42
F=O
F=O
35
40
33
24
38
38
34
38
38
-
37
45
48
40
29
46
45
-
40
OVR
OVR
35
45
36
46
23
32
23
27
29
38
36
45
28
38
RAMo
Qo
RAM15
Q15
35
36
30
26
30
33
24
45
43
35
31
38
41
28
30
37
-
45
-
-
-
35
-
-
24
21
-
28
25
Set-Up and Hold Times Relative to Clock (CP) Input[2,8]
CP:
~
-- --Set-UpTime
Set-UpTime
BeforeH. L
Hold Time
AfterH. L
Speed (ns)
35
45
12
17
B Destination Address
12
17
D
-
-
•
-
-
25
30
Cn
-
-
-
-
19
1012
-
-
-
-
1345
-
-
-
-
1678
12
16
RAMo, RAM 15, 00,015
-
-
•
-
45
3[9]
35
35[10]
45
45[10]
Do Not Changd ll ]
Device
Input
Output
Enable
OE
Y
20
17
CY7C9101-45
OE
Y
23
20
Disable
6-33
0
1
1
0
0
0
30
37
0
0
33
40
0
0
0
0
1
1
13
= 5 pF and measured to O.5V change of output voltage level.
CY7C9101-35
45
0
24
Output EnablelDisable Times[2]
Output disable tests performed with CL
•
35
0
Do Not Changd ll ]
-
Hold Time
MterL.H
BeforeL. H
A, B Source Address
35
3[9]
7f-
15
•
I
o
(;
o
..J
~4
-=::::::;.'
~
CY7C9101
:.. CYPRESS
SEMICONDUCTOR
Applications
Minimum Cycle Time Calculations for 16-Bit Systems
Speed used in calculations for parts other than CY7C9101 and CY7C910 are representative for available MSI parts~
7C9101·10
Pipelined System, Add Without Simultaneous Shift
CY7C245
CY7C901
Register
Data Loop
Clock to Output
A, B to Y,
+ 16, OVR
Set-Up
en
CY7C245
MUX
CY7C910
CY7C245
12
37
4
53 ns
Control Loop
Clock to Output
Select to Output
CCto Output
Access Time
12
12
22
20
66 ns
Minimum Clock Period
= 66 ns
MICROPROGRAM
MEMORY
REGISTER
7C9101·11
Pipelined System, Simultaneous Add and Shift Down (Right)
CY7C245
CY7C9101
XOR and MUX
CY7C9101
Data Loop
Clock to Output
A, B to Y,
+ 16, OVR
Prop. Delay, Select to
Output
RAM15 Set-Up
en
12
37
20
CY7C245
MUX
CY7C91O
CY7C245
11
80 os
Minimum Clock Period = 80 ns
6-34
Control Loop
Clock to Output
Select to Output
CCto Output
Access Time
12
12
22
20
66 ns
.:~
CY7C9101
- ' i E CYPRESS
iF
SEMICONDUCTOR
TYpical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
VS. SUPPLY VOLTAGE
1.6
1.2
l
OUTPUT SOURCE CURRENT
vS.VOLTAGE
60
I
l-
1.4
.9
0
w 1.2
~1.1
:::::i
«
::2: 1.0
0:
z
:::::i 1.0
~
0:
5.0
5.5
6.0
j:'
z
~
0:
125
::J
o 100
/
~
~
75
l-
i[
50
I-
6
25
oI
0.0
/
./
;'
L"
~
z
~ 100
ow
~
gj
Vee = 5.0V
TA = 25°C
1.2
3.0
0.8
z
I
j:'
'" -----
1.5
1.4
1.3
/
L
~ 1.2
«
::2:
0:1.1
oz
1.0
/
o
200
~
60
/'
40
/
I-
6
125
()
~
20
oI
/
Vee = 5.0V
TA = 25°C
L
0.0
1.0
2.0
3.0
4.0
./
1.0
//
0
w 0.9
V~
:::::i
«
0:
0.8
0
z
Vee = 5.0V
TA = 25°C
0.7
I
0.0
600
;'
~
OUTPUT VOLTAGE (V)
N
::2:
400
Io
1/
l-
.9
/
/
4.0
NORMALIZED Icc vs. FREQUENCY
-
V
~
3.0
1.1
1/
w
80
AMBIENT TEMPERATURE (0C)
1.6
2.0
120
o
i[
25
~
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
~
Vee = 5.0V
TYPICAL OUTPUT DELAY
CHANGE VS. OUTPUT LOADING
~
o
1.0
'"
0:
::J
"'---
0.6
-55
4.0
OUTPUT VOLTAGE (V)
o
0
0.0
rE1.4
~ 1.0
~
a..
10
«E 140
...J
~
I6
1.6
::J
J
~
20
""
OUTPUT VOLTAGE (V)
~
If
2.0
i[
NORMALIZED FREQUENCY
VS. AMBIENT TEMPERATURE
o
1.0
30
AMBIENT TEMPERATURE (0C)
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
150
40
I-
0.8 L...-_ _ _- - "_ _ _ _ _- '
-55
25
125
SUPPLY VOLTAGE (V)
«E 175
g
Vee = 5.0V TA = 25°C
50
::J
Vee = 5.SV
VIN = 5.0V
I
4:5
o
~
I-----~~------l
~ 0.91--------4-------:::",.,.,...--l
f=10MHz
TA = 25°C
V
0.6
4.0
::J
N
0:
/'
0
0:
0:
oW
/~
N
0.8
rE
~
()
I
800 1000
CAPACITANCE (pF)
/
o
5
V
10
Vee = 5.0V
TA = 25°C
VIN = OV or 3V
I
I
I
15 20 25 30
FREQUENCY (MHz)
6-35
35
7C9101-12
a
9
~PRFSS
_rs~CONDUcrOR
CY7C9101
Ordering Information
Speed (ns)
Ordering Code
30
CY7C9101-30GC
CY7C9101-30JC
CY7C9101-30PC
CY7C9101-35DMB
CY7C9101-35GMB
CY7C9101-35LMB
CY7C9101-40GC
CY7C9101-40JC
CY7C9101-40PC
CY7C9101-45DMB
CY7C9101-45GMB
CY7C9101-45LMB
35
40
45
Package
Name
G68
J81
P29
D30
G68
LSI
G68
J81
P29
D30
G68
LSI
Package 'JYpe
68-Pin PGA (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
64-Lead (900-Mil) Molded DIP
64-Lead (900-Mil) Bottombraze
68-Pin PGA (Cavity Down)
68-Square Leadless Chip Carrier
68-Pin PGA (Cavity Down)
68-Lead Plastic Leaded Chip Carrier
64-Lead (900-Mil) Molded DIP
64-Lead (900-Mil) Bottombraze
68-Pin PGA (Cavity Down)
68-Square Leadless Chip Carrier
6-36
Operating
Range
Commercial
Military
Commercial
Military
t:~
CYPRESS
~.a
IF
CY7C9101
SEMICONDUCTOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Combinational Propagation Delays (continued)
Parameter
Subgroups
=a
7, 8, 9, 10, 11
7,8,9, 10, 11
Parameter
Subgroups
VOH
VOL
VIR
VILMax.
IIX
loz
Ise
ledOl)
led02)
ledMax.)
1,2,3
From Cn to F
1,2,3
From C n to OVR
1,2,3
1,2,3
From
From 10,1,2 to Y
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
1,2,3
From 10,12 to F15
1,2,3
1,2,3
From 10,1,2 to
1,2,3
1,2,3
From 10,1,2 to F
From 10,1,2 to OVR
7, 8, 9, 10, 11
7, 8, 9, 10, 11
1,2,3
From 10,1,2 to RAMO,15
7, 8, 9, 10, 11
Parameter
From A, B Address to Cn + 16
From A, B Address to G, P
From A, B Address to F
=a
From A, B Address to OVR
From A, B Address to RAMO,15
7, 8, 9, 10, 11
7, 8, 9, 10, 11
=a
From 13,4,5 to Y
7, 8, 9, 10, 11
From 13,4,5 to F15
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
en
Subgroups
From A, B Address to F 15
en + 16
From 10,1,2 to G, P
Combinational Propagation Delays
From A, B Address to Y
en to RAMO,15
From 13,4,5 to
+ 16
From 13,4,5 to G, P
7,8, 9, 10, 11
7,8,9, 10, 11
From 13,4,5 to F
=a
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
From 13,4,5 to OVR
7, 8, 9, 10, 11
From 13,4,5 to RAMO,15
7, 8, 9, 10, 11
7,8,9, 10, 11
From 16,7,8 to Y
7, 8, 9, 10, 11
7, 8, 9, 10, 11
From 16,7,8 to RAMO,15
7, 8, 9, 10, 11
7, 8, 9, 10, 11
From 16,7,8 to 00,15
From A Bypass ALU to Y (I
7, 8, 9,10, 11
= 2XX)
From D to F15
7, 8, 9, 10, 11
7, 8, 9, 10, 11
en
7, 8, 9, 10, 11
From Clock LOW to HIGH to F15
From Clock LOW to HIGH to
+ 16
From Clock LOW to HIGH to G,P
FromDtoOVR
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
From Clock LOW to HIGH to F
From D to RAMO,15
7, 8, 9, 10, 11
From Clock LOW to HIGH to OVR
From
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
From Clock LOW to HIGH to RAMO,15
7, 8, 9, 10, 11
From Clock LOW to HIGH to 0015
7,8,9, 10, 11
FromDto Y
From D to
+ 16
FromDto G,P
FromD toF =
a
en to Y
From en to F 15
From en to C + 16
n
From Clock LOW to HIGH to Y
en
6-37
=a
7, 8,9, lO, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
II
(.)
C3
o...I
;,r~R
CY7C9101
Set-Up and Hold Times Relative to Clock (CP) Input
Parameter
Subgroups
A, B Source Address
Set-Up Time Before H • L
7, 8, 9, 10, 11
A, B Source Address
Hold Time After H • L
A, B Source Address
Set-Up Time Before L • H
A, B Source Address
Hold Time After L • H
B Destination Address
Set-Up Time Before H. L
B Destination Address
Hold Time After H • L
B Destination Address
Set-Up Time Before L. H
B Destination Address
Hold Time After L • H
D Set-Up Time Before L • H
D Hold Time After L. H
en Set-Up Time Before L. H
Hqld Time After L. H
1012 Set-Up Time Before L. H
1012 Hold Time After L • H
1345 Set-Up Time Before L. H
1345 Hold Time After L • H
1678Set-Up Time Before H. L
1678 Hold Time After H
1678 Set-Up Time Before L. H
1678 Hold Time After L • H
RAMo, RAM15, 00, 015
Set-Up Time Before L. H
7,8,9, 10, 11
RAMo, RAM15, 00, 015
7, 8, 9, 10, 11
en
.L
7,8,9, 10, 11
7, 8,9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7,8,9,10,11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9,10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7,8,9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7,8, 9, 10,)1
7,8, 9, 10, 11
Hold Time After L • H
Document #: 38-00017-D
6-38
lOGIC
I
I
I
I
I
I
DATACOM
Ii
MODULES
.:1
ECl
EI
BUS
'm
MiliTARY
"I
TOOLS
ItA
INFO
SRAMs
PROMs
PlDs
FIFOs
QUALITY
PACKAGES
'i'
'i'
~
=.. . ~
Section Contents
~=CYPRESS
~_, SEMICONDUCTOR
. Data Communications Products
Device Number
CY7B923
CY7B933
CY9266-C
CY9266-F
Page Number
Description
HOTLink Transmitter/Receiver ................................................. 7-1
HOTLink Transmitter/Receiver ................................................. 7-1
HOTLink Evaluation Board ................................................... 7 - 26
HOTLink Evaluation Board ................................................... 7 - 26
PRELIMINARY
CYPRESS
SEMICONDUCTOR
HOTLink®
Transmitter/Receiver
Features
Functional Description
•
•
•
•
•
•
•
•
•
•
The CY7B923 HOTLink 1tansmitter and
CY7B933 HOTLink Receiver are pointto-point communications building blocks
that transfer data over high-speed serial
links (fiber, coax, and twisted pair) at 160
to 330 Mbits/second. Figure 1 illustrates
typical connections to host systems or controllers.
Eight bits of user data or protocol information are loaded into the HOTLink transmitter and are encoded. Serial data is
shifted out of the three differential Pseudo
ECL (PECL) serial ports at the bit rate
(which is 10 times the byte rate).
The HOTLink receiver accepts the serial
bit stream at its differential line receiver inputs, and using a completely integrated
PLL clock synchronizer recovers the timing information necessary for data reconstruction. The bit stream is deserialized,
•
•
•
•
•
Fibre Channel compliant
IBM ESCON@l compliant
ATM Compatible
SB/lOB-coded or 10-bit unencoded
160- to 330-Mbps data rate
TTL synchronous I/O
No external PLL components
Triple ECL lOOK serial outputs
Dual ECL lOOK serial inputs
Low power: 350 mW (Tx),
650mW (Rx)
Compatible with fiber optic modules,
coaxial cable, and twisted pair media
Built-In Self-Test
Single +5V supply
28-pin DIP/PLCC/LCC
0.811 BiCMOS
CY7B923 Transmitter Logic Block Diagram
CY7B923
CY7B933
decoded, and checked for transmission errors. The recovered byte is presented in
parallel to the receiving host along with a
byte rate clock.
The 8B/lOB encoder/decoder can be
disabled in systems that already encode or
scramble the transmitted data. I/Os are
available to create a seamless interface
with both asynchronous FIFOs (i.e.,
CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A Built-In Self-Test pattern
generator and checker allows testing of the
transmitter, receiver, and the connecting
link as a part of a system diagnostic check.
HOTLink devices are ideal for a variety of
applications where a parallel interface can
be replaced with a high-speed point-topoint serial link. Applications include interconnecting workstations, servers, mass
storage, and video transmission equipment.
CY7B933 Receiver Logic Block Diagram
::E
AlB - - - - - ,
FOTO
~
INA+
INA-
iCC
C
INB (INB+)
SI (INB-)
so
REFCLK - - - - . - \
MODE
BlSTEN
B923·1
SERIAL LINK
HOST
HOST
Figure 1. HOTLink System Connections
HOTLink is a trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
7-1
•
oo
RF
B923-3
-I~"
:;~PRFSS
CY7B923
CY7B933
PRELIMINARY
SEMICONDUCTOR
CY7B933 Receiver Pin Configurations
CY7B923 Transmitter Pin Configurations
DIP
Top View
DIP
Top View
OutBOutCOutC+
VCCN
BlS"FEN
GND
MODE
RP
Vcca
SVS(Dj)
(Dh) D7
(Dg) D6
(Dj) D5
(Dj) D4
INAINA+
OutB+
OutA+
OutAFOTO
ENN
ENA
Vcca
CKW
GND
SC/D (Dal
Do (Db)
D1 (Del
D2 (Ddl
D3(De)
6923-1
NB
3
BISTEN
RF
GND
RDY
GND
VCCN
RVS(Qj)
(Qh) Q7
(Qg) Q6
(QI)Q 5
(Qj)Q4
4
7
m<~~ ~Ci5::::2:
76923
21
COLO oq-C')C\I ..... 0
0000000
FOTO
ENN
ENA
Vcca
CKW
GND
SC/D (Dal
RF
GND
RDY
GND
VC8N
RVS( j)
(Qh) Q7
"-
CD "C
0
5
6
24
23
22
21
20
76933
9
co
6923-2
In.qo
C')
C\I,...
0
REFCLK
Vcca
SO
CKR
Vcca
GND
SC/D (Qal
6923-4
0000000
~~~~~
0)-
~tbw
Z
> 000000
RP
6
II!:!
+ 1 =Zo
00 1m « « m=O
8:::J:::J:::J :::J:::J:::J
Vcca
SVS(Dj)
(Dh) D7
5
PLCC
Top View
+~
PLCC
Top View
+1 1 ++ 1
z~ ~ $I $1:%:%
BISTEN
GND
MODE
INB (INB+)
SI(INB-)
MODE
REFCLK
Vcca
SO
CKR
Vcca
GND
SC/D (Qal
QO(Qb)
Q1 (Qd
Q2(Qd)
Q3(Q e)
6923-3
~~~~~
.0
0)-
.-
Q)
"C
0
..c
ggggggg
ee.8ee.88
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................... - 65 C to + 150 C
Ambient Temperature with
Power Applied ......................... - 55 C to + 125 C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Input Voltage. . . . . . . . . . . . . . . . . . . . . .. - 0.5V to +7.0V
Output Current into TTL Outputs (LOW) ........... 30 rnA
Output Current into ECL outputs (HIGH) . . . . . . . .. -50 rnA
Static Discharge Voltage ........................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ............................ >200 rnA
7-2
Range
Commercial
Industrial
Military
Ambient
Temperature
O°Cto +70°C
Vee
5V ± 10%
- 40°C to +85°C
5V ± 10%
- 55°C to + 125°C
Case Temperature
5V ± 10%
.
7~
PRELIMINARY
_l= CYPRESS
CY7B923
CY7B933
------~ S~CONDUCTOR
Pin Descriptions
CY7B923 HOTLink Transmitter
Description
Name
I/O
TTL In
Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or
DO-7
on the next rising CKW with ENN LOW). IfENA and ENN are HIGH, a Null character (K28.5) is sent.
(Db - h)
When MODE is HIGH, Do, 1, ...7 become Db, c, ... h respectively.
TTL In
Special Character/Data Select. A HIGH on SC/D when CKW rises causes the transmitter to encode the
SCJD
pattern on DO-7 as a control code (Special Character ~while a LOW causes the data to be coded using the
(Da)
8B/lOB data alphabet. When MODE is HIGH, SC/D (Da) acts as Da input.
TTL In
SVS
Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is e.!!coded and sent while
the data on the parallel inputs is ignored. IfSVS is LOW, the state ofDo-7 and SCID determines the code
(Dj)
sent. In normal or test mode, this pin overrides the BIST generator and forces the transmission of a Violation code. When MODE is HIGH, SVS (Dj) acts as Dj input.
ENA
TTL In
Enable Parallel Data. IfENA is LOW on the rising edge of CKw, the data is loaded, encoded, and sent.
IfENAis HIGH, the data inputs are ignored and the Transmitter will insert a Null character (K28.5) to fill
the space between user data. ENA may be held HIGH/LOW continuously or it may be pulsed with each
data byte to be sent. IfENA is being used for data control, ENN will normally be strapped HIGH, but can
be used for BIST function control.
ENN
TTL In
CKW
TTL In
Enable Next Parallel Data. If ENN is LOW, the data appearing on DO-7 at the next rising edge of CKW
is loaded, encoded, and sent. IfENN is HIGH, the data appearing on DO-7 at the next rising edge ofCKW
will be ignored and the Transmitter will insert a Null character to fill the space between user data. ENN
may be held HIGH/LOW continuously or it may be pulsed with each data byte sent. IfENN is being used
for data control, ENA will normally be strapped HIGH, but can be used for BIST function control.
Clock Write. CKW is both the clock frequency reference for the mUltiplying PLL that generates the highspeed transmit clock, and the byte rate write signal that synchronizes the parallel data input. CKW must
be connected to a crystal controlled time base that runs within the specified frequency range of the Transmitter and Receiver.
FOTO
TTL In
Fiber Optic Transmitter Off. FOTO determines the function of two of the three EeL transmitter output pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs continuously. If FOTO is HIGH, OUTA± and OUTB± are forced to their "logic zero" state (OUT+ = LOW
and OUT - = HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is
unaffected by the level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testing.
OUTA±
OUTB±
OUTC±
ECLOut
Differential Serial Data Outputs. These ECL 100Koutputs (+5V referenced) are capable of driving terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs can be
wired to Vee to reduce power if the output is not required. OUTA± and OUTB± are controlled by the
level on FOTO, and will remain at their "logical zero" states when FOTO is asserted. OUTC± is unaffected by the level on FOTO. (OUTA + and OUTB+ are used as a differential test clock input while in
Jest mode, i.e., MODE= UNCONNECTED.)
.
MODE
3-Level
In
BISTEN
TTL In
Encoder Mode Select. The level on MODE determines the encoding method to be used. When wired to
GND, MODE selects 8B/lOB encoding. When wired to Vee, data inputs bypass the encoder and the bit
pattern on Da _j goes directly to the shifter. When left floating (internal resistors hold the input at Ved2)
the internal bit-clock generator is disabled and OUTA + /OUTB + become the differential bit clock to be
used for factory test. In typical applications MODE is wired to Vee or GND.
Built-In Self-Test Enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends
an alternating 1-0 pattern (DI0.2 or D21.5). When either ENA or ENN is set LOW the transmitter begins a repeating test sequence that allows the Transmitter and Receiver to work together to test the function of the entire link. In normal use this input is held HIGH or wired to Vee. The BIST generator is a
free-running pattern generator that need not be initialized, but if required, the BISTsequence can be initialized by momentarily asserting SVS while BISTEN is LOW.
RP
TTL Out
VeeN
VeeQ
GND
Read Pulse. RP is a 60% LOWduty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent
of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will
remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop.
Power for output drivers.
Power for internal circuitry.
Ground.
7-3
•
::E
o
o
~
iCC
C
4.;ri
-.
~
I'
PRELIMINARY
CYPR.F.SS
CY7B923
CY7B933
SEMICONDUCTOR
CY7:B933 HOTLink Receiver
I/O
TTL Out
Description
SC/D (Oa)
TTL Out
RVS (OJ)
TTL Out
Special CharacterlData Select. SCID indicates the context of received data. HIGH indica~ a Control
(Special Character) code, LOW indicates a Data character. When MODE is HIGH, SCID acts as Oa
output.
Received Violation Symbol. A HIGH on RVS indicates that a code rule violation has been detected in the
received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW on RVS
indicates correct operation ofthe Transmitter, Receiver, and link on a byte-by-byte basis. When MODE
is HIGH, RVS acts as OJ output.
RDY
TTL Out
Data Output Ready. A LOW pulse on RDY indicates that new data has been received and is ready to be
delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted
by the transmitter as a pad between data inputs). In BIST mode RDY will remain LOW for all but the last
byte of a test loop and will pulse HIGH one byte time per BIST loop.
CKR
TTL Out
Clock Read. ThisQyte rate clock output is phase and frequency aligned to the incoming serial data stream.
RDY, 00-7, SCID, and RVS all switch synchronously with the rising edge of this output.
AlB .
ECLin
INA±
DiffIn
Serial Datajnput Select. This ECL lOOK (+5V referenced) input selects INA or INB as the active data
inPllt. If AlB is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If
AlB is LOW INB is selected.
Serial Data Input A. The differential signal at the receiver end of the communication link may be connected to the differential input pairs INA± or INB ±. Either the INA pair or the INB pair can be used as
the main data input and l.he other can be used as a loopback channel or as an alternative data input selected by the state of AlB.
INB
(INB+)
ECLin
(DiffIn)
Serial Data Input B. This pin is either a single-ended ECL data receiver (INB) or half of the INB of the
differential pair. If SO is wired to V cc, then INB± can be used as differential line receiver interchangeably with INA±. If SO is normally connected and loaded, INB becomes a single-ended ECL lOOK ( + 5V
referenced) serial data input. INB is used as the test clock while in Test mode.
SI
(INB-)
ECLin
(DiffIn)
Status Input. This pin is either a single-ended ECL status monitor input (SI) or half of the INB of the
differential pair. If SO is wired to V cc, then INB ± can be used as differential line receiver interchangeably with INA±. If SO is normally connected and loaded, SI becomes a single-ended ECL lOOK ( + 5V
referenced) status monitor input.
SO
TTL Out
RF
TTL In
REFCLK
TTL In
Status Out. SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect output from a fiber-optic receiver. When this pin is normally connected and loaded (without any external
pull-up resistor), SO will assume the same logical level as SI and INB will become a single-ended ECL
serial data input. If the status monitor translation is not desired, then SO may be wired to V cc and the
INB± pair may be used as a differential serial data input.
Reframe Enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC
(K28.5) symbol detected in the shifter will frame the data that follows. When RF is held LOW, the reframing logic is disabled. The incoming data stream is then continuously deserialized and decoded using byte
boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC characters to reframe the data erroneously.
Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of the
Tx/Rxpair, and the frequency must bethe same as the transmitter CKW frequency (within CKW ±O.l %).
MODE
3-Levelln
BISTEN
TTL In
Name
00-7
(Ob -
VCCN
VCCQ
GND
h)
00-7 Parallel Data Output. 00-7 contain the most recently received data. These outputs change synchronously with CKR. When mode is HIGH, 00,1, ...7 become Ob, c, ... h respectively.
Decoder Mode Select. The level on the MODE pin determines the decoding method to be used. When
wired to GND, MODE selects 8B/lOB decoding. When wired to V co registered shifter contents bypass
the decoder and are sent to Oa-j directly. When left floating (internal resistors hold the MODE pin at
V cd2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for
factory test. In typical applications, MODE is wired to V CC or GND.
Built-In Self-Test Enable. When BISTEN is LOW the Receiver awaits a DO.O (sent once per BIST loop)
character and begins a continuous test sequence that tests the functionality of the Transmitter, the Receiver, and the link connecting them. In BIST mode the status of the test can be monitored with RDY and
RVS outputs. In normal use BISTEN is held HIGH or wired to V cc.
Power for output drivers.
Power for internal circuitry.
Ground
7-4
·
.~
~i= CYPRESS
PRELIMINARY
CY7B923
CY7B933
- , SEMICONDUCTOR
CY7B923 HOTLink Transmitter Block Diagram
Description
Input Register
The Input register holds the data to be processed by the HOTLink
transmitter and allows the input timing to be made consistent with
standard FlFOs. The Input register is clocked by CKW and loaded
with information on the DO-7, SC;D, and SVS pins. Two enable inputs (ENA and ENN) allow the user to choose when data is to be
sent. Asserting ENA (Enable, active LOW) causes the inputs to be
loaded on the rising edge of CKW If ENN (Enable Next, active
LOW) is asserted when CKW rises, the data present on the inputs
on the next rising edge of CKW will be loaded into the input register. These two inputs allow proper timing and function for compatibility with either asynchronous FIFOs or clocked FlFOs without
external logic, as shown in Figure 2.
In BIST mode, the Input register becomes the signature pattern
generator by logically converting the parallel input register into a
Linear Feedback Shift Register (LFSR). When enabled, this LFSR
will generate a 511-byte sequence that includes all Data and Special Character codes, including the explicit violation symbols. This
pattern provides a predictable but pseudo-random sequence that
can be matched to an identical LFSR in the Receiver.
Encoder
The Encoder transforms the input data held by the Input register
into a form more suitable for transmission on a serial interface link.
The code used is specified by ANSI X3T9.3 (Fibre Channel) and
the IBM ESCON channel (code tables are at the end of this datasheet). The eight DO-7 data inputs are converted to either a Data
symbol or a Special Character, depending upon the state of the
SCID input. If SC;D is HIGH, the data inputs represent a control
code and are encoded using the Special Character code tables. If
SC;D is LOW, the data inputs are converted using the Data code
table. If a byte time passes with the inputs disabled, the Encoder
will output a Special Character Comma K28.5 (or SYNC) that will
maintain link synchronization. SVS input forces the transmission
of a specified Violation symbol to allow the user to check error
handling system logic in the controller.
The 8B/IOB coding function of the Encoder can be bypassed for
systems that include an external coder or scrambler function as
part of the controller. This bypass is controlled by setting the
MODE select pin HIGH. When in bypass mode, Da-j (note that
bit order is specified in Fibre Channel8B/10B code) become the
ten inputs to the Shifter, with Da being the first bitto be shifted out.
Shifter
The Shifter accepts parallel data from the Encoder once each byte
time and shifts it to the serial interface output buffers using a PLL
multiplied bit clock that runs at ten (10) times the byte clock rate.
Timing for the parallel transfer is controlled by the counter included in the Clock Generator and is not affected by signallevels or
timing at the input pins.
OutA, OutB, OutC
The serial interface ECL output buffers (lOOK referenced to + 5v)
are the drivers for the serial media. They are all connected to the
Shifter and contain the same serial data. Two of the output pairs
(OUTA± and OUTB±) are controllable by the FOTO input and
can be disabled by the system controller to force a logical zero (i.e.,
"light off") at the outputs. The third output pair (OUTC±) is not
affected by FOTO and will supply a continuous data stream suitable for loop-back testing of the subsystem.
OUTA± and OUTB± will respond to FOTO input changes within
a few bit times. However, since FOTO is not synchronized with the
transmitter data stream, the outputs will be forced off or turned on
at arbitrary points in a transmitted byte. This function is intended
to augment an external laser safety controller and as an aid for Receiver PLL testing.
In wire-based systems, control of the outputs may not be required,
and FOTO can be strapped LOW. The three outputs are intended
to add system and architectural flexibility by offering identical serial bit streams with separate interfaces for redundant connections
or for multiple destinations. Unneeded outputs can be wired to
Vee to disable and power down the unused output circuitry.
Clock Generator
The clock generator is an embedded phase-locked loop (PLL) that
takes a byte-rate reference clock (CKW) and multiplies by ten (10)
to create a bit rate clock for driving the serial shifter. The byte rate
reference comes from CKw, the rising edge of which clocks data
into the Input register. This clock must be a crystal referenced
pulse stream that has a frequency between the minimum and maximum specified for the HOTLink Transmitter/Receiver pair. Signals controlled by this block form the bit clock and the timing signals that control internal data transfers between the Input register
and the Shifter.
The read pulse (RP) is derived from the feedback counter used in
the PLL multiplier. It is a byte-rate pulse stream with the proper
phase and pulse widths to allow transfer of data from an asynchronous FIFO. Pulse width is independent of CKW duty cycle, since
proper phase and duty cycle is maintained by the PLL. The RP
pulse stream will insure correct data transfers between asynchronous FIFOs and the transmitter input latch with no external logic.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexerfor Test mode clock distribution, and control logic to properly select the data encoding.
Test logic is discussed in more detail in the CY7B923 HOTLink
Transmitter Operating Mode Description.
CY7B933 HOTLink Receiver Block Diagram
Description
Serial Data Inputs
This pair of differential line receivers are the inputs for the serial
data stream. INA± or INB± can be selected with the AlB input.
INA± is selected with AlB HIGH and INB± is selected with AlB
LOW. The threshold of AlB is compatible with the ECL lOOK signals from ECL fiber optic interface modules. TTL logic elements
can be used to select the A or B in~ts by adding a resistor pull-up
to the TTL driver connected to NB. The differential threshold of
INA± and INB± will accommodate wire interconnect with filtering losses or transmission line attenuation greater than 20 db
(VDIF L 50mv) or can be directly connected to fiber optic interface
modules (any ECL logic family, not limited to ECL lOOK) with up
to 1.2 volts of differential signal. The common mode tolerance will
accommodate a wide range of signal termination voltages. The
highest HIGH input that can be tolerated is VIN = Vee, and the
lowest LOW input that can be interpreted correctly is VIN =
GND+2.0V.
ECL-TTL Translator
The function ofthe INB(INB+) input and the SI(INB-) input is
defined by the connections on the SO output pin. If the ECL/TTL
translator function is not required, the SO output is wired to Vee.
A sensor circuit will detect this connection and cause the inputs to
become INB± (a differential line-receiver serial-data input). If the
ECL/TTL translator function is required, the SO output is connected to its normal TTL load (typically one or more TTL inputs,
7-5
I
:E
o
0
~
a
!;;;;
. i"
c::~CYPRESS
~,
PRELIMINARY
CY7B923
CY7B933
SEMICONDUCTOR
but no pull-up resistor) and the inputs become INB (single-ended
ECL-IOOKserial-data input) and SI (single-ended ECL-IOOKstatus input).
This positive-referenced ECL-to-TTL translator is provided to
eliminate external logic between an ECL fiber-optic interface
module "carrier detect" output and the TTL input in the control
logic. The input threshold is compatible with ECL lOOK levels
(+ 5V referenced). It can also be used as part of the link status indication logic for wire connected systems.
Clock Sync
The Clock Synchronizer function is performed by an embedded
phase-locked loop (PLL) that tracks the frequency of the incoming
bit stream and aligns the phase of its internal bit rate clock to the
serial data transitions. This block contains the logic to transfer the
data from the Shifter to the Decode register once every byte. The
counter that controls this transfer is initialized by the Framer logic.
CKR is a buffered output derived from the bit counter used to control Decode register and Output register transfers.
Clock output logic is designed so that when reframing causes the
counter sequence to be interrupted, the period and pulse width of
CKR will never be less than normal. Reframing may stretch the period of CKR by up to 90%, and either CKR Pulse Width HIGH or
Pulse Width LOW may be stretched, depending on when reframe
occurs.
The REFCLK input provides a byte-rate reference frequency to
improve PLL acquisition time and limit unlocked frequency excursions of the CKR when no data is present at the serial inputs. The
frequency ofREFCLK is required to be within ±O.l % ofthe frequency of the clock that drives the transmitter CKW pin.
Framer
Framer logic checks the incoming bit stream for the pattern that
defines the byte boundaries. This combinatorial logic filter looks
for the X3T9.3 symbol defined as a Special Character Comma·
(K28.5). When it is found, the free-running bit counter in the Clock
Sync block is synchronously reset to its initial state, thus framing
the data correctly on the correct byte boundaries.
Random errors that occur in the serial data can corrupt some data
patterns into a bit pattern identical to a K28.5, and thus cause an
erroneous data-framing error. The RF input prevents this by inhibiting reframing during times when normal message data is present. When RF is held LOW, the HOTLink receiver will deserialize
the incoming data without trying to reframe the data to incoming
patterns. When RF rises, RDY will be inhibited until a K28.5 has
been detected, after which RDY will resume its normal function.
While RF is HIGH, it is possible that an error could cause misframing, after which all data will be corrupted. Likewise, a K28.7 followed by Dl1.x, D20.x, or an SVS (CO.7) followed by Dl1.x will
cause erroneous framing. These sequences must be avoided while
RF is HIGH.
If RF remains HIGH for greater than 2048 bytes, the framer converts to double-byte framing, requiring two K28.5 within 5 bytes.
Shifter
The Shifter accepts serialinputs from the Serial Data inputs one bit
at a time, as clocked by the Clock Sync logic. Data is transferred to
the Framer on each bit, and to the Decode register once per byte.
Decode Register
The Decode register accepts data from the Shifter once per byte as
determined by the logic in the Clock Sync block. It is presented to
the Decoder and held until it is transferred to the output latch.
Decoder
Parallel data is transformed from ANSI X3T9.3 8B/lOB codes back
to "raw data" in the Decoder. This block uses the standard decoder
patterns shown in the Valid Data Characters and Valid Special
Character Codes and Sequences sections of this datasheet. Data
patterns are signaled by a LOW on the SC/D output and Special
Character patterns are signaled by a HIGH on the SCID output.
Unused patterns or disparity errors are signaled as errors by a
HIGH on the RVS output and by specific Special Chiuacter codes.
Output Register
The Output register holds the recovered data (00-7, SCID, and
RVS) and aligns it with the recovered byte clock (CKR). This synchronization insures proper timing to match a FIFO interface or
other logic that requires glitch free and specified output behavior.
Outputs are changed synchronously with the rising edge of CKR.
In BIST mode, this register becomes the signature pattern generator and checker by logically converting the parallel output register
into a Linear Feedback Shift Register (LFSR) pattern generator.
When enabled, this LFSR will generate a 511-byte sequence that
includes all Data and Special Character codes, including the explicit violation symbols. This pattern provides a predictable but pseudo-random sequence that can be. matched to an identical LFSR in
the Transmitter. When synchronized, it checks each byte in the Decoder with each byte generated by the LFSR and shows errors at
RVS. Patterns generated by the LFSR are compared after being
buffered to the output pins and then fed back to the comparators,
allowing test of the entire receive function.
In BIST mode, the LFSR is initialized by the first occurrence of the
transmitter BIST loop start code DO.O (DO.O is sent only once per
BIST loop). Once the BIST loop has been started, RVS will be
HIGH for pattern mismatches between the received sequence and
the internally generated sequence. Code rule violations or running
disparity errors that occur as part of the BIST loop will not cause an
error indication. RDY will pulse HIGH once per BIST loop and
can be used to check test pattern progress. The receiver BIST generator can be reinitialized by leaving and re-entering BIST mode.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic for the decoder. Test logic is discussed
in more detail in the CY7B933 HOTLink Receiver Operating
Mode Description.
7-6
CY7B923
CY7B933
~
~~pRF.SS
SEMICONDUCTOR
PRELIMINARY
~;;
CY7B923/CY7B933 Electrical Characteristics Over the Operating Rangel l ]
Parameter
Description
Test Conditions
Min.
Max.
Unit
0.45
V
'fransmitter TTL-Compatible Pins: DO-7, ~CID, S~NA, ENN, CKw, FOTO, BISTEN, RP
Receiver TTL-Compatible Pins: QO-7' SCID, RVS, RDY, CKR, REFCLK, RF, BISTEN, SO
VOHT
Output HIGH Voltage
IOH = - 2 rnA
VOLT
Output LOW Voltage
IOL = 4 rnA
2.4
V
lOST
Output Short Circuit Current
VOUT =OV[2]
-15
-90
rnA
VIHT
Input HIGH Voltage
2.0
Vee
V
VILT
Input LOW Voltage
- 0.5
0.8
V
IIHT
Input HIGH Current
VIN= Vee
-10
+10
lILT
Input LOW Current
VIN = O.OV
- 500
fAA
fAA
'fransmitter ECL-Compatible Output Pins: OUTA+, OUTA-, OUTB+, OUTB-, OUTC+, OUTCVOHE[3]
Output HIGH Voltage (Vee referenced)
Load = 50 ohms to Vee - 2V
Vee-1.03
Vee- 0.83
V
VOLE
Output LOW Voltage (Vee referenced)
Load = 50 ohms to Vee - 2V
Vee-1.81
Vee- 1.68
V
VODIF
Output Differential Voltage
~OUT+HIGH) to (OUT-LOW~ or
OUT+LOW) to (OUT-HIGH
Load = 50 ohms to Vee - 2V
0.6
V
VIHE
Input HIGH Voltage
Vee-1.17
Vee
V
VILE
IIHE[4]
Input LOW Voltage
2.0
Vee- 1.48
V
Input HIGH Current
VIN = VIHE Max.
+500
IILE[4]
Input LOW Current
VIN = VILLMin.
fAA
fAA
•
mV
C
Receiver ECL-Compatible Input Pins: AlB, SI, INB
+0.5
Differential Line Receiver Input Pins: INA+, INA-, INB+, INBVDIFF
Input Differential Voltage
I(IN+) - (IN-)I
VIHH
Highest Input HIGH Voltage
VILL
Lowest Input LOW Voltage
IIHH
Input HIGH Current
IILL[5]
Input LOW Current
50
1200
Vee
VIN = VIHH Max.
VIN = VILL Min.
V
V
2.0
750
fAA
fAA
-200
Miscellaneous
lecr[6]
Transmitter Power Supply Current
Vee = Max., TA = Max.,
Freq. = Max. (One ECLoutputpair
loaded with 50 ohms to
Vee - 2.0V, others tied to Ved
85
rnA
leeR
Receiver Power Supply Current
Vee = Max., TA = Max.,
Freq. = Max., RF = LOW
155
rnA
Capacitance[7]
Parameter
Description
Input Capacitance
Test Conditions
TA = 25°C, fo = 1 MHz, Vee = 5.0V
Notes:
1. See the last page of this specification for Group A subgroup testing
information.
2. Tested one output at a time, output shorted for less than one second,
less than 10% duty cycle.
3. Specified only for temperatures above O°c.
4. Applies to AlB only.
5. Input currents are always positive at all voltages above Vcd2.
6.
7.
7-7
Icer includes current into V CCQ (pin 9 and pin 22) only. Current into
V CCN is determined by ECL load currents, typically 30 rnA with 50
ohms to V cc - 2Y. Each additional enabled ECL pair adds 5 rnA to
Icer and additional load current to V CCN as described.
Tested initially and after any design or process changes that may affect
these parameters.
==
o
o
~
icC
~~PRFSS
CY7B923
CY7B933
PRELIMINARY
. , ·SEMICONDUcrOR
AC Test Loads and Waveforms
v
OUTPUT
R1 = 9l0Q
R2 = 510Q
Cl < 30 pF
(Includes fixture and
probe capacitance)
~
clI
-
R1
1_
_ _....-_ _...IAA - - - "
~
Cl
R2
-
(a) TTL AC Test Lo~d[8]
Vee -. 2
Y.-------'"
Rl=50Q
Rl
CL< 5 pF
(Includes fixture and
probe capacitance)
(b) ECL AC Test Load[8]
B923-5
3.0V
3.0V---2.0V
GND
B923-7
(c) TTL Input Test Waveform
(d) ECL Input Test Waveform
Transmitter Switching Characteristics Over the Operating Range[l]
7B923
Description
Max.
Unit
tCKW
Write Clock Cycle
30.3
62.5
ns
tB
Bit Timel9]
3.03
6.25
tCPWH
CKWPulse Width HIGH
Parameter
tCPWL
CKW Pulse Width LOW
tSD
Data Set-Up Time[lO]
tl:lD
Data Hold Timel lO]
tSENP
Enable Set-Up Time (to insure correct RP)[ll]
tHENP
Enable Hold Time (to insure correct RP)[l1]
Read Pulse Rise Alignmentl l2]
...
Min.
ns
5
ns
5
ns
~
tpDR
5
ns
0
ns
6tB
+8
lOtB
ns
2
ns
0
-4
ns
tpPWH
Read Pulse HIGH[12]
4tB-3
ns
tpop
Read Pulse Fall Alignmentl l2]
6tB-3
ns
tRISE
tpALL
ECL Output Rise Time 20-80% (ECL Test Load)
1.2
ns
ECL Output Fall Time 80-20% (ECL Test Load)
1.2
ns
Notes:
8. . Cypress uses constant current (ATE) load configurations and forcing
functions. This figure is for reference only.
Transmitter tB is calculated as tCKW/10. The byte rate is one tenth of
the bit rate.
10. Data includes DO-7, SOD, SVS, ENA, ENN, and BlSTEN. tSD and
tHD minimum timing assures correct data load on rising edge of CKw,
but. not RP function or timing.
9.
11. tSENP and tHENP timing insures correct RP function and correct data
load on the rising edge of CKw.
12. Loading on RP pin is ~2 rnA and ~15 pF.
7-8
=;;-
.~
CY7B923
CY7B933
PRELIMINARY
~CYPRF.SS
~.L SEMICONDUCTOR
Receiver Switching Characteristics Over the Operating Rangd 1]
7B933
Parameter
Description
Unit
Min.
Max.
-1
+1
%
3.03
6.25
ns
tB
Read Clock Period (No Serial Data Input), REFCLK as Referencd 13]
Bit Timd 14]
tCPRH
Read Clock Pulse HIGH
5tB-3
ns
tCPRL
Read Clock Pulse LOW
5tB-3
ns
tCKR
tRH
RDY Hold Time
tB-3
ns
tpRF
RDY Pulse Fall to CKR Rise
5tB-3
ns
tpRH
4tB-3
tA
RDY Pulse Width HIGH
Data Access Timd 15, 16]
tROH
Data Hold Timd 15, 16]
tB-3
tCKX
REFCLK Clock Period Referenced to CKW of Transmitterl 17]
-0.1
tCPXH
REFCLK Clock Pulse HIGH
5
tCPXL
REFCLK Clock Pulse LOW
5
tDS
Propagation Delay SI to SO (note ECL and TTL thresholds)[18]
2tB-3
Notes:
13. The period of tCKR will match the period of the transmitter CKW
when the receiver is receiving serial data. When data is interrupted,
CKR may drift to one of the range limits above.
14. Receiver tB is calculated as tCKR/lO if no data is being received, or
tCKW/I0 if data is being received. See note 9.
IS. Data includes QO-7, SCJD, and RVS.
16. tA and tRQH specifications are only valid if all outputs (CKR, RDY,
QO-7, SC/D, and RVS) are loaded with similar DC and AC loads.
ns
2tB+3
ns
ns
+0.1
%
ns
ns
20
ns
17. REFCLK has no phase or frequency relationship with CKR and only
acts as a centering reference to reduce clock synchronization time.
REFCLKmust be within 0.1 % ofthe transmitter CKW frequency, necessitating a ±SOO-PPM crystal.
18. The ECL switching threshold is the midpoint between the ECLVOH, and VOL specification (approximately VCC - 1.3SV). The TIL
switching threshold is l.Sy.
7
0
II::
o
~
ic(
Q
7-9
.~
PRELIMINARY
~=CYPRESS
~, SEMICONDUcrOR
CY7B923
CY7B933
Switching Waveforms for the CY7B923 HOTlink Transmitter
tCKW
CKW
0 0-07 ,
SC/TI,
SVS,
STSTEN
tCKW
CKW
0 0-07 ,
scm,
svs,
BTSTEN
B923-9
7-10
.. ~
PRELIMINARY
_'=CYPRESS
_
_,
SEMICONDUcrOR
CY7B923
CY7B933
Switching Waveforms for the CY7B933 HOTlink Receiver
14-------
tCKR - - - - - - - - '
CKR
....- - - tpRF ---~
00 - 07,
8C/D, RV8
8923-10
•
REFCLK[17]
81
-tDS
80
NOTE 18
1.SV
8923-12
7-11
_
k.:~
CY7B923
CY7B933
PRELIMINARY
'il CYPRESS
_ , SEMICONDUCfOR
CY7B923 HOTlink Transmitter Operating Mode
Description
Encoded Mode Operation
The CY7B923 Transmitter operating with the CY7B933 Receiver
forms a general-purpose data communication subsystem capable
of transporting user data at up to 33 Mbytes per second over several types of serial interface media. In normal operation, the Transmitter can operate in either of two modes. The Encoded mode allows a user to send and receive eight (8) bit data and control
information without first converting it to transmission characters.
The Bypass mode is used for systems in which the encoding and decoding is performed in an external protocol controller.
In either mode, data is loaded into the input register of the Transmitter on the rising edge of CKW. The input timing and functional
response of the Transmitter input can be made to match timing and
function of either an asynchronous FIFO or a clocked FIFO by an
app~opriate connec~ion of input signals (SeePigure 2). Proper operation of the FIFO mterface depends upon various FIFO-specific
access and response specifications.
a::
...J
...J
I-
z
The diagnostic characters and sequences available as Special Characters include those for Fibre Channel link testing, as well as codes
to be used for testing system response to link errors and timing. A
Violation symbol can be explicitly sent as part of a user data packet
(Le., send CO.7;D7-0 = 111 00000 and SC/D = l),oritcanbesent
in response to an external system using the SVS input. This will allow system diagnostic logic to evaluate the errors in an unambiguous manner, and will not require any modification to the transmission interface to force transmission errors for testing purposes.
ASYNCHRONOUS FIFO
CLOCKED FIFO
7C42X!3X!6X!7X
7C44X!5X
,,
w
oa::
In Encoded mode the input data is int~reted as eight bits of data
(Do - D7), a context control bit (SCID), and a system diagnostic
input bit (SV1). If the context of the data is to be normal message
data, the SCID input will be LOW, and the data will be encoded using the valid data character set described in the Valid Data Characters section ofthis datasheet. If the context of the data is to be control or protocol information, the SC/D input will be HIGH, and the
data will be encoded using the valid special character set described
in the Valid Special Character Codes and Sequences section. Special characters include all protocol characters necessary to encode
pac~ets for Fibre Channel, ESCON, proprietary systems, and diagnostIc purposes.
R
ENR
00-8
/' ~
I~
•
I
oo
:E
oa::
Ef\JA
LL
CKW
1
Rp
CKR
Do -7, SC/O
00-8
j
/'
,
II
,
ENf\J
CKW
,/ 9
Do -7. SC/O
78923
78923
HOTLINK TRANSMITTER
HOTLINK TRANSMITTER
HOTLINK RECEIVER
HOTLINK RECEIVER
7B933
CKR
-
ROY
78933
CKR
00 -7. SC/O
I
,d','"
ROY
00-7. SC/O
V
/' 9
V
9
,
,
,
,
Do - 8
CKW
ENW
Do - 8
I
IN
/'
7C42X!3X!6X!7X
7C44X!5X
ASYNCHRONOUS FIFO
CLOCKED FIFO
Figure 2. Seamless FIFO Interface
7-12
B923-13
~~
;); CYPRESS
PRELIMINARY
=t:
,
CY7B923
CY7B933
SEMICONDUCTOR
Bypass Mode Operation
In Bypass mode the input data is interpreted as ten (10) ~its
(Db-h), SC;D (Da), and SVS (Dj) of ~re-enc?ded transmiSSIOn
data to be serialized and sent over the lmk. This data can use any
encoding method suitable to the designer. ~he ~nly restric~i?ns
upon the data encoding method is that it con tam sUitable transItion
density for the Receiver PLL data synchronizer (one per byte), and
that it be compatible with the transmission media.
Data loaded into the Input register on the rising edge of CKW will
be loaded into the Shifter on the subsequent rising edges of CKw.
It will then be shifted to the outputs one bit at a time using the internal clock generated by the clock generator. The first bit of the
transmission character (Da) will appear at the output (OUTA±,
OUTB±, and OUTC±) after the next CKW edge.
While in either the Encoded mode or Bypass mode, if a CKW edge
arrives when the inputs are not enabled (ENA and ENN both
HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0)
to maintain proper link synchronization (in Bypass mode th.e proper sense of running disparity cannot be guaranteed for the fIrS.t pad
character but is correct for all pad characters that follow). ThiS automatic i~sertion of pad characters can be inhibited by i!1suring
that the Transmitter is always enabled (i.e., ENAJENN IS hardwired LOW).
ECL Output Functional and Connection Options
The three pairs of ECL outputs all cont~in the s.ame inform~tion
and are intended for use in systems With multiple connectIOns.
Each output pair may be ~onnected to a d.ifferent seri~l media,
each of which may be a different length, hnk type, or mterface
technology. For systems that do not require all three output pairs,
the unused pairs should be wired to Vee to minimize the po~er
dissipated by the output circuit, and to minimize unwanted nOise
generation.
In systems that require the outputs to be shut off during some periods when link transmission is prohibited (e.g., for laser safetyfunctions) the FOTO input can be asserted. While it is possible to insure that the output state of the ECL d~iv.ers is L31% of tli. 1:ypically
measured while rec~iving datacarned by a bandwidth-limited
channel (e.g., a coaxial transmission line) while maintaining a
Bit Error Rate (BER) <10- 12•
Random Jitter tolerance (Rj) > 42% of tB. Typically measured while receiving data carried by a random-noise-limited
ch~mnel (e.g., a fiber-optic transmission system with low light
levels) while maintaining.a Bit Error Rate (BER) <10-[2.
Total Jitter toleranc~ > 70% of tB. Total of Dj + Rj.
PLL-Acquisition time <2500-bit time,s from worst-case phase
or frequency change in the serial input data stream, to receiving data within BER objective of 10- 12. Stable power supplies
within specifications, stable REFCLK input frequency and
normal<;lataframing protocols are assumed.
Receiver Test Mode Description
The CY7B933 Receiver offers two types of test mode operation,
BIST mode and Test mode. In a normal system application, the
Built-In Self-lest (BIST) mode can be used to check the functionality of the Transmitter, the Receiver and the link connecting them.
This mode is available with minimal impact on user system logic,
and can be used as part of the normal system diagnostics. Typical
connections and timing are shown in Figure 3.
BISTMode
BIST Mode. function is as follows:
1. Set BISTEN LOW to enable self-test generation and await
RDY LOW indicating that the initialization code has been received.
2. Monitor RVS and check for a~e time with the pin HIGH to
detect pattern mismatches. RDY will pulse HIGH once per
BIST loop, and can be used by anex~rnal counter to monitor
test pattern progress.·00-7 and SCID will show the .expected
pattern and may be useful for debug purposes..
3. When testing is completed, set BISTENHIGH and resume normal function.
Note: A specific test of the RVS output may be required to assure
an adequate test. To perform this test, it is only necessary to have
the Transmitter send violation (SVS = HIGH) for a few bytes before beginning the BIST test sequence. Alternatively, the Receiver
could enter BIST mode after the Transmitter has begun sending
BIST loop data, or be removed before the Transmitter finishes
sending BISTloops, each ofwhich contain several deliberate violations and should cause RVS to pulse HIGH.
BIST mode is intended to check the entire function of the Transmitter, serial link, and Receiver. It augments normal factory ATE
testing and provides the user system with a rigorous test mechanism to check the link transmission system, without requiring any
significant system overhead.
When in Bypass mode, the BISTlogicwill function in the same way
as in the Encoded mode. MODE = HIGH and BISTEN = LOW
causes the Receiver to switch to Encoded mode and begin checking
the decoded received data of the BIST pattern, as if MODE =
LOW. When BISTEN returns to HIGH, the Receiver resumes normal Bypass operation. In Test mode the BIST function works as in
the normal mode.
Test Mode
The MODE input pin selects between three receiver functional
modes. Whenwir~d t,o Vee, the Shifter contents bypaSs the Decod-
CY7B923
CY7B933
er and go directly from the Decoder latch to the Oa-j inputs of the
Output latch. When wired to GND, the outputs are decoded using
the 8B/lOB codes shown at the end of this datasheet and become
00-7, RVS, and SC!D. The third function is Test mode, J.1sed for
factory or incoming device test. This mode can be selected by leaving. the MODE pin open (internal circuitry forces the open pin to
Vcd2).
Test mode causes the Receiver to function in its Encoded mode,
but with INB (INB+ ) as the bit rate Test clock instead of the Internal PLL generated bit clock. In this mode, transfers between the
Shifter, Decoder register and Output register are controlled by
their normal logic, but with an external bit rate clock instead of the
PLL (the recovered bit clock). Internallogic and test pattern inputs
can be synchronized by sending a SYNC pattern and allowing the
Framer to align the logic to the bit stream. The flow is as follows:
1. Assert Test mode for several test clock cycles to establish normal
counter sequence.
2. Assert RF to enable reframing.
3. Input a repeating sequence of bits representing K28.5 (Sync).
4. RDY falling shows the byte boundary established by the K28.5
input pattern.
'
5. Proceed with pattern, voltage and timing tests as is convenient
for the test program and tester to be used.
(While in Test mode and in BIST mode with RF HIGH, the 00-7,
RVS, and SC!D outputs reflect various internal logic states and not
the received data.)
Test mode is intended to allow logical, DC, and AC testing of the
Receiver without requiring that the tester generate input data at
the bit rate or accommodate the PLL lock, tracking and frequency
range characteristics that are required when the part operates in its
'
normal mode.
X3T9.3 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight
bits at a time into a lO-bit Transmission Character and then sent
serially, bit by bit. Information received over a serial link is collected ten bits at a time, and those Transmission Characters that
are used for data (Data Characters) are decoded into the correct
eight-bit codes. The lO-bit Transmission Code supports all 256
8-bit combinations. Some ofthe remaining Transmission Characters (Special Characters) are used for functions other than
data transmission.
The primary rationale for use of a Transmission Code is to improve
the transmission characteristics of a serial link. The encoding defined by the Transmission Code ensures that sufficient transitions
are present in the serial bit stream to make clock recovery possible
at the Receiver. Such encoding also greatly increases the likelihood
of detecting any single or multiple bit errors that may occur during
transmission and reception of information. In addition, some Special Characters of the Transmission Code selected by Fibre Channel Standardconsist of a distinct and easily recognizable bit'pattern
(the Special Character Comma) that assists a Receiver in achieving
word alignment on the incoming bit stream.
Notation Conventions
The documentation for the 8B/10B Transmission Code uses letter
notation for the bits in an 8-bit byte. Fibre Channel Standard notation uses a bit notation of A, B, C, D, E, E G,H for the 8-bit byte
for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, jfor encoded lO-bit data. There is a correspondence between bit A and bit
a, Band b, C and c, D and d, E and e, F andf, G and g, and Hand
7-16
•
&.:.~
.... CYPRESS
,
PRELIMINARY
CY7B923
CY7B933
SEMICONDUCTOR
h. Bits i and j are derived, respectively, from (A,B,C,D,E) and
(F,G,H).
The bit labeled A in the description of the 8B/lOB Transmission
Code corresponds to bit 0 in the numbering scheme of the FC-2
specification, B corresponds to bit 1, as shown below.
FC-2 bit designation7 6 5 4 3 2 1 0
HOTLink D/Q designation- 7 6 5 4 3 2 1 0
8B/lOB bit designationH G FED C B A
To clarify this correspondence, the following example shows the
conversion from an FC-2 Valid Data Byte to a Transmission Character (using 8B/lOB Transmission Code notation)
FC-2 45
Bits: 7654 3210
0100 0101
Converted to 8B/lOB notation (note carefully thatthe order of bits
is reversed):
Data Byte Name D5.2
Bits:ABCDE FGH
10100 010
Translated to a transmission Character in the 8B/lOB Transmission
Code:
Bits:abcdei ighj
101001 0101
Each valid Transmission Character of the 8B/10B Transmission
Code has been given a name using the following convention: cxx.y,
where c is used to show whether the Transmission Character is a
Data Character (c is set to D, and the SCiD pin is LOW) or a Special Character (c is set to K, and the SC;D pin is HIGH). When c is
set to D, xx is the decimal value of the binary number composed of
the bits E, D, C, B, and A in that order, and the y is the decimal value of the binary number composed of the bits H, G, and F in that
order. When c is set to K, xx and yare derived by comparing the
encoded bit patterns of the Special Character to those patterns
derived from encoded Valid Data bytes and selecting the names of
the patterns most similar to the encoded bit patterns of the Special
Character.
Under the above conventions, the Transmission Character used for
the examples above, is referred to by the name D5.2. The Special
Character K29.7 is so named because the first six bits (abcdei) of
this character make up a bit pattern similar to that resulting from
the encoding of the unencoded 11101 pattern (29), and because
the second four bits (fghj) make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern (7).
Note: This definition of the lO-bit Transmission Code is based on
(and is in basic agreement with ) the following references, which describe the same lO-bit transmission code.
AX. Widmer and P.A Franaszek. ''A DC-Balanced, PartitionedBlock, 8B/10B Transmission Code" IBM Journal of Research and
Development, 27, No.5: 440-451 (September, 1983).
U.S. Patent 4,488,739. Peter A Franaszek and Albert X. Widmer.
"Byte-Oriented DC Balanced (0.4) 8B/10B Partitioned Block
Transmission Code" (December 4,1984).
Fibre
Channel
Physical
Level
(FC]Hl92-00lR3.0,
X3T9.3/92-092). Working draft proposed for American National
Standard for Information Systems, Rev 3.0 June 16, 1992.
IBM Enterprise Systems Architecture/390 ESCON I/O Interface
(document number SA22-n02).
8B/10B Transmission Code
The following information describes how the tables shall be used
for both generating valid Transmission Characters (encoding) and
checking the validity of received 1tansmission Characters (decoding). It also specifies the ordering rules to be followed when transmitting the bits within a character and the characters within the
higher-level constructs specified by the standard.
Transmission Order
Within the definition of the 8B/lOB 1tansmission Code, the bit
positions of the Transmission Characters are labeled a, b, c, d, e, i,
f, g, h, j. Bit "a" shall be transtnitted first followed by bits b, c, d, e,
i, f, g, h, and j in that order. (Note that bit i shall be transmitted between bit e and bit f, rather than in alphabetical order.)
Valid and Invalid Transmission Characters
The following tables define the valid Data Characters and valid
Special Characters (K characters), respectively. The tables are
used for both generating valid Transmission Characters (encoding)
and checking the validity of received Transmission Characters (decoding). In the tables, each Valid-Data-byte or Special-Charactercode entry has two columns that represent two (not necessarily different) Transmission Characters. The two columns correspond to
the current value of the running disparity ("Current RD-" or
"Current RD + "). Running disparity is a binary parameter with either the value negative ( - ) or the value positive ( + ).
After powering on, the Transmitter may assume either a positive or
negative value for its initial running disparity. Upon transmission
of any Transmission Character, the transmitter will select the properversion ofthe Transmission Character based on the current run- :E
ning disparity value, and the Transmitter shall calculate a new value 0
for its running disparity based on the contents of the transmitted 0
character. Special Character codes C1.7 and C2.7 can be 4sed to ~
force the transmission of a specific Special Character with a specif- ic(
ic running disparity as required for some special sequences in Q
X3T9.3.
After powering on, the Receiver may assume either a positive or
negative value for its initial running disparity. Upon reception of
any Transmission Character, the Receiver shall decide whether the
Transmission Character is valid or invalid according to the following rules and tables and shall calculate a new value for its Running
Disparity based on the contents of the received character.
The following rules for running disparity shall be used to calculate
the new running-disparity value for Transmission Characters that
have been transmitted (Transmitter's running disparity) and that
have been received (Receiver's running disparity).
Running disparity for a Transmission Character shall be calculated
from sub-blocks, where the first six bits (abcdei) form one subblock and the second four bits (fghj) form the other sub-block.
Running disparity at the beginning ofthe 6-bit sub-block is the running disparity at the end of the previous Transmission Character.
Running disparity at the beginning of the 4-bit sub-block is the running disparity at the end of the 6-bit sub-block. Running disparity
at the end of the Transmission Character is the running disparity at
the end of the 4-bit sub-block.
Running disparity for the sub-blocks shall be calculated as follows:
1. Running disparity at the end of any sub-block is positive if the
sub-block contains more ones than zeros. It is also positive at
the end of the 6-bit sub-block if the 6-bit sub-block is 000111,
and it is positive at the end of the 4-bit sub-block if the 4-bit subblock is 0011.
2. Running disparity at the end of any sub-block is negative if the
sub-block contains more zeros than ones. It is also negative at
7-17
•
~~
~=CYPRESS
CY7B923
CY7B933
PRELIMINARY
.~, SEMICONDUCTOR
the end of the 6-bit sub-block if the 6-bit sub-block is 111000,
and it is negative at the end of the 4-bit sub-block if the 4-bit
sub-block is 1100.
.
3. Otherwise, running disparity at the end of the sub-block is the
same as at the beginning of the sub-block.
Use of the Tables for Generating Transmission Characters
The appropriate entry in the table shall be found for the Valid Data
byte or the Special Character byte for which a 'D:ansmission Character is to be generated (encoded). The current value of the Transmitter's running disparity shall be used to select the Transmission
Character from its corresponding column. For each Transmission
Character transmitted, a new value ofthe running disparity shall be
calculated. This new value shall be used as the Transmitter's current running disparity for the next Valid Data byte or Special Character byte to be encoded and transmitted. Table 1 shows naming
notations and examples of valid transmission characters.
Table 1. Valid Transmission Characters
Data
Use of the Tables for Checking the Validity of Received Transmission Characters
The column corresponding to the current value of the Receiver's
running disparity shall be searched for the received 'D:ansmission
Character. If the received Transmission Character is found in the
proper column, then the Transmission Character is valid and the
associated Data byte or Special Character code is determined (decoded). If the received Transmission Character is not found in that
column, then the Transmission Character is invalid. This is called a
code violation. Independentofthe Transmission Character's validity, the received Transmission Character shall be used to calculate
a new value of running disparity. The new value shall be used as the
Receiver's current running disparity for the next received Transmission Character.
Detection of a code violation does not necessarily show that the
Transmission Character in which the code violation was detected is
in error. Code violations may result from a prior error that altered
the running disparity of the bit stream which did not result in a detectable error at the Transmission Character in which the error occurred. Table 2 shows an example of this behavior.
DIN or QOUT
Byte Name
765
43210
Hex Value
DO.O
000
00000
00
Dl. 0
000
00001
01
D2.0
000
00010
02
D5.2
010
000101
45
D30.7
111
11110
FE
111
11111
FF
D31.7
Table 2. Code Violations Resulting from Prior Errors
RD
Character
RD
Character
RD
Character
RD
Transmitted data character
-
D21.1
DlO.2
-
101010 1001
-
D23.5
Transmitted bit stream
+
+
111010 1010
+
+
Code Violation
+
+
+
+
Bit stream after error
Decoded data character
101010 1011
D21.0
7-18
0101010101
0101010101
DlO.2
111010 1010
·4
-·itECYPRESS
==.
--=-,
CY7B923
CY7B933
PRELIMINARY
SEMICONDUCTOR
Valid Data Characters (SC/D = LOW)
fghj
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
fghj
1011
DO.1
001
00000
100111
1001
011000
1001
100010
1011
Dl.1
001
00001
011101
1001
100010
1001
010010
1011
D2.1
001
00010
101101
1001
010010
1001
001
00011
110001
1001
110001
1001
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
DO.O
000
00000
100111
0100
011000
Dl. 0
000
00001
011101
0100
D2.0
000
00010
101101
0100
Bits
Current RD-
Current RD+
Bits
Current RD-
Current RD+
D3.0
000
00011
110001
1011
110001
0100
D3.1
D4.0
000
00100
110101
0100
001010
1011
D4.1
001
00100
110101
1001
001010
1001
D5.0
000
00101
101001
1011
101001
0100
D5.1
001
00101
101001
1001
101001
1001
D6.0
000
00110
011001
1011
011001
0100
D6.1
001
00110
011001
1001
011001
1001
D7.0
000
00111
111000
1011
000111
0100
D7.1
001
00111
111000
1001
000111
1001
DB.O
000
01000
111001
0100
000110
1011
DB.1
001
01000
111001
1001
000110
1001
D9.0
000
01001
100101
1011
100101
0100
D9.1
001
01001
100101
1001
100101
1001
D10.0
000
01010
010101
1011
010101
0100
D10.1
001
01010
010101
1001
010101
1001
D11.0
000
01011
110100
1011
110100
0100
D1l.1
001
01011
110100
1001
110100
1001
D12.0
000
01100
001101
1011
001101
0100
D12.1
001
01100
001101
1001
001101
1001
D13.0
000
01101
101100
1011
101100
0100
D13.1
001
01101
101100
1001
101100
1001
D14.0
000
01110
011100
1011
011100
0100
D14.1
001
01110
011100
1001
011100
1001
D15.0
000
01111
010111
0100
101000
1011
D15.1
001
01111
010111
1001
101000
1001
D16.0
000
10000
011011
0100
100100
1011
D16.1
001
10000
011011
1001
100100
1001
D17.0
000
10001
100011
1011
100011
0100
D17.1
001
10001
100011
1001
100011
1001
D1B.0
000
10010
010011
1011
010011
0100
D1B.1
001
10010
010011
1001
010011
1001
D19.0
000
10011
110010
1011
110010
0100
D19.1
001
10011
110010
1001
110010
1001
D20.0
000
10100
001011
1011
001011
0100
D20.1
001
10100
001011
1001
001011
1001
D21.0
000
10101
101010
1011
101010
0100
D21.1
001
10101
101010
1001
101010
1001
001
10110
011010
1001
011010
1001
D22.0
000
10110
011010
1011
011010
0100
D22.1
D23.0
000
10111
111010
0100
000101
1011
D23.1
001
10111
111010
1001
000101
1001
D24.0
000
11000
110011
0100
001100
1011
D24.1
001
11000
110011
1001
001100
1001
D25.0
000
11001
100110
1011
100110
0100
D25.1
001
11001
100110
1001
100110
1001
D26.0
000
11010
010110
1011
010110
0100
D26.1
001
11010
010110
1001
010110
1001
D27.0
000
11011
110110
0100
001001
1011
D27.1
001
11011
110110
1001
001001
1001
0100
D2B.1
001
11100
001110
1001
001110
1001
11100
001110
000
11101
101110
0100
010001
1011
D29.1
001
11101
101110
1001
010001
1001
000
11110
011110
0100
100001
1011
D30.1
001
11110
011110
1001
100001
1001
000
11111
101011
0100
010100
1011
D31.1
001
11111
101011
1001
010100
1001
D2B.0
000
D29.0
D30.0
D31.0
1011
001110
7-19
•
::E
o
o
~
icC
Q
~
~~PRESS
~JF SEMICONDUCTOR
Valid Data Characters (SCI))
Data
Byte
Name
HGF
DO.2
CY7B923
CY7B933
PRELIMINARY
= LOW) (continued)
Current RD-
CurrentRD+
CurrentRD+
abcdei
fgbj
abcdei
fgbj
Data
Byte
Name
CurrentRD-
EDCBA
HGF
EDCBA
abcdei
fgbj
abcdei
fgbj
010
00000
100111
0101
011000
0101
DO.3
011
00000
100111
0011
011000
1100
D1.2
010
00001
011101
0101
100010
0101
D1.3
011
00001
011101
0011
100010
1100
D2.2
010
00010
101101
0101
010010
0101
D2.3
011
00010
101101
0011
010010
1100
D3.2
010
00011
110001
0101
110001
0101
D3.3
011
00011
110001
1100
110001
0011
D4.2
010
00100
110101
0101
001010
0101
D4.3
011
00100
110101
0011
001010
1100
Bits
Bits
D5.2
010
00101
101001
0101
101001 . 0101
D5.3
011
00101
101001
1100
101001
0011
D6.2
010
00110
011001
0101
011001
0101
D6.3
011
00110
011001
1100
011001
0011
D7.2
010
00111
111000
0101
000111
0101
D7.3
011
00111
111000
1100
000111
0011
DB.2
010
01000
111001
0101
000110
0101
DB.3
011
01000
111001
0011
000110
1100
0011
D9.2
010
01001
100101
0101
100101
0101
D9.3
011
01001
100101
1100
100101
DlO.2
010
01010
010101
0101
010101
0101
D10.3
011
01010
010101
1100
010101
0011
Dl1.2
010
01011
110100
0101
110100
0101
D11. 3
011
01011
110100
1100
110100
0011
Dl2.2
010
01100
001101
0101
001101
0101
D12.3
011
01100
001101
1100
001101
0011
Dl3.2
010
01101
101100
0101
101100
0101
D13.3
011
01101
101100
1100
101100
0011
Dl4.2
010
01110
011100
0101
011100
0101
D14.3
011
01110
011100
1100
011100
0011
Dl5.2
010
01111
010111
0101
101000
0101
D15.3
011
01111
010111
0011
101000
1100
Dl6.2
010
10000
011011
0101
100100
0101
D16.3
011
10000
011011
0011
100100
1100
Dl7.2
010
10001
100011
0101
100011
0101
D17.3
011
10001
100011
1100
100011
0011
DlB .2
010
10010
010011
0101
010011
0101
D1B.3
011
10010
010011
1100
010011
0011
Dl9.2
010
10011
110010
0101
110010
0101
D19.3
011
10011
110010
1100
110010
0011
D20.2
010
10100
001011
0101
001011
0101
D20.3
011
10100
001011
1100
001011
0011
0011
D21.2
010
10101
101010
0101
101010
0101
D21.3
011
10101
101010
1100
101010
022.2
010
10110
011010
0101
011010
0101
D22.3
011
10110
011010
1100
011010
0011
D23.2
010
10111
111010
0101
000101
0101
D23.3
011
10111
111010
0011
000101
1100
D24.2
010
11000
110011
0101
001100
0101
D24.3
011
11000
110011
0011
001100
1100
D25.2
010
11001
100110
0101
100110
0101
D25.3
011
11001
100110
1100
100110
0011
D26.2
010
11010
010110
0101
010110
0101
D26.3
011
11010
010110
1100
010110
0011
D27.2
010
11011
110110
0101
001001
0101
D27.3
011
11011
110110
0011
001001
1100
D2B.2
010
11100
001110
0101
001110
0101
D2B.3
011
11100
001110
1100
001110
0011
D29.2
010
11101
101110
0101
010001
0101
D29.3
011
11101
101110
0011
010001
1100
D30.2
010
11110
011110
0101
100001
0101
D30.3
011
11110
011110
0011
100001
1100
031.2
010
11111
101011
0101
010100
0101
D31.3
011
11111
101011
0011
010100
1100
7-20
CY7B923
CY7B933
~
.
;~
PRELIMINARY
--====,
_·iECYPRESS
SEMICONDUCTOR
Valid Data Characters (SC/D = LOW) (continued)
Data
Byte
Name
Bits
HGF
EDCBA
Current RD-
CurrentRD+
abcdei
abcdei
fghj
Data
Byte
Name
fghj
Bits
HGF
EDCBA
Current RD-
Current RD+
abcdei
fghj
abcdei
fghj
011000
1010
1010
DO.4
100
00000
100111
0010
011000
1101
DO.S
101
00000
100111
1010
D1.4
100
00001
011101
0010
100010
1101
Dl. S
101
00001
011101
1010
100010
D2.4
100
00010
101101
0010
010010
1101
D2.S
101
00010
101101
1010
010010
1010
D3.4
100
00011
110001
1101
110001
0010
D3.S
101
00011
110001
1010
110001
1010
D4.4
100
00100
110101
0010
001010
1101
D4.S
101
00100
110101
1010
001010
1010
DS.4
100
00101
101001
1101
101001
0010
DS.S
101
00101
101001
1010
101001
1010
D6.4
100
00110
011001
1101
011001
0010
D6.S
101
00110
011001
1010
011001
1010
D7.4
100
00111
111000
1101
000111
0010
D7.S
101
00111
111000
1010
000111
1010
D8.4
100
01000
111001
0010
000110
1101
DB.S
101
01000
111001
1010
000110
1010
D9.4
100
01001
100101
1101
100101
0010
D9.S
101
01001
100101
1010
100101
1010
D10.4
100
01010
010101
1101
010101
0010
D10.S
101
01010
010101
1010
010101
1010
D11.4
100
01011
110100
1101
110100
0010
D11.S
101
01011
110100
1010
110100
1010
D12.4
100
01100
001101
1101
001101
0010
D12.S
101
01100
001101
1010
001101
1010
D13.4
100
01101
101100
1101
101100
0010
D13. S
101
01101
101100
1010
101100
1010
D14.4
100
01110
011100
1101
011100
0010
D14.S
101
01110
011100
1010
011100
1010
D1S.4
100
01111
010111
0010
101000
1101
D1S. S
101
01111
010111
1010
101000
1010
D16.4
100
10000
011011
0010
100100
1101
D16.S
101
10000
011011
1010
100100
1010
D17.4
100
10001
100011
1101
100011
0010
D17.S
101
10001
100011
1010
100011
1010
D1B.4
100
10010
010011
1101
010011
0010
D1B.S
101
10010
010011
1010
010011
1010
D19.4
100
10011
110010
1101
110010
0010
D19.S
101
10011
110010
1010
110010
1010
D20.4
100
10100
001011
1101
001011
0010
D20.S
101
10100
001011
1010
001011
1010
D21.4
100
10101
101010
1101
101010
0010
D21.S
101
10101
101010
1010
101010
1010
D22.4
100
10110
011010
1101
011010
0010
D22.S
101
10110
011010
1010
011010
1010
D23.4
100
10111
111010
0010
000101
1101
D23.S
101
10111
111010
1010
000101
1010
D24.4
100
11000
110011
0010
001100
1101
D24.S
101
11000
110011
1010
001100
1010
D2S.4
100
11001
100110
1101
100110
0010
D2S.S
101
11001
100110
1010
100110
1010
D26.4
100
11010
010110
1101
010110
0010
D26.S
101
11010
010110
1010
010110
1010
D27.4
100
11011
110110
0010
001001
1101
D27.S
101
11011
110110
1010
001001
1010
D2B.4
100
11100
001110
1101
001110
0010
D2B.S
101
11100
001110
1010
001110
1010
11101
101110
1010
010001
1010
D29.4
100
11101
101110
0010
010001
1101
D29.S
101
D30.4
100
D31.4
100
11110
011110
0010
100001
1101
D30.S
101
11110
011110
1010
100001
1010
11111
101011
0010
010100
1101
D31.5
101
11111
101011
1010
010100
1010
7-21
•
k
'~PRESS
CY7B923
CY7B933
PRELIMINARY
~IF SEMlCONDUcrOR
Valid Data Characters (SCll)
Data
Byte
Name
HGF
DO.6
= LOW) (continued)
CurrentRD-
CurrentRD+
fgbj
Data
Byte
Name
HGF
EDCBA
abcdei
fghj
abcdei
fgbj
011000
0110
DO.7
111
00000
100111
0001
011000
1110
0110
100010
0110
Dl. 7
111
00001
011101
0001
100010
1110
0110
010010
0110
D2.7
111
00010
101101
0001
010010
1110
110001
0110
110001
0110
D3.7
111
00011
110001
1110
110001
0001
00100
110101
0110
001010
0110
D4.7
111
00100
110101
0001
001010
1110
110
00101
101001
0110
101001
0110
D5.7
111
00101
101001
1110
101001
0001
D6.6
110
00110
011001
0110
011001
0110
D6.7
111
00110
011001
1110
011001
0001
D7.6
110
00111
111000
0110
000111
0110
D7.7
111
00111
111000
1110
000111
0001
D8.6
110
01000
111001
0110
000110
0110
D8.7
111
01000
111001
0001
000110
1110
Bits
CurrentRD-
CurrentRD+
EDCBA
abcdei
fgbj
abcdei
110
00000
100111
0110
Dl. 6
110
00001
011101
D2.6
110
00010
101101
D3.6
110
00011
D4.6
110
D5.6
Bits
D9.6
110
01001
100101
0110
100101
0110
D9.7
111
01001
100101
1110
100101
0001
D10.6
110
01010
010101
0110
010101
0110
D10.7
111
01010
010101
1110
010101
0001
DU.6
110
01011
110100
0110
110100
0110
D11. 7
111
01011
110100
1110
110100
1000
D12.6
110
01100
001101
0110
001101
0110
D12.7
111
01100
001101
1110
001101
0001
D13.6
110
01101
101100
0110
101100
0110
D13.7
111
01101
101100
1110
101100
1000
D14.6
110
01110
011100
0110
011100
0110
D14.7
111
01110
011100
1110
011100
1000
D15.6
110
01111
010111
0110
101000
0110
D1S.7
111
01111
010111
0001
101000
1110
D16.6
110
10000
011011
0110
100100
0110
D16.7
111
10000
011011
0001
100100
1110
D17.6
110
10001
100011
0110
100011
0110
D17.7
111
10001
100011
0111
100011
0001
D18.6
110
10010
010011
0110
010011
0110
D18.7
111
10010
010011
0111
010011
0001
D19.6
110
10011
110010
0110
110010
0110
D19.7
111
10011
110010
1110
110010
0001
D20.6
110
10100
001011
0110
001011
0110
D20.7
111
10100
001011
0111
001011
0001
D21.6
110
10101
101010
0110
101010
0110
D21.7
111
10101
101010
1110
101010
0001
D22.6
110
10110
011010
0110
011010
0110
D22.7
111
10110
011010
1110
011010
0001
D23.6
110
10111
111010
0110
000101
0110
D23.7
111
10111
111010
0001
000101
1110
D24.6
110
11000
110011
0110
001100
0110
D24.7
111
11000
110011
0001
001100
1110
D25.6
110
11001
100110
0110
100110
0110
D2S.7
111
11001
100110
1110
100110
0001
D26.6
110
11010
010110
0110
010110
0110
D26.7
111
11010
010110
1110
010110
0001
D27.6
110
11011
110110
0110
001001
0110
D27.7
111
11011
110110
0001
001001
1110
D28.6
110
11100
001110
0110
001110
0110
D28.7
111
11100
001110
1110
001110
0001
D29.6
110
11101
101110
0110
010001
0110
D29.7
111
11101
101110
0001
010001
1110
D30.6
110
11110
011110
0110
100001
0110
D30.7
111
11110
011110
0001
100001
1110
D31. 6
110
11111
101011
0110
010100
0110
D31.7
111
11111
101011
0001
010100
1110
7-22
.::=0=: _.
'~PRESS
~,
CY7B923
CY7B933
PRELIMINARY
SEMICONDUCTOR
Valid Special Character Codes and Sequences (sc/l> = HIGH) [19, 20]
Bits
S.C. Byte Name
S.C. Code Name
Current RD-
Current RD+
HGF
EDCBA
abcdei
fghj
abcdei
fghj
1011
K28.0
CO.O
(COO)
000
00000
001111
0100
110000
K28.1
Cl. 0
(COl)
000
00001
001111
1001
110000
0110
K28.2
C2.0
(CO2)
000
00010
001111
0101
110000
1010
K28.3
C3.0
(C03)
000
00011
001111
0011
110000
1100
K28.4
C4.0
(C04)
000
00100
001111
0010
110000
1101
K28.S
CS.O
(COS)
000
00101
001111
1010
110000
0101
K28.6
C6.0
(C06)
000
00110
001111
0110
110000
1001
K28.7
C7.0
(C07)
000
00111
001111
1000
110000
0111
K23.7
C8.0
(C08)
000
01000
111010
1000
000101
0111
K27.7
C9.0
(C09)
000
01001
110110
1000
001001
0111
K29.7
C10.0
(COA)
000
01010
101110
1000
010001
0111
K30.7
C1l. 0
(COB)
000
01011
011110
1000
100001
0111
Idle
CO.1
(C20)
001
00000
-K28. S+, D21. 4, D21. S, D21. S, repead 21 ]
R_RDY
Cl.1
(C21)
001
00001
-K28.S+,D21.4,D10.2,D10.2,repeat~~
EOFxx
C2.1
(C22)
001
00010
-K28 . S, Dn. xxxO[23]
+K28. S, Dn. xxx1[23]
C-SOF
C7.1
(C27)
001
00111
001111
1000
•
:i
0
Follows K28.1 for ESCON Connect-SOF (Rx indication only)
0
110000
0111
~
ic(
C
Follows K28.S for ESCON Passive-SOF (Rx indication only)
P-SOF
C7.2
(C47)
010
00111
Exception
CO.7
(CEO)
111
00000
-K28.S
Cl.7
(CE1)
111
00001
+K28.S
C2.7
(CE2)
111
00010
Exception
C4.7
(CE4)
111
00100
Notes:
19. All codes not shown are reserved.
20. Notation for Special Character Byte Name is consistent with Fibre
Channel and ESCON naming conventions. Special Character Code
Name is intended to describe binary information present on I/O pins.
Common usage for the name can either be in the form used for describing Data patterns (Le., CO.O through C31.7), or in hex notation
(Le., Cnn where nn=the specified value between 00 and FF).
21. CO.l = Transmit Negative K28.5 (- K28.5 +) disregarding Current
RDwhen input is held for only one byte time. If held longer, transmit-
7-23
001111
1000
110000
0111
Code Rule Violation and SVS Tx Pattern
1000[24]
0111[24]
100111
011000
1010[25]
1010[25]
001111
001111
110000
0101[26]
Running Disparity Violation Pattern
0101[27]
110111
001000
1010[27]
110000
0101[26]
ter begins sending the repeating transmit sequence - K28.5 +, D21.4,
D21.5, D21.5, (repeat all four bytes) ... defined in X3T9.3 as the primitive signal "Idle word." This Special Character input must be held for
four (4) byte times or multiples of four bytes or it will be truncated by
the new data.
The receiver will never output this Special Character, since K28.5 is
decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded
as data.
~
=:50
~~
_ ' j E CYPRESS
PRELIMINARY
CY7B923
CY7B933
- . I F SEMICONDUCTOR
Notes (continued):
22. CLl = Transmit Negative K28.5 (- K28.5 +) disregarding Current
RDwhen input is held for only one byte time. Ifheld longer, transmitter begins sending the repeating transmit sequence - K28.5 +, D21.4,
DlO.2, DlO.2,(repeat all four bytes) ... defined in X3T9.3 as the primitive signal "Receiver_Ready (R_ RDY)." This Special Character input
must be held for four (4) byte times or multiples of four bytes or it will
be truncated by the new data.
The receiver will never output this Special Character, since K28.5 is
decoded as C5.0, C1.7, or C2.7 and the subsequent bytes are decoded
as data.
23. C2.1 = Transmit either -K28.5+ or +K28.5- as determined by Current RD and modify the Transmission Character that follows, by setting its least significant bit to 1 or O. If Current RD at the start of the
following character is plus ( + ) the LSB is set to 0, and if Current RD
is minus ( - ) the LSB becomes 1. This modification allows construction ofX3T9.3 "EOF" frame delimiters wherein the second data byte
is determined by the Current RD.
For example, to send "EOFdt" the controller could issue the sequence C2.1- D21.4- D21.4- D21.4, and the HOTLink Transmitter
will send either K28.5-D21.4-D21.4-D21.4 or K28.5-D21.5D21.4- D21.4 based on Current RD. Likewise to send "EOFdti" the
controller could issue the sequence C2.1 - D 10.4 - D21.4 - D21.4, and
the HOTLink Transmitter will send either K28.5-DlO.4-D21.4D21.4 or K28.5-DlO.5- D21.4- D21.4 based on Current RD.
The receiver will never output this Special Character, since K28.5 is
decoded as C5.0, Cl. 7, or C2. 7, and the subsequent bytes are decoded
as data.
24. CO.7 = Transmit a deliberate code rule violation. The code chosen for
this function follows the normal Running Disparity rules. Transmission of this Special Character has the same effect as asserting SVS =
HIGH.
The receiver will only output this Special Character if the Transmission Character being decoded is not found in the tables.
25. Cl. 7 = Transmit Negative K28.5 (- K28.5 +) disregarding Current
RD.
The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output Cl. 7
if -K28.5 is received with RD+, otherwise K28.5 is decoded as C5.0
orC2.7.
26. C2.7 = Transmit Positive K28.5 (+ K28.5 -) disregarding Current
RD.
The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C2.7
if + K28.5 is received with RD -, otherwise K28.5 is decoded as C5.0
or C1.7.
27. C4.7 = Transmit a deliberate code rule violation to indicate a Running
Disparity violation.
The receiver will only output this Special Character if the Transmission Character being decoded is found in the tables, but Running Disparity does not match. This might indicate that an error occurred in a
prior byte.
Ordering Information
Ordering Code
Package
Name
Package lYpe
CY7B923-DC
D22
28-Lead (300-Mil) CerDIP
CY7B923-JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7B923-LC
L64
28-Square Leadless Chip Carrier
CY7B923-PC
P21
28-Lead (300-Mil) Molded DIP
CY7B923-JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7B923-PI
P21
28-Lead (300-Mil) Molded DIP
CY7B923- DMB
D22
28-Lead (300-Mil) CerDIP
CY7B923- LMB
L64
28-Square Leadless Chip Carrier
Ordering Code
Package
Name
Package lYpe
CY7B933-DC
D22
28-Lead (300-Mil) CerDIP
CY7B933-JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7B933-LC
L64
28-Square Leadless Chip Carrier
CY7B933-PC
P21
28-Lead (300-Mil) Molded DIP
CY7B933-JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7B933-PI
P21
28-Lead (300-Mil) Molded DIP
CY7B933-DMB
D22
28-Lead (300-Mil) CerDIP
CY7B933 - LMB
L64
28-Square Leadless Chip Carrier
7-24
Operating
Range
Commercial
Industrial
Military
Operating
Range
Commercial
Industrial
Military
---:-
~~~
_'1=
F
PRELIMINARY
CYPRESS
CY7B923
CY7B933
SEMICONDUcrOR
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Switching Characteristics
Subgroup
Parameter
VOHT
1,2,3
tCKW
VOLT
1,2,3
tB
VOHE
1,2
tCPWH
VOLE
1,2,3
tCPWL
VODIP
1,2,3
lOST
1,2,3
VIHT
1,2,3
tHENP
VILT
1,2,3
tpDR
VIHE
1,2,3
tPPWH
VILE
1,2,3
tpDP
IIHT
1,2,3
lILT
1,2,3
IIHE
1,2,3
tCPRH
IILE
1,2,3
tCPRL
Icc
1,2,3
tRH
VDIPP
1,2,3
tpRP
VIHH
1,2,3
VILL
1,2,3
tSD
tHD
tSENP
tRISE
tpALL
tCKR
tpRH
tA
tROH
tCKX
tCPXH
tCPXL
tDS
Document #: 38-00189-C
7-25
Subgroup
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
•
:E
oo
~
iCC
C
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Features
• 160 to 330 Mbps point-to-point serial
data link
• Parallel-to-serial and serial-to-paralleiI/O
• 10-bit-wide 8B/IOB encode, decode or
unencoded
• Compliant with ESCON, Fiber Channel and ATM standards
• Compatible with Fiber Channel FC-O
specification (CY9266 - C):
-2S-TV-EL-S
-2S-MI-EL-S
-2S-TP-EL-S
• Compatible with Fiber Channel FC-O
specification (CY9266- F):
-2S-M6-LE-I
CY9266-C
CY9266-F
HOTLink Evaluation Board
• Development tool for proprietary networks
• Full system diagnostics with Built-InSelf-Test (BIST)
• 1\vo-digit error display for BER
analysis
• Multiple host interface:
-48-pin connector (IBM OLC-266
compatible)
- 60-pin edge connector
- 60-pin two-row right-angle connector
• Socket for optional on-board crystal
oscillator
• Multiple system configurations via
DIP switch
• Multilayer board with surface-mount
technology
• Easy to use for applications development
Applications
• Similar in function to IBM OLC-266
(single channel) and HP HOLC-0266
• HOTLink System Development
• Telecommunications
• Remote data acquisition
• Processor-to-disk/peripheral communications
• Backplane extender
• Point-to-point video/image communications
• Point-to-point CPU/server communications
• High-speed data switching (Tl multiplexer, etc.)
48-PIN
OLC-266
CONNECTOR
60-PIN
EDGE
CONNECTOR
DIAGNOSTIC DISPLAY
9266-1
Figure 1. Copper Media Interface Evaluation Board CY9266-C
,--48-PIN
OLC-266
CONNECTOR
~
Rx
CY7B933
FIBEROPTIC
RECEIVER
C
-----60-PIN
EDGE
CONNECTOR
r---
'---
SYSTEM TEST .1
AND I/O
STATE MACHINE
Tx
CY7B923
FIBEROPTIC
DRIVER
C
DIAGNOSTIC DISPLAY
1
1
Figure 2. Fiber-Optic Interface Evaluation Board CY9266- F
7-26
9266-2
PRELIMINARY
Specification
Board Dimensions
Two media types:
CY9266-C
3.0" x 4.0" (approx., plus media connector)
Mini-coax or twisted-pair cables using two
pin 0.25" sq x 0.1" header or right -angle
BNC connectors
CY9266-F
LED based fiber optic using SC connector
Power Supply
+5V ± 5%
Maximum Clock Rate 33 MHz
Maximum Data Rate 330 Mbps
TTL
Parallel I/O
Serial I/O
Coax or twisted pair (CY9266-C) or
Fiber optic with SC connector
(CY9266-F)
General Description
The HOTLink Evaluation Board (CY9266) is a system development tool that facilitates the design and evaluation of the Cypress
HOTLink transmitter (CY7B923) and receiver (CY7B933) devices. The CY9266 Evaluation Board is offered with two serial media interface options: CY9266-C (copper) and CY9266-F (fiber). The CY9266-C offers a low cost 1/4" coaxial connection
while the CY9266- F interfaces with a longwave (1300nm) LED
optical transceiver and SC fiber optics connector.
CY9266-C
CY9266-F
The CY9266 accepts data and control commands from the host via
the parallel interface ports (available in three connectors). The
48-pin header connector allows interoperability with the IBM
OLC-266 interface. The two 60-pin connectors are functionally
equivalent. The vertical pin connector is used for probing and
monitoring the appropriate signals, while the edge connector can
be connected to a flat ribbon cable as a direct host communication
interface.
In a typical point-to-point link, the host downloads parallel data to
the CY9266 Evaluation Board. Parallel data can be formatted as
pre-encoded 10 bit patterns or 8-bit data/special characters to be
encoded by the HOTLink transmitter. The data is then encoded
(optionally) and serialized by CY7B923 HOTLink Transmitter.
Serial data is then transmitted via coax or fiber.
In the receive operation, serial data is sent from a remote source
(via copper/fiber) and transferred to the CY7B933 HOTLink receiver. The serialized data is converted to parallel and then optionally decoded. Parallel data is transferred to the host system along
with various status and synchronizing signals. All I/O operations
are performed between the host and the Evaluation Board using
simple handshakes.
The CY9266 Evaluation Board can also operate in self-diagnostic
mode and indicate errors in the serial transmission stream using a
built-in two-digit, seven-segment LED display.
Document #: 38-00236
IBM OLC-266 is a trademark of International Business Machines Corporation.
HP HOLC-0266 is a trademark of Hewlett-Packard Corporation.
7-27
•
·
.~
- - j ; CYPRESS
-==:::::::;,
SEMICONDUCTOR
Modules
Section Contents
Page Number
Custom Module Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
Device Number
CYM1420
CYM1441
CYM1464
CYM1465
CYM1471
CYM1481
CYM1560
CYM1622
CYMl720
CYM1730
CYM1821
CYM1828
CYM1831
CYM1832
CYM1836
CYM1838
CYM1840
CYM1841
CYM1851
CYM4208
CYM4209
CYM7232
CYM7264
CYM7485
CYM7490
CYM7491
CYM7492
Description
128Kx 8 Static RAM Module ................................................... 8-5
256K x 8 Static RAM Module .................................................. 8 -11
512K x 8 Static RAM Module .................................................. 8-16
512Kx 8 Static RAM Module .................................................. 8-22
1024Kx 8 Static RAM Module ................................................. 8-28
2048Kx 8 Static RAM Module ................................................. 8-28
1024K x 9 Buffered Static RAM Module with Separate I/O ......................... 8-34
64Kx 16 Static RAM Module .................................................. 8-39
32K x 24 Static RAM Module .................................................. 8-44
64Kx 24 Static RAM Module .................................................. 8-49
16Kx 32 Static RAM Module .................................................. 8-54
32Kx 32 Static RAM Module .................................................. 8-61
64K x 32 Static RAM Module .................................................. 8-68
64K x 32 Static RAM Module .................................... . . . . . . . . . . . . .. 8-73
128K x 32 Static RAM Module ................................................. 8-78
128Kx 32 Static RAM Module ................................................. 8-83
256Kx 32 Static RAM Module ................................................. 8-88
256Kx 32 Static RAM Module ................................................. 8-94
1024K x 32 Static RAM Module ............................................... 8-100
Cascadable 64Kx 9 FIFO .................................................... 8-105
Cascadable 128Kx 9 FIFO ................................................... 8-105
DRAM Accelerator Module .................................................. 8-114
DRAM Accelerator Module .................................................. 8-114
128K Write-Through Secondary Cache Module .................................. 8-194
i486 Level II Cache Module Family ............................................ 8-211
i486 Level II Cache Module Family ............................................ 8-211
i486 Level II Cache Module Family ............................................ 8-211
Custom Module Capabilities
Introduction
Cypress's Multichip Products group is a leading supplier of custom
memory and/or logic modules. This turnkey capability provides designers with a fast, low-risk solution for when they require the ultimate in system performance and density. Detailed information on
standard modules can be found in the Static RAM, FIFO, and
Module sections of this book.
Packaging Guidelines
High-density memory modules are now available in a wide variety
of package styles that satisfy a variety of needs for high-performance system design. Since board space is a primary concern, the
choice of a package style is important in meeting layout constraints
as well as thermal and mechanical design objectives.
Multichip Products currently supports several commonly used
module technologies including plastic components on FR4 or polyimide substrate, and ceramic components mounted on ceramic
substrates. Advanced technologies suitable for the demands of
higher integration components are also available.
The plastic technology employs plastic encapsulated, surfacemount components and an epoxy laminate (FR4 or polyimide)
substrate. The plastic components can be SOJ, SOle, VSOp,
TSOP, QFP, or other surface-mount packages. Die can also be
mounted directly to the substrate and wire bonded to the substrate.
The ceramic technology employs hermetic, ceramic-packaged devices mounted on a ceramic substrate. The components are typically leadless chip carriers, but may include other package types. The
ceramic substrate has a custom interconnect for the particular
components it carries. The ceramic substrate and components offer improved thermal characteristics over the plastic modules. This
makes these modules suitable for extended temperature range operation, such as in military applications.
Common Packaging Options
This section describes several common module packaging options
available from Cypress. A summary table (Table 1) compares relative board areas of each option based on a module with eight
28-pin components.
SIP
The single in-line pin package, or SIp, is a vertically mounted module with a single row of pins along one edge for through-hole
mounting. The SIP configuration is typically constructed with plastic-encapsulated components mounted on an FR4 or polyimide
substrate, although ceramic SIPs are also used. The pins are on a
100-mil pitch. The vertical orientation and the mounting of compo-
nents on both sides ofthe module can increase the component density by a factor of four or more.
Flat SIP
The flat single in-line pin package, or FSlp, is virtually identical to
the SIP except that the substrate is mounted in the horizontal rather than the vertical direction. When mounted to a circuit board, the
flat SIP lies close and parallel to the board. Flat SIP modules save
board area since they, like other modules, employ fine lead pitch
surface-mount components on a high-density substrate. The flat
SIP density approximates double-sided surface-mounted boards
with the advantage of a very low profile and improved mechanical
stability over the vertical SIP.
ZIP
The zigzag in-line pin package, or ZIp, is vertically mounted and is
usually built with plastic encapsulated components on an FR4 or
polyimide substrate. The ZIP module has pins along both sides of
the substrate and the pins on alternate sides are staggered by 50
mils. Adjacent pins on the same side ofthe substrate are separated
by 100 mils. The dual row of staggered pins allows a higher connection density than that of the SIP while maintaining 100-mil minimum spacing between any adjacent pins. The ZIP is especially useful in large pin count devices where the host board is designed with
through-hole design rules.
SIMM
The single in-line memory module, or SIMM, is similar to the ZIP
except that there are no pins for through-hole mounting. Instead,
the bottom edge of the module is equipped with edge connector
contacts that are plated to the substrate. The SIMM is designed to
plug into motherboard sockets. The contacts are on both sides of
the substrate, and contacts directly opposite each other are connected together. SIMM edge connector contacts are on a 50-mil or
100-mil pitch. SIMMs allow greater system functionality and flexibility by allowing easy use of multiple densities and speed grades.
Some module devices are available in both ZIP and SIMM packages with the same form factor. The pin out is designed so that the
pinout and footprint of the SIMM socket matches the footprint of
the ZIP module allowing ZIPs or SIMMs to be used interchangeably with only one board layout. The SIMM may be used in prototyping to test different speed versions of a system and then replaced with a companion ZIP for production, or SIMMs may be
used in production for flexibility in memory size or memory speed.
8-1
·
·~PRFSS
~,
Custom Module Capabilities
SEMICONDUCTOR
VDIP
The VDlp, or vertical dual in-line pin package, is a vertically
mounted module with two rows of pins on 100-mil centers. Row to
row spacing is 100 mils, with pins of the two rows aligned directly
across from one another. The dual row of pins allows a higher connection density than that of the SIP while maintaining 100-mil
minimum spacing between any adjacent pins. VDIP may be either
plastic or ceramic. The VDIP is useful in large pin count devices
where the host board is designed with through-hole design rules.
DIP
The DIP, or dual in-line pin module, is a low-profile package with
excellent mechanical ruggedness. The ceramic DIP is ideally suited
for military applications. Plastic DIPs are often used when a low
vertical profile is required. In some cases, the DIP device is intended to have an identical footprint and similar form factor to
standard integrated circuit components and can provide larger
memory capacity in the same footprint.
PGA
The PGA, or pin grid array, has an array of pins that are perpendicular to the package plane. These pins are arranged in a matrix on a
100-mil grid. Most of the matrix is filled with pins except for a central square that is normally devoid of pins.
QUIP
The QUIP, or quad in-line pin package, is very similar to the DIP
package except that there is a dual row of pins along the package
edge. In-row and row-to-row pin spacing is 100 mils with pins in adjacent rows aligned directly across form one another. The QUIP is
a low-profile package with excellent mechanical ruggedness, with
the added advantage of higher pin density for the same package
length.
QFP
The QFP, or quad flat pack, is a surface-mounted module. Gull
wing pins extend out from the square package on all four sides and
are formed to be coplanar with the package bottom. Lead pitches
are typically 50 mils or smaller.
Package Summary
Table 1 summarizes the various characteristics of the packages discussed above.
Table 1. Package 1Ypes
Package
'JYpe
1Ypical Pin
Count
'JYpical
Heighd 1]
Board Space
(sq. in.)[3]
Mil[2]
Min.
Max.
Min.
Max.
FR4
Cer
SIP
24
50
0.5
0.9
N
Vertical orientation. FR4 or
ceramic technology.
Limited pin count.
1.2
0.9
FSIP
24
50
0.2
0.4
N
Very low profile. Mechanical
stability. FR4 or ceramic technology.
Lower density due to horizontal orientation.
2.7
2.4
ZIP
24
100
0.5
0.9
N
Vertical orientation. JEDECstandard pinouts. Pinout compatible with SIMM.
1.2
N/A
SIMM
24
100
0.5
0.9
N
Vertical orientation. Socket
mounting. Pinout compatible
with ZIP.
1.2
N/A
Advantages
Disadvantages
VDIP
36
104
0.5
0.95
y
Vertical orientation.
1.2
0.9
DIP
24
60
0.17
0.37
Y
Low profile. Excellent mechanical ruggedness.
Horizontal orientation.
2.9
2.9
QUIP
48
200
Y
Low profile. Excellent mechanical ruggedness. Increased number of pins.
Horizontal orientation.
2.9
2.9
QFP
68
144
Y
Surface mount. Low profile.
Excellent mechanical ruggedness. Large number of pins in
small area.
Surface-mount technology required. Horizontal orientation. Components on one side
only.
3.1
3.1
PGA
68
144
Y
Large number of pins in thruhole technology. Low profile.
Excellent mechanical ruggedness.
Multilayer boards. Horizontal
orientation. Components on
one side only.
2.9
2.9
Notes:
1. rv1inimum and lllaxiuIUi11 height are given in inches.
2.
3.
The Mil entry contains a Y(es) or N(o) indicating if the package type
is suitable for military applications.
8-2
Board space roughly yuaniifies the main board area, in square inches,
taken up by the module when the module contains eight, 28-pin components.
--=-
~~
Custom Module Capabilities
_-i!lCYPRESS
JF
SEMICONDUcrOR
Component Selection
Cypress's Multichip Products group handles many types of components to build custom modules_ Typically, any digital component
that is available in surface-mount packaging can be used, but the
module is not limited to this. Standard and custom modules include
SRAM,FIFOs, dual ports, EPROM, Flash, andE2PROM devices,
combined or mixed. Logic may also be employed to provide decoding, pipelined storage, or extra drive capability. The CYM1461 and
the CYM1540 are examples of such devices. In the CYM1461, sixteen 32Kx 8 RAMs are arranged to form a 512Kx 8 module and
the individual SRAMs are selected by an on board decode. The
CYM1540 provides address and control buffering for a 256K x 9
static RAM module so that only a single device load and capacitance is presented to the system. Other custom modules provide
for unusual memory word widths. The CYMl720 is a memory
module specifically designed for 24-bit-wide DSP processors.
ECLis also a logicfamily suitable for collecting into a module_ Unless the system is largely ECL, it makes sense to place the ECL
components onto a module that is optimized for performance. Delivered as a tested component, the ECL module can be assembled
into the system with high confidence of proper functionality. Typical examples of custom ECL modules include wide ECL-to-TTL
translators and deep and/or wide ECL PROM or RAM memory
arrays.
More complex functions may also be integrated onto a custom
module; e.g., processor subsystems, embedded within a system that
are dedicated to specific functions. These functions may include
several forms of memory, a microprocessor or DSp, communication ports, and bus interface circuitry with possibly shared memory
control. A custom module may also include an ASIC designed especially to implement the desired function. One example of such a
device is the CYM4241 deep FIFO. This device includes three
high-speed SRAMs, a surface-mount 50-MHz crystal oscillator,
and a wire-bonded ASIC die on substrate that integrates the RAM
interface control and port access arbitration. This combination of
components yields a 64K by 9 FIFO in a single 28-pin DIP. By simply changing the memory content, the device can be extended to
256Kby9.
Modules undergo complete characterization and qualification before being released to production. Characterization includes the
following: AC and DC characterization over voltage and temperature, and complete custom specificationreview. Release toproduction requires a verified test program with test hardware and correlation samples, complete assembly drawings and approved parts
list, production and test travelers, a formal design review, and customer approval. In production, custom (and standard) modules are
built using fully tested components, and are rigorously tested before they are shipped. As an example of the rigorous production
testing, memory modules are tested for all DC parametrics, all AC
parametrics, and functionality. Functional testing includes a select
set of memory pattern sensitivity tests. This complete testing allows
the module to be treated by the user as a true component with a set
of specifications that are guaranteed by the manufacturer. This
saves time and effort during system manufacture and provides a
degree of reliability not obtainable from operations focused on
only assembly.
Future Technologies
The ultimate in multichip technology is multiple die on a substrate
that offers highly efficient interconnect and the densest multichip
assembly technology. The technology is available now for multi-
chip configurations with silicon chips on ceramic, epoxy laminate,
and silicon substrates.
Introduction to Modules for the New User
The use of modules is growing rapidly since it is a vehicle for obtaining high integration and high performance with minimal impact on cost. Almost every personal computer now has main
memory as plug in SIMM packages constructed from surfacemount DRAM components. High-performance RISC and CISC
CPU subsystems are available as modules where the supplier has
optimized the component I/O design and the substrate layout for
maximum performance amongst the tightly coupled components.
Size is one obvious advantage of modules; their small size allows a
function to fit into a very small space. Consider the economics of
having a large memory array together with the system CPU on a
single card in contrast to the cost of multiple memory cards connected via a backplane bus and the resulting performance loss. In
many cases, the module approach is a considerable savings in materials and manufacturing cost by reducing the total number of system cards.
Applying the tight design rules of modules has its limitations. A
module has line widths and spacings that support close packing of
VSOP and die components, and these spacing/width design rules
are at the limit of what can be handled by capable volume production substrate producers. The use of fully tested modules gives the
density gain oftight design rules at economically attractive system
manufacturing yields. Therefore in the manufacturing process, the
module exhibits the characteristics of a monolithic device: high integration, ease of application, and high system manufacturing
yield. The module brings high-density surface-mount technology
to the through-hole manufacturing environment.
Performance is another significant gain obtainable from module
application. Unfortunately this is the most difficult gain to quantify. Consider a memory subsystem collected tightly around a CPU
versus the same memory capacity spread over one or more boards.
It seems intuitively plausible thatthe larger subsystem will be slower: the distance to travel is longer, and the memory address and
data bus lines have larger capacitance due to their longer length
and the larger number of stubs on the lines. This is indeed the case.
Many of the custom modules include buffers for reduced loading,
registers for data pipelining, and simple or specialized decoders to
ease system bus interfacing. Taken as a component, these modules
typically exhibit higher capacitance than a monolithic component
and incur about 5 ns additional delay for on board decoders or
buffers. However, the module is from four to sixteen times as dense
as through-hole monolithic devices and consequently achieve a net
performance advantage.
Custom Module Development Flow
Multichip's focus is on providing turnkey memory modules. Figure
1 illustrates the tasks performed during the development of the
module.
Module development commences with the generation of a detailed
Objective Specification. The module is designed to this specification, and once in production it will be guaranteed to perform as indicated in the Objective Specification.
Components are selected while the specification is being generated. In many cases, the spec is designed such that multiple sources
of components can be utilized. Once the spec is complete and the
components are selected, a schematic for the module is generated.
The netlistfrom the schematicis used to drive the circuit simulator.
8-3
I·
C/)
W
.J
::)
C
0
::E
~
.
~~pR.ESS
~,
Custom Module Capabilities
SEMICONDUCTOR
Custom Module Development Flow (continued)
During simulation, several types of analyses are performed. A
function simulation is used to ensure that the module's logic is designed properly. Timing simulation is run to verify thatthe module
will function when subjected to the worst -case timing delays of the
components. Finally, thermal analysis may be performed to determine the thermal characteristics of the module.
The layout of the module is also netlist driven. An autorouter may
be used, depending on the complexity and density of the module.
Design rule checks are run to ensure that the layout does not violate any electrical or mechanical design rules. Finally, the layout
output is used to generate the module substrate.
The layout output is also used to drive the pick and place equipment. This ensures consistency between design and manufacturing. While the module prototypes are being assembled, the test
program is generated and the test fixture is constructed. Test program generation is largely automated, using as inputs the simulation outputs and pre-defined test program subroutines for common configurations.
Once prototypes have been generated, the standard release procedure is initiated. This procedure includes steps such as bench testing, module characterization and qualification, and fine tuning of
the test program. Following customer approval of the module, it is
released to production.
Quoting Information
In order to prepare a quotation or proposal, we need as much as
possible of the following information:
• Circuit schematic
• Functional description
• Mechanical dimensions required
• Speed and power requirements
• Prototype and production deadlines
• Production quantity estimates
• An engineering contact to answer questions
Once the above information is received, a budgetary quotation will
typically be provided within one to two weeks.
Figure 1. Custom Module Flow
8-4
CYM1420
128K X 8 Static RAM Module
Features
Functional Description
• High-density I-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 20 ns
• 32-pin, 0.6-inch-wide DIP package
• Low active power
-1.2W (max.)
• Hermetic or plastic SMD technology
• TTL-compatible inputs and outputs
• JEDEC-compatible pinout
• Commercial and military temperature
ranges
The CYM1420 is a very high performance
I-megabit static RAM module organized
as 128K words by 8 bits. This module is
constructed using four 32K x 8 static
RAMs mounted onto a substrate. A decoder is used to interpret the higher-order
addresses A 15 and A 16 and to select one of
the four RAMs.
Writing to the memory module is accomplished when the chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the eight input/output pins (1100
through 1/07) of the device is written into
the memory location specified on the address pins (Ao through A16).
Reading the device is accomplished by taki~chip select (~and output enable
(OE) LOW, while WE remains inactive or
HIGH. Under these conditions, the contents of the memory location specified on
the address pins will appear on the eight input/output pins.
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
Pin Configuration
DIP
An -
Top View
A14
WE
DE
15
NC
Vee
A16
A14
A12
A7
A 15
NC
WE
A 13
As
As
A5
As
All
~
A3
A2
Al
A 15
A 16
DE
A10
CS
An
10F4
DECODER
1/07
1/0 6
1/05
1/04
1/03
1/0 0
1/01
1/02
CS
GND
1420-2
1/00 - 1/07
1420-1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Commercial
Maximum Standby Current (rnA)
Commercial
1420-20
1420-25
1420-30
1420-35
1420-45
20
25
30
35
45
55
210
210
210
210
210
210
210
210
210
210
140
140
140
140
140
140
140
140
140
140
Military
. .
Military
Shaded area contams prehmmary mformatlon .
8-5
1420-55
I
til
W
....I
:::»
Q
0
:.
,
!Y
_
~PRFSS
CYM1420
~ ~CONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired.)
Output Current into Outputs (LOW) ............... 20 rnA
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with .. - 10°C to +85°C (Commercial)
Power Applied .............. - 55°C to + 125°C (Military)
Supply Voltage to Ground Potential ........ - O.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Operating Range
Range
Ambient
Temperature
Vee
Commercial
O°Cto +70°C
5V ± 10%
- 55°C to + 125°C
5V ± 10%
Military
Electrical Characteristics Over the Operating Range
CYM1420
Parameters
Description
VOH
Output HIGH Voltage
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Units
0.4
V
Vee
V
2.4
Vee
V
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
- 0.5
0.8
V
IIX
Input Load Current
GND.s VI.s Vee
-10
+10
loz
Output Leakage Current
GND .s V 0 .s Vee, Output Disabled
-10
los
Output Short Circuit Currentfl)
Icc
Vee Operating Supply Current
ISBl
Automatic CS Power-Down Currentf2)
ISB2
Automatic CS Power-Down Current[2)
= Max., VOUT = GND
Vee = Max., lOUT = 0 rnA, CS .s VIL
Vee = Max., CS ~ VIR,
Min. Duty Cycle = 100%
Vee = Max., CS ~ Vee - 0.3v,
2.2
Vee
+10
!!A
!!A
-300
rnA
210
rnA
140
rnA
80
rnA
VIN ~ Vee - O.3V or VIN .s O.3V
Capacitance[3)
Parameters
Description
CrN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
3.
= 1 MHz,
Max.
Units
35
pF
40
pF
Tested on a sample basis.
AC Test Loads and Waveforms
R1481Q
OUTP~~ ~
1
'n~.~:F -
INCLUDING
JIG AND
SCOPE
-
1
-
R1481Q
R2
OUTP~~ ~
INCLUDING
JIG AND
SCOPE
-
(b)
(a)
Equivalent to:
1
'n,.~:F -
255Q
ALL INPUT PULSES
3.0V---90%
R2
1420-3
THEVENIN EQUIVALENT
OUTPUT~
GND
1255Q
-
1.73V
8-6
1420-4
CYM1420
Switching Characteristics Over the Operating Rangel4]
1420-25
1420-20
Description
Parameters
Min.
Max.
Min.
Max.
1420-30
Min.
Max.
Units
READ CYCLE
20
25
30
ns
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
20
25
30
ns
tDOE
OE LOW to Data Valid
10
10
15
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[5]
tHZCS
CS HIGH to High Z[5, 6]
25
20
3
3
0
3
0
20
ns
20
5
3
ns
ns
20
20
ns
ns
0
10
10
3
30
ns
WRITE CYCLE[7]
twc
Write Cycle Time
20
25
30
ns
tscs
CS LOW to Write End
15
20
25
ns
tAW
Address Set-Up to Write End
15
20
25
ns
tHA
Address Hold from Write End
2
2
5
ns
5
5
5
ns
tSA
Address Set-Up to Write Start
tpWE
WE Pulse Width
15
20
25
ns
tSD
Data Set-Up to Write End
10
12
18
ns
tHD
Data Hold from Write End
2
2
3
ns
tLZWE
WE HIGH to Low Z
0
0
5
ns
tHzWE
WE LOW to High Z[6]
0
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.Sv, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
6. tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±SOO m V from steadystate voltage.
8
7.
8-7
0
10
0
15
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
I
(JJ
W
..J
::J
C
o
==
=-:-.~
- - -iE
CYM1420
CYPRESS
~JF' SEMICONDUCTOR
Switching Characteristics Over the Operating Range (continued) [4]
1420-35
Parameters
Description
Min.
Max.
1420-45
Min.
Max.
1420-55
Min.
Max.
Units
55
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
35
45
55
45
35
ns
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
35
45
55
ns
tDOE
OE LOW to Data Valid
18
25
30
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[S]
tHZCS
CS HIGH to High Z[S, 6]
3
5
0
5
0
3
0
20
20
5
20
ns
ns
25
5
20
ns
ns
25
ns
WRITE CYCLE[7]
twc
Write Cycle Time
35
45
55
ns
tscs
CS LOW to Write End
30
40
45
ns
tAW
Address Set-Up to Write End
30
40
45
ns
tHA
Address Hold from Write End
5
5
5
ns
tSA
Address Set-Up to Write Start
5
5
5
ns
tpWE
WE Pulse Width
25
25
30
ns
tSD
Data Set-Up to Write End
18
20
25
ns
tHD
Data Hold from Write End
3
5
5
ns
tLZWE
WE HIGH to Low Z
5
5
5
tHZWE
WE LOW to High Z[6]
0
15
0
15
0
ns
25
ns
Switching Waveforms
Read Cycle No.
d 8, 9]
F
'tLHA
ADDRESS-----.. .
DATA OUT
PREVIOUS DATA VALID
IRC
~
I
3XXX*================D_A-I=A=V=A=L=ID===========
1420·5
Notes:
8. WE is HIGH for read cycle.
9.
8-8
Device is continuously selected, CS = VIL and OE= VIL.
N~
-='=
--=-, CYPRESS
CYM1420
•
SEM]CONDUCIOR
Switching Waveforms (continued)
Read Cycle No. 2[8, 10]
tRC
~"
} It'
tACS
~"
*
tDOE
j.--tLZOEHIGH IMPEDANCE
I/////V
DATA OUT
I+--tpu
---I}
VCC _ _ _ _ _ _ _ _
SUPPLY
CURRENT
-
~
DATA VALID
1"-"'",,'
tLZCS
tHZOE!+-tHZCSHIGH
IMPEDANCE
/
j4-tpD
50%
~
CC
I
50%
ISB
1420-6
Write Cycle No.1 (WE Controlled)[7, 11]
~--------------------------twc--------------------------~
ADDRESS
~~~, ~~------------------tscs------------------~~~-7-r~~~~-r-r~
CS
~----------------------~w------------------~~--~-------tSA--------~
____
_ _ _ _ _ _ _ _ _ _ _~~~~ ~~----tpwE------~ , -_ _ _ _ _ _ _ _ __
tn
W
....I
:::»
WE
C
o
~~-------tSD------~~tHD
:2
DATA VALID
DATA IN
tHZWE~
--J>
DATA I/O _ _ _ _ _ _ _ _ _
D_AT_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _
-
tLZWE
-----I
HIGH IMPEDANCE
1(,----1420-7
Notes:
10. Address valid prior to or coincident with CS transition LOW.
I
11. Data I/O is high impedance if OE = VIH.
8-9
~
.:"" CYPRESS
--=::.
~,
CYM1420
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled) [7, 11, 12]
ADDRESS
-----------.~------tscs----~·I
~~------tSD------~~
DATA IN
DATA VALID
tHZWE
DATA I/O
-----I
----------------------------------------~I
HIGH IMPEDANCE
DATA UNDEFINED
)>-------------------------1420-8
Note:
12_ If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
'fruth Table
CS
OE
WE
H
X
X
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Outputs
HighZ
Mode
DeselectlPower-Down
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 1Ype
Operating
Range
20
CYM1420PD-20C
PD05
52-Pin DIP Module
Commercial
25
CYM1420HD-25C
HD04
32-Pin DIP Module
Commercial
CYM1420PD-25C
PD05
52-Pin DIP Module
CYM1420HD-30C
HD04
32-Pin DIP Module
CYM1420PD-30C
PD05
52-Pin DIP Module
CYM1420HD-35C
HD04
32-Pin DIP Module
CYM1420PD-35C
PD05
52-Pin DIP Module
CYM1420HD-35MB
HD04
32-Pin DIP Module
Military
CYM1420HD-45C
HD04
32-Pin DIP Module
Commercial
CYM1420PD-45C
PD05
52-Pin DIP Module
CYM1420HD-45MB
HD04
32-Pin DIP Module
Military
CYM1420HD-55C
HD04
32-Pin DIP Module
Commercial
PD05
52-Pin DIP Module
HD04
32-Pm DIP Module
30
35
45
55
CYM1420PD-55C
I CYM1420HD-55MB I
Document #: 38-M-00001-D
8-10
Commercial
Commercial
..
IMIlItary
CYM1441
256K X 8 Static RAM Module
Features
Functional Description
• High-density 2-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 25 ns
• Low active power
- 5.3W (max.)
• SMD technology
• Separate data I/O
• 60-pin ZIP package
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.5 in.
• Small PCB footprint
-1.14 sq. in.
The CYM1441 is a very high performance
2-megabit static RAM module organized
as 256K words by 8 bits. The module is
constructed using eight 256K x 1 static
RAMs in SOJ packages mounted onto an
epoxy laminate substrate with pins. Tho
chip selects (CSL and CSu) are used to independently enable the upper and lower 4
bits of the data word.
Writing to the memory module is accomplished when the chip select (CS) and write
enable (WE) inputs are both Law. Data
on the eight input pins (DIo through DI7)
is written into the memory location specified on the address pins (Ao throughA17).
Pin Configuration
Logic Block Diagram
Ao -
Reading the device is accomplished bytaking ch~elect (CS) LOW while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the
memory location specified on the address
pins will appear on the appropriate data
output pins (DOo through D07).
The data output pins remain in a highimpedance state unless the module is selected and write enable (WE) is HIGH.
Two pins (PDo and PDl) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged.
ZIP
Top View
A17
(OPEN) PDo
NC
Vee
01 0
00 0
Ao
I-
256Kx 1
f-
SRAM
SRAM
256Kx 1
f-
SRAM
I
I
256Kx 1
A2
~
I
GND
01 1
00 1
WE
Ag
SRAM
At>
r-
r-
f-
I
-
256Kx 1
I
I
I
I
I
I
I
I
00 4 - 007
CSL
......
256Kx 1
'--
SRAM
L.--.
01 0 - 01 3
I
256Kx 1
I...-
SRAM
I
I
I
SRAM
I---.
I---
I
......
.........
256Kx 1
I
Ir
I
I
NC
NC
Vee
256Kx 1
I
SRAM
I
I
I
00 0 - 003
1441-1
01 2
00 2
A10
A12
A14
A 16
NC
01 3
003
NC
NC
GND
GND
PD1 (GND)
NC
01 4
00 4
NC
A1
A3
A5
A7
01 5
005
Vee
NC
NC
01 6
006
GND
A11
A13
A 15
A17
01 7
007
Vee
NC
NC
1441-2
Selection Guide
1441-35
25
35
45
Maximum Operating Current (rnA)
960
960
960
Maximum Standby Current (rnA)
320
320
320
8-11
C
:e
CSU
1441-25
W
..J
;:)
0
As
NC
Maximum Access Time (ns)
Ien
1441-45
~
~~
CYM1441
~1iCYPRESS
~, SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired.)
Operating Range
Range
Storage Temperature .................. - 55°C to + 125°C
Ambient Temperature with
Power Applied ......................... -lOoC to +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Commercial
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
CYM1441
Parameter
Test Conditions
Description
VOR
Output HIGH Voltage
VOL
Output LOW Voltage
Min.
= Min., lOR = - 4.0 rnA
Vee = Min., IOL = 12.0 rnA
Max.
Unit
2.4
Vee
V
0.4
V
V
VIR
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltagel 1)
- 0.5
0.8
V
IIX
Input Load Current
GND~VI~Vee
-80
+80
Ioz
Output Leakage Current
GND ~ Vo ~ Veo Output Disabled
-50
+50
!tA
!tA
Ice
Vee Operating Supply Current
Vee
960
rnA
ISBI
Automatic CS
Power-Down Current
Max. Vee, CS~ VIR,
Min. Duty Cycle = 100%
320
rnA
ISB2
Automatic CS
Power-Down Current
Max. Veo CS ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor VIN ~ 0.2V
160
rnA
= Max., lOUT = 0 rnA, CS ~ VIL
Capacitance[2)
Description
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
60
pF
15
pF
Notes:
1.
2.
VIN(min.) = - 3.0V for pulse widths less than 20 ns.
Tested on a sample basis.
AC Test Loads and Waveforms
TI TI
R14810
OUTP~~
30 pF
INCLUDING
JIG AND
SCOPE
R2
I
OUTP~~
5 pF
2550
-
-
INCLUDING
JIG AND
SCOPE
I
-
3.0V---90%
R2
2550
1441-3
1441-4
THEVENIN EQUIVALENT
OUTPUT~
GND
-
(b)
(a)
Equivalent to:
ALL INPUT PULSES
R14810
1.73V
8-12
====-~
--.
~;~
CYM1441
~iE
CYPRESS
- , SEMICONDUcrOR
Switching Characteristics Over the Operating Range[3]
1441-35
1441-25
Description
Parameter
Min.
Max.
Min.
Max.
1441-45
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z
tHZCS
CS HIGH to High Z[4]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
25
45
35
25
3
3
25
3
3
3
0
0
0
25
ns
ns
45
35
ns
ns
30
25
ns
ns
45
35
3
15
ns
45
35
ns
WRITE CYCLErS]
twc
Write Cycle Time
25
35
45
ns
tscs
CS LOW to Write End
20
30
35
ns
ns
tAW
Address Set-Up to Write End
20
30
35
tRA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
2
ns
tpWE
WE Pulse Width
20
25
30
ns
tSD
Data Set-Up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
ns
tLzWE
WE HIGH to Low Z
3
3
3
ns
tJ)
tHZWE
WE LOW to High Z[4]
0
ns
W
..J
15
0
20
0
25
:;:)
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IorJIOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of ACTest
Loads and Waveforms. Transition is measured ± 500 m V from steady
state voltage.
5.
6.
7.
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL.
Switching Waveforms
Read Cycle No. 1[6,7]
ADDRESS
~
tRC
1
---~tOHA~
DATA OUT
I
PREVIOUS DATA VALID ,xxX)k================D=AT=A=V=A=L=ID===========
1441-5
8-13
C
0
:::!
~
==-~
--.
"ircY
~~ ~~NDUcrOR
CYM1441
Switching Waveforms (continued)
Read Cycle No. 2[6, 8]
CS
tRC
~"
~~
tACS
-tHZCS-'
tLZCS
HIGH IMPEDANCE
1/////'/
DATA OUT
HIGH
"' IMPEDANCE
/
DATA VALID
,,"-"-"-"-,
-tPD
~tpu
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
}
~ CC
I
50%
50%
-
ISS
1441-6
Write Cycle No.1 (WE Controlled)[5]
~--------------------------------------twc---------------------------------------~
ADDRESS
~~-+-,
1111------------------------ tscs -------------------------------+1 -.,.-,....,...,....,...+,.....,.....,....,...,....,...
~-------------------------------~w----------------------------.~--______~~~~:::::_tS_A_-_-_-_-_-_-_-_-_~~~~~~~-------tpWE------~,_-_ _ _ _ _ _ _ __
~~----------tSD-----------~
DATA IN
--------------------------------~
DATA VALID
tHZWE
:1
tLZWE~
-J)
HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _ _ _D_A_TA__
UN_D_E_F_IN_E_D___________
1('--______
1441-7
Write Cycle No. 2,(CS Controlled)[5, 9]
ADDRESS
------------.~------tscs---~~
---~------------~
~-------
tPWE
,-----+------
------~
~~~~~~~~~~~~~~~~
-......,...,....,...~~...,...,..~~~
~-r----------tSD----------~
DATA IN
DATA VALID
tHZWE ---.j
DATA OUT
----------------------~ 1
HIGH IMPEDANCE
)>--------------
DATA UNDEFINED
1441-8
t~otes!
8.
Address valid prior to or coincident with CS transition LOW.
9.
8-14
If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
·
::~
_.1=
CYM1441
CYPRESS
- . F SEMICONDUCTOR
'fruth Table
CS
WE
H
X
HighZ
L
H
Data Out
Read
L
L
Data In
Write
L
H
HighZ
Deselect
Input/Output
Mode
Deselect/Power-Down
Ordering Information
Speed
Ordering Code
Package
Name
Package Type
Operating
Range
25
CYMI441PZ-25C
PZ04
60-Pin ZIP Module
35
CYMI441PZ-35C
PZ04
60-Pin ZIP Module
Commercial
45
CYMI441PZ-45C
PZ04
60-Pin ZIP Module
Commercial
Commercial
Document #: 38-M-00020-A
I
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==
8-15
CYM1464
CYPRESS
SEMICONDUCTOR
512K X 8 Static RAM Module
Features
Functional Description
• High-density 4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 20 ns
• Low active power
-1.93W (max.)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.34 inches
The CYM1464 is a high-performance
4-megabit static RAM module organized
as 512K words by 8 bits. This module is
constructed using four 256K x 4 static
RAMs in SOJ packages mounted on an
epoxy laminate substrate with pins.
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW. Data on the
eight input/output pins (1/00 through
1/07) of the device is written into the
memory location specified on the address
pins (Ao through A18). Reading the device
is accomplishe~ taking chip select and
output enable (OE) LOW, while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the
memory location specified on the address
pins (Ao through A18) will appear on the
eight appropriate data input/output pins
(1/00 through 1/07).
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Pin Configuration
Logic Block Diagram
DIP
Top View
512Kx 8
SRAM
1464-2
1464-1
Selection Guide
Maximum Access Time (ns)
1464-20
1464-22
1464-25
1464-30
1464-35
1464-45
20
22
25
30
35
45
55
300
300
300
240
240
240
Maximum Operating Current (rnA)
350
350
350
300
Maximum Standby Current (rnA)
240
240
240
240
8-16
1464-55
==.
~~
_.1=
-====F
CYM1464
CYPRESS
SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired.)
Operating Range
Storage Temperature .................. - 55°C to +125°C
Ambient Temperature with
Power Applied ........................ - 10 ° C to + 85 ° C
Supply Voltage to Ground Potential. . . . . . .. - 0.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - 0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
Range
Ambient
Temperature
Vee
Commercial
O°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
= Min., lOR = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
1464-20, 22, 25
1464-30,35,45,55
Min.
Min.
Max.
Unit
Max.
VOR
Output HIGH Voltage
VOL
Output LOW Voltage
0.4
V
VIR
Input HIGH Voltage
2.2
Vee + 0.3
2.2
Vee + 0.3
V
VIL
Input LOW Voltagel 1]
-0.5
0.8
-0.5
0.8
V
IIX
Input Load Current
GND~ VI~
-10
+10
-10
+10
flA
loz
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
-10
+10
-10
+10
IlA
Icc
Vee Operating Supply
Current
Yce
350
300
rnA
ISBl
Automatic CS
Power-Down Current
Vee = Max., CS L VI~
Min. Duty Cycle = 100 0
240
240
rnA
ISB2
Automatic CS
Power-Down Current
Vee = Max., CS L Vee - 0.2V,
VIN L Vee - 0.2V or VIN ~ 0.2V
10
10
rnA
2.4
Vee
2.4
0.4
Vee
= Max., lOUT = 0 rnA,
V
CS~ VIL
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Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIL (Min.) = - 3.0V for pulse widths less than 20 ns.
2.
TI TI
= 1 MHz,
Max.
Unit
40
pF
30
pF
Tested on a sample basis.
OUTP~~
30 pF
R2
I
INCLUDING
JIG AND
SCOPE
R1481Q
OUTP~~
255Q
-
-
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
I
ALL INPUT PULSES
3.0V---R2
255Q
-
-
(b)
1464-3
THEVENIN EQUIVALENT
167Q
o-----vvv----o
1.73V
8-17
o
:E
AC Test Loads and Waveforms
R1481Q
::J
C
GND
1464-4
--.,. . -irlPRESS
......... ,
CYM1464
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel3]
1464-20
Parameter
Description
Min.
1464-22
Max.
Min.
Max.
1464-25
Min.
Max.
1464-30
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
22
20
25
22
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
20
22
25
30
ns
tDOE
OE LOW to Data Valid
13
13
15
15
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
0
tLzCS
CS LOW to Low Z
5
CS HIGH to High Z[4]
tHZCS
WRITE CYCLE[S]
20
ns
30
5
5
0
0
10
0
0
0
10
0
0
ns
10
10
15
0
ns
ns
0
5
15
30
5
0
10
5
15
0
25
5
ns
ns
20
ns
twc
Write Cycle Time
20
22
25
30
ns
tscs
CS LOW to Write End
15
17
20
25
ns
tAW
Address Set-Up to Write End
15
15
20
25
ns
tHA
Address Hold from Write End
3
3
3
3
ns
tSA
Address Set-Up to Write Start
5
5
5
5
ns
tpWE
WE Pulse Width
15
15
15
20
ns
tSD
Data Set-Up to Write End
12
12
15
15
ns
tHD
Data Hold from Write End
2
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
0
0
0
ns
tHZWE
WE LOW to High Z[4]
15
15
15
15
ns
Notes:
3.
4.
Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V; input pulse levels of 0 to 3.0V; and output
loading of the specified IorJIOH and 30-pF load capacitance.
tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
5.
8-18
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
~~PRFSS
CYM1464
·
- , SEMICONDUCTOR
Switching Characteristics Over the Operating Range (continued) [3]
1464-35
Parameter
Description
Max.
Min.
1464-45
Min.
Max.
1464-55
Min.
Max.
Unit
READ CYCLE
45
35
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
35
5
55
ns
55
45
5
5
ns
ns
tACS
CS LOW to Data Valid
35
45
55
tDOE
OE LOW to Data Valid
20
25
30
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z
0
tLZCS
CS LOW to Low Z
10
tHzCS
CS HIGH to High Z[4]
0
twc
Write Cycle Time
35
45
55
ns
tscs
CS LOW to Write End
30
40
50
ns
40
50
ns
ns
0
0
0
15
0
15
20
0
0
20
0
ns
ns
15
10
10
ns
ns
ns
20
ns
WRITE CYCLE[S]
tAW
Address Set-Up to Write End
30
tHA
Address Hold from Write End
3
3
3
tSA
Address Set-Up to Write Start
6
5
5
ns
tpWE
WE Pulse Width
25
35
40
ns
tSD
Data Set-Up to Write End
20
25
35
ns
tHD
Data Hold from Write End
2
3
3
ns
tJ)
0
0
ns
..oJ
tLzWE
WE HIGH to Low Z
tHzWE
WE LOW to High Z[4]
0
15
15
20
ns
Switching Waveforms
Read Cycle No. 1[6, 7]
}=
ADDRESS
DATA OUT
------l= ~HA
PREVIOUS DATA VALID
~
I
tM
3XXX*================D=AT=A=V=A=L=ID===========
1464-5
Notes:
6. WE is HIGH for read cycle.
7.
8-19
Device is continuously selected, CS = VIL.
I
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~
C
o
==
g :~PRFSS
CYM1464
~, SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No. 2[6,8]
CS
tRC
~K.
/~
tACS
~r
~,
tDOE
tHZOE
DATA OUT
HIGH IMPEDANCE
I/////V
~'":'\.,,'\.1',.
tLZCS
j4--tpu
J}
VCC _ _ _ _ _ _ _ _ _
SUPPLY
CURRENT
-
-+
~tHZCS-
-tLZOE-
HIGH
" IMPEDANCE
DATA VALID
/
I+---tpD
~ CC
I
50%
50%
ISB
1464-6
Write Cycle No.1 (WE Controlled)[S]
~------------------------twc--------------------------~
ADDRESS
~~~, ~~------------------tscs------------------~~~~-r~~~~~-r~
CS
1 4 - - - - - - - - - - - - - - - - - - - - - - tAW
~-------tSA--------~
------------------of__
~----- tpWE
----.I
14--r-------tSD------~~
DATA VALID
DATA IN
tHZWE
::1
-J)
DATA I/O ______________D_A_T_A_U_N_D_E_F_IN_E_D______________
tLZWE
HIGH IMPEDANCE
---I
I(~____
1464-7
Write Cycle No.2 (CS Controlled)[S, 9]
ADDRESS
----------.~-----tscs----~·I
~~-------tSD--------~
DATA IN
DATA VALID
-----.j
-----------------------------------------~~--H-I_G-H-IM-P-E-D-A-N-C-E-------_____
DATA I/O
DATA UNDEFINED
r
tHZWE
1464-8
Notes:
8.
Address valid prior to or coincident with CS transition Law.
9.
8-20
If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
CYM1464
Truth Table
CS
WE
OE
Input/Output
H
X
X
HighZ
L
H
L
Data Out
Read Word
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
Mode
DeselectlPower-Down
Ordering Information
Speed
(ns)
Ordering Code
Package
1Ype
Package 1Ype
Operating
Range
20
CYM1464PD-20C
PD02
32-Pin DIP Module
Commercial
22
CYM1464PD-22C
PD02
32-Pin DIP Module
Commercial
25
CYM1464PD-25C
PD02
32-Pin DIP Module
Commercial
30
CYM1464PD - 30C
PD02
32-Pin DIP Module
Commercial
35
CYM1464PD-35C
PD02
32-Pin DIP Module
Commercial
45
CYM1464PD-45C
PD02
32-Pin DIP Module
Commercial
55
CYM1464PD-55C
PD02
32-Pin DIP Module
Commercial
Document #: 38- M -00030-C
•
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==
8-21
CYM1465
CYPRESS
SEMICONDUCTOR
SI2K x 8 SRAM Module
Features
Functional Description
• High-density 4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 70 ns
• Low active power
- 605 mW (max.)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.27 in.
• Small PCB footprint
- 0.98 sq. in.
The CYM1465 is a high-performance
4-megabit static RAM module organized
as 512K words by 8 bits. This module is
constructed using four 128K x 8 RAMs
mounted on a substrate with pins. Adecoder is used to interpret the higher-order addresses (A17 and AlS) and to select one of
the four RAMs.
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW. Data on the
eight input/output pins (1100 through
1/07) of the device is written into the
memory location specified on the address
pins (Ao through A IS). Reading the device
is accomplished~ taking chip select and
output enable (OE) LOW while write enable remains inactive or HIGH. Under
these conditions, the contents of the
memory location specified on the address
pins (Ao through AlS) will appear on the
eight appropriate data input/output pins
(1100 through 1/07)'
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH.
Logic Block Diagram
Pin Configuration
DIP
Top View
10F4
DECODER
' - -_ _ _ _ _--'-_.....1-_
1/00 - 110,
1465-2
1465-1
Selection Guide
1465-70
1465-85
1465-100
1465-120
1465 150
Maximum Access Time (ns)
70
85
100
120
150
Maximum Operating Current (rnA)
110
110
110
110
110
Maximum Standby Current (rnA)
12
12
12
12
12
8-22
~~
_'=
---=-iF
·
CYM1465
CYPRESS
SEMICONDUCTOR
Operating Range
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................. Ambient Temperature with
Power Applied .........................
Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
in High Z State .........................
DC Input Voltage .......................
Ambient
Temperatnre
Vee
O°C to +70°C
5V ± 10%
- 40°C to +85°C
5V ± 10%
Range
55°C to + 150°C
Commercial
-10°C to +85°C
- 0.5V to + 7.0V
Industrial
- O.5V to +7.0V
- O.5V to +7.0V
Electrical Characteristics Over the Operating Range
1465
Parameter
= Min., IOH = - 1.0 rnA
Vee = Min., IOL = 2.1 rnA
Output HIGH Voltage
VOH
Min.
Test Conditions
Description
VOL
Output LOW Voltage
Unit
Max.
2.4
Vee
V
0.4
V
V
VIR
Input HIGH Voltage
2.2
Vee + 0.3
VrL
Input LOW Voltage
- 0.3
0.8
V
Irx
Input Load Current
GND~ Vr~ Vee
-10
+10
!LA
-20
+20
f.lA
110
rnA
12
rnA
8
rnA
420
!LA
loz
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
lee
Vee Operating Supply
Current
Vee
ISBl
Automatic CS Power-Down
Current
Max. Vee, CS L VIR,
Min. Duty Cycle = 100%
ISB2
Automatic CS Power-Down
Current
Max. Vee, CS .2': Vee - O.2V,
VIN L Vee - 0.2Vor VrN ~ 0.2V
= Max., lOUT = 0 rnA, CS ~ VrL
I Standard Version
I L VersIOn
.
::l
Description
Parameter
CrN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
45
pF
45
pF
AC Test Loads and Waveforms
5V:=F11.847kQ
5V:R1.847kQ
3.0V-----
CL[2]
J
1kQ
-
-
-
(a)
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
J
INCLUDING
JIG AND
SCOPE
5 pF
-
1kQ
G N D - - -....I
~
10ns
-
(b)
1465·3
Equivalent to:
(/)
W
...J
Capacitance[l]
INCLUDING
JIG AND
SCOPE
I
1465·4
THEVENIN EQUIVALENT
648Q
OUTPUT 0-----'Wv----0 1.76V
Notes:
1. Tested on a sample basis.
2.
8-23
Test conditions assume signal transition times of 10 ns or less, timing
reference levels of 1.5V; input levels of 0 to 3.0V; and output loading of
the specified IorJIOH and 100-pF load capacitance for 85-, 100-, 120-,
and 150-ns speeds. CL = 30 pF for 70-ns speed.
C
o
:::E
CYM1465
Switching Characteristics Over the Operating Rangd2]
1465-70
Parameter
Description
Min.
1465-85
Max.
Min.
Max.
1465-100
Min.
Max.
1465-120
Min.
1465-150
Max.
Min.
Max.
Unit
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
70
85
100
70
10
10
10
150
120
100
85
120
ns
150
10
10
ns
ns
tAes
CS LOW to Data Valid
70
85
100
120
150
ns
tDOE
OE LOW to Data Valid
35
45
50
60
75
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[3]
55
ns
tLzes
CS LOW to Low Z
tHzes
CS HIGH to High Z[3]
60
ns
5
5
5
25
30
10
10
5
30
ns
45
10
30
5
35
10
10
35
ns
45
WRITE CYCLE[4]
twe
Write Cycle Time
70
85
100
120
150
ns
ns
tses
CS LOW to Write End
65
75
90
100
115
tAW
Address Set-Up to Write End
65
75
90
100
110
ns
tHA
Address Hold from Write End
0
5
5
5
5
ns
tSA
Address Set-Up to Write Start
0
5
5
5
5
ns
tpWE
WE Pulse Width
55
65
75
85
95
ns
tSD
Data Set-Up to Write End
30
35
40
45
50
ns
tHO
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z
5
5
5
5
5
ns
tHZWE
WE LOW to High Z[3]
25
30
35
40
45
ns
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial
Parameter
Description
Test Conditions
VOR
Vee for Retention Data
CS~
IceoR3
Data Retention Current
tCOR[5]
Chip Deselect to Data Retention Time
VOR = 3.0Y,
CS ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
tR[5]
Operation Recovery Time
Vee - 0.2V
VIN~O.2V
Notes:
3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. 'fransition
is measured ±500 mV from steady-state voltage.
4. The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
5.
8-24
Min.
Max.
2
Industrial
Min.
Max.
Unit
150
fAA
2
50
V
0
0
ns
5
5
ms
Guaranteed, not tested.
~
~ :~PRESS
-IF
CYM1465
SEMICONDUcrOR
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
f~DR1465-5
Switching Waveforms
Read Cycle No. 1[6,7]
-t=
'li~HA
ADDRESS _ _ _ _ _ _
DATA OUT
~R
*-
1
~
PREVIOUS DATA VAUD 3XXX*================D=AT=A=V=A=L=ID===========
1465-6
Read Cycle No. 2[6,8]
cs
tRC
~"
/'{
tACS
~
'\~
tDOE
•
tHZOEI+-tHZCS-
~tL20E-
HIGH IMPEDANCE
DATA OUT
tL2CS
/////v
"
/
DATA VALID
'-"""""
HIGH
IMPEDANCE
1465-7
:E
ADDRESS
~-----------------tscs--------------------~
~----------------------tAW-------------------'~---
~-----tpWE -----.t- _ - - - - - - - - - -
DATA IN
DATA VALID
tHZWE
:1
>
DATA OUT _ _ _ _ _ _ _ _D_A_T_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _ _ _
tL2WE
--..j
HIGH IMPEDANCE
I(r------1465-8
Notes:
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL.
~
C
o
~--------------------------twc--------------------------~~
6.
7.
w
.J
Write Cycle No.1 (WE Controlled)[4]
_ _ _'--I-_-:..-:..:.:.:::_tS_A_-_-_-_-_-_-_-_--....,"'C~+~~
Ien
8.
8-25
Address valid prior to or coincident with CS transition LOW.
~
s·_.iF;~PRESS
CYM1465
SEMICONDUcrOR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[4, 9]
ADDRESS
-----------.~------tscs------~
----~----------------------~
,--------~---------
~~-------tSD-------4~
DATA IN
DATA VALID
tHZWE
::::j
DATA OUT ---------------D-A-I-A-U-N-D-E-F-IN-E-D---------------
»___
H_I~G_H_IM
__
PE_D~A~N~C~E~__________
1465·9
Note:
9.
If CS goes HIGH simuitaneouslywith WE HIGH, the output remains
in a high-impedance state.
Truth Table
Inputs
CS
OE
WE
H
X
X
HighZ
Output
DeselectlPower-Down
L
H
L
Data Out
Read Word
Mode
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
8-26
·
.~
~.iF
--=-,
CYM1465
CYPRESS
SEMICONDUCTOR
Ordering Information
Speed
(ns)
70
Ordering Code
CYMI465PD-70C
Package
Name
Package 'JYpe
Operating
Range
PD03
32-Pin DIP Module
Commercial
PD03
32-Pin DIP Module
Commercial
PD03
32-Pin DIP Module
Industrial
PD03
32-Pin DIP Module
Commercial
PD03
32-Pin DIP Module
Industrial
PD03
32-Pin DIP Module
Commercial
PD03
32-Pin DIP Module
Industrial
PD03
32-Pin DIP Module
Commercial
PD03
32-Pin DIP Module
Industrial
CYMI465LPD-70C
85
CYMI465PD-85C
CYMI465LPD-85C
CYMI465PD-85I
CYMI465LPD-85I
100
CYMI465PD-100C
CYMI465LPD-100C
CYMI465PD-I00l
CYMI465LPD-100I
120
CYM1465PD-120C
CYMI465LPD-120C
CYM1465PD-1201
CYM1465LPD -1201
150
CYM1465PD-150C
CYMI465LPD-150C
CYM1465PD-1501
CYMI465LPD-150I
Document #: 38.:.... M -00036-C
Ien
w
.J
;::)
C
o
:::E
8-27
CYM1471
CYM1481
l024Kx 8 SRAM Module
2048K x 8 SRAM Module
Features
Functional Description
• High-density 8-/16-megabit SRAM
modules
• High-speed CMOS SRAMs
- Access time of 85 ns
• Low active power
- 605 mW (max.), 2M x 8
• Double-sided SMD technology
• TTL-compatible inputs and outputs
• Very low profile version (PF)
- Max. height of 0.205 in.
• Small footprint SIP version (PS)
- PCB layout area of 0.72 sq. in.
• 2V data retention (L version)
• Compatible with CYM1460/CYM1461
The CYMI471 and CYM1481 are highperformance 8-megabit and 16-megabit
static RAM modules organized as 1024K
words (1471) or 2048K words (1481) by 8
bits. These modules are constructed from
eight (1471) or sixteen (1481) 128K x 8
SRAMs in plastic surface-mount packages
on an epoxy laminate board with pins. Two
choices of pins are available for vertical
(PS) or horizontal (PP) through-hole
mounting. On-board decoding selects one
of the SRAMs from the high-order address
lines, keeping the remaining devices in
standby mode for minimum power consumption.
An active LOW write enable signal (WE)
controls the writin~adin~eration of
the memory. When MS and WE inputs are
both LOW, data on the eight data input/
output pins is written into the memory location specified on the address pins. Reading the device is accomplished by selecti!!g
the device and enabling the outputs MS
and OE active LOW while WE remains inactive or HIGH. Under these conditions,
the content of the location addressed by
the information on the address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
Pin Configuration
---------------------------------,
I Ao-A16
I
I
I
I
I
I
I
I
I
I
I
17
DE
i
WE
IA17 -A20
I
I
I
I
SIP
Top View
I
I
I
I
I
MS
L___
CYM1471
GND
1/0 5
A10
A11
As
A13
A20 (1481)
MS(1471)
~
A1S
A16
A12
A 18
As
1/0 1
GND
AQ
1471-1
1471-2
Selection Guide
CYM1481
CYM1471
Maximum Access Time (ns)
85
100
120
85
100
120
Maximum Operating Current (rnA)
95
"'"
~J
"'"
~J
.l.lV
110
110
Maximum Standby Current (rnA)
16
16
16
32
32
32
8-28
.•
CYM1471
CYM1481
:~PRESS
- . I F SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................. - 55°C to + 125°C
Ambient Temperature with
Power Applied ........................... O°C to +70°C
Supply Voltage to Ground Potential. . . . . . .. - O.3V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - 0.3V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . ... - O.3V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Operating Range
Ambient
Temperature
Range
Commercial
Vee
5V ± 10%
O°C to +70°C
Electrical Characteristics Over the Operating Range
1471
Parameter
Description
Test Conditions
Min.
= Min., IOH = - 1.0 rnA
= Min., IOL = 2.0 rnA
2.4
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GND~VI~Vee
Ioz
Output Leakage Current
GND
Icc
Vee Operating Supply
Current
Vee
ISBl
Automatic MS
Power-Down Current
Max. Vee, MS L VIH,
Min. Duty Cycle = 100%
ISB2
Automatic MS
Power-Down Current
Max. Vee, MS L Vee 0.2Y, VIN L Vee - 0.2Y,
or VIN ~ 0.2V
Vo
~
Min.
Max.
2.4
Vee, Output Disabled
Unit
V
0.4
2.0
~
1481
Max.
0.4
V
Vee + 0.3
V
Vee + 0.3
2.2
- 0.3
0.8
-0.3
0.8
V
-20
+20
-20
+20
ftA
-20
+20
-20
+20
ftA
95
110
rnA
16
32
rnA
16
32
rnA
250
500
f.tA
= Max., MS ~ VIL, lOUT = 0 rnA
I Standard
I L Version
I
fJ)
W
Capacitance[l]
...I
Parameter
Description
Test Conditions
CINA
Input Capacitance (Ao-16, OE, WE)
CINB
Input Capacitance (A17-20, MS)
COUT
Output Capacitance
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
:::l
CYM1471
Max.
CYM1481
Max.
Unit
75
125
pF
25
25
pF
95
165
pF
Note:
1. Tested on a sample basis.
AC Test Loads and Waveforms
R125300
5V~
OUTPUT
100 pF
I
R125300
5V
R2
OUTPUT
28300
INCLUDING JIG AND
SCOPE
-
Equivalent to:
OUTPUT
TI
5 pF
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
I
3.0V---90%
R2
28300
-
-
(b)
1471·3
THEVENIN EQUIVALENT
13400
o------vvv-----
2.64V
8-29
GND
1471·4
C
o
:E
CYM1471
CYM1481
~
~iil#CYPRESS
~,
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd 2)
1471-100
1481-100
1471-85
1481-85
Description
Parameter
Max.
Min.
Min.
1471-120
1481-120
Max.
Min.
Max.
Unit
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
100
85
120
85
120
100
10
10
ns
ns
ns
10
tAMS
MS LOW to Data Valid
85
100
120
ns
tDOE
OE LOW to Data Valid
45
50
60
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z(3)
45
ns
tLZMS
MS LOW to Low Z(4)
tHZMS
MS HIGH to High Z[3, 4)
5
5
5
30
ns
35
10
10
10
30
ns
45
35
ns
WRITE CYCLE[S)
twe
Write Cycle Time
85
100
120
ns
tSMS
MS LOW to Write End
75
90
100
ns
tAW
Address Set-Up to Write End
75
90
100
ns
tHA
Address Hold from Write End
7
7
7
ns
tSA
Address Set-Up to Write Start
5
5
5
ns
tpWE
WE Pulse Width
65
75
85
ns
ns
tSD
Data Set-Up to Write End
35
40
45
tHD
Data Hold from Write End
5
5
5
tHZWE
WE LOW to High Z(3)
tLzWE
WE HIGH to Low Z
30
ns
40
35
5
5
ns
ns
5
Data Retention Characteristics (L Version Only)
1471-85
Parameter
Description
VDR
Vee for Retention Data
IceDR
Data Retention Current
tCDR(6)
Chip Deselect to Data
Retention Time
tR
Operation Recovery Time
1471-100
1471-120
1481-85
1481-100
1481-120
Min. Max. Min. Max. Min. Max. Min. Max.
Test Conditions
Ycc =
2
3.0V,
MS ~ Vee - 0.2V,
VIN ~ Vee - 0.2Vor
VIN .s0.2V
Notes:
2. Test conditions assume signal transition time of 10 Its or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading
of 1 TTL load, and 100-pF load capacitance.
3. tHZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads and Waveforms. ltansition is measured ±SOO mV
from steady-state voltage.
4. At any given temperature and voltage condition, tHZMS is less than
tLzMS for any given device. These parameters are guaranteed and not
100% tested_
2
125
400
5.
6.
8-30
2
2
V
250
800
Unit
JlA.
0
0
0
0
ns
5
5
5
5
ns
The internal write time of the memory is defined by the overlap of MS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
Guaranteed, not tested.
-
--=.
CYM1471
CYM1481
:~PRESS
JF
SEMICONDUCTOR
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR 2:. 2V
f~R1471-5
Switching Waveforms
Read Cycle No. }[7,8]
~
ADDRESS
-~'OHA~
DATA OUT
*-
tRC
PREVIOUS DATA VALID
1
'XXX*'--_-_-_-_~-_-_-_-_-_-_-_-_-_-_-D_A-_T-A~_V-A~L~ID~~~~~~~~~~_=
1471-6
II
Read Cycle No. 2[8,9]
tRC
~,
j.t:
C/)
W
.J
::l
tAMS
;t
~K.
I
tDOE
DATA OUT
tLZMS
:E
tHZOE-tHZMS-
~tLZOE-
HIGH IMPEDANCE
C
o
V/////
DATA VALID
1"-"""""""
Notes:
7. Device is continuously selected. OE, MS = VIL.
8. Address valid prior to or coincident with MS transition LOW
HIGH
"\. IMPEDANCE
/
1471-7
9.
8-31
WE is HIGH for read cycle.
CYM1471
CYM1481
~
...........
:~PRESS
-=-_,
SEM]CONDUCTOR
Switching Waveforms (continued)
Write Cycle No.
tl5, 10]
~--------------------------twc--------------------------~
ADDRESS
~~+,
.,.f---------------- tSMS ----------------------..t
""'''''''"''''7'"'"7''''''7''''''7I-''''-:''''''"''''7'"'"7'''-r-
fiifS
~---------------------
tAW
--------------------101+-
14_----tSA -------~
14_----- tPWE
-----..t
~~-------tSD--------14-
DATA IN
DATA VALID
t
HZWE
=1
--J)
DATAI/O _______________D_A_I_A_U_N_D_E_F_IN_E_D______________
tLZWE
---I
HIGH IMPEDANCE
I(~---------1471-8
Write Cycle No. 2[5, 10, 11]
ADDRESS
-----------.~------tSMS----~~
~~-------tSD-------14-
DATA IN
DATA VALID
_
t_H_ZW_E_~J.--------------------------HIGH IMPEDANCE
______________________________________
DATAI/O
DATA UNDEFINED
1471-9
Notes:
10. Data I/O is high impedance if OE = Vm.
11. IfMS goes HIGH simuitaneousiywith WE HIGH, the output remain s
in a high-impedance state.
'fruth Table
MS
WE
OE
H
X
X
Input/Outputs
HighZ
L
H
L
Data Out
Read
Data In
Write
HighZ
Deselect
Mode
DeselectlPower-Down
8-32
CYM1471
CYM1481
-~
. !iii CYPRESS
====.'
SEMICONDUCTOR
Ordering Information
Speed
(ns)
85
Ordering Code
CYM1471PF -85C
Package
1Ype
Package
1Ype
Operating
Range
PF05
36-Pin Flat SIP Module
Commercial
PS08
36-Pin SIP Module
PF05
36-Pin Flat SIP Module
PS08
36-Pin SIP Module
PF05
36-Pin Flat SIP Module
PS08
36-Pin SIP Module
PF04
36-Pin Flat SIP Module
PS06
36-Pin SIP Module
PF04
36-Pin Flat SIP Module
PS06
36-Pin SIP Module
PF04
36-Pin Flat SIP Module
CYM1471LPF -85C
CYM1471PS-85C
CYM1471LPS-85C
100
CYM1471PF-100C
Commercial
CYM1471LPF -lOOC
CYM1471PS-100C
CYM1471LPS-100C
120
CYM1471PF -120C
Commercial
CYM1471LPF -120C
CYM1471PS-120C
CYM1471LPS-120C
85
CYM1481PF -85C
Commercial
CYM1481LPF -85C
CYM1481PS-85C
CYM1481LPS-85C
100
CYM1481PF-100C
Commercial
CYM1481LPF-100C
CYM1481PS-100C
120
CYM1481PF -120C
Commercial
W
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:::>
C
o
CYM1481LPF-120C
CYM1481PS-120C
•
U)
CYM1481LPS-100C
PS06
36-Pin SIP Module
CYM1481LPS-120C
Document #: 38-M-00041-A
8-33
:E
PRELIMINARY
CYPRESS
SEMICONDUCTOR
1024Kx 9 Buffered SRAM
Module with Separate I/O
Features
Functional Description
• High-density 8-megabit SRAM
module plus parity
• High-speed CMOS SRAMs
- Access time of 30 ns
• Buffered address and control inputs
• Low active power
-6.2W (max.)
The CYM1560 is a very high performance
8-megabit static RAM module organized
as 1024K words by 9 bits. This module is
constructed using nine 1024K x 1 static
RAMs in SOJ packages mounted on an
epoxy laminate board with pins. Input
buffers are provided on the address and
control lines to reduce input capacitance
and loading.
Writing to the module is accomplished
when the chip select (CS) and write enable
(WE) inputs are both LOW Data on the
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.53 in.
• Small PCB footprint
-1.5 sq. in.
CYM1560
data input pins (DIo through DIs) of the
device is written into the memory location
specified on the address pins (Ao through
A19). Reading the device is accomplished
by taking chip select LOW while write enable remains inactive or HIGH. Under
these conditions, the contents of the memory location specified on the address pins
will appear on the appropriate data output
pins.
The data output pins remain in a high-impedance state when chip select is HIGH or
when write enable is LOW
Pin Configuration
Logic Block Diagram
SIP
Top View
DOo - DOa
1560-1
1560-2
Selection Guide
CYM1560-45
CYM1560-30
CYM1560-35
30
35
45
Maximum Operating Current (rnA)
1125
1125
1125
Maximum Standby Current (rnA)
350
350
350
Maximum Access Time (ns)
8-34
.. ~
PRELIMINARY
_ · i l l CYPRESS
- , SEMICONDUcrOR
Maximum Ratings
(Above which the useful life may be impaired.)
CYM1560
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
Storage Temperature .................. - 45 ° C to + 125 ° C
Ambient Temperature with
Power Applied ......................... -10°C to +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.3V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Commercial
Electrical Characteristics Over the Operating Range
CYM1560
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Level, Ao
IlL
Input Load Current
loz
Output Leakage Current
lee
Vee Operating Supply Current
Vee
ISBl
Automatic CS Power-Down Currentl1]
ISB2
Automatic CS Power-Down Current[l]
- A19, CS, WE
Min.
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
Max.
Units
2.4
V
0.4
V
2.2
6.0
V
- 0.3
0.8
V
-1.2
V
GNDs VIS Vee
-10
+10
!lA
GND S Vo s Vee, Output Disabled
-10
+10
!lA
1125
rnA
Max. Vee, CS L VIR,
Min. Duty Cycle = 100%
350
rnA
Max. Vee, CS L Vee - 0.2Y,
VIN L Vee - O.2V or VIN S 0.2V
230
rnA
Vee
= Min., lIN = -
= Max., CS S
18 rnA
VIL, lOUT
= 0 rnA
UJ
W
.J
Capacitance[2]
Parameters
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. A pull-up resistor to Vee on the CS input is required to keep the
device deselected during power-up, otherwise ISB will exceed values given.
2.
= 1 MHz,
Max.
Units
15
pF
20
pF
481Q
Tested on a sample basis.
OUTP~~ ~
1J
.~~~~F
-
1255Q
_
OUTP~~ ~
-
1J
.~ . ~:F
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
481Q
-
3.0V---90%
1255Q
_
1560-3
1560-4
THEVENIN EQUIVALENT
OUTPUT~
GND
-
(b)
1.73V
8-35
::l
C
o
::is
AC Test Loads and Waveforms
INCLUDING
JIG AND
SCOPE
•
~~~CTI)R
PRELIMINARY
CYMlS60
Switching Characteristics Over the Operating Rangel 3]
1560-30
Description
Parameters
Max.
Min.
1560-35
Min.
Max.
1560-45
Min.
Max.
Units
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
30
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z
5
tHZCS
CS HIGH to High Z[4]
2
tpu
CS LOW to Power-Up
3
tpD
CS HIGH to Power-Down
45
35
30
35
5
5
30
35
2
45
ns
20
ns
ns
5
20
2
ns
3
3
30
ns
5
5
20
ns
45
ns
45
35
ns
WRITE CYCLE[S]
twc
Write Cycle Time
30
35
45
ns
tscs
CS LOW to Write End
20
25
35
ns
tAW
Address Set-Up to Write End
20
25
35
ns
tRA
Address Hold from Write End
5
5
5
ns
tSA
Address Set-Up from Write Start
5
5
5
ns
tpWE
WE Pulse Width
20
25
35
ns
tSD
Data Set-Up to Write End
15
20
25
ns
tHD
Data Hold from Write End
5
5
5
ns
tLZWE
WE HIGH to Low Z
2
2
2
tHZWE
WE LOW to High Z[4]
2
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.Sv, input pulse levels of 0 to 3.0V, output loading
of the specified IorJIOH, and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
20
5.
6.
7.
2
20
2
ns
20
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL.
Switching Waveforms
Read Cycle No.
ADDRESS
DATA OUT
tl6,7]
t=
------1=
IoHA
PREVIOUS DATA VALID
~
IRe
1
*-
3XXX*================D_A-T=A=V=A=L=ID===========
1560-5
8-36
·
·~PRFSS
~JF
PRELIMINARY
CYM1560
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No. 2[6, 8]
tRC
~,
}~
-tHZCS
tACS
~////V
HIGH IMPEDANCE
DATA OUT
tLZCS
-tpu
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
-
t
~
DATA VALID
1''''-'''-'''-'''
I
HIGH
IMPEDANCE
/I
-tpD
50%
~
CC
I
50%
ISB
1560-6
Write Cycle No.1 (WE Controlled)[5]
~--------------------------twc--------------------------~
ADDRESS
~-----------------tscs--------------------~
~----------------------~W------------------~*----
______~I-_:.:.:.:.:::_tS_A_-_-_-_-_-_-_-_ -_""I:-I..,-t~~~ 1+------ tpWE - - -...... _ - - - - - - - - - WE
DATA IN
Ien
DATA VALID
tLZWE
tHZWE=J
-J)
---+l
HIGH IMPEDANCE
DATA OUT ______________D_A_TA__
UN_D_E_F_IN_E_D______________
I(r--------1560-7
~
C
o
:E
Write Cycle No.2 (CS Controlled) [5, 9]
ADDRESS
-----------.~------tscs-------I-t
14------ tPWE - - - - . i
WE
~~-------tSD--------~
DATA IN
DATA VALID
tHZWE
DATA OUT
w
..J
------I
----------------------~)~I
DATA UNDEFINED
.r
__
H_I_G_H_IM_PE_D_A_N_C_E_ _ _ _ ____
1560-8
Notes:
8. Address valid prior to or coincident with CS transition LOW.
9.
8"':'37
IfCS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
~
~~PRESS
~., SEMICONDUCTOR
PRELIMINARY
'fruth Table
cs
WE
Data In
H
X
X
HighZ
L
H
X
DataOuto-s Read
L
L
DataOot
Data Ino-s HighZ
Mode
DeselectlPower-Down
Write
Ordering Information
Speed
30
35
45
Ordering Code
Package
Name
Package 'JYpe
CYM1560PF - 30C
PF06
44-Pin Flat SIP Module
CYM1560PS-30C
PS07
44-Pin Plastic SIP Module
CYM1560PF - 35C
PF06
44-Pin Flat SIP Module
CYM1560PS- 35C
PS07
44-Pin Plastic SIP Module
CYM1560PF -45C
PF06
44-Pin Flat SIP Module
CYM1560PS-45C
PS07
44-Pin Plastic SIP Module
Document #: 38-M-00043-A
8-38
Operating
Range
Commercial
Commercial
Commercial
CYM1560
CYM1622
64K X 16 Static RAM Module
Features
Functional Description
• High-density I-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 25 ns
The CYM1622 is a very high performance
1-megabit static RAM module organized
as 64K words by 16 bits. The module is
constructed using four 64K x 4 static
RAMs mounted onto a vertical substrate
with pins. The pinout of this module is
compatible with another Cypress module
(CYM1611)tomaximizesystemfiexibility.
• Low active power
- 2.2W (max.)
•
•
•
•
SMD technology
TTL-compatible inputs and outputs
Pinout compatible with CYM1611
Low profile
- Max. height of .50 in.
• Small PCB footprint
- 0.68 sq. in.
Writing to the memory module is accomplished when the chip select (CS) and write
enable (WE) inputs are both LOW Data
on the sixteen input/output pins (1/00
through 1/015) ofthe device is written into
Logic Block Diagram
the memory location specified on the address pins (Ao through AlS).
Reading the device is accomplished by taki~chip select (CS) and output enable
(OE) LOW, while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the appropriate data input/output
pins.
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable (WE) is HIGH.
Pin Configuration
VDIP
Top View
1/0 0
1/0 1
1/02
1/03
Ao
A1
A2
A3
~
A5
As
A7
1/04
1/05
1/0 6
1/07
1/00 -1/015
CS
GND
A14
1622·1
NC
1•
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
::J
Vee
1/015
1/0 14
1/013
1/012
GND
A13
A12
An
AlO
Ag
Aa
1/0 11
1/010
I/Og
I/Oa
WE
OE
A15
NC
1622·2
Selection Guide
1622-25
1622-30
1622-35
Maximum Access Time (ns)
25
30
35
45
Maximum Operating Current (rnA)
400
400
400
400
Maximum Standby Current (rnA)
140
140
140
140
8-39
1622-45
I
tJ)
W
..J
:::»
Q
o
:e
_
======-=
-======. .,~
~,
CYM1622
CYPRESS
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired.)
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
SV ± 10%
Range
Storage Temperature .................. - 65°C to + 125°C
Ambient Temperature with
Power Applied ......................... -10°C to +80°C
Supply Voltage to Ground Potential ........ - O.SV to +7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.SV to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.SV to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Commercial
Electrical Characteristics Over the Operating Range
CYM1622
Parameter
Description
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Output HIGH Voltage
VOH
Min.
Max.
Unit
2.4
Vee
V
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
Vee
0.4
V
V
VIL
Input LOW Voltage[1]
-0.5
0.8
V
flA
IIX
Input Load Current
GND~VI~Vee
-20
+20
Ioz
Output Leakage Current
GND ~ Vo ~ V co Output Disabled
-10
+10
f.tA
Icc
Vee Operating Supply Current
Vee
400
rnA
ISBl
Automatic CS Power-Down Current
Max. V co CS ~ VIH,
Min. Duty Cycle = 100%
140
rnA
ISB2
Automatic CS Power-Down Current
Vee = Max., CS ~ Vee - O.2Y,
VIN ~ Vee - 0.2Vor VIN ~ O.2V
80
rnA
= Max., lOUT = 0 rnA, CS ~ VIL
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Notes:
1. VIL(min.) = - 3.0V for pulse widths less than 20 ns.
2.
= 1 MHz,
Max.
Unit
35
pF
15
pF
Tested on a sample basis.
AC Test Loads and Waveforms
481Q
ALL INPUT PULSES
481Q
OUTP~~ ~ OUTP~~ ~
.~~.~~F1 1255Q
.~ . ~~F1 1255Q
J J _
INCLUDING
JIG AND
SCOPE
-
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
-
90%
GND
-
1622·3
(b)
16224
THEVENIN EQUIVALENT
OUTPUT~
3.0V----
1.73V
8-40
-.-
~~
---=-,
..dE
CYM1622
CYPRFSS
SEMICONDUcrOR
Switching Characteristics Over the Operating Range[3]
1622-25
Parameter
Description
Min.
1622-30
Max.
Min.
Max.
1622-35
Min.
Max.
1622-45
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
30
35
45
tAA
Address to Data Valid
25
30
35
45
ns
tOHA
Data Hold from Address Change
3
3
3
3
ns
tACS
CS LOW to Data Valid
25
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z
tHzCS
CS HIGH to High Z[4]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
30
15
0
0
15
0
3
15
0
25
25
0
25
0
3
30
0
3
30
35
0
35
ns
ns
20
20
20
ns
30
20
20
3
45
35
20
ns
ns
ns
20
ns
45
ns
45
ns
WRITE CYCLE[S]
twc
Write Cycle Time
25
30
35
45
ns
tscs
CS LOW to Write End
20
25
30
40
ns
tAW
Address Set-Up to Write End
20
25
30
40
ns
tHA
Address Hold from Write End
3
3
3
3
ns
tSA
Address Set-Up to Write Start
2
2
2
2
ns
tpWE
WE Pulse Width
20
25
25
30
ns
tSD
Data Set-Up to Write End
15
20
20
25
ns
tHD
Data Hold from Write End
2
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
0
0
0
ns
tHZWE
WE LOW to High Z[4]
0
15
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOr./IOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) ofAC Test
Loads and Waveforms. Transition is measured ±SOO mV from steadystate voltage.
0
5.
8-41
15
0
15
0
20
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
•
CJ)
W
..J
~
C
o
:!E
·
.~
~jJl CYPRESS
~_,
CYM1622
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[6,7]
FIRe
'LLHA
DATA OlIT
PREVIOUS DATA VALID
*-
I
\AA
ADDRESS-----....
3XXX*===============_D-_A-T=A=V=A=L=ID===========
1622-5
Read Cycle No. 2[6, 8]
cs
tRC
~K
/'?
tACS
~
~,
tHZOE ---+
1
tOOE
-tHZCS-
-tLZOEHIGH IMPEDANCE
I/////V
DATA OUT
1'-"" "
tLZCS
HIGH
"' IMPEDANCE
DATA VALID
/
_tpo
tpu
SUPPLY
CURRENT
~ CC
I
VCC _ _ _ _ _ _ _
}
50%
50%
-
ISB
1622-6
Write Cycle No.1 (WE Controlled)[5]
~--------------------------twc--------------------------~
ADDRESS
~-----------------tscs--------------------~
~----------------------~w-------------------'~--____~":.:.:._:.::::_t_SA_-_-_-_-_-_-_-_-_.. ., , , ~+~~ ~-----tpwE - - -...... , _ - - - - - - - - - -
DATA IN
DATA VALID
tHZWE~
y
DATA OUT _ _ _ _ _ _ _ _D_A_T_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _ _ _
-
tlZWE
----I
HIGH IMPEDANCE
I(~_______
1622-7
Notes:
6.
7.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL.
8.
8-42
Address valid prior to or coincident with CS transition LOW.
.~
'i; CYPRESS
.
_
iF
CYM1622
SEMICONDUcrOR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled) [5, 9]
ADDRESS
-----------.~------tscs----~~
(4------ tpWE - - - -.....
(4-~-------tSD-------.~
DATA IN
DATA VALID
tHZWE
DATA OUT
-----..j
-----------------------------------------~)~I--H-I-G-H-IM-P-E-D-A-N-C-E---________
DATA UNDEFINED
. ,..
1622-8
Note:
9. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Table
CS
OE
WE
H
X
X
HighZ
Input/Output
Deselect/power-Down
Read
•
Mode
L
L
H
Data Out
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
en
w
..J
:J
C
o
Ordering Information
Package 'fYpe
Operating
Range
25
CYM1622PV-25C
PV04
40-Pin Plastic VDIP Module
Commercial
30
CYM1622PV -30C
PV04
40-Pin Plastic VDIP Module
Commercial
35
CYM1622PV -35C
PV04
40-Pin Plastic VDIP Module
Commercial
45
CYM1622PV -45C
PV04
40-Pin Plastic VDIP Module
Commercial
Speed
Ordering Code
Package
Name
Document#: 38-M-0000I-C
8-43
:E
CYM1720
32K X 24 Static RAM Module
Features
• High-density 768-kilobit SRAM
module
• High-speed CMOS SRAMs
- Access time of 15 ns
• 56-pin, 0.5-inch-high ZIP package
• Low active power
-1.8W (max. for tAA = 25 ns)
• SMD technology
• TTL-compatible inputs and outputs
• Commercial temperature range
• Small PCB footprint
- 0.66 sq. in.
Functional Description
The CYMl720 is a high-performance
768-kilobit static RAM module organized
as 32K words by 24 bits. This module is
constructed using three 32K x 8 static
RAMs in SOJ packages mounted onto an
epoxy laminate board with pins.
Writing to the device is accomplished when
the chip select (CS) and write enable (WE)
inputs are both LOW. Data on the input/
output pins (1/00 through 1/023) of the de-
vice is written into the memory location
specified on the address pins (Ao through
A14)'
Reading the device is accomplished by taking the chip select (CS) and output enable
(OE) LOW while write enable (WE) remains HIGH. Under these conditions, the
contents of the memory location specified
on the address pins will appear on the input/output pins.
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH.
Pin Configuration
Logic Block Diagram
ZIP
Top View
Vee
Vee
1/°1
1/°3
1/05
1/07
/
/15
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
GND
32Kxa
/
SRAM
Al
A3
1/00 -1/0 7
/a
As
A7
NC
GND
r--32Kxa
/
SRAM
/a
I/Og
1/°11
1/013
1/°15
I/Os -1/015
NC
DE
Ag
All
A13
32Kxa
/
SRAM
'a
NC
GND
1/016 -1/0 23
1/°17
1/0 19
1/°21
1/0 23
1720-1
Vee
1/°0
1/°2
1/04
1/°6
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
GND
Ao
A2
~
~
NC
I/Os
1/°10
1/012
1/°14
GND
WE
As
AlO
A12
A14
GND
1/°16
1/0 1S
1/°20
1/°22
Vee
1720-2
Selection Guide
f' 1720-1S;;;~v
15
Maximum Access Time (ns)
I;}
Maximum Operating Current (rnA)
r;~~;i 450
Maximum Standby Current (rnA)
~:
V[,v'
;120
1720!~20
Z~i~;
45qilf;
120
Shaded area contams prehmmary mformatJon.
8-44
1720-25
ci
1720-30
1720-35
25
30
35
330
330
330
60
60
60
·
.~
-=-,fie
CYM1720
CYPRESS
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. - 55°C to + 125°C
Ambient Temperature with
Power Applied ........................ -10°C to +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Operating Range
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
Commercial
Electrical Characteristics Over the Operating Range
CYM1720:-15,20 CYMl720-25, 30, 35
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
Max. ..
Max.
V
0.4
0.4
V
Vee
2.2
Vee
V
-0.5
0.8
- 0.5
0.8
V
-20
+20"
-20
+20
flA
+10
-10
+10
flA
450
330
rnA
60
rnA
60
rnA
IIX
Input Load Current
Ioz
Output Leakage Current
GND ~ Vo ~ Vee,
Output Disabled
Icc
Vee Operating Supply
Current
Yce
ISBl
Automatic CS
Power-Down Current[l)
Max. Vee, CS ~ VIR,
Min. Duty Cycle = 100%
120
ISB2
Automatic CS
Power-Down Current[l)
Max. Vee, CS ~ Vee - 0.2v,
VIN ~ Vee - O.2V or VIN ~ O.2V
90
GND~VI~Vee
Unit
2.4
2.2,
... -10
,
= Max., lOUT = 0 rnA,
CS~
Min.
,2.4
VIL
0;;:
a
tJ)
Shaded area contams prelImmary mformatlOn.
W
..J
:l
Capacitance[2)
C
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. A pull-up resistor to Vee on the CS input is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
2.
= 1 MHz,
Max.
Unit
35
pF
25
pF
Tested on a sample basis.
AC Test Loads and Waveforms
4810
481Q
OUTP~~ ~
1J
In~~:F
INCLUDING
JIG AND
SCOPE
-
1255Q
_
OUTP~~ ~
-
1J
In,.~:F
INCLUDING
JIG AND
SCOPE
-
90%
1255Q
_
1720-3
1720-4
THEVENIN EQUIVALENT
OUTPUT~
GND
-
(b)
(a)
Equivalent to:
ALL INPUT PULSES
3.0V----
1.73V
8-45
o
:E
~~
~: CYPRESS
CYM1720
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel 3]
~fl'tlJ~lS'}I) i720~i~
.
1720-25
1720-30
1720-35
~~.;Max; ';"ip., ,z~i!. Min. Max. Min. Max. Min. Max.
Description
Parameter
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
~.
Iy
ij'. ~"l
3)'1
'.,
25
.;~
0
,.
. ~1t) .'.
~.}
3
'.
~
,,;11%/;
:20
'0
~'.">'
.':
;t
~'"
3
25
ns
35
30
3
35
ns
ns
3
25
30
35
ns
10
15
18
ns
.10' .
"j;; •
~~
10
,.~
3
,,)
';,
ns
20
20
5
20
.. '~~.
0
20";.;
, ".
0
ns
0
\. :;1;
"a"? "
0
0
"?:,/f '20"
1:5'
30
·~~tiL· 10
iF,l'(),l t~~l
I', (3"
"'I""
25
2P;:,;;
7
10
t
20;\;';\
3
0
25
ns
20
20
25
ns
ns
0
30
ns
WRITE CYCLE[6]
tscs
CS LOW to Write End
I;:~
2'0
tAW
Address Set-Up to Write End
~i;i'20
tHA
Address Hold from Write End
2
tSA
Address Set-Up to Write Start
;:,,1 5
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
Data Hold from Write End
... '.•. 2.
tLzWE
WE HIGH to Low Z
t.O
twc
Write Cycle Time
~O
'12
1",'.
20
<
.·'.it;,;:
";
15 hi
i
1$\ .
", 5' I 2 ~J :
;;!
;'f. n:
'yo .', 10,~
WE LOW to High Z[5]
tHZWE
Shaded area contams prehmmary mformatlOn.
Notes:
3. Test conditions assume signal transition time of S ns or less, timing reference levels of 1.SV, input pulse levels of 0 to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
S. tHZOE, tHZCS, and tLZCE are specified with CL = S pF as in part (b) of
AC Thst Loads and Waveforms. Transition is measured ± SOO mV from
steady-state voltage.
J5 i
""
10
2
30
35
ns
20
25
30
ns
"
20
25
30
ns
,::
2
5
5
ns
\
5,
<:~~:
<
25
'1\,
;<..
5
5
5
ns
20
25
25
ns
12
18
18
ns
2
3
3
ns
0
0
5
5
ns
0
0
6.
8-46
.(
10
0
15
0
15
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
=s'-
.~
5iiiiii=
::::c
IF
CYM1720
CYPRESS
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[7,8]
}=
ADDRESS
------1=
DATA OUT
IOHA
*-
IRe
~
1
PREVIOUS DATA VAUD 3XXX*================D_A-I=A=V.=A=L=ID===========
1720-5
Read Cycle No. 2[7, 9]
tRC
~"\..
/'{
tACS
-+:
~,
tOOE
tHZOEI+-tHZCS -
-tUOE-
HIGH IMPEDANCE
DATA OUT
tucs
/////V
"''-"'--"'-""''\..
"
/
DATA VALID
~tpo
_tpu
---1~
SUPPLY _ _ _ _ _ _---.7f 50%
HIGH
IMPEDANCE
~ CC
I
VCC
50%
ISB
CURRENT
1720-6
•
en
w
-I
Write Cycle No.1 (WE ControIled)[6, 10]
:;:)
Q
o
~--------------------twc--------------------~~
:E
ADDRESS
~~~, ~~--------------tscs--------------~~~~~~~~~~~_
~------------------tAW--------------'~---
14-----tSA
-----..t
1+----
tpWE ---~
~~----tSD--------~
DATA IN
DATA VALID
tHZWEj
--J)
DATA I/O _ _ _ _ _ _ _ _D_A_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _
tLZWE ---.j
HIGH IMPEDANCE
I(r----1720-7
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = VIL and OE= VIL.
9. Address valid prior to or coincident with CS transition Law.
10. Data UO will be high impedance if OE = VIH.
8-47
~
=:;.
_
.~
.111
JF
CYM1720
CYPRESS
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 10, 11]
ADDRESS
-----_"1+---
tscs
1 4 - - 4 - - - - tSD
DATA IN
----I~
---~..
DATA VALID
tHZWE
DATAI/O
DATA UNDEFINED
--..j
~~__H_IG_H__IM_P_E_D_AN_C_E_____________
------------------------'
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
'fi'uth Table
CS
WE
OE
H
X
X
HighZ
DeselectlPower-Down
L
H
L
Data Out
Read Word
Input/Outputs
Mode
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
Ordering Information
Speed
Ordering Code
Package
Name
Package
1YPe
Operating
Range
15
CYMl720PZ-15C
PZ05
56-Pin ZIP Module
Commercial
20
CYMl720PZ-20C
PZ05
56-Pin ZIP Module
Commercial
25
CYMl720PZ-25C
PZ05
56-Pin ZIP Module
Commercial
30
CYMl720PZ-30C
PZ05
56-Pin ZIP Module
Commercial
35
CYMl720PZ- 35C
PZ05
56-Pin ZIP Module
Commercial
Document #: 38-M -00021- A
8-48
1720·8
CYM1730
PRELIMINARY
64Kx 24 Static RAM Module
Features
Functional Description
• High-density 105M SRAM module
• High-speed CMOS SRAMs
- Access time of 25 ns
• 56-pin, 0.5-inch-high ZIP package
• Low active power
-2.SW (max. for tAA = 25 ns)
• SMD technology
• TTL-compatible inputs and outputs
• Commercial temperature range
• Small PCB footprint
-1.05 sq. in.
The CYM1730 is a high-performance
1.5M static RAM module organized as
64K words by 24 bits. This module is constructed using six 32K x 8 static RAMs in
SOJ packages mounted onto an epoxy laminate board with pins.
Writing to the device is accomplished when
the chip select (CS) and write enable (WE)
inputs are both LOW. Data on the input/
output pins (1/00 through 1/023) of the device is written into the memory location
specified on the address pins (Ao through
AlS)·
Reading the device is accomplished by taki~he chip select (CS) and output enable
(OE) LOW while write enable (WE) remains HIGH. Under these conditions, the
contents of the memory location specified
on the address pins will appear on the input/output pins.
The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH.
Logic Block Diagram
Ao- A14
DE
Pin Configuration
/
/15
ZIP
Top View
WE
I--
-
32Kx8
SRAM
I
-
10F2
DECODER
f--
-
-
I
32Kx8
SRAM
I
-
-
I
I
-
I
/
'8
1/0 16 -1/0 23
32Kx8
SRAM
I
L.....--
32Kx8
SRAM
I
I
- -
-
I
I
I
I
-
/
/8
I/0a - 1/015
32Kx8
SRAM
I
I
1/01
1/°3
1/05
1/07
GND
Al
A3
A5
A7
NC
GND
I/0g
1/0 11
1/0 13
1/0 15
NC
DE
L.....-
32Kx8
SRAM
Vee
Vee
-
, /8
1/00 - 1/07
1730-1
Ag
An
A13
A15
GND
1/0 17
1/0 19
1/021
1/°23
Vee
10
12
14
16
16
20
22
24
26
26
30
32
34
36
36
40
42
44
46
46
50
52
54
56
1/0 0
1/0 2
1/04
1/0 6
GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
Ao
A2
A4
As
cs
NC
I/0a
1/0 10
1/°12
1/014
GND
WE
Aa
A10
A12
A14
GND
1/0 16
I/ 0 la
1/0 20
1/022
Vee
1730·2
Selection Guide
1730-25
1730-30
Maximum Access Time (ns)
25
30
35
Maximum Operating Current (rnA)
510
510
510
Maximum Standby Current (rnA)
180
180
180
8-49
1730-35
•
en
W
...I
::l
C
0
:E
iiTl~UCTOR
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
CYM1730
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Operating Range
Storage Temperature .................. - 55°C to + 125°C
Ambient Temperature with
Power Applied ........................ - 10°C to +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.sV to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.sV to +7.0V
Range
Commyrcial
Ambient
Temperature
O°C to +70°C
Vee
SV ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
= Min., IOH = - 4.0 rnA
= Min., IOL = 8.0 rnA
Min.
Unit
Max.
2.4
V
VOH
Output HIGH Voltage
Vee
VOL
Output LOW Voltage
Vee
VIH
Input HIGH Voltage
2.2
Vee + 0.3
V
VIL
Input LOW Voltage
- 0.3
0.8
V
0.4
V
IIX
Input Load Current
GND.s VI.s Vee
- 20
+20
loz
Output Leakage Current
GND.s Vo.s Vee,
Output Disabled
-10
+10
ftA
ftA
Icc
Vee Operating Supply Current
Vee
510
rnA
ISBl
Automatic CS Power-Down
Currend l ]
Max. Vee, CS L VIR,
Min. Duty Cycle = 100%
180
rnA
ISB2
Automatic CS Power-Down
Current[l]
Max. Vee, CS L Vee - 0.2v,
VIN L Vee - 0.2V or VIN .s 0.2V
180
rnA
= Max., lOUT = 0 rnA, CS.s VIL
Capacitance[2]
Parameter
Description
qN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Notes:
1. A pull-up resistor to Vee on the CS input is required to keep the de-
2.
= 1 MHz,
Max.
Unit
50
pF
20
pF
Tested on a sample basis.
vice deselected during Vccpower-up, otherwise ISB will exceed values
given.
AC Test Loads and Waveforms
5V
~481Q
ALL INPUT PULSES
3.0V----
5V 5 f l 4 8 1 Q
OUTPUT
90%
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
J
_
-
255Q
-
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
J
-
(b)
_
255Q
-
1730-3
THEVENIN EQUIVALENT
167Q
o-----wv---o
GND
1.73V
8-50
1730-4
==. ~~
=====
-=
PRELIMINARY
CYPRESS
. ' SEMICONDUCTOR
CYM1730
Switching Characteristics Over the Operating Range(3)
1730-25
Parameter
Description
Min.
Max.
1730-30
Min.
Max.
1730-35
Min.
Max.
Unit
READ CYCLE
30
25
ns
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACS
CS LOW to Data Valid
25
30
35
ns
tDOE
OE LOW to Data Valid
12
15
20
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
20
ns
tLzCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5)
15
ns
25
35
5
5
5
10
15
10
ns
ns
5
5
5
15
ns
ns
3
3
3
35
30
WRITE CYCLE[6)
twc
Write Cycle Time
25
30
35
ns
tscs
CS LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
22
25
30
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
20
23
25
ns
tSD
Data Set-Up to Write End
13
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
3
5
ns
tHZWE
WE LOW to High Z[5)
0
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels ofO to 3.0V, and output loading
of the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
5. tHzOE, tHzCS, and tLzcEare specified with CL = 5 pF as in part (b) of
AC Test Loads and Waveforms. Transition is measured ±500 m V from
steady-state voltage.
6.
8-51
10
0
10
0
15
ns
The internal write time ofthe memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
•
en
w
...J
:::)
C
o
:::i5
~
"""=';~PRESS
,
PRELIMINARY
.
CYM1730
SEMICONDUcrOR
Switching Waveforms
Read Cycle No. 1[7,8]
~
ADDRESS
I
---~toHA~
DATA OUT
PREVIOUS DATA VALID
*-
tRe
~XXX*================D=AT=A=V=A=L=ID===========
1730-5
Read Cycle No. 2[7, 9]
~-------------------------tRe----------------------~
~----------~es----------~
QE--I---_.
DATA OUT
HIGH
IMPEDANCE
--t----------.....
DATA VALID
~------t~es------~ ~~~~-----------~-----'
~+_E_+_{
tPD~ ICC
tpu~~________________________
---I'f 50%
cJ~::~i -----Vee
50%
ISB
1730-6
Write Cycle No.1 (WE Controlled)[6, 10]
~--------------------------twe--------------------------~
ADDRESS
~~~~ ~~---------------tses--------------------~~~~~~~~~~~~
~-------------------~-------tSA-------~
tAW
-------------------~~-----tpWE------~
~~------tSD--------~
DATA IN
DATA VALID
t
HZWE
:!
>
DATA OUT _ _ _ _ _ _ _ _D_A_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _ _ _
tL2WE --.j
HIGH IMPEDANCE
1(,..----1730-7
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = VIL and OE= VIL.
9. Address valid prior to or coincident with CS transition Law.
10. Data I/O will be high impedance if OE = VIH.
8-52
~
~~
~ICYPRESS
PRELIMINARY
~, SEMICONDUCTOR
CYM1730
Switching Waveforms (continued)
Write Cycle No.2 (CS ControlIed)[6, 10, 11]
ADDRESS
- - - - - - 1 4 - - - - tscs
~~~~~~~__~~~~~~~~
------I~
1 4 - - - tpWE - - - - . I
-.,...."....,....,..~"...,....,....,...,....7"'""'l,....
WE
14--1---- tSD
DATA IN
- - - - + j I. .
DATA VALID
tHZWE
DATA OUT
DATA UNDEFINED
----.j
-->~
__
H_I_G_H_IM_PE_D_A_N_C_E_____________
--------------------------------------------
1730-8
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state_
Truth Table
WE
OE
H
X
X
HighZ
L
H
L
Data Out
Read Word
L
L
X
Data In
Write Word
L
H
H
HighZ
Deselect
CS
Input/Outputs
•
Mode
DeselectlPower-Down
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package 'fYpe
Operating
Range
25
CYM1730PZ-25C
PZ07
56-Pin ZIP Module
Commercial
30
CYM1730PZ-30C
PZ07
56-Pin ZIP Module
Commercial
35
CYM1730PZ-35C
PZ07
56-Pin ZIP Module
Commercial
Document #: 38-M-00049
8-53
CYM1821
CYPRESS
SEMICONDUCTOR
16K X 32 Static RAM Module
Features
Functional Description
• High-density 512-Kbit SRAM module
• High-speed CMOS SRAMs
- Access time of 12 ns
• Low active power
-4W(max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .50 in.
• Small PCB footprint
-1.0 sq. in.
• JEDEC-compatible pinout
• 2V data retention (L version)
• SIMM version socket-compatible with
CYM1831 and CYM1841
The CYM1821 is a high-performance
512-Kbit static RAM module organized as
16K words by 32 bits. This module is constructed from eight 16K x 4 SRAM SOJ
packages mounted on an epoxy laminate
board with pins. Four chip selects (CSl,
CSz, CS3, and CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
Writing to each byte is accomplished when
the appropriate chip selects (CSN) and
write enable (WE) inputs are both LOW.
Data on the input/output pins (I/Ox) is
written into the memory location specified
on the address pins (Ao through A13).
Logic Block Diagram
Ao -
Reading the device is accomplished by taking the chip selects (CSN) LOW, while
write enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified on the address pins
will appear on the data input/output pins
(I/Ox).
The data input/output pins stay in the~
impedance state when write enable (WE)
is LOW, or the appropriate chip selects are
HIGH.
Two pins (PDo and PDl) are used
to identify module memory density in
applications where alternate versions of
the JEDEC standard modules can be interchanged.
Pin Configuration
PDo - GND
PD1 - OPEN
A13
DE
ZIP
Top View
PDo
1/°0
1/°1
1/°2
1/°3
14
WE
10
12
14
16
18
20
22
24
26
28
30
32
Vee
A7
1/04 -1/07
1/00 -1/03
As
I/~~
CS1
1/05
1/°6
I/~
1/0 8-1/0 11
WE
NC
1/012 -1/015
CS1
CS2
1/016 - 1/019
1/020 - 1/023
1/024 - 1/027
1/028 -1/0 31
~a
34
36
38
40
42
GND
1/0 16
1/°17
1/018
1/°19
AlO
A11
A12
A13
1/0 20
1/°21
1/°22
1/023
GND
"CS3
"CS4
1821-1
44
46
48
50
52
54
56
58
60
62
64
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
PD1
1/°8
1/°9
1/°10
1/°11
Ao
A1
A2
1/°12
1/°13
1/014
1/°15
GND
NC
CS2
"CS4
NC
DE
1/0 24
1/°25
1/°26
1/°27
A3
~
A5
Vee
As
1/°28
1/029
1/°30
1/°31
1821-2
Selection Guide
1821-12
1821-15
1821-20
1821-25
1821-35
1821-45
Maximum Access Time (ns)
12
15
20
25
35
45
Maximum Operating Current (rnA)
960
960
720
720
720
720
Maximum Standby Current (rnA)
450
450
160
160
160
160
8-54
"i~PRR§
~,
CYM1821
SEMlCONDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Storage Temperature .................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ......................... - lOoC to +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - O.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Commercial
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
1821-20
1821-25
1821-35
1821-45
1821-12
1821-15
Parameter
Description
Min.
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltage
- 0.5
IIX
Input Load Current
Ioz
Output Leakage Current
los
Output Short Circuit Current!l]
Vee
Iec
Vee Operating Supply Current
Yce = Max., lOUT
CS;:;'VIL
ISBl
Automatic CS
Power-Down Current!2]
ISB2
Automatic CS
Power-Down Current!2]
Vee
Min.
Max.
Unit
2.4
2.4
0.4
V
0.4
V
2.2
Vee
V
0.8
- 0.5
0.8
V
GND;:;. VI;:;' Vee
-20
+20
-20
+20
J.tA
GND ;:;. Vo ;:;. Vee, Output Disabled
-20
+20
-20
+20
flA
-350
-350
rnA
960
720
rnA
Max. Vee, CS~ VIR,
Min. Duty Cycle = 100%
450
160
rnA
Max. Veo CSN ~ Vee - 0.3v,
VIN ~ Vee - O.3V or VIN ~ O.3V
160
160
rnA
= Max., VOUT = GND
= 0 rnA,
•
en
w
..J
~
C
o
::i
Capacitance[3]
Parameter
Description
Test Conditions
CINA
Input Capacitance (ADDR, OE, WE)
CINB
Input Capacitance (CS)
COUT
Output Capacitance
Notes:
1. ,Not more than 1 output should be shorted at one time. Duration ofthe
short circuit should not exceed 30 seconds.
2. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
TA = 25°C, f
Vee = 5.0V
3.
8-55
= 1 MHz,
Tested on a sample basis.
Max.
Unit
70
pF
35
pF
20
pF
CYM1821
AC Test Loads and Waveforms
481Q
481Q
OUTP~~ ~
,..
1J
~~~F
INCLUDING
JIG AND
SCOPE
OUTP~~ ~
1255Q
,..
-=
OUTPUT
1J
,.~~F
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
-
3.0V---90%
GND
-
1255Q
-
1821·3
(b)
1821-4
THEVENIN EQUIVALENT
167Q
o-------wv---o
1.73V
Switching Characteristics Over the Operating Rangel 4]
1821-12
Parameter
Description
1821-15
Max.
Min.
Min.
1821-20
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
10
10
10
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[S]
tHZCS
CS HIGH to High Z[S, 6]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
12
15
12
2
20
15
3
2
2
3
8
3
8
0
5
0
12
ns
8
8
ns
ns
8
ns
20
ns
0
15
ns
ns
3
2
8
ns
20
ns
WRITE CYCLE[7]
twc
Write Cycle Time
12
15
20
ns
tscs
CS LOW to Write End
10
12
15
ns
tAW
Address Set-Up to Write End
10
12
15
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
2
ns
tpWE
WE Pulse Width
10
12
15
ns
tSD
Data Set-Up to Write End
10
10
10
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
3
3
ns
tHzwE
WE LOW to High Z[6]
0
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZes is less than
tLZes for any given device. These parameters are guaranteed and not
100% tested.
7
6.
7.
8-56
0
7
0
7
ns
tHZes and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Thansition is measured ±500 m V from steadystate voltage.
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. Tne data inpui seiup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
~
g_ ' i l:~
l CYPRFSS
~,
CYM1821
SEMICONDUCTOR
Switching Characteristics Over the Operating Range (continued)[4)
1821-25
Parameter
Description
Min.
Max.
1821-35
Min.
1821-45
Max.
Min.
Max.
Unit
READ CYCLE
tRe
Read Cycle Time
tAA
Address to Data Valid
25
35
25
45
ns
45
35
ns
tOHA
Data Hold from Address Change
tAes
CS LOW to Data Valid
25
35
45
ns
tDOE
OE LOW to Data Valid
15
25
30
ns
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z
tLzes
CS LOW to Low Z[S)
tHzes
CS HIGH to High Z[S, 6)
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
3
3
3
3
3
3
ns
20
15
5
ns
10
20
10
15
10
0
0
25
ns
ns
20
ns
ns
0
45
35
ns
WRITE CYCLE[7)
twe
Write Cycle Time
25
35
45
ns
tses
CS LOW to Write End
20
25
35
ns
tAW
Address Set-Up to Write End
20
25
35
ns
tHA
Address Hold from Write End
2
2
2
ns
ns
tSA
Address Set-Up to Write Start
2
2
2
tpWE
WE Pulse Width
20
25
30
ns
tSD
Data Set-Up to Write End
13
15
20
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
3
5
5
ns
tHZWE
WE LOW to High Z[6)
0
7
0
10
15
0
ns
Data Retention Characteristics (L Version Only)
CYM1821
Parameter
Description
VDR
Vee for Retention Data
IeeDR
Data Retention Current
teDR[B)
Chip Deselect to Data Retention Time
tR[B)
Operation Recovery Time
IdB)
Input Leakage Current
Notes:
8. Guaranteed, not tested.
Test Conditions
Min.
Yce = 2.0V,
CS L Vee - 0.2V,
VIN L Vee - 0.2Vor
VINsO.2V
2
Max.
Unit
8
rnA
V
0
ns
tRd 9)
ns
10
9.
8-57
tRC = Read Cycle Time.
J.lA.
•
en
w
.J
:::)
C
o
::E
~
~~
=a!IE;; CYPRESS
~.F SEMICONDUCTOR
CYM1821
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VOR2:.2V
1821-5
Switching Waveforms
Read Cycle No.1[IO, 11]
~
'tiIoHA
ADDRESS-----....
DATA OUT
PREViOUS DATA VALiD
*-
IRe
1
1M
3XX><*================DA=I=A=V=A=L=ID===========
1821-6
Read Cycle No.2 (WE Controlled)[10, 12]
CS
tRC
~~
/'?
tACS
,{
~'"
I
tOOE
DATA OUT
HIGH IMPEDANCE
I/////V
tLZCS
1'-." " " " "
SUPPLY
CURRENT
HIGH
" IMPEDANCE
DATA VALID
1/
I+-tpo
I4---tpu
Vee _ _ _ _ _ _ _
tHZOE ----..
f4-tHZCS-
i4--tLZOE-
_
}
50%
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CS = VIL and OE= VIL.
~
50%
ICC
ISB
1821-7
12; Address valid prior to or coincident with CS transition Law.
8-58
--=-,~~PRESS
CYM1821
.
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled)[7]
~--------------------------twc--------------------------~
ADDRESS
~-----------------tscs--------------------~
~----------------------~w------------------~~---
____':I-_-:..-:..:.:.:.::_ts_A_-_-_-_-_-_-.:-_-_-""'...
+~~ ~----- tPWE ----~ _ - - - - - - - - - WE
_______________________
~
~_r-------tsD--------~
DATA IN
DATA VALID
tHZWE
=!
tLZWE -.j
I(~-----
HIGH IMPEDANCE
-.J)
DATA OUT __________D_A_I_A_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _
1821-8
Write Cycle No.2 (CS Controlled)[7, 13]
ADDRESS
. .-----tscs------~
----------~
---+---------------------~
,--------~-------
~~~~~~~~~~~~~~
en
w
~~~~~r7~~_r
:::)
C
WE
o
~_r-------tsD--------~
DATA IN
:E
DATA VALID
tHZWE ----I
DATA OUT
•
..J
~-----tpWE----~
--------------------------~I
HIGH IMPEDANCE
)>--------------
DATA UNDEFINED
1821-9
Note:
13. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
8-59
~
=..
~
~ICYPRESS
~,
CYM1821
SEMICONDUCTOR
Truth Table
CSN WE
OE
Inputs/Outputs
Mode
H
X
X
HighZ
DeselectlPower-Down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Ordering Information
Speed
12
15
20
25
35
45
Package
Name
Package
'JYpe
Operating
Range
CYM1821PM -12C
PMOI
64-Pin Plastic SIMM Module
Commercial
CYM1821PZ-12C
PZOI
64-Pin Plastic ZIP Module
Ordering Code
CYM1821PM -15C
PMOI
64-Pin Plastic SIMM Module
CYM1821PZ-15C
PZOI
64-Pin Plastic ZIP Module
CYM1821PM - 20C
PMOl
64-Pin Plastic SIMM Module
CYM1821LPM - 20C
PMOI
64-Pin Plastic SIMM Module
CYM1821PZ- 20C
PZOI
64-Pin Plastic ZIP Module
CYM1821LPZ- 20C
PZOI
64-Pin Plastic ZIP Module
CYM1821PM - 25C
PMOI
64-Pin Plastic SIMM Module
CYM1821LPM - 25C
PMOI
64-Pin Plastic SIMM Module
CYM1821PZ- 25C
PZOI
64-Pin Plastic ZIP Module
CYM1821LPZ- 25C
PZOl
64-Pin Plastic ZIP Module
CYM1821PM - 35C
PMOI
64-Pin Plastic SIMM Module
CYM1821LPM - 35C
PMOI
64-Pin Plastic SIMM Module
CYM1821PZ- 35C
PZOl
64-Pin Plastic ZIP Module
CYM1821LPZ- 35C
PZOl
64-Pin Plastic ZIP Module
CYM1821PM -45C
PMOI
64-Pin Plastic SIMM Module
CYM1821LPM -45C
PMOI
64-Pin Plastic SIMM Module
CYM1821PZ-45C
PZOI
64-Pin Plastic ZIP Module
CYM1821LPZ-45C
PZOI
64-Pin Plastic ZIP Module
Document #: 38-M-00015-D
8-60
Commercial
Commercial
Commercial
Commercial
Commercial
CYM1828
PRELIMINARY
32K X 32 Static RAM Module
Features
Functional Description
• High-density I-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 25 ns
• 66-pin, 1.I-inch-square PGA package
• Low active power
-3.3W (max.)
• Hermetic SMD technology
• TTL-compatible inputs and outputs
• Commercial and military temperature
ranges
The CYM1828 is a very high performance
i-megabit static RAM module organized
as 32K words by 32 bits. The module is constructed using four 32K x 8 static RAMs
mounted onto a multilayer ceramic substrate. Four chip selects (CSl, CS2, CS3,
CS4) are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use
of selects.
Data on the input/output pins (lIO) is written into the memory location specified on
the address pins (Ao through A14).
Reading the device is accomplished by taking chip selects LOW while write enable
remains HIGH. Under these conditions,
the contents of the memory location specified on the address pins will appear on the
data input/output pins.
The data input/output pins remain in a
high-impedance state when write enable is
LOW or the appropriate chip selects are
HIGH.
Writing to each byte is accom~shed when
the appr~ate chip selects (CS) and write
enable (WE) inputs are both Law.
Logic Block Diagram
Pin Configuration
Top View
Ao -
12
A14 --.1""5-----.
o
o
o
o
o
o
o
o
OE----,
WE1 _ _ _-+-+-1
1/°0-7
CS1 ----+-+-1
WE2 _ _ _-+-+-1
CS2 ----+-+--1
WE3 ----+-+-1
1/°8-15
1/°16-23
CS3
0
1/015
1/0240 Vee 0
1/0310
1/0s 0
CS2 0
1/014
1/0250
cs4 0
1/0 300
1/010 0
GND 0
1/0 13
1/0260
wr:.4 O
1/02s O
As 0
1/027 0
1/0 2S0
00£
A7
0
A3
0
Ao 0
o
NC 0
~
0
A1
0
0wr:.1
As
As
0
A2
0
Vee 01/07
As
CS1 01/06
1/0160
NC
1/0170 GNDO
1/0210
1/0180 1/01s O
1/0 200
A13 01/011 01/0 12
A14
o
NC
OA11
NC
NC
A10
NC
I
(J)
W
...I
;:)
o
o
A12
o
01/05
01/02 01/0 3 01/0 4
11
56
wr:.2
01/01
1828·1
45
34
1/0s 0
01/00 0
1/°24-31
23
22
33
0
0
44
M30
1/0 230
cs3 0
1/0220
55
66
C
0
:::E
1828·2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (rnA)
Commercial
Maximum Standby Current (rnA)
Commercial
1828-25
1828-30
1828-35
1828-45
1828-55
25
30
35
45
55
70
600
600
600
600
600
600
600
600
600
600
200
200
200
200
200
200
200
200
200
200
Military
Military
8-61
1828-70
-====,:~PRESS
PRELIMINARY
·
CYM1828
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................. Supply Voltage to Ground Potential ........
DC Voltage Applied to Outputs
in High Z State .........................
DC Input Voltage .......................
Operating Range
Range
65°C to +150°C
- O.sV to +7.0V
Commercial
Military
- 0.5V to +7.0V
- 0.5V to +7.0V
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
- 55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range
1828
Parameter
Description
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
Vee+ 0 .3
V
VIL
Input LOW Voltage
- 0.3
0.8
V
IIX
Input Load Current
-20
+20
ftA
-20
+20
ftA
600
rnA
GND.5. VI.5. Vee, Vee
V
2.4
Vee
= Max.
loz
Output Leakage Current
GND .5. Vo.5. Vee, Output Disabled
leCx32
Vee Operating Supply Current
by 32 Mode
Vee = Max., lOUT
CS.5. VIL
= 0 rnA,
leCx16
Vee Operating Supply Current
by 16 Mode
Vee = Max., lOUT
CS.5. VIL
= 0 rnA,
leCx8
Vee Operating Supply Current
by8Mode
Vee = Max., lOUT
CS.5. VIL
= 0 rnA,
ISBl
Automatic CS Power-Down
Currentl 1]
Max. Vee; CS2: Vm,
Min. Duty Cycle = 100%
200
rnA
ISB2
Automatic CS Power-Down
Current[l]
Max. Vee; CS 2: Vee - 0.2V,
VIN 2: Vee - O.2Vor VIN.5. 0.2V
100
rnA
L Version
400
rnA
360
L Version
230
rnA
240
L Version
145
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. A pull-up resistor to Vcc on the CS input is required to keep the device deselected during Vccpower-up, otherwise 1SB will exceed values
given.
2.
8-62
= 1 MHz,
Tested on a sample basis.
Max.
Unit
50
pF
20
pF
~
==:.. . ~
--=-,
PRELIMINARY
~jg CYPRESS
CYM1828
SEMICONDUCTOR
AC Test Loads and Waveforms
R1481Q
OUTP~~ ~
30 pF
I
INCLUDING
JIG AND
SCOPE
-
TI
R1481Q
R2
255Q
OUTP~~
5 pF
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
I
-
ALL INPUT PULSES
R2
255Q
1828-3
(b)
1828-4
THEVENIN EQUIVALENT
o----W3--o
1.73V
Switching Characteristics Over the Operating Rangel 3]
1828-25
Description
Parameter
Min.
Max.
1828-30
Min.
Max.
1828-35
Min.
Max.
Unit
35
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
25
30
35
ns
tDOE
OE LOW to Data Valid
15
17
20
ns
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5]
25
35
30
25
3
30
3
3
0
0
15
3
ns
ns
0
15
25
3
3
15
ns
15
ns
ns
25
ns
I
tn
W
..J
::l
Q
WRITE CYCLE[6]
twc
Write Cycle Time
25
30
35
ns
tscs
CS LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
20
25
25
ns
tSD
Data Set-Up to Write End
15
20
17
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z
0
0
0
tHZWE
WE LOW to High Z[5]
0
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance_
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ± 500 m V from steadystate voltage.
15
6.
8-63
0
20
0
ns
30
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
o
:E
~
•
i~PRR§
PRELIMINARY
. , SEMICONDUCTOR
CYM1828
Switching Characteristics Over the Operating Range (continued) [3]
1828-45
Parameter
Description
Min.
Max.
1828-55
Min.
1828-70
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tOOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[4]
45
55
45
3
3
45
30
0
25
CS HIGH to High Z[4, 5]
tHzes
WRITE CYCLE[6]
30
25
ns
70
ns
35
ns
ns
ns
0
3
3
70
3
55
25
0
ns
70
55
30
ns
30
ns
ns
3
30
twe
Write Cycle Time
45
55
70
ns
tscs
CS LOW to Write End
40
45
55
ns
tAW
Address Set-Up to Write End
40
45
55
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
30
35
45
ns
tSD
Data Set-Up to Write End
25
30
40
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z
0
0
0
tHZWE
WE LOW to High Z[5]
0
30
0
30
0
ns
30
ns
Data Retention Characteristics (L Version Only)
1828
Parameter
Description
Test Conditions
VDR
Vee for Retention Data
CS~
ICCOR3
Data Retention Current
tCDR[7]
Chip Deselect to Data Rt?tention Time
CS ~ Vee - 0.2Y,
VIN ~ Vee - 0.2Vor
VIN 5 0.2Y, VOR = 3.0V
tR[7]
Operation Recovery Time
Vee - 0.2V
Note:
7. Guaranteed, not tested.
8-64
Min.
Max.
Unit
320
ItA
2
V
0
ns
tRC
ns
-
=---.~
~.a CYPRESS
~F
SEMICONDUCTOR
PRELIMINARY
CYM1828
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR~2V
1828-5
Switching Waveforms
Read Cycle No. 1[8,9]
t
ADDRESS
~ IoHA~
- - -
DATA OUT
tRC
PREVIOUS DATA VALID
~I
~xxX)k================D=AT=A=V=A=L=ID===========
1828-6
Read Cycle No. 2[8, 10]
CS
tRC
/~
'K.
I
tACS
,{
~~
tDOE
HIGH IMPEDANCE
/////V
tL2CS
"-"""""
HIGH
IMPEDANCE
/
I---tpD
~ CC
I
Vce _______
SUPPLY
CURRENT
;:)
C
"
DATA VALID
tpu
W
.J
tHZOEI+-tHZCS -
i+--tL20E-
DATA OUT
(J)
_
}
50%
50%
ISB
1828-7
Notes:
8. WEN is HIGH for read cycle.
9. Device is continuously selected, CS = VIL and OE= VIL.
10. Address valid prior to or coincident with CS transition LOW.
8-65
o
:i
&;;~PRFSS
~_"
PRELIMINARY
CYM1828
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled)[6, 11]
~--------------------------twc--------------------------~
~-----------------tscs--------------------~
~----------------------~w------------------~~---
______~~_~~~~:::_ts_A_-_-_-_-_-_-_-_-_-~~~~~~-----tpwE------~,____________________
~~-------tsD--------~
DATA IN ----------------------------~
DATA VALID
tHZWE
=-!
tLZWE ----.j
HIGH IMPEDANCE
-J)
DATA I/O _______________D_A_TA__
UN_D_E_F_IN_E_D______________
'("----1828-8
Write Cycle No.2 (CS Controlled)[6, 11, 12]
ADDRESS
----------_01+----- tscs
-------;~
-----+----------------------~
,-------+----------
~-----tpwE-----~
~~-------tsD--------~
DATA IN
DATA VALID
tHZWE ------I
~__J)~'--H-I-G-H-IM--PE-D-A-N-C-E
_____________
.
DATA I/O _ __________________________________
DATA UNDEFINED
r
1828-9
Notes:
11. Data I/O will be high impedance if OE = VIH.
12. If CSN goes HIGH simultaneously with WEN HIGH, the output remains in a high-impedance state.
8-66
-
====----01: ~
;~
PRELIMINARY
- - - j; CYPRESS
JF
CYM1828
SEMICONDUCTOR
Truth Table
CSN
OE
WEN
H
X
X
HighZ
Input/Outputs
DeselectlPower-Down
Mode
L
L
H
Data Out
Read
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package
1Ype
Operating
Range
25
CYM1828HG- 25C
HGOl
66-Pin PGA Module
Commercial
30
CYM1828HG- 30C
HGOl
66-Pin PGA Module
Commercial
35
CYM1828HG- 35C
HGOl
66-Pin PGA Module
Commercial
CYM1828LHG-35C
HGOl
66-Pin PGA Module
CYM1828HG- 35MB
HGOl
66-Pin PGA Module
CYM1828LHG-35MB
HGOl
66-Pin PGA Module
CYM1828HG-45C
HGOl
66-Pin PGA Module
CYM1828LHG-45C
HGOl
66-Pin PGA Module
CYM1828HG-45MB
HGOl
66-Pin PGA Module
CYM1828LHG-45MB
HGOl
66-Pin PGA Module
CYM1828HG-55C
HGOl
66-Pin PGA Module
CYM1828LHG-55C
HGOl
66-Pin PGA Module
CYM1828HG-55MB
HGOl
66-Pin PGA Module
CYM1828LHG-55MB
HGOl
66-Pin PGA Module
CYM1828HG-70C
HGOl
66-Pin PGA Module
CYM1828LHG-70C
HGOl
66-Pin PGA Module
CYM1828HG-70MB
HGOl
66-Pin PGA Module
CYM1828LHG-70MB
HGOl
66-Pin PGA Module
45
55
70
Document #: 38- M -00042
8-67
Military
Commercial
Military
Military
Ien
Commercial
:l
C
Commercial
w
..J
o
::E
Military
CYM1831
CYPRESS
SEMICONDUCTOR
64K X 32 Static RAM Module
Features
Functional Description
• High-density 2-Mbit SRAM module
• High-speed CMOS SRAMs
- Access time of15 ns
• Low active power
- 5.3W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .50 in.
• Small PCB footprint
-1.2 sq. in.
• JEDEC-compatible pinout
The CYM1831 is a high-performance
2-Mbit static RAM module organized as
64K words by 32 bits. This module is constructed from eight 64Kx 4 SRAMs in SOJ
packages mounted on an epoxy laminate
board with pins. Four chip selects (CSt.
CSz, CS3, and CS4) are used to independently enable the four bytes. Reading or
writingcan be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
Writing to each byte is accomplished when
the appropriate chip selects (CSN) and
write enable (WE) inputs are both Law.
Data on the input/output pins (I/Ox) is
written into the memory location specified
on the address pins (Ao through AlS)'
Logic Block Diagram
Reading the device is accomplished by taking the chip selects (CSN) LOW and output enable (OE) LOW while write enable
(WE) remains HIGH. Under these conditions the contents of the memory location
specified on the address pins will appear on
the data input/output pins (I/Ox).
The data input/output pins stay in the~
impedance state when write enable (WE)
is LOW or the appropriate chip selects are
HIGH.
Two pins (PDo and PDl) are used to
identify module memory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
Pin Configuration ZIP/SIMM
Top View
Ao -
A15
--.,>'----r---------------.
PDo - OPEN
PD1 - GND
GND
PD1
1/°8
1/°9
1/°10
1/°11
PDo
1/°0
1/°1
1/02
1/°3
OE ___
16____~~--------------------~
WE ----r~+_--------------~
Vee
~
A7
As
1/04 -1/07
1/00 -1/03
A2
1/°12
1/°13
1/°14
1/°15
GND
I/~~
CS1
1/05
1/°6
1/07
1/0 8 -1/011
WE
1/012 - 1/015
CS2
1/016 - 1/019
1/020 -1/023
1/024 -1/027
1/028 -1/031
~2
~~
CS4
~a
NC
OE
GND
1/°16
1/°17
1/°18
1/°19
A10
An
A12
A13
1/°20
1/°21
1/°22
1/°23
GND
CS3
CS4
1831-1
1/024
1/°25
1/°26
1/027
A3
~
A5
Vee
As
1/°28
1/°29
1/°30
1/°31
1831-2
Selection Guide
1831-15
1831-20
1831-25
1831-30
1831-35
15
20
25
30
35
45
Ma.ximum Operating Current (nv\)
1120
960
720
720
720
720
Maximum Standby Current (rnA)
160
160
160
160
160
160
Maximum Access Time (ns)
8-68
1831-45
~
--~PRFSS
~.iF
CYM1831
SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. Ambient Temperature with
Power Applied ........................ Supply Voltage to Ground Potential ........
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . ..
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
65°C to +150°C
Operating Range
55°C to + 125°C
- O.5V to +7.0V
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
Commercial
- 0.5V to + 7.0V
Electrical Characteristics Over the Operating Range
1831-15
Parameter
Description
Test Conditions
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
2.4
1831-20
Min.
Max.
2.4
1831-25,30,35,45
Min.
Max.
Unit
VOH
Output HIGH Voltage Vee
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
2.2
Vee
2.2
Vee
2.2
Vee
V
VIL
Input LOW Voltage
- 0.5
0.8
- 0.5
0.8
- 0.5
0.8
V
-20
+20
-20
+20
-20
+20
f,tA
-20
+20
-20
+20
-20
+20
f,tA
IIX
Input Load Current
GND~ VI~
loz
Output Leakage
Current
GND~ Vo~
Vee,
Output Disabled
lee
Vee Operating
Supply Current
Yce
ISBl
Automatic CS PowerDown Current[1]
ISB2
Automatic CS PowerDown Currentl1]
= Max., lOUT = 0 rnA,
V
0.4
0.4
0.4
Vee
2.4
V
1120
960
720
rnA
Vee = Max., CSN ~ VIR,
Min. Duty Cycle = 100%
320
320
320
rnA
Vee = Max., CSN ~ Vee - 0.2V,
VIN ~ Vee - 0.2Vor VIN ~0.2V
160
160
160
rnA
CSN~ VIL
I
U)
W
..J
Capacitance[2]
:)
Parameter
Description
Test Conditions
CINA
Input Capacitance (Ao - A15, CS, WE, OE)
CINB
Input Capacitance (1/00 - 1/031)
COUT
Output Capacitance
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
80
pF
15
pF
15
pF
Notes:
1.
A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
2.
Tested on a sample basis.
AC Test Loads and Waveforms
R14810
R14810
ALL INPUT PULSES
OUTP~~ ~ OUTP~~ ~
'n~~~Fi 1
'n,.~~Fi 1
INCLUDING
JIG AND
SCOPE
-
R2
R2
2550
2550
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
-
GND
1831·3
1831·4
THEVENIN EQUIVALENT
1670
90%
-
(b)
OUTPUT ()--'W'V-----O
3.0V----
1.73V
8-69
C
o
:E
-
- ~
~= CYPRF.SS
..
CYM1831
~, SEMICONDUcrOR
Switching Characteristics Over the Operating Range[3]
1831-15
Parameter
Description
1831-20
1831-25
1831-30
1831-35
1831-45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
tOHA
Read Cycle Time
Address to Data Valid
Data Hold from
Address Change
15
20
25
15
3
CS LOW to Data Valid
tACS
OE LOW to Data Valid
tOOE
OE LOW to Low Z
tLZOE
OE LOW to High Z
tHZOE
CS LOW to Low ZL4J
tLZCS
CS HIGH to High ZL4,-'J
tHZCS
WRITE CYCLE[6]
3
3
15
8
20
10
0
3
0
3
0
3
45
30
ns
ns
ns
ns
ns
ns
0
20
3
15
ns
ns
ns
45
35
20
15
13
8
6
3
0
3
0
45
35
30
20
15
10
35
30
25
15
0
8
0
30
25
20
20
3
20
20
Write Cycle Time
CS LOW to Write End
Address Set-Up to
Write End
15
10
10
20
15
15
25
tscs
tAW
20
20
30
25
25
35
30
30
45
40
40
ns
ns
ns
tHA
Address Hold from
Write End
2
2
2
2
2
2
ns
tSA
Address Set-Up to
Write Start
2
2
2
2
2
2
ns
tpWE
WE Pulse Width
tSD
tHD
Data Set-Up to Write End
Data Hold from Write End
tLZWE
tHzWE
WE HIGH to Low Z
WE LOW to High ZL5J
10
8
2
3
0
15
12
2
3
0
20
15
2
3
0
25
15
2
3
0
25
20
2
3
0
30
20
2
3
0
ns
ns
ns
ns
ns
twc
7
10
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
5. tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
6.
7.
8.
13
15
20
20
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL and OE= VIL.
Switching Waveforms
Read Cycle No.
d 7,8]
}==
1=
ADDRESS -----......
DATA OlIT
to"A
PREVIOUS DATA VAUD
IRe
~
I
*-
3SSS*================DA=:r=A=V=A=L=ID===========
1831·5
8-70
· .~
~jJ CYPRESS
~,
CYM1831
SEMICONDUcrOR
Switching Waveforms
Read Cycle No. 2[7, 9]
CS
~-------------------------tRC----------------------~r----------------
~----------~cs----------~
QE-+----
HIGH
IMPEDANCE
DATA VALID
DATA OUT -~-------------------IIfo+~~
SUP~l~
tPut~ "..._---------------------tp-D=:'i-- ICC
___________~ 50%
50% ~ IS8
CURRENT
1831-6
Write Cycle No.1 (WE Controlled)[6]
~--------------------------twc--------------------------~
ADDRESS
~~~, ~~----------------tscs--------------------~~~~~~~~~~~~
~-I-------------------- tAW --------------------t-t4--_____IoI_I-_-:..-:..:.:.:.:.:_ts_A_-_-..:-_-_-_-_-_-..-I-!~~~~ ~----- tpWE ------~ _----""'------
I
WE
DATA IN
f3...I
DATA VALID
tL2WE;---' •
DATA OUT
:)
HIGH IMPEDANCE--(,-"'"_-_-_-_-_-_-_-_-_-_
DATA UNDEFINED
1831-7
Write Cycle No.2 (CS Controlled)[6, 10]
ADDRESS
__-+______~_-_-_-_-__:.._:.._:.._:..:.:.~~~-----tscs------~,---------+---------~-----
tPWE -------.t
~~~~~~~~~~~~~~~~
~~_r~~~_r~~~~
WE
~~-------tSD-------'~
DATA IN
DATA VALID
tHZWE--I
DATA OUT
---------------------------------------------.1
DATA UNDEFINED
HIGH IMPEDANCE
»--------------1-831_8
Note:
9.
Address valid prior to or coincident with CS transition LOW.
10. If CS goes HIGH simuitaneousiywith WE HIGH, the output remains
in a high-impedance state.
8-71
C
o
2
·
;~PRESS
~,
CYM1831
SEMICONDUCTOR
'fruth Table
CSN WE
OE
Inputs/Outputs
Mode
H
X
X
HighZ
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
DeselectlPower-Down
Ordering Information
Speed
15
20
25
30
35
45
Ordering Code
Package
Name
Package
lYPe
CYM1831PM -15C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN -15C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-15C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM -20C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN - 20C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-20C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM-25C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN - 25C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ- 25C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM-30C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN-30C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-30C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM - 35C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN - 35C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-35C
PZOI
64-Pin Plastic ZIP Module
CYM1831PM -45C
PMOI
64-Pin Plastic SIMM Module
CYM1831PN -45C
PNOI
64-Pin Plastic Angled SIMM Module
CYM1831PZ-45C
PZOI
64-Pin Plastic ZIP Module
Document #: 38-M-00018-D
8-72
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CYM1832
CYPRESS
SEMICONDUCTOR
64K X 32 Static RAM Module
Features
Functional Description
• High-density 2-Mbit SRAM module
• High-speed CMOS SRAMs
- Access time of 25 ns
• Low active power
- 5.4W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .5 in.
• Small PCB footprint
-1.0 sq. in.
The CYM1832 is a high-performance
2-Mbit static RAM module organized as
64K words by 32 bits. This module is constructed from eight 64Kx 4 SRAMs in SO]
packages mounted on an epoxy laminate
board with pins. Four chip selects "{CSl,
CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or on any combination of multiple bytes
through proper use of selects.
Writing to each byte is accomplished when
the chip select (CSN) and write enable
(WE) inputs are both LOW. Data on the
input/output pins (I/Ox) is written into the
memory location specified on the address
pins (An through AlS).
Reading the device is accomplished by taking the chip selects (CSN) LOW, while
write enable (WE) remains HIGH. Under
these conditions, the contents of the memory location specified on the address pins
will appear on the data input/output pins
(1I0 x).
The data input/output pins stay in the ~
impedance state when write enable (WE)
is LOW or the appropriate chip selects are
HIGH.
Pin Configuration
Logic Block Diagram
ZIP
Top View
Ao -
A 15
GND
1/°0
1/°1
1/°2
1/°3
16
WE
Vee
A7
1/00 - 1/03
1/04 - 1/07
CS"1
1/0 8 -1/011
1/012 -1/0 15
As
A9
1/04
1/05
1/°6
1/07
WE
Vee
CS1
CS"3
CS"2
GND
1/016 - 1/019
1/020 - 1/023
1/024 - 1/027
1/026 - 1/031
CS3
CS"4
1/°16
1/°17
1/018
1/°19
AlO
A11
A12
A 13
1/020
1/°21
1/°22
1/°23
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1/°8
1/°9
1/°10
1/°11
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Ao
A1
A2
1/°12
1/°13
1/°14
1/°15
1832-45
~
0
::E
~
A5
Vee
As
1/°28
1/0 29
1/°30
1/0 31
1832-55
Maximum Access Time (ns)
25
35
45
55
Maximum Operating Current (rnA)
980
980
980
980
Maximum Standby Current (rnA)
240
240
240
240
8-73
W
CS2
CS4
A14
A15
1/°24
1/°25
1/°26
1/°27
A3
Selection Guide
1832-35
t/)
..J
GND
M1832·2
1832-25
I
C
~~=
~,
CYM1832
SEMICONDUCTOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired.)
Range
Storage Temperature .................. - 45 ° C to + 125 ° C
Ambient Temperature with
Power Applied ......................... -10°C to +85°C
Supply Voltage to Ground Potential. . . . . . .. - O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State ......................... - 0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Commercial
Ambient
Temperature
Vee
O°Cto +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
CYM1832
Parameter
Description
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Min.
Max.
Unit
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.2
Vee
V
VIL
Input LOW Voltage[l]
- 0.5
0.8
V
Vee
Ilx
Input Load Current
GND~ VI~
loz
Output Leakage Current
GND ~ Va ~ Vee, Output Disabled
lee
Vee Operating Supply Current
Vee
ISBI
Automatic CS
Power-Down Currentl2]
Max. Vee, CSN L VIH,
Min. Duty Cycle = 100%
ISB2
Automatic CS
Power-Down Current[2]
Max. Vee, CSN L Vee - 0.2V,
VIN L Vee - 0.2V or VIN ~ 0.2V
Vee
2.4
V
0.4
V
-20
+20
/lA
-100
+100
flA
980
rnA
240
rnA
120
rnA
= Max., lOUT = 0 rnA, CSN ~ VIL
Capacitance[3]
Parameter
Description
CINA
Input Capacitance (Ax, WE)
CINB
Input Capacitance (CS)
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
Notes:
1. VIN(min.) = - 3.0V for pulse widths less than 20 ns.
2. A pull-up resistor to Vee on the CS input is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
3.
8-74
= 1 MHz,
Tested on a sample basis.
Max.
Unit
60
pF
25
pF
15
pF
.~
~iE CYPRESS
·
CYM1832
- , SEMICONDUCTOR
AC Test Loads and Waveforms
TI TI
R1 481 Q
OUTP~~
30 pF
R1 4810
R2
255Q
I
INCLUDING
JIG AND
SCOPE
-
OUTP~~
-
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
I
-
ALL INPUT PULSES
3.0V---90%
R2
255Q
GND
M1B32-3
(b)
M1B32-4
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics Over the Operating Rangd4]
1832-25
Parameter
Description
Min.
1832-35
Max.
Min.
Max.
1832-45
Min.
Max.
1832-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
25
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z[5]
2
tHZCS
CS HIGH to High Z[5, 6]
0
tpu
CS LOW to Power-Up
0
tpD
CS HIGH to Power-Down
35
25
3
45
35
15
45
35
3
0
0
25
0
30
45
ns
ns
30
0
0
35
55
0
ns
ns
3
3
25
ns
55
3
3
3
25
55
45
ns
ns
55
ns
WRITE CYCLE[7]
twc
Write Cycle Time
25
35
45
55
ns
tscs
CS LOW to Write End
20
30
40
45
ns
tAW
Address Set-Up to Write End
20
30
35
45
ns
tHA
Address Hold from Write End
2
2
5
5
ns
tSA
Address Set-Up to Write Start
2
3
5
5
ns
tpWE
WE Pulse Width
20
30
35
45
ns
tSD
Data Set-Up to Write End
15
20
25
35
ns
tHD
Data Hold from Write End
3
5
5
5
ns
tLZWE
WE HIGH to Low Z
3
3
3
3
tHZWE
WE LOW to High Z[6]
0
15
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
5_ At any given temperature and voltage condition, tHZCS is less than
tLzCS for any given device. These parameters are guaranteed and not
100% tested.
6. tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steady
state voltage.
7.
8-75
0
15
0
20
0
ns
30
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE Law. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
I
fa
....:::»
Q
o
::&
~
~~pRF.SS
SEMlCONDUcrOR
CYM1832
~,
Switching Waveforms
Read Cycle No. !lB,9]
}=
l=LHA
ADDRESS - - - - -....
DATA OUT
*-
lee
~
1
PREVIOUS DATA VALID 3XXX*================D=A=:I=A=V=A=L=ID============
M1832-5
Read Cycle No. 2[9, 10]
tRC
~,
/~
tACS
I--tHlCS-
tLZCS
HIGH IMpEDANCE
DATA OUT
/////v
",-",'\.:'\..'\..f'\.
/
~50%
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
-tpD-
I
tpu
"
DATA VALID
50%~
f - - - I CC
K - - I S8
M1832-6
Write Cycle No.1 (WE Controlled)[7]
~---------------twc --------------~
1+--------- tscs - - - - - - - - - - -....
1+--------------
~w ------------.~_ _ _~':..:.:.:.:.:.:.:._t_SA_-_-_-_:.:.:.:.~~~~~ l0iii1---- tPWE - - -..... _ - - - - - - - - - -
DATA IN
DATA VALID
j
tHZWE
-J)
DATA OUT _____________D_Al_A_U_N_D_E_F_IN_E_D______________
·tLZWE
HIGH IMPEDANCE
-.I
1(. . _____
M1832-7
Notes:
8. Device is continuously selected, CS
9_ WE is HIGH for read cycle.
= VIL.
10. Address valid prior to or coincident with CS transition LOW
8-76
~
~~PRESS
~_., SEMICONDUCIOR
CYM1832
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[7, 11]
ADDRESS
-----------.~------tscs------~
14---- tPWE
------~
~~~~~~~~~~~~~~~
,~~~~~~~~~
14-~----tSD----'~
DATA IN
DATA VALID
tHZWE ---../
DATA OUT
----------------------------------------~I
HIGH IMPEDANCE
DATA UNDEFINED
)>-------------------------M1832-8
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Table
CSN
Input/Outputs
WE
Mode
H
X
HighZ
DeselectlPower-Down
L
H
Data Out
Read
L
L
Data In
Write
Ien
w
.J
:::)
Q
Ordering Information
Speed
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
25
CYM1832PZ-25C
PZ02
60-Pin Plastic ZIP Module
Commercial
35
CYM1832PZ-35C
PZ02
60-Pin Plastic ZIP Module
Commercial
45
CYM1832PZ-45C
PZ02
60-Pin Plastic ZIP Module
Commercial
55
CYM1832PZ-55C
PZ02
60-Pin Plastic ZIP Module
Commercial
Document #: 38-M-00019-A
8-77
o
:E
CYM1836
128K X 32 Static RAM Module
Features
Functional Description
• High-density 4-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 20 ns
• Low active power
- 2.6W (max.) at 20 ns
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.57 in.
• JEDEC-compatible pinout
• Small PCB footprint
-0.78 sq. in.
• Available in SIMM, ZIP, or PLCC
format
The CYM1836 is a high-performance
4-megabit static RAM module organized
as 128K words by 32 bits. This module is
constructed from four 128Kx 8 SRAMs in
SOJ packages mounted on an epoxy laminate board~itl'!_"pins. Four chip selects
(CSl, CS2, CS3, CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
into the memory location specified on the
address pins (Ao through Al6).
Reading the device is accomplished by taking the ~ select (CS) LOW while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O).
The data input/output pins stay at the highimpedance state when write enable is
LOW or the appropriate chip selects are
HIGH.
Writing to each byte is accom..E!!shed when
the appr~ate chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the input/output pins (110) is written
Two pins (PDo and PDl) are used to identify module memory density in applications
where alternate versions of the JEDECstandard modules can be interchanged.
Logic Block Diagram
Pin Configurations
~
~ i ;I~ ~
ZIP/SIMM
Top View
PLCC
Top View
6
POo-OPEN
P0 1 -OPEN
<"'«aJ.,t «CD «1!l«'8
17
PDo
987654321~~~M6463~~
PO, (NC)
NC
A'2
A'3
A'4
A'5
A'6
CS1
10
11
12
13
14
15
16
60
59
GND
"C"S2
"C"S3
1/03
1/04
1/0 5
1/06
1/07
NC
4
1/08 - 1/0 15
"C"S,
1/00
I/O,
1/02
NC
GND
1/03'
1/030
1/029
1/028
1/027
1/0 26
GND
I/Oa
I/Og
1/0'0
"C"S4
Vee
1836-2
1/00
I/O,
1/02
1/0 3
Vee
A7
As
Ag
1/04
1/05
1/06
1/0 7
~
A'4
"C"S,
"C"S3
A'6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
1/0'6
1/0 17
1/0'8
I/O,g
AlO
A"
A'2
A'3
1/020
1/02'
1/022
1/023
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
GNO
64
GNO
GND
PO,
1/0 8
I/Og
1/0,0
I/O"
11
13
15
17
19
21
23
25
27
29
31
Ao
A,
A2
1/0'2
1/0'3
1/0'4
1/0'5
GND
"C"S4
33
35
37
39
41
NC
DE
1/0 24
1/0 25
1/0 26
1/0 27
A3
43
45
47
49
51
53
55
57
59
61
63
~
As
Vee
As
1/028
1/029
1/030
1/03'
1836-3
Selection Guide
1836-25
1836-30
1836-35
Maximum Access Time (ns)
25
30
35
45
Maximum Operating Current (rnA)
480
480
480
480
100
100
100
100
1836-20
/:%:;,
I
Maximum Standby Current (rnA)
100
Shaded area contains preliminary information.
8-78
1836-45
=-. ~~PRESS
CYM1836
~, SElviICONDUcrOR
Maximum Ratings
Operating Range
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. Ambient Temperature with
Power Applied .........................
Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . ..
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . ..
Range
55 ° C to + 125 ° C
Commercial
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
-10°C to +85°C
- O.5V to + 7.0V
- O.5V to + 7.0V
- 0.5V to + 7.0V
Electrical Characteristics Over the Operating Range
1836
Parameter
Description
Min.
Test Conditions
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Unit
Max.
V
2.4
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
0.4
V
VIH
Input HIGH Voltage
2.2
Vee
V
VIL
Input LOW Voltage
- 0.5
0.8
V
IIX
Input Load Current
GNDsVIsVee
-20
+20
!-tA
loz
Output Leakage Current
GND s Va s Veo Output Disabled
-20
+20
t-tA
lee
Vee Operating Supply Current
Vee
480
rnA
ISBl
Automatic CS Power-Down
Current[l]
Vee = Max., CS~ VIH,
Min. Duty Cycle = 100%
100
rnA
ISB2
Automatic CS Power-Down
Currentl 1]
Vee = Max., CS~ Vee - 0.2V,
VIN ~ Vee - 0.2V or VIN S 0.2V
28
rnA
Vee
= Max., lOUT = 0 rnA, CS S
VIL
UJ
W
Capacitance[2]
..J
Description
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = S.OV
Notes:
1. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
2.
= 1 MHz,
Max.
Unit
:l
40
pF
o
15
pF
R14810
Tested on a sample basis.
ALL INPUT PULSES
R14810
OUTP~~ ~ OUTP~~ ~
'n~.~:F1
'n,.~~F1 1
J 1
-
R2
R2
2550
2550
-
INCLUDING
JIG AND
SCOPE
90%
GND
1836-4
1836-5
THEVENIN EQUIVALENT
OUTPUT~
3.0V----
-
(b)
(a)
Equivalent to:
-
1.73V
8-79
C
:E
AC Test Loads and Waveforms
INCLUDING
JIG AND
SCOPE
I
~
~
~iiCYPRESS
CYM1836
~, SEMICONDUCTOR
Switching Characteristics Over the Operating Rangd31
J[836-2~Tl
Description
Parameter
I;~~n.' ,~t¢
1836-25
Min.
Max.
1836-30
Min.
Max.
1836-35
Min.
Max.
1836-45
Min.
Max.
Unit
READ CYCLE
~O
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold from Address
Change
tACS
CS LOW to Data Valid
tnoE
OE LOW to Data Valid
I,~'
tLZOE
OE LOW to Low Z
" 0
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4,51
;:~f
,2~l
1,4;1,0
",'
:~
30
25
25
5
5
,
45
35
30
5
ns
45
35
5
ns
ns
t,
20, "
25
30
35
45
ns
8
10
12
15
ns
"
,8~i:
.8",
."
I"
3
""f~O:
15
12
18
15
ns
ns
3
3
13
10
ns
0
0
11
10
3
3 •
I~
0
0
; {;;;'
ns
WRITE CYCLE[6]
twc
Write Cycle Time
tscs
CS LOW to Write End
20
.~
::.
25
30
35
45
ns
,;fj: '
15
18
20
25
ns
15
18
20
25
ns
'
..15
::.",';; ..
15
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tpWE
WE Pulse Width
\I • ;~sr~
15
18
20
25
ns
tso
Data Set-Up to Write End
10
i;'(i
10
13
15
20
ns
tHO
Data Hold from Write End
0"'•.
0
0
0
0
ns
tLZWE
WE HIGH to Low Z
0
0
0
0
0
ns
tHZWE
WE LOW to High Z[51
,(15
,i;
.... '".
,,9!.;.: ,...g,
0
10
0
15
0
15
0
18
ns
Shaded area contaInS prelImInary InformatIOn.
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOIJlOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
5. tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
6.
8-80
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
~
-
:~PRE&S
~;;
CYM1836
SEMICONDUCTOR
Switching Waveforms
Read Cycle No. 1[7,8]
F
~
ADDRESS------'liLHA
DATA OUT
PREVIOUS
IRe
1
DATA VAUD 3xxx>k================DA=r=A=V=A=L=ID===========
1836-6
Read Cycle No. 2[7,9]
CS
tRC
~,
~Z
tACS
*
~~
,
tDOE
I,1// / / /
HIGH IMPEDANCE
f4-- tLZOE
DATA OUT
tLZCS
tHZOE-tHZCS-
DATA VALID
V
""""""
"-
HIGH
IMPEDANCE
/
I
1836-7
Write Cycle No.1 (WE Controlled)[6]
~--------------------------twc--------------------------~
ADDRESS
~~~,~~----------------tscs--------------------~~~~-r~~~~~-r~
~----------------------~w------------------~~---
_ _-J.~":.:.:.:::::_t_SA_-_-_-_-_-_-_-_-_"""".,....
+~~ 1+------ tpWE -------.! _ - - - - - - - - - -
DATA IN
DATA OUT
DATA UNDEFINED
1836-8
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = VIL and OE= VIL.
9.
8-81
Address valid prior to or coincident with CS transition LOW.
I
-:,:n.~
CYM1836
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 10)
ADDRESS
-----------.. .------tscs----~~
----~----------------------~
,--------~--------....- - - - tpWE
-------.t
~~~~~~~~~~~~~~~
r~~-r~~-r~~~
~~------tSD-----~~
DATA IN
DATA VALID
tHZWE
DATA OUT
----.j
----------------------------------------~I
HIGH IMPEDANCE
DATA UNDEFINED
)>------------------------1836-9
Note:
10. IfCS goes HIGH simultaneously with WE HIGH, the outputremains
in a high-impedance state.
Truth Table
CSN
WE
OE
H
X
X
HighZ
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Input/Outputs
Mode
DeselectlPower-Down
Ordering Information
Speed
Ordering Code
(ns)
CYM1836PJ ~ zoe
20
"
'(~~836g~2Q<::.•,
Package
Name
leJ81 ?, I··~ead PEte M!,~e
l.~'PMO~::~il ~::Phi .S~~¥Mqaule'
CY'Ntt836PZ-~fX, '1JjjXPZOS1; :
25
30
35
45
94E:;ein'Z~:7Modul¢:fw
CYM1836PJ - 25C
J81
CYM1836PM - 25C
PM03
64-Pin SIMM Module
CYMI836PZ- 25C
PZ08
64-Pin ZIP Module
CYM1836PJ-30C
J81
CYM1836PM - 30C
PM03
68-Lead PLCC Module
68-Lead PLCC Module
Commercial'
';;'\.~
-"40=/1<$
.,
·ici.
.;".'
Commercial
Commercial
64-Pin SIMM Module
CYMI836PZ-30C
PZ08
64-Pin ZIP Module
CYM1836PM - 35C
PM03
64-Pin SIMM Module
CYMI836PZ-35C
PZ08
64-Pin ZIP Module
CYM1836PM -45C
PM03
64-Pin SIMM Module
CYMI836PZ-45C
PZ08
64-Pin ZIP Module
Shaded areas contain preliminary information
Document #:
Operating
Range
Package lYpe
38-1V!-00050-.LA~
8-82
Commercial
Commercial
CYM1838
PRELIMINARY
128K X 32 Static RAM Module
Features
Functional Description
• High-density 4-megabit SRAM
modnle
• High-speed CMOS SRAMs
- Access time of 25 ns
• 66-pin, 1.1-inch-square PGA package
• Low active power
-4.0W (max.)
• Hermetic SMD technology
• TTL-compatible inputs and outputs
• Commercial and military temperature
ranges
The CYM1838 is a very high performance
4-megabit static RAM module organized
as 128K words by 32 bits. The module is
constructed using four 128K x 8 static
RAMs mounted onto a mult~er ceramic
substrate. Four chip selects (CSl, CSz, CS3,
CS4) are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use
of selects.
Writing to each byte is accom.E!ished when
the appr~ate chip selects (CS) and write
enable (WE) inputs are both LOW
Logic Block Diagram
Data on the input/output pins (I/Ox) is
written into the memory location specified
on the address pins (Ao through A16).
Reading the device is accomplished by taking chip selects LOW while write enable
remains HIGH. Under these conditions,
the contents ofthe memory location specified on the address pins will appear on the
data input/output pins.
The data input/output pins remain in a
high-impedance state when write enable is
LOW or the appropriate chip selects are
HIGH.
Pin Configuration
PGA
Top View
12
23
34
45
56
Ao -A16~1'-7--"'"
OliOs 0
OE---...,
WE1 ----+-+-1
CS1-----1-r~--~
1/°0-7
1/°8-15
WE3 ----+-+~
CS3-----~~~
___
1/°16-23
1/°24-31
WE2 0
1/015
o 1/0 9 0 CS2 0 1/0 14
o 1/0 0 GND 0 1/013
o A13 01/011 0 1/0,2
o A14 o AlO ODE
o A,s OA11 o GND
o A16 o A'2 OWE,
o GND 0 Vee 01/07
10
0
01/00 0
CS,
o
I/O, 0
GND 0
0
1/0
2 01/0 3 0
10
1/024 0
Vee 0
1/0 3
1/025 0
CS40
1/0
300
1/0
290
1/0 260 WE4 0
270
As 0
1/0
A7
A3 0
0
Ao 0
GNDO ~
0
Al
As 0
As
0
A2
A9
WE30
0
Ien
1/02S0
W
.J
0
::l
C
0
0
:::E
1/0230
1/06
1/0 160 CS30
1/0220
1/0 5
1/0170 GNDO
1/0
1/0 4
I/O,sO 1/0'90
1/0 200
2,0
1838-1
11
22
33
44
55
66
1838-2
Selection Guide
Maximum Access Time (ns)
1838-25
1838-30
25
30
1838-35
35
Maximum Operating Current (rnA)
Commercial
720
720
720
Military
720
720
720
Maximum Standby Current (rnA)
Commercial
240
240
240
Military
240
240
240
8-83
~
~~PRESS
....
,
~EMICONDUcrOR
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................. Supply Voltage to Ground Potential ........
DC Voltage Applied to Outputs
in High Z State .... . . . . . . . . . . . . . . . . . . . ..
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . ..
CYM1838
Operating Range
Range
6SoC to + lS0°C
- O.5V to +7.0V
Commercial
Military
- O.5V to + 7.0V
- O.5V to + 7.0V
Ambient
Temperature
Vee
O°C to +70°C
SV ± 10%
- SsoC to + 12SoC
SV ± 10%
Electrical Characteristics Over the Operating Range
1838
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Min.
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Unit
Max.
2.4
Vee
V
0.4
V
6.0
V
- 0.3
0.8
V
-10
+10
-10
+10
!!A
!!A
2.2
VIL
Input LOW Voltage
IIX
Input Load Current
GND~ VI~ Vee,
loz
Output Leakage Current
GND ~ Vo ~ Vee, Output Disabled
leCx32
Vee Operating Supply Current
by 32 Mode
Yce
= Max., lOUT = 0 rnA,
720
rnA
leCx16
Vee Operating Supply Current
by 16 Mode
Yce
= Max., lOUT = 0 rnA,
480
rnA
Vee Operating Supply Current
by 8 Mode
Yce
= Max., lOUT = 0 rnA,
360
rnA
ISBl
Automatic CS Power-Down
Current[l]
Max. Vee; CS 2 VIH,
Min. Duty Cycle = 100%
240
rnA
ISB2
Automatic CS Power-Down
Currentl 1]
Max. Vee; CS 2 Vee - O.2V,
VIN 2 Vee - O.2V or VIN ~ 0.2V
40
rnA
leCx8
Vee
= Max.
CS~ VIL
CS~
CS~
VIL
VIL
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 2SoC, f
Vee = S.OV
Notes:
1. A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
AC Test Loads and Waveforms
R1481Q
30 pF
I
-
R2
255Q
OUTP~~
-
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
5n
I
-
pF
SO
pF
ALL INPUT PULSES
90%
R2
255Q
GND
1838-3
1838-4
THEVENIN EQUIVALENT
167Q
Unit
SO
3.0V----
(b)
~
Max.
Tested on a sample basis.
R1481Q
OUTP~~;n
INCLUDING
JIG AND
SCOPE
2.
= 1 MHz,
1.73V
8-84
~
~::z
~CYPRF.SS
~_"
PRELIMINARY
CYM1838
SEMICONDUCTOR
Switching Characteristics Over the Operating Range[3]
1838-25
Parameter
Description
Max.
Min.
1838-30
Min.
Max.
1838-35
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
35
30
25
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
25
30
35
ns
tOOE
OE LOW to Data Valid
12
13
15
ns
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z
20
ns
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5]
3
30
ns
0
15
10
ns
0
0
15
ns
20
18
ns
ns
0
0
0
35
3
3
ns
WRITE CYCLE[6]
twc
Write Cycle Time
25
30
35
ns
tscs
CS LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tpWE
WE Pulse Width
17
21
25
ns
tso
Data Set-Up to Write End
12
13
15
ns
tHO
Data Hold from Write End
2
2
2
ns
tLzWE
WE HIGH to Low Z
0
0
0
ns
tHzWE
WE LOW to High Z[5]
0
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
5. tHZCS and tHzWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
10
0
12
0
15
ns
I
tn
W
..J
::J
Q
o
6.
8-85
The internal write time of the memory is defined by the overlap of cs
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
:E
.w
~~PRF.SS
~'I SEMICONDUCTOR
PRELIMINARY
CYM1838.
Switching Waveforms
Read Cycle No. 1[7, sf
}=
ADDRESS ______'li~
DATA OUT
*-
~
1
~
PREVIOUS DATA VALID 3XXX*================DA=:r.=A=V=A=L=ID===========
1838-5
Read Cycle No. 2[7,9)
tRC
~,
}~
tACS
;f:
~~
I
tDOE
-tLZOE~
DATA OUT
HIGH IMPEDANCE
tLZCS
'// / / /
.
tHZOE ---+
-tHZCS-
DATA VALID
'",,"-
,'-:\
...
I
HIGH
" IMPEDANCE
/
1838-6
Write Cycle No.1 (WE Controlled)[6, 10)
~----------~--------------twc--------------------------~~
ADDRESS
~~~, ~~----~----------tscs--------------------~~~~~~~~~~~~
CS
~----------------------~w------------------~"---
___~~~~~~~:::_~_A_-_-_-_-_-_-_-_-_-~~~~~~-----tpWE------~,-_ _ _ _ _ _ _ _ __
DATA IN
DATA I/O
DATA VALID
tH_ZW_E_~J
Y~_ _ _ _ _ _ _ _ ___(~__ _ _ __
DATA UNDEFINED
_______________________
1838-7
Notes:
7.
8.
WEN is HIGH for read cycle.
Device is continuously selected, CS = VIL and OE= VIL.
9. Address valid prior to or coincident with CS transition LOW.
10. Data I/O will be high impedance if OE = VIH.
8-86
~
~~PRESS
~_,~ SEMICONDUcrOR
PRELIMINARY
CYM1838
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 10, 11]
ADDRESS
-----------.~------tscs------~
( + - - - - tPWE - - - - - - - - . j
~~~~~~~~~~~~~~~
,~~~~~~~~~
~~-----tSD------~~
DATA IN
DATA VALID
tHZWE---I
DATA OUT
----------------------.1
HIGH IMPEDANCE
DATA UNDEFINED
)>------------1838·8
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Table
CSN
OE
WEN
H
X
X
HighZ
Input/Output
DeselectlPower-Down
Mode
L
L
H
Data Out
Read
II
en
w
L
X
L
Data In
Write
L
H
H
HighZ
Deselect
..J
:::;)
C
o
Ordering Information
Speed
(ns)
25
30
35
Ordering Code
:Ii
Package
Name
Package 1YPe
Operating
Range
CYM1838HG- 25C
HGOI
66-Pin PGA Module
Commercial
CYM1838HG-25M
HGOI
66-Pin PGA Module
Military
CYM1838HG- 25MB
HGOI
66-Pin PGA Module
CYM1838HG-30C
HGOI
66-Pin PGA Module
Commercial
CYM1838HG-30M
HGOI
66-Pin PGA Module
Military
CYM1838HG-30MB
HGOl
66-Pin PGA Module
CYM1838HG-35C
HGOI
66-Pin PGA Module
Commercial
CYM1838HG-35M
HGOI
66-Pin PGA Module
Military
CYM1838HG-35MB
HGOI
66-Pin PGA Module
Document #: 38-M-00046-B
8-87
CYM1840
CYPRESS
SEMICONDUCTOR
256K X 32 Static RAM Module
Features
Functional Description
• High-density 8-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 20 ns
• Independent byte and word controls
• Low active power
-6.2W (max.)
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of .350 in.
• Small PCB footprint
-1.8 sq. in.
The CYM1840 is a high-performance
8-megabit static RAM module organized
as 256K words by 32 bits. This module is
constructed from eight 256Kx 4 SRAMs in
SOJ packages mounted on an epoxy laminate substrate with ~s. Four chip selects
(CSo, CS1, CS2, and CS3) are used to independentl~able the four bytes. Two write
enables (WEo and WE1) are used to independently write to either the upper or
lower 16-bit word of RAM. Reading or
writing can be executed on individual bytes
or on any combination of multiple bytes
through the proper use of selects and write
enables.
Writing to each byte is accom..£Yshed when
the appr~ate chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the input/output pins (I/Ox) is written
into the memory location specified on the
address pins (Ao through A17)'
Reading the device is accomplished by
taking the chi~lects (CS) LOW, while
write enables (WE) remain HIGH. Under
these conditions the contents of the memory location specified on the address pins
will appear on the data input/output pins
(I/O).
The data input/output pins stay in the~
impedance state when write enables (WE)
are LOW or the appropriate chip selects
are HIGH.
Pin Configuration
Logic Block Diagram
DIP
Top View
Ao -
A17
18
WEo
1/026 - 1/031
Selection Guide
1840-55
1840-20
1840-25
1840-30
1840-35
1840-45
20
25
30
35
45
55
Maximum Operating Current (rnA)
1120
1120
1120
1120
1120
1120
Maximum Standby Current (rnA)
320
320
320
320
320
320
Maximum Access Time (ns)
8-88
CYM1840
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
DC Input Voltage ....................... - 3.0V to +7.0V
Operating Range
Storage Temperature .................. - 65°C to +150°C
Ambient Temperature with
Power Applied (PD) ..................... -10°C to +85°C
DC Voltage Applied to Outputs
in High Z State ......................... - 0.5V to +7.0V
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
Range
Commercial
Electrical Characteristics Over the Operating Range
CYM1840
Parameter
Test Conditions
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
= Min., IOH = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Vee
Min.
Max.
Unit
2.4
V
0.4
V
V
VIR
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltage
- 0.5
0.8
V
Ilx
Input Load Current
GND~VI~Vee
-20
+20
!lA
-50
loz
Output Leakage Current
GND ~ Va ~ Vee, Output Disabled
Icc
Vee Operating Supply Current
Vee
ISBI
Automatic CS
Power-Down Current[l]
ISB2
Automatic CS
Power-Down Current[l]
+50
f.lA
1120
rnA
Max. Vee, CSx L VIR,
Min. Duty Cycle = 100%
320
rnA
Max. Vee, CSx L Vee - 0.3v,
VIN L Vee - O.3V or VIN ~ 0.3V
160
rnA
= Max., lOUT = 0 rnA, CSx ~ VIL
Capacitance[2]
Parameter
Test Conditions
Description
CINA
Input Capacitance, Address Pins
CINB
Input Capacitance, I/O Pins
COUT
Output Capacitance
TA = 25°C, f
Vee = 5.0V
Notes:
1. A pull-up resistor to V cc on the CS input is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
2.
8-89
= 1 MHz,
Max.
Unit
100
pF
30
pF
30
pF
Tested initially and after any design or process changes that may affect
these parameters.
•
UJ
W
..J
::l
C
o
:E
~
.~
'
CYM1840
: CYPRESS
SEMICONDUcrOR
AC Test Loads and Waveforms
ALL INPUT PULSES
OUTP~~ T I R
4810
1
OUTP~~ 5 f l R
4810
1
R2
R2
30 pFI
2550
5 pFI
2550
INCLUDING
JIG AND
SCOPE
-
-
INCLUDING
JIG AND
SCOPE
(a)
90%
GND
1840-3
(b)
1840-4
THEVENIN EQUIVALENT
Equivalent to:
OUTPUT
-
3.0V---
~
1.90V
Switching Characteristics Over the Operating Rangel3]
1840-20
Description
Parameter
Min.
Max.
1840-25
Min.
Max.
1840-30
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5]
tpu
CS LOW to Power-Up
tpD
CS HIGH to Power-Down
20
25
20
30
25
5
5
20
20
0
30
5
25
5
5
20
ns
ns
0
25
ns
ns
5
0
ns
ns
30
20
20
ns
30
ns
WRITE CYCLE[6]
twc
Write Cycle Time
20
25
30
ns
tscs
CS LOW to Write End
18
20
25
ns
tAW
Address Set-Up to Write End'
18
20
25
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
15
20
25
ns
tSD
Data Set-Up to Write End
13
15
15
ns
tHD
Data Hold from Write End
2
2
2
ns
tLZWE
WE HIGH to Low Z
0
0
0
tHZWE
WE LOW to High Z[5]
0
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of l.Sv, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrfIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. 'fransition is measured ±SOO m V from steadystate voltage.
6.
8-90
15
0
15
0
ns
15
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
==-.- .~
~~CYPRESS
CYM1840
~iF SEMICONDUcrOR
Switching Characteristics Over the Operating Rangel 3] (continued)
1840-35
Parameter
Description
Min.
Max.
1840-45
Min.
Max.
1840-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Output Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5]
tpu
CS LOW to Power-Up
tpo
CS HIGH to Power-Down
45
35
5
55
45
35
5
5
5
45
35
25
25
25
45
35
ns
ns
0
0
ns
ns
55
5
5
0
ns
55
ns
ns
55
ns
WRITE CYCLE[6]
twc
Write Cycle Time
35
45
55
ns
tscs
CS LOW to Write End
30
40
50
ns
ns
tAW
Address Set-Up to Write End
30
40
50
tRA
Address Hold from Write End
6
6
6
ns
tSA
Address Set-Up to Write Start
6
6
6
ns
tpWE
WE Pulse Width
25
30
40
ns
tso
Data Set-Up to Write End
25
30
35
ns
tHO
Data Hold from Write End
6
6
6
ns
tLzWE
WE HIGH to Low Z
0
0
0
ns
tJ)
tHZWE
WE LOW to High Z[5]
0
ns
W
.J
25
0
25
0
25
I
::l
C
Switching Waveforms
Read Cycle No.
d 7, 8]
F
l---L~
ADDRESS -----...
DATA OUT
PREVIOUS DATA VALID
o
:i
~c
~
1
3XZX:*:================D=AT=A=V=A=L=ID===========-_
1840-5
8-91
~PRFSS
_~CONDUcrOR
CYM1840.
Read Cycle No. 2(7, 8]
tRC
~~
/~
tACS
HIGH IMPEDANCE
1//////
DATA OUT
SUP~I~
-tpu
_____________
CURRENT
-tHZCS-
I
tLZCS
~
HIGH
"' IMPEDANCE
DATA VALID
1''''''''''''''
/
-tpD
~
50% .
50%
CC
I
ISB
1840-6
Write Cycle No.1 (WE Controlled)[6]
~----------------------.--.twc--------------------------~
~----------------tscs--------------------~
~--------------------- tAW - - - - - - - - - - - - - - - - - -....4 - - -
. . . 101---
______
........._-_-_-_-_-_-_-_t_SA
__
-_-:..-_-::.:.:.~=~~
tpWE
----.t _--------------
WE
DATA IN
DATA VALID
t
HZWE
=!
>
tLZWE~
HIGH IMPEDANCE
DATA OUT _ _ _ _ _ _ _ _D_A_TA_U_N_D_E_F_IN_E_D_ _ _ _ _ _ _ _
I(~----1840-7
Notes:
7. Device is continuously selected, CS = VIL.
8.
8-92
WE is HIGH for read cycle.
.....:::::II1II
~~PRESS
JF SEMICONDUcrOR
CYM1840
~
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 9]
ADDRESS
------~---.~------tscs------~
) 4 - - - tPWE ' - - - - - -.....
~~~~~~~~~~~~~~~~
~~~~~~~~~~~
14--!------- tSD - - - - - -.....1DATA IN
DATA VALID
tHZWE-..I
DATA OUT
----------~----------------------------~I
HIGH IMPEDANCE
)>--------------
DATA UNDEFINED
1840-8
Note:
9. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
Truth Table
CS
Input/Output
WE
Mode
H
X
HighZ
DeselectlPower-Down
L
H
Data Out
Read
L
L
Data In
Write
I
U)
W
...I
::l
Q
Ordering Information
Speed
Ordering Code
Package
Name
Package 1YPe
Operating
Range
20
CYM1840PD-20C
PD06
60-Pin DIP Module
Commercial
25
CYM1840PD- 25C
PD06
60-Pin DIP Module
Commercial
30
CYM1840PD-30C
PD06
60-Pin DIP Module
Commercial
35
CYM1840PD- 35C
PD06
60-Pin DIP Module
Commercial
45
CYM1840PD-45C
PD06
60-Pin DIP Module
Commercial
55
CYM1840PD-55C
PD06
60-Pin DIP Module
Commercial
Document #: 38-M-00040-B
8-93
o
:E
CYM1841
256K X 32 Static RAM Module
Features
Functional Description
• High-density 8-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 20 ns
• Low active power
- 5.3W (max.) at 25 ns
The CYM1841 is a high-performance
8-megabit static RAM module organized
as 256K words by 32 bits. This module is
constructed from eight 256Kx 4 SRAMs in
SOJ packages mounted on an epoxy laminate board~it~ins. Four chip selects
(CSl> CS2, CS3, CS4) are used to independently enable the four bytes. Reading or
writing can be executed on individual bytes
or any combination of multiple bytes
through proper use of selects.
Writing to each byte is accom...E!!shed when
the appr~ate chip select (CS) and write
enable (WE) inputs are both LOW. Data
on the input/output pins (I/O) is written
into the memory location specified on the
address pins (Ao through A17)'
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
- Max. height of 0.58 in.
• JEDEC-compatible pinout
• Available in ZIP, SIMM, and angled
SIMM footprint
• 72-pin SIMM version compatible with
1M x 32 (CYMI851)
Logic Block Diagram
Reading the device is accomplished by taking the ~ select (CS) LOW while write
enable (WE) remains HIGH. Under these
conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O).
The data input/output pins stay at the highimpedance state when write enable is
LOW or the appropriate chip selects are
HIGH.
Two pins (PDo and PDl) are used to identify module memory density in applications
where alternate versions of the JEDECstandard modules can be interchanged.
An-pin SIMM is offered for compatibility
with future density generations. This version is socket upgradable to the CYM1851.
Pin ConfigurationsZIP/SIMM
Top View
Ao -
A17
PO o POl P02 P03 -
--."----r--------------.
OE ___
18____~r_---------------------,
GNO
GNO
OPEN (72-pin only)
OPEN (72-pin only)
WE ---~~4_------------~
1/00 -1/03
CSl ---~-+~-~--------~-+~--~
I/Os -1/0 11
CS2 ---~-+~--~---------~-+~--~
CS3---~_+~-~---------~-+~--~
CS4-----------~--------------------~
1841-1
Selection Guide
1841-20
1841-25
1841-30
1841-35
1841-45
20
25
30
35
45
55
Maximum Operating Current (rnA)
1120
960
960
960
960
960
Maximum Standby Current (rnA)
480
480
480
480
480
480
Maximum Access Time (ns)
8-94
1841-55
~~
~jJ
CYM1841
CYPRESS
~, SEMICONDUCTOR
Pin Configurations (continued)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
SIMM
Top View
NC
PD3
PDo
1/°0
1/01
1/°2
1/°3
Vee
A7
A8
I/~:
1/05
1/°6
ILQz
WE
A14
CS 1
CS3
A16
GND
0
1/ 16
1/°17
1/°18
1/°19
AlO
An
A12
A 13
1/°20
1/021
1/°22
1/°23
GND
A19
NC
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Storage Temperature .................. Ambient Temperature with
Power Applied .........................
Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . ..
DC Input Voltage .......................
NC
PD2
GND
PD1
1/0 8
1/0 9
1/°10
1/011
Au
A1
A2
1/°12
1/°13
1/°14
1/°15
GND
A15
2
55°C to + 125°C
-10°C to +8S o C
- O.5V to + 7.0V
- O.SV to + 7.0V
- O.SV to +7.0V
Operating Range
Range
Commercial
Ambient
Temperature
Vee
O°C to +70°C
SV ± 10%
CS
CS4
A17
OE
1/°24
1/°25
1/°26
1/°27
A3
~
As
Vee
As
I
1/°28
1/°29
1/°30
1/°31
A18
NC
1841-3
en
w
...I
~
C
o
Electrical Characteristics Over the Operating Range
:E
1841-20
Parameter
Description
Test Conditions
Min.
Max.
1841-25,30,35,45,55
Max.
Unit
0.4
V
2.2
Vee
V
- 0.5
0.8
V
-16
+16
JlA
-10
+10
JlA
1120
960
rnA
Max. Vee, CS~ VIH,
Min. Duty Cycle = 100%
480
480
rnA
Max. Vee, CS ~ Vee - 0.2V,
VIN ~ Vee - 0.2V, or VIN ~ 0.2V
16
16
rnA
VOH
Output HIGH Voltage
Vee = Min., IOH = - 4.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VIH
Input HIGH Voltage
2.2
Vee
VIL
Input LOW Voltage
- 0.5
0.8
IIX
Input Load Current
GND~VI~Vee
-16
+16
loz
Output Leakage Current
GND ~ Va ~ V co Output Disabled
-10
+10
Icc
Vee Operating
Supply Current
Y.ce = Max., lOUT = 0 rnA,
CS~ VIL
ISBl
Automatic CS PowerDown Currentl1]
ISB2
Automatic CS PowerDown Currentl1]
8-95
2.4
Min.
2.4
0.4
V
~
•
~~
,
"
CYM1841
CYPRESS
SEMICONDUCTOR
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
Unit
70
pF
20
pF
Notes:
1.
A pull-up resistor to Vee on the CS input is required to keep the device deselected during Vee power-up, otherwise ISB will exceed values
given.
2.
Tested on a sample basis.
AC Test Loads and Waveforms
R1481Q
OUTP~~ ~
1
,.-~.~~F -
INCLUDING
JIG AND
SCOPE
-
R1481Q
R2
OUTP~~ ~
1
,.-,.~~F -
1255Q
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
ALL INPUT PULSES
-
3.0V---90%
R2
GND
1255Q
1841-4
(b)
1841·5
THEVENIN EQUIVALENT
OUTPUT~
1.73V
Switching Characteristics Over the Operating Range[3]
1841-20
Parameter
Description
Min.
Max.
1841-25
Min.
Max.
1841-30
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
20
25
tOHA
Output Hold from Address Change
tACS
CS LOW to Data Valid
20
tDOE
OE LOW to Data Valid
13
tLZOE
OE LOW to Low Z
tHzOE
OE HIGH to High Z
tLzes
CS LOW to Low Z[4]
tHzes
CS HIGH to High Z[4,5]
20
5
30
25
ns
25
30
ns
15
20
ns
5
0
5
10
15
10
20
ns
0
0
15
ns
30
ns
15
10
20
ns
ns
20
ns
WRITE CYCLE[6]
Write Cycle Time
20
25
30
ns
tscs
CS LOW to Write End
18
20
25
ns
tAW
Address Set-Up to Write End
18
20
25
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
15
20
25
ns
tSD
Data Set-Up to Write End
13
15
15
ns
twe
tHD
Data Hold from Write End
2
2
2
ns
tLzWE
WE HIGH to Low Z
0
0
0
ns
WE LOW to High Z[5]
o
8-96
15
o
15
o
15
ns
·
·~PRFSS
~,
CYM1841
SEMICONDUCTOR
Switching Characteristics Over the Operating Range (continued)[3]
1841-35
Parameter
Description
Min.
Max.
1841-45
Min.
Max.
1841-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tORA
Data Hold from Address Change
35
55
45
45
35
3
ns
55
5
5
ns
ns
tACS
CS LOW to Data Valid
35
45
55
ns
tDOE
OE LOW to Data Valid
25
30
35
ns
tLZOE
OE LOW to Low Z
tHZOE
OE LOW to High Z
tLzCS
CS LOW to Low Z[4]
tHzCS
CS HIGH to High Z[4,5]
20
tpD
CS HIGH to Power-Down
35
0
0
0
15
10
15
ns
15
ns
20
20
ns
45
55
ns
10
10
ns
WRITE CYCLE[6]
twc
Write Cycle Time
35
45
55
ns
tscs
CS LOW to Write End
30
40
50
ns
tAW
Address Set-Up to Write End
30
40
50
ns
tRA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
30
35
45
ns
tSD
Data Set-Up to Write End
20
25
35
ns
tHD
Data Hold from Write End
2
2
2
ns
tLzWE
WE HIGH to Low Z
0
0
0
ns
tHZWE
WE LOW to High Z[5]
0
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLzCS for any given device. These parameters are guaranteed and not
100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
6.
15
0
15
0
15
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
Switching Waveforms
Read Cycle No. 1[7, 8]
ADDRESS
tg
tRe
I
---~tOHA~
DATA OUT
*-
PREVIOUS DATA VALID ~XXX*================DA=T=A=V=A=L=ID===========
1841-6
8-97
I
UJ
W
...I
::l
C
o
:E
~PRRSS
CYM1841
.nEMICONDUcrOR
Switching Waveforms (continued)
Read Cycle No. 2[7, 9]
CS,
tRC
}~
~
tACS
OE
~
~~
tOOE
tHZOE ----
~tL.ZOE-
HIGH IMPEDANCE
DATA OUT
tL.ZCS
/////v
tHZCS-
"
DATA VALID
'-"""""
HIGH
IMPEDANCE
/
1841-7
Write Cycle No.1 (WE Controlled)[6]
~--------------------------twc--------------------------~~
~-----------------tscs--------------------~
~----------------------~w------------------~~---
14----- tSA --------~
14------ tpWE
---~
~-r-------tso--------~
DATA IN
--------------~
DATA VALID
tHZWE
::1
-J)
DATA OUT _______________
D_AT_A_U_N_D_E_F_IN_E_D______________
tLZWE
----.j
HIGH IMPEDANCE
1(_____
1841-8
Write Cycle No.2 (CS Controlled)[6, 10]
ADDRESS
---------1101+--- tscs ----.,-.
--~----------------~
,-----+-------
~~~~~~~~~~~~~~~~~~~---tpWE---~~~-7~~~~~~~~
WE
14-~-----tso--------~
DATA IN
DATA VALID
tHZWE
DATA OUT
DATA UNDEFINED
----..I
~~---H-IG-H--IM-P-E-D-A-N-C-E------------
------------------------------'
1841-9
Notes:
7.
8.
9.
WE is HIGH for read cycle.
Device is continuously selected, CS = VIL and OE= VIL.
Address valid prior to or coincident with CS transition LOW.
10. IfCS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
8-98
CYM1841
'fiuth Table
CS
WE
OE
Mode
Input/Output
H
X
X
HighZ
DeselectIPower-Down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Ordering Information
Speed
(ns)
20
25
30
35
45
55
Ordering Code
Package
Name
Package 1Ype
CYM1841PM - 20C
PM02
64-Pin Plastic SIMM Module
CYM1841P7-20C
PM04
72-Pin Plastic SIMM Module
64-Pin Plastic Angled SIMM Module
CYM1841PN-20C
PN02
CYM1841PZ-20C
PZ03
64-Pin Plastic ZIP Module
CYM1841PM - 25C
PM02
64-Pin Plastic SIMM Module
CYM1841P7 - 25C
PM04
72-Pin Plastic SIMM Module
CYM1841PN-25C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841PZ-25C
PZ03
64-Pin Plastic ZIP Module
CYM1841PM - 30C
PM02
64-Pin Plastic SIMM Module
CYM1841P7 - 30C
PM04
72-Pin Plastic SIMM Module
CYM1841PN-30C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841PZ-30C
PZ03
64-Pin Plastic ZIP Module
CYM1841PM-35C
PM02
64-Pin Plastic SIMM Module
CYM1841P7~ 35C
PM04
72-Pin Plastic SIMM Module
CYM1841PN - 35C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841PZ-35C
PZ03
64-Pin Plastic ZIP Module
CYM1841PM-45C
PM02
64-Pin Plastic SIMM Module
CYM1841P7 - 45C
PM04
72-Pin Plastic SIMM Module
CYM1841PN -45C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841PZ-45C
PZ03
64-Pin Plastic ZIP Module
CYM1841PM-55C
PM02
64-Pin Plastic SIMM Module
CYM1841P7 - 55C
PM04
72-Pin Plastic SIMM Module
CYM1841PN :....55C
PN02
64-Pin Plastic Angled SIMM Module
CYM1841PZ-55C
PZ03
64-Pin Plastic ZIP Module
Document #: 38- M -00031-C
8-99
Operating
Range
Commercial
Commercial
Commercial
I
Commercial
Commercial
Commercial
CYM18S1
PRELIMINARY
1,024K X 32 Static RAM Module
Features
Functional Description
• High-density 32-megabit SRAM
module
• High-speed CMOS SRAMs
- Access time of 25 ns
The CYM1851 is a high-performance
32-megabit static RAM module organized
as 1,024K words by 32 bits_ This module
is constructed from eight 1,024K x 4
SRAMs in SOJ packages mounted on an
epoxy laminate substrate_ Four chip selects are used to independently enable the
four bytes. Reading or writing can be executed on individual bytes or any combination of mUltiple bytes through proper
use of selects.
The CYM1851 is designed for use with
standard 72-pin SIMM sockets. The pin-
• Low active power
- 6.6W (max.) at 25 ns
• Downward compatible with CYM1821,
CYM1831, CYM1836, and CYM1841
JEDEC modules
• 72 pins
• Available in ZIP, SIMM, or angled
SIMMformat
Logic Block Diagram
out is downward compatible with the
64-pin JEDEC ZIP/SIMM module family
(CYM1821, CYM1831, CYM1836, and
CYM1841). Thus, a single motherboard
design can be used to accommodate
memory depth ranging from 16K words
(CYM1821)
to
1,024K
words
(CYM1851).
Presence detectpins(PDo - PD3) are used
to identify module memory density in applications where modules with alternate
word depths can be interchanged.
Pin Configuration
ZIP/SIMM
Top View
Ao - A19
DE
WE
PDo PDl PD2 PD3 -
20
GND
OPEN
GND
OPEN
1/00 -1/03
NC
PD3
PDo
1/0 0
1/01
1/0 2
1/0 3
1/0 4 -1/0 7
Vee
A7
ts~
CS3
CS4
I/~~
1/08 -1/0 11
1/0 5
1/0 6
110 12 - 1/0 15
I~
CS2
1/0 20
1/0 16 -1/019
-
1/0 23
A16
GND
1/0 16
1/0 17
1/°18
1/°19
Al0
All
A12
A13
1/°20
1/021
1/0 22
1/0 23
GND
A19
NC
CS3
1/0 28 - 1/0 31
1/0 24 - 1/027
CS4
1851-1
Ao
Al
A2
1/012
1/°13
1/°14
1/0 15
GND
A15
CS2
AS
CS1
NC
PD2
GND
PDl
1/°8
1/°9
1/°10
1/0 11
A17
DE
1/°24
1/°25
1/°26
1/0 27
As
~
Vee
As
1/028
1/0 29
1/0 30
1/0 31
A18
NC
1851-2
Selection Guide
1851-25
1851-30
25
30
35
Maximum Operating Current (rnA)
1200
1200
960
MaxImum Standby Current (rnA)
480
480
480
Maximum Access Time (ns)
8-100
1851-35
~
.
;~pR.ESS
PRELIMINARY
""""==11'' SEMICONDUCTOR
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. Ambient Temperature with
Power Applied .........................
Supply Voltage to Ground Potential. . . . . . ..
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . ..
CYM1851
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .. - O.5V to + 7.0V
Operating Range
55°C to + 125°C
Range
-10°C to +85°C
- 0.5V to + 7.0V
Commercial
Ambient
Temperature
Vee
O°C to +70°C
5V ± 10%
- 0.5V to + Vee
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
= Min., lOR = - 4.0 rnA
Vee = Min., IOL = 8.0 rnA
Max.
Unit
2.4
VOR
Output HIGH Voltage
VOL
Output LOW Voltage
VIR
Input HIGH Voltage
2.2
VIL
Input LOW Voltage
Ilx
Input Load Current
loz
Output Leakage Current
Icc
Vee Operating Supply Current
Yce
18Bl
Automatic CS Power-Down
Current[l]
18H2
Automatic CS Power-Down
Currentl 1]
Vee
V
0.4
V
Vee +
0.3
V
- 0.5
0.8
V
GND~VI~Vee
-10
+10
GND ~ Vo ~ Vee, Output Disabled
-10
+10
!!A
!!A
1200
rnA
Max. Vee, CS ~ VIR,
Min. Duty Cycle = 100%
480
rnA
Max. Vee, CS ~ Vee - 0.2V,
VIN ~ Vee - 0.2V, or VIN ~ O.2V
80
rnA
= Max., lOUT = 0 rnA,
CSN~ VIL
tJ)
Capacitance[2]
Parameter
Description
Test Conditions
CINA
Input Capacitance (WE, OE, Ao-19)
CINH
Input Capacitance (CS)
COUT
Output Capacitance
TA = 25°C, f
Vee = 5.0V
Notes:
1. A pull-up resistor to Vee on the CS input is required to keep the device deselected during V ccpower-up, otherwise ISB will exceed values
given.
2.
= 1 MHz,
Max.
Unit
W
..J
80
pF
C
20
pF
20
pF
R14810
==
Tested on a sample basis.
R14810
ALL INPUT PULSES
OUTP~~ ~ OUTP~~ ~
~~~F1 1
,.~~F1 1
R2
-
-
2550
,..
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
-
90%
GND
-
1851-3
(b)
1651-4
THEVENIN EQUIVALENT
1670
o------vv----o
3.0V----
R2
2550
,..
1.73V
8-101
~
o
AC Test Loads and Waveforms
INCLUDING
JIG AND
SCOPE
I
_
e;.~
-==-",
';;M
PRELIMINARY
CYPRESS
SEMICONDUcrOR
CYMI8S1
Switching Characteristics Over the Operating Range[3]
1851-25
Description
Parameter
Min.
Max.
1851-30
Min.
Max.
1851-35
Min.
Max.
Unit
35
ns
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
25
30
25
5
ns
35
30
5
ns
5
25
30
35
ns
15
20
25
ns
12
ns
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z
tLZCS
CS LOW to Low Z[4]
tHZCS
CS HIGH to High Z[4, 5]
12
12
12
ns
tpD
CSHIGH to Power-Down
25
30
35
ns
0
0
10
10
ns
0
12
12
10
ns
WRITE CYCLE[6]
twc
Write Cycle Time
25
30
35
ns
tscs
CS LOW to Write End
20
25
30
ns
tAW
Address Set-Up to Write End
20
25
30
ns
tRA
Address Hold from Write End
3
3
3
ns
tSA
Address Set-Up to Write Start
2
2
2
ns
tpWE
WE Pulse Width
20
25
30
ns
tSD
Data Set-Up to Write End
15
15
20
ns
tHO
Data Hold from Write End
2
2
2
ns
tLzWE
WE HIGH to Low Z
0
0
0
tHZWE
WE LOW to High Z[5]
0
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOrJIOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than
tLZCS for any given device. These parameters are guaranteed and not
100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test
Loads and Waveforms. Transition is measured ±500 m V from steadystate voltage.
6.
12
0
12
0
ns
12
ns
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal
that terminates the write.
Switching Waveforms
Read Cycle No. 1[7, 8]
ADDRESS
I§
tRe
----- c:= IoHA~
I
DATA OUT
PREVIOUS DATA VALID ~XXX*===============D=A=I_A-_-V_A-L=ID===========
1851-5
8-102
~
.
,
i~PRESS
-=:JF
PRELIMINARY
CYM1851
SEMICONDUCTOR
Switching Waveforms (continued)
Read Cycle No. 2[7, 9]
tRC
~~
/1{:
tACS
t
~K
tDOE
tHZOE-
~tHZCS-
i+--tLZOE-
HIGH IMPEDANCE
/////v
tLZCS
'"''''''"
DATA OUT
-tpu
r----- tpD
HIGH
IMPEDANCE
~ CC
I
VCC _ _ _ _ _ _ _
SUPPLY
CURRENT
"
/
DATA VALID
_
}
50%
50%
ISB
1851-6
Write Cycle No.1 (WE Controlled)[6]
~-------------------------twc--------------------------~
~-----------------tscs--------------------~
~--------------------- tAW
14-------- tSA -----~
Ien
-------------------.l+-1 4 - - - tpWE --------..I
w
.J
~
Q
o
14-~----tSD----~~
DATA IN
--------------~
:E
DATA VALID
t
HZWE
=1
.-J)
DATA OUT _ _ _ _ _ _ _ _D_A_TA_U_ND_E_F_IN_E_D_ _ _ _ _ _ _
tLZWE
----I
HIGH IMPEDANCE
I(~--------1851-7
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = VIL, and OE= VIL.
9.
8-103
Address valid prior to or coincident with CS transition Law.
&!CYPRK§
~
PRELIMINARY
CYM1851
SEMICONDUCTOR
Switching Waveforms (continued)
Write Cycle No.2 (CS Controlled)[6, 10]
ADDRESS
-----------.~------tscs------~
----~----------------------~
~--------+---------
~~~~~~~~~~~~~~~~~----tpWE------~~~~~~~~~~~~
WE
DATA IN
DATA VALID
___
E~
_ _____________________________________tH_ZW
~I
DATA OUT
HIGH IMPEDANCE
)>--------------------------
DATA UNDEFINED
1851-8
Note:
10. If CS goes HIGH simultaneously with WE HIGH, the output remains
in a high-impedance state.
'fiuth Table
CS
WE
OE
H
X
X
HighZ
DeselectlPower-Down
L
H
L
Data Out
Read
L
L
X
Data In
Write
L
H
H
HighZ
Deselect
Inputs/Output
Mode
Ordering Information
Speed
(ns)
25
30
35
Ordering Code
Package
'fYpe
CYM1851PM -25C
PM04
72-Pin Plastic SIMM Module
CYM1851PN-25C
PN04
72-Pin Plastic Angled SIMM Module
CYM1851PZ- 25C
PZ09
72-Pin Plastic ZIP Module
CYM1851PM - 30C
PM04
72-Pin Plastic SIMM Module
CYM1851PN-30C
PN04
72-Pin Plastic Angled SIMM Module
CYM1851PZ- 30C
PZ09
72-Pin Plastic ZIP Module
CYM1851PM - 35C
PM04
72-Pin Plastic SIMM Module
CYM1851PN - 35C
PN04
72-Pin Plastic Angled SIMM Module
CYM1851PZ-35C
PZ09
72-Pin Plastic ZIP Module
Package 'fYpe
Document #: 38- M -00052
8-104
Operating
Range
Commercial
Commercial
Commercial
CYM4208
CYM4209
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Cascadable 64K X 9 FIFO
Cascadable 128K X 9 FIFO
Features
Functional Description
• 64K x 9 FIFO buffer memory (4208)
or 128K x 9 FIFO buffer memory
(4209)
• Asynchronous read/write
• High-speed, 28.5-MHz read/write
• Pin-compatible with standard, 28-pin
monolithic FIFOs
• Low operating power
-Icc (max.) = 640 rnA (commercial)
• 600-mil DIP package
• Empty, Full flags
• Small PCB footprint
- 0.88 sq. in.
• Expandable in depth and width
The CYM4208 is a first-in first-out (FIFO)
memory module that is 64K words by 9 bits
wide. The CYM4209 is 128K words by 9
bits wide. Each is offered in a 600-mil-wide
DIP package. Each FIFO memory is organized such that the data is read in the same
sequential order that it was written. Full
and Empty flags are provided to prevent
overrun and underrun. Three additional
pins are also provided to facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one device to another in
parallel, thus eliminating the serial addi-
Logic Block Diagram
W
DO-8
Pin Configuration
xo
-------""T""--I
--------1
tion of propagation delays so that throughput is not reduced. Data is steered in a similarmanner.
The read and write operations may be
asynchronous; each can occur at a rate of
28.5 MHz. The write operation occurs
when the write (Wl signal is LOW. Read
occurs when read (R) goes LOW. The nine
data outputs go to the high-impedance
state when R is HIGH.
In the depth expansion configuration the
(XO) pin provides the expansion out information that is used to tell the next FIFO
that it will be activated.
R
DIP
Top View
00-8
Vee
VII
Vee
08
03
02
04
I
05
06
07
01
00
UJ
IT
XI
MR
FF
EF
00
XO
01
02
03
07
06
05
04
08
C
0
::E
R
GNO
4208-2
~ ---------~
4208-1
Selection Guide
4208-25
4209-25
4208-30
4209-30
4208-40
4209-40
20
Frequency (MHz)
28.5
25
Access Time (ns)
25
30
40
640
640
640
720
720
Maximum Operating Current (rnA)
I Commercial
I Military
8-105
W
..J
:::»
dL;~~
~,
CYM4208
CYM4209
PRELIMINARY
SEMICONDUCTOR
Maximum Ratings'
(Above which the usefullife may be impaired. For user guidelines,
not tested.)
Storage Temperature .................. Ambient Temperature with
Power Applied ....................... Supply Voltage to Ground Potential
(Pm 28 to Pin 14) .......................
DC Voltage Applied to Outputs
in High Z State .........................
65°C to + 150°C
DC Input Voltage ....................... - 0.5V to +7.0V
Operating Range
Ambient
Temperature
O°C to +70°C
Vee
5V ± 10%
Industrial
- 40°C to +85°C
5V ± 10%
Military[lj
- 55°C to + 125°C
5V ± 10%
Range
Commercial
55°C to + 125°C
- 0.5V to +7.0V
- 0.5V to +7.0V
Electrical Characteristics Over the Operating Range
4208
4209
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = - 2.0 rnA
VOL
Output LOW Voltage
Vee = Min., IOL = 8.0 rnA
VJHl:lJ
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Current
loz
Output Leakage Current
R~ VIH, GND.s Vo.s Vee
lee
Operating Current
Vee = Max., lOUT = 0 rnA,
{MAX, Outputs Open
Power-Down Current
Units
V
0.4
V
Com'l
2.0
Vee
V
MillInd
2.2
Vee
V
- 0.5
0.8
V
-10
+10
-10
+10
JAA
JAA
Com'l
640
rnA
MillInd
720
All Inputs = VIH Min., Vee = Max.,
lOUT = 0 rnA
Com'l
100
MillInd
120
All Inputs, Vee - 0.2.s VIN .s 0.2,
Vee = Max., lOUT = 0, {= 0
Com'l
80
MillInd
100
{MAX,
ISB2
Max.
2.4
GND.s VIN.s Vee
Standby Current
ISB!
Min.
rnA
rnA
Capacitance
Parameters
Description
qN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, {= 1 MHz,
Vee = 4.5V
Notes:
1. TA is the "instant on" case temperature.
2.
Max.
Units
30
pF
30
pF
XI must use CMOS levels with VIH ~ 3.5V (CYM4209 only).
AC Test Loads and Waveforms
R1500Q
R1500Q
OUTP~~ ~
1
In~~:F
INCLUDING -
JIG AND
SCOPE
-
R2
OUTP~~ ~
1333Q
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
.n. ~:F1
ALL INPUT PULSES
3.0V---R2
GND
1333Q
-
-
(b)
4208-3
THEVENIN EQUIVALENT
200Q
2V
o-----wv---o
8-106
4208-4
.-~~
--==-,
_
CYM4208
CYM4209
PRELIMINARY
..IE CYPRESS
SEMICONDUCTOR
Switching Characteristics Over the Operating Rangel3, 4, 5]
Spec.-25
Description
Parameters
Min.
Max.
Spec.-30
Min.
Max.
40
Spec.-4O
Min.
Max.
Units
ns
tRC
Read Cycle Time
tA
Access Time
tRR
Read Recovery Time
10
10
10
ns
tpR
Read Pulse Width
25
30
40
ns
tLzR
Read LOW to Low Z
3
3
3
ns
tDVR
Read HIGH to Data Valid
3
3
3
tHZR
Read HIGH to High Z
twc
Write Cycle Time
35
40
50
ns
tpw
Write Pulse Width
25
30
40
ns
tHWz
Write HIGH to Low Z
10
10
10
ns
tWR
Write Recovery Time
10
10
10
ns
tSD
Data Set-Up Time
18
18
20
ns
tHD
Data Hold Time
0
0
0
ns
tMRSC
MR Cycle Time
35
40
50
ns
tpMR
MR Pulse Width
25
30
40
ns
tRMR
MR Recovery Time
10
10
10
ns
ns
35
25
50
30
40
20
18
ns
ns
25
ns
I
tRPW
Read HIGH to MR HIGH
25
30
40
twpw
Write HIGH to MR HIGH
25
30
40
tEFL
MRtoEFLOW
35
40
50
ns
tFFH
MR to FF HIGH
35
40
50
ns
W
.J
tREF
Read LOW to EF LOW
25
30
40
ns
C
tRFF
Read HIGH to FF HIGH
25
30
40
ns
Write HIGH to EF HIGH
25
30
40
ns
tWFF
Write LOW to FF LOW
25
30
40
ns
tRAE
Effective Read from Write HIGH
25
30
40
ns
tRPE
Effective Read Pulse Width Mter EF HIGH
tWAF
Effective Write from Read HIGH
tWPF
Effective Write Pulse Width Mer FF HIGH
tWEF
25
30
25
30
tXOL
Expansion Out LOW Delay from Clock
25
tXOH
Expansion Out HIGH Delay from Clock
25
30
4.
S.
8-107
40
ns
40
ns
40
ns
ns
40
30
Notes:
3. Test conditions assume signal transition time of S ns or less, timing reference levels of l.Sv, and output loading ofthe specified IOrJIOH and
30-pF load capacitance, as in part (a) of AC Test Loads and Waveforms, unless otherwise specified.
ns
40
30
25
ns
tHZR transition is measured at +SOO mV from VOL and -SOO mV
from VOH. tOVR transition is measured at the l.SV level. tHWZ and
tLZR transition is measured at ±100 mV from the steady state.
tHZR and tOVR use capacitance loading as in part (b) of AC Test Loads
and Waveforms.
C/)
::l
o
:E
~PR&SS
_Ts~CONDUcrOR
PRELIMINARY
CYM4208
CYM4209
Switching Waveforms
Aynchronous Read and Write Timing Diagram
00
-as
DATA VALID
______-..J/
Do - Ds
------------~~_______________ ~------------~(~·_____D_A_JA__VA_L_ID____~»----4208-5
Last Write to First Read Full Flag Timing Diagram
LAST WRITE
FIRST READ
FIRST WRITE
--------+-.. .
4208-6
Last Read to First Write Empty Flag Timing Diagram
LAST READ
w
FIRST WRITE
.--------+. . .
ADDITIONAL
READS
FIRST READ
DATA OUT
4208-7
8-108
~
--.
;~PRESS
~.F
PRELIMINARY
CYM4208
CYM4209
SEMICONDUCTOR
Switching Waveforms (continued)
Master Reset Timing Diagram
1 4 - - - - - - tMRscl6] ----...,..------;.1
R,W I7]
EF
4208-8
Empty Flag and Read Bubble-Through Mode Timing Diagram
II
CJ)
W
..J
::)
4208-9
C
o
::E
Full Flag and Write Bubble-Through Mode Timing Diagram
w
DATA IN
,,=1 ___-
DATA OUT
---- 0)
N+k+1
N+k+2
N
Systems asserts DS,
Cntrlr accepts DATA
System asserts DS
N+k (k~ 1)
Cntrlr FIFO goes empty
Cntrlr asserts BACK,
Cntrlr accepts DATA
System asserts AS
MBus,
DS Gnded
Cntrlr FIFO goes empty
Cntrlr asserts BACK
Cntrlr accepts DATA
N
N+k (k > 0)
N+k+1
N
N+k(k>O)
N+k+1
MBusMode
Data Strobe is permanently asserted in MBus mode. The controller operates as if it were in Early Data Strobe mode. The system
asserts Address Strobe in cycle O. The FIFO goes empty in cycle
k. If the FIFO is already empty, k is O. The controller asserts Bus
Acknowledge and accepts the data in the next cycle (k + 1).
Read Operating Modes
The module offers several programmable options to control the
data transfer during memory-read operations. Wait states may be
inserted to allow additional propagation delay through the EDC
path. Error correction can be disabled for diagnostic purposes.
As in write operations, Data Strobe may be used to regulate
transfers over the system interface. Finally, Bus Acknowledges
may be programmed to occur one clock early or in real time with
respect to the corresponding data transfer. The timing of the Bus
Acknowledges is shown in Figure 1.
I
~
NORMAL
BACK
EARLY
BACK
I
DATA
M7232- 2
Figure 1. Early and Normal Bus Acknowledge Modes for Reads
8-120
~
'jg CYPRESS
I·~
,
SEMICONDUCTOR
PRELIMINARY
Read Early BACK Mode
The Read Early BACK data transfer is triggered by the assertion
of Data Strobe and closure of the snoop window (whichever occurs last) in cycle N. Data Strobe, once asserted, must remain asserted throughout the transaction. When read data is about to become available, BACK[1] is asserted (cycle N + k). Read data is
supplied to the bus in cycle N + k + 1.
Read Real-Time BACK Mode
The Read Real-Time BACK Mode begins when both Data Strobe
is asserted and the snoop window is closed (cycle N). The controller responds with data and the corresponding Bus Acknowledge in cycle N + k + 2.
Wait States
The controller module may be programmed to insert wait states
in the data path. This guarantees extra data set-up time when using error correction in system environments with fast bus clocks.
The controller delays the Bus Acknowledges accordingly. Wait
states may be inserted in either early or real-time Bus Acknowledge systems.
Acknowledge on Burst Reads
Read burst acknowledges will not generally be contiguous. The
assertion of the acknowledge on long bursts (above 16 bytes) will
be interrupted as more data is fetched from adjacent 128-bit
DRAM pages. During a burst pause, the acknowledge is deasserted and then three-stated one-half clock later.
Bus Acknowledges in Transformed Transactions
When a read is transformed, the operation internal to the controller becomes a write. Bus Acknowledge becomes an input and
is used as a strobe to clock the data into the reflective FIFO on
each data transfer. The controller will treat the strobe derived
from the incoming bus acknowledge as an early strobe when programmed in the early bus acknowledge mode. Otherwise the controller assumes that the data is aligned with the corresponding
strobe derived from the incoming bus acknowledge.
When a write is transformed, the operation converts to a read. In
this case, the controller behaves according to the invoked read
mode. Transformed operations use a preprogrammed default
burst length to specify their burst duration.
Bus Acknowledge Timing Characteristics
The Bus Acknowledge control signals are bidirectional and may
be driven by the controller or another device on the system bus.
Therefore there are times when no device will be driving this signal line. At high bus speeds, pull-ups may not be sufficient to
guarantee that the Bus Acknowledge line will revert in a sufficiently short time to the de asserted state after the controller has
ceased driving the line. To guarantee the state of the BACK signallines at the end of a transaction, the controller first drives the
outputs HIGH (de asserted) in the first half of the clock cycle in
which Bus Acknowledge is to be deasserted and then three-states
these outputs in the second half of this clock cycle. To insure that
the Bus Acknowledge signal lines remain in the deasserted state
when no device is driving them for long periods, pull-ups should
be employed. At the beginning of a transaction cycle, Bus Acknowledge remains three-stated until it is to be asserted. Thus in
the first acknowledge cycle of a transaction, BACK becomes driven and asserted at the same time. BACK continues to be driven
until the end of the transaction cycle and terminates as described
above.
Burst Last
Any read or write burst transaction may be terminated prematurely with the assertion of BLST. BLST must be asserted during
the clock cycle in which the last piece of data is transferred. Systems that require the data bus to go three-state in the next cycle
must also deassert Data Strobe (DS) when asserting BLST. Burst
last may not be used in Early Back mode or to prematurely terminate a transformed operation.
Inhibits and Snoop Window
Certain constraints apply to the system's assertion of inhibits and
the closing of the snoop window.
The inhibit signal must not be asserted until at least two clocks
after the address phase (i.e., if AS is asserted in bus clock N, inhibit may not be asserted until N + 2 or later).
Mode
Read Action
Read Cycle
Early BACK no wait states
System asserts DS and
closes SNW by cycle N
N
Cntrlr asserts BACK
N+k (k2: 2)
Cntrlr supplies data
N+k+1
System asserts DS and
closes SNW by cycle N
N
Cntrlr asserts BACK
N + k + 1 (k2:2)
Real Time BACK no wait states
Real Time BACK with wait states
Cntrlr supplies data
N+k+2
System asserts DS and
closes SNW by cycle N
N
Cntrlr asserts BACK
and supplies data
N + k (k 2: 2)
System asserts DS and
closes SNW by cycle N
N
Cntrlr asserts BACK
and supplies data
N + k + 1 (k 2: 2)
8-121
•
tJ)
W
.J
~
C
o
::E
Table 2. Read Bus Acknowledge Modes
Early BACK with wait states
CYM7232
CYM7264
~
;~PRESS
Rr
,
PRELIMINARY
CYM7232
CYM7264
SEMICONDUCTOR
Inhibits and Snoop Window (continued)
There must be a minimum of one bus clock cycle between the
close of a transaction's snoop window and the address strobe of
the next transaction (i.e., if the snoop window is deasserted on
the system bus during bus clock N, the next transaction's address
strobe must not be asserted until N + 2). This scenario would
most likely occur when the first transaction is inhibited but not
transformed.
DRAM Interface
The DRAM array is 128 data bits wide. This data is subdivided
into banks: 4 banks of 32 bits each for the 32-bit EDC version
and two banks of 64 bits each for the 64-bit EDC version. Each
bank includes the associated error check bits: 7 bits for the 32-bit
EDC version and 8 bits for the 64-bit EDC version. The DRAM
array is divided in depth into blocks. Each block may be populated with different DRAM chip sizes, however, all DRAM chips
in a given block must have the same depth. From one to four
blocks may be populated with DRAM, however there are certain
restrictions as given in other sections.
The DRAM interface consists of a bidirectional data bus for each
DRAM bank, plus a bidirectional bus for the associated error
detection and correction check bits. There is also a set of bankassociated write/read control ou~. The DRAM blocks are
controlled by separate RAS and CAS control outputs. There is
one RAS and one CAS for each block. The entire DRAM array is
addressed through one set of 12 row/column multiplexed address
lines. The row/column partition is dictated by the DRAM that
populates a particular block.
Latch Requirements
Transparent latches are required between the R/W signals issued
by the controller module and the DRAM. These latches guarantee that the R/W signals to the DRAM are stable while CAS is
asserted. The latch is transparent when CAS is HIGH and closed
when CAS is LOW. The latches can also be used to buffer RIW
lines to the DRAM. A 74ABT373 or equivalent is recommended.
There are two alternatives for the latches:
1. One quad latch is devoted to each DRAM block. Each quad
latch is enabled by the CAS for that block. RIW[3:0) is con~
nected to the four inputs ofthe quad latch and the outputs of the
quad latch are connected to the R/W inputs of the appropriate
DRAM bank in that block. Refer to part (a) in Figure 2.
2. One quad latch is devoted to all of the DRAM blocks. the quad
latch is enabled by the logical OR of CAS [3:0). R/W[3:0) is connected to the fourinputs of the quad latch and the outputs ofthe
quad latch are connected to the R/W inputs of the appropriate
D RAM bank for all of the blocks. Refer to part (b) in Figure 2.
DRAM Interface for the 32·Bit EDC
The controller supports an organization of DRAM that is 156
bits wide (four banks each consisting of 32 bits of data plus 7 error check bits) and~o four blocks dee~ch block is controlled by separate RAS and CAS signals (RAS[3:0), CAS[3:0)).
Each Bank is controlled by separate read/write signals
(RiW[3:0)). The DRAM address outputs from the controller
module consists of a 12-bit row/column multiplexed bus. This bus
is intended to drive a symmetrical set of address driver devices,
which in turn drive the DRAM array address lines. Timing for the
RAS and CAS outputs as well as other DRAM related timing is
programmable. A representation of the DRAM organization is
shown in Figure 3.
Each square in Figure 3 represents a bank of memory that is 32
data bits wide plus 7 check bits. A block is a column of four banks
totalling 128 data bits wide plus 28 check bits. Each block is controlled by dedicated RAS and CAS signals. With 12 multiplexed
row/column address lines, each bank can be up to 16 megabits
deep. The row/column address multiplexing is programmable.
The controller supports 256K-, 1M-, 4M-, and 16M-deep
DRAMs.
DRAM Interface for the 64·Bit EDC
This controller supports an organization of DRAM that is 144
bits wide (two banks each consisting of 64 bits of data plus 8 error
check bits) and up to four .blocks de~ach block is controlled
by separate RAS and CAS signals (RAS[3:0), CA~:O)). Each
bank is controlled by separate read/write signals (R/W[l:0)). Address outputs, RAS and CAS outputs and DRAM timing is identical to that in the 32-bit EDC version. A representation of the
DRAM organization is shown in Figure 4.
Each square in Figure 4 represents a bank of memory that is 64
data bits wide plus 8 check bits. A block is a column of two banks
totaling 128 data bits wide plus 16 check bits. Each block is controlled by dedicated RAS and CAS signals. With 12 multiplexed
row/column address lines, each bank can be up to 16 megabits
deep. As in the 32-bit EDC version, the row/column address multiplexing is programmable. The controller supports 256K-, 1M-,
4M-, and 16M-deep DRAMs.
DRAM Block Placement
There are four physical DRAM blocks. Each block may be populated with an array of DRAMs that are 128 bits wide by 256K,
1M, 4M, or 16M deep. Physical block population need not be
contiguous.
An array of five registers are used to specify the DRAM configuration. At power-up, the controller module is programmed with
the Base address (the starting address of the entire memory
array) and the Logical Block Displacement and Population (the
address gap between logical blocks and their respective DRAM
sizes). Finally, the physical/logical mapping is assigned and each
block's RAS/CAS address split point is specified.
During operation, an incoming memory address is evaluated.
Once the controller determines that this address is valid, the appropriate RAS signal for the selected block is asserted. The controller will remain inactive if the comparison is invalid. Refer to
the register description for programming details.
DRAM Interface Signals
CYM7232 - 32·bit EDC
The module interface to the DRAM array is made through the
signals described below.
DDA[31:0] - Data Bus (Bank 0). DDA[31:0) forms a 32-bit data
bus that is connected to bank 0 in every populated block.
DDB[31:0] - Data Bus (Bank 1). DDB[31:0) forms a 32-bit data
bus that is connected to bank 1 in every populated block.
DDC[31:0] - Data Bus (Bank 2). DDC(31:0) forms a 32-bit data
bus that is connected to bank 2 in every populated block.
DDD[31:0] - Data Bus (Bank 3). DDD[31:0) forms a 32-bit
data bus that is connected to bank 3 in every populated block.
EDA[6:0] - Check Bus (Bank 0). EDA[6:0) forms a 7-bit error
check bit bus that is associated with the data on DDA[31:0).
EDB[6:0] - Check Bus (Bank 1). EDB[6:0) forms a 7-bit error
check bit bus that is associated with the data on DDB[31:0).
8-122
---..
~
--=-,
CYM7232
CYM7264
PRELIMINARY
=:====i iii CYPRESS
SEMICONDUCTOR
CAS [31
CAS [21
CYM7232
(CYM7264)
BLOCK
0
CAS[11
7
BLOCK
1
BLOCK
2
BLOCK
3
1
LRJW[3:0]
LAT
'---
....--i...-
LRJW[3:0]
LAT
R/W[3:0]
-
(R/W[1:0])
J
(LRJW[1:0])
(LRJW[1:0])
;---
LRJW[3:0]
LAT
-
(LRJW[1:0])
....--LRJWf3:01
LAT
(LRJW[1:0])
'---
(a)
I
CIJ
W
..J
CAsr31
:::l
C
CAsr21
CYM7232
(CYM7264)
BLOCK
0
CAsr11
CAsrOl
R/W[3:0]
~
(R/W[1:0])
-I....-
LAT
LRJW[3:0]
(LRJW[1:0])
(b)
Figure 2. RIW Latch Configurations
8-123
BLOCK
1
BLOCK
2
BLOCK
3
o
:E
~
;~PRESS
""'=',
.
PRELIMINARY
CYM7232
CYM7264
SEMICONDUCTOR
CYM7232 - 32-bit EDC (continued)
RAS1 __________~
CAS1
RASO _ _ _ _ _ _--,
CASO
32
DDA[31:0]
EDA[6:0]
LR/W[O]
DDB[31:0]
•
,
32 l
EDB[6:0]
•
LR/W[1]
32
DDC[31:0]
EDC[6:0]
•
LR/W[2]
32
DDD[31:0]
EDD[6:0]
LR/W[3]
M7232·3
Figure 3. DRAM Configuration for the CYM7232
RAS1 __________~
CAS1
RASO __________----.
CASO
DDA[63:0] ....---.;:;6..;.,4'-----1~
EDA[7:0]
--~"-I--~
LR/W[O] -------i~1
DDB[63:0] ............;.64-+-__~
EDB[7:0]
------'+--~
LR/W[1] -------i~1
M7232·4
Figure 4. DRAM Configuration for the CYM7264
EDC[6:0] - Check Bus (Bank 2). EDC[6:0] forms a 7-bit error
check bit bus that is associated with the data on DDC[31:0].
EDD[6:0] - Check Bus (Bank 3). EDD[6:0] forms a 7-bit error
check bit bus that is associated with the data on DDD[31:0].
ADRS [11:0] - Address Bus. ADRS is a 12-bit row!column multiplexed address bus that supplies the address to the DRAM to access the proper 128-bit data word. The multiplexing is programmable for different depths of DRAM.
R/W[3:0] - Read/Write Control. R!W[3:0] are the read/write
controls for the four banks of the DRAM array. R!WO controls
read/write for all blocks ofDDA[31:0], R!W1 controls read/write
for all blocks of DDB[31:01....R/W2 controls read/write for all
blocks ofDDC[31:0], and R(W3 controls read/write for all blocks
of DDD[31:0].
RAS [3:0] - These signals are the four RAS outputs to control
each block of the DRAM .
CAS [3:0] - These signals are the four CAS outputs to control
each block of the DRAM.
The address bus, ADRS[11:0], RAS[3:0], CAS[3:0] should be
connected through a set of drivers to the appropriate DRAM inputs. R/W[3:0] should be connected through a set of latches,
gated by the appropriate CAS to the DRAM RIW controls. The
driver configuration is dependent upon the capacitance that must
be driven.
The data bus, check bus, and read/write control signals are connected across the DRAM array. DDA[31:0] and EDA[6:0] are
connected to the data I/O of all the Bank 0 DRAMs. The Bank 0
DRAMs are the top row of DRAMs in Figure 3. LR!WO is connected to the Write Control input of all the Bank 0 DRAMs.
DDB[31:0] and EDB[6:0] are connected to the data I/O of all the
Bank 1 DRAMs. The bank 1 DRAMs are the second row of
DRAMs. LR!W1 is connected to the Write Control input of all
the Bank 1 DRAMs. This connection pattern continues with
Banks 2 and 3.
RASO and CASO are connected to the RAS and CAS inputs respectively of all of the DRAMs of Block O. Block 0 is the left column of DRAMs in the array in Figure 3. Note that each block
consists of Banks 0 through 3. Similarly, RAS1 and CAS1 are
connected to th~ RAS and CAS inputs respectively of all of the
DRAMs of Block 1. This connection pattern continues through
Block 3.
CYM7264 - 64-bit EDC
The module interface to the DRAM array is made through the
signals described below.
DDA[63:0] - Data Bus (Bank 0). DDA[63:0] forms a 64-bit data
bus that is connected to bank 0 in every populated block.
DDB[63:0] - Data Bus (Bank 1). DDB[63:0] forms a 64-bit data
bus that is connected to bank 1 in every populated block.
EDA[7:0] - Check Bus (Bank 0). EDA[7:0] forms an 8-bit error
check bit bus that is associated with the data on DDA[63:0].
EDB[7:0] - Check Bus (Bank 1). EDB[7:0] forms an 8-bit error
check bit bus that is associated with the data on DDB[63:0].
ADRS [11:0] - Address Bus. ADRS is a 12-bit row/column multiplexed address bus that supplies the address to the DRAM to access the proper 128-bit data word. The multiplexing is programmable for different depths of DRAM.
8-124
CYM7232
CYM7264
~
--.
~~
----" -=
PRELIMINARY
CYM7264 - 64-bit EDC (continued)
Table 4. DRAM Programmable Timing Parameters
CYPRESS
~§ SEMICONDUCTOR
R/W[1:0] - ReadlWrite Control. R/W[1:0] are the read/write
controls for the two banks of the DRAM array. R/WO controls
read/write for all blocks ofDDA[63:0], R/W1 controls read/write
for all blocks of DDB[63:0].
RAS[3:0] - These signals are the four RAS outputs to control
each block of the DRAM.
CAS[3:0] - These signals are the four CAS outputs to control
each block of the DRAM.
The address bus, ADRS[11:0], RAS[3:0], CAS[3:0] should be
connected through a set of drivers to the appropriate DRAM inputs. RIW[1:0] should be connected through a set of latches,
gated by the appropriate CAS to the DRAM RIW controls. The
driver configuration is dependent upon the capacitance that must
be driven.
The data bus, check bus, and read/write control signals are connected across the DRAM array. DDA[64:0] and EDA[7:0] are
connected to the data I/O of all the Bank 0 DRAMs. The Bank 0
DRAMs are the top row of DRAMs in Figure 4. LR/WO is connected to the Write Control input of all the Bank 0 DRAMs.
DDB[63:0] and EDB[7:0] are connected to the data I/O of all the
Bank 1 DRAMs. LR/W[1] is connected to the read / write control
inputs of all of the DRAMs of Bank 1.
RASO and CASO are connected to the RAS and CAS inputs respectively of all of the DRAMs of block O. Block 0 is the left
column of DRAMs in the array in Figure 4. Note that each
block consists of Bank 0 and Bank 1. Similarly, RAS1 and
CAS1 are connected to the RAS and CAS inputs respectively
of all of the DRAMs of block 1.
DRAM Timing
The system bus clock rate determines the DRAM timing through
an internal (X2, X4) phase locked loop, or an externally generated multiple clock (Xl, X2, X3, X4 applied to MCLK input).
Along with the multiplier selection, the appropriate VCO is selected to generate either a 66-MHz, 80-MHz, or 100-MHz internal clock. This selection is shown in Table 3. There are two versions, - Hand - S. The - H version permits the use of the higher
clock frequency multiples for maximum performance.
Table 3. Required PLL Frequency
Phase Lock Loop
Frequency (MHz)
-H
Phase Lock Loop
Frequency (MHz)
-S
80
66 (int), 99 (ext)
80
33
25
100
50 (ext)
Bus Clock
(MHz)
40
66
The phase lock loops should be operated close to their center frequency to guarantee operation. For deviations from the bus clock
frequencies listed in Table 3, consult Command Register 4 (programming of VC0[1:0]). Refer to the CLM[1:0] field in the
Command register for programming details.
DRAM timing is fully programmable through internal registers.
The resolution of the timing is equal to the period of the internal
clock. (This is normally twice the bus clock frequency for 40-MHz
bus speeds.) The parameters listed in Table 4 are programmable.
Refer to the timing diagrams at the end of this data sheet for the
timing definitions. Refer to the Register Descriptions for details.
Parameter
Description
tAR
tRAM
Address to RAS assertion
RAS to multiplexed address
tMAC
tRAS
Multiplexed address to CAS
RAS pulse width
tRPR
tcp
tDe
tRIN
tENR
tENW
RAS pre-charge width
CAS pre-charge width
FIFO data delay to CAS
RAS completion during non-reflective inhibit
Enable delay on read
Enable delay on write
Refresh and Scrubbing
Refresh requirements vary depending on the density and organization of the DRAM chips in the system. However, rows must
be refreshed at the same interval (approximately every 15 microseconds the next row is refreshed). The refresh requests are generated by two cascaded counters. A programmable 7-bit counter
divides CLK down to create a I-MHz clock signal. This clock is
further divided by a 4-bit, modulo 15 counter, to generate a refresh request every 15 flsec. These refresh requests are synchronously arbitrated with memory requests.
The 26-bit Scrub Address counter is comprised of three smaller
counters: the least significant 12 bits form a row scrub counter,
the middle two bits form a block counter, and the most significant
12 bits form a column address counter.
:
All four banks of a given block are scrubbed simultaneously at a
particular address. All error correction channels in the controller (/)
are used in parallel (4 channels in CYM7232, 2 channels in W
II
;t~!':i~~:2b~~~:;nn;e~!~h:o~~~l~=.bi~~k~_~i~~~~~e~i~~~ ~
counter advances after all rows in a particular block are scrubbed.
Finally, the column address is incremented so that all rows and
blocks of the next column are refreshed and scrubbed. A fully
populated memory using 16-Mbit devices to achieve I-gigabyte
capacity is scrubbed in little more than 15 minutes. When an error is detected during scrubbing operations, the correction address will be copied from the Refresh Address counter to the Error Location register. (Note that when an error occurs in a
normal read operation, the corrected data is not written back into
the memory array. Data is corrected inside the DRAMs during
scrubbing cycles only.) When an error occurs during refresh/
scrubbing operations the refresh cycle (i.e., a read to check for
errors) is turned into a scrub cycle (i.e., read-modify-write to correct the errors).
Each block of memory may be populated with different sized
DRAM components however, all banks within a given block must
be populated with the same depth memory chip. For simplicity,
the Refresh Address counter treats every block as if it were populated with DRAMs of maximum (16-Mbit) capacity. When refreshing smaller memories, the same address location will be
scrubbed multiple times before the counter advances to the next
location.
8-125
0
::E
*::~
~=CYPRESS
~,
PRELIMINARY
CYM7232
CYM7264
SEMICONDUCTOR
Refresh Modes
There are two modes of refresh/scrubbing. The four RAS signals
are staggered differently in each mode. Staggering prevents noise
problems when switching current simultaneously to multiple
blocks of DRAM.
Staggered RAS
The system data bus parity signals are equipped with holding
buffers similar to those used by the system data bus.
Table 5. Data Parity Assignments
Data Parity
DP[O]
DP[I]
DP[2]
DP[3]
DP[4]
DP[5]
DP[6]
DP[7]
The onset of each RAS signal is staggered by one bus clock (four
bus clocks overa.!!li!t the first mode. Once all RAS lines are asserted a single CAS signal is selected for presentation to the
scrubbed block of memory. The strobe signal used to enable
clocking of the scrubbed data into the controller is also delayed
by an amount equal to the staggered RAS delay.
Mutually Exclusive RAS
Some SIMMs are constructed with mUltiple sections of RAS enabled DRAM (i.e., common CAS lines across sections) The controller offers a second non-overlapping RAS refresh mode that
supports these SIMMs. This is essential so that the CAS that is
asserted for the scrub operation will enable only the required
SIMM section. Should this type of DRAM SIMM be used, pairs
of blocks would be RAS enabled during refresh or normal
DRAM accesses. Each block pair would share a common CAS.
The controller may be configured to internally OR the appropriate CAS pairs to produce a single CAS output for each pair of
blocks. Refresh in the non-overlapping RAS mode is longer th,an
that of the staggered RAS refresh mode. Refer to the Register
Descriptions for details.
Initialization
The DRAM is initialized when the IN IT command is given. The
DRAMs are energized with 15 RAS only cycles. All of DRAM
can then optionally be filled with zeros and the associated error
check bits.
Diagnostic Features
For diagnostic purposes, the DRAM error check bits may be read
or written by the system. The error check bits may be accessed by
reading the EDC registers at any time. The error check bit fields
will contain the error check bits from the previous DRAM read
cycle. Error check bits may be directly written to DRAM py first
writing the desired check bits to the Write Check Bit register and
then setting the appropriate control bit in the Command register.
All subsequent DRAM writes. will write the check bits from this
register. Clearing the control bit will return the check bit source
to the data path's write error check bit generation circuitry.
Data Byte
D[7:0]
D[15:8]
D[23:16]
D[31:24]
D[39:32]
D[47:40]
D[55:48]
D[63:56]
PMD[2:0] - Parity Mode. The Parity Mode bits specify the parity computation algorithm and identify those signals that participate in the parity computation. They must be hardwired for the
correct configuration. The parity mode selection is applied to
both the address and data buses. These bits are defined below.
PM2
o
Even Parity Computed (sum of bits in byte and
parity bit is even.)
Odd Parity Computed (sum of bits in byte and
parity bit is odd.)
PMl
o
Data Parity Disabled
1
Data Parity Computed
PMO
o
Address Parity Disabled
1
Address Parity Computed
A[35:0] - Address. During the address phase, the system will
supply the transaction's address on A[35:0] and assert AS.
AP[3:0] - Address Parity. During the address phase, the lowest
32 bits of the transaction's address can be checked for parity. The
system can generate a set of parity inputs AP[3:0] that correspond to A[31:0]. Parity is not supported for A[35:32]. The parity's sense (i.e., odd/even and enable/disable) is specified by the
Parity Mode bits, PM[2:0]. Note that the parity mode bits also
define the parity mode for the data bus. AP[3:0] are assigned as
given in Table 6.
Table 6. Address Parity Assignments
Bus Interface Signal Description
D[63:0] - Data. During the data phase, D[63:0] contains the
transactions data. The system data bus signals are equipped with
holding buffers. These buffers use a weak feedback buffer combined with an input buffer to form a latch. The latch holds the
last value driven on the bus.
DP[7:0] -Data Parity. During the data phase, DP[7:0] reflects
the parity of the transaction's data. During the address phase,
DP[7:0] is ignored and the outputs are three-stated. Data parity
is checked only over those bytes that are enabled. During a data
phase write, DP[7:0] are inputs, receiving the parity as transferred across the bus. During a data phase read, DP[7:0] are outputs, indicating the parity of the data that has been applied to the
bus. The parity output is enabled only when the relevant data
byte is enabled. The parity outputs remain three-stated when the
parity is disabled. The parity's sense (i.e., odd/even and enable/
disable) is specified by the Parirj ~v1ode bits, P~v1[2:0]. DP[7:0]
are assigned as given in Table 5.
Address Parity
AP[O]
AP[I]
AP[2]
AP[3]
Address Byte
A[7:0]
A[15:8]
A[23:16]
A[31:24]
TYPE [5:0] - Transaction Type. During the address phase,
TYPE[5:0] specify the Transaction Type (see Table 7). These are
synchronous inputs. Note that the TYPE input may be changed
on a transaction by trans.action basis, consequently, different processors may be mixed within the system.
TYPEO - ReadIWrite. When 0, this bit indicates the transaction
is a write. When 1, this bit indicates the transaction is a read.
8-126
-----~
-==-~
_ ' j ; CYPRESS
-=-
iF
PRELIMINARY
SEMICONDUCTOR
When TYPE 1 = 0 the burst order is sequential. Subsequent addresses are generated by sequentially incrementing the bits of the
address within the range of the burst counter as determined
above. After reaching the address in which all burst counter bits
are ones, the counter wraps around to zero. Higher-order addresses remain fixed.
Table 7. 1Ype Interpretation
Data Size
1Ype Bits
S 4 3 2 1 0
0 o X XX 0 Any
Transaction 1Ype
Write
0 XX XX 1 Any
1
o
Read
X XX 0 Default Burst Write
When TYPE1 = 1 the burst counter increments in the non-sequential fashion characteristic of Intel processors. In all other respects, the address for the burst is the same as that in the sequential case. The non-sequential burst counter algorithm extends the
Intel scheme to any length burst. The nonsequential counting
starts at the address specified by the address bus input. The
counter bits are then incremented in the following fashion:
1 XX XX 1 Default Burst Read
XX XX o X
XX X X 1 X
~Bus
Width
~Bus
Width
XX X 0 XX Any
0 X X 1 XX
XX
o
CYM7232
CYM7264
~Bus
Sequential Burst Order
Intel Burst Order
Size [3:0] are Size Bits
Width
X XX Any
1. the lowest-order bit always toggles,
2. a bit toggles only if the next lowest order bit in the counter
is toggling for the second time (independent of its value).
For example, if the burst counter is 3 bits in length (AD[S:3] as
above) and begins at address 101, then the counting sequence is
Size [7:0] are Byte Enables
Little-Endian Bus
X X 1 XX X Any
Big-Endian Bus
0 1 XX X 0 Any
Posted Write
101, 100, 111, 110, 001, 000, 011, 010
1 1 XX X 0 Default Burst Posted Write
TYPEl - Burst Order. Given a system bus of width N bytes (N =
4 or 8), any transaction as specified by the SIZE input which is
greater than N constitutes a burst. Thus transactions of double
words (8 bytes) and larger are bursts for a 32-bit bus and transactions of 16 bytes and larger are bursts for a 64-bit bus. The maximum burst length is 128 bytes. During bursts the lowest order
bits of the address input are ignored. AD[1:0] are ignored for a
32 bit bus system and AD[2:0] are ignored for a 64 bit bus system. This is the alignment constraint.
The next higher set of address inputs are loaded into a counter,
which generates the proper address as the burst proceeds. The
counter length is given in Table 8. The generated burst address
will wrap around at the cache line end and complete the burst access for the remainder of the cache line.
Table 8. Burst Counter Length
Burst Length
(bytes)
Burst Counter Length
for 32-Bit Bus (bits)
Burst Counter
Length for 64-Bit
Bus (bits)
Not Burst
8
1
16
2
1
32
3
2
64
4
3
128
S
4
A new address, in which the burst counter serves as the lowest
portion, is formed. The counter extends the length of address bits
as shown in Table 8 and starts at AD2 for a 32-bit system bus and
at AD3 for a 64-bit system bus. All higher address bits (above the
counter) remain fixed throughout the burst transaction and are
not affected by rollover of the burst counter. As an example, for a
64-bit system bus and a SIZE of 64 bytes, the system ignores
AD[2:0], fixing these bits at O. AD[S:3] form the internal burst
counter starting from the address as transferred over the system
bus, and AD[3S:6] remain fixed as originally input. This address
generation is shown for this example in Table 9.
Tabl~
9. Burst Address Example
AD[3S:6]
Fixed
I AD[S:3]
IAD[2:0]
Counter
000
I
Notice that in this counting sequence, higher-order bits change
the least often and therefore result in a minimum number of
DRAM page mode accesses.
TYPE2 - SIZE Interpretation. The SIZE bits have two alternative interpretations. When TYPE2 = 0, the transaction length in
bytes is given by the value of SIZE[3:0]. When TYPE2 = 1, the
byte(s) that are enabled in the transaction are specified when
their respective size bits are asserted LOW (e.g., SIZE[N] means
BYTE[N] participates in the transaction). For elaboration see the
SIZE[7:0] definition.
II
TYPE3 - Little EndianlBig Endian. Processors may define the
position of BYTE 0 on the bus in either of two ways. Either
BYTE 0 appears as the lowest byte on the bus (D[7:0] - little (J)
endian, TYPE3 = 0) or BYTE 0 appears as the highest byte on W
the bus (big endian - D[M:M -7], where M = Bw - 1. Bw is the ...J
bus width in bits, TYPE3 = 1). For elaboration see the definition :::)
of the SIZE[7:0] bits.
C
TYPE4 - Write Posting. When TYPE4 = 1, the write data is
posted into the Write FIFO, where it remains until the next read
is completed. This can be used to postpone the actual DRAM
write until after the DRAM read is completed, thereby speeding
cache line fills.
TYPES - Default Burst Mode. When TYPES = 0, the transaction's size is specified by SIZE[7:0] (which are interpreted according to TYPE2). When TYPES = 1, the transaction's size is
specified by the default burst size programmed into the Command register. The burst size defaults to this value regardless of
TYPES during reflective reads transformed into writes and writes
transformed to reads for ownership.
SIZE[7:0] - Transaction Size. During the address phase,
SIZE[3:0] specify the number of bytes to be transferred during a
bus transaction. These are synchronous inputs. SIZE[7:4] are an
extended size control used to support byte enabled transfers. The
expanded definition is compatible with i486, i860, SPARC, MIPS,
88K and 68040 processors. The interpretation of SIZE is determined by TYPE2 as in Table 10 through Table 16. Note that for
size specifications that are larger than the system bus size, the
Transaction Size specifies the internal burst address generation
wraparound.
Two interpretations are offered in the above table to support
SPARC MBus and Motorola 88K processors.
8-127
o
::E
~
~.CYPRF.SS
CYM7232
CYM7264
PRELIMINARY
~, SEMICONDUcrOR
Table 14.32 Bit Bus Address Interpretation Size = 1 Byte
Table 10. Size Interpretation with TYPE2 = 0,
SIZE[7:41 = XXXX
SIZE 2 SIZE 1 SIZE 0
0
0
0
SIZE 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
Al
AO
Byte #
Transaction Size
Byte
X
0
1
0
1
0
1
0
0
1
Halfword (2 Bytes)
X
0
0
1
0
1
0
Word (4 Bytes)
X
1
0
1
1
1
1
0
0
0
1
Doubleword (8 Bytes)
16-Byte Burst
1
1
1
1
0
1
0
0
0
0
1
0
1
0
0
0
1
1
A2
Al
AO
128-Byte Burst
X
32-Byte Burst
X
0
1
32-Byte Burst
64-Byte Burst
1
X
0
Halfword (2 Bytes)
X
1
Byte
1
1
1
1
Table 11. 64 Bit Bus Address Interpretation Size = 1 Byte
0
D[7:0]
X
X
X
X
0
X
X
X
X
X
X
X
0
0
X
D[lS:8]
D[23:16]
D[31:24]
X
X
X
D[39:32]
X
X
X
X
X
D[47:40]
X
X
X
X
X
D[55:48]
X
X
X
X
X
D[63:56]
X
X
X
X
X
X
X
X
X
D[7:0]
X
0
0
0
0
1
1
0
1
1
2
D[SS:48]
D[47:40]
D[lS:8]
D[23:16]
0
X
X
3
4
D[39:32]
D[31:24]
S
6
7
D[23:16]
D[1S:8]
Little Endian
D[31:24]
D[39:32]
D[47:40]
D[SS:48]
D[63:S6]
Table 12. 64 Bit Bus Address Interpretation Size
= 2 Bytes
A2
Al
AO
Halfword#
0
0
1
0
1
X
0
1
D[63:48]
D[47:32]
D[lS:0]
D[31:16]
0
1
X
2
D[31:16]
D[47:32]
X
3
D[lS:0]
D[63:48]
1
X
Big Endian
Little Endian
Table 13. 64 Bit Bus Address Interpretation Size = 4 Bytes
A2
Al
AO
Word #
0
1
X
X
X
X
0
1
Big Endian
D[63:32]
D[31:0]
Little Endian
D[31:0]
D[63:32]
Byte
0
D[63:S6]
D[7:0]
D[lS:0]
D[31:16]
X
0
0
1
D[15:0]
X
Byte #
0
1
1
1
Little Endian
X
0
1
1
X
Big Endian
X
X
AO
0
1
D[31:16]
X
X
0
1
X
Half·
Word #
0
X
X
Al
0
D[31:24]
1
0
1
1
D[23:16]
2
A2
0
D[1S:8]
D[7:0]
3
X
5
X
0
X
Big Endian
2
3
Size [x]
64-Byte Burst
6
1
D[7:0]
D[lS:8]
Table 16. Size Interpretation with TYPE2 = 1
7
0
Little Endian
Table 15. 32 Bit Bus Address Interpretation Size = 2 Bytes
32-Byte Burst
64-Byte Burst
Doubleword (8 Bytes)
Word (4 Bytes)
0
0
1
X
Big Endian
D[31:24]
D[23:16]
4
0
Processors generally require their byte enable signals to be contiguous. No checking is performed to distinguish invalid combinations from valid combinations.
AS - Address Strobe. This signal is asserted by the bus master
during the address phase of the transaction. The address and
transaction attributes are strobed into the Controller Module
during the address phase. The address phase is one clock cycle
long and is normally followed by one or more data phases.
DS - Data Strobe. This signal is asserted by the bus master to
begin the data phase of the transaction. Data strobe is recognized
in certain modes and can be used by the system to delay the onset
of the transaction. If the transaction is a burst, data strobe can
not be used to interrupt or delay individual data phases of the
burst. Data Strobe may be permanently asserted in those applications that do not need this function. Refer to the section on Bus
Acknowledge and Data Strobe Modes for details.
BLST - Burst Last. The burst length is specified by SIZE[3:0] or
the programmed default burst length by way of the TYPE input
during the address phase of every transaction. BLST may be used
by the bus master to override the default or SIZE specified burst
length by prematurely terminating the bus transaction. BLST
must be asserted in the same cycle as the last data transfer.
INH - Inhibit. This signal may be asserted by a cache controller
in multiprocessing environments to abort a bus transaction already in progress. When INH is received before the snoop window ends, the operation is terminated. If the transaction is a
memory read, no data is transferred over the system bus while
the snoop window is open. If the transaction is a memory write
and data has already been transferred, the internal FIFOs are
cieared. Inhibit may be used to prematurely terminate VO opera-
8-128
~
~.CYPRESS
~ JF
PRELIMINARY
CYM7232
CYM7264
SEMICONDUCTOR
tions before data is transferred. INH should not be asserted after
the snoop window closes.
TRC - Transform Cycle. This signal, when asserted along with
mH, transforms an inhibited read cycle into a write cycle (reflective) or an inhibited write cycle into a read cycle (read-for-ownership). Transformed transactions use the programmed default
burst length and ignore the SIZE specified in the original transaction. The burst begins at the address specified at the transaction start.
SNW - Snoop Window. This input may be used to define the
duration of the snoop window. Operations may be inhibited and
transformed in any cycles in which this signal is asserted. As an
alternative, the duration of the snoop window may be defined by
an internal counter.
RSTIN - Reset In. This signal is used to reset the controller. The
signal must last for at least 16 clocks. This signal is internally synchronized to the bus clock.
BACK[1:0] - Bus Acknowledge. These signals supply the transaction acknowledge to the bus master. They are defined in
Table 17. These signals also receive acknowledges from the system during reflective reads thereby acting as data strobes. During
system reset BACK[1:0] act as inputs to program bus acknowledge modes and select the source of the snoop window signal.
BACK[1:0] are used as inputs during Reset to select the Bus Acknowledge and Data Strobe modes. BACK[1:0] must be driven
according to Table 18 when Reset is asserted to invoke the desired mode.
UERR - Uncorrectable Error Interrupt. This signal indicates the
presence of an unrecoverable error condition on a read operation. The signal is asserted at the same time as the associated acknowledge is sent to the system bus. As with BACK[1:0], UERR
may serve as an input. The signal must be driven to select the
source of the Snoop Window signal during system reset. UERR
should be pulled up with a 1K-ohm resistor to Vee.
Table 17. BACK[1:0] Outputs
BACK1
BACKO
0
1
Valid Data Transfer
1
1
Wait States
Three-state
Three-state
Idle Cycles
Definition
Table 18. BACK[1:0] Inputs When RSTIN is Asserted
BACKl BACKO
DSMode
0
MBus (DS Gnd)
0
0
1
Early DS (10k)
0
Real-Time DS
1
1
1
Early DS (2 Clks)
BACK Mode
With Data
With Data
None (Uses BR/FE)
Early BACK (1 Clk)
0
1
BACK1
0
1
Other
BACKO
1
1
Modes
Definition
Valid Data Transfer
Idle Cycle
Invalid
BERR - Bus Error. This signal indicates that a parity error
condition has occurred during the address or data phase of a
transaction. This signal is asynchronous (i.e., it will occur one
cycle after the corresponding address parity error or two cycles
after the corresponding data parity error). BERR may be programmed to last for one clock cycle or until cleared. Due to the
nature of BERR internal to the module, the controller will log a
parity error in its status register if any other device pulls BERR
LOW.
BR/FE - Bus Request/FIFO Empty. This signal will be issued by
the controller during reflective read transactions. BR from the
main memory system should be interpreted as the highest priority
~uest for bus mastership to the~tem'~biter. In this case
BR/FE works in conjunction with BG and BB to effect this mastership. Additional system bus transactions will be prevented until the ongoing write (resulting from the reflective read) to main
memory has completed. Systems having more elaborate protocols
for acknowledging data transfers between a requesting cache and
a cache data owner can use this signal to prevent the next transaction from overwriting the reflective data path inside the controller.
This output may also be programmed to include the empty status
of the FIFOs. BR/FE will then be asserted if either the reflective
FIFO or the normal write FIFO are not empty. This output may
be used by systems that assess the availability of the controller
before the data phase is initiated and pause until the controller
becomes available.
BG - Bus Grant. This signal is asserted by the external arbiter in
response to a BR, to indicate that the controller has been granted
ownership of the bus.
BB - Bus Busy. This signal is asserted by the controller for the
duration of its bus ownership. The controller will acquire the bus
as it completes the main memory write transaction during reflective read operations. When Bus Arbitration is disabled, this bidirectional pin may be used as an output to report read status.
When the controller module begins a read operation, BB will be
asserted indicating that the host can expect data in several clock
cycles (actual number of clock cycles depends on programmed
DRAM timings).
Table 21. ID[3:0] in Generic Mode
Table 19. UERR Inputs When RSTIN is Asserted
UERR(SNW)
Table 20. BACK[1:0] Inputs as Reflective Reads are
Transformed Into Writes
Snoop Window Source
External
Internal
When a read is inhibited and transformed into a write, the
BACK[1:0] signals become inputs and are used to strobe the
bus data into the Reflective FIFO. Table 20 gives the interpretation of the BACK[1:0] inputs when the reflective writes are in
progress.
ID3
ID2
ID1
IDO
DRAM Mode Selection
X
X
Not Selected
0
0
1
0
0
Not Selected
0
1
0
1
I/O Registers
0
0
1
1
0
Indirect Address Register
1
1
Not Selected
1
0
Memory
1
X
X
X
ID [3:0] - Identification. The Identification bits are synchronous
inputs recognized during the address phase. The ID bits are used
in conjunction with address signals to define the nature of the bus
8-129
Ien
W
..J
:::J
Q
o
:E
~
;~PRESS
.
,
PRELIMINARY
CYM7232
CYM7264
SEMICONDUcrOR
transaction and select I/O registers or DRAM memory. For
MBus operation refer to Table 39. For the generic mode a match
is required between 10[3:0] and the fixed values shown in
Table 21.
CLK - Clock. CLK synchronizes all bus transactions. All transactions are strobed in at the rising edge of clock.
MCLK - Multiple Clock. MCLK may be used to supply a higher-frequency DRAM clock in lieu of using the internal PLLs.
MCLK must be an integer multiple of CLK (either 1, 2, 3, or 4).
When using the PLLs, MCLK must be tied to CLK.
INT - Interrupt. This signal indicates that the module has a
pending interrupt that requires service. This output remains asserted until the interrupting condition is cleared.
IMD - Interface Mode. When tied LOW, the controller operates
in the MBus mode. When tied HIGH, the controller operates in
the generic mode.
Pin Description
Table 22 through Table 25 summarize the functional pin connections of the controller module. Power and ground connections
are not listed.
Table 22. Pin Descriptions
Signal Name
0[63:0]
DP[7:0]
I/O
I/O
I/O
PMD[2:0]
I
A[35:0]
I
AP[3:0]
I
AS
I
Description
System Data Bus: These lines are used to
transfer data to and from the DRAM
Module. These lines are normally threestated except when a valid read cycle is in
progress.
Data Bus Parity: These signals follow the
direction of the data bus. When the device
is driving the data bus (read), data parity is
generated and supplied to these pins. When
data is entering the device, data parity is
checked.
Parity Mode: These inputs specify the
parity mode for data and address.
System Address Bus: These lines are used
to transfer the address to the DRAM
module.
Address Bus Parity: These inputs are examined for address integrity during accesses to the device.
Address Strobe: This input is used to indicate that the bus address and control signals are valid. It is used to enable clocking
of the address and control information
into the controller.
Data Strobe: This input is used to indicate
that the data transaction is to take place.
OS
I
BLST
I
Burst Last: This input can be used to terminate a transaction.
I/O
Bus Acknowledge: These acknowledge
signals output the transaction response
back to the bus master. During reflective
reads, these signals are inputs. During Reset, act as inputs and are used to invoke
certain modes.
BACK[1:0]
UERR
I/O
Uncorrectable Error: This interrupt signal reports an unrecoverable error condition during a read. During reset it acts as
an input to select Snoop Window source.
RSTIN
I
CLK
I
BERR
0
Master Reset: Activating this input causes
the module to set all control and status
bits to their reset state.
System Bus Clock: This clock is used to
synchronize the controller's operation to
the system bus clock.
Bus Error (Three-State): Indicates that a
R~~tt e~ror ha~ occurred on the bus.
I J:SbKK IS asynchronous.
Signal Name I/O
INH
I
Description
Inhibit is used to abort read and write operations.
SNW
I
Snoop Window: Defines the time in which
Inhibit can be asserted.
TRC
I
Transform Cycle: This input reverses the
sense of inhibited operations.
TYPE[5:0]
I
Transaction Type: These inputs determine
the transaction type.
SIZE[7:0]
I
Transaction Size: These inputs indicate
the size of the transaction.
INT
0
Interrupt (Three-State): This output indicates that an interrupt request is pending.
10[3:0]
I
BR/FE
0
Identification: Selects memory or internal
registers; positions the module in the address space.
Bus Request/FIFO Empty: Reflects the
status of the reflective or write FIFOs.
BG
I
BB
I/O
Bus Grant.
Bus Busy: Used to assert bus ownership
or to indicate the beginning of a read operation.
DRAM row/column multiplexed address.
R/W[3:0]
0
0
R/W[1:0]
0
DRAM read/write control; one output
per bank. (CYM7264 only)
RAS[3:0]
0
DRAM row address strobe; one per
block.
CAS[3:0]
0
DRAM column address strobe; one per
block.
ADRS[11:0]
8-130
DRAM read/write control; one output
per bank. (CYM7232 only)
~
.
:~PRESS
~,
PRELIMINARY
SEMICONDUCTOR
Table 23. Special Function Signals
Signal
Name
TSTE
CYM7232
CYM7264
I/O
I
data onto the system bus and demultiplex write data from the system bus. The controller may be further connected for a multiplexed address/data bus by tying A[31:0] to D[31:0].
Description
If the system bus employs bus parity, then DPO should be tied to
DP4, DP1 tied to DP5 and so forth forming a four-bit parity
nibble for the 32-bit system bus.
Test Enable: This input must be set to 1 for
proper operation.
TSTM
I
Test Mode.
64-Bit System Bus Connection
TST[2:0]
0
Test Outputs.
MCLK
I
Multiple Frequency Clock: Optional input if
internal PLLs are not used.
IMD
I
MBus/generic interface mode select.
The 64-bit EDC version of the controller may only be connected
to 64 bit bus systems. Address and data may be multiplexed, as in
the 32 bit case, by connecting the module's address bus to a portion of its data bus. Address parity and data parity may also be
shared, by connecting the module's address parity bus bits to a
portion of its data parity bus.
Table 24. DRAM Data Signals (CYM7232)
Internal Registers
Signal
Name
DDA[31:0]
EDA[6:0]
Description
I/O
I/O DRAM data bus interface, Bank 0
I/O DRAM error check bit bus interface, Bank 0
DDB[31:0]
I/O DRAM data bus interface, Bank 1
EDB[6:0]
I/O DRAM error check bit bus interface, Bank 1
DDC[31:0]
I/O DRAM data bus interface, Bank 2
EDC[6:0]
I/O
DDD[31:0]
I/O DRAM data bus interface, Bank 3
EDD[6:0]
I/O DRAM error check bit bus interface, Bank 3
Several internal registers are available to set-up the controller
and report status to the host. Each register is spaced 16 bytes
apart in the address space so that its contents will be accessible
on D[7:0] of the data bus regardless of system bus width or
orientation (little/big endian). The EDC registers are accessed as
32-bit registers. An internal 8-bit indirect address register is provided to point to the individual 110 locations inside the controller. A register map is provided in Table 26.
DRAM error check bit bus interface, Bank 2
Table 25. DRAM Data Signals (CYM7264)
Signal
Name
I/O
I
Description
DDA[63:0] I/O DRAM data bus interface, Bank 0
UJ
W
EDA[7:0]
I/O DRAM error check bit bus interface, Bank 0
DDB[63:0]
I/O DRAM data bus interface, Bank 1
::::l
EDB[7:0]
I/O DRAM error check bit bus interface, Bank 1
o
..oJ
C
::i
Power and Ground Connections
There are two sets of power and ground connections. One set is
for the logic and I/O circuitry and is indicated by V ss and V DD in
the pin diagram. All V ss pins should be connected to ground and
all VDD pins should be connected to the +5 volt supply. There
are separate supply connections for the internal phase lock loops.
VDDL is the +5 volt supply connection and VSSL is the ground
connection for the phase lock loops. For superior noise immunity,
VSSL and VDDL should be connected with independent pcb routing. These connections should run to the power supply where it
connects to the circuit board on which the controller module resides.
The pinout lists several no connect (NC) pins. These connections
should be left open. They may be used in future versions of the
controller. IMD should be tied HIGH to invoke the generic bus
interface mode or LOW for MBus mode. TSTE must be held
HIGH.
32-Bit System Bus Connection
The 32-bit EDC version of the controller (CYM7232) may be
connected to a 32-bit system data bus. This is accomplished by
tying DO to D32, D1 to D33 and so forth. The SBS field in the
Command register must also be programmed with 0 to invoke the
32-bit system bus mode forcing the controller to multiplex read
8-131
CYM7232
CYM7264
~
~~
PRELIMINARY
=====
""""==",= CYPRESS
SEMICONDUcrOR
Table 26. Register Map
Index
Name
R/W
7
OOH
OIH
Command Register 0
Command Register I
RIW
RIW
CIE
INIT
02H
Command Register 2
R/W
03H
04H
Command Register 3
RIW
Command Register 4
R/W
OSH
06H
07H
Command Register S
Command Register 6
Reserved
R/W
R/W
OSH
09H
DRAM Timing 0
R/W
RAM
DRAM Timing 1
R/W
RAS
AR
MAC
OAH
OBH
DRAM Timing 2
DRAM Timing 3
RIW
R/W
CP
RIN
RPR
DC
OCH
ODH
OEH
OFH
DRAM Timing 4
Reserved
Reserved
Reserved
RIW
ENW
ENR
10H
Base Address [7:0]
RIW
llH
Base Address [1S:S]
R/W
12H
Logical Block Displacement [7:0]
R/W
13H
14H
1SH
16H
17H
Logical Block Displacement [15:8]
Reserved
Reserved
Reserved
Reserved
R/W
8-132
IE
5
6
4
I
I
3
o
1
2
RFD
WC AEM
BLP
I SBS
CLM
BAM
PLT
VCO
I
I CAM I RSM I BRM
EME
I EUE I EDE I ESE
IOSWC
EDP lEAP
SNWWRCNT
SNWRDCNT
BA[27:20]
Reserved
I
Reserved
I
RFT
DFB
SEN
BLK
RCM
I
I
ES
BA[35:28]
DS2
I
I
DS1
DS3
CYM7232
CYM7264
~
5:~
PRELIMINARY
_ ' i l l CYPRESS
-=:::=,
SEMICONDUCTOR
Table 26. Register Map (continued)
Index
18H
Name
Logical Block Population Code [7:0]
19H
1AH
R/W
5
6
7
I
LPC3
Logical Block Population Code [15:8]
R!W
R!W
Physical/Logical Map [7:0]
R/W
PBL3
I
I
I
4
lBH
Reserved
Logical Block Mux Position [7:0]
R/W
Reserved
1DH
Logical Block Mux Position [15:8]
R/W
Reserved
lEH
Reserved
LBP3
PBL2
Reserved
Error Location Address [7:0]
R
ELA[7:0]
21H
Error Location Address [15:8]
R
ELA[lS:8]
22H
Error Location Address [23:16]
R
23H
Error Location Address [31:24]
R
24H
EDC Register 0
R
2SH
EDC Register 1
R
26H
Reserved
27H
Reserved
Syndrome FIFO Flags 0
R
29H
Syndrome FIFO Flags 1
R
2AH
Reserved
2BH
Reserved
2CH
2DH
Diagnostic Check Bit 0
W
Diagnostic Check Bit 1
W
2EH
Reserved
2FH
Reserved
30H
Silicon Revision
R
31 H
Bus Error
W
32H
Interrupt Status Register
I
I
LBP1 LBPO
PBLO
LBMPO
I
1FH
28H
ILBP2
I
LBMP3
20H
ELA[23:16]
LPCO
PBLl
LBMP1
o
1
2
LPC1
Reserved
1CH
3
LPC2
LBMP2
ELA[23:16]
ELA[31:24]
See Section on Error Status Registers
I
tn
W
.J
R/W
8-133
I
IC
lOBE
~
REV[3:0]
Reserved
I ABE
BEM
MEW I UEW DEW
I BEC
I SBW
C
o
:E
.~
==r
~~CYPRESS
SEMICONDUCTOR
""""==II!'"
Index Register
IA[7:0] - Index Address. This register's contents points to all
other registers inside the controller. During access to the controller's internal byte wide I/O path, little-endian processors should
apply an address with A[3:0] = 0 to enable data onto D[7:0] on
their system bus. Big-endian processors should apply an address
with their A[3:0] = F to enable data onto D[7:0] on their system
bus. Access to the internal registers is controlled through the ID
bits. For ID3 equal to 1, all accesses occur to memory. For ID3
equal to 0, access is to the internal registers: with ID[2:0] equal to
110, transactions are directed to the Index register, with ID[2:0]
equal to 101, transactions are directed to the register pointed to
by the Index register. For all other combinations of the ID input,
the controller is not selected. ID3 functions as the MemorylIO
select and the remaining ID inputs function as selects or chip enables.
This register is not used in MBus mode. See MBus section for details on writing and reading I/O registers.
Command Registers - Write / Read
Command Register 0
Index
7
6
5
4
3
2
CIE - Coherent Invalidate Acknowledge Enable. When this bit
is set HIGH it enables acknowledges to MBus Coherent Invalidate cycles. BACK[1:0] are generated two clocks after the address phase in which the TYPE bits specify this cycle. Systems requiring different acknowledge delays should set CIE = 0 and use
an external PLD to generate the acknowledge. This bit should be
set to 0 when in the Generic Mode.
RFD - Refresh Counter Divisor. These bits divide CLK down to
1 MHz. The output of this counter is further divided by a fixed
divide "by IS" counter, which produces the 15 microsecond refresh requests. The division factor is the load value plus 1. For example, the divisor load values in decimal for the various bus clock
frequencies are:
7
1
6
32 Bits
64 Bits
ES - EDC Size. Specifies the number of data bits in each EDC
packet.
o
1
32 Bits
64 Bits
CLM - Clock Multiplier. These bits program the multiplication
factor from the incoming bus clock (CLK) to the internal DRAM
timing clock. They are defined as follows:
CLM[1:0]
00
01
10
11
Clock Multiplier
Xl
X2
X3
X4
RFT - Refresh Test Mode. This bit must be clear for proper operation.
4
2
3
BLP[3:0]
0
0
BLK
DFB
0
0
BLK - Number of Blocks. These bits specify the total number of
populated blocks. 0 (H) = 1 block ... 3 (H) = 4 blocks.
DFB - Default Burst Length. This field defines the default burst
length for cache line read/writes. The bus will execute burst transactions with this default length when the appropriate TYPE bit is
asserted during the address phase of a transaction or when an operation is transformed. These bits are interpreted as follows:
DFB[1:0] Default Burst Length
5
4
3
2
00
01
10
11
o
16 Bytes
32 Bytes
64 Bytes
128 Bytes
Command Register 3
Index
7
6
INIT - Initialization. This bit, when set, triggers an initialization
of the DRAM memory and its check bits. The contents of the
memory are set to zero and the corresponding check bits are set.
WC - Write Check Bits. Enables writing of the EDC check bits
from the registers inside the data path.
o Write EDC check word computed from incoming data.
1 Write EDC check word from check bit register.
5
4
3
2
o
RCM - Refresh Control Modes. These bits control refresh and
the DRAM INIT process for test purposes. RCM must be set to
11 for proper operation. When asserted, RCM[O] enables refresh
and RCM[l] enables the INIT process. (The INIT process occurs
after DRAM energizing and fills all DRAM with 0.)
AEM - Address Error Mode. Controls assertion of BERR after
an address parity error.
o BERR asserted for one clock
1
5
BLP - Block Population. These bits define which physical blocks
are populated. BLP[N] = 1 indicates that Block N is populated.
Block population must be contiguous with one exception. BLPO
and BLP2 can be asserted simultaneously with BLP1 and BLP3
de asserted simultaneously when supporting 36- and 40-bit
SIMMS populated with two sections of DRAM memory.
MHz
MHz
39
MHz
49
MHz
Command Register 1
Index
o
I I;~:ltl
7F (h)
25
33
40
50
SBS - System Bus Size. Specifies the number of data bits in the
system bus.
Command Register 2
6
Index
7
0
RFD
24
32
CYM7232
CYM7264
PRELIMINARY
BERR asserted until cleared by writing 1 to ABE in
Interrupt Status register
8-134
·
:~
_·.iECYPRESS
SEMICONDUcrOR
PRELIMINARY
--=-.'
Index Register (continued)
BAM[I:0] - Bus Acknowledge Modes. These bits control the
operating modes for read operations. BAMO controls error
correction. BAM1 controls the insertion of wait states.
BAMO - Error Correction Enable
o
Error correction disabled
1 Error correction enabled
When error correction is disabled, reads as a result of Read
Modify Write operations are not affected. Consequently, singlebit errors in the read portion of RMW cycles are corrected and
merged with the write data. Uncorrectable errors cause the write
back portion of RMW cycles to abort. Read Modify Write transactions are not possible in systems configured without DRAM
check bits.
BAM1 - Wait State Insertion on Reads
o No wait states inserted
1 Wait states inserted
The insertion of wait states allows corrected data to meet minimum set-up requirements in high-speed systems. Wait states
should be inserted for systems requiring greater system bus setup time on reads.
SEN - Scrub Enable. This bit enables scrubbing when asserted
HIGH.
CAM - CAS Assertion Mode
o CAS[3:0] independently asserted.
1 CAS[3:2LQ.Red" to produce CAS2, CAS[1:0] "ORed" to
produce CASO. This mode is provided to support some 36or 40-bit-wide DRAM SIMMs that contain two rows of
memory with independent RAS and common CAS.
RSM - RAS Stagger Mode (during Refresh/Scrub operations).
o RAS[3:0] staggered by one bus clock.
1 RAS[3:0] staggered to be non-overlapping (mutuallyexclusive in time). This mode is provided to support some 36- or
40-bit-wide DRAM SIMMs that contain two rows of
memory with independent RAS and common CAS. The
RAS signals must be mutually exclusive when scrubbing
these SIMMs.
BRM - Bus Request Mode
o Bus arbiter ON. BR/FE assertion indicates reflective FIFO
status only. With bus arbiter ON, BR/FE is deasserted with
the recognition of Bus Grant (BG) and Bus Busy (BB) is asserted after the B~in goes HIGH.
Bus arbiter OFF. BR/FE assertion combines write FIFO
status and reflective FIFO status (logical OR). Both FIFOs
must be empty for the BR/FEoutput to be deasserted. With
the bus arbiter OFF, BG is ignored, the BR/FE output simply reflects the combined FIFO status, and BB acts as an
output signaling the beginning of a read transaction.
Command Register 4
Index
7
6
4
3
2
0
10SWC
F(h)
CYM7232
CYM7264
PLT[I:0] - Phase-Locked Loop Test. This field is for test purposes only. PLT[1:0] should be programmed to 11 when enabling
the internal VCOs, otherwise PLT[1:0] = 00.
veo [1:0] - Voltage Controlled Oscillation Select. This field selects the appropriate VCO for generating the internal multiplied
clock.
00 No VCO selected, use external MCLK
01 70-MHz VCO
10 80-MHz VCO
11 100-MHz VCO
The operating range of the VCOs is given in the following table.
Each VCO requires a minimum of 20 ms to phase lock to the system bus clock after being enabled.
veo (MHz)
Operating Range (MHz)
70
80
65 - 74.9
75 - 84.9
100
95 - 104.9
Ioswe - Snoop Window Count. This value programs the duration of the snoop window for I/O operations in bus clock cycles.
The snoop window counter is enabled one clock after an address
phase on the bus in which the controller is selected. When a 0 is
programmed into the counter the snoop window closes immediately (i.e., the cycle after the address phase). The window can be
extended up to 16 clocks after the address phase appears on the
bus. After power-up the counter defaults to the maximum value.
The internal snoop window is selected by driving UERR appropriately during reset.
Command Register 5
4
3
o
Index
7
6
5
2
I
(J)
W
..J
~
IE - Interrupt Enable. This bit must be set to enable interrupts
to the system bus.
EDP - Enable Data Bus Parity Interrupt. Enables the interrupt
indicating that one of the data bytes has a parity error.
EAP - Enable Address Bus Parity Interrupt. Enables the interrupt indicating that one of the address bytes has a parity error.
EME - Enable Read-Modify-Write Multiple Error Interrupt.
Enables the interrupt indicating that a multiple error has occurred on a read-modify-write cycle.
EVE - Enable Uncorrectable Error in Word Interrupt. Enables
the interrupt indicating that an uncorrectable error has occurred
in a word.
EDE - Enable Double Bit Error in Word Interrupt. Enables the
interrupt indicating that a double bit error has occurred in a 32(64-) bit word.
ESE - Enable Single Bit Error Interrupt. Enables the interrupt
indicating that a single bit correctable error has occurred in a 32(64-) bit word.
Command Register 6
Index
7
6
5
4
320
SNWWRCNT[3:0]
F(h)
8-135
SNWRDCNT[3:0]
F(h)
C
0
:E
:C;1~PRFSS
~,
CYM7232
CYM7264
PRELIMINARY
SEMICONDUcrOR
Index Register (continued)
SNWWRCNT specifies the snoop window duration for memorywrite transactions and SNWRDCNT specifies the snoop window
duration for memory-read transactions. The internal snoop window is used only if selected by driving UERR appropriately during reset. The snoop window counter is enabled one clock after
an address phase on the bus in which the controller is selected.
When a 0 is programmed into the counter, the snoop window
closes immediately (e.g., the cycle after the address phase). the
window can be extended up to 16 clocks after the address phase
appears on the bus. After reset, the counter defaults to the maximum value.
DRAM Timing Program Registers - Write / Read
DRAM Timing Register 0
Index
7
6
5
4
3
2
AR[3:0]
RAM[3:0]
F(h)
F(h)
DRAM Timing Register 1
Index
7
6
5
4
3
2
RAS[3:0]
0
MAC[3:0]
F(h)
DRAM Timing Register 2
Index
7
6
5
0
F(h)
4
3
CP[3:0]
2
DRAM Timing Register 3
Index
7
6
5
4
3
2
0
RIN[3:0]
DC[3:0]
F(h)
F(h)
DRAM Timing Register 4
Index
7
6
5
4
3
2
0
ENW[3:0]
ENR[3:0]
F(h)
F(h)
The DRAM Timing Program registers should not be reprogrammed during operation. The user must reset the part and reprogram all DRAM timing before issuing an INIT.
For optimum performance, DC[3:0] should always be programmed to 0001(b). RIN[3:0] = RAS[3:0] - (RAM[3:0] +
MAC[3:0]).
All timing values are set with 4-bit values. The time intervals are
specified to lO-ns accuracy when the internal clock is running at
100 MHz, 12.5-ns accuracy when the internal clock is running at
80 MHz, 13.3-ns accuracy when the internal clock is running at
75 MHz, or 15.2-ns accuracy when the internal clock is running at
66 MHz. Refer to the timing diagrams for elaboration.
0
RPR[3:0]
F(h)
F(h)
Table 27. DRAM Timing Values
Delay/Width' (ns)
Hex Value
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
66 MHz
15.2
75 MHz
30.3
45.5
60.7
80
91
106
121
13.3
26.6
40
53.3
66.6
80
93.3
106.6
136
152
167
182
197
212
227
242
120
133.3
146.6
160
173.3
186.6
200
213.3
8-136
80 MHz
12.5
25
37.5
50
62.5
75
87.5
100
112.5
125
137.5
150
162.5
175
187.5
200
100 MHz
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
~
i~PRESS
-:::;;;;;;;F
PRELIMINARY
CYM7232
CYM7264
SEMICONDUCTOR
Table 28. DRAM Timing Program[l)
Parameter
Field
Name
tRAM
RAM
Logical Block Displacement Register
Byte Address 12H, LBD[7:0]
Byte Address 13H, LBD[15:8]
15
11 10
8 7
6 5
Description
3 2
o
RAS to multiplexed address
Address to RAS assertion
tAR
AR
tRAS
RAS
RAS pulse width
tMAC
tcp
MAC
Multiplexed address to CAS
CP
CAS pre-charge width
tRPR
RPR
RAS pre-charge width
tRIN
RIN
RAS completion during non-reflective Inhibit
FIFO data delay to CAS
tDC
DC
tENR
ENR
Enable delay on read
tENw
ENW
Enable delay on write
tACC
-
DRAM access time (determine by
DRAM chips)
tCLZ
-
DRAM CAS to Output Low Z (determined by DRAM chips)
tCY
-
Bus CLK period
DS(N) [2:0] - Address Displacement of logical block (N). This
entry specifies the address displacement of logical block (N) from
logical block (N - 1). The starting address of logical block (0) is
the Base address of the memory. The starting address of logical
block (1) is the sum of the Base address and the displacement selected by DS(l). The starting address of logical block (2) is the
sum of the starting address of logical block (1) and the displacement selected by DS(2). The starting address of logical block (3)
is the sum of the starting address of logical block (2) and the displacement selected by DS(3). The programmed displacement,
DS(N), must be equal to or greater than the depth of the memory
chips contained in logical block N -1. When the programmed displacement is equal to the memory chips depth, the memory is
contiguous.
DS(N) [2:0]
Displacement
Note:
000
256K
1.
001
1M
All timings may be resolved to 1/n of tCY, where n is the phase locked
loop multiplier (e.g. 50-MHz systems having a PLL multiplier of2 with
tCY = 20 ns can have DRAM timing resolutions defined to 10 ns).
Therefore, unless the timing values are constrained, the D RAM read
data could arrive at the data path input pipeline on a 10-ns boundary
rather than a bus clock boundary. The controller will automatically extend certain values that are programmed to provide data on a bus clock
boundary, whenever necessary.
DRAM Block Assignment Register Array
Five registers are used to map the incoming address to the four
physical blocks of DRAM. These registers specify the Base address of the DRAM array, the gaps between blocks, the relationship between physical blocks and logical blocks, the size of
memory each block is populated with, and the RAS/CAS address
split point in the DRAMs in each block. The module should be
re-initialized when any of these registers are changed during operation.
The Base Address register, Logical Block Displacement register,
Logical Block Population Code register, and Logical Block MUX
Position register are all 2-byte registers. The Physical/Logical
Block Map register is a I-byte register.
Base Address Register
Byte Address 10H, BA[27:20] (Bits 7:0)
Byte Address llH, BA[35:28] (Bits 15:8)
15
8 7
0
BAO[35:28]
BAO[27:20]
OOH
OOH
BA[35:20] - Base Address of Memory. This entry specifies the
base address of the memory. The base address must be evenly divisible by the depth of the largest DRAM device used multiplied
by 16. For example, if the largest DRAM device used is 1M deep,
then the smallest base address (other than 0) is BA = 0010 (h);
BA[23:20] must be O.
8-137
010
4M
011
16M
100
32M
101
64M
110
128M
111
256M
I
tn
W
.J
:::)
C
0
::E
/
=? :~~~
,
CYM7232
CYM7264
PRELIMINARY
SEMICONDUCTOR
LBMP(N)[2:0] specifies the DRAM column address/row address
split for logical block (N). The split is specified in terms of the
address applied to the DRAM. Note that bus address 4 is DRAM
column address o. All twelve DRAM address bits are valid for all
split selections.
15
12
11
10
9
8
LPC(N) [1:0] - Logical Block Population Code. LPC(N)[1:0]
specifies the DRAM type in logical block (N).
LBMP(N) [2:0]
Row/Column Address Split Location
000
8/7
001
9/8
010
10/9
011
11/10
100
12/11
101
unused
LPC(N) [1:0]
DRAM Depth
110
unused
11
16M
111
unused
10
4M
01
1M
Error Location Register - Read Only
256K
00
The physical blocks may be configured in any order. To obtain a
contiguous memory with no overlaps or gaps, the logical blocks
must be populated in order with the largest DRAM type in logical block 0, followed by the next largest DRAM type in logical
block 1, etc., and the logical block populations must be contiguous (no unpopulated logical blocks between populated blocks).
LBP(N) specifies whether or not the block is populated. LBP(N)
= 0 block not populated. LBP(N) = 1 block populated.
The Error Location register is a 32 bit register that contains the
address of the most recent error. This register is read only and is
byte addressable only. All bytes appear on D[7:0]. Byte addresses
are as follows:
20H ELA[7:0]
21H ELA[15:8]
22H ELA[23:16]
23H ELA[31:24]
Error Location Address [31:0J
o
31
ELA[31:0]
OOH
PBL(N) [1:0] - Physical Block Association. PBL(N)[1:0] specifies the logical block to which physical block N is mapped.
The Error Location Address register reports the address location
of an error in the DRAM and how the error occurred. When the
error ocurs during a read operation the ELA register reports the
address as it appeared on the system bus and the physical block
wherer the system bus address is mapped. When the error occurs
during a refresh, or scrub, operation the ELA reports the physical
block and address in row/column format.
PBL(N) [1:0]
Association
00
Logical Block 0
Read Error Location Register Format
01
Logical Block 1
10
Logical Block 2
11
Logical Block 3
ELA[31:30]
ELA[29:28]
ELA[27:4]
ELA[3:0]
Physical Block in DRAM
00 (Reports Read Error)
System Bus Address A[27:4]
0
Refresh/Scrub Error Location Register Format
LBMP1[2:0]
OOH
15
14
13
11
LBMP3[2:0]
OOH
10
8
ELA[31:30] Physical Block in DRAM
ELA[29:28] 01 (Reports Ref. Error)
ELA[27:16] DRAM Row Address
ELA[15:4]
DRAM Column Address
ELA[3:0]
0
After a system bus read error, diagnostic software will translate
the system bus address to the row/column address inside the
DRAM. This. mapping will depend on the DRAM configuration.
When the error occurs during refresh, or scrub, diagnostic software will extract the meaningful portion of the row/culumn address (from the reported row/column address) based on the
DRAM population of the particular physical block in error. The
8-138
--.-
:~
CYM7232
CYM7264
PRELIMINARY
~=CYPRESS
~JF SEMICONDUCIOR
Error Location Register - Read Only (continued)
DRAM array is always refreshed as if populated with 16-Megabit
DRAMs in all blocks. Therefore higher order row and column
address bits in the internal refresh counter will increment even
when they are not required to span the address space within a
block. These redundant bits must be ignored in calculating the
location of an error which occurred during refresh.
The ELA register is constantly updated with the address of the
current transaction. If an error is detected in the read from
DRAM, further writing to this register is locked out until the interrupt bit is cleared. (If two successive transactions incur errors
and the interrupt bit is not cleared before the address phase of
the second transaction, the address of the second error is lost.)
Error Status Registers - CYM7232
The Error Status registers provide information on errors that
have occurred during any read operation (including scrubbing
and read modify write). The location of these registers on the
data bus will depend on the system bus configuration (32 or 64
bits). Table 29 shows the location of data path registers for the
64-bit system bus.Table 30 shows the location of the same registers in the 32-bit system bus application.
Table 29. Error Status Register Map for CYM7232 with 64-Bit System Bus
Index
Name
24H
2SH
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
EDC Register 0
EDC Register 1
Reserved
Reserved
Syndrome FIFO Flags 0
Syndrome FIFO Flags 1
Reserved
Reserved
Diagnostic Check Bit 0
Diagnostic Check Bit 1
Reserved
Reserved
R/W
R
R
63:56
R
R
CB3
55:48
CB1
47:40
SYN3
39:32
31:24
23:16
CB2
CBO
15:8
7:0
SYN2 SYNO
SYN1
FLO
FLl
W
DCBO
DCB1
W
I
tJ)
W
...I
::::)
Q
o
=e
8-139
#::~CYPRESS
~~
CYM7232
CYM7264
PRELIMINARY
~, SEMICONDUcrOR
Table 30. Error Status Register Map for CYM7232 with 32·Bit System Bus
Index
Name
24H
25H
26H
27H
28H
29H
2AH
2BH
EDC Register 0
EDC Register 1
Reserved
Reserved
Syndrome FIFO Flags 0
Syndrome FIFO Flags 1
Reserved
Reserved
Diagnostic Check Bit 0
Diagnostic Check Bit 1
Reserved
Reserved
2CH
2DH
2EH
2FH
RIW
31:24
23:16
15:8
7:0
R
R
CB2
CB3
CBO
CB1
SYN2
SYN3
SYNO
SYN1
R
R
FLO
FLl
W
W
DCBO
DCB1
EDe Registers
The EDC Registers contain the Read Error Log FIFO and
Check Bits fields. The registers are Read Only. The register at
address 24 appears on D[31:0] and the register at address 25 appears on D[63:32] when the module is connected a 64 bit system
bus. For 32 bit systems, both registers appear on D[31:0].
EDC Register 0
Index
31 30
24 23 22
8 7
16 15 14
o
6
CB2
CBO
SYN2
SYNO
OOH
OOH
Undefined
Undefined
EDC Register 1
Index
31 30
24 23 22
8 7
16 15 14
o
6
CB3
CB1
SYN3
SYN1
OOH
OOH
Undefined
Undefined
This register will appear on D[63:32] of the 64-bit system bus.
When used in a 32-bit system bus application, this register will
appear on D[31:0].
SYNO, SYNl, SYN2, SYN3 - Syndrome Bits. These bits originate
from the outputs of the syndrome FIFO. They reflect the EDC
syndrome bits on any memory read error condition (including
reads, read bursts, scrubs, and read modify writes). The syndrome
outputs contain valid information whenever the FIFO Flag register's corresponding status bits indicate that the FIFOs are not
empty. SYNO contains the syndrome values for errors in DRAM
Bank O. SYN1 contains the syndrome values for errors in DRAM
Bank 1, and so forth.
CBO, CBl, CB2, CB3 - Check Bits. These bits reflect the EDC
check bits that were present during the previous read operation.
CBO contains the check bits from DRAM Bank 0 for the most recent read. CB1 contains the check bits from DRAM Bank1 for
the most recent read and so forth.
Syndrome FIFO Flag Registers
Syndrome FIFO flag register 0 (32- & 64-bit system bus)
The Syndrome FIFO Flag registers contain the full/empty status
of the syndrome FIFOs. The registers are read only (byte addressable only). When the module is used in a 64-bit bus system
the register at address 28 appears on D[7:0] and the register at
address 29 appears on D[39:32]. In 32-bit system bus operation
the register at address 29 will appear on D[7:0].
ESFO, ESFl, ESF2, ESF3 - Syndrome FIFO Empty Flags. These
bits reflect the EDC syndrome FIFO empty status. When set to
1, these bits indicate that the associated FIFO is empty. ESFO re-
Index
7
6
5
4
3
2
1
o
33
32
Reserved
OOH
Syndrome FIFO flag register 1 (64-bit system bus)
Index
39
38
37
36
35
34
Reserved
OOH
Syndrome FIFO flag register 1 (32-bit system bus)
Index
7
6
5
4
3
2
o
Reserved
OOH
flects the status of FIFO 0 which storcs the syndrome values from
DRAM Bank O. ESF1 reflects the status of FIFO 1 which stores
the syndrome values form DRAM Bank 1 and so forth.
8-140
R7
·
~
--=-,
PRELIMINARY
ij; CYPRESS
CYM7232
CYM7264
SEMICONDUcrOR
FSFO, FSFl, FSF2, FSF3 - Syndrome FIFO Full Flags. These
bits reflect the EDC syndrome FIFO full status. When set to 1,
these bits indicate that the associated FIFO is full. FSFO reflects
the status of FIFO 0, which stores the syndrome values form
DRAM Bank O. FSF1 reflects the status of FIFO 1, which stores
the syndrome values from DRAM Bank 1 and so forth.
Diagnostic Check Bit Registers
Diagnostic Check Bit Register 0 (32- & 64-bit system bus)
Index
7
6
5
4
3
2
1
o
Diagnostic Check Bit Register 1 (64-bit system bus)
Index
39
38
37
36
35
34
32
33
DCB1
Diagnostic Check Bit Register 1 (32-bit system bus)
Index
7
6
5
4
3
2
o
DCBO, DCBl: Check Bit Register - Write only. These bits can
be written to override the check bits generated by the write polynomial generator. In a 64-bit system bus configuration, the register at address 2C appears on D[7:0] and the register at address
2D appears on D[39:32]. When used in a 32-bit system bus, the
register at address 2D will appear on D[7:0]. Data written into
Diagnostic Check Bit register 0 will write into the check bits for
DRAM Banks 0 and 2. Data written into Diagnostic Check Bit
register 1 will write into the check bits for DRAM Banks 1 and 3.
The selection to use EDC computed from the write data or use
the EDC as contained in this register is determined by bit WC in
the Command register 1.
OOH
Error Status Registers - CYM7264
Table 31. Data Path Register Map for CYM7264
Index
Name
24H
EDC Register 0
25H
EDC Register 1
26H
Reserved
R/W
R
R
27H
Reserved
28H
29H
2AH
Syndrome FIFO Flags 0
Syndrome FIFO Flags 1
2BH
31:24
23:16
15:8
7:0
CBO
SYNO
CB1
SYN1
R
R
I
FLO
FLl
tJ)
Reserved
2CH
Reserved
Diagnostic Check Bit 0
2DH
2EH
Diagnostic Check Bit 1
Reserved
2FH
Reserved
W
DCBO
W
.J
:::l
W
DCB1
o
C
::a:
EDC Registers
The EDC Registers contain the Read Error Log FIFO and
Check Bits fields. The registers are Read Only. These registers
will appear in D[31:0] of the system data bus as shown in
Table 31.
EDC Register 0
Index
31
24 23
Undefined
EDC Register 1
Index
31
SYNO
OOH
Undefined
Undefined
2423
16 15
o
8 7
SYN1
CB1
Undefined
o
8 7
16 15
CBO
OOH
Undefined
SYNO, SYNI - Syndrome Bits. These bits reflect the EDC syndrome bits on an error condition. SYNO contains the syndrome
values for errors in DRAM Bank O. SYN1 contains the syndrome
values for errors in DRAM Bank 1.
Undefined
CBO, CBl - Check Bits. These bits reflect the EDC check bits
that were present during the previous read operation. CBO contains the check bits read from DRAM Bank O. CB1 contains the
check bits read from DRAM Bank 1.
8-141
':~PRFSS
CYM7232
CYM7264
PRELIMINARY
_ , SEMICONDUcrOR
BEC - Clear Data Bus Error. This bit, when asserted, clears
BERR when MBE (above) is set.
There are two BERR registers in the CYM7232 and two in the
CYM7264. These locations on the data bus depend on the bus
configuration as follows:
Syndrome FIFO Flag Registers
Syndrome FIFO Flag Register 0
Index
7
6
5
4
3
2
o
Reserved
CYM7232
32-Bit Bus mode - Registers programmed simultaneously at
D[7:0]
64-Bit Bus mode - Registers located at D[39:32], D[7:0]
OlH
Syndrome FIFO Flag Register 1
Index
7
6
5
4
3
2
o
CYM7264
64-Bit Bus mode - Registers programmed simultaneously at
D[7:0]
All registers appear at the same address, 31H.
Reserved
01H
ESFO, ESFl - Syndrome FIFO Empty Flags. These bits reflect
the EDC syndrome FIFO Empty status. When set to 1, these bits
indicate that the associated FIFO is empty. ESFO is the flag for
Syndrome FIFO 0 and ESF1 is the flag for Syndrome FIFO 1.
FSFO, FSFl - Syndrome FIFO Full Flags. These bits reflect the
EDC syndrome FIFO full status. When set to 1, these bits indicate that the associated FIFO is full. FSFO is the flag for Syndrome FIFO 0 and FSF1 is the flag for Syndrome FIFO 1.
Diagnostic Check Bit Registers
Diagnostic Check Bit Register 0
Index
7
6
5
b~~,:tl
4
3
2
OOH
7
6
5
~~~:tl
4
3
2
o
DCB1
OOH
130H
6
5
4
3
I
2
0
REV[3:0]
REV[3:0] - Silicon Revision. This field gives the revision number of the module's address controller chip.
BERR Control Register - Write Only
Index
131H
7
6
5
4
6
5
4
3
2
o
IC - Initialization Complete. This bit indicates initialization of
the DRAM is complete.
DBE - Data Parity Error. This bit indicates that a data bus parity
error has occurred over the system bus.
3
DEW - Double Error in a Word. This bit indicates that a double
bit error has occurred in a 32- (64-)bit word.
SBW - Single Correctable Error. This bit indicates that a single
correctable error has occurred in a 32- (64-) bit word.
Interrupt Status register bits ISR[6:0] are latched. Interrupts[5:0]
can be cleared individually by writing the register with the desired
bit high. Otherwise those status bits remain indefinitely, or until
RSTIN is asserted LOW.
Special Characteristics of I/O Registers
Silicon Revision Code - Read Only
7
7
MEW - Multiple Errors in a Read-Modify-Write. This bit indicates that multiple errors have occurred during a read-modifywrite operation.
UEW - Uncorrectable Error in a Word. This bit indicates that an
uncorrectable error has occurred in a 32- (64-) bit word.
DCBO, DCBl - Check Bit Register. These bits can be written to
override the check bits generated by the write polynomial register. Data in DCBO is written to DRAM Bank 0 and data in DCB1
is written to DRAM Bank 1. The selection to use EpC computed
from the write data or use the EDC as contained in this register is
determined by bit WC in the Command register Byte 1.
Index
Index
ABE - Address Parity Error. This bit indicates that an address
bus parity error has occurred over the system bus.
DCBO
Diagnostic Check Bit Register 1
Index
o
Interrupt Status Register
The two EDC registers can be accessed with 32-bit reads over the
system bus. All other I/O registers must be accessed by reading or
writing a single byte at the address location shown. That byte will
always be located at the lowest 8 bits of the system's data bus
(D[7:0D. Programming registers are read/write for diagnostic
purposes. These register's address locations are separated by 16
bytes to support wide system data paths.
Syndrome Decoding
210
I
This register controls operation of the BERR output for data
parity errors.
BEM - Data Bus Error Mode. When BEM is set, BERR remains asserted till explicitly cleared (when reporting data parity
errors). Otherwise BERR is asserted for one clock only.
The following tables give the decoding for the syndrome values
for the 32- and 64-bit error detection and correction algorithms.
Table 32 gives the syndrome decoding for the 32-bit error-detection and correction algorithm. Table 33 gives the syndrome decoding for the 64 bit error detection and correction algorithm. In
these two tables, U indicates a multiple (greater than 2) bit uncorrectable error, D indicates a double bit error, nm indicates an
error in data bit nm, Cn indicates an error in check bit n, and N
indicates no error.
8-142
CYM7232
CYM7264
~
==:::-
~
---=-.IFiJE
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Table 32. Syndrome Decoding, 32-bit EDC
S6
SS
S4
S[3:0]
0
0
0
0000
U
0001
D
0010
D
0011
0100
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
D
0
D
U
U
U
U
D
U
D
D
16
29
7
D
U
D
D
U
U
D
D
U
D
13
23
D
D
28
6
D
U
D
D
17
0101
U
D
D
1
D
12
22
D
0110
U
D
D
U
D
11
21
D
0111
D
27
5
D
U
D
D
C3
1000
D
26
4
D
U
D
D
U
1001
U
D
D
U
D
10
20
D
1010
31
D
D
U
D
9
19
D
1011
D
25
3
D
15
D
D
C2
1100
U
D
D
U
D
8
18
D
1101
D
24
2
D
U
D
D
C1
1110
D
U
U
D
14
D
D
CO
1111
30
D
D
C6
D
C5
C4
N
D
D
I
Table 33. Syndrome Decoding, 64-bit EDC
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
1
C6
D
D
62
C7
D
D
46
D
U
U
D
14
D
U
U
D
D
U
U
D
U
D
D
30
U
D
34
56
D
D
50
40
D
U
D
D
U
S7
S6
SS
S4
S[3:0]
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0000
N
C4
C5
D
0001
CO
D
D
0010
C1
D
D
1
0
0
1
1
1
1
1
0011
D
18
8
D
U
D
D
U
U
D
D
U
D
2
24
D
0100
C2
D
D
15
D
35
57
D
D
51
41
D
U
D
D
31
0101
D
19
9
D
U
D
D
63
U
D
D
47
D
3
25
D
0110
D
20
10
D
U
D
D
U
U
D
D
U
D
4
26
D
0111
U
D
D
U
D
36
58
D
D
52
42
D
U
D
D
U
1000
C3
D
D
U
D
37
59
D
D
53
43
D
U
D
D
U
1001
D
21
11
D
U
D
D
U
U
D
D
U
D
5
27
D
1010
D
33
D
D
U
49
D
D
U
D
6
28
D
54
44
D
1
D
D
U
D
D
22
12
1011
17
D
D
U
D
38
60
D
D
1100
D
23
13
D
U
D
D
U
U
D
D
U
D
7
29
1101
U
D
D
U
D
39
61
D
D
55
45
D
U
D
D
U
1110
16
D
D
U
D
U
U
D
D
U
U
D
0
D
D
U
1111
D
U
U
D
32
D
D
U
48
D
D
U
D
U
U
D
8-143
tn
W
..J
:;)
Q
o
::aE
L~PRFSS
~,
PRELIMINARY
CYM7232
CYM7264
SEMICONDUCTOR
MBus Operation
Bus Transactions General Description
System transactions follow the MBus specification January 31st,
1991, Revision 1.2 (Review draft) including Level 2. Only those
functions required of a main memory system are implemented.
The generic interface is an extension of the MBus specification
adapted to a variety of processors. The descriptions of the generic
interface are therefore applicable to MBus applications. The intent of this section is not to repeat the MBus specification but to
identify those operating characteristics and functions which are
invoked with the MBus mode selection.
Module Connections
The SPARC MBus is an address/data multiplexed bus therefore,
the address and data pins of the module must be wired together.
The controller accommodates the multiplexed bus by storing the
address and control information that is presented during the address phase allowing the data on the address pins to change after
the de assertion of the address strobe. The module connections to
MBus are given in the following tables. Note that some module
pins are tied together to the MBus connection. Other connections must be permanently tied to a HIGH or LOW level.
During reset, BACK[1:0] and UERR must be driven to invoke
the proper MBus modes. The snoop window source can originate
internally. To make these selections, UERR and BACK[1:0] must
be driven to binary 100 during Reset. Refer to Table 18 and
Table 19.
Bus Interface Signal Description
The bus interface signal descriptions are identical to that given in
the generic descriptions except for some minor variations and nomenclature. This section will present only those differences and
highlight the nomenclature equivalences.
Transaction· Specific Control
Transaction specific control information is contained in fields
within the address as specified by MBus. These fields are given in
Table 36.
Table 36. Multiplexed Bus Address Subtields
Signal Name
A[35:0]
TYPE[3:0]
SIZE[2:0]
Table 34. MBus Signal Translation
Controller
CLK
D[63:0]
A[35:0]
TYPE[3:0]
SIZE[2:0]
AS
BACK[l]
INH
BR
BG
BB
ID[3:0]
BERR (Optional)
RSTIN
INT
UERR
MBus
CLK
MAD[63:0]
MAD[35:0]
MAD[39:36]
MAD[42:40]
MAS
MRDY
MIH
MBR
MBG
MBB
ID[3:0]
AERR
RSTIN
INTOUT
MERR
MBus
o(MBus mode)
o(Ignored)
0
0
1
1
(Optional)
Tied high for non-reflective
memory
Tied to INH for reflective
memory
Description
Physical Address
Transaction Type
Transaction Data Size
Reserved
Parity
Parity is not defined for MBus, however, the controller retains
the capability to generate and check parity when configured for
MBus.
TYPE[2:0]: Transaction 1Ype
During the address phase, TYPE[2:0] specify the transaction
type. TYPE[2:0] are multiplexed bus signals and are directly
MBus compatible. The module fully responds to Write, Read,
Coherent Read, Coherent Write and Invalidate, and Coherent
Read and Invalidate. The response to Coherent Invalidate cycles
is programmable. If the Coherent Invalidate Acknowledge Enable in the Command register is 0, the module makes no response to these cycles. This is the default condition after reset ..If
the Coherent Invalidate Acknowledge Enable in the Command
register is 1, the module asserts MRDY for Coherent Invalidate
cycles but, otherwise, plays no role in the transaction.
Table 37. Transaction 'JYpes
Data Size
Transaction Site
0
0
1
1
0
0
0
1
0
1
0
Any
Any
32 Bytes
32 Bytes
Any
0
1
32 Bytes
Write
Read
Coherent Invalidate
Coherent Read
Coherent Write & Invalidate
Coherent Read & Invalidate
Reserved
1YPe
Table 35. Extra Signals in MBus
Controller
IMD
TYPE[5:4]
SIZE[7:3]
DS
BLST
TSTE
PMD[2:0]
TRC
Physical
Signal
MAD[35:0]
MAD[39:36]
MAD[42:40]
MAD[63:43]
2
0
0
0
0
1
1
1
All Other Combinations
TYPE[2:0]: Transaction Size
During the address phase, SIZE[2:0] specify the number of bytes
to be transferred during the data phase of the bus transaction.
SIZE[2:0] are multiplexed bus signals and are directly MBus
compatible.
8-144
~~PRFSS
-=iif!!!IIT' SEMICONDUCTOR
PRELIMINARY
BG - Bus Grant. This signal is asserted by the external arbiter in
response to a BR, to indicate that the controller has been granted
ownership of the bus.
BB - Bus Busy. This signal is asserted by the controller for the
duration of its bus ownership. The controller will require the bus
as it completes the main memory write transaction during reflective read operations.
ID[3:0] - Identification. The ID field selects various configuration spaces within the MBus address space for access to the Port
register and other I/O registers.
Table 38. Size Transaction
Size2
0
0
0
0
1
1
1
1
Sizel
0
0
1
1
0
0
1
1
SizeO
0
1
0
1
0
1
0
1
Transaction Size
Byte
Halfword (2 Bytes)
Word (4 Bytes)
Doubleword (8 Bytes)
16-Byte Burst
32-Byte Burst
64-Byte Burst
128-Byte Burst
Table 42. ID [3:0] Mapping
MBus CONFIGURATION SPACE
ID[3:0]
F/FOOO/OOO H to F/FOFF/FFFF H
oH reserved for boot
Table 39. Address Interpretation in Byte Mode (Size [2:0] =0)
A2
0
0
0
0
1
1
1
1
Al
0
0
1
1
0
0
1
1
AO
0
1
0
1
0
1
0
1
Byte#
0
1
2
3
4
5
6
7
Bits
D[63:56]
D[55:48]
D[47:40]
D[39:32]
D[31:24]
D[23:16]
D[15:8]
D[7:0]
Al
AO
Halfword#
Bits
0
X
1
X
0
1
D[63:48]
D[47:32]
0
X
2
D[31:16]
1
X
3
D[15:0]
Table 41. Address Interpretation in Word Mode (Size [2:0] =2)
A2
0
1
Al
AO
Word#
Bits
X
X
0
D[63:32]
X
X
1
D[31:0]
F/F100/0000 H to F/F1FF/FFFF H
PROM
1H
F/FnOO/OOOO H to F/FnOO/OOOO H
nH
F /FEOO/OOOO H to F/FEFF/FFFF H
F/FFOO/OOOO H to F/FFFF/FFFF H
EH
FH
Internal Registers
Table 40. Address Interpretation in Halfword mode
(Size[2:0] =1)
A2
0
0
1
1
CYM7232
CYM7264
BR/FE - Bus Request. This signal will be issued by the controller
during reflective read transactions. BR from the main memory
system should be interpreted as the highest priority request for
bus mastership to the system's arbiter. Additional system bus
transactions will be prevented until the ongoing write (resulting
from the reflective read) to main memory has completed. (The
original MBus specification has no explicit mechanism for reflective main memories to postpone the next bus transaction while
the data being transferred between two caches is simultaneously
written to DRAM.)
In the MBus mode, The BRM bit in Command register 3 should
be programmed 0 to enable the bus request handshaking. When
this is done, BR is de asserted~on the recognition of BG and is
followed by the assertion of BB. BB remains asserted until the
Reflective FIFO is empty.
Several internal registers are available to set up the DRAM controller and report status to the host. The register's individual bits
are defined in the sections describing the generic mode of operation. The registers appear on the MBus exactly as they would in
the 64-bit bus generic mode, big-end ian operation.
When the MBus mode is invoked, the MBus Port register becomes accessible. Its form, content, and address are defined below. In addition, the Command register 0 contains a control bit
specific to MBus operation. This control bit affects the controllers response to MBus coherent invalidate cycles. Addressing of
the internal registers is direct in the MBus mode and therefore
the index register is not used. The address of each register has the
form (in hexadecimal)
FFnxxOmpx
where n is a nibble that is compared to the input on the ID pins, x
is a don't care condition, and mp are the two nibbles of the indexed address as given in the register descriptions. For example,
if ID[3:0] is A H, then the MBus address for the BERR Register
is FFAxx031x H.
MBus Port Register - 2 Bytes - Read Only
Address 7
6
1:::,1
Address 15
1=;,1
14
5
4
3
o
2
MR
MV
OH
1H
13
12
11
10
9
8
MD
OOH orOl H
MV[3:0] - Vendor Code. This specifies the vendor code for
MBus compatible devices - 1 H for Cypress Semiconductor.
8-145
I
CJ)
W
..J
:::)
0
0
:E
A£:~
PRELIMINARY
~, ~~NDUcrOR
Internal Registers
Maximum Ratings
(continued)
MR[3:0] - Revision Number. This specifies the revision level for
MBus compatible devices - 0 H.
MD[7:0] - Device Number. This specifies a unique number that
indicates the vendor specific MBus device present at this port.
OOH CYM7232
01H CYM7264
MP[31:16] - Reserved for later use.
Specific Programming
For MBus, there will be specific register programming to configure the controller for MBus operation. For convenience, specific
fields are listed below along with the load value appropriate to
MBus. There are other programming selections that must be
made which are dependent upon the specific application.
VCO[I:0]
SBS
10
CYM7232
CYM7264
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 40°C to +125°C
Supply Voltage ........................ - O.3V to +7.0V
Input Voltage .................... - 3.OV to Vee + O.3V
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to Vee Volts
Operating Range
Range
Commercial
Ambient
Temperature
Vee
5V±5%
O°C to +70°C
80-MHz DRAM Clock
64-Bit System Bus
Timing
Bus timing diagrams reflect generic applications, however they
are applicable to MBus. All of the diagrams must be interpreted
for data strobe, DS, permanently asserted.
Electrical Characteristics Over the Operating Range
CYM7232
CYM7264
Parameter
Description
Test Conditions
Min.
Max.
4.75
5.25
V
0
70
°C
Vee
Supply Voltage
TAMB
Ambient Temperature
Commercial
VOHI
Output HIGH Voltage Type 1
Vee
2.4
VOH2
Output HIGH Voltage Type 2
IOH2
2.4
VaLl
Output LOW Voltage 1Ype 1
VOH2
Output LOW Voltage 'JYpe 2
VIR
Input HIGH Voltage
VIL
Input LOW Voltage
lIN
Input Leakage Current
lOUT
Output Leakage Current
Ice
Operating Current
= Min., IOHl = - 8.0 rnA
= -12 rnA
Vee = Min., lOlL = 8.0 rnA
IOH2 = 12 rnA
Unit
V
V
0.4
2.4
-0.3
= Max., 0 ~ VIN ~ Vss
Vee = Max., Vss~ VOUT ~ Vee
Outputs Open, f = fMAX
Vee
V
0.4
V
Vee+ O.3
V
0.8
V
+10
!lA
+10
!lA
300
rnA
Capacitance
Parameter
Description
C
Capacitance, In, Out, I/O
CLK
Capacitance, Input
CBERR, CUERR
Capacitance
Test Conditions
TA = 25°C, f
Vee = 5.0V
= 1 MHz,
Max.
pF
30
pF
pF
30
8-146
Unit
20
CYM7232
CYM7264
~
~ :~PRESS
_?
PRELIMINARY
SEMICONDUcrOR
DC drive of 12 rnA. MBus modules are tested with 100-pF loads
to guarantee compatibility with the MBus specification.
Output Signals by 1Ype
Output
Description
Data and Data Parity Holding Buffers
BACK[l]
Type 2
The system bus data and data parity pins are equipped with holding buffers. These buffers use a weak feedback buffer combined
with the input buffer to form a latch. The latch holds the last value driven on the bus.
Holding Buffer DC Characteristics
BERR
Type 1
BR/FE
Type 2
BB
Type 2
INT, UERR
Type 1
RAS[3:0]
Type 2
CAS[3:0]
Type 2
ADRS[11:0]
Type 2
DDA, DDB, DDC, DDD
Type 1
EDA, EDB, EDC, EDD
Type 1
R/W[3:0]
Type 1
DP[7:0]
Type 1
D[63:0]
Type 1
Holding 0
VIN = OAV
lIN
= 160 f1A (Max.)
45 f1A(Min.)
Holding 1
VIN = 2AV
lIN = - 715 f1A (Max.)
- 175 f1A (Min.)
Flipping Current
Holding 0
VIN = 2.0V
VIN = 2AV
Holding 1
VIN = 0.8V
VIN = OAV
hN = 565 f1A (Max.)
lIN = 630 f1A (Max.)
lIN = - 725 f1A (Max.)
lIN = - 730 f1A (Max.)
Type 1 outputs are designed to drive 50-pF loads with a DC drive
of 8 rnA. Type 2 outputs are designed to drive 50-pF loads with a
AC Test Loads and Waveforms
ALL INPUT PULSES
Output 1Ype 1
446.1l
OUTP~~ ~
,:,~~"PFI
INCLUDING J
JIG AND
SCOPE
OUTP~~ ~
_
1174.1l
-
3.0V----
446.1l
-
'n,~~:Fl
INCLUDING J
JIG AND
SCOPE
(a)
GND
.5. 5 ns
_
-
..J
:)
-
M7232-6
(b)
296.1l
5V~
I
5V~
OUTPUT
OUTPUT
100 pF
--
J.
1150,
50 pF
= 115<1
(d)
THEVENIN EQUIVALENT
125.1l
Type 1
OUTPUT ~ 1.40V
83.1l
OUTPUT~ 1.40V
M7232- 5
8-147
C
o
:E
I
Equivalent to:
296.1l
(/)
W
1174.1l
Output 1Ype 2
(c)
I
90%
Type 2
':iapRFSS
:::::&,
CYM7232
CYM7264
PRELIMINARY
SEMICONDUCTOR
AC Timing Characteristics
40/80 MHz
Description
33/66 MHz
25/75 MHz
Min.
Max.
Min.
Max.
Min.
Max.
Unit
D[63:0], DP[7:0] Output Delay
7
18.5
9
21.5
11
23.5
ns
D[63:0], DP[7:0] Output Hold
3
3.5
3.5
D[63:0], DP[7:0] Input Set-Up
4
5
7
ns
2.5
2.5
2.5
ns
D[63:0], DP[7:0] Input Hold
A[35:0], AP[3:0] Input Set-Up
ns
4
5
7
ns
2.5
2.5
2.5
ns
4
5
7
ns
TYPE[5:0] Input Hold
2.5
2.5
2.5
ns
SIZE[7:0] Input Set-Up
4
5
7
ns
SIZE[7:0] Input Hold
2.5
2.5
2.5
ns
ID[3:0] Input Set-Up
4
5
7
ns
2.5
2.5
2.5
ns
4
5
7
ns
2.5
2.5
2.5
ns
4
5
7
ns
2.5
2.5
2.5
ns
4
5
7
ns
2.5
2.5
2.5
ns
4
5
7
ns
2.5
2.5
2.5
ns
4
5
7
ns
TRCHold
2.5
2.5
2.5
ns
BG Set-Up
4
5
7
ns
A[35:0], AP[3:0] Input Hold
TYPE[5:0] Input Set-Up
ID[3:0] Input Hold
AS Set-Up
AS Hold
DS Set-Up
DSHold
INH Set-Up
INHHold
SNWSet-Up
SNWHold
TRCSet-Up
BGHold
2.5
BR/FE Output Delay
2.5
2.5
17.5
7
9
ns
11
20.5
22.5
ns
BR/FE Output Hold
3
BB Output Delay
10
BB Output Hold
3
3.5
3.5
BB Input Set-Up
4
5
7
ns
BB Input Hold
2.5
2.5
2.5
ns
IMD Input Set-Up
10.5
13.5
16.5
ns
3.5
17.5
3.5
12
20.5
ns
14
22.5
ns
ns
IMD Input Hold
2.5
2.5
2.5
ns
RSTIN Input Set-Up
10.5
13.5
16.5
ns
RSTIN Input Hold
5
5
5
INT Output Delay
7
INT Output Hold
3
BERR Output Delay
7
I
8-148
18.5
9
3.5
I
18.5
I
9
ns
11
21.5
23.5
ns
23.5
ns
3.5
I
21.5
I
11
ns
I
I
I
CYM7232
CYM7264
~
~
;aPRESS
=::::::;;.,
PRELIMINARY
SEMlCONDUCIOR
AC Timing Characteristics (continued)
40/80 MHz
Description
Min.
Max.
33/66 MHz
Min.
Max.
25/75 MHz
Min.
Max.
Unit
BERR Output Hold
3
3.5
3.5
ns
TSTE Input Set-Up
10.5
13.5
16.5
ns
TSTE Input Hold
3
3
3
ns
,TSTM Input Set-Up
10.5
13.5
16.5
ns
TSTM Input Hold
3
UERR Output Delay
7
UERR Output Hold
3
3.5
3.5
ns
UERR Input Set-Up
7.5
10.5
13.5
ns
UERR Input Hold
2.5
2.5
2.5
ns
4
5
7
ns
2.5
2.5
2.5
BACKO Input Set-Up
BACKO Input Hold
9
17.5
BACKO Output Delay (MBus)
BACKO Output Hold (MBus)
3
BACK1 Output Delay (Real Time)
9
3
3
17.5
20.5
20.5
3.5
17.5
11
11
ns
22.5
ns
22.5
ns
22.5
ns
3.5
20.5
13
ns
ns
BACK1 Output Hold (Real Time)
3
3.5
3.5
ns
BACK1 Input Set-Up
4
5
7
ns
BACK1 Input Hold
2.5
BACK1 Output Delay (Early)
11
BACK1 Output Hold (Early)
3
3.5
3.5
ns
BLST Input Set-Up
4
5
7
ns
2.5
2.5
2.5
ns
Ien
ns
..J
BLST Input Hold
ADRS[11:0] Output Delay
7
ADRS[11:0] Output Hold
3
RAS[3:0] Output Delay
7
RAS[3:0] Output Hold
3
CAS[3:0] Output Delay
7
CAS[3:0] Output Hold
3
R/W[3:0]/[1:0] Output Delay
7
2.5
21
16
13
9
2.5
24
18
3.5
16
9
9
11
ns
26
21
3.5
18
3.5
16
15
11
ns
21
3.5
18
3.5
11
ns
ns
ns
21
ns
ns
3.5
ns
17.5
9
20.5
11
23.5
17.5
9
20.5
11
23.5
R/W[3:0]/[1:0] Output Hold
3
DDA[31:0], DDB[31:0], DDC[31:0], DDD[31:0] Output Delay
7
DDA[31:0], DDB[31:0], DDC[31:0], DDD[31:0] Output Hold
1
3
3
ns
DDA[31:0], DDB[31:0], DDC[31:0], DDD[31:0] Input Set-Up
4
5
7
ns
DDA[31:0], DDB[31:0], DDC[31:0], DDD[31:0] Intput Hold
2.5
2.5
2.5
EDA[6:0], EDB[6:0], EDC[6:0], EDD[6:0] Output Delay
7
ns
17.5
9
20.5
11
ns
ns
23.5
ns
EDA[6:0], EDB[6:0], EDC[6:0], EDD[6:0] Output Hold
1
3
3
ns
EDA[6:0], EDB[6:0], EDC[6:0], EDD[6:0] InputSet-Up
4
5
7
ns
EDA[6:0], EDB[6:0], EDC[6:0], EDD[6:0] Intput Hold
2.5
2.5
2.5
ns
BACK[1:0], UERR Input Set-Up During Reset
8
10
12
ns
BACK[1:0], UERR Input Hold During Reset
5
5
5
ns
8-149
w
~
C
o
:E
!C:_~PRESS
~,
CYM7232
CYM7264
PRELIMINARY
SEMICONDUCTOR
AC Timing Characteristics (continued)
40/80 MHz
Description
Min.
33/66 MHz
Max.
Min.
Max.
Clock Frequency
20
40
20
Clock Cycle Time
50
25
50
25/75 MHz
Min.
Max.
Unit
33
20
25
MHz
30
50
40
ns
Clock Rise Time
1.6
1.6
1.6
ns
Clock Fall Time
1.6
1.6
1.6
ns
Clock Symmetry
45
55
45
55
45
55
%
Clock Pulse Width HIGH at 40, 33, and 25 MHz
11
14
13.5
16.5
18
22
ns
Clock Pulse Width LOW at 40, 33, and 25 MHz
11
14
13.5
16.5
18
22
ns
MCLK Frequency
20
80
20
66
20
75
MHz
MCLK Cycle Time
12.5
50
15
50
13.33
50
ns
MCLK Rise Time
1.6
1.6
1.6
ns
MCLK Fall Time
1.6
1.6
1.6
ns
MCLK Symmetry
45
MCLK Pulse Width HIGH at 80, 66, and 75 MHz)
MCLK Pulse Width LOW at 80, 66, and 75 MHz)
MCLKlCLK Skew
55
45
55
5.5
7
6.5
5.5
7
- 1.5
0
8-150
45
55
%
8.5
6
7.5
ns
6.5
8.5
6
7.5
ns
- 1.5
0
- 1.5
0
ns
S.riPRFSS
CYM7232
CYM7264
PRELIMINARY
~,. SEMJCONDUCIOR
Switching Waveforms
Read
REAL-TIME BACK CYCLE
ClK
~~~~~~~~~~~~nn~~~~~~~~
~
\. j
). h. h- h. h..rt..
\~
I
~
EARLY BACK CYCLE
\
i\
\
1/
.li'
Note 4
h.
1£
BUS DATA
~
Do 01
Note 4
h.
~t~C"",tr-
~
02 03
Do 01
1\ Lt
I\. ~
MCLK
- .. -f''PI..
~~ ~
It
tan
.. 21-ADRS[11:0I
R/W
1\
tAR
tRAM
X
ROW
V
COlo
-~
tMAc
tcz
top
tENR
Note 5
I
• :>c
I
V-
4-
"FESTRBl4]
tAC
~
READ DATA)--
Notei
f<
1'- 'I
I
READ DATA
~ II
Note 2
Notes:
2. FESTRB is asserted here following the closure of the snoop window in
the previous clock cycle.
3. FESTRBwouid normally occur after tE~delay if necessary to
align FESTRB to a bus clock boundary. FESTRB is asserted here following the assertion ofl'5S' (data strobe) in the previous clock cycle.
4.
5.
8-151
II
1\
RAM
I
tJ)
W
..J
:::l
ROw
-
Q
o
COl1
:E
tMAC tENR
tENR
\
t---tAR
+2
Min
ROW
COl1
.n ~n ~ ~
.n rut
~ I - - tRPC -
\
DRAM
DATA
M, ~~ ~
I~ ~ n
II
\
--
~READDATA
~ II
.
Note 3
BACK remains three-stated until it is first asserted. At the middle and
end of the transaction, BACK is deasserted in the first half of the clock
cycle and then three-stated.
FESTRB would normally occur here after tENR, however, it is automatically delayed by the controller to align to a bus clock boundary.
wr~~
CYM7232
CYM7264
PRELIMINARY
Switching Waveforms (continued)
Write - Real-Time Bus Acknowledge/Early Data Strobe
WRITE
ClK
rt-rt-rt-rt-rt- rt- rt- rt- rt-rt- rt-rl ~h- rt- rt-h-h. h-h-h- hJ1- ~ ~h.. ~ ~
I--
~ IJ
\. LI
I
I
\
THREE-STATE
"Bo B1
I
\
I
"
I
THREE-STATE
B~ B~
Do
MClK
\
ADRS
[11:0]
R!W
\. LI
1'--LI
nn ~~l~ hr
X
I lOW X
11
t1A -
I
CC
~WR~
-
~
~~ ~~
~ tENW" ~ t2A"
DATA
"'"D~
-,...
COL,
X
..n
M
~ tR
X
D
D2~
IX
II
. X--'"'-
....
-
tENW
-II
JC.
I,
II
1\
~IX
}n~
COL
\ 1\
1\
1/
I-t-
ROW
II
WR01
~ ~~ ~Yt
~~ ~
t1A
Ir~
NOTE 9
X
I
\
DRAM
...!~
r h.
"
S[ST[7)
NOTE 8
THREE-STATE
'tr
~
BUS
DATA
I
Dn,
FESiRI3[6)
!+.
t1B
\
\. ~
1-1
NOTE 10
NOTE 11
Notes:
6. FESTRB is an internal signal that unclocks the FIFO. FESTRB is one
bus clock cycle long.
7. 8LST may be internal or external
8. DS may be deasserted in any of the cycles shown.
9. tR 2 tRPC + 2 MCLK
tR2tAR + 2 MCLK
10.' The assertion of CAS requires
tcp to have expired (from previous transaction)
tMAC have expired (tlA> tMAc)
!nc..!.o have expired (tlB-2 tDc)
Si'j~Vv' io have closed 2 bus clocks previous.
\~
NOTE 12 NOTE 10
11. The assertion of CAS (and all subsequent CAS cycles of the burst) requires
tDC to have expired
tcp to have expired (hA > tc;p)
After CAS asserted, 'FESTRBunclocks the write FIFO presenting
the next data page to the DRAM.
12. tlA is measured from the rising edge of the bus clock after tRAM has
expired.
8-152
~
~~PRFSS
~_, SEMICONDUCIOR
CYM7232
CYM7264
PRELIMINARY
Switching Waveforms (continued)
Write - Real-Time Data Strobe
WRITE
CLKILt1-tLt1-h-h-tl-tl-tLh-r-tfUi ~f"1-tltL ~ ~1L1L1Lh-tLnrtt1AS
I-I\.v
\.L/Jt-t-+-+-i-+--+-+---4--I---\
I
SNW
OS
/
I
\
THREE-STATE
BACK
BUS
DATA
.I'D
D
"'
\
BR/FE
B[Sf[7]
I\..V
MCLK nn
RAS"
~
~~tt"'
\..J
n~ ~~ ~~ ntJ 1nk(n~~tL (n~7~
--~~~I\~rt 't +-- ~
tENW
-I---
t2A •
!ENllI/~RAM ~
I---
1n~
tENW
-Ii
I
tJ)
NOTE 9
W
ADRS.---t-~~~~+-~~~~r-~~~-4-4~44~~~I-k~~_~~~--~~-X-..J
[11:01 _ _t-i'IX'--o.:R~O::.:.W~X,+-~C::.::;O~Lo~-IX
COL1
X
ROW
X
COL
R/W
CAS
--+-+--+-~~'"""
I
I\WR~ WR
-::l
C
II
01
--+-+--+-+-+-+--I--h
FESTRB[6]----1I--I---+-+--oI--oI--"-"'"'
Dn1
X
I\.~
NOTE 12 NOTE 10
8-153
:E
I,
\
G,x
o
I
\WRc\ WR01
~
~~PRFSS
~, ·SEMICONDUcrOR
CYM7232
CYM7264
PRELIMINARY
Switching Waveforms (continued)
Write - Early Bus Acknowledge
WRITE
CLKh-h-h. h-h. h-h- h-1Lh-h.~
AS ~t\..V
\
/
Note 8
I
BACK
P--~I--I""'\.. Bo
BUS DATA
B1 B;
I
I
B~I'l-+--+---ir----+-+-+-+-.j.-""""~
-I-.....j--I--I-(mD~
~/FE
Do
~H-+--+--I-----
\~~+-~~______~-4-+~~~r~~~+-__4-+-__- J
\.L/
MCLK
fin
~~f.t~
\
tjA
~~ tE~~~ t2A~~ M I~t~~~~j l.tE~~
_
I~~
I
Ir-
NOTE 9
-
ADRS --i-iv-~~~~~~-rv--~~--+-+v-~~~~~r-~~-~~'--X
XROW
COL___
[11 :0] _--j---tX~~I~(1W~X~~~C07'Ln:ll..f-+x,,-_~(~:O:.I.L...L_+-+X"-+....!lI.!n..+-V'--I-~
R/W
--+1\..._
----f--fo--+--+-~--i-.
I
l\wR~ WRo
\
II
CAS ----.,H--+--+--I---I----I---h
r---
\'+-_ _-+',
~
II
1\
--
DRAM
DATA
DX
FESTRB[6)
\../
NOTE 11
NOTE 10
8-154
Ir-
\
D
\.. J
NOTE 12 NOTE 10
r-
CYM7232
CYM7264
~
--=-,i~PRESS
PRELIMINARY
.
SEMICONDUCTOR
Switching Waveforms (continued)
I/O Cycles - Read[13]
elK
rL rL rL rL rL rL rL L rL rL L rL
~ 'J
~
\..LI
BUS
DATA
DATA
"'-=--./
BACK
(Normal )
THREE-STATE
BACK
THREEI-STATE
I
THREE-STATE
'--- J'
(Early)
L
I
I
THREE-STATE
Lf'
I
WRITE
~J
'-LI
(/)
W
..J
;:)
C
o
==
BUS
DATA
«« :«« :«« ~«« ««< [««< :«« X
DATA /
THREE-STATE
BACK
(Normal)
BACK
(Early)
I
J
I
I
L
THREE-STATE
L
Note:
13. Data transfer occurs 5 clock cycles after SNW or DS whichever occurs
last.
8-155
J'
LF
THREE-STATE
I
THREE-STATE
~~
PRELIMINARY
~=
CYPRFSS
~, SEMICONDUcrOR
CYM7232
CYM7264
Switching Waveforms (continued)
Arbitration for Bus Mastership During Reflective Read
elK
IL
n- ~)L n-ILn- n- N)L n- n-K >- n-IL
p0-
\.. LJ
\. V
I
I
r
BB(OUTPUT)
r
MASTER BB
8-156
t--
~R:
--.
~4
--=-_'
PRELIMINARY
~= CYPRESS
SEMICONDUcrOR
CYM7232
CYM7264
Switching Waveforms (continued)
Pre-initialization
,SET INIT BIT
RSTIN
PRE-IN IT PHASE -------I~
16 RAS CYCLES
Initialization
I
UJ
W
RSTIN
...I
~
~
RAS
Ulf
CAS
IIIII
ADRS [11:0]
C
o
~
~
:E
:III
:III
NORMAL OPERATION
REFRESH COMMENCES
RESET
PRE-INIT
INIT
(WRITE ALL LOCATIONS IN
ROW REFRESH ORDER)
15[1S--~
~C BIT SET
8-157
eC:f~PRFSS
~,
CYM7232
CYM7264
PRELIMINARY
SEMICONDUCTOR
Switching Waveforms (continued)
Reset Cycle
CLOCK
~------
16 ClK CYCLES/MIN 1 - - - - - - + - - . I
MBus Coherent Invalidate Cycle (CIE set)
ClK
BACK[1]
fiiiRDY'
0
1
2
3
4
I
I
I
I
L
THREE-STATE
"
Note:
14. BACK and UERR used as input to select bus acknowledge modes and
snoop window source during reset.
8-158
CYM7232
CYM7264
~
==- 4
-=-iF
PRELIMINARY
~iE CYPRESS
SEMICONDUCTOR
Timing Diagrams
RESET Invoking Mode 10, External Snoop Window
CLK
AS
•
A<36>
ooooooooo
ooooooooo
ooooooooo
TYPE<6>
00
00
00
SIZE<8>
00
00
00
DS
D<64>
1000000000000000
BACK
I
ooooooooooooooo
I
BACK
BACK<2>
I
BLST
INH
TRC
I
SNW
INT
BERR
tJ)
BR
W
.oJ
I
;:)
BG
Q
o
BB
RST
I
I
8-159
:E
Cifr~
CYM7232
CYM7264
PRELIMINARY
Timing Diagrams (continued)
Preinit Followed by Start of DRAM Init
CLK
MCLK
AS
ADRS<12
RAS
RAS<1>
RAS<2>
RAS<3>
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
RWO
RW2
RWI
RW3
I/O Write Followed by Read, Mode 01
CLK
PMD<3>
AS
A<36>
0
10
h-r
ooooooooo
100
00
SIZE<8>
100
00
D<64>
ooooooooo
ooooooooo
TYPE<6>
DS
0
01
101
00
I---,
I
I fedcba9876S43205
fedcba987654320S
ID
L-J
BACK
8-160
CYM7232
CYM7264
~
-=-,i~PRF.SS
PRELIMINARY
.
SEMICONDUCTOR
Timing Diagrams (continued)
I/O Write Inhibited Follwed by Read Inhibited
CLK
PMD<3>
AS
0
IL-J
ooooooooo
A<36>
ITPE<6>
ooooooooo
ooooooooo
00
100
SIZE<8>
DS
0
0
00
00
~
~
I
I fedcba980000000S
D<64>
101
00
00
fedcba9800000005
fedcba9800000005
BACK<1>
BLST
~
INH
TRC
SNW
~
~
I/O Write Followed by Read, Mode 11
Ien
w
.J
CLK
PMD<3>
AS
10
0
ooooooooo
:i
1°00000000
ooooooooo
ITPE<6>
100
00
SIZE<8>
00
00
D<64>
BACK<1>
o
IL--.J
A<36>
DS
::::»
C
0
10l
ol
00
r-
t-I
Ifedcba987654320S
fedcba9876543205
L-J
8-161
I
L-J
~ .~
CYM7232
CYM7264
PRELIMINARY
~=CYPRESS
~, SEMICONDUcrOR
Timing Diagrams (continued)
Read-Modify-Write Mode 01
CLK
MCLK
PMD<3>
7
AS
IL---J
A<36>
~OOO543200
TYPE<6>
SIZE
7
000543200
000543200
100
00
00
~oo
00
00
DS
J
L
D<64>
Sf7f6f5f4f3f2nf
lSl7f6f5f4f3f2nf
BACK<1>
INH
TRC
SNW
I
I
BR
r--
L
BB
ADRS<12
RAS
CAS
100s
11 320
C
320
r-r--
I
I
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
176543211
~
DDC<32>
DDD<32>
1
~
DDB<32>
c=J
RWO
c=lI
8-162
I
·
.~
====::1=
CYPRESS
-=:!!!!!!!iF SEMICONDUcrOR
CYM7232
CYM7264
PRELIMINARY
Timing Diagrams (continued)
Write Mode 01, Sequential, 32 Bytes
CLK
MCLK
PMD<3>
AS
Ad6>
00
los
SNW
BB
ADRS<12
RAS
05
05
I
I
I
BACK<1>
BR
00
00
D<64>
TRC
000543200
000543200
1000543200
DS
INH
7
~
TYPE<6>
SIZE<8>
7
17
I
I
13333333333333333
I
-
3333333333333333
I
I
I"
I
11 320
IOa8
1321
1000
1320
I
I
CAS
I
I
I
tJ)
CAS<1>
W
..I
CAS<2>
C
::»
o
CAS<3>
::E
DDA<32>
: 14f3f2flf
1122222222
DDB<32>
:1817(6f5f
1122222222
DDC<32>
133333333
DDD<32>
RWO
133333333
RW2
RWI
I
I
I
RW3
I
8-163
I
I
I
I
CYM7232
CYM7264
~
~~PRESS
~, SEMICONDUCTOR
PRELIMINARY
Timing Diagrams (continued)
Write Mode 01, Sequential, Misaligned, 32 Bytes
CLK
MCLK
PMD<3>
AS
A<36>
7
7
IL-J
:=J 000215488
000215488
TYPE<6>
000215488
00
00
SIZE<8>
05
00
05
DS
05
I
I
D<64>
BACK<1>
13333333333333333
1
I
3333333333333333
I
INH
TRC
SNW
BR
Ii
I
I
I
BB
ADRS<12
RAS
1042
11548
1549
I
I
CAS
I
I
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
HI
133333333
DDB<32>
HI
133333333
DDC<32>
II
1122222222
I
DDD<32>
II
1122222222
I
RWO
.
RW2
I
I
I
I
RWI
RW3
1000
1549
1548
I
I
I
I
8-164
.~
·
~~CYPRESS
,
CYM7232
CYM7264
PRELIMINARY
SEMICONDUcrOR
Timing Diagrams (continued)
Write Mode 01, Intel, Misaligned
CLK
MCLK
PMD<3>
AS
7
TYPE<6>
7
n--r
A<36>
SIZE<8>
7
000215488
000215488
000215488
02
J02
05
DS
02
05
05
I
I
I
D<64>
BACK
I
I
3333333333333333
13333333333333333
L
I
INH
TRC
SNW
~
I
BR
I
I
BB
ADRS<12
RAS
000
1042
1549
11548
1548
CAS
I
I
....I
~
CAS<2>
Q
o
CAS<3>
:1
DDA<32>
133333333
I
133333333
1
DDB<32>
:1
DDC<32>
:1413f2nf
1122222222
DDD<32>
:1817f6fSf
1122222222
RWO
I
I
RWI
RW3
Ien
w
CAS<1>
RW2
1000
J
l
I
I
I
I
I
8-165
I
I
:z
.
~
.
~
"
PRELIMINARY
CYPRESS
,
CYM7232
CYM7264
SEMICONDUCTOR
Timing Diagrams (continued)
Write Mode 01, Intel, Misaligned, 64 Bytes
CLK
MCLK
PMD<3>
AS
7
7
I1-J
A<36>
000215488
000215488
TYPE<6>
SIZE<8>
DS
D<64>
7
000215488
02
02
:1
06
06
02
06
I
I
I
BACK<1>
I
I
I
I
I
I
7777777777777777
17777777777777777
I
I
INH
TRC
SNW
IL--J
BR
I
I
BB
ADRS<12
RAS
1042
(549
11548
1154a
154b
(
I
I
CAS
CAS<1>
CAS<2>
CAS<3>
II
II
DDA<32>
DDB<32>
I
I
II
II
I
I
DDC<32>
II
II
I
DDD<32>
II
II
I
RWO
RW2
II
II
I
I
I
RWI
RW3
1000
I
I
I
I
I
8-166
mEr
.~
_'=
--=-,
CYM7232
CYM7264
PRELIMINARY
CYPRFSS
SEMICONDUCTOR
Timing Diagrams (continued)
Write Burst Truncated by BLST, Mode 01
CLK
MCLK
AS
IL-----J
A<36>
TYPE<6>
000543200
000543200
000543200
00
100
SIZE<8>
00
07
DS
07
I
07
I
I
D<64>
11111111111111111
BACK
I
1111111111111111
I
BLST
INH
TRC
SNW
I
I
BR
I
I
BB
ADRS<12
10aS
DOOO
320 1321
11320
CAS<1>
Ien
CAS<2>
..J
CAS<3>
C
RAS
I
I
CAS <0>
I
I
w
~
DDA<32>
14f3f20r
I
DDB<32>
lSI7f6f5f
I
DDC<32>
I
DDD<32>
I
RWO
I
RW2
I
RW3
I
I
I
8-167
I
I
I
RWI
I
I
o
-----
:E
£~PRE§
~CONDUcrOR
CYM7232
CYM7264
PRELIMINARY
. . .'
Timing Diagrams (continued)
Write Mode 01, Transformed
CLK
MCLK
PMD<3>
AS
A<36>
TYPE<6>
SIZE<8>
DS
D<64>
BACK<1>
INH
TRC
SNW
BR
BB
ADRS<12
000
1088
11320
1000
RAS
CAS
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
RWO
RW2
RWI
RW3
8-168
-==r';~pRF.SS
CYM7232
CYM7264
PRELIMINARY
·
SEMICONDUcrOR
Timing Diagrams (continued)
Write Burst Followed by Write, Mode 01
CLK
MCLK
Innnnnnnnnnnnnn
1nn nn nnnnnnn nn
PMD<3>
AS
A<36>
000432111
1000432111
nn nn nnnnnr
7
000543200
1000543200
00
00
00
SIZE<8>
03
103
07
I
~
I I I I I I I I I I I I I I I I
D<64>
BACK
~1 nnnnnn~
7
iU
TYPE<6>
DS
1nn
7
~
ISI7f6f5f4f3f2flf
I
INH
TRC
SNW
h-r
r-
l
BR
BB
ADRS
I
1211
1212
1213
1214
1215
1216 1217
1210
I 1000
II
I
I
I
I I
~
~
CAS
..J
::)
CAS<2>
Q
o
CAS<3>
DDA<32>
U
m
D
DDB<32>
U
I
I
II
n
I
0
DDC<32>
DDD<32>
D
RW3
I
I
I
I
I
D
I
I
-I
I
II
n
I
n
I
I
II
I
D
I
I
RW2
RWI
tn
W
CAS
RWO
11
D
C]------
D
C]------
I
-D-D--
I
~
I
I
I
I
I
I
8-169
~
:E
:~
·
...... ,
CYM7232
CYM7264
PRELIMINARY
~~NDUcrOR
Timing Diagrams (continued)
Write Burst Followed by Read, Mode 01
CLK
MCLK
PMD<3>
AS
A<36>
7
7
h-J
1000432111
TYPE<6>
SIZE<8>
DS
7
00
106
06
1000543200
000543200
101
01
103
03
~
I
D<64>
I
I
BACK
I
I
I
I
I
I
7777777777777777
17777777777777777
U-
I
INH
TRC
SNW
IL-r
BR
I
I
BB
ADRS<12
RAS
I
I
1086
1212
0211
1213
1210
1
I
1000
I
1008
D320
I
1
r~
CAS
CAS<1>
CAS<2>
CAS<3>
DDA<32>
II
II
I
DDB<32>
II
II
I
DDC<32>
I
II
I
DDD<32>
I
II
I
RWO
I
RW2
RWI
RW3
-c::J------c::J------c::J------c::J-----I
I
I
1
\
I
I
8-170
CYM7232
CYM7264
~
~.,~
PRELIMINARY
~=CYPRESS
~ iF
SEMICONDUCTOR
Timing Diagrams (continued)
Write Posted Followed by Read, Mode 01
eLK
MCLK
PMD<3>
AS
A<36>
7
7
7
ru
1000432111
1000543200
TYPE<6>
110
101
01
SIZE<8>
107
103
03
DS
D<64>
BACK
Ii
000543200
I
Ifedcba9876543210
11I111I111111111
II
fedcba9876543210
I
INH
TRC
SNW
h-r
BR
~
I
BB
ADRS<12
I
000
I I
I
I I
I I
I
I
I
I
1
I
II
RAS
r--
CAS
~
CAS<1>
en
w
...I
CAS<2>
::l
CAS<3>
o
C
DDA<32>
I
I
I
I
I
n
I
I----
DDB<32>
D
I
I
I
I
I
I
I---l-----
DDC<32>
I
I
I
I
I
n
I
DDD<32>
I
I
I
I
I
Jl
I
RWO
I
RW2
I
RWI
L
RW3
I
8-171
!----
r---r---r---r----
:E
CYM7232
CYM7264
~
i~pRF.SS
.
--====r'
PRELIMINARY
SEMICONDUCTOR
Timing Diagrams (continued)
Write Mode 10 Showing BR as FE
CLK
MCLK
PMD<3>
17
AS
~
A<36>
~000543200
TYPE<6>
SIZE
7
7
000543200
000543200
00
00
00
~05
05
05
DS
I
D<64>
I
I
I
13333333333333333
1
3333333333333333
BACK<1>
INH
TRC
SNW
I
I
BR
I
I
BB
ADRS<12
RAS
000
11 320
IOa8
1321
1320
I
CAS
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
: 14t3f2flf
1122222222
I
DDB<32>
:1817f6f5f
1122222222
1
DDC<32>
:1
133333333
I
:1
133333333
DDD<32>
RWO
I
RW2
RWI
RW3
1000
I
I
I
I
I
I
I
I
I
8-172
·
·~PRFSS
JF
CYM7232
CYM7264
PRELIMINARY
SEMICONDUCTOR
Timing Diagrams (continued)
Write Burst, Mode 11
CLK
MCLK
PMD<3>
AS
7
IL--J
A<36>
DS
000543200
000543200
TYPE<6>
SIZE<8>
7
7
00
00
00
06
06
:J06
I
I
D<64>
1
BACK<1>
1
1
I
1
1
7777777777777777
17777777777777777
1
I
I
INH
TRC
SNW
IL-.-J
BR
J
I
BB
ADRS<12
RAS
1liaS
8320
1321
D322
1323
I
I
CAS
..J
::)
CAS<2>
C
CAS<3>
DDA<32>
II
II
DDB<32>
II
II
I
IT
I
II
DDC<32>
II
DDD<32>
RW3
o
==
..
..
I
I
II
I
I
RW2
RWI
Ien
w
CAS<1>
RWO
1000
I
I
I
I
I
r
I
8-173
SYl=
~J
CYM7232
CYM7264
PRELIMINARY
SEMICONDUCTOR
Timing Diagrams (continued)
Write 32 Bytes, Misaligned 32-Bit Bns
CLK
MCLK
PMD<3>
AS
A<36>
7
7
h---J
1000215488
000215488
TYPE<6>
000215488
00
00
SIZE<8>
00
05
05
DS
05
I
D<32>
BACK<1>
7
1
I
1
1
I
17777777777777777
1
~
7777777777777777
I
INH
TRC
SNW
II
I
BR
I
I
BB
ADRS<12
RAS
000
1042
1549
11548
I
1548
I
1000
I
CAS
I
I
I
I
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
c::::::::Jl I22222222
166666666
II
DDB<32>
HI 11111111
133333333
I
DDC<32>
deID1234
I
II------
II
DDD<32>
RWO
RW2
RWI
I
I
I
I
r---
I
RW3
I
8-174
I
· ~~
_'iECYPRESS
SEMICONDUcrOR
CYM7232
CYM7264
PRELIMINARY
--=-,
Timing Diagrams (continued)
Write 32 Bytes, Misaligned, Intel Order 32-Bit Bus
, CLK
MCLK
PMD<3>
AS
7
7
L--.I
A<36>
TYPE<6>
7
000215488
000215488
102
SIZE<8>
02
05
DS
000215488
02
05
05
I
I
D<32>
I
1
BACK<1>
1
I
I
I
I
17777777777777777
L
I
INH
TRC
SNW
Ii
I
BR
I
I
BB
ADRS<12
RAS
000
1042
I
1549
11548
I
1000
II
I
CAS
I
I
I
I
(J)
CAS<1>
W
..J
CAS<2>
::l
CAS<3>
o
C
DDA<32>
I
DDB<32>
77777777
DDC<32>
4f3f2flr
DDD<32>
11111111
RWO
I
RW2
RWI
RW3
I
II
77777777 133333333
I
1144444444
1
155555555
:E
I
I!-------
I
I
I
r---
I
I
8-175
J
~~~
CYM7232
CYM7264
PRELIMINARY
Timing Diagrams (continued)
Write with BLST, 32-Bit Bus
CLK
MCLK
AS
~
A<36>
TYPE<6>
000543200
000543200
000543200
100
00
00
SIZE<8>
07
DS
I
07
07
I
I
D<32>
11111111111111111
BACK<1>
1111111111111111
I
I
BLST
INH
TRC
SNW
l
I
BR
r--
I
BB
ADRS<12
RAS
11320
IOa8
0000
320P2l
I
I
CAS
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
II
11413f2flf
DDB<32>
I
flTfffff
ITfIlTfI'
I
DDC<32>
c=J
DDD<32>
RWO
I
I
RW2
RWI
I
l
RW3
8-176
·
.~
-=-,
CYM7232
CYM7264
PRELIMINARY
~iE CYPRESS
SEMICONDUCTOR
Timing Diagrams (continued)
Read Mode 01, 8 Bytes
CLK
MCLK
PMD<3>
AS
A<36>
=
7
==:=J7
II
7
I
000543200
000543200
TYPE<6>
==:=J01
01
01
SIZE<8>
==:=J03
03
03
1000543200
r-
DS
I
D<64>
OOOOXxIl'OOOOXxff
n
OOOOXxflOOOOXxff
BACK<1>
I
l
INH
TRC
SNW
l
I
BR
BB
ADRS<12
RAS
I
I
000 IOa8
1000
11320
l
I
l
CAS
r
I
tn
W
..J
::l
CAS<1>
Q
o
CAS<2>
:E
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
8-177
CYM7232
CYM7264
PRELIMINARY
Timing Diagrams (continued)
Read Mode 01, 32 Bytes
CLK
MCLK
PMD<3>
AS
7
7
7
~
A<36>
000543200
000543200
000543200
TYPE<6>
01
01
01
SIZE<8>
los
05
DS
05
r--
I
D<64>
II
fedcba9876543210
BACK
II
ID
II
r--
I
INH
TRC
SNW
I
I
BR
BB
I
ADRS<12
IOa8
RAS
CAS
r-UOOO
1321
1)320
I
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
8-178
I
~~
~
i= CYPRF.SS
CYM7232
CYM7264
PRELIMINARY
~, SEMICONDUcrOR
Timing Diagrams (continued)
Read Mode 01, Wait State, 32 Bytes
CLK
MCLK
PMD<3>
7
7
:=J 000543200
000543200
000543200
:=J01
01
01
SIZE<8>
:=J05
05
05
DS
W
17
AS
h-----J
A<36>
TYPE<6>
r---
I
D<64>
BACK<1>
III
cba9873143210131
II
III
r--
I
W
II
INH
TRC
SNW
I
I
BR
BB
ADRS<12
RAS
CAS
I
I
000
1008
11320
BOlIO
1321
I
I
I
I
w
..J
:::»
CAS<1>
Q
o
==
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
Ien
c=:::J
8-179
c:=J
CYM7232
CYM7264·
~
. :~PRESS
~, SEMICONDUCTOR
PRELIMINARY
Timing Diagrams (continued)
Read Mode 01, Sequential, Misaligned
CLK
MCLK
PMD<3>
7
AS
~
A<36>
==:J 000215488
000215488
TYPE<6>
os
DS
D<64>
000215488
01
01
01
SIZE<8>
7
7
05
05
I
I
II
7777777777777777
ID
BACK<1>
I
II
II
~
INH
TRC
SNW
I
I
BR
BB
ADRS<12
RAS
CAS
I
I
000
1042
1549
11548
1548
1000
I
I
I
I
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
L--...l
8-180
L--...l
L--...l
.
.~
CYM7232
CYM7264
PRELIMINARY
EiIiIIIE;; CYPRESS
~, SEMICONDUCTOR
Timing Diagrams (continued)
Read Mode 01, Intel, Misaligned, 32 Bytes
CLK
MCLK
PMD<3>
AS
7
7
iL-J
A<36>
TYPE<6>
7
000215488
103
000215488
000215488
03
03
SIZE<8>
DS
05
05
05
r---
I
D<64>
II
fedcba9876543210
BACK<1>
II
II
II
r-
I
INH
TRC
SNW
I
I
BR
BB
ADRS<12
RAS
CAS
I
I
Booo
1549
11548
000 1042
l
I
r
I
•
tJ)
W
..J
CAS<1>
~
C
o
CAS<2>
:E
CAS<3>
DDA<32>
DDB<32>
DDC<32>
c==J
DDD<32>
8-181
c==J
t;;jjw~~R
CYM7232
CYM7264
PRELIMINARY
Timing Diagrams (continued)
Read Mode 01, Intel, Misaligned, 64 Bytes
CLK
MCLK
PMD<3>
AS
A<36>
TYPE<6>
SIZE<8>
03
03
06
106
DS
D<64>
edcba9876543210f
BACK<1>
INH
TRC
SNW
BR
BB
ADRS<12
000
03
06
1042
RAS
CAS
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
8-182
~
~.CYPRESS
CYM7232
CYM7264
PRELIMINARY
~, SEMlCONDUcrOR
Timing Diagrams (continued)
Read with BLST Mode 01
CLK
MCLK
AS
A<36>
~
000543200
000543200
000543200
TYPE<6>
101
01
01
SIZE
107
07
07
DS
I
l
D<64>
III
8I7f6f5f4f3f2flf
BACK
lL
l
I
BLST
INH
TRC
SNW
I
J
BR
BB
ADRS
1
I
11320
IOa8
II
1321
I
I
CAS
I
I
l
I
CAS
•
UJ
W
..J
:l
Q
CAS<2>
o
::IE
CAS<3>
1--
DDA<32>
DDB<32>
I-
DDC<32>
1--
DDD<32>
1--
8-183
~PRRSS
CYM7232
CYM7264
PRELIMINARY
WnEMICONDUCfOR
Timing Diagrams (continued)
Read Mode 01, Transformed
CLK
MCLK
PMD<3>
7
7
7
A<36>
000543200
000543200
000543200
TYPE<6>
01
01
AS
h-J
SIZE<8>
DS
01
05
05
I
I
D<64>
I
BACK<1>
1
I
1
I
I
1
17777777777777777
7777777777777777
I
INH
TRC
SNW
IL---J
BR
BB
ADRS<12
RAS
~
l
I
I
~Oa8
1321
11320
11322
(323
I
I
r--
l
~
CAS
CAS<1>
CAS<2>
CAS<3>
DDA<32>
II
11
1
DDB<32>
II
II
I
DDC<32>
I
II
1
I
IT
J
DDD<32>
"
"
RWO
I
RW2
I
RWI
I
I
RW3
I
I
I
8-184
&:~PRFSS
CYM7232
CYM7264
PRELIMINARY
~, SEMICONDUCTOR
Timing Diagrams (continued)
Read Mode 11
CLK
MCLK
PMD<3>
AS
7
000543200
000543200
01
01
tL---J
A<36>
TYPE<6>
SIZE<8>
7
7
os
los
DS
05
I
1
D<64>
II
fedcba9876543210
BACK<1>
II
m
II
I
1
INH
TRC
SNW
I
I
BR
BB
I
ADRS<12
10aS
RAS
CAS
r--0320
8000
1321
I
I
l
r
I
tJ)
W
-I
CAS<1>
:::»
CAS<2>
o
Q
:E
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
8-185
L~PRFSS
CYM7232
CYM7264.
PRELIMINARY
~, SEMICONDUCIOR
Timing Diagrams (continued)
Reflective Transaction Showing Bus Arbitration
CLK
MCLK
AS
L-J
A<36>
1000543200
000543200
000543200
lYPE<6>
101
01
01
105
05
05
SIZE<8>
DS
"I
D<64>
I
BACK<1>
L
I
I
I
I
I
I
7777777777777777
17777777777777777
I
INH
TRC
SNW
~
BR
I
BG
I
I
I
J
BB
ADRS<12
RAS
Uno
10aS
1321
11 322
1323
1
1000
r---
I
~
CAS
CAS<1>
CAS<2>
CAS<3>
DDA<32>
11
II
DDB<32>
I
II
I
DDC<32>
I
II
1
I
II
I
DDD<32>
I
RWO
I
RW2
I
I
RWI
I
J
RW3
I
I
I
8-186
3¥:~
CYM7232
CYM7264
PRELIMINARY
~ICYPRESS
~, SEMlCONDUcrOR
Timing Diagrams (continued)
Read 32 Bytes, Misaligned 32-Bit Bus
CLK
MCLK
PMD<3>
AS
A<36>
TYPE<6>
7
7
7
000215488
000215488
01
01
iL---J
:==J 000215488
01
os
SIZE<8>
DS
05
05
r-
I
D<32>
I
ffIl'IlTIlTfffIlT
BACK<1>
I
m
m
II
II
m
I
I
L
INH
TRC
SNW
I
I
BR
BB
I
ADRS<12
1042
I
CAS<2>
•
CAS<3>
o
RAS
CAS
11548
1000
1548
1549
I
I
I
I
::l
C
::E
DDA<32>
DDB<32>
DDC<32>
tJ)
W
.J
CAS<1>
[:::=J
DDD<32>
RWO
RW2
RWI
RW3
8-187
c=J
I
I
CYM7232
CYM7264
"
7;.
~~PRESS
"""==" F
PRELIMINARY
SEMICONDUcrOR
Timing Diagrams (continued)
Read 32 Bytes, Misaligned, Intel Order 32-Bit Bus
CLK
MCLK
PMD<3>
AS
7
7
IL--J
A<36>
TYPE<6>
7
000215488
000215488
000215488
03
103
SIZE<8>
03
05
05
DS
05
r--
I
D<32>
II
fffffffffedcba98
BACK<1>
m
I
I
ID
II
ID
II
I
I
INH
TRC
SNW
r-----l
I
BR
BB
ADRS<12
RAS
CAS
I
L
000
11 548
/042
/549
1000
I
I
J
L
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
C:::J
C:::J
C:::J
DDD<32>
RWO
RW2
RWI
I
RW3
8-188
I
I
I
I
I
I
CYM7232
CYM7264
~
;pz
.~
~=
~_.'
PRELIMINARY
CYPRESS
SEMICONDUCTOR
Timing Diagrams (continued)
Read with BLST, 32·Bit Bus
CLK
MCLK
AS
h--.J
A<36>
000543200
000543200
000543200
TYPE<6>
101
01
01
SIZE<8>
107
07
07
DS
D<32>
I
I
817f6f5f413f2Of
817f6f5f413f2flf
!II
BACK<1>
1
I
I
BLST
INH
TRC
SNW
I
I
BR
BB
ADRS<12
RAS
I
I
1321
0320
IOa8
I
CAS
I
I
l
0=
r-r--
II
en
w
CAS<1>
..J
CAS<2>
~
C
CAS<3>
o
1--
DDA<32>
DDB<32>
I------
DDC<32>
1-1--
DDD<32>
RWO
RW2
RWI
RW3
8-189
:::i5
•
4:::~
'. CYPRFSS
"
CYM7232
CYM7264·
PRELIMINARY
SEMICONDUCTOR
Timing Diagrams (continued)
Refresh, Staggered RAS, No Scrub, No Error in Data
CLK
MCLK
AS
ADRS<12
RAS
RAS<1>
RAS<2>
RAS<3>
111 001
001
I[
000
1000
I
I
I
I
I
I
I
I
CAS
l
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
RWO
RW2
RWI
RW3
INT
FESTRB
8-190
r
~
~~PRESS
~_,
SEMICONDUCTOR
CYM7232
CYM7264
PRELIMINARY
Timing Diagrams (continued)
Refresh, Staggered RAS, Scrub
CLK
MCLK
AS
ADRS
RAS
RAS<2>
RAS<3>
CAS
CAS
CAS<2>
CAS<3>
DDA<32>
76543210
DDB<32>
fedcba98
DDC<32>
89abcdef
DDD<32>
01234567
I
RWO
RW2
RWI
tJ)
RW3
....I
W
::;)
Q
INT
o
FESTRB
:E
8-191
..n~=
PRELIMINARY
Timing Diagrams (continued)
Refresh, Mutually Exclusive RAS, Scrub
CLK
MCLK
AS
ADRS<12
I_
RAS
RAS<1>
RAS<2>
RAS<3>
CAS
CAS<1>
CAS<2>
CAS<3>
DDA<32>
DDB<32>
DDC<32>
DDD<32>
RWO
RW2
RWI
RW3
INT
FESTRB
8-192
CYM7232
CYM7264
'$?lPRF$
~
CYM7232
CYM7264
PRELIMINARY
SEMlCONDUcrOR
Power Dissipation
The table below shows the estimated power dissipation for various bus clock frequencies under specific assumptions. The temperatures listed under the air flow column are the maximum ambient air temperature allowed for the frequency at the left and
the air flow at the column top.
The assumptions are: DRAM bus load = 50 pF; system bus load
= 100 pF; system bus data frequency is Y2 of the system clock
(NRZ); DRAM bus data frequency is Y2 of the system clock
(NRZ); and Vee is 5.25Y.
The data pattern assumptions are:
Reads:
213 of all system bus cycles involve the CYM7232.
213 of all CYM7232 cycles are reads.
Y2 of the 64-bit system bus will toggle on average.
The CYM7232 drives the system bus 113 of the
time during a read.
Writes:
213 of all system bus cycles involve the CYM7232.
113 of all CYM7232 cycles are writes.
liz of the 64-bit system bus will toggle on average.
The CYM7232 drives the system bus 1/6 of the
time during a write.
Air Flow -LFM (C)
System Clock
Frequency (MHz)
Power
(watts)
0
100
200
300
400
25
0.8
70
70
70
70
70
33
1.0
60
60
60
70
70
40
1.2
60
60
60
60
60
Socket Data
Textool 3M Grid ZIP PGA Kit 25 x 25
Socket Part # 2-0000-06325 -170-024-000
PGA Pin (gold plated) Part# 3-0000-02740-006-000-002
PGA Pin (nickel plated) Part# 3-0000-02740-006-000-005
Procon Part# 228-401-1001- 2525
Test Receptacle:
(uses Millmac 0400 Pins Part# 0400-0-15-01-47-27-0400)
McKenzie Part# PGA401H009B2-2406R
Production Socket:
Tech Spray Part# 2111-P (Goldfinger Glove)
Installation Lubricant:
McKenzie Part# TOLPGAX-41622-001 (CYM7232)
Extraction Tool:
TOLPGAX -41622-002 (CYM7264)
McKenzie, 44370 Old Warm Springs Boulevard, Fremont, CA 94538 (510) 651-2700
Tech Spray, p.o. Box 949, Amarillo, TX 79105 (806) 372-8523
Procon Tech., 1333 Lawrence Expwy., Suite 207, Santa Clara, CA 95051 (408) 246-4456
Textool,6801 Riverplace Blvd., Austin, TX 78726 (800) 328-0411
Test ZIF Socket:
I
tJ)
W
...I
;:)
Q
o
::E
Ordering Information
Speed (MHz)
BuslDRAM
Ordering Code
Package
Name
Package 'JYpe
Operating
Range
40/80
CYM7232S-40HGC
HG02
401-Pin PGA Module
Commercial
33/99
CYM7232H-33HGC
HG02
401-Pin PGA Module
Commercial
33/66
CYM7232S- 33HGC
HG02
401-Pin PGA Module
Commercial
25/100
CYM7232H - 25HGC
HG02
401-Pin PGA Module
Commercial
25/75
CYM7232S-25HGC
HG02
401-Pin PGA Module
Commercial
Package 'JYpe
Operating
Range
Speed (MHz)
BuslDRAM
40/80
Ordering Code
CYM7264S-40HGC
Package
Name
HG03
401-Pin PGA Module
Commercial
Commercial
33/99
CYM7264H-33HGC
HG03
401-Pin PGA Module
33/66
CYM7264S-33HGC
HG03
401-Pin PGA Module
Commercial
25/100
CYM7264H-25HGC
HG03
401-Pin PGA Module
Commercial
25/75
CYM7264S- 25HGC
HG03
401-Pin PGA Module
Commercial
Document #: 38-M-00051-C
8-193
PRELIMINARY
CYPRESS
SEMICONDUCTOR
CYM7485
128K Write-Through Secondary
Cache "Module
Features
Functional Description
• 128-Kbyte direct-mapped, writethrough, zero-wait-state secondary .
cache module
• Operates with 33-MHz Intel 486 processors
• Uses low-cost CMOS asynchronous
SRAMs as cache data storage and
cache tag storage
• Supports self-invalidation
• 64-position dual-read-out SIMM with
128 leads
• Single 5V (±5%) power supply
• TTL-compatible inputs/outputs
The CYM7485 is a self-contained
128-Kbyte direct-mapped, zero-waitstate, write-through secondary cache
module designed for use in Intel
486-based systems. The line size is 16
bytes. Cache data is stored in four 32K
by 8 asynchronous SRAMs, and the tag
addresses are stored in two 8K by 8
asynchronous" SRAMs.The address from
the processor is captured by high-speed
transparent latches at the beginning of
each access and the lowest two address
bits are incremented according to the Intel burst sequence during burst reads and
cache line fills.
The on-board cache controller coordinates accesses to the cache memory. During a read hit, four 32-bit words are read
from the cache RAMs and returned to the
processor without wait states. If the read
location requested by the processor is not
found in the cache, the memory controller
will hold the processor and retrieve the
missing line from the main memory. Dur~
ing write cycles,' the main memory is always updated with the data from the processor. If the write location is found in
the cache, then the cache content is updated as well.
All components on the cache module are
surface mounted on a multi-layer epoxy
laminate (FR-4) board.The package dimensions are 3.85" x 0.200" x 1.5". All
inputs and outputs of the CYM7485 are
TTL compatible and operate· from a
single 5V power supply. The contaqt pins
are plated with 100 micro-inches of nickel
covered by 5 micro-inches of gold flash.
Logic Block Diagram
CACHE RAMS
LA. -
LA16
0
A
0 0- 031
CA2 - CAa
,--=.
r-
OE
WE
WE
WE
WE
TTI
,/
/4
CLOCK
A2 - A31
A
1~V
TAG RAMS
~-A16
A
r
;---
OE
WE
01+---
--
0
CACHE CONTROLLER
~
CONTROLS
Valid
T
8-194
1
7485-1.
~
~~
~ICYPRF.SS
~, SEMICONDUcrOR
PRELIMINARY
CYM7485
SIMM
Top View
Pin Configuration
GNO
RESET
GNO
CLK
65
66
67
NC
68
M/iO 69
FLUSH
70
EADS 71
GNO
72
ADS 73
BEo
74
75
BE2
NC
76
CRD'Y 77
GNO
78
"CSRDY
79
SKEf\J
80
NC
81
J5FISN
82
NC
83
NC
84
A2
85
Vee 86
87
~
As 88
89
A8
90
Al0
91
A12
92
A14
A16
93
GNO
94
95
A18
96
A20
97
A22
98
A24
99
A26
100
A28
101
A30
GNO
102
103
00
104
02
105
04
Vee 106
107
06
GNO
108
NC
109
110
08
111
010
112
012
GNO
113
014
114
0 16
115
116
018
0 20
117
118
GNO
0 22
119
NC
120
121
024
122
026
GNO
123
124
028
125
030
Vee 126
10 1
127
GNOL 128
Vee
Vee
NC
o/C
BI:AST
BOFF
GNO
W!R
BEl
BE3
CS
NC
GNO
BROYO
START
NC
NC
NC
NC
A3
Vee
A5
A7
A9
All
A13
A15
A17
GNO
A19
A21
A23
A25
A27
A29
~1
GNO
01
03
05
I
tJ)
W
...I
::)
Q
0
::E
Vee
07
GNO
NC
09
0 11
013
GNO
015
017
019
021
GNO
023
NC
0 25
0 27
GNO
029
0 31
Vee
100
GNO
8-195
7485-2
~
;~PRESS
PRELIMINARY
~, SEMICONDUCIOR
CYM7485
Pin Descriptions
Symbol
Parameter
1YPe
Pins
Description
Active
CLK
Clock
I
1
N/A
This input is the timing reference for all module functions. It is the same
as the i486 clock.
RESET
Reset the Cache
I
1
HIGH
RESET is sampled at each clock rise. If it is true, the cache logic will be
placed in the idle state. RESET will not invalidate the cache contents.
ADS
Address Strobe
I
1
LOW
ADS is connected to the ADS signal from the i486. It is used to start
read or write cycles. CS must be asserted for ADS to be recognized.
MilO
Memory/IO
I
1
N/A
This signal is used by the i486 to distinguish between memory and 10
accesses. The module will not cache 10 accesses.
W/R
Write/Read
I
1
N/A
A LOW indicates a read cycle. A HIGH indicates a write cycle.
DIC
Data/Control
N/A
1
N/A
This signal is not used by the CYM748S.
START
Memory Start
0
1
LOW
START is asserted during read miss and write cycles. It signals the main
memory to service the current access.
BRDYO
Burst Ready Out
0
1
LOW
This signal is asserted during read hits only. It indicates to the i486 that
valid data from the cache is available. BRDYO is deasserted during other
accesses.
CBRDY
Cache Burst Ready In
I
1
LOW
This signal is asserted when burst data from the system is ready to be
sampled by the i486 and the cache module.
CRDY
Cache Ready In
I
1
LOW
This signal is asserted when non-burst data from the system is ready to be
sampled by the i486 and the cache module.
BLAST
Burst Last
I
1
LOW
BLAST is asserted by the i486 when the current cycle is the last cycle of a
burst access.
BOFF
Back-off
I
1
LOW
BOFF is sampled at each clock rise except the rising edge of T1 in a i486
access. If BOFF is asserted, the cache module will place its data lines in a
three-stated condition. In addition, START and BRDYO will be
deasserted.
PRSN
Presence
0
1
LOW
This signal is tied to ground. It indicates to the system that the cache
module is present.
A2 - A31
Address Lines
I
30
N/A
Address inputs to the CYM748S.
BBo - BE3
Byte Enables
I
4
LOW
These signals are used during write cycles to determine which byte( s) will
be written.
CS
Chip Select
I
1
LOW
For normal accesses, CS must be LOW before ADS or EADS can be
recognized. If CS is HIGH and ADS is LOW, the cache line selected by
the address on A2 - A31 will be invalidated.
Do - D31
Data Lines
I/O
32
N/A
Data lines to/from the i486, main memory, and other system components.
Do - D7 is the low byte.
SKEN
System Cache Enable
I
1
LOW
This signal is generated by the system to inform the i486 and the cache
module that the current line is cachable. During a cache line fill, SKEN is
sampled one clock cycle before the first word is returned and one clock
cycle before the last word of the line is returned.
FLUSH
Cache Flush
I
1
LOW
If FLUSH is LOW and ADS is LOW, then the cache line selected by the
address on A2 - A31 will be invalidated.
EADS
Valid External
Address
I
1
LOW
If EADS is asserted together with CS, then the cache line selected by the
address on A2 - A31 will be invalidated if a match is found.
IDo - IDl
Cache Size Selector
0
2
N/A
These two lines are not connected on the cache module. They are tied
externally to Vee to select a cache size of 128K bytes.
8-196
~
.
;~PRESS
0'
PRELIMINARY
CYM7485
SEMICONDUCIOR
Basic Operation
The CYM7485 is a complete 128-Kbyte, direct-mapped secondary cache subsystem designed to work with 33-MHz Intel.486
processors. The cache memory is divided into 8K 16-byte hnes
and each line is assigned a dedicated entry in the cache tag RAM.
The CYM7485 supports zero-wait-state operations: it can return
four words from its cache memory in five clock cycles (i.e.,
2-1-1-1). A write-through cache policy is implemented to provide data integrity.
Four 32K by 8 asynchronous SRAMs provide the 128-Kbyte
cache storage and two 8K by 8 asynchronous SRAMs store the
8K 16-bit tag entries. Each tag entry is divided into a 15-bit tag
field (to support the 4-Gbyte processor address space) and a valid
bit. During an access, the contents of the t~g entry selected by
processor address bits, ~ - A16, are dehvered to two 8-bit
comparators where they are matched ~gainst the 15 upper order
address bits from the i486. A match IS declared only If the two
set of addresses are identical and the valid bit of the tag entry is
set.
Addresses from the processor are captured by transparent latches
before they are delivered to the cache memory. The lowest two
address bits (A2 and A3) are increment.ed by the ~ache c0J?-trol~er
according to the Intel burst order durmg read hits and hne fdls
(see Table 1).
The following functions are not supported in the CYM7485: data
parity (DPo - DP3), write protect (WP), write protect strap
(WPSTRAP), cache enable to CPU (CKEN), software flushes,
and global cache invalidation.
Read Cycles
A read cycle is initiated when ADS, CS, and W/R are sampled
LOW at clock rise with MilO sampled HIGH. The processor address is captured by a set of transparent latches as soon as the a~
cess is started. The latch will remain closed until the access IS
completed or until BOFF is asserted (LOW). BEo - BE3 are ignored in all read accesses.
Tag look-up begins whenever a valid processor address is available. Processor address lines are connected to the two tag RAMs
directly to reduce the tag match delay. If the requested location
is found in the cache, the CYM7485 will return the first burst
word in the first T2 cycle. This is followed by three more words
delivered once every clock until the last word is returned or until
BLAST is asserted. START is pulled HIGH in T2 to signal a
cache hit to main memory and BRDYO is pulled LOW in T2 to
signal the processor that valid data is available from the cache.
BRDYO remains LOW until the last word is returned.
If the requested location is not in the cache, then the cache controller will assert START (LOW) to initiate the main memory access and deassert BRDYO (HIGH) to hold the processor.The
CYM7485 cannot accept data from main memory in zero wait
states.The earliest cycle in which main memory data is accepted is
the second clock cycle after START is asserted. The minimum
cache line fill sequence from main memory is 4/3/3/3.
BLAST is sampled concurrently with CBRDY and CRDY. If
BLAST is sampled LOW before the fourth data transfer, then the
line fill operation is aborted. Data from main memory is considered cachable if SKEN is sampled LOW at least one clock cycle
before CBRDY or CRDY is first asserted (LOW). If this condition is satisfied, the data returned from main memory will be
written into the cache each time CBRDY or CRDY is sampled
Law. If SKEN is sampled HIGH when the first CBRDY or
CRDY is sampled Law, or if SKEN is sampled LO~ conc~r
rently with the first CBRDY or CRDY, then the data IS conSidered to be non-cachable and the cache module will not act on the
information.
SKEN is sampled again at the end of the line fill to validate the
cache line. If SKEN is sampled LOW one cycle before the fourth
time CBRDY or CRDY is sampled Law, then the cache line will
be validated.
In order to process the read miss line fill correctly, ~ - A31 from
the processor must remain stable throughout the line fill. O~~er
wise, the cache tag will not be updated properly. In ~ddltlon,
SKEN must be LOW t14 before the end ofT2 and remam LOW
until the line fill is completed.
If the read access is not cachable, then SKEN will be sampled
HIGH after T2. The CYM7485 supports the following types of
non-cachable read accesses. If a single read hit is detected, then
the data word will be returned with BRDYO asserted. If a single
read miss is found, START will be asserted to begin the main
memory access. However, the data returned wil~ no~ be store?
into the cache memory and the selected cache hne IS not vahdated. If a burst read hit is detected, the cache module will treat
it in the same manner as a cachable burst read hit (i.e., four
words will be retrieved from the cache memory with BRDYO asserted). On the other hand, if a burst read miss is found, then
START will be asserted to begin the main memory access. However the four words returned by the main memory will not be
stor~d into the cache and the selected cache line is not invalidated. Table 2 illustrates the various cachable/non-cachable and
single/burst access combinations.
Table 1. Intel Burst Sequence
First Address
Second Address
Third Address
Fourth Address
0
4
8
C
4
0
C
8
8
C
0
4
C
8
4
0
8-197
8
tJ)
W
..J
::J
C
0
:E
PRELIMINARY
CYM7485
Table 2. Cachable/Non-cachable and Single/Bufst Read Access Combinations
SKEN
BLAST at end of T2
Action
Hit/Miss
0
0
Read hit
Cachable single read access. Cache module will return the word from its memory, assert
BRDYO, and then return to the idle state.
0
1
Read hit
Cachable burst access. This is the normal read hit case. Cache module will return 4 words
from its memory with BRDYO asserted. Less than 4 words will be returned if BLAST is
asserted before the end of the burst sequence.
1
0
Read hit
Non-cachable single read access. Cache module will return the word from its memory, assert
BRDYO, and return to the idle state.
1
1
Read hit
Non-cachable burst access. The cache module will process this access like a normal burst
read hit. The 4 words in the line will be returned with BRDYO asserted. Less than 4 words
will be returned if BLAST is asserted before the end of the burst sequence.
0
0
Read miss
Cachable single read access. Cache module will assert START and wait for CBRDY or
CRDY to complete the cycle. The selected cache line is invalidated.
0
1
Read miss
Cachable burst read access. This is the normal read miss case. The cache module will assert
START and wait for the 4 words to return from main memory accompanied by CBRDY or
CRDY. The words will be written into the cache memory and the cache line will be validated
when the fourth word is returned (because SKEN is LOW). If BLAST is asserted before the
fourth word is returned, the line fill is aborted and the selected cache line will remain
invalidated.
1
0
Read miss
Non-cachable single read access. The cache module will assert START and wait for CBRDY
or CRDY to complete the cycle. The word returned from main memory will not be stored
into the cache memory and the valid bit of the selected cache line is not changed.
1
1
Read miss
Non-cachable burst read access. The cache module will process this access like a normal
cachable burst read miss. START will be asserted but the 4 words returned from main
memory not will be stored into the cache. In addition, the valid bit of the selected cache
entry is not changed.
Write Cycles
A write cycle is initiated when ADS and CS are sampled LOW at
clock rise with WfR and M/lO sampled HIGH. The address from
the processor is latched for two clock cycles to allow cache RAM
update in case of a write hit. The latch then reopens to accept
new addresses.
Tag look-up begins as soon as a valid processor address is available. If the location specified by the processor is found in the
cache, the cache RAMs are updated with the data from the processor immediately. Byte enable signals BEO - BE3 are used to
determine which bytes in the 32-bit words are to be modified. If
the location is not found in the cache, the cache RAMs are not
modified.
Because the CYM7485 implements the write-through cache
policy, write data from the processor is always written into the
main memo~dless of cache hits or cache misses. In every
write cycle, START is asserted (LOW) in T2 to trigger the main
memory write operation.This signal will remain LOW until the
system indicates write completion by asserting (LOW) CBRDY
or CRDY. BRDYO is kept HIGH throughout the write cycle.
The minimum write cycle contains one wait state (i.e., three
clocks in the cycle) and the minimum data-hold time is 6 ns.
All write cycles require one wait state.
Invalidations
Individual tag invalidation is supported in the CYM7485. If
EADS, CS, and wfR are sampled LOW and MilO is sampled
HIGH at clock rise, then the tag entry selected by the processor
address is invalidated if a tag match is detected. In other words,
memory read cycles never cause invalidation. The address must
be stable a minimum of 14 ns before the clock edge at which
EADS is sampled Law.
The CYM7485 will recognize invalidation requests under two
conditions only:
1. Self invalidation during a write ~nitiated by asserting
ADS). The earliest time at which EADS can be asserted is the
third clock rise after the one clock cycle in which ADS is
sampled Law. For each invalidation, the address to be invalidated must be stable for two full clock cycles after EADS is asserted. CBRDY or CRDY can be asserted as early as the second clock rise after the one in which EADS is asserted to
complete the write cycle. The CYM7485 can support consecutive EADS invalidations once every three clock cycles before CBRDY or CRDY is returned. For consecutive write
cycles with self-invalidation, the CYM7485 can support one
such operation every six clock cycles (see Self-Invalidation
Timing Diagram).
2. When the cache module is in the "back-off" state (BOFFis asserted).The cache module can be placed in the "back-off"
state by asserting BOFF in all normal access cycles except in
T1. Once in the "back-off" state, the module can accept consecutive invalidations via CS and EADS once every three
clock cycles. The earliest time CS and EADS can be asserted
is the clock rise after the one in which BOFF is asserted. For
each invalidation, the address to be invalidated has to remain
stable for two full clock cycles after the EADS signal is asserted.
8-198
-,....
~
ilCYPRFSS
-=-,
PRELIMINARY
CYM7485
SEMICONDUCTOR
Flush
Reset
The CYM7485 cannot support global cache flushes where the entire cache is invalidated by the assertion of the FrUSH input. To
flush the cache in the CYM7485, the processor has to
1. Assert F'ITISll and AI')S" at clock rise (Le., F'UJSH=LOW
andAI5S=WW)withM}RJsettoHIGH,orassertATISand
deassert CS at clock rise (i.e., ADS = LOW and CS=HIGH)
with M}RJ set to HIGH. Note that <::S, ATIS, and Mt'IO must
satisfy the set-up time requirements (i.e., t8, t6, and t6 respectively).
2. Access (read or write) the 8K locations in the cache tag.
During each access, the cache module will invalidate the cache
entry selected by the address lines. The CYM7485 can accept
new flush accesses no faster than once every three clock cycles
(see the Flush Timing Diagrams). START and BRDYO will remain de asserted (HIGH) during flush cycles. CBRDY and
CRDY are not required to complete the flush cycle.
If RESET is sampled HIGH at clock rise, the cache controller
will enter the idle state and all module outputs will be de asserted.
The cache contents, however, are not invalidated. Refer to the
Flush section for information on cache invalidation.
Back-Off
A cache back-off can be initiated by the assertion of the BOFF in
any normal access cycles except in T1 where the BOFF signal is
ignored. Once BOFF is sampled LOW at clock rise, the data
lines will be placed in a three-stated condition in the same clock
cycle. In addition, both START and BRDYO will be pulled
HIGH. When BOFF is asserted, the cache module w~l ignsre all
cache cycles except RESET, invalidation via CS, AD, and
MOO, and flush operations via FLUSH, CS, ADS, and M/lO.
Maximum Ratings
(Above which the useful life may be impaired For user guidelines,
not tested.)
Storage Thmperature ................•.. -55°C to +125°C
Ambient Thmperature with
Power Applied .......................... -O°C to +70°C
Supply Voltage to Ground Potential ......... -O.5V to + 7.0V
DC Voltage Applied to Outputs
in High Z State .......................... -O.5V to +7.0V
DC Input Voltage ........................ -O.5V to + 7.0V
Output Current into Outputs (LOW) ............... 20 rnA
Operating Range
Range
Commercial
Ambient
Temperature
O°C to +70°C
Vee
5V±5%
I
Electrical Characteristics Over the Operating Range
CYM7485-33
Parameter
Description
Test Conditions
VOHD
Output HIGH Voltage (Data)
Vee=Min., IOH=-4.0 rnA
VOLD
Output LOW Voltage (Data)
Vee=Min., IOL=8.0 rnA
Min.
Max.
2.4
Unit
W
.J
V
::)
0.4
V
o
0.5
V
VOHe
Output HIGH Voltage (Control)
Vee=Min., IOH=-3.2 rnA
VOLe
Output LOW Voltage (Control)
Vee=Min., IOL=16 rnA
VIH
Input HIGH Voltage
2.2
Vee
V
-0.5
0.8
V
2.4
V
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND:::; VI:::; Vee, Vee=Max.
-10
+10
Ioz
Output Leakage Current
GND:::; VI:::; Vee, Output Disabled
-10
+10
fAA
fAA
Icc
Vee Operating Supply Current
Vee=Max., IOUT=O rnA, f=fMAX =1/tRe
1500
rnA
8-199
tn
C
:E
~PRFSS
PRELIMINARY
CYM7485
.nCONDUcrOR
AC Electrical Characteristics
(Vee
= 5.0V ± 5%, TA = 00 to 700C, loading on Do -
Symbol
tl
031
= 75 pF, loading on all other outputs = 50 pF)
Min.
30
Parameter
Clock Period
Max.
Unit
ns
t2
Clock HIGH Time
11
t3
Clock LOW Time
11
ns
ns
t4
A2 - A31, BEo - BE3 Set-Up Before Clock Rise
14
ns
t5
A2 - A31, BEo - BE3 Hold After Clock Rise
3
ns
t6
ADS, MilO, W/R Set-Up Before Clock Rise
14
ns
t7
ADS, MilO, W/R Hold After Clock Rise
3
ns
t8
CS, BLAST Set-Up Before Clock Rise
9
ns
3
ns
t9
CS, BLAST Hold After Clock Rise
tlO
BROYO Valid After Clock Rise
t11
BROYO Hold After Clock Rise
tl2
Do - 031 Valid After Clock Rise During Read Hit
tl3
Do - 031 Hold After Clock Rise
tl4
tl5
tl6
START Valid After Clock Rise
tl7
START Hold After Clock Rise
3
ns
tl8
Do - 031 Set-Up Before Clock Rise During Line Fill
10
ns
tl9
Do - 031 Hold After Clock Rise During Line Fill
15
ns
t20
CBROY, CROY Set-Up Before Clock Rise
14
ns
t21
CBROY, CROY Hold After Clock Rise
3
ns
t22
Do - 031 Set-Up Before Clock Rise During Processor Write Cycle
0
ns
t23
Do - 031 Hold After Clock Rise During Processor Write Cycle
6
ns
t24
EADS Set-Up Before Clock Rise
9
ns
t25
EADS Hold After Clock Rise
3
ns
t26
BOFF Set-Up Before Clock Rise
9
ns
t27
BOFF Hold After Clock Rise
3
t28
START Go HIGH After Clock Rise During BOFF or RESET
18
ns
t29
BROYO Go HIGH After Clock Rise During BOFF or RESET
18
ns
t30
00-031 High Z During BOFF
18
ns
t31
RESET Set-Up Before Clock Rise
9
ns
t32
RESET Hold After Clock Rise
3
ns
17
ns
ns
3
24
ns
3
ns
SKEN Set-Up Before Clock Rise
9
ns
SKEN Hold After Clock Rise
3
ns
17
ns
ns
t33
RESET Duration
+ 12
ns
t34
FLUSH Set-Up Before Clock Rise
9
ns
t35
FLUSH Hold After Clock Rise
3
ns
2 t2
8-200
.~~NDUcrOR
•
PRELIMINARY
CYM7485
:;::;;;;;;;;;::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;:::::::;;::::;::::
Switching Waveforms
Read Hit[l]
eLK
(HIGH)
BRDYO
I+- t10....j,
------+"-----.1.
~
I
,
,I
,
,I
1+--1
t11
'
Ir-_
1_
Ien
w
,
.....
,' - - -
..J
::l
C
o
:IE
7485-3
Note:
Reset is Law, EADS is HIGH, and BOFF is HIGH.
1.
8-201
~PRESS
_Ts~CONDUcrOR
PRELIMINARY
CYM7485' .
Switching Waveforms (continued)
Read Miss, Line Fill (Min. DRAM Access is 4/3/3/3)[2]
co
I
I
C1
I
I
C3
C2
CLK
7485-4
Notes:
2. Reset is LOW, EADS is HIGH, BOFF is HIGH, and CRDY is HIGH.
3. BLAST is LOW t8 before the rising edge of clock period Cil.
8.-:202
~
;~PRESS
.
,
PRELIMINARY
SEMICONDUcrOR
CYM7485
;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;,;;;;;;;;;;;;;;;;:;
Switching Waveforms (continued)
Write Cycle[4]
1
1
1
1
1
~I__~
CLK~'
j.-t6+t7-1
I
I
1
ADS
I
1
I
I
j.- t8 -----I- t9 -I
1
csW///I
1
I
1
1
.
i
1
WWffil/$~p0'74
j.- t6 ---J..- t7 -I
1
1
I
BRDYQ
00-0"
1
1
1
1
t2~~
1
1
1
1
1
1
~t23
j/ff~ff~///IU
1
1
CBRDY
OR CRDY
(HIGH)
I
I
I
I
I
I
Note:
4. Reset is Law, CBRDY is HIGH, EADS is HIGH, BOFF is HIGH.
Access to DRAM must be a minimum of 3 cycles.
8-203
1
1
D<074'ff//ft'~
t20
I.
.1.
1
I
I
.1r------+o-I
t21
1
_ _ __
I
I
I
7485-5
~~
PRELIMINARY
~ICYPRESS
~, SEMICONDUCTOR
CYM7485
Switching Waveforms (continued)
Write Cycle with Self-Invalidation[5]
1
1
1
CO
1
C1
C2
C4
C3
C7
C6
C5
C8
ClK
~$
i ~~
i _~
i t4~~
1 j.- t4 -I
H t5 I.j.-- t4.J
1
t5 ....
1
A,-Aao?f<
1
EADS
START
1
1
1
1
1
1
i i~
1
1
1
1+ t16 -+I
1
i
-r t7 .j
I. I
1
I
·
j.. t6
1
I
1
~
1
1
1
1
1
CBRDY
I
I
OR C R D Y ! !
I
1
1
j..
i iX0< i
1
I
I.
1
j.-~
t2°I'_
1
I
1
j+---+j t171
1
1
I
1
1
1
Ii-1
li't21!
1
i
1
I
1
1
1
1
1
!
1
. ! !
7485-6
Note:
5. Reset is LOW. There is a minimum of 3 clocks between ADS and
EADS, a minimum of two clocks between EADS and CBRDY or
CRDY, a minimum of three clocks between consecutive EADS inside
the same write cycle, and a minimum of 6 clocks between consecutive
ADSs.
8-204
~
. ;~~PRESS
--=-,
PRELIMINARY
SEMICONDUCTOR
CYM7485
========================================
Switching Waveforms (continued)
Single Non-Cachable Read (Cache Hit) [6]
elK
~
I
I
I
I
I
I
I
00-0"
I
I--t6~t7-1
(HIGH)
(HIGH)
I
I
l
~t12----1
I
I
I
I
I
I
I
i--t13---.j
~/$ff$/////0(!
I
I
I
I
I
.
I
I
t10
I-
-II
I
!
Note:
6. Reset is LOW.
8-205
I
I
I
en
I
::l
w
...J
I
Q
>WMd$~/Z
t11
-I
I
I
II
I
I
II
7485-7
o
:E
PRELIMINARY
CYM7485
Switching Waveforms (continued)
Single Non-cachable Read (Cache Miss) Showing a Four-Clock Main Memory Access
I
I
STAAT
(HIGH)
I
I--t16---1
-+1----+1------,'
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
j.- t20 ..,.... t21
I
I
I
I.
I
~ t17
t18
I.
Do~D31 fIV///////.&///////4'II//////f!0<
CBRDY or
CRDY
I
I
I
I
I
I
.1.
i
I
I
.
.1
t19
I
I
I
><'#0
I
-+l
I.
I
I
7485-8
8-206
RT
;~PRESS
~,
PRELIMINARY
CYM7485
SEMICONDUcrOR
Switching Waveforms (continued)
Flush Cycle 1[7, 8]
II
I
CLK~
I
t34 ,.
I
I
I
FLUSH
I
I
I
I
ADS
_,
t35
t34 ,-
I
1
j+-t6+t7-+/
1.
I
I
I+- t4 --J
M~ 0/W~
!
I
I
I
I
I
I
I
I
I
!- t6 -..I.- t7 -1
_I_
I
I
L
-, t35
~---
!-t6+t7--1
1
I
.. --., V4X
I
_I.
I
I
I
t5
H
1
I
I
I-- t4 --I
.-I
I )@<,....--t--lI- t6 - ' - t7 ---I
I
I
I
I
I
I
I
I
I
I
I
w/h///~~
W
I
7485-9
I'
Flush Cycle 2[8, 9]
(/J
I
eLK
-l
I
I
I
I
I
W
..J
~
---'L
o
o
"""'-1
I
I
:E
I
7485-10
Notes:
7. Controlled by FLUSH, ADS, and MOO; CS is a don't care.
8. A minimum of three clocks between consecutive ADS signals is required during Flush cycles. Reset is LOW.
9. Controlled by CS, ADS, and MOO; FLUSH is a don't care.
8-207
.
·
fiA
~
PRELIMINARY
CYPRESS
SEMICONDUCI'OR
CYM7485
Switching Waveforms (continued)
Consecutive Invalidations During BOFF[lO]
elK
1
I
ATIS
Mho/A] .
1
EADS
1
A2- A 31
-r-'?'11~7/"""-+;{0~~
t26U
BOFF
1
11
I
1
I
I II--tS~t9--i
I I I
~//1 i w!4JII//l
i
I-- t24 -+- t25 ~
---+:-"""1
1
I
j4-tS±t9-\
1
ell
i
1
1
1
i 1(jl ,. .,- .:.---
iii
1
I
I
1
1
1
1
I
I-- t6""" t7
--I
~ t24 T" t25 ~
1
1
I--t4-,
1
t5
H
t4
l>@Oi
1
1
I
1
1
I
1
1
1
t6
I-
I
-I-
1
1
-I
I
t7
1
7485-11
Note:
10. Reset is Law. There is a minimum of three clocks between EADS,
and a minimum of one clock between BOFF and EADS.
8-208
~
~~PRESS
~, SEMICONDUCTOR
CYM7485
PRELIMINARY
Switching Waveforms (continued)
BackotT Operation[llj
ClK
t26
BOFF
1
I
START
BRDYO
DO - 031
t------!
\4--1
------I I
t27
I -I--
_--1-
~'~I------~------TI~'
I
I-- t28 +I
I
j4- t29--1
I
i
i
1
I
I
~xj¢W/!ZVA1
W_47A
j . - t30
I
---I
)>--i----------r----7485-12
Ien
Reset Operation
1
ClK
I-
t33
1
I
:::)
C
o
:E
t32
t28
START
w
..J
I
I
L...-----II
,'---_
I
I-- -I
I+-----l
I
I I
I I
I
~ ~
I
W/I/&///I/I//yM
I
I
I
W$(7////////lff41
i
t31
RESET
-I
1...-.---
\..t29~
"ROYO
I
I
I
I
1
I
7485-13
Note:
11. Reset is LOW.
8-209
.r~
PRELIMINARY
CYM7485
Ordering Information
Operating Frequency
(MHz)
Ordering Code
Package
Name
33
CYM7485ZPM - 33C
PM08
Document #: 38-M-00058-A
8-210
Package 'fYpe
128-Pin Dual-Readout SIMM
Operating
Range
Commercial
CYM7490
CYM7491
CYM7492
PRELIMINARY
CYPRESS
SEMICONDUCTOR
i486 Level II Cache Module
Family
Features
Functional Description
• Cache sizes of 64 KB, 256 KB,
orlMB
• Tag width of 8 bits
• Independent dirty bit
• Operates with 33-MHz Intel i486
processors
• Zero-wait-state operation
• Constructed using standard asynchronous SRAMs
• 64-position (128-signal) dual-readout
SIMM
• Single 5V (±5%) power supply
• TTL-compatible inputs/outputs
The CYM7490 module series is a family of
cache memory subsystems for Intel
i486-based systems. Each module contains
two banks of 32-bit-wide data SRAM, an
8-bit-wide tag SRAM, and a single-bitwide, separate I/O dirty SRAM. Banksizes
of 8Kx 32, 32Kx 32, and 128Kx 32 are supported, yielding cache sizes of 64 kilobytes,
256 kilobytes, and 1 megabyte. The address signals for the data and dirty SRAMs
are latched.
The module is configured as a 128-pin
dual-readout single-in-line memory module (SIMM). It is constructed using standard asynchronous SRAMs in SO] pack-
ages mounted on an epoxy laminate substrate. The SIMM contacts are plated with
five micro-inches of gold over 100 microinches of nickel. Module dimensions are
3.85 inches long by 1.15 inches high by 0.33
inches thick.
These modules are designed for zero-waitstate operation in 486-based systems operating at a bus speed of 33 MHz. They are
designed for compatibility with off-theshelf cache controllers and chipsets. The
15-ns device is built using data and tag
SRAMs with an access time of 15 ns, while
the 20-ns version is built with 15-ns tag
SRAMs and 20-ns data SRAMs.
Logic Block Diagram
ADDRESS LATCH
HA 19-4
D
Q
DATASRAMs
I
HACALE
LE
HA3Bo
CACSo
"COOEo
DATA BANKO
A
An
OE
HD[31-01
D
CS
UJ
W
...J
::l
WE
WE
WE
C
WE
0
:E
A
An
CS
OE
WE
WE
WE
WE
DATA BANK 1
CAWE[3-01
~----------------------------~~ A
DI~!-----
DiR'f"YWE
___+-__________________________________--I~ WE DO
DIRTYIN
DIRTYOUT
~----------------------------~~ A
TAGWE
D ~(----------------------------II. TAG [7-01
-----------------------------------4 WE
TAG (BITS)
8-211
7490-1
.:~~~
~_,
CYM7490
CYM7491
CYM7492
PRELIMINARY
SEMICONDUCTOR
Dual-Readout SIMM
Top View
GND
PDo
PD2
NC
NC
NC
GND
NC
TAG 7
GND
PD l
PD3
NC
NC
NC
GND
NC
TAG6
Vee
Vee
TAG 5
TAG3
GND
TAG 1
DIRTYWE
TAG 4
TAG2
GND
TAG o
TAGWE
Vee
Vee
DIRTYIN
HACALE
GND
DIRTYOUT
NC
GND
HA5
HA7
H~
HAs
Vee
Vee
HAS
HAlO
GND
HA12
HA14
88
89
90
91
Vee 92
HA16
93
94
HA18
GND
95
"CACSo 96
NC
97
HA380
98
GND
99
CiJ"OEo
100
GND C 101
CAWEo
102
GAWE2
103
GND
104
HDo C 105
HD2
106
Vee 107
HD4 C 108
HD6 C 109
GND C 110
HD8
111
HD 10
112
Vee 113
HD12 C 114
115
HD14
GND
116
117
HD16
118
HD 18
Vee C 119
HD20 C 120
HD22 C 121
GND C 122
123
HD24
HD26 C 124
Vee C 125
HD28 C 126
127
HD30
GNDq128
HA9
HAll
GND
HA13
HA15
Vee
HA17
HA19
GND
"CACSl
NC
HA381
GND
CiJ"OEl
GND
GAWEl
GAWE3
GND
HDl
HD3
Vee
HD5
HD7
GND
HD9
HDll
Vee
HD13
HD15
GND
HD17
HD19
Vee
HD2l
HD23
GND
HD25
HD27
Vee
HD29
63
HD3l
64p GND
8-212
7490-2
~
=:: i~PRESS
~,
PRELIMINARY
CYM7490
CYM7491
CYM7492
SEMICONDUCTOR
Signal Descriptions
Signal
Type
Description
TAG7-0
I/O
Cache Tag Data Bus
TAGWE
I
Tag Write Enable
DIRTYWE
I
Dirty Bit Write Enable
DIRTYIN
I
Dirty Bit In
DIRTYOUT
a
Dirty Bit Out
HACALE
I
Host Address Bus Latch Enable
HA19-4
I
Host Address Bus.
CACSI-O
I
Cache Memory Chip Selects
HA3BI-O
I
Host Address A3 Bank Select
CDOEI-O
I
Cache Data Output Enable
CAWE3-0
I
Cache Write Enables
HD31-0
I/O
Host Data Bus
PD3-0
a
Presence Detect Pins (see below)
NC
-
Reserved for future use.
Presence Detect Scheme
Device
PD3
PD2
PDl
PDO
CYM7490
Open
Open
Open
GND
CYM7491
Open
Open
GND
Open
CYM7492
Open
Open
GND
GND
I
UJ
W
..J
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
:::l
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ....................... - O.5V to +7.0V Q
Storage Temperature .................. - 55°C to + 150°C
8-213
o
==
~PRFSS
'nCONDUcrOR
CYM7490
CYM7491
CYM7492
PRELIMINARY
Electrical Characteristics Over the Operating Range
CYM7490-15,20
CYM7491-15,20
CYM7492-15, 20
Parameter
Description
Test Conditions
Vee
Supply Voltage
TAMB
Ambient Temperature
Commercial
VOH
Output HIGH Voltage
Vee = Min. IOH = -4.0 rnA
VOL
Output LOW Voltage
Vee = Min. IOL = 8.. 0 rnA
VIH
Input HIGH Voltage Level
Input LOW Voltage Level
VIL
LIN
Input Leakage Output
Vee = Max., O~ VIN~VSS
lOUT
Operating Leakage Current
CS=VIH, Vee=Max.,
Min.
Max.
4.5
5.5
V
0
70
°C
2.4
Unit
V
0.4
V
2.2
Vee
V
-0.5
0.8
V
±20
±20
!!A!!A-
Vss:::;;Vo~Vee
leCl
Operating Current
CACSn = VIL, Outputs Open, f=fMAX
1300
rnA
ISBl
Standby Current· - TTL
Levels
CACSn 2:: Vee -0.2, Vee = Max.,
Vee -0.2 ~ VIN ~ 0.2, Outputs Open
800
rnA
ISB2
Standby Current - CMOS
Levels
CACSn 2:: Vee -0.2, Vee = Max.,
V ee-O.2 ~VIN~ 0.2, Outputs Open
400
rnA
Capacitance
Max.
Unit
CADDR
Input Capacitance, HA19-4, CAA31-O
f=l MHz
50
pF
CWE
Input Capacitance, CAWEI-O, TAGWE
f=l MHz
30
pF
CWE2
Input Capacitance, DIRTYWE, HACALE
f-1 MHz
20
pF
CeSOE
Input Capacitance, CACSI-O,
CDOEI-O
f=l MHz
50
pF
CDATA
Input/Output Capacitance, HD31-0
f=l MHz
90
pF
CTAG
Input/Output Capacitance, TAG7-0,
DIRTYIN, DIRTYOUT
f=l MHz
30
pF
Parameter
Description
Test Conditions
AC Test Loads and Waveforms
481Q
OUTP~~ ~
1· 1_
,,,~~:F J
INCLUDING
JIG AND
SCOPE
OUTP~~ ~
-
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
3.0V---90%
1 1-
,,,,.~:F J
2550
-
ALL INPUT PULSES
481Q
2550
-
-
(b)
7490-3
THEVENIN EQUIVALENT
OUTPUT~
1.73V
8-'-214
GND
7490-4
CYM7490
CYM7491
CYM7492
~
~PRFSS
~.. SEMICONDUcrOR
PRELIMINARY
Switching Characteristics Over the Operating Range
7490-15
7491-15
7492-15
Parameter
Description
Min.
7490-20
7491-20
7492-20
Max.
Min.
Max.
Unit
ADDRESS LATCH
tLPW
Latch Pulse Width
5
5
ns
tLSD
Data Set-Up to ALE Positive
2
2
ns
tLHD
Data Hold from ALE Positive
1.5
1.5
ns
READ CYCLE - Data SRAM Read Timing
tRC
Read Cycle Time
tAA
Address Access Time (Latch Transparent)
20
20
25
ns
tOE
Output Enable to Output Valid
10
10
ns
tCE
Chip Enable to Data Valid
15
20
ns
25
tOHA
Data Hold After Address Change
3
3
tLZCE
Chip Enable to Outputs in Low Z
3
3
tHzCE
Chip Disable to Outputs in High Z
toLZ
Output Enable to Output in Low Z
tOHZ
Output Diable to Outputs in High Z
8
0
ns
ns
ns
10
ns
10
ns
0
8
READ CYCLE - Tag SRAM Read Timing
tTDRC
Read Cycle Time
tTAA
Address Access Time
15
15
20
ns
tTCE
Chip Enable to Data Valid
15
20
ns
tTOHA
Data Hold After Address Change
tTLZCE
Chip Enable to Outputs in Low Z
tTHZCE
Chip Disable to Outputs in High Z
20
3
ns
3
3
ns
3
8
ns
8
ns
READ CYCLE - Dirty SRAM Read Timing
tDRC
Read Cycle Time
tDAA
Address Time
tDOHA
Data Hold After Address Change
20
25
20
ns
25
ns
3
3
ns
20
25
ns
WRITE CYCLE - Data SRAM Write Timing
twc
Write Cycle Time
tSCE
Chip Enable to End of Write
10
15
ns
tAW
Address Set-up to End of Write
20
25
ns
tAR
Address Hold from End of Write
0
0
ns
tSA
Address Set-Up from Beginning of Write
5
5
ns
tpWE
Write Pulse Width
10
. 15
ns
tSD
Data Set-Up to End of Write
7
10
ns
tHD
Data Hold from End of Write
0
0
ns
tLZWE
Write High to Outputs in Low Z
3
3
ns
tHZWE
Write Low to Outputs in High Z
7
8-215
10
ns
I
en
w
..J
::l
C
o
:E
~~PRFSS
~,
CYM7490
CYM7491
CYM7492
PRELIMINARY
SEMICONDUcrOR
Switching Characteristics (continued)
7490-15
7491-15
7492-15
Parameter
Description
Min.
7490-20
7491-20
7492-20
Max.
Min.
Max.
Unit
WRITE CYCLE - Tag SRAM Write Timing
Write Cycle Time
15
15
ns
tTSCE
Chip Enable to End of Write
10
10
ns
tTAW
Address Set-Up to End of Write
10
10
ns
tTAR
Address Hold from End of Write
0
0
ns
tTSA
Address Set-Up from Beginning of Write
0
0
ns
tTPWE
Write Pulse Width
10
10
ns
tTSD
Data Set-Up to End of Write
7
7
ns
tTHD
Data Hold from End of Write
0
0
ns
tTLZWE
Write High to Outputs in Low Z
3
3
tTHZWE
Write Low to Outputs in High Z
tTWC
7
ns
7
ns
WRITE CYCLE - Dirty SRAM Write Timing
tDWC
Write Cycle Time
20
20
ns
tDAW
Address Set-Up to End of Write
17
17
ns
tDAR
Address Hold from End of Write
0
0
ns
tDSA
Address Set-Up from Begining of Write
5
5
ns
tDPWE
Write Pulse Width
12
12
ns
tDSD
Data Set-Up to End of Write
10
10
ns
tDHD
Data Hold from End of Write
0
0
ns
tDLZWE
Write High to Outputs in Low Z
5
5
ns
tDHZWE
Write Low to Outputs in High Z
7
7
ns
Ordering Information
Speed (ns)
Ordering Code
Package
Name
Package lYpe
Cache
Size
64 Kbyte
15 (Data and TaglDirty)
CYM7490PM -15
PM05
128-Pin Dual-Readout SIMM
20 (Data), 15 (TaglDirty)
CYM7490PM-20
PM05
128-Pin Dual-Readout SIMM
Speed (ns)
Ordering Code
Package
Name
Package lYPe
15 (Data and TaglDirty)
CYM7491PM -15
PM06
128-Pin Dual-Readout SIMM
20 (Data), 15 (TaglDirty)
CYM7491PM-20
PM06
128-Piil Dual-Readout SIMM
Speed (os)
Ordering Code
Package
Name
Package lYPe
15 (Data and ThglDirty)
CYM7492PM -15
PM07
128-Pin Dual-Readout SIMM
20 (Data), 15 (TagIDirty)
CYM7492PM-20
PM07
128-Pin Dual-Readout SIMM
Document #: 38-M-00061
8-216
Cache
Size
256 Kbyte
Cache
Size
1 Mbyte
INFO
I'
SRAMs
II
PROMs
U
I'
PlDs
FIFOs
Ii
lOGIC
"Ii
DATACOM
MODULES
.:.
ECl
E'
BUS
1..1
MiliTARY
1"
TOOLS
ItJ
QUALITY
IE)
PACKAGES
Ii'
=a.:~
Section Contents
~.CYPRESS
~, SEMICONDUcrOR
EeL
Device Number
CYlOE383
CYlOIE383
CYlOE384L
CY10E422
CY100E422
CYlOE470
CYlOOE470
CY10E474
CY100E474
CY10E484
CY100E484
CY101E484
Page Number
Description
ECLtrrL/ECL 1tanslator and High-Speed Bus Driver . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
ECLtrrL/ECL Translator and High-Speed Bus Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1
ECLmL/ECL ltanslator .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-8
256 x 4 ECL Static RAM ...................................................... 9-13
256 x 4 ECL Static.RAM ... '.' ...................... ' ... '........................ 9-13
4Kx1ECLStaticRAM ....................................................... 9-20
4Kx 1 ECL Static RAM ....................................................... 9-20
1Kx 4 ECL Static RAM ....................................................... 9-25
1K x 4 ECL Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 9- 25
4Kx 4 ECL Static RAM ....................................................... 9-32
4Kx 4 ECL Static RAM ....................................................... 9-32
4Kx 4 ECL Static RAM ....................................................... 9-32
CYIOE383
CYIOIE383
CYPRESS
SEMICONDUCTOR
ECL/TTL/ECL Translator and
High-Speed Bus Driver
Features
Functional Description
• BiCMOS for optimum speed/power
• High speed (max.)
- 2.5 ns tpD TTL-to-ECL
-3.5 ns tpD ECL-to-TTL
• Low skew < ± 1 ns
• Can operate on single +SV supply
• Full-duplex ECL{fTL data transmission
• Internal 2 kQ ECL pull-down
resistors on each ECL output
• SO-pin PQFP package
• Surface-mount PLCC/CLCC package
• VBB ECL reference voltage output
• Single- or dual-supply operation
• Capable of greater than 2001V ESD
• ECL cable/twisted pair driver
The CY10/101E383 is a new-generation
TIL-to-ECL and ECL-to-TIL logic level
translator designed for high-performance
systems. The device contains ten independent TIL-to-ECL and ten independent
ECL-to-TIL translators for high-speed
full-duplex data transmission, mixed logic,
and bus applications. The CYlO/10lE383
is especially suited to drive ECL backplanes between TIL boards. The
CYlO/lOlE383 is implemented with differential ECL I/O to provide balanced low
noise operation over controlled impedance
buses between TIL and/or ECL subsystems. Inaddition, the device has internal
output 2 kQ pull-down resistors tied to
VEE to decrease the number of external
components. For system testing purposes
or for driving light loads, the 2 kQ is used as
the only termination thereby eliminating
Logic Block Diagram
"-
>
D12
">
013
">
0f3
>
>
14
8*
015
DIFFERENTIAL
015 ECLOUTPUTS
016
">
me
017
D1B
">
">
D19
">
019
TILVCC
TIL 03
TILGND
TIL 02
TILVCC
10E383
101E383
ECLVBB
ECLVCC
12
~
D14
TILGND
TIL 04
ECLD5
ECLOS
ECLD6
ECL IJ6
ECLD7
ECL07
ECLDB
ECLDB
ECLD9
ECLD9
010
OW
011
Off
D13
D17
Top View
01
J)3
TIL INPUTS D15
TIL SUPPLY
D16
PLCC/CLCC
VBB
00
Of
~
D10
up to 20 external resistors. The part meets
standard lOK/lOKH and lOOK logic levels
with the internal pull-down while driving
SOQ to -2Y.
The device is designed with ample ground
pins to reduce bounce, and has separate
ECL and TTL power/ground pins to reduce noise coupling between logic families. The parts can operate in single- or
dual-supply configurations while maintaining absolute 10K/lOKH and 100Klevel
swings. The translators are offered in standard 10K/lOKH (lOE) and lOOK (lOlE)
ECL-compatible versions with - S.2V or
- 4.5V power supply. The TIL I/O is fully
TIL compatible. The CYlO/101E383 is
packaged in 84-pin surface-mountable
PLCCs and CLCCs. To save board space,
an 80-pin PQFP package with 2S-mil-lead
pitch is available.
ECLSUPPLY
017
01B
018
019
TIL 01
TILGND
TIL 00
ECL010
ECLOW
TILGND
TILD19
TILD1B
TILD17
ECLVCC
ECL011
ECLOff
ECLVCC
TILD16
TILD15
TILD14
TILD13
ECL012
ECLID2
ECLVCC
TILD12
TILD11
TILD10
~i ~i~i~i
E3B3-1
E383-2
Note 1
Notes:
1. The PQFP package has one less each TIL Vee and TIL GND pin and two less EeL Vee pins.
9-1
II
...I
(.)
U.I
CYIOE383
CYIOIE383
'.;~PRRSS
~J,. SEMICONDUCTOR
Pin Configurations (continued)
PQFP
Top View
MNnnro~nnnnm~~~oo~~ro~~
ECLD5
ECL05
ECLD6
ECL06
ECLD7
60
59
58
57
56
ECL07
ECLD8
ECL08
ECLD9
ECL OS
55
54
10E383
101E383
ECLVBB
ECLVCC
ECL010
ECLOTO
TIL 04
TILVCC
TIL 03
TILGND
TIL 02
TILVCC
TIL 01
53
52
TILGND
TIL 00
51
50
49
48
47
TILGND
TILD19
TILD18
TILD17
ECLVCC
ECL011
ECL lTIT
ECL012
ECL012
46
45
44
43
ECLVCC
ro~~~M~~V~~~~~~~~~~~~~~
TILD16
TILD15
TILD14
TILD13
TILD12
TILD11
TILD10
42
E383·3
Selection Guide
lOE383-2
lOlE383-2
2.5
3.5
270
Maximum Propagation Delay Time (ns) (TTL to ECL)
Maximum Propagation Delay Time (ns) (ECL to TTL)
Maximum Operating Current (rnA) Sum of lEE and Icc
lOE383-3
lOlE383-3
3
4
270
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Operating Range
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
TTL Supply Voltage to Ground Potential .. - O.5V to +7.0V
TTL DC Input Voltage ................. - 3.0Vto +7.0V
ECL Supply Voltage VEE to ECL Vee .... -7.0V to +O.5V
ECL Input Voltage ........................ VEE to +O.5V
ECL Output Current .......................... - 50 rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current ........................... > 200 rnA
9-2
Ambient
Version Thmperature
Range
I/O
Commercial
10K
10KH
lOE
O°Cto
+75°C
Commercial
lOOK
lOlE
O°Cto
+85°C
Military
10K
lOKH
lOE
-55°C
to +125°C
case
EeL
TTL
VEE
-5.2V
±5%
Vee
5V±
5%
-4.2Vto 5V±
-5.46V
5%
-5.2V
±5%
5V±
5%
CYIOE383
CYIOIE383
~
.
;~PRESS
"""=='?
SEMICONDUcrOR
ECL Electrical Characteristics Over the Operating Rangel2]
Parameter
VOH
Description
Output HIGH Voltage
Temperature[3]
Test Conditions
lOE, RL = 500 to - 2V
Tc = -55°C
VIN =VIRMin.orVILMax.
TA = O°C
= +25°C
TA = +75°C
Tc = +125°C
TA = O°C to 85°C
TA
Output LOW Voltage
VOL
10lE RL = 500 to - 2V,
VIN =VIRMin.orVILMax.
10E, RL = 500 to - 2V
Tc
VIN =VIR Min. orVILMax.
VIR
Input HIGH Voltage
-1260
-1170
-1130
-1070
-1030
-900
-840
-810
-720
-700
Input LOW Voltage
VBB
Output Reference
Voltage
V cm l5J
Common Mode Voltage
Input Voltage
Differential
Input HIGH Current
Input LOW Current
Pull-Down Resistor
101E
lOE
-1950
-1950
-1950
-1950
-1950
-1540
-1480
-1475
-1450
-1450
lOlE
lOEl4J
lOlEl4J
Vdiff
IIR
IlL
RpD
±Vcm with respect to VBB
Required for Full Output
Swing
VIN = VIR Max.
VIN = VILMin.
Connected from All ECL TA = O°C to 75°C
Outputs to VEE
Tc = -55°C to
+125°C
TA
lEE
9-3
-1810 -1620
mV
mV
mV
mV
mV
mV
-1670
-1665
-1650
-1625
-1610
-880
-1810 -1475
-1.18
-1.32
-1.14
-1.40
1.0
150
-0.5
1.6
1.6
-1.23
1.0
150
220
170
2.4
2.4
= O°C to 85°C
-0.5
1.6
-180
Supply Current (All inputs and outputs open)
-880
-1165
-1.37
-1.46
-1.29
Unit
mV
mV
mV
mV
mV
mV
-1025
= -55°C
= O°C
TA = +25°C
TA = +75°C
Tc = +125°C
TA = O°C to 85°C
Tc = -55°C
TA = O°C
TA = +25°C
TA = +75°C
Tc = +125°C
TA = O°C to 85°C
TA = O°C to 75°C
Tc = -55°C
Tc = +125°C
TA = O°C to 85°C
101E RL = 500 to - 2V,
VIN = VIR Min. or VILMax.
lOE
Tc
lOlE383
Min.
Max.
-840
-810
-735
-700
-1920
-1870
-1850
-1830
-1830
TA
VIL
-1000
-960
-900
-880
= -55°C
= O°C
TA = +25°C
TA = +75°C
Tc = +125°C
TA = O°C to 85°C
TA
--
lOE383
Min.
Max.
-1140 -900
220
170
2.4
-180
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
V
V
mV
J.lA
/-lA
kO
rnA
I
..J
oLLI
CYIOE383
CYIOIE383
tis?~a==
TTL Electrical Characteristics Over the Operating Range[2]
lOE383
lOlE383
Parameter
Description
Test Conditions
Min.
Max.
Unit
2.4
Output HIGH Voltage
Vee = Min., IOH = -3.2 rnA
VOL
Output LOW Voltage
Vee = Max., IOL = 16.0 rnA
VIH
Input HIGH Voltagel6]
VIL
Input LOW Voltage[S]
Veo
Input Clamp Diode Voltage
lIN = -lOrnA
-1.5
loS[7]
Output Short-Circuit Current
Vee = Max., VOUT = 0.5V[8]
-180
-40
Ilx
Input Load Current[9]
GND~VI~Vee
-250
+20
!LA
Icc
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA, f = f max.
90
rnA
VOH
V
0.5
V
2.0
V
0.8
V
V
rnA
Capacitance
Parameter
Description
CIN171
Test Conditions
Max.
Unit
4
pF
5
pF
Input Capacitance
Output Capacitance
COUTUj
TTL AC Test Load and W~veform[lO]
R1 2380 (3190 MIL)
5V
OUTPUT
3.0V
0---..--""'"
90%
GNO
R2
1700
(2360 MIL)
CLPFI
-----::TI"------s...
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
E383-5
E383-4
THEVENIN EQUIVALENT (Commercial)
990
OUTPUT OO---"I-'''''''''''''--,()O
THEVENIN EQUIVALENT (Military)
1360
OUTPUT 000----'\·.,.,
..........- - 0 0
2.08V
2. 13Vthm
EeL AC Test Load and Waveform[ll, 12, 13, 14, 15, 16]
GND
INPUT
ALL INPUT PULSES
V
IH - - - - - - ; - ~-------_I
Vcc,VCCO
80%
20%
DoUT
VEE
0.01 IlFJ.
-2.0V
VEE
E383-6
E383-7
Notes:
2. See AC Test Load and Waveform for test conditions.
3. Commercial grade is specified as ambient temperature with transverse
air flow greater than SOO linear feet per minute. Military grade is specified as case temperature.
4. Max. IBB = -1 mAo
S. The internal gain of the CY101/lOE383 guarantees that the output
voltage will not change for common mode signals to ± IV. Therefore,
input CMRR is infinite within the common mode range.
6. These are absolute values with respect to device ground.
7. Characterized initially and after any design or process changes that
may affect these parameters.
8. Not more than one output should be tested at a time. Duration of the
sh.ort should not be more than one second.
9. I/O pin leakage is the worst case of IIX (where X = H or L).
10. TTL test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.S V, input pulse levels of 0 to 3.0V, and output
loading of the specified Im)loH, and CL = 10 pR
11. VIL = VIL Min., VIH = VIH Max. on lOKH version.
12. VIL = -1.7Y, VIH = -0.9Von 100E version
13. ECL RL = SOQ CL < S pF (includes fixture and stray capacitance).
14. All coaxial cables should be SOQ with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
IS. tr = tf = 0.7 ns
16. Ali timing measurements are made from the 50% point of ali waveforms.
9-4
CYIOE383
CYIOIE383
~
~~PRFSS
~, SEMICONDUcrOR
ECL·to·TTL Switching Characteristics Over the Operating Range
lOE383-2
lOlE383-2
Parameter
Description
lOE383-3
lOlE383-3
Test Conditions
Min.
Max.
Min.
Max.
Unit
tpLH
Propagation Delay Time
D n, Dn to On
1
3
1
4
ns
tpHL
Propagation Delay Time
D n, Dn to On
1
3
1
4
ns
TTL·to·ECL Switching Characteristics Over the Operating Range
lOE383-2
lOlE383-2
Parameter
Description
lOE383-3
lOlE383-3
Test Conditions
Min.
Max.
Min.
Max.
Unit
tpLH
Propagation Delay Time
Dn to On, On
1
2.5
1
3
ns
tpHL
Propagation Delay Time
Dn to On, On
1
2.5
1
3
ns
tr
Output Rise Time
20% to 80%
0.35
1.7
0.35
1.7
ns
tf
Output Fall Time
20% to 80%
0.35
1.7
0.35
1.7
ns
Skew Time Switching Characteristics (Same test conditions as TTL-to-ECL and ECL-to-TTL Electrical Characteristics)
Symbol
Test Conditions
Characteristic
tSKT[7]
Data Skew Time ECL-to-TTL
tSKE[7]
Data Skew Time TTL-to-ECL
Min.
Max.
Unit
TTLO n to TTLO n+m
1
ns
ECLO n, On to ECLO n+m, On+m
1
ns
Switching Waveforms
ECL-to-TTL Timing
--)~I+--"~-~ tpLH ~·1 _ _ _~_·YOO_~_","L=-1
--------------.. . .1/'
1.5V
II
~
E383·8
TTL-to-ECL Timing
=*
~.
r- PLH _.
l
______________'_
15VL
F-tPHL-=-t.- - - -
_5_0_%____~------------------~-5-00-Yo--------E383-9
9-5'
...I
(.)
LIJ
CYIOE383
CYIOIE383
1ir~~
Switching Waveforms (continued)
Skew Test (tSKT)
TTLQn-to-TTLQn+m
(0tSKT~ ...---____l=_;_5V-ts_KT-=:1-1-.5V-
~
-------------J 1.5V
E383-10
Skew Test (tSKE)
ECLQR! Qn-to-ECLQn+m, Qn+m
Qn+m(ECL)
50%
50%
On+m(ECL)
E383-11
Table I. CYIOIE383 Nominal Voltages Applied in lOOK System
ECL-to-TTL Truth Table
Inputs
Outputs
ECLD n
ECLDn
TTLQn
Open[17]
Open[17]
L
L
L
H
H
L
H
Note:
17. The EeL inputs will pull to a known logic level if left open.
Supply Pin
Single-Supply
System
Dual-Supply
System
TIL Vee
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECLVee
+S.OV
O.OV
ECLVEE
O.OV
-4.5V
Table 2. CYIOIE383 Nominal Voltages Applied in 101K System
TTL-to-ECL Truth Table
Inputs
Outputs
Supply Pin
Single-Supply
System
Dual-Supply
System
TTLDn
ECLQn
ECLQn
TIL Vee
+S.OV
+S.OV
L
L
H
TILGND
O.OV
O.OV
H
H
L
ECLVee
+S.OV
O.OV
ECLVEE
O.OV
-S.2V
Nominal Voltages
The CYIOl/lOE383 can be used in dual ±SV or single + SV supply
systems. The supply pins should be connected as shown in Tables 1
and2. This connection technique involves shifting up all ECL supply pins by SY. When operating in single-supply systems,the ECL
termination voltage level must also be shifted up by adding SY. For
example, if the termination is SO ohms to - 2V in a dual-supply system, the single + SV system should have SO ohms to + 3Y. If the termination is a thevenin type, then the resistor tied to ground is now
at +5V and the resistor tied to - SV is now at ground potential.
Consideration should be given to the power supply so that adequate bypassing is made to isolate the ECL output switching noise
from the supply. Having separate TIL and ECL + SV supply lines
will help to reduce the noise. Table 3 sho\vs the CYI0E383 nomina!
voltages applied in a 10K system.
9-6'
Table 3. CYIOE383 Nominal Voltages Applied in 10K System
Supply Pin
Single-Supply
System
Dual-Supply
System
TIL Vee
+S.OV
+S.OV
TILGND
O.OV
O.OV
ECLVee
+S.OV
O.OV
ECLVEE
O.OV
-S.2V
CYIOE383
CYIOIE383
~~
~=CYPRESS
~,
SEMICONDUCTOR
Ordering Information
Speed
(ns)
2.5
3
Ordering Code
2.5
3
Package 'JYpe
Operating
Range
84-Lead Plastic Leaded Chip Carrier Commercial
CYIOE383-2JC
J83
CYlOE383-2NC
N80
80-Lead Plastic Quad Flatpack
CYlOE383-3JC
J83
84-Lead Plastic Leaded Chip Carrier Commercial
CYIOE383-3NC
N80
80-Lead Plastic Quad Flatpack
CYIOE383-3YMB
Y84
84-Pin Ceramic Leaded Chip Carrier Military
Speed
(ns)
Package
Name
Ordering Code
Package
- Name
Package 1Ype
Operating
Range
84-Lead Plastic Leaded Chip Carrier Commercial
CYIOIE383-2JC
J83
CYlO1E383-2NC
N80
80-Lead Plastic Quad Flatpack
CYlO1E383-3JC
J83
84-Lead Plastic Leaded Chip Carrier Commercial
CYI01E383-3NC
N80
80-Lead Plastic Quad Flatpack
Document #: 38-A-00023-F
II
...I
oLIJ
9-7
CYIOE384L
ECL/TTL/ECL Translator
Features
• Low power (110 rnA max.)
• BiCMOS for optimum speed/power
• High speed (max.)
-3 ns tpD TTL-to-ECL
-4 ns tpD ECL-to-TTL
• Low skew < ± 1 ns
• Operates on single + SV supply
• 28-pin SOJ package
• Capable of greater than 2001V ESD
Functional Description
balanced low-noise operation over controlled-impedance buses between TTL
and/or ECL subsystems.
The CYlOE384L is a new-generation
TTL-to-ECL and ECL-to-TTL logic level
translator designed for high-performap.ce
systems. The device contains three independent TTL-to-ECL and five independent ECL-to-TTL translators for highspeed data transmission, mixed logic, and
bus applications. The CYlOE384L functions using differential ECL I/O to provide
The device has separate ECL and TTL
power/ground pins to reduce noise coupling between logic families. The translator is offered in ECL-compatible versions
with + S.OV power supply.· The TTL I/O is
fully TTL compatible. The CY10E384L is
packaged in 28-pin surface-mountable
SOJ.
Logic Block Diagram
DIFFERENTIAL
ECllNPUTS
EClSUPPlY
Pin Configuration
DO
DO
D1
01
D2
02
!)2
D3
03
D4
03
DO
C>
D1
C>
D2
TTL OUTPUTS
TTL SUPPLY
04
04
TTL INPUTS
TTL SUPPLY
SOJ
Top View
00
Of
C>
00
00
01
CiT
Q2
DIFFERENTIAL
EClOUTPUTS
EClSUPPlY
02
1111
EClDO
EClDO
EClD1
TTL Vee
EClD1
TTL 04
EClD2
TTL 03
ECl !)2
TTL 02
EClD3
TTL 01
ECl03
TTL 00
EClD4
EClO4
TTlD2
EClOO
TTlD1
ECloo
TTL DO
ECl01
ECl Vee (+5V)
ECl CiT
EClO2
EClGND
ECl02
TTlGND
E3B4-2
E384-1
Selection Guide
10E384L-3
Maximum Propagation Delay Time (ns) (TTL to ECL)
Maximum Propagation Delay Time (ns) (ECL to TTL)
3
4
110
Maximum Operating Current (rnA) Icc
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature ................. - 6SoC to +lS0°C
Ambient Temperature with
Power Applied ...................... -SSoC to +125°C
TIL Supply Voltage to Ground Potential .. - O.5V to + 7.0V
TIL DC Input Voltage ................. - 3.0V to + 7.0V
ECL Supply Voltage Vee to ECL GND ... - O.5V to + 7.0V
ECL Input Voltage . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to Vee
ECL Output Current .......................... - SO rnA
Static Discharge Voltage ....................... > 2001 V
(per MIL-STD-883, Method 301S)
Latch-Up Current ........................... > 200 rnA
Operating Range
Ambient
Version Thmperature
Commercial
lOE
O°C to
lOKH
+75°C
Range
9-8
I/O
10K
ECL
Vee
SV
±5%
TTL
Vee
SV
±S%
~
;~PRESS
~,.
CYIOE384L
SEMICONDUCTOR
ECL DC Electrical Characteristics ECL Vee = 5.0V [1,2]
lOE384L
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
VOL
Input HIGH Voltage
VIR
Input LOW Voltage
VIL
Vcml4J
IIR
IlL
10E, RL = 50g to +3V
VIN = VIR Min. or VIL Max.
10E
lOE
Common Mode Voltage
Input Voltage
Differential
Input HIGH Current
Input LOW Current
Vdiff
Test Conditions
lOE, RL = 50g to + 3V
VIN = VIR Min. or VIL Max.
Temperature[3]
Min.
+3950
TA = O°C
Max.
+4160
Unit
mV
TA = +25°C
+3990
+4190
mV
TA = +75°C
+4050
+4265
mV
TA = O°C
+3080
+3285
mV
TA = +25°C
+3100
+3300
mV
TA = +75°C
+3120
+3325
mV
TA = O°C
+3830
+4160
mV
TA = +25°C
+3870
+4190
mV
TA = +75°C
+3930
+4280
mV
TA = O°C
+3050
+3520
mV
TA = +25°C
+3050
+3525
mV
TA = +75°C
+3050
+3550
mV
1.0
V
mV
220
170
fAA
fAA
±Vem with respect to VBB( +3.7V)
Required for Full Output Swing
150
VIN = VIR Max.
VIN = VIL Min.
-0.5
TTL DC Electrical Characteristics Over the Operating Rangel 1]
lOE384L
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
Vee = Min., IOH = -3.2 rnA
VOL
Output LOW Voltage
Vee = Max., IOL = 16.0 rnA
Min.
Max.
Unit
0.5
V
2.4
V
VIR
Input HIGH Voltagel5]
VIL
Input LOW Voltagel5]
VeD
Input Clamp Diode Voltage
lIN = -lOrnA
-1.5
los
Output Short-Circuit Current
Vee = Max., VOUT = 0.5V[6]
-180
-40
Ilx
Input Load Current[7]
GND~VI~Vee
-250
+20
fAA
Icc
Vee Operating Supply Current
Vee = Max., lOUT = 0 rnA, f = f max.
110
rnA
2.0
V
V
0.8
V
rnA
Capacitance
Parameter
CIN
COUT
Description
Test Conditions
Input Capacitance
Output Capacitance
Notes:
1. See AC Test Load and Waveform for test conditions.
2. DC levels are specified with a nominal ECL Vee of 5Y. The levels will
track the variations in ECL V co
3. Commercial grade is specified as ambient temperature with transverse
air flow greater than 500 linear feet per minute.
4. The internal gain of the CYlOE384L guarantees that the output voltage will not change for common mode signals to ± 1Y. Therefore, input
CMRR is infinite within the common mode range.
5.
6.
7.
9-9
Max.
Unit
4
pF
5
pF
These are absolute values with respect to device ground.
Not more than one output should be tested at a time. Duration of the
short should not be more than one second.
I/O pin leakage is the worst case of IIX (where X = H or L).
II
...I
(J
W
&;J~PRESS
~,
CYIOE384L
SEMICONDUCTOR
ECL AC Test Load and Waveform[8, 9,10,11, 12)
+5V
ALL INPUT PULSES
VIH ------;-,,__-------"'\..I
Vee
INPUT
80%
20%
DoUT
20%
GND
GND
E384-4
E384-3
TTL AC Test Load and Waveform[13)
R12380
5V o-----'lN'-"I
3.0V
----:rr------s.,.
90%
OUTPUT 0 - - - " " " - " " , , ,
GND
CLPFI
INCLUDING
JIGAND _
SCOPE -
Equivalent to:
R2
1700
E384-6
E384-5
THEVENIN EQUIVALENT (Commercial)
990
OUTPUT ().O- - - J V
..\I\,
.. _---b_50o/c_O
_______________¥
~
1.5V
E384-7
TTL-to-ECL Timing
~tPLH=*
r- _ _
t.svL
F-tPHL~-
50%
--------------
50%
---------------E384-8
Skew Test (tSKT)
TTI'Qn-to-TTI'Qn+m
-t0~KT~ ______-1=-1.5VtSKT =:1
~
---------------------J 1.5V
E384-9
I
..J
(.)
UJ
Qn+m(ECL)
On+m(ECL)
50%
50%
E384-10
9-11
~PRRSS
_rs~CONDUcrOR
CYIOE384L
TTL-to-ECL Truth Table
ECL-to-TTL Truth Table
Inputs
Outputs
Inputs
ECLD n
TTLQn
TTLDn
ECLQn
ECLQn
Open
Open
L
L
L
H
L
H
L
H
H
L
H
L
H
Ordering Information
Speed
(ns)
3
Outputs
ECLD n
Ordering Code
CYlOE384L-3VC
Package
Name
V21
Package
lYPe
28-Lead Molded SOJ
Document #: 38-A-00035
9-12
Operating
Range
Commercial
CYIOE422
CYIOOE422
256 X 4 EeL Static RAM
Features
-lEE
Functional Description
= 220mA
• Low-power version
-tAA = 5ns
-lEE
The four independent active LOW block
select (8) inputs control memory selection
and allow for memory expansion and reconfiguration. Each block select (81
through '84), when active, turns off the corresponding output and memory block. The
read and write operations are controlled by
the state of the active LOW write enable
(W) input. With Wand '8x LOW, the corresponding data at Dx is written into the
addressed location. To read, W is held
HIGH, while '8 is held LOW. Open emitter
outputs allow for wired-OR connection to
expand or reconfigure the memory.
• On-chip voltage compensation for
improved noise margin
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
• 256 x 4-bit organization
• Ultra high speed/standard power
-tAA = 3.5ns
= l50mA
• Both lOKH/lOK- and lOOK-compatible I/O versions
• lOK/lOKH military version
• Capable of withstanding >200lV ESD
The Cypress CYlOE422 and CYI00E422
are 256 x 4 ECL RAMs designed for
scratch pad, control, and buffer storage
applications. Both parts are fully decoded
random access memories organized as
1024 words by 4 bits. The CYI0E422 is
10KH/lOK compatible and is available in a
military version .. The CYI00E422 is lOOK
compatible.
Logic Block Diagram
Pin Configurations (continued on next page)
CerDIP
Top View
CerDIP
Top View
VeeA
Ao
A1
a:
w
>
a:0
a:
I
W
A2
01
81
02
82
01
02
0
0
I
I
I
W
I
As
MEMORY CELL ARRAY
As
()
A7
W
A3
0
~
0
VEE
3:
a:
04
83
03
84
04
Vee
04
84
03
83
04
03
~
A3
A2
A1
Vee
VeeA
01
81
92
82
01
Ao
03
~
A3
A2
A1
Ao
VEE
A7
As
&
W
O2
E422-2
E422-3
II
..J
(.)
W
w
E422-1
Selection Guide
lOE422-4
lOOE422-3.5
3.5/4
220
lOE422-5
lOOE422-5
5
220
lOE422-7
lOOE422-7
7
L (Low Power)
150
150
Military (lOKllOKH only)
150
150
Maximum Access Time (ns)
lEE Max. (rnA)
Commercial
9-13
CYIOE422
CYIOOE422
"r~
Pin Configurations (continued)
LCC
Top View
~ ~
Quad Cerpack
Top View
PLCC
Top View
~~8u 8
> u ICO
'Z>OICO
32!!j242322
21
20
02
a2
10E422
100E422
03
82
83
W
~
16
A3
03
01
0
..... C\I
a:
c
~
w
c
0
u
w
c
C470-2
:=0
a:
Q
S
W
D
C470-1
SeIecf Ion GUl"de
10E470-5
100E470-5
5
Maximum Access Time (ns)
lEE Max.
200
(rnA)
9-20
10E470-7
100E470-7
7
200
CYIOE470
CYIOOE470
~
.
;~PRF.SS
--=-,
SEMICONDUcrOR
Maximum Ratings
Operating Range referenced to Vee
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ....................... -55°C to + 125°C
Supply Voltage VEE to Vee .............. -7.0V to +0.5V
Input Voltage ............................ VEE to +0.5V
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 rnA
Ambient
Temperature
Range
Commercial
Version
WE
O°C to + 75°C
VEE
-5.2V ± 5%
Commercial
WOE
O°C to + 85°C
-4.5V ± O.3V
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIR
VIL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
WE RL = 50Q to -2V
VEE = -5.2V
VIN = VIR Max. or VIL Min.
lOOK RL = 50Q to -2V
VEE = -4.5V
VIN = VIR Max. or VIL Min.
WE RL = 500 to -2V
VEE = -5.2V
VIN ::;= VIR Max. or VIL Min.
Temperature[l]
TA = O°C
Min.
-1000
Max.
-840
Unit
mV
TA = +25°C
-960
-810
mV
TA = +75°C
-900
-720
mV
TA = O°C to 85°C
-1025
-880
mV
mV
TA = O°C
-1870
-1665
TA = +25°C
-1850
-1650
mV
TA = +75°C
-1830
-1625
mV
TA = O°C to 85°C
-1810
-1620
mV
TA = DoC
-1145
-840
mV
TA = +25°C
-1105
-810
mV
TA = +75°C
-1045
-720
mV
WOK VEE = -4.5V
TA = O°C to 85°C
-1165
-880
mV
WE
VEE = -5.2V
TA = O°C
-1870
-1490
mV
TA = +25°C
-1850
-1475
mV
..J
(,)
TA = +75°C
-1830
-1450
mV
W
TA = O°C to 85°C
-1810
-1475
mV
220
170
!lA
!lA
!lA
lOOK RL = 50Q to -2V
VEE -4.5V
VIN = VIR Max. or VIL Min.
WE
VEE = -5.2V
WOK VEE = -4.5V
IIR
IlL
Input HIGH Current
Input LOW Current
VIN = VIR Max.
VIN = VIL Min.
lEE
Supply Current
(All inputs and outputs open)
Commercial
S inputs
All other inputs
0.5
-50
-200
rnA
Capacitance[2]
Parameter
CIN
CO UT
Description
Input Pin Capacitance
Output Pin Capacitance
Min.
1YP·
4
6
Notes:
1. Commercial grade is specified as ambient temperature with transverse
air flow greater than 500 linear feet per minute.
2.
9-21
Max.
Unit
pF
pF
Tested initially and after any design or process changes that may affect
these parameters.
I
CYIOE470
CYIOOE470
,4ViPRRSO
~
SEMICONDUCTOR
AC Test Loads and Waveforms[3, 4, 5, 6,.7, 8]
GND
ALL INPUT PULSES
::--tl
Vcc
INPUT
~%
I 1'. .
2~O.;..%_ _
t,
r
O.01I-lF~
C470-4
VEE
C470-3
Switching Characteristics Over the Operating Range
lOE470-5
lOOE470-5
Description
Parameter
Min.
Max.
lOE470-7
lOOE470-7
Min.
Max.
Unit
tAC
Input to Output Delay
3.0
3.5
ns
tRC
Chip Select Recovery
3.0
3.5
os
7.0
os
tAA
Address Access Time
tww
Write Pulse Width
5.0
5.0
7.0
os
tSD
Data Set-Up to Write
0
0
os
tHD
Data Hold to Write
0
0
os
tSA
Address Set-Up/Write
0
1.0
os
tHA
Address Hold/Write
0
1.0
os
tsc
Chip Select Set-Up/Write
0
0
os
tHC
Chip Select Hold/Write
0
0
tws
Write Disable
3.0
3.5
os
tWR
Write Recovery
5.0
8.0
os
tr
Output Rise Time
1.0
2.5
1.0
2.5
os
tf
Output Fall Time
1.0
2.5
1.0
2.5
os
Notes:
3. VIL = VIL Min., VIH = VIH Max. on lOE version.
4. VIL = -1.7V, VIH = -0.9Von lOOK version.
5. RL = 500, C < 30 pF (includes fIxture and stray capacitance).
6. All coaxial cables should be 500 with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
7.
8.
9-22
= =
os
tr
tf 0.7 ns.
All timing measurements are made from the 50% point of all waveforms.
-z£q
CYIOE470
CYIOOE470
.~
~AJCYPRESS
~, SEMICONDUCTOR
Switching Waveforms
Read Mode
Q
~~~~~~~_~_'-_-_-_-_~-_-_-_-_-_-_-_-_-_-_-_-t_AA-_=~~=~~::'~~-=-~=-:"'~=-=-~=~~-.I*-~====-=
ADDRESS
Q
C470-5
Write Mode
~~
;;ll'sO%
so%;
ADDRESS
"K
K
sO~
50~
sO%)~
D
II
~tHD
w
~r- SO%
tSD
I+--
SO%) It'"
I-tHA
tww
tSA
-
(,)
tHC
LLI
/1{
Q
tsc
..J
~
~tws
tWR
C470-6
Truth Table
Inputs
Output
S
W
D
Q
Mode
H
X
X
L
Disabled
L
L
H
L
Write "H"
L
L
L
L
Write "I.:'
L
H
X
DOUT
Read
H = High Voltage Level
L = Low Voltage Level
X = Don't Care
9-23
CYIOE470
CYIOOE470
~>.
~~PRESS
~, SEMICONDUCTOR
Ordering Information
Package
Name
I/O
(rnA)
tAA
(ns)
Ordering Code
10K
200
S.O
CYI0E470-SDC
D4
I8-Lead (300-Mil) CerDIP
7.0
CYI0E470-7DC
D4
I8-Lead (300-Mil) CerDIP
S.O
·CY100E470-SDC
D4
I8-Lead (300-Mil) CerDIP
7.0
CY100E470-7DC
D4
I8~Lead
lEE
lOOK
200
Document #: 38-A-00003-B
9-24
Package 'fYpe
(300-Mil) CerDIP
Operating
Range
Commercial
Commercial
CYIOE474
CYIOOE474
lKx4ECL
Static RAM
Features
• 1024 x 4-bit organization
• Ultra high speed/standard power
-tAA = 3.Sns
-lEE = 275 rnA
• Low-power version
-tAA = Sns
-lEE = 190 rnA
• Both 10KH/10K- and lOOK-compatible I/O versions
• 10K/10KH military version
• Capable of withstanding >2001V ESD
• On-chip voltage compensation for improved noise margin
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
Functional Description
The Cypress CY10E474 and CYlOOE474
are 1Kx 4 ECL RAMs designed for scratch
pad, control, and buffer storage applications. These RAMs are developed by Aspen Semiconductor Corporation, asubsidiary of Cypress Semiconductor. Both
parts are fully decoded random access
Logic Block Diagram
Ag
A1
WandSLOW,thedataatD(1_4)iswr~en
into the addressed location. To read, W is
held HIGH while S is held LOW. Open
emitter outputs allow for wired-OR connection to expand the memory.
A7
A6
CerDiP
Top View
CerDiP
Top View
Vee
O2
~
O2
03
S
01
04
W
04
01
Ag
O2
As
03
A4
A2
The active LOW chip select (S) input controls memory selection and allows for
memory expansion. The read and write operations are controlled by the state of the
active LOW write enable (W) input. With
Pin Configurations (continued next page)
As
A5
A3
memories organized as 1024 words by 4
bits. The CY10E474 is lOKH/lOK compatible and is available in a military version.
The CY100E474 is lOOK comptaible.
I
I
I
I
I
I
I
Vee
A7
01
VeeA
03
VEE
S
I
MEMORY CELL ARRAY
I
I
I
O2
I
I
I
A6
W
~
NC
Ag
Ao
A5
As
A1
A4
A7
A2
A3
E474-2
E474-3
Ao
0(1-4)
S
Vii
0(1-4)
Selection Guide
10E474-4
100E474-3.S
3.5/4
275
Maximum Access Time (ns)
lEE Max. (rnA)
Commercial
10E474-S
100E474-S
5
275
10E474-7
10OE474-7
7
L
190
190
Military (lOK/lOKH only)
190
190
9-25
II
..J
(.)
U.I
CYIOE474
CYIOOE474
~
.
;~pRF.SS
_ " SEMJCONDUcrOR
Pin Configurations (continued)
PLCC
Quad Cerpack
Top View
Top View
«
LCC
Top View
do-»~-»oc5
«
()
Ao
04
W
A1
03
S
A2
10E474
100E474
NC
A3
Ao
4
A1
S
6
D2
01
A2
NC
O2
01
03
A3
A4
A4
S
As
W
o
()
ao~~acf
As
04
10E474
100E474
20
D4
03
19
18
02
01
S
17
Vi
16
9
10 11 12 1314 1S
o
CDW "
co m
Z«~<<«
w 0
" co m
z«~z«««
CD
E474-4
E474-S
Maximum Ratings
E474-6
Operating Range Referenced to VCC
(Above which the useful life maybe impaired. Exposure to absolute
maximum rated conditions for extended periods may affect device
reliability. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to +150°C
Ambient Temperature with
Power Applied ...................... - 55 ° C to + 125 ° C
Supply Voltage VEE to VCC ............. - 7.0V to +0.5V
Input Voltage ........................... VEE to + 0.5V
Output Current ............................... -50 rnA
Range
Commercial
(Standard,L)
I/O
Ambient
Temperature
VEE
lOKH/lOK
O°C to 75°C
-5.2V ± 5%
Commercial
(Standard,L)
lOOK
O°C to + 85°C
-4.5V ± O.3V
Military (L)
lOKH/lOK
-55°C to
+125°C Case
-5.2V ± 5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
10ELlJ RL = 50g to -2V
VEE = -5.2V, Vcc= VCCA =GND
VIN = VIR Max. or VIL Min.
lOOK RL = 50g to -2V,
VEE = -4.5Y, Vcc = VCCA = GND
VIN = VIR Max. or VIL Min.
10E RL = 50g to -2V
VEE = -5.2V, Vcc= VCCA = GND
VIN = VIR Max. or VIL Min.
lOOK RL = 50g to -2V,
VEE = -4.5V, V cc = VCCA = GND
VIN = VIR Max. or VIL Min.
9-26
Temperature[l]
Tc = -55°C
Min.
-1140
Max.
-900
Unit
mV
TA = O°C
TA = +25°C
-1000
-840
mV
-960
-810
mV
TA = +75°C
-900
-735
mV
Tc = +125°C
-880
-700
mV
TA = O°C to 85°C
-1025
-880
mV
Tc = -55°C
-1920 -1670
mV
TA = +O°C
-1870 -1665
mV
TA = +25°C
-1850 -1650
mV
TA = +75°C
-1830 -1625
mV
Tc = +125°C
-1830 ....,1610
mV
TA = O°C to 85°C
-1810 -1620
mV
;;;::
CYIOE474
CYIOOE474
:~PRESS
====?
SEMICONDUCTOR
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Input HIGH Voltage
VIR
IIH
IlL
Input HIGH Current
Input LOW Current
lEE
Supply Current (All
inputs and outputs open)
lOE
VEE
Vee
= -55°C
TA = O°C
TA = +25°C
TA = +75°C
Te = +125°C
TA = O°C to 85°C
Te = -55°C
TA = O°C
TA = +25°C
TA = +75°C
Te = +125°C
Te = O°C to 85°C
Te
= -5.2V
= VeeA = GND
lOOK VEE
Input LOW Voltage
VIL
Temperature[1]
Test Conditions
lOE
VEE
Vee
= -4.5V
= -5.2V
= VeeA = GND
lOOK VEE = -4.5V
Vee = VeeA = GND
VIN = VIH Max.
VIN = VIL Min.
S inputs
All other inputs
Commercial/Military Standard L (Low Power)
Commercial Standard
Min.
-1260
Max.
-900
Unit
mV
-1170
-840
mV
-1130
-810
mV
-1070
-720
mV
-1030
-700
mV
-1165
-880
mV
-1950 -1540
mV
-1950 -1480
mV
-1950 -1475
mV
-1950 -1450
mV
-1950 -1450
mV
-1810 -1475
mV
0.5
-50
-190
-275
220
170
fAA
I-tA
rnA
rnA
Capacitance[3]
Parameter
Description
Input Pin Capacitance
Output Pin Capacitance
CIN
COUT
'tYP·
Max.l 4]
4
5
5
6
Unit
pF
pF
AC Test Loads and Waveforms[5, 6, 7, 8, 9, 10]
..J
(,)
LLI
GND
ALL INPUT PULSES
V1H ------;-.,.--------""1
Vee
80%
INPUT
20%
0.01 f!F~
•
20%
-2.0V
VEE
E474-7
E474-8
Notes:
1. Commercial grade is specified as ambient temperature with transverse
airflow greater than 500 linear feet per minute. Military grade is specified as case temperature.
2. WE specifications support both 10K and lOKH compatibility.
3. Tested initially and after any design or process changes that may affect
these parameters.
4. For all packages except cerDIP (D40), which has maximums of
CIN = S pF, COUT = 9 pF.
5. VIL = VIL Min., VIH = VIH Max. on WE version.
VIL = -1.7V, VIH = -0.9V on WOK version.
RL = 50g, C < 5 pF (3.5/4-ns grade) or < 30 pF (5-, 7-ns grade). Includes fixture and stray capacitance.
S. All coaxial cables should be 50Q with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
9. tr = tf = 0.7 ns.
10. All timing measurements are made from the 50% point of all waveforms.
6.
7.
9-27
CYIOE474
CYIOOE474
~CYPRFSS
~.a
~_, SEMICONDUCTOR
Switching Characteristics Over the Commercial Operating Range
lOOE474-3.5
Parameter
Description
Min.
lOE474-4
Max.
Min.
lOE474-7
lOOE474-7
lOE474-5
lOOE474-5
Max.
Min.
Max.
Min.
Max.
Unit
tAC
Input to Output Delay
2.5
2.5
0.5
3.0
0.5
5.0
ns
tRC
Chip Select Recovery
2.5
2.5
0.5
3.0
0.5
5.0
ns
1.2
5.0
1.2
7.0
ns
tAA
Address Access Time
tw'w
Write Pulse Width
tSD
3.5
4.0
5.0
5.0
5.0
5.0
ns
Data Set-Up to Write
0
0
0
0
ns
tHD
Data Hold to Write
0
0
0
1.0
ns
tSA
Address Set-Up/Write
0
0
0
1.0
ns
tHA
Address Hold/Write
0
0
0
1.0
ns
tsc
Chip Select Set-Up/Write
0
0
0
0
ns
tHC
Chip Select Hold/Write
tws
Write Disable
tWR
0
0
0.3
2.5
Write Recovery
0.5
tr
Output Rise Time
0.35
tf
Output Fall Time
0.35
1.0
0
ns
0.3
3.0
0.3
6.5
3.5
0.5
5.0
0.5
7.0
ns
1.5
0.35
2.5
1.0
2.5
ns
1.5
0.35
2.5
1.0
2.5
ns
0.3
2.5
3.5
0.5
1.5
0.35
1.5
0.35
ns
Switching Characteristics Over the Military Operating Range
lOE474-5
lOE474-7
Min.
Max.
Min.
Max.
Unit
tAC
Input to Output Delay
0.5
4.0
0.5
5.0
ns
tRC
Chip Select Recovery
0.5
4.0
0.5
5.0
ns
tAA
Address Access Time
1.2
5.0
1.2
7.0
ns
tww
Write Pulse Width
5.0
5.0
tSD
Data Set-Up to Write
0
0
ns
tHD
Data Hold to Write
1.0
1.0
ns
tSA
Address Set-Up/Write
1.0
1.0
ns
tHA
Address Hold/Write
1.0
1.0
ns
Parameter
Description
ns
tsc
Chip Select Set-Up/Write
0
0
ns
tHC
Chip Select Hold/Write
1.0
1.0
ns
tws
Write Disable
0.3
4.0
0.3
6.5
ns
tWR
Write Recovery
0.5
5.0
0.5
7.0
ns
tr
Output Rise Time
1.0
2.5
1.0
2.5
ns
tf
Output Fall Time
1.0
2.5
1.0
2.5
ns
9-28
2;.
CYIOE474
CYIOOE474
;~
;""~~UcrOR
Switching Waveforms
Read Mode
Q
----~======~~--------------
ADDRESS
tAA-------------------~~.!~-------
Q
E474 9
Write Mode
~ "ADDRESS
D
Vii
:;'t£50%
50%)
K
50%)
50%)
I(
tso
I+--- tSA
Q
tsc
K
50%
-- -
~r50%
.
50%)1 ~
I+--
tvvw
"l
tHA
------I
tws
....
tHC
....
I+-
•
tHO
tWA
~
(.)
}~
.....
W
E474-10
9-29
CYIOE474
CYIOOE474
1Pr~ClOR
1Ypical DC and AC Characteristics (lOE474/10E474L/IOOE474/100E474L)
NORMALIZED SUPPLY CURRENT
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.2
w
1.1
1.1
J!l
Cl
w
N
::J
«
::E
1.0
0.9
a:
0
z 0.8
-
-'
~
V
w 1.0 1:;;;;;;;;;;;;;;;;;;;;;--+---.-!!!!!!~=9
-'V
J!l
Cl
~
0 . 9 1 - - - - - - - + - - - - -....
::J
«
~ 0.81------+------1
oz
0.71------+------1
0.7
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE
-55
6.0
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2....-----r--........- - . - - - - - ,
1.3
~ 1.2
1.1
::E
1.0
/
a:
~ 0.9
~
0.8
w
N
::J
1.0
::E
a: 0.9
0
z
0.8
25
4.0
125
4.5
5.0
5.5
SUPPLY VOLTAGE
AMBIENT TEMPERATURE (0C)
'Iruth Table
Inputs
1.1
«
------
-55
~
Cl
/
N
::J
«
125
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
_@
25
AMBIENT TEMPERATURE (0C)
M
Output
S
W
D
Q
Mode
R
X
X
L
Disabled
L
L
R
L
WriteR
L
L
L
L
Write L
L
R
X
DOUT
Read
9-30
M
6.0
CYIOE474
CYIOOE474
sa: .~
~~CYPRESS
....... . , SEMlCONDUcrOR
Ordering Information
I/O
(mA)
tAA
(ns)
lOOK
275
3.5
lEE
5
190
5
7
lOElllJ
275
4
5
190
5
7
Ordering Code
Package
Name
Package 1Ype
CYlOOE474-3.5KC
K63
24-Lead Square Cerpack
CYlOOE474-3.5LC
L63
24-Square Leadless Chip Carrier
CYlOOE474-5DC
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOOE474-5KC
K63
24-Lead Square Cerpack
CYlOOE474-5LC
L63
24-Square Leadless Chip Carrier
CYlOOE474L-5DC
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOOE474L-5JC
J64
28-Lead Plastic Leaded Chip Carrier
CYlOOE474L-5KC
K63
24-Lead Square Cerpack
CYlOOE474L-5LC
L63
24-Square Leadless Chip Carrier
CY100E474L-7DC
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOOE474L-7JC
J64
28-LeadPlasticLeaded Chip Carrier
CY100E474L-7KC
K63
24-Lead Square Cerpack
CYlOOE474L-7LC
L63
24-Square Leadless Chip Carrier
CYlOE474-4KC
K63
24-Lead Square Cerpack
CYlOE474-4LC
L63
24-Square Leadless Chip Carrier
CYlOE474-5DC
D40
24-Lead (400-Mil) Sidebraze DIP
CY10E474-5KC
K63
24-Lead Square Cerpack
CYlOE474-5LC
L63
24-Square Leadless Chip Carrier
CY10E474L-5DC
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOE474L-5JC
J64
28-LeadPlasticLeaded Chip Carrier
CYlOE474L-5KC
K63
24-Lead Square Cerpack
CYlOE474L-5LC
L63
24-Square Leadless Chip Carrier
CYlOE474L-5DMB
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOE474L-5KMB
K63
24-Lead Square Cerpack
CYlOE474L-7DC
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOE474L-7JC
J64
28-Lead Plastic Leaded Chip Carrier
CYlOE474L-7KC
K63
24-Lead Square Cerpack
CYlOE474L-7LC
L63
24-Square Leadless Chip Carrier
CY10E474L-7DMB
D40
24-Lead (400-Mil) Sidebraze DIP
CYlOE474L-7KMB
K63
24-Lead Square Cerpack
Notes:
11. lOE specifications support both 10K and lOKH compatibility.
Document #: 38-A-00004-D
9-31
Operating
Range
Commercial
Commercial
Commercial
Commercial
Military
Commercial
Military
•
..J
oLLI
CYIOIE484
CYIOE484
CYIOOE484
CYPRESS
SEMICONDUCTOR
Features
• 4096 x 4-bit organization
• Ultra high speed/standard power
-tAA = 4,5ns
-lEE = 320mA
• Low-power version
-tAA = 7,10 ns
-lEE = 200mA
• Both 10KH/10K- and lOOK-compatible I/O versions
• On-chip voltage compensation for improved noise margin
• Capable of withstanding >2001V ESD
4K x 4 EeL Static RAM
• Open emitter output for ease of
memory expansion
• Industry-standard pinout
Functional Description
The Cypress CY101E484, CYlOE484, and
CY100E484 are 4K x 4 ECL RAMs designed for scratch pad, control, and buffer
storage applications. These parts are fully decoded random access memories organized as 4K words by 4 bits. The
CY10E484 is lOKH-/lOK-compatible. The
CYlOOE484 is lOOK-compatible, and the
CY101E484 is lOOK-compatible with a
-5.2V supply.
The active LOW chip select (8) input controls memory selection and allows for
memory expansion. The read and write operations are controlled by the state of the
active LOW write enable (W) input. With
Wand SLOW, the data at D(1-4) is wr~en
into the addressed location. To read, W is
held HIGH while 8 is held Law. Open
emitter outputs allow for wired-OR connection to expand the memory. The 4-ns
and 5-ns devices are packaged in 28-pin
cerDIPs, CLCCs, and rectangular cerpacks in the high-performance center
power-ground version pin configurations.
The 7-ns and lO-ns~ts are offered with
two write enables (WEb WEz).
Pin Configurations (4-/5-ns Center Power/Ground Only)
Logic Block Diagram
Rectangular Cerpack
Top View
CerDIP
Top View
S
01
O2
A7
As
VII
03
04
NC
01
An
02
A10
NC
As
Vee
VeeA
Ao
NC
W
~
04
As
Cl
Ao
A7
W
A1
As
A2
As
A1
a:
A2
i?
A3
~
A5
As
VEE
03
a:
Cl
0
(,)
~
A3
W
CLCC
Top View
04030201
Cl
484-2
S VII NC
484-3
~a:
0(1-4)
S
WCW1)
CW2)
0(1-4)
01
02
Vee
VeeA
03
04
Ao
484-1
484-4
Selection Guide
Maximum Access Time (ns)
lEE Max. (rnA)
IStandard
101E484-4
10E484-4
100E484-4
lOIE484-5
lOE484-5
lOOE484-5
lOlE484-7
lOE484-7
10OE484-7
101E484-10
10E484-10
100E484-10
4
5
320
7
10
200
200
200
200
320
! Low Power (L)
.. (1OK/10KH only)
IMIlItary
320
9-32
CYIOIE484
CYIOE484
CYIOOE484
d: :~
==-
ill CYPRESS
~_,~
SEM]CONDUcrOR
Pin Configurations (7 ns, 10 ns)
CerDIP
Top View
Rectangular Cerpack
Top View
SOJ
Top View
VeeA
D03
Vee
D02
D1
D2
S
D04
D01
D14
D13
D3
D4
01
WE2
NC
A3
D12
D11
~
cs
As
As
WE1
02
Vee
VeeA
03
Ao
A1
A2
WE1
A11
A10
As
VEE
NC
PLCC
Top View
VeeA
D03
vee
D02
D04
D01
D14
D13
D12
D11
Ao
A1
A2
A3
~
cs
WE1
WE2
NC
04
As
As
As
Ao
A7
A7
A11
A10
A1
A2
As
As
A11
NC
As
NC
VEE
As
A3
~
VEE
A10
As
A7
As
D4 D3 D2 D1
S WE1 WE2
01
NC
02
Vee
A11
101E484
10E484
100E484
A10
As
VEE
WE2
NC
04
NC
Ao
As
A1 A2 A3 ~ As
As
A7
484-7
484-5
484-6
484-8
Maximum Ratings
Operating Range Referenced to Vee
(Above which the useful life may be impaired. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. For user guidelines, not tested.)
Storage Temperature ................. - 65°C to + 150°C
Ambient Temperature with
Power Applied ...................... - 55°C to + 125°C
Supply Voltage VEE to Vee ............. - 7.0V to +O.5V
Input Voltage ............................ VEE to +O.5V
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 50 rnA
Range
I/O
Commercial 10KH/
(Standard, L) 10K
Commercial lOOK
(Standard,L)
Commercial
(Standard,L)
Military
(Standard,L)
101
1OKH/
10K
Ambient
Temperature
VEE
O°C to 75°C
- 5.2V ±5%
O°C to +85°C
- 4.5V ±O.3V
O°C to 75°C
- 5.2V ±5%
- 55°C to + 125°C
Case
- 5.2V ±5%
Electrical Characteristics Over the Operating Range
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
lOELL] RL = 50Q to - 2V
VEE = - 5.2V
Vee = VeeA = GND
VIN = VIR Max. or VIL Min.
100/101K RL = 50Q to - 2V
VEE = - 4.5V (5.2V for 101K)
Vee = VeeA = GND
VIN = VIR Max. or VIL Min.
VOL
Output LOW Voltage
lOE RL = 50Q to - 2V
VEE = - 5.2V
Vee = VeeA = GND
VIN = VIR Max. or VIL Min.
100/101K RL = 50Q to - 2V
VEE = - 4.5V (5.2V for 101K)
Vee = VeeA = GND
VIN = VIR Max. or VIL Min.
9-33
Temperatnre[l]
Min.
Max.
Unit
= - 55°C
TA = O°C
TA = +25°C
TA = +75°C
Te = +125°C
TA = O°C to 85°C
- 1140
- 900
mV
-1000
- 840
mV
- 960
- 810
mV
- 900
- 735
mV
- 880
-700
mV
- 1025
- 880
mV
mV
Te
(75°C for 101K)
= - 55°C
= +O°C
TA = +25°C
TA = +75°C
Te = +125°C
TA = O°C to 85°C
Te
-1920
-1670
TA
-1870
-1665
mV
-1850
-1650
mV
-1830
-1625
mV
-1830
-1610
mV
-1810
-1620
mV
(75°C for 101K)
•
..J
ow
-.-
CYIOIE484
CYIOE484
CYIOOE484
-~
_'Ji1!ICYPRESS
_ , SEMICONDUCTOR
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Input HIGH Voltage
VIH
Input LOW Voltage
Min.
Max.
Unit
= -55°C
TA = O°C
TA = +25°C
TA = +75°C
Te = +125°C
TA = O°C to 85°C
-1260
-900
mV
-1170
-840
mV
-1130
-810
mV
-1070
-720
mV
-1030
-700
mV
-1165
-880
mV
Te
= - 5.2V
= VeeA = GND
lOOK VEE = - 4.5V (- 5.2V for
101K), Vee = VeeA = GND
VIL
Temperature[l)
Test Conditions
lOE
VEE
Vee
10E
VEE
Vee
= - 5.2V
= VeeA = GND
100/101K VEE = - 4.5V (- 5.2V
for 101K), Vee = VeeA = GND
IIH
Input HIGH Current
VIN
IlL
Input LOW Current
VIN
= Vm Max.
= VIL Min.
(75°C for 101K)
= -55°C
= O°C
TA = +25°C
TA = +75°C
Te = +125°C
TA = O°C to 85°C
Te
-1950
-1540
mV
TA
-1950
-1480
mV
-1950
-1475
mV
-1950
-1450
mV
-1950
-1450
mV
-1810
-1475
mV
220
0.5
170
!lA
!lA
(75°C for 101K)
S inputs
-50
All other inputs
Supply Current (All inputs and outputs open)
lEE
Commercial/Military L (Low Power)
-200
rnA
Commercial and Military Standard Power
-320
rnA
Capacitance[3)
Parameter
Description
'JYp.
MaxJ4)
Unit
CIN
Input Pin Capacitance
4
6
pF
COUT
Output Pin Capacitance
5
7
pF
AC Test Loads and Waveforms[5, 6, 7, 8, 9, 10)
GND
ALL INPUT PULSES
V1H ------;-._-------,,1
80%
INPUT
20%
20%
-2.0V
484-10
484-9
Notes:
1. Commercial grade is specified as ambient temperature with transverse air flow greater than 500 linear feet per minute. Military grade is
specified as case temperature.
2. lOE specifications support both 10K and lOKH compatibility.
3. Tested initially and after any design or process changes that may affect
these parameters.
4. For all packages except cerDIP (D42), which has maximums of
CIN = 8 pF, COUT = 9 pH
5. VIL = VIL Min., VIH = VIH Max. on IOE version.
6. VIL = -1.7V, VIH = -0.9V on lOOK version.
RL = 500, C < 5 pF (4-, 5-ns grade) or < 30 pF (7-, lO-ns grade). Includes fixture and stray capacitance.
8. All coaxial cables should be 50Q with equal lengths. The delay of the
coaxial cables should be "nulled" out of the measurement.
9. tr = tf = 0.7 ns.
10. All timing measurements are made from the 50% point of all waveforms.
7.
9-34
.
CYIOIE484
CYIOE484
CYIOOE484
~~
--=-,
_ . ; ; ; : CYPRF.SS
SEMICONDUCTOR
Switching Characteristics Over the Commercial Operating Range
lOlE484-4
lOE484-4
lOOE484-4
Parameter
Description
Min.
lOlE484-5
lOE484-5
lOOE484-5
Max.
Min.
Max.
lOlE484-7
lOE484-7
lOOE484-7
lOlE484-10
lOE484-10
lOOE484-10
Min.
Max.
Min.
Max.
Unit
ns
tAC
Input to Output Delay
3
3
0.5
4
0.5
5
tRC
Chip Select Recovery
3
3
0.5
4
0.5
5
ns
tAA
Address Access Time
4
5
1.2
7
1.2
10
ns
1.5
ns
tww
Write Pulse Width
tNWW
Non-Write Pulse
tSD
Data Set-Up to Write
5
5
5
1.5
0
ns
6
1.5
1.5
0
1
2
ns
ns
tHD
Data Hold to Write
0
0
1
2
tSA
Address Set-UplWrite
0
0
1
2
ns
tHA
Address HoldlWrite
0
0
1
2
ns
ns
tsc
Chip Select Set-UplWrite
0
0
1
2
tHC
Chip Select HoldlWrite
0
0
1
2
tws
Write Disable
tWR
Write Recovery
0.5
4
tr
Output Rise Time
0.35
1.5
tf
Output Fall Time
0.35
1.5
0.35
0.3
3
0.3
3
0.3
0.5
5
0.35
1.5
1.5
ns
5
ns
5
0.3
0.5
8
0.5
12
ns
1
2.5
1
2.5
ns
1
2.5
1
2.5
ns
Switching Characteristics Over the Military Operating Range
lOE484-5
Parameter
Description
Min.
lOE484-7
lOE484-10
Max.
Min.
Max.
Min.
Max.
Unit
tAC
Input to Output Delay
3
0.5
4
0.5
5
ns
tRC
Chip Select Recovery
3
0.5
4
0.5
5
ns
tAA
Address Access Time
5
1.2
7
1.2
10
ns
tww
Write Pulse Width
tNWW
Non-Write Pulse
tSD
Data Set-Up to Write
1
1
2
ns
tHD
Data Hold to Write
1
1
2
ns
tSA
Address Set-UplWrite
1
1
2
ns
tHA
Address HoldlWrite
1
1
2
ns
ns
5
5
1.5
1.5
tsc
Chip Select Set-UplWrite
1
1
2
tHC
Chip Select HoldlWrite
1
1
2
tws
Write Disable
0.3
3
0.3
ns
6
1.5
5
0.3
ns
ns
5
ns
tWR
Write Recovery
0.5
5
0.5
8
0.5
12
ns
tr
Output Rise Time
0.35
1.5
1
2.5
1
2.5
ns
tf
Output Fall Time
0.35
1.5
1
2.5
1
2.5
ns
9-35
•
...I
o
LLI
CYIOIE484
CYIOE484
CYIOOE484
~
_~PRFSS
~" ~b.nCONDUcrOR
Switching Waveforms
Read Mode
;t--t:c
t-tAC
80%
20%
Q
--------------------
tr
=====_~_. . ___
. -_-_-__=__=__=__=__=_-t_AA-=-_-=-=-~==_-==_-==_~-*-~~~=
ADDRESS
Q
484-11
Write Mode
~,
ADDRESS
/~50%
50% ) (
50%)(
D
50%*
50%)(
I
50%/ ~
~~50%
tSD
14--
tWW[ll]
- t SA
Q
tHD
t HA - - " "
tHC
71{
tsc
tWR
- - tws
484-12
Truth Table
Inputs
Output
S
W
D
Q
Mode
H
X
X
L
Disabled
L
L
H
L
Write H
L
L
L
L
Write L
L
H[12]
X
DOUT
Read
Notes:
11. Iftww.5. tNWW the device will not write data to the addressed location.
12. The7-nsand lO-ns parts have two WE pins. Both WEl and WE2ffiust
be LOW to initiate write operation.
9-36
CYIOIE484
CYIOE484
CYIOOE484
-=====-..
~
~~CYPRESS
~_'SEMICONDUCTOR
Ordering Information
I/O
1OIE[13]
lEE
tAA
(rnA)
(ns)
320
4
5
200
7
10
Ordering Code
Package
Name
Package 1Ype/
Pinout
CYlOIE484-4DC
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYlOIE484-4KC
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYlOIE484-4YC
Y64
28-Pin Ceramic Leaded Chip Carrier
Center Power/Ground
CYlOIE484-5DC
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYI0IE484-5KC
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYlOIE484-5YC
Y64
28-Pin Ceramic Leaded Chip Carrier
Center Power/Ground
CYlOIE484L-7DC
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYlOIE484L-7JC
J64
28-Lead Plastic Leaded Chip Carrier
Corner Power/Ground
CYlOIE484L-7KC
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOIE484L-7VC
V21
28-Lead Molded SOJ
Center Power/Ground
CYI0IE484L-lODC
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYlOIE484L-lOJC
J64
28-Lead Plastic Leaded Chip Carrier
Corner Power/Ground
CYlOIE484L-lOKC
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOIE484L-lOVC
V21
28-Lead Molded SOJ
Center Power/Ground
Note:
13. 100E specifications are WOK-compatible with -S.2V supplies.
9-37
Operating
Range
Commercial
Commercial
•
..J
oLLI
CYIOIE484
CYIOE484
CYIOOE484
J.::~
•
'11 CYPRESS
,
'SEMICONDUCTOR
Ordering Information (continued)
I/O
(rnA)
lEE
tAA
(ns)
lOOE
320
4
5
200
7
10
Ordering Code
Package
Name
Package 1YPe/
Pinout
CYI00E484-4DC
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYI00E484-4KC
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYI00E484-4YC
Y64
28-Pin Ceramic Leaded Chip Carrier
Center Power/Ground
CYlOOE484-5DC
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYI00E484-5KC
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYI00E484-5YC
Y64
28-Pin Ceramic Leaded Chip Carrier
Center Power/Ground
CYIOOE484L-7DC
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYlOOE484L-7JC
J64
28-Lead Plastic Leaded Chip Carrier
Corner Power/Ground
CYI00E484L-7KC
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOOE484L-7VC
V21
28-Lead Molded SOJ
Center Power/Ground
CYlOOE484L-I0DC
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYI00E484L-lOJC
J64
28-Lead Plastic Leaded Chip Carrier
Corner Power/Ground
CYIOOE484L-lOKC
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOOE484L-lOVC
V21
28-Lead Molded SOJ
Center Power/Ground
9-38
Operating
Range
Commercial
Commercial
CYIOIE484
CYIOE484
CYIOOE484
~
~~
~.CYPRESS
_ , SEMICONDUCTOR
Ordering Information (continued)
I/O
lOE[14]
(rnA)
tAA
(ns)
320
4
lEE
5
200
7
10
Ordering Code
Package
Name
Package 'tYPe/
Pinout
CYlOE484-4DC
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYlOE484-4KC
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYlOE484-4YC
Y64
28-Pin Ceramic Leaded Chip Carrier
Center Power/Ground
CYlOE484-5DC
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYlOE484-5KC
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYlOE484-5YC
Y64
28-Pin Ceramic Leaded Chip Carrier
Center Power/Ground
CYlOE484-5DMB
D42
28-Lead (400-Mil) CerDIP
Center Power/Ground
CYlOE484-5KMB
K80
28-Lead Rectangular Cerpack
Center Power/Ground
CYlOE484L-7DC
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYlOE484L-7JC
J64
28-Lead Plastic Leaded Chip Carrier
Corner Power/Ground
CYlOE484L-7KC
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOE484L-7VC
V21
28-Lead Molded SOJ
Center Power/Ground
CYlOE484L-7DMB
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CY10E484L-7KMB
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOE484L-10DC
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYlOE484L-lOJC
J64
28-Lead Plastic Leaded Chip Carrier
Corner Power/Ground
CYlOE484L-10KC
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
CYlOE484L-10VC
V21
28-Lead Molded SOJ
Center Power/Ground
CYlOE484L-lODMB
D42
28-Lead (400-Mil) CerDIP
Corner Power/Ground
CYlOE484L-lOKMB
K80
28-Lead Rectangular Cerpack
Corner Power/Ground
Note:
14. lOE specifications support both 10K and lOKH compatibility.
Document #: 38-A-00005-F
9-39
Operating
Range
Commercial
Military
Commercial
Military
II
..J
Commercial
Military
ow
INFO
II
SRAMs
ECl
I
I
I
I
I
I
I
I
BUS
"11
MiliTARY
'Ii
TOOLS
'M
QUALITY
'N
PACKAGES
'ii
PROMs
PlDs
FIFOs
lOGIC
DATACOM
MODULES
=.
~~
'1=
-?
Section Contents
CYPRESS
SEMICONDUCTOR
Page Number
Bus Interface Products
Device Number
Description
VIC64
VIC068A
VAC068A
CY7C964
VMEbus Interface Controller with D64 Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1
VMEbus Interface Controller ........................... " ..................... 10-6
VMEbus Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-14
Bus Interface Logic Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-20
VIC64
CYPRESS
SEMICONDUCTOR
VMEbus Interface Controller
with D64 Functionality
Features
• An enhanced VIC068A
- 64-bit MBLT operation
- Higher transfer rate
• Complete VMEbus interface controller and arbiter
- 58 internal registers for configuration control and VMEbus and local operations status
- Drives arbitration, interrupt, address modifier, utility,
strobe, address line A[7:1], and data line D[7:0] directly.
and provides control signals to drive remaining address
and data lines
- Direct connection to 68K family and mappable to non-68K
processors
• Complete master/slave capability
- Supports read, write, write posting, and block transfers
- Accommodates VMEbus timing requirements with internal digital delay line with half-clock granularity
- Programmable metastability delay
- Programmable data acquisition delays
- Provides programmable timeout timers for local bus and
VMEbus transactions
• Interleaved block transfers
- D64 block transfer capability in conformance with VME64
proposal
- Can act as DMA master on local bus
- Programmable burst counter, transfer length, and interleave period
- Allows master and slave transfer to occur during interleave period
- Also supports local module-based DMA
• Arbitration support
- Supports single-level, priority, and round-robin arbitration
- Support fair request option as requester
• Interrupt support
- Complete support for the VMEbus interrupts; interrupters and interrupt handler
- Seven local interrupt lines
- 8-level interrupt priority encoded
- Total of 29 interrupts mapped through the VIC64
• Miscellaneous features
- Refresh option for local DRAM
- Four broadcast location monitors
- Four module-specific location monitors
- Eight interprocessor communication registers
• See the VIC64/7C964 Design Notes for more information
Functional Description
Cypress's VIC64 VMEbus Interface Controller with D64 functionality is a single chip designed to minimize the cost and board
area requirements and to maximize the performance of a VMEbus master/slave module. Data transfers of 70 Mbyte/sec are possible between boards using VIC64.
In addition to D8, D16 and D32 operations, the VIC64 performs
D64 data transfer. The VIC64 is designed with an advanced CMOS
process using high-performance standard cells. On-chip output
buffers are used to provide direct connection to address and data
lines.
The VIC64 is based on the industry-standard VIC068A. For most
applications, the VIC64 is fully software and plug compatible with
the VIC068A. (As VIC64 uses register bits that are unassigned in
VIC068A, user code may require simple rework to insure compatibility.)
The local bus interface of the VIC64 emulates Motorola's family of
32-bit 68K processor interfaces. Other processors can easily be
adapted to interface to the VIC64 using appropriate logic.
Resetting the VIC64
The VIC64 can be reset by any of three distinct reset conditions:
• Internal Reset. This reset is the most common means of resetting the VIC64. It resets selected register values and logic
within the device.
• System Reset. This reset provides a means of resetting the
VIC64 through the VMEbus backplane. The VIC64 may also
initiate a system reset by writing a configuration register.
• Global Reset. This provides the most complete reset of the
VIC64. It resets all of the VIC64's configuration registers.
All three reset options are implemented in a different manner and
have different effect on the VIC64 configuration registers.
VIC64 VMEbus System Controller
The VIC64 is capable of operating as the VMEbus system controller. It provides VMEbus arbitration functions, including:
• Priority, round-robin, and single-level arbitration schemes
• Driving lACK daisy-chain
• Driving BGiOUT daisy-chain (all four levels)
• Driving SYSCLK output
• VMEbus arbitration timeout timer
The system controller functions are enabled by the SCaN pin of C/)
the VIC64. This pin is sampled during Reset and if Law, VIC64
performs as system controller. After Reset the pin becomes an out- ...
put signifying a D64 transfer.
=
VIC64 VMEbus Master Cycles
The VIC64 is capable of becoming the VMEbus master in response to a request from local resources. In this situation, the local
resource requests a VMEbus transfer. The VIC64 makes a request
for the VMEbus. When the VMEbus is granted to the VIC64, it
then performs the transfer and acknowledges the local resource
and the cycle is complete. The VIC64 is capable of all four VMEbus request levels. In addition, the following release modes are
supported:
•
•
•
•
•
10-1
Release On Request (ROR)
Release When Done (RWD)
Release On Clear (ROC)
Release Under RMC Control
Bus Capture And Hold (BCAP)
~
:~PRESS
==.
~.,
VIC64·
SEMICONDUCTOR
Pin Configurations
Pin Grid Array (PGA)
Bottom View
B
c
D
E
F
WI:2
DACRO
0R02
0R05
ASIZ1
ASIZO
S[SE[1
wmm
L06
SlT
J15I1
VOO
0R01
0R04
0R06
JCFSE[
MWE!
A01
L02
L05
[)EO[R
J15I0
LAEN
0R03
0R07
VSS
S[SE[0
VSS
L01
L03
L07
LOCATOR
PIN
LA7
LOO
L04
S'7SFAf[
LA3
LA5
LA6
IACKIN
meR
AMO
LA2
LA4
VSS
VSS
AS"
AM1
LA1
LAO
VOO
VSS
AM2
AM3
8
CS
DSACK1
OS
VOO
IWORO
AM4
9
PAS
J:BERR
RESET
srnR
WRITE
AM5
10
0SACK0
RfW
FC1
Brl2
J:iS1
J:iS0
11
RALT
lmC
03R
JmS'i'
BR1
BRo
12
FC2
SIZO
"SCON/064
CLK64M
LAOI
VSS
VOO
VSS
VOO
000
BGOOT1
JmlN2
BGlNo
1':!F!3
VSS
13
SIZ1
TF!Em
LAOO
LEOI
OOIR
[WOEfJlN
rn:oo
006
003
001
VSS
BGOUTo
JmlN3
JmlN1
BCIJl
14
mG
ABEN
VOO
LEOO
~
sworn
TSOBE
007
005
004
002
mIDOT3
mIDOT2
SYSCLK
VSS
15
A
VSS
G
H
J
K
FCIACR
L
M
N
p
A02
A04
VOO
vss
11'm4
A03
A05
A07
11'm3
11'm7
2
A06
11'm1
11'm2
11'm6
ACFAf[
3
11'm5
VOO
lACKOUT
4
R
~ DTACK
5
6
7
VIC64-1
10-2
=--~
_-1=
~,
VIC64
CYPRESS
SEMlCONDUcrOR
Pin Configurations (continued)
Quad Flatpack (QFP)
Top View
VSS
VSS
vss
VSS
iPLo
iPL1
LBG
IRESET
IPl2
SCON/064
VOO
CLK64M
LAEN
ABEN
LlAKO
LAOO
LlRQ1
LlRQ2
LAOI
LEOI
LlRQ3
VOO
URQ4
LEOO
LlRQ5
OOIR
LlRQ6
0Rtl7
UWOENIN
VSS
ASIZ1
ASIZO
OENO
LWOENIN
ICFSEL
SWOEN
SLSEL1
ISO BE
VSS
SLSELO
VOO
VSS
WORD
007
FCIACK
006
A1
DOS
004
VSS
VOO
003
A2
A3
002
A4
001
VOO
000
AS
A6
A7
VSS
VSS
BGOUT2
BGOUT3
BGOuT1
Tlm1
BGOUTO
iRo2
iRo3
iRo4
SYSCLK
BGIN3
BGIN2
VSS
VSS
VSS
vss
VIC64-2
10-3
I
tn
::l
m
iC.:? ~PRFSS
VIC64
~_, SEMICONDUCTOR
Functional Description (continued)
The VIC64 supports A32, A24, and A16, as well as user-defined
address spaces.
Master Write-Posting
The VIC64 is capable of performing master write-po~ting (bus decoupling). In this situation, the VIC64 acknowledges the local resource immediately after the request to the VIC64 is made, thus
freeing the local bus. The VI C64latches the local data to be written
and performs the VMEbus transfer without the local resource having to wait for VMEbus arbitration.
Indivisible Cycles
Read-modify-write cycles and indivisible multiple-address cycles
(IMACs) are easily performed using the VIC64. Significant control
is allowed for:
• Requesting the VMEbus on the assertion of RMC independent of MWB (this prevents any slave access from interrupting
local indivisible cycles)
• Stretching the VMEbus AS
• Making the above behaviors dependent on the local SIZi
signals
Deadlock
If a master operation is attempted when a slave operation to the
same module is in progress, a deadlock condition occurs. The
VIC64 signals a deadlock condition by asserting the DEDLOCK
signal. This should be used by the local resource requesting the
VMEbus to try the transfer after the slave access has completed.
Self-Access
If the VIC64, while it is VMEbus master, has a slave select signaled, a self-access has occurred. The VIC64 asserts BERR and
LBERR.
VIC64 VMEbus Slave Cycles
The VIC64 is capable of operating as a VMEbus slave controller.
The VIC64 contains a highly programmable environment to allow
for a wide variety of slave configurations. The VIC64 allows for:
• D64, D32, D16, or D8 configuration
• A32, A24, A16, or user-defined address spaces
• Programmable block transfer support including:
- DMA-type block transfer (PAS and DSACKi held asserted)
- Non DMA-type block transfer (toggle PAS& and DSACKi)
- No support for block transfer
• Programmable data acquisition delays
• Programmable PAS and DS timing
• Restricted slave accesses (supervisory accesses only)
When a slave access is required, the VIC64 requests the local bus.
When local bus mastership is obtained, the VIC64 reads or writes
the data to/from the local resource and asserts the DTACK signal
to complete the transfer.
propriate AM codes through the VIC64 FCi and ASIZi signals, as
well as the block transfer status. For slave accesses, the VIC64 decodes the AM codes and checks the slave select control registers to
see if the slave request is to be supported with regard to address
spaces, supervisory accesses, and block transfers. The VIC64 also
supports user-defined AM codes; that is, the VIC64 can be made to
assert and respond to user-defined AM codes.
VIC64 VMEbus Block Transfers
The VIC64 is capable of both master and slave block transfers. The
master VIC64 performs a block transfer in one of two modes:
• The Master Block Transfer with Local DMA (D16, D32, and
D64)
• The MOVEM-type Block Transfer (D16 and D32)
In addition to these VMEbus block transfers, the VIC64 is also capable of performing block transfers from one local resource to
another in a DMA-like fashion. This is referred to as a module-based DMA transfer.
For D32 block transfers, the VMEbus specification restricts block
transfers from crossing 256-byte boundaries without toggling the
address strobe, in addition to restricting the maximum length of the
transfer to 256 bytes. The VIC64 allows for easy implementation of
block transfers that exceed the 256-byte restriction by releasing the
VMEbus at the appropriate time and re-arbitrating for the bus at
a programmed time later (this in-between time is referred to as the
interleave period), while at the same time holding both the local
and VMEbus addresses with internal latches. All of this is performed without processor/software intervention until the transfer
is complete. For D64 block transfers, the VMEbus specification allows for bursts of up to 2048 bytes.
The VIC64 contains two separate address counters for the VMEbus and local address buses. In addition, a separate address counter
is provided for slave block transfers. The VIC64 address counters
are 8-bit up-counters that provide for transfers up to 256 bytes. For
transfers that exceed the 256 byte limit, the external counters and
latches are required.
The VIC64 is capable ofperformingA32/A16:D641D321D16 master block transfers. For D64 transfers, external logic is required for
the multiplexing of the data and address signals for the upper 24
address/data lines. Multiplexing for the lower 8 bits is done within
the VIC64.
The VIC64 allows slave accesses to occur during the interleave period. Master accesses are also allowed during interleave with programming and external logic. This is referred to as the dual-path
option.
MOVEM Master Block Transfer
Slave Write-Posting
This mode of block transfer provides the simplest implementation
ofVMEbus block transfers. For this mode, the local resource simply configures the VIC64 for a MOVEM block transfer and proceeds with the consecutive-address cycles (such as a 68KMOVEM
instruction). The local resource continues as the local bus master in
this mode.
Master Block Transfers with Local DMA
The VIC64 is capable of performing a slave write-post operation
(bus decoupling). When enabled, the VIC64 latches the data to be
written, and acknowledges the VMEbus (asserts DTACK) immediately thereafter. This prevents the VMEbus from having to wait
for local bus access.
In this mode, the VIC64 becomes the local bus master and reads or
writes the local data in a DMA-like fashion. This provides a much
fasterinterface than the MOVEMbiock transfer, but with less control and fault tolerance.
D64 block transfers are not supported by MOVEM protocol.
Address Modifier (AM) Codes
The VIC64 encodes and decodes the VMEbus address modifier
codes. For VMEbus master accesses, the VIC64 encodes the ap-
10-4
~
=:.
~
VIC64
~=CYPRESS
~,
SEMICONDUCTOR
VIC64 Slave Block Transfer
The VIC64 is capable of decoding the address modifier codes to
determine that a slave block transfer is desired. In this mode, the
VIC64 captures the VMEbus address, and latches it into internal
counters. For subsequent cycles, the VIC64 simply increments this
counter for each transfer. The local protocol for slave block transfers can be configured in a full handshake mode by toggling both
PAS and DS and expecting DSACKi to toggle, or in an accelerated
mode in which only DS toggles and PAS is asserted throughout the
cycle.
For D64 slave block transfers, the SCON!D64 signal is asserted to
indicate a D64 transfer is in progress. External logic is required to
de-multiplex the data from the VMEbus address bus for the upper
24 address/data lines. The lower 8 bits are done within the VIC64.
Module-Based DMA Transfers
The VIC64 can act as a DMA controller between two local resources. This mode is similar to that of master block transfers with
local DMA, with the exception that the VMEbus is not the source
or destination.
VIC64 Interrupt Generation and Handling Facilities
The VIC64 can generate and handle a seven-level prioritized interrupt scheme similar to that used by the Motorola 68K processors.
These interrupts include:
• 7 VMEbus interrupts
• 7 local interrupts
• 5 VIC64 error/status interrupts
• 8 interprocessor communication interrupts.
The VIC64 can be configured to act as handler for any of the seven
VMEbus interrupts. The VIC64 can generate the seven VMEbus
interrupts as well as supplying a user-defined status/lD vector. The
local priority level (IPL) for VMEbus interrupts is programmable.
When configured as the system controller, the VIC64 drives the
lACK daisy chain.
The local interrupts can be configured with the following:
•
•
•
•
User-defined local interrupt priority level (IPL)
Option for VIC64 to provide the status/lD vector
Edge or level sensitivity
Polarity (rising/falling edge, active HIGH/LOW)
The VIC64 is also capable of generating local interrupts on certain
error or status conditions. These include:
• ACFAIL asserted
• SYSFAIL asserted
• Failed master write-post (BERR asserted)
• Local DMA completion for block transfers
• Arbitration timeout
• VMEbus interrupter interrupt
The VIC64 can also interrupt on the setting of a module or global
switch in the interprocessor communication facilities.
Interprocessor Communication Facilities
The VIC64 includes interprocessor registers and switches that can
be written and read through VMEbus accesses. These are the only
such registers that are directly accessible from the VMEbus. Included in the interprocessor communication facilities are:
• Four general-purpose 8-bit registers
• Four module switches
• Four global switches
• VIC64 version/revision register (read-only)
• VIC64 resetlhalt condition (read-only)
• VIC64 interprocessor communication register semaphores
When set through a VMEbus access, these switches can interrupt a
local resource. The VIC64 includes module switches that are intended for a single module, and global switches which are intended
to be used as a broadcast.
Operating Range
Range
Commercial
Ambient
Temperature
O°Cto +70°C
Industrial
-40°C to +85°C
5V ± 10%
Military
-55°C to + 125°C
5V ± 10%
Related Documents
VIC64/CY7C964 Design Notes
VIC068AIVAC068A User's Guide
Ordering Information
Ordering Code
Package
Name
Package 1Ype
VIC64-BC
B144
145-Pin Plastic Pin Grid Array
VIC64-GC
G145
145-Pin Ceramic Pin Grid Array
VIC64-NC
N160
160-Lead Plastic Quad Flatpack
VIC64-UC
U162
160-Lead Ceramic Quad Flatpack
VIC64-GI
G145
145-Pin Ceramic Pin Grid Array
VIC64-UI
U162
160-Lead Ceramic Quad Flatpack
VIC64-GM
G145
145-Pin Ceramic Pin Grid Array
VIC64-GMB
G145
145-Pin Ceramic Pin Grid Array
VIC64-UMB
U162
160-Lead Ceramic Quad Flatpack
VIC64-UM
U162
160-Lead Ceramic Quad Flatpack
Document #: 38-00196-A
10-5
Vee
5V±5%
Operating
Range
Commercial
Industrial
Military
VIC068A
CYPRESS
SEMICONDUCTOR
-
Features
• Complete VMEbus interface controller and arbiter
- 58 internal registers provide configuration control and status of
VMEbus and local operations
- Drives arbitration, interrupt, address modifier utility, strobe, address lines A07through AOI and
data lines D07 through DOO directly, and provides signals for control
logic to drive remaining address
and data lines
- Direct connection to 68xxx family
and mappable to non-68xxx processors
• Complete master/slave capability
- Supports read, write, write posting,
and block transfers
- Accommodates VMEbus timing requirements with internal digital
delay line (Ih-c1ock granularity)
- Programmable metastability delay
- Programmable data acquisition
delays
- Provides timeout timers for local
bus and VMEbus transactions.
• Interleaved block transfers over
VMEbus
- Acts as DMA master on local bus
- Programmable burst count, transfer length, and interleaved period
interval
VMEbus Interface Controller
•
•
•
•
Supports local module-based
DMA.
Arbitration support
- Supports single-level, priority and
round robin arbitration
- Supports fair request option as requester.
Interrupt support
- Complete support for the VMEbus
interrupts: interrupter and interrupt handler
- Seven local interrupt lines
- 8-level interrupt priority encode
- Total of 29 interrupts mapped
through the VIC068A.
Miscellaneous features
- Refresh option for local DRAM
- Four broadcast location monitors
- Four module-specific location monitors
- Eight interprocessor communications registers
- PGA or QFP packages
- Compatible with IEEE Specification 1014, Rev. C
- Supports RMC operations
See the VIC068AJVAC068A User's
Guide for more information
10-6
Functional Description
The VMEbus interface controller
(VIC068A) is a single chip designed to
minimize the cost and board area requirements and to maximize performance of the
VMEbus interface of a VMEbus master/
slave module. This can be implemented on
either a 8-bit, I6-bit, or 32-bit VMEbus
system. The VIC068A was designed using
high-performance standard cellson an advanced I-micron CMOS process. The
VIC068A performs all VMEbus system
controller functions plus many others,
which simplify the development of a VMEbus interface. The VIC068A utilizes patented on-chip output buffers. These
CMOS high-drive buffers provide direct
connection to the address and data lines. In
addition to these signals, the VIC068A
connects directly to the arbitration, interrupt, address modifier, utility ~nd strobe
lines. Signals are provided which control
data direction and latch functions needed
for a 32-bit implementation.
The VIC068A was developed through the
efforts of a consortium of board vendors,
under the auspices of the VMEbus International ltade Association (VITA). The
VIC068A thus insures compatibility between boards designed by different manufacturers.
6f:~
;:'" CYPRESS
VIC068A
_ . , SEMICONDUcrOR
Pin Configurations
Pin Grid Array (PGA)
Bottom View
B
c
D
VSS
Jl5I:2
"DACRO
ITR02
ITR05
ASIZ1
ASIZO
L06
BIT
lJ5[1
VOO
ITR01
ITR04
LD2
L05
iJEDIl(
lJ5[0
LAEN
ITR03
L01
L03
L07
LOCATOR
PIN
LA7
LDO
LA3
E
F
p
J
K
L
M
N
S[SE[1
WOIID
FlACK
A02
A04
VOO
VSS
1R04
ITR06
JCFSE[
MWB
A01
A03
A05
A07
1R03
1R07
2
ITR07
VSS
S[SE[0
VSS
A06
fR01
JR02
1A06
ACFAf[
3
1A05
VDD
lACKOOT
4
LD4
SYSFAf[
I~
JJrl\CK
5
LA5
LA6
lACISm
PI09!
~
PI05!
iOWA
PI08!
PI07
lOSID
VSS
LA29
VSS
VOO
VOO
VSS
LA13
LA9
LAll
PI010
CS
LA31
LA26
LA24
LA22
fOSID
LA17
LA15
LA14
LA12
LA8
RI:SET
14
LA30
SFfRCS
LA28
LA27
LA25
LA23
LA21
LA19
LA20
LA18
LA16
LAl0
JOSro!
15
PI012!
I
VAC068-3
10-16
£;A-
~~
_'lE
-iF
VAC068A
CYPRESS
SEMICONDUCTOR
Pin Configurations (continued)
Quad Flatpack (QFP)
Top View
CD
~
o
a:
00
00
»
VSS
VSS
VSS
VSS
VOO
PI06-IOSEL3
LAOO
SWOEN
PI07
PI013-IOSEL2
'AS
PI08-IOSEL4
LOMACK
PI09-IOSEL5
PI010
OOIR
ABEliI
PI011
VSS
VSS
9
10
CS
LA(30)
11
PI04-IORO
12
PI012-'SFrnCS
LAOI
13
LA(31)
VSBSEL
IBFI
14
15
LA(28)
LA(29)
BLT
16
LA(26)
REFGT
17
LA(24)
SLSELO
18
ICFSEL
19
LA(25)
VOO
VSS
20
21
VSS
VOO
SLSEL1
22
LA(23)
10(8)
23
LA(22)
10(10)
24
LA(21)
10(9)
25
VSS
10(11)
26
27
LA(19)
VOO
IOSEL1
10(12)
28
LA(27)
LA(20)
10(13)
29
LA(17)
10(14)
30
31
VSS
32
33
LA(15)
LA(16)
WORO
10(15)
rnACr<
LA(18)
ASIZ1
34
35
LA(13)
LA(14)
CPUCLK
36
LA(10)
FCO
FC1
37
38
LA(12)
LA(9)
VSS
39
VSS
VSS
40
vss
ASIZO
Ien
=>
m
VAC068-4
10-17
#::4
VAC068A
• CYPRESS
~ . SEMICONDUCTOR
•
VlC068A1VAC068A on 68030 Board
512/256K X 36 ORAM
512/256K X 36 ORAM
68030
4 JEOEC EPROMS
'-------------------1 FCT
024- 031
'-------------------1 FCT
016 - 023
r------------------I ~3
r-----------~ 5~
Al-A7
VAC068
08-015
DRAM
1/0
VAC068-5
VMEbus EPROM
A(8-31)
10-18
~
~~PRFSS
SEMICONDUcrOR
VAC068A
-===,
Operating Range
Ambient
Temperature
Range
Commercial
O°Cto +70°C
VDD
5V±5%
Industrial
-40°C to +85°C
5V ± 10%
Military
-55°C to +125°C
5V ± 10%
Related Documents
VIC068A/VAC068A User's Guide
VIC64/CY7C964 Design Notes
Ordering Information
Ordering Code
Package
Name
Package 1)rpe
VAC068A-BC
B144
145-Pin Plastic Pin Grid Array
VAC068A-GC
G145
145-Pin Ceramic Pin Grid Array
VAC068A-NC
N160
160-Lead Plastic Quad Flatpack
VAC068A-UC
U162
160-Lead Ceramic Quad Flatpack
VAC068A-GI
G145
145-Pin Ceramic Pin Grid Array
VAC068A-UI
U162
160-Lead Ceramic Quad Flatpack
VAC068A-GM
G145
145-Pin Ceramic Pin Grid Array
VAC068A-GMB
G145
145-Pin Ceramic Pin Grid Array
VAC068A-UM
U162
160-Lead Ceramic Quad Flatpack
VAC068A- UMB
U162
160-Lead Ceramic Quad Flatpack
Operating
Range
Commercial
Industrial
Military
Document #: 38-00169- B
I
10-19
CY7C964
CYPRESS
SEMICONDUCTOR
Features
• Comparators, counters, latches, and
drivers minimize logic requirements
for a variety of multiplexed and nonmultiplexed buses
• Directly drives VMEbus address and
data signals
• 8-/16-bit comparator for slave address
decoding
• Flexible interface optimized for VMEbus applications
• Companion device to Cypress VMEbus family of components
• Replaces multiple SSI/MSI components
• Cascadeable
• 64-pin QFP package
• See the VIC64/7C964 Design Notes for
more information
Functional Description
The CY7C964 integrates several spaceconsuming functions into one small package, freeing board space for the implementation of added-value board features.
It contains counters, comparators, latches,
and drivers configured to be of value to implementors of any backplane interfacewith
address and data buses, particularly VME-
Bus Interface Logic Circuit
bus interfaces. The on-chip drivers are suitable for driving the VMEbus directly. The
CY7C964 is ideal in applications where
high-performance and real estate are primary concerns.
Although having many applications, the
Bus Interface Logic Circuit is an ideal companion part to Cypress's VMEbus family
of components, the VIC068A and the
VIC64. It is intended to drive the address
and data buses (only the three upper bytes,
as the VIC068A/VIC64 drives the lower
byte of data and address buses), so three of
these small devices are needed per controller. The VIC068A/VIC64 provides the
control and timing signals to control the
Bus Interface Logic Circuit as it acts as a
bridge between the VMEbus and the Local
bus.
Application with VMEbus
Architecture
Use with Cypress VMEbus Controllers
The CY7C964 Bus Interface Logic Circuit
is a seamless interface between the
VIC068A/VIC64 and the VMEbus signals.
The device functions equally well in the established 32-bit VMEbus arena and the
emerging 64-bit VMEbus standard. The
device contains three 8-bit counters to ful-
fill the functions of Block counters, and
DMA counters as implied by the D64 portion of the VMEbus specification. It also
contains the necessary multiplexing logic
to allow the 64-bit-wide VMEbus path to
be funnelled to and from the 32-bit local
bus. Control circuitry is included to manage the switching ofthe 32-bit address bus
during normal (32-bit) operations, and
during MBLT (64-bit) operations. All the
controls for these operations are directly
provided from the VIC068A/VIC64. The
on-chip drivers are capable of driving the
VMEbus directly (48 rnA).
Use in Other VMEbus Controller
Implementations
The CY7C964 circuitry is designed to be of
use to designers of VMEbus circuitry, including VSB (VME subsystem bus) and
designs not requiring the features of the
Cypress VIC068A and VIC64. The logic
diagram includes general-purpose blocks
of comparators, counters, and latches that
can be controlled using the flexible control
interface to allow many different options
to be implemented. Although the device is
packaged in a small 64-pin package, the
use of multiplexed input and output pins
provides access to the many internal functions, thus saving external circuitry.
Pin Configuration
PQFP/CQFP
Top View
~59~9~9~~§S9~9:5~
GNO
L07
LOS
FC1
STlmBE
MWE!
[COOT
GNO
\1COMJ5
IlOOOT
LAOO
LAOI
LEOI
LEOO
A7
GNO
16
r--Q)mo""C\lC')~Il)COr--.CX)cno,....C\I
,...,...,....C\lC\lC\lC\lC\lC\lC\lC\lC\lC\I(I')t')(")
10-20
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GNO
LOO
LAO
OENJN
1JENJN1
LAEN
mN
IJCIN
VCC
m
064
0EfID
ABEN
DO
AO
GNO
~~
_'= CYPRESS
~,
CY7C964
SEMICONDUCTOR
Application with Other Bus Architectures
The CY7C964 is optimized for applications requiring wide buffers
and high-performance multiplexing operations. The architecture
can be configured to provide functions such as 16-bit bidirectional
three-state latch and 16-bit comparator with mask register, or
more complex functions such as 16-to-8 pipelined bidirectional
multiplexer with address counter/comparator circuitry. The device
can be cascaded to generate counters and comparators suitable for
multiple byte address/data buses. The on-chip 48 rnA drivers can
be directly connected to many standard backplane buses,
Ordering Information
Ordering Code
Package
Name
Package 1Ype
CY7C964-NC
N65
64-Lead Plastic Quad Flatpack
CY7C964-UC
U64
64-Lead Ceramic Quad Flatpack
Operating
Range
Commercial
CY7C964-UI
U64
64-Lead Ceramic Quad Flatpack
Industrial
CY7C964-UM
U64
64-Lead Ceramic Quad Flatpack
Military
CY7C964- UMB
U64
64-Lead Ceramic Quad Flatpack
Related Documents
VIC64/CY7C964 Design Notes
VIC068A/VAC068A User's Guide
Document #: 38-00197-A
I
10-21
=y -
~~
==--=' 1=
~JF
CYPRESS
SEMICONDUCTOR
Military Information
Section Contents
Page Number
Military Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1
Military Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2
Military Ordering Information ................ .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-7
Military Overview
Features
Success in any endeavor requires a high level of dedication to the
task. Cypress Semiconductor has demonstrated its dedication
through its corporate commitment to support the military marketplace. This commitment starts with product design. All products
are designed using our state-of-the-art CMOS and BiCMOS processes, and they must meet the full - 55 to + 125 degrees Celsius
operational criteria for military use. The commitment continues
with the 1986 DESC certification of our automated U.S. facility in
San Jose, California. The commitment shows in our dedication to
meet and exceed the stringent quality and reliability requirements
of MIL-STD-883D and MIL-M-3851OJ. It shows in Cypress's
participation in each of the military processing programs: MILSTD-883D compliant, SMD (Standardized Military Drawing),
and JAN. Finally, our commitment shows in our leadership position in special packages for military use.
Product Design
Every Cypress product is designed to meet or exceed the full temperature and functional requirements of military product. This
means that Cypress builds military product as a matter of course,
rather than as an accidental benefit of favorable test yield. Designs
are being carried out in our industry-leading O.65-micron CMOS
and BiCMOS processes. Cypress is able to offer a family of products that are industry leaders in density, low operating and standby
current, and high speed. In addition, our technology results in
products with very small manufacturable die sizes that will fit into
the LCCs and flatpacks so often used in military programs.
DESC-Certified Facility
On May 8, 1986, the Cypress facility at 3901 North First Street in
San Jose, California was certified by DESC for the production of
JAN Class B CMOS Microcircuits. This certification not only allows Cypress to qualify product for JAN use, but also assures our
customers that our San Jose Facility has the necessary documentation and procedures to manufacture product to the most stringent
of quality and reliability requirements. Our wafer fabrication facilities are Class 10 (San Jose) and Class 1 (Round Rock, TX and
Bloomington, MN) manufacturing environments and our assembly facility is also a clean room.
Data Sheet Documentation
Every Cypress final data sheet is a corporate document with a revision history. The document number and revision appears on each
final data sheet. Cypress maintains a listing of all data sheet documentation and a copy is available to customers upon request. This
gives a customer the ability to verify the current status of any data
sheet and it also gives that customer the ability to obtain updated
specifications as required.
Every final data sheet also contains detailed Group A subgroup
testing information. All of the specified parameters that are tested
at Group A are listed in a table at the end of each final data sheet,
with a notation as to which specific Group A test subgroups apply.
Assembly Traceability Code@
Cypress Semiconductor places an assembly traceability code on
every military package that is large enough to contain the code.
The ATC automatically provides traceability for that product to
the individual wafer lot. This unique code provides Cypress with
the ability to determine which operators and equipment were used
in the manufacture of that product from start to finish.
Quality and Reliability
MIL-STD-883D and MIL-M-3851OJ spell out the toughest of
quality and reliability standards for military products. Cypress
products meet all ofthese requirements and more. Our in-house
quality and reliability programs are being updated regularly with
tighter and tighter objectives. Please refer to the chapter on Quality, Reliability, and Process Flows for further details.
Military Product Offerings
Cypress offers three levels of processing for military product.
First, all Cypress products are available with processing in full
compliance with MIL-STD-883, Revision D.
Second, selected products are available to the SMD (Standardized
Military Drawing) program administered by DESC. These products are not only fully MIL-STD-883D compliant, but are also
screened to the electrical requirements of the applicable military
drawing.
Third, selected products are available as JAN devices. These products are processed in full accordance with MIL-M-3851OJ and
they are screened to the electrical requirements ofthe applicable
JAN slash sheet.
Product Packaging
III
All packages for military product are hermetic. A look at the package appendix in the back of this data book will give the reader an
appreciation of the variety of packages offered. Included are cerDIPs, windowed CerDIPs, leadless chip carriers (LCCs), win- >
dowed leadless chip carriers, cerpaks, windowed cerpaks, quad
cerpaks, windowed quad cerpaks, bottom-brazed flatpacks, and ~
pin grid arrays.
::::i
a:::
Summary
Cypress Semiconductor is committed to the support of the military marketplace. Our commitment is demonstrated by our product designs, our DESC-certified facility, our documentation and
traceability, our quality and reliability programs, our support of all
levels of military processing, and by our leadership in special packaging.
Assembly Traceability Code is a trademark of Cypress Semiconductor Corporation.
11-1
i
"'~PRFSS
~.,
Military Product Selector Guide
SEMICONDUcrOR
Static RAMs
Size
Organization
64
64
64
64
64
1K
1K
1K
lK
1K
4K
4K
4K
4K
4K
4K
4K
4K
4K'
4K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16 x 4-lnverting
16x4-Non-Inverting
16x4-lnverting
16x4-Non-Inverting
16x 4-lnvertinglLow Power
256x4-10KllOKHECL
256x4
256x4
25px4
256x4
4Kx l'-CS Power-Down
4Kx1-CSPower-Down
4Kx 1'-CS Power-Down
4Kx l'-CS Power-Down
1Kx 4-10KllOKH ECL
1Kx4-CS Power-Down
1Kx4-CS Power-Down
1Kx4
1Kx4
1Kx 4-Separate I/O
1Kx8-Dual Port
1Kx 8-Dual-PortSlave
4Kx4'-CSECL
2Kx8-CS Power-Down
2Kx8-CSPower-Down
2Kx8-CS Power-Down
16Kx 1-CS Power-Down
4Kx4-CS Power-Down
4Kx4
4Kx 4-0utput Enable
4Kx 4-Separate I/O
4Kx 4-Separate I/O, PowerDown
2Kx8-Dual-Port
2Kx8-Dual-Port Slave
4Kx8-Dual-Port
4Kx8-Dual-Port
4Kx8-Dual-PortSemaphores
4Kx 8-Dual-Port Semaphores
Int,Busy
4Kx9-Dual-Port Semaphores
Int,Busy
8Kx 8-CS Power-Down
8Kx8'-CSPower-Down
8Kx8'-CS Power-Down
8Kx8-CSPower-pown
8Kx8-CS Power-Down
8Kx8-CS Power-Down
8Kx8-CS Power-Down
16Kx 4-CS Power-Down
16Kx 4-CS Power-Down
16Kx4-CS Power-Down
16Kx 4-CS Power-Down
16Kx 4-0utput Enable
16Kx 4-0utput Enable
16Kx 4-Separate I/O, T-write
16Kx 4-Separate I/O
16Kx 4-Separate I/O, T-write
16Kx 4-Separate I/O
64Kx 1'-CS Power-Down
8Kx8-Dual-Port Semaphores
Int,Busy
8Kx9-Dual-PortSemaphores
Int,Busy
16K
16K
32K
32K
32K
32K
32K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
Pins
(DIP)
16
16
16
16
16
24
22
24S
22
22
18
18
18
18
24
18
18
18
18
24S
48
48
28
JAN/SMD
Number
Part Number
24S
24S
CY7C189
CY7C190
CY27S03/A
CY27S07/A
CY27LS03
CYlOE422L
CY7C122
CY7C123
CY9122/91L22
CY93422N93L422A
CY7C147
CY2147
CY7C147
CY2147
CYlOE474L
CY7C148
CY2148
CY7C149
CY2149
CY7C150
CY7C130/31
CY7C140/41
CY10E484L
CY7C128A
CY6116N7A
CY7C128A
CY7C167A
CY7C168A
CY7C169A
CY7C170A
CY7C171A
CY7Cl72A
48
48
48
52
52
68
CY7C132/36
CY7C142/46
CY7B134
CY7B135
CY7B1342
CY7B138
68
CY7B139
28S
28S
28S
28S
28
28
28
22S
22S
22S
24S
24S
24S
28S
28S
28S
22S
68
CY7C185A
CY7C185A
CY7C185A
CY7B185
CY7C186A
CY7C186A
CY7C186A
CY7Cl64A
CY7C164A
CY7B164
CY7C166A
CY7C166A
CY7B166
CY7C161A
CY7C162A
CY7B161
CY7B162
CY7C187A
CY7B144
68
CY7B145
24S
24
24S
20
20
20
22S
28S
5962-89694
5962-88594
5962-90696
5962-88594
5962-88594
M38510/289
M3851O/289
5962-88587
5962-88587
5962-91518
M385 10/289
M38510/289
5962-88588
5962-86875
5962-86875
5962-89690
5962-89690
84036
84132
5962-86705
5962-89790
5962-90620
5962-90620
5962-93001
5962-93001
5962-38294
5962-89691
5962-85525
5962-91594
5962-38294
5962-89691
5962-85525
5962-89692
5962-86859
5962-91593
5962-89892
5962-86859
5962-91593
5962-90594
5962-89712
5962-92172
5962-86015
11-2
IccflsullcCDR
883
Availability
tAA .,; 10, 12, 15
tAA =35,45
tAA = 45,55,60,75
tAA =35,45
tAA =45,55
tAA =35,45
tAA =45,55
tAA=5,7
tAA =35,45
tAA=45,55
tAA =35,45
tAA =45,55
tAA = 12, 15,25,35
tAA = 35,45,55
tAA = 35,45,55
tAA=7,1O
tAA=20,25
tAA =20,25
tAA = 35,45,55
tAA =20, 25, 35, 45
tAA = 20,25,35,45
tAA =20, 25,35, 40
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 20,25,35,45
70@25
70@25
100@35
100@25
38@65
150@5/7
90@25
150@15
90@45
90@55
1l0/10@35
140/25@45
1l0/10@35
140/25@45
190@5/7
1l0/l0@35
140/25@45
1l0@35
140@45
100@15
120/40@45
120/40@45
200@1O
125@20
125@20
125/40@25
70/20@25
100/20@25
100/20@35
120@25
100/20@25
90@20
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now'
Now
Now
Now
tAA = 35,45,55
tAA = 35, 45, 55
tAA =25,35
tAA =25,35
tAA =25,35
tAA =25,35
170/65@35
120/40@45
280@25
280@25
280@25
280@25
Now
Now
Now
Now
Now
Now
tAA=25,35
280@25
Now
tAA = 20,25,35,45
tAA=20,25
tAA =35,45
tAA = 10, 12, 15
tAA = 20,25,35,45
tAA =20,25
tAA = 35,45,55
tAA =20,25
tAA =35
tAA = 10,12,15
tAA =20,25
tAA =35
tAA = 10, 12, 15
tAA = 20,25,35
tAA = 20,25,35
tAA= 12,15
tAA = 12,15
tAA = 20,25,35
tAA.=25,35
125@20
125@20
100/20/1 @ 45
145/50@15
125@20
125@20
100/20/1 @ 45
90@20
70/20/1@35
135/50@15
90@20
70/20/1@35
135/50@15
70/20/1@35
70/20/1@35
135/50@15
135/50@15
70/20/1@35
2RO@25
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
tAA =25,35
280@25
Now
Speed (ns)
tAA=25
tAA=25
tAA =25,35
tAA =25,35
tAA= 65
tAA=5,7
tAA:= 25,35
(mA@ns)
~
5..
~~
Military Product Selector Guide
======IE CYPRESS
SEMICONDUcrOR
~,
Static RAMs
(continued)
Size
Organization
64K
64K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
1M
1M
1M
1M
4Kxl8-CacheTag
4Kx 18-Cache Tag
32Kx 8-CS Power-Down
32Kx 8-CS Power-Down
64Kx4--CSPower-Down
64Kx4--CSPD + OE/CEI
64Kx 4--CS, OE
64Kx4--CSPD +OE/CE2
64Kx 4--Separate I/O, T-write
64Kx4--Separate I/O
256Kx l-CS Power-Down
32Kx8-CSPower-Down
32Kx8-CS Power-Down
64Kx4--Separatel/0
64Kx 4--CS Power-Down
64Kx4--CSPD,OE
64Kx 4--CS PD, OE, 2CE
32Kx 9-Synchronous Cache
128Kx8-CSPower-Down
128Kx8-CS Power-Down
256Kx 4--CS Power-Down/OE
256Kx4--Separate I/O,
T-Write
256Kx 4--Separate I/O
IMx l-CS Power-Down
1M
1M
Pins
(DIP)
JAN/SMD
Number
Part Number
68
68
28
28S
24S
28S
28S
28S
28S
28S
24S
28
28S
28S
24S
28S
28S
44
32
32S
28S
32S
CY7B180
CY7B181
CY7C198
CY7C199
CY7C194
CY7C195
CY7C195L
CY7C196
CY7C191
CY7C192
CY7C197
CY7B198
CY7B199
CY7B192
CY7B194
CY7B195
CY7B196
CY7B174
CY7C109A
CY7ClO09
CY7ClO06
CY7ClOOl
32S
28S
CY7ClO02
CY7ClO07
Pins
Part Number
24S
24S
24S
24S
24S
24S
24
24
24S
24S
24S
24S
24S
24S
24S
24
24
28S
/44
28S
/44
24S
24S
24S
24
28S
28S
28
28S
28S
CY7C225
CY7C225A
CY7C235
CY7C235A
CY7C281
CY7C281A
CY7C282
CY7C282A
CY7C245
CY7C245A
CY7C245A
CY7C291
CY7C291A
CY7C293A
CY7C293A
CY7C292
CY7C292A
CY7C258/9
5962-88518(0)
5962-88518(0)
5962-88636(0)
5962-88636(0)
5962-87651(0)
5962-87651(0)
5962-87651(0)
5962-87651(0)
5962-87529(W)
5962-89815(W)
5962-88735(0)
5962-87650(W)
5962-88734(0)
5962-88680(W)
5962-92341(0)
5962-88662
5962-88662
5962-88681
5962-89524
5962-90664
5962-89935
5962-88725
5962-89598
5962-91612
5962-92316
Speed (ns)
Icc/IsWIccDR
(mA@ns)
883
Availability
tAA = 15.20
tAA = 15,20
tAA = 20,25,35,45,55
tAA = 20,25,35,45,55
tAA = 20, 25, 35, 45
tAA = 20, 25, 35, 45
tAA = 25,35,45
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 20,25,35,45
tAA = 15,20
tAA = 12,15,20
tAA = 12,15,20
tAA = 12,15,20
tAA = 12,15,20
tAA = 12,15,20
tAA = 18,21
tAA = 25,35,45
tAA = 15,20,25
tAA = 15,20,25
tAA = 15,20,25
250@15
250@15
180/40@20
180/40@20
150/40@20
150/40@20
120/25@25
150/40@20
150/40@20
150/40@20
150/40@20
170/60@15
170/40@12
170/40@12
170/40@12
170/40@12
170/40@12
250@18
140/30@25
180/40@15
165/40@15
165/40@15
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
1Q94
lQ94
lQ94
lQ94
tAA = 15,20,25
tAA = 15,20,25
165/40@15
145/40@15
lQ94
lQ94
PROMs
Size
4K
4K
8K
8K
8K
8K
8K
8K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
16K
64K
64K
64K
64K
64K
64K
64K
64K
64K
Organization
512x8-Registered
512x8-Registered
lKx8-Registered
lKx8-Registered
lKx8
lKx8
lKx8
1Kx8
2Kx 8-Registered
2Kx 8-Registered
2Kx8-Registered
2Kx8
2Kx8
2Kx8-CS Power-Down
2Kx8-CS Power-Down
2Kx8
2Kx8
2Kx8-Reprogrammable State
Machine
2Kx8-Reprogrammable State
Machine
8Kx8-CSPower-Down
8Kx8-CSPower-Down
8Kx8
8Kx8
8Kx8-Registered
8Kx8-Registered
8Kx8-EPROMPinout
8Kx 8-RegisteredlDiagnostic
8Kx 8-RegisteredlDiagnostic
JAN/SMD
Number!l]-
Speed (ns)
Icc/ISB
(mA@ns)
883
Availability
5962-88734(0)
5926-93122(W)
tSNcO = 30/15, 35/20, 40/25
tSNCO= 25/12,30/15,35/20
tSNco = 30/15,40/20
tSNCO= 25/12,30/15,40/20
tAA=45
tAA=30,45
tAA=45
tAA=30,45
tSNco = 35/15,45/25
tSNco = 18/12,25/12,35/15
tSNcO = 18/12,25/12,35/15
tAA = 25,35,50
tAA = 25,30,35,50
tAA = 25,30,35,50
tAA = 25,30,35,50
tAA=35,50
tAA = 25,30,35,45,50
tcp = 12,15,18
120@30/15
120
120@30/15
120
120@45
120
120@45
120
120@35/15
120@18/12
120@18/12
120@35
120@25
120/30@25
120/30@35
120@35
120@30
200@15
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
CY7C258/9
5926-93123(0)
tcp = 12,15,18
200@15
Now
CY7C261
CY7C261
CY7C263/4
CY7C263/4
CY7C265
CY7C265
CY7C266
CY7C269
CY7C269
5962-87515(W)
5962-90803(0)
5962-87515(W)
5962-90803(0)
5962-89967(0)
5962-89484(W)
5962-91624(W)
5962-90831(0)
5962-90930(W)
tAA = 25,35,45,55
tAA = 25,35,45,55
tAA = 25,35,45,55
tAA = 25,35,45,55
tSNco = 15/12,25/20,50/25
tSNco = 15/12,25/20,50/25
tAA=25,45
tSNcO = 15/12,25/20,50/25
t~A/(,() = 15/12 25/20 50/25
140/50@25
120/30@35
140@25
120@35
140@18/15
120@50/25
140/15@25
140@15/12
140@15/12
Now
Now
Now
Now
Now
Now
Now
Now
Now
11-3
a
-CI;~PR£SS
~_.,
Military Product Selector Guide
SEMICONDUCTOR
PROMs (continued)
Organization
Size
128K
128K
256K
256K
256K
256K
256K
256K
256K
256K
256K
512K
512K
512K
512K
512K
16Kx8-CS Power-Down
16Kx8
Processor Specific
16Kx16
32Kx8-CS Power-Down
32Kx8-CS Power-Down
32Kx B-EPROM Pinout
32Kx 8-EPROM Pinout
32Kx 8-Registered
32Kx8-Registered
32Kx 8-Latched
64Kx 8-Fast Column Access
64Kx 8-EPROM Pinout
64Kx 8-EPROM Pin
64Kx 8-Registered
64Kx8-Registered
Pins
Part Number
28S
28
44
44
28S
28S
28
28
28S
28S
28S
28S
28
28
28S
28S
CY7C251
CY7C254
CY7C270
CY7C276
CY7C271
CY7C271
CY7C274
CY7C274
CY7C277
CY7C277
CY7C279
CY7C285
CY7C286
CY7C286
CY7C287
CY7C287
JAN/SMD
Number!lj·
5962-89537(W)
5962-89538(W)
5962-89817(W)
5962-93166(0)
5962-89817(W)
5962-93166(0)
5962-91744(W)
5962-92155(0)
5962-92322(W)
5962-91637(0)
5962-92071(W)
5962-90913(W)
5962-92065(0)
Speed (ns)
tAA = 45,55,65
tAA = 45,55,65
tcp = 15,20,30
tAA=25, 30, 35
tAA = 35,45,55
tAA=35,45,55
tAA = 35,45,55
tAA = 35,45,55
tSA/CO = 40/20,50/25
tSA/CO = 40/20,50/25
tAA=45,55
tAAfFCA = 75/25,85/35
tAA =60,70
tAA=60,70
tSA/CO = 55/20, 65/25
tSA/CO = 55/20, 65/25
IccflsB
(mA@ns)
120/35@45
120@45
250@25
250@30
130/40@35
130/40@55
130/40@35
130/40@35
130@40
130@40
130/40@45
200@75
150@60
150@60
150@65
150@65
883
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
PLDs
Organization
PAUO
PALC20
PALC20
PLD20
PLD24
PLD24
PLDC24
PLD24
PLDC24
PLD24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC24
PLDC28
PLDC28
PLDC28
PLDC28
PLDC28
PLD28
MAX28
MAX40
MAX68
MAX84
PLDC28
Pins
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
16L8, 16R8, 16R6, 16R4
18GB-Generic
22VlOC-Macrocell
22VlOC-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VIO-Macrocell
22VI0D-Macrocell
22VIO-Macrocell
20G 100Generic
20RAIO-Asynchronous
7C330-State Machine
7C330-state Machine
7C331-Asynchronous
7C331-Asynchronous
7C332-Combinatorial
7C335-Universal State
Machine
7C344-32 Macrocell
7C343--64 Macrocell
7C342-128 Macrocell
7C341-192 Macrocell
7C361-State Machine
Part Number
JAN/SMD
Number!lj·
Speed (ns/MHz)
Icc
(mA@ns/MHz)
883
Availability
20
20
20
20
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
24S
28S
28S
28S
28S
28S
28S
PAL16XX
PALC16XX
PALC16XX
PLDC18G8
PAL22VlOC
PAL22VPlOC
PALC22VlO
PALC22VlOB
PALC22VlO
PALC22VlOB
PALC22VI0B
PALC22VlOB
PALC22VlOD
PALC22VlOD
PLDC20GlO
PLD20RAI0
CY7C330
CY7C330
CY7C331
CY7C331
CY7C332
CY7C335
5962-92338(0)
5962-88678(W)
5962-88713(0)
5962-91568(0)
5962-91760(0)
5962-91760(0)
5962-87539(W)
5962-87539(W)
5962-88670( 0)
5962-88670(0)
M38510/507(W)
M3851O/508(0)
5962-89841(0)
5962-89841(0)
5962-88637(0)
5962-90555(0)
5962-89546(W)
5926-90802(0)
5962-90754(W)
5962-89855(0)
5962-91584(W)
tpD=7,10
tpD = 20,30,40
tPD = 20, 30,40
tPD/S/CO = 15/15/20
tPD/S/CO = 10/3.6/7.5
tPD/S/CO = 10/3.6/7.5
tPD/S/CO = 25/18/15
tPD/S/CO = 20/17/15
tPD/S/CO = 25/18/15
tPD/S/CO = 15/12/10
tPD/S/CO = 15/12/10
tPD/S/CO = 15/12/10
tPD/s/co=10/6/7
tPD/S/CO = 10/6/6
tPD/S/CO = 20/17/15
tPD/SU/CO = 20/10/20
50,40,28 MHz
50,40,28 MHz
tpD = 25,30,40
tpD = 25,30,40
tpD = 20, 25, 30
fMAXS = 66.6,50,83
180@7
70@20
70@20
110
190@1O
190@1O
100@25
100@20
100@25
120@15
120@15
120@15
130@10
150@1O
80@30
100@25
180@40MHz
180@40MHz
200@20MHz
200@20MHz
200@24MHz
160@ 66.6 MHz
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
28S
40/44
68
84
28S
CY7C344
CY7C343
CY7C342
CY7C341
CY7C361
5962-90611(W)
5962-92158(W)
5962-89468(W)
5962-92062(W)
tpD=25,35
tpD = 25,30,35
tpD = 30,35,40
tpD = 30,35,40
100,83,66 MHz
220/170
160/120
320/240
320/240
150@100MHz
Now
Now
Now
Now
Now
FIFOs
Organization
64 x 4-Cascadable
64 x 4--Cascadable
64 x 4--Cascadable/OE
64 x 5-Cascadable
64x5-Cascadable/OE
64x8-Cascadable/OE
64 x 9-Cascadable
512x9-Cascadable
Pins
16
16
16
18
18
28S
28S
28
Part Number
CY3341
CY7C401
CY7C403
CY7C402
CY7C404
CY7C408A
CY7C409A
CY7C420
JAN/SMD
Number
5962-89523
5962-86846
5962-89664
5962-89661
5962-89863
11-4
Speed
1.2,2MHz
10,15,25 MHz
10,15,25 MHz
10,15,25 MHz
10,15,25 MHz
15, 25 MHz
15,25 MHz
tA = 25 30 40 65 ns
IccflsB
(mA@ns/MHz)
60@2.0MHz
90@15MHz
90@25MHz
90@15MHz
90@25MHz
120@25MHz
120@25MHz
140/30@30
883
Availability
Now
Now
Now
Now
Now
Now
Now
Now
--
..-::::==:;;..
. .~
ilE CYPRESS
IF SEMICONDUCTOR
Military Product Selector Guide
--=-
FIFOs
(continued)
Organization
512x9-Cascadable
lKx 9-Cascadable
lKx 9-Cascadable
2Kx 9-Cascadable
2Kx 9-Cascadable
2Kx 9-Bidirectional
4Kx 9-Cascadable
4Kx 9-Cascadable
512 x 9-Clocked
2Kx9-Clocked
512x9-Clocked/Cascadable
2Kx 9-Clocked/Cascadable
8Kx9-HalfFullFlag
8Kx9-Prog. Flags
16Kx 9-HalfFull Flag
16Kx 9-Prog. Flags
32Kx 9-HalfFull Flag
32Kx 9-Prog. Flags
512xI8-Prog. Flags
lKxI8-Prog. Flags
2KxI8-Prog. Flags
Pins
JAN/SMD
Number
Part Number
28S
28
28S
28
28S
28S
28
28S
28S
28S
32
32
28
28
28
28
28
28
52
52
52
CY7C421
CY7C424
CY7C425
CY7C428
CY7C429
CY7C439
CY7C432
CY7C433
CY7C441
CY7C443
CY7C451
CY7C453
CY7C460
CY7C470
CY7C462
CY7C472
CY7C464
CY7C474
CY7C455
CY7C456
CY7C457
5962-89863
5962-91585
5962-91585
5962-88669
5962-88669
5962-92321
5962-90715
5962-90715
5962-93173
5962-93124
5962-93008
5962-93152
IcdIsB
(rnA@ns/MHz)
Speed
tA = 25,30,40,65 ns
tA = 25,30,40,65 ns
tA = 25,30,40,65 ns
tA = 25,30,40,65 ns
tA = 25,30,40,65 ns
tA = 30,40,65 ns
tA = 30,40,65 ns
tA = 30,40,65 ns
tc =14,20,30ns
tc =14, 20, 30ns
tc =14, 20, 30 ns
tc =14, 20, 30ns
tA = 20, 25,40ns
tA = 20, 25,40ns
tA = 20, 25,40ns
tA = 20,25,40 ns
tA = 20, 25,40ns
tA = 20, 25,40ns
tA=1O,15,20ns
tA=1O,15,20ns
tA=1O,15,20ns
147/30@25
140/30@30
147/30@25
140/30@30
147/30@25
170/45@30
160/30@30
160/30@30
160@14
160@14
160@14
160@14
165@25
165@25
165@25
165@25
165@25
165@25
180@70
180@70
180@70
883
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
lQ94
lQ94
lQ94
Logic
Organization
Programmable Skew Clock Buffer
(TIL Outputs)
Programmable Skew Clock Buffer
(CMOS Outputs)
2901--4-BitSlice
2901--4-Bit Slice
4 x 2901-16-Bit Slice
2909-Sequencer
2911-Sequencer
2909-Sequencer
2911-Sequencer
2910--Controller (17-WordStack)
2910--Controller (9-Word Stack)
16x 16 Multiplier
16x16Multiplier
16 x 16 Multiplier/Accumulator
Pins
Part Number
32
CY7B991
32
CY7B992
40
40
64
28
20
28
20
40
40
64
64
64
CY7C901
CY2901C
CY7C9101
CY7C909
CY7C911
CY2909A
CY2911A
CY7C91O
CY2910A
CY7C516
CY7C517
CY7C51O
JAN/SMD
Number
Icc
(rnA@ns)
Speed (ns)
883
Availability
fREF = 15 - 80 MHz
75
Now
5962-93112
fREF = 15 - 80 MHz
75
Now
5962-88535
5962-88535
5962-89517
tCLK=27,32
C
tCLK=35,45
tCLK=30,40
tCLK=30,40
A
A
tCLK = 46,51,99
A
tMC = 42,55,75
tMC = 42,55,75
tMC = 55,65,75
90@27
180@32
85@35
55@30
55@30
90@40
90@40
90@46
170@51
1l0@lOMHz
110@lOMHz
1l0@lOMHz
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
5962-90609
5962-90609
5962-87708
5962-87708
5962-86873
5962-87686
5962-88733
VMEbus Interface Products
Organization
VME Interface Controller
VMEAddress Controller
64-BitVIC
Pins
144/160
144/160
144/160
JAN/SMD
Number
Part Number
VIC068A
VAC068A
VIC64
5962-92010
5962-92009
Part Number
Speed (Mbps)
Icc
(rnA)
Speed (MHz)
64
50
64
250
150
300
883
Availability
Now
Now
Now
Communication Products
Organization
HotLink Transmitter
HotLink Receiver
Pins
28
28
CY7B923
CY7B933
160-330
160 - 330
11-5
Icc
(rnA)
TBA
TBA
Packages
D,L,
D,L,
883
Availability
4Q93
4Q93
III
>
a:
IF (nickel = '1') THEN
drinkStatus <= drinkStatus'SUCC(drinkStatus) i
-- goto Five
ELSIF (dime = '1') THEN
drinkStatus <= Teni
ELSIF (quarter = '1') THEN
drinkStatus <= TwentyFivei
ENDIFi
WHEN Five =>
IF (nickel = '1') THEN
drinkStatus <= .Teni
ELS1F (dime = '1') THEN
drinkStatus <= Fifteeni
ELSIF (quarter = '1') THEN
12-2
,~
5!!!!!!!!!!t
CYPRESS
=
,
~,
PRELIMINARY
CY3120
SEMICONDUCIOR
Functions
A major advantage ofVHDL is the ability to implement functions.
The support of functions allows designs to be reused by simply
specifying a function and passing the appropriate parameters.
Wmp2 features some built-in functions such as ttf(truth-tablefunction). The ttf function is particularly useful for state machine or
look-up table designs. The following code describes a seven-segment display decoder implemented with the ttf function:
giveDrink <= '1';
drinkStatus <= drinkStatus'PRED{drinkStatus) ;
goto Zero
ENDIF;
WHEN oweDime =>
returnDime <= '1';
drinkStatus <= zero;
ENTITY seg7 IS
PORT {
inputs: IN BIT_VECTOR (O to 3)
outputs: OUT BIT_VECTOR (O to 6)
when others =>
This ELSE makes sure that the state
-- machine resets itself if
-- it somehow gets into an undefined state,
drinkStatus <= zero;
END CASE;
END PROCESS;
) ;
END SEG7;
ARCHITECTURE mixed OF seg7 IS
END FSM;
VHDL is a highly typed language. It comes with several predefined operators, such as + and/= (add, not-equal-to). VHDLoffers the capability of defining multiple meanings for operators
(such as + ), which results in simplification of the code written. For
example, the following code segment shows that "count = count
+ 1" can be written such that count is a bit vector, and 1 is an integer.
CONSTANT truthTable:
x01_table (O to 11, 0 to 10)
-- input
&
output
"0000"
"0001"
"0010"
"0011"
"0100"
"0101"
"0110"
"0111"
"1000"
"1001"
"101x"
"111x"
ENTITY sequence IS
port (clk: in bit;
s : inout bit);
end sequence;
ARCHITECTURE fsm OF sequence IS
&
&
&
&
&
&
&
&
&
&
&
&
.-
"0111111",
"0000110" ,
"1011011" ,
"1001111",
"1100110",
"1101101",
"1111101",
"0000111",
"1111111",
"1101111",
"1111100", --creates E pattern
"1111100"
);
SIGNAL count: INTEGER RANGE 0 TO 7'
BEGIN
BEGIN
outputs <= ttf{truthTable,inputs);
PROCESS BEGIN
WAIT UNTIL clk
END mixed;
'1' ;
Boolean Equations
A third design-entry method available to Wa1p2 users is Boolean
equations. Figure 2 displays a schematic of a simple one-bit half adder. The following code describes how this one-bit half adder can
be implemented in Wa1p2 with Boolean equations:
CASE count IS
WHEN 0 1 1 1 2 'I
=>
'1';
count <= count + 1;
WHEN 4 =>
s <= '0';
count <= count + 1;
WHEN 5 =>
s <= '1';
count <= 0"0";
WHEN others =>
s <= '0';
count <= 0"0";
S
<=
--entity declaration
ENTITY half adder IS
PORT (x, y : IN BIT;
sum, carry : OUT BIT) ;
END half_adder;
--architecture body
ARCHITECTURE behave OF half_adder IS
BEGIN
~~
END CASE;
END PROCESS;
END FSM;
In this example, the + operator is overloaded to accept both integer and bit arguments. Wmp2 supports overloading of operators.
12-3
carry
I~D~sum
Figure 2. One-Bit Half Adder
•
~
.
i~PRF.SS
~.,
PRELIMINARY
CY3120
SEMICONDUCTOR
sum <= x XOR y;
carry <= x AND y;
END behave;
Structural VHDL (RTL)
While all of the design methodologies described thus far are highlevel entry methods, structural VHDL provides a method for designing at a very low level. In structural descriptions (also called
RTL), the designer simply lists the components that make up the
design and specifies how the components are wired together. Figure 3 displays the schematic of a simple 3-bit shift register and the
following code shows how this design can be described in Wa1p2
using structural VHDL:
ENTITY shifter3 IS port (
elk : IN BIT;
x : IN BIT;
qO
OUT BIT;
ql : OUT BIT;
q2 : OUT BIT) ;
END shifter3;
ARCHITECTURE shift3 OF c22vlO IS
BEGIN
SH1:shifter3 PORT MAP(
elk
=> pinl,
X
=> pin2,
fbx(qO) => pin14,
fbx(ql) => pin15,
fbx(q2) => pin16) ;
END shift3 ;
As indicated in the architecture statement, this design targets the
Cypress 22V10 for implementing the specified function. By simply
changing the architecture statement and appropriately modifying
the pin assignments, a binding architecture file targeting other Cypress PLDs can easily be generated.
Compilation
ARCHITECTURE struct OF shifter3 IS
SIGNAL qO_temp, ql_temp, q2_temp : BIT;
BEGIN
DFF PORT MAP(x,elk,qO_temp);
dl
DFF PORT MAP(qO_temp,clk,ql_temp);
d2
DFF PORT MAP(ql_temp,elk,q2_temp);
d3
qO <= qO_temp;
ql <= ql_temp;
q2 <= q2_temp;
END struet;
All of the design-entry methods described can be mixed as desired.
The ability to combine both high- and low-level entry methods in a
single file is unique to VHDL. The flexibility and power ofVHDL
allows users of Wa1p2 to describe designs using whatever method is
appropriate for their particular design.
Binding Architecture
The purpose of a binding architecture is to map external signals of
a design to the pins of a physical device. The binding architecture
can be in a separate file or appended to the end of the design file.
Here is a binding architecture file for the 3-bit shift register described in the last example:
USE work.rtlpkg.all;
USE work.shift3pkg.all;
qO
q2
q1
Once a design entity and binding architecture have been completed, a design is compiled using Wa1p2. Although implementation is with a single command, compilation is actually a multistep
process (as shown in Figure 1). The first step is synthesizing the input VHDL into a logical representation of the design. Wa1p2 synthesis is unique in that the input language (VHDL) supports a very
high level of abstraction. Competing PLD compilers require very
specific and device-dependent information in the design input file.
The second step ofcompilation is an iterative process of optimizing
the design and fitting the logicinto the targeted PLD. Logical optimization in Wa1p2 is accomplished with the Espresso algorithms.
The optimized design is fed to the Wa1p2 fitter, which applies the
design to the specified target PLD. The Wa1p2 fitter supports
manual or automatic pin assignments as well as automatic selection
ofD or T flip-flops. After the optimization and fitting step is complete, Warp2 automatically creates a JEDEC file for the specified
PLD.
Simulation
Wa1p2 is delivered with Cypress's PLD ToolKit. PLD ToolKit features a graphical waveform simulator that can be used to simulate
designs generated in Wa1p2. The ToolKit simulator provides functional simulation and features interactive waveform editing and
viewing. The simulator also provides the ability to probe internal
nodes, automatically generate clocks and pulses, and to generate
JEDEC test vectors from simulator waveforms.
Programming
The result of Warp2 compilation is a JEDEC file that implements
the input design in the targeted PLD. Using the JEDEC file, Cypress PLDs can be programmed on Cypress's QuickPro II programmer or on any qualified third-party programmer.
System Requirements
ForPCs
x
clk
d
q
d
q
d
q
clk
Figure 3. Three-Bit Shift Register Circuit Design
IBM PC-AT or equivalent (386 or higher recommended)
PC-DOS version 3.3 or higher
2 Mbytes of RAM (4 Mbytes recommended)
EGA, VGA, or Hercules monochrome display
20-Mbyte hard disk drive
1.2-Mbyte 5l;4-inch or 1.44-Mbyte floppy disk drive
Two or three-button mouse
Windows Version 3.1 or higher (optional)
12-4
.
~
~=CYPRESS
~.r SEMICONDUCTOR
PRELIMINARY
For Sun Workstations
Ordering Information
SPARCCPU
Sun as 4.1.1 or later
16 Mbytes of RAM
1.44-Mbyte 3Yz-inch disk drive
CY3120 Wa1p2 PLD Compiler includes:
5V4-inch, 1.2-Mbyte floppy disks
3Yz-inch, 1.4-Mbyte floppy disks
Wa1p2 User's Guide
Wa1p2 Workbook
Wa1p2 Reference Manual
Registration Card
CY3120
Document #: 38-00218-A
Wa1p2 and PLD ToolKit are trademarks of Cypress Semiconductor Corporation.
PC-AT is a trademark of IBM Corporation.
II
en
..J
o
o~
12-5
ADVANCED INFORMATION
CYPRESS
SEMICONDUCTOR
Wap3 VHDL Development
System for PLDs and FPGAs
Features
• Sophisticated PLD/FPGA design and verification system
based on VHDL
• Walp3 is based on ViewLogic's Powerview environment
- Advanced graphical user interface for Windows and Sun
Workstations
- Schematic capture (ViewDraw
- Interactive timing simulator (ViewSim
- Waveform stimulus and viewing (ViewTrace
- Textual design entry using VHDL
- Graphical VHDL debugger
- Mixed-mode design entry support
- EDIF input/output capability
- VHDL to schematic option (ViewGen
• The core of Wary3 is an IEEE 1076 standard VHDL compiler
- VHDL is an open, powerful design language
- VHDL (IEEE standard 1076) facilitates design portability
across devices and/or CAD platforms
- VHDL facilitates the use of industry-standard simulation
and synthesis tools for board and system-level
design
- VHDL facilitates hierarchical design with support for
functions and libraries
TM
TM )
TM )
TM )
TM )
CY3130
• For synthesis Wary3 supports a rich subset ofVHDL for synthesis including
- Enumerated types
-Integers
- For .•. generate loops
- Operator overloading
• State-of-the-art optimization and reduction algorithms
- Optimization for flip-flop type (D type/ T type)
- Automatic pin assignment
- Automatic state assignment (Gray code, binary, one-hot)
• Completely automatic place and route
- Includes timing back annotation into ViewSim
• Support for ALL Cypress PLDs/FPGAs and PROMs,
including:
- Industry-standard 20- and 24-pin devices like the 22VI0
- Cypress 7C33X family of 28-pin PLDs
- CY7C258/9 State Machine PROMs
-MAX5000
-FLASH37X
-pASIC38X
• Sun and PC platforms
Warp3 Design Flow
SUPPORT FOR ALL
CYPR~Jd'~~&tsROMS,
Document #: 38-00242-A
WaTp2 and PLD ToolKit are trademarks of Cypress Semiconductor Corporation.
PC-AT is a trademark of International Business Machines Corporation.
PowerView, ViewDraw, ViewSim, ViewTrace and ViewGen are trademarks of ViewLogic.
12-6
CY3200
PLDS-MAX + PLUS®
Design System
Features
• Unified development system for Multiple Array MatriX (MAX®) EPLDs
• Hierarchical design entry methods for
both graphical and textual designs
- Multiple-level schematics and
hardware language descriptions
- Library of 7400 Series TTL and bus
macrofunctions optimized for MAX
architecture
- Advanced Hardware Description
Language (AHDL) supporting state
machines, Boolean equations, truth
tables, arithmetic, and relational
operations
- Delay prediction for graphic and
text designs
• Logic synthesis and minimization for
quick and efficient processing
• Compiler that compiles a 100% utilized CY7C342 in only 10 minutes
• Automatic error location for AHDL
text files and schematics
• Interactive Simulator with probe assignments for internal nodes
• Runs on IBM PC/AT®, PS/2® or compatible machines
• Waveform Editor for entering and
editing waveforms and viewing simulation results
Description
The PLDS-MAX + PLUS (Programmable
Logic Development System) is a unified
CAE system for designing logic with Cypress's CY7C340 family of EPLDs (Figure
1). PLDS-MAX + PLUS includes design
entry, design processing, timing simulation, and device programming support.
PLDS-MAX+PLUS runs on IBM PS/2,
PC-AT, or compatible machines, and provides tools to quickly and efficiently create
and verify complex logic designs.
The MAX + PLUS software compiles de"
signs for MAX EPLDs in minutes. Designs may be entered with a variety of design entry mechanisms. MAX + PLUS supports hierarchical entry of both Graphic
Design Files (GDFs) with the
MAX + PLUS Graphic Editor, and Text
Design Files (TDFs) with the Advanced
Hardware
Description
Language
(AHDL). The Graphic Editor offers advanced features such as multiple hierarchy
levels, symbol editing, and a library of7 400
series devices as well as basic SSI gates.
AHDL designs may be mixed into any level of the hierarchy or used on a standalone
basis. AHDL is tailored especially for
EPLD designs and includes support for
complex Boolean and arithmetic functions, relational comparisons, multiple
hierarchy levels, state machines with automatic state variable assignment, truth
tables, and function calls.
In addition to multiple design entry mechanisms, MAX + PLUS includes a sophisticated compiler that uses advanced logic
synthesis and minimization techniques in
conjunction with heuristic fitting rules to
efficiently place designs within MAX
EPI,Ds. A programming file created by
the compiler is then used by MAX + PLUS
to program MAX devices with the QP2MAX programming hardware.
Simulations may be performed with a powerful, event-driven timing simulator. The
MAX + PLUS Simulator interactively displays timing results in the MAX + PLUS
Waveform Editor. Hardcopy table and
waveform output is also available. With
the Waveform Editor, input vector waveforms maybe entered, modified, grouped,
(J)
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o
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MAX and MAX + PLUS are registered trademarks of Altera Corporation.
IBM PC/AT and PS/2 are registered trademarks of International Business Machines Corporation.
QP2-MAX and QuickPro II are trademarks of Cypress Semiconductor Corporation.
12-7
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6
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Figure 1. MAX + PLUS Block Diagram
@
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CY3200
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~= CYPRFSS
SEMICONDUcrOR
and ungrouped. In addition, the Waveform Editor compares simulation runs and highlights the differences.
Graphic Editor for schematics or the Text Editor for AHDL
designs.
The integrated structure of MAX + PLUS provides features such as
automatic error location and delay prediction. If a design contains
an error in either a schematic or a text file, MAX + PLUS flags the
error and takes the user to the actual location of the error in the
original schematic or text file. In addition, propagation delays of
critical paths may be determined in both the Graphic and Text Editors with the delay predictor. Mter the source and destination
nodes are tagged, the shortest and longest timing delays are calculated.
MAX +PLUS provides a seamless design framework using a consistent graphical user interface throughout. This frameworksimplifies all stages of the design cycle: design entry, processing, verification, and programming. In addition, MAX + PLUS offers online
help to aid the user.
AHDL
Design Entry
MAX + PLUS offers both graphic and text design entry methods.
GDFsare entered with the MAX + PLUS Graphic Editor; Boolean
equations, state machines, and truth tables may be entered with the
MAX + PLUS Test Editor using AHDL. The ability to freely mix
graphics and text files at all levels of the design hierarchy and to use
either a top-down or bottom-up design method makes design entry
simple and versatile.
Graphic Editor
The Graphic Editor provides a mouse-driven, multi-windowed environment in which commands are entered with pop-up menus or
simple keystrokes. The Hierarchy Display window, shown at the
top, lists all schematics used in a design. The designer navigates the
hierarchy by placing the cursor on the name of the design to be
edited and clicking the left mouse button. The Total View window
(next to the Hierarchy window) shows the entire design. By clicking
on an area in this window, the user is moved to that area of the
schematic. The Error Report window lists all warnings and errors
inthe compiled design; selecting an error with the cursor highlights
the problem node and symbol. A design is edited in the main area,
which may be enlarged by closing the auxiliary windows.
When entering a design, the user may choose from a library of over
2007400 series and special-purpose macrofunctions that are all
optimized for MAX architecture. In addition, the designer my
create custom functions that can be used in any MAX + PLUS
design.
To take advantage ofthe hierarchy features, the userfirst saves the
entered design so the Graphic Editor can automatically create a
symbol representing the design. This symbol may be used in a higher-level schematic or in another design. It may also be modified
with the Symbol Editor.
Tag-and-drag editing is used to move individual symbols or entire
areas. Lines stay connected with orthogonal rubberbanding. A design may be printed on an Epson FX-compatible printer, or plotted
on an HP- or Houston Instruments-compatible plotter.
Symbol Editor
The MAX +PLUS Symbol Editor enables the designer to create or
modify a custom symbol representing a GDF or TDR It is also possible to modify input and output pin placement of an automatically
generated symbol.
The created symbol represents a lower-level design, described by a
GDF or TDR The lower-level design represented by the symbol
may be displayed with a single command that invokes either the
The Advanced Hardware Description Language (AHDL) is a
high-level, modular language used to create logic designs for MAX
EPLDs. It is completely integrated into MAX + PLUS, so AHDL
files may be created, edited, compiled, simulated, and programmed from within MAX + PLUS.
AHDL provides support for state machine, truth tables, and Boolean equations, as well as srithmetic and relational operations.
AHDLis hierarchical, which allows frequently used functions such
as TTL and bus macrofunctions to be incorporated in a design.
AHDL supports complex arithmetic and relational opeartions,
such as addition, subtraction, equality, and magnitude comparisons, with the logic functions automatically generated. Standard
Boolean functions, including AND, OR, NAND, NOR, XOR, and
SNOR are also included. Groups are fully supported so operations
may be performed on groups as well as on single variables. AHDL
also allows the designer to specify the location of nodes within
MAX EPLDs. Together, these features enable complex designs to
be implemented in a concise, high-level description.
Text Editor
The MAX +PLUS Text Editor enables the user to view and edit
text files within the MAX + PLUS environment. Any ASCII text
file, including Vector Files, Table Files, Report Files, and AHDL
Text Design Files (TDFs) may be viewed and edited wihtout having
to exit to DOS.
The Text Editor parallels the Graphic Editor's menu structure. It
has a Hierarchy Display and a Total View window for moving
through the hierarchy levels and around the design. It includes automatic error location and hierarchy traversal. If an error is found
in a TDF during compilation, the Text Editor is automatically invoked and the line ofAHDLcode where the error occurred is highlighted. In addition, a design may use both text and graphic files. As
the designer t4raverses the hierarchy, the Text Editor is invoked for
text files, and the Graphic Editor is invoked for schematics.
Symbol Libraries
The library provided with MAX + PLUS contains the most commonly used 7400 series devices such as counters, decoders, encoders' shift registers, flip-flops, latches, and multipliers, as well as special bus macrofunctions, all of which increase design productivity.
Because of the flexible architecture of MAX EPLDs (that includes
asynchronous preset and clear), true TIL device emulation is
achieved. Cypress also provides special-purpose bus macrofunctions for designs that use buses. All macrofunctions have been optimized to maximize speed and utilization. Refer to the
.MAX+PLUS TTL MacroFunctions manual for more information
on TIL macrofunctions.
Design Processing
The MAX +PLUS Compiler processes MAXdesigns. The Compil- ~
er offers options that speed the processing and analysis of a design.
The user can set the degree of detail of the Report File and the Imaximum number of errors generated, In addition, the user may
select whether or not to extract a netlist file for simulation.
The Compiler compiles a design in increments. If a design has been
previously processed, only the portion of the design that has been
changed is re-extracted, which decreases the compilation time.
This "Make" facility is an automatic feature of the Compile
command.
12-9
8
CY3200
The first module of the Compiler, the Compiler Netlist Extractor,
extracts the netlist that is used to define the design from each file.
At this time, design rules are checked for any errors. If errors ~e
found, the Graphic Editor is invoked when the error appears in a
GOp, and the Text Editor is invoked when the error appears in a
TOP. The Error Report window in both editors highlights the location of the error. A successfully extracted design is built into a database to be used by the Logic Synthesizer.
The Logic Synthesizer module translates and optimizes the userdefined logic for the MAX architecture. Any unused logic within
the design is automatically removed. The Logic Synthesizer uses
expert system synthesis rules to factor and map logic within the
multilevel MAX architecture. It then chooses the approach that
ensures the most efficient use of silicon resources.
The next module, the Fitter, uses heuristic rules to optimally place
the synthesized design into the chosen MAX EPLD. For MAX devices that have a Programmable Interconnect Array (PIA), the Fitter also routes the signals across this interconnect structure, so the
designer doesn't have to worry about placement and routing issues.
A Report File (.RPT) is issued by the Fitter, which shows design
implementation as well as any unused resources in the EPLD. The
designer can then determine how much additional logic may be
placed in the EPLD.
A Simulator Netlist File (.SNF) may be extracted from the compiled design by the Simulator Netlist Extractor if simulation is desired. Finally, the Assembler creates a Programmer Object File
(.POF) from the compiled design. This file is used with the
QP2 - MAX programming hardware to program the desired part.
Delay Prediction and Probes
MAX + PLUS includes powerful analysis tools to verify and analyze the completed design. Delay analysis with the delay predictor
may be performed interactively in the Graphic Editor, or in the
Simulator. The Simulator is interactive and event-driven, yielding
true timing and functional charactersitics ofthe compiled design.
The delay predictor provides instant feedback about the timing of
the processed design. After selecting the start point and end point
of a path, the designer may determine the shortest and longest
propagation delays of speed-critical paths.
Also, a designer may use probes to mark internal nodes in a design.
The designer may enter a probe by placing the cursor on any node
in a graphic design, selecting the SPE (Symbol:Probe:Enter) command, and then entering a unique name to define the probe. This
name may then be used in the Graphic Editor, Simulator, and
Waveform Editor to reference that node, so that lengthy hierarchical path names are avoided.
Simulator
Input stimuli can be defined with a straightforward vector input
language, or waveforms can be directly drawn using the Waveform
Editor. Outputs may also be viewed in the Waveform Editor, or
hardcopy table and waveform files may be printed.
The Sim,ulator used the Simulator Netlist File (SNF) extracted
from the compiled design to perform timing simulation with
1/1O-nanosecond resolution. A Command File may be used for
batch operation, or commands may be entered interactively. Simulator commands allow the user to halt the simulation dependent on
user-defined conditions, to force and group nodes, and perform
AC detection.
Ifflip-flop set-up or hold times have been violated, the Simulator
VJarns the user. In addition, the minimum pulse \vidth and period
of oscillation may be defined. If a pulse is shorter than the mini-
mum pulse width specified, or if a 'node oscillates for longer than
the specified time, the Simulator issues a warning.
Waveform Editor
The MAX + PLUS Waveform Editor provides a mouse-driven environment in which timing waveforms may be viewed and edited. It
functions as a logic analyzer, enabling the user to observe simulation results. Simulated wayeformsmay be viewed and manipulated
at multiple zoom levels. Nodes may be added, deleted, and combined into buses, which may contain up to 32 signals represented in
binary, octal, decimal, or hexadecimal format. Logical opeartors
may also be performed on pairs of waveforms, so that waveforms
may be inverted, ORed, ANDed, or XORed together.
The Waveform Editor includes sophisticated editing features to
define and modify input vectors. Input waveforms are created with
the mouse and familiar text editing commands. Waveforms may be
copied, patterns may be repeated, and blocks may be moved and
copied. For example, all or part of a waveform may be contracted
to simulate the increase in clock frequency.
The Waveform Editor also compares and highlights the difference
between two different simulations. A user may simulate a design,
observe and edit the results, and then resimulate the design, and
the Waveform Editor will show the results superimposed upon
each other to highlight the differences.
MAX + PLUS Timing Analyzer (MTA)
The MAX + PLUS Timing Analyzer (MTA) provides user-configurable reports that assist the designer in analyzing critical delay
paths, set-up and hold timing, and overall system performance of
any MAX EPLD design. Critical paths identified by these reports
may be desplayed and highlighted.
Timing delays between multiple source and destination nodes may
be calculated, thus creating a connection matrix giving the shortest
and longest delay paths between all source and destination nodes
specified. Or, the designer may specify that the detailed paths and
delays between specific sources and destinations be shown.
The set-up/hold option provides set-up and hold requirements at
the device pins for all pins that feed the D, CLK, or ENABLE inputs of flip-flops and latches. Critical source nodes may be specified individually, or set-up and hold at all pins may be calculated.
This information is then displayed in a table, one set of set-up and
hold times per flip-flop/latch.
The MTA also allows the user to print a complete list of all accessible nodes in a design; i.e., all nodes that may be displayed during
simulation or delay prediction.
All MTA options may be listed in an MTA command file. With this
file, the user may specify all information needed to configure the
output.
SNF2GDF Converter
SNF2GDF converts the SNF into logic schematics represented
with basic gates and flip-flop elements. It uses the SNF's delay and
connection iilfortnation and creates aseries of schematics fully annotated with propagation delay and set-up and hold information at
each logic gate. Certain speed paths of a design may be specified
for conversion, so the user may graphically analyze only the paths
considered critical.
If State Machine or Boolean Equation design entry is used,
SNF2GDF shows how the high-level description has been synthesized and placed into the MAX architecture.
12-10
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. ~i= CYPRESS
~~
CY3200
SBillCONDUCTOR
Recommended System Configuration
Device Programming
IBM PS/2 model 70 or higher, or Compaq 386 20-MHz
computer.
PLDS-MAX contains the basic hardware and software for programming the MAX EPLD family. Adapters are included for programming the CY7C344 (DIP and PLCC) and CY7C342 (PLCC)
devices. Additional adapters supporting other MAX devices may
be purchased separately. MAX + PLUS programming software
drives the QP2- MAX programming hardware. The designer can
use MAX + PLUS to program and verify MAX EPLDs. If the security bit of the device is not setto ON, the designer may also read the
contents of a MAX device and use this information to program additional devices.
PC-DOS version 3.3.
640 kbytes of RAM plus 1 MB of expanded memory with LIM
3.2-compatible EMS driver.
VGA graphics display.
20-MB hard disk drive.
System Requirements
1.2-MB 5V4" or 1.44-MB 3Vz" floppy disk drive.
Minimum System Configuration
IBM PS/2 model 50 or higher, PC/AT or compatible
computer.
3-button serial port mouse.
Ordering Information
CY3200
PC-DOS version 3.1 or higher.
640 kbytes RAM.
EGA, VGA or Hercules monochrome display.
PLDS-MAX+PLUS System including:
CY3201
MAX + PLUS software, manuals
and key.
CY3202
QP2- MAX PLD programmer with
CY3342 & CY3344 adapters.
20-MB hard disk drive.
1.2-MB 5V4" or 1.44-MB 3Vz" floppy disk drive.
Device Adapters
2-button serial port mouse.
Document #: 38-00132-A
CY3342
Adapter for CY7C342 in PLCC packages.
CY3344
Adapter for CY7C344 in DIP and PLCC
packages.
CY3342R
Adapter for CY7C342 in PGA packages.
CY33435
Adapter for CY7C343 in DIP
and PLCC packages.
CY3340
Adapter for CY7C341 in PLCC packages.
CY3340R
Adapter for CY7C341 in PGA packages.
CY3342F
Adapter for CY7C342 in flatpack (TMB)
packages.
~
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CY3210
PRELIMINARY
CYPRESS
SEMICONDUCTOR
PLS-EDIF
Bidirectional Netlist Interface
Features
Description
• Bidirectional netIist interface between
MAX +PLUS® and other major CAE
software packages
• Supports the industry-standard Electronic Design Interchange Format
(EDIF) version 200.
• MAX EPLD designs entered on workstation CAE tools can be downloaded to
MAX +PLUS for compilation; compile
designs can then be returned to the
workstation for device- or system-level
simulation.
• EDIF netIist reader imports EDIF netlists into MAX +PLUS. Library Mapping Files (LMFs) convert CAE library functions to MAX + PLUS library functions.
• LMFs allow conversion of common
Dazix, Mentor Graphics, Valid Logic,
and Viewlogic functions to
MAX +PLUS functions.
• EDIF netIist writer produces post-synthesis logic and delay information
used during device- or board-level
simulation with popular CAE tools.
• Runs on IBM PS/2®, PC-AT®, or
compatible machines.
The PLS-EDIF tool kit is a bidirectional
EDIF netlist interface between workstation-based CAE software packages and the
PLDS-MAX + PLUS Design System (Figure 1).
PLS-EDIF allows the designer to enter and
verify logic designs for MAX EPLDs using
third-party CAE tools. The EDIF 200 netlist exchange format is the two-way bridge
between MAX + PLUS and third-party
schematic capture and simulation tools.
PLS-EDIF runs on an IBM PS/2, PC- AT,
or compatible machines.
Any CAE software package that produces
EDIF 200 netlists can interface to
MAX +PLUS with PLS-EDIE EDIF netlists are imported into MAX + PLUS using
the EDIF Design File-to-Compiler Netlist
File (EDF2CNF) Converter. Library Mapping Files (LMFs) are used with
EDF2CNF to map third-party CAE library
functions to the MAX + PLUS libraryfunctions. LMFs are provided for Dazix, Mentor Graphics, Valid Logic, and Viewlogic
software, but designers may create LMFs
to map any CAE software library.
After a design is imported into
MAX +PLUS, it is compiled with the sophisticated MAX+PLUS Compiler, which
CAE Workstation/
PC Platform
uses advanced logic synthesis and minimization techniques together with heuristic
fitting rules to optimize the design for
MAX EPLD architecture. A Programmer
Object File created by the MAX + PLUS
Compiler is then used together with standard Cypress or third-party programming
hardware to program MAX devices.
EDIF netlists can be exported from
MAX +PLUS using the Simulator Netlist
File-to-EDIF Design File (SNF2EDF)
Converter. This converter generates an
EDIF output file from a compiled
MAX +PLUS design. The EDIF file contains the post-synthesis information used
by CAE simulators to perform device- or
board-level simulation.
PLS-EDIF provides an open environment
that allows popular CAE tools to be used
to create and simulate MAX EPLD designs. The designer may use a preferred
workstation schematic capture package to
enter logic designs, and then quickly convert and compile them with EDF2CNF
and MAX + PLUS. Likewise, designs compiled in MAX + PLUS and converted with
SNF2EDF may be transferred to a workstation for simulation. The PLS-EDIFnetlist reader and writer together allow MAX
EPLD designs to be entered and simulated
on any workstation platform.
•
•
Logic Entry
Device Simulation
PC Platform
•
Board Simulation
------------------------------,
---------------------...
I
•
•
Logic Entry
Logic Synthesis
•
•
Device Simulation
Programming
I
EDIF200
Exchange Format
....
_-------------------_.I
1
______
I
------------------------
Shaded items are provided with PLS - EDIF.
Figure 1. PLS- EDIF Workstation Interface
MAX + PLUS is a registered trademark of Altera Corporation.
IBM PS/2 and PC-AT are registered trademarks of International Business Machines Corporation.
12-12
3210·1
.....,....
~~
'lE CYPRESS
CY3210
- , SEMICONDUCTOR
EDF2CNF Converter
The EDF2CNF Converter generates one or more MAX +PLUS
Compiler Netlist Files (CNFs) from an EDIF file. For each CNF, a
Hierarchy Interconnect File (HIF) and a Graphic Design File
(GDF) are also generated (see Figure 2). The CNF contains the
connectivity data for a design file, while the HIF defines the hierarchical connections between design files. The GDF is a symbol that
represents the actual design data in the CNF. This symbol may be
entered in the MAX +PLUS Graphic Editor and integrated into a
logic schematic.
EDF2CNF can convert any EDIF 200 netlistwith the following parameters:
EDIFlevelO
keyword level 0
view type NETLIST
cell type GENERIC
Library Mapping Files (LMFs) are used withEDF2CNF to convert workstation CAE functions into equivalent MAX + PLUS
functions. This direct substitution is beneficial because
MAX +PLUS functions are optimized for both logic utilization
and performance in MAX EPLD designs.
Workstation
EDIFWriter
One or more sets
of eNF, HIF, and GDF
are generated.
One or more
Library Mapping Files
may be used as inputs.
3210-2
Figure 2. EDF2CNF Block Diagram
CJ)
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CY3210
SEMICONDUcrOR
Workstation Information
EDF2CNF has been specifically tested for use with the Dazix,
Mentor Graphics, Valid Logic, and ViewLogic CAE software
packages. In addition, LMFs for these products are provided with
the PLS - EDIF tool kit.
Dazix
To design logic and create an EDIF file with Dazix software, the
following applications are required:
ACE (Dazix graphics editor)
DANCE and DRINK (Dazix compiler)
ENW verison 1.0 (Dazix EDIF netlist writer)
Table 1 lists the Dazix basic functions that are mapped to
MAX + PLUS functions.
Mentor Graphics
To design logic and create an EDIF file using Mentor Graphics
software, the following applications are required:
NETED (Mentor Graphics graphics editor)
EXPAND (Mentor Graphics compiler)
EDIFNET version 7.0 (Mentor Graphics EDIF netlist writer)
Table 2 lists the Mentor Graphics basic functions that are mapped
to MAX + PLUS functions.
Table 1. Dazix Library Mapping File
MAX + PLUS Function
Dazix Function
Thble 2. Mentor Graphics Libary Mapping File
Mentor Graphics
Function
MAX +PLUS Function
AND#
AND#
BUF
SCLK
DELAY
MCELL
DFF2
R#AND
AND#
(# = 2, 3, 4, 5, 6, 7, 8, 9)
DFF
R#ANDD
BNOR#
(# = 2,3,4,5,6,7,8,9)
INV
NOT
JKFF2
(# = 2, 3, 4, 5, 6)
R#NAND
NAND#
(# = 2,3,4,6,7,8,9,13)
JKFF
R#NANDD
BOR#
(# = 2,3,4,5,7, 8, 9, 13)
LATCH
MLATCH
(# = 2, 3, 4, 5)
NAND#
NAND#
(# =2,3,4,5,6,9)
NOR#
NOR#
(# =2,3,4,6,8,16)
(# = 2, 3, 4, 6, 8)
R#NOR
NOR#
R#NORD
BAND#
(# = 2,3)
R#OR
OR#
(# = 2, 3, 4, 5)
OR#
OR2#
R#ORD
BNAND#
(# = 2, 3, 4, 5)
XNOR2
XNOR
RlBUF
MCELL
XOR2
XOR
RlINV
NOT
RlINVD
EXP
R10CBUF
SCLK
R10TBUF
TRIBUF
RlTINV
TRINOT
R2XNOR
XNOR
R2XOR
XOR
R3UAOI
1A2NOR2
R4AOI
2A2NO~2
R40AI
20R2NA2
R8AOI
4A2NOR4
R13TNAND
TNAND13
R13TNANDD
TBOR13
RDFLOP
DFF2
RDLATCH
RDLATCH
RJKFLOP
JKFF2
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CY3210
~"CYPRESS
-:::;", SEMICONDUcrOR
Valid Logic
ViewLogic
To design logic and create an EDIF file using Valid Logic software,
the following applications are required:
ValidGED (Valid Logic graphics editor)
ValidCompiler
GEDIFNET (Valid Logic EDIF netlist writer)
Table 3 lists the Valid Logic basic functions that are mapped to
MAX + PLUS functions.
To design logic and create an ED IF file using ViewLogic software,
the following applications are required:
Workview (ViewLogic graphics editor)
EDIFNET2 version 3.02 (Viewlogic EDIF netlist writer)
Table 4 lists the ViewLogic basic functions that are mapped to
MAX +PLUS functions.
Thble 3. Valid Logic Libary Mapping File
Valid Logic Function
Thble 4. ViewLogic Libary Mapping File
ViewLogic
Function
MAX +PLUS Function
MAX +PLUS Function
INV
EXP
AND#
AND #
LSOO
NAND2
ANDNOR22
2A2NOR2
LS02
NOR2
BUF
SOFT
LS04
NOT
DAND#
DAND#
MCELL
(# = 2, 3, 4, 8)
(# = 2, 3, 4, 8)
LS08
AND2
DELAY
LS10
NAND3
DOR#
DOR#
(# = 2, 3, 4, 8)
LSll
AND3
DXOR#
DXOR#
(# = 2, 3, 4, 8)
LS20
NAND4
JKFFRE
JKFFRE
LS21
AND4
MUX41
MUX41
NOR3
NAND#
NAND #
(# = 2, 3,4,8)
(#=2,3,4,8)
LS27
LS28
NOR2
NOR#
NOR#
LS30
NAND8
NOT
NOT
LS32
OR2
OR#
OR#
(# = 2, 3, 4, 8)
LS37
NAND2
TRIAND#
TAND#
(# = 2, 3, 4, 8)
LS40
NAND4
TRIBUF
TRIBUF
LS74
DFF2
TRINAND#
TNAND#
(# = 2, 3, 4, 8)
LS86
XOR
TRINOR#
TNOR#
(# = 2, 3, 4, 8)
LS126
TRI
TRINOT
TRINOT
LS280
DFF2
TRIOR#
TOR#
LS386
XOR
UBDEC38
DEC38
UDFDL
UDFDL
12-15
UJKFF
UJKFF
XNOR2
XNOR
XNOR#
XNOR#
XOR2
XOR
XOR#
XOR#
(# = 2, 3, 4, 8)
(#
= 3, 4, 8)
(# = 3, 4, 8)
I
~~
~=CYPRESS
CY3210
~, SEMICONDUcrOR
LMF Support for TTL Macrofunctions
In addition to the basic gates, LMFs map various Dazix, Mentor
Graphics, Valid Logic, and ViewLogic TIL macro functions to
their MAX+PLUS equivalents, as shown in Table 5.
Thble 5. TTL Function Mappings in LMFs
MAX +PLUS
7442
Dazix
Mentor Graphics
Valid Logic
ViewLogic
LS42
74LS42
LS42
74LS42·
DFF2
LS74
74LS74A
LS74
74LS74A
7483
LS83
74LS83A
LS83
74LS83A
7485
LS85
74LS85
LS85
74LS85
7491
LS91
74LS91
LS91
74LS91
7493
LS93
74LS93
LS93
74LS93
74138
LS138
74LS138
LS138
74LS138
74139
LS139
74LS139A
LS139
74LS139
74LS151
LS151
74LS151
74139M
74151
LS151
74153
74LS153
74LS153
74153M
LS153
74157
LS157
LS153
74LS157
74LS157
74157M
LS157
74160
LS160
74LS160A
LS160
74LS160A
74161
LS161
74LS161A
LS161
74LS161A
74162
LS162
74LS162A
LS162
74LS162A
74163
LS163
74LS163A
LS163
74LS163A
74164
LS164
74LS164
LS164
74LS164
74165
LS165
74LS165
LS165
74LS165
74174
LS174
74LS174
74174M
74LS174
LS174
74181
LS181
74LS181
LS181
74LS181
74190
LS190
74LS190
LS190
74LS190
74191
LS191
74LS191
LS191
74LS191
74194
LS194
74LS194A
LS194A
74LS194A
74273
LS273
74LS273
74174M
74279MD
74LS273
LS273
LS279
74279M
74LS279
LS279
74LS279
74280
LS280
74LS280
LS280
74LS280
74373
LS373
74LS373
74373M
74374
LS374
74LS374
74374M
74393M
74LS373
LS373
74LS374
LS374
LS393
74LS393
12-16
LS393
74LS393
. ::::: iapRFSS
CY3210
_ , SEMICONDUcrOR
Custom Library Mapping Files
Designers can map their commonly used workstation functions to
MAX + PLUS equivalents by modifying an LMF or creating a new
one. If no equivalent function currently exists in MAX +PLUS, the
user can create the function with the MAX +PLUS Graphic Editor
or Text Editor before mapping the function in an LMR Figure 3
shows an example of this process.
SNF2EDF Converter
The SNF2EDF Converter creates an industry-standard level 0
EDIF file from a MAX +PLUS Simulator Netlist File (SNF). The
SNF, which is optionally generated during compilation of a MAX
EPLD design, contains all post-synthesis functional and delay in-
formation for the completed design. This design-specific information is also contained in the EDIF output file after conversion so
that it may be integrated into a workstation environment for simulation. An optional command file enables the user to customize the
output EDIF file for various workstation environments by renaming certain constructs or by changing the EDIF level or keyword
level (see Figure 4).
The EDIF output file may have one of two formats. The first format expresses all delays with special EDIF property constructs.
The second expresses combinatorial delays with portdelay constructs and registered delays as pathdelay constructs-a format
that is especially useful for behavioral simulators. Both formats are
shown in Figure 5.
Step 1: Select a workstation function for mapping
ADS
A
B
z
C
Step 2: Design an equivalent circuit with the MAX + PLUS Graphic Editor
CYPRESS_AOS
,
INPUT
, AJN
'
r--------·
, AND2
,
Vee
.- - - - - - - - - - - - - - - - - • .---1--:-,--I
.~
I ________
,
INPUT
, BJN
'
._____________ ~e_e __ •
~
, CJN
I.
e .. INPUT
Vee
________________
AN02 - - - -:
.---~---o
: NOR2 - - - -:. - - - - - - - - - - - - - - - - -,
.Jr--:---;==~,==1
• ________ J
~
,
J
'_~~T~~~
• ________ l
Z~~~T___ ~
_e____
ANOi - - - -.
'
•
Step 2: Map the workstation function to the MAX +PLUS function in an LMF
I
LIBRARY new_lib
~
%User Library Mapping File%
o
ot-
BEGIN
FUNCTION MAX_AOS (A_IN, B_IN, C_IN)
RETURNS
(Z_OUT)
FUNCTION "AOS"
RETURNS
END
("A", "B",
"C")
("Z")
3210·3
Figure 3. Creating a Library Mapping File
12-17
C~PRFSS
~, ~kCONDUcrOR
CY3210
Workstation
EDIF Reader
3210-4
Figure 4. SNF2EDF Block Diagram
Format 1: Delays expressed with property constructs
Format 2: Delays expressed with portdelay and pathdelay constructs
(ins tance xor2 5
(viewRef viewl
(cellRef XOR2
(property TPD(integer 20) (unit TIME)))
(instance xor2_5
(v'iewRef viewl
(cellRef XOR2
(portInstance &1
(portDelay
(derivation CALCULATED
(delay(e 20 - 10)))))
Figure 5. EDIF File Formats
System Requirements
Package Contents
• IBM PC/AT or compatible computers; IBM PS/2 models 50,
60,70, or 80
• MS - DOS version 3.1 or later version
• 640 Kbytes of RAM
• 1 Mbyte of expanded memory compatible with version 3.2 or a
later version of the LotuslIntellMicrosoft Expanded Memory
Specification
• EGA, VGA, or Hercules Monochrome display
• 20-Mbyte hard disk drive
• 1.2-Mbyte 5W' or 1.44-Mbyte 3%" floppy disk drive
• MAX + PLUS version 2.01 or a later version
• Workstation-PC network hardware and software with the ability to transfer ASCII files
• Floppy diskettes containing all PLS- EDIF programs and files
for both PC/AT and PS/2 platforms
- EDF2CNF Converter
- SNF2EDF Converter
- Library Mapping Files for Dazix, Mentor Graphics, Valid
Logic, and Viewlogic
- MAX +PLUS macrofunctions for Dazix, Mentor Graphics,
Valid Logic, and ViewLogic libraries
- Example files
• Documentation
Document #: 38-00144
12-18
CY3220
CYPRESS
SEMICONDUCTOR
Features
• Unified development system for Multiple Array MatriX (MAX®) CY7C340
EPLDs plus compiler support for all
Altera Classic, Max 5000, Max 7000,
and STG EPLDs
• Microsoft Windows version 3.0 to provide graphical user interface,
multi-tasking abilities, efficient
memory management, and extensive
printer and plotter support
• Hierarchical design entry methods for
graphical, textual, and waveform designs
- Graphic Editor for schematic
designs
- Text Editor for Text Design Files
(TDFs) in the Advanced Hardware
Description Language (AHDL) will
support state machines, Boolean
equations, truth tables, arithmetic,
and relational operations
- Waveform Editor for waveform
entry to define logic and view
simulation results
• Logic synthesis and minimization for
quick and efficient processing
• Automatic error location for AHDL
text files and schematics
• Interactive Simulator with probe assignments for internal nodes
MAX+PLUS® II
Design System
• Multichip partitioning to divide large
designs into multiple EPLDs
• Library of 7400 series TTL and bus
macrofunctions optimized for MAX
architecture
• Bidirectional EDIF 2 0 0 netHst interface compatible with a variety of CAE
schematic capture and simulation
tools
• Runs on IBM PC/AT®, PS/2® or compatible machines
Description
The MAX +PLUS II programmable logic
development system is a unified CAE system for designing logic with Cypress's
CY7C340 family of EPLDs (Figure 1).
MAX +PLUS II includes design entry, design processing, timing simulation, and device programming support. MAX +PLUS
II runs on IBM PS/2, PC-AT, or compatible
machines, and provides tools to quickly
and efficiently create and verify complex
logic designs.
The MAX + PLUS II software compiles designs for MAX EPLDs in minutes. Designs may be entered with a variety of design entry mechanisms. MAX + PLUS II
supports hierarchical entry of Graphic Design Files (GDFs) with the MAX +PLUS
II Graphic Editor, Text Design Files
(TDFs) with the Advanced Hardware
Description Language (AHDL), and waveforms with the Waveform Editor. The
Graphic Editor offers advanced features
such as multiple hierarchy levels, symbol
editing, and a library of 7400 series devices
as well as basic SSI gates. AHDL designs
may be mixed into any level of the hierarchy or used on a standalone basis. AHDL
is tailored especially for EPLD designs and
includes support for complex Boolean and
arithmetic functions, relational comparisons, multiple hierarchy levels, state machines with automatic state variable assignment, truth tables, and function calls.
MAX +PLUS II includes a sophisticated
compiler that uses advanced logic synthesis and minimization techniques in conjunction with heuristic fitting rules to efficiently place designs within MAX EPLDs.
A programming file created by the compiler is then used by MAX + PLUS II to program MAX devices.
MAX +PLUS II features multichip partitioning that automatically splits large designs into multiple EPLDs, allowing the
user to create large system-level designs.
The partitioner lets the user specify speedcritical path for optimum EPLD selection
and design placement.
Simulations may be performed with a powerful, event-driven timing simulator. The
MAX +PLUS II Simulator interactively
CJ)
..J
o
o
....
MAX and MAX + PLUS II are registered trademarks of Altera Corporation.
IBM PC/AT and PS/2 are registered trademarks ofIntemational Business Machines Corporation.
QP2-MAX and QuickPro II are trademarks of Cypress Semiconductor Corporation.
12-19
f'~m
(/)QN
2
8
:;u
......
N
I
!:5
Figure 1. MAX + PLUS II Block Diagram
n
~
~
=
~
·
.~
~~CYPRESS
;F SEMICONDUcrOR
CY3220
displays timing results in the MAX +PLUS II·Waveform Editor.
Hardcopy table and waveform output is also available. With the
Waveform Editor, input vector waveforms may be entered, modified, grouped, and ungrouped, and simulation errors may be
viewed. In addition, the Waveform Editor compares simulation
runs and highlights the differences.
The integrated structure of MAX +PLUS II provides features such
as automatic error location and delay prediction. If a design contains an error in either a schematic or a text file, MAX +PLUS II
flags the error and takes the user to the actual location of the error
in the original schematic or text file. The designer uses the Clipboard to quickly copy design information from one editor to another. In addition, propagation delays of critical paths may be determined in both the Graphic and Text Editors with the delay
predictor. After the source and destination nodes are tagged, the
shortest and longest timing delays are calculated.
MAX +PLUS II provides a seamless design framework using a
consistent graphical user interface throughout. This framework
simplifies all stages of the design cycle: design entry, processing,
verification, and programming. In addition, MAX +PLUS II offers
extensive, context-sensitive online help to aid the user.
Design Entry
MAX +PLUS II supports three hierarchical design entry mechanisms: (1) the Graphic Editor is used to enter schematic designs;
(2) the Text Editoris used to enter Text Design Files (TDFs) in the
Advanced Hardware Description Language (AHDL); and (3) the
Waveform Editor is used to enter waveforms to define logic. These
design entry methods can be freely mixed within a single project,
allowing the designer to specify each logic block in the most appropriate format. In addition, EDIF 2 0 0 netlists with popular CAE
schematic tools such as ORCAD, Viewlogic, FutureNet, Mentor
Graphics or Valid Logic are easily imported into MAX + PLUS II.
Graphic Editor
The Graphic Editor provides a mouse-driven, multi-windowed environment in which commands are entered with pop-up menus or
simple keystrokes. The Hierarchy Displaywindow lists allschematics used in a design. The designer navigates the hierarchy by placing the cursor on the name of the design to be edited and clicking
the left mouse button. The Total View window shows the entire design. The Error Report window lists all warnings and errors in the
compiled design; selecting an error with the cursor highlights the
problem node and symbol. A design is edited in the main area,
which may be enlarged by closing the auxiliary windows.
When entering a design, the user may choose from a library of over
3007400 series and special-purpose macrofunctions that are all
optimized for MAX architecture. In addition, the designer may
create custom functions that can be used in any MAX+ PLUS II
design.
To take advantage of the hierarchy features, the user first saves the
entered design so the Graphic Editor can automatically create a
symbol representing the design. This symbol may be used in a higher-level schematic or in another design. It may also be modified
with the Symbol Editor.
The Graphics Editor offers many advanced schematic entry and
debugging features. For example, probes can be entered into the
schematic so a specific net (e.g., flip-flops, logic outputs) can be
easily viewed during simulation; critical paths can be specified in
the schematic; and objects can be quickly moved with tag-and-drag
editing. Lines stay connected with orthogonal rubberbanding. Designers can also group nodes into buses, quickly locate source and
destination of nets, and use the search-and-replace to make
changes to the net name. A design may be printed on an Epson FXcompatible printer, or plotted on anHP- or Houston Instrumentscompatible plotter.
Symbol Editor
The MAX + PLUS II Symbol Editor enables the designer to create
or modify a custom symbol representing a GDF or TDF. It is also
possible to modify input and output pin placement of an automatically generated symbol.
The created symbol represents a lower-level design, described by a
GDF or TDF. The lower-level design represented by the symbol
may be displayed with a single command that invokes either the
Graphic Editor for schematics or the Text Editor for AHDL
designs.
AHDL
The Advanced Hardware Description Language (AHDL) is a
high-level, modular language used to create logic designs for MAX
EPLDs. It is completely integrated into MAX +PLUS II, so
AHDL files may be created, edited, compiled, simulated, and programmed from within MAX +PLUS II.
AHDL provides support for state machine, truth tables, and Boolean equations, as well as arithmetic and relational operations.
AHDLis hierarchical, which allows frequently used functions such
as TTL and bus macrofunctions to be incorporated in a design.
AHDL supports complex arithmetic and relational operations,
such as addition, subtraction, equality, and magnitude comparisons, with the logic functions automatically generated. Standard
Boolean functions, including AND, OR, NAND, NOR, XOR, and
XNOR are also included. Groups are fully supported so operations
may be performed on groups as well as on single variables. AHDL
also allows the designer to specify the location of nodes within
MAX EPLDs. Together, these features enable complex designs to
be implemented in a concise, high-level description.
Text Editor
The MAX + PLUS II Text Editor enables the user to view and edit
text files within the MAX +PLUS II environment. Any ASCII text
file, including Vector Files, Table Files, Report Files, and AHDL
Text Design Files (TDFs) may be viewed and edited without having
to exit to DOS.
The Text Editor parallels the Graphic Editor's menu structure. It
has a Hierarchy Display and a Total View window for moving
through the hierarchy levels and around the design. It includes automatic error location, hierarchy traversal, global search-and-replace, and multiple fonts. If an erroris found in a TDF during compilation, the Text Editor is automatically invoked and the line of
AHDLcode where the error occurred is highlighted. In addition, a
design may use both text and graphic files. As the designer traverses the hierarchy, the Text Editor is invoked for text files, and U)
the Graphic Editor is invoked for schematics.
..J
Waveform Editor
The MAX +PLUS II Waveform Editor provides a mouse-driven
environment in which waveform algorithms automatically generate logic from user-defined input and output waveforms. It also
functions as a logic analyzer, enabling the user to observe simulation results.
Simulated waveforms may be viewed and manipulated at multiple
zoom levels. Nodes may be added, deleted, and combined into
12-21
o
~
CY3220
buses, which may contain up to 32 signals represented in binary, octal, decimal, or hexadecimal format. Logical operators may also be
performed on pairs of waveforms, so that waveforms may be inverted, ORed, ANDed, or XORed together.
The Waveform Editor includes sophisticated editing features to
define and modify input vectors. Input waveforms are created with
the mouse and familiar text editing commands. Waveforms may be
copied, patterns may be repeated, and blocks may be moved and
copied. For example, all or part of a waveform may be contracted
to simulate the increase in clock frequency.
The Waveform Editor also compares and highlights the difference
between two different simulations. A user may simulate a design,
observe and edit the results, and then resimulate the design, and
the Waveform Editor will show the results superimposed upon
each other to highlight the differences.
Symbol Libraries
The library provided with MAX + PLUS II contains the most commonly used 7400 series devices such as counters, decoders, encoders, shift registers, flip-flops, latches, and multipliers, as well as special bus macrofunctions, all of which increase design productivity.
Because of the flexible architecture of MAX EPLDs (that includes
asynchronous preset and clear), true TIL device emulation is
achieved. Cypress also provides special-purpose bus macrofunctions for designs that use buses. All macro functions have been optimized to maximize speed and utilization.
EDIF Support
MAX +PLUS II software supports bidirectional EDIF 2 0 0 netlists, providing a convenient way to import popular CAE schematic
capture and simulation tools. The Library Mapping Files (LMFs)
of MAX +PLUS II converts EDIF 2 0 0 netlists into equivalent
primatives and macrofunctions. Users can create their own LMFs
to map any CAE software library. MAX + PLUS II then automatically generates a symbol from a translated EDIF file, so that the
file can be directly incorporated into a MAX +PLUS II schematic
or AHDL design. EDIF netlists can also be exported to the popularsimulation tool of the user's choice. The netlist contains all postsynthesis function and delay information for the completed design.
Design Processing
The MAX + PLUS II Compiler processes MAX designs. The Compiler offers options that speed the processing and analysis of a design. The user can set the degree of detail of the Report File and
the maximum number of errors generated. In addition, the user
may specify for which MAX EPLD the compiler should target the
design and select whether or not to extract a netlist file for simulation.
The Compiler compiles a design in increments. If a design has been
previously processed, only the portion of the design that has been
changed is re-extracted, which decreases the compilation time.
This "Make" facility is an automatic feature of the Compile
command.
The first module ofthe Compiler, the Compiler Netlist Extractor,
extracts the netlist that is used to define the design from each file.
At this time, design rules are checked for any errors. If errors are
found, the Graphic Editor is invoked when the error appears in a
GDF, and the Text Editor is invoked when the error appears in a
TDF. The Error Report window in both editors highlights the location of the error. A successfully extracted design is built into a database to be used by the Logic Synthesizer.
The Logic Synthesizer module translates and optimizes the userdefined logic for the MAX architecture. Any unused logic within
the design is automatically removed. The Logic Synthesizer uses
expert system synthesis rules to factor and map logic within the
multilevel MAX architecture. It then chooses the approach that
ensures the most efficient use of silicon resources.
The next module, the Fitter, uses heuristic rules to optimally place
the synthesized design into the chosen MAX EPLD. For MAX devices that have a Programmable Interconnect Array (PIA), the Fitter also routes the signals across this interconnect structure, so the
designer doesn't have to worry about placement and routing issues.
A Report File (.RPT) is issued by the Fitter, which shows design
implementation as well as any unused resources in the EPLD. The
designer can then determine how much additional logic may be
placed in the EPLD.
For large system-level designs, the logic design is broken up into
multiple EPLDs ofthe same family. The designer does not have to
manually split a large design into many smaller designs. The user
can control the design's partitioning at the source level by specifying chip assignments to flip-flops and pins.
A Simulator Netlist File (.SNF) may be extracted from the compiled design by the Simulator Netlist Extractor if simulation is desired. Finally, the Assembler creates a Programmer Object File
(.POF) from the compiled design. This file is used with the
QP2- MAX programming hardware to program the desired
CY7C340 family member.
Delay Prediction and Probes
MAX +PLUS II includes powerful analysis tools to verify and analyze the completed design. Delay analysis with the delay predictor
may be performed interactively in the Graphic Editor, or in the
Simulator. The Simulator is interactive and event-driven, yielding
true timing and functional characteristics of the compiled design.
The delay predictor provides instant feedback about the timing of
the processed design. After selecting the start point and end point
of a path, the designer may determine the shortest and longest
propagation delays of speed-critical paths.
Also, a designer may use probes to mark internal nodes in a design.
The designer may enter a probe by placing the cursor on any node
in a graphic design, selecting the SPE (Symbol: Probe: Enter ) command, and then entering a unique name to define the probe. This
name may then be used in the Graphic Editor, Simulator, and
Waveform Editor to reference that node, so that lengthy hierarchical path names are avoided.
Simulator
The MAX + PLUS II Simulator uses the virtual memory of Windows 3.0 to run simulations of large, multichip EPLDs.
Input stimuli can be defined with a straightforward vector input
language, or waveforms can be directly drawn using the Waveform
Editor. Outputs may also be viewed in the Waveform Editor, or
hardcopy table and waveform files may be printed.
The Simulator uses the Simulator Netlist File (SNF) extracted
from the compiled design to perform timing simulation with
1I10-nanosecond resolution. A Command File may be used for
batch operation, or commands may be entered interactively. Simulator commands allow the user to halt the simulation dependent on
user-defined conditions, to force and group nodes, and perform
AC detection.
If flip-flop set-up or hold times have been violated, the Simulator
warns the user. In addition, the minimum pulse width and period
of oscillation may be defined. If a pulse is shorter than the minimum pulse width specified, or if a node osciHates for longer than
the specified time, the Simulator issues a warning.
12-22
==- =
~
~
CY3220
5:IE!!!E CYPRESS
~, SEMICONDUCTOR
MAX + PLUS II Timing Analyzer (MTA)
System Requirements
The MAX +PLUS II Timing Analyzer (MTA) provides user-configurable reports that assist the designer in analyzing critical delay
paths, set-up and hold timing, and overall system performance of
any MAX EPLDdesign. Critical paths identified by these reports
may be displayed and highlighted.
Timing delays between multiple source and destination nodes may
be calculated, thus creating a connection matrix giving the shortest
and longest delay paths between all source and destination nodes
specified. Or, the designer may specify that the detailed paths and
delays between specific sources and destinations be shown.
The set-up/hold option provides set-up and hold requirements at
the device pins for all pins that feed the D, CLK, or ENABLE inputs of flip-flops and latches. Critical source nodes may be specified individually, or set-up and hold at all pins may be calculated.
This information is then displayed in a table, one set of set-up and
hold times per flip-flop/latch.
The MTA also allows the user to print a complete list of all accessible nodes in a design; i.e., all nodes that may be displayed during
simulation or delay prediction.
All MTA options may be listed in an MTA command file. With this
file, the user may specify all information needed to configure the
output.
Minimum System Configuration
IBM PS/2 model 70 or higher, PC/AT or compatible
80386-based computer.
PC-DOS version 3.1 or higher.
4 Mbytes RAM.
Microsoft Windows version 3.0.
Microsoft Windows-compatible graphics card and monitor.
EGA, VGA or Hercules monochrome display.
20-MB hard disk drive.
1.2-MB 5Y4" or 1.44-MB 3Vz" floppy disk drive.
2-button serial port mouse compatible with Microsoft
Windows 3.0.
Parallel port.
Recommended System Configuration
IBM PS/2 model 70 or higher, or compatible 386-based computer.
PC-DOS version 3.3 or higher.
SNF2GDF Converter
4 Mbytes of RAM plus 10 Mbytes of expanded memory with
LIM 3.2-compatible EMS driver.
SNF2GDF converts the SNF into logic schematics represented
with basic gates and flip-flop elements. It uses the SNF's delay and
connection information and creates a series of schematics fully annotated with propagation delay and set-up and hold information at
each logic gate. Certain speed paths of a design may be specified
for conversion, so the user may graphically analyze only the paths
considered critical.
If State Machine or Boolean Equation design entry is used,
SNF2GDF shows how the high-level description has been synthesized and placed into the MAX architecture.
Microsoft Windows version 3.0.
VGA graphics display.
20-MB hard disk drive.
1.2-MB 5%" or 1.44-MB 31fz" floppy disk drive.
3-button serial port mouse compatible with Microsoft
Windows 3.0.
Parallel port.
Ordering Information
Device Programming
PLDS-MAX contains the basic hardware and software for programming the CY7C340 MAX EPLD family. Adapters are included for programming the CY7C344 (DIP and PLCC) and
CY7C342 (PLCC) devices. Additional adapters supporting other
MAX devices may be purchased separately. MAX +PLUS II programming software drives the QP2- MAX programming hardware. The designer can use MAX +PLUS II to program and verify
CY7C340 MAX EPLDs. If the security bit of the device is not set
to ON, the designer may also read the contents of a MAX device
and use this information to program additional devices.
CY3220
MAX +PLUS II System including:
CY3221
MAX +PLUS II software, manuals
and key.
CY3202
QP2-MAX PLD programmer with
CY3342 & CY3344 adapters.
Device Adapters
CY3340
Adapter for CY7C341 in PLCC packages.
CY3340R Adapter for CY7C341 in PGA packages.
CY3342
Adapter for CY7C342 in PLCC packages.
CY3342R Adapter for CY7C342 in PGA packages.
~
CY3342F Adapter for CY7C342 in Flatpack (TMB) packages.
0
CY3344
AdapterforCY7C344inDIPandPLCCpackages.
CY33435 Adapterfor CY7C343 in DIP and PLCC packages.
Document #: 38-00187
12-23
I
~
CY3300
QuickPro II@)
Features
•
•
•
•
•
•
•
•
•
•
Combined PROM, PLD, and EPROM Programmer
Programs all Cypress CMOS & ECL PLDs and PROMs
Easy-to-use, menu-driven software
New device and feature updates via floppy disk and adapters
Plugs into standard IBM PC@) parallel port-no need to use
up a bus slot
Compatible with IBM PC/AT@), PS/2@), and compatible computers
Programs 20-, 24-, 28-, 32-, 40-, 44-, and 68-pin Cypress
PLDs and PROMs via device adapters
Modular design with adapter bus for future device support
and future feature enhancements
Comprehensive self-test and automatic calibration software
Supports Vmargin verification for a higher degree of device
reliability
6". The parallel port cable and AC power adapter cable are both
approximately 6' in length.
Power
AC Power Adapter:
Device Adapters
17 VAC@500rnA
Device adapters are external modules with various pin and socket
configurations. Each adapter plugs into the QuickPro II bus connector and maps the pins of particular devices and packages to the
pin electronics resources available at the connector. Each adapter
has at least one LED that indicates when power is being applied to
the socket. In addition to these device adapters, package adapters
are also used to accommodate the various package options available for PLDs and PROMs.
Memory
640K of total memory is necessary to operate the QuickPro II software.
Devices Supported
Description
QuickPro II is Cypress's second-generation QuickPro PLD and
PROM device programmer. It incorporates new architectural features that enable it to handle all current and future devices through
a 96-pin universal bus connector. The QuickPro II hardware can be
installed on any IBM PC/AT- or PS/2-compatible computer by simply plugging into a standard parallel port. The software communicates with the QuickPro II electronics via this parallel port and utilizes intelligent programming algorithms to minimize device
programming time.
The QuickPro II architecture and feature set were dictated by the
needs of Cypress's new-generation PLDs and PROMs. Many of
these devices offer very high performance and complexity with
large numbers of pins. To meet these needs, the QuickPro II utilizes flexible pin electronics, a universal adapter bus and a carefully
engineered system design that minimizes electrical noise. Pin electronics are located as close as possible to the device being programmed. In addition to the V pp and Vee voltage sources needed
to program parts, the QuickPro II incorporates a Vmargin voltage
source for measuring the relative programming margins to which a
device has been programmed and a Vrefvoltage source for doing
self-testing and calibration.
For PLDs, QuickPro II uses the JEDEC standard data format, so
present and future design tools such as PLD ToolKit~ ABEL@),
CUPL@), and PALASM@) can be used. QuickPro II reads Intellec
86~ Motorola S, TEK and space format files. It also reads and
writes PROM PC DOS binary files for use with assemblers and
compilers. QuickPro II is alow-cost,full-featureprogramminglverification system with a flexible and extendible architecture. The
user interface software is menu -driven with complete on-screen explanations.
QuickPro II hardware and software supports the programming and
verification of all Cypress and Aspen PLDs and PROMs.
Ordering Information
CY3300
QuickPro II system including:
CY3301
QuickPro II base unit
CY3302
QuickPro II parallel port cable
CY3303
QuickPro II AC power adapter
CY3304
QuickPro II software (disk & manual)
CY3202
QP2-MAX version of QuickPro II for
PLDS-MAX + PLUS design tool that consists of
the CY3300 system and the CY3342 and CY3344
adapters.
International versions (220V) ofthe CY3300 and the CY3202 are
also available.
Device Adapters
Technical Information
Size
The QuickPro II base unit is approximately 10 1/2" x 81/2" xl".
Individual device family adapters vary in size from 5" x 3" to 6" x
12-24
CY3320
Adapterfor all Cypress 20-, 24-, 28-, and 32-pin
devices excluding the MAX parts. Contains
20-, 24, and 28- pin DIP sockets (package
adapters required for 32-pin devices).
CY3342
Adapter for the CY7C342-PLCC
CY3342R
Adapter for the CY7C342-PGA
CY3342F
Adapter for the CY7C342-Flatpack
CY3340
Adapter for the CY7C341-PLCC
CY3340R
Adapter for the CY7C341-PGA
CY3344
Adapter for the CY7C344-PLCC & DIP
CY33435
Adapter for the CY7C343-PLCC & DIP
=¥-:~PRFSS
CY33 00
~.iF SEMICONDUCTOR
Package Adapters
Package adapters are used with the CY3320 generic device programming adapter on the OuickPro II in order to accommodate
Cypress's wide variety of device packaging options. The package
adapters used with devices having 28 native pins on the OuickPro
II are the same as those used on the original OuickPro~ The number of native pins that a device has refers to the number of actual
signal, power and ground pins used-excluding any N/C (No Connects) in a particular package. All devices are programmed in the
Devices with 20 native pins
CY3320 adapter's DIP socket having the same number of pins as
the native pins on the device. Therefore, a 22VlO is programmed in
the 24-pin DIP socket, regardless of whether it is in a DIP package
or a PLCC package, even though the PLCC package has 28 pins (4
are N/Cs). A package adapter between the 28-pin PLCC and the
24-pin DIP sockets is used to accomplish this. The following list
summarizes the package adapters used with the CY3320 adapter
on the OuickPro II.
CY3005
20-pin LCC - Package codes L61 and 061 - All devices
CY3007
20-pin PLCC - Package code J61 - All devices
CY3031
20-pin SOJ - Package code V5 - All devices
CY3021
20-pin Cerpack - Package code K71
Devices with 24 native pins
CY3004A
28-pin LCC (22V10, CG7C323, CG7C324)
CY3004B
28-pin LCC (7C225, 7C235, 7C245, 7C26113/4, 7C281/2, 7C29112, 7C245, 7C291N2N3A)
CY3010
28-pin LCC (20G 10, 20RAlO)
CY3006A
28-pin PLCC and HLCC (22VlO, CG7C323, CG7C324)
CY3006B
28-pin PLCC and HLCC (7C225, 7C235, 7C245, 7C261/3/4, 7C281/2, 7C291/2, 7C245, 7C291N2N3A)
CY3011
28-pin PLCC and HLCC (20G 10, 20RAlO)
CY3019
24-pin Cerpack - Package codes K73, T73 - All devices
CY3030
24-pin SOIC - Package code S13 - All devices
Devices with 28 native pins
CY3008
28-pin LCC - Package codes L64 and 064 - All devices
CY3009
28-pin PLCC and HLCC - Package codes J64 and H64 - All devices
CY3014
28-pin SOIC - Package code S21 - All devices
CY3022
28-pin SOJ - Package code V21 - All devices
CY3020
28-pin Cerpack - Package codes K74, T74 - All devices
CY3017
32-pin rectangular LCC (7C251/4)
CY3024
32-pin rectangular LCC (7C266, 7C271/4, 7C277, 7C279, 7C286)
CY3026
32-pin DIP (7C289)
CY3027
32-pin rectangular LCC (7C285, 7C287)
CY3029
32-pin rectangular LCC (7C289)
Document #: 38-00129-B
QuickPro, QuickPro II, and PLD ToolKit are trademarks of Cypress Semiconductor Corporation.
IBM PC, PC/AT, and PS/2 are registered trademarks of International Business Machines Corporation.
ABEL is a registered trademark of Data I/O Corporation.
CUPL is a registered trademark of Assisted Technology.
PALASM is a registered trademark of Monolithic Memories Inc.
Intellec 86 is a trademark of Intel Corporation.
12-25
I
INFO
SRAMs
PROMs
PlDs
FIFOs
lOGIC
I
I
I
I
I
I
DATACOM
BUS
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MiliTARY
II
TOOLS
QUALITY
II
II
PACKAGES
II
MODULES
ECl
S;~PRFSS
~_,.i SEMICONDUcrOR
Quality and Reliability
Section Contents
Page Number
Quality, Reliability, and Process Flows ...................................................................... 13-1
Jape and Reel Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-16
Quality, Reliability, and Process Flows
Corporate Views on Quality and Reliability
Cypress believes in product excellence. Excellence can only be defined by how the users perceive both our product quality and reliability. If you, the user, are not satisfied with every device that is
shipped, then product excellence has not been achieved.
Product excellence does not occur by following the industry
norms. It begins by being better than one's competitors, with better designs, processes, controls and materials. Therefore, product
quality and reliability are built into every Cypress product from
the start.
Some of the techniques used to insure product excellence are the
following:
• Product Reliability is built into every product design, starting
from the initial design conception.
• Product Quality is built into every step of the manufacturing
process through stringent inspections of incoming materials
and conformance checks after critical process steps.
• Stringent inspections and reliability conformance checks are
done on finished product to insure the finished product quality requirements are met.
• Field data test results are encouraged and tracked so that
accelerated testing can be correlated to actual use experiences.
Product Assurance Documents
Cypress Semiconductor uses MIL-STD-883D and MIL-M38510J as baseline documents to determine our Test Methods,
Procedures and General Specifications for semiconductors.
Customers using our commercial and industrial grade product receive the benefit of a military patterned process flow at no additional charge.
Product Testing Categories
Five different testing categories are offered by Cypress:
1. Commercial operating range product: O°C to +70°C.
2. Industrial operating range product: - 40°C to +85°C.
3. Military Gradeproductprocessed to MIL-STD-883D; Military
operating range: - 55°C to +125°C.
4. SMD (Standardized Military Drawing) approved product: Militaryoperatingrange: - 55°Cto + 125°C,electricallytestedper
the applicable Military Drawing.
5. JAN qualified product; Military operating range: - 55°C to
+ 125 ° C, electrically tested per MIL-M -3851 OJ slash sheet requirements.
Categories 1, 2, and 3 are available on all products offered by Cypress Semiconductor. Categories 4 and 5 are offered on a more
limited basis, dependent upon the specific part type in question.
Commercial Product Assurance Categories
Commercial grade devices are offered with two different classes of
product assurance. Every device shipped, as a minimum, meets
the processing and screening requirements of level l.
Levell:
For commercial or industrial systems where the demand for quality and reliability is high, but where field
service and device replacement can be reasonably accomplished.
Level 2:
For enhanced reliability applications and commercial
or industrial systems where maintenance is difficult
and/or expensive and reliability is paramount.
Devices are upgraded from Levell to Level 2 by additional testing and a burn-in of 12 hours at 150°C.
Tables 1 and 2 list the 100% screening and quality conformance
testing performed by Cypress Semiconductor in order to meet requirements of these programs.
Military Product Assurance Categories
Cypress's Military Grade components and SMD products are processed per MIL-STD-883D using methods 5004 and 5005 to define our screening and quality conformance procedures. The processing performed by Cypress results in a product that meets the
class B screening requirements as called out by these methods. Every device shipped, as a minimum, meets these requirements.
JAN, SMD, and Military Grade devices supplied by Cypress are
processed for applications where maintenance is difficult or expensive and reliability is paramount. Tables 3 through 7 list the
screening and quality conformance testing that is performed in order to meet the processing requirements required by MILSTD-883D and MIL-M-3851OJ.
13-1
II
~~
" CYPRESS
•
,
Quality, Reliability, and Process Flows
SEMICONDUCTOR
Table 1. Cypress Commercial and Industrial Product Screening Flows-Components
Product Temperature Ranges
Commercial O°C to +70°C; Industrial -40°C to +85°C
Level 2
Levell
Plastic
Hermetic
Plastic
Hermetic
O.4%AQL
100%
O.4%AQL
100%
LTPD = 5
100%
Does Not Apply
Does Not Apply
LTPD = 5
100%
100%
100%[1]
100%
100%[1]
100%
5% (max)[2]
100%
5% (max)[2]
MIL-STD-883D Method
Screen
Visual/Mechanical
• Internal Visual
2010
• Hermeticity
- Fine Leak
- Gross Leak
1014, CondAorB (sample) Does Not Apply
Does Not Apply
1014, Cond C
Burn-in
• Pre-Bum-in Electrical
• Burn-in
Per Device Specification
Does Not Apply Does Not Apply
Per Cypress Specification
Does Not Apply Does Not Apply
• Post-Burn-in Electrical
Per Device Specification
Does Not Apply Does Not Apply
Does Not Apply Does Not Apply
• Percent Defective
Allowable (PDA)
Final Electrical
Per Device Specification
Not Performed
Not Performed
100%[1]
100%[1]
Supplies Extremes
2. At Hot Temperature and
Power Supply Extremes
100%
100%
100%
100%
• External Visual
2009
Note 3
Note 3
Note 3
Note 3
• Final Electrical
Conformance
Cypress Method 17-00064
Note 3
Note 3
Note 3
Note 3
• Static (DC), Functional,
and Switching (AC) Tests
1. At 25 ° C and Power
Cypress Quality
Lot Acceptance
Table 2. Cypress Commercial and Industrial Product Screening Flows.....,..Modules
Product Temperature Ranges
Commercial O°C to +70°C; Industrial -40°C to +85°C
Screen
MIL-STD-883D Method
Levell
Level 2
100%
Burn-iu
• Pre-Bum-in Electrical
• Burn-in
Per Device Specification
Does Not Apply
1015
Does Not Apply
100%
• Post-Burn-in Electrical
Per Device Specification
Does Not Apply
100%
Does Not Apply
15%
Not Performed
100%
100%
100%
Per Cypress Module Specification
Per Cypress Module Specification
Note 3
Note 3
• Percent Defective
Allowable (PDA)
Final Electrical
• Static (DC), Functional,
and Switching (AC) Tests
Per Device Specification
1. At 25 ° C and Power
Supply Extremes
2. At Hot Temperature and
Power Supply Extremes
Cypress Quality
Lot Acceptance
• External Visual
• Final Electrical
Conformance
Notes:
2009
Cypress Method 17-00064
1. Burn-in is performed as a standard for 12 hours at 150°C.
2. Electrical Test is performed after burn-in. Results of this are used
to determine PDA percentage.
3.
13-2
Lot acceptance testing is performed on every lot to guarantee
200 PPM average outgoing quality.
Quality, Reliability, and Process Flows
Table 3. Cypress JAN/SMD/Military Grade Product Screening Flows for Class B
Screen
Product Temperature Ranges - 55 ° C to
Screening Per
Method 5004 of
MIL-STD-883D
JAN
SMD/Military
Grade Product
+ 125 ° C
Military Grade
Module
VisuaIlMechanical
• Internal Visual
Method 2010, Cond B
100%
100%
N/A
• Temperature Cycling
Method 1010, Cond C, (10 cycles)
100%
100%
Optional
• Constant Acceleration
Method 2001, Cond E (Min.),
Y1 Orientation Only
100%
100%
N/A
Method 1014, Cond A or B
Method 1014, Cond C
100%
100%
100%
100%
N/A
N/A
• Pre-Bum-in Electrical
Parameters
Per Applicable Device
Specification
100%
100%
100%
• Burn-in Test
Method 1015, Cond D,
160 Hrs at 125°C Min. or
80 Hrs at 150°C
100%
100%
100%
(48 Hours at 125°C)
• Post-Bum-in Electrical
Parameters
Per Applicable Device
Specification
100%
100%
100%
• Percent Defective
Allowable (PDA)
Maximum PDA, for All Lots
5%
5%
10%
• Hermeticity:
-Fine Leak
-Gross Leak
Bum-in
Final Electrical Tests
• Static Tests
Method 5005
Subgroups 1, 2, and 3
100% Test to
Slash Sheet
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Functional Tests
Method 5005
Subgroups 7, 8A, and 8B
100% Test to
Slash Sheet
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
• Switching
Method 5005
Subgroups 9, 10, and 11
100% Test to
Slash Sheet
100% Test to
Applicable Device
Specification
100% Test to
Applicable
Specification
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
Sample
100%
100%
100%
Quality Conformance Tests
• GroupA[4]
• Group B
• Group C[5]
Method 5005, see
Tables 4 - 7 for details
• Group D[5]
External Visual
Method 2009
Notes:
4.
Group A subgroups tested for SMD/Military Grade products are 1, 2,
3,7, 8A, 8B, 9, 10, 11, or per JAN Slash Sheet.
5.
Group C and D end-point electrical tests for SMD/Military Grade
products are performed to Group A subgroups 1,2,3,7, 8A, 8B, 9, 10,
11, or per JAN Slash Sheet.
II
13-3
I=;~PRRSS
~.;.
Quality, Reliability, and Process Flows
SEMICONDUCTOR
Table 4. Group A Test Descriptions
Sub·
group
1
2
Description
Static Tests at 25°C
package type and lead finish built within a sixweek seal period and
submitted to Group B testing at the same time.
Sample Size/Accept No.
Modules [6)
116/0
116/0
Static Tests at
Maximum Rated
Operating Temperature
116/0
3
Static Tests at
Minimum Rated
Operating Temperature
116/0
116/0
4
Dynamic Thsts at 25°C
116/0
116/0
5
Dynamic Tests at
Maximum Rated
Operating Temperature
116/0
116/0
6
Dynamic Thsts at
Minimum Rated
Operating Temperature
116/0
116/0
Sub·
group
116/0
1
7
Functional Tests at 25 ° C
116/0
116/0
8A
Functional Tests at
Maximum Temperature
116/0
116/0
8B
Functional Tests at
Minimum Temperature
116/0
116/0
9
Switching Tests at 25°C
116/0
116/0
10
Switching Tests at
Maximum Temperature
116/0
116/0
Switching Tests at
Minimum Temperature
116/0
11
Table 6. Group C Quality Tests
Components
Sub·
group
116/0
Quantity/Accept #
orLTPD
Components Modules [6)
2
Resistance to Solvents,
Method 2015
3/0
3/0
3
Solderability,
Method 2003
10
10
5
Bond Strength,
Method 2011
15
NA
Group B testing is performed for each inspection lot. An inspection lot is defined as a group of material of the same device type,
Note:
6.
5
15/0
Table 7. Group D Quality Tests (Package Related)
Military Gt:atieModules are processed to proposed JEDEC standard
flows-f6r MIL-STD-883D compliant modules.
13-4
Description
Quantity/Accept #
orLTPD
Components Modules [6]
1
Physical Dimensions,
Method 2016
15
15/0
2
Lead Integrity, Seal:
Fine and Gross Leak,
Method 2004 and 1014
5
15/0
3
Thermal Shock, Temp
Cycling, Moisture
Resistance, Seal: Fine
and Gross Leak, Visual
Examination, EndPoint, Electricals,
Methods 1011, 1010,
1004 and 1014
15
15/0
4
Mechanical Shock,
Vibration - Variable
Frequency, Constant
Acceleration, Seal:
Fine and Gross Leak,
Visual Examination,
End-Point Electricals,
Methods 2002, 2007,
2001 and 1014
15
15/0
Table 5. Group B Quality Tests
Description
Steady State Life Test,
End-Point Electricals, .
Method 1005, Cond D
Components Modules [6)
Group C tests for JAN product are performed on one device type
from one inspection for lot representing each technology. Sample
tests are performed per MIL-M-3851OJ from each three month
production of devices, which is based upon the die fabrication date
code.
Group C tests for SMD and Military Grade products are performed on one device type from one inspection lot representing
each technology. Sample tests are performed per MIL-STD-883D
from each four calendar quarters production of devices, which is
based upon the die fabrication date code.
End-point electrical tests and parameters are performed per the
applicable device specification.
Cypress uses an LTPD sampling plan that was developed by the
Military to assure product quality. Testing is performed to the subgroups found to be appropriate for the particular device type. All
Military Grade component products have a Group A sample test
performed on each inspection lot per MIL-STD-883D and the
applicable device specification.
Sub·
group
LTPD
Description
~
. JFiapRESS
_
Quality, Reliability, and Process Flows
SEMICONDUCTOR
Thble 7. Group D Quality 'lests (Package Related)
(continued)
Subgroup
Description
5
Salt Atmosphere,
Seal: Fine & Gross Leak,
Visual Examination,
Methods 1009 & 1014
6
Internal Water-Vapor
Content; 5000 ppm
maximum @ 100°C.
Method 1018
Military Grade Product
• SMD and Military Grade components are manufactured in
compliance with paragraph 1.2.1 of MIL-STD-883D. Compliant products are identIfied by an 'MB' suffix on the part
number (CY7C122-25DMB) and the letter "C"
• JAN devices are manufactured in accordance with
MIL-M-3851OJ
• Military grade devices electrically tested to:
- Cypress data sheet specifications
Quantity/Accept #
orLTPD
Components Modules [71
15 (0)
15/0
3(0) or 5(1)
N/A
OR
- SMD devices electrically tested to military drawing specifications
7
Adhesion of Lead
Finish,[8]
Method 2025
15(0)
15/0
8
Lid Torque,
Method 2024[9]
5(0)
N/A
OR
- JAN devices electrically tested to slash sheet specifications
• All devices supplied in hermetic packages
• Quality conformance inspection: Method 5005, Groups A, B,
C, and D performed as part of the standard process flow
• Burn-in performed on all devices
- Cypress detailed circuit specification for non-Jan devices
Notes:
7. Does not apply to leadless chip carriers.
8. Based on the number of leads.
9. Applies only to packages with glass seals.
OR
- Slash sheet requirements for JAN products
Group D tests for JAN product are performed per MIL-M -3851OJ
on each package type from each six months of production, based
on the lot inspection identification (or date) codes.
Group D tests for SMD and Military Grade products are performed per MIL-STD-883D on each package type from each six
months of production, based on the lot inspection identification
(or date) codes.
End-point electrical tests and parameters are performed per the
applicable device specification.
• Static functional and switching tests performed at 25°C as
well as temperature and power supply extremes on 100% of
the product in every lot
• JAN product manufactured in a DESC certified facility
Ordering Information
JAN Product:
Product Screening Summary
• Order per military document
• Marked per military document
Ex: JM3851O/28901BVA
Commercial and Industrial Product
SMD Product:
• Screened to either Levell or Level 2 product assurance flows
• Hermetic and molded packages available
• Incoming mechanical and electrical performance guaranteed:
- 0.02% AQL Electrical Sample test performed on every lot
prior to shipment
- 0.65% AQL External Visual Sample inspection
• Order per military document
• Marked per military document
Ex: 5962-8867001LA
Military Grade Product:
- Order per Cypress standard military part number
- Marked the same as ordered part number
Ex: CY7C122-25DMB
• Electrically tested to Cypress data sheet
Ordering Information
Military Modules
Product Assurance Grade: Levell
• Military Temperature Grade Modules are designated with an
'M' suffix only. These modules are screened to standard combined flows and tested at both military temperature extremes.
• MIL-STD-883D Equivalent Modules are processed to proposed JEDEC standard flows for MIL-STD-883D compliant
modules. All MIL-STD-883D equivalent modules are assembled with fully compliant MIL-STD-883D components.
• Order Standard Cypress part number
• Parts marked the same as ordered part number
Ex: CY7C122-15PC, PALC22V10-25PI
Product Assurance Grade: Level 2
• Burn-in performed on all devices to Cypress detailed circuit
specification
• Add 'B' Suffix to Cypress standard part number when ordering to designate bum-in option
• Parts marked the same as ordered part number
Ex: CY7C122-15PCB, PALC22VlO-25PIB
13-5
I
-tjj~crPR&
,
Quality, Reliability, and Process Flows
SEMICONDUCTOR
Product Quality Assurance Flow-Components
Area
PROCESS
Process Details
QC
INCOMING MATERIALS
INSPECTION
All incoming materials are inspected to documented procedures covering the
handling, inspection, storage, and release of raw materials used in the
manufacture of Cypress products. Materials inspected are: wafers, masks,
leadframes, ceramic packages and/or piece parts, molding compounds, gases,
chemicals, etc.
FAB
DIFFUSION/ION
IMPLANTATION
Sheet resistance, implant dose, species and CV characteristics are measured
for all critical implants on every product run. Test wafers may be used to collect
this data instead of actual production wafers. If this is done, they are processed
with the standard product prior to collecting specific data. This insures accurate
correlation between the actual product and the wafers used to monitor
implantation.
FAB
OXIDATION
Sample wafers and sample sites are inspected on each run from various
positions of the furnace load to inspect for oxide thickness. Automated
equipment is used to monitor pinhole counts for various oxidations in the
process. In addition, an appearance inspection is performed by the opeartor to
further monitor the oxidation process.
FAB
PHOTOLITHOGRAPHY
/ETCHING
Appearance of resist is checked by the operator after the spin operation. Also,
after the film is developed, both dimensions and appearance are .checked by
the operator on a sample of wafers and locations upon each wafer. Final CDs
and alignment are also sample inspected on several wafers and sites on each
wafer on every product run.
FAB
METALIZATION
Film thickness is monitored on every run. Step coverage cross-sections are
performed on a periodic basis to insure coverage.
FAB
PASSIVATION
An outgoing visual inspection is performed on 100% of the wafers in a lot to
inspect for scratches, particles, bubbles, etc. Film thickness is verified on a
sample of wafers and locations within each given wafer on each run. Pinholes
are monitored on a sample basis weekly.
FAB
QC VISUAL OF
WAFERS
FAB
E-TEST
Electrical test is performed for final process electrical characteristics on every
wafer.
FAB
QC MONITOR OF
E-TEST DATA
Weekly review of all data trends; running averages, minimums, maximums,
etc. are reviewed with the process control manager.
TEST
WAFER PROBE/SORT
Verify functionality, electrical characteristics, stress test devices.
TEST
QC CHECK PROBING
AND ELECTRICAL
TEST RESULTS
Pass/fail lot based on yield and correct probe placement.
TO ASSEMBLY
AND TEST
(continued)
13-6
.-
7~PRESS
------~
Quality, Reliability, and Process Flows
SENITCONDUCTOR
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
COMMERCIAL AND INDUSTRIAL PRODUCT
PLASTIC
ASSEMBLY
FLOW
HERMETIC
ASSEMBLY
FLOW
Wafer Prep/Mount/Saw
Inspect for accurate sawing of
scribeline and 100% saw-through
Die Visual Inspection
Inspect die per Cypress equivalent to
MIL-STD-883D, Method 201 0, condition B
QC Visual Lot Acceptance
Sample inspect die; 1.0% AQL
Die Attach
Attach per Cypress detailed specification
QC Process Monitor
Inspect for die position, quality and uniformity of
die attach and attachment strength,
MIL-STD-883D, Method 2010, criteria
Wire Bond
Bond per Cypress detailed specification
QC Process Monitor - Wire Bonding
Monitor bond strength and failure mode
Internal Visual Inspection
Low-power (30x) inspection of workmanship
MIL-STD-883D, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect lot to verify workmanship,
MIL-STD-883D, Method 2010, condition B,
criteria; 0.4% AQL
Die Coat
Coating applied to selected products
(continued)
13-7
I
·
.~
~"CYPRESS
~, SEMICONDUCTOR
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
PLASTIC
HERMETIC
QC Visual Lot Acceptance for Die Coated Products
Mold/Encapsulate Plastic Devices
Seal Hermetic Devices
Periodic QC Monitor, Lid-Torque
Shear strength of glass-frit seal tested
to MIL-STD-883D, Method 2024
Post Mold Cure
Per Cypress method for molding compound
Lead Trim/Form
Lead trim and form for plastic devices, lead
trim for hermetic devices (where applicable)
Lot ID
Mark assembly lot on devices
Lead Prep/Finish (Solder Dip)
Prepare leads for solder dip, solder dip devices
and inspect for uniform solder coverage
ac
Process Monitor
Verify workmanship and solder coverage
Fine and Gross Leak Test
Method 1014, Cond A or 8; fine leak (sample)
Method 1014, Cond C; gross leak (100%)
External Visual Inspection
Inspect for workmanship, construction, cracked or
broken devices, bent leads, crazing, castellation
alignment, and solder coverage.
MIL-STD-883D, Method 2009
(continued)
13-8
.
.~
--=-,":1=
Quality, Reliability, and Process Flows
CYPRESS
SEMICONDUcrOR
Product Quality Assurance Flow-Components (continued)
Commercial and Industrial Product
HERMETIC
PLASTIC
OPTIONAL BURN-IN PROCESSING FOR LEVEL 2
Pre-Burn-In Electrical Test
o
o
o
o
Burn-In
I
I
QC Monitor - Burn-In Documents/Results
I
o
I
[j
Post-Burn-In Electricals
Per applicable device specification
I
I
I
QC Inspection
PDA verified within limits
<>-l
Final Electrical Test
100% test lot; static (DC), functional and switching (AC)
tests perfomed per applicable device specification
Final Device Marking
Final Visual Inspection
Inspect for bent leads, marking, solder coverage, etc.
I QC LOT ACCEPTANCE I
External Visual Sample
Method 2009; 0.4% AQL
Electrical Sample Test
0.02% AQL to guarantee 200 PPM
Inspection - Pre-Shipment
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
Pack/Ship Order
o
Key
Production Process
D
Test/Inspection
[Q]
Production Process and Test Inspection
<>
QC Sample Gate and Inspection
13-9
a
~
~~PRFSS
~, SEMICONDUCTOR
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components
Military Components
MILITARY ASSEMBLY FLOW
Wafer Prep/Mount/Saw
Inspect for accurate sawing of scribeline and 100% saw-through
Die Visual Inspection
Inspect die per MIL-STD-883D, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect die; 1.0% AQL
Die Attach
Attach per Cypress detailed specification
Die Adherence Monitor
MIL-STD-883D, Method 2019 or Method
2027
Wire Bond
Bond per Cypress detailed specification
Bond Pull Monitor
MIL-STD-883D, Method 2011
Internal Visual Inspection
Low-power and high-power inspection per
MIL-STD-883D, Method 2010, condition B
QC Visual Lot Acceptance
Sample inspect lot per MIL-STD-883D,
Method 2010, condition B, 0.4% AQL
Die Coat
Coating applied to selected products
QC Visual Lot Acceptance for Die Coated Products
Seal
Periodic QC Monitor, Lid-Torque
Shear strength of glass
(continued)
13-10
~
zo
___-~
olE
--=-.F
Quality, Reliability, and Process Flows
CYPRESS
SEMICONDUCTOR
Product Quality Assurance Flow-Components (continued)
Military Components
Temperature Cycle
Method 1010, Cond C, 10 cycles
Constant Acceleration
Method 2001, Cond E, Y1 Orientation
Lead Trim
Lead trim when applicable
LotlD
Mark assembly lot on devices
Lead Finish
Solder dip or matte tin plate applicable devices and inspect
QC Process Monitor
Verify workmanship and lead finish coverage
External Visual Inspection
Method 2009
Pre-Burn-In Electrical Test
Method 5004, per applicable device specification
Burn-In
Method 1015, condition D
Post-Burn-In Electricals
Method 5004, per applicable device specification
PDA Calculation
Method 5004, 5%
Final Electrical Test
Method 5004; Static, functional and switching
tests per applicable device specification
(continued)
13-11
B!. ,~
.'': CYPRESS
~.,
SEMICONDUcrOR
Quality, Reliability, and Process Flows
Product Quality Assurance Flow-Components (continued)
Military Components
Lead Finish - Solder Dip
Solder dip applicable devices
Fine and Gross Leak Test
Method 1014, condition A or B, fine leak; condition C, gross leak
Final Device Marking
MIL-STD-883D or applicable device specification
Group B
Method 5005
Group A
Method 5005, per applicable device specification
Group C and D
Method 5005, in accordance with
1.2.1 of MIL-STD-883D; JAN devices
in accordance with MIL-M-38510J
External Visual
Method 2009, 100% inspection
External Visual Sample
Method 2009, 0.4% AQL
Plant Clearance
Pack/Ship Order
o
Key
Production Process
D
Test/Inspection
IQ]
Production Process and Test Inspection
<>
QC Sample Gate and Inspection
13-12
--====,
2#
. .~
Quality, Reliability, and Process Flows
i); CYPRESS
SEMICONDUcrOR
Product Quality Assurance Flow-Modules
..
Incoming materials
inspection
All incoming materials are inspected to documented
procedures covering the handling, inspection, storage,
and release of raw materials used in the manufacture of
Cypress products. Materials inspected are: substrates,
active device packages, chip capacitors, lead frames,
solder paste, inks, chemicals, etc.
Kit Picked
Compliance verified, documented,
and traceability established
Clean
Pre-assembly cleaning of components
Solder Paste Depostion
Screen printed and/or dispensed per detailed specifiction
Component Placement
Robotic and/or manual per detailed specification
Solder Reflow
Microprocessor controlled infrared reflow oven
Data logging
(optional)
<> ._
Clean
Flux removal by vapor phase
per detailed specification
100% visual
AQLvisual
2-sided
o
IQ]
o
Double-Sided Assembly
Repeat process for side 2
Solder paste deposition
I
1-sided
Component placement
I
Solder reflow
o
~
o
o
<> -.-~ ----
1-sided
I
I
o
... ·:···0
2-sided
Clean
AQLvisual
Inspect
100% visual
Lead Trim
Electrical Test
(Pre-burn-in test)
(continued)
13-13
I
~
~
ill CYPRESS
Quality, Reliability, and Process Flows
~, SEMICONDUCTOR
Product Quality Assurance Flow-Modules (continued)
OPTIONAL BURN-IN PROCESSING FOR LEVEL 2
(STANDARD FOR MIL DEVICES)
- --I
o
o
o
Burn-In
Method 1015
o
QC Monitor - Burn-In Documents/
Results
D
Post-Burn-In Electricals
Per applicable device specification
I
o,,
I
~-<>
QC Inspection
PDA verified within limits
<>-~
,- ---
I
Final Electrical Test
100% test lot; DC, AC, functional, and dynamic
tests performed per applicable device specification
Final Device Marking
Final Visual Inspection
Confirm part type, count, package, check for
completeness of processing requirements, confirm
supporting documentation is sent, if required
QA electrical test
(roomtemperature)
Inspection - Pre-Shipment
Pack/Ship Order
o
Key
Production Process
D
Test/Inspection
[Q)
Production Process and Test Inspection
<)
,- --
QC Sample gate and inspection
13-14
.=-
---=-.':~PRESS
Quality, Reliability, and Process Flows
.
SEMICONDUcrOR
Reliability Monitor Program
The Reliability Monitor Program is a documented Cypress procedure that is described in Cypress specification #25-00008, which is
available to Cypress customers upon request. This specification
describes a procedure that provides for periodic reliability monitors to insure that all Cypress products comply with established
goals for reliability improvement and to minimize reliability risks
for Cypress customers. The Reliability Monitor Program monitors
our most advanced technologies and packages. Every technology
produced at a given fabrication site (Tech. - Fab.) and all assembly houses are monitored at least quarterly. If failures occur, detailed failure analyses are performed and corrective actions are
implemented. A summary of the Reliability Monitor Program test
and sampling plan is shown below.
Quarterly Reliability Monitor Test Matrix
# per
Quarter
Devices Tested
Stress
HTOL
HAST
Tech. - Fab.
6
All High Volume
2
Tech. - Fab.
6
All High Volume
2
PCT
Plastic Packages
4
TC
Tech. - Fab.
6
Plastic Packages
3
Ceramic Packages
5
All High Volume
2
DRET
FAMOS - San Jose and Texas
2
HTSSL
All Technologies
4
TEV
All Technologies
4
Total
46
Reliability Monitor Test Conditions
Abbrev.
Temp. (0C)
R.H. (%)
Bias
Sample
Size
LTPD
Read Points
(hrs.)
High-Temperature
Operating Life
HTOL
+150
N/A
5.75V Dynamic
116
2
48, 168, 500,
1000
High-Temperature SteadyState Life
HTSSL
+150
N/A
5.75V Static
116
2
48, 168, 500,
1000
Data Retention for
Plastic Packages
DRET
+165
N/A
N/A
76
3
168, 1000
Data Retention for
Ceramic Packages
DRET2
+250
N/A
N/A
76
3
168,1000
Test
PCT
+121
100
N/A
76
3
96, 168
Highly Accelerated Stress
Test
HAST
+140
85
5.5V Static
76
3
128
Temperature Cycling for
Plastic Packages
TC
-40 to
+125°C
N/A
N/A
76
3
500, 1000 Cycles
Temperature Cycling for
Ceramic Packages
TC2
-65 to
+ 150°C
N/A
N/A
45
5
500, 1000 Cycles
Temperature Extreme
Verification
TEV
Commercial
Hot & Cold
oto +70°C
N/A
N/A
116
2
N/A
Pressure Cooker
13-15
Il
CYPRESS
SEMICONDUCTOR
Tape and Reel Specifications
Description
Surface-mounted devices are packaged in embossed tape and
wound onto reels for shipment in compliance with Electronics Industries Association Standard EIA-481 Rev. A.
Specifications
Cover Tape
• The cover tape may not extend past the edge of the carrier tapes
• The cover tape shall not cover any part of any sprocket hole.
• The seal of the cover tape to the carrier tape is uniform, with the
seal extending over 100% of the length of each pocket, on each
side.
SOIC Devices
• The force to peel back the cover tape from the carrier tape shall
be: 20 gms mmimal, 70 gms nominal, 100 gms maximal, at a pullback speed of 300 ± 10 mm/min.
Loading the Reel
Empty pockets between the first and last filled pockets on the tape
are permitted within the following requirements:
• No two consecutive pockets may be left empty
• No more than a total of ten (10) empty pockets may be on a reel
The surface-mount devices are placed in the carrier tape with the
leads down, as shown in Figure 1.
TYPICAL
PLCC and LCC Devices
TYPICAL
DIRECTION OF FEED
SOJDevices
TYPICAL
DIRECTION OF FEED
[[][[][[]
DIRECTION OF FEED
Figure 1. Part Orientation in Carrier Tape
13-16
PIN #1 TO BE ON CIRCULAR
SPROCKET-HOLE SIDE OF TAPE
Tape and Reel
Leaders and Trailers
The carrier tape and the cover tape may not be spliced. Both tapes
must be one single uninterrupted piece from end to end.
Both ends of the tape must have empty pockets meeting the following minimum requirements:
•
•
•
•
Trailer end (inside hub of reel) is 300 mm minimum
Leader end (outside of reel) is 500 mm min., 560 mm max.
Unfilled leader and trailer pockets are sealed
Leaders and trailers are taped to tape and hub respectively using
masking tape
Cypress pin
Cypress CS number (if applicable)
Customer pin
• Each box will contain an identical label plus an ESD warning
label.
Ordering Information
CY7Cxxx-yyzzz
xxx = part type
yy
= speed
Packaging
zzz = package, temperature, and options
• Full reels contain a standard number of units (refer to Table 1)
• Reels may contain up to 3 inspection lots.
• Each reel is packed in an anti-static bag and then in its own individual box.
• Labels are placed on each reel as shown inFigure 2. The information on the label consists of a minimum of the following information, which complies with EIA 556, "Shipping and Receiving
Transaction Bar Code Label Standard":
- Barcoded Information:
Customer PO number
Quantity
Date code
- Human Readable Only:
Package count (number of reels per order)
Description
"Cypress-San Jose"
SCT = soic, commercial temperature range
SIT = soic, inductrial temperature range
SCR = soic, commercial temperature plus burn-in
SIR = soic, industrial temperature plus burn-in
VCT = soj, commercial temperature range
VIT = soj, industrial temperature range
VCR = soj, commercial temperature plus burn-in
VIR = soj, industrial temperature plus burn-in
JCT = pIcc, commercial temperature range
JIT = pIcc, industrial temperature range
JCR = pIcc, commercial temperature range plus burn-in
JIR = pIcc, industrial temperature range plus burn-in
Notes:
1. The T or R suffix will not be marked on the device. Units will be
marked the same as parts in a tube.
2. Order releases must be in full-reel multiples as listed in Table 1.
Table 1. Parts Per Reel and Tape Specifications
Package lYPe
Terminals
Carrier Width (mm)
Pocket Pitch
Parts Per Meter
Parts Per Full Reel
PLCC
18
20
24
16
3
3
83.3
83.3
750
750
28(S)
24
4
62.5
500
32
44
24
32
4
62.5
6
41.6
500
400
52
32
44
6
8
41.6
31.2
400
250
68
84
SOIC
SOJ
44
8
31.2
250
20
24
3
83.3
1,000
24
24
3
83.3
1,000
28
20
24
24
83.3
83.3
1,000
1,000
24
24
24
3
3
3
83.3
1,000
3
83.3
1,000
28
13-17
•
~~PRFSS
Tape and Reel
~# SEMICONDUCTOR
Tape and Reel Shipping Medium
ESD STICKER
TAPE SLOT IN CORE
13"
REGULAR, SPECIAL, OR
BAR CODE LABEL
Label Placement
Figure 2. Shipping Medium and Label Placement
13-18
INFO
SRAMs
PROMs
PlDs
FIFOs
lOGIC
DATACOM
MODULES
ECl
BUS
MiliTARY
TOOLS
QUALITY
PACKAGES
I
I
11
II
I
I
I
I
I
I
I
I
I
I
~PRFSS
_rs~CONDUcrOR
Packages
Section Contents
Page Number
Thermal Management and Component Reliability ............................................................ 14-1
Package Diagrams ...................................................................................... 14 -11
Module Package Diagrams ................................................' ............................... 14-66
Sales Representatives and Distributors
Direct Sales Offices
North American Sales Representatives
International Sales Representatives
Distributors
CYPRESS
SEMICONDUCTOR
Thermal Management and
Component Reliability
One of the key variables determining the long-term reliability of
an integrated circuit is the junction temperature of the device
during operation. Long-term reliability of the semiconductor chip
degrades proportionally with increasing temperatures following
an exponential function described by the Arrhenius equation of
the kinetics of chemical reactions. The slope of the logarithmic
plots is given by the activation energy of the failure mechanisms
causing thermally activated wear out of the device (see Figure 1).
Typical activation energies for commonly observed failure mechanisms in CMOS devices are shown in Table 1.
J
/
/
I
,
I
1.4 eV
1.0 eV
I
I
,
I
I
I
~
I
I
II
/
/
V
V
104
:::::i
iIi
J
I
«
:::::i
w
a:
w
>
,
/
V
J
103
1
I
/
0.5 eV ;;;;;;;;;;
~
C\J
C\J
L
()
w
a:
J /
102
I
I
,
I
/,
~V
C\J
C\J
~ ~C; -'
O.4ev./
,/1
0.3eV
./
'JA
~
, , ,
- - - --- - -- - - l'.... ,
,
"'- ~~
r-- -- -- - - - - - - -
"
~
,
'"
a:
a:
100000 SQ. MIL
,,
'~ i'..
w
U
5000 SQ. MIL
30000 SQ. MIL
,
E>JC
- --
r-- -
-
-
-
- --
-- r--
- - - - - - -- -- - - f--
f-- -
o
16
20
24
28
32
36
40
44
48
52
56
60
64
LEAD COUNT
Figure 2. Thermal Resistance of Cypress Plastic DIPs (Package type "P")
120
DIE SIZE
110
- - - - - - -
100
90 1\\
~
~
80
~,
'~ ,
w
u
z
j:!:
en
-- - -
\~
"'-:'
70
'\1\ '
60
Ci5
w
50
...J
40
~~
w
J:
BJA
i'-..
f'
:::!!:
a:
,
,.~
a:
«
30
<::
, ,
~
~
20
I- - _
r=-
0
16
E>JC
~
20
-- -- - -- - - - - - - - -- ---r-- -1 - ---
~
~
10
5000 SQ. MIL
30000 SQ. MIL
-- ---- - - - -- - - - - - - - -- - - - -- - ---- -- r-- -
roo - _
24
28
r-
32
36
40
44
48
1---
52
56
-1-
60
64
LEAD COUNT
Figure 3. Thermal Resistance of Cypress Ceramic DIPs (Package type "D" and "W")
14-4
100000 SQ. MIL
·4
Thermal Management
~~CYPRESS
--=-,
SEMICONDUCTOR
120
DIE SIZE
110
- - - - - - -
100
5000 SQ. MIL
30000 SQ. MIL
90
,,
~
80
~
w
70
z
60
~
:::
-- - -
,,
~
,,
"
~
()
~
'I'--:
CI)
Ci5
w
a:
...J
50
-B>
R. 0.20 TYP.
14-38
L
O.BO±O.15
~~
,
Package Diagrams
--=-.'
_'=CYPRESS
SEMICONDUCTOR
Plastic Quad Flatpacks (continued)
160-Lead Plastic Quad Flatpack N160
PIN #1
--...l
L.300 [,012]
TYP
.650 [,0256]
TYP.
DIMENSION IN
MM
[
INCHES o.s reference only ]
LEAD CDPLANARITY .100 [.004]
_LI
.127±.02
c.005±.001l
I
MIN. 3.59
MAX. 3.99
~_,~~~~~~~~~---.l.
Uill
SEATING PLANE
U57l
t MIN. 050t
MAX.
560
[.002]
[.020]
~L
.800±.15
c.031±.006]
II
14-39
Package Diagrams
Plastic Quad Flatpacks (continued)
160-Lead Plastic Quad Flatpack
with Molded Carrier Ring N161
1 - - - - - - - 63 X .650±.025 = 40.95±.lO - - - - - - - 1
O.35±O.15
0.65±0.20
.....wJw,.,.",---'-
1.50±O.l3
F}+"II4--I--17.600
+i:1:jj::t=t==1~:~~01
Vl
W
f-
PACKAGE
PIN #1
L-
o
W
L:J
'"
W
W
'"
-----~~~++-O.OOO
Vl
f-
::0
o
o
f-
.50 DIA. TYP
1.50 DlA. TYP
2.50±0.50 RAD.
TOP & BOTTOM
TEST PAD
#64
TEST PAD
#65
0.25 TYP
TEST PAD
#129
TEST PAD
#128
- - - - - - 41.50 TYP TOP AND BOTTOM - - - - - - - - 1
4.00±O.50 RAD.
TOP & BOTTOM
7'±I' TYP
SECTION B- B
0.45±O.05
~~~~~~~~~~~~~~~~§~o
O~
0.110
0.325
II
0. 310
0.385
-l
~
O~
0"'0
0280-oj
.
~.~~~
0.012+
I-
0.020
3' MIN.
20-Lead (300-MiI) Molded DIP P5
PIN 1
DIMENSIONS IN INCHES MIN.
MAX.
~
Q.2ZQ.
L
~~120
~
Jl
0i90
SEATING PLANE
0140
"''"
o
0160
0015
0060
~
0.110
0055
0065
II ~
-II- 0020
14-41
Q.QQ'2.
0012
~ 0o325
280 ~
-M
~
1-.!ld1Q-l
0.385
3' MIN
I
~
5IIIIIi ~PRFSS
Package Diagrams
~, SEMJCONDUcrOR
Plastic Dual-In-Line Packages (continued)
22-Lead (400-MiI) Molded DIP P7
DIMENSIONS IN INCHES MIN,
MAX,
r-
0,380
---j
Ii 0.425 11
ffE3]~r
0,009
0012l}-
30 MIN
~M1Q---1
0.485
22-Lead (300-MiI) Molded DIP P9
PIN I
DIMENSIONS IN INCHES !1li'!,.
MAX,
r-
0280-j
Ir 0 325 II
9
Q&Q2
0012+
I-
~~ 30
MIN
0,310--1
0,385
24-Lead (600-MiI) Molded DIP PH
PIN I
DIMENSIONS IN INCHES
t=
~
ir==
~~IJ~lttl
~
~
+
0060
I-lZ]Q
SEATING PLANE
0160M¥¥¥¥~
0.110
~~~~ JL~
I
r
_._--
U.ucu
14-42
0012
0 570
";3'
~
l,.,,,
0610----1
0.685
'
·
.~
Package Diagrams
ij; CYPRESS
~IF SEMICONDUCTOR
Plastic Dual-In-Line Packages (continued)
;
,
:
oq
24-Lead (300-MiI) Molded DIP PI3/P13A
0.270
---.l
NOTE B
~
DIMENSIONS IN INCHES MIN.
MAX.
I NOTE A
I NOTE B
P 13
P 13A
1.170
1.200
1:260
1.230
QM&
0.080
.!1Q;N
0.050
1rr Jilllll-j
0.325
11
0.009
0.012
+I-B
~~
.
3. MIN
0.310-1
0.385
28-Lead (600-MiI) Molded DIP PIS
PIN 1
DIMENSIONS IN INCHES
t1ll-L.
MAX.
~
450
1480
~
0155
OA50~00
0160
J
~
0090
o:i.TO
40-Lead (600-Mil) Molded DIP P17
PIN 1
DIMENSIONS IN INCHES MIN.
MAX.
r--1~2070
2040
III
14-43
~
~~PRESS
...
,
~~CONDUCTOR
Package Diagrams
Plastic Dual-In-Line Packages (continued)
32-Lead (600-MiI) Molded DIP P19
PIN 1
DIMENSIONS IN INCHES
MIN.
MAX.
r-- .625 ----J
1,--~I
600
:~~~ ~
L~-1
3' MIN.
,670
oq;':
28-Lead (300-MiI) Molded DIP P21
DIMENSIONS IN INCHES .!::1.!!::k
MAX.
0,270
~
~
~
0.Q30
0.080
370
r-
1425
~
.!1.ill.
~
J
~
0T-0090
0,110
0280-j
Ir 0325 II
0009
0012
+B
~t
3'MIN
~~~
48-Lead (600-MiI) Molded DIP P2S
PIN 1
O
DIMENSIONS IN INCHES MIN.
MAX,
0,530
~j50
~I
~ 0,065
0,085
L
~
o~wmJ~l~
M~ ~ ~ ~-
0160
~
a,iio
-j
r-
~ ~~~
u,u::>::>
=
II"""
-II-
Ir= ~~~~ ~
. "' -t~ = ~~~ ,. '"
SEATING PLANE
0015
0 060
14-44
0012
L-
O§oo
u,/uu
---J
Package Diagrams
Plastic Dual-In-Line Packages (continued)
64-Lead (900-MiI) Molded DIP P29
DIMENSIONS IN INCHES MIN,
MAX,
I
I
3.160
3,240
o*o~~ado,
0,A~'~25
,J ~ ,
I
°flO
0.160
r~
0 055
0,065
~ ~~
r
SEATING PLANE
0015
0:060
0,020
~
0,009
0,012
rr=
--P
I----
0,880
0,920
~
0,960
1.050
==J
:
J I~ 3'
-I
MIN,
------I
32-Lead (300-MiI) Molded DIP P31
DIMENSIONS IN INCHES MIN,
MAX
28-Lead (400-MiI) Molded DIP P41
DIMENSIONS IN INCHES MIN,
MAX,
rr~~
0
0
0,015' 0 0 9 E 3 3
MlQ
0.485
14-45
MIN'
II
-
~~
Package Diagrams
~,ilgyPRF.SS
SEMICONDUCIOR
Plastic Dual-In-Line Packages (continued)
32-Lead (400-MiI) Molded DIP P43
PIN 1
o~
DIMENSIONS IN INCHES MIN.
MIil[
Ceramic Windowed Leadless Chip Carriers
20-Pin Windowed Square Leadless Chip Carrier Q61
MIL-STD-1835 C-2A
32-Pin Windowed Rectangular Leadless Chip Carrier Q55
MIL-STD-1835 C-12
DIMENSIONS IN INCHES
MIN.
MAX.
32 PLACES
,280 DIA,
LENS
DIMENSIONS IN INCHES
MIN.
MAX,
,QM~
~
:oso
,110
,050
~
14-46
L~PRFSS
~_
Package Diagrams
. , SEMICONDUCTOR
Ceramic Windowed Leadless Chip Carriers (continued)
44-Pin Windowed Leadless Chip Carrier Q67
MIL-STD-1835 C-5
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
DIMENSIONS IN INCHES
MIN,
MAX,
BOTTOM
.045
,055
.114
,290 DIA,
LENS
11
TOP
C-'R/ JJ
""
1~
&!!Zi
:m
087
114
045
066
~
I
""'~
~
458~
I
Ceramic Windowed Pin Grid Arrays
68-Pin Windowed PGA Ceramic R68
DIMENSIONS IN INCHES
MIN,
MAX.
F
1.112
1.089~
.990
TOIO
,175
,185
INDEX MARK
68 X
l
1-i
fu
L
~DIA'S
,100
TYP .
.100 TYP,
68 X .080 DIA, MAX.
SEATING
PLANE
14-47
•
~PRFSS
Package Diagra.ms
.nCONDUcrOR
Ceramic Windowed Pin Grid Arrays (continued)
84-Lead Windowed Pin Grid Array R84
SEATING PLANE
,390 DIA,
LENS
INDEX MARK
(NO PIN)
(
.100
~----~~=-~~~~-=~~~
X
~DIA '
,020
BDTTDM VIEVI
Plastic Small Outline ICs
16-Lead Molded sOle SI
PIN 1 ID
DIMENSIONS IN INCHES
MIN,
MAX,
LEAD CDPLANARITY 0,004 MAX,
0,291
0,300
J
0,393
0.420
~tk1
0,032
t=
0,397
----j
SEA TING PLANE
0.413~~
Jl
~
~
0,050
TYP,
0,013
0,019
0,092
0,105
0,003
o:Gi2
14-48
g:~
Package Diagrams
Jj; CYPRESS
_ , SEMICONDUcrOR
Plastic Small Outline ICs (continued)
IS-Lead (300-MiI) Molded
sOle S3
PIN 1 ID
~
MAX,
LEAD COPLANARITY 0,004 MAX,
DIMENSIONS IN INCHES
t=
---j
0.447
SEATING PLANE
0,463 _ _..+~
~-.l
0,050
TYP,
II
0,013
-j f-- o:Di9
0.092
0.105
~
0,012
20-Lead (300-MiI) Molded sOle S5
PIN 1 ID
0,291
0,300 0,393
J
DIMENSIONS IN INCHES ~
MAX,
LEAD COPLANARITY 0,004 MAX,
0.420
~~
0,032
0.497
----j
+__----,
t=
~-.l
SEATING PLANE
0,513 _ _ _
0092
0.105
0,050
Typ,
II
0,013
-j f-- o:Di9
•
0,003
o:Gi2
14-49
~PRE&S
Package Diagrams
WnEMICONDUCTOR
Plastic Small Outline ICs (continued)
24-Lead (300-Mil) Molded sOle S13
PIN 1 ID
DIMENSIONS IN INCHES
~
MAX,
LEAD CDPLANARITY 0,004 MAX,
r----
I~
SEATING PLANE
0,597
0,615
---j
~L----.i
)j I'----------'h~~
~--<:.1ciJ
0,050
TYP,
II
--H-
0,013
0,019
Qlli5.
0,050
0,003
o:oT2
28-Lead (300-Mil) Molded
J [L
0,007
0,013
sOle S21
PIN 1 ID
DIMENSIONS IN INCHES ~
MAX,
LEAD CDPLANARITY 0,004 MAX,
SEATING PLANE
~~ D.i05
""92
0,050
TYP,
II
--II--
0,013
0,019
0,003
0,012
14-50
=::.
-~
-=-,
Package Diagrams
=======' .. CYPRESS
SEMICONDUCTOR
Plastic Small Outline ICs (continued)
28-Lead (400-MiI) Molded
DIMENSIONS IN INCHES
sOle S28
l1.l.t:L
DETAIL
MAX
LEAD COPLANARITY 0.004 MAX.
A
EXTERNAL LEAD DESIGN
PIN 1 ID
QH
;026
-J~JlU
,019
'---------w
I-o",~-- ';~~
----
'-i!HiI--lH}HJ-JlHHHHHHHJ--IJ
,050
OPTION 1
I
1
~ ~~~
Jj \
I
,015
,050
32-Lead (400-MiI) Molded
MIN,
MAX,
LEAD COPLANARITY 0,004 MAX,
OPTION 2
,SEATING PLA_N_E_ _ __
:~~~
TYP,
.032
,015
,020
t~
IlL ,007
-II- ,013
sOle S33
DIMENSIONS IN INCHES
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
rR1~~
~'032
W
,026
,015
,020
SEATING PLANE
,830
,820
,050
TYP,
002
II
:oi4
14-51
~
~~PRESS
..
,
~b..nCONDUcrOR
Package Diagrams
Windowed Cerpacks
24-Lead Windowed Cerpack T73
DIMENSIONS IN INCHES
MIN,
MAX,
/
PIN 1 L D I ' \
I
I
,005
,015
.170 DIA, LENS
~';:;"
/
o
,590
RO
F====
~
,050 BSC
~==1
~
L ,005
L360~
0400
MIN,
BASE AND
SEATING
PLANE
,004
,009L
t
I
L,260J
,325
28-Lead Windowed Cerpack T74
r
,
r
,7
40
MAX,
,005
,015
fr
PIN 1 LD,
t-- ,180 _
f'
TYP,
045 MAX,
1
t
~
TYP,
DIMENSIONS IN INCHES
MIN,
MAX,
=
=
~
=
=
~D
t
~'
050 BSC
1
~
=
L,340~
,380
L ,005
MIN,
BASE AND
SEATING
PLANE
14-52
-m.
:~
Package Diagrams
- - -. • CYPRESS
F SEMICONDUcrOR
Windowed Cerpacks (continued)
68-Lead Windowed Cerquad Flatpack T91
ELECTRICAL
PIN 1
1
.942
.958
II
14-53
#_~
Package Diagrams
~ ill CYPRESS
~_, SEMICONDUCTOR
Ceramic Quad Flatpacks
64-Lead Ceramic Quad Flatpack (Cavity Up) U65
TYP,
DIMENSIONS IN MILLIMETERS
LEAD CDPLANARITY 0,102 MAX,
DIMENSION
0,80 TYP,
a
~221
"±4"
-'
2,83
3,00
MAX,
~
0.10 MIN,
STANDOFF
~
R, 0,20 TYP,
~L~" LDfl
-
0,25
0,50±0,15
14-54
MIN,
MAX,
~
==:::-
.~
Package Diagrams
- J ,=. CYPRESS
~., SEMICONDUCTOR
Ceramic Quad Flatpacks (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
DIMENSION IN MM
~~~
BASE PLANE
590
r---:620---i
Fill
I
~",J
,690
SEATING PLANE
I
14-61
Package Diagrams
Ceramic Windowed Dual-In-Line Packages (continued)
28-Lead (300-MiI) Windowed CerDlP W22
MIL-STD-1835 D-15 Config. A
.140 X ,300 DR
.140 X 0400
GLASS LENS
PIN 1
32-Lead (300-MiI) Windowed CerDlP W32
..
,140 X ,300 DR
.140 X 0400
GLASS LENS
DIMENSIONS IN INCHES
MIN
MAX
D
t
155
245
-,~~~~-,~.-~~-,~~o
~~~
MIN~l-
~
850
d B A S E PLANE
I
I
1650
290
2O~~~j_t~r··~~~~LI,
;;;~j065
015
,020
!TO
SEA TING PLANE
14-62
15'
330
390
-
~
~.if CYPRESS
.
Package Diagrams
.
~ iF SEMICONDUCTOR
Ceramic J-Leaded Chip Carriers
52-Pin Ceramic Leaded Chip Carrier Y59
DIMENSIONS IN INCHES
MIN.
MAX
PIN 1
_+1m
_
SEE
VIE\-! A
',738 .785
756 .795
~ 7~Er
.756
.785
.795
SEA TING PLANE
-11-.050
D40 X 45°
BSC
VIE\-! A
II
14-63
~
~PRFSS
~.. SEMICONDUCTOR
Package Diag~ams
Ceramic J-Leaded Chip Carriers (continued)
28-Pin Ceramic Leaded Chip Carrier Y64
PIN 1
I
---+---
n
1
I
-J
~
k,050
,032
BSC
,040 X 45°
14-64
~
~~PRESS
~, SEMICONDUCTOR
Package Diagrams
Ceramic J-Leaded Chip Carriers (continued)
84-Pin Ceramic Leaded Chip Carrier Y84
DIMENSIONS IN INCHES
MIN.
PIN 1
I
---+---
MAX.
m
1.142
1.158
1.185
1.195
E ll~2=fJ
1.158
1.185
1.195
.155
200
I
I
---+---
I
.040 X 45°
--ll-.050
BSC
1:ypical Marking for DIP Packages (P and D 1Ype)
DEVICE WITH
SPEED, PACKAGE, AND TEMP RANGE
DATE CODE:
X'X'fY
XX = YEAR
YY = WORK WEEK
WEEK PARTS WERE MARKED (FOR PLASTIC)
WEEK PARTS WERE SEALED (FOR HERMETIC)
ASSEMBLY CODE:
IDENTIFIES SPECIFIC MARK LOT
THE PRODUCT CAME FROM.
14-65
IDENTIFIES THE SPECIFIC ASSEMBLY
LOT THE PRODUCT CAME FROM.
II
Module Package Diagrams
CYPRESS
SEMICONDUCTOR'
32·Pin DIP Module 8D04
-
-
T
0.590
0.610
~
1
•
- +
~
0.013
DIMENSIONS IN INCHES
MIN.
MAX.
0.100
TYP
0.015
0.021
0.050
TYP
60·Pin Ceramic DIP Module 8D06
,-
-,
~
[I D~ D~01D ~ IJ ~ I ~ 1
-I
0.610
=4
.Q.QQZ
0.013
DIMENSIONS IN INCHES
0.035
0.060
0.015
0.021
0.100
TYP
14-66
MIN.
MAX.
~
~.~
~i; CYPRESS
-iF
Module Package Diagrams
SEMICONDUcrOR
28-Pin Ceramic DIP Module UDtO
1.415/1.445
-I
PIN 1
INDICATOR
~ ~I
~1.300~
I
.100TYP.
32-Pin DIP Module UD12
I'
'I
'.~
DDDJoo
~
0.175
f.Q:ill
DIMENSIONS IN INCHES
MIN.
MAX.
EMAX
JL
0.60~
0.100
II
14-67
Module Package Diagrams
66·Pin PGA Module HGOI
11 2233
445566
®®®
®®®
®®®
®®®
®®®
®®®
®® 0
®®®
®®®
®®®
®®®
®®®
®®®
®®®
®®®
®®®
®® 0
1 1223
344556
14-68
1.000TYP.
~
.
:~PRESS
Module Package Diagrams
_ , SEMICONDUCTOR
401-Pin PGA Module HG02
i
2
,828 M A X i
0
0
0
0
.lOO±,OOS TYP,
·0
0
0
0
0
2,828 MAX
0
0
PDLARIZA TJDN PIN
("PIN #401")
0
80
,200 ±,014 TYP
0
PIN 1 MARK
,100 ±,OOS TYP
TOP VIE\,!
.100
,180
~ 2,828 MAX
BOTTOM VIE\,!
I
I
~'00;'t-' 1 Iil l~t"rFrl~' ' t!r' i' ';' ~ 't'~"'r"r ~' 'r ~' 'r f~
=tL
±,014 TYP
~~
050
'"DC
MAX
Jt
II=,"02
2,400 ±,OOs--J
END VIE\,!
050 DIA ± 002
SHOULDER DETAIl
(TYPICAL 4 CORNER PINS)
I
14-69
~
.
·~PRFSS
""""=IIIr'
Module Package Diagrams
SEMICONDUCTOR
401-Pin PGA Module HG03
1 - - - - - - - - 3,030 MAX - - - -
D
,100±,005 TYP,
D
0
0
.0
0
D
D
3,030 MAX
1(\
D
I~ ~
POLARIZA TlON PIN
('PIN #401')
0
0
BD
,300 ±,015 TYP
D
Co
PIN 1 MARK
,100 ±,005 TYP
TOP VIE'W
±,015 TYP
BOTTOM VIE'W
y~050
jt
!I .018
END VIE'W
'005
DIA '002
,050 DIA ±,002
SHOULDER DETAIL
I
~
M
~~
E9
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
To
I- 0.350-1
1--;:::,
=(dREF
~
.
==-
.~
Module Package Diagrams
~=CYPRESS
~.' SEMICONDUCTOR
128-Pin Dual-Readout SIMM Module PMOS
1 ·~
_________
3'855 MAX
--------,-,--"'1
,330 MAX
3.580/3.588 - - - - - - - - ".
r-
l
r
.123/.127 DIA
2 PLCS
PIN 65
128-Pin Dual-Readout SIMM Module PM06
I
--------=-----1"1
" "-,,_____- - - - - - - - - 3 . 8 5 5 MAX
r3,580/3,588 - - - - - - - - -
,330 "AX
'"'
~~l
o
0
O
=mmrnnnnmr
~
__
~_J ~061/063R~~
l
c:::::::JDc:::::::J
,123/,127 DIA
2 PLCS
c:: : : J
oc:::::::Joc:::::::Joc:::::::J
=
o
$
l
r
1150 MAX
I
PIN 65
249/251
3,348/3,352 - - - - - - - -
128-Pin Dual-Readout SIMM Module PM07
1--------------
3,855 MAX - - - - - - -
.0--------------
1<'
3,580/3,588 - - - - - - - c >
,330 MAX
.123/.127 DIA
2 PLCS
PIN 65
II
14-77
12S-Pin Dual-Readout SIMM PMOS
64-Pin Plastic Angled SIMM Module PNOI
_-------3.845/3.855-------
-t
.590/.600
14-78
~
~~PRFSS
~_;tII'.I SEMICONDUcrOR
Module Package Diagrams
64-Pin Plastic Angled SIMM Module PN02
~--------
3.845/3.855 - - - - - - - - - . \
3.348/3.352
.245/.255 - .
------~
64-Pin Plastic Angled SIMM Module PN03
oI
128K X 8
c::J
@
]
I
c::J c::J
128K X 8
€l
]
I
c::J c::J
128K X 8
@
]
I
c::J c::J
128K X 8
E?
]
0
c::J
II
14-79
~PR&§.
_~ICONDUcroR
Module Package Diagrams
72-Pin Plastic Angled SIMM Module PN04
4,255 MAX
1----------
3,980/3,988
---------1
I
"""l r
i-I--~-[]
-~-[]-~-=]---:--~-[]-+-i~ ~M" ,
It-.------- 3'748/3'752~ ~ ~ ~ ~ ~ ~ ~:- - 1~REF
44-Pin Plastic SIP Module PS04
I-
-I
~
I
l
~
~ -..J~II~f.-
_I 1 0.100
i i lYP
0,075
~
--.j
0,340
MAX
rTO,330
~,350
~
_II
ii
0,007
M13
0.015 0.125
0,025 0,175
DIMENSIONS IN INCHES
MIN,
~
36-Pin SIP Module PS05
Top View
0,01
lYP
14-80
.
_
~~
Module Package Diagrams
. :... CYPRESS
. , SEMICONDUcrOR
36-Pin SIP Module PS06
J
~_ _ _ _ _ _ _ _ 3.755 _ _ _ _ _ _ _ _~.1
3.765
--1
PIN 1
-,
r MAX.
.190
f.-.1 00 TYP
\4-------- 3.500 (36 PINS)
..
1
44-Pin Plastic SIP Module PS07
I'"
-1
-I
4.400 MAX.
G:
O~==D~-r.:MAX.
I --I ~ 0.100TYP.
I
BUFFERS
4.300 (44 PINS)
II!
•
0.125
~ 0.175
,
r-
0.335 MAX.
~'5rve
0032REF~-+
SRAM (1Mx 1)
STAND-OFF DETAIL
36-Pin SIP Module PS08
1+-_ _ _ _ _ _ _
3.755 _ _ _ _ _ _ _ _-+1_\
3.765
.120 MAX.
~====~ ~====~II~
I
.755/ .040 TYp.
_plIN-1~1~~.~~fl='1~00~TYmp~flW~~flW-1m~~'02lO'TY'P."'_1~2H75
.-
3.500 (36 PINS)
- .
14-81
II
Module Package Diagrams
40-Pin VDIP Module PVOI
0.345
N
L~lf ~
f
~
0100
~ L
TvP I ,- .
~L
0.10~ ~
0.Q15
I I M25
0.013
TYP
0.175
DIMENSIONS IN INCHES
MIN.
MAX.
36-Pin Plastic Vertical DIP Module PV03
0.100xO.100
CHAMFER
1.~
-I
0.345
0000 0
MAX.
rI
f
0.540
MAX.
PIN 1
~n~
0.100
TYP
1.700 REF.
-J
0.090
ITITO
DIMENSIONS IN INCHES
MIN.
MAX.
14-82
~
.
;~PRESS
-===,
Module Package Diagrams
SEMICONDUCTOR
40-Pin Plastic VDIP Module PV04
0.100 x 0.100
CHAMFER
MAX.
O
o
0
0
-----,t~
0
h
~
0.100
TYP
1.900 REF.
W
0.540
I
~~~~~~~~~~~~
PIN 1
-110Jr
t
MAX.
t
0.005 MIN.
~
DIMENSIONS IN INCHES
MIN.
MAX.
64-Pin Plastic ZIP Module PZOI
Bottom View
~~0.050
~
-I
J.:C]oC]oC]oC]o*
1.120
1.150
I
!-'I!~""'ll'Ir'Ill'IrlI~""~,"l'IIrlI",,~ma!ll'Ir'Ill'IrlI~""~,"l'IIrlI",,~ma!If----,r~""'ll'Ir'Il'Ir'Il""l'lI"'Il'IIrtll'Ir~l'I!IIll'Ir'Ill'IrlI~""~,"I'IIrlI",,~f'nIIlf-'~
I ~I 1..L
0.135
.11.
ii
0.015
JO.250L
J
r-:-
1_
i
0.100
.J I.
Ji
0.165
0.025
""1 TYP
""1
TYP
' ; a a a aa a a a no a a a a aa a a aa a a aa a a a a a a a
a a a a a a a aa a a a a a a a a aa a a aa a a a a a a a a n
0.050
TYP
I
J
~
0.100
TYP
Pin 1
DIMENSIONS IN INCHES
MIN.
MAX.
II
(J)
UJ
CJ
.150
I
~~m~I'Ir'I~~ll'IrIIf~~'trII"rrllf'lrlIf'rIroItl'tl~m~I'Ir'I~.~...,.,~m~I'Ir'I~~I~f~~'trII"rrII"'rlIf'rI~""'~m~1'Ir'I~I""'-'-
1 f.¥. . . . .+. ~ ...- !"~1Pr.I
r.-
i"""""""""""""""
. . . . .--l
r,O~O. , , ,Jr ~
""""""""""""""""
I
0.008
0.014
J
~
0.100
TYP
Pin 1
DIMENSIONS IN INCHES
MIN.
MAX.
56-Pin ZIP Module PZ05
Bottom View
DIMENSIONS IN INCHES
MIN.
MAX.
II
14-85
f.y;cYPRFSS
~_
Module Package Diagrams
SEMICONDUCTOR
56-Pin ZIP Module PZ07
.125/.175
t
2.750 REF - - - - - - - + 1
-I 1-
.100 REF
64-Pin ZIP Module PZ08
RAMS (CAPACITORS UNDERNEATH)
CHAMFER
3MAX195 MAXl
nr.m.1fI]rmrmJi.nrum••••m,~Jmf!:------'L
PIN 1
.125/.175
JL
.090/.110
.135/.165
72-Pin Plastic ZIP Module PZ09
I'
3.85,"AX
'1350
"AXl
r
~~~~~,
~~~~
MAX
o~~o:JI,
......
.
. ....
3d ~:'50
(72
14-86
J
L.100
TYP.
,I
.575
~
.090/.UOJ
L
~
.
i~PRESS
,
Module Package Diagrams
SEMICONDUCTOR
64-Pin ZIP Module PZIO
r - - - - - - - 3150 (64 PINS)
PIN 1
•
14-87
~CYPRKSS
~;.
Sales Representatives and Distributors
SEMICONDUCTOR
Domestic Direct Sales Offices
Corporate Headquarters
Cypress Semiconductor
3901 N. First Street
San Jose, CA 95134
(408) 943-2600
Thlex: 821032 CYPRESS SNJ UD
TWX: 910 997 0753
FAX: (408) 943-2741
Alabama
Cypress Semiconductor
555 Sparkman Drive, Ste. 1212
Huntsville, AL 35816
(205) 721-9500
FAX: (205) 721-0230
California
Northwest Sales Office
Cypress Semiconductor
3901 N. First Street
San Jose, CA 95134
(408) 943-4867
FAX: (408) 943-6860
Cypress Semiconductor
23586 Calabasas Rd., Ste. 201
Calabasas, CA 91302
(818) 222-3800
FAX: (818) 222-3810
Cypress Semiconductor
2 Venture Plaza, Suite 460
Irvine, CA 92718
(714) 753-5800
FAX: (714) 753-5808
Cypress Semiconductor
12526 High Bluff Dr., Ste. 300
San Diego, CA 92130
(619) 755-1976
FAX: (619) 755-1969
Canada
Cypress Semiconductor
701 Evans Avenue
Suite 312
Toronto, Ontario M9C 1A3
(416) 620-7276
FAX: (416) 620-7279
Colorado
Cypress Semiconductor
4704 Harlan St., Suite 360
Denver, CO 80212
(303) 433-4889
FAX: (303) 433-0398
Florida
Cypress Semiconductor
10014 N. Dale Mabry Hwy. 101
Thmpa, FL 33618
(813) 968-1504
FAX: (813) 968-8474
Cypress Semiconductor
255 South Orange Avenue
Suite 1255
Orlando, FL 32801
(407) 422-0734
FAX: (407) 422-1976
Georgia
Cypress Semiconductor
1080 Holcomb Bridge Rd.,
Building 100, Suite 300
Roswell, GA 30076
(404) 998-0491
FAX (404) 998-2172
Illinois
Cypress Semiconductor
1530 E. Dundee Rd., Ste. 190
Palatine, IL 60067
(708) 934-3144
FAX: (708) 934-7364
Maryland
Cypress Semiconductor
8850 Stanford Blvd., Suite 1600
Columbia, MD 21045
(410) 312-2911
FAX: (410) 290-1808
Minnesota
Cypress Semiconductor
14525 Hwy. 7, Ste. 360
Minnetonka, MN 55345
(612) 935-7747
FAX: (612) 935-6982
New Hampshire
Cypress Semiconductor
61 Spit Brook Road, Ste. 110
Nashua, NH 03060
(603) 891-2655
FAX: (603) 891-2676
New Jersey
Cypress Semiconductor
35 Bailey Hollow Road
Morristown, NJ 07960
(201) 267-6773
FAX: (201) 267-6599
New York
Cypress Semiconductor
244 Hooker Ave., Ste. B
Poughkeepsie, NY 12603
(914) 485-6375
FAX: (914) 485-7103
North Carolina
Cypress Semiconductor
7500 Six Forks Rd., Suite G
Raleigh, NC 27615
(919) 870-0880
FAX: (919) 870-0881
Oregon
Cypress Semiconductor
8196 S.w. Hall Blvd. Suite 100
Beaverton, OR 97005
(503) 626-6622
FAX: (503) 626-6688
Pennsylvania
Cypress Semiconductor
Tho Neshaminy Interplex, Ste. 206
Trevose, PA 19053
(215) 639-6663
FAX: (215) 639-9024
Texas
Cypress Semiconductor
333 West Campbell Rd., Ste. 240
Richardson, TX 75080
(214) 437-0496
FAX: (214) 644-4839
Cypress Semiconductor
Great Hills Plaza
9600 Great Hills 'frail, Ste. 150W
Austin, TX 78759
(512) 502-3023
FAX: (512) 338-0865
Cypress Semiconductor
20405 SH 249, Ste. 216
Houston, TX 77070
(713) 370-0221
FAX: (713) 370-0222
Virginia
Cypress Semiconductor
3151C Anchorway Court
Falls Church, VA 22042
(703) 849-1733
FAX: (703) 849-1734
~
.
·~PRFSS
?
Sales Representatives and Distributors
SEMICONDUCTOR
Domestic Sales Representatives
Alabama
Giesting & Associates
4835 University Square
Suite 15
Huntsville, AL 35816
(205) 830-4554
FAX: (205) 830-4699
Arizona
Thorn Luke Sales, Inc.
9700 North 91st St., Suite A - 200
Scottsdale, AZ 85258
(602) 451-5400
FAX: (602) 451-0172
California
TAARCOM
451 N. Shoreline Blvd.
Mountain View, CA 94043
(415) 960-1550
FAX: (415) 960-1999
TAARCOM
735 Sunrise Ave., Suite 200
Roseville, CA 95661
(916) 782-1776
FAX: (916) 782-1786
Canada
bbd Electronics, Inc.
6685 -1 Millcreek Dr.
Mississauga, Ontario LSN 5M5
(416) 821-7800
FAX: (416) 821-4541
bbd Electronics, Inc.
298 Lakeshore Rd., Ste. 203
Pointe Claire, Quebec H9S 4L3
(514) 697-0801
FAX: (514) 697-0277
bbd Electronics, Inc. - Ottawa
(613) 564-0014
FAX: (416) 821 - 4092
bbd Electronics, Inc. - Winnipeg
(204) 942-2977
FAX: (416) 821-4092
Western Canada
Microwe Electronics Corporation
5330 Wallace Avenue
Delta, British Columbia V4M 1A1
(604) 943-5020
FAX: (604) 943-8184
Connecticut
HLM
3 Pembroke Rd.
Danbury, CT 06810
(203) 791-1878
FAX: (203) 791-1876
Florida
CM Marketing
252 Springs Colony Circle, Unit 382
Altamonte Springs, FL 32714
(407) 682-7709
FAX: (407) 682-7995
CM Marketing
1435-C Gulf to Bay Blvd.
Clearwater, FL 34615
(813) 443-6390
FAX: (813) 443-6312
CM Marketing
664 Hollows Circle
Deerfield Beach, FL 33442
(305) 429-8626
FAX: (305) 429-3440
Georgia
Giesting & Associates
2434 Highway 120
Suite 108
Duluth, GA 30136
(404) 476-0025
FAX: (404) 476-2405
Illinois
Micro Sales Inc.
901 W. Hawthorn Drive
Itasca,IL 60143
(708) 285-1000
FAX: (708) 285-1008
Indiana
Technology Mktg. Corp.
1526 East Greyhound Pass
Carmel, IN 46032
(317) 844-8462
FAX: (317) 573-5472
Technology Mktg. Corp.
4630-10 W. Jefferson Blvd.
Ft. Wayne, IN 46804
(219) 432-5553
FAX: (219) 432-5555
Technology Marketing Corp.
1214 Appletree Lane
Kokomo, IN 46902
(317) 459-5152
FAX: (317) 457-3822
Iowa
Midwest Technical Sales
463 Northland Ave., N.E.
Suite 101
Cedar Rapids, IA 52402
(319) 377 -1688
FAX: (319) 377-2029
Kansas
Midwest Technical Sales
13 Woodward Dr.
Augusta, KS 67010
(316) 775-2565
FAX: (316) 775-3577
Midwest Technical Sales
15301 W. 87 Parkway, Ste. 200
Lenexa, KS 66219
(913) 888-5100
FAX: (913) 888-1103
Kentucky
Technology Marketing Corp.
718 Amhurst Place
Louisville, KY 40223
(502) 245-7411
FAX: (502) 245-4818
Michigan
Techrep
2200 North Canton Center Rd.
Suite 110
Canton, MI 48187
(313) 981-1950
FAX: (313) 981- 2006
Missouri
Midwest Technical Sales
514 Earth City Expwy., #239
Earth City, MO 63045
(314) 298-8787
FAX: (314) 298-9843
Nevada
TAARCOM
735 Sunrise Ave.
Suite 200-4
Roseville, CA 95661
(916) 782-1776
FAX: (916) 782-1786
New Jersey
HLM
333 Littleton Rd.
Parsippany, NJ 07054
(201) 263-1535
FAX: (201) 263-0914
New York
HLM
64 Mariners Lane
P.O. Box 328
Northport, NY 11768
(516) 757-1606
FAX: (516) 757-1636
Reagan/Compar
96 W. Forest Dr.
Rochester, NY 14624
(716) 271-2230
FAX: (716) 381-2840
Reagan/Compar
214 Dorchester Ave., #3C
Syracuse, NY 13203
(315) 432-8232
FAX: (315) 432-8238
Reagan/Compar
3301 Country Club Road
Ste.2211
P.O. Box 8635
Endwell, NY 13760
(607) 754-2171
FAX: (607) 754-4270
Sales Representatives and Distributors
Domestic Sales Representatives (continued)
Ohio
Pennsylvania
KW Electronic Sales, Inc.
8514 North Main Street
Dayton, OH 45415
(513) 890-2150
FAX: (513) 890-5408
L. D. Lowery
2801 West Chester Pike
Broomall, PA 19008
(215) 356-5300
FAX: (215) 356-8710
KW Electronic Sales, Inc.
3645 Warrensville Center Rd. #244
Shaker Heights, OH 44122
(216) 491-9177
FAX: (216) 491-9102
KW Electronic Sales, Inc.
4068 Mt. Royal Blvd., Ste. 110
Allison Park, PA 15101
(412) 492-0777
FAX: (412) 492-0780
Oregon
Northwest Marketing Associates
6975 S. W. Sandburg Rd, Ste. 330
Beaverton, OR 97223
(503) 620-0441
FAX: (503) 684-2541
Puerto Rico
Electronic Technical Sales
P.O. Box 10758
Caparra Heights Station
San Juan, P.R. 00922
(809) 798-1300
FAX: (809) 798-3661
Utah
Sierra Technical Sales
1192 E. Draper Parkway
Suite 103
Draper, UT 84020
(801) 571-8195
FAX: (801) 571-8194
Washington
Northwest Marketing Associates
12835 Bellevue-Redmond, Ste. 330N
Bellevue, WA 98005
(206) 455-5846
FAX: (206) 451-1130
Wisconsin
Micro Sales Inc.
210 Regency Court
~Mite LI01
~aukesha, WI 53186
(414) 786-1403
FAX: (414) 786-1813
..::::P"":' -
'~PRESS
Sales Representatives and Distributors
- , SEMICONDUCTOR
International Direct Sales Offices
Cypress Semiconductor
International-Europe
Avenue Ernest Solvay, 7
B-13lO La Hulpe, Belgium
Tel: (32) 2-652-0270
Telex: 64677 CYPINT B
FAX: (32) 2-652-1504
France
Cypress Semiconductor France
Miniparc Bat. no 8
Avenue des Andes, 6
Z.A de Courtaboeuf
91952 Les Ulis Cedex, France
Tel: (33) 1-69-07-55-46
FAX: (33) 1-69-07-55-71
Germany
Cypress Semiconductor GmbH
Munchner Str. 15A
W-8011, Zorneding, Germany
Tel: (49) 81-06-2855
FAX: (49) 81-06-20087
Italy
Cypress Semiconductor
Via del Poggio Laurentino 118
00144 Rome, Italy
Tel: (39) 65-920-723
FAX: (39) 65-921-577
Cypress Semiconductor
Interporto di Torino
Proma Strada n. 51B
10043 Orbassano, Italy
Tel: (39) 11-397-57-98
or (39) 11-397-57-57
FAX: (39) 11-397-58-10
Japan
Cypress Semiconductor Japan KK
Fuchu-Minami Bldg., 2F
10-3, l-Chome, Fuchu-machi,
Fuchu-shi, Tokyo, Japan 183
Tel: (81) 423-69-82-11
FAX: (81) 423-69-82-10
Sweden
Cypress Semiconductor
Scandinavia AB
Taby Centrum, Ingang S
S-18311 Taby, Sweden
Tel: (46) 8 638 0100
FAX: (46) 8 792 1560
United Kingdom
Cypress Semiconductor U.K, Ltd.
3, Blackhorse Lane, Hitchin,
Hertfordshire, U.K, SG4 9EE
Tel: (44) 462-42-05-66
FAX: (44) 462-42-19-69
Cypress Semiconductor Manchester
27 Saville Rd. Cheadle
Gatley, Cheshire, U.K
Tel: (44) 614-28-22-08
FAX: (44) 614-28-0746
Cypress Semiconductor GmbH
Buro Nord
Matthias-Claudius-Str. 17
W - 2359 Henstedt-Ulzburg, Germany
Tel: (49) 4193-77217
FAX: (49) 4193-78259
International Sales Representatives
Australia
Braemac Pty. Ltd.
Unit 6,111 Moore St.
Leichhardt, N.S.W. 2040, Australia
Tel: (61) 2-564-1211
FAX: (61) 2-564-2789
Braemac Pty. Ltd.
10-12 Prospect Street, Box Hill
Melbourne, Victoria, 3128, Australia
Tel: (61) 3-899-1272
FAX: (61) 3-899-1276
Austria
Hitronik Vertriebsge GmbH
St. Veitgasse 51
A -1130 Wien, Austria
Tel: (43) 1-877-4199
Telex: 133404 HIT A
FAX: (43) 1-876-55-72
Belgium
Sonetech
Limburg Stirum 243
1810 Wemmel, Limburg
Tel: (32) 2-460-0707
FAX: (32) 2-460-1200
Denmark
Avnet Nortec
Transformervej 17
DK-2730 Herlev, Denmark
Tel: (45) 42-84-20-00
Telex: 35200 NORDEL DK
FAX: (45) 44-92-15-52
France
Arrow Electronics
73179, Rue des Solets
Silic 585
94653 Rungis Cedex
Tel: (33) 1 49 78 49 00
FAX: (33) 1 49 78 05 99
Arrow Electronics
Les Jardins d'Entreprises
BetimentB3
213, Rue Gerland
69007 Lyon
Tel: (33) 78 72 79 42
FAX: (33) 78 72 80 24
Arrow Electronics
Centreda
Avenue Didier Daurat
31700 Blagnac
Tel: (33) 61 15 75 18
FAX: (33) 61 30 01 93
Arrow Electronics
Immeuble St. Christophe
Rue de la Frebardiere
ZiSudEst
35135 Chantepie
Tel: (33) 99417044
FAX: (33) 99 50 11 28
Newtek
Rue de I.:Esterel, 8, Silic 583
F-94663 Rungis Cedex, France
Tel: (33) 1-46-87 - 22-00
Telex: 263046 F
FAX: (33) 1-46-87-80-49
Newtek
Rue de l'Europe, 4
Zac Font- Ratel
38640 Claix, France
Tel: (33) 16-76-98-56-01
FAX: (33) 16-76-98-16-04
Scaib, SA
80 Rue d'Arcueil Silic 137
9 4523 Rungis, Cedex, France
Tel: (33) 1-46-87-23-13
FAX: (33) 1-45-60-55-49
Germany
API Electronik GmbH
Lorenz- Brarenstr 32
W-8062 Markt, Indersdorf
Germany
Tel: (49) 8136 7092
Telex: 527 0505
FAX: (49) 8136 7398
Sales Representatives and Distributors
International Sales Representatives (continued)
Metronik GmbH
Leonhardsweg 2, Postfach 1328
W-8025 Unterhaching,
Germany
Tel: (49) 89 611080
Telex: 17 897434 METRO D
FAX: (49) 89 6116468
Metronik GmbH
Laufamholzstrasse 118
W-85OO Niimberg,
Germany
Tel: (49) 911 544966
Telex: 6 26 205
FAX: (49) 911 542936
Metronik GmbH
LOewenstrasse 37
W -7000 Stuttgart 70
Germany
Tel: (49) 711 764033
Telex: 7-255-228
FAX: (49) 7117655181
Metronik GmbH
Siemensstrasse 4-6
W -6805 Heddesheim, Germany
Tel: (49) 6203 4701
Telex: 465 035
FAX: (49) 6203 45543
Metronik GmbH
Zum Lonnenhohl38
W-46OO Dortmund 13, Germany
Tel: (49) 231 217041
FAX: (49) 231 210799
Metronik GmbH
Buckhomer Moor 81
W-2000 Norderstedt, Germany
Tel: (49) 40 5228091
Telex: 2162488
FAX: (49) 40-522 80 93
Metronik Halle
Thalmannplatz 16/0904
0-4020 Halle, Germany
SASCOGmbH
Hermann-Oberth-Str. 16
8011 Putzbrunn, Germany
Tel: (089) 4611-211
Telex: 529 504 sasco d
FAX: (089) 4611-271
SASCOGmbH
Gibitzenhofstr. 62
8500 Numberg 70, Germany
Tel: (0911) 42 10 65
Telex: 623097
FAX: (0911) 4257 94
SASCOGmbH
Stafflenbergstr.24
7000 Stuttgart 1, Germany
Tel: (0711) 244521
Telex: 723936
FAX: (0711) 23 39 63
SASCOGmbH
Am Gansacker 26
7801 Umkirch bei Freiburg
Tel: (07665) 70 18
Telex: 7722945
FAX: (07665) 87 78
SASCOGmbH
Hainer Weg 48
D-60599 Frankfum, Germany
Tel: (49) 69 61 03 91
Telex: 414435
FAX: (49) 69618824
SASCOGmbH
Beratgerstr. 36
4600 Dortmund 1, Germany
Tel: (0231) 179791
Telex: 8227826
FAX: (0231) 17 29 91
SASCOGmbH
Am Uhrturm7
3000 Hannover 81, Germany
Tel: (0511) 83 90 20
Telex: 921123
FAX: (0511) 8 437618
SASCOGmbH
Europaallee 3
2000 Norderstedt, Germany
Tel: (040) 5 23 20 13
Telex: 2165623
FAX: (040) 5 23 23 78
Hong Kong
Tekcomp Electronics, Ltd.
913-4 Bank Centre
636, Nathan Road, Mongkok
Kowloon, Hong Kong
Tel: (852) 3-880-629
Telex: 38513 TEKHL
FAX: (852) 7-805-871
India
Spectra Innovations Inc.
Manipal Centre, Unit No. S-822
47, Dickenson Rd.
Bangalore- 560,042
Kamataka, India
Tel: 80-588-323
Telex: 845 2696 or 8055
(Attn: ICTP-705)
FAX: 80-586-872
Israel
Thlviton Electronics
P.O. Box 21104, 9 Biltmore Street
Tel Aviv 61 210, Israel
Tel: (972) 3-544-2430
Telex: 33400 VITKO
FAX: (972) 3-544-2085
Italy
Dott. Ing. Guiseppe De Mico s.p.a.
V. Le Vittorio Veneto, 8
1-20060 Cassina d'Pechi
Milano, Italy
Tel: (39) 29-53-43-600
Telex: 330869 DEMICO I
FAX: (39) 29-52-19-12
Silverstar Ltd. SPA
Viale Fulvio Testi, 280
20126 Milano, Italy
Tel: (39) 2 661251
Teles: 33 2189 SIL 71
FAX: (39) 2 66101359
Japan
Tomen Electronics Corp.
2-1-1 Uchisaiwai-Cho, Chiyoda-Ku
Tokyo, 100 Japan
Tel: (81) 3-3506-3673
Telex: 23548 TMELCA
FAX: (81) 3-3506-3497
CTC Components Systems Co. Ltd.
4-8-1,1Suchihashi,
Miyamae- Ku, Kawasaki -Shi,
Kanagawa, 213 Japan
Tel: (81) 44-852-5121
Telex: 3842272 CTCEC J
FAX: (81) 44-877-4268
Fuji Electronics Co., Ltd.
Ochanomizu Center Bldg.
3-2-12 Hongo, Bunkyo-Ku
Tokyo, 113 Japan
Tel: (81) 3-3814-1411
Telex: J28603 FUJITRON
FAX: (81) 3-3814-1414
N.D.A. Co. Ltd.
The Second Preciza Bldg.
4-8-3 Iidabashi Chiyoda-Ku
Tokyo, 102 Japan
Tel: (81) 3-3264-1321
Telex: J29503 lSI JAPAN
FAX: (81) 3-3264-3419
Fujitsu Devices, Inc.
Osaki West Bldg.
8-8, Osaki 2-Chome,
Shinagawa - ku
Tokyo 141, Japan
Tel: (81) 3-3490-3321
FAX: (81) 3-3490-7274
Japan Electronics
Materials Co., Ltd (JEMCO)
2-20-10 Minamikaneda, Suita-shi,
Osaka 564 Japan
Tel: (81) 6-385-6707
FAX: (81) 6-330-6814
Ryoyo Electro Corporation
Knowa Bldg., 1-12-22 'Thukiji,
Chuo-ku, Tokyo 104 Japan
Tel: (81) 3-5565-1531
FAX: (81) 3-5565-1546
Korea
Logicom Inc.
1634-9 Bongchun-Dong
Kwanak-ku
Seoul, Korea 151-061
Tel: (822) 888-2858
FAX: (822) 888-7040
superCHIP Inc.
5th Floor, Sunjin Bldg. 82-8
Yangjae-dong, Seocho-ku
Seoul, Korea 137 -130
Tel: (02) 576-2111
FAX: (02) 576-2177
~·~PRFSS
-iF
Sales Representatives and Distributors
SEMICONDUCTOR
International Sales Representatives (continued)
Netherlands
Sonetech B.Y.
Gulberg 33, NL-5674
TeNuenen
The Netherlands
Tel: (31) 40-83-70-75
Telex: 59418 INTRA NL
FAX: (31) 40-83-23-00
Norway
Avnet Nortec Electronics NS
Smedsvingen 4, P.O. Box 123
N -1364 Hvalstad, Norway
Tel: (47) 66-84-62-10
Telex: 77546 NENAS N
FAX: (47) 66-84-65-45
Singapore
Electec PTE Ltd.
Block 50, Kallang Bahru
#04-21, Singapore 1233
Tel: (65) 294-8389
FAX: (65) 294-7623
Spain
AID Electronica
Avda. de la Industria No. 32
Nave 17, 2B, 28100 A1cobendas
Madrid, Spain
Tel: (34) 1-66-16-551
FAX: (34) 1-66-16-300
AID Electronica, Lda.
Edificio A1tejo
Rua 3 piso 5th sala 505
Urbanizacao da Matinha
1900 Lisboa, Portugal
Tel: (351) 1-858-0191/2
FAX: (351) 1-858-7841
AID Electronica
Comte Borrell, 208-1
08029 Barcelona, Spain
Tel: (93) 451-58-93
FAX: (93) 451-40-70
Sweden
TH:s Elektronik AB
P.O. Box 3027
Arrendevagen 36
S163 03 SPANGA, Sweden
Tel: (46) 8 362 970
Telex: 111 45 tenik s
FAX: (46) 8 761 3065
Switzerland
Basix flir Elektronik A. G.
Hardturrnstrasse 181
CH-8010 Zurich, Switzerland
Tel: (41) 1-276-11-11
Telex: 822762 BAEZ CH
FAX: (41) 1-276-14-48
Taiwan R.O.C.
Prospect Technology Corp.
5F, No. 348, Section 7
Cheng-Teh Rd.
Thipei, Taiwan
Tel: (886) 2-820-5353
Telex: 14391 PROSTECH
FAX: (886) 2-820-5731
United Kingdom
Ambar Components Ltd.
17 Thame Park Road
Thame, Oxfordshire
England, OX9 3XD
Tel: (44) 844-26-11-44
Telex: 837427
FAX: (44) 844-26-17-89
Arrow Electronics (UK) Ltd.
St. martins Business Centre
Cambridge Road
Bedford MK42 OLF, u.K.
Tel: (44) 234 270272
FAX: (44) 234 214674
Pronto Electronic System Ltd.
City Gate House
Eastern Avenue, 399-425
Gants Hill, liford,
Essex, U. K IG2 6LR
Tel: (44) 81-554-62-22
Telex: 8954213 PRONTO G
FAX: (44) 81-518-32-22
· -;~PRFSS
-=-,
Sales Representatives and Distributors
SEMICONDUcrOR
Distributors
Arrow Electronics:
Alabama
Huntsville, AL 35816
(205) 837-6955
Arizona
Tempe, AZ 85282
(602) 431-0030
California
Calabasas, CA 91302
(818) 880-9686
San Diego, CA 92123
(619) 565-4800
San Jose, CA 95131
(408) 441-9700
San Jose, CA 95134
Tustin, CA 92680
(714) 587-0404
Canada
Mississauga, Ontario L5T IMA
(416) 670-7769
Dorval, Quebec H9P 2T5
(514) 421-7411
Neapean, Ontario K2E 7W5
(613) 226-6903
Quebec City, Quebec G2E 5RN
(418) 871-7500
Burnaby, British Columbia V5A 4T8
(604) 421-2333
Florida (continued)
Lake Mary, FL 32746
(407) 333-9300
Georgia
Deluth, GA 30071
(404) 497-1300
Illinois
Itasca, IL 60143
(708) 250-0500
Indiana
Indianapolis, IN 46268
(317) 299-2071
Kansas
Lenexa, KS 66214
(913) 541-9542
Maryland
Columbia, MD 21046
(410) 596-7800
Gathersburg, MD
(301) 596-7800
Massachusetts
Wilmington, MA 01887
(617) 658-0900
Michigan
Livonia, MI 48152
(313) 462-2290
Minnesota
Eden Prairie, MS 55344
(612) 941-5280
Colorado
Englewood, CO 80112
(303) 799-0258
Missouri
St. Louis, MO 63146
(314) 567-6888
Connecticut
Wallingford, CT 06492
(203) 265-7741
New Jersey
Marlton, NJ 08053
(609) 596-8000
Florida
Deerfield Beach, FL 33441
(305) 429-8200
Pinebrook, NJ 07058
(201) 227-7880
New York
Rochester, NY 14623
(716) 427-0300
Haufpauge, NY 11788
(516 231-1000
North Carolina
Raleigh, NC 27604
(919) 876-3132
Ohio
Centerville, OH 45458
(513) 435-5563
Solon, OH 44139
(216) 248-3990
Oklahoma
Tulsa, OK 74146
(918) 252-7537
Oregon
Beaverton, OR 97006-7312
(503) 629-8090
Pennsylvania
Pittsburgh, PA 15238
(412) 963-6807
Texas
Austin, TX 78758
(512) 835-4180
Carrollton, TX 75006
(214) 380-6464
Houston, TX 77099
(713) 530-4700
Washington
Bellevue, WA 98007
(206) 643-9992
Spokane, WA 99206-6606
(509) 924-9500
Wisconsin
Brookfield, WI 53045
(414) 792-0150
==r:. c~
_'.i!lCYPRESS
Sales Representatives and Distributors
- , SEMICONDUCTOR
Distributors (continued)
Marshall Industries:
Alabama
Huntsville, AL 35801
(205) 881-9235
Arizona
Phoenix, AZ 85044
(602) 496-0290
California
Marshall Industries, Corp. Headquarters
El Monte, CA 91731-3004
(818) 307 -6000
Irvine, CA 92718
(714) 458-5301
Calabasas, CA 91302
(818) 878-7000
Rancho Cordova, CA 95670
(916) 635-9700
San Diego, CA 92123
(619) 627-4140
Milpitas, CA 95035
(408) 942-4600
Canada
Brampton, Ontario L6T 5G3
(416) 458-8046
Ottawa, Ontario
(613) 564-0166
Pointe Claire, Quebec H9R 5P9
(514) 694-8142
Florida (continued)
Altamonte Springs, FL 32701
(407) 767-8585
St. Petersburg, FL 33716
(813) 573-1399
Georgia
Norcross, GA 30093
(404) 923-5750
Illinois
Schaumbrug, IL 60173
(708) 490-0155
Indiana
Indianapolis, IN 46278
(317) 297 -0483
Kansas
Lenexa, KS 66214
(913) 492-3121
Maryland
Silver Springs, MD 20904
(301) 622-1118
Massachusetts
Wilmington, MA 01887
(508) 658-0810
Michigan
Livonia, MI 48150
(313) 525-5850
Minnesota
Plymouth, MN 55447
(612) 559-2211
Colorado
Thornton, CO 80241
(303) 451-8383
Missouri
Bridgeton, MO 63044
(314) 291-4650
Connecticut
Wallingford, CT 06492-0200
(203) 265-3822
New Jersey
Fairfield, NJ 07006
(201) 882-0320
Florida
Ft. Lauderdale, FL 33309
(305) 977-4880
Mt. Laurel, NJ 08054
(609) 234-9100
New York
Endicott, NY 13760
(607) 785 - 2345
Hau)page, NY 11788
(516 273-2695
Rochester, NY 14624
(716) 235-7620
North Carolina
Raleigh, NC 27604
(919) 878-9882
Ohio
Solon, OH 44139
(216) 248-1788
Dayton, OH 45414
(513) 898-4480
Oregon
Beaverton, OR 97005
(503) 644-5050
Pennsylvania
Mt. Laurel, NJ 08054
(609) 234-9100
Texas
Austin, TX 78754
(512) 837-1991
Richardson, TX 75081
(214) 705-0600
Houston, TX 77043
(713) 467 -1666
Utah
Salt Lake City, UT 84119
(801) 973-2288
Washington
Bothell, WA 98011
(206) 486-5747
Wisconsin
Waukesha, WI 53186
(414) 797-8400
~PRRSS
Sales Representatives and Distributors
,nCONDUcrOR
Distributors (continued)
Semad:
Calgary
Calgary, Alberta T2H 2S8
(403) 252-5664
FAX: (800) 565-9779
Anthem Electronics, Inc.:
Tempe, AZ 85281
(602) 966 - 6600
Zeus Electronics:
Yorba Linda, CA 92686
(714) 921-9000
Chatsworth, CA 91311
(818) 775 -1333
San Jose, CA 95131
(408) 629-4789
Montreal
Pointe Claire, Quebec H9R 427
(514) 694-0860
1-800-361-6558
FAX: (514) 694-0965
East Irvine, CA 92718
(714) 768-4444
Lake Mary, FL 32746
(407) 333-3055
Rocklin, CA 95677
(916) 624-9744
Wilmington, MA 01887
(508) 658-4776
Ottawa
Ottawa, Ontario KlB lA7
(613) 526-4866
PAX: (613) 523-4372
San Jose, CA 95131
(408) 453 -1200
Port Chester, NY 10573
(914) 937-7400
San Diego, CA 92121
(619) 453-9005
Carrollton, TX 75006
(214) 380-4330
Toronto
Markham, Ontario L3R 4Z4
(416) 475-3922
PAX: (416) 475-4158
Vancouver
Burnaby, British Columbia V5G 4Ml
(604) 451-3444
1-800-663-8956
FAX: (604) 451-3445
Englewood, CO 80112
(303) 790-4500
Waterbury, CT 06705
(203) 575 -1575
Altamonte Springs, FL 32701
(407) 831-0007
Schaumburg, IL 60173
(708) 884-0200
Wilmington, MA 01887
(508) 657-5170
Falcon Electronics:
Milford, CT 06460
(203) 878-5272
Columbia, MD 21046
(301) 995-6640
Eden Prairie, MN 55344
(612) 944-5454
Winter Park, FL 32792
(407) 671-3739
Pine Brook, NJ 07058
(201) 227-7960
Hauppauge, LI, NY 11788
(516) 724-0980
Commack, NY 11725
(516) 864-6600
Beaverton, OR 97005
(503) 643-1114
Horsham, PA 19044
(215) 443-5150
Richardson, TX 75081
(214) 238-7100
Salt Lake City, UT 84119
(801) 973-8555
Bothel, WA 98011
(206) 483-1700
Cypress Semiconductor
3901 North First Street
San Jose, CA 95134
(408) 943-2600
1-8930BOOK 80000
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