1993_Intel_Embedded_Microcontrollers_and_Processors_Volume_1 1993 Intel Embedded Microcontrollers And Processors Volume 1
User Manual: 1993_Intel_Embedded_Microcontrollers_and_Processors_Volume_1
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EMBEDDED
MICROCONTROLLERS
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VOLUME I
1993
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intaL
MCS® ..48 Single Component
System
MCS® .. 48 Expanded System
MCS® .. 48 Instruction Set
MCS® .. 48 Data Sheets
MCS® .. 51 Architectural
Overview
MCS® .. 51 Programmer's Guide
and Instruction Set
MCS® .. 51 Hardware
Descriptions and Data Sheets
8XC51FX Hardware
Description and Data Sheets
8XC51 GB Hardware
Description and Data Sheets
int:et
83ClS2 Hardware
Description and Data Sheet
MCS® .. Sl Development
Support Tools
RUPI.. 44 Family
MCS® .. 80/8S Data Sheets
MCS® .. 96 Architectural
Overview and Quick References
•
8X9X Data Sheets
•
8XC196KBDataSheets
..
~
8XC 1 96KC Data Sheet
8XC196KD Data Sheets
II
int:et
8XC196KRDataSheet
•
8XCI96NT/8XCI96NQand
8XC 196KT Data Sheets
•
8XC 196MC Data Sheet
MCS® .. 96 Development
Support Tools
.
MCS® .. 51 and MCS .. 96
Packaging Information
80186/188/CI86/CI88
Data Sheets
80186/80188 Development
Support Tools
i3 7 6 ™ Processor and
Peripherals Data Sheets
i3 7 6™ Processor
Development Tools
II
II
III
II
II
•
infel·
CAN 82527 Data Sheet
CAN 82527 Development
Tool
Table of Contents
Alphanumeric Index ................ .-... .............. .....................
xxi
MCS®-48 FAMILY
Chapter 1
MCS®-48 Single Component System ...... ........... ........................
1-1
Chapter 2
MCS®-48 Expanded System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
Chapter 3
MCS®-48 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
3-1
Chapter 4
MCS®-48 DATA SHEETS
8243 MCS-48 Input/Output Expander.. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .
P87 48H/P87 49H/8048AH/8035AHL/8049AH/8039AHLl8050AH/8040AH L
HMOS Single Component 8-Bit Microcontroller .............................
D8748H/D8749H HMOS-E Single-Component 8-Bit Microcontroller .. . . .. . . . . . . .
P8049KB HMOS Single-Component 8-Bit Microcontroller ......................
MCS-48 Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-8
4-21
4-33
4-45
MCS®-51 FAMILY
Chapter 5
MCS-51 Family of Microcontrollers Architectural Overview. . . . . . . . .. . . . . . . . . . . . .
5-1
Chapter 6
MCS-51 Programmer's Guide and Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
Chapter 7
8051,8052 and 80C51 Hardware Description ... ;. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8XC52/54/58 Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
8X5X DATA SHEETS
MCS-51 8-Bit Control-Oriented Microcontrollers 8031 AH/8051 AH/8032AH /
8052AH/8751 H/8751 H-8 . .. . .. . .. .. .. .. .. . .. . .. . .. . .. .. .. . .. . ... . .. . . . . .
8051 AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected
ROM..................................................................
8751 BH Single-Chip 8-Bit Microcontroller with 4 Kbytes of EPROM Program
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8751BH Express..........................................................
8752BH Single-Chip 8-Bit Microcontroller with 8 Kbytes of EPROM Program
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
8752BH Express. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8XC5X DATA SHEETS
80C31BH/80C51BH Express ...............................................
80C51 BHP CHMOS Single-Chip 8-Bit Microcontroller with Protected ROM. . . . . . ..
87C51 /80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcontroller with
4 Kbytes Internal Program Memory . . .. . .. . .. .. . .. . .. .. .. .. . .. . .. . . .. . .. ...
87C51 Express ...........................................................
87C51-20/-3 Commercial/Express 20 MHz CHMOS Microcontroller .............
8XC51 SLlLow Voltage 8XC51SL Keyboard Controller. . . . . . . . . . . . . . .. . . . . . . . ..
87C52/80C52/80C32 CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes
Internal Program Memory ....................................... . . . . . . . ..
87C52/80C52/80C32 Express. .. . .. .. .. . .. . . . .. . . . .. . . . . . .. .. . .. .. .. .. . .. ..
87C52-20/80C52-20/80C32-20 Commercial/Express 20 MHz Microcontroller ....
87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal
Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
87C54/80C54 Express ....................................................
87C54-201-3 80C54-20/-3 Commercial/Express 20 MHz Microcontroller . . . . . . . ..
xvii
7-1
7-37
7-48
7-63
7-73
7-85
7-87
7-99
7-101
7-103
7-117
7-136
7-139
7-153
7-154
7-170
7-172
7-188
7-204
7-206
Table of Contents (Continued)
87C58/80C58 CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes Internal
Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-222
87C58/80C58 Express .................................................... 7-239
87C58-201-3 80C58-201-3 Commercial/Express 20 MHz Microcontroller . . . . . . . .. 7-241
Chapter 8
8XC51 FX Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8XC51FX DATA SHEETS
83C51 FA/80C51 FA Express ...............................................
87C51 FA/83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller with 8
Kbytes Internal Program Memory ....... : . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
87C51 FA Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
87C51 FA-201-3 Commercial/Express 20 MHz CHMOS Microcontroller ..........
87C51 FB/83C51 FB CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes
Internal Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .
87C51 FB-201-3 83C51 FB-201-3 Commercial/Express 20 MHz Microcontroller . . ..
87C51 FC/83C5tFC CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes
Internal Program Memory ......................... i • • • • • • • • • • • • . • • • • • • • ••
87C51 FC/83C51 FC Express .............................................. ,
87C51 FC-201-3 83C51 FC-201-3 Commercial/Express 20 MHz Microcontroller....
8-1
8-44
8-46
8-65
8-68
8-83
8-100
8-115
8-132
8-134
Chapter 9
87C51GB Hardware Description............................................
8XC51GB DATA SHEETS
87C51 GB/83C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller. . .. . . . .
87C51 GB/80C51 GB CHMOS Single-Chip 8-Bit Microcontroller Express. . . . . . . . . .
9-1
9-56
9-78
Chapter 10
83C152 Hardware Description .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1
8XC152JXDATASHEET
.
8XC152JAI JBI JCI JD Universal Communication Controller 8-Bit Microcontroller .. 10-71
Chapter 11
MCS®-51 DEVELOPMENT SUPPORT TOOLS
Development Tools for the MCS-51 Family of Microcontrollers .................. .11-1
ACE51 FX Software. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-7
EV80C51 FX Evaluation Board ............................ . . . . . . . . . . . . . . . . . .
11-8
EV80C51 GX Evaluation Board.. . .. . . .. . . ... . . . . .. . .. . .. .. .. .. .. .. .. .. . .. . .. 11-11
THE RUPI FAMILY
Chapter 12
The RUPI-44 Family: Microcontroller with On-Chip Communication Controller. . . . .
12-1
8044 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
12-9
The RUPI-44 Serial Interface Unit ........................................... 12-19
8044 Application Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-57
8044 DATA SHEET
8044AH/8344AH/8744AH High Performance 8-Bit Microcontrollerwith On-Chip
Serial Communication Controller .......................................... 12-131
MCS®-80/85 FAMILY
Chapter 13
MCS®-80/85 DATA SHEETS
8080Al8080A-1/8080A-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . .
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors . . . . . . . . . . . . . . . . . ..
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and
Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8185/8185-21024 x 8-Bit Static RAM for MCS®-85........... .................
8224 Clock Generator and Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xviii
13-1
13-11
13-31
13-45
13-50
Table of Contents (Continued)
8228 System Controller and Bus Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . .. 13-55
8755A 16,384-Bit EPROM with 1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-59
MCS®·96 FAMILY
Chapter 14
MCS-96 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8X9X Quick Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8XC196KB Quick Reference. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8XC196KC Quick Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8XC196KD Quick Reference ...............................................
8XC196KR Quick Reference ...............................................
8XC196KT Quick Reference ................................................
8XC196MCQuick Reference ...............................................
8XC196NT /NQ Quick Reference ............................................
MCS-96 AID Converter Quick Reference .....................................
14-1
14-15
14-40
14-73
14-104
14-134
14-161
14-190
14-224
14-253
Chapter 15
8X9X DATA SHEETS
809XBH/839XBH/879XBH Commercial/Express HMOS Microcontroller.........
8097JF/8397JF/8797JF Commercial/Express HMOS Microcontroller ...........
8098/8398/8798 Commercial/Express HMOS Microcontroller . . . . . . . . . . . . . . . . ..
15-1
15-23
15-42
Chapter 16
8XC196KB DATA SHEETS
80C196KB1 0/83C196KB1 0/80C196KB12/83C196KB12 Commercial/Express
CHMOS Microcontroller. . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . •. . . .
16-1
80C198/83C198/80C194/83C194 Commercial/Express CHMOS Microcontroller. 16-22
8XC196KB/8XC196KB16 Commercial/Express CHMOS Microcontroller . . . . . . . .. 16-38
8XC198 Commercial CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-60
Chapter 17
8XC196KC DATA SHEET
8XC196KC Commercial/Express CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . .
17-1
Chapter 18
8XC196KD DATA SHEETS
8XC196KD/8XC196KD20 Commercial CHMOS Microcontroller . . . . . . . . . . . . . . . . .
18-1
8XL 196KD Commercial CHMOS Microcontroller ...................•.......... 18-26·
Chapter 19
8XC196KR DATA SHEET
8XC196KR/KQ/JR/JQ Commercial/Express CHMOS Microcontroller ...........
19-1
Chapter 20
8XC196NT18XC196NQ AND 8XC196KT DATA SHEETS
8XC196NT/8XC196NQ CHMOS Microcontroller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-1
8XC196KT Commercial CHMOS Microcontroller .............................. 20-33
Chapter 21
, 8XC196MC DATA SHEET
87C196MC Industrial Motor Control Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . .
21-1
Chapter 22
MCS®-96 DEVELOPMENT SUPPORT TOOLS
ICE-196KD/HX In-Circuit Emulator. .. . .. . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . 22-1
ICE-196 KD/PC In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
MCS-96 Software Development Packages.. . . . . . . . . . .. . . .. . . . . . . . . .. . . . . . . . . .
22-9
ApBuilder Programming Package. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . .. 22-12
EV80C196KX/EV8097BH/EV80C196KB/EV80C196KC/EV80C196KD Evaluation
Boards ................................................................ 22-15
EV80C196KR Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22-22
xix
Table of Contents (Continued)
EV80C196MC Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22-24
Chapter 23
MCS®-51 and MCS-96 PACKAGING INFORMATION
MCS-51 and MCS-96 Packaging Information ..... , ..................,..........
23-1
80186/80188 FAMILY
Chapter 24
80186/188/C186/C188 DATA SHEETS
80186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
80C186 CHMOS High Integration 16-Bit Microprocessor....................... 24-59
80C186XL20, 16, 12, 1016-Bit High Integration Embedded Processor ........... 24-128
80C186EA20, 16, 1216-Bit High Integration Embedded Processor .............. 24-174
80C186EB-20 ,-16, -13, -8, 16-Bit High-Integration Embedded ProceSsor ......... 24-227
80C186EC-16, -13 16-Bit High-Integration Embedded Processor ................ 24-283
80l186EA816-Bit High Integration Embedded Processor ...................•.. 24-338
80L 186EB"13, -8, 16-Bit High-Integration Embedded Processor .•............... 24-366
80C187 80-Bit Math Coprocessor ........................................... 24-390
80188 High Integration 8-Bit Microprocessor ................•............•.... 24-420
80C188 CHMOS High Integration 16-Bit Microprocessor ...................... ; 24-479
80C188XL20, 16, 12, 10 16-Bit High Integration Embedded Processor ........... 24-551
80C188EA20, 16, 12 16-Bit High Integration Embedded Processor .............. 24-597
80C188EB-20, -16, -13, -8 16-Bit High-Integration Embedded Processor .......... 24-649
80C188EC-16, -13 16-Bit High-Integration Embedded Processor .............•.. 24-704
80l188EA816-Bit High Integration Embedded Processor ...................•.. 24-761
80l188EB-13, -8, 16-Bit High-Integration Embedded Processor ...........•..... 24-788
82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors ....... 24-812
Chapter 25
80186/80188 DEVELOPMENT SUPPORT TOOLS
ICE-186/188 Family In-Circuit Emulator ......... , . .. . . . . . .. . . . . . .. . . .. . . ... ..
8086/80C186 Software Development Tools. . . . . . . . . . . . . . . . .. . . . . . . . . . • . . . . . •
EV80C186EAlXL Evaluation Board .... .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
. EV80C186EB Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV80C186EC Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . ..
DB86A Artic Software Debugger ............................................
25-1
25-8
25-13
25-16
25-19
25-21
i376™ EMBEDDED PROCESSOR
Chapter 26
i376TM PROCESSOR AND PERIPHERALS DATA SHEETS
376. High Performance 32-Bit Embedded Processor ..............•..........•.
Intel387 SXMath CoProcessor ...•............ ~ . . . . . . . . . . . . . . . . . . . . . . . . • . . ..
82355 Bus Master Interface Controller.(BMIC) '.. . . .. . . . . . .. . . . . . . . . . . . . . . . . . ..
82370 Integrated System Peripheral . . . . . . . . .. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . ..
82596DX and 82596SX High-Performance 32-Bit Local Area Network'
Coprocessor .............................................................
26-1
26-96
26-97
26-98
26-99
Chapter 27
i376TM PROCESSOR DEVELOPMENT TOOLS
Intel386 and Intel486 Family Development Support.. . . . . .. .. .. . . . . . . . . . . . ... . .
TRANS 186-376 Assembly Code Translator..................................
27-1
27-9
CAN 82527 CONTROLLER
Chapter 28
82527 DATA SHEET
Serial Communications Controller (Controller Area Network Protocol) . . . . . . . . . . . .
28-1
Chapter 29
82527 DEVELOPMENT TOOL
EV82527 Evaluation Kit.....................................................
xx
29-1
Alphanumeric Index
376 High Performance 32-Bit Embedded Processor. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
26-1
80186 High Integration 16-Bit Microprocessor.......................................
24-1
80188 High Integration 8-Bit Microprocessor ........................................ 24-420
8044 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-57
8044 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-9
8044AH/8344AH/8744AH High Performance 8-Bit Microcontroller with On-Chip Serial
Communication Controller ...................................................... 12-131
8051, 8052 and 80C51 Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
8051AHP MCS-51 Family 8-Bit Control-Oriented Microcontroller with Protected ROM. . . . .
7-63
8080A/8080A-1 /8080A-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . .. 13-11
8086/80C186 Software Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8
8097 JF /8397 JF /8797 JF Commercial/Express HMOS Microcontroller . . . . . . . . . . . . . . . . .. 15-23
8098/8398/8798 Commercial/Express HMOS Microcontroller ........................ 15-42
809XBH/839XBH/879XBH Commercial/Express HMOS Microcontroller................
15-1
80C186 CHMOS High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24-59
80C186EA20, 16, 12 16-Bit High Integration Embedded Processor ..................... 24-174
80C186EB-20 ,-16, -13, -8, 16-Bit High-Integration Embedded Processor ................ 24-227
80C186EC-16, -13 16-Bit High-Integration Embedded Processor ....................... 24-283
80C186XL20, 16, 12, 10 16-Bit High Integration Embedded Processor .................. 24-128
80C187 80-Bit Math Coprocessor .................................................. 24-390
80C188 CHMOS High Integration 16-Bit Microprocessor .............................. 24-479
80C188EA20, 16, 12 16-Bit High Integration. Embedded Processor ..................... 24-597
80C188EB-20, -16, -13, -816-Bit High-Integration Embedded Processor ................ 24-649
80C188EC-16, -13 16-Bit High-Integration Embedded Processor ....................... 24-704
80C188XL20, 16, 12, 10 16-Bit High Integration Embedded Processor .................. 24-551
80C196KB1 0/83C196KB1 0/80C196KB12/83C196KB12 Commercial/Express CHMOS
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1
80C198/83C198/80C194/83C194 Commercial/Express CHMOS Microcontroller. . . . . . .. 16-22
80C31BH/80C51BH Express ...................................................... 7-101
80C51 BHP CH MOS Single-Chip 8-Bit Microcontroller with Protected ROM .............. 7-103
80L 186EA8 16-Bit High Integration Embedded Processor ............................. 24-338
80L 186EB-13, -8, 16-Bit High-Integration. Embedded Processor ........................ 24-366
80L 188EA8 16-Bit High Integration Embedded Processor ............................. 24-761
80L 188EB-13, -8, 16-Bit High-Integration Embedded Processor ........................ 24-788
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer.. 13-31
8185/8185-21024 x 8-Bit Static RAM for MCS®-85 .................................. 13-45
82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors .............. 24-812
8224 Clock Generator and Driver fOi 8080A CPU. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 13-50
8228 System Controller and Bus Driver for 8080A CPU ............................... 13-55
82355 Bus Master Interface Controller (BMIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 26-97
82370 Integrated System Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 26-98
8243 MCS-48 Input/Output Expander. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
4-1
82596DX and 82596SX High-Performance 32-Bit Local Area Network Coprocessor ...... 26-99
83C152 Hardware Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
83C51 FAl80C51 FA Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
8751 BH Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . 7-85
8751 BH Single-Chip 8-Bit Microcontroller with 4 Kbytes of EPROM Program Memory. . . ..
7-73
8752BH Express................................................................. 7-99
8752BH Single-Chip 8-Bit Microcontroller with 8 Kbytes of EPROM Program Memory. . . . . 7-87
8755A 16,384-Bit EPROM with I/O ................................................. 13-59
87C196MC Industrial Motor Control Microcontroller ........ . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
87C51 Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .... 7-136
87C51-20/-3 Commercial/Express 20 MHz CHMOS Microcontroller .......... , . . . . . .... 7-139
xxi
Alphanumeric Index (Continued)
. 87C51 /80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcontroller with 4 Kbytes
Internal Program Memory . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-117
87C51 FA Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 8-65
87C51 FA-20/-3 Commercial/Express 20 MHz CHMOS Microcontroller ................. 8-68
87C51 FAl83C51 FAl80C51 FA CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes
Internal Program Memory .................' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
87C51 FB-20/ -3 83C51 FB-20/ -3 Commercial/Express 20 MHz Microcontroller .......... 8-100
87C51 FB/83C51 FB CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal
Program Memory ............................................................... 8-83
87C51 FC-20/-3 83C51 FC-20/ -3 Commercial/Express 20 MHz Microcontroller .......... 8-134
87C51 FC/83C51 FC CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes Internal
Program Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-115
87C51 FC/83C51 FC Express ...................................................... 8-132
87C51GB Hardware Description................... ................................
9-1
87C51GB/80C51GB CHMOS Single-Chip 8-BitMicrocontrolier Express.............. ..
9-78
9-56
87C51GB/83C51GB/80C51GB CHMOS Single-Chip 8-Bit Microcontroller ..............
87C52-20/80C52-20/80C32-20 Commercial/Express 20 MHz Microcontroller . . . . . . . . . .. 7-172
87C52/80C52/80C32 CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes Internal
Program Memory.............................................................. 7-154
87C52/80C52/80C32 Express .................................................... 7-170
87C54-20/-3 80C54-20/-3 Commercial/Express 20 MHz Microcontroller. . . . . . . . . . . . . . .. 7-206
87C54/80C54 CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal Program
Memory...................................................................... 7-188
87C54/80C54 Express........................................................... 7-204
87C58-20/ -3 80C58-20/ -3 Commercial/Express 20 MHz Microcontroller ............... , 7-241
87C58/80C58 CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes Internal Program
Memory .... ;................................................................. 7-222
87C58/80C58 Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. 7-239
8X9X Quick Reference ......................................................... '.' 14-15
8XC152JAIJB/ JC/ JD Universal Communication Controller 8-Bit Microcontroller . . . . . . . .. 10-71
8XC196KB Quick Reference ....................... . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 14-40
8XC196KB/8XC196KB16 Commercial/Express CHMOS Microcontroller. . . . . . . . . . . . . . .. 16-38
17-1
8XC196KC Commercial/Express CHMOS Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8XC196KC Quick Reference ...................................................... 14-73
8XC196KD Quick Reference ...................................................... 14-104
8XC196KD/8XC196KD20 Commercial CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . . . .
18-1
8XC196KR Quick Reference .................' ..................................... 14-134
19-1
8XC196KR/KQ/JR/JQ Commercial/Express CHMOS Microcontroller..................
8XC196KT Commercial CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20-33
8XC196KT Quick Reference ...................................................... 14-161
8XC196'MC Quick Reference ...................................................... 14-190 .
8XC196NT /8XC196NQ CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
8XC196NT /NQ Quick Reference .................................................. 14-224
8XC198 Commercial CHMOS Microcontroller .............................. ; . . . . . . . .. 16-60
8XC51 FX Hardware Description ...................................................
8-1
8XC51 SL/Low Voltage 8XC51 SL Keyboard Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-153
8XC52/54/58 Hardware Description .. ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . 7-37
8XL 196KD Commercial CHMOS Microcontroller . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 18-26
ACE51 FX Software .............................................................. 11-7
ApBuilder Programming Package .................................................. 22-12
D8748H/D8749H HMOS-E Single-Component 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . 4-21
DB86A Artic Software Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25-21
DevelopmentTools for the MCS-51 Family of Microcontrollers.........................
11-1
EV80C186EAlXL Evaluation Board................................................ 25-13
xxii
Alphanumeric Index (Continued)
EV80C186EB Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV80C186EC Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV80C196KR Evaluation Board .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV80C196KX/EV8097BH/EV80C196KB/EV80C196KC/EV80C196KD Evaluation
Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV80C196MC Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV80C51 FX Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EV80C51 GX Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EV82527 Evaluation Kit. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICE-186/188 Family In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICE-196 KD/PC In-Circuit Emulator ................................................
ICE-196KD/HX In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel386 and Intel486 Family Development Support.. ................. ... .............
Intel387 SX Math CoProcessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MCS-48 Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS-51 8-Bit Control-Oriented Microcontrollers 8031 AH/8051 AH/8032AH/8052AHI
8751H/8751H-8 ...............................................................
MCS-51 and MCS-96 Packaging Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS-51 Family of Microcontrollers Architectural Overview............ ................
MCS-51 Programmer's Guide and Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
MCS-96 AID Converter Quick Reference ...........................................
MCS-96 Architectural Overview. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS-96 Software Development Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS®-48 Expanded System ......................................................
MCS®-48 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS®-48 Single Component System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P8049KB HMOS Single-Component 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P87 48H/P87 49H/8048AH/8035AHL/8049AH 18039AHLl8050AH/8040AHL HMOS
Single Component 8-Bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications Controller (Controller Area Network Protocol) . . . . . . . . . . . . . . . . . . .
The RUPI-44 Family: Microcontroller with On-Chip Communication Controller. . . . . . . . . . . .
The RUPI-44 Serial Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TRANS 186-376 Assembly Code Translator.........................................
xxiii
25-16
25-19
22-22
22-15
22-24
11-8
11-11
29-1
25-1
22-6
22-1
27-1
26-96
4-45
7-48
23-1
5-1
6-1
14-253
14-1
22-9
2-1
3-1
1-1
4-33
4-8
28-1
12-1
12-19
27-9
, MCS®--48 Single Component
System
1
intet
THE SINGLE COMPONENT MCS(B;·48 SYSTEM
1.0 INTRODUCTION
•
•
•
•
•
•
•
Section; 2 through S describe in detail the functional characteristics of the 8748H and 8749H EPROM,
8048AH/8049AH/80S0AH ROM, and 8035AHLI
8039AHU8040-AHL CPU only single component microcomputers. Unless otherwise noted, details within these
sections apply to all versions. This chapter is limited to
those functions useful in single-chip implementations of
the MCS~.-48. The Chapter on the Expanded MCS~-48
System discusses functions which allow expansion of
program memory. data memory. and input output capability.
Add With or Without Carry
AND. OR. Exclusive OR
IncrementlDecrement
Bit Complement
Rotate Left. Right
Swap Nibbles
BCD Decimal Adjust
If the operation performed by the ALU results in a value
represented by more than 8 bits (overflow of most significant bit), a Carry Flag is set in the Program Status
Word.
ACCUMULATOR
2.0 ARCHITECTURE
The following sections break the MCS-48 Family into
functional blocks and describe each in detail. The following description will use the 8048AH as the representative
product for the family. See Figure L
The accumulator is the single most important data register
in the processor. being one of the sources of input to the
ALU and often the destination of the result of operations
performed in the ALU. Data to and from 110 ports and
memory also normally passes through the accumulator.
2.1 Arithmetic Section
2.2 Program Memory
The arithmetic section of the processor contains the basic
data manipulation functions of the 8048AH and can be
divided into the following blocks:
Resident program memory consists of 1024. 2048. or 4096
words eight bits wide which are addressed by the program
counter. In the 8748H and the 8749H this memory is user
programmable and erasable EPROM; in the 8048AHI
8049AHl8050AH the memory is ROM which is mask
programmable at the factory. The 8035AHUB039AHU
B040AHL has no internal program memory and is used
with external memory devices. Program code is completely interchangeable among the various versions. To
access the upper 2K of program memory in the 8050AH.
and other MCS-48 devices, a select memory bank and a
JUMP or CALL instruction must be executed to cross the
2K boundary.
• Arithmetic Logic Unit (ALU)
• Accumulator
• Carry Flag
• Instruction Decoder
In a typical operation data stored in the accumulator is
combined in the ALU with data from another source on
the internal bus (such as a register or I/o port) and the
result is stored in the accumulator or another register.
There are three locations in Program Memory of special
importance as shown in Figure 2.
The following is more detailed description of the function
of each block.
LOCATION 0
Activating the Reset line of the processor causes the first
instruction to be fetched from location O.
INSTRUCTION DECODER
LOCATION 3
Activating the Interrupt input line of the processor (if
interrupt is enabled) causes a jump to subroutine at location 3.
The operation code (op code) portion of each program
instruction is stored in the Instruction Decoder and con-,
verted to outputs which control the function of each of
the blocks of the Arithmetic Section. These lines control
the source of data and the destination register as well as
the function performed in the ALU.
ARITHMETIC LOGIC UNIT
LOCATION 7
A timer/counter interrupt resulting from timer counter
overflow (if enabled) causes a jump to subroutine at location 7.
The ALU accepts 8-bit data words from one or two sources
and generates an 8-bit result under control of the Instruction Decoder. The ALU can perform the following
functions:
Therefore. the first instruction to be executed after initialization is stored in location O. the first word of an
external interrupt service subroutine is stored in location
3, and the first word of a timer/counter service routines
1-1
l
EXPANSION TO
MORE 110 AND
MEMORY
~
RESIDENT
EPROM ROM
"II
iii
c
iii
=-"
S!?
z
G)
QI
rm
~
QI
:x
(')
0
0
is:
CD
~
QI
"0
:x
0
Z
m
Z
CD
....
N
~
~
--:x
, QI
0
en
:r:o
0'
C')
c
iii"
ea
2
REGISTER
3
TE5T1
REGISTER
4
REGISTER
5
REGISTER
6
iil
3
VCC
REGISTER
7
FlAG 0
~
POWER
{
SUPPLY
PROGRAM SUPPLY
FLAG 1
V
-EE.... .SV (LOW POWER STANDBY) I
TIMER
FlAG
VSS
-----..GND
1
REGISTER
INT
~
0
TEST 0
0
:x
m
REGISTER
REGISTER
CARRY
w
0
0
u
w
0
8 lEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER ,BANK
ACC
Ace BIT
DATA STORE
TEST
RESIDENT
RAM ARRAY
PROM/
INTERRUPT
I
CPU!
EXPANDER MEMORY
STROBE SEPARATE
INITIALIZE
OSCILLATOR
XTAl
ADDRESS
LATCH
STROBE
CYCLE
CLOCK
PROGRAM SINGLE
READ
WRITEMEMORY
STEP
STROBES
ENABLE
-I
is:
(')
en,o,
I
~
00
en
-<
en
-I
m
is:
intel~
SINGLE COMPONENT
is stored in location 7. Program memory can be used to
store constants as well as program instructions. Instructions such as MOVP and MOVP3 allow easy access to
data "lookup" tables.
t SELMB1
2047~TSELMBO
:z:
L[=
0:
i
II.
-
SYSTEM
registers in place of locations 0-7 and are then directly
addressable. This second bank of working registers may
be used as an extension of the first bank or reserved for
use during interrupt service subroutines allowing the registers of Bank 0 used in the main program to be instantly
"saved" by a Bank Switch. Note that if this second bank
is not used, locations 24-31 are still addressable as general
purpose RAM. Since the two RAM pointer Registers RO
and RI are a part of the working register array, bank
switching effectively creates two more pointer registers
(ROland RII) which can be used with RO and RI to easily
access up to four separate working areas in RAM at one
time. RAM locations (8-23) also serve a dual role in that
they contain the program counter stack as explained in
Section 2.6. These locations are addressed by the Stack
Pointer during subroutine calls as well as by RAM Pointer
Registers RO and R I. If the level of subroutine nesting is
less than 8, all stack registers are not required and can be
used as general purpose RAM locations. Each level of
subroutine nesting not used provides the user with two
additional RAM locations.
-0
2048c=:=J
MCS~-48
r--""'
:z::
"'!
il
ILl
~ ~.
o o·
zi
8
7
6
5
4
.
LOCATION 7TIMER INTERRUPT
VECTORS
PROGRAM HERE
(12~ , . . . - - - - - - - .
((255))
LOCATION 3EXTERNAL
INTERRUPT
~I-2
VECTORS
PROGRAM HERE
1
716151413121110 ~ RESET VECTORS
PROGRAM HERE
ADDRESS
USER RAM
32 x 8
(96 x 8)
((224 x 8))
32t-____________
3
o
31
~
BANK 1
WORKING
REGISTERS
8 8
-----Fif- -----AD' ---x
24
'Figure 2. Program Memory Map
23
2.3 Data Memory
8 LEVEL STACK
OR
USER RAM
16 x 8
Resident data memory is organized as 64, 128, or 256 by
8-bits wide in the 8048AH, 8049AH and 8050AH. All
locations are indirectly addressable through either of two
RAM Pointer Registers which reside at address 0 and I
of the register array. In addition, as shown in Figure 3,
the first 8 locations (0-7) of the array are designated as
working registers and are directly addressable by several
instructions, Since these registers are more easily addressed, they are usually used to store frequently accessed
intermediate results. The DJNZ instruction makes very
efficient use of the working registers as program loop
counters by allowing the programmer to decrement and
test the register in a single instruction.
8
7t-----~B~A~NK~0-----i
WORKING
REGISTERS
t------8 R,8- - - x
o -----RO----
I
DIRECTLY
ADDRESSABLE
WHEN BANK 1
IS SELECTED
I
ADDRESSED
INDIRECTLY
THROUGH
R1 OR RO
(RO' OR R1')
I
DIRECTLY
ADDRESSABLE
WHEN BANK 0
IS SELECTED
I
IN ADDITION RO OR R1 (RO' OR R1')
( ) 8049AH. 8749H.
MAY BE USED TO ADDRESS 256
WORDS OF EXTERNAL RAM.
(( )) 8050AH
By executing a Register Bank Switch instruction (SEL
RB) RAM locations 24-31 are designated as the working
Figure 3. Data Memory Map
1-3
intel..
SINGLE COMPONENT MCS®-48 SYSTEM
VCC
VCC
a
INTERNAL
BUS
D
D
FLIP
FLOP
CLK
1/0
PIN
PORTl
AND 2
LOW
IMPEDANCE
PULLDOWN
a
WRITE
PULSE
-=-
IN
4V
VOH
OV
VOH(V)
LOW IMPEDANCE PULLUP
HIGH IMPEDANCE PULLUP
2V
LOW IMPEDANCE PULLDOWN
These graphs are for Informational purposes only and are not guaranteed minimums or maximums.
Figure 4. "Quasi-bidirectional" Port Structure
1·4
4V
VOL
intel .
SINGLE COMPONENT
2.4 Input/Output
MCS~-48
SYSTEM
statically latched output port or non-latching input port.
Input and output lines on this pon cannot be mixed
however.
The 8048AH has 27 lines which can be used for input or
output functions. These lines are grouped as 3 pons of 8
lines each which serve as either inputs. outputs or bidirectional pons and 3 "test" inputs which can alter program sequences when tested by conditional jump
instructions.
As a static pon, data is written and latched using the OUTL
instruction and inputted using the INS instruction. The
INS and OUTL instructions generate pulses on the corresponding RD and WR output strobe lines; however, in
the static port mode they are generally not used. As a
bidirectional port the MOVX instructions are used to read
and write the port. A write to the port generates a pulse
on the WR ou~ line and output data is valid at the
trailing~e of WR. A read of the port generates a pulse
on the RD output line and input data must be valid at the
trailing edge of RD. When not being written or read, the
BUS lines are in a high impedance state. See also sections
7 and 8 in the Expanded MCS-48 System chapter.
PORTS 1 AND 2
Pons I and 2 are each 8 bits wide and have identical
characteristics. Data written to these pons is statically
latched and remains unchanged until rewritten. As input
pons these lines are non-latching. i.e., inputs must be
present until read by an input instruction. Inputs are fully
1TL compatible and outputs will drive one standard 1TL
load.
2.5 Test and INT Inputs
The lines of pons I and 2 are called quasi-bidirectional
because of a special output circuit structure which allows
each line to serve as an input, and output, or both even
though outputs are statically latched. Figure 4 shows
the circuit configuration in detail. Each line is continuously pulled up to VCC through a resistive device of
relatively high impedance.
Three pins serve as inputs and are testable with the~
ditional jump instruction. These are TO, TI, and INT.
These pins allow inputs to cause program branches without
the necessity to load an input port into the accumulator.
The TO, n, and INT pins have other possible functions
as well. See the pin description in Section 3.
2.6 Program Counter and Stack
This pullup is sufficient to provide the source current for
a 1TL high level yet can be pulled low by a standard 1TL
gate thus allowing the same pin to be used for both input
and output. To provide fast switching times in a "0" to
"I" transition a relatively low impedance device is
switched in momentarily (... liS of a machine cycle) whenever a "I" is written to the line. When a "0" is written
to the line a low impedance device overcomes the light
pullup and provides 1TL current sinking capability. Since
the pulldown transistor is a low impedance device a "I"
must first be written to any line which is to be used as an
input. Reset initializes all lines to the high impedance "I"
state.
The Program Counter is an independent counter while the
Program Counter Stack is implemented suing pairs of registers in the Data Memory Array. Only 10, 11, or 12 bits
of the Program Counter are used to address the 1024,
2048, or 4096 words of on-board program memory of the
8048AH, 8049AH, or 8050AH, while the most significant
bits can be used for external Program Memory fetches.
See Figure 5. The Program Counter is initialized to
zero by activating the Reset line.
1~IAwl~I~I~I~I~I~I~I~I~I~1
,
,
It is important to note that the ORL and the ANL are read!
write operations. When executed, the p£ "reads" the
pon, modifies the data according to the instruction, then
"writes" the data back to the pon. The "writing" (essentially an OUTL instruction) enables the low impedance
pull-up momentarily again even if the data was unchanged
from a "1." This specifically applies to configurations
that have inputs and outputs mixed together on the same
port. See also section 8 in the Expanded MCS-48 System
chapter.
r
Conventional Program Counter
• Count. OOOH to 7FFH
• Overflow. 7FFH to OOOH
, Figure 5. Program Counter
An interrupt or CALL to a subroutine causes the contents
of the program counter to be stored in one ofthe 8 register
pairs of the Program Counter Stack as shown in Figure
6. The pair to be used is determined by a 3-bit Stack
Pointer which is part of the Program Status Word (PSW).
BUS
Bus is also an 8-bit port which is a true bidirectional port
with associated input and output strobes. If the bidirectional feature is not needed, Bus can serve as either a
1-5
infel"
SINGLE COMPONENT MCS®-4S SYSTEM
·
paiN TER
the word. The Program Status Word is actually a collection
of flip-flops throughout the machine which can be read or
written as a whole. The ability to write to PSW allows
for easy restoration of machine status after a power down
sequence.
R23
--"'-
111
22
--"-
21
110
20
SAVED IN STACK
I
STACK POINTER
,
19
101
lS
...L
·
100
lS
·•
13
·
·
..;.
psw
000
PC4-7
•
•
MSB
CARRY
AUXILIARY CARRY
FLAG 0
REGISTER BANK SELECT
Figure 7. Program Status Word (PSW)
12
11
The upper four bits of PSW are stored in the Program
Counter Stack with every call to subroutine or interrupt
vector and are optionally restored upon return with the
RETR instruction. The RET return instruction does not
update PSW.
...L
001
LSB
CY
AC
FO
BS
14
...L
010
MSB
16
~
011
So
17
10
9
PCS-ll
RS
PCO-3
LSB
The PSW bit definitions are as follows:
Bits 0-2: Stack Pointer bits (So' S,. S2)
Figure 6. Program Counter Stack
Data RAM locations 8-23 are available as stack registers
and are used to store the Program Counter and 4 bits of
PSW as shown in Figure 6. The Stack Pointer when
initialized to 000 points to RAM locations 8 and 9. The
first subroutine jump or interrupt results in the program
counter contents being transferred to locations 8 and 9 of
the RAM array. The stack pointer is then incremented by
one to point to locations 10 and I I in anticipation of
another CALL. Nesting of subroutines wihtin subroutines
can continue up to 8 times without overflowing the stack.
If overflow does occur the deepest address stored (locations 8 and 9) will be overwritten and lost since the stack
. pointer overflows from I I I to 000. It also underflows from
000 to I I I.
.
The end of a subroutine. which is signalled by a return
instruction (RET or RETR), causes the Stack Pointer to
bl decremented and the contents of the resulting register
pair to be transferred to the Program Counter.
Bit 3:
Bit 4:
Not used (" I" level when read)
Working Register Bank Switch Bit (BS)
Bank a
I = Bank I
a=
Bit 5:
Flag a bit (Fa) user controlled flag which can
be complemented or cleared, and tested with
the conditional jump instruction JFO.
Bit 6:
Auxiliary Carry (AC) carry bit generated by
an ADD instruction. and used by the decimal
adjust instruction DA A .
Bit 7:
Carry (CY) carry flag which indicates that the
previous operation has resulted in overflow of
the accumulator.
2.8 Conditional Branch Logic
The conditional branch logic within the processsor enables
several conditions internal and external to the processor
to be tested by the users program. By using the conditional
jump instruction the conditions that are listed in Table
lean effect a change in the sequence of the program
execution.
2.7 Program Status Word
An 8-bit starus word which can be loaded to and from the
accumulator exists called the Program Status Word
(PSW). Figure 7 shows the information available in
1-6
inteL
SINGLE COMPONENT MCS@,·48 SYSTEM
Table 1
Device Testable
Jump Conditions
(Jump On)
not all
Accumulator
Accumulator Bit
Carry Flag
User Flags (FO, FI)
Timer Overflow Flag
Test Inputs (TO,-'D)
Interrupt Input (INT)
All zeros,
0
-
0
0
zero~
I
I
I
I
I
-
2.9 Interrupt
An interrupt sequence is initiated by applying a low "0"
level input to the INT pin. Interrupt is level triggered and
active low to allow "WIRE DRing" of several interrupt
sources at the input pin. Figure 8 shows the interrupt
logic of the 8048AH. The Interrupt line is sampled every
instruction cycle and when detected causes a "call to
subroutine" at location 3 in program memory as soon as
all cycles of the current instruction are complete. On 2cycle instructions the interrupt line is sampled on the 2nd
cycle only. INT must be held low for at least 3 machine
cycles to ensure proper interrupt operations. As in any
CALL to subroutine,the Program Counter and Program
Status word are saved in the stack. For a description of
this operation see the previous section, Program Counter
and Stack. Program Memory location 3 usually contains
an unconditional jump to an interrupt service subroutine
elsewhere in program memory. The end of an interrupt
service subroutine is signalled by the execution of a Return
and Restore Status instruction RETR. The interrupt system
is single level in that once an interrupt is detected all
further interrupt requests are ignored until execution of an
RETR reenables the interrupt input logic. This occurs at
the beginning of the second cycle of the RETR instruction.
This sequence holds true also for an internal interrupt
generated by timer overflow. Jf an internal timer/counter
generated interrupt and an external interrupt are detected
at the same time, the external source will be recognized.
See the following Timer/Counter section for a description
of timer interrupt. If needed, a second external interrupt
can be created by enabling the timer/counter interrupt,
loading FFH in the Counter (ones less t1Jan terminal
count), and enabling the event counter mode. A "I" to
"0" transition on the TI input will then cause an interrupt
vector to location 7.
INTERRUPT TIMING
The interrupt input may be enabled or disabled under
Program Control using the EN I and DIS I instructions.
Interrupts are disabled by Reset and remain so until en-
abled by the users program. An interrupt request must be
removed before the RETR instruction is executed upon
return from the service routine otherwise the processor
will re-enter the service routine immediately. Many peripheral devices prevent this situation by resetting their
interrupt request line whenever the processor accesses
(Reads or Writes) the peripherals data buffer register. If
the interrupting device does not require access by the
processor, one output line of the 8048AH may be designated as an "interrupt acknowledge" which is activated
by the service subroutine to reset the interrupt request.
The INT pin may also be tested using the conditional jump
instruction IN!. This instruction may be used to detect the
presence of a pending interrupt before interrupts are enabled. If interrupt is left disabled, !NT may be used as
another test input like TO and Tl.
2.10 Timer/Counter
The 8048AH contains a counter to aid the user in counting
external events and generating accurate time delays without placing a burden on the processor for these functions.
In both modes the counter operation is the same, the only
difference being the source of the input to the counter.
The timer/event counter is shown in Figure 9.
COUNTER
The 8-bit binary counter is presenable and readable with
two MOV instructions which transfer the contents of the
accumulator to the counter and vice versa. The counter
content may be affected by Reset and should be initialized
by software. The counter is stopped by a Reset or STOP
TCNT instruction and remains stopped until started as a
timer by a START T instruction or as an event counter
by a START CNT instruction. Once started the counter
will increment to this maximum count (FF) and overflow
to zero continuing its count until stopped by a STOP TCNT
instruction or Reset.
The increment from maximum count to zero (overflow)
results in the setting of an overflow flag flip-flop and in
the generation of an interrupt request. The state of the
overflow flag is testable with the conditional jump instruction JTF. The flag is reset by executing a JTF or by Reset.
The interrupt request is stored in a latch and then ORed
with the external interrupt input INT. The timer interrupt
may be enabled or disabled independently of external interrupt by the EN TCNTI and DIS TCNTI instructions.
If enabled, the counter overflow will cause a subroutine
call to location 7 where the timer or counter service routine
may be stored.
If timer and external interrupts occur simultaneously, the
external source will be recognized and the Call will be to
intel~
SINGLE COMPONENT MCS!!c-48 SYSTEM
CONDITIONAL
JUMP LOGIC
S
JTF
EXECUTED _ _-r-"........~-+_~ R
RESET---i---'
TIMER
FLAG
INTERRUPT
CALL
EXECUTED
Q
EXTERNAL
INTERRUPT
RECOGNIZED
a
TIMER
INTERRUPT
RECOGNIZED
CLR
D
bl~ER~LOW -------<>--1 S
TIMER INT
RECOGNIZED
EXECUTED
Q
TIMER
OVERFLOW
FF
CLK
}---lR
RESET
S
S
DIS TCNTI _ _.._.......
EXECUTED
~--~ R
Q
INTERRUPT
IN
PROGRESS
FF
R
Q
TIMER
INT
ENABLE
a
RESET
INTcr------~ D
PIN
RESET
INT
FF
CLK
RETR
EXECUTED
a
ALE-~-""
LAST CYCLE
OF INST.
EN I
EXECUTED
DIS I
EXECUTED
RESET ---i---'
~----~
S
Q
INT
ENABLE
R
1. WHEN INTERRUPT IN PROGRESS FLIP-FLOP IS SET
ALL FURTHER INTERRUPTS ARE LOCKED OUT
INDEPENDENT OF STATE OF EITHER INTERRUPT
ENABLE FLIP-FLOP.
2. WHILE TIMER INTERRUPTS ARE DISABLED TIMER
OVERFLOW flf WILL NOT STORE ANY OVERFLOW
THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER.
Figure 8_ Interrupt Logic
1-8
inteL
MCS~-48
SINGLE COMPONENT
SYSTEM
PRESCALER
XTAL
15-
32
LOAD OR READ
CLEARED ON START TIMER
r-------------,
EDGE
DETECTOR
JUMP ON
TIMER FLAG
START
TIMER
START
COUNTER
8 BITTIMERI
EVENT COUNTER
o
OVERFLOW
FLAG
STOPT
INT
ENABLE---------.~__~
Figure 9. Timer/Event Counter
location 3. Since the timer interrupt is latched it will remain pending until the external device is serviced and
immediately be recognized upon return from the service
routine. The pending timer interrupt is reset by the Call
to location 7 or may be removed by executing a DIS
TCNTI instruction.
olution less than I count an external clock can be applied
to the T 1 input and the counter operated in the event
counter mode. ALE divided by 3 or more can serve as
this external clock. Very small delays or "fine tuning"
of larger delays can be easily accomplished by software
delay loops.
AS AN EVENT COUNTER
Often a serial link is desirable in an MCSA8 family member. Table 2 lists the timer counts and cycles needed
for a specific baud rate given a crystal frequency.
Execution of a START CNT instruction connects the Tl
input pin to the counter input and enables the counter.
The Tl input is sampled at the beginning of state 3 or in
later MCS-48 devices in state time 4. Subsequent high to
low transitions on TI will cause the counter to increment.
Tl must be-held low for at least I machine cycle to insure
it won't be missed. The maximum rate at which the
counter may be incremented is once per three instruction
cycles (every 5.7 f.isec when using an 8 MHz crystal) -there is no minimum frequency. Tl input must remain
high for at least 1/5 machine cycle after each transition.
AS A TIMER
Eexcution of a START T instruction connects an internal
clock to the counter input and enables the counter. The
internal clock is derived bypassing the basic machine cycle
clock through a -;- 32 prescaler. The prescaler is reset
during the START T instruction. The resulting clock increments the counter every 32 machine cycles. Various
delays from I to 256 counts can be obtained by presetting
the counter and detecting overflow. Times longer than 256
counts may be achieved by accumulating multiple overflows in a register under software control. For time res-
1-9
2.11 Clock and Timing Circuits
Timing generation for the 8048AH is completely selfcontained with the exeception of a frequency reference which
can be XT AL, ceramic resonator, or external clock source.
The Clock and Timing circuitry can be divided into the
following functional blocks.
OSCILLATOR
The on-board oscillator is a high gain parallel resonant
circuit with a frequency range of I to 11 MHz. The X I
external pin is the input to the amplifier stage while X2
is the output. A crystal or ceramic resonator connected
between Xl and X2 provides the feedback and phase shift
required for oscillation. If an accurate frequency reference
is not required, ceramic resonator may be used in place
of the crystal.
For accurate clocking, a crystal should be used. An externally generated clock may also be applied to XI-X2
as the frequency source. See the data sheet for more
information.
SINGLE COMPONENT MCSS!-48 SYSTEM
Table 2. Baud Rate Generation
Frequency
(MHz)
Tcy
TO Prr(1/5 Tcy}
Timer Prescaler
(32 TCY)
4
6
8
11
750ns
500ns
375ns
275ns
8 MHz
Timer Counts +
Instr. Cycles
120/-LS
80/-LS
60.2/-LS
43.5/-LS
11 MHz
Timer Counts +
Instr. Cycles
Baud
Rate
4 MHz
Timer Counts +
Instr. Cycles
3.75/-LS
2.50/-LS
1.88/-LS
1.36/-LS
6 MHz
Timer Counts +
Instr. Cycles
110
75 + 24 Cycles
.01% Error
113 + 20 Cycles
.01% Error
151 + 3 Cycles
.01% Error
208 + 28 Cycles
.01% Error
300
27 + 24 Cycles
.1% Error
41 + 21 Cycles
.03% Error
55 + 13 Cycles
.01% Error
76 + 18 Cycles.
.04% Error
1200
6 + 30 Cycles
.1% Error
10 + 13 Cycles
.1% Error
12 + 27 Cycles
.06% Error
19 + 4 Cycles
.12% Error
1800 .
4 + 20 Cycles
.1% Error
6 + 30 Cycles
.1% Error
9 + 7 Cycles
.17% Error
12 +24 Cycles
.12% Error
2400
3 + 15 Cycles
.1% Error
5 + 6 Cycles
.4% Error
6 + 24 Cycles
.29% Error
9+ 18 Cycles
.12% Error
4800
1 + 23 Cycles
1.0% Error~
2 + 19 Cycles
.4% Error
3 + 14 Cycles
.74% Error
4 + 25 Cycles
.12% Error
STATE COUNTER
power supply is within tolerance.Only 5 machine cycles
(6.8 JLS @ II MHz) are required if power is already on
and the oscillator has stabilized. ALE and PSEN (if EA
= 1) are active while in Reset.
The output of the oscillator is divided by 3 in the State
Counter to create a clock which defines the state times of
the machine (CLK). CLK can be made available on the
external pin TO by executing an ENTO CLK instruction.
The output of CLK on TO is disabled by Reset of the
processor.
Reset perfonns the following fundions:
1) Sets program counter to zero.
CYCLE COUNTER
2) Sets stack pointer to zero.
ClK is then divided by 5 in the Cycle Counter to provide a clock which defines a machine cycle consisting
of 5 machine states as shown in Figure 10. Figure 11
shows the different internal operations as divided into
the machine states. This clock is called Address latch
Enable (ALE) because of its function in MCS-48 systems with external memory. It is provided continuouslyon the ALE output pin.
3) Selects register bank O.
2.12 Reset
7) Disables interrupts (timer and external).
The reset input provides a means for .initialization for the
processor. This Schmitt-trigger input has an internal pullup device which in combination with an external 1 JL fd
capacitor provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset, as shown in Figure
12. If the reset pulse is generated externally the RESET
pin must be held -low for at least 10 milliseconds after the
8) Stops timer.
4) Selects memory bank O.
5) Sets BUS to high impedance state (except when
EA
= 5V).
6) Sets Ports I and 2to input mode.
9) Clears timer flag.
. 10) Clears FO and Fl.
11) Disables clock output from TO.
1·10
infel"
SINGLE COMPONENT
XTAL2
11
MHzCJ
MCS~-48
SYSTEM
JUMP ON
TEST 01 OR 0
_----"'1
+'3
STATE
COUNTER
XTAL 1 - - - - - - '
.273 ~.ec (3.67 MHz)
~
+5
CYCLE
(733 KHz)
COUNTER
_ _ _ _... 1.36
~.ec
DIAGRAM OF B048AH CLOCK UTILITIES
.
S1
55
52
S3
INPUT DECODE
INST.
I
S4
55
S1
INPUT
EXECUTION
OUTPUT
ADDRESS
INC. PC
I
I
,
1.36 ~.ec CYCLE
I
I
I
INSTRUCTION CYCLE
(1 BYTE, 2 CYCLE INSTRUCTION ONLY)
PREVIOUS CYCLE
__
I"
.....
1ST CYCLE----;__
~I - - - - 2 N D CYCLE---.
__~I
5TATETIME:
82
I
83
I
54
I
S5
I
51
I
S2
I
53
I
54
55
I
51
55
I
81
I
82
(02)-nI
~~
ALE
PSEN' - - - - - - ,
RO,~
______~~~________~r-l~________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ,
"EXTERNAL MODE
"IF ENABLED
804BAH/8049AH TIMING
Figure 10.
MCS~-48
Timing Generation and Cycle Timing
2.13 Single-Step
This feature, as pictured in Figure 13, provides the
user with a debug capability in that the processor can be
stepped through the program one instruction at a time.
While stopped. the address of the next instruction to be
fetched is available concurrently on BUS and the lower
1-11
half of Port 2. The user can therefore follow the program
through each of the instruction steps. A timing diagram,
showing the interaction between output ALE and input
SS, is shown. The BUS buffer contents are lost during
single step; however, a latch may be added to reestablish
the lost liD capability if needed. Data is valid at the leading
edge of ALE.
_.
-
1
CYCLE 2
CYCLE 1
INSTRUCTION
Sl
S2
S4
S3
S5
Sl
- - - - ------
=-co
0
~
ro
-
INCREMENT"
PROGRAM COUNTER
'OUTPUT
TO PORT
-
-
INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT
-
-
-
-
INCREMENT
PROGRAM COUNTER
OUTPUT
TO PORT
ANL P,
DATA
INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER
-
'INCREMENT
TIMER
'INCREMENT
TIMER
REAO PORT
DATA
INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER
-
'INCREMENT
TIMER
-
INCREMENT
TIMER
-
-
INCREMENT
TIMER
OUTPUT
TO PORT
-
-
'INCREMENT
TIMER
READ PORT
FETCH
IMMEDIATE DATA
INSA, BUS
OUTL BUS, A
FETCH
INSTRUCTION
INCREMENT
PROGRAM COUNTER
FETCH
ANL BUS, " DATA
INSTRUCTION
INCREMENT
PROGRAr,I COUNTER
-
READ PORT
FETCH
IMMEDIATE DATA
/'
1--
READ
PORT
-
I---~-
-
-
INCREMENT
PROGRAM COUNTER
'OUTPUT
TO PORT
m
-
-
-
READ P2
LOWER
-
-
-
-
-
-
-
~
MOVXA,@R
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT RAM
ADDRESS
INCREMENT
TIMER
-
-
READ
DATA
S'
MOVD A,P i
INCREMENT"
FETCH
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
-
-
MOVD PI,A
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT DATA
TOP2LOWER
-
ANLD P,A
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT
DATA
-
-
ORLD P,A
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
OUTPUT
OPCODE/ADDRESS
INCREMENT
TIMER
OUTPUT
DATA
-
SAMPLE
CONDITION
'INCREMENT
SAMPLE
-
FETCH
IMMEDIATE DATA
::I:
"-!l.
UI
c:
0'
~
-f
3'
5'
IC
C
iii'
IC
iil
3
INCREMENT
FETCH
J(CONDITIONAL)
INSTRUCTION PROGRAM COUNTER
1------
STRTT
STRTCNT
FETCH
INSTRUCTION
STOP TCNT
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
ENI
f-------~
INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER
--
INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER
DISI
-~
ENTO CLK
INCREMENT
PROGRAM COUNTER
-""
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
INCREMENT
PROGRAM COUNTER
"~---"
f-------~-"--
- - I----
'OUTPUT
TO PORT
--"-"-- .. --- ..
-
START
COUNTER
-
STOP
COUNTER
-
• ENABLE
INTERRUPT
-
-
• DISABLE
INTERRUPT
-
-
---_._----
--
-._"_.
-----"~
'
ENABLE
CLOCK
-----
-
-
._-_.
-
-
-
-
-
-
---
-
UPDATE
PROGRAM COUNTER
-
------~-~
.~----
~--"
--
---~--~
-----
o
o
-
-
~
m
-
-
FETCH
IMMEDIATE DATA
Z
G)
r-
s:'tI
OUTPUT
DATA TO RAM
READ PORT
-----~
-
en
-
INCREMENT
TIMER
- - I---~-"---
-
. _ - - - - - - -----
OUTPUT RAM
ADDRESS
'INCREMENT
TIMER
-
-
------
INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER
FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER
-
--f-
-
a
I---
""--------- - - - - ---.-- -
MOVX@R,A
ORL BUS, " DATA
-
- -f - - " - " - - - - -
~
iii
0
::I:
...
FETCH
IMMEDIATE DATA
OUTL P,A
FETCH
INSTRUCTION
;
...
-
-
l
-_.-
-
'INCREMENT
TIMER
INCREMENT
PROGRAM COUNTER
S5
-
-
FETCH
INSTRUCTION
S4
._--
-
INCREMENT
PROGRAM COUNTER
0
S3
--~-----------
-
FETCH
INSTRUCTION
ORL P,
::!!
c:
IC
.----.--~
READ
PORT
INA,P
~
S2
-~~--~--
·VALID INSTRUCTION ADDRESSES ARE OUTPUT
AT THIS TIME IF EXTERNAL PROGRAM MEMORY IS
BEING ACCESSED.
(1) IN LATER MCS·48 DEVICES TlIS SAMPLED IN S4_
o
Z
Z
-I
s::
oen
(~
I
"'CO"
en
~
-I
m
s::
intel.,
SINGLE COMPONENT MCS&-48 SYSTEM
clear input. ALE should be buffered since the clear input
of an SN7474 is the equivalent of 3 TTL loads. The
processor is now in the stopped state. The next instruction
is initiated by clocking a . 'I" into the flip-flop. This' 'I"
will not appear on SS unless ALE is high removing clear
from the flip-flop. In response to SS going high the processor be~s an instruction fetch which brings ALE low
resetting SS through the clear input and causing the processor to again enter the stopped state.
EXTERNAL RESET
Vcc
ACTIVE
PULLUP
2.14 Power Down Mode
(8048AH, 8049AH, 8050AH,
8039AHL, 8035AHL, 8040AHL)
POWER ON RESET
Vcc
.D-
1K
[
Extra circuitry has been added to the 8048AH/8049AHI
8050AH ROM version to allow power to be removed from
all but the data RAM array for low power standby operation. In the power down mode the contents of data RAM
can be maintained while drawing typically 10% to 15%
of normal operating power requirements.
~
80 Kit
vcc serves as the 5V supply pin for the bulk of circuitry
Figure 12.
while the V DO pin supplies only the RAM array. In normal
operation both pins are a 5V while in standby, Vcc is at
ground and VDO is maintained at its standby value. Applying Reset to the processor through the RESET pin
inhibits any access to the RAM by the processor and
guarantees that RAM cannot be inadvertently altered as
power is removed from V cc.
TIMING
The 8048AH operates in a single· step mode as follows:
I) The processor is requested to stop by applying a low
level on SS.
A typical power down sequence (Figure 14) occurs as
follows:
2) The processor responds by stopping during the address
fetch portion of the next instruction. If a double cycle
instruction is in progress when the single step command is received, both cycles will be completed before
stopping.
1) Imminent power supply failure is detected by user defined circuitry. Signal must be early enough to allow
8048AH to save all necessary data before Vcc falls
below normal operating limits.
3) The processor acknowledges it has entered the stopped
state by raising ALE high. In this state (which can be
maintained indefinitely) the address of the next instruc·
tion to be fetched is present on BUS and the lower
half of port 2.
2) Power fail signal is used to interrupt processor and
vector it to a power fail service routine.
4) SS is then raised high to bring the processo~ out of the
stopped mode allowing it to fetch the next instruction.
The exit from stop is indicated by the processor bringing ALE low.
3) Power fail routine saves all important data and machine
status in the internal data RAM array. Routine may
also initiate transfer of backup supply to the V DD pin
and indicate to external circuitry that power fail routine
is complete.
5) To stop the processor at the next instruction SS must
be brought low again soon after ALE goes low. If SS
is left high the processor remains in a "Run" mode.
4) Reset is applied to guarantee data will not be altered
as the power supply falls out of limits. Reset must be
held low until Vcc is at ground level.
A diagram for implementing the single·step function of
the 8748H is shown in Figure 13. D-type flip-flop with
preset and clear is used to generate 55. In the run mode
SS is held high by keeping the flip· flop preset (preset has
precedence over the clear input). To enter single step,
preset is removed allowing ALE to bring SS low via the
Recovery from the Power Down mode can occur as any
other power-on sequence with an external capacitor on
the Reset input providing the necessary delay. See the
previous section on Reset,
1-13
infel .
SINGLE COMPONENT
MCS~-48
SYSTEM
·5V
I
I
MOMENTARY
PUSHBUTTON
>
i'
SINGLE
STEP
+5V
10K
~~--------~
RUN!
10K
:
PRESET
o
·5V
SS
Q
r - - - - i > CLOCK
CLE~R
DEBOUNCE
LATCH
!
112
1/27400
~474
-
c4- ALE
SINGLE STEP CIRCUIT
1 S3
1
S4
1
S5
I
Sl
S3
1 S21
I
..
·1
S3
I
S4
1
S5
I
I
S2
1
ALE~
n
SS
BUS
P20-23
PC 0-7
I/O
;
PC 8-11
f
C
:
SINGLE STEP TIMING
Figure 13. Single Step Operation
1-14
1/0
intet
SINGLE COMPONENT MCS@'-48 SYSTEM
POWER
SUPPLY
reset the prescaler and time state generators. TO may then
be brought down with the rising edge of X I. Two clock
cycles later, with the rising edge of X I , the device enters
into Time State I, Phase I, SS' is then brought down to
5 volts 4 clocks later after TO. RESET' is allowed to go
high 5 tCY (75 clocks) later for nonnal execution of code.
See Figure IS.
...........
PROCESSOR:
,,~_ _
INTE~RU?TED i
POWER - - - ,
I
SUPPLY
I
FAIL SIGNAL
1
_ _~_ _~I
:
I
NORMAL
_1 _ _ _ POWER ON
I
SEQUENCE
I
FOLLOWS
U __
RESET
I
I
DATA SAVE
ROUTINE
EXECUTED
ACCESS TO
DATA RAM
INHIBITED
Figure 14. Power Down Sequence
2.15 External Access Mode
Nonnally the first IK (8048AH), 2K (8049AH), or 4K
(8050AH) words of program memory are automatically
fetched from internal ROM or EPROM. The EA input pin
however allows the user to effectively disable internal
program memory by forcing all program memory fetches
to reference external memory. The following chapter explains how access to external program memory is
accomplished.
The External Access mode is very useful in system test
and debug because it allows the user to disable his internal
applications program and substitute an external program
of his choice - a diagnostic routine for instance. In addition, the date sheet shows how internal program memory can be read externally, independent of the processor.
A "I" level on EA initiates the external accesss mode.
For proper operation, Reset should be applied while the
EA input is changed.
2.16 Sync Mode
The 8048AH, 8049AH, 8050AH has incorporated a new
SYNC mode. The Sync mode is provided to ease the
design of multiple controller circuits by allowing the designer to force the device into known phase and state time.
The SYNC mode may also be utilized by automatic test
equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the OUT (device under test).
SYNC mode is enabled when SS' pin is raised to high
voltage level of + 12 volts. To begin synchronization, TO
is raised to 5 volts at least four clocks cycles after SS'.
TO must be high for at least four X I clock cycles to fully
1-15
intel..
SINGLE COMPONENT MCS®-48 SYSTEM
X1
PHASE 1- -
-
-
-
-
-
-
-
-
-
-
-
PHASE 2- -
-
-
-
-
-
-
-
-
-
-
-
TIME STATE
SS
TO
ALE
RESET
3
4
12V
,r--------------------~----------~
SV~
~-----------------------------
OV
SV
OV--------------~
SV
SV
OV--------------------------------------------------~
OV--------------------------------------------------------------------SYNC MODE TIMING
Figure 15. Sync Mode Timing
3.0 PIN DESCRIPTION
The MCS-48 processors are packaged in 40 pin Dual InLine Packages (DIP's). Table 3 is a summary of the
functions of each pin. Figure 16 is the logic symbol
for the 8048AH product family. Where it exists, the second paragraph describes each pin's function in an expanded MCS-48 system. Unless otherwise specified, each
input is TIL compatible and each output will drive one
standard TIL load.
PORT
#1
XTAL{
RESET
SINGLE STEP
EXTERNAL
MEM
TEST{
INTERRUPT
BUS
PORT
#2
8048AH
8049AH
8050AH
READ
WRITE
PROGRAM
STORE ENABLE
ADDRESS
LATCH ENABLE
Figure 16. 8048AH and 8049AH Logic Symbol
1-16
int'eL
SINGLE COMPONENT MCS®-48 SYSTEM
Table 3. Pin Description
Designation
Pin
Number'
Function
vss
20
Circuit G!'\ D potential
V tm
26
Programming power supply; 21 V during program for the 8748H/8749H: + 5V during
operation for both ROM and EPROM. Low power standby pin in 8048AH and
8049AH/8050AH ROM versions.
Vet"
40
Main power supply: +5\' during operation and during X7-tXH and H749H programming.
PROG
25
Program pulse: + I xv input pin during 874gH. X749H programming. Output strobe
for g243 I 0 expander.
1'10-1'17
(Port I)
27-34
X-bit quasi-bidirectional port. (Internal Pullup = SOKll)
1'20 P27
(Pon 2)
21-24
353X
X-bit quasi-bidirectional port. (Internal Pullup = 50Kll)
1'20- P23 contain the four high order program counter bib during an e"tcrnal program memory fetch and serve as a 4-bit 1 0 expander hus for X2-t3.
DO-D7
(BUS)
1219
True bidirectional port which can be written or read synchronously using the ill.
WR strobes. The pon can also be statically latched.
Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSE\. Also
contains .the address and data during an external RA \1 data store instruction.
under control of ALE, RD. and WR.
Input pin testahle using the conditional transfer instructions .ITO and .I\;TO. TO
can be designated as a clock output using E:>ITO ClK instruction. TO is also used
during programming and sync mode.
TO
TI
39
Input pin testable using the JTI. and .I\TI instructiom. Can be designated thc
event counter input using the STRT CNT instruction. (See Section 2.10).
6
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled
after a reset. (Activc 10\\ I
Interrupt must remain 10\\ for at \east 3 machine cycles to ensure proper operation.
RD
Output strobe acti\'ated during a BUS read. Can be used to enable data onto the
BUS from an external de\ ice. (Acti\ e 10\\)
Used as a Read Strobe to External Data Memory.
ALE
4
Input which is used to initialize the processor. Also used during EPROM programming
and verification. (Active low) (Internal pullup = 80K 0)
10
Output ,trohe during a BUS \\fite. (Acti\'c 10\\') Used as
data memory.
II
Addre" l.atch Enable. This signal'lccurs once during each c\dc and is useful as
a clnck output.
\I
rite strohe to e.,tcrnal
The negati\ c edge of ALE strohl'S address intn external data and prngram memor,.
1-17
infel·
SINGLE COMPONENT MCS®-48 SYSTEM
Table 3. Pin Description (Continued)
Designation
Pin
Number*
--.
Function
PSE:-'
9
Program Store Enable. This output occurs only during a fetch to external program
memory. (Active low)
SS
5
Single step input can be used in conjunction with ALE to "single step" the processor
through ea'ch instruction. (Active 10\\) (Internal pullup "" 300K!l) +12V for sync
modes (See 2.16).
EA
7
E.xternal Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug, and essential for testing and program verification. (Active high) + J 2V· for 8048AH 8049AH !<050AH program
verification and +18V for 8748H . 8749H program verification (Internal pullup ""
10M!! on 8048AH 8049AH 8035AHL 8039AHL B050AH 8040AHl)
XTALI
2
One side of crystal input for internal oscillator. Also input for external source.
XTAL2
3
Other side of crystal external source input.
'Unle" otherwise stated. inputs do not ha\·e internal pull up resistors.
~04~AH. H74~H. ~049AH.
K050AH. K()40AHI.
4.0 PROGRAMMING, VERIFYING AND
ERASING EPROM
8748H AND 8749H ERASURE
CHARACTERISTICS
The internal Program Memory of the 8748H and the
8749H may be erased and reprogrammed by tlie user as
explained in the following sections. See also the 8748H
and 8749H data sheets.
The erasure characteristics of the 8748H and 8749H are
such that erasure begins to occur when exposed to light
with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8748H and 8749H in approximately 3 years while it would
take approximately I week to cause erasure when exposed
to direct sunlight. If the 8748H or 8749H is to be exposed
to these types of lighting conditions for extended periods
of time, opaque labels should be placed over the 8748H
window to prevent unintentional erasure.
4.1 ProgrammlngNerificatlon
In brief, the programming process consists of: activating
the program mode, applying an address, latching the address, applying data, and applying a programming pulse.
This programming algorithm applies to both the 8748H
and 8749H. Each word is programmed completely before
moving on to the next and is followed by a verification
step. The following is a list of the pins used for programming and a descsription of their functions:
Pin .
XTAL I
Reset
Test 0
EA
BUS
P20-1
P20-2
Voo
PROG
PIO-Pll
When erased, bits of the 8748H and 8749H Program Memory are in the logic "0" state.
Function
The recommended erasure procedure for the 8748H and
8749H is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (I.e .• UV intensity X exposure time) for erasure
should be a minimum of I 5W-seclcm 2 • The erasure iime
with this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a I2000/LW/cm 2 power rating.
The 8748H and 8749H should be placed within one inch
from the lamp tubes during erasure. Some lamps have a
filter in their tubes and this filter should be removed before
erasure ..
Clock Input (3 to 4 MHz)
Initialization and Address Latching
Selection of Program (OV) or Verify
(5V) Mode
Activation of Program/Verify Modes
Address and Data Input Data Output
During Verify
Address Input for 8748H
Address Input for 8749H
Programming Power Supply
Program Pulse Input
Tied to ground (8749H only)
1-18
intel .
SINGLE COMPONENT MCS-48 SYSTEM
COMBINATION PROGRAMIVERIFY MOOE (EPROM's ONLY)
18V
/
EA 5V __________- J
i--------PROGRAM--------I---VERIFY--·+I·----PROGRAM~ITW--I
TO
--IWW--!
Ir---------------------~----------~
RESET
--+---+- IWA
lAW -+j
~
r-~O~A=TA~T=O~B=E--~
OBO-DB7 ~ - -
P20-P22
PROGRAMMED VALID
, LAST
ADDRESS
NEXT
ADDRESS
VERIFY MODE (ROM/EPROM)
EA
_--.II
"TO,
RESET
\'--__~I
DBO-DB7
P20-P22
ADDRESS (8-10) VALID
NEXT ADDRESS VALID
NOTES:
1, PROG MUST FLOAT IF EA IS LOW (I.E., ,. 18V).
"TO ON EPROM ONLY,
Figure 17. ProgramNerify Sequence for 8749H/8748H
1-19
MCS® . .48 Expanded
System
2
intel·
EXPANDED MCS®-48 SYSTEM
of
1.0 INTRODUCTION
1) The contents
the 12-bit program counter will be
output on BUS and the lower half of port 2.
2) Address Latch Enable (ALE) will indicate the time at
which address is valid. The trailing edge of ALE is
used to latch the address externally.
3) Program Store Enable (PSEN) indicates that an external instruction fetch is in progress and serves to enable
the external memory device.
4) BUS reverts to input (floating) mode and the processor
accepts its 8-bit contents as an instruction word.
If the capabilities resident on the single-chip 8048AHI
8748Ht803SAH118049AHl8749H/8039AHL are not sufficient for your system requirements, special on-board cir- .
cuitry allows the addition of a wide variety of external
memory, liD, or special peripherals you may require. The
processors can be directly and simply expanded in the
following areas:
• Program Memory to 4K words
• Data Memory to 320 words (384 words with
8049AH)
• 110 by unlimited amount
• Special Functions using 8080/8085AH peripherals
L
By using bank switching techniques, maximum capability
is essentially unlimited. Bank switching is discussed later
in the chapter. Expansion is accomplished in two ways:
I) Expander 110 - A special liD Expander circuit, the
8243, provides for the addition of four 4-bit Input!
Output ports with the sacrifice of only the lower half
(4-bits) of port 2 for inter-device communication. Multiple 8243's may be added to this 4-bit bus by generating the required "chip select" lines.
2) Standard 8085 Bus - One port of the 8048AHI
8049AH is like the 8-bit bidirectional data bus of the
8085 microcomputer system allowing interface to the
numerous standard memories and peripherals of the
MCSiI-80/8S microcomputer family.
FLOATING
BUS
~FLOATINGO FLOATING
ADDRESS
INSTRUCTION
Figure 1. Instruction Fetch from
External Program Memory
All instruction fetches, including internal addresses, can be
forced to be external by activating the EA pin of the 8048AHI
8049AHJ8050AH. The 803SAHl18039AHl18040AHL pr0cessors without program memory always operate in the external program memory mode (EA = SV).
MCS-48 systems can be configured using either or both
of these expansion features to optimize system capabilities
to the application.
2.2 Extended Program Memory .
Addressing (Beyond 2K)
Both expander devices and standard memories and peripherals can be added in virtually any number and combination required.
For programs of 2K words or less, the 8048AHl8049AH
addresses program memory in the conventional manner.
Addresses beyond 2047 can be reached by executing a
program memory bank switch instruction (SEL MBO. SEL
MBI) followed by a branch instruction (JMP or CALL).
The bank switch feature extends the range of branch instructions beyond their normal 2K range and at the same
time prevents the user from inadvertently crossing the 2K
boundary.
2.0 EXPANSION OF PROGRAM MEMORY
Program Memory is expanded beyond the resident I K or
2K words by using the 8085 BUS feature of the MCSiI48. All program memory fetches from the addresses less
than 1024 on the 8048AH and less than 2048 on the
8049AH occur internally with no external signals being
generated (except ALE which is always present). At address 1024 on the 8048AH, the processor automatically
initiates external program memory fetches.
PROGRAM MEMORY BANK SWITCH
The switching of 2K program memory banks is accomplished by directly setting or resetting the most significant
bit of the program counter (bit 11); see Figure 2. Bit
11 is not altered by normal incrementing of the program
counter but is loaded with the contents of a special flipflop each. time a JMP or CALL instruction is executed.
This special flip-flop is set by executing an SEL MB I
2.1 Instruction Fetch Cycle (External)
As shown in Figure 1, for all instruction fetches from
addressc;s of 1024 (2048) or greater. the following will
occur:
2-1
infel~
EXPANDED MCS-48.
TEST
INPUTS
3.1 Read/Write Cycle
1/0
All address and data is transferred over the 8 lines of
BUS. As shown in Figure 5, a read or write cycle
occurs as follows:
Figure 4. External Program Memory Interface
ALE
BUS
J
L
FLOATING
~_ _ _F_L_O_A_T_IN_G_ __
FLOATING
READ FROM EXTERNAL DATA MEMORY
ALE
BUS
J
L
FLOATING
FLOATING
WRITE TO EXTERNAL DATA MEMORY
Figure 5. External Data Memory Timings
2-3
infel .
EXPANDED MCS®-48 SYSTEM
1) The contents ofregister RO or RI is outputed on BUS.
4.0 EXPANSION OF INPUT/OUTPUT
2) Address Latch Enable (ALE) indicates addresss is
valid. The trailing edge of ALE is used to latch the
address externally.
3) A read (RD) or write (WR) pulse on the corresponding
output pins of the S04SAH indicates the type of data
memory access i!!..E!:ogress. Output data is valid at the
trailing edge of WR and input data must be valid at
the trailing edge of RD.
There are four possible modes of liO expansion with the
S04SAH: one using a special low-cost expander, the S243;
another using standard MCS-SO/85 liO devices; and a third
using the combination memory 110 expander devices the
8155,8355, and 8755. It is also possible to expand using
standard TTL devices.
4.1 I/O Expander Device
4) Oat (S bits) is transferred in or out over BUS.
The most efficient means of 110 expansion for small systems is the 8243 liO Expander Device which requires only
4 port lines (lower half of Port 2) for c<;,mmunication with
the 8048AH. The 8243 contains four 4-bit liO ports which
serve as an extension of the on-chip I/O and are addressed
as ports #4-7 (see Figure 13-7). The following operations
may be performed on these ports:
3.2 Addressing External Data Memory
External Data Memory is accessed with its own two-cycle
move instructions. MOVXA, @R and MOVX@R, A.
which transfer S bits of data between the accumulator and
the external memory location addressed by the contents
of one of the RAM Pointer Registers RO and RI. This
allows 256 locations to be addressed in addition to the
resident locations. Additional pages may be added by
"bank switching" with extra output lines of the S048AH.
• Transfer Accumulator to Port
• Transfer Port to Accumulator
• AND Accumulator to Port
3.3 Examples of Data Memory ExpanSion
• OR Accumulator to Port
Figure 6 shows how the S04S-AH can be expanded
using the SI55 memory and liO expanding device. Since
the 8155 has an internalS-bit address latch, it can interface
directly to the S04SAH without the use of an external
latch. The S155 provides an additional 256 words of static
data memory and also includes 22 I/O lines and a 14-bit
timer. See the following section on liO expansion and the
SI55 data sheet for more details on these additional
features.
BUS
A 4-bit transfer from a port to the lower half of the Accumulator sets the most significant four bits to zero. All
communication between the 8048AH and the 8243 occurs
over Port 2 lower (P20-P23) with timing provided by an
output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles: The first containing the
"op code" and port address, and the second containing
the actual 4 bits of data.
-"
..
8
ALE
8048AH
ADO_7
WR
ALE 8155
256' 8
WR RAM
AD
AD
PORT
3
22
1/0
TIMER IN
TIMER OUT
101M
Ji~~JTS
..J-,
18
) 1/0
Figure 6. 8048AH Interface to 256 x 8 Standard Memories
2-4
intel"
EXPANDED
MCS~-48
SYSTEM
CHIP SELECT CONNECTION IF MORE
THAN ONE EXPANDER IS USED
1/0
P4
1/0
P5
'v--.2....--,/ 1/0
P6
1/0
P7
1/0
PROG
TEST
INPUTS
B050AH
B049AH
B04BAH
B243
DATA IN
P2
EXPANDER INTERFACE
BITS 0, 1
PROG
\
/
' - . _ _ _- J
P20-P23
--<~
___-,X'-______J»-----
BITS 2, 3
0001
PORT
00, READ
01 L WRITE
~~ ~
~~ ~ ~~D
ADDRESS
DATA (4-BITS)
ADDRESS
AND OPCODE
(4-BITS)
OUTPUT EXPANDER TIMING
Figure 7. 8243 Expander 1/0 Interface
Nibble I
I 0
o
II II IA IA I
Instruction
Code
II
00 Read
01 Wrile
IOOR
II A'D
4.2 1/0 Expansion with Standard
Peripherals
Nibble 2
I did I did I
Pori
Address
Standard MCS-80/85 type lIO devices may be added to
the MCS®-48 using the same bus and timing used for Data
Memory expansion. Figure 8 shows an example of how
an 8048AH can be connected to an MCS-85 peripheral.
110 devices reside on the Data Memory bus and in the
data memory address space and are accessed with the same
MOVX instructions. (See the previous section on data
memory expansion for a description of timing.) The following are a few of the Standard MCS-80 devices which
are very useful in MCS®-48 systems:
• 8214 Priority Interrupt Encoder
• 8251 Serial Communications Interface
• 8255 General Purpose Programmable lIO
• 8279 Keyboard/Display Interface
• 8254 Interval Timer
dala
AA
00 -POri
01 - Pori
10 - Pori
II -Pori
#4
#5
P6
#7
A high to low transition of the PROG line indicates that
address is present, while allow to high transition indicates
the presence of data. Additional 8243 's may be added to
the four-bit bus and chip selected using additional output
lines from the 8048AH/8748H.
I/O PORT CHARACTERISTICS
4.3 Combination Memory and
1/0 Expanders
Each \If the four 4-bit ports of the 8243 can serve as either
input or output and can provide high drive capability in
both the high and low state.
As mentioned in the sections on program and data memory
expansion, the 8355/8755 and 8155 expanders also contain
110 capability.
2-5
infel·
EXPANDED MCS®-48 SYSTEM
8
INT
INT
P20
CID
CNTL
8279
KEYBOARD
DISPLAY
B048AH
RD
RD
WR
WR
BUS
8
KEYBOARD
INPUTS
SCAN
OUTPUTS
(A) DISPLAY·
OUTPUT
DATA
BUS
Cs
(B) DISPLAY
OUTPUT
Figure 8. Keyboard/Display Interface
port. These three registers and a Control/Status register
are accessible as external data memory with the MOVX
instructions. The contents of the control register determines the mode of the three ports. The ports can be programmed as input or output with or without associated
handshake communication lines. In the handshake mode.
lines of the six-bit port become input and output strobes
for the two 8-bit ports. Also included in the 8155 is a
14-bit programmable timer. The clock input to the tiiner
and the timer overflow output are available on external
pins. The timer can be programmed to stop on terminal
count or to continuously reload itself. A square wave or
pulse output on terminal count can also be specified.
8355/8755: These two pat:ts of ROM and EPROM equivalents and therefore contain the same 110 structure. 1/0
consists of two 8~bit ports which normally reside in the
external data memory address space and are accessed with
MOVX instructions. Associated with each port is an 8bit Data Direction Register whieh defines each bit in the
port as either an input or an output. The data direction
registers are directly addressable. thereby allowing the
user to define under software control·each individual bit
of the ports as either input or output. All outputs are
statically latched and double buffered. Inputs are not
latched.
8155/8156: I/O on the 8155/8156 is configured as two
8-bit programmable I/O ports and one 6-bit programmable
B04BAH
PORT 2
8
PROG~----------~~------------~-------------+------------~
Figure 9. Low Cost I/O Expansion
2-6
intel.,
EXPANDED MCS@·48 SYSTEM
110 EXPANSION EXAMPLES
Figure 10 shows the 8048AH interface to a standard
MCS~-80 peripheral; in this case, the 8255 Programmable
Peripheral Interface, a 4O-pin part which provides three
8-bit programmable 110 pons. The 8255 bus interface is
typical of programmable MCS~-80 peripherals with an
8-bit bidirectional data bus, a RD and WR input for Read!
Write control, a CS (chip select) input used to enable the
ReadlWrite control logic and the address inputs used to
select various internal registers.
Figure 9 shows the expansion of 110 using multiple
8243's. The only difference from a single 8243 system is
the addition of chip selects provided by additional 8048AH
output lines. Two output liens and a decoder could also
be used to address the four chips. Large numbers of 8243's
would require a chip select decoder chip such as the 8205
to save 110 pins.
Ao
8048AH ALE
RD
WR
8255
A1 PROGRAM·
MABLE
PERIPHERAL
INTERFACE
BUS
P20
P21
PORT
A
Ao
8255
A1 PROGRAM·
MABLE
PERIPHERAL
INTERFACE
PORT
B
8048AH _
RD
Ro
PORT
C
WR
ViR
BUS
8
PORT
C
CS
-=-
Figure 10. Interface to
PORT
B
00-7
CS
OPTION.1
PORT
A
OPTIONN2
MCS~ ·80
-=-
Peripherals
addressing of the various memories and 110 pons. Note
that in this confilzuration address lines AIO and All have
been ORed to chip select the 8355. This ensures that the
chip is active for all external program memory fetches in
the 1K to 3K range and is disabled for all other addresses.
This gating has been added to allow the 110 pon of the
8355 to be used. If the chip was left selected all the time.
there would be conflict between these pons and the RAM
and 110 of the 8156. The NOR gate could be eliminated
and All connected directly to the CE (instead of CE) input
of the 8355; however. this would create a 1K word "hole"
in the program memory by causing the 8355 to be active
in the 2K and 4K range instead of the normal IK to 3K
range.
Interconnection to the 8048AH is very straightforward
with BUS, RD, and WR connecting directly to the corresponding pins on the 8255. The only design consideration is the way in which the internal registers of the 8255
are to be addressed. If the registers are to be addressed
as external data memory using the MOVX instructions,
the appropriate number of address bits (in this case, 2)
must be latched on BUS using ALE as described in the
section on external data memories. If only a single device
is connected to BUS, the 8255 may be continuously selected by grounding CS. If multiple 8255's are used, additional address bits can be latched and used as chip
selects.
A second addressing method eliminatcs external latches
and chip sclcct dc(:odcrs by using output port lines as addrcs> and chip sclect lines directly. This method. of
course. rC4uircs the selting of an output pOri with address
information prior \0 executing a MOVX instruction.
In this system the various locations are addressed as
follows:
• Data RAM - Addresses 0 to 255 when Pon 2 Bit
o has been previously set = I and Bit 1 set = 0
• RAM 110 - Addresses 0 to 3 when Port 2 Bit 0 =
1 and Bit I = I
5.0 MULTI·CHIP MCSI!)·48 SYSTEMS
• ROM 110 Bit 3 = I
Figure II shows the addition of two memory expanders
to the 8048AH, one 8355/8755 ROM and one 8156 RAM.
The main consideration in designing such a system is the
Addresses 0 to 3 when Pon 2 Bit 2 or
See the memory map in Figure 12.
2-7
infel .
EXPANDED MCS\!t-48 SYSTEM
8156/8355
PORT
PORT
ALE
PSEN
I048AH
iii)
-
iiii
BUS
PORT
8
A
PORT
B
PORT
C
Figure 11. The Three-Component
6.0 MEMORY BANK SWITCHING
MCS~""'8
System
Jumping to subroutines across the boundary should be .
avoided when possible since the programmer must keep
track ·of which barik to return to after completion of the
subroutine. If these subroutines are to be nested and ac·
cessed from either bank, a software "stack" should be
implemented to save the bank switch bit just as if it. were
another bit of the program counter.
Cenain systems may require more than the 4K words of
program memory which are directly addressable by· the
program counter or more than the 256 data memory and
VO locations directly addressable by the pointer registers
RO and Rl. These systems can be achieved using "bank
switching" techniques. Bank switching is merely the se·
lection of various blocks of "banks" of memory using
dedicated· output pon lines from the processor. In the case
of the 8048AH, program memory is selected in blocks of
4K words at a time, while data memory and VO are enabled 256 words at a time.
From a hardware standpoint bank switching is very
straightforward and involves only the connection of an
110 line or lines as bank enable signals. These enables are
ANDed with normal memory and 110 chip select signals
to activate the proper bank.
The most imponant consideration in implementing two or
more banks is the software required to cross the bank
boundaries. Each crossing of the boundary requires that
the processor first write a control bit to an output pon
before accessing memory or 110 in the new bank. If pr0gram memory is being switched, programs should be organized to keep boundary crossings to a minimum.
7.0 CONTROL SIGNAL SUMMARY
1llble 1 summarizes the instructions which activate the
various control outputs of the MCS~-48 processors. During all other instructions these outputs are driven to the
active state.
2-8
int:el.,
EXPANDED
MCS~-48
Table 1. MCS' ·48 Control Signals
Control
Signal
RD
When Active
During MOVX, A, @R or INS Bus
WR
During MOVX @R, A or OUTL Bus
ALE
Every Machine Cycle
During Fetch of external program memory (instruction or immediate data)
During MOVO, A,P ANLO P,A MOVO
P,A ORLO P,A
PSEN
PROG
SYSTEM
The latched mode (INS, OUTL) is intended for use in the
single-chip configuration where BUS is not begin used as
an expander port. OUTL and MOVX instructions can be
mixed if necessary. However, a previously latched output
will be destroyed by executing a MOVX instruction and
BUS will be left in the high impedance state. INS does
not put the BUS in a high impedance state. Therefore,
the use of MOVX after OUTL to put the BUS in a high
impedance state is necessary before an INS instruction
intended to read an external word (as opposed to the previously latched value).
OUTL should never be used in a system with external
program memory, since latching BUS can cause the next
instruction, if external, to be fetched improperly.
8.0 PORT CHARACTERISTICS
8.1 BUS Port Operations
8.2 Port 2 Operations
The BUS port can operate in three different modes: as a
latched 110 port, as a bidirectional bus port, or as a program memory address output when external memory is
used. The BUS port lines are either active high, active
low, or high impedance (floating).
The lower half of Port 2 can be used in three different
ways: as a quasi-bidirectional static port, as an 8243 expander port, and to adddress external program memory.
PROGRAM MEMORY
SPACE
r-----'BFFH
MB'
8355
(2K)
EXTERNAL DATA
MEMORY SPACE
MBOi-----i400H
I
I ~~5
I
II 8155
10
- - - - - - - - 300H
RESIDENT
I
--j';Kj'--
I
I
200H
8155 (256)
- - - - - - - 100H·
i
"-----'OOOH 1--------1
SECTION
PROG.MEM
DATAMEM
8155 PORTS
8355 PORTS
RESIDENT DATA
MEMORY
(64)
ADDRESS
DESIGNATION
OOO-BFF
100-IFF
300
301
302
303
304
305
400
401
402
403
CMO/STATUS
PORTA
PORTB
PORTC
TIMER LOW
TIMER HI
PORTA
PORTB
DORA
DDRB
Figure 12. Memory Map for Three·Component
2·9
MCS~·48
Family
infel~
EXPANDED
MCS~-48
SYSTEM
viously latched will be automatically removed temporarily
while address is present. then retored when the fetch is
complete. However. if lower Pon 2 is used to communicate with an 8243. previously latched 110 infonnation
will be removed and not restored. After an input from the
8243. P20-3 will be left in the input mode (floating). After
an output to the 8243. P20-3 will contain the value written.
ANDed. or ORed to the 8243 pon.
In all cases outputs· are driven low by an active device
and driven high momentarily by a low impedance device
and held high by a high impedance device to vee.
The port may contain latched 110 data prior to its use in
another mode without affecting operation of either. If
lower Port 2 (P20-3) is used to output address for an
external program memory fetch, the 110 infonnation pre-
110
110
8749H
8049AH
8048AH
8748H
a035AHL
8039AHL
r - - - - - - - , ,.-_ _ _ _ _...J
8251
USART
SERIAL
OUTPUT
8279
KEYBOARDI
DISPLAY
SERIAL
INPUT
CI
CI
Figure 13.
MCS~
·48 Expansion Capability
2-10
00
MCS® . .48 Instruction Set
3
int'el..
MCS®-48 INSTRUCTION SET
1.0 INTRODUCTION
1.1 Data Transfers
The MCS@-48 instruction' set is extensive for a machine
of its size and has been tailored to be straightforward and
very efficient in its use of program memory. All instructions are either one or two bytes in length and over 80%
are only one byte long. Also, all instructions execute in
either one or two cycles and over 50% of all instructions
execute in a single cycle. Double cycle instructions include all immediate instructions, and allIlO instructions.
As can be seen in Figure 1 the 8-bit accumulator is
the central point for all data transfers within the 8048.
Data can be transferred between the 8 registers of each
working register bank and the accumulator directly, i.e.,
the source or destination register is specified by the instruction. The remaining locations of the internal RAM
array are referred to as Data Memory and are addressed
indirectly via an address stored in either RO or R I of the
active register bank. RO and R 1 are also used to indirecly
address external data memory when it is present. Transfers
to and from internal RAM require one cycle, while transfers to external RAM require two. Constants stored in
Program Memory can be loaded directly to the accumulator and to the 8 working registers. Data can also be
transferred directly between the accumulator and the on-
The MCS-48 microcomputers have been designed to handle arithmetic operations efficiently in both binary and
BCD as well as handle the single-bit operations required
in control applications. Special instructions have also been
included to simplify loop counters, table look-up routines,
and N-way branch routines.
1---------------1
I
I
PROGRAM
MEMORY
(#DATA)
I
DATA
MEMORY
I
MOV
WORKING REG
ADD
MOV
MOVP
MOVP3
ANL
ORL
XRL
MOV
ADD
ANL
ORL
XRL
XCH
EXPANDER I'''-_,.,.,----'--''\ ~"'------------....:..C----~~ 1":::-:::'-:::':--'-.1"\ EXTERNAL
MEMORY
1/0 PORTS
AND
4-7
PERIPHERALS
8749H
8048AH
8049AH
ANL
ORL
8748H
8035AHL'
8039AHL'
I
J
~--------
Figure 1. Data Transfer Instructions
3-1
'NO PROGRAM
MEMORY
infel~
MCS®·48 INSTRUCTION SET
1.4 Flags
board timer counter or the accumulator and the Program
Status word (PSW). Writing to the PSW alters machine
status accordingly and provides a means ofrestoring status
after an interrupt or of altering the stack pointer if
necessary.
There are four user-accessible flags in the 8048AH: Carry,
Auxiliary Carry, FO and Fl. Carry indicates overflow of
the accumulator, and Auxiliary Carry is used to indiate
overflow between BCD digits and is used during decimaladjust operation. Both Carry and Auxiliary Carry are accessible as part of the program status word and are stored
on the stack during subroutines. FO and FI are undedicated
general-purpose flags to be used as the programmer desires. Both flags can be cleared or complemented and
tested by conditional jump instructions. FO is also accessible via the Program Status word and is stored on the
stack with the carry flags.
1.2 Accumulator Operations
Immediate data, data memory, or the working registers
can be added with or without carry to the accumulator.
These sources can also be ANDed, ORed, or Exclusive
ORed to the accumulator. Data may be moved to or from
the accumulator and working registers or data memory.
The two values can also be exchanged in a single
operation.
1.5 Branch Instructions
In addition, the lower 4 bits of the accumulator can be
exchanged with the lower 4-bits of any of the internal
RAM locations. This instruction, along with an instruction
which swaps the upper and lower 4-bit halves of the accumulator, provides for easy handling of 4-bit quantities.
including BCD numbers. To facilitate BCD arithmetic. a
Decimal Adjust instruction is included. This instruction
is used to correct the result of the binary addition Of two
2-digit BCD numbers. Performing a decimal adjust on the
result in the accumulator produces the required BCD
result.
The unconditional jump instruction is two bytes and allows
jumps anywhere in the first 2K words of program memory.
Jumps to the second 2K of memory (4K words are directly
addressable) are made first by executing a select memory
bank instruction, then executing the jump instruction. The
2K boundary can only be crossed via ajump or subroutine
call instruction, i.e., the bank switch does not occur until
a jump is executed. Once a memory bank has been selected
all subsequent jumps will be to the selected bank until
another select memory bank instruction is executed. A
subroutine in the opposite bank can be accessed by a select
memory bank instruction followed by a call instruction.
Upon completion of the subroutine, execution will automatically return to the original bank; however, unless the
original bank is reselected, the next jump instruction encountered will again transfer execution to the opposite
bank.
Finally, the accumulator can be incremented, decremented, cleared, or complemented and can be rotated left
or right I bit at a time with or without carry.
Although there is no subtract instruction in the 8048AH,
this operation can be easily implemented with three singlebyte single-cycle instructions.
Conditional jumps can test the following inputs and machine status:
A value may be subtracted from the accumulator with the
result in the accumulator by:
• TO Input Pin
• Complementing the accumulator
• Tl Input Pin
• Adding the value to the accumulator
• INT Input Pin
• Accumulator Zero
• Complementing the accumulator
• Any bit of Accumulator
1.3 Register Operations
• Carry Flag
• FO Flag
The working registers can be accessed via the accumulator
as explained above, or can be loaded immediate with
constants from program memory. In addition, they can be
incremented or decremented or used as loop counters using
the decrement and jump, if not zero instruction, as explained under branch instructions.
• Fl Flag
Conditional jumps allow a branch to any address within
the current page (256 words) of execution. The conditions
tested are the instantaneous values at the time the conditional jump is executed. For instance, the jump on accumulator zero instruction tests the accumulator itself, not
an intermediate zero flag.
All Data Memory including working registers can be accessed with indirect instructions via RO and R I and can
be incremented.
3·2
int:el.,
MCS~-48
INSTRUCTION SET
The decrement register and jump if not zero instruction
combines a decrement and a branch instruction to create
an instruction very useful in implementing a loop counter.
This instruction can designate anyone of the 8 working
registers as a counter and can effect a branch to any address
within the current page of execution.
The working register bank switch instructions allow the
programmer to immediately substitute a second 8-register
working register bank for the one in use. This effectively
provides 16 working registers or it can be used as a means
of quickly saving the contents of the registers in response
to an interrupt. The user has the option to switch or not
to switch banks on interrupt. However, if the banks are
switched, the original bank will be automatically restored
upon execution of a return and restore status instruction
at the end of the interrupt service routine.
A single-byte indirect jump instruction allows the program
to be vectored to anyone of several different locations
based on the contents of the accumulator. The contents
of the accumulator points to a location in program memory
which contains the jump address. The 8-bit jump address
refers to the current page of execution. This instruction
could be used, for instance, to vector to anyone of several
routines based on an ASCII character which has been
loaded in the accumulator. In this way ASCII key inputs
can be used to initiate various routines.
A special instruction enables an internal clock, which is
the XTAL frequency divided by three to be output on pin
TO. This clock can be used as a general-purpose clock in
the user's system. This instruction should be used only to
initialize the system since the clock output can be disabled
only by application of system reset.
1.6 Subroutines
1.9 Input/Output Instructions
Subroutines are entered by executing a call instruction.
Calls can be made like unconditional jumps to any address
in a 2K word bank, and jumps across the 2K boundary
are executed in the same manner. Two separate return
instructions determine whether or not status (upper 4-bits
of PSW) is restored upon return from the subroutine.
Ports 1 and 2 are 8-bit static 110 ports which can be loaded
to and from the accumulator. Outputs are statically latched
but inputs are not latched and must be read while inputs
are present. In addition, immediate data from program
memory can be ANDed or ORed directly to Port 1 and
Port 2 with the result remaining on the port. This allows
"masks" stored in program memory to selectively set or
reset individual bits of the 110 ports. Ports 1 and'2 are
configured to allow input on a given pin by first writing
a "I" out to the pin.
The return and restore status instruction also signals the
end of an interrupt service routine if one has been in
progress.
1.7 Timer Instructions
An 8-bit port called BUS can also be accessed via the
accumulator and can have statically latched outputs as
well. It too can have immediate data ANDed or ORed
directly to its outputs, however, unlike ports 1 and 2, all
eight lines of BUS must be treated as either input or output
at anyone time. In addition to being a static port, BUS
can be used as a true synchronous bi-directional pon using
the Move External instructions used to access external
data memory. When these instructions are executed, a
corresponding READ or WRITE pulse is generated and
data is valid only at that time. When data is not being
transferred, BUS is in a high impedance state. Note that
the OUTL, ANL, and the ORL instructions for the BUS
are for use with internal program memory only.
The 8-bit on board timer/counter can be loaded or read
via the accumulator while the counter is stopped or while
counting. The counter can be started as a timer with an
internal clock source or an event counter or timer with an
external clock applied to the Tl input pin. The instruction
executed determines which clock source is used. A single
instruction stops the counter whether it is operating with
an internal or an external clock source. In addition, two
instructions allow the timer interrupt to be enabled or
disabled.
1.8 Control Instructions
The basic three on-board 110 ports can be expanded via
a 4-bit expander bus using half of pon 2. 110 expander
devices on this bus consist of four 4-bit pons which are
addressed as ports 4 through 7. These pons have their
own AND and OR instructions like the on-board pons as
well as move instructions to transfer data in or out. The
expander AND and OR instructions, however, combine
the contents of accumulator with the selected pon rather
than immediate data as is done with the on-board ports.
Two instructions allow the external interrupt source to be
enabled or disabled. Interrupts are initially disabled and
are automatically disabled while an interrupt service routines is in progress and re-enabled afterward.
There are four memory bank select instructions, two to
designate the active working register bank and two to
control program memory banks. The operation of the program memory bank switch is explained in Section 2.2
in the Expanded MCS-48 System chapter.
3-3
int:et
MCS®-48 INSTRUCTION SET
I/O devices can also be added externally using the BUS
port as the expansion bus. In this case the 110 ports become
"memory mapped", i.e., they are addressed in the same
way as external data memory and exist in the external
data memory address space addressed by pointer register
RO or Rl.
The alphabetical listing includes the following
infonnation.
• Mnemoni!=
• Machine Code
• Verbal Description
• Symbolic Description
• Assembly Language Example
The machine code is represented with the most significant
bit (7) to the left and two byte instructions are represented
with the first byte on the left. The assembly language
examples are fonnulated as follows:
2.0 INSTRUCTION SET DESCRIPTION
The following pages describe the MCS®-48 instruction set
in detail. The instruction set is first summarized with instructions grouped functionally. This summary page is
followed by a detailed description listed alphabetically by
mnemonic opcode.
Arbitrary
Label: Mnemonic, Operand;
Descriptive Comment
3-4
intel·
MCS®-48 INSTRUCTION SET
B04BAH/B74BH/B049AH/B050AH/B749H
Instruction Set Summary
Mnemonic
Description
Mnemonic
Bytes Cycle
XRLA,@R
XRL, A, # data
INCA
DEC A
CLRA
CPLA
DAA
SWAP A
RLA
RLCA
RRA
RRCA
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory
with carry
Add immediate
with carry
And register to A
And data memory to A
And immediate to A
o.r register to A
o.r data memory to A
o.r immediate to A
Exclusive o.r register
toA
Exclusive or data
memory to A
Exclusive or
immediate to A
IncrementA
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left
through carry
Rotate A right
Rotate A right
through carry
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2
INCR
INC@R
DECR
Mo.VD P, A
ANLD P, A
o.RLD P, A
Increment register
Increment data memory
Decrement register
1
1
1
1
1
1
Jump unconditional
Jump indirect
Decrement register
and jump
Jump on carry =1
Jump on carry =0
Jump on A Zero
Jump on A not Zero
Jump on TO =1
Jump on TO =0
Jump on T1 =1
Jump on T1 =0
Jump on FO =1
Jump on F1 =1
Jump on timer flag ='1
Jump on INT =0
Jump on Accumulator
Bit
2
1
2
2
2
2
2
2
Jump to subroutine
Return
Return and restore
status
2
2
1
1
2
2
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear Flag 1
Complement Flag 1
1
1
1
1.
1
1
1
1
1
1
1
Move register to A
Move data memory
toA
Move immediate to A
Move A to register
Move A to data
memory
Move immediate
to register
Move immediate to
data memory
Move PSWtoA
MoveAto PSW
1
1
1
1
2
1
1
2
2
2
2
2
1
1
1
1
Branch
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNI addr
JBb addr
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Flags
2
CLRC
CPLC
CLR FO
CPL FO
CLR F1
CPL F1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Subroutine
CALL addr
RET
RETR
Input/Output
INA, P
o.UTLP,A
ANL P, # data
o.RL P, # data
'INSA, BUS
'o.UTL BUS, A
'ANL BUS,
# data
'o.RL BUS,
# data
Mo.VDA, P
Bytes Cycles
Registers
Accumulator
ADD A, R
ADDA,@R
ADD A,# data
AD DC A, R
ADDCA,
@R
AD DC A,
# data
ANLA, R
ANLA,@R
ANL A, # data
QRL A, R
o.RLA@R
o.RL A, # data
XRLA, R
Description
I nput port to A
o.utput A to port
And immediate to port
o.r immediate to port
Input BUS to A
o.utput A to BUS
And immediate to BUS
1
1
2
2
1
1
2
o.r immediate to BUS
2
2
Input Expander port
toA
o.utput A to Expander
port
And A to Expander port
o.r A to Expander port
1
2
Mo.VA,#data
Mo.VR, A
Mo.V@R,A
1
2
Mo.V R, # data
1
1
2
Mo.V@R,
# data
Mo.VA, PSW
Mo.V PSW, A
2
2
2
,.
Data Moves
2
2
Mo.VA, R
Mo.VA,@R
2
2
Mnemonics copyright Intel Corporation 1983,
'For use with internal memory only.
3-5
1
1
MCS®-48 INSTRUCTION SET
8048AH/874SH/S049AH/S050AH/S7 49H
Instruction Set Summary (Con't)
Mnemonic
Description
Data Moves
(Cont'd)
XCH A, R
DIS TCNTI
Mnemonic
Control
EN I
Exchapge A and
register
XCH A,@R
Exchange A and
data memory
XCHDA, @R
Exchange nibble of A
and register
MOVX A, @R
Move external data
memory to A
Move A to external
MOVX@R,A
data memory
MOVPA,@A
Move to A from
current page
MOVP3A,@A Move to A from Page 3
Timer/Counter
MOVA, T
MOVT, A
STRTT
STRT CNT
STOP TCNT
EN TCNTI
Bytes Cycle
Read Timer/Counter
load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter
Interrupt
Disable Timer/Counter
Interrupt
1
1
DIS I
1
1
1
1
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
• 1
SEl RBO
SEl RB1
SEl MBO
. SEl MB1
ENTO ClK
NOP
Description
Bytes Cycle
Enable external
Interrupt
Disable external
Interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output
on TO
No Operation
Mnemonics copyright Intel Corporation 1983.
3-6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
int:eL
MCS®-48 INSTRUCTION SET
Symbols and Abbreviations Used
A
AC
addr
Bb
BS
BUS
C
ClK
CNT
CRR
D
data
DBF
Fa, F1
I
P
PC
Pp
PSW
Ri
Rr
SP
T
TF
TO, T1
X
#
@
$
(X)
((X) )
Accumulator
Auxiliary Carry
12-Bit Program Memory Address
Bit Designator (b = 0-7)
Bank Switch
BUS Port
Carry
Clock
Event Counter
Conversion Result Register
Mnemonic for 4-Bit Digit (Nibble)
8-Bit Number or Expression
Memory Bank Flip-Flop
Flag 0, Flag 1
Interrupt
Mnemonic for "in-page" Operation
Program Counter
Port Designator (p = 1,2 or 4-7)
Program Status Word
Data memory Pointer (i = 0, or 1)
Register Designator (r = 0-7)
Stack Pointer
Timer
Timer Flag
Test 0, Test 1
Mnemonic for External RAM
Immediate Data Prefix
Indirect Address Prefix
Current Value of Program Counter
Contents of X
Contents of location Addressed by X
Is Replaced by
Mnemonics copyright Intel Corporation 1983.
3-7
MCS®-48 INSTRUCTION SET
ADD A,R r
Add Register Contents to Accumulator
Encoding:
I0
1 1 0
I1 r
r r
I
68H-6FH
Description: The contents of register 'r' are added to the accumulator. Carry is
affected.
Operation: (A) -
r = 0-7
(A) + (Rr)
;ADD REG 6 CONTENTS
;TO ACC
Example: ADDREG: ADD A,R6
ADD A,@R, Add Data Memory Contents to Accumulator
Encoding;
I0
1 1 0
I0 0 0 i I
60H-61H
Description: The contents of the resident data memory location addressed by register 'i' bits
0-5** are added to the accumulator. Carry is affected.
Operation: (A) - (Al + «Ri»
Example: ADDM: MOV RO, #OlFH
ADD A, @RO
ADD A,#data
Encoding:
i = 0-1
;MOVE '1F' HEX TO REG 0
;ADD VALUE OF LOCATION
;31 TO ACC
Add Immediate Data to Accumulator
10 0 0 0 I 0 0
I L£d6
I
dS d4 1d3 d2 d 1 dO
03H
Description: This is a 2-cycle instruction. The specified data is added to the accumulator.
Carry is affected.
Operation: (A) -
1 1
(A) + data
Example: ADDID: ADD A,#ADDER:
ADDC A,R r
;ADD VALUE OF SYMBOL
;ADDER' TO ACC
Add Carry and Register Contents to Accumulator
Encoding: 10 1 1 1 11 r r r
I
78H-7FH
Description: The content of the carry bit is added to accumulator location 0 and the carry
bit cleared. The contents of register 'r' are then added to the accumulator.
Carry is affected.
Operation: (A) -
r = 0-7
(A) + (Rr) + (C)
Example: ADDRGC: AD DC A,R4
;ADD CARRY AND REG 4
;CONTENTS TO ACC
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-8
MCS®-48 INSTRUCTION SET
ADDC A,@Ri
Encoding:
Add Carry and Data Memory Contents to Accumulator
I0 1 1 1 I 0 0 0 i I
70H-71H
Description: The content of the carry bit is added to accumulator location 0 and the carry bit
cleared. Then the contents of the resident data memory location addressed by
register 'i' bits 0-5** are added to the accumulator. Carry is affected.
Operation: (A) -
(A) + «Ri)) + (C)
i = 0-1
Example: ADDMC: MOV R1,#40
ADDC A,@R1
ADDC A,@data
;MOVE '40' DEC TO REG 1
;ADD CARRY AND LOCATION 40
;CONTENTS TO ACC
Add Carry and Immediate Data to Accumulator
Encoding: 10 0 0 1
I0 0
1 1
I I d7 d6 d5
d4
Id3 d 2 d1
dO
I
13H
Description: This is a 2-cycle instruction. The content of the carry bit is added to
accumulator location 0 and the carry bit cleared. Then the specified data is
added to the accumulator. Carry is affected.
Operation: (A) -
(A) + data + (C)
Example: ADOC A,#225
ANL A,R r
;ADD CARRY AND '225' DEC
;TO ACC
Logical AND Accumulator with Register Mask
Encoding: 10 1 0 1 \1 r r r
I
58H-5FH
Description: Data in the accumulator is logically ANOed with the mask contained in
working register 'r'.
Operation: (A) -
r = 0-7
(A) AND (Rr)
Example: ANOREG: ANL A,R3
ANL A,@Ri
;'AND' ACC CONTENTS WITH MASK
;IN REG 3
Logical AND Accumulator with memory Mask
Encoding:
I0 1 0 1 I0 0 0 i I
50H-51H
Description: Data in the accumulator is logically ANDed with the mask contained in the
data memory location referenced by register 'i' bits 0-5*'.
Operation: (A) -
(A) AND «Ri))
i
Example: ANDDM: MOV RO,#03FH
ANL A, @RO
=0-1
;MOVE '3F' HEX TO REG 0
;'ANO' ACC CONTENTS WITH
;MASK IN LOCATION 63
•• 0-5 in S04SAHIS74SH
0-6 in S049AHIS74.9H
0-7 in S050AH
3-9
int:el..
ANL A,#data
Encoding:
MCS®-48 INSTRUCTION SET
Logical AND Accumulator with Immediate Mask
lo
1 a 1 1a a 1 1
1
53H
Description: This is a 2-cycle instruction. Data in the accumulator is logically ANDed
with an immediately-specified mask.
(A) AND data
Operation: (A) -
;'AND' ACC CONTENTS
;WITH MASK 10101111
;'AND' ACC CONTENTS
;WITH VALUE OF EXP
;'3 + XY/Y'
Examples: ANDID: ANL A,#OAFH
ANL A,#3 + X/Y
ANL BUS,#data*
Logical AND BUS with Immediate Mask
Encoding: /1 a a 1 /1 a a a
98H
1
Description: This is a 2-cycle instruction. Data on the BUS port is. logically ANDed
with an immediately-specified mask. This instruction assumes prior
specification of an 'OUTL BUS, A' instruction.
Operation: (BUS) -
(BUS) AND data
Example: ANDBUS: ANL BUS,#MASK
ANL Pp,#data
;'AND' BUS CONTENTS
;WITH MASK EQUAL VALUE
;OF SYMBOL 'MASK'
Logical AND Port 1-2 with Immediate Mask
99H-9AH
Encoding: /1 a a 1 1 1 . a p p I
Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with an
immediately-specified mask.
Operation: (Pp) -
p = 1-2
(Pp) AND DATA
Example: ANDP2: ANL P2,#OFOH
;'AND' PORT 2 CONTENTS
;WITH MASK 'Fa' HEX
;(CLEAR P20-23)
• For use with internal program memory ONLY.
3-10
in1'el"
ANLD Pp,A
MCS®-48 INSTRUCTION SET
Logical AND Port 4-7 with Accumulator Mask
Encoding: 11 0 0 1 11 1 P P 1
9CH-9FH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ANDed with the
digit mask contained in accumulator bits 0-3.
Operation: (Pp) - (Pp) AND (AO-3)
P = 4-7
Note: The mapping of port 'p' to opcode bits 0-1 is as follows:
1 0 Port
00
4
01
5
106
11
7
;'AND' PORT 4 CONTENTS
;WITH ACC BITS 0-3
Example: ANDP4: ANLD P4,A
CALL address
Encoding:
Subroutine Call
Ia10 a9 as 1 I0 1 0 0 I Ia7 a6 a5 a4 Ia3 a2 a1 aO I
Page
Hex Op Code
o
14
34
54
74
94
B4
D4
F4
1
2
3
4
5
6
7
Description: This is a 2-cycle instruction. The program counter and PSW bits 4-7 are
saved in the stack. The stack pointer (PSW bits 0-2) is updated. Program
control is then passed to the location specified by 'address'. PC bit 11 is
determined by the most recent SEL MB instruction.
A CALL cannot begin in locations 2046-2047 or 4094-4095. Execution
continues at the instruction following the CALL upon return from the
subroutine.
Operation: ((SP)) - (PC), (PSW 4 - 7 )
(SP) - (SP) + 1
(PCS- 10) - (addrS_1O)
(PCO-7) - ( addr O_7)
(PC11) - DBF
3-11
MCS®-48 INSTRUCTION SET
Example: Add three groups ~f two numbers. Put subtotals in locations 50, 51 and
total in location 52.
MOV RO,#50
;MOVE '50' DEC TO ADDRESS
;REGO
;MOVE CONTENTS OF REG 1
;TOACC
;ADD REG 2 TO ACC
;CALL SUBROUTINE 'SUBTOT'
;ADD REG 3 TO ACC
;ADD REG 4 TO AQC
;CALL SUBROUTINE 'SUBTOT'
;ADD REG 5 TO ACe
;ADD REG S TO ACC
;CALL SUBROUTINE 'SUBTOT'
;MOVE CONTENTS OF ACC TO
;LOCATION ADDRESSED BY
;REGO
;INCREMENT REG 0
;RETURN TO MAIN PROGRAM
BEGADD: MOV A,R1
ADD A,R2
CALL SUBTOT
ADDC A R3
ADDC A,R4
CALL SUBTOT
ADDCA,R5
ADDC A,RS
CALL SUBTOT
SUBTOT: MOV @RO,A
INC RO
RET
CLR A
Clear Accumulator
Encoding: lOb 1 0
I0 1 1 1 I
27H
Description: The contents of the accumulator are cleared to zero.
Operation: A CLR C
0
Cle~r Carry Bit
Encoding: 11 0 0 1.1 0 1
1 '1
97H
Description: During normal program execution, the carry bit can be set to one by the
ADD, ADDC, RLC, CPL C, RRC, and DAA insructions. This instruction'
resets the carry bit to zero.
Operation: C CLR F1
0
Clear Flag 1
Encoding: 11 0 1 0
I0 1 0 1 I
A5H
Description: Flag 1 is cleared to zero.
Operation: (F1) -
0
3-12
int:et
CLR FO
MCS®-48 INSTRUCTION SET
Clear Flag 0
I0 1 0 1 I
Encoding: 11 0 0 0
85H
Description: Flag 0 is cleared to zero.
Operation: (FO) CPL A
0
Complement Accumulator
Encoding:
I0 0 1 1 I 0 1 1 1 I
37H
Description: The contents of the accumulator are complemented. This is strictly a one's
complement. Each one is changed to zero and vice-versa.
Operation: (A) -
NOT (A)
Example: Assume accumulator contains 01101010.
CPLA: CPL A
;ACC CONTENTS ARE C,)MPLE·
;MENTED TO 10010101
CPL C
Complement Carry Bit
Encoding: 11 0 1 0
I0
1 1 1
I
A7H
Description: The setting of the carry bit is complemented; one is changed to zero, and
zero is changed to one.
Operation: (C) -
NOT (C)
Example: Set C to one; current setting is unknown.
CT01: CLR C
;C IS CLEARED TO ZERO
CPL C
;C IS SET TO ONE
CPL FO
Complement Flag 0
I
Encoding: 11 0 0 1 0 1 0 11
95H
Description: The setting of flag 0 is complemented; one is changed to zero, and zero is
changed to one.
Operation: FO CPL F1
NOT (FO)
Complement Flag 1
Encoding: 11 0 1 1
I0
1 0 1/
85H
Description: The setting of flag 1 is complemented; one is changed to zero, and zero is
changed to one.
Operation: (F1) -
NOT (F1)
3-13
intet
MCS~-48
INSTRUCTION SET
DA A Decimal Adjust Accumulator
I
I
Encoding: 0 1 0 1 0 1 1 1
I
57H
Description: The S-bit accumulator value is adjusted to form two 4-bit Binary Coded
Decimal (BCD) digits following the binary addition of BCD numbers.
The carry bit C is affected. If the contents of bits 0-3 are greater than nine,
or if AC is one, the accumulator is incremented by six.
The four high-order bits are then checked. If bits 4-7 exceed nine, or if
C is one, these bits are increased by six. If an overflow occurs, C is set
to one.
Example: Assume accumulator contains 10011011.
DA A
;ACC Adjusted to 00000001
;WITH CSET
C AC 7
43
0
0010011011
o0 0 00 1 10
ADD SIX TO BITS 0-7
o
101 0 0 001
o110
ADD SIX TO BITS 4-7
1 00 0 0 0 0 0 0 1
OVERFLOW TO C
DEC A Decrement Accumulator
Encoding:
I0 0 0 0 I0 1 1 1 1
07H
Description: The contents of the accumulator are decremented by one. The carry flag
is not affected.
Operation: (A) -
(A) -1
Example: Decrement contents of external data memory location 63.
MOV RO,#3FH
;MOVE '3F' HEX TO REG 0
MOVX A, @RO
;MOVE CONTENTS OF
;LOCATION 63 TO ACC
;DECREMENT ACC
DEC A
MOVX @RO,A
;MOVE CONTENTS OF ACC TO
;LOCATION 63 IN EXPANDED
;MEMORY
DEC Rr
Decrement Register
Encoding: 111 0 0 11 r r r
I
CSH-CFH
Description: The contents of working register 'r' are decremented ,by one.
Operation: (Rr) -
r = 0-7
(Rr) -1
Example: DECR1: DEC R1
;DECREMENT CONTENTS OF REG 1
3-14
inteL
DIS I
MCS®-48 INSTRUCTION SET
External Interrupt
Encoding: 1 0 0 0 1 10 1 0 1
I
15H
Description: External interrupts are disabled. A low signal on the interrupt input pin has
no effect.
DIS TCNTI
Disable Timer/Counter Interrupt
Encoding: 10 0 1 1 1 0 1 0 1 1
35H
Description: Timer/counter interrupts are disabled. Any pending timer interrupt request
is cleared. The interrupt sequence is not initiated by an overflow, but the
timer flag is set and time accumulation continues.
DJNZ Rr• address
Decrement Register and Test '
Encoding: 11 1 1 0 11 r r r 1
I a7
a6 a5 a4
I a3
a2 a1 aO
I
E8H-EFH
Description: This is a 2-cycle instruction. Register 'r' is decremented, then tested for
zero. If the register contains all zeros, program control falls through to the
next instruction. If the register contents are not zero, control jumps to the
specified 'address'.
The address in this case must evaluate to 8-bits, that is, the jump must be
to a location within the current 256-location page.
Example: (Rr) - (Rr) -1
r =0-7
If Rr not 0
(PCO-7) - addr
Note: A 12-bit address specification does not cause an error if the
DJNZ instruction and the jump target are on the same page. If the DJNZ
instruction begins in location 255 of a page, it must jump to a target
address on the following page.
Example: Increment values in data memory locations 50-54.
MOV RO,#50
;MOVE '50' DEC TO ADDRESS
;REG 0
;MOVE '5' DEC TO COUNTER
MOV R3,#5
;REG 3
INCRT: INC @RO
;INCREMENT CONTENTS OF
;LOCATION ADDRESSED BY
;REG 0
INC RO
;INCREMENT ADDRESS IN REG 0
DJNZ R3, INCRT
;DECREMENT REG 3 - JUMP TO
;'INCRT' IF REG 3 NONZERO
NEXT ;'NEXT' ROUTINE EXECUTED
;IF R3 IS ZERO
3-15
infel .
EN I
MCS~-48
INSTRUCTION SET
Enable External Interrupt .
Encoding: 10 0 0 0 10 1 0 1
I
05H
Description: External interrupts are enabled. A low signal on the interrupt input pin
initiates the interrupt sequence.
EN TCNTI
Enable Timer/Counter Interrupt
Encoding: 10 0
1 0 10 1 0 11
25H
Description: Timer/counter interrupts are enabled. An overflow of the timer/counter
initiates the interrupt sequence.
ENTO ClK
Enable Clock Output
Encoding: 10 1 1 1 10 1 01
I
75H
Description: The test 0 pin is enabled to act as the clock output. This function is
'
disabled by a system reset.
Example: EMTSTO: ENTO ClK
;ENABlE TO AS CLOCK OUTPUT
IN A,Pp Input Port or Data to Accumulator
Encoding: 10 0 0 0 11 0 P pi
09H-OAH
Description: This is a 2-cycle instruction. Data present on port 'p' is
transferred (read) to the accumulator.
p = 1-2
;INPUT PORT 1 CONTENTS TO ACC
;MOVE ACC CONTENTS TO REG 6
;INPUT PORT 2 CONTENTS TO ACC
;MOVE ACC CONTENTS TO REG 7
Operation: (A) - (Pp)
INP12: IN A,P1
MOV R6,A
INA,P2
MOV R7,A
INC A Increment Accumulator
Encoding: 10 0 0 1 1 0 1 1
11
17H
Description: The contents of the accumulator are incremented by one. Carry is not
affected.
Operation: (A) -
(A) +1
3-16
intel ~
MCS®-48 INSTRUCTION SET
Example: Increment contents of location 100 in external data memory.
INCA: MOV RO,#100
;MOVE '100' DEC TO ADDRESS REG 0
MOVX A,@RO
;MOVE CONTENTS OF LOCATION
;100TO ACC
INC A
;INCREMENT A
MOVX @RO,A
;MOVE ACC CONTENTS TO
;LOCATION 101
INC Rr
Increment Register
Encoding: 10 0 0 1 11 r r r
I
18H-1 FH
Description: The contents of working register 'r' are incremented by one.
Operation: (Rr) -
r'" 0-7
(Rr) + 1
Example: INCRO: INC RO
;INCREMENT CONTENTS OF REG 0
INC @R 1 Increment Data Memory Location
Encoding: 10 0 0 1 1 0 0 0 i
I
10H-11H
Description: The contents of the resident data memory location addressed by register 'i' bits
0-5** are incremented by one.
Operation: {(Ri)) -
«Ri)) + 1
i '" 0-1
;MOVE ONES TO REG 1
;INCREMENT LOCATION 63
Example: INCDM: MOV R1,#03FH
INC @R1
INS A,BUS· Strobed Input of BUS Data to Accumulator
Encoding: 10 0 0 0 11 0 0 0
I
OSH
Description: This is a 2-cycle instruction. Data present on the BUS port is transferred
(read) to the accumulator when the RD pulse is dropped. (Refer to section
on programming memory expansion for details.)
Operation: (A) -
(BUS)
Example: INPBUS: INS A,BUS
;INPUT BUS CONTENTS TO ACC
• For use with internal program memory ONLY.
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-17
infel .
MCSfIl-48 INSTRUCTION SET
JBb addr... Jump If Accumulator Bit II S.t
Encoding: \b2 b, bO ' 10 0 , 01
I a7 8S a5 84 la3 a2 a, aO I
Accumulator Bit Hex Op Code
o
'2
1
2
32
52
72
3
4
92
5
S
82- 02
F2
7
Delcrlptlon: This is a 2-cycle instruction. Control passes to the specified address if
accumulator bit 'b' is set to one.
-,
b= 0-7
If Bb = 1
If Bb = 0
;JUMP TO 'NEXT' ROUTINE
;IF ACC BIT 4 = 1
Operation:
(PCO-7) - addr
(PC) = (PC) + 2
Example: JB4IS1: JB4 NEXT
JC addrell Jump If Carry II Set
EncodIng:
I' , , , 10'
, 0
I 1a7 as 85 a4 I83 82 a, 80 I
FSH
Delcrlptlon: This is a 2-cycle instruction. Control passes to the specified address if the
carry bit is set to one.
Operation: (PCO-7) - 8ddr
(PC) = (PC) + 2
If C = ,
If C = 0
Example: JC1:- JC OVFLOW
;JUMP TO 'OVFLOW' ROUTINE
;IFC
=,
JFO address Jump If Flag Ols Set
I'
I
I I
I
I
EncodIng:
0 , , 0 , 1 0
87 as a5 a4 a3 82 81 aO
BSH
DescriptIon: This iS8 2-cycle instruction. Control passes to the specified address if
flag 0 is set to one.
Operation: (PCO-7) - 8ddr
(PC) =(PC) + 2
If FO = 1
If FO = 0
Example: JFOIS1: JFO TOTAL
;JUMP TO 'TOTAL' ROUTINE IF FO= 1
3-18
inteL
MCS®-4B INSTRUCTION SET
JF1 address
Jump If Flag 1 Is Set
Encoding: 10 1 1 1
I0 1 1 0 I
76H
Description: This is a 2-cycle instruction. Control passes to the specified address if
flag 1 is set to one.
If F1 = 1
If F1 = 0
Operation: (PCO-7) - addr
(PC) =(PC + 2)
;JUMP TO 'FILBUF'
;ROUTINE IF F1 = 1
Example: JF1IS1: JF1 FILBUF
JMP address
Encoding:
Direct Jump within 2K Block
Ia1 0
ag as 0
I0
1 0 0
I
Page
Hex Op Code
0
1
2
3
4
04
24
44
64
84
A4
C4
E4
5
6
7
Description: This is a 2-cycle instruction. Bits 0-10 of the program counter are replaced
with the directly-specified address. The setting of PC bit 11 is
determined by the most recent SELECT MB instruction.
Operation: (PCS-10) - addr S-10
(PCO-7) - addr 0-7
(PC11) - DBF
Example:' JMP SUBTOT
JMP $-6
;JUMP TO SUBROUTINE 'SUBTOT'
;JUMP TO INSTRUCTION SIX
;LOCATIONS BEFORE CURRENT
;LOCATION
;JUMP TO ADDRESS '2F' HEX
JMP 2FH
JMPP @A
Indirect Jump within Page
Encoding: 11 0 1 1 10 0 1 1 1
B3H
Description: This is a 2-cycle insruction. The contents of the program memory location
pointed to by the accumulator are substituted for the 'page' portion of the
program counter, (PC bits 0-7).
3-19
int:et
MCS®-48 INSTRUCTION SET
Operation: (PCO-7) -
«A))
Example: Assume accumulator contains OFH.
JMPPAG: JMPP @A
;JUMP TO ADDRESS STORED IN
;LOCATION 1SIN CURRENT PAGE
JNC address
Jump If Carry Is Not Set
Encoding: 11 1 1 0 1 0 1 1 0 1
1a7 a6 aSa4 1 a3 a2 a1 aO 1
E6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
the carry bit is not set, that is, equals zero.
If C = 0
If C = 1
Operation: (PCO-7) - addr
(PC) = (PC) + 2
;JUMP TO 'NOVFLO' ROUTINE
;IF C = O·
Example: JCO: JNC NOVFLO
JNI address
Jump If Interrupt Input Is Low
Encoding: 11 0 0 0 1 0 1 1 0 1
1a7 a6 as a4
I a3
a2 a1 aO
I
86H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
interrupt input signal is low (= 0), that is, an external interrupt has been
signaled. (This signal initiates an interrupt service sequence if the external
interrupt is enabled.)
If 1= 0
If I = 1
;JUMP TO 'EXTINT' ROUTINE
;IF I = 0
Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: LOC 3: JNI EXTINT
JNTO address
Encoding:
Jump If Test 0 is Low
I00 10 I0110
1
1a7 a6 as a41 a3 a2 a1 aO 1
26H
Description: This is a 2-cycle instruction. Control passes to the specified address, if the
test 0 signal is low.
IfTO = 0
If TO = 1
Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: JTOLOW: JNTO 60
;JUMP TO LOCATION 60 DEC
;IF TO = 0
3-20
intel .
JNT1 address
Encoding:
MCS®-48 INSTRUCTION SET
Jump If Test 1 Is Low
I0 1 0 0 I 0 1 1 0 1 Ia7 a6 a5 a4 Ia3 a2 a1 aO I
46H
. Description: This is a 2-cycle instruction. Control passes to the specified address, if
the test 1 signal is low.
If T1 =0
IfT1 = 1
Operation: (PCO-7) - addr
(PC) = (PC) + 2
JNZ Address
Jump If Accumulator Is Not Zero
Encoding: 11 0 0 1 1 0 1 1 0 1
Ia7 a6 a5 a4 l·a3 a2 a1 aO I
96H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
accumulator contents are nonzero at the time this instruction is executed.
If A¢ 0
IfA=O
Operation: (PCO-7) - addr
(PC) = (PC) + 2
;JUMP TO LOCATION 'AS' HEX
;IF ACC VALUE IS NONZERO
Example: JACCNO: JNZ OASH
JTF address
Jump If Timer Flag Is Set
Encoding: 10 0 0 1
I 0 1 1 0 I Ia7 a6 a5 a41 a3 a2 a1
aO 1
16H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
timer flag is set to one, that is, the timer/counter register has overflowed.
Testing the timer flag resets it to zero. (This overflow initiates an interrupt
service sequence if the timer-overflow interrupt is enabled.)
IfTF = 1
If TF = 0
Operation: (PCO-7) - addr
(PC) = (PC) + 2
;JUMP TO 'TIMER' ROUTINE
;IF TF = 1
Example: JTF1: JTF TIMER
JTO address
Encoding:
Jump If Tes.t 0 Is High
10
0 1 1
I0 1 1 0 I
36H
Description: This is a 2-cycle instruction. Control passes to the specified address if
the test 0 signal is high (= 1).
Operation: (PCO-7) - addr
(PC) = (PC) + 2
If TO
If TO
Example: JTOHI: JTO 53
=1
=0
;JUMP TO LOCATION 53 DEC
;IF TO = 1
3·21
inteL
MCS®-48 INSTRUCTION SET
JT1 address
Jump If Test 1 Is High
Encoding: 10 1 0 1 1 0 1 1 0
I
1a7 a6 as a41 a3 a2 a1 aO 1
S6H
Description: This is a 2-cycle instruction. Control passes to the specified address if the
test 1 signal is high (= 1).
IfT1 = 1
If T1 = 0
Operation: (PC O- 7) - addr
(PC) =: (PC) + 2
Example: JT1HI: JT1 COUNT
JZ address
;JUMP TO 'COUNT ROUTINE
;IF T1 = 1
Jump If Accumulator Is Zero
Encoding: 11 1 0 0 1 0 1 1 0 1
1a7 a6 as a4 1 a3 a2 a1 aO
I
C6H
Description: This is a 2-cycle instruction. Control passes to the specified address if
the accumulator contains all zeros at the time this instruction is executed.
If A =0
If A¥-1
Operation: (PCO-7) - addr
(PC) = (PC) + 2
Example: JACCO: JZ OA3H
MOV A,#data
Encoding:
;JUMP TO LOCATION 'A3' HEX
;IF ACC VALUE IS ZERO
Move Immediate Data to Accumulator
I0
23H
0 1 0 10 0 1 1 1
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is loaded
in the accumulator.
Operation: (A) -
data
Example: MOV A,#OA3H
MOV A,PSW
;MOVE 'A3' HEX TO ACC
Move PSW Contents to Accumulator
Encoding: 11 1 0 01 0 1 1 1 1
C7H
Description: The contents of the program status word are moved to the accumulator.
Operation: (A) -
(PSW)
Example: Jump to 'RB1SET' routine if PSW bank switch, bit 4, is set.
BSCHK: MOV A,PSW
;MOVE PSW CONTENTS TO ACC
JB4 RB1SET
;JUMP TO 'RB1SET IF ACC BIT 4
3-22
=1
infel·
MCS®-48 INSTRUCTION SET
MOV A,R r
Move Register Contents to Accumulator
Encoding: 11 1 1 1 11 r r r
I
F8H-FFH
Description: 8-bits of data are removed from working register 'r' into the accumulator.
Operation: (A) -
r =0-7
(Rr)
Example: MAR: MOV A,R3
MOV A,@Ri
;MOVE CONTENTS OF REG 3 TO ACC
Move Data Memory Contents to Accumulator
Encoding 111 1 1 10 0 0 i 1
FOH-F1H
Description: The contents of the resident data memory location addressed by bits 0-5** of
register 'i' are moved to the accumulator. Register 'i' contents are unaffected.
Operation: (A) -
i = 0-1
«Ri))
Example: Assume R1 contains 00110110.
MADM: MOV A,@R1
MOV A,T
;MOVE CONTENTS OF DATA MEM
;LOCATION 54 TO ACC
Move Timer/Counter Contents to Accumulator
Encoding: 10 1. 0 01 0 0 1 0 1
42H
Description: The contents of the timer/event-counter register are moved to the
accumulator.
Operation: (A) -
(T)
Example: Jump to "EXIT" routine when timer reaches '64', that is, when bit 6 setassuming initialization 64,
TIMCHK: MOV A,T
;MOVE TIMER CONTENTS TO ACe
JB6 EXIT
;JUMP TO 'EXIT' IF AeC BIT 6 = 1
MOV PSW,A
Move Accumulator Contents to PSW
I
Encoding: 11 1 0 1 0 11 1
I
D7H
Description: The contents of the accumulator are moved into the progam status word.
All condition bits and the stack pOinter are affected by this move.
Operation: (PSW) -
(A)
Example: Move up stack pointer by two memory locations, that is, increment the
pointer by one.
INCPTR: MOV A,PSW
;MOVE PSW CONTENTS TO ACC
INC A
;INCREMENT ACe BY ONE
MOV PSW,A
;MOVE Ace CONTENTS TO PSW
•• 0-5 in B04BAH/B74BH
0-6 in B049AH/B749H
0-7 in B050AH
3-23
intel .
MOV Rr,A
MCS@-48 INSTRUCTION SET
Move Accumulator Contents to Register
Encoding: 11 0 1 0 11 r r r 1
A8H-AFH
Description: The contents of the accumulator are moved to register 'r'.
Operation: (Rr) -
(A)
r = 0-7
Example: MRA: MOV RO,A
MOV Rr,#data
;MOVE CONTENTS OF ACC TO REG 0
Move Immediate Data to Register
B8H-BFH
Encoding: 11 0 1 1 11 r2 r1 rO 1
Description: This is a 2-cycle instruction. The 8-bit value specified by 'data' is moved to
register 'r'.
Operation: (Rr) -
r = 0-7
data
;THE VALUE OF THE SYMBOL
;'HEXTEN' IS MOVED INTO REG 4
:THE VALUE OF THE EXPRESSION
;'PI'(R'R)' IS MOVED INTO REG 5
;'AD' HEX IS MOVED INTO REG 6
Examples: MIR4: MOV R4,#HEXTEN
MIR 5: MOV R5,#PI'(R'R)
MIR 6: MOV R6, #OADH
MOV @ Ri,A
Move Accumulator Contents to Data Memory
Encoding: 11 0 '1 0 10 0 0 i
I
AOH-A1H
Description: The contents of the accumulator are moved to the resident data memory
location whose address is specified by bits 0-5" of register 'i'. Register 'i'
contents are unaffected.
Operation: «Ri» -
i
(A)
Example: Assume RO contains 00000111.
MDMA: MOV@RO,A
MOV @ Ri,#data
=0-1
;MOVE CONTENTS OF ACC TO
;LOCATION 7 (REG 7)
Move Immediate Data to Data memory
Encoding: 11 0 1
i 10 0 0 i
I Id7 d6 d5 d4 I d3 d2 d1 dO I
BOH-B1H
Description: This is a 2-cycle instruction, The 8-bit value specified by 'data' is moved
to the resident data memory location addressed by register 'i', bits 0-5",
Operation: «Ri» -
data
i =0-1
Examples: Move the hexadecimal value AC3F to locations 62-63,
;MOVE '62' DEC TO ADDR REG 0
MIDM: MOV RO,#62
MOV @RO,#OACH
;MOVE 'AC' HEX TO LOCATION 62
INC RO
;INCREMENT REG 0 to '63'
MOV @RO,#3FH
;MOVE '3F' HEX TO LOCATION 63
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3·24
MCS@-48 INSTRUCTION SET
MOV T,A
Move Accumulator Contents to Timer/Counter
Encoding: 10
I0 0 1 0 I
110
62H
Description: The contents of the accumulator are moved to the timer/event-counter
register.
Operation: (T) -
(A)
Example: Initialize and start event counter.
;CLEAR ACC TO ZEROS
INITEC: CLR A
MOVT,A
;MOVE ZEROS TO EVENT COUNTER
START CNT
;START COUNTER
MOVD A,Pp
Encoding:
Move Port 4-7 Data to Accumulator
10
0 0 0
11 1 P P 1
OCH-OFH
Description: This is a 2-cycle instruction. Data on 8243 port 'p' is moved (read) to
accumulator bits 0-3. Accumulator bits 4-7 are zeroed.
Operation: (0-3) (4-7) -
(Pp)
p
=4-7
0
Note: Bits 0-7 of the opcode are used to represent ports 4-7. If you are
coding in binary rather than assembly language, the mapping is as
follows:
Bits 1 0
Port
00
4
01
5
106
11
7
Example: INPPT5: MOVD A,P5
MOVD Pp,A
Encoding:
;MOVE PORT 5 DATA TO ACC
;BITS 0-3, ZERO ACC BITS 4-7
Move Accumulator Data to Port 4-7
10
0
1 1 11 1 P
P
I
3CH-3FH
Description: This is a 2-cycle instruction. Data in accumulator bits 0-3 is moved
(written) to 8243 port 'p'. Accumulator bits 4-7 are unaffected. (See NOTE
above regarding port mapping.)
Operation: (Pp) -
P = 4-7
(AO-3)
Example: Move data in accumulator to ports 4 and 5.
OUTP45: MOVD P4,A
SWAP A
MOVD P5,A
;MOVE ACC BITS 0-3 TO PORT 4
;EXCHANGE ACC BITS 0-3 and 4-7
;MOVE ACC BITS 0-3 TO PORT 5
3·25
intel .
MOVP A,@A
MCS®-48 INSTRUCTION SET
Move Current Page Data to Accumulator
Encoding: 11 0 1 0 1 0 0 1 1 1
A3H
Description: The contents of the program memory location addressed by the
accumulator are moved to the accumulator. Only bits 0-7 of the program
counter are affected" limiting the program memory reference to the
current page. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(A) - «PC»
Note: This is a 1-byte, 2-cycle instruction. If it appears in location 255 of a
program memory page, @A addresses a location in the following page.
Example: MOV12S: MOV A,#12S
MOVP A,@A
MOVP3 A,@A
;MOVE '12S' DEC TO ACC
;CONTENTS OF 129th LOCATION IN
;CURRENT PAGE ARE MOVED TO ACC
Move Page 3 Data to Accumulator
Encoding: 11 1 1 0 1 0 01 1 1
E3H
Description: This is a 2-cycle instruction. The contents of the program memory location
(within page 3) addressed by the accumulator are moved to the
accumulator. The program counter is restored following this operation.
Operation: (PCO-7) - (A)
(PCS-11) - 0011
(A) - «PC»
Example: Look up ASCII equivalent of hexadecimal code in table contained at the
beginning of page 3. Note that ASCII characters are designated by a
7-bit code; the eighth bit is always reset.
TABSCH: MOV A,#OBSH
;MOVE 'BS' HEX TO ACC (10111000)
ANL A,#7FH
;LOGICAL AND ACC TO MASK BIT
;7 (00111000)
;MOVE CONTENTS OF LOCATION '38'
MOVP3 A,@A
;HEX IN PAGE 3 TO ACC (ASCII '8')
Access cont~nts of location in page 3 labelled TAB1.
Assume current program location is not in page 3.
TABSCH: MOV A,#LOW TAB 1 ;ISOLATE BITS 0-7 OF LABEL
;ADDRESS VALUE
MOVP3 A,@A
;MOVE CONTENTS OF PAGE 3
;LOCATION LABELED 'TAB1' TO ACC
3-26
inteL
MCS®-48 INSTRUCTION SET
MOVX A,@Ri
Move External-Data-Memory Contents to Accumulator
Encoding: 11 0 0 0 1 0 0 0 i
I
80H-81 H
Description: This is a 2-cycle instruction. The contents of the external data memory
location addressed by register 'i' are moved to the accumulator. Register 'i'
contents are unaffected. A read pulse is generated.
Operation: (A) -
((Ri))
i
Example: Assume R1 contains 01110110.
MAXDM: MOVX A,@R1
MOVX@Rj,A
= 0-1
;MOVE CONTENTS OF LOCATION
;118 TO ACC
Move Accumulator Contents to External Data Memory
Encoding: 11 0 0 1 1 0 0 0 i
I
90H-91H
Description: This is a 2-cycle instruction. The contents of the accumulator are moved to
the external data memory location addressed by register 'i'. Register 'i'
contents are unaffected. A write pulse is generated.
Operation: «Ri)) -
A
i
Example: Assume RO contains 11000111.
MXDMA: MOVX @RO,A
NOP
= 0-1
;MOVE CONTENTS OF ACC TO
;LOCATION 199 IN EXPANDED
;DATA MEMORY
The NOP Instruction
Encoding: 10 0 0 0
I0 0 0 0 1
OOH
Description: No operation is performed. Execution continues with the following
instruction.
ORL A,R r
Logical OR Accumulator With Register Mask
Encoding: 10 1 0 0 11 r r r 1
48H-4FH
Description: Data in the accumulator is logically ORed with the mask contained in
working register 'r'.
Operation: (A) -
(A) OR (Rr)
r
Example: ORREG: ORL A,R4
=0-7
;'OR' ACC CONTENTS WITH
;MASK IN REG 4
3·27
intel .
ORL A,@Rj
MCS®-48 INSTRUCTION SET
Logical OR Accumulator With Memory Mask
'EnCOding: 10 1 0 0 10 0 0 i
I
40H-41H
Description: Data in the accumulator is logica"y ORed with the mask contained in the
resident data memory location referenced by register "i", bits 0-5**.
Operation: (A) -
(A) OR ((Ri))
i = 0-1
Example: ORDM: MOV RO,#3FH
ORL A,@RO
ORL A,#data
;MOVE '3F' HEX TO REG 0
;'OR' AC CONTENTS WITH MASK
;IN LOCATION 63
Logical OR Accumulator With Immediate Mask
Encoding: 10100100111
Id7 d6 dS d41 d3 d2 d1 dol
43H
Description: This is a 2-cycle instruction. Data in the accumulator is logically ORed with
an immediately-specified mask.
Operation: (A) -
(A) OR data
Example: ORID: ORL A,#'X'
;'OR' ACC CONTENTS WITH MASK
;01011000 (ASCII VALUE OF 'X')
ORL BUS,#data* Logical OR BUS With Immediate Mask
88H
Encoding: 11 0 0 0 11 0 0 0 1
Description: This is a 2-cycle instruction. Data on the BUS port is logically ORed with an
immediately-specified mask. This instruction assumes prior specification
on an 'OUTL BUS,A' instruction.
Operation: (BUS) -
(BUS) OR data
Example: . ORBUS: ORL BUS,#HEXMSK
ORL Pp, #data
:'OR' BUS CONTENTS WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXMSK'
Logical OR Port 1 or 2 With Immediate Mask
Encoding: 11 0 0 0 11 0 P pi
1d7 d6 dS d4 1 d3 d2 d1 dO
I
89H-8AH
Description: This is a 2-cycle instruction. Data on port 'p' is logically ORed with an
immediately-specified mask.
Operation: (Pp) -
(Pp) OR data
p
Example: ORP1: ORL P1, #OFFH
= 1-2
;'OR' PORT 1 CONTENTS WITH MASK
;'FF' HEX (SET PORT 1 TO ALL ONES)
* For use with internal program memory ONLY.
** 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 8050AH
3-28
int'eL
ORlD Pp,A
MCS®-48 INSTRUCTION SET
logical OR Port 4-7 With Accumulator Mask
Encoding: 11
De~cription:
a a a 11
1 P P
I
8CH-8FH
This is a 2-cycle instruction. Data on port 'p' is logically ORed with the
digit mask contained in accumulator bits 0-3.
Operation: (Pp) -
(Pp) OR (AO-3)
p
Example: ORP7: ORlD P7,A
=4-7
;'OR' PORT 7 CONTENTS WITH ACC
;BITS 0-3
OUTl BUS,A- Output Accumulator Data to BUS
Encoding: 10
a a a Ia a
1
aI
02H
D.escription: This is a 2-cycle instruction. Data residing in the
accumulator is transferred (written) to the BUS port and
latched. The latched data remains valid until altered by
another OUTl instruction. Any other instruction requiring
use of the BUS port (except INS) destroys the contents of
the BUS latch. This includes expanded memory operations
(such as the MOVX instruction). logical operations on
BUS data (AND, OR) assume the OUTl BUS,A instruction
has been issued previously.
Operation: (BUS) -
(A)
Example: OUTlBP: OUTl BUS, A
OUTl Pp,A
;OUTPUT ACC CONTENTS TO BUS
Output Accumulator Data to Port 1 or 2
Encoding: 1 a
a
1 1 11
a
p pi
39H-3AH
Description: This is a 2-cycle instruction. Data residing in the accumulator is transferred
(written) to port 'p' and latched.
Operation: (Pp) -
p = 1-2
(A)
Example: OUTlP: MOV A,R7
OUTl P2,A
MOV A, R6
OUTL P1,A
;MOVE REG 7 CONTENTS TO ACC
;OUTPUT ACC CONTENTS TO PORT 2
;MOV REG 6 CONTENTS TO ACC
;OUTPUT ACC CONTENTS TO PORT 1
• For use with internal program memory ONLY.
3-29
infel~
RET
MCS®-48 INSTRUCTION SET
Return Without PSW Restore
Encoding: 11 0 0 0 1 0 0 1 1/
83H
Description: This is a 2-cycle instruction. The stack pointer (pSW bits 0-2) is
decremented. The program counter is then restored from the stack. PSW
bits 4-7 are not restored.
Operation: (SP) + - (SP)-1
(PC) + - «SP))
RETR
Return with PSW Restore
Encoding: 11 0 0 1 1 0 0 1 1
I
93H
Description: This is a 2-cycle instruction. The stack pointer is decremented. The
program counter and bits 4-7 of the PSW are then restored from the stack.
Note that RETR should be used to return from an interrupt, but should
not be used within the interrupt service routine as it signals the end of an
interrupt routine by resetting the Interrupt in Progress flip-flop.
Operation: (SP) + - (SP)-1
(PC) + - «SP))
(pSW 4-7) - «SP))
3-30
intel~
RL A
MCS@-48INSTRUCTION SET
Rotate Left without Carry
Encoding: 11 1 1 0 1 0 1 1 1
I
E7H
Description: The contents of the accumulator are rotated left one bit. Bit 7 is rotated
into the bit 0 position.
Operation: (An + 1) (AO) -
(An)
(A7)
n = 0-6
Example: Assume accumulator contains 10110001.
RLNC: RL A
;NEW ACC CONTENTS ARE 01100011
RLC A
Rotate Left through Carry
I0
Encoding: 11 1 1 1
1 1 1
I
F7H
Description: The contents of the accumulator are rotated left one bit. Bit 7 replaces the
carry bit; the carry bit is rotatd into the bit 0 position.
Operation: (An + 1) n = 0-6
(An)
(AO) - (C)
(C) -(A7)
Example: Assume accumulator contains a 'signed' number; isolate sign without
changing value.
RLTC: CLR C
;CLEAR CARRY TO ZERO
;ROTATE ACC LEFT, SIGN
RLCA
;BIT (7) IS PLACED IN CARRY
RR A
;ROTATE ACC RIGHT - VALUE
;(BITS 0-6) IS RESTORED,
;CARRY UNCHANGED, BIT 7
;IS ZERO
RR A
Rotate Right without Carry
Encoding: 10 1 1 1
I0 1 1 1 1
77H
Description: The contents of the accumulator are rotated right one bit. Bit 0 is rotated
into the bit 7 position.
Operation: (An)
~
(A7) -
(An + 1)
(AO)
n
=0-6
Example: Assume accumulator contains 10110001.
RRNC: RR A
;NEW ACC CONTENTS ARE 11011000
3-31
int:et
MCS®-48 INSTRUCTION SET
----~-~~
~RC
A
..-~--~-~----------------------------
Rotate Right through Carry
Encoding: 10 1 1 0
I0 1 1 1 I
67H
Description: The contents of the accumulator are rotated right one bit. Bit 0 replaces the
carry bit; the carry bit is rotated into .the bit 7 position.
Operation: (An) -
(An + 1)
(A7) - (C)
(C) - (AO)
n = 0-6
Example: Assumecarry is not set and accumulator contains 10110001.
RRTC: RRC A
;CARRY IS SET AND ACC
;CONTAINS 01011000
SEL MB1
Select Memory Bank 1
Encoding: 11 1 1 1 1 0 1 0 1 1
F5H
Description: PC bit 11 is set to one on next JMP or CALL instruction. All references to
program memory addresses fall within the range 2048-4095.
Operation: (DBF) -
1
3-32
-
inteL
SEL RBO
MCS®-48 INSTRUCTION SET
Select Register Bank 0
I0
Encoding: 11 1 0 0
1 0 1
I
C5H
Description: PSW bit 4 is set to zero. References to working registers 0-7 address data
memory locations 0-7. This is the recommended setting for normal
program execution.
Operation: (BS) -
SEL RB1
0
Select Register Bank 1
I0 1 0 1 I
Encoding: [1 1 0 1
D5H
Description: PSW bit 4 is set to one. References to working registers 0-7 address data
memory locations 24-31. This is the recommended setting for interrupt service
routines, since locations 0-7 are left intact. The setting of PSW bit 4 in
effect at the time of an interrupt is restored by the RETR instruction when
the interrupt service routine is completed.
Operation: (BS) -
1
Example: Assume an external interrupt has occurred, control has passed to program
memory location 3, and PSW bit 4 was zero before the interrupt.
SEL RB1
MOV R7,#OFAH
;JUMP TO ROUTINE 'INIT' IF
;INTERRUPT INPUT IS ZERO
;MOVE ACC CONTENTS TO
;LOCATION 7
;SELECT REG BANK 1
;MOVE 'FA' HEX TO LOCATION 31
SEL RBO
MOV A,R7
RETR
;SELECT REG BANK 0
;RESTORE ACC FROM LOCATION 7
;RETURN - RESTORE PC AND PSW
Operation: LOC3: JNI INIT
INIT: MOV R7,A
STOP TCNT
Encoding:
Stop Timer/Event-Counter
I0
1 1 0
I0
1 0 1
I
65H
Description: This instruction is used to stop both time accumulation and event counting.
3-33
intel .
MCS~-48
INSTRUCTION SET
Example: Disable interrupt, but jump to interrupt routine after eight overflows and
stop timer. Count overflows in register 7.
START: DIS TCNTI
;DISABLE TIMER INTERRUPT
;CLEAR ACC TO ZEROS
CLRA
;MOVE ZEROS TO TIMER
MOVT,A
;MOVE ZEROS TO REG 7
MOV R7,A
STRTT
;START TiMER
MAIN: JTF COUNT
;JUMP TO ROUTINE 'COUNT'
;IF TF = 1 AND CLEAR TIMER FLAG
JMPMAIN
;CLOSE LOOP
;INCREMENT REG 7
COUNT: INC R7
MOVA,R7
;MOVE REG 7 CONTENTS TO ACC
;JUMP TO ROUTINE 'INT' IF ACC
JB31NT
;BIT 3 IS SET (REG 7 = 8)
;OTHERWISE RETURN TO ROUTINE
JMP MAIN
;MAIN
;STOPTIMER
;JUMP TO LOCATION 7 (TIMER)
;INTERRUPT ROUTINE
INT: STOP TCNT
JMP7H
STRT CNT
Start Event Conter
I
Encoding: 10 1 0 0 0 1 0 1
I
45H
DescrIptIon: The test 1 (T1) pin is enabled as the event-counter input and the counter
is started. The event-counter register is incremented with each high-to-Iow
transition on the T1 pin.
Example: Initialize and start event counter.
input.
STARTC: EN TCNTI
MOV A,#OFFH
MOVT,A
STRT CNT
3-34
Assume overflow is desired with first T1
;ENABLE COUNTER INTERRUPT
;MOVE 'FF'HEX (ONES) TO ACC
;MOVES ONES TO COUNTER
;ENABLE T1 AS COUNTER
;INPUT AND START
int:eL
STRT T
MCS®-48 INSTRUCTION SET
Start Timer
Encoding: 10 1 0 1
I0 1 0 1 I
55H
Description: Timer accumulation is initiated in the timer register. The register is
incremented every 32 instruction cycles. The prescaler which counts the
32 cycles is cleared but the timer register is not.
Example: Initialize and start timer.
STARTT: CLR A
MOV T,A
EN TCNTI
STRTT
SWAP A
;CLEAR ACC TO ZEROS
;MOVE ZEROS TO TIMER
;ENABLE TIMER INTERRUPT
;START TIMER
Swap Nibbles within Accumulator
Encoding: 10 1 0 0 \ 0 1 1 1 \
47H
Description: Bits 0-3 of the accumulator are swapped with bits 4-7 of the accumulator.
Operation: (A 4 - 7 ) ~ (AO-3)
Example: Pack bits 0-3 of locations 50-51 into location 50.
PCKDIG: MOV RO, #50
;MOVE '50' DEC TO REG 0
MOV R1, #51
;MOVE '51' DEC TO REG 1
XCHD A,@RO
;EXCHANGE BITS 0-3 OF ACC
;AND LOCATION 50
SWAP A
;SWAP BITS 0-3 AND 4-7 OF ACC
XCHD A,@R1
;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 51
MOV @RO,A
;MOVE CONTENTS OF ACC TO
;LOCATION 50
XCH A,R r
Exchange Accumulator-Register Contents
Encoding:
I0
0 1 0 \1 r r r
J
28H-2FH
Description: The contents of the accumulator and the contents of working register 'r'
are exchanged.
Operation: (A) ~ (Rr)
r
= 0-7
Example: Move PSW contents to Reg 7 without losing accumulator contents.
XCHAR7: XCH A,R7
;EXCHANGE CONTENTS OF REG 7
;AND ACC
MOV A, PSW
;MOVE PSW CONTENTS TO ACC
;EXCHANGE CONTENTS OF REG 7
XCH A,R7
'AND ACC AGAIN
3-35
MCS®-48 INSTRUCTION SET
XCH A,@Ri
Exchange Accumulator and Data Memory Contents
Encoding: 10 0 1 0 10 0 0 i
I
20H-21H
Description: The contents of the accumulator and the contents of the resident data
memory location addressed by bits 0-5** of register 'i' are exchanged.
Register 'i' contents are unaffected.
Operation: (A)
~
((Ri))
i = 0-1
Example: Decrement contents of location 52.
DEC52: MOV RO,#52
;MOVE '52' DEC TO ADDRESS REG 0
XCH A,@RO
;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52
DEC A
;DECREMENT ACC CONTENTS
XCH A,@RO
;EXCHANGE CONTENTS OF ACC
;AND LOCATION 52 AGAIN
XCHD A,@Ri
Exchange Accumulator and Data Memory 4-811 Data
I
Encoding: 10 0 1 1 0 0 0 i
I
30H-31 H
Description: This instruction exchanges bits 0-3 of the accumulator with bits 0-3 of
the data memory location addressed by bits 0-5** of register 'i'. Bits 4-7 of
the accumulator, bits 4-7 of the data memory location, and the contents of
register 'i' are unaffected.
Operation: (AO-3)
~
((RiO-3))
i
=0-1
Example: Assume program counter contents have been stacked in locations 22-23.
XCHNIB: MOV RO,#23
CLR A
XCHD A,@RO
;MOVE '23' DEC TO REG 0
;CLEAR ACC TO ZEROS
;EXCHANGE BITS 0-3 OF ACC AND
;LOCATION 23 (BTS 8-11 OF PC ARE
;ZEROED, ADDRESS REFERS
:TO PAGE 0)
XRL A,R r Logical XOR Accumulator With Register Mask
Encoding: 11 1 0 1 11 r r r
I
D8H-DFH
Description: Data in the accumulator is EXCLUSIVE ORed with the mask contained in
working register 'r'.
Operation: (A) -
r = 0-7
(A) XOR (Rr)
;'XOR' ACC CONTENTS WITH
;MASK IN REG 5
Example: XORREG: XRL A,R5
•• 0-5 in 8048AH/8748H
0-6 in 8049AH/8749H
0-7 in 80SOAH
3-36
infel .
XRL A,@Ri
MCS®-48 INSTRUCTION SET
Logical XOR Accumulator With Memory Mask
Encoding: 11 1 0 1 1 0 0 0 i 1
DOH-D1 H
Description: Data in the accumulator is EXCLUSIVE ORed with the mask contained in the
data memory location addressed by register 'i', bits 0-5:*
Operation: (A) .
i
(A) XOR ((Ri))
;MOVE '20' HEX TO REG 1
;'XOR' ACC CONTENTS WITH MASK
;IN LOCATION 32
Example: XORDM: MOV R1,#20H
XRL A,@R1
XRL A,#data
= 0-1
Logical XOR Accumulator With Immediate Mask
Encoding: 11 1 0 1
I0
D3H
0 1 11
Description: This is a 2-cycle instruction. Data in the accumulator is EXCLUSIVE ORed
with an immediately-specified mask.
Operation: (A) -
(A) XOR data
Example: XORID: XOR A,#HEXTEN
;XOR CONTENTS OF ACC WITH MASK
;EQUAL VALUE OF SYMBOL 'HEXTEN'
•• 0-5 in S04SAH/S74SH
0-6 in S049AH/S749H
0-7 in S050AH
3-37
MCS® . .48 Data Sheets
4
8243
MCS®-48 INPUTIOUTPUT EXPANDER
•
O°C TO 70°C Operation
PORT4
PSG
PORT 5
Vee
P51
P52
P53
P40
PlC1
PIC2
PORT 2
PORT6
PIC3
P50
CS
P61
PAOG
P23
P22
P21
P62
P63
P73
P72
P71
P70
P20
GND
270161-2
PORT 7
Figure 2. 8243 Pin
Configuration
270161-1
Figure 1. 8243 Block Diagram
4·1
November 1990
Order Number: 270161·001
intel~
8243
Table 1. Pin Description
Symbol
Pin No.
Function
PROG
7
Clock Input. A high to low transition on PROG signifies that address
and control are available on P20-P23, and a low to high transition
signifies that data is available on P20-P23.
CS
6
Chip Select Input. A high on CS inhibits any change of output or
internal status.
P20-P23
GND
11-8
12
P40-P43
2-5
P50-P53
P60-P63
P70-P73
1,23-21
20-17
13-16
Vee
24
Four (4) bit bi-directional port contains the address and control bits on
a high to low transition of PROG. During a low to high transition, P2
contains the data for a selected output port if a write operation, or the
data from a selected port before the low to high transition if a read
operation.
OV supply.
Four (4) bit bi-directional I/O ports.
May be programmed to be input (during read), low impedance latched
output(after write), or a tri-state (after read). Data on pins P20-P23
may be directly written, ANDed or ORed with previous data.
+5Vsupply.
either high or low when power is applied. The first
high to low transition of PROG causes the device to
exit power on mode. The power on sequence is initiated if Vee drops below 1V.
Instruction
Address
P21 P20
P23 P22
Code
Code
FUNCTIONAL DESCRIPTION
General Operation
The 8243 contains four 4-bit I/O ports which serve
as an extension of the on-chip I/O and are addressed as Ports 4-7. The following operations may
be performed on these ports:
0
0
0
0
1
• Transfer Accumulator to Port.
• Transfer Port to Accumulator.
• AND Accumulator to Port.
• OR Accumulator to Port.
Port 4
Port 5
Port 6
Port 7
0
0
1
1
0
1
0
Read
Write
ORlD
ANlD
Write Modes
All communication between the 8048 and the 8243
occurs over Port 2 (P20-P23) with timing provided
by an output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles:
The first containing the "op code" and port address
and the second containing the actual 4-bits of data.
A high to low transition of the PROG line indicates
that address is present while a low to high transition indicates the presence of data. Additional 8243's
may be added to the 4-bit bus and chip selected
using
additional
output
lines
from
the
8048/8748/8035.
Power On Initialization
The device has three write modes. MOVD Pi, A directly writes new data into the selected port and old
data is lost. ORLD Pi, A takes new data, OR's it with
the old data and then writes it to the port, ANLD Pi,
A takes new data, AND's it with the old data and
then writes it to the port. Operation code and port
address are latched from the input Port 2 on the high
to low transition of the PROG pin. On the low to high
transition of PROG data on Port 2 is transferred to
the logic block of the specified output port.
After the logic manipulation is performed, the data is
latched and outputed. The old data remains latched
until new valid outputs are entered.
Read Mode
Initial application of power to the device forces input/ output Ports 4, 5, 6, and 7 to the tri-state and
Port 2 to the input mode. The PROG pin may be
The device has one read mode. The operation code
and port address are latched from the input Port 2
4-2
int'et
8243
on the high to low transition of the PROG pin. As
soon as the read operation and port address are
decoded, the appropriate outputs are tri-stated, and
the input buffers switched on. The read operation is
terminated by a low to high transition of the PROG
pin. The port (4, 5, 6 or 7) that was selected is
switched to the tri-stated mode while Port 2 is returned to the input mode.
Normally, a port will be in an output (write mode) or
input (read mode). If modes are changed during operation, the first read following a write should be ignored; all following reads are valid. This is to allow
the external driver on the port to settle after the first
read instruction removes the low impedance drive
from the 8243 output. A read of any port will leave
that port in a high impedance state.
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias ...... O·C to 70'C
Storage Temperature .......... - 6S'C to
+ 1S0'C
Voltage on Any Pin
with Respect to Ground .......... - O.SV to
+ 7V
• WARNING: Stressing the device beyond the ''Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation ........................ 1 Watt
D.C. CHARACTERISTICS TA = O'Cto 70'C, Vee = sv ± 10%
Symbol
Parameter
Min
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL1
Output Low Voltage Ports 4-7
VOL2
Output Low Voltage Port 7
VOH1
Output High Voltage Ports 4-7
2.4
Vil
Typ
Max
Units
0.8
V
Vee
+ 0.5
V
0.45
V
1
V
V
IIl1
Input Leakage Ports 4-7
-10
20
,.,.A
IIl2
Input Leakage Port 2, CS, PROG
-10
10
,.,.A
VOl3
Output Low Voltage Port 2
Icc
Vee Supply Current
VOH2
Output Voltage Port 2
IOl
Sum of All10l From 16 Outputs
10
..
4-3
= 4.5 rnA'
IOL = 20 rnA
IOH = 240,.,.A
Yin = Vee to OV
Yin = Vee toOV
IOL = 0.6 rnA
IOl
0.45
V
20
rnA
(Note 1)
72
rnA
4.5 rnA Each Pin
2.4
"
'Refer to Figure 3 for additional Sink current capability.
Test
Conditions
IOH
=
100,.,.A
intel .
8243
A.C. CHARACTERISTICS
Symbol
. tA
TA
= 0·Cto70·C, vcc = 5V ±
Parameter
Units
Test Conditions
50
ns
80pF Load
Min
Code Valid before PROG
10%
Max
ts
Code Valid after PROG
60
ns
20pF Load
Ie
Data Valid before PROG
200
ns
80pF Load
to
Data Valid after PROG
20
ns
20pF Load
tH
Floating after PROG
0
ns
20pF Load
150
tK
PROG Negative Pulse Width
700
ns
tcs
CS Valid before/after PROG
50
ns
tpo
Ports 4-7 Valid after PROG
tLP1
Ports 4-7 Valid before/after PROG
tACC
Port 2 Valid after PROG
700
100
ns
100 pF Load
ns
650
80pF Load
ns
NOTE:
1. Icc (-40"C to 85·C EXPRESS options) 15 mA typical/25 mA maximum.
"'X:: > ~-~. <~: x. ___
2.4 - - - ,
0.45----
_
270161-3
A.C. Testing: Inputs are driven at 2.4V for a logic "1" and 0.45Vfora logic "0". Output timing measurements are made at 2.0V for logic "1"
and O.SV for a logic "0".
4-4
intet
8243
WAVEFORMS
PAOG
~
PORT2
_______________ IK ______________
-'~
FLOAT
FLOAT
PORT2
PORTS 4-7
OUTPUT
VALID
PREVIOUS OUTPUT VALID
PORTS 4-7
INPUT VALID
ICS
ICS
270161-4
4·5
int:el..
8243
125
100
C
!
::;
9
.
..
::!.
75
zOJ
a:
a:
~
u
z
;;;
...
GUARANTEED WORST CASE
OF ANY 1/0 PORT PIN va. TOTAL
SINK CURRENT OF All PINS
50
~
..
0
25
13
MAXIMUM SINK CURRENT ON ANY PIN @ .45V
MAXIMUM 10l WORST CASE PIN (mAl
270161-5
Figure 3. 8243 Current Sink Capability
NOTE:
A 10 to 50 KO pullup resistor to + 5V should be
added to 8243 outputs when driving to 5V CMOS
directly.
Sink Capability
The 8243 can sink 5 mA @ 0.45V on each of its 16
110 lines simultaneously. If, however, all lines are
not sinking simultaneously or all lines are not fully
loaded, the drive capability of any individual line increases as is shown by. the accompanying curve.
Example: This example shows how the use of the
20 mA sink capability of Port 7 affects the
sinking capability of the other I/O lines.
An 8243 will drive the following loads
simultaneously.
2 loads-20 mA @ 1V (Port 7 only)
For example, if only 5 of the 16 lines are to sink
current at one time, the curve shows that each of
those 5 lines is capable of sinking 9 mA @ 0.45V (if
any lines are to sink 9. mA the total IOL must not
exceed 45 mA or five 9 mA loads).
8 10ads-4 mA
Example: How many pins can drive 5 TTL loads
(1.6 mAl assuming .remaining pins are unloaded?
IOL = 5
x
@
6 loads-3.2 mA
0.45V
@
0.45V
Is this within the specified limits?
elOL = (2 x 20)
= 91.2 mA.
1.6 mA = 8 mA
+
(8 X 4)
+
(6 X 3.2)
From the curve: for IOL = 4 mA, elOL ~
93 mAo Since 91.2 mA < 93 mA the loads
are within specified limits.
Although the 20 mA @ 1V loads are used
in calculating elOL' it is the largest current
required @ 0.45V which determines the
maximum allowable eIOL.
elOL = 60 mA from curve
# pins = 60 mA -7- 8 mA/pin = 7.5 = 7
In this case, 7 lines can sink 8 mA for a
total of 56 mA. This leaves 4 mA sink current capability which can be divided in any
way among the remaining 8 I/O lines of
the 8243.
4-6
intaL
8243
n
-">
C5
A- 20
110
"
-y
.4
.ROG
AV
8048
4
.ROG
v
110
A
3
P5
J ~~:JT5
4
8243
,) 110
A
.20-.23
P6
4
.7
4
DATA IN
4
.2
-y
110
-) 110
270161-6
Figure 4. Expander Interface
.ROG
'20·P23
~\ ....... _ _ _--oJ/
---{\",_ _ _
JX\",_____-J)~---
ADDRESS 14·81T51
BITS 3,2
BITS 1,0
00 } READ
01
WRITE
10 DR
11
AND
00
01 } PORT
10
ADDRESS
11
DATA 14-BIT51
270161-7
Figure 5. Output Expander Timing
3243
BUS
PORT 1
8048
PORT 2
PROG~---------------~----~--------~----------------~--------------~
270161-8 _
k -______________________________________________________________________________
Figure 6. Using Multiple 8243'5
4-7
P8748H/P8749H
8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
HMOS SINGLE-COMPONENT 8-BIT
MICROCONTROLLER
•
•
•
•
•
ROMs Using 21V
• Programmable
Easily Expandable Memory and I/O
• Up to 1.36 p,s Instruction Cycle All
• Instructions 1 or 2 Cycles
High Performance HMOS II
Interval Time/Event Counter
Two Single Level Interrupts
Single 5-Volt Supply
Over 96 Instructions; 90% Single Byte
The Intel MCS®-48 family are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.
The family contains 27 I/O lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems
that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcontrollers are available in both masked ROM and ROMless versions as well as a new version,
The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
while providing the flexibility of a device that can be programmed at the time of requirement and to the desired
data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
times and code risks.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting of mostly single byte instructions and no instructions over 2 bytes in length.
Memory
RAM STANDBY
B050AH
Device
4KxBROM
256xB RAM
yes
B049AH
2KxB ROM
12BxB RAM
yes
B04BAH
1KxBROM
64xBRAM
yes
B040AHL
None
256 xB RAM
yes
B039AHL
None
12BxBRAM
yes
64xBRAM
yes
Internal
B035AHL
None
PB749H
2K x B Programmable ROM
12B x B RAM
no
PB74BH
1K x B Programmable ROM
64xBRAM
no
270053-1
Figure 1. Block Diagram
270053-2
Figure 2. Logic Symbol
4-8
August 1989
Order Number: 270053·003
int:el..
MCS®-48
It;;
~ N
~ -~
0
~ ~ ~
\VlW!;(I-OUO_NNN
VI«
TO
XTAL 1
XTAL 2
RESET
5S
INT
EA
AD
PSEN
WALE
DBO
OB,
DB2
DB3
DB.
DBS
DB6
DB7
x
I-
Z
>
I-
~
~
~
Vee
I
2
TI
P27
P26
P25
P2.
P17
PI6
PIS
PI.
PI3
PI2
P11
PIO
VDO
PROG
P23
•
iHT
39
P2.'
EA
R5
PSEN
ViR
NC
10
8049AH/8039AHL
8050AH/B040AHL
44- PIN
PLCC
P1.4
NC
ALE
P1.3
OBO
OBI
Top Vltlw
082
Looking down on PC Board
PI.2
Pl..
083
1819202122232425262728
V55 -=_---':.:.r
270053-3
270053-14
Figure 3. Pin Configuration
Figure 4. Pad Configuration
Table 1. Pin Description
Symbol
Pin
No.
VSS
20
VDD
26
Function
Circuit GND potential.
Device
All
+ 5V during normal operation.
All
low power standby pin.
8048AH
8035AHl
8049AH
8039AHl
8050AH
8040AHl
Programming power supply (+ 21 V).
P8748H
P8749H
+ 5V during operation and programming.
Vee
40
Main power supply;
PROG
25
Output strobe for 8243 liD expander.
Program pulse
(+ 18V) input pin During Programming.
All
All
P8748H
P8749H
P10-P17
Port 1
27-34
8-bit quasi-bidirectional port.
All
P20-P23
P24-P27
Port 2
21-24
35-38
8-bit quasi-bidirectional port. P20-P23 contain the four high order
program counter bits during an external program memory fetch and
serve as a 4-bit liD expander bus for 8243.
All
DBO-DB7
BUS
12-19
True bidirectional port which can be written or read synchronously
using the RD, WR strobes. The port can also be statically latched.
Contains the 8 low order program counter bits during an external
program memory fetch, and receives the addressed instruction under
the control of PSEN. Also contains the address and data during an
external RAM data store instruction, under control of ALE, RD, and
WR.
All
Input pin testable using the conditional transfer instruction JTO and
JNTO. TO can be designated as a clock output using ENTO ClK
instruction.
All
Used during programming.
P8748H
P8749H
TO
1
4-9
int:et
MCS®·48
Table 1. Pin Description (Continued)
Symbol
Pin
No.
T1
39
Input pin testable using the JT1, and JNT1 instructions. Can be
designated the timer/counter input using the STRT CNT instruction.
All
INT
6
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction.
(Active low) interrupt must remain low for at least 3 machine cycles for
proper operation.
All
RD
B
Output strobe activated during a BUS read. Can be used to enable
data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low)
All
RESET
4
Input which is used to initialize the processor. (Active low) (Non TIL
VI H)
Used during"power down.
All
Function
Device
B04BAH
B035ARL
B049AH
B039AHL
B050AH
B040AHL
Used during programming.
PB74BH
PB749H
Used during ROM verification.
B04BAH
PB74BH
B049AH
PB749H
B050AH
WR
10
Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
All
ALE
11
Address latch enable. This signaroccurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
All
PSEN
9
Program store enable. This output occurs only during a fetch to
external program memory. (Active low)
All
SS
5
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction.
All
(Active low) Used in sync mode.
B04BAH
B035AHL
B049AH
B039AHL
B050AH
B040AHL
External access input which forces all program memory fetches to
reference external memory. Useful for emulation and debug. (Active
high)
All
Used during (1BV) programming.
PB74BH
PB749H
Used during ROM verification (12V).
B04BAH
B049AH
B050AH
One side of crystal input for internal oscillator. Also input for external
source. (Non TIL VIH)
All
EA
XTAL1
7
2
""
XTAL2
3
Other side of crystal input.
All
4-10
int:el..
MCS®-48
Table 2. Instruction Set
r------------------------------.
Input/Output
Accumulator
Mnemonic
ADDA,R
ADD A, @R
Description .
Add register to A
Add data memory
toA
ADD A, #data Add immediate to A
ADDCA,R
Add register with
carry
ADDCA,@R
Add data memory
with carry
ADDC A, #data Add immediate with
carry
ANLA, R
And register to A
ANLA, @R
And data memory
toA
ANLA, #data And immediate to A
ORLA, R
Or register to A
ORLA, @R
Or data memory
toA
ORLA, #data Or immediate to A
XRLA, R
Exclusive or register.
toA
XRLA, @R
Exclusive or data
memory to A
XRLA, #data Exclusive or
immediate to A
IncrementA
INCA
DECA
Decrement A
CLRA
Clear A
CPLA
Complement A
DAA
Decimal adjust A
Swap nibbles of A
SWAP A
RLA
Rotate A left
RLCA
Rotate A left
through carry
RRA
Rotate A right
RRCA
Rotate A right
through carry
Bytes Cycles
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mnemonic
Description
INA,P
OUTLP,A
ANLP, #data
Input port to A
Output A to port
And immediate to
port
ORL P, #data
Or immediate to
port
Input BUS to A
INS A, BUS
OUTLBUS,A
Output A to BUS
ANL BUS, #data And immediate to
BUS
ORL BUS, # data Or immediate to
BUS
Input expander port
MOVDA, P
toA
MOVDP,A
Output A to
expander port
And A to expander
ANLDP,A
port
Or A to expander
ORLDP,A
port
Bytes Cycles
2
2
2
2
2
2
1
2
2
2
2
2
2
1
1
2
2
2
2
Registers
Mnemonic
INCR
INC@R
DECR
Description
Increment register
Increment data memory
Decrement register
Bytes Cycles
1
1
1
Branch
Mnemonic
Description
JMPaddr
Jump unconditional
Jump indirect
JMPP@A
DJNZ R, addr Decrement register
and skip
JC addr
Jump on carry = 1
JNCaddr
Jump on carry == 0
JZ addr
Jump on Azero
Jump on A not zero
JNZ addr
JTO addr
Jump onTO = 1
Jump onTO = 0
JNTO addr
JT1 addr
Jump on T1 = 1
Jump on T1 = 0
JNT1 addr
JFO addr
Jump on FO = 1
Jump on F1 = 1
JF1 addr
JTF addr
Jump on timer flag
JNI addr
Jump on INT = 0
Jump on accumulator
JBb addr
bit
1
1
4-11
Bytes Cycles
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
MCS@·48
Table 2. Instruction Set (Continued)
r--------------------------------,
Subroutine
Mnemonic
Description
CALLaddr
RET
RETR
Jump to subroutine
Return
Return and restore
status
r------------------------------~
Timer/Counter
Bytes Cycles
2
2
2
2
1
1
Flags
Mnemonic
CLI~ C
CPLC
CLRFO
CPLFO
CLR F1
CPLF1
Description
Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
1
1
'1
1
1
1
1
1
1
MovA;R
MOVA,@R
Description
Move register to A
Move data memory
toA
MOVA, #data Move immediate to
A
MOVR,A
Move A to register
MOV@R,A
Move A to data
memory
MOVR, #data Move immediate to
register
MOV @R, #data Move immediate to
data memory
MOVA,PSW
MovePSWtoA
MOVPSW,A
MoveAtoPSW
XCHA,R
Exchange A and
register
XCHA,@R
Exchange A and
data memory
XCHDA,@R
Exchange nibble of
A and data memory
MOVXA,@R
Move external data
memory to A
MOVX@R,A
Move A to external
, data memory
MOVPA,@A
Move to A from
,current page
MOVP3A,@A Move to A from
page 3
1
1
2
2
2
2
2
2
Bytes Cycles
Mnemonic
Description
1
1
1
1
1
1
1
1
1
1
1
1
Bytes Cycles
ENI
Enable external
interrupt
DIS I
Disable external
interrupt
SELRBO
Select register bank 0
Select register bank 1
SELRB1
SELMBO Select memory bank 0
Select memory bank 1
SELMB1
ENTOCLK Enable clock output
onTO
Bytes Cycles
1
1
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/
counter interrupt
Disable timer/
counter interrupt
Control
Data Moves
Mnemonic
Description
MOVA, T
MOVT,A
STRTT
STRTCNT
STOP TCNT
EN TCNTI
DIS TCNTI
Bytes Cycles
1
1
1
Mnemonic
2
2
2
2
4-12
1
1
Mnemonic
Description
Bytes
Cycles
NOP
No operation
1
1
infel .
MCS®·48
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Case Temperature Under Bias ....... O·C to + 70·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent. damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature .......... -6S·C to + 150·C
Voltage on any Pin with Respect
to Ground ...................... - O.SV to + 7V
Power Dissipation .......................... 1.SW
D.C. CHARACTERISTICS
-
Symbol
TA
=
O·Cto +70·C;Vee
=
Voo
Limits
Parameter
Min
Typ
=
SV ±10%;Vss
Unit
=
OV
Test Conditions .
Device
Max
Vil
Input Low Voltage (All
Except RESET, X1, X2)
-0.5
0.8
V
All
VIl1
Input Low Voltage
(RESET, X1, X2)
-0.5
0.6
V
All
VIH
Input High Voltage
(All Except XTAL1,
XTAL2, RESET)
2.0
Vee
V
All
VIH1
Input High Voltage
(X1, X2, RESET)
3.8
Vee
V
All
VOL
Output Low Voltage
(BUS)
0.45
V
IOl
=
2.0mA
All
VOl1
Output Low Voltage
(RD, WR, PSEN, ALE)
0.45
V
IOl
=
1.8mA
All
VOl2
Output Low Voltage
(PROG)
0.45
V
IOl = 1.0mA
All
VOl3
Output Low Voltage
(All Other Outputs)
0.45
V
IOl = 1.6mA
All
VOH
Output High Voltage
(BUS)
2.4
V
IOH
=
-400/LA
All
VOH1
Output High Voltage
(RD, WR, PSEN, ALE)
2.4
V
IOH
=
-100 /LA
All
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH
=
-40/LA
All
4-13
intel·
MCS@·48
D.C. CHARACTERISTICS TA
Symbol
= O·Cto +70·C;Vee = voo = 5V ±10%;Vss = OV(Continued)"
limits
Parameter
Min
1L1
Leakage Current
(T1,INT).
IUl
Input Leakage Current
(P10-P17, P20-P27,
EA, SS)
IU2
Input Leakage Current
RESET
ILO
Leakage Current
(BUS, TO) (High
Impedance State)
100
Voo Supply Current
(RAM Standby)
100 +
Typ
Unit
Test Conditions
±10
/k A
Vss :5: VIN :5: Vee
All
-500
/k A
Vss + 0.45 :5: VIN :5: Vee
All
-300
/k A
Vss :5: VIN :5: 3.S
All
±10
/k A
Vss :5: VIN :5: Vee
All
3
5
mA
S04SAH
S035AHL
4
7
mA
S049AH
S039AHL
5
10
mA
S050AH
S040AHL
30
65
mA
S04SAH
S035AHL
35
70
mA
S049AH
S039AHL
40
SO
mA
S050AH
S040AHL
30
100
mA
PS74SH
50
110
mA
PS749H
2.2
5.5
V
2.2
5.5
V
S049AH
S039AH
2.2
5.5
V
S050AH
S040AHL
-10
Total Supply Current"
lee
Voo
·ICC
RAM Standby Voltage
Device
Max
+ 100 are measured with all outputs In their high Impedance stete; m:m low; 11
4-14
Standby Mode Reset
:5:VIL1
MHz crystal applied;
S04SAH
S035AH
m, ~, and EA floallOg.
intel"
MCS®-48
A.C. CHARACTERISTICS TA = O·C to + 70·C; Vcc = Voo = 5V ± 10%; VSS = OV
11 MHz
f (t)
(Note 3)
Min
Max
Clock Period
1/xtal freq
90.9
1000
tLL
ALE Pulse Width
3.5t-170
150
ns
tAL
Addr Setup to ALE
2t-110
70
ns
Symbol
t
Parameter
tLA
Addr Hold from ALE
tCCt
Control Pulse Width (RD, WR)
tCC2
Control Pulse Width (PSEN)
tow
Data Setup before WR
two
Data Hold after WR
tOR
Data Hold (RD, PSEN)
tROt
RD to Data in
tR02
PSEN to Data in
Unit
Conditions
(Note 1)
ns
(Note 3)
t-40
50
ns
7.5t-200
480
ns
6t-200
350
ns
6.5t-200
390
ns
t-50
40
1.5t-30
0
ns
110
ns
6t-170
375
ns
4.5t-170
240
ns
tAW
Addr Setup to WR
tAOt
Addr Setup to Data (RD)
10.5t-220
5t-150
tA02
Addr Setup to Data (PSEN)
7.5t-200
tAFCt
Addr Float to RD, WR
300
ns
730
ns
460
ns
140
ns
(Note 2)
0.5t-40
10
ns
(Note 2)
3t-75
200
ns
1.5t-75
60
ns
2t-40
tAFC2
Addr Float to PSEN
tLAFCt
ALE to Control (RD, WR)
tLAFC2
ALE to Control (PSEN)
tCAl
Control to ALE (RD, WR, PROG)
t-65
25
ns
tCA2
Control to ALE (PSEN)
4t-70
290
ns
tcp
Port Control Setup to PROG
1.5t-80
50
ns
tpc
Port Control Hold to PROG
4t-260
100
ns
tpR
PROG to P2 Input Valid
tpF
Input Data Hold from PROG
top
(Note 2)
8.5t-120
650
ns
140
ns
1.5t
0
Output Data Setup
6t-290
250
ns
tpo
Output Data Hold
1.5t-90
40
ns
tpp
PROG Pulse Width
10.5t-250
700
ns
tpL
Port 2 1/0 Setup to ALE
4t-200
160
ns
tLP
Port 2 1/0 Hold to ALE
0.5t-30
15
tpv
Port Output from ALE
4.5t+ 100
tOPRR
TO Rep Rate
3t
270
ley
Cycle Time
15t
1.36
ns
5.0
ns
15.0
)A-s
ns
NOTES:
1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance Load 20 pF
3. fIt) assumes 50% duty cycle on Xt, X2. Max clock period is for a 1 MHz crystal input.
4-15
inteL
MCS®-48
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY
READ FROM EXTERNAL DATA MEMORY
-..1
'LAFe.
ALE
r-
Ro
270053-5
270053-4
WRITE TO EXTERNAL DATA MEMORY
INPUT AND OUTPUT FOR A.C. TESTS
x==
X
2.4V - - - - ,
2.0 ... TEST POINTS'Z,O
O.45Y _ _ _-.J. ,0.';
"'0.8.
270053-7
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Output timing measurements are made at 2.0V for a
logic "1" and 0.8V for a logic "0".
270053-6
PORT lIPORT 2 TIMING
2ND
CYCLE
ALE
PSEN
P20-23
I
PCH
OUTPUT
P,?FlT 20-23 DATA
NEW P20-23 DATA
I
PCH
I
P24~27
P10-17
PORT 24-27, PORT 10-17 DATA
NEW PORT
OUTPUT
~ATA
'LP
--II----'LA---·~I··-
EXPANDEA
PORT
OUTPUT
PCH
~
I r-----i
_ _ _ _ _ _ _ _ _ _J
~
______
-J~
______
~-J
I
I
EXPANDER
PORT
INPUT
PCH
PROG
270053-8
4-16
intel .
MCS®-48
CRYSTAL OSCILLATOR MODE
CERAMIC RESONATOR MODE
C1
C1
r-_-'__--'-___2-j XTAL1
~ ;-~~'~T~
JE~!
f-_____--.-___2-j XTAl1
~(
J- ca.D"'~~
C2
=-
I
t---'--.L-.--::-J
1-11
XTAL2
C3
C3
270053-9
Cl = 5 pF ±Yz pF + (STRAY < 5 pF)
C2 = (CRYSTAL + STAY) < 8 pF
C3 = 20pF ±1 pF + (STRAY < 5pF)
Crystal series resistance should be less lhan 300 at 11 MHz; less
than 750 at 6 MHz; less than 1800 at 3.6 MHz.
XTAL2
3
270053-10
DRIVING FROM EXTERNAL SOURCE
+5V
47011
»-.----=-1 XTAL1
+5V
TTL OPEN
COLLECTOR
47011
GATES
'-----'--""'3 XTAL2
270053-11
For XTAL1 and XTAl2 define "high" as voltages above I.BV and
"low" as voltages below I.BV. The duty cycle requirements for
externally driving XTAL1 and XTAL2 using the circuits shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAl2 must be high 35-65% of the period. Rise and fall times
must be faster than 20 ns.
4-17
infel·
MCS®-48
PROGRAMMING AND VERIFYING THE
P8749H/48H PROGRAMMABLE ROM
WARNING:
An attempt to program a missocketed P8749H/48H
will result in severe damage to the part. An indication
of a properly socketed part is the appearance of the
ALE clock output. The lack of this clock may be
used to disable the programmer.
Programming Verification
In brief, the programming process consists of: activating the program mode,. applying an address,
latching the address, applying data, and applying a
programming pulse. Each word is programmed completely before moving on to the next and is followed
by a verification step. The following is a list of the
pins used for programming and a description of their
functions:
Pin
XTAL1
XTAL2
RESET
TO
EA
BUS
The ProgramlVerify sequence is:
h Voo = SV, Clock applied or internal oscillator
operating, RESET =. OV, TO = SV, EA = 5V,
BUS and PROG floating. P10 and P11 must be
tied to ground.
2. Insert P8749H/48H in programming socket
3. TO = OV (select program mode)
Function
Clock Input (3 to 4.0 MHz)
4. EA = 18V (activate program mode)
(
S. Address applied to BUS and P20-22
6. RESET = SV (latch address)
Initialization and Address Latching
Selection of Program or Verifying Mode
Activation of ProgramlVerify Modes
Address and Data Input
Data Output During Verify
P20-P22 Address Input
Programming Power Supply
Voo
PROG
Program Pulse Input
7. Data applied to BUS
8. Voo = 21V (programming power)
9. PROG = Vee or float followed by one 50 ms
pulse to 18V
10. Voo = SV
11. TO = SV (verify mode)
12. Read and verify data on BUS
13. TO
=
OV
14. RESET
= OV and repeat from step S
1S. Programmer should be at conditions of step 1
when P8749H/48H is removed from socket.
NOTE:
Once programmed the P8749H/48H cannot be
erased.
4-18
intel~
MCS®-48
A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY
TA
=
25°C ±5°C; VCC
=
Symbol
5V ±5%; VOO
=
21 ±0.5V
Parameter
Min
tAW
Address Setup Time to RESET
4tCY
Max
Unit
ms
tWA
Address Hold Time After RESET
4tcy
tow
Data in Setup Time to PROG
4tCY
two
tpH
Data in Hold Time After PROG
4tCY
RESET Hold Time to Verify
4tCY
tvoow
Voo Hold Time Before PROG
0
1.0
tVOOH
tpw
Voo Hold Time After PROG
0
1.0
ms
Program Pulse Width
50
60
ms
tTW
TO Setup Time for Program Mode
4tCY
tWT
TO Hold Time After Program Mode
4tCY
too
TO to Data Out Delay
tww
tr , tl
RESET Pulse Width to Latch Address
tCY
tRE
Test Conditions
4tCY
Voo and PROG Rise and Fall Times
4tCY
0.5
100
p.s
CPU Operation Cycle Time
3.75
5
p.s
RESET Setup Time before EA
4tCY
NOTE:
II Test 0 is high, too can be triggered by RESET.
D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY
TA
=
25°C ±5°C; Vcc
Symbol
=
5V ±5%; Voo
=
21 ±0.5V
Parameter
Min
Max
Unit
VOOH
Voo Program Voltage High Level
20.5
21.5
V
VOOL
Voo Voltage Low Level
4.75
5.25
V
VPH
PROG Program Voltage High Level
17.5
18.5
V
VPL
PROG Voltage Low Level
4.0
VEAH
EA Program or Verify Voltage High Level
17.5
Vcc
18.5
V
100
Voo High Voltage Supply Current
20.0
mA
IpROG
lEA
. PROG High Voltage Supply Current
EA High Voltage Supply Current
4-19
V
1.0
mA
1.0
mA
Test Conditions
MCS®-48
SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE
SUBSEQUENT ROM DUMP CYCLES
I
: (INPUT)
DB---~
ADDRESS
H
ROM DATA
L--("""IN"'P"'U"'T"')-..I
H
~f---------
ADDRESS
(OUTPUT), '---(:'::IN:::P::"U=T::"'")-
(OUTPUT):
I
I
!
I
REsET _ _ _ _ _ _....
: (INPUT)
I
P2~P23---_L_ _ _ _A_D_DR_E_S_S____~~L---A-D-D-R-ES-S---~-_ _ _ _ _ __
: (INPUT)
270053-12
Al0
All
SOH
Vee
=
VDD
ADDR
ADDR
Vss
=
OV
=
+5V
NOTE:
ALE is function of Xl, X2 inputs.
COMBINATION PROGRAM/VERIFY MODE (PROGRAMMABLE ROMS ONLY)
VEAH
EA
VCC
TO
Vee
~IREt
EITW-
VIL1
r---~
IWW-
Vee
RESET
VILl
IAW-t---+~+twA
~
DBo-DB7
PROGRAM --------If---VERIFY---+I-.---PROGRAM-
---F - -
r-~D...
A~~A,...T~O~BE~~
PROGRAMMED VALID
__ -{NEXT ADDRK
VALID
NEXT
ADDRESS
LAST
ADDRESS
.:;::
...w~-~-----------__-----PAO~:--_--------:~t?H1~:----- _____________ .
270053-13
4-20
D8748H/D8749H
HMOS-E SINGLE-COMPONENT
8-BIT MICROCONTROLLER
with 8080/8085 Peripherals
• Compatible
Expandable Memory and 1/0
• Easily
Up to 1.35 }J-s Instruction Cycle;
• All Instructions 1 or 2 Cycles
Performance HMOS-E
• High
Interval Timer /Event Counter
• Two Single Level Interrupts
• Single 5-Volt Supply
• Over 96 Instructions; 90% Single Byte
•
The Intel D8749H/D8748H are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channelsilicon gate HMOS-E process.
The family contains 27 I/O lines, an 8-bit timer/counter, on-chip RAM and on-board oscillator/clock circuits.
For systems that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals:
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
Device
Internal Memory
D8749H
2Kx8 EPROM·
D8748H
1Kx 8 EPROM
I
I
128x8 RAM
64x8RAM
PORT
1
RESET
SINGLE
STEP
PORT
D87"BH
2
D87.49H
READ
WRITE
PROGRAM
STORE
ENABLE
INTERRUPT
ADDRESS
LATCH
ENABLE
BUS
PORT
EXPANDER
STROBE
210983-1
Figure 1.
Block Diagram
210983-2
Figure 2.
Logic Symbol
4-21
September 1992
Order Number: 210983-004
intel .
D8748H/D8749H
XTAL 1
P26
P2.
P2.
P17
P16
Pl'
P"
P13
P12
Pl1
PIC
V••
P"OO
P23
P22
P21
210983-3
Figure 3. Pin Configuration
Table 1. Pin Description (40·Pln DIP)
Symbol
Function
Pin No.
Vss
20
Voo
26
Circuit GND potential.
+ 5V during normal operation.
Programming power supply (+ 21 V).
Vee
PAOG
+ 5V during operation and programming.
40
Main power supply;
25
Output strobe for 8243 I/O expander.
Program pulse ( + 18V) input pin during programming.
P10-P17
Port 1
27-34
8-bit quasi-bidirectional port.
P20-P23
21-24
8-bit quasi-bidirectional port. P20-P23 contain the four high order program
counter bits during an external program memory fetch and serve as a 4-bit
I/O expander bus for 8243.
P24-P27
Port 2
35-38
DBO-DB7
BUS
12-19
True bidirectional port which can be written or read synchronously using the
AD, WA strobes. The port can also be statically latched. Contains the 8 low
order program counter bits during an external program memory fetch, and
receives the addressed instruction under the control of PSEN. Also contains
the address and data du!!!!g an ~xternal AAM data store instruction, under
control of ALE, AD, and WR.
TO
1
Input pin testable using the conditional transfer instructions JTO and JNTO.
TO can be designated as a clock output using ENTO CKL instruction.
T1
39
Input pin testable using the JT1, and JNT1 instructions. Can be deSignated
the timer/counter input using the STAT CNT instruction.
Used during programming.
INT
6
Interrupt input. Initiates an interrupt if interrupt is enabled. lriterrupt is
disabled after a reset. Also testable with conditional jump instruction. (Active
low) interrupt must remain low for at least 3 machine cycles for proper
operation.
AD
8
Output strobe activated during a BUS read. Can be used to enable data onto
the' bus from an external device.
Used as a read strobe to external data memory. (Active low)
4-22
intel .
D8748H/D8749H
Table 1. Pin Description (40-Pin DIP) (Continued)
Symbol
Pin No.
RESET
4
Input which is used to initialize the processor. (Active low) (Non TTL VIH)
WR
10
Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
ALE
11
Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and program
memory.
PSEN
9
Program store enable. This output occurs only during a fetch to external
program memory. (Active low.)
SS
5
. Single step input can be used in conjunction with ALE to "single step" the
processor through each instruction.
EA
7
External access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug. (Active high.)
XTAL1
2
One side of crystal input for internal oscillator. Also input for external source.
(Non TTL VIH.)
XTAL2
3
Other side of crystal input.
Function
Used during programming.
Used during (1BV) programming.
Table 2. Instruction Set
Mnemonic
Description
ACCUMULATOR
ADDA,R
Add register to A
ADDA,@R
Add data
memory to A
ADD A, #data
Add immediate
toA
Add register with
ADDCA,R
carry
ADDCA,@R
Add data
memory with
carry
ADDC A, #data Add immediate
with carry
ANLA, R
And register to A
ANLA,@R
And data
memory to A
ANLA, #data
And immediate
toA
ORLA,R
Or register to A
ORLA,@R
Or data memory
toA
ORLA, #data
Or immediate to
A
XRLA,R
Exclusive or
register to A
XRLA,@R
Exclusive or
data memory to
A
XRLA, #data
Exclusive or
immediate to A
Bytes
Cycles
2
2
2
2
2
2
2
2
Mnemonic
Description
ACCUMULATOR (Continued)
INCA
IncrementA
DECA
Decrement A
Clear A
CLRA
CPLA
Complement A
DAA
Decimal adjust A
Swap nibbles of
SWAP A
A
RLA
Rotate A left
Rotate A left
RLCA
through carry
RRA
Rotate A right
RRCA
Rotate A right
through carry
INPUTIOUTPUT
INA,P
OUTLP,A
ANLP, #data
ORLP, #data
INSA, BUS
OUTLBUS,A
ANL BUS, #data
ORL BUS, #data
2
MOVDA,P
2
4-23
Input port to A
Output A to port
And immediate
to port
Or immediate to
port
Input BUS to A
Output A to BUS
And immediate
to BUS
Or immediate to
BUS
Input expander
port to A
Bytes
Cycles
1
1
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
intel..
D8748H/D8749H
Table 2. Instruction Set (Continued)
Mnemonic
Description
INPUT/OUTPUT (Continued)
MOVDP,A
Output A to
expander port
ANlDP,A
And A to expander
port
ORlDP,A
Or A to expander
port
REGISTERS
INCR
INC@R
DECR
BRANCH
JMPaddr
JMPP@A
DJNZ R, addr
JC addr
JNCaddr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNI addr
JBb addr
SUBROUTINE
CALladdr
RET
RETR
FLAGS
ClRC
CPlC
ClRFO
CPlFO
ClRF1
CPLF1
DATA MOVES
MOVA,R
MOVA,@R
MOVA, #data
Bytes
Mnemonic
Description
DATA MOVES (Continued)
MOVR,A
Move A to register
MOV@R,A
Move A to data
memory
MOVR, #data
Move immediate to
register
MOV @R, #data Move immediate to
data memory
MOVA,PSW
Move PSWtoA
MOVPSW,A
MoveAto PSW
XCHA,R
Exchange A and
register
XCHA,@R
Exchange A and
data memory
XCHDA,@R
Exchange nibble
of A and register
MOVXA,@R
Move external
data memory to A
MOVX@R,A
Move A to external
data memory
MOVPA,@A
Move to A from
current page
MOVP3A,@A
Move to A from
page 3
Cycles
2
2
2
Increment register
Increment data
memory
Decrement register
Jump unconditional
Jump indirect
Decrement register
and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
Jump onTO = 1
Jump on TO = 0
Jump on T1 = 1
JumponT1 = 0
Jump on FO = 1
Jumpon F1 = 1
Jump on timer flag
Jump on INT = 0
Jumpon
accumulator bit
Jump to subroutine
Return
Return and restore
status
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
TIMER/COUNTER
MOVA,T
Read
timer/counter
MOVT,A
load
timer/counter
STRTT
Start timer
STRTCNT
Start counter
STOP TCNT
Stop timer/counter
EN TCNTI
Enable timer/
counter interrupt
DIS TCNTI
Disable timer/
counter interrupt
CONTROL
ENI
DISI
Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Move register to A
Move data memory
toA
Move immediate
toA
SELRBO
SElRB1
SElMBO
SElMB1
ENTOClK
2
2
NOP
4-24
Enable external
interrupt
Disable external
interrupt
Select register
bank 0
Select register
bank 1
Select memory
bank 0
Select memory
bank 1
Enable clock
output on TO
No operation
Bytes
Cycles
2
2
2
2
2
2
2
2
int:eL
D8748H/D8749H
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to
Storage Temperature .......... - 65·C to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 70·C
'WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 150·C
Voltage On Any Pin With Respect
to Ground ...................... - 0.5V to
+ 7V
Power Dissipation ....................... 1.0 Watt
DC CHARACTERISTICS
Symbol
TA
=
O·C to
Parameter
VIL
Input Low Voltage (All
Except RESET, X1, X2)
VIU
Input Low Voltage
(RESET, X1, X2)
VIH
+ 70·C; Vee =
Voo
Limits
Min
-0.5
Typ
Max
=
5V ± 10%; Vss
Unit
=
OV
Test Conditions
Device
0.8
V
All
-0.5
0.6
V
All
Input High Voltage
(All Except XTAL 1,
XTAL2, RESET
2.0
Vee
V
All
VIH1
Input High Voltage
(X1, X2, RESET)
3.8
Vee
V
All
VOL
Output Low Voltage (BUS)
0.45
V
IOL
All
Vou
0.45
V
IOL
=
=
2.0 rnA
Output Low Voltage
(RD, WR, PSEN, ALE)
1.8 rnA
All
VOL2
Output Low Voltage
(PROG)
0.45
V
IOL
=
1.0 rnA
All
VOL3
Output Low Voltage
(All Other Outputs)
0.45
V
IOL
=
1.6 rnA
All
VOH
Output High Voltage (BUS)
2.4
V
IOH
All
Output High Voltage
(RD, WR, PSEN, ALE)
2.4
V
IOH
=
=
-400 IJ-A
VOH1
-100 IJ-A
All
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH
=
-40 IJ-A
All
Leak~
Iu
±10
IJ-A
Vss ::;; VIN ::;; Vee
All
-500
IJ-A
Vss
+ 0.45
All
-300
IJ-A
Vss ::;; VIN ::;; 3.8V
All
±10
IJ-A
Vss ::;; VIN ::;; Vee
All
80
100
rnA
8748H
95
110
rnA
8749H
Current
(T1, INT)
IU1
Input Leakage Current
(P10-P17, P20-P27,
EA, SS)
IU2
Input Leakage Current
RESET
ILO
Leakage Current
(BUS, TO) (High
Impedance State)
100
+ Icc
Total Supply Current'
-10
::;; VIN ::;; Vee
NOTE:
'lee + 100 is measured with all outputs disconnected; ss, RESET, and INT equal to Vee; EA equal to Vss.
4-25
intel .
D8748H/D8749H
AC CHARACTERISTICS
Symbol
TA = O·C to
+ 70·C; Vcc
Parameter·
= Voo = 5V
± 10%; VSS
11 MHz
f(t)
(Note 3)
Min
Max
1000
= OV
Unit
Conditions
(Note. 1)
ns
(Note 3)
t
Clock Period
1 /xtal freq
90.9
3.5t - 170
150
ns
2t-110
70
ns
t - 40
50
ns
7.5t - 200
480
ns
6t -200
350
ns
6.5t - 200
390
ns
t - 50
40
ns
0
tLL
ALE Pulse Width
tAL
Addr Setup to ALE
tLA
Addr Hold from ALE
tCCl
Control Pulse Width (RD, WR)
tCC2
Control Pulse Width (PSEN)
tow
Data Setup before WR
. two
Data Hold after WR
tOR
Data Hold (RD, PSEN)
1.5t - 30
tROl
RD to Data In
6t - 170
4.5t - 170
110
ns
375
ns
240
ns
tR02
PSEN to Data In
tAW
Addr Setup to WR
tAOl
Addr Setup to Data (RD)
10.5t - 220
730
ns
tA02
Addr Setup to Data (PSEN)
7.5t - 200
460
ns
tAFCl
Addr Float to RD, WR
tAFC2
Addr Float to PSEN
tLAFCl
ALE to Control (RD, WR)
tLAFC2
ALE to Control (PSEN)
teAl
Control to ALE (RD, WR, PROG)
t - 65
25
ns
tCA2
Control to ALE (PSEN)
4t - 70
290
ns
tcp
Port Control Setup to PROG
1.5t - 80
50
ns
tpc
Port Control Hold to PROG
4t - 260
100
ns
tpR
PROG to P2 Input Valid
tpF
Input Data Hold from PROG
top
Output Data Setup
tpo
Output Data Hold
tpp
PROG Pulse Width
5t - 150
(Note 2)
ns
300
2t - 40
140
ns
(Note 2)
0.5t - 40
10
ns
(Note 2)
3t - 75
200
ns
1.5t - 75
60
ns
8.5t - 120
650
ns
140
ns
1.5t
0
6t - 290
250
ns
1.5t - 90
40
ns
10.5t - 250
700
ns
tpL
Port 21/0 Setup to ALE
4t - 200
160
ns
tLP
Port 2 I/O Hold to ALE
0.5t - 30
15
ns
4.5t
+ 100
510
tpv
Port Output from ALE
tOPRR
TO Rep Rate
3t
270
tCY
Cycle Time
15t
1.36
ns
15.0
NOTES:
1. Control outputs CL = 80 pF; BUS outputs CL = 150 pF.
2. BUS High Impedance Load 20 pF.
3. f(t) assumes 50% duty cycle on Xl. X2. Max clock period is for a 1 MHz crystal input.
4-26
ns
JLs
intel·
D8748H/D8749H
WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY
WRITE TO EXTERNAL DATA MEMORY
ALE
J
L
ADDRESS
210983-6
210983-4
INPUT AND OUTPUT FOR AC TESTS
READ FROM EXTERNAL DATA MEMORY
--!tLAFC1L
ALE
J'---'L..I_....;1____. . .
2.4V - - - - " " \
O.4SV _ _ _ _
tCA11RD
r----
.JX~:~:: TEST POtNTS::~:~X,--_ __
210983-7
AC testing inputs are driven at 2.4V for a Logic "I" and 0.45V for
a Logic "0". Output timing measurements are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0."
210983-5
4-27
D8748H/D8749H
PORT 1/PORT 2 TIMING
II--
tPL
--l
2ND
-Ir-C_YC_L_E.....
ALE
1
~----------~
PSEN
I
P20-23
OUTPUT
PCH
P24-27
P10-17
OUTPUT
PORT 24-27, PORT 10-17 DATA
tLP
EXPANDER
PORT
OUTPUT
1
PCH
NEW PORT DATA
I
PORT 20-23 DATAl
---l
I'PD
i
I PORT CONTROL
tDP
.
I-t
CA1
Tal
I
OUTPUT DATAl
I I
I
I
EXPANDER
PORT
INPUT
'-----------{,
--+----tLA----Ia-tI··-tPL~
PCH
I
NEW P20-23 DATA
P9RT 20-23 DATA
Fi
tPF
tPR -----<==
X
2.4V - - - - - ,
O.45V---~.
ALE
2.0" TEST POINTS .. 2.0
,0.8#
-'0 .•,
270790-6
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Output timing measurements are made at 2.0V for a
logic "1" and O.BV for a logic "0".
'WD
FLOATING
270790-5
PORT 1/PORT 2 TIMING
~STCYCLE
I
ALE
PSEN --j_ _ _-'-,
.I
P20-23
OUTPUT
L-~~
________- J
~
20-23 DATA
____Pc?RT________
~
~~
NEW P20-23 DATA
__________
I
~I
PCH
P2'·21
P'O~17
PORT 24-27. PORT 10-17 DATA
NEW PORT 9ATA
OUTPUT
.---1 I-'CA1
I.po
'LP
DP
Ir------:-----;'
OUTPUT
~
PCH
_____
_ _ _ _ _ _ __ J
I
PORT
L ______
~
I
I
OUTPUT DATA
I
1...1
r--'PR~A
I
EXPANDER
INPUT
r-' --T1
-+---'LA--~·+I··-
EXPANDER
PORT
r.----'----..
PCH
PROG
270790-7
4-41
P8049KB
CRYSTAL OSCILLATOR MODE
CERAMIC RESONATOR MODE
Cl
~
-=
(-C-2-"-::-~~r~~-_~--JE!~~-_-~1-1--':2:.t
!
C3
~
I---(- - - - T-----'1
,, -11-11 I XTAU
"
"
=-
T
_---JII..-________,,-!
1-(
Cl
XTALI
C1 = CI = 33pf :t 5""
1
~HI
Tc:::::J
XTAL2
XTALa
3
C3
270790-8
Cl = 5 pF ± Y. pF + (STRAY < 5 pFJ
C2 = (CRYSTAL + STAY) < 8 pF
C3 = 20 pF ±1 pF + (STRAY < 5 pF)
Crystal series resistance "should be less than son al8 MHz; less
than 75n at 6 MHz; less than 180n at 3.6" MHz.
3
270790-9
DRIVING FROM EXTERNAL SOURCE
'5V
47011
»-.___-=2'--1 XTALI
.SV
TTL OPEN
COLLECTOR
GATES
470fl
'------'---;3;-1 XTALI
270790-10
For XTALI and XTAL2 define "high" as voltages above 1.6V and
"low" as voltages below 1.6V. The duty cycle requirements for
externally driving XTALI and XTAL2 using the circuits shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAL2 must be high 35-65% of the period. Rise and fall times
must be faster than 20 ns.
4-42
intel~
P8049KB
VERIFYING THE 8049KB ROM
WARNING:
Programming Verification
An indication of a properly socketed part is the appearance of the ALE clock output. The lack of this
clock may be used to disable the programmer.
The following is a list of the pins used for verification
and a description of their functions:
Pin
XTAL1
XTAL2
RESET
TO
EA
BUS
P20-P22
The Verify sequence is:
1. VDD = SV, Clock applied or internal oscillator operating, RESET = OV, EA = SV, BUS floating.
2. Insert 8049KB in verify socket
Function
Clock Input (3 to 4.0 MHz)
3. EA
Initialization and Address Latching
Selection of Program or Verifying Mode
Activation Verify Modes
Address and Data Output During Verify
Address Input
=
12V (activate verify mode)
4. Address applied to BUS and P20-23
S. RESET = SV (latch address)
6. Read and verify Data on BUS
7. RESET = OV and repeat from step 4
8. Verify socket should be at conditions of step 1 for
removal from socket.
4-43
int'et
P8049KB
SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE
SUBSEQUENT ROM DUMP CYCLES
I
I
ALE
(NOTE 1)
: (OUTPUT)
-12V
I
I
: (INPUT)
EA---1
I
I
H
I
DB----I
ADDRESS
I
H
L--(-IN""P""U""T-).,.-..1
ROM DATA
(OUTPUT)
,
ADDRESS
(INPUT)
ILIROril
~I--------(OUTPUT);
I
!
RESET _ _ _ _ _ _....
,,
(INPUT)
I
P2~P23----lL_ _ _ _A_D_DR_E_S_S_ _ _~~L---A-D-D-R-E~SS----t--------I
(INPUT)
I
270790-11
Vee ~ VDD ~ +5V
50H
Al0
ADDR
All
ADDR
Vss
NOTE:
ALE is function of Xl, X2 inputs.
4-44
~
OV
MCS®-48
EXPRESS
•
O°C to 70°C Operation
•
- 40°C to
+ 85°C Operation
•
• 168 Hr. Burn-In
8048AH/8035AHL
•
8748H
•
8049AH/8039AHL
•
8243
•
8050AH/8040AHL
•
8749H
The new Intel EXPRESS family of single-component 8·bit microcomputers offers enhanced processing options
to the familiar 8048AH/8035AHL, 8748H, 8049AH/8039AHL, 8749H, 8050AH/8040AHL Intel components.
These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards, but fall short of military conditions.
The EXPRESS options include the commercial standard and - 40°C to + 85°C operation with or without 168
± 8 hours of dynamic burn-in at 125°C per MIL-STD-883, method 1015. Figure 1 summarizes the option
marking deSignators and package selections.
For a complete description of 8048AH/8035AHL, 8748H, 8049AH/8309AHL, 8749H, 8040AHL and 8050AH
features and operating characteristics, refer to the respective standard commercial grade data sheet. This
document highlights only the electrical specifications which differ from the respective commercial part.
I
I
Temp Range °C
Burn In
-40-+85
0-70
0-70
-40-+85
o Hrs
o Hrs
168 Hrs
168 Hrs
P8048AH
D8048AH
D8748H
P8035AHL
D8035AHL
P8049AH
D8049AH
D8749H
P8039AHL
D8039AHL
P8050AH
D8050AH
P8040AHL
D8040AHL
P8243
D8243
TP8048AH
TD8048AH
TD8748H
TP8035AHL
TD8035AHL
TP8049AH
TD8049AH
TD8749AH
TP8039AHL
TD8039AHL
TP8050AH
TD8050AH
TP8040AHL
TD8040AHL
TP8243
TD8243
OP8048AH
OD8048AH
OD8748H
OP8035AHL
OD8035AHL
OP8049AH
ODB049AH
OD8749H
OP8039AHL
OD8039AHL
OP8050AH
OD8050AH
OP8040AHL
OD8040AHL
OP8243
OD8243
LP8048AH
LD8048AH
LD8748H
LP8035AHL
LD8035AHL
LP8049AH
LD8049AH
LD8749AH
LP8039AHL
LD8039AHL
LP8050AH
LD8050AH
LP8040AHL
LD8040AHL
,
LD8243
* Commercial Grade
P Plastic Package
D Cerdip Package
4-45
September 1987
Order Number: 270225-002
MCS®-48 EXPRESS
Extended Temperature Electrical Specification Deviations'
TP8048AH/TP8035AHL/LP8048AH/LP8035AHL
.TD8048AH/TD8035AHL/LD8048AH/LD8035AHL
D.C. CHARACTERISTICS TA
Symbol
= -40°C to +S5°C; Vee
Parameter
Min
VIH
Input High Voltage (All Except
XTAL 1, XTAL2, RESET)
= Voo = 5V ±10%; Vss = OV
Limits
Typ
2.2
Unit
Test Conditions
Max
Vee
V
100
Voo Supply Current
4
S
rnA
100 + lee
Total Supply Current
40
SO
rnA
TP8049AH/TP8039AHL/LP8049AH/LP8039AHL
TD8049AH/TD8039AHL/LD8049AH/LD8039AHL
D.C. CHARACTERISTICS
Symbol
TA
= -40°C to +S5°C;Vee = Voo = 5V ±10%;Vss = OV
Limits
Parameter
Min
VIH
Input High Voltage (All Except
XTAL 1, XTAL2, RESET)
100
Voo Supply Current
100 + lee
Total Supply Current
Typ
2.2
,5
50
Unit
Test Conditions
Max
Vee
V
10
rnA
100
rnA
TP8050AH/TP8040AHL/LP8050AHL/LP8040AHL
TD8050AH/TD8040AHL/LD8050AH/LD8040AHL
D.C. CHARACTERISTICS TA = -40°C to +S5°C;Vee = Voo = 5V ±10%;Vss = OV
Symbol
Limits
Parameter
Min
VIH
100
100 + lee
Input High Voltage (All Except
XTAL 1, XTAL2, RESET)
Typ
2.2
. Voo Supply Current
Total Supply Current
4-46
Unit
Max
Vee
V
10
20
rnA
75
120
rnA
Test Conditions
intel~
MCS®-48 EXPRESS
Extended Temperature Electrical Specification Deviations'
TD8748H/LD8748H
D.C. CHARACTERISTICS TA = -40°C to +85°C; Vee = Voo
Symbol
= 5V ±10%; Vss
Limits
Parameter
Min
VIH
input High Voltage (All Except
XTAL1, XTAL2, RESET)
100 + lee
Total Supply Current
Unit
Typ
=
OV
Test Conditions
Max
2.2
50
Vee
V
130
mA
TD8749H/LD8749H
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = Voo = 5V ± 10%; Vss = OV
Symbol
Limits
Parameter
Min
VIH
Input High Voltage (All Except
XTAL1, XTAL2, RESET)
100 + lee
Total Supply Current
Unit
Typ
Test Conditions
Max
2.2
75
Vee
V
150
mA
TP8743/TD8243/LD8243
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = 5V ±10%;Vss = OV
Symbol
Limits
Parameter
Min
lee
..
Vee Supply Current
J
I
Typ
15
1
Unit
Max
I
'Refer to individual commercial grade data sheet for complete operating characteristics.
4-47
25
mA
Test Conditions
MCS®,,51 Architectural
Overview
5
intel.
September 1989
MCS®-51 Family of
Microcontrollers
Architectural Overview
Order Number: 270251-004
5-1
CONTENTS
MCS®-51 FAMILY OF
MICROCONTROLLERS
ARCHITECTURAL
OVERVIEW
PAGE
INTRODUCTION ......................... 5-3
CHMOS Devices ......................... 5-5
MEMORY ORGANIZATION IN MCS®·51
DEVICES .............................. 5-5
Logical Separation of Program and Data
Memory ................................ 5-5
Program Memory ......................... 5-6
Data Memory ............................. 5-7
THE MCS®·51 INSTRUCTION SET ...... 5-8
Program Status Word ..................... 5-8
Addressing Modes ....................... 5-9
Arithmetic Instructions .................... 5-9
Logical Instructions ...................... 5-11
Data Transfers .......................... 5-11
Boolean Instructions ... .' ................ 5-13
Jump Instructions ........ .".............. 5-15
CPU TIMING .. .......................... 5-16
Machine Cycles ....1 • • • • • • • • • • • • • • • • • • • • • 5_17
Interrupt Structure ....................... 5-19
ADDITIONAL REFERENCES ........... 5-21
5-2
int:eL
MCS®-S1 ARCHITECTURAL OVERVIEW
INTRODUCTION
The 8051 is the original member of the MCS®-51 family, and is the core for all MCS-51 devices. The features of the
8051 core are:
• 8-bit CPU optimized for control applications
• Extensive Boolean processing (single-bit logic) capabilities
• 64K Program Memory address space
• 64K Data Memory address space
• 4K bytes of on-chip Program Memory
•
•
o
o
128 bytes of on-chip Data RAM
32 bidirectional and individually addressable I/O lines
Two 16-bit timer/counters
Full duplex UART
• 6-source/5-vector interrupt structure with two priority levels
o On-chip clock oscillator
The basic architectural structure of this 8051 core is shown in Figure 1.
EXTERNAL
INTERRUPTS
}
TXD
PO
P2
Pl
COUNTER
INPUTS
RXD
P3
ADDRESS/DATA
270251-1
Figure 1. Block Diagram of the 8051 Core
5-3
_0·
l..
Each device on the MCS-51 family consists of all the core features plus some additional features. A feature comparison of all the MCS-51· devices is shown in
Table 1.
Table 1. The MCS®-S1 Family of Microcontrollers
Device
U1
./>.
ROMless
Version
8051
8031
8051AH
8031AH
EPROM
Version
-
i:
Programmable
Serial
Global
8-Blt
16-Blt
Interrupt
Counter
Expansion
Serial
DMA
AID
Power Down
ROM RAM
1/0
Timerl
Sourcesl
UART
Array
Port
Bytes Bytes
Channel Channels Channels
and Idle Modes
Ports Counters
Vectors
(SEP) .
(GSC)
(PCA)
4K
128
4
2
~
. 6/5
8751H
8751BH
4K
128
4
2
~
6/5
o
:::E:
=t
m
8032AH
8752BH
8K
256
4
3
~
8/6
80C51BH
80C31BH
87C51
4K
128
4
2
~
6/5
~
~
80C52
80C32
-
8K
256
4
3
~
8/6
83C51FA
80C51FA
87C51FA
8K
256
4
3
~
~
14/7
~
83C51FB
80C51FA
87C51FB
16K
256
4
3
~
~
1417
~
-
8K
256
5
2
~
~
2
19/11
~
-
256
7
2
~
~
2
19/11
~.
-
80C152JB
8K
256
5
2
~
~
2
19/11
~
-
80C152JD
-
-
256
7
2
~
~
2
19/11
~
83C452
80C452
87C452P
_.
8K
256
5
2
~
9/8
~
83C152JC 80C152JC
-"
~
:a
8052AH
83C152JA 80C152JA
~@l
•
en
~
c:
:a
~
r-
o
<
m
:a
<
iii
::e
intel .
MCS®-S1 ARCHITECTURAL OVERVIEW
PROGRAM MEMORY
(READ ONLY)
------------------.----FFFFH: .....- - - .
DATA MEMORY
(READ/WRITE)
--------------------------r----,
FFFFH:
EXTERNAL
EXTERNAL
EA=O
EA=1
EXTERNAL
INTERNAL
'TmT'
L-"""r'-~ 0000 ~L-_--I
00
I
0000 &...,........,...J
270251-2
Figure 2. MCS@-51 Memory Structure
MEMORY ORGANIZATION IN
MCS®-51 DEVICES
CHMOS Devices
Functionally, the CHMOS devices (designated with
"C" in the middle of the device name) are all fully
compatible with the 8051, but being CMOS, draw less
current than an HMOS counterpart. To further exploit
the power savings available in CMOS circuitry, two reduced power modes are added:
• Software-invoked Idle Mode, during which the CPU
is turned off while the RAM and other on-chip
peripherals continue operating. In this mode, current draw is reduced to about 15% of the current
drawn when the device is fully active.
• Software-invoked Power Down Mode, during which
all on-chip activities are suspended. The on-chip
RAM continues to hold its data. In this mode the
device typically draws less than 10 fJoA.
Logical Separation of Program and
Data Memory
All MCS-51 devices have separate address spaces for
Program and Data Memory, as shown in Figure 2. The
logical separation of Program and Data Memory allows
the Data Memory to be accessed by 8-bit addresses,
which can be more quickly stored and manipulated by
an 8-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register.
Program Memory can only be read, not written to.
There can be up to 64K bytes of Program Memory. In
the ROM and EPROM versions of these devices the
lowest 4K, 8K or 16K bytes of Program Memory are
provided on-chip. Refer tp Table I for the amount of
on-chip ROM (or EPROM) on each device. In the
ROMless versions all Program Memory is external.
'J?e read strobe for external Program Memory is the
Signal PSEN (Program Store Enable).
Although the 80C51BH is functionally compatible with
its HMOS counterpart, specific differences between the
two types of devices must be considered in the design of
an application circuit if one wishes to ensure complete
interchangeability between the HMOS and CHMOS
devices. These considerations are discussed in the Application Note AP-252, "Designing with the
80C5IBH".
For more information on the individual devices and
features listed in Table I, refer to the Hardware Descriptions and Data Sheets of the specific device.
5-5
infel .
MCS®·51 ARCHITECTURAL OVERVIEW
The lowest 4K (or 8K or 16K) bytes of Program Memory can be either in the on-chip ROM or in an external
ROM. This selection is made by strapping the EA (Ex-'
ternal Access) pin to either Vee or Vss.
Data Memory occupies a separate address space from
Program Memory. Up to 64K bytes of external RAM
can be addressed in the ext~rnal Data Memo~ace.
The CPU generates read and write signals, RD and
WR, as needed during external Data Memory accesses.
In the 4K byte ROM devices, if the EA pin is strapped
to Vee, then program fetches to addresses OOOOH
through OFFFH·are directed to the internal ROM; Program fetches to addresses lOOOH through FFFFH are
directed to external.ROM.
External Program Memory and external Data Memory
may be combined if desired by applying the RD and
PSEN signals to the inputs of an AND gate and using
the output of the gate as the read strobe to the external
ProgramlData memory. ,
In the 8K byte ROM devices, EA = Vee selects ad-'
dresses OOOOH through IFFFH to be internal, and addresses 2000H through FFFFH to be external. '
Program Memory
In the 16K byte ROM 'devices, EA = Vee selects addresses OOOOH through 3FFFH to be internal, and addresses 4000H through FFFFH to be external.
Figure 3 shows a map of the lower part of the Program
Memory. After reset, the CPU begins execution from
, location OOOOH.
As shown in Figure 3, each interrupt is assigned a fixed
location in Program Memory. The interrupt causes the
CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must
begin at location 0003H. If the interrupt is not going to
be used, its service location is available as general purpose Program Memory.
If the EA pin is strapped to Vss, then all program
fetches are directed to external ROM. The ROMless .
, parts must have this pin externally strapped to Vss to
enable them to execute properly.
The read strobe to external ROM, PSEN, is used for all
external program fetches. PSEN is not activated for internal program fetches.
MCS -51
EPROM
INSTR.
(0033H)
002BH
0023H
INTERRUPT
LOCATIONS
LATCH
P2~=====:;:t
00IBH=r
8 BYTES
270251-4
OOOBH
.......
'--_
l'~
Of
0013H
Figure 4. Executing from External
Program Memory
0003H
OOOOH
270251-3
The hardware configuration for external program exe- .
cution is shown in Figure 4. Note that 16 I/O lines
(ports 0 and 2) are dedicated to bus functions during
external Program Memory fetches. Port 0 (PO in Figure
4) serves as a multiplexed address/data bus. It emits
the low byte of the Program Counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During
the time that the low byte of the Program Counter is
valid on PO, the signal ALE (Address Latch Enable)
clocks this byte into an address latch. Meanwhile, Port
2 (P2 in Figure 4) emits the high byte of the Program
Counter (PCR). Then PSEN strobes the EPROM and
the code byte is read into the microcontroller.
Figure 3. MCS@·S1 Program Memory
The interrupt service locations are spaced at 8-byte intervals: 0003H for External Interrupt 0, OOOBH for
Timer 0, 0013H for External Interrupt 1, OOlBH for
Timer 1, etc. If an interrupt service routine is short
enough, (as is often the case in control applications), it
can reside entirely within that 8-byte interval. Longer
service routines can use a jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
5-6
intel"
MCS®·51 ARCHITECTURAL OVERVIEW
Internal Data Memory is mapped in Figure 6. The
memory space is shown divided into three blocks,
which are generally referred to as the Lower 128, the
Upper 128, and SFR space.
Program Memory addresses are always 16 bits wide,
even though the actual amount of Program Memory
used may be less than 64K bytes. External program
execution sacrifices two of the 8-bit ports, PO and P2, to
the function of addressing the Program Memory.
Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
However, the addressing modes for internal RAM can
in fact accommodate 384 bytes, using a simple trick.
Direct addresses higher than 7FH access one memory
space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Upper 128 and SFR space occupying the same block of
addresses, 80H through FFH, although they are physically separate entities.
Data Memory
The right half of Figure 2 shows the internal and external Data Memory spaces available to the MCS-51 user.
Figure 5 shows a hardware configuration for accessing
up to 2K bytes of external RAM. The CPU in this case
is executing from internal ROM. Port 0 serves as a
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are being used to page the RAM. The CPU
generates RD and WR signals as needed during external RAM accesses.
7FH
BANK
SELECT
BITS IN
PSW~
11
10
2FH
T-ADDRESSABLE SPACE
} BI
(B IT ADDRESSES 0-7F)
20H
1FH
{ 18H
17H
4 BANKS Of
B REGISTERS
RO -R7
{ 10H
01 { OBH
OFH
07H
00 ( 0
-
RESET VALUE OF
STACK POINTER
270251-7
Figure 7. The Lower 128 Bytes of Internal RAM
270251-5
The Lower 128 bytes of RAM are present in all
MCS-51 devices as mapped in Figure 7. The lowest 32
bytes are grouped into 4 banks of 8 registers. Program
instructions call out these registers as RO through R 7.
Two bits in the Program Status Word (PSW) select
which register bank is in use. This allows more efficient
use of code space, since register instructions are shorter
than instructions that use direct addressing.
Figure 5. Accessing External Data Memory.
If the Program Memory is Internal, the Other
Bits of P2 are Available as I/O.
There can be up to 64K bytes of external Data Memory. External Data Memory addresses can be either 1 or
2 bytes wide. One-byte addresses are often used in conjunction with one or more other I/O lines to. page the
RAM, as shown in Figure 5. Two-byte addresses can
also be used, in which case the high address byte is
emitted at Port 2.
FFH' _ •• - - _. : ACCESSIBLE
• BY INDIRECT
• ADDRESSING
r-----,
UPPER
128
BOH:
7FH
LOWER
128
ONLY
ACCESSIBLE
BY DIRECT
AND INDIRECT
ADDRESSING
0 ....._ _........
FFH
FFH
NO BIT-ADDRESSABLE
SPACES
ACCESSIBLE
BY DIRECT
ADDRESSING
AVAILABLE AS STACK
SPACE IN DEVICES WITH
256 BYTES RAM
BOH
\ . . SPECIAL } PORTS
fUNCTION STATUS AND
REGISTERS CONTROL BITS
TIMER
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)
NOT IMPLEMENTED IN 8051
80H
270251-8
270251-6
Figure 8. The Upper 128 Bytes of Internal RAM
Figure 6. Internal Data Memory
5-7
MCS®-51 ARCHITECTURAL OVERVIEW
I
CY
I
AC
I
FO
I RSll RSO I ov I
I
P
I
L
.J
PSW 7
CARRY FLAG RECEIVES CARRY OUT
FRO'" BIT 1 OF ALU OPERANDS
.-
PSW 0
PARITY OF ACCUMULATOR SET
BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S. OTHERWISE
IT IS RESET TO 0
' - - - PSW 1
PSW 6
AUXILIARY CARRY FLAG RECEIVES
CARRY OUT FRO'" BIT 1 OF
ADDITION OPERANDS
USER DEFINABLE FLAG
PSW 5
GENERAL PURPOSE STATUS FLAG
PSW 2
OVERFLOW FLAG SET BY
ARITHMETIC OPERATIONS
PSW 4
REGISTER BANK SELECT BIT 1
PSW 3
REGISTER BANK SELECT BIT 0
270251-10
Figure 10. PSW (Program Status Word) Register In MCS®-51 Devices
The next 16 bytes above the register banks form a block
of bit-addressable memory space. The MCS-51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this
area are DOH through 7FH.
Sixteen addresses in SFR space are both byte- and bitaddressable. The bit-addressable SFRs are those whose
address ends in DOOB. The bit addresses in this area are
80H through FFH.
THE MCS®·51 INSTRUCTION SET
All of the bytes in the Lower 128 can be accessed by
either direct or indirect addressing. The Upper 128
(Figure 8) can only be accessed by indirect addressing.
The Upper 128 bytes of RAM are not. implemented in
the 8051, but are in the devices with 256 bytes of RAM.
(See Table I).
All members of the MCS-51 family execute the same
instruction set. The MCS-51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal
RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for
one-bit variables as a separate data type, allowing direct
bit manipulation in control and logic systems that require Boolean processing.
Figure 9 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, tim-'
ers; peripheral controls, etc. These registers can only be
accessed by direct addressing. In general, all MCS-51
microcontrollers have the same SFRs as the 8051, and
at the same addresses in SFR space. However, enhancements to the 8051 have additional SFRs that are not
present in the 8051, nor perhaps in other proliferations
of the family.
FFH
EOH
0
0
REGISTER-MAPPED PORTS
ACC
0
0
BOH
An overview of the MCS-51 instruction set is presented
below, with a brief description of how certain instructions might be used. References to "the assembler" in
this discussion are to Intel's MCS-51 Macro Assembler,
ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler User's Guide (Order No. 9800937 for ISIS Systems, Order
No. 122752 for DOS Systems).
Program Status Word
ADDRESSES THAT END IN
OH OR BH ARE ALSO
BIT-ADDRESSABLE
The Program Status Word (PSW) contains several
status bits that reflect the current state of the CPU. The
PSW, shown in Figure 10, resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow
flag, a Parity bit, and two user-definable status flags.
PORT 3
0
AOH
PORT 2
90H
PORT 1
BOH
PORT 0
-PORT PINS
-ACCUMULATOR
-PSW
(ETC.)
The Carry bit, other than serving the functions of a
Carry bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.
0
270251-9
Figure 9. SFR Space
5-B
MCS®-S1 ARCHITECTURAL OVERVIEW
The bits RSO and RS I are used to select one of the four
register banks shown in Figure 7. A number of instructions refer to these RAM locations as RO through R7.
The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS 1
at execution time.
IMMEDIATE CONSTANTS
The value of a constant can follow the opcode in Program Memory. For example,
MOV A, #100
The Parity bit reflects the number of Is in the Accumulator: P = 1 if the Accumulator contains an odd number of Is, and P = 0 if the Accumulator contains an
even number of Is. Thus the number of Is in the Accumulator plus P is always even.
loads the Accumulator with the decimal number 100.
The same number could be specified in hex digits as
64H.
Two bits in the PSW are uncommitted and may be used
as general purpose status flags.
Only Program Memory can be accessed with indexed
addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program
Memory. A 16-bit base register (either DPTR or the
Program Counter) points to the base of the table, and
the Accumulator is set up with the table entry number.
The address of the table entry in Program Memory is
formed by adding the Accumulator data to the base
pointer.
INDEXED ADDRESSING
Addressing Modes
The addressing modes in the MCS-Sl instruction set
are as follows:
DIRECT ADDRESSING
Another type of indexed addressing is used in the "case
jump" instruction. In this case the destination address
of a jump instruction is computed as the sum of the
base pointer and the Accumulator data.
In direct addressing the operand is specified by an 8-bit
address field in the instruction. Only internal Data
RAM and SFRs can be directly addressed.
INDIRECT ADDRESSING
Arithmetic Instructions
In indirect addressing the instruction specifies a register
which contains the address of the operand. Both internal and external RAM can be indirectly addressed.
The menu of arithmetic instructions is listed in Table 2.
The table indicates the addressing modes that can be
used with each instruction to access the operand. For example, the ADD A, instruction can
be written as:
The address register for 8-bit addresses can be RO or
R I of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the
16-bit "data pointer" register, DPTR.
ADD
ADD
ADD
ADD
REGISTER INSTRUCTIONS
The register banks, containing registers RO through R 7,
can be accessed by certain instructions which carry a
3-bit register specification within the opcode of the instruction. Instructions that access the registers this way
are code efficient, since this mode eliminates an address
byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four
banks is selected at execution time by the two bank
select bits in the PSW.
A,7FH
A,@RO
A,R7
A,#I27
(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)
The execution times listed in Table 2 assume a 12 MHz
clock frequency. All of the arithmetic instructions execute in I fJ-s except the INC DPTR instruction, which
takes 2 fJ-s, and the Multiply and Divide instructions,
which take 4 fJ-s.
Note that any byte in the internal Data Memory space
can be incremented or decremented without going
through the Accumulator.
One of the INC instructions operates on the 16-bit
Data Pointer. The Data Pointer is used to generate
16-bit addresses for external memory, so being able to
increment it in one 16-bit operation is a useful feature.
REGISTER-SPECIFIC .INSTRUCTIONS
Some instructions are specific to a certain register. For
example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that. Instructions that refer to the Accumlator as A assemble
as accumulator-specific opcodes.
The MUL AB instruction multiplies the Accumulator
by the data in the B register and puts the 16-bit product
into the concatenated B and Accumulator registers.
5-9
int'et
MCS®-51 ARCHITECTURAL OVERVIEW
Table 2. A List of the MCS®-S1 Arithmetic Instructions
Mnemonic
ADD
A,
Addressing Modes
Operation
Dir
Ind
Reg
Imm
Execution
Time (~s)
A = A +
X
X
X
X
1
ADDC A, < byte>
A = A + + C
X
X
X
X
1
SUBB A,
A = A - - C
X
X
X
X
1
INC
A
A=A+1
INC
= + 1
INC
DPTR
DPTR = DPTR + 1
Data Pointer only
2
DEC
A
A=A-1
Accumulator only
1
Accumulator only
X
X
1
X
1
DEC
= - 1
MUL
AB
B:A = BxA
ACC and B only
4
DIV
AB
A = Int [AlB]
B = Mod [AlB]
ACC and B only
4
DA
A
Decimal Adjust
Accumulator only
1
X
X
X
1
completes the shift in 4 ~s and leaves the B register
holding the bits that were shifted out.
The DIV AB instruction divides the Accumulator by
the data in the B register and leaves the 8-bit quotient
in the Accumulator, and the 8-bit remainder in the B
register.
The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be followed by a DA A operation,
to ensure that the result is also in BCD. Note that DA
A will not convert a binary number to BCD. The DA
A operation produces a meaningful result only as the
second step in the addition of two BCD bytes.
Oddly enough, DIV AB finds less use in arithmetic
"divide" routines than in radix conversions and programmable shift operations. An example of the use of
DIV AB in a radix conversion will be given later. In
shift operations, dividing a number by 2n shifts its n
bits to the right. Using DIV AB to perform tht: division
Table 3. A List of the MCS®-S1 Logical Instructions
Mnemonic
Addressing Modes
Operation
Execution
Dir
Ind
Reg
Imm
X
X
X
X
Time(~s)
ANL
A,
A = A .AND.
ANL
,A
= .AND.A
X
1
ANL
= .AND. #data
A = A .OR.
X
2
OAL
,#data
A,
OAL
,A
= .OR.A
X
1
OAL
,#data
= .OR. #data
X
2
XAL
A,
,A
A = A .XOR.
= .XOR.A
X
XAL
X
1
XAL
,#data
X
2
CAL
A
= .XOR. #data
A = OOH
CPL
A
RL
A
RLC
X
X
X
X
X
X
X
1
1
1
Accumulator only
1
A = .NOT.A
Accumulator only
1
Rotate ACC Left 1 bit
Accumulator only
1
A
Rotate Left through Carry
Accumulator only
1
RA
A
Rotate ACC Aight 1 bit
Accumulator only
1
RAC
A
Rotate Right through Carry
Accumulator only
1
Swap Nibbles in A
Accumulator only
1
SWAP A
5-10
intel"
MCS®-51 ARCHITECTURAL OVERVIEW
Logical Instructions
Table 3 shows the list of MCS-51 logical instructions.
The instructions that perform Boolean operations
(AND, OR, Exclusiv~ OR, NOT) on bytes perform the
operation on a bit-by-bit basis. That is, if the Accumu- .
lator contains OOl10101B and contains
0101001lB, then
ANL
The SWAP A instruction interchanges the high and
low nibbles within the Accumulator. This is a useful
operation in BCD manipulations. For example, if the
Accumulator contains a binary number which is known
to be less than 100, it can be quickly converted to BCD
by the following code:
MOY
DIY
SWAP
ADD
A,
B,#1O
AB
A
A,B
wi11leave the Accumulator holding 000 1000 lB.
Dividing the number by 10 leaves the tens digit in the
low nibble of the Accumulator, and the ones digit in the
B register. The SWAP and ADD instructions move the
tens digit to the high nibble of the Accumulator, and
the ones digit to the low nibble.
The addressing modes that can be used to access the
operand are listed in Table 3. Thus, the ANL
A, < byte> instruction may take any of the forms
ANL
ANL
ANL
ANL
A,7FH
A,@Rl
A,R6
A;#53H
(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)
Data Transfers
INTERNAL RAM
All of the logical instructions that are Accumulatorspecific execute in l,...s (using a 12 MHz clock). The
others take 2 ,...s.
Table 4 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used
with each one. With a 12 MHz clock, all of these instructions execute in either 1 or 2 ,...s.
Note that Boolean operations can be performed on any
byte in the lower 128 internal Data Memory space or
the SFR space using direct addressing, without having
to use the Accumulator. The XRL , #data instruction, for example, offers a quick and easy way to
invert port bits, as in
XRL
The MOY , instruction allows data to
be transferred between any two internal RAM or SFR
locations without going through the Accumulator. Remember the Upper 128 byes of data RAM can be accessed only by indirect addressing, and SFR space only
by direct addressing.
.
Pl,#OFFH
If the operation is in response to an interrupt, not using
the Accumulator saves the time and effort to stack it in
the service routine.
Note that in all MCS-51 devices, the stack resides in
on-chip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies
the byte into the stack. PUSH and POP use only direct
addressing to identify the byte being saved or restored,
The Rotate instructions (RL A, RLC A, etc.) shift the
Accumulator 1 bit to the left or right. For a left rotation, the MSB rolls into the LSB position; For a right
rotation, the LSB rolls into the MSB position.
Table 4. A List of the MCS®-S1 Data Transfer Instructions that Access Internal D.ata Memory Space
Dir
Ind
Reg
Imm
Execution
Time (,...s)
MOV
A,
A=
X
X
X
X
1
MOV
,A
= A
X
X
X
MOV
,
=
X
X
X
X
2
.MOV
DPTR,#data16
X
2
Mnemonic
Addressing Modes
Operation
DPTR = 16-bit immediate constant.
PUSH
INC SP: MOV "@SP",
X
POP
MOV , "@SP" : DEC SP
X
XCH
A,
ACC and exchange data
X
XCHD A,@Ri
ACC and @Ri exchange low nibbles
5-11
1
2
2
X
X
X
1
1
MeS@~51
ARCHITECTURAL OVERVIEW
but the stack itself is accessed by indirect addressing
using the SP register. This means the stack Can go into
the Upper 128, if they· are implemented, but not into
SFR space.
In devices that do not implement the Upper 128, if the
SP points to the Upper 128, PUSHed bytes are lost, and
POPped bytes are indeterminate.
The Data Transfer instructions include a 16-bit MOV
that can be used to initialize the Data Pointer (DPTR)
for look-up tables in Program Memory, or for 16-bit
external Data Memory accesses.
After the routine has been executed, the Accumulator
contains the two digits that were shifted out on the
right. Doing the routine with direct MOVs uses 14 code
bytes and 9 J.l.s of execution time (assuming a 12 MHz
. clock). The same operation with XCHs uses less code
and executes almost twice as fast.
To right-shift by an odd number of digits, a one~digit
shift must be executed. Figure 12 shows a sample of
code that will right~shift a BCD number one digit, using the XCHD instruction. Again, the contents of the
registers holding the number and of the Accumulator
are shown alongside each instruction.
The XCH A, instruction causes the Accumulator and addressed byte to exchange data. The XCHD
A,@Ri instruction is similar, but only the low nibbles
are involved in the exchange.
MOV R1,#2EH
MOV RO,#2DH
loop for R1 = 2EH:
LOOP: MOV A,@R1
XCHD A,@RO
SWAP A
MOV @R1,A
DEC R1
DEC RO
CJNE R1,#2AH,LOOP
To see how XCH and XCHD can be used to facilitate
data manipulations, consider first. the problem of shifting an 8-digit BCD number two digits to the right. Figure II shows how this can be done using direct MOVs,
and for comparison how it can be done using XCH
instructions. To aid in understanding how the code
works, the contents of the registers that are holding the
BCD number and the content of the Accumulator are
shown alongside each instruction to indicate their
status after the instruction has been executed.
2A 2B 2C
00 12 34
MOV A,2EH
MOV 2EH,2DH 00 12 34
MOV 2DH,2CH 00 12 34
MOV 2CH,2BH 00 12 12
MOV 2BH,#0
00 00 12
(a) Using direct MOVs: 14 bytes, 9 ,...S
CLR
A
XCH A,2BH
XCH A,2CH
XCH A,2DH
XCH A,2EH
(b) Using XCHs:
2A 2B
00
12
00
00
00
00
00
00
00
00
9 bytes, 5 ,...S
2C
34
34
12
12
12
20
56
56
34
34
34
20
56
56
56
34
34
2E
78
56
56
56
56
ACC
78
78
78
78
78
2E
78
78
78
78
56
ACC
00
12
34
56
78
:~~~:~~ =~ : ~g~~
2BH: .
loop for R1
CLR
XCH
=
A
A,2AH
00
00
00
00
00
00
12
12
12
12
12
12
34
34
34
34
34
34
56
58
58
58
58
58
78
78
78
67
67
67
78
76
67
67
67
67
IggI~~ I~~ I:~ I~~I ~~
08 0123 45 67 01
I0800 10101 1231451671
00
23 45 67 08
Figure 12. Shifting a BCD Number
One Digit to the Right
First, pointers RI and RO are set up to point to the two
bytes containing the last four BCD digits. Then a loop
is executed which leaves the last byte, location 2EH,
holding the last two digits of the shifted number. The
pointers are decremented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and
Jump if Not Equal) is a loop control that will be described later.
The loop is executed from LOOP to CJNE for RI =
2EH, 2DH, 2CH and 2BH. At that point the digit that
was originally shifted out on the right has propagated
to location 2AH. Since that location should be left with
Os, the lost digit is moved to the Accumulator.
Figure 11. Shifting a BCD Number
Two Digits to the Right
5-12
int:eL
MCS®·51 ARCHITECTURAL OVERVIEW
Table 6. The MCS@·51 Lookup
Table Read Instructions
EXTERNAL RAM
Table 5 shows a list of the Data Transfer instructions
that access external Data Memory. Only indirect addressing can be used. The choice is whether to use a
one-byte address, @Ri, where Ri can be either RO or
R I of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using 16-bit addresses if
only a few K bytes of external RAM are involved is
that 16-bit addresses use all 8 bits of Port 2 as address
bus. On the other hand, 8-bit addresses allow one to
address a few K bytes of RAM, as shown in Figure 5,
without having to sacrifice all of Port 2.
All of these instructions execute in 2 /Ls, with a
12 MHz clock.
Table 5. A List ofthe MCS®·51 Data
Transfer Instructions that Access
External Data Memory Space
Address
Width
Operation
Execution
Time (I-'s)
MOVXA,@Ri
Read external
RAM@Ri
2
MOVX@Ri,A
Write external
RAM@Ri
2
16 bits
MOVX A,@DPTR
Read external
RAM@DPTR
2
16 bits
MOVX @DPTR,A
Write external
RAM@DPTR
2
B bits
B bits
Mnemonic
Mnemonic
Operation
Execution
Time (I-'s)
MOVC
A,@A+DPTR
Read pgm Memory
at (A+DPTR)
2
MOVC
A,@A+PC
Read pgm Memory
at (A+PC)
2
The first MOVC instruction in Table 6 can accommodate a table of up to 256 entries, numbered 0 through
255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is set up to point to
beginning of the table. Then
MOVC
A,@A+DPTR
copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table
base, and the table is accessed through a subroutine.
First the number of the desired entry is loaded into the
Accumulator, and the subroutine is called:
MOV
CALL
A,ENTRY_NUMBER
TABLE
The subroutine "TABLE" would look like this:
TABLE:
Note that in all external Data RAM accesses, the Ac.cumulator is always either the destination or source of
the data.
MOVC
RET
A,@A+PC
The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered I through 255. Number 0 can not be used, because at the time the MOVC
instruction is executed, the PC contains the address of
the RET instruction. An entry numbered 0 would be
the RET opcode itself.
The read and write strobes to external RAM are activated only during the execution of a MOVX instruction. Normally these signals are inactive, and in fact if
they're not going to be used at all, their pins are available as extra I/O lines. More about that later.
LOOKUP TABLES
Boolean Instructions
Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since
these instructions access only Program Memory, the
.lookup tables can only be read, not updated. The mnemonic is MOVC for "move constant".
MCS-51 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other
addressable bits. All of the port lines are bit-addressable, and each one can be treated as a separate singlebit port. The instructions that access these bits are not
just conditional branches, but a complete menu of
move, set, clear, complement, OR, and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byteoriented software.
If the table access is to external Program Memory, then
the read strobe is PSEN.
5-13
intel .
MCS@-51 ARCHITECTURAL OVERVIEW
Table 7. A List of the MCS®-51
Boolean Instructions
Operation
Mnemonic
ANL
C,bit
ANL
ORL
C = C .AND. bit
C,Ibit C = C .AND .. NOT. bit
C,bit C = C.OR.bit
ORL
MOV
MOV
C,Ibit C = C .OR. .NOT. bit
C,bit C = bit
bit,C bit = C
CLR
C
Execution
Time (tJ-s)
2
2
bit = 0
C=1
1
1
SETB bit
CPL
C
CPL
bit
bit = 1
C = .NOT.C
1
JB
JNB
JBC
rei
JumpifC = 1
JumpifC = 0
1
1
2
Jump if bit = 1
2
2
bit,rel
Jump if bit = 0
2
bit,rel
Jump if bit = 1; CLR bit
2
The instruction set for the Boolean processor is shown
in Table 7. All bit accesses are by direct addressing. Bit
addresses OOH through 7FH are in the Lower 128, and
bit addresses 80H through FFH are in SFR space.
Note how easily an internal flag can be moved to a port
pin:
MOV
MOV
MOV
C,bitl
bit2,OVER
JNB
CPL
C
OVER: (continue)
2
CLR bit
SETB C
rei
bit, rei
The software to do that could be as follows:
2
1
1
JC
JNC
C = bitl .XRL. bit2
2
C=O
bit = .NOT. bit
Note that the Boolean instruction set includes ANL
and ORL operations, but not the XRL (Exclusive OR)
operation. An XRL operation is simple to implement in
software. Suppose, for example, it· is required to form
the Exclusive OR of two bits:
C,FLAG
PI.O,C
In this example, FLAO is the name of any addressable
bit in the Lower 128 or SFR space. An 1/0 line (the
LSB of Port I, in this case) is set or cleared depending
on whether the flag bit is I or O.
The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carry-specific
instructions (CLR C, etc). The Carry bit also has a
direct address, since it resides in the PSW register,
which is bit-addressable.
First, bitl is moved to the Carry. If bit2 = 0, then C
now contains the correct result. That is, bit! .XRL. bit2
= bit!·if bit2 = O. On the other hand, if bit2 = I C
now contains the complement· of the correct result. It
need only be inverted (CPL C) to complete the operation.
This code uses the JNB instruction, one of a series of
bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is
not set (JNC, JNB). In the above case, bit2 is being
tested, and if bit2 = 0 the CPL C instruction is jumped
over.
JBC executes the jump if the addressed bit is set, and
also clears the bit. Thus a flag can be tested and cleared
in one operation.
All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
available to the bit-test instructions.
RELATIVE OFFSET
The destination address for these jumps is specified to
the assembler by a label or by an actual address in
Program Memory. However, the destination address
assembles to a relative offset byte. This is a signed
(two's complement) offset byte which is added to the
PC in two's complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to + 127 Program Memory bytes relative to the first byte following
the instruction.
5-14
intel..
MCS®-51 ARCHITECTURAL OVERVIEW
the Accumulator. Typically, DPTR is set up with the
address of a jump table, and the Accumulator is given
an index to the table. In a 5-way branch, for example,
an integer 0 through 4 is loaded into the Accumulator.
The code to be executed might be as follows:
Jump Instructions
Table 8 shows the list of unconditional jumps.
Table 8. Unconditional Jumps
in MCS®-51 Devices
Mnemonic
JMP
addr
JMP @A+OPTR
CALL addr
Operation
MOV
MOV
RL
JMP
Execution
Time (".s)
Jump to addr
Jump to A+ OPTR
2
2
RET
Call subroutine at addr
Return from subroutine
RETI
Return from interrupt
2
NOP
No operation
1
DPTR,#JUMP_TABLE
A,INDE~NUMBER
A
@A+DPTR
2
The RL A instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
because each entry in the jump table is 2 bytes long:
2
JUMP_TABLE:
AJMP
AJMP
AJMP
AJMP
AJMP
The Table lists a single "JMP addr" instruction, but in
fact there are three-SJMP, UMP and AJMP-which
differ in the format of the destination address. JMP is a
generic mnemonic which can be used if the programmer does not care which way the jump is encoded.
CASE_O
CASE_l
CASE_2
CASE_3
CASE_4
Table 8 shows a single "CALL addr" instruction, but
there are two of them-LCALL and ACALL-which
differ in the format in which the subroutine address is
given to the CPU. CALL is a generic mnemonic which
can be used if the programmer does not care which way
the address is encoded.
The SJMP instruction encodes the destination address
as a relative offset, as described above. The instruction
is 2 bytes long, consisting of the opcode and the relative
offset byte. The jump distance is limited to a range of
-128 to + 127 bytes relative to the instruction following the SJMP.
The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Program Memory space. The ACALL instruction uses the
ll-bit format, and the subroutine must be in the same
2K block as the instruction following the ACALL.
The UMP instruction encodes the destination address
as a 16-bit constant. The instruction is 3 bytes long,
consisting of the opcode and two address bytes. The
destination address can be anywhere in the 64K Program Memory space.
In any case the programmer specifies the subroutine
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the address
into the correct format for the given instructions.
The AJMP instruction encodes the destination address
as an ll-bit constant. The instruction is 2 bytes long,
consisting of the opcode, which itself contains 3 of the
11 address bits, followed by another byte containing the
low 8 bits of the destination address. When the instruction is executed, these 11 bits are simply substituted for
the low 11 bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K
block as the instruction following the AJMP.
Subroutines should end with a RET instruction, which
returns execution to the instruction following the
CALL.
RETI is used to return from an interrupt service routine. The only difference between RET and RET! is
that RET! tells the interrupt control system that the
interrupt in progress is done. If there is no interrupt in
progress at the time RET! is executed, then the RETI
is functionally identical to RET.
In all cases the programmer specifies the destination
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instruction will
not support the distance to the specified destination address, a "Destination out of range" message is written
into the List file.
Tabie 9 shows the list of conditional jumps available to
the MCS-51 user. All of these jumps specify the destination address by the relative offset method, and so are
limited to a jump distance of -128 to + 127 bytes from
the instruction following the conditional jump instruction. Important to note, however, the user specifies to
the assembler the actual destination address the same
way as the other jumps: as a label or a 16-bit constant.
The JMP @A + DPTR instruction supports case
jumps. The destination address is computed at execution time as the sum of the 16-bit DPTR register and
5·15
intel .
MCS@-51 ARCHITECTURAL OVERVIEW
Table 9. Conditional Jumps In MCS~-51 Devices
Addressing Modes
Mnemonic
Operation
Reg
Dlr
Ind
Imm
Jump if A = 0
JZ
rei
Accumulator only
Jump if A =F 0
Accumulator only
JNZ rei
DJNZ ,rei
Decrement and jump if not zero
X
X
X
X
CJNE A, ,rei
Jump if A =F < byte>
CJNE ,#data,rel
Jump if =F #data
X
X
There is no Zero bit in the PSW. The JZ and JNZ
instructions test the Accumulator data for that condi·
tion.
2
2
2
2
2·
~
IICS -51
HIIOS
OR CHMOS
r-..---IXTAL2
The DJNZ instruction (DeCrement and Jump if Not
Zero) is for loop control. To execute a loop N times,
load a counter byte with N and terminate the loop with
a DJNZ to the beginning of the loop, as shown below
for N = 10:
LOOP:
Execution
Time (I's) ,
QUAR~ g~mAi'=
RESONATOR
-= '--__
VSS
..I
270251-11
MOV
COUNTER,# 10
(begin loop)
Figure 13. Using the OnoChlp Oscillator
•
.
'
~
(end loop)
DJNZ
COUNTER,LOOP
(continue)
NCS -51
HIIOS
OR CHMOS
XTAL2
The CJNE instruction (Compare and Jump if Not
Equal) can aIso be used for loop control as in Figure 12.
Two bytes are specified In the operand field of the instruction. The jump is executed only if the two bytes
are not equal. In the example of Figure 12, the two
bytes were the data in RI and the constant 2AH. The
initial data in RI was 2EH. Every time the loop was
executed, RI was decremented, and the looping was to
continue until the RI data reached 2AH.
EXTERNAL
CLOCK
SIGNAL
XTALI
VSS
270251-12
A. HMOS or CHMOS
~
MCS -51
HMOS
ONLY
EXTERNAL
CLOCK
SIGNAL
Another application of this instruction is in "greater
than, less than" comparisons. The two bytes in the operand field are taken as unsigned integers. If the first is
less than the second, then the Carry bit is set (I). If the
first is greater than or equal to the second, then the
Carry bit is cleared.
XTAL2
XTALI
VSS
270251-13
B.HMOSOnly
CPU TIMING
~
IICS -51
CHIIOS
ONLY
All MCS-51 microcontrollers have an on-chip oscillator
which can be used if desired as the clock source for the
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALI and XTAL2
pins of the microcontroller, and capacitors to ground as
shown in Figure 13.
(NC)
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
vss
270251-14
C. CHMOS Only
Figure 14. Using an External Clock
5-16
int:eL
MCS®-S1 ARCHITECTURAL OVERVIEW
Examples of how to drive the clock with an external
oscillator are shown in Figure 14. Note that in the
HMOS devices (8051, etc.) the signal at the XTAL2 pin
actually drives the internal clock generator. In the
CHMOS devices (80C51BH, etc.) the signal at the
XT AL 1 pin drives the internal clock generator. If only
one pin is going to be driven with the external oscillator
signal, make sure it is the right pin.
Machine Cycles
A machine cycle consists of a sequence of 6 states,
numbered S 1 through S6. Each state time lasts for two
oscillator periods. Thus a machine cycle takes 12 oscillator periods or 1 fJ-s if the oscillator frequency is
12 MHz.
Each state is divided into a Phase 1 half and a Phase 2
half. Figure 15 shows the fetch/execute sequences in
The internal clock generator defines the sequence of
states that make up the MCS-51 machine cycle.
OSC.
(XTAL2)
ALE
_[
::~D NEXT OPCODE AGAIN.
- - - - - - ....--J-.,.--r--,-..l-,---r-:-:_1
______
'--_.L-_...L-_--'-_~_~_~:__
(A) l-byle, l-cyelelnslruellon, e.g., INC A.
I
I
READ OPCODE.
I
:
_
[_R:~ NEXT OPCODE.
--------~~-_r-_rJ-,_-._:_:_1
________
~---l._--l-_-'-_...L-_~--:
(B) 2-byle, l-eyel. Inslruellon, e.g., ADD A, #dala
READ OPCODE.
READ NEXT
OPCODE (DISCARD).
(C) l-byle, 2-cyele in.luellon, •. g., INC DPTR.
I
READ NEXT OPCODE AGAIN.
READOPCODE
(MOVX).
'NO
NO FETCH.
1
J
I
I ____ _
DATA
(D) MOVX (l-byle, 2-cyele)
I
ACCESS EXTERNAL MEMORY
270251-15
Figure 15. State Sequences in MCS®-51 Devices
5-17
intel..
MCS®-51 ARCHITECTURAL OVERVIEW
states and phases for various kinds of instructions. Normally two program fetches are generated during each
machine cycle, even if the instruction being executed
doesn't require it. If the instruction being executed
doesn't need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incremented.
The fetch/execute sequences are the same whether the
Program Memory is internal or external to the chip.
Execution times do not depend on whether the Program Memory is internal or external.
Figure 16 shows the signals and timing involved in program fetches when the Program Memory is external. If
Program Memory is external, then the Program Memory read strobe PSEN is normally activated twice per
machine cycle, as shown in Figure 16(A).
Execution of a one-cycle instruction (Figure 15A and
B) begins during State I of the machine cycle, when the
opcode is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle.
Execution is complete at the end of State 6 of this machine cycle.
If an access to external Data Memory occurs, as shown
in Figure 16(B), two PSENs are skipped, because the
address and data bus are being used for the Data Memoryaccess.
The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the second cycle of a MOVX instruction. This is the only time
program fetches are skipped. The fetch/execute sequence for MOVX instructions is shown in Figure
15(D).
Note that a Data Memory bus cycle takes twice as
much time as a Program Memory bus cycle. Figure 16
shows the relative timing of the addresses being emitted
at Ports 0 and 2, and of ALE and PSEN. ALE is used
to latch the low address byte from PO into the address
latch.
l O N E MACHINE CYCLE--r--0NE MACHINE CYCLEi
I~I~I~I~I~I~I~I~I~I~I~I~I
ALE
PsEN
AD
------~----------~----------_+----------_7----------~----
PO
,
,,
I,
I
t.PCLOUT
VALID
tPCLOUT
VALID
tPCLOUT
VALID
t.PCLOUT
VALID
(A)
WITHOUT A
MOVX.
I
ALE
PsEN
AD
(8)
------~----------~----~
WITH A
MOVX.
lpCLOUT
VALID
270251-16
Figure 16. Bus Cycles in MCS®-S1 Devices Executing from External Program Memory
5-18
in1:et
MCS®-51 ARCHITECTURAL OVERVIEW
When the CPU is executing from internal Program
Memory, PSEN is not activated, and program addresses are not emitted. However, ALE continues to be activated twice per machine cycle and so is available as a
clock output signal. Note, however, that one ALE is
skipped during the execution of the MOVX instruction.
named IE (Interrupt Enable). This register also contains a global disable bit, which can be cleared to disable all interrupts at once. Figure 17 shows the IE register for the 8051.
INTERRUPT PRIORITIES
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in the SFR named IP (Interrupt Priority).
Figure 18 shows the IP register in the 8051.
Interrupt Structure
The 8051 core provides 5 interrupt sources: 2 external
interrupts, 2 timer interrupts, and the serial port interrupt. What follows is an overview of the interrupt
structure for the 8051. Other MCS-51 devices have additional interrupt sources and vectors as shown in Table 1. Refer to the appropriate chapters on other devices for further information on their interrupts.
A low-priority interrrupt can be interrupted by a highpriority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by
any other interrupt source.
If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority
level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is servi<;ed. Thus
within each priority level there is a second priority
structure determined by the polling sequence.
INTERRUPT ENABLES
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR
(MSB)
(LSB)
IEA I-I -I ES I En I EXl I ETa I EXO I
Figure 19 shows, for the 8051, how the IE and IP registers and the polling sequence work to determine which
if any interrupt will be serviced.
Enable bit = 1 enables \he interrupt.
Enable bit = a disables it.
Symbol
Position
EA
IE.7
Function
disables all interrupts. If EA = 0, no
.interrupt wiJl be acknowledged. If EA
=
1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
IE.6
reserved'
reserved·
IE.5
ES
IE.4
Serial Port Interrupt enable bit.
ETl
IE.3
Timer 1 Overflow Interrupt enable bit.
EXl
External Interrupt 1 enable bit.
IE.2
ETa
Timer a Overflow Interrupt enable bit.
IE.l
EXO
IE.O
External Interrupt a enable bit.
'These reserved bits are used in other MCS-51 devices.
(MSB)
(LSB)
I-I - I -I PS I PTl I PXl I PTa I pxo I
PriOrity bit = 1 assigns high priOrity.
Priority bit = a assigns low priority.
Symbol
Position
IP.7
IP.6
IP.5
PS
IP.4
PTl
IP.3
PXl
IP.2
PTa
.IP.l
PXO
IP.O
'These reserved bits are
Figure 17.IE (Interrupt Enable)
Register in the 8051
Function
reserved'
reserved·
reserved·
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External Interrupt 1 priority bit.
Timer a interrupt priority bit.
External Interrupt a priority bit.
used in other MCS-51 devices.
Figure 18.IP (Interrupt Priority)
Register in the 8051
5-19
infel~
MCS®-51 ARCHITECTURAL OVERVIEW
HIGH PRIORITY
INTERRUPT
IP REGISTER
~o-f.--t-o-........
o-~----t-~
I
I
I
I
T F O - - - - - -.....-<>'
O-of>t-I-o-~_I_-__I-+I
INTERRUPT
POLLING
SEQUENCE
I
I
I
~
I~--~~~--~~
TF1--------------+........0'
,
I
I
I
!--
o--o'j
(:H----~O_"_
o-~----~~
I
I
I
I
RI
TI
")---.........,*"'"-C5-~-=+I
I
INDIVIDUAL
ENABLES
LOW PRIORITY
INTERRUPT
GLOBAL
DISABLE
270251-17
Figure 19.8051 Interrupt Control System
In operation, all the interrupt flags are latched into the
interrupt control system during State 5 of every machine cycle. The samples are polled during the following machine cycle. If the flag for an enabled interrupt is
found to be set (1), the interrupt system generates an
LCALL to the appropriate location in Program Memory, unless some other condition blocks the interrupt.
Several conditions can block an interrupt, among them
that an interrupt of equal or higher priority level is
already in progress.
pleted in less time than it takes other architectures to
commence them.
.
SIMULATING A THIRD PRIORITY LEVEL IN
SOFTWARE
Some applications require more than the two priority
levels that are provided by on-chip hardware in
MCS-51 devices. In these cases, relatively simple software can be written to produce the same effect as a
third priority level.
The hardware-generated LCALL causes the contents of
the Program Counter to be pushed onto the stack, and
reloads the PC with the beginning address of the service
routine. As previously noted (Figure 3), the service routine for each interrupt begins at a fixed location.
First interrupts that are to have higher priority than 1
are ~ssigned to priority I in the IP (Interrupt Priority)
register. The service routines for priority 1 interrupts
that are supposed to be interruptible by "priority· 2"
interrupts are written to include the following code:
Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Having only the PC be automatically saved allows the p:ogrammer to decide how much time to spend savmg
which other registers. This· enhances the interrupt response time, albeit at the expense of increasing the programmer's burden of responsibility. As a result, many
interrupt functions that are typical in control applications-toggling a port pin, for example, or reloading a
timer, or unloading a serial buffer-can often be com-
PUSH
MOV
CALL
IE
IE,#MASK
LABEL
*******
(execute service routine)
*******
POP
IE
RET
LABEL: RETI
5-20
intel .
MCS®-51 ARCHITECTURAL OVERVIEW
As soon as any priority 1 interrupt is acknowledged,
the IE (Interrupt Enable) register is re-defined so as to
disable all but "priority 2" interrupts. Then, a CALL to
LABEL executes the RETI instruction, which clears
the priority 1 interrupt-in-progress flip-flop. At this
point any priority 1 interrupt that is enabled can be
serviced, but only "priority 2" interrupts are enabled.
ADDITIONAL REFERENCES
The following application notes are found in the Embedded Control Applications handbook. (Order Number: 270648)
1. AP-69 "An Introduction to the Intel MCS®-SI Single-Chip Microcomputer Family"
2. AP-70 "Using the Intel MCS®-SI Boolean Processing Capabilities"
POPping IE restores the original enable byte. Then a
normal RET (rather than another RET!) is used to
terminate the service routine. The additional software
adds 10 ,""S (at 12 MHz) to priority 1 interrupts.
5-21
MCS® . . 51 Programmer's Guide
and Instruction Set
6
int'el.
July 1989
MCS®-51 Programmer's Guide
and Instruction Set
Order Number: 270249-003
6-1
CONTENTS
MCS®-51 PROGRAMMER'S
GUIDE AND INSTRUCTION
SET
PAGE
MEMORY ORGANiZATION ........... ... 6-4
PROGRAM MEMORY ............ ~ ....... 6-4
Data Memory ............................. 6-5
INDIRECT ADDRESS AREA ............. 6·7
DIRECT AND INDIRECT ADDRESS
AREA .................................. 6-7
SPECIAL FUNCTION REGISTERS ....... 6-9
- WHAT DO THE SFRs CONTAIN JUST
AFTER POWER-ON OR A RESET .... 6-10
SFR MEMORY MAP .................... 6-11
PSW: PROGRAM STATUS WORD. BIT
ADDRESSABLE ...................... 6-12
PCON: POWER CONTROL REGISTER.
NOT BIT ADDRESSABLE ............ 6-12
INTERRUPTS ........................... 6-13
IE: INTERRUPT ENABLE REGISTER.
BIT ADDRESSABLE .................. 6-13
ASSIGNING HIGHER PRIORITY TO
ONE OR MORE INTERRUPTS ........ 6-14
PRIORITY WITHIN LEVEL .............. 6-14
IP: INTERRUPT PRIORITY REGISTER.
BIT ADDRESSABLE .................. 6-14
TCON: TIMER/COUNTER CONTROL
REGISTER. BIT ADDRESSABLE ..... 6-15
TMOD: TIMER/COUNTER MODE
CONTROL REGISTER. NOT BIT
ADDRESSABLE ...................... 6-15
TIMER SET-UP ......................... 6-16
TIMER/COUNTER 0 .................... 6-16
TIMER/COUNTER 1 .............
n ......
6-17
T2CON: TIMER/COUNTER 2 CONTROL
REGISTER. 13IT ADDRESSABLE ..... 6-18
TIMER/COUNTER 2 SET-UP ........... 6-19
SCON: SERIAL PORT CONTROL
REGISTER. BIT ADDRESSABLE ..... 6-20
6-2
CONTENTS
CONTENTS
PAGE
SERIAL PORT SET·UP ................. 6·20
PAGE
USING TIMER/COUNTER 2 TO
GENERATE BAUD RATES ........... 6·21
GENERATING BAUD RATES ........... 6·20
Serial Port in Mode a .................... 6·20
Serial Port in Mode 1 .................... 6·20
SERIAL PORT IN MODE 2 .............. 6·21
USING TIMER/COUNTER 1 TO
GENERATE BAUD RATES ........... 6·21
MCS®·51 INSTRUCTION SET .......... 6·22
SERIAL PORT IN MODE 3 .............. 6·21
INSTRUCTION DEFINITIONS ~ .......... 6·29
6·3
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MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
The information presented in this chapter is collected from the MCS®-5! Architectural Overview and the Hardware
Description of the 8051, 8052 and 80C5! chapters of this book. The material has been selected and rearranged to
form a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the
8051, 8052 and 80C51.
MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separate address spaces for Program Memory and Data Memory. The Program Memory can be up to
64K bytes long. The lower 4K (8K for the 8052) may reside on-chip.
Figure 1 shows a map of the 8051 program memory, and Figure 2 shows a ma~ of the 8052 program memory.
FFFF r - - - - - - - - - - - - ,
FFFFr------------,
&oK
BYTES
EXTERNAL
84K
--OR--.~
BYTES
EXTERNAL
1000 .....----------~
AND
O~Fr_-----------------__,
4KBYTES
INTERNAL
0000 ....... _ _ _ _ _ _ _ _ _.J
0000 .......---------~
270249-1
Figure 1. The 8051 Program Memory
6-4
int'et
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
FFFF , - - - - - - - - - - - - ,
FFFF r-----------~
58K
BYTES
EXTERNAL
64K
- - O R - - - i....
BYTES
EXTERNAL
2000 ' - - - - - - - - - - - - 1
AND
lFFF r - - - - - - - - - - - - ,
BK BYTES
INTERNAL
~~---------~
~ ~-----------~
270249-2
Figure 2. The 8052 Program Memory
Data Memory:
The 8051 can address up to 64K bytes of Data Memory external to the chip. The "MOYX" instruction is- used to
access the external data memory. (Refer to the MCS-51 Instruction Set, in this chapter, for detailed description of
instructions).
The 8051 has 128 bytes of on-chip RAM (256 bytes in the 8052) plus a number of Special Function Registers (SFRs).
The lower 128 bytes of RAM can be accessed eithe!" by direct addressing (MOY data addr) or by indirect addressing
(MOY @Ri). Figure 3 shows the 8051 and the 8052 Data Memory organization.
6-5
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MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
OFFFr-------------------~
INTERNAL
FF..------------.
84K
BYTES
EXTERNAL
SFR.
DIRECT
ADDRESSING
ONLY
80
7F~-----------------~
- - AND
----l• •
DIRECT &
INDIRECT
ADDRESSING
oo~--------~
oooo~---------j
270249-3
Figure 3a. The 8051 Data Memory
FFFF,--------------------,
INTERNAL
f
INDIRECT
ADDRESSING ONLY
80H TO FFH
FFI
FFr-~-------~
SFR.
DIRECT
ADDRESSING
ONLY
14K
BYTES
EXTERNAL
I--AND~
80
7Fr---------~
DIRECT &
INDIRECT
ADDRESSING
001------------1
0000 ' - - - - - - - - - - - - - - - - - - - -......
270249-4
Figure 3b. The 8052 Data Memory
6-6
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MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses (80H-OFFH). Nevertheless, they are two separate areas and are accessed in two different ways.
For example the instruction
MOY
80H,#OAAH
writes OAAH to Port 0 which is one of the SFRs and the instruction
MOY
RO,#80H
MOY
@RO,#OBBH
writes OBBH in location 80H of the data RAM. Thus, after execution of both of the above instructions Port 0 will
contain OAAH and location 80 of the RAM will contain OBBH.
Note that the stack operations are examples of indirect addressing, so .the upper 128 bytes of data RAM are available
as stack space in those devices which implement 256 bytes of internal RAM.
DIRECT AND INDIRECT ADDRESS AREA:
The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments
as listed below and shown in Figure 4.
1. Register Banks 0-3: Locations 0 through IFH (32 bytes). ASM-51 and the device after reset default to register
bank O. To use the other register banks the user must select them in the software (refer to the MCS-51 Micro
Assembler User's Guide). Each register blink contains 8 one-byte registers, 0 through 7.
Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the
first register (RO) of the second register bank. Thus, in order to use more than one register bank, the SP should be
intialized to a different location of the RAM where it is not used for data storage (ie, higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this
segment can be directly addressed (0-7FH).
The bits can be referred to in two ways both of which are acceptable by the ASM-51. One way is to refer to their
addresses, ie. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.
Each of the 16 bytes in this segment can also be addressed as a byte.
3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if the stack pointer
has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction.
6-7
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Figure 4 shows the different segments of the on-chip RAM.
--------8 Byte. - - - - - -.....~I
.......
78
7F
70
n
68
SF
60
67
5&
SF
50
57
46
4F
40
47
38
3F
30
37
SCRATCH
PAD
... 7F
28
20
0 ...
2F
27
AREA
BIT
ADDRESSAB LE
SEGMENT
18
3
1F
10
2
17
REGISTER
08
1
OF
BANKS
00
0
07
270249-5
Figure 4. 128 Bytes of RAM Direct and Indirect Addressable
6-8
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SPECIAL FUNCTION REGISTERS:
Table I contains a list of all the SFRs and their addresses.
Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first
column of the diagram in Figure 5.
Table 1
Symbol
'ACC
'B
'PSW
SP
DPTR
DPL
DPH
'PO
'P1
'P2
'P3
'IP
"IE
TMOD
"TCON
'+ T2CON
THO
TLO
TH1
TL1
+TH2
+TL2
+ RCAP2H
+ RCAP2L
'SCON
SBUF
PCON
Name
Accumulator
B Register
Program Status Word
Stack Pointer
Data Pointer 2 Bytes
Low Byte
High Byte
Port 0
Port 1
Port 2
Port 3
Interrupt Priority Control
Interrupt Enable Control
Timer/Counter Mode Control
Timer/Counter Control
Timer/Counter 2 Control
Timer/Counter 0 High Byte
Timer/Counter 0 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 1 Low Byte
Timer/Counter 2 High Byte
Timer/Counter 2 Low Byte
T /C 2 Capture Reg. High Byte
T /C 2 Capture Reg. Low Byte
Serial Control
Serial Data Buffer
Power Control
• = Bit addressable
+
=
8052 only
6-9
Address
OEOH
OFOH
ODOH
81H
82H
83H
80H
90H
OAOH
OBOH
OB8H
OA8H
89H
88H
OC8H
8CH
8AH
SDH
8BH
OCDH
OCCH
OCBH
OCAH
98H
99H
87H
intel .
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
WHAT DO THE SFRs CONTAIN JUST AFTER POWER·ON OR A RESET?
Table 2 lists the contents of ~ch SFR after power-on or a hardware reset.
Table 2. Contents of the SFRs after reset
Register
Value In Binary
'ACC
00000000
00000000
00000000
00000111
·S
'PSW
SP
DPTR
DPH
DPL
'PO
'P1
'P2
*P3
*IP
00000000
00000000
11111111
11111111
11111111
11111111
8051 XXXOOOOO,
8052 XXOOOOOO
80510XXOOOOO,
8052 OXOOOOOO
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Indeterminate
HMOS OXXXXXXX
CHMOS OXXXOOOO
'IE
TMOD
'TCON
*+T2CON
THO
TLO
TH1
TL1
+TH2
+TL2
+ RCAP2H
+ RCAP2L
'SCON
SBUF
PCON
x -•
+
Undefined
= Bit Addressable
= 8052 only
6-10
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SFR MEMORY MAP
8 Bytes
F8
FO
FF
B
F7
EF
E8
EO
ACC
E7
OF
08
DO
C8
PSW
T2CON
07
RCAP2L
RCAP2H
TL2
TH2
CF
CO
B8
BO
A8
AO
98
90
88
80
C7
IP
P3
IE
P2
SCON
P1
TCON
PO
i
BF
B7
AF
A7
SBUF
9F
97
TMOO
SP
TLO
OPL
TL1
OPH
Figure 5
Bit
Addressable
6-11
THO
TH1
8F
PCON
87
intel .
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit
is provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.
PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
CY
AC
CY
AC
FO
RSI
RSO
OV
PSW.7
PSW.6
P
psw.o
psw.s
PSW.4
PSW.3
PSW.2
PSW.I
FO
RS1
RSO
P
OV
Carry Flag.
Auxiliary Carry Flag.
Flag 0 available to the user for general purpose.
Register Bank selector bit 1 (SEE NOTE I).
Register Bank selector bit 0 (SEE NOTE I).
Overflow Flag.
User defimlble flag.
Paritytlag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of
'I' bits in the accumulator.
NOTE:
1. The value presented by RSO and RS1 selects the corresponding register bank.
RS1
RSO
Register Bank
Address
0
0
1
1
0
1
0
1
0
1
2
3
OOH-07H
OSH-OFH
10H-17H
1SH-1FH
PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOD
GF1
GFO
PO
IDL
SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled
when the Serial Port is used in modes I, 2, or 3.
Not implemented, reserved for future use.·
Not implemented, reserved for future use.·
Not implemented, reserved for future use. •
GFI
General purpose flag bit.
GFO
General purpose flag bit.
PD
Power Down bit. Setting this bit activates Power Down operation in the 8OCSIBH. (Availabie oniy in
CHMOS).
.
IDL
Idle Mode bit. Setting this bit activates Idle Mode operation in the 80CSIBH. (Available only in CHMOS).
If Is are written to PD and IDL at the same time, PD takes precedence.
'User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
6-12
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MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INTERRUPTS:
In order to use any of the interrupts in the MCS-51, the following.three steps must be taken.
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below.
Interrupt
Source
Vector
Address
lEO
TFO
IE1
TF1
RI&TI
TF2& EXF2
0003H
OOOBH
0013H
001BH
0023H
002BH
In addition, for external interrupts, pins INTO and INTI (p3.2 and P3.3) must be set to 1, and depending on whether
the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1.
ITx = 0 level activated
ITx = 1 transition activated
IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.
EA
ET2
EA
IE.7
ET2
ES
ETI
EXI
ETO
EXO
IE.6
IE.5
lEA
IE.3
IE.2
IE.!
IE.O
ES
ET1
EX1
ETO
EXO
Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Not implemented, reserved for future use.'
Enable or disable the Timer 2 overflow or capture interrupt (8052 only).
Enable or disable the serial port interrupt.
Enable or disable the Timer 1 overflow interrupt.
Enable or disable External Interrupt 1.
Enable or disable the Timer 0 overflow interrupt.
Enable or disable External Interrupt O.
'User software should not write Is to reserved bits. These bits may be used in future MCS-51 products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be I.
6-13
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MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt th~ corresponding bit in the IP register must be set to 1.
Remember that while an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt.
PRIORITY WITHIN LEVEL:
Priority within level is only to resolve simultaneous requests of the same priority level.
From high to low, interrupt sources are listed below:
lEO
TFO
lEI
TFI
RI or TI
TF2 or EXF2
IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a
higher priority.
I '- I
PT2
PS
PTI
PXl
PTO
PXO
IP.7
IP. 6
IP.5
IP. 4
IP.3
IP.2
IP. 1
IP. 0
PT2
PS
PT1
PX1
PTO
PXO
Not implemented, reserved for future use.'
Not implemented, reserved for futQl'e use.'
Defines the Timer 2 interrupt priority level'(8052 only).
Defines the Serial Port interrupt priority level.
Defines the Timer 1 interrupt priority level.
Defines External Interrupt 1 priority level.
Defines the Timer 0 interrupt priority level.
Defines the External Interrupt 0 priority level.
'User software should not write Is to reserved bits. These bits may be used in future MeS-51 products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
6-14
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MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TCON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.
TF1
TFI
TRI
TFO
TRO
IEI
IT!
IEO
ITO
TR1
TFO
TRO
IE1
IT1
lEO
ITO
TCON.7 Timer I overflow flag. Set by hardware when the Timer/Counter I overflows. Cleared by hardware as processor vectors to the interrupt service routine.
TCON.6 Timer I run control bit. Set/cleared by software to turn Timer/Counter ION/OFF.
TCON.5 Timer 0 overflow flag. Set by·hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine.
TCON.4 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.
TCON.3 External Interrupt I edge flag. Set by hardware when External Interrupt edge is detected.
Cleared by hardware when interrupt is processed.
TCON.2 Interrupt I type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
TCON. I External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
TCON.O Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE ..
I
CIT
GATE
M1
MO
\:
)
GATE
CIT
MI
MO
I\: GATE
CIT
M1
MO
)
I
TIMER I
TIMER 0
When TRx (in TCON) is set and GATE = I, TIMER/COUNTERx will run only while INTx pin is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = I (software
control).
Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin).
Mode selector bit. (NOTE I)
Mode selector bit. (NOTE I)
NOTE 1:
M1
o
o
1
MO
Operating Mode
o
o
1
1
2
3
o
1
3
13-bit Timer (MCS-48 compatible)
16-bit Timer/Counter
8-bit Auto-Reload Timer/Counter
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0
control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits.
(Timer 1) Timer/Counter 1 stopped.
6-15
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER SET-UP
Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes.
It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and 1 simultaneously, in any
mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6).
For example, if it is desired to run Timer 0 in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER,
then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover, it is assumed that the user, at this point, is not ready to turn the timers on and will do that at a different
point in the program by setting bit TRx (in TCON) to 1.
TIMER/COUNTER 0
As a Timer:
Table 3
TMOD
MODE
TIMER 0
FUNCTION
0
1
2
3
13·bit Timer
16·bit Timer
a·bit Auto·Reload
two a·bit Timers
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
. OOH
01H
02H
03H
08H
09H
OAH
OBH
As a Counter:
Table 4
TMOD
MODE
COUNTER 0
FUNCTION
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
0
1
2
3
13·bit Timer
16·bit Timer
a·bit Auto·Reload
one 8·bit Counter
04H
05H
06H
07H
OCH
ODH
OEH
OFH
NOTES:
1. The Timer is turned ON/OFF by setting/clearing bit TRO in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INTO (P3.2) when TRO = 1
(hardware control).
6·16 .
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER/COUNTER 1
As a Timer:
Table 5
TMOD
MODE
TIMER 1
FUNCTION
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
0
1
2
3
13-bit Timer
16-bit Timer
8-bit Auto-Reload
does not run
OOH
10H
20H
30H
80H
90H
AOH
BOH
As a Counter:
TableS
TMOD
MODE
COUNTER 1
FUNCTION
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
0
1
2
3
13-bit Timer
16-bit Timer
8-bit Auto-Reload
not available
40H
50H
60H
COH
DOH
EOH
-
-
NOTES:
1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) when TR1 = 1
(hardware control).
6-17
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
I TF2
EXF2
RCLK
TCLK
EXEN2
TR2
TF2
C/T2
CP/RL2
T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
either RCLK = 1 or CLK = 1
T2CON. 6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on
EXF2
T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK
T2CON.5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes 1 & 3. RCLK = 0 causes Timer t' overflow to be used for the receive
clock.
TLCK
T2CON. 4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes 1 & 3. TCLK = 0 causes Timer 1 overflows to be used for the
transmit clock.
EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative trap.sition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2 Software START/STOP control for Timer 2. A logic 1 starts the Timer.
C/T2
T2CON.l Timer or Counter select.
o = Internal Timer. 1 = External Event Counter (falling edge triggered).
CP/RL2 T2CON.O Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = I,
this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow.
6-18
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
TIMER/COUNTER 2 SET-UP
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to tum the Timer on.
As a Timer:
Table 7
T2CON
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
16-bit Auto-Reload
OOH
OSH
16-bit Capture
01H
09H
BAUD rate generator receive &
transmit same baud rate
34H
36H
receive only
24H
26H
transmit only
14H
16H
MODE
As a Counter:
TableS
TMOD
MODE
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
16-bit Auto-Reload
16-bit Capture
02H
03H
OAH
OBH
NOTES:
1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX
(P1.1) pin except when Timer 2 is used in the baud rate generating mode.
6-19
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MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.
SMO
SMO
SMI
SM2
SM1
SM2
REN
RB8
TB8
TI
RI
SCON.7 Serial Port mode specifier. (NOTE 1).
SCON.6 Serial Port mode specifier. (NOTE 1).
SCON. 5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, if SM2 is set
to I then RI will not be activated if the received 9th data bit (RBS) is O. In mode 1, ifSM2 = 1
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be O.
(See Table 9).
SCON. 4 Set/Cleared by software to Enable/Disable reception.
REN
SCON. 3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.
SCON.2 In modes 2 & 3, is the 9th data bit that was received. In mode 1, ifSM2 = 0, RBS is the stop bit
that was received. In mode 0, RBS is not used.
SCON. 1 Transmit interrupt flag. Set by hardware at the end of the Sth bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
SCON. 0 Receive interrupt flag. Set by hardware at the end of the Sth bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by software.
TBS
RBS
TI
RI
NOTE 1:
SMO
SM1
Mode
Description
Baud Rate
o
0
1
0
0
1
2
SHIFT REGISTER
8-Bit UART
9-Bit UART
3
9-Bit UART
Fosc.l12
Variable
Fosc.l64 OR
Fosc.l32
Variable
o
1
SERIAL PORT SET-UP:
Table 9
MODE
SeON
SM2 VARIATION
0
1
2
3
10H
50H
90H
DOH
Single Processor
Environment
(SM2 = 0)
0
1
2
3
NA
70H
BOH
FOH
Multiprocessor
Environment
(SM2 = 1)
GENERATING BAUD RATES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of
the Timer/Counters need to be set up. Only the SCON register needs to be defined.
Baud Rate
=
Osc Freq
--1-2-
Serial Port in Mode 1:
Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (S052 only).
6-20
intel..
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter.
B dR
_
K x Oscillator Freq.
au
ate - 32 x 12 x [256 - (TH1)1
If SMOD = 0, then K = 1.
If SMOD = 1, then K = 2. (SMOD is the PCON register).
Most of the time the user knows the baud rate and needs to know the reload value for TH1.
Therefore, the equation to calculate THI can be written as:
TH1 = 256 _ K x Osc Freq.
384 x baud rate
THI must be an integer value. Rounding off THI to the nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORmg the PCON register. (ie, ORL
PCON, # SOH). The address of PCON is S7H.
USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:
For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is being clocked through pin T2 (P1.0) the baud rate is:
B
Timer 2 OverflOW Rate
R
au d ate =
16
And if it is being clocked internally the baud rate is:
Bau
dR
Osc Freq
ate = 32 x [65536 - (RCAP2H, RCAP2L)l
To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as:
RCAP2H, RCAP2L = 65536 _
O:c F~e~
32 x au
ate
SERIAL PORT IN MODE 2:
The baud rate is fixed in this mode and is
bit in the PCON register.
'1S2 or '1.4 of the oscillator frequency depending on the value of the SMOD
In this mode none of the Timers are used and the clock comes from the internal phase 2 clock.
SMOD
= 1, Baud Rate = '1S2 Osc Freq.
SMOD = 0, Baud Rate =
To set the SMOD bit: ORL
'1.4 Osc Freq.
PCON,#SOH. The address of PCON is S7H.
SERIAL PORT IN MODE 3:
The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.
6-21
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MCS®-S1 INSTRUCTION SET
Table 10. 8051 Instruction Se~ Summary
Interrupt Response Time: Refer to Hardware De·
scription Chapter.
Mnemonic
ADD
ADDC
SUSS
MUL
DIV
DA
RRC
RLe
SETSC
Flag
Instruction
C OV AC
X X
X CLRC
X CPLC
X X
X X
X ANLC,bit
ANLC,Ibit
0 X
ORLC,bit
0 X
X
ORLC,bit
MOVC,bit
X
X
CJNE
Byte
Oscillator
Period
ARITHMETIC OPERATIONS
A,Rn
ADD
Add register to
12
Accumulator
ADD
A,direct Add direct byte to
12
2
Accumulator
A,@Ri
ADD
Add indirect RAM
12
to Accumulator
A,#data Add immediate
ADD
2
12
data to
Accumulator
AD DC A,Rn
Add register to
12
Accumulator
with Carry ,
ADDC A,direct Add direct byte to
2
12
Accumulator
with Carry
AD DC A,@Ri
Add indirect
12
RAM to
Accumulator
with Carry
ADDC A,#data Add immediate
2
12
data to Acc
with Carry
Subtract Register
SUSS A,Rn
12
from Acc with
borrow
2
12
SUSS A,direct Subtract direct
byte from Acc
with borrow
SUSS A,@Ri
Subtract indirect
12
RAMfromACC
with borrow
SUSS A,#data Subtract
2
12
immediate data
from Acc with
borrow
INC
Increment
12
A
Accumulator
INC
Rn
Increment register
12
INC
direct
Increment direct
2
12
byte
@Ri
INC
Increment direct
12
RAM
DEC
A
Decrement
12
Accumulator
DEC
Rn
Decrement
12
Register
DEC
direct
Decrement direct
2
12
byte
@Ri
DEC
Decrement
12
indirect RAM
All mnemonics copyrighted ©Intel Corporation 1980
Instructions that Affect Flag Settings(l)
Instruction
Description
Flag
C OV AC
0
X
X
X
X
X
X
X
(I)Note that operations on SFR byte address 208 or
bit addresses 209-215 (i.e., the PSW or bits in the
PSW) will also affect flag settings.
Note on instruction set and addressing modes:
Rn
- Register R7-RO of the currently selected Register Bank.
direct
- 8-bit internal data location's address.
This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O
port, control register, status register,
etc. (128-255)).
@Ri
- 8-bit internal data RAM location (0255) addressed indirectly through register Rl or RO.
# data
- 8-bit constant included in instruction.
#data 16 - 16-bit constant included in instruction.
addr 16 - 16-bit destination address. Used by
LCALL & UMP. A branch can be
anywhere within the 64K-byte Program Memory address space.
addr 11 - II-bit destination address. Used by
ACALL & AJMP. The branch will be
within the same 2K-byte page of program memory as the first byte of the
following instruction.
-'- Signed (two's complement) 8-bit offset
rei
byte. Used by SJMP and all conditional jumps. Range is - 128 to + 127
bytes relative to first byte of the following instruction.
bit
- Direct Addressed bit in Internal Data
RAM or Special Function Register.
6-22
intel~
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10.8051 Instruction Set Summary (Continued)
Mnemonic
Description
Byte
ARITHMETIC OPERATIONS (Continued)
INC DPTR
Increment Data
Pointer
MUL AS
Multiply A & S
DIV AS
DivideAby8
Decimal Adjust
DA
A
Accumulator
LOGICAL OPERATIONS
ANL A,Rn
AND Registerto
Accumulator
ANL A,direct
AND direct byte
to Accumulator
ANL A,@Ri
AND indirect
RAM to
Accumulator
ANL A,#data
AND immediate
data to
Accumulator
ANL direct,A
AND Accumulator
to direct byte
ANL direct, # data AND immediate
data to direct byte
ORL A,Rn
OR register to
Accumulator
OR direct byte to
ORL A,direct
Accumulator
OR indirect RAM
ORL A,@Ri
to Accumulator
ORL A,#data
OR immediate
data to
Accumulator
ORL direct,A
OR Accumulator
to direct byte
ORL direct, #data OR immediate
data to direct byte
XRL A,Rn
Exclusive-OR
register to
Accumulator
Exclusive-OR
XRL A,direct
direct byte to
Accumulator
XRL A,@Ri
Exclusive-OR
indirect RAM to
Accumulator
XRL A,#data
Exclusive-OR
immediate data to
Accumulator
Exclusive-OR
XRL direct,A
Accumulator to
direct byte
XRL direct, # data Exclusive-OR
immediate data
to direct byte
CLR A
Clear
Accumulator
Complement
CPL A
Accumulator
Oscillator
Period
Mnemonic
LOGICAL OPERATIONS (Continued)
Rotate
RL
A
Accumulator Left
A
Rotate
RLC
Accumulator Left
through the Carry
RR
A
Rotate
Accumulator
Right
RRC
A
Rotate
Accumulator
Right through
the Carry
Swap nibbles
SWAP A
within the
Accumulator
DATA TRANSFER
Move
MOV A,Rn
register to
Accumulator
MOV A,direct
Move direct
byte to
Accumulator
MOV A,@Ri
Move indirect
RAM to
Accumulator
MOV A,#data
Move
immediate
data to
Accumulator
Move
MOV Rn,A
Accumulator
to register
MOV Rn,direct
Move direct
byte to
register
MOV Rn,#data
Move
immediate data
to register
Move
MOV direct,A
Accumulator
to direct byte
Move register
MOV direct,Rn
to direct byte
MOV direct,direct Move direct
byte to direct
Move indirect
MOV direct,@Ri
RAM to
direct byte
MOV direct, # data Move
immediate data
to direct byte
MOV @Ri,A
Move
Accumulator to
indirect RAM
24
48
48
12
12
2
12
12
2
12
2
12
3
24
12
2
12
12
2
12
2
12
3
24
12
2
12
12
2
12
2
12
3
24
Description
12
12
Byte
Oscillator
Period
12
12
12
12
12
12
2
12
12
2
12
12
2
24
2
12
2
12
2
24
3
24
2
24
3
24
12
All mnemonics copyrighted © Intel Corporation 1980
6-23
intet
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10. 8051 Instruction Set Summary (Continued)
Mnemonic
Description
DATA TRANSFER (Continued)
@Ri,direct
Move direct
MOV
byte to
indirect RAM
Move
MOV @Ri,#data
immediate
data to
indirect RAM
MOV DPTR,#data16 Load Data
Pointer with a
16-bit constant
MOVC A,@A+DPTR
Move Code
byte relative to
DPTR toAcc
MOVC A,@A+PC
Move Code
byte relative to
PC to Acc
MOVX A,@Ri
Move
External
RAM (B-bit
addr) to Acc
MOVX A,@DPTR
Move
External
RAM (16-bit
addr) to Acc
MOVX @Ri,A
Move Acc to
External RAM
(a-bit addr)
MOVX @DPTR,A
MoveAcc to
External RAM
(16-bit addr)
PUSH direct
Push direct
byte onto
stack
POP
direct
Pop direct
byte from
stack
XCH
A,Rn
Exchange
register with
Accumulator
XCH
A,direct
Exchange
direct byte
with
Accumulator
A,@Ri
XCH
Exchange
indirect RAM
with
Accumulator
XCHD A,@Ri
Exchange loworder Digit
indirect RAM
withAcc
Byte
Oscillator
Period
2
24
2
12
3
24
Mnemonic
24
24
24
24
24
24
2
24
12
2
Byte
BOOLEAN VARIABLE MANIPULATION
Clear Carry
CLR
C
1
CLR
bit
Clear direct bit
2
SETB
Set Carry
1
C
Set direct bit
2
SETB
bit
CPL
Complement
C
Carry
CPL
bit
Complement
2
direct bit
C,bit
AND direct bit
2
ANL
to CARRY
ANL
C,Ibit
AND complement
2
of direct bit
to Carry
C,bit
OR direct bit
ORL
2
to Carry
C,Ibit
OR complement
2
ORL
of direct bit
to Carry
MOV
C,bit
Move direct bit
2
to Carry
MOV
bit,C
Move Carry to
2
direct bit
JC
rei
Jump if Carry
2
is set
JNC
rei
Jump if Carry
2
not set
JB
bit,rel
Jump if direct
3
Bit is set
Jump if direct
JNB
bit,rel
3
Bit is Not set
JBC
bit,rel
Jump if direct
3
Bit is set &
clear bit
PROGRAM BRANCHING
ACALL addrll Absolute
2
Subroutine
Call
LCALL addr16 Long
3
SubroutinEi
Call
RET
Return from
Subroutine
RETI
Return from
interrupt
AJMP
addrll Absolute
2
Jump
LJMP
addr16 Long Jump
3
SJMP
rei
Short Jump
2
(relativeaddr)
24
2
Description
12
12
12
Oscillator
Period
12
12
12
12
12
12
24
24
24
24
12
24
24
24
24
24
24
24
24
24
24
24
24
24
All mnemonics copyrighted © Intel Corporation 1980
6-24
int:et
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 10. 8051 Instruction Set Summary (Continued)
Mnemonic
Description
Byte
Oscillator
Period
Mnemonic
PROGRAM BRANCHING (Continued)
JMP
@A+DPTR
JZ
rei
JNZ
rei
CJNE
A,direct,rel-
CJNE
A,#data,rel
Jump indirect
relative to the
DPTR
Jump if
Accumulator
is Zero
Jump if
Accumulator
is Not Zero
Compare
direct byte to
AccandJump
if Not Equal
Compare
immediate to
AccandJump
if Not Equal
Description
Byte
Oscillator
Period
3
24
3
24
2
24
3
24
PROGRAM BRANCHING (Continued)
24
2
24
2
24
3
24
CJNE
CJNE
DJNZ
3
24
DJNZ
NOP
Rn, # data,rel
Compare
immediate to
register and
Jump if Not
Equal
@Ri,#data,rel Compare
immediate to
indirect and
Jump if Not
Equal
Rn,rel
Decrement
register and
Jump if Not
Zero
direct,rel
Decrement
direct byte
and Jump if
\ NotZero
No Operation
12
All mnemonics copyrighted @Intel Corporation 1980
6-25
intel·
MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 11.lnstru'ctlon Opcodes In Hexadecimal Order
Hex
Code
00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F
30
31
32
Number
of Bytes
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
2
1
Mnemonic
NOP
AJMP
LJMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
. INC
INC
J8C
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
J8
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JN8
ACALL
RETI
Hex
Code
Operands
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
43
codeaddr
codeaddr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr, code addr
code addr
code addr
A
A
data addr
@RO
@R1
RO
R1
R2
R3
R4
R5
R6
R7
bit addr, code addr
codeaddr
44
45
46
47
48
49
4A
48
4C
4D
4E
4F
50
5.1
52
53
54
55
56
57
58
59
5A
58
5C
5D
5E
5F
60
61
62
63
64
65
A
A,#data
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bit addr, code addr
codeaddr
6-26
Number
of Bytes
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
Mnemonic
RLC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ.
AJMP
XRL
XRL
XRL
XRL
Operands
A
A,#data
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
co'cleaddr
codeaddr
dataaddr,A
data addr, # data
A,#data
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
dataaddr,A
data addr, # data
. A,#data
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
dataaddr,A
data addr,#data
A,#data
A,dataaddr
intet
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 11. Instruction Opcodes in Hexadecimal Order (Continued)
Hex
Code
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
13
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
Number
of Bytes
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
Mnemonic
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
AJMP
ANL
MOVC
DIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
Hex
Code
Operands
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code addr
code addr
C,bitaddr
@A+DPTR
A,#data
data addr,#data
@RO,#data
@R1,#data
RO,#data
R1,#data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
code addr
code addr
C,bitaddr
A,@A+PC
AB
data addr, data addr
data addr,@RO
data addr,@R1
data addr,RO
data addr,R1
data addr,R2
data addr,R3
data addr,R4
data addr,R5
data addr,R6
data addr,R7
DPTR,#data
codeaddr'
bitaddr,C
A,@A+DPTR
A,#data
A,dataaddr
A,@RO
A,@R1
A,RO
99
9A
9B
9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
6-27
Number
of Bytes
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
1
1
1
1
1
1
Mnemonic
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reserved
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
XCH
XCH
XCH
XCH
XCH
XCH
Operands
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
C,Ibit addr
code addr
C,bitaddr
DPTR
AB
@RO,data addr
@R1,data addr
RO,data addr
R1 ,data addr
R2,data addr
R3,data addr
R4,data addr
R5,data addr
R6,data addr
R7,data addr
C,Ibit addr
code addr
bit addr
C
A,#data,code addr
A,data addr,code addr
@RO,#data,codeaddr
@R1,#data,codeaddr
RO,#data,code addr
R1,#data,code addr
R2,#data,code addr
R3,#data,code addr
R4,#data,code addr
R5,#data,code addr
R6, # data, code addr
R7, # data, code addr
data addr
I
code addr
bit addr
C
A
A,dataaddr
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
int:et
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Table 11. Instruction Opcodes in Hexadecimal Order (Continued)
Hex
Code
CC
CD
CE
CF
DO
D1
D2
D3
D4
D5
DS
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
Number
of Bytes
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
Mnemonic
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
DA
DJNZ
XCHD
XCHD
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
Hex
Code
Operands
ES
E?
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
FS
F?
F8
F9
FA
FB
FC
FD
FE
FF
A.R4
A,R5
A,RS
A,R7
data addr
codeaddr
bit addr
C
A
data addr,code addr
A,@RO
A,@R1
RO,code addr
R1,code addr
R2,code addr
R3,code addr
R4,code addr
R5,code addr
RS,code addr
R7,code addr
A,@DPTR
code addr
A,@RO
A,@R1
A
A,dataaddr
6·28
, Number
of Bytes
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
Mnemonic
Operands
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A,@RO
A,@R1
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,RS
A,R?
@DPTR,A
code addr
@RO,A
@R1,A
A
dataaddr,A
@RO,A
@R1,A
RO,A
R1,A
R2,A
R3,A
R4,A
R5,A
RS,A
R7,A
int:eL
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
INSTRUCTION DEFINITIONS
ACALL
addr11
Function:
Absolute Call
Description:
ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The
destination address is obtained by successively concatenating the five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called
must therefore start within the same 2K block of the program memory as the first byte of the
instruction following ACALL. No flags are affected.
Example:
Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After
executing the instruction,
ACALL
SUBRTN
at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain
25H and OIH, respectively, and the PC will contain 0345H.
Bytes:
2
Cycles:
2
Encoding:
Operation:
_a_1_0_a_9_a8_-.1._0_ 0_ 0 _1--,
1-1
a7 a6 a5 a4
ACALL
(PC) ~ (PC) + 2
(SP) ~ (SP) + I
«SP» ~ (PC7-0)
(SP) ~ (SP) + I
«SP» ~ (PCI5-S)
(PC10-O) ~ page address
6-29
a3 a2 a1 aO
intel.,
ADD
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,
Function:
Description:
Add
ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indiCiltes an
overflow occured.
OV is set if there isa carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number pro-
duced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example:
The Accumulator holds OC3H (1IOOOOllB) and register 0 holds OAAH (10 10 10 lOB). The
instruction,
ADD
A,RO
will leave 6DH (01 101 lOlB) in the Accumulator with the AC flag cleared and both the carry
flag and 0 V set to 1.
ADD
A,Rn
Bytes:
Cycles:
Encoding:
Operation:
ADD
I0 0
0
ADD
(A) ~ (A)
1 r r r
+
(Rn)
A,dlrect
Bytes:
2
Cycles:
Encoding:
Operation:
I 00
o1
0
ADD
(A) ~ (A)
+
0 1
direct address
(direct)
6-30
int:et
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,@Ri
ADD
Bytes:
Cycles:
Encoding:
100 1 0
Operation:
ADD
(A) ~ (A)
011
+
«Rj»
A, # data
ADD
Bytes:
2
Cycles:
Encoding:
100 1 0
Operation:
ADD
(A)~(A)
ADDC
o1
+
0 0
immediate data
# data
A, < src-byte >
Function:
Description:
Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator
contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding
unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of
bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as·the sum of two positive operands or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example:
The Accumulator holds OC3H (1 100001 IB) and register 0 holds OAAH (10101010B) with the
carry flag set. The instruction,
ADDC A,RO
will leave 6EH (01101 1 lOB) in the Accumulator with AC cleared and both the Carry flag and
OV set to 1.
6-31
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ADDC
A,Rn
Bytes:
Cycles:
Encoding:
Operation:
ADDC
I
°°
1
ADDC
(A) -- (A)
r r r 1
+
(C)
+ (RJ
A,dlrect
Bytes:
2
Cycles:
Encoding:
1.. 1_o_o_1_-,--0_1_o_1-,
Operation:
ADDC
(A) -- (A)
ADDC
+
(C)
+
direct address
(direct)
A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
ADDC
I °° 1 1 °1 .1 i
ADDC
(A) -- (A)
+
(C)
+
«Rj))
A,#data
Bytes:
2
Cycles:
Encoding:
1,--0_o_1_-,--0_1_0_0-,
Operation:
ADDC
(A) -- (A)
+
(C)
+
immediate data
#data
6-32
infel .
AJMP
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
addr11
Function:
Description:
Example:
Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte of the instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP
JMPADR
is at location 0345H and will load the PC with 0123H.
Bytes:
2
Cycles:
2
Encoding:
Operation:
ANL
I a10 a9 a8 0
0 0 0 1
a7 a6 a5 a4
a3 a2 a1 aO
AJMP
(PC) - (PC) + 2
(PCIO"() -page address
< dest-byte > , < src-byte >
Function:
Description:
Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins. .
Example:
If the Accumulator holds OC3H (1 100001 IB) and register 0 holds 55H (OlOlOlOlB) then the
instruction,
ANL
A,RO
will leave 4IH (OlOOOOOlB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
the Accumulator at run-time. The instruction,
ANL Pl,#OlllOOllB
will clear bits 7, 3, and 2 of output port 1.
6-33
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ANL
A,Rn
Bytes:
Cycles:
ANL
Encoding:
1 01
Operation:
ANL
(A) -
o1
1 r r r
(A) 1\ (Rn)
A,dlrect
Bytes:
2
Cycles:
Encoding:
1 01
Operation:
ANL
(A) -
ANL
o1
o10
1
direct address
(A) 1\ (direct)
A,@RI
Bytes:
Cycles:
Encoding:
1 01
Operation:
ANL
(A) -
ANL
o1
o1
1
(A) 1\ «Ri»
A, # data
Bytes:
2
Cycles:
ANL
Encoding:
1 01
Operation:
ANL
(A) -
o1
o10
0
immediate data
(A) 1\ #data
dlrect,A
Bytes:
2
• "
Cycles:
o1
Encoding:
1 01
Operation:
ANL
(direct) -
001 0
direct address
(direct) 1\ (A)
6-34
"""".t".~,
.' .. I1"
...','...........
_.",,·t'.
intel .
ANL
ANL
MCS@-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
dlrect,#data
Bytes:
3
Cycles:
2
Encoding:
1
Operation:
ANL
(direct) -
Function:
Example:
ANL
0 0 1 1
direct address
immediate data
(direct) II #data
C,
Description:
ANL
0 1 0 1
Logical-AND for bit variables
If the Boolean value ofthe source bit is a logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash ("/") preceding the operand in the ass~bly language
indicates that the logical complement of the addressed bit is used as the source value, but the
source bit itself is not affected. No other flags are affected.
Only direct addressing is allowed for the source.operand.
Set the carry flag if, and only if, Pl.O = 1, ACC. 7 = 1, and OV
= 0:
MOV C,Pl.O
;LOAD CARRY WITH INPUT PIN STATE
ANL C,ACC.7
;AND CARRY WITH ACCUM. BIT 7
ANL C,/OV
;AND WITH INVERSE OF OVERFLOW FLAG
C,blt
Bytes:
2
Cycles:
2
Encoding:
11
Operation:
ANL
(C) -
000
001 0
bit address
(C) II (bit)
C,/blt
Bytes:
2
Cycles:
2
Encoding:
11 o 1
Operation:
ANL
(C) -
000 0
(C) II.,
bit address
(bit)
6-35
I.
int'el.,
CJNE
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
< dest-byte > , < src-byte > , rei
Function:
Description:
Compare and Jump if Not Equal.
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of < dest-byte > is less than the unsigned
integer value of ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.
Example:
The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CJNE
R7,#60H, NOT_EQ
R7 = 60H.
IFR7 < 6OH.
R7> 60H.
JC
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag,
this instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then the instruction,
WAIT:
CJNE A,PI,WAIT
clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from Pl. (If some other value was being input on PI, the program
wi1lIoop at this point until the PI data changes to 34H.)
CJNE
A,dlrect,rel
Bytes:
3
Cycles:
2
Encoding:
1<-1_0_1_1-->.._0_1_o_1-'
Operation:
(PC) +- (PC) + 3
IF (A) < > (direct)
THEN
(PC) +- (PC)
+
direct address
relative offset
IF (A) < (direct)
THEN
(C)+-I
ELSE
(C)+-O
6-36
reI. address
int:eL
CJNE
MCS®·51 PROGRAMMER'S GUIDE AND
IN~TRUCTION
SET
A, # data,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
I10
1 1
(PC) IF (A)
immediate data
0 1 0 0
+
(PC)
< > data
reI. address
3
THEN
(PC) + relative offset
(PC) IF (A) < data
THEN
(C)-l
ELSE
(C)-O
CJNE
Rn,#data,rel
Bytes:
3
Cycles:
2
Encoding:
I1 0 1 1
Operation:
(PC) - (PC) + 3
IF (Rn) < > data
1 r r r
THEN
(PC) IF (Rn)
(PC)
immediate data
+
reI. address
relative offset
< data
THEN
(C)-l
ELSE
(C)-O
CJNE
@Ri,#data,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
I10
1 1
(PC) IF
«Ri»
(PC)
+
3
< > data
THEN
(PC) IF
«Ri»
immediate data
0 1 1
(PC)
+
relative offset
< data
THEN
(C) - 1
ELSE
(C)-O
6-37
reI. address
int:et
CLR
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A
Function:
Description:
Example:
Clear Accumulator
The Accumulator is cleared (all bits set on zero). No flags are affected.
The Accumulator contains 5CH (0101 1lOOB). The instruction,
CLR A
will leave the Accumulator set to OOR (OOOOOOOOB).
Bytes:
Cycles:
Encoding:
Operation:
I1
1 0
0 1 0 0
CLR
(A)-O
CLR
bit
Function:
Description:
Example:
Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the
carry flag or any directly addressable bit.
Port 1 has previously been written with 5DH (0101 1101B). The instruction,
CLR P1.2
will leave the port set to 59H (OlOllOOlB).
CLR
C
Bytes:
Cycles:
Encoding:
Operation:
I1
0 0
0 0 1 1
CLR
(q-o
CLR
bit
Bytes:
2
Cycles:
Encoding:
Operation:
I1
1 0 0
CLR
(bit) -
0 0 1 0
bit address
0
6-38
int'et
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CPL A
Function:
Description:
Example:
Complement Accumulator
Each bit of the Accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to a zero and vice-versa. No flags are affected.
The Accumulator contains SCH (OlOlllOOB). The instruction,
CPL A
will leave the Accumulator set to OA3H (lOlOOOllB).
Bytes:
Cycles:
Encoding:
I1
Operation:
CPL
1 1
(A)~""
CPL
0 1 0 0
(A)
bit
Function:
Description:
Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero and
vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:
Port 1 has previously been written with SBH (OlOl1lOlB). The instruction sequence,
CPL Pl.l
CPL P1.2
will leave the port set to SBH (0101 101 lB).
CPL
C
Bytes:
Cycles:
Encoding:
1L--1_0_1_-,--0_0_1_,_1oJ
Operation:
CPL
(C)~...,(C)
6-39
MCS$-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
CPL bit
Bytes:
2
Cycles:
Encoding:
L-1_1_0_1_..L.-0_O_1_O-,
Operation:
CPL
(bit) +- .., (bit)
bit address
DA A
Function:
Description:
De,cimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC
instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxxlOl0-xxxxllll), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This
internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (lOlOxxxx-lllxxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the,
decimal conversion by adding OOH, 06H, 6OH, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction.
6-40
inlet
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Example:
The Accumulator holds the value 56H (01010110B) representing the packed BCD digits of the
decimal number 56. Register 3 contains the value 67H (0lIOOI1IB) representing the packed
BCD digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDC
DA
A,R3
A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OOIOOI00B), indicating the packed BCD digits of the decimal number 24, the low-order two
digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal
Adjust instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and 1 is
124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD
A,#99H
DA
A
will leave the carry set and 29H in the Accumulator, since 30
byte of the sum can be interpreted to mean 30 - 1 = 29.
Bytes:
Cycles:
Encoding:
Operation:
I1
0 1
0 1 0 0
DA
-contents of Accumulator are BCD
IF
[[(A3-0) > 9] V [(AC) = III
THEN(A3-O) ~ (A3-0) + 6
AND
IF
[[(A7-4) > 9] V [(C) = III
THEN (A7-4) ~ (A7-4) + 6
6-41
+
99 = 129. The low-order
intel .
DEC
MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
byte
Function:
Description:
Decrement
The variable indicated is decremented by 1. An original value of OOH will underflow to OFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or reg!ster-indirect.
Note: When this instruction is used to modify an output port, the value use , < rel·addr >
Function:
Description:
Decrement and Jump if No.t Zero.
DJNZ decrements the Io.catio.n indicated by I, and branches to. the address indicated by the
seco.nd o.perand if the resulting value is no.t zero. An o.rigi~al value o.f OOH will underflo.w to.
OFFH. No. flags are affected. The branch destinatio.n wo.uld be co.mputed by adding the signed
relative-displacement value in the last instructio.n byte to. the PC, after incrementing the PC to.
the first byte o.f the fo.llo.wing instructio.n.
The Io.catio.n decremented may be a register o.r directly addressed byte.
Note:. When this instructio.n is used to. mo.dify an o.utput po.rt, the value used as the o.riginal
po.rt data will be read fro.m the o.utput data latch, not the input pins.
Example:
Internal RAM Io.catio.ns 40H, SOH, and 60H co.ntain the values OIH, 70H, and ISH, respectively. The instructio.n sequence,
DJNZ 40H,LABEL_I
DJNZ 50H,LABEL_2
DJNZ 60H,LABEL_3
will cause a jump to. the instructio.n at labei LABEL_2 with the values OOH, 6FH, and ISH in
the three RAM Io.catio.ns. The first jump was not taken because the result was zero..
This instructio.n pro.vides a simple way o.f executing a pro.gram Io.o.p a given number o.f times,
o.r fo.r adding a mo.derate time delay (from 2 to. 512 machine cycles) with a singleinstructio.n.
The instructio.n sequence,
TOGGLE:
MOV
CPL
DJNZ
R2,#8
PI.7
R2,TOGGLE
will to.ggle PI. 7 eight times, causing fo.ur o.utput pulses to. appear at bit 7 o.f o.utput Po.rt 1.
Each pulse will last three machine cycles; two. fo.r DJNZ and o.ne to. alter the pin.
DjNZ
Rn,rel
Bytes:
2
Cycles:
2
Encoding:
LI_1_1_0_1-,-_1_r_r_r-.J
Operation:
DJNZ
(PC) - (PC) + 2
(Rn) - (Rn) - I
IF (Rn) > 0 o.r (Rn) < 0
THEN
(PC) - (PC)
reI. address
+
rei
6-44
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
DJNZ
dlrect,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
INC
I1 1 0 1
0 1 0 1
direct address
reI. address
DJNZ
(PC) ..- (PC) + 2
(direct) ..- (direct). - 1
IF (direct) > 0 or (direct) < 0
THEN
(PC) ..- (PC) + reI
Function:
Description:
Increment
INC increments the indicated variable by 1. An original value of OFFH will overflow to COH.
No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
Register 0 contains 7EH (OlIIIIIIOB). Internal RAM locations 7EH and 7FH contain OFFH
and 4OH, respectively. The instruction sequence,
INC @RO
INC RO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) COH and 41H.
INC
A
Bytes:
Cycles:
Encoding:
Operation:
I0 0 0 0 I 0 1 0 0
INC
(A)"- (A)
+
I
6-45
intel~
INC
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Rn
Bytes:
Cycles:
Encoding:
Operation:
INC
I 000 0 I 1 r r r
INC
(Rn) +- (Rn)
+
1
direct
Bytes:
2
Cycles:
Encoding:
Operation:
INC
I 000 0 I o 1 0 1
INC
(direct) +- (direct)
direct address
+
@Ri
, Bytes:
Cycles:
Encoding:
Operation:
INC
I 0000 I o 1 1
INC
«Ri» +- «Ri»
+
1
DPTR
Function:
Description:
Increment Data Pointer
Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an
overflow of the low-order byte of the data pointer (DPL) from OFFH to DOH will increment
the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Example:
Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and OIH.
Bytes:
Cycles:
Encoding:
Operation:
2
I10
1 0
0 0 1 1
INC
(DPTR) +- (DPTR)
+
1
6-46
infel .
JB
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
blt,rel
Function:
Jump if Bit set
Description:
If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example:
The data present at input port 1 is I 10010 lOB. The Accumulator holds 56 (010101 lOB). The
instruction sequence,
JB
P1.2,LABELl
JB
ACC.2,LABEL2
will cause program execution to branch to the instruction at label LABEL2.
Bytes:
3
Cycles:
2
Encoding:
Operation:
I0 0 1 0
JB
(PC)
bit address
0 0 0 0
(PC) + 3
= I
THEN
(PC) ~ (PC)
rei. address
~
IF (bit)
JBC
+
rel
blt,rel
Function:
Description:
Jump if Bit is set and Clear bit
If the indicated bit is one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third ·instruction byte to the PC, after
incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value u.sed as the original data
will be read from the output data latch, not the input pin.
Example:
The Accumulator holds 56H (OIOlOllOB). The instruction sequence,
JBC
JBC
ACC.3,LABELl
ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (OIOIOOIOB).
6-47
intel..
MCSI8l·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Bytes:
3
Cycles:
2
Encoding:
Operation:
I0 0 0 1
bit address
0 00 0
JBC
(PC) - (PC) + 3
IF (bit) = 1
THEN
(bit) (PC) -
0
(PC)
+
rei. address
reI
JC rei
Function:
Description:
Example:
Jump if Carry is set
If the carry flag is set, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.
The carry flag is cleared. The instruction sequence,
JC
CPL
JC
LABELl
C
LABEL 2
will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes:
2
Cycles:
2
Encoding:
Operation:
I0 1 0 0
reI. address
0 0 0 0
JC
(PC) - (PC) + 2
IF (C) = 1
THEN
(PC) -
(PC)
+
reI
6-48
intel"
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
JMP @A+DPTR
Function:
Jump indirect
Description:
Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and
load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order
eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data
Pointer is altered. No flags are affected.
Example:
Ari even number from 0 to 6 is in the Accumulator. The following sequence of instructions will
branch to one of four AJMP instructions in a jump table starting at JMP_TBL:
MOV
JMP
AJMP
AJMP
AJMP
AJMP
DPTR, #JMP_TBL
@A+DPTR
LABELO
LABELl
LABEL2
LABEL3
If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at
every other address.
Bytes:
Cycles:
2
Encoding:
1...._o__
1_1--'-_o_o_1_1.....
Operation:
JMP
(PC) ...- (A) + (DPTR)
6-49
infel .
JNB
MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
blt,rel
Function:
Jump if Bit Not set
Description:
If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC,. after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example:
The data present at input port I is llOOlOlOB. The Accumulator holds 56H (010101 lOB). The
instruction sequence,
JNB PU,LABELl
JNB ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.
Bytes:
3
Cycles:
2
Encoding:
Operation:
.
JNC
I0 0 1 1
0 0 0 0
JNB
(PC) -- (PC) + 3
IF (bit) = 0
THEN (PC) -- (PC)
bit address
+
reI. address
reI.
rei
Function:
Description:
Jump if Carry not set
If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative~displacement in
the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The carry flag is not modified.
Example:
The carry flag is set. The instruction sequence,
JNC LABELl
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by
the label LABEL2.
Bytes:
2
Cycles:
2
Encoding:
Operation:
I0 1 0 1
rei. address
0 0 0 0
JNC
(PC) -- (PC) + 2IF (C) = 0
THEN (PC) -- (PC)
+
rei
6-50
int:et
JNZ
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
rei
Function:
Description:
Jump if Accumulator Not Zero
If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example:
The Accumulator originally holds OOH. The instruction sequence,
JNZ LABELl
INC A
JNZ LABEL2
will set the Accumulator to OIH and continue at label LABEL2.
Bytes:
2
Cycles:
2
Encoding:
Operation:
_0__
1_1--1._0_ 0_0_ 0 ....J
1...1
JNZ
(PC) -- (PC) + 2
IF
(A) =1=
THEN (PC) -- (PC)
°
JZ
reI. address
+
rei
rei
Function:
Description:
Example:
Jump if Accumulator Zero
If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
The Accumulator originally contains OIH. The instruction sequence,
JZ LABELl
DEC A
JZ
LABEL2
will change the Accumulator to OOH and cause program execution to continue at the instruction identified by the label LABEL2.
Bytes:
2
Cycles:
2
Encoding:
1 0 1 1
Operation:
. JZ
° °°
0
0
(PC) -- (PC) + 2
IF
(A) =
THEN (PC) -- (PC)
°
reI. address
+
rei
6-51
infel .
LCALL
MCS@·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
addr16
Function:
Long call
Description:
LCALL calls a subroutine located at the indicated address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first), incrementing the Stack Pointer by two.. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of
the LCALL instruction. Program execution continues with the instruction at this address. The
subroutine may therefore begin anywhere in the full 64K-byte program memory address space.
No flags are affected.
Example:
Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory
location 1234H. After executing the instruction,
LCALI. SUBRTN
at location 0123H, the Stack Pointer will contain 09H, internal RAM locations OSH and 09H
will contain 26H and OlH, and the PC will contain 1234H.
Bytes:
3
Cycles:
2
Encoding:
100010010
Operation:
LCALL
(PC) - (PC) + 3
(SP) - (SP) + 1
«SP» -(PC7-O)
(SP) - (SP) + 1
«SP» - (PCIS.g)
(PC) - addrlS.O
LJMP
addr15-addrS
addr7-addrQ
I.·
addr16
Function:
Long Jump
Description:
UMP causes an unconditional branch to the indicated address, by loacling the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address- space. No
flags are affected.
Example:
The label "JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
UMP JMPADR
at location 0l23H will load the program counter with 1234H.
Bytes:
3
Cycles:
2
Encoding:
1000010010
Operation:
UMP
(PC) -
addr15-addrS
addrls-O
6-52
addr7-addrO
int:et
MOV
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
,
Functlon:
Description:
Move byte variable
The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.
Example:
Internal RAM location 30H holds 40H. The value of RAM location 40H is lOH. The data
present at input port 1" is llOOIOlOB (OCAH).
MOV
MOV
MOV
MOV
MOV
MOV
RO,#30H ;RO <= 30H
A,@RO
;A <= 40H
RI,A
;Rl <= 40H
B,@RI
;B <= IOH
@Rl,PI
;RAM (40H) < = OCAH
P2,PI
;P2 #OCAH
leaves the value 30H in register 0, 40H in both the Accumulator and register I, IOH in register
B, arid OCAH (1IOOIOlOB) both in RAM location 40H and output on port 2.
MOV A,Rn
Bytes:
Cycles:
Encoding:
11 1 1 0
Operation:
MOV
(A) -
1 r r r
(Rn)
·MOV A,dlrect
Bytes:
2
Cycles:
Encoding:
11 1 1 0
Operation:
MOV
(A) -
o1
0 1
direct address
(direct)
MOV A,ACC Is not a valid Instruction.
6-53
intel .
MOV
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
MOV
I1 1 10
o1
MOV
(A) +- «Ri»
A, # data
Bytes:
2
Cycles:
MOV
Encoding:
1 1
1 01
Operation:
MOV
(A) +- #data
o1
0 0
.immediate data
Rn,A
Bytes:
Cycles:
Encoding:
Operation:
MOV
1 r r r
MOV
(Rn) +- (A)
Rn,direct
Bytes:
2
Cycles:
2
Encoding:
Operation:
MOV
I1 1 1 1
I 1 010
1 r r r
direct ·addr.
MOV
(Rn) +- (direct)
Rn, # data
Bytes:
2
Cycles:
Encoding:
1 1
1 01
Operation:
MOV
(Rn) +- #data
1 r r r
immediate data
6-54
intel..
MOV
MCS®-51 PROGRAMMER'S GUIDE.AND INSTRUCTION SET
direct,A
Bytes:
2
Cycles:
Encoding:
Operation:
MOV
2
Cycles:
2
direct address
I 1 000
1 r r r
direct address
MOV
(direct) +- (Rn)
dlrect,dlrect '
Bytes:
3
Cycles:
2
Encoding:
Operation:
MOV
1
MOV
(direct) +- (A)
Bytes:
Operation: .
MOV
o1 0
dlrect,Rn
Encoding:
MOV
I 1 111
I 1 000
o10
1
dir. addr. (src)
dir. addr. (dest)
MOV
(direct) +- (direct)
dlrect,@RI
Bytes:
2
Cycles:
2
o1
Encoding:
11 000
Operation:
MOV
(direct) +- «Ri»
direct addr.
direct, # data
Bytes:
3
Cycles:
2
1 1
o1 0
Encoding:
1 01
Operation:
MOV
(direct) +- #data
1
direct address
6-55
immediate data
infel .
MCS@-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOY @RI,A
Bytes:
Cycles:
Encoding:
Operation:
I1 1 1
011
MOY
«Ri» +- (A)
MOY @RI,dlrect
Bytes:
2
Cycles:
2
Encoding:
Operation:
I 1 010
011
direct addr.
MOY
«Ri» +- (direct)
MOY @RI,#data
Bytes:
2
Cycles:
Encoding:
Operation:
MOY
I0 1
011
immediate data
MOY
«RI» +- #data
< dest-blt > , < src-blt >
Function:
Move bit data
Description:
The ~oolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.
Example:
The carry flag is originally set. The data present at input Port 3 is llOOOlOlB. The data
previously written to output Port I is 35H (OOIIOIOIB).
MOY p1.3,e
MOY e,P3.3
MOY p1.2,e
will leave the carry cleared and change Port I to 39H (OOIIIOOIB).
6·56
inteL
MOV
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
C,bit
Bytes:
2
Cycles:
Encoding:
Operation:
I 1 010
001 0
bit address
001 0
bit address
MOV
(C) -- (bit)
MOV
bit,C
Bytes:
2
Cycles:
2
Encoding:
Operation:
MOV
I 1 001
MOV
(bit) -- (C)
DPTR,#data16
Function:
Description:
Load Data Pointer with a 16-bit constant
The Data Pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded
into the second imd third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This
Example:
lS the only instruction which moves
16 bits of data at once.
The instruction,
MOV
DPTR, # 1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
Bytes:
3
Cycles:
2
Encoding:
Operation:
I1001
0 0 0 0
immed. data15-8
MOV
(DPTR) -- #data15-O
DPH 0 DPL -- #data15_8 0 #data7_0
6-57
immed. data7-0
int'eL
MOVC
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,@A+
Function:
Move Code byte
Description:
The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.
Example:
A value between and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
°
REL_PC:
INC
A
MOVC A,@A+PC
RET
DB
66H
DB
77H
DB
88H
DB
99H
If the subroutine is called with the Accumulator equaf to OlH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC
A,@A+DPTR
Bytes:
Cycles:
2
Encoding:
1L..-1_O_O_1--,-_O_O_1_1-'
Operation:
MOVC
(A) +- «A) + (DPTR»
MOVC
A,@A +'PC
Bytes:
Cycles:
Encoding:
Operation:
2
I 1 ° ° °° 1 1
(j
MOVC
'(PC) +- (PC) + 1
(A) +- «A) + (PC»
6-58
infel~
MOVX
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
, < src-byte >
Function:
Description:
Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data
memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or Rl in the current register bank provide an eight-bit
address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the loworder eight bits (DPL) with data. The P2 Special Function Register retains its previous contents while the P2 output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer. or with code to
output high-order address bits to P2 followed by a MOVX instruction using RO or Rl.
Example:
An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port O. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H.
Location 34H of the external RAM holds the value 56H. The instruction sequence,
MOVX A,@Rl
MOVX
@RO,A
copies the value 56H into both the Accumulator and external RAM location 12H.
6-59
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
MOVX
A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
MOVX
2
I1 1 1 0
001
MOVX
(A) +- «Ri»
A,@DPTR
Bytes:
Cycles:
Encoding:
Operation:
MOVX
2
I1 1 1 0
o0 0 0
MOVX
(A) +- «DPTR»
@Ri,A
Bytes:
Cycles:
Encoding:
Operation:
MOVX
2
I1 1 1 1
001
MOVX
«Ri» +- (A)
@DPTR,A
Bytes:
Cycles:
Encoding:
Operation:
2
I1 1 1 1
0000
MOVX
(DPTR) +- (A)
6-60
intet
MUL
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
AB
Function:
Multiply
Description:
MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte in
B. If the product is greater than 255 (OFFH) the overflow flag is set; otherwise it is cleared.
The carry flag is always cleared.
Example:
Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH).
The instruction,
MUL
AB
will give the product 12,800 (3200H), so B is changed to 32H (OOll00IOB) and the Accumulator is cleared. The overflow flag is set, carry is cleared.
Bytes:
Cycles:
Encoding:
Operation:
4
I1 0 1 0
0 1 0 0
MUL
(Ah-o -- (A) X (B)
(B)15-8
NOP
Function:
No Operation
Description:
Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.
Example:
It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must
be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence,
CLR
NOP
NOP
NOP
NOP
SETB
P2.7
P2.7
Bytes:
Cycles:
Encoding:
Operation:
I0 0 0 0 I0 0 0 0
NOP
(PC) -- (PC) + I
6-61
infel .
ORL
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Function:
Description:
Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
'
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
If the Accumulator holds OC3H (1 100001 IB) and RO holds 55H (OlOlOlOlB) then the instruction,
ORL A,RO
will leave the Accumulator holding the value OD7H (110101 11 B).
When the destination is a directly addressed byte, the instruction can set combinations of bits
in any RAM location or hardware register. The pattern orbits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable computed
. in the Accumulator at run-time. The instruction,
ORL Pl,#OOl1OOlOB
will set bits 5, 4, and 1 of output Port 1.
ORL A,Rn
Bytes:
Cycles:
Encoding:
Operation:
I0
0 0
.1 r r r
ORL
(A) ~ (A) V (Rn)
6-62
intel.,
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
ORL A,dlrect
Bytes:
2
Cycles:
Encoding:
Operation:
1
01
o0
o1
0 1
direct address
ORL
(A) ~ (A) V (direct)
ORL A,@RI
Bytes:
Cycles:
Encoding:
Operation:
1
01 00
o1
1 i
ORL
(A) ~ (A) V «Ri»
ORL A, # data
Bytes:
2
Cycles:
Encoding:
Operation:
1
01 00
o1
0 0
immediate data
ORL
(A) ~ (A) V #data
ORL dlrect,A
Bytes:
2
Cycles:
Encoding:
Operation:
1
01
o0
ORL
(direct)
~
001 0
direct address
(direct) V (A)
ORL direct, # data
Bytes:
3
Cycles:
2
Encoding:
Operation:
1
01
o0
ORL
(direct)
~
o0
1 1
direct addr.
(direct) V #data
6-63
immediate data
intel .
ORL
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
C,
Logical-OR for bit variables
Function:
Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state
otherwise. A slash ("/") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Description:
Set the carry flag if and only if P1.0 = I, ACC. 7 = I, or OV = 0:
Example:
MOV C,P1.0
;LOAD CARRY WITH INPUT PIN PIO
ORL e,AeC.7
;OR CARRY WITH THE ACe. BIT 7
ORL C,/OV
;OR CARRY WITH THE INVERSE OF OV.
ORL C,blt
Bytes:
2
Cycles:
2
Encoding:
001 0
1 1
1 01
Operation:
ORL
(C) -
(e)
v
bit address
(bit)
ORL C,/blt
Bytes:
2
Cycles:
2
I 1 010
Encoding:
o0
0 0
bit address
ORL
Operation:
I
(C) _
(C) V (bit)
6-64
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
POP
direct
Function:
Pop from stack.
Description:
The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.
Example:
The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OIH, respectively. The instruction sequence,
POP
DPH
POP
DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP
SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).
Bytes:
2
Cycles:
2
Encoding:
Operation:
PUSH
_1__0_1-,-_0_0_0_0-,
L..I
direct address
POP
(direct) +- «SP»
(SP) +- (SP) - I
direct
Function:
Push onto stack
Description:
The Stack Pointer is incremented by one. The contents of the indicated variable is then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.
Example:
On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instruction sequence,
PUSH
DPL
PUSH
DPH
will leave the Stack Pointer set to OBH and store 23H and OIH in internal RAM locations
OAH and OBH, respectively.
Bytes:
2
Cycles:
2
Encoding:
Operation:
1 1 1 0 0
°° °
0
direct address
PUSH
(SP) +- (SP) + I
«SP» +- (direct)
6-65
infel .
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RET
Function:
Return from subroutine
Description:
RET pops the high- and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.
Example:
. The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH
contain the values 23H and OlH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.
Bytes:
Cycles:
2
Encoding:
10010
Operation:
RET
(PCls-S) +- «SP»
(!)P) +- (SP) - 1
(PC7'() +- «SP»
(SP) +- (SP) - 1
0010
RETI
Function:
Return from interrupt
Description:
RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
.
interrupt is processed.
Example:
The Stack Pointer originally contains the value OBH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAH andOBH contain the
values 23H and OlH, respectively. The instruction,
RETI
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
Bytes:
Cycles:
2
Encoding:
1...1_0_0_1_-,--0_0_1_0-,
Operation:
RETI
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7'() +- «SP»
(SP) +- (SP) - 1
6-66
intel .
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RL A
Function:
Description:
Example:
Rotate Accumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
The Accumulator holds the value OC5H (1IooolOIB). The instruction.
RL A
leaves the Accumulator holding the value 8BH (looo1011B) with the carry unaffected.
Bytes:
Cycles:
Encoding:
1 0 0 1 0
Operation:
RL
(An + 1) - (An) n = 0 - 6
(AO) - (A7)
0 0 1 1
RLC A
Function:
Rotate Accumulator Left through the Carry flag
Description:
The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No
other flags are affected.
Example:
The Accumulator holds the value OC5H (11ooolOIB). and the carry is zero. The instruction.
RLC A
leaves the Accumulator holding the value 8BH (IOOO101OB) with the carry set.
Bytes:
Cycles:
Encoding:
....
1 _0_0_1_-,--0_0_1_1-,
Operation:
RLC
(An + 1) - (An) n = 0 - 6
(AO) -(C)
(C) -(A7)
6-67
intel .
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
RR A
Function:
Description:
Example:
Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
The Accumulator holds the value OCSH (1IOOOIOIB). The instruction,
RR A
leaves the Accumulator holding the value OE2H (I 11000 1OB) with the carry unaffected.
Bytes:
Cycles:
Encoding:
Operation:
I0 0 0 0 I0 0 1 1
RR
(An) - (An + I) n = 0 - 6
(A7)- (AO)
RRC A
Function:
Description:
Example:
Rotate Accumulator Right through Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position. No other flags are affected.
.
The Accumulator holds the value OCSH (1IOOOlOIB), the carry is zero. The instruction,
RRC A
leaves the Accumulator holding the value 62 (OIIOOOIOB) with the carry set.
Bytes:
Cycles:
Encoding:
Operation:
I0 0 0 1
RRC
(An) - (An
(A7) - (C)
(C)-(AO)
0 0 1 1
+
I) n = 0 - 6
6-68
intel;.
SETB
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
Function:
Set Bit
Description:
SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected.
Example:
The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The
instructions,
SETB C
SETB Pl.O
will leave the carry flag set to 1 and change the data output on Port 1 to 35H (00110101B).
SETB C
Bytes:
Cycles:
Encoding:
Operation:
I1 1 0 1
001 1
SETB
(C)-1
SETB bit
Bytes:
2
Cycles:
Encoding:
Operation:
I1 1 0 1
001 0
bit address
SETB
(bit) - 1
6-69
infel ...
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SJMP rei
Function:
Short Jump
Description:
Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC. after
incrementing the PC twice. Therefore. the range of destinations allowed is from 128 bytes
preceding this instruction to 127 bytes following it.
Example:
The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction.
SJMP RELADR
will assemble into location 0100H. After the instruction is executed. the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore.
the displacement byte of the instruction will be the relative offset (0123H-0102H) = 21H. Put
another way. an SIMP with a displacement ofOFEH would be a one-instruction infinite loop.)
Bytes:
2
Cycles:
2
Encoding:
11000
Operation:
SIMP
(PC) +- (PC)
(PC) +- (PC)
0000
reI. address
+. 2
+ reI
6-70
int:et
SUBB
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,
Function:
Description:
Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed
for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.
Example:
The Accumulator holds OC9H (1IOOIOOlB), register 2 holds 54H (OlOlOlOOB), and the carry
flag is set. The instruction,
SUBB A,R2
will leave the value 74H (OlllOIOOB) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or mUltiple-precision subtraction, it should be explicitly cleared by a
CLR C instruction.
SUBB
A,Rn
Bytes:
Cycles:
Encoding:
Operation:
1 r r r
SUBB
(A) +- (A) - (C) - (Rn)
6-71
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
SUBB
A,direct
Bytes:
2
Cycles:
Encoding:
Operation:
I100
1
0 1 0 1
direct address
SUBB
(A) +- (A) - (C) - (direct)
A,@RI
SUBB
Bytes:
Cycles:
Encoding:
I1 0 0 1
Operation:
SUBB
0 1 1
(A) +- (A) - (C) -
SUBB
«Ri»
A,#data
Bytes:
2
Cycles:
Encoding:
Operation:
SWAP
I1 0 0 1
0 1 0 0
immediate data
SUBB
(A) +- (A) - (C) - #data
A
Function:
Description:
Example:
Swap nibbles within the Accumulator
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No
flags are affected.
The Accumulator holds the value OC5H (ll000lOlB). The instruction,
SWAP A
leaves the Accumulator holding the vahle 5CH (01011100B).
Bytes:
Cycles:
Encoding:
Operation:
I1 1 0 0
0 1 0 0
SWAP
(A3-a) ~ (A7-4)
6-72
intel~
XCH
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,
Function:
Exchange Accumulator with byte variable
Description:
XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct, or register-indirect addressing.
Example:
RO contains the address 20H. The Accumulator holds the value 3FH (OOllllllB). Internal
RAM location 20H holds the value 75H (01 I 10 101 B). The instruction,
XCH
A,@RO
will leave RAM location 20H holding the values 3FH (OOllllllB) and 75H (01 110 10 lB) in
the accumulator.
XCH
A,Rn
Bytes:
Cycles:
Encoding:
Operation:
XCH
I1
o0
1 r r r
XCH
(A) ~ (Rn)
A,direct
Bytes:
2
Cycles:
Encoding:
Operation:
XCH
I 1 100
o1 o1
direct address
XCH
(A) ~ (direct)
A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
I 1 100
011
XCH
(A) ~ «Ri»
6-73
intel..
XCHD
MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
A,@RI
Function:
Exchange Digit
Description:
XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags
are affected.
Example:
RO contains the address 20H. The Accumulator holds the value 36H (001 101 lOB). Internal
RAM location 20H holds the value 75H(01l101OIB). The instruction,
XCHD
A,@RO
will leave RAM location 20H holding the value 76H (OlllOllOB) and 35H (OOllOlOIB) in the
Accumulator.
Bytes:
Cycles:
Encoding:
Operation:
XRL
_1_1_o_1--,-_o_1_1--,
LI
XCHD
(A3.0) ~
«Ri3.0»
,
Function:
Description:
Logical Exclusive-OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can, be the Accumulator or immediate data.
(Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example:
If the Accumulator holds OC3H (1IOOOOIIB) and register 0 holds OAAH (10 10 10 lOB) then
the instruction,
XRL
A,RO
will leave the Accumulator holding the value 69H (OllOIOOIB).
When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a
variable computed in the Accumulator at run-time. The instruction,
XRL
PI,#OOllOOOIB
will complement bits 5, 4, and 0 of output Port I.
6-74
MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XRL A;Rn
Bytes:
Cycles:
Encoding:
Operation:
1
01 1 0
1 r r r
XRL
(A) +- (A) ¥ (Rn)
XRL A,direct
Bytes:
2
Cycles:
Encoding:
Operation:
1
01 1 0
o1 0
1
direct address
XRL
(A) +- (A) ¥ (direct)
XRL A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
1
01 1 0
o1 1 i
XRL
(A) +- (A) ¥ «Ri»
XRL A, # data
Bytes:
2
Cycles:
Encoding:
Operation:
1
01 1 0
o1 0 0
immediate data
XRL
(A) +- (A) ¥ #data
XRL direct,A
Bytes:
2
Cycles:
Encoding:
Operation:
1
01 1 0
001 0
direct address
XRL
(direct) +- (direct) ¥ (A)
6-75
intel"
MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET
XRL direct, # data
Bytes:
3
Cycles:
2
Encoding:
Operation:
I0 1 1 0
0 0 1 1
direct address
XRL
(direct) +- (direct) ¥ # data
6-76
immediate data
MCS® . . 51 Hardware
Descriptions and Data Sheets
7
infel·
October 1991
8051,8052 and 80C51
Hardware Description
Order Number: 270252-005
7-1
8051, 8052 and 80C51 Hardware Description
CONTENTS
CONTENTS
PAGE
INTERRUPTS .. .........................
Priority Level Structure ............... : ..
How Interrupts Are Handled .............
External Interrupts .......................
Response Time .........................
INTRODUCTION ......................... 7-3
Special Function Registers ............... 7-3
PORT STRUCTURES AND
OPERATION ...........................
1/0 Configurations ........................
Writing to a Port ..........................
Port Loading and Interfacing ..............
Read-Modify-Write F~ature ...............
PAGE
7-6
7-7
7-7
7-23
7-24
7-24
7-25
7-25
SINGLE-STEP OPERATION ............ 7-26
7-8
RESET .................................. 7-26
7-9
ACCESSING EXTERNAL MEMORy ..... 7-9
POWER-ON RESET .................... 7-27
TIMER/COUNTERS ..................... 7-9
Timer 0 and Timer 1 ..................... 7-10
Timer 2 ................................. 7-12
POWER-SAVING MODES OF
OPERATION ......................... 7-27
CHMOS Power Reduction Modes ........ 7-27
SERIAL INTERFACE ...................
Multiprocessor Communications .........
Serial Port Control Register ..............
Baud Rates ........ ; ....................
More About Mode 0 .....................
More About Mode 1 .....................
More About Modes 2 and 3 ..............
EPROM VERSiONS .....................
Exposure to Light ........................
Program Memory Locks .................
ONCE Mode .... ·........................
7-13
7-14
7-14
7-29
7-29
7-29
7-30
7-15
7-17
THE ON-CHIP OSCILLATORS . ......... 7-30
HMOS Versions ......................... 7-30
7-20
CHMOS Versions ....................... 7-32
7-17
INTERNAL TIMING . .................... 7-33
7-2
8051, 8052 AND 80C51
HARDWARE DESCRIPTION
• The EPROM versions of the 8051AH, 8052AH and
80C51BH
INTRODUCTION
This chapter presents a comprehensive description of
the on-chip hardware features of the MCS®-51 microcontrollers. Included in this description are
• The port drivers and how they function both as
ports and, for Ports 0 and 2, in bus operations
The devices under consideration are listed in Table 1.
As it becomes unwieldy to be constantly referring to
each of these devices by their individual names, we will
adopt a convention of referring to them generically as
8051s and 8052s, unless a specific member of the group
is being referred to, in which case it will be specifically
named. The "805Is" include the 8051AH, 80C51BH,
and their ROMless and EPROM versions. The "8052s"
are the 8052AH, 8032AH and 8752BH.
• The Timer/Counters
• The Serial Interface
• The Interrupt System
• Reset
• The Reduced Power Modes in the CHMOS devices
Figure I shows a functional block diagram of the 8051s
and 8052s.
Table 1. The MCS-51 Family of Microcontrollers
Device
Name
ROMless
Version
EPROM
Version
ROM
Bytes
RAM
Bytes
16-bit
Timers
Ckt
Type
8051AH
8052AH
80C51 BH
8031AH
8032AH
80C31BH
8751 H, 8751 BH
8752BH
87C51
4K
8K
4K
128
256
128
2
3
2
HMOS
HMOS
CHMOS
Special Function Registers
A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2. SFRs marked
by parentheses are resident in the 8052s but not in the 8051s.
7-3
int'et
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
PO.O-PO.7
r--------~~~
P2.0-P2.7
~~~----------.--,
~
P-l
-= I
I
I
I
I
I
I
I
I
I
1 "'-::>L-..,
I~=
I
1
I
1
1,--_,..--,
PSEN
ALE
EA
I
RST
I
I
I
I
I
I
_'==r.:c:r-:a:::::r.i... _ _ _ _ _ _ .J
9R .. ldenl in 8052/8032 only.
P3.0-P3.7
Pl.0-Pl.7
270252-1
Figure 1. MCS-S1 Architectural Block Diagram
7-4
intel~
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
8 Bytes
F8
FO
FF
B
F7
EF
E8
EO
ACC
E7
DF
D8
DO
C8
PSW
(T2CON)
D7
(RCAP2L)
(RCAP2H)
(TL2)
(TH2)
CF
CO
B8
BO
A8
AO
98
90
88
80
C7
IP
P3
IE
P2
SCON
P1
TCON
PO
BF
B7
AF
A7
9F
SBUF
97
TMOD
SP
TLO
DPL
TL1
DPH
THO
TH1
PCON
8F
87
Figure 2. SFR Map. ( ... ) Indicates Resident in 8052s, not in 8051s
Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.
to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent S-bit registers.
User software should not write Is to these unimplemented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be 1.
PO, PI, P2 and P3 are the SFR latches of Ports 0, I, 2
and 3, respectively.
PORTS 0 TO 3
SERIAL DATA BUFFER
ACC isthe Accumulator register. The mnemonics for
Accumulator-Specific instructions, however, refer to
the Accumulator simply as A.
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Moving
a byte to SBUF is what initiates the transmission.)
When data is moved from SBUF, it comes from the
receive buffer.
B REGISTER
TIMER REGISTERS
The functions of the SFRs are outlined below.
ACCUMULATOR
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.
. Register pairs (THO, TLO), (THI, TLI), and (TH2,
TL2) are the 16-bit Counting registers for Timer/Counters 0, I, and 2, respectively.
PROGRAM STATUS WORD
CAPTURE REGISTERS
The PSW register contains program status information
as detailed in Figure 3.
The register pair (RCAP2H, RCAP2L) are the Capture registers for the Timer 2 "Capture Mode." In this
mode, in response to a transition at the S052's T2EX
pin, TH2 and TL2 are copied into RCAP2H and
RCAP2L. Timer 2 also has a 16-bit auto-reload mode,
and RCAP2H and RCAP2L hold the reload value for
this mode. More about Timer 2's features in a later
section.
STACK POINTER
The Stack Pointer Register is S bits wide. It is incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in onchip RAM, the Stack Pointer is initialized to 07H after
a reset. This causes the stack to begin at location OSH.
CONTROL REGISTERS
DATA POINTER
Special Function Registers IP, IE, TMOD, TCON,
T2CON, SCON, and PCON contain control and status
bits for the interrupt system, the Timer/Counters, and
the serial port. They are described in later sections.
The Data Pointer (DPTR) consists of a high byte
(DPH) and a low byte (DPL). Its intended function is
7-5
int'eL
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
(MSB)
(LSB)
CY
Symbol
Position
CY
AC
PSW.7
PSW.6
FO
PSW.5
RSI
RSO
PSW.4
PSW.3
AC
FO
RSI
RSO
Name and Significance
Carry flag.
Auxiliary Carry flag.
(For BCD operations.)
Flag 0
(Available to the user for general
purposes.)
Register bank select control bits I &
O. Set/cleared by software to
determine working register bank (see
Note).
ov
P
SymbOl
Position
OV
PSW.2
PSW.I
PSW.O
P
Name and Significance
Overflow flag.
User definable flag.
Panty flag.
Sell cieared by hardware each
instruction cycle to indicate.an oddl
even number of "one" bits in the
Accumulator, i.e., even panty.
NOTE:
The contents of (ASI, RSO) enable the working register banks as
follows:
(00H-07H)
(O.O)-Bank 0
(OBH-OFH)
(O.I)-Bank I
(IOH-17H)
(I.O)-Bank 2
(I.I)-Bank 3
(IBH-IFH)
Figure 3. PSW: Program Status Word Register
READ
.LATCH
ADDR/DATA
VCC
INT. B:,;U:,;S'--t--I
WRITE
TO
LATCH
INT. B",",U:::S'--+-I
WRITE
TO
LATCH
READ
PIN
READ
PIN
270252-3
270252-2
B. Port 1 Bit
A. Port 0 Bit
ALTERNATE
OUTPUT
FUNCTION
ADDR
READ
LATCH
READ
LATCH
INT. BUS
INT. BUS
WRITE
TO
LATCH
WRITE
TO
LATCH
READ
PIN
READ
PIN
270252-4
ALTERNATE
INPUT
FUNCTION
270252-5
C. Port 2 Bit
D. Port 3 Bit
Figure 4. 8051 Port Bit Latches and 1/0 Buffers
'See Figure 5 for details of the internal pullup.
external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is 16
bits wide. Otherwise the Port 2 pins continue to emit
the P2 SFR content.
PORT STRUCTURES AND
OPERATION
All four ports in the 8051 are bidirectional. Each consists of a latch (Special Function Registers PO through
P3), an output driver, and an input buffer.
All the Port 3 pins, and (in the 8052) two Port 1 pins
are multifunctional. They are not only port pins, but
also serve the functions of various special features as
listed on the following page.
The output drivers of Ports 0 and 2, and thejnput buffers of Port 0, are used in accesses to external memory.
In. this application, Port 0 outputs the low byte of the
7-6
infel .
HARDWARE DESCRIPTION OF,THE 8051, 8052 AND 80C51
Port Pin
Alternate Function
·P1.0
T2 (Timer/Counter 2
external input)
T2EX (Timer/Counter 2
Capture/Reload trigger)
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt)
INT1 (external interrupt)
TO (Timer/Counter 0 external
input)
T1 (Timer/Counter 1 external
input)
WR (external Data Memory
write strobe)
RD (external Data Memory
read strobe)
·P1.1
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
ADDR/DATA BUS). To be used as an input, the port
bit latch must contain a 1, which turns off the output
driver FET. Then, for Ports I, 2, and 3, the pin is
pulled high by the internal pullup, but can be pulled
low by an external source.
Port 0 differs in not having internal pull ups. The pullup
FET in the PO output driver (see Figure 4) is used only
when the Port is emitting Is during external memory
accesses. Otherwise the pullup FET is off. Consequently PO lines that are being used as output port lines are
open drain. Writing a 1 to the bit latch leaves both
output FETs off, so the pin floats. In that condition it
can be used a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pullups
they are sometimes called "quasi-bidirectional" ports.
When configured as inputs they pull high and will
source current (IlL, in the data sheets) when externally
pulled low. Port 0, on the other hand, is considered
"true" bidirectional, because when configured as an input it floats.
·PI.O and PI.I serve these alternate functions only on
the 8052.
The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin is stuck at O.
All the port latches in the 8051 have Is written to them
by the reset function. If a 0 is subsequently written to a
port latch, it can be reconfigured as an'input by writing
a I to it.
I/O Configurations
Writing to a Port
Figure 4 shows a functional diagram of a typical bit
latch and I/O buffer in each of the four ports. The bit
latch (one bit in the port's SFR) is represented as a
Type D flip-flop, which will clock in a value from the
internal bus in response to a "write to latch" signal
from the CPU. The Q output of the flip-flop is placed
on the internal bus in response to a "read latch" signal
from the CPU. The level of the port pin itself is placed
on the internal bus in response to a "read pin" signal
from the CPU. Some instructions that read a port activate the "read latch" signal, and others activate the
"read pin" signal. More about that later.
In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch
during S6P2 of the final cycle of the instruction. However, port latches are in fact sampled by their output
buffers only during Phase 1 of any clock period. (During Phase 2 the output buffer holds the value it saw
during the previous Phase I). Consequently, the new
value in the port latch won't actually appear at the
output pin until the next Phase 1, which will be at SIPl
of the next machine cycle. See Figure 39 in the Internal
Timing section.
'
As shown in Figure 4, the output drivers of Ports 0 and
2 are switchable to an internal ADDR and ADDR/
DATA bus by an internal CONTROL signal for use in
external memory accesses. During external memory accesses, the P2 SFR remains unchanged, but the PO SFR
gets Is written to it.
If the change requires a O-to-I transition in Port 1, 2, or
3, an additional pullup is turned on during SIPI and
SIP2 of the cycle in which the transition occurs. This is
done to increase the transition speed. The extra pullup
can source about 100 times the current that the normal
pullup can. It should be noted that the internal pull ups
are field-effect transistors, not linear resistors. The pullup arrangements are shown in Figure 5.
Also shown in Figure 4, is that if a P3 bit latch contains
a I, then the output level is controlled by the signal
labeled "alternate output function." The actual P3.x
pin level is always available to the pin's alternate input
function, if any.
In HMOS versions of the 8051, the fixed part of the
pullup is a depletion-mode transistor with the gate
wired to the source. This transistor will allow the pin to
source about 0.25 mA when shorted to ground. In
parallel with the fixed pullup is an enhancement-mode
transistor, which is activated during SI whenever the
port bit does a O-to-l transition. During this interval, if
the port pin is shorted to ground, this extra transistor
will aIlow the pin to source an additional 30 mAo
Ports 1, 2, and 3 have internal pullups. Port 0 has open
drain Qutputs. Each I/O line can be independently used
as an input or an output. (Ports 0 and 2 may not be
used as genera,l purpose I/O when being used as the
7-7
intel..
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
VCC
2 OSC. PERIOOS
00
ENHANCEMENT MODE FET
~
270252-6
A. HMOS Configuration. The enhancement mode transistor
is turned on for 2 osc. periods after Q makes a O-to-1 transition.
Vcc
Vcc
Vcc
a
FROM PORT
LATCH
READ
PORT PIN
270252-7
B. CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q
makes a O-to-1 transition. During this time, pFET :I also turns on pFET 3
through the inverter to form a latch which holds the 1. pFET 2 Is also on.
Figure 5. Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations.
Port 2 is Similar Except That It Holds The Strong Pullup On While Emitting
1s That Are Address Bits. (See Text, "Accessing External Memory".)
In the CHMOS versions, the pullup consists of three
pFETs. It should be noted that an n-channel FET
(nFET) is turned on when a logical 1 is applied to its
gate, and is turned off when a logical 0 is applied to its
gate. A p-channel FET (pFET) is the opposite: it is on
when its gate sees a 0, and off when its gate sees a 1.
Port Loading and Interfacing
The output buffers of Ports 1, 2, and 3 can each drive 4
LS TTL inputs. These ports on HMOS versions can be
driven in a normal manner by any TTL or NMOS circuit. Both HMOS and CHMOS pins can be driven by
open-collector and open-drain outputs, but note that 0to-l transitions will not be fast. In the HMOS device, if
the pin is driven by an open-collector output, a O-to-l
transition will have to be driven by the relatively weak
depletion mode FET in Figure 5(A). In the CHMOS
device, an input 0 turns off pullup pFET3, leaving only
the very weak pullup pFET2 to drive the transition.
pFETl in Figure 5 is the transistor that is turned on for
2 oscillator periods after a O-to-l transition in the port
latch. While it's on, it turns' on pFET3 (a weak pullup), through the inverter. This inverter and pFET form
a latch which hold the 1.
Note that if the pin is emitting a 1, a negative glitch on
the pin from some external source can turn off pFET3,
causing the pin to go into a float state. pFET2 is a very
weak pullup which is on whenever the nFET is off, in
traditional CMOS style. It's only about '1'0 the strength
of pFET3. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.
In external bus mode, Port 0 output buffers can each
drive 8 LS TTL inputs. As port pins, they require external pullups to drive any inputs.
7-8
int'eL
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. Note that the Port 2
drivers use the strong pullups during the entire time
that they are emitting address bits that are Is. This is
during the execution of a MOVX @DPTR instruction.
During this time the Port 2 latch (the Special Function
Register) does not have to contain Is, and the contents
of the Port 2 SFR are not modified. If the external
memory cycle is not immediately followed by another
external memory cycle, the undisturbed contents of the
Port 2 SFR will reappear in the next cycle.
Read-Modify-Write Feature
Some instructions that read a port read the latch and
others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modifycwrite" instructions. The instructions listed below are read-modify-write instructions. When the destination operand is
a port, or a port bit, these instructions read the latch
rather than the pin:
ANL
(logical AND, e.g., ANL PI, A)
ORL
(logical OR, e.g., ORL P2, A)
XRL
(logical EX-OR, e.g., XRL P3, A)
JBC
Gump if bit = I and clear bit, e.g.,
JBC Pl.1, LABEL)
CPL
(complement bit, e.g., CPL P3.0)
INC
(increment, e.g., INC P2)
DEC
(decrement, e.g., DEC P2)
DJNZ
(decrement and jump if not zero, e.g.,
DJNZ P3, LABEL)
MOV, PX.Y, C (move carry bit to bit Y of Port X)
CLR PX.Y
(clear bit Y of Port X)
SETB PX.Y
(set bit Y of Port X)
If an 8-bit address is being used (MOVX @Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facilitate paging.
In any case, the low byte of the address is time-multiplexed with the data byte on Port O. The ADDR/
DATA signal drives both FETs in the Port 0 output
buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do not require external pullups. Signal ALE (Address Latch Enable) should be
used to capture the address byte into an external latch.
The address byte is valid at the negative transition of
ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is activated, and remains there until after WR is deactivated. In a read
cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated.
It is not obvious that the last three instructions in this
list are read-modify-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.
During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0
SFR may have been holding. If the user writes to Port 0
during an external memory fetch, the incoming code
byte is corrupted. Therefore, do not write to Port 0 if
external program memory is used.
The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid
possible misinterpretation of the voltage level at the
pin. For example, a port bit might be used to drive the
base of a transistor. When a 1 is 'written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
correct value of 1.
a
External Program Memory is accessed under two conditions:
1) Whenever signal EA is active; or
2) Whenever the program counter (PC) contains a
number that is larger than OFFFH (IFFFH for the
8052).
ACCESSING EXTERNAL MEMORY
This requires that the ROMless versions have EA wired
low to enable the lower 4K (8K. for the 8032) program
bytes to be fetched from external memory.
Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Mem~ccesses to external Program Memory
use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use RD or
WR (alternate functions ofP3.7 and P3.6) to strobe the
memory. Refer to Figures 36 through 38 in the Internal
Timing section.
When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for general purpose I/O.
During external program fetches they output the high
byte of the PC. During this time the Port 2 drivers use
the strong pullups to emit PC bits that are Is.
Fetches from external Program Memory always use a
16-bit address. Accesses 'to external Data Memory can
use either a 16-bit address (MOVX @DPTR) or an
8-bit address (MOVX @Ri).
TIMER/COUNTERS
The 8051 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. The 8052 has these two plus one
7-9
intel·
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
more: Timer 2. All three can be configured to operate
either as timers or event counters.
four operating modes, which are selected by bit-pairs
(MI, ;MO) in TMOD. Modes 0, I, and 2 are the same
for both Timer/Counters. Mode 3 is different. The four
operating modes are described in the following text.
In the "Timer" function, the register is incremented
every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is '112 of the oscillator
frequenby.
MODE 0
Either Timer in Mode 0 is an 8-bit Counter with a
divide-by-32 prescaIer. This 13-bit timer is MCS-48
compatible. Figure 7 shows the Mode 0 operation as it
applies to Timer 1.
In the "Counter" function, the register is incremented
in response to a I-to-O transition at its corresponding
external input pin, TO, Tl or (in the 8052) T2. In this
function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register
during S3PI of the cycle following the one in which the
transition was detected. Since it takes 2 machine cycles
(24 oscillator periods) to recognize a I-to-O transition,
the maximum count rate is '1.4 of the oscillator frequency. There are no restrictions on the duty cycle of
the external input signal, but to ensure that a given
level is sampled at least once before it changes, it
should be held for at least one full machine cycle.
In this mode, the Timer register is configured as a
13-Bit register. As the count rolls over from allis to all
Os, it sets the Timer interrupt flag TFI. The counted
input is enabled to the Timer when TRI = I and either
GATE = 0 or INTI = 1. (Setting GATE = I allows
the Timer to be controlled by external input INTI, to
facilitate pulse width measurements.) TRI is a control
bit in the Special Function Register TCON (Figure 8).
GATE is in TMOD.
The 13-Bit register consists of all 8 bits ofTHI and the
lower 5 bits of TLI. The upper 3 bits of TLI are indeterminate and should be ignored. Setting the run flag
(TR I) does not clear the registers.
In addition to' the "Timer" or "Counter" selection,
Timer 0 and Timer I have four operating modes from
which to select. Timer 2, in the 8052, has three modes
of operation: "Capture," "Auto-Reload" and "baud
rate generator."
Mode 0 operation is the same for Timer 0 as for Timer
1. Substitute TRO, TFO arid INTO for the corresponding Timer I signals in Figure 7. There are two different
GATE bits, one for Timer I (TMOD.7) and one for
Timer 0 (TMOD.3).
Timer 0 and Timer 1
These Timer/Counters are present in both the 8051 and
the 8052. The "Timer" or "Counter" function is selected by control bits CIT in the Special Function Register
TMOD (Figure 6). These two Timer/Counters have
l
(MSB)
GATE
CIT
Ml
MO
MODE 1
Mode I is the same as Mode 0, except that the Timer
register is, being run with all 16 bits.
1
(LSB)
GATE
CiT
MO
)
T
Timer 1
GATE
clf
Timer 0
Gating control when set. Timer/Counter "x" is enabled
only while "IiiIIx" pin is high end "TRx" control pin is
set. When cleared Timer "x" is enabled whenever
"TRx" control bit is.set.
M1
MO
o
o
o
Timer or Counter Selector cleared for Timer operation
(input from internal system clock). Set for Counter
operation (input frdm "Tx" input pin).
Operating Mode
B·blt Timer/Counter "THx" with "TLx" as S-bit
prescaler.
lS·blt Timer/Counter "THx" and "TLx" are
cascaded; there is no prescaler.
o
B-M auto-reload TimerfCounter "THx" holds a
value which is to be reloaded into "TLx" each
time It overflows.
(Timer 0) TlO is an B-bit Timer/Counter
controlled by the standard Timer 0 control bits.
THO is an B-bit timer only controlled by Timer 1
control bits.
(Timer 1) TimerfCounter 1 stopped.
Figure 6. TMOO: TImer/Counter Mode Control Register
7-10
infel .
, HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
CiT =0
T1 PIN
______~1
INTERRUPT
CIT =I
CONTROL
-
270252-9
Figure 7. Timer/Counter 1 Mode 0: 13-Bit Counter
(LSB)
(MSB)
TFI
TRI
TFO
TRO
lEI
1T1
lEO
ITO
Symbol
Position
Name and Significance
Symbol
Position
Name and Significance
TFI
TCON.7
Timer I overflow Flag. Set by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
lEI
TCON.3
Interrupt I Edge flag. Set by hardware
when ext,ernal interrupt edge
detected. Cleared when interrupt
processed.
TRI
TCON.S
Timer I Run control bit. Set!cleared
by software to turn Timer/Counter on/
off.
ITI
TCON.2
TFO
TCON.5
Timer 0 overflow Flag. Set by
. hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Interrupt I Type control bit. Set!
cleared by software to specify falling
edge/low level triggered external
interrupts.
lEO
TCON.I
Interrupt 0 Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.
ITO
TCON.O
Interrupt 0 Type control bit Set!
cleared by software to specify falling
edge/low level triggered external
interrupts.
TRO
TCONA
Timer 0 Run control bit. Set! cleared
by software to turn Timer/Counter on/
off.
Figure a.TCON: Timer/Counter Control Register
Timer 0 in Mode 3 establishes TLO and THO as two
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 10. TLO uses the Timer 0 control bits:
clf, GATE, TRO, INTO, and TFO. THO is locked into
a timer function (counting machine cycles) and takes
over the use ofTRl and TFI from Timer 1. Thus, THO
now controls the "Timer 1" interrupt.
MODE 2
Mode 2 configures the Timer register as an 8-bit Counter (TLl) with automatic reload, as shown in Figure 9.
Overflow from TLI not only sets TFl, but also reloads
TLI with the contents of THl, which is preset by software. The reload leaves THI unchanged.
Mode 3 is provided for applications requiring an extra
8-bit timer or counter. With Timer 0 in Mode 3, an
8051 can look like it has three Timer/Counters, and an
8052, like it has four. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of
and into its own Mode 3, or can still be used by the
serial port as a baud rate generator, or in fact, in any
application not requiring an interrupt.
Mode 2 operation is the same for Timer/Counter O.
MODE 3
Timer 1 in Mode 3 simply holds its count. The effect is
the same as setting TRI = O.
7-11
intel .
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
INTERRUPT
270252-10
Figure 9. Timer/Counter 1 Mode 2: a-Bit Auto-Reload
I,
osc
b-B-
1112105C
1I12.105C - - - - - - ,
t---
INTERRUPT
TO P I N - - - ' - - - - - - '
CONTROL -
TRO-----t
GATE
1I12105C
----------+I-·-o11
.
_(8_~_O_) H T~
______T
..
-to..
...
r--
INTERRUPT
CONTROL
TRl
-
270252-11
Figure 10. Timer/Counter 0 Mode 3: Two a-Bit Counters
Timer 2
Table 2. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052, Like Timers 0 and I, it can operate
either as a timer or as an event counter, This is selected
by bit C/T2 in the Special Function Register T2CON
(Figure 11), It has thfee operating modes: "capture,"
"auto-load" and, ''baud rate generator, n, which are selected by bits in T2CON as shown in Table 2,
RCLK
+ TCLK CP/RL2 TR2
0
0
1
X
7-12
0
1
X
X
1
1
1
0
Mode
16-bit Auto-Reload
16-bit Capture
Baud Rate Generator
(off)
intal..
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
(LSB)
(MSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
Position
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when either RCLK = 1 or TCLK = 1.
Name and Significance
EXF2
T2CON.6
Timer 2 eldernal flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1
will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software.
RCLK
T2CON.5
Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflow
to be used for the receive clock.
TCLK
T2CONA
Transmit clock flag. When set: causes the serial port to use Timer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit clock.
EXEN2
T2CON.3
Timer 2 eldernal enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on T2EX if Timer 2 is not being used to clock the
serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic 1 starts the timer.
C/f2
T2CON.l
Timer or counter select. (Timer 2)
= Internal timer (OSC/12)
1 = Eldernal event counter (falling edge triggered).
o
CP/RL2
T2CON.O
Capture/Reload flag. When set, captures will occur on negative transitions at
T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK
= 1 or TCLK = 1, this bit is ignored and the timer is forced to auto·reload on
Timer 2 overflow.
Figure 11. T2CON: Timer/Counter 2 Control Register
added feature that a I-to-O transition at external input
T2EX will also trigger the 16-bit reload and set EXF2.
In the Capture Mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0,
then Timer 2 is a 16-bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit,
which can be used to generate an interrupt. If EXEN2
= 1, then Timer 2 still does the above, but with the
added feature that a I-to-O transition at external input
T2EX causes the current value in the Timer 2 registers,
TL2 and TR2, to be captured into registers RCAP2L
and RCAP2R, respectively. (RCAP2L and RCAP2H
are new Special Function Registers in the 8052.) In
addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2, like TF2, can generate an
interrupt.
The auto-reload mode is illustrated in Figure 13.
The baud rate generator mode is selected by RCLK =
1 and/or TCLK = 1. It will be described in conjunction with the serial port.
SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit
and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from
the receive register. (However, if the first byte still
hasn't been read by the time reception of the second
byte is complete, one of the bytes will be lost). The
serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to
SBUF loads the transmit register, and reading SBUF
accesses a physically separate receive register.
The Capture Mode is illustrated in Figure 12.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, then when Timer 2 rolls over it not only
sets TF2 but also causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L
and RCAP2H, which are preset by software. IfEXEN2
= 1, then Timer 2 still does the above, but with the
7-13
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
nMER2
INTERRUPT
EXEN2
270252-12
Figure 12. Timer 2 in Capture Mode
The serial port can operate in 4 modes:
Multiprocessor Communications
Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at
1/12 the oscillator frequency.
Modes 2 and 3 have a special provision for mUltiprocessor communications. In these modes, 9 data bits are
received. The 9th one goes into RB8. Then comes a
stop bit. The port can be programmed such that when
the stop bit is received, the serial port interrupt will be
activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in
multiprocessor systems is as follows.
Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (I). On receive, the stop bit goes
into RB8 in Special Function Register SCON. The
baud rate is variable.
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2 = I, no
slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each
slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit
and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their
SM2s set and go on about their business, ignoring the
coming data bytes.
Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (1).
On Transmit, the 9th data bit (TB8 in SCON) can be
assigned the value of 0 or 1. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Functon
Register SCON, while the stop bit is ignored. The baud
rate is programmable to either '132 or 'I•• the oscillator
frequency.
Mode 3: II bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In
fact, Mode 3 is the same as Mode 2 in all respects
except the baud rate. The baud rate in Mode 3 is variable.
SM2 has no effect in Mode 0, and in Mode 1 can be
used to check the validity of the stop bit. In a Mode 1
reception, if SM2 = 1, the receive interrupt will not be
activated unless a valid stop bit is received.
Serial Port Control Register
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other
modes by the incoming start bit if REN = 1.
The serial port control and status register is the Special
Function Register SCON, shown in Figure 14. This
register contains not only the mode selection bits, but
also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).
7-14
int:eL
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER 2
INTERRUPT
EXEN2
270252-13
Figure 13. Timer 21n Auto-Reload Mode
(MSB)
SMO
(LSB)
SMI
SM2
REN
Where SMO, SMI specify the serial port mode, as follows:
SMO
0
0
SM1
0
0
Mode
0
1
2
3
•
•
SM2
REN
Description
shift register
8·bitUART
9·bitUART
Baud Rate
fose/ 12
variable
fose/64
or
fose/32
9·bit UART variable
enables the multiprocessor
communication feature in Modes 2
and 3. In Mode 2 or 3, if SM2 is set to
1 then RI will not be activated if the
received 9th data bit (RB8) is O. In
Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not
received. In Mode 0, SM2 should be
O.
TB8
RB8
TI
RI
•
TB8
is the 9th data bit that will be
transmitted in Modes 2 and 3. Set or
clear by software as desired.
•
RB8
in Modes 2 and 3, is the 9th data bit
that was received. In Mode 1, if SM2
= 0, RB8 is the stop bit that was
received. In Mode 0, RB8 is not used.
•
TI
is transmit interrupt flag. Set by
hardware at the end of the 8th bit time
in Mode 0, or at the beginning of the
stop bit in the other modes, in any
serial transmission. Must be cleared
by software.
•
RI
is receive interrupt flag. Set by
hardware at the end of the 8th bit time
in Mode 0, or halfway through the stop
bit time in the other modes, in any
serial reception (except see SM2).
Must be cleared by software.
enables serial reception. Set by
software to enable reception. Clear
by software to disable reception.
Figure 14. SCON: Serial Port Control Register
Baud Rates
The baud rate in Mode 0 is fixed:
Mode 2 Baud
Oscillator Frequency
Mode 0 Baud Rate = -------''--~
12
2 SMOD
Rate=~X(Oscillator
Frequency)
In the 8051, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. In the 8052, these
baud rates can be determined by Timer 1, or by Timer
2, or by both (one for transmit and the other for receive).
The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register peON. If SMOD
= 0 (which is the value on reset), the baud rate '/64 the
oscillator frequency. If SMOD = 1, the baud rate is
'132 the oscillator frequency.
7-15
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Using Timer 1 to Generate Baud Rates
mode (high nibble of TMOD = DO lOB). In that case,
the baud rate is given by the formula
When Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by the
Timer 1 overflow rate and the value of SMOD as follows:
Modes 1, 3 2SMOD Oscillator Frequency
Baud Rate = - - - X ----::-----''---:32
12x [256 - (THI)l
One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a 16-bit timer (high nibble of
TMOD = OOOIB), and using the Timer 1 interrupt to
do a 16-bit software reload.
Modes 1, 3 2SMOD
Baud Rate =
X (Timer 1 Overflow Rate)
----n-
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3
running modes. In the most typical applications, it is
configured for "timer" operation, in the auto-reload
Figure 15 lists various commonly used baud rates and
how they can be obtained from Timer 1.
Timer 1
Baud Rate
Mode 0 Max: 1 MHZ
Mode 2 Max: 375K
Modes 1, 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110
fose
SMOD
12MHZ
12MHZ
12MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.986 MHZ
6MHZ
12MHZ
X
1
1
1
0
0
0
0
0
0
0
cif
Mode.
X
X
0
0
0
0
0
0
0
0
'0
X
X
2
2
2
2
2
2
2
2
1
Reload
Value
X
X
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
Figure 15. Timer 1 Generated Commonly Used Baud Rates
11). Note then the baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode,
as shown in Figure 16.
Using Timer 2 to Generate Baud Rates
In the 8052, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Figure
neA 1
OVERFLOW
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12.
12P1H--_--'
RXCLOCK
TXCLOCK
"nIlER 2"
TUX PIN
INTERRUPT
EXEN!
L
NOTE AVAILABILITY OF ADDmONAL EXTERNAL
I~AAUPT
Figure 16. Timer 2 in Baud Rate Generator Mode
7-16
270252-14
int:et
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
The baud rate generator mode is similar to the auto-reload mode, in that a roIlover in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a 1 into the 9th position of the
transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such
that one full machine cycle will elapse between "write
to SBUF," and activation of SEND.
Now, the baud rates in Modes 1 and 3 are determined
by Timer 2's overflow rate as follows:
SEND enables the output of the shift register to the
alternate output function line of P3.0, and also enables
SHIFT CLOCK to the alternate output function line of
P3.I. SHIFT CLOCK is low during S3, S4, and S5 of
every machine cycle, and high during S6, S1 and S2. At
S6P2 of every machine cycle in which SEND is active,
the contents of the transmit shift register are shifted to
the right one position.
Timer 2 Overflow Rate
Modes 1, 3 Baud Rate = - - - - - - - 16
The Timer can be configured for either "timer" or
"counter" operation. In the most typical applications, it
is configured for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's
being used as a baud rate generator. Normally, as a
timer it would increment every machine cycle (thus at
1/1. the oscillator frequency). As a baud rate generator,
however, it increments every state time (thus at Y. the
oscillator frequency). In that case the baud rate is given
by the formula
As data bits shift out to the right, zeroes come in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the
MSB, and all positions to the left of that contain zeroes.
This condition flags the TX Control block to do one
last shift and then deactivate SEND and set n. Both of
these actions occur at SIPl of the 10th machine cycle
after "write to SBUF."
Modes 1, 3
Oscillator Frequency
Baud Rate = --:-:--:---:----'--....:...-----:32x [65536 - (RCAP2H, RCAP2L)1
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Reception is initiated by the condition REN = 1 and
Rl = O. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
shift register, and in the next clock phase activates RECEIVE.
Timer 2 as a baud rate generator is shown in Figure 16.
This Figure is valid only if RCLK + TCLK = 1 in
T2CON. Note that a rollover in TH2 does not set TF2,
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2
is in the baud rate generator mode. Note too, that if
EXEN2 is set, a I-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
as a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.
RECEIVE enables SHIFT CLOCK to the alternate
output function line of P3.I. SHIFT CLOCK makes
transitions at 83Pl and S6Pl of every machine cycle.
At S6P2 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left one position. The value that comes in
from the right is the value that was sampled at the P3.0
pin at S5P2 of the same machine cycle.
As data bits come in from the right, Is shift out to the
left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift
register, it flags the RX Control block to do one last
shift and load SBUF. At SIPl of the 10th machine
cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.
It should be noted that when Timer 2 is running (TR2
= 1) in "timer" function in the baud tate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP registers may be read, but
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. Tum the
Timer off (clear TR2) before accessing the Timer 2 or
RCAP registers, in this case.
More Abou~ Mode 1
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit goes iato
RB8 in SCON. In the 8051 the baud rate is determined
by the Timer 1 overflow rate. In the 8052 it is determined either by the Timer 1 overflow rate, or the Timer
2 overflow rate, or both (one for transmit and the other
for receive).
More About Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8
data bits (LSB first). The .baud rate is fixed at Y1. the
oscillator frequency.
Figure 17 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing.
Figure 18 shows a simplified functional diagram of the
serial port in Mode 1, and associated timings for transmit receive.
7-17
intet
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
WRITE
SBUF
TO
----r~~~i:~~~~~----~~------r_~
RXD
P3.0 ALT
OUTPUT
FUNCTION
S6-r-----I
TXD
P3.1 ALT
OUTPUT
FUNCTION
REN
' - - - - t R X CLOCK
RX CONTROL
)-----oiSTART
Ri-""'--~
SHIFT
'----r-,-""T'".,.-,-,r-r""T......
r:~~~~~1--~----
RXD
P3.0ALT
INPUT
FUNCTION
REAO
SBUF
ALE
---I1 WRITE TO SBUF
SENDt:S8P2
I
SHIFT
TRANSMIT
RXD (DATA OUT) ,
TXD (SHIFT CLOCK)
TI
-.ll WRITE TO SCON(CLEAR RI)
L-R~~~~====j=====================================================~r----
~CEIVE
SHIFT
RECEIVE
RXD (DATA IN)------;D':''=--ll''~-_o=--_{J='-----{F'''---_{I''-'<---_{]I'"''--__lr'-----
TXD (SHIFT CLOCK)
270252-15
Figure 17. Serial Port Mod.e 0
7-18
inteL
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER2
OVERFLOW
TIMER 1
OVERFLOW
WRITE
__
---'---:==~~~~---:~~--~----r-~ -3~'
SBUF
TO
TXD
RXD
TRANSMIT
I
R;~LfX
RECEIVE
~16RESET
tJiTART
em
DO
D1
..
lilT DETECTOR SAMI'U TIMES
D3
.. .
De
01
SHIFT
____________________________________________________
~RI~
STOP BIT
~r----
270252-16
Figure 18. Serial Port Mode 1. TCLK, RCLK and Timer 2 are Present in the 8052/8032 Only.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads a I into the 9th bit position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission actually
commences at SIPI of the machine cycle following the
next rollover in the divide-by-16 counter. (Thus, the bit
times are synchronized to the divide-by-16 counter, not
to the "write to SBUF" signal).
The transmission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit of the
transmit shift register to TXD. The first shift pulse occurs one bit time after that.
7-19
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
As data bits shift out to the right, zeroes are clocked in
from the left. When the MSB of the data byte is at the
output position of the shift register, then the I that was
initially loaded into the 9th position is just to the left of
the MSB, and all· positions to the left of that contain
zeroes. This condition flags the TX Control unit to do
one last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after
"write to SBUF."
mit, the 9th data bit (TBS) can be assigned the value of
1. On receive, the 9th data bit goes into RBS in
SCON. The baud rate is programmable to either Ya. or
'/64 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer I
or 2 depending on the state of TCLK and RCLK.
o or
Figures 19 and 20 show a functional diagram of the
serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode 1. The transmit portion
differs from Mode I only in the 9th bit of the transmit
shift register.
Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
Transmission is initiated by any instruction that. uses
SBUF as a destination register. The "write to SBUF"
signal also loads TBS into the 9th bit position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission commences at SIPI of the machine cycle following the next
rollover in the divide-by-16 counter. (Thus, the bit
times are synchronized to the divide-by-16 counter, not
to the "write to SBUF" signal.)
The 16 states of the counter divide each bit time into
16ths. At the 7th, Sth, and 9th counter states of each bit
time, the bit detector samples the value of RXD. The
value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking for another I-to-O transition. This is to provide rejection of false start bits. If the start bit proves valid, it
is shifted into the input shift register, and reception of
the rest of the frame will proceed.
The transmission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit of the
transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a I
(the stop bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked in. Thus, as
data bits shift out to the right, zeroes are clocked in
from the left. When TBS is at the output position of the
shift register, then the stop bit is just to the left of TBS,
and all positions to the left of that contain zeroes. This
condition flags the TX Control unit to do one last shift
and then deactivate SEND and set TI. This occurs at
the II th divide-by-16 rollover after "write to SBUF."
As data bits come in from the right, Is shift 'out to the
left. When the start bit arrives at the leftmost position
in the shift register, (which in mode I is a 9-bit register), it flags the RX Control block to do one last shift,
load SBUF and RBS, and set RI. The signal to load
SBUF and RBS, and to set RI, will be generated if, and
only if, the following conditions are met at the time the
final shift pulse is generated.
1) RI = 0, and
2) Either 8M2 = 0, or the received stop bit
=
Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and I FFH is written to the input shift
register.
1
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met,
the stop bit goes into RBS, the S data bits go into
SBUF, and RI is activated. At this time, whether the
above conditions are met or not, the unit goes back to
looking for a I-to-O transition in RXD.
At the 7th, 8th and 9th counter states of each bit time,
the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit goes
back to looking for another I-to-O transition. If the
start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(through RXD): a start bit (0), S data bits (LSB first), a
programmable 9th data bit, and a stop bit (I). On trans-
7-20
intel~
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
WRITE
SBUF
TO
__
---lr----~~~~;r~--~~----~----r_~ ~~~
TXD
PHASE 2 CLOCK
('h tose)
MODE2
TI
SMOD= 1
SMOD=O
SERIAL
PORT
INTERRUPT
(SMOD IS PCON.7) '-....-----__-1
LOAD
SBUF
RXD
TRANSMIT
c::J!.iL:JSTOP
BIT
~--------------------------------------
________________~r---270252-17
Figure 19. Serial Port Mode 2
7-21
infel ~
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
TIMER 1
OVERFLOW
TIMER 2
OVERFLOW
WRITE
TO ;---r---===JFr~~:i~--~~----~----r-~
SBUF
TCLK -
____~~
TXD
TXCONTROL
TI
RI
LOAD
SBUF
SHIFT t------------,
RXD
TX
~LOC~~~!~=_~L---Jl----IL---~~--~L--~'L---JL---~L--~'----IL---
.....-J WRITE TO SBUF
- - - - , SEND
DATA L SlPl I
SHIFT
TRANSMIT
STOP BIT
RECEIVE
RXD BIT DETECTORI STA"T 81T ,
SAMPLE TIMES
SHIFT
____IL___~L___~IL-__~I____~l____~L____~L____~L____~L_____
______________
______________________________________________
1
~RI~
--Jr-----
~
270252-18
Figure 20. Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in the 8052/8032 Only.
7-22
intel"
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
As data bits come in from the right, Is shift out to the
left. When the start bit arrives at the leftmost position
in the shift register (which in Modes 2 and 3 is a 9-bit
register), it flags the RX Control block to do one last
shift, load SBUF and RB8, and set RI. The signal to
load SBUF and RB8, and to set RI, will be generated if,
and only if, the following conditions are met at the time
the final shift pulse is generated:
1) RI = 0, and
2) Either SM2 =
°
was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.
The Timer 0 and Timer I Interrupts are generated by
TFO and TFI, which are set by a rollover in their respective Timer/Counter registers (except see Timer 0 in
Mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
or the received 9th data bit = 1
The Serial Port Interrupt is generated by the logical OR
of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact,
the service routine will normally have to determine
whether it was RI or TI that generated the interrupt,
and the bit will have to be cleared in software.
If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes into
RB8, and the first 8 data bits go into SBUF. One bit
time later, whether the above conditions were met or
not, the unit goes back to looking for a I-to-O transition
at the RXD input.
In the 8052, the Timer 2 Interrupt is generated by the
logical OR ofTF2 and EXF2. Neither of these flags is
cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the
interrupt, and the bit will have to be cleared in software.
Note that the value of the received stop bit is irrelevant
to SBUF, RB8, or RI.
INTERRUPTS
The 8051 provides 5 interrupt sources. The 8052 provides 6. These are shown in Figure 21.
All of the bits that generate interrupts can be set or
cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be canceled
in software.
The External Interrupts INTO and INTI can each be
either level-activated or transition-activated, depending
on bits ITO and ITI in Register TCON. The flags that
actually generate these interrupts are bits lEO and IE!
in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when
the. service routine is vectored to only if the interrupt
(MSB)
(LSB)
1~1-1~1~lmlml~I~1
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
TFO--------.
INTERRUPT
SOURCES
~1--------~
Symbol
EA
Position
IE.7
Function
disables all interrupts. If EA = 0, no
interrupt will be acknowledged. If EA
= 1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
IE.S
reserved.
ET2
IE.5
Timer 2 interrupt enable bit.
ES
lEA
Serial Port interrupt enable bit.
ETI
IE.S
Timer 1 interrupt enable bit.
EXI
1E.2
External interrupt 1 enable bit.
ETO
IE.l
Timer 0 interrupt enable bit.
EXO
IE.O
External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, since
they may be used in future MCS-51 products.
Figure 22. IE: Interrupt Enable Register
~2~
EXF2~(e0520NLY)
-
270252-19
Figure 21. MCS®·51 Interrupt Sources
7-23
infel .
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 22). IE contains also a
global disable bit, EA, which disables all interrupts at
once.
ceived simultaneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence, as follows:
1.
2.
3.
4_
5_
6.
Note in Figure 22 that bit position IE.6 is unimplemented. In the 8051s, bit position IE.5 is also unimplemented. User software should not write Is to these bit
positions, since they may be used in future MCS-51
products.
Priority Level Structure
TF2
+ EXF2
Priority Within Level
(highest)
(lowest)
Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priori-
Each interrupt source can also be individually programmed to one of .two priority levels by setting or
clearing a bit in Special Function Register IP (Figure
23). A low-priority interrupt can itself be interrupted
by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source.
(MSB)
Source
lEO
TFO
IE1
TF1
RI +TI
ty level
The IP register contains a number of unimplemented
bits. IP.7 and IP.6 are vacant in the 8052s, and in the
8051s these and IP.5 are vacant. User software should
not write Is to these bit positions, since they may be
used in future MCS-51 products.
(LSB)
I-I-I~I~I~I~I~I~I
How Interrupts Are Handled
Priority bit = 1 assigns high priority.
Priority bit = 0 assigns low priority.
Figure 23. IP: Interrupt Priority Register
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. The 8052's TiIiler 2 interrupt cycle
is different, as described in the Response Time Section.
If one of the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it and the
interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated tCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in
the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to
the IE or IP registers.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are re-
Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be
Symbol
Position
IP.7
Function
reserved
IP.e
reserved
PT2
IP.5
Timer 2 interrupt priority bit.
PS
IP.4
Serial Port interrupt priority bit.
PT1
IP.3
Timer 1 interrupt priority bit.
PX1
IP.2
External interrupt 1 priority bit.
PTO
IP.l
Timer 0 interrupt priority bit.
PXO
IP.O
External interrupt 0 priority bit.
User software should never write 1s to unimplemented bits, since
they may be used in future MCS-51 products.
........ - - C l -....~I" ' - - C 2 - - ' "ofo----C3---'"....--C4--.~1....- - C S - -.... •
ISSP21
S&
........ ~\-,---'--~1'~----L.-~11'tl------l'-------
r.1
INTERRUPT
GOES
ACTIVE
INTERRUPT
LATCHED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPTS
ARE POLLED
INTERRUPT ROUTINE
270252-20
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
Figure 24. Interrupt Response Timing Diagram
7-24
intel~
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any access to IE or IP, then at least one more
instruction will be executed before any interrupt is vectored to.
External Interrupts
The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit
IT! or ITO in Register TCON. If ITx = 0, external
interrupt x is triggered by a detected low at the INTx
pin. If ITx = I, external interrupt x is edge-triggered.
In this mode if successive samples of the INTx pin
show a high in one cycle and a low in the next cycle,
interrupt request flag lEx in TCON is set. Flag bit lEx
then requests the interrupt.
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. Note then that if
an interrupt flag is active but not being responded to for
one of the above conditions, and is not still active when
the blocking condition is removed, the denied interrupt
will not be serviced. In other words, the fact that the
interrupt flag was once active but not serviced is not
remembered. Every polling cycle is new.
Since the external interrupt pins are sampled once each
machine .cycle, an input high or low should hold for at
least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
machine cycle, and then hold it low for at least one
machine. cycle to ensure that the transition is seen so
that interrupt request flag lEx will be set. lEx will be
automatically cleared by the CPU when the service
routine is called.
The polling cycle/LCALL sequence is illustrated in
Figure 24.
Note that if an interrupt of higher priority level goes
active prior to S5P2 of the machine cycle labeled C3 in
Figure 24, then in accordance with the above rules it
will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is
completed, or else another interrupt will be generated.
Thus the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases
it doesn't. It never clears the Serial Port or Timer 2
flags. This has to be done in the user's software. It
clears an external interrupt flag (lEO orIEl) only if it
was transition-activated. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectored to, as shown below.
Vector
Source
Address
lEO
0OO3H
TFO
OOOBH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
Response Time
The INTO and INTI levels are inverted and latched
into the interrupt flags lEO and lEI at S5P2 of every
machine cycle. Similarly, the Timer 2 flag EXF2 and
the Serial Port flags RI and TI are set at. S5P2. The
values are not actually polled by the circuitry until the
next machine cycle.
The Timer 0 and Timer I flags, TFO and TFl, are set at
SSP2 of the cycle in which the timers overflow. The
values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag TF2 is set at S2P2 and is
polled in the same cycle in which the timer overflows.
If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between
activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 24 shows interrupt response timings.
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no
longer in progress, then pops the top two bytes from the
stack and reloads the Program Counter. Execution of
the interrupted program continues from where it left
off.
A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If
an interrupt of equal or higher priority level is already
in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If
the instruction in progress is not in its final cycle, the
additional wait time cannot be more than 3 cycles, since
the longest instructions (MUL and DIV). are only 4
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking
an interrupt was still in progress.
7-25
inteL
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
cycles long, and if the instruction in progress is RETI
or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one more
cycle to complete the instruction in progress, plus 4
cycles to complete the next instruction if the instruction
is MUL or DIV).
RESET
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high
for at least two machine cycles (24 oscillator periods),
while. the oscillator is running. The CPU responds by
generating an internal reset, with the timing shown in
Figure 25.
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.
SINGLE-STEP OPERATION
The 8051 interrupt structure allows single-step execution with very little software overhead. As previously
noted, an interrupt request will not be responded to
while an interrupt of equal priority level is still in progress, nor will it be responded to after RETI until at
least one other instruction has 'been executed. Thus,'
once an interrupt routine has been entered, it cannot be
re-entered until at least one instruction of the interrupted program is executed. One way to use this feature for
single-stop operation is to program one of the external
interrupts (say, INTO) to be level-activated. The service
routine for the interrupt will terminate with the following code:
JNB P3.2,$ ;Wait Here Till INTO Goes High
JB
P3.2,$ ;Now Wait Here Till it Goes Low
:Go Back and Execute One Instruction
RETI
While the RST pin is high, ALE and PSEN are weakly
pulled high. After RST is pulled low, it will take 1 to 2
machine cycles for ALE and PSEN to start clocking.
For this reason, other devices can not be synchronized
to the internal timings of the 8051.
Driving the ALE and PSEN pins to 0 while reset is
active could cause the device to go into an indeterminate state.
The internal reset algorithm writes Os to all the SFRs
except the port latches, the Stack Pointer, and SBUF.
The port latches are initialized to FFH, the Stack
Pointer to 07H, and SBUF is indeterminate. Table 3
lists the SFRs and their reset values.
Now if the INTO pin, which is also the P3.2 pin, is held
normally low, the CPU will go right into the External
Interrupt 0 routine and stay there until INTO is pulsed
(from low to high to low). Then it will execute RET!,
go back to the task program, execute one instruction,
and immediately re-enter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the
task program is executed each time P3.2 is pulsed.
r-- 1
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2
of every machine cycle. The port pins will maintain
their current activities for 19 oscillator periods after a
logic 1 has been sampled at the RST pin; that is, for 19
to 31 oscillator periods after the external reset signal
has been applied to the RST pin.
The internal RAM is not affected by reset. On power
up the RAM content is indeterminate.
2 OSC. PERIODS------1
1 S5 1 S6 1 S1 1 S2 1 S3 1 S4 1 S5 1 S6 1 Sl 1 S2.1 S3 1 S4 1 S5 1 S6 1 Sl 1 S2 1 S3 1 S4 1
~n
11111111111
,
ALE:
C
'--'
'--'
SAMPLE RST
INTERNAL RESET SIGNAL
,
SAMPLE RST
1I...'r-.--.. .nL-_-'
PSEN:
po:
--~,--~~--~~--~~--~~--~~
- 1 1 osc. PERIODS -,- - - - - - - - 1 9 OSC. PERIODS - - - - - . , , ,
270252-33
Figure 25. Reset Timing
7-26
infel~
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Table 3. Reset Values of the SFRs
SFR Name
POWER-ON RESET
Reset Value
For HMOS devices when Vee is turned on an automatic reset can be obtained by connecting the RST pin to
Vee through a 10 J-I-F capacitor and to Vss through an
8.2 K!1 resistor (Figure 26). The CHMOS devices do
not require this resistor although its presence does no
harm. In fact, for CHMOS devices the external resistor
can be removed because they have an internal pulldown
on the RST pin. The capacitor value could then be reduced to 1 J-I-F.
OOOOH
OOH
PC
ACC
B
OOH
PSW
OOH
SP
DPTR
07H
OOOOH
PO-P3
FFH
IP (8051)
IP (8052)
XXXOOOOOB
IE (8051)
IE (8052)
OXXOOOOOB
OXOOOOOOB
When power is turned on, the circuit holds the RST pin
high for an amount of time that depends on the capacitor value and the rate at which it charges. To ensure a
valid reset the RST pin must be held high long enough
to allow the oscillator to start up plus two machine
cycles.
XXOOOOOOB
TMOD
OOH
TCON
OOH
OOH
THO
TLO
On power up, Vee should rise within approximately
ten milliseconds. The oscillator start-up time will depend on the oscillator frequency. For a 10 MHz crystal,
the start-up time is typically I ms. For a I MHz crystal,
the start-up time is typically 10 ms.
OOH
OOH
TH1
TL1
OOH
TH2 (8052)
TL2 (8052)
With the given circuit, reducing Vee quickly to 0 causes the RST pin voltage to momentarily fall below OV.
However, this voltage is internally limited and will not
harm the device.
OOH
OOH
OOH
RCAP2H (8052)
RCAP2L (8052)
OOH
SCON
NOTE:
The port pins will be in a random state until
the oscillator has started and the internal reset
algorithm has written Is to them.
OOH
Indeterminate
SBUF
PCON (HMOS)
OXXXXXXXB
OXXXOOOOB
PCON (CHMOS)
Powering lIP the device without a valid reset could
cause the CPU to start executing instructions from an
indeterminate location. This is because the SFRs, specifically the Program Counter, may not get properly
initialized.
vee
POWER-SAVING MODES OF
OPERATION
+
10"'=:=
vee I--
For applications where power consumption is critical
the CHMOS version provides power reduced modes of
operation as a standard feature. The power down mode
in HMOS devices is no longer a standard feature and is
being phased out.
8051
RST
8.2KIl
CHMOS Power Reduction Modes
VSS
CHMOS versions have two power-reducing modes,
Idle and Power Down. The input through which backup power is supplied during these operations is VCC.
Figure 27 shows the internal circuitry which implements these features. In the Idle mode (IDL = I), the
oscillator continues to run and the Interrupt, Serial
Port, and Timer blocks continue to be clocked, but the
=
270252-21
Figure 26. Power on Reset Circuit
7-27
intel .
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
clock signal is gated off to the CPU. In Power Down
(PD = I), the oscillator is frozen. The Idle and Power
Down modes are activated by setting bits in Special
Function Register PCON. The address of this register
is 87H. Figure 28 details its contents.
(MSB)
(LSB)
SMOO
GF1
PeON.7
Double Baud rate bit. When set to a 1
and Timer 1 is used to generate baud
rate, and the Serial Port is used in
modes 1, 2, or 3.
PCON.S
(Reserved)
PCON.5
(Reserved)
(Reserved)
GF1
PCON.3
. General·purpose flag bit.
GFO
PCON.2
General·purpose flag bit.
PO
PCON.1
Power Down bit. Setting this bit
activates power down operation.
IOL
PCON.O
Idle mode bit. Setting this bit activates
idle mode operation.
If Is are written to PO and IOL at the same time, PO takes
precedence. The reset value of PCON is (OXXXOOOO).
In the HMOS devices the PCON register only contains SMOO.
The other four bits are implemented only In the CHMOS devices.
.User software should never.write 1s to unimplemented bits, since
they may be used in future MCS-51 products.
The flag bits GFO and GFl can be used to give an
indication if an interrupt occurred during normal operation or during an Idle. For example, an instruction
that acti vates Idle can also set one or both flag bits.
When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
~
=
Name and Function'
PositIon
Figure 28. PCON: Power Control Register
There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PCON.O to be cleared
by hardware, terminating the Idle mode. The interrupt
will be serviced, and following RETI the next instruction to be executed will be the cine following the instruction that put the device into Idle.
XTAL 2
IOL
SMOO
PCON.4
An instruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions. The CPU status is preserved
in its entirety: the Stack Pointer, Program Counter,
Program Status Word, Accumulator, and all other reg-.
isters maintain their data during Idle. The port pins
hold the logical states they had at the time Idle was
activated. ALE and PSEN hold at logic high levels.
PO
Symbol
In the HMOS devices the PCON register only contains
SMOD. The other four bits are implemented only in
the CHMOS devices. User software should never write
Is to unimplemented bits, since they may be used in
future MCS-51 products.
IDLE MODE
GFO
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only
two machine cycles (24 oscillator periods) to complete
the reset.
XTAL 1
The signal at the RST pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes
program execution from where it left off; that is, at the
instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
cycles of program execution may take place before the
internal reset· algorithm takes control. On-chip hardware inhibits access to the internal RAM during this
time, but access to the port pins is not inhibited. To
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to
external Data RAM.
INTERRUPT,
I-_-C>:SERIAL PORT,
nMERBLDCKS
CPU
270252-22
Figure 27. Idle and Power Down Hardware
POWER DOWN MODE
An instruction that sets PCON.I causes that to be the
last instruction executed before going into the Power
Down mode. In the Power Down mode, the on-chip
oscillator is· stopped. With the clock frozen, all func-
7-28
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Table 4. EPROM Versions of the 8051 and 8052
Device
Name
EPROM
Version
EPROM
Bytes
Ckt
Type
VPP
Time Required to
Program Entire Array
8051AH
8751 H/8751 BH
4K
HMOS
21.0V/12.75V
4 minutes
80C51BH
87C51
4K
CHMOS
12.75V
13 seconds
8052AH
8752BH
8K
HMOS
12.75V
26 seconds
tions are stopped, but the on-chip RAM and Special
Function Registers are held. The port pins output the
values held by their I:espective SFRs. ALE and PSEN
output lows.
Program Memory Locks
In some microcontroller applications it is desirable that
the Program Memory be secure from software piracy.
Intel has responded to this need by implementing a
Program Memory locking scheme in some of the MCS51 devices. While it is impossible for anyone to guarantee absolute security against all levels of technological
sophistication, the Program Memory locks in the MCS51 devices will present a substantial barrier against illegal readout of protected software.
The only exit from Power Down for the 80C5l is a
hardware resel Reset redefmes all the SFRs, but does
not change the on-chip RAM.
In the Power Down mode of operation, VCC can be
reduced to as low as 2V. Care must be taken, however,
to ensure that VCC is not reduced before the Power
Down mode is invoked, and that VCC is restored to its
normal operating level, before the Power Down mode is
terminated. The reset that terminates Power Down also
frees the oscillator. The reset should not be activated
before VCC is restored to its normal operating level,
and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10
msec).
One Lock Bit Scheme on 8751H
The 8751H contains a lock bit which, once progrl!mmed, denies electrical access by any external
means to the on-chip Program Memory. The effect of
this lock bit is that while it is programmed the internal
Program Memory can not be.read out, the device can
not be further programmed, and it can not execute external Program Memory. Erasing the EPROM array
deactivates the lock bit and restores the device's full
functionality. It can then be re-programmed.
EPROM VERSIONS
The EPROM versions of these devices are listed in Table 4. The 8751H programs at VPP = 2lV using one
50 msec PROG pulse per byte programmed. This results in a total programming time (4K bytes) of approximately 4 minutes.
The procedure for programming the lock bit is detailed
in the 8751H data sheet.
Two Program Memory Lock Schemes
The 8751BH, 8752BH and 87C51 use the faster
"Quick-Pulse" programmingTM algorithm. These devices program at VPP = 12.75V using a series of
twenty-five 100 ,...S PROG pulses per byte programmed;
This results in a total programming time of approximately 26 seconds for the 8752BH (8 Kbytes) and
13 seconds for the 87C51(4 Kbytes).
The 8751BH, 8752BH and 87C51 contain two Program
Memory locking schemes: Encrypted Verify and Lock
Bits.
Encryption Array: Within the EPROM is an array of
encryption bytes that are initially unprogrammed (all
I's). The user can program the array to encrypt the
code bytes during EPROM verification. The verification procedure sequentially XNORs each code byte
with one of the key bytes. When the last key byte in the
array is reached, the verify routine starts over with the
first byte of the array for the next code byte. If the key
bytes are unprogrammed, the XNOR process leaves the
code byte unchanged. With the key bytes programmed,
the code bytes are encrypted and can be read correctly
only if the key bytes are known in their proper order.
Table 6 lists the number of encryption bytes available
on the various products.
Detailed procedures for programming and verifying
each device are given in the data sheets.
Exposure to Light
It is good practice to cover the EPROM window with
an opaque label when the device is in operation. This is
not so much to protect the EPROM array from inadvertent erasure, but to protect the RAM and other onchip logic. Allowing light to impinge on the silicon die
while the device is operating can cause logical malfunction.
When using the encryption array, one important factor
should be considered. If a code byte has the value
7-29
intel .
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
OFFH, verifying the byte will produce the encryption
byte value. If a large block of code is left unprogrammed, a verification routine will display'the encryption array contents. For this reason all unused code
bytes should be programmed with some value other
than OFFH, and not all of them the same value. This
will ensure maximum program protection.
When Lock Bit 1 is programmed, the logic level at the
EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes
to a random value, and holds that value until reset is
activated. It is necessary that the latched value of EA
be in agreement with the current logic level at that pin
in order for the device to function properly.
Program Lock Bits: Also included in the Program
Lock scheme are Lock Bits which can be enabled to
proVide varying degrees of protection. Table 5 lists the
Lock Bits and their corresponding effect on the microcontroller. Refer to Table 6 for the Lock Bits available
on the various products.
ROM PROTECTION
The 8051AHP and 80C51BHP are ROM Protected
versions of the 8051AH and 80C51BH, respectively. To
incorporate this Protection Feature, program verification has been disabled and external memory accesses
have been limited to 4K. Refer to the data sheets on
these parts for more information.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returning the part to full functionality.
ONCETM Mode
Table 5. Program Lock BIts and theIr Features
Program Lock Bits
The ONCE (Uon-circuit emulation") mode facilitates
testing and debugging of systems using the device without the device having to be removed from the circuit.
The ONCE mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN
is high;
2. Hold ALE low as RST is deactivated.
Protection Type
LB1
LB2
LB3
1
U
U
U
No program lock features
enabled. (Code verify will
still be encrypted by the
encryption array if
programmed.)
2
P
U
U
MOVC instructions
executed from external
program memory are
disabled from fetching
code bytes from internal
memory, EA is sampled
and latched on reset, and
further programming of
the EPROM is disabled.
3
P
P
U
Same as 2, also verify is
disabled.
4
P
P
P
Same as 3, also external
execution is disabled.
While the device is in ONCE mode, the Port 0 pins go
into a float state, and the other port pins and ALE and
PSEN are weakly pulled high. The oscillator circuit
remains active. While the device is in this mode, an
emulator or test CPU can be used to drive the circuit.
Normal operation is restored after a normal reset is
applied.
THE ON-CHIP OSCILLATORS
HMOS Versions
The on-chip oscillator circuitry for the HMOS
(HMOS-I and HMOS-II) members of the MCS-51 family is a single stage linear inverter (Figure 29), intended
for use as a crystal-controlled, positive reactance oscillator (Figure 30). In this application the crystal is operated in its fundamental response mode as an inductive
reactance in parallel resonance with capacitance external to the crystal:
P-Programmed
U-Unprogrammed
Any other combination of the Lock Bits is not dermed.
Table 6. Program Protection
Device
Lock Bits
Encrypt Array
8751BH
8752BH
87C51
LB1,LB2
LB1,LB2
LB1,LB2,LB3
32 Bytes
32 Bytes
64 Bytes
7-30
intel~
HARDWARE DESCRIPTION OFTHE 8051, 8052 AND 80C51
Vee
XTALl
f
SUBST.
270252-23
Figure 29. On-Chip Oscillator Circuitry in the HMOS Versions of the MCS®-51 Family
In general, crystals used with these devices typically
have the following specifications:
02
TO INTERNAL
TIMING CKTS
ESR (Equivalent Series Resistance)
Co (Shunt Capacitance)
CL (Load Capacitance)
Drive Level
VSS
see Figure 31
7.0pFmax.
30 pF ±3 pF
ImW
~--"1'--OUARTZ
CRYSTAL
OR CERAMIC RESONATOR
500
~
270252-24
400
:I:
Figure 30. Using the HMOS On-Chip Oscillator
The crystal specifications and capacitance values (CI
and C2 in Figure 30) are not critical. 30 pF can be used
in these positions at any frequency with good quality
crystals. A ceramic resonator can be used in place of
the crystal in cost-sensitive applications. When a ceramic resonator is used, CI and C2 are normally selected to be of somewhat higher values, typically, 47 pF.
The manufacturer of the ceramic resonator should be
consulted for recommendations on the values of these
capacitors.
~
300
'"~
200
100
4
8
16
12
CRYSTAL FREQUENCY In. 104Hz
270252-34
Figure 31. ESR vs Frequency
7-31
intet
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
Frequency, tolerance and temperature range are determined by the system requirements.
CHMOS Versions
A more in-depth discussion of crystal specifications, ceramic resonators, and the selection of values for Cl and
C2 can be found in Application Note AP-155, "Oscillators for Microcontrollers," which is included in the
Embedded Applications Handbook.
The on-chip oscillator circuitry for the 80C51BH,
shown in Figure 33, consists of a single stage linear
inverter intended for use as a crystal-controlled, positive reactance oscillator in the same manner as the
HMOS parts. However, there are some important differences. .
To drive the HMOS parts with an external clock
source, apply the external clock signal to XTAL2, and
ground XTALl, as shown in Figure 32. A pullup resistor may be used (to increase noise margin), but is optional ifVOH of the driving gate exceeds the VIH MIN
specification of XTAL2.
One difference is that the 80C5IBH is able to turn off
its oscillator under software control (by writing a 1 to
the PD bit in PCON). Another difference is that in the
80C5IBH the internal clocking circuitry is driven by
the signal at XTALI, whereas in the HMOS versions it
is by the signal at XTAL2.
The feedback resistor Rf in Figure 33 consists of paralleled n- and p- channel PETs controlled by the PD bit,
'such that Rf is opened when PD = 1. The diodes D I
and D2, which act as clamps to VCC and VSS, are
parasitic to the Rf FETs.
VCC
8051
EXTERNAL
.;><:---+------t
OSCilLATOR
SIGNAL
t
TTL
GATE
XTAL2
The oscillator can be used with the same external components as the HMOS versions, as shown in Figure 34.
Typically, Cl = C2 = 30 pF when the feedback element is a quartz crystal, and Cl = C2 = 47 pI< when a
ceramic resonator is used.
KTAll
VSS
WITH
TOTEM-POLE
OUTPUT
To drive the CHMOS parts with' an external clock
source, apply the external clock signal to XTALl, and
leave XTAL2 float, as shown in Figure 35.
270252-25
Figure 32. Driving the HMOS MCS®-S1
Parts with an External Clock Source
VCC
TO INTERNAL
TIMING CKTS
01
4000
XTAll
XTAL2
02
PO----I
270252-26
Figure 33. On-Chip Oscillator Circuitry in the CHMOS Versions of the MCS®-S1 Family
7-32
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
vce
TO INTERNAL
TIMINGCKTS
RI
XTAll-----
XTAL2------
_--;,--QUARTZ CRYSTAL
OR CERAMIC
RESONATOR
270252-27
Figure 34_ Using the CHMOS On-Chip Oscillator
INTERNAL TIMING
8OC5l
NC
EXTERNAL
OSCilLATOR
SIGNAL
t
")c>-------;
Figures 36 through 39 show when the various strobe
and port signals are clocked internally. The figures do
not show rise and fall times of the signals, nor do they
show propagation delays between the XTAL signal and
events at other pins.
XTAL2
XTAll
VSS
CMOS GATE
Rise and fall times are dependent on the external loading that each pin must drive. They are often taken to be
something in the neighborhood of 10 nsec, measured
between O.SV and 2.0V.
270252-28
Figure 35. Driving the CHMOS MCS®-51
Parts with an External Clock Source
Propagation delays are different for different pins. For
a given pin they vary with pin loading, temperature,
VCC, and manufacturing lot. If the XTAL waveform is
taken as the timing reference, prop delays may vary
from 25 to 125 nsec.
The reason for this change from the way the HMOS
part is driven can be seen by comparing Figures 29 and
33. In the HMOS devices the internal timing circuits
are driven by the signal at XTAL2. In the CHMOS
devices the internal timing circuits are driven by the
signal at XTALl.
The AC Timings section of the data sheets do not reference any timing to the XTAL waveform. Rather, they
relate the critical edges of control and input signals to
each other. The timings published in the data sheets
include the effects of propagation delays under the
specified test conditions.
7-33
intel .
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
I~I~
I~I~
STATE 11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 81 STATE 1 STATE 21
~I~
~I~
~I~ ~I~
~I~
~I~
XTAL:
ALE:
P2:
PCHOUT
PCH OUT
PCHOUT
270252-29
Figure 36. External Program Memory Fetches
I
I
STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~I~
~I~
~I~
~I~
~I~
~I~ ~I~
~I~
XTAL:
ALE:
RD:
DATA SAMPLED
FLOAT
PO:
~:
PCH OR
~SFR
DPH OR P2 SFR OUT
PCH OR
P2 SFR
270252-30
Figure 37. External Data Memory Read Cycle
7-34
int:eL
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
I~I~
I~I~
STATE 41 STATE 51 STATE 61 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~I~
~I~
~I~
~I~
~I~
~I~
XTAL:
ALE:
PCl OUT IF
PROGRAM MEMORY
WR:
PO:
P2
DATA OUT
PCH OR
P2SFR
PCH OR
P2 SFR
DPH OR P2 SFR OUT
270252-31
Figure 38. External Data Memory Write Cycle
I
STATE 41 STATE 51 STATE 61 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
1
~I~
~I~
~I~
~I~
~I~
~I~ ~I~
~I~
XTAL:
~PO,P1,P2,P3
~
O'P1'P2'P3
INPUTS SAMPLED:
RST
MOY PORT, SRC:
SERIAL PORT
SHIFT CLOCK
(MODE 0)
=::rI.-RST
NEW DATA
OLD DATA
--l
I-- RXD PIN SAMPLED
RXD SAMPLED
--1
\4270252-32
Figure 39. Port Operation
7-35
infel~
HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
ADDITIONAL REFERENCES
The following application notes and articles are found in the Embedded Applications handbook.
(Order Number: 270648)
1. AP-125 "Designing Microcontroller Systems for Electrically Noisy Environments".
2. AP-155 "Oscillators for Microcontrollers".
3. AP-252 "Designing with the 8OC5lBH".
4. AR-517 "Using the 8051 Microcontroller with Resonant Transducers".
7-36
intel·
8XC52/54/58 HARDWARE DESCRIPTION
INTRODUCTION
PIN DESCRIPTION
The 8XC52/54/58 is a highly integrated 8-bit microcontroller based on the MCS®-5! architecture. The key
features are an enhanced serial port for multi-processor
communications and an up/down timer/counter. As
this product is CHMOS, it has two software selectable
reduced power modes: Idle Mode and Power Down
Mode. Being a member of the MCS-51 family, the
8XC52/54/58 is optimized for control applications.
The 8XC5X pin-out is the same as the 80C5l. The olIly
difference is the alternate function of pins PLO and
Pl.l. PLO is the external clock input for Timer 2. Pl.l
is the Reload/Capture/Direction Control for Timer 2.
DATA MEMORY
The 8XC5X implements 256 bytes of on-chip RAM.
The upper 128 bytes occupy a parallel address space to
the Special Function Registers. That means they have
the same addresses, but they are physically separate
from SFR space.
This document presents a comprehensive description of
the on-chip hardware features of the 8XC52/54/58 as
they differ from the 80C5IBH. It begins by describing
how the I/O functions are different and then discusses
each of the peripherals as follows:
When an instruction accesses an internal location abDve
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of RAM or the SFR space by the
addressing mode used in the instruction. Instructions
that use direct addressing access SFR space. For example,
• 256 Bytes On-Chip RAM
• Special Function Registers (SFR)
• Timer 2
- Capture Timer/Counter
- Up/Down Timer/Counter
- Baud Rate Generator
MOV OAOH, #data (Direct Addressing)
• Full-Duplex Programmable Serial Interface with
- Framing Error Detection
- Automatic Address Recognition
accesses the SFR at location OAOH (which is P2). Instructions that use indirect addressing access the upper
128 bytes of RAM. For example,
• 6 Interrupt Sources
• Enhanced Power Down Mode
MOV @RO, #data (Indirect Addressing)
where RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH) .
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
• Power Off Flag
•. ONCE Mode
The 8XC52/54/58 uses the standard 8051 instruction
set and is pin-for-pin compatible with the existing
MCS-51 family of products. Table 1 summarizes the
product names and memory differences of the various
8XC52/54/58 products currently available. Throughout this document, the products will generally be referred to as the 8XC5X.
SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 2.
Table 1. 8XC52/54/58 Microcontrollers
Note that not all of the addresses are occupied. Unoccupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate effect.
ROM EPROM ROMless ROM/EPROM RAM
Bytes
Bytes
Device Version Version
80C52 87C52
80C54 87C54
80C58 87C58
80C32
80C32
80C32
8K
16K
32K
256
256
256
User software should not write Is to these unlisted locations, since they may be used in future MCS-51 products to invoke new features. In that case the reset or
inactive values of the new bits will always be O.
For a description of the features that are the same as
the 80C51, the reader should refer to the MCS-51 Architectural Overview, MCS-51 Programmers Guide/
Instruction Set, and the Hardware Description of the
80C51 in the Embedded Microcontrollers and Processors Handbook (Order #270645).
7-37
Order Number: 270783-004
inteL
8XC52/54/58 HARDWARE DESCRIPTION
Table 2. 8XC5X SFR Map and Reset Values
OFFH
OF8H
OFOH
B
00000000
OF7H
OEFH
OE8H
OEOH
ACC
00000000
OE7H
OD8H
ODFH
PSW
00000000
RCAP2L RCAP2H
TL2
TH2
T2CON
T2MOD
OC8H
00000000 XXXXXXOO 00000.000 00000000 0.0000000 00000000
OD7H
OCOH
OC7H
ODOH
OB8H
OBOH
OA8H
OAOH
98H
90H
88H
80H
IP
SADEN
XOOOOOOO 00000000
P3
11111111
IE
00000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
PO
11111111
OCFH
OBFH
IPH
OB7H
XOOOOOOO
SADDR
00000000
OAFH
OA7H
SBUF
XXXXXXXX
9FH
97H
TMOD
TLO
TL1
THO
TH1
00000000 0.0000000 00000000 00000000 00000000
DPL
DPH
SP
00000111 00000000 00000000
8FH
PCON
87H
00000000
Timer Registers-Control and status bits are contained
in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16bit auto-reload mode.
Interrupt Registers-The individual interrupt enable
bits are in the IE register. Two priorities can be set for
each of the 6 interrupt sources in the IP register. The
IPH register allows four priorities.
Serial Port Registers-Registers SADDR and SADEN are used to define the Given and the Broadcast
addresses for the Automatic Address Recognition feature.
TIMER 2
Timer 2 is a 16-bit Timer/Counter which can operate
either as a timer or an event counter. This is selectable
by bit C/T2 in the SFR T2CON (Table 3). It has three
7-38
intel .
8XC52/54/58 HARDWARE DESCRIPTION
operating modes: capture, auto-reload (up or down
counting), and baud rate generator. The modes are selected by bits in T2CON as shown in Table 4.
ternal input pin, T2. In this function, the external input
is sampled during SSP2 of every machine cycle. When
the samples show a high in one cycle and a low in the
next cycle, the count is incremented. The new count
value appears in the register during S3Pl of the cycle
following the one in which the transition was detected.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a I-to-O transition, the maximum count rate
is 1'24 of the oscillator frequency. To ensure that a given
level is sampled at least once before it changes, it
should be held for at least one full machine cycle.
Timer 2 consists of two 8-bit registers, TH2 and TL2.
In the Timer function, the TL2 register is incremented
every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1"2 of the oscillator
frequency.
In the Counter function, the register is incremented in
response to a I-to-O transition at its corresponding ex-
Table 3. T2CON-Timer/Counter 2 Control Register
T2CON Address = OCBH
Reset Value = 0000 OOOOB
Bit Addressable
Bit
7
6
5
3
4
Symbol
o
2
Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses
for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to
be used for the receive clock.
TCLK
Transmit ciock enable. When set, causes the serial port to use Timer 2 overflow pulses
for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows
to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2
= 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2
C/T2
Timer or counter select for Timer 2. C/T2
event counter (falling edge triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions
at T2EX if EXEN2 = 1.. CP /RL2 = a causes automatic reloads to occur when Timer 2
overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK
or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2
overflow.
=
7-39
1 starts the timer.
=
0 for timer function. C/T2
=
1 for external
8XC52/54/58 HARDWARE DESCRIPTION
Table 4. Timer 2 Operating Modes
RCLK
+ TCLK
CP/RL2
TR2
MODE
0
1
16-Bit Auto-Reload
0
0
1
1
. 16-Bit Capture
1
X
1
Baud Rate Generator
X
X
0
(Off)
CAPTURE MODE
In the capture mode there are two options selected by
bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a
16-bit timer or counter which upon overflow sets bit
TF2 in T2CON. This bit can then be used to generate
an interrupt. If EXEN2 = I, Timer 2 still does the
above, but with the added feature that a I-to-O transition at external input T2EX causes the current value
in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respectively. In addition, the transition at
T2EX causes bit EXF2 in T2CON to be set. The EXF2
bit, like TF2, can generate an interrupt. The capture
mode is illustrated in Figure 1.
AUTO-RELOAD (Up or Down Counter)
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature
oJ
is invoked by a bit named DCEN (Down Counter Enable) located in the SFR T2MOD (see Table 5). Upon
reset the DCEN bit is set to 0 so that Timer 2 will
default to count up. When DCEN is set, Timer 2 can
count up or down depending on the value of the T2EX
pin.
Figure 2 shows Timer 2 automatically counting up
when DCEN = O. In this mode there are two options
selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 counts up to OF,FFFH and then sets the TF2
. bit upon overflow. The overflow also causes the timer
registers to be reloaded with the 16-bit value in
RCAP2H and RCAP2L. The values in RCAP2H and
RCAP2L are preset by software. If EXEN2 = I, a
16-bit reload can be triggered either by an overflow or
by a I-to-O transition at external input T2EX. This
transition also sets the EXF2 bit. Both the TF2 and
EXF2 bits can generate an interrupt if enabled.
C/T2=1
T2 PIN
TRANSITION
DETECTION
T2EX PIN
270783-1
Figure 1. Timer 21n Capture Mode
7-40
intel·
8XC52154/58 HARDWARE DESCRIPTION
Table 5. T2MOD-Timer 2 Mode Control Register
T2MOD Address
=
Reset Value = XXXX XXOOB
OC9H
Not Bit Addressable
T20E
Bit
7
6
5
3
4
Symbol
DC EN
o
2
Function
Not implemented, reserved for future use.
T20E
Timer 2 Output Enable bit.
DCEN
When set, this bit allows Timer 2 to be configured as an up/down counter.
crJ
OVERFLOW
C/TI=1
T2 PIN
TIMER 2
INTERRUPT
TRANSITION
DETECTION
T2EX PIN
270783-2
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE)
a--.
+12
0-1
C/TI=1
T2 PIN
COUNT
DIRECTION
1=UP
O=DOWN
T2EX PIN
270783-3
Figure 3. Timer 2 Auto Reload Mode (DCEN
7-41
=
1)
int'eL
8XC52/54/58 HARDWARE DESCRIPTION
--,
Transition
1QIr----Ff. .+I---1B..--· ~~~;~;Pt
1:..- Detector
. (T;~X)'
T20E (T2MOD.1)
EXEN2
270783-6
Figure 4. Timer 2 in Clock-Out Mode
Setting the DCEN bit enables Timer 2 to count up or
down as shown in Figure 3. In this mode the T2EX pin
controls the direction of count. A logic I at T2EX
makes Timer 2 count up. The timer will overflow at
OFFFFH and set the TF2 bit. This overflow also causes
the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
BAUD RATE GENERATOR
Timer 2 is selected as the baud rate generator by setting
TCLK andlor RCLKin T2CON (Table 3). Note that
the baud rates for transmit and receive can be different.
This is accomplished by using Timer 2 for the receiver
or transmitter and using Timer I for the other function.
Setting RCLK andlor TCLK puts Timer 2 into its
baud rate generator mode, as shown in Figure 5.
A logic 0 at T2EX makes Timer 2 count down. Now
the timer underflows when TH2 and TL2 equal the
values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes OFFFFH to be reloaded into the timer registers.
The baud rate generator mode is similar to the auto-reload. mode, in that a rollover in TH2 causes the Timer 2
registers to be reloaded with thel6-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows. This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not
flag an interrupt.
The baud rates in Modes I and 3 are determined by
Timer 2's overflow rate as follows:
Modes 1 and 3 Baud Rates =
7-42
Timer 2 OverflOW Rate
16
int:eL
8XC52/54/58 HARDWARE DESCRIPTION
The Timer can be configured for either "timer" or
"counter" operation. In most apE!!.cations, it is configured for "timer" operation (CP /T2 = 0). The "timer"
operation is different for Timer 2 when it's being used
as a baud rate generator. Normally, as a timer, it increments every machine cycle (thus at '1.2 the oscillator
frequency). As a baud rate generator, however, it increments every state time (thus at '12 the oscillator frequency). The baud rate formula is given below:
Modes 1 and 3 _
Baud Rate
32
The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, TCAP2L) as shown in this equation:
.
Oscillator Frequency
Clock-Out Frequency = 4 x (65536 - RCAP2H, RCAP2L)
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator
simultaneously. Note, however, that the baud-rate and
clock-out frequencies can not be determined independently from one another since they both use RCAP2H
and RCAP2L.
Oscillator Frequency
- (RCAP2H, RCAP2Lll
x [65536
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
UART
Timer 2 as a baud rate generator is shown in Figure 5.
This figure is valid only if RCLK or TCLK = I in
T2CON. Note that a rollover in TH2 does not set TF2,
and will not generate an interrupt. Note too, that if
EXEN2 is set, a I-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
as a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.
The UART in the SXCSX operates identically to the
UART in the SOCSI except for the following enhancements. For a complete understanding of the SXCSX
UART please refer to the description in the SOCSI
Hardware Description chapter in the Embedded Microcontrollers and Processors Handbook.
Framing Error Detection-Framing Error Detection
allows the serial port to check for valid stop bits in
modes I, 2 or 3. A missing stop bit can be caused, for
example, by noise on the serial lines, or transmission by
two CPUs simultaneously.
It should be noted that when Timer 2 is running (TR2
= 1) in "timer" function in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP2 registers may be read, but
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. The timer
should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
If a stop bit is missing a Framing Error bit (FE) is set.
The FE bit can be checked in software after each reception to detect communication errors. Once set, the FE
bit must be cleared in software. A valid stop bit will not
clear FE.
The FE bit is located in SCON and shares the same bit
address as SMO. Control bit SMODO in the PCON register (location PCON.6) determines whether the SMO
or FE bit is accessed. If SMODO = 0, then accesses to
SCON.7 are to SMO. If SMODO = I, then accesses to
SCON.7 are to FE.
PROGRAMMABLE CLOCK OUT
A 50% duty cycle clock can be programmed to come
out on P1.0. This pin, besides being a regular I/O pin,
has two alternate functions. It can be programmed (1)
to input the external clock for Timer/Counter 2 or (2)
to output a 50% duty cycle clock ranging from 61 Hz
to 4 MHz at a 16 MHz operating frequency.
Automatic Address Recognition-Automatic Address
Recognition reduces the CPU time required to service
the serial port. Since the CPU is only interrupted when
it receives its own address, the software overhead to
compare addresses is eliminated. With this feature enabled in one of the 9-bit modes, the Receive Interrupt
(RI) flag will only get set when the received byte corresponds to either a Given or Broadcast address.
To configure the Timer/Counter 2 as a clock generator,
bit C/T2 (T2CON.l) must be cleared and bit T20E
(T2MOD.l) must be set. Bit TR2 (T2CON.2) starts
and stops the timer.
7-43
inteL
8XC52/54/58 HARDWARE DESCRIPTION
TIMER 1 OVERFLOW
NOTE: OSC. FREQ. IS DIVIDED BY 2. NOT 12.
- - -SMOD1
cr1
C/T2=1
T2 PIN
TRANSITION
DETECTION
T2EX PIN
270783-4
Figure 5. Timer 2 In Baud Rate Generator Mode
A slave's individual address is specified in SADDR.
SADEN is a mask byte that defines don't-care bits to
form the Given Address. These don't-cares allow flexibility in the user-dermed protocol to address one or
more slaves at a time. The following is an example of
how the user could define Given Addresses to selectively address different slaves.
A way to use this feature in multiprocessor systems is
as follows:
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. Remember,
an address byte has its 9th bit set to I, whereas a data
byte has its 9th bit set to O. All the slave processors
should have their SM2 bits set to I so they will only be
interrupted by an address byte. The Automatic Address
Recognition feature allows only the addressed slave to
be interrupted. In this mode, the address comparison
occurs in hardware, not software. (On the 80CSI serial
port, an address byte interrupts all slaves for an address
comparison).
Slave 1:
SADDR
SADEN
1111 0001
11111010
GIVEN
11110XOX
Slave 2:
The addressed slave then clears its SM2 bit and prepares to receive the data bytes that will be coming. The
other slaves are unaffected by these data bytes as they
are still waiting to receive an address byte.
SADDR
SADEN
1111 0011
11111001
GIVEN
1111 OXX1
The feature works the same way in the 8-bit mode
(Mode I) as in the 9-bit modes, except that the stop bit
takes the place of the 9th data bit. If SM2 is set, the RI
flag is set only if the received byte matches the Given or
Broadcast Address and is terminated by a valid stop
bit. Setting the SM2 bit has no effect on Mode O.
The SADEN bits are selected such that each slave can
be addressed separately. Notice that bit 0 (LSB) is a
don't-care for Slave I's Given Address, but bit 0 = I
for Slave 2. Thus, to selectively communicate with just
Slave 1 the master must send an address with bit 0 = 0
(e.g., 1111 0000).
The master can selectively communicate with groups of
slaves by using the Given Address. Addressing all
slaves at once is possible with the Broadcast Address.
These addresses are defined for each slave by two Special Function Registers: SADDR and SADEN.
Similarly, bit I = 0 for Slave I, but is a don't-care for
Slave 2. Now to communicate with just Slave 2 an address with bit I = I must be used (e.g., 1111 0111).
7-44
int:et
8XC52/54/58 HARDWARE DESCRIPTION
Finally, for a master to communicate with both slaves
at once the address must have bit 0 = 1 and bit 1 = O.
Notice, however, that bit 2 is a don't-care for both
slaves. This allows two different addresses to select
both slaves (1111 0001 or 1111 0101). If a third slave
was added that required its bit 2 = 0, then the latter
address could be used to communicate with Slave 1 and
2 but not Slave 3.
rupts (Timers 0, 1 and 2) and the serial port interrupt.
These interrupts are all shown in Figure 6.
Timer 2 Interrupt is generated by the logical OR of bits
TF2 and EXF2 in register T2CON. Neither of these
flags is cleared by hardware when the service routine is
vectored to. In fact, the service routine may have to
determine whether it was TF2 or EXF2 that generated
the interrupt and that bit will have to be cleared in
software.
The master can also communicate with all slaves at
once with the Broadcast Address. It is formed from the
logical OR of the SADDR and SADEN registers with
zeroes dermed as don't-cares. The don't-cares also allow flexibility in defining the Broadcast Address, but in
most applications a Broadcast Address will be OFFH.
The Timer 0 and Timer 1 flags, TFO and TFl, are set at
S5P2 of the cycle in which the timers overflow. The
values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag, TF2 is set at S2P2 and is
polled in the same cycle in which the timer overflows.
SADDR and SADEN are located at address OA9H and
OB9H, respectively. On reset, the SADDR and
SAD~N registers are initialized to DOH which defines
the Given and Broadcast Addresses as XXXX XXXX
(all don't-cares). This assures the 8XC5X serial port to
be backwards compatible with other MCS®-51 products which do not implement automatic address recognition.
Interrupt Priority Structure
A second Interrupt Priority register (IPH) has been
added, increasing the number of priority levels to four.
Table 6 shows this second register. The added register
becomes the MSB of the priority select bits and the
existing IP register acts as the LSB. This scheme maintains compatibility with the rest of the MCS-51 family.
Table 7 shows the bit values and priority levels associated with each combination.
.
INTERRUPTS
The 8XC5X has a total of 6 interrupt vectors: two external interrupts (INTO and INTI), three timer inter-
Table 6. IPH: Interrupt Priority High Register
IPH Address = OB7H
7
Bit
Reset Value = XOOO 0000
PPCH
PT2H
PSH
PT1H
PX1H
6
5
4
3
2
Symbol
-
Function
Not Implemented, reserved for future use.
PPCH
PCA interrupt priority high bit.
PT2H
Timer 2 interrupt priority high bit.
PSH
Serial Port interrupt priority high bit.
PT1H
Timer 1 interrupt priority high bit.
PX1H
External interrupt 1 priority high bit.
PTOH
Timer 0 interrupt priority high bit.
PXOH
External interru pt p riority hi g h bit.
7-45
PTOH
PXOH
o
8XC52/54/58 HARDWARE DESCRIPTION
With an external interrupt, INTO or INTI must be enabled and configured as level-sensitive before entering
Power Down. Holding the pin low restarts the oscillator and brin~ng the pin back high completes the exit.
After the RETI instruction is executed in the interrupt
service routine, the next instruction will be the one following the instruction that put the device in Power
Down.
Table 7. Priority Level Bit Values
Priority Bits
Interrupt Priority Level
IPH.x
IP.x
0
0
Level 0
0
1
Level 1
1
0
Level 2
1
1
Level 3
(Lowest)
(Highest)
POWER DOWN MODE
The 8XCSX can exit Power Down with either a hardware reset or external interrupt. Reset redefines all the
SFRs but does not change the on-chip RAM. An external interrupt aUows both the SFRs (except PD in
PCON) and the on-chip RAM to retain their values.
POWER OFF FLAG
The Power OtT Flag (pOF) located at PCON.4 is set by
. hardware when Vee rises from 0 to approximately SV.
POF can also be set or cleared by software. This allows
the user to distinguish between a "cold start" reset and
a "wann start" reset.
A cold start reset is one that is coincident with Vee
being turned on to the device after it was turned off. A
wann start reset occurs while Vee is still applied to the
device and could be generated, for example, by an exit
from Power Down.
Immediately after reset, the user's software can check
the status of the POF bit. POF = I would indicate a
cold start. The software then Clears PDF and commences its tasks. POF = 0 immediately after reset
.
would indicate a warm start.
1
Vee must remain above 3V for POF to retain a O.
rro--------------------------~.~
Program Memory Lock
In some microcontroller applications it is desirable that
the Program Memory be secure from software piracy.
The 8XCSX has varying degrees of program protection
depending on the device. Table 8 outlines the lock
schemes available for each device.
TF1
TI
RI
TF2
EXF2
D
D
Encryption Array: Within the EPROMIROM is an array of encryption bytes that are initia1ly unprogrammed
(all I's). For EPROM devices, the user can program
the encryption array to encrypt the program code bytes
during EPROM verification. For ROM devices, the
user submits the encryption array to be programmed by
the factory. If an encryption array is submitted, LBI
willru.so be programmed by the factory. The encryption
array is not available Without the Lock Bit. Program
code verification is perfonned as usual except that each
code byte comes out exclusive-NOR'ed (XNOR) with
one of the key bytes. Therefore, to read the
ROM/BPROM code, the user has to know the encryption key bytes in their proper sequence.
•
•
270783-5
Figure .6. Interrupt Sources
To properly tenninate Power Down the reset or external interrupt should not be applied before Vee is restored to its normal operating level and must be held
active long enough for the oscillator to restart and stabilize (nonnally less than 10 msec).
Unprogrammed bytes have the value OFFH. If the En~
cryption Array is left unprogrammed, aU the key bytes
have the value OFFH. Since any code byte XNOR'ed
7-46
int:el..
8XC52154/58 HARDWARE DESCRIPTION
with OFFH leaves the byte unchanged, leaving the Encryption Array unprogrammed in effect bypasses the
encryption feature.
ONCE MODE
The ON-Circuit Emulation (ONCE) mode facilitates
testing and debugging of systems using the 8XC5X
without having to remove the device from the circuit.
The ONCE mode is invoked by either:
1. Pulling ALE low while the device is in reset and
PSEN is high;
2. Holding ALE low as RESET is deactivated.
Program Lock Bits: Also included in the Program
Lock scheme are Lock Bits which can be enabled to
provide varying degrees of protection. Table 9 lists the
Lock Bits and their corresponding influence on the microcontroller. Refer to Table 8 for the Lock Bits available on the various products. The user is responsible for
programming the Lock Bits on EPROM devices. On
ROM devices, LBI is automatically set by the factory
when the encryption array is submitted. The Lock Bit
is not available without the encryption array on ROM
devices.
'
While the device is in ONCE mode, the Port 0 pins go
into a float state, and the other port pins, ALE, and
PSEN are weakly pulled high. The oscillator circuit
remains active. While the device is in this mode, an
emulator or test CPU can be used to drive the circuit.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returning the part to full functionality.
Normal operation is restored after a valid reset is applied.
Table 8. Program Protection
Device
Lock Bits
80C52
80C54
80C58
87C52
87C54
87C58
LB1
LB1
LB1
LB1,LB2,LB3
LB1,LB2,LB3
LB1,LB2,LB3
ADDITIONAL REFERENCES
Encrypt Array
64
64
64
64
64
64
The following application notes provide supplemental
information to this document and 'can be found in the
Embedded Applications handbook (Order No. 270648).
1. AP-125 "Designing ·Microcontroller Systems for
Electrically Noisy Environments"
2. AP-155 "Oscillators for Microcontrollers"
3. AP-252 "Designing with the 80C5IBH"
4. AP-41O "Enhanced Serial Port on the 83C51FA"
Bytes
Bytes
Bytes
Bytes
Bytes
Bytes
Table 9. Lock Bits
Program
Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. (Code verify ",,:iII still be encrypted by the
encryption array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
P = Programmed
U = Unprogrammed
Any other combination of Lock Bits is not defined.
7-47
MCS®-51
8-BIT CONTROL-ORIENTED MICROCONTROLLERS
8031AH/8051AH
8032AH/8052AH
8751H/8751H-8
•
•
•
•
•
•
•
•
•
•
•
High Performance HMOS Process
Internal Timers/Event Counters
2-Level Interrupt Priority Structure
32 I/O Lines (Four 8-Bit Ports)
64K Program Memory Space
Security Feature Protects EPROM Parts
Against Software Piracy
Boolean Processor
Bit-Addressable RAM
Programmable Full Duplex Serial
Channel
111 Instructions (64 Single-Cycle)
64K Data Memory Space
The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8,bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
The 8751 H is an EPROM version of the 8051 AH. It has 4 Kbytes of electrically programmable ROM which can
be erased with ultraviolet light. It is fully compatible with the 8051AH but incorporates one additional feature: a
Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The
8751 H-8 is identical to the 8751 H but only operates up to 8 MHz.
The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is
fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this
table for the ROM, ROMless and EPROM versions of each product.
Device
8052AH
8051AH
8032AH
8031AH
8751H
8751H-8
Internal Memory
Program
Data
8Kx8 ROM
4Kx8 ROM
none
none
4Kx8 EPROM
4Kx8 EPROM
256 x 8 RAM
128x8 RAM
256x8 RAM
128x8 RAM
128x8 RAM
128x8 RAM
7-48
Timers!
Event Counters
Interrupts
3 x 16-Bit
2 x 16-Bit
3 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
6
5
6
5
5
5
August 1992
Order Number: 270048-007
int:eL
MCS®-51
PO.O-PO.7
vee
va
P2.G-P2.7
r----------
-------------,
I
r.
I
I
I
I
nlllHG
AND
Ei
RST-+
CONTROL
I
h /L--.....:::..<::....-.....:::.~------">.~-""""---'
I
I
I
~~ ~----:(~~--------------------_r~----~~~-v1---------.J
~a:
I
I
I
I '--~-'---'
I
I
I
I
I
I
'-rr'T::r:i+I~
L
________
j
I
XTAL 1
P3.0-P3.7
P1.Q-Pl.7
270048-1
Figure 1. MCS®-S1 Block Diagram
PROCESS INFORMATION
The 8031AH/8051AH and 8032AH/8052AH devices are manufactured on P414.1, an HMOS II process. The 8751 H/8751 H-8 devices are manufactured on P421.X, an HMOS-E process. Additional
process and reliability information is available in Intel's Components Quality and Reliability Handbook,
Order Number 210997.
7-49
intel ...
MCS@·51
PACKAGES
Part
Prefix
. Package Type
OJ8
0Je
8051AHI
8031AH
P
D
N
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
45°C/W
45°C/W
4soC/W
1soC/W
15°C/W
1soC/W
8052AHI
8032AH
P
D
N
40-Pin Plastic DIP
40-P.in CERDIP
44-Pin PLCC
45°C/W
45°C/W
4soC/W
1soC/W
1soC/W
1soC/W
8751HI
8751H-8
D
40-Pin CERDIP
45°C/W
1soC/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of In~dl's thermal impedance test methodology.
tOIl]
t"'J L·j l1 t-J
rJ
L~
t::J l~ l;J ~, •.
• !~ PO.4(AD4)
rli: Pq.5 (AD5)
m PO.8(ADI)
[i! PO.7 (AD7)
10
11
n~
IIIvpp'
[~
R_rvecl"
12
13
ni
ALE/PIRm'
14
15
16
17
~!t
PIER
:¥. P2.& (AI4)
m P2.7(AI5)
:~!
f!!l
18
XTALI
VSS
~l ~:
1;;1 :=:
f~l !i.1 rIC:
riel ::;: :=:
P2.5 (AI3)
19
...2_0_ _ _ _---J
270048-3
DIP
PLCC
"EPROM only
""Do not connect reserved pins.
Figure 2. MCS®-S1 Connections
Port 0 pins that have 1's written to them float, and in
that state can be used as high-impedance inputs.
PIN DESCRIPTIONS
Vee: Supply voltage.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1's and can source and
sink 8 LS TIL inputs.
Vss: Circuit ground.
Port 0: Port 0 is an 8-bit open drain bidirectional 1/0
port. As an output port each pin can sink 8 LS TIL
inputs.
)
7-50
intel"
MCS®-51
Port 0 also receives the code bytes during programming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
EPROM parts. External pull ups are required during
program verification.
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1's
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will
source current (IlL on the data sheet) because of the
internal pullups.
Port 2 also receives the high-order address bits during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1's
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will
source current (IlL on the data sheet) because of the
pullups.
Port 1 also receives the low-order address bytes
during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
In the 8032AH and 8052AH, Port 1 pins P1.0 and
P1.1 also serve the T2 and T2EX functions, respectively.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1's
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will
source current (IlL on the data sheet) because of the
internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
7-51
Port
Pin
Alternative Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
infel"
MCS®-51
XTAL 1: Input to the inverting oscillator amplifier.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
XTAL2: Output from the inverting oscillator amplifier.
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during programming of the
EPROM parts.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
EA/Vpp: External Access enable EA must be
strapped to VSS in order to enable any MCS-51 device to fetch code from external Program memory
locations starting at OOOOH up to FFFFH. EA must
be strapped to Vee for internal program execution.
EXTERNAL
OSCILLATOR
SIGNAL
----f
XTAL2
Note, however, that if the Security Bit in the EPROM
devices is. programmed, the device will not fetch
code from any location in external Program Memory.
r - - - - XTAL1
This pin also receives the 21V programming supply
voltage (VPP) during programming of the EPROM
parts.
.....---.1 vss
C2
270048-5
r--~I~-....- - I XTAL2
Figure 4. External Drive Configuration
o
.....-
..... I~-.....- - t
DESIGN CONSIDERATIONS
If an 8751 BH or 8752BH may replace an 8751 H in a
future design, the user should carefully compare
both data sheets for DC or AC Characteristic differences. Note that the VIH and IIH specifications for
the EA pin differ significantly between the devices.
XTAL1
C1
.....-------.~ vss
Exposure to light when the EPROM device is in operation may cause logic errors. For this reason, it is
suggested that an opaque label be placed over the
window when the die is exposed to ambient light.
270048-4
C1. C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer.
Figure 3. Oscillator Connections
7-52
MCS®-51
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias. - 40·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on EAlVpp Pin to VSS ... - 0.5V to + 21.5V
Voltage on Any Other Pin to Vss .... -0.5V to + 7V
Power Dissipation .......................... 1.5W
Operating Conditions: TA (Under Bias) =
DC CHARACTERISTICS
Symbol
O·Cto +70·C; Vee
=
5V ±10%; Vss
=
OV
(Over Operating Conditions)
Parameter
Min
Max
Units
-0.5
0.8
V
0
0.7
V
Test Conditions
VIL
Input Low Voltage (Except EA Pin of
8751 H & 8751 H-8)
VIL1
Input Low Voltage to EA Pin of
8751 H & 8751 H-8
VIH
Input High Voltage (Except XTAL2, RST)
2.0
Vee + 0.5
V
VIH1
Input High Voltage to XTAL2, RST
2.5
Vee + 0.5
V
XTAL1
VOL
Output Low Voltage (Ports 1, 2, 3)'
0.45
V
IOL
VOL1
Output Low Voltage (Port 0, ALE, PSEN)*
0.60
0.45
V
V
IOL
IOL
0.45
V
8751 H, 8751 H-8
All Others
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN)
2.4
V
VOH1
Output High Voltage (Port 0 in
External Bus Mode)
2.4
V
IlL
Logical 0 Input Current (Ports 1, 2, 3,
RST)8032AH,8052AH
All Others
Vss
1.6 mA
= 3.2mA
= 2.4 mA
IOL = 3.2mA
IOH = -80 p.A
IOH = - 400 p.A
0.45V
0.45V
VIN
=
=
=
mA
VIN
=
0.45V
±100
±10
p.A
p.A
0.45 :0: VIN :0: Vee
0.45 :0: VIN :0: Vee
-800
-500
p.A
p.A
VIN
VIN
Logical 0 Input Current to EA Pin of
8751 H & 8751 H-8 Only
-15
mA
IIL2
Logical 0 Input Current (XT AL2)
-3.2
III
Input Leakage Current (Port 0)
8751 H & 8751 H-8
All Others
IIL1
=
=
0.45V
IIH
Logical 1 Input Current to EA Pin of
8751 H & 8751 H-8
500
p.A
VIN
=
2.4V
IIH1
Input Current to RST to Activate Reset
500
p.A
VIN
<
(Vee - 1.5V)
Icc
Power Supply Current:
8031 AH/8051 AH
8032AH/8052AH
8751 H/8751 H-8
125
175
250
mA
mA
mA
All Outputs
Disconnected;
EA = Vee
pF
Test freq
CIO
Pin Capacitance
10
~
=
1 MHz
*NOTE:
Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3.
The noise is due to external bus capa~citance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0
transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
7-53
intet
MCS®·51
AC CHARACTERISTICS Over Operating Conditions;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
Symbol
Parameter
12 MHz Oscillator
Max
Min
Variable Oscillator
Min
Max
12.0
1/TCLCL
Oscillator Frequency
TLHLL
ALE Pulse Width
127
3.5
2TCLCL-40
TAVLL
TLLAX
Address Valid to ALE Low
Address Hold after ALE Low
43
48
TCLCL-40
TCLCL-35
TLLlV
ALE Low to Valid Instr In
8751H
All Others
TLLPL
TPLPH
TPLIV
ALE Low to PSEN Low
PSEN Pulse Width
8751H
All Others
TPXIX
PSEN Low to Valid Instr In
8751H
All Others
Input Instr Hold after PSEN
TPXIZ
Input Instr Float after PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instr In
8751H
All Others
TPLAZ
PSEN Low to Address Float
TRLRH
RD Pulse Width
WR Pulse Width
TWLWH
MHz
ns
ns
ns
4TCLCL-150
4TCLCL-100
183
233
Units
ns
ns
58
TCLCL-25
ns
190
215
3TCLCL-60
3TCLCL-35
ns
ns
100
125
0
3TCLCL-150
3TCLCL-125
ns
ns
ns
TCLCL-20
ns
0
63
TCLCL-8
75
267
302
20
ns
5TCLCL-150
5TCLCL-115
ns
ns
20
ns
ns
6TCLCL-100
6TCLCL-100
400
400
RD Low to Valid Data In
252
ns
5TCLCL-165
ns
ns
TRLDV
TRHDX
Data Hold after RD
TRHDZ
TLLDV
Data Float after RD
ALE Low to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
TAVWL
ALE Low to RD or WR Low
Address to RD or WR Low
203
3TCLCL-50
4TCLCL-130
TOVWX
Data Valid toWR Transition
8751H
All Others
13
23
TCLCL-70
TCLCL-60
ns
ns
Data Valid to WR High
433
7TCLCL -.150
Data Hold after WR
33
TCLCL-50
ns
ns
TOVWH
TWHOX
TRLAZ
TWHLH
RD Low to Address Float
RD or WR High to ALE High
8751H
All Others
0
0
200
97
2TCLCL-70
ns
517
8TCLCL-150
ns
585
300
9TCLCL-165
ns
ns
20
33
43
133
123
NOTE:·
'This table does not include the 8751-8 AC characteristics (see next page).
7-54
. TCLCL-50
TCLCL-40
3TCLCL+50
ns
20
ns
TCLCL+50
TCLCL+40
ns
ns
intel~
MCS®-51
This Table is only for the 8751H-8
AC CHARACTERISTICS Over Operating Conditions;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
Symbol
Parameter
8 MHz Oscillator
Min
Max
Variable Oscillator
Min
Max
3.5
8.0
Units
1/TCLCL
Oscillator Frequency
TLHLL
ALE Pulse Width
210
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
85
TCLCL-40
ns
TLLAX
Address Hold after ALE Low
90
TCLCL-35
TLLlV
ALE Low to Valid Instr In
TLLPL
ALE Low to PSEN Low
100
TCLCL-25
TPLPH
PSEN Pulse Width
315
3TCLCL-60
TPLIV
PSEN Low to Valid Instr In
TPXIX
Input Instr Hold after PSEN
TPXIZ
Input Instr Float after PSEN
225
0
PSEN to Address Valid
TAVIV
Address to Valid Instr In
TPLAZ
PSEN Low to Address Float
TRLRH
RD Pulse Width
650
TWLWH
WR Pulse Width
650
TRLDV
RD Low to Valid Data In
ns
0
475
20
ns
ns
5TCLCL-150
ns
20
ns
6TCLCL-100
ns
6TCLCL-100
ns
5TCLCL-165
460
ns
ns
TCLCL-20
TCLCL-8
117
ns
ns
3TCLCL-150
105
TPXAV
ns
4TCLCL-150
350
MHz
ns
TRHDX
Data Hold after RD
TRHDZ
Data Float after RD
180
2TCLCL-70
ns
0
0
ns
TLLDV
ALE Low to Valid Data In
850
8TCLCL-150
ns
TAVDV
Address to Valid Data In
960
9TCLCL-165
ns
TLLWL
ALE Low to RD or WR Low
325
3TCLCL+50
ns
TAVWL
Address to RD or WR Low
370
TaVWX
Data Valid to WR Transition
TaVWH
Data Valid to WR High
TWHaX
Data Hold after WR
75
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
425
3TCLCL-50
4TCLCL-130
ns
55
TCLCL-70
ns
725
7TCLCL-150
ns
TCLCL-50
20
75
175
7-55
TCLCL-50
ns
20
ns
TCLCL+50
ns
intel~
MCS®-51
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
--",
PSEN
--",
PORTO _ _ _oJ
PORT 2 _ _ _ _ _,~_ _ _ _ _ _ _~~~_ _ _ _ _J,____A_8_-_A~1~5_ _ ___
270048-6
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
i+-----TLLDV
"
---->....- - TRLRH
PORTO
PORT 2
INSTR. IN
_-Jl~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _J
A8-A15 FROM PCH
P2.0-P2.7 OR A8-A15 FROM DPH
270048-7
EXTERNAL DATA MEMORY WRITE CYCLE
,
ALE
I
~TWHLH
TLHLL-
/
\.
-TLLWL
- TAVLL
,
~
TQVWH
DATA OUT
FROt.tRrt.t DPL
I
~TLLAX- ~
PORTO
~
TWLWH
-TWHQX
XAO-A7 FROM PeL
INSTR. IN
TAVWL
PORT 2
:::::>
P2.0-P2.7 OR A8-A 15 FROM DPH
X
A8-A 15 FROM PCH
270048-8
7-56
intel"
MCS®-51
SERIAL PORT TIMING-SHIFT REGISTER MODE
=
Test Conditions: Over Operating Conditions; Load Capacitance
Symbol
12 MHz Oscillator
Parameter
Min
Max
80 pF
Variable Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1.0
12TCLCL
J.Ls
TOVXH
Output Data Setup to Clock Rising
Edge
700
1OTCLCL -133
ns
TXHOX
Output Data Hold after Clock
Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold after Clock Rising
Edge
0
0
ns
TXHDV
Clock Rising Edge to Input Data
Valid
700
1OTCLCL -133
ns
SHIFT REGISTER TIMING WAVEFORMS
INSTRUCTlON
CLOCK
Il.-
~'QVXH ....
\
~
.A.T£ TO S8UF
'"PUT
UHQI
X
"HD'
I- - I j
X
X~
__~X~__~X~__~X~__~X~__~7
t
SUll
I-"HD'
0"'"
ellARRI
7-57
infel .
MCS@·S1
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TClCl
Oscillator Frequency (except 8751 H-8) .
8751H-8
3.5
3.5
12
8
MHz
MHz
TCHCX
High Time
20
TClCX
low Time
20
TClCH
Rise Time
20
ns
TCHCl
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
~---------TCLCL----------~~
270048-10
AC TESTING INPUT, OUTPUT WAVEFORM
z.e=><
.
z.o
0.1> TEST POINTS
< )C
z.o
0.1
.
0.45
270048-1i
AC Testing: Inputs are driven at 2.4V for a Logic "1" and 0.4SV
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
7-58
int'eL
MCS®·51
EPROM CHARACTERISTICS
Mode
Program
Inhibit
Verify
Security Set
RST
1
1
1
1
Table 3 EPROM Programming Modes
P2.7
PSEN
ALE
EA
o·
0
VPP
1
0
1
1
X
0
1
1
0
O·
VPP
1
0
NOTE:
P2.6
0
0
0
1
P2.5
P2.4
X
X
X
X
X
X
X
X
"1" = logic high for that pin
"0" = logic low for that pin
"X" = "don't care"
"VPP" = + 21V ± 0.5V
• ALE is pulsed low for 50 ms.
Programming the EPROM
Note that the EAIVPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for
any amount of time. Even a narrow glitch above that
voltage level can cause permanent damage to the
device. The VPP source should be well regulated
and free of glitches.
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0-P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Port 2 pins, and RST, PSEN, and EA
should be held at the "Program" levels indicated in
Table 3. ALE is pulsed low for 50 ms to program the
code byte into the addressed EPROM location. The
setup is shown in Figure 5.
Program Verification
If the Security Bit has not been programmed, the on·
chip Program Memory can be read out for verifica·
tion purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0-P2.3. The other pins should be held at the
"Verify" levels indicated in Table 3. The contents of
the addressed location will come out on Port O. External pullups are required on Port 0 for this operation.
Normally EA is held at a logic high until just before
ALE is to be pulsed. Then EA is raised to +21V,
ALE is pulsed, and then EA is returned to a logic
high. Waveforms and detailed timing specifications
are shown in later sections of this data sheet.
The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active·
low read strobe.
+SV
+SV
8151H
P2.0P2.J
8751H
P2."
P2.S
P2.6
P2.7
' - -....HXTALl
XTA12
V55
XTAll
V55
270048-12
Figure 5. Programming Configuration
270048-13
Figure 6. Program Verification
7-59
inteL
MCS®-51
EPROM Security
+5V
X = "DON'T CARE"
The security feature consists of a "locking" bit which
when programmed denies electrical access by any
external means to the on-chip Program Memory.
The bit is programmed as shown in Figure 7. The
setup and procedure are the same as for normal
EPROM programming, except that P2.6 is held at a
logic high. Port 0, Port 1 and pins P2.0-P2.3 may be
in any state. The other pins should be held at the
"Security" levels indicated in Table 3.
VCC
Pl
PO
P2.0P2.3
X
P2.4
X
8751H
ALE
AlE/PROG
P2.5
P2.6
Once the Security Bit has been programmed, it can
be cleared only by full erasure of the Program Memory. While it is programmed,. the internal Program
Memory can not be read out, the device can not be
further programmed, and it can not execute out of
external program memory. Erasing the EPROM,
thus clearing the Security Bit, restores the device's
full functionality. It can then be reprogrammed.
P2.7
EA.'VPP
XTAl2
RST
VIHl
XTALl
YSS
270048-14
Figure 7_ Programming the Security Bit
Erasure Characteristics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an ex- .
tended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2 . Exposing the
EPROM to an ultraviolet lamp of 12,000 /1-W/cm 2
rating for 20 to 30 minutes, at a distance of about 1
inch, should be sufficient.
Erasure leaves the array in an all 1's state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 27"C; VCC = 5V ±10%; VSS = ov
TA
Symbol
VPP
IPP
Parameter
Min
Programming Supply Voltage
Programming Supply Current
20.5
Max
21.5
30
Units
V
4
6
MHz
1/TCLCL
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
TGHDX
48TCLCL
48TCLCL
TEHSH
Data Setup to PROG Low
Data Hold after PROG
P2.7 (ENABLE) High to VPP
TSHGL
VPP Setup to PROG Low
10
TGHSL
VPP Hold after PROG
10
TGLGH
TAVQV
PROGWidth
45
TELQV
TEHQZ
Oscillator Frequency
mA
48TCLCL
Address to Data Valid
ENABLE Low to Data Valid
Data Float after ENABLE
/1-s
55
48TCLCL
48TCLCL
0
7-60
48TCLCL
/1-s
ms
int'el..
MCS®-S1
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
VERIFICATION
ADDRESS
ADDRESS
Pl.0-Pl.7
P2.0-P2.3
PORTO
_TAVQV
DATA IN
TDVGL
TAVGL
DATA OUT
I- _
~
'-
/
4!--TGHDX
I-
TGHAX
LE/PROG
TSHGL
E"A/VPP
\---'
TGHSL
TGLGH
21V '" .SV
~
\
TTL HIGH
--
TTL HIGH
TTL HIGH
TEHSH
P2.7
(ENABLE)
,
TELQV_
J
1--
!--TEHQZ
J
270048-15
For programming conditions see Figure 5.
For verification conditions see Figure 6.
DATA SHEET REVISION HISTORY
This data sheet (270048-007) is valid for 8051 AH/8031 AH and 8052AH/8032AH devices with an "A" at the
end of the topside tracking number. It is also valid for 8751 H/8751 H-8 devices without an "A" at the end of the
topside tracking number. Data sheets are changed as new device information becomes available. Verify with
your local Intel sales office that you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet (270048-007) and the previous version (270048-006):
1. Data sheet title was changed from:
MCS-51 8-Bit Control-Oriented Microcomputers 8031AH/8051AH 8032AH/8052AH 8751 H/8751 H-8
to:
MCS-51 8-Bit Control-Oriented Microcontrollers 8031AH/8051AH 8032AH/8052AH 8751 H/8751 H-8
2. The Operating Temperature Range has been changed to: O·C to
+ 70·C.
The following differences exist between the -006 and the -005 version of this data sheet.
1. 8051/8031 device offering deleted.
2. 8ja and 8je specifications added to the "Packages" table.
3. Capacitor values for ceramic resonators deleted from Figure 3.
The following are the key differences between the -005 and the -004 version of this data sheet.
1. Data sheet status changed from "Preliminary" to "Production".
2. LCC package offering deleted.
3. Maximum Ratings Warning and Data Sheet Revision History revised.
7-61
infel~
MCS®-51
The .following are the key differences between the -004 and the -003 version of this data sheet:
1. Introduction was expanded to include product descriptions.
2. Package table was added.
3. Design Considerations added.
4. Test Conditions for IIL1 and IIH specifications added to the DC Characteristics.
5. Data Sheet Revision History added.
7-62
8051AHP
MCS®-51 FAMILY
8-BIT CONTROL-ORIENTED MICROCONTROLLER
WITH PROTECTED ROM
•
•
•
•
•
•
•
•
•
•
High Performance HMOS Process
Internal TimerslEvent Counters
2-Level Interrupt Priority Structure
32 1/0 Lines (Four 8-Blt Ports)
4K Program Memory Space
•
Protection Feature Protects ROM Parts
Against Software Piracy
•
Boolean Processor
Bit-Addressable RAM
Programmable Full Duplex Serial
Channel
111 Instructions (64 Single-Cycle)
4K Data Memory Space*
*Expandable to 64K
Available in 40 Pin Plastic and CERDIP
Packages
(See Packaging Outlines and Dimensions Order #231369)
The MCS@-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
MCS-S1 HMOS
Family Device
8051AH
8051AHP
Internal Memory
Program
Data
4Kx8ROM
4Kx8ROM
128x8 RAM
128x8 RAM
Timers!
Event Counters
Interrupts
2 x 16-Bit
2 x 16-Bit
5
5
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.
7-63
October 1990
Order Number: 270279-004
intel .
8051AHP
P2.O-P2.7
PO.O-PO.r
vee
VIS
r-----------~~~ -~~~-------------,
I
~:
I
I
I
I
12-BIT
BUS IN
8051AHP
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PSiii
,----r--.
nMING
ALE
AND
Eli
CDNTIIDL
AST-+-
I ___--.,.-A--l
I
I
I
I
L
XTAL 1
I
Lrrr:;:-;::::'r-r-' ________ )
o
.(rl
P3.0-P3.7
P1.0-P1.7
270279-1
Figure 1. MCS®-S1 Block Diagram
7-64
I
I
infel"
8051AHP
LS TTL inputs. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
PACKAGES
Part
Prefix
Package Type
a051AHP
P
D
40-Pin Plastic DIP
40-Pin CERDIP
RXD P3,0
TXD P3,1
Port 2
vee
P1.0
Pt.1
PO.O
PO.1
PO,2
PO,3
PO,4
PO,S
PO,6
PO,7
10
ADO
AD1
AD2
AD3
AD4
ADS
AD6
AD7
Port 2 is an a-bit bidirectional 1/0 port with internal
pullups. The Port 2 output buffers can sinklsource 4
LS TTL inputs. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the internal pullups.
Eli
ALE
INTO P3.2
INTI P3,3
13
Wii P3,6
16
iiSEN
P2,7
P2,6
P2,S
P2,4
P2,3 Al1
P2,2 Al0
P2,1 A9
PIN DESCRIPTIONS
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. Bits
P2.4 through P2.7 are forced to 0, effectively limiting
external Data and Code space to 4K each in the
8051AHP during external accesses·. During accesses to external Data Memory that use 8-bit addresses
(MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
Vec
Port 3
Supply voltage.
Port S is an 8-bit bidirectional 1/0 port with internal
pullups. The Port S output buffers can sink/source 4
LS TTL inputs. Port S pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port S
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the pullups.
RDP3.7
XTAL2
XTALI
VSS
270279-2
Pin (PDIP, CERDIP)
Figure 2. MCS®-S1 Connections
Vss
Circuit ground.
PortO
Port S also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port 0 is an a-bit open drain bidirectional 1/0 port. As
an output port each pin caf'l sink a LS TTL inputs.
Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.
F'vrt 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data MemorY. In this application it uses strong internal pullups when emitting 1s and can source and
sink a LS TTL inputs.
Port 1
Port
Pin
Alternative Function
PS.O
PS.1
PS.2
PS.S
PS.4
PS.5
PS.6
PS.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INn (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory,read strobe)
Port 1 is an a-bit bidirectional 1/0 port with internal
pullups. The Port 1 output buffers can sink source 4
'Protection feature
7-65
8051AHP
RST
XTAL2
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
ALE
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning .
the use of the on-chip .oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory.
In normal operation ALE. is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
be observed.
Program Store Enable is the read strobe to external
Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
EXTERNAL
OSCILLATOR
SIGNAL
-----t
External Access enable EA should be strapped to
Vee for internal program executions. EA must be
strapped to Vss in order to enable any MeS-51 device to fetch code from external Program memory
locations starting at OOOOH up to FFFFH.
XTAL2
r--..,XTALl
....--f VSS
C2
270279-5
r---n-~~--I XTAL2
Figure 4. External Drive Configuration
o
...- - i l l - -.....- - I
DESIGti CONSIDERATION
The 8051AHP cannot access external Program or
Data memory l:jbove 4K. This means that the following instructions that use the Data Pointer only read/
write data at address locations below OFFFH:
XTAL1
C1
...-------1 vss
MOVX A, @DPTR
MOVX @DPTR, A
270279-4
C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
When the Data Pointer contains an address above
the 4K limit, those locations will not be accessed.
Figure 3. Oscillator Connections
To access Data Memory above 4K, the MOVX, @Ri,
A or MOVX A, @Ri instructions must be used.
XTAL1
Input tp the inverting oscillator amplifier.
7-66
8051AHP
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 70°C.
Ambient Temperature Under Bias .... O°C to
Storage Temperature ....... '" -65°C to
+ 150°C
Voltage on EAlVpp Pin to Vss ... -0.5V to
+ 21.5V
Voltage on Any Other Pin to Vss .... - 0.5V to
- WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7V
Power Dissipation .......................... 1.5W
Operating Conditions: TA (Under Bias) =
D.C. CHARACTERISTICS
Symbol
O°C to
+ 70°C; Vee =
5V ± 10%; Vss
=
OV
(Under Operating Conditions)
Parameter
Min
Max
Units
-0.5
0.8
V
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL2, RST)
2.0
Vee
VIH1
Input High Voltage to XTAL2, RST
2.5
Vee
VOL
Output Low Voltage (Ports 1, 2, 3)-
VOL1
Output Low Voltage (Port 0, ALE, PSEN)*
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN)
2.4
VOH1
Output High Voltage (Port 0 in External Bus Mode)
2.4
IlL
Logical 0 Input Current
-500
/LA
IIL2
Logical 0 Input Current (XTAL2)
-3.2
III
Input Leakage Current (Port 0)
±10
IIH
Input Current to RST to Activate Reset
Icc
Power Supply Current
CIO
Pin Capacitance
+ 0.5
+ 0.5
Test Conditions
V
=
V
XTAL1
0.45
V
0.45
V
mA
= 1.6 mA
= 3.2 mA
IOH = -80/LA
IOH = - 400 /LA
VIN = 0.45V
VIN = 0.45V
/LA
0.45 ~ VIN ~ Vee
500
/LA
VIN
125
mA
All Outputs
Disconnected;
EA = VCC
10
pF
Test freq
V
V
VSS
IOL
IOL
< (Vee
=
- 1.5V)
1 MHz
-NOTE:
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port O. and Port 2 pins when these pins make 1-to-0
transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
7-67
int:et
8051AHP
.A.C. CHARACTERISTICS Under Operating Conditions;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF
Symbol
Parameter
12 MHz OSCillator
Min
Max
Variable Oscillator
Min
Max
3.5
12.0
Units
MHz
1/TCLCL
Oscillator Frequency
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold after ALE Low
48
TCLCL-35
ns
TLLlV
ALE Low to Valid Instr In
TLLPL
ALE Low to PSEN Low
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instr In
TPXIX
Input Instr Hold after PSEN
TPXIZ
Input Instr Float after PSEN
4TCLCL-100
233
TCLCL-25
58
125
0
Address to Valid Instr In
TCLCL-20
TCLCL-8
TPLAZ
PSEN Low to Address Floet
TRLRH
RD Pulse Width
400
TWLWH.
WR Pulse Width
400
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold after RD
TRHDZ
Data Float after RD
302
20
ns
ns
20
ns
ns
6TCLCL-100
ns
5TCLCL-;-165
ns
ns
0
0
ns
5TCLCL-115
6TCLCL-100
252
ns
ns
0
75
PSEN to Address Valid
TAVIV
ns
3TCLCL-125
63
TPXAV
ns
3TCLCL-35
215
ns
97
2TCLCL-70
ns
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
TAVDV
Address to Valid Data In
585
9TCLCL-165
ns
3TCLCL+50
ns
300
. 3TCLCL-50
TLLWL
ALE Low to RD or WR Low
200
TAVWL
Address to RD or WR Low
203
4TCLCL-130
ns
ns
TOVWX
Data Valid to WR Transition
23
TCLCL-60
TOVWH
Data Valid to WR High
433
7TCLCL-150
ns
33
TCLCL-50
ns
TWHOX
Data Hold after WR
TRLAZ
RD Low to Address Float
20
RD or WR High to ALE High
123
TWHLH
43
7-68
TCLCL-40
20
ns
TCLCL+40
ns
intel .
8051AHP
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORTO
PORT 2
270279-6
EXTERNAL DATA MEMORY READ CYCLE
ALE
i-----TLLDV-----t
-.~~---TRLRH+_--~
PORTO
I------TAVDV-----~
PORT 2
P2.0-P2.7 OR A8-A 15 FROM DPH
A8-A 15 FROM PCH
,270279-7
7-69
intel .
8051AHP
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
TLLWL-t-i..- - - T W L W H - - - - I
,..-.,..--+1
PORTO
POAT2
TOVWX
t--+---TQVWH-----I
DATA OUT
P2.0-P2.7 OR A8-A 15 FROM DPH
A8-.<115 FROM PCH
270279-8
7-70
intel~
8051AHP
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: TA = O·C to +70·C; Vee = 5V ±10%; Vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator
Parameter
Symbol
Min
Max
Variable Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1.0
12TCLCL
,""S
TOVXH
Output Data Setup to Clock Rising
Edge
700
1OTCLCL -133
ns
TXHOX
Output Data Hold after Clock
Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold after Clock Rising
Edge
0
0
ns
TXHDV
Clock Rising Edge to Input Data
Valid
700
1OTCLCL -133
ns
SHIFT REGISTER TIMING WAVEFORMS
1..-...-
-------.
'XLXL
\
t--'
WAITE
to sau'
~
X
"H.'
I--l j
X
f.- ,,"0'
X~
__~X~__~X~__~X~__~X~___JI
t
SET 'I
7-71
int'et
8051AHP
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TClCl
Oscillator Frequency
3.5
12
MHz
TCHCX
High Time
20
TClCX
low Time
20
TClCH
Rise Time
20
ns
TCHCl
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
i------TCLCL
-------..,~
270279-10
x=:
A.C. TESTING INPUT, OUTPUT WAVEFORM
. =X >
20
.
TEST POINTS
D.45
08
<
2.0
0.8
DATA SHEET REVISION HISTORY
The following are the key differences between this
and the -003 version of the 8051AHP data sheet:
1. Data sheet status changed from "Preliminary" to
"Production" .
2. Revised Maximum Ratings Warning and Data
Sheet Status Notice.
270279-11
A.c. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
'
Logic "1" and 0.8V for a Logic "0".
The following are the key differences between this
and the -002 version of 8051AHP data sheet:
1. Package Table was added.
2. Added clearer explanation to DESIGN CONSIDERATION.
Program Verification
The program verification test mode has been eliminated on the 8051 AH P. It is not possible to verify the
ROM contents using this mode, the way EPROM
programmers typically do. Also, the ROM contents
cannot be verified by a program executing out of
external program memory due to the restricted addressing on the 8051AHP.
3. Data Sheet Revision History was added.
7-72
8751BH
SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 4 KBYTES OF EPROM PROGRAM MEMORY
•
Program Memory Lock
•
Two 16-Bit Timer/Counters
•
•
128 Bytes Data Ram
Quick Pulse Programming Algorithm
•
5 Interrupt Sources
•
Programmable Serial Channel
•
12.75 Volt Programming Voltage
•
64K External Program Memory Space
•
Boolean Processor
•
64K External Data Memory Space
•
32 Programmable I/O Lines
PO.o- PO.7
r----------
v~
Vss
~.....,......~;
P2.0-P2.7
-=r~."IJC- -
-
-
-
-
-
-
-
-
-
-
,
~
!'SEN
AL~~
RST
P3.0- P3.7
PloD-Pl.?
270248-1
Figure 1. 8751BH Block Diagram
7-73
September 1992
Order Number: 270248-005
8751BH
PACKAGES
PIN DESCRIPTIONS
Part
Prefix
Package Type
Vee: Supply Voltage.
8751BH
P
N
40-Pin Plastic DIP
44-Pin PLCC
Vss: Circuit ground.
PLO
vee
Pl.l
PO.O (ADO)
P1.2
PO.l (A01)
P1.3
PO.2 (A02)
P1.4
PO.3 (A03)
P1.S
PO.4 (A04)
P1.S
PO.S (ADS)
P1.7
PO.S (ADS)
RESET
Port 0: Port 0 is an 8-bit open drain bidirectional 1/0
port. As an output port each pin can sink 8 LS TIL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1s, and can source and
sink 8 LS TIL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pull ups are required
during program verification.
PO.7 (A07)
(RXO) P3.0
EA/VPP
(TXO) P3.1
ALE/PROG
(iNTO) P3.2
PSEN
(INTl) P3.3
P2.7 (A1S)
(TO) P3.4
P2.S (AI4)
(T1) P3.S
(iYR) P3.S
(Ril) P3.7
P2.S (AI3)
XTAL2
P2.2 (Al0)
XTALI
P2.1
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 1 output buffers can sinkl
source 4 LS TIL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.
P2.4 (AI2)
P2.3 (All)
(A9)
P2.0 (A8)
VSS
270246-2
Port 1 also receives the low-order address bytes
during EPROM programming and program verification.
Pin (DIP)
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can sinkl
source 4 LS TIL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pull ups.
PO.4 (A04)
PO.S (ADS)
P1.7
PO.6 (A06)
RST
PO.7 (A07)
(RXO) P3.0
Ne
11
EA/Vpp
8751BH
(TXO) P3.1
Ne
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
ALE/PROG
(iNTO) P3.2
PSEN
(iNn) P3.3
P2.7 (A1S)
(TO) PM
P2.6 (A14)
(n) P3.S
P2.S (A13)
Port 2 also receives the high-order address bits during EPROM programming and program verification.
270246-14
Pad (PLCC)
Figure 2. Pin Connections
7-74
inteL
8751BH
XTAL2: Output from the inverting oscillator amplifier.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the pullups.
OSCILLATOR CHARACTERISTICS
Alternate Function
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Applications Note AP-155, "Oscillators for Microcontrollers."
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
C2
I--t---t
XTAL 2
D
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming.
1--6---t XTAL 1
.....--------1 vss
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
270248-3
C1, C2 ~ 30 pF ± 10 pF for Crystals
For Ceramic Resonators. contact resonator manufacturer.
Figure 3. Oscillator Connections
PSEN: Program Store Enable is the Read strobe to
External Program Memory.
EXTERNAL
OSCILLATOR----I XTAL2
SIGNAL
When the 8751 BH is executing code from external
Program Memory, PSEN is ac!ivated twice each machine cycle, except that two PSEN activations are
skipped during each access to External Data Memory.
r - - XTALl
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations
starting at OOOOH up to FFFFH. Note, however, that
if either of the Lock Bits are programmed, EA will be
internally latched on reset.
270248-4
Figure 4. External Clock Drive Configuration
DESIGN CONSIDERATIONS
EA should be strapped to Vee for internal program
executions.
If an 8751 BH is replacing an 8751 H in an existing
design, the user should carefully compare both data
sheets for DC or AC Characteristic differences. Note
that the VIH and IIH specifications for the EA pin differ significantly between the 8751 Hand 8751 BH.
This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
7-75
intel .
8751BH
ABSOLUTE MAXIMUM RATINGS'"
Ambient Temperature Under Bias •... O·C to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 70·C
Storage Temperature .•...•. : .. - 65·C to
+ 150·C
Voltage on EAlVpp Pin to Vss ... -0.5V to
+ 13.0V
Voltage on Any Other Pin to Vss ...• -0.5V to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
these are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7V
Maximum IOL Per 1/0 Pin ......•..••.....•• 15 mA
Power Dissipation .•.......•...•..........•. 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions: TA (Under Bias) =
DC CHARACTERISTICS
Symbol
O·C to
+ 70·C; Vee =
5V
± 10%; Vss =
ov
(Under Operating Conditions)
Parameter
Min
Max
Unit
VIL
Inp!.!t Low Voltage (Except EA)
-0.5
0.8
V
Vll1
Input Low Voltage EA
Vss
0.7
V
VIH
Input High Voltage
(ExceptXTAL2, RST, EA)
2.0
Vee + 0.5
V
VIH1
Input High Voltage XTAl2, RST
2.5
Vee + 0.5
V
VIH2
Input High Voltage to EA
4.5
5.5
V
VOL
Output Low Voltage (Note 3)
(Ports 1 , 2 and 3)
0.45
V
IOL
=
1.6 mA (Note 1)
VOl1
Output Low Voltage (Note ~)
(Port 0, ALE/PROG, PS N)
0.45
V
IOL
=
3.2 mA (Notes 1 , 2)
VOH
Output High Voltage
(Ports 1, 2, 3, ALE/PROG and PSEN)
2.4
V
IOH
=
-80 p.A
VOH1
Output High Voltage
(Port 0 in External Bus,Mode)
2.4
V
IOH
=
-400 p.A
IlL
Logical 0 Input Current
(Ports 1, 2, 3 and RST)
-1
mA
VIN
=
0.45V
= VSS
= 0.45 V XTAL 1 =
0.45 < VIN < Vee
4.5V < VIN < 5.5V
VIN < (Vee - 1.5V)
IIL1
Logical 0 Input Current (EA)
-10
mA
IIL2
Logical 0 Input Current (XTAL2)
-3.2
mA
III
Input Leakage Current (Port 0)
±10
p.A
Test Conditions
XTAL1
=
VSS
VIN
VIN
Vss
IIH
Logical 1 Input Current (EA)
1
mA
IIH1
Input Current to RST
to Activate Reset
500
p.A
lee
Power Supply Current
175
mA
All Outputs Disconnected
CIO
Pin CapaCitance
10
pF
Test Freq
=
1MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external-bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PROG pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the 8751BH. ALE refers to a timing signal that is output on the ALE/PROG pin.
3. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per 8-bit port Port 0:
26 mA
Ports 1, 2, and 3:
15 mA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7-76
intal..
8751BH
AC CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and
PSEN
= 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
12 MHz Osc
Parameter
Min
1/TCLCL
Max
Oscillator Frequency
Variable Oscillator
Min
Max
3.5
12.0
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
48
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
302
5TCLCL-115
ns
TPLAZ
PSEN Low to Address Float
20
20
ns
TCLCL-35
233·
'.
58
TCLCL-25
ns
3TCLCL-35
ns
125
3TCLCL-125
0
0
TCLCL-8
RD Pulse Width
400
6TCLCL-100
WR Pulse Width
400
6TCLCL-100
RD Low to Valid Data In
Data Hold After RD
252
0
ns
ns
TCLCL-20
63
75
TRLRH
TRLDV
ns
215
TWLWH
TRHDX
ns
4TCLCL-100
ns
ns
ns
ns
5TCLCL-165
0
. ns
ns
TRHDZ
Data Float After RD
97
2TCLCL-70
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
ns
TAVDV
Address to Valid Data In
585
9TCLCL-165
ns
3TCLCL+50
ns
TLLWL
ALE Low to RD or WR Low
200
TAVWL
Address to RD or WR Low
203
300
3TCLCL-50
ns
4TCLCL-130
ns
TQVWX
Data Valid to WR Transition
23
TCLCL-60
ns
TQVWH
Data Valid to WR High
433
7TCLCL-150
ns
TWHQX
Data Held After WR
33
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
TCLCL-50
0
43
7-77
123
TCLCL-40
ns
0
ns
TCLCL+40
ns
intel .
8751BH
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ __
PSEN
---
PORTO _ _ _J
PORT 2
---..I
.270248-5
EXTERNAL DATA MEMORY 'READ CYCLE
ALE
PSEN
i-----TLLDV
'I
----<-1--- TRLRH -----+\
,---------------------
~---------+----------"'
PORTO=:~~~~~~~~~~~~~~~i:=:=:=:=:~~=:=:=:=:::~~I~NS=T~R.~I:N
PORT2 ___,~_ _ _ _~P2~.0~-~P~2~.7_0~R~Af.8--~Al~5~F~R~O~M~D~PH~_ _ _~r'__~A8~-~A~1~5~FR~O~M~P~C~H~__
270248-6
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLLWL--_---TWLWH---!
I---+---TQVWH - - - - - I
PORTO
PORT 2
__
FROM RI OR DPL
i----TAVWL----I
-"~
DATA OUT·
____ _____________________
~
P2.0-P2.7 OR A8-A 15 FROM DPH
INSTR. IN
A8-A15 FROM PCH
270248-7
7-78
intel .
8751BH
SERIAL PORT TIMING TEST CONDITIONS
Symbol
(TA
=
SHIFT REGISTER MODE
O°C to
+ 70°C; Vee =
5V ± 10%; VSS
Min
OV; Load Capacitance
=
80 pF)
Variable Oscillator
12MHzOsc
Parameter
=
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1.0
12TCLCL
,...s
TQVXH
Output Data Setup to
Clock Rising Edge
700
1OTCLCL -133
ns
TXHQX
Output Data Hold After
Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After
Clock Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to
Input Data Valid
700
1OTCLCL -133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
0
2
4
3
5
7
6
8
ALE
CLOCK
OUTPUT DATA
X
3
X
4
I
X
5
X
6
X
7
t
7
SET TI
WRITE TO SBUF
INPUT DATA
I
CLEAR RI
EXTERNAL CLOCK DRIVE WAVEFORMS
_--TCLCL--+l
7-79
270248-9
infel .
8751BH
AC TESTING INPUT/OUTPUT WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min Max Units
1/TCLcl Oscillator Frequency 3.5
12
2 . 4 = X 2.0
D.B
MHz
TCHCX
High Time
20
ns
TClCX
low Time
20
ns
TClCH
Rise Time
20
ns
TCHCl
Fall Time
20
ns
EPROM CHARACTERISTICS
Programming the EPROM
2.0
TEST POINTS
D.B
)C
DASV
270248-10
AC inputs during testing are driven at 2.4V for a logic "1" and
0.45V for a logic "0". Timing measurements are made at 2.0V' for
a logic "1" and 0.8V for a logic "0".
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0 - P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Port 2 and 3 pins, and RST, PSEN, and
EAlVpp should be held at the "Program" levels indicated in Table 1. AlE/PROG is pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.
+5V
8751BH
Normally EA~is held at a logic high-':!,ntil just
before AlE/PROG is to be pulsed. Then EAlVpp is
raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The voltage on the EAlVpp pin must be at the valid EAlVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
Vss
270248-11
Figure 5. Programming the EPROM
Note that the EAlVpp pin must not be allowed to go
above the maximum specified Vpp level for any
7-80
intel .
8751BH
Table 1. EPROM Programming Modes
RST
PSEN
ALEI
PROG
EAI
Vpp
P2.7
P2.6
P3.6
P3.7
Program Code Data
1
0
O·
Vpp
1
0
1
1
Verify Code Data
1
0
1
1
0
0
1
1
Program Encryption Table
Use Addresses 0-1 FH
1
0
O·
Vpp
1
0
0
1
1
1
0
0
O·
O·
Vpp
Vpp
1
1
1
1.
1
0
1
0
1
0
1
1
0
0
0
0
MODE
Program Lock
Bits (LBx)
Read Signature
x=1
x=2
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12.75V ±0.25V
• ALE/PROG is pulsed low for 100 p.s for programming. (Quick-Pulse Programming)
tents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port 0
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually "unencrypt" the data during verify.)
QUICK-PULSE PROGRAMMING
ALGORITHM
The 8751 BH can be programmed using the QuickPulse Programming Algorithm for microcontrollers.
The features of the new programming method are a
lower Vpp (12.75 volts as compared to 21 volts) and
a shorter programming pulse. It is possible to program the entire 4 Kbytes of EPROM memory in less
than 13 seconds with this algorithm
The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.
To program the part using the new algorithm, Vpp
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 tJ.seconds, 25 times. Then, the byte just
programmed may be verified. After programming,
the entire· array should be verified. The Program
Lock features are programmed using the same
method, but with the setup as shown in Table 1. The
only difference in programming Lock features is that
the Lock features cannot be directly verified. Instead, verification of programming is by observing
that their features are enabled.
8751BH
PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0 - P2.3. The other pins should be held at
the "Verify" levels indicated in Table 1. The con-
270248-12
Figure 6. Verifying the EPROM
7-81
infel·
8751BH
PROGRAM MEMORY LOCK
!
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy.
ERASURE CHARACTERISTICS
This device is in a plastic package without a window
and, therefore, cannot be erased.
Encryption· Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
Reading the Signature Bytes
The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. the values returned are:
(030H) = 89H indicates manufactured by Intel
(031 H) = 51 H indicates 8751 BH
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.
Lock Bits
Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in
Table 2.
Table 2. Lock Bits and their Features
Lock Bits
To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its
external state.
Logic Enabled
LB1
LB2
U
U
Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)
P
U
MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled
P
P
Same as above, but Verify is also
disabled
U
P
Reserved for Future Definition
P - Programmed
U = Unprogrammed
7-82
infel~
8751BH
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21"C to 27"C, vee = 5.0V ±10%, Vss = OV)
Symbol
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
IPP
Programming Supply Current
50
rnA
6
MHz
Units
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold After PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold After PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
J.Lsec
TGHSL
Vpp Hold After PROG
10
J.Lsec
TGLGH
PROGWidth
90
TAVOV
Address to Data Valid
TELOV
ENABLE Low to Data Valid
TEHOZ
Data Float After ENABLE
0
TGHGL
PROG High to PROG Low
10
4
110
J.Lsec
48TCLCL
48TGLCL
48TCLCL
J.Lsec
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
P1.0-P1.7
P2.0-P2.3
VERIFICAnON
-----<=:JA~OD~R~ES~S~:==r-----{=:JA~DD~R~ES~SC:J-----TAVOV
PORTO------1rt=~~~:::::~------_1~DA~T!A~O~UT~~-----TDVGL
ALE/PROG
------,,1
TGHDX
TGHAX
TGLGH
~
fA/Vpp
__
Vpp
---~-r+=J T_EH_S_H_ _ _ _ _ _ _ _ _ _ _~
P2.7
-----
TEHOZ
~----~
270248-13
7-83
infel·
8751BH
DATA SHEET REVISION HISTORY
The following is the key difference between this and the -004 version of the 8751 BH data sheet:
Data sheet title was changed from:
8751BH Single-Chip 8-BitMicrocomputer with 4K Bytes of EPROM Program Memory
to:
8751BH Single-Chip 8-Bit Microcontroller with 4 Kbytes of EPROM Program Memory
The following are the key differences between the -004 and the -003 version of the 8751 BH data sheet:
1. Data sheet status changed from "Preliminary" to "Production".
2. Revised Maximum Ratings Warning and data sheet status notice.
The following are the key differences between the -003 and the -002 version of the 8751 BH data sheet:
1. Status went from ADVANCE INFORMATION to PRELIMINARY.
2. Package Table was added.
3. PLCC pin connections shown.
4. Design Considerations section replaced with reference to previous designs using the 8751 H.
5. Note 3 on maximum current specification was added to DC Characteristics.
6. Table 1 updated to show Read Signature Mode.
7. ERASING'THE EPROM paragraph deleted.
8. ERASURE CHARACTERISTICS section changed to indicate plastic packages only.
9. Signature Bytes added.
10. Data Sheet Revision History was added.
7-84
8751BH
EXPRESS
•
Extended Temperature Range
•
Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program is an extended temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vee
guidelines in MIL-STD-883, Method 1015.
= 5.5V ± 0.25V, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to + 85°C; Vee = 5V ±10%;Vss = OV
Symbol
VIH
Parameter
Min
Input High Voltage (Except
XTAL2, RST, EA)
2.1
7-85
Max
Vee
+ 0.5
Unit
Test Conditions
V
January 1989
Order Number: 270708-001
intel~
8751BH EXPRESS
Table 1. Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
plastic
commercial
no
N
PLCC
commercial
no
TP
plastic
extended
no
TN
PLCC
extended
no
LP
plastic
extended
yes
Please note:
• Commercial temperature range is O°C to 70°C. Extended temperature range is - 40°C to
• Burn-in is dynamic, for a minimum time of 160 hours at 125°C, Vee
MIL-STD-883 Method 1015 (Test Condition D).
+ 85°C .
= 5.5V ±0.25V, following guidelines in
Examples: N8751 BH indicates 8751 BH in a PLCC package and specified for commercial temperature range,
without burn-in. LP8751 BH indicates 8751 BH in a plastic package and specified for extended temperature
range with burn-in.
7-86
8752BH
SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 8 KBYTES OF EPROM PROGRAM MEMORY
• 2·Bit Program Memory Lock
•
12.75 Volt Programming Voltage
• 6 Interrupt Sources
• Programmable Serial Channel
• Separate Transmit/Receive Baud Rate
Capability
•
Boolean Processor
• .64K External Program Memory Space
• 256 Bytes Data Ram
• Quick Pulse Programming Algorithm
• 64K External Data Memory Space
• 32 Programmable I/O Lines
• Three 16·Bit Timer/Counters
PO.O-PO.7
Veer - - - - - - - - v"""4
P2.0-P2.7
-P.fil.i:ti;
-----------,
-F
rnN
ALE/I'lmll
EX/Vpp
RST
P3.0-P3.7
P1.0-P1.7
270429-1
Figure 1. Block Diagram
7-87
September 1992
Order Number: 270429-004
intel..
8752BH
PACKAGES
Part
8752BH
Package Type
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
Prefix
P
D
N
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1s, and can source and
sink 8 LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
(T2) PI.D
(12EX) PI.1
P1.2
PO.I (AD1)
P1.3
PO.2 (A02)
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.
PO.,3 (,4,03)
P1.5
PI.6
(RXD) P3.0
EA/Vpp
(TXO) P3.!
ALE/PROG
PSEN
Port 1 also receives the low-order address bytes
during EPROM programming and program verification.
270429-2
DIP
In addition, P1.0 and P1.1 serve the functions of the
following special features of the MCS®-51 Family:
Port Pin
P1.0
P1.1
6
RST
5
"
.3
2
10
(RXD) P3.0
I,
8752BH
,.
N'
12
(TXD)P3.,
13
AlE,IP'RCiG
(iNTO) P3.2
(iNfi) P3.3
'4
P'S'fN
Ne
15
(TO) P3.4
16
(TI) P3.S
17
18
a
Alternate Function
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)
20 21 22 23 24 25 26 27 28
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pull ups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pull ups when emitting 1s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
270429-15
PLCC
Figure 2. Pin Connections
PIN DESCRIPTION
Port 2 also receives the high-order address bits during EPROM programming and program verification.
VCC:·Supply voltage.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the pullups.
Vss: Circuit ground.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
7-88
int'eL
8752BH
Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Applications Note AP-155, "Oscillators for Microcontrollers."
Port Pin
Alternate Function
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
INTO (external interrupt 0)
P3.2
P3.3
INT1 (external interrupt 1)
P3.4
TO (Timer 0 ex1ernal input)
P3.5
I!JTimer 1 ex1ernal input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
To drive the device from an external clock source,
XTAL1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
2
~
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming on
the 8752BH.
o
XTAL2
Cl
XTAL 1
Vss
270429-3
C1, C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators, Contact Resonator Manufacturer.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
Figure 3. Oscillator Connections
EXTERNAL
OSCILLATOR - - - - I XTAL 2
SIGNAL
PSEN: Program Store Enable is the Read strobe to
Ex1ernal Program Memory.
XTAL 1
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to External Data Memory.
Vss
270429-4
Figure 4. External Clock Drive Configuration
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations
starting at OOOOH up to FFFFH. Note, however, that
if either of the Lock Bits are programmed, EA will be
internally latched on reset.
DESIGN CONSIDERATIONS
Exposure to light when the 8752BH is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window
of the 8752BH when the die is exposed to ambient
light.
EA should be strapped to Vee for internal program
executions.
This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
Due to a timing problem in the Timer/Counter 2 interrupt circuitry; the device may vector to location
03H (External Interrupt 0 vector address). It happens
when a low priority interrupt has been in progress for
either 1 or 2 machine cycles and Timer/Counter 2
generates a priority 1 interrupt. Therefore, Timer /
Counter 2 should only be assigned priority level O.
XTAL 1: Input to the inverting oscillator amplifier. .
XTAL2: Output from the inverting oscillator amplifier.
If an 8752BH is replacing an 8751 H in an existing
design, the user should carefully compare both data
sheets for DC or AC characteristic differences. Note
that the VIH and IIH specifications for the EA pin differ significantly between the 8751 Hand 8752BH.
OSCILLATOR CHARACTERISTICS
XTAL1 and XT AL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
7-89
infe'.
8752BH
ABSOLUTE MAXIMUM RATINGS·
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Ambient Temperature Under Bias .•. ; .• O·C to 70·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. pperation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 1S0·C
Voltage on EAlVpp Pin to Vss .•. -O.SV to + 13.0V
Voltage on Any Other Pin to Vss .... -O.SV to + 7V
Storage Temperature ..•.•.•... - 6S·C to
Maximum IOL Per 1/0 Pin ••. ; •....•........ 1S rnA
Power Dissipation ••..••.....•.••......•.•.• 1.SW
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions: TA (under Bias) =
DC CHARACTERISTICS
Symbol
Vil
O·C to
+ 70·C; Vcc = sv ± 10%; Vss = ov
(Under Operating Conditions)
Parameter
Input Low Voltage (Except Eli)
.
Min
Max
Units
-0.5
O.S
V
Test Conditions
VIl1
Input Low Voltage EA
Vss
0.7
V
VIH
Input High Voltage
(ExceptXTAL2, RST, EA)
2.0
Vee + 0.5
V
VIH1
Input High Voltage XTAL2, RST
2.5
Vee + 0.5
V
VIH2
Input High Voltage to Eli
4.5
5.5
V
VOL
Output Low Voltage (Note 3)
(Ports I, 2 and 3)
0.45
V
10L = 1.6 mA (Note 1)
VOL1
Output Low Voltage (Note 3)
(Port 0, ALE/Pl'iOG, PSEN)
0.45
V
10l
= 3.2 mA (Note 1, 2)
VOH
Output High Voltage
(Ports 1, 2, 3, ALE/PROG and PSE:N)
2.4
V
10H
= -SOpA
VOH1
Output High Voltage
(Port 0 in External Bus Mode)
2.4
V
10H
=
III
Logical 0 Input Current
(Ports 1, 2, 3 and RST)
IIl1
Logical 0 Input Current (EA)
XTALI = Vss
-400/LA
-500
pA
VIN = 0.45V
mA
pA
VIN
= VSS
500
= 0.45V XTAL1 = Vss
-10
11L2
Logical 0 Input Current (XTAL2)
-3.2
mA
VIN
III
Input Leakage Current (Port 0)
±10
/LA
0.45
IIH
Logical 1 Input Current (EA)
mA
4.5V
IIHI
Input Current to RST
to activate Reset
500
/LA
VIN
Icc
Power Supply Current
175
mA
All Outputs Disconnected
CIO
Pin Capacitance
10
pF
Test freq
1
-
< VIN < Vee
< VIN < 5.5V
< (Vee - 1.5V)
= 1 MHz
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOlS of ALE/J5l'K5G
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make l-to-O transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PFIDG pin may exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2. ALE/~ refers to a pin on the device. ALE refers to a timing signal that is output on the ALE/J5l'K5G pin.
3. Under steady state (non-transient) conditions, 10l must be externally limited as follows:
Maximum 10l per port pin:
10 mA
Maximum 10l per S-bit portPort 0:
26 mA
Ports I, 2, and 3:
15 mA
Maximum total 10l for all output pins:
71 mA
If 10l exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
.7-90
int'et
8752BH
L:Logic level LOW, or ALE
P:PSEN
Q:Output data
R:RD signal
T:Time
V:Valid
W:WR signal
X:No longer a valid logic level
Z:Float
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A:Address
C:Clock
D:lnput Data
H:Logic level HIGH
1:lnstruction (program memory contents)
For example,
TAVLL = Time from Address Valid to ALE Low.
TLLPL = Time from ALE Low to PSEN Low.
AC CHARACTERISTICS
(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and
PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
12MHzOsc
Min
Max
Variable Oscillator
Min
Max
3.5
12.0
Units
1/TCLCL
Oscillator Frequency
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
48
TCLCL-35
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
302
5TCLCL-115
ns
TPLAZ
PSEN Low to Address Float
20
20
ns
TRLRH
RD Pulse Width
400
6TCLCL-100
TWLWH
WR Pulse Width
400
6TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
97
2TCLCL-70
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
ns
TAVDV
Address to Valid Data In
585
9TCLCL-165
ns
TLLWL
ALE Low to RD or WR Low
200
3TCLCL+50
ns
TAVWL
Address to RD or WR Low
203
4TCLCL-130
ns
TOVWX
Data Valid to WR Transition
23
TCLCL-60
ns
TOVWH
Data Valid to WR High
433
7TCLCL-150
ns
TWHOX
Data Held After WR
33
TCLCL-50
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
233
58
TCLCL-25
3TCLCL-35
ns
0
63
0
ns
ns
3TCLCL-50
0
43
123
7-91
TCLCL-40
ns
ns
0
300
ns
ns
5TCLCL-165
252
ns
ns
TCLCL-20
TCLCL-8
75
ns
ns
3TCLCL-125
125
0
ns
4TCLCL-100
215
MHz
ns
0
ns
TCLCL+40
ns
intel .
8752BH
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PORT 0 _ _ _,
PO~2
1'-..;,;;.....;,;~-~
_ _ _ _-'~_ _ _ _ _~.....;,;~_ _ _ _J,_ _ _~.....;,;~_ ___
270429-5
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
i--:------'--TLLDV - - - - - - 1
PORTO=j~~~~~1=~~==
TAVWL
TAVDV
PORT2 __~,,-_______~P~2.~O-~P~2~.7~O~R~A~8~-A~1~5~F~RO~M~D~P~H_______~__.....;,;A~8~-A~1~5~F~RO~M~PC~H~__
270429-6
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLLWL--<-t---TWLWH
I-'--f---TQVWH---+J
PORTO
FROM RI OR OPL
DATA OUT·
TAVWL
PORT2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
---"~------------------------~--I~--------------270429-7
7-92
intel®
8752BH
SERIAL PORT TIMING-SHIFT REGISTER MODE
TEST CONDITIONS
Symbol
T A = O°C to
+ 70°C; Vee
= 5V
± 10%; VSS
= OV; Load Capacitance = 80 pF
12 MHzOsc
Parameter
Variable Oscillator
Max
Min
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1.0
12TCLCL
p..s
TOVXH
Output Data Setup to
Clock Rising Edge
700
1OTCLCL -133
ns
TXHOX
Output Data Hold After
Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After
Clock Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to
Input Data Valid
1OTCLCL -133
700
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
0
2
5
4
7
6
8
ALE
CLOCK
OUTPUT DATA
f
X
\.-~~ '-~~ \.-';;""..J
3
X
4
X
5
X
6
X
7
t
I
SET TI
WRITE TO SBUF
INPUT DATA ----~~~,.....,J ~~~-,~~_""I.I.~V__,~~__.~~-'\.r.~~"""'~v
..
t
f
SET RI
CLEAR RI
270429-8
EXTERNAL CLOCK DRIVE WAVEFORMS
i-o---TCLCL - - _
7-93
270429-9
intet
8752BH
EXTERNAL CLOCK DRIVE
Symbol
Parameter
AC TESTING INPUT/OUTPUT WAVEFORMS
Min Max Units
1/TClCl Oscillator Frequency 3.5
12
2 . 4 = X 2.0
0.8
MHz
TCHCX
High Time
20
ns
TClCX
low Time
20
ns
TClCH
Rise Time
20
ns
TCHCl
Fall Time
20
ns
2.0
TEST POINTS
0.8
)C
0.4SV
270429-10
AC inputs during testing are driven at 2.4V for a logic "1" and
0.45V for a logic "0". Timing measurements are made at 2.0V for
a logic "1" and O.BV for a logic "0".
gram" levels indicated in Table 1. AlE/PROG is
pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.
EPROM CHARACTERISTICS
Table 1 shows the logic levels for programming the
Program Memory, the Encryption Table, and the
lock Bits and for reading the signature bytes.
Normally EA~is held at a logiC high-.!:!,ntil just
before AlE/PROG is to be pulsed. Then EAlVpp is
raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The voltage on the EAlVpp pin must be at the valid EAlVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
Programming the EPROM
To be programmed, the 8752BH must be running
with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is
being used to transfer address and program data to
appropriate internal registers.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port o. The other Port 2 and 3 pins, and RST,
PSEN, and EAlVpp should be held at the "Pro-
Note that the EAlVpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.
+5V
ALE/PROG
25 100}'. PULSES TO GND
8752BH
.--_---fXTAL2
'----'--+--fXTAL 1
Vss
270429-11
Figure 5. Programming the EPROM
7-94
inteL
8752BH
Table 1. EPROM Programming Modes
RST
PSEN
ALEI
PROG
EAt
1
0
o·
Verify Code Data
1
0
Program Encryption Table
Use Addresses 0-1 FH
1
0
1
1
0
0
1
0
MODE
Program Code Data
Program Lock
Bits (LBx)
x=1
x=2
Read Signature
P2.7
P2.6
P3.6
P3.7
Vpp
1
0
1
1
1
1
0
0
1
1
O·
Vpp
1
·0
0
1
O·
O·
Vpp
Vpp
1
1
1
1
1
0
1
0
1
1
0
0
0
0
Vpp
NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = +12.75V ±0.25V
*ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming)
QUICK-PULSE PROGRAMMING
ALGORITHM
PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0 - P2.4. The other pins should be held at
the "Verify" levels indicated in Table 1. The contents of the addressed location will come out on Port
o. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port 0
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually "unencrypt" the data during verify.)
The 8752BH can be programmed using the QuickPulse Programming Algorithm for microcontrollers.
The features of the new programming method are a
lower Vpp (12.75 volts as compared to 21 volts) and
a shorter programming pulse. It is possible to program the entire 8 Kbytes of EPROM memory in less
than 25 seconds with this algorithm!
To program the part using the new algorithm, Vpp
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 ""seconds, 25 times as shown in Figure
6. Then, the byte just programmed may be verified.
After programming, the entire array should be verified. The Program Lock features are programmed
using the same method, but with the setup as shown
in Table 1. The only difference in programming Lock
features is that the Lock features cannot be directly
verified. Instead, verification of programming is by
observing that their features are enabled.
The setup, which is shown in Figure 7, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.
1'------25 PULSES
1 14
ALE/PROG:~-.----~
'--------'
'--.
10}'s
M'N1I'
n
!~~t:
'I
.n
ALE/PROG : - - - . . : . . . ,
o L _ _ _ _ _ _ _....I· '-_ _ _ _ _ _..1_ "'_ _ __
270429-12
Figure 6. PROG Waveforms
7-95
intel .
8752BH·
OSy
270429-13
Figure 7. Verifying the EPROM
Table 2. Lock Bits and their Features
PROGRAM MEMORY LOCK
Lock Bits
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against soft.
ware piracy.
LB2
U
U
Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)
P
U
MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled
P
P
Same as above, but Verify is also
disabled
U
P
Res~rved
ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
Logic Enabled
LB1
for Future Definition
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.
P = Programmed
U = Unprogrammed
LOCK BITS
READING THE SIGNATURE BYTES
Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in Table
The signature bytes are read by th!3 same procedure
as a normal verification of locations 030H and 031 H,
except that P3:6 and P3.7 need to be pulled to a
logic low. The values returned are:
2.
Erasing the EPROM also erases the Encryption Array and the Lock Bits, returning the part to full unlocked functionality.
(030H) = 89H indicates manufactured by Intel
(031 H) = 52H indicates 8752BH
To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its
external state.
7-96
8752BH
ERASURE CHARACTERISTICS
this type of exposure, it is suggested that an opaque
label be placed over the window.
.
Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at lease 15 W-secl cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 fJ-W/cm rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1s state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA
=
21°C to 27"C , Vee
Symbol
=
50V +
- 10% , Vss
=
OV)
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
50
mA
6
MHz
Units
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold After PROG
48TCLCL
TOVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold After PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
fJ-s
TGHSL
Vpp Hold After PROG
10
fJ-s
90
4
TGLGH
PROG Width
TAVQV
Address to Data Valid
48TCLCL
48TCLCL
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float After ENABLE
0
TGHGL
PROG High to PROG Low
10
110
fJ-s
48TCLCL
fJ-s
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
Pl.0-Pl.7
P2.0-P2.4
VERIFICATION
-----1=~A~DD~R~ES~S~~=~-----C=~AD§D~RE~SSC:::>----TAVQV
PORTO-----11=~~~~~t_-----~~DA~~~0~u~T::~---TDYGL
TAYGL
ALE/PROG - - - - - ,
TSHGLr-TGLGH
EIi/vpp
Jf
Ypp
l=.iTEHSH
P2.7
-----111-------------- ~__......J
TEHQZ
270429-14
7-97
8752BH
DATA SHEET REVISION HISTORY
The following is the key difference between this and the -003 version of the 8752BH data sheet:
Data sheet title was changed from:
8752BH Single-Chip 8-Bit Microcomputer with 8K Bytes of EPROM Program Memory
to:
8752BH Single-Chip 8-Bit Microcontroller with 8 Kbytes of EPROM Program Memory.
The following are the key differences between the -003 and the -002 version of the 8752BH data sheet.
1. Data sheet status changed from "Preliminary" to "Production".
2. Deleted LCC Package offering.
3. Revised Maximum Ratings warning and data sheet status notice.
The following are the key differences between the -002 and the -001 version of the 8752BH data sheet.
1. PLCC pin connection diagram was added.
2. Package table was added.
3. Timer/Counter 2 Design Consideration was added.
4. Design Consideration was added referring to previous designs using the 8751 H.
5. Note 3 was added to DC Characteristics. to explain the maximum current specification.
6. Signature Byte was corrected.
7. Data Sheet Revision History was added.
7-98
8752BH
EXPRESS
•
Extended Temperature Range
•
Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-S1 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards ..
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over t~e range of - 40·C to + 8S·C.
.
The optional burn-in is dynamic, for a minimum time of 160 hours at 12So C with Vee
guidelines in MIL-STD-883, Method 101S.
= S.SV ± 0.2SV, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee =
Symbol
VIH
sv ±10%;Vss = ov
Parameter
Min
Max
Unit
Input High Voltage (Except
XTAL2, RST, EA)
2.1
Vee + O.S
V
7-99
Test Conditions
January 1989
Order Number: 270650-002
intel .
8752BH EXPRESS
Table 1. Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
plastic
commercial
no
D
cerdip
commercial
no
N
PLCC
commercial
no
R
LCC
commercial
no
-
TO
cerdip ,
extended
no
ap
plastic
commercial
yes
LD
cerdip
extended
yes
Please note:
• Commercial temperature range is O·C to 70·C. Extended temperl;lture range is -40·C to +85~C .
• Burn-in is dynamic, for a minimum time of 160 hours at 125·C, Vee = 5.5V ±0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
Examples: N8752BH indicates 8752BH in a PLCC package and specified for commercial temperature range,
without burn-in. LD8752BH indicates 8752BH in a cerdip package and specified for extended temperature
range with burn-in.
DATA SHEET REVISION SUMMARY
The following are the key differences between this and the -001 version of the 8752BH Express data sheet:
1. VIH parameter changed to read "(Except XTAL2, RST, EA)".
2. aD option removed.
3. Data Sheet Revision Summary added.
7-100
80C31 BH/80C51 BH
EXPRESS
•
Extended Temperature Range
•
Burn-In
•
3.S to 12 MHz Vee
=
SV ± 20%
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of -40·C to + S5·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125·C with Vee
guidelines in MIL-STD-883, Method 1015.
=
6.9V
± 0.25V, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial SOC51 BH/SOC31 BH
data sheet, 270064-008.
7-101
September 1990
Order Number: 270218-003
intel .
80C31BH/80C51BH EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS
Symbol
TA
=
-40'Cto +S5'C;Vcc
=
5V ±20%;Vss
=
OV
Limits
Parameter
Min
VIL
Input Low Voltage (Except EA)
VIL1
EA
VIH
Input High Voltage (Except XTAL 1, RST)
VIH1
Input High Voltage to XTAL 1, RST
IlL
Logical 0 Input Current (Port 1, 2, 3)
ITL
Logical 1 to 0 transition
Current (Ports 1, 2, 3)
Max
Unit
-0.5
0.2Vcc - 0.15
V
-0.5V
0.2Vcc - 0.35
V
Test
Conditions
0.2Vcc + 1
Vcc + 0.5
V
0.7Vcc + 0.1
Vcc + 0.5
-75
V
/LA
Yin = 0.45V
-750
/LA
Yin = 2.0V
Table 1. Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
D
Cerdip
Commercial
No
N
PLCC
Commercial
No
TP
Plastic
Extended
No
TD
Cerdip
Extended
No
TN
PLCC
Extended
No
OP
Plastic
Commercial
Yes
Yes
aD
Cerdip
Commercial
ON
PLCC
Commercial
Yes
LP
Plastic
Extended
Yes
LD
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
NOTE:
• Commercial temperature range is O'C to 70'C. Extended temperature range is - 40'C to + B5'C.
• Burn-in is dynamic for a minimum time of 160 hours at 125'C, Vee = 6.9V ±0.25V, following guidelines in MIL-STD-BB3
Method 1015 (Test Condition D).
Examples:
PSOC31 BH indicates SOC31 BH in a plastic package and specified for commercial temperature range, without
burn-in.
LDSOC51 BH indicates SOC51 BH in a cerdip package and specified for extended temperature range with burnin.
DATA SHEET REVISION HISTORY
The following are the key differences between this and the -002 version of the SOC31 BH/SOC51 BH express
data sheet:
1. Data sheet status changed from "Preliminary" to "Production".
2. Added this revision history.
7·102
80C51BHP
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH PROTECTED ROM
80CS1BHP-3.S-12 MHz, Vee = SV ± 20%
80CS1BHP-1-3.S-16 MHz, Vee = SV ± 20%
80CS1BHP-2-o.S-12 MHz, Vee := SV ± 20%
•
•
•
•
•
•
Power Control Modes
128 x 8-Blt RAM
32 Programmable I/O Lines
Two 16-Blt Timer/Counters
4K Program Memory Space
Protection Feature Protects ROM Parts
Against Software Piracy
•
•
•
•
•
•
High Performance CHMOS Process
Boolean Processor
S Interrupt Sources
Programmable Serial Port
4K Data Memory Space
(Expandable to 64K)
ONCE (On-Circuit Emulation) Mode
The MCS
..............
270603-2
270603-3
Pin (PDIP)
Pad (PLCC)
Figure 2. Connection Diagrams
7-105
intel .
80C51BHP
While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the 80C51 BHP is in this
mode, an emulator or test CPU can be used to drive
the circuit. Normal operation is restored when a normal reset is applied.
PACKAGES
Part
Prefix
Package Type
80C51BHP
P
N
40-Pin Plastic DIP
44-Pin PLCC
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal PUIIUPS when emitting 1s. In the
80C51 BHP, Bits 2.4 through 2.7 are forced to 0, effectively limiting external data and code space to 4K
each during external accesses (see Design Considerations). During accesses to external Data Memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits
the contents of the P2 Special Function Register.
Port 3
Vee
Port 3 is an 8-bit bidirectional 110 port with internal
pullups. Port 3 pins that have 1s written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (ilL, on
the data sheet) because of the pullups.
Supply voltage during normal, Idle, and Power Down
operations.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
PIN DESCRIPTIONS
Port Pin
Vss
P3.0
Circuit ground.
P3.1
P3.2
P3.3
P3.4
P3.5
Port 0
Port 0 is an 8-bit open drain bidirectional 1/0 port.
Port 0 pins that have 1's written to them float, and.in
that state can be used as high-impedance inputs.
P3.6
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pull ups when emitting 1s.
Port 1
Port 1 is an 8-bit bidirectional 1/0 port with internal
pull ups. Port 1 pins that have 1s written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (ilL, on
the data sheet) because of the internal pullups.
Port 2
Port 2 is an 8-bit bidirectional 1/0 port with internal
pull ups. Port 2 pins that have 1s written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IlL, on
the data sheet) because of the internal pullups.
P3.7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt O)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write
strobe)
RD (external data memory read
strobe)
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
An internal diffused resistor to Vss permits PowerOn reset using only an external capacitor to Vee.
ALE
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
7-106
infel .
80C51BHP
Program Store Enable is the read strobe to external
Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are.
skipped during each access to external Data Memory. PSEN is not activated during fetches from internal program memory.
.
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by·two flip-flop, but minimum and
maximum high and low times specified on the data
sheet must be observed.
Design Considerations
External Access enable. EA must be strapped to
Vss in order to enable the device to fetch code from
external Program Memory locations starting at
OOOOH up to FFFFH. If EA is strapped to Vee the
device executes from internal Program Memory unless the program counter contains an address greater than OFFFH.
XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
XTAL2
• The 80C51 BHP cannot access external Program
or Data memory above 4K. This means that the
following instructions that use the Data Pointer
only read/write data at address locations below
OFFFH:
MOVX A, @DPTR
MOVX @DPTR, A
When the Data Pointer contains an address
above the 4K limit, those locations will not be accessed. To access Data Memory above 4K, the
MOVX @Ri, A or MOVX A, @Ri instructions must
be used.
• Before entering the Power Down mode the contents of the Carry Bit and B.7 must be equal.
• When the Idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reo
set, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
Output from the inverting oscillator amplifier.
XTAL2
XTAL 1
t - - - - - - - - - 1 Vss
270603-4
-
Figure 3. Crystal OSCillator
EXTERNAL
OSCILLATOR
SIGNAL
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip OSCillator, as shown in
Figure 3. More detailed information concerning the
use of the on-chip oscillator is available in Application Note AP-155, "Oscillator for Microcontrollers".
7-107
NC
XTAL2
-----------1
XTAL 1
270603-5
Figure 4. External Drive Configuration
80C518HP
ABSOLUTE MAXIMUM RATINGS·
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Ambient Temperature Under Bias •••. O·C to + 70·C
Storage Temperature ••.•.•••••• - 65·C to
+ 150·C
Voltage on any
Pin to Vss ................ -0 ..5V to VCC +0.5V
Voltage on Vcc to Vss .••..••.•••.. -0.5V to 6.5V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
/
Maximum IOL per 110 Pin .••.••..•...••.••. 15 rnA
Power Dissipation ......................... 1.0W*
'This value is based on the maximum allowable die temperature and
the thermal resistance of the package.
Operating Conditions: T A (Under Bias) =
DC CHARACTERISTICS
Symbol
O·C to + 70·C; Vcc
=
5V
± 20%; Vss =
OV
(Under Operating Conditions)
Parameter
Typ(3)
Max
Unit
VIL
Input Low Voltage
(ExceptEA)
-0.5
0.2 Vee -0.1
V
VILl
Input Low Voltage (EA)
-0.5
0.2 Vee - 0.3
V
VIH
Input High Voltage
(Except XTALl , RSn
VIHl
Input High Voltage
(XTAl1,RSn
VOL
Output Low Voltage (6)
(Ports 1, 2, 3)
0.45
V
IOL
=
1.6 rnA (1)
VOL1
Output Low Voltage (6)
(Port 0, ALE, PSEN)
0.45
V
IOL
=
3.2 rnA (1)
VOH
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
VOHl
Output High Voltage
(Port 0 in External Bus
Mode)
Min
0.2 Vee
+ 0.9
0.7 Vee
Vee
+ 0.5
V
Vee
+ 0.5
V
Test Conditions
2.4
V
IOH
=
-60 /l-A Vee
0.75 Vee
V
IOH
=
-25/1-A
0.9 Vee
V
IOH
=
-10~
2.4
V
IOH
=
-800 /l-AVee
0.75 Vee
V
IOH
=
-300/l-A
0.9 Vee
V
IOH
=
-80 /l-A (2)
IlL
Logical 0 Input Current
(Ports 1, 2, 3)
-50
/l- A
VIN
=
0.45V
ITL
Logical 1 to 0 Transition
Current (Ports 1, 2, 3)
-650
/l- A
VIN
=
2V
III
Input Leakage Current
(PortO, EA)
±10
~
0.45
150
KG
10
pF
20
5
50
rnA
rnA
",A
RRST
Reset Pulldown Resistor
CIO
Pin Capacitance
Icc
Power Supply Current:
Active Mode, 12 MHz (4)
Idle Mode, 12 MHz (4)
Power Down Mode
50
11
1.7
5
7-108
=
5V ± 10%
=
5V ±10%
< VIN < Vee
Test Freq
=
1 MHz, TA
(5)
=
25·C
infel .
80C51BHP
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 Vee
specification when the address bits are stabilizing.
3. "Typicals" are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temperature, 5V.
4. ICCMAX at other frequencies is given by
Active Mode: ICCMAX = 1.47 x FREQ + 2.35
Idle Mode: ICCMAX = 0.33 x FREQ + 1.05
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 5.
5. See Figures 6 through 9 for lee test conditions. Minimum Vee for Power Down is 2V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per Port Pin:
Maximum IOL per 8-Bit Port-
10 mA
PortO:
26mA
Ports 1,2 and 3:
15 mA
71 mA
Maximum TotaiiOL for all output pins:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
!.tAX
25 r----,----,;---....-"T1 ACTIVE !.tOOE
PO
RST
EA
TYP(3)
1---+--+F--+--7I ACTIVE !.tOOE
XTAL2
XTALI
vss
270603-7
!.tAX
IDLE !.tOOE
Figure 6. Icc Test Condition, Active Mode
All other pins are disconnected.
TYP(3)
L:~~::::±::::1::==J IDLE!.tOOE
4!.tHz
8!.tHz
12!.tHz 16!.tHz
FREQ AT XTAL 1
270603-6
Figure 5. Icc vs. Frequency
Valid only within frequency specifications of
the device under test.
XTAL2
XTALI
vss
270603-8
Figure 7. Icc Test Condition, Idle Mode
All other pins are disconnected.
7-109
80C51BHP
-------"J"'"----_
Vee·O.S
0.7 Vcc
0.4SV---'(0.2 Vcc·O.l
TCHCL
270603-9
Figure 8. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TCLCH = TCHCL= 5 ns
XTAL2
XTALI
vss
270603-10
Figure 9. Icc Test Condition, Power Down Mode. All other pins arEi disconnected. Vcc = 2V to 6V
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char·
acter is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A:
C:
D:
H:
I:
L:
Address.
Clock.
Input data.
Logic level HIGH.
Instruction (program memory contents).
Logic level LOW, or ALE.
P: PSEN.
Q: Output data.
R: RD signal.
T: Time.
V: Valid.
W:WR signal.
X: No longer a valid logic level.
Z: Float.
EXAMPLE:
TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
7·110
int:eL
80C51BHP
AC CHARACTERISTICS
(Under Operating Conditions: Load Capacitance for Port 0, ALE, and PSEN = 100 pF, Load Capacitance for
All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHzOsc
Min
1/TCLCL
Max
Oscillator Frequency
80C51 BH/80C31 BH
80C51 BH-1 180C31 BH-1
80C51 BH-2/80C31 BH-2
Variable Oscillator
Units
Min
Max
3.5
3.5
0.5
12
16
12
MHz
TLHLL
ALE Pulse Width
127
2TCLCL - 40
TAVLL
Address Valid to ALE Low
28
TCLCL - 55
ns
TLLAX
Address Hold After ALE Low
48
TCLCL - 35
ns
TLLlV
ALE Low to Valid Instr In
TLLPL
ALE Low to PSEN Low
43
TPLPH
PSEN Pulse Width
205
TPLIV
PSEN Low to Valid Instr In
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
TAVIV
Address to Valid Instr In
TPLAZ
PSEN Low to Address Float
234
ns
4TCLCL - 100
TCLCL - 40
ns
ns
3TCLCL - 45
ns
3TCLCL - 105
ns
59
TCLCL - 25
ns
312
5TCLCL - 105
ns
10
10
ns
145
0
ns
0
TRLRH
RD Pulse Width
400
6TCLCL - 100
ns
TWLWH
WR Pulse Width
400
6TCLCL - 100
ns
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
5TCLCL - 165
252
0
0
ns
ns
TRHDZ
Data Float After RD
97
2TCLCL - 70
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL - 150
ns
9TCLCL - 165
ns
TAVDV
Address to Valid Data In
TLLWL
ALE Low to RD or WR Low
200
TAVWL
Address Valid to RD or WR Low
203
4TCLCL - 130
ns
TQVWX
Data Valid to WR Transition
23
TCLCL - 60
ns
TWHQX
Data Hold After WR
33
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
585
300
3TCLCL - 50
7-111
+
50
TCLCL - 50
0
43
3TCLCL
123
ns
0
TCLCL - 40
ns
TCLCL
ns
+ 40
ns
intel .
80C51BHP
EXTERNAL DATA MEMORY READ CYCLE
TWHLH
ALE
I------TLLDV----
--TLLWL-- - - - - - T R L R H - + - - - - I
iiii
.-
-TRlAZ
PORTO
------TAVDV-------
AI-A 15 FROM peH
P2.0·P2.7 OR Aa-AfS FROM DPH
PORT 2
270603-11
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
-TAYLl- - - - - - T P L P H - - -
TLLPl
TLLlY
TPXIZ\--
TLUX
-TPLAZ
PORTO
TP•• I -
-
INSTA
IN
Af-A15
PORT.
270603-12
7·112
int'el..
80C51BHP
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE
JIftii
--TLLWL-I
TWLWH
\iii
TOVWI
~
PORTO
PORT 2
TWHOI
..L
DATA OUT
P2.0 - P2.7 OR AI - A15 FROM DPH
INSTR
IN
AI - A15 FROM PCH
270603-13
7-113
infel·
80C51BHP
.... i•
..
o
I
Shift Register Mode Timing Waveforms
. 7-114
int:eL
80C51BHP
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
80C51BHP
80C51BHP-1
80C51BHP-2
3.5
3.5
0.5
12
16
12
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
MHz
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
SERIAL TIMING-SHIFT REGISTER MODE
Test Conditions: T A
Symbol
=
O°C to 70°C; Vee
=
5V ± 20%; VSS
=
OV; Load Capacitance
12 MHzOsc
Parameter
Min
80 pF
Variable Oscillator
Min
Units
Max
1.0
12TCLCL
700
10TCLCL - 133
ns
TXHOX Output Data Hold After Clock Rising Edge
50
2TCLCL - 117
ns
TXHDX Input Data Hold After Clock Rising Edge
0
TXLXL
Serial Port Clock Cycle Time
Max
=
TOVXH Output Data Setup to Clock Rising Edge
,..,s
ns
0
TXHDV Clock Rising Edge to Input Data Valid
10TCLCL - 133
700
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270603-15
AC TESTING INPUT, OUTPUT WAVEFORMS
V C c - o . s - y 0.2 VCC+0.9
0.45 V
FLOAT WAVEFORMS
V-J1L
TIMING REFERENCE
POINTS
-A_0_.2_V-=C~C_-_0._1_ _ _
VOL +0.1 V
270603-17
270603-16
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOL/IOH <: ± 20 mA.
AC Inputs during testing are driven at Vee - 0.5 for a logic "1"
and 0.45 V for a logic "0". Timing measurements are made at VIH
min. for a logic "1" and VIL max. for a logic "0".
7-115
intel'"
80C51BHP
DATA SHEET REVISION HISTORY
The following is the key difference between this and the -003 version of the 80C51 BHP data sheet:
Data sheet title was changed from:
80C51 BHPCHMOS Single-Chip 8-Bit Microcomputer with Protected ROM
to:
80C51 BHP CHMOS Single-Chip 8-Bit Microcontroller with Protected ROM
The following are the key differences between the -003 and the -002 version of the 80C51 BHP data sheet:
1. Data sheet status changed from "Preliminary" to "Production".
2. Revised Maximum Ratings Warning and Data Sheet Status Notice.
3. ONCE Mode feature added.
The following are the key differences between the -002 and the -001 version of the 80C51 BHP data sheet:
1. Package Table was added.
2. Note 6 on Maximum Current Specifications was added to DC Characteristics.
3. Data Sheet Revision History was added.
7-116
87C51/80C51 BH/80C31 BH
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 4 KBYTES INTERNAL PROGRAM MEMORY
S7C51/S0C51BH/SOC31BH-3.5 to 12 MHz, Vee = 5V ±20%
S7C51-1/S0C51BH-1/S0C31BH-1-3.5 to 16 MHz, Vee = 5V ±20%
S7C51-2/S0C51BH-2/S0C31BH-2-0.5 to 12 MHz, Vee = 5V ± 20%
S7C51-L-3.5 MHz to S MHz, Vee = 3.3V ±O.3V
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
Low Voltage Operation (-L Only)
Improved Quick-Pulse Programming
Algorithm
3-Level Program Memory Lock
Boolean Processor
12S-Byte Data RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
•
•
•
•
•
•
•
•
5 Interrupt Sources
Programmable Serial Port
TTL- and CMOS-Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
Idle and Power Down Modes
ONCE Mode Facilitates System Testing
Power Control Modes
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31 BH). In
addition the device can address up to 64K of program memory external to the chip. .
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51 is a single-chip control-oriented microcontrolier which is fabricated on Intel's reliable CHMOS
III-E technology. The Intel 80C51 BH/80C31 BH is fabricated on CHMOS III technology. Being a member of the
MCS®-51 family, the 87C51 /80C51 BH/80C31 BH uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of products.
Applications that require low voltage can use the 87C51-L. The 87C51-L will. operate at 3.3V ± O.3V at a
frequency range of 3.5 MHz to 8 MHz.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
For the remainder of this document, the 87C51, 80C51 BH, and 80C31 BH will be referred to as the 87C51 /BH,
unless information applies to a specific device.
7-117
October 1992
Order Number: 270147-008
87C51/80C51 BH/80C31 BH
P2.0-P2.7
PSEN
A~
RST·
TIMING
AND
: : CONTROL
z
~
ei
g~ljL__~~__~~____________~'-__-L~______~
~~
I
270147-1
Figure 1. 87C51/BH Block Diagram
PROCESS INFORMATION
The 87C51 is manufactured on P629.0, a CHMOS
III-E process. The 80C51 BH/80C31 BH are manufactured on P645, a CHMOS III process. Additional
process and reliability information is available in
Intel's Components Quality and Reliability Handbook, Order Number 210997.
7-118
infel .
87C51/80C51BH/80C31BH
PACKAGES
Part
Prefix
Package Type
lila
IIle
Part
Prefix
Package Type
lila
IIle
87C51
P
40-Pin Plastic
DIP (OTP)
40-Pin CERDIP
(EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
45'C/W
16'C/W
80C51BHI
80C31BH
45'C/W
15'C/W
P
D
N
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-PinQFP
75'C/W
36'C/W
46'C/W
98'C/W
23'C/W
13'C/W
16'C/W
24'C/W
46'C/W
9S'C/W
16'C/W
24'C/W
D
N
S
S
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
fl
. . . ~~
Pl.D
Vee
Pl.l
PO.O (ADO)
Pl.2
PO.l (A01)
Pl.3
PO.2 (A02)
Pl.~
PO.3 (A03)
Pl.5
Pl.5
PO.~ (AO~)
Pl.6
PO.5
P1.6
PO.5 (A05)
Pl.7
PO.6
Pl.7
PO.6 (A06)
RST
RESET
PO.7 (A07)
P3.0
.,
~ '"a:
INDEX
CORNER
0
"
~
0
>" ..
N
.,
~ ~ ~
PO ••
PO.7
IT
87C51/BH
RESERVED'
(RXO) P3.0
EA
(TXO) P3.1
ALE
P3.1
ALE
(INTO) P3.2
PSEii
P3.2
PsEN
(iNri) P3.3
P2.7
RESERVED'
(A15)
P3.3
P2.7
P3.~
P2.6 (AU)
P3.4
P2.6
(T1) P3.5
P2.5 (A 13)
P3.5
P2.S
(TO)
(Wii)
(Rii)
P3.6
P2.~
(A12)
P3.7
P2.3 (All)
XTAL2
P2.2 (Al0)
XTAL1
P2.1
..
.,~
(A9)
~
~
'"
. . . ..., ...
",0
>
~
0
"l
N N
N N
~
~
P2.0 (AB)
Vss
.... N
,,; ~
270147-21
PLCC
270147-2
DIP
.~
0
INDEX
CORNER \
. . .. . . ~
"": "! C'! --:
~
"
~
0
>" ..
N
.,
~ ~ ~
270147-22
'Do not connect reserved pins.
QFP
Figure 2. Pin Connections
7-119
87C51/80C51 BH/80C31 BH
PIN -DESCRIPTION
Vee: Supply voltage during normal, Idle and Power
Down operations.
Vss: Circuit ground.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TTL
inputs. Port 0 pins that have 1's written to them float,
and in that state can be used as high-impedance
inputs.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port 0 is also the multiplexed· low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emitting 1's.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
Port 1 also receives the low-order address bytes
during EPROM programming and program verification.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pull ups. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX @DPTR). In this application it uses
strong internal pullups when emitting 1'so
During accesses to external Data Memory that use
8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Pin
Name
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD
TXD
INTO
INT1
TO
T1
WR
RD
Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
I:xternal Data Memory Write strobe
External Data Memory Read strobe
Port- 3 also receives some control' signals for
EPROM programming and program verification.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not (87C51 only). An
internal pulldown resistor permits a power-on reset
with only a capacitor connected to Vee.
ALE/PROG: Address Latch Enable output signal for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or Movc instruction.
Otherwise the pin is weakly pulled high. Setting the
ALE-disable bit has no effect if the microcontroller is
in external execution mode.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
PSEN: Program Store Enable is the Read strobe to
External Program Memory. When the 87C51/SH is
executing from Internal Program Memory, PSEN is
inactive (high). When the device is executing code
from External Program Memory, PSEN is activated
7-120
87C51/80C51 BH/80C31 BH
twice each machine cycle, except that two PSEN
activations are skipped during each access to External Data Memory.
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the 87C51 IBH to
fetch code from External Program Memory locations
starting at OOOOH up to FFFFH. Note, however, that
if either of the Lock Bits is programmed, the logic
level at EA is internally latched during reset.
EA must be strapped to Vcc for internal program
execution.
This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock Signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the data
sheet must be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external Signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active.' The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hardware reset.
XTAL 1
+------1 Vss
270147-3
Figure 3. Using the On-Chip Oscillator
NC
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.
IDLE MODE
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
OSCILLATOR CHARACTERISTICS
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm
takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that
invokes .Idle should not be one that writes to a port
pin or to external memory.
XTAL2
XTAL 1
Vss
270147-4
Figure 4. External Clock Drive
Table 1. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
Idle
External
1
Power Down
Internal
0
0
Data
Power Down
External
0
0
Float
Mode
PORTO
PORT1
PORT2
PORT3
1
Data
1
Float
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "DeSigning with the 80C51 BH."
7-121
87C51/80C51 BH/80C31 BH
• The 87C51 has some additional features that are
not available on the 80C51BH/80C31BH. The
features are: asynchronous port reset, 4 interrupt
priority levels, power off flag, ALE disable, serial
port automatic address recognition, serial port
framing error detection, 64-byte encryption array,
and 3 program lock bits. These features cannot
be used with the 80C51BH/80C31BH.
POWER DOWN MODE
In the Power Down'mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.
The only exit from Power Down is a hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before Vee is restored to its normal operating leveland
must be held active long enough to allow the oscillator to restart and stabilize.
DESIGN CONSIDERATIONS
• The 87C51-L will operate at 3.3V ± O.3V at a frequency range of 3.5 MHz to 8 MHz. Operating
beyond these specifications 'could cause improper device functionality. (To program the 87C51-L,
follow the same procedure as the 87C51.)
• Exposure to light when the device is in operation
may cause logiC errors. For this reason, it is suggested that an opaque label be placed over the
window when the die is exposed to ambient light.
ONCE MODE
The ONCE ("On-Circuit Emulation") mode facilitates
testing and debugging of systems using the
87C51/BH without the 87C51/BH having to be removed from the circuit. The ONCE mode is invoked
by:
1. Pull ALE low while the device is in reset and
, PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 87C51BH is in this mode, an emulator
or test CPU can be used to drive the circuit. Normal .
operation is restored when a normal reset is applied.
7-122
intel .
87C51/80C51 BH/80C31 BH
ABSOLUTE MAXIMUM RATINGS·
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias. -40·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to + 6.5V
Maximum IOL per I/O Pin .......•.......... 15 rnA
Power Dissipation ........•................. 1.5W
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
(Based on package heat transfer limitations, not device power consumption).
OPERATING CONDITIONS
= O·C to +70·C; Vee =
TA (under Bias)
5V ±20%; Vss
=
OV (87C51-L, Vee
=
3.3V ±0.3V)
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol
Parameter
Max
Unit
-0.5
Min
Typ(1)
VIL
Input Low Voltage
0.2 Vee - 0.1
V
VIL1
Input Low Voltage EA
0
0.2 Vee - 0.3
V
VIH
Input High Voltage
(Except XTAL1, RST)
0.2 Vee + 0.9
Vee + 0.5
V
VIH1
Input High Voltage
(XTAL 1, RST)
0.7 Vee
Vee + 0.5
V
VOL
Output Low Voltage(6)
(Ports 1, 2, 3)
0.3
V
VOL1
VOH
VOH
VOH1
VOH1
Output Low Voltage(6)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
87C51
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
80C51 BH/31 BH
Output High Voltage
(Port 0 in External Bus Mode)
87C51
Output High Voltage
(Port 0 in External Bus Mode)
80C51 BH/31 BH
0.45
V
1.0
V
0.3
V
0.45
V
1.0
V
Vee - 0.3
V
Vee - 0.7
V
Vee - 1.5
V
0.9 Vee
V
0.75 Vee
V
2.4
V
Vee - 0.3
V
Vee - 0.7
V
Vee - 1.5
V
Test Conditions
= 100 /LA(2)
IOL = 1.S mA(2)
IOL = 3.5 mA(2)
IOL = 200 /LA(2)
IOL = 3.2 rnA (2)
IOL = 7.0 mA(2)
IOH = -10/LA(3)
IOH = -30/LA(3)
IOH = -SO /LA(3)
IOH = -10 /LA(3)
Vee = 5V ±10%
IOH = -25/LA
IOH = -SO /LA(3)
IOH = -200/LA(3)
IOH = -3.2 mA(3)
IOH = -7.0 mA(3)
IOL
V
IOH = -80/LA
Vee = 5V ±10%
0.75 Vee
V
IOH
2.4
V
IOH
0.9 Vee
7-123
= = -
300 /LA
800 /LA
S7C511S0C51BH/SOC31BH
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
Symbol
Max
Unit
IlL
Logical 0 Input Current
(Ports 1, 2, 3)
Parameter
-50
p.A
VIN
VIN
III
Input Leakage Current
(Port 0)
±10
PA
0.45
ITL
LogicaI1-to-0 Transition Current
(Ports 1, 2, 3)
-650
p.A
VIN
RRST
RST Pull down Resistor
300
Kn
Cia
Pin Capacitance
Icc
Power Supply Current
Active Mode
87C51-L at 8 MHz
All Others at 12 MHz(4)
Idle Mode @ 12 MHz(4)
Power Down Mode
Min
Typ(1)
50
pF
10
Test Conditions
@
=
=
2V (87C51)
0.45V
< VIN < Vcc
=
2V
1 MHz,25°C
(Note 5)
12
20
5
50
11.5
1.7
5
rnA
rnA
rnA
p.A
NOTES:
1. ''Typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.SV. It may be desirable to qualify ALE or other Signals with a Schmitt Trigger, or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the address bits are stabilizing.
4. IccMAX at other frequencies is given by:
Active Mode: IccMAX = 0.94
Idle Mode:
IccMAX = 0.14
x FREQ
x FREQ
+
+
13.71
2.31
• where FREQ is the external oscillator frequency in MHz. IccMAX is given in mAo See Figure 5.
5. See Figures 6 through 9 for ICC test conditions. Minimum Vcc for Power Down is 2V.
6. Under'steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per 8-bit portPortO:
26 mA
Ports 1, 2, and 3:
15 mA
Maximum totallOL for all output pins:
71 rnA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
7-124
intel~
87C51/80C51BH/80C31BH
MAX
ACTIVE MODE
TYP(l)
«
E
h~-+--l---+-------,I ACTIVE MODE
270147-18
(j
S!
Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.
f---+.~-+---+----I
MAX
__......- - 1 IDLE MODE
L~:::::::::b:::::±==t=J IDLE MODE
TYP(l)
4MHz
8MHz
12MHz
16MHz
FREQ AT XTAL 1
270147-16
Figure 5. Icc vs. FREQ. Valid only
within frequency specifications of the
device under test.
(NC)
XTAL2
XTAL1
Vss
270147-20
Figure 9. Icc Test Condition, Power Down
Mode. All other pins are disconnected.
Vcc = 2V to 5.5V.
XTAL2
XTALl
vss
270147-17
Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.
Vee-O.5 • - - - - - -.~~---0.7 Vee
O.45V --.JiO.2 Yee-O.l
TCHCL
270147-19
Figure 8. Clock Signal Waveform for Icc tests in Active and Idle Modes.
TCLCH = TCHCL = 5 ns.
7-125
87C51/80C51 BH/80C31 BH
L:Logic level LOW, or ALE.
EXPLANATION OF THE 'AC SYMBOLS
P:PSEN.
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
Q:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No.longer a valid logic level.
A:Address.
C:Clock.
D:lnput data.
Z:Float.
For example,
H:Logic level HIGH.
1:lnstruction (program memory contents).
TAVLL = Time from Address Valid to ALE Low.
TLLPL = Time from ALE Low to PSEN Low.
AC CHARACTERISTICS: (Over Operating Conditions; Load Capacitance for Port 0, ALE, and
PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
1/TCLCL
Parameter
12 MHz Oscillator
Min
Max
Oscillator Frequency
87C51/BH
87C51-1/BH-1
87C51-2/BH-2
Variable Oscillator
Min
Max
3.5
3.5
0.5
12
16
12
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
87C51
80C51 BH/C31 BH
43
28
TCLCL-40
TCLCL-55
ns
ns
Address Hold After ALE Low
87C51
80C51BH/C31BH
53
48
TCLCL-30
TCLCL-35
ns
ns
TLLAX
4TCLCL-100
TLLlV
ALE Low to Valid Instr In
TLLPL
ALE Low to PSEN Low
87C51
80C51 BH/C31 BH
53
43
TCLCL-30
TCLCL-40
ns
ns
TPLPH
PSEN Pulse Width
205
3TCLCL-45
ns
TPLIV
PSEN Low to Valid Instr In
TPXIX
Input Instr Hold After PSEN
TPXIZ
Input Instr Float After PSEN
59
TCLCL-25
ns
TAVIV
Address to Valid Instr In
312
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
TRLRH
RD Pulse Width
400
400
TWLWH
WR Pulse Width
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD .
234
145
0
3TCLCL-105
0
ns
6TCLCL-100
0
7-126
ns
5TCLCL-165
0
ns
ns
6TCLCL-100
252
ns
ns
ns
87C51/80C51 BH/80C31 BH
EXTERNAL MEMORY CHARACTERISTICS (Continued)
Symbol
TAHDZ
Parameter
12 MHz Oscillator
Min
Max
Variable Oscillator
Min
Units
Max
Data Float After AD
87C51
80C51 BH/C31 BH
107
97
TLLDV
ALE Low to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE Low to AD or WA Low
200
TAVWL
Address to AD or WA Low
203
4TCLCL-130
ns
TOVWX
Data Valid to WA Transition
87C51
80C51 BH/C31 BH
33
23
TCLCL-50
TCLCL-60
ns
ns
Data Hold After WA
33
TCLCL-50
ns
TWHOX
TALAZ
AD Low to Address Float
TWHLH
AD or WA High to ALE High
2TCLCL-60
2TCLCL-70
ns
ns
517
8TCLCL-150
ns
585
9TCLCL-165
ns
300
3TCLCL-50
3TCLCL+50
0
43
123
TCLCL-40
ns
0
ns
TCLCL+40
ns
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
_--J
Pm!
_ _. I
PORT 0__--,
PORT 2----'
A8-A15
270147-5
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
TAVWL TAVDV
PORTO===~~~F~RO~W~R~IO~R~D~PL~~~~t::::::::f========~~========::~~1N=ST=R=.I=N
PORT2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
270147-6
7-127
intel .
87C51/80C51 BH/80C31 BH
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
PSEN
--i----
PORTO
PORT2
,
TWLWH - - - - I
INSTR. IN
DATA OUT
__-J~____________________________- J
P2.0-P2.7 OR A8-A15 fROM DPH
A8-A15 fROM PCH
270147-7
EXTERNAL CLOCK DRIVE
Symbol
Parameter
EXTERNAL CLOCK DRIVE WAVEFORM
Min Max Units
1/TCLCL Oscillator Frequency
87C51/BH
3.5
87C51-1/BH-1
3.5
~7C51-2/BH-2
0.5
12
16
12
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
270147-8
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol
Parameter
12 MHz
OSCillator
Min
TXLXL
Serial Port Clock Cycle Time
TOVXH Output Data Setup to Clock Rising Edge
Max
Variable Oscillator
Min
Units
Max
1.0
12TCLCL
,...s
700
10TCLCL-133
ns
TXHOX Output Data Hold After Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock Rising Edge
0
TXHDV
Clock Rising Edge to Input Data Valid
0
700
7-128
ns
1OTCLCL -133
ns
intel·
87C51/80C51 BH/80C31 BH
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
2
5
ALE
CLOCK
OUTPUT DATA
t
WRITE TO S8UF
INPUT DATA -------.,r..~.r~~
I
SET TI
':":"7:'r-\r.~v---'.r..~.r.......~~~"""",~~r-.....r.777~"'-~!":':":"~
t
I
CLEAR RI
SET RI
270147-9
AC TESTING INPUT, OUTPUT WAVEFORMS
Vee-0.5
0.45 V
=x
0.2Vee+0.9
FLOAT WAVEFORMS
><=
, - - - - - - - - " ' vOH-o., v
0.2Vee-0.l
;..........;;.;;....-----
' _ _ _ _ _ _ _ _J
VOL +0.1 V
270147-11
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ~ ±20 mA. (-L, IOlliOH ~ ± 10 mAl
270147-10
AC inputs during testing are driven at Vee - 0.5 for a Logic "1"
and 0.45V for a Logic "0." Timing measurements are made at VIH
min for a Logic "1" and VIL max for a Logic "0".
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz· to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address Jines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig~until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 respectively for AO-A14.
DATA LINES: PO.0-PO.7 for DO-D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.6,
P3.7.
PROGRAM SIGNALS: ALE/PROG, EAlVpp.
NOTE:
• Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
• Programming specifications for the 87C51-L are
the same as the standard 87C51.
7-129
87C51/80C51BH/80C31BH
Table 2. EPROM Programming Modes
Mode
RST
.
PSEN
ALEI
PROG
EAI
Vpp
P2.6
P2.7
P3.6
P3.7
-U-
12.75V
L
H
H
H
Program Code Data
H
L
Verify Code Data
H
L
H
H
L
L.
H
H
Program Encryption
Array Address 0-3F
H
L
-U-
12.75V
L
H
L
H
Bit 1
H
L
-U-
12.75V
H
H
H
H
Bit 2
H
L
-U-
12.75V
H
H
L
L
Bit 3
H
L
-U-
12.75V.
H
L
H
L
H
L
H
H
L
L
L
L
Program Lock Bits
Read Signature Byte
+5V
87C5'
AO-A7
PI
A8_-AI-,-""'·P2.0P2.3
POM DATA
EA/Vpp
ALE/PROG 1 - _ _
} PROGRAM
SIGNALS
PSENI---
P2.71---P2.1I1--CONTROl. SIGNALS
P3.71---
P3.SI---RSTI---270147-12
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
7-130
int:eL
87C51/80C51 BH/80C31 BH
ADDRESS
X
X
X
DATA
CDNTROL
SIGNALS
12.7SV
EA/Vpp
SV
X
12 BITS
X
X
8 BITS
7 BITS
..J
'-
TGLGH
ALE/PROG
270147-13
'For compatibility. 25 pulses may be used.
Figure 11. Programming Waveforms
PROGRAMMING ALGORITHM
EPROM Lock System
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times' for the EPROM array,
and 25 times for the encryption table and the lock
bits.
The 87C51 program lock system, when programmed, protects the onboard program against
software piracy.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
Program Verify
Verification may be done after programming either
one byte or a block of bytes. In either case a complete verify of the array will ensure reliable programming of the 87C51.
The 87C51 has a 3-level program lock system and a
64-byte encryption array. Since this is an EPROM
device, all locations are user-programmable. See
Table 3.
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in its
original, unmodified form. For programming the Encryption Array, refer to Table 2 (Programming the
EPROM).
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
7-131
When using the encryption array, one important factor needs to be considered. If a code byte has the
value OFFH, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be programmed with some value other than OFFH, and not
all of them the same value. This will ensure maximum program protection.
int:eL
87C51/80C51BH/80C31BH
Program Lock Bits
The 87C51 has 3 programmable lock bits that when
programmed according to Table 3 will provide different levels of protection for the on-chip code and
data.
Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 87C51 has 3 signature bytes in locations 30H,
31 H, and 60H. To read these bytes follow the procedure for EPROM verify, but activate the control lines
provided in Table 2 for Read Signature Byte.
Contents
Location
87C51
30H
89H
31H
58H
60H
51H
Erasure Characteristics
(Windowed Devices Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1's state.
Table 3. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. (Code verify will still be encrypted by the
encryption array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
7-132
87C51/80C51 BH/80C31 BH
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA = 21°C to 27°C,
vee
Symbol
= 5V ±10%, VSS = OV)
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
rnA
1/TCLCL
Oscillator Frequency
6
MHz
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold After PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold After PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to. Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
TGHSL
Vpp Hold After PROG
10
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float After ENABLE
0
TGHGL
PROG High to PROG Low
10
4
Units
/Jos
/Jos
110
/JoS
48TCLCL
/JoS
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING·
P1.0-P1.7
P2.0-P2.3
VERIFlcAnoN·
-----{==!Ao~O~R~ES~S==)_------{==A~D~DR~E!SS~=>-----TAVQV
PORTO-----t<=:J~~=~t_-------_t!D~AT~AJO~U~T=)_-----ALE/PROG
------'"li
"EA/Vpp - - - -
LOGIC 1
LOGIC 1
LOGIC 0
TEHQZ
P2.7
(ENABLE) _ _ _"
270147-15
·For programming conditions see Figure 10.
··5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
7-133
87C51/80C51 BH/80C31 BH
DATA SHEET REVISION HISTORY
This data sheet (271047-008) is valid for devices with an "A" at the end of the topside tracking number. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
'
The following differences exist between this data sheet (271047-008) and the previous version (271047-007):
1. The 80C51 BH/80C31 BH CHMOS Single-Chip 8-Bit Microcomputer data sheet (270064-008) has been
combined with the 87C51 CHMOS Single-Chip 8-Bit Microcontroller with 4 Kbytes of EPROM Program
Memory data sheet (271047-001) to create this new data sheet.
2. 80C51 BH/80C31 BH specs have been added to the Package Table, DC Characteristics Table and AC
Characteristics Table.
3. Added 3.3V device to data sheet.
4. EPROM Programming Information has been added.
5. The Operating Temperature Range has been changed to: O·C to
+ 70·C.
The following are the key differences between the -007 and the -006 versions of the 87C51 data sheet.
1. Pins labeled "NC" and "VSS1" changed to "Reserved" in Figure 2.
2. Bja and Bjc specifications added to "Packages" table.
3. VSS1 pin description deleted.
4. Capacitor values for ceramic resonators deleted from Figure 3.
5. Second paragraph added to "Encrypted Verify" under "Program Memory Lock" section.
6. All pin numbers and the P3.3 control line deleted from Figure 10.
The following differences exist between the -006 and the -005 versions of the 87C51 data sheet:
1. Technology changed from CHMOS II-E to CHMOS III-E.
2. QFP package offering added.
3. Asynchronous Reset added.
4. ALE disable added.
5. Program Memory Lock feature changes:
-
Third lock bit added
-
Encryption array enhanced to 64 bytes
6. Data sheet status notice and Absolute Maximum Ratings warning revised.
7. DC Characteristics changes:
= 100 /A-A, 1.0V @ IOL = 3.5 mA).
= 200 /A-A, 1.0V @ IOL = 7.0 mA).
IOH = -60 /A-A, 0.75 Vee @ IOH = -25 /A-A, and 0.9 Vee
-
Additional VOL entriesadded (0.3V
-
Additional VOL1 entries added (0.3V
-
VOH entries changed from 2.4V
-10 /A-A to the current values.
-
VOH1 entries changed from 2.4V @ IOH = -800 /A-A. 0.75 Vee
= - 80 /A-A to the current values.
@
@
IOL
@
IOL
@
IOH = -300 /A-A, and 0.9 Vee
-
RRST changed from 50 Kn min and 300 Kn max to the current values.
-
CIO changed from 10 pF max to 10 pF typical
8. Note 2 reworded (ALE noise pulses).
9. Note 4 deleted (transition current sourcing).
7-134
@
IOH =
@
IOH
intet
87C51/80C51BH/80C31BH
DATA SHEET REVISION HISTORY (Continued)
10. AC Timings improved for:
T AVLL changed from TCLCL - 55 to TCLCL - 40
TLLAX changed from TCLCL-35 to TCLCL-30
TLLPL changed from TCLCL - 40 to TCLCL - 30
TRHDZ changed from 2 TCLCL-70 to 2 TCLCL-60
TaVWX changed from TCLCL-60 to TCLCL-50
11. EPROM programming control line (P3.3) added to Figure 10.
12. Programming Algorithm paragraph reworded to describe programming changes.
13. Figure 11 changed to show 5 programming pulses rather than 25.
14. Figure 12 deleted (Program Verification).
15. Program Verification paragraph reworded.
16. Third signature byte added; location and definition included.
17. ProgramlVerify Algorithms paragraph deleted.
18. Ipp programming spec changed from 50 mA to 75 mA.
The following are the key differences between -005 and the -004 versions of the 87C51 data sheet:
1. Package table was added.
2. Note 7 on maximum current specifications added to DC Characteristics.
3. Data Sheet Revision Summary was added.
7-135
87C51
EXPRESS
•
Extended Temperature Range
•
Burn-In
•
3.5 MHz to 12 MHz Vee = 5V ± 10%
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125·C with Vee
guidelines in MIL-STD-883, Method 1015.
=
6.9V ±0.25V, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
7-136
September 1988
Order Number: 270430-002
int'eL
87C51 EXPRESS
Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
.
D.C. CHARACTERISTICS
Symbol
TA
=
-40°C to
+ 85°C; Vee =
5V ± 10%; VSS
=
OV
Limits
Parameter
VIL
Input Low Voltage (Except EA)
VIL1
EA
VIH
Input High Voltage (Except XTAL 1, RST)
VIH1
Input High Voltage to XTAL 1, RST
Unit
Min
Max
-0.5
0.2Vee - 0.15
V
0
0.2Vee - 0.35
V
+1
+ 0.1
0.2Vee
0.7Vee
Vee
Vee
+ 0.5
+ 0.5
Test
Conditions
V
V
IlL
Logical 0 Input Current (Port 1,2; 3)
-75
p.A
VIN
ITL
Logical 1 to 0 transition
Current (Ports 1, 2, 3)
-750
p.A
VIN
ICC
Power Supply Current
Active Mode
Idle Mode
Power Down Mode
35
mA
mA
p.A
=
=
0.45V
2.0V
(Note 1)
6
50
NOTE:
1. Vce = 4.5V-5.5V, Frequency Range = 3.5 MHz-12 MHz.
7-137
iniaL
87C51 EXPRESS
Table 1 Prefix Identification
Package Type
Temperature Range(2)
Burn-ln(3)
P
Plastic
Commercial
No
D
Cerdip
Commercial
No
Prefix
N
PLCC
Commercial
No
TP
Plastic
Extended
No
TO
Cerdip
Extended
No
TN
PLCC
Extended
No
OP
Plastic
Commercial
Yes
aD
Cerdip
Commercial
Yes
ON
PLCC
Commercial
Yes
LP
Plastic
Extended
Yes
LD
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
NOTES:
2. CommerCial temperature range is O·C to + 70·C. Extended temperature range is - 40·C to + 85·C.
3. Burn-in is dynamic for a minimum time of 160 hours at + 125·C, Vee = 6.9V ±0.25V, following guidelines in MIL-STD883 Method 1015 (Test Condition D).
Examples:
P87C51 indicates 87C51 in a plastic package and specified for commercial temperature range, without burn-in.
LD87C51 indicates 87C51 in a cerdip package and specified for extended temperature range with burn-in.
7-138
87CS1-20/-3
COMMERCIAL/EXPRESS
20 MHz CHMOS MICROCONTROLLER
87C51-2o-3.5 to 20 MHz, Vee = 5V ± 20%
87C51-3-24 MHz Internal Operation, Vee = 5V ± 20%
•
•
•
High Performance CHMOS EPROM
24 MHz Internal Operation (-3 only)
Improved Quick-Pulse Programming
Algorithm
iI 3-Level Program Memory Lock
•
•
•
•
•
Boolean Processor
128-Byte Data RAM
32 Programmable I/O Lines
•
•
•
•
•
•
Programmable Serial Channel
TTL- and CMOS-Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
IDLE and POWER DOWN Modes
ONCE Mode Facilitates System Testing
Two 16-Bit Timer/Counters
5 Interrupt Sources
The B7C51-20 is the EPROM version of the BOC51 BH. It is fabricated on Intel's CHMOS III-E process. It
contains 4 Kbytes of on-chip Program memory that can be electrically programmed, and can be erased by
exposure to ultraviolet light.
The B7C51-20 EPROM array uses an improved Quick-Pulse programming algorithm, by which the entire 4
Kbyte array can be programmed in less than 3 seconds.
The B7C51-3 has the same 3.5 MHz to 20 MHz frequency range as the B7C51-20 when operating out of
external program/data memory. When running out of internal program/data memory, the B7C51-3 can operate
up to 24 MHz.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
Throughout this document B7C51-20 will refer to both the B7C51-20 and the B7C51-3.
7-139
September 1992
Order Number: 272082-002
inteL
87C51-20/-3
PO.O-PO.7
---,
PSEN
A~.....,..
TlhllNG
AND
RST ......... CONTROL
I
I
I
---.I
P1.0-P1.7
P3.0 - P3.7
272082-1
Figure 1. 87C51-20 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Compo'lents Quality
and Reliability Handbook, Order Number 210997.
7-140
intel .
87C51-20/-3
PACKAGES
Part
Prefix
Package Type
8JA
8JC
87C51-20
P
D
N
S
40-Pin Plastic DIP (OTP)
40-Pin CERDIP (EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
45°C/W
45°C/W
46°C/W
98°C/W
16°C/W
15°C/W
16°C/W
24°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
"': "! "!
INDEX
CORNER
0:: 0:: 0::
"!
!
..
0
"!
... ... &= ~ .;... .;... .;... ...
0
Pl.S
PO.4
Pl.6
PO.S
Pl.7
PO.S
RST
PO.7
Vi/vpp
P3.0
R... rved·
Reserved-
Pl.0
P3.1
ALE/PROO
P3.2
PsEii
Pl.l
Vee
PO.O (ADO)
P1.2
PO.l (AD1)
P3.3
P2.7
P1.3
PO.2 (AD2)
P3.4
P2.G
P1.4
PO.3 (AD3)
P3.5
P2.S
Pl.S
PO.4 (AD4)
P1.6
PO.S (ADS)
Pl.7
PO.6 (AD6)
-
N
JII')
.....
N N 0..
N a..
N
a.. a..
PO.7 (AD7)
RESET
(RXD) P3.0
EA/Vpp
(TXD) P3.1
ALE/PROO
272082-3
(iNfO) P3.2
PSEN
(iNIT) P3.3
P2.7 (A1S)
(TO) P3.4
P2.6 (AI4)
(Tl) P3.S
P2.S· (AI3)
(ViR) P3.6
P2.4 (AI2)
(iiii) P3.7
P2.3 (All)
XTAL2
P2.2 (Ala)
XTALI
P2.1 (A9)
Vss
P2.0 (A8)
272082-2
DIP
PLCC
.
"ll
INDEX
CORNER,
~
"':,,!,,!,,:,,!:
~ ~ ~ ~ ~
0
0
-
..
..,
& ~f f f f
.~~~~!~~:~~~~:~~!~=!!~~:~~~~~~
Pl.S
Pl.6
Pl.7
RST
C!
(!
(!
(!
P3.0 S:!
Reserved- (}
1;[2
po.s
1~) PO.6
1;(0
87C51-20
P3.1 7:!
P3.2
"
1;[3 PO.4
PO.7
1(9 EA/Vpp
Re.erved-
Lia
1{l ALE/PROO
Lt6 PSEN
1tS P2.7
s:!
P3.3 ( !
P3.4 1] ~
i))
P3.S lj!
P2.6
1t3 P2.S
.~~ ~~ ::~ :~~ :-~~ :~~ :~~ :~~ ~~ :-~~ :~~.
272082-4
QFP
°00 not connect reserved pins.
Figure 2. Pin Connections
7-141
intel·
87C51·20/~3
PIN DESCRIPTIONS
Symbol
Vee
Name and Function
Main supply voltage (5V).
Vss
Circuit ground.
PortO
8-bit, open drain, bidirectional 110 port. These pins are shared with the multiplexed
address/data bus which has strong internal pullups. Port 0 also receives the code bytes
during EPROM programming, and outputs the code bytes during verification. When used as
an I/O port, pullups to Vee may be needed.
Port 1
8-bit bidirectional I/O port. All of the port 1 pins are shared with other functions in the
87C51-20. Port 1 is also used as the low-order address byte input during EPROM
programming.
'
Port 2
8-bit bidirectional I/O port. Port 2 also emits the high-order address byte during accesses to
1S-bit external memory locations. Some of the Port 2 pins are also used as address bits for
EPROM programming.
.
Port 3
8-bit bidirectional I/O port. All of the port 3 pins are sharEld with other functions in the
87C51-20. Two of the pins are u~ed as control lines (RD, WR) for accessing external RAM.
RESET
Reset input to the chip. A high Input for a minimum of two machine cycles with the oscillator
running resets the device. The port pins will be reset when a voltage above VIH is applied
whether the oscillator is running or not. RST has an internal pulldown.
ALE/PROG
Address Latch Enable. Provides a signal to demultiplex the address from the address/data
bus. In normal operation ALE is emitted at a constant rate of 1/S the oscillator frequency.
Note, however, that one ALE pulse is skipped during each access to external data memory.
If desired, ALE can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode. This pin is also the program pulse input during EPROM programming.
PSEN
Program Store Enable. Acts as read strobe for external program memory fetches.
EAlVpp
External Access Enable. EA must be strapped to Vss in order to enable the device to fetch
code from external program memory locations OOOOH to OFFFFH. EA should be strapped
to Vee for internal program executions. If any of the lock bits are programmed, EA will be
internally latched on reset. This pin also receives the programming supply voltage (Vpp)
during EPROM programming.
XTAL1
Input to the inverting oscillator amplifier.
XTAL2
Output from the inverting oscillator amplifier.
DESIGN CONSIDERATION
When running out of internal program/data memory, the 87C51-3 can be operated using a 24 MHz clock. If the
87C51-3 is running out of external program/data memory, the operating frequency must be between 3.5 MHz
to 20 MHz. The 87C51-3 will not function properly at 24 MHz when running out of external program/data
memory.
7-142
intel .
87CS1-20/-3
ABSOLUTE MAXIMUM RATINGS·
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature
Under Bias .................. -4S·Cto +8S·C
Storage Temperature .......... -6S·C to + 1S0·C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -o.SV to +6.SV
Maximum IOL per 1/0 Pin .................. 15 rnA
Power Dissipation .....•.................... 1.SW
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
(Based on package heat transfer limitations, not device power consumption).
OPERATING CONDITIONS
Symbol
TA
Vee
Fose
Description
Ambient Temperature Under Bias
Commercial
Express
Supply Voltage
Oscillator Frequency
Min
Max
Units
0
-40
4.0
3.5
+70
+85
6.0
20
·C
·C
V
MHz
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
VIL
VIL1
VIH .
VIH1
VOL
Parameter
Input Low Voltage (Except EA)
Commercial
Express
Input Low Voltage (EA)
Commercial
Express
Input High Voltage
(Except XTAL 1, RSn
Commercial
Express
Input High Voltage
(XTAL1, RSn
Commercial
Express
Output Low Voltage(5)
(Ports 1, 2, 3)
VOL1"
Output Low Voltage(5)
(Port 0, ALE, PSEN)
VOH
Output High Voltage
(Ports 1, 2, 3)
VOH1
Output High Voltage
(Port 0 in External Bus Mode,
ALE, PSEN)
IlL
Logical 0 Input Current
(Ports 1, 2, 3)
Commercial
Express
Typ(1)
Max
Unit
-0.5
-0.5
0.2 Vee - 0.1
0.2 Vee - 0.15
V
0
0
0.2 Vee - 0.3
0.2 Vee - 0.35
V
0.2 Vee + 0.9
0.2 Vee + 1.0
Vee + 0.5
Vee + 0.5
V
0.7 Vee
0.7 Vee + 0.1
Vee + 0.5
Vee + 0.5
0.3
0.45
1.0
0.3
0.45
1.0
V
Min
Vee
Vee
Vee
Vee
Vee
Vee
-
0.3
0.7
1.5
0.3
0.7
1.5
-50
-75
.7-143
Test Conditions
V
V
V
V
V
V
V
V
V
IOL = 100 ,...A(2)
IOL = 1.6 mA(2)
IOL = 3.5 mA(5)
IOL = 200 ,...A(2)
IOL = 3.2 rnA (2)
IOL = 7.0 mA(2)
IOH = -10,...A(3)
IOH = - 30 ,...A(3)
IOH = -60,...A(3)
V
V
V
IOH
IOH
IOH
= - 200 ,...A(3)
= -3.2 mA(3)
= -7.0 mA(3)
,...A
VIN
= 2.0V
87C51-20/-3
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
Min
III
Input Leakage Current
(PortO)
.
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
Commercial
Express
RRST
RST Pu"down Resistor
Cia
Pin Capacitance
Icc
Power Supply Current
Active Mode
Commercial
Express
Idle Mode
Commercial
Express
Power Down Mode
Typ(l)
50
Max
±10
Unit
p.A
0< VIN < Vcc
Test Conditions
-650
-750.
p.A
VIN
=
2.0V
KO
300
10
pF
@
1 MHz,25°C
(Note 4)
1B
32.5
45.5
rnA
mA
2.5
5
7.5
50
mA
rnA
p.A
3.0
NOTES:
1. "Typicals" are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fa" below the 0.9Vcc specification when the address bits are stabilizing.
4. See Figures 6 through 9 for Icc test conditions. Minimum Vcc for Power Down is 2V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per B-bit portPortO: 26mA
Ports 1, 2; and 3:
15 rnA
Maximum totallOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
3SmA
30mA
2SmA
20mA
ISmA
10mA
SmA
OmA
OMHz
-----~
~~
~~
"C1~
~
4101Hz
---------
~
8101Hz
ID~E
MAX
----
IDLE TYPICA~(I)
12 101Hz
Icc Max at other frequencies is given by:
Active Mode
Icc Max = 0.94 x FREQ + 13.71
Idle Mode
Icc Max = 0.141' FREQ + 2.31
Where Osc Freq is in MHz, Icc is in mA .
Figure 3. Icc vs Frequency
7-144
16IAHz
20lAHz
272082-7
infel .
87CS1-20/-3
RST
XTAL2
XTALI
XTAL2
XTALI
VSS
VSS
272082-9
272082-8
Figure 5. Icc Test Condition, Idle Mode.
All other pins are disconnected.
Figure 4. Icc Test Condition, Active Mode.
All other pins are disconnected.
PO
RST
EA
XTAL2
XTALI
VSS
272082-10
Figure 6. Icc Test Condition, Power Down Mode. All other pins are disconnected. Vcc = 2V to 5.5V.
Vee- O•S - - - - - - - . . , . . - - - - - . , .
0.7 Vee
O.4SV ---'ilO.2 Vee-0.1
TCHCL
272082-11
Figure 7. Clock Signal Waveform for Icc Tests In Active and Idle Modes.
TCLCH == TCHCL = 5 ns.
7-145
87C51-20/-3
l:
EXPLANATION OF THE AC SYMBOLS
Logic level LOW, or ALE
P:PSEN
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
0: Output data \
R: RD signal
T:Time
V: Valid
W: WR signal
A: Address
X: No longer a valid logic level
C: Clock
Z: Float
D: Input data
For example,
H: Logic level HIGH
I: Instruction (program memory contents)
TAVLL = Time from Address Valid to ALE Low.
TLLPL
=
Time from ALE Low to PSEN Low.
AC CHARACTERISTICS
(Over Operating Conditions; Load Capacitance for Port 0, ALE and
PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Min
Max
Variable Oscillator
Min
Max
Units
1/TCLCL
Oscillator Frequency
TLHLL
TAVLL
ALE Pulse Width
Address Valic:t to ALE Low
60
10
TLLAX
Address Hold After ALE Low
ALE Low to Valid Instr In
20
TLLlV
TLLPL
ALE Low to PSEN'Low
TPLPH
TPLIV
J5SEN Pulse Width ,
J5SEN Low to Valid Instr In
20
105
TPXIX
Input InstrHold After PSEN
TPXIZ
TAVIV
Input Instr Float After PSEN
30
TCLCL-20
ns
Address to Valid Instr In
145
5TCLCL-105
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
10
10
ns
ns
TPLAZ
TRLRH
TWLWH
TRLDV
3.5
2TCLCL-40
TCLCL-40
20
ns
ns
ns
TCLCL-30
4TCLCL-75
125
TCLCL-30
o '
3TCLCL-90
0
200
6TCLCL-100
200
6TCLCL-100
RD Low to Valid Data In
ns
ns
ns
ns
ns
5TCLCL-95
155
ns
TRHDX
Data Hold After RD
TRHDZ
TLLDV
Data Float After RD
ALE Low to Valid Data In
40
310
2TCLCL-60
8TCLCL-90
ns
TAVDV
Address to Valid Data In
9TCLCL-90
TLLWL
ALE Low to RD or WR Low
100
360
200
ns
ns
TAVWL
Address to AD or WR Low
110
4TCLCL-130
ns
TOVWX
TWHOX
Data Valid to WR Transition
Data Hold After WR
15
TCLCL-35
TCLCL-40
ns
ns
TOVWH
Data Valid to WR High
TRLAZ
AD Low to Address Float
RD or WR High to ALE High
TWHLH
0
ns
ns
3TCLCL-45
60
MHz
ns
0
10
280
3TCLCL-50
3TCLCL+50
7TCLCL-70
0
90
10
7-146
TCLCL-40
ns
ns
0
TCLCL+40
ns
ns
87C51-20/-3
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _J
PORT 0
---
PORT 2 _ _ _J
A8 - A 15
272082-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
I------TLLDV
-----I'j
TLLWL - - - I . . j + - - - TRLRH
PORTO
A -A
INSTR. IN
fROt.4 RI OR DPL
TAVWL
TAVDV
PORT 2
P2.D-P2.7 OR A8-A 15 fROt.l DPH
A8-A15 fROt.l PCH
272082-13
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
PSEN
--~---
TWLWH
WR
PORTO
PORT 2
DATA OUT
P2.D-P2.7 OR A8-A 15 fROt.l DPH
I"'STR. IN
A8-A 15 fROt.l PCH
272082-14
--"'~---------------.'---------
7-147
intet
87C51-20/-3
XTAL2
NC EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
XTAL2
----I
XTAL 1
£ ..
....- - - - - - 1 VSS
V_Ss_ _
272082-5
272082-6
Figure 8. Using the On-Chip Oscillator
Figure 9. External Clock Drive
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
3.5
20
MHz
TCHCX
High Time
20
20
ns
TCLCX
Low Time
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272082-15
SERIAL PORT TIMING-SHIFT REGISTER MODE
20 MHz
Symbol
Parameter
Oscillator
Min
Max
Variable Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycl~ Time
600
12TCLCL
ns
TOVXH
Output Data Setup to Clock Rising Edge
367
1OTCLCL - 133
ns
TXHOX
Output Data Hold After Clock Rising Edge
50
2TCLCL-50
ns
TXHDX
Input Data Hold After Clock Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input Data Valid
367
7-148
1OTCLCL -133
ns
intel .
87C51-20/-3
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
ALE
CLOCK
OUTPUT DATA
t
WRITE TO SBUr
INPUT DATA
'---"T'" '-----,J
'--_-IX'-_--IX'-_--IX'-......;..--IX'-_--Ix'-_--JI
+
SET T1
------I.r~.,.."""\!J 7':''::\..<,--"'','77':'"~J-"'J~~-"\J.7':'7':''::\.J'-....J'~''-\.r~\.r-\r~\J
t
+
CLEAR RI
SET RI
272082-16
=x
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC -0.5
0.45 V
x==
0.2 Vec+0.9
FLOAT WAVEFORMS
.
0.2 Vce-0.1
' _ _ _ _ _ _ _ _..1 VOL +0.1V
-.....;;;......-----
272082-17
AC inputs during testing are driven at Vee - 0.5 for a Logic "1"
and 0.45V for a Logic "0," Timing measurements are made at VIH
min for a Logic "1" and VIL max for a Logic "0",
272082-18
For timing purposes a port pin is no longer floating when a 100
mV change from load voltage occurs, and begins to float when a
100 mV change from the loaded VOHIVOL level occurs, IOLliOH
<: ±20 mA.
PROGRAMMING THE EPROM
Table 1. EPROM Programming Modes
Mode
RST
PSEN
ALE I
PROG
EAI
Vpp
P2.6
P2.7
P3.6
P3.7
Program Code Data
H
L
LS
12.75V
L
H
H
H
Verify Code Data
H
L
H
H
L
L
H
H
Program Encryption
Array Address 0-3F
H
L
LS
12.75V
L
H
L
H
Program Lock Bits
Bit 1
H
L
LS
12.75V
H
H
H
H
Bit 2
H
L
LS
12.75V
H
H
L
L
H
L
LS
12.75V
H
L
H
L
H
L
H
H
L
L
L
L
Bit3
Read Signature Byte
7-149
87C51·20/·3
+5V
Vcc
1-8
AO-A7
40
87C51-20
PI
32-39
21-24
P2.0P2.3
A8-Al1
PGW DATA
PO
31
EA/Vpp
ALE/PROG
PSEN
P2.7
P2.&
18
...--1----iXTAL 2
30
~___
29
28
27
17
P3.7
P3.6
PROGRAW
} SIGNALS
.
CONTROL SIGNALS
16
19
........._-+...;..;-IXTAL 1
20 VSS
RST
9
272082-19
'See Table 1 for proper input on these pins
Figure 10. EPROM Programming Configuration
ADDRESS
DATA
CONTROL
SIGNALS
X____x
12 BITS
X_ _ _ _ _ _X
X________________x
_
12.75V-1
EA/Vpp
5V
8 BITS
7 BITS
-L
TGLGH
ALE/PROG
272082-20
5 Pulses'
'5 Pulses for EPROM array, 25 pulses for encryption array and lock bits.
For compatibility, 25 pulses may be used to program the EPROM array.
Figure 11. Programming Waveforms
7-150
int:et
87CS1-20/-3
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
Signature Bytes
Location
Contents
Description
30H
31H
60H
89H
58H
51H
Indicates Intel Device
Indicates FX-Core Product
Indicates 87C51 Device
Erasure Characteristics
(Windowed Devices Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/ cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1's state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 2JOC, Vee = 5V ±10%, Vss = OV)
Symbol
Vpp
Parameter
Min
Max
Units
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
1/TCLCL
Oscillator Frequency
4
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold After PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold After PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
TGHSL
Vpp Hold After PROG
10
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
75
mA
6
MHz
p.s
/-Ls
110
/-Ls
48TCLCL
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float After ENABLE
0
TGHGL
PROG High to PROG Low
10
48TCLCL
7-151
48TCLCL
/-Ls
intel .
87C51-20/-3
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
VERIFICATION-
P1.0-P1.7 _ _ _ _
P2.0-P2.3
-<=:!D~~=)_-----C=!AD~DR§ES~=)----A. DRESS
TAVOV
roRTO-----=~~=~!E=~:::------~~M~TA~O~UT~)_-----
ALE/PROG - - - - - - , I
fA/vpp
LOGIC 1
_ _ _oJ
LOGIC 1
_______ ,!;2.G!£..O___ _
rELQV
(ENABLE)
P2.7
TEHQZ
272082-21
"For programming conditions see Figure 10.
""5 pulses for EPROM array, 25 pulses for encryption table and lock bits. For compatibility, 25 pulses may be used to
program the EPROM array.
DATA SHEET REVISION HISTORY
This data sheet (272082-002) is valid for devices with an "A" at the end of the topside tracking number. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data'sheet (272082-002) and the previous version (272082-001):
1. Added 87C51-3 to 20 MHz data sheet.
2. References to second functions of Port 1 pins have been removed.
3. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
From
To
120
125
TLLlV
4TCLCL-80
4TCLCL-75
3TCLCL - 95
3TCLCL - 90
TPLIV
TCLCL-50
TCLCL-35
TOVWX
TWHOX
o
10
TCLCL-50
TCLCL-40
TOVWH has been added.
The following differences exist between version -001 of this data sheet (272082-001) and the 87C51
(270147-006) data sheet.
1. All explanatory wording duplicated in the device user's guide was deleted.
2. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
From
To
4TCLCL -1 00
4TCLCL - 80
TLLlV
3TCLCL -1 05
3TCLCL - 95
TPLIV
TCLCL - 25
TCLCL - 20
TPXIZ
5TCLCL -165
5TCLCL - 95
TRLDV
8TCLCL -150
8TCLCL - 90
TLLDV
TAVDV
9TCLCL -165
9TCLCL - 90
4TCLCL-130
4TCLCL-90
TAVWL
TCLCL-50
TCLCL-35
TOVWX
3. TXHOX in the Serial Port Timing Table changed from (2TCLCL -117) to (2TCLCL - 50).
7-152
8XC51SL/LOW VOLTAGE 8XC51SL
KEYBOARD CONTROLLER
80C51SL -CPU with RAM and 1/0; Vee = 5V ±10%
81C51SL-16K ROM Preprogrammed with SystemSoft Keyboard Controller and Scanner
Firmware. Vee = 5V ± 10%.
83C51SL - 16K Factory Programmed ROM. Vee = 5V ± 10%.
87C51SL - 16K OTP, ROM. Vee = 5V ± 10%.
Low Voltage 80C51SL- CPU with RAM and 1/0; Vee = 3.3V ± 0.3V
Low Voltage 81C51SL- 16K ROM Preprogrammed with SystemSoft Keyboard Controller
and Scanner Firmware. Vee = 3.3V ±0.3V.
Low Voltage 83C51SL- 16K Factory Programmed ROM. Vee = 3.3V ± 0.3V.
Low Voltage 87C51SL- 16K OTP ROM. Vee = 3.3V ±0.3V.
•
•
•
•
•
•
•
•
Proliferation of 8051 Architecture
Complete 8042 Keyboard Control
Functionality
8042 Style Host Interface
Optional Hardware Speedup of
GATEA20 and RCL
Local 16 x 8 Keyboard Switch Matrix
Support
Two Industry Standard Serial Keyboard
Interfaces; Supported via Four High
Drive Outputs
5 LED Drivers
8-Bit AID
• 4-Channel,
for up to 32 Kbytes of
• Interface
External Memory
Rate Controlled I/O Buffers Used
• Slew
to Minimize Noise
256 Bytes Data RAM
• Three
Multifunction 1/0 Ports
• 10 Interrupt
Sources with 6 User• Definable External
Interrupts
2
MHz Clock Frequency
• 100-Pin PQFP (8XC51SL)
• 100-Pin SQFP (Low Voltage 8XC51SL)
~Hz-16
Low Power CHMOS Technology
The 8XC51SL, based on Intel's industry-standard MCS®-51 microcontroller family, is designed for keyboard
control in laptop and notebook PCs. The highly integrated keyboard controller incorporates an 8042-style UPI
host interface with expanded memory, keyboard scan, and power management. The 8XC51SL supports both
serial and scanned keyboard interfaces and is available in pre-programmed versions to reduce time to market.
The Low Voltage 8XC51SL is the 3.3V version optimized for even further power savings. Throughout the
remainder of this document, both devices will generally be referred to as 51 SL.
The 8XC51SL is a pin-for-pin compatible replacement for the 8XC51SL-BG. It does, however have some
additional functionality. Those additional functions are as follows:
1. 16K OTP ROM: The 8XC51SL-BG had only 8K of ROM.
2. New Register Set: The 8XC51SL adds a second set of host interface registers available for use in supporting power management. This required an additional address line (A1) for decoding. To accommodate this,
one Vee pin was'removed. However, in order to maintain compatibility with the -BG version, an enable bit
for this new register set was added in configuration register o. This allows the 8XC51SL to be drop in
compatible to existing 8XC51SL-BG designs; no software modifications required.
3. Interrupt Enable: The 10 available interrupts on the 8XC51SL-BG were split into two groups of five, each
with its own global enable. The 8XC51SL combines those two groups into a single group with one global
enable for all 10 interrupts.
For the complete data sheet on this product, refer to the 1993 Mobile Computer Products
handbook.
7-153
October 1992
Order Number: 272271-001
87C52/80C52/80C32
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 8 KBYTES INTERNAL PROGRAM MEMORY
S7C52/S0C52/S0C32-3.5 MHz to 12 MHz, Vee = 5V ±20%
S7C52-1/S0C52-1/S0C32-1-3.5 MHz to 16 MHz, Vee = 5V ±20%
S7C52-L-3.5 MHz to S MHz, Vee = 3.3V ±O.3V
Performance CHMOS EPROM/
• High
ROM/CPU
Low Voltage Operation (-L Only)
• Three
16-Bit Timer/Counters
• Programmable
Clock Out
• Up/Down Timer/Counter
• Three Level Program Lock System
•
EPROM/ROM
• SK256On-Chip
Bytes of On-Chip Data RAM
• Improved
• Algorithm Quick Pulse Programming
Processor
• Boolean
• 32 Programmable I/O Lines
Interrupt Sources
• 6Programmable
Serial Channel with:
•-
Framing Error Detection
- Automatic Address Recognition
and CMOS Compatible Logic
• TTL
Levels
External Program Memory Space
• 64K
64K External Data Memory Space
• MCS®-51 Compatible Instruction Set
• Power
• Modes Saving Idle and Power Down
(On-Circuit Emulation) Mode
• ONCE
• Four-Level Interrupt Priority
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside on-chip, (except 80C32). The device
can also address up to 64K of program memory external to the chip.
OATA MEMORY: This microcontro"er has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C52/80C52/80C32 is a single-chip control-oriented microcontro"er which is fabricated on Intel's
reliable CHMOS III-E technology. Being a member of the MCS-51 family, the 87C52/80C52/80C32 uses the
same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS51 family of products. The 87C52/80C52/80C32 is an enhanced version of the 87C51 /80C51 BH/SOC31 BH.
It's added features make it an even more powerful microcontro"er for applications that require clock output,
and up/down counting capabilities such as motor control. It also has a more versatile serial channel that
facilitates multi-processor communications.
Applications that require low voltage operation can use the 87C52-L. The 87C52-L will operate at 3.3V ±O.3V
at a frequency range of 3.5 MHz to 8 MHz.
Throughout this document 8XC52 will refer to the 87C52, 80C52 and 80C32.
7-154
October 1992
Order Number: 270757-003
intel"
87C52/80C52/80C32
PO.O-PO.7
!'sEN
ALE/PiWif
EA/VPP
RST
TIMING
AND
CONTROL
'"
I~::::~~==~::::::::~::~~::~~:::::;~~::J
270757-1
Figure 1. 8XC52 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
7-155
87C52/80C52/80C32
PACKAGES
Part
Prefix
Package Type
91a
Ole
8XC52
87C52
8XC52
8XC52
P
D
N
S
40-Pin Plastic DIP (OTP)
40-Pin CERDIP (EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
45°C/W
45°C/W
46°C/W
87"C/W
16°C/W
15°C/W
16°C/W
18°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
(T2) PI.D
.., "! "!
0: 0: 0: 0: 0:
"':
INDEX
CORNER
>~ >e ~
. .. ...,
.,; .,; .,;
(T2EX) PI. I
Vee
PO.O (ADO)
P1.2
PO. I (ADI)
PI.S
PO.4
PI.3
PO.2 (A02)
PI.6
PO.S
PI.4
PO.3 (AD3)
PI.7
PO.6
PI.S
PO.4 (AD4)
RST
PI.6
PO.S (ADS)
P3.0
PI.7
PO.6 (AD6)
Reserved·
Reserved-
RESET
PO.7 (AD71
P3.1
ALE/PROO
EA/Vpp
P3.2
(TXD) P3.1
ALE/PROO
P3.3
P2.7
(iNTO) P3.2
(iiifi) P3.3
i'SEN
P3.4
P2.6
P2.7 (AIS)
P3.S
P2.S
(RXD) P3.0
(TO) P3.4
P2.6 (AI4)
(TI) P3.S
(iiR) P3.6
P2.S (AI3)
PO.7
EA/Vpp
...., ..,...., .
"!
P2.4 (A 12)
(Rli) P3.7
P2.3 (All)
XTAL2
P2.2 (AID)
XTAL1
P2.1 (A9)
Vss
P2.0 (AS)
. ..., ....
.
.
..
:
U) ~ N N N N N
~ )~(
~
)(
~
270757-3
PLCC
270757-2
DIP
INDEX
CORNER \
"'II; ~ C'! ~ ~
.... - - .... ~
~
~
~
~
en
u
C! '"",: l"o! "1
oooo
>U>J u
~
~
~
~
.!~ !!!!!~!~!~!~!!~! !~:!=!:!~:!~
C~
[:[3
P1.6 2:!
i:;tz
P1.5
PO.S
;:[1 PO.6
P1.7 3: ~
RST
P3.0
Reserved*
i):o
.[!
S:!
L{9
(!
LtB
LV
excsz
P3.1 7: ~
iI6
P3.2 8: ~
P3.3
S:!
P3.'" 1]!
P3.S 1] ~,_.
PO.'"
L2)
PO.7
EA/Vpp
ReservedALE/PROO
PSEN
P2.7
1:(4 p2.e
1_ 'I
roo
'1.- '1.'I
roo
'I ,_ 'I ... 'I ... 'I ... 'I ...
J,2) P2.S
.I~II~II::!II~II~II~II~II~II~II~II~I •
...., .
...
N N
QFP
'00 not connect reserved pins.
Figure 2. Pin Connections
7-156
270757-4
infel"
87C52/80C52/80C32
PIN DESCRIPTIONS
Vee: Supply voltage.
Vss: Circuit ground.
VSS1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the Vss pin (pin 22).
Port 0: Port 0 is an 8-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong i(lternal pull ups when emitting1 's, and can source and
sink several LS TTL inputs.
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pull ups when emitting 1'so During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit .bidirectional 1/0 port with
internal pull ups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
In addition, Port 1 serves the functions of the following special features of the 8XC52:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timerl
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)
P1.1
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIHI voltage is applied whether
the oscillator is running or not. An internal pulldown
resistor permits a power-on.reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the B7C52.
In normal ope~ation ALE is emitted at a constant
rate of Ys the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location BEH. With the bit set, ALE is
active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakJy pulled high. Setting the
ALE-disable bit has no effect if the microcontroller is
.
in external execution mode.
7-157
87C52/80C52/80C32
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
high and low times specified on the data sheet must
be observed.
piri.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the 8XC52 is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
Memory.
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
EA should be strapped to Vee for internal program
executions.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
Nle
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
Vss
270757-5
Figure 4. External Clock Drive Configuration
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
'
~
2
o
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the eXC52 either a hardware reset or an external
ii:lterrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
XTAL2
CI
XTAL 1
Vss
To properly terminate Power down the reset or external interrupt should not be executed before Vee is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
270757-6
C1, C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
Figure ,3. OSCillator Connections
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. TherE~.. are no requirements on the
duty cycle of the external 'clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding ,
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
7-158
int:eL
87C52/80C52/80C32
Table 1. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
Mode
PORTO
PORT1
PORT2
PORT3
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the 80C51 BH."
DESIGN CONSIDERATION
ONCE MODE
• The 87C52-L will operate at 3.3V ± O.3V at a frequency range of 3.5 MHz to 8 MHz. Operating
beyond these specifications could cause improper device functionality. (To program the 87C52-L,
follow the same procedure as the 87C52.)
The ONCE ("On-Circuit Emulation") Mode facilitates·
testing and debugging of systems using the 8XC52
without the 8XC52 having to be removed from the
circuit. The ONCE Mode is invoked by:
• The window on the 87C52 must be covered by an
opaque label. Otherwise, the DC and AC characteristics may not be met, and the device may
functionally be impaired.
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0NPins
float and the other port pins and ALE and PSE are
weakly pulled high. The oscillator circuit remains active. While the 8XC52 is in this mode, an emulator or
test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
7-159
intel.,
87C52/80C52/80C32
ABSOLUTE MAXIMUM RATINGS·
NOTICE: This data sheet contains preliminary infor·
mation on new products in production. The specifica·
tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature Under Bias. -40°C to + 85°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... 0Vto + 13.0V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex·
tended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on Any Other Pin to Vss .. .....:0.5Vto +6.5V
IOL Per I/O Pin ........................... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions:
.
TA (under bias) = O°C to +70·C; Vee = 5V ±20%; Vss = OV (87C52·L, Vee = 3.3V ±0.3V)
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both 5V and 3.3V devices unless otherwise indicated.
Symbol
Parameter
Typ
(Note 4)
Min
Max
Unit
-0.5
0.2Vee- 0.1
V
VIL
Input Low Voltage
VIL1
Input Low Voltage EA
0
0.2Vee- 0.3
V
VIH '
Input High Voltage
(Except XTAL1, RST)
0.2 Vcc+0.9
Vee + 0.5
V
VIH1
Input High Voltage (XTAL 1, RST)
0.7 Vee
Vee + 0.5
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
VOL1
VOH
VOH1
Output High Voltage
(Port 0 in External Bus Mode)
IlL
Logical 0 Input Current
(Ports 1, 2 and 3)
III
Input leakag~ Current (Port 0)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
0.3
V
IOL = 100 /LA (Note 1)
0.45
V
IOL = 1.6 mA (Note 1)
1.0
V
IOL = 3.5 mA (Note 1)
0.3
V
IOL = 200 /LA (Note 1)
0.45
V
IOL = 3.2 mA (Note 1)
1.0
V
IOL ~ 7.0 mA (Note 1)
Vee- 0.3
V
IOH = -10/LA
Vee- 0.7
V
IOH = -30J.LA
Vee- 1.5
V
IOH = -60
Vee- 0.3
V
IOH = -200/LA
Vee- 0.7
V
IOH = -3.2mA
Vee- 1.5
V
IOH= -7.0 mA
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2 and 3, ALE, PSEN)
Test Conditions
-50
/LA VIN =0.45V
±10
J.LA VIN = VIL or VIH
-650
7·160
J.LA
/LA VIN = 2V
intet
87C52/80C52/80C32
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to both 5V and 3.3V devices unless otherwise indicated.
Symbol
Parameter
Min
50
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
Icc
Power Supply Current:
Active Mode
87C52-L at 8 MHz
All Others at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
Typ
(Note 4)
Max
Unit
300
KD.
10
pF
Test Conditions
@1 MHz, 25°C
(Note 3)
15
5
5
12
30
7.5
75
rnA
rnA
rnA
p.,A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOLS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from'1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.SV. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vcc specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vcc for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
Maximum IOL per S-bit portPort 0:
26 mA
Ports 1, 2 and 3:
15 mA
71 mA
Maximum total IOL for all output pins:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
40mA
r----------r----------.----------.--~----__,
30mA
~--------~----------~------~~~------__4
BXC52
20mA r----------r------~~r----------t------~~
CLOCK
SIGNAL
10 mA
~--------~--_=_-="-~---------t
MAX.
270757-7
OmA
L -________-L__________L -________
OMHz
4MHz
BMHz
IDLE TYPICAL (4)
~
________
12MHz
~
16MHz
270757-21
ICC Max at other frequencies is given by:
Active Mode
Icc Max = 2.2 x Freq + 3.1
Idle Mode
Icc Max = 0.49 x Freq + 1.6
Where Freq is in MHz, IcC Max is given in mA.
Figure 5. Icc vs Frequency
7-161
All o1her pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 6. Icc Test Condition,
Active Mode
infel .
87C52/80C52/80C32
Vee
PO
PO
RST
EAt---'"I
RST
8XCS2
EAt---'"I
8XC52
XTAL2
XTALI
CLOCK
XTAL2
SIGNAL--..... XTAL 1
VSS
Vss
270757-8
270757-9
All other pins disconnected
TCLCH = TCHCL = 5 ns
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 6.0V
Figure 7. Icc Test Condition Idle Mode
Vee-a.s .--.----~~---0.7 Vee
0.45V ---700.2 Vee-O.t
TCHCL
270757-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
7-162
int:eL
87C52/80C52/80C32
L: Logic level LOW, or ALE
P:PSEN
0: Output Data
R: RD signal
T:Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock,
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
For example,
TAVLL
TLLPL
= Time from Address Valid to ALE Low
=
Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
Min
Min
Max
3.5
16
Max
1/TCLCL Oscillator Frequency
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
53
TCLCL-30
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
53
TCLCL-30
TPLPH
PSEN Pulse Width
205
3TCLCL-45
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
59
TCLCL-25
ns
312
5TCLCL-105
ns
10
10
234
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
TRLRH
RD Pulse Width
400
TWLWH WR Pulse Width
400
ns
0
ns
ns
6TCLCL-100
ns
ns
6TCLCL-100
ns
5TCLCL-165
252
ns
ns
3TCLCL-105
145
0
ns
4TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
107
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
ns
TAVDV
Address to Valid Data In
585
9TCLCL-165
ns
300
3TCLCL-50 3TCLCL+50
ns
ns
0
0
ns
ns
TLLWL
ALE Low to RD or WR Low
200
TAVWL
Address Valid to WR Low
203
4TCLCL-130
TOVWX Data Valid before WR
33
TCLCL-50
ns
TWHOX Data Hold after WR
33
TCLCL-50
ns
TOVWH Data Valid to WR High
433
TRLAZ
RD Low to Address Fioat
TWHLH
RD or WR High to ALE High
7TCLCL-150
0
43
7-163
123
TCLCL-40
ns
0
ns
TCLCL+40
ns
- intel..
87C52/80C52/80C32
EXTERNAL -PROGRAM MEMORY READ CYCLE
ALE _ _.I
PSEN _ _. I
PORT 0
---
PORT 2 _ _ _. I
A8 -A15
270757-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
t-----TLLDV
----0-1---
------~~~----~
"
TRLRH
PORTO
INSTR. IN
PORT2 ____,~________~P~2.~0-~P~2~.7_0~R~A~8_-A~I~5~F~R~OM~DP~H~________J,____A~8~-~A~15~F~R~OM~PC~H~___
270757-12
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLLWL--~---TWLWH
t---l---TQVWH
PORTO
FROII RI OR DPL
---I
-----I
DATA OUT
INSTR. IN
t----TAVWL---~
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
270757-13
7-164
intet
S7C52/S0C52/S0C32
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions:
Symbol
Over Operating Conditions; Load Capacitance = 80 pF
12 MHz Oscillator
Parameter
Min
Variable Oscillator
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1
12TCLCL
TQVXH
Output Data Setup to Clock
Rising Edge
700
1OTCLCL -133
Il s
ns
TXHQX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
1OTCLCL - 133
700
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
2
4
3
5
6
7
8
ALE
CLOCK
OUTPUT DATA
t
X
~--~~--~~--~
3
X
4
X
5
X
6
X
7
7
+
SET TI
WRITE TO SBUF
INPUT DATA - - - -......~~...-~ ~~......~~...-~~_""'-~V""'-.~~~~~-~~
+
t
SET RI
CLEAR RI
270757-20
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
8XC52
8XC52-1
3.5
3.5
12
16
MHz
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
TCHCX
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270757-14
7-165
intel~
87C52/80CS2/80C32
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC- 0.5
0.45
-V-
FLOAT WAVEFORMS
~.
0.2 VCC+0.9
TIMING REFERENCE
A-
V~_0_.2_VC.;;..C;;.,.-_0_.1_ _ _ _
POINTS
270757-15
AC Inputs during testing are driven ~t Vee-0.5V for a Logic "1"
and OA5V for a Logic "0". Timing measurements are made at VIH
min for a Logic "1" and Vil max for a Logic "0".
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOllioH = ±20 mA (·L, IOl/lOH = ± 10 mAl.
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running witli a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig.!!J.lntll just before ALEI
PROG is to be pulsed. The EAlVpp is raiSed to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5 respectively for AO-A13.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTES:
• Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
. glitches.
• Programming specifications for the 87C52-L are
the same as the standard 87C52.
Tabie 2. EPROM Programming Modes
RST
PSEN
ALEI
PROG
EAI
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
'"l..f"
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
'"l..f"
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
'"l..f"
12.75V
H
H
H
H
H
Bit2
H
L
'"l..f"
12.75V
H
H
H
L
L
Bit3
H
L
'"l..f"
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Mode
Read Signature Byte
7-166
87C52/80C52/80C32
87CS2
AO-A7
P1
A8-A-1~3-~"~~:~ -
EA/Vpp
} PROGRAt.t
ALE/PROO t - - - SIGNALS
PSENi--P2.7i--P2.6t--P3.7i---
CONTROL SIGNALS'
P3.6i--P3.3t--RSTi---·J
270757-17
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C52 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
ADDRESS
X
PROGRAM VERIFY
Program verify may be done after each byte or block
of bytes. is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C52.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
x
14 BITS
X_________________X
X_________________X
DATA
8 BITS
CONTROL
SIGNALS
7 BITS
12.7SV
EA/Vpp
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
I
SV - - '
'--
TGLGH
ALE/PROO
5 Pulses
Figure 11. Programming Signal's Waveforms
7-167
270757-18
intel .
87C52/80C52/80C32
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
Reading the Signature Bytes
The 87C52/80C52 each has 3 signature bytes in locations 30H, 31H, and 60H. To read these bytes follow the procedure for EPROM verify, but activate
the control lines provided in Table 2 for Read Signature Byte.
Location
30H
31H
60H
Content
87C52
80C52
89H
58H
52H
89H
58H/53H
52H/12H
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of. at least 15 W-sec/cm 2. Exposing the
EPROM to an ultraviolet lamp of, 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
Erasure Characteristics
(Windowed Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA
=
21°C to 27°C; Vee = 5V ±20%; Vss
=
OV)
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
rnA
6
MHz
Symbol
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
p.s .
TGHSL
Vpp Hold after PROG
10
p.s
PROGWidth
90
TGLGH
TAVQV
4
Units
TELQV
ENABLE Low to Data Valid
TEHQZ
Da~a
TGHGL
PROG High to PROG Low
110
p.s
48TCLCL
' Address to Data Valid
48TCLCL
Float after ENABLE
0
10
7-168
48TCLCL
p.s
intel0
87C52/80C52/80C32
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
P1.0-P1.7
P2.0-P2.5
VERIFICATION
------{==:§~~:~=~~-----{=~A~D~DR~E~SS~=>-----TAVQV
PO------t1:::!~~~!==>i-------~~DA~T~A~O~UT~:)-----TGHDX
ALE/PROG
EA/Vpp
------_1
TGHAX
Vce
EA/HIGH
-----'
TEHQZ
CONTROL ---"'~r----------------~I,.---",Lr------SIGNALS
(ENABLE)
----'1'1----------------'1'-----'1'1------270757-19
"5 pulses for the EPROM array. 25 pulses for the encryption table and lock bits.
DATA SHEET REVISION HISTORY
The following differences exist between this data sheet (270757-003) and the previous version (270757-002):
1. Data sheet title was changed from:
SOC52/S0C32 CHMOS Single-Chip S-Bit Microcomputer.
to:
S7C52/S0C52/S0C32 CHMOS Single-Chip S-Bit Microcontroller with S Kbytes Internal Program Memory.
2. Added 3.3V device to data sheet.
3. Revision History added to data sheet.
7-169
S7C52/S0C52/S0C32
EXPRESS
S7CS2/S0CS2/S0C32-3.S MHz to 12 MHz, Vee = SV ±20%
S7CS2-1/S0CS2-1/S0C32-1-3.S MHz to 16 MHz, Vee = SV ± 20%
•
Extended Temperature Range
•
Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontro"ers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in. .
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of -40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125·C with Vee
guidelines in MIL-STD-883, Method 1015.
=
6.9V
± 0.25V, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for a"
parameters not listed here. This data sheet is valid in conjunction with the commercial 87C52/80C52/80C32
data sheet 270757-003.
7-170
September 1992
Order Number: 270868-002
intel .
87C52/80C52/80C32 EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
DC and AC parameters not included here are the same as in the commercial temperature range data sheets.
DC CHARACTERISTICS
Symbol
TA
=
-40'Cto +85'C;Vcc = 5V ±10%;Vss
Limits
Parameter
Min
= ov
Unit
Max
liL
Logical 0 Input Current (Port 1, 2, 3)
-75
p.A
III
Input Leakage Current
(Port 0 and EA)
±15
p.A
ITL
Logical 1 to 0 Transition
Current (Ports 1,2, 3)
-750
p.A
ICC
Power Supply Currrent
Active Mode
Idle Mode
Power Down Mode
35
7.5
150
mA
mA
p.A
Test
Conditions
VIN
= 0.45V
= VIL or VIH
VIN
= 2.0V
VIN
(Note 1)
NOTE:
1. Vee = 4.5V-5.5V, Frequency Range =3.5 MHz-12 MHz.
Table 1 Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
O·
Cerdip
Commercial
No
N
,
PLCC
Commercial
No
TP
Plastic
Extended
No
TO·
Cerdip
Extended
No
TN
PLCC
Extended
No
LP
Plastic
Extended
Yes
LO·
Cerdip
Extended
Yes
PLCC
Extended
Yes
LN
·Avallable for 87C52 only.
NOTE:
.;. Commercial temperature range is O'C to 70'C. EXtended temperature range is -40'C to +85'C.
• Burn-in is dynamic for a minimum time of 168 hours at 125'C, Vee = 6.9V ±0.25V, following guidelines in MIL-STO-883
Method 1015 (Test Condition 0).
Examples:
P80C52 indicates 80C52 in 8; plastic package and specified for commercial temperature range, without burn-in.
L080C52 indicates 80C52 ilia cerdip package and specified for extended temperature range with burn-in.
7-171
87C52-20/80C52-20/80C32-20
COMMERCIAL/EXPRESS
20 MHz MICROCONTROLLER
87C52-20/80C52-20/80C32-2D-3.5 MHz to 20 MHz, Vee = 5V ± 20%
87C52-3/80C52-3-24 MHz Internal Operation, Vee ~ 5V ± 20%
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
24 MHz Internal Execution (-3 only)
Three 16-Blt Timer/Counters
III Programmable Clock Out
Up/Down Timer/Counter
Three Level Program Lock System
8K On-Chip EPROM/ROM
256 Bytes of On-Chlp Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
32 Programmable I/O Lines
•
•
•
•
•
•
•
•
6 Interrupt Sources
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory Space.
III 64K External Data Memory Space
MCS@-51 Compatible Instruction Set
Power Saving Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
Four-Level Interrupt Priority
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to S Kbytes of the program memory can reside on-chip (except S0C32). The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x S on-Chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel S7C52-20/S0C52-20/S0C32-20 is a single-chip control-oriented microcontroller which is fabricated
on Intel's reliable CHMOS III-E technolpgy. Being a member of thE! MCS-51 family, the S7C52-20/S0C52-20/
SOC32-20 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with
the existing MCS-51 family of products. The S7C52-20/S0C52-20/S0C32-20 is an enhanced version of the
S7C51/S0C51BH/SOC31BH. Its added features make it an even more powerful microcontroller for applica~
tions that require clock output, and up/down counting capabilities such as motor control. It also has a more
versatile serial channel that facilitates multi-processor communications.
The S7C52-3/S0C52-3 has the same 3.5 to 20 MHz frequency range as the S7C52-20/S0C52-20 when
operating out of external program/data memory. When running out of internal program/data memory, the
S7C52-3/S0C52-3 can operate up to 24 MHz.
Throughout this document, SXC52-20 will refer to the S7C52-20, SOC52-20, SOC32-20, 87C52-3 and SOC52-3.
7-172
October 1992
Order Number: 272272-001
intel .
B7C52-20/BOC52-20/BOC32-20
PO.O-PO.7
-.,
r-V~
I
I
I
I
I
I
I
I
I
VSS
~
I
I
I
mN
ALE/t'RM'
t:A/VPP
RST
TIlliNG
AND
CONTROL
PI.O - PI.7
P3.0- P3.7
272272-1
Figure 1. 8XC52-20 Block Diagram
7-173
87C52~20/"OC52-20/80C32-20
PACKAGES
Part
Prefix
Package Type
OJA
8XC52-20
87C52-20
8XC52-20
8XC52-20
P
D
4O-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-PinQFP
45°C/W
45°C/W
46°C/W
87°C/W
N
S
(T2) Pl.0
(T2EX) Pl.l
Vee
PO.O (ADO)
Pl.2
PO.l (AD1)
Pl.3
PO.2 (AD2)
PI ••
PO.3 (AD3)
Pl.S
PO •• (AD.)
Pl.6
PO.S (ADS)
Pl.7
PO.6 (AD6)
RESET
PO.7 (AD7)
EA/Vpp
(RXD) P3.0
(TXD) P3.1
(iiffii) P3.2
·OJC
16°C/W
15°C/W
16°C/W
1aoC/W
INDEX
CORNER
Pl.S
Pl.6
Pl.7
RST
P3.0
RESERVEDP3.1
P3.2
P3;3
P3 ••
P3.S
ALE/PRoo
PSEN
P2.7 (A1S)
(iiffi) P3.3
(TO) P3 ••
(TI) P3.S
P2.6 (AI.) ..
P2.S (A13)
(Wi) P3.6
(Ro) P3.7
P2 •• (A12)
P2.3 (AI I)
XTAL2
P2.2 (AID)
XTALI
P2.1 (A9)
VSS
P2.0 (Ae)
272272-3
PLCC
272272-2
DIP
INDEX
CORNER \
.!~!~!~!~!~ !~: ~~!~ !~: !~:!~
PI.S
C!
iD
Pl.6
(!
ilj
i~) PO.6
Lt~ PO.7
PI.7 3:!
RST
P3.0
.:!
s: !
RESERVED-
(!
P3.1
a:!
P3.2
P3.3
P3 ••
P3.5
PL.
PO.5
Lis
8XC52-20
EA/Vpp
iie RESERVED-
iT
(!
i
(!
i(& PSEN
PL7
ii
iO
iO
~!
G!
ALE/PRoo
n~
PLS
.;~~ ::~:!~ ~~ ;~~ ;E::~ ~~ ~~ ~~;;;~ ;~~_
-
Nt')..,.
co-i N N N
a. a..
CL
a.
272272-4
QFP
• Do not connect reserved pins.
Figure 2. Pin Connections
7-174
intel .
87C52-20/80C52-20/80C32-20
PIN DESCRIPTIONS
Vee: Supply voltage.
Vss: Circuit ground.
VSS1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the Vss pin (pin 22).
Port 0: Port 0 is an 8-bit, open drain, bidirectional 110
port. As an output port each pin can sink several LS
TIL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port'O is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pull ups when emitting1 's, and can source and
sink several LS TIL inputs.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pull ups when emitting 1'So During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification. .
Port 3: Port 3 is an 8-bit bidirectional 110 port with
internal pullups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1 's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional 110 port with
internal pullups. The POI\ 1 output buffers can drive
LS TIL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
In addition, Port 1 serves the functions of the following special features of the 8XC52-20:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timerl
Counter 2), Clock-Out
P1.1
T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condi·
tion when a minimum VIHI voltage is applied whether
the oscillator is running or not. An internal pulldown
resistor permits a power-on reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C52·20.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
Port 2: Port 2 is an 8-bit bidirectional 110 port with
internal pullups. The Port 2 output buffers can drive
LS TIL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
7-175
87C52-20/80C52-20/80C32-20
If desired, ALE operation can be disabled by setting
bit 0 of SFR location BEH. With the bit set, ALE is
active only during a MOVX or MOVC instruction.
, Otherwise, the pin is weakly pulled high. Setting the
ALE-disable bit has no effect if the microcontroller is
in external execution mode.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the BXC52-20 is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
'
Memory.
EAlVpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset. .
.
EA should be strapped to Vee for internal program
executions.
'
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTALI
Vss
272272-6
Figure 4. External Clock Drive Configuration
IDLE MODE
XTAL2: Output from the inverting oscillator amplifier.
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the on board RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs.
OSCILLATOR CHARACTERISTICS
POWER DOWN MODE
XTAL1 and XTAL2 are the input and output, respectively, of a inverting' amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode, is terminated.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
2 0
~
XTAL2
On the 8XC52-20 either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
CI
XTAL I
Vss
Cl, C2 = 30 pF ± 1()PF for Crystals
272272-5
For Ceramic Resonators, contact resonator manufacturer.
To properly terminate Power down the reset or external interrupt should not be executed before Vee is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
Figure 3. OSCillator Connections
7-176
intel .
87C52-20/80C52-20/80C32-20
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
DESIGN CONSIDERATION
• When running out of internal program/data memory, the 87C52-3/80C52-3 can be operated using
a 24 MHz clock. If the 87C52-3/80C52-3 is running out of external program/data memory, the
operating frequency must be between 3.5 to
20 MHz. The 87C52-3/80C52-3 will not function
properly at 24 MHz when running out of external
program/data memory.
TIMER 2 PROGRAMMABLE
CLOCK OUT
• The window on the 87C52-20 must be covered
by an opaque label. Otherwise, the DC and AC
characteristics may not be met, and the device
may functionally be impaired.
The 8XC52-20 has a new Timer 2 feature. A 50%
duty cycle clock can be programmed to come out on
P1.0. The output frequency ranges from 61 Hz to
4 MHz depending on the oscillator frequency and
the reload value of the Timer 2 capture registers
(RCAP2H, RCAP2L) as shown in' the equation below:
o
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
_
Oscillator Frequency
Clock-Out Frequency - 4 x (65536 - RCAP2H, RCAP2L)
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared, and bit
T20E in T2MOD must be set. Bit TR2 (T2CON.2)
starts and stops the timer.
For a complete description of all Timer 2 functions,
please reference the 8XC52/54/58 Hardware Description of the 8-Bit Embedded Controllers Handbook.
°NOTE:
Even though the equation permits a maximum
clock-out frequency of 5 MHz using a 20 MHz oscillator, the maximum device output frequency is
4 MHz. When using a 20 MHz oscillator, RCAP2L
must be limited to a maximum value of FEH.
ONCE MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC52-20 without the 8XC52-20 having to be removed from the circuit. The OJ\JCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC52-20 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Table 1. Status of the External Pins durIng Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
Idle
Power Down
Power Down
External
Internal
External
1
0
0
Mode
PORTO
PORT1
PORT2
PORT3
1
Data
Data
Float
Data
Data
Data
Data
Data
1
0
0
Address
Data
Data
Data
Data
Data
Data
Float
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the BOC51BH."
7-177
intel·
87C52-20/80C52-20/80C32-20
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias.' - 40·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to + 6.5V
IOL Per 1/0 Pin ........................... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability. ,
OPERATING, CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
-40
+70
+85
·C
DC
Vee
Supply Voltage
4.0
6.0
V
fose
Oscillator Frequency
3.5
20
MHz
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
VIL
Parameter
Input Low Voltage
Typ
Min
(Note 4)
Max
Unit
0.2Vcc- 0.1 V
-0.5
VIL1
Input Low Voltage EA
0
0.2 Vee-0.3
V
VIH
Input High Voltage
(Except XTAL1, RST)
0.2 Vee + 0.9
Vee + 0.5
V
VIH1
Input High Voltage (XTAL1, RST)
0.7 Vee
Vee + 0.5
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
. VOL1
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
1
VOH
VOH1
Output High Voltage
(Ports 1, 2 and 3, ALE, PSEN)
Output High Voltage
(Pprt 0 in External Bus Mode)
= 100 p.A (Note 1)
= 1.6 mA (Note 1)
IOL = 3.5 mA (Note 1)
IOL = 200 p.A (Note 1)
IOL = 3.2 mA (Note 1)
IOL = 7.0 mA (Note 1)
IOH = -10 p.A
IOH = -30 p.A
IOH = -60 p.A
IOH = - 200 p.A
IOH = -3.2mA
IOH = -7.0mA
0.3
V
IOL
0.45
V
IOL
1.0
V
0.3
V
0.45
V
1.0
V
Vee- 0.3
V
Vee- 0.7
V
Vee- 1.5
V
Vee- 0.3
V
Vee- 0.7
V
Vee- 1.5
V
7-178
Test Conditions
infel .
87C52·20/80C52·20/80C32·20
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
IlL
III
ITL
Parameter
Min
Typ
(Note 4)
~aJ!:
Unit
-50
/LA
Logical 0 Input Current
(Ports 1, 2 and 3)
Commercial
Express
-7Ei
Input Leakage Current (Port 0)
Commercial
Express
±10
±15
Logical 1 to 0 Transition Current
(Ports 1 , 2 and 3)
Commercial
Express
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
Icc
Power Supply Current:
Active Mode
Commercial
Express
Idle Mode (Figure 5)
Power Down Mode
50
-650
-750
/LA
300
Kn
10
24
47.1
55
8
5
/LA
11.4
75
Test Conditions
VIN = 2.0V
VIN = VIL or VIH
VIN = 2.0V
pF
@1 MHz, 25°C
rnA
rnA
rnA
(Note 3)
/LA
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed, on the VOLS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be ~esirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vee for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
e;. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per B-bit portPorto:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
'
7-179
infel·
87C52-20/80C52-20/80C32-20
50mAr----------~r----------~------------~------------_r---------~
40mA~---------_4~----------4---------+--------~~~--~
30mA~------~~------~----~--~~------~------~
8XC52
20mA~--~---_4~--~~~--------~------~~~~----~
10mAt;~~~=:J
ID~[ TYPICA~ (4)
OmA
OMHz
4MHz
8MHz
12MHz
1SMHz
20MHz
272272-7
Icc Max at other frequencies is given by:
Active Mode
Icc Max = 2.2 X FREQ + 3.14
Idle Mode
Icc Max = 0.49 X FREQ + 1.6
Where Osc Freq Is in MHz, Icc Is in mAo
272272-8
All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 6. Icc Test Condition,
Active Mode
Figure 5. Icc vs Frequency
CLOCK
SI""AL
272272-10
272272-9
All other pins disconnected
All other pins disConnected
TCLCH = TCHCL = 5 ns
Figure 8. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 6.0V
Figure 7. ICC Test Condition Idle Mode
272272-11
Figure 9. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TClCH = TCHCl = 5 ns
7-180
int:eL
87C52-20/80C52-20/80C32-20
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P:PSEN
0: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions) Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Variable Oscillator
Min
Min
Max
3.5
20
Max
1/TCLCL Oscillator Frequency
Units
MHz
TLHLL
ALE Pulse Width
60
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
10
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
20
TCLCL-30
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
20
TCLCL-30
TPLPH
PSEN Pulse Width
105
3TCLCL-45
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
IrPXIZ
Input Instruction Float After PSEN
30
TCLCL-20
ns
TAVIV
Address to Valid Instruction In
145
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
TRLRH
RD Pulse Width
200
6TCLCL-100
TWLWH WR Pulse Width
200
6TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
125
60
0
ns
4TCLCL-75
ns
ns
ns
3TCLCL-90
0
ns
ns
ns
ns
5TCLCL-95
ns
40
2TCLCL-60
ns
155
0
0
ns
TLLDV
ALE Low to Valid Data In
310
8TCLCL-90
ns
TAVDV
Address to Valid Data In
360
9TCLCL-90
ns
TLLWL
ALE Low to RD or WR Low
100
200
3TCLCL-50 3TCLCL+50
ns
TAVWL
Address Valid to WR Low
110
4TCLCL-90
ns
15
TCLCL-35
ns
TWHOX Data Hold after WR
.10
TCLCL-40
ns
TOVWH Data Valid to WR High
280
7TCLCL-70
TOVWX Data Valid before WR
TRLAZ
RD Low to Address.Float
TWHLH
RD or WR High to ALE High
0
10
7-181
90
TCLCL-40
ns
0
ns
TCLCL+40
ns
87C52-20/80C52-20/80C32-20
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _. I
PSEN _ _.I
PORT 0
---'
PORT 2
A8 - A 15
272272-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
t------TLLDV
'I
---00++-- TRLRH
PORTO
INSTR. IN
PORT 2
P2.0-P2.7 OR A8-A 15 FROM DPH
A8-A 15 FROM PCH
272272-13
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLLWL --"*---TWLWH
I---l---TQVWH
PORTO
AO-A7
---I
----I
DATA OUT
rROM RI OR DPL
INSTR. IN
~---TAVWL---~
PORT 2
_-",~_ _ _ _ _ _ _ _ _ _ _ _ _ _J
P2.0-P2.7 OR A8-A 15 FROM DPH
A8-A 15 FROM PCH
272272-14
7-182
intel~
87C52-20/80C52-20/80C32-20
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: Over Operating Conditions; Load Capacitance
Symbol
= 80 pF
Variable Oscillator
20 MHz Oscillator
Parameter
Min
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
600
12TCLCL
ns
TOVXH
Output Data Setup to Clock
Rising Edge
367
1OTCLCL -133
ns
TXHOX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-50
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
1OTCLCL -133
367
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
0
3
2
4
5
6
7
8
ALE
CLOCK
~ITXHQX
OUTPUTOATA
I
WRITE TO
\
IX
0
j
1
I:
IX
X
2
3
-lrTXHDX
SBUF
TXHDV
INPUT DATA - - - -......Ulv":':'AL:-::IDV-"""'r.A~LI~Dr--v:~AL~IDV-"""\.o~,.,.~~~-v:::~r--v.:~.,-""'\J~~
+
I
SET RI
CLEAR RI
272272-21
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
3.5
20
MHz
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272272-15
7-183
intel .
87C52-20/80C52-20/80C32-20
AC TESTING INPUT, OUTPUT WAVEFORMS
)xC
vee-aoS=>< 0.2 vee + 0.9
0.45 V
FLOAT WAVEFORMS
__0_.2_Vee~-_0_.1_ _ _~
nMING REFERENCE
POINTS
.
272272-16
AC Inputs during testing are driven at Vcc-0.5V for a Logic "I"
and 0.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "I" and Vil max for a Logic "0".
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH :> ± 20 rnA.
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig~until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5 respectively for AO-A 13.
DATA LINES: PO.0-PO.7 for 00-07;
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
Table 2. EPROM Programming Modes
RST
PSEN
ALEI
PROG
EAI
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
H
L
I.S
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
I.S
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
I.S
. 12.75V
H
H
H
H
H
Bit 2
H
L
I.S
12.75V
H
H
H
L
L
Bit3
H
L
I.S
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Mode
Program Code Data
Read Signature Byte
7-184
87C52-20/80C52-20/80C32-20
+5V
vee
87e52
"fA/vpp
ALE/PROG 1-__
}
PROGRA~
SIGNALS
PSEN
P2.7
P2.6
XTAL 2
P3.7
CONTROL SIGNALS·
P3.6
P3.3
XTAL 1
RST
vss
272272-18
·See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C52-20 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAM VERIFY
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C52-20.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
X
ADDRESS
X_1_4_B_IT_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
DATA
X_8_BIT_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
CONTROL
SIGNALS
7 BITS
X
12.75V
"fA/vpp
X
X
-----~--
J
5V..J
TGLGH
ALE/PROG
272272-19
5 Pulses
Figure 11. Programming Signal's Waveforms
7-185
int:et
87C52-20/80C52-20/80C32-20
Reading the Signature Bytes
The 87C52-20/80C52-20 each has 3 signature
bytes in locations 30H, 31 H, and 60H. To read these
bytes follow the procedure for EPROM verify, but
activate the control lines provided in Table 2 for
Read Signature Byte.
Content
Location
30H
31H
60H
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
87C52-20
80C52-20
89H
58H
52H
89H
·58H/53H
52H/12H
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-secl cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
Erasure Characteristics
(Windowed Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA
=
21°C to 27"C; Vee
Symbol
=
5V ±20%;
vss
=
OV)
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
4
Units
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
p.s
TGHSL
Vpp Hold after PROG
10
p.s
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
110
p.s
48TCLCL
48TCLCL
7-186
48TCLCL
p.s
intel·
87C52-20/80C52-20/80C32-20
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
VERifiCATION
PROGRAMMING
P1.0-Pl.7 _ _ _ _ _<=:::!§!~:
P2.0-P2.S
ADDRESS
TAVQV
PO-----1~=~~!::::::~-------1~DA~T~A~OU~T::~------TDVGL
ALE/Pif<=
vcc-o.s=x 0.2 Vee + 0.9
TIMING REFERENCE
POINTS
VLOAD
0.2 Vee-O.1
~
0.45 V
270816-17
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOLIIOH = ± 20 mAo (·L. IOLIIOH = ± 10 mAl
270816-16
AC Inputs during testing are driven at Vcc-0.5V for a Logic "I"
and 0.45V for a Logic "0". TIming !"easurements are made at VIH
min for a Logic "I" and VIL max for a Logic "0".
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAIVpp is held at logic hig.!!...!Jntii just before ALEI
PROG is to be pulsed. The EAIVpp is raised to Vpp,
.ALE/PROG is pulsed low and then EAIVpp is re~
turned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.S respectivelyfor AO-A13.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAIVpp
NOTE:
Exceeding the Vppmaximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
Table 2. EPROM Programming Modes
Mode
RST
PSEN
ALEI
PROG
EAI
L
L.r
12.7SV
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
L
H
H
H
H
Program Code Data
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
L.r
12.7SV
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
L.r
12.7SV
H
H
H
H
H
Bit 2
H
L
L.r
12.7SV
H
H
H
L
L
L
L.r
12.7SV
H
L
H
H
L
L
H
H
L
L
L
L
L
Bit 3
Read Signature Byte
H
H
i
7-200
int'el.
87C54/80C54
+5V
vee
87C54
AO-A7
A8-A 13
EA/Vpp
ALE!PROO
1-__}
PROGRA~
SIGNALS
PSEN
P2.7
P2.6
XTAL2
P3.7
CONTROL SIGNALS'
P3.6
P3.3
XTAL 1
RST
VSS
270816-18
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C54 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±0.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
ADDRESS
PROGRAM VERIFY
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C54.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
X_ _ _ _X
14 BITS
X________________X
X_________________X
DATA
8 BITS
CONTROL
SIGNALS
7 BITS
12.7SV
EA/Vpp
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
SV
..J
TGHGL
TGLGH
-/1--
'--
ALE/PRoG
5 Pulses
Figure 11. Programming Signal's Waveforms
7-201
270816-19
87C54/80C54
Reading the Signature Bytes
The 87C54/80C54 each has 3 signature bytes in locations 30H, 31 H, and SOH. To read these bytes follow the procedure for EPROM verify, but activate
the control lines provided in Table 2 for Read Signature Byte.
Content
Location
30H
31H
SOH
87C54
8OC54
89H
58H
54H
89H
58H
54H/14H
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-secl cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
. should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
Erasure Characteristics
(Windowed Packages Only)
Erasure of the EPROM· begins to occur when the
chip is exposed to light with wavelength shorter than
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C; Vee = 5V ±20%; Vss = OV)
Parameter
Min
Max
Units
Vpp
Symbol
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
4
75
rnA
S
MHz
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
JLs
TGHSL
Vpp Hold after PROG
10
p.s
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
110
p.s
48TCLCL
48TCLCL
7-202
48TCLCL
p.s
intel~
87C54/80C54
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
PI.O-PI.7
P2.0-P2.S
VERIFICATION
------1~:~~~~5o::)_------C::::!A~DO~R~ES~S=:>-----50
TAVQV
PO----H::~
DATA OUT
TOVGL
TGHDX
TGHAX
ALEJiiROO
-------'\1
g
TGLGH
EA/Vpp
Vee
~
V
_ _ _......
TEHS:
CONTROL
._
SIGNALS
(ENABLE) - - - - '
P
270816-20
*5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
DATA SHEET REVISION HISTORY
The following differences exist between this data
sheet (270816-004) and the previous version
(270816-003):
1. Added 3.3V device to data sheet.
2. Data sheet status changed from "Preliminary"
to "Production".
3. References to second functions of Port 1.2thru
Port 1.7 pins have been removed.
4. The Operating Temperature Range has been
changed to: O°C to + 70°C.
The following differences exist between the -003
and -002 versions of this data sheet:
1. QFP package type added.
2. "NC" pin labels changed to "Reserved" in Figure 2.
3. 8ja and 8jc information added to Packages table.
4. Capacitor value for ceramic resonators deleted
in Figure 3.
5. Pin numbers deleted from Figure 10.
6. Second paragraph under "Encryption Array"
section added.
7. All references to Program Lock Bit and Encryption Array deleted from "Program Verification"
section. This information is available in the hardware description.
The following differences exist between the -002
and the -001 versions of the 87C54/80C54 data
sheet:
1. Changed data sheet status from "Advanced" to
"Preliminary" .
2. Added "Four-Level Interrupt Priority" feature
bullet.
3. Revised RST pin description.
4. Changed Figure 3 to read "= 40 pF ± 10 pF for
Ceramic Resonators".
5. Added VIL 1 specification to DC Characteristics
table.
6. Changed test conditions under III from OV to
0.45V for VIN minimum.
7. Revised Absolute Maximum Ratings warning
and data sheet status notice.
8. Reworded DC Characteristics Note 1.
9. Changed 1/TCLCL Minimum specification from
0.5 MHz to 3.5 MHz.
10. Deleted -2 reference in "External Clock Drive"
table.
11. Revised "ROM and EPROM Lock System" section.
7-203
87C54/80C54
EXPRESS
87CS4/80CS4--3.S MHz to 12 MHz, Vee = SV ± 20%
87CS4-1/80CS4-1-3.S MHz to 16 MHz, Vee = SV ± 20%
•
Extended Temperature Range
iii Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs. of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125·C with Vee = 6.9V
guidelines in MIL-STD-883, Method 1015.
± 0.25V, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial 87C54/80C54 data
sheet, 270816-002.
7-204
October 1990
Order Number: 270901-001
87C54/80C54 EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
O.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS
TA
= -40°C to +S5°C;Vcc = 5V ±20%;Vss = OV
Limits
Parameter
Symbol
Min
-750
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
ITL
Max
Unit
Test
Conditions
!LA
VIN = 2V
Table 1. Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
0'
Cerdip
Commercial
No
N
PLCC
Commercial
No
TP
Plastic
Extended
No
TO'
Cerdip
Extended
No
TN
PLCC
Extended
No
LP
Plastic
Extended
Yes
LO'
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
'Available for 87C54 only.
NOTE:
• Commercial temperature range is O·C to 70°C. Extended temperature range is - 40·C to + 85·C.
• Burn-in is dynamic for a minimum time of 168 hours at 125'C, Vee = 6.9V ±0.25V, following guidelines in MIL-STD-883
Method 1015 (Test Condition D).
Examples:
PSOC54 indicates SOC54 in a plastic package and specified for commercial temperature range, without burn-in.
LOSOC54 indicates SOC54 in a cerdip package and specified for extended temperature range with burn-in.
DATA SHEET REVISION SUMMARY
This is Rev. 1 of the SOC54/S7C54 Express data sheet.
7-205
infel~
87C54-20/-3
80C54-20/-3
COMMERCIAL/EXPRESS 20 MHz MICROCONTROLLER
87C54-20/80C54-2D-3.5 MHz to 20 MHz, Vee = 5V ± 20%
87C54-3/80C54-3-24 MHz Internal Operation, Vee = 5V ± 20%
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
24 MHz Internal Operation (-3 only)
Three 16-Bit Timer/Counters
Programmable Clock Out
Up/Down Timer/Counter
Three Level Program Lock System
16K On-Chip EPROM/ROM
256 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
32 Programmable I/O Lines
•
•
•
•
•
•
•
•
•
6 Interrupt Sources
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory $pace
64K External Data Memory Space
MCS®-51 Compatible Instruction Set
Power Savln~ Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
Four-Level Interrupt Priority
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16 Kbytes of the program memory can reside in the on-chip EPROM. The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x a on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel aXC54-20/-3 is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the aXC54-20/-3 uses the same powerful
instruction set, has the same architecture, and is. pin-for-pin compatible with the existing MCS-51 family of
products. The aXC54-20/-3 is an enhanced version of the a7C51 /aOC51 BH. Its added features make it an
even more powerful microcontroller for applications that require clock output, and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-processor communications.
The a7C54-3/aOC54-3 has the. same 3.5 MHz to 20 MHz frequ('jncy range as the a7C54-20/aOC54-20 when
operating out of ('jxternal program/data memory. When running out of internal program/data memory, the
a7C54-3/aOC54-3 can operate up to 24 MHz.'
Throughout this document aXC54-20 will refer to the a7C54-20, aOC54-20, a7C54-3 and the aOC54-3.
7-206
October 1992
Order Number: 270941.003
intel·
87C54-20/-380C54-20/-3
PO.O- PO.7
r---------- ~~~~~
V~
..c
VSS
PSEN
ALE/PIfO"C
rJ./VPP
RST
TIMING
CO~~~OL
~IJL---.;::.:;...-....:..:;......----L..l.-~.:...--~L------'
~"'"----=-------,....,..-----r-r---....,.:-----.c/l
0:
Pl.0- Pl.7
P3.0-P3.7
"
270941-1
Figure 1. 8XC54-20 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III·E process. Additional process and reliability infor·
mation is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
7·207
intel·
87C54-20/-380C54-20/-3
PACKAGES
Part
Prefix
SXCS4-20
S7CS4-20
·SXCS4-20
SXCS4-20
P
D
N
S
Package Type
BJ.
BJe
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-PinQFP
4soC/W
4soC/W
1soC/W
46°C/W
96°C/W
16°C/W
24°C/W
16"C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
(T2) Pl.0
(T2EX) Pl.l
Vee
PO.O (ADO)
Pl.2
PO.HAD1)
Pl.3
PO.2 (AD2)
Pl.4
PO.3 (AD3)
P1.S
PO.4 (AD4)
Pl.6
PO.5 (AD5)
Pl.7
PO.6 (AD6)
RESET
EA/Vpp
(TXD) P3.l
ALE/PiiOO
Go
0
f.
. ... ....,
Go
Go
Go
Pl.S
.0.4
Pl:&
PO.5
Pl.7
PO.S
RST
PO.7
lA/Vpp
P3.0
PO.7 (AD7)
(RXD) P3.0
q ~ "1 "!
ii: ii: ii: ii: >'a >8
INDEX
CORNER
RESERVED'
RESERVED-
P3.l
ALE/PiiOO
P3.2
Pmi
(iNTo) P3.2
(iiiIT) P3.3
PSEN
P3.3
P2.7
P2.7 (A15)
P3.4
P2.S
(TO) P3.4
P2.6 (A14)
P3.5
P2.5
(T1) P3.5
P2.5 (A13)
(WR) P3.6
(iiii) P3.7
P2.3 (All)
XTAL2
P2.2 (Al0)
XTAL 1
P2.l
. ...
'" ,...~.........
~ ~
(A12)
,.;
Go
~
q
~
~
~
.. .. .
"1
Go
'"
(A9)
P2.0 (AS)
Vss
::'8
PLCC
270941-2
DIP
INDEX
CORNER \
:
~
Pl.5
Pl.&
Pl.7
RST
P3.0
RESERVED'
P3.l
P3.2
P3.3
PL4
P3.5
~
~::!:: ~ ~!:l~
~
a
a
a
> > a
ci::l ci
aLL
.~!~!~ ~~!!~!~!~!=!: !~!!~!~!~
C~
L:£3
z: ~
PO.4
i{2 PO.5
(~
4.: ~
L~) PO.6
i(O PO.7
s: ~
(~
7: ~
~
(~
~~
1] ~
its
8XC54-20
.
s:
iis
LV
Lis
EA/Vpp
RESERVED"
ALE/PiiOO
PSEN
iZ:5 P2.7
......................................
:'ii
P~6
i(3 P2.5
I~II~II:!II~II~II~II~II~II~IINII~I~
270941-4
QFP
°00 not 'connect reserved pins.
Figure 2. Pin Connections
7-20S
~
Go
270941-3
intel~
87CS4-20/-380CS4-20/-3
PIN DESCRIPTIONS
Vee: Supply voltage.
Vss: Circuit ground.
VSS1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the Vss pin (pin 22).
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting1 's, and can source and
sink several LS TTL inputs.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1'so During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pull up resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
In addition, Port 1 serves the functions of the following special features of the 8XC54-20:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
P1.1
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIHI voltage is applied whether
the oscillator is running or not. An internal pulldown
resistor permits a power-on reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C54-20.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pull c
ups.
7-209
87C54-20/-380C54-20/-3
If desired, ALE operation can be disabled by setting
bit 0 of SFR location BEH. With the bit set, ALE isactive only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the
ALE-disable bit has no effect if the microcontroller is
in external execution mode.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
To drive the device from an extern·al clock source,
XTAL1 should be driven, while XTAl2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock Signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed...
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
When the BXC54-20 is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two ~ activations
are skipped during each access to external Data
Memory.
EAlVpp: External Access enable. EA must be
strapped to Vss .in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
EA should be strapped to Vee for internal program
executions.
NIC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL t
Vss
270941-6
Figure 4. External Clock Drive Configuration
IDLE MODE
XTAl2: Output from the inverting oscillator amplifier.
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs.
OSCILLATOR CHARACTERISTICS
POWER DOWN MODE
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which -can be configured for use as an on-Chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in ~ppli
cation Note AP-155, "Oscillators for Microcontrollers."
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
c
~
0
XTAL2
On the BXC54-20 either a hardware reset or .an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
Ct
XTALt
Vss
Cl. C2 = 30 pF ± HlpF for Crys1als
270941-5
For Ceramic Resonators. contact resonator manufacturer_
To properly terminate Power down the reset or external interrupt should not be executed before Vee is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
.
Figure 3. Oscillator Connections
7-210
intet
87C54-20/-380C54-20/-3
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
TIMER 2 PROGRAMMABLE
CLOCK OUT
The 8XC54-20 has a new Timer 2 feature. A 50%
duty cycle clock can be programmed to come out on
P1.0. The output frequency ranges from 61 Hz to
4 MHz depending on the oscillator frequency and
the reload value of the Timer 2 capture registers
(RCAP2H, RCAP2L) as shown in the equation below:
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared, and bit
T20E in T2MOD must be set. Bit TR2 (T2CON.2)
starts and stops the timer.
For a complete description of all Timer 2 functions,
please reference the 8XC52/54/58 Hardware Description of the 8-Bit Embedded Controllers Handbook.
'NOTE:
Even though the equation permits a maximum
clock-out frequency of 5 MHz using a 20 MHz oscillator, the maximum device output frequency is
4 MHz. When using a 20 MHz oscillator, RCAP2L
must be limited to a maximum value of FEH.
DESIGN CONSIDERATION
• When running out of internal program/data memory, the 87C540-3/80C54-3 can be operated using
a 24 MHz clock. If the 87C54-3/80C54-3 is running out of external program/data memory, the
operating frequency must be between 3.5 MHz to
20 MHz. The 87C54-3/80C54-3 will not function
properly at 24 MHz when running out of external
program/data memory.
• The window on the 87C54-20 must be covered
by an opaque label. Otherwise, the DC and AC
characteristics may not be met, and the device
may functionally be impaired.
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-Chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
ONCE MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC54-20 without the 8XC54-20 having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC54-20 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Mode
Idle
Idle
Power Down
Power Down
Table 1_ Status of the External Pins during Idle and Power Down
Program
PSEN
PORTO
PORT1
PORT2
ALE
Memory
Internal
1
1
Data
Data
Data
External
1
Float
Data
Address
1
Internal
0
Data
Data
Data
0
0
External
Data
Data
0
Float
PORT3
Data
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the BOC51 BH."
7-211
87C54-20/-380C54-20/-3
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature Under Bias. -40·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
Voltage· on EAlVpp Pin to Vss ....... OV to + 13.0V
• WARNING: Stressing the device lJeyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V
IOL Per 1/0 Pin ........................... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
-40
+70
+85
·C
·C
Vee
Supply Voltage
4.0
6.0
V
fose
Oscillator Frequency
3.5
20
MHz
TA
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
Typ
(Note 4)
Min
Max
Unit
-0.5
0.2Vee- 0.1
V
Test Conditions
VIL
Input Low Voltage
VIL1
Input Low Voltage EA
0
0.2 Vee-0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2 Vee+0.9
Vee + 0.5
V
VIH1
Input High Voltage
(XTAL 1, RST)
0.7 Vee
Vee+ 0.5
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
V
IOL = 100 /LA (Note 1)
0.45
V
IOL = 1.6 mA (Note 1)
1.0
V
IOL = 3.5 mA (Note 1)
0.3
V
IOL = 200 /LA (Note 1)
0.45
V
IOL = 3.2 mA (Note 1)
VOL1
,
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
1.0
VOH
VOH1
IlL
Output High Voltage
(Ports 1, 2 and 3, ALE, PSEN)
Output High Voltage
(Port 0 in External Bus Mode)
V
IOL = 7.0 mA (Note 1)
Vee- 0.3
V
IOH = -10/LA
Vee~0.7
V
IOH = -30/LA
Vee- 1.5
V
IOH = -60/LA
Vee- 0.3
V
IOH = - 200 /LA
Vee- 0.7
V
IOH = -3.2mA
Vee- 1.5
V
IOH = -7.0mA
-50
Logical 0 Input Current
(Ports 1, 2 and 3)
7-212
/LA VIN = 0.45V
87C54-20/-380C54-20/-3
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
III
Input Leakage Current (Port 0)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Commercial
Express
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
Icc
Power Supply Current:
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
Min
Typ
(Note 4)
40
Max
Unit
±10
p.A
0.45
-650
-750
p.A
p.A
VIN = 2V
225
K!l.
pF
10
Test Conditions
< VIN < Vcc
@1 MHz, 25°C
(Note 3)
20
5
15
40
10
100
mA
mA
p.A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOlS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vee for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOl must be externally limited as follows:
Maximum IOl per port pin:
10 mA
Maximum IOl per B-bit portPort 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOl for all output pins:
71 mA
If IOl exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7-213
87C54-20/-380C54-20/-3
70mA
/'
60mA
SOmA
"Om ...
30mA
/"
20mA
. /V
lOrnA
A/
"':r
V
/
'~
~
....-
IDLE WAX.
/~
IDLE
--
axes"
2Z0941-8
All other pins disconnected
TCLCH = TCHCL = 5 ns
TYPICAL (4)
OmA
OMHz
... t.lHz
8WHz
12 101Hz
16WHz
Figure 6. Icc Test Condition, Active Mode
20t.lHz
270941-7
ICC Max at other frequencies is given by:
Active Mode
Icc Max = (Osc Freq x 3) + 4
Idle Mode
Icc Max = (Osc Freq x 0.5) + 4
Where Osc Freq is in MHz, Icc is in rnA.
Figure 5. Icc vs Frequency
axcs.
270941-10
270941-9
All other pins disconnected
All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 8. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 6.0V
Figure 7. Icc Test Condition Idle Mode
270941-11
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
7-214
intel~
87C54-20/-380C54-20/-3
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of aU the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P:PSEN
Q: Output Data
A: AD signal
T:Time
V: Valid
W: WA signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions) Load Capacitance for Port 0, ALE/PAOG and
PSEN = 100 pF, Load Capacitance for AU Other Outputs = BO pF)
.
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Variable Oscillator
Min
Min
Max
3.5
20
Max
1/TCLCL Oscillator Frequency
TLHLL
ALE Pulse Width
TAVLL
Units
MHz
60
2TCLCL-40
ns
Address Valid to ALE Low
10
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
20
TCLCL-30
TLLlV
ALE Low to Valid instruction In
TLLPL
ALE Low to PSEN Low
20
TCLCL-30
ns
TPLPH
PSEN Pulse Width
105
3TCLCL-45
ns
125
ns
4TCLCL-75
ns
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
30
TCLCL-20
ns
TAVIV
Address to Valid Instruction In
145
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
TALAH
AD Pulse Width
200
6TCLCL-100
TWLWH WA Pulse Width
200
6TCLCL-100
60
0
TALDV
AD Low to Valid Data In
TAHDX
Data Hold After AD
TAHDZ
Data Float After AD
TLLDV
TAVDV
TLLWL
ALE Low to AD or WA Low
100
TAVWL
Address Valid to WA Low
3TCLCL-90
0
ns
ns
ns
5TCLCL-95
ns
40
2TCLCL-60
ns
ALE Low to Valid Data In
310
BTCLCL-90
ns
Address to Valid Data In
360
9TCLCL-90
ns
200
3TCLCL-50 3TCLCL+50
ns
110
4TCLCL-90
ns
TQVWX Data Valid before WA
15
TCLCL-35
ns
TWHQX Data Hold after WA
10
TCLCL-40
ns
2BO
7TCLCL-70
ns
TQVWH Data Valid to WA High
TALAZ
AD Low to Address Float
TWHLH
AD or WA High to ALE High
155
ns
0
0
0
10
7-215
90
TCLCL-40
ns
0
ns
TCLCL+40
ns
inlet..
87C54-20/-380C54-20/-3
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _..I
PSEN _ _..I
TPXIZ
PORT 0
PORT 2
----
AO-A7
A8-A15
----'
270941-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
j.-----TLLDV
-------1----
'I
TRLRH
--~
PORTO
PORT2
INSTR. IN
_--'~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A 15 FROM PCH
270941-13
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
~TLHLL--OO
PORTO
PORT2
::::r
=>
1
i==I-TWHLH
~TLLWL
TAVLL ~
,
\.
J
TWLWH
I
~TLLAX- ~
-.
..-TWHQX
TQVWH
FROIt~iSk
DPL
DATA OUT
AO-A7 FROM PCL
INSTR. IN
TAVWL
P2.0-P2.7 OR A8-A 15 FROM DPH
A8-A 15 FROM PCH
270941-14
7-216
intel"
87C54-20/-380C54-20/-3
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions:
Symbol
Over Operating Conditions; Load Capacitance = 80 pF
20 MHz Oscillator
Parameter
Min
Variable Oscillator
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
600
12TCLCL
ns
TOVXH
Output Data Setup to Clock
Rising Edge
367
1OTCLCL -133
ns
TXHOX
Output Data Hold after
Clock Rising Edge
SO
2TCLCL-SO
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
1OTCLCL -133
367
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
0
2
3
5
4
7
6
8
ALE
CLOCK
X
2
OUTPUT DATA
I
3
X
4
X
5
X
6
X
I
7
t
SET TI
INPUT DATA ----_.,.r.:":~-~~r_"Y':=.r__y~'V""_~~_.,.r.:":~-'\A"!':~r_"Y':~
ALlO
AUO
ALlD
WRITE TO SBUF
t
I
SET RI
CLEAR RI
270941-15
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
3.S
20
MHz
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270941-16
7·217
87C54-20/-380C54-20/-3
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC- 0.5
0.45
-y-
FLOAT WAVEFORMS
>C
0.2 VCC+ 0.9
nMING REFERENCE
. VLOAD
v-A_0._2..,.;VCC~-_0._1_ _ _.
POINTS
270941-18
For Uming purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;, ±20 mA.
270941-17
AC Inputs during testing are driven at Vcc-0.5V for a Logic "1"
and 0.45V for a Logic "0". nming measurements are made at VIH
min for a Logic "1" and Vil max for a Logic "0".
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig~ntil just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
ALE/PROG is pulsed low and then EAlVpp is re~
turned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5 respectively for AO-A13.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
Table 2. EPROM Programming Modes
PSEN
ALEI
PROG
EAt
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
'H
L
l..J
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
l..J
12.75V
L
H
H
L
H
Program Lock
Bits
H
L
l..J
12.75V
H
H
H
H
H
RST
Mode
Program Code Data
Bit 1
Bit2
H
L
l..J
12.75V
H
H
H
L
L
Bit 3
H
L
l..J
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Read Signature Byte
7-218
87C54-20/-380C54-20/-3
+5V
vee
87e54
EA/Vpp
}
ALE/PROG
PROGRA~
SIGNALS
PSEN
P2.7
P2.6
XTAL 2
P3.7
CONTROL SIGNALS'
P3.6
P3.3
XTAL 1
RST
Vss
270941-19
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
PROGRAM VERIFY
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C54-20 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C54-20.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
4. Raise EAlVpp from Vee to 12.75V ±0.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
ADDRESS
DATA
CONTROL
SIGNALS
X. . .
X__________________X
X___________--------X
5V..J
8 BITS
7 BITS
12.75V
EA/Vpp
X
l_4_B_IT_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
,.------------------.'--
TGLGH
ALE/PROG
270941-20
5 Pulses
Figure 11. Programming Signal's Waveforms
7-219
87C54-20/-380C54-20/-3
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources ove.r' an' extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
Reading the Signature Bytes
The 87C54-20/80C54-20 each has 3 signature
bytes in locations 30H, 31H, and 60H. To read these
bytes follow the procedure for EPROM verify, but
activate the control lines provided in Table 2 for
Read Signature Byte.
Location
30H
31H
60H
Content
87C54·20
80C54-20
89H
58H
54H
89H
58H
54H/14H
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 }J-W/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
Erasure Characteristics
(Windowed Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27"C; Vee = 5V ±20%;
vss
= 0V)
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
Symbol
4
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
48TCLCL
48TCLCL
Units
TGHAX
Address Hold after PROG
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
}J-s
TGHSL
Vpp Hold after PROG
10
p.s
90
TGLGH
PROGWidth
TAVOV
Address to Data Valid
TELOV
ENABLE Low to Data Valid
TEHOZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
110
}J-s
48TCLCL
i
48TCLCL
7-220
. 48TCLCL
}J-s
intel.,
87C54-20/-380C54-20/-3
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
VERIFICATION
-----1::~~~~
PLO-Pl.'
P2.0-P2.S
ADDRESS
TAVQV
PO _ _ _ _
~~
TDVGl
AlE/PRiiii
DATA OUT
TGHDX
-----~
'fA/Vpp
TEHQZ
-:::::
~~~~~~(ENABLE)
270941-21
NOTE:
·5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits
DATA SHEET REVISION HISTORY
The following differences exist between this data sheet (270941-003) and the previous version (270941-002):
1, Added 87C54-3/80C54-3 to 20 MHz data sheet.
2. Added EXPRESS version of 8XC54-20/-3 to 20 MHz data sheet.
3. References to second functions of Port 1.2 thru Port 1.7 pins have been removed.
4. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
TLLlV
From
120
4TCLCL-80
To
125
4TCLCL-75
TPLIV
3TCLCL-95
3TCLCL-90
TWHOX
0
TCLCL-50
10
TCLCL-40
TOVWH
200
7TCLCL-150
280
7TCLCL-70
The following differences exist between the -002 and -001 versions of this data sheet:
1. "NC" pin labels changed to "Reserved" in Figure 2.
2. 9ja and 9jc information added to Packages table.
3. Capacitor value for ceramic resonators deleted in Figure 3.
4. Serial Port Tfmings under "20 MHz Oscillator" corrected to agree with the variable oscillator equations for
TXLXL, TOVXH and TXHDV.
5. Pin numbers deleted from Figure 10.
6. Second paragraph under "Encryption Array" section added
7. All references to Program Lock Bit and Encryption Array deleted from "Program Verification" section. This
information is available in the hardware description.
7-221
87C58/80C58
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 32 KBYTES INTERNAL PROGRAM MEMORY
87C58/80C58-3.5 MHz to 12 MHz, Vee = 5V ± 20%
87C58-1/80C58-1-3.5 MHz to 16 MHz, Vee = 5V ± 20%
87C58-L/80C58-L-3.5 MHz to 8 MHz, Vee = 3.3V ± .3V
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
Low Voltage Operation (-L only)
Three 16-Bit Timer/Counters
Programmable Clock Out
Up/Down Timer/Counter
Three Level Program Lock System
32K On-Chip EPROM/ROM
256 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
32 Programmable I/O Lines
•
•
•
•
•
•
•
•
•
6 Interrupt Sources
Four Level Interrupt Priority Structure
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
MCS®-51 Compatible Instruction Set
Power Saving Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on-chip EPROM. The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontrolier has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C58/80C58 is a single-chip control-oriented microcontrolier which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 87C58/80C58 uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 87C58/80C58 is an enhanced version of the 87C51 /80C51 BH. It's added features make it an
even more powerful microcontrolier for applications that require clock output, and up/down counting capabilities such as motor control. It also has a more versatile serial chan riel that facilitates multi-processor communications.
Applications that require low voltage can use the 87C58-L/80C58-L. The 8XC58-L will operate at 3.3V
a frequency range of 3.5 MHz to 8 MHz.
± .3V at
Throughoutthis document 8XC58 will refer to both the 87C58 and the 80C58.
7-222
October 1992
Order Number: 270900-003
infel~
87C58/80C58
PO.O-PO.7
,. --
----------,
V~
VSS
E
PSEN
ALE/~
EA/VPP
RST
TIMING
AND
CONTROL
'"
~~::::~~~~::::::::~~::~::::~~:::::;~~::~
'"
- - ...
P3.0-P3.7
PLO - Plo7
270900-1
Figure 1. 8XC58 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS .
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
7-223
87C58/80C58
PACKAGES
Part
Prefix
8XC58
87C58
8XC58
8XC58
P
D
N
S
Package Type
40-Pin
40-Pin
44-Pin
44-Pin
Plastic DIP (OTP)
CERDIP (EPROM)
PLCC (OTP)
QFP (OTP)
°ja
°je
45°C/W
45°C/W
46°C/W
90°C/W
16°C/W
15°C/W
16°C/W
22°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
(T2) PLO
(T2EX)
(RXD)
"': "l "!
INDEX
CORNER
Vee
PLI
PO.O (ADO)
0.
0.
;;:
0.
c;;
'"
u
~
>Vl ~:r
0.
~
.. .,
.,; .,;
0.
0.
PI.2
PO.l (AD1)
Pl.S
PL3
PO.2 (AD2)
Pl.S
PO.S
PI.4
PO.3 (AD3)
PL7
PO.6
PLS
PO.4 (AD4)
RST
PLS
PO.S (ADS)
P3.0
PI.7
PO.S (ADS)
RESERVED"
RESET
PO.7 (AD7)
P3.1
ALE!PROO
EA/Vpp
P3.2
PSEN
P3.0
(TXD) P3.1
PO.4
PO.7
fA/vpp
RESERVED·
ALE!PROO
P3.3
P2.7
(iNTO) P3.2
PSEN
P3.4
P2.6
(fNfl) P3.3
P2.7 (AIS)
P3.S
P2.5
(TO) P3.4
P2.S
(TI)
(AI4)
P3.S
P2.S (AI3)
(WR) P3.S
(Ril) P3.7
P2.4 (A 12)
XTAL2
P2.2 (AID)
XTAL I
P2.1
.. ...
,.;
0.
~
P2.3 (All)
vss
~
:::;
~ ~
""
0
f:'i
i:l
It:
270900-3
(A9)
PLCC
P2.0 (A8)
270900-2
DIP
INDEX
CORNER \
"': "l "!
'"
;;: ;;: ;;: ;;: ;;:
iii (,)
~
>'" >U
0.
0
.... d
.,; .,;
0.
0.
.1:11~11~11-:;11S:11~11~11::;;11~11~11~1
P1.5
1:~"-'·-·"-'''-·''''''·-·''''''''-·''_·''-'L_·L3:3 PO.4
P1.6
2: ~
L:[2
P1.7
(!
;::[1 PO.6
{~
~
RESERVED- (~
P3.1 (~
5:
P3.2
s: ~
P3.3
(!
PO.5
;fo PO.7
RST
P3.0
8XC58
Ltg
EA/Vpp
L:[8
RESERVED'
iv
ALE!PROO
;:[6 PSEN
;:~5 P2.7
.,
...
N 0.
N
0.
270900-21
*00 not connect reserved pins.
.. ., ...
'" Q
N N N N N
> '"
> 0. 0. 0. 0. 0.
QFP
Figure 2. Pin Connections
7-224
intel"
87C58/80C58
PIN DESCRIPTIONS
Vee: Supply voltage.
Vss: Circuit ground.
Vss 1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
NOTE:
This pin is not a substitute for the Vss pin (pin 22).
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1's, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
In addition, Port 1 serves the functions of the following special features of the 8XC58:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
P1.1
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pull ups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not. An internal pull-·
down resistor permits a power-on reset with only a
capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C58.
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit· bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the
ALE-disable bit has no effect if the microcontroller is
in external execution mode.
7-225
intel..
87C58/80C58
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the 8XC58 is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
Memory.
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
EA should be strapped to Vee for internal program
executions.
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
Vss
,
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
270900-5
Figure 4_ External Clock Drive Configuration
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are. the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
C2
I - -......--f XTAL2
On the 8XC58 either a hardware reset or an external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
I - -.......--f XTAL 1
t - - - - - - - - t vss
270900-4
Cl. C2 = 30 pF ± 10 pF for Cryslals
For Ceramic Resonators. contact resonator manufacturer.
Figure 3_ Oscillator Connections
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 floats, as
To properly terminate Power down the reset or .external interrupt should not be executed before Vee is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
7-226
int:et
87C58/80C58
With an external interrupt, INTO or INT1 must be enabled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
nal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
ONCE MODE
DESIGN CONSIDERATION
• The 8XC58-L will operate at 3.3V ± .3V at a frequency range. of 3.5 MHz to 8 MHz. Operating
beyond these specifications could cause improper device functionality. (To program the 87C58-L,
follow the same procedure as the 87C58.)
• The window. on the 87C58 must be covered by an
opaque label. Otherwise, the DC and AC characteristics may not be met, and the device may
functionally be impaired.
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to inter-
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the 8XC58
without the 8XC58 having to be removed from the
circuit. The ONCE Mode is invoked by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC58 is in this mode, an emulator or
test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
Idle
External
1
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
Mode
PORTO
PORT1
PORT2
PORT3
1
Data
1
Float
Data
Data
Data
Data
Address
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the 80C51 BH."
7-227
87C58/80C58
,
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Ambient Temperature Under Bias. -40·C to + 85·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V
Voltage on Any Other Pin to Vss •. -0.5V to +6.5V
IOL Per I/O Pin ........................... 15,mA
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions T A (Under Bias)
= O·C to + 70·C; Vee = 5V ± 20%; Vss = OV
(8XC58-L, Vee
=
3.3V ±.3V)
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both 5V and 3.3V devices unless otherwise indicated.
Symbol
Parameter
Typ
(Note 4)
Min
Max
Unit
Test Conditions '
VIL
Input Low Voltage
-0.5
0.2Vee- 0.1
V
VIL1
Input Low Voltage EA
0
0.2Vee- 0.3
V
VIH
Input High Voltage
(ExceptXTAL1, RST)
0.2 Vee+0.9
Vee + 0.5
V
VIH1
Input High Voltage (XTAL 1, RST)
0.7 Vee
Vee+ 0.5
V
0.3
V
IOL = 100 IJ-A (Note 1)
0.45
V
IOL = 1.6 mA (Note 1)
1.0
V
IOL = 3.5 mA (Note 1)
VOL
VOL1
VOH
VOH1
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
V
IOL = 200 /LA (Note 1)
0.45
V
IOL = 3.2 mA (Note 1)
1.0
V
IOL = 7.0 mA (Note 1)
Vee- 0.3
V
IOH = -10 IJ-A
Vee- 0.7
V
IOH = -30 IJ-A
Vee- 1.5
V
IOH = -60 IJ-A
Vee- 0.3
V
IOH = - 20,0 IJ-A
Vee- 0.7
V
IOH = -3.2mA
V
IOH = -7.0 mA
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2 and 3, ALE, PSEN)
Output High Voltage
(Port 0 in External Bus Mode)
Vee- 1.5
o
IlL
Logical Input Current
(Ports 1, 2 and 3)
III
Input leakage Current (Port 0)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
-50
±10
-650
7-228
IJ-A VIN = 0.45V
IJ-A 0.45
< VIN < Vee
IJ-A VIN = 2V
87C58/80C58
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to both 5V and 3.3V devices unless otherwise indicated.
Symbol
Parameter
Typ
(Note 4)
Min
RRST
RST Pulldown Resistor
40
CIO
Pin Capacitance
Icc
Power Supply Current:
Active Mode
8XC58-L at 8 MHz
All others at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
Max
Unit
225
Kn
10
pF
Test Conditions
@1 MHz, 25°C
(Note 3)
20
5
15
12
40
10
100
mA
mA
mA
p.A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOlS of ALE and
Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
o.av. It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vce specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vcc for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOl must be externally limited as follows:
Maximum IOl per port pin:
10mA
Maximum IOl per a-bit portPort 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOl for all output pins:
71 mA
If IOl exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
60 rnA
SOmA
40 rnA
30 rnA
20 rnA
lOrnA
ornA
OMHz
TYPICAL (4)
IDLE
4MHz
8MHz
ICC Max at other frequencies is given by:
Active Mode
Icc Max = (Osc Freq X 3) + 4
Idle Mode
ICC Max = (Osc Freq X 0.5) + 4
Where Osc Freq is in MHz, Icc is in rnA.
Figure
5. Icc vs Frequency
7-229
12MHz
16MHz
270900-6
int:el..
87C58/80C58
Vee
Vee
Vee
lice
,
Vee
Vee
PO
PO
EA I+-_.J
RST
RST
8XC58
8XC58
CLOCK (NC)
SIGNAL
EA 1---.,
XTAL2
XTALI
VSS
XTAL2
- - - + I XTALI
VSS
270900-8
270900-7
All other pins disconnected
TCLCH = TCHCL = 5 ns
All other pins disconnected,
TCLCH = TCHCL = 5 ns
Figure 7. Icc Test Condition Idle Mode
Figure 6. Icc Test Condition, Active Mode
Vee
PO
EA 1---,
RST
8XCS8
XTAL2
XTAL1
VSS
270900-9
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 6.0V
Vee-O.S • - - - - - -..r~----"""
0.7 Vee
0.45V---TciO.2 Vee-c.l
TCHCL
270900-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns
7-230
infel .
87C58/80C58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
P:PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
A: Address
C: Clock
For example,
D: Input Data
H: Logic level HIGH
TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents)
TLLPL = Time from ALE Low to PSEN Low
L: Logic level LOW, or ALE
AC CHARACTERISTICS· (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oscillator
Min
Max
Variable Oscillator
Min
Max
3.5
16
Units
1/TCLCL
Oscillator Frequency
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
53
TCLCL-30
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
53
205
ns
4TCLCL-100
234
MHz
TCLCL-30
ns
ns
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
59
TCLCL-25
ns
TAVIV
Address to Valid Instruction In
312
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
TRLRH
RD Pulse Width
400
6TCLCL-100
TWLWH
WR Pulse Width
400
6TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
107
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
ns
TAVDV
Address to Valid Data In
585
9TCLCL-165
ns
TLLWL
ALE Low to RD or WR Low
200.
3TCLCL+50
ns
TAVWL
Address Valid to WR Low
203
4TCLCL-130
TOVWX
Data Valid before WR
33
TCLCL-50
ns
TWHOX
Data Hold after WR
33
TCLCL-50
ns
TOVWH
Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
3TCLCL-45
145
0
ns
3TCLCL-105
252
0
ns
ns
5TCLCL-165
0
300
3TCLCL-50
0
43
123
7-231
TCLCL-40
ns
ns
ns
7TCLCL-150
433
ns
ns
0
ns
0
ns
TCLCL+40
ns
infel·
87C58/80C58
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _. I
PORT 0 _ _. I
PORT 2
_ _ _ _ _ _ _,,~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ J
A8-A15
270900-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
i--------TLLDV
"
-'---0'1--- TRLRH - - - - I
PORTO
INSTR. IN
PORT2 __~,~________~P2~.~O-~P~2~.7~O~R~A~8~-~Al~5~F~R~O~~~D~PH~________,~__~A~8-~A~I~5~F~RO~~~PC~H~__
270900-12 '
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
~TLHLL~
I
\.
~
i=l-lWHLH
~
!---TLLWL
.....
TAVLL
Ii-TLLAX-
PORTO
PORT 2
:::r
-
~
lWLWH
,
...J
~
r-lWHQX
TQVWH
rRo.t~i~~
DATA OUT
DPL
K
AO-A7
rRO~
PCL
INSTR. IN
TAVWL
P2.0-P2.7 OR A8-A15
FRO~
DPH
X
A8-A15 FROM PCH
270900-13
7-232
intel..
87C58/80C58
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions:
Symbol
Over Operating Conditions; Load Capacitance
Parameter
12 MHz Oscillator
Min
Max
= 80 pF
Variable Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1
12TCLCL
fJ-s
TOVXH
Output Data Setup to Clock
Rising Edge
700
1OTCLCL -133
ns
TXHOX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
700
SHIFT REGISTER MODE TIMING WAVEFORMS
7-233
1OTCLCL -133
ns
int'el.,
87C58/80C58
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TClCl
Oscillator Frequency
8XC58
8XC58-1
3.5
3.5
12
16
MHz
TCHCX
High Time
20
TClCX
low Time
20
ns
ns
TClCH
Rise Time
20
TCHCl
Fall Time
20
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270900-15
FLOAT WAVEFORMS
AC TESTING INPUT, OUTPUT WAVEFORMS
vee-o.s=>( 0.2 vee+O.9
D.45V
>C
TIMING REFERENCE
POINTS
0.2 vee-O.1
~
270900-16
AC Inputs during testing are driven at Vee-0.5V for a Logic "1"
and 0.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "1" and VIL max for a Logic "0".
For -timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOl/lOH = ±20 mA (·L, IOl/lOH = ±10 mAl.
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig.!l..until just before AlEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
AlE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 re-
spectively for AO-A14.
DATA LINES: PO.0-PO.7 for DO-D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: AlE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
7-234
intel~
87C58/80C58
Table 2. EPROM Programming Modes
Mode
RST
PSEN
ALE!
PROG
EAt
L
L..r
12.75V
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
L
H
H
H
H
Program Code Data
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
L..r
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
L..r
12.75V
H
H
H
H
H
Bit 2
H
L
L..r
12.75V
H
H
H
L
L
H
L
L..r
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Bit 3
Read Signature Byte
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C58 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
.
4. Raise EAlVpp from Vee to 12.75V ±0.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAM VERIFY·
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C58.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
+5V
vee
8XC58
AO-A?
PI
A8-A13
P2.0 P2.5
PO
EA/Vpp
ALE,tPRoG
A14
PGM DATA
P3.4
t----
}
PROGRAM
SIGNALS
PSEN
P2.?
P2.6
XTAL2'
P3.?
CONTROL SIGNALS'
P3.6
P3.3
XTAL 1
RST
Vss
270900-18
• See Table 2 for proper inpul on these pins
Figure 10. Programming the EPROM
7-235
intel"
87C58/80C58
ADDRESS
X
DATA
X
8 BITS
X
7 BITS
CONTROL
SIGNALS
12.75V
EA/Vpp
X
15 BITS
X
X
J
5V
'--
TGlGH
ALE/PROO
5 Pulses
270900-19
Figure 11. Programming Signal's Waveforms
. Reading the Signature Bytes
The 87C58/80C58 each has 3 signature bytes in locations 30H, 31 Hand 60H. To read these bytes follow the procedure for EPROM verify, but activate
the control lines provided in Table 2 for Read Signature Byte.
Location
30H
31H
60H
Content
87CS8
80CS8
89H
58H
58H
89H
58H
58H/18H
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p,W/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a.1 's state.
Erasure Characteristics (Windowed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
7-236
intel .
87C58/80C58
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA
=
21°C to 27°C; Vee
=
5V ±20%; vss = OV)
Symbol
Vpp
Parameter
Min
Max
Units
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
1/TCLCL
Oscillator Frequency
TAVGL
. Address Setup to PROG Low
TGHAX
75
rnA
6
MHz
4
48TCLCL
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
TGHSL
Vpp Hold after PROG
10
TGLGH
PROG Width
90
10
J.Ls
J.Ls
110
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
J.Ls
48TCLCL
J.Ls
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
VERIfiCATION
PROGRAt.lt.lING
P2.0~P2.5
PLO-Pl.7
P3.4
ADDRESS
------{::!§~C~::r-----;::!!!§~:}---TAVQV
PO.O-PO.7
-----t1:J~:!!~
TDVGL
ALE/PRciG
------_1
DATA OUT
TGHDX
TGHAX
TSHGL
TGLGH
EA/Vpp
vee
_ ___
~Ir-~V~--~
~
EA/HIGH
TEHS:P
._
TELQV
CONTROL
SIGNALS
(ENABLE) - - - - '
'
L
l_--1--T_E_HQ_Z_-270900-20
NOTE:
'5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
7-237
intel~
87C58/80C58
REVISION HISTORY
The following differences exist between this data sheet (270900-003) and the previous version (270900-002):
1. Added 3.3V device to data sheet.
2. Data sheet status changed from "Preliminary" to "Production".
3. The Operating Temperature Range has been changed to:
O'C to
+ 70'C.
The following differences exist between the -002 and -001 versions of this data sheet: .
1. Data sheet status changed from "Advanced" to "Preliminary".
2. QFP package type added.
3. "NC" pin labels changed to "Reserved" in Figure 2.
4. 0ja and 0jc information added to Packages table.
5. Capacitor value for ceramic resonators deleted in Figure 3.
6. Pin numbers deleted from Figure 10.
7. Second paragraph under "Encryption Array" section added.
8. All references to Program Lock Bit and Encryption Array deleted from "Program Verification" section. This
information is available in the hardware description.
7-238
87C58/80C58
EXPRESS
87C58/80C58-3.5 MHz to 12 MHz, Vee = 5V ± 20%
87C58-1/80C58-1.;...3.5 MHz to 16 MHz, Vee = 5V ± 20%
•
Extended Temperature Range
•
Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS@·S1 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn·in and an extended
temperature range with or without burn·in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature rangE:! option, operational characteristics are
guaranteed over the range of - 40·C to + 8S·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 12S·C with Vee = 6.9V ±0.2SV, following
guidelines in MIL·STD·883, Method 101S.
Package types and EXPRESS versions are identified by a one· or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
This data sheet is valid in conjunction with the commercial 87CS8/80CS8 data sheet, 270900-001.
7-239
September 1990
Order Number: 270902-001
87C58/80C58 EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS
TA
=
-40·Cto +8S·C;Vcc
=
SV ±20%;Vss
Umlts
Parameter
Symbol
Min
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
ITL
I
Max
j
-7S0
=
OV
Unit
p.A
Test
Conditions
VIN = 2V
Table 1. Prefix Identification
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
Prefix
0"
Cerdip
Commercial
No
N
PLCC
Commercial
No
TP
Plastic
Extended
No
TO"
Cerdip
Extended
No
TN
PLCC
Extended
No
LP
Plastic
Extended
Yes
LO"
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
NOTE:
• Commercial temperature range is O"C to 70"C. Extended temperature range is -40"C to +8SoC.
• Bum-in is dynamic for a minimum time of 168 hours at 12SoC, Vee = 6.9V ±0.2SV, following guidelines in MIL-STO-883
Method 101S (Test Condition 0).
EXAMPLES:
P80CS8 indicates 80CS8 in a plastic package and specified for commercial temperature range, without burn-in.
LD80CS8 indicates 80CS8 in a cerdip package and specified for extended temperature range with burn-in.
'Available in EPROM version only.
DATA SHEET REVISION SUMMARY
This is the -001 version of the 87CS8/80CS8 Express data sheet.
7-240
87C58-20/-3
80C58-20/-3
COMMERCIAL/EXPRESS 20 MHz MICROCONTROLLER
87C58-20/80C58-2o-3.5 MHz-20 MHz Vee = 5V ± 20%
87C58-3/80C58-3-24 MHz Internal Operation, Vee = 5V ± 20%
CHMOS EPRO
• 24HighMHzPerformance
Internal Operation (-3 only)
• Three 16-Bit
• ProgrammableTimer/Counters
Clock Out
• Up/Down Timer/Counter
• Three Level Program Lock System
• 32K On-Chip EPROM/ROM
• 256 Bytes of On-Chip Data RAM
•
Quick Pulse Programming
• Improved
Algorithm
Processor
• Boolean
• 32 Programmable I/O Lines
Interrupt Sources
• 6Programmable
Channel with:
• - Framing ErrorSerial
Detection
- Automatic Address Recognition
and CMOS Compatible Logic
• TTL
Levels
External Program Memory Space
• 64K
External Data Memory Space
• 64K
MCS®-51 Compatible Instruction Set
•
Saving Idle and Power Down
• Power
Modes
(On-Circuit Emulation) Mode
• ONCE
Four-Level Interrupt Priority
•
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on-chip EPROM. The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 8XC58-20/-3 is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 8XC58-20/-3 uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 8XC58-20/-3 is an enhanced version of the 87C51 /80C51 BH. Its added features make it an
even more powerful microcontroller for applications that require clock output and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-processor communications.
The 87C58-3/80C58-3 has the same 3.5 MHz to 20 MHz frequency range as the 87C58-20/80C58-20 when
operating out of external program/data memory. When running out of internal program/data memory, the
87C58-3/80C58-3 can operate up to 24 MHz.
Throughout this document 8XC58-20 will refer to the 87C58-20, 80C58-20, 87C58-3 and the 80C58-3.
7-241
October 1992
Order Number: 272029-002
infel .
87C58·20/·380C58·20/·3
P2.0-P2.7
r---------- ~~~~~
----------- ..
~~
VSS
~
PSEN
ALuPRoG
EA/VPP
RST
TilliNG
AND
CONTROL
ffi 1I'1-_~~_x.._ _ _ _....L...L__~_
___IL....L._ _ ___l
ti;
~ 1\r---=-------rT----.,..r---""?~--1I
Pl.0-Pl.7
Pl.O - Pl.7
272029-1
Figure 1. 8XC58·20 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
7-242
int:et
87C58-20/-380C58-20/-3
PACKAGES
Part
Prefix
Package Type
°ja
Ole
8XC58-20
87C58-20
8XC58-20
8XC58-20
P
D
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-Pin QFP
45°C/W
45°C/W
46°C/W
90°C/W
16°C/W
15°C/W
16°C/W
22°C/W
N
S
. '"
"'!
INDEX
CORNER
"'-
~
0:
"!
"'-
"'-
~
>VI
o"!
0
>U "'-
N
'"
~ ~ ~
(TZ)
PLO
Vee
(TZEX)
PI.l
PO.O (ADO)
Pl.Z
PO.l (AD1)
Pl.S
PO.4
Pl.3
PO.Z (ADZ)
Pl.6
PO.S
Pl.4
PO.3 (AD3)
Pl.7
PO.6
Pl.S
PO.4 (AD4)
RST
Pl.6
PO.S (ADS)
P3.0
Pl.7
PO.6 (AD6)
RESERVED'
RESET
PO.7 (AD7)
(RXD)
P3.0
EA
(TXD)
P3.1
ALE
(iNTo) P3.Z
PSEN
(i"Nf"f)
P3.3
P2.7
(A1S)
(TO)
P3.4
PZ.6
(A14)
(Tl)
P3.S
PZ.S
(A13)
(i'iR) P3.6
(RD) P3.7
PZ.4
(A1Z)
PZ.3
(A ll)
XTALZ
PZ.2 (A 10)
XTAL 1
PZ.l
(A9)
Vss
P2.0
(AB)
PO.7
EA
RESERVED·
P3.1
ALE
P3.2
PSEN
P3.3
P2.7
P3.4
P2.6
P3.S
P2.S
"
....
.; .;
"'- "'-
N
~
...
~
~"
~w
>
ffi
0
~
~
N
"'- "'- "'-
272029-3
PLCC
272029-2
DIP
INDEX
CORNER \
"'!
~
~
~
0: 0: ;;: ;;: ;;:
in (.)
~
>V'I ~ ~
0
0 0 '"
N
"'-
"'-
"'-
.~~! ~~! !~! ~~! ~~! !~! !=!! !~! !~! !~:!~
P1.S
P1.6
Pl.7
RST
2: !
6••
P3.3
-,
7: !
PO.4
PO.S
Lil PO.6
Lfo PO.7
4...
RESERVED'
P3.Z
!:f2
(!
-,
S: ;
P3.1
·33
L.
(;
P3.0
.
" " "'" ~
8XC58-20
(;
-,
9_ •
Lt9
EA
LZ:S
RESERVED'
LV
Li6
ALE
i))
PZ.7
PSEN
P3.4
(9 !
Lt4 PZ.6
P3.S
1J ~
LZ)
pz.s
.:~~ :~~ ;!~ :~~ ~~ :~~ ;~~ ~~~ ~~~ :~~ :~~.
272029-4
QFP
*Do not connect reserved pins.
Figure 2. Pin Connections
7-243
87C58-20/-380C58-20/-3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pull ups.
PIN DESCRIPTIONS
Vee: Supply voltage.
Vss: Circuit ground.
Port 2 emits the high-order address byte during
from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR).· In this application it
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
fetch~s
VSS1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the Vss pin. Connect
Vss and VSS1 with the lowest impedance path possible:
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TIL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pull ups when emitting1 's, and can source and
sink several LS TIL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. l:he Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal p'ullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally· being pulled low will source
current (Ill. on the data sheet) because of the pullups.
Port' 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TIL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal PUIIUPS, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
In addition, Port 1 serves the functions of the following spec{al features of the 8XC58-20:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capture/
r:leload Trigger and Direction Control)
P1.1
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
TN'ff (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven.to their reset condition when a voltage above VI HI voltage'is applied
whether the oscillator is running or not. An internal
pulldown resistor permits a power-on reset with only
a capacitor connected to Vee.
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
ALE: Address Latch Enable output pulse for latching
the low byte of the address dUring~Gesses to external memory. This pin (ALE/PR
) is also the
program pulse input during EPROM programming for
the 87C58-20.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TIL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state. can be used as inputs. As inputs, Port 2
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
7-244
int:et
87C58-20/-380C58-20/-3
If desired, ALE operation can be disabled by setting
bit 0 of SFR location BEH. With the bit set, ALE is
active only during a MOVX instruction. Otherwise,
the pin is weakly pulled high.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the BXC5B-20 is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
Memory.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but the minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
EA should be strapped to Vee for internal program
executions.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
C2
Nlc
XTAL 2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
272029-6
Figure 4. External Clock Drive Configuration
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on~chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
I-~P---f XTAL 2
o
1----4~-_I
XTAL 1
.....-------1 Vss
272029-5
Cl, C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer.
Figure 3. Oscillator Connections
On the BXC5B-20 either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-Chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values .
To properly terminate Power down the reset or ex. ternal interrupt should not be executed before Vee is
restored to its normal operating level. The external
interrupt or reset signal must be held active long
enough for the oscillator to restart and stabilize (normally less than 10 ms).
7-245
infel~
87C58-20/-380C58-20/-3
With an external interrupt, INTO and INT1 must be
enabled and Configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
DESIGN CONSIDERATION
• When running out of internal program/data memory, the 87C58-3/80C58-3 can be operated using
a 24 MHz clock. If the 87C58-3/80C58-3 is running out of external program/data memory, the
operating frequency must be between 3.5 MHz to
20 MHz. The 87C58-3/80C58-3 will not function
properly at 24 MHz when running out of external
program/data memory.
• The window on the 87C58-20 must be covered
by an opaque label. Otherwise, the DC and AC
characteristics may not be met, and the device
may functionally be impaired.
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
.
TIMER 2 PROGRAMMABLE
CLOCK OUT
The 8XC58-20 has a new Timer 2 feature. A 50%
duty cycle clock can be programmed to come out on
P1.0. The output frequency ranges from 61 Hz to
4 MHz depending on the oscillator frequency and
the reload value of the Timer 2 capture registers
(RCAP2H, RCAP2L) as shown in the equation below:
'CI
k 0 F'
Oscillator Frequency
oc • ut requency ~ 4 X (65536 - RCAP2H, RCAP2L)
To configure the TilT)er/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared, and bit
T20E in T2MOD must be set. Bit TR2 (T2CON.2)
starts and stops the timer.
For a complete description of all Timer 2 functions,
please reference the 8XC52/54/58 Hardware Description of the 8-Bit Embedded Controllers Handbook.
"NOTE:
Even though the equation permits a maximum
clock-out frequency of 5 MHz using a 20 MHz oscillator, the maximum device output frequency is
4 MHz. When using a 20 MHz oscillator, RCAP2L
must be limited to a maximum value of FEH.
ONCE MODE
/
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC54-20 without the 8XC58-20 having to be removed from the circuit. The ONCE Mode is invoked
by:
'
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC58-20 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Table 1. Status of the External Pins During Idle and Power Down
Program
Memory
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Mode
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the 80C51BH."
7-246
87C58-20/-380C58-20/-3
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias. -40°C to + 85°C
Storage Temperature .......... -65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V
IOL Per 1/0 Pin ........................... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
-40
+70
+85
°C
°C '
Vee
Supply Voltage
4.0
6.0
V
fose
Oscillator Frequency
3.5
20
MHz
TA
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
Min
Typ(4)
Max
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0. 2Vee- 0.1
V
VIL1
Input Low Voltage EA
0
0. 2Vee- 0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2Vee+ 0.9
Vee + 0.5
V
0.7 Vee
Vee+ 0.5
V
0.3
V
IOL
100 /-LA(1)
0.45
V
IOL
1.6 mA(1)
VIH1
Input High Voltage (XTAL 1, RST)
VOL
Output Low Voltage(5)
(Ports 1, 2, and 3)
VOL1
VOH
IlL
III
V
V
0.45
V
1.0
V
Vee- 0.3
V
IOH
Vee- 0.7
V
IOH
Vee- 1.5
V
IOH
Vee- 0.3
V
IOH
Vee- 0.7
V
IOH
Vee-1.5
V
IOH
/-LA
VIN
/-LA
0.45
Output Low Voltage(5)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2, and 3, ALE, PSEN)
\
VOH1
1.0
0.3
=
=
IOL =
IOL =
IOL =
IOL =
Output High Voltage
(Port 0 in External Bus Mode)
Logical 0 Input Current
(Ports 1, 2, and 3)
-50
Input leakage Current (Port 0)
±10
=
=
=
=
=
=
=
3.5 mA(1)
200/-LA(1)
3.2 mA(1)
7.0 mA(1)
-10/-LA
-30/-LA
-60/-LA
-200/-LA
-3.2 mA
-7.0 mA
0.45V
,
7-247
< VIN < Vee
intel .
87C58-20/-380C58-20/-3
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameters values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
ITl
Parameter
Min
Logical 1 to 0 Transition Current
(Ports 1, 2, and 3)
Commercial
Express
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
Icc
Typ(4)
Max
Unit
-650
-750
!LA
225
K!l
40
10
/LA
pF
Test Conditions
VIN
=
2V
@1 MHz, 25°C
(Note 3)
Power Supply Current:
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
20
5
15
40
10
100
mA
mA
/LA
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test.conditions. Minimum Vee for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited a!) follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per B-bit portPort 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
70mA
./
60mA
SOmA
40mA
A~
/'"
30mA
V
20mA
10mA
/
/A/
,---- V--
~
IDLE t.lAX.
/.........:::: ......
OmA
OIotHz
V
IDLE
~
-
TYPICAL
4t.lHz
SIotHz
1210tHz
Icc Max at oiher frequencies is given by:
Active Mode
Icc Max = (Osc Freq X 3) + 4
Idle Mode
Icc Max = (Ose Freq X 0.5) + 4
Where Osc Freq is in MHz, ICC is in rnA.
Figure 5.
Icc vs Frequency
7-248
16 MHz
20 IotHz
272029-7
inteL
87C58-20/-380C58-20/-3
Vee
Vee
PO .,, _ __
PO
EAi----,
RST
8XC58-20
8XC58-20
XTAL2
XTAL1
CLOCK
SIGNAL
XTAL2
XTAL 1
CLOCK
SIGNAL
Vss
VSS
272029-9
272029-8
All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 6. Icc Test Condition, Active Mode
Figure 7. Icc Test Condition Idle Mode
Vee
PO . , _ - - - '
EA t----.
RST
8XC58-20
XTAL2
XTAL 1
Vss
272029-10
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 6.0V
VCC -0.5 -------".r~:-----,
0.7 Vcc
0.45V ---'C0.2 Vce-D.1
lCHCL
272029-11
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes
TCLCH = TCHCL = 5 ns
P:PSEN
EXPLANATION OF THE AC SYMBOLS
Q: Output Data
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The foilowing is a list of ail the characters and
what they stand for.
A: Address
C: Clock
0: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
R: RD signal
T:Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
7-249
87C58·20/·380C58·20/·3
AC CHARACTERISTICS
(Over Operating Conditions.) Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Variable Oscillator
Min
Min
Max
3.5
20
Max
1/TCLCL Oscillator Frequency
Units
MHz
60
2TCLCL~40
ns
Address Valid to ALE Low
10
TCLCL-40
ns
Address Hold After ALE Low
20
TCLCL-30
ns
TLHLL
ALE Pulse Width
TAVLL
TLLAX
4TCLCL-75
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
20
125
TPLPH
PSEN Pulse Width
105
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
30
TCLCL-20
ns
TAVIV
Address to Valid Instruction In
145
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
TCLCL-30
RD Pulse Width
200
6TCLCL-100
WR Pulse Width
200
6TCLCL-100
RD Low to Valid Data In
Data Hold After RD
TRHDZ
Data Float After RD
ns
ns
5TCLCL-95
155
ns
ns
0
0
ns
ns
0
0
TWLWH
TRHDX
ns
3TCLCL-90
TRLRH
TRLDV
ns
3TCLCL-45
60
ns
40
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
310
8TCLCL-90
ns
TAVDV
Address to Valid Data In
360
9TCLCL-90
ns
3TCLCL+50
ns
200
3TCLCL-50
TLLWL
ALE Low to RD or WR Low
100
TAVWL
Address Valid to WR Low
110
4TCLCL-90
ns
TOVWX
Data Valid before WR
15
TCLCL-35
ns
TWHOX
Data Hold after WR
10
TCLCL-40
ns
TOVWH
Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
7TCLCL-70
280
0
10
. 7-250
90
TCLCL-40
ns
0
ns
TCLCL+40
ns
infel"
87C58·20/·380C58·20/·3
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _.I
PSEN _ _. I
PORT 0
PORT 2
--..I
A8-A15
---'~----------"'~------272029-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
"I
i+-----TLLDV
---1---
TRLRH
INSTR. IN
PORTO
PORT 2
P2.0-P2.7 OR A8-A 15 FROM DPH
--"~---------------
A8-A15 FROM PCH
272029-13
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
r
-1-TLHLL~
~TWHLH
\.
J
\.
ro--TLLWL
...
TAVLL
I!-TLLAX ....
,
PORT 2
:::r
-
~
DATA OUT
FROt/Rro"{ DPL
..
J
~
TQVWH
PORTO
J
TWLWH
I-TWHQX
K XAO-A7 FROM PCL
INSTR. IN
TAVWL
P2.0-P2.7 OR A8-A 15 FROM DPH
X
A8-A 15 FROM PCH
272029-14
7-251
87C58-20/-380C58-20/-3
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions
Symbol
TA
==
O·C to
+ 70·C; Vee =
5V ± 20%; Vss
20 MHz Oscillator
Parameter
MIn
=
OV; Load Capacitance
=
80 pF
Variable Oscillator
Min
Max
Units
Max
TXLXL
Serial Port Clock Cycle Time
600
12TCLCL
ns
TQVXH
Output Data Setup to Clock
Rising Edge
367
1OTCLCL -133
ns
TXHQX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-50
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
10TCLCL-133
367
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
20
MHz
1/TCLCL
Oscillator Frequency
3.5
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272029-16
7-252
ns
int:eL
87C58-20F-380C58-20/-3
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
)xC
VCC-0.5~ 0.2 VCC+0.9
0.45 V ---.!\_0_.2_VC.;..C,--_0_.1_ _ _
TIMING REFERENCE
~.
POINTS
272029-17
AC Inputs during testing are driven at Vcc-0.5V for a Logic "1"
and 0.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "1" and VIL max for a Logic "0".
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOL/loH :e ± 20 mA.
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig!!.....until just before ALE I
PROG is to be pulsed. The EAlVpp is raised to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 re-
spectively for AO-A14.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
Table 2. EPROM Programming Modes
RST
PSEN
ALE!
PROG
EAt
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
H
L
L...J
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
L...J
12.75V
L
H
H
L
H
Program Lock
Bits
H
L
L...J
12.75V
H
H
H
H
H
Mode
Program Code Data
Bit 1
Bit 2
H
L
L...J
12.75V
H
H
H
L
L
Bit 3
H
L
L...J
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Read Signature Byte
7-253
int:eL
87C58-20/-380C58-20/-3
+SV
Vee
40
B7CS8 - 20
32-39
PO
EA/Vpp
ALE/PROG
u
A14
-PSEN
P3.4
P2.7
P2.6
XTAL2
P3.7
P3.6
P3.3
XTAL 1
PGM DATA
31
PROGRAM
30
1 - _ _ } SIGNALS
29
2B
27
17
CONTROL SIGNALS·
16
13
RST
VSS
272029-19
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C58-20 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM' array, and 25 times for the encryption table and
the lock bits.
ADDRESS
PROGRAM VERIFY
Program verify may be done after each byte or block
of bytes that is programmed. A complete verify of
the array will ensure. reliable programming of the
87C58-20.
The lock bits cannot be directly verified. They are
verified by observing that their features are enabled.
Refer to the EPROM Program Lock section in this
data sheet.
x
-.-________X
X
IS BITS
X
X__________X
DATA
B BITS
CONTROL
SIGNALS
7 BITS
12.7SV
EA/Vpp
Repeat 1 thOrough 5 changing the address and data
for the entire array or until the end of the object file is
reached.
SV
J
'--
TGLGH
ALE/PROG
272029-20
5 Pulses
Figure 11. Programming Signal's Waveforms
7-254
int'et
87C58-20/-380C58-20/-3
ROM and EPROM Lock System
Program Lock Bits
The 87C58-20 and the 80C58-20 program lock systems, when programmed, protect the onboard'program against software piracy.
The 87C58-20 has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data.
The 80C58-20 has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
3. If program protection is desired, the user submits
the encryption table with their code, and both the
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the
user must submit an encryption table.
The 87C58-20 has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, all locations are user programmable. See Table 3.
Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 8XC58-20 has 3 signature bytes in locations
30H, 31 H, and 60H. To read these bytes follow the
procedure for EPROM verify, but activate the control
lines provided in Table 2 for Read Signature Byte.
Content
Location
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in it's
original, unmodified form. For programming the Encryption Array, refer to Table 2 (Programming the
EPROM).
When using the encryption array, one important factor needs to be considered. If a code byte has the
value of OFFH, verifying the byte will produce the
encryption byte value. If a large block (> 64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be programmed with some value other than OFFH, and not
all of them the same value. This will ensure maximum program protection.
30H
31H
60H
87C58-20
80C58-20
89H
58H
58H
89H
58H
58H/18H
Erasure Characteristics
(Windowed Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
7-255
intet
87C58-20/-380C58-20/-3
Table 3. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
Any other combination of the lock bits is not defined.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21QC to 27QC; Vee = 5V ±20%; vss = OV)
Symbol
Parameter
Min
Max
Units
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
1/TCLCL
Programming Supply Current
Oscillator Frequency
4
75
mA
6
MHz
TAVGL
Address Setup to PROG Low
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
p.s
TGHSL
Vpp Hold after PROG
10
p.s
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
48TCLCL
110
p.s
48TCLCL
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
48TCLCL
7·256
,
48TCLCL
p.s
int:eL
87C58·20/·380C58·20/·3
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMWING
AO-AI.4
VERIFICATION
----1::::::!AD§DR~ES~S~~=::(----{=JA:§DD~RE:§SS=::>---TAVQV
00-07 - -_ _
-1{::J~~':::}t__----~~D~AT!:AO~U!:T~~---
lOVGl
TGHDX
ALEIi'RoG ----~
£A/HIGH
L
)
__
TE_HQ_Z_ _
272029-21
DATA SHEET REVISION SUMMARY
The following differences exist between this data sheet (272029-002) and the previous version (272029-001):
1. Added 87C58-3/80C58-3 to 20 MHz data sheet.
2. Added EXPRESS version of 8XC58-20/-3 to 20 MHz data sheet.
3. 8ja and 8jc information added to Packages table.
4. References to second functions of Port 1.2 thru Port 1.7 pins have been removed.
5. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
From
To
120
125
TLLlV
4TCLCL - 80
4TCLCL - 75
3TCLCL - 95
3TCLCL - 90
TPLIV
TWHQX
o
10
TCLCL - 50
TCLCL - 40
TQVWH
200
280
7TCLCL - 150
7TCLCL - 70
The following differences exist between version -001 of the 87C58-20/80C58-20 data sheet and the 87C58/
80C58 (270900-001) data sheet:
1. QFP package added.
2. Timer 2 Programmable Clock Out paragraph added.
3. 20 MHz extension added to Figure 5.
4. 12 MHz Oscillator timings changed to 20 MHz Oscillator timings in External Program Memory Characteristics and Serial Port Timing tables.
5. Variable Oscillator equations in External Program Memory Characteristics Table changed as follows:
From
To
4TCLCL - 100
4TCLCL - 80
TLLlV
3TCLCL - 105
3TCLCL - 95
TPLIV
TCLCL - 25
TCLCL - 20
TPXIZ
5TCLCL - 165
5TCLCL - 95
TRLDV
8TCLCL - 150
8TCLCL - 90
TLLDV
9TCLCL - 165
9TCLCL - 90
TAVDV
4TCLCL - 130
4TCLCL - 90
TAVWL
TCLCL - 50
TCLCL - 35
TQVWX
6. TXHQX in the Serial Port Timing Table changed from (2TCLCL - 117) to (2TCLCL - 50).
7. RRST Specification in DC Characteristics table changed from 40 K!l min, 225 K!l max to 50 K!l min,
300 K!l max.
7-257
8XC51FX Hardware
Description and Data Sheets
8
intel·
September 1991
8XC51FX
Hardware, Description
Order Number: 270653-004
8-1
HARDWARE DESCRIPTION OF THE 8XC51FX
CONTENTS
CONTENTS
PAGE
PAGE
7.4 Baud Rates ....................... 8-30
1.0 INTRODUCTION ..................... 8-3
7.5 Using Timer 1 to Generate Baud
Rates .............................. 8-30
2.0 MEMORY ............................ 8-3
7.6 Using Timer 2 to Generate Baud
Rates .............................. 8-30
2.1 Program Memory .................. 8-3
2.2 Data Memory ...................... 8-3
8.0 INTERRUPTS ....................... 8-32
3.0 SPECIAL FUNCTION
REGISTERS ........................... 8-4
8.1 External Interrupts ................ 8-33
4.0 PORT STRUCTURES AND
OPERATION . .......................... 8-7
8.2 Timer Interrupts .................. 8-33
8.3 PCA Interrupt ................. : ... 8-33
4.1 I/O Configurations ................. 8-7
8.4 Serial Port Interrupt ............... 8-33
4.2 Writing to a Port ................... 8-8
8.5 Interrupt Enable .................. 8-33
4.3 Port Loading and Interfacing ...... 8-10
8.6 Priority Level Structure ............ 8-33
4.4 Read-Modity-Write Feature ....... 8-10
4.5 Accessing External Memory ...... 8-10
8.7 Response Time ................... 8-37
9.0 RESET .............................. 8-37
9.1 Power-On Reset .................. 8-38
5.0 TIMERS/COUNTERS ............... 8-12
5.1 TIMER 0 AND TIMER 1 ........... 8-12
10.0 POWER-SAVING MODES OF
OPERATION ......................... 8-38
10.1 Idle Mode ....................... 8-38
5.2 TIMER 2 .......................... 8-15
6.0 PROGRAMMABLE COUNTER
ARRAY ............................... 8-18
10.2 Power Down Mode .............. 8-40
6.1 PCA 16-Bit Timer/Counter ........ 8-20
10.3 Power Off Flag .................. 8-40
6.2 Capture/Compare Modules .,' ..... 8-22
11.0 EPROM VERSIONS .. .............. 8-40
6.3 16-Bit Capture Mode .............. 8-24
6.4 16-Bit Software Timer Mode ...... 8-24
12.0 PROGRAM MEMORY LOCK ....... 8-40
6.5 High Speed Output Mode ......... 8-25
13.0 ONCE MODE ...................... 8-41
6.6 Watchdog Timer Mode ............ 8-25
14.0 ON-CHIP ,OSCILLATOR ........... 8-42
6.7 Pulse Width Modulator Mode ...... 8-26
15.0 CPU TIMING . .......... , ........... 8-43
7.0 SERIAL INTERFACE ............... 8-27
7.1 Framing Error Detection .......... 8-28
7.2 Multiprocessor Communications .. 8-28
7.3 Automatic Address Recognition ... 8-28
8-2
int'eL
8XC51FX HARDWARE DESCRIPTION
Table 1. C51FX Family of Mlcrocontrollers
1.0 INTRODUCTION
The 8XC51FX is a highly integrated 8-bit microcontroller based on the MCS-51 architecture. As a member
of the MCS-51 family, the 8XC51FX is optimized for
control applications. Its key feature is the programmable counter array (PCA) which is capable of measuring
and generating pulse information on five I/O pins. Also
included are an enhanced serial port for mUlti-processor communications, an up/down timer/counter, and a
program lock scheme for the on-chip program memory.
Since the 8XC51FX products are CHMOS, they have
two software selectable reduced power modes: Idle
Mode and Power Down Mode.
ROM
Device
EPROM
Version
ROMI
RAM
ROMless
EPROM
Bytes
Version
Bytes
8K
256
83C51FB 87C51FB 80C51FA
16K
256
83C51FC 87C51FC 80C51FA
32K
256
83C51FA 87C51FA 80C51FA
2.0 MEMORY ORGANIZATION
All MCS-51 devices have a separate address space for
Program and Data Memory. Up to 64 Kbytes each of
external Program and Data Memory can be addressed.
The 8XC51FX uses the standard 8051 instruction set
and is pin-for-pin compatible with the existing MCS-51
family of products.
2.1 Program Memory
This document presents a comprehensive description of
the on-chip hardware features of the 8XC51FX. It begins with a discussion of the on-chip memory and then
discusses each of the peripherals listed below.
If the EA pin is connected to Vss, all program fetches
are directed to external memory. On the 83C51FA (or
87C51FA), if the EA pin is connected to Vee, then
program fetches to addresses OOOOH through IFFFH
are directed to internal ROM and fetches to addresses
2000H through FFFFH are to external memory.
Please note that 8XC51FX does not include the
80C51FA and 83C51FA. Therefore, these devices do
not have some of the features found on the 8XC5IFX.
These features are: programmable clock out, four level
interrupt priority structure, enhanced program lock
scheme and asynchronous port reset.
• Four 8-Bit Bidirectional Parallel Ports
• Three 16-Bit Timer/Counters with
- One Up/Down Timer/Counter
- Clock Out
• Programmable Counter Array with
- Compare/Capture
- Software Timer
- High Speed Output
- Pulse Width Modulator
- Watchdog Timer
• Full-Duplex Programmable Serial Port with
- Framing Error Detection
- Automatic Address Recognition
• Interrupt Structure with
- Seven Interrupt Sources
- Four Priority Levels
On the 83C51FB (or 87C51FB) if EA is connected to
VCC, program fetches to addresses OOOOH through
3FFFH are directed to internal ROM, and fetches to
addresses 4000H through FFFFH are to external memory.
On the 83C51FC (or 87C51FC) ifEA is connected to
Vee, program fetches to addresses OOOOH through
7FFFH are directed to internal ROM or EPROM and
fetches to addresses 8000H through FFFFH are to external memory.
2.2 Data Memory
The C51FX implements 256 bytes of on-chip data
RAM. The'upper 128 bytes occupy a parallel address
space to the Special Function Registers. That means
they have the same addresses, but are physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of data RAM or to SFR space by
the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For
example:
• Power-Saving Modes
- Idle Mode
- Power Down Mode
MOV OAOH, # data
Table I summarizes the product names and memory
differences of the various 8XC51FX products currently
available. Throughout this document, the products will
generally be referred to as the C5IFX.
8-3
intel~
8XC51FX HARDWARE DESCRIPTION
PO .O-PO.7
v~~---------- ~~~~~
Vss
E
!'SEN
TIMING
~~===:;======:;::=~~=:::;:~==:;~~=~
CO~~~OL
~"
ox
AL[/~
£l/vpp
RST
I
Pt.O-Pt.7
P3.0- P3.7
270653-1
Figure 1. 8XC51FX Functional Block Diagram
accesses the SFR at locationOAOH (which is P2). Instructions that use indirect addressing access the upper
128 bytes of data RAM. For example:
3.0 SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the SFR
(Special Function Register) space is shown in Table 2.
MOV @RO,#data
Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.
where RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH).
Note that stack operations are examples of indirect ad·
dressing, so the upper 128 bytes of data RAM are available as stack space.
8-4
intel·
8XC51FX HARDWARE DESCRIPTION
The functions of the SFRs are outlined below. More
information on the use of specific SFRs for each peripheral is included in the description of that peripheral.
User software should not write Is to these unimplemented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be 1.
Accumulator: ACC is the Accumulator register. The
mnemonics for Accumulator-Specific instructions,
however, refer to the Accumulator simply as A.
Table 2. SFR Mapping and Reset Values
FF
CCAP2H
CCAP3H
CCAP4H
CH
CCAPOH CCAP1H
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
F8
FO "B
00000000
F7
CL
CCAPOL
CCAP1L
00000000 XXXXXXXX XXXXXXXX
E8
EO "ACC
00000000
08 CCON
CMOO
CCAPMO CCAPM1
OOXOOOOO OOXXXOOO XOOOOOOO XOOOOOOO
DO "PSW
00000000
,
T2MOO
RCAP2L
RCAP2H
C8 T2CON
00000000 XXXXXXOO 00000000 00000000
CO
B8
CCAP2L
XXXXXX~X
CCAP3L
CCAP4L
XXXXXXXX XXXXXXXX
E7
CCAPM2
XOOOOOOO
OF
CCAPM3 CCAPM4
XOOOOOOO XOOOOOOO
07
TL2
00000000
CF
TH2
00000000
C7
BF
"IP
SAOEN
XOOOOOOO 00000000
IPH
XOOOOOOO
BO " P3
11111111
A8 "IE
SAOOR
00000000 00000000
AO • P2
11111111
"SBUF
98 "SCON
00000000 XXXXXXXX
B7
AF
A7
9F
97
90 • P1
11111111
'THO
88 " TCON
"TMOO
" TH1
" TLO
• TL1
00000000 00000000 00000000 00000000 00000000 00000000
80 " PO
" OPH
" SP
• OPL
11111111 00000111 00000000 00000000
• =
•• =
X=
EF
. .
Found In the 8051 core (See 8051 Hardware Description for explanations of these SFRs) .
See description of PCON SFR. Bit PCON.4 is not affected by reset.
Undefined.
8-5
8F
'PCON ,. 87
OOXXOOOO
intel .
8XC51FX HARDWARE DESCRIPTION
Table 3. PSW: Program Status Word Register
PSW
Address = ODOH
Reset Value = 0000 OOOOB
Bit Addressable
CY
AC
FO
RS1
RSO
OV
P
7
6
5
4
3
2
o
Bit
Symbol
Function
CY
AC
FO
RS1
RSO
Carry flag.
Auxiliary Carry flag. (For BCD Operations)
Flag O. (Available to the user for general purposes).
Register bank select bit 1.
Register bank select bit o.
RS1
RSO
Working Register Bank and Address
0
Bank 0
(00H-07H)
0,
1
Bank 1
(08H-OFH)
1
0
Bank 2
(10H-17H)
1
1
Bank 3
(18H-1 FH)
Overflow flag.
User definable flag.
Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the Accumulator, i.e., even parity.
'
o
OV
P
8 Register: The B register is used during multiply and
divide operations. For other instructions it can be treated as another scratch pad register.
RCAP2L) are the capture/reload registers for Timer 2
in 16-bit capture mode or 16-bit auto-reload mode.
Programmable Counter Array (PCA) Registers: The
Hi:bit PCA timer/counter consists of registers CH and
CL. Registers CCON and CMOD contain the control
and status bits for the PCA. The CCAPMn (n = 0, I,
2, 3, or 4) registers control the mode for each ofthe five
PCA modules. The register pairs (CCAPnH, CCAPnL)
are the 16-bit compare/capture registers for each PCA
module.
Stack Pointer: The Stack Pointer Register is 8 bits
wide. 'It is incremented before data is stored during
PUSH and CALL executions. The stack may reside
anywhere in on-chip RAM. On reset, the Stack Pointer
is initialized to 07H causing the stack to begin at location 08H.
Data Pointer: The Data Pointer (DPTR) consists of a
high byte (DPH) and a low byte (DPL). Its intended
function is to hold a 16-bit address, but it may be ma~
nipulated as a 16-bit register or as two independent
8-bit registers.
Serial Port Registers: The Serial Data Buffer, SBUP,
is actually two separate registers: a transmit buffer and
a receive buffer register. When data is moved to SBUF,'
it goes to the transmit buffer where it is held for serial
transmission. (Moving a byte to SBUF initiates the
transmission). When data is moved from SBUF, it
comes from the receive buffer. Register SCON contains
the control and status bits for the Serial Port. Registers
SADDR and SADEN are used to define the Given and
the Broadcast addresses for the Automatic Address
Recognition feature.
Program Status Word: The PSW register contains program status information as detailed in Table 3.
Ports 0 to 3 Registers: PO, PI, P2, and P3 are the SFR
latches o(Port 0, Port I, Port 2, and Port 3 respectively.
Interrupt Registers: The individual interrupt enable
bits are in the IE register. Two priorities can be set for
each of the 7 interrupts in the IP register.
Timer Registers: Register pairs (THO, TLO), (THI,
TLI), and (TH2, TL2) are the 16-bit count registers for
Timer/Counters 0, I, and 2 respectively. Control and
status bits are contained in registers TCON and TMOD
for Timers 0 and 1 and in registers T2CON and
T2MOD for Timer 2. The register pair (R.CAP2H,
Power Control Register: PCON controls the Power
Reduction Modes. Idle and Power Down Modes.
8-6
intet
8XC51FX HARDWARE DESCRIPTION
Table 4. Alternate Port Functions
4.0 PORT STRUCTURES AND
OPERATION
The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin is stuck at O.
Port Pin
Alternate Function
PO.O/ADO- Multiplexed Byte of Address/Data for
PO.7/AD7 External Memory
P1.0/T2
Timer 2 External Clock Input/ClockOut
Pl.l1T2EX Timer 2 Reload/Capture/Direction
Control
P1.2/ECI PCA External Clock Input
P1.3/CEXO PCA Module 0 Capture Input,
Compare/PWM Output
P1.4/CEXI PCA Module 1 Capture Input,
Compare/PWM Output
P1.5/CEX2 PCA Module 2 Capture Input,
Compare/PWM Output
P1.6/CEX3 PCA Module 3 Capture Input,
Compare/PWM Output
P1.7/CEX4 PCA Module 4 Capture Input,
Compare/PWM Output
4.1 1/0 Configurations
P2.0/ASP2.7/AI5
High Byte of Address for External
Memory
Figure 2 shows a functional diagram of a typical bit
latch and I/O buffer in each of the four ports. The bit
latch (one bit in the port's SFR) is represented as a
Type D flip-flop, which clocks in a value from the internal bus in response to a "write to latch" signal from
the CPU. The Q output of the flip-flop is placed on the
internal bus in response to a "read latch" signal from
the CPU. The level of the port pin itself is placed on the
internal bus in response to a "read pin" signal from the
CPU. Some instructions that read a port activate the
"read latch" signal, and others activate the "read pin"
signal. See the Read-Modify-Write Feature section.
P3.0/RXD
P3.1ITXD
P3.2/INTO
P3.3/INT
P3.4/TO
P3.5ITI
P3.6/WR
P3.7/RD
Serial Port Input
Serial Port Output
External Interrupt 0
External Interrupt 1
Timer 0 External Clock Input
Timer 1 External Clock Input
Write Strobe for External Memory
Read Strobe for External Memory
All four ports in the C5lFX are bidirectional. Each
consists of a latch (Special Function Registers PO
through P3), an output driver, and an input buffer.
The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory.
In this application, Port 0 outputs the low byte of the
external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is
16 bits wide. Otherwise the Port 2 pins continue to emit
the P2 SFR content.
All the Port 1 and Port 3 pins are multifunctional.
They are not only port pins, but also serve the functions
of various special features as listed in Table 4.
As shown in Figure 2, the output drivers of Ports 0 and
2 are switchable to an internal ADDRESS and ADDRESS/DATA bus by an internal CONTROL signal
for use in external memory accesses. During external
memory accesses, the P2 SFR remains unchanged, but
the PO SFR gets Is written to it.
8-7
int'el..
8XC51FX HARDWARE DESCRIPTION
A. Port 0 Bit
B. Port 1 or Port 3 Bit
ADDR/DATA
ALTERNATE
OUTPUT
FUNCTION
VCC
WRITE
TO
LATCH
WRITE
TO
LATCH
270653-2
ALTERNATE
INPUT
FUNCTION
270653-4
C. Port 2 Bit
ADDR
CONTROL
REAO
LATCH
VCC
INT. BUS
WRITE
TO
LATCH
270653-3
·See Figure 4 for details of the internal pullup
Figure 2. C51FX Port Bit Latches and 1/0 Buffers
Also shown in Figure 2 is that if a PI or P3 latch
contains ai, then the output level is controlled by the
signal labeled "alternate output function." The actual
pin level is always available to the pin's alternate input
function, if any.
When configured as inputs they pull high and will
source current (IlL in the data sheets) when externally
pulled low. Port 0, on the other hand, is considered
"true" bidirectional, because it floats when configured
as an input.
Ports 1,2, and 3 have internal pullups. Port 0 has open
drain outputs. Each I/O line can be independently used
as an input or an output (Ports 0 and 2 may not be used
as general purpose I/O when being used as the ADDRESSIDATA BUS). To be used as an input, the port
bit latch must contain a 1, which turns off the output
driver FET. On Ports 1,2, and 3, the pin is pulled high
by the internal l'ullup, but can be pulled low by an
external source.
All the port latches have 1s written to them by the reset
function. If a 0 is subsequently written to a port latch, it
can be reconfigured as an input by writing a 1 to it.
4.2. Writing to a Port
In the execution of an instruction that changes the
value in a port latch, the new value arrives at the latch
during State 6 Phase 2 of the final cycle of the instruction. However, port latches are in fact sampled by their
output buffers only during Phase 1 of any clock period.
(During Phase 2 the output buffer holds the value it
saw during the previous Phase 1). Consequently, the
new value in the port latch won't actually appear at the
output pin until the next Phase 1, which will be at SIPl
of the next machine cycle. Refer to Figure 3. For more
information on internal timings refer to the CPU Timing section.
Port 0 differs from the other ports in not having internal pullups. The pullup FET in the PO output driver
(see Figure 2) is used only when the Port is emitting Is
during external memory accesses. Otherwise the pullup
FET is off. Consequently PO lines that are being used as
output port lines are open drain. Writing a 1 to the bit
latch leaves both output FETs off, which floats the pin
and allows it to be used as a high-impedance input.
Because Ports 1 through 3 have fixed internal pull ups
they are sometimes call "quasi-bidirectional" ports.
8-8
intel~
8XC51FX HARDWARE DESCRIPTION
I~I~41 ~I~51 ~I~61 ~I~ I~I~21 ~I~31 ~I~41 ~I~51
STATE
STATE
STATE
STATE 1 STATE
STATE
STATE
STATE
XTAL1:
-y=c
PO'Pl'P2,P3~
'Pl'P2'P3
INPUTS SAMPLED:
RST
MOV PORT, SRC:
SERIAL PORT
SHIFT CLOCK
(MODE 0)
RST=:r-l.-
NEW DATA
OLD DATA
--+I
j.- RXD PIN SAMPLED
RXD SAMPLED
--l
f-270653-33
Figure 3. Port Operation
pFET 1 in is the transistor that is turned on for 2 oscillator periods after a O-to-l transition in the port latch.
A 1 at the port pin turns on pFET3 (a weak pull-up),
through the invertor. This invertor and pFET form a
latch which hold the 1.
If the change requires a O-to-l transition in Ports 1, 2,
and 3, an additional pullup is turned on during SIPl
and SlP2 of the cycle in which the transition occurs.
This is done to increase the transition speed. The extra
pullup can source about 100 times the current that the
normal pullup can. The internal pullups are field-effect
transistors, not linear resistors. The pull-up arrangements are shown in Figure 4.
If the pin is emitting a 1, a negative glitch on the pin
from some external source can tum off pFET3, causing
the pin to go into a float state. pFET2 is a very weak
pullup which is on whenever the nFET is off, in traditional CMOS style. It's only about '1'0 the strength of
pFET3. Its function is to restore a·l to the pin in the
event the pin had a 1 and lost it to a glitch.
The pullup consists of three pFETs. Note that an
n-channel FET (nFET) is turned on when a logical 1 is
applied to its gate, and is turned off when a logical 0 is
applied to its gate. A p-channe1 FET (PFET) is the
opposite: it is on when its gate sees a 0, and off when its
gate sees a 1.
VCC
VCC
VCC
Q
FROM PORT
LATCH
INPUT
DATA
CJ-----'''<.
READ
PORT PIN
270653-5
CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q makes a O-to-1 transition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is also on. Port 2 is similar except
that it holds the strong pullup on while emitting 1s that are address bits. (See text, "Accessing External Memory".)
Figure 4. Ports 1 and 3 Internal Pullup Configurations
8-9
8XC51FX HARDWARE DESCRIPTION
(decrement and jump if not zero, e.g.,
DJNZ P3, LABEL)
MOV, PX.Y, C (move carry bit to bit Y of Port X)
(clear bit Y of Port X)
CLRPX.Y
(set
bit Y of Port X)
SETBPX.Y
DJNZ
4.3 Port Loading and Interfacing
The output buffers of Ports 1, 2, and 3 can each sink
1.6 rnA at 0.45 V. These port pins can be driven by
open-collector and open-drain outputs although O-to-l
transitions will not be fast since there is little current
pulling the pin up. An input 0 turns off pullup pFET3,
leaving only the very weak pullup pFET2 to drive the
transition.
It is not obvious that the last three instructions in this
list are read-modify-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.
In external bus mode, Port 0 output buffers can each
sink 3.2 rnA at 0.45V. However, as port pins they
require external pullups to be able to drive any inputs.
The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the
pin. For example, a port bit might be used to drive the
base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
correct value of 1.
See the latest revision of the data sheet for design-in
information.
'
4.4 Read-Modify-Write Feature
Some instructions that read a port read the latch and
others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modify-write" instructions. Listed below are the read-modify~write instructions. When the destination operand is a port, or a
port bit, these instructions read the latch rather than
the pin:
ANL
(logical AND, e.g., ANL PI, A)
(logical OR, e.g., ORL P2, A)
ORL
(logical EX-OR, e.g., XRL P3, A)
XRL
mc
Gump if bit = I and clear bit, e.g.,
JBC Pl.l, LABEL)
(complement bit, e.g., CPL P3.0)
CPL
(increment, e.g., INC P2)
INC
(decrement, e.g., DEC P2)
DEC
4.5 Accessing External Memory
Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory
use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use RD or
WR (alternate functions ofP3.7 and P3.6) to strobe the
memory. Refer to Figures 5 through 7.
Fetches from external Program Memory always use a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOVX @ DPTR) or an
8-bit address (MOVX @ Ri).
11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 1ISTATE 21
1STATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
P2:
PCH OUT
PCH OUT
PCH OUT
270653-30
Figure 5. External Program Memory Fetches
8-10
intel·
8XC51FX HARDWARE DESCRIPTION
I
I
STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51
~I~
~I~
~I~
~I~
~I~
~I~
~I~
~I~
XTAL1:
ALE:
RD:
PO:
P2:
PCH OR
P2 SFR
DPH OR P2 SFR OUT
I
PCH OR
P2 SFR
270653-31
Figure 6. External Data Memory Read Cycle
41 STATE 51 STATE 81 STATE 11 STATE 21 STATE 31 STATE 41 STATE 51
ISTATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
ALE:
WR:
PCLOUTIF
'
~_MM_
IS EXTERNAL
PO:
~
-----I
PCH OR
P2 SFR
DPL OR RI
OUT
DATA OUT
DPH OR
~
~f ~
SFR OUT
PCH OR
~SFR
270653-32
Figure 7. External Data Memory Write Cycle
8-11
intel·
8XC51FX HARDWARE DESCRIPTION
Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. The Port 2 drivers
use the strong pullups during the entire time that they
are emitting address bits that are Is. This occurs when .
the MOVX @ DPTR instruction is executed. During
this time the Port 2 latch (the Special Function Register) does nothave to contain Is, and the contents of the
Port 2 SFR are not modified. If the external memory
cycle is not immediately followed by another external
memory cycle, the undisturbed contents of the Port 2
SFR will reappear in the next cycle.
If an 8-bit address is being used (MOVX @ Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. In this case,
Port 2 pins can be used to page the external data memory.
In either case, the low byte of the address is time-multiplexed with the data byte on Port o. The ADDRESS/
DATA signal drives both FETs in the Port 0 output
buffers. Thus, in external bus mode the Port 0 pins are
,not open-drain outputs and do not require external
pullups. The ALE (Address Latch Enable) signal
should be used to capture the address byte into an external latch. The address byte is valid at the negative
transition of ALE. Then, in a write cycle, the data byte
to be written appears on Port 0 just before WR is activated, and remains there until after WR is deactivated.
In a read cycle, the incomin~e is accepted at Port 0
just before the read strobe (RD) is deactivated.
During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register), thus obliterating the information in the Port 0
SFR. Also, a MOV PO instruction must not take place
during external memory accesses. If the user writes to
Port 0 during an external memory fetch, the incoming
code byte is corrupted. Therefore, do not write to Port
o if external program memory is used.
External Program Memory is accessed under two conditions:
1. Whenever signal EA is active, or
2. Whenever the program counter (PC) contains an address greater than IFFFH (8K) for the 8XC51FA or
3FFFH (16K) for the 8XC5IFB, or 7FFFH (32K)
for the 87C51FC.
5.0 TIMERS/COUNTERS
The C51FX has three 16-bit Timer/Counters: Timer 0,
Timer I, and Timer 2. Each consists of two 8-bit registers, THx and TLx, (x = 0, 1, and 2). All three can be
configured to operate either as timers or event counters.
In the Timer function, the TLx register is incremented
every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the oscillator frequency.
.
In the Counter function, the register is incremented in
response to a I-to-O transition at its corresponding external input pin-TO, Tl, or T2. In this function, the
external input is sampled during S5P2 of every machine
cycle. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. The
new count value appears in the register during S3PI of
the cycle following the one in which the transition was
. detected. Since it takes 2 machine cycles (24 oscillator
periods) to recognize a I-to-O transition, the maximum
count rate is '1.4 of the oscillator frequency. There are
no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at
least once before it changes, it should be held for at
least one full machine cycle.
In addition to the Timer or Counter selection, Timer 0
and Timer I have four operating modes from which to
select: Modes 0 - 3. Timer 2 has three modes of operation: Capture, Auto-Reload, and Baud Rate Generator.
5.1 Timer 0 and Timer 1
The Timer or Counter function is selected by control
bits CIT in the Special Function Register TMOD (Table 5). These two Timer/Counters have four operating
modes, which are selected by bit-pairs (MI, MO) in
TMOD. Modes 0, I, and 2 are the same for both Timer/Counters. Mode 3 operation is different for the two
timers.
MODE 0
Either Timer 0 or Timer I in Mode 0 is an 8-bit Counter with a divide-by-32 prescaler. Figure 8 shows the
Mode 0 operation for either timer.
This requires that the ROMless versions have EA wired
to Vss enable the lower 8K, 16K, or 32K program
bytes. to be fetched from external memory.
In this mode, the Timer register is configured as a
13-bit register. As the count rolls over from all Is to. all
Os, it sets the Timer interrupt flag TFx. The counted
input is enabled to the Timer when TRx = I and either
GATE = 0 or INTx = 1. (Setting GATE = I allows
the Timer to be controlled by external input INTx, to
facilitate pulse width measurements). TRx and TFx are
When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for general purpose I/O.
During external program fetches they output the high
byte of the PC with the Port 2 drivers using the strong
pullups to emit bits that are Is.
8-12
intal.
8XC51FX HARDWARE DESCRIPTION
control bits in SFR TCON (Table 6). The GATE bit is
in TMOD. There are two different GATE bits, one for
Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
MODE 2
Mode 2 configures the Timer register as an 8-bit Counter (TLx) with automatic reload, as shown in Figure 10.
Overflow from TLx not only sets TFx, but also reloads
TLx with the contents of THx, which is preset by software. The reload leaves THx unchanged.
The 13-bit register consists of all 8 bits of THx and the
lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate and should be ignored. Setting the run flag
(TRx) does not clear these registers.
MODE 1
Mode 1 is the same as Mode 0, except that the Timer
register uses all 16 bits. Refer to Figure 9. In this mode,
THx and TLx are cascaded; there is no prescaler.
Table 5. TMOD: Timer/Counter Mode Control Register
TMOD
Reset Value = 0000 OOOOB
Address = a9H
Not Bit Addressable
TIMER 0
TIMER 1
Bit
I GATE I
CIT
7
6
I
M1
5
I
MO
GATE
4
3
I
CIT
I
M1
I
2
MO
I
o
Symbol
Function
GATE
Gating control when set. Timer/Counter 0 or 1 is enabled only while INTO or INT1 pin
is high and TRO or TR1 control pin is set. When cleared, Timer 0 or 1 is enabled
whenever TRO or TR1 control bit is set.
Timer or Counter Selector. Clear for Timer operation (input from internal system
clock). Set for Counter operation (input from TO or T1 input pin).
CIT
M1
o
o
MO
0
1
o
Operating Mode
8-bit Timer/Counter. THx with TLx as 5-bit prescaler.
16-bit Timer/Counter. THx and TLx are cascaded; there is no prescaler.
a-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx
each time it overflows.
(Timer 0) TLO is an a-bit Timer/Counter controlled by the standard Timer 0 control
bits. THO is an a-bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter stopped.
INTERRUPT
x = Oor1
270653-6
Figure 8. Timer/Counter 0 or 11n Mode 0: 13·Blt Counter
8-13
infel .
8XC51FX HARDWARE DESCRIPTION
Table 6. TCON: Timer/Counter Control Register
TCON
Address
=
88H
Reset Value
=
OOOOOOOOB
Bit Addressable
TF1
TR1
TFO
TRO
IE1
IT1
7
6
5
4
3
2
Bit
lEO
ITO
o
Symbol
Function
TF1
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
.
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
TFO
Timer 0 overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared by
hardware when processor vectors to interrupt routine.
TRO
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
IE1
Interrupt 1 flag. Set by hardware when external interrupt 1 edge is detected
(transmitted or level-activated). Cleared when interrupt processed only if transitionactivated.
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupt 1.
lEO
Interrupt 0 flag. Set by hardware when external interrupt 0 edge is detected
(transmitted or level-activated). Cleared when interrupt processed only if transitionactivated.
ITO
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level
triggered external interrupt O.
THx
TLx
INTERRUPT
CONTROL
TxPIN - - - - - '
TRx----t
x = Oor 1
GATE
270653-34
Figure 9. Timer/Counter 0 or 1 in Mode 1: 16-Bit Counter
a timer function (counting machine cycles) and takes
over the use ofTRI and TFI from Timer 1. Thus THO
now controls the Timer 1 interrupt.
MODE 3
Timer 1 in Mode 3 simply holds its count. The effect is
the same as setting TRI = O.
Mode 3 is provided for applications requiring an extra
8-bit timer or counter. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of
and into its own Mode 3, or can still be used by the
serial port as a baud rate generator, or in any application not requiring an interrupt.
Timer 0 in Mode 3 establishes TLO and THO as two
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 11. TLO uses the Timer 0 control bits:
CIT, GATE, TRO, INTO, and TFO. THO is locked into
8-14
int'el.
8XC51FX HARDWARE DESCRIPTION
CiT = 0
INTERRUPT
_____--'1
Tx PIN -
CiT = 1
-
TRx------i
GATE
INTx PIN
x
~
Oar 1
270653-7
Figure 10. Timer/Counter 1 Mode 2: S-Bit Auto-Reload
~B--
osc
111210SC
1/12 IOSC - - - - - - . . . ,
~-- INTERRUPT
TO PIN _ _ _ _ _ _..J
OVERFLOW
CONTROL
GATE
1/12 IOSC
-----------+\..,.....1 I .\ (::~l HL._T_F_1. . .~
__ _ _ _ _ _}...JCONTROL
TRI
INTERRUPT
OVERFLOW
-
270653-8
Figure 11. Timer/Counter 0 Mode 3: Two S-Bit Counters
Table 7. Timer 2 Operating Modes
5.2 Timer 2
RCLK
Timer 2 is a 16-bit Timer/Counter which can operate
either as a timer or as an event counter. This is selected
by bit C/T2 in the Special Function Register T2CON
(Table 8). It has three operating modes: capture, autoreload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON as shown in
Table 7.
8-15
+
TCLK CP/RL2 T2*OE TR2
0
0
0
1
0
1
0
1
1
X
X
1
X
0
1
1
X
X
X
0
Mode
16-Bit
Auto-Reload
16-Bit
Capture
Baud_Rate
Generator
Clock-Out
on P1.0
Timer Off
int'et
8XC51FX HARDWARE DESCRIPTION
Table 8. T2CON: Timer/Counter 2 Control Register
T2CON
= OC8H
Address
Reset Value = 0000 OOOOB
Bit Addressable
TF2
EXF2
7
6
Bit
Symbol
I RCLK I TCLK IEXEN21
TR2
4
2
5
3
o
Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will
not be set when either RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition
on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not
cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used
for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
TCLK
transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used
for the transmit clock.
EXEN2 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
TR2
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2)
o = Internal timer (OSC/12 or OSC/2 in baud rate generator mode).
1 = External event counter (falling edge triggered).
CP/R[2 Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RClK = 1 or TCLK = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
16-bit timer or counter which upon overflow sets bit
TF2 in T2CON. This bit can then be used to generate
an interrupt. If EXEN2 = I, Timer 2 still does the
above, but with the added feature that a I-to-O tran-
CAPTURE MODE
In the capture mode there are two options selected by
bit EXEN2 in :f2CON. If EXEN2 = 0, Timer 2 is a
_
+ Cjf2-1
-
T2 PIN [ J - - - '
TR2
CAPTURE
nMER 2
INTERRUPT
TRANsmON
DETEcnON
T2EX PIN
EXEN2
270653-9
Figure 12. Timer 21n Capture Mode
8-16
intel.,
8XC51 FX HARDWARE DESCRIPTION
default to count up. When DCEN is set, Timer 2 can
count up or down depending on the value of the T2EX
pin.
sition at external input T2EX causes the current value
in the Timer 2 registers, TH2 and TL2, to be captured
into registers RCAP2H and RCAP2L, respectively. In
addition, the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can generate
an interrupt. The capture mode is illustrated in Figure
12.
Figure 13 shows Timer 2 automatically counting up
when DCEN = O. In this mode. there are two options
selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 counts up to OFFFFH and then sets the TF2
bit upon overflow. The overflow also causes the timer
registers to be reloaded with the l6-bit value in
RCAP2H and RCAP2L. The values in RCAP2H and
RCAP2L are preset by software. If EXEN2 = 1, a 16bit reload can be triggered either by an overflow or by a
l-to-O transition at external input T2EX. This transition also sets the EXF2 bit. Either the TF2 or EXF2
bit can generate the Timer 2 interrupt if it is enabled.
AUTO-RELOAD MODE
(UP OR DOWN COUNTER)
Timer 2 can be programmed to count up or down when
configured in its l6-bit auto-reload mode. This feature
is invoked by a bit named DCEN (Down Counter Enable) located in the SFR T2MOD (see Table 9). Upon
reset the DCEN bit is set to 0 so that Timer 2 will
Table 9. T2MOD: Timer 2 Mode Control Register
T2MOD
Reset Value = XXXX XXOOB
Address = OC9H
Not Bit Addressable
T20E
7
Bit
6
5
4
3
DCEN
o
2
Symbol
Function
T20E
DCEN
Not implemented, reserved for future use.'
Timer 2 Output Enable bit.
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down
counter.
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
T2 PIN
_
OVERflOW
+ cjT2 = 1
0----'
TR2
TRANSITION
DEfECTION
TIMER 2
INTERRUPT
T2EX PIN
EXEN2
270653-10
Figure 13. Timer 2 Auto Reload Mode (DCEN = 0)
B-17
8XC51FX HARDWARE DESCRIPTION
Setting the DCEN bit enables Timer 2 to count up or
down as shown in Figure 14. In this mode the T2EX
pin controls the direction of count. A logic I at T2EX
makes Timer 2 count up. The timer will overflow at
OFFFFH and set the TF2 bit which can then generate
an interrupt if it is enabled. This overflow also causes a
the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
The Clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:
Clock-out Frequency =
Oscillator Frequency
4 X (65536 - RCAP2H, RCAP2L)
In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator
simultaneously. Note, however, that the baud-rate and
Clock-out frequencies cannot be determined independently of one another since they both use the values in
RCAP2H and RCAP2L.
A logic 0 at T2EX makes Timer 2 count down. Now
the timer underflows when TH2 and TL2 equal the
values stored in RCAP2H and RCAP2L. The underflow sets the TF2.bit and causes OFFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows. This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not
generate an interrupt.
6.0 PROGRAMMABLE COUNTER
ARRAY
BAUD RATE GENERATOR MODE
The Programmable Counter Array (PCA) consists of a
16-bit timer/counter and five 16-bit compare/capture
modules as shown in Figure 15a. The PCA timer/counter serves as a common time base for the five modules
and is the only timer which can service the PCA. Its
clock input can be programmed to count anyone of the
following signals:
The baud rate generator mode is selected by setting the
RCLK and/or TCLK bits in T2CON. Timer 2 in this
mode will be described in conjunction with the serial
port.
PROGRAMMABLE CLOCK OUT
• oscillator frequency -;- 12
• oscillator frequency -;- 4
A 50% duty cycle clock can be programmed to come
out on Pl.O. This pin, besides being a regular I/O pin,
has two alternate functions. It can be programmed (I)
to input the external clock for Timer/Counter 2 or (2)
to output a 50% duty cycle clock ranging from 61 Hz
to 4 MHz at a 16 MHz operating frequency.
• Timer 0 overflow
• external input on ECI (Pl.2).
Each compare/capture module can be programmed in
anyone of the following modes:
• rising and/or falling edge capture
To configure the Timer/Counter 2 as a clock generator,
bit C/T2 (in T2CON) must be cleared and bit T20E in
T2MOD must be set. Bit TR2 (T2CON.2) also must be
set to start the timer (see Table 6 for operating modes).
• software timer
• high speed output
• pulse width modulator.
, Module 4 can also be programmed as a watchdog timer.
When the compare/capture modules are programmed
in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA
timer overflow share one interrupt vector (more about
this in the PCA Interrupt section).
8-18
infel ..
8XC51FX HARDWARE DESCRIPTION
(DOWN COUNTING RELOAD VALUE)
TOGGLE
T2 PIN
_ + C/T2=1
I:]--'
COUNT
DIRECTION
I
UP
0= DOWN
=
(UP COUNTING RELOAD VALUE)
T2EX PIN
270653-11
Figure 14. Timer 2 Auto Reload Mode (DCEN = 1)
PI.O
(T2)
---,
Transition
'!..... D.t.ctor
PI. 1
l- I
v-\l1-----1-~o
(T2EX)~
a----.
T20E (T21100.1)
Timor 2
Int.rrupt
EXEN2
270653-35
Figure 15. Timer 21n Clock-Out Mode
8-19
8XC51FX HARDWARE DESCRIPTION
-
16 BITS EACH - -
I.
1
MODULE 0
.1
1
I.
MODULE 1
1
:::: PI.3/CEXO
.::: PI.4/CEXI
-16BITS-
I
.1
PCA TI .. ER/COUNTER :
"'
1
.. ODULE 2
I
:::: Pl.5/CEX2
.r:'1-..
.r:'1-..·0:::
::...._ ..
_O_D_U_L_E_3_ _
:0::: PI.6/CEX3
~:...._M_O_D_U_L_E_4_ _
PI.7/CEX4
270653-12
Figure 15a. Programmable Counter Array
The PCA timer/counter and compare/capture modules
share Port 1 pins for external VO. These pins are listed
below. If the port pin is not used for the PCA, it can
still be used for standard I/O.
PCA Component
16-bit Counter
16-bit Module 0
16-bit Module 1
16-bit Module 2
16-bit Module 3
16-bit Module 4
External I/O Pin
P1.21 ECI
P1.3/ CEXO
P1.4/ CEX1
P1.51 CEX2
P1.6/ CEX3
P1.7/CEX4
6. t PCA 16·Bit Timer/Counter
The PCA has a free-running 16-bit timer/counter consisting of registers CH and CL (the high and low bytes
of the count value). These two registers can be read or
written to at any time. Figure 16 shows a block dia~
gram of this timer. The clock input can be selected
from the following four modes:
• Oscillator frequency .;- 12
.
The CL register is incremented at S5P2 of every
machine cycle. With a 16 MHz crystal, the timer
increments every 750 nanoseconds.
• Oscillator frequency .;- 4
The CL register is incremented at S1P2, S3P2 and
S5P2 of every machine cycle. With a 16 MHz crystal, the timer increments every 250 nanoseconds.
• Timer 0 overflows
The CL register is incremented at S5P2 of the machine cycle when Timer 0 overflows. This mode allows a programmable input frequency to the PCA.
• External input
The CL register is incremented at the first one of
S1P2, S3P2 and S5P2 after a 1-to-0 transition is detected on the ECI pin (P1.2). P1.2 is sampled at S1P2, S3P2 and S5P2 of every machine cycle. The maximum input frequency in this mode is
oscillator frequency .;- 8.
TO PCA MODULES 0-4
fOSC/12
fOSC/4
TIMER 0
OVERflOW
EXTERNAL
INPUT
(ECI)
~-kl"'-:-O-!I--_INTERRUPT
CIDL
PROCESSOR IN
IDLE MODE
270653-13
Figure 16. PCA Timer/Counter
8-20
inteL
8XC51FX HARDWARE DESCRIPTION
The CCON register, shown in Table II, contains two
more bits which are associated with the PCA timer!
counter. The CF bit gets set by hardware when the
counter overflows, and the CR bit is set or cleared to
turn the counter on or off. The other five bits in this
register are the event flags for the compare!capture
modules and will be discussed in the next section.
CH is incremented after two oscillator periods when
CL overflows.
The mode register CMOD contains the Count Pulse
Select bits (CPS I and CPSO) to specify the clock input.
CMOD is shown in Table 10. This register also contains the ECF bit which enubles the PCA counter overflow to generate the PCA interrupt. In addition, the
user has the option of turning off the PCA timer during
Idle Mode by setting the Counter Idle bit (CIDL). The
Watchdog Timer Enable bit (WDTE) will be discussed
in a later section.
Table 10. CMOD: PCA Counter Mode Register
CMOD
Address
=
Reset Value
OD9H
=
OOXX XOOOB
Not Bit Addressable
CIDL
I WDTE I
7
6
Bit
CPS1
5
4
3
2
CPSO
ECF
o
Symbol Function
CIDL
WDTE
CPS1
CPSO
ECF
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
Not implemented, reserved for future use.'
PCA Count Pulse Select bit 1.
PCA Count PiJlse Select bit O.
CPS1 CPSO Selected PCA Input"
o
0
Internal clock, Fosc -.;-12
o
1
Internal clock, Fosc -7- 4
1
0
Timer 0 overflow
1
1
External clock at ECI/P1.2 pin (max. rate = Fosc -7- 8)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be O. and its active value will be 1. The value
read from a reserved bit is indeterminate.
""Fosc = oscillator frequency
8-21
8XC51FX HARDWARE DESCRIPTION
Table 11. CCON: PCA Counter Control Register
CCON
Address
= 008H
Reset Value = OOXO OOOOB
Bit Addressable
Bit
CF
CR
7
6
CCF4
CCF3
CCF2
4
3
2
5
CCF1
CCFO
o
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an
interrupt if bit ECF in CMOO is set. CF may be set by either hardware or software but can
only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCFO
PCA Module 0 interrupt flag: Set by hardware when a match or capture occurs. Must be
cleared by software.
Not implemented, reserved for future use".
'NOTE:
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
when a module's event flag is set. The event flags
(CCFn) are located in the CCON register and get set
when a capture event, software timer, or high speed
output event occurs for a given module.
6.2 Capture/Compare Modules
Each of the five compare/capture modules has six possible functions it can perform:
16-bit Capture, positive-edge triggered
- 16-bit Capture, negative-edge triggered
- 16-bit Capture, both positive and negative-edge
triggered
16-bit Software Timer
16-bit High Speed Output
8-bit Pulse Width Modulator.
Table 13 shows the combinations of bits in the
CCAPMn register that are valid and have a defined
function. Invalid combinations will produce undefined
results.
Each module also has a pair of 8-bit compare/capture
registers (CCAPnH and CCAPnL) associated with it.
These registers store the time when a capture event occurred or when a compare event should occur. For the
PWM mode, the high byte regiser CCAPnH controls
the duty cycle of the waveform.
In addition, module 4 can be used as a Watchdog Timer. The modules can be programmed in any combination of the different modes.
The next five sections describe each of the compare/
capture modes in detail.
Each module has a mode register called CCAPMn
(n = 0, 1, 2, 3, or 4) to select which function it will
perform. The CCAPMn register is shown in Table 12.
Note the ECCFn bit which enables the PCA interrupt
8-22
int:el.
8XC51FX HARDWARE DESCRIPTION
Table 12. CCAPMn: PCA Modules Compare/Capture Registers
CCAPMO
CCAPM1
CCAPM2
CCAPM3
CCAPM4
Not Bit Addressable
CCAPMn Address
(n = 0-4)
OOAH
OOBH
OOCH
OOOH
OOEH
Reset Value = XOOO OOOOB
IECOMn I CAPPn I CAPNn I MATn
7
Bit
5
6
4
3
TOGn
PWMn
I ECCFn I
o
2
Symbol Function
Not implemented, reserved for future use'.
ECOMn Enable Comparator. ECOMn = 1 enables the comparator function.
Capture Positive, CAPPn = 1 enables positive edge capture.
CAPPn
CAPNn Capture Negative, CAPNn = 1 enables negative edge capture.
MATn
Match. When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
TOGn
Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
PWMn
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
ECCFn
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
Table 13. PCA Module Modes (CCAPMn Register)
-
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Module Function
X
0
0
0
0
0
0
0
No operation
X
X
1
0
0
0
0
X
16·bit capture by a postive·edge trigger on CEXn
X
X
0
1
0
0
0
X
16·bit capture by a negative·edge trigger on CEXn
X
X
1
1
0
0
0
X
16·bit capture by a transition on CEXn
X
1
0
0
1
0
0
X
16·bit Software Timer
X
1
0
0
1
1
0
X
16·bit High Speed Output
X
1
0
0
0
0
1
0
a·bit PWM
X
1
0
0
1
x
0
x
Watchdog Timer
x=
Don't Care
8-23
int'el.,
8XC51FX HARDWARE DESCRIPTION
In the interrupt service routine, the l6-bit capture value
must be saved in RAM before the next capture event
occurs. A ~ubsequent capture on the same CEXn pin
will write over the first capture value in CCAPnH and
CCAPnL.
6.3 16·Bit Capture Mode
Both positive and negative transitions can trigger a capture with the PCA. This gives the PCA the flexibility to
measure periods, pulse widths, duty cycles, and phase
differences on up to five separate inputs. Setting the
CAPPn and/or CAPNn in the CCAPMn mode register
select the input trigger-positive and/or negative transition-for module n. Refer to Figure 17.
6.4 16·Bit Software Timer Mode
In the compare mode, the 16-bit value of the PCA timer is compared with a 16-bit value pre-loaded in the
module's compare registers (CCAPnH, CCAPnL). The
comparison occurs three times per machine cycle in
order to recognize the fastest possible clock input (i.e.
'14 x oscillator frequency). Setting the ECOMn bit in
the mode register CCAPMn enables the comparator
function as shown in Figure 18.
The external input pins CEXO through CEX4 are sampled for a transition. When a valid transition is detected
(positive and/or negative edge), hardware loads the
16-bit value of the PCA timer (CH, CL) into the module's capture registers (CCAPnH, CCAPnL). The resulting value in the capture registers reflects the PCA
timer value at the time a transition was detected on the
CEXn pin.
For the Software Timer mode, the MATn bit also needs
to be set. When a match occurs between the PCA timer
and the compare registers, a match signal is generated
and the module's event flag (CCFn) is set. An interrupt
is then flagged if the ECCFn bit is set. The PCA interrupt is generated only if it has been properly enabled.
Software must clear the event flag before the next interrupt will be flagged.
Upon a capture, the module's event flag. (CCFn) in
CCON is set, and an interrupt is flagged if the ECCFn
bit in the mode register CCAPMn is set. The PCA interrupt will then be generated if it is enabled. Since the
hardware does not clear an event flag when the interrupt is vectored to, the flag must be cleared in software.
-I---~ INTERRUPT
L-..,...._..............
PCA
TIt.tER/COUNTER
CEXn
PIN
CCAPt.tn t.tODE REGISTER
n
x
~
~
0,1,2,3 or 4
Don't Care
270653-14
Figure 17. PCA 16·Bit Capture Mode
8-24
inteL
8XC51FX HARDWARE DESCRIPTION
During the interrupt routine, a new 16-bit compare value can be written to the compare registers (CCAPnH
and CCApnL). Notice, however, that a write to
CCAPnL clears the ECOMn bit which temporarily disables the comparator function while these registers are
being updated so an invalid match does not occur. A
write to CCAPnH sets the ECOMn bit and re-enables
the comparator. For this reason, user software should
write to CCAPnL first, then CCAPnH.
regular hold-off signals to the Watchdog. These circuits
are used in applications that are subject to electrical
noise, power glitches, electrostatic discharges, etc., or
where high reliability is required.
The Watchdog Timer function is only available on
PCA module 4. In this mode,every time the count in
the PCA timer matches the value stored in module 4's
compare registers, an internal reset is generated. (See
Figure 19.) The bit that selects this mode is WDTE in
the CMOD register. Module 4 must be set up in either
compare mode as a Software Timer or High Speed Output.
6.5 High Speed Output Mode
The High Speed Output (HSO) mode toggles a CEXn
pin when a match occurs between the PCA timer and a
pre-loaded value in a module's compare registers. For
this mode, the TOGn bit needs to be set in addition to
the ECOMn and MATn bits as seen in Figure 18. By
setting or clearing the pin in software, the user can
select whether the CEXn pin will change from a logical
o to a logical I or vice versa. The user also has the
option of flagging an interrupt when a match event occurs by setting the ECCFn bit.
When the PCA Watchdog Timer times out, it resets the
chip just like a hardware reset, except that it does not
drive the reset pin high.
To hold off the reset, the user has three options:
(I) periodically change the compare value so it will
never match the PCA timer,
(2) periodically change the PCA timer value so it will
never match the compare value,
(3) disable the Watchdog by clearing the WDTE bit
before a match occurs and then later re-enable it.
The HSO mode is more accurate than toggling port
pins in software because the toggle occurs before
branching to an interrupt. That is, interrupt latency
will not effect the accuracy of the output. If the user
does not change the compare registers in an interrupt
routine, the next toggle will occur when the PCA timer
rolls over and matches the last compare value.
The first two options are more reliable because the
Watchdog Timer is never disabled as in option # 3. The
second option is not recommended if other PCA modules are being used since this timer is the time base for
all five modules. Thus, in most applications the first
solution is the best option.
6.6 Watchdog Timer Mode
If a Watchdog Timer is not needed, module 4 can still
be used in other modes.
A Watchdog Timer is a circuit that automatically invokes a reset unless the system being watched sends
PCA
TIMER/COUNTER L..._ _..J
CEXn PIN
ENABLE
CCAPMn MODE REGISTER
RESET
WRITE TO
CCAPnL
n = 0,1,2,3 or 4
x
=
Don'1 Care
270653-15
Figure 18. PCA 16-81t Comparator Mode: Software Timer and High Speed Output
8-25
int:et
8XC51FX HARDWARE DESCRIPTION
The PCA generates 8-bit PWMs by comparing the low
byte of the PCA timer (CL) with the low byte of the
module's compare registers (CCAPnL). Refer to Figure
20. When CL < CCAPnL the output is low. When CL
;::: CCAPnL the output is high. The value in CCAPnL
controls the duty cycle of the waveform. To change the
value in CCAPnL without output glitches, the user
must write to the high byte register (CCAPnH). This
value is then shifted by hardware into CCAPnL when
CL rolls over from OFFH to DOH which corresponds to
the next period of the output.
6.7 Pulse Width Modulator Mode
Any or all of the five PCA modules can be programmed to be a Pulse Width Modulator. The PWM
output can be used to convert digital data to an analog
signal by simple external circuitry. The frequency of the
PWM depends on the clock sources for the PCA timer.
With a 16 MHz crystal the maximum frequency of the
PWM waveform is 15.6 KHz.
F::.::.j---I-'" -.f----+
PCA
TIMER/COUNTER ' -_ _.......
RESET
ENABLE
CCAPM4 MODE REGISTER
RESET
WRITE TO·
CCAP4L
WRITE TO
CCAP4H
x
~
Don't Care
270653-16
Figure 19. Watchdog Timer Mode
CL MADE
FF TO 00 _ _---'l~
TRANSITION
"0"
CL
<
CL
~
CCAPnL
CCAPnl
CEXn PIN
"1"
n
x
~
~
0, I, 2, 3 or 4
Don't Care
CCAPMn MODE REGISTER
Figure 20. peA 8-Bit PWM Mode
8-26
270653-17
int:eL
8XC51FX HARDWARE DESCRIPTION
DUTY CYCLE
CCAPnH
1001:
00
90%
25
50%
128
101:
230
0.4%
255
OUTPUT WAVEFORf.4
270653-18
Figure 21. CCAPnH Varies Duty Cycle
CCAPnH can contain any integer from 0 to 255 to vary
the duty cycle from a 100% to 0.4% (see Figure 21).
The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at
1/12 the oscillator frequency.
7.0 SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit
and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from
the receive register. (However, if the first byte still
hasn't been read by the time reception of the second
byte is complete, one of the bytes will be lost). The
serial port receive and transmit registers are both accessed through Special Function Register SBUF. Actually, SBUF is two separate registers, a transmit buffer
and a receive buffer. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically
separate receive register.
Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes
into RB8 in Special Function Register SCaN. The
baud rate is variable.
Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (1).
Refer to Figure 22. On Transmit, the 9th data bit (TB8
in SCaN) can be assigned the value of 0 or 1. Or, for
example, the parity bit (P in the PSW) could be moved
into TB8. On receive, the 9th data bit goes into RB8 in
SCaN, while the stop bit is ignored. (The validity of
the stop bit can be checked with Framing Error Detection.) The baud rate is programmable to either '132 or
'1.4 the oscillator frequency.
The serial port control and status register is the Special
Function Register SCaN, shown in Table 14. This register contains the mode selection bits (SMO and SMl);
the SM2 bit for the multiprocessor modes (see Multiprocessor Communications section); the Receive Enable bit (REN); the 9th data bit for transmit and receive
(TB8 and RB8); and the serial port interrupt bits (TI
and RI).
STOP BIT
NINTH DATA BIT (Mod .. 2 Bnd 3 only)
Figure 22. Data Frame: Modes 1, 2 and 3
8-27
270653-19
intet
8XC51FX HARDWARE DESCRIPTION
Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In
fact, Mode 3 is the same as Mode 2 in all respects
except the baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other
modes by the incoming start bit if REN = 1. For more
detailed information on eac.h serial port mode, refer to
the "Hardware Description of the 8051, 8052, and
80C51."
byte has its 9th bit set to O. All the slave processors
should have their SM2 bits set to 1 so they will only be
interrupted by an address byte. In fact, the C51FX has
an Automatic Address Recognition feature which allows only the addressed slave to be interrupted. That is,
the address comparison occurs in hardware, not software. (On the 8051 serial port, an address byte interrupts all slaves for an address comparison.)
The addressed slave's software then clears its SM2 bit
and prepares to receive the data bytes that will be coming. The other slaves are unaffected by these data bytes.
They are still waiting to be addressed since their SM2
bits are all set.
7.3 Automatic Address Recognition
7.1 Framing Error Detection
Automatic Address Recognition reduces the CPU time
required to service the serial port. Since the CPU is
only interrupted when it receives its own address, the
software overhead to compare addresses is eliminated.
With this feature enabled in one of the 9-bit modes, the
Receive Interrupt (RI) flag will only get set when the
received byte corresponds to either a Given or Broadcast address.
Framing Error Detection allows the serial port to check
for valid stop bits in modes 1,2, or 3. A missing stop bit
can be caused, for example, by noise on the serial lines,
or transmission by two CPUs simultaneously.
If a stop bit is missing, a Framing Error bit FE is set.
The FE bit can be checked in software after each reception to detect communication errors. Once set, the FE
bit must be cleared in software. A valid stop bit will not
clear FE.
The feature works the same way in the 8-bit mode
(Mode 1) as in the 9-bit modes, except that the stop bit
takes the place of the 9th data bit. If SM2 is set, the RI
flag is set only if the received byte matches the Given or
Broadcast Address and is terminated by a valid stop
bit. Setting the SM2 bit has no effect in Mode O.
The FE bit is located in SCON and shares the same bit
address as SMO. Control bit SMODO in the PCON register (location PCON.6) determines whether the SMO
or FE bit is accessed. If SMODO = 0, then accesses to
SCON.? are to SMO. If SMODO = 1, then accesses to
SCON.? are to FE.
7.2 Multiprocessor Communications
The master can selectively communicate with groups of
slaves by using the Given Address. Addressing all
slaves at once is possible with the Broadcast Address.
These addresses are defined for each slave by two Special Function Registers: SADDR and SADEN.
Modes 2 and 3 provide a 9-bit mode to facilitate multiprocessor comunication. The 9th bit allows the controller to distinguish between address and data bytes. The
9th bit is set to 1 for address bytes and set to 0 for data
bytes. When receiving, the 9th bit goes into RB8 in
SCON. When transmitting, TB8 is set or cleared in
software.
A slave's individual address is specified in SADDR.
SADEN is a mask byte that defines don't-cares to form
the Given Address. These don't-cares allow flexibility
in the user-defined protocol to address one or more
slaves at a time. The following is an example of how the
user could define Given Addresses to selectively address different slaves.
The serial port can be programmed such that when the
stop bit is received the serial port interrupt will be activated only if the received byte is an address byte (RB8
= 1). This feature is enabled by setting the SM2 bit in
SCON. A way to use this feature in mUltiprocessor systems is as follows.
Slave 1:
SADDR
SADEN
GIVEN
=
1111
1111
0001
1010
1111
OXOX
1111
1111
0011
1001
1111
OXX1
Slave 2:
SADDR
SADEN
GIVEN
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. Remember,
an address byte has its 9th bit set to 1, whereas a data
8-28
infel .
8XC51FX HARDWARE DESCRIPTION
Table 14. SCON: Serial Port Control Register
SCON
Address = 98H
Reset Value = 0000 OOOOB
Bit Addressable
iSMO/FEI
Bit:
SM1
7
6
(SMODO = 0/1)*
5M2
REN
TB8
RB8
5
4
3
2
TI
F.l1
a
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE
bit is not cleared by valid frames but should be cleared by software. The SMODO' bit must be
set to enable access to the FE bit.
SMa
Serial Port Mode Bit 0, (SMODO must = a to access bit SMa)
SM1
Serial Port Mode Bit 1
SM2
REN
SMO
SM1
Mode
Description
Baud Rate"
a
a
a
1
a
1
a
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
Fose/12
variable
Fose/64 or Fose/32
variable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If 5M2 = 1 then RI will
not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received
byte is a Given or Broadcast Address. In Mode 1, if 5M2 = 1 then RI will not be activated
unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, 5M2 should be o.
. Enables serial reception. Set by software to enable reception. Clear by software to disable
reception.
'
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop
bit that was received. In Mode 0, RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the
beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by
software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway
through the stop bit time in the other modes, in' any serial reception (except see 5M2). Must
be cleared by software.
NOTE:
'SMODO is located at peON6.
"Fosc = oscillator frequency
The SADEN byte are selected such that each slave can
be addressed separately. Notice that bit 1 (LSB) is a
don't-care for Slave l's Given Address, but bit I = 1
for Slave 2. Thus, to selectively communicate with just
Slave 1 the master must send an address with bit 1 = a
(e.g. 1111 0000).
Notice, however, that bit 3 is a don't-care for both
slaves. This allows two different addresses to select
both slaves (1111 0001 or 1111 0101). If a third slave
was added that required its bit 3 = 0, then the latter
address could be used to communicate with Slave 1 and
2 but not Slave 3.
Similarly, bit 2 = a for Slave 1, but is a don't-care for
Slave 2. Now to communicate with just Slave 2 an address with bit 2 = 1 must be used (e.g. 1111 0111).
The master can also communicate with all slaves at
once with the Broadcast Address. It is formed from the
logical OR of the SADDR and SADEN registers with
zeros defined as don't-cares. The don't-cares also allow
Finally, for a master to communicate with both slaves
at once the address must have bit 1 = 1 and bit 2 = o.
8-29
inl'el.
8XC51FX HARDWARE DESCRIPTION
flexibility in defining the Broadcast Address, but in
most applications a Broadcast Address will be OFFli.
Modes 1 and 3
Baud Rate
SADDR and SADEN are located at address A9H and
B9H, respectively. On reset, the SADDR and SADEN
registers are initialized to ooH which defines the Given
and Broadcast Addresses as XXXX XXXX (all don'tcares). This assures the C51FX serial port to be backwards compatibility with other MCS@-51 products
which do not implement Automatic Addressing;
The Timer 1 interrupt sholild be disabled in this application. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3
running modes. In most applications, it is configured
for "timer" operation in the auto-reload mode (high
nibble ofTMOD = ooI0B). In this case, the baud rate
is given by the formlila:
7.4 Baud Rates
Modes 1 and 3
2SMODl x Oscillator Frequency
Baud Rate =
32 x 12 x [256 - (TH1))
The baud rate in Mode 0 is fixed:
Mode 0 Bau d Rate
=
SMODl
=
2
x
TImer 1 Overflow Rate
32
One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a 16-bit timer (high nibble of
TMOD = OOOlB), and using the Timer 1 interrupt to
do a 16-bit software reload.
Oscillator Frequency
12
The baud rate in Mode 2 depends on the value of bit
SMODI in Special Function Register PCON. If
SMODI = 0 (which is the value on reset), the baud
rate is '164 the oscillatorfrequency. If SMODI = 1, the
baud rate is !fa. the oscillator frequency.
Table 15 lists various commonly used baud rates and
how they can be obtained from Timer 1.
7.6 Using Timer 2 to Generate Baud
Rates
Mode 2 Baud Rate = 2SMODl x OScillato~:requency
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 7). Note that
the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in
Figure 23.
The baud rates in Modes 1 and 3 are determined by the
Timer 1 overflow rate, or by Timer 2 overflow rate, or
by both (one for transmit and the other for receive). '
7.5 Using Timer 1 to Generate Baud
Rates
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
When Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by the
Timer 1 overflow rate and the value of SMOD I' as follows:
Table 15. Timer 1 Generated Commonly Used Baud Rates
Timer 1
Baud Rate
fose
SMOD
Mode 0 Max: 1 MHz
12MHz
Mode 2 Max: 375K
12MHz
12 MHz'
Modes 1, 3: 62.5K
11.059 MHz
19.2K
9.6K
'11.059 MHz
4.8K
11.059 MHz
11.059 MHz
2.4K
11.059 MHz
1.2K
137.5
11.986 MHz
110
6MHz
110
12MHz
8-30
X
1
1
1
0
()
0
0
0
0
0
CIT
Mode
Reload
Value
X
X
X
X
X
X
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
0
0
0
intel~
8XC51FX HARDWARE DESCRIPTION
The baud rates in Modes I and 3 are determined by
Timer 2's overflow rate as follows:
Modes 1 and 3 Baud Rates
~
as a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.
Timer 2 O~:rfIOW Rate
It should be noted that when Timer 2 is running (TR2
= I) in "timer" function in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP2 registers may be read, but
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. The timer
should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
The Timer can be configured for either "timer" or
"counter" operation. In most aEE!ications, it is configured for "timer" operation (C/T2 = 0). The "Timer"
operation is different for Timer 2 when it's being used
as a baud rate generator. Normally, as a timer, it increments every machine cycle (1/12 the oscillator frequency). As a baud rate generator, however, it increments
every state time ('12 the oscillator frequency). The baud
~ate formula is given below:
Modes 1 and 3
Baud Rate
Table 16 lists commonly used baud rates and how they
can be obtained from Timer 2.
Oscillator Frequency
32 x [65536 - (RCAP2H, RCAP2Lll
Table 16. Timer 2 Generated
Commonly Used Baud Rates
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a 16-bit unsigned
integer.
Baud
Rate
Osc
Freq
RCAP2H
RCAP2L
Timer 2 as a baud rate generator is shown in Figure 23.
This figure is valid only if RCLK and/or TCLK = I in
T2CON. Note that a rollover in TH2 does not set TF2,
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2
is in the baud rate generator mode. Note too, that if
EXEN2 is set, a I-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
375K
9.6K
4.8K
2.4K
1.2K
300
110
300
110
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
6MHz
6MHz
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
Timer 2
nMER 1
OVERFLOW
NOTE: OSC. FREa.IS DIVIDED BV 2. NOT 12.
T2P1N----......J
RX CLOCK
TX CLOCK
"TIMER 2"
T2EXPIN
INTERRUPT
EXEN2
L
NOTE
AVAILABI~ITV OF ADDITIONAL EXTERNAL INTERRUPT
270653-20
Figure 23. Timer 2 in Baud Rate Generator Mode
8-31
infel~
8XC51FX HARDWARE DESCRIPTION
All of the bits that generate interrupts can be set or
cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be cancelled
in software.
8.0 INTERRUPTS
The C51FX has a total of 7 interrupt vectors: two external interrupts (INTO and INTI), three timer interrupts (Timers 0, I, and 2), the PCA interrupt, and the
serial port interrupt. These interrupts are all shown in
Figure 24.
INTO---a'
Each of these interrupts will be briefly described followed by a discussion of the interrupt enable bits and
the interrupt priority levels.
ITO
TF'O-----~------------------.
INT1---a'
1T1
TF'1-----------------------------.
INTERRUPT
SOURCES
CF'~ECF'
5
~\---------....,D>---------------+~
D >-----------------+
rF'2X F ' 2 - - - - - - - - E
270653-21
(See exceptions when Timer 2 is used as baud rate generator or an up/down counter.)
Figure 24. Interrupt Sources
8-32
ini'et
8XC51FX HARDWARE DESCRIPTION
8.1 Externallnterrupts
8.3 peA Interrupt
External Interrupts INTO and INTI can each be either
level-activated or transition-activated, depending on
bits ITO and ITl in register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the
INTx pin. If ITx = 1, external interrupt x is negative
edge-triggered. The flags that actually generate these
interrupts are bits lEO and lEI in TCON. These flags
are cleared by hardware when the service routine is
vectored to only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag,
rather than the on-chip hardware.
The PCA interrupt is generated by the logical OR of
CF, CCFO, CCFl, CCF2, CCF3, and CCF4 in register
CCON. None of these flags is cleared by hardware
when the service routine is vectored to. Normally the
service routine will have to determine which bit flagged
the interrupt and clear that bit in software. The PCA
interrupt is enabled by bit EC in the Interrupt Enable
register (see Table 16). In addition, the CF flag and
each of the CCFn flags must also be enabled by bits
ECF and ECCFn in registers CMOD and CCAPMn
respectively, in order for that flag to be able to cause an
interrupt.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt request flag lEx will be set. lEx will be automatically
cleared by the CPU when the service routine is called.
8.4 Serial Port Interrupt
The serial port interrupt is generated by the logical OR
of bits RI and TI in register SCON. Neither of these
flags is cleared by hardware when the service routine is
vectored to. The service routine will normally have to
determine whether it was RI or TI that generated the
interrupt, and the bit will have to be cleared in software.
If external interrupt INTO or INTI is level-activated,
the external source has to hold the request active until
the requested interrupt is actually generated. Then it
has to deactivate the request before the interrupt service routine is completed, or else another interrupt will
be generated.
8.2 Timer Interrupts
Timer 0 and Timer 1 Interrupts are generated by TFO
and TFI in register TCON, which are set by a rollover
in their respective Timer/Counter registers (except see
Timer 0 in Mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip
hardware when the service routine is vectored to.
8.5 Interrupt Enable
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in the
. Interrupt Enable (IE) register. (See Table 17.) Note
that IE also contains a global disable bit, EA. If EA is
set (1), the interrupts are individually enabled or disabled by their corresponding bits in IE. If EA is clear
(0), all interrupts are disabled.
8.6 Priority Level Structure
Each interrupt source can also be individually programmed to one of two priority levels, by setting or
clearing a bit in the Interrupt Priority (IP) register
shown in Table 18. A low-priority interrupt can itself
be interrupted by a higher priority interrupt, but not by
another low-priority interrupt. A high priority interrupt cannot be interrupted by any other interrupt
source.
Timer 2 Interrupt is generated by the logical OR of bits
TF2 and EXF2 in register T2CON. Neither of these
flags is cleared by hardware when the service routine is
vectored to. In fact, the service routine may have to
determine whether it was TF2 or EXF2 that generated
the interrupt, and the bit will have to be cleared in
software.
8-33
intel .
8XC51FX HARDWARE DESCRIPTION
Table 17. IE: Interrupt Enable Register
IE
Reset Value = 0000 OOOOB
Address = OA8H
Bit Addressable
. EA
Bit
1
EC
ET2
ES
ET1
6
5
4
3
.7
Enable Bit = 1 enables the interrupt.
Enable Bit = a disables it.
EX1
ETa
EXO
o
2
Symbol
Function
EA
Global disable bit. If EA = 0, all Interrupts are disabled. If EA = 1, each Interrupt can be
individually enabled or disabled by setting or clearing its enable bit.
EC
ET2
PCAinterrupt enable bit.
Timer 2 interrupt enable bit.
ES
Serial Port interrupt enable bit.
ET1
Timer 1 interrupt enable bit.
EX1
External interrupt 1 enable bit.
ETa
Timer a interrupt enable bit.
External interrupt a enable bit.
EXO
Table 18. IP: Interrupt Priority Registers
IP
Address
= OB8H
Reset Value
Bit Addressable
7
Bit
PPC
PT2
PS
PT1
6
5
4
3
I. PX1
2
PTa
=
XOOO OOOOB
PXO
a
Priority Bit = 1 assigns high priority
Priority Bit = a assigns low priority
Symbol
Function
PPC
Not implemented, reserved for future use. •
PCA interrupt priority bit.
PT2
Timer 2 interrupt priority bit.
PS
PT1
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
PX1
PTO
PXO
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt a priority bit. .
NOTE:
·User software should not write 1s to reserved bits. These bits may be used in future B051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
8·34
intel.,
8XC51FX HARDWARE DESCRIPTION
If two requests of different priority levels are received
simultaneously,. the request of higher priority level is
serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence shown in Table 19.
Table 21. Priority Level Bit Values
Priority
Bits
Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priority level.
Table 19. Interrupt Priority
within Level Polling Sequence
1 (Highest)
IPH.x
IP.x
0
0
Level 0
0
1
Level 1
1
0
Level 2
1
1
Level 3 (Highest)
(Lowest)
How Interrupts are Handled
INTO
Timer 0
INT1
Timer 1
PCA
Serial Port
Timer 2
2
3
4
5
6
7 (Lowest)
Interrupt Priority
Level
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. The Timer 2 interrupt cycle is
slightly different, as described in the Response Time
section .. If one of the flags was in a set condition at
S5P2 of the preceding cycle, the polling cycle will find
it and the interrupt system will generate an LCALL to
the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the
following conditions:
1. An interrupt of equal 'or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in
the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to
the IE or IP registers.
8XC51FX Interrupt Priority Structure
In the 8XC51FX, a second Interrupt Priority register
(IPH) has been added, increasing the number of priority levels to four. Table 20 shows this second register.
The added register becomes the MSB of the priority
select bits and the existing IP register acts as the LSB.
This scheme maintains compatibility with the rest of
the MCS-51 family. Table 21 shows the bit values and
priority levels associated with each combination.
Table 20. IPH: Interrupt Priority High Register
IPH
Address = OB7H
Reset Value = XOOO 0000
Not Bit Addressable
Bit
7
PPCH
PT2H
PSH
6
5
4
Symbol
Function
PPCH
PT2H
PSH
PT1 H
PX1 H
PTOH
PXOH
Not implemented, reserved for future use.
PCA interrupt priority high bit.
Timer 2 interrupt priority high bit.
Serial Port interrupt priority high bit.
Timer 1 interrupt priority high bit.
External interrupt 1 priority high bit.
Timer 0 interrupt priority high bit.
External interrupt priority high bit.
8-35
PT1 H
PX1 H
PTOH
PXOH
320
infel .
8XC51FX HARDWARE DESCRIPTION
Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be
completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any write to IE or IP, then at least one more
instruction will be executed before any interrupt is vectored to.
Table 22. Interrupt Vector Address
Interrupt
Source
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. If the interrupt
flag for a level-sensitive external interrupt is active but
not being responded to for one of the above conditions
and is not still active when the blocking condition is
removed, the denied interrupt will not be serviced. In
other words, the fact that the interrupt flag was once
active but not serviced is not remembered. Every polling cycle is new.
Thus the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the appropriate servicing routine. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectored to, as shown in
Table 22.
lEO
TIMER 0
TFO
INT1
IE1
TIMER 1
TF1
Yes
001BH
SERIAL PORT
RI,TI
No
0023H
TIMER 2
TF2, EXF2
No
002BH
PCA
CF,CCFn
(n = 0-4)
No
0033H
Yes
OOOBH
No (level) 0013H
Yes (trans.)
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no
longer in progress, then pops the top two bytes from the
stack and reloads the Program Counter. Execution of
the· interrupted program continues from where it left
off.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking
interrupt was still in progress.
Note that the starting addresses of consecutive interrupt service routines are only 8 bytes apart. That means
if consecutive interrupts are being used (lEO and TFO,
for example, or TFO and IEI). and if the first interrupt
routine is more than 7 bytes long, thim that routine will
have to execute a jump to some other memory location
where the service routine can be completed without
overlapping the starting address of the next interrupt
routine.
········---C1-_."1I,..._--C2--...~I.-_ _ C3
IS5P21
No (level) 0003H
Yes (trans.)
INTO
The polling cycle/LCALL sequence is illustrated in
Figure 25.
Note that if an interrupt of a higher priority level goes
active prior to S5P2 of the machine cycle labeled C3 in
Figure 25, then in accordance with the above rules it
will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed.
Interrupt
Cleared by Vector
Request Bits Hardware Address
I •
C 4 - -......I.-.--C5--·····
56
········~'r----'--~111t----'---"t.l\'~----'----
f'71
INTERRUPT
GOES
ACTIVE
INTERRUPT
LATCHED
INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPT ROUTINE
270653-22
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or write IE or IP.
Figure 25. Interrupt Response Timing Diagram
8-36
int:eL
8XC51FX HARDWARE DESCRIPTION
or write to IE or IP, tile additional wait time cannot be
more than 5 cycles (a maximum of one or more cycle to
complete the instruction in progress, plus 4 cycles to
complete the next instruction if the instruction is MUL
or DIY).
8.7 Response Time
The INTO and INTI levels are inverted and latched
into the Interrupt Flags lEO and lEI at S5P2 of every
machine cycle. Similarly, the Timer 2 flag EXF2 and
the Serial Port flags RI and TI are set at S5P2. The
values are not actually polled by the circuitry until the
next machine cycle;
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.
The Timer 0 and Timer I flags, TFO and TFI, are set at
S5P2 of the cycle in which the timers overflow. The
values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag TF2 is set at S2P2 and is
polled in the same cycle in which the timer overflows.
9.0 RESET
The reset input is the RST pin, which has a Schmitt
Trigger input. A reset is accomplished by holding the
RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU
responds by generating an internal reset, with the timing shown in Figure 26.
If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapses between
activation of an external interrupt request and the beginning of execution of the service routine's first instruction. Figure 25 shows interrupt response timing.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2
of every machine cycle. ALE and PSEN will maintain
their current activities for 19 oscillator periods after a
logic 1 has been sampled at the RST pin; that is, for 19
to 31 oscillator periods after the external reset signal
has been applied to the RST pin. The port pins are
driven to their reset state as soon as a valid high is
detected on the RST pin, regardless of whether the
clock is running.
A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If
an interrupt of equal or higher priority level is already
in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If
the instruction in progress is not in its final cycle, the
additional wait time cannot be more than 3 cycles, since
the longest instructions (MUL and DIY) are only 4
cycles long, and if the instruction in progress is RETI
--1
I S2 I S3 I S4 I S5 I S6 I S1 I S2 I S3 I S4 I S5 I S6 I S1 I S2 I S3 I S4 I
/ - - 1 2 OSC. PERIODS
I S5 I S6 I S1
RST:
~/ 1111111117~
,
SAMPLE, RST
SAt.4PLE RST
,
ALE:
CINTERNAL RESET SIGNAL
-
IL..:'. . ._-In. __
..-I
PSEN:
po:
,
- - 1 1 OSC. PERIODS - - - - - - - - 1 9 OSC. PERIODS - - - - -....
270653-23
Figure 26. Reset Timing
8-37
infel·
8XC51FX HARDWARE DESCRIPTION
/
While the RST pin is high, the port pins, ALE and
PSEN are weakly pulled high. After RST is pulled low,
it will take 1 to 2 machine cycles for ALE and PSEN to
start clocking. For this reason, other devices can not be
synchronized to the,internal timings of the 8XC51FX.
Note that the port pins will be in a random state until the
oscillator has started and the internal reset algorithm
has written 1s to' them.
Powering up the device without a valid reset could
cause the CPU to start executing instructions from an
indeterminate location. This is because the SFRs, specifically the Program Counter, may not get' properly
initialized.
Driving, the ALE and PSEN pins to 0 while reset is
active could cause the device to go into an indeterminate state.
The internal reset algorithm redefines all the SFRs. Table I lists the SFRs and their reset values. The internal' ,
RAM is not affected by reset. On power, up the RAM
content is indeterminate.
For applications where power consumption is critical,
the C51FX provides two power reducing modes of operation: Idle and Power Down. The input through
which backup power is supplied during these operations is Vco Figure 28 shows, the internal circuitry
which implements these features. In the Idle mode
(IDL = 1), the oscillator continues to run and the Interrupt, Serial Port, PCA, and Timer blocks continue
to be clocked, but the clock signal is gated off to the
CPU. In Power Down (PD = 1), the oscillator is frozen. The Idle and Power Down modes are activated by
setting bits in Special Function Register PCON (Table
9.1 Power-On Reset
For CHMOS devices, when VCC is turned on, an automatic reset can be obtained by connecting the RST pin
to VCC through a 1 p.F capacitor (Figure 27). The
CHMOS devices do not require an external resistor like
the HMOS devices because they have an internal pulldown on the RST pin.
When power is turned on, the circuit holds the RST pin
high for an amount of time that depends on the capacitor value and the rate at which it charges. To ensure a
valid reset the RST pin must be held high long enough
to allow the oscillator to startup plus two machine
cycles.
Vcc -
23).
10.1 Idle Mode
An instruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions. The PCA can be programmed either to pause or continue operating during
Idle (refer to the PCA section for more details). The
CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during
Idle. The port pins hold the logical states they had at
the time Idle was activated. ALE and PSEN hold at
logic high levels:
....- - - - - - - - - ,
+
10.0 POWER-SAVING MODES OF
OPERATION
Vee
8XC51 F"A/FB/FC
RST
Vss
There are two ways to terminate the Idle Mode. Activation of any enabled interrupt will cause PCON.O to be
cleared by hardware, terminating the Idle mode. The
interrupt will be serviced, and following RET! the next
instruction to be executed will be the one following the
instruction that put the device into Idle.
270653-24
Figure 27. Power on Reset Circuitry
'On power up, Vcc should rise within approximately
ten milliseconds. The oscillator start-up time will depend on the oscillator frequency. For a 10 MHz crystal,
the start-up time'is typically 1 msec. For a 1 MHz
crystal, the start-up time is typically 10 msec.
The flag bits (GFO and GFl) can be used to give an
indication if an interrupt occurred during normal operation or during Idle. For example, an instruction that
activates Idle can also set one or both flag bits. When
Idle is terminated by an interrupt, the interrupt service
routine can examine the flag bits.
With the given circuit, reducing Vcc quickly to 0 causes the RST pin voltage to momentarily fall below OV.
However, this voltage is internally limited and will not
harm the device.
8-38
8XC51FX HARDWARE DESCRIPTION
The other way of terminating the Idle mode is with a
hardware reset. Since' the clock oscillator is still running, the hardware reset needs to be held active for only
two machine cycles (24 oscillator periods) to complete
the reset.
The signal at the RST pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes
program execution from where it left otT; that is, at the
instruction following the one that invoked the Idle
Mode. As shown in Figure 26, two or three machine
cycles of program execution may take place before the
~~
XTAL 2
....
XTAL 1
INTERRUPT,
I--,-.....-C>SERIAL PORT,
TIMER BLOCKS
CPU
270653-25
Figure 28. Idle and Power Down Hardware
Table 23. PCON: Power Control Register
PCON
Address = 8?H
Reset Value = OOXX OOOOB
Not Bit Addressable
ISMOD1 ISMODO I
Bit
?
6
5
POF
GF1
GFO
4
3
2
PD
IDL
o
Symbol
Function
SMOD1
Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rates, and the
Serial Port is used in modes 1, 2, or 3.
SMODO
When set, Read/Write accesses to SCON.? are to the FE bit. When clear, Read/Write
accesses to SCON.? are to the SMO bit.
POF
Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This
flag allows detection of a power failure caused reset. Vee must remain above 3V to retain
this bit.
GF1
General-purpose flag bit.
GFO
General-purpose flag bit.
Not implemented, reserved for future use. •
PD
Power Down bit. Setting this bit activates Power Down operation.
IDL
Idle mode bit. Setting this bit activates idle modes operation.
If 1s are written to PD and IDL at the same time, PD takes precedence.
NOTE:
,
·User softWare should not write 1s to unimplemented bits. These bits may be used in future 8051 family products to
invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
The value read from a reserved bit is indeterminate
8-39
infel·
8XC51FX HARDWARE DESCRIPTION
iittemal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during this
time, but access to the port pins is not inhibited. To
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to
external Data RAM.
warm start reset occurs while Vee is still applied to the
device and could be generated, for example, by a
Watchdog Timer or an exit from Power Down.
Immediately after reset, the user's software can check
the status of the POF bit. POF = 1 would indicate a
cold start. The software then clears POF and commences its tasks. POF =. 0 immediately after reset
would indicate a warm start.
10.2 Power Down Mode
Vee must remain above 3 volts for POF to retain a O.
An instruction that sets PCON.l causes that to be the
last instruction executed before going into the Power
Down mode. In this mode the on-chip oscillator is
stopped. With the clock frozen, all functions are
stopped, but the on-chip RAM and Special Function
Registers are held. The port pins output the values held
by their respective SFRs, and ALE and PSEN output
lows. In Power Down Vee can be reduced to as low as
2V. Care must be taken, however, to ensure that Vee is
not reduced before Power Down is invoked.
11.0 EPROM VERSIONS
The 8XCSIFX uses the Improved "Quick-Pulse" programming™ algorithm. These devices program at Vpp
= 12.7SV (and Vee = S.OV) using a series of five
100 pos PROG pulses per byte programmed. This results in a total programming time of approximately S
seconds for the 87CSIFA's 8 Kbytes, 10 seconds for the
87CSIFB's 16 Kbytes, and 20 seconds for the
87CSIFC's 32 Kbytes.
The CSIFX can exit Power Down with either a hardware reset or external interrupt. Reset redefmes all the
SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip
RAM to retain their values.
Exposure to Light: The EPROM window must be covered with an opaque label when the device is in operation. This is not so much to protect the EPROM array
from inadvertent erasure, but to protect the RAM and
other on-chip logic. Allowing light to impinge on the
silicon die while the device is operating can cause logical malfunction.
To properly terminate Power Down the reset or external interrupt should not be executed before Vee is
restored to its normal operating level and must be held
active long enough for the oscillator to restart and stabilize (normally less than 10 msec).
12.0 PROGRAM MEMORY LOCK
With an external interrupt, INTO or INTI must be enabled and configured as level-sensitive. Holding the pin
low restarts the oscillator and bringing the pin back
high completes the exit. After the RET! instruction is
executed in the interrupt service routine, the next instruction will be the one following the instruction that
put the device in Power Down.
In some microcontroller applications, it is desirable
that the Program Memory be secure from software piracy. The CSIFX has varying degrees of program protection depending on the device. Table 24 outlines the
lock schemes available for each device.
Encryption Array: Within the EPROM/ROM is an array of encryption bytes that are initially unprogrammed
(alII's). For EPROM devices, the user can program
the encryption array to encrypt the program code bytes
during EPROM verification. For ROM devices, the
user submits the encryption array to be programmed by
the factory. If an encryption array is submitted, LBI
will also be programmed by the factory. The encryption
array is not available without the Lock Bit. Program .
code verification is performed as usual, except that each
code byte comes out exclusive-NOR'ed (XNOR) with
10.3 Power Off Flag
The Power Off Flag (pOF) located at PCON.4, is set
by·hardware when Vee rises from 0 to S Volts. POF
can also be set or cleared by software. This allows the
user to distinguish between a "cold start" reset and a
"warm start" reset.
A cold start reset is one that is coincident with Vee
being turned on to the device after it was turned off. A
8-40
inlet.
8XC51FX HARDWARE DESCRIPTION
one of the key bytes. Therefore, to read the
ROM/EPROM code, the user has to know the encryption key bytes in their proper sequence.
Table 24. C51FX Program ProtectIon
Unprogrammed bytes have the value OFFH. If the En~
cryption Array is left unprogrammed, all the key bytes
have the value OFFH. Since any code byte XNOR'ed
with OFFH leaves the byte unchanged, leaving the Encryption Array unprogrammed in effect bypasses the
encryption feature.
When using the encryption array feature, one important factor should be considered. If a code byte has the
value OFFH, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is
left unprogrammed, a verification routine will display
the encryption array contents. For this reason all unused code bytes should be programmed with some value other than OFFH, and not all of them the same value. This will ensure maximum program protection.
Lock Bits
Encrypt Array
None
None
83C51FB
LB1
64 Bytes
83C51FC
LB1
64 Bytes
87C51FA
LB1,LB2,LB3
64 Bytes
87C51FB
LB1,LB2,LB3
64 Bytes
87C51FC
LB 1, LB2, LB3
64 Bytes
13.0 ONCETM MODE
The ONCE (ON-Circuit Emulation) mode facilitates
testing and debugging of systems using the C5lFX
without having to remove the device from the circuit.
The ONCE mode is invoked by:
1. Pulling ALE low while the device is in reset and
PSEN is high;
2. Holding ALE low as RST is deactivated.
Program Lock Bits: Also included in the Program
Lock scheme are Lock Bits which can be enabled to
provide varying degrees of protection. Table 25 lists the
Lock Bits and their corresponding influence on the microcontroller. Refer to Table 24 for the Lock Bits available on the various products. The user is responsible for
programming the Lock Bits on EPROM devices. On
ROM devices, LBl is automatically set by the factory
when the encryption array is submitted. The Lock Bit
is not available without the encryption array on ROM
devices.
Device
83C51FA
While the device is in ONCE mode, the Port 0 pins go
into a float state, and the other port pins, ALE, and
PSEN are weakly pulled high. The oscillator circuit
remains active. While the device is in this mode, an
emulator or test CPU can be used to drive the circuit.
. Normal operation is restored after a valid reset is applied.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returning the part to full functionality.
Table 25. Lock Bits
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. (Code verify will still be encrypted by the
encryption array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
P = Programmed
U = Unprogrammed
Any other combination of the Lock Bits is not defined.
8-41
intel .
8XC51FX HARDWARE DESCRIPTION
14.0 ON-CHIP OSCILLATOR
Frequency, tolerance, and temperature range are determined by the system requirements.
The on-chip oscillator for the CHMOS devices, shown
in Figure 29, consists of a single stage linear inverter
intended for use tis a crystal-controlled, positive reactance oscillator. In this application the crystal is operating in its fundamental response mode as an inductive
reactance in parallel resonance with capacitance external to the crystal (Figure 30).
A ceramic resonator can be used in place of the crystal
in cost-sensitive applications. When a ceramic. resonator is used, Cl and C2 are normally selected as higher
values, typically 47 pF. The manufacturer of the ceramic resonator should be consulted for recommendations
on the values of these capacitors.
A more in-depth discussion of crystal specifications, ceramic resonators, and the selection of values for Cl and
C2 can be found in Application Note AP-155, "Oscillators for Microcontrollers" in the Embedded Applications handbook.
The oscillator on the CHMOS devices can be turned off
under software control by setting the PO bit in the
PCON register. The feedback resistor Rr in Figure 29
consists of paralleled n- and p-channel PETs controlled
by the PO bit, such that Rr is opened when PO = 1.
The diodes 01 and 02, which act as clamps to Vee
and Vss, are parasitic to the Rr PETs.
To drive the CHMOS parts with an external clock
source, apply the external clock signal to XTALi and
leave XTAL2 floating as shown in Figure 31. This is an
important difference from the HMOS parts. With
HMOS, the external clock source is applied to XTAL2,
and XTALI is grounded.
The crystal specifications and capacitance values (Cl
and C2 in Figure 30) are not critical. 30 pF can be used
in these positions at any frequency with good quality
crystals. In general, crystals used with these devices
typically have the following specifications:
ESR (Equivalent Series Resistance) see Figure 32
Co (shunt capacitance)
7.0 pF maximum
CL (load capacitance)
30 pF ± 3 pF
Orive Level
1 MW
An external oscillator may encounter as much as a
100 pF load at XTALl when it starts up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed
20pF.
Vcc
TO INTERNAL
TlMINGCKTS
D1
4000
XTAL1
XTALZ
D2
r
PO
270653-26
Figure 29. On-Chip Oscillator Circuitry
8-42
intel .
8XC51 FX HARDWARE DESCRIPTION
VCC
TO INTERNAL
T1MING CKTS
VSS
XTAU------
8OC51
~'--'r---
Cl
QUARTZ CRYSTAL
OR CERAMIC
RESONATOR
C2
270653-27
Figure 30_ Using the CHMOS On-Chip Oscillator
BXC51FX
NC
500
XTAL2
~o----I XTAL 1
~ 400
x
o
.5 300
CMOS GATE
'"~
270653-28
200
100
Figure 31. Driving the CHMOS Parts with an
External Clock Source
4
8
12
16
CRYSTAL FREQUENCY In MHz
270653-29
15.0 CPU TIMING
The internal clock generator defines the sequence of
states that make up a machine cycle. A machine cycle
consists of 6 states, numbered SI through S6. Each
state time lasts for two oscillator periods. Thus a machine cycle takes 12 oscillator periods or I microsecond
if the oscillator frequency is 12 MHz. Each state is then
divided into a Phase I and Phase 2 half.
Rise and fall times are dependent on the external loading that each pin must drive. They are approximately
10 nsec, measured between O.SV and 2.0V.,
Figure 32. ESR vs Frequency
each other. The timings published in the data sheets
include the effects of propagation delays under the
specified test condition.
ADDITIONAL REFERENCES
The following application notes provide supplemental
information to this document and can be found in the
Embedded Applications handbook.
1. AP-125 "Designing Microcontroller Systems for
Electrically Noisy Environments"
2. AP-155 "Oscillators for Microcontrollers"
3. AP-252 "Designing with the SOC5IBH"
4. AP-410 "Enhanced Serial Port on the S3C5IFA"
5. AP-415 "S3C51FA/FB PCA Cookbook"
6. AB-41 "Software Serial Port Implemented with the
PCA"
7. AP-425 "Small DC Motor Control"
S. The appropriate data sheet.
Propagation delays are different for different pins. For
a given pin they vary with pin loading, temperature,
Vee, and manufacturing lot. If the XTALI waveform
is taken as the timing reference, propagation delays
may vary from 25 to 125 nsec.
The AC Timings section of the data sheets do not reference any timing to the XTAL1 waveform. Rather, they
relate the critical edges of control and input signals to
8-43
83C51 FA/80C51 FA
EXPRESS
83C51FA/80C51FA-3.5 MHz to 12 MHz, Vee = 5V ± 10%
83C51FA-1I80C51FA-1-3.5 MHz to 16 MHz, Vee = 5V ± 10%
83C51FA-2/80C51FA-2-Q.5 MHz to 12 MHz, Vee = 5V ± 10%
• Extended Temperature Range
•
Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS@-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125·C with Vee = 6.9V ± 0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
8-44
August 1988
Order Number: 270620-001
infel"
83C51FA/80C51FA EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°Cto + 85°C; Vee = 5V ±10%; Vss =
Symbol
Limits
Parameter
Min
IlL
Logical 0 Input Current (Port 1, 2, 3)
VOHl
Output High Voltage
(Port 0 in External Bus Mode)
Max
-75
Vee -1.5
ov
Unit
,...A
V
Test
Conditions
Vin = 0.45V
IOH = -6.0 mA
Table 1. Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
D
Cerdip
Commercial
No
N
TP
PLCC
Commercial
No
Plastic
Extended
No
TD
Cerdip
Extended
No
TN
PLCC
No
LP
Plastic
Extended
. Extended
LD
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
Yes
NOTE:
• Commercial temperature range is O°C to 70'C. Extended temperature range is ..:. 40'C to + 85'C.
• Burn·in is dynamic for a minimum time of 168 hours at 125'C, Vee = 6.9V ±0.25V, following guidelines in MIL-STD-883
Method 1015 (Test Condition D).
Examples:
P83C51 FA indicates 83C51 FA in a plastic package and specified for commercial temperature range, without
burn-in.
LD80C51 FA indicates 80C51 FA in a cerdip package and specified for extended temperature range with burnin.
8-45
87C51FA/83C51 FA/80C51 FA
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 8 KBYTES INTERNAL PROGRAM MEMORY
87CS1FAl83CS1FA/80CS1FA-3.S MHz to 12 MHz, Vee = SV ±20%
87CS1FA-1I83CS1FA-1I80CS1FA-1-3.S MHz to 16 MHz, Vee = 5V ±20%
83C51FA-2/80CS1FA-2-o.S MHz to 12 MHz, Vee = 5V ±20%
87C51FA-L-3.S MHz to 8 MHz, Vee = 3.3V ±O.3V
.
Processor
• 32Boolean
Programmable I/O Lines
• Interrupt Sources
• 7Programmable
Channel with:
• - Framing ErrorSerial
Detection
- Automatic Address Recognition
TTL Compatible Logic Levels
• 64K
Program Memory Space
• 64K External
External Data Memory Space
• MCS®-51
Compatible Instruction Set
• Power Saving
• Modes Idle and Power Down
• ONCE (On-Circuit Emulation) Mode
• High Performance CHMOS EPROM
• Low Voltage Operation (-L only)
• Power Control Modes
• Three 16-Blt Timer/Counters
• Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer Capabilities
• Up/Down Timer/Counter
• Three Level Program Lock System
• 8K On-Chip Program Memory
• 256 Bytes of On-Chip Data RAM
• Improved Quick Pulse Programming
Algorithm
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside on-chip (except 80C51 FA). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51 FA is a single-chip control oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. The Intel 83C51 FAl80C51 FA is fabricated on CHMOS III technology. Being a member of the MCS®-51 family, the 87C51 FA/83C51 FAl80C51 FA uses the same powerful instruction set, has the
same architecture, and is pin-for-pin compatible with the existing MCS-51 products. The 87C51 FA!B3C51 FA!
BOC51 FA is an enhanced version of the B7C52/BOC52/BOC32. Its added features make it an even more
powerful microcontroller for applications that require Pulse Width Modulation, High Speed 1/0 and upldown
counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications.
Applications that require low voltage operation can use the B7C51 FA-L. The 87C51 FA-L will operate at 3.3V
± O.3V at a frequency range of 3.5 MHz to B MHz.
For the remainder of this document, the B7C51 FA, 83C51 FA, BOC51 FA will be referred to as the 8XC51 FA,
unless information applies to a specific device.
8-46
October 1992
Order Number: 270258-007
int:eL
87C51FA/83C51FA/80C51FA
P2 .0- P2.7
PSEN
ALE/i'mlG
EA/vpp
RST
TIMING
AND
CONTROL
el
8~ \,~==~==~~========~~==::::==~======~~==~~~Ck~
'"
270258-1
Figure 1. 8XC51FA Block Diagram
PROCESS INFORMATION
The 87C51 FA is manufactured on P629.0, a
CHMOS III-E process. The 83C51 FA/80C51 FA are
manufactured on P645, a CHMOS III process. Additional process and reliability information is available
in Intel's Components Quality and Reliability Handbook, Order Number 210997.
8-47
·in1:el.
87C51 FA/83C51 FA/80C51 FA
PACKAGES
Prefix Package Type
Part
87C51FA
P
D
N
S
40·Pin Plastic
DIP (OTP)
40·Pin CERDIP
(EPROM)
44·Pin PLCC
(OTP)
44·PinOFP
(OTP)
OJ8
Part
0Jc
4SoC/W 16°C/W
Prefix Package Type
83C51FAI
80C51FA
P
4SoC/W 1SoC/W
40·Pin Plastic
DIP
40·Pin CERDIP
44·Pin PLCC
44·Pin OFP
D
N
S
46°C/W 16°C/W
018
°lc
45°C/W 16°C/W
36°C/W 13°C/W
46°C/W 16°C/W
97°C/W 24°C/W
97°C/W 24°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
(T2)
no
(T2EX) PI.I
Vee
PO.O (ADO)
(ECI) PI.2
PO.I (AOI)
(CEXO) PI.l
PO.2 (AD2)
(CEXI) PI ••
PO.l (AOl)
(CEX2) PI.5
PO •• (AD.)
(CEXl) P!.S
PO.S (ADS)
(CEU) PI.7
PO.& (ADS)
RESP
PO.7 (A07)
(RXD) Pl.O
EA
(TXO) Pl. I
ALE
(INTO) Pl.2
PSEN
(INTI) Pl.l
P2.7 (AI5)
(TO) Pl.4
P2.& (AI4)
(TI) Pl.5
P2.5 (All)
(ViR) Pl.S
(Rii) Pl.7
P2.4 (A 12)
XTAL2
P2.2 (AIO)
XTAL I
P2.1
INDEX
CORNER
<'j
..
;;: >~
"!
.. ..... ..'"
JJ g .,;
.,; .,;
PI.5
po .•
PI.&
PO.S
PI.7
PO.6
RST
PO.7
Pl.O
RESERVED'
RESERVED'
Pl.I
ALE
Pl.2
PSEH
Pl.l
P2.7
Pl.4
P2.6
Pl.5
P2.S
. . ...~ ~
::;
<-
'" .;
.;
P2.l (All)
vss
"': "l
;;: ;;: ;;:
><
"'.
",0
>
~
. . .... ....'" ..
0
~
(A9)
270258-23
P2.0 (A8)
PLCC
270258-2
DIP
INDEX
~
CORNER \
i i ~ i ; >8 g ~ g ~
.1::11:11~1.:;r I~II~II~II::;' I~II~II~I
P1.5
Cf . ·. ....,. . .,. --..
PI.6
2:~
~
Lf3
_I .... , .... , .... , .... , .....
PO,",
;:[2 PM
PI.7
:[~
;:[1 PO.S
RST
{!
[3:0 PD.7
P3.0 5:!
(~
Pl. I 7: ~
Pl.2
~
RESERVED'
8XC51 FA
P3."
EA
RESERVED'
;V
s:
P3.3
Ltg
;2)
;t6
its
it"
t!
(9!
ALE
PSEN
P2.7
P2.6
P3.S 1]!,.... ,..... ,.... ,.... ,.. "I,.................. .L:[3 P2.5
.'~II~II:!II:.!!II:eII:::II~II=II~IINII~lft
"I ...
270258-24
'Do not connect Reserved Pins.
Figure 2. Pin Connections
8·48
intel~
87C51FA/83C51FA/80C51FA
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
PIN DESCRIPTIONS
Vee: Supply voltage.
Port 2: Port 2 is an a-bit bidirectional 1/0 port with
internal pull ups. The Port 2 output buffers can drive
LS TIL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
Vss: Circuit ground.
VSS1: Secondary ground (only on PLCC and QFP of
a7C51 FA). Provided to reduce ground bounce and
improve power supply by-passing.
NOTE:
This pin is not a substitution for the Vss pin.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Port 0: Port 0 is an a-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS
TIL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1's, and can source and
sink several LS TIL inputs.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the pullups.
Port 1: Port 1 is an a-bit bidirectional 1/0 port with
internal pull ups. The Port 1 output buffers can drive
LS TIL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IlL, on the data sheet) because of the internal pullups.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
In addition, Port 1 serves the functions of the following special features of the aXC51 FA:
Port PIn
Alternate Function
P1.0
T2 (External Count Input to Timerl
Counter 2), Clock Out
P1.1
T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
P1.2
P1.3
CEXO (External 1/0 for Comparel
Capture Module 0)
P1.4
CEX1 (External 1/0 for Comparel
Capture Module 1)
CEX2 (External 1/0 for Compare I
Capture Module 2)
P1.5
P1.6
CEX3 (External 1/0 for Compare I
Capture Module 3)
P1.7
CEX4 (External 1/0 for Compare I
Capture Module 4)
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not (87C51 FA only). An
internal pulldown resistor permits a power-on reset
with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FA.
8-49
intet
87C51FA/83C51 FA/80C51 FA
In normal operation ALE is emitted at a constant
rate of Ys the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
put to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the
ALE-disable bit has no effect if the microcontroller is
in external execution mode.
Throughout the remainder of this data sheet, ALE .
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
C2
....--11/--...--1
XTAL2
I-_~--I XTAL 1
PSEN: Program Store Enable is the read strobe to
external Program Memory.
+-------1 vss
When the 8XC51FA is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
270258-3
C1, C2 = 30 pF ± 10 pF for Cryslals
For Ceramic Resonators, contact resonator manufacturer.
Figure 3. Oscillator Connections
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be internally latched on reset.
NIC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL I
vss
EA should be strapped to Vee for internal program
executions.
270258-4
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
Figure 4. External Clock Drive Configuration
XTAL 1: Input to the inverting oscillator amplifier.
IDLE MODE
XTAL2: Output from the inverting oscillator amplifier.
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the in8-50
87C51FA/83C51FA/80C51FA
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
• The 87C51 FA has some additional features that
are not available on the B3C51 FA!BOC51 FA. The
features are: Timer 2 clockout, 4 interrupt priority
levels, asynchronous port reset, 64-byte encryption array, and 3 program lock bits. These features cannot be used with the B3C51 FA!
BOC51FA.
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the BXC51 FA either hardware reset or external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the
SFRs and the on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt should not be executed before Vcc is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt, INTO or INT1 must be enabled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
ONCE MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
BXC51 FA without the 8XC51 FA having to be removed from the circuit. The ONCE Mode is invoked
by:
DESIGN CONSIDERATION
• The B7C51 FA-L will operate at 3.3V ± O.3V with a
frequency range of 3.5 MHz to B MHz. Operating
beyond these specifications could cause improper device functionality. (To program the
87C51 FA-L, follow the same procedure as the
B7C51 FA).
• Ambient light is known to affect the internal RAM
contents during operation. If the 87C51 FA application requires the part to be run under ambient
lighting, an opaque label should be placed over
the window to exclude light.
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the BXC51 FA isin this mode, an emulator
or test CPU can· be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
Idle
External
1
Power Down
Internal
0
0
Power Down
External
0
0
Mode
PORTO
PORT1
PORT2
PORT3
1
Data
1
Float
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the 80C51 BH."
B-51
87C51FA/83C51FA/80C51FA
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias. -40·C to +85·C
Storage Temperature .......... - 65·C to + 150·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on EAlVpp Pin to Vss ....... 0Vto + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V
IOL per 1/0 Pin ............... ."........... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
OPERATING CONDITIONS
T A (Under Bias)
=
O·C to + 70·C; Vee
=
5V ± 20%; Vss
=
OV
(87C51 FA-L, Vee = 3.3V ±0.3V)
DC CHARACTERISTICS
(Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol
Parameter
Typical
(Note 4)
Min
Max
Units
Test Conditions
VIL
Input Low Voltage
-0.5
0.2 Vee - 0.1
V
VIL1
Input Low Voltage EA
0
0.2 Vee - 0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2 Vee
Vee +0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
+ 0.5
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
0.45
1.0
V
IOL = 100fJ-A
IOL = 1.6 rnA (Note 1)
IOL = 3.5 rnA
VOL1
Output Low Voltage (Note 5)
(Port 0; ALE/PROG, PSEN)
0.3
0.45
1.0
V
IOL = 200 fJ-A
IOL = 3.2 mA (Note 1)
IOL = 7.0 rnA
VOH
Output High Voltage
(Ports 1, 2 and 3
ALE/PROG and PSEN)
Vee - 0.3
Vee - 0.7
Vee- 1.5
V
V
V
IOH= - 1O fJ-A
IOH = -30 fJ-A (Note 2)
IOH = -60 fJ-A
VOH1
Output High Voltage
(Port 0 in External Bus Mode)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
IOH = - 2OO fJ-A
IOH = -3.2 mA (Note 2)
IOH = -7.0mA
IlL
Logical 0 Input Current
(Ports 1, 2 and 3)
-50
fJ-A
VIN = 0.45V
III
Input leakage Current
(Port 0)
±10
fJ-A
VIN = VIL or VIH
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
-650
fJ-A
VIN = 2V
+
0.9
0.7 Vee
Vee
8-52
int:eL
87C51FA/83C51FA/80C51FA
DC CHARACTERISTICS
(Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol
RRST
Parameter
Min
RST Pulldown Resistor
87C51FA
83C51 FA/80C51 FA
Typical
(Note 4)
50
40
CIO
Pin Capacitance
Icc
Power Supply Current:
Active Mode
87C51 FA-L at 8 MHz
All Others at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
Max
Units
300
225
Kn
Kn
10
pF
Test Conditions
@1MHz,25'C
(Note 3)
12
40
7.5
75
20
5
5
mA
mA
mA
!J-A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOLs of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may
exceed O.BV. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vec specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vee for power down is 2V.
4. Typicals are based on limited number of samples. and are not guaranteed. The values listed are at room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10 rnA
.
Maximum IOL per B-bit port Port 0:
26 rnA
Ports 1. 2. and 3:
15 rnA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition. VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
40mA
r----------r----------r----------r----------,
30mA
~--------~----------+---------~c-------~
20mA
~--------~------~~+----------+------~~
lOrnA
1----------+-::;;;0--=::.....+----------+ MAX.
IDLE TYPICAL (4)
OmA ~--------~----------~--------~--------~
oMHz
4MHz
8MHz
12MHz
Icc Max at other frequencies is given by:
Active Mode
.
Icc MAX ~ 2.2 x FREQ + 3.1
Idle Mode
Icc MAX ~ 0.49 x FREQ + 1.6
Where FREQ is in MHz. IcCMAX is given in rnA.
Figure 5. Icc vs Frequency
8-53
16MHz
270258-5
intel .
87C51 FA/83C51 FA/80C51 FA
vee
RST
Vee
Vee
PO
PO
EA
RST
8XC51,A
CLOCK
SIGNAL
(NC)
EA 1----,
8XCSlfA
XTAL2
XTAL1
CLOCK
(NC)
SIGNAL
VSS
XTAL2
XTAL 1
Vss
270258-7
270258-6
All other pins disconnected
rCLCH = rCHCL = 5 ns
All other pins disconnected
rCLCH = rCHCL = 5 ns
Figure 6. Icc Test Condition, Active Mode
Figure 7. Icc Test Condition Idle Mode
Vee
PO
RST
.",.---
EA 1----,
8XCS1 fA
(NC)
XTAL2
XTALI
Vss
270258-8
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode.
Vcc = 2.0V to 5.5V.
Vce·O.S • - - - - - -1'""~----""Il
0.7 Vee
0.45V ---'(0.2 Vee·O.l
TCHCL
270258-19
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH
8·54
= TCHCL = 5 ns.
infel~
87C51FA/83C51FA/80C51FA
L: Logic level LOW, or ALE
P: PSEN
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
A: Address
X: No longer a valid logic level
Z: Float
C: Clock
D: Input Data
H: Logic level HIGH
For example,
I: Instruction (program memory contents)
T AVLL
=
Time from Address Valid to ALE Low
TLLPL
=
Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
1
TCLCL
Parameter
12 MHz Oscillator
Variable Oscillator
Min
Min
Max
3.5
3.5
0.5
12
16
12
Max
Oscillator Frequency
8XC51FA
8XC51FA-1
8XC51 FA-2
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
53
TLLAX
Address Hold After ALE Low
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
53
TCLCL-30
ns
TPLPH
PSEN Pulse Width
205
3TCLCL-45
ns
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
TCLCL-30
234
3TCLCL-105
145
0
0
400
TWLWH WR Pulse Width
400
TRLDV RD Low to Valid Data In
ns
TCLCL-25
ns
5TCLCL-105
ns
10
ns
6TCLCL-100
ns
6TCLCL-100
0
ns
5TCLCL-165
0
TRHDZ Data Float After RD
107
TLLDV
ALE Low to Valid Data In
8-55
ns
59
252
TAVDV Address to Valid Data In
ns
312
10
TRLRH RD Pulse Width
TRHDX Data Hold After RD
ns
4TCLCL-100
ns
ns
2TCLCL-60
ns
517
8TCLCL-150
ns
585
9TCLCL-165
ns
intel·
87C51 FA/83C51 FA/80C51 FA
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF) (Continued)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
12 MHz Oscillator
Parameter
:
Min
Max
300
Variable Oscillator
Units
Min
Max
3TCLCL-50
3TCLCL+50
TLLWL
ALE Low to RD or iNA Low
200
TAVWL
Address Valid to iNA Low
203
4TCLCL-130
ns
ns
TOVWX Data Valid to WR Transition
33
TCLCL-50
ns
TWHOX Data Hold after WR
33
TCLCL-50
ns
TOVWH Data Valid to iNA High
433
TRLAZ
AD Low to Address Float
TWHLH
RD or WR High to ALE High
7TCLCL-150
0
43
123
TCLCL-40
ns
0
ns
TCLCL+40
ns
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
PSEN
PORT 0
PORT 2
_ _J
----------,-----------~-------'
A8-A15
270258-9
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
'I
i-----TLLDV
--'1----
TRLRH - - - I
PORTO
PORT2
INSTR. IN
_-"~____________________________J
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A 15 FROM PCH
270258-10
8-56
87C51 FA/83C51 FA/80C51FA
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
--i..-TLHLL~
I
=t-lW~LH
\.
~
\.
!---TLLWL
.....
TAVLL
-
I-TLLAXPORTO
PORTZ
::r
~
lWLWH
J
~
.....
t-lWHQX
TQVWH
FROt.t'~i~~
DATA OUT
DPL
K XAO-A7 FROt.! PCL
INSTR. IN
TAVWL
=>
PZ.O-PZ.7 OR AB-A15 FROt.! DPH
AB-A 15 FROt.! PCH
270258-11
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions:
Symbol
Over Operating Conditions; Load Capacitance = 80 pF
Parameter
12 MHz Oscillator
Min
Max
Variable Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1
12TCLCL
,...s
TOVXH
Output Data Setup to Clock
Rising Edge
700
1OTCLCL -133
ns
TXHOX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
700
SHIFT REGISTER MODE TIMING WAVEFORMS
1OTCLCL -133
ns
int:et
87C51FA/83C51FA/80C51FA
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TClCl
Oscillator Frequency
8XC51FA
8XC51FA-1
8XC51FA-2
3.5
3.5
0.5
12
16
12
MHz
TCHCX
High Time
20
TClCX
low Time
20
TClCH
Rise Time
20
ns
TCHCl
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270258-13
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC - O . 5 - y - 0.2 vcc+ O•9
0.45 V
-A_
FLOAT WAVEFORMS
>C
TIMING REFERENCE
POINTS
' -_ _ _ _ _ _JVOL+O.l V
O_.2_V-"'cc;;..-_O_.1_ _ _ _ •
270258-15
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOLIiOH = ±20 rnA (oL, IOLIiOH = ±10 rnA).
270258-14
AC Inputs during testing are driven at Vee-0.5V for a Logic "I"
and O.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "1" and VOL max for 'a Logic "0".
Normally EAlVpp is held at logic high until just before AlE/PRpG is to be pulsed. Then EAlVpp is
raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The voltage on the EAlVpp pin must be at the valid EAlVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
PROGRAMMING THE EPROM
To be programmed, the part must be running with a
4 to 6 MHz osciUator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal EPROM locations.) The address of an
EPROM location to be programll)ed is applied to
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port O. The other Port 2 and 3 pins, RST PSEN,
and EAlVpp should be held at the "Program" levels
indicated in Table 2. AlE/PROG is pulsed low to
program the code byte into the addressed EPROM
location. The setup is shown in Figure 10.
NOTE:
eEAlVpp pin must not be allowed to go above the
maximum specified Vpp level for any amount of
time. Even a narrow glitch above that voltage level can cause permanent damage to the device.
The Vpp source should be well regulated and free
of glitches.
e Programming specifications for the 87C51 FA-l
are the same as the standard 87C51 FA.
8-58
inteL
87C51FA/83C51FA/80C51FA
Table 2. EPROM Programming Modes
Mode
Program Code Data
RST
PSEN
ALE!
PROG
EA!
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
H
L
"1...J
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
"1...J
12.75V
L
H
H
L
H
Program Lock
Bits
H
L
"1...J
12.75V
H
H
H
H
H
Bit2
H
L
"1...J
12.75V
H
H
H
L
L
Bit3
H
L
"1...J
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Bit 1
Read Signature Byte
+5V
87C51FA
vee
PO
PGM DATA
EA/Vpp
ALE/PROG 1 - _ _
}
PROGRAM
SIGNALS
PSEN
P2.7
P2.6
XTAL2
P3.7
CONTROL SIGNALS'
P3.6
P3.3
XTAL 1
RST
Vss
270258-20
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
Repeat 1 through 5 changing the address and data
for the entire array or untii the end of the object fiie is
reached.
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 FA the following sequence must be exercised.
PROGRAM VERIFY
1. Input the valid address on the address lines.
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C51 FA.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
The lock bits cannot be directiy verified. Verification
of the lock bits is done by observing that their features are enabled.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse, ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
8-59
87C51FA/83C51FA/80C51FA
ADDRESS
X
X
X
DATA
CONTROL
SIGNALS
12.7SV
X
X
8 BITS
7 BITS
-
J
TGHGL
-/1-
SV
Ef./Vpp
X
13 BITS
n n n
ALE/PROG
'-
S Pul_
270258-21
Figure 11. Programming Signals Waveforms
tion Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in its
original, unmodified form. For programming the Encryption Array; refer to Table 2 (Programming the
EPROM).
EPROM Lock System
The 87C51FA program lock system, when programmed, protects the onboard program against
software piracy.
The 87C51 FA has a 3-level program lock system
and a 64-byte encryption· array. Since this is an
EPROM device, all locations are user-programmable. See Table 3. The 83C51 FA does not have protection features.
When using the encryption array, one important factor needs to be considered. If a code byte has the
value OFFH, verifying the byte will produce the ericryption byte value. If a large block (>64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be programmed with some value other than OFFH, and not
all of them the same value. This will ensure maximum program protection. .
Encryption Array
Within the EPROM array are 64-bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryp-
Table 3. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
2
P
U
U
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on Reset, and
. further programming of the EPROM is disabled.
..
- -IS not defined_
Any other combination 01 the lock bits
8-60
intel~
87C51FA/83C51FA/80C51FA
Erasure Characteristics (Windowed
Packages Only)
Program Lock Bits
The 87C51 FA has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data.
Reading the Signature Bytes
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The 87C51 FA ha~ 3 signature bytes in locations
30H, 31 H, and 60H. The 83C51 FA has 2 signature
bytes in locations 30H and 31 H. To read these bytes
follow the procedure for EPROM verify, but activate
the control lines provided in Table 2 for Read Signa~
ture Byte.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose ·of at least 15 W-secl cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
Contents
Location
Erasure leaves the all EPROM Cells in a 1's state.
87C51FA
83C51FA
30H
89H
89H
31H
58H
53H
60H
FAH
8-61
87C51FA/83C51FA/80C51FA
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C; Vee = 5V ±20%; vss = OV)
Symbol
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
4
Units
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
TGHSL
Vpp Hold after PROG
TGLGH
PROGWidth
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
10
p.s
,10
p.s
90
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
110
p's
48TCLCL
p's
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
VERifiCATION
Pl.0-Pl.7 _ _ _ _ _<=:::!~~~
P2.0-P2.4
ADDRESS
TAVQV
PORT 0
AlE/PROG
-----1K:=~~~
TDVGl
DATA OUT
TGHDX
------"\1
...If
TGlGH
EA/Vpp
-~TEHS:P
EA/HIGH
---'
ti
TElQV
P2.7 _ _ _
L
I
111----1'"'1
,...._T_E_HQ_Z_ __
270258-18
NOTE:
°5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
8·62
int:et
87C51FA/83C51FA/80C51FA
DATA SHEET REVISION HISTORY
This data sheet (270258-007) is valid for devices with an "A" at the end of the topside tracking number. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet (270258-007) and the previous version (270258-006):
1. The 83C51 FA/80C51 FA CHMOS Single-Chip 8-Bit Microcontroller data sheet (270538-004) has been
combined with the 87C51 FA CHMOS Single-Chip 8-Bit Microcontroller with 8 Kbytes User Programmable
EPROM data sheet (270258-006) to create this new data sheet.
2. 83C51 FAl80C51 FA specs have been added to the Package Table and DC Characteristics Table.
3. Added 3.3V device to data sheet.
4. EPROM Programming Information has been added.
5. The Operating Temperature Range has been changed to: O°C to + 70°C.
The following differences exist between the -006 and the -005 versions of the 87C51 FA data sheet.
1. "NC" pin labels changed to "Reserved" in Figure 2.
2. 0ja and 0jc information added to Packages table.
3. Capacitor value for ceramic resonators deleted in Figure 3.
4. Maximum Power Down current spec corrected to 75 p.A from 7.5 p.A.
5. Pin numbers deleted from Figure 10.
6. Absolute Maximum Ambient Temperature under Bias changed from "o°c to +70°C" to "-40°C to
+85°C".
7. All references to Program Lock Bit and Encryption Array deleted from "Program Verification" section. This
information is available in the hardware description.
The following differences exist between the -005 and the -004 versions of the 87C51 FA data sheet:
1. Voltage tolerance changed from ± 10% to ± 20%.
2. Technology changed from CHMOS II-E to CHMOS III-E.
3. QFP package offering added.
4. Asynchronous port reset added.
5. ALE disable paragraph added.
6. C1, C2 guideline clarified in Figure 3.
7. Data sheet status notice and absolute maximum ratings warning reworded.
8. Operating Conditions heading added.
9. RRST changed from 40 K!l. min, 225 K!l. max to 50 K!l. min, 300 k!l. max
10. Typical values deleted for IlL, .ILI, ITL and RRST.
11. Note 1 (ALE noise pulses) reworded.
12. Figure 5 Icc graph lines extended from 12 MHz to 16 MHz.
13. Various EPROM programming algorithm changes implemented:
- P3.3 control line added to Table 2
-
Lock Bit 3 added to Table 2
-
Number of programming pulses decreased from 25 to 5
-
Figure 12 deleted
14. Number of Signature Bytes changed from 2 to 3.
15. Programming Supply Current changed from 50 mA to 75 mA Max.
16. Program Lock System changed from 2 Lock Bits to 3, and from 32 Encryption Bytes to 64.
8-63
int'el..
87C51FA/83C51FA/80C51FA
DATA SHEET REVISION HISTORY (Continued)
The following are the key differences between the -004 and the -003 versions of the 87C51 FA data sheet:
1. Included the 16 MHz device.
2. Deleted the word Maximum from the IOL line of ABSOLUTE MAXIMUM RATINGS.
3. Deleted the EA from VIH line of DC Table.
4. Pin capacitance now specified as Typical only.
The following are the key differences between the -003 and the -002 version of the 87C51 FA data sheet:
1. Data sheet was upgraded from ADVANCE INFORMATION to PRELIMINARY.
2. The old device name (87C252) was removed from the title.
3. PLCC pin connection diagram was added.
4. Package table was added.
5. Exit from Power Down Mode was clarified.
6. Maximum IOL per 1/0 was added to ABSOLUTE MAXIMUM RATINGS.
7. Note 4 was added to explain the maximum safe current specification.
8. IpD was improved from 100 /LA to 75 /LA.
9. Typical DC Characteristics were added for IlL. Ill. ITL. RRST and Icc.
10. Note 5 was added to explain the test conditions for typical values.
11. Timing specifications improved for:
TAVLL changed from "TCLCL - 55 to TCLCL - 40
TLLAX changed from TCLCL - 35 to TCLCL - 30
TLLPL changed from TCLCL-40 to TCLCL-30
TRHDZ changed from TCLCL-70 to TCLCL-60
TQVWX changed from "Address Valid Before WR" to "Data Valid to WR Transition" and changed from
TCLCL - 60 to TCLCL - 50
TQVWH was added.
12. Data sheet revision summary was added.
13. EA Leakage current not specified.
8-64
87C51FA
EXPRESS
•
Extended Temperature Range
•
Burn-In
•
3.5 MHz to 12 MHz Vee = 5V
± 10%
The Intel EXPRESS system offers enhancements to the operational specifications of the 8051 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 168 hours at '1 25·C with Vee
guidelines in MIL-STD-883, Method 1015.
= 6.9V ±0.25V, following
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.
8-65
June 1988
Order Number: 270619-001
intel®
Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA =
Symbol
-40°C to +85°C;Vcc
= 5V ±10%;Vss = OV
Limits
Parameter
Min
Unit
Max
Test
Conditions
IlL
Logical 0 Input Current (Port 1, 2, 3)
-75
/LA
VIN
= 0.45V
III
Input Leakage Current
(Port 0 and EA)
±15
/LA
VIN
= VIL or VIH
ITl
Logical 1 to 0 transition
Current (Ports 1, 2, 3)
-750
/LA
VIN
= 2.0V
ICC
Power Supply Current
Active Mode
Idle Mode
Power Down Mode
35
7.5
150
mA
mA
/LA
(Note 1)
NOTE:
1. Vee = 4.SV-S.SV, Frequency Range = 3.S MHz-12 MHz.
8-66
87C51FA EXPRESS
infel"
~[Q)\W~OO©[§ OOOIr@OOIMl~iiO@OO
Table 1. Prefix Identification
Prefix
Package Type
Temperature Range(2)
Burn-ln(3)
P
Plastic
Commercial
No
D
Cerdip
Commercial
No
N
PLCC
Commercial
No
TP
Plastic
Extended
No
TD
Cerdip
Extended
No
TN
PLCC
Extended
No
LP
Plastic
Extended
Yes
LD
Cerdip
Extended
Yes
Extended
Yes
LN
PLCC
.
NOTES:
2. Commercial temperature range is O'C to +70'C. Extended temperature range is -40'C to +B5'C.
3. Burn-in is dynamic for a minimum time of 16B hours at + 125'C. Vcc = 6.9V ±0.25V. following guidelines in MIL-STDBB3 Method 1015 (Test Condition D).
Examples:
P87C51 FA indicates 87C51 FA in a plastic package and specified for commercial temperature range, without
burn-in.
LD87C51 FA indicates 87C51 FA in a cerdip package and specified for extended temperature range with burnin.
8-67
87CS1FA-20/-3
COMMERCIAL/EXPRESS
20 MHz CHMOS MICROCONTROLLER
87C51FA-2Q-3.5 MHz to 20 MHz,Vee = 5V ±20%
87C51FA-3-24 MHz Internal Operation, Vee = 5V ±20%
CHMOS EPROM
• 24HighMHzPerformance
Internal Operation (-3 only)
• Power Control
Modes
• Three 16-Bit Timer/Counters
• Programmable Counter Array with:
• - High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer Capabilities
Up/Down Timer/Counter
• Three
Level Program Lock System
• 8K On-Chip
• 256 Bytes ofEPROM
Data RAM
• Improved QuickOn-Chip
Pulse Programming
• Algorithm
Processor
• Boolean
Programmable I/O Lines
• 732Interrupt
Sources
• Programmable
Channel with:
•. - Framing ErrorSerial
Detection
- Automatic Address Recognition
TTL Compatible Logic Levels
• 64K
Program Memory Space
• 64K External
External Data Memory Space
• MCS®-51 Compatible Instruction Set
• Power Saving Idle and Power Down
• Modes
• ONCE (On.Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51 FA-20 is a single-chip control oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS®-51 family, the 87C51 FA-20 uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The
87C51 FA-20 is an enhanced version of the 87C51. It's added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-processor communications.
The 87C51 FA-3 has the same 3.5 MHz to 20 MHz frequency range as the 87C51 FA-20 when operating out of
external program/data memory. When running out of internal program/data memory, the 87C51 FA-3 can
operate up to 24 MHz.
Throughout this document 87C51 FA-20 will refer to both the 87C51 FA-20 and the 87C51 FA-3.
8-68
September 1992
Order Number: 272081-002
intel~
87C51 FA-20/-3
PO.O - PO.7
-.,
r-----
V~
VSS
E
PSEN
ALEjPROG
rAjvpp
RST
TIUING
AND
CONTROL
P3.0 - P3.7
PloD - Pl.7
272081-1
Figure 1. 87C51FA-20 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
8-69
inteL
87C51FA-20/-3
PACKAGES
Part
Prefix
87C51FA-20
P
D
N
S
Package Type
40-Pin
40-Pin
44-Pin
44-Pin
Plastic DIP (OTP)
CERDIP (EPROM)
PLCC (OTP)
QFP (OTP)
8Ja
8Jc
45°C/W
45°C/W
46°C/W
97°C/W
16°C/W
15°C/W
16°C/W
24°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
INDEX
CORNER
"": "!
;;:
0..
q
;;:
"j
;;:
0..
.. '"
iii " q .,; .,; .,;
f
>VI >u
0..
n.
0..
PLS
PO.4
PLS
PO.S
Pl.7
PO.S
RST
PO.7
P3.0
EA/Vpp
Reserved-
Reserved-
P3.1
ALE/PRoG
P3.2
(T2) Pl.D
Vee
PO.O (ADO)
P3.3
PLI
P3.4
P2.6
(ECI) PL2
PO. 1 (AD!)
P3.S
P2.S
(CEXO) PL3
PO.2 (AD2)
(CEX1) PL4
PO.3 (AD3)
(CEX2) Pl.S
PO.4 (AD4)
(CEX3) Pl.S
PO.S (ADS)
(T2EX)
(CEX4) PL7
PO.S (ADS)
RESET
PO.7 (AD7)
EA/Vpp
(TXD)
ALE/PRoG
(iijTo) P3.2
(iiffi) P3.3
PSEN
P2.7
(1)
;! ;!
x
x
;
P2.7
...
'"
'" '" '" '" '"
N
0
0..
n.
0..
0..
o.
'"
272081-3
PLCC
(RXD) P3.0
P3.1
31
INDEX
CORNER \
(A15)
"": "!
"j
o.
0..
;;:
q
o.
0..
'"
N
iii "q .,; .,;
.,;
>'" ~ f 0.. 0.. 0..
_I:II~II~II;II~II~II:::;II~II~II~II~I
(TO) P3.4
P2.S (A14)
(T1) P3.S
(WR) P3.6
P2.S (A13)
-1
PL5 1_ •
L3)
P2.4 (A12)
Pl.S
(~
L3)
PO.S
(Ro) P3.7
P2.3 (All)
PL7
3_ •
L:[l
PO.S
;:(0
PO.7
XTAL2
P2.2 (AID)
XTAL1
P2.1
VSS
.~.~.~.~.~._I.~.~._I.~.~
RST
(A9)
P3.0
P2.D (AS)
Reserved-
P3.1
272081-2
P3.2
DIP
P3.3
-1
{~
5: !
(~
L2) EA/Vpp
S7CS1FA-2D
-1
7_ •
(!
-1
9_ •
P3.4
IE:
P3.S
1] :
PO.4
1:(8
Reserved-
Pf7
L_
ALE/PRoG
;)j
L~
PSEN
;:2:4
P2.6
L2)
P2.S
P2.7
.:~~ ~~ :!~ :~~ ~~~ :~~ :~~ :~~ ~~ :~~ :~~-
272081-4
QFP
• Do not connect reserved pins.
Figure 2. Pin Connections
8-70
inteL
87C51 FA-20/-3
PIN DESCRIPTIONS
Name and Function
Symbol
Vee
Main supply voltage (5V).
Vss
Circuit ground.
VSS1
Secondary ground (connection not necessary). Provided to reduce ground bounce and
improve power supply bypassing.
NOTE:
This pin is not a substitute for the Vss pin. Connect Vss and VSS1 with the lowest
impedance path possible.
Port 0
8-bit, open drain, bidirectional I/O port. These pins are shared with the multiplexed
address/data bus which has strong internal pullups. Port 0 also receives the code bytes
during EPROM programming, and outputs the code bytes during verification. When used as
an I/O port, pullups to Vee may be needed.
Port 1
8-bit bidirectional I/O port. All of the port 1 pins are shared with other functions in the
87C51 FA-20. Port 1 is also used as the low-order address byte input during EPROM
programming.
Port 2
8-bit bidirectional I/O port. Port 2 also emits the high-order address byte during accesses to
16-bit external memory locations. Some of the Port 2 pins are also used as address bits for
EPROM programming.
Port 3
8-bit bidirectional I/O port. All of the port 3 pins are shared with other functions in the
87C51 FA-20. Two of the pins are used as control lines (RD, WR) for accessing external
RAM.
RESET
Reset input to the chip. A high Input for a minimum of two machine cycles with the oscillator
running resets the device. The port pins will be reset when a voltage above VIH is applied
whether the oscillator is running or not. RST has an internal pulldown.
ALE/PROG
Address Latch Enable. Provides a signal to demultiplex the address from the address/data
bus. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency.
Note, however, that one ALE pulse is skipped during each access to external data memory.
If desired, ALE can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode. This pin is also the program pulse input during EPROM programming.
PSEN
Program Store Enable. Acts as read strobe for external program memory fetches.
EAlVpp
External Access Enable. EA must be strapped to VSS in order to enable the device to fetch
code from external program memory locations OOOOH to OFFFFH. EA should be strapped
to Vee for internal program executions. If any of the lock bits are programmed, EA will be
internally latched on reset. This pin also receives the programming supply voltage (Vpp)
during EPROM programming.
XTAL1
Input to the inverting oscillator amplifier.
XTAL2
Output from the inverting oscillator amplifier.
8-71
int:et
87C51FA-20/-3
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature
Under Bias .................. - 40°C to + 85°C
Storage Temperature .......... - 65°C to + 150°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V
Voltage on Any Other Pin to VSS .. -0.5V to + 6.5V
IOL per I/O Pin ........................... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
-40
+70
+85
°C
°C
Vee
Supply Voltage
4.0
6.0
V
fose
Oscillator Frequency
3.5
20
MHz
TA
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
Typical
(Note 4)
Min
Max
Units
Test Conditions
VIL
Input Low Voltage
-0.5
0.2 Vee - 0.1
V
VIL1
Input Low Voltage EA
0
0.2 Vee - 0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2 Vee + 0.9
vee + 0.5
V
VIH1
Input High Voltage
(XTAL 1, RST)
0.7 Vee
Vee + 0.5
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
0.45
1.0
V
VOL1
Output Low Voltage (Note 5)
(Port 0, ALE/PROG, PSEN)
0.3
0.45
1.0
V
VOH
Output High Voltage
(Ports 1, 2 and 3
ALE/PROG and PSEN)
Vee - 0.3
Vee - 0.7
Vee- 1.5
V
V
V
VOH1
Output High Voltage
(Port 0 in External bus Mode)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
IlL
Logical 0 Input Current
(Ports 1, 2 and 3)
Commercial
Express
-50
-75
p.A
VIN
= 2.0V
Input Leakage Current (Port 0)
Commercial
Express
±10
±15
p.A
VIN
= VIL or VIH
III
8-72
= 100 p.A
= 1.6 mA (Note 1)
= 3.5 mA
IOL = 200 p.A
IOL = 3.2 mA (Note 1)
IOL = 7.0 mA
IOH = -10 p.A
IOH = - 30 p.A (Note 2)
IOH = -60 p.A
IOH = - 200 p.A
IOH = -3.2 mA (Note 2)
IOH = -7.0 mA
IOL
IOL
IOL
int:eL
87C51FA-20/-3
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Parameter
Symbol
ITL
Min
Typical
(Note 4)
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Commercial
Express
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
Icc
Power Supply Current
Active Mode
Commercial
Express
Idle Mode
Power Down Mode
Max
Units
-650
-750
iJ-A
300
K!l
Test Conditions
,
50
10
VIN = 2.0V
pF
@1MHz,25°C
(Note 3)
24
47.1
55
8
1104
mA
mA
mA
5
75
iJ-A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above OAV to be superimposed on the VOLS of
ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when
these pins change from 1 to O. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals
may exceed O.SV. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 4-7 for test conditions. Minimum Vee for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
.
Maximum IOL per port pin:
10 rnA
Maximum IOL per S-bit port Port 0:
26 mA
15 rnA
Ports 1, 2 and 3:
Maximum total IOL for all output pins:
71 rnA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
50mAr---------~----------,_----------r_--------_.----------,
40mA~--------_+----------~--------~r_--------_+~~~----;
30mA~--------_+----------4_----~--~~~------_+~--------~
20mA~--------_+------~~4_----------~------~~~~=-----~
lIlmAt;~~~=:J
IDLE TYPICAL (4)
OmA
o MHz
4 MHz
Icc Max at other frequencies is given by:
Active Mode
Icc Max = 2.2 x FREQ + 3.14
Idle Mode
Icc Max = 0.49 x FREQ + 1.6
Where Osc Freq is in MHz, Icc is in rnA
8 MHz
12 MHz
Figure 3. Icc vs Frequency
8-73
16 MHz
20 MHz
272081-7
intet
87C51FA-20/-3
Vee
Vee
PO.,._ _....
PO
RST
EA!+---'
RST
EAt---,
87C51FA-20
CLOCK
XTAL2
SlGNAL---+I XTAL 1
VSS
CLOCK
XTAL2
SIGNAL---+I XTALt
Vss
272081-9
272081-8
All other pins disconnecled
TCLCH ~ TCHCL ~ 5 ns
All olher pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 5. Icc Test Condition Idle Mode
Figure 4. Icc Test Condition, Active Mode
Vee
RST
PO .'r--~
EAt---,
XTAL2
XTAL 1
Vss
272081-10
All other pins disconnecled
Figure 6. Icc Test Condition, Power Down Mode.
Vcc = 2.0V to 5.5V.
Vee -0.5
-------'.1"'"-----"""-
0.7 Vee
0.45V - - -TrO.2 vee-0.1
TCHCL
272081-11
Figure 7. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TClCH
8-74
=
TCHCl
=
5 ns.
inteL·
87C51FA·20/·3
L: Logic level LOW, or ALE
EXPLANATION OF THE AC SYMBOLS
P:PSEN
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
Q: Output Data
R: RD signal
T:Time
V: Valid
W: WR signal
A: Address
X: No longer a valid logic level
C: Clock
Z: Float
D: Input Data
For example,
H: Logic level HIGH
I: Instruction (program memory contents)
TAVLL
= Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
AC CHARACTERISTICS: (Under Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
1
Parameter
-TCLCL
Oscillator Frequency
87C51FA-20
TLHLL
ALE Pulse Width
20 MHz OSCillator
Variable OSCillator
Min
Min
Max
3.5
20
Max
Units
MHz
60
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
10
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
20
TCLCL-30
ns
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
20
105
4TCLCL-75
125
TCLCL-30
ns
ns
3TCLCL-45
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
30
TCLCL-20
ns
TAVIV
Address to Valid Instruction In
145
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
0
0
TRLRH RD Pulse Width
200
TWLWH WR Pulse Width
200
TRLDV RD Low to Valid Data In
TRHDX Data Hold After RD
ns
6TCLCL-100
ns
5TCLCL-95
ALE Low to Valid Data In
TAVDV Address to Valid Data In
8-75
ns.
ns
0
0
ns
ns
6TCLCL-100
155
TRHDZ Data Float After RD
TLLDV
ns
3TCLCL-90
60
40
2TCLCL-60
ns
310
8TCLCL-90
ns
360
9TCLCL-90
ns
infel .
87C51 FA-20/-3
AC CHARACTERISTICS: (Under Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF) (Continued)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Variable Oscillator
Min
Max
Min
200
TLLWL
ALE Low to RD or WR Low
100
TAVWL
Address Valid to WR Low
Units
Max
3TCLCL-50 3TCLCL+50
ns
110
4TCLCL-90
ns
TQVWX Data Valid to WR Transition
15
TCLCL-35
ns
TWHQX Data Hold after WR
10
TCLCi..-40
ns
280
7TCLCL-70
ns
TQVWH Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
0
10
123
0
ns
TCLCL+40
ns
I
TCLCL-40
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _- ,
PSEN _ _J
PORT 0
PORT 2
---'
AB-AI5
---'~----------------"'.~------------2720BI-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
i-----TLLDV
-,
---1--- TRLRH
RD
PORTO
PORT 2
INSTR. IN
P2.0-P2.7 OR AB-A 15 FROM DPH
AB-AI5 FROM PCH
272081-13
8-76
infel .
87C51 FA-20/-3
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
t. '
I
TLHLL-
\.
~
:::t-TWHLH
\.
,
-TLLWL
....
TAVLL
-
-TLLAX-
:::r
PORTO
..
J
~
TQVWH
AO-A
FROII RI OR DPL
-TWHQX
DATA OUT
AD-A7 FROM PCL
INSTR. IN
TAVWL
=>
PORT 2
TWLWH
X
P2.0-P2.7 OR AB-A 15 FROM DPH
AB-A15 FROM PCH
·272081-14
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: Over Operating Conditions; Load C~pacitance
Parameter
Symbol
= 80 pF
20 MHz Oscillator
Min
Variable Oscillator
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
600
12TCLCL
ns
TQVXH
Output Data Setup to Clock
Rising Edge
367
1OTCLCL -133
ns
TXHQX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-50
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
o·
ns
TXHDV
Clock Rising Edge to Input
Data Valid
1OTCLCL -133
367
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
ALE
CLOCK
OUTPUT DATA
~
__~~__~~__-JX~__3__~X
4
X
5
X
t
6
X
7
I
•
SET TI
WRITE TO SBUF
INPUT DATA - - - - - - -.......~~,,....."~~_""I~~I"'"_.~~,......,~~~-~~.
__~~_u~~
•
t
SET RI
CLEAR RI
272081-15
8-77
87C51FA-20/-3
C2
I-~"""-'"
XTAL 2
N/c
XTAL2
1--+----1 XTAL 1
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
+--------1 VSS
VSS
272081-5
Cl, C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer.
272081-6
Figure 9. External Clock Drive Configuration
Figure 8. Oscillator Connections
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
3.5
20
MHz
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
TCHCL
Fall Time
ns
ns
20
20
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272081-16
FLOAT WAVEFORMS
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC-o.s~_D_.2_V..:C..:C_+_D._9
0.45 V
-.1'\
0.2 VCC- D.1
'(LOAD
_ _ _ _:
A-
TIMING REFERENCE
POINTS
VOH-D.l V
VOL+O.l V
272081-18
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOL/IOH ;;, ± 20 mA.
272081-17
AC Inpuis during testing are driven at Vcc-0.5V for a Logic "I"
and 0.45V for a LogiC "0". TIming measurements are made at VIH
min for a Logic "I" and VOL max for a Logic "0".
.
8-78
intet
87C51FA-20/-3
EPROM CHARACTERISTICS
Table 1. EPROM Programming Modes
Mode
Program Code Data
RST
PSEN
ALE!
PROG
EA!
H
L
--u-
P2.6
P2.7
P3.3
P3.6
P3.7
12.75V
L
H
H
H
H
L
L
H
H
Vpp
Verify Code Data
H
L
H
H
L
Program Encryption
Array Address 0-3FH
H
L
--u-
12.75V
L
H
H
L
H
12.75V
H
H
H
H
H
12.75V
H
H
H
L
L
12.75V
H
L
H
H
L
H
L
L
L
L
L
Program Lock
Bits
Bit 1
H
L
Bit 2
H
L
Bit 3
H
L
--u--u--u-
H
L
H
Read Signature Byte
+5V
Vee
87C51FA-20
PG~
DATA
EA/Vpp
ALE/P'ROG t - - -
}
PROGRA~
SIGNALS
PSENi--P2.7i--P2.6t--P3.7t---
CONTROL SIGNALS'
P3.61---P3.3i--RSTt--272081-19
'See Table 1 for proper input on these pins
Figure 10. EPROM Programming Configuration
8·79
int'et
87C51FA-20/-3
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 FA-20 the following sequence must be exercised.
1. Input the valid address on the address lines.
2: Input the appropriate data byte on the data
lines.
PROGRAM VERIFY
Program verify may be done after each byte that is
programmed, or after a block of bytes that is programmed. In either case a complete verify of the
entire array that has been programmed will ensure a
reliable programming of the 87C51 FA-20.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±0.25V.
5. Pulse, ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
ADDRESS
X_l_4_B_'T_S_______________X
DATA
X________________X
X________________X
L
8 BITS
CONTROL
SIGNALS
_
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
7 BITS
12.75V--1
EA/Vpp
5V
TGLGH
ALE!PROG
5 PULSES·
272081-20
'5 pulses for EPROM array, 25 pulses for encryption table and lock bits.
Figure 11. Programming Waveforms
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
Signature Bytes
Location
Contents
Description
30H
31H
60H
89H
58H
FAH
Indicates Intel Devices
Indicates FX-Core Product
Indicates 87C51 FA Device
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 /J-W/cm rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure Characteristics (Window'ed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
Erasure leaves the all EPROM Cells in a 1's state.
8-80
int'eL
87C51 FA-20/-3
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 27°C; Vee = 5V ±20%; vss = OV)
(TA
Symbol
Units
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
rnA
6
MHz
1/TCLCL
Oscillator Frequency
4
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
TGHSL
Vpp Hold after PROG
10
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
JLs
JLs
110
JLs
48TCLCL
JLs
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
P1.0-Pl.7
P2.0-P2.4
VERIFICATION
-----<=:J~~~
ADDRESS
ADDRESS
TAVQV
PORT 0
----~K=~~~
TDVGL
TGHDX
TAVGL
ALE/PROG
------"'1
TGLGH
--A1r--V----I
EX./Vpp
EA/HIGH
P
----dTEHS:
Jf
TELQV
P2.7 _ _.....
L
I
1]10---)...1[__
T_EH_Q_Z_ __
272081-21
"5 pulses for EPROM array, 25 pulses for encryption table and lock bits.
8-81
•
intel~
87C51FA-20/-3
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility
of an unexpected write when Idle is terminated
by reset, the instruction following the one that
invokes Idle should not be one that writes to a
port pin or to external memory.
• The Timer 2 clock out frequency on the
8XC51 FA-20 is determined by the equation in the
8XC51 FX Hardware Description as shown below:
DESIGN CONSIDERATION
• When running out of internal program/data memory, the 87C51 FA-3 can be operated using a
24 MHz clock. If the 87C51 FA-3 is running out of
external program/data memory, the operating
frequency must be between 3.5 MHz to 20 MHz.
The 87C51 FA-3 will not function properly at
24 MHz when running out of external program/
data memory.
• Ambient light is known to affect the internal RAM
contents during operation. If the 87C51 FA-20 application requires the part to be run under ambient lighting, an opaque label should be placed
over the window to exclude light. .
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
Clock-Out Frequency
=
Oscillator Frequency
4 x (65536 - RCAP2H, RCAP2L)
Even though the equation permits a clock-out
frequency of 5 MHz with a 20 MHz oscillator, the
maximum output frequency is 4 MHz. When
operating the device above 16 MHz, RCAP2L
must be limited to FEH.
DATA. SHEET REVISION HISTORY
This data sheet (272081-002) is valid for devices with an "A" at the end of the topside tracking number. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet (272081-002) and the previous version (272081-001):
1. Added 87C51 FA-3 to 20 MHz data sheet.
2. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
TLLlV
TPLIV
TWHQX
TQVWH
From
120
4TCLCL-80
3TCLCL-95
o
TCLCL-50
200
7TCLCL -150
To
125
4TCLCL-75
3TCLCL-90
10
TCLCL-40
280
7TCLCL -70
The following differences exist between revision 1 of the 87C51FA-20 (272081-001) data sheet and the
87C51 FA (270258-005) data sheet.
1. All explanatory wording duplicated in the device user's guide was deleted.
2. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
From
To
4TCLCL-100
4TCLCL-80
TLLlV
3TCLcL -1 05
3TCLCL - 95
TPLIV
TCLCL - 25
TCLCL - 20
TPXIZ
5TCLCL -165
5TCLCL - 95
TRLDV
8TCLCL -150
8TCLCL - 90
TLLDV
9TCLCL -165
9TCLCL - 90
TAVDV
4TCLCL -130
4TCLCL - 90
TAVWL
TCLCL - 50
TCLCL - 35
TQVWX
3. TXHQX in the Serial Port Timing Table changed from (2TCLCL - 117) to (2TCLCL - 50).
4. All references to Program lock Bit and Encryption Array deleted from "Program Verification" section. This
information is available in the hardware description.
8-82
87C51FB/83C51FB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 16 KBYTES INTERNAL PROGRAM MEMORY
sv
87CS1FB/83CS1FB-3.S MHz to 12 MHz, Vee =
± 20%
87CS1FB-1/83CS1FB-1-3.S MHz to 16 MHz, Vee = SV ± 20%
87CS1 FB-L/83CS1 FB-L-3.S MHz to 8 MHz, Vee = 3.3V ± 0.3V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
Low Voltage Operation (-L Only)
Three 16-Bit Timer/Counters
Programmable Clock Out
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer capabilities
Up/Down Timer/Counter
Three Level Program Lock System
16K On-Chip EPROM
32 Programmable I/O Lines
7 Interrupt Sources
Four. Level Interrupt Priority
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
MCS®-S1 Fully Compatible Instruction
Set
Saving Idle and Power Down
• Power
Modes
2S6 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
•
Boolean Processor
ONCE (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16 Kbytes ofthe program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51 FB/83C51 FB is a single-chip control-oriented microcontroller which is fabricated on Intel's
reliable CHMOS III-E technology. Being a member of the MCS-51 family, the 87C51 FB/83C51 FB uses the
same powerful instruction set, has the same architecture, and is pin for pin compatible with the existing
MCS-51 family of products. The 87C51 FB/83C51 FB is an enhanced version of the 87C51 /80C51 BH. It's
added features make it an even more powerful microcontroller for applications that require Pulse Width
Modulation, High Speed I/O, and up/down counting capabilities such as motor control. It also has a more
versatile serial channel that facilitates multi-processor communications.
Applications that require low voltage operation can use the 87C51 FB-L/83C51 FB-L. The 8XC51 FB-L will
operate at 3.3V ± O.3V at a frequency range of 3.5 MHz to 8 MHz.
Throughout this document 8XC51 FB will refer to both the 83C51 FB and the 87C51 FB.
8-83
October 1992
Order Number: 270563-005
87C51 FB/83C51 FB
PO.O-PO.7
--------,
i'SEN
ALE/~
EA/Vpp
RST
270563-1
Figure 1. 8XC51FB Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components and Reliability Handbook, Order Number 210997.
8-84
intel~
87C51 FB/83C51 FB
PACKAGES
Part
Prefix
8XC51FB
87C51FB
8XC51FB
8XC51FB
P
D
N
S
Package Type
40-Pin
40-Pin
44-Pin
44-Pin
Plastic DIP
CERDIP
PLCC
QFP
°ja
45°C/W
45°C/W
46°C/W
96°C/W
°je
16°C/W
15°C/W
16°C/W
24°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
"': "1
INDEX
CORNER
~
c: c: c:
0..
"c:
;;;
0"
>"' >0 0
0..
N
.,; .,; '"
.,;
0..
0..
0..
PLS
PO.4
PL6
PO.S
Pl.,
PO.6
RST
PO.7
IT
P3.0
Reserved·
vee
(T2) PLO
(T2EX) P1.1
PO.O (ADO)
(Ecl) Pl.2
PO.l (AD1)
(CEXO) P1.3
PO.2 (AD2)
(CEX1) Pl.4
PO.3 (AD3)
(CEX2) Pl.S
PO.4 (AD4)
(CEX3) Pl.6
PO.S (ADS)
Reserved·
P3.1
ALE
P3.2
PSEN
P3.3
P2.7
P3.4
P2.6
P3.S
P2.S
,,;
"' ,,;"
0..
(CEX4) Pl.7
PO.6 (AD6)
RESET
PO.7 (AD7)
N
-'
-'
l-
I-
"" ""
X
X
.
"'
"'..,
~
>
0
...
N
'" N
N N N N
0..
.,.
0..
0..
0..
~
0:
270563-3
(RXD) P3.0
EA
(TXD) P3.l
ALE
(INTO) P3.2
PSEN
(INT1) P3.3
P2.7 (A15)
(TO) P3.4
P2.6 (A14)
(T1 ) P3.5
(WR) P3.6
P2.5 (A13)
(Rii) P3.7
P2.3 (All)
XTAL2
P2.2 (Al0)
XTAL1
P2.1
PLCC
INDEX
CORNER \
P1.5
(~
;:3) PO.4
P1.6
2: ~
;:3)
;:[1
;::[0
PO.S
Lt9
Lt8
EA
Lt"T
ALE
(~
RST {~
P3.0
~
PL7
(A9)
P2.0 (AS)
~ ~ ~ ~ ~ U; 0 ~ ..... N ~
~
~
~
~
~
>(1')00000
> ~ ~ ~ ~
-~~! ~~! ~~! ~~! ~~! ~~! ~~! ~~! ~~! ~~! ~~: "
P2.4 (A12)
VSS
0..
5:
Reserved·
P3.1
270563-2
DIP
P3.2
S:~
8XCS1FB
7: !
(}
Lts
(~
P3.4 (§ ~
;:2)
P3.3
P3.5
PO.7
ReservedPSEN
P2.7
Lt4 P2.6
tt3 P2.S
1J!
•
PO.6
;~~ ;~~ :~~ :~~ ;~~ ;~~ ;~~ :~~ :~~ :~~ :~~tJ,
...
N N. "1
~ N0.. N
11.
-
0..
270563-4
QFP
• Do not connect reserved pins.
Figure 2. Pin Connections
8-85
intel~
87C51 FB/83C51 FB
In addition, Port 1 serves the functions of the following special features of the 8XC51 FS·
PIN DESCRIPTIONS
Vee: Supply voltage.
Port Pin
Alternate Function
Vss: Circuit ground.
P1.0
VSS1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
P1.1
T2 (External Count Input to Timer/
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
P1.2
P1.3
NOTE:
This pin is not a substitute for the Vss pin. Connect
Vss and VSS1 with the lowest impedance path possible.
P1.4
P1.5
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
P1.6
P1.7
Port 0 is also the multiplexed low-order address arid
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pull ups when emitting 1's, and can source and
sink several LS TTL inputs.
CEXO (External I/O for Compare/
Capture Module 0)
CEX1 (External I/O for Compare/
Capture Module 1)
. CEX2 (External I/O for Compare/
Capture Module 2)
CEX3 (External I/O for Compare/
Capture Module 3)
CEX4 (External I/O for Compare/
Capture Module 4)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (ilL, on the data sheet) because of the internal pullups.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because· of the internal pullups.
.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pull ups when emitting 1'so During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
8-86
int:et
87C51 FB/83C51 FB
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
EA should be strapped to Vee for internal program
executions.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier. ,
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The Port Pins will be driven to their reset condition when a voltage above VIH1 is applied whether
the oscillator is running or not. An internal pulldown
resistor permits a power-on reset with only a capacitor connected to Vee.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but the minimum and maximum
high and low times specified on the data sheet must
be observed.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FB.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX instruction. Otherwise the
pin is weakly pulled high.
2
~
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
o
XTAL2
Cl
XTAL 1
Vss
270563-5
C1; C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
.
Figure 3. Oscillator Connections
When the 8XC51 FB is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if either of
the Program Lock bits are programmed, EA will be
internally latched on reset.
XTAL 1
270563-6
Figure 4. External Clock Drive Configuration
8-87
infel·
87C51 FB/83C51 FB
IDLE MODE
DESIGN CONSIDERATION
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
• The 8CX51 FB-L will operate at 3.3V ± O.3V at a
frequency range of 3.5 MHz to 8 MHz. Operating
beyond these specifications could cause improper device functionality. (To program the
87C51 FB-L, follow the same procedure as the
87C51FB.)
• The window on the 87C51 FB must be covered by
an ·opaque label. Otherwise, the DC and AC characteristics may not be met, and the device may
functionally be impaired.
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power .
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the 8XC51 FB either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
. ONCE MODE
To properly terminate Power down the reset or externalinterrupt should not be executed before Vee is
restored to its normal operating level. The external
interrupt or· Reset signal must be held active long
enough for the oscillator to restart and stabilize (normally less than 10 ms).
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC51FB without the 8XC51FB having to be removed from the circuit. The ONCE Mode is invoked
by:
With an external interrupt, INTO or INT1 must be enabled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
2) Hold ALE low as RST is deactivated.
1) Pull ALE low while the device is in reset and
PSEN is high;
,
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC51 FB is in this mode, an emulator
or test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
Idle
Internal
1
Idle
External
Power Down
Internal
Power Down
External
0
Mode
PSEN
PORTO
PORT1
PORT2
PORT3
1
Data
Data
Data
Data
1
1
Float
Data
Address
Data
0
0
Data
Data
Data
Data
0
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "Designing with the BOC51 BH."
8-88
intel®
87C51FB/83C51FB
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias .... O°C to + 70°C
Storage Temperature .......... - 6SoC to + 1S0°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. - O.SV to + 6.SV
IOl Per I/O Pin ........................... 1S mA
Power Dissipation .......................... 1.SW
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions:
TA (under Bias) = O°C to +70°C, Vee = SV ±20%, Vss = OV (8XCS1FB-L, Vee = 3.3V ±0.3V)
DC CHARACTERISTICS: (Over Operating Conditions)
All parameter values apply to both SV and 3.3V devices unless otherwise indicated.
Symbol
Parameter
Typ
(Note 4)
Min
Max
Unit
V
Test Conditions
Vil
Input Low Voltage
-0.5
0. 2Vee- 0.1
VIL1
Input Low Voltage EA
0
0.2Vee- 0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2Vee+ 0.9
Vee+ O.S
V
VIHl
Input High Voltage (XTAL 1, RST)
0.7 Vee
Vee+ O.S
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2, and 3)
0.3
V
IOL = 100 p.A (Note 1)
0,45
V
IOl =1.6 mA (Note 1)
1.0
V
IOl = 3.5 mA (Note 1)
IOl = 200 p.A (Note 1)
VOL1
VOH
VOHl
I
Output Low Voltage (Note S)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2, and 3, ALE, PSEN)
Output High Voltage
(Port 0 in External Bus Mode)
0.3
V
0,45
V
IOL = 3.2 mA (Note 1)
1.0
V
IOl = 7.0 mA (Note 1)
V
IOH = -10 p.A
Vee- 0.3
Vee- 0.7
V
IOH = -30 p.A
Vee- 1.5
V
IOH = -60 p.A
Vee- 0.3
V
IOH = -200 p.A
Vee- 0.7
V
IOH = -3.2mA
V
Vee- 1.5
III
Logical 0 Input Current
(Ports 1, 2, and 3)
III
Input leakage Current (Port 0)
III
Logical 1 to 0 Transition Current
(Ports 1, 2, and 3)
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
lee
Power Supply Current:
Active Mode
8XC51 FB-L at 8 MHz
All Others at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
50
IOH = -7.0mA
-50
p.A
VIN = 0,45V
±10
p.A
0,45V < VIN < Vee
-6S0
p.A
VIN = 2V
300
KO
10
pF
@1 MHz, 25°C
(Note 3)
20
5
15
8-89
12
40
10
100
mA
mA
mA
p.A
87C51FB/83C51FB
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOLS of ALE and
Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum VCC for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, 10L must be externally limited as follows:
Maximum 10L per port pin:
10mA
Maximum 10L per B-bit portPort 0:
26 mA
15 mA
Ports 1, 2 and 3:
71 mA
Maximum total 10L for all output pins:
If 10L exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
60mA
SOmA
MAX.
40mA
30mA
A~
20mA
.OmA
....-
OmA
o MHz
~
---=
~
IDLE
--
~
Vee
~
Vee
PO
TYPICA~
MAX.
87C51rs
_
TYPICAL ~
XTAL2
XTAL1
vss
IDLE
8MHz
4MHz
Eli
RST
12MHz
16MHz
270563-7
270563-8
Icc Max at other frequencies is given by:
Active Mode
Icc Max = (Ose Freq x 3) + 4
Idle Mode
ICC Max = (Ose Freq x 0.5) + 4
Where Osc Freq is in MHz, Icc is in rnA.
All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 6. Icc Test Condition, Active Mode
Figure 5_ Icc vs Frequency
Vee
PO
RST
RST
Eli
87C51rs
87C51rs
XTAL2
XTAL1
XTAL2
XTAL1
Vss
Vss
270563-9
270563-10
All other pins disconnected
TCLCH = TCHCL = 5 ns
All other pins disconnected
Figure 8. Icc Test Condition, Power
Down Mode Vcc = 2.0V·to 6.0V
Figure 7. Icc Test Condition Idle Mode
270563-11
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH
8-90
=
TCHCL
=
5 ns
intet
87C51FB/83C51FB
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P:PSEN
Q: Output Data
R: RD Signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
Min
Min
Max
3.5
16
Max
1/TCLCL Oscillator Frequency
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL-40
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
53
TCLCL-30
ns
234
ns
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
53
TCLCL-30
4TCLCL-100
TPLPH
PSEN Pulse Width .
205
3TCLCL-45
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
59
TCLCL-25
TAVIV
Address to Valid Instruction In
312
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
0
ns
ns
3TCLCL-105
145
ns
0
ns
ns
ns
TRLRH
RD Pulse Width
400
6TCLCL-100
TWLWH
WR Pulse Width
400
6TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
107
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
ns
TAVDV
Address to Valid Data In
585
9TCLCL-165
ns
TLLWL
ALE Low to RD or WR Low
200
3TCLCL+50
ns
TAVWL
Address Valid to WR Low
203
4TCLCL-130
ns
TOVWX
Data Valid before WR
33
TCLCL-50
ns
TWHOX
Data Hold after WR
33
TCLCL-50
ns
TOVWH
Data Valid to WR High
433
7TCLCL-150
ns
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
252
0
ns
5TCLCL-165
0
300
3TCLCL-50
0
43
ns
123
TCLCL-40
ns
ns
0
ns
TCLCL+40
ns
intel·
87C51FB/83C51FB
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE'_ _01
PSEN _ _.I
PORT 0
---
PORT 2 _ _ _ _
,~
___
~~~
___
A8-A15 _ __
-J~~_~~~
270563-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
'I
t------TLLDV
---0-1---- TRLRH -----+/
PORTO
INSTR. IN
P2.0-P2.7 OR A8-A15 FROM DPH
PORT2
A8-A15 FROM PCH
270563-13
EXTERNAL DATA MEMORY WRITE CYCLE
I
ALE
~TWHLH
-i-TLHLL'-:
\.
~
1
..-J-TLLWL
- TAVLL
-TLLAX-
,
TWLWH
j
~
.....
t-TWHQX
TQVWH
PORTO
PORT 2
~
--,
-
FROI.r~i~~
OPL
DATA OUT
K XAO-A7 FROM PCL
INSTR. IN
TAVWL
P2.0-P2.7 OR A8-A15 FROM DPH
X
A8-A15 FROM PCH
270563-14
8-92
int:eL
87C51FB/83C51FB
SERIAL PORT TIMING· SHIFT REGISTER MODE
Test Conditions:
Symbol
TA
= O°C to + 70°C; Vee = 5V ±20%; vss = OV; Load Capacitance = 80 pF
12 MHz Oscillator
Parameter
Min
Variable Oscillator
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1
12TCLCL
/-Ls
TOVXH
Output Data Setup to Clock
Rising Edge
700
1OTCLCL -133
ns
TXHOX
Output Data Hold after
Clock Rising Edge
50
2TCLCL -117
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
1OTCLCL - 133
700
SHIFT REGISTER MODE TIMING WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
8XC51FB
8XC51FB-1
3.5
3.5
12
16
MHz
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270563-16
8-93
ns
intel·
87C51FB/83C51FB
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
V-
VCC-O.5~O.2VCC+O.9
..,
O.45V~_O_.2_VC::.:C:....-_O_.l_ _ _~~
TIMING REFERENCE
POINTS
270563-18
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH = ± 20 rnA. (·L, IOl/lOH = ± 10 rnA.)
270563-17
AC Inputs during testing are driven at Vee-0.5V for a Logic "'I"
and 0.45V for a Logic "'0". Timing measurements are made at VIH
min for a Logic "'1" and Vil max for a Logic "'0"'.
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig~ntil just before ALEI
PROG is to be pulsed. The EAlVpp is rais~d to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, respectively for AO-A 13.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
• Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
• Programming specifications for the 87C51 FB-L
are the same as the standard 87C51 FB.
Table 2. EPROM Programming Modes
Mode
RST
PSEN
ALE!
PROG
EAI
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
L...r
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
L...r
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
L...r
12.75V
H
H
H
H
H
Bit2
H
L
L...r
12.75V
H
H
H
L
L
Bit3
H
L
L...r
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Read Signature Byte
8-94
int:eL
87C51 FB/83C51 FB
+5V
vee
B7C51 Fa
40
31
[A/V,p
30
ALE/PROG
-PSEN
}
PROGRAM
SIGNALS
29
2B
P2.7
27
P2.6
lB
XTAL2
17
P3.7
CONTROL SIGNALS'
16
P3.6.
13
19
P3.3
XTAL 1
20
RST
Vss
270563-19
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
PROGRAM VERIFY
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 FB the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
Verification may be done after programming either
one byte or a block of bytes. A complete verify of the
array will ensure reliable programming of the
87C51FB.
The lock bits cannot be directly verified. They are
verified by observing that their features are enabled.
Refer to the EPROM Program Lock section in this
data sheet for a description of the lock bit features.
ROM and EPROM Lock System
The 87C51 FB and the 83C51 FB program lock systems, when programmed, protect the onboard program against software piracy.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
ADDRESS
X_ _ _ _X
16 BITS
X________________X
X _______________X
DATA
B BITS
~
7 BITS
CONTROL
SIGNALS
12.75V
[A/Vpp
5V
J
TGHGL
TGLGH
--/1-
'--
ALE!PRoG
270563-20
5 Pulses
Figure 11_
Pr~gramming
8-95
Signal's Waveforms
infel .
87C51 FB/83C51 FB
The B3C51 FB has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
3. If program protection is desired, the user submits
the encryption table with their code, and both the
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the
user must submit an encryption table.
Program Lock Bits
The 87C51FB has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data.
Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
The B7C51 FB has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, a" locations are user-programmable. See Table 3.
Reading the Signature Bytes
The 8XC51 FB has 3 signature bytes in locations
30H, 31 H, and 60H. To read these bytes follow the
procedure for EPROM verify, but activate the control
lines provided in Table 2 for Read Signature Byte.
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (a" 1's). Every
time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (a" 1's), will return the code in it's
original, unmodified form. For programming the Encryption Array, refer to Table 2 (Programming the
EPROM).
Contents
Location
87C51FB
83C51FB
89H
89H
30H
When using the encryption array, one important factor needs to be considered. If a code byte has the
value OFFH, verification of the byte will produce the
encryption byte value. If a large block (> 64 bytes)
of code is left unprogrammed, a verification routine
will display the contents of the encryption array. For
this reason it is strongly recommended that a" unused code bytes be programmed with some value
other than OFFH, and not a" of them the same value. This practice will ensure the maximum possible
program protection for this feature.
31H
58H
58H
60H
FBH
FBHI7BH
Erasure Characteristics (Windowed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in room-
Table 3 Program Lock Bits and the Features
Program Lock Bits
Protection Type '
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled:
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
Any other combination of the lock bits
IS
not defined.
8-96
intel"
87C51 FB/83C51 FB
level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
ed dose of at least 15 W-sec/ cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 /1-W/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
Erasure leaves all the EPROM Cells in a 1's state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 2rc; Vee = 5V ±20%; Vss = OV)
Symbol
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frequency
4
Units
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
/1-s
TGHSL
Vpp Hold after PROG
10
/1-s
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
110
/1-s
48TCLCL
48TCLCL
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
48TCLCL
/1-s
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
VERIFICATION
AO-A15----------(:::=A~D~D~RE~S~S~~::::)_----------_1==::~A~DD~R~E~SS~~~--------TAVOV
DATA OUT
DO-D7
TGHDX
TDVGL
TGHAX
TAVGL
ALE/PROG
TSHGLr---TGLGH
EA/Vpp
CONTROL
Vee
1
c,-,,","
EA/HIGH
Vpp
TELOV-*_____
TEHOZ
SIGNALS
270563-21
8-97
87C51 FB/83C51 FB
DATA SHEET REVISION HISTORY
This data sheet (270563-005) is valid for devices with an "A" at the end of the topside tracking number. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet (270563-005) and the previous version (270563-004):
1. Added 3.3V device t6 data sheet.
2. Data sheet title was changed from:
87C51 FB/83C51 FB CHMOS Single-Chip 8-Bit Microcontroller 16 Kbytes User Programmable EPROM
to:
87C51 FB/83C51 FB CHMOS Single-Chip 8-Bit Microcontroller with 16 Kbytes Internal Program Memory
3. Data sheet status changed from "Preliminary" to "Production".
4. Added process information after block diagram.
5. 0ja and 0je information added to Packages table.
6. Signature byte location 60H, 83C51 FB changed to FBHI7BH.
The following differences exist between the -004 and -003 versions of this data sheet.
1. Name changed from 87C51 FB to 87C51 FB/83C51 FB.
2. Data sheet status changed from "ADVANCE" to "PRELIMINARY".'
3. Device -2 version deleted.
4. 4 Level Interrupt Priority added.
5. QFP package offering added.
6. VSS1 pin description added.
7. Asynchronous Reset added.
8. ALE disable added.
9. RRST spec changed from 40 KO min, 225 KO max to 50 KO min, 300 KO max.
10. Note 1 reworded (ALE noise pulses).
11. Control line (P3.3) added to Table 2 and Figure 10.
12. Programming Algorithm and verification paragraphs reworded to describe programming changes.
13. Figure 11 changed to show 5 programming pulses rather than 25.
14. Figure 12 deleted (Program Verification).
15. Program Memory Lock feature changes:
- Third lock bit added
- Encryption array enhanced to 64 bytes
16. Third signature byte added; location and definition included.
17. Ipp programming spec changed from 50 mA to 75 mAo
The following are the key differences between the -003 and -002 version of the 87C51 FB data sheet:
1. Word'''Maximum'' was deleted from the IOL line in the Absolute Maximum Ratings.
2. Parameter VIL 1 was deleted from the DC Characteristics.
3. Note 4, "Care must be taken not to exceed the maximum allowable power dissipation" was deleted from
DC Characteristics and from the list of notes and notes were resequenced.
4. Parameter IU1 was deleted from the DC Characteristics.
5. Figure 5 was replaced to show correct ICC curves.
6. External clock capacitive loading note was added.
8-98
87C51FB/83C51FB
The following are the differences between the -002 and -001 version of the 87C51 FB data sheet:
1. Title changed to include -1 and -2 version of the device.
2. PLCC pin connection diagram was added.
3. Package table was added.
4. Exit from power down mode was clarified.
5. Maximum IOL per 1/0 pin was added to the Absolute Maximum Ratings.
6. Note 6 was added to explain the maximum safe current specification.
7. Typical values for Icc table were added.
8. Note 5 was added to explain the test conditions for typical values.
9. Timing specifications improved for:
TLLAX changed from TCLCL - 35 to TCLCL - 30
TLLPL changed from TCLCL - 40 to TCLCL - 30
TRHDZ changed from TCLCL - 70 to TCLCL - 60
TaVWX changed from TCLCL - 60 to TCLCL - 50
TaVWH was added.
10. Data sheet revision summary was added.
8-99
87C51 FB-20/-3
83C51 FB-20/-3
COMMERCIAL/EXPRESS
20 MHz MICROCONTROLLER
87C51 FB-20/83C51 FB-20-3.5 MHz to 20 MHz, Vee = 5V ± 20%
MHz Internal Operation, Vee = 5V ±20%
87C51FB-3/83C51FB~3-24
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
24 MHz Internal Operation (-3 only)
Three 16-Bit Timer/Counters
Programmable Clock Out
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer Capabilities
Up/Down Timer/Counter
Three Level Program Lock System
16K On-Chip EPROM
256 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
Programmable I/O Lines
• 732Interrupt
• Four Level Sources
Interrupt Priority
• Programmable
Channel with:
• - Framing· ErrorSerial
Detection
- Automatic Address Recognition
•
TTL and CMOS Compatible Logic
Levels
External Program Memory Space
• 64K
64K External Data Memory Space
•
•
•
•
MCS®-51 Fully Compatible Instruction
Set
Power Saving Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16 Kbytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontrolier has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 8XC51 FB-20/-3 is a single-chip control-oriented microcontrolier which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 8XC51 FB-20/-3 uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 8XC51 FB-20/-3 is an enhanced version of the 87C51 /80C51 BH. It's added features make it an
even more powerful microcontrolier for applications that require Pulse Width Modulation, High Speed I/O and
up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates
multi-processor communications.
The 87C51 FB-3/83C51 FB-3 has the same 3.5 to 20 MHztrequency range asthe 87C51 FB-20/83C51 FB-20
when operating out of external program/data memory. When running out of internal program/data memory,
the 87C51 FB-3/83C51 FB-3 can operate up to 24 MHz.
Throughout this document 8XC51 FB-20 will refer to the 83C51 FB-20, 87C51 FB-20, 83C51 FB-3 and the
87C51FB-3.
8-100
October 1992
Order Number: 272080-002
int'eL
87C51FB-20/-3
83C51FB-20/-3
PO.O - PO.7
PSEN
ALWRoG
EA/VPP
RST
TIMING
AND
CONTROL
272080-1
Figure 1. 8XC51FB-20 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components and Reliability Handbook, Order Number 210997.
8-101
intel·
87C51 FB-20/-3
83C51 FB-20/-3
PACKAGES
Part
Prefix
Package Type
8XC51FB-20
87C51FB-20
8XC51FB-20
8XC51FB-20
P
D
N
S
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-PinQFP
8Ja
45°C/W
45°C/W
46°C/W
96°C/W
8Jc
16°C/W
15°C/W
16°C/W
24°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
PI.S
PO.'
PI.6
PO.S
PI.'
PO.6
RST
PD.7
P3.0
R...~·
vee
(T2) PI.O
(T2EX) PI. I
PO.O (ADO)
(ECI) PI.2
PO.I (ADI)
(CEXO) PI.3
PO.2 (AD2)
(CEXI) PI.4
PO.3 (AD3)
(CEX2) PI.S
PO.4 (AD4)
(CEX3) PI.6
PO.S (ADS)
(CEX4) PI.'
PO.6 (AD6)
RESET
PO.' (AD')
(RXD) P3.0
EA
(TXD) P3.1
ALE/PROO
P3.1
ALE/PiiOO
P3.2
P3.3
P2.7
P3.4
P2.6
P3.S
P2.S
272080-3
PLCC
(iNTO) P3.2
(iiffi) P3.3
P2.' (AIS)
INDEX
"'; "! "! ":
(TO) P3.4
P2.6 (AI4)
CORNER\
ii:
PSEN
(TI) P3.S
P2.S (AI3)
(ViR) P3.6
(iffi) P3.'
P2.4 (A 12)
PI.S (~
P2.3 (All)
PI.6 (~
XTAL2
P2.2 (AIO)
Pl., (~
XTALI
P2 .. 1 (A9)
RST {~
Vss
P2.0 (AS)
P3.0
~
Reserved. (~
0
-
0
_
..
'"
a: a: a: a: >Y),.}f f f f
.~~! ~~! ~~: ~~ ~~: ~~! ~~! ~~: ~;: ~~:~;:
5:
272080-2
P3.1
DIP
P3.2
P3.3
PM
8XCSIFB-20
(~
s::
s: ~
PO."
po.s
PO.6
PO.7
EA
R...rvod·
ALE/PROO
i(6 PsEN
i2}
(g!
P3.S 1J
i3l
ift
i3J
i3}
i2j
i2J
itT
P2.'
i(4
P2.6
~._.
roo ,roo . . . . ,_.,_. roo 'roo ..... ,_ .... J(3
_
_
_
_
_
_
_
_
N
P2.S
.INIIf')II ....
llll)llfDllr--.IICOIIg)IIOII-NIIN~-'
~~
272080-4
QFP
·00 not connect reserved pins
Figure 2. Pin Connections
8-102
intel"
87C51FB-20/-3
83C51FB-20/-3
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Circuit ground.
VSS1
Secondary ground (connection not necessary). Provided to reduce ground bounce and
improve power supply bypassing.
NOTE:
This pin is not a substitute for the Vss pin. Connect Vss and VSS1 with the lowest
impedance path possible.
PortO
8-Bit, open drain, bidirectional I/O port. These pins are shared with the multiplexed
address/data bus which has strong internal pullups. Port 0 also receives the code bytes
during EPROM programming, and outputs the code bytes during verification. When used as
an I/O port, pullups to Vee may be needed ..
Port 1
8-Bit bidirectional I/O port. All of the port 1 pins are shared with other functions in the
8XC51 FB-20. Port 1 is also used as the low-order address byte input during EPROM
programming.
Port 2
8-Bit bidirectional I/O port. Port 2 also emits the high-order address byte during accesses
to 16-bit external memory locations. Some of the Port 2 pins are also used as address bits
for EPROM programming.
Port 3
8-Bit bidirectional I/O port. All of the port 3 pins are shared with other functions in the
8XC51 FB-20. Two of the pins are used as control lines (RO, WR) for accessing external
RAM.
RESET
Reset input to the chip. A high input for a minimum of two machine cycles with the oscillator
running resets the device. The port pins will be reset when a voltage above VIH is applied
whether the oscillator is running or not. RST has an internal pulldown.
ALE/PROG
Address Latch Enable. Provides a signal to demultiplex the address from the address/data
bus. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency.
Note, however, that one ALE pulse is skipped during each access to external data memory.
If desired, ALE can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode. This pin is also the program pulse input during EPROM programming.
PSEN
Program Store Enable. Acts as read strobe for external program memory fetches.
EAlVpp
External Access Enable. EA must be strapped to VSS in order to enable the device to fetch
code from external program memory locations OOOOH to OFFFFH. EA should be strapped
to Vee for internal program executions. If any of the lock bits are programmed, EA will be
internally latched on reset. This pin also receives the programming supply voltage (Vpp)
during EPROM programming.
XTAL1
Input to the inverting oscillator amplifier.
XTAL2
Output from the inverting oscillator amplifier.
8-103
intel®
87CS1FB-20/-3
83CS1FB-20/-3
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature
Under Bias .................. - 40°C to + 85°C
Storage Temperature .......... -65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to + 6.5V
IOL Per I/O Pin ........................... 15 mA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
-40
+70
+85
°C
°C
Vee
Supply Voltage
4.0
6.0
V
Fose
Oscillator Frequency
3.5
20
MHz
DC CHARACTERISTICS
Symbol
(Over Operating Conditions)
Parameter
Max
Unit
-0.5
0.2Vee- 0.1
V
'VIL1
Input Low Voltage EA
0
0.2Vee- 0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2 Vee+0.9
Vee + 0.5
V
0.7 Vee
Vee+ 0.5
V
0.3
V
0.45
V
1.0
V
0.3
V
VIL
Input Low Voltage
Typ
(Note 4)
Min
VIH1
Input High Voltage (XT AL 1, RST)
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
VOL1
VOH
VOH1
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2 and 3)
Output High Voltage
(Port 0 in External Bus Mode,
ALE, PSEN)
0.45
V
1.0
V
Vee- 0.3
V
Vee- 0.7
V
Vee- 1.5
V
Vee- 0.3
V
Vee- 0.7
V
Vee- 1.5
V
Test Conditions
= 100 /kA (Note 1)
IOL = 1.6 mA (Note 1)
IOL = 3.5 mA (Note 1)
IOL = 200 /kA (Note 1)
IOL = 3.2 mA (Note 1)
IOL = 7.0 mA (Note 1)
IOH = -10/kA
IOH = -30/kA
IOH = -60/kA
IOH = - 200 /kA
IOH = -3.2 mA
IOH = -7.0 mA
VIN = 0.45V
IOL
IlL
Logical 0 Input Current
(Ports 1, 2 and 3)
-50
/k A
III
Input Leakage Current (Port 0)
±10
/k A 0.45V
8-104
< VIN < Vee
inteL
87C51 FB-20/-3 83C51 FB-20/-3
DC CHARACTERISTICS
Symbol
(Over Operating Conditions) (Continued)
Parameter
Typ
(Note 4)
Min
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Commercial
Express
ITl
RRST
RST Pulldown Resistor
Cia
Pin Capacitance
Icc
Power Supply Current:
Running at ,20 MHz (Figure 5)
Idle Mode at 20 MHz (Figure 5)
Power Down Mode
50
Max
Unit
Test Conditions
-650
-750
J1-A
J1-A
K!1
VIN = 2V
300
10
pF
@1 MHz, 25°C
(Note 3)
32
7
15
64
14
100
mA
mA
J1-A
NOTES:
1. Capacitive loading on Ports a and 2 may cause noise pulses above OAV to be superimposed on the VOLs of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins
change from 1 to" O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS·level input logic.
2. Capacitive loading on Ports a and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vcc specification when the
address lines are stabilizing.
3. See Figures 4-7 for test conditions. Minimum Vcc for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, 10L must be ex1ernally limited as follows:
Maximum 10L per port pin:
10mA
Maximum 10L per B-bit portPort 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total 10L for all output pins:
71 mA
If 10L exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
70mA
,/
60mA
./
SOmA
.OmA
~
/
V
..v,\~~
30mA
/
lOrnA
.,/
---:::::
.........
~.)
\"t
~~
jl.C1
V ___
20mA
----
IOLE. MAX.
---
1210lHz
CLOCK
SIGNAL
EA
XTAL2
XTALI
Vss
272080-8
All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 4. Icc Test Condition,
Active Mode
\OLE TYPICAL (.4)
8WHz
PO
OST
OmA
oMHz
vee
vee
16WHz
20 MHz
272080-7
ICC Max at other frequencies is given by:
Active Mode
Icc Max ~ (Osc Freq x 3) + 4
Idle Mode
Icc Max ~ (Osc Freq x 0.5) + 4
Where Osc Freq is in MHz, Icc is in rnA.
Figure 3. Icc vs Frequency
8-105
int:et
87C51 FB-20/-3
83C51 FB-20/-3
05T
05T
87C51FB-20
XTAL2
XTAl2
XTAL1
XTAL 1
VSS
Vss
272080-10
272080-9
All other pins disconnected
All other pins disconnected
TCLCH ~ TCHCL ~ 5 ns
Figure 6. Icc Test Condition, Power
Down Mode Vec = 2.0V to 6.0V
Figure 5. Icc Test Condition Idle Mode
27201\0-11
Figure 7. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH
= TCHCL = 5 ns
L: Logic level LOW, or ALE
P:PSEN
Q: Output Data
R: RD signal
T:Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
For example,
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
AC CHARACTERISTICS
PSEN
=
(Over Operating Conditions, Load Capacitance for Port 0, ALE/PROGand
100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Min
Max
1/TCLCL Oscillator Frequency
Variable Oscillator
Min
Max,
3.5
20
Units
MHz
TLHLL
ALE Pulse Width
60
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
10
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
20
TCLCL-30
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
20
TCLCL-30
TPLPH
PSEN Pulse Width
105
3TCLCL-45
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
8·106
ns
0
30
ns
ns
3TCLCL-90
60
0
ns
4TCLCL-75
125
ns
ns
TCLCL-20
ns
infel~
87C51FB-20/-3
83C51FB-20/-3
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
.'
(Continued)
20 MHz Oscillator
Min
Max
Variable Oscillator
Min
Units
Max
145
5TCLCL-105
ns
10
10
ns
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
TRLRH
RD Pulse Width
200
6TCLCL-100
TWLWH
WR Pulse Width
200
6TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
40
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
310
8TCLCL-90
ns
TAVDV
Address to Valid Data In
360
9TCLCL-90
ns
TLLWL
ALE Low to RD or WR Low
100
3TCLCL+50
ns
TAVWL
Address Valid to WR Low
110
4TCLCL-90
TOVWX
Data Valid before WR
15
TCLCL-35
ns
TWHOX
Data Hold after WR'
10
TCLCL-40
' ns
TOVWH
Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
ns
ns
5TCLCL-95
155
200
3TCLCL-50
ns
7TCLCL-70
280
0
90
10
ns
ns
0
0
TCLCL-40
ns
0
ns
TCLCL+40
ns
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _.I
PSEN _ _.I
PORT 0 _ _J
PORT 2
AS - A15
-----'"
272080-12
8-107
intel .
87CS1FB-20/-3 83CS1FB-20/-3
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
~----TLLDV
"'
--~-- TRLRH
---I
RD
PORTO
PORT 2
INSTR. IN
__
-"~
_____________________________ '_______________
P2.0-P2.7 OR AB-A15 fROt.! DPH
AB-A15 fROt.! PCH
2720BO-13
EXTERNAL DATA MEMORY WRITE CYCLE
I
ALE
-1.-TLHLL-
~
PTWHLH
\.
PORTO
PORT 2
:::>-:::::>
~TLLWL
TAVLL
I-
,
J
~TLLAX- ~
TQVWH
fROM
~
TWLWH
'jg-trJ OPL
i+-TWHQX
K
DATA OUT
AO-A7 fROt.! PCL
INSTR. IN
TAVWL
P2.0-P2.7 OR AB-A 15 fROt.! DPH
AB-AI5 fROM PCH
272~80-14
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions:
Symbol
Over Operating Conditions; Load Capacitance
Parameter
20 MHz Oscillator
Min
Max
= 80 pF
Variable Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
600
12TCLCL
ns
TQVXH
Output Data Setup to Clock
Rising Edge
367
1OTCLCL -133
ns
TXHQX
Output Data Hold after
Clock Rising Edge
2TCLCL-50
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
,
. 50
0
367
8-108
1OTCLCL - 133
ns
intel~
87C51FB-20/-3
83C51FB-20/-3
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
o
2
5
4
3
7
6
ALE
CLOCK
X
OUTPUT DATA
~~-J
I
WRITE TO SBUF
INPUT DATA
3
X
4
X
5
X
6
X
...
-----""Y~~
I
7
+
SET TI
~ ':":'~-~~.,..._~~-~~v-~~~,.....~~v-~~~
I
+
SET RI
CLEAR RI
272080-15
C2
I-~P---I XTAL 2
o
1---4~--I XTAL 1
.--------1 VSS
N/c
XTAL 2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
272080-5
C1. C2 ~ 30 pF ± 10 pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
272080-6
Figure 8. Oscillator Connections
Figure 9. External Clock Drive Configuration
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TClCl
Oscillator Frequency
3.5
20
MHz
TCHCX
High Time
TClCX
low Time
20
20
TClCH
Rise Time
TCHCl
Fall Time
ns
ns
20
20
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272080-16
8·109
intet
87C51 FB-20/-3
AC TESTING INPUT, OUTPUT WAVEFORMS
83C51 FB-20/-3
FLOAT WAVEFORMS
V-
VCC - 0 . 5 - y - 0.2 Vcc+ 0.9
0.45 v-A_0_.2_V...;;C.;;.C_-_0._l_ _ _
TIMING REFERENCE
POINTS
~~
272080-18
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
'OL/loH ;, ±20 rnA.
272080-17
AC Inputs during testing are driven at Vee-0.5V for a Logic "1"
and OA5V for a Logic "0". Timing measurements are made at V,H
min for a Logic "1" and V,L max for a Logic "0".
PROGRAMMING THE EPROM
Table 1. EPROM Programming Modes
Mode
RST
PSEN
ALEI
PROG
EAt
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
l..J
12.75V
L
H
H
H
H
H
H
L
L
L
H
H
Program Code Data
H
L
Verify Code Data
H
'L
Program Encryption
Array Address 0-3FH
H
L
l..J
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
l..J
12.75V
H
H
H
H
H
Bit 2
H
L
l..J
12.75V
H
H
H
L
L
Bit 3
H
L
l..J
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Read Signature Byte
+5V
87CS t F8-20
AO-A7
A8-A13
vee
PO
P2.0P2.S
PGM DATA
"EA/vpp
ALE/PROG 1 - - - -
}
PROGRAM
SIGNALS
PSEN
P2.7
P2.6
P3.7
CONTROL SIGNALS'
P3.6
P3.3
RST
272080-19
'See Table 1 for proper input on these pins
Figure 10. Programming the EPROM
8·110
87C51FB-20/-3
ADDRESS
DATA
CONTROL
SIGNALS
X
X
X
_
12.75V~
EA/Vpp
5V
83C51FB-20/-3
X
14 BITS
X
X
8 BITS
7 BITS
'--
TGLGH
ALE/PROG
5 Pulses·
272080-20
*5-pulses for the EPROM array, 25 pulses for the Encryption Table and Lock Bits.
Figure 11. Programming Waveforms
fluorescent. lighting have wavelengths in this range,
exposure to these 'light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
Signature Bytes
Location Contents
30H
31H
60H
60H
89H
58H
FBH
7BH
Description
Indicates Intel Device
Indicates FX-Core Product
Indicates 87C51 FB-20 Device
Indicates 83C51 FB-20 Device
Erasure Characteristics (Windowed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
8-111
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p,W/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
87C51 FB-20/-3
83C51 FB-20/-3
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 27°C; Vee = 5V ±20%; vss = OV)
(TA
Symbol
Parameter'
Min
Max
Vpp
Programming Supply. Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frequency
4
TAVGL
Address Setup to PROG Low
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
TGHSL
Vpp Hold after PROG
10
TGLGH
PROGWidth
90
TAVaV
Address to Data Valid
48TCLCL
TELaV
ENABLE Low to Data Valid
48TCLCL
TEHaZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
Units
48TCLCL
fLs·
fLs
110
fLs
48TCLCL
fLs
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
P1.0-P1.7
P2.0-P2.5
VERIFICATION
-----{=:JA~D~DR~ES~S~
ADDRESS
TAVQV
DATA OUT
PO
TDVGL
ALE/PROG
TGHDX
g
TSHGL
TGLGH
EA/Vpp
CONTROL
Vee
,~
EA/HIGH
,,~"
TELQV
L
I
1---1,....-TE_HQ_Z---
SIGNALS
272080-21
·5 pulses for the EPROM array, 25 pulses for the Encryption Table and Lock Bits.
8-112
intel·
87C51 FB-20/-3
83C51 FB-20/-3
DESIGN CONSIDERATIONS
• When running out of internal program/data memory, the 87C51 FB-3/83C51 FB-3 can be operated
using a 24 MHz clock. If the 87C51 FB3/83C51 FB-3 is running out of external program/
data memory, the operating frequency must be
between 13.5 to 20 MHz. The 87C51 FB3/83C51 FB-3 will not function properly at 24 MHz
when running out of e)(ternal program/data memory.
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle
should not be one that writes to a port pin or to
external memory.
Timer 2 Programmable Clock Out
• The window on the 87C51 FB-20 must be covered
by an opaque label. Otherwise, the DC and AC
characteristics may not be met, and the device
may functionally be impaired.
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
• The Timer 2 clock out frequency on the
8XC51 FB-20 is determined by the equation in the
8XC51 FX Hardware Description as shown below.
Oscillator Frequency
Clock·out Frequency ~ 4 X (65536 - RCAP2H, RCAP2L)
Even though the equation permits a maximum
clock-out frequency of 5 MHz using a 20 MHz
oscillator, the maximum output frequency is
4 MHz. When operating the part above 16 MHz,
RCAP2L must be limited to a maximum value of
FEH.
DATA SHEET REVISION HISTORY
This data sheet (272080-002) is valid for devices with an "A" at the end of the topside tracking number. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet (272080-002) and the previous version (272080-001):
1. Added 87C51 FB-3/83C51 FB-3 to 20 MHz data sheet.
2. Variable Oscillator equations in External Memory Characteristics Table changed as follows:
From
To
TLLlV
1~
1~
4TCLCL - 80
4TCLCL - 75
3TCLCL - 95
3TCLCL - 90
TPLIV
o
10
TWHOX
TCLCL - 50
TCLCL - 40
200
280
TOVWH
7TCLCL -150
7TCLCL - 70
The following differences exist between revision 1 of the 87C51 FB-20/83C51 FB-20 (272080-001) data sheet
and the 87C51 FB/83C51 FB (270563-004) data sheet.
1. All explanatory wording duplicated in the device user's guide was deleted.
2. Pins labeled "NC" changed to "Reserved" in Figure 2.
3. Timer 2 Programmable Clock Out paragraph added.
4. RRST specification in DC Characteristics Table changed from 40 K!l min, 225 K!l max to 50 K!l min,
300 K!l max.
8-113
intel@
87C51FB-20/-3
83C51FB-20/-3
5. 20 MHz extension added to Figure 3.
6. Variable Oscillator equations in External Memory Characteristics Table changed as follows~
From
To
TLLlV
4TCLCL - 100
4TCLCL - 80
TPLIV
3TCLCL - 105
3TCLCL - 95
TPXIZ
TCLCL - 25
TCLCL - 20
TRLDV
5TCLCL - 165
5TCLCL - 95
TLLDV
8TCLCL - 150
8TCLCL - 90
TAVDV
9TCLCL - 165
9TCLCL - 90
TAVWL
4TCLCL - 130
4TCLCL - 90
TQVWX
TCLCL - 50
TCLCL - 35
7. TXHQX in the Serial Port Timing Table changed from (2TCLCL - 117) to (2TCLCL - 50).
8-114
87C51 FC/83C51 Fe
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 32 KBYTES INTERNAL PROGRAM MEMORY
87C51FC/83C51 FC-3.5 MHz to 12 MHz, Vee = 5V ±20%
87C51 FC-%3C51 FC-1-3.5 MHz to 16 MHz, Vee = 5V ±20%
87C51 FC-L/83C51 FC-L-3.5 MHz to 8 MHz, Vee = 3.3V ± O.3V
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
Low Voltage Operation (-L only)
Three 16-Bit Timer/Counters
Programmable Clock Out
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer capabilities
Up/Down Timer/Counter
Three Level Program Lock System
32K On-Chip EPROM
256 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
•
•
•
•
•
•
•
•
•
•
32 Programmable I/O Lines
7 Interrupt Sources
Four Level Interrupt Priority
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
MCS®-51 Fully Compatible Instruction
Set
Power Saving Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on·chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition itcan address up to 64 Kbytes of
external data memory.
The Intel 87C51 FC/83C51 FC is a· single-chip control-oriented microcontroller which is fabricated on Intel's
reliable CHMOS III-E technology. Being a member of the MCS-51 family, the 87C51 FC/83C51 FC uses the
same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing
MCS-51 family of products. The 87C51 FC/83C51 FC is an enhanced version of the 87C51 /BOC51 BH. It's
added features make it an even more powerful microcontroller for applications that require Pulse Width
Modulation, High Speed I/O and up/down counting capabilities such as motor control. It also has a more
versatile serial channel that facilitates multi-processor communications.
Applications that require low voltage can use the 87C51 FC-L/B3C51 FC-L. The 8XC51 FC-L will operate at
3.3V ± O.3V at a frequency range of 3.5 MHz to 8 MHz.
Throughout this document 8XC51 FC will refer to both the B3C51 FC and the 87C51 FC.
8-115
October 1992
Order Number: 270789-004
inteL
87C51FC/83C51FC
P2.0-P2.7
----------,
PSEN
ALE/i'liOG
£A/vpp
RST
z
TIMING ~~
AND
g~LA----~--~~---------L~--~~--~L-------~
~
CONTROL ~ 81\r------"A:-------------,.-r---------r.-------:7O::-----,;~
"''''
~
P3.0- P3.7
270789-1
Figure 1. 8XC51FC Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III·E process. Additional process and reliability information is available in Intel's Components and Reliability Handbook, Order Number 210997.
8-116
int:et
87C51 FC/83C51 FC
PACKAGES
Part
Prefix
8XC51FC
87C51FC
8XC51FC
8XC51FC
P
D
N
S
Package Type
40-Pin
40-Pin
44-Pin
44-Pin
°ja
45°C/W
36°C/W
46°C/W
8rC/W
Plastic DIP
CERDIP
PLCC
QFP
°je
16°C/W
13°C/W
16°C/W
18°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
(TZ)
P1.0
Vee
(T2EX)
PI. 1
PO.O (ADO)
INDEX
CORNER
(Eel) P1.Z
PO.l (AD1)
(eEXO) P1.3
PO.2 (ADZ)
(eEX 1) P 1.4
PO.3 (AD3)
P1.S
(eEXZ) P1.S
PO.4 (AD4)
P1.6
PO.S
(eEX3) P1.S
PO.S (ADS)
P1.7
PO.6
(eEX4) P1.7
PO.S (ADS)
RST
PO.7
RESET
PO.7 (AD7)
P3.0
PO."
(RXD)
P3.0
fi
(TXD)
P3.1
ALE
P3.1
ALE
(INTO)
P3.2
PSEN
P3.Z
PSEN
(iNTi)
P3.3
PZ.7
(A1S)
P3.3
P2.7
(TO)
P3.4
P2.6
(A 14)
P3.4
P2.S
(Tl) P3.S
P2.S
(A 13)
P3.S
P2.5
(WR)
(Ro)
P3.S
P2.4
(A 12)
RESERVED'
P3.7
PZ.3
(A 11),
XTAL2
PZ,Z
(Al0)
XTAL1
PZ.l
(AS)
PZ.O
(A8)
Vss
RESERVED'
270789-22
270789-21
PLCC
DIP
INDEX
CORNER
\~~"':~"'~N:".,....,,:0:,,,=V>_L>
0_
> > ......
~
~
~
~
~
.....
~...."1"
~
~
(/)UOOOO
~
~
.1:11~11~11:;11~11~11~11:;;11~11~11~1
~~~~~~~_.~~L~L~L~L_IL~L~
P1.5
(~
t3)
P1.S
2: ;
~3) PO.S
P1.7
3: ~
;:f1
PO.S
(~
;:[0
PO.7
5: l
(~
;:2) fi
;:2) RESERVED'
;:[7 ALE
RST
P3.0
RESERVED·
P3.1
P3.2
P3.3
P3.4
P3.S
7: ~
8XCSl Fe
PO.4
(;
L~6
PSEN
(!
12!
1J!
;:2.:5
P2.7
~t4
P2.S
;:~) P2.S
270789-23
QFP
• Do not connect Reserved pins.
Figure 2. Pin Connections
8-117
int:eL
87C51FC/83C51FC
In addition, Port 1 serves the functions of the following special features of the 8XC51 FC:
PIN DESCRIPTIONS
Vee: Supply voltage.
Port Pin
Vss: Circuit ground.
Alternate Function
P1.0
VSS1: Secondary ground (not on DIP). 'Provided to
reduce ground bounce and improve power supply
by-passing.
T2 (External Count Input to Timerl
Counter 2), Clock-Out
P1.1
T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)
NOTE:
P1.2
P1.3
ECI (External Count Input to the PCA)
CEXO (External 1/0 for Comparel
Capture Module 0)
CEX1 (External 1/0 for Comparel
Capture ~odule 1)
CEX2 (External 1/0 for Comparel
Capture Module 2)
This pin is not a substitute for the Vss pin. Connect
Vss and VSS1 with the lowest impedance path possible.
P1.4
Port 0: Port 0 is an 8-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-imped'
ance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1's, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
~ort 1: Port 1 is an 8-bit bidirectional ,I 10 port with
Internal pull ups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
t~at state can be used as inputs. As inputs, Port 1
PinS that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
P1.5
P1.6
CEX3 (External 1/0 for Comparel
Capture Module 3)
P1.7
CEX4 (External 1/0 for Comparel
Capture Module 4)
Port 1 receives' the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional 110 port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory 'and during
8-118
intel$
87C51 FC/83C51 FC
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that stafe can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the 8XC51 FC is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if either of
the Program· Lock bits are programmed, EA will be
internally latched on reset.
EA should be strapped to Vee for internal program
executions.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The Port Pins will be driven to their reset condition when a voltage above VIH1 is applied whether
the oscillator is running or not. An internal pulldown
resistor permits a power-on reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FC.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX instruction. Otherwise the
pin is weakly pulled ~igh.
XTAL 1 and XT AL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
.
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
8-119
infele
87C51 FC/83C51 FC
To properly terminate Power down the reset or external interrupt should not be executed before Vee is
restored to its normal operating level. The external
interrupt or reset signal must be held active long
enough for the oscillator to restart and stabilize (normally less than 10 ms).
.
C2
1 - -.....--1 XTAL2
I--t---I
XTALI
With an external interrupt; INTO or INT1 must be enabled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
~-----~VSs
270789-4
C1, C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer.
Figure 3. Oscillator Connections
DESIGN CONSIDERATION
NIC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTALI
• The 8XC51 FC-L will operate at 3.3V ±0.3V at a
frequency range of 3.5 MHz to 8 MHz. Operating
beyond these specifications could cause improper device functionality. (To program the
87C51 FC-L, follow the same procedure as the
87C51 FC.)
Vss
• The window on the 87C51 FC must be covered by
an opaque label. Otherwise, the DC and AC characteristics may not be met, and the device may
functionally be impaired.
270789-5
Figure 4. External Clock Drive Configuration
0
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access tQ internal RAM in this event, but access to the .port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
o
0
ONCE MODE
POWER DOWN MODE
To save even more power,·a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC51 FC without the 8XC51 FC having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALl: low as RST is deactivated.
On the 8XC51 FC either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the .on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
While the device is in ONCE Mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC51 FC is in this mode, an emulator
or test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
8-120
intel·
87C51 FC/83C51 FC
Table 1. Status of the External Pins During Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Mode
PORTO
PORT1
PORT2
PORT3
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note Ap·252 (Embedded Applications Handbook), "Designing with the 80C51BH".
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V
IOL Per I/O Pin ........................... 15 rnA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions:
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex·
tended exposure beyond the "Operating Conditions"
may affect device reliability.
T A (under Bias) = O°C to + 70°C, VCC = 5V ± 20%, Vss = OV
(8XC51 FC-L, VCC = 3.3V ± 0.3V)
DC CHARACTERISTICS: (Over Operating Conditions)
All parameter values apply to both 5V and 3.3V devices unless otherwise indicated.
Symbol
Parameter
Typ
(Note 4)
Min
Max
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0.2Vee- 0.1
V
VIL1
Input Low Voltage EA
0
0.2 Vee-0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2 Vee+0.9
Vee+ 0.5
V
0.7 Vee
Vee+ 0.5
V
0.3
V
0.45
V
IOL = 1.6 rnA (Note 1)
1.0
V
IOL = 3.5 rnA (Note 1)
0.3
V
IOL = 200 JJ-A (Note 1)
0.45
V
IOL = 3.2 rnA (Note 1)
1.0
V
IOL = 7.0 rnA (Note 1)
VIHl
Input High Voltage (XTAL1, RST)
VOL
Output Low Voltage (Note 5)
(Ports 1, 2, and 3)
VOlt
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
8-121
IOL = 100 JJ-A (Note 1)
inial.
87C51 FC/83C51 FC
DC CHARACTERISTICS:
(Over Operating Conditions)
All parameter values apply to both 5V and 3.3V devices unless otherwise indicated. (Continued)
Symbol
VOH
VOH1
Parameter
Output High Voltage
(Ports 1, 2, and 3, ALE, PSEN)
Output High Voltage
(Port 0 in External Bus Mode)
Min
Typ
(Note 4)
Max
V
IOH
= -10 p,A
Vee- O.?
V
IOH
Vee- 1.5
V
IOH
Vee- 0.3
V
IOH
Vee- O.?
V
IOH
=
=
=
=
=
=
Logical 0 Input Current
(Ports 1, 2, and 3)
III
Input leakage Current (Port 0)
ITl
Logical 1 to 0 Transition Current
(Ports 1 , 2, and 3)
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
lee
Power Supply Current:
Active Mode
8XC51 FC-L at 8 MHz
All others at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
Test Conditions
Vee- 0.3
V
IOH
-50
p,A
VIN
Vee- 1.5
III
Unit
40
±10
p,A
0.45V
-650
p,A
VIN
225
K!1
10
pF
=
-30 p,A
-60 p,A
- 200 p,A
-3.2 mA
-?O mA
0.45V
< VIN <
Vee
2V
@1 MHz, 25°C
(Note 3)
20
5
15
12
40
10
100
mA
mA
mA
p,A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOlS of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
O.BV. It may be desirable to qualify ALE or other signals with Schmitt triggers or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vee for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, IOl must be externally limited as follows:
Maximum IOl per port pin:
10mA
Maximum IOl per B-bit portPort 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOL for all output pins:
?1 mA
If IOl exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
8-122
intel"
87C51FC/83C51FC
60mA
SOmA
IotAX.
40mA
30mA
----
~
A~
20mA
",
OmA
OIotHz
TYPICA.=----
-
A~ ----1ot~X.
~
IOmA
~
IDLE
TYPICAL IDLE
410tHz
810tHz
1210tHz
1610tHz
270789-6
ICC Max at other frequencies is given by:
Active Mode
Icc Max = (OSC Freq x 3) + 4
Idle Mode
Icc Max = (Osc Freq x 0.5) + 4
Where Osc Freq is in MHz, Icc Is in rnA.
Figure 5. Icc vs Frequency
Vee
VCC
Vee
PO
RST
".~_--I
po.,,~_~
EAH----'
RST
87C5tfC
EAI--......
87C5lfC
XTAL2
XTALt
XTAL2
XTALI
vss
vss
270789-7
270789-8
All other pins disconnected
TCLCH = TCHCL = 5 ns
All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 6. Icc Test Condition, Active Mode
Figure 7. Icc Test Condition Idle Mode
Vee
POI,\ .._~
EA 1---..
RST
87CStfC
XTAL2
XTALI
vss
270789-9
All other pins disconnected
Figure 8. Icc Test Condition, Power Down Mode. Vcc
=
2.0V to 6.0V
.1""___.---_
Vec-O.S -------.
0.7 vce
0.4SV---li0.2 Vee-O.l
TCHCL
270789-10
Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH
8·123
= TCHCL =
5 ns
intaL
87C51 FC/83C51 FC
P: PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
0: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oscillator
Min
Max
1/TCLCL Oscillator Frequency
Variable Oscillator
Min
Max
3.5
16
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX
Address Hold After ALE Low
53
TCLCL-30
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
53
TCLCL-30
TPLPH
PSEN Pulse Width
205
3TCLCL-45
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
ns
ns
ns
3TCLCL-105
145
0
ns
4TCLCL-100
234
0
ns
ns
TPXIZ
Input Instruction Float After PSEN
59
TCLCL-25
ns
TAVIV
Address to Valid Instruction In
312
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
TRLRH
RD Pulse Width
400
6TCLCL-100
TWLWH
WR Pulse Width
400
6TCLCL-100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
10
10
ns
5TCLCL-165
252
0
ns
ns
0
ns
ns
TRHDZ
Data Float After RD
107
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL-150
ns
TAVDV
Address to Valid Data In
9TCLCL-165
ns
TLLWL
ALE Low to RD or WR Low
200
TAVWL
Address Valid to WR Low
203
4TCLCL-130
ns
TOVWX
Data Valid before WR
33
TCLCL-50
ns
TWHOX
Data Hold after WR
33
TCLCL-50
ns
433
TQVWH
Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
585
300
3TCLCL-50
7TCLCL-150
0
43
123
8-124
3TCLCL+50
TCLCL-40
ns
ns
0
ns
TCLCL+40
ns
int:et
87C51FC/83C51FC
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
---
PSEN _ _. I
PORT 0 _ _J
----,--------------------'
PORT 2-
A8-A15
270789-11
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
'I
1 - - - - - TLLDV
- - - - 0. . . . .- -
RD
-------~------~
TRLRH - - - . I
r-----------------
PORTO~~~~
~E:
INSTR. IN
TAVWL
PORT2 __~r~________~P2~.0~-~P~2~.7~O~R~A~8_-~Al~5~F~R~O~M~D~PH~______~r~__~A~8-~A~I~5~F~RO~M~PC~H~__
270789-12
EXTERNAL DATA MEMORY WRITE CYCLE
,
ALE
I
-TLHLL-
\.
~
i=4-TWHLH
\.
-TLLWL
...
TAVLL
-
-TLLAX--
PORTO
PORT 2
:::r
:=J
,
TWLWH
...J
~
I-TWHOX
TOVWH
FROt.t~iS~
DPL
DATA OUT
K XAO- A7 FROM PCL
INSTR. IN
TAVWL
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
270789-13
8-125
intel..·
87C51FC/83C51FC
SERIAL PORT TIMING • SHIFT REGISTER MODE
Test Conditions:
Symbol
TA
=
O·C to
+ 70·C; Vee =
5V ± 20%; Vss
12 MHz Oscillator
Parameter
Min
=
OV; Load Capacitance
=
80 pF
Variable Oscillator
Min
Max
Units
Max
TXLXL
Serial Port Clock Cycle Time
12TCLCL
IJ-s
TOVXH
Output Data Setup to Clock
Rising Edge
700 '
1OTCLCL -133
ns
TXHOX
Output Data Hold after
Clock Rising Edge
50
2TCLCL-117
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
1
1OTCLCL -;-133
700
SHIFT REGISTER MODE TIMING WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol
P~rameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
8XC51FC
8XC51 FC-1
3.5
3.5
12
16
MHz
TCHCX
High Time
20
ns ,
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
.'
8-126
ns
int:eL
87C51FC/83C51FC
EXTERNAL CLOCK DRIVE WAVEFORM
270789-15
AC TESTING INPUT, OUTPUT WAVEFORMS
V-
VCC-0.5-y- 0.2 VCC+0.9
0.45
FLOAT WAVEFORMS
~.
V~_0_.2_VC::..:C:...-_0_.1_ _ _~~
TIMING REFERENCE
POINTS
270789-17
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOLlloH = ±20 mAo (·L, IOL/IOH = ±10 mAl
270789-16
AC Inputs during testing are driven at Vcc-0.5V for a Logic "1"
and 0.45V for a Logic "0". Timing measurements are made at VIH
min for a Logic "I" and VIL max for a Logic "0",
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hig..!:!...until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 respectively for AO-A14.
DATA LINES: PO.O-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
Table 2. EPROM Programming Modes
Mode
RST
PSEN
ALE!
PROG
EA!
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
H
Program Code Data
H
L
l..J
12.75V
L
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
l..J
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
l..J
12.75V
H
H
H
H
H
Bit 2
H
L
l..J
12.75V
H
H
H
L
L
Bit3
H
L
l..J
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Read Signature Byte
8-127
infel~
87C51 FC/83C51 FC
Repeat 1 through 5 changing the address and c;tata
for the entire array or until the end of the object file is
reached.
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 FC the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the co~rect combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
PROGRAM VERIFY
Program verify may be done after each byte or block
of bytes is programmed. A complete verify of the
array will ensure reliable programming of the
87C51FC.
The lock bits cannot be directly verified. They are
verified by observing that their features are enabled.
Refer to the EPROM Program Lock section in this
data sheet.
+5V
vee
87e51 FC
P1
P2.0P2.5
A14
EA/Vpp
P3.4
PSEN
P2.7
18
P2.6
XTAL2
P3.7
P3.6
19
20
32-39
PGM DATA
PO
ALE/PROG
14
40
P3.3
XTAL 1
RST
V55
31
30
} PROGRAM
SIGNALS
29
28
27
17
CONTROL SIGNALS'
16
13
9
270789-18
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
ADDRESS
X_________________X
X________________
DATA
8 BITS
CONTROL
SIGNALS
~X
7 BITS
12.75V
EA/Vpp
x
X'1581T5
I
5V--'
\....
TGLGH
ALE/PROG
270789-19
5 Pulses
Figure 11. Programming Signal's Waveforms
8-128
intal..
87C51 FC/83C51FC
ROM and EPROM Lock System
Program Lock Bits
The 87C51 FC and the 83C51 FC program lock systems, when programmed, protect the on board program against software piracy.
The 87C51 FC has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-Chip code
and data.
The 83C51 FC has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
3. If program protection is desired, the user submits
the encryption table with their code, and both the
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the
user must submit an encryption table.
The 87C51 FC has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, all locations are user-programmable. See Table 3.
Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 8XC51 FC has 3 signature bytes in locations
30H, 31 H, and 60H. To read these bytes follow the
procedure for EPROM verify, but activate the control
lines provided in Table 2 for Read Signature Byte.
Contents
Location
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (aIl1's), will return the code in it's
original, unmodified form. For programming the Encryption Array, refer to Table 2 (Programming the
EPROM).
When using the encryption array, one important factor needs to be considered. If. a code byte has the
value OFFH, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of
code is left unprogrammed,.a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be programmed with some value other than OFFH, and not
all of them the same value. This will ensure maximum program protection.
.
30H
87C51FC
83C51FC
89H
89H
31H
58H
58H
60H
FCH
FCHI7CH
Erasure Characteristics (Windowed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p..W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1's state.
8-129
intel .
87C51 FC/83C51 FC
Table 3. Program Lock Bits and the Features
Program Lock BItS
Protection Type
LB1
LB2
LEl3
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
Any other combination of the lock bits is not defined.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C; Vee = 5V ±20%; Vss = OV)
Symbol
. Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frequency
4
Units
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
VppSetup to PROG Low
10
jLs
TGHSL
Vpp Hold after PROG
10
,""S
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
110
,""S
48TCLCL
48TCLCL
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
8-130
48TCLCL
,""S
int'et
87C51FC/83C51FC
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
AO-A 14
VERIFICATION
-----{::~A~D~DR~E~S!S~
ADDRESS
TAVQV
DO-D7
-----+C:~!!~
TDVGL
ALEjiiROO
TGHDX
------"""'\l
EA/Vpp Vee
TGLGH
g-~V----li
EA/HIGH
TEHS:P
_ ___
CONTROL
__
SIGNALS
(ENABLE) - - - -
TELQV
L
l_--1_-T-EH-Q-Z--270769-20
DATA SHEET REVISION HISTORY
The following differences exist. between this data
sheet (270789-004) and the previous version
(270789-003):
1. Added 3.3V device to data sheet.
2. Data sheet title was changed from:
87C51 FC/~3C51 FC CHMOS Single-Chip 8-Bit
Microcontroller 32 Kbytes User Programmable
EPROM
to:
87C51 FC/83C51 FC CHMOS Single-Chip 8-Bit
Microcontroller with 32 Kbytes Internal Program
Memory
3. Data sheet status changed from "Preliminary" to
"Production" .
4. Added process information after block diagram.
5. IIja and IIje information added to Packages table.
The following differences exist between the -003
and -002 versions of this data sheet.
1. QFP package type added.
2. Changed "NC" pin labels to "Reserved".
3. Added second paragraph under "Encryption Array" section.
The following differences exist between the
270789-002 data sheet and the 270789-001 version:
1. Changed title from "87C51 FC" to "87C51 FCI
83C51 FC".
2. Changed data sheet status from "Advanced" to
"Preliminary" .
3. Deleted all references to -2 version.
8-131
4. Added "Four Level Interrupt Priority" feature bullet.
5. Changed feature bullet, "Two Level Program
Lock System" to read, "Three Level Program
Lock System".
6. Revised RST pin description to include asynchronous port reset feature.
7. Changed Figure 3 to read, "= 40 pF ± 10 pF for
Ceramic Resonators".
8. Added VIL 1 specification to DC Characteristics
Table.
9. Changed test conditions under III from OV to
0.45V for VIN minimum.
10. Changed Vee maximum from 5.5V to 6.0V for
lee Test Condition under Figure 8.
11. Revised Absolute Maximum Ratings warning
and data sheet status notice.
12. Reworded DC Characteristics Note 1.
13. Changed 1/TCLCL Minimum specification from
0.5 MHz to 3.5 MHz.
14. Revised "EPROM Program Lock" section to include ROM lock description.
15. Deleted all references to A 15 in "Definition of
Terms" and Figure 10.
16. Changed number of encryption array address
lines from 5 to 6 under "Encryption Array" section.
17. Added signature byte table to "Reading the Signature Bytes" section.
18. Added this revision summary.
87C51 FC/83C51FC
EXPRESS
sv
87CS1 FC/83CS1 FC-3.S MHz to 12 MHz, Vee =
± 20%
87CS1FC-1/83CS1FC-1-3.S MHz to.16 MHz, Vee = SV :1:20%
• Extended Temperature Range
• Burn-In
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS~-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O·C to 70"C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic for a minimum time of 168 hours at 125·C with Vee = 6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here. This data sheet is valid in conjunction with the commercial 87C51FC/83C51FC
data sheet, 270789-002.
8-132
October 1990
Order Number: 270903-001
int'eL
87C51 FC/83C51 FC EXPRESS
Electrical Deviations from Commercial Specifications for Extended Temperature
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.
D.C. CHARACTERISTICS TA = -40°C to +85°C;Vcc = 5V ±20%;Vss = OV
Symbol
Limits
Parameter
Min
-750
Logical 1 to 0 Transition Current
(Ports 1. 2 and 3)
ITL
Unit
Max
/LA
Test
Conditions
VIN
=
2V
Table 1. Prefix Identification
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
0"
Cerdip
Commercial
No
Prefix
N
PLCC
Commercial
No
TP
Plastic
Extended
No
TO"
Cerdip
Extended
No
TN
PLCC
Extended
No
LP
Plastic
Extended
Yes
LO"
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
NOTE:
• Commercial temperature range is O'C to 70'C. Extended temperature range is - 40'C to + 85'C.
• Burn-in is dynamic for a minimum time of 168 hours at 125'C. Vee = 6.9V ±0.25V. following guidelines in MIL-STD-883
Method 1015 (Test Condition D).
"Available for 87C51FC only.
Examples:
P87C51 FC indicates 87C51 FC in a plastic package and specified for commercial temperature range. without
burn-in.
L087C51 FC indicates 87C51 FC in a cerdip package and specified for extended temperatu,re range with burnin.
DATA SHEET REVISION SUMMARY
This is Rev. 1 of the 87C51 FC/83C51 FC Express data sheet.
8-133
87C51 FC-20/-3
83C51 FC-20/-3
COMMERCIAL/EXPRESS 20 MHz MICROCONTROLLER
87CS1 FC-20/83CS1 FC-2o-3.S MHz to 20 MHz, Vee = SV±200/0
87CS1 FC-3/83CS1 FC-3-24 MHz Internal Operation, Vee = SV±200/0
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS EPROM
24 MHz Internal Operation (-3 only)
Three 16-Bit Timer/Counters
Programmable Clock Out
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
~ Watchdog Timer capabilities
Up/Down Timer/Counter
T!1ree Level Program Lock System
32K On-Chip EPROM
2S6 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
•
•
•
•
•
•
•
•
•
•
32 Programmable I/O Lines
7 Interrupt Sources
Four Level Interrupt Priority
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
MCS®-S1 Fully Compatible Instruction
Set
Power Saving Idle and Power Down
Modes
ONCE (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 8XC51 FC-20/-3 is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the 8XC51 FC-20/-3 uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 8XC51 FC-20/-3 is an enhanced version of the 87C51 /80C51 BH. Its added features make it an
even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O and
up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates
multi-processor communications.
The 87C51 FC-3/8SC51 FC-S has the same S.5 MHz to 20 MHz frequency range as the 87C51 FC-20/
8SC51 FC-20 when operating out of external program/data memory. When running out of internal program/
data memory, the 87C51 FC-3/8SC51 FC-S can operate up to 24 MHz.
Throughout this document 8XC51 FC-20 will refer to the 8SC51 FC-20, 87C51 FC-20, 8SC51 FC-S and the
87C51 FC-3.
8-1S4
October 1992
Order Number: 272028-002
intel..
87C51 FC-20/-3 83C51 FC-20/-3
PO.O -PO.7
PSEN
ALW'iiOO
EA/VPP
RST
TIMING
AND
CONTRGL
272028-1
Figure 1. 8XC51 FC-20 Block Diagram
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components and Reliability Handbook, Order Number 210997.
8-135
intel .
87C51 FC-20/-3 83C51 FC-20/-3
PACKAGES
Part
Prefix
8XCS1FC-20
~7CS1FC-20
8XCS1FC-20
8XCS1FC-20
P
D
N
S
Package Type
BJa
BJc
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-PinQFP· .
4SoC/W
36°C/W
46°C/W
87°C/W
16°C/W
13°C/W
16°C/W
18°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
(T2) PI.O
(ECI) PI.2
Vee
PO.O (ADO)
PO. I (Ao1)
(CEXO) PI.3
PO.2 (A02)
(CEX1) PI.4
PO.3 (A03)
(CEX2) PI.5
PO.4 (A04)
(TZEX) PLI
INDEX
CORNER
"! "! OJ
a:: a:: a:: a:: ::l... .} >'d
0
f ...ci
. ...,.,
ci ci
...
PI.5
PO.4
PI.&
PO.5
PI.7
PO.6
PO.7
RST
(CEX3) P1.6
PO.5 (ADS)
(CEX4) PI.7
PO.& (AD&)
P3.0
RESET
(RXo) PM
PO.7 (A07)
RESERVED"
EA
P3.1
ALE
(TXo) P3.1
ALE
P3.2
PSEN
(iNfO) P3.2
CiN'fi) P3.3
PSEN
P3.3
P2.7
P2.7 (AI5)
P2.6 (AI4)
P3.4
P2.6
P3.5
P2.5
(TO) P3.4
(T1) P3.5
P2.S (AI3)
P2.4 (A 12)
(iii) P3.&
(iiO) P3.7
XTAL2
XTALI
Vss
EA
aXCS1 FC - 20
RESERVED"
P2.3 (All)
P2.2 (AIO)
..'" ...... .....~ :::;~ III •~... -N ..N ....
P2.1 (A9)
P2.0 (A8)
'"
~
,.; ,.;
C"'I
a.. a.. a..
>
"!
"!
('II
0..
~
272028-3
PLCC
272028-2
DIP
INDEX
CORNER,
P1.S
::~~::~
~8~ddd
~ ~ a. a. a. ~
> a. ~ a. ~
.;;I.I=:II::II:;:II~II::;II~II~II~II~II:I
C!.....
i :{3
_I . . . . . . . . . . . . . . . . . _ . . . . . . . . . _l
PI.S (~
PI.7 (~
RST
P3.0
RESERVED"
P3.1
PU
~3
i;[2 PM
i!1 PO.6
i(o PO.7
.(!
5:!
s: ~
Ph ....
aXCS1 FC - 20
(!
a: ~
i(9 EA
its RESERVED"
L~ ALE
PSEN
Lts
(!
~n7
Lt4
1]!......... ~.,...... ,...._ ...........Lt3
.1~11::!11;!11~11~11~11~11~1121INII~1.
P3.4 19!
P2.6
Pl.S
P2.5
272028-'4
QFP
• Do not connect reserved pins.
Figure 2. Pin Connections
8-136
int:eL
87C51 FC-20/-3 83C51FC-20/-3
In addition, Port 1 serves the functions of the following special features of the 8XC51 FC-20:
PIN DESCRIPTIONS
Vee: Supply voltage.
Vss: Circuit ground.
VSS1: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
P1.1
NOTE:
P1.2
This pin is not a substitute for the Vss pin. Connect
Vss and VSS1 with the lowest impedance path possible.
P1.3
CEXO (External I/O for Compare/
Capture Module 0)
P1.4
CEX1 (External I/O for Compare/
Capture Module 1)
P1.5
CEX2 (External 110 for Compare/
Capture Module 2)
P1.6
CEX3 (External I/O for Compare/
Capture Module 3)
CEX4 (External I/O for Compare/
Capture Module 4)
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1's, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
P1.7
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
8-137
87C51 FC-20/-3 83C51 FC-20/-3
pin, and the pin will be referred to as the ALE/PROG
pin.
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional 1/0 port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INn (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
When the 8XC51 FC-20 is executing code from external Program Memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to external
Data Memory.
EAlVpp~ External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH. Note, however, that if either of
the Program Lock bits are programmed, EA will be
internally latched on reset.
EA should be strapped to Vee for internal program
executions.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The Port Pins will be driven to their reset condition when a voltage above VIH1 is applied whether
the oscillator is running or not. An internal pull down
resistor permits a power-on reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FC-20.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX instruction. Otherwise the
pin is weakly pulled high.
XTAL 1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning·
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 floats, as
shown in Figure ~. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but the minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
8-138
inteL
87C51 FC-20/ -3 83C51 FC-20/-3
With an external interrupt, INTO or INT1 must be enabled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
t---t--; XTAL2
t-.....-~XTALI
t - - - - - - ; Vss
272028-5
TIMER 2 PROGRAMMABLE
CLOCK OUT
=
30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer.
Cl, C2
Figure 3. Oscillator Connections
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
The maximum Timer 2 clock out frequency on the
8XC51 FC-20 cannot be determined by the equation
in the 8XC51 FX Hardware Description as shown below.
CI
\
Even though the equation permits a maximum clockout frequency of 5 MHz using a 20 MHz oscillator,
the maximum device output frequency is 4 MHz.
When using a 20 MHz oscillator, RCAP2L must be
limited to a maximum value of FEH.
Vss
272028-6
Figure 4. External Clock Drive Configuration
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
For a complete description of ali Timer 2 functions,
please reference the 8XC51 FX Hardware Description in the Embedded Microcontrollers and Processors Handbook Volume I.
DESIGN CONSIDERATION
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the 8XC51 FC-20 either a hardware reset or an
external interrupt can cause an exit from Power
Down. Reset redefines all the SFRs but does not
change the on-chip RAM. An external interrupt allows both the SFRs and on-chip RAM to retain their
~~~
k0 F
Oscillator Frequency
oc - ut requency = 4 X (65536 - RCAP2H, RCAP2L)
.
. To properly terminate Power down the reset or external interrupt should not be executed before Vcc is
restored to its normal operating level. The external
interrupt or reset signal must be held active long
enough for the oscillator to restart and stabilize (normally less than 10 ms).
8-139
• When running out of internal program/data memory, the 87C51 FC-3/83C51 FC-3 can be operated
using
a
24
MHz
clock.
If
the
87C51 FC-3/83C51 FC-3 is running out of external
program/data memory, the operating frequency
must be between 3.5 MHz to 20 MHz. The
87C51 FC-3/83C51 FC-3 will not function properly
at 24 MHz when running out of external program/
data memory.
• The window on the 87C51 FC-20 must be covered by an opaque label. Otherwise, the DC and
AC characteristics may not be met, and the device may functionally be impaired.
II When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
infel .
87C51 FC·20/·3 83C51 FC·20/·3
While the device is in ONCE Mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC51 FC-20 is in this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is
applied.
ONCE MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC51 FC-20 without the 8XC51 FC-20 having to be
removed from the circuit. The ONCE Mode is invoked by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
Table 1. Status of the External Pins During Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
Idle
External
1
Power Down
Internal
0
Power Down
External
0
Mode
,
PORTO
PORT1
PORT2
PORT3
1
Data
1
Float
Data
Data
Data
Data
Address
Data
0
Data
Data
Data
Data
0
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), "DeSigning with the BOC51 BH."
8-140
int:et
87C51 FC-20/-3 83C51 FC-20/-3
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias. -40°C to + 85°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V
IOL Per 1/0 Pin ........................... 15 rnA
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
-40
+70
+85
°C
°C
Vee
Supply Voltage
4.0
6.0
V
fose
Oscillator Frequency
3.5
20
MHz
TA
DC CHARACTERISTICS Over Operating Conditions
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
Max
Unit
0.2 Vee-0.1
V
Input Low Voltage EA
0
0.2 Vee-0.3
V
Input High Voltage
(Except XTAL 1, RST)
0.2 Vee + 0.9
Vee+ 0.5
V
0.7 Vee
Vee+ 0.5
V
0.3
V
0.45
V
IOL= 1.6 mA(1)
Input Low Voltage
VIL1
VIH
VIH1
Input High Voltage (XTAL 1, RST)
VOL
Output Low Voltage(5)
(Ports 1, 2, and 3)
VOL1
VOH
VOH1
Typ(4)
-0.5
VIL
Min
Output Low Voltage(5)
(Port 0, ALE, PSEN)
Output High Voltage
(Ports 1, 2, and 3, ALE, PSEN)
Output High Voltage
(Port 0 in External Bus Mode)
IOL = 100 fLA(1)
1.0
V
IOL = 3.5 mA(1)
0.3
V
IOL = 200 fLA(1)
0.45
V
IOL = 3.2 mA(1)
1.0
V
IOL
Vee- 0.3
V
Vee- 0.7
V
Vee- 1.5
V
Vee- 0.3
V
Vee- 0.7
V
Vee- 1.5
V
8-141
Test Conditions
= 7.0 mA(1)
IOH = -10 fLA
IOH = -30 fLA
IOH = -60 fLA
IOH = - 200 fLA
iOH = -3.2mA
IOH = -7.0mA
intaL
87C51 FC-20/-3 83C51 FC-20/-3
DC CHARACTERISTICS Over Operating Conditions (Continued)
All parameter values apply to both Commercial and Express devices unless otherwise indicated.
Symbol
Parameter
Min
Typ(4)
Max
Unit
Test Conditions
IlL
Logical 0 Input Current
(Ports 1 , 2, and 3)
-50
p.A
VIN = 0.45V
III
Input leakage Current (Port 0)
±10
p.A
0.45V
ITL
Logical 1 to 0 Transition Current
(Ports 1 , 2, and 3)
Commercial
Express
-650
-750
p.A
VIN = 2V
225
K!l
RRST
RST Pulldown, Resistor
CIO
. Pin Capacitance
Icc
Power Supply Current:
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode
40
10
pF
< VIN < Vcc
@1 MHz, 25°C
(Note 3)
20
5
15
40
10
100
mA
mA
p.A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above O.4V to be superimposed on the VOLS of ALE and
Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other Signals with Schmitt triggers or CMOS-level input logiC.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vcc speCification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vee for Power Down is 2V.
4. Typicals are based on limited numberof samples and are not guaranteed. The values listed are at room temperature and
5V.
.
5. Under steady state (non-tranSient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
Maximum IOL per 8-bit portPort 0:
26 mA
Ports1,2and3:
15mA
Maximum total IOL for ali output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
8-142
intel .
87C51 FC-20/-3 83C51 FC-20/-3
70mA
./
60mA
/
50mA
~
40mA
A:Y
30 rnA
./
20 rnA
/'"
" .----:.
10mA
OmA
OMHz
.."
A~
4 MHz
----
8MHz
~
IDLE IjAX
---
IDLE
.---
-
TYPICAL
12MHz
16MHz
20MHz
272028-7
Icc Max at other frequencies is given by:
Active Mode
Icc' Max = (Osc Freq x 3) + 4
Idle Mode
Icc Max = (Osc Freq x 0.5) + 4
Where Osc Freq is in MHz, Icc is in mA.
Figure 5. Icc vs Frequency
Vee
Vee
Vee
PO
RST
''\..---1
PO
EAI+--.I
RST
fi...---.,
87C51rC-20
CLOCK
XTAL2
SIGNAL ---+I XTAL 1
CLOCK
XTAL2
SIGNAL ---+I XTAL 1
Vss
Vss
272028-8
272028-9
All other pins disconnected
TCLCH = TCHCL = 5 ns
All other pins disconnected
TCLCH = TCHCL = 5 ns
Figure 6. Icc Test Condition, Active Mode
Figure 7. ICC Test Condition Idle Mode
8-143
infel .
87C51 FC-20/-3 83C51FC-20/~3
Vcc
PO I V - - -
EA t----,
RST
87CS1FC-20
XTAL2
XTALI
VSS
272028-10
All other pins disconnected
Figure 8. Icc Test Condition, Power Down'Mode
Vce = 2.0V to 6.0V
---,
Vce- O•S -------~~.;..<
0.7 vcc
O.-4SV.
0.2 Vee-0.1
TCHCL
272028-11
Figure 9. Clock Signal Waveform for Icc Tests In Active and Idle Modes
TCLCH = TCHCL = 5 ns
P:PSEN
EXPLANATION OF THE AC SYMBOLS
Q: Output Data
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
R: RD Signal
T:Time
V: Valid
W: WR signal
X: No longer a valid logic level
A: Address
Z: Float
C: Clock
0: Input Data
For example,
H: Logic level HIGH
TAVLL = Time from Address Valid to ALE Low
I: Instruction (program memory contents)
TLLPL
L: Logic level LOW, or ALE
8-144
= Time from ALE Low to PSEN Low
87C51 FC-20/-3 83C51 FC-20/-3
AC CHARACTERISTiCS
PSEN
=
(Over Operating Conditions, Load Capacitance for Port 0, ALE/PAOG and
100 pF, Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
20 MHz Oscillator
Min
Max
1/TCLCL Oscillator Frequency
Variable Oscillator
Min
Max
3.5
20
Units
MHz
60
2TCLCL-40
ns
Address Valid to ALE Low
10
TCLCL-40
ns
Address Hold After ALE Low
20
TCLCL-30
ns
TLHLL
ALE Pulse Width
TAVLL
TLLAX
TLLlV
ALE Low to Valid Instruction In
TLLPL
ALE Low to PSEN Low
20
125
105
4TCLCL-75
TCLCL-30
ns
ns
3TCLCL-45
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instruction In
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instruction Float After PSEN
30
TCLCL-20
ns
TAVIV
Address to Valid Instruction In
145
5TCLCL-105
ns
TPLAZ
PSEN Low to Address Float
10
10
ns
0
ns
3TCLCL-90
60
0
ns
ns
TRLRH
AD Pulse Width
200
6TCLCL-100
ns
TWLWH
WR Pulse Width
200
6TCLCL-100
ns
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
5TCLCL-95
155
0
0
ns
ns
TRHDZ
Data Float After RD
40
2TCLCL-60
ns
TLLDV
ALE Low to Valid Data In
310
8TCLCL-90
ns
TAVDV
Address to Valid Data In
9TCLCL-90
ns
TLLWL
ALE Low to RD or WR Low
3TCLCL+50
ns
360
100
200
3TCLCL-50
TAVWL
Address Valid to WR Low
110
4TCLCL-90
TaVWX
Data Valid before WR
15
TCLCL-35
ns
TWHaX
Data Hold after WR
10
TCLCL-40
ns
TaVWH
Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
7TCLCL-70
280
0
10
8-145
90
TCLCL-40
ns
ns
0
ns
TCLCL+40
ns
87C51 FC-20/-3 83C51 FC-20/-3
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _J
PSEN _ _J
PORT 0
---
PORT 2 _ _ _J
A8 - A15
272028-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
~----TLLDV
"'
- - - - > - \ - - - TRLRH
PORTO
INSTR. IN
PORT 2
P2.0-P2.7 OR A8-A 15 FROM DPH
A8-A15 FROM PCH
272028-13
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
-i.-TLHLL~
I
\.
~
=l-TWHLH
~
-TLLWL
- -
TWLWH
TAVLL
- TLLAX-
PORTO
PORT 2
:::r
-~
~
TQVWH
FROM'Rro"rf DPL
DATA OUT
-
-TWHQX
XAO-A7 FROM PCL
INSTR: IN
TAVWL
P2.0-P2.7 OR A8-A 15 FROM DPH
X
A8-A15 FROM PCH
272028-14
8-146
intel .
87CS1FC-20/-383CS1FC-20/-3
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions:
Symbol
TA
=
O°C to
+ 70°C; Vee =
=
SV ± 20%; Vss
OV; Load Capacitance
20 MHz Oscillator
Parameter
Min
=
80 pF
Variable Oscillator
Max
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
600
12 TCLCL
ns
TQVXH
Output Data Setup to Clock
Rising Edge
367
10 TCLCL - 133
ns
TXHQX
Output Data Hold after
Clock Rising Edge
SO
2 TCLCL - SO
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
367
10 TCLCL - 133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
I
0
2
3
4
6
7
8
ALE
CLOCK
~ITXHQX
OUTPUT DATA
\
I
WRITE TO SBUF
INPUT DATA
0
IX
I
...j TXHDV
IX
t
X
2
3
X
4
X
5
X
6
X
I
7
•
I:
..JrTXHDX
SET TI
------.UV~AL:O::ID~~~AU~D-""'V~AU-::DV--'~":!!01'~~~-\r.:~"--~'-"",,~'-1
•
I
SET RI
CLEAR RI
272028-15
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
3.S
20
MHz
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272028-16
8·147
87C51 FC-20/-3 83C51 FC-20/-3
AC TESTING INPUT, OUTPUT WAVEFORMS
V-
VCC-0.5-y 0.2 VCC+0.9
0.45
FLOAT WAVEFORMS
TIMING REFERENCE
POINTS
v-A_
0_.2_V.:;.CC;;...-_0_.,_ _ _ _" -
272028-18
For timing purposes a port pin is no longer lIoating when a
100 mV change Irom load voltage occurs, and begins to lIoat
when a 100 mV change Irom the loaded VOHIVOL level occurs.
IOLliOH = ± 20 rnA.
272028-17
AC Inputs during testing are driven at Vcc-0.5V lor a Logic "1"
and 0.45V lor a Logic "0". TIming measurements are made at VIH
min lor a Logic "1" and VIL max lor a Logic "0".
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EAlVpp is held at logic hi9.b..until just before ALEI
PROG is to be pulsed. The EAlVpp is raised to Vpp,
ALE/PROG is pulsed low and then EAlVpp is returned to a high (also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.5, P3.4 respectively for AO-A14.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
Table 2. EPROM Programming Modes
Mode
RST
PSEN
ALEI
PROG
EAt
Vpp
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
L.r
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0-3FH
H
L
L.r
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
L.r
12.75V
H
H
H
H
H
Bit2
H
L
L.r
12.75V
H
H
H
L
L
Bit3
H
L
L.r
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
,
Read Signature Byte
8-148
intel .
87C51 FC-20/-3 83C51 FC-20/-3
+5V
87C51FC- 20
1-8
AO-A7
PI
PGM DATA
21-26
A8-A13
P2.0---vIP2.5
31
Ei./Vpp
30
ALEIPROG
14
A 14 - - - - t P 3 . 4
-PSEN
P2.7
P2.6
..........._ _1;...;8-fXTAL 2
P3.7
P3.6
L-. . ._~;...;19-fXTAL I
P3.3
20 VSS
RST
~_.....;.
}
PROGRAM
SIGNALS
29
28
27
17
CONTROL SIGNALS'
16
13
9
272028-19
'See Table 2 for proper input on these pins
Figure 10. Programming the EPROM
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51 FC-20 the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the enqryption table and
the lock bits.
ADDRESS·
PROGRAM VERIFY
Program verify may be done after· each byte, or
block of bytes that is programmed. A complete verify
of the array will ensure reliable programming of the
87C51 FC-20.
The lock bits cannot be directly verified. They are
verified by observing that their features are enabled.
Refer to the EPROM Program Lock section in this
data sheet.
X __
X
15_B_IT_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_________________X
X
X______
8 BITS
DATA
CONTROL
SIGNALS
7 BITS
12.75V
Ei./Vpp
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
~
_________X
_ - - - - - -......- - - - - - - - - - _ ' - -
5VJ
TGLGH
ALE/PROO
272028-20
5 Pulses
Figure 11. Programming Signal's Waveforms
8-149
intel·
87C51 FC-20/-3 83C51 FC-20/-3
ROM and EPROM Lock System
Program Lock Bits
The 87C51 FC-20 and the 83C51 FC-20 program lock
·systems, when programmed, protect the onboard
program against software piracy.
The 87C51 FC-20 has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data.
The 83C51 FC-20 has a one-level program lock system and a 64-byte encryption table. See line 2 of
Table 3. If program protection is desired, the user
submits the encryption table with their code, and
both the lock-bit and encryption array are programmed by the factory. The encryption array is not
available without the lock bit. For the lock bit to be
programmed, the user must submit an encryption table.
The 87C51 FC-20 has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, all locations .are user-prQgrammable. See Table 3.
EraSing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 8XC51 FC-20 has 3 Signature bytes in locations
30H, 31 H, and 60H. To read these bytes follow the
procedure for EPROM verify, but activate the control
lines provided in Table 2 for Read Signature Byte.
Location
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed diJring a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in it's
original, unmodified form. For programming the Encryption Array, refer to Table 2 (Programming the
EPROM).
When using the encryption array, one important factor needs to be considered. If a code byte has the
value OFFH, verifying the byte will produce the encryption byte value. If a large block (> 64 ,bytes) of
code is left unprogrammed, a verification routine will
di.splay the contents of the encryption array. Forthis
reason all unused code bytes should be programmed with some value other than OFFH, and not
all of them the same value. This will. ensure maximum program protection.
Contents
87C51 FC-20
83C51 FC-20
30H
89H
a9H
31H
58H
58H
60H
FCH
FCH17CH
Erasure Characteristics (Windowed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 jLW/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure IEiavels all the EPROM Cells in a 1's state.
8-150
intele
87C51 FC-20/-3 83C51 FC-20/-3
Table 3. Program Lock Bits and the Features
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
Any other combination of the lock bits
IS
not defined.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C; Vee = 5V ±20%; Vss = OV)
Symbol
Parameter
Min
Max
Units
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
1/TCLCL
Programming Supply Current
Oscillator Frequency
4
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold' after PROG '
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
TGHSL
Vpp Hold after PROG
10
TGLGH
PROGWidth
90
TAVOV
Address to Data Valid
TELOV
ENABLE Low to Data Valid
TEHOZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
75
mA
6
MHz
110
,...S
,...S
,...S
10
48TCLCL
48TCLCL
8·151
48TCLCL
,...S
87C51 FC-20/-3 83C51 FC-20/-3
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
AO-A 14
VERIFICATION
-----1C=~A~OO~R~ES~S~
ADDRESS
TAVQV
00-07
AlE/PROG
EA/Vpp
-----...,~=~!!J~
TOVGl,
DATA OUT
TGHOX
------,,1
Vee
EA/HIGH
L l __
TElQV)"'-_ _
CONTROL - - SIGNALS _ __
TE_HQ_Z_ __
272028-21
DATA SHEET REVISION SUMMARY
The following differences exist between this data sheet (272028-002) and the previous version (272028-001):
1. Added 87C51 FC-3/83C51 FC-3 to 20 MHz data sheet.
2. Added EXPRESS version of 8XC51 FC-20/-3 to 20 MHz data sheet.
3. Data sheet title was changed from:
87C51 FC-20/83C51 FC-20 20 MHz CHMOS Single-Chip 8-Bit Microcontroller with 32 Kbytes User Programmable EPROM
to:
87C51 FC-20/-3 83C51 FC-20/-3 Commercial/Express 20 MHz Microcontroller
4. Added process information after block diagram.
5. 8ja and 8jc information added to Packages Table.
6. Variable Oscillator equations in External Memory Characteristics Table changed as follows: .
From
To
TLLlV
120
125
4TCLCL - 80
4TCLCL -75
TPLIV
3TCLCL - 95
3TCLCL - 90
TWHOX
0
10
TCLCL-50
TCLCL-40
TOVWH
200
280
7TCLCL -150
7TCLCL - 70
8-152
intel·
87C51 FC-20/-3 83C51 FC-20/-3
The following differences exist between revision 1 of the 87C51 FC-20/83C51 FC-20 (272028-001) data sheet
and the 87C51 FC/83C51 FC (270789-002) data sheet:
1. OFP package added.
2. Pins labeled "NC" changed to "Reserved" on the PLCC pinout.
3. Timer 2 Programmable Clock Out paragraph added.
4. RRST specification in DC Characteristics Table changed from 40 KO min, 225 KO max to 50 KO min,
300 KO max.
5. 20 MHz extension added to Figure 3.
6. 12 MHz Oscillator timings changed to 20 MHz in External Program Memory Characteristics and Serial Port
Timing Tables.
7. Variable Oscillator equations in External Program Memory Characteristics Table changed as follows:
From
To
TLLlV
4TCLCL - 100
4TCLCL - 80
3TCLCL - 105
3TCLCL - 95
TPLIV
TCLCL - 25
TCLCL - 20
TPXIZ
TRLDV
5TCLCL - 165
5TCLCL - 95
8TCLCL - 150
8TCLCL - 90
TLLDV
TAVDV
9TCLCL - 165
9TCLCL - 90
4TCLCL - 130
4TCLCL - 90
TAVWL
TCLCL - 50
TCLCL - 35
TOVWX
8. TXHOX in the Serial Port Timing Table changed from (2TCLCL - 117) to (2TCLCL - 50).
8-153
8XC51GB Hardware
Description and Data Sheets
9
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intel·
September 1992
87C51GB
Hardware Description
Order Number: 270897-003
9-1
87C51 GB Hardware Description
CONTENTS
CONTENTS
PAGE
1.0 INTRODUCTION TO THE
8XC51GB .............................. 9-4
PAGE
7.0 PROGRAMMABLE COUNTER
ARRAY ... ............................ 9-24
7.1 PCA Timer/Counter .............. 9-25
Reading the PCA Timer ............ 9-27
7.2 Compare/Capture Modules ....... 9-27
7.3 PCA Capture Mode ............... 9-28
7.4 Software Timer Mode ............. 9-30
7.5 High Speed Output Mode ......... 9-31
7.6 Watchdog Timer Mode ...... ~ ..... 9-31
7.7 Pulse Width Modulator Mode ...... 9~32
2.0 MEMORY ORGANIZATION .......... 9-4
2,1 Program Memory .................. 9-4
2.2 Data Memory ...................... 9-4
3.0 SPECIAL FUNCTION
REGISTERS ........................... 9-6
4.0 I/O PORT£? .......................... 9-9
4.1 I/O Configurations ..... : ........... 9-9
4.2 Writing to a Port .................. 9-10
4.3 Port Loading and Interfacing ...... 9-11
4.4 Read-Modify-Write Instructions ... 9-11
4.5 Accessing External Memory ....... 9-12
8.0 SERIAL PORT ...................... 9-34
8.1 Framing Error Detection .......... 9-36
8.2 Multiprocessor C0!11munications .. 9-36
8.3 Automatic Address Recognition ... 9.-37
8.4 Baud Rates ....................... 9-37
8.5 Timer 1 to Generate Baud
Rates ......... .' ..................... 9-37
8.6 Timer 2 to Generate Baud
Rates .............................. 9-38
5.0 TIMER/COUNTERS ................. 9-14
5.1 Timer 0 and Timer 1 .............. 9-14
ModeO ........................... 9-15
Mode 1 ........................... 9-16
Mode 2 ........................... 9-17
Mode 3 ........................... 9-17
5.2 Timer 2 ........................... 9-18
Timer 2 Capture Mode ............. 9-19
Timer 2 Auto-Reload Mode ........ 9-19
5.3 Programmable Clock-Out ......... 9-21
9.0 SERIAL EXPANSION PORT ........ 9-39
9.1 Programmable Modes and Clock
Options ............................ 9-40
9.2 SEP Transmission or Reception . .'. 9-41
10.0 HARDWARE WATCHDOG
TIMER ................................ 9-41
10.1 Using the WDT .................. 9-41
10.2 WDT During Power Down and
Idle ............... : ................ 9-41
6.0 A/D CONVERTER .................. 9-22
6.1 AID Special Function Registers ... 9-22
6.2 AID Comparison Mode ........... 9-23
6.3 AID Trigger Mode ................ 9-23
6.4 AID Input Modes ................. 9-23
6.5 Using the AID with Fewer than 8
.Inputs .............................. 9-23
6.6 AID in Power Down ............... 9-24
11.0 OSCILLATOR FAIL DETECT ...... 9-41
11.1 OFD During Power Down ........ 9-42
9-2
CONTENTS
CONTENTS
PAGE
PAGE
12.0 INTERRUPTS . ..................... 9-42
12.1 External Interrupts ............... 9-42
14.0 POWER-SAVING MODES ......... 9-50
14.1 Id.le Mode ....................... 9-52
12.2 Timer Interrupts ................. 9-44
14.2 Power Down Mode .............. 9-52
12.3 peA Interrupt .................... 9-44
14.3 Power Off Flag .................. 9-52
12.4 Serial Port Interrupt .............. 9-44
15.0 EPROM/OTP PROGRAMMING .... 9-53
15.1 Program Memory Lock .......... 9-53
12.5 Interrupt Enable ................. 9-44
12.6 Interrupt Priorities ............... 9-46
Program Lock Bits ................. 9-53
12.7 Interrupt Processing ............. 9-48
12.8 Interrupt Response Time ........ 9-49
16.0 ONCE MODE ...................... 9-53
13.0 RESET .......... ................... 9-50
17.0 ON-CHIP OSCILLATOR ........... 9-53
13.1 Power-On Reset ................. 9-50
18.0 CPU TIMING ....................... 9-55
9-3
infel .
87C51GB HARDWARE DESCRIPTION
•
•
-
1.0 INTRODUCTION TO THE
8XC51GB
The 8XC51GB is a highly integrated 8-bit ~icrocon
troller based on the MCS®-51 architecture. As a member of the MCS-51 family, the 8XC51GB is optimized
for control applications. Its key features are an analog
to digital converter and two programmable counter arrays (PCA) capable of measuring and generating pulse
information on ten I/O pins. Also included are an enhanced serial port for multi-processor communications,
a serial expansion port,hardware watchdog timer, oscillator fail detection, an up/down timer/counter and a
program lock scheme for the on-chip program memory.
Since the 8XC51GB is CHMOS, it has two software
selectable reduced power modes: Idle Mode and Power
Down Mode.
The table below summarizes the product names of the
various 8XC51GB products currently available.
Throughout this document, the products will generally
be referred to as the 8XC51GB. Figure 1 shows a functional block diagram of the 8XC5IGB.
The 8XC51GB used the standard 8051 instruction set
and is functionally compatible with the existing
MCS-51 family of products.
This document presents a comprehensivl'\ description of
the on-chip hardware features of the 8XC51GB. It begins with a discussion of how the memory is organized,
followed by the instruction set, and then discusses each
of the peripherals listed below.
• Six 8-bit Bidirectional Parallel Ports
• Three 16-bit Timer/Counters with
- One Up/Down Timer/Counter
- Programmable Clock Output
• Analog to Digital Converter with
- 8 channels
- 8-bit resolution
- compare mode
• Two Programmable Counter Arrays with
- Compare/Capture
- Software Timer
- High Speed Output
- Pulse Width Modulator
- Watchdog Timer (PCA only)
• Full-Duplex Programmable Serial Port with
- Framing Error Detection
- Automatic Address Recognition
• Serial Expansion Port
- four programmable modes
- four selectable frequencies
• Hardware Watchdog Timer
• Reset
- asynchronous
- active low
Interrupt Structure with
IS interrupt sources
Four priority levels
Power-Saving Modes
Idle Mode
Power Down Mode
ROM
Device
OTP
Version
ROMless
Version
ROMI
OTP
Bytes
RAM
Bytes
87C51GB
87C51,GB
80C51GB
8K
256
2.0 MEMORY ORGANIZATION
All MCS-51 devices have a separate address space for
Program Memory and Data Memory. The logical separation of Program and Data Memory allows the Data
Memory to be accessed by 8-bit addresses, which can be
, more quickly stored and manipulated by an 8-bit CPU.
Nevertheless, 16-bit Data Memory addresses can also
be generated through the DPTR register. Up to
64 Kbytes each of external Program and Data Memory
can be addressed.
2.1 Program Memory,
Program Memory can only' be read, not written to.
There can be up to 64 Kbytes of Program Memory.
The read strobe for external Program Memory is the
signal PSEN (Program Store Enable). PSEN is not activated for internal program fetches.
If the EA (External Access) pin is connected to Vss, all
program fetches are directed to external memory. For
the ROMless devices, all:..E!ogram fetches must be to
external memory. If the EA pin is connected to Veeo
then program fetches greater than 8K are to external
addresses for the 8XC51GB products.
On the 87C51GB with EA connected to Vee, program
fetches to addresses OOOOH through IFFFH are to internal ROM, and fetches to addresses 2000H through
FFFFH are to external memory.
2.2' Data Memory
The ,8XC51GB implements 256 bytes of on-chip data
RAM. The' memory space is divided into three blocks,
• Oscillator Fail Detection
9-4
intel .
87C51GB HARDWARE DESCRIPTION
PO.O- PO.7
v~
- - - - - - - - - - - - - - <'-"....1..-'.................
Vss I
~
SF'Rs
nMERs
P.C.A
P.CA.l
SERIAL PORTS
. PSEN
ALE/PROG
EA/Vpp
RESfi'
r-~"--1--'-TRIGIN
COMPREF
AVREF'
......rr.Ir'%T"'r-.AVSS
A
P1.0-Pl.7
P4.0- P4.7
P5.0-P5.7
P3.0-P3.7
C
H
-+
o
A
C
H
7
270897-1
Figure 1. 87C51GB Block Diagram
which are generally referred to as the Lower 128, the
Upper 128, and SFR space. The Upper 128 bytes occupy a parallel address space to the Special Function Registers. That means they have the same addresses, but
they are physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of data RAM or to SFR space by
the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For
example,
The Lower 128 bytes of RAM are present in all
MCS~51 devices. All of the bytes in the Lower 128 can
be accessed by either direct or indirect addressing. The
lowest 32 bytes are grouped into 4 banks of 8 registers.
Program instructions call out these registers as RO
through R7. Two bits in the Program Status Word
(pSW) select which register bank is in use. This allows
more efficient use of code space, since register instructions are shorter than instructions that use direct addressing.
MOV OAOH, data
accesses the SFR at location OAOH (which is P2). Instructions that use indirect addressing access the upper
128 bytes of data RAM. For example,
MOV @RO, data
9-5
inteL
87C51GB HARDWARE DESCRIPTION
where RO containsOAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
latches, timers, peripheral controls, etc. These registers
can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bit-addressable.
The bit-addressable SFRs are those whose address ends
in OOOB. The bit addresses in this area are 80H through
OFFH.
3.0 SPECIAL FUNCTION REGISTERS
Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses
to these addresses will in general return random data,
and write accesses will have no effect.
A map of the on-chip memory area called by the SFR
(Special Function Register) space is shown in Table 1.
Special Function Registers (SFRs) include the Port
Table 1. SFR Mapping and Reset Values
F8
FO
E8
EO
D8
DO
C8
co
S8
so
A8
AO
98
90
88
80
P5
00000000
*S
00000000
C1CON
00000000
'ACC
00000000
CCON
OOXOOOOO
'PSW
00000000
T2CON
00000000
P4
00000000
*IP
XOOOOOOO
*P3
11111111
'IE
00000000
'P2
00000000
'SCON
00000000
'P1
00000000
'TCON
00000000
'PO
11111111
CH
CCAPOH CCAP1H CCAP2H
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
AD7
00000000
CL
CCAPOL
CCAP1L
CCAP2L
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
AD6
00000000
CMOD
CCAPMO .CCAPM1
CCAPM2
OOXXXOOO XOOOOOOO XOOOOOOO XOOOOOOO
AD5
00000000
T2MOD
RCAP2L
RCAP2H
TL2
XXXXXXOO 00000000 00000000 00000000
AD4
00000000
SADEN C1CAPOH C1CAP1H C1CAP2H
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
AD3
00000000
SADDR
C1CAPOL C1CAP1L C1CAP2L
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
AD2
00000000
*SSUF C1CAPMO C1CAPM1 C1CAPM2
XXXXXXXX XOOOOOOO XOOOOOOO XOOOOOOO
AD1
00000000
*TMOD
'TLO
'TL1
'THO
00000000 00000000 00000000 00000000
'SP
'DPL
"DPH
ADO
00000111 00000000 00000000 00000000
. .
CCAP3H CCAP4H
XXXXXXXX XXXXXXXX
SEPSTAT
F7
XXXXXOOO
CCAP3L
CCAP4L
XXXXXXXX XXXXXXXX
X
=
Undefined.
9-6
EF
SEPDAT E7
XXXXXXXX
CCAPM3 CCAPM4
XOOOOOOO XOOOOOOO
DF
SEPCON
XXOOOOOO D7
TH2
00000000
C1CAP3H
XXXXXXXX
IPAH
00000000
C1CAP3L
XXXXXXXX
OSCR
XXXXXXXO
C1CAPM3
XOOOOOOO
CF
EXICON
XOOOOOOO
C1CAP4H
XXXXXXXX
IPA
00000000
C1CAP4L
XXXXXXXX
WDTRST
XXXXXXXX
C1CAPM4
XOOOOOOO
'TH1
00000000
• = Found In the 8051 core (see 8051 Hardware DeSCription for explanations of these SFRs) .
= See description of PCON SFR. Bit PCON.4 is not affected by reset.
"*
FF
ACMP
00000000
CH1
00000000
IPH
XOOOOOOO
CL1
00000000
lEA
00000000
C1MOD
XXXXOOOO
ACON
XXOOOOOO
C7
SF
S7
AF
A7
9F
97
8F
"PCON"
OOXXOOOO 87
intel .
87C51GB HARDWARE DESCRIPTION
User software should not write l's to these unimplemented locations, since they may be used in future
MCS-Sl products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be 1.
Ports 0 to 5 Registers: PO, PI, P2, P3, P4, and PS are
the SFR latches of Ports 0 through S respectively.
Timer Registers: Register pairs (THO, TLO), (THI,
TLI) and (TH2, TL2) are the 16-bit count registers for
Timer/Counters 0, I, and 2 respectively. Control and
status bits are contained in registers TCON and TMOD
for Timers 0 and I and in registers T2CON and
T2MOD for Timer 2. The register pair (RCAP2H,
RCAP2L) are the capture/reload registers for Timer 2
in 16-bit capture mode or 16-bit auto-reload mode.
The functions of the SFRs are outlined below. More
information on the use of specific SFRs for each peripheral is included in the description of that peripheral.
Accumulator: ACC is the Accumulator register. The
mnemonics for Accumulator-Specific instructions,
however, refer to the Accumulator simply as A.
Programmable Counter Array (PCA and PCAl) Registers: The 16-bit PCA and PCAI timer/counters consist
of register CH (CHI) and CL (CLI). Registers CCON
(CICON) and CMOD (CIMOD) contain the control
and status bits for the PCA (and PCAI). The
CCAPMn (n = 0, I, 2, 3, or 4) and the CICAPMn
registers control the mode for each of the five PCA and
the five PCAI modules. The register pairs (CCAPnH,
CCAPnL and CICAPnH, CICAPnL) are the 16-bit
compare/capture registers for each PCA and PCAI
module.
B Register: The B register is used during multiply and
divide operations. For other instructions it can be treat-.
ed as another scratch pad register.
Stack Pointer: The Stack Pointer Register is S bits
wide. It is incremented before data is stored during
PUSH and CALL executions. The stack may reside
anywhere in on-chip RAM. On reset, the Stack Pointer
is initialized to 07H causing the stack to begin at location OSH.
Serial Port Registers: The Serial Data Buffer, SBUF, is
actually two separate registers: a transmit buffer and a
receive buffer register. When data is moved to SBUF, it
comes from the receive buffer. Register SCON contains
the control and status bits for the Serial Port. Registers
SADDR and SADEN are used to define the Given and
the Broadcast addresses for the Automatic Address
Recognition feature.
Data Pointer: The Data Pointer (DPTR) consists of a
high byte (DPH) and a low byte (DPL). Its intem;led
function is to hold a 16-bit address, but it may be manipulated as a 16-bit register or as two independent
S-bit registers.
Program Status Word: The PSW register contains program status information as detailed in Table 2.
Table 2. PSW: Program Status Word Register
Address = ODOH
Bit Addressable
PSW
Bit
Reset Value = 0000 OOOOB
CY
AC
FO
7
6
5
I RS1 I RSO I OV
4
3
Symbol
Function
CY
AC
FO
RS1
RSO
Carry flag.
Auxiliary Carry flag. (For BCD Operations)
Flag O. (Available to the user for general purposes).
Register bank select bit 1.
Register bank select bit O.
RS1
o
o
OV
P
RSO
o
1
o
2
Working Register Bank and Address
Bank 0
(OOH-07H)
Bank 1
(OBH-OFH)
Bank 2
(10H-17H)
Bank 3
(1BH-1 FH)
P
o
1
Overflow flag.
User definable flag.
Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number
of "one" bits in the Accumulator, i.e., even parity.
9-7
87C51GB HARDWARE DESCRIPTION
channels 0 through 7 respectively. The register ACMP
contains the results of the AID comparison feature.
ACON is the control register for AID conversions.
Serial Expansion Port Registers: The Serial Expansion
Port is controlled through the register SEPCON.
SEPDAT contains data for the Serial Expansion Port
and SEPSTAT is used to monitor its status.
Power Control Register: PCON controls the Power Reduction Modes, Idle and Power Down.
Interrupt Registers: The individual interrupt enable
bits are in the IE and lEA registers. One of four priority levels can be selected for each interrupt using the IP,
IPH, IPA and IPAH registers. The EXICON register
. controls the selection of the activation polarity for external interrupts two and three.
Oscillator Fail Detect Register: The OSCR register is
used both to monitor the status of the OFD circuitry
and to disable the feature.
Watchdog Timer Register: The WatchDog Timer
ReSeT (WDTRST) register is used to keep the watchdog timer from periodically resetting the part.
Analog to Digital Converter Registers: The results of
AID conversions' are placed in registers ADO, ADl,
AD2, AD3, AD4, ADS, AD6, and AD7 for analog
Table 3. Alternate Port Functions
Port Pin
Alternate Function
PO.O/ ADO-PO.7 / AD7
Multiplexed Byte of Address/Data for external memory.
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEXO
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
Timer 2 External Clock Input/Clockout
Timer 2 Reload/Capture/Direction Control
PCA External Clock Input
PCA Module 0 Capture Input, Compare/PWM Output
PCA Module 1 Capture Input, Compare/PWM Output
PCA Module 2 Capture Input, Compare/PWM Output
PCA Module 3 Capture Input, Compare/PWM Output
PCA Module 4 Capture Input, Compare/PWM Output
P2.0/A8-P2.7/A15
High Byte of Address for External Memory
P3.0/RXD
P3.1/TXD
P3.2/INTO
P3.3/1NT1
P3.5/T1
P3.6/WR
P3.7/RD
Serial Port Input
Serial Port Output
External Interrupt 0
External Interrupt 1
Timer 0 External Clock Input
Timer 1 External Clock Input
Write Strobe for External Memory
Read Strobe for ,External Memory
P4.0/SEPCLK
P4.1/SEPDAT
P4.2/ECI1
P4.3/C1EXO
P4.4/C1EX1
P4.5/C1EX2
P4.6/C1EX3
P4.7/C1EX4
Clock Source for SEP
Data I/O for SEP
PCA1 External Clock Input
PCA1 Module 0, Capture Input, Compare/PWM Output
PCA 1 Module 1, Capture Input, Compare/PWM Output
PCA 1 Module 2, Capture Input, Compare/PWM Output
PCA1 Module 3, Capture Input, Compare/PWM Output
PCA1 Module,4, Capture Input, Compare/PWM Output
P5.2/INT2
P5.3/1NT3
P5.4/iNT4
P5.5/1NT5
P5.6/1NT6
External
External
External
External
External
P3.4/TO
Interrupt 2
Interrupt 3
Interrupt 4
Interrupt 5
Interrupt 6
NOTE:
The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port
pin will not go high.
.
.
9-8
int'et
87C51GB HARDWARE DESCRIPTION
4.0 1/0 PORTS
4.1 1/0 Configurations
All six ports in the 8XC5lGB are bidirectional. Each
consists of a latch (Special Function Register PO
through P5), output driver and an input buffer. All the
ports, except for Port 0, have Schmitt Trigger inputs.
Functional diagrams of a bit latch and I/O buffer in
each of the four ports are shown in Figure 2.
The bit latch (one bit in the port's SFR) is represented
as a Type D flip-flop, which clocks in a value from the
internal bus in response to a "write to latch" signal
from the CPU. The Q output of the flip-flop is placed
on the internal bus in response to a "read latch" signal
from the CPU. The level of the port pin itself is placed
on the internal bus in response to a "read pin" signal
from the CPU. Some instructions that read a port activate the "read latch" signal, and others activate the
"read pin" signal. Those that read the latch are the
Read-Modify-Write instructions.
The output drivers of Ports 0 and 2, 'and the input buffers of Port 0, are used in accesses to external memory.
In this application, Port 0 outputs the low byte of the
external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is 16
bits wide. Otherwise the Port 2 pins continue to emit
the P2 SFR content.
All the Port I, Port 3, Port 4 and most of Port 5 pins
are multi-functional. They are not only port pins, but
also serve the functions of various special features as
shown in Table 3.
The output drivers of Ports 0 and 2 are switchable to an
internal ADDRESS and ADDRESS/DATA bus by an
internal control signal for use in external memory accesses. During external memory accesses, the P2 SFR
ADDR/DATA
ALTERNATE
OUTPUT
FUNCTION
VCC
VCC
INTERNAL
PULL-UP*
INT. B;:.;U;:.;S,---+~
WRITE
TO
_---Ir'----.l
LATCH
WRITE
TO
LATCH
READ
PIN
270897-2
ALTERNATE
INPUT
FUNCTION
A. PortO Bit
270897-3
B. Port 1, 3, 4, or 5 Bit
ADDR
CONTROL
READ
LATCH
VCC
INT. BUS
WRITE
TO
LATCH
270897-4
c. Port 2 Bit
'See Figure 4 for details of the internal pullup.
Figure 2. 8XC51GB Port Bit Latches and I/O Buffers
9-9
87C51GB HARDWARE DESCRIPTION
remains unchanged, but the PO SFR gets I s written to
it.
If a PI through PS latch contains a I, then the output
level is controlled by the signal labeled "alternate output function." The pin level is always available to the
pin's alternate input function, if any.
Ports 1 through 5 have internal pullups. Port 0 has
open drain outputs. Each I/O line can be independently
used as an input or an output (ports 0 and 2 may not be
used as general purpose I/O when being used as the
ADDRESS/DATA BUS). To be used as an input, the
port bit latch must contain a 1, which turns off the
output driver FET. On Ports 1 through 5 the pin is
pulled high by the internal pullup, but can be pulled
low by an external source.
PI, P2, P4, and PS reset to a low state. While in reset
these pins can sink large amounts of current. If these
ports are to be used as inputs and externally driven
high while in reset, the user should be aware of possible
contention. A simple solution is to use open collector
interfaces with these port pins or to buffer the inputs.
Port 0 differs from the other ports in not having internal pUllups. The pullup FET in the PO output driver is
used only when the port is emitting Is during external
memory accesses. Otherwise the pullup FET is off.
Consequently PO lines that are being used as output
I
4/
port lines are open drain. Writing a I to the bit latch
leaves both output FETs off, which floats the pin and
allows it to be used as a high-impedance input. Because
Ports 1 through 5 have fixed internal pullups they are
sometimes called "quasi-bidirectional" ports.
When configured as inputs they pull high and will
source current (IlL in the data sheets) when externally
pulled low. Port 0, on the' other hand, is considered
"true" bidirectional, because it floats when configured
as an input.
The latches for ports 0 and 3 have Is written to them by
the reset function. If a 0 is subsequently written to a
port latch, it can be reconfigured as an input by writing
altoit.
'
4.2 Writing to a Port
In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch
during State 6, Phase 2 of the final cycle of the instruction. However, port latches are sampled by their output
buffers only during Phase 1 of any clock period. (During Phase 2 the output buffer holds the value it saw
during the previous Phase 1). Consequently, the new
value in the port latch won't actually appear at the
output pin until the next Phase 1, which will be at SIP 1
of the next machine cycle. Refer to Figure 3.
81
21
41
STATE STATE 5/ STATE
STATE 1 / STATE STATE 3/ STATE STATE 5/
~Ipz ~Ipz ~Ipz ~Ipz ~Ipz ~Ipz ~Ipz ~Ipz
XTAL1:
INPUTS SAMPLED:
MOV PORT, SAC:
n
PO,Pl,PZ, P3,P4,P5 ~
'Pl'PZ'P3,P4. P5
RST
RST=:r/.-
OLD DATA
NEW DATA
SERIAL PORT
SHIFT CLOCK
(MOOED)
-+l
I+- RXD PIN SAMPLED
Figure 3. Port Operation
9-10 .
RXD SAMPLED -+l,
I--
270897-5
inleL
87C51GB HARDWARE DESCRIPTION
For more information on internal timings refer to the
CPU Timing section.
4.3 Port Loading and Interfacing
The output buffers of Ports 1 through 5 can each sink
at least the amount of current specified by VOL in the
data sheet. These port pins can be driven by open-collector and open-drain outputs although O-to-I transitions will not be fast since there is little current pulling the pin up. An input 0 turns off pullup pFET2,
leaving only the very weak pullup pFET2 to drive the
transition.
If the change requires a O-to-I transition in Ports I
through 5, an additional pullup is turned on during
SIPI and SIP2 of the cycle in which the transition
occurs. This is done to increase the transition speed.
The extra pullup can source about 100 times the current that the normal pullup can. The internal pullups
are field-effect transistors, not linear resistors. The pullup arrangements are shown in Figure 4.
In external bus mode, Port 0 output buffers can each
sink the amount of current specified at the test conditions for VOLI in the data sheet. However, as port pins
they require external pull ups to be able to drive any
inputs.
The pullup consists of three pFETs. Note that an
n-channel FET (nFET) is turned on when a logical I is
applied to its gate, and is turned off when a logical 0 is
applied to its gate. A p-channel FET (pFET) is the
opposite: it is on when its gate sees a 0, and off when its
gate sees a 1.
See the latest revision of the data sheet for design-in
information.
pFET I is the transistor that is turned on for 2 oscillator periods after a O-to-I transition in the port latch. A
1 at the port pin turns on pFET3 (a weak pullup),
through the inverter. This inverter and pFET form a
latch which hold the 1.
4.4 Read-Modify-Write Instructions
Some instructions that read a port read the latch and
others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modify-write"
instructions. Listed on the following page, are the
read-modify-write instructions. When the destination
If the pin is emitting a I, a negative glitch on the pin
from some external source can turn off pFET2, causing
the pin to go into a float state. pFET2 is a very weak
pullup which is on whenever the nFET is off, in traditional CMOS style. It's only about '/10 the strength of
pFET2. Its function is to restore a 1 to the pin in the
event the pin had a I and lost it to a glitch.
Vcc
Vcc
Vcc
<5
FROM PORT
LATCH
INPUTo-_ _'C
DATA
READ
PORT PIN
270897-6
NOTE:
CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q mades a O-to-1 transition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is also on. Port 2 is similar except
that it holds the strong pullup on while emitting 1s that are address bits. (See text, "Accessing External Memory".)
Figure 4. Ports 1, 3, 4, and 5 Internal Pullup Configuration
9-11
int'et
87C51GB HARDWARE DESCRIPTION
operand is a port, or a port bit, these instructions read
the latch rather than the pin:
ANL
(logical AND, e.g. ANL PI, A)
ORL
(logical OR, e.g. ORL P2, A)
XRL
(logical EX-OR, e.g. XRL P3, A)
JBC
Gump if bit = I and clear bit, e.g. mc
Pl.l, LABEL)
CPL
(complement bit, e.g. CPL P3.0)
INC
(increment, e.g. INC P2)
DEC
(decrement, e.g. DEC P2)
DJNZ
(decrement and jump if not zero, e.g.
DJNZ P3, LABEL)
MOV px.y, C (move carry bit to bit Y of Port X)
CLR PX.Y
(clear bit Y of Port X)
SETB PX.Y
(set bit Y of Port X)
They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.
The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the
pin. For example, a port bit might be used to drive the
base of a transistor. When a I is written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
correct value of I.
4.5 Accessing External Memory
Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory
use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use RD or
WR (alternate functions ofP3.7 and P3.6) to strobe the
memory. Refer to Figures 5 through 7.
It is not obvious that the last three instructions in this
list are read-modify-write instructions, but they are.
'1 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE' ISTATE 21
ISTATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAL1:
ALE:
P2:
PCH OUT
PCH OUT
PCH OUT
270897-7
Figure 5. External Program Memory Fetches
9-12
int:eL
87C51GB HARDWARE DESCRIPTION
41 STATE 51 STATE 61 STATE ISTATE 21 STATE 31 STATE 41 STATE 51
ISTATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
1
XTAll:
ALE:
PCl OUT IF
PROGRAM MEMORY
RO:
PO:
P2:
PCH OR
P2 SFR
DPH OR P2 SFR OUT
PCH OR
P2 SFR
270897-8
Figure 6. External Data Memory Read Cycle
41 STATE 51 STATE 61 STATE 1 ISTATE 21 STATE 31 STATE 41 STATE 51
ISTATE
~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~ ~I~
XTAll:
ALE:
WR:
PO:
P2
DATA OUT
PCH OR
P2 SFR
DPH OR P2 SFR OUT
PCH OR
P2 SFR
270897-9
Figure 7. External Data Memory Write Cycle
9-13
int:eL
87C51GB HARDWARE DESCRIPTION
Fetches from external Program Memory always use a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOYX @ DPTR) or an
S-bit address (MOYX @ Ri).
Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for· the
duration of the read or write cycle. The Port 2 drivers
use the strong pullups during the entire time that they
are emitting address bits that are Is. This occurs when
the MOYX @ DPTR instruction is executed. During
this time the Port 2 latch (the Special Function Register) does not have to contain lSi and the contents of the
Port 2 SFR are not modified. If the external- memory
cycle is not immediately followed by another external
memory cycle, the undisturbed contents of the Port 2
SFR will reappear in the next cycle.
function and may not be used for general purpose I/O.
During external program fetches they output the high
byte of the PC with the Port 2 drivers using the strong
pullups to emit bits that are Is.
5.0 TIMER/COUNTERS
The SXC51GB has three 16-bit Timer/Counters: Timer 0, Timer I, and Timer 2. Each consists of two S-bit
registers: THx and TLx with x = 0, I, or 2. All three
can be configured to operate either as timers or event
counters.
In the Timer function, the TLx register is incremented
every machine cycle. Thus, you can think of it as counting machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1;12 of the oscillator
frequency.
If an S-bit address is being used (MOYX @ Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. In this case,
Port 2 pins can be used to page the external data memory.
In the Counter function, the register is incremented in
response to a I-to-O transition at its corresponding external input pin: TO, T I, or T2. In this function, the
external input is sampled during S5P2 of every machine
cycle. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. The
new count value appears in the register during S3PI of
the cycle following the one in which the transition was
detected. Since it takes 2 machine cycles (24 oscillator
periods) to recognize a I-to-O transition, the maximum
count rate is 1;24 of the oscillator frequency. There are
no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at
least once before it changes, it should be held for at
least one full machine cycle.
In either case, the low byte of the address is time-multiplexed with the data byte on Port O. The ADDRESS/
DATA signal drives both FETs in the Port 0 output
buffers. Thus, in external bus mode the Port 0 pins are
not open-drain outputs and do not require external
pullups. The ALE (Address Latch Enable) signal
should be used to capture the address byte into an external latch. The address byte is valid at the negative
transition of ALE. Then, in a write cycle, the data byte
to be written appears on Port 0 just before WR is activated, and remains there until after WR is deactivated.
In a read cycle, the incomin0te is accepted at Port 0
just before the read strobe (RD) is deactivated.
Timer 0 and Timer I have four operating modes:
Mode 0: 13-bit timer
Mode I: 16-bit timer
Mode 2: S-bit auto-reload timer
Mode 3: Timer 0 as two separate S-bit timers
During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register), thus obliterating the information in the Port 0
SFR. Also, a MOY PO instruction must not take place
during external memory accesses. If the user writes to
Port 0 during an external memory fetch, the incoming
code byte is corrupted. Therefore, do not write to Port
o if external program memory is used.
Also, its possible to use Timer I to generate baud rates.
Timer 2 has three modes of operation:
Timer 2 Capture
Timer 2 Auto-Reload (up or down counting), and
Timer 2 as a Baud Rate Generator
External Program Memory is accessed under two conditions:
1. Whenever signal EA is high, or
2. Whenever the program counter (PC) contains an address greater than IFFFH (SK).
5.1 Timer 0 and Timer 1
This requires that the ROMless versions have EA wired
to Yss to enable the lower SK of program bytes to be
fetched from external memory.
The Timer/Counter function is selected by control bits
C_Tx in TMOD (Table 4). These two Timer/Counters have four operating modes, which are selected by
bit-pairs (MIx, MOx) also in TMOD. Mode 0, Mode I,
and Mode 2 are the same for both Timer/Counters.
Mode 3 operation is different for the two timers.
When the CPU is executing out of external Program
Memory, all S bits of Port 2 are dedicated to an output
9-14
intel .
87C51GB HARDWARE DESCRIPTION
Table 4. TMOD: Timer/Counter Mode Control Register
TMOD
Address = S9H
Reset Value = 0000 OOOOB
Not Bit Addressable
TIMER 1
Bit
I GATE I
CIT
7
6
I
M1
TIMER 0
I
MO
GATE
CIT
I
M1
I
MO
I
320
4
5
I
Symbol
Function
GATE
Gating control when set. Timer/Counter 0 or 1 is enabled only while INTO or INT1 pin
is high and TRO or TR1 control pin is set. When cleared, Timer 0 or 1 is enabled
whenever TRO or TR1 control bit is set.
Timer or Counter Selector. Clear for Timer operation (input from internal system
clock). Set for Counter operation (input from TO or T1. .input pin).
CIT
M1
MO
0
o
o
Operating Mode
S-bit Timer/Counter. THx with TLx as 5-bit prescaler.
1
16-bit Timer/Counter. THx and TLx are cascaded; there is no prescaler.
OS-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx
each time it overflows.
(Timer 0) TLO is an S-bit Timer/Counter controlled by the standard Timer 0 control
bits. THO is an S-bit timer only controlled by Timer 1 control bits.
(Timer 1) Timer/Counter stopped.
As the count rolls over from all Is to alIOs, it sets the
timer interrupt flag TFO or TF1. The counted input is
enabled to the timer when TRO or TRI = I, and either
GATEx = 0 or INTx pin = 1. (Setting GATEx = 1
allows the Timer to be controlled by external input
INTx pin, to facilitate pulse width meaSurements).
MODE 0
Either Timer 0 or Timer 1 in Mode 0 is an 8-bit counter
with a divide-by-32 prescaler. In this mode, the Timer
register is configured as a 13-bit register. Figure 8
shows the Mode 0 operation for either timer.
CIT = 0
INTERRUPT
Tx PIN
_____-...1- CIT =
1
CONTROL
OVERFLOW
270897-10
Figure S. Timer/Counter 0 or 1 in Mode 0: 13-81t Counter
9-15
87C51GB HARDWARE DESCRIPTION
TRx and TFx are control bits in the SFR TCON. The
GATEx bits are in TMOD. There are two different
GATE bits: one for Timer I (TMOD.7) and one for
Timer 0 (TMOD.3).
MODE 1
Mode 1 is the same as Mode 0, except that the Timer
register uses alII6-bits. In this mode, THx and TLx are
cascaded; there is no prescaler. Refer'to Figure 9.
The 13-bit register consists of all 8 bits of THx and the
lower 5 bits of TLx. The upper 3 bits of TLx are indeterminate and should be ignored. Setting the run flag
(TRx) does not clear these registers.
As the count rolls over from all Is to all Os, it sets the
timer interrupt flag TFO or TF1. The counted input is
enabled to the timer when TRO or TRI = I, and either
GATEx = 0 or INTx pin =1. (Setting GATEx = 1
Table 5. TCON:. Timer/Counter Control Register
TCON
Address =
aaH
Reset = 0000 OOOOB
Bit Addressable·
I
Bit
Symbol
TF1
TR1
TFO
TRO.
IE1
IT1
lEO
ITO
TF1
7.
I
TR1
TFO
6
5
I
TAO
4
I
IE1
IT1
3
2
I
lEO liTO
I
0
Function
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine.
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
Timer 0 overflow Flag. Set by hardware on Timer/Counter 0 overflow. Cleared by hardware
when processor vectors to interrupt routine.
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
Interrupt 1 flag. Set by hardware when external interrupt 1 edge is detected (transmitted or
level-activated). Cleared when interrupt processed only if transition-activated.
Interrupt 1 Type control bit. ·Set/cleared by software to specifiy falling edge/low level triggered
external interrupt 1.
Interrupt 0 flag: Set by hardware when external interrupt 0 edge is detected (transmitted or
level-activated). Cleared when interrupt processed only if transition-activated.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupt O.
clf: 0
THx
TxPIN
_____---'1- cif:
1
CONTROL
INTERRUPT
TLx
OVERFLOW
270897-11
Figure 9. Timer/Counter 0 or 1 In Mode 1: 16-Blt Counter
9-16
intel~
87C51GB HARDWARE DESCRIPTION
allows the Timer to be controlled by external input
INTx pin to facilitate pulse width measurements).
(Setting GATEx = 1 allows the Timer to be controlled
by external input INTx pin, to facilitate pulse width
measurements).
TRx and TFx are control bits in the SRF TCON. The
GATEx bits are in TMOD. There are two different
GATE bits: one for Timer 1 (TMOD.7) and one for
Timet 0 (TMOD.3).
TRx and TFx are control bits in the SFR TCON. The
GATEx bits are in TMOD. There are two different
GATE bits: one for Timer 1 (TMOD.7) and one for
Timer 0 (TMOD.3).
MODE 2
MODE 3
Mode 2 configures the Timer register as an 8-bit Counter (TLx) with automatic reload as shown in Figure 10.
Overflow from TLx not only sets TFx, but also reloads
TLx with the contents of THx, which is preset by software. The reload leaves THx unchanged.
Timer 1 in Mode 3 simply holds its count. The effect is
the same as setting TRI = O.
Timer 0 in Mode 3 establishes TLO and THO as two
separate counters. TLO uses the Timer 0 control bits:
C_TO, GATEO, TRO, and TFO. THO is locked into a
The counted input is enabled to the timer when TRO or
TRI = I, and either GATEx = 0 or INTx pin = I.
ciT
~ 0
INTERRUPT
TxPIN
_____---'t CiT ~
1
-
TRx-----f
GATE
INTx PIN
270897-12
Figure 10. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload
osc
~G--
l/l210SC
l/l210SC - - - - - - - - ,
INTERRUPT
TO PIN - - - - - - - - '
CONTROL
l/l210S C
OVERFLOW
----+-11 I .\ (~~) ~INTERRUPT
TRl
1r~CONTROL
_ _________
-
OVERFLOW
270897-13
Figure 11. Timer/Counter 0 Mode 3: Two 8-Bit Counters
9-17
int:el.,
87C51GBHARDWARE DESCRIPTION
timer function (counting machine cycles) and takes
over the use of TRI and TFI from Timer 1. Thus THO
now controls the Timer 1 interrupt. The logic for Mode
3 on Timer 0 is shown in Figure 11.
Timer 2 Auto-Reload (up or down counting), and
Timer 2 as a Baud Rate Generator.
The modes are also selected by bits in T2CON as
shown in Table 6.
Mode 3 is provided for applications requiring an extra
8-bit timer or counter. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of
and into' its own Mode 3, or can still be used by the
serial port as a baud rate generator, or in any application not requiring an interrupt.
Table 6. Timer 2 Operating Modes
RCLK
5.2 Timer 2
Timer 2 is a 16-bit Timer/Counter which can operatCl
either as a timer or as an event counter. This is selected
by bit C_T2 in the SFR T2CON (Table 7). It has the
following three operating modes:
Timer 2 Capture,
+ TCLK
CP/RL2 T2·0E TR2
0
0
0
1
0
1
0
1
1
X
X
1
X
0
1
1
X
X
X
0
Mode
16·Bit
Auto-Reload
16-Bit
Capture
Baud_Rate
Generator
Clock-Out
on Pl.0·
Timer Off
·Present only on the 67C51 Fe.
Table 7. T2CON: Timer/Counter 2 Control Reglst~r
T2CON
Reset Value = 0000 OOOOB
Address = OC8H
Bit Addressable
TF2
EXF2
RCLK
7
6
5
Bit
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
TCLK I EXEN21
3
4
TR2
2
C/T2 ICP/RL21
o
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not
be set when either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on
T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled EXF2 = 1 will cause the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not
cause an interrupt in up/down counter mode (DCEN = 1).
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for
the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used
for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 .
causes Timer 2 to ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select, (Timer 2)
o = Internal timer (OSC/12 or OSC/2 in baud rate generator mode.)
1 = External event counter (falling edge triggered).
Capture/Reload flag. When set, captures will occur on negative transition at T2EX if EXEN2
= 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative
transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overflow.
9-18
intel .
87C51GB HARDWARE DESCRIPTION
The T2 Pin has /iIlother alternate function on the
87C51GB. It can be configured as a Programmable
Clock Out.
addition, the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can generate
an interrupt. Figure 12 illustrates this.
TIMER 2 CAPTURE MODE
TIMER 2 AUTO-RELOAD
(UP OR DOWN COUNTER)
In the capture mode there are two options selected by
bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a
16-bit timer on counter which, upon overflow, sets bit
TF2 in T2CON. This bit can then be used to generate
an interrupt. If EXEN2 = I, Timer 2 still does the
above, but with the added feature that a I-to-O transition at external input T2EX causes the current value
in the Timer 2 registers (TH2 and TL2) to be captured
into registers RCAP2H and RCAP2L, respectively. In
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature
is invoked by a bit named DCEN (Down Counter Enable) located in the SFR T2MOD (see Table 8). Upon
reset the DCEN bit is set to 0 so that Timer 2 will
default to count up. When DCEN is set, Timer 2 can
c?unt up or down depending on the value of the.(2EX
pm.
TH2
_
-+
T2 PIN I:r----'
cjf2 =
TL2
1
TR2
CAPTURE
TIMER 2
INTERRUPT
TRANSITION
DETECTION
T2EX PIN
EXEN2
270897-14
Figure 12. Timer 21n Capture Mode
Table 8. T2MOD: Timer 2 Mode Control Register
Address = OC9H
T2MOD
Reset Value
=
XXXX XXOOB
Not Bit Addressable
Bit
7
6
5
4
3
2
o
Symbol
Function
T20E
DECN
Not implemented, reserved for future use.·
Timer 2 Output Enable bit.
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down
counter
·User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
9-19
intel .
87C51GB HARDWARE DESCRIPTION
In the auto-reload mode with DCEN = 0, there are
two options selected by bit EXEN2 in T2CON. If
EXEN2 = 0, Timer 2 counts up to OFFFFH and then
sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit
value in RCAP2H and RCAP2L. The values in
RCAP2H and RCAP2L are preset by software. If
EXEN2 = I, a 16-bit reload can be triggered either by
an overflow or by a. I-to-O transition at external input·
T2EX. This transition also sets the EXF2 bit. Either
the TF2 or EXF2 bit can generate the Timer 2 interrupt if it is enabled. Figure 13 shows timer 2 automatically counting up when DCEN = O.
_
+ cjT2 -
T2 PIN [J-----'
Setting the DCEN bit enables Timer 2 to count up or
down as shown in Figure 14. In this, mode the T2EX
pin controls the direction of count. A logic 1 at T2EX
makes Timer 2 count up. The timer will overflow at
OFFFFH and set the TF2 bit which can then generate
an interrupt if it is enabled. This overflow also causes
the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. Now
the timer underflows when TH2 and TL2 equal the
values stored in RCAP2H and RCAP2L. The under-
1
TR2
TRANSITION
DETECTION
TIMER 2
INTERRUPT
T2EX PIN
EXEN2
27D897-15
Figure 13. Timer 2 Auto Reload Mode (DCEN
=
0)
(DOWN COUNTING RELOAD VALUE)
TOGGLE
_ + Cm-1
T2 PINQ--'
COUNT
DIRECTION
1 UP
0= DOWN
=
(UP COUNTING RELOAD VALUE)
270897-16
Figure 14. Timer 2 Auto Reload Mode (DCEN
9-20
=
1)
inteL
87C51GB HARDWARE DESCRIPTION
flow sets the TF2 bit and causes OFFFFH to be reload·
ed into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows. This bit can be used as a 17th bit ofresolu·
tion if desired. In this operating mode, EXF2 does not
generate an interrupt.
. To configure the Timer/Counter 2 as a clock generator,
bit C_T2 (in T2CON) must be cleared and bit T20E
(in T2MOD) must be set. Bit TR2 (in T2CON) also
must be set to start the timer.
The Clock Out frequency depends on the oscillator fre·
quency and the reload value of Timer 2 capture regis·
ters (RCAP2H, RCAP2L) as shown in this equation:
5.3 Programmable Clock Out
Clock Out _
Oscillator Frequency
Frequency - 4 x [65536 - (RCAP2H. RCAP2Ll]
The 87C51GB has a new feature. A 50% duty cycle
clock can be programmed to come out on P1.0. This
pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed (1) to input the exter·
nal clock for Timer/Counter 2, or (2) to output a 50%
duty cycle clock ranging from 61 Hz to 4 MHz at a
16 MHz operating frequency. Figure 15 shows Timer 2
in clock·out mode.
In the Clock Out mode, Timer 2 roll·overs wi:
generate an interrupt. This is similar to when it is used
as a baud·rate generator. It is possible to use Timer 2 as
a baud·rate generator and a clock generator simulta·
neously. Note, however, that the baud·rate and the
clock·out frequency will be the same.
PLO
(12)
T20E (12t.l00. 1)
EXEN2
270897-17
Figure 15. Timer 2 in Clock-Out Mode
9-21
int:et
87C51GB HARDWARE DESCRIPTION
6.0 AID CONVERTER
Table 9. AID SFRs
The A/D converter on the 8XC51GB consists of: 8
analog inputs (ACHO-ACH7), an external trigger input (TRIGIN), separate analog voltage supplies (AVss
and AVREP), a comparison reference input
(COMPREF) and internal circuitry. The internal circuitry includes: an 8 channel multiplexer, a 256 element
resistive ladder, a comparator, sample-and-hold capacitor, successive approximation register, A/D trigger
control, a comparison result register and 8 AID result
registers as shown in the A/D block diagram, Figure
16.
(MSB)
I :
:
:
:
:
:
(MSB)
1- : -
:
(LSB)
.
tDO ... AD7
OB4H ... OF4H
(LSB) ACON
: AIF : ACE : ACS1 : ACSO: AIM: ATM I097H
(MSB)
(LSB)
EMP O:CMP 1 :CMP 2:CMP 3:CMP 4:CMP S:CMP S:CMP
7!;~~:
ADO through AD7 contain the results of the 8 analog
conversion. Each SFR is updated as each conversion is
complete, starting with the lowest channel and ending
with channel 7.
AVREP must be held within the tolerances stated on
the 8XC51GB data sheet. The accuracy of the AID
cannot be improved, for instance, by tying AVREP to
'I. the voltage on Vee.
ACMP is the comparison result register. ACMP is organized differently than all the other SFRs in that
CMPO occupies the MSB and CMP7 the LSB. CMPO
6.1 AID Special Function Registers
The A/D has 10 SFRs associated with it. The SFRs are
shown in Table 9.
CONTINUOUS
---"'6
r-----
1+--+- TRIGIN
.---~===--l- AVREF
ATM
. - - - - -_ _- -....-
.--------.
._------_.
A TO 0
..--------.
_------_.
8
0
0
: ADO RESULT
••
•
: ADS RESULT
.--------.
._------_.
: AD7 RESULT
AIF
.--------.
: ACMP RESULT
._------_.
(Trigger In)
CONVERSION ENABLE (ACE)
MUX
II
I I
ACSO
ACSl
LADDER
........
ACHO
•
•
•
ACH7
SCAN/SELECT (AIM)
COMPREF
AVss
270897-18
Figure 16. AID Block Diagram
9-22
inteL
87C51GB HARDWARE DESCRIPTION
through CMP7 correspond to analog inputs 0 through
7. CMPn is set to a I if the analog input is greater than
COMPREF. CMPn is cleared if the analog input is less
than or equal to COMPREF.
edge is detected, the AID conversions begin on the next
machine cycle and complete when channel 7 is converted. After channel 7 is converted, AIF is set and the
conversions halt until another trigger is detected while
ACE= 1. External triggers are ignored while a conversion cycle is in progress.
ACON is the AID control register and contains the
AID Interrupt Flag (AIF), AID Conversion Enable
(ACE), AID Channel Select (ACSO and ACSI), AID
Input Mode (AIM), and AID Trigger Mode (ATM).
6.4 AID Input Modes
The 8XCSlGB has two input modes: Scan mode and
Select mode. Clearing AIM places the 8XCSIGB in
Scan mode. In Scan mode the analog conversions occur
in the sequence ACHO, ACHl, ACH2, ACH3, ACH4,
ACHS, ACH6, and ACH7. The result of each analog
conversion is placed in the corresponding analog result
register: ADO, AD!, AD2, AD3, AD4, ADS, AD6,
and AD7.
6.2 AID Comparison Mode
The AID Comparison mode is always active while the
AID converter is enabled. The Comparison mode is
used to compare each analog input against an external
reference voltage applied to COMPREF. Whenever the
AID converter is triggered, each bit in ACMP is updated as each analog conversion is completed, starting
with channel 0 up to channel 7 regardless of whether
Select or Scan mode is invoked. The comparison mode
can provide a quicker "greater-than or less-than" decision than can be performed with software and it is more
code efficient. It can also be used to convert the analog
inputs into digital inputs with a variable threshold. If
the comparison mode is not used, COMPREF should
be tied to Vee or Vss.
Setting AIM activates Select mode. In Select mode, one
of the lower 4 analog inputs (ACHO-ACH3) is converted four times. After the first four conversions are
complete the cycle continues with ACH4 through
ACH7. The results of the first four conversion are
placed in the lower four result registers (ADO through
AD3). The rest of the conversions are placed in their
'matching result register. ACSO and ACSI determine
which analog inputs are used as shown in Table 10.
6.3 AID Trigger Mode
Table 10. AID Channel Selection
The analog converter can be triggered either internally
or externally. To enable internal trigger mode, ATM
should be cleared.
When in internal trigger mode, AID conversions begin
in the machine cycle which follows the setting of the
ACE bit. The lowest channel (see "AID Input Modes"
below) is converted first, followed by all the other channels in sequence. The AIF flag is set upon completion
of the channel 7 conversion. AIF will flag an interrupt
if the AID interrupt is enabled. Once a conversion cycle is completed, a new cycle begins, starting with the
lowest channel. If the user wishes each channel to be
converted only once, the ACE bit should be cleared.
Clearing ACE stops all AID conversion activity. If a
new AID cycle begins, the result of the previous conversion will be overwritten.
ACS1
ACSO
0
0
1
1
0
1
0
1
Selected
Channel
ACHO
ACH1
ACH2
ACH3
6.5 Using the AID with Fewer than
. 81nputs
There are several options for a user who wishes to convert fewer than eight analog input channels. If time is
not critical the user can simply wait for the AID interrupt to be generated by the AIF bit after channel 7 is
converted and can ignore the results for unused channels. If a user needs to know the results of a conversion
immediately after it occurs, a timer should be used to
generate an interrupt. The amount of time required for
each AID conversion is specified in the 8XCSIGB data
sheet. The user could also periodically poll the result
registers, provided he or she is looking only for a
change in the analog voltage. Using the Select mode
(see above) does not reduce the time required for a conversion cycle but will convert a given channel more
frequently.
In external mode, the AID conversions begin when a
falling edge is detected at the TRIGIN pin. There is no
edge detector on the TRIGIN pin; is it sampled once
every machine cycle.
A negative edge is recognized when TRIGIN is high in
one machine cycle and low in the next. For this reason,
TRIGIN should be held high for at least one machine
cycle and low for one machine cycle. Once the falling
9-23
intel.,
87C51GB HARDWARE DESCRIPTION
6.6 AID in Power Down
Table 11. PCA and PCA 1 SFRs
PCA
The AID on the 8XC51GB contains circuitry that limits the amount of current dissipated during Power
Down mode to leakage current only. For this circuitry
to function properly, AVREF should be tied to Vee
during power down. The IpD specification in the data
sheet includes the current for the entire chip. While
A VREF is tied to Vee during Power Down, the voltage
may be reduced to the minimum voltage as shown in
the data sheet.
PCA1
SFRs:
CCON ...................... C1CON
CMOD ...................... C1MOD
CCAPMO ................... C1 CAPMO
CCAPM1 ................... C1CAPM1
CCAPM2 ................... C1 CAPM2
CCAPM3 ................... C1 CAPM3
CCAPM4 ................... C1 CAPM4
CL ......................... CL1
CCAPOL .................... C1 CAPOL
CCAP1 L .................... C1 CAP1 L
CCAP2L .................... C1 CAP2L
CCAP3L ..................... C1CAP3L
CCAP4L .................... C1CAP4L
CH ......................... CH1
CCAPOH .................... C1 CAPOH
CCAP1 H .................... C1 CAP1 H
CCAP2H .................... C1 CAP2H
CCAP3H .................... C1 CAP3H
CCAP4H .................... C1 CAP4H
7.0 PROGRAMMABLE COUNTER
ARRAY
Programmable Counter Arrays (PCAs) provide more
timing capabilities with less CPU intervention than the
standard timer/counters. Their advantag~s include reduced software overhead and improved accuracy. For
example, a PCA can provide better resolution than
Timers 0, I, and 2 because the PCA clock rate can be
three times faster. A PCA can also perform many tasks
that these hardware timers cannot (i.e. measure phase
differences between signals or generate PWMs).
BITS:
ECI ......................... ECI1
CEXO ....................... C1EXO
CEX1 ....................... C1EX1
CEX2 ....................... C1EX2
CEX3 ....................... C1EX3
CEX4 ....................... C1EX4
CCFO ....................... C1CFO
CCF1 ....................... C1CF1
CCF2 ....................... C1CF2
CCF3 ...... : ................ C1CF3
CCF4· ....................... C1CF4
CR ......................... CR1
CF ......................... CF1
The 8XC51GB has two PCAs called PCA and PCAI.
The following text and figures address only PCA but
are also applicable to PCAI with the following exceptions:
I. PCAI, Module 4 does not support the Watchdog
Timer
2. All the SFRs and bits have Is added to their names
(see Table II).
3. Port 4 is the interface for PCAI:
ECIl
P4.2
P4.3
CIEXI
P4.4
CIEX2
P4.5
CIEX2
P4.6
CIEX3
P4.7
CIEX4
16 BITS EACH
Pl.3/CEXO
P1.4/CEXl
16 BITS
PCA TIIolER/COUNTER t---+----,~
i.!OOULE 2
Pl.5/CEX2
P1.6/CEX3
Pl.7/CEX4
270897-19
Figure 17. PCA Block Diagram
9-24
int:eL
87C51GB HARDWARE DESCRIPTION
4. There has been one additional bit added to CICON
to allow both PCAs to be enabled simultaneously.
The bit is called CRE and occupies bit position 5 of
CICN. Its bit address is OEDH. When CRE is set,
both CR and CRI must be set to enable PCAI.
When the compare/capture modules are programmed
in the capture mode, software timer, or high speed output mode, an interrupt can be generated whenever the
module executes its function. All five modules plus the
PCA timer overflow share one PCA interrupt vector.
Each PCA consists of a l6-bit timer/counter and five
16-bit compare/capture modules as shown in Figure
17. The PCA timer/counter serves as a common time
base for the five modules and is the only timer which
can service the PCA. Its clock input can be programmed to count anyone of the following signals:
Oscillator frequency / 12
Oscillator frequency / 4
Timer 0 overflow
External input on ECI (PI.2).
The PCA timer/counter and compare/capture modules
share Port 1 pins for external I/O. These pins are listed
below. If the port pin is not used for the PCA, it can
still be used for standard I/O.
The compare/capture modules can be programmed in
anyone of the following modes:
rising and/or falling edge capture
software timer
high speed output
pulse width modulator.
PCA Component
External 1/0 Pin
16-bit Counter
16-bit Module 0
16-bit Module 1
16-bit Module 2
16-bit Module 3
16-bit Module 4
P1.2/
P1.3 /
P1.4 /
P1.5 /
P1.6 /
P1.7 /
ECI
CEXO
CEX1
CEX2
CEX3
CEX4
7.1 PCA Timer/Counter
The PCA has a free-running 16-bit timer/counter consisting of registers CH and CL (the high and low bytes
of the count value). These two registers can be read or
written to at any time. Reading the PCA timer as a full
16-bit value simultaneously requires using one of the
PCA modules in the capture mode and toggling a port
pin in software.
Module 4 can also be programmed as a watchdog
timer.
FOSC/12
FOSC/4
TII.IER a
OVERFLOW
EXTERNAL
INTERRUPT
INPUT
(ECI)
CIDL
PROCESSOR IN
IDLE MODE
270897-20
Figure 18. PCA Timer/Counter
9-25
infel"
87C51GB HARDWARE DESCRIPTION
The clock input can be selected from the following four
modes:
External Input:
The PCA timer increments when a I-to-O transition is
detected on the ECI pin (P1.2). The maximum input
frequency in this mode is oscillator frequency / 8.
Oscillator frequency 112:
The PCA timer increments once per machine cycle.
With a 16 MHz crystal, the timer increments every
750 ns.
The mode register CMOD (Table 12) contains the
Count Pulse Select bits (CPS! and CPSO) to specify the
clock input. This register also contains the ECF bit
which enables the PCA counter overflow to generate
the PCA interrupt. In addition, the user has the option
of turning off the PCA timer during Idle Mode by setting the Counter Idle bit (CIDL). This can further reduce power consumption by an additional 30%.
Oscillator frequency I 4:
The PCA timer increments three times per machine
cycle. With a 16 MHz crystal, the timer increments
every 250 ns.
The CCON (Table 13) register contains two more bits
which are associated with the PCA timer/counter. The
CF bit gets set by hardware when the counter overflows, and the CR bit is set or cleared to tum the counter on or off.
Timer 0 overflows:
The PCA timer increments whenever Timer 0 overflows. This mode allows a programmable input frequency to the PCA.
Table 12. CMOD: PCA Counter Mode Register
CMOD
Address = OD9H
Reset Value = OOXX XOOOB
Not Bit Addressable
CIDL
I WDTE I
7
6
Bit
I
5
4
CPS1
3
2
CPSO
ECF
o
Symbol Function
CIDL
WDTE
CPS1
CPSO
ECF
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
Not implemented, reserved for future use. •
PCA Count Pulse Select bit 1~
PCA Count Pulse Select bit o.
CPS1 CPSO Selected PCA Input"·
o
0
Internal clock, Fosc+ 12
o
1
Internal clock, Fosc + 4
1
0
Timer 0 overflow
External clock at ECI/P1.2 pin (max. rate == Fosc + 8)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
NOTE:
·User software should not write 1s to reserved bits. These bits may be used in future 8051 family productS to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
··Fosc = oscillator frequency'
9-26
infel .
87C51GB HARDWARE DESCRIPTION
Table 13. CCON: PCA Counter Control Register
CCON
Address = OD8H
Reset Value
= OOXO OOOOB
Bit Addressable
Bit
CF
CR
7
6
CCF4
CCF3
CCF2
4
3
2
5
CCF1
CCFO
o
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an
interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can
only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
Not implemented, reserved for future use'.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCFO
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
°NOTE:
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
READING THE PCA TIMER
7.2 Compare/Capture Modules
Some applications may require that the full 16-bit PCA
timer value be read simultaneously. Since the timer
consists of two 8-bit registers (CH, CL), it would normally take two MaY instructions to read the whole
timer value. An invalid read could occur if the registers
rolled over in between the execution of the two MaYs.
Each of the five compare/capture modules has six possible functions it can perform:
16-bit Capture, positive-edge triggered
16-bit Capture, negative-edge triggered
16-bit Capture, both positive and negative-edge
triggered
16-bit Software Timer
16-bit High Speed Output
8-bit Pulse Width Modulator.
However, with the PCA Capture Mode the l6-bit timer
value can be loaded into the capture registers by toggling a port pin. For example, configure Module 0 to
capture falling edges and initialize P1.3 to be high.
Then, when the user wants to read the PCA timer,
clear Pl.3 and the full 16-bit timer value will be saved
in the capture registers. It's still optional whether the
user wants to generate an interrupt with the capture.
In addition, module 4 can be used as a Watchdog Timer. The modules can be programmed in any combination of the different modes.
9-27
87C51GB HARDWARE DESCRIPTION
Each module has a mode register called CCAPMn
(n = 0, 1, 2, 3, or 4) to select which function it will
perform. The ECCFn bit enables the PCA interrupt
when a module's event flag is set. The event flags
(CCFn) are located in the CCON register and get set
when a capture event, software timer, or high speed
output event occurs for a given module.
7.3 PCA Capture Mode
Both positive and negative transitions can trigger a capture with the PCA. This gives the PCA the flexibility to
measure periods, pulse widths, duty cycles, and phase
differences on up to five separate inputs. Setting the
CAPPn and/or CAPNn bits in the CCAPMn mode
register (Table 14) selects the input trigger-positive
and/or negative transition-for module n. Refer to Figure 19.
Each module also has a pair of 8-bit compare/capture
registers (CCAPnH and CCAPnL) associated with it.
These registers store the time when a capture event occurred or when a compare event should occur. For the
PWM mode, the high byte register CCAPnH controls
the duty cycle of the waveform.
Table 15 shows the combinations of bits in the
CCAPMn register that are valid and have a defined
function. Invalid combinations will produce undefined '
results.
Table 14. CCAPMn: PCA Modules Compare/Capture Registers
CCAPMn Address
(n = 0-4)
CCAPMO
CCAPM1
CCAPM2
CCAPM3
CCAPM4
Not Bit Addressable
Bit
7
Reset Value = XOOO OOOOB
OOAH
OOBH
OOCH
OOOH
OOEH
IECOMn ICAPPn IcAPNnl
MATn
TOGn
5
3
2
6
4
I PWMn IECCFn I
0
Symbol Function
Not implemented; reserved for future use*.
ECOMn 'Enable COmparator. ECOMn = 1 enables the comparator function.
CAPPn
Capture Positive, CAPPn = 1 enables positive edge capture.
CAPNnCapture Negative, CAPNn = 1 enables negative edge capture.
MATn
Match. When MATn = 1, a match of the PCA counter with this module's compare/ capture
register causes the CCFn bit in CCON to be set, flagging an interrupt. "
TOGn
Toggle. When TOGn = 1, a match of the peA counter with this module's compare/capture
register causes the CEXn pin to toggle.
PWMn
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
ECCFn
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case,the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
9-28
87C51GB HARDWARE DESCRIPTION
Table 15. PCA Module Modes (CCAPMn Register)
-
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Module Function
X
0
0
0
0
0
0
0
No operation
X
X
1
0
0
0
0
X
16·bit capture by a postive·edge trigger on CEXn
X
X
0
1
0
0
0
X
16·bit capture by a negative·edge trigger on CEXn
X
X
1
1
0
0
0
X
16·bit capture by a transition on CEXn
X
1
0
0
1
0
0
X
16·bit Software Timer
X
1
0
0
1
1
0
X
16·bit High Speed Output
X
1
0
0
0
0
1
0
8-bitPWM
X
1
0
0
1
x
0
x
Watchdog Timer
x = Don't Care
-1----+
INTERRUPT
L.-....---,~
PCA
TIMER/COUNTER
CEXn
PIN
n = 0,1,2,3 or 4
x = Don'l Care
CCAPMn MODE REGISTER
270897-21
Figure 19. PCA 16-Bit Capture Mode
In the interrupt service routine, the 16-bit capture value
must be saved in RAM before the next capture event
occurs. A subsequent capture on the same CEXn pin
will write over the first capture value in CCAPnH and
CCAPnL.
The external input pins CEXO through CEX4 are sampled for a transition. When a valid transition is detected
(positive and/or negative edge), hardware loads the
16-bit value of the PCA timer (CH, CL) into the module's capture registers (CCAPnH, CCAPnL). The reSUlting value in the capture registers reflects the PCA
timer value at the time a transition was detected on the
CEXnpin.
The time it takes to service this interrupt routine determines the resolution of back-to-back events with the
same PCA module. To store two 8-bit registers and
clear the event flags takes at least 9 machine cycles.
That includes the call to the interrupt routine. At
12 MHz, tliis routine would take less than 10 ,""S. However, depending on the frequency and interrupt latency,
the resolution will vary with each application.
Upon a capture, the module's event flag (CCFn) in
CCON is set, and an interrupt is flagged if the ECCFn
bit in the mode register CCAPMn is set. The PCA. interrupt will then be generated if it is enabled. Since the
hardware does not clear an event flag when the interrupt is vectored to, the flag must be cleared in software.
9-29
87C51GB HARDWARE DESCRIPTION
7.4 Software Timer Mode
In most applications a software timer is used to trigger
interrupt routines which must occur at periodic intervals. The user preloads a 16-bit value in a module's
compare registers. When. a match occurs between this
compare value and the PCA timer value, an event nag
is set and an interrupt can then be generated.
In the PCA compare mode, the 16-bit value of the PCA
timer is compared with a 16-bit value pre-loaded in the
module's compare registers (CCAPnH, CCAPnL) as
seen in Figure 20. The comparison occurs three times
per machine cycle in order to recognize the fastest possible clock input (i.e. II. X oscillator frequency). Setting the ECOMn bit in the mode register CCAPMn
enables the comparator function.
For the Software Timer mode, the MATn bit also needs
to be set. When a match occurs between the PCA timer
and the compare registers, a match signal is generated
and the module's event flag (CCFn) is set. An interrupt
is then flagged if the ECCFn bit is set. The PCA interrupt is generated only if it has been properly enabled.
Software must clear the event flag before the next interrupt will be flagged.
During the interrupt routine, a new 16-bit compare value can be written to the compare registers (CCAPnH
and CCAPnL). Notice, however, that a write to
CCAPnL clears the ECOMn bit which temporarily disables the comparator function while these registers are
being updated so an invalid match does not occur. A
write to CCAPnH sets the ECOMn bit and re-enables
the comparator. For this reason, user software should
write to CCAPnL first, then CCAPnH.
-+---.......
INTERRUPT
PCA
TIMER/COUNTER
ENABLE
CCAPMn MODE REGISTER
RESET
WRITETO-....
CCAPnL
~
WRITE TO
CCAPnH
"1"
270B97-22
Figure 20. PCA 16-Blt Comparator Mode: Software Timer
9-30
intel .
87C51GB HARDWARE DESCRIPTION
Without any CPU intervention, the fastest waveform
the PCA can generate with the HSO mode is a 30.5 Hz
signal at 16 MHz.
7.5 High Speed Output Mode
The High Speed Output (HSO) mode toggles a CEXn
pin when a match occurs between the PCA timer and a
pre-loaded value in a module's compare registers. For
this mode, the TOGn bit needs to be set in addition to
the ECOMn and MATn bits in the CCAPMn mode
register. By setting or clearing the pin in software, the
user can select whether the CEXn pin will change from
a logical 0 to a logical 1 or vice versa. The user also has
the option of flagging 1m interrupt when a match event
occurs by setting the ECCFn bit. See Figure 21.
7.6 Watchdog Timer Mode
A Watchdog Timer is a circuit that automatically invokes a reset unless the system being watched sends
regular hold-off signals to the Watchdog. These circuits
are used in applications that are subject to electrical
noise, power glitches, electrostatic discharges, etc., or
where high reliability is required.
The HSO mode is more accurate than toggling port
pins in software because the toggle occurs before
branching to an interrupt. That is, interrupt latency
will not effect the accuracy of the output. In fact, the
interrupt is optional. Only if the user wants to change
the time for the next toggle is it necessary to update the
compare registers. Otherwise, the next toggle will occur
when the PCA timer rolls over and matches the last
. compare value.
.
The Watchdog Timer function is only available on
PCA Module 4. If a Watchdog Timer is not needed,
Module 4 can still be used in other modes.
As a Watchdog timer, every time the count in the PCA
timer matches the value stored in module 4's compare
registers, an internal reset is generated (see Figure 22).
The bit that selects this mode is WDTE in the CMOD
register. Module 4 must be set up in either compare
mode as a "Software Timer" or High Speed Output.
PCA
TIMER/COUNTER
CEXn PIN
ENABLE
CCAPMn MODE REGISTER
RESET -------......
WRITE TO
)----.
CCAPnL
WRITE TO
CCAPnH
"1"
270897-23
Figure 21_ PCA 16-Blt Comparator Mode: High Speed Output
9-31
87C51GB HARDWARE DESCRIPTION
I'
CCAP4H I CCAP4L
I
WOTE
PCA
- f - -.... RESET
TIMER/COUNTER
ENABLE
RESET
WRITE TO
CCAP4L
CCAPM4 MODE REGISTER
_-'i"-'"
>--....,
WRITE TO _ _--,
CCAP4H
"1"
270897-24
Figure 22. Watchdog Timer Mode
To hold off the reset, the user has three options:
1. periodically change the compare value so it will never match the peA timer,
2. periodically change the peA timer value so it will
never match the compare value,
3. disable the Watchdog by clearing the WDTE bit before a match occurs and then later re-enable it.
counter goes astray and gets stuck in an infinite loop,
interrupts will still be serviced, and the watchdog will
not reset the controller. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine
from the main program within 65536 counts of the
peA timer.
7.7 Pulse Width Modulator Mode
The first two options are more reliable because the
Watchdog Timer is never disabled as in option #3. The
second option is not recommended if other peA modules are being used since this timer is the time base for
all five modules. Thus, in most applications the first
solution is the best option.
Any or all of the five peA modules can be programmed to be a Pulse Width Modulator. The PWM
output can be used to convert digital data to an analog
signal by simple external circuitry. The frequency of the
PWM depends on the clock source for the peA timer.
With a 16·MHz crystal the maximum frequency of the
PWM waveform is 15.6 KHz. Table 16 shows the various frequencies that are possible.
The watchdog routine should not be part of an interrupt service routine. Why? Because if the program
9-32
intel®
87C51GB HARDWARE DESCRIPTION
Table 16. PWM Frequencies
PWM Frequency
PCA Timer Mode
12MHz
16MHz
1/12 Osc. Frequency
3.9 KHz
5.2 KHz
1/4 Osc. Frequency
11.8 KHz
15.6 KHz
Timer a Overflow:
8-bit
16-bit
8-bit Auto-Reload
15.5 Hz
0.06 Hz
3.9 KHz to 15.3 Hz
20.3 Hz
0.08 Hz
5.2 KHz to 20.3 Hz
External Input (Max)
5.9 KHz
7.8 KHz
The value in CCAPnL controls the duty cycle of the
waveform. To change the value in CCAPnL without
output glitches, the user must write to the high byte
register (CCAPnH). This value is then shifted by hardware into CCAPnL when CL rolls over from OFFH to
OOH which corresponds to the next period of the output.
For this mode, the ECOMn bit and the PWMn bits in
the CCAPMn mode register need to be set. The PCA
generates 8-bit PWMs by comparing the low byte of the
PCA timer (CL) with the low byte of the module's
compare registers (CCAPnL). When CL < CCAPnL
the output is low. When CL > CCAPnL the output is
high. Refer to Figure 23.
CL MADE
FF TO 00 ---~,
TRANSITION
"0"
CL
< CCAPnL
CL
~
CCAPnL
CEXn PIN
ENABLE
"1"
CCAPMn MODE REGISTER
270897-25
Figure 23. PCA 8-Bit PWM Mode
9-33
int'et
87C51GB HARDWARE DESCRIPTION
CCAPnH can contain any integer from 0 to 255 to vary
the duty cycle from a 100% to 0.4%. A 0% duty cycle
can be obtained by writing directly to the port pin with
the CLR bit instruction. To calculate the CCAPnH value for a given duty cycle, use the following equation:
the receive register. (However, if the first byte still
hasn't been read by the time reception of the second
byte is complete, one of the bytes will be lost).
CCAPnH = 256 x (1 - Duty Cycle)
where CCAPnH is an S-bit integer and Duty Cycle is /
expressed as a fraction. See Figure 24.
The serial port receive and transmit registers are both
accessed through Special Function Register SBUF. Actually, SBUF is two separate registers, a transmit buffer
and a receive buffer. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically
separate receive register.
The serial port control and status register is the Special
Function Register SCON (Table 17). This register contains the mode selection bits (SMO and SM1); the SM2
bit for the multiprocessor modes; the Receive Enable
bit (REN); the 9th data bit for transmit and receive
(TBS and RBS); and the serial port interrupt bits (TI
and RI).
8.0 SERIAL PORT
The serial port is full duplex, meaning it can transmit
and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from
9-34
infel~
87C51GB HARDWARE DESCRIPTION
Table 17. SCON: Serial Port Control Register
SCON
Reset Value
Address = 98H
=
OOOOOOOOB
Bit Addressable
I SMO/FE I SM1
Bit:
7
6
5M2
REN
TB8
RB8
5
4
3
2
TI
RI
o
(SMODO=0/1)*
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE
bit is not cleared by valid frames but should be cleared by software. The SMODO' bit must
be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMODO must = 0 to access SMO)
Serial Port Mode Bit 1
SMO SM1 Mode Description
Baud Rate"'
o
0
0
shift register
Fosc/12
o
1
1
8-bit UART
variable
1
0
0
9-bit UART Fosc/64 or FOSC/32
3
9-bit UART
variable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If 5M2 = 1 then RI
will not be set unless the received byte is a Given or Broadcast Address. In Mode 1,
if 5M2 = 1 then RI will not be activated unless a valid stop bit was received, and the
received byte is a Given or Broadcast Address. In Mode 0, 5M2 should be o.
Enables serial reception. Set by software to enable reception. Cleared by software to
disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1 if 5M2 = 0, RB8 is the stop
bit that was received. In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the
beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by
software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0 or halfway
through the stop bit time in the other modes, in any serial reception (except see 5M2).
Must be cleared by software.
SMO
SM1
5M2
REN
TB8
RB8
TI
RI
NOTE:
*SMODO
**Fosc
=
is located at peON6.
oscillator frequency
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other
modes by the incoming start bit if REN = 1.
The serial port can operate in 4 modes:
Mode 0: Shift Register, fixed frequency
Mode 1: 8-Bit UART, variable frequency
Mode 2: 9-Bit UART, fixed frequency
Mode 3: 9-Bit UART, variable frequency
Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at
1/12 the oscillator frequency.
The baud rate in some modes is fixed and in others is
generated by Timer 1 or Timer 2.
9-35
intel..
87C51GB HARDWARE DESCRIPTION
Mode 1: 10 bits are transmitted (through TXD) or re-·
ceived (through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes
into RB8 in SCON. The baud rate in Mode 1 is variable: you can use either Timer 1 to generate baud rates
and/or Timer 2 to generate baud rates. Figure 25 shows
the mode 1 Data Frame.
I
I
Start Bit
Doto Byte
-I- '1
I
The FE bit is located in SCON and shares the same bit
address as SMO. Control bit SMODO in the PCON register determines whether the SMO or FE bit is accessed.
IfSMODO = 0, then accesses to SCON.7 are to SMO.
IfSMODO = I, then accesses to SCON.7 are to FE.
Stop Bit
270697-27
Figure 25. Mode 1 Data Frame
Mode 2: 11 bits are transmitted (through TXD) or .received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (1).
On Transmit, the 9th data bit (TB8 in SCON) can be
assigned the value of 0 or 1. Or, for example, the parity
bit (P in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in SCON, while
the stop bit is ignored. (The validity of the stop bit can
be checked with Framing Error Detection.) The baud
rate is programmable to either 1132 or 1164 the oscillator frequency. See Fignre 26.
I
8.2 Multiprocessor Communications
Modes 2 and 3 provide a 9-bit mode to facilitate multiprocessor communication. The 9th bit allows the controller to distinguish between address and data bytes.
The 9th bit is set to 1 for address and set to 0 for data
bytes. When receiving, the 9th bit goes into RB8 in
SCON. When transmitting, the ninth bit TB8 is set or
cleared in software.
The serial port can be programmed such that when the
stop bit is received the serial port interrupt will be activated only if the received byte is an address byte (RB8
= 1). This feature is enabled by setting the SM2 bit in
SCON. A way to use this feature in multiprocessor systems is as follows.
1DO 101 1021 031 041 051 061 071 osl
I- -I-
Oato syte
-I- -I- -
I
stolSlt
stol Bit
Ninth Data Bit
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. Remember,
an address byte has its 9th bit set to I, whereas a data
byte has its 9th bit set to O. All the slave processors
should have their SM2 bits set to 1 so they will only be
interrupted by an address byte. In fact, the 8XC51GB
has an Automatic Address Recognition feature which
allows only the addressed slave to be interrupted. That
is, the address comparison occurs in hardware, not software. (On the 8051 serial port, an address byte interrupts all slaves for an address comparison.)
270697-26
Figure 26. Mode 2 Data Frame
Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In
fact, Mode 3 is the same as Mode 2 in all respects
except the baud rate. The baud rate in Mode 3 is variable: you can use Timer 1 and/or Timer 2 to generate
baud rates. See Figure 27.
I
The addressed slave then clears its SM2 bit and prepares to receive the data bytes that will be coming. The
other slaves are unaffected by these data bytes. They
are still waiting to be addressed since their SM2 bits are
all set.
100 101 1021 031 041 051 061 071 osl
I- -I-
Data Byte
StalSlt
'1-
Framing Error Detection allows the serial port to check
for valid stop bits in modes 1,2, or 3. A missing stop bit
can be caused, for example, by noise on the serial lines,
or transmission by two CPUs simultaneously.
If a stop bit is missing, a Framing Error bit (FE) is set.
The FE bit can be checked in software after each reception to detect communication errors. Once set, the FE
bit must be cleared in software. A valid stop bit will not
clear FE.
1DO 101 102 103 1041 05 106 1071
I- '1-
8.1 Framing Error Detection
-I- -
I
stal Bit
Ninth Data Bit
270697-29
Figure 27. Mode 3 Data Frame
9-36
intel"
87C51GB HARDWARE DESCRIPTION
zeros defined as don't-cares. The don't-cares also allow
flexibility in defining the Broadcast Address, but in
most applications a Broadcast Address will be OFFH.
8.3 Automatic Address Recognition
Automatic Address Recognition reduces the CPU time
required to service the serial port. Since the CPU is
only interrupted when it receives its own address, the
software overhead to compare addresses is eliminated.
Automatic address recognition is enabled by setting the
SM2 bit in SCON. With this feature enabled in one of
the 9-bit modes, the Receive Interrupt (RI) flag will
only get set when the received byte corresponds to either a Given or Broadcast address.
The feature works the same way in the 8-bit mode
(Mode 1) as in the 9-bit modes, except that the stop bit
takes the place of the 9th data bit. If SM2 is set, the RI
flag is set only if the received byte matches the Given or
Broadcast Address and is terminated by a valid stop
bit. Setting the SM2 bit has no effect in Mode O.
On reset, the SADDR and SADEN registers are initialized to OOH, which defines the Given and Broadcast
Addresses as XXXX XXXX (all don't-cares). This assures the 8XC51GB serial port to be backwards compatibility with other MCS-51 products which do not
implement Automatic Addressing.
The master can selectively communicate with groups of
slaves by using the Given Address. Addressing all
slaves at once is possible with the Broadcast Address.
These addresses are defined for each slave by two Special Function Registers: SADDR and SADEN.
A slave's individual' address is specified in SADDR.
SADEN is a mask byte that defines don't-cares to form
the Given Address. These don't-cares allow flexibility
in the user-defined protocol to address one or more
slaves at a time. The following is an example of how the
user could define Given Addresses to selectively address different slaves.
Slave 1:
SADDR =
SADEN =
GIVEN =
Slave 2:
SADDR =
SADEN =
GIVEN =
1111
1111
0001
1010
1111
OXOX
1111
1111
0011
1001
1111
OXX1
8.4 Baud Rates
The baud rate in Mode 0 is fixed:
Mode
a Baud Rate
= Oscillator Frequency
12
The baud rate in Mode 2 depends on the value of bit
SMODI in Special Function Register PCON. If
SMODI = 0 (which is the value on reset), the baud
rate is 1/64 the oscillator frequency. If SMODI = I,
the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = 2 SMOD1 x
Oscillator~requency
The baud rates in Mode I and Mode 3 are determined
by the Timer I overflow rate, or by Timer 2 overflow
rate, or by both (one for transmit and the other for
receive).
The SADEN bytes are selected such that each slave can
be addressed separately. Notice that bit 1 (LSB) is a
don't-care for Slave 1's Given Address, but bit I = 1
for Slave 2. Thus, to selectively communicate with just
Slave 1 the master must send an address with bit 1 = 0
(e.g. 1111 0000). Similarly, bit 2 = 0 for Slave I, but is
a don't-care for Slave 2. Now to communicate with just
Slave 2 an address with bit 2 = 1 must be used (e.g.
1111 0111). Finally, for a master to communicate with
both slaves at once the address must have bit I = I and
bit 2 = O.
8.5 Timer 1 to Generate Baud Rates
When Timer I is used as the baud rate generator, the
baud rates in Modes I and 3 are determined by the
Timer I overflow rate and the value of SMOD I as follows:
Modes 1 and 3 = 2 SMOD
. Timer 1 Overflow Rate
32
Baud Rate
1x
Notice, however, that bit 3 is a don't-care for both
slaves. This allows two different addresses to select
both slaves (1111 0001 or 1111 0101). If a third slave
was added that required its bit 3 = 0, then the latter
address could be used to communicate with Slave I and
2 but not Slave 3.
Figure 28 shows how commonly used Baud Rates may
be generated. The Timer I interrupt should be disabled
in this application. Timer 1 can be configured for either
"timer" or "counter" operation, and in any of its 3
running modes. In most applications, it is configured
for "timer" operation in the auto-reload mode (high
The master can also communicate with all slaves at
once with the Broadcast Address. It is formed from the
logical OR of the SADDR and SADEN registers with
9-37
int:et
87C51GB HARDWARE DESCRIPTION
nibble of TMOD = ()()10B). In this case, the baud rate
is given by the formula:
8.6 Timer 2 to Generate Baud Rates
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON. Note that the baud
rates for transmit and receive can be simultaneously
different. Setting RCLK and/or TCLK puts Timer 2
into·its baud rate generator mode as shown in Figure
Modes 1 and 3 _ 2 SMOD1 x
Oscillator Frequency
Baud Rate
32 X 12 X [256 - (TH1)j
One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a 16-bit timer (high nibble of
TMOD = OOOlB), and using the Timer 1 interrupt to
do a 16-bit software reload.
Baud Rate
Mode 0 Max: 1 MHz
Mode 2 Max: 375K
Modes 1 & 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110
29.
Fosc
SMOD
12 MHz
12 MHz
12 MHz
. 11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
6MHz
12 MHz
X
Timer 1
C_T
Mode
Reload Value
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
1
1
1
0
0
0
0
0
0
0
Figure 28. Timer 1 Generated Commonly Used Baud Rates
TIMER 1
OVERFLOW
RX CLOCK
TX CLOCK
"TlMER 2"
nEXPIN
INTERRUPT
EXEN2
L
NOTE AVAILABILITY OF AOOIT1ONAL EXTERNAL INTERRUPT
270897-30
Figure 29. Timer 2 in Baud Rate Generator Mode
9-38
infel .
87C51GB HARDWARE DESCRIPTION
Table 18 lists commonly used baud rates and how they
can be obtained from Timer 2.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
It should be noted that when Timer 2 is running (TR2
= I) in "timer" function in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP2 registers may be read, but
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. The timer
should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
The baud rates in Modes 1 and 3 are determined by
Timer 2's overflow rate as follows:
Modes 1 and 3
Baud Rates
=
Timer 2 Overflow Rate
16
Timer 2 can be configured for either "timer" or "counter" operation. In most applications, it is configured for
"timer" operation (C_T2 = 0). The "Timer" operation is different for Timer 2 when it's being used as a
baud rate generator. Normally, as a timer, it increments
every machine cycle (1/12 the oscillator frequency). As
a baud rate· generator, however, it increments every
state time ('/2 the oscillator frequency). The baud rate
formula is given below:
Table 18. Timer 2 Generated Baud Rates
Modes 1 and 3 _
Oscillator Frequency
Baud Rate
32 x [65536 - (RCAP2H, RCAP2L)1
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is valid only if RCLK
and/or TCLK = I in T2CON. Note that a rollover in
TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer 2 interrupt does not have to
be disabled when Timer 2 is in the baud rate generator
mode. Note too, that if EXEN2 is set, a I-to-O transition on the T2EX pin will set EXF2 but will not cause
a reload from (RCAP2H, RCAP2L) to (TH2, TL2).
Thus when Timer 2 is in use as a baud rate generator,
T2EX can be used as an extra external interrupt, if
desired.
Timer 2
Baud Rate
Fosc
375K
9.6K
4.SK
2.4K
1.2K
300
110
300
110
12MHz
12MHz
·12 MHz
12MHz
12MHz
12MHz
12MHz
6MHz
6 MHz
RCAP2H
RCAP2L
FFH
FFH
FFH
FFH
FEH
FBH
F2H
FDH
F9H
FFH
D9H
B2H
64H
CSH
1EH
AFH
SFH
57H
9.0 SERIAL EXPANSION PORT
The Serial Expansion Port (SEP) allows a wide variety
of serially hosted peripherals to be connected to the
8XC51GB. The SEP has four programmable modes
and four clock options. There is a single bi-directional
data pin (p4.1) and a clock output pin (P4.0). Data
transfers consist of 8 clocks with 8 bits of data received
or transmitted. When not transmitting or receiving the
data and clock pins are inactive. There are 3 SFRs associated with the SEP as shown in Figure 30.
r(~M~S~B)~~____' -____- r____- r____- ,______. -____~~(L~SB~)
I
~:~~:~~:~
~
(MSB)
(LSB)
SEPDAT
OE7H
r(~M_S_B)~'-____~______r -____' -____- r____~r-____,-~(L_S_B~)
I
: SEPFWR : SEPFRD:
Figure 30. SEP SFRs
9-39
SEPCON
~I~
SEPIF
I
SEPSTAT
OF7H
87C51GB HARDWARE DESCRIPTION
None of the SEP SFRs are bit addressable. However,
the individual bits of SEPSTAT and SEPCON are significant and have symbolic names associated with them
as shown. The meaning of these bits are:
SEPE
- SEP Enable bit
SEPREN - SEP Receive ENable
CLKPOL - CLocK POLarity
CLKPH - CLocK PHase
SEPS 1 - SEP Speed select 1
SEPSO - SEP Speed select 0
SEPFWR - SEP Fault during WRite
SEPFRD - SEP Fault during ReaD
SEPIF - SEP Interrupt Flag
Table 19. Determination of SEP Modes
CLKPOL
CLKPH
SEPMode
0
0
1
1
0
1
0
1
SEPMODEO
SEPMODE1"
SEPMODE2
SEPMODE3"
The four clock options determine the rate at which data
is shifted out of or into the SEP. All four rates are
fractions of the oscillator frequency. Table 20 shows the
various rates that can be selected for the SEP.
Table 20. SEP Data Rates
9.1 Programmable Modes and
Clock Options
The four programmable modes determine the inactive
level of the clock pin and which edge of the clock is
used for transmission or reception. These four modes
are shown in Figure 31. Table 19 shows how the modes
are determined.
SEPS1
SEPSO
Data Rate
0
0
1
1
0
1
0
1
Fosc/ 12
Fosc/24
Fosc/48
Fosc/96
SEPMODEO
CLOCK
SEPMODE2
CLOCK
DATA SAMPLED
DATA OUTPUT
• SEPMODEI
CLOCK
·SEPMODE3
CLOCK
DATA SAMPLED
DATA OUTPUT
270897-31
·Cannot be used for receive mode.
Figure 31. SEP Modes
9-40
intel .
87C51GB HARDWARE DESCRIPTION
rupts may still be serviced, even after a software upset.
To make the best use of the WDT, it should be serviced
in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
9.2 SEP Transmission or Reception
To transmit or receive a byte the user should initialize
the SEP mode (CLKPOL and CLKPH), clock frequency (SEPS I and SEPSO), and enable the SEP (SEPE). A
transmission then occurs if the user loads data into
SEPDATA. A reception occurs if the user sets
SEPREN while SEPDATA is empty and a transmission is not iii progress. When 8 bits have been received
SEPREN will be cleared by hardware. Once the transmission or reception is complete, SEPIF will be set.
SEPIF remains set until cleared by software. SEPIF is
also the source of the SEP interrupt. Data is transmitted and received MSB first.
10.2 WDT During Power Down and
Idle
In Power Down mode the oscillator stops, which means
the WDT also stops. While in Power Down the user
does not need to service the WDT. There are two methods of exiting Power Down: by a reset or via a level
activated external interrupt which is enabled prior to
entering Power Down. If Power Down is exited with
reset, servicing of the WDT should occur as it normally
does whenever the 8XC51GB is reset. Exiting Power
Down with an interrupt is significantly different. The
interrupt is held low which brings the device out of
Power Down and starts the oscillator. The user must
hold the interrupt low long enough for the oscillator to
stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting
the device while the interrupt pin is held low, the WDT
is not started until the interrupt is pulled high. It is
suggested that the WDT be reset during the interrupt
service routine for the interrupt used to exit Power
Down.
If the user attempts to read or write the SEPDATA
register or write to the SEPCON register while the SEP
is transmitting or receiving an error bit is set. The
SEPFWR bit is set if the action occurred while the SEP
was transmitting. The SEPFRD bit is set if the action
occurred while the SEP was receiving. There is no interrupt associated with these error bits. The bit remains
set until cleared by software. The attempted read or
write of the register is ignored. The reception of transmission that was in progress will not be affected.
10.0 HARDWARE WATCHDOG TIMER
To ensure that the WDT does not overflow within a
few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
The hardware WatchDog Timer (WDT) resets the
8XC51GB when it overflows. The WDT is intended as
a recovery method in situations where the CPU may be
subjected to a software upset. The WDT consists of a
14-bit counter and the WatchDog Timer ReSeT
(WDTRST) SFR. The WDT .is always enabled and increments while the o3(:illator is running. There is no
way to disable the WDT. This means that the user must
still service the WDT while testing or debugging an
application. The WDT is loaded with 0 when the
8XC51GB exits reset. The WDT described in this section is not the Watchdog Tilner associated with PCA
module 4. The WDT does not drive the Reset pin.
In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the 8XC51GB while in
Idle, the user should always set up a timer that will
periodically exit Idle, service the WDT, and re-enter
Idle mode.
11.0 OSCILLATOR FAIL DETECT
The Oscillator Fail Detect (OFD) circuitry keeps the
8XC51GB in reset when the oscillator speed is below
the OFD trigger frequency. The OFD trigger frequency
is shown in the data sheet as a minimum and maximum. If the oscillator frequency is below the minimum,
the device is held in reset. If the oscillator frequency is
greater than the maximum, the device will not be held
in reset. If the frequency is between the minimum and
maximum, it is indeterminate whether the device will
be held in reset or not.
10.1 Using the WDT
Since the WDT is automatically enabled while the
processor is running, the user only needs to be concerned with servicing it. The 14-bit counter overflows
when it reaches 16383 (3FFFH). The WDT increments
once every machine cycle. This means the user must
reset the WDT at least every 16383 machine cycles. If
the user does not wish to use the functionality of the
WDT in an application, a tilner interrupt can be used
to reset the WDT. To reset the WDT the user must
write 01EH and OEIH to WDTRST. WDTRST is a
write only register. The WDT count cannot be read or
written. Using a timer interrupt is not recommended in
applications that make use of the WDT because inter-
The OFD is automatically enab1ed when the device
comes out of reset or when Power Down is exited with
a reset or an interrupt.
The OFD is intended to function only in situations
where there is a gross failure of the oscillator, such as a
9-41
87C51GB HARDWARE DESCRIPTION
broken crystal. To fulfill this need the OFD trigger frequency is significantly below the normal operating frequency. The OFD will not reset the 8XC51GB if the
oscillator frequency should change to another point
within the operating range.
TFO---------------+
11.1 OFD During Power Down
In Power Down, the 8XC51GB oscillator stops in order to conserve power. To prevent the 8XC51GB from
immediately resetting itself out of power down the
OFD must be disabled prior to setting the PD bit. Writing the sequence "OEIH, OIEH" to the OSCillatoR
(OSCR) SFR, turns the OFD off. Once disabled, the
OFD can only be re-enabled by a reset or exit from
Power Down with an interrupt. The status of the OFD
(whether on or oft) can be determined by reading
OSCR. The LSB indicates the status of the OFD. The
upper 7 bits of OSCR will always be Is when read. If
OSCR = OFFH, the OFD is enabled. If OSCR
OFEH, the OFD is disabled.
INT1--~
TFO---------------+
CF~ECF
lY~F
CCFn~ECCFn
1
Y'---1'5
- ) 1 -----1
.~=======
12.0 INTERRUPTS
TF2:======
The 8XC51GB has a total of 15 interrupt vectors: seven
external interrupts (INTO, INTI, INT2, INTJ, INT4,
INT5, and INT6), three timer interrupts (Timers 0, I,
and 2), two PCA interrupts (pCAO and PCAI), the AI
D interrupt, the SEP interrupt, and the serial port interrupt. Figure 32 shows the interrupt sources.
EXF2
I N T 2 - -......
All of the bits that generate interrupts can be set or
cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be canceled
in software.
INT3--~
INT4------I
12.1 Externallnterrupts
External Interrupts iNTO and INTI can each be either
level-activated or negative edge-triggered, depending on
bits ITO and IT! in register TCON. If ITx = O,external interrupt x is triggered by a detected low at the
INTx pin. If ITx = I, external interrupt x is negative
edge-triggered.
INTs------I
INTS------I
CF1~ECl
lY~F··
C1CFn~EC1CFn
INT2 and INT3 cali each be either negative or positive
edge-triggered, depending on bits IT2 and IT3 in register EXICON. If ITx = 0, external interrupt x is negative edge-triggered. If ITx = I, external interrupt x is
positive edge-triggered.
1
Y
51
)
AIF---------------+
SEP---------------+
INT4, INT5, and INT6 are positive edge-triggered
only.
270897-32
Figure 32. Interrupt Sources
9-42
intel .
87C51GB HARDWARE DESCRIPTION
Table 21. EXICON: External Interrupt Control Register
EXICON
Bit
EXICON
Symbol
IE6
IE5
IE4
IE3
IE2
IT3
IT2
Reset Value = XOOO OOOOB
Address = OC6H
Not Bit Addressable
7
6
5
4
3
210
IE2
IT3
IT2
IE6
IE5
IE4
IE3
Function
Not implemented, reserved for future use. •
In~errupt 6 Edge flag. This bit is set by hardware when an external interrupt edge
is detected.
Interrupt 5 Edge flag. This bit is set by hardware when an external interrupt edge
is detected.
Interrupt 4 Edge flag. This bit is set by hardware when an external interrupt edge
is detected.
Interrupt 3 Edge flag. This bit is set by hardware when an external interrupt edge
is detected.
Interrupt 2 Edge flag. This bit is set by hardware when an external interrupt edge
is detected.
. Interrupt 3 Type control bit. This bit is set or cleared by software to control
whether INT3 is positive or negative transition activated. When IT3 is high, IE3 is
set by a positive transition on pin INT3. When IT3 is low, IE3 is set by a negative
transition on pin INT3.
Interrupt2 Type control bit. This bit is set or cleared by software to control
whether INT2 is positive or negative transition activated. When IT2 is high, IE2 is
set by a positive transition on pin INT2. When IT2 is low, IE2 is set by a negative
transition on pin INT2.
·Using software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from reserved bit is indeterminate.
The flags that actually generate the interrupts are bits
lEO and lEI in TCON and IE2, IE3, IE4, IE5, and IE6
in EXICON. These flags are cleared by hardware when
the service routine is vectored to if the interrupt was
transition-activated. If the interrupt was level-activated,
then the external requesting source is what controls the
request flag, rather than the on-chip hardware. The external interrupts are enabled through bits EXO and
EXI in the IE register and EX2, EX3, EX4, EX5, and
EX6 in the lEA register.
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt request flag lEx will be set. lEx will be automatically
cleared by the CPU when the service routine is called.
If external interrupt INTO or INTI is level-activated,
the external source has to hold the request active until
the requested interrupt is actually generated. Then it
has to deactivate the request before the interrupt service routine is completed, or else another interrupt will
be generated. .
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 oscillator periods to ensure sampling. If the
9-43
intel .
87C51GB HARDWARE DESCRIPTION
The PCA interrupt is enabled by bit EC in the IE register. The PCAI interrupt is enabled by bit ECI in the
lEA register. In addition, the CF (CFI) flag and each
of the CCFn (CICFn) flags must also be individually
enabled by bits ECF (ECF1) and ECCFn (ECICFn) in
CMOD
(C I MOD)
and
CCAPMn
registers
(CICAPMn), respectively, in order for that flag to be
able to cause an interrupt.
12.2 Timer Interrupts
Timer 0 and Timer I interrupts are generated by TFO
. and TFI in register TCON, which are set by a rollover
in their respective Timer/Counter registers; the exception is Timer 0 in Mode 3. When a timer interrupt is
generated, the flag that generated it is cleared by the
on-chip hardware when the service routine is vectored
to. These timer interrupts are enabled by bits ETO.and
ETl in the IE register.
12.4 Serial Port Interrupt
Timer 2 interrupt i~ generated by the logical OR of bits
TF2 and EXF2 in register T2CON, Neither of these
flags is cleared by hardware when the service routine is'
. vectored to. In fact, the service routine may have to .
determine whether it was TF2 or EXF2 that generated
the interrupt, and the bit will have to be cleared in
software. The Timer 2 interrupt is enabled by the ET2
bit in the IE register.
12.3 peA Interrupt
The serial port interrupt is generated by the logical OR
of bits RI and TI in register SCON. Neither of these
flags is cleared by hardware when the service routine is
vectored to. The service routine will normally have to
determine whether it was RI or TI that generated the
interrupt, and the bit will have to be cleared in software. The serial port interrupt is enabled by bit ES in
the IE register.
12.5 Interrupt Enable
The PCA interrupts are generated by the logical OR of
five event flags (CCFn, CICFn) and the PCA timer
overflow flag (CF, CFI) in the registers CCON and
CICON. None of these flags are cleared by hardware
when the service routine is vectored to. Normally the
service routine will have to determine which bit flagged
the interrupt and clear that bit in software. This allows
the user to define the priority of servicing each PCA
module.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in the
Interrupt Enable (IE and lEA) registers as shown in
Table 22. Note that IE also contains a global disable
bit, EA. If EA is set (1), the interrupts are individually
enabled or disabled by their corresponding bits in IE
and lEA. If EA is clear (0), all interrupts are disabled.
Figure 33 shows the interrupt control system.
9-44
int'eL
87C51GB HARDWARE DESCRIPTION
SEP--------------+lf-,O.-c'.
INT2 - - - "
Ql
(J
c:
Ql
:J
C"
Ql
(/)
01
,§
o--I-I-HI+I ~
a.
:J
Alf--------------+l";O'''''.
L.
L.
Ql
o--I-I-HI+I 1:
INT4-----;
rrl--------------~";O'~
Cf-----..:.JECf
INTS-----;
~:::::::::::::::[~~---~~~
~~====-----r-~---~~~
INT6-----;
Lowest
Priority
Interrupt
270897-33
Figure 33. Interrupt Control System
9-45
87C51GB HARDWARE DESCRIPTION
Table 22. Interrupt Enable Registers
IE
Reset Value = OOOOOOOOB
Address = OASH
Bit Addressable
I EA I EC I ET21
Bit
7
6
ES
ET1
EX1
4
3
2
5
I EXO I
0
Reset Value = 0000 OOOOB
Address = OA7H
lEA
ETO
Not Bit Addressable
I EAD I EX61 EX5 I EX41 EX3 I EX21 EC1 IESEPI
Bit
7
6
5
4
3
2
o
Enable bit = 1 enables the interrupt
Enable bit = 0 disables the interrupt
Symbol
Function
EA
Global disable bit. ItEA = 0, all Interrupts are disabled. It EA ='1, each Interrupt can be
individually enabled or disabled by setting or clearing its enable bit.
PCA interrupt enable bit.
Timer 2 interrupt enable bit
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enabie bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
AID converter interrupt enable bit.
External interrupt 6 enable bit.
External interrupt 5 enable bit.
External interrupt 4 enable bit.
External interrupt 3 enable bit.
External interrupt 2 enable bit.
PCA 1 interrupt enable bit.
Serial Expansion Port interrupt enable bit.
EC
ET2
ES
ET1
EX1
ETO
EXO
EAD
EX6
EX5
EX4
EX3
EX2
EC1
ESEP
12.6 Interrupt Priorities
Each interrupt source on the 8XC51GB can be individually programmed to one of four priority levels, by setting or clearing the bits in the Interrupt Priority (IP
and IPA) registers and the Interrupt Priority High
(IPH and IPAH) registers. See Table 23. The IPH registers have the same bit map as 'the IP registers with an
"H" added to each bit's name. This gives each interrupt
source two bits for setting the priority levels. The LSB
of the Priority Select Bits is in the IP SFR, and the
MSB is in the IPH SFR.
A low-priority interrupt can itself be interrupted by a
higher priority interrupt, but not by another interrupt
. of the same priority. The highest priority interrupt cannot be interrupted by any other interrupt source.
If two or more requests of different priority levels lI!"e
received simultaneously, the request of higher priority
level is serviced. If requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence shown in
Table 24.
9-46
intaL
87C51GB HARDWARE DESCRIPTION
Table 23 Interrupt Priority Registers
IP
Address
=
OB8H
Reset Value
=
XOOO OOOOB
=
0000 OOOOB
Bit Addressable
IIPA
I PPC I PT2 I PS
Address
=
I
PT1
I
PX1
I
PTO I PXO I
OB6H
Reset Value
Not Bit Addressable
I PAD I PX6
IPH
Address
=
I PX5 I PX4
I PX3 I PX2 I PC1
OB7H
I PSEPI
Reset Value = XOOO OOOOB
Not Bit Addressable
I
IPHA
-
I PPPC I PT2H I PSH I PT1H I PX1H
Address
=
OB5H
I PTOH I PXOH I
Reset Value
=
0000 OOOOB
Not Bit Addressable
IPADH I PX6H I PX5H IPX4H I PX3H I PX2H I PC1 H IpSEP~
Priority Bit
Priority Bit H
Priority
0
0
1
1
0
1
0
1
Lowest
Symbol
PPC, PPCH
PT2,PT2H
PS, PSH
PT1,PT1H
PX1,PX1H
PTO,PTOH
PXO,PXOH
PAD, PADH
PX6,PX6H
PX5, PX5H
PX4,PX4H
PX3,PX3H
PX2, PX2H
PC1, PC1H
PSEP,PSEPH
Highest
Function
Not Implemented, reserved for future use'
PCA interrupt priority bits
Timer 2 interrupt priority bits
Serial Port interrupt priority bits
Timer 1 interrupt priority bits
External interrupt 1 interrupt priority bits
Timer 0 interrupt priority bits
External interrupt 0 interrupt priority bits
AID converter interrupt priority bits
External interrupt 6 interrupt priority bits
External interrupt 5 interrupt priority bits
External interrupt 4 interrupt priority bits
External interrupt 3 interrupt priority bits
External interrupt 2 interrupt priority bits
PCA 1 interrupt priority bits
Serial Expansion Port interrupt priority bits
-,
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future 8051 f~mily products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value
read from a reserved bit is indeterminate.
9-47
intel.,
87C51GB HARDWARE DESCRIPTION
Table 24. Interrupt Polling Sequence
1 (Highest)
2
3
4
5
6
7
8
9
10
11
12
13
14
15 (Lowest)
INTO
SEP
INT2
Timer 0
PCA1
INT3
INT1
AID
INT4
Timer 1
PCA
INT5
PCA
Timer 2
INT6
Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priority level.
12.7 Interrupt Processing
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. The Timer 2 overflow interrupt is
slightly different, as described in the Interrupt Response Time section. If one of the flags was in a set
condition at. S5P2 of the preceding cycle, the polling
cycle will find it and the interrupt system will generate
an LCALL to the appropriate service routine, provided
this hardware-generated LCALL is not blocked by any
of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in
the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to
the IE or IP registers.
not being responded to for one of the above conditions
and is not still active when the blocking condition is
removed, the denied interrupt will not be serviced. In
other words, the fact that the interrupt flag was once
active but not serviced is not remembered. Every polling cycle is new.
The polling cycle/LCALL sequence is illustrated in the
Interrupt Response Timing Diagram.
Note that if an interrupt of a higher priority level goes
active prior to S5P2 of the machine cycle labeled C3 in
the diagram, then in accordance with the above rules it
will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed. This is the fastest possible response when C2 is
the final cycle of an instruction other than RETI or
write IE or IP.
Thus the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the appropriate servicing routine. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectored to. Table 25
shows the interrupt vector addresses.
Table 25. Interrupt Vector Addresses
Interrupt
Source
Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be
completed before vectoring to any service routine. Condition 3 ensures that if the instruction· in progress· is
RETl or any write to IE or IP, then at least one more
instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. If the interrupt
flag for a level-sensitive external interrupt is active but
9-48
Interrupt
Cleared by Vector
Request Bits Hardware Address
No (level)
Yes (trans.)
0003H
TFO
Yes
OOOBH
IE1
No (level)
Yes (trans.)
0013H
TF1
Yes
001BH
INTO
lEO
Timer 0
INT1
Timer 1
Serial Port
RI,TI
No
0023H
Timer 2
TF2, EXF2
No
002BH
PCA
CF,CCFn
(n = 0-4)
No
0033H
AID
AIF
No
003BH
PCA1
CF1, C.1 CCFn
(n = 0-4)
No
0043H
SEP
SEPIF
No
004BH
INT2
IE2
Yes
0053H
INT3
IE3
Yes
005BH
INT4
IE4
Yes
0063H
INT5
IE5
Yes
006BH
INT6
IE6
Yes
0073H
intet
87C51GB HARDWARE DESCRIPTION
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no
longer in progress, then pops the top two bytes from the
stack and reloads the Program Counter. Execution of
the interrupted program continues from where it left
off.
The Timer 0 and Timer I flags, TFO and TFI, are set at
S5P2 of the cycle in which the timers overflow. The
values are then polled by the circuitry in the next cycle.
However, the Timer 2 flag TF2 is set at S2P2 and is
polled in the same cycle in which the timer overflows.
If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapses between
activation of an external interrupt request and the beginning of execution of the service routine's first instruction. See Figure 34.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking
interrupt was still in progress.
The starting addresses of consecutive interrupt service
routines are only 8 bytes apart. That means if consecutive interrupts are being used (lEO and TFO, for example, or TFO and lEI), and if the first interrupt routine is
more than 7 bytes long, then that routine will have to
execute a jump to some other memory location where
the service routine can be completed without overlapping the starting address of the next interrupt routine.
A longer response time would result if the request is
blocked by one of the 3 conditions discussed in the Interrupt Processing section. If an interrupt of equal or
higher priority level is already in progress, the additional wait time obviously depends on the nature of the
other interrupt's service routine. If the instruction in
progress is not in its final cycle, the additional wait time
cannot be more than 3 cycles, since the longest instructions (MUL and DIY) are only 4 cycles long, and if the
instruction in progress is RETI or write to IE or IP, the
additional wait time cannot be more than 5 cycles (a
maximum of one or more cycles to complete the instruction in progress, plus 4 cycles to complete the next
instruction if the instruction is MUL or DIY).
12.8 Interrupt Response Time
The INTO and INTI levels are inverted and latched
into the Interrupt Flags lEO, and lEI at S5P2 of every
machine cycle. The level of interrupts 2 through 6 are
also latched into the appropriate flags (IE2- 1E6) in
S5P2. Similarly, the Timer 2 flag EXF2 and the Serial
Port flags RI and TI are set at S5P2. The values are not
actually polled by the circuitry until the next machine
cycle.
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.
.. ...... _--C1--..a-tI...> - - - C 2 - -.....,I"'".---C3
ISSP21
• I •
C 4 - -.....,Ij-..--CS-_.... •
S6
........ ~'r,----L...----'\111f---L..-..-"t1'l:\~---'----
f7't
INTERRUPT
GOES
ACTIVE
INTERRUPT
LATCHED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPTS
ARE POLLED
INTERRUPT ROUTINE
270697-34
This is the fastest possible response whenC2 is the final cycle of an instruction other than RETI or write IE or IP.
Figure 34. Interrupt Response Timing Diagram
9-49
87C51GB HARDWARE DESCRIPTION
When power is turned on, the circuit holds the
RESET pin high for an amount of time that depends on
the capacitor value and the rate at which it charges. To
ensure a valid reset the RESET pin must be held low
long enough to allow the oscillator to start up plus two
machine cycles.
13.0 RESET
The reset input is the RESET pin, which has a Schmitt
Trigger input. A reset is accomplished by holding the
RESET pin low for at least two machine cycles. (24
oscillator periods). On the 8XC5IGB, reset is asynchronous to the CPU clock. This means that the oscillator does not have to be running for the 1/0 pins to be
in their reset condition. However, Vee has to be within
the specified operating conditions.
On power up, Vee should rise within approximately
ten milliseconds. The oscillator start-up time will depend on the oscillator frequency. For'a 10 MHz crystal,
the start-up time is typically 1 ms. For a 1 MHz crystal,
the start-up time is typically 10 ms.
Once Reset has reached a high level, the 8XC51GB
may remain in its reset state for up to 5 machine cycles.
This is caused by the OFD circuitry.
Powering up the device without a valid reset· could
cause the CPU to start executing instructions from an
indeterminate location. This is because the SFRs, specifically the Program Counter, may not get properly
initialized.
While the RESET pin is low, the port pins, ALE and
PSEN are weakly pulled high. After RESET is pulled
high, it will take up to 5 machine cycles for ALE and
PSEN to start clocking. For this reason, other devices
can not be synchronized to the internal timings of the
8XC5IGB.
14.0 POWER-SAVING MODES
For applications where power consumption is critical,
the 8XC51GB provides two power reducing modes of
operation: Idle and Power Down. The input through
which backup power is supplied during these operations is Vee. The Idle and Power Down modes are
activated by setting bits IDL and PD, respectively, in
the SFR PCON (Table 26). Figure 36 shows the Idle
and Power Down circuitry.
Driving the ALE and PSEN pins to 0 while reset is
active could cause the device to go into an indeterminate state.
The internal reset algorithm redefines most of the
SFRs. Refer to individual SFRs for their reset values.
The internal RAM is not affected by reset. On power
up the RAM content is indeterminate.
13.1 Power-On Reset
For CHMOS devices, when Vee is turned on, an automatic reset can be obtained by connecting the
. RESET pin to Vss through a 1 p.F capacitor. The
CHMOS devices do not require an external resistor like
the HMOS devices because they have an internal pullup
on the RESET pin. Figure 35 shows this.
In the Idle mode (IDL = I), the oscillator continues to
run and the Interrupt, Serial Port, PCA, and Timer
blocks continue to be clocked, but the clock signal is
. gated off to the CPU. In Power Down (PD = I), the
oscillator is frozen.
1 pF
vss
270897-35
Figure 35. Power-On Reset Circuitry
9-50
intel"
87C51GB HARDWARE DESCRIPTION
Table 26. PCON: Power Control Register
PCON
Address = 87H
Reset Value = OOXX OOOOB
Not Bit Addressable
ISMOD1 ISMODO I
Bit
7
5
6
POF
GF1
GFO
4
3
2
PD
IDL
o
Symbol
Function
SMOD1
Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rates, and the
Serial Port is used in modes 1, 2, or 3.
SMODO
When set, Read/Write accesses to SCON.7 are to the FE bit. When clear, Read/Write
accesses to SCON.7 are to the SMO bit.
POF
Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This
flag allows detection of a power failure caused reset. Vee must remain above 3V to retain
this bit.
GF1
General-purpose flag bit.
GFO
General-purpose flag bit.
Not implemented, reserved for future use.'
PD
Power Down bit. Setting this bit activates Power Down operation.
IDL
Idle mode bit. Setting this bit activates idle modes operation.
If 1s are written to PO and IDL at the same time, PD takes precedence.
NOTE:
'User software should not write 1s to unimplemented bits. These bits may be used in future 8051 family products to
invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.
The value read from a reserved bit is indeterminate.
~!~
XTAL 2
=
XTAL 1
INTERRUPT,
1--+--0 SERIAL PORT,
TIMER BLOCKS
CPU
270897-36
Figure 36. Idle and Power Down Hardware
9-51
intel~
87C51GB HARDWARE DESCRIPTION
14.1 Idle Mode
14.2 Power Down Mode
An instruction that sets the IDL bit causes that to be
the last instruction executed before going into the Idle
mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions. The PCA and PCA1 timers
can be programmed either to pause or continue operating during Idle with the CIDL (CIIDL) bit in CMOD
(C1MOD). The CPU status is preserved in its entirety:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. ALE and
PSEN hold at logic high levels. Refer to Table 27.
An instruction that sets the PD bit causes that to be the
last instruction executed before going into the Power
Down mode. In this mode the on-chip oscillator is
stopped. With the clock frozen, all functions are
stopped, but the on-chip RAM and Special Function
Registers are held. The port pins output the values held
by their respective SFRs, and ALE and PSEN output
lows. In Power Down, Vee can be reduced to as low as
2V. Care must be taken, however, to ensure that Vee is
not reduced before Power Down is invoked. If the Oscillator Fail Detect circuitry is not disabled before entering powerdown, the part will reset itself (see Section
11.0 "Oscillator Fail Detect"). Table 28 shows the
status of external pins during Power Down mode.
Table 27. Status of the External Pins
during Idle Mode
Table 28. Status of the External Pins
during Power Down Mode
Program
Ports
ALE PSEN PortO Port 1 Port 2
Memory
3,4,5
Internal
External
1
1
1
1
Data
Float
Program
Ports
ALE PSEN PortO Port 1 Port 2
Memory
3,4,5
Data
Data
Data
Data Address Data
Internal
External
There are two ways to terminate the Idle Mode. Activation of any enabled interrupt will cause the IDL bit to
be cleared by hardware, terminating the Idle mode. The
interrupt will be serviced, and following RET! the next
instruction to be executed will be the one following the
instruction that put the device into Idle.
0
0
0
0
Data
Float
Data
Data
Data
Data
Data
Data
The 8XC5lGB can exit Power Down with either a
hardware reset or external interrupt. Reset redefines
most of the SFRs but does not change the on-chip
RAM. An external interrupt allows both the SFRs and
the on-chip RAM to retain their values.
The flag bits (GFO and GF1 in PCON) can be used to
give an indication if an interrupt occurred during normal operation or during Idle. For example, an instruction that activates Idle can also set one or both flag bits.
When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
To properly terminate Power Down the reset or external interrupt should not be executed before Vee is restored to its normal operating level and must be held
active long enough for the oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INTO or INTI must be enabled and configured as level-sensitive. Holding the pin
low restarts the oscillator and bringing the pin back
high completes the exit. After the RETI instruction is
executed in the interrupt service routine, the next instruction will be the one following the instruction that
put the device in Power Down.
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is stilI running, the hardware reset needs to be held active for only
two machine cycles (24 oscillator periods) to complete
the reset.
The signal at the RESET pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes
program execution from where it left off; that is, at the
instruction following the one that invoked the Idle
Mode. As shown in the Reset Timing diagram, two or
three machine cycles of program execution may take
place before the internal reset algorithm takes control.
On-chip hardware inhibits access to the internal RAM
during this time, but access to the port pins is not inhibited. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that
invokes Idle should not be one that writes to a port pin
or to external Data RAM.
14.3 Power Off Flag
The Power Off Flag (POF) located at PCON.4 is set by
hardware when Vee rises from OV to 5V. POF can also
be set or cleared by software. This allows the user to
distinguish between a "cold start" reset and a "warm
start" reset.
A cold start reset is one that is coincident with Vee
being turned on to the device after it was turned off. A
warm start reset occurs while Vee is still applied to the
device and could be generated, for example, by a
Watchdog Timer or an exit from Power Down.
9-52
<
infel,;
87C51GB HARDWARE DESCRIPTION
Immediately after reset, the user's software can check
the status of the POF bit. POF = I would indicate a
cold start. The software then clears POF and commences its tasks. POF = 0 immediately after reset
would indicate a warm start.
Table 29. EPROM/OTP Lock Bits
Program
Lock Bits
LB1 LB2 LB3
Vee must remain above 3V for POF to retain a O.
U
U
U
No Program Lock features
enabled. (Code Verify will still
be encrypted by the
Encryption Array.)
P
U
U
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory. EA is
sampled and latched on
reset, and further
programming of EPROM is
disabled.
P
P
U
Same as above, but Verify is
also disabled (option
available on EPROM only).
P
P
P
Same as above and all
external program execution is
inhibited and internal RAM
cannot be read externally.
15.0 EPROM/OTP PROGRAMMING
The 8XCSIGB uses the fast "Quick-Pulse" Programming algorithm. The devices program at Vpp =
12.7SV (and Vee = S.OV) using a series of five 100 /Ls
PROG pulses per byte programmed.
15.1 Program Memory Lock
In some microcontroller applications it is desirable that
the Program Memory be secure from software piracy.
The 8XCSIGB has a three-level program lock feature
which protects the code of the on-chip EPROM/OTP
or ROM.
Within the EPROM/OTP /ROM are 64 bytes of Encryption Array that are initially unprogrammed (all
Is). The user can program the Encryption Array to
encrypt the program code bytes during EPROM/OTPI
ROM verification. The verification procedure is performed as usual except that each code byte comes out
exclusive-NOR'ed (XNOR) with one of the key bytes.
Therefore, to read the ROM code the user has to know
the 64 key bytes in their proper sequence.
Logic Enabled
NOTE:
All other combinations of lock bits may produce indeterminate results and should not be used.
16.0 ONCE MODE
Unprogrammed bytes have the value OFFH. So if the
Encryption Array is left unprogrammed, all the key
bytes have the value OFFH. Since any code byte
XNORed with OFFH leaves the byte unchanged, leaving the Encryption Array unprogrammed in effect bypasses the encryption feature.
The ONCE (ON-Circuit Emulation) mode facilitates
testing and debugging of systems using the 8XCSiGB
without having to remove the device from the circuit.
The ONCE mode is invoked by:
1. Pulling ALE low while the device is in reset and
PSEN is high;
2. Holding ALE low as RST is deactivated.
PROGRAM LOCK BITS
While the device is in ONCE mode, the Port 0 pins go
into a float state, and the other port pins, ALE, and
PSEN are weakly pulled high. The oscillator circuit
remains active. While the device is in this mode, an
emulator or test CPU can be used to drive the circuit.
Also included in the Program Lock scheme are three
Lock Bits which can be programmed to disable certain
functions as shown in Table 29.
To obtain maximum security of the on-board program
and data, all 3 Lock Bits and the Encyption Array must
be programmed.
Normal operation is restored after a valid reset is applied.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returning the part to full functionality:
17.0 ON-CHIP OSCILLATOR
The on-chip oscillator for the CHMOS devices consists
of a single stage linear inverter intended for use as a
9-53
inteL
87C51GB HARDWARE DESCRIPTION
crystal-controlled, positive reactance oscillator. In this
application the crystal is operating in its fundamental
response mode as an inductive reactance in parallel resonance with capacitance external to the crystal. Figure
37 shows the on-chip oscillator circuitry.
The oscillator on the CHMOS devices can be turned off
under software control by setting the PD bit in the
PCON register (Figure 38). The feedback resistor Rr
shown in the figure consists of parallel n- and p-channel
FETs controlled by the PD bit, such that Rr is opened
when PD = 1. The diodes Dl and D2, which act as
clamps to Vee and V ss, are parasitic to the Rr FETs.
The crystal specifications and capacitance values (Cl
and C2 in Figure 39) are not critical. 30 pF can be used
in these positions at any frequency with good quality
crystals. In general, crystals used with these devices
typically have the following specifications:
ESR (Equivalent Series Resistance)
.CO (shunt capacitance)
CL (load capacitance)
Drive Level
7.0 pF maximum
30 pF ± 3 pF
1 MW
Vcc
TO INTERNAL
TIMING CKTS
01
Rf
4000
XTAL1
XTAL2
02
r
PO
270897-37
Figure 37. On-Chip Oscillator Circuitry
Vcc
TO INTERNAL
TIMING CKTS
RI
VSS
-------BOC51
XTAL1-----
XTAL2-----CRYSTAL
OR CERAMIC
RESONATOR
~--t--QUARTZ
270897-38
Figure 38. Using the CHMOS On-Chip Oscillator .
9-54
intel~
87C51GB HARDWARE DESCRIPTION
There are no requirements on the duty cycle of the
external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times
specified in the data sheets must be observed. Refer to
the External Clock Specifications for this information.
500
~ 400
:t:
~
300
'"~
200
An external oscillator may encounter as much. as a
100 pF load at XTALI when it starts up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications, the capacitance will not exceed
20 pF.
100
4
8
12
16
CRYSTAL FREQUENCY In MHz
270897-39
18.0 CPU TIMING
Figure 39. ESR vs Frequency
The internal clock generator defines the sequence of
states that make up a machine cycle. A machine cycle
consists of 6 states, numbered S1 through S6. Each
state time lasts for two oscillator periods. Thus a machine cycle takes 12 oscillator periods or 1 ,..,S if the
oscillator frequency is 12 MHz. Each state is then divided into a Phase 1 and Phase 2 half.
Frequency, tolerance, and temperature range are deter·
mined by the system requirements.
A ceramic resonator can be used in place of the crystal
in cost-sensitive applications. When a ceramic resonator is used, CI and C2 are normally selected as higher
values, typically 47 pF. The manufacturer of the cer~m
ic resonator should be consulted for recommendations
on the values of these capacitors.
Rise and fall times are dependent on the external loading that each pin must drive. They are approximately
10 ns, measured between O.BV and 2.0V.
A more in-depth discussion of crystal specifications, ceramic resonators, and the selection of values for C 1 and
C2 can be found in Application Note AP-155, "Oscillators for Microcontrollers" in the Embedded Control
Applications handbook.
Propagation delays are different for different pins. For
a given pin they vary with pin loading, temperature,
Vee. and manufacturing lot. If the XTALI waveform
is taken as the timing reference, propagation delays
may vary from 25 ns to 125 ns.
To drive the CHMOS parts with an external clock
source, apply the external clock signal to XTALI and
leave XTAL2 floating. Refer to the External Clock
Source diagram. This is an important difference from
the HMOS parts. With HMOS, the external clock
source is applied to XTAL2, and XTALI is grounded.
See Figure 40.
The AC Timings section of the data sheets do not reference any timing to the XTAL 1 waveform. Rather, they
relate the critical edges of control and input signals to
each other. The timings published in the data sheets
include the effects of propagation delays under the
specified test condition.
8XC51GB
NC -
External
Oscillator
Signal
:>C_:>----f
CMOS Gate
XTAL2
XTAL1
rLV_S;';S_ __
Vss
270897-40
Figure 40. Driving the CHMOS Devices with an External Clock Sources
9-55
87C51 GB/83C51 GB/80C51 GB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
87C51GB-8 Kbytes OTP/8 Kbytes Internal Program Memory
83C51GB-8 Kbytes Factory Programmable ROM
80C51GB-CPU with RAM and I/O
8XC51GB-3.5 MHz to 12 MHz ±20% Vee
8XC51GB-1-3.5 MHz to 16 MHz ± 20% Vee
•
•
•
8 Kbytes On-Chip ROM/OTP ROM
256 Bytes of On-Chip Data RAM
Two Programmable Counter Arrays
with:
- 2 x 5 High Speed Input/Output
Channels Compare/Capture
- Pulse Width Modulators
- Watchdog Timer Capabilities
16-Bit Timer/Counters with
• -Three
Four Programmable Modes:
- Capture, Baud Rate Generation
(Timer 2)
Watchdog Timer
• Dedicated
A/D with:
• -8-Bit,Eight8-Channel
8-Bit Result Registers
- Four Programmable Modes
Serial Channel with:
• -Programmable
Framing Error Detection
- Automatic Address Recognition
Expansion Port
• Serial
Programmable Clock Out
•
Programmable I/O Lines with
• 4840 Schmitt
Trigger Inputs
15 Interrupt Sources with:
• - 7 External, 8 Internal Sources
- 4 Programmable Priority Levels
Port States on Reset
• Pre-Determined
High Performance CHMOS Process
• TTL and CHMOS Compatible Logic
• Levels
Power Saving Modes
• 64K
Data Memory Space
• 64K External
Program Memory Space
• ThreeExternal
Level Program Lock System
•
(ON-Circuit Emulation) Mode
• ONCETM
Quick Pulse Programming™ Algorithm
• MCS®-51 Fully Compatible Instruction
• Set
Boolean Processor
• Oscillator
Detect
• Available inFail68-Pin
PLCC
•
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8 Kbytes of the program memory can reside in the on-chip ROM. Also, the device
can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 8XC51 GB isa single-chip control oriented microcontroller which is fabricated on Intel's CHMOS III-E
technology. The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction
set and architecture as existing MCS®-51 products. Added features make it an even more powerful microcontroller for applications that require On-Chip AID, Pulse Width Modulation, High Speed I/O, up/down counting
capabilities and memory protection features. It also has a more versatile serial channel that facilitates multiprocessor communications.
9-56
July 1992
Order Number: 270869-003
intel..
87C51GB/83C51GB/80C51GB
SFRs
nUERs
P.C.A
P.CA.l
SERIAL PORTS
PSEN
ALE/PROG
EJ./vpP
RESET
r-~":"'-"""''''''''TRIGIN
COMPREF
AVREF
L...__...........I--rAVSS
P1.0-Pl.7
P4.0- P4.7
PS.O -PS.7
P3.0- P3.7
270869-1
Figure 1. 8XC51GB Block Diagram
PROCESS INFORMATION
PACKAGES
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
Package Type
68-Pin PLCC.
\
9-57
intel~
87C51GB/83C51GB/80C51GB
PARALLEL I/O PORTS
Port Pins as Inputs
The 8XC51GB contains six 8-bit parallel 1/0 ports.
All six ports are bidirectional and consist of a latch,
an output driver, and an input buffer. Many of the
port pins have multiplexed 110 and control functions.
The pins of all six ports are configured as inputs by
writing a logic 1 to them. Since Port 0 is an open
drain port, it provides a very high input impedance.
Since pins of Port 1, 2, 3, 4and 5 have weak pullups
(which are always on), they source a small current
when driven low externally. All ports except Port 0
have Schmitt trigger inputs.
Port Pins as Outputs
Port 0 has open drain outputs when it is not serving
as the external data bus. The internal pullup is active
only when the pin is outputting a logic 1 dwing external memory access. An external pullup resistor is
required on Port 0 when it is serving as an output
port.
Port States During Reset
Ports 0 and 3 reset asynchronously to a one and
Ports 1, 2, 4, and 5 reset to a zero asynchronously.
PIN DESCRIPTIONS
Ports 1, 2, 3, 4, and 5 have quasi-bidirectional outputs. A strong pullup provides a fast rise time when
the pin is set to a logic 1. This pullup turns on for two
oscillator periods to drive the pin high and then turns
off. The pin is held high bya weak pullup.
The 8XC51 GB will be packaged in the 68-lead PLCC
package. Its pin assignment is shown in Figure 2.
Vee: Supply Voltage.
Writing the PO, P1, P2, P3, P4 or P5 Special Function
Register sets the corresponding port pins. All six
port registers are bit addressable.
Vss: Circuit Ground.
Diagram Is for Pin Reference Only_ Package Size is Not to Scale.
~ ~ ~ ~ ~ ~ ~ ~
•
~
N
_
0
~
•
~
N
E~ ~ ~ ~ ~ ~ ~ ~ ~ ~ << < <
""
"ci"
"""'"
•
ci ci ci d 0 ci 0 N N N N
U 0
•
~
N
-
0
~
~
~
•
~
N
-
0
~
~
~
•
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
C 1 EX2/P4.S
P2.3/All
C 1 EX3/P4.6
P2.2/Al0
C1EX4/P4.7
P2.1/A9
P2.0/AB
Vee
EA/V;.
PS.O
ALE/PROG'
PS.l
INT2/PS.2
PSEN
INT3/PS.3
XTAL2
INU/PS.4
XTAL 1
INTS/PS.S
Vss
INT6/PS.6
TRIGIN
PS.7
ACHO
T2/P1.0
ACHI
T2EX/Pl.l
ACH2
ECI/P1.2
ACH3
CEXO/Pl.3
ACH4
CEX1/P1.4
ACHS
270869-3
·OTP only
Figure 2. Pin Connections
9-58
infel·
87C51GB/83C51GB/80C51GB
ALTERNATE PORT FUNCTIONS
Ports 0, 1, 2, 3, 4 and 5 have alternate functions as well as their I/O function as described below.
Port Pin
Alternate Function
PO.O/ ADO-PO. 7 / AD7
Multiplexed Address/Data for External Memory
P1.0/T2
Timer 2 External Clock Input/Clock-Out
P1.1/T2EX
Timer 2 Reload/Capture/Direction Control
P1.2/ECI
PCA External Clock Input
P1.3/CEXO-P1.7/CEX4
PCA Capture Input, Compare/PWM Output
P2.0/ AB-P2.7 / A 15
High Byte of Address for External Memory
P3.0/RXD
Serial Port Input
P3.1/TXD
Serial Port Output
P3.2/INTO
External Interrupt 0
P3.3/INT1
External Interrupt 1
P3.4/TO
Timer 0 External Clock Input
P3.5/T1
Timer 1 External Clock Input
P3.6/WR
Write Strobe for External Memory
P3.7/RD
Read Strobe for External Memory
P4.0/SEPCLK
Clock Source for Serial Expansion Port
P4.1/SEPDAT
Data I/O for the Serial Expansion Port
P4.2/ECI1
PCA1 External Clock Input
P4.3/C1 EXO-P4. 7 /C1 EX4
PCA 1 Capture Input, Compare/PWM Output
P5.2/INT2-P5.6/INT6
External Interrupt INT2-INT6
RST: Reset input. A low on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a voltage below VIL max voltage is applied, whether the oscillator is running or not. An
internal pullup resistor permits a power-on reset with
only a capacitor connected to Vss.
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
.
When the 8XC51GB is executing code from external
Program Memory,PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin (ALE/PROG) is also
the program pulse input during programming of the
.
87C51GB.
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from external Program Memory locations
OOOOH to 1FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be internally latched on reset.
In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
EA should be strapped to Vee for internal program
executions.
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX instruction. Otherwise the
pin is weakly pulled high.
This pin also receives the 12.75V programming supply voltage (Vpp) during programming (OTP only).
XTAL 1: Input to the inverting oscillator amplifier.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
XTAL2: Output from the inverting oscillator amplifier.
9-59
intel .
87C51GB/83C51 GB/80C51GB
AID CONVERTER
The 8XC51 GB AID converter has a resolution of 8
bits and an accuracy of ± 1 LSB (± 2 LSB for channels 0 and 1). The conversion time for a single channel is 20 /Ls at a clock frequency of 16 MHz with the
sample and hold function included. Independent
supply voltages are provided for the AID. Also, the
AID operates both in Normal Mode or in Idle Mode.
which of the six PCAIPCA 1 interrupts has occurred.
The EC Bit in the IE (Interrupt Enable) Special Function Register is a global interrupt enable for the PCA
P1.7/P4.7.-.-..
REG/COM MODULE 4
(CEX4)/(C1 EX4) ,
t--------I
P1.6/P4.6.-.-..
REG/COM MODULE 3
(CEX3)/(C1 EX3)
t--------I
Pl.5/P4.5.-.-..
REG/COM MODULE 2
(CEX2)/(Cl EX2)
I--------t
P1.4/P4.4 . - . - . .
REG(~OM MODULE 1
(cm )/(Cl EX1)
t--:...-.-----I
P1.3/P4.3 . - . - . .
REG/COM MODULE D
(CEXO)/(C1 EXO)
....~-:-_-:--:-.....
The AID has 8 analog input pins; ACHO (AID CHannelO) ... ACH7, 1 reference input pin; COMPREF
(COMParison REFerence), 1 control input pin; TRIGIN (TRIGger IN), and 2 power pins; AVREF (Voltage REFerence) and analog ground (ANalog
GrouND). In addition, the AID has 8 conversion result registers; ADRESO (AID result for channel 0) ...
ADRES7,1 comparison result register; ACMP (Analog Comparison), and 1 control register; ACON (AID
Control).
The control bit ACE (AID Conversion Enable) in
ACON controls whether the AID is in operation or
not. ACE = 0 idles the AID. ACE = 1 enables AID
conversion. The control bit AIM (A/D Input mode) in
ACON controls the mode of channel selection. AIM
= 0 is the Scan Mode, and AIM = 1 is the Select
Mode. The result registers ADRES4 ... ADRES7 always contain the result of a conversion from the corresponding channels ACH4 ... CH7. However, the
result registers ADRESO ... ADRES3 depend on the
mode selected. In the scan mode, ADRESO ... ADRES3 contain the values from ACHO ... ACH3. In
the Select Mode, one of the four channels ACHO ...
ACH3 is converted four times, and the four values
are stored sequentially in locations ADRESO ... ADRES3. Its channel is selected by bits ~CS1 and
ACSO (AID Channel Select 1 and 0) in ACON.
tt ... t t
COUNTER MODULE
270869-4
Figure 3~ Programmable Counter Arrays
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 4. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
To drive the device from an external clock source,
XTAL should be driven, while XTAL2 floats, as
shown in Figure 5. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
'
be observed.
PROGRAMMABLE COUNTER ARRAYS
The Programmable Counter Arrays (PCA-PCA1) are
each made up of a Counter Module and five Register/Comparator Modules as shown below. The
16-bit output of the counter module is available to all
five Register/Comparator Modules, providing one
common timing reference. Each Register/Comparator Module is associated with a pin of Port 1 or Port 4
and is capable of performing input capture, output
compare and pulse width modulation functions. The
PCAs are exactly the same in function except for the
addition of clock input sources on PCA 1.
C2
t--9---I XTAL2
t-~It-_""'--I XTAL 1
t - - - - - - - I Vss
270869-5
C1, C2 = 30 pF ± 10 pF for Crystals
For Ceramic Resonators contact resonator
manufacturer.
The PCA Counter and five Register/Comparator
Modules each have a status bit in the CCON/
C1 CON Special Function Registers. These six
status bits are set according to the selected modes
of operation described below. The CCON/C1 CON
Register provides a convenient means to determine
Figure 4. Oscillator Connections
9-60
intet
87C51GB/83C51GB/80C51GB
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL I
modes. The interrupt must be enabled and configured as level sensitive. To properly terminate Power
Down the reset or external interrupt should not be
executed before Vcc is restored to its normal operating level. The reset or external interrupt must be
held active long enough for the oscillator to restart
and'stabilize. The Oscillator Fail Detect must be disabled prior to entering Power Down.
vss
DESIGN CONSIDERATIONS
270869-6
• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
• As RESET rises, the 8XC51GB will remain in reset for up to 5 machine cycles (60 oscillator periods) after RESET reaches VIH1.
Figure 5. External Clock Drive Configuration
IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during idle, peripherals continue to operate, but the processor
stops executing instructions. Idle Mode will be exited
if the chip is reset or if an enabled interrupt occurs.
The PCA timer/counter can optionally be left running or paused during Idle Mode. The Watchdog
Timer continues to count in ldle Mode and must be
serviced to prevent a device RESET while in Idle.
ONCE MODE
POWER DOWN MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
8XC51GB without removing it from the circuit. The
ONCE Mode is invoked by:
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
1) Pulling ALE low while the device is in reset and
PSEN is high;
2) Holding ALE low as RESET is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC51GB is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
On the 8XC51 GB either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt does not redefine the SFR's or change the on-chip RAM. An
external interrupt will modify the interrupt associated
SFR's in the same way an interrupt will in all other
Table 1. Status of the External Pins during Idle and Power Down
Mode
Program
Memory
Idle
Idle
Power Down
Power Down
Internal
External
Internal
External
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
1
1
1
1
0
0
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers
and Processors Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook). "Designing with the 80C51BH."
9-61
87C51GB/83C51GB/80C51GB
Four Interface Modes- High/Low/Falling/Rising
Edges.
Interrupt Driven.
Watchdog Timer (WDT)
The 8XC51GB contains a dedicated Watchdog Timer (WDT) to allow recovery from a software or hardware upset. The WDT consists of a 14-bit counter
which is cleared on Reset, and subsequently incremented every machine cycle. While the oscillator is
running, the WDT will be incrementing and cannot
be disabled. The counter may be reset by writing
1EH and E1 H in sequence to the WDTRST Special
Function Register. If the counter is not reset before
it reaches 3FFFH (16383D), the chip will be forced
into a reset sequence by the WDT. This works out to
12.28 ms @ 16 MHz. WDTRST is a write only register. The WDT does not force the external reset pin
low.
Oscillator Fail Detect (OFD)
The Oscillator Fail Detect Circuitry triggers a reset if
the oscillator frequency is lower than the OFD trigger frequency. It can be disabled by software by writing E1 H followed by 1EH to the OFDCON register.
Before going into Power Down Mode, the OFD must
be disabled or it will force the GB out of Power
Down. The OFD has the following features.
OFD Trigger Frequency: Below 20 KHz, the
8XC51 GB will be held in reset. Above 400 KHz,
the 8XC51GB will not be held is reset.
While in Idle mode the WDT continues to count. If
the user does not wish to exit Idle with a reset, then
the processor must be periodically "woken up" to
service the WDT. In Power Down mode, the WDT
stops counting and holds its current value.
Functions in Normal and Idle Modes.
Reactivated by Reset (or EXternal Interrupt Zero/One Pins) after Software Disable.
Serial Expansion Port (SEP)
The Serial Expansion Port is a half-duplex synchronous serial interface with the following features:
Four Clock Frequencies- XTAL/12, 24, 48, 96.
9-62
.infel"
87C51GB/83C51GB/80C51GB
ABSOLUTE MAXIMUM RATINGS·
Storage Temperature .........• - 65'C to
+ 70'C
+ 150'C
Voltage on EAlVpp
Pin to Vss ..................... OV to
+ 13.0V·
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature under Bias .... O'C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
IOL per 1/0 Pin ........................... 15 mA
Voltage on Any Other
Pin to Vss .................... - 0.5V to
+ 6.5V
Power Dissipation ............•............. 1.5W
(Based on Package heat transfer limitations, not device power consumption)
'OTP only.
Operating Conditions: T A (under bias) =
DC CHARACTERISTICS
Symbol
O'C to
+ 70'C, Vee =
5.0V
± 20%; Vss = OV
(Over Operating Conditions)
Parameter
Targeted
Min
Targeted
Typ(1)
Targeted
Max
Unit
VIL
Input Low Voltage
(except Port 2 and EA)
-0.5
0.2 Vee - 0.1
V
VIL1
Input Low Voltage
(Port 2)
-0.5
0.2 Vee - 0.3
V
VIL2
Input Low Voltage
(EA)
a
0.2 Vee - 0.3
V
VIH
Input High Voltage
(exceptXTAL1 and RST)
VIH1
Input High Voltage
(XTAL 1, RST)
VOL
Output Low Voltage
(Ports 1, 2, 3, 4 and 5)
VOL1
VOH
VOH1
0.2 Vee
+ 0.9
0.7 Vee
Output Low Voltage
(Port 0, PSEN, ALE)
Output High Voltage
(Ports 1, 2, 3, 4 and 5,
ALE, PSEN)
Output High Voltage
(Port in External
Bus Mode)
a
Vee
+ 0.5
V
Vee
+ 0.5
V
. 0.3
V
0.45
V
1.0
V
0.3
V
0.45
V
1.0
V
Vee - 0.3
V
Vee - 0.7
V
Vee - 1.5
V
Vee - 0.3
V
Vee - 0.7
V
Vee - 1.5
V
9-63
Test Conditions
= 100 J.A-A (2,3)
= 1.6 mA (2,3)
IOL = 3.5 mA (2,3)
IOL = 200 J.A-A (2,3)
IOL = 3.2 mA (2,3)
IOL = 7.0 mA (2;3)
IOH = -10 J.A-A (4)
IOH = -30 J.A-A (4)
IOH = -60 J.A-A (4)
IOH = -200J.A-A
IOH = -3.2 mA
IOH = -7.0 mA
IOL
IOL
87C51 GB/83C51GB/80C51GB
DC CHARACTERISTICS
Symbol
(Over Operating Conditions) (Continued)
Parameter
III
Logical 0 Input Current
(Ports 1, 2, 3, 4, 5)
ITl
LogicaI1-to-0 Transition
Current (Ports 1, 2, 3, 4, 5)
III
Input Leakage Current
(Port 0)
RRST
RST Pullup Resistor
CIO
Pin Capacitance
Ipo
Power Down Current
Min
Typ(1)
50
Max
Unit
-50
p,A
VIN = 0.45V
-650
p,A
VIN.= 2.0V
±10
p,A
0.45
300
k!l
10
50
IOL
Idle Mode Current
18
Icc
Operating Current
50
IREF
AID Converter Reference
Current
5
Test Conditions
< VIN < VCC
pF
Freq = 1 MHz
TA = 25°C
p,A
rnA
rnA
rnA
(5)
(5)
(5)
NOTES:
1. Typical values are obtained using Vee = 5.0V, TA = 25°C, and are not guaranteed.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per Port Pin:
10 mA
Maximum IOL per a-Bit PortPort 0:
26 mA
15 mA
Ports 1-5:
Maximum TotaiiOL for All Outputs Pins: 101 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V on the low level outputs of ALE and
Ports 1.. 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1"10 O. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
o.av. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic:
4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 Vee specification when the
address lines are stabilizing.
5. See Figures 6-10 for test conditions. Minimum Vee for Power Down is 2V.
9-64
int:et
87C51 GB/83C51GB/80C51 GB
60mA
SOmA
~AX •
• OmA
30mA
AC~
20mA
.OmA
.....
-
~
IDLE
~
OmA
OMHz
--
~
~
TYPICAL ______
MAX.
_
TYPICAL -
IOLE
4MHz
BMHz
12MHz
16 114Hz
270869-8
270869-7
All other pins disconnected.
TCLCH = TCHCL = 5 ns
ICC Max at other frequencies is given by:
Active Mode
Icc Max = (OSC Freq x 3) + 4
Idle Mode
IcC Max = (Osc Freq x 0.5) + 4
Where Osc Freq is in MHz, Icc is in mAo TCLCH = TCHCL = 5 ns
Figure 7. Icc Test Condition,
Active Mode
Figure 6. Icc vs Frequency
Vee
Vee
PO
BXC51GB
-=
-=
270869-9
270869-10
All other pins disconnected.
All other pins disconnected.
TCLCH = TCHCL = 5 ns
Figure 9. Icc Test Condition, Power Down Mode
Vcc = 2.0V to 5.5V
Figure 8. Icc Test Condition Idle Mode
270869-11
Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH
=
TCHCL
=
5 ns.
AC SPECIFICATIONS
Over Operating Conditions, Load Capacitance on Port 0, ALE, and PSEN
other outputs = 80 pF
=
100 pF, Load Capacitance on all
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
1/TCLCL
Osc. Freq.
TLHLL
ALE Pulse Width
12 MHzOsc.
Min
Max
Variable Osc.
Units
Min
Max
3.5
16
127
2TCLCL - 40
MHz
ns
TAVLL
AD DR Valid to ALE Low
43
TCLCL - 40
ns
TLLAX
ADDR Hold after ALE Low
53
TCLCL - 30
ns
9-65
intel .
87C51GB/83C51GB/80C51GB
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS (Continued)
Symbol
Parameter
12 MHzOsc.
Min
TLLlV
ALE Low to Valid Inst. IN
TLLPL
ALE LOW to PSEN LOW
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid Instr In
TPXIX
Input Instr. Hold after PSEN
Variable Osc.
Min
Max
Max
4TCLCL - 100
234
Units
ns
53
TCLCL - 30
ns
205
3TCLCL - 45
ns
3TCLCL - 105
145
0
0
ns
ns
TPXIZ
Input Instr. Float after PSEN
59
TCLCL - 25
ns
TAVIV
ADDR to Valid Instr. In
312
5TCLCL - 105
ns
10
ns
10
TPLAZ
PSEN Low to AD DR Float
TRLRH
RD Pulse Width
400
TWLWH
WR Pulse Width
400
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold after RD
TRHDZ
Data Float after RD
107
2TCLCL - 60
ns
TLLDV
ALE Low to Valid Data In
517
8TCLCL - 150
ns
TAVDV
ADDR to Valid Data In
585
9TCLCL - 165
ns
+ 50
ns
6TCLCL - 100
ns
6TCLCL - 100
ns
5TCLCL - 165
252
0
0
300
3TCLCL - 50
ns
ns
TLLWL
ALE Low to RD or WR Low
200
TAVWL
ADDR Valid to RD or WR Low
203
4TCLCL - 130
3TCLCL
ns
ns
TQVWX
Data Valid to WR Transition
33
TCLCL - 50
TWHQX
Data Hold after WR
33
TCLCL - 50
ns
TQVWH
Data Valid to WR High
433
7 TCLCL - 150
ns
TRLAZ
RD Low to Addr Float
TWHLH
RD or WR High to ALE High
0
123 .
43
ns
0
TCLCL - 40
TCLCL
+ 40
ns
L: Logic Level LOW, or ALE
P:PSEN
Q: Output Data
R: RD Signal
T:Time
V: Valid
W: WR Signal
X: No Longer a Valid Logic Level
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a "Tn (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for:
A: Address
C: Clock
D: Input Data
H: Logic Level HIGH
I: Instruction (Program Memory Contents)
Z: Float
For Example:
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
9-66
int:et
87C51GB/83C51GB/80C51GB
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE _ _..I
PSEN _ _..I
TPXIZ
PORT 0
PORT 2
AO-A7
----'
A8-A1S
----'
270869-12
EXTERNAL DATA MEMORY READ CYCLE
ALE
PSEN
'I
i+-----TLLDV
----0-1---- TRLRH - - - + I
INSTR. IN
PORTO
PORT2
_-'l~
_ _ _P2.0-P2.7
___
_ _ _ _ _ _ _ _J~_ _
_ _ _ ____
OR A8-A15 FROM DPH
A8-A15 FROM PCH
270869-13
EXTERNAL DATA MEMORY WRITE CYCLE
,
ALE
X
-TLHLL-
\.
/
4TWHLH
J
-TLLWL
.....
TAVLL
-
-TLLAX-
,
TWLWH
j
....
~
I-TWHQX
TQVWH
PORTO
~
rROll~i~k DPL
DATA OUT
K XAO- A7 FROM PCL
INSTR. IN
TAVWL
PORT2
:::::)
P2.0-P2.7 OR A8-A15 FROM DPH
X
AB-A15 FROM PCH
270869-14
9-67
in1:et
87C51GB/83C51GB/80C51GB
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: Over Operating Conditions, Load Capacitance = 80 pF
12MHz
Symbol
TXLXL
Serial Port Clock
Cycle Time
TQVXH
Output Data Setup to
Clock Rising Edge
Output Data Hold after
Clock Rising Edge
TXHQX
Variable
Oscillator
Oscillator
Min
Max
1
Parameter
TXHDX
Input Data Hold after
Clock Rising Edge
TXHDV
Clock Rising Edge to
Input Data Valid
Min
12TCLCL
Units
Max
I-I-s
700
10TCLCL - 133
ns
50
2TCLCL - 117
ns
0
0
ns
700
10TCLCL - 133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRU~ION
I
4
ALE
CLOCK
OUTPUT DATA
o
WRITE TO SBUF
I
J
TXHDV
INPUT DATA
1
t
I
2
JrTXHDX
SET TI
----~AU:':lDV-+..~UD:V--U~AU':'!\D~~'~UDV-~~AU~D,--~AL:':lIDV-~VA~L",.,..-U~AU~D
t
SET RI
CLEAR RI
270869-15
EXTERNAL CLOCK DRIVE
Symbol
1/TCLCL
Oscillator Frequency
Parameter
TCHCX
High Time
TCLCX
Low Time
TCLCH
TCHCL
Rise Time
Fall Time
Min
3.5
20
20
Max
16
20
20
Units
MHz
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
270869-16
9-68
intel..
87C51GB/83C51GB/80C51GB
SEP AC TIMING SPECiFICATIONS
Test Conditions: Over Operating Conditions, Load Capacitance = 80 pF
Symbol
12MHz
Oscillator
Parameter
Variable
Oscillator
Max
Min
TXSXL
SEPCLK Cycle Time
1
TXSST
Output Data Setup to SEPCLK
TXSOH
Output Data Hold after SEPCLK
TXSIH
Input Data Hold after SEPCLK
Sampling Edge
210
2 TCLCL
Units
Max
Min
12 TCLCL
p.s
435
6 TCLCL - 65
ns
445
6 TCLCL - 55
ns
+ 43
ns
""-
TXSDV
Input Data Valid to SEPCLK
Sampling Edge
SEP Waveform
(SEPS1
=
0; SEPSO
=
0; CLKPOL
r-
-!
SEPCLK
12 TCLCL - 53
947
=
=
0; CLKPH
TXSXL
~ •••••
SEPIO
(OUTPUT)
0)
1-"""""--,.
IL
..... f..'"---_}
-
270869-22
MSB
DATA SHIFT
SEPIO
(INPUT)
LSB
t
1
I
I
I:i
t
f-- TXSIH
~
MSB
DATA SAMPLED
t
t
t
TXSDV
..... 'E)
LSB
t
9-69
t
270869-23
ns
intel .
87C51GB/83C51GB/80C51GB
ACTESTING INPUT, OUTPUT WAVEFORMS
V -0.5
FLOAT WAVEFORMS
_ _ _......_ _ _.;...._
~ 0.2 VCC+O.9
~
0.45V ~...0_.2_V.;:CC;:;.-_0_.I_ _ _ _ _ _" - - - -
CC
270869-17
270869-18
Ae inputs during testing are driven at Vcc-0.5V for a Logic
For timing purposes a port pin is no longer floating
when a 100 mV change from load voltage occurs,
and begins to float when a 100 mV change from
the loaded VOHIVOl level occurs. IOl/lOH :2: ±20
"1" and 0.5V for a Logic "0". Timing measurements are
made at VIH for a Logic "1" and VOL max for a Logic "0".
mAo
A TO D CHARACTERISTICS
OPERATING CONDITIONS
The absolute conversion accuracy is dependent on
the accuracy of AVREF. The specifications given below assume adherence to the Operating Conditions
section of this data sheet. Testing is done at
AVREF = 5.12V, and Vee = 5.0V.
Vee ............................... 4.0V to 6.0V
AVREF .......................... , .. 4.5V to 5.5V
Vss, AVss .................................. OV
ACHO-7 .............. , ........... AVSStoVREF
T A ....................... O·C to + 70'C Ambient
FOSC (STD Version) ........... 3.5 MHz to 12 MHz
FOSC (-1 Version) ............. 3.5 MHz to 16 MHz
AID CONVERTER SPECIFICATIONS
Parameter
Resolution
Min
= O'Cto +70'C
Typ·
Max
256
256
TA
Units··
8
8
Levels
Bits
Absolute Error (Ch 2-7)
0
±1
LSB
Absolute Error (Ch 0 and 1)
0
±2
LSB
Full Scale Error
±1
Zero Offset Error
LSB
±1
LSB
Non-Linearity
0
±1
LSB
Differential Non-Linearity
0
±1
LSB
Channel-to-Channel Matching
0
±1
LSB
Repeatability
±O.25
9-70
LSB
Notes
int:el.
87C51GB/83C51 GB/80C51 GB
AID CONVERTER SPECIFICATIONS
Parameter
TA
Min
=
O·C to
Typ'
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
Max
Vcc Power Supply Rejection
Units"
Notes
LSBrC
LSBrC
LSBrC
3
pF
dB
(8,9)
-60
dB
(8)
dB
(8)
-60
Off Isolation
. Feedthrough
DC Input Leakage
(Continued)
0.003
0.003
0.003
Input Capacitance
Input Resistance to
Sample-and-Hold Capacitor
+ 70·C
-60
750
1.2K
n
0
3.0
/-LA
NOTES:
"These values are expected for most parts at 25·C
"" AN "LSB" as used here, has a value of approximately 20 mV.
8. DC to 100 KHz.
9. Multiplexer Break·Before-Make Guaranteed.
10. There is no indication when a single AID conversion is complete. Please refer to the 8XC51GB Hardware Description on
how to read a single AID conversion.
11. TCy = 12 TCLCL
AID Conversion Time
Per Channel
8 Conversions
I
I
Notes
26TCY
(10,11)
208 TCY
(11 )
9-71
87C51GB/83C51GB/80C51GB
PROGRAMMING THE OTP
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of a location to. be programmed is applied to address lines while the code
byte to be programmed in that location is applied to
data lines. Control and program signals must be held
at the levels indicated in Table 2. Normally EAlVpp
is held at logic t.!!a.h until just before ALE/PROG is to
be pulsed. The EAlVpp is raised to Vpp, ALE/PROG
is pulsed low and then EAlVpp is returned to a high
(also refer to timing diagrams).
ADDRESS LINES: P1.0-P1.7, P2.0-P2.4, respectively for AO-A 12.
DATA LINES: PO.0-PO.7 for 00-07.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EAlVpp
NOTE:
Exceeding the Vpp maximum for any amount of
time could damage the device permanently. The
Vpp source must be well regulated and free of
glitches.
+5V
22-29
AD-A7
57-61
A8-A12
87C51GB
PI
56
P2.0P2.4
EA/Vpp
p. ROGRAM
}
55
ALEjiiRoG 1 - - - - SIGNALS
54
PSEN
64
P2.7
63
P2.6
38
CONTROL SIGNALS'
P3.7
37
P3.6
34
P3.3
3D
RST
270869-19
'See Table 2 for proper input on these pins.
Figure 11. Programming the OTP
Table 2. OTP Programming Modes
Mode
Program Code Data
RST
PSEN
ALE I
PROG
EAI
L
L
L.r
12.75V
P2.6
P2.7
P3.3
P3.6
P3.7
L
H
H
H
H
H
L
L
L
H
H
Vpp
Verify Code Data
L
L
H
Program Encryption
Array Address 0-3FH
L
L
L.r
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
L
L
L.r
12.75V
H
H
H
H
H
Bit 2
L
L
L.r
12.75V
H
H
H
L
L
Bit3
L
L
L.r
12.75V
H
L
H
H
L
L
H
H
H
L
L
L·
L
L
Read Signature Byte
9-72
intel"
87C51GB/83C51GB/80C51GB
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 11 and 12 for address,
data, and control signals set up. To program the
87C51 GB the following sequence must be exercised.
PROGRAM VERIFY
1. Input the valid address on the address lines.
Program verity may be done after each byte that is
programmed, or after a block of bytes that is programmed. In either case a complete verity of the
array will ensure that it has been programmed correctly.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of controlsignals.
4. Raise EAlVpp from Vee to 12.75V ±O.25V.
5. Pulse ALE/PROG 5 times for the OTP array, and
25 times for the encryption table and the lock bits.
ADDRESS
X""'""-"-_ _ _x
13 BITS
X_________X
X_________X
DATA
8 BITS
CONTROL
SIGNALS
7 BITS
12.7SV
EA/Vpp
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled. Refer to the Program Lock section in this data sheet.
I
sv..J
'-
TGLGH
ALE/PROG
270869-20
Figure 12. Programming Signal's Waveforms
9-73
intel .
87C51GB/83C51GB/80C51GB
When using the encryption array feature, one important factor needs to be considered. If a code byte
has the value OFFH, verification of the byte will produce the encryption byte value. If a large block (>64
bytes) of code is left unprogrammed, a verification
routine will display the contents of the encryption
array. For this reason it is strongly recommended
that all unused code bytes be programmed with
some value other than OFFH, and not all of them the
same value. This practice will ensure the maximum
possible program protection.
ROM and EPROM Lock System
The 87C51GB and the 83C51GB program lock systems, when programmed, protect the on-board program against software piracy.
The 83C51GB ha:s a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
3. If program protection is desired, the user submits
the encryption table with their code, and both the
lock bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the
user must submit an encryption table.
Program Lock Bits
The 87C51GB has 3 programmable lock bits that
when programmed according to Table 3 will provide
different levels of protection for the on-chip code
and data. The 83C51 GB has 1 program lock bit.
See line 2 of Table 3.
The 87C51GB has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, all locations are user programmable. See Table 3.
Encryption Array
Reading the Signature Bytes
Within the programmable array are 64 bytes of Encryption Array that are initially unprogrammed (all
1's). Every time that a byte is addressed during a
verify, 5 address lines are used to select a byte of
the Encryption Array. This byte is then exclusiveNOR'ed (XNOR) with the code byte, creating an Encryption Verify byte. The algorithm, with the array in
the unprogrammed state (all 1's), will return the
code in its original, unmodified form. For programming the Encryption Array, refer to Table 2.
The 8XC51GB has 3 signature bytes in locations
30H, 31 H, and 60H. To read these bytes follow the
procedure for verify, but activate the control lines
provided in Table 2 for Read Signature Byte.
Contents
Location
87C51GB
83C51GB
89H
89H
30H
31H
58H
58H
60H
EBH
EBH/6BH
Table 3. Program Lock Bits and the Features
·Program Lock Bits
Protection Type
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled. (Code verify will
still be encrypted by the Encryption Array if
programmed).
2
P
U
U
MOVC instructions executed from external program
memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is
disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
• Any other combination of lock bits
IS
not defined.
9-74
intel~
87C51 GB/83C51 GB/80C51 GB
OTP PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA
= 21°C to 27"C; Vee = 5V ± 20%; Vss = OV)
Symbol
Units
Parameter
Min
Max
Vpp
Programming Supply Voltage
12.5
13.0
V
Ipp
Programming Supply Current
75
mA
6
MHz
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
4
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
(Enable) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
fLs
TGHSL
Vpp Hold afterPROG
10
fLs
TGLGH
PROGWidth
90
TAVQV
Address to Data Valid
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
48TCLCL
110
fLs
48TCLCL
48TCLCL
48TCLCL
fLs
PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
AO-A 12
VERIFICATiON
----~C=~A~DD~R~ES~S~
ADDRESS
TAVQV
00-07
-----K=~:i!:~
TGHDX
ALE!PROG - - - - - -... 1
EA/Vpp
CONTROL
SIGNALS
vee
EA/HIGH
----..I
TELQV
TEHQZ
---"I.I---------------,I,---'"'\.L,.....-----
---Ji'---------------"i"----'l'Io.....----270869-21
'25 Pulses for Encryption Table and Lock Bits.
9-75
inteL
87C51GB/83C51GB/80C51 GB
Ideal Characteristic-A characteristic with its first
code transition at VIN = 0.5 LSB, its last code transition at VIN = (VREF - 1.5 LSB) and all code
widths equal to one LSB.
AID Glossary of Terms
Absolute Error-The maximum difference between
corresponding actual and ideal code transitions. Absolute Error accounts for all deviations of an actual
converter from an ideal converter.
Input Resistance-The effective series resistance
from the analog input pin to the sample capacitor.
Actual Characteristic-The characteristic of an actual converter. The characteristic of a given converter may vary over temperature, supply voltage, and
frequency conditions. An actual characteristic rarely
has ideal first and last transition locations or ideal
code widths. It may even vary over multiple conversions under the same conditions.
LSB-Least Significant Bit-The voltage corresponding to the full scale voltage divided by 2 n, '
where n is the number of bits of resolution of the
converter. For an a-bit converter with a reference
voltage of 5.12V, one LSB is 20 mV. Note that this is
different than digital LSBs since an uncertainty of
two LSBs, when referring to an AID converter,
equals 40 mV. (This has been confused with an uncertainty of two digital bits, which would mean four
counts, or 80 mV).
Break-Before-Make-The property of a multiplexer
which guarantees that a previously selected channel
will be deselected before a new channel is selected
(e.g., the converter will not short inputs together).
Monotonic-The property of successive approximation converters which guarantees that increasing
input voltages produce adjacent codes of increasing
value, and that decreasing input voltages produce
adjacent codes of decreasing value.
Channel-to-Channel Matching-The difference between corresponding code transitions of actual characteristics taken from different channels ,under the
same temperature, voltage and frequency conditions.
'
No Missed Codes-For each and every output
code, there exists a unique input voltage range
which produces that code only.
Characteristlc-A graph of input voltage versus the
resultant output code for an AID converter. It describes the transfer function of the AID converter.
Non-Linearity-The maximum deviation of code
transitions of the terminal based characteristic from
the corresponding code transitions of the ideal characteristic.
Code-The digital value output by the converter.
Code Center-The voltage corresponding to the
midpoint between two adjacent code transitions.
Off-Isolation-Attenuation of a voltage applied on a
deselected channel of the AID converter. (Also referred to as Crosstalk.)
Code Transition-The point at which the converter
changes from an output code of Q, to a code of Q +
1. The input voltage corresponding to a code transition is defined to be that voltage which is equally
likely to produce either of two adjacent codes.
Repeatability":"The difference between' corresponding code transitions from different actual characteristics taken from the same converter on the
same channel at the same temperature, voltage and
frequency conditions.
Code Width-The voltage corresponding to the difference between two adjacent code transitions.
DC Input Leakage-Leakage current to ground
from an analog input pin.
Resolution-The number of input voltage levels
that the converter can unambiguously distinguish
between. Also defines the number of useful bits of
information which the converter can return.
Differential Non-Linearity-The difference between the ideal and actual code widths of the terminal based characteristic.
Sample Delay-The delay from receiving the start
conversion Signal to when the sample window
opens.
Feedthrough-Attenuation of a voltage applied on
the selected channel of the AID Converter after the
sample window closes.
Sample Delay Uncertainty-The variation in the
sample delay.
Crosstalk-5ee "Off-Isolation".
Sample Time-The time that the sample window is
open.
Full Scale Error-The difference between the expected and actual input voltage corresponding to
the full scale code transition.
Sample Time Uncertainty-The variation in the
sample time.
9-76
int'el..
87C51GB/83C51GB/80C51GB
The following differences exist between the 270869002 data sheet and the previous version (270869001):
1. Changed data sheet status from "Product Preview" to "Advance Information" and updated associated notices.
2. Asynchronous port reset was added to RESET
pin description.
3. ALE disable paragraph was added to ALE pin description.
4. C1. C2 guidelines clarified in Figure 4.
5. Operating Conditions heading was added.
6. Maximum IOL per 110 pin was added to Absolute
Maximum Ratings.
Sample Window-Begins when the sample capacitor is attached to a selected channel and ends when
the sample capacitor is disconnected from the selected channel.
Successive Approximation-An AID conversion
method which uses a binary search to arrive at the
best digital representation of an analog input.
Temperature Coefflcients-Change in the stated
variable per degree centrigrade temperature
change. Temperature coefficients are added to the
typical values of a specification to see the effect of
temperature drift.
Terminal Based Characteristic-An actual characteristic which has been rotated and translated to remove zero offset and full scale error.
7. VT +. VT -. VHYS. VOL2. and VTL removed.
8. VOL value for ALE included with VOL1.
Vee Rejection-Attenuation of noise on the Vcc
line to the AID converter.
9. VIL 1 and VIL2 added.
10. RRST minimum changed from 40K to 50K.
RRST maximum changed from 225K to 300K.
11. Ipo maximum changed from 200 p.A to 50 p.A.
12. IOL maximum changed from 15 mA to 18 mAo
Zero Offset-The difference between the expected
and actual input voltage corresponding to the first
code transition.
13. Typical values for Ipo. IOL. Icc. and IREF removed.
14. Note 3 (page 9) was reworded.
15. SEP AC Timings added.
16. AID Absolute Error for Channels 0 and 1
changed to ± 2 LSB.
DATA SHEET REVISION SUMMARY
The following differences exist between this data
sheet and the previous version (270869-002):
1. Changed data sheet status from "Advance Information" to "Preliminary" and updated associated
notices.
2. Added 83C51GB throughout.
17. TCY clarified.
18. Encryption array paragraph was added.
19. Corrected pin numbers on Figure 11 to reflect
PLCC package.
3. Added Package and Process Information.
4. Clarified ± 2 LSB accuracy for channels 0 and 1
in AID Converter Section.
5. Added "ROM and EPROM Lock System" section
and added 83C51 GB to "Program Lock Bits"
section.
6. Modified Signature Bytes Table.
9-77
87C51GB/80C51GB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Express
87C51GB-8K Bytes OTP/Factory
grammable ROM
80C51GB-CPU with RAM and 110
3.5 MHz-16 MHz ± 20% Vee
Temperature Range
• (-Extended
40°C to + 85°C)
On-Chip ROM/OTP ROM
• 8K256Bytes
of On-Chip Data RAM
• TwoBytes
Programmable Counter Arrays
• with:
- 2 x 5 High Speed Input/Output
Channels Compare/Capture
- Pulse Width Modulators
- Watchdog Timer Capabilities
16-Bit Timer/Counters with
• -Three
Four Programmable Modes:
- Capture, Baud Rate Generation
(Timer 2)
Watchdog Timer
• Dedicated
A/D with:
• -a-Bit,Eight8-Channel
8-Bit Result Registers
- Four Programmable Modes
Serial Channel with:
• -Programmable
Framing Error Detection
- Automatic Address Recognition
Expansion Port
• Serial
Programmable Clock Out
•
Pro-
I/O Lines with:
• -48 40Programmable
Schmitt Trigger Inputs
Sources with:
• -15 7Interrupt
External, 8 Internal Sources
- 4 Programmable Priority Levels
Port States
• Pre-Determined
High Performance CHMOS Process
• TTL and CHMOS Compatible Logic
• Levels
Power Saving Modes
• 64K
Data Memory Space
• 64K External
Program Memory Space
• ThreeExternal
Level Program Lock System
• ONCETM (ON-Circuit Emulation) Mode
• Quick Pulse Programming™ Algorithm
• MCS®-51 Fully Compatible Instruction
• Set
Boolean Processor
• Oscillator
Detect
• Available inFall68-Pin
PLCC
•
The Intel EXPRESS system offers enhancements to the operation specifications of the MCS-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose .
operating requirements exceed commercial standards.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of Q·C to + 7Q·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 4Q·C to + 85·C.
The 87C51GB EXPRESS is packaged in the 58-lead PLCC package. In order to designate a part as an
EXPRESS part, a 'T' is added as a prefix to the part number. TN87C51 GB denotes an EXPRESS part in a
PLCC package.
All A.C. and D.C. parameters in the commercial data sheets apply to the EXPRESS devices.
9-78
July 1990
Order Number: 270889-001
83C152 Hardware
Description and Data Sheet
10
intel·
August 1990
83C152 Hardware Description
Order Number: 270427-004
10-1
II
CONTENTS
83C152 HARDWARE
DESCRIPTION
PAGE
1.0 INTRODUCTION .................... 10-3
2.0 COMPARISON OF 80C152 AND
80C51BH FEATURES ............. 10-3
2.1 Memory Space .................. 10-3
2.2 Interrupt Structure .............. 10-11
2.3 Reset .......................... 10-12
2.4 Ports 4,5 and 6 ................. 10-13
2.5 Timers/Counters ............... 10-13
2.6 Package .................. ~ ..... 10-13
2.7 Pin Description ................. 10-14
2.S Power Down and Idle ........... 10-17
2.9 Local Serial Channel ............ 10-17
3.0 GLOBAL SERIAL CHANNEL ...... 10-17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.S
Introduction .....................
CSMAlCD Operation ...........
SDLC Operation ................
User Defined Protocols .........
Using the GSC ..................
GCS Operation .................
Register Descriptions ...........
Serial Backplane vs Network
Environment ... : ..............
10-17
10-20
10-27
10-34
10-34
10-42
10-44
10-47
4.0 DMA OPERATION ................. 10-47
4.1
4.2
4.3
4.4
4.5
DMA with the SOC152 ...........
Timing Diagrams ................
Hold/Hold Acknowledge ........
DMA Arbitration .................
Summary of DMA Control Bits ...
10-47
10-50
10-50
10-55
10-59
5.0 INTERRUPT STRUCTURE ......... 10-60
5.1 GSC Transmitter Error
Conditions .................... 10-62
5.2 GSC Receiver Error
Conditions ................. '... 10-63
6.0 GLOSSARy ........................ 10-64
10-2
83C152 HARDWARE DESCRIPTION
use of external program memory. The second difference
is that RESET is active low in the 83CI52 and active
high in the 80C5lBH. This is very important to.designers who may currently be using the 80C5lBH and plan1
ning to use the 83C152, or are planning on using both
devices on the same board. The third difference is that
GFO and GFI, general purpose flags in PCON, have
been renamed GFIEN and XRCLK. GFIEN enables
idle flags to be generated in SDLC mode, and XRCLK
enables the receiver to be externally clocked. All of the
previously unused bits are now being used and interrupt vectors have been added to support the new enhancements. Programmers using old code generated for
the 80CS lBH will have to examine their programs to
ensure that new bits are properly loaded, and that the
new interrupt vectors will not interfere with their program.
1.0 INTRODUCTION
, The 83CIS2 Universal Communications Controller is
an 8-bit microcontroller designed for the intelligent
management of peripheral systems or components. The
83CIS2 is a derivative of the 80CS IBH and retains the
same functionality. The 83CIS2 is fabricated on the
same CHMOS III process as the 80C51BH. What
makes the 83CIS2 different is that it has added functions and peripherals to the basic 80C5lBH architec~
ture that are supported by new Special Function Registers (SFRs). These enhancements include: a high speed
multi-protocol serial' communication interface, two
channels for DMA transfers, HOLD/HLDA bus control, a fifth I/O port, expanded data memory, and expanded program memory.
In addition to a standard UART, referred to here as
Local Serial Channel (LSC), the 83CI52 has an onboard multi-protocol communication controller called
the Global Serial Channel (GSC). The GSC interface
supports SDLC, CSMA/CD, user definable protocols,
and a subset of HDLC protocols. The GSC capabilities
include: address recognition, collision resolution, CRC
generation, flag generation, automatic retransmission,
and a hardware based acknowledge feature. This high
speed serial channel is capable of implementing the
Data Link Layer and the Physical Link Layer as shown
in the OSI open systems communication model. This
model can be found in the document "Reference Model
for Open Systems Interconnection Architecture",
ISO/TC97/SCI6 N309.
Throughout the rest of this manual the 80CI52 and the
83CIS2 will be referred to generically as the "CI52".
The CI52 is based on the 80CSIBH architecture and
utilizes the same 80C51BH instruction set. Figure 1.1 is
a block diagram of the C152. Readers are urged to
compare this block diagram with the 80CS lBH block
diagram. There have been no new instructions added.
All the new features and peripherals are supported by
an extension of the Special Function Registers (SFRs).
Very little of the information pertaining specifically to
the 80C5lBH core will be discussed in this chapter.
The detailed information on such functions as: the instruction set, port operation, timer/counters, etc., can
be found in the MCS®-51 Architecture chapter in the
Intel Embedded Controller Handbook. Knowledge of
the 80C5lBH is required to fully understand this manual and the operation of the C152. To gain a basic understanding on the operation of the 80CS lBH, the
reader should familiarize himself with the entire MCSSI chapter of the Embedded Controller Handbook.
The DMA circuitry consists of two 8-bit DMA channels with 16-bit addressability. The control signals;
Read (RD), Write (WR), hold and hold acknowledge
(HOLD/HLDA) are used to access external memory.
The DMA channels are capable of addressing up to
64K bytes (16 bits). The destination or source address
can be automatically incremented. The lower 8 bits of
the address are multiplexed on the data bus Port 0 and
the upper eight bits of address will be on Port 2. Data is
transmitted over an 8-bit address/data bus. Up to 64K
bytes of data may be transmitted for each DMA activation.
Another source of information that the reader may find
helpful is Intel's LAN Components User's Manual, order number 230814. Inside are descriptions of various
protocols, application examples, and application notes
dealing with different serial communication environments.
The new I/O port (P4) functions the same as Ports 1-3,
found on the 80C5lBH.
2.0 COMPARISON OF 80C152 AND
80C51BH FEATURES
Internal memory has been doubled in the 83ClS2. Data
memory has been expanded to 256 bytes, and internal
program memory has been expanded to 8K bytes.
2.1 Memory Space
There are also some specific differences between the
83CI52 and the 80C5lBH. The first is that the numbering system between the 83CI52 and the 80CSIBH is
slightly different. The 83CIS2 and the 80C5lBH are
factory masked ROM devices. The 80CI52 and the
80C3lBH are ROMless devices which require the
A good understanding of the memory space and how it
is used in the operation of MCS-Sl products is essential. All the enhancements on the CIS2 are implemented by accessing Special Function Registers (SFRs),
added data memory, or added program memory.
10-3
II
_.
P4.0-P4.7
PO.O-PO.7
€:
P2.0-P2.7
8
~~d
SARL1
II
II
SARHI
OARL1
DARHI
BCRL1
BciiHl-1
II
CO
(0)
0
......
UI
N
'TI
..
IE
c
ID
:..
-'"
0
III
:t:
~
1.£1
::D
c
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./:. 0'
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::D
m
~
C
C
m
.
en
3
:u-I
iii'
e
0
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::D
5Z
MYSLOT
P1.0- P1.7
ADRO-3
IFS
BAUD
TCDCNT
P3.0- P3.7
270427-7
inteL
83C152 HARDWARE DESCRIPTION
(IDA), Source Address Space bit (SAS), Increment
Source Address bit (ISA), DMA Channel Mode bit
(DM), Transfer Mode bit (TM), DMA Done bit
(DONE), and the GO bit (GO). DCONO is used to
control DMA Channel o.
2.1.1 SPECIAL FUNCTION REGISTERS (SFRs)
The following list contains all the SFRs, their names
and function. All of the SFRs of the 80C5lBH are retained and for a detailed explanation of their operation,
please refer to the chapter, "Hardware Description of
the 8051 and 8052" that is found in the Embedded
Controller Handbook. An overview of the new SFRs is
found in Section 2.1.1.1, with a detailed explanation in
Section 3.7, Section 4.5, and 6.0.
DCONl - (93H) Same as DCONO except this is for
DMA Channell.
GMOD - (84H) Contains the Protocol bit (PR), the
Preamble Length (PLI,O), CRC Type (CT), Address
Length (AL), Mode select (Ml,O), and External Transmit Clock (TXC). This register is used for GSC operation only.
2.1.1.1 New SFRs
The following descriptions are quick overviews of the
new SFRs, and not intended to give a complete understanding of their use. The reader should refer to the
detailed explanation in Section 3 for the GSC SFRs,
and Section 4 for the DMA SFRs.
lENl - (OC8H) Interrupt enable register for DMA and
GSC interrupts.
IFS - (OA4H) Determines the number of bit times separating transmitted frames.
ADR 0,1,2,3 - (95H, OA5H, OB5H, OC5H) Contains
the four bytes for address matching during GSC operation.
IPNl - (OF8H) Interrupt priority register for DMA
and GSC interrupts.
AMSKO - (ODSH) Selects "don't care" bits to be used
with ADRO.
MYSLOT - (OF5H) Contains the Jamming mode bit
(DCJ), the Deterministic Collision Resolution Algorithm bit (DCR), and the DCR slot address for the
GSC.
AMSKI - (OE5H) Selects "don't care" bits to be used
with ADRI.
P4 - (OCOH) Contains the memory "image" of Port 4.
BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will
equal (fosc)!«BAUD+ I) X 8).
PRBS - (OE4H) Contains a pseudo-random number to
be used in CSMA!CD backoff algorithms. May be read
or written to by user software.
BCRLO - (OE2H) Contains the low byte of a countdown counter that determines when the DMA access
for Channel 0 is complete.
RFIFO - (F4H) RFIFO is used to access a 3-byte FIFO
that contains the receive data from the GSc.
BCRHO - (OE3H) Contains the high byte for countdown counter for Channel o.
BCRHI - (OF3H) Same as BCRHO except for DMA
Channell.
RSTAT - (OE8H) Contains the Hardware Based Acknowledge Enable bit (HABEN), Global Receive Enable bit (GREN), Receive FIFO Not Empty bit
(RFNE), Receive Done bit (RON), CRC Error bit
(CRCE), Alignment Error bit CAE), Receiver Collision!Abort detect bit (RCABT), and the Overrun bit
(OVR), used with both DMA and GSC.
BKOFF - (OC4H) An 8-bit count-down timer used
with the CSMA!CD resolution algorithm.
SARLO - (OA2H) Contains the low byte of the source
address for DMA transfers.
DARLO - (OC2H) Contains the low byte of the destination address for DMA Channel O.
SARHO - (OA3H) Contains the high byte of the source
address for DMA transfers.
DARHO - (OC3H) Contains the high byte of the destination address for DMA Channel o.
SARLI - (OB2H) Same as SARLO but for DMA Channell.
DARLI - (OD2H) Same as DARLO except for DMA
Channell.
SARHl - (OB3H) Same as SARHl but for DMA Channel 1.
DARHl - (OD3H) Same as DARHO except for DMA
Channel 1.
SLOTTM - (OB4H) Determines the length of the slot
time in CSMA!CD.
DCONO - (92H) Contains the Destination Address
Space bit (DAS), Increment Destination Address bit
TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using CSMA!CD GSC.
BCRLl - (OF2H) Same as BCRLO except for DMA
Channell.
10-5
•
intet
83C152 HARDWARE DESCRIPTION
Old(O)lNew(N)
Name
Addr
Function
0
A
ADRO
ADR1
ADR2
ADR3
AMSKO
AMSK1
B
BAUD
BCRLO
BCRHO
BCRL1
BCRH1
BKOFF
DARLO
DARHO
DARL1
DARH1
DCONO
DCON1
DPH
DPL
GMOD
IE
IEN1
IFS
IP
IPN1
MYSLOT
PO
P1
P2
P3
P4
P5
P6
PCON
PRBS
PSW
RFIFO
RSTAT
SARLO
SARHO
SARL1
SARH1
SBUF
SCON
SLOTTM
SP
TCDCNT
TCON
TFIFO
THO
TH1
TLO
TL1
TMOD
TSTAT
OEOH
095H
OA5H
OB5H
OC5H
OD5H
OE5H
OFOH
094H
OE2H
OE3H
OF2H
OF3H
OC4H
OC2H
OC3H
OD2H
OD3H
092H
093H
083H
082H
084H
OA8H
OC8H
OA4H
OB8H
OF8H
OF5H
080H
090H
OAOH
OBOH
OCOH
091H
OA1H
087H
OE4H
ODOH
OF4H
OE8H
OA2H
OA3H
OB2H
OB3H
099H
098H
OB4H
081H
OD4H
088H
085H
08CH
08DH
08AH
08BH
089H
OD8H
ACCUMULATOR
I
GSC MATCH ADDRESS 0
GSC MATCH ADDRESS 1
GSC MATCH ADDRESS 2
GSC MATCH ADDRESS 3 .
GSC ADDRESS MASK 0
GSC ADDRESS MASK 1
B REGISTER
GSC BAUD RATE
DMA BYTE COUNT 0 (LOW)
DMA BYTE COUNT 0 (HIGH)
DMA BYTE COUNT 1 (LOW)
DMA BYTE COUNT 1 (HIGH)
GSC BACKOFF TIMER
DMA DESTINATION ADDR 0 (LOW)
DMA DESTINATION ADDR 0 (HIGH)
DMA DESTINATION ADDR 1 (LOW)
DMA DESTINATION ADDR 1 (HIGH)
DMA CONTROL 0
DMA CONTROL 1
DATA POINTER (HIGH)
DATA POINTER (LOW)
GSCMODE
INTERRUPT ENABLE REGISTER 0
INTERRUPT ENABLE REGISTER 1
GSC INTERFRAME SPACING
INTERRUPT PRIORITY REGISTER 0
INTERRUPT PRIORITY REGISTER 1
GSC SLOT ADDRESS
PORTO
PORT 1
PORT 2
PORT 3
PORT4
PORT 5
PORT 6
POWER CONTROL
GSC PSEUDO-RANDOM SEQUENCE
PROGRAM STATUS WORD
GSC RECEIVE BUFFER
RECEIVE STATUS (DMA & GSC)
DMA SOURCE ADDR 0 (LOW)
DMA SOURCE ADDR 0 (HIGH)
DMA SOURCE ADDR 1 (LOW)
DMA SOURCE ADDR 1 (HIGH)
LOCAL SERIAL CHANNEL (LSC) BUFFER
LOCAL SERIAL CHANNEL (LSC) CONTROL
GSC SLOT TIME
STACK POINTER
GSC TRANSMIT COLLISION COUNTER
TIMER CONTROL
GSC TRANSMIT BUFFER
TIMER 0 (HIGH)
TIMER 1 (HIGH)
TIMER 0 (LOW)
TIMER 1 (LOW)
TIMER MODE
TRANSMIT STATUS (DMA & GSC)
N
N
N
N
N
N
0
N
N
N
N
N
N
N
N
N
N
N
N
0
0
N
0
N
N
0
N
N
0
0
0
0
N
N
N
0
N
0
N
N
N
N
N
N
0
0
.N
0
N
0
N
0
0
0
0
0
N
,
10-6
83C152 HARDWARE DESCRIPTION
TFIFO - (85H) TFIFO is used to access a 3-byte FIFO
that contains the transmission data for the GSC.
TSTAT - (OD8H) Contains the DMA Service bit
(DMA). Transmit Enable bit (TEN). Transmit FIFO
Not Full bit (TFNF). Transmit Done bit (TDN).
Transmit Collision Detect bit (TCDT). Underrun bit
(UR). No Acknowledge bit (NOACK). and the Receive Data Line Idle bit (LNI). This register is used
with both DMA and GSC.
The general purpose flag bits (GFO and GF1) that exist
on the 80C51BH are no longer available on the C152.
GFO has been renamed GFIEN (GSC Flag Idle Enable) and is used to enable idle fill flags. Also GFI has
been renamed XRCLK (External Receive Clock Enable) and is used to enable the receiver to be clocked
externally.
2.1.2 DATA MEMORY
Internal data memory consists of 256 bytes as shown in
Figure 2.1. The first 128 bytes are addressed exactly
like an 80C51BH. using direct addressing.
The addresses of the second 128 bytes of data memory
happen to overlap the SFR addresses. The SFRs and
their memory 10cationF are shown in Figure 2.2. This
means that internal data memory spaces have the same
address as the SFR address. However. each type of
memory is addressed differently. To access data memory above 80H. indirect addressing or the DMA channels must be used. To access the SFRs. direct addressing is used. When direct addressing is used. the address
is the source or destination. e.g. MOV A. lOH, moves
the contents of location 10H into the accumulator.
When indirect addressing is used. the address of the
destination or source exists within another register. e.g.
MOV A. @RO. This instruction moves the contents of
the memory location addressed by RO into the accumulator. Directly addressing the locations 80H to OFFH
will access the SFRs. Another form' of indirect addressing is with the use of Stack Pointer Operations. If the
Stack Pointer contains an address and a PUSH or POP
instruction is executed, indirect addressing is actually
used. Directly accessing an unused SFR address will
give undefined results.
Physically. there are separate SFR memory and data
memory spaces allocated on the chip. Since there are
separate spaces. the SFRs do not diminish the available
data memory space.
OFFH
OFFH
(0)
(0)
OVERLAPPING
IAEIAORY
A
(0)
oaOH
(0)
SPECIAL FUNCTION REGISTER
SPACE
02FH
BIT ADDRESSABLE
MEIAORY SPACE
020H
01FH
REGISTER BANK 3
017H
REGISTER BANK 2
010H
REGISTER BANK 1
007H
REGISTER BANK 0
OOOH
USER DATA MEMORY SPACE
270427-1
o NOTE:
User data memory above BOH must be addressed indirectly. Using direct addressing above BOH accesses the Special
Function Registers.
Figure 2.1. Data Memory Map
'10-7
intel~
83C152 HARDWARE DESCRIPTION
External data memory is accessed like an 80C51BH,
with "MOVX" instructions. Addresses up to 64K may
be accessed when using the Data Pointer (DPTR).
When accessing external data memory with the DPTR,
the address appears on Port 0 and 2. When using the
DPTR, if less than 64K of external data memory is
used, the address is emitted on all sixteen pins. This
means that. when using the DPTR, the pins of Port 2
not used for addresses cannot be used for general purpose I/O. An alternative to using 16-bit addresses with
the DPTR is to use RO or RI to address the external
data memory. When using the registers to address external data memory, the address range is limited to 256
bytes. However, software manipulation of I/O Port 2
pins as normal I/O, allows this 256 bytes restriction to
be expanded via bank switching. When using RO or RI
as data pointers, Port 2 pillS that are not used for addressing, can be used as general purpose I/O.
(O)IPNl
2.1.2.1 Bit Addressable Memory
The Cl52 has .several memory spaces in which the bits
are directly addressed by their location. The directly
addressable bits and their symbolic names are shown in
Figure 2.3A, 2.3B, and 2.3C.
Bit addresses 0 to 7FH reside in on-board user data
RAM in byte addresses 20H to 2FH (see Figure 2.3A).
Bit addresses 80H to OFFH reside in the SFR memory
space, but not every SFR is bit addressable, see Figure
2.3B. The addressable bits are scattered throughout the
SFRs. The addressable bits occur every eighth SFR address starting at 80H and occupy the entire byte. Most
of the bits that are addressable in the SFRs have been
given symbolic names. These names will often be referred to in this or other documentation on the C152.
Most assemblers also allow the use of the symbolic
names when writing in assembly language. These
names are shown in Figure 2.3C.
PGSTE POIIA 1 PGSlV PIllotAO PGSRE PGSRV OF8H
IoIYSLOT DCJ
RFIFO
BCRHl
BCRLl
OCR
SAS
SA4
SA3
SA2
SAl
SAO
RO
OFOH
(0) IE
EA
RFNE OREN HABEN OEBH
AORl
'I.
(O)B
'II.
'II. 'II.
'I.
CRCE
'I.
RDN
(O)A
(O)TSTAT
OE4H
OE3H
OE2H
'i-
'i-
'iOEOH
LNI
NOACK
UR
TCDT
TON
TFNF
TEN
DIIA
AIoISKO
TCOCNT
DARH 1
CARLl
OOSH
004H
003H
002H
'1/1.
(O)PSW
ODBH
eY
AC
'I.
'I.
FO
'I.
'II. 'II.
RSl
RSO
P
AOR3
BKOFF
DARHO
DARLO
OCSH
OC4H
OC3H
OC2H
(0)P4
OCOH
'I.
'II. 'II.
(O)IP
'I.
PS
'I.
'II. 'II.
PTl
THl
THO
TLl
TLO
'I.
PTO
'I.
PXO
0BOH
EXO
0A8H
EXl
ETC
'II.
'I.
OB8H
'I.
TB8
RB8
ISA
ISA
OM
OM
TM
TM
!"'.:>~~~~!-'t~~~~~"'.:~~~"'.:~~~"""""
P.4,5
P4.S
P4.6
P4.6
P4.7
P4.7
N.C.
PS.3
EA
EA
ALE
ALE
PSEN
PSEN
fiiSfN
N.C.
80C152JA/ JC
83C152JA/JC
P3.4
P6.2
PS.7
P5.1
P6.4
P3.3
N.C.
N.C.
PS.2
N.C.
PS.3
P2.7
P3.S
P2.6
P2.S
N.C.
P2.7
P3.S
P2.6
P3.6
P3.6
P2.S
P3.7
P2."
P3.7
N.C.
N.C.
P2.!
P2."
P2.3
270427-37
270427-6
Figure 2.58. PLCC Pin Out
Figure 2.5C. PLCC Pin Out
2.7 Pin Description
The pin description for the 80C5lBH also applies to the C152 and is listed below. Changes have been made to the
descriptions as they apply to the C152.
PIN DESCRIPTION
Pin #
DIP
PLCC(1)
Description
,
48
2
Vcc-Supply voltage.
24
3,33(2)
VSS-Circuit ground.
18-21,
25-28
27-30,
34-37
Port O-Port 0 is an 8-bit open drain bi-directionall/O port. As an output port each
pir can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the
multiplexed data bus. In these applications it uses strong internal pullups when
emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
required during program verification.
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-14
int:et
83C152 HARDWARE DESCRIPTION
PIN DESCRIPTION (Continued)
Pin #
DIP
1-8
Description
PLCC(1)
4-11
Port 1-Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pull ups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
29-36
41-48
Pin
Name
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
GRXD
GTXD
DEN
TXC
RXC
HLD
HLDA
Alternate Function
GSC data input pin
GSC data output pin
GSC enable signal for an external driver
GSC input pin for external transmit clock
GSC input pin for external receive clock
DMA hold input/output
DMA hold acknowledge input! output
Port 2-Port 2 is an 8-bit bi-directionall/O port with internal pull ups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled low. During accesses to external Data Memory that use
16-bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order
address byte. In these applications it uses strong internal pullups when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
10-17
47-40
14-16,
18,19,
23-25
65-58
Port 3-Port 3 is an 8-bit bi-directionall/O port with internal pullups. Port 3 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special features of the MCS-51 Family,
as listed below:
Pin
Name
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD
TXD
INTO
INT1
TO
T1
WR
RD
Alternate Function
Serial input line
Serial output line
External interrupt 0
External interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe .
Port 4-Port 4 is an 8-bit bi-directionall/O port with internal pullups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-15
III
intel·
83C152 HARDWARE DESCRIPTION
PIN DESCRIPTION (Continued)
Pin #
DIP
Description
PLCC(1)
9
13
RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a poweron reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be,
transmitted for up to 4 machine cycles after Reset is first applied.
38
55
ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of % the oscillator frequency,
and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external Data Memory. While in Reset,
ALE remains at a constant high level.
37
54
PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.
39
56
EA-External Access enable. EA must be externally pulled low in order to enable
the8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
I
EA must be connected to VCC for internal program execution.
23
32
22
31
XTAL2-Output from the oscillator amplifier.
N/A
17,20
21,22
38,39
40,49
Port 5-Port 5 is an 8-bit bi-directionall/O port with internal pullups. Port 5 pins
that have 1s written to them are pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 5 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups.
Port 5 is also the multiplexed low-order address and'data bus during accesses to
external program memory if EBEN is pulled high. In this application it uses strong
pullups when emitting 1s.
N/A
67,66
52,57
50,68
1,51
Port 6-Port 6 is an 8-bit bi-directionall/O port with internal pullups. Port 6 pins
that have 1s written to them are pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 6 pins that are externally pulled low will
source current (IlL, on the data sheet) because of the internal pullups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. 'In this application it uses, strong pullups when
emitting 1s.
N/A
12
EBEN-E-Bus Enable input that designates whether program memory fetches take
place via Ports 0 and 2 or Ports 5 and 6. Table 2.1 shows how the ports are used in
conjunction with EBEN.
53
EPSEN-E-bus Program Store Enable is the Read strobe to external program
memory when EBEN is high. Table 2.1 shows when EPSEN is used relative to
PSEN depending on the status of EBEN and EA.
XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.
NOTES:
1, N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
10-16
int:et
83C152 HARDWARE DESCRIPTION
2.8 Power Down and Idle
2.9 Local Serial Channel
Both of these operations function identically as. in the
80C5IBH. Application Note 252, "Designing with the
80C51BH" gives an excellent explanation on the use of
the reduced power consumption modes. Some of the
items not covered in AP-252 are the considerations that
are applicable when using the GSC or DMA in conjunction with the power saving modes.
The Local Serial Channel (LSC) is the name given to
the UART that exists on all MCS-51 devices. The
LSC's function and operation is exactly the same as on
the 80C51BH. For a description on the use of the LSC,
refer to the 8051/52 Hardware Description Chapter in
the Intel Embedded Controller Handbook, under Serial
Interface.
The GSC continues to operate in Idle as long as the
interrupts are enabled. The interrupts need to be enabled, so that the CPU can service the FIFO's. In order
to properly terminate a reception or transmission the
C152 must not be in idle when the EOF is transmitted
or received. After servicing the GSC, user software will
need to again invoke the Idle command as the CPU
does not automatically re-enter the Idle mode after
servicing the interrupts.
The GSC does not operate while in Power Down so the
steps required prior to entering Power Down become
more complicated. The sequence when entering Power
Down and the status of the I/O is of major importance
in preventing damage to the C152 or other components
in the system. Since the only way to exit Power Down
is with a Reset, several problem areas become very significant. Some of the problems that merit careful consideration are cases where the Power Down occurs during the middle of a transmission, and the possibility
that other stations are not or cannot enter this same
mode. The state of the GSC I/O pins becomes critical
and the GSC status will need to be saved before power
down is entered. There will also need to be some method of identifying to the CPU that the following Reset is
probably not a cold start and that other stations on the
link may have already been initialized.
The DMA circuitry stops operation in both Idle and
Power Down modes. Since operation is stopped in both
modes, the process should be similar in each case. Specific steps that need to be taken include: notification to
other devices that DMA operation is about to cease for
a particular station or network, proper withdrawal
from DMA operation, and saving the status of the
DMA channels. Again, the status of the I/O pins during Power Down needs careful consideration to avoid
damage to the C152 or other components.
Port 4 returns to its input state, which is high level
using weak pullup devices.
3.0 GLOBAL SERIAL CHANNEL
3.1 Introduction
The Global Serial Channel (GSC) is a multi-protocol,
high performance serial interface targeted for data rates
up to 2 MBPS with on-chip clock recovery, and 2.4
MBPS using the external clock options. In applications
using the serial channel, the GSC implements the Data
Link Layer and Physical Link Layer as described in the
ISO reference model for open systems interconnection.
The GSC is designed to meet the requirements of a
wide range of serial communications applications and is
optimized to implement Carrier-Sense Multi-Access
with Collision Detection (CSMA/CD) and Synchronous Data Link Control (SDLC) protocols. The GSC
architecture is also designed to provide flexibility in defining non-standard protocols. This provides the ability
to retrofit new products into older serial technologies,
as well as the development of proprietary interconnect
schemes for serial backplane environments.
The versatility of the GSC is demonstrated by the wide
range of choices available to the user. The various
modes of operation are summarized in Table 3.1. In
subsequent sections, each available choice of operation
will be explained in detail.
In using Table 3.1, the parameters listed vertically (on
the left hand side) represent an option that is selected
(X): The parameters listed horizontally (along the top
of the table) are all the parameters that could theoretically be selected (Y). The symbol at the junction of
both X and Y determines the applicability of the option
Y.
Note, that not all combinations are backwards compatible. For example, Manchester encoding requires half
duplex, but half duplex does not require Manchester
encoding.
10-17
intel~
83C152 HARDWARE DESCRIPTION
Table 3.1
AVAILABLE
OPTIONS
-+
N = NOT AVAILABLE
M=MANDATORY
O=OPTIONAL
P = NORMALLY PREFERRED
X=N/A
DATA
ENCODING
M
A
N
N
N
R
R
Z
Z
I
C
H
E
S
T
FLAGS
0
1
1
1
1
1
1
0
1
1
/
I
D
L
E
DUPLEX
CRC
N
0
N
E
E
1
6
B
I
3
2
B
I
T
T
C
C
I
Ii.
T
0
H
A
L
F
F
U
L
L
ACKNOWLEDGE
D
N
L
E
0
T
T
N
8
B
I
M
A
E
E
E
T
R
R
N
A
T
M
E
E
I
S
D
T
N
A
S
E
R
D
E
0
R
D
R
F
E
I
E
W
U
T
PREAMBLE
R
U
A
N
N
BACKOFF
0
H
0
N
8
B
I
E
T
/
A
L
L
1
6
B
I
T
N
L
N
R
i
ADDRESS
RECOGNITION
A
I
N
I
C
SELECTED
FUNCTION
DATA ENCODING:
MANCHESTER(CSMAlCD)
X
N
N
1
P
1
0
0
M
N
0
0
0
0
0
0
0
0
0
N
0
NRZI (SDLC)
N
x
N
P
1
1
0
0
0
0
0
N
P
0
0
0
N
N
N
0
0
NRZ (EXT CLK)
N
N
X
0
0
1
0
0
0
0
0
N
0
0
0
0
0
0
0
0
0
FLAGS:01111110 (SDLC)
N
P
0
X
1
1
0
0
0
0
0
N
P
0
0
0
N
N
N
0
0
P
N
0
1
X
1
0
0
0
N
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
X
N
N
1
N
1
1
1
1
1
1
N
N
N
1
1
16-BITCCITI
0
0
0
0
0
N
X
N
0
0
0
0
0
0
0
0
0
0
0
0
0
32-BIT AUTODIN II
11/IDLE
CRC:NONE
0
0
0
0
0
N
N
X
0
N
0
0
0
0
0
0
0
0
0
0
0
DUPLEX:HALF
0
0
0
0
0
1
0
0
X
N
0
0
0
0
0
0
0
0
0
0
0
FULL
N
0
0
M
N
N
M
N
N
X
0
N
P
0
0
0
N
N
N
0
0
0
0
0
0
0
1
0
0
0
0
X
N
N
0
0
0
0
0
0
0
0
HARDWARE
0
N
N
N
0
1
0
0
0
N
N
X
N
0
0
0
N
0
0
N
0
USER DEFINED
0
P
0
0
0
1
0
0
0
P
N
N
X
0
0
0
0
0
0
0
0
ACKNOWLEDGEMENT:NONE
ADDRESS RECOGNITION:
NONE/ALL
0
0
0
0
0
1
0
0
0
0
0
0
0
X
N
N
0
0
0
0
0
8-BIT
0
0
0
0
0
1
0
0
0
0
0
0
0
N
X
N
0
0
0
0
0
16-BIT
0
0
0
0
0
1
0
0
0
0
0
0
0
N
N
X
0
0
0
0
0
COLLISION RESOLUTION:
NORMAL
0
N
0
N
0
N
0
0
M
N
0
N
0
0
0
0
X
N
N
N
0
ALTERNATE
0
N
0
N
0
N
0
0
M
N
0
0
0
0
0
0
N
X
N
N
0
DETERMINISTIC
0
N
0
N
0
N
0
0
M
N
0
0
0
0
0
0
N
N
X
N
0
N
0
0
0
1
1
0
0
0
0
0
N
0
0
0
0
N
N
N
X
N
8-BIT
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
N
X
32-BIT
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
N
N
64-BIT
PREAMBLE:NONE
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
N
N
JAM:D.C.
M
N
N
N
0
N
0
0
M
N
0
0
0
0
0
0
0
0
0
N
0
CRC
M
N
N
N
0
N
0
0
M
N
0
0
0
0
0
0
0
0
0
N
0
N
M
N
a
0
N
0
0
0
0
0
N
0
0
0
0
N
N
N
0
0
0
0
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLOCKING:EXTERNAL
INTERNAL
CONTROL: CPU
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAW RECEIVE:
1
1
1
1
1
1
1
1
1
N
1
1
1
1
1
1
0
0
0
1
1
RAW TRANSMIT:
1
1
1
1
1
1
1
1
1
N
1
1
1
1
1
1
N
N
N
1
1
CSMAlCD:
0
N
N
1
P
1
0
0
M
N
0
0
0
0
0
0
0
0
0
N
0
SDLC:
N
0
0
P
1
1
0
0
0
0
0
N
0
0
0
0
N
N
N
P
0
DMA
10-18
inteL
83C152 HARDWARE DESCRIPTION
Table 3.1 (Continued)
AVAILABLE
OPTIONS
-+
N= NOT AVAILABLE
M=MANDATORY
O=OPTIONAL
P=NORMALLY PREFERRED
X=N/A
!
PREAMBLE
3
2
B
I
T
6
4
JAM
CLOCK
D
C
C
R
B
I
T
C
I
E
X
T
E
R
N
A
L
I
N
T
E
R
N
A
L
CONTROL
C
P
U
D
M
A
R
A
R
A
C
W
W
R
E
T
R
A
N
S
M
A
C
E
I
V
E
SELECTED
FUNCTION
S
S
0
L
C
I
C
D
M
I
T
DATA ENCODING:
MANCHESTER
0
0
0
0
N
M
0
0
0
0
M
N
NRZI
0
0
N
N
N
M
0
0
0
0
N
M
NRZ
0
0
0
0
M
N
0
0
0
0
0
0
FLAGS:01111110
0
0
N
N
0
0
0
0
0
1
1
P
11/IDLE
0
0
0
0
0
0
0
0
0
1
P
1
1
1
N
N
1
1
1
1
1
1
1
1
16-BITCCITI
0
0
0
0
0
0
0
0
1
1
0
0
32-BIT AUTO DIN II
0
0
0
0
0
0
0
0
1
1
0
0
DUPLEX:HALF
0
0
0
0
0
0
0
0
0
0
0
0
FULL
0
0
N
N
0
0
0
0
N
N
N
P
0
0
0
0
0
0
0
0
0
0
0
0
HARDWARE
0
0
0
0
N
0
0
0
N
N
0
N
USER DEFINED
0
0
0
0
0
0
0
0
0
0
0
1
CRC:NONE
ACKNOWLEDGEMENT:NONE
ADDRESS RECOGNITION:
NONE
0
0
0
0
0
0
0
0
0
0
0
0
8-BIT
0
0
0
0
0
0
0
0
1
1
0
0
16-BIT
0
0
0
0
0
0
0
0
1
1
0
'0
COLLISION RESOLUTION:
NORMAL
0
0
0
0
N
0
0
0
0
N
M
N
ALTERNATE
0
0
0
0
N
0
0
0
0
N
M
N
DETERMINISTIC
0
0
0
0
N
0
0
0
0
N
M
N
N
N
N
N
0
0
0
0
0
0
N
P
N
N
0
0
0
0
0
0
1
1
0
0
32-BIT
X
N
0
0
0
0
0
0
1
1
0
0
64-BIT
N
X
0
0
0
0
0
0
1
1
0
0
JAM:D_C,
0
0
X
N
N
0
0
0
0
N
M
N
CRC
0
0
N
X
N
0
0
0
0
N
M
N
0
0
N
N
X
N
0
0
0
0
N
0
INTERNAL
0
0
0
0
N
X
0
0
0
0
0
0
CONTROL:CPU
0
0
0
0
0
0
X
N
0
0
0
0
0
0
0
0
0
0
N
X
0
0
0
0
RAW RECEIVE:
1
1
0
0
1
1
1
1
X
N
1
1
RAW TRANSMIT:
1
1
N
N
1
1
1
1
N
X
1
1
CSMAlCD:
0
0
0
0
N
0
0
0
0
0
X
N
SDLC:
0
0
N
N
0
0
0
0
0
0
N
X
PREAMBLE:NONE
8-BIT
CLOCKING:EXTERNAL
DMA
10-19
II
intel .
83C152 HARDWARE DESCRIPTION
Note 1: Programmable in Raw transmit or receive
mode.
Almost all the options available from Table 3.1 can be
implemented with the proper software to perform the
functions that are necessary for the options selected. In
Table 3.1, a judgment has been made by the authors on
which options are practical and which are not. What
this means is that in Table 3.1, an "N" should be interpreted as meaning that the option is either not practical
when implemented with user software or that it cannot
be done. An "0" is used when that function is one of
several that can be implemented with the GSC without
additional user software.
The GSC is targeted to operate at bit rates up to 2.4
MBps using the external clock options and up to 2
MBps using the internal baud rate generator, internal
data formatting and on-chip clock recovery. The baud
rate generator allows most standard rates to be
achieved. These standards include the proposed
IEEE802.3 LAN standard (1.0MBps) and the Tl standard (1.544MBps). The baud rate is derived from the
crystal frequency. This makes crystal selection important when determining the frequency and accuracy of
the baud rate.
Th~ user needs to be aware that after reset, the GSC is
in CSMA/CD mode, .IFS = 256 bit times, and a bit
time equals 8 oscillator periods. The GSC will remain
in this mode until the interframe space expires. If the
user changes toSDLC mode or the parameters used in
CSMA/CD, these changes will not take effect until the
interframe space expires. A requirement for the interframe space timer to begin is that the receiver be in an
idle state. This makes it possible for the GSC to be in
some other mode than the user intends for a significant
amount of time after reset. To prevent unwanted GSC
errors from occurring, the user should not enable the
GSC or the GSC interrupts for 170 machine cycles
«256 X 8)/12) after LNI bit is set.
3.2 CSMA/CD Operation
3.2.1 CSMA/CD OVERVIEW
CSMA/CD operates by sensing the transmission line
for a carrier, which indicates link activity. At the" end of
link activity, a station must wait a period of time, called
the deference period, before transmission may begin.
The deference period is also known as the interframe
space. The interframe space is explained in Section
3.2.3.
With this type of operation, there is always the possibility of a collision occurring after the deference period
due to line delays. If a collision is detected after transmission is started, a jamming mechanism is used to ensure that all stations monitoring the line are aware of
the collision. A resolution algorithm is then executed to
resolve the contention. There are three different modeS
of collision resolution made available to the user on the
C152. Re-transmission is attempted when a resolution
algorithm indicates that a station's opportunity has arrived.
Normally, in CSMA/CD, re-transmission slot assignments are intended to be random. This method gives all
stations an equal opportunity to utilize the serial communication link but also leaves the possibility of another" collision due to two stations having the same slot
assignment. There is an option on the C152 which allows all the stations to have their slot assignments previously determined by user software. This pre-assignment of slots is called the deterministic resolution
mode. This method allows resolution after the first collision and ensures the access of the link to each station
during the resolution. Deterministic resolution can be
advantageous when the link is being heavily used and
collisions are frequently occurring and in real time applications where determinism is required. Deterministic
resolution may also be desirable if it is known beforehand that a certain station's communication needs to be
prioritized over those of other stations if it is involved
in a collision.
3.2.2 CSMA/CD FRAME FORMAT
The frame format in CSMA/CD consists of a preamble, Beginning of Frame flag (BOF), address field, information field, CRC, and End of Frame flag (BOF) as
shown in Figure 3.1.
IPREAMBLE IBOF IADDRESS IINFO ICRC IEOF I
Figure 3.1 Typical CSMA/CD Frame
PREAMBLE - The preamble is a series of alternating
Is and Os. The length of the preamble is programmable
to be 0, 8, 32, or 64 bits. The purpose of the preamble is
to allow all the receivers to synchronize to the same
clock edges and identifies to the other stations on-line
that there is activity indicating the link is being used.
For these reasons zero preamble length is not compatible with standard 'CSMA/CD, protocols. When using
CSMA/CD, the BOF is considered part of the preamble compared to SDLC, where the BOF is not part of
the preamble. This means that if zero preamble length
were to be used in CSMA/CD mode, no BOF would be
generated. It is strongly recommended that zero preamble length never be used in CSMA/CD mode. If the
preamble contains two consecutive Os, the preamble is
considered invalid. If the C152 detects an invalid preamble, the frame is ignored.
,
BOF - In CSMA/CD the Beginning-Of-Frame is a part
of the preamble and consists of two sequential Is. The
purpose of the BOF is to identify the end of the preamble and indicate to the receiver(s) that the address will
immediately follow.
10-20
intel·
83C152 HARDWARE DESCRIPTION
ADDRESS - The address field is used to identify which
messages are intended for which stations. The user
must assign addresses to each destination and source.
How the addresses are assigned, how they are maintained, and how each transmitter is made aware of
which addresses are available is an issue that is left to
the user. Some suggestions are discussed in Section
3.5.5. Generally, each address is unique to each station
but there are special cases where this is not true. In
these special cases, a message is intended for more than
one station. These multi-targeted messages are called
broadcast or multicast-group addresses. A broadcast
adqress consisting of all Is will always be received by
all stations. A multicast-group address usually is indicated by using a las the first address bit. The user can
choose to mask off all or selective bits of the address so
that the GSC receives all messages or multicast-group
messages. The address length is programmable to be 8
or 16 bits. An address consisting of all I s will always be
received by the GSC on the C152. The address bits are
always passed from the GSC to the CPU. With user
software, the address can be extended beyond 16 bits,
but the automatic address recognition will only work
on a maximum of 16 bits. User software will have to
resolve any remaining address bits.
INFO - This is the information field and contains the
data that one device on the link wishes to transmit to
another device. It can be of any length the user wishes
but needs to be in multiples of 8 bits. This is because
mUltiples of 8 bits are used to transfer data into or out
of the GSC FIFOs. The information field is delineated
from the rest of the components of the frame by the
preceding address field and the following CRC. The
receiver determines the position of the end of the information field by passing the bytes through a temporary
storage space. When the EOF is received the bytes in
temporary storage are the CRC, and the last bit received previous to the CRC constitute the end of the
information field.
CRC - The Cyclic Redundancy Check (CRC) is an error checking algorithm commonly used in serial communications. The C152 offers two types of CRC algorithms, a 16-bit ~nd a 32-bit. The l6-bit algorithm is
normally used in the SDLC mode and will be described
in the SDLC section. In CSMA/CD applications either
algorithm can be used but IEEE 802.3 uses a 32-bit
CRC. The generation polynomial the C152 uses with
the 32-bit CRC is:
G(X) = X32 + X26 + X23 + X22 + X16 + X12 +
X" + XIO + X8 + X7 + X5 + X4 + X2
+X+l
The CRC generator, as shown in Figure 3.2, operates
by taking each bit as it is received and XOR'ing it with
bit 31 of the current CRC. This result is then placed in
temporary storage. The result of XOR'ing bit 31 with
the received bit is then XOR'd with bits 0, I, 3, 4, 6, 7,
9, 10, 11, 15,21,22,25 as the CRC is shifted right one
position. When the CRC is shifted right, the temporary
storage space holding the result of XOR'ing bit 31 and
the incoming bit is shifted into position O. The whole
process is then repeated with the next incoming or outgoing bit.
The user has no access to the CRC generator or the bits
which constitute the CRC while in CSMA/CD. On
transmission, the CRC is automatically appended to
the data being sent, and on reception, the CRC bits are
not normally loaded into the receive FIFO. Instead,
they are automatically stripped. The only indication the
user has for the status of the CRC is a pass/fail flag.
The pass/fail flag only operates during reception. A
CRC is considered as passing when the the CRC generator has 11000111 00000100 11011010 OIIIIOIIB as a
remainder after all of the data, including the CRC
checksum, from the transmitting station has been cycled through the CRC generator. The preamble, BOF
and EOF are not included as part of the CRC algorithm. An interrupt is available that will interrupt the
CPU if the CRC of the receiver is invalid. The user can
enable the CRC to be passed to the CPU by placing the
receiver in the raw receive mode.
This method of calculating the CRC is compatible with
IEEE 802.3.
EOF - The End Of Frame indicates when the transmission is completed. The end flag in CSMA/CD consists
of an idle condition. An idle condition is assumed when
there is no transitions and the link remains high for 2 or
more bit times.
10-21
III
I
intel~
83C152 HARDWARE DESCRIPTION
270427-8
Figure 3.2. CRe Generator
3.2.3 INTERFRAME SPACE
The interframe space is the amount of time that transmission is delayed after the link is sensed as being idle
and is used to separate transmitted frames. In alternate
backoff mode, the interframe space may also be included in the determination of when retransmissions may
actually begin. The. C152 allows programmable interframe spaces of even numbers of bit times from 2 to
256. The hardware enforces the interframe space in
SDLC mode as well as in CSMA/CD mode.
The period of the interframe space is determined by the
contents of IFS. IFS is an SFR that is programmable
from 0 to 254. The interframe space is measured in bit
times. The value in IFS multiplied by the bit time
equals the interframe space unless IFS equals O. If IFS
does equal 0, then the interframe space will equal 256
bit times. One of the considerations when loading the
IFS is that only even numbers (LSB must be 0) can be
used because only the 7 most significant bits are loaded
into IFS. The LSB is controlled by the GSC and determines which half of the IFS is currently being used. In
some modes, the interframe space timer is re-triggered
if activity is detected during the first half of the period.
The GSC determines which half of the interframe space
is currently being used by examining the LSB. A one
indicates the first half and zero indicates the second
half of the IFS.
After reset IFS is 0, which delays the first transmission
for both SDLC and CSMA/CD by 256 bit times (after
reset, a bit time equals 8 oscillator clock periods).
In most applications, the period of the interframe space
will be equal to or greater than the amount of time
needed to turn-around the received frame. The turnaround period is the amount of time that is needed by
USter software to complete thte handling of a received
frame and be prepared to receive the next frame. An
interframe space smaller than the required turn-around
period could, be used, but would allow some frames to
be missed.
When a GSC transmitter has a new message to send, it
will first sense the link. If activity is detected, transmission 'will be deferred to allow the frame in progress to
complete. When link activity ceases, the station continues deferring for one interframe space period.
As mentioned earlier, the interframe space is used during the collision resolution period as well as during normal transmission. The backoff method selected affects
how the deference period is handled during normal
transmission. If normal backoff mode is selected, the
interframe spacte timer is reset if activity occurs during
approximately the first half of the interframe space. If
alternate backoff or dteterministic backoff is selected,
the timer is not reset. In all cases when the interframe
space timer expires, transmission may begin, regardless
if there is activity on the link or not. Althou&h the
C152 resets the interframe space timer if activity is detected during the first one-half of the interframe space,
this is not nectessarily true of all CSMA/CD systems.
(IEEE 802.3 recommends that the interframe space be
reset if activity is detected during the first two-thirds or
less of the interframe space.)
10-22
infel"
83C152 HARDWARE DESCRIPTION
3.2.4 CSMA/CD DATA ENCODING
Narrow Pulses
Manchester encoding/decoding is automatically selected when the user software selects CSMA/CO transmission mode (See Figure 3.3). In Manchester encoding
the value of the bit is determined by the transition in
the middle of the bit time, a positive transition is decoded as a I and a negative transition is decoded as a O.
The Address and Info bytes are transmitted LSB first.
The CRC is transmitted MSB first.
A valid Manchester waveform must stay high or low
for at least a half bit-time, nominally· 4 sample-times.
Jitter tolerance allows a waveform which stays high or
low for 3 sample-times to also be considered valid. A
sample sequence which shows a second transition only
I or 2 sample-times after the previous transition is considered to be the result of a collision. Thus, sample
sequences such as 0000110000 and 111101111 are interpreted' as collisions.
If the external IX clock feature is chosen the transmission mode is always NRZ (see SeCtion 3.5.11). Using
CSMA/CO with the external clock option is not supported because the data needs reformatting from NRZ
to Manchester for the receiver to be able to detect code
violations and collisions.
3.2.5 COLLISION DETECTION
The GSC hardware detects collisions by detecting Manchester waveform violations at its GRXO pin. Three
kinds of waveform violations are detected: a missing
O-to-l tr.ansition where one was expected, a 1-to-0 transition where none was expected, and a waveform that
stays low (or high) for too short a time.
The GSC hardware recognizes the collision to have oc- •
curred within 3/8 to 1/2 bit-time following the second
transition.
Missing 0-to-1 Transition
A O-to-l transition is expected to occur at the center of
any bit cell that begins with O. If the previous 1-to-0
transition occurred at the bit cell edge, a jitter tolerance
of ± 1 sample is allowed. Sample sequences such as
1111:00001111 and 1111:000001111 are valid, where
U:" indicates a bit cell edge. Sequences of the form
1111 :OOOOOOXXX are interpreted as collisions.
For these kinds of sequences, the GSC recognizes the
collision to have occurred within 1 to 1 1/8 bit-times
after the previous I-to-O transition.
Jitter Tolerance
A valid Manchester waveform must have a transition at
the midpoint of any bit cell, and may have a transition
at the edge of any bit cell. Therefore, transitions will
nominally be separated by either 1/2 bit-time or 1 bittime.
The GSC samples the GRXD pin at the rate of 8 x the
bit rate. The sequence of samples for the received bit
sequence 001 would nominally be:
samples: 1 1 1 1 0 0 0 0 : 1 1 1 1 0 0 0 0 : 00 0 0 1 1 1 1 :
bit value:
0
0
1
: < -bit cell- > : < -bit cell- > : < -bit cell- > :
The sampling system allows a jitter tolerance of ± 1
sample for transitions that are 1/2 bit-time apart, and
± 2 samples for transitions that are 1 bit-time apart.
If the previous I-to-O transition occurred at the center
of the previous bit cell, a jitter tolerance of ± 2 samples
is allowed. Thus, sample sequences such as
11110000:00001111 and 111100000:000001111 are valid. Sequences of the form 111100000:000000XXX are
interpreted as collisions.
For these kinds of sequences, the GSC recognizes the
collision to have occurred within 1 5/8 to 1 3/4 bittimes after the previous I-to-O transition.
Unexpected 1-to-0 Transition
If the line is at a logic 1 during the first half of a bit cell,
then it is expected to make a I-to-O transition at the
midpoint of the bit cell. If the transition is missed, it is
assumed that this bit cell is the first half of an EOF flag
o
o
o
,
BIT
I
-TIME-:
270427-14
Figure 3.3. Manchester Encoding
10-23
I
int:et
83C152 HARDWARE DESCRIPTION
(GREN = 0), and the Receive Error Interrupt flag
RCABT is set. If DCR has been selected, the GSC
participates in the resolution algorithm.
(line idle for two bit-times). One bit-time later (which
marks the midpoint of the next bit cell), if there is still
no I-to-O transition, a valid EOF is assumed and the
line idle,bit (LNI in TSTA1) gets set.
However, if the' assumedEOF flag is interrupted by a
I-to-O transition in the bit-time following the first missing transition, a collision is assumed. In that case the
GSC hardware recognizes the collision to have occurred within 1/2 to 5/8 bit-time after the unexpected I
transition.
3.2.6 RESOLUTION OF COLLISIONS
How the GSC responds to a detected collision depends
on what it was doing at the time the collision was detected. What it might be doing is either transmitting or
receiving a frame, or it might be inactive.
Incoming bits take 1/2 bit time to get from the GRXD
pin, to the bit decoder. The bit decoder strips off the
preamble/BOF bits, and the first bit after BOF is shifted into a serial strip buffer. The length of the strip
buffer is equal to the number of bits in the selected
CRC. It is within this buffer that address recognition
takes place. If the address is recognized as one for
which reception should proceed, then when the first
address bit exits th,e strip buffer it is shifted into an 8-bit
shift register. When the shift register is full, its content .
is transferred to RFIFO. That is the event that determines whether a collision sets RCABT or not.
GSC Transmitting
If the GSC is in the process of transmitting a frame at
the time the collision is detected, it will in every case
execute its jamlbackoff procedure. Its reponse beyond
that depends on whether the first byte of the frame has
been transferred from TFIFO to the output shift register yet or not. That transfer takes place at the beginning
of the fIrSt bit of the BOF; that is, 2 bit-times before the
end of the preamblelBOF sequence.
GSC Inactive
.The collision is detected whether the GSC is active or
not. If the GSC is neither transmitting nor receiving at
the time the collision is detected, it takes no action unless user software has selected the Deterministic Collision Resolution (DCR) algorithm. If DCR has been
selected, the GSC will participate in the resolution algorithm.
If the transfer from TFIFO hasn't occurred yet, the
GSC Receiving
If the GSC is already in the process of receiving a frame
at the time the collision is detected, its response de- ,
pends on whether the first byte of the frame has been
transferred 'into RFIFO yet or not. If that hasn't occurred, the GSC simply aborts the reception, but takes
no other action unless DCR has been selected. If DCR
has been selected, the GSC participates in the resolution algorithm.
If the reception has already progressed to the point
where a byte has been transferred to RFIFO by the
time the collision is detected, the receiver is disabled
GSC hardware will try again to gain access to the line
after its backoff time has expired. Up to 8 automatic
restarts can be attempted. If the 8th restart is iIiterrupted by yet another collision, the transmitter is disabled
(TEN . = 0) and the Transmit Error Interrupt flag
TCDT is set.
If the transfer from TFIFO occurs before a collision is
detected, the transmitter is disabled (TEN = 0) and
the TCDT flag is set.
The response of the GSC to detected collisions is summarized in FigUre 3.4.
What the GSC was doing
Response
nothing
None, unless OCR = 1.
If OCR = 1, begin OCR countdown.
Receiving a Frame, first
byte not in RFIFO yet.
None, unless OCR = 1.
If OCR = 1, begin OCR countdown.
Receiving a Frame, first
byte already in RFIFO.
Set RCABT, clear GREN.
If OCR = 1, begin OCR countdown.
Transmitting a Frame, first
byte still in TFIFO
Execute jam/backoff.
Restart if collision count s; 8.
Transmitting a Frame, first
byte already taken from TFIFO
Execute jam/backoff.
Set TCDT, clear TEN.
Figure 3·4. Response to a Detected Collision. References to DCR and the DCR Countdown
Have to Do with the Deterministic Collision Resolution Algorithm.
10-24
inteL
83C152 HARDWARE DESCRIPTION
Jam
In the Deterministic algorithm, the GSC backs off to
await its pre-determined turn.
The jam signal is generated by any 8XCI52 that is involved in transmitting a frame at the time a collision is
detected at its GRXD pin. This is to ensure that if one
transmitting station detects a collision, all the other stations on the network will also detect a collision.
Random Backott
If a transmitting 8XCI52 detects a collision during the
preamble/BOF part of the frame that it is trying to
transmit, it will complete the preamble/BOF and then
begin the jam signal in the first bit time after BOF. If
the collision is detected later in the frame, the jam signal will begin in the next bit time after the collision was
detected.
The jam signal lasts for the same number of bit times as
the selected CRC length-either 16- or 32-bit times.
The 8XCI52 provides two types of jam signals that can
be selected by user software. If the node is DC-coupled
to the network, the DC jam can be selected. In this case
the GTXD pin is pulled to a logic 0 for the duration of
the jam. If the node is AC-coupled to the network, then '
AC jam must be selected. In this case the GSC takes
the CRC it has calculated thus far in the transmission,
inverts each bit, and transmits the inverted CRC. The
selection of DC or AC jam is made by setting or clearing the DC] bit, which resides in the SFR named
MYSLOT.
When the jam signal is completed, the 8XCI52 goes
into an idle state. Presumeably, other stations on the
network are also generating their own jam signals, after
which they too go into an idle state. When the 8XCI52
detects the idle state at its own GRXD pin, the backoff
sequence begins.
Backott
There are three software selectable collision resolution
algorithms in the 8XC152. The selection is made by
writing values to 3 bits:
DCR
M1
MO
Algorithm
0
0
1
0
1
1
0
1
1
Normal Random
Alternate Random
Deterministic
MI and MO reside in GMOD, and DCR is in
MYSLOT.
In the Normal Random algorithm, the GSC backs off
for a random number of slot times and then decides
whether to restart the transmission. The backoff time
begins as soon as a line idle condition is detected.
In either of the random algorithms, the first thing that
happens after a collision is detected is that a I gets
shifted into the TCDCNT (Transmit Collision Detect
Count) register, from the right.
Thus if the software cleared TCDCNT before telling
the GSC to transmit, then TCDCNT keeps track of
how many times the transmission had to be aborted
because of collisions:
TCDCNT = 00000000
first attempt
00000001
first collision
00000011
second collision
00000111
third collision
00001111
fourth collision
11111111
eighth collision
After TCDCNT gets a
shifted into it, the logical
AND of TCDCNT and PRBS is loaded into a countdown timer named BKOFF. PRBS is the name of an
SFR which contains the output of a pseudo-random
binary sequence generator. Its function is to provide a
random number for use in the backoff algorithm.
Thus on the first collision BKOFF gets loaded randomly with either 00000000 or 0000000 1. If there is a second collision it gets loaded with the random selection of
00000000, 00000001, 00000010, or 00000011. On the
third collision there will be a random selection among 8
possible numbers. On the fourth, among 16, etc. Figure
3.5 shows the logical arrangement ofPRBS, TCDCNT,
and BKOFF.
BKOFF starts counting down from its preload value,
counting slot times. At any time, the current value in
BKOFF can be read by the CPU, but CPU writes to
BKOFF have no effect. While BKOFF is counting
down, if its current value is not 0, transmission is disabled., The output signal "BKOFF = 0" is asserted
when BKOFF reaches 0, and is used to re-enable transmission.
At that time transmission can proceed, subject of
course to IFS enforcement, unless:
• shifting a I into TCDCNT from the right caused a I
to shift out from the MSB of TCDCNT, or
• the collision was detected after TFIFO had been accessed by the transmit hardware.
The Alternate Random algorithm is the same as the
Normal Random except the backoff time doesn't start
until an IFS has transpired.
10-25
II
83C152 HARDWARE DESCRIPTION
SKOFF
=MYSLOT
270427-38
Figure 3.5. Backoff Timer Logic
In either of these cases, the transmitter is disabled
(TEN = 0) and the Transmit Error flag TCDT is set.
The automatic restart is canceled.
Where the Normal and Alternate Random backoff algorithms differ is that in Normal Random backoff ~he
BKOFF timer starts counting down as soon as a Ime
idle condition is detected, whereas in Alternate Random backoff the BKOFF timer doesn't start counting
down till the IFS expires.
The Alternate Random mode was designed for networks in which the slot time is less than the IFS. If the
randomly assigned backoff time for a given transmitter
happens to be 0, then it is free to transmit as soon as the
IFS ends. If the slot time is &horter than the IFS, Normal Random mode would nearly guarantee that if
there's a first collision there will be a second collision.
The situation is avoided in Alternate Random mode,
since the BKOFF countdown doesn't start till the IFS
is over.
The unit of count to the BKOFF timer is the slot time.
The slot time is measured in bit-times, and is determined by a CPU write to the register SLOTTM. The
slot time clock is a I-byte downcounter which starts its
countdown from the value written to SLOTTM. It is
decremented each bit time when a backoff is in progress, and when it gets to I it generates one tick in the
slot time clock. The next state after I is the reload value
which was written to SLOTTM. If 0 is the value written to SLOTTM, the slot time clock will equal 256 bit
times.
A CPU write to SLOTTM accesses the reload register.
A CPU read of SLOTTM accesses the downcounter. In
most protocols, the slot period must be equal to or
greater than the longest round trip propagation time
plus the jam time.
Deterministic Backoff
In the Deterministic backoff mode, the GSC is assigned
(in software) a slot number. The slot assignment is wri~
ten to the low 6 bits of the register MYSLOT. This
same register also contains, in the 2 high bit positions,
the control bits DCJ and DCR.
Slot assignments therefore can run from 0 to 63. It will
turn out that the higher the slot assignment, the sooner
the GSC will get to restart its transmission in the event
of a collision.
The highest slot assignment in the network is w~tten
by each station's software into its TCDCNT register.
Normally the highest slot assignment is just the total
number of stations that are going to participate in the
backoff algorithm.
In deterministic backoff mode a collision will not cause
a I to be shifted into TCDCNT. TCDCNT will still be
ANDed with PRBS and the result loaded into BKOFF.
In order to insure that all stations have the same value
loaded into BKOFF, which determines the first slot
number to occur, the PRBS should be loaded with
OFFH; the PRBS will maintain this value until either
the 8XCI52 is reset or the user writes some other value
into PRBS. After BKOFF is loaded it begins counting
down slot times as soon as the IFS ends. Slot times are
defiried by the user, the same way as before, by loading
SLOTTM with the number of bit times per slot.
10-26
infel .
83C152 HARDWARE DESCRIPTION
When BKOFF equals the slot assignment (as defined in
MYSLOT), the signal "BKOFF = MYSLOT" in Figure 3.5 is asserted for one slot time, during which the
GSC can restart its transmission.
While BKOFF is counting down, if any activity is detected at the GRXO pin, the countdown is frozen until
the activity ends, a line idle condition is detected, and
an IFS transpires. Then the countdown resumes from
where it left off.
If a collision is detected at the GRXO pin while
BKOFF is counting down, the collision resolution algorithm is restarted from the beginning.
In effect, the GSC "owns" its assigned slot number, but
with one. exception. Nobody owns slot number 0.
Therefore if the GSC is assigned slot number 0, then
when BKOFF = 0, this station and any other station
that has something to say at this time will have an
equal chance to take the line.
A transmitting station with HABEN enabled expects
an acknowledge. It must receive one prior to the end of
the interframe space, or else an error is assumed and
the NOACK bit is· set. Setting of the TON bit is also
delayed until the end of the interframe space. Collisions
detected during the interframe space will also cause
NOACK to be set.
If the user software has enabled OMA servicing of the
GSC, an interrupt is generated when TON is set. TON
will be set at the end of the interframe space if a hardware based acknowledge is required and received. If the
GSC is serviced by the CPU, the user must time out the
interframe space and then check TON before disabling
the transmitter or transmit error interrupts. NOACK
will generate a transmit error interrupt if the transmitter and interrupts are enabled during the interframe
space.
3.3 SOLe Operation
3.2.7 HARDWARE BASED ACKNOWLEDGE
3.3.1 SDLC OVERVIEW
Hardware Based Acknowledge (HBA) is a data link
packet acknowledging scheme that the user software
can enable with CSMA/CO protocol. It is not an option with SOLC protocol however.
SOLC is a communication protocol developed by IBM
and widely used in industry. It is based on a primary/
secondary architecture and requires that each secondary station have a unique address. The secondary stations can only communicate to the primary station, and
then, only when the primary station allows communication to take place. This eliminates the possibility of
contention on the serial line caused by the secondary
station's trying to transmit simultaneously.
In general HBA can give improved system response
time and increased effective transmission rates over acknowledge schemes implemented in higher layers of the
network architecture. Another benefit is the possibility
of early release of the transmit buffer as soon as the
acknowledge is received.
The acknowledge consists of a preamble followed by an
idle condition. A receiving station with HABEN enabled will send an acknowledge only if the incoming
address is unique to the receiving station and if the
frame is determined to be correct with no errors. For
the acknowledge to be sent, TEN must be set. For the
transmitting station to recognize the acknowledge
GREN must be set. A zero as the LSB of the address
indicates that the address is unique and not a group or
broadcast address. Errors can be caused by collisions,
incorrect ·CRC, misalignment, or FIFO overflow. The
receiver sends the acknowledge as soon as the line is
sensed to be idle. The user must program the interframe
space and the preamble length such that the acknowledge is completed before IFS expires. This is normally
done by programming IFS larger than the preamble.
In the C152, SOLC can be configured to work in either
full or half duplex. When adhering to strict SOLC protocol, full duplex is required. Full duplex is selected
whenever a 16-bit CRC is selected. At the end of a valid
reset the 16-bit CRC is selected. To select half duplex
with a 16-bit CRC, the receiver must be turned off by
user software before transmission. The receiver is
turned off by clearing the GREN bit (RSTAT.l). The
receiver needs to be turned off because the address that
is transmitted is the address of the secondary station's
receiver. If not turned off, the receiver could mistake
the outgoing message as being intended for itself. When
32-bit CRCs are used, half duplex is the only method
available for transmission.
10-27
II
I
83C152 HARDWARE DESCRIPTION
3.3.2 SOLC Frame Format
The format of an SDLC frame is shown in Figure 3.6.
The frame consists of a Beginning of Frame flag, Address field, Control Field, Information field (optional),
a CRC, and the End of Frame flag.
IBOF , ADDRESS' CONTROL 'INFO' CRC , EOF ,
Figure 3.6. Typical SOLC Frame
BOF - The begin of frame flag for SDLC is 01111110.
It is only one of two possible combinations that have six
consecutive ones in SDLC. The other possibility is an
abort character which consists of eight or more consecutive ones. This· is because SDLC utilizes a process
called bit stuffing. Bit stuffing is the insertion of a 0 as
the next bit every time a sequence of five consecutive Is
is detected. The receiver automatically removes a 0 after every consecutive group of five ones. This removal
of the 0 bit is referred to as bit stripping. Bit stuffing is
discussed in Section 3.3.4. All the procedures required
for bit stuffing and bit stripping are automatically handled by the GSC.
In standard SDLC protocol the BOF signals the start of
a frame and is limited to 8 bits in length. Since there is
no preamble in SDLC the BOF is considered an entire
separate field and marks the beginning of the frame.
The BOF also serves as the clock synchronization
mechanism and the reference point for determining the
position of the address and control fields.
ADDRESS - The address field is used to identify which
stations the message is intended for. Each secondary
station must have a unique address. The primary station must then be made aware of which addresses are
assigned to each station. The address length is specified
as 8-bits in standard SDLC protocols but it is expandable to 16-bits in the C152. User software can further
expand the number of address bits, but the automatic
address recognition feature works on a maximum of 16bits.
..
In SDLC the addresses are normally unique for each
station. However, there are several classes of messages
that are intended for more than one station. These messages are called broadcast and group addressed frames.
An address consisting of allIs will always be automatically received by the GSC, this is defined as the broadcast address in SDLC. A group address is an address
that is common to more than one station. The GSC
provides address masking bits to provide the capability
of receiving group addresses. .
If desired, the user software can mask off all the bits of
the address. This type of masking puts the GSC in a
promiscuous mode so that all addresses are received.
CONTROL - The control field is used for initialization
of the system, identifying the sequence of a frame, to
identify if the message is complete, to tell secondary
stations if a response is expected, and acknowledgement
of previously sent frames. The user software is responsible for insertion of the control field as the GSC hardware has no provisions for the management of this
field. The interpretation and formation of the control
field must also be handled by user software. The information following the control field is typically used for
information transfer, error reporting, and various other
functions. These functions are accomplished by the format of the control field. There are three formats available. The types of formats are Informational, Supervisory, or Unnumbered. Figure 3.7 Shows the various format types and how to identify them.
Since the user software is responsible for the implementation of the control field, what follows is a simple explanation on the control field and its functions. For a
complete understanding and proper implementation of
SDLC, the user should refer to the IBM document,
GA27-3093-2, IBM Synchronous Data Link Control
General Information. Within that document, is another
list of IBM documents which go into detail on the
SDLC protocol and its use.
The control field is eight bits wide and the format is
determined by bits 0 and 1. If bit 0 is a zero, then the
frame is an informational frame. If bit 0 is a one and bit
1 a zero, then it is a supervisory frame, and if bit 0 is a
one and bit 1 a one then the frame is an unnumbered
fr~e.
In an informational frame bits 3,2,1 contain the sequence count of the· frame being sent.
Bit 4 is the P IF (PolllFinal) bit. If bit 4 equals 1 and
originates from the primary, then the secondary station
is expected to initiate a transmission. If bit 4 equals 1
and originates from a secondary station, then the frame
is the final frame in a transmission.
Bits 7,6,5 contain the sequence count a station expects
on the next transmission to it. The sequence count can
vary from OOOB to lllB. The count then starts over
again at OOOB after the value IllB is incremented. The
acknowledgement is recognized by the receiving station
when it decodes bits 7,6,5 of an incoming frame. The
station sending the transmission is acknowledging the
frames received up to the count represented in bits 7,6,5
(sequence count-I). With this method, up to seven sequential frames may be transmitted prior to an acknowledgement being received. If eight frames were allowed to pass before an acknowledgement, the sequence
count would roll over and this would negate the purpose of the sequence numbers.
10-28
infel .
83C152 HARDWARE DESCRIPTION
7
6
'5
4
3
2
1
0
~
POSITIONS-r-...;.........,_..;....--,....---.,;~
........---.,;_..--..;;........,_,;;;;;..-.,..._..;............--.,;;--.
RECEPtiON POLLj
SEQUENCE FINAL
SENDING
SEQUENCE
o
270427-15
RECEPTION SEQUENCE - The sequence expected in the SENDING SEQUENCE portion of the control byte
in the next received frame. This also confirms correct reception of up to seven frames prior to the sequence given.
POLL/FINAL - Identifies the frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
SENDING SEQUENCE - Identifies the sequence of the frame being transmitted.
o - If bit 0 = 0 the frame is identified as a informational format type.
INFORMATION FORMAT
~
POSITIONS-
7
6
5
432
0
r--R-E""""C-E-P-T""":IO-N---,-PO-LL-j-r------,'----r-----..,:::',,..---1---,
O
SEQUENCE FINAL MOpE
270427-16
RECEPTION SEQUENCE - Expected sequence of frame for next reception.
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
MODE - Identifies whether receiver is ready (00), not ready (10) or a frame was rejected (01). The rejected frame
is identified by the reception sequence.
0,1 - If bits I,D = 0,1 the frame is identified as a supervisory format type.
SU PERVISORY FORMAT
~
POSITIONS-..--_--.,.
_ _....,-_ _...-_---,r-_--.,._ _........_;.........,....-_---.
7
6
5
432
CO:MMAI~lD/ POLLj COM~AND/
R~SPONSE
FINAL RESPPNSE
0
1 1
270427-17
COMMAND/RESPONSE - Identifies the type of command or response,
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
1,1 - If bits I,D = 1,1 the frame is identified as an unnumbered format type.
NONSEQU ENCED FORMAT
Figure 3.7. SOLC Control Field
10-29
270427-18
83C152 HARDWARE DESCRIPTION
Following the infonnational control field comes the infonnation to be transferred.
When the modeis 10, the sending station is indicating
that its receiver is not ready to accept frames.
In the supervisory format (bits 1,0 = 0,1) bits 3,2 detennine vyhich mode is being used.
'
Mode 11 is an illegal mode in SDLC protocol.
When the mode is 00 it indicates that the receive line of
the station that sent the supervisory frame is enabled
and ready to accept frames.
When the mode is, 01, it indicates that previously a
received frame was rejected. The value in the receive
count identifies which frame(s) need to be retransmitted.
Bits' 7,6,5 represent the value of the sequence the station expects when the next transfer occurs for that station. There is no infonnation following the control field
when the supervisory fonnat is used.
In the unnumbered fonnat (bits 1,0
the primary to secondary stations or requests ofSecondary stations to the primary.
The standard commands are:
BITS 7 6 5 3 2 Command
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
l'
1
1
0
Unnumbered Information (UI)
Set initialization mode (SIM)
Disconnect (DISC)
Response optional (UP)
Function descriptor in
information field (CFGR)
1 Identification in information field. (XID)
0 Test pattern in information field. (TEST)
0
1
0
0
1
The standard responses are:
BITS 7
0
0
0
1
0
1
1
0
1
6
0
0
0
0
1
0
5
0
0
0
0
1
1
0
0
1
1
3
0
0
1
0
0
1
0
0
1
0
= 1,1) bits 7, 6, 5,
3, 2 (notice bit 4 is missing) indicate commands from
2 Command
0 Unnumbered information (UI)
Request for initialization (RIM)
1 Station in disconnected mode (OM)
1 Invalid frame received (FRMR)
0 Unnumbered acknowledgement (UA)
Signal loss of input (BCN)
Function descriptor in information field (CFGR)
0 Station wants to disconnect (RD) ,
1 Identification in information field (XID)
0 Test pattern in information field (TEST)
10-30
intel~
83C152 HARDWARE DESCRIPTION
In an unnumbered frame, information of variable
length may follow the control field if VI is used, or
information of fixed length may follow if FRMR is
used.
As stated earlier, the user software is responsible for the
proper management of the control field. This portion of
the frame is passed to or from the GSC FIFOs as basic
informational type data.
INFO - This is the information field and contains the
data that one device on the link wishes to transmit to
another device. It can be of any length the user wishes,
but must be a multiple of 8 bits. It is possible that some
frames may contain no information field.· The information field is identified to the receiving stations by the
preceding control field and the following CRC. The
GSC determines where the last of the information field
is by passing the bits through the CRC generator.
When the last bit or EOF is received the bits that remain constitute the CRC.
CRC - The Cyclic Redundancy Check (CRC) is an error checking sequence commonly used in serial communications. The C152 offers two types of CRC algo-
rithms, a 16-bit and a 32-bit. The 32-bit algorithm is
normally used in CSMA/CD applications and is described in section 3.2.2. In most SDLC applications a
16-bit CRC is used and the hardware configuration that
supports 16-bit CRC is shown in Figure 3.8. The generating polynomial that the CRC generator uses with the
16-bit CRC is:
G(X) = X16
+
X12
+
X5
+
1
The way the CRC operates is that as a bit is received it
is XOR'd with bit 15 of the current CRC and placed in
temporary storage. The result of XOR'ing bit 15 with
the received bit is then XOR'd with bit 4 and bit 11 as
the CRC is shifted one position to the right. The bit in
temporary storage is shifted into position O.
The required CRC length for SDLC is 16 bits. The
CRC is automatically stripped from the frame and not
passed on to the CPU. The last 16 bits are then run
though the CRC generator to insure that the correct
remainder is left. The remainder that is checked for is
001110100001111B (lDOF Hex). If there is a mismatch, an error is generated. The user software has the
option of enabling this interrupt so the CPU is notified.
270427-19
Figure 3.8. 16·Bit CRC
10-31
II
I
infel~
83C152 HARDWARE DESCRIPTION
EOF - The End Of Frame (EOF) indicates when the
transmission is complete. The EOF is identified by the
end flag. An end flag consists of the bit pattern
01111110. The EOF can also serve as the BOF for the
next frame.
3.3.3 DATA ENCODING
The transmission of data in SDLC mode is done via
NRZI encoding as shown in Figure 3.9. NRZI encoding transmits data by changing the state of the output
whenever a 0 is being transmitted. Whenever a I is
transmitted the state of the output remains the same as
the previous bit and remains valid for the entire bit
time. When SDLC mode is selected it automatically
enables the NRZI encoding on the transmit line and
NRZI decoding on the receive line. The Address and
Info bytes are transmitted LSB first. The CRC is transmitted MSB first.
3.3.4 BIT STUFFING/STRIPPING
In SDLC mode one of the primary rules of the protocol
is that in any normal data transmission, there will never
be an occurrence of more than 5 consecutive Is. The
GSC takes care of this housekeeping chore by automatically inserting a 0 after every occurrence of 5 consecutive Is and the receiver automatically removes a zero
after receiving 5 consecutive Is. All the necessary steps
required for implementing bit stuffing and stripping are
incorporated into the GSC hardware. This makes the
operation transparent to the user. About the only time
this operation becomes apparent to the user, is if the
actual data on the transmission medium is being monitored by a device that is not aware of the automatic
insertion of Os. The bit stuffing/stripping guarantees
that there will be at least one transition every 6 bit
times while the line is active.
3.3.5 SENDING ABORT CHARACTER
An abort character is one of the exceptions to the rule
that disallows more than 5 consecutive Is. The abort
character consists of any occurrence of seven or more
consecutive ones. The simplest way for the C152 to
send an abort character is to clear the TEN bit. This
causes the output to be disabled which, in turn, forces it
to a constant high state. The delay necessary to insure
that the link is high for seven bit times is a task that
needs to be handled by user software. Other methods of
sending an abort character are using the IFS register or
using the Raw Transmit mode. Using IFS still entails
clearing the TEN bit, but TEN can be immediately reenabled. The next message will not begin until the IFS
expires. The IFS begins timing out as soon as DEN
goes high which identifies the end of transmission. This
also requires that IFS contain a value equal to or greater than 8. This method may have the undesirable effect
that DEN goes high and disables the external drivers.
The other alternative is to switch to Raw Transmit
mode. Then, writing OFFH to TFIFO would generate a
high output for 8 bit times. This method would leave
DEN active during the transmission of the abort character.
When the receiver detects seven or more consecutive Is
and data has been loaded into the receive FIFO, the
RCABT flag is set in RSTAT and that frame is ignored. If no data has been loaded into the receive
FIFO, there are no abort flags set and that frame is just
ignored. A retransmitted frame may immediately folIowan abort character, provided the proper flags are
used.
o
o
o
NRZ~
BIT
'
TIME~
270427-20
Figure 3.9. NRZI Encoding
10-32
intele
83C152 HARDWARE DESCRIPTION
3.3.6 LINE IDLE
If 15 or more consecutive Is are detected by the receiv·
er the Line Idle bit (LNI) in TSTAT is set. The seven
Is from the abort character may be included when sensing for a line idle condition. The same methods used for
sending the Abort character can be used for creating
the Idle conditiQn. However, the values would need to
be changed to reflect 15 bit times, instead of seven bit
times.
3.3.7 ACKNOWLEDGEMENT
Acknowledgment in SOLC is an implied acknowledge
and is contained in the control field. Part of the control
frame is the sequence number of the next expected
frame. This sequence number is'-called the Receive
Count. In transmitting the Receive Count, the receiver
is in fact acknowledging all the previous frames prior to
the count that was transmitted. This allows for the
transmission of up to seven frames before an acknowledge is required back to the transmitter. The limitation
of seven frames is necessary because the Receive Count
in the control field is limited to three binary digits. This
means that if an eighth transmission occurred this
would cause the next Receive Count to repeat the first
count that still is waiting for an acknowledge. This
would defeat the purpose of the acknowledgement. The
processing and general maintenance of the sequence
count must be done by the user software. The Hardware Based Acknowledge option that is provide9 in the
C152 is not compatible with standard SOLC protocol.
3.3.8 PRIMARY/SECONDARY STATIONS
All SOLC networks are based upon a primary/secondary station relationship. There can be only one primary
station in a network and all the other stations are considered secondary. All communication is between the
primary and secondary station. Secondary station to
secondary station direct communication is prohibited.
If there is a need for secondary to secondary communication, the user software will have to make allowances
for the master to act as an intermediary. Secondary
stations are allowed use of the serial line only when the
master permits them. This is done by the master polling
the secondary stations to see if they have a need to
access the serial line. This should prevent any collisions
from occurring, provided each secondary station has its
own unique address. This arrangement also partially
determines the types of networks supported. Normal
SOLC networks consist of point-to-point, multi-drop,
or ring configurations and the Cl52 supports all of
these. However, some SOLC processors support an au-.
. tomatic one bit delay at each node that is not supported
by the C152. In a "Loop Mode" configuration, is is
necessary that the transmission be delayed from the reception of the frames from the upstream station before
passing the message to the downstream station. This
delay is necessary so that a station can decode its own
address before the message is passed on. The various
networks are shown in Figure 3.10.
3.3.9 HDLC/SDLC COMPARISON
HOLC (High level Oata Link Control) is a standard
adopted by the International Standards Organization
(ISO). The HOLC standard is defined in the ISO document #ISO 6159 - HOLC unbalanced classes ofprocedures. IBM developed the SOLC protocol as a subset of
HOLC. SOLC conforms to HOLC protocol requirements, but is more restrictive. SOLC contains a more
precise definition on the modes of operation.
Some of the major differences between SOLC and
HOLC are:
SDLC
HDLC
Unbalanced (primary/
secondary)
Modulo 8 (no extensions
allowed, up to 7 outstanding frames before
acknowledge is required)
8-bit addressing only
Byte aligned data
Balanced
(peer to peer)
Modulo 128 (up to 127
outstanding frames
before acknowledge
is required)
Extended addressing
Variable size of data
The C152 does not support HOLC implementation requiring data alignment other than byte alignment. The
user will find that many of the protocol parameters are
programmable in the C152 which allows easy implementation of proprietary or standard HOLC network.
User software needs to implement the control field
functions.
3.3.10 USING A PREAMBLE IN SDLC
When transmitting a preamble in SOLC mode, the user
should be aware that the pattern of 10101010 ... is
output. NRZI encoding is used in SOLC when the internal baud rate generator is the clock source and this
means that a transition will occur every two bit times,
when a 0 is transmitted. This compares with some other SOLC devices, most of which transmit the pattern
OOOOOOOO . . . which will cause a transition every bit
time. Our past experience has shown that the C152 preamble does not cause a problem with most other devices. This is because the preamble is used only to define
the relative bit time boundaries within some variation
allowed by the receiving station, and the C152 preamble fulfills this function. The Cl52 does not have any
problems with receiving a preamble consisting of aliOs .
One note of caution however. If idle fill flags are used
in conjunction with a preamble, the addresses OO(OO)H
and 55(55)H should not be assigned to any C152 as the
preamble following the idle fill flags will be interpreted
as an address.
10-33
•
intel~
83C152 HARDWARE 'DESCRIPTION
3.4 User Defined Protocols
3.5 Using the GSC
The explanation on the implementation of user defined
protocols would go beyond the scope of this manual,
but examining Table 3.1 should give the reader a consolidated list of most of the possibilities. In this manual,
any deviation from the documents that cover the implementation of CSMA/CD or SDLC are considered user
defined protocols, Examples of this would be the use of
SDLC with the 32-bit CRC selected or CSMA/CD
with hardware based acknowledge.
3.5.1 LINE DISCIPLINE
Line discipline is how the management of the transfer
of data over the physical medium is controlled. Two
types of line discipline will be discussed in this section:
full duplex and half duplex.
Point-to-Point Network
270427-21
Multi-Drop Network
270427-22
Ring Network
270427-23
Figure 3.10. SDLC Networks
10-34
intet
83C152 HARDWARE DESCRIPTION
Full duplex is the simultaneous transmission and reception of data. Full duplex uses anywhere from two to
four wires. At least one wire is needed for transmission
and one wire for reception. Usually there will also be a
ground reference on each signal if the distance from
station to station is relatively long. Full-duplex operation in the Cl52 requires that both the receive and the
transmit portion of the GSC are functioning at the
same time. Since both the transmitter and receiver are
operating, two CRC generators are also needed. The
Cl52 handles this problem by having one 32-bit CRC
generator and one 16-bit CRC generator. When supporting full-duplex operation, the 32-bit CRC generator
is modified to work as a 16-bit CRC generator. Whenever the 16-bit CRC is selected, the GSC automatically
enters the full duplex mode. Half duplex with a 16-bit
CRC is discussed in the following paragraph.
expansion plans become a mute issue. However, it"is
strongly suggested that there always be some allowance
for future modifications.
Half duplex is the alternate transmission and reception
of data over a single common wire. Only one or two
wires are needed in half-duplex systems. One wire is
needed for the signal and if the distance to be covered is
long there will also be a wire for the ground reference.
In half-duplex mode, only the receiver or transmitter
can operate at one time. When the receiver or transmitter operates is determined by user software, but typically the receiver will always be enabled uuless the GSC is
transmitting. When using the C152 in half-duplex and
the receiver is connected to the transmitter it is possible
that a station will receive its' own transmission. This
can occur if a broadcast address is sent, the address
mask register(s) are filled with all Is, or the address
being sent matches the sending stations address
through the use of the address masking registers. The
receiver must be disabled by the user while transmitting
if any of these conditions will occur, unless the user
wants a station to receive its own transmission. The
receiver is disabled by clearing GREN (and GAREN if
used). Half-duplex operation in the Cl52 is supported
with either 16-bit or 32-bit CRCs. Whenever a 32-bit
CRC is selected, only half-duplex operation can be supported by the GSC. It is possible to simulate full-duplex
operation with a 32-bit CRC, but this would require
that the CRC be performed with software. Calculating
the CRC with the CPU would greatly reduce the. data
rates that could be used with the GSC. Whenever a 16bit CRC is selected, full-duplex operation is automatically chosen and the GSC must be reconfigured if halfduplex operation is preferred.
4) If using CSMAlCD without deterministic resolution, any increase in network size will have a negative
impact on the average throughput of the network and
lower the efficiency. The user will have to give careful
consideration when deciding how large a system can
ultimately be and still maintain adequate performance.
3.5.2 PLANNING FOR NETWORK CHANGES
AND EXPANSIONS
A complete explanation on how to plan for network
expansion will not be covered in this manual as there
are far too many possibilities that would need to be
discussed. But there are several areas that will have
major impact when allowing for changes in the system.
In cases where there will never be any changes allowed,
Some of the general areas that will impact the overall
scheme on how to incorporate future changes to the
system are:
1) Communication of the change to all the stations or
the primary station.
2) Maximum distance for communication. This will affect the drivers used and the slot time.
3) More stations may be on the line at one time. This
may impact the interframe space or the collision resolution used.
3.5.3 DMA SERVICING OF GSC CHANNELS
There are two sources that can be used to control the
GSC. The first is CPU control and the second is DMA
control.
CPU control is used when user software takes care of
the tasks such as: loading the TFIFO, reading the RFIFO, checking the status flags, and general tracking of
the transmission process. As the number of tasks grow
and higher data transfer rates are used, the overhead
required by the CPU becomes the dominant consumption of time. Eventually, a point is reached where the
CPU is spending 100% of its time responding to the
needs of the GSC. An alternative is to have the DMA
channels control the GSC.
A detailed explanation on the general use of the DMA
channels is covered in Section 4. In this section only
those details required for the use of the DMA channels
with the GSC will be covered.
The DMA channels cali be configured by user software
so that the GSC data transfers are serviced by the
DMA controller. ~ince there are two DMA channels,
one channel can be used to service the receiver, and one
channel can be used to service the transmitter. In using
the DMA channels, the CPU is relieved of much of the
time required to do the basic servicing of the GSC buffers. The types of servicing that the DMA channels can
provide are: loading of the transmit FIFO, removing
data from the receive FIFO, notification of the CPU
when the transmission or reception has ended, and response to certain error conditions. When using the
10-35
intel .
83C152 HARDWARE DESCRIPTION
DMA channels the source or destination of the data
intended for serial transmission can be internal data
memory, external data memory, or any of the SFRs.
The only tasks required after initialization of the DMA
and GSC registers are enabling the proper interrupts
and informing the DMA controller when to start. After
the DMA channels are started all that is required of the
CPU is to respond to error conditions or wait until the
end of transmission.
Initialization of the DMA channels requires setting up
the control, source, and destination address registers.
On the DMA channel servicing the receiver, the control register needs to be loaded as follows: DCONn.2 =
0, this sets the transfer mode so that response is to GSC
interrupts and put the DMA control in alternate cycle
mode; DCONn.3 = 1, this enables the demand mode;
DCONn.4 = 0, this clears the automatic increment
option for the source address; and DCONn.5 = 1, this
defines the source as SFR. The DMA channel servicing
the receiver also needs its source address register to
contain the address of RFIFO (SARHN = XXH,
SARLN = OF4H). On the DMA channel servicing the
transmitter, the control register needs to be loaded as
follows: DCONn.2 = 0; DCONn.3 = 1; DCONn.6 =
0, this clears the automatic increment option for the
destination address; and DCONn.7 = 1, this sets the
destination
SFR. The DMA channel serving the
transmitter also requires that its destination address
register contains the address of TFIFO (DARHN =
XXH, DARLN = 85H). Assuming that DCONO
would be serving the receiver and DCONI the trans. mitter, DCONO would be loaded with XXI01OXOB
and DCONI would be loaded with lOXXlOXOB. The
contents of SARHO and DARHI do not have any impact when using internal SFRs as the source or destination.
as
When using the DMA channels to service the GSC, the
byte count registers will also need to be initialized.
The Done flag for the DMA channel servicing the receiver should be used if fixed packet lengths only are
being transmitted or to insw;e that memory is not overwritten by long received data packets. Overwriting of
data can occur when using a smaller bjlffer than the
packet size. In these cases the servicing of the DMA
and/or GSC would be in response to the DMA Done
flag when the byte count reaches zero.
In some cases the buffer size is not the limiting factor
and the packet lengths will be unknown. In these cases
it would be desirable to eliminate the function of the
Done flag. To effectively disable the Done flag for the
DMA channel servicing the receiver, the byte count
should be set to some number larger than any packet
that will be received, up to 64K. If not using the Done
flag, then GSC servicing would be driven by the receive
Done (RDN) flag and/or interrupt. RDN is set when
the EOF is detected. When using the RDNflag, RFNE
should also be checked to insure that all the data has
been emptied out of the receive FIFO.
The byte count register is used for all transmissions and
this means that all packets going out will have to be of
the same length or the length of the packet to be sent
will have to be known prior to the start of transmission.
When using the DMA channels to service the GSC
transmitter, there is no practical way to disable the
Done flag. This is because the transmit done flag
(TDN) is set when the transmit FIFO is empty and the
last message bit has been transmitted. But, when using
the DMA channel to service the transmitter, loads to
the TFIFO continue to occur until the byte count
reaches o. This makes it impossible to use TDN as a
flag to stop the DMA transfers to TFIFO. It is possible
to examine some other registers or conditions, such as
the current byte count, to determine when to stop the
DMA transfers to TFIFO, but this is not recommended
as a way to service the DMA and GSC when transmitting because frequent reading of the DMA registers will
cause the effective DMA transfer rate to slow down.
When using the DMA channels, initialization of the .
GSC would be exactly the same as normal except that
TSTAT.O = 1 (DMA), this informs the GSC that the
DMA channels are going to be used to service the GSC.
Although only TSTAT is written to, both the receiver
and transmitter use this same DMA bit.
The interrupts EGSTE (IEN1.5), GSC transmit error;
EGSTV (IEN1.3), GSC transmit valid; EGSRE
(IENl.1), GSC receive error; and EGSRV (IENl.O),
GSC receive valid; need to be enabled. The DMA interrupts are normally not used when servicing the GSC
with the DMA channels. To ensure that the DMA interrupts are not responded to is a function of the user
software and should be checked by the software to
make sure they are not enabled. Priority for these interrupts can also be set at this time. Whether to use high
or low priority needs to be decided by the user. When
responding to the GSC interrupts, if a buffer is being
used to store the GSC information, then the DMA registers used for the buffer will probably need updating.
After this initialization, all that needs to be done when
the GSC is actually going to be used is: .load the byte
count, set-up the source addresses for the DMA channel servicing the transmitter, set-up the destination addresses for the DMA channel servicing the receiver,
and start the DMA transfer. The GSC enable bits
should be set first and then the GO bits for the DMA.
This initiates the data transfers.
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intel~
83C152 HARDWARE DESCRIPTION
This simplifies the maintenance of the GSC and can
make the implementation of an external buffer for
packetized information automatic.
Initialization of the system can be broken down into
several steps. First, are the assumptions of each network station.
An external buffer can be used as the source of data for
transmission, or the destination of data from the receiver. In this arrangement, the message size is limited to
the RAM size or 64K, whichever is smaller. By using
an external buffer, the data can be accessed by other
devices which may want access to the serial data. The
amount of time required for the external data moves
will also decrease. Under CPU control, a "MOVX"
command would take 24 oscillator periods to complete.
Under DMA control, external to internal, or internal to
external, data moves take only 12 oscillator periods.
The first assumption is that the type of data encoding
to be used is predetermined for the system and that
each station will adhere to the same basic rules defining
that encoding. The second assumption is that the basic
protocol and line discipline is predetermined and
known. This means that all stations are using CSMA/
CD or SDLC or whatever, and that all stations are
either full or half duplex. The third assumption is that
the baud rate is preset for the whole system. Although •
the baud rate could probably be determined by the microprocessor just by monitoring the link, it will make it
much simpler if the baud rate is known in advance.
3.5.4 BAUD RATE
One of the first things that will be required during system initialization is the assignment of unique addresses
for each station. In a two-station only environment this
is not necessary and can be ignored. However, keep in
mind, that all systems should be constructed for easy
future expansions. Therefore, even in only a two station
system, addresses should be assigned. There are three
basic ways in which addresses can be assigned. The
first, and most common is preassigned addresses that
are loaded into the station by the user. This could be
done with a DIP-switch, through a keyboard. The second method of assigning addresses is to randomly assign an address and then check for its uniqueness
throughout the system, and the third method is to
make an inquiry to the system for the assignment of a
unique address. Once the method of address assignment
is determined, the method should become part of the
specifications for the system to which all additions will
have to adhere. This, then, is the final assumption.
The GSC baud rate is determined by the contents of the
SFR, BAUD, or the external clock. The formula used
to determine the baud rate when using the internal
clock is:
(fosc)/«BAUD+ 1)'8)
For example if a 12 MHz oscillator is used the baud
rate can vary from:
12,000,000/«0+1)'8) = 1.5 MBPS
to:
12,000,000/«255+ 1)'8) = 5.859 KBPS
There are certain requirements that the external clock
will need to meet. These requirements are specified in
the data sheet. For a description of the use of the GSC
with external clock please read Section 3.5.11.
3.5.5 INITIALIZATION
Initialization can be broken down into two major components, 1) initialization of the component so that its
serial port is capable of proper communication; and 2)
initialization of the system or a station so that intelligi.
ble communication can take place.
Most of the initialization of the component has already
been discussed in the previous sections. Those items not
covered are the parameters required for the component
to effectively communicate with other components.
These types of issues are common to both system and
component initialization and will be covered in the following text.
The negotiation process may not be clear for some
readers. The following two procedures are given as a
guideline for dynamic address assignment.
In the first procedure, a station assumes a random address and then checks for its uniqueness throughout the
system. As a station is initialized into the system it
sends out a message containing its assumed address.
The format of the message should be such that any
station decoding the address recognizes it as a request
for initialization. If that address is already used, the
receiving station returns a message, with its own address stating that the address in question is already taken. The initializing station then picks another address.
When the initializing station sends its inquiry for the
address check, a timer is also started. If the timer expires before the inquiry is responded to, then that station assumes the address chosen is okay.
10-37
I
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83C152 HARDWARE DESCRIPTION
In the second procedure, an initializing station asks for
an address assignment from the system. This requires
that some station on the link take care of the task of
maintaining a record of which addresses are used. This
station will be called station-1. When the initializing
station, called station-2, gets on the link, it sends out a
message with a broadcast address. The format of the
message should be such that all other stations on the
link recognize it as a request for address assignment.
Part of the message from station-2 is a random number
generated by the station requesting the address. Station-2 then examines all received messages for this random number. The random number could be the address
- of the received message or could be within the information section of a broadcast frame. All the stations, except station-I, on the link should ignore the initialization request. Station-I, upon receiving the initialization
request, assigns an address and returns it to station-2.
Station-I will be required to format the message in such
a manner so that all stations on the link recognize it as
a response to initialization. This means that all stations
except station-2 ignore the return message.
3_5.6 TEST MODES
There are two test modes associated with the GSC that
are made available to the user. The test modes are
named Raw Receive and Raw Transmit. The test
modes are selected by the proper setting of the two
mode bits in GMOD (MO = GMOD.5, Ml =
GMOD.6). If Ml,MO = 0,1 then Raw Transmit is selected. If MI,MO = 1,0 then Raw Receive is enabled.
The 32-bit CRC cannot be used in any of the test
modes, or else CRC errors will occur.
In .Raw Receive, the transmitter should be externally connected to the receiver. To do this a port pin should
be used to enable an external device to connect the two
pins together. In Raw Receive mode the receiver acts as
normal except that all bytes following the BOF are
loaded into the receive FIFO, including the CRC. Also
address recognition is not active but needs to be performed in software. IfSDLC is selected as the protocol,
zero-bit deletion is still enabled. The transmitter still
operates as normal and in this mode most of the transmitter functions and an external transceiver can be tested. This is also the only way that the CRC can be read
by the CPU, but the CRC error bit will not be set.
3.5.7 EXTERNAL DRIVER INTERFACE
A signal is provided from the C152 to enable transmitter drivers for the serial link. This is provided for systems that require more than what the GSC ports are
capable of delivering. The voltage and currents that the
GSC is capable of providing are the same levels as those
for normal port operation. The signal used to enable the
external drivers is DEN. No similar signal is needed for
the receiver.
DEN is active one bit time before transmission begins.
In CSMA/CD DEN remains active for two bit times
after the CRC is transmitted. In SDLC DEN remains
active until the last bit of the EOF is transmitted.
3.5.8 JITTER (RECEIVE)
In Raw Transmit, the transmit output is internally connected to the Receiver input. This is intended to be
used as a local loop-back test mode, so that all data
written to the transmitter will be returned by the receiver. Raw Transmit can also be used to transmit user
data. If Raw Transmit is used in this way the data is
emitted with no preamble, flag, address, CRC, and no
bit insertion. The data is still encoded with whatever
format is selected, Manchester with CSMA/CD, NRZI
with SDLC or as NRZ if external clocks are used. The
receiver still operates as normal and in this mode most
of the receive functions can be tested.
Data jitter is the difference between the actual transmitted waveform and the exact calculated value(s). In
NRZI, data jitter would be how-much the actual waveform exceeds or falls short of one calculated bit time. A
bit time equals I/baud rate. If using Manchester encoding, there can be two transitions during one bit time as
shown in Figure 3.11. This causes a second parameter
to be considered when trying to figure out the complete
data jitter amount. This other parameter is the half-bit
jitter. The half-bit jitter is comprised of the difference in
time that the half-bit transition actually occurs and the
calculated value. Jitter is important because if the transition occurs too soon it is considered noise, and if the
transition occurs too late, then either the bit is missed
or a collision is assumed.
10-38
83C152 HARDWARE DESCRIPTION
LOGICAL
VALUE
o
o
o
MANCHESTER
ENCODING
I.
"1" BIT TIME
"1" BIT TIME
I.
I
I
I
,
,
,
.. -
--.
I
I
I
.- ..,
,
,
,
,
I
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...
,
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... ...
_..
,
I
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....
,
"1" BIT TIME
i------'"'T
--.
"I
RECEIVED ,
DATA'
•
, •
t
(B X BAUD
RECEIV
SAMPLING'
RATE
RECEIVED,
DATA
• I
,
,
,
,
"0" BIT TIME
I
I
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'
, I
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• _____
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..
y-___..-_ _- ;
'
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: : :
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~ ------~-----~
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270427-24
Figure 3.11. Jitter
3.5.9 Transmit Waveforms
The GSC is capable of three types of data encoding,
Manchester, NRZI, and NRZ. Figure 3.12 shows examples of all three types of data encoding.
3.5.10 Receiver Clock Recovery
The receiver is always monitored at eight times the
baud rate frequency, except when an external clock is
used. When using an external clock the receiver is loaded during the clock cycle.
In CSMA/CD mode the receiver synchronizes to the
transmitted data during the preamble. If a pulse is detected as being too short it is assumed to be noise or a
collision. If a pulse is too long it is assumed to be a
collision or an idle condition.
In SDLC the synchronization takes place during the
BOF flag. In addition, pulses less than four sample periods are ignored, and assumed to be noise. This sets a
lower limit on the pulse size of received zeros.
In CSMA/CD the preamble consists of alternating Is
and Os. Consequently, the preamble looks like the
waveform in Figure 3.13A and 3.13B.
3.5.11 External Clocking
To select external clocking, the user is given three
choices. External clocking can be used with the transmitter, with the receiver, or with both. To select external clocking for the transmitter, XTCLK (GMOD.7)
has to be set to a 1. To select external clocking for the
receiver, XRCLK (PCON.3) has to be set to a 1. Setting both bits to 1 forces external clocking for the receiver and transmitter. The minimum frequency the
GSC can be externally clocked at is 0 Hz (D.C.).
The external transmit clock is applied to pin 4 (TXC),
P1.3. The external receive clock is applied to pin 5
(RXC), PI.4. To enable the external clock function on
the port pin, that pin has to be set to a I in the appropriate SFR, PI.
10-39
intel~
83C152 HARDWARE DESCRIPTION
,
,
BIT
,
--TIME-',
o
o
o
L
NRZ
NRZ~
270427-25
Figure 3.12. Transmit Waveforms
Whenever the external clock option is used, the format
of the transmitted and received data is restricted to
NRZ encoding and the protocol is restricted to SDLC.
With external clock, the bit stuffing/stripping is still
active with SDLC protocol.
(AMSKO, AMSK1) in the C152. These function with
the GSC receiver only. The transmitted address is treated like any other data. The address is transmitted under
software control by placing the address byte(s) at the
proper location (usually first) in the sequence of bytes
to be output in the outgoing packet.
3.5.12 Determining Receiver Errors
The C152 can have up to four different 8-bit addresses
or two different 16-bit addresses assigned to each station. When using 16-bit addressing, ADRO:ADRI form
one address and ADR2:ADR3 form the second address. If the receiver is enabled, it looks for a matching
address after every BOF flag is detected. As the data is
received, if the 8th (or 16th) bit does not match· the
address recognition circuitry, the· rest of the frame is
ignored and the search continues for another flag: If the
address does match the address recognition circuitry,
the address and all subsequent data is passed into the
receive FIFO until the EOF flag or an error occurs.
The address .is not stripped and is also passed to
RFIFO.
It is possible that several receiver error bits will be set
in response to a single cause. The multiple errors that
can occur are:
AE and CRCE may both be set when an alignment
error occurs due to a bad CRC caused by the mis.
aligned frame.
RCABT, AE, and CRCE may be set when an abort
occurs.
OVR, AE, and CRCE may be set when a overrun occurs.
In order to determine the correct cause of the error a
specific order should be followed when examining the
error ~its. This order is:
I)OVR
2) RCBAT
3) AE
4) CRCE
The address masking registers, AMSKO and AMSK1,
work in conjunction with ADRO and ADRI respectively to identify "don't care" bits. A 1 in any position in
the AMSKn register makes the respective bit in the
ADRn register irrelevant. These combinations can then
be used for form group addresses. If the masking registers are filled with all Is, the CI52 will receive all packets, which is called the promiscuous mode. If 16-bit
addressing is used, AMSKO:AMSKI form one 16-bit
address mask.
3.5.13 Addressing
There are four 8-bit address registers (ADRO, ADR1,
ADR2, ADR3) and two 8-bit address mask registers
10-40
int:et
83C152 HARDWARE DESCRIPTION
CSMAICO Clock Recovery
o
1
1
o
0
, 0:
000
IDEAL WAVEFORM
1
ax
t
I
I
I
I
L
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
I
I
I
I
I
SAMPLING RATE IIII1111 IIIII IIIIIIIII1111111 II111111 I111111111111111111111111\111111111111111111111111111 1111111111111111111111111111111111111111111111111111111
ACTUAL WAVEFORM
RECOVERED BIT
STREAM CLOCK
270427-26
Figure 3.13A. Clock Recovery
SOLC Clock Recovery
o
o
000
IDEAL WAVEFORM
1
ax
I
I
I
I
I
L
I
I
I
I
1
I
I
I
I
I
I
I
L
I
I
I
L
I
I
I
I
I
I
I
SAMPLING RATE 111111 II 111111111111111111111111111111111111111111111111111111111111111111111111 I11111 III IIII III I111111 IIII111111 III III IIII IIII I1111111 III III
ACTUAL WAVEFORM
RECOVERED BIT
STREAM CLOCK
270427-27
Figure 3.138. Clock Recovery
10-41
83C152 HARDWARE DESCRIPTION
3.6 GSC Operation
3.6.1 Determining Line Discipline
In normal operation the OSC uses full or half duplex
operation. When using a 32-bit CRC (OMOD.3 = I),
operation can only be half duplex. If using a 16-bit
. CRC (OMOD.3 = 0), full duplex is selected by default. When using a 16-bit CRC the receiver can be
turned off while transmitting (RSTAT. I = 0), and the
transmitter. can be turned off during reception
(TSTAT.I = 0). This simulates half-duplex operation
when using a 16-bit CRC.
Normally, HDLC uses a 16-bit CRC, so half duplex is
determined by turning off the receiver or transmitter.
This is so that the receiver will not detect its own address as transmission takes place. This also needs to be
done when using CSMA/CD with a 16-bit CRC for the
same reason.
3.6.2 CPU/DMA CONTROL OF THE GSC
The data for transmission or reception can be handled
by either the CPU (TSTAT.O = 0) or DMA controller
(TSTAT.O = I). This allows the user two sets of flags
. to control the FIFO. Associated with these flags are
interrupts, which may be enabled by the user software.
Either one or both sets of flags may be used at the same
time.
In CPU control mode the flags (RFNE,TFNF) are generated by the condition of the receive or transmit FIFO's. After loading a byte into the transmit FIFO,
there is a one machine cycle latency until the TFNF
flag is updated. Because of this latency, the status of
TFNF should not be checked immediately following
the instruction to load the transmit FIFO. If using the
interrupts to service the transmit FIFO,the one machine cycle of latency must be considered if the TFNF
flag is checked prior to leaving the subroutine.
When using the CPU for control, transmission normally is initiated by setting the TEN bit (TSTAT.I) and
then writing to TFIFO. TEN must be set before loading the transmit FIFO, as setting TEN clears the transmit FIFO. TCDCNT should also be checked by user
software and cleared if a collision occurred on a prior
transmission.
To enable the receiver, OREN (RSTAT.I) is set. After
OREN is set, the OSC begins to look for a valid BOF.
After detecting a valid BOF the OSC attempts to
match the received address byte(s) against the address
match registers. When a match occurs the frame is
loaded into the OSC. Due to the CRC strip hardware,
there is a 40 or 24 bit time delay following the BOF
until the first data byte is loaded into RFIFO if the 32
or 16 bit CRC is chosen. If the end offrame is detected
before data is loaded into the receive FIFO, the receiver
ignores that frame.
If the receiver detects a collision during reception in
CSMA/CD mode and if any bytes have been loaded
into the receive FIFO, the RCABT flag is set. The OSC
hardware then halts reception and resets OREN. The
user software needs to filter any collision fragment data
which may have been received. If the collision occurred
prior to the data being loaded into RFIFO the CPU is
not notified and the receiver is left enabled. At the end
of a reception the RDN bit is set and OREN is cleared.
In HABEN mode this causes an acknowledgement to
be transmitted if the frame did not have a broadcast or
multi-cast address. The user software can enable the
interrupt for RDN to determine when a frame is completed.
•
In DMA mode the interrupts are generated by the internal "transmit/receive done" (TDN,RDN)conditions. When the CPU responds to TDN or RDN,
checks are performed to see if the transmit underrun
error has occurred. The underrun condition is only
checked when using the DMA channels.
Upon power up the CPU mode is initialized. General
DMA control is covered in Section 4.0. DMA control
of the OSC is covered in Section,3.5.4. If DMA is to be
used for serving the OSC, it must be configured into the
serial channel demand mode and the DMA bit in
TSTAT has to be set.
3.6.3 COLLISIONS AND BACKOFF
The actions that are taken by the OSC if a collision
occurs while transmitting depend on where the collision occurs. If a collision' occurs in CSMAlCD mode
following the preamble and BOF flag, the TCDT flag is
set and the transmit hardware completes a jam. When
this type of collision occurs, there will be no. automatic
retry at transmission. After the jam, control IS returned
to the CPU and user software must then initiate whatever actions are necessary for a proper recovery. The
possibility that data might have been loaded into or
from the OSC deserves special consideration. If these
'fragments of a message have been passed on to other
devices user software may have to perform some extensive e~or handling or notification. Before starting a
new message, the transmit and receive FIFOs will need
to be cleared. If DMA servicing is being used the pointers must also be reinitialized. It should be noted that a
collision should never occur after the BOF flag in a well
designed system, since the system slot time will likely
be less than the preamble length. The occurrence of
such a situation is normally due to a station on the link
that is not adhering to proper CSMA/CD protocol or
is not using the same timings as the rest of the network.
A collision occurring during the preamble or BOF flag
is the normal type of collision that is expected. When
this type of collision occurs the OSC automatically
handles the retransmission attempts for as many as
eight tries. If on the eighth attempt a collision occurs,
10-42
intel..
83C152 HARDWARE DESCRIPTION
the transmitter is disabled, although the jam and backoff are performed. If enabled, the CPU is then interrupted. The user software should then determine what
action to take. The possibilities range from just reporting the error and aborting transmission to reinitializing
the serial channel registers and attempt retransmission.
If less than eight attempts are desired TCDCNT can be
loaded with some value which will reduce the number
of collisions possible before TCDCNT overflows. The
value loaded should consist of all !s as the least significant bits, e.g. 7, OFH, 3FH. A solid block of Is is suggested because TCDCNT is used as a mask when generating the random slot number assignment. The
TCDCNT register operates by shifting the contents one
bit position to the left as each collision is detected. As
each shift occurs a I is loaded into the LSB. When
TCDCNT overflows, GSC operation stops and the
CPU is notified by the setting of the TCDT bit which
can flag an interrupt.
The amount of time that the GSC has before it must be
ready to retransmit after a collision is determined by
the mode which is selected. The mode is determined
MO (GMOD.5) and MI (GMOD.6). If MO and MI
equal 0,0 (normal backotl) then the minimum period
before retransmission will be either the interframe
space or the backoff period, whichever is longer. If MO
and MI equal!,! (alternate backotl) then the minimum
period before retransmission will be the interframe
space plus the backoff period. Both of these are shown
in Figure 3.4. Alternate backoff must be enabled if using deterministic resolution. If the GSC is not ready to
retransmit by the time its assigned slot becomes· available, the slot time is lost and the station must wait until
the collision resolution time period has passed.
Instead of waiting for the collision resolution to pass,
the transmission could be aborted. The decision to
abort is usually dependent on the number of stations on
the link and how many collisions have already occurred. The number of collisions can be obtained by
examining the register, TCDCNT. The abort is normally implemented by clearing TEN. The new transmission begins by setting TEN and loading TFIFO. The
minimum amount of time available to initiate a retransmission would be one interframe space period after the
line is sensed as being idle.
As the number of stations approach 256 the probability
of a successful transmission decreases rapidly. If there
are more than 256 stations involved in the collision
there would be no resolution since at least two of the
stations will always have the same backoff interval selected.
All the stations monitor the link as long as that station
is active, even if not attempting to transmit. This is to
ensure that each station always defers the minimum
amount of time before attempting a transmission and so
that addresses are recognized. However, the collision
detect circuitry operates slightly differently.
In normal back-off mode, a transmitting station always •
monitors the link while transmitting. If a collision is
detected one or more of the transmitting stations apply
the jam signal and all transmitting stations enter the
back-off algorithm. The receiving stations also constantly monitor for a collision but do not take part in
the resolution phase. This allows a station to try to
transmit in the middle of a resolution period. This in
tum mayor may not cause another collision. If the new
station trying to transmit on the link does so during an
unused slot time then there will probably not be a collision. If trying to transmit during a used slot time, then
there will probably be a collision. The actions the receiver does take when detecting a collision is to just
stop receiving data if data has not been loaded into
RFIFO or to stop reception, clear receiver. enable
(REN) and set the receiver abort flag (RCABT RSTAT.6).
If deterministic resolution is used, the transmitting stations go through pretty much the same process as in
normal back-off, except that the slots 'are predetermined. All the receivers go through the back-off algorithm and may only transmit during their assigned slot.
3.6.4 SUCCESSFUL ENDING OF
TRANSMISSIONS AND RECEPTIONS
In both CSMA/CD and SDLC modes, the TDN bit is
set and TEN cleared at the end of a successful transmission. The end of the transmission occurs when the
TFIFO is empty and the last byte has been transmitted.
In CSMA/CD the user should clear the TCDCNT register after successful transmission.
At the end of a successful reception, the RDN bit is set
and GREN is cleared. The end of reception occurs
when the EOF flag is detected by the GSC hardware.
10-43
I
intet
83C152 HARDWARE DESCRIPTION
3.7 Register Descriptions
ADRO,I,2,3 (9SH, OASH, OBSH, OCSH) - Address
Match Registers 0,1,2,3 - Contains the address match
values which determines which data will be accepted as valid. In 8 bit addressing mode, a match with any of the
four registers will trigger acceptance. In 16 bit addressing mode a match with ADRI:ADRO or ADR3:ADR2
will be accepted. Addressing mode is determined in
GMOD(AL).
AMSKO, I (ODSH, OESH) - Address Match Mask 0, I Identifies which bits in ADRO, I are "don't care" bits.
Writing a one to a bit in AMSKO,I masks out that
corresponding bit in ADDRO,I.
BAUD (94H) - GSC Baud Rate Generator - Contains
the value of the programmable baud rate. The data rate
will equal (frequency of the oscillator)/«BAUD + I)
X (8». Writing to BAUD actually stores the value in a
reload register. The reload register contents are copied
into the BAUD register when the Baud register decrements to OOH. Reading BAUD yields the current timer
value. A read during GSC operation will give a value
that may not be current because the timer could decrement between the time it is -read by the CPU and by the
time the value is loaded into its destination.
BKOFF (OC4H) - Backoff Timer - The backoff timer is
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the
CSMA/CD collision_ resolution algorithm. The user
software may read the timer but the value may be invalid as the timer is clocked asynchronously to the CPU.
Writing to OC4H will have no effect.
I
7
XTCLK
I
6
M1
GMOD(84H)
543
210
PL 1
I PLO I PR I
Figure 3.14. GMOD
The length includes the two bit Begin Of Frame (BOP)
flag in CSMAlCD but does not include the SDLC flag.
In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
in CSMA/CD mode. The user software is responsible
for setting or clearing these bits.
GMOD.3 (CT) - CRC Type - If set, 32 bit AUTODIN11-32 is used. If cleared, 16 bit CRC-CCITT is used.
The user software is responsible for setting or clearing
this flag.
GMOD.4 (AL) - Address Length _- If set, 16 bit addressing is used. If cleared, 8 bit addressing is used. In 8
bit mode a match with any of the 4 address registers
will be accepted (ADRO, ADRI,ADR2, ADR3).
"Don't Care" bits may be masked in ADRO and ADRI
with AMSKO and AMSKI. In 16 bit mode, addresses
are matched against "ADRI:ADRO" or "ADR3:
ADR2". Again, "Don't Care" bits in ADRI:ADRO
can be masked in AMSKI:AMSKO. A received address
of all ones will always be recognized in any mode. The
user software is responsible for setting or clearing this
flag.
GMOD.S,6 (MO,MI) - Mode Select - Two test modes,
an optional "alternate backoir' mode, or normal backoff can be enabled with these two bits. The user software is responsible for setting or clearing the mode bits.
MI
o
o
I
I
MO
0
I
0
I
Mode
Normal
,
Raw Transmit
Raw Receive
Alternate Backoff
In raw receive mode, the receiver operates as normal
except that all the bytes following the BOF are loaded
into the receive FIFO, including the CRC. The transmitter operates as normal.
GMOD.O (PR) - Protocol - If set, SDLC protocols with
NRZI encoding and SDLCflags are used. If cleared,
CSMAlCD link access with Manchester encoding is
used. The user software is responsible for setting or
clearing this flag.
In raw transmit mode the transmit output is internally
connected to the receiver input. The internal connection is not at the actual port pin, but inside the port
latch. All data transmitted is done without a preamble,
flag or zero bit insertion, and without appending a
CRC. The receiver operates as normal. Zero bit deletion is performed.
GMOD.I,2 (PLO,I) - Preamble length
PLI PLO LENGTH (BITS)
o 0
0
o
I
8
I
0
-32
I
I
64
In alternate backoff mode the standard backoff process
is modified so the the backoff is delayed until the end of
the IFS. This should help to prevent collisions constantly happening because the IFS time is usually larger
than the slot time.
-10-44
int:eL
83C152 HARDWARE DESCRIPTION
GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to Pl.3
(T X C). The user software is responsible for setting or
clearing this flag. External receive clock is enabled by
setting PCON.3.
IFS (OA4H) - Interframe Spacing - Determines the
number of bit times separating transmitted frames in
CSMA/CD and SDLC. A bit time is equal to l/baud
rate. Only even interframe space periods can be used.
The number written into this register is divided by two
and loaded in the most significant seven bits. Complete
interframe space is obtained by counting this seven bit
number down to zero twice. A user software read of
this register will give a value where the seven most significant bits gives the current count value and the least
significant bit shows a one for the first count-down and
a zero for the second count. The value read may not be
valid as the timer is clocked in periods not necessarily
associated with the CPU read of IFS. Loading this register with zero results in 256 bit times.
PCON (087H)
76543210
PCON contains bits for power control, LSC control,
DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCON.4.
PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
GFIEN to a 1 caused idle flags to be generated between
transmitted frames in SDLC mode. SDLC idle flags
consist of 01111110 flags creating the sequence
01111110011111110 ...... 011111110. A possible side
effect of enabling GFIEN is that the maximum possible
latency from writing to TFIFO until the first bit is
transmitted increased from approximately 2 bit-times
to around 8 bit-times. GFIEN has no effect with
CSMA/CD.
PCON.3 (XRCLK) - GSC External Receive Clock Enable - Writing a 1 to XRCLK enables an external clock
to be applied to pin 5 (Port 1.4). The external dock is
used to determine when bits are loaded into the receiver.
MYSLOT.O, I, 2, 3, 4, 5 - Slot Address - The six address bits choose I of 64 slot addresses. Address 63 has
the highest priority and address I has the lowest. A
value of zero will prevent a station from transmitting
during the collision resolution period by waiting until
all the possible slot times have elapsed. The user software normally initializes this address in the operating
software.
PCON.4 (GAREN) - GSC Auxiliary Receiver Enable
Bit - This bit needs to be set to a 1 to enable the reception of back-to-back SDLC frames. A back-to-back
SDLC frame is when the EOF and BOF is shared between two sequential frames intended for the same station on the link. If GAREN contains a 0 then the receiver will be disabled upon reception of the EOF and
by the time user software re-enables the receiver the
first bit(s) may have already passed, in the case of backto-back frames. Setting GAREN to a I, prevents the
receiver from being disabled by the EOF but GREN
will be cleared and can be checked by user software to
determine that an EOF has been received. GAREN has
no effect if the GSC is in CSMA/CD mode.
MYSLOT.6 (DCR) - Deterministic Collision Resolution Algorithm - When set, the alternate collision resolution algorithm is selected. Retriggering of the IFS on
reappearance of the carrier is also disabled. When using
this feature Alternate Backoff Mode must be selected
and several other registers must be initialized. User
software must initialize TCDCNT with the maximum
number of slots that are most appropriate for a particular application. The PRBS register must be set to all
ones. This disables the PRBS by freezing it's contents at
OFFH. The backoff timer is used to count down the
number of slots based on the slot timer value setting the
period of one slot. The user software is responsible for
setting or clearing this flag.
PRBS (OE4H) - Pseudo-Random Binary Sequence
This register contains a pseudo-random number to be
used in the CSMA/CD backoff algorithm. The number
is generated by using a feedback shift register clocked
by the CPU phase clocks. Writing all ones to the PRBS
will freeze the value at all ones. Writing any other value
to it will restart the PRBS generator. The PRBS is initialized to all zero's during RESET. A read of location
OE4H will not necessarily give the seed used in the
backoff algorithm because the PRBS counters are
clocked by internal CPU phase clocks. This means the
contents of the PRBS may have been altered between
the time when the seed was generated and before a
READ has been internally executed.
Figure 3.15. MYSLOT
MYSLOT.7 (DCJ) - D.C. Jam - When set selects D.C.
type jam, when clear, selects A.C. type jam. The user
software is responsible for setting or clearing this flag.
10-45
83C152 HARDWARE DESCRIPTION
RFIFO (OF4H) - Receive FIFO - RFIFO is a 3 byte
buffer that is loaded each time the GSC receiver has a
byte of data. Associated with RFIFO is a pointer that is
automatically updated with each read of the FIFO. A
read of RFIFO fetches the oldest data in the FIFO.
RSTAT (OE8H) - Receive Status Register
76543210
IORIRCABTIAElcRCEIRDNIRFNEIGRENIHABENI
Figure 3.16. RSTAT
RSTAT.O (HABEN) - Hardware Based Acknowledge
Enable - If set, enables the hardware based acknowledge feature. The user software is responsible for setting
or clearing this flag.
RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. The user
must clear RFIFO with software before enabling the
receiver. RFIFO is cleared by reading the contents of
RFIFO until RFNE = O. After each read ofRFIFO, it
takes one machine cycle for the status of RFNE to be
updated. Setting GREN also clears RDN, CRCE, AE,
and RCABT. GREN is cleared by hardware at the end
of a reception or if any receive errors are detected. The
user software is responsible for setting this flag and the
GSC or user software can clear it. The status of GREN
has no effect on whether the receiver detects a collision
in CSMA/CD mode as the receiver input circuitry always monitors the receive pin.
RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive
data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO pointers. Setting GREN to a one will clear the receive FIFO.
The status of this flag is controlled by the GSC. It is
cleared if user empties receive FIFO.
RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred. The status of this flag is controlled by
the GSC.
RSTATA (CRCE) - CRC Error - If set, indicates that a
properly aligned frame was received with a mismatched
CRC. The status of this flag is controlled by the GSC.
RSTAT.6 (RCABT) - Receiver CollisionlAbort Detect
- If set, indicates that a collision was detected after data
had been loaded into the receive FIFO in CSMA/CD
mode. In SDLC rnode, RCABT indicates that 7 consecutive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO. AE may
also be set. The setting of this flag is controlled by the
GSC.
RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
written into it. AE and/or CRCE may also be set. The
setting of this flag is controlled by the GSC and it is
cleared by user software.
SLOTTM (OBH) - Slot Time - Determines the length of
the slot time used in CSMA/CD. A slot time equals
(SLOTTM) X (11 baud rate). A read of SLOTTM will
give the value of the slot time timer but the value may
be invalid as the timer is clocked asynchronously to the
CPU. Loading SLOTTM with 0 results in 256 bit
times. .
TCDCNT (OD4H) - Transmit Collision Detect Count Contains the number of collisions that have occurred if
probabilistic CSMA/CD is used. The user software
must clear this register before transmitting a new frame
so that the GSC backoff hardware can accurately distinguish a new frame from a retransmit attempt.
In deterministic backoff mode, TCDCNT is used to
hold the maximum number of slots.
TFIFO (85H) - GSC Transmit FIFO - TFIFO is a 3
byte buffer with an associated pointer that is automatically updated for each write by user software. Writing a
byte to TFIFO loads the data into the next available
location in the transmit FIFO. Setting TEN clears the
transmit FIFO so the transmit FIFO should not be
written to prior to setting TEN. If TEN is already set
transmission begins as soon as data is written to TFIFO.
TSTAT (OD8) - Transmit Status Register
76543210
LNI I NOACK I UR I TCDT I TDN I TFNF I TEN I DMA I
Figure 3.17. TSTAT
TSTAT.O (DMA) - DMA Select - If set, indicates that
DMA channels are used to service the GSC FIFO's and
GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the
GSC is operating in its normal mode and interrupts
occur on TFNF and RFNE. For more information on
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3). The user software
is responsible for setting or clearing this flag.
RSTAT.5 (AE) - Alignment Error - In CSMA/CD
mode, AE is set if the receiver shift register (an internal
serial·to-parallel converter) is not full and the eRC is
bad when an EOF is detected. In CSMA/CD the EOF
is a line idle condition (see LNI) for two bit times. If
the CRC is correct while in CSMA/CD mode, AE is
not set and any mis-alignment is assumed to be caused
by dribble bits as the line went idle. In SDLC mode,
AE is set if a non-byte-aligned flag is received. CRCE
may also be set. The setting of this flag is controlled by
the GSc.
10-46
inteL
83C152 HARDWARE DESCRIPTION
TSTAT.l (TEN) - Transmit Enable - When set causes
TDN, UR, TCDT, and NOACK flag to be reset and
the TFIFO cleared. The transmitter will clear TEN after a successful transmission, a collision during the
data, CRC, or end flag. The user software is responsible
for setting but the GSC or user software may clear this
flag. If cleared during a transmission the GSC transmit
pin goes to a steady state high level. This is the method
used to send an abort character in SDLC. Also DEN is
forced to a high level. The end of transmission occurs
whenever the TFIFO is emptied.
TSTAT.2 (TFNF) - Transmit FIFO not full - When
set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte buffer that loads the transmit shift register with data. The
status of this flag is controlled by the GSC.
TSTAT.3 (TDN) - Transmit Done - When set, indicates the successful completion of a frame transmission.
If HABEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the
acknowledge can be checked. If an acknowledge is expected and not received, TDN is not set. An acknowledge is not expected following a broadcast or multi-cast
packet. The status of this flag is controlled by the GSC.
TSTAT.4 (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or
if there are more than eight collisions. The status of this
flag is controlled by the GSC.
TSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter halts
without sending the CRC or the end flag. The status of
this flag is controlled by the GSC.
TSTAT.6 (NOACK) - No Acknowledge - If set, indicates that no acknowledge was received for the previous
frame. Will be set only if HABEN is set and no acknowledge is received prior to the end of the IFS.
NOACK is not set following a broadcast or a multicast packet. The status of this flag is controlled by the
GSC.
TST AT. 7 (LNI) - Line Idle - If set, indicates the receive line is idle. In SDLC protocol it is set if 15 consecutive ones are received. In CSMA/CD protocol, line
idle is set if GR X D remains high for approximately 1.6
bit times. LNI is cleared after a transition on GR X D.
The status of this flag is controlled by the GSC.
3.S Serial Backplane vs. Network
Environment
The Cl52 GSC port is intended to fulfill the needs of
both serial backplane environment and the serial communication network environment. The serial backplane
is where typically, only processor to processor communications take place within a self contained box. The
communication usually only encompasses those items
which are necessary to accomplish the dedicated task
for the box. In these types of applications there may not
be a need for line drivers as the distance between the
transmitter and receiver is relatively short. The n e t - I I
work environment; however, usually requires transmission of data over large distances and requires drivers
and/or repeaters to ensure the data is received on both
ends.
I
4.0 DMA Operation
The Cl52 contains DMA (Direct Memory Accessing)
logic to perform high speed data transfers between any
two of
Internal Data RAM
Internal SFRs
External Data RAM
If external RAM is involved, the Port 2 and Port 0 ~
are used as the address/data bus, and RD and WR
signals are generated as required.
Hardware is also implemented to generate a Hold Request signal and await a Hold Acknowledge response
before commencing a DMA that involves external
RAM.
Alternatively, the Hold/Hold Acknowledge hardware
can be programmed to accept a Hold Request signal
from an external device and generate a Hold Acknowledge signal in response, to indicate to the requesting
device that the Cl52 will not commence a DMA to or
from external RAM while the Hold Request is active.
4.1 DMA with the SOC152
The Cl52 contains two identical general purpose 8-bit
DMA channels with 16-bit addressability: DMAO and
DMAL DMA transfers can be executed by either channel independent of the other, but only by one channel at
a time. During the time that a DMA transfer is being
executed, program execution is suspended. A DMA
transfer takes one machine cycle (12 oscillator
10-47
83C152 HARDWARE DESCRIPTION
Dt.lA CHANNEL 0
DARHO
I I
DARlO
Dt.lA CHANNEL 1
I,
DARHl
DESTINATION ADDRESS
\
1
SARHO
I
I·
SARLO
I,
\
1 SARHl I 1 SARL1 I,
SOURCE ADDRESS
\
SOURCE ADDRESS
1 BCRHO I 1 BCRlO I,
\
I
BCRHl
DCONO
I 1 BCRL1 I
\
BYTE COUNT
I
I 1 DARL1 I,
DESTINATION ADDRESS
BYTE COUNT
I
1
Dt.lAO CONTROL
DCONl
I
Dt.lA 1 CONTROL
PCON
'--'
~ Two new bit. In
PCON control
Hold/Hold Acknowledge logic
270427-28
Figure 4.1. DMA Registers
Two other bits in DCONn specify the physical source
of the data to be transferred. These are· SAS (Source
Address Space) and ISA (Increment Source Address).
If SAS = 0, the source is in data memory external to
the C152. IfSAS = I, the source is internal. IfSAS =
1 and ISA = 0, the internal source is an SFR. If SAS
= 1 and ISA = I, the internal source is in the 256-byte
data RAM.
periods) per byte transferred, except when the destination and source are both in External Data RAM. In
that case the transfer takes two machine cycles per
byte. The term DMA Cycle will be used to mean the
transfer of a single data byte, whether it takes I or 2
machine cycles.
Associated with each channel are seven SFRs, shown in
Figure 4.1. SARLn and SARHn holds the low and high
bytes of the source address. Taken together they form a
16-bit Source Address Register. DARLn and DARHn
hold the low and high bytes of the destination address,
and together form the Destination Address Register.
BCRLn and BCRHn hold the low and high bytes of the
number of bytes to be transferred, and together form
the Byte Count Register. DCONn contains control and
flag bits.
In any case, ifiSA = I, the source address is automatically incremented after each byte transfer. If ISA = 0,
it is not.
The functions of these four control bits are summarized
below:
Two bits in DCONn are used to· specify the physical
destination of the data transfer. These bits are DAS
(Destination Address Space) and IDA (Increment Destination Address). If DAS = 0, the destination is in
data memory external to the C152. If DAS = I, the
destination is internal to the C152. If DAS = I and
IDA = 0, the internal destination is a Special Function
Register (SFR). If DAS = I and IDA = I, the internal destination is in the 256-byte data RAM.
In any case, if IDA = 1, the destination address is
automatically incremented after each byte transfer. If
IDA = 0, it is not.
10-48
DAS
IDA
Destination
Auto-Increment
0
0
0
External RAM
External RAM
SFR
Internal RAM
no
yes
no
yes
1
1
0
1
1
SAS
ISA
Source
Auto-Increment
0
0
1
0
1
1
External RAM
External RAM
SFR
Internal RAM
no
yes
no
yes
1
0
int'et
83C152 HARDWARE DESCRIPTION
There are four modes in which the DMA channel can
operate. These are selected by the bits DM and TM
(Demand Mode and Transfer Mode) in DCONn:
DM
TM
Operating Mode
0
0
1
1
0
1
0
1
Alternate Cycles Mode
Burst Mode
Serial Port Demand Mode
External Demand Mode
The operating modes are described below.
4.1.1 ALTERNATE CYCLE MODE
In Alternate Cycles Mode the DMA is initiated by set·
ting the GO bit in DCONn. Following the instruction
that set the GO bit, one more instruction is executed,
and then the first data byte is transferred from the
source address to the destination address. Then another
instruction is executed, and then another byte of data is
transferred, and so on in this manner.
Each time a data byte is transferred, BCRn (Byte
Count Register for DMA Channel n) is decremented.
When it reaches OOOOH, on-chip hardware clears the
GO bit and sets the DONE bit, and the DMA ceases.
The DONE bit flags an interrupt.
4.1.2 BURST MODE
Burst Mode differs from Alternate Cycles mode only in
that once the data transfer has begun, program execution is entirely suspended until BCRn reaches OOOOH,
indicating that all data bytes that were to be transferred
have been transferred. The interrupt control hardware
remains active during the DMA, so interrupt flags may
get set, but since program execution is suspended, the
interrupts will not be serviced while the DMA is in
progress.
4.1.3 SERIAL PORT DEMAND MODE
In this mode the DMA can be used to service the Local
Serial Channel (LSC) or the Global Serial Channel
(GSC).
In Serial Port Demand Mode the DMA is initiated by
any of the following conditions, if the GO bit is set:
Source Address = SBUF
.AND. RI = 1
Destination Address = SBUF .AND. TI = 1
Source Address = RFIFO
.AND. RFNE = 1
Destination Address = TFIFO .AND. TFNF = 1
Each time one of the above conditions is met, one
DMA Cycle is executed; that is, one data byte is transferred from the source address to the destination ad-
dress. On-chip hardware then clears the flag (RI, TI,
RFNE, or TFNF) that initiated the DMA, and decrements BCRn. Note that since the flag that initiated the
DMA is cleared, it will not generate an interrupt unless
DMA servicing is held off or the byte count equals O.
DMA servicing may be held off when alternate cycle is
being used or by the status of the HOLD/HLDA logic.
In these situations the interrupt for the LSC may occur
before the DMA can clear the RI or TI flag. This is
because the LSC is serviced according to the status of
RI and TI, whether or not the DMA channels are being
used for the transferring of data. The GSC does not use
RFNE or TFNF flags when using the DMA channels
so these do not need to be disabled. When using the
DMA channels to service the LSC it is recommended
that the interrupts (RI and TI) be disabled. If the decremented BCRn is OOOOH, on-chip hardware then
clears the GO bit and sets the DONE bit. The DONE
bit flags an interrupt.
4.1.4 EXTERNAL DEMAND MODE
In External Demand Mode the DMA is initiated by
one of the External Interrupt pins, provided the GO bit
is set. INTO initiates a Channel 0 DMA, and INTI
initiates a Channel 1 DMA.
If the external interrupt is configured to be transitionactivated, then each 1-to-0 transition at the interrupt
pin sets the corresponding external interrupt flag, and
generates one DMA Cycle. Then, BCRn is decremented. No more DMA Cycles take place until another
1-to-0 transition is seen at the external interrupt pin. If
the decremented BCRn = OOOOH, on-chip hardware
clears the GO bit and sets the DONE bit. If the external interrupt is enabled, it will be serviced.
If the external interrupt is configured to be level-activated, then DMA Cycles commence when the interrupt
pin is pulled low, and continue for as long as the pin is
held low and BCRn is not OOOOH. If BCRn reaches 0
while the interrupt pin is still low, the GO bit is cleared,
the DONE bit is set, and the DMAceases. If the external interrupt is enabled, it will be serviced.
If the interrupt pin is pulled up before BCRn reaches
OOOOH, then the DMA ceases, but the GO bit is still 1
and the DONE bit is still O. An external interrupt is not
generated in this case, since in level-activated mode,
pulling the pin to a logical 1 clears the interrupt flag. If
the interrupt pin is then pulled low again, DMA transfers will continue from where they were previously
stopped.
The timing for the DMA Cycle in the transition-activated mode, or for the first DMA Cycle in the level-activated mode is as follows: If the 1-to-0 transition is
10-49
II
I
int:el.,
83C152 HARDWARE DESCRIPTION
detected before the final machine cycle of the instruction in progress, then the DMA commences as soon as
the instruction in progress is completed. Otherwise, one
more instruction will be executed before the DMA
starts. No instruction is executed during any DMA Cycle.
4.2 Timing Diagrams
Timing diagrams for single-byte DMA transfers are
shown in Figures 4.2 through 4.5 for four kinds of
DMA Cycles: internal memory to internal memory, internal memory to external memory, external memory
to internal memory, and external memory to external
memory. In each case we assume the C152 is executing
out of external program memory. If the C152 is executing out of internal program memory, then PSEN is inactive, and the Port 0 and Port 2 pins emit PO and P2
SFR data. If External Data Memory is involved, the
Port 0 and Port 2 pins are used as the address/data bus,
and RD and/or WR signals are generated as needed, in
the same manner as in the execution of a MOVX
@DPTR instruction.
4.3 Hold/Hold Acknowledge
Two operating modes of Hold/Hold Acknowledge logic' are available, and either or neither may be invoked
by software. In one mode, the C152 generates a Hold
Request signal and awaits a Hold Acknowledge response before commencing a DMA that involves external RAM. This is called the Requester Mode.
In the other mode, the C152 accepts a Hold Request
signal from an external device and generates a Hold
Acknowledge signal in response, to indicate to the requesting device that the C152 will not commence a
DMA to or from external RAM while the Hold Request is active. This is called the Arbiter mode.
tool- - - - - - 1 2 osc. PERIODS -----+;1
ALE ~,--- _ _ _ _ _ _ _ _~r-\.,-
___
~----------------------------------~---~
PO ~
__ • __________ _ • _ • ..r~Of~.
~~~!~
_•• _••••••• •
P2~____________~p~2~sr~R________~__-JX~~PC~H_____
_
11_
_ _ _ _ _ _ OMA CYCLE _ _ _ _ _ _ _
RESUME PROGRAM
EXECUTION
270427-29
Figure 4.2. DMA Transfer from Internal Memory to Internal Memory
tool- - - - - - 1 2 osc. PERIODS -----+;,I
....Jr-\.,-___
ALE ~_ _ _ _ _ _ _ _ _ _ _ _
PmlJ
PO
INST : : ]
OARLn
X
OMA DATA OUT
P2~______________~OA~R~H_n____________-JX~__~PC~H~___
WR
\ ....____~I
1_.- - - - - - OMA CYCLE
------_1_ RES~:E~0~g~RAM
270427-30
Figure 4.3. DMA Transfer from Internal Memory to External Memory
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intel~
83C152 HARDWARE DESCRIPTION
t+1- - - - - - 1 2 OSC. PERIODS ------11
ALE
---JI\,--__
~~ _ _ _ _ _ _ _ _
P2~_______________
SA_R_H_n____________~X~
' ....._-----!/
-------D~A CYCLE -------1
___
PC_H_____
RESU~E PROGRA~
EXECUTION
270427-31
Figure 4.4. DMA Transfer from External Memory to Internal Memory
1-"----12
osc.
PERIODS - - - - - 1 - - - - - 1 2 OSC. PERIODS - - - - I
ALE
P2~____________S_A_RH_n__________-,X~
\~
_____..J/
-----------D~A
____________
DA_R_Hn________JX~
___
p_CH
__~
,
.....----~/
1_ RES~:E~~~g~RA~
CYCLE _ _ _ _ _ _ _ _ _ _ _ _ _
270427-32
Figure 4.5. DMA Transfer from External Memory to External Memory
4.3.1 REQUESTER MODE
4.3.2 ARBITER MODE
The Requester Mode is selected by setting the control
bit REQ, which resides in PCON. In that mode, when
the CI52 wants to do a DMA to External Data Memo·
ry, it first generates a Hold Request signal, HLD, and
waits for a Hold Acknowledge signal, HLDA, before
commencing the DMA operation. Note that program
execution continues while HLDA is awaited. The
DMA is not begun until a logical 0 is detected at the
HLDA pin. Then, once the DMA has begun, it goes to
completion regardless of the logic level at HLDA.
For DMAs that are to be driven by some device other
than the C152, a different version of the, Hold/Hold
Acknowledge protocol is available. In this version, the
device which is to drive the DMA sends a Hold Request signal, HLD, to the C152. If the C152 is currently performing a DMA to or from External Data Memory, it will complete this DMA before responding to the
Hold Request. When the CI52 responds to the Hold
Request, it does so by activating a Hold Acknowledge
signal, HLDA. This indicates that the CI52 will not
commence a new DMA to or from External Data
Memory while HLD remains active.
The protocol is activated only for DMAs (not for program fetches or MOVX operations), and only for
DMAs to or from External Data Memory. If the data
destination and source are both internal to the C152,
the HLD/HLDA protocol is not used.
The HLD output is an alternate function of port pin
P1.5, and the HLDA input is an alternate function of
port pin P1.6.
10-51
Note that in the Arbiter Mode the C152 does not suspend program execution at all, even if it is executing
from external program memory. It does not surrender
use of its own bus.
The Hold Request input, HLD, is at P1.5. The Hold
Acknowledge output, HLDA, is at P1.6. This
inteL
83C152 HARDWARE DESCRIPTION
version of the HoldlHold Acknowledge feature is selected by setting the control bit ARB in PCON.
es are done only through DMA operations, not by
MOVX instructions.
The functions of the ARB and REQ bits in PCON,
then, are
One CPU is programmed to be the Arbiter and the
other, to be the Requester. The ALE Switch selects
which CPU's ALE signal will be directed to the address
latch. The Arbiter's ALE is selected if HLDA is high,
and the Requester's ALE is selected if HLDA is low.
ARB
REQ
Hold/Hold Acknowledge Logic
0
0
1
1
0
1
0
1
Disabled
C152 generates HLD, detects HLDA
C152 detects HLD, generates HLDA
Invalid
ALE _ _-.r-_
(ARB)
ALE (ARB)
RIiiA
=1
4.3.3 USING THE HOLD/HOLD ACKNOWLEDGE
IF
The HOLD/HOLDA logic only affects DMA operation with external RAM and doesn't affect other operations with external RAM, such as MOVX instruction.
IF RlJlA =0
ALE (REO)
ALE
(REO)--~~
270427-34
Figure 4.6 shows a system in which two 83CI52s are
sharing a global RAM. In this system, both CPUs are
executing from internal ROM. Neither CPU uses the
bus except to access the shared RAM, and such access-
Figure 4.7. ALE Switch Select
The ALE Switch logic can be implemented by a single
74HCOO, as shown in Figure 4.7.
Vee
8)( 10k.n
83C152
REO
~
pOI\r----~
iiii
P2~=:::::j ~=::::j
~------------~~
~-------~~
270427-33
Figure 4.6. Two 83C152s Sharing External RAM
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intel"
83C152 HARDWARE DESCRIPTION
4.3.4 INTERNAL LOGIC OF THE ARBITER
The internal logic of the arbiter is shown in Figure 4.8.
In operation an input low at HLD sets Q2 if the arbiter's internal signal DMXRQ is low. DMXRQ is the
arbiter's "DMA to XRAM Request". Setting Q2 activates HLDA through Q3. Q2 being set also disables
any DMAs to XRAM that the arbiter might decide to
do during the requester's DMA.
When the arbiter wants to DMA the XRAM, it first
activates DMXRQ. This signal prevents Q2 from being
set if it is not already set. An output low· from Q2 enables the arbiter to carry out its DMA to XRAM, and
maintains an output high at HLDA. When the arbiter
completes its DMA, the signal DMXRQ goes to 0,
which enables Q2 to accept signals from the HLD input
again.
Figure 4.9 shows the minimum response time, 4 to 7
CPU oscillator periods, between a transition at the
HLD input and the response at HLDA.
D
Inhibit Arbiter's
Ot.tA to XRAt.t
Ot.tXRQ
HLO Input
1-....-10
(P1.5)
HLOA Output
(Pl.6)
Clock 1
Clock 2
Clock 1
270427-39
Figure 4.8. Internal Logic of the Arbiter
10-53
intet
83C152 HARDWARE DESCRIPTION
HLD Input
~
1
CPU Osc. Periods
~.&+,- - - - - - -
I I I I I I II I , I I I I. I I I I I I
Clock 1
Clock 2
HLDA Output
1_1
'2 Osc. 40so. '
Periods Period.
I
270427-40
Figure 4.9. Minimum HLD/HLDA Response Time
Inhibit Requester's
DMA to XRAM
Dt.1XRQ
HLDA Input
(Pl.6)
Clock 2
270427-41
Figure 4.10. Internal Logic of the Requester
(Clock 1 and Clock 2 are Shown In Figure 4.9)
10-54
intel..
83C152 HARDWARE DESCRIPTION
4.3.5 Internal Logic of the Requester
The internal logic of the requester is shown in Figure
4.10. Initially, the requester's internal signal DMXRQ
(DMA to XRAM Request) is at 0, so Q2 is set and the
HLD output is high. As long as Q2 stays set, the requester is inhibited from starting any DMA to XRAM.
When the requester wants to DMA the XRAM, it first
activates DMXRQ. This signal enables Q2 to be cleared
(but doesn't clear it), and, if HLDA is high, also activates the HLD output.
A I-to-O transition from HLDA can now clear Q2,
which will enable the requester to commence its DMA
to XRAM. Q2 being low also maintains an output low
at HLD. When the DMA is completed, DMXRQ goes
to 0, which sets Q2 and de-activates HLD.
the request and receive another acknowledge before another DMA cycle to XRAM can proceed. Obviously in
this case, the "alternate cycles" mode may consist of
single DMA cycles separated by any number ofinstruction cycles, depending on how long it takes the requester to regain the bus.
A channel 1 DMA in progress will always be overridden by a DMA request of any kind from channel O. If a
channel 1 DMA to XRAM is in progress and is overridden by a channel 0 DMA which does not require the
bus, DMXRQ will~ 0 during the channel 0 DMA,
thus de-activating HLD. Again, the requester must
new its request for the bus, and must receive a new 1to-O transition in HLDA before channel 1 can continue
its DMA to XRAM.
re-II
4.4 DMA Arbitration
Only DMXRQ going to 0 can set Q2. That means once
Q2 gets cleared, enabling the requester's DMA to proceed, the arbiter has no way to stop the requester's
DMA in progress. At this point, de-activating HLDA
will have no effect on the requester's use of the bus.
Only the requester itself can stop the DMA in progress,
and when it does, it de-activates both DMXRQ and
HLD.
If the DMA is in alternate cycles mode, then each time
a DMA cycle is completed DMXRQ goes to 0, thus deactivating HLD. Once HLD has been de-activated, it
can't be re-asserted till after HLDA has been seen to go
high (through flip-flop QIA). Thus every time the
DMA is suspended to allow an instruction cycle to proceed, the requester gives up the bus and must renew
The DMA\Arbitration described in this section is not
arbitration \between two devices wanting to access a
shared RA!vf:, but on-chip arbitration between the two
DMA channels on the 8XC152.
The 8XC152 provides two DMA channels, either of
which may be called into operation at any time in response to real time conditions in the application circuit.
Since a DMA cycle always uses the 8XC152's internal
bus, and there's only one internal bus, only one DMA
channel can be serviced during a single DMA cycle.
Executing program instructions also requires the internal bus, so program execution will also be suspended in
order for a DMA to take place.
o
2
270427-42
Figure 4.11. Internal Bus Usage
10-55
I
intel~
83C152 HARDWARE DESCRIPTION
Figure 4.11 shows the three tasks to which the internal
bus of the 8XC152 can be dedicated. In this figure,
Instruction Cycle means the complete execution of a
single instruction, whether it takes 1, 2 or 4 machine
cycles. DMA Cycle means the transfer of a single data
byte from source to destination, whether it takes 1 or 2
machine cycles. Each time a DMA Cycle or an Instruction Cycle is executed, on-chip arbitration logic determines which type of cycle is to be executed next.
Note that when an instruction is executed, if the instruction wrote to a DMA register (defined in Figure
4.1 but excluding PCON), then another instruction is
executed without further arbitration. Therefore, a single write or a series of writes to DMA registers will
prevent a DMA from taking place, and will continue to
prevent a DMA from taking place until at least one
instruction is executed which does not write to any
DMA register.
The logic that determines whether the next cycle will be
a DMAO cycle, a DMAI cycle, or an Instruction Cycle
is shown in Figure 4.12 as a pseudo-HLL function. The
statements in Figure 4.12 are executed sequentially unless an "if' condition is satisfied, in which case the corresponding "return" is executed and the remainder of
the function is not. The return value of 0, 1, or 2 is
passed to the arbitration logic block in Figure 4.11 to
determine which exit path from the block is used.
The return value is based on the condition of the GO
bit for each channel, and on the value returned by another function, named mode~ogic (). The algorithm
for mode_logic ( ) is the same for both channels. The
function is shown in Figure 4.13 as a pseudo-HLL
function, mode_logic (n), where n = 0 when the function is invoked for DMA channel 0, and n = 1 when
it's invoked for DMA channell. The value returned by
this function is either 0 or 1, and will be passed on to
the DMA arbitration logic in Figure 4.12.
Note that the arbitration logic as shown in Figure 4.12
always gives precedence to channel 0 over channel 1. If
GOO is set and mode_logic (0) returns a 1, then a
DMAO cycle is called without further reference to the
situation in channell. That is not to say a DMAI Cycle will be interrupted once it has begun. Once a cycle
has begun, be it an Instruction Cycle or a DMA Cycle,
it will be completed without interruption.
The statements in mode_logic (n), Figure 4.13, are executed sequentially until an "if' condition, based on the
DMA mode programmed into DCONn, is satisfied.
For example, if the channel is configured to Burst
mode, then the first if-condition is satisfied, so the "return 1" expression is executed and the remainder of the
function is not.
arbitration_logic:
if (GOO
1 .AND. mode_logic (0)
1) return 0;
if (GOl
1 .AND. mode_logic(l)
1) return 1;
el,se return 2;
end arbitration_logic;
Figure 4.12. DMA Arbitration Logic
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intel·
83C152 HARDWARE DESCRIPTION
mode_logic(n) :
if (DCONn indicates burst_mode) return 1;
if (DCONn indicates extern_demand_mode)
if (demand_flag
= 1)
return 1;
else return 0;
II
if (DCONn indicates SP_demand_mode)
.
.
if
(SARn = SBUF .AND. RI = 1) return 1·
if
(DARn = SBUF .AND. TI = 1) return 1·
if
(SARn = RFIFO .AND. RFNE = 1) return 1 ;
if
(DARn = TFIFO .AND. TFNF = 1 .AND.
previous_cycle = instruction_cycle) return 1 ;
else return 0;
if (DCONn indicates alt_cycles_mode)
if (DCONm indicates .NOT. alt_cycles_mode
.OR. GOm = 0)
if (previous_cycle = instruction_cycle)
return 1;
else return 0;
if (previous_cycle
= instruction_cycle
.AND. previous_dma_cycle = .NOT. DMAn)
return 1;
return 0;
end mode_logic(n) ;
Figure 4.13. DMA Mode Logic
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83C152 HARDWARE DESCRIPTION
If the channel is configured to External Demand mode,
then the first if-condition is not satisfied but the second
one is. In that case the block of statements following
that if-condition and delimited by {... J is executed: if
the demand flag (lEO for channel 0 and lEI for channel I) is set, the "return I" expression is executed and
the remainder of the function is not. If the demand flag
is not set, the "return 0" expression is executed and the
remainder of the function is not.
For example, consider the situation where channel 0 is
configured to service TFIFO and channel 1 is configured to Alternate Cycles mode. Then DMAs to TFIFO
will always override the alternate cycles of channel 1. If
TFIFO needs more than I byte it will receive them in
precendence over channel I, but each DMA to TFIFO
must be preceded by an Instruction cycle. The sequence
of cycles might be:
DMAI cycle
Instruction cycle
DMAI cycle, during which TFNF gets set
Instruction cycle
DMAO cycle
, Instruction cycle
DMAO cycle, as a result of which TFNF gets cleared
Instruction cycle
DMAI cycle
Instruction cycle
DMAI cycle
Instruction cycle
If the channel is configured to Serial Port Demand
mode, the source and destination addresses, SARn and
DARn, have to be checked to see which Serial Port
buffer is being addressed, and whether its demand flag
is set.
.
SARn refers to the 16-bit source address for "this channe1." Note that the condition
SARn = SBUF
cannot be true unless the SAS and ISA bits in DCONn
are configured to select SFR space. If SARn is numerically equal to the address of SBUF (99H), and SAS and
ISA are configured to select internal RAM rather than
SFR space, then SARn refers to location 99H in the
"upper 128" of internal RAM, not to SBUF.
The requirement that a DMA to TFIFO be preceded
by an Instruction cycle can result in the normal precedence of channel 0 over channel 1 being thwarted. Consider for example the situation where channel 0 is configured to service TFIFO, and is in the process of doing
so, and channel 1 decides it wants to do a Burst mode
DMA. The sequence of events might be:
If the test for SARn = SBUF is true, and if the flag RI
is set, mode_logic (n) returns as 1 and the remainder
of the function is not executed. Otherwise, execution
proceeds to the next if-condition, testing DARn against
SBUF and T1 against 1.
Instruction cycle (sets GO bit in DCONI)
Instruction cycle (during which TFNF gets set)
DMAO cycle
DMAI cycle
DMAI cycle
DMAI cycle
The same considerations regarding SAS and ISA in the
SARn test are now applied to DAS and IDA in the
DARn test. If SFR space isn't selected, no Serial Port
buffer is being addressed.
Note that if DMA channel n is configured to Alternate
Cycles mode, the logic must examine the other DCON
register, DCONm, to determine if the other channel is
also configured to Alternate Cycles mode and whether
its GO bit is set. In Figure 4.13, the symbol DCONn
refers to the DCON register for "this channel," and
DCONm refers to "the other channel."
A careful examination of the logic in Figure 4.13 will
reveal some idiosyncracies that the user should be
aware of. First, the logic allows sequential DMA cycles
to be generated to service RFIFO, but not to service
TFIFO. This idiosyncracy is due to internal timing
conflicts, and results in each individual DMA cycle to
TFIFO having to be immediately preceded by an Instruction cycle. The logic disallows that there be two
DMAs to TFIFO in a row.
If the user is unaware of this idiosyncracy, it can cause
problems in situations where one DMA channel is servicing TFIFO and the other is configured to a completely different mode of operation.
DMAI cycle (completes channell burst)
Instruction cycle
DMAO cycle
Instruction cycle
This sequence begins with two Instruction cycles. The
first one accesses a DMA register (DCONI), and therefore is followed by another Instruction cycle, which
presumably does not access a DMA register. After the
second Instruction cycle both channels are ready to
generate DMA cycles, and channel 0 of course takes
precedence. After the DMAO cycle, channel 0 must
wait for an Instruction cycle before it can access
TFIFO again. Channel I, being in Burst mode, doesn't
have that restriction, and is therefore granted a DMAI
cycle. After the first DMAI cycle, channel 0 is still
waiting for an Instruction cycle and channel 1 still does
not have that restriction. There follows another DMAI
cycle.
10-58
infel .
83C152 HARDWARE DESCRIPTION
Function Register (SFR). If DAS = 1 and IDA
the destination is in Internal Data RAM.
=
The result is that in this particular case channel 0 has
to wait until channel 1 completes its Burst mode DMA,
and then has to wait for an Instruction cycle to be generated, before it can continue its own DMA to TFIFO.
The delay in servicing TFIFO can cause an Underflow
condition in the GSC transmission.
IDA (Increment Destination Address) If IDA = 1, the
destination address is automatically incremented after
each byte transfer. If IDA = 0, it is not.
The delay will not occur if channel 1 is configured to
Alternate Cycles mode, since channel 0 would then see
the Instruction cycles it needs to complete its logic requirements for asserting its request.
SAS specifies the Source Address Space. If SAS = 0,
the source is in External Data Memory. If SAS = 1
and ISA = 0, the source is an SFR. If SAS = 1 and
ISA = 1, the source is Internal Data RAM.
4.4.1 DMA Arbitration with Hold/Hold Ack
ISA (Increment Source Address) If ISA = 1, the •
source address .is automatically incremented after each
byte transfer. If ISA = 0, it is not.
The HoldlHold Acknowledge feature is invoked by setting either the ARB or REQ bit in PCON. Their effect
is to add the requirements of the HoldlHold Ack protocol to mode_logic ( ). This amounts to replacing every expression "return 1" in Figure 4.13 with the expression "return hldjlda~ogic ()", where
hld_hlda_logic () is a function which returns 1 if the
HoldlHold Ack protocol is satisfied, and returns 0 otherwise. A suitable definition for hldjlda_logic ( ) is
shown in Figure 4.14.
DM (Demand Mode) If DM = 1, the DMA Channel
operates in Demand Mode. In Demand Mode the
DMA is initiated either by an external signal or by a
Serial Port flag, depending on the value of the TM bit.
If DM = 0, the DMA is requested by setting the GO
bit in software.
TM (Transfer Mode) If DM = 1 then TM selects
whether a,DMA is initiated by an external signal (TM
= 1) or by a Serial Port flag (TM = 0). If DM = 0
then TM selects whether the data transfers are to be in
bursts (TM = 1) or in alternate cycles (TM = 0).
4.5 Summary of DMA Control Bits
DeONn
I DAS I IDA I SAS liSA I OM I TM I DONE I GO I
DONE indicates the completion of a DMA operation
and flags an interrupt. It is set to 1 by on-chip hardware
when BCRn = 0, and is cleared to 0 by on-chip hardware when the interrupt is vectored to. It can also be
set or cleared by software.
DAS specifies the Destination Address Space. If DAS
= 0, the destiilation is in External Data Memory. If
DAS = 1 and IDA = 0, the destination is a Special
hold_holda( ):
= 0 .AND. REQ = 0) return
SARn = XRAM .OR. DARn = XRAM)
if (ARB
if
= 1)
HLDA = 0)
1,
1;
if (ARB
=1
.AND. HLDA
return 1;
if (REQ
=1
.AND.
return 1;
else return 0;
return 1;
end hold_holda( );
Figure 4.14. Hold/Hold Acknowledge Logic as a Pseudo-HLL Function
10-59
I
83C152 HARDWARE DESCRIPTION
GO is the enable bit for the DMA Channel itself. The
DMA Channel is inactive if GO = O.
PCON I SMOD I ARB I REO I GAR EN I XRCLK I GFIEN I PDN IIDL I
ARB enables the DMA logic to detect HLD and generate HLDA. After it has activated HLDA, the Cl52 will
not begin a new DMA to or from External Data Memory as long as HLD is seen to be active. This logic is
disabled when ARB = 0, and enabled when ARB = 1.
The Receive and Transmit Error interrupt flags are
generated by the logical OR of a number of error conditions, which are described in Section 3.6.5.
REQ enables the DMA logic to generate HLD and detect HLDA before performing a DMA to or from External Data Memory. After it has activated HLD, the
CI52 will not begin the DMA until HLDA is seen to be
active. This logic is disabled when REQ = 0, and enabled when REQ = 1.
5.0 INTERRUPT STRUCTURE
The 8XCI52 retains all five interrupts of the 80C5IBH.
Six new interrupts are added in the 8XC152, to support
its GSC and the DMA features. They are as listed below, and the flags that generate them are shown in Figure 5.1.
GSCRV
GSCRE
GSCTV
GSCTE
DMAO
DMAI
-
Note that setting the DMA bit does not itself configure
the DMA channels to service the GSC. That job must
be done by software writes to the DMA registers. The
DMA bit only selects whether the GSCRV and
GSCTV interrupts are flagged by a FIFO needing service or by an "operation done" signal.
Each interrupt is assigned a fixed location in Program
Memory, and the interrupt causes the CPU to jump to
that location. All the interrupt flags are sampled at
S5P2 of every machine cycle, and then the samples are
sequentially polled during the next machine cycle. If
more than one interrupt of the same priority is active,
the one that is highest in the polling sequence is serviced first. The interrupts and their fixed locations in
Program Memory are listed below in the order of their
polling sequence.
RFNE~DMA=O
~GSCRV
RON
GSC Receive Valid
GSC Receive Error
GSC Transmit Valid
GSC Transmit Error
DMA Channel 0 Done
DMA Channel I Done
---t
DMA = 1
.,
270427-43
CRCE~
AE
RCABT
OVR
As shown in Figure 5.1, the Receive Valid interrupt can
be signaled either by the RFNE flag (Receive FIFO
Not Empty), or by the RDN flag (Receive Done).
Which one of these flags causes the interrupt depends
on the setting of the DMA bit in the SFR named
TSTAT.
GSCRE
270427-44
TFNF~DMA=O
~GSCTV
TON
---t
DMA = 1
270427-45
DMA = 0 means the DMA hardware is not configured to service the GSC, so the CPU will service it in
software in response to the Receive FIFO not being
empty. In that case, RFNE generates the Receive Valid
interrupt.
DMA = I means the DMA hardware is configured to
service the GSC, in which case the CPU need not be
interrupted till the receive is complete. In that case,
RDN generates the Receive Valid interrupt.
Similarly the Transmit Valid interrupt can be signaled
either by the TFNF flag (Transmit FIFO Not Full), or
by the TDN flag (Transmit Done), depending on
whether the DMA bit is 0 or 1.
10-60
TCDT3C>--+
UR
GSCTE
NOACK
270427-46
DONE
(DCONO.I)
~ DMAO
DONE
(DCON1.1 )
~ DMA1
270427-47
270427-48
Figure 5.1. Six New Interrupts in the 8XC152
int:eL
83C152 HARDWARE DESCRIPTION
Interrupt
Location
lEO
GSCRV
TFO
GSCRE
DMAO
IE1
GSCTV
DMA1
TF1
GSCTE
TI+RI
0003H
002BH
OOOBH
0033H
003BH
0013H
0043H
0053H
001BH
004BH
0023H
The two Interrupt Priority registers in the 8XCl52 are
as follows: \
3
2
1
0
7
6
5
4
Name
External Interrupt 0
GSC Receive Valid
Timer 0 Overflow
GSC Receive Error
DMA Channel 0 Done
External Interrupt 1
GSC Transmit Valid
DMA Channel 1 Done
Timer 1 Overflow
GSC Transmit Error
UART Transmit/Receive
76
FEd
IPN 1
To support the new interrupts a second Interrupt Enable register and a second Interrupt Priority register are
implemented in bit-addressable SFR space. The two Interrupt Enable registers in the 8XClS2 are as follows:
76543210
I EX1 I ETO I EXO I
Address of IE in SFR space = OA8H (bit-addressable)
76
5
4
3
2
1
5
4
3
2
1
0
PGSTEI PDMA 11PGSTVI PDMAOI PGSRElpGSRg
Address of IPNI in SFR space = OF8H (bit-addressable)
The locations of the new interrupts all follow the locations of the basic 8051 interrupts in Program Memory,
but they are interleaved with them in the polling sequence.
1EA 1-1-1 ES 1ET1
PX1 1 PTO 1 PXO 1
Address of IP in SFR space = OB8H (bit-addressable)
Note that the locations of the basic 8051 interrupts are
the same as in the rest of the MCS-Sl Family. And
relative to each other they retain their same positions in
the polling sequence.
IE:
1- 1-I - 1PS 1PT1
IP:
The bits in IP are unchanged from the standard 8051
IP register. The bits in IPNI are as follows:
PGSTE = 1 GSC Transmit Error Interrupt Priority
to High
= 0 Priority to Low
PDMAI = 1 DMA Channell Done Interrupt Priority to High
= 0 Priority to Low
PGSTV = 1 GSC Transmit Valid Interrupt Priority
to High
= 0 Priority to Low
PDMAO = 1 DMA Channel 0 Done Interrupt Priority to High
= 0 Priority to Low
PGSRE = I GSC Receive Error Interrupt Priority to
High
= 0 Priority to Low
PGSRV = 1 GSC Receive Valid Interrupt Priority to
High
= 0 Priority to Low
0
Note that these registers all have unimplemented bits
("-"). Ifthese bits are read, they will return unpredictable values. If they are written to, the value written
goes nowhere.
IEN1 :lddEGSTEIEDMA 11EGSTVIEDMAOIEGSREIEGSRg
Address pF lEI in SFR space = OC8H (bit-addressable)
The bits in IE are unchanged from the standard 8051
IE register. The bits in IENI are as follows:
EGSTE = 1 Enable GSC Transmit Error Interrupt
= 0 Disable
EDMAI = 1 Enable DMA Channell Done Interrupt
= 0 Disable
EGSTV = 1 Enable GSC Transmit Valid Interrupt
= 0 Disable
EDMAO = 1 Enable DMA Channel 0 Done Interrupt
= 0 Disable
EGSRE = 1 Enable GSC Receive Error Interrupt
= 0 Disable
EGSRV = 1 Enable GSC Receive Valid Interrupt
= 0 Disable
It is recommended that user software 'should never
write Is to unimplemented bits in MCS-51 devices. Future versions of the device may have new bits installed
in these locations. If so, their reset value will be O. Old
software that writes Is to newly implemented bits may
unexpectedly invoke new features.
The MCS-51 interrupt structure provides hardware
support for only two priority levels, High and Low.
With as many interrupt sources as the 8XC152 has, it
may be helpful to know how to augment the priority
structure in software. Any number of priority levels can
be implemented in software by saving and redefining
the interrupt enable registers within the interrupt service routines. The technique is described in the "MCS51" Architectural Overview" chapter in this handbook.
10-61
intel .
83C152 HARDWARE DESCRIPTION
The TCDT bit can get set only if the GSC is configured
to CSMA/CD mode. In that case, the GSC hardware
sets TCDT when a collision is detected during a transmission, and the collision was detected after TFIFO has
been accessed. Also, the GSC hardware sets TCDT
when a detected collision causes the TCDCNT register
to overflow.
5.1 GSC Transmitter Error Conditions
The GSC Transmitter section reports three kinds of
error conditions:
TCDT - Transmitter Collision Detector
UR
- Underrun in Transmit FIFO
NOACK - No Acknowledge
The UR bit can get set only if the DMA bit in TSTAT
is set. The DMA bit being set informs the GSC hardware that TFIFO is being serviced by DMA. In that
case, if the GSC goes to fetch another byte from TFIFO
and finds it empty, and the byte count register of the
DMA channel servicing TFIFO is not zero, it sets the
UR bit.
These bits reside in the TSTAT register. User software
can read them, but only the GSC hardware can write to
them. The GSC hardware will set them in response to
the various error conditions that they represent. When
user software sets the TEN bit, the GSC hardware will
at that time clear these flags. This is the only way these
flags can be cleared.
If the DMA hardware is not being used to service
TFIFO, the UR bit cannot get set. If the DMA bit is 0,
then when the GSC finds TFIFO empty, it assumes
that the transmission of data is complete and the transmission of eRC bits can begin.
The logical OR of these three bits flags the GSC Transmit Error interrupt (GSCTE) and clears the TEN bit,
as shown in Figure 5.2. Thus any detected error condition aborts the transmission. No CRC bits are transmitted. In SDLC mode, no EOF flag is generated. In
CSMA/CD mode, an EOF is generated by default,
since the ,GTXD pin is pulled to a logic 1 and held
there.
WR C O :
NOACK
T
The, NOACK bit is functional only in CSMA/CD
mode, and only when the RABEN bit in RSTAT is set.
The RABEN bit turns on the Hardware Based Acknowledge feature, as described in Section 3.2.6. If this
feature is not invoked, the NOACK bit will stay at 0.
§D=:GSCTE
Clear
TEN
TEN
.
TRANSMIT
EOF
Set
------+ TDN
I -....
270427-49
Figure 5.2. Transmit Error Flags (Logic for Clearing TEN, Setting TON)
10-62
inteL
83C152 HARDWARE DESCRIPTION
>-"""1_-----+ GSCRE
)-_ _.Clear
'---"_'"
GREN
l -....._ _ _ _ _--i~Set
RON
270427-50
Figure 5.3. Receive Error Flag (Logic for Clearing GREN, setting RON)
If the NOACK bit gets set, it .means the GSC has completed a transmission, and was expecting to receive a
hardware based acknowledge from the receiver of the
message, but did not receive the acknowledge, or at
least did not receive it cleanly. There are three ways the
NOACK bit can get set:
1. The acknowledge signal (an unattached preamble)
was not received before the IFS was completed.
2. A collision was detected during the IFS.
3. The line was active during the last bit-time of the
IFS.
The first condition is an obvious reason for setting the
NOACK bit, since that's what the hardware based acknowledge is for. The other two ways the NOACK bit
can get set are to guard against the possibility that the
transmitting station might mistake an unrelated transmission or transmission fragment for an acknowledge
signal.
5.2 GSC Receiver Error Conditions
The GSC Receiver section reports four kinds of error
conditions:
CRCE - CRC Error
AE
- Alignment Error
RCABT - Receive Abort
OVR
- Overrun in Receive FIFO
These bits reside in the RSTAT register. User software
can read them, but only the GSC hardware can write to
them. The GSC hardware will set them in response to
the various error conditions that they represent. When
user software sets the GREN bit, the GSC hardware
will at that time clear these flags. This is the only way
these flags can be cleared.
The logical OR of these four bits flags the GSC Receive
Error interrupt (GSCRE) and clears the GREN bit, as
shown in Figure 5.3. Note in this figure that any error
condition will prevent RON from being set.
A CRC Error means the CRC generator did not come
to its correct value after calculating the CRC of the
message plus received CRC. An Alignment Error
means the number of bits received between the BOF
and EOF was not a multiple of 8.
In SOLC mode, the CRCE bit gets set at the end of any
frame in which there is a CRC Error, and the AE bit
gets set at the end of any frame in which there is an
Alignment Error.
In CSMA/CO mode, if there is no CRC Error, neither
CRCE nor AE will get set. If there is a CRC Error and
no Alignment Error, the CRCE bit will get set, but not
the AE bit. If there is both a CRC Error and an Alignment Error, the AE bit will get set, but not the CRCE
bit. Thus in CSMA/CO mode, the CRCE and AE bits
are mutually exclusive.
The Receive Abort flag, RCABT, gets set if an incoming frame was interrupted after received data had already passed to the Receive FIFO. In SOLC mode, this
can happen if a line idle condition is detected before an
EOF flag is. In CSMA/CO mode, it can happen if
there is a collision. In either case, the CPU will have to
re-initialize whatever pointers and counters it might
have been using.
The Overrun Error flag, OVR, gets set if the GSC Receiver is ready to push a newly received byte onto the
Receive FIFO, but the FIFO is full.
Up to 7 "dribble bits" can be received after the EOF
without causing an error condition.
10-63
III
infel .
83C152 HARDWARE DESCRIPTION
6.0 GLOSSARY
DAS - Destination Address Space, see DCON.
ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address
Match Registers 0,1,2,3 - The contents of these SFRs
are compared against the address bits from the serial
data on the GSC. If the address matches the SFR, then
the C 152 accepts that frame. If in 8 bit addressing
mode, a match with any of the four registers will trigger
acceptance. In 16 bit addressing mode, a match with
ADRI:ADRO or ADR3:ADR2 will be accepted. Address length is determined by GMOD (AL).
DCJ - D.C. Jam, see MYSLOT.
DCONO/I (092H,093H)
7
6
IDAS I IDA
5
4
3
2
1
o
GO
The DCON registers control the operation of the DMA
channels by determining the source of data to be transferred, the destination of the data to be transfer, and the
various modes of operation.
AE - Alignment Error, see RSTAT.
AL - Address Length, see GMOD.
AMSKO, I (OD5H, OE5H) - Address Match Mask 0, I Identifies which bits in ADRO, I are "don't care" bits.
Setting a bit to 1 in AMSKO,l identifies the corresponding bit in ADDRO,l as not to be examined when
comparing addresses.
DCON.O (GO) - Enables DMA Transfer - When set it
enables a DMA channel. If block mode is set then
DMA transfer starts as soon as possible under CPU
control. If demand mode is set then DMA transfer
starts when a demand is asserted and recognized.
DCON.I (DONE) - DMA Transfer is Complete When set the DMA transfer is complete. It is set when
BCR equals 0 and is automatically reset when the
DMA vectors to its interrupt routine. If DMA interrupt is disabled and the user software executes a jump
on the DONE bit, then the user software must also
reset the done bit. If DONE is not set, then the DMA
transfer is not complete.
BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will
equal (fosc)/«BAUD+ I) X 8).
BCRLO, I (OE2H, OF2H) - Byte Count Register Low
0,1 - Contains the lower byte of the byte count. Used
during DMA transfers to identify to the DMA channel~ when the transfer is complete.
BKOFF (OC4H) - Backoff Timer - The backoff timer is
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the
CSMA/CD collision resolution algorithm.
DCON.2 (TM) - Transfer Mode - When set, DMA
burst transfers are used if the DMA channel is configured in block mode or external interrupts are used to
initiate a transfer if in Demand Mode. When TM is
cleared, Alternate Cycle Transfers are used if DMA is
in the Block Mode, or Local Serial channeVGSC interrupts are used to initiate a transfer if in Demand Mode.
BOF - Beginning of Frame flag - A term commonly
used when dealing with packetized data. Signifies the
beginning of a frame.
DCON.3 (OM) - DMA Channel Mode - When set,
Demand Mode is used and when cleared, Block Mode
is used.
CRC - Cyclic Redundancy Check - An error checking
routine that mathematically manipulates a value dependent on the incoming data. The purpose is to identify
, when a frame has been received in error.
DCONA (ISA) - Increment Source Address - When
set, the source address registers are automatically incremented during each transfer. When cleared, the source
address registers are not incremented.
BCRHO, I (OE3H, OF3H) - Byte Count Register High
0,1 - Contains the upper byte of the byte count.
CRCE - CRC Error, see RSTAT.
CSMAlCD - Stands for Carrier Sense, Multiple Access, with Collision Detection.
CT - CRC Type, see GMOD.
DARLO/I (OC2H, OD2H) - Destination Address Register Low 0/1 - Conta.ins the lower byte of the destinations' address when performing DMA transfers.
DARHO/I (OC3H, OD3H) - Destination Address Register Low 0/1 - Contains the upper byte of the destinations' address when performing DMA transfers.
DCON.5 (SAS) - Source Address Space - When set, the
source of data for the DMA transfers is internal data
memory if autoincrement is also set. If autoincrement is
not set but SAS is, then the source for data will be one
of the Special Function Registers. When SAS is cleared,
the source for data is external data memory.
DCON.6 (IDA) - Increment Destination Address
Space - When set, destination address registers are incremented once after each byte is transferred. When
cleared, the destination address registers are not automatically incremented.
10-64
inteL
83C152 HARDWARE DESCRIPTION
DCON.7 (DAS) - Destination Address Space - When
set, destination of data to be transferred is internal data
memory if autoincrement mode is also set. If autoincrement is not set the destinationwill be one of the Special
Function Registers. When DAS is cleared then the destination is external data memory.
DCR - Deterministic Resolution, see MYSLOT.
DEN - An alternate function of one of the port I pins
(Pt.2). Its purpose is to enable external drivers when
the GSC is transmitting data. This function is always
active when using the GSC and if Pt.2 is programmed
to a t.
DM - DMA Mode, see DCONO.
GMOD(84H)
76543210
IXTCLK I M1 I MO I AL I CT I PL1 I PLO I PR I
The bits in this SFR, perform most of the configuration
on the type of data transfers to be used with the GSC.
Determines the mode, address length, preamble length,
protocol select, and enables the external clocking of the
transmit data.
GMOD.O (PR) - Protocol - If set, SDLC protocols with
NRZI encoding, zero bit insertion, and SDLC flags are
used. If cleared, CSMA/CD link access with Manchester encoding is used.
GMOD.I,2 (PLO,I) - Preamble length
DMA - Direct Memory Access mode, see TSTAT.
DONE - DMA done bit, see DCONO.
DPH - Data Pointer High, an SFR that contains the
high order byte of a general purpose pointer called the
data pointer (DPTR).
DPL - Data Pointer Low, an SFR that contains the low
order byte of the data pointer.
EDMAO - Enable DMA Channel 0 interrupt, see
lENt.
EDMAI - Enable DMA Channel I interrupt, see
lENt.
EGSRE - Enable GSC Receive Error interrupt, see
lENt.
EGSRV - Enable GSC Receive Valid interrupt, see
lENt.
. EGSTE - Enable GSC Transmit Error interrupt, see
lENt.
EGSTV - Enable GSC Transmit Valid interrupt, see
lENt.
EOF - A general term used in serial communications.
EOF stands for End Of Frame and signifies when the
last bits of data are transmitted when using packetized
data.
PLl PLO LENGTH (BITS)
o 0
0
018
I
0
32
I
I
64
The length includes the two bit Begin Of frame (BOF)
flag in CSMA/CD but does not include the SDLC flag.
In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
in CSMA/CD mode.
GMOD.3 (CT) - CRC Type - If set, 32-bit AUTODIN11-32 is used. If cleared, 16-bit CRC-CCITT is used.
GMODA (AL) - Address Length - If set, 16-bit addressing is used. If cleared, 8-bit addressing is used. In
8-bit mode, a match with any of the 4 address registers
will allow that frame to be accepted (ADRO, ADRI,
ADR2, ADR3). "Don't Care" bits may be masked in
ADRO and ADRI with AMSKO and AMSKt. In 16bit . mode,
addresses
are
matched
against
"ADRI:ADRO" or "ADR3:ADR2". Again, "Don't
Care" bits in ADRI:ADRO can be masked in AMSKI:AMSKO. A received address of all ones will always be recognized in any mode.
GMOD.5, 6 (MO,MI) - Mode Select - Two test modes,
an optional "alternate backo!r' mode, or normal backoff can be enabled with these two bits.
MI MO Mode
0
0 Normal
I Raw Transmit
0
I
0 Raw Receive
I
I Alternate Backoff
ES - Enable LSC Service interrupt, see IE.
ETO - Enable Timer 0 interrupt, see IE.
ETl - Enable Timer I interrupt, see IE.
EXO - Enable External interrupt 0, see IE.
GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
cleared the internal baud rate generator provides the
EXI - Enable External interrupt I, see IE.
10-65
III
I
83C152 HARDWARE DESCRIPTION
IE.2 (EXI) - Enables the external interrupt INTI on
P3.3.
transmit clock. The input clock is applied to P 1.3
(TxC). The user software is responsible for setting or
clearing this flag. External receive clock is enabled by
setting PCON.3.
IE.3 (ETI) - Enables the Timer I interrupt.
GO - DMA Go bit, see DCONO.
IE.4 (ES) - Enables the Local Serial Channel interrupt.
GRxD - GSC Receive Data input, an alternate function
of one of the port 1 pins (P 1.0). This pin is used as the
receive input for the GSC. P1.O must be programmed
to a 1 for this function to operate.
IE.7 (EA) - The global interrupt enable bit. This bit
must be set to a I for any other interrupt to be enabled.
GSC - Global Serial Channel - A high-level, multi-protocol, serial communication controller added to the
SOC5IBH core to accomplish high-speed transfers of
packetized serial data.
GTxD - GSC Transmit Data output, an alternate function of one of the port 1 pins (P 1.1). This pin is used as
the transmit output for the GSC. Pl.1 must be programmed to a I for this function to operate.
HBAEN - Hardware Based Acknowledge Enable, see
RSTAT.
HLDA - Hold Acknowledge, an alternate function of
one of the port 1 pins (P1.6). This pin is used to perform the "HOLD ACKNOWLEDGE" function for
DMA transfers. HLDA can be an input or an output,
depending on the configuration of the DMA channels.
P1.6 must be programmed to a I for this function to
operate.
HOLD - Hold, an alternate function of one of the port
I pins (P1.5). This pin is used to perform the "HOLD"
function for DMA transfers. HOLD can be an input or
an output, depending on the configuration of the DMA
channels. P1.5 must be programmed to a I for this
function to operate.
76
7
EA
6
5
I ES I ET1 I EX1 I ETO
4
IENI - (OCSH)
3
2
1
0
IIIEGSTEIEDMA11EGSTVIEDMAOIEGSREIEGSRVI
Interrupt enable register for DMA and GSC interrupts.
A I in any bit po~ition enables that interrupt.
IEN1.O (EGSRV) - Enables the GSC valid receive interrupt.
IENl.1 (EGSRE) - Enables the GSC receive error interrupt.
IEN1.2 (EDMAO) - Enables the DMA done interrupt
for Channel O.
IEN1.3 (EGSTV) - Enables the GSC valid transmit interrupt.
IEN1.4 (EDMAl) - Enables the DMA done interrupt
for Channel 1.
IEN1.5 (EGSTE) - Enables the GSC transmit error interrupt
IFS - (OA4H) Interframe Space, determines the number
of bit times separating transmitted frames in CSMAI
CD and SDLe.
IDA - Increment Destination Address, see DCONO.
IE (OASH)
4
3
2
5
IP (OBSH)
76543210
o
PS I PT1 I PX1 I PTO
EXO
Interrupt Enable SFR, used to individually enable the
Timer and Local Serial Channel interrupts. Also contains the global enable bit which must be set to a I to
enable any interrupt to be automatically recognized by
the CPU.
IE.O (EXO) - Enables the external interrupt INTO on
P3.2.
.
PXO
Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IE. A 1 assigns
the corresponding interrupt in IE a higher interrupt
than an interrupt with a corresponding O.
IP.O (PXO) - Assigns the priority of external interrupt,
INTO.
IP.I (PTO) - Assigns the priority of Timer 0 interrupt,
TO.
IE.l (ETO) - Enables the Timer 0 interrupt.
10-66
intel .
83C152 HARDWARE DESCRIPTION
IP.2 (PX1) - Assigns the priority of external interrupt,
INT!.
IP.3 (PT1) - Assigns the priority of Timer 1 interrupt,
T1.
IP.4 (PS) - Assigns the priority of the LSC interrupt,
SBUF.
IPNI - (OFSH)
7
6
I I I
5
PGSTE
I
4
PDMAI
3
2
·1
Determines which type of Jam is used, which backoff
algorithm is used, and the DCR slot address for the
GSC.
MYSLOT.O,I,2,3,4,S (SAO,I,2,3,4,5) - These bits determine which slot address is assigned to the C1S2 when
using deterministic backoff during CSMA/CD operations on the GSC. Maximum slots available is 63. An
address of OOH prevents that station from participating
in the backoff process.
0
I PGSTV I PDMAO I PGSRE I PGSRV I
Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IEN1. A 1 assigns the corresponding interrupt in IENI a higher interrupt than an interrupt with a corresponding O.
IPN1.0 (PGSRV) - Assigns the priority ofGSC receive
valid interrupt.
IPN 1.1 (pGSRE) - Assigns the priority of GSC error
receive interrupt.
.
MYSLOT.6 (DCR) - Determines which collision resolution algorithm is used. If set to a I, then the determi-II
nistic backoff is used. If cleared, then a random slot
.assignment is used.
MYSLOT.7 (DCJ) - Determines the type of Jam used
during CSMA/CD operation when a collision occurs.
If set to a 1 then a low D.C. level is used as the jam
signal. If cleared, then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
CRC length.
NOACK - No Acknowledgment error bit, see TSTAT.
IPN1.2 (PDMAO) - Assigns the priority ofDMA done
interrupt for Channel O.
IPN1.3 (PGSTV) - Assigns the priority of GSC transmit valid interrupt.
NRZI - Non-Return to Zero inverted, a type of data
encoding where a 0 is represented by a change in the
level of the serial link. A 1 is represented by no change.
OVR - Overrun error bit, see RSTAT.
IPN1.4 (PDMA1) - Assigns the priority of DMA done
interrupt for Channel 1.
PR - Protocol select bit, see GMOD. PCON (S7H)
76543210
IPN1.5 (PGSTE) - Assigns the priority of GSC transmit error interrupt.
ISMool ARBI REOI GAREN IXRCLKI GFIENI pol lOLl
ISA - Increment Source Address, see DCONO.
PCON.O (IDL) - Idle bit, used to place the C1S2 into
the idle power saving mode.
LNI - Line Idle, see TSTAT.
LSC - Local Serial Channel - The asynchronous serial
port found oil. all MCS-51 devices. Uses start/stop bits
and can transfer only 1 byte at a time.
MO - One of two GSC mode bits, see TMOD.
Ml - One of two GSC mode bits, see TMOD
7
6
MYSLOT - (OFSH)
5
432
1
PCON.l (PD) - Power Down bit, used to place the
C1S2 into the power down power saving mode.
PCON.2 (GFIEN) - GSC Flag Idle Enable bit, when
set, enables idle flags (01111110) to be generated between transmitted frames in SDLC mode.
PCON.3 (XRCLK) - External Receive Clock bit, used
to enable an external clock to be used for only the receiver portion of the GSC.
0
1~locRI~I~I~I~lwl~1
PCON.4 (GAREN) - GSC Auxiliary Receive Enable
bit, used to enable the GSC to receive back-to-back
SDLC frames. This bit has no effect in CSMA/CD
mode.
10-67
int:el..
83C152 HARDWARE DESCRIPTION
PCON.5 (REQ) - Requester mode bit, set to a 1 when
CI52 is to be operated as the requester station during
DMA transfers.
RI - LSC Receive Interrupt bit, see SCON.
RFIFO - (F4H) RFIFO is a 3-byte FIFO that contains
the receive data from the GSC.
PCON.6 (ARB) - Arbiter mode bit, set to a 1 when
CI52 is to be operated as the arbiter during DMA
transfers.
RSTAT (OE8H) - Receive Status Register
76543210
PCON.7 (SMOD) - LSC mode bit, used to double the
baud rate on the LSC.
RSTA T.O (HBAEN) - Hardware Based Acknowledge
Enable - If set, enables the hardware based acknowledge feature.
PDMAO - Priority bit for DMA Channel 0 interrupt,
see IPNI.
PDMAI - Priority bit for DMA Channell interrupt,
see IPNI.
RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. The user
must clear RFIFO with software before enabling the
receiver. RFIFO is cleared by reading the contents of
RFIFO until RFNE = O. After each read of RFIFO, it
takes one machine cycle for the status of RFNE to be
updated. Setting GREN also clears RDN, CRCE, AE,
and RCABT. GREN is cleared by hardware at the end
of a reception or if any receive errors are detected. The
status of GREN has no effect on whether the receiver
detects a collision in CSMAlCD mode as the receiver
input circuitry always monitors the receive pin.
PGSRE - Priority bit for GSC Receive Error interrupt,
see IPNI.
PGSRV - Priority bit for GSC Receive Valid interrupt,
see IPNI.
PGSTE - Priority bit for GSC Transmit Error interrupt, see IPNI.
PGSTV - Priority bit for GSC Transmit Valid interrupt, see IPNI.
RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The re- ,
ceive FIFO is a three byte buffer into which the receive
data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO pointers. Setting GREN to a one will clear the receive FIFO.
The status of this flag is controlled by the GSc. This bit
is cleared if user software empties receive FIFO.
PLO - One of two bits that determines the Preamble
Length, see GMOD.
PLl - One of two bits that determines the Preamble
Length, see GMOD.
PRBS - (OE4H) Pseudo-Random Binary Sequence, generates the pseudo-random number to be used in
CSMA/CD backoff algorithms.
RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred.
PS - Priority bit for the LSC service interrupt, see IP.
PTO - Priority bit for Timer 0 interrupt, see IP.
RSTAT.4 (CRCE) - CRC Error - Ifset, indicates that a
properly aligned frame was received with a mismatched
CRC.
PTl - Priority bit for Timer 1 interrupt, see IP.
PXO - Priority bit for External interrupt 0, see IP.
PXI - Priority bit for External interrupt I, see IP.
RCABT - GSC Receiver Abort error bit, see RSTAT.
RDN - GSC Receiver Done bit, see RSTAT.
GREN - GSC Receiver Enable bit, see RSTAT.
RFNE - GSC Receive FIFO Not Empty bit, see
RSTAT.
RSTAT.5 (AE) - Alignment Error - In CSMA/CD
mode, AE is set ifthe receiver shift register (an internal
serial-to-parallei converter) is not full and the CRC is
bad when an EOF is detected. In CSMA/CD the EOF
is a line idle condition (see LNI) for two bit times. If
the CRC is correct while in CSMA/CD mode, AE is
not set and any mis-alignment is assumed to be caused
by dribble bits as the line went idle. In SDLC mode,
AE is set if a non-byte-aligned flag is received. CRCE
may also be set. The setting of this flag is controlled by
the GSC.
10-68
inteL
83C152 HARDWARE DESCRIPTION
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
- If set, indicates that a collision was detected after data
had been loaded into the receive FIFO in CSMA/CD
mode. In SDLC mode, RCABT indicates that 7 consecutive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO. AE may
also be set if RCABT is set.
RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
written into it. It is cleared by user software. AE
and/or CRCE may also be set if OVR is set.
SARHO (OA3H) - Source Address Register High 0,
contains the high byte of the source address for DMA
ChannelO.
SCON.7 (SM2) - LSC mode specifier.
SDLC - Stands for Synchronous Data Link Communication and is a protocol developed by IBM.
SLOTTM - (OB4H) Determines the length of the slot
time in CSMA/CD.
SP (081 H) - Stack Pointer, an eight bit pointer register
used during a PUSH, POP, CALL, RET, or RET!.
TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using probabilistic CSMA/CD •
and contains the maximum number of slots in the deterministic mode.
TCDT - Transmit Collision Detect, see TSTAT.
SARHI (OB3H) - Source Address Register High 1,
contains the high byte of the source address for DMA
Channel 1.
SARLO (OA2H) - Source Address Register Low 0, contains the low byte of the source address for DMA
ChannelO.
7
I TF1
6
5
I TR1 I TFO
TCON(088H)
4
3
I TRO
2
IIE1 IIT1
1
lEO liTO
TCON.I (lEO) - External interrupt 0 edge flag.
SAS - Source Address Space bit, see DCONO.
TCON.3 (lEI) - External interrupt 1 edge flag.
SBUF (099H) - Serial Buffer, both the receive and
transmit SFR location for the LSC.
TCONA (TRO) - Timer 0 run control bit.
I SMO I SM1 15M2 I REN I TBS I RBS I TI I RI
I
TCON.O (ITO) - Interrupt 0 mode control bit.
SARLI (OB2H) - Source Address Register Low I, contains the low byte of the source address for DMA
Channell.
SCON(09SH)
76543210
0
TCON.2 (ITt) - Interrupt 1 mode control bit.
CON.S (TFO) - Timer 0 overflow flag.
I
TCON.6 (TRI) - Timer 1 run control bit.
TCON.7 (TFI) - Timer 1 overflow flag.
SCON.O (RI) - Receive Interrupt flag.
TDN - Transmit Done flag, see TSTAT.
SCON.1 (TI) - Transmit Interrupt flag.
TEN - Transmit Enable bit, see TSTAT.
SCON.2 (RBS) - Receive Bit 8, contains the ninth bit
that was received in Modes 2 and 3 or the stop bit in
Mode 1 if SM20. Not used in Mode O.
TFNF - Transmit FIFO Not Full flag, see TSTAT.
SCON.3 (TB8) - Transmit Bit 8, the ninth bit to be
transmitted in Modes 2 and 3.
TFIFO - (SSH) TFIFO is a 3-byte FIFO that contains
the transmission data for the GSC.
THO (08CH) - Timer 0 High byte, contains the high
byte for timer/counter O.
SCONA (REN) - Receiver Enable, enables reception
for the LSC.
SCON.S (SM2) - Enables the mUltiprocessor communication feature in Modes 2 and 3 for the LSC.
SCON.6 (SMI) - LSC mode specifier.
10-69
int:el.,
83C152 HARDWARE DESCRIPTION
THI (OSDH) - Timer I High byte, contains the high
byte for timer/counter 1.
TI - Transmit Interrupt, see SCON.
TLO (OSAH) - Timer 0 Low byte, contains the low byte
for timer/counter O.
TLl (OSBH) - Timer I Low byte, contains the low byte
for timerI counter 1.
ter a successful transmission, a collision during the
data, CRC, or end flag. If cleared during a transmission
the GSC transmit pin goes to a steady state high level.
This is the method used to send an abort character in
SDLC. Also DEN is forced to a high level. The end of
. transmission occurs whenever the TFIFO is emptied.
TSTAT.2 (TFNF) - Transmit FIFO not full - When
set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte buffer that loads the transmit shift register with data.
TM - Transfer Mode, see, DCONO.
TMOD(OS9H)
76543210
, GATE' CIT' M1 , MO , GATE' CIT' M1 , MO I
TMOD.O (MO) - Mode selector bit for Timer O.
TMOD.1 (MI) - Mode selector bit for Timer O.
TSTAT.3 (TDN) - Transmit Done - When set, indicates the successful completion of a frame transmission.
If HBAEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the
acknowledge can be checked. If an acknowledge is expected and not received, TDN is not set. An acknowledge is not expected following a broadcast or multi-cast
packet.
TSTATA (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or
if there are more than eight collisions.
TMOD.2 (CIT) - Timer/Counter selector bit for
Timer O.
TMOD.3 (GATE) - Gating Mode bit for Timer O.
TiSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter halts
without sending the CRC or the end flag.
TMODA (MO) - Mode selector bit for Timer 1.
TMOD.5 (MI) - Mode selector bit for Timer 1.
TMOD.6 (CIT) - Timer/Counter selector bit for
Timer 1.
TSTAT.6 (NOACK) - No Acknowledge - Ifset, indicates that no acknowledge was received for the previous
frame. Will be set only if HBAEN is set and no acknowledge is received prior to the end of the IFS.
NOACK is not set following a broadcast or a multicast packet.
TMOD.7 (GATE) - Gating Mode bit for Timer 1.
TSTAT (OD8) - Transmit Status Register
76543210
, LNII NOACK I UR I TCDT I TON I TFNF I TEN I DMA I
TSTAT.O (DMA) - DMA Select - If set, indicates that
DMA channels are used to service the GSC FIFO's and
GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the
GSC is operating in it normal mode and interrupts occur on TFNE and RFNE.For more information on
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3).
TSTAT. I (TEN) - Transmit Enable - When set causes
TDN, UR, TCDT, and NOACK flags to be reset and
the TFIFO cleared. The transmitter will clear TEN af-
TSTAT.7 (LNI) - Line Idle - If set, indicates the receive line is idle. In SDLC protocol it is set if 15 consecutive ones are received. In CSMA/CD protocol, line
idle is set if GR X D remains high for approximately 1.6
bit times. LNI is cleared .after a transition on GR X D.
TxC - External Clock input for GSC transmitter.
UR - Underrun flag, see TSTAT.
XRCLK - External GSC Receive Clock Enable bit, see
PCON.
XTCLK - External GSC Transmit Clock Enable bit,
see GMOD.
10-70
8XC152JA/JB/JC/JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCONTROLLER
•
•
•
•
•
•
•
•
8K Factory Mask Programmable ROM Available
Superset of 80C51 Architecture
Multi-Protocol Serial Communication
I/O Port (2.048 Mbps/2.4 Mbps Max)
- SDLC/HDLC Only
- CSMA/CD and SDLC/HDLC
- User Definable Protocols
Full Duplex/Half Duplex
MCS®-51 Compatible UART
16.5 MHz Maximum Clock Frequency
Multiple Power Conservation Modes
64KB Program Memory Addressing
•
•
•
•
•
•
•
•
•
64KB Data Memory Addressing
256 Bytes On-Chip RAM
Dual On-Chip DMA Channels
Hold/Hold Acknowledge
Two General Purpose Timer/Counters
5 or 7 I/O Ports
56 Special Function Registers
11 Interrupt Sources
Available in 48 Pin Dual-in-Line Package
and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec. Order #231369)
The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-toserial and serial-ta-parallel converters. The 83C152 contains, in silicon, all the features needed for the serialto-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of these-cost, network parameter and real estate improvementsapply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
10-71
October 1989
Order Number: 270431-003
III
intel.,
~mI!..OfM1000b\OOW
8XC152JA/JB/JC/JD
vee
(GTOX) P1.1
P4.0
(DEN) P1.2
P4.1
(TXC)
P1.3
P4.2
(RXc) P1.4
(HLD) P1.S
(HillA) P1.6
P4.3
P.,4
P1.7
P....6
P3.1
P".7
P3.2
RESET
"l
CORNER""
~
'1 C"f
~
tft.i u
z z
:l
z
..,
i ~ :. :. i
N
. . .'" . ..,.
"-
~
;;
1O
P4.5
P1.7
11
N.C.
12
P"',6
P4.7
N.C.
13
P",5
9
. .... .... ~>~>8~
IMOO<
(GRXD) P1.0
1.
(RXD) P3.0
u
(TXD) P3.1
(iNTO) P3.2
(IN11) P3.3
ALE
P3.3
PSEN
Pl.4
N.C.
U
ALE
PSEN
(TOP VIEW)
17
N.C.
80C152JA
83C152JA
80C152JC
83C152JC
N.C.
N.C.
P2.7 (A15)
N.C.
(TO) P3.4
P2.6 (AU)
N.C.
N.C.
N.C.
(11) P3.5
P2.5 (A13)
P2.4 (A12)
N.C.
P2.7
P3.5
P2.6
(Viii) P3.6
(iffi) P3.7
(A/DO) PO.O
(A/Dl) PO.l
(A/D2) PO.2
P2.3 (Al1)
P2.2 (Al0)
P3.6
P2.5
P3.7
P2 ....
P2.1 (A9)
P2.0 (A8)
N.C.
~
(A/D3) PO.3
PO.7 (A/D7)
XTAL2
PO.6 (A/D6)
XTAL1
PO.5 (A/DS)
po."
VSS
1!l
..
N
0
..,
;;; :;:
q """: <'j '1 !:j
~ f ~ ~ ~
~
~ ~
li!'I
>
~
....
..,'" :s: ::; .., ..,
.., <>
"l
~
g~
:Z Z ~
(A/O<)
P4.S
P1.6
P1.7
P4.6
EBEN
P•.7
P6.3
U
P3.0
P3.2
P5.0
P3.3
P3.•
c,j
:;:
~ ~
~ ~
N
~
270431-2
270431-1
P3.1
P2.3
~
(TOP VIEW)
80C152JB
80C152JD
ALE
PSEN
[PSEN
P6.2
P6.7
P5.1
P6 ....
P5.2
P5.7
P5.3
P2.7
P3.5
P2.6
P3.6
P2.5
P3.7
P2."
P2.3
N.C.
270431-3
Figure 1. Connection Diagrams
10-72
infel"
8XC152JA/JB/JC/JD
RXD
TXD
8 kBYTE
ROM/
EPROM
SPECIAL
FUNCTlON
REGISTIERS
256
BYTES
8 BIT
CPU
RAM
8
GLOBAL
SERIAL
CHANNEL
III
HLD/HLDA
._--------INT
INPUT
'On 80C152JB/JD Only
270431-18
Figure 2. Block Diagram
10-73
8XC152JAtJBtJCtJD
EPSEN is used in conjunction with Port 5 and Port 6
program memory operations. EPSEN functions like
PSEN during program mesory operation, but supports Port 5 and Port 6. EP EN is the read strobe to
external program memory for Port 5 and Port 6.
EPSEN is activated twice during each machine cycle
unless an external data memory operation occurs on
Port(s) 0 and Port 2. When external data memory is
accessed the second activation of EPSEN is
skipped, which is the same as when using PSEN.
Note that data memory fetches cannot be made
through ports 5 and 6.
80C152JB/JD General Description
The 80C152JB/JD is a ROMless extension of the
80C152 Universal Communication controller. The
80C152JB has the same five 8-bit I/O ports of the
80C152, plus an additional two 8-bit I/O ports, Port 5
and Port 6. The 80C152JB/JD also has two additional control pins, EBEN (EPROM Bus ENable), and
EPSEN (EPROM bus Program Store ENable).
EBEN selects the functionality of Port 5 and Port 6.
When EBEN is low, these ports are strictly I/O, similar to Port 4. The SFR location for Port 5 is 91 Hand
Port 6 is OA 1H. This means Port 5 and Port 6 are not
bit addressable. With EBEN low, all program memory fetches take place via Port 0 and Port 2. (The
80C152 is a ROMless only product). When EBEN is
high, Port 5 and Port 6 form an address/data bus
called the E-Bus (EPROM-Bus) for program memory
operations.
When EBEN is high and EA is low, all program memory operations take place via Ports 5 and 6. The high
byte of the address goes out on Port 6, and the low
byte is output on Port 5. ALE is still used to latch the
address on Port 5. Next, the op code is read on Port
5. The timing is the same as when using Ports 0 and
2 for external program memory operations.
Table 1. Program Memory Fetches
EBEN
~
Program
Fetch via
PSEN
EPSEN
Comments
Addresses O-OFFFFH
0
0
PO,P2
Active
Inactive
0
1
N/A
N/A
N/A
1
0
P5,P6
Inactive
Active
1
1
P5,P6
PO,P2
Inactive
Active
Active
Inactive
Invalid Combination
Addresses O-OFFFFH
.Addresses 0-1 FFFH
Addresses :<:: 2000H
Table 2 8XC152 Product Differences
ROMless
Version
CSMA/CO
and
HOLC/SOLC
80C152JA
80C152JB
80C152JC
80C152JD
HOLC/SOLC
Only
*
*
*
*
ROM
Version
Available
*(83C152JA)
*
*(83C152JC)
*
PLCC,
Only
options available
o standard frequency range 3.5 MHz to 12 MHz
0"-1" frequency range 3.5 MHz to 16.5 MHz
10-74
51/0
Ports
71/0
Ports
*
*
*
*
*
NOTES:
*=
PLCC
and
DIP
*
infel .
DIP
8XC152JAI JBI JCI JD
Pin #
PLCC(1)
48
Pin Description
2
3,33(2)
Vcc-Supply voltage.
24
18-21,
25-28
27-30,
34-37
Port O-Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin
can sink 8 LS TIL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the multiplexed
data bus. In these applications it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
required during program verification.
1-8
4-11
Port 1-Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
Vss-Circuit ground.
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
Alternate Function
Name
GSC data input pin
GSC data output pin
GSC enable signal for. an external driver
GSC input pin for external transmit clock
GSC input pin for external receive clock
DMA hold input/output
DMA hold acknowledge input/output
GRXD
GTXD
DEN
TXC
RXC
HLD
HLDA
29-36
41-48
Port 2-Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the intern~1 pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled low, During accesses to external Data Memory that use 16bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order
address byte. In these applications it uses strong internal pullups when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
10-17
14-16,
18,19,
23-25
Port 3-Port 3 is an 8-bit bidirectional 1/0 port with internal pullups. Port 3 pins that
have 1s wri~en to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Alternate Function
Pin
Name
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD
TXD
INTO
INT1
TO
T1
WR
RD
Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe
10-75
II
infel .
8XC1,52JA/JB/JC/JD
Pin Description (Continued)
Pin #
47-40
65-58
9
13
38
55
37
54
39
56
23
32
22
N/A
31
17,20
21,22
38,39
40,49
N/A
67,66
·52,57
50,68
·1,51
N/A
12
N/A
53
Pin Description
Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pull ups. In addition,
Port 4 also receives the low-order address bytes during program verification.
RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.
ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.
PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.
EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetqh code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.
XTAL 1-lnput to the inverting oscillator amp.lifier and input to the internal clock
generating circuits.
XTAL2-Output from the inverting oscillator amplifier.
Port 5-Port 5 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 5 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. AS-inputs, Port 5 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups.
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled high. In this application it uses strong
pull ups when emitting 1s.
Port 6-Port 6 is an 8-bit bidirectional 1/0 port with internal pullups. Port 6 pins that
have 1s wi'itten to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 6 pins that are externally pulled low will source
current (IlL, on the data sheet) because of the internal pull ups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. In this application it uses strong pull ups when
emitting 1s.
EBEN-E-Bus Enable input that designates whether program memory fetches take
place via Ports 0 and 2 or Ports 5 and 6. Table 1 shows how the ports are used in
conjunction with EBEN.
EPSEN-E-bus Program Store Enable is the Read strobe to external program
memory when EBEN is high. Table 2 shows when EPSEN is used relative to PSEN
depending on the status of EBEN and EA.
10-76
inteL
8XC152JAIJBt JCt JD
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.
NC -
XTAL2
EXTERNAL
OSCILLATOR - - - o f XTAL 1
SIGNAL
To drive the device from an external clock source,
XTAL 1 should be driven, while XT AL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
£,-v_s_s__
270431-6
Figure 4. External Clock Drive
IDLE MODE
An external oscillator may encounter as much as a
100 pF load at XTAL 1 when it starts-up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.
XTAL2
POWER DOWN MODE
In Power Down Mode, the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software. The Power Down
Mode can be terminated only by a hardware reset.
XTAL 1
.....-------1 vss
270431-5
Figure 3. Using the On-Chip Oscillator
Table 3. Status of the External Pins During Idle and Power Down Modes
80C152JA/83C152JA/80C152JC/83C152JC
Program
Memory
ALE
PSEN
PortO
Port 1
Port 2
Port 3
Port 4
Idle
Internal
1
1
Data
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Data
Power Down
External
0
ot
Float
Data
Data
Data
Data
Mode
80C152JB/80C152JD
Mode
Instruction
ALE PSEN EPSEN PortO Port 1
Bus
Port 2
Port 3 Port 4 Port 5
Port 6
Idle
PO,P2
1
1
1
Float
Data
Address
Data
Data
OFFH
Idle
P5,P6
1
1
1
Data
Data
Data
Data
Data
OFFH Address
Power Down
PO, P2
0
0
1
Float
Data
Data
Data
Data
OFFH
OFFH
OFFH
OFFH
Power Down
P5,P6
0
1t
0
Data
Data
Data
Data
Data
OFFH
NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "Designing with the BOC51 BH."
tNote difference of logic level of PSEN during Power Down for ROM JAlJC and ROM emulation mode for JC/JD.
10-77
II
axc 152JAtJBtJCtJD
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature Under Bias .... O·C to + 70·C
Storage Temperature .......... -65·Cto +150·C··
Voltage on Any pin to Vss ... -0.5V to (Vee + 0.5V)
Voltage on Vee to VSS ...... ; .. , . -0.5V to + 6.5V
Power Dissipation ....................... 1.0W(9)
D.C. CHARACTERISTICS
Symbol
(TA
=
Parameter
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
O·C to + 70·C; Vee
=
5V ± 10%; Vss
Typ
(Note 3)
Min
=
OV)
Max
Unit
Test Conditions
Vlt
Input Low Voltage
.(AII Except EA, EBEN)
-0.5
0.2Vee- 0.1
V
VIL1
Input Low Voltage
(EA, EBEN)
-0.5
0.2Vee- 0.3
V
VIH
Input High Voltage
(Except XTAL 1, RST)
0.2Vee+ 0.9
Vee+ 0.5
V
VIH1
Input High Voltage
(XTAL 1, RST)
0.7Vee
Vee+ 0.5
V.
VOL
Output Low Voltage
(Ports 1, 2, 3, 4, 5, 6)
0.45
V
IOL = 1.6 mA
(Note 4)
Vou
Output Low Voltage
(Port 0, ALE, PSEN, EPSEN)
0.45
V
IOL = 3.2mA
(Note 4)
VOH
Output High Voltage
(Ports 1, 2, 3, 4, 5, 6 COMM9
ALE, PSEN, EPSEN)
2.4
V
IOH = -60/LA
Vee = 5V ±10%
0.9Vee
V
VOH1
Output High Voltage
(Port 0 in External
Bus Mode)
2.4
V
0.9Vee
V
IlL
Logical 0 Input
Current (Ports 1, 2, 3, 4, 5, 6)
-50
/LA
ITL
Logical 1 to 0
Transition Current
(Ports 1, 2, 3, 4, 5, 6)
-650
/LA
III
Input Leakage
(Port 0, EA)
±10
/LA
RRST
Reset Pullup Resistor
IIH
Logical 1 Input Current (EBEN)
Icc
Power Supply Current:
Active (16.5 MHz)
Idle (16.5 MHz)
Power Down Mode
40
= -10 /LA
= - 400 /LA
= 5V ±10%
= - 40 /LA (Note 5)
VIN = 0.45V
IOH
IOH
Vee
IOH
VIN
=
2V
0.45c
vee-o.s=>( 0.2 Vee+0.9
0.2Vee -0.1
0.4S v
;........;;.;...-----
r-------""""\
VLOAO+0.1 V
VLOAO
____ TIMING REFERENCE..............
,
- -_
- __
POINTS
---VLOAO-0.1 V '_
____
_
270431-13
270431-14
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs, and Begins to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH ;, ± 20 rnA.
AC Inputs During Testing are Driven at Vee-O.S for a Logic "1"
and O.4SV for a Logic "0". Timing Measurements are made at VIH
Min for a Logic "1" and Vil Max for a Logic "0".
10-83
II
intel..
8XC152JA/JB/JC/JD
GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate Generator
Symbol
16.5 MHz (BAUD = 0)
Parameter
Min
Variable Oscillator
Min
Max
Unit
Max
HBTJR
Allowable jitter on
the Receiver for %
bit time (Manchester
encoding only)
0.0375
(0.125 x
(BAUD+1)X
STCLCL)
-25ns
ILs
FBTJR
Allowable jitter on
the Receiver for one
full bit time (NRZI
and Manchester)
0.10
(0.25 x
(BAUD+1)X
STCLCL)
-25ns
ILs
HBTJT
Jitter of data from
Transmitter for %
bit time (Manchester
encoding only)
±10
±10
ns
FBTJT
Jitter of data from
Transmitter for one
full bit time (NRZI
and Manchester)
±10
±10
ns
DRTR
Data rise time for
Receiver(11)
20
20
ns
DFTR
Data fall time for
Receiver(12)
20
20
ns
GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)
I'
I
MANCHESTER
=::x
I
I
NRZI
=::x
BT
'I
I
~*~
~
....1
*~
~I~I
1. . . .i'~·
HBTJR
~
"
I
)K
'i
l
.~
I
X=::GRXD
I
FBTJR
GRxD
FBTJR
270431-15
10-S4
infel"
8XC152JA/JB/JC/JD
GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)
*
~I'--------BT--------~'I
I
I
c::GTxD
MANCHESTER =:Ji(,.....--~$'"'*
$
$
$
I
1~'-'jo,""'---""'--9,'--'I
I
H8TJT
FBTJT
I
NRZI=:Ji("'-______""$¢'.==~~:.==.$~,______.......
F8TJT
r
1------"'"
c:: GTxD
270431-16
GLOBAL SERIAL PORT TIMINGS-External Clock
Symbol
16.5 MHz
Parameter
Min
Variable Oscillator
Max
Min
2.4
0.009
Unit
Max
x
1/ECBT
GSC Frequency with an
External Clock
ECH
External Clock High
170
2TCLCL
+ 45ns
ns
ECL(13)
External Clock Low
170
2TCLCL
+ 45ns
ns
ECRT
External Clock Rise
Time(11)
20
20
ns
ECFT
External Clock Fall
Time(12)
20
20
ns
ECDVT
External Clock to Data
Valid Out - Transmit
(to External Clock
Negative Edge)
150
150
ECDHT
External Clock Data
Hold - Transmit
(to External Clock
Negative Edge)
Fosc
0.145
MHz
ns
ns
0
0
ECDSR
External Clock Data
Set-up - Receiver
(to External Clock
Positive Edge)
45
45
ns
ECDHR
External Clock to Data
Hold - Receiver
(to External Clock
Positive Edge)
50
50
ns
10-85
II
intaL
8XC152JAt JBtJCt JD
GSC TIMINGS (EXTERNAL CLOCK)
I'
ECBT
'I
"
)1
1
~I
EXTERNAL CLOCK
\
1
TRANSMIT DATA
X
Yo
I . - E C L - - : : - - - ECH ~ ""I_ _ _ _ _J
~
I
: - ECDVT
:X.,.--------...,..--
X
--~:
ECDHT ~
:+-
1"'1'-----ECBT----~'1
1
EXTERNAL CLOCK
~I\
1
,~
':
/,'
~I______- J
:
I
~----~
- : ECDSR '-ECDHR-:
RECEIVE DATA
:::::::::::)(:00-,------J,~::::::::::::::::::::::::::::::::
270431-1;>
NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.
3. "Typicals" are based on samples taken from early manufacturing lots and are not guaranteed. The measurements were
made with Vee = 5V at room temperature.
4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports·
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE pin may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
5. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vee specification when the address bits are stabilizing.
6. lee is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL =; 5 ns, VIL = Vss + 0.5V, VIH =
~ - 0.5V; XTAL2 N.C.; Port 0 pins connected to VeL'Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vee and GSC inactive.
7. The specifications relating to external data memory characteristics are also applicable to DMA operations.
a. Tavwx should not be confused with TaVWX as specified for aOC51BH. On aOC152, TaVWX is measured from data
valid to rising edge of WR. On aOC51 BH, TaVWX is measured from data valid to falling edge of WR. See timing diagrams.
9. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
10. All specifications relating to external program memory characteristics are applicable to:
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the aOC152JB/JD.
11. Same as TCLCH, use External Clock Drive Waveform.
12. Same as TCHCL, use External Clock Drive Waveform.
13. When using the same external clock to drive both the receiver and transmitter, the minimum ECL spec effectively
becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) requirements must also be met (150 + 45 = 195 ns). The 195 ns requirement would also increase to include the maximum
propagation delay between receivers and transmitters.
10-86
intel·
8XC152JA/JB/JC/JD
DESIGN NOTES
Within the BXC152 there exists a race condition that may set both the RDN and AE bits at the end of a valid
reception. This will not cause a problem in the application as long as the following steps are followed:
-Never give the receive error interrupt a higher priority than the valid reception interrupt
-Do not leave the valid reception interrupt service routine when AE is set by using a RETI instruction until AE
is cleared. To clear AE set the GREN bit, this enables the receiver. If the user desires that the receiver remain
disabled, clear GREN after setting it before leaving the interrupt service routine.
-If the AE bit is checked by user software in response to a valid reception interrupt, the status of AE should
be considered invalid.
The race condition is dependent upon both the temperature that the device is currently operating at and the
processing the device received during the wafer fabrication.
When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from
where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port pin or to external memory.
DATA SHEET REVISION SUMMARY
The following represent the key differences between the "-003" and the "-002" version of the
BOC152/B3C152 data sheet. Please review this summary carefully.
1. Removed minimum GSC frequency spec when used with an external clock.
2. Change figure "External Program Memory Read Cycle" to show Port O/Port 5 address floating after PSEN
goes low.
3. Added design note on terminating idle with reset.
4. Added status of PSEN during Power Down mode to Table 3.
5. Moved all notes to back of data sheet.
6. Changed microcomputer to microcontroller.
7. Added External Oscillator start-up capacitance note.
The following represent the key differences between the "-002" and the "-001" version of the BOC152/
B3C152 data sheet. Please review this summary carefully.
1. Status of data sheet changed from "ADVANCED" to "PRELIMINARY".
2. BOC152JC, B3C152JC, and BOC152JD were added.
3. Added AE/RDN design note.
4. This revision summary was added.
5. Note # 13 was added (Effective ECL spec at higher clock rates).
6. Table #2 changed to Table #3 (Status of pins during Idle/Power Down).
7. Current Table #2 was added (JA vs. JB vs. JC vs. JD matrix).
B. Transmit jitter spec changed from ± 35 ns and ± 70 ns to ± 10 ns.
10-B7
II
MCS®--51 Development
Support Tools
11
•
DEVELOPMENT TOOLS FOR THE MCS®-51
FAMILY OF MICRO CONTROLLERS
..
281424-1
CUT COSTS, NOT CORNERS
Intel supports application development for its MCS-51 family of micro controllers with a
complete set oftools. Development Tools for the MCS-51 include in-circuit emulators,
languages, and utilities.
The ICETM-511PC in circuit emulators are easy to use, powerful, and attractive in price.
A windowed user interface and source level debugging simplify use. The sophisticated
event recognition features, ability to access debug information during emulation, and
performance analysis functions provide debugging power.
The software development tools consist of a macro assembler, PL/M compiler, linker I
relocator program, librarian utility, and object-to-hex utility. C compilers for the MCS-51
architecture are available from several vendors. Develop code in the languages you
desire, then combine object modules from different languages into a single, fast program.
These tools were designed to work with each other, with the MCS-51 architecture, and
with the Intel line of MCS-51 emulators.
11-1
September 1992
Order Number: 281424'()01
FEATURES
FEATURES
Augmenting command entry is a syntax guide
and recall! editing of prior commands. Of
course, command syntaxis compatible with
prior non-windowed Intel emulators.
Help is at your fingertips. One keystroke pops
up the help menu. Help is available for a
variety of topics, including emulator
commands, window operation, function keys,
pull-down menus, and error messages. In
addition, a Key Reference Line displays a list
of the currently active function keys as well as
brief help text for menus and forms.
Software Support Tools
• ASM-51 macro assembler
• PL/M-51 high-level language
o Linker/relocator program
• Librarian Utility
• Object to hexadecimal converter
• Hosted on IBM PC XT / AT running DOS
V 3.0 or later
• Worldwide service and support
Emulator Family
• Color windowed user interface
• Source level debugging with symbolic
referencing and display
• Recognition of internal data write, external
data read/write, instruction fetch, execution
address, external input line state, and trace
buffer full events
• AND/OR combination of events
• Qualification of an event by number of
occurrences
• Arming of an event conditional on the
occurrence of another event
• Access to microcontroller contents/memory
during emulation
• 4096 frame trace buffer accessible during
emulation
• Emulation and event timers for performance
analysis
• User-definable debug and test procedures
with variables and literal definitions
• Mappable emulator memory: 64 Kbytes code
plus 64 Kbytes xdata
• On-circuit emulation of surface mounted
components
• Four input logic pins to capture external
events
• Supports component speeds up to 20 MHz
Source Level Debugging
Source level debuggillg features complement
the windowed user interface. For example,
simply use a pull-down menu to load the
program. Breakpoints are set by highlighting a
line of code within the Source Window and
pressing a function key. Set trace
specifications through the pop-up fill-in-theblank form in the Trace Window. And with the
current execution point and breakpoints
highlighted in color, press a function key to
begin emulation.
Scroll to another line in the Source Window
and press a function key to execute to that
point, bypassing yet retaining the previously
set breakpoints. From there, use a pull-down
menu to add a variable, referenced
symbolically, to the Watch Window. With each
press of another function key the program is
executed one source line at a time and the
Watch Window display is updated.
Source statements and symbolic information
are also displayed when memory is
disassembled (in the Memory Window) or
within the trace buffer (in the Trace Window).
ICETM·51IPC
For ease of use and learning, the ICE-511PC
emulators feature a windowed interface. Each
window, such as Memory, Source, Register,
and Watch (user variable display), presents a
different view of the system. A Custom
Window allows a user-defmed function. Within
each window, option menus, pop-up fill-in-theblank forms, and scroll keys control the view.
Windows may be added, sized, zoomed to full
screen,·or completely removed.
Pull down menus and function keys streamline
emulator use by providing convenient access to
common functions. The Command Line
Window provides the power user with the most
efficient access to all emulator functions.
Event Recognition and Trace
To speed the debugging process, the ICE-51/PC
user has access to sophisticated event
recognition capabilities. Internal data write,
external data read/write, instruction fetch,
execution address, external input line state,
and trace buffer full events may be used as
triggers. Compound triggers may be
constructed through AND/OR combinations of
events. The recognition of an event may be
armed based on the occurrence of another
event. Events may be further qualified by a
number of occurrences. Since this
sophistication may lead to complex break/
trace definitions, four Break Registers are
available to store definitions for reuse.
11-2
infel~
SPECIFICATIONS
The Fastbreaks feature ofthe ICE-51/PC
emulators allows the user to execute emulator
commands with minimal intrusion on
emulation. Fastbreaks are typically used for
accesses to microcontroller contents or
memory. A Fastbreak halts emulation,
performs the requested memory access,
resumes emulation, and reports back to the
user. Emulation is halted only for the few
machine cycles necessary to perform the
access.
Similarly, the trace buffer is accessible during
emulation. The buffer produces 4096 frames of
execution address, opcode in hex and
mnemonic formats, operands in hex and
symbolic formats, bus activity, external line
(clips) states, and source code.
To aid performance analysis, an event timer
records the time from/to specified events while
an emulation timer records the total duration
of emulation.
Genuine Intel Tools
The ICE-51/PC provides the most
comprehensive support for the Intel MCS-51
family of microcontrollers. When you trust
your component selection to Intel, why trust
its emulation to someone else? And the
ICE-51/PC emulators work better because they
work together with products such as C
compilers, from leading independent software
vendors as well as Intel's own software tools.
Emulator Electrical
Characteristics
The AC characteristics for all pins except PO,
P2, ALE, and PSEN # are maintained with a
maximum capacitive target load 15 pF less
than specified in the component data sheet for
the 8xC51GB.
The AC timing degradations for PO, P2, ALE,
and PSEN # are maintained with a maximum
capacitive target load of70 pF.
The maximum rise and fall times for ALE and
PSEN # with a target load of 20 pF are 7 ns
and 2 ns respectively.
The maximum rise and fall times for PO and
P2 with a target load of 50 pF are 27 ns and
10 ns respectively. Rise and fall times are
specified at the 10% and 90% points.
The emulation processor requires 2 to 3 clock
cycles longer to respond to reset.
For external program memory characteristics
involving RD# and WR#, observe the
following degradations:
• Setup time to RD# is 11 ns longer (max.).
• It takes 30 ns longer for data to appear on
the bus with respect to WR# (max.).
• The falling edges of RD # and WR # can be
delayed by 70 ns (max.).
Table C-1 shows the characteristics for
external program memory.
Table C-1. External Program Memory Characteristics
Symbol
Parameter
TAVLL
Address Valid to ALE Low
TLLAX
Address Hold after ALE Low
TLLIV
ALE Low to Valid Instruction In
Minimum
Maximum
0.85 TCLCL - 19
ns
10
ns
3.15 TCLCL - 18
TLLPL
ALE Low to PSEN # Low
TpLIV
.PSEN # Low to Valid Instruction In
TpXIZ
Input Instr Float after PSEN #
TpXAV
PSEN # to Address Valid
TAVIV
Address to Valid Instruction In
TpLAZ
PSEN # Low to Address Float
TLLDV
TAVDV
Units
ns
0.85 TCLCL - 1
TCLCL
ns
2.15 TCLCL - 18
ns
24
ns
+ 20
ns
4.15 TCLCL - 66
ns
4
ns
ALE Low to Valid Data In
7.15 TCLCL - 18
ns
Address to Valid Data In
8.15 TCLCL - 66
ns
Note: ;; mdlCates active-low lOgIc.
11-3
a
SPECIFICATIONS
PROCESSOR MOOULE
PIN 1
TOPYIEW
CONTROLLER POD CONNECTOR
}
[
If o .· - - - - - - - - - - - -CABLEB~O;'DY~---------------------------zLE~----------~
- 36"-------------i---3.25"------j
SIDE VIEW
TARGET
ADAPTOR
PROCESSOR MODULE
b!f~
281424-2
Note: Processor module dimensions will vary for the ICE-51FX/PC.
Figure 1: Processor Module Dimensions
Create and
C Compiler
(Other Vendors):
Ic~
I
2B1424-3
Figure 2: MCS®-51 Application Development Process
11-4
int'el.
SPECIFICATIONS
ASM·51 Macro Assembler
segments. Modules can be written in either
ASM-51 or PL/M-51.
The ASM-51 Macro Assembler provides full
and accurate support for the MCS-51 family of
microcontrollers. Symbolic access to the many
features of the component, an "include" me
with appropriate c9mponent registers, and
memory space definition are a few of the
features of the assembler. With the macro
facility of ASM-51 common code sequences
need only be developed once, saving time in
both development and maintenance.
LIB·51
The Intel LIB-51 utility creates and maintains
libraries of software object modules. Standard
modules can be placed in a library and linked
to your application programs using RL-51.
When using libraries, the linker will link only
those modules that are required to satisfy
external references.
PLIM·51 Compiler
PL/M-51 is a high-level language designed to
support the software requirements of the
MCS-51 family of microcontrollers. The
PL/M-51 compiler translates PL/M high-level
language statements into MCS-51 relocatable
object code. Major features of the PLlM-51
compiler include:
• Structured programming for ease of
maintenance and enhancement. The
PL/M-51 language supports modular and
structured programming, making programs
easier to understand, maintain, and debug.
• Data types to facilitate a variety of common
functions. PL/M-51 supports three data
types to facilitate various arithmetic,logic,
and address functions. The language also
uses BASED variables that map more than
one variable to the same memory location to
save memory space.
• Interrupt attribute to speed coding effort.
The INTERRUPT attribute allows you to
easily define interrupt handling procedures.
The compiler will generate code to save and
restore the program status word for
INTERRUPT procedures.
• Code optimization for minimizing memory
requirements. The PL/M-51 compiler has
four different levels of optimization for
significantly reducing the size of programs.
• Language compatibility for faster
development. PL/M-51 object modules are
compatible with object modules generated by
all other MCS-51 language translators. This
compatibility allows for easy linking of all
modules and the ability to do symbolic
debugging with the Intel MCS-51 In-Circuit
Emulators.
RL·51 LinkerlRelocator
Intel's RL-51 utility is used to link multiple
MCS-51 object modules into a single program,
resolve all references between modules and
assign absolute addresses to all relocatable
OB Object to Bexidecimal
Converter
The OH utility converts Intel OMF-51 object
modules into standard hexidecimal format.
This allows the code to be loaded directly into
PROM via non-Intel PROM programmers.
Third Party Vendor Tools for
MCS®·51
The MCS-51 architecture is supported by a
growing number of vendors providing C
language compilers. The following vendors
provide C language compilers for the Intel
MCS-51 Architecture.
Archimedes Software, Inc 415-567-4010 (U.S.)
RSO Tasking 617-894-7800 (U .S.),
31-33-55-8584 (Europe)
Franklin Software, Inc 408-296-8051 (U.S.)
IAR 46-18-15-7920 (Europe)
Microtec Research, Inc 408-980-1300 (U.S.)
Worldwide Service, Support, and
Training
To augment its development tools, Intel offers
field application engineering expertise and
hotline technical support.
Intel also offers a Software Support Contract
which includes technical software information,
automatic distributions of software and
documentation updates, iCOMMENTS
publication, remote diagnostic software, and a
development tools troubleshooting guide.
Intel's 90-day Hardware Support package
includes technical hardware information,
telephone support, warranty on parts,labor,
material, and on-site hardware support.
Intel Development Tools also offers a 30-day,
money-back guarantee to customers who are
not satisfied after purchasing any Intel
development tool.
11-5
III
SPECIFICATIONS
Configuration and Ordering
Information
form factor), 36" cable (connects
controller to probe), and target
probe fitted with a 68-lead male
PLCC adapter. Supports
87C51GB components (MCS-51
microcontrollers with on'chip
The ICE-511PC emulator utilizes an IBM PC
XT, PC AT, or compatible personal computer
with hard disk drive, 640 Kbytes of memory,
and DOS 3.3 or 5.0 as the host system.
Emulator host software is provided on both
5.25 and 3.5 inch flexible disk media.
The ICE-51/PC emulators utilize a common
emulation controller card with
interchangeable target interface boards (TIB).
An ICE-5IFX/PC may be converted to support
the 87C51GB microcontroller by installing a
probe kit. Likewise, an ICE-51GX/PC may be
converted to an ICE-51FX/PC by installing a
probe kit.
A Crystal Power Accessory (CPA) is optionally
available for testing the TIB to target system
connection. Standalone software execution
does not require a CPA.
AID).
Note:· 1. PC host software is delivered on 5 '/." (360 KB) and
3 'j,. (720 KB) diskettes
2. Emulator kits do NOT include a CPA (Crystal Power
Accessory)
pICE51FXCPA
pICE5IGXCPA
Upgrade Kits
Emulator Kits
pICE51FXPC ICE-51FX/PC emulator kit.
Contains all required emulator
hardware and software to
execute stand-alone or in-target.
Kit includes emulation
controller board (8-bit, PC-card
form factor), 36" cable (connects
controller to probe), target
probe fitted with a 40-pin male
DIP adapter, and a 44-lead
PLCC target adapter. Supports
the following components:
1) 8031
2)8031AH
3)8032AH
4) 8051
5)8051AH
6)8051AHP
7)8052AH
8)80C3IBH
9) 8OC3IBH-1
10) 80C3IBH-2
11) 80C32
12)8OC5IBH
13) 8OC5IBH-1
14) 8OC51BH-2
15) 80C5IBHP
16) 80C51FA
17) 8OC52
18) 83C51FA
19) 83C51FB
20) 875IBH
21) 8751H
22) 8751H-8
Crystal Power Accessory
for ICE-51FX/PC (used to
run confidence tests on
probe's pin circuitry)
Crystal Power Accessory
for ICE-51GX/PC (used to
run confidence tests on
probe's pin circuitry)
23) 8752BH
24) 87C51
25) 87C51-1
26) 87C51-2
27) 87C51FA
28) 87C51FB
29) 87C51FC
pICE51GXPC ICE-51GX/PC emulator kit.
Contains all required emulator
hardware and software to
execute stand-alone or in-target.
Kit includes emulation
controller board (8-bit, PC-card
pICE51FXPROBE Conversion kit for existing
ICE-51GX/PC emulators
(kit includes FX target
probe and PC host
software)
pICE51GXPROBE Conversion kit for existing
ICE-51FX/PC emulators
(kit includes GX target
probe and PC host
software)
Target Adapter
HADPTONC44PLCC target: 44-lead PLCC
components (surfacemounted)
Software Tools
D86PLM51NL DOS-hosted PL/M crosscompiler. Language features
allow direct architecture
access. Optimized for real-time,
embedded applications.
D86ASM5INL DOS-hosted macro assembler.
Supports all MCS-51
components.
Note: All software tool packages include a relocatorllinker
(RL-51), an object-to-hex converter (OH), and a
librarian (LIB-51).
11-6
ACE51TMFx SOFrWARE
To order ACE51 TMFx
Software, contact
your local
Intel Sales Office.
270865-1
ACE51 TMFx SOFTWARE MAKES YOU AN
ARCHITECTURAL WIZ~INSTANTLY
If you want to learn 80C51Fx architecture as fast as possible, so that you can develop
hardware and software in parallel, Intel has the perfect solution. We call it ACE51 TMFx
Software..
PC-BASED SOFTWARE TRAINING SPEEDS LEARNING
ACE51 TMFx Software is a PC-Based Expert System that uses artificial intelligence
technology to guide you through detailed product training.
Its menu-driven software is designed to speed up your learning curve--and reduce your
total design time, no matter what level of MCS-51 experience you have. ACE51 TMFx
software includes:
• A Hypertext Manual
• Peripheral Design Modules
• Application Development Modules
It uses "Hypertext" to efficiently present 80C51Fx documentation by providing
highlighted links to related topics. You can follow these links several layers into the
documentation-without having to search through hundreds of cross-referenced pages.
CONCENTRATE ON APPLICATIONS INSTEAD
OF BIT-BY-BIT PROGRAMMING
After learning the basics of the architecture, you can use the ACE51 TMFx design module
to program peripherals. So, you can concentrate on application needs versus bit-by-bit
programming materials. You'll save design time and minimize programming errors.
Also, ACE51TMFx Software generates fully commented initialization code and features
scoreboards to document just how each peripheral has been programmed. The application
development modules provide examples of generating customized code for the
Programmable Counter Array (PCA). Application examples include High-Speed Outputs,
Software Timers, and measurement of frequency, duty cycle, pulse width and phase
differences.
System requirements: IBM compatible XTor AT··, EGA Monitor, hard disk, 1.2 meg
floppy drive, 640K memory.
'IBM PC, XT, AT and DOS are registered trademarks of International Business Machines Corporation.
11-7
March 1991
Order Number: 270865-002
a
EV80C51FX EVALUATION BOARD
270972·1
LOW COST CODE EVALUA TION TOOL
Intel's EVaOC51FX evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
aOC51FC, single chip, CHMOS', a-bit microcontrollers, the newest member of the
industry standard a051 family. The board allows the user to take full advantage of the
power of the a051. The EVaOC51FX provides up to 16 MHz execution of a user's code.
Plus, its memory (ROMsim) can be reconfigured to match the user's planned memory
system, allowing for exact analysis of code execution speeds in a particular application.
Popular features such as a single line assembler/disassembler, single-step program
execution and sixteen software breakpoints are standard on the EVaOC51FX. Intel
. provides a complete code development environment using assembly language (ASM-51)
as well as Intel's high-level language PLlM-51 to accelerate development schedules.
The evaluation board is hosted on an IBM PC" or BIOS-compatible clone, already a
standard development solution in most of today's engineering environments. The source
code for the on-board monitor (written in ASM-51) is public domain. The program is about
3 Kbytes and can be easily modified to be included in the user's target hardware. In this
way, the provided PC host software can be used throughout the development phase.
EV80C51FX FEATURES
•
•
•
•
•
Up to 16 MHz Execution Speed
32 Kbytes of ROMsim
Flexible Chip-Select Controller
Totally CMOS, Low Power Board
Concurrent Interrogation of Memory and
Registers
•
•
•
•
•
Sixteen Software Breakpoints
Program Step Mode
High-Level Language Support
Single Line Assembler/Disassembler
RS-232-C Communication Link
'CHMOS is patented Intel process.
··IBM PC~, XT, AT and DOS are registered trademarks of International BUB2ness Machines Corporation.
11-8
August 1991
Order Number: 270972·001
EV80C51FX EVALUATION BOARD
FULL SPEED EXECUTION
The EV80C51FX executes the user's code from
on-board ROMsim at up to 16 MHz. By
changing crystals on the 8OC51FC, any slower
execution speed can be evaluated. The board's
host interface timing is not affected by this
crystal change.
.
32 KBYTES OF ROMSIM
The board comes with 32 Kbytes of SRAM to
be used as ROMsim for the user's code and as
data memory if needed.
FLEXIBLE MEMORY
DECODING
or a breakpoint is reached, the user's code is
restored in the ROMsim.
PROGRAM STEP MODE
The stepping mode redirects the external
interrupt 1 vector for use by the monitor. All
other interrupts are available to the user, and
will function as normal.
mGH-LEVELLANGUAGE
SUPPORT
The host software for the EV80C51FX board is
able to load absolute object code generated by
ASM-51, PL/M-51 or RL-51, all of which are
available from Intel.
By changing the Programmable Logic Device
(PLD) on the board, the memory on the board
can be made to look like the memory system
planned for the user's hardware application.
The PLD controls the chip-select inputs on the
board with 128 byte boundaries of resolution.
SINGLE LINE
ASSEMBLER/DISASSEMBLER
TOTALLY CMOS BOARD
RS-232-C
COMMUNICATION LINK
The EV80C51FX board is built totally with
CMOS components. Its power consumption is
therefore very low, requiring 5V at only
225 mAo If the on board LEDs are disabled, the
current drops to only 80 mAo The board also
requires ± 12V at 10 mAo
CONCURRENT
INTERROGATION
OF MEMORY AND REGISTERS'
The monitor for the EV80C51FX allows the
user to read and modify internal registers and
external memory :while the user's code is
running in the board.
SIXTEEN SOFTWARE
BREAKPOINTS
There are sixteen breakpoints available which
automatically substitute an LCALL
instruction for a user's instruction at the
breakpoint location. The substitution occurs
when execution is started. If the code is halted
The host has a Single Line Assembler, and a
Disassembler, to simplify modification and
examination of code loaded on the board.
The EV80C51FX communicates with the host
using an Intel 82510 UART provided on board.
This frees the on-chip UART of the 80C51FC;
or for the user's application.
PERSONAL COMPUTER
REQUmEMENTS
The EV80C51FX Evaluation Board is hosted
on an IBM PC··, XT··, AT'· or BIOS
compatible clone. The PC must meet the
following minimum requirements.
• 512 Kbytes of Memory
• One 360 Kbyte floppy Disk Drive
• PC DOS'· 3.1 or Later
• A Serial Port (COM1 or COM2) at 9.600 Baud
• ASM-51 or PL/M-51
• A text editor such as AEDIT
11-9
infel·
EV80C51FXEVALUATION BOARD
1111
I
~~
On-Chip
Serial
Pan
8OC51FX
CPU
CHIP
SELECT
and
MEMORY
MAP LOGIC;:
.I
32Kx8
DATA
-
I
ADDRESS
RAM
Dr
DIGITAL
110
~
CONTROL
EPROM
MEMORY
I
II
I
32Kx8
RAM
Dr
EPROM
MEMORY
EXTERNAL
UART
f~
270972-2
11-10
EV80C51GX EVALUATION BOARD
270974-1
LOW COST CODE EVALUATION TOOL
Intel's EV8OC51GX evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C51GB, single chip, CHMOS', 8-bit microcontrollers, the newest member ofthe
industry standard 8051 family. The board allows the user to take full advantage of the
power of the 8051. The EV80C51GX provides up to 16 MHz execution of a user's code.
Plus, its memory (ROMsim) can be reconfigured to match the user's planned memory
system, allowing for exact analysis of code execution speeds in a particular application.
Popular features such as a single line asembler/disassembler, single-step program
execution and sixteen software breakpoints are standard on the EV80C51GX. Intel
provides a complete code development environment using assembly language (ASM-51)
as well as Intel's high-level language PLlM-51 to accelerate develpment schedules.
The evaluation board is hosted on an IBM PC" or BIOS-compatible clone, already a
standard development solution in most oftoday's engineering environments. The source
code for the on-board monitor (written in ASM-51) is public domain. The program is about
3 Kbytes and can be easily modified to be included in the user's target hardware. In this
way, the provided PC host software can be used throughout the development phase.
EV80C51GX FEATURES
•
•
•
•
•
Up to 16 MHz Execution Speed
32 Kbytes of ROMsim
Flexible Chip-Select Controller
Totally CMOS, Low Power Board
Concurrent Interrogation of Memory and
Registers
•
•
•
•
•
Sixteen Software Breakpoints
Program Step Mode
High-Level Language Support
Single Line Assembler/Disassembler
RS-232-C Communication Link
'CHMOS is a patented Intel process.
"IBMI5 PC, XT. AT and DOS are registered trademarks of Intemational Business Machines Corporation.
11-11
June 1991
Order Number: 270974-001
intet
EV80C51GX EVALUATION BOARD
FULL SPEED EXECUTION
The EV80C51GX executes the user's code from
on-board ROMsim at up to 16 MHz. By
changing crystals on the 80C51GB any slower
execution speed can be evaluated. The board's
host interface timing is not affected by this
crystal change.
32 KBYTES ofROMSIM
or a breakpoint is reached, the user's code is
restored in the ROMsim.
PROGRAM STEP MODE
The stepping mode redirects the external
interrupt 1 vector for use by the monitor. All
other interrupts are available to the user, and
will function as normal.
HIGH-LEVEL LANGUAGE
SUPPORT
The board comes with 32 Kbytes of SRAM to
be used as ROMsim for the user's code and as
data memory if needed.
The host software for the EV80C51GX board is
able to load absolute object code generated by
ASM-51, PL/M-51 or RL-51, all of which are
available from Intel.
FLEXIBLE MEMORY
DECODING
By changing the Programmable Logic Device
(PLD) on the board, the memory on the board
can be made to look like the memory system
planned for the user's hardware application.
The PLD controls the chip-select inputs on the
board with 128 byte boundaries of resolution.
SINGLE LINE
ASSEMBLER/DISASSEMBLER
The host has a Single Line Assembler, and a
Disassembler, to simplify modification and
examination of code loaded on the board.
TOTALLY CMOS BOARD
The EV80C51GX board is built totally with
CMOS components. Its power consumption is
therefore very low, requiring 5V at only
250 mAo If the on board LEDs are disabled, the
current drops to only 80 rnA. The board also
requires ± 12V at 10 rnA.
RS-232-C
COMMUNICATION LINK
The EV80C51GX communicates with the host
using an Intel 82510 DART provided on board.
This frees the on-chip DART of the 80C51FC;
or for the user's application.
PERSONAL COMPUTER
REQUIREMENTS
CONCURRENT
INTERROGATION
OF MEMORY AND REGISTERS
The monitor for the EV80C51GX allows the
user to read and modify internal registers and
external memory while the user's code is
running in the board.
SIXTEEN SOFTWARE
BREAKPOINTS
There are sixteen breakpoints available which
automatically substitute an LCALL
instruction for a user's instruction at the
breakpoint location. The substitution occurs
when execution is started. Ifthe code is halted
The EV80C51GX Evaluation Board is hosted
on an IBM PC-', XT-': AT'- or BIOS
compatible clone. The-PC must meet the
following minimum requirements:
• 512 Kbytes of Memory
• One 360 Kbyte Floppy Disk Drive
• PC DOS-' 3.1 or Later
• A Serial Port (COM1 or COM2) at 9600 Baud
• ASM-51 or PLlM-51
• A text editor such as AEDIT
11-12
EV80C51GX EVALUATION BOARD
I.
-{)~
~
~~
ANALOG
INPUT
On-Chip
Serial
Po"
It--
CHIP
SELECT
and
MEMORY
MAP LOGIC
80C51GX
CPU
I
DATA
-
8Kx8
RAM
or
DIGITAL
VO
t--
CONTROL
I
1
ADDRESS
EPROM
MEMORY
I
8Kx8
RAM
or
EPROM
MEMORY
I
EXTERNAL
UART
f-
I--
270974-2
11-13
RUPI..44 Family
,
12
intel·
October 1988
The RUPITM_44 Family:
Microcontroller with On-Chip
Communication Controller
Order Number: 296163-001
12-1
THE RUPITM-44 FAMILY:
MICROCONTROLLER WITH
ON-CHIP COMMUNICATION
CONTROLLER
CONTENTS
PAGE
INTRODUCTION ........................ 12-3
1.0 ARCHITECTURE OVERViEW ....... 12-3
2.0 THE HDLC/SDLC PROTOCOLS .... 12-5
2.1 HOLe/SOLe Advantages over
Async .........................
2.2 HOLe/SOLe Networks ..........
2.3 Frames ..........................
2.4 Zero Bit Insertion ................
12-5
12-6
12-6
12-6
2.5 Non-Return to Zero Inverted
(NR21) ........................ 12-7
2.6 References ...................... 12-7
3.0 RUPITM·44 DESIGN SUPPORT ..... 12-7
3.1 Design Tool Support ............. 12-7
3.28051 Workshop .................. 12-8
12-2
THE RUPITM-44 FAMILY
real-time control applications such as instrumentation, I
industrial control, and intelligent computer peripherals.
The microcontroller features on-chip peripherals such
as two 16-bit timer/counters and 5 source interrupt capability with programmable priority levels. The microcontroller's high performance CPU executes most instructions in I microsecond, and can perform an 8 X 8
multiply in 4 microseconds. The CPU features a Boolean processor that can perform operations on 256 directly addressable bits. 192 bytes of on-chip data RAM can
be extended to 64K bytes externally. 4K bytes of onchip program ROM can be extended to 64K bytes externally. The CPU and SIU run concurrently. See Figure 2.
INTRODUCTION
The RUPI-44 family is designed for applications requiring local intelligence at remote nodes, and communication capability among these distributed nodes. The
RUPI-44 integrates onto a single chip Intel's highest
performance microcontroller, the 805 I-core, with an
intelligent and high performance Serial communication
controller, called the Serial Interface Unit, or SIU. See
Figure 1. This dual controller architecture allows complex control and high speed data communication functions to be realized cost effectively.
The RUPI-44 family consists of three pin compatible
parts:
• 8344-8051 Microcontroller with SIU
• 8044-An 8344 with 4K bytes of on-chip ROM program memory
• 8744-An 8344 with 4K bytes of on-chip EPROM
program memory
The SIU is designed to perform serial communications
with little or no CPU involvement. The SIU supports
data rates up to 2.4 Mbps, externally clocked, and
375 Kbps self clocked (i.e., the data clock is recovered
by an on-chip digital phase locked loop). SIU hardware
supports the HDLC/SDLC protocol: zero bit insertion/deletion, address recognition, cyclic redundancy
check, and frame number sequence check are automatically performed.
1.0 ARCHITECTURE OVERVIEW
The SIU's Auto mode greatly reduces communication
software overhead. The AUTO mode supports the
SDLC Normal Response Mode, by performing secondary station responses in hardware without any CPU
involvement. The Auto mode's interrupt control and
frame sequence numbering capability eliminates software overhead normally required in conventional systems. By using the Auto mode, the CPU is free to concentrate on real time control of the application.
The 8044's dual controller architecture enables the
RUPI to perform complex control tasks and high speed
communication in a distributed network environment.
The 8044 microcontroller is the 8051-core, and maintains complete software compatibility with it. The microcontroller contains a powerful CPU with on-chip
peripherals, making it capable of serving sophisticated
-:=-, =H ~ H ~I
r--------------------,
"·--+1--"· ca::-;~::-~ON
~--------------------~
Figure 1. RUPITM-44 Dual Controller Architecture
12-3
296163-1
_.
l
@
REFERENCE
OSCIlLATOII
!!
ce
...
C
ID
~
en
1
1
::!l
I
I
3"
-g
ID
I\J
.j,.
a.
01
.,...,..0
ID
0"
()
~
c
iii"
ce
...
DI
3
1
1
1
1
1
1
L
----------------------,
----
r
50--1
1
GR~:
TWO
~R
COUNTERS
4kBYTES
PllOO/IAM
MEMOIIY
I
I
I
2P011T
DATA RAM
1
-I
%
I
SERIAL
1051
UNIT (SIUI
BUS
PIIOGRAMMABLE
EXPANSION
-----.--
1
1
1
1
INTERFACE
CPU
----
ItO
m
:xl
c:
"U
":::j
.
~
-liIo
-liIo
ICILC/SDlC
I
I
it!
!!E
1
1
r-
-<
___________ J
INTERRUPTS
296163-2
int:el..
THE RUPITM·44 FAMILY
• EFFICIENT: Well Defined Message-Level Operation
• RELIABLE: Frame Check Sequence and Frame
Numbering
2.0 THE HOLC/SOLC PROTOCOLS
2.1 HDLe/SOLC Advantages over
Async
The SDLC reduces system complexity. HDLC/SDLC
are "data transparent" protocols. Data transparency
means that an arbitrary data stream can be sent without concern that some of the data could be mistaken for
a protocol controller. Data transparency relieves the
communication controller having to detect special
characters.
The High Level Data Link Control, HDLC, is a standard communication link control established by the International Standards Organization (ISO). SDLC is a
subset of HDLC.
HDLC and SDLC are both well recognized standard
serial protocols. The Synchronous Data Link Control,
SDLC, is an IBM standard communication protocol.
IBM originally developed SDLC to provide efficient,
reliable and simple communication between terminals
and computers.
SDLC/HDLC provides more data throughout than
Async. SDLC/HDLC runs at Message-level Operation
which transmits mUltiple bytes within the frame,
whereas Async is based on character-level operation.
Async transmits or receives a character at a time. Since
Async requires start and stop bits in every transmission, there is a considerable waste of overhead compared to SDLC/HDLC.
.
The major advantages of SDLC/HDLC over Asynchronous communications protocol (Async):
• SIMPLE: Dat~ Transparency
I
PRIMARY
,-
·1
a) Point to
~
PRIMARY
1044 CONTROLLED
SECONDARY
Poin~
I
296163-3
Half Duplex
L
J
I
t
I
1044 CONTROLLED·
SECONDARY
1044 CONTROLLED
. SECONDARY
8044 CONTROLLED
SECONDARY
296163-4
b) MultipOint, Half Duplex
~
PRIMARY
~
,
1044 CONTROLLED
SECONDARY
1044 CONTROLLED
SECONDARY
t
t
8044 CONTROLLED
SECONDARY
t--
1044 CONTROLLED
SECONDARY
296163-5
c) SDLC Loop Configuration
Figure 3. RUPITM·44 Supported Network Configurations
12-5
intet
THE RUPITM-44 FAMIL V
Oue to SOLC/HOLC's well delineated field (see Figure 4) the CPU does not have to interpret character by
character to determine control field and information
field. In the case of Async, CPU must look at each
character to interpret what it means. The practical advantage of such feature is straight forward use of OMA
for information transfer.
2.3 Frames
An HOLC/SOLC frame consists of five basic fields:
Flag, Address, Control, Oata and Error Oetection. A
frame is bounded by flags-opening and closing flags.
An address field is 8 bits wide in SOLC, extendable to 2
or more bytes in HOLC. The control field is also 8 bits
wide, extendable to two bytes in HOLC. The SOLC
data field or information field may be any number of
bytes. The HOLC data field mayor may not be on an 8
bit boundary. A powerful error detection code called
Frame Check Sequence contains the calculated CRC
(Cycle Redundancy Code) for all the bits between the
flags. See Figure 4.
In addition, SOLC/HOLC further improves Oata
throughput using implied Acknowledgement of transferred information. A station using SOLC/HOLC may
acknowledge previously received .information while
transmitting different information in the same frame.
In addition, up to 7 messages may be outstanding before an acknowledgement is required.
In HOLC and SOLC are three types of frames; an Information Frame is used to transfer data, 'a Supervisory
Frame is used for control purposes, and a Nonsequenced Frame is used for initialization and control of
the secondary stations.
The HOLC/SOLC protocol can be used to realize reliable data links. Reliable Oata transmission is ensured at
the bit level by sending a frame check sequence, cyclic
redudancy checking, within the frame. Reliable frame
transmission is ensured by sending a frame number
identification with each frame. This means that a receiver can sequentially count received frames and at
any time infer what the number of the next frame to be
received should be. More important,it provides a
means for the receiver to identify to the sender some
particular frame that it wishes to have resent because of
errors.
For a more detailed discussion of higher level protocol
functions interested readers may refer to the references
listed in Section 2.6.
2.4 Zero Bit Insertion
In data communications, it is desirable to transmit data
which can be of arbitrary content. Arbitrary data transmission requires that the data field cannot contain
characters which are defined to assist the transmission
protocol (like opening flag in HOLC/SOLC communications). This property is referred to as "data transparency" .. In HOLC/SOLC, this code transparency is
made possible by Zero Bit Insertion (ZBI).
2.2 HOLC/SOLC Networks
In both the HOLC and SOLC line protocols a (Master)
primary station controls the overall network (data link)
and issues commands to the secondary (Slave) stations.
The latter complies with instructions and responds by
sending appropriate responses. Whenever a transmitting station must end transmission prematurely, it
sends an abort character. Upon detecting an abort character, a receiving station ignores the transmission block
called a frame.
The flag has a unique bit pattern: 01111110 (7E HEX).
To eliminate the possibility of the data field containing
a 7E HEX pattern, a bit stuffing technique called Zero
Bit Insertion is used. This technique specifies that during transmission, a binary 0 be inserted by the transmitter after any succession of five contiguous binary l's.
This will ensure that no pattern of 0 1 1 1 1 1 lOis ever
transmitted between flags. On the receiving side, after
receiving the flag, the receiver hardware automatically
deletes any 0 following five consecutive l's. The 8044
performs zero bit insertion and deletion automatically.
RUPI-44 supported HOLC/SOLC network configurations are point to point (half duplex) multipoint (half
duplex), and loop. In the loop configuration the staticms themselves act as repeaters, so that long links can
be easily realized, see Figure 3.
\
OPENING
FLAG
ADDRESS
FIELD
CONTROL
FIELD
01111110
I BITS
I BITS
INFORMATION
FIELD
VARIABLE LENGTH
(ONLY IN I FRAMES)
FRAME ,CHECK
SEQUENCE (FCS)
CLOSING
FLAG
111 BITS
01111110
296163-6
Figure 4. Frame Format
12-6
infel·
THE RUPITM-44 FAMILY
2.5 Non-return to Zero Inverted (NR21)
NRZI is a method of clock and data encoding that is
well suited to the HDLC/SDLC protocol. It allows
HDLC/SDLC protocols to be used with low cost asynchronous modems. NRZI coding is done at the transmitter to enable clock recovery from the data at the
receiver terminal by using standard digital phase locked
loop (DPLL) techniques. NRZI coding specifies that
the signal condition does not change for transmitting a
I, while a 0 causes a change of state. NRZI coding
ensures that an active data line will have a transition at
least every 5-bit times (recall Zero Bit Insertion), while
contiguous O's will cause a change of state. Thus, ZBI
and NRZI encoding makes it possible for the 8044's onchip DPLL to recover a receive clock (from received
data) synchronized to the received data and at the same
time ensure data transparency.
296163-7
2.6 i:leferences
Figure 5. RUPITM-44 Development Support
Configuration Intellec® System, ICETM-44 Buffer
Box, and ICE-44 Module Plugged
into a User Prototype Board
1. IBM Synchronous Data Link Control Generol Information GA27-3093-2 File No. GENL-09.
2. Standard Network Access Protocol Specification, DATAPAC Trans-Canada Telephone System CCG111.
3. IBM 3650 Retail Store System Loop Interface OEM
Information, IBM. GA27-3098-0.
4. Guidebook to Data Communications, Training Manual, Hewlett-Packard 5955-1715.
5. "Serial Backplane Suits Multiprocessor Architectures': Mike Webb, Computer Design, July 1984, pp.
85-96.
6. ''Serial Bus Simplifies Distributed Control': P.D.
MacWilliams, Control Engineering, June 1984, pp.
101-104.
7. "Chips Support Two Local Area Networks': Bob
Dahlberg, Computer Design, May 1984, pp. 107-114.
8. "Build a VLSI-based Workstation for the Ethernet
Environment': Mike Webb, EDN, 23 February 1984,
pp. 297-307.
9. "Networking With the 8044': Young Sohn & Charles
Gopen, Digital Design, May 1984, pp. 136-137.
A primary tool is the 8044 In Circuit Emulator, called
ICE-44. See Figure 5. In conjunction with Intel's Intellec® Microprocessor Development System, the ICE-44
emulator allows hardware and software development to
proceed interactively. This approach is more effective
than the traditional method of independent hardware
and software development followed by system integration. With the ICE-44 module, prototype hardware can
be added to the system as it is designed. Software and
hardware integration occurs while the product is being
developed.
The ICE-44 emulator assists four stages of development:
1) Software Debugging
It can be operated without being connected to the
user's system before any of the user's hardware is
available. In this stage ICE-44 debugging capabilities
can be used in conjunction with the Intellec text editor and 8044 macroassembler to facilitate program
development.
2) Hardware Development
The ICE-44 module's precise emulation characteristics and full-speed program RAM make it a valuable
tool for debugging hardware, including the time-critical SDLC serial port, parallel port, and timer interfaces.
3.0 RUPITM·44 DESIGN SUPPORT
3.1 Design Tool Support
A critical design consideration is time to market. 'Intel
provides a sophisticated set of design tools to speed
hardware and software development time of 8044 based
products. These include ICE-44, ASM-51, PL/M-5I,
and EMV-44.
12-7
int:eL
THE RUPITM·44 FAMILY
3) System Integration
Integration of software .and hardware can begin
when, any functional element of the user system
hardware is connected to the 8044 socket. As each
section of the user's hardware is completed, it is added to the prototype. Thus, each section of the hardware and software is system tested in real-time operation as it becomes available.
4) System Test
When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-44 module is then used for real-time emulation of the 8044 to debug the system as a completed
unit.
The final product verification test may be performed
using the 8744 EPROM version of the 8044 microcomputer. Thus, the ICE-44 module provides the
user with the ability to debug a prototype or production system at any stage in its development.
296163-6
Figure 6. RUPI-44 iPDS Personal Development
System, EMV-44 Buffer Box, and EMV-44 Module
Plugged into a User Prototype Board
A conversion kit, ICE-44 CON, is available to upgrade
an ICE-Sl module to ICE-44.
Integration, and System Test. The iPDS's rugged portability and ease of use also make it an ideal system for
production tests and field service of your finished design. In addition, the iPDS offers EPROM programming module for the 8744, and direct communications
with the 8044-based BITBUS via an optional iSBX-344
distributed control module.
Intel's ASM-Sl Assembler supports the 8044 special
function registers and assembly program development.
PL/M-Sl provides designers with a high level language
for the 8044. Programming in PL/M can greatly reduce development time, and ensure quick time to market.
3.28051 Workshop
These tools have recently been expanded with the addition of the EMV-44CON. This conversion kit allows
you to convert an EMV-Sl into an EMV-44 emulation
vehicle. The resultant low cost emulator is designed for
use with 'an iPDS Personal Development System, which
also supports the ASM-Sl assembler and PL/M-S1. See
Figure 6.
Intel provides 80S 1 training to its customers through
the S-day 80S1 workshop. Familiarity with the 80S1
,and 8044 is achieved through a combination of lecture
and laboratory exercises.
For designers not familiar with the 80S 1, the workshop
is an effective way to become proficient with the 80S 1
architecture and capabilities.
Emulation support is similar to the ICE-44 with support for Software and Hardware Development, System
12-8
int:el.
October 1988
8044 Architecture
Order Number: 296164-001
12-9
8044 ARCHITECTURE
CONTENTS
PAGE
GENERAL ............................. 12-11
1_0 MEMORY ORGANIZATION
OVERVIEW ...................... 12-11
1.1 Special Function Registers ...... 12-11
1.2 Interrupt Control Registers ...... 12-13
2.0 MEMORY ORGANIZATION
DETAILS ......................... 12-14
2.1 Operand Addressing ............ 12-15
2.2 Register Addressing ............ 12-16
2.3 Direct Addressing ........... ; ... 12-16
3.0 RESET ............................. 12-18
4.0 RUPITM·44 FAMILY PIN
DESCRIPTION ................... 12-18
...
12·10
infel .
8044 ARCHITECTURE
GENERAL
same byte as the opcode of an instruction. Thus, a large
number of instructions are one-byte instructions.
The 8044 is based on the 80S 1 core. The 8044 replaces
the 8051's serial port with an intelligentHDLC/SDLC
controller called the Serial Interface or SIU. Thus the
differences between the two result from the 8044's increased on-chip RAM (192 bytes) and additional special function registers necessary to control the SIU.
Aside from the increased memory, the SIU itself, and
differences in 5 pins (for the serial port), the 8044 and
80S 1 are compatible.
The next higher 16 bytes of the internal RAM (locations 20H through 2FH) have individually addressable
bits. These are provided for use as software flags or for
one-bit (Boolean) processing. This bit-addressing capability is an important feature of the 8044. In addition to
the 128 individually addressable bits in RAM, twelve of
the Special Function Registers also have individually
addressable bits.
This chapter describes the differences between the 8044
and 8051. Information pertaining to the 8051 core, ego
instruction set, port operation, EPROM programming,
etc. is located in the 80S 1 sections of this manual.
A memory map is shown in Figure 2.
A block diagram of the 8044 is shown in Figure 1. The
pinpoint is shown on the inside front cover.
The Special Function Registers are as follows:
• ACC
Accumulator (A Register)
• B
B Register
• PSW
Program Status Word
SP
.Stack Pointer
DPTR
Data Pointer (consisting of DPH
AND DPL)
Port 0
• PO
Port 1
• PI
Port 2
* P2
Port 3
• P3
Interrupt Priority
• IP
Interrupt Enable
• IE
Timer/Counter Mode
TMOD
Timer/Counter Control
* TCON
Timer/Counter 0 (high byte)
THO
Timer/Counter 0 (low byte)
TLO
Timer/Counter 1 (high byte)
THI
Timer/Counter 1 (low byte)
TLI
Serial Mode
SMD
Status/Command
• STS
SendlReceive Count
* NSNR
Station Address
STAD
Transmit Buffer Start Address
TBS
TBL
Transmit Buffer Length
Transmit Control Byte
TCB
RBS
Receive Buffer Start Address
Receive Buffer Length
RBL
Received Field Length
RFL
Received Control Byte
RCB
DMA Count
DMACNT
. FIFO (three bytes)
FIFO
SIUST
SIU State Counter
Power Control
PCON
1.0 MEMORY ORGANIZATION
OVERVIEW
The 8044 maintains separate address spaces for Program Memory and Data Memory. The Program Memory can be up to· 64K bytes long, of which the lowest
4K bytes are in the on-chip ROM.
If the EA pin is held high, the 8044 executes out of
internal ROM unlwess the Program Counter exceeds
OFFFH. Fetches from locations l000H through
FFFFH are directed to external Program Memory.
If the EA pin is held low, the 8044 fetches all instructions from external Program Memory.
The Data Memory consists of 192 bytes of on-chip
RAM, plus 35 Special Function Registers, in addition
to which the device is capable of accessing up to 64K
bytes of external data memory.
The Program Memory uses 16-bit addresses. The external Data Memory can use erither 8-bit or 16-bit addresses. The internal Data Memory uses 8-bit addresses, which provide a 256-location address space. The
lower 192 addresses access the on-chip RAM. The Special Function Registers occupy various locations in the
upper 128 bytes of the same address space.
The lowest 32 bytes in the internal RAM (locations 00
through IFH) are divided into 4 banks of registers,
each bank consisting of 8 bytes. Anyone of these banks
can be selected to be the "working registers" of the
CPU, and can be accessed by a 3-bit address in the
1.1 Special ~unction Registers
The registers marked with • are both byte- and bit-addressable.
12-11
•
_.
€:
8
PSEN ALE
I
CSC
I
TilliNG
1·5.0
.---
TIMERI
COUNTERS
CPU
I
!!
10
C
RD,WR
t
PROGRAM
MEMORY
INTERRUPT
CONTROL
INT1
~
i
TO,T1
INTo
INT1
Ci1
:u
J
c:
... "m~
I}>
I\)
0'
()
1
ADI ~/I/O·
(
~
PORT
~
v-
11
I
I1
~
SIU
HARDWARE
REGISTERS
PORT
2
0
r-"
0
PORT
3
-
~
I
PORT
1
f'o-
~
:D
(')
::z::
=i
m
~P
~
c::
r'
ii
10
:D
INTERNAL
TWDPORT
DATA
RAM
ill
3
~
......
)-
:-"
(
I
51
ADDR/DATA/I/O
m
J
P3
SCLR
DATA
110
1
SlU
RTS
CTS
296164-1
intel .
8044 ARCHITECTURE
FFFF
FFFF
EXTERNAL
1000
J..
om
OFFF
1
/ \ OVERLAPPED
I '\
INTERNAL
lEA
SPACE
EXTERNAL
lEA
1)
0)
I
0000 _ _ _ _ _
01
0000
~
...
J
V
V
J
INTERNAL
DATA MEMORY
PROGRAM MEMORY
...
EXTERNAL
DATA
MEMORY
296164-2
Figure 2. RUPITM·44 Memory Map
Stack Pointer
The Stack Pointer is S bits wide. The stack can reside
anywhere in the 192 bytes of on-chip RAM. When the
8044 is reset, the stack pointer is initialized to 07H.
When executing a PUSH or a CALL, the stack pointer
is incremented before data is stored, so the stack would
begin at location OSH.
External Interrupt control bits ITO and ITI are in
TCQN.O and TCON.2, respectively. Reset leaves all
flags inactive, with ITO and ITl cleared.
All the interrupt flags can be set or cleared by software,
with the same effect as by hardware.
The Enable and Priority Control Registers are shown
below. All of these control bits are set or cleared by
software. All are cleared by reset.
1.2 Interrupt Control Registers
The Interrupt Request Flags are as listed below:
Source
Request Flag
P3.2
TCON.l
Timer 0 Overflow
TCON.5
External Interrupt 1 INTl, if ITl = 0
lEI, if ITl ;", 1
Timer 1 Overflow
TFI
Serial Interface Unit SI
8it:76543
Location
External Interrupt 0 INTO, if ITO = 0
lEO, if ITO = 1
TFO
IE: Interrupt Enable Register (blt·addressable)
P3.3
TCON.3
TCON.7
STS.4
210
IEAlxlxIESIET1 EX1 I ETO I EXO I
where:
-EA disables all interrupts. If EA = 0, no interrupt
will be acknowledged. If EA = I, each interrupt source is individually enabled or disabled
by setting or clearing its enable bit.
-ES
enables or disables the Serial Interface Unit interrupt. If ES = 0, the Serial Interface Unit
interrupt is disabled.
- ETl
12·13
enables or disables the Timer 1 Overflow inter·
rupt. If ETl = 0, the Timer 1 interrupt is
disabled.
•
intel .
• EXl
• ETO
8044 ARCHITECTURE
enables or disables External Interrupt 1. If
EXl = 0, External Interrupt 1 is disabled.
enables or disables the Timer 0 Overflow interrupt. If ETO = 0, the Timer 0 interrupt is
disabled.
all. Program Memory fetches are from external memory. The execution speed ofthe 8044 is the same regardless of whether fetches are from internal or external
Program Memory. If all program storage is on-chip,
byte location 4095 should be left vacant to prevent an
undesired prefetch from external Program Memory address 4096.
IP: Interrupt Priority Register (bit-addressable)
Bit:
7
6
5
4
3
2
X
X
X
PS
PT1
PX1
Certain locations in Program Memory are reserved for
specific programs. Locations 0000 through 0002 are reserved for the initialization program. Following reset,
the CPU always begins execution at location 0000. Locations 0003 through 0042 are reserved for the five interrupt-request service programs. Each resource that
can request an interrupt requires that its service program be stored at its reserved location.
0
PTO
PXO
where:
• PS
defines the Serial Interface Unit interrupt priority level. PS = 1 programs it to the higher
priority level.
• PTl defines the Timer I interrupt priority level.
PTl = I programs it to the higher priority
level.
• PXI defines the External Interrupt priority level.
PXI = I programs it to the higher priority
level.
• PTO defines the Timer 0 interrupt priority level.
PTO = I programs it to the higher priority
level.
• PXO defines the External Interrupt 0 priority level.
PXO = I programs it to the higher priority
level.
The 64K-byte External Data Memory address space is
automatically accessed when the MOVX instruction is
executed.
.
Functionally the Internal Data Memory is the most
flexible of the address spaces. The Internal Data Memory space is subdivided into a 256-byte Internal Data
RAM address space and a 128-byte Special Function
Regist~r address space as shown in Figure 3.
SPECIAL
FUNCTION
REGISTERS
~
m 255
248 FlH
FOH
EIH
EOH
DIH
2.0 MEMORY ORGANIZATION
DETAILS
RAM
DOH
C8H
~iii
D
In the 8044 family the memory is organized over three
address spaces and the program counter. The memory
spaces shown in Figure 2 are the:
• 64K-byte Program Memory address space
• 64K-byte External Data Memory address space
• 320-byte Internal Data Memory address space
COH
BaH
80H
ADDRESSABLE
BITS IN
SFRo
(121 BlTSI
AIH
AOH
18H
IOH
~ 135
88H
121 IOH
12T
The 16-bit Program Counter register provides the 8044
with its 64K addressing capabilities. The Program
Counter allows the user to execute calls and branches
to any location within the Program Memory space.
There are no instructions that permit program execution to move from the Program Memory space to any
of the data memory spaces.
ADDRESSABLE
BITS IN
!! i:=-"""(
SFRo
32 7
0
- R7
24 RO BANK3
(128 BITSI
127
REGISTERS
R7 BANK2
!! I!!R!!-7----l
8 RO BANK1
-
In the 8044 and 8744 the lower 4K of the 64K Program
Memory address space is filled by inteni.al ROM and
EPROM, respectively. By tying the EA pin high, the
processor can be forced to fetch from the. internal
ROMJEPROM for Program Memory addresses 0
through 4K. Bus expansion for accessing Program
Memory beyond 4K is automatic since external instruction fetches occur automatically when the Program
Counter increases above 4095. If the EA pin is tied low
12-14
120
...!!.
R7 BANKO
0
INTERNAL
DATA RAM
SPECIAL FUNCTlON
REGISTERS
296164-3
Figure 3. Internal Data Memory Address Space
8044 ARCHITECTURE
The Internal Data RAM address space is 0 to 255.
Four 8-Register Banks occupy locations 0 through 31.
The stack can be located anywhere in the Internal Data
RAM address space. In addition, 128 bit locations of
the on-chip RAM are ·accessible through Direct Addressing. These bits reside in Internal Data RAM at
byte locations 32 through 47. Currently locations 0
through 191 of the Internal Data RAM address space
are filled with on-chip RAM.
The stack depth is limited only by the available Internal
Data RAM, thanks to an 8-bit reloadable Stack Pointer. The stack is used for storing the Program Counter
during subroutine calls and may be used for passing
parameters. Any byte of Internal Data RAM or Special
Function Register accessible though Direct Addressing
can be pushed/popped.
The Special Function Register address space is 128 to
255. All registers except the Program Counter and the
four 8-Register Banks reside here. Memory mapping
the Special Function Registers allows them to be accessed as easily as internal RAM. As such, they can be
operated on by most instructions. In the overlapping
memory space (address 128-191), indirect addressing is
used to access RAM, and direct addressing is used to
access the SFR's. The SFR's at addresses 192-255 are
also accessed using direct addressing. The Special
Function Registers are listed in Figure 4. Their mapping in the Special Function Register address space is
shown in Figures 5 and 6.
Performing a read from a location of the Internal Data
memory where neither a byte of Internal Data RAM
(Le., RAM addresses 192-255) nor a Special Function
Register exists will access data of indeterminable value.
Architecturally, each memory space is a linear sequence of 8-bit wide bytes. By Intel convention the
storage of multi-byte address and data operands in program and data memories is the least significant byte at
the low-order address and the most significant byte at
the high-order address. Within byte X, the most significant bit is represented by X.7 while the least significant
bit is X.O. Any deviation from these conventions will be
explicitly stated in the text.
2.1 Operand Addressing
There are five methods of addressing source operands.
They are Register Addressing, Direct Addressing,
Register-Indirect Addressing, Immediate Addressing
ARITHMETIC REGISTERS:
Accumulator', B register',
Program Status Word'
POINTERS:
Stack Pointer, Data Pointer (high & low)
PARALLEL I/O PORTS:
Port 3', Port 2*, Port 1", Port O'
INTERRUPT SYSTEM:
Interrupt Priority Control',
Interrupt Enable Control'
TIMERS:
Timer Mode, Timer Control', Timer 1
(high & low), Timer 0 (high & low)
SERIAL INTERFACE UNIT:
Transmit Buffer Start,
Transmit Buffer Length,
Transmit Control Byte,
Send Count Receive Count',
DMA Count,
Station Address
Receive Field Length
Receive Buffer Start
Receive Buffer Length
Receive Control Byte,
Serial Mode,
Status Register.'
ARITHMETIC REGISTERS:
Accumulator", B register",
.Program Status Word"
POINTERS:
Stack Pointer, Data Pointer (high & low)
PARALLEL I/O PORTS:
Port 3', Port 2', Port 1', Port O'
INTERRUPT SYSTEM:
Interrupt Priority Control',
Interrupt Enable Control'
TIMERS:
Timer Mode, Timer Control', Timer 1
(high & low), Timer 0 (high & low)
SERIAL INTERFACE UNIT:
Serial Mode, Status/Command',
SendlReceive Count', Station Address,
Transmit Buffer Start Address,
Transmit Buffer Length,
Transmit Control Byte,
Receive Buffer Start Address,
Receive Buffer Length,
Receive Field Length,
Receive Control Byte,
DMA Count,
FIFO (three bytes),
SIU Controller State Counter
'Bits in these registers are bit addressable.
OBits in these registers are bit-addressable.
Figure 4. Special Function Registers
Figure 5. Mapping of Special Function Registers
12-15
•
8044 ARCHITECTURE
and Base-Register-plus Index-Register-Indirect Addressing. The first three of these methods can also be
used to address a destination operand. Since operations
in the 8044 require 0 (NOP only), 1,2,3 or 4 operands,
these five addressing methods are used in combinations
to provide the 8044 with its 21 addressing modes.
Most instructions have a "destination, source" field
that specifies the data type, addressing methods and
operands involved. For operations other than moves,
the destination operand is also a source operand. For
example, in "subtract-with-borrow A, # 5" the A register receives the result of the value in register A minus 5;
minus C.
Most operations involve operands that are located in
Internal Data Memory. The selection of the Program
Memory space or External Data Memory space for a
second operand is determined by the operation mnemonic unless it is an immediate operand. The subset of
the Internal Data Memory being addressed is determined by the addressing method and address value. For
example, the Special Function Registers can be accessed only through Direct Addressing with an address
of 128-255. A summary of the operand addressing
methods is shown in Figure 6. The following paragraphs describe the five addressing methods.
REGISTER NAMES
SYMBOLIC
ADDRESS
2.2 Register Addressing
Register Addressing permits access to the eight registers (R7-RO) of the selected Register Bank (RB). One of
the four 8-Register Banks is selected by a two-bit field
in the PSW. The registers may also be accessed through
Direct Addressing and Register-Indirect Addrrssing,
since the four Register Banks are mapped into the lowest 32 bytes of internal Data RAM as shown in Figures
9 and 10. Other Internal Data Memory locations that
are addressed as registers are A, B, C, AB and DPTR.
2.3 Direct Addressing
Direct Addressing provides the only means of accessing
the memory-mapped byte-wide Special Function Registers and memory mapped bits within the Special Function Registers and Internal Data RAM. Direct Addressing of bytes may also be used to access the lower
128 bytes ofInternai Data RAM. Direct Addressing of
bits gains access to a128 bit subset of the Special Function Registers as shown in Figures 5, 6, 9, and 10.
BIT ADDRESS
BYTE
ADDRESS
~
B REGISTER
ACCUMULATOR
'THREE BYTE FIFO
TRANSMIT BUFFER START
TRANSMIT BUFFER LENGTH
TRANSMIT CONTROL BYTE
'SIU STATE COUNTER
SEND COUNT RECEIVE COUNT
PROGRAM STATUS WORD
'DMACOUNT
STATION ADDRESS
RECEIVE FIELD LENGTH
RECEIVE BUFFER START
RECEIVE BUFFER LENGTH
RECEIVE CONTROL BYTE
SERIAL MODE
. STATUS REGISTER
INTERRUPT PRIORITY CONTROL
PORT 3
INTERRUPT ENABLE CONTROL
PORT 2
PORT 1
TIMER HIGH 1
TIMER HIGH 0
TIMER LOW 1
TIMER LOW 0
TIMER MODE
TIMER CONTROL
DATA POINTER HIGH
DATA POINTER LOW
STACK POINTER
PORTO
240
224
223
222
221
220
219
21B
217
21B
B
ACC
FIFO
FIFO
FIFO
TBS
TBL
TCB
SIUST
NSNR
PSW
DMACNT
STAD
RFL
RBS
RBL
RCB
SMD
STS
IP
P3
IE
P2
Pl
THl
THO
TLl
TLO
TMOD
TCON
DPH
DPL
SP
PO
208
207
208
205
204
203
202
201
200
184
178
188
180
144
141
140
138
138
137
138
131
130
129
128
(FOH)
(EOH)
(DFH)
(DEH)
(DDH)
(DCH)
(DBH)
(DAH)
(DBH)
(DBH)
(DOH)
(CFH)
(CEH)
(CDH)
(CCH)
(CBH)
(CAH)
(ceH)
(CBH)
(88H)
(80H)
(ABH)
(AOH)
(90H)
(8DH)
(BCH)
(8BH)
(8AH)
(89H)
(88H)
(83H)
(82H)
(81 H)
(80H)
SFR'. CONTAINING
DIRECT ADDRESSABLE BITS
296164-4
Figure 6, Mapping of Special Function Registers
12-16
8044 ARCHITECTURE
Register
(LSB) Symbol
240
F7
I F6 I F5 I
F4
I
F3
224
E7
I E6 I
E4
I
E3.1 E2
NS2 NSI
216
DF
D7
E5
AC
FO
RSI
RSO
I D6 I D5 I D4 I
RE
RTS
CF
I CE
1 CO
51
176
B7
I
Fl
I
L El L EO
D9
I
CPB
AM
CB
PXl
PTa
BB
I BA I
B9
I
B3
I
Bl
I
B4
I
E5
ETt
CA
B2
NSNR
I
I
EXI
C9
DO
PSW
RBP
PTt
I
I
C8
STS
PXO
ETa
B8
lP
BO
P3
EXO
168
AF
I - I - I
I
AB
I
AA
I
A8
IE
160
A7
I A6 I AS I A4 I
A3
I
A2
I AI I AO
P2
97
I
93
I
92
I
PI
144
TFI
96
I
TRI
95
AC
I
TFO
94
I
TRO
lEI
A9
91
I
I
lEO
ITI
90
8F
I 8E I 8D I 8C I
8B
I
8A
I
89
I
88
TCON
128
87
I
83
I
82
I
81
I
80
PO
I
85
I
84
I
• Immediate Addressing
- Program Memory (in-code constant)
• Base-Register-plus Index-Regjster-Indirect Addressing
Program Memory (@ DPTR + A, @ PC + A)
ITO
136
86
• Direct Addressing
Lower 128 bytes of Internal Data RAM
Special Function Registers
128 bits in subset of Special Function Register
address space
• Register-Indirect Addressing
Internal Data RAM [@Rl, @RO, @SP (PUSH
and POP only)]
Least Significant Nibbles in Internal Data
RAM (@Rl, @RO)
External Data Memory (@Rl, @RO, @DPTR)
ACC
P
PS
I B6 I B5 I
D8
I D2 I Dl I
D3
8
NRO SER
Lcc I
EA
Fa
OV
BV
- I - I - I BC I
184
F2
NSO SES NR2 NRI
TBF
200
I
I
I DE I DD I DC I DB I DA I
CY
204
• Register Addressing
- R7-RO
- A, B, C (bit), AB (two bytes), DPTR (double
byte)
Hardware
BilAddress
Direct
Byte
Address (MSB)
Figure 8. Operand Addressing Methods
Figure 7. Special Function Register Bit Address
SPECIAL
FUNCTION
REGISTERS
.AM
BYTE
.FH
,MSI,
I
7E
2EH
'DH
,.H
2AH
HH
''"
27H
....
7D
"
10
SF
5E
os
so
"
50
"
"
..
OE
"H
22H
"H
20H
"H
7e
7.
"
"
'"..
5e
OA
5.
..
53
•D
.e
"
5A
"
'D
27
....
"
01
..
"
,e
,." "
70
os
50
INDIREC ,
'DDRES.[G~
'A
,e
22
'D
.. ..
.e
os
..
oe
.
OA
"
01
00
8.nll. 2
IOH
B.nkl
'27
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.~ DIRECTADDREIIING
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STACIC-POINTER REGISTER·INDIRECT AND
REGISTER·INDIRECT ADDRE~ING
B.nkO
OOH
296164-6
296164-5
Figure 10. Addressing Operands
in Internal Data Memory
FIgure 9. RAM Bit Address
12-17
II
infel·
8044 ARCHITECTURE
Register-Indirect Addressing using the content of Rl
or RO in the selected Register Bank, or using the content of the Stack Pointer (pUSH and POP only), addresses the Internal Data RAM. Register-Indirect Addressing is also used for accessing the External Data
Memory. In this case, either Rl or RO in the selected
Register Bank may be used for accessing locations
within a 2S6-byte block. The block number can be preselected by the contents of a port. The 16-bit Data
Pointer may be used for accessing any location within
the full 64K external address space.
3.0 RESET
Reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods) while
the oscillator is running. The CPU responds by executing an internal reset. It also configures the ALE and
PSEN pins as inputs. (They are quasi-bidirectiorial.)
The internal reset is executed during the second cycle in
which RST is high and is repeated every cycle until
RST goes low. It leaves the internal registers as follows:
Register
PC
A
B
PSW
SP
DPTR
PO-P3
IP
IE
TMOD
TCON
THO
TlO
TH1
Tl1
SMD
STS
NSNR
STAD
Content
OOOOH
OOH
OOH
·OOH
07H
OOOOH
OFFH
(XXXOOOOO)
(OXXOOOOO)
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
TBS
TBl
TCB
RBS
RBl
RFl
RCB
DMACNT
FIF01
FIF02
FIF03
SIUST
PCON
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
01H
(OXXXXXXX)
The internal RAM is not affected by reset. When VCC
is turned on, the RAM content is indeterminate unless
VPD was applied prior to VCC being turned off (see
Power Down Operation.)
4.0 RUPITM·44 FAMILY PIN
DESCRIPTION
VSS: Circuit ground potential.
VCC: Supply voltage during programming (of the
8744), verification (of the 8044 or 8744), and normal
operation.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. It is also the multiplexed low-order address and
data bus during accessses to external memory (during
which accesses it activates internal pullups). It also outputs instruction bytes during program verification. (External pullups are required during program verification.) Port 0 can sink eight LS TTL inputs.
Port 1: Port 1 is an 8-bit bidirectional· I/O port with
internal pullups. It receives the low-order address byte
during program verification in the 8044 or 8744. Port 1
can sink/source four LS TTL inputs, It can drive MOS
inputs without external pullups.
.
Two of the Port 1 pins serve alternate functions, as
listed below:
Port Pin
P1.6
12-18
Alternate Function
RTS (R~est to Send). In a non-loop configuration, R TS signals that the 8044 is ready to
transmit data.
intel·
October 1988
II
The RUPITM -44
Serial Interface Unit
Order Number: 296165-001
12-19
THE RUPITM-44 SERIAL
INTERFACE UNIT
CONTENTS
PAGE
1.0 DATA LINK CONFIGURATIONS ... 12-21
2.0 DATA CLOCKING OPTIONS ...... 12-21
3.0 DATA RATES ...................... 12-21
4.0 OPERATIONAL MODES ........... 12-24
4.1 AUTO Mode .................... 12-24
4.2 FLEXIBLE Mode .. , ............. 12-27
5.08044 FRAME FORMAT
OPTIONS ........................ 12-27
5.1 Standard SDLC Format ......... 12-27
5.2 No Control Field
(Non-Buffered Mode) ......... 12-27
5.3 No Control Field and No Address
Field ......................... 12-27
5.4 No FCS Field ................... 12-28
6.0 HLDC .............................. 12-29
7.0 SIU SPECIAL FUNCTION
REGISTERS .....................
7.1 Control and Status Registers ....
7.2 Parameter Registers ............
7.3 ICE Support Registers ..........
8.0 OPERATION .......................
8.1 Initialization .....................
8.2 AUTO Mode ....................
8.3 FLEXIBLE Mode ................
8,4 8044Data Link Particulars ......
8.5 Turn Around Timing .............
12-29
12-29
12-30
12-31
12-33
12-33
12-34
12-34
12-34
12-34
9.0 MORE DETAILS ON SIU
HARDWARE ..................... 12-51
9.1 The Bit Processor .. .. .. .. .. .. ... 12-51
9.2 The Byte Processor ............. 12-51
10.0 DIAGNOSTiCS ................... 12-53
12-20
inial..
THE RUPITM·44 SERIAL INTERFACE UNIT
SERIAL INTERFACE
Externally Clocked Mode
The serial interface provides a high-performance communication link. The protocol used for this communication is based on the IBM Synchronous Data Link
Control (SDLC). The serial interface also supports a
subset of the ISO HDLC (International Standards Organization High-Level Data Link Control) protocol.
In the externally clocked mode, a common Serial Data
Clock (SCLK on pin 15) synchronizes the serial bit
stream. This clock signal may .come from the master
CPU or primary station, or from an external phaselocked loop local to the 8044. Figure 3 illustrates the
timing relationships for the serial interface signals when
the externally clocked mode is used in point-to-point
and multipoint data link configurations.
The SDLC/HDLC protocols have been accepted as
standard protocols for many high-level teleprocessing
systems. The serial interface performs many of the
functions required to service the data link without intervention from the 8044's own CPU. The programmer
is free to concentrate on the 8044's function as a peripheral controller, rather than having to deal with the details of the communication process.
Incoming data is sampled at the rising edge of SCLK,
and outgoing data is shifted out at the falling edge of
SCLK. More detailed timing information is given in the
8044 data sheet.
-
Self Clocked (Asynchronous) Mode
Five pins on the 8044 are involved with the serial interface:
RTS/P16
Pin 7
CTS/P17
Pin 8
Pin 10 I/O/RXD/P30
Pin 11 DATAlTXD/P31
Pin 15 SCLK/T1//P35
The self clocked mode allows data transfer without a
common system data clock. Using an on-chip DPLL
(digital phase locked loop) the serial interface r e c o v e r s .
the data clock from the data stream itself. The DPLL
requires a reference clock equal to either 16 times or 32
times the data rate. This reference clock may be externally supplied or internally generated. When the serial
interface generates this clock internally, it uses either
the 8044's internal logic clock (half the crystal frequency's PH2) or the "timer I" overflow. Figure 4 shows
the serial interface signal timing relationships for the
loop configuration, when the unclocked mode is used.
Figure 1 is a functional block diagram of the serial interface unit (SIU). More details on the SIU hardware
are given later in this chapter.
1.0 DATA LINK CONFIGURATIONS
The serial interface is capable of operating in three serial data link configurations:
1) Half-Duplex, point-to-point
2) Half-Duplex, multipoint (with a half-duplex or fullduplex primary)
3) Loop
Figure 2 shows these three configurations. The RTS
(Request to Send) and CTS (Clear to Send) hand-shaking signals are available in the point-to-point and multi.point configurations.
The DPLL monitors the received data in order to derive a data clock that is centered on the received bits.
Centering is achieved by detecting all transitions of the
received data, and then adjusting the clock transition
(in increments of '118 bit period) toward the center of
the received bit. The DPLL converges to the nominal
bit center within eight bit transitions, worst case.
To aid in the phase locked loop capture process, the
8044 has a NRZI (non-return-to-zero inverted) data encoding and decoding option. NRZI coding specifies
that a signal does not change state for. a transmitted
binary 1, but does change state for a binary o. Using the
NRZI coding with zero-bit insertion, it can be guaranteed that an active signal line undergoes a transition at
least every six bit times.
2.0 DATA CLOCKING OPTIONS
The serial interface can operate in an externally clocked
mode or in a self clocked mode.
3.0 DATA RATES
The maximum data rate in the externally clocked mode
is 2.4M bits per second (bps) a half-duplex configuration, and 1.0M in a loop configuration.
12-21
_.
l
~
BIT PROCESSOR
BYTE PROCESSOR
SYNCHRONIZED
a
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296165-1
intel .
THE RUPITM-44 SERIAL INTERFACE UNIT
8044
CONTROLLED
SECONDARY
MASTERI
PRIMARY
296165-2
1) HALF-DUPLEX, POINT-TO-POINT
MASTERI
PRIMARY
-
~
~
8044
CONTROLLED
SECONDARY
8044
CONTROLLED
SECONDARY
296165-3
2) HALF-DUPLEX, MULTIPOINT
MASTERI
PRIMARY
8044
CONTROLLED
SECONDARY
8044
CONTROLLED
SECONDARY
8044
CONTROLLED
SECONDARY
296165-4
3) LOOP
Figure 2. RUPI-44 Data Link Configurations
12-23
•
infel· .
THE RUPITM·44 SERIAL INTERFACE UNIT
In the self clocked mode with an external reference
clock, the maximum data rate is 375K bps.
In the self clocked mode with an internally generated
reference clock, and the 8044 operating with a 12 MHz
crystal, the available data rates are 244 bps to 62.5K
bps, 187.5K bps and 375K bps.
For more details see the table in the SMD register description, below.
4.0 OPERATIONAL MODES
The Serial Interface Unit (SIU) can operate in either of
two response modes:
1) AUTO mode
2) FLEXIBLE (NON"AUTO) mode
In the AUTO mode, the SIU performs in hardware a
subset of the SDLC protocol called the normal response mode. The AUTO mode enables the sm to recognize and respond to certain kinds of SDLC frames
without intervention from the 8044's CPU. AUTO
mode provides a faster turnaround. time and a simplified software interface, whereas NON-AUTO mode
provides a greater flexibility with regard to the kinds of
operation permitted.
In AUTO mode, the 8044 can act only as a normal
response mode secondary station-that is, it can ~ans
mit only when instructed to do so by the primary station. All such AUTO mode responses adhere strictly to
IBM's SDLC definitions.
In the FLEXIBLE mode, reception or transmission of
each frame by the SIU is performed under the control
of the CPU. In this mode the 8044 can be either a
primary station or a secondary station.
In both AUTO and FLEXIBLE modes, short frames,
aborted frames, or frames which have had CRC's are
ignored by the sm.
The basic format of an SDLC frame is as follows:
IFlag IAddress IControl IInformation IFCS IFlag I
Format variations consist of omitting one or more of
the fields in the SDLC frame. For example, a supervisory frame is formed by omitting the information field.
Supervisory frames are used to confirm received
frames, indicate ready or busy conditions, and to report
errors. More details on frame formats are given in the
SDLCFrame Format Options section, below.
4.1 AUTO Mode
To enable the SIU to receive a frame in AUTO mode,
the 8044 CPU sets up a receive buffer. This is done by .
writing two registers-Receive Buffer Start (RBS) Address and Receive Buffer Length (RBL).
The SIU receives the frame, examines the control byte,
and takes the appropriate action. If the frame is an
information frame, the SIU will load the receive buffer,
interrupt the CPU (to have the receive buffer read), and
make the required acknowledgement to the primary
station. Details on these processes are given in the Operation section, below.
In addition to receiving the information frames~ the
SIU in AUI'O mode is capable of responding to the
following commands (found in the control field of supervisory frames) from the primary station:
RR (Receive Ready): Acknowledges that the Primary
station has correctly received numbered frames up
through NR - 1, and that it is ready to receive frame
NR·.
RNR (Receive Not Ready): Indicates a temporary busy
condition (at the primary station) due to buffering or
other internal Constraints. The quantity NR in the control field indicates the number of the frame expected
after the busy condition ends, and may be used to acknowledge the correct reception of the frames up
through NR - 1.
REJ (Reject): Acknowledges the correct reception of
frames up through NR - 1, and requests transmission
or retransmission starting at frame NR. The 8044 is
capable of retransmitting at most the previous frame,
and then only if it is still available in the transmit buffer.
UP (Umiumbered Poll): Also called NSP (Non-Sequenced Poll) or ORP (Optional Response Poll). This
command is used in the loop configuration.
To enable the SIU to transmit an information frame in
AUTO mode, the CPU sets up a transmit buffer. This
is done by writing two registers-Transmit Buffer Start
(TBS) Address and Transmit Buffer Length (TBL), and
filling the transmit buffer with the information to be
transmitted.
When the transmit buffer is full, the SIU can automatically (without CPU intervention) send an information
frame (I-frame) with the appropriate sequence numbers, when the data link becomes available (when the·
8044 is polled for information). After the sm has
transmitted the I-frame, it waits for acknowledgement
from the receiving station. If the acknowledgement is
'12-24
intel .
THE RUPITM-44 SERIAL INTERFACE UNIT
negative, the SIU retransmits the frame. If the acknowledgement is positive, the SIU interrupts the
CPU, to indicate that the transmit buffer may be reloaded with new information.
\J
RTs
7
CTs
TRANSCEIVER/BUFFER
8
8044
I/O
10
~
[>
-
DATA
- _______
. ~~~1~__~__________~~:::;f;~~::
..J
CLEAR "RTS"
SET "SI"
TRANSMIT
ABORT
SEQUENCE
296165-24
Figure 12_ SIU FLEXIBLE Mode Transmit Flowchart
12-49
II
THE RUPITM·44 SERIAL INTERFACE UNIT
CLEAR "sr'
XMIT
-1,PENDING
BUFFULL
TBF INDICATES
LAST TRANSMIT
ABORTED BY CPU
OR PRIMARY.
BUFEMPTY
CTRL FIELD . .TCB
I·FIILD .. XMITBUF
SET"T8F"
SET "ATS·
296165-25
Figure 13. FLEXIBLE Mode Response to TrlJnsmlt "SI"
12-50
THE RUPITM·44 SERIAL INTERFACE UNIT
9.0 MORE DETAILS ON SIU
HARDWARE
The SIU divides functionally into two sections-a bit
processor (BIP) and a byte processor (BYP)-sharing
some common timing and control logic. As shown in
Figure 14, the BIP operates between the serial port pins
and the SIU bus, and performs all functions necessary
to transmit/receive a byte of data to/from the serial
data stream. These operations include shifting, NRZI
encoding/decoding, zero insertion/deletion, and FCS
generation/checking. The BYP manipulates bytes of
data to perform message formatting, and other transmitting and receiving functions. It operates between the
sm bus (SIB) and the 8044's internal bus (IB). The
interface between the SIU and the CPU involves an
interrupt and some locations in on-chip RAM ,space
which are managed by the BYP.
The maximum possible data rate for the serial port is
limited to '12 the internal clock rate. This limit is imposed by both the maximum rate of DMA to the onchip RAM, and by the requirements of synchronizing
to an external clock. The internal clock rate for an 8044
running on a 12 MHz crystal is 6 MHz. Thus the maximum 8044 serial data rate is 3 MHz. This data rate
drops down to 2.4 MHz when time is allowed for external clock synchronization.
9.1 The Bit Processor
In the asynchronous (self clocked) modes the Clock is
extracted from the data stream using the on-chip digital
phase-locked-loop (DPLL). The DPLL requires a clock
input at 16 times the data rate. This 16 X clock may
originate from SCLK, Timer 1 Overflow, or PH2 (one
half the osciJIator frequency). The extra divide by-two
described above allows these sources to be treated alternatively as 32 X clocks.
The DPLL is a free-running four-bit counter running
off the 16 X clock. When a transition is detected in the
receive data stream, a count is dropped (by suppressing
the carry-in) if the current count value is greater than 8.
A count is added (by injecting a carry into the second
stage rather than the first) if the count is less than 8. No
adjustment is made if the transition occurs at the count
of 8. In this manner the counter locks in on the point at
which transitions in the data stream occur at the count
of 8, and a clock pulse is generated when the count
overflows to O.
The zero insert/delete circuitry (ZID) performs zero
insertion/deletion, and also detects flags, GA's (GoAhead's), and aborts (same as GA's) in the data
stream. The pattern 1111110 is detected as an early
GA, so that the GA may be turned into a flag for loop
mode transmission.
The shut-off detector monitors the receive data stream
for a sequence of eight zeros, which is a shut-off command for loop mode transmissions. The shut-off detector is a three-bit counter which is cleared whenever a
one is found in the receive data stream. Note that the
ZID logic could not be used for this purpose, because
the receive data must be monitored even when the ZID
is being used for transmission.
As an example of the operation of the bit processor, the
following sequence occurs in relation to the receive
data:
1) RXD is sampled by SCLK, and then synchronized
to the internal processor clock (IPC).
2) If the NRZI mode is selected, the incoming data is
NRZI decoded.
3) When receiving other than the flag pattern. the ZID
deletes the '0' after 5 consecutive 'I 's (during transmission this zero is inserted). The ZID locates the
byte boundary for the rest of the circuitry. The ZID
deletes the 'O's by preventing the SR (shift register)
from receiving a clocking pulse.
4) The FCS (which is a function of the data between
the flags-not including the flags) is initialized and
started at the detection of the byte boundary at the
end of the opening flag. The FCS is computed each
bit boundary until the closing flag is detected. Note
that the received FCS has gone through the ZID
during transmission.
9.2 The Byte Processor
Figure 15 is a block diagram of the byte processor
(BYP). The BYP contains the registers and controllers
necessary to perform the data manipulations associated
with SDLC communications. The BYP registers may
be read or written by the CPU over the 8044's internal
bus (IB). using standard 8044 hardware register operations. The 8044 register select PLA controls these operations. Three of the BYP registers connect to the IB
through the IBS, a sub-bus which also connects to the
CPU interrupt control registers.
In order to perform NRZI decoding, the NRZI decoder compares each bit of input data to the previous bit.
There are no clock delays in going through the NRZI
decoder.•
12-51
THE RUPITM·44 SERIAL INTERFACE UNIT
INTERRUPT
IB
l
CPU
RAM
r
- ----
r-I
r------------Siij,
-------
SHARED
REGISTERS
h
~
'--
BIP
BYP
SIB
I
I
I
I
I
I
I
1/01 RXD
DATAITXD
I
L ___________________________ J
296165-26
Figure 14. The Bit and Byte Processors
Simultaneous access of a register by both the IB and the
SIB is prevented by timing. In particular, RAM access
is restricted to alternate internal processor cycles for
the CPU and the SIU, in such a way that collisions do
not occur.
As an example of the operation of the byte processor,
the following sequence occurs in relation to the receive
~~
.
1) Assuming that there is an address field in the frame,
the BYP takes the station address from the register
file into temporary storage. After the opening flag,
the next field (the address field) is compared to the
station address in the temporary storage. If a match
occurs, the operation continues.
2) Assuming that there is a control field in the frame,
the BYP takes the next byte and loads it into the
RCB register. The RCB register has the logic to
update the NSNR register (increment receive count,
set SES and SER flags, etc.).
3) Assuming that there is an information field, the next
byte is dumped into RAM at the RBS location. The
DMA CNT (RBL at the opening flag) is loaded
from the DMA CNT register into the RB register
and decremented. The RFL is then loaded into the
RB register, incremented, and stored back into the
register file.
4) This process continues until the DMA CNT reaches
zero, or until a closing flag is received. Upon either
event, the BYP updates the status, and, if the CRC
is good, the NSNR register.
12-52
int'eL
THE RUPITM-44 SERIAL INTERFACE UNIT
ir---------------'
I
I
I
I
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I
RECEIVE
BYTE
REGISTER
I
I
M
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I
I
I
TEMP
REGISTER
-
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I
I
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I
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SIB
(
11
SHIFT
REGISTER
I
I
I
I
I
11
I
BIP
I
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I
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11
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II
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TIMING
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CONTROL
~
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REGISTERS
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L ______________
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IB
I
I
I
I
I
~~
296165-27
Figure 15. The Byte Processor
10.0 DIAGNOSTICS
An SIU test mode has been provided, so that the onchip CPU can perform limited diagnostics on the SIU.
The test mode utilizes the output latches for P3.0 and
P3.1 (pins 10 and 11). These port 3 pins are not useful
as out-put ports, since the pins are taken up by the
serial port functions. Figure 16 shows the signal routing
associated with the SIU test mode.
Writing a 0 to P3.1 enables the serial test mode (P3.1 is
set to 1 by reset). In test mode the P3.0 bit is mapped
into the received data stream, and the 'write port 3'
control signal is mapped into the SCLK path in place of
Tl. Thus, in test mode, the CPU can send a serial data
stream to the SIU by writing to P3.0. The transmit data
stream can be monitored by reading P3.1. Each successive bit is transmitted from the SIU by writing to any
bit in Port 3, which generates SCLK.
In test mode, the P3.0 and P3.1 pins are placed in a
high voltage, high impedance state. When the CPU
reads P3.0 and P3.1 the logic level applied to the pin
will be returned. In the test mode, when the CPU reads
3.1, the transmit data value will be returned, not the
voltage on the pin. The transmit data remains constant
for a bit time. Writing to P3.0 will result in the signal
being outputted for a short period of time. However,
since the signal is not latched, P3.0 will quickly return
to a high voltage, high impedance state.
12-53
1----/-
l
9
CPU
BUS
PIN 15
SCLKI
TIl
P35
TIMER 1 OVF
SYSCLK
SIUSERIAL
DATACLDCK
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READ PORT 3
WRITE PORT 3
PINll
DATAl
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P31
SIU
TRANSMIT
DATA
STREAM
296165-28
int'eL
THE RUPITM·44 SERIAL INTERFACE UNIT
The serial test mode is disabled by writing a 1 to P3.1.
Care must be taken that a 0 is never written to P3.1 in
the course of normal operation, since this causes the
test mode to be entered.
transmits a supervisory frame. This frame consists of an
opening flag, foIIowed by the station address, a control
field indicating that this is a supervisory frame with an
RNR command, and then a closing flag.
Figure 17 is an example of a simple program segment
that can be imbedded into the user's diagnostic program. That example shows how to put the S044 into
"Loop-back mode" to test the basic transmitting and
receiving functions of the SIU.
Each byte of the frame is transmitted by writing that
byte into the A register and then caIIing the subroutine
XMITS. Two additional SCLKs are generated to guarantee that the last bits in the frame have been clocked
into the SIU. FinaIIy the CPU reads the status register
(STS). If the operation has proceeded correctly, the
status wiII be 072R. If it is not, the program jumps to
the ERROR loop and terminates.
Loop-back mode is functionaIIy equivalent to a hardwire connection between pins 10 and lIon the S044.
In this example, the S044 CPU plays the role of the
primary station. The SIU is in the AUTO mode. The
CPU sends the SIU a supervisory frame with the poII
bit set and an RNR command. The SIU responds with
a supervisory frame with the poII bit set and an RR
command.
The operation proceeds as foIIows:
Interrupts are disabled, and the self test mode is enabled by writing a zero to P3.L This establishes P3.0 as
the data path from the CPU to the SIU. CTS (clear-tosend) is enabled by writing a zero to Pl.7. The station
address is initialized by writing OSAR into the STAD
(station address register).
The SIU is configured for receive operation in the
clocked mode and in AUTO mode. The CPU then
The SIU generates an SI (SIU interrupt) to indicate
that it has received a frame. The CPU clears this interrupt, and then begins to monitor the data stream that is
being generated by the SIU in response to what it has
received. As each bit arrives (via P3.1), it is moved into
the accumulator, and the CPU compares the byte in the
accumulator with 07ER, which is the opening flag.
When a match occurs, the CPU identifies this as byte
boundary, and thereafter processes the information
byte-to-byte.
The CPU caIIs the RCVS subroutine to get each byte
into the accumulator. The CPU performs compare operations on (successively) the station address, the control field (which contains the RR response), and the
closing flag. If any of these do not compare, the program jumps to the ERROR loop. If no error is found,
the program jumps to the DONE loop.
12-55
II
infel..
THE RUPITM-44 SERIAL INTERFACE UNIT
PlCS-51 "'ACAO ASSEMBLER
DATA
ISIS-II MCS-51 ""CRD ASSEMILER VOl. 0
PLACED IN : Fl: DATA. Ol~
DI~ECT ~DULE
ASSEMBLER rNVC*.ED BV;
LOC
Ol~
••• 51: 11: d.t •. un 'evice(44)
LINE
SOURCE
1
:I
0000
0003
0005
0007
7!!CBOO
C2U
C297
75CEBA
OOOA '5D86111
0000 75e90!
0010 7:5CeCa
0013
0015
00IS
OOIA
0010
OOIF
0022
0024
0027
002<;>
747E
.20066
74SA
120066
7495
.20066
747E
1200<>1>
0280
0210
0028 E5C8
0020 14722A
0030 cacc
0032 7400
0034 710C
3
4
INn:
6
7
8
9
.0
11
.:1
13
14
.5
'6
17
18
19
20
21
2:1
23
24
25
D210
A211
13
B47E03
020046
DIF3
004302005111
0046 1200SC
0049848AOE
004C .2005C
004F 14BIOB
OO:J2 12005C
0058 847£02
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
EnaUe .. ,If t •• t Mod.
En.bl, eTB
STAD. *SAH
005A SOFE
005C 7808
005E DalO
0060
0062
001>3
0065
Aii!SI
13
D8F9
22
OOA6 '1B09
0068 13
0069 0901
0061 22
COAC 400 ..
OOI>E C210
0070 SOFA
C07;! 0280
0074 SOF2
57
58
59
60
61
62
63
64
65
66
67
68
69
70
7.
7a
73
74
7.
76
BEND:
NBNR.
",p,
1K)1H
STS.
IOC2H
I1DV
CALL
I1DV
CALL
I1DV
CALL
I1DV
CALL
BETI
SETI
MaV
e.INE
J
addr •••
SES-O. NUS)-' • •"-0
NFCB-l
T8F-l. R8E-l, M-J
J
,
,
A • • 7EH
XMITS
A • • SAH
XMITS
A. .a95H
XMITS
~
• 7EH
XMITS
P3.0
. P3.0
n.
,
.
A. BTB
A • • 721-1.
Ttll SIU l'eceiv ••• '1 •• f:l,..t
n.lt
.dd" ••• i .
RNA SUP FAAf1£ wi th P/F-l. tMCP)-4
,
,
,
,
Aecei..,. C'losing fl ••
Own.,..,. ext". SCLK', to
Initht • .,..ceiv. ar.:t:ian
Chec' for .pprop"'.'. .t.tus
ERROR
PREPARE TO RECEIVE AUPI'S RESPONCE TO PRI"ARY'S'RNR
RECV:
; Ch.,. 91
I 'Ch.,. ACe
i
T'f"V 1.
CLR
IIOV
lIOII
L~
WFLAQI:
WFLQI'
CNTINU;
t, •••
FOR THE OPENINO FLAG
SETB
P3.0
I1DY
RRC
CJNE
C. P3.1
A
A • • 07EH.
.JPIP
R3. WFLAQI
ERROR
CALL
Revs
C.JNE
.DJNZ
,
,
C~NE
.IMP
DONE
ERROR:
JttP
ERROR
MOV
RD. .OS
P3.0
C. P3. I
A
RD. OETBIT
CALL
RCVS:
OETBIT: SETB
MOV
RRC
D~NZ
T,.an •• Uted lI.t.
CNTINU
DONE:
C~NE
BCLII
WFLQI
A • • OBAH. ERROR
RCYS
A. .08IH. ERROR
RCVS
A • • 07EH. ERROR
CALL
·,
·
,
,
Oet SJU', Tl"fI!'n •• Uted .d'l'lt"
"eU
Pri··,.v
'1'0. stU
expects to receive RR
Xl'1ITB:
~OV
L3:
RRC
Ll:
L2·
RD • • 9
A
DJNZ
RET
RD.
~C
La
CLR
P3., 0
L3
"""
SETB
~MP
·,,
fl_.
Rec.ive claling
Initialize the bit count ....
BCLII
T".n,.' tted d.t.
RET
77
78
79
80
81
82
83
84
II
NSfS)-3.
I.AH
I1DY
I1DY
I1DY
56
0058 80FE
Ini tiel i
I
TRANSMIT A SUPERVISORY FR ...... FROM THE PRII'IARV BTATION WITH THE POLL
I I T SET AND A RNA CCIft\ND
3';>
0031>
0038
003A
0031
003E
0041
BTB ••OOH
P3. I
PI.7
I CONFIGURE RECEIVE OPERATlDN
OIl>
27
28
29
30
3.
32
33
34
35
36
37
38
~V
CLR
CLR
I1DY
5
..
counts,.
InitiaU,. tho
Put th_bit to b. trwn.-IUted
in the e.""\1
When _II bit. have b •• n •• nt
L'
",.tu,."
I I tho
,
c."',,,,
bit i .
•• t. . . t
port P3.0 e1,.
cl •• r port P3.0
P3.0
L3
ond
296165-29
Figure 17. Loop-Back Mode Software
12-56
infel·
November 1989
II
8044 Application Examples
Order Number: 296166-001
12-57
8044 APPLICATION
EXAMPLES
CONTENTS
PAGE
8044 APPLICATION EXAMPLES
1.0 INTERFACING THE 8044 TO A
MICROPROCESSOR ................ 12-59
Overview ...............................
The Interface ...........................
The Software ..........................
Conclusion .............................
12-59
12-59
12-59
12-60.
A HIGH PERFORMANCE NETWORK
USING THE 8044 .................... 12-68
2.0 INTRODUCTION ................... 12-68
2.1 Hardware .......................... 12-68
2.2 SDLC Basic Repertoire ............. 12-69
2.3 Secondary Station Driver Using AUTO
Mode ................................ 12-72
2.4 Application Module; ASYNC to SDLC
Protocol Converter ................... 12-80.
2.5 Primary Station ..................... 12·84
APPENDIX A: 8044 SOFTWARE
FLOWCHA~TS
...................... 12-88
APPENDIX B: LISTINGS OF
SOFTWARE MODULES ............ 12-10.8
12-58
infel .
8044 APPLICATION EXAMPLES
1.0 INTERFACING THE 8044 TO A
MICROPROCESSOR
The 8044 is designed to serve as an intelligent controller for remote peripherals. However, it can also be used
as an intelligent HOLC/SOLC front end for a microprocessor, capable of extensively off-loading link control functions for the CPU. In some applications, the
8044 can even be used for communications preprocessing, in addition to data link control.
This section describes a sample hardware interface for
attaching the 8044 to an 8088. It is general enough to
be extended to other microprocessors such as the 8086
or the 80186.
OVERVIEW
A sample interface is shown in Figure 1. Transmission
occurs when the 8088 loads a 64 byte block of memory
with some known data. The 8088 then enables the
8237A to OMA this data to the 8044. When the 8044
has received all of the data from the 8237A, it sends the
data in a SOLC frame. The frame is captured by the
Spectron Oatascope™' which displays it on a CRT in
hex format.
In reception, the Oatascope sends a SOLC information
frame to the 8044. The 8044 receives the SOLC frame,
buffers it, and sends it to the 8088's memory. In this
example the 8044 is being operated in the NON-AUTO
mode; therefore, it does not need to be polled by a primary station in order to transmit.
THE INTERFACE
The 8044 does not have a parallel slave port. The
8044's 32 I/O lines can be configured as a local microprocessor bus master. In this configuration, the 8044
can expand the ROM and RAM memory, control peripherals, and communicate with a microprocessor.
The 8044, like the 8051, does not have a Ready line; so
there is no way to put the 8044 in wait state. The clock
on the 8044 cannot be stopped. Oual port RAM could
still be used, however, software arbitration would be
the only way to prevent collisions. Another way to interface the 8044 with another CPU is to put a FIFO or
queue between the two processors, and this was the
method chosen for this design.
Figure 2 shows the schematic of the 8044/8088 interface. It involves two 8-bit tri-state latches, two SR flipflops, and some logic gates (6 TTL packs). The circuitry implements a one byte FIFO. RS422 transceivers are
used, which can be connected to a multidrop link. Fig'Datascope is a trademark of Spectron Inc.
ure 3 shows the 8088 and support circuitry; the memory and decoders are not shown. It is a basic 8088 Min
Mode system with an 8237A OMA controller and an
8259A interrupt controller.
OMA Channel One transfers a block of memory to the
tri-state latch, while Channel Zero transfers a block of
data from the latch to 8088's memory. The 8044's Interrupt 0 signal vectors the CPU into a routine which
reads from the internal RAM and writes to the latch.
The 8044's Interrupt I signal causes the chip to read
from the latch and write to its on-chip data RAM. Both
OMA requests and acknowledges are active low.
Initially, when the power is applied, a reset pulse coming from the 8284A initializes the SR flip-flops. In this
initialization state, the 8044's transmit interrupt and
the 8088's transmit OMA request are active; however,
the software keeps these signals disabled until either of
the two processors are ready to transmit. The software
leaves the receive signals enabled, unless the receive
buffers are full. In this way either the 8088 or the
are always ready to receive, but they must enable the
transmit signal when they have prepared a block to
transmit. After a block has been transmitted or received, the OMA and interrupt signals return to the
initial state.
804411
The receive and transmit buffer sizes for the blocks of
data sent between the 8044 and the 8088 have a maximum fixed length. In this case the buffer size was 64
bytes. The buffer size must be less than 192 bytes to
enable 8044 to buffer the data in its on-chip RAM. This
design allows blocks of data that are less than 64 bytes,
and accommodates networks that allow frames of varying size. The first byte transferred between the 8088
and the 8044 is the byte count to follow; thus the 8044
knows how many bytes to receive before it transmits
the SOLC frame. However, when the 8044 sends data
to the 8088's memory, the 8237A will not know if the
8044 will send less than the count the 8237A was programmed for. To solve this problem, the 8237A is operated in the single mode. The 8044 uses an I/O bit to
generate an interrupt request to the 8259A. In the
8088's interrupt routine, the 8237A's receive OMA
channel is disabled, thus allowing blocks of data less
than 64 bytes to be received.
THE SOFTWARE
The software for the 8044 and the 8088 is shown in
Table 1. The 8088 software was written in PL/M86,
and the 8044 software was written in assembly language.
The 8044 software begins by initializing the stack, interrupt priorities, and triggering types for the interrupts. At this point, the SIU parameter registers are
12-59
intel~
8044 APPLICATION EXAMPLES
------------,
DISPLAY/KEYBOARD
INTERFACE
I
I
I
I
I
I
I
I
DATASCOPE
296166-1
Figure 1. Block Diagram of 8088/8044 Interface Test
initialized. The receive and transmit buffer starting addresses and lengths are loaded for the on-chip DMA.
This DMA is for the serial port. The serial station address and the transmit control bytes are loaded too.
Once the initialization has taken place, the SIU interrupt is enabled, and the external interrupt which receives bytes from the 8088 is enabled. Setting the 8044's
Receive Buffer Empty (RBE) bit enables the receiver. If
this bit is reset, no serial data can be received. The 8044
then waits in a loop for either RECEIVE DMA interrupt or the SERIAL INT interrupt.
The RECEIVE DMA interrupt occurs when the
8237A is transferring a block of data to the 8044. The
first time this interrupt occurs, the 8044 reads the latch
and loads the count value into the R2 register. On subsequent interrupts, the 8044 reads the latch, loads the
data into the transmit buffer, and decrements R2.
When R2 reaches zero, the interrupt routine sends the
data in an SDLC frame, and disables the RECEIVE
DMA interrupt. After the frame has been transmitted,
a serial interrupt is generated. The SERIAL INT routine detects that a frame has been transmitted and reenables the RECEIVE DMA interrupt. Thus, while the
frame is being transmitted through the SIU, the 8237A
is inhibited from sending data to the 8044's transmit
buffer.
The TRANSMIT DMA routine sends a block of data
from the 8044's receive buffer to the 8088's memory.
Normally this interrupt remains disabled. However, if a
serial interrupt occurs, and the SERIAL INT routine
detects that a frame has been received, it cal1s the
SEND subroutine. The SEND subroutine loads the
number of bytes which were received in the frame into
the receive buffer. Register Rl points to the receive
buffer and R2 is loaded with the count. The TRANSMIT DMA interrupt is enabled, and immediately upon
returning from the SERIAL INT routine, the interrupt
is acknowledged. Each time the TRANSMIT DMA interrupt occurs, a byte is read from the receive buffer,
written to the latch, and R2 is decremented. When R2
reaches 0, the TRANSMIT DMA interrupt is disabled,
the SIU receiver is re-enabled, and the 8044 interrupts
the 8088.
CONCLUSION
For the software shown in Table 1, the transfer rate
from the 8088's memory to the 8044 was measured at
75K bytes/sec. This transfer rate largely depends upon
the number of instructions in the 8044's interrupt service routine. Fewer instructions result in a higher transfer rate.
There are many ways of interfacing the 8044 10cal1y to
another microprocessor: FIFO's, dual port RAM with
software arbitration, and 8255's are just a few. Alternative approaches, which may be more optimal for certain
applications, are certainly possible.
12-60
_.
l
~
OREOl
OREOI
OACKl
+5V
/\
I
SPIED
"'11
cEo
.
C
ID
I§M
lOW
8
5
}V
8259A
Nl
INT
iNTA
-......ftUllpsENA1SL
lip'
I
MI
~
5
6
!'3
I\)
....
....
DOACKI
S"
_ RESET
..-...
III
·n
...
...
ID
0
::T
ID
01)
o
"'"'""
»
'U
P5
l
C»
0
m
.... ID
1
2
3
4
'U
r-
(;
~
oZ
2732A
~K'
01
oJ2!!.
In
><
»
s::
'U
oJ2!!'Kl
_lOW
C»
0
C»
C»
r-
0'
01
In
(J)
GIlD
02
03
+5V
DC
OS
D6
07
Vee
At
~ 2128
RUPI EXPANSION BUS
A3
M
AS
Pl
AS
A7
AS
A9
101'
~~l2
WE/WR
OE/RD
296166-2
11
_.
l
-5
C5
•
@)
nf%"",,"W"""'.....,
83 1820 -
BYSINeI.
RESET
r To 110
V
REB
~
fa
C
~
~
I\)
en
I\)
:iii:
5'
.iiI:
~
(/)
1
~
PCLK
PCLK
,...
CBYNe
CLK
:=
RST
CLK
MEMR
r AI
L : : 7. 04
~ 81
~~
t5
IK
RDY
Ol:~~~~~~~~~~~~~~~~~~~~~~~~~~~~§~ ~:-
~L g~
I
121.
::fn
l!
~
82
RDYI ~
5257
D3
lOW
t5V
A4 OC
-f
,.~a
...
~
.,~ .,
'-~ '" ~. ..
~ ~
...
-
.
~~
DI7
D07
DIS
DOl
DIS Fl DOS
JI
INTH:81
ADI
g:;
Dl2
LS
AI3 All AOI
AI5 AI2 AI
DI1
DIf
._ (MIN)
8
TEIt
(AUf (A'1
ADI
ADS
AD4
~
=
!
N
DQ2
DOl
DOl
-<
~
AfJ..A7
rm
~
'1J
en
04
-c> Do-D7
(((rt(r(
I
co
g
f2K
-c> AI5·AS
DE Bra
DI7
D07
g:: 01 gg:
8~N~
DIZ
Dli
DIt
=
DQ2
DOl
DOl
WI
296166-3
intet
8044 APPLICATION EXAMPLES
Table 1. Transmit and Receive Software for an 8044/8088 System
LOC OBJ LINE
SOURCE
I
2
0000
0000
0000 8024
0026
0026
0029
002C
002F
7581AA
75B800
75C954
758844
0032 758DEC
0035 758920
0038
003B
003E
0041
0044
0047
75DC6A
75DB40
75CC2A
75CB40
75CE55
75DAII
004A 901000
004D D200
004F D2CE
0051 75A894
0054 80FE
0056 80FE
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 +1
37
0058 85CD29
005B 7929
0050 AACD
005F OA
0060 D2A8
0062 22
0063
0013
0013 020063
0063
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Sdebug
title
FIRSLBYTE
INIT:
ERROR:
SEJ
(8044/8088 INTERFACE)
BIT
ORG
SJMP
0
INIT
ORG
26H
MOV
MOV
MOV
MOV
SP. #170
IP. #00
SMD. *54H
TCON.#44H
MOV
MOV
THI. #OECH
TMOD. *20H
MOV
MOV
MOV
MOV
MOV
MOV
TBS. #106
; SET UP SIU PARAMETER REGISTERS
TBL. #64
RBS. *42
RBL. *64
STAD. *55H
TCB. *ooOIOOOIB; RR. P/F= I
MOV
SETB
DPTR. HlooOH
FIRSLBYTE
SETB
MOV
RBE
IE. #IOOIOlooB
; DPTR POINTS TO TRI-STATE LATCH
; FLAG TO INDICATE FIRST BYTE
; FOR RECEIVE INTERRUPT ROUTINE
; READY TO RECEIVE
; ENABLE RECEIVE DMA AND SIU INTERRUPT
SJMP
S
; WAIT HERE FOR INTERRUPTS
SJMP
ERROR
;••••••••••••••••••••••••••
SEND:
; FLAG
0
MOV
MOV
MOV
INC
SETB
RET
41.RFL
.RI.H41
R2. RFL
R2
EXO
;...................
LOCTMPSET
ORG
LJMP
ORG
; INITIALIZE STACK
; ALL INTERRUPTS ARE EQUAL PRIORITY
; TIMER I OVERFLOW. NRZI. PRE-FRAME SYNC
; EDGE TRIGGERED EXTERNAL INTERRUPT I
; LEVEL TRIGGERED EXTERNAL INTERRUPT 0
;TIMER I ON
; INITIALIZE TIMER. 3125 BPS
; TIMER I AUTO RELOAD
SUBROUTINES
•••••••••••••••••••••••••••••••
; FIRST BYTE IN BLOCK IS COUNT
; POINT TO BLOCK OF DATA
; LOAD COUNT
; ENABLE DMA TRANSMIT INTERRUPT
INTERRUPT SERVICE ROUTINES
•••••••••••••••••••••
S
; SET UP INTERRUPT TABLE JUMP
0013H
RECEIVLDMA
LOCTMP
RECEIVLDMA:
296166-69
12-63
II
intel·
8044 APPLICATION EXAMPLES
Table 1. Transmit and Receive Software for an 8044/8088 System (Continued)
0063 10000E
0066 EO
0067 F6
0068 08
0069DA08
006B D2CF
0060 D2CD
006F 0200
0071 C2AA
0073 32
0074 78M
0076 EO
0077 FA
0078 32
0079
0003
0003 020079
0079
0079
007A
007B
007C
E7
FO
09
DA08
007E
0080
0082
0084
C2A8
C294
0294
D2CE
0086 32
0087
0023
0023 020087
0087
0081 30CE06
oo8A 30CFOB
0080 020056
0090
0093
0095
0097
20CBeJ
1158
C2CC
32
0098 C2CC
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114.
MOVX
MOV
INC
DJNZ
A,@DPTR
@RO,A
RO
R2,L2
SETB
SETB
SETB
CLR
TBF
RTS
FIRSLBYTE
EXI
;SENDDATA
; RO IS A POINTER TO THE TRANSMIT
; BUFFER STARTING ADDRESS
; PUT THE FIRST BYTE INTO
; R2 FOR THE COUNT
RETI
L1:
MOV
RO,1106
MOVX
MOV
RETI
A,@DPTR
R2,A
74
75
76
78
79
80
81
FIRST-BYTE, L I ; THE FIRST BYTE TRANSFERRED IS THE COUNT
L2:
72
73
77
JBC
LOCTMPSET
ORG
LJMP
ORG
; READ THE LATCH
; PUT IT IN TRANSMIT BUFFER
; AFTER READING BYTES,
S
oo03H
TRANSMIT-DMA
LOCTMP
TRANSMILDMA
L3:
MOV
MOVX
I,NC
DJNZ
A,@RI
@DPTR,A
RI
R2, L}
; READ BYTE OUT OF THE RECEIVE BUFFER
; WRITE IT TO THE LATCH
CLR
cr..R
SETB
SETB
IE.O
PI. 4
PI. 4
RBE
; DISABLE INTERRUPT
; CAUSE 8088 INTERRUPT TO TERMINATE DMA
; WHEN ALL BYTES HAVE BEEN SENT
; ENABLE RECEIVER AGAIN
RETI
LOCTMPSET
ORG
LJMP
ORG
S
0023H
SERIALINT
LOC-TMP
SERIALINT:
JNB
JNB
LJMP
RCV:
XMIT:
JB
CALL
.CLR
RETI
CLR
RBE, RCV
TBF,XMIT
ERROR
; WAS A FRAME RECEIVED
; WAS A FRAME TRANSMITTED
; IF NEITHER ERROR
BOV, ERROR
SEND
SI
; IF BUFFER OVERRUN THEN ERROR
; SENDTHE FRAME TO THE 8088
SI
296166-70
12-64
inteL
8044 APPLICATION EXAMPLES
Table 1. Transmit and Receive Software for an 8044/8088 System (Continued)
009A D2AA
009C 32
115
116
117
liS
SETB
RETI
EXI
END
SYMBOL TABLE LISTING
NAME
TYPE
VALUE
BOV
ERROR
EXO
EXI
FIRSLBYTE
IE
INIT
IP
LI
B ADDR
C ADDR
B ADDR
B ADDR
B ADDR
D ADDR
C ADDR
D ADDR
C ADDR
C ADDR
C ADDR
C ADDR
D ADDR
B ADDR
D ADDR
D ADDR
C ADDR
C ADDR
D ADDR
B ADDR
C ADDR
C ADDR
B ADDR
D ADDR
D ADDR
D ADDR
B ADDR
D ADDR
D ADDR
D ADDR
D ADDR
D ADDR
D ADDR
C ADDR
C ADDR
00CSH.3
0056H
OOASH.O
00ASH.2
0020H.O
OOASH
0026H
OOBSH
0074H
0073H
OOS6H
OOS7H
0090H
00CSH.6
OOCBH
OOCCH
0090H
0063H
OOCDH
OOCSH.5
005SH
00S7H
OOCSH.4
00C9H
OOSIH
OOCEH
OOCSH.7
OODBH
OODCH
OODAH
OOSSH
OOSDH
OOS9H
0079H
009SH
L2
L3
LOCTMP
PI
RBE
RBL
RBS
RCV
RECEIVE_DMA
RFL
RTS
SEND
SERIALINT
SI
SMD
SP
STAD
TBF
TBL
TBS
TCB
TCON
THI
TMOD
TRANSMILDMA
XMIT
ATTRIBUTES
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
II
REGISTER BANK(S) USED: 0, TARGET MACHINE(S): S044
ASSEMBLY COMPLETE, NO ERRORS FOUND
296166-71
12-65
8044 APPLICATION EXAMPLES
Table 2. PL/M·86 Compiler RUPI/8088 Interface Example
SERIES-III PL/M-B6 VI. 0 COMPILATION OF MODULE RUPI_BB
ODJECT MODULE PLACED IN :Fl:R88.0BJ
COMPILER INVO~EDBY: PLMB6.86 :Fl:R88.SRC
.DEBUG
.TITLE
('RUPI/808B INTERFACE EXAMPLE')
RUPI_88: DO.
DECLARE
2
LIT
TRUE
FALSE
LITERALLY
LIT
LIT
RECV_BUFFER(64)
XMIT_BUFFER(64)
I
WAIT
BYTE.
BYTE,
BYTE,
BYTE,
1*
'LITERALLY' •
'otH',
'OOH',
8237 PORTS*/
MASTER_CLEAR_37
COMMAND_37
ALL_MASK_37
SINgLE_MASK_37
STATU8 37
REOUEBT_REG_37
MODE_REg_37
CLEAR_BYTE_PTR_37
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
'OFFDDH',
'OFFDBH'.
CHO_ADDR
CHO_COUNT
CHl_ADDR
CHI_COUNT
CH2_ADDR
CH2_CDUNT
CH3_ADDR
CH3_CDUNT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
'OFFDOH',
'OFFDIH'.
'OFFD2H'.
'OFFD3H',
'OFFDFH',
'OFFDAH'.
'OFFDBH',
'OFFD9H',
'OFFDBH'.
'OFFDCH'.
'OFFD4H',
'OFFD~H'.
'OFFD6H',
'OFFD7H',
/* 8237 BIT ASBIGNMENTS */
CHO_SEL
CHI_BEL
CH2_SEL
CH3_SEL
WRITE_XFER
READ_X FER
DEMAND_MODE
SINgLE_MODE
BLOCK_MODE
BET_MASK
'DOH'.
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT,
LIT
'OlH',
'02H'.
'03H'.
'04H',
'OBH',
'DOH',
'4OH',
'BOH',
'04H',
.E.JECT
/* 8259 PORTB */
STATUB_PDLL_~9
ICWl_~9
DCWl_~9
DCW2_~9
DCW3_~9
ICW:I_~9
ICW3_~9
ICW4_~9
LIT
LIT
LIT
LIT
LIT
LIT
'OFFEOH'.
'OFFEOH'.
'OFFEIH'.
'OFFEOH',
'OFFEOH',
'OFFEIH'.
LIT
LIT
'OFFE1H',
'OFFEIH'.
/* INTERRUPT BERVICE ROUTINE *1
PROCEDURE
3
4
~
2
2
"
:I
INTERRUPT 32.
OUTPUT (BINGLE_MABK_37)-40H.
WAIT-FALSE.
END.
296166-4
12-66
intel .
8044 APPLICATION EXAMPLES
Table 2. PL/M·86 Compiler RUPI/8088 Interface Example (Continued)
7
DISABLE.·
,. INITIALIZE S237 .,
S
'I
10
II
12
13
14
15
16
17
IS
1'1
20
:Z1
DUTPUTCMASTER_CLEAR_37)
OUTPUTCCOMMAND_37)
OUTPUTCALL_MASK_37)
OUTPUT CMODE_REg_37)
OUTPUTCMODE_REg_37)
OUTPUT CCLEAR_BYTE_PTR_37)
OUTPUTCCHO_ADDR)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
OUTPUTCCHO~DDR)
OUTPUTCCHO_COUNT)
OUTPUTCCHO_COUNT)
OUTPUTCCHI_ADDR)
OUTPUTCCHI_ADDR)
OUTPUTCCHI_COUNT)
OUTPUTCCHI_COUNT)
-0.
-04OHJ
-OFH.
-CSINgLEJ'IODE OR WRITE_XFER OR CHO_SEL).
-CSINgLE_MODE OR READ_XFER OR CHI_SEL).
-D.
-OOH.
-4OH.
-64.
-00;
-40H.
-4OH.
-641
-00,
,. INITIALIZE S25'1 .,
OUTPUT< ICWI_5'1)
-13H. '.SINgLE MODE, EDgE TRiggERED
INPUT, BOB6 INTERRUPT TYPE.'
-2OH. '.INTERRUPT TYPE 32.'
-03H. '.AUTO-EOI.'
-OFEH. '*ENABLE INTERRUPT LEVEL 0.,
DUTPUT< ICW2_5'1)
OUTPUT< ICW4_5'1)
OUTPUTCOCWI_5'1)
23
24
25
_E.JECT
CALL SET_INTERRUPT
27
2S
2'1
30
C32,OFF_RECV~MA).
I
2
DO
I- I TO 64. ,. FILL UP THE
I )-1.
OUTPUTIALL_MASK_37)-OFCH.
32
ENABLE.
33
34
35
2
36
37
2
XMIT~UFFER
WITH DATA .,
XMn~UFFERI
END• .
2
31
38
'.LOAD INTERRUPT VECTOR LOCATION.'
XMIT-,UFFERIO)-64. '.THE FIRST BYTE IN THE BLOCK OF DATA IS THE NUMBER
OF BYTES TO BE TRANSFERED. NOT INCLUDINg THE FIRST BYTE.'
WAn-TRUE.
DO WHILE WAIT.
END.
I
I
'.ENABLE CHANNEL I AND 2 .,
,. A BLOCK OF DATA WILL BE TRANSFERRED TO THE RUPI.
WHEN THE RUPI RECEIVES A BLOCK OF DATA IT WILL
SEND IT TO THE BOB8 HEMORY AND INTERRUPT THE B0B8.
THE INTERRUPT· SERVICE ROUTINE WILL SHUT OFF THE DMA
CONTROLLER AND SET 'WAIT' FALSE .,
DD WHILE I.
END.
I
ENO.
MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
124 LINES READ
o PROQRAM WARN I NOS
o PROgRAM ERRORS
-
00D7H
OOOOH
00B2H
OOIEH
215D
OD
130D
30D
END DF PL'M-B6 COMPILATION
296166-5
12-67
II
8044 APPLICATION E:XAMPLES
A HIGH PERFORMANCE NETWORK
USING THE 8044
2.0 INTRODUCTION
This section describes the design of an SOLC data link
using the 8044 (RUPI) to implement a primary station
and a secondary station. The design was implemented
and tested. The following discussion assumes that the
reader understands the 8044 and SOLC. This section is
divided into two parts. First the data link design example is discussed. Second the software modules used to
implement the data link are described. To help the
reader understand the discussion of the software, flow
charts and software listings are displayed in Appendix
A and Appendix B, respectively.
APPLICATION DESCRIPTION
This particular data link design example uses a two
wire half-duplex multidrop topology as shown in Figure 4. In an SOLC multidrop topology the primary
station communicates with each secondary station. The
secondary stations communicate only to the primary.
Because of this hierarchial architecture, the logical topology for an SOLC multidrop is a star as shown in
Figure 5. Although the physical topology of this data
link is multidrop, the easiest way to understand the
information flow is to think of the logical (star) topology. The term data link in this case refers to the logical
communication pathways between the primary station
and the secondary stations. The data links are shown in
Figure 5 as two way arrows.
The application example uses dumb async terminals to
interface to the SOLC network. Each secondary station
has an async terminal connected to it. The secondary
stations are in effect protocol converters which allows
any async terminal to communicate with any other
async terminal on the network. The secondary stations
use an 8044 with a UART to convert SOLC to async.
Figure 6 displays a block diagram of the data link. The
primary station, controls the data link. In addition to
data link control the primary provides a higher level
layer which is a path control function or networking
layer. The primary serves as a message exchange or
switch. It receives information from one secondary station and retransmits it to another secondary station.
Thus a virtual end to end connection is made between
any two secondary stations on the network.
Three separate software modules were written for this
network. The first module is a Secondary Station Oriver (SSO) which provides an SOLC data link interface
and a user interface. This module is a general purpose
driver which requires application software to run it.
The user interface to the driver. provides four functions:
OPEN, CLOSE, TRANSMIT, and SIU_RECV. Using these four functions properly will allow any application software to communicate over this SOLC data link
without knowing the details of SOLC. The secondary
station driver uses the 8044's AUTO mode.
The second module is an example of application software which is linked to the secondary station driver.
This module drives the 8215A, buffers data, and interfaces with the secondary station driver's user interface.
The third module is a primary station, which is a standalone program (i.e., it is not linked to any other module). The primary station uses the 8044's NON-AUTO
or FLEXIBLE mode. In addition to controlling the
data link it acts as a message switch. Each time a secondary station transmits a frame, it places the destination address of the frame in the first byte of the information or I field. When the primary station receives a
frame, it removes the first byte in the I field and retransmits the frame to the secondary station whose ad. dress matches this byte.
This network provides two complete layers of the OSI
(Open Systems Interconnection) reference model: the
physical layer and the data link layer. The physical layer implementation uses the RS-422 electrical interface.
The mechanical medium consists of ribbon cable and
connectors. The data link layer is defined by SOLC.
SOLC's use of acknowledgements and frame numbering guarantees that messages will be received in the
same order in which they were sent. It also guarantees
message integrity over the data link. However this network will not guarantee secondary to secondary message delivery, since there are acknowledgements between secondary stations.
2.1 Hardware
The schematic of the hardware is given in Figure 7. The
8251A is used as an async communications controller,
in support of the 8044. TxROY and RxROY on the
8251A are both tied to the two available external interrupts of the 8044 since the secondary station driver is
totally interrupt driven. The 8044 buffers the data and
some variables in a 2016 (2K x 8 static RAM). The
8254 programmable interval timer is employed as a
programmable baud rate generator and system clock
driver for the 8251A. The third output from the 8254
could be used as an external baud rate generator for the
8044. The 2732A shown in the diagram was not used
12-68
8044 APPLICATION EXAMPLES
since the software for both the primary and secondary
stations used far less than the 4K bytes provided on the
8744. For the async interface, the standard RS-232 mechanical and electrical interface was used. For the
SDLe channel, a standard two wire three state RS-422
driver is used. A DIP switch connected to one of the
available ports on the 8044 allows the baud rate, parity,
and stop bits to be changed on the async interface. The
primary station hardware does not use the USART,
8254, nor the RS-232 drivers.
2.2 SOLe Basic Repertoire
The SDLe commands and responses implemented in
the data link include the SDLe Basic Repertoire as
defined in the IBM SDLe General Information manual. Table 3 shows the commands and responses that the
primary and the secondary station in this data link design recognize and send.
PRIMARY
STATION
SECONDARY
STATION
SECONDARY
STATION
SECONDARY
STATION
296166-6
Figure 4. SOLC Multidrop Topology
SECONDARY
STATION
SECONDARY
STATION
PRIMARY
STATION
SECONDARY
STATION
SECONDARY
STATION
296166-7
Figure 5. SOLC Logical Topology
12-69
infel .
8044 APPLICATION EXAMPLES
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co
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Figure 6. Block Diagram of the Data Link Application Example
12-70
infel .
8044 APPLICATION EXAMPLES
B
I·
=
Figure 7. Schematic of Async/SDLC Secondary Station Protocol Converter
12-71
in1et.
8044 APPLICATION EXAMPLES
nal. The SSD is independent of the main application, it
just provides theSDLC communications. Existing 8051
applications could add high performance SDLC communications capability by linking the SSD to the existing software and providing additional software to be
able to communicate witl). the SSD.
Table 3. Data Link Commands and
Responses Implemented for This Design
Primary Station
Responses
Recognized
Commands
Sent
UA
OM
FRMR
'RD
SNRM
DISC
Supervisory
RR
RNR
RR
RNR
Information
I
I
Unnumbered
'.
DATA LINK INTERFACE AND USER
INTERFACE STATES
The SSD has two software interfaces: a data link interface and a user interface as shown in Figure 8. The data
link interface is the part of the software which controls
the SDLC communications. It· handles link access,
command recognition/response, acknowledgements,
and error recovery; The user interface .provides four
functions: OPEN, CLOSE, TRANSMIT, and SIU_
RECV. These are the only four functions which the
application software has to interface in order to communicate using SDLC. These four functions are common to many I/O drivers like floppy and hard disks,
keyboard/CRT, and async communication drivers.
Secondary Station
Commands
Recognized
Responses
Sent
SNRM
DISC
'TEST
UA
OM
FRMR
oRO
'TEST
RR
RNR
REJ
RR
RNR
I
I
Unnumbered
Supervisory
Information
The data link and the user interface each have their
own states. Each interface can only be in one state at
any time. The SSD uses the states of these two interfaces to help synchronize the application module to the
data link.
'not Included In the SDLe BasIc Repertoire
The term command specifically means all frames which
the primary station transmits and the secondary stations receive. Response refers to frames which the secondary stations transmit and the primary station receives.
NUMBER OF OUTSTANDING FRAMES
This particular data link design only allows one outstanding frame before it must receive an acknowledgement. Immediate acknowledgement allows the secondary station drivers to use the AUTO mode. In addition,
. Qne outstanding frame uses less memory for buffering,
and the software becomes easier to manage.
2.3 Secondary Station Driver using
AUTO Mode
The 8044 secondary station driver (SSD) was written as
a general purpose SDLC driver. It was written to be
linked to an application module. The application software implemenis the actual application in addition to
interfacing to the SSD. The main application could be,
a printer or plotter, a medical instrument, or a termi-
There are three states which the secondary station data
link interface can be iIi: Logical Disconnect State
(L~_S), Frame Reject State (FRMLS), and the
IDformation Transfer State (LTJ). The LogIcal
Disconnect State is when a station is physically connected to the channel but either the primary or secondary have not agreed to enter the Information Transfer
State. Both the primary and the secondary stations synchronize to enter into the Information Transfer State.
Only when the secondary station is in the LT_S is it
able to transfer data or information to the primary. The Frame Reject State (FRMR-S) indicates that the secondary station has lost software synchronization with
the primary or encountered· some kind of error condition. When the secondary station is in the FRMLS,
the primary station must reset the secondary to resynchronize.
The user interface has two states, open or closed. In the
closed state, the user program does not want to communicate over the network. The communications channel is closed and not available for. use. The secondary
station tells the primary this by responding to all commands with DM. The primary continues to poll the
secondary in case it wants to enter the I_T_S state.
When the user program begins communication over the
data link it goes into the open state. It does this by
calling the OPEN procedure. When the user interface is
in the open state it may transfer information to the
primary.
12-72
intel®
8044 APPLICATION EXAMPLES
SECONDARY STATION
SECONDARY
STATION
DRIVER
MODULE
APPLICATION
MODULE
DATA
LINK
INTERFACE
SSD
INTERFACE
"
1I
t
V
SSD
INTERFACE
PROCEDURES
USER
INTERFACE
USER STATES
1. OPEN
2. CLOSED
DATA LINK
STATES
1. LOGICAL
DISCONNECT
STATE
2. INFORMATION
TRANSFER
STATE
3. FRAME
REJECT
STATE
...J
W
Z
Z
c(
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OPEN
CLOSE
TRANSMIT
SIU RECV
o
...J
c(
o
iii
>-
...
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296166-10
Figure 8. Secondary Station Software Modules
12-73
infel .
8044 APPLICATION EXAMPLES
-
SECONDARY STATION COMMANDS,
RESPONSES AND STATE TRANSITIONS
Table 4 shows the commands which the secondary station recognizes and the responses it generates. The first
row in Table 4 displays commands the secondary station recognizes and each column shows the potential
responses with respect to secondary station. For example, if the secondary is in the Logical Disconnect State
it will only respond with DM, unless it receives a
SNRM command and the user state is open. If this is
the case, then the response will be UA and the secondary station will move into the I_T_S.
There is a buffer overrun.
The Nr that was received from the primary station
is invalid.
The secondary station cannot leave the FRMLS until
it receives a SNRM or a DISC command.
SOFTWARE DESCRIPTION OF THE SSD
To aid in following the description of the software, the
reader may either look at the flow charts which are
given for each procedure, or read the PL/M-SI listing
provided in Appendix A.
Figure 9 shows the state diagram of the secondary
station. When power is first applied to the secondary
station, it goes into the Logical Disconnect 'State. As
mentioned above, the I_T_S is entered when the secondary station receives a SNRM command and the
user state is open. The secondary responds with UA to
let the primary know that it has accepted the SNRM
and is entering the I_T_S. The I_T_S can go into
either the L_D_S or the FRMLS. The I_T_S
goes into the L_D_S if the primary sends the secondary DISC. The secondary has to respond with UA, and
then goes into the L_D_S. If the user interface
changes from open to close state, then the secondary
sends RD. This causes the primary to send a DISC.
A block diagram of the software structure of the SSD is
given in Figure 10. A complete module is identified by
the dotted box, and a procedure is identified by the
solid box. Therefore the SIU_RECV procedure is not
included in the SSD module, it exists in the application
software. Two or more procedures connected by a solid
line means the procedure above calls the procedure below. Transmit, Power_on_D, Close, and Open are all
called by· the application software. Procedures without
any solid lines connected above are interrupt procedures. The only interrupt procedure in the SSD module
is the SID_INT.
The FRMR_S is entered when a secondary station is
in the 1_T_S and either one of the following conditions occurs.
- A command can not be recognized by the second- '
ary station.
The entire SSD module is interrupt driven. Its design
allows the application program to handle real time
events or just dedicate more CPU time to the application program. The SIU_INT is the only interrupt procedure in the SSD. It is automatically entered when an
SIU interrupt occurs. This particular interrupt can be
the lowest priority interrupt in the system.
Table 4. Secondary Station Responses to Primary Station Commands
Data Link
States
Information
Transfer State
PrImary Statlon-Commands
I
I
RR
RNR
RD
FRMR
RR
I
RR
RNR
RD
FRMR,
RNR
I
RR
RNR
RD
FRMR
SNRM
DISC
RD
UA
TEST
RD
UA
Test
Logical
Disconnect State
OM
OM
OM
OM
OM
OM
UA
Frame
Reject State
FRMR
FRMR
FRMR
FRMR
UA
12-74
UA
intel~
8044 APPLICATION EXAMPLES
DISC
UA
II
~~~ER
____________~
296166-11
Figure 9. State Diagram of Secondary Station
12·75
int'et
8044 APPLICATION EXAMPLES
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Figure 10. Secondary Station Driver
12-76
zw
...o
8044 APPLICATION EXAMPLES
SSD INITIALIZATION
Upon reset the-application software is entered first. The
application software initializes its own variables then
calls Power_On_D which is the SSD's initialization
routine. The SSD's initialization sets up the transmit
and receive data butTer pointers (TBS and RBS), the
receive butTer length (RBL), and loads the State variables. The STATION_STATE begins in the L_D_S
state, and the USE~STATE begins in the closed
state. Finally Power_On_D initializes XMIT_
BUFFE~MPTY which is a bit flag. This flag
serves as a semaphore between the SSD and the application software to indicate the status of the on chip
transmit butTer. The SSD does not set the station address. It is the application software's responsibility to
do this. After initialization, the SSD is read to respond
to all of the primary station commands. Each time a
frame is received with a matching station address and a
good CRC, the SIU_INT procedure is entered.
reasons for the SIU to automatically leave the AUTO
mode. The following is a list of these reasons, and the
responses given by the SSD based on each reason.
1. The SIU has received a command field it does not
recognize.
Response: If the CPU recognizes the command, it
generates the appropriate response. If neither the
SIU nor the CPU recognize the command, then a
FRMR response is sent.
2. The SIU has received a Sequence Error Sent
(SES= 1 in NSNR register). Nr(P)*Ns(S)+ I, and
Nr(P) * Ns(S).
Response: Send FRMR.
3. A butTer overrun has occurred. BOV = 1 in STS register.
Response: Send FRMR.
4. An I frame with data was received while RPB = 1.
Response: Go back into AUTO mode and send an
AUTO mode response
SIU_INT PROCEDURE
The first thing the SIU~NT procedure clears is the
serial interrupt_bit (SI) in the STS register. If the
SIU~NT procedure returns with this bit set, another
SI interrupt will occur.
The SIU_INT procedure is branches three independent cases. The first case is entered if the STATION_
STATE is not in the I_T_S. If this is true, then the
SIU is not in the AUTO mode, and the CPU will have
to respond to the primary on its own. (Remember that
the AUTO mode is entered when the STATION_
STATE enters into I_T_S.) If the STATION_
STATE is in the 1_TJ , then either the SIU has just
left the AUTO mode, or is still in the AUTO mode.
This is the second and third case, respectively.
In the first case, if the STATIONJTATE is not in
the I_TJ, then it must be in either the L_D_S or
the FRM~S. In either case a separate procedure is
called based on which state the station is in. The IlLDisconnectJtate procedure sends to the primary a
DM response, unless it received a SNRM command
and the USERJTATE. equals open. In that case the
SIU sends a UAand enters into the I_T_S. The IlLFRM~State procedure will send the primary the
FRMR response unless it received either a DISC or an
SNRM. If the primary's command was a DISC, then
the secondary will send a UA and enter into the L_
D_S. If the primary's command was a SNRM, then
the secondary will send a UA, enter into the I_T_S,
and clear NSNR register.
For the second case, if the STATION_STATE is in
the LTJ but the SIU left the AUTO mode, then the
CPU must determine why the AUTO mode was exited,
and generate a response to the primary. There are four
In addition to the above reasons, there is one condition
where the CPU forces the SIU out of the AUTO mode.
This is discussed in the SSD's User Interface Procedures section in the CLOSED procedure description
Finally, case three is when the STATION_STATE is
in. the I_T_S and the AUTO mode. The CPU first
looks at the TBF bit. If this bit is 0 then the interrupt
may have been caused by a frame which was transmitted and acknowledged. Therefore the XMITJUFFE~EMPTY flag is set again, indicating that the application software can transmit another frame.
The other reason this section of code could be entered
is if a valid I frame was received. When a good I frame
is received the RBE bit equals O. This means that the
receiver is disabled. Ifthe primary were to poll the 8044
while RBE=O, it would time out since no response
would be given. Time outs reduce network throughput.
To improve network performance, the CPU first sets
RBP, then sets RBE. Now when the primary polls the
8044 an immediate RNR response is given. At this
point the SSD calls the application software procedure
SIU_RECV and passes the length of the data as a
parameter. The SIU~CV procedure reads the data
out of the receive butTer then returns to the SSD module. Now that the receive information has been transferred, RBP can be cleared.
COMMAND_DECODE PROCEDURE
The CommanLDecode procedure is called from the
SIU_INT procedure when the STATION_STATE
= I T S and the SIU left the AUTO mode as a
result of not being able to recognize the receive control
byte. Commands which the SIU AUTO mode does not
12-77
•
infel .
8044 APPLICATION EXAMPLES
C·FIELD OF THE REJECTED COMMAND, AS RECEIVED
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INVALID OR NONIMPLEMENTED COMMAND
296166-13
Figure 11. Information Field of the FRMR Response, as Transmitted
recognize are handled here. The commands recognized
in this procedure are: SNRM, DISC, and TEST. Any
other command received will generate a Frame Reject
, with the nonimplemented command bit set in the third
data byte of the FRMR frame. Any additional unnum·
bered frame commands which the secondary station is
going to implement, should be implemented in this pro·
cedure.
IF an SNRM is received the command_decode proce·
dure calls the SNR~esponse procedure. The
SNR~Response procedure sets the STATION_
STATE = I_T_S, clears the NSNR register and responds with a UA frame. If a DISC is received, the
command_decode procedure sets the STATION,,STATE = L_D_S, and responds with a UA frame.
When a TEST frame is received, and there is no buffer
overrun, the command_decode procedure responds
with a TEST frame retransmitting the same data it reo
ceived. However if a TEST frame is received and there
is a buffer overrun, then a TEST frame will be sent
without any data, instead of a FRMR with the buffer
overrun bit set.
field. Figure 11 displays the format for'the three data
bytes in the I field of a FRMR response. The XMIT_
FRMR procedure sets up the Frame Reject response
frame based on the parameter REASON which is
passed to it. Each place in the SSD code that calls the
XMIT_FRMR procedure, passes the REASON that
this procedure was called, which in tum is communicated to the primary station. The XMIT~R procedure uses three bytes of internal RAM which it initializes for the correct response. The TBS and TBL registers are then changed to point to the FRMR buffer so
that when a response is sent these three bytes will be
included mthe I field.
The INJRMR-STATE procedw:e is called by the
SIU_INT procedure when the STATIONJTATE
already is in the FRMR state and a response is required. The IN_FRMR-STATE procedure will only
allow two commands to remove the secondary station
from the FRMR state: SNRM and DISC. Any other
command which is received while in the FRMR state
will result in a FRMR response frame.
XMIT_UNNUMBERED PROCEDURE
FRAME REJECT PROCEDURES
There are two procedures which handle the FRMR,
state: XMIT_FRMR and IN~R-STATE.
XMITJRMR is entered when the secondary station
first goes into the FRMR state. The frame reject reo
sponse frame contains the FRMR response in the com·
mand field plus three additional data bytes in the I
This is a general purpose transmit procedure, used only
in the FLEXIBLE mode, which sends unnumbered responses to the primary. It accepts the control byte as a
parameter, and also expects the TBL register to be set
before the procedure is called. This procedure waits until the frame has been transmitted before returning. If
12-78
8044 APPLICATION EXAMPLES
this procedure returned before the transmit interrupt
was generated, the SIU_INT routine would be entered. The SIU_INT routine would not be able to distinguish this condition.
SSD's User Interface Procedures-OPEN, CLOSE,
TRANSMIT, SIU_RECV-are discussed in the following section.
The OPEN procedure is the simplest of all, it changes
the USER_STATE to OPEN_S then returns. This
lets the SSD know that the user wants to open the
channel for communications. When the SSD receives a
SNRM command, it checks the USER_STATE. If the
USER_ST ATE is open, then the SSD will respond
with a UA, and the STATION_STATE enters the
I_T_S.
The CLOSE procedure is also simple, it changes the
USER_STATE to CLOSED_S and sets the AM bit
to O. Note that when the CPU sets the AM bit to 0 it
puts the SIU out of the AUTO mode. This event is
asynchronous to the events on the network. As a result
an I frame can be lost. This is what can happen.
1. AM is set to 0 by the CLOSE Procedure.
2. An I frame is received and an SI interrupt occurs.
3. The SIU_INT procedure enters case 2 (STATION_STATE = I_T_S, and AM = 0).
4. Case 2 detects that the USER_STATE
CLOSED_S, sends an RD response and ignores the
fact that an I frame was received.
Therefore it is advised to never call the CLOSE procedure or take the SIU out of the AUTO mode when it is
receiving I frames or an I frame will be lost.
For both the TRANSMIT and SIU_RECV procedures, it is the application software's job to put data
into the transmit buffer, and take data out of the receive buffer. The SSD does not transfer data in or out
of its transmit or receive buffers because it does not
know what kind of buffering the application software is
implementing. What the SSD does do is notify the application software when the transmit buffer is empty,
XMIT_BUFFEIL-EMPTY = I, and when the receive buffer is full.
One of the functions that the SSD performs to synchronize the application software to the SDLC data link.
However some of the synchronization must also be
done by the application software. Remember that the
SSD does not want to hang up the application software
waiting for some event to occur on the SDLC data link,
therefore the SSD always returns to the application
software as soon as possible.
application software thinks that the SDLC channel is
now open and it can transmit. This is not the case'. For
the channel to be open, the SSD must receive an
SNRM from the primary and respond with a UA.
However, the SSD does not want to hang up the application software waiting for an SNRM from the primary
before returning from the OPEN procedure. When the
TRANSMIT procedure is called, the SSD expects the
STATION_STATE to be in the I_T_S. If it isn't,
the SSD refuses to transmit the data. The TRANSMIT
procedure first checks to see if the USER_STATE is
open. If not, the USER_STATE_CLOSED parameter is passed back to the application module. The next
thing TRANSMIT checks is the STATION_STATE.
If this is not open, then TRANSMIT passes back
LINK_DISCONNECTED. This means that the
USER_STATE is open, but the SSD hasn't received
an SNRM command from the primary yet. Therefore,
the application software should wait awhile and try
again. Based on network performance, one knows the
maximum amount of time it will take for a station to be
polled. If the application software waits this length of
time and tries again but still gets a LINK_DISCONNECTED parameter passed back, higher level recovery
must be implemented.
Before loading the transmit buffer and calling the
TRANSMIT procedure, the application software must
check to see that XMIT_BUFFER_EMPTY = 1.
This flag tells the application software that it can write
new data into the transmit buffer and call the TRANSMIT procedure. After the application software has verified that XMIT_BUFFER_EMPTY = 1, it fills the
transmit buffer with the data and calls the TRANSMIT procedure passing the length of the buffer as a
parameter. The TRANSMIT procedure checks for
three reasons why it might not be able to transmit the
frame. If any of these three reasons are true, the
TRANSMIT procedure returns a parameter explaining
why it couldn't send the frame. If the application software receives one of these responses, it must rectify the
problem and try again. Assuming these three conditions are false, then the SSD clears XMIT_BUFFER_EMPTY, attempts to send the data and returns
the parameter DATA_TRANSMITTED. XMIT_
BUFFER_EMPTY will not be set to 1 again until the
data has been transmitted and acknowledged.
The SIU_RECV procedure must be incorporated into
the application software module. When a valid I frame
is received by the SIU, it calls the SIU_RECV procedure and passes the length of the received data as a
parameter. The SIU_RECV procedure must remove
all of the data from the receive buffer before returning
to the SIU_INT procedure.
For example, when the application software calls the
OPEN procedure, the SSD returns immediately. The
12-79
intel~
8044 APPLICATION EXAMPLES
LINKING UP TO THE SSD
Figure 12 shows the necessary parts to include in a
PL/M-51 application program that will be linked to the
SSD module. RL51 is used to link and locate theSSD
and application modules. The command line used to do
this is:
$registerbank(O)
user$mod: do;
$include (reg44.dcl)
declare
lit
literally 'literally',
buffer_length
lit
'60',
siu_xmit_buffer
(buffer_length)
byte
external idata,
siu_recY_buffer
(buffer_length)
byte
external,
xmit_buffer_empty bit
external;
external procedures
external;
close: procedure
end close;
external using 1;
open: procedure
end open;
external using 1;
(1)8044 Secondary Station
/
transmit: procedure
(xmit_buffer_length) byte
declare xmit_buffer_length
end transmit;
'0
local procedures
After the secondary station powers up, it enters the
'terminal mode', which accepts data from the terminal.
However, before any data is sent, the user must configure the station. The station address and destination
address must be set, and the station must be placed
online. To configure the station the ESC character is
entered at the terminal which puts the protocol converter into the 'configure mode'. Figure 13 shows the
menu which appears on the terminal screen.
0'
power_on_d: procedure
end power_on_d;
2.4 Application Module; ASYNC to
SOLC Protocol Converter
One of the purposes of this application module is to
demonstrate how to interface software to the SSD. Another purpose is to implement and test a practical application. This application software performs I/O with an
async terminal through a USART, buffers data, and
also performs I/O with the SSD. In addition, it allows
the user on the async terminal to: set the station address, set the destination address, and go online and
offline. Setting the station address sets the byte in the
STAD register. The destination address is the first byte
in the I field. Going online or offline results in either
calling the OPEN or CLOSE procedure respectively.
RL5l SSD.obj,filename.obj,PLM5l.LIB TO
filename & RAMSIZE(192)
'0
The SSD module uses the $REGISTERBANK(1) attribute. Some procedures are modified with the USING
attribute based on the register bank level of the calling
procedure.
I2345-
external;
byte;
0'
siu_recy: procedure (length)
public
length byte,
declare
Set the Station Address
Set the Destination Address
Go Online
Go Offline
Return to terminal mode
Enter option _
using 1;
Figure 13. Menu for the Protocol Converter
•
•
•
In the terminal mode data is buffered up in the secondary station. A Line Feed character 'LF' tells the secondary station to send an I frame. If more than 60 bytes
are buffered in the secondary station when a 'LF' is
received, the applications software packetizes the data
into 60 bytes or less per frame. If a LF is entered when
the station is offline, an error message comes on the
screen which says 'Unable to Get Online'.
end siu_recy;
Figure 12. Applications Module Link Information
PL'M-S1 AND REGISTER BANKS
The 8044 has four register banks. PL/M-51 assumes
that an interrupt procedure never uses the same bank as
the procedure it interrupts. The USING attribute of a
procedure, or the $REGISTERBANK control, can be
used to ensure that.
The secondary station also does error checking on the
async interface for Parity, Framing Error, and Overrun
Error. If one of these errors are detected, an error message is displayed on the terminal screen.
12-80
8044 APPLICATION EXAMPLES
MULTIDROP
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12-81
intel .
8044 APPLICATION EXAMPLES
BUFFERING
There are two separate buffers in the application module: a transmit buffer and a receive buffer. The transmit
buffer receives data from the USART, and sends data
to the SSD. The receive buffer receives data from the
SSD, and transmits data to the USART. Each buffer is
a 256 byte software FIFO. If the transmit FIFO becomes full and no 'LF' character is received, the secondary station automatically begins sending the data.
In addition, the application modules will shut off the
terminal's transmitter using CTS until the FIFO has
been partially emptied. A block diagram of the buffering for the protocol converter is given in Figure 14.
APPLICATION MODULE SOFTWARE
A block diagram of the application module software is
giveh in Figure 15. There are three interrupt routines in
this module: USART_RECV_INT, USART_
XMIT_INT, and TIMER-OJNT. The first two are
for servicing the USART. TIMER-O_INT is used if
the TRANSMIT procedure in the SSD is called and
does not return with the DATA-TRANSMITTED
parameter. TIMER-O_INT employs Timer 0 to wait
a finite amount of time before trying to transmit again.
The highest priority interrupt is USART~CV_
INT. The main program and all the procedures it calls
use register bank 0, USART_XMITJNT and TIMER-O_INT and FIFO-R-OUT use bank 1, while
USART-.RECVJNT and all the procedures it calls
use register bank 2.
POWER_ON PROCEDURE
The Power_On procedure initializes all of the chips in
the system including the 8044. The 8044 is initialized to
use the on-chip DPLL with NRZI coding, PreFrame
Sync, and Timer 1 auto reload at a baud rate of
62.5 Kbps. The 8254 and the 825IA are initialized next
based on the DIP switch values attached to port 1 on
the 8044. Variables and pointers are initialized, then the
-SSD's Power-Up Procedure, Power_OD-D, is called.
Finally, the interrupt system is enabled and the main
program is _entered.
MAIN PROGRAM
The main program is a simple loop which waits for a
frame transmit command. A frame transmit command
is indicated when the variable SEND~ATA is greater than O. The value of SEND_DATA equals the
number of'LF' characters in the transmit FIFO, hence
it also indicates the number of frames pending transmission. Each time a frame is sent, SEND~ATA is
decremented by one. Thus when SEND~ATA is
greater than 0, the main program falls down into the
next loop which polls the XMITJUFFER-EMPTY bit. When XMITJUFFER-EMPTY equals I,
the SIU--"MITJUFFER can be loaded. The first
byte in the buffer is loaded with the destination address
while the rest of the buffer is loaded with the data.
Bytes are removed from the transmit FIFO and placed
into the SIU--"MITJUFFER until one of three
things happen: 1. a 'LF' character is read out of the
FIFO, 2. the number of bytes loaded equals the size of
the SIU--"MITJUFFER, or 3. the transmit FIFO
is empty.
After the SIU--"MIT_BUFFER is filled, the SSD
TRANSMIT procedure is called and the results from
the procedure are checked. Any result other than
DATA-TRANSMITTED will result in several retries
within a finite amount of time. If all the retries fail,
then the LIN~ISC procedure is called which sends
a message to the terminal, 'Unable to Get Online'.
USART_RECV_INT PROCEDURE
When the 825IA receives a character, the RxRDY pin
on the 825IA is activated, and this interrupt procedure
is entered. The routine reads the USART status register
to .determine if there are any errors in the character
received. If there are; the character is discarded and the
ERROR procedure is called which prints the type of
error on the screen. If there are no errors, the received
character is checked to see if it's an ESC. If it is an
ESC, the MENU procedure is called which allows the
user to'change the configuration. If neither one of these
two conditions exists, the received character is inserted
into the transmit FIFO. The received character mayor
. may not be echoed back to the terminal based on the
dip switch settings.
TRANSMIT FIFO
The transmit FIFO consists of two procedures: FIFO_
TJN and FIFO_T_OUT. FlFO_TJN inserts a
character into the FIFO, and FIFO_T_OUT removes a character from the FIFO. The FIFO itself is
an array of 256 bytes called FlFO_T. There are two
pointers used as indexes in the array to address the
characters: IN~T and OUTJTR-T. IN_
PTR-T points to the location in the array which will
store the next byte of data inserted. OUTJTR-T
points to the next byte of data removed from the array.
Both INJTR-T and OUTJTR-T are declared
as bytes. The FlFO_TJN procedure receives a character from the USART~CV_INT procedure and
stores it in the array location pointed to by INJTRT, then INJTR-T is incremented. Similarly, when
FIFO_T_OUT is called by the main program, to
load the SIU--"MITJUFFER, the byte in the array
12-82
_.
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intel~
8044 APPLICATION EXAMPLES
pointed to by OUT_PTR-T is read, then OUT_
PTR-T is incremented. Since IN_PTR_T and
OUT_PTR_T are always incremented, they must be
able to roll over when they hit the top of the 256 byte
address space. This is done automatically by having
both IN_PTR_T and OUT_PTR_T declared as
bytes. Each character inserted into the transmit FIFO
is tested to see if it's a LF. If it is a LF, the variable
SEND_DATA is incremented, which lets the main
program know that it is time to send an I frame. Similarly each character removed from the FIFO is tested.
SEND_DATA is decremented for every LF character
removed from the FIFO.
stations and receives ·responses from them. The primary
station controls link access, link level error recovery,
and the flow of information. Secondaries can only
transmit when polled by the primary.
Most primary stations are either micro/minicomputers,
or front end processors to a mainframe computer. The
example primary station in this design is standalone. It
is possible for the 8044 to be used as an intelligent front
end processor for a microprocessor, implementing the
primary station functions. This latter type of design
would extensively off-load link control functions for the
microprocessor. The code listed in this paper can be
used as the basis for this primary station design. Additional software is required to interface to the microprocessor. A hardware design example for interfacing
the 8044 to a microprocessor can be found in the applications section of this handbook.
IN_PTR_T and OUT_PTR_T are also used to indicate how many bytes are in the FIFO, and whether it
is full or empty. When it character is placed into the
FIFO and IN_PTR_T is incremented, the FIFO is
full if IN-,-PTR-T equals OUT_PTR_T. When a
character is read from the FIFO and OUT_PTR-T
is incremented, the FIFO is empty if OUT_PTR_T
equals IN_PTR_T. If the FIFO is neither full nor
empty, then it is in use. A byte called BUFFER_
STATUS_T is used to indicate one of these three conditions. The application module uses the buffer status
information to control the flow of data into and out of
the FIFO. When the transmit FIFO is empty, the main
program must stop loading bytes into the SIU_
XMIT_BUFFER. Just before the FIFO is full, the
async input must be shut off using CTS. Also, if the
FIFO is full and SEND_DATA = 0, then SEND_
DATA must be incremented to automatically send the
data without an LF.
From the listing of the software it can be seen that the
variable NUMBER_OF_STATIONS is a literal declaration, which is 2 in this design example. There were
three stations tested on this data link, two secondaries
and one primary. Following the NUMBER-OF_
STATIONS declaration is a table, loaded into the object code file at compile time, which lists the addresses
of each secondary station on the network.
RECEIVE FIFO
REMOTE STATION DATABASE
The receive FIFO operates in a fashion similar to the
transmit FIFO. Data is inserted into the receive FIFO
from the SIU_RECV procedure. The SIU_RECV
procedure is called by the SIU_INT procedure when a
valid I frame is received. The SIU_RECV procedure
merely polls the receive FIFO status to see if it's full
before transferring each byte from the SIU_RECV_
BUFFER into the receive FIFO. If the receive FIFO is
full, the SIU_RECV procedure remains polling the
FIFO status until it can insert the rest of the data. In
the meantime, the SIU AUTO mode is responding to
all polls· from the primary with a RNR supervisory
frame. The USART_XMIT_INT interrupt procedure removes data from the receive FIFO and transmits it to the terminal. The USART transmit interrupt
remains enabled while the receive FIFO has data in it.
When the receive FIFO becomes empty, the USART
transmit interrupt is disabled.
The primary station keeps a record of each secondary
station on the network. This is called the Remote Station Database (RSD). The RSD in this software is an
array of structures, which can be found in the listing
and also in Figure 16. Each RSD stores the necessary
information about that secondary station.
2.5 Primary Station
The primary station is responsible for controlling the
data link. It issues commands to the secondary
The primary station must know the addresses of all the
stations which will be on the network. The software for
this primary needs to know this before it is compiled,
however a more flexible system would download these
parameters.
To add additional secondary stations to the network,
one simply adjusts the NUMBER-OF_STATIONS
declaration, and adds the additional addresses to the
SECONDARY_ADDRESSES table. The number of
RSDs is automatically allocated at compile time, and
the primary automatically polls each station whose address is in the SECONDARY_ADDRESSES table.
Memory for the RSDs resides in external RAM. Based
on memory requirements for each RSD, the maximum
number of stations can be easily buffered in external
RAM. (254 secondary stations is the maximum number
SDLC will address on the data link; i.e. 8-bit address,
FF H is the broadcast address, and 0 is the null address. Each RSD uses 70 bytes of RAM. 70 x 254
17,780.)
12-84
int'eL
8044 APPLICATION EXAMPLES
The station state, in the RSD structure, maintains the
status of the secondary. If this byte indicates that the
secondary is in the DISCONNECT_S, then the primary tries to put the station in the LT_S by sending
an SNRM. If the response is a UA then the station
state changes into the I_T_S. Any other frame received results in the station state remaining in the DISCONNECT_S. When the RSD indicates that the station state is in the I_T_S, the primary will send either
an I, RR, or RNR command, depending on the local
and remote buffer status. When the station state equals
GO_TO_DISC the primary will send a DISC command. If the response is a UA frame, the station state
will change to DISCONNECT_S, else the station
state will remain in GO_TO_DISC. The station state
is set to GO_TO~ISC when one of the following
responses occur:
1. A receive buffer overrun in the primary.
2. An I frame is received and Nr(P)
Ns(S).
3. An I frame or a Supervisory frame is received and
Ns(P) + 1 Nr(S) and Ns(P)
Nr(S).
4. A FRMR response is received.
5. An RD response is received.
6. An unknown response is received.
'*
'*
'*
The send count (Ns) and receive count (Nr) are also
maintained in the RSD. Each time an I frame is sent by
the primary and acknowledged by the secondary, Ns is
incremented. Nr is incremented each time a valid I
frame is received. BUFFE~STATUS indicates the
status of the secondary station's buffer. If an RR response is received, BUFFE~STATUS is set to
BUFFE~READY. If a RNR response is received,
BUFFE~STATUS is set to BUFFE~NOT_
READY.
BUFFERING
The buffering f9r the primary station is as follows:
within each RSD is a 64 byte array buffer which is
initially empty. When the primary receives an I frame,
it looks for a match between the first byte of the I frame
and the addresses of the secondaries on the network. If
a match exists, the primary places the data in the RSD
buffer of the destination station. The INFO_
LENGTH in the RSD indicates how many bytes are in
the buffer. If INFO_LENGTH equals 0, then the
buffer is empty. The primary can buffer only one I
frame per station. If a second I frame is received while
the addressed secondary's RSD buffer is full, the primary cannot receive any more I frames. At this point
the primary continues to poll the secondaries using
RNR supervisory frame.
.
PRIMARY STATION SOFTWARE
A block diagram of the primary station software is
shown in Figure 17. The primary station software consists of a main program, one interrupt routine, and several procedures. The POWE~ON procedure begins
by initializing the SIU's DMA and enabling the receiver. Then each RSD is initialized.. The DPLL and the
timers are set, and finally the TIMER interrupt is
enabled.
°
The main program consists of an iterative do loop within a do forever loop. The iterative do loop polls each
secondary station once through the do loop. The variable STATION~MBER is the counter for the iterative do statement which is also used as an index to the
array ofRSD structures. The primary station issues one
command and receives one response from every secondary station each time through the loop. The first statement in the loop loads the secondary station address,
indexed by STATION.-:.NUMBER into the array of
the RSD structures. Now when the primary sends a
command, it will have the secondary's address in the
address field of the frame. The automatic address recognition feature is used by the primary to recognize the
.
response from the secondary.
Next, the main program determines the secondary station's state. Based on this state, the primary knows
what command to send. If the station is in the DISCONNECT_S, the primary calls the SNR~P procedure to try and put the secondary in the I_TJ. If
the station state is in the GO_TO_DISC state, the
DISC_P is called to try and put the secondary in the
L_DJ. If the secondary is in neither one of the
above two states, then it is in the LT_So When the
secondary is in the I_TJ, the primary could send
one of three commands: I, RR, or RNR. If the RSD's
buffer has data in it, indicated by INFOJENGTH
being greater than zero, and the secondary's BUFFE~STATUS equals BUFFE~READY, then an I
frame will be sent. Else if RPB = 0, an RR supervisory
frame will be sent. If neither one of these cases is true,
then an RNR will be sent. The last statement in the
main program checks the RPB bit. If set to one, the
BUFFE~TRANSFER procedure is called, which
transfers the data from the SIU receive buffer to the
appropriate RSD buffer.
12-85
intel·
8044 APPLICATION EXAMPLES
ASD
maximum frame length time comes from the fact the
8044 does not generate an interrupt from a received
frame until it has been completely received, and the
CRC is verified as correct. This means that the timeout is bit rate dependent.
'STATION-ADDRESS
STATION-STATE
NS
NR
BUFFER-STATUS
Ns AND Nr CHECK PROCEDURES
INFO-LENGTH
DATA (0)
Each time an I frame or supervisory frame is received,
the Nr field in the control byte must be checked. Since
this data link only allows one outstanding frame, a valid Nr would satisfy either one of two equations;
Ns(P) + 1 = Nr(S) the I frame previously sent by the
primary. is acknowledged, Ns(P) = Nr(S) the I frame
previously sent is not acknowledged. If either one of
these two cases is true, the CHEC~NR procedure
returns a parameter of TRUE; otherwise a FALSE parameter is returned. If an acknowledgement is received,
the Ns byte in the RSD structure is incremented, and
the Information buffer may be cleared. Otherwise the
. information buffer remains full.
DATA (63)
Figure 16. Remote Station Database Structure
RECEIVE TIME OUT
Each time a frame is transmitted, the primary sets a
receive time out timer; Timer O. If a response is not
received within a certain time, the primary returns to
the main program and continues polling the rest of the
stations. The minimum length of time the primary
should wait for a response can be calculated as the sum
of the following parameters.
1. Propagation time to the secondary station
2. Clear-to-send at the secondary station's DCE
3. Appropriate time for secondary station processing
4. Propagation time from the secondary station
5. Maximum frame length time
The clear-to-send time and the propagation time are
negligible for a local network at low bit rates. However,
the turnaround time and the maximum frame length
time are significant factors. Using the 8044 secondaries
in the AUTO mode minimizes turnaround time. The
When an I frame is received, the Ns field has to be
checked also. If Nr(P) = Ns(S), then the procedure
returns TRUE, otherwise a FALSE is returned.
RECEIVE PROCEDURE
The receive procedure is called when a supervisory or
information frame is sent, and a response is received
before the time-out period. The RECEIVE procedure
can be broken down into three parts. The first part is
entered if an I frame is received. When an I frame is
received, Ns, Nr and buffer overrun are checked. If
there is a buffer overrun, or there is an error in either
Ns or Nr, then the station state is set to GO_TO_
DISC. Otherwise Nr in the RSD is incremented, the
receive field length is saved, and the RPS. bit is set. By
incrementing the Nr field, the I frame just received is
acknowledged the next time the primary polls the secondary with an I frame or a supervisory frame. Setting
RBP protects the received data, and also tells the main
program that there is data to transfer to one of the RSD
buffers.
12-86
intele
8044 APPLICATION EXAMPLES
MAIN PROGRAM
BUFFER
TRANSFER
ITiMER _.0 _INT
I
296166-16
Figure 17. Block Diagram of Primary Station Software Structure
If a supervisory frame is received, the Nr field is
checked. If a FALSE is returned, then the station state
is set to GO_TO_DISC.lfthe supervisory frame received was an RNR, buffer status is set to not ready. If
the response is not an I frame, nor a supervisory frame,
then it must be an Unnumbered frame.
The only Unnumbered frames the primary recognizes
are UA, DM, and FRMR. In any event, the station
state is set to GO_TO~ISC. However, if the frame
received is a FRMR, Nr in the second data byte of the I
field is checked to see if the secondary acknowledged an
I frame received before it went into the FRMR state. If
this is not done and the secondary acknowledged an I
frame which the primary did not recognize, the primary transmits the I frame when the secondary returns
to the LT_S. In this case, the secondary would receive duplicate I frames.
12-87
II
8044 APPLICATION EXAMPLES
APPENDIX A
8044 SOFTWARE FLOWCHARTS
'POWER·ON·D PROCEDURE
USER-5TATE
STATION·STATION
=
CLOSED·S
= DISCONNECT.S
TBS
= SIU·XMIT·BUFFER STARTING ADDRESS
RBS
= SIU·RECV·BUFFER STARTING ADDRESS
RBL
= BUFFER LENGTH'
ENABLE SIU RECEIVER: RBE
XMIT·BUFFER·EMPTY
=,
=1
RETURN
296166-17
CLOSE PROCEDURE
AM -0
RETURN
OPEN PROCEDURE
RETURN
296166-18
Figure 18. Secondary Station Driver Flow Chart
12-88
intel$
8044 APPLICATION EXAMPLES
XMIT-UNNUMBERED PROCEDURE
II
296166-19
TRANSMIT PROCEDURE
STATUS = USER-STATE-ClOSE
LINK
STATUS ~
DISCONNECTED
=
STATUS
?VERFlOW
XMIT-BUFFER-EMPTY = 0
TBl
= XMIT-BUFFER-lENGTH
I-FRAME-LENGTH = XMIT-BUFFER-lENGTH
STATUS = DATA-TRANSMITTED
RETURN STATUS
296166-20
Figure 19_ Secondary Station Driver Flow Chart
12-89
intel .
8044 APPLICATION EXAMPLES
XMIT-FRMR PROCEDURE
FRMR-BUFFER (2)
STATION-STATE
= REASON
=
FRMR-S
N
y
SEND FRMR
FRAME
296166-21
Figure 20. Secondary Station Driver Flow Chart
12-90
intel..
8044 APPLICATION EXAMPLES
IN-DISCONNECT-STATE PROCEDURE
N
296166-22
SNRM-RESPONSE PROCEDURE
•
296166-23
Figure 21. Secondary Station Driver Flow Chart
12-91
intel"
8044 APPLICATION EXAMPLES
IN-FRMR-STATE PROCEDURE
y
y
296166-24
Figure 22. Secondary Station Driver Flow Chart
12-92
8044 APPLICATION EXAMPLES
COMMAND DECODE PROCEDURE
•
296166-25
Figure 23. Secondary Station Driver Flow Chart
12-93
l
SIU·INT PROCEDURE
~
-y L
N
:!!
c
..
CD
y
CD
~
UJ
CD
n
0
'"cO
--
~
~
):0
XMIT·BUFFER·EMPTY
=1
a.
III
..... '<
UJ
0
y
::J
..
QI
CALL COMMAND-DECODE
I\)
'V
'V
r-
CALL XMIT·UNNUMBERED
(REQ.DISC)
(;
):0
N
-I
(5
III
"'" c::Ji"
Z
m
CALL XMIT·FRMR
><
):0
C
:1
.
<
CD
i:
'V
rm
:!!
0
:e
(IJ
0
::J"
III
CALL COMMAND DECODE
;:I.
296166-26
8044 APPLICATION EXAMPLES
MAIN PROGRAM
LOAD DESTINATION
ADDRESS IN FIRST
BYTE OF SIU-XMIT
BUFFER
•
LOAD INFORMATION
INTO SIU XMIT-BUFFER
SIU BUFFER LENGTH
OR FIFO-T EMPTY
Y
OUTPUT MESSAGE
TO TERMINAL
'UNABLE TO GET ON LINE'
i
296.166-27
Figure 25_ Application Module Flow Chart
12-95
intel·
8044 APPLICATION EXAMPLES
USART·RECV·INT INTERRUPT PROCEDURE
N
296166-28
Figure 26. Application Module Flow Chart
12-96
int'eL
8044 APPLICATION EXAMPLES
MENU PROCEDURE
OUTPUT MENU
TO TERMINAL
CALL OUTPUT· MESSAGE
'ENTER THE STATION ADDRESS: __ '
CALL GET·HEX
SHIFT TO LEFT BY FOUR
II
LOAD ADDRESS
INTO STAD
CALL OUTPUT·MESSAGE
'THE NEW STATION ADDRESS:_'
N
CALL OUTPUT·MESSAGE
'ENTER THE DESTINATI9N ADDRESS:_'
CALL GET·HEX
SHIFT TO LEFT BY FOUR
LOAD ADDRESS
INTO DESTINATION·ADDRESS
CALL OUT·MESSAGE
'THE NEW DESTINATION ADDRESS IS:_'
RETURN
296166-29
Figure 27. Application Module Flow Chart
12-97
intel.,
8044 APPLICATION EXAMPLES
ERROR PROCEDURE
y
y
RESET ERROR FLAGS ON USART
296166-30
Figure 28. Application Module Flow Chart
12-98
int'eL
8044 APPLICATION EXAMPLES
FIFO·T-oUT PROCEDURE
DISABLE
INTERRUPTS
II
296166-31
Figure 29. Application Module Flow Chart
12-99
8044 APPLICATION EXAMPLES
FIFO·T·IN PROCEDURE
N
RETURN
296166-32
Figure 30. Application Module Flow Chart
12·100
int:eL
8044 APPLICATION EXAMPLES
SIU-RECV PROCEDURE
296166-33
Figure 31. Application Module Flow Chart
POWER ON
I
INITIALIZE SIU REGISTERS
I
1
FOR EACH STATION
INITIALIZE RSD RECORDS
1. STATION-ADDRESS
2. STATIQN-STATE
DISCONNECT
3. BUFFER-STATE
BUFFER-NOT-READY
4. INFO-LENGTH = 0
=
l
=
I
RETURN
I
296166-34
Figure 32. Primary Station Flow Charts
12-101
inteL
8044 APPLICATION EXAMPLES
PRIMARY STATION MAIN PROGRAM
ADDRESS NEXT STATION
SET STAD
CALL SEND-SNRM
CALL SEND-DISC
Y
Y
CALL XMIT I T S ~_ _--.,;Y;. _ _ _ _~
IT-I-FRAME) ...,
CALL XMIT-I-T-S
(T-RR)
Y
CALL BUFFER-TRANSFER
296166-35
Figure 33. Primary Station Flow Charts
12-102
int:et
8044 APPLICATION EXAMPLES
SEND-SNRM PROCEDURE
N
296166-36
SEND-DISC PROCEDURE
N
STATION-STATE = DISCONNECT-S
BUFFER-STATUS = BUFFER-NOT-READY
296166-37
Figure 34. Primary Station Flow Charts
12-103
int:et
8044 APPLICATION EXAMPLES
XMIT'T·S PROCEDURE
BUILD CONTROL
FIELD. USING EITHER
I, RR, RNR
AND NR AND/OR NS
CALL RECEIVE
y
296166-38
XMIT PROCEDURE
296166-39
Figure 35. Primary Station Flow Charts
12·104
int:eL
8044 APPLICATION EXAMPLES
BUFFER·TRANSFER PROCEDURE
MOVE DATA FROM
SIU·RECV·BUFFER
TO RSD BUFFER
II
296166-40
Figure 36. Primary Station Flow Charts
12-105
8044 APPLICATION EXAMPLES
296166-41
CHECK-NsPROCEDURE
296166-42
Figure 37. Primary Station Flow Charts
12·106
_.
l
a
REMOTE BUFFER-STATUS
=
BUFFER-READY
J!
a
c
Gl
2
~
:J>
~
'tI
'tI
'U
::!.
r-
3
(;
.!.. UJ
oz
~
I\)
o
~
!II
'<
~
..
i
m
:I
"II
~
0'
:e
o:I'
J
iii:
'tI
rm
rn
STATION-STATE
= DISCONNECT·S
~
a
296166-43
I
ab44 APPLICATION EXAMPLES
APPENDIX B
LISTINGS OF SOFTWARE MODULES
20: 24: 47
09/20/83
PAGE
IBIS-II PL'''-51 VI.O
CDtPJLER INVOKED BY:
: F2: PL"51 : F2: APNDTE. SRC
('RUPI-44 S.cond."u St.ti0l') Of'iYer')
.TITLE
tDEBUO
tREOISTER8ANK( 1)
I'tAlN'P«lD: DOl
.rcJLIST
'*
To .ave p.pe,. the RUPI ,. •• 1.t." • •
DECLARE LIT
TRUE
FALSE
FOREVER
6
r.
nat li.ted, but thh is the-st.tement
und to include th ... : _INCLUDE (:F2:RE044. DCU . /
DECLARE SNRM
UA
DISC
D"
FR""
REOJJlSC
UP
TEST
LITERALLY
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
DISCDNECT _8
FR~_S
]_T_8
',3H',
'33H',
'0E3H',
'DOH',
'OlH',
'*
LIT
LIT
LIT
UBERJJTATE_CUJSED
'DOH',
'WHILE l'i
'B3H'.
'73H',
'43H'.
'IFH'.
'97H',
LIT
LIT
OPENJ!
CLOSEDJ!
'LITERALLY' •
'OFFH',
'OOH',
LOOICALLV DISCONNECTED STATE*,
'OlH', /. FRNE RE.JECT STATE *1
'02H'. /. nFORItATION TRANSFER STATE . /
LIT
LINKJ)ISCONOECTED
. OVERFLOW
LIT
LIT
DATA_TRANS"'JTTED
LIT
UNASSIONED_C .
.
NO_'J'ELD...ALLOWED
LIT
LIT
BUFF_OVERRUN
SEB..ERR
LIT
LIT
'OOH'.
'OlH',
'02H',
·03H'.
'OOH',
'OlH'.
'02H',
'03H',
296166-44
12-108
intet
8044 APPLICATION EXAMPLES
20: 24: 47
UBERJlTATE
BYTE
IVTE
BYTE
STATlON_BTATE
IJRIlMEJ.ENOTH
09/~O/B3
PME
iii:
MlXILIMV.
M,lXILIMY.
AUXlLJARV.
BUFFERJ.ENOTH
SIU_XIUTJlUFFERC.UFFERJ.ENOTHI
SIU.../IECYJlUFFER C.UFFERJ.ENOTH I
FRIIRJlUFFERC31
.YTE.
'60',
LIT
.YTE
PUILIC
.YTE
PU.LIC.
aIT PUBLIC.
7
2
S
,
2
I
BIU.../IECY: PROCEIIURE CLENOTHI EXTERNAL,
DECLME LENGTH IYTE.
END SIU.../IECY,
10
\I
12
2
OPEN: PROCEDURE PUlL.IC USINQ
,
END OPEN.
2
a.
USERJlTATE-OPEN_S.
,3
2
14
2
CLOSE: PROCEDURE PU.LIC USINO 2,
M-O,
"
16
2I
END CL.OSEI
PDWER_DNJ): PROCEDURE
17
2
18
2
19
20
21
22
23
24
2
2
2
2
2
2
2D
USEltJlT"TE-CLOIIEDJI.
PUILIC USING 0.
•
USERJlTATE-CL.OSED_S,
STATION_BTATI!-DISCDNNl!.CT..II'
T8S-.8IU.-XPlITJlUFFERCO),
R..... BIU.../IECYJlUFFERCOI,
'* En.bJ. thl
R.L·IUF'P'ER~THI
RIE-l,
SIU', ,..cdv.,. ./
X"IT JlUFFER..EIW'TV"I.
END PDWERJIN....D'
26
2
27
2
DECLARE X"IT JlUFFERJ.ENOTH
I
STATUS
28
2
30
2
32
2
34
3
IF USIIRJlTATEoCLDIED_S
THEN STATUs-UBERJlTIITE_CLDBED.
ELSE IF STATlDNJlTllTE"DIICIHIECT..II
THEN BTATUIIoLINK....DIIC_CTED.
ELSE IF X"ITJlUFFERJ.ENOTH)IUFFERJ.ENOTH
THEN STATUSoOYERFUIW.
ELSE DO.
TRANMIT: PRDCEDURE CX"IT JlUFFERJ.ENOTHI IYTE
IYTE,
IYTE
IVTI!
PUBLIC USINO O.
AUXILIARY.
AUXILIARY,
296166-45
12-109
infel .
8044 APPLICATION EXAMPLES
PL' ....51 COIPJLER
35
20: 24: 47
36
3
3
37
3
38
3
39
40
3
3
2
1
END TRANSMIT.
43
2
X"JT_IN«IIIIIEREII: .PROCEllUllE (CDNTROLJVTE) •
44
2
45
46
47
2
2
2
4J
42
...
49
SO
END.
RETURN STATUI,
DECLARE CDNTROLJYTE
IYTE.
TCI-CDNTROLJVTE.
TIF-l,
"""1,
DO WHILE NOT BI.
END.
81-0,
3
2
END
X"n_~D'
52
2
_"..JIE8I'DN8E:. PROCEDURE •
53
2
2
2
NBNR-o.
IF CRCI AND lOtH 0
54
55
STATION..BTATE-I_T_BI
~DO.
57
SIt
59
60
3
62
63
64
6'
3
3
:I
0
'*
R•• ,Dnll i f pall . . . . /
TlL-o,
CALL ."IT_\NIUIIEREDCUAJ,
3
ENlb
3
2
PAK
IPiIT JlUFFEIIJ;:PP'Y-o,
TIL.... IT.JIUFFER_LENOTH,
Ij'RNE...,LEN8TH.)CPlIT...UFFERJ,.EMiJTH' , . 'Stare lenltlt In c •••• tation
'e " ••• , II. FR... SHRill eh. .,
TIP-&,
STATUS-DAT"_TRMatITTED,
3
51
09/20/83
IF
•
X"IT..IWFER~TY-o
TIEN DDI
, . If an I ,,.. . . . . . le,t p.ncUng tr.n •• a.elon
t"en ",.'-a". It:
*'
TIL-ljRNEJ,.ENCITH.
TlF-l,
END. '
2
66
..
67
2
2
X"JT...FR~:
PROCEDURE
(R~)
DECUIR. REASON
•
BYTE,
69
2
TC....... ,
70
71
72
2
2
2
73
74
75
2
:I
3
TIS-. FRMJUFFEIUOII
TlL.-3,
FRM,JIUI'FER (O)-RC ••
/ . . . ., nibil I •• 1n . . . . . . ,
FW. .....,IurFER(lI.C . . . CC . . . AND O£tU,.) OR
SHRCCNBNR AND OEOH),4»1
DO CA8E REA-.
F'RttRJlUFFERCiiU-olH,
, . IMMSIONED_C . /
.
296166-46
12-110
3
inial.,
8044 APPLICATION EXAMPLES
PLItt-51 CDf1PILER
76
77
78
79
3
3
3
3
eo
FRttR.-BUFFER(2)-0Zf1
FRPWlJlUFFER (2)-04H1
ENI),
FRttR_IUFFER (2) -08H,
09/.20/83
PAGE
'*
ND_IJIELD..ALLDWED . /
'* BUFF_OVERRUN
./
, . SESpR
*'
STATION_STATE-FRI'IR_S,
81
2
B3
84
8S
3
3
4
B6
4
87
3
3
BB
20: 24: 47
IF (RCB AND lOH) <>0
THEN 00,
TIF-l,
RTS-l,
DO WHILE NOT SI,
END,
91-0,
END,
"
I
END Xt1IT...FRf1R,
90
2
INJUSCDNECT_STATE: PROCEDURE " . Celhd ffoa. SIU_~NT procedure
91
2
IF (CUSER_SrATE-OPEN_SJ AND C(RCI AND OEFH)-SNR,U J
THEN CALL. BNR"JtESPON8E1
~
2
96
97
98
"
3
3
3
1
EL.SE IF CRCI AND lOH) <> 0
THEN 00,
TlL.-O,
CALL X"IT_UfNIPtIEREDCI)ft),
99
2
100
2
102
103
104
3
3
3
lOS
2
107
lOB
109
3
3
3
111
112
113
114
4
4
4
3
liS
116
3
3
118
119
4
*'
END,
END INJlISCCNNECTJlTATE,
JNjR"".JJTATE: PROCEDURE I , . C.lled at.,. BIU_INT _hen. fIT ••• h •• b . . n r.ceived
..hen in th. FR..... t.t • • /
IF CRCB AND OEFHI-sNR"
THEN 00,
CALL _"..RESPONSE,
Ta&-. SIU.-I"ITJlUFFERCO),
END,
/. R•• to". t".n •• it: buff.,. st.,.t add" ••• */
ELBE IF (RCI AND OEFH)-DISC
nEN DO,
4
STATION_STATE-DISCONNECT_S,
T8S-. BJU_Xt1ITJUFFERCO),
/. R•• tore tr.n •• it buffer .t.rt .ddr •••• ,
IF (RCB AND JOH)<> 0
THEN DO,
END,
ELSE DO,
TIL-O,
CALL X"IT_U~BEREDCUA).
END,
, . Recei ..... control b\lt. h
IF CRCI AND lOtU <> 0
THEN 00,
TBF-l,
.D•• thing o'her th.n DISC or INRI" . ,
RTB-II
296166-47
12-t11
4
intel .
8044 APPLICATION EXAMPLES
110,24,47
1110
121
122
123
DO WHILE NDT
END.
END.
5
5
4
3
124
PAGE
ai,
END INJ_...,."'TE.
CIII'IIWID..PECDIII£: PROCEDURE.
125
2
126
2
IF IRCB AND OEFHI-_M
THEN C....... _MJlESPIINIIE.
128
2
ELSE IF (RC8 AND OEFHJ-DISC
nEN DOl
130
131
3
3
133
134
135
136
4
4
4
3
137
2
139
3
141
4
143
144
145
146
147
148
149
ISO
lSI
09/110/83
ST"'TIDNJlTATE-DI8CDMlECTJI'
IF IRCI AND 10HIOO
THEN DO,
'IL-O,
C......L XMIT _ _ IEREDCUA'.
ENOl
END.
ELSE IF CRCB AND OEFHI-TEST
'*
TtEN DO,
*'
IF IRC8 AND IOH»O
R•• ,and if poUed
THEN DO,
, . FOR BOY-I, SEND THE TEST RESPONSE WITHDUT AN I FIELD ./
IF (IOV-I)
THEN DD.
TBL-O,
C......L XMITJjNNUM8EREDITEST OR IOH"
END.
ELSE DO' /. If no lOY, .. n. ,..ce:Lv.d I 'hld bacll to
TIL....FL'
TI_IS.
CALL X"IT_UNNUI'IIEAEDCTEBT OR 10H) I
11&-. BIUJI"tTJlUf'P'ERIOh
/. R•• ,.,.. TaS . /
,
,
,S
5
5·
5
''''''''\1 .,
5
5
END.
, . If an I .,. ........ pending,
1S2
4
1S4
US
1M
IS7
lSe
159
,
160
2
162
163
3
3
16'
3
•• t it up a ... :l.n . /
IF XMITJlUFFER..,.EMPTY-o
THEN DO.
TlL-IJR_~OTH.
5
S
_I.
4
3
3
'IF-I,
END.
ENOl
END.
ELBE
IF,
CRCa AND 01H) • 0 , .
THEN DD.
:!C~.:,.:::
:!.
t::C:~d
II:::
1:·:=;': 1 ./
Nt. 11
IF "MITJUFFER..,.EMPTY - I
THEN TIL. O.
'IF • II
/. aentl .n AUTO .ode ,. •• ,on . . . /
296166-48
12-112
5
intel~
8044 APPLICATION EXAMPLES
20: 24: 47
PL./ .... :ll COI1PILER
166
167
3
3
168
2
RTa •
ENOl
0CI'/ilO/S3
p~
6
11
169
170
2
171
2
DECLME
172
173
2
2
91-01
IF BTATIDN_BTATE<> I_T_9
170
3
SIU_tNT:
PROCEDURE INTERRUPT 41
AUXILIARV,
BVTE
'*
THEN DO.
,,
177
17B
17'"
1110
IBI
I""
IB3
lB.
Kud 0. in NON-AUTO Mod.
IF RBE-O /. R.c.i .... d • frail'!.?
*'
'Uve ,. •• pons. */
THEN DOl
DO CASE STATION_STATE!
,,
••
CALL INJHSCONNECT_STATEI
CALL I N_FRt1R_9TATE I
ENDI
RBE-II
END,
3
3
RETURN,
ENOl
/ . 1f the progr .... r •• ch •• thi. point,
.. hich ••• n. the SIU .ith.", w•••
IB5
2
IB7
3
I'"
3
191
19l!
193
19.
••
19.
3
IF
"'THEN
,,-0
II
IF CRCB AND OEFH)-DISC
THEN CALL COI'tI1AND_DECODEI
ELSE IF USER_STATE-<:LOSED_B
THEN DO,
4
TBL-O.
CALL XI'IIT_UNNUKBERED(REO_DISCll
ENOl
3
ELSE IF BES-t
THEN CALL XI'tITJRf1RCBES_ERR);
ELSE IF 80Y-l
THEN DOl 1* DON'T SEND FRfm IF A TEST WAS RECEIVED.,
IF (RCB AND QEFH)-TEST
THEN CALL COf'It'Iot.ND_DECODEI
••
ELBE
CALL XI'tIT_FRI'1RCBUFF_OVERRUN)1
END.
ELSE CALL COf'tt'IANDJ)ECODE'
R8E-l;
3
3
3
205
206
*'
DOl
19B
200
<201
<202
<203
<20'
STATION_BTATE.I_T .....S
or sU 11 is in the AUTD I'IlDE
END.
ELSE DOl
3
3
20B
/. !'lUST STILL BE IN AUTO 110DE .,
IF TBF-O
THEN Xt1IT_BUFFERJI1PTY-l,
, . TRANSMITTED A FRN1E . ,
IF RBE-O
THEN DO,
296166-49
,
:210
4
211
212
213
214
4
4
4
..
3
1
21~
216
217
20: 24:·H
RUPI-44 Second_"" Bhtion DT'ive,.
PL.'f'I-:1l COI'1PILER
*'
*'
'*
'*
RIP-II
RNR STATE
RBE-l,
RE-ENAIILE RECEIVER
CALL SIU-.R,ECV(AFU I
RIP-a,
RR STATE
END,
'*
09/:Z0/83
PAQE
*'
ENOl
END StU_INT.
END
""l~t1ODI
WMNINOS:
4 IS THE HIQHEBT USED INTERRUPT
ttODULE UFORr1AT ICN:
CODE SIZE
CONSTANT 81 ZE
DIRECT VARIABLE SIlE
INDIRECT VARIABLE SUE
lIT eUE
8 IT-ADDRESSABLE SUE
AUXILIARY VARIABLE SIZE
MXlI'tUf'I STACK SIZE
RECnSTER-BANKCS) USED:
(BT AT IC+QVERLAYABLE)
- 026FH
6"D
•
OOOOH
3FH+OilH
3CH+OOH
0IH+OOH
OOH+OOH
• OOO6ti
• 0017H
o I 2
00
630+
600+
10+
00+
60
23D
2D
OD
00
00
460 LINES READ
PROORAI'I ERROR (B)
o
END OF PL/t'I-'l CO'tPILATION
296166-50
12-113
8044 APPLICATION EXAMPLES
18:~:
ISIB-II PL'"-51 VI.O
INYOKED BY:
C~ILER
.TITLE
.tI•• u•
53
09/19/83
PAGE
: '2: ,1_'1 : f2: unot ...... c
('Appl ication Ma'uh: "'s\lnc/SDLe P1"otocal cony.,.'."')
• " •• t.te"lI.n.COI
u••""Otl:tlOI
,
.NllLIIIT
DECLARE
LIT
T"UE
LITERALLY
LIT
FALSE
FCltEVER
ESC
LF
CR
IS
IEL
El'PTV
IMa
I'ULL
_-.sTATE_CLOSED
LINKJ)lBCONNECTED
DYERFLDW
DAT"-TRANBtIITTED
'LITERALLY',
'OFFH',
'QOH',
LIT
LIT
LIT
LIT
LIT
LIT
LIT
L.IT
LIT
L.IT
LIT
LIT
•.... ILE 1',
'18H',
'OAH',
'OI)H'.
'OBH'.
'07H',
'OOH',
'OIH'.
'02H·.
'0011',
'OIH',
'02H',
'03H'.
LIT
LIT
/. BUFFERS . ,
BUFFER..LENOTH
LIT
BIU.)I"ITJlUFFERCBUFFEAJ.ENCITH)
SIU...AECVJlUFFERCBUFFERJ.ENOTH)
FIFD_T(2116)
BYTE
INJ'TR_T
IYTE
OUTJ'TR_T
IYTE
IUFFEA-.BTATUB_T
BYTE
I'IFO...A(2116)
IYTE
INJTR...A
BYTE
OUTJTII...A
BYTE
IUFFEA-.sTATUB...A
BYTE
LENOTH
CHAR
I
UBMT_CIID
DESTiNATlDNJIODAEBS
BEND....DATA
~_ _ INDEX
ER"JE_JTR
I.
" •••••••
IYTE
IYTE
IYTE
IYTE
BYTE
BYTE
IYTE
IYTE
_D
'60',
-BYTE
EXTERNAL
BYTE
EXTERNAL,
AUXILIARV.
AUXILIARY.
AUXILIARY.
AUXILIARY,
AUXlllMV,
-AUXILIARY,
AUXILIARY,
AUXILIARY,
IDATA,
MJX1LIAAY,
AUXILIARY,
AUXILIARY,
AUXILIARY,
AUXILIARY,
AUXILIARY,
AUXILIARY.
AUXILIARY,
AUXILIARY.
Sent to the T.".inal
./
.PMITY'*) BYTE CDNSTMTCLF, CR. 'P.1'itU E1'1'o1' Det.ct.ed'.LF.CR,OOH).
FRNEC*) BVTE CDNBTANTCLF.CR. 'F1'•• inl E1'T'01' D.tect.d'.LF.CR.OOHJ.
296166-51
12-114
inteL
8044 APPLICATION EXAMPLES
PL''''-5l COt1PILER
18: '0:
'J
09/19/93
PAgE
OYE"-.RUNC*) BYTE CONBTANTU.F. CR. 'Overrun Error Detected'. LF. CR. 0).
LINKC.) BYTE CONSTANT eLF. CR. 'Un_Ill. to Oet Onlin.',lF,CR.OOH),
DEBT_ADORe.) BYTE CDNSTNIIT(CR. LF.lF.
'Ente ... the d •• tination .-dd" ••• :
" DB. BS. 0),
D-"DDA_ACK(*) BVTE CONBTANT(CR. LF. LF.
'Th.- n.w d •• tin.tiD" .-ddr ••• ia ',0),
STI\T_ADDRC*) BYTE CCNSTlMHCR. LF. LF.
'Ental" the statian .ddT ••• ;
S-"DDR.jICKC.) BVTE CONBTANTCCR. LF. LF.
'Th. n.w .t.tian addr ••• i_
"DDR~CK_FIN(.)
SION_ONCe)
',88,88,01,
',0),
BYTE CONSTANTe 'H', CR. LF. LF. 01,
BVTE CONSTANTCCR.
LF. LF.
'(\/) RUPI-44 Buonde.,.\! 9t.t1on', CR. LF •
• \ " , CR, LF. LF.
'I - S.t the 8t.tlon Add" .... ',LF,CR •
•~
'3
'4
':5
•
-
Set the D•• t1natlon Add" ••• '.CR.LF.
00 Onlin.'.CR.LF,
00 O•• lin.'.CR.LF.
R.tuT'n to t.T'",in.l .od.', CA. IF. IF.
Ent.T' option: _', BS. 0).
FIN(*)
BYTE CONSTANTCCR.lF.LF.O).
HEX_TABlE(!7) BYTE CONSTANT ( 'OI~3456789ABCDEF·. BEL).
I1ENU_CHAR(6) BYTE CONSTANT( '1234:5'. BEL),
X"IT JlUFFER..EttPTY
BTDPJlIT
ECHO
WAIT
ERROR..FC .....
BIT
BIT
BIT
'* ,*
'* n •• out
*'
EXTERNAL.
S . . . phoT'. fof' RUPI SIOU Trans. it Bu".T' *'
AT(147) REg.
T.T'min.1 p.T'.III.tn.
ATCOB4H) REO.
BIT.
BIT.
f:1.g
*'
, . ET'T'oT' m•••• g. Fl.g . ,
'* P.T'ihaT'.l AddT' . . . . . *'
UBART _STATUS
UBART..DATA
TlP1ER_CONTROL
TlI1ER_O
T1t£R_1
T1t£R~
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
AT<0801H)
ATtOBOOH)
ATCtOO3H)
ATCI000H)
AT(100tH)
AT (100iii2)U
AUXILIARY.
AUXILIARY,
AUXILIARY.
AUXILIARY,
AUXILIARY.
AUXlL.IARYI
296166-52
12-115
2:
intel~
8044 APPLICATION EXAMPLES
IS: SO: 53
PI..'I'1-'1 CDf1PILER
6
7
2
I
PDWER_ONJ): PROCEDURE
END PDWER_ONJ)J
8
•
2
I
CLOSE:
10
II
2
I
OPEN: PROCEDURE EXTERNAL USING 21
END OPEN,
12
13
14
2
2
I
END TRANBf'fn,
15
16
17
2
2
I
END Tlf'IER_O_INTI
18
2
POWER_ON:
I.
2
DECLARE TEr1P
20
21
22
23
2
2
2
2
BI'1D-,4HI
TI1On-21H,
THI-OFFH,
24
25
26
27
2
2
2
2
Tlf'ER_O-ooHi
()9/19/B3
PAGE
EXTERNAL,
PROCEDURE EXTERNAL USINO ::2,
END CLOSE,
TRANSMIT:
PROCEDURE
(XI1ITJUFFERJ.ENOTH)
DECLARE ."ITJUFFERJ.ENOTH
TI~R_O_INT:
EXTERNAL,
BVTE
BYTE,
PROCEDURE INTERRUPT 1 USINO 1,
WAIT-O,
PROCEDURE USING 0,
AUXILIARY,
BYTE
'*'*
Using DPLL. NAZI. PFS. TU1ER 1 • • 62. S Kbp.
Tillin 0 16 bit. lillllT' 1 auta rdoad
*'
*'
TCON ..40H,
Tlt1ER_CONTROL-37HI
TlPER_O-o4HI
Tlt1ER_CONTROL-77H,
'*
'*
,* InUiaUu T.C.
IniUalize UBARr's _"shill clodl 9254 . /
RIC
*,
D.flinU1an faT' dip s,dtch thd to P1. 0 to P1. a
Bit Rate
300
1200
2400
4800
.600
1.200
on
on
on
on
0"
0"
0"
of'
0"
on
off
on
off
Stop bit
on
off
off
odd
0"
on
on
0"off
0"on
off
296166-53
12-116
3
6044 APPLICATION EXAMPLES
PL/ ...."
C,",ILER
18: SO: '53
Echo
...
.n
2"
2
TEI'I--Pl AND 07H,
:z
3
34
4
4
4
35
4
:No
/. 1200'/
39
4
4
4
4
40
4.
42
4
/. 2400 I'
4
4
43
4
END.
44
45
46
47
4
4
4
4
END.
48
49
4
4
4
4
END.
5.
53
4
4
54
4
55
56
'3
52
*'
Tt£N TEMP-OI
DO C,.BE TEttP I
32
33
50
"
, . R•• d t h dip ... itch to d,t.,..in, the Uti rat,
IF 1'EN')5
3'
37
38
PAGE
on
0"
:za
09/19/83
/. 300
*'
DO.
TZttER_l-a:»tl
TUtER_l-:ZOH,
END.
DOl
TI"EA_l;':ZOH,
TJt£A_I-o!5H.
END.
DO.
TJt£R_1-60H'
TUIER_I-02H.
TII"ER_l-3OH1
TIl1ER_'-OlH.
TII'IER_l-oSH.
TlP£R_l-0,
, . 19200 . / DO.
TIIER_l-33HI
TlptER_I-O,
END. -
4
END.
57
58
59
60
:z
2
:z
2·
USMTJlTATUa-40H,
61
2
T£PII-oAH,
USMT_BTATUB-OI
, . BDfia....... POIIII,,-on ,. ••• to for 8251'" . ,
USMT JlTATUS-O.
USNlTJlTATUS-O.
'* D.t,,..ine
the p."U, and. D' stop "ib ./
62
63
:z
:z
65
2
ELSE TEN'-TEtIP DR 40HI
66
2
67
:z
::i~:=7T=:'T _~~D~~i 1:~::"~D~:':~nd
68
2
STAD-OFFH.
TEI'P-TeIP DR IPI AND 3OH),
IF STOPJllT-'
THEN TEI'P-TEMP OR OCOH,
Ward RTB.
R.E,' DTR.
TIEN-l*'
296166-54
12-117
infel·
8044 APPLICATION EXAMPLES
18: 50: 53
69
II
70
II
71
II
IUF'FERJlTATUB_T. lurFER-'lTATUS...JI- EPPTY.
CALL POWERJlNJh
711
II
73
II
74
II
75
II
BENDJh'TA-OI /. InthU'e Fl •••• /
INJ'TR_T. DUTJTA_T, INYTAJt. OUTJTRJ' • O,I-Initialile FIFO
USMT'. RaRdU h
the hi, .... , pl'io"U, . ,
Int*T'l'upti ."8 hval ,,.,, ••,,.d*/
/. En.ll1. USMT RIRd •• sr. an4 Tl ••" 0 inte,.rupt.a,
EIIRDRJLM-OI
II
79
80
II
II
FIFOJIC INJ'TRJlI-CHM,
I,NJ'TRJI-INJ'TRJI+I,
81
II
IF BUFFER_STllTUSJI_TV
THEN DO,
87
II
3
3
3
3
3
II
P'1F'O..Jt_IN: PROCEDURE (CtIM) USINO I.
DECLME CtWt
BYTE.
EII-Q,
BUFFERJlTATUS...JI-INUBE,
EX1-1,
/. Enabl. UBMT'. TID int.,.,.upt *1
EA-l,
,
END,
ELSE IF CCBUFFER_8TIITUSJl-INU8EI lIND CINJ'TRJI-auTJ'TRJI I I
THEN BUFFER_8TATUSJI-FlJLL,
90
END FIFOJl_IN'
91
II
ft
II
DECLARE CHM
93
II
II
CHM-FIFOJlCOUTJ'TRJlI,
OUTJ'TRJI-auTJ'TRJI+I,
IF OUTJ'TRJI-INJ'TRJI
THEN DO,
,
EU-Ch
Shut aft T.D int."''I'upt
94
9S
..
97
II
99
100
3
3
3
II
102
II
103
104
PTR._'
'* /. Bath u,.,.nal
IE..:JH.
77
78
..
PAGE
END PIllER_ON,
76
83
84
8S
09/19/83
FIFOJ'_ClUT: PROCEDURE BYTE USING 11
BYTE
AUXILIARY,
'*
*'
BUFFEA_BTATUS...JI-DPTV,
END,
ELBE IF CCIUFFERJlTIITUSJl-FlJLLI _
THEN BUFFER.:,.sTATUS...JI-IMJBE.
COUTJ'TRJI-IIO-INJ'TRJI"
RETURN CHAR,
END FIFOJlJlUT,
II
296166-55
12-118
5
intel.,
8044 APPLICATION EXAMPLES
flL/K-'l CDrPIL£R
..,.
105
Application I'toduh: A... ne/BDLe PT'otocol conve?teT'
a
DECLARE
2
IF ERRDR..JLAO
BYTE
19: 50:'3
09/19/83
PofIOE
6.
CONSTANT,
TI£N DO,
.08
3
110
112
0
0
0
113
110
115
0
0
0
IF I1ES8AOECERRJESSAOE_INDEX)<>O
/. Then canUnu. to . . ncl the ••••••• _,
TIEN DO,
"'
USART_DATA • t£SQAQEtERRJESSAQE_INDEX)1
ERRJtESSAOE_INDEX-EARJtESSAOE_INDEX+SI
ENOl
ELSE DO,
'*
I f . . . . ., . is don ....... t ERRORJLAO and shut off interrupt i f FIFO ia •• ptV
ERROR_FlAG-O.
*'
IF BUFFER_STATUBJI - EI'FTV
THEN EX1-0,
111
11_
0
3
119
2
ENOl
END.
'20
""
.1I2
2
2
DECLARE LENGTH
I
'"3
.1I0
.1I5
.lIb
• 21
3
DO 1-0 TO LENQTH-l,
00 WHILE BUFFER_STATUSJI-FULLI/. Chad to . . . i f fifo is flull
•0
3
3
SJUJtECV:
PROCEDURE (LENOTH) PUBLIC USINO 11
BVTE.
BYTE
AUXIL.IARY,
END.
CALL FIFD_R_INCSJUJ'ECV_BUFFERtl»'
*'
•
END •
• lIB
.:19
2
.30
2
DECLNtE CHIIA
13'
'133
32
2
2
1I
FIFO_T( INYTR_T)aCHAlh
INJTR_T-INJTR_T+ll
135
1I
BYTEI
IF CHAR-LF
THEN SEND_DATA-SEND...DATA+IJ
JF BUFFER_STATUS_T-e:PI'TY
THEN IUFFER_STATUS_T-IMJSEI
131
139
140
3
3
,., •
I., •I
•••
ELSE IF "BUFFER_STATUS_T-INUSE) AND UNJTR_T+2o-DUTJTR_l»)
llEN DO, ,- Stop ,..c.pt:l.on u.tng CTS -,
USART_STATUS. UBART_CMD-UBART_CttD AND NDTC2OH)1
IUFFER_STATUS_T-FULLI
IF SEND.J)ATA-O
THEN SENDJ)ATA-l,'*U tb. lIuff.,. i . full and no LF
ha. 1I •• n ,..c.lv.d th.n •• nd d.t. -/
ENDI
296166-56
12-119
int:el..
8044 APPLICATION EXAMPLES
18: 50: 53
105
:I
146
;I
DECLARE CHAR
147
148
14'
;I
;I
CHARaFIFD_TCOUTJTR_T),
lSI
3
3
3
3
3
1S2
153
I'.
I"
2
1S6
:I
158
IS'
160
161
163
164
3
3
3
;I
PAGE
AUXILIARY,
BVTE
OUTJTR_T-our J'TR_T+l.
IF OVT...pTR_T-IN_PTR_T
THEN DO.
EA-O,
/. Th.n FIFO_T h
••ptV
*'
IUFFER_BTATU9_T-Ef1PTV,
BEND_DATA-O,
EA-SI
END.
ELSE IF ('IUFFER_BTATUB_T-FULL) AND COUTJTR_T-SG-INJTR_T)
THEN DO.
UBMT_STATUS. USART_CHD-USART_CHD DR iiZOH,
BUFFER_STATUB_T-INUSE,
END.
IF (CHM-LF AND SEND_DATA)O) lIEN SEND..DATI\-SEND_DATA-1J
RETURN CHAR,
:I
I
END FIFO_T_ooYI
16'
:I
ERROR: PROCEDURE (STATUS) USINO 2,
166
:I
DECLARE STATUS
167
2
JF (STATUS AND oeH)(>O
16'
2
171
;I
173
2
UBMTJiTATU9-CUSART_CHD OR SOH),
174
17'
176
2
2
2
ERRJESSAOE_INDEX • 0,
177
09/19/83
BYTE,
TJ£N ERRJ'tEB8AOEJ'TRa, PARJTY,
ELBE IF (STATUS AND lOH)<>O
TtEN ERRJlES8AOE_PTR-. DYER.}"""
EL.SE IF (STATUS AND 2OH) <)0
TtEH ERRJEBSAOEJlTR-. FANE,
ERRORJLItQ-l,
EXt-!,
'*
/ . A. . . . . . "Tor 'hi_ an USART
TuT'" on TI Int.r1'upt
*'
*'
END ERRDfh
17.
2
17'
;I
lao
:I
181
182
183
184
;I
2
:z
3
LI*JU~:
PROCEDURE,
DECLARE ME_JTR
IE&IIAOE
,J
EXI_8TORE
WORD
BASED
BYTE
BITo
AUXILIARY,
PEBSAQE"pTR ( 1 J
AUXILIARY,
BYTE
EXl_STORE-EXlJ
,_ Shut off ..... nc tOJ.
CONSTANT,
*'
296166-57
12-120
intel .
8044 APPLICATION EXAMPLES
PL/t1-~l
IS.
IS.
IS7
ISS
111'1
190
191
CDI'IPILER
"pplic.tion r1oduh:
,•
3
3
3
2
I
192
193
2
2
I ..'
19.
19.
3
DO WHILE (USART_STATUS "ND OIH)-O.
ENOl
'* R•• tar • • • \lnc
Ell-Ell_STOREI
END U .... JHSC'
PAGE
DECLARE CHAR
1* We1t '01" rl.RDY an UBART *1
tr.ns",it int.rrupt
*'
BYTE,
DO WHILE (USART_STATUS AND OUU • 0,
ENOl
UBART ..DATA-CHAR I
END CO,
PROCEDURE BYTE USINg 2,
DO WHILE (UQART _STATUS AND 02H) • O.
END.
RETURN USAAT..oATAI
END CII
202
2
gETflX: PROCEDURE BYTE USINg 2,
,
DeCLARE CHAR
20'
2
BYTE
BYTE
AUXILIARY.
AUXILIARY,
II
LO: CHAR-CI,
20.
DO 1-0 TO
I~h
IF CHAR-HEI_TABL.E( I)
THEN COTO Ll.
207
209
END.
210
211
L1:
CALL. COCHEX_TA8LEC!»,
IF 1-16
THEN COTO L.O,
213
RETURN 1;
214
END eET JfEX I
21'
21.
OUTPUT..J£BSAOE: PAOCEDURE Ct1ESSACE.)JTR) USING 2,
DECLIIRE t1EBBME.)JTR WORD.
I'IESSAQE
BASED
HESSAOEJlTR ( 1 ) BVTE CONSTANT.
I
BVTE
AUXILIARV.
217
21S
219
220
9
CD: PROCEDURE (CHAR) USINO 21
ex:
20'
09/19/83
J·J+11
198
203
~3
END.
3
2
3
3
2
19: 50:
con"eTt~T'
USART..DATA-I'IESSAQE(J) I
197
I ....
200
201
"_\lnc/SDLe Protocol
3
3
3
DO WHILE t1EBBAOEU) () OJ
CALL CO UIESBAQE U ) )j
1-1+1,
296166-58
12-121
8044 APPLICATION EXAMPLES
1'L/....ll COIPILER
221
3
222
'1
ZI3
2
IJ24
2
221
-
2
227
3
3
ZIII
2
18: 110:'3
09/19/83
PMIE
END.
END DUTPUT_ _ •
f!IENU: PROCElKME USINO 2.
DECLARE I
BYTE
CHM
BYTE
BT...TION..o\DIIREBI BYTE
AUXILIARY.
AUXILIARY.
AUXILIARY.
BTART:
CALL DUTPUT.JEBIIM1E(. BIONJlNh
1'10: CHM-CI.
'* R••d •
eller.eter
.,
DO 1-0 TO 4.
IF CHMof1ENU_CHMU)
THEN ODTO "I.
END.
ZIG
3
231
23lI
II
2
"I: CALL COCI'lEMlJOtMRCUJ,
234
3
DOC_I.
231
236
4
4
237
4
IF I-a
THEN OOTO PIO.
DO.
CALL DUTPUTJ1E_C. BT...T..o\DIIRI.
BTATIDNj\DDRElJ8-stLCOETJEX, 4),
2311
4
BT...TION..o\DIIREaa-(BT...TlON....fI\IIIIREBB DR OETJ1EXI.
239
4
BT_T...TION..J\DJlREBB.
240
4
CALL QUTPUTJ1E88M1EC. • ..J\DDII...ACK I.
241
242
4
4
CALL CO(I£X_T....LE (BHR (BT...TION..o\DIIREBI. 4111.
CALL CO(I£X_T....LE.(OFH lIND ST...TlON..J\DDREB81 h
243
244
4
4
END.
24.
4
DO.
246
4
247
4
DESTI .....TION.J'I)DRE• •BHL.COETJEX, 4),
24B
4
DEBTlNATIDN...ADJlREBB-(DEBTlNATION..o\DIIREBB OR OETJlEX I.
249
4
CALL DUTPUTJ1E_C. D..J\DDII...ACKh
CALL DUTPUTJIEB_( ....OJIR...ACKJINI.
CALL DUTPUT...,M:_C. DEBT......DDRI.
296166-59
12-122
9
8044 APPLICATION EXAMPLES
1S: 50: 53
PL./H-51 CIlt'PILER
250
251
4
4
252
4
253
4
CALL. OUTPUTJEBSAQEC. ADDR_ACKJ'INJI
ENOl
00,
4
4
ENOl
•
DO,
4
END,
CAlL OUTPUT_f1ESBAOEt. FIN),
2~~
2~9
CALL OPENI
CALL OUTPUTJESBAQEC FIN"
CALL CLOSE,
4
•
262
3
263
3
26.
CALL OUTPUT _MESBAgEC" FIN) I
ENOl
,_ DO CASE _,
END HENUI
26~
2
266
~
USART_RECV_INT: PROCEDURE INTERRUPT 0 USINg 21
DECLAAE CHAR
STATUS
267
269
269
2
2
2
271
2
27'
274
27~
3
3
3
277
3
BVTE
BVTE
AUXILIARY,
AUXlL.IARY,
CHAR-UBART_DATAI
STATUS-USAAT_STATUS AND :JSHI
II
IF 9TATUSOO
THEN CALL ERRORCSTATUBb
EL.SE IF CHAR-ESC
THEN CALL I1ENUI
ELSE DO,
CALL FIFO_T_INCCHAR)I
IF ECHO-O
THEN CALL toetHAR))
ENOl
278
BEgIN:
CALL POWER_ON I
27'
280
281
2
2
283
4
284
4
28~
3
3
286
287
10
tAU. COCHEX_TADLECOFH AND DESTINATION_ADDRESS»1
256
2'7
2~8
PAgE
CALL CO(HEX_TABLECBI·IUDEBTINATJON_ADDAEB9. 4))) I
2'. 44
260
261
0fi/19/B3
•
DO FOREVER,
IF SEND_DATA>O
TI£N DO,
DO WHILE
NOT(xP1lT_DUFFER~HPTY)j ,_Wd\ unUl BW_Xl1lT_BVFF."
h "'Ipt~ -,
ENOl
LENOTH. CHAR -11
SIU_XHI T _BUFFER (O)-DEBTlNATION_ADDRESSI
DO WHILE «CHAR(>LF) AND (LENQTH(BUFFERJ.ENOTH) AND Et'1PTY»1
296166-60
12-123
intel~
8044 APPLICATION EXAMPLES
App li,taU on l'1odu Ie: AS\lnc ISDle ProtacD 1 c onv.,.t ....
288
lZS9
•
•
:190
:191
4
•
lB: '0:
~3
09/19/83
PAgE
CHAR-FIFO_T_OUT'
S IU_XI'II TJHJFFER (LENGTH) -CHAR I
LENGTH-LENGTH+ 1 i
END.
U gr •• tel' th.n DUFFER_LENGTH ,ch.,. • • end the
fbst 8UFFERJ.ENOTH char. then und the r . . t, sinel the SIU buff.,. h ani" BVFFER_LENgTH bllhs . ,
I-OJ 1* U•• I to count the nUMbe ... of un.Ute •• ful
/* If the lin. ,ntlrld at the terllina1
:192
3
ll:
:193
:19'
3
3
RETRY:
transmUs
:19.
:197
:198
299
300
301
302
303
30.
30.
307
30S
309
310
311
312
313
'*
••
•,,
'*,
*'
WAtT-I'
*'
THO-3CH,
TLO-OAFH,
4
TRO-lI
DO WHILE WAIT.
ENOl
,••
,,
,
•
TRo-OJ
1-1+11
IF 1)100 THEN DO,
'* Wait
•• nd
:5 uc to g,t on line el . .
e,.1'o" ,. •••• g. to tlT'",inal
and tTV again -I
CALL LINK_DISCI
COTO L11
ENOl
COTO RETRY,
END.
4
3
2
1
*'
RESULT-TRANSf'UTCLENOTH),
Send the ,.. . . . 11.
IF RESULT<)OATA_TRANSI'1ITTED
THEN DO.
Wait 50 .s.c 'or lin .. to connlct then t1'l1 Igain
ENOl
END;
END UBERermD.
WARNINCS:
2 IS THE HICHEST USED INTERRUPT
P100ULE INFORMATION:
CODE BIZE
CONSTANT SIZE
DIRECT VARIABLE SIZE
INDIRECT V"RIABLE SIZE
BIT SIZE
BIT-ADDRESSABLE SIZE
AUXILIARY VARIABLE SIZE
...... XItrutt STACK SIZE
RECISTER-BANK(S) USED:
713 LINES READ
o PRDCRAM ERROR(S)
END OF PL/f'1-51 COMPILATION
(STATIC+OYERLAYABLE)
• 06B2H
1714D
• 01CFH
4630
OOH+05H
00+
OOH+OOH
00+
02H+01H
2D+
OOH+OOH
00+
• 021FH
5430
• 002BH
40D
o 1 2
50
OD
10
00
296166-61
12-124
11
8044 APPLICATION EXAMPLES
P~/"-51 COPlPI~ER
co: 47: 13
RUPI-44 Pri ..n" ShUan
ISIS-1I P~/"-" VI.O
C,,"PILER INVOKED BV:
O~/26/B3
PAGE
: F::i!: PL"'! : F:iI: PNOTE. SRC
.TITLE
('RUPI-44 P1'jlll."U ShUon')
'DEBUG
sREQISTERBANKCO)
J1AIN''''OD: DOJ
/. To •• VI p.plr thl RUPI "'gist,r. 1,.1 nat liat,d. !lut this is the at.t''''I"\
u . . d to includ. th .... :
'INCLUDE (: f2: RE044. DCL) */
.NOLIST
DECLARE L.IT
TRUE
FALSE
FOREVER
'*
LITERALLY
LIT
'LITERALLV·.
'OFFH',
LIT
LIT
'OOH'.
'WHILE l' j
SDL.C COt1"ANDS AND RESPONSES
UA
DISC
D"
FRI1R
REO..oISC
UP
TEST
RR
RNR
'93H',
'73H',
'53H',
'lFH',
'97H',
~IT
~IT
~IT
',3H',
~IT
~IT
~IT
'33H',
'OF3H'.
'11H',
'l:SH ' ,
~IT
~IT
'*
REMOTE STATION SUFFER STATUS
'*
~IT
STATION STATES
DISCDNNECT_S
L.IT
OD_TD..DISC
LIT
I_T_9
LIT
*'
·OOH'.
'OlH',
'02W.
PARAt1ETER5 PASSED TO XI'IIT _1_T _5
T_IJRA"E
~IT
'OOH',
T~R
LJT
'OlH'.
T..RNR
~IT
'02H',
'*
*'
'0',
'I',
~IT
BUFFER..READY
BUFFERJlOT..READY
'*
*'
~IT
~IT
DECLARE SNR ..
'*
'*
*'
SECONDARY STATJON lDENTJF1CATJON
LOGICALLV DisCONNECT~D STATE*I
INFORf'lATIDN TRANSFER STATE
*'
*'
NUI'IBER_OF_STATIONS LJT
'2'.
SECONDARY_ADDRESSES CNUI'IDER_DF_STAT IONS)
BYTE
CONSTANTC55H.43H),
296166-62
12-125
8044 APPLICATION EXAMPLES
PL/K-Sl COI'IPILER
RUPI-44 Pf'i ... "U St.Uon
20: 47: 13
09/26/83
PAQE
RSDCNIJI'UIER_OF _STATIONS) STRUCTURE
CBTATlON...ADDREBS
STATION_STATE
NS
BYTE.
BYTE.
BYTE.
~
BY~.
BUFFER_STATUS
BYTE,
B~.
INFOJ.ENOTH
DATA(64)
'*
BYTE)
, . VARIABLES . /
BTATlDN _ _ BER
BYTE
RECYJ'IELDJ.ENOTH
BYTE
WAIT
alT.
/ . BUFFERS
BIUj:HITJUFFER(64)
*'
SIUJtECYJUFFERC64)
Th • • t.tu. of th_ •• cand..,.·" It.'tion' bu'''" *1
AUXILIARY.
AUXILIARY.
MJXILIARY.
BYTE
IOATA.
BYTE,
POWER_ON: PROCEDURE I
B
2
9
10
Tas-, SIU_XHIT_8UFFERCO)J
RBS-. SIU..RECYJlUFFERCO) ,
12
2
2
2
2
13
3
DO I- 0 TO NUKBER_CIF'_STATIONS-II
14
16
17
3
3
3
3
IB
3
END.
19
20
21
2
2
2
2
2
SPtD-54H,
Tf1OD-.1H,
TH1-0FFH,
II
U
22
23
24
25
BYTE
RIL-64,
R8E-l,
AUXILIARY,
*'
, . 64 aute receive buff.,.
En.U. the 81U', "ueiv.,. ./
.'*
RSD ( I ). STATIDNJDDRESS-SECONDARV-ADDRESSES II ) I
RSOC I ). STATIDN~TATE-DlSC~CT _8'
RSOC I), BUFFER_STATUS-BUFFERJ«IT..READY'
RSDC I). INFO~NOTH.OI
TCON-4OHI
IE-a.H,
'* Using
DPLL. NRZI. PFB. TlI'IER I • • 6 •. 5 K.p. */
'* U••
URI.'" 0 foT' ",.c.1v. U •• out int."'T'upt ./
END POWER_ON,
2
26
27
2B
DECLARE I
X"IT: PROCEDURE CCONTROL..BVTE),
DECL~RE
2
2
CONTROL..BYTE
BYTE,
TCB-CONTROLJVTEI
T8F-l,
296166-63
12-126
:z
inteL
8044 APPLICATION EXAMPLES
RUPI-44 Prima,,'1 Station
,.
"
END XMlTj
2
2
1
37
TlMER_O_INT: PROCEDURE INTERRUPT 1
WAIT-Oj
END TIMER_O_INTi
TIME_OUT:
PROCEDURE BYTE,
USING 1 j
/* Time_out returns true if there 1II • • n't
.. frame received within 200 m•• c.
If there "' • • • flr.me recRived \&Iith!n
200 ms.c then time_out returns false.
2
39
40
41
42
43
44
4'
PAGE
B]-Oj
"
38
09/i2b/83
RIS-l1
DO WHILE NOT 51.
ENOl
'0
31
'4
3'
'6
20; 47: 13
DECLARE
AUXILIARY;
BYTE
*,
DO 1-0 TO 31
WAIT-!;
THO-3CH;
TLO-OAFHi
TRO-ll
DO WHILE WAIT!
IF 51-1
THEN OOTO T _01;
3
3
3
3
4
4
47
48
END.
4.
RETURN TRUE;
ENOl
•
50
51-0,
RETURN FALSE;
"
"
",.
""
,.
'6
END TIME_OUT;
SEND_DISC:
2
2
2
PROCEDURE;
TBLaOI
CALL Xt1ITIDISCli
IF TIME OUT··FALSE
THEN IF RCS-VA OR RCS-OM
07
THEN DOl
RSOI STAT ION_NUMBER). BUFFER_STATUS-BUFFER_NDT _.READYJ
RSD! STATION_NUMBER). STATION_STATE-DISCONNECT _5.
60
61
6'
END;
63
END SEND_DISC.
64
SEND_SNRM:
6'
TBL""'O.
PROCEDURE.
296166-64
12-127
intel~
8044 APPLICATION EXAMPLES
PL/I'I-'l CDI"IPIlER
••
.7
2
2
.9
3
70
3
71
3
72
73
3
2
20: 47: 13
09/26/B3
PAOE
CALL Xl'1lTCSNRM)1
IF CTII'tE_OUr-FALSE) AND 'Rca_VAl
THEN DOl
RSOCSTAT ION_NUMBER). STATlON_BTATE-I_T _61
RSDCSTATION_NUf'lBER). NB-OJ
RSDCSTATJONJruf'tBER). NR-O.
ENOl
74
CHECK_HB:
7.
2
IF SHR(RCB. 5))
THEN RETURN FALSE,
RETURN TRUEI
B9
RECEIVE:
PROCEDURE I
DECLARE
BYTE
AUXILIARVj
RSD( STATION_NUMBER}. BUFFER_STATUS-aUFFER-.READVI
1*
93
9'
97
9B
2
[ f .n RNR ,1.11• • recei\,ed buffer_.t.tul will be ch.nged in the lup.rvhorll
frame decode .ection luther down in thtl proc:edure • • nll other re.pon.e
mean. the remote .t.tions buffer 15 r.ad~ *1
IF (RCB AND 01H)-O
THEN DO,
1* I Frame Rec.i ..... d *1
IF (CHECK_NS-TRUE AND BOV-O At~D CHECK-.NR-TRUEI
THEN DOl
RSD(STATION NUMBER I. NRllie (RSD(STATION_NUMBERI. NR+l) AND 07H)j
RBP"1i
-
296166-65
12-128
intel .
8044 APPLICATION EXAMPLES
PL/I'1-51 COMPILER
••
100
4
4
101
:3
3
102
103
:;z
RUPI-44 Prim.,.\! St.tian
:3
107
3
109
3
110
111
:3
3
113
114
115
116
117
4
4
4
3
3
118
2
119
09/26/83
PAQE
RECV _F I ELD_LENCTH-RFL-ll
ENOl
ELSE RSDISTATJDN~UI1DER». BTATlON_STATE-CO_TC_DISC.
ENOl
ELSE IF (RCD AND 03H)-OlH
THEN DO.
105
:;ZO: 47: 13
1* Supe"vhar\l 1,.11111* received
*'
IF CHECK_NR-FALSE
THEN RSD(STATlON~UI'18ER). STAT ION_STATE-CO_TOJlISC;
EL.SE IF «RCB AND OFH)-05H) 1* then RNR . /
THEN RSDCSTATlDN..NUHBERJ. BUFFER_STATUS-aUFFER_NOT .-READY'
ENOl
'*
ELSE 001
Unnumbered ,,..m. or un'nown '" .. me ,...ceived
IF RCa-FRptR
THEN DO.
If FRHR ..,.~ ,.ec.ived chec. Nr far .an
.cknowledged I frame
'*
*'
*'
RCB-SIU_RECV _BUFFER C 1 ) I
I-CHECK_NR.
ENOl
RSDCSTATION..NUI1BER». STATIDN_STATE-GD_TO_DISCi
ENDI
END RECEIVE;
120
2
121
2
122
2
124
12.
12.
4
4
4
DO TEI1P-O TO RSD(STATIoN~Ut1DER L INFD~ENQTH-l1
SIU_XI'1IT JlUFFER (TEMP )-RSD(STATION~UMBER). DATA(TEHP)J
ENOl
127
129
12.
130
3
3
3
3
TEMP-(SHL(RSD(STATION_NUMBERJ.r.lR.:U DR SHLtRSDtSTATION_NUt1BERLN5.1) OR 10Hli
TBl-RSDt STAT ION_NUMBER). INF0J.ENQTHI
CALL XI1 IT (TEMP h
IF TIME_OUT-FALSE
THEN CALL RECE I VEl
DECLARE
TEMP
BVTE;
IF TEMP-T_I_FRAME
THEN DOl
1* T",anlilit 1 #"am. *1
1* T"ansf.r th. statiDn buf'." intD int."nill "illII *1
1* Build t .... I
132
""am.
cont"ol .hld *1
END;
133
134
3
3
13.
3
ELSE DO;
1* T"ansmit RR 0" RNR*I
IF TEMP-T _RR
THEN TEI1P-RRJ
ELSE TEKP_RNRi
296166-66
12-129
intel·
8044 APPLICATION EXAMPLES
PL/I1-S1 COI'tPILER
137
138
13.
140
•••
•
144
BUFFER_TRANSFER: PROCEDURE,
BYTE
BYTE
DECLARE
••
•
ENDi
Tl:
IF r-NUI1BER_DF_STATlDNS
•••
•
RETURN,
ENDi
4
4
4
RBD( I), DA1A(")-1 )-SJU_RECV_BUFFER (vi),
END.
I
RBP""O,
ENDI
••
BEQIN:
CALL POWER_ON,
2
DO FOREVER,
•
DO
3
•
STATJON~Uf'lBER.O TO NUrlBER_OF _STATIONS-I,
STAD.RSD(STATIDN~P'lBER) ° STATION_ADDRESS,
IF RSD(STATION~Uf'lBER)' STATION_STATE - DISCONNECT_S
THEN CALL SEND_SNR""
ELSE IF ° RSD(STATIDN_NUt18ERL STATION_STATE - ~O_tO_DISC
THEN CALL SEND_DISc.;
ELSE IF «RSDCSTATION_NUMBERL INFO_lENGTHXU AND
CRSDCSTATION_NUMBER) ° BUFFER_STATUS-BUFFER_READVI)
THEN CALL XMIT_I_T_SCT_I_FRAt1E);
ELSE IF RBP-O
THEN CALL XMIT _I_T _SCT _RR' I
ELSE CAll XI'tIT_I_T_SCT_RNR';
170
174
176
177
then discard the dat ..
ELSE IF RGDe I). INFD_LENQTH-O
THEN DO;
RBD( I». INFDJ-ENQTH-RECY_FIELD_LENGTHi
DO "'-I TO RECV_FIELD_LENQTHi
2
164
172.
*'
I f the .ddT'u •• d st.tiDn do •• nat eait ••
ROP-O,
END BUFFER_TRANSFER I
166
167
168
'*
THEN DOl
16.
165
AUXILIARY,
AUXILIARY,
DO 1-0 TO NUMBER_OF _STATIONS-II
IF RBDe J), STATIDN..ADDRESS-SIU_RECV_BUFFERCO)
THEN OOTO T.,
100
107
lOS
10.
160
161
162
6
ENOl
145
152
103
154
. .5
PAGE
TEHP.CSHLCRSDCSTATION_NUl'lBERL NR. S) DR TEI1P) 1
END XHlT _1_1 _61
146
147
09/26/83
TBl-O,
CALL XI1ITCTEI'IPI,
IF TIttE_DUT-FALSE
THEN CALL RECEIVE,
142
14'
14.
20: 47: 13
RUPI-44 Prima"" St.tion
•
•
•
•
IF RBP-l
THEN CALL BUFFER_TRANSFER.
296166-67
PLitt-51 COMPILER
17.
IBO
IBI
20:47:13
RUPI-44 P"ilh""~ Station
OCU26/B3 ·PAQE
END;
ENOl
END toIAIN.toIOD.
WARNINCS:
1 IS THE HICHEST USED INTERRUPT
MODULE UoIFORI'1AnON:
CODE SIZE
CONSTANT SIZE
DIRECT VARIABLE SIZE
INDIRECT VARIABLE SIZE
D IT SIZE
D IT-ADDRESSABLE SIZE
AUXILIARV VARIABLE SIZE
MAXIMUM STACK SIZE
REGISTER-BANKeS) USED:
'''6 LI NES READ
o PROORAM ERROR(S)
END OF Pl/M-51 COMPILATION
(STAT IC+OVERlAYABlE I
= 053DH
13410
.. 0002H
2D
40H+02H
640+
40H+OOH
640+
01H+00H
10+
OOH+OOH
00+
"" OO~3H
1470
IZ 0019H
250
o
20
00
00
00
I
296166-68
12-130
7
8044AH/8344AH/8744H
HIGH PERFORMANCE 8-BIT MICROCONTROLLER
WITH ON-CHIP SERIAL COMMUNICATION CONTROLLER
• 8044AH-lncludes Factory Mask Programmable ROM
• 8344AH-For Use with External Program Memory
• 8744H-lncludes User Programmable/Eraseable EPROM
8051 MICROCONTROLLER CORE
•
SERIAL INTERFACE UNIT (SIU) .
•
2.4 Mbps Maximum Data Rate
• 375
• LoopKbps using On-Chip Phase Locked
Software in Silicon:
• -Communication
Complete Data Link Functions
Optimized for Real Time Control 12
MHz Clock, Priority Interrupts, 32
Programmable I/O Lines, Two 16-bit
Timer/Counters
Serial Communication Processor that
Operates Concurrently to CPU
Processor
• 4KBoolean
x 8 ROM, 192 x 8 RAM
• 64K Accessible External Program
• Memory
Accessible External Data Memory
• 64K
4 p.s Multiply and Divide
•
- Automatic Station Response
•
Operates as an SDLC Primary or
Secondary Station
The RUPI-44 family integrates a high performance 8-bit Microcontroller, the Intel 8051 Core, with an Intelligent/high performanceHDLC/SDLC serial communication controller, called the Serial Interface Unit (SIU).
See Figure 1. This dual architecture allows complex control and high speed data communication functions to
be realized cost effectively.
Specifically, the 8044's Microcontroller features: 4K byte On-Chip program memory space; 32 110 lines; two
16-bit timer I event counters; a 5-source; 2-level interrupt structure; a full duplex serial channel; a Boolean
processor; and on-Chip oscillator and clock circuitry. Standard TIL and most byte-oriented MCS-80 and MCS85 peripherals can be used for 110 amd memory expansion.
The Serial Interface Unit (SIU) manages the interface to a high speed serial link. The SIU offloads the On-Chip
8051 Microcontroller of communication tasks, thereby freeing the CPU to concentrate on real time control
tasks.
.
The RUPI-44 family consists of the 8044, 8744, and 8344. All three devices are identical except in respect of
on-chip program memory. The 8044 contains 4K bytes of mask-programmable ROM. User programmable
EPROM replaces ROM in the 8744. The 8344 addresses all program memory externally.
The RUPI-44 devices are fabricated with Intel's reliable
aged in a 40-pin DIP.
+ 5 volt,
silicon-gate HMOSII technology and pack-
The 8744H is available in a hermetically sealed, ceramic, 40-lead dual in-line package which includes a
window that allows for EPROM erasure when exposed to ultraviolet light (See Erasure Characteristics). During
normal operation, ambient light may adversely affect the functionality of the chip. Therefore applications which
expose the 8744H to ambient light may require an opaque label over the window.
8044'5 Dual Controller Architecture
HOLC/
SOLC
port
231663-1
Figure 1. Dual Controller Architecture
12-131
September 1990
Order Number: 231663-004
II
intel"
8044AH/8344AH/8744H
Table 1. RUPITM-44 Family Pin Description
-
DATA TxD (PS.1) In point-to-point or multipoint
configurations, this pin functions as data input!
output. In loop mode, it serves as transmit pin.
A '0' written to this pin enables diagnostic
mode.
-
verification.
INTO (PS.2). Interrupt 0 input or gate control
input for counter o.
-
INT1 (PS.S). Interrupt 1 input or gate control
input for counter 1.
PORTO
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and
data bus when using external memory. It is used
for data output during program verification. Port 0
can sinklsource eight LS TTL loads (six in 8744):
-
TO (PS.4). Input to counter
-
SCLK T1 (PS.5). In addition to 1/0, this pin provides input to counter 1 or serves as SCLK (serial clock) input.
-
WR (PS.6). The write control signal latches the
data byte from Port 0 into the External Data
Memory.
-
RD (PS.7). The read control signal enables External Data Memory to Port o.
VSS
Circuit ground potential.
vee
+ 5V power supply during operation
and program
PORT 1
Port 1 is an 8-bit quasi-bidirectional 1/0 port. It is
used for the low-order address byte during program verification. Port 1 can sinklsource four LS
TTL loads.
In non-loop mode two of the 1/0 lines serve alternate functions:
-
RTS (P1.6). RequesHo-Send output. A low indicates that the RUPI-44 is ready to transmit.
-
CTS (P1. 7) Clear-to-Send input. A low indicates
that a receiving station is ready to receive.
PORT 2
Port 2 is an 8-bit quasi-bidirection 1/0 port. It also
emits the high-order address byte when accessing
external memory. It is used for the high-order address and the control signals during program verification. Port 2 can sinklsource four LS TTL loads.
o.
RST
A high on this pin for two machine cycles while the
oscillator is running resets the device. A small external pulldown resistor (:::: 8.2Kfi) from RST to
Vss permits power-on reset when a capacitor
(:::: 10/Lf) is also connected from this pin to Vee.
ALE/PROG
Provides Address Latch Enable output used for
latching the address into external memory during
normal operation. It is activated every six oscillator
periods except during an external data memory access. It also receives the program pulse input for
programming the EPROM version.
PSEN
PORT 3
Port S is an 8-bit quasi-bidirectional 1/0 port. It also,
contains the interrupt, timer, serial port and RD
and WR pins that are used by various options. The
output latch corresponding to a secondary function
must be programmed to a one (1) for that function
to operate. Port Scan sinklsource four LS LTT
loads.
In addition to 1/0, some of the pins also serve alternate functions as follows:
-
1/0 RxD (PS.O). In pOint-to-point or multipoint
configurations, this pin controls the direction of
pin PS.1. Serves as Receive Data input in loop
and diagnostic modes.
The Program Store Enable output is a control signal that enables the external Program Memory to
the bus during external fetch operations. It is activated every six oscillator periods, except during
external data memory accesses. Remains high
during internal program execution.
EA/VPP
When held at a TTL high level, the RUPI-44 executes instructions from the internal ROM when the
PC is less than 4096. When held at a TTL low
level, the RUPI-44 fetches all instructions from external.Program Memory. The pin also receives the
21 V EPROM programming supply voltage on the
8744.
12-1S2
8044AH/8344AH/8744H
Table 1. RUPITM-44 Family Pin Description (Continued)
XTAL 1
XTAL2
Input to the oscillator's high gain amplifier. Required when a crystal is used. Connect to VSS
when external source is used on XTAL 2.
Output from the oscillator's amplifier. Input to the
internal timing circuitry. A crystal or external source
can be used.
.
pt.a
f};_
~:: ~c
...
...
..
-
.
..
~
~
TO
~
~
.
1;1
.
INT' ..........
seLK....!.!::
WR_
a::
2
-
i
-
Q
1iD __
PO.2
AD2
PO.3
AD3
Pt.S
pt.,
PO.•
PO.S
AD.
ADS
Pt.7
PO.'
PO.7
AOt
AD7
110
AXD
P3.a
Ii
DATA
TXD
INTO
P3.t
ALE
P302
IIIIfi
eTS
2 --
Pt 1
PU
AST
_.
=}@I
DATA~ __
~
~
m
i[~
..........
~r -~
~
iiTs
::I
_
Pt.2
vee
PO.D AOO
PO.t ADt
Pt.t
seLK
'v"
"lOG
INTt
P3.3
PU
AtS
TO
PU
,u
At.
Tt
P3.5
Wi!
iiii
P3.'
P3.7
'2.3
An
XTAL2
'2.2
Ata
XTALt
'2.t
p2.a
A'
~
'2.5 AU
P2 .• A12
vss
A'
231663-3
231663-2
Figure 3A. DIP Pin Configuration
Figure 2. Logic Symbol
...
N
"I; "l "! "": "!
~ ... "! c::i c:i c:i
ii: ii: ii: ii: ii: z >" ' 0
a.. a.. a.. a..
Pl.S
7
PO.4
Pl.6
8
PO.S
Pl.7
9
PO.6
RST/VPD
P3.0
10
PO.7
N/C
P3.1
12
11.
EA
8044
8344
13
N/C
ALE
PSEN
P3.2
14
P3.3
15
31
P2.7
P3.4
16
30
P2.6
P3.5
17
29
P2.S
CD I",.; ,.; ::l
a.. a.. <
..J
~
~ ><
...
0
-.t
~~
N "!
N
N N
> z N
a.. a.. a.. a.. a..
231663-21
Figure 3B. PLCC Pin Configuration
12-133
II
intel~
8044AH/8344AH/8744H
FREQUENCE
REFERENCE
r-I
DATA
I
I '-T----,,.-J
I
I Ior--r-.........-r'
1-+1--••
L.._",,?,:"_..J
I
I
L
INTERRUPTS
1/0
HDLCISDLC
SERIAL
COMMUNICATIONS
......-~---.I
1
I
I
1
1
TWO 16-BIT
TIMER EVENT
COUNTERS
~""""r-r-"'"
1_ _ _ _
INTERRUPTS
1
I
I
...J
CONTROL
COUNTERS
PARALLEL PORTS
ADDRESS DATA BUS
AND 1/0 PINS
231663-4
Figure 4_ Block Diagram
FUNCTIONAL DESCRIPTION
• 4K bytes of ROM
• 192 bytes of RAM
General
•
•
•
•
•
The 8044 integrates the powerful 8051 microcontroller with an intelligent Serial Communication Controller to provide a single-chip solution which will efficiently implement a distributed processing or distributed control system. The microcontroller is a selfsufficient unit containing ROM, RAM, ALU, and its
own peripherals. The 8044's architecture and instruction set are identical to the 8051 'so The 8044
replaces the 8051 's serial interface with an intelligent SOLC/HOLC Serial Interface Unit (SIU). 64
more bytes of RAM have been added to the 8051
RAM array. The SIU can communicate at bit rates up
to 2.4 M bps. The SIU works concurrently with the
Microcontroller so that there is no throughput loss in
either unit. Since the SIU possesses its own intelligence, the CPU is off-loaded from many of the communications tasks, thus dedicating more of its computing power to controlling .Iocal peripherals or some
external process.
32 I/O lines
64K address space for external Data Memory
64Kaddress space for external Program Memory
two fully programmable 16-bit timer/counters
a five-source interrupt structure with two priority
levels
• bit addressability for Boolean processing
SPECIAL
FUNCTION
,..............
REGISTERS
m 255
{O
DOH
R.M
CIH
COH
,..--J----., iii
INDIRECT
ADDRESS·
ING
241 FI"
FOH
EIH
EOH
DOH
"H
.OH
.IH
.OH
.....
ADDRESS-
BITS IN
SFA,
(1218IT5)
"H
,OH
IIH
'!.!!
135
128 80H
DIRECT
127
ADDRESSING
The Microcontroller
The microcontroller is a stand-alone high-performance single-chip computer intended for use in sophisticated real-time application such as instrumentation, industrial control, and intelligent computer peripherals.
INTERNAL
DATA RAM
The major features of the microcontroller are:
• 8-bit CPU
• on-chip oscillator
SPECIAL FUNCTION
REGISTERS
231663-5
Figure 5. Internal Data Memory Address Space
12-134
int:eL
8044AH/8344AH/8744H
• 1 /Ls instruction cycle time for 60% of the instructions 2 /Ls instruction cycle time for 40% of the
instructions
• 4 /Ls cycle time for 8 by 8 bit unsigned Multiply/
Divide
INTERNAL DATA MEMORY
Functionally the Internal Data Memory is the most
flexible of the address spaces. The Internal Data
Memory space is subdivided into a 256-byte Internal
Data RAM address space and a 128-bit Special
Function Register address space as shown in Figure
5.
The Internal Data RAM address space is 0 to 255.
Four 8-Register Banks occupy locations 0 through
31. The stack can be located anywhere in the Internal Data RAM address space. In addition, 128 bit
locations of the on-chip RAM are accessible through
Direct Addressing. These bits reside in Internal Data
RAM at byte locations 32 through 47. Currently locations 0 through 191 of the Internal Data RAM address space are filled with on-chip RAM.
Parallel 1/0
The 8044 has 32 general-purpose I/O lines which
are arranged into four groups of eight lines. Each
group is called a port. Hence there are four ports;
Port 0, Port 1, Port 2, and Port 3. Up to five lines
from Port 3 are dedicated to supporting the serial
channel when the SIU is invoked. Due to the nature
of the serial port, two of Port 3's I/O lines (P3.0 and
P3.1) do not have latched outputs. This is true
whether or not the serial channel is used.
Port 0 and Port 2 also have an alternate dedicated
function. When placed in the external access mode,
Port 0 and Port 2 become the means by which the
8044 communicates with external program memory.
Port 0 and Port 2 are also the means by which the
8044 communicates with external data memory. Peripherals can be memory mapped into the address
space and controlled by the 8044.
Table 2. MCS®-S1Instruction Set Description
Mnemonic
Description
ARITHMETIC OPERATIONS
ADD
A,Rn
Add register to
Accumulator
ADD
A,direct Add direct byte
to Accumulator
A,@Ri
ADD
Add indirect
RAM to
Accumulator
A,#data Add immediate
ADD
data to
Accumulator
AD DC A,Rn
Add register to
Accumulator
with Carry
AD DC A,direct Add direct byte
to A with Carry
flag
AD DC A,@Ri
Add indirect
RAM to A with
Carry flag
ADDC A,#data Add immediate
data to A with
Carry flag
SUBB A,Rn
Subtract register
from A with
Borrow
SUBB A,direct Subtract direct
byte from A with
Borrow
Byte Cyc
Mnemonic
Description
Byte Cyc
ARITHMETIC OPERATIONS (Continued)
SUBB A,@Ri
Subtract indirect
RAM from A with
Borrow
SUBB A,#data Subtract immed
data from A with
Borrow
2
INC
A
Increment
Accumulator
INC
Rn
Increment
register
INC
direct
Increment direct
byte
2
@Ri
INC
Increment
indirect RAM
DPTR
Increment Data
INC
Pointer
DEC
A
Decrement
Accumulator
DEC
Rn
Decrement
register
DEC
direct
Decrement
direct byte
2
@Ri
DEC
Decrement
indirect RAM
Multiply A & B
MUL
AB
DIV
AB
DivideAby B
DA
A
Decimal Adjust
Accumulator
2
2
2
2
2
12-135
2
1
4
4
int:eL
8044AH/8344AH/8744H
Table 2. MCS@·51 Instruction Set Description (Continued)
Mnemonic
Description
LOGICAL OPERATIONS
ANL A,Rn
AND register to
Accumulator
AND direct byte
ANL A,direct
to Accumulator
ANL A,@RI
AND indirect
RAM to
Accumulator
ANL A,#data
AND immediate
data to
Accumulator
ANL direct,A
AND
Accumulator to
direct byte
ANL direct, # data AND immediate
data to direct
byte
ORL A,Rn
OR register to
Accumulator
OR direct byte to
ORL A,direct
Accumulator
ORL A,@Ri
OR indirect RAM
to Accumulator
ORL A,#data
OR immediate
data to
Accumulator
OR Accumulator
ORL direct,A
to direct byte
ORL direct, # data OR immediate
data to direct
byte
Exclusive-OR
XRL A,Rn
register to
Accumulator
Exclusive-OR
XRL A,direct
direct byte to
Accumulator
XRL A,@RI
Exclusive-OR
indirect RAM to
A
Exclusive-OR
XRL A,#data
immediate data
toA
Exclusive-OR
XRL direct,A
Accumulator to
direct byte
XRL direct, # data Exclusive-OR
immediate data
to direct
CLR A
Clear
Accumulator
Complement
CPL A
Accumulator
Byte Cyc
Mnemonic
1
2
2
2
3
2
2
2
2
3
2
2
2
2
3
Description
LOGICAL OPERATIONS (Continued)
Rotate
RL
A
Accumulator
Left
Rotate A Left
RLC A
through the
Carry flag
RR
A
Rotate
Accumulator
Right
RRC A
Rotate A Right
through Carry
flag
Swap nibbles
SWAP A
within the
Accumulator
DATA TRANSFER
Move register to
MOV A,Rn
Accumulator
Move direct byte
MOV A,direct
to Accumulator
Move indirect
MOV A,@RI
RAM to
Accumulator
Move immediate
MOV A,#data
data to
Accumulator
Move
MOV Rn,A
Accumulator to
register
Move direct byte
MOV Rn,direct
to register
Move immediate
MOV Rn,#data
data to register
Move
MOV direct,A
Accumulator to
direct byte
Move register to
MOV direct,Rn
direct byte
MOV direct,direct Move direct byte
to direct
Move indirect
MOV direct,@Ri
RAM to direct
byte
MOV direct,#data Move immediate
data to direct
byte
Move
MOV @Ri,A
Accumulator to
indirect RAM
Move direct byte
MOV @Ri,direct
to indirect RAM
2
12-136
Byte Cyc
2
2
2
2
2
2
2
2
3
2
2
2
3
2
2
2
intel·
8044AH/8344AH/8744H
Table 2. MCS®-S1 Instruction Set Description (Continued)
Mnemonic
Description
DATA TRANSFER (Continued)
Move immediate
MOV @Ri,#data
data to indirect
RAM
MOV DPTR,#data16Load Data
Pointer with a
16-bit constant
MOVCA,@A+DPTR Move Code byte
relative to DPTR
toA
MOVCA,@A+PC
Move Code byte
relative to PC to
A
MOVXA,@Ri
Move External
RAM (8-bit addr)
toA
MOVXA,@DPTR
Move External
RAM (16-bit
addr) to A
MOVX@Ri,A
Move A to
External RAM
(8-bit addr)
MOVX @DPTR,A
Move A to
External RAM
(16-bit) addr
Push direct byte
PUSH direct
onto stack
Pop direct byte
POP direct
from stack
Exchange
XCH A,Rn
register with
Accumulator
Exchange direct
XCH A,direct
byte with
Accumulator
Exchange
XCH A,@Ri
indirect RAM
with A
XCHDA,@Ri
Exchange loworder Digit ind
RAMwA
ByteCyc
Mnemonic
Byte Cyc
BOOLEAN VARIABLE MANIPULATION
(Continued)
ANL
C,/bit
AND
complement of
direct bit to
Carry
2
ORL
C/bit
OR direct bit to
Carry flag
2
C,/bit
OR complement
ORL
of direct bit to
Carry
2
Move direct bit
MOV C,/bit
to Carry flag
2
MOV bit,C
Move Carry flag
to direct bit
2
2
3
Description
2
2
2
2
2
2
2
2
PROGRAM AND MACHINE CONTROL
ACALL addr11
Absolute
Subroutine Call
LCALL addr16
Long Subroutine
Call
RET'
Return from
subroutine
RETI
Return from
interrupt
AJMP addr11
Absolute Jump
LJMP addr16
Long Jump
Short Jump
SJMP rei
(relative addr)
@A+ DPTR Jump indirect
JMP
relative to the
DPTR
JZ
rei
Jump if
Accumulator is
Zero
Jump if
JNZ
rei
Accumulator is
Not Zero
rei
Jump if Carry
JC
flag is set
JNC
rei
Jump if No Carry
flag
JB
bit,rel
Jump if direct Bit
set
bit,rel
Jump if direct Bit
JNB
Not set
bit,rel
Jump if direct Bit
JBC
is set & Clear bit
CJNE A,direct,rel Compare direct
to A & Jump if
Not Equal
CJNE A, # data, rei Comp, immed,
to A & Jump if
Not Equal
2
2
2
2
2
2
2
2
BOOLEAN VARIABLE MANIPULATION
Clear Carry flag
1
CLR C
Clear direct bit
2
CLR bit
Set Carry Flag
SETB C
SETB bit
Set direct Bit
2
CPL C
Complement
Carry Flag
Complement
CPL bit
2
direct bit
AND direct bit to
ANL C,bit
Carry flag
2
2
12-137
2
2
3
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
2
3
2
3
2
3
2
3
2
intet
8044AH/8344AH/8744H
Table 2. MCS®-S1 Instruction Set Description (Continued)
Mnemonic
Description
Byte Cyc
PROGRAM AND MACHINE CONTROL
(Continued)
CJNE Rn,#data,rel Comp, immed,
to reg & Jump if
Not Equal
CJNE @Ri,#data, rei Comp, immed,
to ind.& Jump if
Not Equal
DJNZ Rn,rel
Decrement
register & Jump
if Not Zero
DJNZ direct, rei
Decrement
direct & Jump if
Not Zero
NOP
No operation
3
2
3
2
2
2
3
1
2
1
Notes on data addressing modes:
(Continued)
# data - 8-bit constant included in instruction
#data16-16-bit constant included as bytes 2
& 3 of instruction
bit
- 128 software flags, any I/O pin, controll or status bit
Notes on program addressing modes:
addr16 - Destination address for LCALL &
LJMP may be anywhere within the
64-K program memory address
space
Addr11 - Destination address for ACALL &
AJMP will be within the same 2-K
page of program memory as the first
byte of the following instruction
rei
- SJMP and all conditional jumps include an 8-bit offset byte, Range is
+ 127 -128 bytes relative to first
byte of the following instruction
Notes on data addressing modes:
Rn
- Working register RO-R7
direct
- 128 internal RAM locations, any I/O
port, control or status register
@Ri
- Indirect internal RAM location addressed by register RO or R1
All mnemonic copyrighted© Intel Corporation 1979
TimerICounters
Serial Interface Unit (SIU)
The 8044 contains two 16-bit counters which can be
used for measuring time intervals, measuring pulse
widths, counting events, generating precise periodic
interrupt requests, and clocking the serial communications. Internally the Timers are clocked at 1/12 of
the crystal frequency, which is the instruction cycle
time. Externally the counters can run up to 500 KHz.
The Serial Interface Unit is used for HDLC/SDLC
communications. It handles Zero Bit Insertion/Deletion, Flags automatic access recognization, and a
16-bit cyclic redundancy check. In addition it implements in hardware a subset of the SDLC protocol
certain applications it is advantageous to have the
CPU control the reception or transmission of every
single frame. For this reaSOn the SIU has two modes
of operation: "AUTO" and "FLEXIBLE" (or "NONAUTO"). It is in the AUTO mode that the SIU responds to SDLC frames without CPU intervention;
whereas, in the FLEXIBLE mode the reception or
transmission of every single frame will be under CPU
control.
Interrupt System
External events and the real-time driven on-chip peripherals require service by the CPU asynchronous
to the execution of any particular section of code. To
tie the asynchronous activities of these functions to
normal program execution, a sophisticated multiplesource, two priority level, nested interrupt system is
provided. Interrupt response latency ranges from 3
Jlosec to 7 Jlosec when ·using a 1.2 MHz clock.
All five interrupt sources can be mapped into one of
the two priority levels. Each interrupt source can be
enabled or disabled individually or the entire interrupt system can be enabled or disabled. The five
interrupt sources are: Serial Interface Unit, Timer 1,
Timer 2, and two external interrupts. The external
interrupts can be either level or edge triggered.
There are three control registers and eight parameter registers that are used to operate the serial interface. These registers are shown in Figure 5 and Figure 6. The control register set the modes of operation and provide status information. The eight parameter registers buffer the station address, receive
and transmit control bytes, and point to the on-chip
transmit and receive buffers.
Data to be received or transmitted by the SIU must
be buffered anywhere within the 192 bytes of onchip RAM. Transmit and receive buffers are not allowed to "wrap around" in RAM; a "buffer end" is
generated after address 191 is reached.
12-138
int:el.
8044AH/8344AH/8744H
SYMBOLIC
ADDRESS
REGISTER NAMES
B REGISTER
ACCUMULATOR
·THREE BYTE FIFO
B
ACC
FIFO
FIFO
FIFO
TBS
TBL
TCB
SIUST
NSNR
PSW·
DMA CNT
STAD
RFL
RBS
RBL
RCB
SMD
STS
IP
P3
IE
P2
PI
THI
THO
TRANSMIT BUFFER START
TRANSMIT BUFFER LENGTH
TRANSMIT CONTROL BYTE
• SIU STATE COUNTER
SEND COUNT RECEIVE COUNT
PROGRAM STATUS WORD
·DMA COUNT
STATION ADDRESS
RECEIVE FIELD LENGTH
RECEIVE BUFFER START
RECEIVE BUFFER LENGTH
RECEIVE CONTROL BYTE
SERIAL MODE
STATUS REGISTER
INTERRUPT PRIORITY CONTROL
PORT 3
INTERRUPT ENABLE CONTROL
PORT 2
PORT 1
TIMER HIGH 1
TIMER HIGH 0
TIMER LOW 1
TIMER LOW 0
TIMER MODE
TIMER CONTROL
DATA POINTER HIGH
DATA POINTER LOW
STACK POINTER
PORT 0
BYTE
ADDRESS
BIT ADDRESS
20;
th,ough
th'Ough
2CO
124
115
th,oUllh
208
th,ough
ii
th,ough
th,ough
141
Tl1
TLO
TMOD
TCON
DPH
OPt.
SP
PO
2CO
224
223
222
221
220
219
21B
217
216
208
207
206
205
204
203
202
201
200
184
176
168
160
144
143
,",oug"
'''
135
th,ough
128
140
139
13B
137
136
131
130
129
12B
IFOH)
IEOH)
IDFH)
IDEH)
IDDH)
lOCH)
IDBH)
IDAH)
ID9H)
(D8H)
(DOH)
ICFH)
ICEH)
ICDH)
ICCH)
ICBH)
(CAH)
IC9H)
IC8H)
IB8H)
IBOH)
IA8H)
IAOH)
I90H)
18DH)
IBCH)
IBBH)
IBAH)
(B9H)
I6BH)
IB3H)
IB2H)
IB1H)
IBOH)
SFR's CONTAINING
DIRECT ADDRESSABLE BITS
III
231663-6
NOTE:
*ICE Support Hardware registers. Under normal operating conditions there is no need for the CPU to access these
registers.
Figure 5. Mapping of Special Function Registers
SERIAL MODE REGISTER (SMD) SCM2
SCMl
SCMO
NRZI
LOOP
PFS
I I
STATUS REGISTER ISTS)
TBF
RBE
RTS
SI
BOV
I
NB
I
OPB
AM
I
I
NFCS
'---- NO FRAME CHECK SEQUENCE
NON-BUFFERED
PRE·FRAME EYNC
LOOP
NON RETURN TO ZERO INVERTED
SELECT CLOCK MODE
RBP
L - RECEIVE BUFFER PROTECT
AUTO MODE/ADDRESSED MODE
OPTIONAL POLL BIT
RECEIVE INFORMATION BUFFER OVERRUN
SERIAL INTERFACE UNIT INTERRUPT
REQUEST TO SEND
RECEIVE BUFFER EMPTY
TRANSMIT BUFFER FULL
SEND COUNT RECEIVE
COUNT REGISTER (NSNR) . .=-r-;;;;:-r:=:T7i;;;-r::;;;:;;-r-;;;;;-r;;;;;;;-r70""
SEQUENCE ERROR RECEIVED
' - - - ' - - - ' - - - - - RECEIVE SEQUENCE COUNTER
' - - - - - - - - - - - - - SEQUENCE ERROR SEND
'--~--'---------------- SEND SEQUENCE COUNTER
231663-7
Figure 6. Serial Interface Unit Control Registers
12-139
intel~
8044AH/8344AH/8744H
With the addition of only a few bytes of code, the
8044's frame size is not limited to the size of its
internal RAM (192 bytes), but rather by the size of
external buffer with no degradation of the RUPI's
features (e.g. NRZI, zero bit insertion/deletion, address recognition, cyclic redundancy check). There
is a special function register .called SIUST whose
contents dictates the operation of the SIU. At low
data rates, one section of the SIU (the Byte Processor) performs no function during known intervals.
For a given data rate, these intervals (stand-by
mode) are fixed. The above characteristics make it
possible to program the CPU to move data to/from
external RAM and to force the SIU to perform some
desired hardware tasks while transmission or reception is taking place. With these modifications, external RAM can be utilized as a transmit and received
buffer instead of the internal RAM.
When the Receive Buffer Empty bit (RBE) indicates
that the Receive Buffer is empty, the receiver is enabled, and when the RBE bit indicates that the Receive Buffer is full, the receiver is disabled. Assuming that the Receiver Buffer is empty, the SIU will
respond to a poll with an I frame if the Transmit Buffer is full. If the Transmit Buffer is empty, the SIU will
respond to a poll with a RR command if the Receive
Buffer Protect bit (RBP) is cleared, or an RNR command if RBP is set.
AUTO Mode
In the FLEXIBLE mode all communications are under control of the CPU. It is the CPU's task to encode and decode control fields, manage acknowledgements, and adhere to the requirements of the
HOLC/SOLC protocols. The 8044 can be used as a
primary or a secondary station in this mode.
In the AUTO mode the SIU implements in hardware
a subset of the SOLC protocol such that it responds
to many SOLC frames without CPU intervention. All
AUTO mode responses to the primary station will
comform to IBM's SOLC definition. The advantages
of the AUTO mode are that less software is required
to implement a secondary station, and the hardware
generated response to polls is much faster than doing it in software. However, the Auto mode can not
be used at a primary station.
To transmit in the AUTO mode the CPU must load
the Transmit Information Buffer, Transmit Buffer
Start register, Transmit Buffer Length register, and
set the Transmit Buffer Full bit. The SIU automatically responds to a poll by transmitting an information
frame with the P/F bit in the control field set. When
the SIU receives a positive acknowledgement from
the primary station, it automatically increments the
Ns field in the NSNR register and interrupts the
CPU. A negative acknowledgement would cause the
SIU to retransmit the frame.
To receive in the AUTO mode, the CPU loads the
Receive Buffer Start register, the Receive Buffer
Length register, clears the Receive Buffer Protect
bit, and sets the Receive Buffer Empty bit. If the SIU
is polled in this state, and the TBF bit indicates that .
the Transmit Buffer is empty, an automatic RR response will be generated. When a valid information
frame is received the SIU will automatically increment Nr in the NSNR register and interrupt the CPU.
While in the AUTO mode the SIU can recognize and
respond to the following commands without CPU intervention: I (Information), RR .(Receive Ready),
RNR (Receive Not Ready), REJ (Reject), and UP
(Unnumbered Poll). The SIU can generate the fol-
lowing responses without CPU intervention: I (Information), RR (Receive Ready), and RNR (Receive
Not Ready).
FLEXIBLE (or NON-AUTO) Mode
To receive a frame in the FLEXIBLE mode, the CPU
must load the Receive Buffer Start register, the Receive Buffer Length register, clear the Receive Buffer Protect bit, and set the Receive Buffer Empty bit.
If a valid opening flag is received and the address
field matches the byte in the Station Address register or the address field contains a broadcast address, the 8044 loads the control field in the receive
control byte register, and loads the I field in the receive buffer. If there is no CRC error, the SIU interrupts the CPU, indicating a frame has just been received. If there is a CRC error, no interrupt occurs.
The Receive Field Length register provides the number of bytes that were received in the information
field.
To transmit a frame, the CPU must load the transmit
information buffer, the Transmit Buffer Start register,
the Transmit Buffer Length register, the Transmit
Control Byte, and set the TBF and the RTS bit. The
SIU, unsolicited by an HOLC/SOLC frame, will transmit the entire information frame, and interrupt the
CPU, indicating the completion of transmission. For
supervisory frames or unnumbered frames, the
transmit buffer length would be O.
CRC
The FCS register is initially set to all 1's prior to calculating the FCS field. The SIU will not interrupt the
CPU if a CRC error occurs (in both AUTO and FLEXIBLE modes). The CRC error is cleared upon receiving of an opening flag.
12-140
8044AH/8344AH/8744H
Frame Format Options
In addition to the standard SDLC frame format, the
8044 will support the frames displayed in Figure 7.
The standard SDLC frame is shown at the top of this
figure. For the remaining frames the information field
will incorporate the control or address bytes and the
frame check sequences; therefore these fields will
be stored in the Transmit and Receive buffers. For
example, in the non-buffered mode the third byte is
treated as the beginning of the information field. In
the non-addressed mode, the information field begins after the opening flag. The mode bits to set the
frame format options are found in the Serial Mode
register and the Status register.
NFCS
NB
AM1
Standard SOLC
NON-AUTO Mode
0
0
0
I F IA IC I
I
I FCS I F I
Standard SOLC
AUTO Mode
0
0
1
I F IA IC I
I
I FCS I F I
Non-Buffered Mode
NON-AUTO Mode
0
1
1
IF IA I
Non-Addressed Mode
NON-AUTO Mode
0
1
0
IF I
No FCS Field
NON-AUTO Mode
1
0
0
I F IA IC I
I
I
F
I
No FCSFleld
AUTO Mode
1
0
1
I F I A I c-I
I
I
F
I
No FCS Field
Non-Buffered Mode
NON-AUTO Mode
1
1
1
IF IA I
No FCSField
Non-Addressed Mode
NON-AUTO Mode
1
1
0
IF I
FRAME OPTION
Mode
AM
NB
NFCS
Key
F=
A=
C=
FRAME FORMAT
I FCS I
I
I FCS I
I
I
I
F
F
F
I
I
I
•
I
I
F
I
I
Bits:
- "AUTO" Mode/Addressed Mode
- Non-Buffered Mode
- No FCS Field Mode
to Abbreviations:
Flag (01111110)
Address Field
Control Field
I = Information Field
FCS= Frame Check Sequence
Note 1:
The AM bit function is controlled by the NB bit. When NB = 0, AM becomes AUTO mode select, when NB = 1, AM
becomes Address mode select.
Figure 7. Frame Format Options
12-141
II
intel .
8044AH/8344AH/8744H
transmit and receive data in this mode at rates up to
2.4 Mbps.
Extended Addressing
To .realize an extended control field or an extended
address field using the HDLC protocol, the FLEXIBLE mode must be used. For an extended control
field, the SIU is programmed to be in the non-buffered mode. The extended control field will be the
first and second bytes in the Receive and Transmit
Buffers. For extended addressing the SIU is placed
in the non-addressed mode. In this mode the CPU
must implement the address recognition for received
frames. The addressing field will be the initial bytes
in the Transmit -and Receive buffers followed by the
control field.
The SIU can transmit and receive only frames which
are multiples of 8 bits. For frames received with other than 8-bit multiples, a CRC error will cause the
SIU to reject the frame.
SOLC Loop Networks
The SIU can be used in an SDLC loop as a secondary or primary station. When the SIU is placed in the
Loop mode it receives the data on pin 10 and transmits the data one bit time delayed on pin 11. It can
also recognize the Go ahead signal and change it
into a flag when it is ready to transmit. As a secondary station the SIU can be used in the AUTO or
FLEXIBLE modes. Asa primary station the FLEXIBLE mode is used; however, additional hardware is
required for generating the Go Ahead bit pattern. In
the Loop mode the maximum data rate is 1 Mbps
clocked or 375 Kpbs self-clocked.
This self clocked mode allows data transfer without
a common system data clock. An on-chip Digital
Phase Locked Loop is employed to recover the data
clock which is encoded in the data stream. The
DPLL will converge to the nominal bit center within
eight bit transitions, worst case. The DPLL requires a
reference clock of either 16 times (16x) or 32 times
(32x) the data rate. This reference clock may be externally applied or internally generated. When internally generated either the 8044's internal logic clock
(crystal frequency divided by two) or the timer 1
overflow is used as the reference clock. Using the
internal timer 1 clock the data rates can vary from
244 to 62.5 Kbps. Using the internal logic clock at a
16x sampling rate, receive data can either be 187.5
Kbps, or 375 Kbps. When the reference clock for the
DPLL is externally applied the data rates can vary
from 0 to 375 Kbps at a 16x sampling rate.
To aid in a Phase Locked Loop capture, the SIU has
a NRZI (Non Return to Zero Inverted) data encoding
and decoding option. Additionally the SIU has a preframe sync option that transmits two bytes of alternating 1's and O's to ensure that the receive station
. DPLL will be synchronized with the data by the time
it receives the opening flag.
Control and Status Registers
. There are three SIU Control and Status Registers:
Serial Mode Register (SMD)
Status/Command Register (STS)
SOLC Multidrop Networks
Send/Receive Count Register (NSNR)
The SIU can be used in a SDLC non-loop configuration as a secondary or primary station. When the SIU
is placed in the non-loop mode, data is received and
transmitted on pin 11, and pin 10 drives a tri-state
buffer. In non-loop mode, modem interface pins,
RTS and CTS, become available.
The SMD, STS, and NSNR, registers are all cleared
by system reset. This assures that'the SIU will power
up in an idle state (neither receiving. nor transmitting).
OataClocking Options
These registers and their bit assignments are described below.
SMD: Serial Mode Register (byte-addressable)
The 8044's serial port can operate in an externally
clocked or self clocked system. A clocked system
provides to the 8044 a clock synchronization to the
data. A self-clocked system uses the 8044's on-chip
Digital Phase Locked Loop (DPLL) to recover the
clock from the data, and clock this data into the Serial Receive Shift Register.
In this mode, a clock synchronized with the data is
externally fed into the 8044. This clock may be generated from an External Phase Locked Loop, or possibly supplied along with the data. The 8044 can
Bit 7:
6
5
4
3
2
1
0
ISCM21sCM11sCMO I NRZII LOOP I PFsl NBI NFCsl
The Serial Mode Register (Address C9H) selects the
operational modes of the SIU. The 8044 CPU can
both read and write SMD. The SIU can read SMD
but cannot write to it. To prevent conflict between
CPU and SIU access to SMD, the CPU should write
SMD only when the Request To Send (RTS) and
12-142
int:eL
8044AH/8344AH/8744H
Receive Buffer Empty (RBE) bits (in the STS register) are both false (0). Normally, SMD is accessed
only during initialization.
The individual bits of the Serial Mode Register are as
follows:
Bit#
Name Description
SMD.O NFCS No FCS field in the SDLC frame.
SMD.1
NB
SMD.2 PFS
CPU, and enables the SIU to post status information
for the CPU's access. The SIU can read STS, and
can alter certain bits, as indicated below. The CPU
can both read and write STS asynchronously. However, 2-cycle instructions that access STS during
both cycles ('JBC/B, REL' and 'MOV IB, C.') should
not be used, since the SIU may write to STS between the two CPU accesses.
The individual bits of the Status/Command Register
are as follows:
Non-Buffered mode. No control
field in the SDLC frame.
Pre-Frame Sync mode. In this
mode, the 8044 transmits two
bytes before the first flag of a
frame, for DPLL synchronization.
If NRZI is enabled, OOH is sent;
otherwise, 55H is sent. In either
case, 16 preframe transitions are
guaranteed.
Bit#
Name
Description
STS.O
RBP
Receive Buffer Protect. Inhibits
writing of data into the receive
buffer. In AUTO mode, RBP
forces an RNR response instead
of an RR.
STS.1
AM
AUTO Model Addressed Mode.
Selects AUTO mode where
AUTO mode is allowed. If NB is
true, (= 1), the AM bit selects the
addressed mode. AM may be
cleared by the SIU.
SMD.3 LOOP Loop configuration:
SMD.4 NRZI NRZI coding option. If bit = 1,
NRZI coding is used. If bit = 0,
then it is straight binary (NRZ).
SMD.5 SCMO Select Clock Mode-Bit 0
SMD.6 SCM1
STS.2
OPB
Optional Poll Bit. Determines
whether the SIU will generate an
AUTO response to an optional
poll (UP with P = 0). OPM may
be set or cleared by the SIU.
STS.3
BOV
Receive Buffer Overrun. BOV
may be set or cleared by the SIU.
STS.4
SI
SIU Interrupt. This is one of the
five interrupt sources to the CPU.
The vector location = 23H. SI
may be set by the SIU. It should
be cleared by the CPU before
returning from an interrupt
routine.
STS.5
RTS
Request To Send. Indicates that
the 8044 is ready to transmit or is
transmitting. RTS may be read or
written by the CPU. RTS may be
read by the SIU, and in AUTO
mode may be written by the SIU.
STS.6
RBE
Receive Buffer Empty. RBE can
be thought of as Receive Enable.
RBE is set to one by the CPU
when it is ready to receive a
frame, or has just read the buffer,
and to zero by the SIU when a
frame has been received.
STS.7
TBF
Transmit Buffer Full. Written by
the CPU to indicate that it has
filled the transmit buffer. TBF may
be cleared by the SIU.
Select Clock Mode-Bit 1
SMD.7 SCM2 Select Clock Mode-Bit 2
The SCM bits decode as follows:
SCM
2
0
0
0
0
1
1
1
1
Data Rate
1 0 Clock Mode
(Bits/sec)'
0 0 Externally clocked
0-2.4M"
0 1 Reserved
1 0 Self clocked, timer overflow 244-62.5K
1 1 Reserved
0 0 Self clocked, external 16x
0-375K
0 1 Self clocked, external 32x
0-187.5K
1 0 Self clocked, internal fixed
375K
1 1 Self clocked, internal fixed
187.5K
NOTES:
'Based on a 12 Mhz crystal frequency
"0-1 M bps in loop configuration
STS: Status/Command Register (bitaddressable)
Bit:
7
6
5
4
3
2
1
0
ITBF IRBE IRTS ISI IBOV IOPB IAM IRBP I
The StatuslCommand Register (Address C8H) provides operational control of the SIU by the 8044
12-143
II
8044AH/8344AH/8744H
NSNR: Send/Recelye Count Register (blt~
addressable)
7
B~
6
5
4
3
2
1
TBS: Transmit Buffer Start Address Register
(byte-addressable)
0
INS21NS11NsoisESINR21NR11NROIsERI
The Send/Receive Count Register (Address D8H)
contains the transmit and receive sequence numbers, plus tally error indications. The SIU can both
read and write NSNR. The 8044 CPU can both read
and write NSNR asynchronously. However, 2-cycle
instructions that access NSNR during both cycles
(,JBC /B, REl,' and 'MOV IB,C') should not be
used, since the SIU may write to NSMR between the
two 8044 CPU accesses.
The individual bits of the Send/Receive Count Register are as follows:
Bit #
Name Description
NSNR.O SER
Receive Sequence Error:
NS (P) =F NR (S)
NSNR.1 NRO
Receive Sequence Counter-Bit 0
NSNR.2 NR1
Receive Sequence Counter-Bit 1
NSNR.3 NR2
Receive Sequence Counter-Bit 2
NSNR.4 SES
Send Sequence Error:
NR (P) =F NS (S) and
NR (P) =F NS (S) + 1
NSNR.5 NSO
Send Sequence Counter-Bit 0
NSNR.6 NS1
Send Sequence Counter-Bit 1
NSNR.7 NS2
Send Sequence Counter-Bit 2
The Transmit Buffer Start address register. (Address
DCH) points to the location in on-chip RAM for the
beginning of the I-field of the frame to be transmitted. The CPU should access TBS only when the SIU
is not transmitting a frame (when TBF = 0).
TBl: Transmit Buffer length Register
(byte = addressable)
The Transmit Buffer length register (Address DBH)
contains the length (in bytes) of the I-field to be
transmitted. A blank I-field (TBl = 0) is valid. The
CPU should access TBl only when the SIU is not
transmitting a frame (when :rBF = 0).
NOTE:
The transmit and receive buffers are not allowed to
"wrap around" in the on-Chip RAM. A "buffer end"
is automatically generated if address 191 (BFH) is
reached.
TCB: Transmit Control Byte Register
(byte-addressable)
The Transmit Control Byte register (Address DAH)
contains the byte which is to be placed in the control
field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB
only when the SIU is not transmitting a frame (when
TBF = 0). The Nsand NR counters are not used in
the NON-AUTO mode.
RBS: Receive Buffer Start Address Register
(byte-addressable)
Parameter Registers
There are eight parameter registers that are used in
connection with SIU operation. All eight registers
may be read or written by the 8044 CPU. RFl and
RCB are normally loaded by the SIU.
The eight parameter registers are as follows:
The Receive Buffer Start address register (Address
CCH) pOints to the location in on-chip RAM where
the beginning of the I-field of the frame being received is to be stored. The CPU should write RBS
only when the SIU is not receiving a frame (when
RBE = 0).
RBl: Receive Buffer length Register
STAD: Station Address Register
(byte-addressable)
(~yte-addressable)
The Station Address· register (Address CEH) contains the. station address. To prevent acess conflict,
the CPU should access STAD only when the SIU is
idle (RTS = 0 and RBE =0). Normally, STAD is
accessE!d only during initialization.
The Receive Buffer length register (Address CBH)
contains the length (in bytes) of the area in on-chip
RAM allocated for the received I-field. RBl=O is
valid. The CPU should write RBl only when RBE = O.
12-144
intet
8044AH/8344AH/8744H
RFL: Receive Field Length Register
(byte-addressable)
The Receive Field Length register (Address CDH)
contains the length (in bytes) of the received I-field
that has just been loaded into on-chip RAM. RFL is
loaded by the SIU. RFL = 0 is valid. RFL should be
accessed by the CPU only when RBE = o.
RCB: Receive Control Byte Register
(byte-addressable)
The Received Control Byte register (Address CAH)
contains the control field of the frame that has just
been received. RCB is loaded by the SIU. The CPU
can only read RCB, and should only access RCB
when RBE = o.
The emulator operates with Intel's Inteliec™'development system. The development system interfaces
with the user's 8044 system through an in-cable
buffer box. The cable terminates in a 8044 pin-compatible plug, which fits into the 8044 socket in the
user's system. With the emulator plug in place, the
user can excercise his system in real time while collecting up to 255 instruction cycles of real-time data.
In addition, he can single-step the program.
Static RAM is available (in the in-cable buffer box) to
emulate the 8044 internal and external program
memory and external data memory. The designer
can display and alter the contents of the replacement memory in the buffer box, the internal data
memory, and the internal 8044 registers, including
the SFR's.
SIUST: SIU State Counter (byte-addressable)
ICE Support
The 8044 In-CircuIt Emulator (ICE-44) allows the
user to exercise the 8044 application system and
monitor the execution of instructions in real time.
The SIU State Counter (Address D9H) reflects the
state of the internal logic which is under SIU controL
Therefore, care must, be taken not to write into this
register. This register provides a useful means for
debugging 8044 receiver problem.
12-145
II
intel~
8044AH/8344AH/8744H
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Ambient Temperature Under Bias ...... O°C to 70°C
Storage Temperature ........... - 65°C to -' 150°C
Voltage on EA, VPP Pin to VSS ... - 0.5V to - 21.5V
Voltage on Any Other Pin to VSS .... - 0.5V to -7V
Power Dissipation ........................... 2W
D.C. CHARACTERISTICS
TA
=
"WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
O°C to 70°C, VCC
Parameter
Symbol
=
5V
=
10%, VSS
=
OV
Min
Max
Unit
-0.5
0.8
V
0
0.8
V
VIL
Input Low Voltage (Except EA Pin of 8744H)
VIL1
Input Low Voltage to EA Pin of8744H
VIH
Input High Voltage (Except XTAL2, RST)
2.0
VCC
VIH1
Input High Voltage to XTAL2, RST
2.5
VCC
VOL
Output Low Voltage (Ports 1,2, 3)"
VOL1
Output Low Voltage (Port O,ALE,PSEN)"
8744H
8044AH/8344AH
+
+
0.5
V
0.5
V
XTAL1
0.45
V
IOL
=
1.6mA
0.60
0.45
V
V
IOL
IOL
=
=
3.2 mA
2.4 mA
0.45
V
= 3.2mA
= -80/LA
IOH = -400/LA
VOH
Output High Voltage (Ports 1, 2, 3)
2.4
V
VOH1
Output High Voltage (Port 0 in External
Bus Mode, ALE, PSEN)
2.4
V
"L
Logical 0 Input Current (Ports 1, 2, 3)
-500
/LA
"L1
Logical 0 Input Current to EA Pin
of 8744H only
-15
mA
"L2
Logical 0 Input Current (XTAL2)
-3.6
III
Input Leakage Current (Port 0)
8744H
8044AH/8344AH
VSS
IOL
IOH
=
0.45V
mA
Yin
=
0.45V
±100
±10
/LA
/LA
0.45
0.45
Logical 1 Input Current to EA Pin of 8744H
500
/LA
"H1
Input Current to RST to Activate Reset
500
/LA
ICC
Power Supply Current:
8744H
8044AH/8344AH
285
170
mA
mA
10
pF
Pin Capacitance
=
Yin
"H
CIO
Test Conditions
Yin
< Vin < VCC
< Yin < VCC
< (VCC
- 1.5V)
A" Outputs Disconnected: EA = VCC
Test Freq.
=
1 MHz(1)
"NOTES:
1. Sampled not 100% tested. TA = 25'C.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pin when these pins make 1-too transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
12-146
int:eL
8044AH/8344AH/8744H
A.C. CHARACTERISTICS
T A = O·C to + 70·C, VCC = 5V ± 10%, VSS = OV, Load Capacitance for Port 0, ALE, and PSEN
Load Capacitance for All Other Outputs = 80 pF
= 100 pF,
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHzOsc
Min
Max
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
Min
Unit
Max
TLHLL
ALE Pulse Width
127
2TCLCL-40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL-40
ns
TLLAX1
Address Hold After ALE Low
48
TCLCL-35
TLLlV
ALE Low to Valid Instr in
8744H
8044AH/8344AH
ns
ns
183
233
4TCLCL-150
4TCLCL-100
TLLPL
ALE Low to PSEN Low
58
TCLCL-25
ns
TPLPH
PSEN Pulse Width
8744H
a044AH/8344AH
190
215
3TCLCL-60
3TCLCL-35
ns
ns
TPLIV
TPXIX
PSEN Low to Valid Instr in
8744H
8044AH/8344AH
Input Instr Hold After PSEN
TPXIZ2
Input Instr Float After PSEN
TPXAV2
PSEN to Address Valid
TAVIV
Address to Valid Instr in
8744H
8044AH/8344AH
TAZPL
Address Float to PSEN
100
125
0
3TCLCL-150
3TCLCL-125
ns
0
TCLCL-20
63
75
-25
5TCLCL-150
5TCLCL-115
-25
ns
ns
TCLCL-8
267
302
ns
ns
ns
ns
ns
NOTES:
1. TLLAX for access to program memory is different from TLLAX for data memory.
2. Interfacing RUPI-44 devices with float times up to 75ns is permissible. This limited bus contention will not cause any
damage to Port 0 drivers.
12-147
II
8044AH/8344AH/8744H
EXTERNAL DATA MEMORY CHARACTERISTICS
Symbol
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
12 MHzOsc
Parameter
Min
Max
Min
Unit
Max
TRLRH
RD Pulse Width
400
6TCLCL-100
TWLWH
WR Pulse Width
400
6TCLCL-100
ns
TLLAX
Address Hold after ALE
48
TCLCL-35
ns
TRLDV
RD Low to Valid Data in
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
TAVDV
TLLWL
ALE Low to RD or WR Low
200
TAVWL
Address to RD or WR Low
203
4TCLCL-130
ns
TQVWX
Data Valid to WR Transition
8744H
8044AH/8344AH
13
23
TCLCL-70
TCLCL-60
ns
ns
TQVWH
Data Setup Before WR High
433
7TCLCL-150
ns
TWHQX
Data Held After WR
33
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
8744H
8044AH/8344AH
ns
252
5TCLCL-165
ns
97
2TCLCL-70
ns
ALE Low to Valid Data In·
517
8TCLCL-150
ns
Address to Valid Data In
585
9TC!-CL-165
ns
3TLCLCL+50
ns
0
0
300
ns
3TCLCL-50
TCLCL-50
ns
25
33
43
133
123
TCLCL-50
TCLCL-40
25
ns
TCLCL+50
TCLCL+50
ns
ns
NOTE:
1. TLLAX for access to program memory is different from TLLAX for access data memory.
Serial Interface Characteristics
Symbol
TDCY
Parameter
Min
Data Clock
420
Max
Unit
ns
TDCL
Data Clock Low
180
ns
TDCH
Data Clock High
100
ns
tTD
Transmit Data Delay
tOSS
Data Setup Time
40
ns
tOHS
Data Hold Time
40
ns
140
12-148
ns
intel .
8044AH/8344AH/8744H
WAVEFORMS
Memory Access
PROGRAM MEMORY READ CYCLE
~-------------------------------'TCY--------------------------~
ALE
PSEN
INSTRIN
PORTO
ADDRESS AIS-AB
PORT2
231663-8
DATA MEMORY READ CYCLE
~------~ ~----------TLLDV------------~
TWHLH
ALE
PSEN
RD
-----------------r------------~~~--------_+TRLRH----------~,-------
TRLDV
TRHDX
A7-AO
PORTO
DATA IN
TRLAZ
PORT 2
ADDRESS
OR SFR-P2
ADDRESS AIS-AB OR SFR-P2
231663-9
DATA MEMORY WRITE CYCLE
TWHlH
ALE
- - - -____________; -__________--{I4-----------TWLWH-----------.~-------
TOVWH
PORT 2
TWHQX
DATA OUT
PORTO
ADDRESS A15-A8 OR SFR-P2
231663-10
12-149
•
8044AH/8344AH/8744H
SERIAL 1/0 WAVEFORMS
SYNCHRONOUS DATA TRANSMISSION
~------------~y------------~
--------~ I - - - - T D C L - - - t
,.------"""1
SClK
' - -_ _ _ _- - ' - - J
I----TDCH----I ' - - - - - - -
DATA
TTD
231663-11
SYNCHRONOUS DATA RECEPTION
t------------TDCy-------+\
selK
- - - - - - - - , . t----TDCL -'-----I , - - - - - - - - - ,
I-------~H --~
DATA
TOSS
I------TDHS-----~
231663-12
12-150
int:et
8044AH/8344AH/8744H
=x
AC TESTING INPUT, OUTPUT, FLOAT WAVEFORMS
~F-LO-A-T----------------'
INPUT/OUTPUT
2.4
0.45
2.0
2.o}C.
TEST POINTS
''''0.""._ _ _ _ _......:0=.8
231663-13
AC testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0".
2.4
0.45
j
>-----FLOAT----t.j
2.0
2.0
2.4
:.....- - - - - - - - 0.....
0.45
231663-14
EXTERNAL CLOCK DRIVE XTAL2
TCHCL
1 + - - - - - - - TCLCL - - - - - - - . j
231663-15
Symbol
Parameter
TCLCL
Oscillator Period
TCHCX
High Time
TCLCX
Low Time
TCLCH
Rise Time
TCHCL
Fall Time
Variable Clock
Freq = 3.5 MHz to 12 MHz
Unit
Min
Max
83.3
20
20
285.7
ns
TCLCL-TCLCX
ns
TCLCL-TCHCX
ns
20
20
ns
12-151
ns
•
intel~
8044AH/8344AH/8744H
CLOCK WAVEFORMS
XTAL2
STATE.4 I STATE 5 1S,'ATE 6 I STATE 1 I STATE 2
I ~I~
~I~ ~I~
~I~ ~I~
IULfl-I"L.fU
ALE
---'
STATE 3
INTERNAL
CLOCK
Pl
I P2
STATE 4
Pl
P2
I
I'
STATE 5
Pl
P2
I
EXTERNAL PROGRAM MEMORY FETCH
PO
P2(EXT)
----II INDICATES ADDRESS TRANSIONS 1...__________...J
____
READ CYCLE
RD
DPLOR Ri
OUT
PO
P2
WRITE CYCLE
~¢
OOH IS EMITTED
DURING THIS PERIOD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
FLOATS=b"
n~
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
OUT(EVEN IF PROGRAM
'---------------1I PCL
MEMORY IS INTERNAL)
WR
DPL OR Ri
OUT
PO
P2
!.
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
.5 .:
tCL OUT
:I~OGRAM
I MEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT, SRC
MOV DEST, PO
OLD DATA
I NEW DATA
~~~==-______________----I---LPO PINS SAMPLED
!--4!.
~_~
MOV DEST. PORT (Pl. P2. P3)
(INCLUDES INTO, INn. TO. n)
PO PINS SAMPLED
~~-------------------hL
Pl. P2. P3 PINS SAMPLED
SERIAL PORT SHIFT CLOCK
Pl. P2, P3
PINS SAMPLED
~---.....;q:r
J~gDE O)------.....;~XD SAMPLED
RXD SAMPLED
231663-16
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the
pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as tempera·
ture and pin loading. Propagation also varies from output to output and component to component. Typically
though, (TA = 25°C, fully loaded) AD and WA propagation delays are approximately 50 ns. The other signals
are typically 85 ns. Propagation delays are incorporated in the AC specifications.
12·152
int:eL
8044AH/8344AH/8744H
ure B. Detailed timing specifications are provided in
the EPROM Programming and Verification Characteristics section of this data sheet.
8744H EPROM CHARACTERISTICS
Erasure Characteristics
Erasure of the B744H Program Memory begins to
occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have
wavelengths in this range, constant exposure to
these light sources over an extended period of time
(about 1 week in sunlight, or 3 years in room-level
fluorescent lighting) could cause unintentional erasure. If an application subjects the B744H to this
type of exposure, it is suggested that an opaque label be placed over the window.
Program Memory Security
Erasure leaves the array in an all 1s state.
The program memory security feature is developed
around a "security bit" in the B744H EPROM array.
Once this "hidden bit" is programmed, electrical access to the contents of the entire program memory
array becomes impossible. Activation of this feature
is accomplished by programming the B744H as described in "Programming the EPROM" with the ex- .
ception that P2.6 is held at a TTL high rather than a
TTL low. In addition, Port 1 and P2.0-P2.3 may be in
any state. Figure 9 illustrates the security bit programming configuration. Deactivating the security
feature, which again allows programmability of the
EPROM, is accomplished by exposing the EPROM
to ultraviolet light. This exposure, as described in
"Erasure Characteristics," erases the entire EPROM •
array. Therefore, attempted retrieval of "protected
code" results in its destruction.
Programming the EPROM
Program Verification
To be programmed, the B744H must be running with
a 4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate registers.) The address of an EPROM location
to be programmed is applied to Port 1 and pins P2.0P2.3 of Port 2, while the data byte is applied to Port
O. Pins P2.4-P2.6 and PSEN should be held low, and
P2.7 and RST high. (These are all TTL levels except
RST, which requires 2.5V for high.) EAIVPP is held
normally high, and is pulsed to + 21V. While EAI
VPP is at 21V, the ALE/PROG pin, which is normally
being held high, is pulsed low for 50 msec. Then
EAIVPP is returned to high. This is illustrated in Fig-
Program Memory may be read only when the "security feature" has not been activated. Refer to Figure
10 for Program Verification setup. To read the Program Memory, the following procedure can be used.
The unit must be running with a 4 to 6 MHz oscillator. The address of a Program Memory location to
be read is applied to Port 1 and pins P2.0-P2.3 of
Port 2. Pins P2.4-P2.6 and PSEN are held at TTL
low, while the ALE/PROG, RST, and EAIVPP pins
are held at TTL high. (These are all TTL levels except RST, which requires 2.5V for high.) Port 0 will
be the data output lines. P2.7 can be used as a read
strobe. While P2.7 is held high, the Port 0 pins float.
When P2.7 is strobed low, the contents of the addressed location will appear at Port o. External pullups (e.g., 10K) are required on Port 0 during program
verification.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-secl cm 2 rating for 20 to 30
minutes, at a distance of about 1 inch, should be
sufficient.
12-153
intel .
8044AH/8344AH/8744H
+5V
Vcc
ADDA. - - - . -.......~
Pl
OOOOH1744H
OFFFH
P2.0P2.3
PO
PGMDATA
P2.4
ALE _ _ ALE PROG
P2.5
P2.6
P2.7
EA
KTAl2
KTAll
--!AiVPP
AST
VIHl
PSErii
VSS
-
231663-17
Figure 8. Programming Configuration
+5V
VCC
NC Pl
1744H
P2.0NC P2.3
P2.4
P2.5
PO NC
ALE _ _ ALElPimGSO ml PULSE TO GND
P2.6
TTL HIGH
P2.7
KTAL2
KTAll
-
VSS
EA
--EAIVPP +21V PULSE
RST
VIHl
PSEN
231663-18
Figure 9. Security Bit Programming Configuration
12-154
intel@
8044AH/8344AH/8744H
+SV
Vee
ADDR. --.---"""""
OOOOHOFFFH
G744H
,..---..--1
r-----'\
PGM DATA
PO f - - - - - - , / (USE 10K PULLUPS)
P2.0P2.3
P2.4
P2.S
A:
P2.6
ENABLE --~ P2.7
EA
,..--r----Il(TAL2
RST
'---4-~f--j )(TAL 1
PSEN
--r-
TTL HIGH
...J
VIH1
~
VSS
231663-19
Figure 10. Program Verification Configuration
II
EPROM PROGRAMMiNG, SECURiTY BIT PROGRAMMING
AND VERiFICATION CHARACTIERISTICS
TA = 21°C to 2rc, Vee = 4.5V to 5.5V, vss = ov
Symbol
Vpp
Parameter
Min
Max
Units
Programming Supply Voltage
20.5
21.5
V
IPP
Programming Current
1/TCLCL
Oscillator Frequency
4
TAVGL
Address Setup to PROG
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
ENABLE High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG
TGHSL
Vpp Hold after PROG
10
TGLGH
PROGWidth
45
30
mA
6
MHz
10
/-Lsec
/-Lsec
55
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE to Data Valid
48TCLCL
TEHQZ
Data Float after ENABLE
0
12-155
48TCLCL
msec
intel .
8044AH/8344AH/8744H
EPROM PROGRAMMING, ,SECURITY BIT PROGRAMMING
AND VERIFICATION WAVEFORMS
PROGRAMMING
Pl,O·PU
P2,O·P2,3
VERIFICATION
ADDRESS
\
ADDRESS
-TAVOV
PORTO
DATA IN
---
--
TDVGL
TGHDX
TAVGL
TGHAX
\
ALEPROG
TSHGL
DATA OUT
I.-.i
TGLGH
~
21V ..SV
.~
T
\
TTL HIGH
TTL HIGH
TTL HIGH
EAVPP
,~J~~~~)-----TEHSH
_ TELOV
_
TEHOZ
231663-20
12-156
MCS®.-80/85 Data Sheets
13
II
r.~
intel 8-BIT N-CHANNEL
8080A/8080A-1/8080A-2
MICROPROCESSOR
®
•
•
TTL Drive Capability
2p.s (-1:1.3 p's, -2:1.5p.s) Instruction
Cycle
Powerful Problem Solving Instruction
• Set
General Purpose Registers and an
• 6Accumulator
16-Bit Program Counter for Directly
• Addressing
up to 64K Bytes of Memory
16-Bit Stack Pointer and Stack
• Manipulation
Instructions for Rapid
Decimal, Binary, and Double Precision
• Arithmetic
Ability to Provide Priority Vectored
• Interrupts
Directly Addressed 1/0 Ports
• 512
in EXPRESS
• -Available
Standard Temperature Range
in 40-Lead Cerdip and Plastic
• Available
Packages
(See Packaging Spec. Order "231369)
Switching of the Program Environment
The Intel® 8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip
using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control
and processing applications.
The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose
registers may be addressed individually or in pairs providing both single and double precision operators.
Arithmetic and logical instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic operation.
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out
stack to store/retrievE1 the contents of the accumulator, flags, program counter, and all of the 6 general
purpose registers. The 16-bit stack pointer controls the addressing of this external stack. This stack gives the
8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor
status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line
bidirectional data busses are used to facilitate easy interface to memory and I/O. Signals to control the
interface to memory and I/O are provided directly by the 8080A. Ultimate control of the address and data
busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the
address and data busses into a high impedance state. This permits OR-tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
NOTE:
The 8080A is functionally ~nd electrically compatible with the Intel 8080.
13-1
November 1986
Order Number: 231453-001
II
intel~
SOSOAISOSOA·1/S0S0A·2
II 81T I
INTERNAL DATA BUS
B
REG.
°
REG.
H
REG.
...
...
...
III
E
REG.
L
'"
III
REG.
ST ACO POINTER
PROGRAM COUNTER
REGISTER
ARRAV
nl'
''''
1111
..... -A"
ADDRESSBUS
Figure 1. Block Diagram
A,O
GND
40
39
38
37
D.
D.
D.
07
0,
D.
0, 0
36
8080A
Do
-5V
RESET
HOLD
INT
••
DBIN
WR
SYNC
+5V
15
16
17
18
19
A"
A,.
A13
Au
o
A15
35
At
34
A.
A7
33
32
31
30
29
28
27
28
25
24
23
22
21
....
....
....
A,
+12V
A.
A,
Ao
.,
WAIT
READY
HLDA
231453-2
Figure 2. Pin Configuration
13-2
231453-1
8080A/8080A-1/8080A-2
Table 1 Pin Description
Symbol
Type
A1s-Ao
0
DrDo
I/O
DATA BUS: The data bus provides bi-directional communication between the CPU,
memory, and I/O devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 8080A outputs a status word 01") the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNC
0
SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.
DBIN
0
DATA BUS IN: The DBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be used to enable the gating of data onto the 8080A data
bus from memory or I/O.
I
READY: The READY signal indicates to the 8080A that valid memory or input data is
available on the 8080A data bus. This signal is used to synchronize the CPU with slower
memory or I/O devices. If after sending an address out the 8080A does not receive a
READY input, the 8080A will enter a WAIT state for as long as the READY line is low.
READY can also be used to single step the CPU.
READY
Name and Function
ADDRESS BUS: The address bus provides the address to memory (up to 64K 8-bit
words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.
WAIT
WR
0
0
WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.
WRITE: The WR signal is used for memory WRITE or I/O output control. The data on
the data bus is stable while the WR Signal is active low (WR = 0).
HOLD
I
HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state
allows an external device to gain control of the 8080A address and data bus as soon as
the 8080A has completed its use of these busses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
the CPU is in the T2 or TW state and the READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A1S-Ao) and DATA BUS (Dr Do)
will be in their high impedance state. The CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.
e
0
HOLD ACKNOWLEDGE: The HLDA signal appears in response to the HOLD signal and
indicates that the data and address bus will go to the high impedance state. The HLDA
signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLDA signal appears after the rising edge of <1>2.
INTE
0
INT
I
INTERRUPT ENABLE: Indicates the content of the internal interrupt enable flip/flop.
This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET signal.
INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable flip/flop is reset it will not honor the request.
RESET1
I
HLDA
Vss
Voo
Vee
·Vss
<1>1, <1>2
RESET: While the RESET Signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The INTE and
HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared.
GROUND: Reference.
POWER: +12 ±5% V.
POWER: +5 ±5% V,
POWER: -5 ±5% V.
CLOCK PHASES: 2 externally supplied clock phases. (non TIL compatible)
NOTE:
1. The RESET signal must be active for a minimum of 3 clock cycles.
13-3
II
8080A/8080A-1/8080A-2
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Temperature Under Bias ............ O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
All Input or Output Voltages
with Respect to Vss ........... - 0.3V to + 20V
Vcc, Voo and Vss
with Respect to Vss ........... - 0.3V to + 20V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex. tended exposure beyond the "Operating Conditions"
may affect device reliability.
Power Dissipation .......................... 1.5W
D.C. CHARACTERISTICS
TA = O°C to 70°C, Voo = + 12V ± 5%, Vec
noted
= + 5V ± 5%, VSS = - 5V ± 5%, Vss = OV; unless otherwise
Symbol
Min
Parameter
Typ
Max
Unit
VILC
Clock Input Low Voltage
Vss - 1
Vss + 0.8
V
VIHC
Clock Input High Voltage
9.0
Voo + 1
V
VIL
Input Low Voltage
Vss - 1
Vss + 0.8
V
VIH
Input High Voltage
3.3
Vcc + 1
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
3.7
V
Test Condition
} IOL
IOH
V
= 1.9 mA on All Outputs,
= - 150 JlA
) 0,,,.,;,,
100 (AV) Avg. Power Supply Current (Voo)
40
70
mA
ICC (AV) Avg. Power Supply Current (Vce)
60
80
mA
Iss (AV) Avg. Power Supply Current (VBS)
0.01
1
mA
±10
/LA
Vss ,,; VIN ,,; Vec
IlL
Input Leakage
TCY = 0.48/LS
ICL
Clock Leakage
±10
/LA
Vss ,,; VCLOCK ,,; Voo
10L
Data Bus Leakage in Input Mode
-100
-2.0
/LA
mA
Vss ,,; VIN ,,; Vss + 0.8V
Vss + 0.8V ,,; VIN ,,; VCC
IFL
Address and Data Bus Leakage
During HOLD
+10
-100
/LA
V AOOR/OATA = VCC '
V AOOR/OATA = Vss + 0.45V
CAPACITANCE
1.5..----..,-----,-----,
TA = 25°C, VCC = VOO = Vss = OV, VBS = -5V
Symbol
Parameter
Typ
Max
Unit
Test Condition
C
Clock
Capacitance
17
25
pF
tc = 1 MHz
CIN
Input
Capacitance
6
10
pF
Unmeasured Pins
COUT
Output
Capacitance
10
20
pF
Returned to Vss
>~
~
::>
u
~
1.01------'''''''''......:=---+-----4
~
0.50'----.'::':-5---.-'50-----'.75
AMBIENT TEMPERATURE reI
231453-3
Typical Supply Current vs
Temperature, Normalized
ill Supply! ilT A = - O.450/0/"C
13-4
int'et
SOSOAISOSOA-1/S0SOA-2
A.C. CHARACTERISTICS (8080A) TA = O°C to 70°C, VOO = + 12V ± 5%, VCC
VSS
=
-5V ±5%, VSS
Symbol
=
=
± 5%,
-1 -1 -2 -2
Unit Test Condition
Min Max Min Max Min Max
Parameter
tCy(3)
Clock Period
t r, tf
Clock Rise and Fall Time
t1
<1>1 Pulse Width
60
50
60
ns
<1>2 Pulse Width
220
145
175
ns
ns
t2
+ 5V
OV; unless otherwise noted
0.48 2.0 0.32 2.0 0.38 2.0
0
50
0
25
0
t01
Delay <1> 1 to <1>2
0
0
0
t02
Delay <1>1 to <1>2
70
60
70
t03
Delay <1>1 to <1>2 Leading Edges
80
60
70
50
ILs
ns
ns
ns
tOA
Address Output Delay From <1>2
200
150
175
ns
too
Data Output Delay From <1>2
200
180
200
ns
toc
Signal Output Delay From <1>1 or <1>2
(SYNC, WR, WAIT, HLDA)
120
110
120
ns
tOF
tOI(1)
DBIN Delay From <1>2
140
ns
tOF
ns
tOS1
Data Setup Time During <1>1 and DBIN
30
10
20
ns
tOS2
tOH(1)
Data Setup Time to <1>2 During DBIN
150
120
130
ns
Data Hold Time From <1>2 and DBIN
(1 )
(1 )
(1 )
tiE
INTE Output Delay From <1>2
tRS
READY Setup Time During <1>2
120
90
90
ns
tHS
HOLD Setup Time During <1>2
140
120
120
ns
tiS
INT Setup Time During <1>2
120
100
100
ns
tH
Hold Time From <1>2 (READY, INT, HOLD)
0
0
0
ns
tFo
Delay to Float During Hold
(Address and Data Bus)
25
Delay for Input Bus to Enter Input Mode
140
25
tOF
130
25
tOF
200
120
120
120
ns
ns
tAW
Address Stable Prior to WR
(5)
(5)
(5)
ns
tow
Output Data Stable Prior to WR
(6)
(6)
(6)
ns
two
Output Data Stable From WR
(7)
(7)
(7)
ns
tWA
Address Stable From WR
(7)
(7)
(7)
ns
tHF
HLDA to Float Delay
(8)
(8)
(8)
ns
tWF
WR to Float Delay
(9)
(9)
(9)
ns
tAH
Address Hold Time After DBIN During HLDA -20
-20
-20
ns
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
'1
CL "100 PF
-=
CL = 100 pF
CL Includes Jig Capacitance
13-5
231453-4
=
100 pF
CL = 50 pF
ns
200
200
CL
CL
=
50 pF
•
~,
- Ff'~'
rf'-
'ev
f\
J
__ t~2-'
¢2
03_1
-I
.1-1
° -°
7
~
.I
0
-r
SYNC
- '0:1DBIN
~
(L)
WR
m
READY
_.
::l.
c[
@
3:
en
"-I
t02 . -
l-'oA~1 - - -too---I
o":II
J
-- I
A1S-Ao
l\
l\
-
\-
-J
:IE
J>
<
m
-
--
-
J.
-- .j..~~
...... ~
-1 -toHI--
~tOD-
~ATAIN
~
...J
tOI
-'h
-- --- -- -- --'AW
-
tO~I~-
,...-- -tow
- t052 -
-f
ATA OUT
- ---
-
-f
C»
o
C»
o
tocl-
l.
l>
.....
C»
l
1-'0,":1
......toF--1
o
C»
l
-----------
~
'oe ~I
....
.....
.ltH-~
------------
-
WAIT
~~ ---:1
r.-..
.I@
tR:
'H- toc-
tRS .....:.
C»
o
C»
o
toe
l>
l
{
..-
N
tH _ _ 1__
-.I@
HOLD
:x
J
- ~r-tHS ;""":"
HLDA
"~
'H-
INT
INTE
!'"'
231453-5
NOTE:
Timing measurements are made at the following reference voltages: CLOCK "1" =
"0" = o.av
a.ov,
"0" = 1.0V; INPUTS "1" = 3.3V, "0" =
o.av; OUTPUTS "1"
= 2.0V,
inlet.
8080Al8080A·1/8080A·2
Typical A Output Delay vs A Capacitance
WAVEFORMS (Continued)
~, ~F\
~2
A1S'Ao
°
7 ,00
f.-J
I-
--
Y
--1-t-/'wA
I-
- I--I--Y
~
+20
l\
!
>
-
2 + tcf>2 +tl2' + t02 + trl ~
4aO ns (-1 :320 ns, - 2:3aO ns).
13-7
3. The following are relevant· when interfacing the
aOaOA to devices having VIH = 3.3V:
a) Maximum output rise time from O.BV to 3.3V =
100 ns @ CL = SPEC.
b} Output delay when measured to 3.0V = SPEC
+60 ns @ CL = SPEC.
c} If CL = SPEC, add 0.6 ns/pF if CL > C5PEC,
subtract 0.3 ns/pF (from modified delay) if CL <
C5PEC· .
4. tAW =2 tCY - t03 - tr2 - 140 ns (-1:110
ns, - 2:130 ns).
5. tow = tCY - t03 - tr2 - 170 ns (-1:150 ns,
- 2:170 ns).
6. If not HLDA, two = tWA = t03 + tr2 + 10 ns.
If HLDA, two = tWA = tWF·
7. tHF = t03 + tr2 -50 ns.
a. tWF =. t03 + trcf>2 :- 10 ns.
9. Data In must be stable for this period during
DBIN T3. Both t051 and t052 must be satisfied.
10. Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
11. Hold signal must be stable for this period during
T2 or T W when entering hold mode, and during T3,
T4, T 5 and TWH when in hold mode. (External synchronization is not required.)
12. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order
to be recognized on the following instruction. (External synchronization is not required.)
13. This timing diagram shows timing relationships
only; it does not represent any specific machine cycle.
8080A/8080A-1/8080A-2
INSTRUCTION SET
The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate addressing modes. .
Move, load, and store instruction groups provide the
ability to move either 8 or 16 bits of data between
memory, the six working registers and the accumulator using direct, indirect, and immediate addressing
modes.
The ability to branch to different portions of the program is provided with jump, jump conditional, and
computed jumps. Also the ability to call to and return
from subroutines is provided both conditionally and
unconditionally. The RESTART (or single byte call
instruction) is useful for interrupt vector operation.
Double precision operators such as stack manipulation and double add instructions extend both the
arithmetic and interrupt handling capability of the
8080A. The ability to increment and decrement
memory, the six general registers and the accumulator is provided as well as extended increment and
decrement instructions to operate on the register
pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator left or right
through or around the carry bit.
Input and output may be accomplished using memory addresses as I/O ports or the directly addressed
I/O provided for in the 8080A instruction set.
The following special instruction group completes
the 8080A instruction set: the NOP instruction,
HALT to stop processor execution and the DAA instructions provide decimal arithmetic capability. STC
allows the carry flag to be directly set, and the CMC
instruction allows it to be complemented. CMA complements the contents of the accumulator and
XCHG exchanges the contents of two 16-bit register
pairs directly.
Data and Instruction Formats
Data in the 8080A is stored in the form of 8-bit binary integers. All data transfers to they system data bus will
be in the same format.
I D7 D6 D5 D4 D3 D2 D1 Dol
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in
successive words in program memory. The instruction formats then depend on the particular operation executed.
One Byte Instructions
TYPICAL INSTRUCTIONS
ID7 D6 D5 D4 D3 D2 D1 Dol
OP CODE
Register to register, memory reference,
arithmetic or logical, rotate, return, push,
pop, enable or disable Interrupt
instructions
Two Byte Instructions
ID7 D6 D5 D4 D3 D2 D1 Dol
OP CODE
ID7 D6 D5 D4 D3 D2 D1 Dol
OPERAND
Immediate mode or I/O instructions
Three Byte Instructions
Jump, call or direct load and store
instructions
ID7 D6 D5 D4 D3 D2 D1 Dol
OPCODE
ID7 D6 D5 D4 D3 D2 D1 Dol
LOW ADDRESS OR OPERAND 1
I D7 D6 D5 D4 D3 D2 D1 Dol
HIGH ADDRESS OR OPERAND 2
For the 8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level.
13-8
intel.
8080A/8080A-1/8080A-2
Table 2. Instruction Set Summary
Instruction Code (1)
~nemonlc'
D7DsD5D4D3D2Dl D
Operations
Description
Clock
Cyclel
(2)
Mnemonic'
MOVE, LOAD, AND STORE
MOVr1,r2
o
MOVM,r
0
MOVr,M
0
MVlr
0
MVIM
0
LXIB
0
LXI 0
0
LXIH
0
STAXB
STAXD
LDAXB
LDAXD
STA
LOA
SHLD
LHLD
XCHG
0
0
0
0
0
0
0
0
1
1 D DDS S S Move register to
register
1 1 1 o S S S Move register to
memory
1 DOD 1 1 o Move memory to
register
0 D D D 1 1 o Move immediate
register
0 1 1 0 1 1 o Move immediate
memory
0 0 0 0 0 0 1 Load immediate
register Pair B & C
0 0 1 0 0 0 1 Load immediate
register Pair 0 & E
0 1 0 0 0 0 1 Load immediate
register Pair H & L
0 0 0 0 0 1 o Store A indirect
0 0 1 0 0 1 o Store A indirect
0 0 0 1 0 1 o Load A indirect
0 0 1 1 0 1 o Load A indirect
0 1 1 0 0 1 o Store A direct
0 1 1 1 0 1 o Load A direct
0 1 0 0 0 1 o Store H & L direct
0 1 0 1 0 1 o Load H & L direct
1 1 0 r 0 1 1 Exchange 0 & E,
H & L Registers
JM
JPE
5
JPO
PCHL
7
7
Instruction Code (1)
D7DsDsD4D3D2Dl D(
I
I
1 I
1 I
I 1 0 1 o Jump on minus
0 1 0 I o Jump on parity
even
1 I I 0 0 0 1 o Jump on parity odd
I 1 1 0 1 0 0 I H & L to program
counter
PUSHD
PUSHH
PUSH
PSW
POPB
POP 0
POPH
POPPSW
XTHL
SPHL
LXISP
INXSP
DCXSP
1 1 0 0 0 1 0 1 Push register Pair
B &Con stack
1 1 0 1 0 1 0 1 Push register Pair
0& Eon stack
1 1 1 0 0 1 0 1 Push register Pair
H & Lon stack
1 1 1 1 0 1 0 1 Push A and Flags
on stack
1 1 0 0 0 0 0 1 Pop register Pair B
&Coifstack
1 1 0 1 0 0 0 1 Pop register Pair 0
& E off stack
1 1 1 0 0 0 0 1 Pop register Pair H
& Loff stack
1 1 1 1 0 0 0 1 Pop A and Flags
off stack
1 1 1 0 0 0 1 1 Exchange top of
stack, H & L
1 1 1 1 1 0 0 1 H& Ltostack
pointer
0 0 1 1 0 0 0 1 Load immediate
stack pOinter
0 0 1 1 0 0 1 1 Increment stack
pointer
0 0 1 1 1 0 1 1 Decrement stack
pointer
CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
10
10
10
10
7
7
7
7
13
13
16
16
JC
JNC
JZ
JNZ
JP
1 1 0 0 0 0 1 1 Jump
unconditional
1 1 0 1 1 0 1 o Jump on carry
1 1 0 1 0 0 1 o Jump on no carry
1 1 0 0 1 0 1 o Jump on zero
1 1 0 0 0 0 1 o Jump on no zero
1 I I I 0 0 I o Jump on positive
10
10
10
5
1 I 0 0 I
1 0 1 Call unconditional
o Call on carry
o Call on no carry
1 0 0 I I 0 o Call on zero
I 0 0 0 I 0 o Call on no zero
1 1 1 0 1 0 o Call on positive
1 1 1 I 1 0 o Call on minus
I 1 0 I I 0 o Call on parity even
1 1 0 0 I 0 o Call on parity odd
17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
1 0 0 I 0 0 I Return
I 0 1 I 0 0 o Return on carry
I 0 1 0 0 0 o Return on no carry
10
5111
5/11
5/11
5/11
5/11
5/11
5111
1 I 0 1 1 1 0
1 I 0 1 0 1 0
1
1
1
1
I
I
RETURN
4
11
RET
RC
RNC
RZ
RNZ
RP
RM
RPE
1
I
I
1
1
1
1
1
RPO
1 1 1 0 0 0 0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0 0
o Return on zero
o Return on no zero
o Return on positive
o Return on minus
o Return on parity
even
o Return on parity
5/11
odd
RESTART
11
RST
11
1 1 A A A 1 1 1 Restart
11
INCREMENT AND DECREMENT
INRr
DCRr
INRM
DCRM
INXB
o
o
INXD
0 0 0 1 0
INXH
0 0 1 0 0
5
DCXB
DCXD
DCXH
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
10
ADD
5
ADDr
ADCr
11
10
10
10
10
18
5
ADDM
ADCM
JUMP
JMP
Clock
Cyclel
(2)
CALL
7
STACKOPS
PUSHB
Operations
Description
10
ADI
ACI
10
10
10
10
10
DADB
DADO
DADH
DADSP
13-9
ODD
ODD
0 0 1 1
0 0 1 1
0 0 0- 0
0
0
0
0
0
o Increment register
1 0 1 Decrement register
1 0 o Increment memory
1 0 1 Decrement memol1
0 1 1 Increment B & C
registers
0 1 1 Increment D & E
registers
0 1 1 Increment H & L
registers
0 1 1 Decrement B & C
0 1 1 Decrement 0 & E
0 1 1 Decrement H & L
1 0
1 0 0 0 0 S S S Add register to A
1 0 0 0 1 S S S Add register to A
with carry
1 0 0 0 0 1 1 o Add memory to A
1 0 0 0 1 1 1 o Add memory to A
with carry
1 1 0 0 0 1 1 o Add immediate to A
1 1 0 0 1 1 1 o Add immediate to A
with carry
0 0 0 0 1 0 0 1 AddB&CtoH&L
0 0 0 1 1 0 0 1 AddD&EtoH&L
0 0 1 0 1 0 0 1 AddH&LtoH&L
0 0 1 1 1 0 0 1 Add stack pointer
toH&L
5
5
10
10
5
5
5
5
5
5
4
4
7
7
7
7
10
10
10
10
•
int'et~
8080A/8080A-1/8080A-2
Table 2. Instruction Set Summary (Continued)
Instruction Code (1)
Mnemonic'
07 De 05 D4 Ds D2 01 D
Operations
Description
Clock
Cyclel
(2)
SUBTRACT
SUBr
Instruction Code (1)
D?De Ds D4Ds D2D1D
Operations
Description
Clock
Cycle.
(2)
ROTATE
1 0 0 1 0 S S S Subtract register
SBBr
1 0 0 1, 1 S S S
SUBM
1 0 0 1 0 1 1 o
SBBM
1 0 0 1 1 1 1 o
SUI
1 1 0 1 0 1 1 o
SBI
1 1 0 1 1 1 1 o
from A
Subtract register
from A with borrow
Subtract memory
from A
Subtract memory
from A with borrow
Subtract
Immediate from A
Subtract
immediate from A
with borrow
4
RLC
RRC
RAL
0 0 0 0 0 1 1 1 Rotate A left
0 0 0 0 1 1 1 1 Rotate A right
0 0 0 1 0 1 1 1 Rotate A left
7
RAR
0 0 0 1 1 1 1 1 Rotate A right
4
4
4'
4
through carry
4
through carry
7
7
7
SPECIALS
CMA
STC
CMC
DAA
0 0 1 0
0 0 1 1
0 '0 1 1
o 0 1 0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Complement A
Set carry
Complement carry
Decimal adjust A
4
4
4
4
INPUT/OUTPUT
LOGICAL
ANAr
~nemonlc'
1 0 1 0 0 S S S And register
XRAr
1 0 1 0 1 S S S
ORAr
CMPr
1 0 1 1 0 S S S
1 0 1 1 1 S 5 S
ANAM
1 0 1 0-0 1 1 o
XRAM
1 0 1 0 1 1 1 o
ORAM
CMPM
1 0 1 1 0 1 1 o
1 0 1 1 1 1 1 o
ANI
1 1 1 0 0 1 1 o
XRI
1 1 1 0 1 1 1 o
ORI
1 1 1 1 0 1 1 o
CPI
1 1 1 1 1 1 1 o
with A
Exclusive or
register with A
Or register with A
Compare register
with A
And memory
with A
Exclusive Or
memory with A
Or memory with A
Compare memory
with A
And immediate
with A
Exclusive Or
immediate with A
Or immediate
with A
Compare
immediate with A
4
IN
OUT
4
CONTROL
4
4
EI
01
NOP
HLT
7
1 1 0 1 1 0 1 1 Input
1 1 0 1 0 0 1 1 Output
10
10
0
0
0
1
4
4
4
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
0
0
0
1
1
0
1
1 Enable Interrupts
1 Disable Interrupt
o No-operation
o Halt
7
7
7
7
7
7
7
NOTES:
1. DOD or SSS: B = 000, C = 001,0 = 010, E = 011, H = 100, L = 101, Memory = 110, A
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
·AII mnemonics copyright IS) Intel Corporation 1977
'
13-10
= 111.
7
SOS5AH/SOS5AH-2/S0S5AH-1
S-BIT HMOS MICROPROCESSORS
System Controller; Advanced
• On-Chip
Cycle Status Information Available for
+ SV Power Supply with 10%
• Single
Voltage Margins
MHz, S MHz and 6 MHz Selections
• 3Available
20% Lower Power Consumption than
• SOSSA
for 3 MHz and S MHz
1.3 J.Ls Instruction Cycle (SOSSAH); O.S
• J.Ls (SOSSAH-2); 0.67 J.Ls (SOSSAH-1)
100% Software Compatible with SOSOA
• On-Chip
Generator (with External
• Crystal, LCClock
or RC Network)
Large System Control
•
Four Vectored Interrupt Inputs (One Is
Non-Maskable) Plus an SOSOACompatible Interrupt
In/Serial Out Port
• Serial
Decimal, Binary and Double Precision
• Arithmetic
Addressing Capability to 64K
• Direct
Bytes of Memory
in 40-Lead Cerdip and Plastic
• Available
Packages
(See Packaging Spec., Order #231369)
The Intel 8085AH is a complete 8-bit parallel Central Processing Unit (CPU) implemented in N-channel,
depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the
8080A microprocessor, and it is designed to improve the present 8080A's performance by higher system
speed. Its high level of system integration allows a minimum system of three IC's [8085AH (CPU), 8156H
(RAM/IO) and 8755A (EPROM/IO)] while maintaining total system expandability. The 8085AH-2 and
8085AH-1 are faster versions of the 8085AH.
The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller)
provided for the 8080A, thereby offering a higher level of system integration.
The 8085AH uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit
data bus. The on-chip address latches of 8155H/8156H/8755A memory products allow a direct interface with
the 8085AH.
x,
X2
RESET OUT
SOD
SID
TRAP
RST7.5
B
<.,
C
REG
o
I"
H
11\
Ell'
REG
REG
REG
'I>
REG
l
IIUI
'"
STACKI'OINTER
1111
",OCR"'. COUNTER
nil
IHCREM1NTlllIDECREIIIIENTlR
ACORE.LATCH
1111
RST 6.5
RST 55
INTR
l-'
INTA
ADO
AD,
AD2
AD3
AD4
AD5
AD6
AD7
ARRAY
VSS
.....
~1.euI
..
""'~
ADDREUlDATAIUI
231718-1
Figure 1. 8085AH CPU Functional Block Diagram
13-11
Vee
HOLD
HLOA
elK lOUT!
RESET IN
READY
101M
S,
AD
WR
ALE
So
A15
A'4
A13
A'2
All
AlO
A9
AS
231718-2
Figure 2. 8085AH Pin
Configuration
September 1987
Order Number: 231718·001
SOS5AH/SOS5AH-2/S0S5AH-1
Table 1_ Pin Description
Symbol
Ae-A15
Type
Name and Function
0
ADDRESS BUS: The most significant 8 bits of memory address or the 8 bits of the
110 address, 3-stated during Hold and Halt modes and during RESET.
I/O
MULTIPLEXED ADDRESS/DATA BUS: Lower 8 bits of the memory address (or
I/O address) appear on the bus during the first clock cycle (T state) of a machine
cycle. It then becomes the data bus during the second and third clock cycles.
ALE
0
ADDRESS LATCH ENABLE: It occurs during the first clock state of a machine
cycle and enables the address to get latched into the on-chip latch of peripherals.
The falling edge of ALE is set to guarantee setup and hold times for the address
information. The falling edge of ALE can also be used to strobe the stat~s
information. ALE is never 3-stated.
So, S1 .and 10/M
0
MACHINE CYCLE STATUS:
ADo-7
-
IO/M S1 So
0
0 1
1 0
0
1
0 1
1
1 0
0
1 1
1
1 1
Status
Memory write
Memory read
I/O write
I/O read
Opcode fetch
Interrupt Acknowledge
• 0 0 Halt
• X X Hold
• X X Reset
• = 3-state (high impedance)
X = unspecified
S1 can be used as an advanced R/W status. 10/M, SO and S1 become valid at the
beginning of a machine cycle and remain stable throughout the cycle. The falling
edge of ALE may be used to latch the state of these lines.
RD
0
READ CONTROL: A low level on RD indicates the selected memory or I/O device
is to be read and that the Data Bus is available for the data transfer, 3-stated during
Hold and Halt modes and during RESET.
WR
0
WROTE CONTROL: A low level on WR indicates the data on the Data Bus is to be
written into the selected memory or I/O location. Data is set up at the trailing edge
of WR. 3-stated during Hold and Halt modes and during RESET.
READY
I
READY: If READY is high during a read or write cycle, it indicates that the memory
or peripheral is ready to send or receive data. If READY is low, the CPU will wait an
integral number of clock cycles for READY to go high before completing the read
or write cycle. READY must conform to specified setup and hold times.
HOLD
I
HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the bus
as soon as the completion of the current bus transfer. Internal processing can
continue. The processor can regain the bus only after the HOLD ~ removed. When
the HOLD is acknowledged, the Address, Data RD, WR, and 10/M lines are
3-stated.
HLDA
0
HOLD ACKNOWLEDGE: Indicates that the CPU has received the HOLD request
and that it will relinquish the bus in the next clock cycle. HILDA goes low after the
Hold request is removed. The CPU takes the bus one half clock cycle after HLDA
goes low.
INTR
I
INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled only
during the next to the last clock cycle of an instruction and during Hold and Halt
states. If it is active, the Program Counter (PC) will be inhibited from incrementing
and an INTA will be issued. During this cycle a RESTART or CALL instruction can
be inserted to jump to the interrupt service routine. The INTR is enabled and
disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.
13-12
iniaL
8085AH/8085AH-2/8085AH-1
Table 1. Pin Description (Continued)
Symbol
Type
Name and Function
INTA
0
INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as)
RD during the Instruction cycle after an INTR is accepted. It can be used to
activate an 8259A Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5
RST7.5
I
RESTART INTERRUPTS: These three inputs have the same timing as INTR
except they cause an internal REST ART to be automatically inserted.
TRAP
I
TRAP: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the
same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt
Enable. It has the highest priority of any interrupt. (See Table 2.)
RESET IN
I
RESET IN: Sets the Program Counter to zero and resets the Interrupt Enable and
HlDA flip-flops. The data and address buses and the control lines are 3-stated
during RESET and because of the asynchronous nature of RESET, the processor's
internal registers and flags may be altered by RESET with unpredictable results.
RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for
power-on RESET delay (see Figure 3). Upon power-up, RESET IN must remain low
for at least 10 ms after minimum Vee has been reached. For proper reset
operation after the power-up duration, RESET IN should be kept Iowa minimum of
three clock periods. The CPU is held in the reset condition as long as RESET IN is
applied.
RESET OUT
0
RESET OUT: Reset Out indicates CPU is being reset. Can be used as a system
reset. The signal is synchronized to the processor clock and lasts an integral
number of clock periods.
Xl, X2
I
Xl and X2: Are connected to a crystal, lC, or RC network to drive the internal
clock generator. Xl can also be an external clock input from a logic gate. The input
frequency is divided by 2 to give the processor's internal operating frequency.
ClK
0
CLOCK: Clock output for use as a system clock. The period of ClK is twice the Xl,
X2 input period.
SID
I
SERIAL INPUT DATA LINE: The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.
SOD
0
SERIAL OUTPUT DATA LINE: The output SOD is set or reset as specified by the
SIM instruction.
The priority of these interrupt is ordered as shown in Table 2. These interrupts have
a higher priority than INTR. In addition, they may be individually masked out using
the SIM instruction.
Vee
VSS
POWER:
+ 5 volt supply.
GROUND: Reference.
Table 2. Interrupt Priority, Restart Address and Sensitivity
Priority
Address Branched to(1)
When Interrupt Occurs
Type Trigger
TRAP
1
24H
Rising Edge AND High level until Sampled
RST7.5
2
3CH
Rising Edge (latched)
RST6.5
3
34H
High level until Sampled
RST 5.5
4
2CH
High level until Sampled
INTR
5
(Note 2)
High level until Sampled
Name
NOTES:
1. The processor pushes the PC on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged.
13-13
•
intel.,
8085AH/8085AH-2/8085AH-1
(SID) and Serial Output Data (SOD) lines for simple
serial interface.
RESET IN
:
C,
R,
VecO
1
J
Typical Power-On Reset RC Values'
R,
C,
In addition to these features, the 8085AH has three
maskable, vector interrupt pins, one nonmaskable
TRAP interrupt, and a bus vectored interrupt, INTR.
I~
INTERRUPT AND SERIAL 1/0
231718-3
The 8085AH has 5 interrupt inputs: INTR, RST 5.5,
RST 6.5, RST 7.5, and TRAP. INTR .is identical in
function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is
nonmaskable.
75 K!1
1 "F
'Values May Have 10 Vary Due 10 Applied Power Supply Ramp
Up Time.
~
~
Figure 3. Power-On Reset Circuit
FUNCTIONAL DESCRIPTION
The 8085AH is a complete 8-bit parallel central
processor. It is designed with N-channel, depletion
load, silicon gate technology (HMOS), and requires
a single + 5V supply. Its basic clock speed is 3 MHz
(8085AH), 5 MHz (8085AH-2), or 6 MHz (8085-AH-1),
thus improving on the present 8080A's performance
with higher system speed. Also it is designed to fit
into a minimum system of three IC's: The CPU
(8085AH), a RAM/IO (8156H), and an EPROM/IO
chip (8755A).
The 8085AH has twelve addressable 8-bit .registers.
Four' of them can function only as two 16-bit register
pairs. Six others can be used interchangeably as
8-bit registers or as 16-bit register pairs. The
8085AH register set is as follows:
Mnemonic
Register
Contents
ACC or A
Accumulator
8 Bits
PC
Program Counter 16-Bit Address
BC, DE, HL General-Purpose 8-Bits x 6 or
Registers; data
16 Bits x 3
pointer (H L)
SP
Stack Pointer
16-Bit Address
Flags or F Flag Register
5 Flags (8-Bit Space)
The 8085AH uses a multiplexed Data Bus. The ad"
dress is split between the higher 8-bit Address Bus
and the lower 8-bit Address/Data Bus. During the
first T state (clock cycle) of a machine cycle the low
order address is sent out on the Address/Data bus.
These lower 8 bits may be latched externally by the
Address Latch Enable signal (ALE). During the rest
of the machine cycle the data bus is used for memory or I/O data.
The 8085AH provides RD, WR, So, S" and 10/M
signals for bus control. An Interrupt Acknowledge
signal (INTA) is also provided. HOLD and all Interrupts are synchronized with the processor's internal
clock. The 8085AH also provides Serial Input Data
The three maskable interrupt cause the internal execution of RESTART (saving the program counter in
the stack and branching to the RESTART address) if
the interrupts are enabled and if thei interrupt mask
is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of
the state of the interrupt enable or masks. (See Table 2.)
There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high level-sensitive like INTR (and INT on the 8080) and are recognized with the same timing as INTR. RST 7.5 is rising
edge-sensitive.
Fo~ RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request (a normally high level signal with a low going
pulse is recommended for highest system noise immunity). The RST 7.5 request flip-flop remains set
until the request is serviced. Then it is reset automatically. This flip-flop may also be reset by using
the SIM instruction or by issuing a RESET IN to the
8085AH. The RST 7.5 internal flip-flop will be set by
a pulse on the RST 7.5 pin even when the RST 7.5
interrupt is masked out.
.
The status of the three RST interrupt masks can
only be. affected by the SIM instruction and
RESET IN. (See SIM, Chapter 5 of the 8080/8085
User's Manual.)
The interrupts. are arranged in a fixed priority that
determines which interrupt is to be recognized if
more than one is pending as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR...,-Iowest priority. This priority scheme does not take into
account the priority of a routine that was started by a
higher priority interrupt. RST 5.5 can interrupt an
RST 7.5 routine if the interrupts are re-enabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic events
such as power failure or bus error. The TRAP input is
recognized just as any other interrupt but has the
13-14
intet
8085AH/8085AH·2/8085AH·1
highest priority. It is not affected by any flag or mask.
The TRAP input is both edge and level sensitive.
The TRAP input must go high and remain high until it
is acknowledged. It will not be recognized again until
it goes low, then high again. This avoids any false
triggering due to noise or logic glitches. Figure 4 illustrates the TRAP interrupt request circuitry within
the 8085AH. Note that the servicing of any interrupt
(TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables
all future interrupts (except TRAPs) until an EI instruction is executed.
INSIDE THE
EXTERNAL
Note the use of the 20 pF capacitor between X2 and
ground. This capacitor is required with crystal frequencies below 4 MHz to assure oscillator startup at
the correct frequency. A parallel-resonant LC citcuit
may be used as the frequency-determining network
for the 80B5AH, providing that its frequency tolerance of approximately ± 10% is acceptable. The
components are chosen from the formula:
INTERRUPT
fillEifN
Parallel resonance at twice the clock frequency desired
CL (load capacitance) s 30 pF
Cs (Shunt capacitance) s 7 pF
Rs (equivalent shunt resistance) s 75!l
Drive level: 10 mW
Frequency tolerance: ± 0.005% (suggested)
8085AH
TRAP
REOUEST
hence, the 8085AH is operated with a 6 MHz crystal
(for 3 MHz clock), the 8085AH-2 operated with a 10
MHz crystal (for 5 MHz clock), and the 8085AH-1
can be operated with a 12 MHz crystal (for 6 MHz
clock). If a crystal is used, it must have the following
characteristics:
TRAP
SCHMITT
TRIGGER
t-5V
0
eLK
o
f =
FIF
INTERNAL
TRAP
1
21T~L(Cext
+ Cint)
To minimize variations in frequency, it is recommended that you choose a value for Cext that is at
least twice that of Cinlo or 30 pF. The use of an LC
circuit is not recommended for frequencies higher
than approximately 5 MHz.
TRAP F.F.
ACKNOWLEDGE
231718-4
Figure 4. TRAP and RESET In Circuit
The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable
status. Performing the first RIM instruction following
a TRAP interrupt allows you to determine whether
interrupts were enabled or disabled prior to the
TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR, or RST 5.5-7.5 will provide
current Interrupt Enable status, revealing that interrupts are disabled. See the description of the RIM
instruction in the 8080/8085 Family User's Manual.
The serial I/O system is also controlled by the RIM
and SIM instruction. SID is read by RIM, and SIM
sets the SOD data.
DRIVING THE X1 AND X2 INPUTS
You may drive the clock inputs of the 8085AH,
8085AH-2, or 8085AH-1 with a crystal, an LC tuned
circuit, an RC network, or an external clock source.
The crystal frequency must be at least 1 MHz, and
must be twice the desired internal clock frequency;
An RC circuit may be used as the frequency-determining network for the 8085AH if maintaining a precise clock frequency is of no importance. Variations
in the on-chip timing generation can cause a wide
variation in frequency when using the RC mode. Its
advantage is its low component cost. The driving
frequency generated by the circuit shown is approximately 3 MHz. It is not recommended that frequencies greatly higher or lower than this be attempted.
Figure 5 shows the recommended clock driver circuits. Note in d and e that pullup resistors are required to assure that the high level voltage of the
input is at least 4V and maximum low level voltage
of 0.8V.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to X1 and leave X2
open-circuited (Figure 5d). If the driving frequency is
from 6 MHz to 12 MHz, stability of the clock generator will be improved by driving both X1 and X2 with a
push-pull source (Figure 5e). To prevent self-oscillation of the 8085AH, be sure that X2 is not coupled
back to X1 through the driving circuit.
13-15
•
i
intet
SOS5AH/SOS5AH-2/S0S5AH-1
+$V
X,
IGISAH
----,
4700
TO
lKO
I
I
I CrNT
*-15pF
I
L...;:....-~----l
I
2 X
'20 pF capacitors required for
crystal frequency,;; 4 MHz only.
2_ _ _ ...J
L -_ _ _ _ _ __
231718-5
a. Quartz Crystal Clock Driver
x_
*
'X2 left floating
x,
----1
231718-8
d. 1-6 MHz Input Frequency
Clock Driver Circuit
I
I CrNT
..i.. -15pF
CEXT
T
2
+$V
I
X2_ _ _ ...1
231718-6
b. LC Tuned Circuit Clock Driver
r-
'1
t··
-
x,
4700
'-----1 x.
-81(
231718-9
~ x_
e. 1-12 MHz Input Frequency
External Clock Driver Circuit
L-
231718-7
c. RC Circuit Clock Driver
Figure 5. Clock Driver Circuits
GENERATING AN 8085AH WAIT
STATE
If .your system requirements are such that slow
memories or peripheral devices are being used, .the
circuit shown in Figure 6 may be used to insert one
WAIT state in each 8085AH machine cycle.
As in the 8080, the READY line is used to extend the
read and write pulse lengths so that the 8085AH can
be used with slow memory. HOLD causes the CPU
to relinquish the bus when· it is through with it by
floating the Address and Data Buses.
SYSTEM INTERFACE
The D flip-flops should be chosen so· that
• CLK is rising edge-triggered
• CLEAR is low-level active.
-
~
AlEO ____
CLEAR
CLK
"0"
F/F
+5V- 0
cue OUTPI/T"
0
~
-
The 8085AH family includes memory components,
which are directly compatible to the 8085AH CPU.
For example, a system conSisting of the three chips,
8085AH, 8156H and 8755A will have the following
features:
• 2K Bytes EPROM
TO
CLK
"0"
F/F
0
• 256 Bytes RAM
• 1 Timer/Counter
READY
-
IN PUT
~I-
• 4 8-bit I/O Ports
.
231718-10
'ALE and ClK (OUT) should be buffered if ClK input of latch
exceeds 8085AH IOl or IOH.
• 1 6-bit I/O Port
• 4 Interrupt Levels
• Serial In/Serial Out Ports
Figure 6. Generation of a
Walt State for 8085AH CPU
13-16
inlet
SOS5AH/SOS5AH-2/S0S5AH-1
This minimum system, using the standard 1/0 technique is as shown in Figure 7.
shows the system configuration of Memory Mapped
1/0 using 8085AH.
In addition to the standard 1/0, the memory mapped
The 8085AH CPU can also interface with the standard memory that does not have the multiplexed addressldata bus. It will require a simple 8-bit latch as
shown in Figure 9.
1/0 offers an efficient 1/0 addressing technique.
With this technique, an area of memory address
space is assigned for 1/0 address, thereby, using
the memory address for 1/0 manipulation. Figure 8
--
r1D~x,
x,
TRAP
---=
Vss vee
rI I
RST6,5
8085AH
RST5.5
INTA
ADDA
RESET IN
HOLD
I-
rrSID I 5, r-So r--
HLDA
RST7.5
SOD
RESET
ADDR/
OUT
DATA ALE AD WR 101M
ROY eLK
T
(8) :.
(8)
~
~-
Vr
PORr~
WR
_
PORT
RD 8156H B
ALE
PORT
C
'\ DATAl
ADDR
"
IN
101M
RESET
TIMER
OUT
~
(8)
•
~
(6)
----
lOW
AD
ALE
I t-r--
.CE
'---
"-
r-
v'
"-
PORT
A
~
As. 10
8755A
DATAl
ADDR
...
101M
RESET
--*
ROY
~
ClK
~-
PORT
B
~
Vee
lOR
..J
.t t J 1.
Vss Vee Voo PROG
Vee
Vee
Vee
231718-11
'NOTE:
Optional Connection
Figure 7. 8085AH Minimum System (Standard 1/0 Technique)
13-17
_.
l
8
A
)
~
--....
AS-15
'
(ADO-7
~'\.
"ALE
"11
0'
c....
WR
CD
0
RESET OUl I
Q)
U1
READY
3:
S'
c
3
RESET
en
-
(,) '<
CD
i
VCC
vcc
II
i
TIMER
IN
+
WR
AD
ALE
AD
CE " ' / 0 7
ASAD
VA10V07
101M
QI)
0
-
I
I.
3'
-
-
ClK
Q)
/';:,
-
101M
!»
......
......
-
RD
8085AH
101
CE M
I
I.
I
ALE
vcc
QI)
(11
):0
I
......
QI)
AD 1i5i\ ClK RST!RDY
0
QI)
(11
.
):0
In
CD
I
3
I\)
......
~
QI)
CD
0
T6~~R _
3
0
-<
QI)
(11
-
.
):0
8156H
[RAM + I/O + COUNTERfTIMERl
3:
DI
'C
'C
CD
C.
::::
'"
'"
/
I
....
8755A [EPROM + I/O]
/,
.9
231718-12
'NOTE:
Optional Connection
inteL
8085AH/8085AH-2/8085AH-1
----
TRAP
X,
X2 ,
RESET IN
HOLD
HLDA
RST7
RST6
SOD
8085AH
RST5
INTR
INTA
ADDR
SID
S,
RESET
So
OUT
ADDR/
ROY CLK
DATA ALE R5 WR 10/M
-----
I--
f-
' 'Icl','~.
10/M (CSI
WR
RD
A
DATA
...
1\
\
STANDARD
MEMORY
ADDR (CSI
(
\
•
(161
~
CLK
RESET
10/M (CSI
I/O POR TS,
LS
WR
AD
V
DATA
~
"
"-
I
STANDARD
I/O
K5
ADDR
'~UI
II
V
./'A
Vee
Y
AA
Vee
Vy
Vee
231718-13
Figure 9. 8085 System (Using Standard Memories)
13-19
intel .
8085AH/8085AH~2/8085AH·1
the three control signals (RD, WR, and INTA). (See
Table 3.) The status lines can be used as advanced.
controls (for device selection, for example), since
they become active at the T 1 state, at the outset of
each machine cycle. Control lines RD and WR become active later, at the time when the transfer of
data is to take place, so are 'used as command lines.
BASIC SYSTEM TIMING
The 8085AH has a multiplexed Data Bus. ALE is
used as a strobe to sample the lower 8-bits of address on. the Data Bus. Figure 10 shows an instruction fetch, memory read and 110 write cycle (as
would occur during processing of the OUT instruc.tion). Note that during the 1/0 write and read cycle
that the 1/0 port address is copied on both the upper and lower half of the address.
A machine cycle normally consists of three T states,
with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or
HOLD states are forced by the receipt of READY or
HOLD inputs). Any T state must be one of ten possible states, shown in Table 4.
There are seven possible types of machine cycles.
Which of these seven takes place is defined by the
status of the three status lines (101M, Sl, So) and
Table 3. 8085AH Machine Cycle Chart
Status
Machine Cycle
Control
101M
51
SO
RD
WR
INTA
OPCODE FETCH
(OF)
0
1
1
0
1
1
MEMORY READ
. (MR)
0
1
0
0
1
1
(MW)
0
0
1
1
0
1
1/0 READ
(lOR)
1
1
0
0
1
1
1/0 WRITE
(lOW)
1
0
1
1
0
1
ACKNOWLEDGE
OFINTR
(INA)
1
1
1
1
0
BUS IDLE
(BI):
0
1
0
1
1.
1
1
1
TS
1
1
MEMORY WRITE
DAD
ACK.OF
RST,TRAP
HALT
1
1
1
1
TS
0
0
TS
Table 4. 8085AH Machine State Chart
Machine
State
Status & Buses
Control
51,50
101M
Aa-A1s
ADo-AD7
T1
X
X
X
X
T2
X
X
X
X
TWAIT
X
X
X
X
T3
X
X
X
X
T4
1
X
Ts
1
X
RD,WR
INTA
ALE
1
1
1*
X
X
0
X
X
0
X
X
0
TS
1
1
0
TS
1
1
0
Ts
1
ot
ot
ot
X
TS
1
1
0
TRESET
X
TS
TS
TS
TS
1
0
THALT
0
TS
TS
TS
TS
1
0
THOLD
X
TS
TS
TS
TS
1
0
o = LogIC "0"
T$ = HIgh Impedance
1 = Logic "1"
X = Unspecified
• ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
t 101M = 1 during T4- T6 of INA machine cycle.
.
13-20
inteL
8085AH/8085AH-2/8085AH-1
M,
CLK
Aa-A'5
M2
M3
T,
PCH (HIGH ORDER ADDRESS)
(PC + l!H
ADO_1
ALE
AD
WR
101M
STATUS
S,So (FETCH)
10 (READ)
01 WRITE
11
231718-14
Figure 10. 8085AH Basic System Timing
13-21
..
8085AH/8085AH-2/8085AH-1
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature under Bias ...... ooe to 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on Any Pin
with Respect to Ground .......... - 0.5V to + 7V
Power Dissipation .......................... 1.5W
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
D.C. CHARACTERISTICS
ooe to 70°C, Vee = 5V ± 10%, Vss = OV; unless otherwise specified'
ooe to 70°C, Vee = 5V ±5%, Vss = OV; unless otherwise specified'
8085AH, 8085AH-2: TA =
8085AH-1: TA =
Sym!lol
Parameter
Min
Max
Units
VIL
Input low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
VOL
Output low Voltage
0.45
V
IOL
VOH
Output High Voltage
V
IOH
lee
Power Supply Current
2.4
Test Conditions
= 2mA
= - 400 p,A
135
rnA
8085AH, 8085AH-2
200
rnA
8085AH-1
o sVIN s Vee
0.45V s VOUT s
IlL
Input leakage
±10
p,A
ILO
Output leakage
±10
p,A
VILR
Input low level, RESET
-0.5
+0.8
V
VIHR
Input High level, RESET
2.4
Vee + 0.5
V
VHY
Hysteresis, RESET
0.15
Vee
V
A.C. CHARACTERISTICS
8085AH, 8085AH-2: TA =
ooe to 70°C, Vee
= 5V ± 10%, Vss = OV'
8085AH-1: TA = O°C to 70°C, Vee = 5V ±5%, VSS = OV
Symbol
teye
Parameter
ClK Cycle Period
8085AH (2)
8085AH-2 (2)
8085AH-1 (2)
Min
Max
Min
Max
Min
Max
320
2000
200
2000
167
2000
Units
ns
t1
ClK low Time (Standard ClK loading)
80
40
20
ns
t2
ClK High Time (Standard ClK loading)
120
70
50
ns
tr, tf
ClK Rise and Fall Time
tXKR
X1 Rising to ClK Rising
tXKF
X1 Rising to ClK Falling
tAe
AS-15 Valid to leading Edge of Control (1)
270
240
tAeL
AO-7 Valid to leading Edge of Control
tAD
AO-15 Valid to Valid Data In
tAFR
Address Float after leading Edge of
READ (INTA)
tAL
AS-15 Valid before Trailing Edge of ALE (1)
30
20
120
20
150
30
20
100
20
110
115
30
ns
20
100
ns
20
110
ns
70
115
ns
60
ns
575
350
225
ns
0
0
0
ns
115
- °NOTE:
For Extended Temperature EXPRESS use MSOS5AH Electricals Parameters.
13-22
50
25
ns
inteL
8085AH/8085AH-2/8085AH-1
A.C. CHARACTERISTICS (Continued)
Symbol
8085AH (2)
Parameter
Min
tALL
AO-7 Valid before Trailing Edge of ALE
tARY
READY Valid from Address Valid
tCA
Address (AS-15) Valid after Control
tcc
Width of Control low (RD, WR, INT A)
Edge of ALE
tCL
Trailing Edge of Control to leading Edge
of ALE
tDW
Data Valid to Trialing Edge of WRITE
tHABE
HlDA to Bus Enable
tHABF
Bus Float after HlDA
tHACK
HlDA Valid to Trailing Edge of ClK
tHDH
HOLD Hold Time
tiNS
INTR, RST, and TRAP Setup Time to
Falling Edge of ClK
tLCK
ALE low During ClK High
tLDR
ALE to Valid Data during Read
tLDW
ALE to Valid Data during Write
tLL
ALE Width
tLRY
ALE to READY Stable
tRAE
Trailing Edge of READ to Re-Enabling
of Address
Units
Max
25
ns
40
100
ns
60
230
30
150
ns
50
25
0
ns
ns
140
230
150
150
210
210
tlNH
Address Hold Time after ALE
Min
Max
120
400
420
HOLD Setup Time to Trailing Edge of ClK
Trailing Edge of ALE to leading Edge
of Control
Min
220
INTR Hold Time
tLA
8085AH-1 (2)
50
90
tHDS
tLC
Max
8085AH-2 (2)
ns
150
150
ns
ns
110
0
170
0
160
40
0
120
0
150
0
0
120
0
150
100
130
50
60
20
25
ns
100
50
15
ns
460
200
140
110
30
ns
ns
ns
ns
ns
10
50
150
300
ns
50
90
150
ns
175
110
270
140
80
ns
ns
ns
ns
75
ns
tRD
READ (or INTA) to Valid Data
tRV
Control Trailing Edgeto leading Edge
of Next Control
400
220
160
ns
0
0
110
0
0
100
0
5
100
ns
tRDH
Data Hold Time after READ INTA
tRYH
READY Hold Time
tRYS
READY Setup Time to leading Edge
ofClK
tWD
Data Valid after Trailing Edge of WRITE
tWDL
lEADING Edge of WRITE to Data Valid
100
60
40
ns
ns
30
20
ns
30
ns
NOTES:
1. As-A15 address Specs apply 101M, So, and S1 except As-A15 are undefined during T4-T6 of OF cycle whereas 101M,
So, and S1 are stable.
2. Test Conditions: tCYC = 320 ns (8085AH)/200 ns (8085AH-2);/167 ns (8085AH-1); CL = 150 pF.
3. For all output timing where C =/= 150 pF use the following correction factors:
25 pF $: CL < 150 pF: -0.10 ns/pF
150 pF < CL $: 300 pF: + 0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. To calculate timing specifications at other values of tCYC use Table 5.
13-23
II
int'eL
8085AH/8085AH-2/8085AH-1
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT {OUTPUT
"=X
2.0
0.45
0.8
>
<
2.0
TEST POINTS
0.8
x=
DEVICE
UNDER
TEST
231718-15
~CL~150PF
-=
231718-16
CL ~ 100 pF
CL Includes Jig Capacitance
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
Table 5. Bus Timing Specification as a T eye Dependent
8085AH
Symbol
8085AH-2
8085AH-1
tAL
(1/2)T - 45
(1/2)T - 50
(1/2)T - 58
Minimum
tLA
(1/2)T - 60
(1/2)T - 50
(1/2)T - 63
Minimum
tll
(1/2)T - 20
(1/2)T - 20
(1/2)T - 33
Minimum
tlCK
(1/2)T - 60
(1/2)T - 50
(1/2)T - 68
Minimum
tlC
(1/2)T - 30
(1/2)T - 40
(1/2)T - 58
Minimum
+ N)T + N)T -
225
(5/2
180
(3/2
+
+
N)T - 150
(5/2
N)T - 150
(3/2
+ N)T + N)T -
192
Maximum
175
Maximum
tAD
(5/2
tAD
(3/2
tAAE
(1/2)T - 10
(1/2)T - 10
(1/2)T - 33
Minimum
tCA
(1/2)T - 40
(1/2)T - 40
(1/2)T - 53
Minimum
tow
(3/2
+
Minimum
two
(1/2)T - 60
tcc
(3/2
tCl
(1/2)T - 110
(1/2)T - 75
tARY
(3/2)T - 260
tHACK
(1/2)T - 50
+ N)T
+
tHABF
(1/2)T
tHABE
(1/2)T
- 60
N)T - 80
+ 50
+ 50
(3/2
+ N)T -
70
(1/2)T - 40
(3/2
+ N)T -
70
(3/2
N)T - 110
(1/2)T - 53
Minimum
+
Minimum
(3/2
N)T - 100
(1/2)T - 83
Minimum
(3/2)T - 200
(3/2)T - 210
Maximum
(1/2)T - 60
(1/2)T - 83
Minimum
+ 67
+ 67
Maximum
(1/2)T
(1/2)T
+ 50
+ 50
(1/2)T
(1/2)T
Maximum
tAC
(2/2)T - 50
(2/2)T - 85
(2/2)T - 97
Minimum
t1
(1/2)T - 80
(1/2)T - 60
(1/2)T - 63
Minimum
t2
(1/2)T - 40
(1/2)T - 30
(1/2)T - 33
Minimum
tAV
(3/2)T - 80
(3/2)T - 80
(3/2)T - 90
Minimum
tlOA
(4/2
(4/2)T - 130
(4/2)T - 159
Maximum
+
N)T - 180
NOTE:
N is equal to the total WAIT states. T = tCyc.
13-24
intel~
8085AH/8085AH-2/8085AH-1
WAVEFORMS
CLOCK
X, INPUT
elK
OUTPUT
-1,------1
- - - - - - - tcye - - - - - - _ . 1
------ t X K F - -
231718-17
READ
T,
elK
, )!
)j
I
ADDRESS
---
-------_.. _-
~.
ADDRESS
____
_Ill _
t
LA
t
AFR
-
_
_tAL_
RO/INTA
-4----
AC
-41// ;W')
- ____ tAO __
tAOH ___
DATA IN
-
t
CA
_
~1_tRAE
"I<.
I
-I r - -
tLC~--"
~
-'Cl~J
tLDR----~
=:::--
II
1'---
-_
J
_ I
'\-.--J/
llCK_
'\-_-J
T,
T3
\\-.----Jlr---~'-----J'
_
ALE
T,
1
~l
.t
_
231718-18
WRITE
T,
''-_....II
)!
r--
).
I-
X
ADDRESS
tLOW
I'CA-I
-
)
lLA-~
tLL _ I . . -
~
ALE
- tow
. -two--I
I
: - - tWDL
~tAL_
WR
X
DATA OUT
ADDRESS
f--
- tee
-'l=f
.
-.t
CL
_
r----tAC-
231718-19
13-25
int:eL
8085AH/8085AH-218085AH-1
WAVEFORMS (Continued)
HOLD
T,
T,
:\
\
ClK
\
/
~~
"\
t.t
'HDS'" ..r-tHDH
HACK --
t
HLDA
\.
t HABF -
I.
tHABE-I.
>---;
(ADDRESS, CONTROLS)
BUS
T,
T HOLD
/
t
HOLD
T HOLD
I
231718-20
READ OPERATION WITH WAIT CYCLE (TYPICAL)-SAME READY TIMING APPLIES TO WRITE
T,
1
T,
~
CLK
--
IIa-A,.
ADo-AD,
)
)
tLCK
-
'Al
I
I~READY
_ICA_
-
'AD
j#§)!
~'LAtAFR_
RD/iNTA
J
\
ADDRESS
,.
T,
ADDRESS
jr-'"ALE
T,
TWAIT
.
-
IJ
'ARY
,I
'RYS
-
'RO
---'CC
'RYH
·f'RAE~
-,..
DATA IN
;
-I
-'Cl~y
"I_
IRYS
--{----I------I1IIIIII/A
,I
'i
-'LC_1'\l
I.---.- 'LRY..
..
ILDR
1tAC
tRDH
tRYH
I
231718-21
NOTE:
1. Ready must remain stable during setup and hold times.
13-26
intel .
8085AH/8085AH-2/8085AH-1
WAVEFORMS (Continued)
INTERRUPT AND HOLD
1-----
BUS FLOATING"
-----1
ALE
~,------------~~--~~----------------~
•
HOLD
HLDA
231716-22
-NOTE:
101M is also floating during this time.
13-27
int'et
808SAH/808SAH-2/808SAH-1
Table 6. Instruction Set Summary
Mnemonic
Instruction Code
07 06 Os 04 03 O2 01 Do
Operations
Description
M
MOVE, LOAD AND STORE
0
1 D D D S S
MOVM.r
0
1
0
1 D D D 1
MOVr.M
MVlr
,
1
0
S Move register
to register
S S S Move register
to memory
1
0 Move memory
POPPSW 1 1
1 1 0
0 0
XTHL
1 1
1 0
0
SPHL
1
LXISP
0 0
1 1 0
0 0
1 Load immediate
stack pointer
INXSP
0
0
1 1 0
0
1 Increment stack
pointer
0
0
1 1
1 1 1
0
1 0
0 D D D 1
1
0 Move immediate
0
register
MVIM
0
0
1
1
0
1
1
0 Move immediate
1 Pop A and Flags
off stack
1 1 Exchange top of
stack,H & L
to register
0
Operations
Description
STACK OPS (Continued)
MOVr1 r2
1
.
Instruction Code
nemomc 07 06 Os 04 03 02 01 Do
1
memory
1 H & Ltostack
pointer
LXI B,
0
0
0
0
0
0
0
1 Load immediate
register Pair B & C
DCXSP
LXID
0
0
0
1
0
0
0
1 Load immediate
register Pair D & E
JUMP
JMP
1
1 0
0 0
LXIH
0
0
1
0
0
0
0
1 Load immediate
register Pair H &
JC
1
1 0
1
STAXB
0
0
0
0
0
0
1
0 Store A indirect
JNC
1 1 0
STAXD
0
0
0
1
0
0
1
0 Store A indirect
JZ
1 1 O. 0
LDAXB
0
0
1
0
1
0
1
0 Load A indirect
JNZ
1 1 0
LDAXD
0
0
0
1
1
0
1 0 Load A indirect
JP
1
STA
0
0
1
1
0
0
1
0 Store A direct
JM
1 1
JPE
1
1 1 0
1 0
JPO
1
1 1 0
0 0
1
o Jump on parity odd
PCHL
1
1 1 0
1 0
0
1 H & L to program
counter
L
LDA
0
0
1
1
1
0
1
0 Load A direct
SHLD
0
0
1
0
0
0
1
0 Store H & L direct
LHLD
0
0
1
0
1
0
1
0 Load H & L direct
XCHG
1
1
1
0
1
0
1
1 Exchange D & E,
H & L Registers
PUSHD
PUSHH
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
0 Jump on minus
0 Call on carry
CNC
1 1 0
1 0
1 0
0 Call on no carry
CZ
1 1 0
0
CNZ
1 1 0
0 0
1 0
CP
1
1
1 1 0
1 0
0 Call on positive
CM
1
1 1 1
1
1 0
0 Calion minus
1 Push A and Flags
on stack
CPE
1 1 1 0
1
1 0
0 Call on parity even
CPO
1 1 1 0
0
1 0
0 Call on parity odd
RETURN
1 Push register Pair
B & Can stack
1 Push register Pair
D & E on stack
1 Push register Pair
H & L on stack
0
0
0
1 Pop register Pair
B & C off stack
POPD
1
1
0
1
0
0
0
1 Pop register Pair
D & E off stack
RET
1 1 0
RC
1
1 Pop register Pair
H & L off stack
RNC
1
RZ
1
0
1
1 0 Jump on parity even
1 0
0
0
1 0 Jump on positive
1 1
0
0
1 0 Jump on no zero
0
1
0
1 1 0
1 0 Jump on zero
1 1 0
1
1
1
0
0
1 0 Jump on no carry
1 1 0
POPB
1
1
0
0 0 0
1 Jump unconditional
1 0 Jump on carry
CC
1
1
1
0
0
1 0
1
CALL
PUSH
PSW
POPH
1
0
1 0
1 1 1 0
1
0
1 0
1 1 Decrement stack
painter
CALL
STACKOPS
PUSHB
1 0
13·28
0
1 1 0
1 1 0
1 0
0
1 Call unconditional
0 Call on zero
0 Call on no zero
1 Return
1 1 0
0 0 Return on carry
1 0
1 0
0
0 0 Return on no carry
1 0
0
0 0 0 Return on zero
1 0
1
8085AH/8085AH-2/8085AH-1
Table 6. Instruction Set Summary (Continued)
M
.
Instruction Code
nemomc 07 Os 05 04 03 02 01 Do
Operations
Description
RETURN (Continued)
M
.
Instruction Code
nemomc 07 Os 05 04 03 02 01 Do
Operations
Description
ADD (Continued)
RNZ
1
1 0
0
0
0
0
0 Return on no zero
DADD
0 0 0 1 1 0 0 1 AddD&EtoH&L
RP
1
1
1
1 0
0
0
0 Return on positive
DADH
0 0 1 0 1 0 0 1 Add H & Lto H & L
RM
1
1
1
1
1 0
0 0 Return on minus
DADSP
RPE
1
1
1 0
1 0
0
0 Return on
parity even
0 0 1 1 1 0 0 1 Add stack pointer
to H & L
RPO
1
1
1 0
0
0
0 Return on
parity odd
1
1 A A A 1
0
SUBTRACT
RESTART
RST
1
1 0
1
1 0
OUT
1
1 0
1 0
0
1
1 Input
1
1 Output
INR r
0
0 D D D 1 0
0 Increment register
DCRr
0
0 D D D 1 0
1 Decrement register
INRM
0
0
1 0
1 0
DCRM
0
0
1
1 0
1 0
INXB
0 0
0
0.0
0
INXD
0
0
0
1 0
0
SBBr
1 0 0 1 1 S S S Subtract register
from A with borrow
SUBM
1 0 .0 1 0 1 1
o Subtract memory
SBBM
1 0 0 1 1 1 1
o Subtract memory
SUI
1 1 0 1 0 1 1
o Subtract immediate
SBI
1 1 0 1 1 1 1
o Subtract immediate
from A
from A with borrow
INCREMENT AND DECREMENT
1
1 0 0 1 0 S S S Subtract register
from A
1 1 Restart
INPUTIOUTPUT
IN
SUB r
from A
from A with borrow
0 Increment memory
1 Decrement memory
LOGICAL
ANAr
1 0 1 0 0 S S S And register with A
XRAr
1 Increment D & E
registers
1 0 1 0 1 S S S Exclusive OR
register with A
ORAr
1 0 1 1 0 S S S OR register
with A
CMPr
1 0 1 1 1 S S S Compare register
with A
1 1 Increment B & C
registers
1
INXH
0
0
1 0
0
0
1
1 Increment H & L
registers
DCXB
0
0
0 0
1 0
1
1 Decrement B & C
DCXD
0
0
0
1
1 0
1
1 Decrement D & E
ANAM
1 0 1 0 0 1 1
1 Decrement H & L
XRAM
1 0 1 0 1 1 1
ORAM
1 0 1 1 0 1 1
CMPM
1 0 1 1 1 1 1
o OR memory with A
o Compare
ANI
1 1 1 0 0 1 1
o And immediate
DCXH
0
0
1 0
1 0
1
with A
ADD
ADDr
1 0
0
0 0
ADCr
1 0
0
0
o And memory with A
o Exclusive OR memory
S S S Add register to A
1 S S S Add register to A
with carry
memory with A
ADDM
1 0 C 0
0
1
1 0 Add memory to A
ADCM
1 0
0
0
1
1
1 0 Add memory to A
with carry
XRI
1 1 1 0 1 1 1
o Exclusive OR
ADI
1 1 0
0
0
1
1 0 Add immediate to A
ORI
1 1 1 1 0 1 1
o OR immediate
ACI
1 1 0
0
1
1
1 0 Add immediate to A
with carry
CPI
1 1 1 1 1 1 1
o Compare
DADB
0 0
0
0
1 0
0
with A
immediate with A
with A
1 AddB&CtoH&L
immediate with A
13-29
•
8085AH/8085AH-2/8085AH-1
Table 6. Instruction Set Summary (Continued)
Mnemonic
Instruction Code
D7 D6 D5 D4 D3 D2 D, Do
Operations
Description
ROTATE
Instruction Code
Mnemonic 0-, D8 D5 D4 D3 D2 D, Do
Operations
Description
CONTROL
1
1
1 Rotate A left
EI
1
1
1
1
1
1
1 Rotate A right
DI
1
1
1
1 0
0
1
1 Disable Interrupt
RAL
a a 0 a 0
a a a 0 1
a a a 1 a
1
1
1 Rotate A left
through carry
NOP
0
0
a
0 No-operation
HLT
0
a a a a
1 1 1 a
1
1
a
RAR
0
1
1
1 Rotate A right
through carry
NEW 8085AH INSTRUCTIONS
SIM
RLC
RRC
0
0
1
1
RIM
SPECIALS
a
a a
1
a
1
1
1
1 Complement A
STC
1
1
a
1
1
1 Set carry
CMC
0
0
1
1
1
1
1
1 Complement carry
DAA
0
a
1
a a
1
1
1 Decimal adjust A
CMA
0
1
1 Enable Interrupts
0
1
0
a
0
a a
a a
1
1
0
a
0
-0
NOTES:
1. DDS or SSS: B 000, C 001, D 010, EO", H 100, L101, Memory 110, A 111.
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags .
• All mnemonics copyrighted @Intel Corporation 1976.
13-30
1 0
Halt
Read Interrupt
Mask
0 Sefinterrupt Mask
8155H/8156H/8155H-2/8156H-2
2048-BIT STATIC HMOS RAM
WITH 1/0 PORTS AND TIMER
•
•
•
•
•
•
•
•
Single + 5V Power Supply with 10%
Voltage Margins
30% Lower Power Consumption than
the 8155 and 8156
1 Programmable 6-Bit 1/0 Port
Programmable 14-Bit Binary CounterI
Timer
with 8085AH and 8088 CPU
• Compatible
Multiplexed Address and Data Bus
• Available in EXPRESS
• - Standard Temperature Range
256 Word x 8 Bits
Completely Static Operation
Internal Address Latch
- Extended Temperature Range·
2 Programmable 8-Bit I/O Ports
The Intel® 8155H and 8156H are RAM and I/O chips implemented in N-Channel, depletion load, silicon gate
technology (HMOS), to be used in the 8085AH and 8088 microprocessor systems. The RAM portion is
designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit
use with no wait states in 8085AH CPU. The 8155H-2 and 8156H-2 have maximum access times of 330 ns for
use with the 8085H-2 and the 5 MHz 8088 CPU.
The 110 portion consists of three general purpose I/O ports. One of the three ports can be programmed to be
status pins, thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter ltimer is also included on chip to provide either a square wave or terminal •
count pulse for the CPU system depending on timer mode.
.
10/M
256 X 8
ADo· ,
STATIC
RAM
*
ALE
RD
WR
RESET
TIMER
G
G
PIIo-,
pCa - 5
vcc (+5Vl
vss (OVI
TIMER elK
Vee
PC.
PC.
PC,
RESET
PC.
PC,
PB,
TIMER OUT
PBs
101M
8
TIMER OUT
'8155H/8155H·2
PAo-,
PC 3
231719-1
= CEo 8156Hi8156H·2 = CE
flO
WR
PB,
PB.
PB 3
PB.
ALE
PB,
AO.
PB.
AO,
PA,
AO.
PAs
A0 3
PA,
AD.
AD,
PA.
PA 3
AD.
PA.
AD,
PA,
vss
PAg
231719-2
Figure 1, Block Diagram
Figure 2. Pin Configuration
13-31
December 1986
Order Number: 231719-001
~;J~\
8155H/8156H/8155H-2/8156H-2
Table 1. Pin Description
Type
Name and Function
RESET
I
RESET: Pulse provided by the 8085AH to initialize the system (connect to
8085AH RESET OUT). Input high on this line resets the chip and initializes the
three 1/0 ports to input mode. The width of RESET pulse should typically be
two 8085AH clock cycle times.
ADo_7
I/O
ADDRESS/DATA: 3-state Address/Data lines that interface with the CPU
lower 8·bit Address/Data Bus. The 8·bit address is latched into the address
latch inside the 8155H/56H on the falling edge of ALE. The address can be
either for the memory section or the I/O section depending on the 101M input.
The 8-bit dataJ!..either written into the chip or read from the chip, depending
on the WR or RD input signal.
Symbol
CEorCE
I
CHIP ENABLE: On the 8155H, this pin is CE and is ACTIVE LOW. On the
8156H, this pin is CE and is ACTIVE HIGH.
RD
I
READ CONTROL: Input low on this line with the Chip Enable active enables
and ADo-7 buffers. If 101M pin is low, the RAM content will be read out to the
AD bus. Otherwise the content of the selected 1/0 port or commandlstatus
registers will be read to the AD bus.
WR
I
WRITE CONTROL: Input low on this line with the Chip Enable active causes
the data on the Address/Data bus to be written to the RAM or 1/0 ports and
commandlstatus register, depending on 101M.
.
ALE
I
ADDRESS LATCH ENABLE: This control signal latches ~th the address on
the ADo_7lines and the state of the Chip Enable and 101M into the chip at the
falling edge of ALE.
101M
I
I/O MEMORY: Selects memory if low and 1/0 and commandlstatus registers
if high.
PAO-7 (8)
1/0
PORT A: These 8 pins are general purpose 1/0 pins. The inlout direction is
selected by programming the command register.
PBO-7 (8)
I/O
PORT B: These 8 pins are general purpose 1/0 pins. The inlout direction is
selected by programming the command register.
PCO-5 (6)
1/0
PORT C: These 6 pins can function as either input port, output port, or as
control signals for PA and PB. Programming is done through the command
register. When PCO~5 are used as control Signals, they will provide the
following:
PCo-A INTR (Port A Interrupt)
PC1-ABF (Port A Buffer Full)
PC::A STB. (Port A Strobe)
PCs-B INTR (Port B Interrupt)
PC4-B BF (Port B Buffer Full)
PCs-B STB (Port B Strobe)
TIMER IN
I
TIMER INPUT: Input to the timer·counter.
TIMER OUT
0
TIMER OUTPUT: This output can be either a square wave or a pulse,
depending on the timer mode.
+ 5V supply.
Vee
VOLTAGE:
Vss
GROUND: Ground reference.
13-32
inteL
8155H/8156H/8155H-2/8156H-2
FUNCTIONAL DESCRIPTION
I
I
I
I
I
I
The 8155H/8156H contains the following:
• 2K Bit Static RAM organized as 256 x 8
• Two 8-bit I/O ports (PA & PB) and one 6-bit I/O
port (PC)
• 14-bit timer-counter
I
I
I
I
I
I
I
I
I
TIMER
MODE
I
I
_ _ _ _ _ _ _ _ _ ...3
I
I
I
I
I
The 10/M (IO/Memory Select) pin selects either the
five registers (Command, Status, PAO-7, PBO-7,
PCO-5) or the memory (RAM) portion.
L ____ _
231719-3
The 8-bit address on the Address/Data lines, Chip
Enable input CE or CE, and 10/M are all latched onchip at the falling edge of ALE.
CE(B155H)
Figure 3. 8155H/8156H Internal Registers
\
V
'\
/
1\
/
\
V
\
OR
CE(31!5eH)
101M
7
X
ADDRESS
I\.
j
X
II
DATA VALID
Al E
R
NOTE:
231719-4
For detailed timing information, see Figure 12 and A.C. Characteristics.
Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle
..
13-33
8155H/8156H/8155H·2/8156H·2
PROGRAMMING OF THE COMMAND
REGISTER
READING THE STATUS REGISTER
The status register consists of seven latches, one
for each bit; six (0-5) for the status of the ports and
one (6) for the status of the timer.
The command register consists of eight latches.
Four bits (0-3) define the mode of the ports, two bits
(4-5) enable or disable the interrupt from port C
when it acts as control port, and the last two bits
(6-7) are for the timer.
The status of the timer and the liD section can be
polled by reading the Status Register (Address
XXXXXOOO). Status word format is shown in Figure
6. Note that you may never write to the status register since the command register shares the same liD
address and the command register is selected when
a write to that address is issued.
The command register contents can be altered at
any time by using the liD address XXXXXOOO during
a WRITE operation with the Chip Enable active and
101M = 1. The meaning of each bit of the command
byte is defined in Figure 5. The contents of the command register may never be read.
r=
lIM, TMII'EBI'EAI pc,' PC,
L----l
PB' PA
I
DF.FINESPA .., }
DEFINES PBO_7
0'" INPUT
" '" OUTPUT.
DO
DEFINES PCo-s
=
All 1
11=ALT2
{
01
=
ALT 3
10=AlT4
' -_ _ _ _ _ _ ENABLE PORT A
INTERRUPT
1 '" ENABLE
}
' -_ _ _ _ _ _ _ ~.:'r"E"RL~J,.~RT B
0= DISABLE
00'" NOP - DO NOT AFFECT COUNTER
OPERATION
01
=
STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING IF THE TIMER IS
RUNNING
-TIMER COMMAND
10'" STOP AFTER re - STOP IMMEDIATELY
AFTER PRESENT Te IS REACHED (NOP
IF TIMER HAS NOT STARTED)
"
= START - LOAD MODE AND CNT LENGTH
AND START IMMEDIATELY AFTER
LOADING (IF TIMER IS NOT PRESENTLY
RUNNING). IF TIMER IS RUNNING, START
THE NEW MODE AND CNT LENGTH
IMMEDIATEL Y AFTER PRESENT Te
IS REACHED.
231719-5
Figure 5. Command Register Bit Assignment
AD,
.0_
ADs
AD4
AD]
AD2
AD,
lXITlMFAII~TEI B~ IIN~RII~EI ~
!
I I
ADo
IIN;AI
L
~
PORT A INTERRUPT REOUEST
PORT A BUFFER FULL/EMPTY
(INPUT/OUTPUT)
PORT A INTERRUPT ENABLE
PORT B INTERRUPT ReQUEST
PORT B BUFFER FUll/EMPTY
{INPUT/OUTPUTI
PORT B INTERRUPT ENABLED
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED •.• AND IS RESET TO
LOW UPON READING OF THE
CIS REGISTER AND BY
HARDWARE RESET).
231719-6
Figure 6. Status Register Bit Assignment
13-34
intel .
8155H/8156H/8155H-2/8156H-2
ond is an output signal indicating whether the
buffer is full or empty, and the third is an input pin
to accept a strobe for the strobed input mode.
(See Table 2.)
INPUTIOUTPUT SECTION
The I/O section of the 8155H/8156H consists of
five registers: (see Figure 7.)
• CommandlStatus Register (C/S}--Both registers are assigned the address XXXXXOOO. The
CIS address serves the dual purpose.
When the CIS registers are selected during
WRITE operation, a command is written into the
command register. The contents of this register
are not accessible through the pins.
When the CIS (XXXXXOOO) is selected during a
READ operation, the status information of the liD
ports and the timer becomes available on the
ADo-7 lines.
• PA Register-This register can be programmed
to be either input or output ports depending on
the status of the contents of the CIS Register.
Also depending on the command, this port can
operate in either the basic mode or the strobed
mode (see timing diagram). The liD pins assigned in relation to this register are PAO-7. The
address of this register is XXXXX001.
• PB Register-This register functions the same
as PA Register. The liD pins assigned are
PBO-7' The address of this register is XXXXX010.
• PC Register-This register has the address
XXXXX011 and contains only 6 bits. The 6 bits
can be programmed to be either input ports, output ports or as control signals for PA and PB by
properly programming the AD2 and AD3 bits of
the CIS register.
When PCO-5 is used as a control port, 3 bits are
assigned for Port A and 3 for Port B. The first bit
is an interrupt that the 8155H sends out. The sec-
When the 'C' port is programmed to either ALT3 or
ALT4, the control signals for PA and PB are initialized as follows:
Control
BF
INTR
STB
Input Mode
Low
Low
Input Control
1/0 Addresst
Selection
A7 A6 A5 A4 A3 A2 Al AD
X X X X X 0
0
X X X X X 0
X X X X X 0
X X X X X 0
0
X X X X X 1
0
X X X X X 1
0
1
1
0 Interval Command/Status
Register
1 General Purpose I/O Port A
0 General Purpose I/O Port B
1 Port C-General Purpose
I/O or Control
0 Low-Order 8 bits of Timer
Count
1 High 6 bits of Timer Count
and 2 bits of Timer Mode
X: Don't Care.
t: I/O Address must be qualified by CE = 1 (BI56H) or CE
= 0 (8155H) and 10/M = 1 in order to select the appropriate register.
Figure 7. 110 Port and Timer Addressing Scheme
Figure 8 shows how liD PORTS A and B are structured within the 8155H and 8156H:
8155H/8156H One Bit of Port A or Port B
NOTES:
(1) Output Mode
(2) Simple Input
(3) Strobed Input
1 .
Multiplexer
Control
Output Mode
Low
High
Input Control
STO
(4) = 1 for Output Mode
= 0 for Input Mode
READ Port = (IO/M = 1) • (RD = 0) • (CE Active). (Port Address Selected)
WRITE Port = (101M = 1). (WR = 0) • (CE Active) • (Port Address Selected)
Figure 8. 8155H/8156H Port Functions
13-35
231719-7
II
intet
8 t55H/8156H/8155H-2/8156H-2
Table 2 Port Control Assignment
Pin
ALT1
ALT2
PCO
PC1
PC2
PC3
PC4
PC5
Input Port
Input Port
Input Port
Input Port
Input Port
Input Port
Output Port
Output Port
Output Port
Output Port
Output Port
Output Port
ALT3
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
Output Port
Output Port
Output Port
Note in the diagram that when the 1/0 ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation
when appropriately addressed.
The outputs of the 8155H/8156H are "glitch-free"
meaning that you can write a "1" to !i bit position
that was previously "1" and the level at the output
pin will not change.
Note also that the output latch is cleared when the
port enters the input mode. The output latch cannot
be loaded by writing to the port if the port is in the
input mode. The result is that each time a port mode
is changed from input to output, the output pin will
go low. When the 8155H/56H is RESET, the output
latches are all cleared and all 3 ports enter the input
mode.
ALT4
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
B INTR (Port B Interrupt)
B BF (Port B Buffer Full)
B STB (Port B Strobe)
TIMER SECTION
The time is a 14-bit down-counter that counts the
TIMER IN pulses and provides either a square wave
or pulse when terminal count (TC) is reached.
The timer has the 1/0 address XXXXX100 for the
low order byte of the register and the 1/0 address
XXXXX101 for the high order byte of the register.
(See Figure 7.)
To program the timer, the COUNT LENGTH REG is
loaded first, one byte at a time, by selecting the timer addresses. Bits 0-13 of the high order count register will specify the length of the next count and bits
14-15 of the high order register will specify the timer
output mode (see Figure 10). The value loaded into
the count length register can have any value from
2H through 3FFFH in Bits 0-13.
When in the ALT 1 or ALT 2 modes, the bits of
PORT C are structured like the diagram above in the
simple input or output mode, respectively.
76543210
I I I
M,
Reading from an input port with nothing connected
to the pins will provide unpredictable results.
M,
T131 T121 Tn
I I
T,.
Tol
Tal
L.-..,-----J ,
r
MSB OF CNT LENGTH
TIMER MODE
76543210
I~I~I~I~I~I~I~I~I
Figure 9 shows how the 8155H/8156H 1/0 ports
might be configured in a typical MCS®-85 system.
I
I
LSB OF
CNT
LENGTH
231719-9
TO B085AH !'1ST INPUT
PORT A
"--1
PORT C
OUTPUT
-A) PORT A
A INTA{!'IGNAlS DATA RECEIVEDI
A BF (SIGNALS DATA READY)
I
A STB (ACKNOWL DATA RECEIVED)
B srB (LOADS PORT B LATCH)
B BF (SIGNALS BUFFER IS FULL!
B INTR (SIGNALS BUFFER
A.. REAOY FOR READING)
PORTa
Figure 10. Timer Format
1
INPUT
I
} m,,".
There are four modes to choose from: M2 and M1
define the timer mode, as shown in Figure 11.
PERIPHERAL
INTERFACE
TIMER OUT WAVEFORMS:
MODE
TO INPUT PORT (OPTIONAL)
BITS
TO B085AH RST INPUT
231719-8
Figure 9. Example:
Command Register == 00111001
Ml
Ml
o
0
START
COUNT
TERMINAL
COUNT
(TERMINAL)
COUNT
I
I
I
1. SINGLE
SQUARE WAVE
~-----------
2. CONTINUOUS
SOUAREWAVE
3
~~"c~~EON
----,V-----------
TERMINAL COUNT
4. CONTINUOUS
PULSES
----~ur--~u----
231719-10
Figure 11. Timer Modes
13-36
int'eL
8155H/8156H/8155H-2/8156H-2
Bits 6-7 (TM2 and TM1) of command register contents are used to start and stop the counter. There
are four commands to choose from:
TM2
o
o
TM1
0
o
Nap-Do not affect counter operation.
STOP-Nap if timer has not started; stop
counting if the timer is running.
STOP AFTER TC-Stop immediately after
present TC is reached (Nap if timer has not
started)
START-Load mode and CNT length and
start immediately after loading (if timer is not
presently running). If timer is running, start
the new mode and CNT length immediately
after present TC is reached.
Note that while the counter is counting, you may
load a new count and mode into the count length
registers. Before the new count and mode will be
used by the counter, you must issue a START command to the counter. This applies even though you
may only want to change the count and use the previous mode.
In case of an odd-numbered count, the first half-cycle of the squarewave output, which is high, is one
count longer than the second (low) half-cycle, as
shown in Figure 12.
-
5
231719-11
NOTE:
The counter in the 8155H is not initialized to any
particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore,
counting cannot begin following RESET until a
START command is issued via the CIS register.
Please note that the timer circuit on the 8155HI
8156H chip is designed to be a square-wave timer,
not an event counter. To achieve this, it counts
down by twos twice in completing one cycle. Thus,
its registers do not contain values directly representing the number of TIMER IN pulses received. You
cannot load an initial value of 1 into the count register and cause the timer to operate, as its terminal
count value is 10 (binary) or 2 (decimal). (For the
detection of single pulses, it is suggested that one of
the hardware interrupt pins on the 8085AH be used.)
After the timer has started counting down, the values residing in the count registers can be used to
calculate the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining count, perform the following operations in order:
1. Stop the count
2. Read in the 16-bit value from the count length
registers
3. Reset the upper two mode bits
4. Reset the carry and rotate right one position all 16
bits through carry
.
5. If carry is set, add % of the full original count (%
full count-1 if full count is odd).
NOTE:
If you started with an odd count and you read the
count length register before the third count pulse
occurs, you will not be able to discern whether one
or two counts has occurred. Regardless of this, the
8155H/56H always counts out the right number of
pulses in generating the TIMER OUT waveforms.
5 and 4 refer to the number of clocks in that time period.
Figure 12_ Asymmetrical Square-Wave Output
Resulting from Count of 9
13-37
II
intel®
8155H/8156H/8155H-2/8156H-2
• 2K Bytes EPROM
8085AH MINIMUM SYSTEM
CONFIGURATION
• 38 I/O Pins
• 1 Interval Timer
• 4 Interrupt Levels
Figure 13a shows a minimum system using three
chips, containing:
• 256 Bytes RAM
A8-15
A
=>
ADO·7
~lE
II085AH
'-
f--
Ro
I-I--
WR
101M
f-f--
elK
RESET OUT
I
READY
;>.
I--
r-
f-Vee
TIMER
RESET
T6~~R
_
IN
B
WARD
ALE
'-L
eE
L
256 x 8
RAM
81_
~
.fil0
_10/
/:.~ CE
M ALE
Iill,OW elK RS
ROY
I
LATCHES
--r------i
CONTROL
101M
AB-
1
J
J
~~~~
888
8755A (EPROM + 1/01
·8 8
231719-12
Figure 13a. 8085AH Minimum System Configuration (Memory Mapped I/O)
13-38
intel ~
8155H/8156H/8155H-2/8156H-2
8088 FIVE CHIP SYSTEM
• 38
1/0 Pins
• 1 Interval Timer
Figure 13b shows a five chip system containing:
• 2 Interrupt Levels
• 1.2SK Bytes RAM
• 2K Bytes EPROM
~ 0-
Vss
Vee
j
POR!~
I
I+-----
CE
~t--WR
Rii
PORT
~
(8)
8115"'2 B
PORT~
C
(6)
ALE
DATAl
ADOR
t-
---
IN_
101M
TIMER
OUT
RESET
Aa- A19 ~DilR
ADo - AD7
r---- ClK
l/t
"'
AODR/OATA
8088
.--
rD1
x,
RST@
~CKIREADY
I----
ALE
'--
~
r-
-V
f---
I---
Rii
-
f-- +-
WR
ttt-
~
8284
PORT
A
CE
A S _10
fN
875511-2
DATAl
ADDR
101M
RES
laIr;;
I
PORT
~- RESET
B
-
tell
\_t
cc -
'WT
I - t RV -
!\-
J
TIMER IN
~
231719-17
13-42
int:et
8155H/8156H/8155H-2/8156H-2
WAVEFORMS (Continued)
STROBED INPUT
BF
'sa,
INTR
INPUT DATA
FROM PORT
--------~~--~~~--------------------------231719-18
STROBED OUTPUT
BF
INTR
'WI
OUTPUT DATA
TO PORT
-------------------------------------------'~-------------------------------------------------------231719-19
BASIC INPUT
.BASIC OUTPUT
RD
',. i..
INPUT
===>(
DATA BUS· - , - - -
-
'., }
}
-
=-x:
-I
WR
~
DATA BUS·
OUTPUT
-------
231719-20
231719-21
"Data Bus Timing is shown in Figure 7.
13-43
~
iii:
m
:u
0
c:
~
'U
c:
~
0
2
)
-I
RELOAD COUNTER FROM CLR
I
2
I
1
"II
:u
0
i:
TIMER IN
U1
~
...
0
.....
c.l
TIMER OUT
(PULSE)
\
(NOTE 11
8
en
~
c:
CD
B
....
CD
UI
UI
J:
......
....CD
m
J:
......
II
....UICD
\ .. _ _ _ J
~
l
s:::
:i"
I~
_.
:II
~
C
--I
<
c:
z
LOAO COUNTER FROM CLR
~
m
."
0
00
0
)
:e
.
"'"
UI
J:
I\)
nMER OUT
(SOUARE WAVE)
\
(NOTE 11
\ '- _ _ _ _ _ _ _ _ J I
......
I
....
CD
UI
.
t:1I
J:
I\)
231719-22
NOTE:
1. The timer output is periodic if in an automatic reload mode (M1 Mode bit = 1).
~ 1$5/t8l ~ 85 2
3",[8l~T STAT~C RAM FOR
m
1f024 ~
Multiplexed Address and Data Bus
• Directly
8085AH and
Compa~ible wi~h
11
8088 Microprocessors
MCS®-85
II Low Standby Power Dissipation
@
Single
+ 5V Supply
EJ High Density 18·Pin Package
• Low Operating Power Dissipation
The Intel 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using Nchannel Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface
directly to the 8085AH and 8088 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085AH-2 and the
5 MHz 8088.
Yce
ADO
cs
CE,
.
CE2
RD
PJW
LOGIC
WR
ALE
~
t-..
ADo-ADr
r-v'
DATA
BUS
BUFFER
lKx8
RAM
r.1EMOFlY
ARMY
RD
AD2
WR
AD3
ALE
AD4
CS
ADs
CE,
1. 0 6
CE2
ADr
A9
Yss
A8
231450-2
Figure 2. Pin Configuration
X-V DECODE
~.~U
.
:>,.
Pin Names
ADO-AD7
LATCH
As,A9
ALE
AD,
As. Ag
CS
CE,
CE2
ALE
WR
231450-1
Figure 1. Block Diagram
13-45
Address/Data Lines
Address Lines
Chip Select
Chip Enable (IO/M)
Chip Enable
Address Latch Enable
Write Enable
November 1989
Order Number: 231450-002
8185/8185-2
FUNCTIONAL DESCRIPTION
The 8185 has been designed to provide for direct
interface to the multiplexed bus structure and bus
timing of the 8085A microprocessor.
-----
At the beginning of an 8185 memory access cycle,
the 8-bit address on ADo-7' As and Ag, and the
status of GEl and GE2 are all latched internally ,in
the 8185 by the falling edge of ALE. If the latched
status of both GEl and GE2 are active, the 8185
powers itself up, but no action occurs until the GS
line goes low and the appropriate RD or WR control
signal input is activated.
rlDh
TRAP
X,
Vss Vee
I II
RESET IN
HOLD
X,
IffSID Is,t--
RST7.5
HLDA
RST6.5
SOD
8085A
AST5.5
IN:rR
lfmI
ADDR
ADDR/
DATA ALE
'8'
1m
5or-
RESET
OUT
WR 101M
ROY eLK
VI Vr
,8,
I~+-
POR~W
CE
WR~
'
PORT
CE2
CS
(CS*)(2)
8185 Status
1
X
X
0
Power Down and
Function Disable(l)
X
0
X
0
Power Down and
Function Disable(l)
0
1
1
0
Powered Up and
Function Disable(l)
0
1
0
1
Powered Up and
Enabled
PORT~
ALE
DATAl
ADOR
"
C
(61
IN
.... t- r-
101M
TIMER
RESET
aUT
I=:
lOW
Rli
ALE
t-
Table 1. Truth Table for
Power Down and Function Enable
CE1
8)
110 8156 •
The GS input is not latched by the 8185 in order to
allow the maximum amount of time for address decoding in selecting the 8185 chip. Maximum power
consumption savings will occur, however, only when
GEl and GE2 are activated selectively to power
down the 8185 when it is not in use. A possible connection would be to wire the 8085A's 10/M line to
the 8185's GEl input, thereby keeping the 8185
powered down during 1/0 and interrupt cycles.
PORT
A
ee
"
i=
V
W
A II _10
8755A
DATAl
ADOR
~
t-
......
101M
PORT
RESET
RDY
B
fN
ClK
vs! v!c vto tRaG
WR
RD
CE,
8185
ALE
In-
NOTES:
X = Don't Care.
1: Function Disable implies Data Bus in high impedance
state and not writing.
2: CS* = (CEl = 0) X (CE2 = 1) x (CS = 0).
CS' = 1 signifies all chip enables and chip select active.
i
CS, CE2
~I-
As.Ag
ADG-7
t v!c
v"
Vee
Vee
Table 2. Truth Table for
Control and Data Bus Pin Status
'v
231450-3
ADo-7 During Data
(CS*) RD WR
8185 Function
Portion of Cycle
0
X X Hi-Impedance
1
0
1 Data from Memory Read
1
1
0 Data to Memory
Write
1
1
1 Hi-Impedance
Reading, but not
Driving Data Bus
'v
Figure 3. 8185 In an MCS®-85 System
4 Chips:
2K Bytes EPROM
1.25K Bytes RAM
38 I/O Lines
1 Counter/Timer
2 Serial I/O Lines
5 Interrupt Inputs
No Function
,NOTE:
X = Don't Care.
13-46
intet
8185/8185-2
iAPX 88 FIVE CHIP SYSTEM:
• 1.25K Bytes RAM
• 2K Bytes EPROM
• 38 I/O Pins
• 1 Internal Timer
• 2 Interrupt Levels
v••
/
Vee
I I
~ POR!~
1---
~r----_WR
POR~
RD
W
(8)
115502
PORT~
ALE
DATAl
ADDR
r-
---
tOIM
RESET
~-
Ae;-A19
ADo - AD7
ClK
-
AOOR
r Ol
X,
x,
CD
ClK
READY
-
-Vee
__
Tr-
-
r--
-
f-- f -
wn
-
RESET
ROY1
f--'-- -
RD
-
IZI4A
PORT
-
A
CE
ALE
101M
RES
ALE
~~
READY
RST
tN_
TIMER
OUT I--
RD
---'\
1=
MN/MX
(6)
row
-V
AODRIOATA
SOBS
-
-'\
C
~--1',
y
A
a. 10
~
181SIA~2
DATAl
ADDR
101M
I
PORT
~- RESET'
B
~
Vee
READY
tOR
1 11
-l
L.ROG
Vss Vee Voo
Vee
WJj
....
RO
CD
CEt '185-2
ALE
\-
CS,
T--
CE,
\-f--
Aa. Ag
V
ADO_7
! !
VS.
7-
Vee
7
231450-4
Figure 4. iAPX 88 Five Chip System Configuration
13·47
II
intel.
8185/8185-2
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Temperature Under Bias ............ O·C to + 70·C
Storage Temperature •......... - 6S·C to + 1S0·C
Voltage on Any Pin
; with Respect to Ground .......... - O.SV to + 7V
Power Dissipation .... , •...........•........ 1.SW
D.C. CHARACTERISTICS
Symbol
TA
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
= O·C to 70·C, Vcc = SV ± 10%
Min
Parameter
Max
Units
Vil
Input Low Voltage
-O.S
0.8
V
VIH
Input High Voltage
2.0
Vcc+ O.S
V
VOL
Output Low Voltage
O.4S
V
VOH
Output High Voltage
Test Conditions
IOl
2.4
IOH
= 2mA
= -400/LA
III
Input Leakage
±10
/LA
OV ~ VIN ~ Vcc
ILO
Output Leakage Current
±10
/LA
O.4SV ~
Icc
Vcc Supply Current
Powered Up
100
mA
Powered Down
3S
mA
A.C. CHARACTERISTICS
Symbol
TA = O·C to 70·C, Vcc =
sv
8185
Min
Address to Latch Set Up Time
~ Vcc
± 10%
Parameter
tAL
Your
8185·2
Max
Min
Max
Units
so
30
ns
tLA
Address Hold Time After Latch
80
30
ns
tlC
Latch to READ/WRITE Control
100
40
ns
tRO
Valid Data Out Delay from READ Control
170
140
ns
tLO
ALE to Data Out Valid
300
200
ns
tll
tROF
Latch Enable Width
100
Data Bus Float After HEAD
0
70
100
0
ns
80
ns
tCl
READ/WRITE Control to Latch Enable
20
10
ns
tec
READ/WRITE Control Width
2S0
200
ns
tow
Data In to WRITE Set Up Time
1S0
1S0
ns
two
Data In Hold Time After WRITE
20
20
ns
ns
tsc
Chip Select Set Up to Control Line
10
10
tcs
Chip Select Hold Time After Control
10
10
ns
ns
ns
tAlCE
Chip Enable Set Up to ALE Falling
30
10
tLACE
Chip Enable Hold Time After ALE
SO
30
13-48
intel®
8185/8185·2
A.C. TESTING INPUT, OUTPUT WAVEFORM
=x > x=
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
2.0
2 .•
TEST POINTS
D.e
0.45
DEVICE
UNDER
TEST
<
2.0
0.8
1"~"'"
-=-
231450-5
AC. Testing: Inputs Are Driven at 2.4V for a Logic "1" and
0.45V for a Logic "0." Timing Measurements Are Made at
2.0V for a Logic "1" and O.BV for a Logic "0."
231450-6
CL = 150 pF
CL Includes Jig Capacitance
WAVEFORM
ALE
(CE,-O).
ICE,"11
AOD"AD7
(READ CYCLE)
(Aa,Ag)
IWRITE CVCLEI
(DESELECTED)
ISELECTEDI
231450-7
13-49
•
8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
•
•
•
•
•
Single Chip Clock Generator/Driver for
8080A CPU
Power-Up Reset for CPU
Ready Synchronizing Flip-Flop
Advanced Status Strobe
Oscillator Output for External System
Timing
•
•
•
•
Crystal Controlled for Stable
System Operation
Reduces System Package Count
Available in EXPRESS
- Standard Temperature Range
Available in 16-Lead Cerdip Package
(See Packaging Spec, Order #231369)
The Intel 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected
by the designer to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe, and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing
for 8080A.
RESET
£E> XTALI
IE> XTAL2
m>
OSC
TANK
.,
CLOCK
GEN.
+"
ED
a:::>
rI>
~2(TTL)
IT>
II>
RESIN
READY
RDYIN
XTAL2
READY
TANK
SYNC
OSC
~2 (TTL)
~
~2
voo
IE>
DD
RESET
XTAL 1
RDYIN
STSTB
~2
STSTB
SYNC
IJD
Vee
RESIN
ID
[D
231464-2
RESIN
Reset Input
RESET
Reset Output
XTAll
RDYIN
Ready Input
XTAl2
READY
Ready Output
TANK
Used with Overtone XTAl
SYNC
Sync Input
OSC
Oscillator Output
STSTB
StatusSTB
(Active low)
1
cf>1 Pulse Width
t2
cf>2 Pulse Width
tD1
cf>1 to cf>2 Delay
0
tD2
cf>2 to cf>1 Delay
tD3
cf>1 to cf>2 Delay
2tcy
-14ns
9
2tcy
9
tR
cf>1 and cf>2 Rise Time
20
tF
cf>1 and cf>2 Fall Time
20
tD2
cf>2 to cf>2 (TIL) Delay
tDSS
,cf>2 to STSTB Delay
tpw
STSTB Pulse Width
tDRS
RDYIN Setup Time to
Status Strobe
tDRH
RDYIN Hold Time
afterSTSTB
tDR
RDYIN or RESIN to
cf>2 Delay
= 20 pF to 50 pF
ns
CL
cf>2TIl, Cl = 30
R1 = 3000.
R2 = 6000.
2tcy
+ 20ns
9
-5
+15
ns
6tcy
- 30ns
9
tcy
- - 15ns
9
4tcy
50ns - 9
4tcy
9
4tcy
- 25ns
9
6tcy
9
ns
STSTB, CL
R1 = 2K
R2 = 4K
= 15 pF
ns
ns
tcy
9
tCLK
ClK Period
f max
Maximum OSCillating
Frequency
27
MHz
Cin
Input Capacitance
8
pF
Ready & Reset
CL = 10 pF
R1 = 2K
R2 = 4K
ns
VCC = +5.0V
VDD = +12V
VSIAS = 2.5V
f = 1 MHz
NOTE:
These formulas are based on the internal workings of the part and intended for customer convenience. Actual testing of the
part is done at tcy = 488.28 ns.
13-52
intet
8224
A.C. CHARACTERISTICS (Continued)
For tey
= 488.28 ns; TA = O·C to 70·C, Vee = + 5V ± 5%, VOO = + 12V ± 5%
Symbol
Limits
Parameter
Typ
Min
Units
Max
t1
cf>1 Pulse Width
89
ns
t.,,2
cf>2 Pulse Width
236
ns
t01
Delay cf>1 to cf>2
0
ns
t02
Delay cf>2 to cf>1
95
ns
t03
Delay cf>1 to cf>2 Leading Edges
109
tr
Output Rise Time
t,
Output Fall Time
toss
cf>2 to STSTB Delay
296
tOcf>2
cf>2 to cf>2 (TTL) Delay
-5
+15
ns
tpw
Status Strobe Pulse Width
40
ns
tORS
RDYIN Setup Time to STSTB
-167
ns
tORH
RDYIN Hold Time after STSTB
217
ns
tOR
READY or RESET
to cf>2 Delay
192
ns
fMAX
Oscillator Frequency
2.0
TEST POINTS
0.8
20
ns
20
ns
326
ns
ley = 488.28 ns
cf>1 & cf>2 Loaded to
CL = 20 pF to 50 pF
Ready & Reset Loaded
to 2 mAl10 pF
All measurements
referenced to 1.5V
unless specified
otherwise.
MHz
A.C. TESTING LOAD CIRCUIT
2.4=X
.
>
.
ns
18.432
A.C. TESTING, INPUT,
OUTPUT WAVEFORM
0.45
129
-
Test Conditions
< )C
.
2.D
D.8
231464-3
231464-4
A.C. Testing: Inputs are driven at 2.4V for a logic "1" and 0.45V
for a logic "0". Timing measurements are made at 2.0V for a
logic "1" and O.BV for a logic "0" (unless otherwise noted).
CL Includes Jig Capacitance
13-53
•
8224
WAVEFORMS
.,
.2
_1'1~----~2----~
h(TTL) _ _ _ _ _~----+',
SYNC - - - - - ' "
(FRON 8080A)
1----------- ~SS f-----------I-
ROYIN OR RESIN
READY OUT
- - --- - - - - - - - - - - - - -- - - ...i - - - -...r-----------:---
--------------------~
RESET OUT
231464-S
VOLTAGE MEASUREMENT POINTS: .,." 2 Logic "0" = 1.0V, Logic "1" = B.OV. All other Signals measured at 1.SV.
CLOCK HIGH AND LOW TIME (USING X1, X2)
18NHz
~
.."",.
'*
Xl
elK
X2
iR2
-
231464-6
13·54
8228
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU
Chip System Control for
• Single
MCS®-80 Systems
Built-In Bidirectional Bus Driver for
• Data
Bus Isolation
the Use of Multiple Byte
• Allows
Instructions (e.g. CALL) for Interrupt
Acknowledge
• Reduces System Package Count
User Selected Single Level Interrupt
• Vector
(RST 7)
in EXPRESS
• -Available
Standard Temperature Range
in 28-Lead Cerdip and Plastic
• Available
Packages
(See Packaging Spec, Order #231369)
The Intel® 8228 is a single chip system controller and bus driver for MCS®-80. It generates all signals required
to directly interface MCS-80 family RAM, ROM, and I/O components.
A bidirectional bus driver is included to provide high system TIL fan-out. It also provides isolation of the 8080
. data bus from memory and I/O. This allows for the optimization of control signals, enabling the systems
designer to use slower memory and I/O. The isolation of the bus driver also provides for enhanced system
noise immunity.
A user selected Single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small
system requirements. The 8228 also generates the correct control Signals to allow the use of multiple byte
instructions (e.g" CALL) in response to an interrupt acknowledge by the 8080A. This feature permits large,
interrupt driven systems to have an unlimited number of interrupt levels.
•
The 8228 is designed to support a wide variety of system bus structures and also reduce system package
count for cost effective, reliable design of MCS-80 systems.
NOTE:
The specifications for the 3228 are identical with those for the 8228.
00
-+
0,-
-+
-+
D. -+
es-+
0, -+
0.,-+
0,
CPU
DATA
BUS
D,
231465-2
STSTB~~----------------~
DBIN ~~------------------------I
WR~~------------------------q
HLDA ~~-------------------------f
231465-1
07-00
Data Bus (8080 Side)
INTA
Interrupt Acknowledge
087·080
Data Bus (System Side)
HLOA
HLDA (from B060)
IIOR
111YVV
Im.lR
!lOAead
I/OWnle
WR
WR (from B080)
IlUSrn Bus Enable Input
MernoryAead
S'IllTS
lm!W
Memory Write
Vee
+5V
CBIN
CBIN (from 6080)
GND
o Volts
Status Strobe (from 8224)
Figure 2. Pin Configuration
Figure 1. Block Diagram
13-55
November 1992
Order Number: 231465-002
infel .
8228
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ O·C to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 70·C
• WARNING: Stressing the device beyond the "Absolute
.Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 150·C
Supply Voltage, Vee ............... - 0.5V to + 7V
Input Voltage ...................... -1.5 to + 7V
Storage Temperature .......... - 65·C to
Output Current .......................... 100 rnA
D.C. CHARACTERISTICS
+ 70·C, Vee =
Parameter
Symbol
Ve
Input Clamp Voltage,
All Input
IF
Input Load Current
IR
TA = O·C to
5V
Min Typ(1)
0.75
STSTB
Power Supply Current
VOL
VOH
Output Low Voltage
Output High Voltage
V
500
/LA
Vee = 5.25V
VF = 0.45V
750
/LA
/LA
All Other Inputs
250
/LA
100
/LA
20
/LA
100
/LA
2.0
V
0.8
140
190
Vee = 4.75V; Ie = -5 rnA
Vee = 5.25V
VR = 5.25V
Vee = 5V
rnA Vee = 5.25V
00- 0 7
0.45
V
All Other Outputs
0.45
V
10L = 10 rnA
V
Vee = 4.75V; 10H = -10/LA
V
10H = -1 rnA
00-0 7
3.6
3.8
All Other Outputs 2.4
los
Short Circuit Current, All Outputs
10 (off)
Off State Output Current
All Control Outputs
liNT
Test Conditi9ns
-1.0
250
All Other Inputs
lee
Unit
00,01,04,
05&07
OBo-OB7
Input Threshold
Voltage, All Inputs
Max
02&06
Input Leakage Current STSTB
VTH
± 5%
Limits
15
INTA Current
NOTE:
1. Typical values are for TA = 25·e and nominal supply voltages.
Vee = 4.75V; 10L = 2 rnA
90
rnA Vee = 5V
100
/LA
Vee =5.25V; Vo = 5.25V
-100
/LA
Vo = 0.45V
5
rnA (See INTA Test Circuit)
intel~
8228
CAPACITANCE VSIAS = 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz
1. This parameter is periodically sampled and not 100% tested.
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Control Signals
I/O
I/O Capacitance
(0 or DB)
A.C. CHARACTERISTICS
TA = O°Cto
Symbol
Limits
Typ(1)
Min
Max
12
8
7
8
+ 70°C, Vee
Unit
pF
15
pF
15
pF
= 5V ±5%
Limits
Parameter
Min
22
tpw
Width of Status Strobe
tss
Setup Time, Status Inputs 00-07
tSH
toe
tRR
Hold Time, Status Inputs 00-07
Delay from STSTB to any Control Signal
Delay from DBIN to Control Outputs
tRE
Delay from DBIN to Enable/Disable 8080 Bus
tRO
tWR
Delay from System Bus to 8080 Bus during Read
Delay from WR to Control Outputs
Max
ns
60
30
ns
ns
CL = 100 pF
CL = 100 pF
45
30
ns
CL = 25 pF
CL = 25 pF
CL=100pF
5
45
ns
ns
5
30
40
ns
ns
CL = 100 pF
CL = 100 pF
CL - 100 pF
tWE
Delay to Enable System Bus DBa-DB7 after STSTB
two
Delay from 8080 Bus 00-07 to System Bus
DBo-DB7 during Write
tE
Delay from System Bus Enable to System Bus DBo-DB7
30
ns
tHO
tos
HLDA to Read Status Outputs
Setup Time, System Bus Inputs to HLDA
Hold Time, System Bus Inputs to HLDA
25
ns
tOH
A.C. TESTING LOAD CIRCUIT
Conditions
ns
ns
8
5
20
Unit
10
ns
ns
20
CL = 100 pF
INTA Test Circuit (for RST 7)
+12V
8228
231465-3
For Do-D7; Rl = 4 Kn, R2 = oon, CL = 25 pF.
For all other outputs: Rl = 500n, R2 = 1 Kn, CL
=
23
100 pF.
INTA
P-------'
231465-4
13-57
•
8228
WAVEFORMS
T,
., ---...I
~===o.
STATUS STROBE
_ _ _ _ _ _~-~W~r--------------~----------~
8080 DATA BUS
\
OBIH
\
HLDA
iNTA.iOR.~
DURING HlDA
\
8080 BUS DURING READ
~ .. s -I--~H...:;k___----------------------
-------------- -- ------ -=:i-=.. t:.
------------- ---:~~ ~
1::::·1'i;""-------------------------------------------\
twR
iOW
--I
.....
r
- tw; t=
SYSTEIi! BUS OUTPUTS
J
::::::::::::::: ::==f. . --I._ _ _ __
SYSTENBUSDURINGWRITE - - - - - - - - - - - - - - -
SYSTEt.4 BUS ENABLE
.r\
OR NEt.lW
8080 BUS DURING WRITE
_ _ _ _ _ _ _ _ _ _ ____
I
____________________
SYSTEN BUS DURING READ
~Ir-~_D
.
)K
)'~r
--~-----------------~-~- .. :
.
f~----------------------231465-5
VOLTAGE MEASUREMENT POINTS: 00-07 (when outputs) Logic "0" = O.BV, Logic "1" =
sured at 1.5V.
13-58
a.ov. All other signals mea-
8755A
16,384-BIT EPROM WITH I/O
•
•
•
•
•
•
•
•
•
•
2048 Words x 8 Bits
Single
+ 5V Power Supply (Vee)
Directly Compatible with 8085AH
U. V. Erasable and Electrically
Reprogrammable
Internal Address Latch
2 General Purpose 8-Bit 1/0 Ports
Each 1/0 Port Line Individually
Programmable as Input or Output
Multiplexed Address and Data Bus.
40-Pin DIP
Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
The Intel 8755A is an erasable and electrically reprogram mabie ROM (EPROM) and 1/0 chip to be used in the
8085AH microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum
access time of 450 ns to permit use with no wait states in an 8085AH CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line
is individually programmable as input or output.
CLK
READY
ADo-7
AS-tO
CE2
2K.8
EPROM
101M
ALE
RD
lOW
RESET
G
G
lOR
PROG/CE t
Voo,--_...J
~VeC(+5VI
vss
10V)
231735-1
Figure 1. Block Diagram
PROG ANDCE,
vee
CE 2
PB 7
CLK
PB 6
RESET
PBs
Voo
PB 4
READY
PB 3
101M
PB 2
lOR
PB,
AD
PB o
lOW
PA 7
ALE
PA 6
ADo
PA5
AD,
PA 4
AD2
PA 3
AD3
PA 2
AD4
PAl
ADs
PA o
AD6
A,o
AD7
Ag
Vss
As
231735-2
Figure 2. Pin Configuration
13·59
November 1986
Order Number: 231735-002
II
8755A
Table 1. Pin Description
Symbol
Type
Name and Function
I
AD!!.RESS LATCH ENABLE: When Address latch Enable goes high, ADO-I!..
101M, AS-l0, ~ and CEl enter the address latches. The signals, (AD, 101M,
ADS-l0, CE2, CE1) are latched in at the trailing edge of ALE.
ADO-7
I
BIDIRECTIONAL ADDRESSIDATA BUS: The lower 8 bits of the PROM or 1/0
address are applied to the bus lines when ALE is high .
Du~ an 1/0 cycle, Port A or B is selected based on the latched value of ADo.
IF RD or lOR is low when the latched Chip Enables are active, the output
.buffers present data on the bus.
ADs-l0
I
ADDRESS BUS: These are the high order bits of the PROM address. They do
not affect 1/0 operations.
PROG/CEl
CE2
I
CHIP ENABLE INPUTS: CEl is active low and CE2 is active high. The 8755A
can be accessed only when both Chip Enables are active at the time the ALE
signal latches them up. If either Chip Enable input is not active, the ADo-7' and
READY ouputs will be in a high impedance state. CEl is also used as a
programming pin. (See section on programming.)
101M
I
1/0 MEMORY: If the latched 101M is high when RD is low, the output data
comes from an 1/0 port. If it is low the output data comes from the PROM.
RD
I
READ: If the latched Chip Enables are active when RD goes low, the ADo-7
output buffers are enabled and output either the selected PROM location or
1/0 port. When both RD and lOR are high, the ADo-7 output buffers are 3·
stated.
lOW
I
1/0 WRITE: If the latched Chip Enables are active, a low on lOW causes the
output port pointed to bt,!he latched value of ADo to be written with the data on
ADo_7. The state of 101M is ignored.
ClK
I
CLOCK: The ClK is used to force the READY into its high impedance state
after it has been forced low by CEl low, CE2 high, and ALE high.
READY
0
READY is a 3·state output controlled by CE1, CE2, ALE and ClK. READY is
forced low when the Chip Enables are active during the time ALE is high, and
remains low until the rising edge of the next ClK. (See Figure 6c.)
PAO-7
1/0
PORT A: These are general purpose 1/0 pins. Their input/output direction is
determined by the contents of Data Direction Register (DDR). Port A~
selected for write operations when the Chip Enables are active and lOW is low
and a 0 was previously latched from ~ AD1.
Read Operation is selected by either lOR low and active Chip Enables and ADo
and ADl low, or 101M high, RD low, active Chip Enables, and ADo and ADl
low.
PBO-7
1/0
PORT B: The general purpose 1/0 port is identical to Port A except that it is
selected by a 1 latched from ADo and a 0 from AD1.
RESET
I
RESET: In normal operation, an input high on RESET causes all pins in Ports A
and B to assume input mode (clear DDR register).
lOR
I
I/O READ: When the Chip Enables are active, a low on lOR will output the
selected 1/0 port o.!]!o the AD bus. lOR low performs the same function as the
combination of 101M high and RD low. When lOR is not used in a system, lOR
should be tied to Vee ("1 ").
ALE
.
+ 5V supply.
Vee
POWER:
Vss
GROUND: Reference.
Voo
POWER SUPPLY: Voo is a programming voltage, and must be tied to Vee
when the 8755A is being read.
For programming, a high voltage is supplied with Voo = 25V, typical. (See
section on programming.)
13·60
int"eL
8755A
A port can be read out when the latched Chip Enables are active and either RD goes low with 10/M
high, or lOR goes low. 80th input and output mode
bits of a selected port will appear on lines ADo_7.
FUNCTIONAL DESCRIPTION
PROM Section
The 8755A contains an 8-bit address latch which
allows it to interface directly to MCS®-48 and
MCS®-85 processors without additional hardware.
To clarify the function of the I/O Ports and Data Direction Registers, the following diagram shows the
configuration of one bit of PORT A and DDR A. The
same logic applies to PORT 8 and DDR 8.
The PROM section of the chip is addressed by the
11-bit address and the Chip Enables. The address,
CEl and CE2 are latched into the address latches on
the falling edge of ALE. If the latched Chip Enables
are active and 10/M is low when RD goes low, the
contents of the PROM location addressed by the
latched address are put out on the ADO-7 lines (provided that Voo is tied to Vee).
8755A ONE BIT OF PORT A AND DDR A
I/O Section
""~
The I/O section of the chip is addressed by the
latched value of ADo-l. Two 8-bit Data Direction
Registers (DDR) in 8755A determine the input/output status of each pin in the corresponding ports. A
"0" in a particular bit position of a DDR signifies that
the corresponding I/O port bit is in the input mode. A
"1" in a particular bit position signifies that the corresponding I/O port bit is in the output mode. In this
manner the I/O ports of the 8755A are bit-by-bit programmable as inputs or outputs. The table summarizes port and DDR designation. DDR's cannot be
read.
AD1 ADo
0
0
1
1
0
1
0
1
;
RESET
o.
231735-3
WRITE PA = (lOW = 0) • (CHIP ENABLES ACTIVE) • (PORT A
ADDRESS SELECTED)
WRITE DDR A = (lOW = 0) • (CHIP ENABLES ACTIVE) • (DDR
A ADDRESS SELECTED)
READ PA = {(101M = 1) • (RD = 0) + (lOR = O)} • (CHIP
ENABLES ACTIVE) • (PORT A ADDRESS SELECTED)
NOTE:
Write PA is not qualified by 101M.
Selection
PortA
Port 8
Port A Data Direction Register (DDR A)
Port 8 Data Direction Register (DDR 8)
When lOW goes ·Iow and the Chip Enables are active, the data on the ADo-7 is written into I/O port
selected by the latched value of ADo-l. During this
operation all I/O bits of the selected 'port are affected, regardless of their I/O mode and the state of 10/
M. The actual output level does not change until
lOW returns high. (Glitch free output.)
Note that hardware RESET or Vo'riting a zero to the
DDR latch will cause the output latch's output buffer
to be disabled, preventing the data in the Output
Latch from being passed through to the pin. This is
equivalent to putting the port in the input mode. Note
also that the data can be written to the Output Latch
even though the Output 8uffer has been disabled.
This enables a port to be initialized with'a value prior
to enabling the output.
The diagram also shows that the contents of PORT
A and PORT 8 can be read even when the ports are
configured as outputs.
13-61
•
intel..
8755A
ERASURE CHARACTERISTICS
SYSTEM APPLICATIONS
The erasure characteristics of the 8755A are such
that erasure begins to occur when exposed to light
with wavelengths shorter than approximately 4000
Angstroms (.1\). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000A range. Data show that constant
exposure to room level fluorescent lighting could
erase the typical 8755A in approximately 3 years
while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the
8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labelsare available from Intel which should be placed
over the 8755A window to prevent unintentional erasure.
System Interface ¥11th 8085AH
A system using the 8755A can use either one of the
two 110 Interface tephniques:
• Standard I/O .
• Memory Mapped 110
If a standard 110 technique is used, the system can
use the feat!Jre of. both CE2 and CE"1. By using a
combination of unused address lines A11-15 and the
Chip Enable inputs, the 808?AH system can use up
to 5· 875M's without requiring a· CE decoder: See
Figure 4; . ,
..
.
The recommended erasure procedure for the 8755A
is exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.Wlcm2
power rating. The 8755A should be placed within
one inch from the lamp tubes during erasure. Some
lamps have a filter on their tubes and this filter
should be removed before .erasure.
If a memory mapped 110 approach is used the
8755A will be selected by the combination of both
the Chip Enables and !O/M using APS-15 address
lines. See. Figure 3.
.
r-----:
A
j.
"--,,
;.
8085AH
;
Ao".7
y
~lE
r-r-r--
jftj
. \VII
PROGRAMMING
elK 1.21
foo-
READY
Initially, and after each erasure, all bits of the
EPROM portions of the 8755A are in the "1" state.
Information is introduced by selectively programming "0" into the desired bit locations. A programmed "0" can only be changed to a "1" by UV
erasure.
r--
IDiM
v
'---,
l"'
iiiii
i
f0o~/D"J
,
l
7
A1-1.
,1Iii elK lolii
in READY fi
ALE
B755A
..
The 8755A can be programmed on the Intel Universal Programmer (iUP), and iUPF8744A programming
module.
231735-4
Figure 3. 8755A In 8085AH System
(Memory-Mapped 110)
The program mode itself consists of programming a
single address at a time, giving a single 50 msec
pulse for every address. Generally, it is desirable to
have a verify cycle after a program cycle for' the
same address as shown in the attached timing diagram. In the verify cycle (I.e., normal memory
read cycle) 'Voo' should be at + 5V.
13-62
_.
l
:=t>
",-"
An
An
."
AU
V
AIS
"'II
..
IE
c
CD
~.
CD
.....
U1
U1
~
....AH
ALE
iffi
WR
eLK 1.21
S·
READY
CD
101M
0
~
~
r-
r-
t-
-
t-
t-
r-
-
r-
r-
t-
t-
t-
-
rr-
r-
-
t-
-
1--
f-
-
t-
t-
-
r-
r-
CD
U1
-
CI)
......
m :J:~
t.)
t.)
-..
C1I
C1I
»
Ul
'<
III
CD
3
en
r\
~
Q.
I»
Q.
::::
.9
7
AID._r
I»
1m.
~
7
t\
'II . .
.~" ALERDmwmREADY'DIMEEl
iiiii
,
'II
~, .~.. AURDi!ieLKREADY'D/IIIeE,
t\...
iloR
v"
~,
f
'II' . .
.~.. AURDfimRUDY'DliitEt
lOR
1
7~
~, .~..
.,
'II' . . .,
'0/111tE,
ALEiiiiRJiiellRUDY
iiiR
7
.~..
'I
'0';;Cl ,
A.U'0ili'elKREADY
875SA
8755A
875SA
87S5A
8155A
12K BYTESI
12K BYTESI
12K BYTESI
12K BYTESI
12K BYTESI
231735-6
NOTE:
Use GEl for the first 8755A in the system, and GE2 for the other 8755A's. Permits up to 5-8755A's in a system without GE decoder.
iii
int'eL
8755A
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 70°C
+ 150°C
Temperature Under Bias ............ O°C to
Storage Temperature .......... - 65°C to
Voltage on any Pin
with Respect to Ground .......... - 0.5V to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7V
Power Dissipation .......................... 1.5W
D.C. CHARACTERISTICS
= O°C to 70°C, Vee = Voo =
TA
Symbol
5V ±5%
Min
Max
Unit
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IlL
Input Leakage
ILO
Output Leakage Current
lee
Vee Supply Current
100
VIL
Parameter
+ 0.5
Vee
Test Conditions
= 5.0V
Vee = 5.0V
IOL = 2 mA
IOH = -400 p.A
Vee
V
0.45
V
10
p.A
Vss ~ VIN ~ Vee
±10
p.A
0.45V ~ VOUT ~ Vee
180
mA
Voo Supply Current
30
mA
Voo
CIN
Capacitance of Input Buffer
10
pF
fe
ClIO
Capacitance of 1/0 Buffer
15
pF
fe
V
2.4
D.C. CHARACTERISTICS-PROGRAMMING
= O°C to 70°C, Vee = 5V ±5%, Vss = OV, Voo = 25V
TA
=
=
=
Vee
1 p.Hz
1 p.Hz
±1V
Parameter
Min
Typ
VOD
Programming Voltage (during Write to EPROM)
24
25
26
V
IOD
Prog Supply Current
15
30
mA
Symbol
13-64
Max
Unit
intel·
8755A
A.C. CHARACTERISTICS
TA = O°C to 70°C, Vee = 5V ±5%
Symbol
8755A
Parameter
Min
Max
Unit
teye
Clock Cycle Time
320
ns
T1
ClK Pulse Width
.80
ns
T2
ClK Pulse Width
120
tf, tr
ClK Rise and Fall Time
tAL
Address to latch Set Up Time
tLA
tlC
tRD
Valid Data Out Delay from READ Control'
ns
30
ns
50
ns
Address Hold Time after latch
80
ns
latch to READ/WRITE Control
100
tAD
Address Stable to Data Out Valid""
tll
latch Enable Width
ns
170
ns
450
ns
100
ns
tRDF
Data Bus Float after READ
0
tCl
READ/WRITE Control to latch Enable
20
ns
tce
READ/WRITE Control Width
250
ns
tow
Data in Write Set Up Time
150
ns
two
Data in Hold Time after WRITE
30
twp
WRITE to Port Output
tpR
Port Input Set Up Time
50
tRP
Port Input Hold Time to Control
50
tRYH
READY HOLD Time to Control
0
tARY
ADDRESS (CE) to READY
tRV
Recovery Time between Controls
300
ns
tRDE
READ Control to Data Bus Enable
10
ns
100
ns
ns
400
ns
ns
ns
160
ns
160
ns
NOTES:
CLOAD = 150 pF.
'Or TAD - (TAL + T Lcl. whichever is greater.
•• Defines ALE to Data Out Valid in conjunction with TAL.
A.C. CHARACTERISTICS-PROGRAMMING
= O°C to 70°C. Vce = 5V ±5%. VSS = OV, VDD = 25V
TA
Symbol
±1V
Parameter
Min
tps
Data Setup Time
10
tpD
Data Hold Time
0
ns
ts
Prog Pulse Setup Time
2
/Jos
tH
Prog Pulse Hold Time
2
tpR
Prog Pulse Rise Time
0.01
2
tpF
Prog Pulse Fall Time
0.01
2
/Jos
tpRG
Prog Pulse Width
45
50
ms
13-65
Typ
Max
Unit
ns
/Jos
/Jos
II
intel.
8755A
A.C. TESTING INPUT, OUTPUT WAVEFORM
"=X >
2.0
< )C
DEVICE
UNDER
2.0
TEST POINTS
0.45
A.C. TESTING LOAD CIRCUIT
0.'
.
TEST
'1CL.150PF
0.8
231735-7
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing Measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
CL=150pF
CL Includes Jig Capacitance
231735-8
WAVEFORMS
CLOCK SPECIFICATION FOR 8755A
231735-9
PROM READ, I/O READ AND WRITE
Aa·1Q
10f"
~
ADDRESS
l(
ADDRESS
'AD
ALE
~
ADDRESS
eE,
~----<
DATA
'LL-
ADDRESS
>-
rI
-'AC~
(PROGI/CE l
)---~D
I---'LA-
ViI II/, 'II
\
\.
-
f---tRDf.
-
\
tADF
I--
~
r-twD
I\...-
J
-'LC-
IDW-
-'Ru
f\..-
lOW
1------.---- 'cc - - - - r---'CL~
IRV
231735-10
Please note that eEl must remain low for the entIre cycle.
13·66
infel~
8755A
WAVEFORMS (Continued)
1/0 PORT
~OR
'\LF-____________J~
t ____________
u.f '"
f- + '..
~]K~~_-_-_-__
-
~
PO'NpRUTT - - - - .
~~:AO-
-
-- -
-
--y
--------"--------------------
231735-11
A. Input Mode
\
!
----------'::~XO"""'
GLITCH FREE
PORT
OUTPUT
------------
DATA O
-
BUS
____ _
-
-
-
-
' "
- "_ _ _ _ _ _ _J
X\,._______
231735-12
B. Output Mode
WAIT STATE (READY
=
0)
elK
ALE
231735-13
13-67
•
8755A
WAVEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION
11. . . . . . . . . . .- - - - - -
PROGRAM CYCLE - - - - - -...._*I.o-----VERIFY CYCLE'
------1_
PROGRAM CYCLE
ALE
DATA TO BE
PROGRAMMED
A/DO·7
IpO
A8·10
eEZ
IpS
+25
Voo
+5-------------------------(
\J-231735-14
'Verify cycle is a regular Memory Read Cycle (with VDD =
+ 5V for 8755A).
13-68
MCS®--96 Architectural
Overview and Quick
References
14
III
infel·
September 1992
MCS®-96 Architectural Overview
Order Number: 272109-002
14-1
MCS-96 Architectural Overview
CONTENTS
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .................... 14-3
5.0 aXC196KB PERIPHERALS ......... 14-7
2.0 THE CPU ........................... 14-4
6.0 aXC196KC/KD PERiPHERALS ..... 14-9
3.0 THE ARCHITECTURE .............. 14-5
7.0 aXC196KR/KT PERIPHERALS . ... 14-10
3.1 Addressing Modes ................ 14-5
a.o aXC196NT PERIPHERALS ........ 14-12
4.0 aX9X PERiPHERALS ............... 14-6
9.0 aXC196MC PERiPHERALS ........ 14-13
14-2
int:el.,
1.0
MCS-96 ARCHITECTURAL OVERVIEW
components have enhancements to provide higher performance with lower power consumption. To further
decrease power usage, idle and power-down modes are
available on these devices. These microcontrollers contain dedicated I/O subsystems and perform 16-bit
arithmetic instructions including multiply and divide
operations.
INTRODUCTION
The MCS-96 family members are all high performance
microcontrollers with a 16-bit CPU and at least 230
bytes of on-chip RAM. The Intel MCS-96 family easily
handles high speed calculations and fast input/output
(I/O) operations. Typical applications include closedloop control and mid-range digital signal processing.
Modems, motor control system, printers, engine control system, photocopiers, anti-lock brakes, air conditioner control systems, disk drives and medical instrumentation all use MCS-96 products.
This overview briefly describes the MCS-96 instruction
set and architecture and provides descriptions for the
8X9X, 80C196KB, 80C196KC and 80C196KR key
features. Comprehensive user's guides that contain
more information about these devices are available.
Figure 1.1 shows a block diagram of the MCS-96 architecture.
All of the MCS-96 components share a common instruction set and architecture. However, the CHMOS
XTAL1
XTAL2
~-. .------~.
CONTROL SIGNALS
L:':':':':::::''':::::::'J4I--II--,r---t+ ADDR/DATA BUS
•
VREF
ANGND
O-/N...,..,.ltlCD
8c::;g;;ee
I- a:::
(IJ
(I)
V)
S:~~~1i:1i:1i:
~~~~~~~
'-r-'
(I)
~
KR Only
KR
272109-1
Figure 1.1. MCS-96 Block Diagram
14-3
intet
MCS-96 ARCHITECTURAL OVERVIEW
Calculations perforIIled by the CPU take place in the
RALU. The RALU shown in Figure 2.1 contains a
17-bit ALU, the Program Status Word (PSW), the Program Counter (PC), a loop counter and three temporary registers. The RALU operates directly on the Register File, thus eliminating accumulator bottleneck and
providing for direct control of I/O operations through
the SFRs.
2.0 THE CPU
The major components of the MCS-96 CPU are the
Register File and the Register/Arithmetic Logic Unit
(RALU). Locations OOH through 17H are the I/O control registers or Special Function Registers (SFRs). Locations ISH and 19H contain the stack pointer, which
can serve as general purpose RAM when not performing stack operations. The remaining bytes of the register file serve as general purpose RAM, accessible as
bytes, words or double-words.
---------------~------~--------.r------------------Memory Controller
Memory
BUB
CPU
r---~
Register
File
Register
RAM
16
CPU BUSES
272109-2
Figure 2.1 Block Diagram of the Register File, RALU, Memory Controller and Interrupt Controller
14-4
intet
MCS-96 ARCHITECTURAL OVERVIEW
Long and double-word operations include shifts, normlize, multiply and divide. The divide instruction functions as a 32-bit by l6-bit divide that generates a 16-bit
quotient and 16-bit remainder. The word multiply operates as a l6-bit by l6-bit multiply with a 32-bit result.
Both operations can function in either the signed or
unsigned mode. The normalize instruction and sticky
bit flag provide hardware support for the software
floating point package (FPAL-96).
3.0 THE ARCHITECTURE
The MCS-96 supports a complete instruction set which
includes bit operations, byte operations, word operations, double-word operations (unsigned 32-bit), long
operations (signed 32-bit), flag manipulations as well as
jump and call instructions. All the standard logicai and
arithmetic instructions function as both byte and word
operations. The Jump Bit Set and Jump Bit Clear instructions can operate on any of the SFRs or bytes in
the lower register file. These fast bit manipulations ale
low for rapid I/O functions.
3.1 Addressing Modes
The MCS-96 instruction set supports the following addressing modes: register-direct, indirect, indirect with
auto-increment, immediate, short-indexed and long-indexed. These modes increase the flexibility and overall
execution speed of the MCS-96 devices. Each instruction uses at least one of the addressing modes. These
modes and formats are shown in Figure 3.1.
Byte and word operations make-up most of the instruction set. The assembly language ASM-96 uses a "B"
suffix on a mnemonic for a byte operation, otherwise
the mnemonic refers to a word operation. One, two or
three operand forms exist for many of the instructions.
Mnem
Mnem
Mnem
Dest or Srcl
Dest, Srcl
Dest, Srcl, Src2
tOne operand direct
;Two operand direct
;Three operand direct
Mnem
Mnem
Mnem
#Srcl
Dest, #Srcl
Dest, Srcl, #Src2
tOne operand immediate
;Two operand immediate
;Three operand immediate
Mnem
Mnem
Mnem
Mnem
Mnem
Mnem
[addr]
[addr]
Dest, [addr]
Dest, [addr] +
Dest, Srcl, [addr]
Dest, Srcl, [addr] +
tOne operand indirect
tOne operand indirect auto-increment
;Two operand indirect
;Two operand indirect auto-increment
;Three operand indirect
;Three operand indirect auto-increment
Mnem
Mnem
Dest, offs[addr]
Dest, ~rcl, offs[addr]
;Two operand indexed (short or long)
;Three operand indexed (short or long)
+
Where:
Mnem
instruction mnemonic
destination register
Dest
Srcl, Src2
source registers
addr
word register used in computing the address of an operand
offs
offset used in computing the address of an operand
=
=
=
=
=
Figure 3.1 Instruction Format
14-5
II
intet
MCS-96 ARCHITECTURAL OVERVIEW
The register-direct and immediate addressing modes
execute faster than the other addressing modes. The
register-direct addressing mode provides access to the
addresses in the register file and the SFRs. The indexed
modes provide for direct access to the remainder of the
64K address space. Immediate addressing uses the data
following the opcode as the operand.
The multiple addressing modes of the MCS-96 make it
easy to program in assembly language and provide an
excellent interface to high-level languages. The instructions accepted by the assembler consist of mnemonics
followed by either addresses or data .. Refer to the.Quick
Reference section for Instruction Summary tables for
each device. The MCS-96 Macro Assembler Users
Guide contains additional ASM96 information.
Both of the indirect addressing modes use the value in a
word register as the address of the operand. The indirect auto-increment mode increments a word address
by one after a byte operation and two after a word
operation.· This addressing mode provides easy access
into look-up tables.
4.0
8X9X PERIPHERALS
Standard I/O Ports-The 8X9X has five 8-bit I/O
ports. Port 0 is an input port that is also the anlog input
for the A/D converter. Port 1 is a quasi-bidirectional
port. Port 2 contains three types of port lines: quasi-bidirectional, input and output. Other functions on the
8X9X share the input and output lines with Port 2.
Ports 3 and 4 are open-drain bidirectional ports that
share their pins with the address/data bus.
The long-indexed addressing mode provides direct access to any of the locations in the 64K address space.
This mode forms the address of the operand by adding
a 16-bit 2's complement value to the contents of a word
register. Indexing with the zero register allows "direct"
addressing to any location. The short-indexed addressing mode forms the address of the operand by adding
an 8-bit 2's complement value to the contents of a word
register.
Timers-The 8X9X has two 16,bit timers, Timer! and
Timer2. An internal clock increments the Timer! value
every 8 state times. (A state time is 3 oscillator periods.)
An external clock increments Timer2 on every positive
and negative transition. Either an internal or external
source can reset Timer2. Timer! and Timer2 can generate an interrupt when crossing the OFFFFH/OOOOH
boundary. The 8X9X also includes separate, dedicated
timers for the Serial Port baud rate generator and
Watchdog Timer. The Watchdog Timer is an internal
timer that resets the system if the software fails to operate properly.
The 8XC196NT has 9 new instructions which have
been implemented to support addressing the extended
1 Mbyte address space of the 8XC196NT family. Four
extended load and store instructions using indirect, indirect auto increment, or extended indexed addressing,
can be used to address the 1 Mbyte address space.
Three instructions are for extended calls, branches, and
jumps. An extended version of the interruptible and
non-interruptible block moves have also been implemented.
Table 1. MCS-96 Family Devices
Product
Timers
HSIO
IEPA
AID
CHS
Serial
Port
Synch.
Serial
Port
PWMS
PTS
8098
2
HSIO
4
YES
1
8097BH
2
HSIO
8
YES
1
8097JF
2
HSIO
8
YES
1
80C198
2
HSIO
4
YES
1
80C196KB
2
HSIO
8
YES
1
80C196KC
2
HSIO
8
YES
3
YES
80C196KD
2
HSIO
8
YES
3
YES
80C196KR
2
EPA
8
YES
80C196KT
2
EPA
8
YES
80C196NT
2
EPA
4
YES
2
EPA
13
YES
80C196MC
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
14-6
Slave
Port
3-Phase
Waveform
Generator
YES
infel~
MCS-96 ARCHITECTURAL OVERVIEW
High Speed Input Unit (HSI)-The 8X9X HSI unit
can record times of external events with a 9 state time
resolution. It can monitor four independently configurable HSI lines and capture the value of Timerl when
an event(s) takes place. The four types of events that
can trigger captures include: rising edges only, falling
edges only, rising or falling edges, or every eighth rising
edge. The HSI unit can store up to 8 entries (Timerl
values). Reading the HSI holding register unloads the
earliest entry placed in the FIFO. The HSI unit can
generate an interrupt when loading an entry into the
HSI holding register or loading the sixth entry into the
FIFO.
Pulse Width Modulator (PWM)-The PWM output
waveform is a variable duty cycle pulse that repeats
every 256 state times. The Pulse Width Modulator of
the 8X9X can provide useful signals for a· variety of
applications. The PWM output can perform digital to
analog conversions and drive several types of motors
that require a PWM waveform for more efficient operation.
A/D Converter-The 8X9X A/D Converter converts
an analog input to a 10-bit digital equivalent. The main
components of the A/D Converter are: 8 analog inputs,
an 8 to 1 multiplexer, a sample and hold capacitor and
the resistor ladder. The A/D Quick Reference section
defines the A/D terms. The A/D Converter can start a
conversion immediately or the High Speed Output unit
can trigger a conversion at a preprogrammed time. The
AID Converter performs a conversion in 88 state
times. Upon completion of each conversion the converter can generate a conversion complete interrupt.
The 8X9X provides separate VREF and ANGND supply pins to isolate noise on the Vee or Vss lines.
High Speed Output Unit (HSO)-The 8X9X HSO unit
can trigger events at specified times based on Timer I or
Timer2. These programmable events include: starting
an A/D conversion, resetting Timer2, generating up to
four software time delays, and setting or clearing one or
more of the 6 HSO output lines. The HSO unit stores
pending events and the specified times in a Content
Addressable Memory (CAM) file. This file stores up to
eight commands. Each command specifies the action
time, the nature of the action, whether an interrupt is to
occur, and whether Timerl or Timer2 is the reference
timer. Every 8 state times the HSO compares the CAM
locations for time matches. The HSO unit triggers the
specified event when it finds a time match. A command
is cleared from the CAM as soon as it executes.
Interrupts-There are 21 interrupt sources and 8 interrupt vectors on the 8X9X. When the interrupt controller detects one of the 8 interrupts it sets the
corresponding bit in the interrupt pending register. Individual interrupts are enabled or disabled by setting or
clearing bits in the interrupt mask register. When the
interrupt controller decides to process an interrupt, it
executes a "call" to an Interrupt Service Routine (ISR).
The corresponding interrupt vector contains the address of the ISR. The interrupt controller then clears
the associated pending bit.
The Serial Port-The Serial Port on the 8X9X has one
synchronous (Mode 0) and three asynchronous modes
(Modes I, 2 and 3). The asynchronous modes are full
duplex, meaning they can transmit and receive data
simultaneously. The receiver on the 8X9X is buffered
so the reception of a second byte may begin before the
first byte is read. The most common use of Mode 0, the
synchronous mode, is to expand the I/O capability of
the 8X9X using shift registers. Mode 1 is the standard
asynchronous mode used for normal serial communication. The data frame for Mode 1 consists of 10 bits: a
start bit, 8 data bits (LSB first) and a stop bit. If parity
is enabled (PEN = 1), an even parity bit is sent instead
of the 8th data bit. Modes 2 and 3 are 9-bit modes
commonly used for multiprocessor communications.
The data frame used in these modes consists of 11 bits:
a start bit, nine data bits (LSB first) and a stop bit.
Devices in Mode 2 will interrupt upon reception only if
the 9th data bit is set. Devices in Mode 3 will always
interrupt upon reception. Mode 3 also allows transmission of 8 data bits plus an even parity bit.
5.0
8XC196KB PERIPHERALS
Standard I/O Ports-The 8XC196KB has five 8-bit
I/O ports. Port 0 is an input port that is also the analog
input for the AID converter. Port I is a quasi-bidirectional port. Port 2 contains three types of port lines:
quasi-bidirectional, input and output. Other functions
on the 8XC196KB share the input and output lines
with Port 2. Ports 3 and 4 are open-drain bidirectional
ports that share their pins with the address/data bus.
14-7
•
intel~
MCS-96 ARCHITECTURAL OVERVIEW
Timers-The 8XCI96KB has two 16-bit timers, Timerland Timer2. An internal clock increments the
Timer! value every 8 state times. (A state time is 2
oscillator periods.) An external clock increments or
decrements Timer2 on every positive and negative transition. Either an internal or external source can reset
Timer2. Timer! can generate an interrupt when crossing the OFFFFH/OOOOH boundary. Timer2 can generate an interrupt when crossing the OFFFFH/OOOOH
boundary or the 7FFFH/8000H boundary. The
8XCI96KB also includes separate, dedicated timers for
the baud rate generator and Watchdog Timer. The
Watchdog Timer is an internal timer that resets the
system if the software fails to operate properly.
The Serial Port-The Serial Port on the 8XCl96KB
has one synchronous (Mode 0) and three asynchronous
modes (Modes 1, 2 and 3). The asynchronous modes
are full duplex, meaning they can transmit and receive
data simultaneously. The receiver on the 8XC196KB is
buffered so the reception of a second byte may begin
before the first byte is read. The transmitter is also double buffered and can generate continual transmissions.
The most common use of Mode 0, the synchronous
mode, is to expand the 1/0 capability of the
8XC196KB using shift registers. Mode I is the standard asynchronous mode used for normal serial communication. The data frame for Mode I consists of 10
bits: a start bit, 8 data bits (LSB first) and a stop bit. If
parity is enabled (PEN = I), an even parity bit is sent
instead of the 8th data bit. Modes 2 and 3 are 9-bit
modes commonly used for multiprocessor communications. The data frame used in these modes consists of II
bits: a start bit, nine data bits(LSB first) and a stop bit.
Devices in Mode 2 will interrupt upon reception only if
the 9th data bit is set. Devices in Mode 3 will always
interrupt upon reception. Mode 3 also allows transmission of 8 data bits plus an even parity bit.
High Speed Input Unit (HSI)-The 8XCI96KB HSI
unit can record times of external events with a 9 state
time resolution. It can monitor four independently configurable HSI lines and capture the value of Timer!
when an event(s) takes place. The four types of events
that can trigger captures include: rising edges only, falling edges only, rising or falling edges, or every eighth
rising edge. The HSI unit can store up to 8 entries
(Timer! values), 7 in the 7-level FIFO and 1 in the HSI
holding register. Reading the'HSI holding register unloads the earliest entry placed in the FIFO. The HSI
unit can generate an interrupt when: loading an entry
into the HSI holding register, loading the fourth entry
into the FIFO or loading the sixth entry into the FIFO.
Pulse Width Modulator (PWM)-The Pulse Width
Modulator of the 8XCI96KB can provide useful signals for a variety of applications. The PWM output can
perform digital to analog conversions and drive several
types of motors that require a PWM waveform for
more efficient operaton. The PWM output waveform is
a variable duty cycle pulse that repeats every 256 state
times or 512 state times.
High Speed Output Unit (HSO)-The 8XCI96KB
HSO unit can trigger events at specified times based on
Timer! or Timer2. These programmable events include: starting an AID conversion, resetting Timer2,
generating up to four software time delays, and setting
or clearing one or more of the 6 HSO output lines. The
HSO unit stores pending events and the specified times
in a Content Addressable Memory (CAM) file. This file
stores up to eight commands. Each command specifies
the action time, the nature of the action, whether an
interrupt is to occur, and whether Timerl or Timer2 is
the reference timer. Every 8 state times the HSO compares the CAM locations for time matches. The HSO
unit triggers the specified event when it finds a time
match. A command can either clear from the CAM as
soon as it executes or remain in the CAM as a locked
CAM entry and continue to execute whenever its time
tag matches the reference timer. Locked entries are useful in applications requiring periodic or repetitive
events to occur such as multiple PWMs.
AID Converter-The 8XCI96KB AID Converter converts an analog input to a IO-bit digital equivalent. The
main components of the AID Converter are: 8 analog
inputs, an 8 to I multiplexer, a sample and hold capacitor and the resistor ladder. Refer to the data sheet for
all specifications on AID performance. The AID
Quick Reference section defines the AID terms. The
AID Converter can start a conversion immediately or
the High Speed Output unit can trigger a conversion at
a preprogrammed time. The AID Converter can perform a conversion in either 91 state times for low crystal frequencies and 158 state times for higher crystal
frequencies. Upon completion of each conversion the
converter generates a conversion complete interrupt.
The 8XCl96KB provides separate VREF and ANGND
supply pins to isolate noise on the Vee or V ss lines.
14-8
intel~
MCS-96 ARCHITECTURAL OVERVIEW
Interrupts-There are 28 interrupt sources and 16 interrupt vectors on the 8XCI96KB. Additionally, there
are 2 special interrupt vectors for Software Trap and
Unimplemented Opcodes. When the interrupt controller detects one of the 16 interrupts it sets the corresponding bit in one of two interrupt pending registers.
Individual interrupts are enabled or disabled by setting
or clearing bits in the interrupt mask registers. When
the interrupt controller decides to process an interrupt,
it executes a "call" to an Interrupt Service Routine
(ISR). The corresponding interrupt vector contains the
address of the ISR. The interrupt controller then clears
the associated pending bit.
6.0
nsmg edge. The HSI unit can store up to 8 entries
(Timer! values), 7 in the 7-level FIFO and 1 in the HSI
holding register. Reading the HSI holding register unloads the earliest entry placed in the FIFO. The HSI
unit can generate an interrupt when: loading an entry
into the HSI holding register, loading the fourth entry
into the FIFO or loading the sixth entry into the FIFO.
High Speed Output Unit (HSO)-The 8XC196KC/
KD HSO unit can trigger events at specified times
based on Timer! or Timer2. These programmable
events include: starting an A/D conversion, resetting
Timer2, generating up to four software timers, and setting or clearing one or more of the 6 HSO output lines.
The HSO unit stores pending events and the specified
times in a Content Addressable Memory (CAM) file.
This file stores up to eight commands. Each command
specifies the action time, the nature of the action,
whether an interrupt is to occur, and whether Timer!
or Timer2 is the reference timer. Every 8 state times the
HSO compares the CAM locations for time matches.
The HSO unit triggers the specified event when it finds
a time match. A command can either clear from the
CAM as soon as it executes or remain in the CAM as a
locked CAM entry and continue to execute whenever
its time tag matches the reference timer. Locked entries
are useful in applications requiring periodic or repetitive events to occur such as multiple PWMs.
8XC196KC and 8XC196KD
PERIPHERALS
Standard I/O Ports-The 8XCI96KC/KD has five
8-bit I/O ports. Port 0 is an input port that is also the
analog input for the A/D converter. Port I is a quasibidirectional port that shares pins with two PWM outputs. Port 2 contains three types of port lines: quasi-bidirectional, input and output. Other functions on the
8XCI96KC/KD share the input and output lines with
Port 2. Ports 3 and 4 are open-drain bidirectional ports
that share their pins with the address/data bus.
Timers-The 8XCI96KC/KD has two 16-bit timers,
Timer! and Timer2. An internal clock increments the
Timer! value every 8 state times. (A state time is 2
oscillator periods.) An internal clock or an external
clock can drive Timer2. When clocked internally Timer2 can increment every 1 or 8 state times. When
clocked externally Timer2 increments or decrements on
every positive and negative transition. Either an internal or external source can reset Timer2. Timer! can
generate an interrupt when crossing the OFFFFH/
OOOOH boundary. Timer2 can generate an interrupt
when crossing the OFFFFH/OOOOH boundary or the
7FFFH/8000H boundary. The 8XCI96KC/KD also
includes separate, dedicated timers for the baud rate
generator and Watchdog Timer. The Watchdog Timer
is an internal timer that resets the system if the software
fails to operate properly.
The Serial Port-The Serial Port on the 8XCI96KC/
KD has one synchronous (Mode 0) and three asynchronous modes (Modes I, 2 and 3). The asynchronous
modes are full duplex, meaning they can transmit and
receive data simultaneously. The receiver on the
8XCI96KC/KD is buffered so the reception of a second byte may begin before the first byte is read. The
transmitter is also double bufered and can generate
continual transmissions. The most common use of
Mode 0, the synchronous mode, is to expand the I/O
capability of the 8XCI96KC/KD using shift registers.
Mode 1 is the standard asynchronous mode used for
normal serial communication. The data frame for
Mode I consists of 10 bits: a start bit, 8 data bits (LSB
first) and a stop bit. If parity is enabled (PEN = I), an
even parity bit is sent instead of the 8th data bit. Modes
2 and 3 are 9-bit modes commonly used for multiprocessor communications. The data frame used in these
modes consists of II bits: a start bit, nine data bits (LSB
first) and a stop bit. Devices in Mode 2 will interrupt
upon reception only if the 9th data bit is set. Devices in
Mode 3 will always interrupt upon reception. Mode 3
also allows transmission of 8 data bits plus an even
parity bit.
High Speed Input Unit (HSI)-The 8XCI96KC/KD
HSI unit can record times of external events with a 9
state time resolution. It can monitor four independently
configurable HSI lines and capture the value of Timer!
when an event(s) takes place. The four types of events
that can trigger captures include: rising edges only, falling edges only, rising or falling edges, or every eighth
14-9
III
MCS-96 ARCHITECTURAL OVERVIEW
Pulse Width Modulator (PWM)-The 8CXI96KC/
KD has 3 PWM outputs. The output waveform is a
variable duty cycle pulse which is selectable to repeat
every 256 state times or 512 state times. Several types of
motors require a PWM waveform for most efficient operation. Additionally, filtering this waveform will produce a DC level that can change in 256 steps by varying
the duty cycle.
A/D Converter-The 8XCI96KC/KD A/D Converter converts an analog input to a digital equivalent. Resolution is either 8 or 10 bits with programmable sample
and convert times. The main components of the AID
Converter are: a sample and hold, an 8-channel multiplexer, and an 8-bit or 1O-bit successive approximation
analog-to-digital converter. Refer to the data sheet for
all specifications on A/D performance. The A/D
Quick Reference section defines the A/D terms. The
converter can start a conversion immediately or the
High Speed Output unit can trigger a conversion at a
preprogrammed time. Upon completion of each conversion the converter generates a conversion complete interrupt. The 8XCI96KC/KD provides separate VREF
and ANGND supply pins to isolate noise on the Vee
or Vss lines.
Interrupts-There are 28 interrupt sources and 16 interrupt vectors on the 8XCI96KC/KD. In addition
there are 2 special interrupt vectors (Software Trap and
Unimplemented Opcode) used in Intel development
tools or evaluation boards. When the interrupt controller detects one of the 16 interrupts it sets the corresponding bit in one of two interrupt pending registers.
Individual interrupts are enabled or disabled by setting
or clearing bits in the interrupt mask registers. When
the interrupt controller decides to process an interrupt,
it executes a "call" to an Interrupt Service Routine
(ISR). The corresponding interrupt vector contains the
address of the ISR. The interrupt controller then clears
the associated pending bit.
Peripheral Transaction Server (PTS)-The PTS is a
microcoded hardware interrupt processor. It responds
to interrupts with a fixed set of actions. These actions
consist of: transferring data, starting an AID conversion, reading the HSI FIFO and loading HSO events.
The PTS completes these tasks much faster than using
interrupt driven service routines. The PTS can service
all interrupts except NMI, Trap and Unimplemented
Opcode. Each interrupt managed by the PTS requires a
block of data called the PTS Control Block (PTSCB).
Each PTSCB requires 8 data bytes in register RAM.
The PTSCB determines: the type of PTS, the number of
PTS responses (if applicable), the source for data and
the destination (if applicable). PTS cycles have a higher
priority than interrupts and may temporarily suspend
interrupt. service routines.
7.0
8XC196KR and 8XC196KT
PERIPHERALS
Standard I/O Ports-The 8XCI96KRlKT has six
8-bit I/O ports. Each pin operates as a dedicated input
or output. Most pins also have an alternate function.
The KR/KT does not use the quasi-bidirectional port
pins found on previous MCS-96 devjces. As an input,
the pin is a true high impedance with no pull-ups or
pull-downs. Most ports (Ports I, 2, 5 and 6) have direction
registers
(Px_DIR),
mode
registers
(Px_MODE), data input registers (Px_PIN) and data
output registers (Px_REG). This allows the user to
configure each port pin as input, output, open-drain
output or alternate function. Ports 3 and 4 have
Px~PIN and Px_REG registers and lack internal
pull-ups. As standard outputs, these pins can only furiction in open-drain mode and need external pull-ups.
Ports 3 and 4 also are the multiplexed address/data
bus. When emitting the address, an internal pull-up device is active and does not need external pull-ups. Port
o is the analog input port, and only has a Px_PIN
register because there are no output drivers. As a digital
port, Port 0 pins can only function as inputs.
Event Processor Array (EP A)-The EPA performs input event capture and output event generation functions using Timerl and Timer2. It consists of 10 capture/compare modules, 2 compare only modules and
the 2 timers. In capture mode, when an external event
occurs the EPA stores the value of the timer, generates
an interrupt or both. A rising, falling, or any edge can
trigger a capture. All captures are double buffered. In
compare mode, when the timer matches the value in
the compare register the EPA changes the state of an
output pin, generates an interrupt, or both. The EPA
sets, resets or toggles the pin when the compare occurs.
The timers can count up or count down. The clock
source to the timers can be internal or external. The
clock also goes through a programmable prescaler. The
prescaler divides the oscillator frequency within a range
of I to 64. The EPA also allows two channels to control
a single output pin that is useful for high-speed PWM
generation.
14-10
int:eL
MCS-96 ARCHITECTURAL OVERVIEW
Serial I/O Port (SIO}-The SIO (also known as the
UART) supports 8- or 9-bit data frames with one synchronous mode and 3 asynchronous modes. The synchronous mode transmits or receives 8 bits of data
without start or stop bits and generates a shift clock.
All other devices must synchronize to the 8XCI96KR/
KT's shift clock. The asynchronous frames contain a
start and stop bit, making them ei1;her 10 or 11 bits
long. The II-bit frames allow implementation of specialized multiprocessor communication interfaces. Two
of the asynchronous modes support parity error detection. All three asynchronous modes support full or half
duplex operation. Also included is a dedicated baud
rate generator. The SIO on the 8XCI96KR/KT is
compatible with all MCS-96 and MCS-51 devices.
Synchronous Serial I/O Port (SSIO}-The SSIO includes two Serial I/O communication ports with separate data and clock pins. The data format is eight data
bits only. The clock and data pins can be inputs or
outputs. This peripheral supports several standard synchronous serial protocols. A handshake mode allows
two serial channels to transfer data without requiring
extra lines to convey their status. The handshake mode
also permits servicing of the SSIO by the PTS. The
serial channel includes a dedicated baud rate generator.
Each channel has a single byte buffer. If clocked externally, both channels can simultaneously operate at different frequencies. Maximum baud rate is Ya the oscillator frequency. The transmission or reception of a byte
sets an interrupt pending flag.
A/D Converter-Converts analog inputs to a digital
equivalent. Resolution is either 8 or 10 bits with programmable sample and convert times. The main components of the A/D converter are: 8 analog inputs, 8 to
I multiplexer, sample and hold capacitor and the resistor ladder. Refer to the data sheet for all specifications
on AID performance. The A/D Quick Reference section defines the AID terms. Another function implemented with the A/D converter is threshold detection.
The converter generates an interrupt when the analog
input is greater than or less than a programmed digital
value. The KR/KT provides separate VREF and
ANGND supply pins to isolate noise on the Vee or
VSS lines.
Interrupts-There are 37 interrupt sources and 18 interrupt vectors on the 8XCI96KR/KT. With so many
more sources than vectors, the KR/KT implements in-
direct interrupts. 17 of the interrupts are direct, which
means each interrupt has one source and a dedicated
vector location. The remaining 20 interrupt sources are
the indirect interrupts. The term indirect is used because they share the same interrupt vector and another
register identifies the interrupt source. The register,
EPAIPV, contains the highest ending interrupt.
EPAIPV is read to determine the interrupt needing sevice. The TIJMP instruction with EPAIPV simplifies
the servicing of indirect interrupts. The direct interrupts include: NMI, External Interrupt, Trap, Unimplemented Opcode, SIO interrupts, SSIO interrupts,
slave port interrupts, A/D converter and the lower 4
EPA channels. The indirect interrupts include: the upper 6 EPA channels, the 2 compare channels, all 10
EPA overruns and both timer overflows.
Peripheral Transaction Server (PTS)-The PTS is a
microcoded hardware interrupt processor. It responds
to interrupts with a fixed set of actions. These actions
consist of: transferring data, starting an A/D conversion or generating PWM outputs. The PTS completes
these tasks much faster than using interrupt driven
service routines. The PTS can service all interrupts except NMI, Trap and Unimplemented Opcode. The register PTSSEL selects the interrupts handled by the
PTS. Each interrupt managed by the PTS requires a
block of data called the PTS Control Block (PTSCB).
Each PTSCB requires 8 data bytes in register RAM.
The PTSCB determines: the type of PTS, the number of
PTS responses (if applicable), the source for data and
the destination (if applicable). PTS cycles have a higher
priority than interrupts and may temporarily suspend
interrupt service routines.
Slave Port-The slave port is an interface between the
KR/KT and a microprocessor. The KR/KT sits on the
address/data bus of the processor and is accessed as a
memory mapped peripheral. The slave port includes: a
chip select input, 8-bit bidirectional data bus, an addres~ut line, ALE input (to latch the address), WR
and RD inputs to input/output data and an interrupt
output. The address line and the RD/WR select which
registers are accessed (Output data, Status output, Input data or Command input). The various control signals and port structure allow the KR/KT and the processor to communicate with each other without having
to be synchronized.
14-11
•
MCS-96 ARCHITECTURAL OVERVIEW
8.0 8XC196NT PERIPHERALS
Extended Address Port (EPORT)-The 80CI96NT is
the first member of the MCS-96 family to offer addressing that exceeds 64 Kbytes. The 80CI96NT has a
I Mbyte liner address space which is implemented
through 4 address lines added by the EPORT. EPORT
lines are individually assigned to function as either address or I/O. When assigned as I/O, they have the
same functionality as a standard I/O port. As an input,
the pin is a true high-impedance with no pull-ups or
pull-downs. As an output, the pin is either complementary or open-drain. When assigned as address, the
EPORT outputs address AI6-AI9. The address is
strongly driven through the entire bus cycle, eliminating the need for an address latch.
Standard I/O Ports-The 8XCI96NT has six 8-bit
I/O ports. Each pin operates as a dedicated input or
output. Most pins also have an alternate function. The
NT does not use the quasi-bidirectional port pins found
on previous MCS-96 devices. As an input, the pin is a
true high impedance with no pull-ups or pull-downs.
Most ports (ports I, 2, 5 and 6) have direction
registers (P~IR), mode registers (plL-MODE),
data input registers (Px-PIN) and data output registers (plL-REG). This allows the user to configure each
port pin as input,' output, open-drain output or alternate function. Ports 3 and 4 have PxJIN and
PlL-REG registers and lack internal pull-ups. As standard, outputs, these pins can only function in opendrain mode and need external pull-ups. Ports 3 and 4
also are the multiplexed address/data bus. When emitting the address, an internal pull-up device is active and
does not need external pull-ups. Port 0 is the analog
input port, and only has a PxJIN register because
there are no output drivers. As a digital port, Port 0
pins can only function as inputs.
Event Processor Array (EPA)-The EPA performs input event capture and output event generation functions using Timer! and Timer2. It consists of 10 capture/compare modules, 2 compare only modules and
the 2 timers. In capture mode, when an external event
occurs the EPA stores the value of the timer, generates
an interrupt or both. A rising, falling, or any edge can
trigger a capture. All captures are double buffered. In
compare mode, when the timer matches the value in
the compare register the EPA changes the state of an
output pin, generates an interrupt, or both. The EPA
sets, resets or toggles the pin when the compare occurs.
The timers can count up or count down. The clock
source to the timers can be internal or external. The
clock also goes through a programmable prescaler. The
prescaler divides the oscillator frequency within a range
of I to 64. The EPA also allows two channels to control
a single output pin that is useful for high-speed PWM
generation.
Serial I/O Port (SIO)-The SIO (also known as the
UART) supports 8- or 9-bit data frames with one synchronous mode and 3 asynchronous modes. The synchronous mode transmits or receives 8 bits of data
without start or stop bits and generates a shift clock.
All other devices must synchronize to the 8XC196NT's
shift clock. The asynchronous frames contain a start
and stop bit, making them either 10 or II bits long. The
II-bit frames allow implementation of specialized multiprocessor communication interfaces. Two of the asynchronous modes support parity error detection. All
three asynchronous modes support full or half duplex
operation. Also included is a dedicated baud rate generator. The SIO on the 8XCI96NT is compatible with all
MCS-96 and MCS-51 devices.
Synchronous Serial I/O Port (SSIO)-The SSIO includes two Serial I/O communication ports with separate data and clock pins. The data format is eight data
bits only. The clOck and data pins can be inputs or
outputs. This peripheral supports several standard synchronous serial protocols. A handshake mode allows
two serial channels to transfer data without requiring
extra lines to convey their status. The handshake mode
also permits servicing of the SSIO by the PTS. The
serial channel includes a dedicated baud rate generator.
Each channel- has a single byte buffer. If clocked externally, both channels can simultaneously operate at different frequencies. Maximum baud rate is Y. the oscillator frequency. The transmission or reception of a byte
sets an interrupt pending flag.
AID Converter-Converts analog inputs to a digital
equivalent. Resolution is either 8 or 10 bits with programmable sample and convert times. The main components of the AID converter are: 4 analog inputs, 4 to
I multiplexer, sample and hold capacitor and the resistor ladder. Refer to the data sheet for all specifications
on AID performance. The AID Quick Reference section defines the AID terms. Another function implemented with the AID converter is threshold detection.
The converter generates an interrupt when the analog
input is greater than or less than a programmed digital
value. The NT provides separate VREF and ANGND
supply pins to isolate noise on the Vee or Vss lines.
14-12
infel"
MCS-96 ARCHITECTURAL OVERVIEW
Interrupts-There are 37 interrupt sources and 18 interrupt vectors on the 8XCI96NT. With so many more
sources than vectors, the NT implements indirect interrupts. 17 of the interrupts are direct, which means each
interrupt has one source and a dedicated vector location. The remaining 20 interrupt sources are the indirect interrupts. The term indirect is used because they
share the same interrupt vector and another register
identifies the interrupt source. The register, EPAIPV,
contains the highest ending interrupt. EPAIPV is read
to determine the interrupt needing service. The TIJMP
instruction with EPAIPV simplifies the servicing of in"
direct interrupts. The direct interrupts include: NMI,
External Interrupt, Trap, Unimplemented Opcode, SIO
interrupts, SSIO interrupts, slave port interrupts, A/D
converter and the lower 4 EPA channels. The indirect
interrupts include: the upper 6 EPA channels, the 2
compare channels, all 10 EPA overruns and both timer
overflows.
Peripheral Transaction Server (PTS)-The PTS is a
microcoded hardware interrupt processor. It responds
to interrupts with a fixed set of actions. These actions
consist of: transferring data, starting an. A/D conversion or generating PWM outputs. The PTS completes
these tasks much faster than using interrupt driven
service routines. The PTS can service all interrupts except NMI, Trap and Unimplemented Opcode. The register PTSSEL selects the interrupts handled by the
PTS. Each interrupt managed by the PTS requires a
block of data called the PTS Control Block (PTSCB).
Each PTSCB requires 8 data bytes in register RAM.
The PTSCB determines: the type of PTS, the number of
PTS responses (if applicable), the source for data and
the destination (if applicable). PTS cycles have a higher
priority than interrupts and may temporarily suspend
interrupt service routines.
Slave Port-The slave port is an interface between the
, NT and a microprocessor. The NT sits on the address/
data bus of the processor and is accessed as a memory
mapped peripheral. The slave port includes: a chip select input, 8-bit bidirectional data bus, an address input
line, ALE input (to latch the address), WR and RD
inputs to input/output data and an interrupt output.
The address line and the RD/WR select which registers are accessed (Output data, Status output, Input
data or Command iriput). The various control signals
and port structure allow the NT and the processor to
communicate with each other without having to be synchronized.
.
9.0
8XC196MC PERIPHERALS
On-Chip Peripherals-The 8XCI96MC's on-chip peripherals provide special functions useful in a variety of
applications. The peripherals are monitored and controlled via special function registers (SFRs) that can be
accessed indirectly or windowed and thereby treated as
CPU "accumulators."
I/O Ports-The 8XCI96MC has 7 I/O ports, labeled
0-6. Individual port pins are multiplexed to serve for
standard I/O or to carry special signals. All ports are 8bit except port I which is a 5-bit port.
Ports 0, I, 2 and 6 are controlled by SFRs that can be
directly addressed by the RALU through a window in
the register file. Ports 0 and I serve as input to the 13channel A/D, and can also be read as digital inputs.
Port 2 can be configured either as standard I/O ports
or to serve special functions. Port 6 is the output port
for the PWM and WG units.
Ports 3, 4 and 5 are memory mapped and cannot be
windowed. These ports are accessed only via 16-bit addresses. Ports 3 and 4 also serve as the 16-bit external
address/data bus. The Port 5 lines can be selected for
standard I/O or to serve as system bus control pins.
Timers and the Event Processor Array
0
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VREF
AD3/P3.3
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AD4/P3.4
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68-PIN
LEADLESS CHIP CARRIER
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AD5/P3.5
AD6/P3.6
AD7/P3.7
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AD8/P4.0
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AD9/P4.1
TOP VIEW
LOOKING DOWN ON
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PL1
P1.2
P1.3
AD10/P4.2
AD11/P4.3
AD12/P4.4
P1.4
AD13jP4.5
HSI.O
AD14/P4.6
HSI.1
AD15/P4.7
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14-23
II
inlet
8X9X QUICK REFERENCE
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ACH4/PO.4/PUOD.O
AD1/P3.1
AD2/P3.2
ANGND
8X96BH
8X97BH
8X97JF
VREF
VpD
EXTINT/P2.2/PROG
RESET
AD3jP3.3
AD4/P3.4
AD5/P3.5
AD6/P3.6
68-PIN
PLCC
RXD/P2. l/PALE
TXD/P2.0/PVER/SALE
PLO
PLI
PL2
PL3
PL4
AD7/P3.7
AD8/P4.0
AD9/P4.1
AD10/P4.2
TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
HSIO/SID.l
AD11/P4.3
AD12/P4.4
AD13/P4.5
AD14/P4.6
AD15/P4.7
HSII/SID.2
T2CLK/P2.3
HSI2/HS04/SID.3
27 28 29 30 31 32333435 36 37 38 39 40 41 4243
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272110-17
14-24
intel~
8X9X QUICK REFERENCE
EA
ACH3/PO.3
ACH I/PO. I
ACHO/PO.O
ACH2/PO.2
ACH6/PO.6/PhlOD.2
ACH7/PO.7/PhlOD.3
ACH5/PO.5/PhlOD.l
ACH4/PO.4/PhlOD.0
ANGND
VREF
VpD
EXTINT/P2.2/PROG
RESET
RXD/P2.1/PALE
TXD/P2.0/PVER/SALE
Pt.O
Pt.1
Pt.2
Pt.3
Pt.4
HSI.O/SID. I
HSI.l/SID.2
HSO.4/HSI.2/SID.3
HSO.5/HSI.3/SID.4
HSO.O/PACT
HSO. I
Pt.5
Pt.6
Pt.7
P2.6
HSO.2
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8X97BH
8X97JF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vee
Vss
XTALt
XTAL2
ALE/ADV
CD
ADO/P3.0
ADI/P3.1
AD2/P3.2
AD3/P3.3
AD4/P3.4
AD5/P3.5
AD6/P3.6
AD7/P3.7
AD8/P4.0
AD9/P4. I
ADIO/P4.2
ADll/P4.3
ADI2/P4.4
ADI3/P4.5
AD14/P4.6
ADI5/P4.7
T2CLK/P2.3
READY
T2RST/P2.4
BHE/WRH
WR/WRL
PWhl/P2.5/PDO/SPROG
P2.7
Vpp
Vss
HSO.3
272110-18
Shrink-DIP Package
14-25
•
infel .
8X9X QUICK REFERENCE
RESET
RXD/P2.1/PALE
EXTINT/P2.2/PROG
TXD/P2.0/PVER/SALE
HSI.O/SID.1
VpD
HSI.l/SID.2
VREF
HSI.2/HSO.4/SID.3
ANGND
HSI.3/HSO.5/SID.4
ACH4/PO.4/PMOD.0
HSO.O/PACT
ACH5/PO.5/PMOD.l
HSO.l
ACH7 /PO. 7/PMOD.3
HSO.2
ACH6/PO.6/PMOD.2
HSO.3
EA
VSS
Vpp
PWM/P2.5/PoO/SPROG
8095
8395
8X98
4a-PIN
DIP
Vee
Vss
XTALI
XTAL2
WRL/WR
WRH,!BHE
ALE/AoV
RD
READY
ADI5/P4.7
ADO/P3.0
ADI4/P4.6
AD1/P3.1
AD.13/P4.5
AD2/P3.2
ADI2/P4.4
AD3/P3.3
ADll/P4.3
AD4/P3.4
AD10/P4.2
AD5/P3.5
AD9/P4.1
AD6/P3.6
AD8/P4.0
AD7/P3.7
272110-19
14-26
int'eL
5.0
8X9X QUICK REFERENCE
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are two VSS pins, both of which must be connected.
VPD
RAM standby supply voltage (5V). This voltage must be present during normal operation.
In a Power Down condition (Le., Vee drops to zero), if RESET is activated before Vee
drops below spec and VPD continues to be held within spec., the top 16 bytes in the
Register File will retain their contents.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the
analog portion of the A/D converter and the logic used to read Port O. Must be
connected to use A/D or Port O.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential
as Vss.
Vpp
Programming voltage for the EPROM devices. It should be + 12.75V for programming
and will float to 5V otherwise. The pin should not be above Vee for ROM and CPU
devices. This pin must be left floating in the application circuit for EPROM devices.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT*t
Output of the internal clock generator. The frequency of CLKOUT is
frequency. It has a 33% duty cycle.
RESET
Reset input to the chip. Input low for a minimum 10 XTAL 1 cycles to reset the chip. The
subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-statetime RESET sequence.
SUSWIDTH*t
Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the
bus cycle in progress. If SUSWIDTH is a 1, a 16-bit bus cycle occurs. If SUSWIDTH is a 0
an S-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an S-bit bus. If this pin is left
unconnected, it will rise to Vee.
Va the oscillator
NMI*t
A positive transition causes a vector to external memory location OOOOH.
INST*t
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to off-chip
memory. EA = + 12.75V causes execution to begin in the Programming Mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Soth pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory
reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CGA. WR will go low
for every external write, while WRL will go low only for external writes where an even byte
is being written. WR/WRL is activated only during external memory writes.
SHE/WRH
Sus High Enable or Write High output to external memory, as selected by the GGR. SHE
will go low for external writes to the high byte of the data bus. WRH will go low for
external writes where an odd byte is being written. SHE/WRH is activated only during
external memory writes.
14-27
•
intet
5.0
8X9X QUICK REFERENCE
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
READY
Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge
of CLKOUT, the memory controller goes into a wait mode untii the next positive transition
in CLKOUT occurs with READY high. When the external memory is not being used,
READY has no effect. Internal control of the number of wait states inserted into a bus
cycle held not ready is avaiiable in the CCR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are avaiiable: HSO.O, HSO.1 , HSO.2,
HSO.3, HSOA and HSO.5. Two of them (HSOA and HSO.5) are shared with the HSI Unit.
Port 0:1:
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1t
8-bit quasi-bidirectional I/O port.
Port 2t
8-bit multi-functional port. Six of its pins are shared with other functions in the 8096BH, the
remaining 2 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional 110 ports with open drain outputs. These pins are shared with the
multiplexed address/data bus. Ports 3 and 4 are also used as a command, address and
data path by EPROM devices operating in the Programming Mode.
PMODE
Determines the EPROM programming mode.
PACT
A low signal in Auto Programming Mode indicates that programming is in progress. A high
signal indicates programming is complete.
PVAL
A low signal in Auto Programming Mode indicates that the device was programmed
correctly.
. SALE
A falling edge of Auto Programming Mode indicates that Ports 3 and 4 contain valid
programming address/command information (output from master).
SPROG
A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid
programming data (output from master).
SID
Assigns a pin of Ports 3 and 4 to each slave to pass programming verification.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates that Ports 3 and 4 contain valid programming address/command
information (input to slave).
PROG
A falling edge in Slave Programming Mode indicates that Ports 3 and 4 contain valid
programming data (input to slave).
PVER
A high signal in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates the byte programmed correctly.
PVAL
A high signal in Slave Programming Mode indicates the device was programmed correctly.
PD~
A low signal in Slave Programming Mode indicates that the PROG pulse was applied for
longer than allowed.
'Not available on Shrink-DIP package.
tNot available on 48-pin device.
:j:Port 0.0.1.2.3 not available on 48-pin device.
14-28
intel~
8X9X QUICK REFERENCE
6.0 OPCODE TABLE
Opcode
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
Instruction
SKIP
CLR
NOT
NEG
XCH
DEC
EXT
INC
SHR
SHL
SHRA
RESERVED"
SHRL
SHLL
SHRAL
NORML
RESERVED"
CLRB
NOTB
NEGB
XCHB
DECB
EXTB
INCB
SHRB
SHLB
SHRAB
RESERVED"
RESERVED"
RESERVED"
RESERVED"
RESERVED"
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SCALL
SCALL
SCALL
SCALL
SCALL
SCALL
SCALL
SCALL
JBC
JBC
JBC
JBC
14-29
Opcode
Instruction
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
JBC
JBC
JBC
JBC
JBS
JBS
JBS
JBS
JBS
JBS
JBS
JBS
AND DIRECT (3 OPS)
AND IMMEDIATE (3 OPS)
AND INDIRECT (3 OPS)
AND INDEXED (3 OPS)
ADD DIRECT (3 OPS)
ADD IMMEDIATE (3 OPS)
ADD INDIRECT (3 OPS)
ADD INDEXED (3 OPS)
SUB DIRECT (3 OPS)
SUB IMMEDIATE (3 OPS)
SUB INDIRECT (3 OPS)
SUB INDEXED (3 OPS)
MULU DIRECT (3 OPS)
MULU IMMEDIATE (3 OPS)
MULU INDIRECT (3 OPS)
MULU INDEXED (3 OPS)
ANDB DIRECT (3 OPS)
ANDB IMMEDIATE (3 OPS)
ANDB INDIRECT (3 OPS)
ANDB INDEXED (3 OPS)
ADDB DIRECT (3 OPS)
ADDB IMMEDIATE (3 OPS)
ADDB INDIRECT (3 OPS)
ADDB INDEXED (3 OPS)
SUBB DIRECT (3 OPS)
SUBB IMMEDIATE (3 OPS)
SUBB INDIRECT (3 OPS)
SUBB INDEXED (3 OPS)
MULUB DIRECT (3 OPS)
MULUB IMMEDIATE (3 OPS)
MULUB INDIRECT (3 OPS)
MULUB INDEXED (3 OPS)
AND DIRECT (2 OPS)
AND IMMEDIATE (2 OPS)
AND INDIRECT (2 OPS)
AND INDEXED (2 OPS)
ADD DIRECT (20PS)
ADD IMMEDIATE (2 OPS)
ADD INDIRECT (2 OPS)
ADD INDEXED (2 OPS)
III
inteL
6.0
8X9X QUICK REFERENCE
OPCODE TABLE (Continued)
Opcode
Instruction
Opcode
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
SUB DIRECT (2 OPS)
SUB IMMEDIATE (2 OPS)
SUB INDIRECT (2 OPS)
SUB INDEXED (2 OPS)
MULU DIRECT (2 OPS)
MULU IMMEDIATE (2 OPS)
MULU INDIRECT (2 OPS)
MULU INDEXED (2 OPS)
ANDB DIRECT (2 OPS)
ANDB IMMEDIATE (2 OPS)
ANDB INDIRECT (2 OPS)
ANDB INDEXED (2 OPS)
ADDB DIRECT (2 OPS)
ADDB IMMEDIATE (2 OPS)
ADDB INDIRECT (2 OPS)
ADDB INDEXED (2 OPS)
SUBB DIRECT (2 OPS)
SUBB IMMEDIATE (2 OPS)
SUBB INDIRECT (2 OPS)
SUBB INDEXED (2 OPS)
MULUB DIRECT (2 OPS)
MULUB IMMEDIATE (2 OPS)
MULUB INDIRECT (2 OPS)
MULUB INDEXED (2 OPS)
OR DIRECT
OR IMMEDIATE
OR INDIRECT
OR INDEXED
XOR DIRECT
XOR IMMEDIATE
XOR INDIRECT
XOR INDEXED
CMP DIRECT
CMP IMMEDIATE
CMP INDIRECT
CMP INDEXED
DIVU DIRECT
DIVU IMMEDIATE
DIVU INDIRECT
DIVU INDEXED
ORB DIRECT
ORB IMMEDIATE
ORB INDIRECT
ORB INDEXED
XORB DIRECT
XORB IMMEDIATE
XORB INDIRECT
XORB INDEXED
CMPB DIRECT
CMPB IMMEDIATE
CMPB INDIRECT
CMPB INDEXED
9C
90
9E
9F
AO
A1
A2
A3
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
14-30
Instruction
DIVUB DIRECT
DIVUB IMMEDIATE
DIVUB INDIRECT
DIVUB INDEXED
LD DIRECT
LD IMMEDIATE
LD INDIRECT
LD INDEXED
ADDCDIRECT
ADDC IMMEDIATE
ADDC INDIRECT
AD DC INDEXED
SUBCDIRECT
SUBC IMMEDIATE
SUBC INDIRECT
SUBCINDEXED
LOBZE DIRECT
LOBZE IMMEDIATE
LOBZE INDIRECT
LDBZE INDEXED
LOB DIRECT
LOB IMMEDIATE
LOB INDIRECT
LOB INDEXED
ADDCB DIRECT
ADDCB IMMEDIATE
ADDCB INDIRECT
ADDCB INDEXED
SUBCB DIRECT
SUBCB IMMEDIATE
SUBCB INDIRECT
SUBCB INDEXED
LDBSE DIRECT
LDBSE IMMEDIATE
LOBSE INDIRECT
LOBSE INDEXED
STDIRECT
RESERVED"
ST INDIRECT
STINDEXED
STB DIRECT
RESERVED"
STB INDIRECT
STB INDEXED
PUSH DIRECT
PUSH IMMEDIATE
PUSH INDIRECT
PUSH INDEXED
POP DIRECT
RESERVED"
POP INDIRECT
POP INDEXED
infel~
6.0
8X9X QUICK REFERENCE
OPCODE TABLE (Continued)
Opcode
DO
01
02
03
04
05
06
07
08
.09
OA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
Instruction
Opcode
JNST
JNH
JGT
JNC
JNVT
JNV
JGE
JNE
JST
JH
JLE
JC
JVT
JV
JLT
JE
OJNZ
RESERVED"
RESERVED"
BR (INDIRECT)
RESERVED"
RESERVED*"
RESERVED"
LJMP
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF
Instruction
RESERVED"
RESERVED"
RESERVED"
RESERVED"
RESERVED"
RESERVED"
RESERVED"
LCALL
RET
RESERVED"
PUSHF
POPF
RESERVED"
RESERVED"
RESERVED"
TRAP
CLRC
SETC
01
EI
CLRVT
NOP
'OIV10lVB/MUL/MULB
RST
'Two Byte Instrucllon
"Opcodes which do not have a corresponding instruction will not generate an interrupt if executed.
14-31
II
infel~
7.0
8X9X QUICK REFERENCE
INSTRUCTION SUMMARY
Mnemonic
Operands
Flags
Operation (Note 1)
ADD/ADDB
2
D
~
D+A
ADD/ADDB
3
D
~
B+A
D ~ D+A+C
D
~
D-A
SUS/SUSS
3
D
~
S-A
J,
,.,.-
SUSC/SUSCS
2
D
~
D-A+C-1
J,
CMP/CMPS
2
D-A
MUL/MULU
2
D,D + 2
~
MUL/MULU
3
D,D + 2
~
S* A
MULS/MULUS
2
D,D + 1
~
DOA
MULS/MULUS
3
D,D + 1
~
SOA
,.-
2
D
~
(D, D + 2)/ A, D + 2
~ remainder
2
D
~
(D, D + 1)/A, D + 1
~
remainder
DIV
2
D
~
(D, D + 2)/ A, D + 2
~
remainder
DIVS
2
D
~
(D,D + 1)/A,D + 1
~
remainder
AND/ANDS
2
D
~
DandA
AND/ANDS
3
D
~
SandA
OR/DRS
2
D
~
DorA
XOR/XORS
2
D
~
D (excl. or) A
LD/LDS
2
D~A
ST/STS
2
A~D
LDBSE
2
D
~
A;D + 1
~
LDBZE
2
D
~
A;D + 1
~O
PUSH
1
SP
POP
1
A
PUSHF
0
SP ~ SP - 2; (SP).
PSW ~ OOOOH
~
~
SP - 2; (SP)
(SP); SP
~
~
A
SP + 2
~
PSW;
I
0
PSW ~ (SP); SP ~ SP + 2;
SJMP
1
PC
LJMP
1
PC ~ PC + 16-bit offset
SR [indirect)
1
PC~
SCALL
1
LCALL
RET
1
0
PC + 11-bit offset
(A)
'SP
PC
~
SP
PC
~
~
SP - 2; (SP) ~ PC;
PC + 16-bit offset
PC
~
(SP);SP
~
SP - 2; (SP) ~ PC;
PC + 11-bit offset
~
-
- - - - - ,.- ,.-
-
?
?
2
-
?
3
-
?
3
-
3
,.,.,.,.-
,.,.,.,.-
SP + 2
14-32
I
V
-
-
-
?
-
?
t
t
t
t
0
0
-
-
0
0
0
0
-
0
0
-
- - - -
-
-
-
-
-
-
2
2
-
-
3,4
- - - - - - - -
-
0
0
0
0
0
,.-
,.- ,.- ,.-
,.-
,.-
-
-
-
-
5
- - - - - - -
-
-
5
-
- - -
-
-
5
- - - -
-
-
-
POPF
~
-
-
SIGN(A)
-
,.,.,.,.,.,.,.-
2
DIVU
t
t
t
t
t
t
t
,.,.-
2
DIVUS
,.- ,.,.- ,.,.- ,.,.- ,.,.- ,.,.- ,.,.- ,.-
C
ADDC/ADDCB
D*A
ST
N
SUB/SUBB
Notes
VT
Z
0
3,4
-
~O
~,.-
-
5
intel~
7.0
8X9X QUICK REFERENCE
INSTRUCTION SUMMARY (Continued)
Mnemonic
Operands
Flags
Operation (Note 1)
J (conditional)
1
PC -
JC
1
Jump if C
PC
+
Z
S-bit offset (if taken)
= 1
JNC
1
Jump ifC
=0
JE
1
Jump if Z
= 1
JNE
1
Jump ifZ
=0
JGE
1
Jump if N
=0
JLT
1
Jump ifN
= 1
JGT
1
Jump if N
JLE
1
Jump if N
= 0 and Z = 0
= 1 or Z = 1
JH
1
Jump if C
= 1 and Z = 0
JNH
1
Jump if C
= 0 or Z = 1
JV
1
Jump if V
JNV
1
= 1
Jump if V = 0
JVT
1
Jump if VT
= 1; Clear VT
JNVT
1
Jump if VT
= 0; Clear VT
JST
1
Jump ifST
= 1
JNST
1
Jump ifST
=0
JBS
3
Jump if Specified Bit
= 1
JBC
3
Jump if Specified Bit
=0
DJNZ
1
D PC -
D - 1; if D 06 0 then
PC + S-bit offset
DEC/DECB
1
D -
D-1
NEG/NEGB
1
D -
O-D
INC/INCB
1
D -
D
EXT
1
D -
D; D
EXTB
1
D -
D;D
NOT/NOTB
1
D -
Logical Not (D)
+
1
+2
+1
-
Sign (D)
-
Sign (D)
CLR/CLRB
1
D-O
SHL/SHLB/SHLL
2
C -
SHRISHRB/SHRL
2
0-- msb-----Isb -- C
msb-----Isb -
0
SHRA/SHRAB/SHRAL
2
msb -- msb-----Isb -- C
SETC
0
C-1
CLRC
0
C-O
CLRVT
0
VT -
N
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
14-33
V VT ST
- - - - - - - - - - - - - - - - - - - - - - - - - 0 - 0 - - - - - - - - -
Notes
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5,6
5,6
- - - - - ,,- ,,- ,,- ,,- i ,,- ,,- ,,- ,,- i ,,- ,,- ,,- ,,- i ,,- ,,- 0 0 - ,,- ,,- 0 0 - ,,- ,,- 0 0 - 1 0 0 0 ,,- ? ,,- ,,- i -
5
,,- ? ,,,,- ,,- ,,-
7
- - - -
0
C
1
0
-
0
-
,,,,-
0 - - - - - 0 -
2
3
7
7
II
8X9X QUICK REFERENCE
7.0
INSTRUCTION SUMMARY (Continued)
Mnemonic
Flags
Operands
Operation (Note 1)
Z
0
N
V
Notes
VT
ST
RST
0
PC -
0
0
0
0
01
0
-
-
-
EI
0
Disable All Interrupts (I 0)
Enable All Interrupts (I +-:- 1)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
'"
?
0
-
-
-
7
-
-
-
-
-
-
9
20BOH
NOP
0
PC-PC+1
SKIP
0
PC -
NORML
2
Left shift till msb = 1; 0 -
TRAP
0
SP PC -
PC + 2
SP - 2; (SP) (2010H)
shift count
PC
0
C
B
. NOTES:
1. If the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done. Operands 0, B and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can be
located anywhere in memory.
2. D, 0 + 2 are consecutive WORDS in memory; 0 is DOUBLE-WORD aligned.
3. D, D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 204B bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
S. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
20BOH .
. 9. The assembler will not accept this mnemonic.
14-34
inteL
8.0
8X9X QUICK REFERENCE
OPCODES, INSTRUCTION LENGTH AND STATE TIMES
DIRECT
0
Z
0
W
W
0
III
W
LONG
W
III
W
0
III
W
eWw
lll
III
W
eWw
lll
W
0
III
W
e@
-Ill
III
W
e~
II.
0
m
64
3
4
65
4
5
66
3
6/11
3
7/12
67
4
6111
5
7112
44
4
5
45
5
6
46
4
7/12
4
8/13
47
5
7/12
6
8/13
0
0
m
ADD
2
ADD
3
W
II.
0
t: IIlF
~
z
INDEXED@
SHORT
AUTO-INC.
Will
~w
I-'~
0
W
NORMAL
III
0
z
c
a:
~
INDIRECT@
IMMEDIATE
0
II.
0
0
Will
'"'W
~~
t: IIlF
0
0
II.
0
~~
~~
t: !;iF m
t: !;iF
m
0
0
II.
0
Ww
~~
Ww
~~
t:m !;iF m
t: !;iF
ARITHMETIC INSTRUCTIONS
ADOB
2
74
3
4
75
3
4
76
3
6/11
3
7112
77
4
6/11
5
7/12
ADDB
3
54
4
5
55
4
5
56
4
7/12
4
8/13
57
5
7/12
6
8/13
ADDC
2
A4
3
4
A5
4
5
A6
3
6/11
3
7112
A7
4
6/11
5
7112
ADDCB
2
B4
3
4
B5
3
4
B6
3
6/11
3
7112
B7
4
6/11
5
7/12
7/12
SUB
2
68
3
4
69
4
5
6A
3
6/11
3
7/12
6B
4
6/11
5
SUB
3
48
4
5
49
5
6
4A
4
7/12
4
8113
4B
5
7/12
6
8/13
SUBB
2
78
3
4
79
3
4
7A
3
6/11
3
7112
7B
4
6/11
5
7/12
SUBB
3
58
4
5
59
4
5
5A
4
7/12
4
8/13
5B
5
7/12
6
8/13
SUBC
2
A8
3
4
A9
4
5
AA
3
6111
3
7/12
AB
4
6/11
5
7/12
SUBCB
2
B8
3
4
B9
3
4
BA
3
6/11
3
7/12
BB
4
6/11
5
7/12
CMP
2
88
3
4
89
4
5
8A
3
6/11
3
7/12
8B
4
6111
5
7/12
CMPB
2
98
3
4
99
3
4
9A
3
6/11
3
7/12
9B
4
6/11
5
7/12
MULU
2
6C
3
25
6D
4
26
6E
3
27/32
3
28/33
6F
4
27132
5
28/33
MULU
3
4C
4
26
4D
5
27
4E
4
28/33
4
29/34
4F
5
28/33
6
29/34
MULUB
2
7C
3
17
7D
3
17
7E
3
19/24
3
20/25
7F
4
19/24
5
20/25
MULUB
3
5C
4
18
5D
4
18
5E
4
20/25
4
21/26
5F
5
20/25
6
21/26
MUL
2
4
29
5
30
4
31/36
4
32137
5
31/36
6
32137
MUL
3
6
31
MULB
2
4
21
MULB
3
12>
12>
12>
12>
DlVU
2
8C
DlVUB
2
DlV
2
DlVB
2
5
30
4
21
5
22
12>
12>
®
12>
5
22
12>
12>
12>
12>
3
25
80
4
26
8E
9C
3
17
9D
3
17
12>
12>
4
29
5
30
4
21
12>
®
4
21
5
32/37
5
33/38
4
23/28
4
24/29
5
24/29
5
25/30
12>
12>
12>
12>
3
28/32
3
29/33
8F
9E
3
20/24
3
21/25
12>
12>
4
32/36
4
33/37
4
24/28
4
25/29
6
32137
7
33/38
5
23/28
6
24/29
6
24/29
7
25/30
4
28/32
5
29/33
9F
4
20124
5
21/25
12>
12>
5
32/36
6
33/37
5
24/28
6
25/29
272110-20
NOTES:
'Long indexed and Indirect + instructions have identical opcodes with Short indexed and Indirect modes, respectively. The
second byte of instructions using any Indirect or indexed addressing mode specifies the exact mode used. If the second
byte is even, use Indirect or Short indexed. If it is odd, use Indirect + or Long indexed. In all cases the second byte of the
instruction always specifies an even (word) location for the address referenced.
2
2
16120
16120
OPCODE
EF
28-2F@
PO
F7
BYTES
STATES
3
2
I
I
1311~
1311~
1211~
21124
272110-21
NOTES:
'"
0..
.; .;
"'0.. >uu
0..
'" >
'"
'"' >tll~a:t:l '"' ......'a:"' >'"
......
w
N
0..
1~......
...z
;::
xw
0..
~
0
x
a:
0
0
0..
0..
- ;;:
~
0..
HSO.4/HSI.2/SID.2
"l "": "!
0..
>
0..
......
0
;;:
Vi Vi
:x: :x:
......
0
ci
Vi
:::ci
Vi
...x
272111-22
NOTE:
N.C. means No Connect (do not connect these pins).
SO-Pin QFP Package Diagram
14-51
III
intel .
8XC196KB QUICK REFERENCE
17 15 13 11
7
5
3
18 19 16 14 12 10 8
6
4
9
2 68
67 66
20 21
68-PIN
GRID ARRAY
65 64
26 27
TOP VIEW
61 60
2829
Looking Down on
Component Side
of PC Board
59 58
2223
2425
30 31
63 62
57 56
55 54
32 33
34 36 38 40 42 44 46 48 50 53 52
35 37 39 41 43 45 47 49 51
272111-23
68-Pln PGA Package (Top View) 80C196KB Only
PGA
Description
PGA
Description
PGA
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
ACH7/PO.7/PMODE.3
ACH6/PO.6/PMODE.2
ACH2/PO.2
ACHO/PO.O
ACH1/PO.l
ACH3/PO.3
NMI
EA
VCC
Vss
XTALI
XTAL2
CLKOUT
BUSWIDTH
INST
ALE/ADV
RD
ADO/P3.0/PVAL
AD1/P3.1
AD2/P3.2
AD3/P3.3
AD4/P3.4
AD5/P3.5
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
AD6/P3.6
AD7 IP3.7 IEXTINT
AD8/P4.0
AD9/P4.1
AD10/P4.2
ADll/P4.3
AD12/P4.4
AD13/P4.5
AD14/P4.6
AD15/P4.7
T2CLK/P2.3
READY
T2RST IP2.41 AINC
BHE/WRH
WR/WRL
PWM/P2.5
P2.7/T2CAPTURE/PACT
Vpp
Vss
HSO.3/SID3
HSO.2/SID2
P2.6/T2UPDN
Pl.7/HOLD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pl.6/HLDA
Pl.5/BREQ
HSO.l
HSO.O
HSO.5/HSI.3/SID.3
HSO.4/HSI,2/SID.2
HSl,l/SID.l
HSI,O/SID.O
Pl.4
Pl.3
Pl.2
Pl.l
Pl.0
TSD/P2.0/PVER
RXD/P2.1/PALE
RESET
EXTINTIP2.2/PROG
VSS(1)
VREF
ANGND
ACH4/PO.4/PMODE.0
ACH5/PO.5/PMODE.l
NOTE:
1. This pin was formerly the Clock Detect Enable pin. This function is not guaranteed to work. This pin must be directly
connected to Vss.
14-52
inteL
8XC196KB QUICK REFERENCE
0
c
..:
'"
...
In
>'" O!:
> c
......
~ ~...; ...;
0..
~ I~
..:
0
0..
0..
ACH5jPt.lODE. 1jPO.5
P3.2jAD2
ACH4jPt.lODE.OjPO.4
P3.3jAD3
ANGND
P3.4jAD4
VREr
P3.5jAD5
52-PIN PLCC
Vss
EXTlNTjPROGjP2.2
P3.SjADS
P3.7 JAD7
8XC198
RESET
P4.0jAD8
RXD(iiilljP2.1
P4.1jAD9
P4.2jAD10
TXDjPVERjP2.0
TOP VIEW
SID.OjHSI.O
SID. 1jHSI. 1
P4.3jAD11
P4.4jAD12
Looking Down on
Component Sid.
of PC Board
SID.2jHSI.2jHSO.4
SID.3jHSI.3jHSO.5
N
0 0 >'"
0 V)
0
V)
:I:
:I:
'"
:I:
s:'".
P4.5jAD13
P4.SjAD14
:I:
.
,...
>c '"
..:
...
......
~ I-J ~
'"' ......
'"
~~~ " '"..:
... ...
...'"
(I)
a. II) ~ ......
>tn>o..N~r.4
0..
0..
..J
0..
..:
()
N
In
N
272111-24
52·Pin PLCC Package Diagram
14-53
8XC196KB QUICK REFERENCE
.,.c
.......
.,.""
... ... '" Q Q c.,. ..,Q ...Q c
~ .......
... .......""'" ~::;"" ...to "" "" ~.,. ......."".., .........."" ~'" ~., ~...
","! ""
to to
..,c ...c c
'"
to >'"
Q.
..,
Q.
.,
0
II)
c c c c
....... ~ ....... .......
.. .. i. . . i. . .
0
Q.
Q.
>
Q.
Q.
Q.
Q.
Q.
Q.
Q.
Q.
o
AD1/P3.1
ADO/PVAL/P3.0
RD
P2.3/T2CLK
Vss
READY
P2.4/T2RST!AiiiC
ALE/ADv"
INST
N.C.
VSS
WR/WiiL
N.C.
P2.5/PWM
BO-PIN QFP
XTAL2
N.C.
XTAL1
Vpp
BXC19B
VSS
Vss
Yss
Vss
HSO.3
Vee
Vce
TOP VIEW
Ycc
EA
YSS
Looking Down on
Component Side
of PC Board
Vss
N.C.
HSO.2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
HSO.1
ACH6/PMODE.2/PO.6
HSO.O
ACH7 /EXTINT/PMODE.3/PO. 7
N.C.
HSO.5/HSI.3/SID.3
ACH5/PMODE.1/PO.5
Vss
HSO.4/HSI.2/SID.2
ACH,VPMODE.O/PO.4
c
z
z
'"
""
... "'.,.
~ >(1) ~ >~Iti
~
~...
Q.
z
;:::
(;l
'"
0
'" '"'"
Q.
~
~
c
x
'"
Q.
.......
>~ ~
c..i c..i c..i c..i "!
iii
Z :i % Z iii :z:
:z:
'"fr.
';:;-
.......
0
:::-
ci ci
iii iii
~
272111-25
NOTE:
N.C. means No Connect (do not connect these pins).
80-Pin QFP Package Diagram
14-54
8XC196KB QUICK REFERENCE
....z
;::
1:5
0
"'"...;
...;
Q
Q
0
:I
0
:I
Q
«
N
"- ""- CD
""
0 0
1i5
"-
"-
'"
>0
VI
>VI
~"
Q
«
~
::; N...J
0
«
«
.... ~ ~ ~ 1ii1 ,.;"- ,.;"....
x x > ~ ""
PMODE.l/PO.5
P3.2/AD2
PMODE.O/PO.4
P3.3/AD3
ANGND
P3.4/AD4
VREf
P3.5/AD5
52-PIN PLCC
Vss
EXTINT/PROG/P2.2
P3.6/AD6
P3.7/AD7
8XC194
RESET
P4.0/AD8
RXD/PALE/P2.1
P4.1/AD9
TXD/PVER/P2.0
P4.2/AD10
TOP VIEW
SID.O/HSI.O
SID.l/HSI.l
P4.3/ADll
P4.4/ADI2
Looking Down on
Component Side
of PC Board
SID.2/HSI.2/HSO.4
SID.3/HSI.3/HSO.5
0
N
0 0
0 V>
V>
::c ::c ::c
V>
VI
>VI
'"c:i ..:'
VI
a.
It}
~
~
I-J
P4.5/ADI3
P4.6/ADI4
..
>Q.c-.i~N
V>
::c
~~~«
"-
III
"~ N ..t
«
0::
~ ""
....
V>
'""""
...J
U
N
....
"-
":;:
OIl
0::
N
....
272111-26
52-Pin PLCC Package Diagram
14-55
inteL
8XC196KB QUICK REFERENCE
'" • '" < ...
~ ~ ~
..... ~
.....;
",,,! •
..;
..; '"
..;
'"a. >"'~
a. a. ~~ a.
'"
0
0
<
.....
AD1/P3.1
0
CD
0
0
0
CD
0
• ;:;'"
'"a. •a. '"a. a. ...a.
0
0
'" ;:;'"
;:; ;:; ;:;
a.
a.
a.
eo
'"
0
~
~ ~
~ ~ ~ ~
~
N
CD
0
.. . . . . . . .
P2.3/T2CLK
0
ADO/PYAL/P3.0
RD
Yss
READY
61
ALE/ADV
INST
P2.4/T2RST
/AiNC
N.C.
YSS
WRJiiiRL
N.C.
P2.5/PWM
BO-PIN QFP
XTAL2
N.C.
XTAL1
Ypp
BXC194
YSS
YSS
YSS
YSS
Yee
HSO.3
TOP VIEW
Vee
vee
EX
51
Looking Down on
Component Side
of PC Board
VSS
N.C.
Vss
HSO.2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
PMODE.2/PO.6
HSO.1
EXTINT/PMODE.3/PO. 7
HSO.O
N.C.
HSO.5/HSI.3/SID.3
PMODE.1/PO.5
Vss
PMODE.O/PO.4
HSO.4/HSI.2/SID.2
0
z
z
CI
<
... '"
'"
N
0
. u u u U "! iii
...
III
~It;; .... ....
::'> ....
a. > '" a. 0.. ;;"~ Z Z Z Z iii
:J:: :J::
~
...
'"
t-
z
x
;::
...
.....
~ -;:;.
...'">
a.
o
x
'"
.....
0
~
ci ci
iii iii
~
272111-27
NOTE:
N.C. means No Connect (do not connect these pins).
SO-Pin QFP Package Diagram
14-56
intel"
6.0
8XC196KB QUICK REFERENCE
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are three VSS pins, all of them must be connected.
VREF
Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
Vss·
Vpp
Programming voltage. Also timing pin for the return from power down circuit. Connect this pin
with a 1 ,...F capacitor to Vss. If this function is not used, connect to Vee.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is
frequency. It has a 50% duty cycle.
RESET
Reset input and open-drain output. Input low for at least 4 state times to reset the chip. The
subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-state-time
sequence in which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to
location 2080H is executed. Input high for normal operation. RESET has an internal pullup.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TIL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide
a signal to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.
% the oscillator
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even by1e is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE = 0
selects the bank of memory that is connected to the high by1e of the data bus. AO = 0
selects the bank of memory that is connected to the low byte of the data bus. Thus accesses
to a 16-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only
(AO = 1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the
pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only
during 16-bit external memory write cycles.
14-57
•
intel~
8XC196KB QUICK REFERENCE
6.0 PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is
low priorto the failing edge of CLKOUT, the memory controller goes into a wait mode until the
next positive transition in CLKOUT occurs with READY high. When the external memory is
not being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle (held not ready) is available through configuration of CCA.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
the SID in Slave Programming Mode.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSOA and HSO.5) are shared with the HSI Unit.
Port 0
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode.
Port 1
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSA.7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ
Bus Request output activated when the bus controller has a pending external memory cycle.
Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2, and 3. The TxD function is
enabled by setting IOC1.5. In mode 0 the pin is used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin functions as input or output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt. EXTINT is selected as the
external interrupt source by setting IOC1.1 high.
T2CLK
The T2CLK pin is.the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.3. T2RST is enabled as the reset source by clearing IOCO.5.
PWM
Port 2.5 can be enabled as a PWM output by setting IOC1.0. The duty cycle of the PWM is
determined by the value loaded into the PWM-CONTROL register (17H).
T2UPDN
The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2
up/ down function is enabled by setting IOC2.1.
T2CAP
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15).
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
SID
Slave 10 Number. Used to assign each slave a pin of Port 30r 4 to use for passing
programming verification acknowledgement. For example, if gang programming in the Slave
Programming Mode, the slave with SID = 001 will use Port 3.1 to signal correct or incorrect
program verification.
14-58
in1et
6;0
8XC196KB QUICK REFERENCE
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
PROG
Program.ming. Falling edge indicates valid data on PBUS and the beginning of programming.
Rising edge indicates end of programming.
PACT
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
PVAL
Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.
PVER
Program Verification. Used in Slave Programming and Auto CLB Programming Modes.
Signal is low after rising edge of PROG if the programming was not successful.
AINC
Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
PORT
3 and4
During
Programming
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory. Should have pull ups to Vee (15 kO).
7.0
OPCODE TABLE
00
SKIP
15
DECB
2A
SCALL
01
CLR
16
EXTB
2B
SCALL
02
NOT
17
INCB
2C
SCALL
,
03
NEG
1B
SHRB
2D
SCALL
04
RESERVED
19
SHLB
2E
SCALL
05
DEC
1A
SHRAB
2F
SCALL
06
EXT
1B
RESERVED
30
JBC
07
INC
1C
RESERVED
31
JBC
OB
SHR
10
RESERVED
32
JBC
09
SHL
1E
RESERVED
33
JBC
OA
SHRA
1F
RESERVED
34
JBC
20
SJMP
35
JBC
OB
RESERVED
DC
SHRL
21
SJMP
36
JBC
00
SHLL
22
SJMP
37
JBC
OE
SHRAL
23
·SJMP
38
JBS
OF
NORML
24
SJMP
39
JBS
10
RESERVED
25
SJMP
3A
JBS
11
CLRB
26
SJMP
3B
JBS
12
NOTB
27
SJMP
3C
JBS
13
NEGB
2B
SCALL
3D
JBS
14
RESERVED
29
SCALL
3E
JBS
14-59
II
intel·
8XC196KB QUICK REFERENCE
7.0 OPCODE TABLE (Continued)
3F JBS
64 ADD DIRECT (2 OPS)
89
CMP IMMEDIATE
40 AND DIRECT (3 OPS)
65 ADD IMMEDIATE (2 OPS)
8A
CMP INDIRECT
41
66 ADD INDIRECT (2 OPS)
8B
CMPINDEXED
42 AND INDIRECT (3 OPS)
67 ADD INDEXED (2 OPS)
8C
DIVUDIRECT
AND IMMEDIATE (3 OPS)
43 AND INDEXED (3 OPS)
68 SUB DIRECT (2 OPS)
8D
DIVU IMMEDIATE
44 ADD DIRECT (3 OPS)
69 SUB IMMEDIATE (20PS)
8E
DIVU INDIRECT
45 ADD IMMEDIATE (30PS)
6A SUB INDIRECT (2 OPS)
8F
DIVU INDEXED
46 ADD INDIRECT (3 OPS)
6B SUB INDEXED (2 OPS)
90
ORB DIRECT
47 ADD INDEXED (3 OPS)
6C MULU DIRECT (2 OPS)
91
ORB IMMEDIATE
48 SUB DIRECT (3 OPS)
6D MULU IMMEDIATE (2 OPS)
92
ORB INDIRECT
49 SUB IMMEDIATE (3 OPS)
6E MULU INDIRECT (2 OPS)
93
ORB INDEXED
4A SUB INDIRECT (3 OPS)
6F' MULU INDEXED (2 OPS)
94
XORBDIRECT
95
XORB IMMEDIATE
96
XORB INDIRECT
4B SUB INDEXED (3 OPS)
70 AN DB DIRECT (2 OPS)
4C MULU DIRECT (30PS)
71
AN DB IMMEDIATE (2 OPS)
4D MULU IMMEDIATE (3 OPS)
72
AN DB INDIRECT (2 OPS)
97
XORB INDEXED
4E MULU INDIRECT (3 OPS)
73 AN DB INDEXED (2 OPS)
98
CMPB DIRECT
4F MULU INDEXED (3 OPS)
74 ADDB DIRECT (2 OPS)
50 AN DB DIRECT (3 OPS)
75
51
99
CMPB IMMEDIATE
9A
CMPB INDIRECT
76 AD DB INDIRECT (2 OPS)
9B
CMPB INDEXED
77 AD DB INDEXED (2 OPS)
9C
DIVUB DIRECT
53 AN DB INDEXED (3 OPS)
78 SUBB DIRECT (2 OPS)
9D
DIVUB IMMEDIATE
54 ADDB DIRECT (3 OPS)
79 SUBB IMMEDIATE (20PS)
9E
DIVUB INDIRECT
55 ADDB IMMEDIATE (3 OPS)
7A SUBB INDIRECT (2 OPS)
9F
DIVUB INDEXED
56 ADDB INDIRECT (3 OPS)
7B SUBB INDEXED (2 OPS)
AO
LDDIRECT
57 AD DB INDEXED (30PS)
7C MULUB DIRECT (2 OPS)
A1
LD IMMEDIATE
58 SUBB DIRECT (3 OPS)
7D MULUB IMMEDIATE (20PS)
A2
LDINDIRECT
AN DB IMMEDIATE (3 OPS)
52 AN DB INDIRECT (3 OPS)
ADDB IMMEDIATE (2 OPS)
59 SUBB IMMEDIATE (3 OPS)
7E MULUB INDIRECT (2 OPS)
A3
LDINDEXED
5A SUBB INDIRECT (3 OPS)
7F MULUB INDEXED (2 OPS)
A4
ADDCDIRECT
5B SUBB INDEXED (3 OPS)
80 OR DIRECT
A5
ADDC IMMEDIATE
5C MULUB DIRECT (3 OPS)
81
A6
AD DC INDIRECT
5D MULUB IMMEDIATE (3 OPS)
82 OR INDIRECT
A7
AD DC INDEXED
5E MULUB INDIRECT (3 OPS)
83 OR INDEXED
A8
SUBCDIRECT
5F MULUB INDEXED (3 OPS)
84
XOR DIRECT
A9
SUBCIMMEDIATE
60 AND DIRECT (2 OPS)
85
XOR IMMEDIATE
AA
SUBC INDIRECT
AB
SUBCINDEXED
61
AND IMMEDIATE (2 OPS)
OR IMMEDIATE
86 XOR INDIRECT
62 AND INDIRECT (2 OPS)
87 XOR INDEXED
AC
LDBZE DIRECT
63
88 CMPDIRECT
AD
LDBZE IMMEDIATE
AND INDEXED (2 OPS)
14-60
int:eL
7.0
8XC196KB QUICK REFERENCE
OPCODE TABLE (Continued)
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9·
LDBZE INDIRECT
LDBZE INDEXED
LDB DIRECT
LDB IMMEDIATE
LDB INDIRECT
LDBINDEXED
ADDCB DIRECT
ADDCB IMMEDIATE
ADDCB INDIRECT
ADDCBINDEXED
SUBCB DIRECT
SUBCB IMMEDIATE
SUBCB INDIRECT
SUBCB INDEXED
LDBSE DIRECT
LDBSE IMMEDIATE
LDBSE INDIRECT
LDBSE INDEXED
STDIRECT
BMOV
ST INDIRECT
ST INDEXED
STB DIRECT
CMPL
STB INDIRECT
STBINDEXED
PUSH DIRECT
CA
CB
CC
CD
CE
CF
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
PUSH INDIRECT
PUSH INDEXED
POP DIRECT
RESERVED
POP INDIRECT
POP INDEXED
JNST
JNH
JGT
JNC
JNVT
JNV
JGE
JNE
JST
JH
JLE
JC
JVT
JV
JLT
JE
DJNZ
DJNZW
RESERVED
BR (INDIRECT)
RESERVED
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
PUSH IMMEDIATE
NOTE:
'Two Byte Instruction
RESERVED-Execution of reserved instructions will cause unimplemented opcode interrupt.
14·61
RESERVED
RESERVED
LJMP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
LCALL
RET
RESERVED
PUSHF
POPF
PUSHA
POPA
IDLPD
TRAP
CLRC
SETC
DI
EI
CLRVT
NOP
'DIV IDIVB/MULfMULB
RST
III
inteL
8.0
8XC196KB QUICK REFERENCE
INSTRUCTION SET SUMMARY
Mnemonic
Operands
Flags
Operation (Note 1)
Z
ADD/ADDB
2
D -
D+A
ADD/ADDB
3
D -
B+A
ADDC/ADDCB
2
D -
D+A+C
SUB/SUBB
2
D -
D-A
SUB/SUBB
3
D -
B-A
SUBC/SUBCB
2
D-D-A+C-1
CMP/CMPB
2
D-A
MUL/MULU
2
D,O + 2 -
MUL/MULU
3
D,D + 2 -
MULB/MULUB
2
D,D + 1 -
MULB/MULUB
3
D,D + 1 -
DIVU
2
D -
xA
BxA
DxA
BxA
D
(D,D + 2) I A,D + 2 -
C
V
"" "" ""
""i "" ""
"" ""
"" "" ""
""i "" ""
"" ""
""- ""- ""-
""
""
N
""
""
""
""
""-
Notes
VT ST
t
t
t
t
t
t
t
-
-
-
-
2
-
-
-
-
-
-
2
-
-
-
-
-
-
3
-
-
-
-
-
-
3
remainder
-
-
-
""
2
""
""
""0
t
t
t
t
-
3
-
-
0
0
-
-
0
0
-
-
-
-
OIVUB
2
D -
(O,D + 1) IA,D + 1 -
remainder
-
-
-
DIV
2
o-
(D,D + 2) I A,D + 2 -
remainder
-
-
-
DIVB
2
D -
(D,D + 1) I A,D + 1 -
remainder
-
-
-
AND/ANDB
2
D -
DANDA
0
-
XOR/XORB
2
D -
LD/LOB
2
D-A
"" ""
"" ""
"" ""
""- ""-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3,4
-
-
-
-
-
-
3,4
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
AND/ANDB
3
0 - BANDA
OR/ORB
2
D -
DORA
D(ecxl.or)A
ST/STB
2
A-D
LDBSE
2
D -
A; D + 1 -
SIGN(A)
LDBZE
2
D -
PUSH
1
SP -
POP
1
A -
PUSHF
0
SP SP - 2; (SP) PSW;
PSW OOOOH; I 0
POPF
0
PSW -
SJMP
1
PC -
PC
LJMP
1
PC -
PC
BR (indirect]
1
PC -
SCALL
1
SP SP - 2;
(SP) PC; PC -
LCALL
1
SP PC -
A; D + 1 - 0
SP - 2; (SP) (SP); SP
+2
0
11-bit offset
""- ""- ""- ""- ""- ""-
16-bit offset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
5
(SP); SP -
+
+
A
0
SP + 2; I -
""
(A)
5
5
PC + 11-bit offset
SP - 2; (SP) PC;
PC + 16-bit offset
14-62
int'eL
8.0
8XC196KB QUICK REFERENCE
INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operands
Flags
Operation (Note 1)
~
RET
0
PC
J (conditional)
1
PC ~ PC
(SP); SP
+
~
SP
+
2
8-bit offset (if taken)
Notes
Z
N
C V VT ST
-
-
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
5
Jump if C
1
-
Jump if C
0
-
-
-
-
-
-
5
1
-
-
-
-
-
-
5
0
-
-
-
-
-
-
5
0
-
-
-
-
-
-
5
1
-
-
-
-
-
-
5
0 and Z = 0
-
-
-
-
-
-
5
-
-
-
-
-
-
5
= 1 and Z = 0
= 0 or Z = 1
= 1
= 0
-
-
-
-
-
-
5
-
-
-
-
-
-
5
-
-
-
-
-
-
5
JGT
1
JLE
1
=
=
Jump if Z =
Jump if Z =
Jump if N =
Jump if N =
Jump if N =
Jump if N =
JH
1
Jump if C
JNH
1
Jump if C
JV
1
Jump if V
JNV
1
Jump if V
-
-
-
-
-
-
5
JVT
1
Jump if VT = 1; Clear VT
-
-
-
-
0
-
5
JNVT
1
Jump if VT
-
-
-
-
0
-
5
1
Jump if ST
=
=
0; Clear VT
JST
1
-
-
-
-
-
-
5
JNST
1
Jump ifST
= 0
-
-
-
-
-
-
5
JBS
3
Jump if Specified Bit
-
-
-
-
-
-
5,6
-
-
-
-
-
-
5,6
-
-
-
-
-
-
5
10
~
~
~
~
-
~
~
~
~
~
~
~
~
i
i
i
JC
1
JNC
1
JE
1
JNE
1
JGE
1
JLT
1
1 or Z
=
JBC
3
Jump if Specified Sit
OJNZI
OJNZW
1
o
OEC/OECS
1
NEG/NEGS
1
INC/INCS
1
~
If 0
*-
0 -1;
0 then PC
1
= 1
= 0
~ PC
+
8-bit offset
NOT/NOTS
1
o~
o~
o~
o~
o~
o~
~
~
0
0
-
-
CLR/CLRB
1
O~O
1
0
0
0
-
-
SHL/SHLB/SHLL
2
C ~ msb - - - - - 19b ~ 0
~
~
~
~
i
-
7
SHRISHRB/SHRL
2
o -+
~
~
~
0
-
~
7
~
7
EXT
1
EXTB
1
0-1
0- 0
+
1
0; 0
+
+
0
0;0
-
2
~
Sign (0)
~
~
0
0
-
-
2
1
~
Sign (0)
~
~
0
0
-
-
3
Logical Not (0)
msb - - - - - 19b -+ C
SHRA/SHRAB/SHRAL
2
msb -+ msb - - - - - 19b -+ C
~
~
0
-
~
SETC
0
C~1
-
-
1
-
-
-
CLRC
0
C~O
-
-
0
-
-
-
14-63
III
intet
8.0
8XC196KB QUICK REFERENCE
INSTRUCTION SET SUMMARY (Continued)
Mnemonic
CLRVT
Operands
0
VT
~
0
~
2080H
AST
0
PC
DI
0
Disable All Interrupts (I
EI
0
Enable All Interrupts (I
NOP
0
PC~PC+1
SKIP
1
PC~PC+2
NORML
2
Left shift till msb = 1; D
0
SP ~ SP - 2;
(SP) ~ PC; PC
TRAP
Flags
Operation (Note 1)
~
N
C
V
VT
ST
-
-
-
-
0
-
0
0
0
0
0
0
0)
-
-
-
-
-
-
1)
-
-
-
-
-
-
-
-
-
-
-
-
~
~
Notes
Z
~
shift count
8
-
-
-
-
-
-
j,JI
j,JI
0
-
-
-
7
-
-
-
-
-
-
9
0
0
0
0
0
0
(2010H)
PUSHA
1
SP ~ SP-2; (SP) ~ PSW;
PSW ~ OOOOH; SP ~ SP-2;
(SP) ~ IMASK1/WSA; IMASK1
POPA
1
IMASK1/WSA ~ (SP); SP ~ SP+2
PSW ~ (SP); SP ~ SP+2
j,JI
j,JI
j,JI
j,JI
j,JI
j,JI
IDLPD
1
IDLE MODE IF KEY = 1;
MODE IF KEY = 2;
CHIP AESET OTHEAWISE
-
-
-
-
-
-
~
OOH
POWEADOWt~
CMPL
2
D-A
j,JI
j,JI
j,JI
j,JI
i
-
BMOV
2
[PTA_HI] + ~ [PTA_LOW] + ;
UNTILCOUNT=O
-
-
-
-
-
-
NOTES:
1. If the mnemonic ends in "8" a byte operation is performed, otherwise a word operation is done. Operands D, 8 and A
must conform to the alignment rules for the required operand type. D and 8 are locations in the Register File; A can be
located anywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOU8LE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
10. The DJNZW instruction is not guaranteed to work.
14-64
intel~
9.0
8XC196KB QUICK REFERENCE
INSTRUCTION LENGTH/OPCODE
MNEMONIC
DIRECT
INDIRECT
IMMED
INDEXED
NORMAU1)
A-INC(1)
SHORT(1)
LONG(1)
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
AD DC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
4/44
4/48
3/64
3/68
3/A4
3/A8
3/88
4/54
4/58
3/74
3/78
3/B4
3/B8
3/98
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3/75
3/79
3/B5
3/B9
3/99
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
5/47
5/4B
4/67
4/6B
4/A7
4/AB
4/8B
5/57
5/5B
4/77
4/7B
4/B7
4/BB
4/9B
6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
5/77
5/7B
5/B7
5/BB
5/9B
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
3/7C
4/(2)
3/9C
6/(2)
5/40
5/(2)
4/60
5/(2)
4/80
5/(2)
4/50
4/(2)
3/70
4/(2)
3/90
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
6/(2)
5/4F
5/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
417F
5/(2)
4/9F
7/(2)
6/4F
6/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
5/7F
6/(2)
5/9F
AND (3-op)
AND (2-op)
OR (2-op)
XOR
AN DB (3-op)
ANDB (2-op)
ORB (2-op)
XORB
4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94
5/41
4/61
4/81
4/85
4/51
3/71
3/91
3/95
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
PUSH
POP
2/C8
2/CC
3/C9
2/CA
2/CE
2/CA
2/CE
3/CB
3/CF
4/CB
4/CF
-
I
14-65
intel~
9.0
8XC196KB QUICK REFERENCE
INSTRUCTION LENGTH/OPCODE (Continued)
MNEMONIC
LO
LOB
ST
STB
LOBSE
LBSZE
DIRECT
IMMED
3/AO
4/A1
3/BO
3/CO
INDIRECT
INDEXED
NORMAL
A-INC
SHORT
LONG
3/A2
3/A2
4/A3
5/A3
3/B1
3/B2
3/B2
4/B3
5/B3
-
3/C2
3/C2
4/C3
5/C3
3/C6
3/C6
4/C7
5/C7
3/BE
3/AE
3/BE
3/AE
4/BF
4/AF
5/BF
5/AF
3/C4
3/BC
3/BO
3/AC
3/AO
Mnemonic
Length/Opcode
Mnemonic
Length/Opcode
PUSHF
POPF
PUSHA
POPA
1/F2
1/F3
1/F4
1/F5
OJNZ
OJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB
3/EO
3/E1(4)
3/0F
3/0C
3/00
3/0E
3/08
3/18
3/09
3/19
3/0A
3/1A
CLRC
SETC
01
EI
CLRVT
NOP
RST
SKIP
10LPO
BMOV
1/F8
1/F9
TRAP
LCALL
SCALL
RET
LJMP
SJMP
BR[ 1
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
JE
JBC
JBS
1/F7
3/EF
2/28-2F(3)
1/FO
3/E7
2/20-27(3)
2/E3
1/00
1/08
1/01
1/09
1/02
1/0A
1/B3
1/08
1/04
1/0C
1/05
1/FA
1/FB
1/FC
1/FO
1/FF
2/00
1/F6
3/C1
1/00
1/06
1/0E
1/07
1/0F
3/30-37
3/38-3F
NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.
4. The DJNZW instruction is not guaranteed to work.
14-66
infel"
8XC196KB QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
MNEMONIC
DIRECT
IMMED
INDIRECT
INDEXED
NORMAL"
A-INC"
SHORT"
LONG"
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
5
5
4
4
4
4
4
5
5
4
4
4
4
4
6
6
5
5
5
5
5
5
5
4
4
4
4
4
7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
MUL (3-op)
MULU (3-op)
MUL(2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
16
14
16
14
26
24
12
10
12
10
18
16
17
15
17
15
27
25
12
10
12
10
18
16
18/21
16/19
18/21
16/19
28/31
26/29
14/17
12/15
14/17
12/15
20/23
18/21
19/22
17119
19/22
17119
29/32
27/30
15/18
12/16
15/18
13/15
21/24
19/22
19/22
17120
19/22
17/20
29/32
27/30
15/18
12/16
15/18
12/16
21/24
19/22
20/23
18/21
20/23
18/21
30/33
28/31
16/19
14/17
16/19
14/17
22/25
20/23
AND (3-op)
AND (2-op)
OR (2-op)
XOR
AN DB (3-op)
AN DB (2-op)
ORB (2-op)
XORB
5
4
4
4
5
4
4
4
6
5
5
5
5
4
4
4
7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
7/10
' 6/8
6/8
6/8
7110
6/8
6/8
6/8
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
4,4
4,4
4
4
5,4
4
4
5/8
5/8
5/8
5/8
6/8
6/9
6/8
6/8
6/9
6/9
6/96/9
7/10
7/10
7/10
7/10
10/13
11/13
12/15
14/16
11/14
12/14
13/16
15/17
LD, LOB
ST,STB
LDBSE
LDBZE
internal/internal: 6 + 8 per word
external/internal: 6 + 11 per word
external/ external: 6 + 14 per word
BMOV
PUSH (int stack)
POP (int stack)
PUSH (ext stack)
POP (ext stack)
6
8
8
11
7
9
-
9/12
10/12
11/14
13/15
10/13
11/13
12/15
14/16
"Times for operands as: SFRs and Internal RAM (O-1FFH)!.memory controller (200H-OFFFFH)
NOTE:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue; Internal stack is 200H-1 FFH and external stack is 200H-OFFFFH.
II
intel .
8XC196KBQUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES) (Continued)
MNEMONIC
PUSHF (int stack)
POPF (int stack)
PUSHA (int stack)
POPA (int stack)
TRAP (int stack)
LCALL (int stack)
SCALL (int stack)
RET (int stack)
MNEMONIC
12
12
PUSHF (ext stack)
POPF (ext stack)
PUSHA (ext stack)
POPA (ext stack)
8
10
18
18
16
11
11
11
TRAP (ext stack)
LCALL (ext stack)
SCALL (ext stack)
RET (ext stack)
18
13
13
14
OEC/OECB
EXT/EXTB
INC/INCB
3
4
3
6
7
CMPL
CLR/CLRB
NOT/NOTB
NEG/NEGB
7
3
3
3
WMP
SJMP
BR [indirect]
JNST, JST
JNH,JH
JGT, JLE
JNC,JC
JNVT, JVT
JNV, JV
JGE, JLT
JNE, JE
JBC,JBS
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
5/9 jump not taken/jump taken
OJNZ
OJNZW (Note 1)
5/9 jump not taken/jump taken
5/9 jump not taken/jump taken
NORML
SHRL
SHLL
SHRAL
SHR/SHRB
SHL/SHLB
SHRAISHRAB
8
CLRC
SETC
01
EI
CLRVT
NOP
RST
SKIP
10LPO
2
2
2
2
2
2
15 (includes fetch of configuration byte)
3
8/25 (proper key/improper key)
7
7
7
+ 1 per shift (9 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
NOTE:
1. The DJNZW instruction is not guaranteed to work.
14-68
intel"
11.0
8XC196KB QUICK REFERENCE
INTERRUPT TABLE
80C196KB Interrupt Priorities
Number
Source
Vector Location
Priority
INT15
NMI
203EH
15
INT14
HSI FIFO Full
203CH
14
INT13
EXTINT1
203AH
13
INT12
TIMER2 Overflow
2038H
12
INT11
TIMER2 Capture
2036H
11
INT10
4th Entry into HSI FIFO
2034H
10
INT09
RI
2032H
9
INT08
TI
2030H
8
SPECIAL
Unimplemented Opcode
2012H
N/A
SPECIAL
Trap
2010H
N/A
EXTINT
200EH
?
INTO?
INT06
Serial Port
200CH
6
INT05
Software Timer,
200AH
5
INT04
HSI.O Pin
2008H
4
INT03
High Speed Outputs
2006H
3
INT02
HSI Data Available
2004H
2
INT01
AID Conversion Complete
2002H
1
INTOO
Timer Overflow
2000H
0
14-69
inteL
8XC196KB QUICK REFERENCE
Interrupt Source
Interrupt Vector
NMI
NMI
Timer 2 Capture
Timer 2 Capture
HSI fIFO fourth Entry
HSI fIFO 4
RI flag
Receive
Serial Port
TI flag
Transmit
Unimplemented Opcode
Unimplemented Opcode
TRAP Instruction - - - - - - - - - - - - - - - - - - - - - Software Trap
IOC1.l
PO.7
P2.2
_____---'~I-------- EXTINT
-------~
....- - - - - - - - - - EXTINTl
Software Timer 0-3
Timer 2 Reset
Software Timer
AID Conversion Start
HSI.O
HSI.O Pin
HSO.0-HSO.5 - - - - - - - - - - - - - - - - - - High Speed Outputs
HSI fifO full
fifO full
9)_7_"_____
HSI Holding Reg. Loaded - - - ,
HSI Data Available
AID Conversion Complete
AID Conversion Complete
Timer 2 Overflow - - - - - -..~-------------- Timer 2 Overflow
Timer 1 Overflow
I
IOC1.3
Timer Overflow
IOC1.2
272111-29
14-70
intel"
12.0
S){C196KB QUICK REFERENCE
Clock Prescaler Off (IOC2.4 = 1)
FORMULAS
Convert Time: 91 States
Sample Time: 8 States
Baud Rate
Asynchronous Modes 1, 2 and 3:
BAUD_REG =
Baud Rate
or
2.00 ,...s
@
@
8 MHz
8 MHz
PWM_Control = 256 x Duty Cycle
or
PWM_Control
=
512
x
Duty Cycle
x8
State Time
Synchronous Mode 0:
BAUD_REG =
22.75,...s
=
Pulse Width lViodulation (PWM)
XTAL1
- 1
Baud Rate x 16
T2CLK
or
=
2
1 State Time = XTAL 1 = 2Tase
XTAL1
- 1
Baud Rate x 2
Signature Word and Voltage Levels
T2CLK
Description
Location
Value
AID Sample and Conversion Times
Signature Word
Programming Vcc
2070H
2072H
Clock Prescaler On (lOC2.4 = 0)
Programming Vpp
2073H
897CH
040H
(5.0V)
OA3H
(12.75V)
Baud Rate
Convert Time: 158 States = 26.33 ,...s
Sample Time: 15 States = 2.50
,...5 @
@
12 MHz
12 MHz
II
14-71
intel·
13.0
8XC196KB QUICK REFERENCE
RESET STATUS
Pin Name
Name
Multiplexed
Port Pins
Value of the
Pin on Reset
RESET
Mid-Sized Pullup
ALE
Weak Pull up
RD
Weak Pullup
BHE
Weak Pullup
WR
Weak Pull up
INST
Weak Pullup
EA
Undefined Input'
READY
Undefined Input'
NMI
Undefined Input"
BUSWIDTH
Undefined Input'
CLKOUT
Phase 2 of Clock
System 8us
P3.0-P4.7
Weak Pullup
ACHO-7
PO.0-PO.7
Undefined Input'
PORT1
P1.0-P1.7
Weak Pull ups
TXD
P2.0
Weak Pullup
RXD
P2.1
Undefined Input'
EXTINT
P2.2
Undefined Input'
T2CLK
P2.3
Undefined Input'
T2RST
P2.4
Undefined Input'
PWM
P2.5
Weak Pulldown
-
P2.6-P2.7
Weak Pullups
HSI0-HSI1
Undefined Input'
HSI2/HS04
Undefined Input'
HSI3/HS05
Undefined Input'
HSOO-HS03
Weak Pulldown
Register Name
AD
RESULT
HSI_STATUS
S8UF(RX)
INT_MASK
INT
PENDING
Value
7FFOH"
xOxOxOx08
OOH
000000008
OOOOOOOOB
TIMER1
OOOOH
TIMER2
OOOOH
IOPORT1
111111118
IOPORT2
11000001 B
SP_STAT/SP_CON
000010118
IMASK1
000000008
IPEND1
000000008
WSR
XXXXOOOOB
HSI_MODE
111111118
IOC2
XOOOOOO08
lOCO
000000X08
IOC1
PWM
001000018
CONTROL
OOH
IOPORT3
111111118
IOPORT4
111111118
10SO
000000008
IOS1
000000008
IOS2
000000008
NOTE:
'These pins must be driven and not left floating.
"The RESET value of AD_RESULT for devices with a
change indicator of "E", "F", and "G" is 7FCOH.
14-72
intel.
September 1992
8XC196KC
Quick Reference
III
Order Number: 272112-002
14-73
8XC196KC Quick Reference
CONTENTS
PAGE
CONTENTS
PAGE
1.0 MEMORY MAP .................... 14·75
7.0 OPCODE TABLE .................. 14·87
2.0 SFR MAP .......................... 14·75
8.0 INSTRUCTION SET SUMMARY ... 14·90
3.0 SFR BIT SUMMARy ............... 14·76
9.0 INSTRUCTION
LENGTH/OPCODE .................. 14·93
4.0 8XC196KC PIN DEFINITION
TABLE .............................. 14·81
10.0 INSTRUCTION EXECUTION TIMES
(IN STATE TIMES) .................. 14·95
5.0 PACKAGE PIN ASSiGNMENTS .... 14·83
11.0 INTERRUPT TABLE .............. 14·97
6.0 PIN DESCRIPTIONS ............... 14·85
12.0 FORMULAS ..................... 14·100
13.0 RESET STATUS ................. 14·101
14·74
intel®
1.0
8XC196KC QUICK REFERENCE
MEMORY MAP
OFFFFH
EXTERNAL MEMORY OR 110
6000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
20BOH
RESERVED
205EH
PTSVECTORS
2040H
UPPER INTERRUPT VECTORS
2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE
201BH
RESERVED
2014H
LOWER INTERRUPT VECTORS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY
200H
ADDITIONAL RAM
100H
REGISTER FILE AND
EXTERNAL PROGRAM MEMORY
NOTE:
Code executed in locations a to 1FFH will be forced external.
2.0
o
SFR MAP
19H
SP(HI)
19H
SP(HI)
19H
SP(HI)
19H
SP(HI)
19H
SP(HI)
lBH
SP(LO)
lBH
SP(LO)
lBH
SP(LO)
lBH
SP(LO)
lBH
SP(LO)
17H
IOS2
17H
PWMO_CONTROL
17H
PWMLCONTROL
17H
PWMO_CONTROL
17H
IOS2
16H
10Sl
16H
10Cl
16H
PWM1_CONTROL
16H
10Cl
16H
10Sl
15H
10SO
15H, lOCO
15H
RESERVED
15H
lOCO
15H
10SO
14H
WSR
14H
WSR
14H
WSR
14H
WSR
14H
WSR
13H
INT_MASKl
13H
INT_MASKl
13H
INT_MASKl
13H
INT_MASKl
13H
INT_MASKl
12H
INT_PENDl
12H
INT_PENDl
12H
INT_PENDl
12H
INT_PENDl
12H
INT_PENDl
llH
SP_STAT
llH
SP_CON
llH
RESERVED"
llH
SP_CON
llH
SP_STAT
10H
PORT2
10H
PORT2
10H
RESERVED"
10H
RESERVED
10H
RESERVED"
OFH
PORTl
OFH
PORTl
OFH
RESERVED"
OFH
RESERVED
OFH
RESERVED"
OEH
PORTO
OEH
BAUD_REG
OEH
RESERVED"
OEH
RESERVED
OEH
RESERVED"
ODH
TIMER2(HI)
ODH
TIMER2 (HI)
ODH
RESERVED"
ODH
T2CAPTURE (HI)
ODH
T2CAPTURE (HI)
OCH
TIMER2 (LO)
OCH
TIMER2 (LO)
OCH
IOC3'
OCH
T2CAPTURE (LO)
OCH
T2CAPTURE (LO)
OBH
TIMERl (HI)
OBH
IOC2
OBH
RESERVED"
OBH
IOC2
OBH
TIMERl (HI)
OAH
TIMERl (LO)
OAH
WATCHDOG
OAH
RESERVED"
OAH
WATCHDOG
OAH
TIMERl (LO)
09H
INT_PEND
09H
INT_PEND
09H
INT_PEND
09H
INT_PEND
09H
INT_PEND
OSH
INT_MASK
OSH
INT_MASK
OBH
INT_MASK
OSH
INT_MASK
OSH
INT_MASK
07H
SBUF(RX)
07H
SBUF(TX)
07H
PTSSRV(HI)
07H
SBUF (TX)
07H
SBUF(RX)
06H
HSI_STATUS
OSH
HSO_COMMAND
OSH
PTSSRV (LO)
OSH
HSO_COMMAND
OSH
HSI_STATUS
05H
HSLTIME (HI)
05H
HSO_TIME (HI)
05H
PTSSEL(HI)
05H
HSO_TIME (HI)
05H
HSI_TlME (HI)
04H
HSI_TIME (LO)
04H
HSO_TIME (LO)
04H
PTSSEL(LO)
04H
HSO_TlME (LO)
04H
HSI_TIME (LO)
03H
AD_RESULT (HI)
03H
HSI_MODE
03H
AD_TIME
03H
HSL_MODE
03H
AD_RESULT (HI)
02H
AD_RE;;ULT (LO)
02H
AD_COMMAND
02H
RESERVED"
02H
AD_COMMAND
02H
AD_RESULT (LO)
01H
ZERO_REG (HI)
01H
ZERO_REG (HI)
01H
ZERO_REG (HI)
01H
ZERO_REG (HI)
01H
ZERO_REG (HI)
OOH
ZERO_REG (LO)
OOH
ZERO_REG (LO)
OOH
ZERO_REG (LO)
OOH
ZERO_REG (LO)
OOH
ZERO_REG (LO)
HWINDOWO
when Read
HWINDOWO
when Written
HWINDOW 1
Read/Write
'Formerly labeled T2CONTROL or T2CNTC
"Reserved bytes must be written with zero.
14-75
HWINDOW 15
when Read
HWINDOW 15
when Written
II
int:el.
8XC196KC QUICK REFERENCE
8XC196KC CHIP CONFIGURATION BYTE
CCR (2018H: Byte)
-
7
5
6
I LOC1 I LOCO , IRC1
PD
3
4
2
'IRCO , ALE.'
WR
,
1
BWO
,
0
PD
I
1 = Powerdown mode enabled
Powerdown mode disabled
1 = Buswidth is BUSWIDTH pin controlled
BWO
o = Buswidth is 8-bit
1 = WR/BHE
WR
0= WRLlWRH
1 = ALE
ALE
0= ADV
IRCO, 1 READY control. (see Table below)
LOCO,1 ROM, EPROM Protection. (see Table below)
IRC1
IRCO
0
0
o=
LOC1
LOCO
Function
1 Wait State
Max Walt States
0
0
Read and Write Protected
0
1
2 Wait States
0
1
Read Protected Only
1
0
3 Wait States
1
0
Write Protected Only
1
1
READY Pin Controlled
1
1
No Protection
3.0 SFR BIT SUMMARY
HSI_MODE
I7
6
I5
4
I3
(03H HWINO Write)
(03H HWIN15 Read)
2
HSI_STATUS
I1 I0 I
L
(06H HWINO Read)
(06H HWIN15 Write)
HSI.O MODE
HSI.1 MODE
HSI.2 MODE
HSI.3 MODE
L - - - - - - - H S I . 2 STATUS
WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
11
.......- - - - - - - - H S I . 3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURRED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)
272112-2
272112-1
14·76
intel®
8XC196KC QUICK REFERENCE
AD_TIME
(03H HWINI R/W)
AD_COMMAND
(02H HWINO Write)
(02H HWIN15 Read)
o
CHANNEL NUMBER
0 \0 7
=
CONVERSION TIME (CON V)
CONY = 2 \0 31
3
"GO" BIT
0= HSO STARTS
1 = START IMMEDIATELY
4
5
SAMPLE TIME (SAM)
SAM = 1 to 7
272112-3
6
RSV'
7
RSV'
'RSV - RESERVED BITS MUST BE WRITTEN AS 0
272112-4
AD_RESULT (HI)
-o
(03H HWINO Read)
(03H HWIN15 Write)
AD_RESULT (LO)
-
1
(02H HWINO Read)
(02H HWIN15 Write)
:
}CHANNEL NUMBER
3
"READY" BiT
4
RSV'
5
RSV'
:
} Z LSB RESULT OF 10-BIT CONVERSION
2
3
-
""'o-=-A/-D-·-,.-ID-L-E--.
8-BIT AID RESULT AND
BYTE
OF 10-BIT CONVERSION
>- MOST SIGNIFICANT
4
-5
-6
-7
-
1 = AID is BUSY
MOST SIGNIFICANT BIT
'RSV - RESERVED BITS MUST BE WRITTEN AS 0
272112-5
272112-6
HSO_COMMAND
o
Z
3
(06H HWINO Write)
(06H HWIN15 Read)
CHANNEL NUMBER:
0-5: HSO.O TO HSO.5 INDIVIDUALLY
6:
HSO.O AND HSO.l
7:
HSO.Z AND HSO.3
8-B: SOFTWARE TIMERS
C:
HSO.O TO HSO.5 SIMULTANEOUSLY
D:
RESERVED
E:
RESET TIMERZ
F:
START AID CONVERSION
0= NO INTERRUPT
1 = INTERRUPT
4
5
6
CLEAR BIT
1----., 0=
1 = SET BIT
0= TIMER 1
1 = TlMER2
272112-7
14-77
8XC196KC QUICK REFERENCE
10SO
(15H HWINO Read)
(15H HWIN15 Write)
lOCO
(15H HWINO Write)
(15H HWIN15 Read)
HSO.O CURRENT STATE
HSI.O INPUT ENABLE / DISABLE
HSO.1 CURRENT STATE
TIMER 2 RESET EACH WRITE
HSO.2 CURRENT STATE
HSI.1 INPUT ENABLE / DISABLE
HSO.3 CURRENT STATE
TIMER 2 EXTERNAL RESET ENABLE / DISABLE
HSO.4 CURRENT STATE
HSI.2 INPUT ENABLE / DISABLE
HSO.5 CURRENT STATE
TIMER 2 RESET SOURCE HSI.O / T2RST
CAM OR HOLDING REGISTER IS FULL
HSI.3 INPUT ENABLE / DISABLE
HSO HOLDING REGISTER IS FULL
TIMER 2 CLOCK SOURCE HSI.1 / T2CLK
272112-8
10Sl
272112-9
(16H HWINO Read)
(16H HWIN15 Write)
10Cl
o
SOFTWARE TIMER 0 EXPIRED
7
(16H HWINO Write)
(16H HWIN15 Read)
SELECT PWM / SELECT P2.5
SOFTWARE TIMER 1 EXPIRED
EXTERNAL INTERRUPT ACH7 / EXTINT
SOFTWARE TIMER 2 EXPIRED
TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE
SOFTWARE TIMER 3 EXPIRED
TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE
TIMER 2 HAS OVERFLOW
HSO.4 OUTPUT ENABLE / DISABLE
TIMER 1 HAS OVERFLOW
SELECT TXD / SELECT P2.0
HSI FlrO IS FULL
HSO.5 OUTPUT ENABLE / DISABLE
HSI HOLDING REGISTER DATA AVAILABLE
HSI INTERRUPT
FlrO FU LL / '""HO"'L"""D"'N"'
I "'G'"'R"'E"'G"'IS"'T"'ER;:-;-LO"""A'"'D"'E""D
BITS 0-5 ARE CLEARED WHEN READ
272112-11
272112-10
IOS2
(17H HWINO Read)
(17H HWIN15 Write)
IOC2
(OBH HWINO Write)
(OBH HWIN15 Read)
INDICATES WHICH HSO EVENT OCCURRED
o
ENABLE FAST INCREMENT OF T2
HSO.O
ENABLE T2 AS UP/DOWN COUNTER
HSO.1
ENABLE /2 PRESCALER ON PWMs
HSO.2
ENABLE BOC 196KC A/DMODES
HSO.3
A/D CLOCK PRESCALER DISABLE
HSO.4
T2 ALTERNATE INTERRUPT @ BOOOH
HSO.5
ENABLE LOCKED CAM ENTRIES
T2RESET
CLEAR ENTIRE CAM'
START A/D
'THIS BIT ALWAYS READS AS 1
IOS2 IS CLEARED WHEN READ
272112-18
272112-19
14-78
int'eL
8XC196KC QUICK REFERENCE
BAUD_REG
SP_STAT
(OEH HWINO Write)
(11H HWINO Read)
(11H HWIN15 Write)
o
RSV'
RSV'
LSB
MSB
2
OE-- OVERRUN ERROR"
3
TXE -
4
FE - - FRAMING ERROR"
5
SBUF _ TX EMPTY
TI - - TRANSMIT INTERRUPT"
14
RI - - RECEIVE INTERRUPT"
15 0 = T2CLK (EXTERNAL) CLOCK SOURCE
1 = XTAL 1 (INTERNAL) CLOCK SOURCE
BAUD = BAUD RATE.
MUST WRITE BV AS 2 CONSECUTIVE
BYTES, LSB FIRST.
7
RECEIVED PARITY ERROR/
RECEIVED BIT B"
'RSV - RESERVED BITS MUST BE WRITTEN AS 0
"THESE BITS CLEARED WHEN READ
272112-15
272112-14
SBUF_RX
RPE/
RBB
(07H HWINO Read)
(07H HWIN15 Write)
WSR
(14H all windows R/W)
DO - LEADING DATA BIT
01
02
WI NDOW SELECT BITS
03
04
05
06
O=HOLD DISABLED
1= HOLD ENABLED
07
272112-17
272112-16
SBUF_ TX
-
0
DO - LEADING DATA BIT
1
01
2
02
-
3
-
4
-
--
o
04
05
6
06
-
07
M1
M2
03
5
7
SP_CON
(07H HWINO Write)
(07H HWIN15 Read)
00 =
01 =
10 =
11 =
(llHHWINOWrlte)
(llH HWIN15 Read)
MODE
MODE
MODE
MODE
0:
1:
2:
3:
SYNCHRONOUS
STANDARD ASYNC
9th BIT ENABLE
9th BIT DATA
2
PEN - 1 = PARITY ENABLED
3
REN - 1 = RECEIVE ENABLED
4
TBB -
5
RSV'
6
RSV'
7
RSV'
9th BIT FOR TRANSMISSION
'RSV - RESERVED BITS MUST BE WRITTEN AS 0
272112-12
272112-13
14-79
II
8XC196KC QUICK REFERENCE
INT_MASK
INT_PEND
I
7
EXT
INT
(OSH all windows R/W)
(09H all windows R/W)
INT_MASKI
INT_PENDI
I
I I I .. I I I I I
6
5
SER
PORT
SOFT
TIMER
HSI.O
PIN
3
2
I
0
HSO
PIN
HSI
DATA
AVAIL
A/D
DONE
TIMER
OVF
7
NMI'
(13H all windows R/W)
(12H all windows R/W)
I I I .. I I I I I
6
5
FIFO
FULL
EXT
INTI
T2
OVF
3
2
I
0
T2
CAP
HSI4
RI
TI
• NMI IS A RESERVED BIT, MUST BE WRITTEN AS O.
272112-21
272112-20
NOTE:
MASK and PEND bits share the same names
NOTE:
MASK and PEND bits share the same names
PTSSRV
PTSSEL
(06H: Word In HWINI Read/Write)
(04H: Word In HWINI Read/Write)
15
14
13
12
II
10
9
8
7
6
5
4
3
2
RSV'
FIFO
FULL
EXT
INTI
T2
OVF
T2
CAP
HSI
FIFO
FULL
RI
TI
EXT
INT
SER
PORT
SOFT
TIMER
HSI.l
PIN
HSO
PIN
HSI
DATA
0
A/D
DONE
TIMER
OVF
• RSV - RESERVED BIT MUST BE WRITTEN AS 0
272112-22
NOTE:
PTSSRV and PTSSEL bits share the same names
IOC3 (OCH HWINI READ/WRITE)
o
2
3
4
RSV'
5
RSV'
RSV'
7
RSV'
272112-27
NOTE:
°RSV-Reserved bits must be = 0
CLKOUT_DIS only available on C-step or later KC
14-80
infel .
4.0
8XC196KC QUICK REFERENCE
8XC196KC PIN DEFINITION TABLE
Pin Name
ACHO
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADV
AINC
ALE
ANGND
BHE
BREQ
BUSWIDTH
CPVER
CLKOUT
EA
EXTINT
HOLD
6BLPLCC
BOLQFP
BOLSQFP
6
5
7
4
11
18
17
19
16
24
23
20
21
2
1
80
78
17
16
18
15
22
21
19
20
80
79
78
10
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
62
42
62
12
41
30
64
77
76
74
73
72
71
70
69
68
67
66
65
4
61
4
25
60
46
Pin Name
77
76
75
74
32
48
46
45
37
HSI.1
HSI.2
HSI.3
HSO.O
HSO.1
HSO.2
HSO.3
HSO.4
HSO.5
INST
NMI
PO.O
25
26
27
28
29
34
35
26
27
63
3
6
5
7
4
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
23
58
44
4
47
5
12
26
BOLSQFP
47
39
40
PO.4
PO.5
PO.6
PO.7
P1.0
63
2
59
2
6
49
7
14
28,21
BOLQFP
31
24
PO.1
PO.2
PO.3
73
70
69
68
67
66
65
64
33
65
2
15,9
6BLPLCC
HLDA
HSI.O
P2.2
P2.3
P2.4
P2.5
P2.6
14-81
41
43
44
45
50
53
41
43
5
15
18
17
19
16
24
38
39
41
42
43
48
51
39
41
3
13
17
16
18
15
22
21
19
11
10
8
9
19
20
21
23
20
21
34
35
36
22
23
30
31
37
38
46
47
32
18
17
48
32
31
15
44
42
39
28
64
61
58
45
46
30
29
26
62
59
56
33
49
47
20
32
33
34
35
36
44
II
int:eL
8XC196KC QUICK REFERENCE
4.0 8XC196KC PIN DEFINITION TABLE (Continued)
68lPlCC
80lQFP
P2.7
38
57
55
P3.0
60
2
80
Pin Name
80lSQFP
68l PlCC
80lQFP
80lSQFP
PWMO
39
58
56
PWM1
22
37
35
Pin Name
P3.1
59
1
79
PWM2
23
38
36
P3.2
58
80
78
RD
61
3
1
P3.3
57
78
77
READY
43
62
60
P3.4
56
77
76
RESET
16
30
28
P3.5
55
76
75
RXD
17
31
29
P3.6
54
74
74
T2CAPTURE
38
57
55
P3.7
53
73
73
T2CLK
44
64
62
P4.0
52
72
70
T2RST
42
61
59
P4.1
51
71
69
T2UP-DN
33
49
47
P4.2
50
70
68
TXD
18
32
30
P4.3
49
69
67
Vee
1
P4.4
48
68
66
12,13,29,
52, 75
10,11,
27,50
P4.5
47
67
65
Vpp
37
56
54
64
VREF
13
26
24
Vss
P4.6
46
66
14,36,68 10,11,27, 8,9,25,
33,42,51, 31,40,49,
54,55,63, 52,53,61
79
P4.7
45
65
63
PACT
38
57
55
PALE
17
31
29
PMODE.O
11
24
22
WR
40
59
57
40
59
57
PMODE.1
10
23
21
WRL
PMODE.2
8
20
19
WRH
41
60
58
·67
'66
9
7
8
6
PMODE.3
9
21
20
XTAL1
PROG
15
28
26
XTAL2
PVER
18
32
30
14-82
infel~
8XC196KC QUICK REFERENCE
5.0 PACKAGE PIN ASSIGNMENTS
ACH5/PMOOE.l/PO.5
P3.0/ADO
ACH4/PMODE.O/PO.4
P3.1/ADI
ANGND
P3.2/AD2
VREF
P3.3/AD3
vss
P3.4/AD4
EXTINT/PROG/P2.2
P3.5/AD5
68-PIN PLCC
RESET
RXO!ffiE/P2.1
P3.6/AD6
P3.7/AD7
N8XC196KC, TN8XC196KC
TXD/PVER/P2.0
P4.0/ADS
P4.1/AD9
Pl.0
P4.2/AD10
PI.1
TOP VIEW
P1.2
PWMI/Pl.3
Looking Down on
PWM2/P1.4
Component Side
of PC Board
HSI.O
P4.3/ADII
P4.4/ADI2
P4.5/ADI3
P4.6/ADI4
P4.7/ADI5
HSI.l
P2.3/T2CLK
HSI.2/HSO.4
"'c:i
0
......
"!
:I:
III
:I:
iii
:I:
c:i
c:i
III III
:I:
,.,
Q.
"! ": ..; N
c:i c:i
III
Q.
Q.
Q.
LI.I
Q
Q!
...J
'"
Ii> 1":< I'aC> ~
>
a..
oJ"!
III
:::I:
...J
:::I:
III
:I:
La.I
U
......
Z
0
I
Q.
:::>
N
l-
:I:
". 'It
~D-~U1~~.
I: 1=; ~~
~ ~ ~
a..
~
....
0:
:::>
t
<
U
,..0
<
....
0:
<
I-
III
0:
~
N
I-
272112-24
68·Lead PLCC Package Diagram
14-83
•
8XC196KC QUICK REFERENCE
AD1/P3.1
ADO/P3.0
iD
P2.3/T2CLK
0
Vss
READY
ALE(i:.DV
61
INST
BHE/WRH
BUSWIDTH
WR!WRL
CLKOUT
XTAL2
P2.S/PWMO
SO-PIN QFP
XTALI
Vss
ACH3/PO.3
VSS
VSS
IiSO.3
Vee
NMI
P2.7/T2CAPTURE PACT
Vpp
SSXC196KC
VSS
Vee
EA
P2.4/T2RST!AiiiC
TOP VIEW
Lookl ng Down on
Component Side
of PC Board
ACH1/PO.l
vee
VSS
HSO.2
P2.6/T2UP-DN/CPVER
Pl.7/HOLD
ACHO/PO.O
Pl.6/HLDA
ACH2/PO.2
Pl.S/BREQ
ACH6/PMODE.2/PO.6
HSO.l·
CH7/EXTINT/PMODE.3/PO.7
HSO.O
N.C.
HSO.S/HSI.3
ACHS/PMODE.l/PO.S
Vss
HSO.4/HSI.2
ACH4/PMODE.O/PO.4
272112-25
80-Lead QFP Package Diagram
14-84
intel"
6.0
8XC196KC QUICK REFERENCE
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are three Vss pins, all of them must be connected.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
Vss·
Vpp
Programming voltage. Also timing pin for the return from power down circuit. Connect this pin
with a 1 J.IoF capacitor to Vss. If this function is not used, connect to Vee.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is
frequency. It has a 50% duty cycle.
RESET
Reset input and open-drain output. Hold low to reset the chip. The subsequent low-to-high
transition re-synchronizes CLKOUT and commences a 10-state-time sequence in which the
PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is
executed. Input high for normal operation. RESET has an internal pullup.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
% the oscillator
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCA. BHE = 0
selects the bank of memory that is connected to the high byte of the data bus. AO = 0 selects
the bank of memory that is connected to the low byte of the data bus. Thus accesses to a 16bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only (AO =
1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the pin will
go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only during 16bit external memory write cycles.
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is
low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the
next positive transition in CLKOUT occurs with READY high. When the external memory is not
being used, READY has no effect. Internal control of the number of wait states inserted into a
bus cycle (held not ready) is available through configuration of CCA.
14-85
II
8XC196KC QUICK REFERENCE
6.0
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
the SID in Slave Programming Mode.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.S. Two of them (HSO.4 and HSO.S) are shared with the HSI Unit.
PortO
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode.
Port 1
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR. 7.
BREQ
Bus Request output activated when the bus controller has a pending external memory cycle.
Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. The TxD function is
.enabled by setting IOC1.S. In mode 0 the pin is used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin functions as input or output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt. EXTINT is selected as
the external interrupt source by setting IOC1.1 high.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A riSing edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.3. T2RST is enabled as the reset source by clearing 10CO.S.
PWMO-2
Port 2.S can be enabled as a PWM output. The duty cycle of the PWM is determined by the
value loaded into the PWM-CONTROL registers.
T2UPDN
The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2
up/down function is enabled by setting IOC2.1.
T2CAP
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register (location
OCH in Window 1S).
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming Mode.
Used to indicate that Ports 3 and 4 contain a command/ address.
PROG·
Programming. Falling edge indicates valid data on PBUS and the beginning of programming.
Rising edge indicates end of programming.
PACT
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
PVER
Program Verification. Used in Slave Programming and Auto Programming Modes. Signal is
low after rising edge of PROG if the programming was not successful.
AINC
Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
14-86
intet
6.0
8XC196KC QUICK REFERENCE
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
PORT
3 and 4
(During
Programming)
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory.
CPVER
Cumulative Program Output Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.
7.0
00
01
02
03
04
05
06
07
OB
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
OPCODE TABLE
SKIP
CLR
NOT
NEG
XCH
DEC
EXT
INC
SHR
SHL
SHRA
XCH
SHRL
SHLL
SHRAL
NORML
RESERVED
CLRB
NOTB
NEGB
XCHB
DECB
EXTB
INCB
SHRB
SHLB
SHRAB
XCHB
RESERVED
RESERVED
RESERVED
RESERVED
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SCALL
SCALL
SCALL
SCALL
SCALL
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
43
44
45
46
47
4B
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
5B
59
SCALL
SCALL
SCALL
JBC
JBC
JBC
JBC
JBC
JBC
JBC
JBC
JBS
JBS
JBS
J8S
JBS
JBS
JBS
JBS
AND DIRECT (3 OPS)
AND IMMEDIATE (3 OPS)
AND INDIRECT (3 OPS)
AND INDEXED (3 OPS)
ADD DIRECT (3 OPS)
ADD IMMEDIATE (3 OPS)
ADD INDIRECT (3 OPS)
ADD INDEXED (3 OPS)
SUB DIRECT (3 OPS)
SUB IMMEDIATE (3 OPS)
SUB INDIRECT (3 OPS)
SUB INDEXED (3 OPS)
MULU DIRECT (3 OPS)
MULU IMMEDIATE (3 OPS)
MULU INDIRECT (3 OPS)
MULU INDEXED (3 OPS)
AN DB DIRECT (3 OPS)
ANDB IMMEDIATE (3 OPS)
ANDB INDIRECT (3 OPS)
ANDB INDEXED (3 OPS)
ADDB DIRECT (3 OPS)
ADDB IMMEDIATE (3 OPS)
ADDB INDIRECT (3 OPS)
ADDB INDEXED (3 OPS)
SUBB DIRECT (3 OPS)
SUBB IMMEDIATE (3 OPS)
14-87
5A
5B
5C
50
5E
5F
60
61
62
62
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
78
7C
70
7E
7F
80
81
82
83
84
85
86
SUBB INDIRECT (3 OPS)
SUBB INDEXED (3 OPS)
MULU8 DIRECT (3 OPS)
MULUB IMMEDIATE (3 OPS)
MULUB INDIRECT (3 OPS)
MULUB INDEXED (3 OPS)
AND DIRECT (2 OPS)
AND IMMEDIATE (2 OPS)
AND INDIRECT (2 OPS)
AND INDEXED (2 OPS)
ADD DIRECT (2 OPS)
ADD IMMEDIATE (2 OPS)
ADD INDIRECT (2 OPS)
ADD INDEXED (2 OPS)
SUB DIRECT (2 OPS)
SUB IMMEDIATE (2 OPS)
SUB INDIRECT (2 OPS)
SUB INDEXED (2 OPS)
MULU DIRECT (2 OPS)
MULU IMMEDIATE (2 OPS)
MULU INDIRECT (2 OPS)
MULU INDEXED (2 OPS)
ANDB DIRECT (2 OPS)
ANDB IMMEDIATE (2 OPS)
ANDB INDIRECT (2 OPS)
AN DB INDEXED (2 OPS)
AD DB DIRECT (2 OPS)
ADDB IMMEDIATE (2 OPS)
ADDB INDIRECT (2 OPS)
ADDB INDEXED (2 OPS)
SUBB DIRECT (2 OPS)
SUBB IMMEDIATE (2 OPS)
SUBB INDIRECT (2 OPS)
SUBB INDEXED (2 OPS)
MULUB DIRECT (2 OPS)
MULUB IMMEDIATE (2 OPS)
MULUB INDIRECT (2 OPS)
MULUB INDEXED (2 OPS)
OR DIRECT
OR IMMEDIATE
OR INDIRECT
OR INDEXED
XOR DIRECT
XOR IMMEDIATE
XOR INDIRECT
•
8XC196KC QUICK REFERENCE
7.0
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
OPCODE TABLE (Continued)
XOR INDEXED
CMPDIRECT
CMP IMMEDIATE
CMP INDIRECT
CMPINDEXED
DIVUDIRECT
DIVU IMMEDIATE
DIVU INDIRECT
DIVU INDEXED
ORB DIRECT
ORB IMMEDIATE
ORB INDIRECT
ORB INDEXED
XORBDIRECT
XORB IMMEDIATE
XORB INDIRECT
XORB INDEXED
CMPBDIRECT
CMPB IMMEDIATE
CMPB INDIRECT
CMPB INDEXED
DIVUB DIRECT
DIVUB IMMEDIATE
DIVUB INDIRECT
DIVUB INDEXED
LDDIRECT
LD IMMEDIATE
LDINDIRECT
LD INDEXED
AD DC DIRECT
ADDC IMMEDIATE
ADDC INDIRECT
ADDC INDEXED
SUBCDIRECT
SUBC IMMEDIATE
SUBC INDIRECT
SUBC INDEXED
LDBZE DIRECT
LDBZE IMMEDIATE
LDBZE INDIRECT
LDBZE INDEXED
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
D1
D2
D3
D4
D5
D6
D7
D8
LDBDIRECT
LDB IMMEDIATE
LDB INDIRECT
LDBINDEXED
ADDCB DIRECT
ADDCB IMMEDIATE
ADDCB INDIRECT
ADDCB INDEXED
SUBCB DIRECT
SUBCB IMMEDIATE
SUBCB INDIRECT
SUBCB INDEXED
LDBSE DIRECT
LDBSE IMMEDIATE
LDBSE INDIRECT
LDBSE INDEXED
STDIRECT
BMOV
STINDIRECT
STINDEXED
STBDIRECT
CMPL
STB INDIRECT
STB INDEXED
PUSH DIRECT
PUSH IMMEDIATE
PUSH INDIRECT
PUSH INDEXED
POP DIRECT
BMOVI
POP INDIRECT
POP INDEXED
JNST
JNH
JGT
JNC
JNVT
JNV
JGE
JNE
JST
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
JH
JLE
JC
JVT
JV
JLT
JE
DJNZ
DJNZW
TIJMP
BR (INDIRECT)
RESERVED
RESERVED
RESERVED
LJMP
RESERVED
RESERVED
RESERVED
RESERVED
DPTS
EPTS
RESERVED"
LCALL
RET
RESERVED
PUSHF
POPF
PUSHA
POPA
IDLPD
TRAP
CLRC
SETC
DI
EI
CLRVT
NOP
'DIV IDIVB/MULIMULB
RST
NOTE:
'Two Byte Instruction
RESERVED-Execution of RESERVED instructions will cause unimplemented opcode interrupt.
"Opcode EE is reserved, but it does not generate an unimplemented opcode interrupt.
14-88
inteL
8XC196KC QUICK REFERENCE
0
0
0
N
0
'"0
N
'"
....
on
0
0
....
on
0..
0..
'"0 ....0
..;
'" ..;.... uz uz
< < < < < < < <
.......
....... ....... ....... ....... ....... ....... .......
0
..; ..; ..; ..; ..; ..;
0..
Ro
0..
0..
0..
0..
0..
-
"
N
0
:! ~ ...J
IX)
en
e e 0 0 e e e e Nu
< < < ....
<
<
<
<
<
....... ....... ....... ....... ....... ....... ....... ....... .......
'"
... ... ... ...'" ....... ...on "'... ....... N'"
N
0
0..
0..
0..
0..
0..
0..
0..
0..
0..
en
>'"
READY
0
ALE/AoV
INST
P2.4/T2RST/AiNC
BHE!WRH
8USWIDTH
WR/WRL
CLKOUT
P2.5/PWM.O
80 PIN SQFP
XTAL2
P2. 7 /T2CAPTURE!PAcT
SB87C196KC
XTAL 1
Vpp
VSS
VSS
VSS
VSS
Vec
HSO.3
TOP VIEW
Vee
Vee
EA
VSS
NMI
HSO.2
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
N.C.
ACH3/PO.3
ACH1/PO.1
P2.S/T2UP-DN/CPVER
P1.7 /HOLD
P t.S/HLDA
ACHO/PO.O
P 1.5/8REQ
ACH2/PO.2
HSO.1
ACHS /PMODE. 2/PO. S
HSO.O
ACH7/PMODE.3/PO.7
HSI.3/HSO.5
on .... e
"...
.; .; zc.:> >0::.
0..
0..
Z
<
~ .......
0
c:i
0
::E
0..
c:i
0
::E
0..
....... .......
....
"'::t:
::t:
<
<
U
U
en
en N•
> ~ >
.......
~....
z
;:::
...
X
81 ...w.......N .......N
'" ...'"
!~....... .......>
0
Vl
0..
0..
en
en
>
0
N
•
-0..
0..
0..
0..
e
x
'"
e
x
~
"": "!
'"en
iii iii >
0: 0: iii
::t: ::t: ::t:
~ .......
N
~
~
0..
"!
~
.......
....
0
0..
::t:
~
Vl
....
272112-28
NOTE:
N.C. means No Connect (do not connect these pins).
aO·Pin SQFP Package
14-89 -
III
int'et
8.0
8XC196KC QUICK REFERENCE
INSTRUCTION SET SUMMARY
Mnemonic
Operands
Flags
Operation (Note 1)
Z
N
C
V
",
",
",
ADD/ADDB
2
D+-D+A
",
ADD/ADDB
3
D+-B+A
",
",
",
",
ADDC/ADDCB
2
D+-D+A+C
,t.
",
",
",
Notes
VT ST
t
t
t
t
t
t
t
-
SUB/SUBB
2
D+-D-A.
",
",
",
",
SUB/SUBB
3
D+-B-A
",
",
",
",
SUBC/SUBCB
2
D+-D-A+C-1
,t.
",
",
",
CMP/CMPB
2
D-A
",
",
",
",
MULIMULU
2
0,0 + 2 +- 0
-
-
-
-
-
-
2
MUUMULU
3
0,0 + 2 +- B
-
-
-
-
-
-
2
MULB/MULUB
2
0,0 +
-
-
-
-
-
-
3
MULB/MULUB
3
0,0 +
-
-
-
-
-
-
3
DIVU
2
2 +- remainder
-
-
",
2
2
1 +- remainder
-
-
-
",
-
3
DIV
2
2 +- remainder
-
-
-
",
DIVB
2
-
",
t
t
t
t
-
DIVUB
AND/ANDB
2
o +- (0,0 + 2) I A,D +
o +- (0,0 + 1) IA,D +
o +- (0,0 + 2) I A,D +
o +- (0,0 + 1) I A,D +
o +- DANDA
-
-
AND/ANDB
3
OR/ORB
2
XOR/XORB
xA
xA
1 +- 0 x A
1 +- B x A
-
-
-
-
",
",
0
0
-
D+- BANDA
",
",
0
0
-
-
D+- DORA
",
",
0
-
-
2
o +- 0 (ecxl. or) A
",
",
0
0
-
-
LD/LDB
2
D+-A
-
-
-
-
-
-
ST/STB
2
A+-D
-
-,
-
-
-
-
XCH/XCHB
2
D+-A,A+-D
-
-
-
-
-
-
LDBSE
2
-
-
-
-
-
-
3,4
2
o +- A; 0
o +- A; 0
+ 1 +- SIGN(A)
LDBZE
+ 1 +- 0
-
-
-
-
-
-
3,4
PUSH
1
SP +- SP - 2; (SP) +- A
-
-
-
-
-
-
POP
1
A +- (SP); SP + 2
-
-
-
-
-
-
PUSHF
0
SP +- SP - 2; (SP) +- PSW;
PSW +- OOOOH; I+-O
0
0
0
0
0
0
POPF
0
PSW +- (SP); SP +- SP + 2; I+-",
",
",
",
",
",
",
SJMP
1
PC +- PC + 11-bit offset
-
-
-
-
-
-
5
LJMP
1
PC +- PC + 16-bit offset
-
-
-
-
-
-
5
BR[indirect]
1
PC +- (A)
-
-
-
-
-
-
TIJMP
3
PC +- [A] + 2 • ([B] AND C)
-
-
-
-
-
-
SCALL
1
SP +- SP - 2;
(SP) +- PC; PC +- PC + 11-bit offset
-
-
-
-
-
-
5
LCALL
1
SP +- SP - 2; (SP) +- PC;
PC +- PC + 16-bit offset
-
-
-
-
-
-
5
1 +- remainder
14-90
0
-
intel~
8.0
8XC196KC QUICK REFERENCE
INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operands
Flags
Operation (Note 1)
Notes
Z
N C
V VT ST
RET
0
PC +- (SP); SP +- SP + 2
-
-
-
-
-
-
J (conditional)
1
PC +- PC + 8-bit offset (if taken)
-
-
-
-
-
-
5
JC
1
Jump if C = 1
-
-
-
- -
-
5
JNC
1
Jump ifC = 0
-
-
-
-
-
-
5
-
-
-
-
-
5
JE
1
Jump if Z = 1
-
JNE
1
Jump if Z = 0
-
5
-
5
JGE
1
Jump if N = 0
JLT
1
Jump if N = 1
- - - - - - - - - -
-
-
-
-
5
-
-
-
-
-
5
JGT
1
Jump if N = 0 and Z = 0
-
JLE
1
Jump if N = 1 or Z = 1
-
-
-
-
5
-
5
JH
1
Jump if C = 1 and Z= 0
JNH
1
Jump if C = 0 or Z = 1
- - - -
-
-
5
JV
1
Jump if V = 1
-
-
-
-
-
-
5
JNV
1
Jump if V = 0
-
-
-
-
-
-
5
JVT
1
Jump if VT= 1; Clear VT
-
-
-
-
0
-
5
JNVT
1
Jump if VT = 0; Clear VT
-
-
-
-
0
-
5
JST
1
Jump if ST = 1
-
5
JNST
1
Jump ifST = 0
- - - - - - - -
JBS
3
Jump if Specified Bit = 1
-
-
-
JBC
3
Jump if Specified Bit = 0
-
-
DJNZI
DJNZW
1
D +- D - 1;
If D 0 then PC +- PC + 8-bit offset
-
-
DEC/DECB
1
D+-D-1
~
NEG/NEGB
1
D+-O-D
INC/INCB
1
D+-D+1
EXT
1
EXTB
1
NOT/NOTB
1
CLR/CLRB
-
-
-
-
-
-
-
5,6
-
-
-
-
5,6
-
- -
-
5
~
~
~
-
~
~
~
~
~
~
~
~
t
t
t
D +- D; D + 2 +- Sign (D)
~
~
0
0
D +- D; D + 1 +- Sign (D)
~
~
0
0
D +- Logical Not (D)
~
~
0
1
D+-O
1
0
SHL/SHLB/SHLL
2
C +- msb - - - - - Isb +- 0
~
SHRISHRB/SHRL
2
o~
"*
msb - - - - - Isb
~
C
-
-
-
2
-
-
3
0
-
-
0
0
-
-
~
~
~
t
-
7
~
~
~
0
-
~
7
~
7
SHRAISHRAB/SHRAL
2
msb
~
~
0
-
~
SETC
0
C+-1
-
-
1 -
-
-
CLRC
0
C+-O
-
-
0
-
-
-
~
msb - - - - - Isb
14-91
~
C
5
•
8XC196KC QUICK REFERENCE
8.0
INSTRUCTION SET SUMMARY (Continued)
Mnemonic Operands
Flags
Operation (Note 1)
Z
CLRVT
AST
01
EI
a
a
a
a
VT -
a
PC -
2080H
-
-
-
-
-
-
-
-
- - - - - - - a -
-
-
-
Disable Allinterupts (I -
0)
Enable All Interupts (I -
1)
-
-
Disable all PTS Cycles (PSE = 0)
Enable all PTS Cycles (PSE = 1)
-
NOP
PC-PC+1
-
SKIP
1
PC-PC+2
-
Left shift till msb = 1; 0 SP SP - 2;
(SP) PC; PC -
shift count
ST
-
-
O.
2
Notes
VT
-
a
a
a
V
- - - a
a a a a a
OPTS
NORML
C
-
EPTS
TRAP
N
a
-
-
-
-
-
-
a a a a a
a
""- ""-
-
8
7
9
(2010H)
PUSHA
1
SP-2; (SP)· PSW;
SP PSW OOOOH; SP SP-2;
IMASK1/WSR; IMASK1 (SP) -
POPA
1
IMASK1/WSR (SP); SP PSW (SP);SP SP+2
IDLPD
1
IDLE MODE IF KEY = 1;
POWER DOWN MODE IF KEY = 2;
CHIP RESET OTHERWISE
-
CMPL
2
D-A
BMOV,
BMOVi
2
[PTA_HI) + UNTIL COUNT =
""- ""- ""- ""-
[PTR_LOW] + ;
a
OOH
SP+2
"" "" "" "" "" ""
-
- -
-
-
t
-
-
-
NOTES:
1.. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is done. Operands D, B and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can be
.
located anywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
14-92
int:et
9.0
8XC196KC QUICK REFERENCE
INSTRUCTION LENGTH/OPCODE
MNEMONIC
DIRECT
IMMED
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUB8 (3-op)
ADDB (2-op)
SUBB (2-op)
ADDC8
SUBCB
CMPB
4/44
4/48
3/64
3/68
3/A4
3/A8
3/88
4/54
4/58
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3174
3178
3175
3179
3/B4
3/B8
3/98
3/B5
3/B9
3/99
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
317C
4/(2)
3/9C
6/(2)
5/40
5/(2)
4/60
5f(2)
4/8D
5/(2)
4/50
4/(2)
AND (3-op)
AND (2-op)
OR (2-op)
XOR
ANDB (3-op)
AND8 (2-op) •
ORB (2-op)
XORB
PUSH
POP
INDIRECT
INDEXED
NORMAL(1)
A-INC(1)
SHORT(1)
LONG(1)
4/46
4/4A
3/66
3/SA
3/A6
3/AA
3/8A
4/56
4/5A
5/47
5/48
4/67
4/68
4/A7
4/A8
4/88
5/57
5/58
4/77
3/7A
3/86
3/BA
3/9A
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
4/B7
4/B8
4/98
6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
5/77
5/7B
5/B7
5/88
5/9B
4/(2)
3/9D
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
317E
4/(2)
3/9E
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
317E
4/(2)
3/9E
6/(2)
5/4F
5/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
4/7F
5/(2)
4/9F
7/(2)
6/4F
6/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
517F
6/(2)
5/9F
4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94
5/41
4/61
4/81
4/85
4/51
3/71
3/91
3/95
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
4/42
3/62
3/82
3/86
4/52 .
3/92
3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
2/C8
2/CC
3/C9
2/CA
2/CE
2/CA
2/CE
3/C8
3/CF
4/C8
4/CF
3170
-
3176
14-93
3172
4178
•
8XC196KC QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODE (Continued)
MNEMONIC
INDIRECT
INDEXED
DIRECT
IMMED
NORMAL
A·INC
SHORT
LONG
LO
3/AO
4/A1
3/A2
3/A2
4/A3
5/A3
LOB
3/BO
3/B1
3/B2
3/B2
4/B3
5/B3
ST
3/CO
3/C2
3/C2
4/C3
5/C3
STB
3/C4
3/C6
3/C6
4/C7
5/C7
XCH
3/04
-
-
4/0B
5/0B
5/1B
XCHB
3/14
-
-
-
4/1B
LOBSE
3/BC
3/BO
3/BE
3/BE
4/BF
5/BF
LBSZE
3/AC
3/AO
3/AE
3/AE
4/AF
5/AF
Mnemonic
Length/Opcode
Mnemonic
Length/Opcode
PUSHF
POPF
PUSHA
POPA
1/F2
1/F3
1/F4
1/F5
TRAP
LCALL
SCALL
RET
LJMP
SJMP
BR!]
TIJMP
1/F7
3/EF
2/2B-2F(3)
1/FO
3/E7
2/20-27(3)
2/E3
4/E2
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
1/00
1/0B
1/01
1/09
1/02
1/0A
1/B3
1/0B
1/04
1/0C
1/05
1/00
1/06
1/0E
1/07
JE
JBC
JBS
OJNZ
OJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB
1/0F
3/30-37
3/3B-3F
3/EO
3/E1
3/0F
3/0C
3/00
3/0E
3/0B
3/1B
3/09
3/19
3/0A
3/1A
CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
BMOV
BMOVi
1/FB
1/F9
1/FA
1/FB
1/EC
1/EO
1/FC
1/FO
1/FF
2/00
1/F6
3/C1
3/CO
NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.
14-94
intet
10.0
8XC196KC QUICK REFERENCE
INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
MNEMONIC
INDIRECT
INDEXED
DIRECT
IMMED
NORMAL'
A·INC·
SHORT'
LONG'
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
5
5
4
4
4
4
4
5
5
4
4
4
4
4
6
6
5
5
5
5
5
5
5
4
4
4
4
4
7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
16
14
16
14
26
24
12
10
12
10
18
16
17
15
17
15
27
25
12
10
12
10
18
16
18/21
16/19
18/21
16/19
28/31
26/29
14/17
12/15
14/17
12/15
20/23
18/21
19/22
17/19
19/22
17/19
29/32
27/30
15/18
12/16
15/18
13/15
21/24
19/22
19/22
17/20
19/22
17/20
29/32
27/30
15/18
12/16
15/18
12/16
21/24
19/22
20/23
18/21
20/23
18/21
30/33
28/31
16/19
14/17
16/19
14/17
22/25
20/23
AND (3-op)
AND (2-op)
OR (2-op)
XOR
ANDB (3-op)
AN DB (2-op)
ORB (2-op)
XORB
5
4
4
4
5
4
4
4
6
5
5
5
5
4
4
4
7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
LD, LOB
ST, STB
XCH,XCHB
LDBSE
LDBZE
4,4
4,4
5,5
4
4
5,4
5/8
5/8
5/8
5/8
6/8
6/9
6/8
6/8
6/9
6/9
8/13
6/9
6/9
7/10
7/10
9/14
7/10
7/10
4
4
BMOV
6 + 8 per word + 3 for each memory controller reference
BMOVi
7+8 per word
+ 14 for each interrupt + 3 for each memory controller reference
PUSH (int stack)
POP (int stack)
PUSH (ext stack)
POP (ext stack)
6
8
8
11
7
9
-
9/12
10/12
11/14
13/15
10/13
11/13
12/15
14/16
10/13
11/13
12/15
14/16
11/14
12/14
13/16
15/17
'Times for operands addressed as SFRs and internal RAM (0-1 FFH)/memory controller references (200-0FFFFH)).
NOTES:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue.
2. INT stack is 0-IFFH and EXT stack is 200-0FFFFH.
14-95
•
8XC196KC QUICK REFERENCE
10.0
INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
PUSHF (int stack)
POPF (int stack)
PUSHA (int stack)
POPA (int stack)
TRAP (int stack)
LCALL (int stack)
SCALL (int stack)
RET (int stack)
(Continued)
MNEMONIC
MNEMONIC
6
7
12
12
16
11
11
11
CMPL
CLR/CLRB
NOTINOTB
NEG/NEGB
7
3
3
3
PUSHF (ext stack)
POPF (ext stack)
PUSHA (ext stack)
POPA (ext stack)
8
10
18
18
TRAP (ext stack)
LCALL (ext stack)
SCALL (ext stack)
RET (ext stack)
18
13
13
14
OEC/OECB
EXT/EXTB
INC/INCB
3
4
3
LJMP
SJMP
BR [indirect]
TIJMP
JNST. JST
JNH. JH
JGT. JLE
JNC. JC
JNVT. JVT
JNV.JV
JGE. JLT
JNE. JE
JBC.JBS
7
7
7
OJNZ
OJNZW
5/9 jump not taken/jump taken
6/10 jump not taken/jump taken
NORML
SHRL
SHLL
SHRAL
SHR/SHRB
SHL/SHLB
SHRAISHRAB
8
CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
2
2
2
2
2
2
2
2
20 (includes fetch of configuration byte)
3
8/25 (proper key/improper key)
15 + 3 for each memory controller reference
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
5/9 jump not taken/jump taken
+ 1 per shift (9 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
14-96
intel·
8XC196KC QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
(Continued)
PTSCYCLES
18 (+ 3 for each memory controller reference)
13 (+ 7 for each transfer, 1 minimum
+ 3 for each memory controller reference)
21
25
12 ( + 10 for each transfer, 1 minimum)
16 (+ 10 for each transfer, 1 minimum)
11 (+ 10 for each transfer, 1 minimum)
15 (+ 11 for each transfer, 1 minimum)
Single Transfer
Block Transfer
AID Mode (SFRs/internal RAM)
(MEMORY CONT)
HSI MODE (SFRs/internal RAM)
(MEMORY CONT)
HSO MODE (SFRs/internal RAM)
(MEMORY CONT)
11.0
INTERRUPT TABLE
80C196KC Interrupt Priorities
Number
Source
PTS Vector Table
INT15
NMI
203EH
15
N/A
PTS
Table
(1,2)
INT14
HSI FIFO Full
203CH
14
INT13
EXTINT1
203AH
13
INT12
TIMER2 Overflow
2038H
12
INT11
TIMER2 Capture
2036H
11
INT10
4th Entry into HSI FIFO
2034H
10
INT09
RI
2032H
9
INT08
TI
2030H
8
2012H
N/A
SPECIAL Unimplemented
Opcode
SPECIAL Trap
2010H
N/A
INT07
200EH
7
EXTINT
PTS Vector
Vector
Priority
Location
Location
HSI FIFO Full
205CH
EXTINT1
205AH
TIMER2 Overflow
2058H
TIMER2 Capture
2056H
4th HSI FIFO Entry
2054H
RI
2052H
TI
2050H
EXTINT
204EH
Serial Port
204CH
Software Timer
204AH
HSI.O Pin
2048H
High Speed Outputs
2046H
HSI Data Available
2044H
AID Conversion Complete
2042H
Timer Overflow
2040H
INT06
Serial Port
200CH
6
INT05
Software Timer
200AH
5
INT04.
HSI.O Pin
2008H
4
NOTES:
1. PTS interrupts have higher priority than all other inter-
INT03
High Speed Outputs
2006H
3
rupts except NMI.
2. PTS priorities are in the same order as conventional interrupts.
INT02
HSI Data Available
2004H
2
INT01
AID Conversion
Complete
2002H
1
INTOO
Timer Overflow
2000H
0
14-97
intel~
8XC196KC QUICK REFERENCE
11.0
(Continued)
INTERRUPT TABLE
PTS Control Blocks
PTSVEC --+
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
PTSBLOCK
UNUSED
PTSBLOCK
PTSBLOCK
UNUSED
PTSDST(HI)
PTSDST(HI)
REG (HI)
UNUSED
PTSDST(LO)
PTSDST(LO)
REG (LO)
UNUSED
UNUSED
PTSSRC(HI)
PTSSRC(HI)
SID (HI)
PTSSRC(HI)
PTSDEST (HI)
PTSSRC(LO)
PTSSRC(LO)
SID (LO)
PTSSRC(LO)
PTSDEST (LO)
PTSCON
PTSCON
PTSCON
PTSCON
PTSCON
PTSCOUNT
PTSCOUNT
PTSCOUNT
PTSCOUNT
PTSCOUNT
Single
Transfer
Block
Transfer
AID Mode
HSOMode
HSI Mode
14·98
intel~
8XC196KC QUICK REFERENCE
11.0
(Continued)
INTERRUPT TABLE
80C196KC Interrupt Sources
Interrupt Source
Interrupt Vector
NMI .................................................................................. NMI
Timer 2 Capture _ ................................................................................-
HSI FIFO Fourth Entry _ ................................................................................-
Timer 2 Capture
HSI FIFO"
RI Flag - ............................1~~
................................................ Receive
0 - - - - - - - -......
TI Flag - ............................-4-~
............................................-
Unimplemented Opcode _ ................................................................................-
TRAP Instruction - ................................~I-:O-:C"':"l-.l~................................-
PO.7
---------'-~tl----------
P2.2 ............................ ...............................................-
D>-.. . . . . . . . . . . . . .
Software Timer 0-3 ~
Timer 2 Reset
AID Conversion Start
Serial Port
Transmit
Unimplemented Code
Software Trap
EXTINT
EXTINT 1
Software Timer
HSI.O .................................................................................. HSI.O Pin
HSO.O-HSO.5 ....................................................................................- High Speed Outputs
HSI FIFO Full ............................~I-............................................-
~ol1.1_7
FIFO Full
....................................-
HSI Holding Reg. Loaded - - - - . ,
_
•
HSI Data Available
AID Conversion Complete ....................................................................................- AID Conversion Complete
Timer 2 Overflow - .......................
~
........................................................-
~
IOC1.3
Timer 1 Overflow - - - ,
Timer 2 Overflow
~ Timer Overflow
_
IOC1.2
272112-26
14-99
int:eL
8XC196KC QUICK REFERENCE
12.0 FORMULAS
Conversion time, p.s
Sample time, p.s
Value loaded into AD_TIME bits 5, 6, 7.
Must equal 1 through 7
Value loaded into AD_TIME bits 0-5.
Must equal 2 through 31
Processor frequency, MHz
8 for 8-bit conversion
10 for lO-bit conversion
TeONV
TSAMP
Baud Rate
SAM
Asynchronous Modes 1, 2 and 3:
CONV
BAUD_REG =
XTAL 1
- 1
Baud Rate. 16
XTALI
B
T2CLK
Baud Rate. a
or
Pulse WIdth Modulation (PWM)
Synchronous Mode 0:
BAUD REG =
XTAL1
- 1
Baud Rate. 2
T2CLK
Baud Rate
or
B
PWM_CONTROL = 256 • duty cycle or
PWM_CONTROL = 512. duty cycle
State Time
2
1 STATE TIME = XTAL1 = 2 Tose
AID Conversion
1O-Bit value = INT [1023 • (VIN - ANGND)]
(VREF - ANGND)
Signature Word and Voltage Levels
a-Bit value = INT [255 • (VIN - ANGND)]
(VREF - ANGND)
Description
Location
Value
Signature Word
Programming VCC
70H
72H
Programming Vpp
73H
879CH
040H
5.0V
OAOH
12.50V
SAM = (TSAM • Fosel - 2
a
TSAM = (a. SAM)
+2
Fose
CONY = (TeONV • Fosel
2xB
TeoNV =
+3
(2. B'. CONY) - 3
F
ose
14-100
infel·
8XC196KC QUICK REFERENCE
13.0 RESET STATUS
SFR Reset Status
Register Name
Value
AD_RESULT
7FFOH
AD_TIME
OFFH
HSI_STATUS
XOXOXOXOB
SBUF(RX)
OOH
INT_MASK
OOOOOOOOB
INT_PENDING
OOOOOOOOB
TIMER1
OOOOH
TIMER2
OOOOH
IOPORT1
11111111B
IOPORT2
11000001B
SP_STAT /SP_CON
00001011B
IMASK1
OOOOOOOOB
IPEND1
OOOOOOOOB
WSR
XXXXOOOOB
HSI_MODE
11111111B
IOC2
XOOOOOOOB
lOCO
OOOOOOXOB
IOC1
·00100001B
PWM_CONTROL8
OOH
IOPORT3
11111111B
IOPORT4
11111111B
1080
OOOOOOOOB
1081
OOOOOOOOB
1082
OOOOOOOOB
IOC3·
11110010B
NOTE:
·Was previously called T2CONTROL or T2CNTC.
14-101
intel..
8XC196KC QUICK REFERENCE
8XC196KC Pin Reset Stats
Pin Name
Multiplexed
Port Pins
Pin Status
during Reset
Pin Status
after Reset
ACHO-ACH?
PO.O-PO.?
Undefined Inputs(l)
Undefined Inputs(l)
PORT1
P1.0-P1.?
Weak Pull-Ups (IlL Spec)
Weak Pull-Ups (IlL Spec)
TXD
P2.0
Strong Pull-Up (ILIl Spec)
Strongly Driven
RXD
P2.1
Undefined Input(3)
Undefined Input(3)
EXTINT
P2.2
Undefined Input(3)
Undefined Input(3)
T2CLK
P2.3
Undefined Input(3)
Undefined Input(3)
T2RST
P2.4
Undefinedlnput(3)
Undefined Input(3)
PWMO
P2.5
Medium Pull-Down
Strongly Driven
-
P2.6-P2.7
Weak Pull-Ups
Weak Pull-Ups
ADO-AD15
P3.0-P4.7
Weak Pull-Ups
Address/Data Bus or
Open-Drain 1/0(2)
HSLO, HSL1
-
Undefined Input(3)
Undefinedlnput(3)
Undefined Input(3)
Undefined Input(3)
Undefined Input(3)
Undefined Input(3)
HSL2/HSO.4
HSL3/HSO.5
HSO.0-HSO.3
ALE
BHE
BUSWIDTH
CLKOUT
EA
INST
NMI
RD
READY
RESET
WR
\
Weak Pull-Down
Weak Pull-Down
Weak Pull-Up
Strongly Driven
Weak Pull-Up
Strongly Driven
Undefined Input(3)
Undefined Input(3)
CLKOUT (Strongly Driven)
CLKOUT (Strongly Driven)
Undefined Input(3)
Undefined Input(3)
Weak Pull-Down
Strongly Driven
Weak Pull-Down (lIHl Spec)
Weak Pull-Down (IIHI Spec)
Weak Pull-Up
Strongly Driven
Undefined Input(3)
Undefined Input(3)
Medium Pull-Up (RRST Spec)
Medium Pull-Up (RRST Spec)
Weak Pull-Up
Strongly Driven
NOTES:
1. These pins are allowed to float. However, it is recommended that unused pins be tied high or low.
2'. The state of these pins depends on device configuration. If the address/data bus is active, the pins act as a strongly
driven bus; otherwise, they act as an open-drain I/O port and are left floating.
3. These pins must be driven and not left floating. Input voltage must not exceed Vcc during power-up.
4. Consult the 8XC196KC/KD data sheet for specifications.
14-102
8XC196KC QUICK REFERENCE
8XC196KC Pin Status Descriptions
Pin Status
Approximate Value
Weak Pull-Up
70/J-A
Medium Pull-Up
1 mA
Strong Pull-Up
12'mA
Weak Pull-Down
200/J-A
Medium Pull-Down
1 mA
Strongly Driven High
See VOH Specification
Strongly Driven Low
See VOL Specification
NOTE:
These typical maximum values are approximate; they are
provided for reference only and are not guaranteed.
III
14-103
intel.
October 1992
8XC196KD
Quick Reference
Order Number: 272265-001
14-104
8XC196KD Quick Reference
CONTENTS
PAGE
CONTENTS
PAGE
1.0 MEMORY MAP ................... 14·106
7.0 OPCODE TABLE ................. 14·119
2.0 SFR MAP ......................... 14·106
a.o INSTRUCTION SET SUMMARY .. 14·121
3.0 SFR BIT SUMMARy .............. 14·107
9.0 INSTRUCTION
LENGTH/OPCODE ................. 14·124
4.0 aXC196KD PIN DEFINITION
TABLE ............................. 14·112
10.0 INSTRUCTION EXECUTION TIMES
(IN STATE TIMES) ................. 14·126
5.0 PACKAGE PIN ASSIGNMENTS .. 14·114
11.0 INTERRUPT TABLE ............. 14·128
6.0 PIN DESCRiPTIONS .............. 14-117
12.0 FORMULAS ..................... 14·130
13.0 RESET STATUS .......,.......... 14-131
III
14·105
intel~
8XC196KD QUICK REFERENCE
1.0 MEMORY MAP
OFFFFH
EXTERNAL MEMORY OR I/O
AOOOH
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
20BOH
RESERVED
20SEH
PTSVECTORS
2040H
UPPER INTERRUPT VECTORS
2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE
201BH
RESERVED
2014H
LOWER INTERRUPT VECTORS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY
400H
ADDITIONAL RAM
100H
REGISTER FILE AND
EXTERNAL PROGRAM MEMORY
o
NOTE:
Code executed in locations 0 to 1FFH will be forced external.
2.0 SFR MAP
19H
SP(HI)
19H
SP(HI)
19H
SP(HI)
19H
SP(HI)
19H
SP(HI)
lBH
SP(LO)
lBH
SP(LO)
lBH
SP(LO)
lBH
SP(LO)
lBH
SP(LO)
17H
IOS2
17H
PWMO_CONTROL
17H
PWM2_CONTROL
17H
PWMO_CONTROL
17H
IOS2
16H
10Sl
16H
10Cl
16H
PWM1_CONTROL
16H
10Cl
16H
10Sl
15H
10SO
lSH
lOCO
lSH
RESERVED
lSH
lOCO
lSH
10SO
14H
WSR
14H
WSR
14H
WSR
14H
WSR
14H
WSR
13H
INT_MASKl
13H
INT_MASKl
13H
INT_MASKl
13H
INT_MASKl
13H
INT_MASKl
12H
INT_PENDl
12H
INT_PENDl
12H
INT_PENDl
12H
INT_PENDl
12H
INTJENDl
llH
SP_STAT
llH
SP_CON
llH
RESERVED"
llH
SP_CON
llH
SP_STAT
10H
PORT2
10H
PORT2
10H
RESERVED"
10H
RESERVED
10H
RESERVED"
OFH
PORTl
OFH
PORT1
OFH
RESERVED"
OFH
RESERVED
OFH
RESERVED"
OEH
PORTO
OEH
BAUD_REG
OEH
RESERVED"
OEH
RESERVED
OEH
RESERVED"
ODH
TIMER2 (HI)
ODH
TIMER2(HI)
ODH
RESERVED"
ODH
T2CAPTURE (HI)
ODH
T2CAPTURE (HI)
OCH
TIMER2 (LO)
OCH
TIMER2(LO)
OCH
IOC3'
OCH
T2CAPTURE (LO)
OCH
T2CAPTURE (LO)
OBH
TIMERl (HI)
OBH
IOC2
OBH
RESERVED"
OBH
IOC2
OBH
TIMERl (HI)
OAH
TIMERl (LO)
OAH
WATCHDOG
OAH
RESERVED"
OAH
WATCHDOG
OAH
TIMERl (LO)
09H
INT_PEND
09H
INT_PEND
09H
INT_PEND
09H
INT_PEND
09H
INT_PEND
OBH
INT_MASK
08H
INT_MASK
OBH
INT_MASK
OBH
INT_MASK
OBH
INT_MASK
07H
SBUF(RX)
07H
SBUF(TX)
07H
PTSSRV(HI)
07H
SBUF(TX)
07H
SBUF(RX)
06H
HSI_STATUS
06H
HSO_COMMAND
06H
PTSSRV(LO)
06H
HSO_COMMAND
06H
HSI_STATUS
OSH
HSI_TIME (HI)
OSH
HSO_TIME (HI)
OSH
PTSSEL(HI)
OSH
HSO_TIME (HI)
OSH
HSI_TIME(HI)
04H
HSI_TIME (LO)
04H
HSO_TIME (LO)
04H
PTSSEL(LO)
04H
HSO_TIME (LO)
04H
HSI_TIME (LO)
03H
AD_RESULT (HI)
03H
HSI_MODE
03H
AD_TIME
03H
HSI_MODE
03H
AD_RESULT (HI)
02H
AD
COMMAND
02H
AD
01H
ZERO_REG (HI)
01H
ZERO_REG (HI)
OOH
ZERO_REG (LO)
DOH
ZERO_REG (LO)
02H
AD_RESULT (LO)
02H
AD_COMMAND
02H
RESERVED"
01H
ZERO_REG (HI)
01H
ZERO_REG (HI)
01H
ZERO
OOH
ZERO_REG (LO)
OOH
ZERO_REG (LO)
OOH
ZERO_REG (LO)
HWINDOWO
when Read
HWINDOWO
when Written
REG (HI)
HWINDOW1
Read/Write
"Formerly labeled T2CONTROL or T2CNTC
""Reserved bytes must be written with zero:
14-106
HWINDOW15
when Read
RESULT (LO)
HWINDOW15
when Written
int:el.,
8XC196KD QUICK REFERENCE
8XC196KD CHIP CONFIGURATION BYTE
CCR (2018H: Byte)
7
6
5
PO
o
432
I LOC1 I LOCO I IRC1 I IRCO I ALE I WR
BWO
PO
1 = Powerdown mode enabled
Powerdown mode disabled
BWO
1 = Buswidth is BUSWIDTH pin controlled
o = Buswidth is B·bit
WR
1 = WR/BHE
0= WRL/WRH
ALE
1 = ALE
0= ADV
IRCO, 1 READY control. (see Table below)
LOCO, 1 ROM, EPROM Protection. (see Table below)
3.0
IRC1
IRCO
0
0
o=
LOC1
LOCO
Function
1 Wait State
0
0
Read and Write Protected
Max Wait States
0
1
2 Wait States
0
1
Read Protected Only
1
0
3 Wait States
1
0
Write Protected Only
1
1
READY Pin Controlled
1
1
No Protection
SFR BIT SUMMARY
HSI-MODE
(03H HWINO Write)
(03H HWIN15 Read)
HSLSTATUS
I 7 I 6 15
4
(06H HWINO Read)
(06H HWIN15 Write)
13 2111 0 I
L
1-_ _ _ _ _ _ HSI.2 MODE
HSI.O STATUS
HSl.l STATUS
1-_ _ _...,...._ _ _ _ HSI.3 MODE
HSI.2 STATUS
WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
11
HSI.3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURRED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
272265-2
8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)
272265-1
14-107
II
8XC196KD QUICK REFERENCE
AD_TIME
(03H HWINI R/W)
AD_COMMAND
(02H HWINO Write)
(02H HWIN15 Read)
CHANNEL NUMBER
0 to 7
=
CONVERSION TIME (CONV)
CONV=2 to 31
o = HSO
STARTS
t = START IMMEDIATELY
CONVERSION
MODE
RSV·
- J 0 = 10-BIT
5
SAMPLE TIME (SAM)
SAM = 1 to 7
I
.
RSV·
7
272265-3
AD_RESULT (HI)
1 1 = B-BIT
RSV·
·RSV - RESERVED BITS MUST BE WRITTEN AS 0
272265-4
AD_RESULT (LO)
(03H HWINO Read)
(03H HWIN15 Write)
:}'""""
8-BIT A/D RESULT AND
MOST SIGNIFICANT BYTE
OF 10-BIT CONVERSION
(02H HWINO Read) .
(02H HWIN15 Write)
'""'''
"-0-=-A""':/""'D-'s--ID-LE-'
1 = A/D is BUSY
3
"READY" BIT
<4
RSV·
5
RSV·
:
} 2 LSB RESULT OF 10-BIT CONVERSION
MOST SIGNIFICANT BIT
·RSV - RESERVED BITS MUST BE WRITTEN AS 0
272265-6
272265-5
HSO_COMMAND
(06H HWINO Write)
(06H HWIN15 Read)
CHANNEL NUMBER:
0-5: HSO.O TO HSO.5 INDIVIDUALLY
6:
HSO.O AND HSO.l
7:
HSO.2 AND HSO.3
8-B: SOFTWARE TIMERS
C:
HSO.O TO HSO.5 SIMULTANEOUSLY
0:
RESERVED
E:
RESET TIMER2
F:
START A/D CONVERSION
0= NO INTERRUPT
1 = INTERRUPT
1--",--,
0= CLEAR BIT
1 = SET BIT
0= TIMER 1
1 = TlMER2
272265-7
14-108
int'et
8XC196KD QUICK REFERENCE
10SO
(15H HWINO Read)
(15H HWIN15 Write)
lOCO
o
HSO.O CURRENT STATE
(15H HWINO Write)
(15H HWIN15 Read)
HSI.O INPUT ENABLE I DISABLE
TIMER 2 RESET EACH WRITE
HSO.1 CURRENT STATE
HSO.2 CURRENT STATE
2
HSI. 1 INPUT ENABLE I DISABLE
HSO.3 CURRENT STATE
3
TIMER 2 EXTERNAL RESET ENABLE I DISABLE
HSO.4 CURRENT STATE
4
HSI.2 INPUT ENABLE I DISABLE
HSO.5 CURRENT STATE
5
TIMER 2 RESET SOURCE HSI.O I T2RST
CAM OR HOLDING REGISTER IS FULL
6
HSI.3 INPUT ENABLE I DISABLE
HSO HOLDING REGISTER IS FULL
7
TIMER 2 CLOCK SOURCE HSI.1
I
T2CLK
272265-9
272265-8
10Sl
o
(16H HWINO Read)
(16H HWIN15 Write)
(16H HWINOWrlte)
(16H HWIN15 Read)
10Cl
SOFTWARE TIMER 0 EXPIRED
o
SOFTWARE TIMER 1 EXPIRED
SELECT PWM
I
SELECT P2.5
EXTERNAL INTERRUPT ACH7 I EXTINT
liiiSAaLE
2
SOFTWARE TIMER 2 EXPIRED
3
SOFTWARE TIMER 3 EXPIRED
TIMER 2 OVERFLOW INTERRUPT ENABLE I DISABLE
2
TIMER 1 OVERFLOW INTERRUPT ENABLE
4
TIMER 2 HAS OVERFLOW
HSO.4 OUTPUT ENABLE I DISABLE
5
TIMER 1 HAS OVERFLOW
SELECT TXD I SELECT P2.0
6
HSI FIFO IS FULL
HSO.5 OUTPUT ENABLE I
7
HSI HOLDING REGISTER DATA AVAILABLE
HSI INTERRUPT
FIFO FULL I ;;H"OL"D"'I;;NG""R"'EG;<;I;;:S"'TE""R~LO;;cA"D"'E~D
BITS 0-5 ARE CLEARED WHEN READ
DiSABLE
272265-11
272265-10
1052
IOC2
(17H HWINO Read)
(17H HWIN15 Write)
(OBH HWINO Write)
(OBH HWIN15 Read)
INDICATES WHICH HSO EVENT OCCURRED
o
ENABLE FAST INCREf.tENT OF T2
HSO.O
ENABLE T2 AS UP IOOWN COUNTER
HSO.1
2
ENABLE
HSO.2
3
HSO.3
4
HSO.4
12
PRES CALER ON PWMs
ENABLE 80C 196KC AID MODES
4
AID CLOCK PRESCALER DISABLE
5
T2 ALTERNATE INTERRUPT@8000H
HSO.5
ENABLE LOCKED CAM ENTRIES
T2RESET
7
START AID
CLEAR ENTIRE CAM'
'THIS BIT ALWAYS READS AS 1
IOS2 IS CLEARED WHEN READ
272265-13
272265-12
14-109
a
8XC196KD QUICK REFERENCE
BAUD_REG
o
SP_STAT
(OEH HWINO Write)
(llH HWINO Read)
(llH HWIN15 Write)
BAUD RATE VALUE (BY) ~
MODE 0:
MODE 1,2,3:
LSB
MSB
14
15 0 ~ T2CLK (EXTERNAL) CLOCK SOURCE
1 ~ XTAL 1 (INTERNAL) CLOCK SOURCE
BAUD ~ BAUD RATE.
MUST WRITE BV AS 2 CONSECUTIVE
BYTES, LSB FIRST.
272265-14
SBUF_RX
2
OE- OVERRUN ERROR""
3
TXE -
SBUF _ TX EMPTY
4
FE -
FRAMING ERROR""
5
TI - - TRANSMIT INTERRUPT""
6
RI - - RECEIVE INTERRUPT""
7
RPE/
RB8
"RSY - RESERVED BITS MUST BE WRITTEN AS 0
""THESE BITS CLEARED WHEN READ
272265-15
WSR
(07H HWINO Read)
(07H HWIN15 Write)
1
(14H all windows R/W)
o
r0O DO - LEADING DATA BIT
I-
RECEIVED PARITY ERROR/
RECEIVED BIT 8""
01
I2
I-
02
WINDOW SELECT BITS
3
03
,4
04
5
05
6
06
-
07
7
0
DISABLED
1~ HOLD ENABLED
272265-17
272265-16
SBUF_TX
--
O~HOLD
SP_CON
(07H HWINO Write)
(07H HWIN15 Read)
o
DO - LEADING DATA BIT
M1
M2
(llH HWINO Write)
, (llH HWIN15 Read)
00
~
10
11
~
MODE 0:
1:
MODE 2:
MODE 3:
o1 ~ MODE
~
SYNCHRONOUS
STANDARD ASYNC
9th BIT ENABLE
9th BIT DATA
-
1
01
2
02
2
PEN - 1
3
03
3
REN -
1 ~ RECEIVE ENABLED
4
04
4
TB8 -
9th BIT FOR TRANSMISSION
05
5
RSV"
6
06
7
07
5
-....
~
PARITY ENABLED
RSY"
272265-18
'RSY - RESERVED BITS MUST BE WRITTEN AS 0
272265-19
14-110
infel"
8XC196KD QUICK REFERENCE
INT_MASK
INT_PEND
(OSH all windows R/W)
(09H all windows R/W)
INT-MASK1
INT--"END1
I I I I I I I I I
I I I I I I I I I
7
6
5
4
3
2
1
0
EXT
INT
SER
PORT
SOFT
TIMER
HSI.O
PIN
HSO
PIN
HSI
DATA
AVAIL
A/D
DONE
TIMER
OVf
13
12
11
EXT
INn
T2
OVf
T2
CAP
I
10
I
HSI
fifO
fULL
4
3
2
1
0
T2
OVf
T2
CAP
HSI4
RI
TI
MASK and PEND bits share the same names
PTSSRV
PTSSEL
14
5
EXT
INTl
NOTE:
MASK and PEND bits share the same names
fifO
fULL
6
fifO
fULL
272265-21
NOTE:
15
7
NMI"
• NMI IS A RESERVED BIT, MUST BE WRITTEN AS 0
272265-20
RSV'
(13H all windows R/W)
(12H all windows R/W)
(06H: Word In HWIN1 Read/Write)
(04H: Word In HWIN1 Read/Write)
9
8
7
6
RI
TI
EXT
INT
SER
PORT
I
5
SOFT
TIMER
"'
3
HSI.l
PIN
I
HSO
PIN
2
HSI
DATA
0
A/D
DONE
TIMER
OVf
• RSV - RESERVED BIT MUST BE WRITTEN AS 0
272265-22
NOTE:
PTSSRV and PTSSEL bits share the same names
IOC3
(OCH HWIN1 Read/Write)
III
RSV'
RSV'
RSV'
RSV'
272265-23
NOTE:
'RSV-Reserved bits must be =
0
14-111
8XC196KD QUICK REFERENCE
4.0 8XC196KD PIN DEFINITION TABLE
68l PlCC
80lQFP
80lSQFP
HLDA
31
47
45
16
HSI.O
24
39
37
18
HSI.1
25
40
38
68lPlCC
80lQFP
80lSQFP
ACHO
6
18
17
ACH1
5
17
ACH2
7
19
Pin Name
Pin Name
ACH3
4
16
15
HSI.2
26
41
39
ACH4
11
24
22
HSI.3
27
43
41
ACH5
10
23
21
HSO.O
28
44
42
ACH6
8
20
19
HSO.1
29
45
43
ACH7
9
21
20
HSO.2
34
50
48
ADO
60
2
80
HSO.3
35
53
51
26
41
39
AD1
59
1
79
HSOA
AD2
58
80
78
HSO.5
27
43
41
AD3
57
78
77
INST
63
5
3
AD4
56
77
76
NMI
3
15
13
76
75
PO.O
6
18
17
AD5
55
AD6
54
74
74
PO.1
5
17
16
AD7
53
73
73
PO.2
7
19
18
AD8
52
72
70
PO.3
4
16
15
AD9
51
71
69
POA
11
24
22
AD10
50
70
68
PO.5
10
23
21
AD11
49
69
67
PO.6
8
20
19
AD12
48
68
66
PO.7
9
21
20
AD13
47
67
65
P1.0
19
34
32
AD14
46
66
64
P1.1
20
35
33
AD15
45
65
63
P1.2
21
36
34
ADV
62
4
2
P1.3
22
37
35
AINC
42
61
59
P1.4
23
38
36
ALE
62
4
2
P1.5
30
46
44
ANGND
12
25
23
P1.6
31
47
45
BHE
41
60
58
P1.7
32
48
46
BREQ
30
46
44
P2.0
18
32
30
BUSWIDTH
64
6
4
P2.1
17
31
29
CPVER
33
49
47
P2.2
15
28
26
CLKOUT
65
7
5
P2.3
44
64
62
EA
2
14
12
P2A
42
61
59
15,9
28,21
26
P2.5
39
58
56
32
48
46
P2.6
33
49
47
EXTINT
HOLD
14-112
intel.
4.0
8XC196KD QUICK REFERENCE
8XC196KD PIN DEFINITION TABLE (Continued)
Pin Name
68LPLCC
80LQFP
P2.7
38
57
55
P3.0
60
2
80
P3.1
59
1
79
P3.2
58
80
78
P3.3
57
78
77
P3.4
56
77
76
P3.5
55
76
75
RXD
17
31
29
P3.6
54
74
74
T2CAPTURE
38
57
55
P3.7
53
73
73
T2CLK
44
64
62
P4.0
52
72
70
T2RST
42
61
59
P4.1
51
71
69
T2UP-DN
33
49
47
P4.2
50
70
68
TXD
18
32
30
P4.3
49
69
67
Vee
1
P4.4
48
68
66
12,13,29,
52,75
10, 11,
27,50
P4.5
47
67
65
Vpp
37
56
54
64
VREF
13
26
24
P4.6
46
66
80LSQFP
68LPLCC
80LQFP
PWMO
39
58
56
PWM1
22
37
35
PWM2
23
38
36
RD
61
3
1
READY
43
62
60
RESET
16
30
28
Pin Name
Vss
80LSQFP
14,36,68 10,11,27, 8,9,25,
33,42,51, 31,40,49,
54,55,63, 52,53,61
79
P4.7
45
65
63
PACT
38
57
55
PALE
17
31
29
PMODE.O
11
24
22
WR
40
59
57
PMODE.1
10
23
21
WRL
40
59
57
PMODE.2
8
20
19
WRH
41
60
58
PMODE.3
9
21
20
XTAL1
67
9
7
XTAL2
66
8
6
PROG
15
28
26
PVER
18
32
30
14-113
II
int'el.,
8XC196KD QUICK REFERENCE
5.0 PACKAGE PIN ASSIGNMENTS
....
::c:
u
""
'IZ
"'
;:: ::c:
x u
'" '""N
'-
'"..;
Cl
0
::E
..;
Cl
N
::E
U
c:i
D..
0
'"
"" :::"" ""
"c:i c:i "'"c:i
::c: ::c: ::c: ::c:
0
""N
'.... '- 'D..
D..
"'c:i
c:i
D..
D..
U
U
D..
D..
::c:
U
0
D..
l-
:;
.:i
"
Vl
I~ >" >In
Z
N
..J
:::J
0
"" "" '"
~
I-
X
..J
U
I-
Cl
~
III
:::J
'"
I-
III
!!:
I~
"'"
..J
""
I~
ACHS/PMODE.l/PO.S
P3.0/ADO
ACH4/PMODE.O/PO.4
P3.1/ADl
ANGND
P3.2/AD2
VREF
P3.3/AD3
vss
P3.4/AD4
EXTINT /PROG/P2.2
I
P3.S/ADS
68"""PIN PLCC
RESET
RXD/PALE/P2.1
P3.S/ADS
P3.7/AD7
N8XC196KD
TXD/PVER/P2.0
P4.0/AD8
PLO
P4.1/AD9
Pl.l
P4.2/AD10
TOP VIEW
Pl.2
PWM1/Pl.3
P4.3/ADll
P4.4/AD12
Looking Down on
Component Side
PWM2/Pl.4
P4.S/AD13
of PC Board
HSI.O
P4.S/AD14
HSI.l
P4.7/AD1S
HSI.2/HSO.4
P2.3/T2CLK
0
If!
c:i c:i c:i
Vl
Ll)
""
D..
Vl
::c: ::c: ::c: '-
'~
iii
::c:
~
":
D..
D..
'-"
I~ I~ I~
"'
'"
0..
N
d
III
'"d
Vl
'- ::c: ::c:
"''">
0..
u
'Z
Cl
I
D..
:::J
N
l-
Vl
Vl
>
......
..
•
>
N
N
Ll)
I"'~
>~
iji ..
N Cl
" ~I~
::e == I: C: I~
I~'- '" "':;;:
D..
a::::
0..
'""'
:::J
lD..
Z
""
"''"
'I-
III
"'N
I-
""
U
N
I-
272265-24
S8·Lead PLCC Package Diagram
14-114
intel~
8XC196KD QUICK REFERENCE
'"... ...... ...'"
"- "-
...'"
"0
.;
'"
0
0
"-
... '"
.; .;
Vl"!
>Vl
11.
'11.
"
11.
11.
...
en
..."-'" "-"... "-... "-... "-;;... "-;;... "-...'" "-;;...'" "-;;... "-;;...'"
~ .;
" ... ... '"... '"... ... ...'" ...'" "...
0
u 11.
11.
11.
11.
11.
11.
;i
11.
11.
11.
o
AD1/P3.1
ADO/P3.0
RD
P2.3/T2CLK
Vss
READY
61
ALE/ADV
INST
P2.4/T2RST
/AiNC
BHE/WRH
BUSWIDTH
WR,tWR[
CLKOUT
P2.S/PWt.tO
SO-PIN QFP
XTAL2
P2.7/T2CAPTURE/PACT
XTAL1
Vpp
SSXC196KD
Vss
Vss
Vss
Vss
Vee
HSO.3
TOP VIEW
Vee
Vee
IT
Vss
Looking Down on
Component Side
Nt.tl
HSO.2
of PC Board
ACH3/PO.3
P2.6/T2UP-DN/CPVER
ACH1/PO.1
P1.7/HOLD
ACHO/PO.O
P1.6/HLDA
ACH2/PO.2
P1.sjBiffii
HSO.1
ACH6/Pt.tODE.2/PO.6
HSO.O
ACH7/EXTINT/Pt.tODE.3/PO.7
HSO.S/HSI.3
N.C.
ACHS/Pt.tODE. l/PO.S
Vss
ACH4/Pt.tODE.O/PO.4
HSO.4/HSI.2
0
z
z
...'"
~
w
Vl
>rr. >
' "•
~
"-
I~"...z
>=
X
tllt;;
> en
W
0:
0
'"' '"'
~
11.
11.
"- "-
I~"- "->
11.
0
Vl
Vl
>
x 0x
0:
...
0
11.
11.
11.
"!
"": "!
11.
:J:
a:
"- "-
iii iii
:J:
'""" '"""'"
11.
11.
w
272265-25
aD-Lead QFP Package Diagram
14-115
•
intel~
8XC196KD QUICK REFERENCE
N
0
'" ...
'",,; ...,,;
an
'" ...
'",,; ...,,;
N
0
,,; ,,; ,,;
0..
RD
0..
0..
0..
0..
an
,,;
0..
0..
0..
0
-
N
'" ...
an
""
..J
e C C C 0 e e <.>
....N
0..
0..
READY
0
ALE!ADV
INST
P2.4/T2RST!AiNC
BHE,tWRil
BUSWIDTH
WR/iV'RL
CLKOUT
P2.S/PWM.O
80 PIN SQFP
XTAL2
P2. 7 /T2CAPTURE/PACT
SB87C196KD
XTAL1
Vpp
VSS
VSS
VSS
VSS
VCC
HSO.3
TOP VIEW
Vcc
Vcc
'fA
VSS
NMI
HSO.2
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
N.C.
ACH3/PO.3
ACH1/PO.l
P2.S/T2UP-DN/CPVER
p1.7;Hoi1i
P1.6/HLDA
ACHO/PO.O
P1.s,Ii3'iiEo
. ACH2/PO.2
HSO.l
ACHS/PMODE.2/PO.6
HSO.O
ACH7/PMODE.3/PO.7
HSI.3/HSO.5
...
an
e
c::i c::i z
0.. 0.. z
.......
-:::-
0
0
0
::IE
::IE
0
0
a. 0..
....... .......
...
an
:r :r
<.>
::lIt;;
~ a. N
0.. >
....... .......
.......
-:::- .......
N
'"""
:::f :::f
>
a.
~
~
a. a.
e .......
....
e
VlN
VI
•
>0:. >
~
~
z
x
;:::
""
'"
~
x
'"
"!
iii
:r
VI
>VI
...
.......
c::i
VI
:r
x
....
272265-26
NOTE:
N.C. means No Connect (do not connect these pins).
SO·Pin SQFP Package
14-116
intel"
6.0
8XC196KD QUICK REFERENCE
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are three Vss pins, all of them must be connected.
VREF
Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
Vss·
Vpp
Programming voltage. Also timing pin for the return from power down circuit. Connect this pin
with a 1 f-LF capacitor to Vss. If this function is not used, connect to Vee.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter. ,
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency. It has a 50% duty cycle.
RESET
Reset input and open-drain output. Hold low to reset the chip. The subsequent low-to-hightransition re-synchronizes CLKOUT and commences a 10-state-time sequence in which the
PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is
executed. Input high for normal operation. RESET has an internal pullup.
SUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If SUSWIDTH is a 1, a 16-bit bus cycle occurs. If SUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TTL~low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Soth pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
SHE/WRH
Sus High Enable or Write High output to external memory, as selected by the CCA. SHE = 0
selects the bank of memory that is connected to the high byte of the data bus. AO = 0 selects
the bank of memory that is connected to the low byte of the data bus. Thus accesses to a 16bit wide memory can be to the low byte only (AO = 0, SHE = 1), to the high byte only (AO =
1, SHE = 0), or both bytes (AO = 0, SHE = 0). If the WRH function is selected, the pin will
go low if the bus cycle is writing to an odd memory location. SHE/WRH is valid only during 16bit external memory write cycles.
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is
low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the
next positive transition in CLKOUT occurs with READY high. When the external memory is not
being used, READY has no effect. Internal control of the number of wait states inserted into a
bus cycle (held not ready) is available through configuration of CCA.
14-117
II
8XC196KD QUICK REFERENCE
6.0
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
the SID in Slave Programming Mode.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
PortO
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins set the Programming Mode.
Port 1
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ
Bus Request output activated when the bus controller has a pending external memory cycle.
Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. The TxD function is
enabled by setting IOC1.5. In mode 0 the pin is used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin functions as input or output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt. EXTINT is selected as
the external interrupt source by setting IOC1.1 high.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.3. T2RST is enabled as the reset source by clearing IOCO.5.
PWMO-2
Port 2.5 can be enabled as a PWM output. The duty cycle of the PWM is determined by the
value loaded into the PWM-CONTROL registers.
T2UPDN
The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2
up/down function is enabled by setting IOC2.1.
T2CAP
A riSing edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15).
PM ODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming Mode.
Used to indicate that Ports 3 and 4 contain a command/address.
PROG
Programming. Falling edge indicates valid data on PBUS and the beginning of programming.
Rising edge indicates end of programming.
PACT
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
PVER
Program Verification. Used in Slave Programming and Auto Programming Modes. Signal is
low after rising edge of PROG if the programming was not successful.
AINC
Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
14-118
intel"
6.0
8XC196KD QUICK REFERENCE
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
PORT
3 and 4
(During
Programming)
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory.
CPVER
Cumulative Program Output Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.
7.0 OPCODE TABLE
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
SKIP
CLR
NOT
NEG
XCH
DEC
EXT
INC
SHR
SHL
SHRA
XCH
SHRL
SHLL
SHRAL
NORML
RESERVED
CLRB
NOTB
NEGB
XCHB
DECB
EXTB
INCB
SHRB
SHLB
SHRAB
XCHB
RESERVED
RESERVED
RESERVED
RESERVED
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SCALL
SCALL
SCALL
SCALL
SCALL
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
SCALL
SCALL
SCALL
JBC
JBC
JBC
JBC
JBC
JBC
JBC
JBC
JBS
JBS
JBS
JBS
JBS
JBS
JBS
JBS
AND DIRECT (3 OPS)
AND IMMEDIATE (3 OPS)
AND INDIRECT (3 OPS)
AND INDEXED (3 OPS)
ADD DIRECT (3 OPS)
ADD IMMEDIATE (30PS)
ADD INDIRECT (3 OPS)
ADD INDEXED (3 OPS)
SUB DIRECT (3 OPS)
SUB IMMEDIATE (3 OPS)
SUB INDIRECT (3 OPS)
SUB INDEXED (30PS)
MULU DIRECT (3 OPS)
MULU IMMEDIATE (3 OPS)
MULU INDIRECT (3 OPS)
MULU INDEXED (3 OPS)
AN DB DIRECT (3 OPS)
AN DB IMMEDIATE (3 QPS)
ANDB INDIRECT (3 OPS)
ANDB INDEXED (3 OPS)
ADDB DIRECT (3 OPS)
ADDB IMMEDIATE (3 OPS)
ADDB INDIRECT (3 OPS)
ADDB INDEXED (3 OPS)
SUBB DIRECT (3 OPS)
SUBB IMMEDIATE (3 OPS)
14-119
5A
5B
5C
5D
5E
5F
60
61
62
62
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
SUBB INDIRECT (3 OPS)
SUBB INDEXED (3 OPS)
MULUB DIRECT (3 OPS)
MULUB IMMEDIATE (3 OPS)
MULUB INDIRECT (3 OPS)
MULUB INDEXED (3 OPS)
AND DIRECT (2 OPS)
AND IMMEDIATE (2 OPS)
AND INDIRECT (2 OPS)
AND INDEXED (2 OPS)
ADD DIRECT (2 OPS)
ADD IMMEDIATE (2 OPS)
ADD INDIRECT (20PS)
ADD INDEXED (2 OPS)
SUB DIRECT (2 OPS)
SUB IMMEDIATE (20PS)
SUB INDIRECT (2 OPS)
SUB INDEXED (2 OPS)
MULU DIRECT (2 OPS)
MULU IMMEDIATE (2 OPS)
MULU INDIRECT (2 OPS)
MULU INDEXED (2 OPS)
ANDB DIRECT (2 OPS)
ANDB IMMEDIATE (2 OPS)
ANDB INDIRECT (2 OPS)
ANDB INDEXED (20PS)
AD DB DIRECT (2 OPS)
ADDB IMMEDIATE (20PS)
ADDB INDIRECT (2 OPS)
ADDB INDEXED (2 OPS)
SUBB DIRECT (2 OPS)
SUBB IMMEDIATE (2 OPS)
SUBB INDIRECT 12 OPS)
SUBB INDEXED (2 OPS)
MULUB DIRECT (2 OPS)
MULUB IMMEDIATE (2 OPS)
MULUB INDIRECT (2 OPS)
MULUB INDEXED (2 OPS)
OR DIRECT
OR IMMEDIATE
OR INDIRECT
OR INDEXED
XORDIRI;:CT
XOR IMMEDIATE
XOR INDIRECT
II
intel .
8XC196KD QUICK REFERENCE
7.0 OPCODE TABLE (Continued)
87
88
B9
8A
BB
8e
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
XOR INDEXED
CMPDIRECT
CMP IMMEDIATE
CMP INDIRECT
CMPINDEXED
DIVUDIRECT
DIVU IMMEDIATE
DIVU INDIRECT
DIVU INDEXED
ORB DIRECT
ORB IMMEDIATE
ORB INDIRECT
ORB INDEXED
XORBDIRECT
XORB IMMEDIATE
XORB INDIRECT
XORB INDEXED
CMPBDIRECT
CMPB IMMEDIATE
CMPB INDIRECT
CMPB INDEXED
DIVUB DIRECT
DIVUB IMMEDIATE
DIVUB INDIRECT
DIVUB INDEXED
LDDIRECT
LD IMMEDIATE
LDINDIRECT
LDINDEXED
ADDCDIRECT
ADDC IMMEDIATE
ADDC INDIRECT
ADDCINDEXED
SUBCDIRECT
SUBC IMMEDIATE
SUBC INDIRECT
SUBCINDEXED
LDBZE DIRECT
LDBZE IMMEDIATE
LDBZE INDIRECT
LDBZE INDEXED
BO
B1
B2
B3
B4
B5
B6
B7
BB
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
. C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
D1
D2
D3
D4
D5
D6
D7
D8
LDBDIRECT
LDB IMMEDIATE
LDB INDIRECT
. LOB INDEXED
ADDCB DIRECT
ADDCB IMMEDIATE
ADDCB INDIRECT
ADDCB INDEXED
SUBCB DIRECT
SUBCB IMMEDIATE
SUBCB INDIRECT
,SUBCBINDEXED
LDBSE DIRECT
LDBSE IMMEDIATE
LDBSE INDIRECT
LDBSEINDEXED
STDIRECT
BMOV
STINDIRECT
STINDEXED
STBDIRECT
CMPL
STB INDIRECT
STBINDEXED
PUSH DIRECT
PUSH IMMEDIA'rE
PUSH INDIRECT
PUSH INDEXED
POP DIRECT
BMOVI
POP INDIRECT
POP INDEXED
JNST
JNH
JGT
JNC
JNVT
JNV
JGE
JNE
JST
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
FB
F9
FA
FB
FC
FD
FE
FF
JH
JLE
JC
JVT
JV
JLT
JE
DJNZ
DJNZW
TIJMP
BR (INDIRECn
RESERVED
RESERVED
RESERVED
LJMP
RESERVED
RESERVED
RESERVED
RESERVED
DPTS
EPTS
RESERVED"
LCALL
RET
RESERVED
PUSHF
POPF
PUSHA
POPA
IDLPD
TRAP
CLRC
SETC
DI
EI
CLRVT
NOP
'DIVIDIVB/MUL/MULB
RST
NOTE:
'Two Byte Instruction
RESERVED-Execution of RESERVED instructions will cause unimplemented opcode interrupt.
"Opcode EE is reserved but does not generate an unimplimented opcode interrupt.
14-120
intel~
8.0
8XC196KD QUICK REFERENCE
INSTRUCTION SET SUMMARY
Mnemonic
Flags
Operation (Note 1)
Operands
Z
N
C
V
ADD/ADDB
2
D~D+A
~
~
~
~
ADD/ADDB
3
D~B+A
~
~
~
~
ADDC/ADDCB
2
D~D+A+C
.l-
~
~
~
SUB/SUBB
2
D~D-A
~
~
~
~
SUB/SUBB
3
D~B-A
~
~
~
~
SUBC/SUBCB
2
D~D-A+C-1
.l-
~
~
~
CMP/CMPB
2
D-A
~
~
~
~
MUL/MULU
2
D,D +
2~D
xA
-
-
- -
MUL/MULU
3
D,D +
2~B
x A
-
2
D,D + 1 ~ D x A
-
- -
MULB/MULUB
-
-
-
MULB/MULUB
3
D,D + 1 ~ B x A
DIVU
2
D ~ (D,D + 2) I A,D + 2 ~ remainder
-
- - ~
Notes
VT ST
t
t
t
t
t
t
t
-
-
-
-
2
-
-
-
-
3
-
-
3
t
t
t
t
-
2
DIVUB
2
D ~ (D,D + 1) IA,D + 1 ~ remainder
-
DIV
2
D ~ (D,D + 2) I A,D + 2 ~ remainder
-
-
DIVB
2
D ~ (D,D + 1) IA,D + 1 ~ remainder
-
-
-
~
AND/ANDB
2
D~
DANDA
~
~
0
0
-
-
AND/ANDB
3
D~BANDA
~
~
0
0
-
OR/ORB
2
D~DORA
~
~
0
0
XOR/XORB
2
D ~ D(ecxl. or) A
~
~
0
0
-
LD/LDB
2
D~A
-
2
A~D
-
ST/STB
-
-
0
0
0
0
~
~
~
~
2
D~A,A~D
-
LDBSE
2
D ~ A; D + 1 ~ SIGN(A)
-
LDBZE
2
D~A;D+1~O
PUSH
1
SP
-
~
SP - 2; (SP)
~
A
(SP); SP + 2
POP
1
A
PUSHF
0
SP ~ SP - 2; (SP) ~ PSW;
PSW ~ OOOOH; I ~ 0
POPF
0
PSW
SJMP
1
PC
~
PC + 11-bit offset
LJMP
1
PC
~
PC + 16-bit offset
~
(SP); SP
~
SP + 2; I ~
~
~
- - - - - - - - - - -
XCH/XCHB
~
~
-
-
-
-
-
0
0
~
~
- - - - - - ,-- -
3
-
-
-
2
-
..
3,4
3,4
5
5
BR[indirect]
1
PC~(A)
-
-
-
-
-
-
TIJMP
3
PC ~ [A] + 2 • ([B] AND C)
-
-
-
-
-
SCALL
1
SP~SP
-
-
-
-
-
-
5
-
-
-
-
-
-
5
(SP)
LCALL
1
~
- 2;
PC; PC
~
PC + 11-bit offset
SP ~ SP - 2; (SP) ~ PC;
PC ~ PC + 16-bit offset
14-121
intel .
8XC196KD QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operands
Flags
Operation (Note 1)
Z
RET
0
PC -
(SP); SP -
J (conditional)
1
PC -
PC + 8-bit offset (if taken)
JC
1
. JumpifC
JNC
1
Jump ifC
JE
1
JumpifZ
JNE
1
JumpifZ
JGE
1
JLT
1
JGT
1
JLE
1
JH
1
JNH
1
JV
1
JNV
1
JVT
1
JNVT
1
JST
1
JNST
1
JBS
3
JBC
3
OJNZI
OJNZW
1
OEC/OECB
1
SP + 2
=1
=0
=1
=0
N C
- - - - - - - - - - - - - - - - - - - -
-
-
-
JumpifN"'; 0
-
-
- -
=1
Jump if N = 0 and Z = 0
Jump if N = 1 or Z = 1
Jump if C = 1 and Z = 0
Jump if C = 0 or Z = 1
Jump if V = 1
Jump if V = 0
Jump if VT = 1; Clear VT
Jump if VT = 0; Clear VT
Jump ifST = 1
JumpifST = 0
Jump if Specified Bit = 1
Jump if Specified Bit = 0
- - - -
Jump if N
0 . - 0-1;
If 0
0 then PC -
*
Notes
V VT ST
-
-
-
-
-
-
-
-
-
- - -
-
-
-
-
-
-
-
5
-
-
5
-
-
5
5
-
5
-
- - 0
- - 0
- - - - - - - - """ - - - - - - - - -
-
5
-
5
-
5
-
5
5
5
-
5
-
5
-
5
-
5,6
-
5,6
-
5
5
5
5
PC + 8-bit offset
0-0-1
~
~
~
~
t t t -
NEG/NEGB
1
0-0-0
~
~
~
~
INCIINCB
1
0 - 0+ 1
~
,.,
~
~
~
~
0
0
-
~
~
0
0
-
~
~
0
0
-
1
0
0
0
-
0
~
~
~
~
t
-
7
~ C
~
~
~
0
-
~
7
~
~
~
0
-
~
7
1
-
-
-
-
-
EXT
1
EXTB
1
NOT/NOTB
1
ooo-
CLR/CLRB
1
0-0
SHLlSHLB/SHLL
2
C -
SHRISHRB/SHRL
2
o ~. msb-----Isb
0; 0 + 2 0; 0 + 1 -
Sign (D)
Sign (D)
Logical Not (D)
msb - - - - - Isb ~
SHRA/SHRAB/SHRAL
2
msb
SETC
0
C-1
CLRC
0
c-o
msb - - - - - Isb
~
C
- - -
14-122
0
-
2
3
-
inteL
8.0
8XC196KD QUICK REFERENCE
INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operands
Flags
Operation (Note 1)
CLRVT
0
VT +- 0
RST
Notes
Z
N
C
V
VT
ST
-
-
-
-
0
-
0
PC +- 2080H
0
0
0
0
0
0
DI
0
Disable Allinterupts (I +- 0)
-
-
-
-
-
-
EI
0
Enable Allinterupts (I +- 1)
-
-
-
-
-
-
DPTS
0
Disablesll PTS Cycles (PSE = 0)
-
-
-
-
-
-
EPTS
0
Enable all PTS Cycles (PSE = 1)
-
-
-
-
-
-
NOP
0
PC +- PC + 1
-
-
-
-
-
-
8
SKIP
1
PC +- PC + 2
-
-
-
-
-
-
NORML
2
Left shift till msb = 1; D +- shift count
y
y
0
-
-
-
7
-
-
-
-
9
TRAP
0
SP +- SP - 2;
(SP) +- PC; PC +- (2010H)
-
-
PUSHA
1
SP +- SP-2; (SP) +- PSW;
PSW +- OOOOH; SP +- SP-2;
(SP) +- IMASK1/WSR; IMASK1 +- OOH
0
0
0
0
0
0
POPA
1
IMASK1/WSR +- (SP); SP +- SP+2
PSW +- (SP); SP +- SP + 2
y
y
y
y
y
y
IDLPD
1
IDLE MODE IF KEY = 1;
POWERDOWN MODE IF KEY = 2;
CHIP RESET OTHERWISE
-
-
-
-
-
-
CMPL
2
D-A
y
y
y
y
i
-
BMOV,
BMOVi
2
[PTR_Hil + +- [PTR_LOWl + ;
UNTILCOUNT=O
-
-
-
-
-
-
NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is done. Operands D, B and A
must conform to the alignment rules for the required operand type, D and B are locations in the Register File; A can be
located anywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
14-123
•
8XC196KD QUICK REFERENCE
9.0
INSTRUCTION LENGTH/OPCODE
MNEMONIC
INDIRECT
INDEXED
DIRECT
IMMED
NORMAU1)
A-INC(1)
SHORT(1)
LONG(1)
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
4/44
4/48
3/64
3/68
3/A4
3/A8
3/88
4/54
4/58
3/74
3/78
3/B4
3/B8
3/98
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3/75
3/79
3/B5
3/B9
3/99
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
5/47
5/4B
4/67
4/6B
4/A7
4/AB
4/8B
5/57
5/5B
4/77
4/7B
4/B7
4/BB
4/9B
6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
5/77
5/7B
5/B7
5/BB
5/9B
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
3/7C
4/(2)
3/9C
6/(2)
5/4D
5/(2)
4/6D
5/(2)
4/8D
5/(2)
4/5D
4/(2)
3/7D
4/(2)
3/9D
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
6/(2)
5/4F
5/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
4/7F
5/(2)
4/9F
7/(2)
6/4F
6/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
5/7F
6/(2)
5/9F
AND (3-op)
AND (2-op)
OR (2-op)
XOR
AN DB (3-op)
ANDB (2-op)
ORB (2-op)
XORB
4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94
5/41
4/61
4/81
4/85
·4/51
3/71
3/91
3/95
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
PUSH
POP
2/C8
2/CC
3/C9
2/CA
2/CE
2/CA
2/CE
3/CB
3/CF
4/CB
4/CF
-
14-124
inteL
9.0
8XC196KD QUICK REFERENCE
INSTRUCTION LENGTH/OPCODE (Continued)
MNEMONIC
LO
LOB
ST
STB
XCH
XCHB
LOBSE
LBSZE
INDIRECT
INDEXED
DIRECT
IMMED
NORMAL
A-INC
SHORT
LONG
3/AO
4/A1
3/A2
3/A2
4/A3
5/A3
3/BO
3/B1
3/B2
3/B2
4/B3
5/B3
3/CO
-
3/C2
3/C2
4/C3
5/C3
3/C6
3/C6
4/C7
5/C7
-
4/0B
5/0B
-
4/1B
5/1 B
3/C4
3/04
3/14
-
3/BC
3/BO
3/BE
3/BE
4/BF
5/BF
3/AC
3/AO
3/AE
3/AE
4/AF
5/AF
Mnemonic
Length/Opcode
Mnemonic
Length/Opcode
PUSHF
POPF
PUSHA
POPA
1/F2
1/F3
1/F4
1/F5
TRAP
LCALL
SCALL
RET
LJMP
SJMP
BR[]
TIJMP
1/F7
JE
JBC
JBS
OJNZ
OJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB
3/30-37
3/38-3F
3/EO
3/E1
3/0F
3/0C
3/00
3/0E
3/08
3/18
3/09
3/19
3/0A
3/1A
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
3/EF
2/28-2F(3)
1IFO
3/E7
2/20-27(3)
2/E3
4/E2
1/00
1/08
1/01
1/09
1/02
1/0A
1/B3
1/08
1/04
1/0C
1/05
CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
BMOV
BMOVi
1/00
1/06
1/0E
1/07
1/0F
1/F8
1/F9
1/FA
1/FB
1/EC
1/EO
1/FC
1/FO
1/FF
2/00
1/F6
3/C1
3/CO
NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for Signed multiply and divide are the unsigned opcode with an "FE" prefix.
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.
14-125
•
8XC196KD QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
MNEMONIC
DIRECT
INDIRECT
IMMED
NORMAL'
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
AND (3-op)
AND (2-op)
OR (2-op)
XOR
AN DB (3-op)
ANDB (2-op)
ORB (2-op)
XORB
LD, LOB
ST, STB
XCH,XCHB
LDBSE
LDBZE
·BMOV
BMOVi
PUSH (int stack)
POP (int stack)
PUSH (ext stack)
POP (ext stack)
5
5
4
4
4
4
4
5
5
4
4
4
4
4
16
14
16
14
26
24
12
10
12
10
18
16
5
4
4
4
5
4
4
4
4,4
4,4
5,5
4
4
6
8
8
11
INDEXED
A-INC'
7/10
7/10
7/10
6/8
6/8
6/8
6/8
6/8
6/8
6/8
6/8
6/8
6/8
7/10
7/10
7/10
7/10
6/8
6/8
6/8
6/8
6/8
6/8
6/8
6/8
6/8
6/8
18/21
19/22
16/19
17/20
18/21
19/22
16/19
17/20
28/31
29/32
26/29
27/30
14/17
15/18
12/15
12/16
14/17
15/18
12/15
12/16
20/23
21/24
18/21
19/22
7/10
7/10
6/8
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
6/8
5/8
6/9
5/8
6/9
8/13
5/8
6/8
6/9
4
5/8
6/8
6/9
4
6 + 8 per word + 3 for each memory controller reference
7+8 per word
+ 14 for each interrupt + 3 for each memory controller reference
9/12
10/13
10/13
7
10/12
11/13
11/13
11/14
12/15
12/15
9
13/15
14/16
14/16
6
6
5
5
5
5
5
5
5
4
4
4
4
4
17
15
17
15
27
25
12
10
12
10
18
16
6
5
5
5
5
4
4
4
5,4
7110
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
19/22
17/19
19/22
17/19
29/32
27/30
15/18
12/16
15/18
13/15
21/24
19/22
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
6/8
6/9
SHORT'
LONG'
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
20/23
18/21
20/23
18/21
30/33
28/31
16/19
14/17
16/19
14/17
22/25
20/23
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
7/10
7/10
9/14
7/10
7/10
11/14
12/14
13/16
15/17
'Times for operands addressed as SFRs and internal RAM (0-1 FFH)/memory controller references (200-0FFFFH)).
NOTES:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue.
2. INT stack is 0-lFFH and EXT stack is 200-0FFFFH.
14-126
infel"
8XC196KD QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
MNEMONIC
(Continued)
MNEMONIC
PUSHF (int stack)
POPF (int stack)
PUSHA (int stack)
POPA (int stack)
6
7
12
12
PUSHF (ext stack)
POPF (ext stack)
PUSHA (ext stack)
POPA (ext stack)
8
10
18
18
TRAP (int stack)
LCALL (int stack)
SCALL (int stack)
RET (int stack)
16
11
11
11
TRAP (ext stack)
LCALL (ext stack)
SCALL (ext stack)
RET (ext stack)
.18
13
13
14
CMPL
CLR/CLRB
NOT/NOTB
NEGINEGB
7
3
3
3
OEC/OECB
EXT/EXTB
INCIINCB
LJMP
SJMP
BR [indirect]
TIJMP
JNST,JST
JNH, JHJGT,JLE
JNC, JC
JNVT,JVT
JNV, JV
JGE, JLT
JNE, JE
JBC, JBS
7
7
7
15 + 3 for each memory controller reference
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
5/9 jump not taken/jump taken
OJNZ
OJNZW
5/9 jump not taken/jump taken
6/10 jump not taken/jump taken
NORML
SHRL
SHLL
SHRAL
SHR/SHRB
SHLlSHLB
SHRA/SHRAB
8 + 1 per shift (9 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
2
2
2
2
2
2
2
2
20 (includes fetch of configuration byte)
3
8/25 (proper key/improper key)
14-127
3
4
3
8XC196KD QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
(Continued)
PTSCYCLES
18 (+ 3 for each memory controller reference)
13 (+ 7 for each transfer, 1 minimum
+ 3 for each memory controller reference)
21
25
12 (+ 10 for each transfer, 1 minimum)
16 (+ 10 for each transfer, 1 minimum)
11 (+ 10 for each transfer, 1 minimum)
15 ( + 11 for each transfer, 1 minimum)
Single Transfer
Block Transfer
AID Mode (SFRs/internal RAM)
(MEMORY CONT)
HSI MODE (SFRs/internal RAM)
(MEMORY CONT)
HSO MODE (SFRs/internal RAM)
(MEMORY CONT)
11.0 INTERRUPT TABLE
80C196KD Interrupt Priorities
Numb.er
Source
PTS Vector Table
Vector
Priority
Location
PTSVector
Location
HSI FIFO Full
205CH
EXTINT1
205AH
TIMER2 Overflow
2058H
INT15
NMI
203EH
15
~/A
PTS
Table
(1,2)
INT14
HSI FIFO Full
203CH
14
TIMER2 Capture
2056H
INT13
EXTINT1
203AH
13
4th HSI FIFO Entry
2054H
INT12
TIMER2 Overflow
2038H
12
RI
2052H
INT11
TIMER2 Capture
2036H
11
TI
2050H
INT10
4th Entry into HSI FIFO
2034H
10
EXTINT
204EH
INT09
RI
2032H
9
Serial Port
204CH
INT08
TI
Software Timer
204AH
HSI.O Pin
2048H
High Speed Outputs
2046H
2030H
8
SPECIAL Unimplemented
Opcode
2012H
N/A
SPECIAL Trap
2010H
N/A
INT07
200EH
7
EXTINT
INT06
Serial Port
200CH
6
INT05
Software Timer
200AH
5
INT04
HSI.O Pin
2008H
4
INT03
High Speed Outputs
2006H
3
INT02
HSI Data Available
2004H
2
INT01
AID Conversion
Complete
2002H
1
fNTOO
Timer Overflow
2000H
0
HSI Data Available
2044H
AID Conversion Complete
2042H
Timer Overflow
2040H
NOTES:
1. PTS, interrupts have higher priOrity than all other interrupts except NMI.
2. PTS priorities are in the same order as conventional interrupts.
14-128
in1et
8XC196KD QUICK REFERENCE
11.0
(Continued)
INTERRUPT TABLE
PTS Control Blocks
PTSVEC_
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
PTSBLOCK
UNUSED
PTSBLOCK
PTSBLOCK
UNUSED
PTSDST(HI)
PTSDST(HI)
REG (HI)
UNUSED
PTSDST(LO)
PTSDST(LO)
REG (LO)
UNUSED
UNUSED
PTSSRC(HI)
PTSSRC(HI)
SID (HI)
PTSSRC(HI)
PTSDEST (HI)
PTSSRC(LO)
PTSSRC(LO)
SID (LO)
PTSSRC(LO)
PTSDEST (LO)
PTSCON
PTSCON
PTSCON
PTSCON
PTSCON
PTSCOUNT
PTSCOUNT
PTSCOUNT
PTSCOUNT
PTSCOUNT
Single
Transfer
Block
Transfer
AID Mode
HSOMode
HSI Mode
80C196KD Interrupt Sources
Interrupt Source
Interrupt Vector
N M I - - - - - - - - - - - - - - - - NMI
Timar 2 Capture - - - - - - - - - - - - - - - - Timer 2 Capture
H51 FIFO fourth Entry - - - - - - - - - - - - - - - - H51 FIFO 4
RI
nag ------~----------Recaiv.
:
- - - - 5",., P••,
TI Flag - - - - - -..
_ _ _ _ _ _ _ _ _ _ _ Tranlmit
Unimplemented Opcode - - - - - - - - - - - - - - - - Unimplemented Coda
TRAP Instruction - - - - - - - - : : : ; : : - ; - - - - - - - Software Trap
PO.7
P2.2
Software
Timer
0-5
Timar
2 Reset
AID Conver.lon Start
------1f-'-------EXTINT
------~
---------EXTINTI
......
::::::3=:;:======1::
~
D>-----
Software Timar
H51.0 - - - - - - - - - - - - - - - - H 5 1 . 0 PIn
H50.0-H50.5 - - - - - - - - - - - - - - - - High Spatd Outputl
HSI FIFO Full ------1~----------FIFO Full
~0,1.L....---7
~
H51 Holding Reg. Loaded - - - - ,
, - - - - - - - .H51 Data Available
A./D Conversian Complete - - - - - - - . . . . ; . . - - - - - - - - AID Conversion Complete
Timar 2 Overflow -----<~r----------Tim.r 2 Overflow
loe1.3
Timer 1 Overflow - ,
Tlmar Overflow
IOC1.2
272265-27
14-129
infel .
8XC196KD QUICK REFERENCE
12.0 FORMULAS
Baud Rate
Asynchronous Modes 1, 2 and 3:
BAUD REG =
XTAL1
- 1
Baud Rate. 16
T2CLK
Baud Rate. a
or
Synchronous Mode 0:
BAUD REG =
XTAL1
- 1
Baud Rate * 2
T2CLK
Baud Rate
or
CONV
XTALI.
B
B
Pulse Width Modulation (PWM)
PWM_CONTROL = 256 " duty cycle or
PWM_CONTROL = 512. duty cycle
State Time
2
1 STATE TIME = XTAL1 = 2 Tosc
AID Conversion
10.Bi
I = INT [1023" (VIN - ANGND)]
tva ue
(VREF _ ANGND)
Signature Word and Voltage Levels
a.Bit value = INT [255. (VIN - ANGND)]
(VREF - ANGND)
SAM = (TSAM· Fosel -2
a
TSAM -_ (a " SAM) +2
Fosc
CONY = (TCONV • Fosel + ·3
2*B
T
CONY =
Conversion time, ,""S
Sample time, ,""S
Value loaded into AD_TIME bits 5, 6, 7.
Must equal 1 through 7
Value loaded into AD_TIME bits 0-5.
Must equal 2 through 31
Processor frequency, MHz
8 for 8-bit conversion
10 for lO-bit conversion
TCONV
TSAMP
SAM
(2' B· CONY) -3
Fosc
14-130
Description
Location
Value
Signature Word
Programming VCC
70H
72H
Programming Vpp
73H
879CH
040H
5.0V
OAOH
12.50V
8XC196KD QUICK REFERENCE
13.0 RESET STATUS
SFR Reset Status
Value
Register Name
AD_RESULT
7FFOH
AD_TIME
OFFH
HSI_STATUS
XOXOXOX08
S8UF(RX)
OOH
INT_MASK
000000008
INT_PENDING
000000008
OOOOH
TIMER1
TIMER2
OOOOH
IOPORT1
111111118
IOPORT2
110000018
SP_STAT /SP _CON
000010118
IMASK1
000000008
IPEND1
000000008
WSR
XXXXOOO08
HSI_MODE
111111118
IOC2
XOOOOOO08
lOCO
000000X08
IOC1
001000018
PWM_CONTROLS
OOH
,
IOPORT3
111111118
IOPORT4
111111118
10SO
000000008
IOS1
000000008
IOS2
000000008
IOC3
111100108
14-131
intel~
8XC196KD QUICK REFERENCE
8XC196KD Pin Reset Status
Pin Name
Multiplexed
Port Pins
Pin Status
During Reset
Pin Status
After Reset
ACHO-ACH7
PO.O-PO.7
Undefined Inputs(l)
Undefined Inputs(l)
PORT1
P1.0-P1.7
Weak Pull-ups (IlL Spec)
Weak Pull-ups (IlL Spec)
TXD
P2.0
Strong Pull-up (11L2 Spec)
Strongly Driven
RXD
P2.1
Undefined Input(3)
Undefined Input(3)
EXTINT
P2.2
Undefined Input(3)
Undefined Input(3)
T2CLK
P2.3
Undefined Input(3)
Undefined Input(3)
T2RST
P2,4
Undefined Input(3)
Undefined Input(3)
PWMO
P2.5
Medium Pull-down
Strongly Driven
P2.6-P2.7
Weak Pull-ups
Weak Pull-ups
P3.0-P4.7
Weak Pull-ups
Address/Data Bus or
Open-Drain 1/0(2)
HSI,O, HSI,1
Undefined Input(3)
Undefined Input(3)
HSI.2/HSO,4
Undefined Input(3)
Undefined Input(3)
ADO-AD15
HSI.3/HSO.5
Undefined Input(3)
Undefined Input(3)
HSO.O/HSO.3
Weak Pull-down
Weak PUll-down
ALE
Weak Pull-up
Strongly Driven
BHE
Weak Pull-up
Strongly Driven
BUSWIDTH
Undefined Input(3)
Undefined Input(3)
CLKOUT
CLKOUT (Strongly Driven)
CLKOUT (Strongly Driven)
EA
Undefined Input(3)
Undefined Input(3)
INST
Weak Pull-down
Strongly Driven
NMI
Weak Pull-down (11H1 Spec)
Weak PUll-down (lIH1 Spec)
RD
Weak Pull-up
Strongly Driven
READY
Undefined Input(3)
Undefined Input(3)
RESET
Medium Pull-up (RRST Spec)
Medium Pull-up (RRST Spec)
WR
Weak Pull-up
Strongly Driven
NOTES:
1. These pins are allowed to float. However, it is recommended that unused pins be tied high or low.
2. The state of these pins depends on device configuration. If the addressl data bus is active. the pins act as a strongly
driven bus; .otherwise, they act as an open-drain 110 port and are left floating.
3. These pins must be driven and not left floating. Input voltage must not exceed Vee during power-up.
4. Consult the BXC196KC/KD data sheet for specifications.
14-132
inteL
8XC196KD QUICK REFERENCE
8XC196KD Pin Status Descriptions
Pin Status
Approximate Value
Weak Pull·up
70/-LA
Medium Pull·up
1 rnA
Strong Pull· up
12mA
Weak Pull·down
200/-LA
Medium Pull·down
1 rnA
Strongly Driven High
See VOH Specification
Strongly Driven Low
See VOL Specification
NOTE:
These typical maximum values are approximate; they are
provided for reference only and are not guaranteed.
14·133
intel·
October 1991
8XC196KR
Quick Reference
Order Number: 272113-001
14-134
8XC196KR Quick Reference
CONTENTS
PAGE
CONTENTS
PAGE
1.0 MEMORY MAP ................... 14-136
8.0 INSTRUCTION SET SUMMARY .. 14-149
2.0 SFR MAP ......................... 14-136
9.0 INSTRUCTION
LENGTH/OPCODES ............... 14-152
3.0 SFR BIT SUMMARy .............. 14-138
4.0 PIN DEFINITION TABLE .......... 14-142
10.0 INSTRUCTION EXECUTION TIMES
(IN STATE TIMES) ................. 14-154
5.0 PACKAGE PIN ASSIGNMENTS .. 14-143
11.0 INTERRUPT TABLE ............. 14-157
6.0 PIN DESCRIPTION ............... 14-144
12.0 FORMULAS ..................... 14-158
7.0 OPCODE TABLE ................. 14-147
13.0 RESET STATUS ................. 14-159
•
14-135
8XC196KR QUICK REFERENCE
1.0 MEMORY MAP
OFFFFH
06000H
05FFFH
02080H
0207FH
0205EH
0205DH
02040H
0203FH
02030H
0202FH
02020H
0201FH
0201BH
0201AH
02019H
02018H
02017H
02014H
02013H
02000H
01FFFH
01 FOOH
01EFFH
00500H
004FFH
00400H
003FFH
00200H
001FFH
OOOOOH
External
Memory
Internal ROM/EPROM
or External Memory
Reserved
PTS Vectors
Interrupt
Vectors (Upper)
ROM/EPROM
Security Key
Reserved
CCB1
Reserved
CCBO
Reserved
Interrupt
Vectors (Lower)
Internal SFRs
External Memory
Internal RAM
External
Memory
Register File
2.0 SFR MAP
CPU Special Function Registers
17H
16H
15H
14H
13H
12H
11 H
10H
OFH
OEH
ODH
OCH
(Reserved)
(Reserved)
(Reserved)
WSR
INT_MASK1
INT_PEND1
OBH
OAH
09H
08H
07H
06H
05H
04H
03H
02H
01H
OOH
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
14-136
(Reserved)
WATCHDOG
INT_PEND
INT_MASK
PTSSRV(Hi)
PTSSRV (Lo)
PTSSEL(Hi)
PTSSEL (Lo)
Read as FFH
Read as FFH
ZERO_REG (Hi)
ZERO_REG (Lo)
-..
5'
CD
~
Memory Mapped I/O SFRs
HIGH BYTE
LOW BYTE
lFFEH
P4_PIN
P3_PIN
lFFCH
P4_REG
lFFAH
lFFBH
LOW BYTE
HIGH BYTE
1FBEH
(Reserved)
(Reserved)
lFBEH
P3_REG
lFBCH
SP_BAUD (Hi)
SP_BAUD (Lo)
lFBCH
(Reserved)
SLP_CON
SLP_CMD
lFBAH
SP_CON
SBUF_TX
lFBAH
COMPO TIME (Hi)
COMPO_TIME (Lo)
(Reserved)
SLP_STAT
1FBBH
SP_STATUS
SBUF_RX
1FBBH
(Reserved)
COMPO CON
EPA9_TIME (Lo)
:
!
COMP1
TIME (Hi)
LOW BYTE
COMP1_TIME (Lo)
COMP1
CON
lFF6H
P5_PIN
USFR
1FB6H
(Reserved)
(Reserved)
lFB6H
EPA9 TIME (Hi)
lFF4H
P5_REG
(Reserved)
lFB4H
(Reserved)
SSIO_BAUD
lFB4H
(Reserved)
lFF2H
P5_DIR
(Reserved)
lFB2H
SSIOO_CON
SSIOO
lFB2H
EPAB_TIME (Hi)
lFFOH
P5_MODE
(Reserved)
1FBOH
SSI01_CON
SSI01_BUF
1FBOH
(Reserved)
lF7EH
EPA7 TIME (Hi)
EPA7 TIME (Lo)
lF7CH
(Reserved)
EPA7_CON
lF7AH
EPA6 TIME (Hi)
EPA6 TIME (Lo)
......
-....I
EPASFRs
HIGH BYTE
Port 0, Port 1 and
Port 6 SFRs
!c.:>
!!!.
Serfall/O and Synchronous
SIOSFRs
BUF
I
A/DandEPA
Interrupt SFRs
HIGH BYTE
LOW BYTE
lFDEH
(Reserved)
(Reserved)
1FAEH
lFDCH
(Reserved)
(Reserved)
1FACH AD_COMMAND (Hi) AD_COMMAND (Lo)
lFDAH
(Reserved)
PO_PIN
lFAAH
AD_RESULT (Hi)
lFDBH
(Reserved)
(Reserved)
lFABH
(Reserved)
EPAIPV
lFD6H
P6_PIN
Pl_PIN
lFA6H
(Reserved)
EP~ENDl
lFD4H
P6_REG
Pl_REG
lFA4H
(Reserved)
EP~ASKl
HIGH BYTE
LOW BYTE
AD_TIME
AD_TEST
AD~ESULT
(Lo)
lFD2H
P6_DIR
Pl_DIR
lFA2H
EPA_PEND (Hi)
EPA-PEND (Lo)
lFDOH
P6_MODE
P1~ODE
1FAOH
EPA-MASK (Hi)
EPA-MASK (Lo)
Port2SFRs
Timer 1 and Timer 2 SFRs
HIGH BYTE
LOW BYTE
HIGH BYTE
1FCEH
PLPIN
(Reserved)
lF9EH
TIMER2(Hi)
TIMER2(Lo)
1FCCH
PLREG
(Reserved)
lF9CH
(Reserved)
T2CONTROL
1FCAH
PLDIR
(Reserved)
lF9AH
TIMERl (Hi)
TIMERl (Lo)
1FCBH
PLMODE
(Reserved) ._
lF9BH
(Reserved)
T1CONTROL
II
LOW BYTE
I
EPA9
CON
EPAB_TIME (Lo)
EPAB
CON
_.
£
8
en
'0
CD
(')
e:
."
C
~
(')
0'
~
J:I
CD
CQ
-..
(ii'
CD
til
CD
><
0
...
CO
en
"
:D
1F7BH
(Reserved)
EPA6_CON
lF76H
EPA5 TIME (Hi)
EPA5 TIME (Lo)
"nc:
:D
lF74H
(Reserved)
EPA5_CON
lF72H
EPA4 TIME (Hi)
EPA4 TIME (Lo)
lF70H
(Reserved)
EPA4_CON
lF6EH
EPA3 TIME (Hi)
EPA3_TIME (Lo)
1F6CH
EPA3
EPA3
CON (Hi)
CON (Lo)
lF6AH
EPALTIME (Hi)
1F6BH
(Reserved)
EPA2 CON
1F66H
EPA1_TIME(Hi)
EPA1_TIME (Lo)
CON (Hi)
EPALTIME (Lo)
EPAl
CON (Lo)
lF64H
EPAl
lF62H
EPAO_TIME (Hi)
EPAO_TIME (Lo)
1F60H
(Reserved)
EPAO_CON
"m
.."
m
m
:D
Z
0
m
intel~
8XC196KR QUICK REFERENCE
3.0 SFR BIT SUMMARY
EPAx-CONTROL
876543210
I RM I TB I CE I M1 I MO I RE I AD I ROT I ON/RT I
RM: "1" Enables Remapping (EPA1 & EPA3 Only)
TB: "0" Selects Timer1, "1" Selects Timer2
CE: "0" Disables Comparator, "1" Enables Comparator
M1, MO: Mode Bits
M1,MO
Capture:
Compare:
00
01
10
11
NoOp
Capture Negative
Capture Positive
Capture All Edges
Interrupt Only
Output "0"
Output "1"
Toggle Output
7
6
543
x
X
x
EPAIPV
6
5
o
2
PEN
M2
TB8: 9th Bit for Transmission
REN: Enables the Receiver
PEN: Enables Parity (Even)
M2, M1:
00: Mode O/Sync
01: Mode 1/Async (std)
10: Mode 2/Async (9th Bit Enable)
, 11: Mode 3/ Async (9th Bit Data)
RE: Reenable Entry = "1" (Lock Entry)
AD: Start AID
ROT: Reset Opposite Time Base
ON/RT: Overrun and Reset Timer Enable
7
I TB8 1 REN
SP_BAUD
1FBCH: Word
1FABH: Byte
4
3
2
1
0
0 I 0 I o I PV4 I PV3 I PV2 I PV1 I PVO I
IPV4-PVO:
Returns the encoded highest priority interrupt
Value from lH-14H.
OH = No Interrupt Pending
14H = EPAINT4
13H = EPAINT5
12H = EPAINT6
11H = EPAINT7
10H = EPAINT8
OFH = EPAINT9
OEH = OVRINTO
DOH = OVRINT1
OCH = OVRINT2
OSH = OVRINT3
OAH
09H
08H
07H
06H
05H
04H
03H
02H
01 H
= OVRINT4
= OVRINT5
= OVRINT6
= OVRINT7
= OVRINT8
= OVRINT9
= Compare Channel 0
= Compare Channel 1
= TIMER1 Overflow
= TIMER2 Overflow
PORT 1/2/5/6 Control
Px.-MODE = "I" for Peripheral Control
Px.-MODE = "0" for Standard Port
Px-DIR = "1" for INPUT or OPEN DRAIN
OUTPUT
Px-DIR = "0" for OUTPUT (PUSH/PULL)
Px-PIN is for PORT READs
Px-REG is for PORT WRITEs
1F9BH: Byte = T1
1F9CH: Byte = T2
TxCONTROL
7
6
5
4
3
2
1
0
UD
MO I P2 I P1 I PO I
I M1"1"IEnables
ICE:CE"0"I Disables
I M2Timer,
Timer
UD: "0" Counts Down, "1" Counts Up
P2, P1, po-Prescale Bits
M2, M1, Mo-Mode Bits
000
+ 1 (250 ns@ 16 MHz) Xtal.4
001
+ 2 (500 'nS @ 16 MHz) Xtal.8
010
+ 4 (11'5 @ 16 MHz) Xtal.16
011
+ 8 (2 1'5 @ 16 MHz) Xtal.32
100
+ 16 (4I's@ 16 MHz).Xtal.64
110
= Internal/Direction = UD
Clock = External/Direction = UD
Clock = Internal/Direction = TxDIR
Clock = External/Direction = TxDIR
Clock = T1 Overflow/Direction = UD
Clock = T1 Overflow/Direction = T1
101
+ 32 (81'S @ 16 MHz) Xtal.128
111
Quadrature Count (TxCLK/TxDIR)
110
+ 64 (16I's@ 16 MHz) Xtal.256
111
Reserved
000
x01
010
011
100
Clock
,
14-138
M1
infel"
8XC196KR QUICK REFERENCE
INT_MASK/INT_MASK1
08H/13H: Byte
INT_PEND/INT_PEND1
09H/12H: Byte
15
14. 13
12
11
10
9
8
PTS_SRV
PTS_SELECT
7
AD_TEST
1FAEH: Byte
76543210
7
SP_STATUS
1FB9H: Byte
6543210
I 0 I 0 I 0 I 0 I OF1 I OFO I VREF I AGND I
I RB8/RPE I RI I TI I FE I TXE I OE I X I X I
AGND: Convert on AnGND
VREF: Convert on VREF
OF1, OFO: Offset Adjust
00: No Adjustment
01: ADD 2.5 mV
10: SUB 2.5 mV
11: SUB 5.0 mV
RPB: Set if 9th Bit set (No Parity)
RPE: Set if Parity Enabled and Parity Error
RI: Set after Last Data Bit Received
TI: Set at Beginning of STOP Bit
FE: Set if No STOP Bit Found
TXE: Set when Byte is in SBUF_TX
OE: . Set if Overrun Error Occurred
7
6
AD_TIME
5
4
AD_COMMAND
1 FACH: Byte/Word
76543210
1FAFH: Byte
3
'2
1
o
I 0
1 0
I T
I. M
1 GO 1
C7annel; #
Channel # = 0 to 7
GO: "1" to Start Now/"O" for EPA Start
M: "0" = 10-Bitl"1" = 8-Bit Conversion
"0" = Detect High/"1" = Detect Low
T: "0" = Normal Conversion/"1" = Threshold Detect
SAM=1t07
CONY = 2t031
Total Conversion Time:
T = (4 • SAM) + (B.(CONV + 1) + 2.5)
Where B = B for 8-Bit, 10 for 10-Bit
r - - - - - - -_ _ •
EPA-MASK1/EPA-PEND1
EPIL-MASK/EPA-PEND
1 FA4H/1 FA6H: Byte
1FAOH/1 FA2H: Word
14-139
8XC196KR QUICK REFERENCE
~
o
PO
1: BWO
Reserved Must Be "0" -
"0"
=
Always Enabled -
0
"""WOE
3
-~4
Reserved Must Be
"0" Enables Write Lock
"~OH" [
7 ~ - "0" Enables Read Lock
-
~ 5
-
-
1
1
~
6
7
BW1
BWO
Bus Width
IRC2
IRC1
IRCO
Max Wait States
o
o
1
o
1
o
1
1
ILLEGAL
16-Bit Only
8-Bit Only
BUSW Pin Controlled
0
0
0
1
1
1
1
0
1
X
0
0
1
1
0
X
1
0
1
0
1
Zero Wait States
Illegal
Illegal
1 Wait State
2 Wait States
3 Wait States
INFINITE
SLP_CON
765432
I0
0
:~~
2 ~ - "1" = WR/BHE - "0" = WRL/WRH
3 ALE
"1" = ALE - "0" = AOV
4~:
: ~ :
~
201AH: Byte
2018H: Byte
- "1" Enables Powerdown
1FFBH: Byte
1
1FF8H: Byte
0
7
I 0 I 0 I 0 I SLP I SLPL IIBEmask I OBFmask I
SLP
SLPL
=
IBEmask =
=
OBFmask =
=
5
4
3
I
2
I
1
I
0
STAT
CBE
IBE
OBF
STAT These bits are written by the 8XC196KR user
and defined by the 8XC196KR user for
communication flags.
CBE (Command Buffer Empty)
= 1 After 8XC196KR Reads SLPCMD
= 0 After Master Writes to SLPCMD
or SLP = 0 in SLP_CON
IBE (Input Buffer Empty)
= 1 After 8XC196KR Reads SLPDIN
= 0 After Master Writes to SLPDIN,
or SLP = 0 in SLP_CON
OBF (Output Buffer Full)
= 1 After 8XC196KR Writes to SLPDOUT
= 0 After Master Reads SLPDOUT
= 1 Enables Slave Port Operation
= 0 Disables Slave Port Operation and
=
6
Clears Bits, CBE, IBE, and OBF
in SLP_STAT
1 ALE Latches SLPJDDR from
AD1 (PS.1)
0 ALE is SLPJDDR
1 IBE Can Affect SLPINT
0 IBE .Cannot Affect SLPINT
1 OBF Can Affect SLPINT
0 OBF Cannot Affect SLPINT
14-140
infel~
8XC196KR QUICK REFERENCE
USFR
7
6
SSIO,,-CON Registers
1 FF6H (Read Only): Byte
4
5
1
2
3
0
765
IR~I~vl~lool~DI~IR~I~1
I MIS
M/S
T/R
TRT
THS
STE
ATR
OUF
TBS
NOTE:
Do not write to location 1FF6H. Bits DED and DEI are
written as specified in users manual.
Device
B7C196KR
DEI
UPROM Bit
DED
UPROM Bit
B3C196KR
N/A
DED-Disable External Data
DEI-Disable External Instructions
N/A
4
1 FB1 H: Byte = 88100
1 FB3H: Byte = 88101
3
2
1
0
I T/R I TRT I THS I STE I ATR I OUF I TBS
Master/Slave
Transmit Receive
Transmitter/Receiver Toggle
Transceiver Handshake Select
Single Transfer Enable
Auto Transfer Re-Enable
Overflow/Underflow Flag
Transceiver/Buffer Status
I
1FAAH: Word
15
14
A/D Channel
BUSY
RSV
2 LSB
8 MSB
Bit 4. 5
13
12
11
9
10
8
76543
BMSB
Channel Number: 0-7
0= AID Idle
1 = AID in Use
Reserved
2 Least Significant Bits
8 Most Significant Bits
0
2 LSB
WSR
7
6
5
2
0
AID Channel
14H: Byte
4
3
HLDEN
HLDEN
I RSV I RSV IBUSyl
,,;, 0 Disables HOLD/HLDA
= 1 Enables HOLD/HLDA
14-141
2
o
II
8XC196KR QUICK REFERENCE
4.0 PIN DEFINITION TABLE
68
52
PLCC PLCC
40
41
42
43
44
45
46
47
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
04
36
04
48
08
35
10
39
38
29
57
56
33
34
35
36
37
38
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
02
30
02
39
32
31
24
44
43
Function
ACHO
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADV
AINC
ALE
ANGND
SHE
BREQ
SUSWIDTH
CLKOUT
CPVER
EA
EPAO
EPA1
68
52
PLCC PLCC
55
54
53
52
51
50
58
59
34
38
37
03
36
28
40
41
42
43
44
45
46
47
57
56
55
54
53
52
51
50
32
33
34
35
36
42
41
45
46
29
31
30
33
34
35
36
37
38
44
43
42
41
27
28
29
30
Function
68
52
PLCC PLCC
EPA2
EPA3
EPA4
EPA5
EPA6
EPA7
EPA8
EPA9
EXTINT
HLDA
HOLD
INST
INTOUT
NMI
PO.O
PO.1
PO.2
PO.3
PO,4
PO.5
PO.6
PO.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2,4
14-142
37
38
39
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
04
03
09
07
01
08
02
10
58
59
60
61
62
63
64
31
32
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
02
06
05
45
46
47
48
49
Function
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3,4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4,4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5,4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6,4
P6.5
P6.6
68
52
PLCC PLCC
65
39
33
44
45
46
47
34
32
07
02
27 .
33
62
64
63
65
01
60
61
57
55
32
31
06
49
05
30
68
09
08
09
67
66
50
32
28
35
36
37
38
29
27
05
23
28
47
49
48
50
27
26
04
40
01.
03
25
06
06
52
51
Function
P6.7
PACT
PALE
PMODE.O
PMODE.1
PMODE.2
PMODE.3
PROG
PVER
RD
READY
RESET
RXD
SCO
SC1
SDO
SD1
SLPINT
T1CLK
T1DIR
T2CLK
T2DIR
TXD
Vee
Vpp
VREF
Vss
Vss
Vss
WR
WRH
WRL
XTAL1
XTAL2
8XC196KR QUICK REfERENCE
5.0 PACKAGE PIN ASSIGNMENTS
6
!i
"
:5
2.
I U 87 65 6.5 U 63 82 61
eo
BUSWIOTH-/ps.7
ADIS/P •. 7
P6.2/TtCLK
P6.1/EPA9
ADI4/P4.6
P6.0/EPA8
AOU/N . .5
PI.O/EPAO/T2CLI(
... DIl/P•. 4
68-PIN
PLCC
87C196KR/87C196KQ
80C196KR/80C196KQ
PI.I/EPA!
AD7/Pl.7
TOP VIEW
PI.6/EPA!
ADe/P3.6
Compon,nt Sid,
ef PC Soard
PI.1/EPA7
ADII!P •. !
AD10/P4.2
AD9/p4.,
A08/P4.0
AD5/Pl . .5
Pl.2/EPA2/T20IR
PU/EPA!
PUlE?,...
P1..5/EPA5
VREF
AHGNO
AD"/P!.'
ADl/Pl.3
PO. 7/PIoIODE.3/ ACH1
ADz/rl.2
PO.S/PIoIOOE.2/ACH6
ADI/P3.!
Po •.5/PWODE.! / A.CH5
ADD/no
PO •• /PWDDE.O/ACH4
272829303132. 33 J4 3536 37 38 39 40414243
272113-2
NOTE:
"In earlier versions of documentation these pins were referred to as:
INTOUT -+ INTINTOUT
BREQ -+ INTB
BUSWIDTH -+ BUSW
HOLD -+ HLD
AD14/P4.6
P6.1/EPA9
ADI3/P •. 5
P6.a/EPAS
AOI2/P .....
AD11/P-4.3
AD10/P4.2
AD9/P4.1
ADS/P4.0
PI.O/EPAO
8XC196JR
52-PIN
PLCC
AD7/P3.7
TOP VIEW
A06/P3.6
Component Sid.
of PC Board
AD5/P3.5
•
PI.1fEPA!
Pt.2/EPA2
PI.3/EPA3
VREF
ANGND
PO.7/PI!.40DE.3/ACH7
PO.6/P~ODE.2/ ACH6
AD4/P3.-4
PO.5/P"00'.,/ ACH5
A03/P3.3
PO.4/Pl-IODE.O/ACH'"
AD2/P3.2
PO.3/ACH3
NOTE:
"In earlier versions of documentation these pins were referred to as:
INTOUT -+ INTINTOUT
BREQ -+ INTB
BUSWIDTH -+ BUSW
HOLD -+ HLD
14-143
272113-3
inteL
8XC196KR QUICK REFERENCE
6.0 PIN DESCRIPTION
Symbol
Name and Function
(+ 5V).
Vee
Main supply voltage
VSS1, VSS2, VSS3
Digital circuit ground (OV). There are three Vss pins, all of which MUST be
\
connected.
VREF
Reference and supply voltage for the AID converter and PortO
connected for AID and Port 0 to function.
Vpp
Programming voltage for the EPROM parts. It should be + 12.5V for programming.
It is also the timing pin for the return from power-down circuit. Connect this pin with
a 1 JLF capacitor to Vss and a 1 Mn resistor to Vee. If this function is not used,
connect Vpp to Vee.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same
potential as VSS.
ACHO-ACH7/PORTO
Analog inputs to the on-chip AID converter. Also a digital input pin."
ALE/ ADV /P5.0
Address Latch Enable or Address Valid output. Goes low to latch and demultiplex
the address/data bus. When the pin is ADV, it goes inactive (high) at the end of the
bus cycle, providing a chip select for external memory. ADV is active only during
external memory accesses. Alsoa standard I/O pin.'
BHE/WRH/P5.5
Byte High Enable or Write High output. BHE = 0 when accessing odd (high) bytes
or complete words in external memory. WRH = 0 when writing to odd bytes or
complete words in external memory. BHE/WRH is only valid during 16-bit external
memory cycles. Also a standard I/O pin.'
BREQ/P2.3
Bus Request output. Active low when the bus controller is in hold and has a
pending external memory cycle. Also a standard I/O pin.'
BUSWIDTH/P5.7
Input for bus width selection. If BUSWIDTH is low, at} 8-bit cycle occurs. If
BUSWIDTH is high, a 16-bit cycle occurs. Also a standard I/O pin."
CLOCKOUT /P2. 7
Output of the internal clock generator. A 50% duty cycle signal at 1/2 XTAL 1·
frequency. Also a standard I/O pin.'
EA
Input for memory select (External Access). EA = 1 directs memory accesses from
locations 2000H through 5FFFH to on-chip EPROM/ROM. EA = 0 directs all
memory accesses to off-chip memory. EA = + 12.5V causes execution to begin in
the Programming Mode. EA is latched at reset.
EPAO-7/P1.0-1.7
EPA8-9/P6.0-6.1
I/O pins for the Event Processor Array. EPAO and EPA2 also function as T2CLK
and T2DIR. Also a standard I/O pin.'
EXTINT /P2.2
External Interrupt input pin. A positive transition sets the EXTINT interrupt pending
flag. The minimum high and low times are 2 oscillator cycles. Also a standard I/O
pin.'
INST/P5.1
Instruction fetch signal. Output high during the entire bus cycle of an external
instruction fetch. INST is active only during external memory fetches; during internal
memory fetches, INST is low. Also a standard I/O pin.'
INTOUT /P2.4
Interrupt output indicating that a pending interrupt requires use of the external bus.
Also a standard I/O pin.'
HLDAlP2.6
Bus Hold Acknowledge output indicating release of the bus in response to a HOLD
request. Also a standard I/O pin.' This is also a TEST MODE enable pin. Do not
use it as an input without careful hardware evaluation.
\
'These pinS may be used for the system or peripheral functions or as a standard I/O pin.
14-144
(+ 5V). Must be
infel .
8XC196KR QUICK REFERENCE
6.0 PIN DESCRIPTION
Symbol
(Continued)
Name and Function
HOLD/P2.5
Sus Hold request input. HOLD is sent by another processor to request control of
8XC196KR system bus. Also a standard I/O pin.'
NMI
Non-Maskable interrupt input pin. A positive transition causes a non-maskable
interrupt vector through memory location 203EH. If not used, this pin should be tied
to Vss. May be used by Intel Evaluation boards.
PORTO
8-bit high impedance input-only port. Also used as AID converter inputs. Port 0 pins
should not be left floating. In EPROM devices these pins are also used to select the
Programming Mode.
PORT1
8-bit bidirectional standard I/O port. All of its pins are shared with the EPA.
PORT2
8-bit bidirectional standard I/O port. All of its pins are shared with other functions
(TxD, RxD, EXTINT, SREQ, INTOUT, HOLD, HLDA, CLKOUT).
PORT3
PORT4
8-bit bidirectional standard I/O with open drain outputs. These pins are shared with
the multiplexed address/data bus which u~es complementary drivers.
PORT5
8-bit bidirectional standard I/O port. All of its pins are shared with other functions
(ALE/ ADV, INST, WR/WRL, RD, SLPINT, SHE/WRH, READY, BUSWIDTH).
PORT6
8-bit bidirectional standard I/O port. All of its pins are shared with other functions
(EPA8, EPA9, T1CLK, T1DIR, SCO, SDO, SC1, SD1).
RD/P5.3
Read signal output to external memory. RD is low only during external memory
reads. Also a standard I/O pin.'
READY/P5.6
Ready input to lengthen external memory cycles. If READY = 1, CPU operation
continues in a normal manner. If READY = 0 wait states are added. Also a
standard I/O pin. •
Reset input to the chip. Held low for at least 16 state times to reset the chip. The
subsequent low to high transition starts the reset Sequence. Input high for normal
operation. RESET has an internal pull up.
RESET
RXD/P2.1
Receive data input pin for the Serial I/O (SID) port. Also a standard I/O pin.'
SLPINT /P5.4
Slave Port Interrupt output pin. Also a standard I/O pin.'
SSI0/P6.4-P6.7
(SCO, SDO, SC1, SD1)
Synchronous Serial I/O pins. SCO/SC1 a~e clock pins and SDO/SD1 are data pins.
Also a standard I/O pin. •
TIMER1 Clock input. TIMER1 increments or decrements on both rising and falling
edges. Also a standard I/O pin."
T1CLK/P6.2
T1DIR/P6.3
TIMER1 Direction input. TIMER1 increments when this pin is high and decrements
when this pin is low. Also a standard I/O pin.'
T2CLK/P1.0
TIMER2 Clock Input. TIMER2 increments or decrements on both rising and falling
edges. Also a standard I/O pin.'
T2DIR/P1.2
TIMER2 Direction input. TIMER2 increments when this pin is high and decrements
when this pin is low. Also a standard I/O pin.'
TXD/P2.0
Transmit data output pin for the Serial I/O (SID) port. Also a standard I/O pin.'
WR/WRL/P5.2
Write and Write Low output to external memory. WR goes low for every external
write. WRL goes low only for writes to even addresses. WR/WRL is active only
during ~xternal memory writes. Also a standard I/O pin.'
XTAL1
Input of the oscillator invertor and the internal clock generator. If using an external
clock source connect it to this pin.
XTAL2
Output of the oscillator invertor. Leave floating unless connected to a crystal/
resonator circuit.
"These pins may be used for the system or peripheral functions or as a standard I/O pin.
14-145
•
infel~
8XC196KR QUICK REFERENCE
6.0 PIN DESCRIPTION
(Continued)
Programming Mode Pin Definitions
Name
Name and Function
PMODE
POA-7
Programming Mode Select. Determines the EPROM programming algorithm that is performed.
PMODE is sampled after a chip reset and should be static while the part is operating.
PALE
Programming ALE Input. Accepted by an 8XC196KR that is in Slave Programming Mode. Used
to indicate that Port 3 and 4 contain a command/address.
PROG
Programming. Falling edge latches data on PBUS and begins programming. Rising edge inputs
ends programming.
PACT
Programming Active. Used to indicate when programming activity is complete.
PVER
Programming Verification. Signal is low after rising edge of PROG if the programming was not
successful.
AINC
Auto Increment. Active low input enables the auto increment mode. Auto increment will allow
reading or writing of sequential EPROM locations without address transactions across the
PBUS for each read or write.
PORTS
3 and4
Address/Command/Data Bus. Used to pass commands, addresses and data to and from
8XC196KRs. Also used in the Auto Programming Mode as a regular system bus to access
external memory.
CPVER
Cumulative Program Verification. Pin is high if all locations since entering a programming mode
have programmed correctly.
14-146
infel .
8XC196KR QUICK REFERENCE
7.0 OPCODE TABLE
00
SKIP
2F
SCALL
5E
01
CL.R
30
JBC
5F
MULUB INDEXED (3 OPS)
02
NOT
31
JBC
60
AND DIRECT (2 OPS)
03
NEG
32
JBC
61
AND IMMEDIATE (2 OPS)
04
XCH
33
JBC
62
AND INDIRECT (2 OPS)
05
DEC
34
JBC
63
AND INDEXED (2 OPS)
06
EXT
35
JBC
64
ADD DIRECT (2 OPS)
07
INC
36
JBC
65
ADD IMMEDIATE (2 OPS)
06
SHR
37
JBC
66
ADD INDIRECT (2 OPS)
09
SHL
36
JBS
67
ADD INDEXED (2 OPS)
OA
SHRA
39
JBS
66
SUB DIRECT (2 OPS)
OB
XCH
3A
JBS
69
SUB IMMEDIATE (2 OPS)
OC
SHRL
3B
JBS
6A
SUB INDIRECT (2 OPS)
OD
SHLL
3C
JBS
6B
SUB INDEXED (2 OPS)
OE
SHRAL
3D
JBS
6C
MULU DIRECT (2 OPS)
OF
NORML
3E
JBS
6D
MULU IMMEDIATE (2 OPS)
10
RESERVED
3F
JBS
6E
MULU INDIRECT (2 OPS)
11
CLRB
40
AND DIRECT (3 OPS)
6F
MULU INDEXED (2 OPS)
12
NOTB
41
AND IMMEDIATE (3 OPS)
70
AN DB DIRECT (2 OPS)
13
NEGB
42
AND INDIRECT (3 OPS)
71
AN DB IMMEDIATE (2 OPS)
14
XCHB
43
AND INDEXED (3 OPS)
72
ANDB INDIREC,' (2 OPS)
15
DECB
44
ADD DIRECT (3 OPS)
73
ANDB INDEXED (2 OPS)
16
EXTB
45
ADD IMMEDIATE (3 OPS)
74
AD DB DIRECT (2 OPS)
17
INCB
46
ADD INDIRECT (3 OPS)
75
ADDB IMMEDIATE (2 OPS)
16
SHRB
47
ADD INDEXED (3 OPS)
76
AD DB INDIRECT (2 OPS)
19
SHLB
46
SUB DIRECT (3 OPS)
77
AD DB INDEXED (2 OPS)
SHRAB
49
SUB IMMEDIATE (3 OPS)
76
SUBB DIRECT (2 OPS)
.1A
MULUB INDIRECT (3 OPS)
1B
XCHB
4A
SUB INDIRECT (3 OPS)
79
SUBB IMMEDIATE (2 OPS)
1C
RESERVED
4B
SUB INDEXED (3 OPS)
7A
SUBB INDIRECT (2 OPS)
10
RESERVED
4C
MULU DIRECT (30PS)
7B
SUBB INDEXED (2 OPS)
1E
RESERVED
4D
MULU IMMEDIATE (3 OPS)
7C
MULUB DIRECT (2 OPS)
1F
RESERVED
4E
MULU INDIRECT (3 OPS)
7D
MULUB IMMEDIATE (2 OPS)
20
SJMP
4F
MULU INDEXED (3 OPS)
7E
MULUB INDIRECT (2 OPS)
21
SJMP
50
ANDB DIRECT (3 OPS)
7F
MULUB INDEXED (2 OPS)
22
SJMP
51
ANDB IMMEDIATE (3 OPS)
60
OR DIRECT
23
SJMP
52
ANDB INDIRECT (3 OPS)
61
OR IMMEDIATE
24
SJMP
53
ANDB INDEXED (3 OPS)
62
OR INDIRECT
25
SJMP
54
ADDB DIRECT (3 OPS)
63
OR INDEXED
26
SJMP
55
ADDB IMMEDIATE (3 OPS)
64
XOR DIRECT
27
SJMP
56
ADDB INDIRECT (3 OPS)
65
XOR IMMEDIATE
26
SCALL
57
ADDB INDEXED (3 OPS)
66
XOR INDIRECT
29
SCALL
56
SUBB DIRECT (3 OPS)
67
XORINDEXED
2A
SCALL
59
SUBB IMMEDIATE (3 OPS)
66
CMPDIRECT
2B
SCALL
5A
SUBB INDIRECT (3 OPS)
69
CMP IMMEDIATE
2C
SCALL
5B
SUBB INDEXED (3 OPS)
6A
CMP INDIRECT
2D
SCALL
5C
MULUB DIRECT (3 OPS)
6B
CMPINDEXED
2E
SCALL
5D
MULUB IMMEDIATE (3 OPS)
6C
DIVU DIRECT
14-147
•
intel~
8XC196KR QUICK REFERENCE
7.0 OPCODE TABLE
(Continued)
8D
DIVU IMMEDIATE
B4
ADDCB DIRECT
DA
8E
DIVU INDIRECT
B5
ADDCB IMMEDIATE
DB
JC
8F
DIVU INDEXED
B6
ADDbB INDIRECT
DC
JVT
90
ORB DIRECT
B7
ADDCB INDEXED
DD
JV
91
ORB IMMEDIATE
B8
SUBCB DIRECT
DE
JLT
92
ORB INDIRECT
B9
SUBCB IMMEDIATE
DF
JE
93
ORB INDEXED
BA
SUBCB INDIRECT
EO
DJNZ
94
XORBDIRECT
BB
SUBCB INDEXED
E1
DJNZW
95
XORB IMMEDIATE
BC
LDBSE DIRECT
E2
TIJMP
96
XORB INDIRECT
BD
LDBSE IMMEDIATE
E3
BR (INDIRECT)
97
XORB INDEXED
BE
LDBSE INDIRECT
E4
RESERVED
98
CMPBDIRECT
BF
LDBSE INDEXED
E5
RESERVED
99
CMPB IMMEDIATE
CO
STDIRECT
E6
RESERVED
9A
CMPB INDIRECT
C1
BMOV
E7
LJMP
JLE
9B
CMPB INDEXED
C2
STINDIRECT
EB
RESERVED
9C
DIVUB DIRECT
C3
STINDEXED
E9
RESERVED
9D
DIVUB IMMEDIATE
C4
STBDIRECT
EA
RESERVED
9E
DIVUB INDIRECT
C5
CMPL
EB
RESERVED
9F
DIVUB INDEXED
C6
STB INDIRECT
EC
DPTS
AO
LDDIRECT
C7
STB INDEXED
ED
EPTS
A1
LD IMMEDIATE
C8
PUSH DIRECT
EE
RESERVED
A2
LDINDIRECT
C9
PUSH IMMEDIATE
EF
LCALL
A3
LD INDEXED
CA
PUSH INDIRECT
FO
RET
A4
ADDCDIRECT
CB
PUSH INDEXED
F1
RESERVED
A5
ADDC IMMEDIATE
CC
POP DIRECT
F2
PUSHF
A6
AD DC INDIRECT
CD
BMOVI
F3
POPF
A7
ADDC INDEXED
CE
POP INDIRECT
F4
PUSHA
A8
SUBCDIRECT
CF
POP INDEXED
F5
POPA
A9
SUBC IMMEDIATE
DO
JNST
F6
IDPLD
AA
SUBC INDIRECT
D1
JNH
F7
TRAP
AB
SUBC INDEXED
D2
JGT
F8
CLRC
AC
LDBZE DIRECT
D3
JNC
F9
SETC
AD
LDBZE IMMEDIATE
D4
JNVT
FA
DI
AE
LDBZE INDIRECT
D5
JNV
FB
EI
AF
LDBZE INDEXED
D6
JGE
FC
CLRVT
BO
LDB DIRECT
D7
JNE
FD
NOP
B1
LDB IMMEDIATE
D8
JST
FE
'DIV IDIVB/MULIMULB
B2
LDB INDIRECT
D9
JH
FF
RST
B3
LDB INDEXED
'Two Byte Instruction· This opcode is placed as the first byte of an instruction to make it a signed operation instead of
unsigned.
14·148
8XC196KR QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY
Flags(2)
Mnemonic
Operation(1)
Operands
Z
N
C
V
VT
i
i
i
i
i
i
i
AOO/AOOB
2
O=O+A
Y'
Y'
Y'
Y'
AOO/AOOB
3
O=B+A
Y'
Y'
Y'
Y'
AOOC/AOOCB
2
O=O+A+C
t
Y'
Y'
Y'
SUB/SUBB
2
O=O-A
Y'
Y'
Y'
Y'
SUB/SUBB
3
O=B-A
Y'
Y'
Y'
Y'
SUBC/SUBCB
2
0=0-A+C-1
t
Y'
Y'
Y'
CMP/CMPB/CMPL
2
O-A
Y'
Y'
Y'
Y'
MULIMULU
2
0,0 + 2 = 0
MUL/MULU
3
0,0 + 2 =
MULB/MULUB
2
0,0 + 1 =
MULB/MULUB
3
0,0 + 1 =
OIVU
2
o = (0,0 + 2)/ A,O + 2 = Remainder
Y'
OIVUB
2
0= (0,0 + 1)/A,0 + 1 = Remainder
Y'
OIV
2
o = (0,0 + 2)/ A,O + 2 = Remainder
Y'
ST
xA
Bx A
0 x A
B xA
Notes
3
3
4
4
OIVB
2
0= (0,0 + 1)/A,0 + 1 = Remainder
ANO/ANOB
2
0=
o and A
Y'
Y'
0
0
ANO/ANOB
3
0= B and A
Y'
Y'
0
0
Y'
i
i
i
i
3
4
OR/ORB
2
0= 0 or A
Y'
Y'
0
0
XOR/XORB
2
o = 0 (exclusive or) A
Y'
Y'
0
0
LO/LOB
2
O=A
ST/STB
2
A=O
XCH
2
o
XCHB
2
O~A
BMOV,
BMOVI
2
(PTR_HI) + = (PTR_LOW) +;
Until COUNT = 0
LOBSE
2
o = A; 0 + 1 = Sign (A)
4, 5
LOBZE
2
0=A;0+1=0
4,5
~
A;O + 1
~
•
A+1
PUSH
1
SP = SP - 2; (SP) = A
POP
1
A = (SP); SP = SP + 2
PUSHF
0
SP = SP - 2; (SP) = PSW;
PSW = 0; I = 0; PSE = 0
POPF
0
PSW = (SP); SP = SP + 2; I
PUSHA
0
SP = SP - 2; (SP) = PSW;
PSW = OOOOH; SP = SP - 2;
(SP) = IMASK1/WSR;
IMASK1 = OOH; I = 0; PSE = 0
paPA
0
IMASK1/WSR = (SP); SP = SP + 2;
PSW = (SP); SP = SP + 2
14-149
~ Y'
0
0
0
0
0
0
11
Y'
Y'
Y'
Y'
Y'
Y'
11
0
0
0
O·
0
0
Y'
Y'
Y'
Y'
Y'
Y'
8XC196KR QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operation(1)
Operands
Flags(2)
Z
N
C
V
VT
5T
Notes
SJMP
1
PC = PC + 11-Bit-Offset
6
WMP
1
PC = PC + 16-Bit-Offset
6
TRAP
1
3
0
PC = (A)
SCALL
BR [Indirect]
TIJMP
PC = ([index] and MASK)2 + (Table)
SP = SP - 2; (SP) = PC;
PC = (2010H)
10
1
SP = SP - 2; (SP) = PC;
PC = PC + 11-Bit-Offset
6
LCALL
1
SP = SP - 2; (SP) = PC;
PC = PC + 16-Bit-Offset
6
PC = (SP); SP = SP + 2
RET
0
J(conditioned)
1
PC = PC + a-Bit-Offset (If Taken)
6
JC
1
Jump ifC = 1
6
JNC
1
JumpifC = 0
6
JE
1
Jump if Z = 1
6
JNE
1
Jump ifZ = 0
6
JGE
1
Jump ifN = 0
6
JLT
1
Jump if N = 1
6
JGT
1
Jump if N = 0 and Z = 0
6
JLE
1
Jump if N = 1 or Z = 1
6
JH
1
Jump if C = 1 and Z = 0
6
JNH
1
Jump if C = 0 or Z = 1
6
JV
1
Jump if V = 0
6
JNV
1
Jump if V = 1
JVT
1
Jump if VT = 1; Clear VT
0
6
JNVT
1
Jump if VT = 0; Clear VT
0
6
JST
1
Jump if ST = 1
JNST
1
Jump if ST = 0
JBS
Jump if Specific Bit = 1
6,7
Jump if Specific Bit = 0
6,7
OJNZ/OJNZW
3
3
1
JBC
6
6
6
0= 0 - 1;
If 0 =F 0 then PC = PC + a-Bit-Offset
6
OEC/OECB
1
0=0-1
VI
VI
VI
VI
NEG/NEGB
1
0=0-0
VI
VI
VI
VI
INC/INCS
1
0=0+1
VI
VI
VI
VI
EXT
1
o=
0;0 + 2 = Sign (D)
VI
VI
0
0
EXTS
1
0= 0;0 + 1 = Sign (D)
VI
VI
0
0
VI
VI
0
0
1
0
0
0
NOT/NOTB
1
o=
CLR/CLRB
1
0=0
Logical Not (D)
14-150
t
t
t
3
4
8XC19SKR QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY
(Continued)
Flags(2)
Mnemonic
Operation(1)
Operands
Z
v
SHL/SHLB/SHLL
2
C +- msbooolsb +- 0
SHRISHRB/SHRL
2
o -?
SHRA/SHRAB/SHRAL
2
msb
NORML
2
Left Shift until msb = 1;0 =
Shift Count
msbQOOlsb
C
N
C
V
VT
Y'
Y'
"0
i
SETC
0
C = 1
" " "
"" " ""
" 0.,
CLRC
0
C=O
0
CLRVT
0
VT = 0
RST
0
PC = 2080H
01
0
Disable All Interrupts (I = 0)
EI
0
Enable Allinterupts (I = 1)
OPTS
0
Disable PTS Interrupts (PSE = 0)
EPTS
0
Enable PTS Interrupts (PSE = 1)
-?
-l>
msbooolsb
-?
C
ST
8
"
"
0
Notes
8
8
8
v'
0
0
0
0
0
0
0
9
+1
+2
NOP
0
PC = PC
SKIP
0
PC = PC
IPLPO
1
Idle Mode IF Key = 1;
Powerdown Mode IF Key = 2
Chip RESET Otherwise
NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is performed. Operands D, Band
A must conform to the alignment rules for the required operand type. D and B are locations in the Lower Register File; A can
be located anywhere in memory.
2. The symbols indicate the effects on the flags:
" Cleared or set as appropriate
o Cleared
1 Set
't Set if appropriate; never cleared
-l- Cleared if appropriate; never set
3. D, D + 2 are consecutive WORDs in memory; D is DOUBLE-WORD aligned.
4. D, D + 1 are consecutive BYTEs in memory; D is WORD aligned.
5. Changes a BYTE to WORD.
6. Offset is a 2's complement number.
7. Specific Bit must be in or windowed into the Lower Register File.
8. The "L" (LONG) suffix indicates DOUBLE-WORD operations.
9. Initiates a RESET by pulling RESET low. Software should re-initialize all the neccessary registers with code starting at
2080H.
10. The assembler does not accept this mnemonic (use the macro file for definition).
11. I = Interrupt Enable (PSW1).
14-151
•
8XC196KR QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODES
Mnemonic
Direct
Indirect
Immed
Indexed
Normal(1)
A-lnc(1)
Short(1)
Long(1)
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
4/46
4/4A·
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
5/47
5/4B
4/67
4/6B
4/A7
4/AB
4/8B
5/57
5/5B
4/77
4/7B
4/B7
4/BB
4/9B
6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
AD DB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
3/A8
3/88
4/54
4/58
3/74
3/78
3/B4
3/B8
3/98
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3/75
3/79
3/B5
3/B9
3/99
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
3/7C
4/(2)
3/9C
6/(2)
5/4D
5/(2)
4/6D
5/(2)
4/8D
5/(2)
4/5D
4/(2)
3/7D
4/(2)
3/9D
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
6/(2)
5/4F
5/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
4/7F
5/(2)
4/9F
7/(2)
6/4F
6/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
5/7F
6/(2)
5/9F
AND (3-op)
AND (2-op)
OR (2-op)
XOR
ANDB (3-op)
AN DB (2-op)
ORB (2-op)
XORB
4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94
5/41
4/61
4/81
4/85
4/51
3/71
3/91
3/95
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
4/42
3/62
3/82
3/86
4/52
3/72
3/92
-3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
PUSH
POP
2/C8
2/CC
3/C9
-
2/CA
2/CE
2/CA
2/CE
3/CB
3/CF
4/CB
4/CF
LD
3/AO
4/A1
3/A2
3/A2
4/A3
5/A3
4/44
4/48
3/64
3/68
3/A4
5/77
5/7B
5/B7
5/BB
5/9B
LDB
3/BO
3/B1
3/B2
3/B2
4/B3
5/B3
ST
3/CO
3/C2
3/C2
4/C3
5/C3
STB
3/C4
-
3/C6
3/C6
4/C7
5/C7
14-152
intel~
8XC196KR QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODES (Continued)
Mnemonic
Direct
Indirect
Immed
Normall l )
XCH
XCHB
LOBSE
LBSZE
A·lnc(l)
ShortLMASK) x 2
+
[TBASE]
EPA PrescalerP2
P1
PO
°o
°°
°
°
°
°
1
1
1
1
0
1
1
1
1
°°
1
0
1
1
1
71
72
74
78
716
732
764
Reserved
SIO Baud RateModes 1,2 and 3
SP BAU D = XTAL 1 Frequency - 1
Baud Rate x 16
(B;;:: 0, SP_BAUD.15 = 1)
SP_BAUD = T1CLK Frequency - 1
Baud Rate x 8
(B> 0, SP_BAUD.15 == 0)
Mode 0
SP_BAUD = XTAL 1 Frequency - 1
Baud Rate x 2
(B > 0, SP_BAUD.15 = 1)
SP_BAUD = T1CLK Frequency ~ 1
Baud Rate
(B > 0, SP_BAUD.15 = 0)
5SI0 Baud RateSSIO.O - S810.6 = XTAL 1 Frequency - 1
Baud Rate x 8
A/DSample States = 4 x SAM + 1
(SAM = AD_TIME.5 - AD_TIME.?)
Conversion States = B x (CONV + 1) + 1.5
(CONV = AD_TIME.O - AD_TIMEA)
(B = 8 for 8-Bit Conversion)
(B = 10 for 10-Bit Conversion)
Total Conversion Time = State Time x [(4 x SAM)
+
(B x (CONV
Programming Pulse WidthPPR
=
((PPW) x (~~4SC)) - 144
+ 32?68
14-158
+
1))
+
2.5]
intel~
8XC196KR QUICK REFERENCE
13.0 RESET STATUS
Reset Value
SFR
AD_RESULT
7FBOH
AD_COMMAND
OCOH
AD_TEST
OCOH
AD_TIME
OFFH
SSIOO_BUF, SSI01_BUF
OOH
SSIOO_CON, SSI01_CON
SSIO
OOH
OXXXXXXXB
BAUD (Baud Rate Control (Read))
SSIO_BAUD (Baud Rate Down Count (Write))
RX, SBUF
SBUF
OOH
OOH
TX
SP_STAT
OBH
SP_CON
EOH
SP_BAUD
OOOOH
COMPO_CON, COMP1_CON
COMPO
TIME, COMP1
OOH
TIME
OOOOH
EPA1_CON, EPA3_CON
OOOOH
= 0, 2, 4-9)
EPA)LTIME (x = 0-9)
OOOOH
TIMER1, TIMER2
OOOOH
OOH
EPA)LCON (x
T1 CONTROL, T2CONTROL
OOH
EPLMASK, EPLMASK1
OOH
EPLPEND, EPLPEND1
OOH
OOH
EPAIPV
PIN, P1
PO
PIN, P3
PIN, P4
PIN, P6
PIN
XXH
OOH
P1_MODE, P6_MODE
DIR
OFFH
P1_REG, P3_REG, P4_REG, P5_REG, P6_REG
OFFH
P1
P2
DIR, P5
PIN, P5
DIR,P6
1XXXXXXXB
PIN
P2_MODE, P5_MODE
BOH
P2_DIR, P2_REG
7FH
INT
MASK,INT
OOH
PEND
OOH
INT_MASK1,INT_PEND1
OOOOH
PTSSRV, PTSSEL
OOH
WSR
14-159
•
8XC196KR QUICK REFERENCE
Pin States, during Reset, Idle and Powerdown
Pin Name
Reset
Idle
PO
wk1
wk1
wk1
ALE (P5.0)
wk1
(A)
(A)
INST (P5.1)
wkO
(A)
(A)
RESET
RO (P5.3), WR (P5.2),
SPLINT (P5.4)
I
wk1
(I)
(I)
BHE (P5.5)
wk1
(B)
(B)
READY (P5.6),
BUSW (P5.7)
wk1
(C)
(C)
EA,NMI
HZ
HZ
HZ
P3, P41 AD (EA
=
=
0)
wk1
HZ
HZ
1)
wk1
0010
0010
ACH/PO
HZ
HZ
HZ
P1
wk1
(D)
(D)
P3, P4/AO (EA
CLKOUT (P2.7)
elk, LZ
(E)
(G)
P2.0-P2.6
wk1
(E)
(E)
P6.0-P6.7
wk1
(F)
Vpp
HZ
1, LZ
-
(F)
1, LZ
XTAL1
HZ
HZ
HZ
XTAL2
ose,LZ
ose, LZ
(H)
NOTES:
(A) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1 and HLDA = 1, then LZ o. If P5_MODE.x = 1 and
HLDA = 0, then HZ.
(8) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1 and HLDA = 1, then LZ 1. If P5_MODE.x = 1 and
HLDA = 0, then HZ.
(C) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1, then HZ.
(D) If P1_MODE.x = 0, port is as programmed. If P1_MODE.x = 1, pin is as specified by P1_DIR and associated
peripheral.
(E) If PLMODE.x = 0, port is as programmed. If P2_MODE.x = 1, pin is as specified by P2_DIR and associated
peripheral.
(F) If P6_MODE.x = 0, port is as programmed. If P6_MODE.x = 1" pin is as specified by P6_DIR ·and associated
peripheral.
(G) If P2_MODE.7 = 0, port is as programmed. If PLMODE.7 = 1, then LZ O.
(H) If XTAL1 = 1, then LZ O. IF XTAL1 =0, then LZ 1.
(I) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1, then pin is as specified by P5_DIR and associated
peripheral.
HZ
= High impedance
LZ
= Low Impedance
wk1 = Weakly pulled high
0010 = Open drain input/output
osc = Oscillator
wkO = Weakly pulled low
14-160
8XC196KT
Quick Reference
14-161
October 1992
Order Number: 272269-001
8XC196KT Quick Reference
CONTENTS
PAGE
CONTENTS
PAGE
1.0 MEMORY MAP ................... 14-163
8.0 INSTRUCTION SET SUMMARY .. 14-177
2.0 SFR MAP ......................... 14-164
9.0 INSTRUCTION
LENGTH/OPCODES ............... 14-180
3.0 SFR BIT SUMMARY .............. 14-166
10.0 INSTRUCTION EXECUTION TIMES
4.0 PIN DEFINITION TABLE .......... 14-170
(IN STATE TIMES) ................. 14-182
5.0 PACKAGE PIN ASSIGNMENTS .. 14-171
11.0 INTERRUPT TABLE . ............ 14-186
6.0 PIN DESCRiPTION ............... 14-172
12.0 FORMULAS ..................... 14-187
7.0 OPCODE TABLE ................. 14-175
13.0 RESET STATUS ................. 14-188
14-162
inteL
8XC196KT QUICK REFERENCE
1.0 MEMORY MAP
OFFFFH
AOOOH
24 Kbytes External Memory
9FFFH
2080H
Internal ROM/EPROM or
External Memory
207FH
205EH
Reserved
205DH
2050H
PTS Vectors
203FH
2030H
Interrupt Vector (Upper)
202FH
2020H
ROM/EPROM Security Key
201FH
201CH
Reserved. Must
= OFFH
201BH
Reserved. Must
= 20H
201AH
CCB1
2019H
Reserved. Must
= 20H
2018H
CCBO
2017H
2014H
Reserved. Must
2013H
2000H
Interrupt Vectors (Lower)
1FFFH
1FOOH
Internal SFR's
1EFFH
0600H
External Memory
05FFH
0400H
Internal RAM
03FFH
OOOOH
Register File
14-163
= OFFH
intet
8XC196KT QUICK REFERENCE
2.0 SFR MAP
CPU Special Function Registers
17H
16H
15H
14H
13H
12H
11H
10H
OFH
OEH
ODH
OCH
(Reserved)
(Reserved)
(Reserved)
WSR
INT MASK1
INT_PEND1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
OSH
OAH
09H
OSH
07H
06H
05H
04H
03H
02H
01H
OOH
14·164
(Reserved)
WATCHDOG
INT_PEND
INT_MASK
PTSSRV (Hi)
PTSSRV (La)
PTSSEL(Hi)
PTSSEL (La)
Read as FFH
Read as FFH
ZERO_REG (Hi)
ZERO_REG (La)
HIGH BYTE
U1
LOW BYTE
LOW BYTE
EPASFRs
HIGH BYTE
LOW BYTE
P4_PIN
P3
PIN
1FBEH
(Reserved)
(Reserved)
1F8EH
COMP1_TIME (Hi)
COMP1_TIME (Lo)
1FFCH
P4_REG
P3_REG
1FBCH
SP_BAUD (Hi)
SP_BAUD (Lo)
1F8CH
(Reserved)
COMP1_CON
1FFAH
SLP_CON
SLP
CMD
1FBAH
SP_CON
SBUF_TX
1F8AH
COMPO_TIME (Hi)
COMPO_TIME (Lo)
1FF8H
(Reserved)
SLP
STAT
1FB8H
SP_STATUS
SBUF_RX
1F88H
(Reserved)
COMPO_CON
1FF6H
P5_PIN
1FB6H
(Reserved)
(Reserved)
1F86H
EPA9_TIME (Hi)
EPA9_TIME (Lo)
1F84H
(Reserved)
EPA9_CON
USFR
1FF4H
P5
REG
(Reserved)
1FB4H
(Reserved)
SSIO_BAUD
1FF2H
P5_DIR
(Reserved)
1FB2H
SSIOO_CON
SSIOO_BUF
1F82H
EPA8_TIME (Hi)
EPAB_TIME (Lo)
1FFOH
P5_MODE
(Reserved)
1FBOH
SSI01_CON
SSI01_BUF
1F80H
(Reserved)
EPAB_CON
1FEOH
(Reserved)
IRAM_REG
1F7EH
EPA7_TIME (Hi)
EPA7_TIME (Lo)
1F7CH
(Reserved)
EPA7_CON
1F7AH
EPA6_TIME (Hi)
EPA6_TIME (Lo)
1F78H
(Reserved)
EPA6_CON
1F76H
EPA5_TIME (Hi)
EPA5_TIME (Lo)
A/DandEPA
Interrupt SFRs
Port 0. Port 1 and
Port6SFRs
I
HIGH BYTE
1FFEH
....
!OJ
!!!.
Serial I/O and Synchronous
SIOSFRs
Memory Mapped I/O SFRs
HIGH BYTE
LOW BYTE
1FAEH
HIGH BYTE
LOW BYTE
AD_TIME
AD_TEST
_.
-... I~
:::J
CD
:::J
en
"C
CD
n
~
."
c:
:::J
n
o·
:::J
::IJ
CD
cc
iii'
...CD
til
QI)
><
(')
.co
en
'-I"
0
c:
c;
'J:I"
1FDEH
(Reserved)
(Reserved)
1FACH AD_COMMAND (Hi) AD_COMMAND (Lo)
1FDCH
(Reserved)
(Reserved)
1FAAH
AD_RESULT (Hi)
1FDAH
(Reserved)
1FA8H
(Reserved)
EPAIPV
1F70H
(Reserved)
EPA"4_CON
1FD8H
(Reserved)
1FA6H
(Reserved)
EPA-PEND1
1F6EH
EPA3_TIME (Hi)
EPA3_TIME (Lo)
m
"TI
m
J:I
m
1FA4H
(Reserved)
EPA-MASK1
1F6CH
EPA3_CON (Hi)
EPA3_CON (Lo)
(')
1F6AH
EPA2_TIME (Hi)
EPALTIME (Lo)
PO
PIN
(Reserved)
1FD6H
P6
1FD4H
P6_REG
P1_REG
1FA2H
EPA-PEND (Hi)
EPA-PEND (Lo)
1FD2H
P6_DIR
P1_DIR
1FAOH
EPA-MASK (Hi)
EPA-MASK (Lo)
1FDOH
P6
PIN
MODE
P1
P1
PIN
AD_RESULT (Lo)
MODE
Timer 1 and Timer 2 SFRs
HIGH BYTE
Port2SFRs
LOW BYTE
HIGH BYTE
LOW BYTE
1F9EH
TIMER2(Hi)
TIMER2(Lo)
1FCEH
PLPIN
(Reserved)
1F9CH
(Reserved)
T2CONTROL
1FCCH
PLREG
(Reserved)
1F9AH
TIMER1 (Hi)
TIMER1 (Lo)
1FCAH
P2_DIR
(Reserved)
1F98H
(Reserved)
T1CONTROL
-------
1FC8H
PLMODE
(Reserved)
-
1F74H
(Reserved)
EPA5_CON
1F72H
EPA4_TIME (Hi)
EPA4_TIME (Lo)
1F68H
(Reserved)
EPA2_CON
1F66H
EPA1_TIME (Hi)
EPA1_TIME (Lo)
1F64H
EPA1_CON (Hi)
EPA1_CON (Lo)
1F62H
EPAO_TIME (Hi)
EPAO_TIME (Lo)
1F60H
(Reserved)
EPAO_CON
z
m
intel"
8XC196KT QUICK REFERENCE
3.0 SFR BIT SUMMARY
EPAx-CONTROL
7
8
6
4
5
SP_CON
1
2
3
x
1 RM 1 TB 1 CE 1 M1 1 MO 1 RE 1 AD 1 ROT 1 ON/RT 1
RM: "1" Enables Remapping (EPA1 & EPA3 Only)
TB: "0" Selects Timer1, "1" Selects Timer2
CE: "0" Disables Comparator, "1" Enables Comparator
M1, MO: Mode Bits
M1,MO
Capture:
Compare:
00
01
10
11
NoOp
Capture Negative
Capture Positive
Capture All Edges
Interrupt Only
Output "0"
Output "1"
Toggle Output
X
EPAIPV
X 1 TBB 1 REN
2
1
PEN
M2
0
·1
TBB: 9th Bit for Transmission
REN: Enables the Receiver
PEN: Enables Parity (Even)
M2, Ml:
00: Mode O/Sync
01: Mode 1/Async (std)
10: Mode 2/Async (9th Bit Enable)
11: Mode 3/ Async (9th Bit Data)
RE: Reenable Entry = "1" (Lock Entry)
AD: Start AID
ROT: Reset OppOSite Time Base
ON/RT: Overrun and Reset Timer Enable
765
1FBBH: Byte
76543
0
SP_BAUD
1FBCH: Word
1FA8H: Byte
4
3
2
1
0
o I· 0
0 1 PV4 1 PV3 1 PV2 1 PVl
PVO
PV4-PVO: Returns the encoded highest priority interrupt.
Value from lH-14H.
OH =
14H =
13H =
12H =
llH =
10H =
OFH =
OEH =
ODH =
OCH =
OBH =
No Interrupt Pending
EPAINT4
EPAINT5
EPAINT6
EPAINT7
EPAINTB
EPAINT9
OVRINTO
OVRINTl
OVRINT2
OVRINT3
OAH
09H
OBH
07H
06H
05H
04H
03H
02H
01 H
=
=
=
=
=
=
=
=
=
=
OVRINT4
OVRINT5
OVRINT6
OVRINT7
OVRINTB
OVRINT9
Compare Channel 0
Compare Channell
TIMERl Overflow
TIMER2 Overflow
TxCONTROL
7
6
5
PORT 1/2/5/6 Control
Fx-MODE = "1" for Peripheral Control
Px-MODE = "0" for Standard Port
Px-DIR = "1" for INPUT or OPEN DRAIN
OUTPUT
Px-DIR = "0" for OUTPUT (PUSH/PULL)
PlL-PIN is for PORT READs
Px-REG is for PORT WRITEs
1F98H: Byte = T1
1F9CH: Byte = T2
4
3
2
1
CE 1 UD 1 M2 1 Ml 1 MO 1 P2 1 Pl
1
CE: "0" Disables Timer, "1" Enables Timer
UD: "0" Counts Down, "1" Counts Up
0
1 PO 1
110
M2, M1, MO-Mode Bits
Clock = Internal/Direction = UD
Clock = External/Direction = UD
Clock = Internal/Direction = TxDIR
Clock = External/Direction = TxDIR
Clock = T1 Overflow/Direction = UD
Clock = T1 Overflow/Direction = Tl
111
Quadrature Count (TxCLK/TxDIR)
110
+ 64 (16 J.£s @16 MHz) Xtal.256
111
Reserved
000
xOl
010
011
100
P2, P1, po-Prescale Bits
14-166
000
+ 1 (250 ns@ 16 MHz) Xtal.4
001
+ 2 (500 ns @16 MHz) Xtal.B
010
+ 4 (1 J.£s@ 16 MHz) Xtal.16
011
+ B (2 J.£s @16 MHz) Xtal.32
100
+ 16 (4 J.£s@ 16 MHz) Xtal.64
101
+ 32 (B J.£s @16 MHz) Xtal.12B
Ml
intel~
8XC196KT QUICK REFERENCE
PTS_SRV
PTS_SELECT
INT_MASK/INT_MASK1
08H/13H: Byte
INT_PEND/INT_PEND1
09H/12H: Byte
15
14
12
11
9
8
AD_TEST
1FAEH: Byte
7654321
I 0 I 0 I 0 I 0 I OF1 I OFO
o
7
I RBS/RPE I RI I TI I FE I TXE I OE I X I X I
VREF
RP8: Set if 9th Bit set (No Parity)
RPE: Set if Parity Enabled and Parity Error
RI: Set after Last Data Bit Received
TI: Set at Beginning of STOP Bit
FE: Set if No STOP Bit Found
TXE: Set when Byte is in SBUF_ TX
OE: Set if Overrun Error Occurred
AGNO: Convert on AnGND
VREF: Convert on VREF
OF1 , OFO: Offset Adjust
00: No Adjustment
01: ADD 2.5 mV
10: SUB 2.5 mV
11: SUB 5.0 mV
AD_TIME
765
4
sa0Ple Time
AD_COMMAND
1FACH: Byte/Word
76543210
1FAFH: Byte
3
2
1
0
c~nVerSi?n Tim~ (CO~V)
SAM=1to7
SP_STATUS
1FB9H: Byte
6543210
I 0
I 0
I TIM
I
GO
I
c~annel: #
Channel # = 0 to 7
GO: "1" to Start Now/"O" for EPA Start
M: "0" = 10-Bitl"1" = 8-Bit Conversion
"0" = Detect High/"1" = Detect Low
T: "0" = Normal Conversion/"1" = Threshold Detect
CONV=2to31
Total Conversion Time:
T = (4 - SAM) + (B-(CONV + 1) + 2.5)
Where B = 8 for 8-Bit, 10 for 10-Bit
EPA-MASK1/EPLPEND1
EPA-MASK/EPA-PEND
1 FA4H/1 FA6H: Byte
1 FAOH/1 FA2H: Word
14-167
intel .
8XC196KT QUICK REFERENCE
CCB
(2018H': Byte)
CCBi (201AH : Byte)
.----
r--
o~ =
1~ =
2~ =
3~ =
41 IRCO =
5~ =
6 1 LOCO =
7~
=
"1" Enables Powerdown
Sealable
"1" = WR/BHE
"0" = WRLlWR'R
"1" = ALE - "0" = ADii
{
}
Seelable
}
Seelable
O~ =
Reserved Must Be "0"
1~ =
Seelable
2~ =
Seelable
=
4~ =
5~ =
6 1MSELO =
7~ =
"0"
= Always Enabled
}
Reserved Must Be "01"
}
Sealable
3 1 WOE
LOCi
LOCO
Function
IRC2
IRCi
IRCO
Max Wait states
0
0
1
1
0
1
0
1
Read and Write Protected
Write Protected Only
Read Protected Only
No Protection
0
1
1
1
1
0
0
0
0
0
1
1
0
Zero Wait States
1 Wait State
2 Wait States
3 Wait States
INFINITE
MSELi
MSELO
0
0
1
0
1
0
1
1
SLP_CON
765432
Bus Timing Mode
Mode 0
Mode 1
Mode 2
Mode 3
SLPL
=
IBEmask =
=
OBFmask =
=
BWO
Bus Width
0
0
1
1
0
1
0
1
ILLEGAL
16-BitOnly
8-BitOnly
BW Pin Controlled
1FFBH: Byte
1
1FF8H: Byte
0
7
6
543
2
1
0
STAT
1 CBE 1 IBE 1 OBF I·
STAT These bits are written by the 8XC196KT user
and defined by the 8XC196KT user for
communication flags.
CBE (Command Buffer Empty)
= 1 After 8XC196KT Reads SLPCMD
= 0 After Master Writes to SLPCMD
or SLP = 0 in SLP_CON
IBE (Input Buffer Empty)
= 1 After 8XC196KT Reads SLPDIN
= 0 After Master Writes to SLPDIN,
or SLP = 0 in SLP....:.CON
OBF (Output Buffer Full)
= 1 After 8XC196KT Writes to SLPDOUT
= 0 After Master Reads SLPDOUT
= 1 Enables Slave Port Operation
= 0 Disables Slave Port Operation and
=
1
BWi
(1-Wait KR)
(Long R/W)
(Early Address)
(KR Compatible)
I 0 I 0 I 0 1 0 1 SLP 1 SLPL 1 IBEmask 1 OBFmask 1
SLP
1
Clears Bits, CBE"IBE, and OBF
in SLP_STAT
'
1 ALE Latches SLP.....ADDR from
AD1 (P3.1)
0 ALE is SLP.....ADDR
1 IBE Can Affect SLPINT
0 IBE Cannot Affect SLPINT
1 OBF Can Affect SLPINT
0 OBF Cannot Affect SLPINT
14-168
8XC196KT QUICK REFERENCE
USFR
7
6
1 FF6H (Read Only): Byte
5
4
3
2
SSIOx-CON Registers
1
1 FB1 H: Byte = 8SI00
1 FB3H: Byte = 88101
76543210
0
IRSV I RSV I RSV I DEI I DED I RSV I RSV I RSV I
IMIS I T/R I TRT I THS I STE I ATR I OUF I TBS I
MIS
T/R
TRT
THS
STE
ATR
OUF
TBS
NOTE:
Do not write to location 1FF6H. Bits DED and DEI are
written as specified in users manual.
Device
87C196KR
DEI
UPROM Bit
OED
UPROM Bit
83C196KR
N/A
DED-Disable External Data
DEI-Disable External Instructions
N/A
AD_RESULT
15
14
AID Channel
BUSY
RSV
2 LSB
8 MSB
Bit 4,5
13
12
11
10
8MSB
Channel Number: 0-7
0= AID Idle
1 = AID in Use
Reserved
2 Least Significant Bits
8 Most Significant Bits
0
9
HLDEN
1FAAH: Word
7
8
6
5
2 LSB
WSR
7
MasterlSlave
Transmit Receive
Transmitter/Receiver Toggle
Transceiver Handshake Select
Single Transfer Enable
Auto Transfer Re-Enable
Overflow/Underflow Flag
Transceiver/Buffer Status
6
4
3
I RSV I RSV IBUSyl
2
14H: Byte
5
4
3
III
0
2
= 0 Disables HOLD/HLDA
= 1 Enables HOLD/HLDA
IRAM_CON
~
RSV'
IRAM
0
1
EA-STAT
0
AID Channel
RSV'
1FEOH: Byte
RSV'
RSV'
RSV'
RSV'
= INTERNAL RAM MAPPED INTERNAL
= INTERNAL RAM
MAPPED EXTERNAL
ICOMPLEMENT OF EA PIN I
272269-1
E~ST AT
not effected by write
*RSV-reserved bit must be = 0
14-169
8XC196KT QUICK REFERENCE
4.0 PIN DEFINITION TABLE
68
68
68
68
PLCC
Function
PLCC
Function
PLCC
Function
PLCC
Function
40
41
42
43
44
45
46
47
26
25
24
23
22
21
20
19
18
ACHO
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADV
AINC
ALE
ANGND
BHE
BREQ
BUSWIDTH
CLKOUT
CPVER
EA
EPAO
EPA1
55
54
53
52
51
50
58
59
34
38
37
03
36
28
40
41
42
43
44
45
46
47
57
56
55
54
53
52
51
50
32
33
34
35
36
EPA2
EPA3
EPA4
EPA5
EPA6
EPA7
EPA8
EPA9
EXTINT
HLDA
HOLD
INST
INTOUT
NMI
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
. P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
37
38
39
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
04
03
09
07
01
08
02
10
58
59
60
61
62
63
64
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
65
39
33
44
45
46
47
34
32
07
02
27
33
62
64
63
65
01
60
61
57
55
32
31
06
49
05
30
68
09
08
09
67
66
P6.7
PACT
PALE
PMODE.O
PMODE.1
PMODE.2
PMODE.3
PROG
PVER
RD
READY
RESET
RXD
SCO
SC1
SDO
SD1
SLPINT
T1CLK
T1DIR
T2CLK
T2DIR
TXD
Vee
Vpp
VREF
Vss
Vss
Vss
WR
WRH
WRL
XTAL1
XTAL2
17
16
15
14
13
12
11
04
36
04
48
08
35
10
39
38
29
57
56
14-170
intel®
8XC196KT QUICK REFERENCE
5.0 PACKAGE PIN ASSIGNMENTS
I~~ l~'-
I~'-
'-'- I''-" '-
I~ ~ I~
~
"!
'" '""-
[L
"'"-"- >V1
>-
>-
z
a::
...'-'" '-'" '-:5'"'" '-'"
~
>-
<0
'"
[L
C
...J
Z
""
...J
...
>-
x
U
0
C
0
U
...>- '-"'".,; '-'" '-.,;'"'" '-'""':
x
"N
...J
<0
<0
[L
[L
<0
[L
'"is
>-
'"!
<0
"-
BUSWIDTH·/PS.7
PS.2/T1CLK
AD1S/P4.7
PS.l/EPA9
AD 14/P4.S
PS.O/EPAS
AD 13/P4.S
P1.0/EPAO/T2CLK
AD12/P4.4
P1.1/EPAl
ADll/P4.3
P 1.2/EPA2/T2DIR
68-PIN
PLCC
8XC196KT
AD10/P4.2
AD9/P4.1
ADS/P4.0
P1.3/EPA3
P1.4/EPA4
P1.5/EPA5
AD7/P3.7
TOP VIEW
P1.S/EPAS
ADS/P3.S
Component Side
of PC Board
Pl.7/EPA7
AD5/P3.5
VREf
AD4/P3.4
ANGND
A03/P3.3
PO. 7/PMOOE.3/ ACH7
AD2/P3.2
PO.S/PMOOL2/ ACHS
A01/P3.1
PO.S/PMOOL1/ACH5
ADO/P3.0
PO.4/PMODLO/ ACH4
I~
"'I:f"
to
~ 1:5 >1.n>UNNNNNN N "N c:i c:i c:i "'
c:i
Il..
a.. a.. a.. a.. a..
(/)
<.)
0
...-
........ ~
N
I't')
8a::: I~-< l~::x:
~ I~a.. I~a.. 1
a..
............................
co
.........
>~ ';l
a::: ~
I~
5
'"
;;:
c
x
>-
0
0
<0
[L
....................................
[L
~I~
> ...
'"
U
[L
[L
u
'-
[L
N
[L
"-
[L
''~ '0
N
...u ...u u... "'u...
:I:
:I:
:I:
:I:
' - >:::>
l~ '"u
0
...J
272269-2
14-171
..
8XC196KT QUICK REFERENCE
6.0 PIN DESCRIPTION
Symbol
Name and Function
(+ 5V).
Vee
Mainsupply voltage
VSS1, VSS2, VSS3
Digital circuit ground (OV). There are three VSS pins, all of which MUST be
connected.
VREF
Reference and supply voltage for the AID converter and PortO
connected for A/D and Port 0 to function.
Vpp
Programming voltage for the EPROM parts. It should be + 12.5V for programming.
It is also the timing pin for the return from power-down circuit. Connect this pin with
a 1 p.F capacitor to VSS and a 1 Mfi resistor to Vee. If this function is not used,
connect Vpp to Vee.
ANGND
Reference ground for the AID converter. Must be held at nominally the same
potential as VSS.
Analog inputs to the on-chip A/D converter. Also a digital input pin."
ACHO-ACH7/PORTO
(+ 5V). Must be
ALE/ ADV /P5.0
Address Latch Enable or Address Valid output. Goes low to latch and demultiplex
the address/data bus. When the pin is ADV, it goes inactive (high) at the end of the
bus cycle, providing a chip select for external memory. ADV is active only during
external memory accesses. Also a standard I/O pin.'
BHE/WRH/P5.5
Byte High Enable or Write High output. BHE = 0 when accessing odd (high) bytes
or complete words in external memo'1:..Y,l!RH = 0 when writing to odd bytes or
complete words in external memory. BHE/WRH is only valid during 16-bit external
memory cycles. Also a standard I/O pin.'
BREQ/P2.3
Bus Request output. Active low when the bus controller is in hold and has a
pending external memory cycle. Also a standard I/O pin.'
BUSWIDTH/P5.7
Input for bus width selection. If BUSWIDTH is low, an 8-bit cycle occurs. If
BUSWIDTH is high, a 16-bit cycle occurs. Also a standard I/O pin.'
CLOCKOUT /P2. 7
Output of the internal clock generator. A 50% duty cycle signal at 1/2 XTAL 1
frequency. Also a standard I/O pin.'
EA
Input for memory select (External Access). EA = 1 directs memory accesses from
locations 2000H through 9FFFH to on-£b!p EPROM/ROM. EA = 0 directs all
memory accesses to off-chip memory. EA = + 12.5V causes execution to begin in
the Programming Mode. EA is latched at reset.
EPAO-7/P1.0-1.7
EPA8-9/P6.0-6.1
I/O pins for the Event Processor Array. EPAO and EPA2 also function as T2CLK
and T2DIR. Also a standard I/O pin.'
EXTINT /P2.2
External Interrupt input pin. A positive transition sets the EXTINT interrupt pending
flag. The minimum high and low times are 2 oscillator cycles. Also a standard I/O
pin."
INST/P5.1
Instruction fetch signal. Output high during the entire bus cycle of an external
instruction fEiltch. INST is active only during external memory fetches; during internal
memory fetches, INST is low. Also a standard I/O pin.'
INTOUT /P2.4
Interrupt output indicating that a pending interrupt requires use of the external bus.
Also a standard I/O pin."
HLDAlP2.6
Bus Hold Acknowledge output indicating release of the bus in response to a HOLD
request. Also a standard I/O pin.' This is also a TEST MODE enable pin. Do not
use it as an input without careful hardware evaluation.
"These PinS may be used for the system or penpheral functions or as a standard I/O pin.
14-172
int:eL
8XC196KT QUICK REFERENCE
6.0 PIN DESCRIPTION
Symbol
(Continued)
Name and Function
HOLD/P2.5
Bus Hold request input. HOLD is sent by another processor to request control of
8XC196KT system bus. Also a standard 1/0 pin. *
NMI
Non-Maskable interrupt input pin. A positive transition causes a non-maskable
interrupt vector through memory location 203EH. If not used, this pin should be tied
to Vss. May be used by Intel Evaluation boards.
PORTO
8-bit high impedance input-only port. Also used as AID converter inputs. Port 0 pins
should not be left floating. In EPROM devices these pins are also used to select the
Programming Mode.
PORT1
8-bit bidirectional standard 1/0 port. All of its pins are shared with the EPA.
PORT2
8-bit bidirectional standard 1/0 port. All of its pins are shared with other functions
(TxD, RxD, EXTINT, BREQ, INTOUT, HOLD, HLDA, CLKOUT).
PORT3
PORT4
8-bit bidirectional standard 110 with open drain outputs. These pins are shared with
the multiplexed addressldata bus which uses complementary drivers.
PORT5
8-bit bidirectional standard 1/0 port. All of its pins are shared with other functions
(ALEI ADV, INST, WR/WRL, RD, SLPINT, BHE/WRH, READY, BUSWIDTH).
PORT6
8-bit bidirectional standard 1/0 port. All of its pins are shared with other functions
(EPA8, EPA9, T1CLK, T1DIR, SCO, SDO, SC1, SD1).
RD/P5.3
Read signal output to external memory. RD is low only during external memory
reads. Also a standard 110 pin.*
READY/P5.6
Ready input to lengthen external memory cycles. If READY = 1, CPU operation
continues in a normal manner. If READY = 0 wait states are added. Also a
standard 1/0 pin. *
RESET
Reset input to the chip. Held low for at least 16 state times to reset the chip. The
subsequent low to high transition starts the reset sequence. Input high for normal
operation. RESET has an internal pullup.
RXD/P2.1
Receive data input pin for the Serial 110 (SIO) port. Also a standard 1/0 pin.'
SLPINT/P5.4
Slave Port Interrupt output pin. Also a standard 1/0 pin. *
SSIO/P6.4-:,P6.7
(SCO, SDO, SC1, SD1)
Synchronous Serial 1/0 pins. SCO/SC1 are clock pins and SDO/SD1 are data pins.
Also a standard 1/0 pin. *
T1CLK/P6.2
TIMER1 Clock input. TIMER1 increments or decrements on both rising and falling
edges. Also a standard 1/0 pin. *
T1DIR/P6.3
TIMER1 Direction input. TIMER1 increments when this pin is high and decrements
when this pin is low. Also a standard 1/0 pin. *
T2CLK/P1.0
TIMER2 Clock Input. TIMER2 increments or decrements on both rising and falling
edges. Also a standard 1/0 pin. *
T2DIR/P1.2
TIMER2 Direction input. TIMER2 increments when this pin is high and decrements
when this pin is low. Also a standard 1/0 pin. *
TXD/P2.0
WR/WRL/P5.2
Transmit data output pin for the Serial 110 (SIO) port. Also a standard 1/0 pin. *
XTAL1
Input of the oscillator invertor and the internal clock generator. If using an external
clock source connect it to this pin.
XTAL2
Output of the oscillator invertor. Leave floating unless connected to a crystal I
resonator circuit.
Write and Write Low output to external memory. WR goes low for every external
write. WRL goes low only for writes to even addresses. WR/WRL is active only
during external memory writes. Also a standard 110 pin. *
'These PinS may be used for the system or peripheral functions or as a standard liD pin.
14-173
III
8XC196KT QUICK REFERENCE
6.0 PIN DESCRIPTION (Continued)
Programming Mode Pin Definitions
Name
Name and Function
PMODE
PO.4-7
Programming Mode Select. Determines the EPROM programming algorithm that is performed.
PMODE is sampled after a chip reset and should be static while the part is operating.
PALE
Programming ALE Input. Accepted by an 8XC196KT that is in Slave Programming Mode. Used
to indicate that Port 3 and 4 contain a command/address.
PROG
Programming. Falling edge latches data on PBUS and begins programming. Rising edge inputs
ends, programming.
PACT
Programming Active. Used to indicate when programming activity is complete.
PVER
Programming Verification. Signal is low after rising edge of PROG if the programming was not
successful.
AINC
Auto Increment. Active low input enables the auto increment mode. Auto increment will allow
reading or writing of sequential EPROM locations without address transactions across the,
PBUS for each read or write.
PORTS
3 aild 4
Address/Command/Data Bus. Used to pass commands, addresses and data to and from
8XC196KTs. Also used in the Auto Programming Mode as a regular system bus to access
external memory.
CPVER
Cumulative Program Verification. Pin is high if all locations since entering a programming mode
have programmed correctly.
14-174
inteL
8XC196KT QUICK REFERENCE
7.0 OPCODE TABLE
MULUB INDIRECT (3 OPS)
00
SKIP
2F
SCALL
5E
01
CLR
30
JBC
5F
MULUB INDEXED (3 OPS)
02
NOT
31
JBC
60
AND DIRECT (2 OPS)
03
NEG
32
JBC
61
AND IMMEDIATE (2 OPS)
04
XCH
33
JBC
62
AND INDIRECT (2 OPS)
AND INDEXED (2 OPS)
05
DEC
34
JBC
63
06
EXT
35
JBC
64
ADD DIRECT (2 OPS)
07
INC
36
JBC
65
ADD IMMEDIATE (2 OPS)
08
SHR
37
JBC
66
ADD INDIRECT (2 OPS)
09
SHL
38
JBS
67
ADD INDEXED (2 OPS)
OA
SHRA
39
JBS
68
SUB DIRECT (2 OPS)
OB
XCH
3A
JBS
69
SUB IMMEDIATE (2 OPS)
OC
SHRL
3B
JBS
6A
SUB INDIRECT (2 OPS)
OD
SHLL
3C
JBS
6B
SUB INDEXED (2 OPS)
OE
SHRAL
3D
JBS
6C
MULU DIRECT (2 OPS)
OF
NORML
3E
JBS
60
MULU IMMEDIATE (2 OPS)
10
RESERVED
3F
JBS
6E
MULU INDIRECT (2 OPS)
11
CLRB
40
AND DIRECT (3 OPS)
6F
MULU INDEXED (2 OPS)
12
NOTB
41
AND IMMEDIATE (3 OPS)
70
ANDB DIRECT (2 OPS)
13
NEGB
42
AND INDIRECT (3 OPS)
71
ANDB IMMEDIATE (2 OPS)
14
XCHB
43
AND INDEXED (3 OPS)
72
ANDB INDIRECT (2 OPS)
15
DECB
44
ADD DIRECT (3 OPS)
73
ANDB INDEXED (2 OPS)
16
EXTB
45
ADD IMMEDIATE (3 OPS)
74
ADDB DIRECT (2 OPS)
17
INCB
46
ADD INDIRECT (3 OPS)
75
ADDB IMMEDIATE (2 OPS)
18
SHRB
47
ADD INDEXED (3 OPS)
76
ADDB INDIRECT (2 OPS)
19
SHLB
48
SUB DIRECT (3 OPS)
77
ADDB INDEXED (2 OPS)
lA
SHRAB
49
SUB IMMEDIATE (3 OPS)
78
SUBB DIRECT (2 OPS)
lB
XCHB
4A
SUB INDIRECT (3 OPS)
79
SUBB IMMEDIATE (2 OPS)
lC
EST INDIRECT"
4B
SUB INDEXED (3 OPS)
7A
SUBB INDIRECT (2 OPS)
10
EST INDEXED"
4C
MULU DIRECT (3 OPS)
7B
SUBB INDEXED (2 OPS)
lE
ESTB INDIRECP'
4D
MULU IMMEDIATE (3 OPS)
7C
MULUB DIRECT (2 OPS)
iF
ESTB INDEXED"
4E
MULU INDIRECT (3 OPS)
70
MULUB IMMEDIATE (2 OPS)
20
SJMP
4F
MULU INDEXED (3 OPS)
7E
MULUB INDIRECT (2 OPS)
21
SJMP
50
Ai<.JDB DIRECT (3 OPS)
7F
MULUB INDEXED (2 OPS)
22
SJMP
51
AN DB IMMEDIATE (3 OPS)
80
OR DIRECT
23
SJMP
52
AN DB INDIRECT (3 OPS)
81
OR IMMEDIATE
24
SJMP
53
ANDB INDEXED (3 OPS)
82
OR INDIRECT
25
SJMP
54
ADDB DIRECT 13 OPS)
83
OR INDEXED
26
SJMP
55
ADDB IMMEDIATE (3 OPS)
84
XORDIRECT
27
SJMP
56
ADDB INDIRECT (3 OPS)
85
XOR IMMEDIATE
28
SCALL
57
ADDB INDEXED (3 OPS)
86
XOR INDIRECT
29
SCALL
58
SUBB DIRECT (3 OPS)
87
XOR INDEXED
2A
SCALL
59
SUBB IMMEDIATE (3 OPS)
88
CMPDIRECT
2B
SCALL
5A
SUBB INDIRECT (3 OPS)
89
CMP IMMEDIATE
2C
SCALL
5B
SUBB INDEXED (3 OPS)
8A
CMP INDIRECT
2D
SCALL
5C
MULUB DIRECT (3 OPS)
8B
CMPINDEXED
2E
SCALL
5D
MULUB IMMEDIATE (3 OPS)
8C
DIVU DIRECT
14-175
•
8XC196KT QUICK REFERENCE
7.0 OPCODE TABLE
(Continued)
8D
DIVU IMMEDIATE
B4
ADDCB DIRECT
DA
8E
DIVU INDIRECT
B5
ADDCB IMMEDIATE
DB
JLE
JC
8F
DIVU INDEXED
B6
ADDCB INDIRECT
DC
JVT
90
ORB DIRECT
B7
ADDCB INDEXED
DD
JV
91
ORB IMMEDIATE
B8
SUBCB DIRECT
DE
JLT
92
ORB INDIRECT·
B9
SUBCB IMMEDIATE
DF
JE
93
ORB INDEXED
BA
SUBCB INDIRECT
EO
DJNZ
94
XORBDIRECT
BB
SUBCB INDEXED
E1
DJNZW
95
XORB IMMEDIATE
BC
LDBSE DIRECT
E2
TIJMP
96
XORB INDIRECT
BD
LDBSE IMMEDIATE
E3
BR (INDIRECT)
97
XORB INDEXED
BE
LDBSE INDIRECT
E4
EBMOVI"
98
CMPBDIRECT
BF
LDBSE INDEXED
E5
RESERVED
99
CMPB IMMEDIATE
CO
STDIRECT
E6
EJMP"
9A
CMPB INDIRECT
C1
BMOV
E7
LJMP
9B
CMPB INDEXED
C2
STINDIRECT
E8
ELD INDIRECT"
9C
DIVUB DIRECT
C3
STINDEXED
E9
ELD INDEXED"
9D
DIVUB IMMEDIATE
C4
STBDIRECT
EA
ELDB INDIRECP'
9E
DIVUB INDIRECT
C5
CMPL
EB
ELDB INDEXED"
9F
DIVUB INDEXED
C6
STB INDIRECT
EC
DPTS
AO
LDDIRECT
C7
STBINDEXED
ED
EPTS
A1
LD IMMEDIATE
C8
PUSH DIRECT
EE,
RESERVED
A2
LDINDIRECT
C9
PUSH IMMEDIATE
EF
LCALL
A3
LDINDEXED
CA
PUSH INDIRECT
FO
RET
A4
ADDCDIRECT
CB
PUSH INDEXED
F1
ECALL"
A5
ADDC IMMEDIATE
CC
POP DIRECT
F2
PUSHF
A6
ADDC INDIRECT
CD
BMOVI
F3
POPF
A7
ADDC INDEXED
CE
POP INDIRECT
F4
PUSHA
A8
SUBCDIRECT
CF
POP INDEXED
F5
POPA
A9
SUBC IMMEDIATE
DO
JNST
F6
IDPLD
AA
SUBC INDIRECT
D1
JNH
F7
TRAP
AB
SUBC INDEXED
D2
JGT
F8
CLRC
AC
LDBZE DIRECT
D3
JNC
F9
SETC
AD
LDBZE IMMEDIATE
D4
JNVT
FA
DI
AE
LDBZE INDIRECT
D5
JNV
FB
EI
AF
LDBZE INDEXED
D6
JGE
FC
CLRVT
BO
LDBDIRECT
D7
JNE
FD
NOP
B1
LDB IMMEDIATE
D8
JST
FE
'DIVIDIVB/MUL/MULB
B2
LDB INDIRECT
D9
JH
FF
RST
B3
LDB INDEXED
'Two Byte Instruction - This opcode is placed as the first byte of an instruction to make it a signed operation instead of
unsigned.
"These instructions exist for compatibility with future devices, and are not tested on the 8XC196KT.
14-176
8XC196KT QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY
Mnemonic
,
Flags(2)
Operatlon(1)
Operands
Z
N
C
V
VT ST
Notes
t
t
t
t
t
t
t
ADD/AD DB
2
D=D+A
~
~
~
j;I
ADD/AD DB
3
D=B+A
~
j;I
~
j;I
ADDC/ADDCB
2
D=D+A+C
J.
~
~
j;I
SUB/SUBB
2
D=D-A
~
~
~
j;I
SUB/SUBB
D=B-A
~
~
~
j;I
SUBC/SUBCB
3
2
D=D-A+C-1
J.
~
j;I
j;I
CMP /CMPB/CMPL
2
D-A
~
~
~
j;I
MULIMULU
2
D,D + 2 = D
MULIMULU
3
D,D + 2 = B
3
3
MULB/MULUB
4
xA
xA
DxA
BxA
2
D,D + 1 =
MULB/MULUB
3
D,D + 1 =
DIVU
2
D = (D,D + 2)/ A,D + 2 = Remainder
j;I
DIVUB
2
D = (D,D + 1)/A,D + 1 = Remainder
j;I
DIV
2
D = (D,D + 2)/ A,D + 2 = Remainder
j;I
DIVB
2
D = (D,D + 1)/ A,D + 1 = Remainder
j;I
AND/ANDB
2
D = DandA
~
~
0
0
AND/ANDB
D = BandA
~
~
0
OR/ORB
3
2
D = DorA
~
~
0
0
0
XOR/XORB
2
D = D (exclusive or) A
~
~
0
0
4
t
t
t
t
3
4
II
LD/LDB
2
D=A
ELD/ELDB
2
D=A
ST/STB
2
A=D
EST/ESTB
2
A=D
XCH
2
D+-+A;D+1 +--+A+1
XCHB
2
D +--+ A
BMOV,
BMOVIIEBMOVI
2
(PTR_HI) + = (PTR_LOW) +;
Until COUNT = 0
LDBSE
2
D = A; D + 1 = Sign (A)
4,5
LDBZE
2
D=A;D+1=0
4,5
PUSH
1
SP = SP - 2; (SP) = A
POP
1
A = (SP); SP = SP + 2
PUSHF
0
SP = SP - 2; (SP) = PSW;
PSW = 0; I = 0; PSE = 0
POPF
0
PSW = (SP); SP = SP + 2; I +-
PUSHA
0
SP = SP - 2; (SP) = PSW;
PSW = OOOOH; SP = SP - 2;
(SP) = IMASK1/WSR;
IMASK1 = OOH; I = 0; PSE = 0
POPA
0
IMASK1/WSR = (SP); SP = SP + 2;
PSW = (SP); SP = SP + 2
SJMP
1
PC = PC + 11-Bit-Offset
14-177
~
0
0
0
0
0
0
11
~
~
~
j;I
j;I
~
11
0
0
0
0
0
0
~
~
~
j;I
~
~
6
infel .
8XC196KT QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY
Mnemonic
(Continued)
Flags(2)
Operatlon(1)
Operands
Z
EBR [Indirect]
1
TIJMP
3
TRAP
0
ECALL
1
LCALL
(16-Bit Mode)
1
LCALL
(24-Bit Mode)
1
SCALL
(16-Bit Mode
1
SCALL
(24-Bit Mode)
1
RET
(16-Bit Mode)
0
RET
(24-Bit Mode)
0
PC
J(conditioned)
1
PC
JC
1
JNC
1
=1
JumpifC = 0
Jump if Z = 1
JumpifZ = 0
Jump if N = 0
Jump if N = 1
Jump if N = 0 and Z = 0
Jump if N = 1 or Z = 1
Jump if C = 1 and Z = 0
Jump if C = 0 or Z = 1
Jump if V = 0
Jump if V = 1
Jump if VT = 1; Clear VT
Jump if VT = 0; Clear VT
JumpifST = 1
JumpifST = 0
Jump if Specific Bit = 1
Jump if Specific Bit = 0
D = D - 1;
If D =F- 0 then PC = PC + 8-Bit-Offset
1
1
I
JE
1
JNE
1
JGE
1
JLT
1
JGT
1
JLE
1
JH
1
JNH
1
JV
1
JNV
1
JVT
1
JNVT
1
JST
1
JNST
1
JBS
3
JBC
3
DJNZ/DJNZW
1
PC
PC
PC
PC
C
V
VT
+ 16-Bit-Offset
+ 24 = Bit-Offset
=
=
PC =
PC =
SP =
PC =
SP =
PC =
SP =
PC =
SP =
PC =
SP =
PC =
SP =
PC =
PC =
WMP
EJMP
N
ST
Notes
6
6,12
(A)
12
([index] and MASK)2
SP - 2; (SP)
(2010H)
=
+ (Table)
PC;
10
SP - 4; (SP) = PC
PC + 20-Bit Offset
6, 12
SP - 2; (SP) = PC
PC + 16-Bit Offset
6
SP - 4; (SP) = PC
PC + 16-Bit Offset
6, 13
SP - 2; (SP) = PC
PC + 11-Bit Offset
6
SP - 4; (SP) = PC
PC + 11-Bit Offset
6,13
(SP); SP
=
SP
+2
=
(SP); SP
=
SP
+4
=
PC
13
+ 8-Bit-Offset (If Taken)
6
JumpifC
14-178
6
6
6
6
6
6
6
6
6
6
6
6
0
6
0
6
6
6
6, 7
6, 7
6
inteL
8XC196KT QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Flags(2)
Operation(1)
Operands
Z
N
C
V
VT
i
i
i
ST
Notes
DEC/DECB
1
D= D- 1
Y'
Y'
Y'
Y'
NEG/NEGB
1
D=O-D
Y'
Y'
Y'
Y'
INCIINCB
1
D=D+1
Y'
Y'
Y'
Y'
EXT
1
D = D;D + 2 = Sign (D)
Y'
Y'
0
0
3
EXTB
1
D = D;D + 1 = Sign (D)
Y'
Y'
0
0
4
NOT/NOTB
1
D = Logical Not (D)
Y'
Y'
0
0
CLR/CLRB
1
D=O
1
0
0
0
SHL/SHLB/SHLL
2
C +- msb".lsb +- 0
Y'
Y'
Y'
Y'
SHRISHRB/SHRL
2
o~
Y'
Y'
Y'
0
Y'
8
SHRAISHRAB/SHRAL
2
msb
Y'
Y'
Y'
0
Y'
8
NORML
2
Left Shift until msb = 1;D =
Shift Count
Y'
Y'
0
msb."lsb
~
~
msb."lsb
C
~
C
SETC
0
C= 1
1
CLRC
0
C=O
0
CLRVT
0
VT = 0
RST
0
PC = 2080H
DI
0
Disable All Interrupts (I = 0)
i
8
8
0
0
=
EI
0
Enable All Interupts (I
DPTS
0
Disable PTS Interrupts (PSE
0
0
0
0
0
9
1)
= 0)
= 1)
EPTS
0
Enable PTS Interrupts (PSE
Nap
0
PC = PC + 1
SKIP
0
PC = PC + 2
IPLPD
1
Idle Mode IF Key = 1;
Powerdown Mode IF Key = 2
Chip RESET Otherwise
NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is performed. Operands D, Band
A must conform to the alignment rules for the required operand type. D and B are locations in the Lower Register File; A can
be located anywhere in memory.
2. The symbols indicate the effects on the flags:
'" Cleared or set as appropriate
o Cleared
1 Set
i Set if appropriate; never cleared
J.. Cleared if appropriate; never set
3. D, D + 2 are consecutive WORDs in memory; D is DOUBLE-WORD aligned.
4. D, D + 1 are consecutive BYTEs in memory; D is WORD aligned.
5. Changes a BYTE to WORD.
6. Offset is a 2's complement number.
7. Specific Bit must be in or windowed into the Lower Register File.
S. The "L" (LONG) suffix indicates DOUBLE-WORD operations.
9. Initiates a RESET by pulling RESET low. Software should re-initialize all the neccessary registers with code starting at
20S0H.
10. The assembler does not accept this mnemonic (use the macro file for definition).
11. I = Interrupt Enable (PSW1).
12. These instructions will only function in 24-bit mode.
13. These instructions push/pop two additional bytes on/off stack in 24-bit mode.
14-179
•
8XC196KT QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODES
Mnemonic
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
Direct
Immed
4/44
4/48
3/64
3/68
3/A4
3/A8
3/88
4/54
4/58
3/74
3/78
3/B4
3/B8
3/98
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3175
3/79
3/B5
3/B9
3/99
Indirect
Indexed
Normal(1)
A-lnc(1)
Short(1)
Long(1)
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/B6
3/BA
3/9A
5/47
5/4B
4/67
4/6B
4/A7
4/AB
4/8B
5/57
5/5B
4/77
4/7B
4/B7
4/BB
4/9B
6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
5/77
5/7B
5/B7
5/BB
5/9B
6/(2)
7/(2)
4/5E
4/(2)
5/4F
5/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
6/4F
6/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
3/7E
4/(2)
3/9E
3/7E
4/(2)
3/9E
4/7F
5/(2)
4/9F
5/7F
. 6/(2)
5/9F
5/41
4/61
4/81
4/85
4/51
3171
3/91
3/95
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
4/42
3/62
3/82
3/86
4/52
3172
3/92
3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
3/C9
-
2/CA
2/CE
2/CA
2/CE
3/CB
3/CF
4/CB
4/CF
3/AO
4/A1
3/A2
3/A2
4/A3
5/A3
3/BO
3/B1
3/B2
3/B2
4/B3
5/B3
5/(2)
6/(2)
5/(2)
4/4C
4/(2)
3/6C
4/(2)
5/4D
5/(2)
4/4E
4/(2)
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7C
4/(2)
3/9C
4/6D
5/(2)
4/8D
5/(2)
4/5D
4/(2)
3/70
4/(2)
3/9D
4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94
PUSH
POP
2/C8
2/CC
LD
LDB
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
. AND (3-op)
AND (2-op)
OR (2-op)
XOR
ANDB (3-op)
ANDB (2-op)
ORB (2-cip)
XORB
3/8C
5/(2)
4/5C
4/(2)
ELD
3/E8
3/E8
6/E9
ELDB
3/EA
3/EA
6/EB
-
3/C2
3/C2
4/C3
5/C3
3/C6
3/C6
4/C7
5/C7
EST
3/1C
3/1C
6/10
ESTB
3/1 E
3/1E
6/1F
ST
3/CO
STB
3/C4
14-180
int:eL
8XC196KT QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODES (Continued)
Mnemonic
XCH
XCHB
LOBSE
LBSZE
Direct
Immed
-
3/04
3/14
Indirect
Indexed
Normal(1)
A·lnc(1)
Short(1)
long(1)
-
-
4/0B
5/0B
4/1B
5/1B
3/BC
3/BO
3/BE
3/BE
4/BF
5/BF
3/AC
3/AO
3/AE
3/AE
4/AF
5/AF
Mnemonic
length/Opcode
Mnemonic
length/Opcode
PUSHF
POPF
PUSHA
POPA
1/F2
1/F3
1/F4
1/F5
OJNZ
OJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB
3/EO
3/E1
3/0F
3/0C
3/00
3/0E
3/08
3/18
3/09
3/19
3/0A
3/1A
CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
BMOV
BMOVi
EBMOVi
1/F8
1/F9
1/FA
TRAP
LCALL
SCALL
ECALL
RET
LJMP
SJMP
EJMP
BR[ 1
TIJMP
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
JE
JBC
JBS
1/F7
3/EF
2/28-2F(3)
4/F1
1/FO
3/E7
2/20-27(3)
4/E6
2/E3
4/E2
1/00
1/08
1/01
1/09
1/02
1/0A
1/B3
1/08
1/04
1/0C
1/05
1/FB
1/EC
1/EO
1/FC
1/FO
1/FF
2/00
1/F6
3/C1
3/CO
3/E4
1/00
1/06
1/0E
1/07
1/0F
3/30-37
3/38-3F
NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.
14-181
•
8XC196KT QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
Instruction
Direct
Immediate
Indirect
Indexed
Normal
A·lnc
Short
Long
ADD (30p)
5
6
7/10
8/11
7/10
8/11
SUB (30p)
5
6
7/10
8/11
7/10
8/11
ADD (2op)
4
5
6/8
7/9
6/8
7/9
SUB (2op)
4
5
6/8
7/9
6/8
7/9
7/9
6/8
7/9
ADDC
4
5
6/8
SUBC
4
5
6/8
7/9
6/8
7/9
CMP
4
5
6/8
7/9
6/8
7/9
ADDB (30p)
5
5
7/10
8/11
7/10
8/11
8/11
7/10
8/11
SUBB (30p)
5
5
7/10
ADDB (2op)
4
4
6/8
7/9
6/8
7/9
SUBB (2op)
4
4
6/8
7/9
6/8
7/9
ADDCB
4
4
6/8
7/9
6/8
7/9
4
4
6/8
7/9
6/8
7/9
CMPB
4
4
6/8
7/9
6/8
7/9
CMPL
7
MUL (30p)
16
17
18/21
19/22
19/22
20/23
MULU (30p)
14
15
16/19
17/20
17/20
18/21
MUL (2op)
16
17
18/21
19/22
19/22
20/23
MULU (2op)
14
15
16/19
17/20
17/20
18/21
SUBCB
DIV
26
27
28/31
29/32
29/32
30/33
DIVU
24
25
26/29
27/30
27/30
28/31
MULB (30p)
12
12
14/17
15/18
15/18
16/19
MULUB (30p)
10
10
12/15
12/16
12/16
14/17
MULB (2op)
12
12
14/17
15/18
15/18
16/19
MULUB (2op)
10
10
12/15
12/16
12/16
14/17
DIVB
18
18
20/23
21/24
21/24
22/25
DIVUB
16
16
18/21
19/22
19/22
20/23
AND (30p)
5
6
7/10
8/11
7/10
8/11
AND (2op)
4
5
6/8
·7/9
6/8
7/9
OR
4
5
6/8
7/9
6/8
7/9
XOR
4
5
6/8
7/9
6/8
7/9
ANDB (30p)
5
5
7/10
8/11
7/10
8/11
AN DB (2op)
4
4
6/8
7/9
6/8
7/9
ORB
4
4
6/8
7/9
6/8
7/9
XORB
4
4
6/8
7/9
6/8
7/9
LD
4
5
5/8
6/8
6/9
7/10
14-182
Extended
I
intel"
8XC196KT QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES) (Continued)
Instruction
Direct
ST
4
LDB
4
STB
4
Indirect
Immediate
Indexed
Normal
A-Inc
Short
Long
5/8
6/9
6/9
7/10
5/8
6/8
6/9
7/10
6/9
7/10
4
Extended
5/8
6/9
ELD
6/9
8/11
8/11
EST
6/9
8/11
8/11
ELDB
6/9
8/11
8/11
6/9
8/11
ESTB
8/11
XCH
5
8/13
STB
4
8/13
9/14
XCHB
5
8/13
9/14
BMOV
6
BMOVi
7
+ 8 per Word
+ 8 per Word
6
7
+ 14 for Each Interrupt
EBMOVI
+ 11/14perWord
+ 11/14 per Word
+ 14 for Each Interrupt
+ 14/20 per Word
+ 16 for Each Interrupt
8
4
4
PUSH (int)
6
7
POP (int)
8
LDBSE, LDBZE
9/14
PUSHF (int)
6
POPF (int)
7
PUSHA (int)
12
POPA (int)
12
PUSH (ext)
8
POP (ext)
11
PUSHF (ext)
8
POPF (ext)
10
PUSHA (ext)
18
POPA (ext)
18
EJMP (24-Bit Mode)
8
LJMP
7
SJMP
7
EBR [Indirect] (24-Bit Mode)
9
BR[lndirect]
7
TIJMP (Internal Table)
15
TIJMP (External Table)
18
TRAP (24-Bit Mode, Int)
19
TRAP (16-Bit Mode, Int)
16
9
5/7
6/8
6/8
7/9
9/12
10/13
10/13
11/14
10/12
"11/13
11/13
12/14
11/14
12/15
12/15
13/16
13/15
14/16
14/16
15/17
14-183
III
intel·
8XC196KT QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
Instruction
Direct
Indirect
Immediate
Normal
ECALL (24-Bit Mode, Int)
Indexed
Short
. Extended
Long
16
LCALL (16-Bit Mode, Int)
11
LCALL (24-Bit Mode, Int)
15
SCALL (16-Bit Mode,lnt
11
SCALL (24-Bit Mode, Int)
15
RET (24-Bit Mode, Int)
16
RET (16-Bit Mode, Int)
11
TRAP (24-Bit Mode, Ext)
25
TRAP (16-Bit Mode, Ext)
18
ECALL (24-Bit Mode, Ext)
22
LCALL (16-Bit Mode, Ext)
13
LCALL (24-Bit Mode, Ext)
18
SCALL (16-Bit Mode, Ext)
13
SCALL (24-Bit Mode, Ext)
18
RET (24-Bit Mode, Ext)
22
RET (16-Bit Mode, Ext )
..
14
JNST,JST
4/8 Jump Not Takenl Jump Taken
JNH, JH
4/8 Jump Not Takenl Jump Taken
JGT,JLE
4/8 Jump Not Takenl Jump Taken
JNC,JC
4/8 Jump Not Takenl Jump Taken
JNVT, JVT
4/8 Jump Not Takenl Jump Taken
JNV,JV
4/8 Jump Not Takenl Jump Taken
JGE, JLT
4/8. Jump Not Takenl Jump Taken
JNE,JE
4/8 Jump Not Takenl Jump Taken
JBS,JBC
5/9 Jump Not TakenlJump Taken
DJNZ
5/9 Jump Not TakenlJump Taken
DJNZW
6/10 Jump Not TakenlJump Taken
CLR, NOT, NEG
3
DEC,INC
3
EXT
4
CLRB, NOTB
3
DECB,INCB
3
NEGB
3
EXTB
4
NORML
A-Inc
(Continued)
8
+
1 per Shift (9 for 0 Shift)
14-184
int:eL
8XC196KT QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TiMES)
Instruction
Direct
SHRL
7
SHLL
7
SHRAL
7
SHR
6
SHL
6
SHRA
6
SHRB
6
SHLB
6
SHRAB
6
+
+
+
+
+
+
+
+
+
CLRC
2
SETC
2
01
2
EI
2
OPTS
2
EPTS
2
CLRVT
2
NOP
2
RST
SKIP
10LPO
I
Immediate
I
Indirect
Normal
A·lnc
(Continued)
Indexed
Short
Extended
Long
1 per Shift (8 for 0 Shift)
1 per Shift (8 for 0 Shift)
1 per Shift (8 for 0 Shift)
1 per Shift (7 for 0 Shift)
1 per Shift (7 for 0 Shift)
1 per Shift (7 for 0 Shift)
1 per Shift (7 for 0 Shift)
1 per Shift (7 for 0 Shift)
1 per Shift (7 for 0 Shift)
20 (Includes Fetch of CCBO/CCB1)
3
8/25 (Proper Key/Improper Key)
PTS
Single Transfer
18
Burst Transfer
13
PWM Modes
15
A/O Scan Mode
( + 3 for Ext Reference, + 1 If XFER Count = 0)
(+ 7 for Each Transfer, 1 Minimum
+ 3 for Each Memory Controller Reference)
21/25
NOTES:
The timing figures are minimum execution times expressed as state times (one period of CLKOUT = two oscillator periods)
and are based on the following assumptions:
1. The opcode, along with any required operands, have been pre-fetched and reside in the instruction queue.
2. The bus controller operates with the 16-bit bus selected and without wait states for external memory references and prefetches. For instructions with indirect or indexed addressing, execution times separated by a slash are for instructions requiring a fetch from internal/external memory.
3. Times for jumps, calls and returns include the 4 state times required to flush the pre-fetch queue and to fetch the opcode
at the destination address. This is reflected in the jump taken/not-taken times shown in the table.
14-185
III
intet
8XC196KT QUICK REFERENCE
11.0 INTERRUPT TABLE
Name
Vector
Priority
NMI
203EH
32 (Highest)
PTS14
EXTINT Pin
205CH
31
PTS13
Reserved
205AH
30
INT15
Source
PTS12
ReceiveSIO
2058H
29
PTS11
Transmit SIO
2056H
28
PTS10
SSIO Channel 1 Transfer
2054H
27
PTS09
SSIO Channel 0 Transfer
2052H
26
PTS08
Command Buffer Full (SLP)
2050H
25
PTS07
Input Buffer Full (SLP)
204EH
24
PTS06
Output Buffer Empty (SLP)
204CH
23
PTS05
AID Conversion Complete
204AH
22
PTS04
EPAO
2048H
21
PTS03
EPA1
2046H
20
PTS02
. EPA2
2044H
19
PTS01
EPA3
2042H
18
PTSOO
EPA4-9, Overrun (EPAO-9),
CompareO-1, Timer Overflow
2040H
17
INT14
EXTINT Pin
203CH
16
INT13
Reserved
203AH
15
INT12
ReceiveSIO
2038H
14
INT11
Transmit SIO
2036H
13
INT10
SSIO Channel 1 Transfer
2034H
12
INT09
SSIO Channel 0 Transfer
2032H
11
INT08
Command Buffer Full (SLP)
2030H
10
N/A
UNIMPLEMENTED OPCODE
2012H
09
N/A
TRAP
2010H
08
INT07
Input Buffer Full (SLP)
200EH
07
INT06
Output Buffer Empty (SLP)
200CH
06
INT05
AID Conversion Complete
200AH
05
INT04
EPAO
2008H
04
INT03
EPA1
2006H
03
INT02
EPA2
2004H
02
INT01
EPA3
2002H
01
INTOO
EPA4-9, Overrun (EPAO-9),
CompareO-1, Timer Overflow
2000H
00 (Lowest)
14-186
8XC196KT QUICK REFERENCE
12.0 FORMULAS
State Time = 2 Oscillator Periods
TIJMP CalculationDestination = (!INDEX) AND INDEX-MASK) x 2
+
[TBASE)
EPA PrescalerP2
o
o
o
o
1
1
1
1
P1
o
o
1
1
o
o
1
1
PO
o
+ 1
1
+2
o
+4
1
+8
1
+ 16
+ 32
+ 64
Reserved
a
1
a
510 Baud RateModes 1, 2 and 3
SP BAUD = XTAl1 Frequency - 1
Baud Rate x 16
(B:2: O,SP_BAUD.15
=
S P BAUD -_ T1 ClK Frequency -1
Baud Rate x 8
(B > a, SP_BAUD.15
= a)
1)
Mode 0
SP_BAUD
= XTAl 1 Frequency - 1
Baud Rate x 2
SP BAUD
-
= T1 ClK Frequency - 1
Baud Rate
(B > a~ SP_BAUD.15 = 1)
(B> 0, SP_BAUD.15 = O)
5510 Baud RateSSIO.O - SS10.6
= XTAl 1 Frequency - 1
Baud Rate x 8
AIDSample States
= 4 x SAM + 1
(SAM = AD_TIME.5 - AD_TIME.7)
Conversion States = B x (CONV + 1) + 1.5
(CONV = AD_TIME.a - AD_TIME.4)
(B = 8 for 8-Bit Conversion)
(B = 1a for 1a-Bit Conversion)
Total Conversion Time
= State Time x [(4 x SAM) + (B x (CONV + 1» + 2.51
Programming Pulse WidthPPR
= «PPW) x (FOSC» - 144 + 32768
144
14-187
•
intel .
8XC196KT QUICK REFERENCE
13.0 RESET STATUS
SFR
Reset Value
AD_RESULT
7F80H
AD_COMMAND
OCOH
AD_TEST
OCOH
AD_TIME
OFFH
. SSIOO_BUF, SSI01_BUF
OOH
. SSIOO_CON, SSI01_CON
OOH
SSIO_BAUD (Baud Rate Control (Read»
OXXXXXXXB
SSIO_BAUD (Baud Rate Down Count (Write»
OOH
SBUF_RX, SBUF_ TX
OOH
SP_STAT
OBH
SP_CON
EOH
\
SP_BAUD
OOOOH
COMPO_CON, COMP1_CON
OOH
COMPO_TIME, COMP1_TIME
OOOOH
EPA1_CON, EPA3_CON
OOOOH
EPA><-CON (x = 0, 2, 4-9)
OOH
EPA><-TIME (x .; 0-9)
OOOOH
TIMER1, TIMER2
OOOOH
T1 CONTROL, T2CONTROL
OOH
EPA-MASK, EPA....:.MASK1
OOH
EPA-PEND, EPA-PEND1
OOH
EPAIPV
OOH
PO_PIN, P1_PIN, P3_PIN, P4_PIN, P6_PIN
XXH
P1_MODE, P6_MODE
OOH
P1_DIR,P5_DIR,P6_DIR
OFFH
P1_REG, P3_REG, P4_REG, P5_REG, P6_REG
OFFH
PLPIN, P5_PIN
1XXXXXXXB
PLMODE, P5_MODE
80H
PLDIR, PLREG
7FH
INT_MASK, INT_PEND
OOH
INT_MASK1, INT_PEND1
OOH
PTSSRV, PTSSEL
OOOOH
WSR
OOH
14-188
intel.,
8XC196KT QUICK REFERENCE
Pin States, during Reset, Idle and Powerdown
Pin Name
Reset
Idle
PO
RESET
wk1
wk1
wk1
ALE (P5.0)
wk1
(A)
(A)
INST (P5.1)
wkO
(A)
(A)
RD (P5.3), WR (P5.2),
SPLINT (P5.4)
wk1
(I)
(I)
BHE (P5.5)
wk1
(B)
(B)
READY (P5.6),
BUSW (P5.7)
wk1
(C)
(C)
EA,NMI
HZ
HZ
HZ
P3, P41 AD (EA = 0)
wk1
HZ
HZ
P3, P4/AD (EA = 1)
wk1
ODIO
ODIO
ACH/PO
HZ
HZ
HZ
wk1
(D)
(D)
P1
elk, LZ
(E)
(G)
P2.0-P2.6
wk1
(E)
(E)
P6.0-P6.7
wk1
(F)
(F)
Vpp
HZ
1, LZ
1, LZ
CLKOUT (P2.7)
XTAL1
HZ
HZ
HZ
XTAL2
ose, LZ
ose,LZ
(H)
NOTES:
(A) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1 and HLDA = 1, then LZ O. If P5_MODE.x = 1 and
HLDA = 0, then HZ.
(8) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1 and HLDA = 1, then LZ 1. If P5_MODE.x = 1 and
HLDA = 0, then HZ.
(C) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1, then HZ.
(D) If P1_MODE.x = 0, port is as programmed. If P1_MODE.x = 1, pin is as specified by P1_DIR and associated
peripheral.
(E) If P2_MODE.x = 0, port is as programmed. If P2_MODE.x = 1, pin is as specified by P2_DIR and associated
peripheral.
(F) If P6_MODE.x = 0, port is as programmed. If P6_MODE.x = 1, pin is as specified by P6_DIR and associated
peripheral.
(G) If P2_MODE.7 = 0, port is as programmed. If P2_MODE.7 = 1, then LZ O.
(H) If XTAL1 = 1, then LZ O. IF XTAL1 = 0, then LZ 1.
(I) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1, then pin is as specified by P5_DIR and associated
.
~~~
HZ
LZ
wk1
ODIO
osc
wkO
= High impedance
= Low Impedance
= Weakly pulled high
=
Open drain input/output
= Oscillator
= Weakly pulled low
14-189
•
int'et
October 1992
8XC196MC Quick Reference
Order Number: 272114-002
14-190
8XC196MC Quick Reference
CONTENTS
PAGE
CONTENTS
PAGE
1.0 MEMORY MAP ................... 14-192
8.0 INSTRUCTION SET SUMMARY .. 14-212
2.0 SFR MAP ......................... 14-193
9.0 INSTRUCTION
LENGTH/OPCODES ............... 14-215
3.0 SFR BIT SUMMARy .............. 14-194
4.0 PIN DEFINITION TABLE .......... 14-203
10.0 INSTRUCTION EXECUTION TIMES
(IN STATE TIMES) ................. 14-217
5.0 PACKAGE PIN ASSiGNMENT .... 14-204
11.0 INTERRUPT TABLE ............. 14-220
6.0 PIN DESCRiPTIONS .............. 14-207
12.0 FORMULAS ..................... 14-222
7.0 OPCODE TABLE ................. 14-210
13.0 RESET STATUS ................. 14-222
III
14-191
in1et
1.0
8XC196MC
MEMORY MAP
8XC196MC Memory Map
OFFFFH External Memory
06000H
05FFFH Internal ROM/EPROM or External Memory
02080H
0207FH Reserved Memory (Internal ROM/EPROM
02000H or External Memory)
01FFFH Internal Special Function Registers (SFRs)
01FOOH
01EFFH External Memory
00200H
Upper Register File
(Address with indirect or
indexed modes or through
windows.)
001FFH
00100H Reg'".e RAM )
OOOFFH
Register RAM
0OO18H
0OO17H
CPU SFRs
OOOOOH
)
Lower Register File
(Address with direct
indirect or indexed
modes.)
Register
File
8XC196MC Reserved Memory
0207FH
02074H
Reserved
02073H
02072H
Programming Voltages
02071H
02070H
Signature Word
0206FH
0205EH
Reserved
0205DH
02040H
Peripheral Transaction Server (PTS) Vectors
0203FH
02030H
Interrupt Vectors (Upper)
0202FH
02020H
Security Key
0201FH
0201EH
0201DH
0201CH
20H
Reserved
20H
Reserved
0201 BH
0201AH
02019H
02018H
20H
CCB1 (Chip Configuraton Byte 1)
20H
CCB (Chip Configuration Byte 0)
02017H
02014H
Reserved
02013H
02000H
Interrupt Vectors (Lower)
NOTE:
Reserved locations must be filled with OFFH unless noted.
14-192
int:eL
2.0
8XC196MC
SFR MAP
CORE SFR MAP
0019H:
001BH:
0017H:
0016H:
0015H:
0014H:
0013H:
0012H:
0011 H:
0010H:
OOOFH:
OOOEH:
OOODH:
OOOCH:
OOOBH:
OOOAH:
0009H:
0008H:
0007H:
0006H:
0005H:
0004H:
0003H:
0002H:
0001 H:
OOOOH:
SP(HI)
SP(LO)
reserved
reserved
reserved
WSR
INT_MASK1
INT_PEND1
reserved
reserved
reserved
reserved
reserved
reserved
reserved
WATCHDOG
INT_PEND
INT_MASK
PTSSRV(HI)
PTSSRV (LO)
PTSSEL(HI)
PTSSEL(LO)
reserved
reserved
ZERO_REG (HI)
ZERO_REG (LO)
PERIPHERAL SFR MAP
1FFFH:
1FFEH:
1FFDH:
1FFCH:
1FF8H - 1FFBH:
1FF7H:
1FF6H:
1FF5H:
1FF4H:
1FF3H:
1FF2H:
1FF1 H:
1FD7H - 1FFOH:
1FD6H:
1FD5H:
1FD4H:
1FD3H:
1FD2H:
1FD1H:
1FDOH:
1FCFH:
1FCEH:
1FCCH:
1FCAH:
1FC8H:
1FC6H:
1FC4H:
1FC2H:
1FCOH:
1FBFH:
1FBEH:
1FBDH:
1FBCH:
1FB7H - 1FBBH:
1FB6H:
1FB5H:
1FB4H:
1FB3H:
1FB2H:
1FB1H:
1FBOH:
1FAFH:
P4_PIN
P3_PIN
P4_REG
P3_REG
reserved
P5_PIN
USFR
P5_REG
reserved
P5_DIR
reserved
P5_MODE
reserved
P2_PIN
reserved
P2_REG
reserved
P2_DIR
reserved
PLMODE
reserved
WG_PROTECT
WG_CON
WG_COUNT
WG_RELOAD
WG_COMP3
WG_COMP2
WG_COMP1
WG_OUT
reserved
PI_PEND
reserved
PI_MASK
reserVed
PWM_PER_CNT
reserved
PWM_PERIOD
reserved
PWM1
reserved
PWMO
AD_TIME
1FADH:
1FAEH:
1FACH:
1FAAH:
1FA9H:
1FABH:
1FBOH-1FA7H:
1F7EH:
1F7DH:
1F7CH:
1F7AH:
1F79H:
1F7BH:
1F74H - 1F77H:
1F72H:
1F68H - 1F71 H:
1F66H:
1F65H:
1F64H:
1F62H:
1F61H:
1F60H:
1F5EH:
1F5DH:
1F5CH:
1F5AH:
1F59H:
1F58H:
1F50H - 1F57H:
1F4EH:
1F4DH:
1F4CH:
1F4AH:
1 F49H:
1F48H:
1F46H:
1F45H:
1F44H:
1F42H:
1F41 H:
1F40H:
reserved
AD_TEST
AD_COMMAND
AD_RESULT
P1_PIN
PO_PIN
reserved
TIMER2'
reserved
T2CONTROL
TIMER1 '
reserved
T1CONTROL
reserved
T1RELOAD
reserved
COMP3_TIME'
reserved
COMP3_CON
COMP2_TIME'
reserved
COMP2_CON
COMP1_TIME'
reserved
COMP1_CON
COMPO_TIME'
reserved
COMPO_CON
reserved
CAPCOMP3_TIt.IE'
reserved
CAPCOMP3_CON
CAPCOMPLTIME'
reserved
CAPCOMPLCON
CAPCOMP1_TIME'
reserved
CAPCOMP1_CON
CAPCOMPO_TIME'
reserved
CAPCOMPO CON
NOTE:
'These registers can only be addressed as word registers, not as separate byte registers.
14-193
III
inteL
8XC196MC
3,0 SFR BIT SUMMARY
IRC1
IRCO
0
0
0
0
CHIP CONFIGURATION BYTES
CCB (2018H)
msb
I LOC1 I LOCO I IRC1 I tRCO I ALE I WR
Isb
BWO
PO
CCB1 (201AH)
msb
l'
l'
0'
I
l'
I WO I BW1
tsb
tRC21
0'
I
'. These bits are reserved and must be written as indicated.
WD: Watch Dog Timer Disable.
o = Starts RUNNING immediately
and cannot be stopped.
I = Does not run until enabled in software.
BWI-BWO: Bus Width. These two bits separately,
OR along with BUSWIDTH pin determine the external bus width (8-bit or
16-bit wide).
BW1
BWO
BUSWIDTH (pin)
Bus Width
0
0
0
x
Illegal
1
X
16
1
0
x
8
1
1
0
8
1
1
1
16
Number of
IRC2
Wait States
0
X
1
Illegal
0
1
X
Illegal
1
0
0
1
1
0
1
2
1
1
0
3
1
1
1
Infinite
ALE: ALE/ADV
ALE = 0 The ALE pin becomes ADV
ALE = I The ALE pin remains ALE
WR: Write Strobe Mode/Standard Mode
WR = 0 The BHE pin becomes WRH and
WR becomes WRL
WR = I The BHE and WR are unchanged
PD:
Power Down Enable
PD = 0 The power down instruction does not
have any effect
PD = I The power down instruction is
enabled
WINDOW SELECT REGISTER
WSR (OO14H)
msb
I
LOCO:
Internal OTPROM Write Protect.
LOCO = I No Write protection.
LOCO = 0 Address locations
2000H to 5FFFH are write
protected.
LOCI:
Internal OTPROM Read Protect.
LOCI = I No read protection.
LOCI = 0 Address locations
2080H to 5FFFH are read
protected, also locations 2020H to
202FH are read/write protected.
IRC2, IRCI, IRCO: Internal Ready Control. They
limit the number of the wait states
to be asserted in the external bus
operation.
14-194
W7
I
W6
W7-WO:
00000000
OIXXXXXX
OOlXXXXX
OOOIXXXX
W5
I
W4
I
W3
I
W2
I
Isb
W1
WO
Window select bits
No windowing
32 Byte windowing
64 Byte windowing
128 Byte windowing
The window select bits are combined with the register address to access the RAM area in locations
0000 through IFFH or the upper SFR area in locations ICOOH through IFFFH.
8XC196MC
PROGRAM STATUS WORD
PSW
msb
Isb
1z
Z:
N:
V:
VT:
C:
PSE:
IE:
ST:
N
v
1
1
VT
c
1
ST
PSE
INTMASK
Zero Flag
Negative Flag
Overflow Flag
Overflow Trap Flag
Carry Flag
PTS Enable bit
Interrupt Enable bit
Sticky Bit Flag
PORT 2 AND PORT 5 CONTROL REGISTERS
Pn_MODE (n = 2
@
1FDOH, n = 5
@
AD COMMAND REGISTER
1FF1H)
AD_COMMAND (1FACH)
msb
1716151413121 1 101
Pn_REG (n
2
=
@
1FD4H, n
=
5
@
1FF5H)
0-3: Channel Select
4:
GO, indicates when to begin conversion
GO = 1 means start now
GO = 0 means EPA controls when to
start conversion.
5, 6: CONVERSION MODE:
00 = IO-bit
01 = 8-bit
10 = Threshold detect high
11 = Threshold detect low
7:
Reserved, write O.
7161514131211101
Pn_DIR (n
=
2
@
1FD2H, n
=
5 @ 1FF3H)
716151413121110
Pn_PIN (n
=
2
@
1FD6H, n
=
5 @ 1FF7H)
716151413121110
PIL-PIN contains the pin data delayed by
time.
'12
state
Each pin of Port 2 can be programmed to function in
one of the following modes:
Mode Dir Reg
0
0
0
0
0
1
1
0
1
0
1
1
X
X
0
Pull
Up
OFF
ON
OFF
OFF
Pull
Down
AD TIME REGISTER
AD_TIME (1FAFH)
Function
msb
Output 0
Output 1
Open Drain 0
Open Drain 1
(Input)
System
System System
Pin
Pin
Pin
X
X
X
X
Dir
0
0
1
1
Reg
0
1
0
1
Pull
Up
ON
OFF
ON
OFF
OFF
ON
OFF
OFF
Pull
Down
ON
OFF
ON
OFF
Isb
7 16 15 1
0-4:
13 12 1 1 10
Conversion Time = n + 1 state times (n = 2
4
to 31).
5-7: Sample Time = 4n
7).
.
+
1 state times (n = 1 to
AD RESULT REGISTER (READ)
Each pin of Port 5 can be programmed to function in
one of the following modes.
Mode
Isb
176151413121101
Function
AD_RESULT (1FAAH)
msb
Isb
15-6
0-3:
4:
Channel Number
Busy
0= AD is idle
1 = Conversion is in progress
5:
Reserved
6-15: IO-bit AD result
Output 0
Output 1
Open Drain 0
Open Drain 1
(Input)
14-195
intel~
8XC196MC
AD RESULT REGISTER (WRITE)
AD_RESULT (1FAAH)
msb
19b
15-6
o
7-5
I
0-3:
4:
Channel Number
Busy
0= AD is idle
1 = conversion is in progress
5-7: Reserved, write 0
8-15: SAR value. Writing to the AD_RESULT register selects the threshold detection value. Presetting the
ASR is required before selecting one of the threshold detect modes.
AD_TEST (1FAEH)
TIMER 1 CONTROL REGISTER
msb
T1 CONTROL (1 F78H)
msb
I CE
UD 1 M2
1
I.
Isb
M1
1 MO
1 P2
1
P1
1
PO
7
b4
b3
0
0
1
0
1
0
X
1
5-7: Reserved
o
o
M2 M1 MO Clock Source Clock Direction
0
1
0
1
0
0
1
1
0
1
1
UD Bit
UD Bit
External Pin
External Pin
Internal
External
Internal
External
Reserved
Reserved
Quadrature
Clocking(l)
NOTE:
1. The counter input clock and the count direction is
taken from the quadrature clocking circuit.
P2 PI
po: EPA Clock control bits.
P2 P1 PO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Resolution
Input
Divide By
(at16 MHz)
1
2
4
8
16
32
64
1
250 ns
500 ns
1 J.l-s
2 J.l-s
4 J.l-s
8 J.l-s
16 J.l-s
enable T1 RELOAD
1
5
1
4
1
3
1
0-1: Reserved
2-4: Adjust offset
I = timer/counter enabled
o = timer/counter disabled
UD:
1 = count up
o = count down
M2 Ml MO: EPA Clock source and direction mode
select.
0
0
1
Isb
6
1
CE:
0
0
0
0
1
1
1
1
14-196
b2
O-no change
1-add 2.5 mV
O-sub 2.5 mV
1-sub 5.0 mV
X-reserved
2
1
1
1
0
1
8XC196MC
TIMER 2 CONTROL REGISTER
CAPTURE/COMPARE CONTROL REGISTERS
T2 CONTROL (1F7CH)
msb
I CE
Isb
I
UD I M2 I M1 ! MO ! P2 ! P1
!
PO
msb
TB
I
Isb
CE
I = timer/counter enabled
timer/counter disabled
UD:
I = Count up
o = Count down
M2MI MO: EPA Clock source and direction mode
select.
CE:
o=
M2
M1
MO
Clock
Source
Clock
Direction
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
Internal
Reserved
Reserved
Reserved
T1 Over/Underflow
T1 Over/Underflow
Reserved
UDBit
P2 PI
po:
TB:
P1
PO
UD Bit
Timer 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Input
Divide By
Resolution
(at 16 MHz)
1
2
4
8
16
250 ns
500 ns
1 IJ-s
2 IJ-s
4 IJ-s
8 IJ-s
16 IJ-s
32
64
Reserved
MO
RE
PFE I ROT ION/RT!
n
Address
0
1F40H
1
1F44H
2
1F48H
3
1F4CH
I = selects TIMER2 as time base
selects TIMER I as time base
CE:
I = enables compare mode
o = disables capture mode
MI, MO: Mode Selects
On Capture Mode (CE = 0)
00 = no operation
01 = capture - edge
10 = capture + edge
II = capture ± edge
On Compare Mode (CE = I)
00 = no compare
01 = clear output pin
10 = set output pin
11 = toggle output pin
PFE:
I
peripheral function enable
o = no action
RE:
I = output event is automatically enabled after execution
o = output event is disabled after execution
ROT:
Reset Opposite Timer
On Capture Mode (CE = 0)
I = reset opposite timer
o = no action
On Compare Mode (CE = I)
I = reset opposite timer
o = reset selected timer
Timer prescalar control
P2
M1
o=
ON/RT: Overwrite New/Reset Timer
On Capture Mode (CE = 0)
I = old data of COl_BUFF lost on
data overrun
o = new data lost on data overrun
On Compare Mode (CE = I)
I = reset timer (selected by TB and
ROT)
0= no action
14-197
int:el..
8XC196MC
CAPTURE/COMPARE CONTROL REGISTERS (Continued)
TB
CE
M1
MO
RE
PFE
ROT
ON/RT
0
0
0
0
0
0
0
0
0
0
0
1
0
1
-
1
X
-
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
X
1
1
X
-
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation (No Interrupt)
Capture on Positive Transition
Capture on Negative Transition
Capture on Either Transition
Reset Opposite Timer
Reset Opposite Timer
Peripheral Function Enable
Peripheral Function Enable
Generate Interrupt
Generate Interrupt
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
X
X
X
X
X
Reset Output Pin
Set Output Pin
Toggle Output pin
Reset Associated Time Base Timer
Reset Opposite Time Base Timer
Peripheral Function Enable
Generate Interrupt
Generate Interrupt Only (Soft Timer)
Operating Mode
Capture:
X
X
X
X
X
X
X
X
X
X
X
1
1
X
0
1
1
1
0
1
X
X
X
X
X
X
X
X
0
0
1
1
X
X
Compare:
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
0
0
X: Bit selects additional options
-: Bit is not used in Capture Mode
COMPARE CONTROL REGISTER
lab
msb
TB
TB:
CE:
CE
1=
0=
1=
0=
M1
MO
RE
PFE I ROT ION/RTI
n
ADDRESS
0
1F58H
1
1F5CH
2·
1F60H
3
1F64H
TIMER2 as time base
TIMERI as time base
enables comparator
disables comparator
Ml, MO: 00 =
01 =
10 =
11 =
PFE:
1=
0=
RE:
1 =
ROT:
no action on output pin
clear output pin
set output pin
toggle output pin
peripheral function enable
no action
output event is automatically re-enabled after execution
o = output event is disabled after execution
1 = reset opposite timer (timer not select.
ed by TB)
o = reset selected timer (selected by TB)
ON/RT:.1 = reset timer (selected by ROT)
o = no action
14-198
intel~
8XC196MC
COMPARE CONTROL REGISTER (Continued)
TB
CE
M1
MO
RE
PFE
ROT
RT
Operating Mode
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
X
0
1
1
X
X
X
X
X
1
0
1
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
0
X
X
X
X
0
1
X
X
X
X
X
X
X
1
1
X
X
0
No Operation (No Interrupt)
Reset Output Pin
Set Output Pin
Toggle Output Pin
Reset Associated Time Base Timer
Reset Opposite Time Base Timer
Peripheral Function Enable
Generate Interrupt
Generate Interrupt Only (Soft Timer)
0
..
X: Bit selects additional options
COMPARE TIME REGISTER
Scheduled time for programmed event. This register must only be read and written as a word.
msb
14
15
13
12
11
10
I
9
8
I,
7
I
6
n
ADDRESS
0
1F42H
1
1F46H
2
1F4AH
3
1F4EH
PERIPHERAL INTERRUPT MASK REGISTER
1- I
-:
WG:
TF2:
TFl:
- I
WG
I
TF2
5
I
4
I
3
I
Isb
2
o
I
II
PERIPHERAL INTERRUPT PENDING REGISTER
PI_MASK (1FBCH)
msb
I
PI_PEND (1FBEH)
Isb
msb
TF1
1- I
Reserved, write 0
Waveform Generator interrupt mask
Timer/Counter 2 overflow interrupt mask
Timer/Counter 1 overflow interrupt mask
-:
WG:
TF2:
TFl:
NOTE:
A logical 1 in the bit position allows the corresponding function to set its interrupt pending flag.
Isb
TF2
TF1
Reserved, write 0
Waveform Generator status flag
Timer/Counter 2 overflow status flag
Timer/Counter 1 overflow status flag
NOTE:
This register can be read but not written. When
read, all bits in this register are reset. Therefore,
the value of the register must be stored in a shadow register if more than one bit of this register is
used.
14-199
int:et
8XC196MC
WAVE GENERATOR CONTROL REGISTER
WG_CON (1FCCH)
Isb
msb
I- I
-
I M1 I MO I CS I
EC
I
09
I
08
I
07
I
06
I
05
I
04
I
03
I
02
I
01
I
00
I
-: Reserved, write 0
MI, MO: Mode bits
Mode Bit
M1
MO
PWM
Output
Counter
Operation
0
1
0
0
0
1
Center
Center
Up/Dn
Up/Dn
2
3
1
1
0
1
Edge
Edge
Mode
cs:
EC:
Reload Triggering Signal
for WG_COMPn
for WG_OUT (Note 1)
(WG_Countlmatch
(WG_Countlmatch
or (WG_Count) = 1
(WG_Countlmatch or
EPA event
(WG_Countlmatch
(WG_Countlmatch
or (WG_Countl = 1
(WG_Countlmatch
(WG_Countlmatch
or EPA event
Up
Up
D9-DO: 10 bit Down Counter value
Counter Status
I = up counting
o = down counting
Enable/Disable Counter (WG_Count)
I = enable counting
o = disable counting
NOTE:
1. The WG_OUT reload trigger signals are enabled
when the SYNC bit in the Output Control Register
(WG_OUT) is 1.
WG COMPARE REGISTER
msb
15
14
13
12
11
10
9
I
8
I
7
I
6
n
Address
1
1FC2H
2
1FC4H
3
1FC6H
I
5
I
4
I
3
I
2
I
Isb
o
I
WG_COMP controls the duty cycle of the waveform generator outputs.
WG RELOAD REGISTER
WG_RELOAD (1FC8H)
19b
msb
15
14
13
12
11
o
10
14-200
I
inteL
8XC196MC
WAVE GENERATOR OUTPUT CONTROL REGISTER
WG_OUT (1FCOH)
I
msb
OPl
I
OPI:
OPO:
SYNC:
OPO
I
SYNC
I
I
PEl
PEO
I
PH32
I
PH22
I
PH12
Output Polarity for positive-phase outputs
I = P6.1, P6.3 and P6.5 are active-high
o = P6.1, P6.3 and P6.5 are active-low
Output Polarity for negative-phase outputs
I = P6.0, P6.2 and P6.4 are active-high
o = P6.0, P6.2 and P6.4 are active-low
Synchronize Loading of Output Buffer
I = outputs are synchronized with
Reload triggering signal for
WG_COMPn
0= outputs are not synchronized with
WG_COMPn
PHn2
PHn1
PHnO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I
Pl
I
PH3l
I
PH30
I
PH2l
I
PH20
I
PHll
I
lab
PH10
I
. PEl, PEO: Enable P6.7, P6.6 (respectively) as PWM
output
PI, PO:
P6.7, P6.6 (respectively) output value
PEn
Pn
Pin Output
0
0
1
0
1
X
0
1
PWM output
PH12
PH22
PH32
OP~
Low
Low
High
High
Low
Low
PWM
PWM
Low
High
Low
High
Low
PWM
Low
PWM
High
High
Low
Low
High
High
PWM
PWM
PH10
PH20
PH30
PH11
PH21
PH31
WGn
OP1 = 1
OP1 = 0
WG PROTECTION CONTROL REGISTER
--
control PS.O and PS.1
control PS.2 and PS.3
control PS.4 and PS.5
WGn
= 1
OP~ = 0
(n = 1, 2, or 3)
High
Low
High
Low
High
PWM
High
PWM
•
PTS VECTORS PTSVEC, PTSVEC1
WG_PROTECT (1FCEH)
mab
I
PO
Each PTS vector points to internal RAM space and
must be aligned to a quad word boundary.
lab
1- I
msb
I, , , ,
ES: Enable Sampling Circuitry
I = protection/interrupt triggered by sampling
o = protection/interrupt triggered by edge
IT: Interrupt Type control bit
I = rising edge/high trigger
o = falling edge/low trigger
DP: DisablelEnable Protection Circuit
1 = disable protection output
o = enable protection output
EO: Enable/Disable Output. Must be set when
port is used as output
I = enable output
o = disable output
Isb
r
,Ib b b b b b blo 0 01
r ... r Reserved (Write 0)
b ... b Upper bits of the to-bit pointer to the PTS
Control Block located in Internal Ram.
14-201
inlet
8XC196MC
PTSCON-GENERAL TRANSFER MODES
I
msb
M2
I
M1
I
MO
I B/W I
SU
I ou I
SI
I
PTSCON1-ASIO MODE
Isb
msb
I
01
M2, Ml, MO: 000 = PTS Burst Transfer Mode
100 = PTS Single Transfer Mode
B/W:
1 = Transfer in bytes
o = Transfer in words
SU:
1 = Update PTSSRC at end of each
PTS cycle
0= No update
DU:
1 = Update PTSDST at end of each
PTS cycle
o = No update
SI:
1 = Source address auto-increment
o = No auto-increment
DI:
1 = Destination address autoincrement
o = No auto-increment
msb
M2
M1
MO
o
I
UPOT
I
0
I
1
M2
I
M1
MO
SA
o
I
0
I
PEN
I
0
I
0
I
0
I
FE
I
Isb
TPAR
I
I
msb
I
0
I
0
I
0
I
0
I
0
I
0
I
TRG
I
Isb
0
I
TRC: Transmit/Receive Control
. 1 = Receive/Transmit bit on first PTS request and every other one thereafter
o = ReceiveiTransmit data bit on second
PTS request and every other one thereafter. Throughout the transmission/reception, this bit is toggled.
0:
Write 0 to these bits
PTSCON-SERIAL PORT MODES
msb
I
PTSCON1-5SIO MODE
M2, MI, MO: 110 = PTS AID mode
UPDT:
1 = Update SRC/DST pointer
0= No update
0:
Write 0 to these bits
1:
Write 1 to these bits
I
RPAR
Parity Enable bit
I = Enable
0= Disable
FE:
Framing Error flag
1 = The Stop Bit received was not a I. It
must be reset at the start of every reception.
0= No Error
TPAR: Transmit Parity Control. This bit must be
initialized at the start of every reception.
1 = Odd
0= Even
RPAR: Receive Parity Control/Status. This bit
has two functions, control and status. Before reception, initialize for Even (0) or
Odd (1) parity. If at the end of a reception
this bit is a 1, a parity error has occurred.
This bit must be initialized before the start
of each reception.
0:
Write 0 to these bits
Isb
1
I
PEN:
PTSCON-A/D MODE
I
0
Isb
M2, Ml, MO: 011 = Transmit mode
001 = Receive mode
SA:
1 = Synchronous mode
o = Asynchronous mode
MAJ:
1 = Enable Majority 'Sample mode
1 = Disable Majority Sample mode
0:
Write 0 to these bits
14-202
int:eL
4.0
8XC196MC
PIN DEFINITION TABLE
8XC196MC Package Pin Assignments
PLCC
Pin #
OFP
Pin #
SDIP
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
73
74
75
76
77
78
79
80
63
64
1
2
3
4
5
6
7
8
9
10
11
12
6
7
10
8
11
9
1
2
3
4
5
12
13
14
15
16
13
14
15
16
17
18
19
20
21
22
23
17
18
19
20
21
22
23
24
24
25
26
27
28
29
30
27
28
25
26
29
30
31
32
Description
PLCC
Pin #
OFP
Pin #
P5.4
P5.6/READY
P5.1/INST
Vss
P5.0/ALE
Vpp
P5.3/RD
P5.5/BHE
NC
P5.2/WR
P5.7/BUSW
P4.7/AD15
P4.6/AD14
Vee
P4.5/AD13
CLKOUT
P4.4/AD12
P4.3/AD11
P4.2/AD10
P4.1/AD09
P4.0/AD08
NC
NC
P3.7/AD07
P3.6/AD06
P3.5/AD05
P3.4/AD04
P3.3/AD03
P3.2/AD02
P3.1/AD01
P3.0/ADOO
NC
RESET
NMI
NC
EA
Vss
Vss
Vee
P6.5/WG3
P6.4/WG3
P6.3/WG2
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
.59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
14-203
SDIP
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
VSS
P6.2/WG2
P6.1/WG1
P6.0/WG1
P1.3/ACH11
P1.2/ACH10
Vss
P1.4/ACH12
P1.1/ACH9
P1.0/ACH8
PO.7 I ACH7 IPMODE.3
PO.61 ACH6/PMODE.2
AGND
VREF
PO.51 ACH5/PMODE.1
P0.41 ACH4/PMODE.0
PO.3/ACH3
PO.2/ACH2
PO.1/ACH1
PO.O/ACHO
NC
P2.0/CAPCOMPO/PVER
P2.1 ICAPCOMP1 IPALE
NC
NC
P2.2/CAPCOMP2/PROG
P2.3/CAPCOMP2
P2.7/COMPARE3
NC
NC
P2.4/COMPAREOI AINC
P2.5/COMPARE1/PACT
P2.6/COMPARE2/CPVER
P6.7/PWM1
P6.6/PWMO
NC
NC
NC
XTAL2
XTAL1
VSS
EXTINT
II
8XC196MC
5.0
PACKAGE PIN ASSIGNMENT
Package Prefix Identification Table
Package
Device
N87C196MC
PLCC
EIAJQFP
S87C196MC
SDIP
U87C196MC
PS.6/READY
Vss
PS.O/ALE
PS.4
EXTINT
vpp
PS.3!Ri5
Vss
ps.s/B'iiE
XTALI
PS.2!WR
XTAL2
PS.7/BUSW
P6.6/PW~O
• P4.6/ADI4
P6.7/PW~1
• P4.S/ADI3
P2.6/CO~PARE2/CPVER
• P4.7/ADIS
P2.5/CO~PAREI /Pill
vee
P2.4/CO~PAREO,lAi'Nc'
P4.4/ADI2
P2.3/CAPCO~3
P4.3/ADll
P2.2/CAPCO~2!PROG
P4.2/AD10
P4.1/AD09
P4.0/AD08
INTEL
87C196MC
P2.1/CAPCO~I/PALE
P2. 0 / CAPCO~O /PVER
PO.O/ACHO
P3.7/AD07
PO. I/ACH 1
P3.6/AD06
PO.2/ACH2
P3.S/AD05
PO.3/ACH3
P3.4/AD04
PO.4/ACH4/P~ODE.O
P3.3/AD03
PO.S/ACHS/P~ODE.l
P3.2/AD02
P3.1/ADOI
VREF'
AGND
P3.0/ADOO
PO.6/ACH6/P~ODE.2
po. 7 / ACH7 /P~ODE.3
RESET
N~I
Pl.0/ACH8
EX
Pl.l/ACH9
Vss
Pl.2/ACH10
Vee
Pl.3/ACHll
P6.S/WG3
P6.0!WGT
P6.4!ffi
P6.1/WGI
P6.3/WG2
P6.2!ffi
272114-1
NOTE:
'The pin sequence is correct.
64·Lead SDIP Package Pinout
14-204
intel~
8XC196MC
'"
""
it
u
"...-<
N
~
(II~
ii: ~
".,;....o..
0..
~~ ...."
.,;
'" .,;'" > "-
(II
...J
N
.,;
t-
""-<
Z
0
U
Z
"-
"-
'"
0..'"
>'"
>O
:::E
is
~
"- '"
" ...
.,; .,; .,;
0..
"-
'"
0
"-
tZ
;::
X
""
...J
0..
N
...J
'" -< -<
tX
>'" tX
:::E
U
0..
0..
"U; "....U; "N
U
Z
U
Z
U
Z
0..
:::E
0
~
0..
0..
P4.7/AD15
P2.5/COt.tPARE 1/PACT
P4.6/AD14
P2.4/COt.tPAREOjAiNC
NC
Vee
71
P4.5/AD13
NC
CLKOUT
P2. 7/COt.tPARE3
P4.4/AD12
P2.3/CAPCOt.tP3
P2.2/CAPCOt.tP2/PROG
P4.3/AD11
INTEL
P4.2/AD10
P4.1/AD09
NC
NC
87C196MC
P4.0/AD08
NC
Top view looking down
NC
on component side
P3.7/AD07
P2.1/CAPCOt.tP1/PALE
P2.0/CAPCOt.tPO/PVER
NC
PO.O/ACHO
of PC board
61
P3.6/AD06
PO.1/ACH1
P3.5/AD05
PO.2/ACH2
P3.4/AD04
PO.3/ACH3
P3.3/AD03
PO.4/ACH4/PMODE.O
P3.2/AD02
PO.5/ ACH5/PMODE. 1
P3.1/AD~1
VREF
AGND
P3.0/ADOO
PO.6/ ACH6/PMODE.2
NC
I~
'i ~
z
liS >'" >'" >"'"~ ~~ C> >'""'~C>~
"'"u; ...u; "'"u; u;
(f)
V)
U
(,!)
(!)
0
N
::t:
~
N
0..
0..
0..
0..
u
u;
"-
::t:
u
-< -<
"! ~
" "
0..
0..
-
'" N
::t:
>'"
u
-<
QI
::t:
U
co
::t:
U
-< -<
q
'"
LJ
C
0
:::E
""';Ii: " "Ii: "....
-<
"....c:i
0..
0..
::t:
U
0..
272114-2
NOTE:
NC means No Connect. Do not connect these pins.
84-Lead PLCC Package Pinout
14-205
•
8XC196MC
~~
...
...J
..:
......
.,; .,;
'" !I:~I>- >~
l>- I>- >
It)
>-
e
0-
'"z
"
:;;
l>-
0
:s
~
......
'"CD -ot z
.,; .,; ;::
~
:::;
0-
I>-
IL
~..:
1:i >
~
I>-
......
N
...J
..:
~
CD
(J
Z
(J
(J
Z
Z
.,;
I>-
PS.2/WR
P6.7/PWt.ll
PS.7/BUSW
P2.6/COt.lPARE2/CPVER
P4.7/ADI5
P2.5/COt.lPAREI/PAc'f
61
P4.6/ADI4
P2.4/COt.lPAREO,IAiNC
NC
Vee
P4.S/ADI3
NC
CLKOUT
P2. 7/COt.lPARE3
P4.4/ADI2
P2.3/CAPCOt.lP3
P4.3/ADll
P4.2/AD10
P4.1/AD09
P4.0/AD08
P3.7/AD07
P3.6/AD06
P2.2/CAPCOt.lP2/PROG
INTEL
NC
NC
87C196MC
P2.1/CAPCOt.lPI/PALE
Top view looking
down on
P2.0/CAPCOt.lPO/PVER
51
NC
P3.5/AD05
component side of
PO.O/ACHO
P3.4/AD04
PC board
PO.l/ACHI
P3.3/AD03
PO.2/ACH2
P3.2/AD02
PO.3/ACH3
P3.I/ADOI
PO.4/ACH4/Pt.lODE.O
P3.0/ADOO
PO.S/ACH5/Pt.lODE.1
NC
VREF
RESET
AGND
Nt.l1
PO.6/ACH6/Pt.lODE.2
EA
41
PO.7 /ACH7 /Pt.lODE.3
272114-3
NOTE:
NC means No Connect. Do not connect these pins.
80-Lead Shrink EIAJQFP (Quad Flat Pack)
14-206
int'et
6.0
8XC196M~
PIN DESCRIPTIONS
Symbol
Name and Function
ACHO-ACH12
(PO.0-PO.7, P1.0-P1.4)
Analog inputs to the on-chip AID converter. ACHO-7 share the input pins
with PO.0-7 and ACH8-12 share pins with P1.0-4. If the A/D is not used,
the port pins can be used as standard input ports.
ANGND
Reference ground for the A/D converter. Must be held at nominally the
same potential as Vss.
ALE/ ADV (PS.O)
Address Latch Enable or Address Valid output, as selected by CCR. Both
options allow a latch to demultiplex the address/data bus. When the pin is
ADV, it goes inactive (high) at the end of the bus cycle. When the pin is ALE,
the address can be latched on the falling edge. ALE/ ADV is active only
during external memory accesses. Can be used as standard I/O when not
used as ALE/ ADV.
BHE/WRH (P5.5)
Byte High Enable or Write High output, as selected by the CCA. BHE = 0
selects the bank of memory that is connected to the high byte of the data
bus. If the WRH function is selected, the pin will go low when the bus cycle is
writing to an odd memory location. BHE/WRH is only valid during 16-bit
external memory cycles. Can be used as standard I/O when not used as a
bus control signal.
BUSWIDTH (PS.7)
-
. Input for bus width selection. If CCR bits 1 and 2 = 1, this pin dynamically
controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as
standard I/O when not used as BUSWIDTH.
CAPCOMPO-CAPCOMP3
(P2.0-P2.3)
The EPA Capture/Compare pins. These pins share P2.0-P2.3. If not used·
for EPA, they can be configured as standard I/O pins.
CLKOUT
Output of the internal clock generator. The frequency is
frequency. It has a SO% duty cycle.
COMPAREO-COMPARE3
(P2.4-P2.7)
The EPA Compare pins. These pins share P2.4-P2.7. If not used for EPA,
they can be configured as standard I/O pins.
EA
% of the oscillator
External Access enable pin. EA = 0 causes all memory accesses to be
. external to the chip. EA = 1 causes memory accesses from locations
2000H to SFFFH to be from the on-chip OTPROM/ROM. EA = 12.SV
causes execution to begin in the programming mode. EA is latched at reset
EXTINT
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH. The input may be selected to be a
positive/negative edge or a high/low level.
INST (PS.1)
INST is high during the instruction fetch from the external memory and
throughout the bus cycle. It is low otherwise. This pin can be configured as
standard I/O if not used as INST.
NMI
A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH. If not used, it should be tied to Vss. May
be used by Intel Evaluation boards.
PORTO
8-bit high impedance input-only port. Also used as AID converter inputs.
PortO pins should not be left floating. These pins also used to select
programming modes in the OTPROM devices.
PORT1
S-bit high impedance input-only port. P1.0-P1.4 are also used as AID
converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock
input and direction select respectively.
14-207
•
intel .
~XC196MC
6.0 PIN DESCRIPTIONS
(Continued)
Symbol
Name and Function
PORT2
8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O
pins (CAPCOMPO-S and COMPAREO-S).
PORTS,
PORT4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared
with the multiplexed address/data bus which uses strong internal pullups.
PORT5
8-bit bidirectional I/O port. 7 of the pins are shared bus control signals (ALE,
INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard 110.
PORTS
8-bit output-only port. PS.S and PS.7 output PWM and the rest are used as the
Wave Generator outputs. Can be used as standard Qutput ports.
PWMO,PWM1
(P6.S, PS.7)
Programmable duty cycle, programmable frequency Pulse Width Modulator
pins. The duty cycle has a resolution of 25S steps, and the frequency can vary
from 122 Hz to S1 KHz (1S MHz input clock). Pins may be configured as
standard output if PWM is not used.
RD (P5.S)
Read signal output to external memory. RD is low only during external memory
reads. Can be used as standard I/O when not used as RD.
.
READY (P5.S)
Ready input to lengthen external memory cycles. If READY = 0, the memory
controller inserts wait states until the next positive transition of ClKOUT
occurs with READY = 1. Can be used as standard I/O when not used as
READY.
RESET
Reset input to and open drain output from the chip. Held low for at least 1S
state times to reset the chip. Input high for normal operation. RESET has an
Ohmic internal pullup resistor.
T1 ClK (P1.2)
Timer 1 Clock input. This pin has two other alternate functions: ACH1 0 and
P1.2.
T1 DIR (P1.S)
Timer 1 Direction input. This pin has two other alternate functions: ACH11 and
P1.S.
Vpp
The programming voltage is applied to this pin. It is also the timing pin for the
return from Power Down circuit. Connect this pin with a 1 ,...F capacitor to VSS
and a 1 Mn resistor to Vee. If the Power Down feature is not used, connect
the pin to Vee.
WG1-WGS/WG1-WGS
(PS.0-PS.5)
S-phase output signals and their complements used in motor control
applications. The pins can also be configured as standard output pins.
WR/WRl (P5.2)
Write and Write low output to external memory. WR will go low every external
write. WRl will go low only for external writes to an even byte. Can be used as
standard I/O when not used as WR/WRL.
XTAL1
Input of the oscillator inverter and the internal clock generator. This pin should
be used when using an external clock source.
XTAl2
Output of the oscillator inverter.
14-208
intel .
8XC196MC
Programming Mode Pin Definitions
Name
Name and Function
PMODE.0-3
(PO.4-7)
Programming Mode Select. Determines the EPROM programming algorithm
that is performed. PMODE is sampled after a chip reset and should be static
while the part is operation.
PALE
(P2.1)
Programming ALE Input. Accepted by an 8XC196MC that is in slave
programming mode. Used to indicate that port 3 and 4 contain a command/
address.
PROG
(P2.2)
Programming. Falling edge latches data on PBUS and begins programming.
Rising edge input ends programming.
PACT
(P2.5)
Programming Active. Use to indicate when programming activity is complete.
PVER
(P2.0)
Programming Verification. Signal is low after rising edge of PROG if they
programming was not successful.
AINC
(P2.4)
Auto Increment. Active low input enables the auto increment mode. Auto
increment will allow reading or writing of sequential EPROM locations without
address transactions across the PBUS for each read or write.
PORTS
3 and 4
(During Programming)
Address/Command/Data Bus. Used to pass commands, addresses and data
to and from 8XC196MC. Also used in the auto programming mode as a regular
system bus to access external memory.
CPVER
(P2.6)
Cumulative Program Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.
Programming Mode PMODE Values
PMODE
Programming Mode
Reserved
0
1-4
Reserved
5
Slave Programming
6
ROM Dump
7-8
Reserved
9
UPROM Programming
OAH-OBH
Reserved
OCH
Auto Programming
ODH
PCCB, Programming
OEH-OFH
Reserved
14-209
•
intel .
8XC196MC
7.0 OPCODE TABLE
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
SKIP
CLR
NOT
NEG
XCH
DEC
EXT
INC
SHR
SHL
SHRA
XCH
SHRL
SHLL
SHRAL
NORMAL
RESERVED
CLRB
NOTB
NEGB
XCHB
DECB
EXTB
INCB
SHRB
SHLB
SHRAB
XCHB
RESERVED
RESERVED
RESERVED
RESERVED
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SJMP
SCALL
SCALL
SCALL
SCALL
SCALL
SCALL
SCALL
SCALL
JBC
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
JBC
JBC
JBC
JBC
JBC
JBC
JBC
JBS
JBS
JBS
JBS
JBS
JBS
JBS
JBS
AND DIRECT (3 OPS)
AND IMMEDIATE (3 OPS)
AND INDIRECT (3 OPS)
AND INDEXED (30PS)
ADD DIRECT (3 OPS)
ADD IMMEDIATE (3 OPS)
ADD INDIRECT (3 OPS)
ADD INDEXED (3 OPS)
SUB DIRECT (3 OPS)
SUB IMMEDIATE (3 OPS)
SUB INDIRECT (3 OPS)
SUB INDEXED (3 OPS)
MULU DIRECT (3 OPS)
MULU IMMEDIATE (3 OPS)
MULU INDIRECT (3 OPS)
MULU INDEXED (3 OPS)
AN DB DIRECT (3 OPS)
ANDB IMMEDIATE (3 OPS)
ANDB INDIRECT (3 OPS)
ANDB INDEXED (3 OPS)
ADDB DIRECT (30PS)
ADDB IMMEDIATE (3 OPS)
ADDB INDIRECT (3 OPS)
ABBD INDEXED (3 OPS)
SUBB DIRECT (3 OPS)
SUBB IMMEDIATE (3 OPS)
SUBB INDIRECT (3 OPS)
SUBB INDEXED (3 OPS)
MULUB DIRECT (3 OPS)
MULUB IMMEDIATE (3 OPS)
MULUB INDIRECT (3 OPS)
MULUB INDEXED (3 OPS)
AND DIRECT (2 OPS)
14-210
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
AND IMMEDIATE (2 OPS)
AND INDIRECT (2 OS)
AND INDEXED (2 OPS)
ADD DIRECT (2 OPS)
ADD IMMEDIATE (2 OPS)
ADD INDIRECT (2 OPS)
ADD INDEXED (2 OPS)
SUB DIRECT (2 OPS)
SUB IMMEDIATE (2 OPS)
SUB INDIRECT (2 OPS)
SUB INDEXED (20PS)
MULU DIRECT (2 OPS)
MULU IMMEDIATE (20PS)
MULU INDIRECT (2 OPS)
MULU INDEXED (2 OPS)
ANDB DIRECT (2 OPS)
ANDB IMMEDIATE (2 OPS)
AN DB INDIRECT (2 OPS)
AN DB INDEXED (2 OPS)
ADDB DIRECT (2 OPS)
ADDB IMMEDIATE (20PS).
ADDB INDIRECT (2 OPS)
ADDB INDEXED (2 OPS)
SUBB DIRECT (2 OPS)
SUBB IMMEDIATE (2 OPS)
SUBB INDIRECT (2 OPS)
SUBB INDEXED (20PS)
MULUB DIRECT (2 OPS)
MULUB IMMEDIATE (2 OPS)
MULUB INDIRECT (2 OPS)
MULUB INDEXED (20PS)
OR DIRECT
OR IMMEDIATE
OR INDIRECT
OR INDEXED
XOR DIRECT
XOR IMMEDIATE
XOR INDIRECT
XOR INDEXED
CMPDIRECT
CMP IMMEDIATE
CMP INDIRECT
CMP INDEXED
DIVU DIRECT
DIVU IMMEDIATE
DIVU INDIRECT
DIVU INDEXED
inteL
8XC196MC
7.0 OPCODE TABLE (Continued)
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
ORB DIRECT
ORB IMMEDIATE
ORB INDIRECT
ORB INDEXED
XORB DIRECT
XORB IMMEDIATE
XORB INDIRECT
XORB INDEXED
CMPB DIRECT
CMPB IMMEDIATE
CMPB INDIRECT
CMPB INDEXED
DIVUB DIRECT
DIVUB IMMEDIATE
DIVUB INDIRECT
DIVUB INDEXED
LDDIRECT
LD IMMEDIATE
LD INDIRECT
LDINDEXED
ADDC DIRECT
ADDC IMMEDIATE
ADDC INDIRECT
ADDC INDEXED
SUBC DIRECT
SUBC IMMEDIATE
SUBC INDIRECT
SUBCINDEXED
LDBZE DIRECT
LDBZE IMMMEDIATE
LDBZE INDIRECT
LDBZE INDEXED
LOB DIRECT
LOB IMMEDIATE
LOB INDIRECT
LOB INDEXED
ADDCB DIRECT
ADDCB IMMEDIATE
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
04
05
06
07
08
09
DA
ADDCB INDIRECT
ADDCB INDEXED
SUBCB DIRECT
SUBCB IMEDIATE
SUBCB INDIRECT
SUBCBINDEXED
LDBSE DIRECT
LDBSE IMMEDIATE
LDBSE INDIRECT
LDBSE INDEXED
STDIRECT
BMOV
STINDIRECT
STINDEXED
STB DIRECT
CMPL
STB INDIRECT
STB INDEXED
PUSH DIRECT
PUSH IMMEDIATE
PUSH INDIRECT
PUSH INDEXED
POP DIRECT
BMOVI
POP INDIRECT
POP INDEXED
JNST
JNH
JGT
JNC
JNVT
JNV
JGE
JNE
JST
JH
JLE
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB·
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
JC
JVT
JV
JLT
JE
DJNZ
DJNZW
TIJMP
BR (INDIRECT)
RESERVED
RESERVED
RESERVED
LJMP
RESERVED
RESERVED
RESERVED
RESERVED
OPTS
EPTS
RESERVED
LCALL
RET
RESERVED
PUSHF
POPF
PUSHA
POPA
IDLPD
TRAP
CLRC
SETC
01
EI
CLRVT
NOP
*DIV IDIVB/MUL/MULB
RST
NOTES:
'Two byte instruction
RESERVED-Execution of reserved instructions will cause Unimplemented Opcode interrupt.
14-211
II
8XC196MC
8.0
INSTRUCTION SET SUMMARY
Mnemonic
Operatlon(1}
Operands
ADD/AD DB
2
D=D+A
ADD/AD DB
3
D=B+A
ADDC/ADDCB
2
D=D+A+C
SUB/SUBB
2
D=D-A
SUB/SUBB
3
D=B-A
SUBC/SUBCB
2
D=D-A+C-1
CMP/CMPB/CMPL
2
D-A
MUL/MULU
2
0,0 + 2 = 0
MUL/MULU
3
0,0 + 2 =
MULB/MULUB
2
0,0 -+: 1 =
xA
0 xA
0 xA
BxA
Z
Flags(2}
Notes
N C V VT ST
'" "'''''''
'"J. "'''''''
"'''''''
'" "'''''''
'" "'''''''
J.
"'''''''
'" "'''''''
i
i
i
i
i
i
i
3
3
4
MULB/MULUB
3
0,0 + 1 =
DIVU
2
o=
DIVUB
2
0= (0,0 + 1)/A,D + 1 = remainder
DIV
2
o=
4
(0,0 + 2)/ A,D + 2 = remainder
(0,0 + 2)IA,D + 2 = remainder
DIVB
2
0= (0,0 + 1)/A,D + 1 = remainder
AND/ANDB
2
0= DandA
AND/ANDB
3
0= BandA
OR/ORB
2
0= DorB
XOR/XORB
2
o=
LD/LDB
2
D=A
ST/STB
2
A=D
XCH
2
D~A;D+1
XCHB
2
D~A
BMOV,
BMOVI
2
(PTR_HI) + = (PTR_LOW) +;
Until COUNT = 0
LDBSE
2
o=
LDBZE
2
D=A;D+1=0
PUSH
1
SP = SP - 2; (SP) = A
POP
1
A = (SP); SP = SP + 2
PUSHF
0
SP = SP - 2; (SP) = PSW;
PSW = 0; I = 0; PSE = 0
POPF
0
PSW = (SP); SP = SP + 2;1 -- '"
PUSHA
0
SP = SP - 2;(SP) = PSW;PSW = OOOOh;
SP = SP -2;(SP) = IMASKI/WSR;
IMASKI = OOh; I = 0; PSE = 0
0 (exclusive or) A
'" '"
'" '"
'" '"
'" '"
0
'"
'"
'"
'"0
i
i
i
t
3
4
0 0
0 0
0 0
~·A+1
A; 0 + 1 = Sign (A)
14-212
4,5
4,5
0
11
'" "''''''' '" '"
0 0 0 0 0 0
11
0
0 0 0
0
11
intet
8.0
8XC196MC
INSTRUCTION SET SUMMARY (Continued)
Mnemonic
POPA
Flags(2)
Operation(1)
Operands
0
IMASKI/WSR = (SP); SP = SP
PSW = (SP); SP = SP + 2
SJMP
1
PC = PC
LJMP
1
PC = PC
+ 2;
Z
N
C
V
VT
ST
v
v
v
v
v
v
+ 11-Bit-Offset
+ 16-Bit-Offset
BR[lndirect]
1
PC = (A)
TIJMP
3
PC = ([index] and MASK)2
TRAP
0
SP = SP -2; (SP) = PC;
PC = (2010h)
Notes
6
6
+
(Table)
10
SCALL
1
SP = SP - 2; (SP) = PC;
PC = PC + 11-Bit Offset
6
LCALL
1
SP = SP - 2; (SP) = PC.
PC = PC + 16-Bit-Offset
6
RET
0
PC = (SP); SP = SP
J (conditional)
1
PC = PC
JC
1
Jump ifC = 1
6
JNC
1
JumpifC = 0
6
+2
+ a-Bit-Offset (If Taken)
6
JE
1
Jump if Z = 1
6
JNE
1
Jump if Z = 0
6
JGE
1
Jump if N = 0
6
JLT
1
Jump if N = 1
6
JGT
1
Jump if N = 0 and Z = 0
6
JLE
1
Jump if N = 1 or Z = 1
6
JH
1
Jump if C = 1 and Z = 0
6
JNH
1
Jump if C = 0 or Z = 1
6
Jump if V = 1
6
JV
1
JNV
1
Jump if V = 0
JVT
1
Jump if VT = 1; Clear VT
0
6
JNVT
1
Jump if VT = 0; Clear VT
0
6
1
Jump if ST = 1
JNST
1
Jump ifST = 0
JBS
3
Jump if Specific Bit = 1
6, 7
JBC
3
Jump if Specific Bit = 0
6, 7
DJNZ/DJNZW
1
D = D - 1;
If D 0 then PC = PC
JST
"*
DEC/DECB
1
D = D-I
NEG/NEGB
1
D=O-D
6
6
6
6
+ a-Bit-Offset
v
v
14-213
v
v
v
v
v
v
i
i
III
intet
8.0
8XC196MC
INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operatlon(1)
Operands
INC/INCB
1
D=D+1
EXT
1
D = D; D + 2 = Sign (D)
EXTB
1
NOTINOTB
1
o=
o=
D; D + 1 Sign (D)
Flags(2)
Z N C V VT ST
"" "" ""0 ""0
"" "" 0 0
NORML
2
SETC
0
"" "" 0 0
""1 ""0 0 0
D=O
C msb .. .Isb 0
"" "" "" ""0
o --+ msb ... Isb --+ C
"" "" "" 0
msb --+ msb ... Isb --+ C
"" "" ""0
Left Shift until msb = 1; D = Shift Count
"" "" 1
C=1
CLRC
0
C=O
CLRVT
0
VT = 0
CLR/CLRB
1
SHL/SHLB/SHLL
2
SHRISHRB/SHRL
2
SHRAISHRAB/SHRAL
2
Notes
i
3
4
Logical Not (D)
i
8
""
8
""
8
0
9
8
0
0
0 0 0 0' 0
RST
0
PC = 2080H
DI
0
Disable All Interrupts (I = 0)
EI
0
Enable All Interrupts (I = 1)
DPTS
0
Disable PTS Interrupts (PSE = 0)
EPTS
0
Enable PTS Interrupts (PSE = 1)
NOP
0
PC=PC+1
SKIP
0
PC=PC+2
IPLPD
1
Idle Mode IF Key = 1;
Powerdown Mode IF Key = 2
Chip RESET Otherwise
NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is performed. Operands D, Band
A must conform to. the alignment rules for the required operand type. D and B are locations in the Lower Register File; A can
be located anywhere in memory.
2. The symbols indicate the effects on the flags:
", Cleared or set as appropriate
o Cleared
1 Set
t Set if appropriate; never cleared
!- Cleared if appropriate; never set
3. D.D + 2 are consecutive WORDs in memory; D is DOUBLE-WORD aligned.
4. D.D + 1 are consecutive BYTEs in memory; D is WORD aligned.
5. Changes a BYTE to WORD. \
6. Offset is a 2's complement number.
7. Specific Bit must be in or windowed into the Lower Register File.
8. The "L" (LONG) suffix indicates DOUBLE-WORD operations.
9. Initiates a RESET by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
10. The assembler does not accept this mnemonic (use the macro file for definition).
11. I = Interrupt Enable (PSW.9).
14-214
in1eL
9.0
8XC196MC
INSTRUCTION LENGTH/OPCODES
Mnemonic
Direct
Immed
ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
AD DB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB
4/44
4/48
3/64
3/68
31M
3/A8
3/88
4/54
4/58
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3/74
3/75
3/79
MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB
5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
4/60
5/(2)
4/80
5/(2)
4/50
4/(2)
3/7C
3/70
4/(2)
3/9C
4/(2)
3/90
AND (3-op)
AND (2-op)
OR (2-op)
XOR
AN DB (3-op)
AN DB (2-op)
ORB (2-op)·
XORB
4/40
3/60
3/80
3/84
4/50
PUSH
POP
2/C8
2/CC
3/78
3/B4
3/B8
3/98
Indirect
Indexed
Normal(1)
A-inc(1)
Short(1)
Long(1)
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
5/47
5/4B
4/67
4/6B
4/A7
4/AB
4/8B
5/57
5/5B
6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
3/7A
3/76
3/7A
4/77
4/7B
5/77
5/7B
3/B5
3/B9
3/99
3/B6
3/BA
3/9A
3/B6
3/BA
3/9A
4/B7
5/B7
4/BB
5/BB
4/9B
5/9B
6/(2)
5/(2)
4/4E
4/(2)
5/(2)
6/(2)
7/(2)
4/4E
4/(2)
3/6E
4/(2)
5/4F
5/(2)
6/4F
6/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
4/7F
5/7F
5/40
5/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
3/9E
4/(2)
3/9E
5/41
4/61
4/81
4/85
4/51
4/42
3/62
3/82
3/86
4/52
4/42
3/62
3/82
3/86
4/52
3/70
3/71
3/72
3/90
3/94
3/91
3/95
3/92
3/96
3/72
3/92
3/C9
2/CA
2/CE
-
14-215
5/(2)
6/(2)
4/9F
5/9F
,
3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
2/CA
2/CE
3/CB
3/CF
4/CB
4/CF
•
8XC196MC
Instruction Length (in bytes)/Opcode
Indexed
Indirect
Mnemonic
Direct
Immed
Normal
A-inc
Short
Long
LO
LOB
ST
STB
XCH
XCHB
LOBSE
LBSZE
3/AO
4/A1
3/A2
3/A2
4/A3.
5/A3
Mnemonic
3/BO
3/B1
3/B2
3/B2
4/B3
5/B3
3/CO
-
3/C2
3/C2
4/C3
5/C3
3/C4
-
3/C6
3/C6
4/C7
5/C7
3/04
-
-
-
4/0B
5/0B
-
4/1B
5/1B
3/BO
3/AO
3/BE
3/AE
3/BE
3/AE
4/BF
4/AF
5/BF
5/AF
3/14
3/BC
3/AC
Length/Opcode
PUSHF
POPF
PUSHA
POPA
1/F2
1/F3
.1/F4
1/F5
TRAP
LCALL
SCALL
RET
LJMP
SJMP
BR[)
TIJMP
1/F7
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
JE
JBC
JBS
3/EF
2/2S-2F(3)
1/FO
3/E7
2/20-27(3)
2/E3
4/E2
Mnemonic
Length/Opcode
OJNZ
OJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB
3/EO
CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
BMOV
BMOVI
1/00
1/0S
1/01
1/09
1/02
1/0A
1/B3
1/0S
1/04
1I0C
1/05
1/00
3/E1
3/0F
3/0C
3/00
3/0E
3/0S
3/1S
3/09
3/19
3/0A
3/1A
1/FS
1/F9
1/FA
1/FB
1/EC
1/EO
1/FC
1/FO
1/FF
2/00
1/F6
3/C1
3/CO
1/06
1/0E
1/07
1/0F
3/30-37
3/3S-3F
NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2'5 complement offset.
14-216
infel .
10.0
8XC196MC
INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
Instruction
Direct
Immediate
ADD (30p) I
SUB (30p)
ADD (2op)
SUB (2op)
AD DC
SUBC
CMP
ADDB (30p)
SUBB (30p)
ADDB (2op)
SUBB (2op)
ADDCB
SUBCB
CMPB
CMPL
MUL (30p)
MULU (30p)
MUL(2op)
MULU (2op)
DIV
DIVU
MULB (30p)
MULUB (30p)
MULB (2op)
MULUB (2op)
DIVB
DIVUB
AND (30p)
AND (2op)
OR
XOR
ANDB (30p)
AN DB (2op)
ORB
XORB
LD
ST
XCH
LOB
5
6
6
5
4
4
4
4
4
Indirect
Normal
A·inc
Indexed
Long
Short
7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8
8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9
17
15
17
15
27
25
12
10
12
10
18
16
6
5
5
5
5
4
4
4
5
18/21
16/19
18/21
16/19
28/31
26/29
14/17
12/15
14/17
12/15
20/23
18/21
7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8
5/8
5/8
19/22
17/20
19/22
17/20
29/32
27/30
15/18
12/16
15/18
12/16
21/24
19/22
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
6/8
6/9
4
5/8
6/8
19/22
17/20
19/22
17/20
29/32
27/30
15/18
12/16
15/18
12/1.6
21/24
19/22
7/10·
6/8
6/8
6/8
7/10
6/8
6/8
6/8
6/9
6/9
8/13
6/9
20/23
18/21
20/23
18/21
30/33
28/31
16/19
14/17
16/19
14/17
22/25
20/23
8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9
7/10
7/10
9/14
7/10
5
5
5
5
5
5
5
5
4
4
4
4
4
7
16
14
16
14
26
24
12
10
12
10
18
16
5
4
4
4
5
4
4
4
4
4
5
4
5
4
4
4
4
4
14-217
•
intel·
8XC196MC
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES) (Continued)
Instruction
Direct
STB
4
XCHB
5
Immediate
Indirect
Normal
A-Inc
5/8
BMOV
6
+ 8 per Word
6 + 11
14 per Word
BMOVI
7
+ 8 per Word
7 + 11/
14 per Word
+ 14 for
Each Interrupt
+ 14 for Each Interrupt
6/9
Indexed
Short Long
6/9
7/10
8/13
9/14
6/8
7/9
LDBSE, LDBZE
4
4
5/7
6/8
PUSH (int)
6
7
9/12
10/13
10/13 11/14
POP (int)
8
10/12
11/13
11/13
PUSHF(int)
6
POPF (int)
7
PUSHA (int)
12
POPA (int)
12
PUSH (ext)
8
.POP (ext)
11
PUSHF (ext)
8
POPF (ext)
10
PUSHA(ext)
POPA (ext)
18
LJMP
7
SJMP
7
18
BR [indirect]
TIJMP
9
7
15 (
+ 3 for External Reference)
TRAP (int)
16
LCALL (int)
11
SCALL (int)
11
RET (int)
11
TRAP (ext)
18
LCALL (ext)
13
SCALL(ext)
13
RET (ext)
14
JNST, JST
4/8 Jump Not Taken/Jump Taken
JNH,JH
4/8 Jump Not Taken/Jump Taken
JGT,JLE
4/8 Jump Not Taken)Jump Taken
JNC,JC
4/8 Jump Not Taken/ Jump Taken
JNVT,JVT
4/8 Jump Not Taken/ Jump Taken
JNV,JV
4/8 Jump Not Taken/ Jump Taken
JGE,JLT
4/8 Jump Not Taken/Jump Taken
JNE,JE
4/8 Jump Not Taken/Jump Taken
JBS,JBC
5/9 Jump Not Taken/ Jump Taken
DJNZ
DJNZW
5/9 Jump Not Taken/ Jump Taken
6/10 Jump Not Taken/Jump Taken
14-218
12/14
11/14
12/15 12/15
13/16
13/15
14/16 14/16
15/17
int'eL
8XC196MC
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES) (Continued)
Instruction
Direct
CLR, NOT, NEG
3
DEC,INC
3
EXT
4
CLRB, NOTB
3
DECB,INCB
3
NEGB
3
EXT
4
+ 1 per Shift (9 for 0 Shift)
+ 1 per Shift (8 for 0 Shift)
7 + 1 per Shift (8 for 0 Shift)
7 + 1 per Shift (8 for 0 Shift)
6 + 1 per Shift (7 for 0 Shift)
6 + 1 per Shift (7 for 0 Shift)
6 + 1 per Shift (7 for 0 Shift)
6 + 1 per Shift (7 for 0 Shift)
6 + 1 per Shift (7 for 0 Shift)
6 + 1 per Shift (7 for 0 Shift)
NORML
8
SHRL
7
SHLL
SHRAL
SHR
SHL
SHRA
SHRB
SHLB
SHRAB
CLRC
2
SETC
2
DI
2
EI
2
DPTS
2
EPTS
2
CLRVT
2
NOP
2
RST
SKIP
IDLPD
Indexed
Indirect
Normal A·inc Short Long
Immediate
•
20 (Includes Fetch of CCB/CCB1)
3
8/25 (Proper Key/Improper Key)
PTS
Single Transfer
18
Burst Transfer
13
PWM Modes
15
AID Scan Mode
( + 3 for Ext Reference, + 1 If XFER Count =
( + 7 for Each Transfer, 1 Minimum
+ 3 for Each Memory Controller Reference)
0
12/25
NOTES:
The timing figures are minimum execution times expressed as state times (one period of CLKOUT = two oscillator periods.
Section 11.3) and are based on the following assumptions:
1. The opcode, along with any required operands, have been pre-fetched and reside in the instruction queue.
2. The bus controller operates with the 16-bit bus selected and without wait states for external memory references and prefetches. For instructions with indirect or indexed addressing, execution times separated by a slash are for instructions requiring a fetch from internal! external memory.
3. Times for jumps, calls, and returns include the 4 state times required to flush the pre-fetch queue and to fetch the opcode
a the destination address. This is reflected in the jump taken!not-taken times shown in the table.
14-219
int:eL
8XC196MC
11.0 INTERRUPT TABLE
8XC196MC Summary of Interrupts and Priorities
Number
Symbol
Source
INT15
Non-Maskable Interrupt
PTS14PTSO
PTS
NMI
•
Vector
Location
Priority
203EH
15
•
•
INT14
EXTINT Pin
EXT/NT
203CH
14
INT13
WG_COUNTER
WG
203AH
13
INT12
Reserved
2038H
12
INT11
Reserved
2036H
11
-
INT10
Reserved
2034H
10
INT09
COMPARE3
CM3
2032H
9
INT08
CAPCOMP3
CP3
2030H
8
N/A
N/A
Unimplemented Opcode
2012H
TRAP Instruction
N/A
N/A
2010H
N/A
N/A
INTO?
COMPARE2
CM2
2003H
?
INT06
CAPCOMP2
CP2
200CH
6
INT05
COMPARE1
CM1
200AH
5
INT04
CAPCOMP1
CP1
2008H
4
INT03
COMPAREO
CMO
2006H
3
INT02
CAPCOMPO
CPO
2004H
2
INT01
AID Complete
AID DONE
2002H
1
INTOO
T1 IT2 Overflow
TOVF
2000H
0
NOTE:
"Refer to PTS Vector Table
Interrupt SFRs. The Interrupt SFRs are listed with
'
their addresses:
SFR
Address
INT_MASK
INT_PEND
INT_PEND1
INT_MASK1
08H
09H
12H
13H
\
14-220
infel~
8XC196MC
PTS Vector Table
Priority
Name
HIGHEST
PTS14
EXTINT
Source
205CH
•
•
PTS13
WG_COUNT
205AH
PTS12
RESERVED
2058H
•
PTS11
RESERVED
2056H
•
PTS10
RESERVED
2054H
•
•
PTS9
COMPARE3
2052H
PTS8
CAPCOMP3
2050H
•
•
•
•
•
•
•
PTS7
COMPARE2
204EH
PTS6
CAPCOMP2
204CH
PTS5
COMPARE2
204AH
PTS4
CAPCOMP1
2048H
PTS3
COMPAREO
2046H
PTS2
CAPCOMPO
2044H
PTS1
AID Done
2042H
LOWEST
PTSO
TOVF
2040H
PTS Vector
The end-of-PTS interrupt is treated as a normal interrupt. It vectors through the associated location in the normal
interrupt vector table (Table 11.1). For example, if the AID interrupt is selected by the PTS, an AID interrupt is
directed to its PTSCB by the PTS vector at 2042H; its end-of-PTS interrupt is at 2002H. Thus, the user would write
an end-of-PTS interrupt routine for TI and store a vector pointing to it at location 2002H.
An end-of-PTS interrupt has higher priority than any normal interrupt (with the exception of NMI). Within the
group of end-of-PTS interrupts, the priorities are the same as for normal interrupts.
14-221
III
inteL
8XC196MC
12.0 FORMULAS
State Time
=
13.0 RESET STATUS
2 Oscillator periods
2
Pin States during RESET, Idle or Powerdown
= -.FOSC
Pin Name
TIJMP Calculation-
RESET
P5.0 (ALE)
P5.1 (INST)
P5.2 (WR)
P5.3 (RD)
P5.4
P5.5 (BHE)
P5.6 (READY)
P5.7 (BUSWIDTH)
EA
NMI
P3, P4 (EA = 0)
P3, P4 (EA = 1)
CLKOUT
EXTINT
PO (ACH)
P1 (ACH)
P2.0
P2.[7,5:1]
P2.6
P6. [5:0]
P6. [7:6]
Vpp
XTAL1
XTAL2
Destination = ([INDEX] and INDELMASK) • 2 +
[TBASE]
EPA Prescaler
P2
P1
PO
Divide By
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7 1
72
74
78
7 16
732
764
Reserved
AlDSAM = (TSAM' Foscl - 2
8
(8' SAM)
TSAM =
F
+2
OSC
CONY = (TCONy • Foscl
2'B
+3
HZ
LZ
wk1
wkO
mdl
ODIO
.
(2 ' B ' CONY) - 3
'CONV =
F
osc
Programming Pulse Width-
Reset
wk1
wk1 •
wk1
wk1 '
wk1 '
mdl'
wk1
wk1
wk1
HZ
wkO
wk1
wk1
elk
HZ
HZ
HZ
Idle
Powerdown
wk1
(A)
(B)
wk1
(A)
(B)
(C)
(C)
(C)
(C)
(C)
(C)
(C)
(C)
(D)
(D)
HZ
wkO
HZ
(D)
(D)
HZ
wkO
HZ
0010
0010
clk
HZ
HZ
HZ
(E)
(E)
(E)
O,LZ
HZ
HZ
HZ
(E)
(E)
(E)
wk1 •
wk1 *
mdl'
wk1
(F)
(F)
wkO
(F)
(F)
,HZ
1, LZ
1, LZ
HZ
HZ
HZ
ose, LZ ose,LZ (G)
-High Impedance
-Low Impedance
-Weakly Pulled High
-Weakly Pulled Low
-Medium Strength High
-Open Drain 10
• These pins are also used to control test mode entry.
PPR
=
((PPW) , (Foscl) - 144 + 32768
144
(A)
SIO Baud RateBAUDCONST = Fosc/(4 • Baud Rate. EPA prescale)
SSIO Baud RateBAUDCONST
(C)
Fosc/(8 • Baud Rate. EPA prescale)
=
(B)
Wave Generator Up/Down Mode-
(D)
(E)
WG_RELOAD = (Fosc • PWM Period)/4
(F)
Wave Generator Up ModeWG_RELOAD
=
(Fosc • PWM Period)/2
(G)
14-222
if P5_MODE.O = 0 then port value
if P5_MODE.O = 1 and OCR.3 = 1 (ALE mode)
then LZ 0
if P5_MODE.O = 1 and OCR.3 = 0 (ADV mode)
then LZ 1
if P5_MODEI = 0 then port value
if P5_MODEI = 1 then LZ 0
if P5_MODEy = 0 then port value
if P5_MODEy = 1 then LZ 1
if P5_MODE.y = 0 then port value
if P5_MODE.y = 1 then HZ
if P2_MODE.y = 0 then port value
if P2_MODE.y = 1 then as peripheral specifies
if output port then port value
if special function then as peripheral specifies
if XTAL1 = 1 then LZ 0
if XTAL1 = 0 then LZ 1
8XC196MC
SFR Reset Values
CAPCOMPO_TIME
INDETERMINATE
CAPCOMP1_TIME
INDETERMINATE
CAPCOMP2_TIME
INDETERMINATE
CAPCOMP3_TIME
INDETERMINATE
COMPO_TIME
INDETERMINATE
COMP1_TIME
INDETERMINATE
COMP2_TIME
INDETERMINATE
COMP3_TIME
INDETERMINATE
T1RELOAD
INDETERMINATE
PO_PIN
FFH (when pin is not driven)
Pi_PIN
FFH (when pin is not driven)
AD_RESULT (LO)
COH
AD_RESULT (HI)
FFH
AD_COMMAND
SOH
AD_TEST
COH
AD_TIME
FFH
PI_MASK
AAH
PLPEND
AAH
WG_COUNT
INDETERMINATE
WG_CON
COH
WG_PROTECT
FOH
P2_DIR, P2_REG
FFH
P2_PIN
FFH (when pin is not driven)
P5_MODE
SOH IF EA
P5_DIR, P5_PIN
FFH
= HIGH, A9H IF EA = LOW
P5_REG
FFH (when pin is not driven)
USFR
02H
P3_REG, P4_REG
FFH
P3_PIN, P4-,-PIN
FFH (when pin is not driven)
NOTE:
This table lists all the registers that their reset value is not O.
Given values include the reserved bits (when applicable).
14-223
III
intel·
,
October 1992
8XC196NTINQ
Quick Reference
Order Number: 272270-001
14-224
8XC196NT/NQ Quick Reference
CONTENTS
PAGE
CONTENTS
PAGE
1.0 MEMORY MAP ................... 14-226
8.0 INSTRUCTION SET SUMMARY .. 14-240
2.0 SFR MAP ......................... 14-227
9.0 INSTRUCTION
LENGTH/OPCODES ............... 14-243
3.0 SFR BIT SUMMARy .............. 14-229
10.0 INSTRUCTION EXECUTION TIMES
4.0 PIN DEFINITION TABLE .......... 14-233
(IN STATE TIMES) ................. 14-245
5.0 PACKAGE PIN ASSIGNMENTS .. 14-234
11.0 INTERRUPT TABLE ............. 14-249
6.0 PIN DESCRIPTION ............... 14-235
12.0 FORMULAS ..................... 14-250
7.0 OPCODE TABLE ................. 14-238
13.0 RESET STATUS ................. 14-251
..
14-225
intel~
8XC196NT/NQ QUICK REFERENCE
1.0 MEMORY MAP
FFFFFFH
FFAOOOH
FF9FFFH
FF2080H
External Memory
Internal ROM/EPROM
or External Memory
FF207FH
FF205EH
Reserved
FF205DH
FF2040H
PTSVectors
Interrupt
FF203FH
FF2030H
Vectors (Upper)
FF202FH
FF2020H
ROM/EPROM
Security Key
FF20tFH
FF201DH
Reserved
FF201CH
CCB2
FF201BH
Reserved
FF201AH
CCB1
FF2019H
Reserved
FF2018H
CCBO
FF2017H
FF2014H
Reserved
FF2013H
FF2000H
Interrupt
Vectors (Lower)
FF1FFFH
FF0600H
External Memory
FF05FFH
FF0400H
Internal RAM
FF03FFH
FF0100H
External Memory
Reserved
FFOOFFH
FFOOOOH
for ICE
FEFFFFH
100000H
Expansion Memory
for future devices
..
OFFFFFH
984 Kbytes
External Memory
OOAOOOH
009FFFH
002080H
Internal ROM/EPROM
or External Memory
00207FH
00205EH
Reserved
00205DH
002040H
PTSVectors
00203FH
002030H
Interrupt Vectors
00202FH
002020H
ROM/EPROM
Security Key
00201FH
00201DH
Reserved
00201CH
CCB2
(Upper)
00201BH
Reserved
00201AH
CCB1
002019H
Reserved
002018H
CCBO
002017H
002014H
Reserved
002013H
002000H
>
NOTE: Addresses FF2000H to FF9FFFH
are remapped to 2000H to 09FFFH
when Eli is high and CCB2.2 is set.
OthelVlise they are external memory.
Interrupt
Vectors (Lower)
001FFFH
001 FOOH
Internal SFRs
001EFFH
000600H
External Memory
0005FFH
000400H
Internal RAM
0003FFH
OOOOOOH
Register File
14-226
int'et
8XC196NT/NQ QUICK REFERENCE
2.0 SFR MAP
CPU Special Function Registers
17H
16H
15H
14H
13H
12H
11H
10H
OFH
OEH
ODH
OCH
(Reserved)
(Reserved)
(Reserved)
WSR
INT MASK1
INT_PEND1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
OSH
OAH
09H
OSH
07H
06H
05H
04H
03H
02H
01H
OOH
(Reserved)
WATCHDOG
INT_PEND
INT_MASK
PTSSRV(Hi)
PTSSRV(Lo)
PTSSEL(Hi)
PTSSEL(Lo)
Read asFFH.
Read asFFH
ZERO_REG (Hi)
ZERO_REG (Lo)
•
14-227
S'
Memory Mapped I/O SFRs
........
...
CD
:::J
HIGH BYTE
LOW BYTE
lFFEH
P4JIN
P3_PIN
lFFCH
P4_REG
P3_REG
lFFAH
SLP_CMD
SLP_CMD
HIGH BYTE
LOW BYTE
lFF8H
(Reserved)
SLP_STAT
lFBEH
(Reserved)
(Reserved)
!!.
Serial I/O and Synchronous
SIOSFRs
EPASFRs
HIGH BYTE
LOW BYTE
lFFSH
P5JIN
USFR
lFBCH
SP.-BAUD (Hi)
SP.-BAUD (Lo)
lF8EH
COMP1_TIME(Hi)
COMP1_TIME (Lo)
lFF4H
P5~EG
(Reserved)
lFBAH
SP_CON
SBUF_TX
lF8CH
(Reserved)
COMP1_CON
lFF2H
P5_DIR
(Reserved)
lFB8H
SP_STATUS
SBUF_RX
lF8AH
COMPO_TIME (Hi)
COMPO_TIME (Lo)
lFFOH
P5_MODE
(Reserved)
lFBSH
(Reserved)
(Reserved)
lF88H
(Reserved)
COMPO_CON
lFEEH
(Reserved)
(Reserved)
'lFB4H
(Reserved)
SSIO_BAUD
lF8SH
EPA9_TIME (Hi)
EPA9_TIME (Lo)
lFECH
(Reserved)
(Reserved)
lFB2H
SSIOO_CON
SSIOO_BUF
lF84H
(Reserved)
EPA9_CON
lFEAH
(Reserved)
(Reserved)
SSI01_BUF
lF82H
EPA8_TIME (Hi)
EPA8_TIME (Lo)
lFE8H
(Reserved)
(Reserved)
lF80H
(Reserved)
EPA8_CON
lFE6H
EP_PIN
(Reserved)
lF7EH
EPA7_TIME (Hi)
EPA7_TIME (Lo)
lFE4H
EP~EG
lFE2H
EP_DIR
(Reserved)
EP_MODE
IRA~EG
~
Port 0, Port 1 and
Port 6 SFRs
HIGH BYTE
lFDEH
(Reserved)
A/OandEPA
Interrupt SFRs
(Reserved)
lFEOH
!XI
SSIOl_CON
lFBOH
LOW BYTE
(Reserved)
LOW BYTE
'lF7AH
EPA6_TIME (Hi)
EPA6_TIME (Lo)
AD_TIME
AD_TEST
lF78H
(Reserved)
EPA6_CON
lFACH AD
COMMAND (Hi) AD_COMMAND (Lo)
lF7SH
EPA5_TIME (Hi)
EPA5_TIME (Lo)
(Reserved)
EPA5_CON
lFAAH
AD~ESULT
AD_RESULT (La)
lF74H
lFA8H
(Reserved)
EPAIPV
lF72H
EPA4_TIME (Hij
EPA4_TIME (Lo)
lFA6H
(Reserved)
EPA.J'ENDl
lF70H
(Reserved)
EPA4_CON
lFA4H
(Reserved)
EPA-MASKl
1FSEH
EPA3_TIME (Hij
EPA3_TIME (Lo)
(Hi)
(Reserved)
(Reserved)
(Reserved)
PO_PIN
lFA2H
EPA.J'END (Hi)
EPA-PEND (La)
lFAOH
EPA-MASK (Hi)
EPA-MASK (La)
(Reserved)
lFDSH
PSJIN
P1JIN
lFD4H
P6_REG
Pl_REG
lFD2H
PS_DIR
Pl~IR
lFDOH
PS_MODE
Pl~ODE
Port2SFRs
HIGH BYTE
LOW BYTE
1FCEH
P2JIN
(Reserved)
1FCCH
PLREG
(Reserved)
1FCAH
P~IR
(Reserved)
1FC8H
P~ODE
(Reserved)
EPA7_CON
HIGH BYTE
lFDAH
(Reserved)
(Reserved)
lFAEH
lFDCH
lFD8H
lF7CH
TImer 1 and TImer 2 SFRs
1FSCH
EPA3_CON (Hi)
EPA3_CON (Lo)
lF6AH
EPALTIME (Hi)
EPALTIME (Lo)
1FS8H
(Reserved)
EPALCON
1FSSH
EPA1_TIME (Hi)
EPA1_TIME (Lo)
HIGH BYTE
LOW BYTE
lF64H
EPA1_CON (Hi)
EPA1_CON (Lo)
lF9EH
TIMER2(Hi)
TIMER2(La)
1FS2H
EPAO_TIME (Hi)
. EPAO_TIME (Lo)
lF9CH
(Reserved)
T2CONTROL
lF60H
(Reserved)
lF9AH
TIMERl (Hi)
TIMERl (La)
lF9BH
(Reserved)
T1CONTROL
EPAO_CON
_.
€:
8
en
'0
CD
n
e:
."
C
:::J
n
O·
:::u
:::J
CD
CO
fii"
...UICD
CD
><
0
...
CD
en
z
-I
.....
Z
0
0
c:
(;
"lI,m
"'1'1
m
m
II
z
0
m
int:eL
8XC196NT/NQ QUICK REFERENCE
3.0 SFR BIT SUMMARY
EPAx-CONTROL
8
7
6
4
5
3
1
2
0
I RM I TB I CE I M1 I MO I RE I AD I ROT I ON/RT I
RM: "1" Enables Remapping (EPA1 & EPA3 Only)
TB: "0" Selects Timerl, "1" Selects Timer2
CE: "0" Disables Comparator, "1" Enables Comparator
M1, MO: Mode Bits
M1,MO
Capture:
Compare:
00
01
10
11
NoOp
Capture Negative
Capture Positive
Capture All Edges
Interrupt Only
Output "0"
Output "1"
Toggle Output
EPAIPV
6
5
I0 I0 I0 I
3
2
PV4
I PV3 I
PV2
3
x
x
x
4
I TB8 I REN
SP_BAUD
o
2
PEN
M2
Ml
1FBCH: Word
or
1
I
5
Mode 0:
,-----,
1FA8H: Byte
4
1FBBH: Byte
6
TB8: 9th Bit for Transmission
REN: Enables the Receiver
PEN: Enables Parity (Even)
M2, Ml:
00: Mode O/Sync
01: Mode 1/ Async (std)
10: Mode 2/Async (9th Bit Enable)
11: Mode 3/ Async (9th Bit Data)
RE: Reenable Entry = "1" (Lock Entry)
AD: Start A/D
ROT: Reset Opposite Time Base
ON/RT: Overrun and Reset Timer Enable
7
SP_CON
7
0
I
PVl
PVO
I
PV4-PVO: Returns the encoded highest priority interrupt
Value from lH-14H.
OH =
14H =
13H =
12H =
11 H =
10H =
OFH =
OEH =
ODH =
OCH =
OBH =
No Interrupt Pending
EPAINT4
EPAINT5
EPAINT6
EPAINT7
EPAINT8
EPAINT9
OVRINTO
OVRINTI
OVRINT2
OVRINT3
OAH
09H
OSH
07H
06H
05H
04H
03H
02H
01 H
= OVRINT4
=
=
=
=
=
=
=
=
=
OVRINT5
OVRINT6
OVRINT7
OVRINT8
OVRINT9
Compare Channel 0
Compare Channell
TIMERI Overflow
TIMER2 Overflow
PORT 1/2/5/6 Control
Px-MODE = "1" for Peripheral Control
Px-MODE = "0" for Standard Port
Px-DIR = "1" for INPUT or OPEN DRAIN
OUTPUT
Px-DIR = "0" for OUTPUT (PUSH/PULL)
Px-PIN is for PORT READs
Px-REG is for PORT WRITEs
1F98H: Byte = T1
1F9CH: Byte = T2
TxCONTROL
7
I
CE
6
I
UD
4
5
I
M2
I
Ml
I
1
2
3
I
MO
P2
I
CE: "0" Disables Timer, "1" Enables Timer
UD: "0" Counts Down, "1" Counts Up
000
xOl
010
011
100
110
111
M2, M1, MO-Mode Bits
Clock = Internal/Direction = UD
Clock = External/Direction = UD
Clock = Internal/Direction = TxDIR
Clock = External/Direction = TxDIR
Clock = Tl Overflow/Direction = UD
Clock = Tl Overflow/Direction = Tl
PI
0
I
PO
I
P2, P1, PO-Prescale Bits
I
Quadrature Count (TxCLK/TxDIR)
14-229
000
"'" 1 (250 ns@ 16 MHz) Xtal.4
001
"'" 2 (500 ns @16 MHz) Xtal.8
010
"'" 4 (1 J.Ls @16 MHz) Xtal.16
011
"'" 8 (2 J.LS @16 MHz) Xtal.32
100
"'" 16 (4 J.Ls
@
16 MHz) Xtal.64
101
"'" 32 (8 J.Ls
@
16 MHz) Xtal.128
110
"'" 64 (16 J.Ls @16 MHz) Xtal.256
111
Reserved
III
inteL
8XC196NT /NQ QUICK REFERENCE
INT_MASK/INT_MASK1
INT_PEND/INT_PEND1
15
13
12
08H/13H: Byte
09H/12H: Byte
11
10
9
8
AD_TEST
1FAEH: Byte
7654321
0 0
0 0
OF1
OFO
VREF
I I I I I
I
PTS_SRV
PTS_SELECT
7
o
7
6
AD_TIME
5
4
sarPle Time
1 FB9H: Byte
SP_STATUS
6543210
I RBB/RPE I RI I TI I FE I TXE I OE I X I X I
RP8: Set if 9th Bit set (No Parity)
RPE: Set if Parity Enabled and Parity Error
RI: Set after Last Data Bit Received
TI: Set at Beginning of STOP Bit
FE: Set if No STOP Bit Found
TXE: Set when Byte is in SBUF_ TX
OE: Set if Overrun Error Occurred
AGND: Convert on AnGND
VREF: Convert on VREF
OF1, OFO: Offset Adjust
00: No Adjustment
01: ADD 2.5 mV
10: SUB 2.5 mV
11: SUB 5.0 mV
J
6
1FAFH: Byte
3
2
1
AD_COMMAND
1FACH: Byte/Word
76543210
0
I I I TIM I
c~nversifn Timr (CO~V)
0
0
GO
I
C7annel; #
Channel # = 0 to 7
GO: "1" to Start Now/"O" for EPA Start
M: "0" = 10-Bitl"1" = 8-Bit Conversion
"0" = Detect High/"1" = Detect Low
T: "0" = Normal Conversion/"1" = Threshold Detect
SAM = 1 to 7
CONY = 2 to 31
Total Conversion Time:
T = (4. SAM) + (B.(CONV + 1) + 2.5)
Where B = 8 for 8-Bit, 10 for 10-Bit
EPA-MASK1/EPA-PEND1
EPL.MASK/EPA-PEND
1FA4H/1 FA6H: Byte
1FAOH/1 FA2H: Word
14-230
intel$
8XC196NT/NQ QUICK REFERENCE
CCB (FF2018H: Byte)
CCB1 (FF201AH: Byte)
' r'--------"1-Fetch CCB2
r---
0
PO
f----
1~
2~
3
ALE
~
~
~
f----
41
5
~
IRCO
IRCI
~
~
7~
~
~
LDCCB2
f--1
IRC2
See Table
"1"
"0"
"1"
~
~
~
WR/BHE
WRL/WRH
ALE - "0"
}
See Tabla
}
See Table
f----
6~
o
"1" Enables Powerdown
0
1
~
See Table
1
MODE16
~
See Table
2
REMAP
~
"0"
~
3
1
}
Reserved must
be "01"
}
See Table
0-00 Not Fetch CCB2
f---
2~
~
ADV
3
WOE
f---
4
~
5
0
f--6 I MSELO
7~
CCB2 (FF201CH: Byte)
~
~
~
..
~
Always Enabled
4
1
5
1
6
1
7
1
~
~
~
~
"0" - 24·bit mode
"1" - 16·bit mode
"0" - EPROM @
FF2000H only
"1" - EPROM also
mapped to
02000H,
LOC1
LOCO
Function
IRC2
IRC1
IRCO
Max Wait States
0
0
1
1
0
1
0
1
Read and Write Protected
Write Protected Only
Read Protected Only
No Protection
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
Zero Wait States
1 Wait State
2 Wait States
3 Wait States
INFINITE
MSEL1
MSELO
Bus Timing Mode
BW1
BWO
Bus Width
0
0
1
1
0
1
0
1
Mode 0 (1·Wait KR)
Mode 1 (Long R/W)
Mode 2 (Early Address)
Mode 3 (KR Compatible)
0
0
1
1
0
1
0
1
ILLEGAL
16·Bit Only
8·Bit Only
BW Pin Controlled
SLP_CON
1 FFBH: Byte
765432
1
0
I 0 I 0 I 0 I 0 I SLP I SLPL IIBEmask I OBFmask I
SLP
SLPL
1FF8H: Byte
7
=
IBEmask =
=
OBFmask =
=
5
STAT
43
2
1
I CBE I IBE
0
I OBF
STAT These bits are written by the 8XC196NT/NQ
user and defined by the 8XC196NT INQ user for
communication flags.
CBE (Command Buffer Empty)
= 1 After 8XC196NT/NQ Reads SLPCMD
= 0 After Master Writes to SLPCMD
or SLP = 0 in SLP_CON
IBE
(Input Buffer Empty)
= 1 After 8XC196NT/NQ Reads SLPDIN
= 0 After Master Writes to SLPDIN,
or SLP = 0 in SLP_CON
OBF (Output Buffer Full)
1 After 8XC196NT/NQ Writes to SLPDOUT
= 0 After Master Reads SLPDOUT
= 1 Enables Slave Port Operation
= 0 Disables Slave Port Operation and
=
6
Clears Bits, CBE, IBE, and OBF
in SLP_STAT
1 ALE Latches SLPJDDR from
AD1 (P3.1)
0 ALE is SLPJDDR
1 IBE Can Affect SLPINT
0 IBE Cannot Affect SLPINT
1 OBF Can Affect SLPINT
0 OBF Cannot Affect SLPINT
14-231
8XC196NT/NQ QUICK REFERENCE
USFR
SSIO,,-CON Registers
1FB1 H: Byte = SSIOO
1FB3H: Byte = SSI01
76543210
1 FF6H (Read Only): Byte
76543210
IRSV I RSV I RSV I DEI IDEO I RSV I RSV I RSV I
I MIS I T/R I TRT I THS I STE I ATR I OUF I TBS I
MIS
NOTE:
Do not write to location 1FF6H. Bits DED and DEI are
written as specified in users manual.
T IR
TRT
THS
STE
ATR
OUF
TBS
Device
87C196NT INQ
OED-Disable External· Data
DEI-Disable External Instructions
AD_RESULT
15
14
AID Channel
BUSY
RSV
2 LSB
8 MSB
Bit 4,5
11
10
12
8MSB
Channel Number: 0-7
0= AID Idle
1 = AID in Use
Reserved
2 Least Significant Bits
8 Most Significant Bits
0
13
WSR
7
HLDEN
1FAAH: Word
7
5
4
3
6
2 LSB I RSV I RSV IBUSyl
B
9
6
5
MasterlSlave
Transmit Receive
Transmitter/Receiver Toggle
Transceiver Handshake Select
Single Transfer Enable
Auto Transfer Re-Enable
Overflow/Underflow Flag
Transceiver/Buffer Status
2
0
AID Channel
14H: Byte
4
3
2
0
= 0 Disables HOLD/HLDA
= 1 Enables HOLD/HLDA
IRAM_CON (lFEOH: BYTE)
7161514131211101
~
IRA:SV:
=R~::ERNR:::AMR:VA·PPE:S:~TERRNS::
1 = INTERNAL RAM MAPPED EXTERNAL
EA_STAT
ICOMPLEMENT OF EA PIN
ELSTAT NOT EFFECTED BY WRITE
• RSV--RESERVED BIT MUST BE = 0
14-232
272270-2
intel.,
8XC196NT/NQ QUICK REFERENCE
4.0 PIN DEFINITION TABLE
68
PLCC
44
45
46
47
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
04
40
04
48
08
39
10
43
42
33
14
Function
ACH4
ACH5
ACH6
·ACH7
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
ADV
AINC
ALE
ANGND
BHE
BREQ
BUSWIDTH
CLKOUT
CPVER
EA
EPO
68
PLCC
13
12
11
57
56
55
54
53
52
51
50
58
59
38
42
41
03
40
32
44
45
46
47
57
56
55
54
53
52
51
50
36
37
38
68
Function
PLCC
EP1
EP2
EP3
EPAO
EPA1
EPA2
EPA3
EPA4
EPA5
EPA6
EPA7
EPA8
EPA9
EXTINT
HLDA
HOLD
INST
INTOUT
NMI
PO.4
PO.5
PO.6
PO.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
39
40
41
42
43
30
29
28
27
26·
25
24
23
22
21
20
19
18
17
16
15
04
03
09
01
08
02
10
58
59
60
61
62
63
14-233
Function
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6,4
P6.5
68
PLCC
64
65
43
37
44
45
46
47
38
36
07
02
31
37
62
64
63
65
01
60
61
57
55
36
35
06
49
05
34
09
08
09
67
66
Function
P6.6
P6.7
PACT
PALE
PMODE.O
PMODE.1
PMODE.2
PMODE.3
PROG
PVER
RD
READY
RESET
RXD
SCO
SC1
SDO
SD1
SLPINT
T1CLK
T1DIR
T2CLK
T2DIR
TXD
Vee
Vpp
VREF
Vss
Vss
WR
WRH
WRL
XTAL1
XTAL2
II
8XC196NTINQ QUICK. REFERENCE
5.0 PACKAGE PIN ASSIGNMENTS
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CD
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en ...
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ui ui ui ui
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.
-
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BUSWIDTH/P5.7
P6.2/T1CLK
ADI9/EP.3
P6.1/EPA9
ADI8/EP.2
P6.0/EPAB
AD17/EP.1
P1.0/EPAO
AD16/EP.0
P1.1/EPA1
AD15/P4.7
Pl.2/EPA2
AD14/P4.6
ADq/P4.5
AD12/P4.4
AD11/P4.3
P1.3/EPA3
68 PIN PLCC
Pl.5/EPA5
N87C196NT
AD10/P4.2
Pl.6/EPA6
P1.7/EPA7
AD9/P4.1
AD8/P4.0
P1.4/EPA4
VREF
TOP VIEW
ANGND
AD7/P3.7
po. 7/PIAODE.3/ACH7
AD6/P3.6
PO.6/PIAODE.2/ ACH6
AD5/P3.5
AD4/P3.4
Looking Down on
Component Side
Of PC Board
PO.5/PIAODE.1/ACH5
PO.4/PIAODE.0/ ACH4
272270-1
Figure 1. S8-Pin PLCC Package Diagram
14-234
int"eL
8XC196NT/NQ QUICK REFERENCE
6.0 PIN DESCRIPTION
Symbol
Name and Function
Vee
Main supply voltage ( + 5V).
VSS1, VSS2, VSS3
Digital circuit ground (OV). There are three VSS pins, all of which MUST be
connected.
VREF
Reference and supply voltage for the AID converter and PortO
connected for AID and Port 0 to function.
Vpp
Programming voltage for the EPROM parts. It should be + 12.5V for programming.
It is also the timing pin for the return from power-down circuit. Connect this pin with
a 1 /LF capacitor to VSS and a 1 MO resistor to Vee. If this function is not used,
connect Vpp to Vee.
ANGND
Reference ground for the AID qonverter. Must be held at nominally the same
potential as Vss.
ACH4-ACH7/PORTO
Analog inputs to the on-chip AID converter. Also a digital input pin. *
ALEI ADV IP5.0
Address Latch Enable or Address Valid output. Goes low to latch and demultiplex
the addressldata bus. When the pin is ADV, it goes inactive (high) at the end of the
bus cycle, providing a chip select for external memory. ADV is active only during
external memory accesses. Also a standard 1/0 pin.'
BHE/WRH/P5.5
Byte High Enable or Write High output. BHE = 0 when accessing odd (high) bytes
or complete words in external memory. WRH = 0 when writing to odd bytes or
complete words in external memory. BHE/WRH is only valid during 16-bit external
memory cycles. Also a standard 1/0 pin.'
BREQ/P2.3
BU13 Request output. Active low when the bus controller is in hold and has a
pending external memory cycle. Also a standard 1/0 pin.'
BUSWIDTH/P5.7
Input for bus width selection. If BUSWIDTH is low, an 8-bit cycle occurs. If
BUSWIDTH is high, a 16-bit cycle occurs. Also a standard 1/0 pin.'
CLOCKOUT/P2.7
Output of the internal clock generator. A 50% duty cycle signal at 112 XTAL 1
frequency. Also a standard 1/0 pin.'
EA
Input for memory select (External Access). EA = 1 directs memory accesses from
locations OF2000H through OF9FFFH to on-chip EPROM/ROM. EA = 0 directs all
memory accesses to off-chip memory. EA = + 12.5V causes execution to begin in
the Programming Mode. EA is latched at reset.
EPAO-7/P1.0-1.7
EPA8-9/P6.0-6.1
1/0 pins for the Event Processor A.rray. EPAO and EPA2 also function as T2CLK
and T2DIR. Also a standard 1/0 pin.'
EPORT
4-bit bidirectional standard 1/0 port. These pins are shared with the extended
address bus, A16-A19. Pin function is selected on a per pin basis.
EXTINT IP2.2
External Interrupt input pin. A positive transition sets the EXTINT interrupt pending
flag. The minimum high and low times are 2 oscillator cycles. Also a standard 1/0
pin.'
INST/P5.1
Instruction fetch signal. Output high during the entire bus cycle of an external
instruction fetch. INST is active only during external memory fetches; during internal
memory fetches, INST is low. Also a standard 1/0 pin.'
INTOUT IP2.4
Interrupt output indicating that a pending interrupt requires use of the external bus.
Also a standard 1/0 pin.'
HLDA/P2.6
Bus Hold Acknowledge output indicating release of the bus in response to a HOLD
request. Also a standard 1/0 pin. * This is also a TEST MODE enable pin. Do not
use it as an input without careful hardware evaluation.
'These pins may be used for the system or peripheral functions or as a standard I/O pin.
14-235
(+ 5V). Must be
•
intele
8XC196NT/NQ QUICK REFERENCE
6.0 PIN DESCRIPTION
Symbol
(Continued)
Name and Function
HOLD/P2.5
Bus Hold request input. HOLD is sent by another processor to request control of
8XC196NT /NO system bus. Also a standard 1/0 pin.'
NMI
Non-Maskable interrupt input pin. A positive transition causes a non-maskable
interrupt vector through memory location FF203EH. If not used, this pin should be
tied to Vss. May be used by Intel Evaluation boards.
PORTO
8-bit high impedance input-only port. Also used as AID converter inputs. Port 0 pins
should not be left floating. In EPROM devices these pins are also used to select the
Programming Mode.
PORT1
8-bit bidirectional standard liD port. All of its pins are shared with the EPA.
PORT2
8-bit bidirectional standard liD port. All of its pins are shared with other functions
(TxD, RxD, EXTINT, BREO, INTOUT, HOLD, HLDA, CLKOUT).
PORT3
PORT4
8-bit bidirectional standard liD with open drain outputs. These pins are shared with
the multiplexed addressldata bus which uses complementary drivers.
PORT5
8-bit bidirectional standard liD port. All of its pins are shared with other functions
(ALEI ADV, INST, WR/WRL, RD, SLPINT, BHE/WRH, READY, BUSWIDTH).
PORT6
8-bit bidirectional standard liD port. All of its pins are shared with other functions
(EPA8, EPA9, T1 CLK, T1 DIR, SCO, SDO, SC1, SD1).
RD/P5.3
Read signal output to external memory. RD is low only during external memory
reads. Also a standard liD pin.'
READY/P5.6
Ready input to lengthen external memory cycles. If READY = 1, CPU operation
continues in a normal manner. If READY = 0 wait states are added. Also a
standard liD pin.'
RESET
Reset input to the chip. Held low for at least 16 state times to reset the chip. The
subsequent low to high transition starts the reset sequence. Input high for normal
operation. RESET has an internal pullup.
RXD/P2.1
Receive data input pin for the Serial 110 (SID) port. Also a standard I/O pin.'
SLPINT/P5.4
Slave Port Interrupt output pin. Also a standard liD pin.'
SSIO/P6.4-P6.7
(SCO, SDO, SC1, SD1)
Synchronous Serial 110 pins. SCO/SC1 are clock pins and SDO/SD1 are data pins.
Also a standard 1/0 pin.'
T1CLK/P6.2
TIMER1 Clock input. TlMER1 increments or decrements on both rising and falling
edges. Also a standard liD pin.'
T1DIR/P6.3
TIMER1 Direction input. TlMER1 increments when this pin is high and decrements
when this pin is low. Also a standard 1/0 pin.'
T2CLK/P1.0
TIMER2 Clock Input. TIMER2 increments or decrements on both rising and falling
edges. Also a standard liD pin.'
T2DIR/P1.2
TIMER2 Direction input. TIMER2 increments when this pin is high and decrements
when this pin is low. Also a standard 1/0 pin. •
TXD/P2.0
WR/WRL/P5.2
Transmit data output pin for the Serial 110 (SIO) port. Also a standard liD pin.'
XTAL1
Input of the oscillator invertor and the internal clock generator. If using an external
clock source connect it to this pin.
XTAL2
Output of the oscillator invertor. Leave floating unless connected to a crystal I
resonator circuit.
Write and Write Low output to external memory. WR goes low for every external
write. WRL goes low only for writes to even addresses. WR/WRL is active only
during external memory writes. Also a standard I/O pin. •
'These pins may be used for the system or peripheral functions or as a standard 1/0 Pin.
14-236
intel.,
8XC196NT/NQ QUICK REFERENCE
6.0 PIN DESCRIPTION
(Continued)
Programming Mode Pin Definitions
Name
Name and Function
PMODE
PO.4-7
Programming Mode Select. Determines the EPROM programming algorithm that is performed.
PMODE is sampled after a chip reset and should be static while the part is operating.
PALE
Programming ALE Input. Accepted by an 8XC196NT /NO that is in Slave Programming Mode.
Used to indicate that Port 3 and 4 contain a command/address.
PROG
Programming. Falling edge latches data on PBUS and begins programming. Rising edge inputs
ends programming.
PACT
Programming Active. Used to indicate when programming activity is complete.
PVER
Programming Verification. Signal is low after rising edge of PROG if the programming was not
successful.
AINC
Auto Increment. Active low input enables the auto increment mode. Auto increment will allow
reading or writing of sequential EPROM locations without address transactions across the
PBUS for each read or write.
PORTS
3and4
Address/Command/Data Bus. Used to pass commands, addresses and data to and from
8XC196NT /NOs. Also u.sed in the Auto Programming Mode as a regular system bus to access
external memory.
CPVER
Cumulative Program Verification. Pin is high if all locations since entering a programming mode
have programmed correctly.
II
14-237
infel·
8XC196NTINQQUICK REFERENCE
7.0 OPCODE TABLE
00
SKIP
2F
SCALL
5E
01
CLR
30
JBC
5F
MULUB INDIRECT (3 OPS)
MULUB INDEXED (3 OPS)
02
NOT
31
JBC
60
AND DIRECT (2 OPS)
03
NEG
32
JBC
61
,AND IMMEDIATE (20PS)
04
XCH
'33
JBC
62
AND INDIRECT (2 OPS)
05
DEC
34
JBC
63
AND INDEXED (2 OPS)
06
EXT
35
JBC
64
ADD DIRECT (2 OPS)
07
INC
36
JBC
65
ADD IMMEDIATE (2 OPS)
08
SHR
37
JBC
.66
ADD INDIRECT (2 OPS)
09
SHL
38
JBS
67
ADD INDEXED (20PS)
OA
SHRA
39
JBS
68
SUB DIRECT (2 OPS)
OB
XCH
3A
JBS
69
SUB IMMEDIATE (2 OPS)
OC
SHRL
3B
JBS
6A
SUB INDIRECT (2 OPS)
00
SHLL
3C
JBS
6B
SUB INDEXED (2 OPS)
OE
SHRAL
3D
JBS
6C
MULU DIRECT (2 OPS)
OF
NORML
3E
JBS
60
MULU IMMEDIATE (20PS)
10
RESERVED
3F
JBS
6E
. MULU INDIRECT (2 OPS)
11
CLRB
40
AND DIRECT (3 OPS)
6F
MULU INDEXED (2 OPS)
12
NOTB
41
AND IMMEDIATE (3 OPS)
70
ANDB DIRECT (2 OPS)
13
NEGB
42
AND INDIRECT (3 OPS)
71
ANDB IMMEDIATE (2 OPS)
14
XCHB
43
AND INDEXED (3 OPS)
72
AN DB INDIRECT (2 OPS)
15
DECB
44
ADD DIRECT (3 OPS)
73
AN DB INDEXED (2 OPS)
16
EXTB
45
ADD IMMEDIATE (3 OPS)
74
ADDS DIRECT (2 OPS)
17
INCB
46
ADD INDIRECT (3 OPS)
75
ADDS IMMEDIATE (2 OPS)
18
SHRB
47
ADD INDEXED (30PS)
76
ADDB INDIRECT (2 OPS)
19
SHLB
48
SUB DIRECT (3 OPS)
77
ADDB INDEXED (2 OPS)
1A
SHRAB
49
SUB IMMEDIATE (3 OPS)
78
SUBB DIRECT (2 OPS)
1B
XCHB
4A
SUB INDIRECT (3 OPS)
79
SUSS IMMEDIATE (20PS)
-
1C
EST INDIRECT
4B
SUB INDEXED (3 OPS)
7A
SUBB III/DIRECT (2 OPS)
10
EST INDEXED
4C
MULU DIRECT (3 OPS)
7B
SUBB INDEXED (2 OPS)
1E
ESTB INDIRECT
40
MULU IMMEDIATE (3 OPS)
7C
MUlUB DIRECT (2 OPS)
1F
ESTB INDEXED
4E
MULU INDIRECT (3 OPS)
70
MULUB IMMEDIATE (2 OPS)
20
SJMP
4F
MULU INDEXED (3 OPS)
7E
MULUB INDIRECT (2 OPS)
21
SJMP
50
AN DB DIRECT (3 OPS)
7F
MULUB INDEXED (2 OPS)
22
SJMP
51
ANDB IMMEDIATE (30PS)
80
OR DIRECT
23
SJMP
52
AN DB INDIRECT (3 OPS)
81
OR IMMEDIATE
24
SJMP
53
AN DB INDEXED (3 OPS)
82
OR INDIRECT
25
SJMP
54
ADDB DIRECT (3 OPS)
83
OR INDEXED
26
SJMP
55
ADDB IMMEDIATE (3 OPS)
84
XOR DIRECT
27
SJMP
56
ADDB INDIRECT (3 OPS)
85
XOR IMMEDIATE
28
SCALL
57
ADDB INDEXED (3 OPS)
86
XOR INDIRECT
29
SCALL
58
SUBB DIRECT (3 OPS)
87
XOR INDEXED
2A
SCALL
59
SUBB IMMEDIATE (3 OPS)
88
CMPDIRECT
2B
SCALL
5A
SUBB INDIRECT (3 OPS)
89
CMP IMMEDIATE
2C
SCALL
5B
SUBB INDEXED (3 OPS)
8A
CMP INDIRECT
20
SCALL
5C
MULUB DIRECT (3 OPS)
8B
CMPINDEXED
2E
SCALL
50
MULUB IMMEDIATE (3 OPS)
8C
DIVUDIRECT
14-238
int:eL
8XC196NT/NQ QUICK REFERENCE
7.0 OPCODE TABLE
(Continued)
8D
DIVU IMMEDIATE
B4
ADDCB DIRECT
DA
JLE
8E
DIVU INDIRECT
B5
ADDCB IMMEDIATE
DB
JC
8F
DIVU INDEXED
B6
ADDCB INDIRECT
DC
JVT
90
ORB DIRECT
B7
ADDCB INDEXED
DD
JV
91
ORB IMMEDIATE
B8
SUBCB DIRECT
DE
JLT
92
ORB INDIRECT
B9
SUBCB IMMEDIATE
DF
JE
93
ORB INDEXED
BA
SUBCB INDIRECT
EO
DJNZ
94
XORB DIRECT
BB
SUBCBINDEXED
E1
DJNZW
95
XORB IMMEDIATE
BC
LDBSE DIRECT
E2
TIJMP
96
XORB INDIRECT
BD
LDBSE IMMEDIATE
E3
uEBR (INDIRECT)
97
XORB INDEXED
BE
LDBSE INDIRECT
E4
EBMOVI
98
CMPBDIRECT
BF
LDBSE INDEXED
E5
RESERVED
EJMP
99
CMPB IMMEDIATE
CO
STDIRECT
E6
9A
CMPB INDIRECT
C1
BMOV
E7
WMP
9B
CMPB INDEXED
C2
STINDIRECT
E8
ELD INDIRECT
9C
DIVUB DIRECT
C3
STINDEXED
E9
ELD INDEXED
9D
DIVUB IMMEDIATE
C4
STBDIRECT
EA
ELDB INDIRECT
9E
DIVUB INDIRECT
C5
CMPL
EB
ELDBINDEXED
9F
DIVUB INDEXED
C6
STB INDIRECT
EC
DPTS
AO
LD DIRECT
C7
STBINDEXED
ED
EPTS
A1
LD IMMEDIATE
C8
PUSH DIRECT
EE
RESERVED
A2
LD INDIRECT
C9
PUSH IMMEDIATE
EF
LCALL
A3
LD INDEXED
CA
PUSH INDIRECT
FO
RET
,
A4
ADDCDIRECT
CB
PUSH INDEXED
F1
ECALL
A5
AD DC IMMEDIATE
CC
POP DIRECT
F2
PUSHF
A6
ADDC INDIRECT
CD
BMOVI
F3
POPF
A7
ADDC INDEXED
CE
POP INDIRECT
F4
PUSHA
A8
SUBCDIRECT
CF
POP INDEXED
F5
POPA
A9
SUBC IMMEDIATE
DO
JNST
F6
IDPLD
AA
SUBC INDIRECT
D1
JNH
F7
TRAP
AB
SUBCINDEXED
D2
JGT
F8
CLRC
AC
LDBZE DIRECT
D3
JNC
F9
SETC
AD
LDBZE IMMEDIATE
D4
JNVT
FA
DI
AE
LDBZE INDIRECT
D5
JNV
FB
EI
AF
LDBZE INDEXED
D6
JGE
FC
CLRVT
BO
LDB DIRECT
D7
JNE
FD
NOP
B1
LDB IMMEDIATE
D8
JST
FE
'DIV IDIVB/MUL/MULB
B2
LDB INDIRECT
D9
JH
FF
RST
B3
LDB INDEXED
'Two Byte Instruction - This opcode
unsigned.
IS
placed as the first byte of an instruction to make it a signed operation instead of
14-239
•
intet
8XC196NTINQ QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY
Mnemonic
Flags(2)
Operation(1)
Operands
Z
N
C
V
VT
t
t
t
t
t
t
t
ST
Notes
AOO/AOOB
2
O=O+A
",
",
",
",
AOO/AOOB
3
O=B+A
",
",
",
",
AOOC/AOOCB
2
O=O+A+C
t
",
",
",
SUB/SUBB
2
O=O-A
",
",
",
",
SUB/SUBB
3
O=B-A
",
",
",
",
SUBC/SUBCB
2
0=0-A+C-1
t
",
",
",
CMP/CMPB/CMPL
2
O-A
",
",
",
",
MUL/MULU
2
0,0 + 2 = 0
xA
3
MULIMULU
3
0,0 + 2 = B X A
3
MULB/MULUB
2
0,0 + 1 = 0
4
MULB/MULUB
3
0,0 + 1 =
xA
BxA
OIVU
2
o=
(0,0 + 2)/ A,O + 2 = Remainder
",
OIVUB
2
0= (0,0 + 1)/A,0 + 1 = Remainder
",
OIV
2
o=
",
OIVB
2
0= (0,0 + 1)/A,0 + 1 = Remainder
",
",
4
(0,0 + 2)/ A,O + 2 = Remainder
",
ANO/ANOB
2
0= Oand A
0
0
ANO/ANOB
3
0= BandA
",
",
0
0
OR/ORB
2
0= 0 orA
",
",
0
0
XOR/XORB
2
0= 0 (exclusive or) A
",
",
0
0
LO/LOB
2
O=A
ELb/ELOB
2
O=A
ST/STB
2
A=O
EST/ESTB
2
A=O
XCH
2
o
XCHB
2
O~A
BMOV,
BMOVI/EBMOVI
2
(PTR_HI) + = (PTR_LOW) +;
Until COUNT = 0
LOBSE
2
o=
LOBZE
2
0=A;0+1=0
PUSH
1
SP = SP - 2; (SP) = A
POP
1
A = (SP); SP = SP + 2
PUSHF
0
SP = SP - 2; (SP) = PSW;
PSW = 0; I = 0; PSE = 0
POPF
0
PSW = (SP); SP = SP + 2; I
PUSH A
0
POPA
0
~
A;O + 1
~
t
t
t
t
3
4
A+1
A; 0 + 1 = Sign (A)
4; 5
4, 5
0
0
0
0
0
0
11
",
",
",
",
",
",
11
SP = SP - 2; (SP) = PSW;
PSW = OOOOH; SP = SP - 2;
(SP) = IMASK1/WSR;
IMASK1= OOH; 1= 0; PSE = 0
0
0
0
0
0
0
IMASK1/WSR = (SP); SP = SP + 2;
PSW = (SP); SP = SP + 2
",
",
",
",
",
",
14-240
~
",
inteL
8XC196NT/NQ QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY
Mnemonic
(Continued)
Flags(2)
Operation(1)
Operands
Z
1
PC
LJMP
1
PC
EJMP
1
PC
EBR[lndirect]
1
PC
TIJMP
3
PC
TRAP
0
SP
PC
ECALL
1
SP
PC
LCALL
(16-Bit Mode)
1
SP
PC
LCALL
(24-Bit Mode)
1
SP
PC
SCALL
(16-Bit Mode
1
SP
PC
SCALL
(24-Bit Mode)
1
SP
PC
RET
(16-Bit Mode)
0
PC
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
RET
(24-Bit Mode)
0
PC
= (SP); SP = SP + 4
J(conditioned)
1
JC
1
JNC
1
JE
1
JNE
1
= PC + 8-Bit-Offset (If Taken)
Jump ifC = 1
Jump ifC = 0
Jump if Z = 1
Jump if Z = 0
Jump if N = 0
Jump if N = 1
Jump if N = 0 and Z = 0
Jump if N = 1 or Z = 1
Jump if C = 1 and Z = 0
Jump if C = 0 or Z = 1
Jump if V = 0
Jump if V = 1
Jump if VT = 1; Clear VT
Jump if VT = 0; Clear VT
Jump if ST = 1
Jump ifST = 0
Jump if Specific Bit = 1
Jump if Specific Bit = 0
D = D - 1;
If D
0 then PC = PC + 8-Bit-Offset
JGE
1
JLT
1
JGT
1
JLE
1
JH
1
JNH
1
JV
1
JNV
1
JVT
1
JNVT
1
JST
1
JNST
1
JBS
3
JBC
3
DJNZ/DJNZW
1
PC
PC
C
V
VT
+ 11-Bit-Offset
+ 16-Bit-Offset
+ 24-Bit Offset
SJMP
PC
N
Notes
6
6
6, 12
(A)
12
([index] and MASK)2
SP - 2; (SP)
FF2010H
+
(Table)
= PC;
10
SP - 4; (SP) = PC
PC + 24-Bit Offset,
6, 12
SP - 2; (SP) = PC
PC + 16-Bit Offset
6
SP - 4; (SP) = PC
PC + 16-Bit Offset
6,13
SP - 2; (SP) = PC
PC + 11-Bit Offset
6
SP - 4; (SP) = PC
PC + 11-Bit Offset
6, 13
(SP); SP
= SP + 2
13
PC
*
ST
6
6
6
6
6
6
6
6
6
6
6
6
6
0
0
6
6
6
6
6, 7
6, 7
6
•
int'eL
8XC196NT/NQ QUICK REFERENCE
8.0 INSTRUCTION SET SUMMARY (Continued)
Mnemonic
Operation(1)
Operands
Flags(2)
Z
N
C
V
VT
ST
Notes
i
i
i
OEC/OECB
1
0= 0-1
~
~
~
~
NEG/NEGB
1
0=0-0
~
~
~
~
INC/INCB
1
0=0+1
~
~
~
~
EXT
1
o=
0;0 + 2 = Sign (0)
~
~
0
0
3
EXTB
1
0= 0;0 +1 = Sign (0)
~
~
0
0
4
NOT/NOTB
~
~
0
0
1
o=
CLR/CLRB
1
0=0
1
0
0
0
SHL/SHLB/SHLL
2
C +-- msb."lsb +-- 0
~
~
~
~
SHRISHRB/SHRL
2
o-
~
~
~
0
~
8
SHRAISHRAB/SHRAL
2
~
~
~
0
~
8
NORML
2
msb".lsb - C
msb Left Shift until msb = 1;0 =
Shift Count
~
~
0
Logical Not (0)
msb".lsb -
C
SETC
0
C=1
1
CLRC
0
C=O
0
CLRVT
0
VT = 0
RST
0
PC = 2080H
01
0
Disable All Interrupts (I = 0)
EI
0
Enable All Interupts (I = 1)
OPTS
0
Disable PTS Interrupts (PSE = 0)
EPTS
0
Enable PTS Interrupts (PSE = 1)
NOP
0
PC=PC+1
SKIP
0
PC=PC+2
IPLPO
1
Idle Mode IF Key = 1;
Powerdown Mode IF Key = 2
Chip RESET Otherwise
,
i
8
8
0
0
0
0
0
0
0
9
NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is performed. Operands D, Band
A must conform to the alignment rules for the required operand type. D and B are locations in the Lower Register File; A can
be located anywhere in memorY.
2. The symbols indicate the effects on the flags:
., Cleared or set as appropriate
o Cleared
1 Set
i Set if appropriate; never cleared
t Cleared if appropriate; never set
3. D, D + 2 are consecutive WORDs in memory; D is DOUBLE-WORD aligned.
4. D, D + 1 are consecutive BYTEs in memory; Dis WORD aligned.
5. Changes a BYTE to WORD.
6. Offset is a 2's complement number.
7. Specific Bit must be in or windowed into the Lower Register File.
8. The "L" (LONG) suffix indicates DOUBLE-WORD operations.
9. Initiates a RESET by pulling RESET low. Software should re-initiali~e all the neccessary registers with code starting at
FF2080H.
10. The assembler does not accept this mnemonic (use the macro file for definition).
11. I = Interrupt Enable (PSW1).
12. These instructions will only function in 24-bit mode.
13. These instructions push/pop 2 additional bytes on/off stack in 24-bit mode.
14-242
int:et
8XC196NTINQ QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODES
Mnemonic
Indirect
Indexed
Direct
Immed
Normal(1)
A-lnc(1)
Short(1)
ADD (3-op)
SU8 (3-op)
ADD (2-op)
SU8 (2-op)
AD DC
SU8C
CMP
ADD8 (3-op)
SU88 (3-op)
ADD8 (2-op)
SU88 (2-op)
ADDC8
SU8C8
CMP8
4/44
4/48
3/64
3/68
3/A4
3/AS
3/88
4/54
4/58
3/74
3/78
3/84
3/88
3/98
5/45
5/49
4/65
4/69
4/A5
4/A9
4/89
4/55
4/59
3/75
3/79
3/85
3/89
3/99
4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/86
3/8A
3/9A
4/46
4/4A
3/66
3/6A
3/AB
3/AA
3/8A
4/56
4/5A
3/76
3/7A
3/86
3/8A
3/9A
5/47
5/48
4/67
4/68
4/A7
4/A8
4/88
5/57
5/58
4/77
4/78
4/87
4/88
4/98
6/47
6/48
5/67
5/68
5/A7
5/A8
5/88
6/57
6/58
5/77
5/78
5/87
5/88
• 5/98
MUL(3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MUL8 (3-op)
MULU8 (3-op)
MUL8 (2-op) ,
MULU8 (2-op)
DIV8
DIVU8
5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
3/7C
4/(2)
3/9C
6/(2)
5/4D
5/(2)
4/6D
5/(2)
4/8D
5/(2)
4/5D
4/(2)
3/7D
4/(2)
3/9D
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
3/7E
4/(2)
3/9E
6/(2)
5/4F
5/(2)
4/6F
5/(2)
4/8F
6/(2)
5/5F
5/(2)
4/7F
5/(2)
4/9F
7/(2)
6/4F
6/(2)
5/6F
6/(2)
5/8F
7/(2)
6/5F
6/(2)
5/7F
6/(2)
5/9F
AND (3-op)
AND (2-op)
OR (2-op)
XOR
AND8 (3-op)
AND8 (2-op)
OR8 (2-op)
XOR8
4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94
5/41
4/61
4/81
4/85
4/51
3/71
3/91
3/95
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96
5/43
4/63
4/83
4/87
5/53
4/73
4/93
4/97
6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97
PUSH
POP
2/C8
2/CC
3/C9
2/CA
2/CE
2/CA
2/CE
3/CB
3/CF
4/C8
4/CF
Long(1)
LD
3/AO
4/A1
3/A2
3/A2
4/A3
5/A3
LD8
3/80
3/81
3/82
3/82
4/83
5/83
ELD
3/E8
3/E8
6/E9
ELD8
3/EA
3/EA
6/E8
ST
3/CO
3/C2
3/C2
4/C3
5/C3
ST8
3/C4
3/C6
3/C6
4/C7
5/C7
EST
3/1C
3/1C
6/10
EST8
3/1E
3/1E
6/1F
14-243
•
inlet
8XC196NT/NQ QUICK REFERENCE
9.0 INSTRUCTION LENGTH/OPCODES (Continued)
Mnemonic
Indexed
Indirect
Direct
Immed
Normal(1)
A·lnc(1)
Short(1)
Long(1)
3/04
-
-
4/0B
5/0B
XCHB
3/14
-
-
4/1B
5/1B
LOBSE
3/BC
3/BO
3/BE
3/BE
4/BF
5/BF
LBSZE
3/AC
3/AO
3/AE
3/AE
4/AF
5/AF
XCH
Mnemonic
Length/Opcode
Mnemonic
PUSHF
POPF
PUSHA
POPA
1/F2
1/F3
1/F4
1/F5
TRAP
LCALL
SCALL
ECALL
RET
WMP
SJMP
EJMP
EBR[]
TIJMP
1/F7
JNE
JE
JBC
JBS
DJNZ
DJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
3/EF
2/2B-2F(3)
4/F1
1/FO
3/E7
2/20-27(3)
4/E6
2/E3
4/E2
Length/Opcode
1/07
1/0F
3/30-37
3/3B-3F
3/EO
3/E1
3/0F
3/0C
3/0D
3/0E
3/0B
3/1B
3/09
3/19
3/0A
3/1A
1/00
1/0B
1/01
1/09
1/02
CLRC
SETC
DI
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
BMOV
BMOVi
EBMOVI
1/0A
1/B3
1/0B
1/04
1/DC
1/05
1/00
1/06
1/0E
NOTES:
1/FB
1/F9
1/FA
1/FB
1/EC
1/EO
1/FC
1/FO
1/FF'
2/00
1/F6
3/C1
3/CO
3/E4
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
'
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.
3. The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.
14-244
int:eL
8XC196NT/NQ QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
Instruction
Direct
Immediate
Indirect
Indexed
Normal
A·lnc
Short
Long
5
6
7/10
8/11
7/10
8/11
SUB (30p)
5
6
7/10
8/11
7/10
8/11
ADD (2op)
4
5
6/8
7/9
6/8
7i9
SUB (2op)
4
5
6/8
7/9
6/8
7/9
ADDC
4
5
6/8
7/9
6/8
7/9
SUBC
4
5
6/8
7/9
6/8
7/9
CMP
4
5
6/8
7/9
6/8
7/9
AD DB (30p)
5
5
7/10
8/11
7/10
8/11
SUBB (30p)
5
5
7/10
8/11
7/10
8/11
7/9
6/8
7/9
ADD (30p)
AD DB (2op)
4
4
6/8
SUBB (2op)
4
4
6/8
7/9
6/8
7/9
ADDCB
4
4
6/8
7/9
6/8
7/9
SUBCB
4
4
6/8
7/9
6/8
7/9
CMPB
4
4
6/8
7/9
6/8
7/9
19/22
19/22
20/23
CMPL
7
MUL (30p)
16
17
18/21
MULU (30p)
14
15
16/19
17/20
17/20
18/21
MUL (2op)
16
17
18/21
19/22
19/22
20/23
MULU (2op)
14
15
16/19
17/20
17/20
18/21
DIV
26
27
28/31
29/32
29/32
30/33
DIVU
24
25
26/29
27/30
27/30
28/31
MULB (30p)
12
12
14/17
15/18
15/18
16/19
MULUB (30p)
10
10
12/15
12/16
12/16
14/17
MULB (2op)
12
12
14/17
15/18
15/18
16/19
MULUB (2op)
10
10
12/15
12/16
12/16
14/17
DIVB
18
18
20/23
21/24
21/24
22/25
DIVUB
16
16
18/21
19/22
19/22
20/23
AND (30p)
5
6
7/10
8/11
7/10
8/11
7/9
7/9
AND (2op)
4
5
6/8
7/9
6/8
OR
4
5
6/8
7/9
6/8
XOR
4
5
6/8
7/9
6/8
7/9
ANDB (30p)
5
5
7/10
8/11
7/10
8/11
ANDB (2op)
4
4
6/8
7/9
6/8
7/9
ORB
4
4
6/8
7/9
6/8
7/9
7/9
7/10
XORB
4
4
6/8
7/9
6/8
LD
4
5
5/8
6/8
6/9
14-245
Extended
•
int'et
8XC196NT/NQ QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES) (Continued)
Instruction
. Direct
ST
4
LOB
4
STB
4
Immediate
Indirect
Indexed
Normal
A-Inc
Short
Long
5/8
6/9
6/9
7/10
Extended
5/8
6/8
6/9
7/10
5/8
6/9
6/9
7/10
ELD
6/9
8/11
8/11
EST
6/9
8/11
8/11
4
ELDB
6/9
8/11
8/11
ESTB
6/9
8/11
8/11
XCH
5
8/13
9/14
STB
4
8/13
9/14
5
8/13
9/14
XCHB
BMOV
BMOVI
EBMOVI
+ 8 per Word
6 + 11 /14 per Word
7 + 8 per Word
7 + 11/14 per Word
+ 14 for Each Interrupt + 14 for Each Interrupt
8 + 14/20 per Word
+ 16 for Each Interrupt
6
LOBSE, LDBZE
4
4
PUSH (int)
6
7
POP (int)
8
PUSHF (int)
6
POPF (int)
7
PUSHA (int)
12
POPA (int)
12
PUSH (ext)
8
POP (ext)
11
PUSHF (ext)
8
POPF (ext)
10
PUSHA (ext)
18
POPA (ext)
18
EJMP (24-Bit Mode)
8
LJMP
7
SJMP
7
EBR[lndirectj(24-Bit Mode)
9
BR[lndirect]
7
TIJMP (Internal Table)
15
TIJMP (External Table)
18
TRAP (24-Bit Mode, Int)
19
TRAP (16-Bit Mode, Int)
16
9
517
6/8
6/8
7/9
9/12
10/13
10/13
11/14
10/12
11/13
11/13
12/14
11/14
12/15
12/15
13/16
13/15
14/16
14/16
15/17
14-246
8XC196NT/NQ QUICK REFERENCE
10.0 INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
Instruction
Direct
ECALL (24-Bit Mode, Int)
16
LCALL (16-Bit Mode, Int)
11
LCALL (24-Bit Mode, Int)
15
SCALL {16-Bit Mode, Int
11
SCALL (24-Bit Mode, Int)
15
RET (24-Bit Mode,lnt)
16
RET (16-Bit Mode, Int)
11
TRAP (24-Bit Mode, Ext)
25
TRAP (16-Bit Mode, Ext)
18
ECALL (24-Bit Mode, Ext)
22
LCALL (16-Bit Mode, Ext)
13
LCALL (24-Bit Mode, Ext)
18
SCALL (16-Bit Mode, Ext)
13
SCALL (24-Bit Mode, Ext)
18
RET (24-Bit Mode, Ext)
22
RET (16-Bit Mode, Ext )
14
JNST, JST
Immediate
Indirect
Normal
4/8 Jump Not Taken/Jump Taken
JGT, JLE
4/8 Jump Not TakenlJump Taken
JNC,JC
4/8 Jump Not TakenlJump Taken
JNVT,JVT
4/8 Jump Not Taken/Jump Taken
JNV, JV
4/8 Jump Not Takenl Jump Taken
JGE, JLT
4/8 Jump Not TakenlJump Taken
JNE,JE
4/8 Jump Not Takenl Jump Taken
JBS,JBC
5/9 Jump Not TakenlJump Taken
DJNZ
5/9 Jump Not TakenlJump Taken
DJNZW
6/10 Jump Not TakenlJump Taken
CLR, NOT, NEG
3
DEC,INC
3
EXT
4
CLRB, NOTB
3
DECB,INCB
3
NEGB
3
EXTB
SHRL
SHLL
Indexed
Short
Long
Extended
4/8 Jump Not Taken/Jump Taken
JNH,JH
NORML
A-Inc
(Continued)
4
+ 1 per Shift (9 for 0 Shift)
7 + 1 per Shift (8 for 0 Shift)
7 + 1 per Shift (8 for 0 Shift)
8
14-247
II
intel .
10~O
8XC196NT/NQ QUICK REFERENCE
INSTRUCTION EXECUTION TIMES (IN STATE TIMES)
Instruction
Direct
I Immediate
Indirect
:
Normal
SHRB
6
+ '1 per Shift (8 for 0 Shift)
+ 1 per Shift (7 for 0 Shift)
+ 1 per Shift (7 for 0 Shift)
+ 1 per Shift (7 for 0 Shift)
+ 1 per Shift (7 for 0 Shift)
SHLB
6
+ 1 per Shift (7 for 0 Shift)
SHRAB
6
+
SHRAL
7
SHR
6
SHL
6
SHRA
6
CLRC
2
SETC
2
01
2
EI
2
OPTS
2
EPTS
2
CLRVT
2
NOP
RST
SKIP
10LPO
A-Inc
(Continued)
Indexed
Short
Extended
Long
1 per Shift (7 for 0 Shift)
2
20 (Includes Fetch of CCBO/CCB1)
3
8/25 (Proper Key/Improper Key)
PTS
Single Transfer
18
Burst Transfer
13
PWM Modes
15
AID Scan Mode
( + 3 for Ext Reference, + 1 If XFER Count = 0)
(+ 7 for Each Transfer, 1 Minimum
+ 3 for Each Memory Controller Reference)
i
21/25
NOTES:
The timing figures are minimum execution times expressed as state times (one period of CLKOUT = two oscillator periods)
and are based on the following assumptions:
'
I. The opcode, along with any required operands, have been'pre-fetched and reside in the instruction queue.
2. The bus controller operates with the 16-bit bus 'selected and without wait states for external memory references and prefetches. For instructions with indirect or indexed addressing, execution times separated by a slash are for instructions requiring a fetch from internal/external memory.
3. Times for jumps, calls and returns include the 4 state times required to flush the pre·fetch queue and to fetch the opcode
at the destination address. This is reflected in the jump taken/not-taken times shown in the table.
'
14-248
intel~
8XC196NT/NQ QUICK REFERENCE
11.0 INTERRUPT TABLE
Name
Source
Vector
Priority
FF203EH
32 (Highest)
INT15
NMI
PTS14
EXTINTPin
FF205CH
31
PTS13
Reserved
FF205AH
30
PTS12
Receive SIO
FF2058H
29
PTS11
Transmit SIO
FF2056H
28
PTS10
SSIO Channel 1 Transfer
FF2054H
27
PTS09
SSIO Channel 0 Transfer
FF2052H
26
PTS08
Command Buffer Full (SLP)
FF2050H
25
PTS07
Input Buffer Full (SLP)
FF204EH
24
PTS06
Output Buffer Empty (SLP)
FF204CH
23
PTS05
AID Conversion Complete
FF204AH
22
PTS04
EPAO
FF2048H
21
PTS03
EPA1
FF2046H
20
PTS02
EPA2
FF2044H
19
PTS01
EPA3
FF2042H
18
PTSOO
EPA4-9, Overrun (EPAO-9),
CompareO-1, Timer Overflow
FF2040H
17
INT14
EXTINTPin
FF203CH
16
INT13
Reserved
FF203AH
15
INT12
ReceiveSIO
FF2038H
14
INT11
Transmit SIO
FF2036H
13
INT10
SSIO Channel 1 Transfer
FF2034H
12
INT09
SSIO Channel 0 Transfer
FF2032H
11
INT08
Command Buffer Full (SLP)
FF2030H
10
N/A
UNIMPLEMENTED OPCODE
FF2012H
09
N/A
TRAP
FF2010H
08
INT07
Input Buffer Full (SLP)
FF200EH
07
INT06
Output Buffer Empty (SLP)
FF200CH
06
INT05
AID Conversion Complete
FF200AH
05
INT04
EPAO
FF2008H
04
INT03
EPA1
FF2006H
03
INT02
EPA2
FF2004H
02
INT01
EPA3
FF2002H
01
INTOO
EPA4-9, Overrun (EPAO-9),
CompareO-1, Timer Overflow
FF2000H
00 (Lowest)
14-249
•
intel·
8XC196NT/NQ QUICK REFERENCE
12.0 FORMULAS
State TIme = 2 Oscillator Periods
TIJMP CalculationDestination = ([INDEX) AND INDEX-MASK) x 2
+
[TBASE)
EPA PrescalerPO
0
1
0
1
0
1
0
1
P1
0
0
1
1
0
0
1
1
P2
o
o
o
o
1
1
1
1
+ 1
+2
+4
+8
+ 16
+ 32
+ 64
Reserved
810 Baud RateModes 1,2 and 3
SP BAU D
-
=
XTAl1 Frequency
Baud Rate x 16
-
1
SP BAU D = T1 ClK Frequency - 1
Baud Rate x 8
(B
~
0, SP_BAUD.15 = 1)
(B > 0, SP_BAUD.15 = 0)
Mode 0
SP BAUD = XTAl1 Frequency - 1
Baud Rate x 2
(B > 0, SP_BAUD.15 = 1)
SP BAUD = T1 ClK Frequency - 1
Baud Rate
(B> 0, SP_BAUD.15 = 0)
8810 Baud RateSSIO.O - SS10.6 = XTAL1 Frequency - 1
.
Baud Rate x 8
AIDSample States = 4 x SAM + 1
(SAM = AD_TIME.5 - AD_TIME.7)
Conversion States = B x (CONV + 1) + 1.5
(CONV = AD_TIME.O - AD_TIME.4)
(B = 8 for 8-Bit Conversion)
(B = 10 for 10-Bit Conversion)
Total Conversion Time = State Time x [(4 x SAM)
+
(B x (CONV
Programming Pulse WidthPPR = «PPW) x (FOSC» - 144
144
+ 32768
14-250
+
1»
+
2.5]
intel·
8XC196NT/NQ QUICK REFERENCE
13.0 RESET STATUS
Reset Value
SFR
AD_RESULT
7FBOH
AD_COMMAND
OCOH
AD_TEST
OCOH
AD_TIME
OFFH
SSIOO_BUF, SSI01_BUF
SSIOO
OOH
CON
CON, SSI01
OOH
SSIO_BAUD (Baud Rate Control (Read))
OXXXXXXXB
SSIO_BAUD (Baud Rate Down Count (Write))
OOH
SBUF_RX,SBUF_TX
OOH
SP
STAT
OBH
SP_CON
EOH
SP_BAUD
COMPO
OOOOH
CON, COMP1
CON
OOH
COMPO_TIME, COMP1_TIME
CON, EPA3
EPA1
OOOOH
OOOOH
CON
EPA)LCON (x = 0, 2, 4-9)
OOH
EPA)LTIME (x = 0-9)
OOOOH
TIMER1, TIMER2
OOOOH
T1 CONTROL, T2CONTROL
OOH
EPA-.MASK, EPA_MASK1
OOH
EPA-.PEND, EPA-.PEND1
OOH
EPAIPV
OOH
PO_PIN, P1_PIN, P3_PIN, P4_PIN, P6_PIN, EP_PIN
XXH
P1
MODE, P6_MODE
P1
DIR, P5
DIR,P6
OOH
P2
PIN, P5
OFFH
DIR
P1_REG, P3_REG, P4_REG, P5_REG,
P6~REG,
EP_REG
OFFH
1XXXXXXXB
PIN
P2_MODE, P5_MODE
BOH
P2
7FH
INT
DIR, P2
REG
MASK,INT
OOH
PEND
INT_MASK1,INT_PEND1
OOH
OOOOH
PTSSRV, PTSSEL
OOH
WSR
14-251
II
intet
8XC196NT/NQ QUICK REFERENCE
Pin States, during Reset, Idle and Powerdown
Pin Name
Reset
Idle
PO
RESET
wk1
wk1
wk1
ALE (P5.0)
wk1
(A)
(A)
.INST (P5.1)
wkO
(A)
(A)
RD (P5.3), WR (P5.2),
SPLINT (P5.4)
wk1
(I)
(I)
8HE (P5.5)
wk1
(8)
(8)
READY (P5.6),
8USW (P5.7)
wk1
(C)
(C)
EA, NMI
HZ
HZ
HZ
EP, P3, P41 AD (EA = 0)
wk1
HZ
HZ
EP, P3, P4/AO (EA = 1)
wk1
0010
0010
HZ
ACH/PO
HZ
HZ
P1
wk1
(D)
(D)
elk, LZ
(E)
(G)
P2.0-P2.6
wk1
(E)
(E)
P6.0-P6.7
wk1
(F)
(F)
Vpp
HZ
1, LZ
1, LZ
CLKOUT (P2.7)
XTAL1
HZ
HZ
HZ
XTAL2
ose, LZ
ose, LZ
(H)
NOTES:
(A) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1 and HLDA = 1, then LZ 0. If P5_MODE.x = 1 and
HLDA = 0, then HZ.
(8) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1 and HLDA = 1, then LZ 1. If P5_MODE.x = 1 and
HLDA = 0, then HZ.
(C) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1, then HZ.
(D) If P1_MODE.x = 0, port is as programmed. If P1_MODE.x = 1, pin is as specified by P1_DIR and associated
peripheral.
(E) If P2_MODE.x = 0, port is as programmed. If P2_MODE.x = 1, pin is as specified by P2_DIR and associated
peripheral.
(F) If P6_MODE.x = 0, port is as programmed. If P6_MODE.x = 1, pin is as specified by P6_DIR and associated
peripheral.
(G) If P2_MODE.7 = 0, port is as programmed. If P2_MODE.7 = 1, then LZ 0.
(H) If XTAL 1 = 1, then LZ 0. IF XTAL1 = 0, then LZ 1.
(I) If P5_MODE.x = 0, port is as programmed. If P5_MODE.x = 1, then pin is as specified by P5_DIR and associated
peripheral.
.
= High impedance
HZ
LZ
= Low Impedance
wk1 = Weakly pulled high
ODIO = Open drain input/output
osc = Oscillator
wkO = Weakly pulled low
14-252
int'el.
October 1991
MCS®-96 AID Converter
Quick Reference
Order Number: 272115-001
14-253
iniaL
MCS-96 AID CONVERTER QUICK REFERENCE
1.0 The MCS-96 AID Converter
Analog inputs to the MCS-96 family are handled by the
AID converter system. As shown in Figure I, the converter system has an 8 channel multiplexer, a sample
and hold, and a lO-bit successive approximation AID
converter. Conversions can be performed on one of 8
channels, the inputs of which share pins with port O.
There are various versions of the AID converter, depending on the specific device type. The 8X9X family
offers a lO-bit fixed conversion time. The 8XCI96KB
family offers a 10-bit conversion with either a fast or
slow conversion time. The 8XC196KC family offers an
8- or lO-bit conversion with programmable sample and
convert times. The 8XCI96KR has all of the KC features, with the addition of offset correction and internal
conversion of Vref and ANGND. The 8XCI96MC includes all of the KR features, and the multiplexer has
been expanded to 13 analog input channels.
This chapter describes the basic operation and terminology of the AID converter. The different devices
control the AID in different ways, but the principals of
operation remain the same throughout.
1.1 AID Conversion Process
The conversion process is initiated by an HSO or EPA
command, or by writing a one to the GO Bit in the
AID Control Register. Either activity causes a start
conversion signal to be sent to the AID converter controllogic.
Once the AID unit receives a start conversion signal,
there is a one state time delay before sampling (Sample
Delay) while the successive approximation register is
reset and the proper mUltiplexer channel is selected.
After the sample delay, the multiplexer output is connected to the sample capacitor and remains connected
for the sample time. After the "sample window" closes,
the input to the sample capacitor is disconnected from
the multiplexer so that changes on the input pin will
not alter the stored charge while the conversion is in
progress. The comparator is then auto-zeroed and the
conversion begins. The sample delay and sample time
uncertainties are each approximately ± 50 ns, independent of clock speed.
To perform the actual analog-to-digital conversion the
MCS-96 implements a successive approximation algorithm. The converter hardware consists of a 256-resistor ladder, a comparator, coupling capacitors and a
lO-bit successive approximation register (SAR) with
logic that guides the process. The resistor ladder provides 20 mV steps (VREF = 5.12V), while capacitive
coupling creates 5 mV steps within the 20 mV ladder
voltages. Therefore, 1024 internal reference voltages are
available for comparison against the analog input to
generate a 10-bit conversion result.
A successive approximation conversion is performed by
comparing a sequence of reference voltages, to the analog input, in a binary search for the reference voltage
that most closely matches the input. The '/2 full scale
reference voltage is the first tested. This corresponds to
a lO-bit result where the most significant bit is zero,
and all other bits are ones (0111.1 11 1.1 lb). If the analog input was less than the test voltage, bit 10 of the
SAR is left a zero, and a new test voltage of '14 full scale
(OOI1.1111.11b) is tried. If this test voltage was lower
than the analog input, bit 9 of the SAR is set and bit 8
is cleared for the next test (0101.1111.11 b). This binary
search continues until 10 tests have occurred, at which
time the valid lO-bit conversion result resides in the
SAR where it can be read by software.
1.2 AID Interface Suggestions
The external interface circuitry to an analog input is
highly dependent upon the application, and can impact
converter characteristics. In the external circuit's design, important factors such as input pin leakage, sample capacitor size and multiplexer series resistance from
the input pin to the sample capacitor must be considered.
These factors are idealized in Figure 1. The external
input circuit must be able to charge a sample capacitor
(Cs) through a series resistance (RI) to an accurate
voltage given a DC leakage (IL)' Typically Cs is around
2 pF, RI is around 5 K!1 and IL is specified as 3 /LA. In
determining the necessary source impedance Rs, the
value of VBIAS is not important.
otjt>
VS1A:l.
272115-1
Figure 1. Idealized AID Sampling Circuitry
External circuits with source impedances of 1 K!1 or
less will be able to maintain an input voltage within a
tolerance of about ±0.61 LSB (1.0 K!1 X 3.0 /LA =
3.0 mY) given the DC leakage. Source impedances
above 2 K!1 can result in an external error of at least
one LSB due to the voltage drop caused by the 3 /LA
leakage. In addition, source impedances above 25 K!1
may degrade converter accuracy as a result of the internal sample capacitor not being fully charged during the
sample window.
14-254
inteL
MCS-96 AID CONVERTER QUICK REFERENCE
If large source impedances degrade converter accuracy
because the sample capacitor is not charged during the
sample time, an external capacitor connected to the pin
compensates for this. Since the sample capacitor is
2 pF, a O.OOS f.LF capacitor (2048 • 2 pF) will charge
the sample capacitor to an accurate input voltage of
±O.S LSB. An external capacitor does not compensate
for the voltage drop across the source resistance,but
charges the sample capacitor fully during the sample
time.
Placing an external capacitor on each analog input will
also reduce the sensitivity to noise, as the capacitor
combines with series resistance in the external circuit to
form a low-pass filter. In practice, one should include a
small series resistance prior to the external capacitor on
the analog input pin and choose the largest capacitor
value practical, given the frequency of the signal being
converted. This provides a low-pass filter on the input,
while the resistor will also limit input current during
over-voltage conditions.
Figure 2 shows a simple analog interface circuit based
upon the discussion above. The circuit in the figure also
provides limited protection against over-voltage conditions on the analog input. Should the input voltage inappropriately drop significantly below ground, diode
D2 will forward bias at about 0.8 DeV. Since the specification of the pin on most devices has an absolute maximum low voltage of -0.3V, this will leave about O.SV
across the 270n resistor, or about 2 rnA of current.
This should limit the current to a safe amount. Note
that if any input pins are driven much beyond VREF or
below ANGND, the accuracy of all analog input channels may be adversely affected. This is because the input protection circuit will start to conduct, thus injecting current into the internal reference circuitry and upsetting the reference voltage. Refer to the data sheet for
exact device specifications.
However, before any circuit is used in an actual application, it should be thoroughly analyzed for applicability to
the specific problem at hand.
VREF
DI
FR?M USER CIRCUIT
>-"'>---..JVVIr-.-a ANALOG
INPUT PIN
D2
ANGND
272115-2
Figure 2. Suggested AID Input Circuit
ANALOG REFERENCES
Reference supply levels and noise strongly influence the
absolute accuracy of the conversion. For this reason, it
is recommended that the ANGND pin be tied to the
Vss pins close to the device. Bypass capacitors should
also be used between VREF and ANGND. ANGND
should be within about a tenth of a volt of Vss· VREF
should be well regulated and used only for the A/D
converter. The VREF supply_ needs to be able to source
around SmA.
Note that if only ratiometric information is desired,
VREF can be connected to Vee. In addition, VREF and
ANGND must be connected even if the A/D converter
is not being used. Remember that Port 0 receives its
power from the VREF and ANGND pins even when it
is used as digital I/O.
1.3 The AID Transfer Function
The conversion result is a 8- or lO-bit ratiometric representation of the input voltage, so the numerical value
obtained from the conversion will be:
INT [255
x (V,N - ANGND)/(VREF - ANGND)l or
INT [1023
x (V,N - ANGND)/(VREF - ANGND)]
This produces a stair-stepped transfer function when
the output code is plotted versus input voltage (see Fig- •
ure 3). The resulting digital codes can be taken as simpie ratiometric information, or they provide information about absolute voltages or relative voltage changes
on the inputs. The more demanding the application is
on the A/D converter, the more important it is to fully
understand the converter's operation. For simple applications, knowing the absolute error of the converter is
sufficient. However, closing a servo-loop with analog
inputs necessitates a detailed understanding of an A/D
converter's operation and errors.
The errors inherent in an analog-to-digital conversion
process are many: quantizing error, zero offset, fullscale error, differential non-linearity and non-linearity.
These are "transfer function" errors related to the A/D
converter. In addition, converter temperature drift,
Vee rejection, sample-hold feed through, multiplexer
off-isolation, channel-to-channel matching and random
noise should be considered. Fortunately, one "Absolute
Error" specification is available which describes the
sum total of all deviations between the actual conversion process and an ideal converter. However, the various SUb-components of error are important in many
applications. These error components are described in
the text below where ideal and actual converters are
compared.
14-255
•
_.
€:
7
I
FINAL CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO (Vref - 1 1/2 (LSB».
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ACTUAL CHARACTERISTIC OF
AN IDEAL A/D CONVERTER
Q
~
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o
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.....
N
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C
I
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THE VOLTAGE CHANGE
BETWEEN ADJACENT CODE
TRANSITIONS (THE ""CODE
WIDTH"") IS
1 LSB.
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=
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om
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FIRST CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO 1/2 LSB.
o
1/2
2
3
I
4
INPUT VOLTAGE (LSBs)
5
6
61/2
7
8
272115-3
_.
7
--
6
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CHARACTERISTIC
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ZERO OFFSET
O~--~~-.--------'--------.---------'--------r--------.----r----'--------.
1/2
2
4
3
INPUT VOLTAGE (LSBs)
I
5
6
61/2
7
B
272115-4
_.
c(
7
IDEAL FULL-SCALE CODE
TRANSITION
ACTUAL
FULL -SCALE CODE
TRANSITION
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IDEAL FIRST TRANSITION
1/2
2
3
4
INPUT VOLTAGE (LSBs)
5
6
61/2
7
8
272115-5
inteL
MCS-96 AID CONVERTER QUICK REFERENCE
An unavoidable error simply results from the conversion of a continuous voltage to an integer digital representation. This error is called quantizing error, and is
always ± 0.5 LSB. Quantizing error is the only error
seen in a perfect AID converter, and is obviously present in actual converters. Figure 3 shows the transfer
function for an ideal 3-bit AID converter (i.e., the Ideal
Characteristic).
Note that in Figure 3 the Ideal Characteristic possesses
unique qualities: its first code transition occurs when
the input voltage is 0.5 LSB; its full-scale code transition occurs when the input voltage equals the fullscale reference minus 1.5 LSB; and its code widths are
all exactly one LSB. These qualities result in a digitization without offset, full-scale or linearity errors. In other words, a perfect conversion.
Figure 4 shows an Actual Characteristic of a hypothetical 3-bit converter, which is not perfect. When the Ideal
Characteristic is overlaid with the imperfect characteristic, the actual converter is seen to exhibit errors in the
location of the first and final code transitions and code
widths. The deviation of the first code transition from
ideal is called "zero offset", and the deviation of the
final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two
types of errors. Differential Non-Linearity and NonLinearity. Differential Non-Linearity is a local linearity
error measurement, whereas Non-Linearity is an overall linearity error measure.
Differential Non-Linearity is the degree to which actual
code widths differ from the ideal one LSB width. It
gives the user a measure of how much the input voltage
may have changed in order to produce a one count
change in the conversion result. Non-Linearity is the
worst case deviation of code transitions from the corresponding code transitions of the Ideal Characteristic.
Non-Linearity describes how much Differential NonLinearities could add up to produce an overall maximum departure from a linear characteristic. If the Differential Non-Linearity errors are too large, it is possible for an AID converter to miss codes or exhibit nonmonotonicity. Neither behavior is desirable in a closedloop system. A converter has no missed codes if there
exists for each output code a unique input voltage range
that produces that code only. A converter is monotonic
if every subsequent code change represents an input
voltage change in the same direction.
Differential Non-Linearity and Non-Linearity are
quantified by measuring the Terminal Based Linearity
Errors. A Terminal Based Characteristic results when
an Actual Characteristic is shifted and rotated to eliminate zero offset and full-scale error (see Figure 5). The
Terminal Based Characteristic is similar to the Actual
Characteristic that would be seen if zero offset and fullscale error were externally trimmed away. In practice,
this is done by using input circuits which include gain
and offset trimming. In addition, VREF could also be
closely regulated and trimmed within the specified
range to affect full-scale error.
Other factors that affect a real AID Converter system
include sensitivity to temperature, failure to completely
reject all unwanted signals, multiplexer channel dissimilarities and random noise. Fortunately these effects are
small.
Temperature sensitivities are described by the rate at
which typical specifications change with a change in
temperature.
Undesired signals come from three main sources. First,
noise on V cc- Vee Rejection. Second, input signal
changes on the channel being converted after the sample window has closed-Feedthrough. Third, signals applied to channels not selected by the multiplexer-OffIsolation.
Finally, multiplexer on-channel resistances differ slightly from one channel to the next causing Channel-toChannel Matching errors, and random noise in general
results in Repeatability errors.
1.4 AID Glossary of Terms
Figures 3, 4 and 5 display many of these terms. Refer to
AP-406 'MCS-96 Analog Acquisition Primer' for additional information on the AID terms.
ABSOLUTE ERROR-The maximum difference between corresponding actual and ideal code transitions.
Absolute Error accounts for all deviations of an actual
converter from an ideal converter.
ACTUAL CHARACTERISTIC-The characteristic of
an actual converter. The characteristic of a given converter may vary over temperature, supply voltage, and
frequency conditions. An Actual Characteristic rarely
has ideal first and last transition locations or ideal code
widths. It may even vary over multiple conversion under the same conditions.
BREAK-BEFORE-MAKE-The property of a multiplexer which guarantees that a previously selected
channel will be deselected before a new channel is selected. (e.g., the converter will not short inputs together.)
CHANNEL-TO-CHANNEL MATCHING-The difference between corresponding code transitions of actual characteristics taken from different channels under
the same temperature, voltage and frequency conditions.
CHARACTERISTIC-A graph of input voltage versus
the resultant output code for an AID converter. It de,scribes the transfer function of the AID converter.
14-259
II
intel~
MCS-96 AID CONVERTER QUICK REFERENCE
CODE-The digital value output by the converter.
CODE CENTER-The voltage corresponding to the
midpoint between two adjacent code transitions.
CODE TRANSITION-The point at which the converter changes from an output code of Q, to a code of
Q+ L The input voltage corresponding to a code transition is defined to be that voltage which is equally likely to produce either of two adjacent codes.
CODE WIDTH- The voltage corresponding to the difference between two adjacent code transitions.
NON-LINEARITY - The maximum deviation of code
transitions of the terminal based characteristic from the
corresponding code transitions of the ideal characteristics.
OFF-ISOLATION-Attenuation of a voltage applied
on a deselected channel of the AID converter. (Also
referred to as Crosstalk.)
REPEATABILITY - The difference between corresponding code transitions from different actual characteristics taken from the same converter on the same
channel at the same temperature, voltage and frequency
conditions.
CROSSTALK-See "Off-Isolation".
DC INPUT LEAKAGE-Leakage current to ground
from an analog input pin.
DIFFERENTIAL NON-LINEARITY - The difference
between the ideal and actual code widths of the terminal based characteristic of a converter.
FEEDTHROUGH-Attenuation of a voltage applied
on the selected channel of the AID converter after the
sample window closes.
FULL SCALE ERROR-The difference between the
expected and actual input voltage corresponding to the
full scale code transition.
IDEAL CHARACTERISTIC-A characteristic with
its first code transition at V IN = 0.5 LSB, its last code
transition at VIN = (VREF - 1.5 LSB) and all code
widths equal to' one LSB.
INPUT RESISTANCE-The effective series resistance
from the analog input pin to the sample capacitor.
~SB (LEAST SIGNIFICANT BIT)-The voltage value
corresponding to the full scale voltage divided by 2n ,
where n is the number of bits of resolution of the converter. For a IO-bit converter with a reference voltage
of 5.12 volts, one LSB is 5.0 mY. Note that this is
different than digital LSBs, since an uncertainty of two
LSBs, when referring to an AID converter, equals
10 mY. (This has been confused with an uncertainty of
two digital bits, which would mean four counts, or
20 mV.)
MONOTONIC-The property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value,
and that decreasing input voltages produce adjacent
codes of decreasing value.
NO MISSED CODES-For each and every output
code, there exists a unique input voltage range which
produces that code only.
RESOLUTION - The number of input voltage levels
that the converter can unambiguously distinguish between. Also defines the number of useful bits of information which the converter can return.
SAMPLE DELAY-The delay from receiving the start
conversion signal to when the sample window opens.
SAMPLE. DELAY UNCERTAINTY-The variation
in the Sample Delay.
SAMPLE TIME-The time that the sample window is
open.
SAMPLE TIME UNCERTAINTY-The variation in
the sample time.
SAMPLE WINDOW -Begins when the sample capacitor is attached to a selected channel and ends when the
sample capacitor is disconnected from the selected
channel.
SUCCESSIVE APPROXIMATION-An AID conversion method which uses a binary search to arrive at
the best digital representation of an analog input.
TEMPERATURE COEFFICIENTS-Change in the
stated variable per degree centigrade temperature
change. Temperature coefficients are added to the typical values of a specification to see the effects of temperature drift.
TERMINAL BASED CHARACTERISTIC-An Actual Characteristic which has been rotated and translated to remove zero offset and full-scale error.
Vee REJECTION-Ratio of the change in the AID
characteristic to the change in Vee.
ZERO OFFSET-The difference between the expected
and actual input voltage corresponding to the first code
transition.
14-260
8X9X Data Sheets
15
•
809XBH/839XBH/879XBH
COMMERCIAL/EXPRESS HMOS MICROCONTROLLER
II 879XBH: an 809XBH with 8 Kbytes of On-Chip EPROM
III 839XBH: an 809XBH with 8 Kbytes of On-Chip ROM
•
•
•
•
•
•
232 Byte Register File
II High Speed I/O Subsystem
Register-to-Register Architecture
III Full Duplex Serial Port
10-Bit A/D Converter with S/H
01 Dedicated Baud Rate Generator
Five 8-Bit I/O Ports
•
20 Interrupt Sources
6.25 }J-s 16 x 16 Multiply
III 6.25 }J-s 32116 Divide
fill 16-Bit Watchdog Timer
Pulse-Width Modulated Output
• Run-Time Programmable EPROM
• Extended Temperature Available
II Four 16-Bit Software Timers
ROM/EPROM Lock
.
II Two 16-Bit Counter/Timers
•
Extended Burn-In Available
The MCS®-96 family of 16-bit microcontrollers consists of many members, all of which are designed for highspeed control functions. The MCS-96 family members produced using Intel's HMOS-III process are described
in this data sheet.
The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the
instruction set. With a 12 MHz input frequency the 8096BH can do a 16-bit addition in 1.0 jLs and a 16 x 16-bit
multiply or 32/16 divide in 6.25 jLs. Instruction execution times average 1 to 2 jLs in typical applications.
Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can
simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once.
The on-chip AID converter includes a Sample and Hold, and converts up to 8 multiplexed analog input
channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 jLs. This. feature is only
available on the 8X95BHs and 8X97BHs, with the 8X95BHs having 4 multiplexed analog inputs.
PORTO PORT 1
PORT 2
AL T FUNCTIONS
HSI
HSO
270090-50
Figure.1. 8X9XBH Block Diagram
15-1
July 1992
Order Number: 270090-010
II
int'eL
8X9XBH
Also provided on-chip are a serial port, a Watchdog
Timer and a pulse-width modulated output signal.
With the. extended burn-in option, the burn-in is dynamic for a minimum time of 160 hours at 125°C with
Vee = 5.5V ±0.5V, following the guidelines in MILSTD-883, Method 1015.
With the commercial (standard) temperature option,
operational characteristics are guaranteed over the
temperature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are guaranteed over the temperature
range of -40°C to +85°C. Unless otherwise noted,
the specifications are the same for both options.
See the Packaging Information for extended temperature and extended burn-in designators.
OFFH , . . - - - - - - - - - - - - - - - , 255,
POWER-DOWN
RAM
OFOH
240
OEFH
r-------------------~
INTERNAL
REGISTER FILE
(RAM)
239
FFFFH
lAH L-_ _ _ _ _ _ _ _ _ _ _ _.J
19H
STACK POINTER
STACK POINTER
1SH
EXTERNAL MEMORY
OR I/O
25
4000H
24
17H
PWM_CONTROL
23
22
16H
IOS1
10Cl
1SH
10SO
lOCO
14H
13H
26
INTERNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY
21
20aOH
20
RESERVED
RESERVED
12H
RESERVED
19
18
l1H
SP_STAT
SP_CON
17
10H
10 PORT 2
10 PORT 2
16
OFH
10 PORT 1
10 PORT 1
15
OEH
10 PORT 0
BAUD_RATE
14
SIGNATURE WORD
2070H - 2071 H
RESERVED
2030H - 206FH
SECURITY KEY
2020H - 202FH
RESERVED
201CH-201FH
SELF JUMP OPCODE (27H FEH)
RESERVED
201AH-201BH
2019H
ODH
TIMER2 (HI)
OCH
TIMER2 (LO)
OSH
TIMERl (HI)
OAH
TIMERl (LO)
WATCHDOG
09H
INLPENDING
INLPENDING
OSH
INLMASK
INLMASK
a
07H
SBUF (RX)
SBUF (TX)
7
PORT 4
lFFFH
06H
HSI_STATUS
HSO_COMMAND
6
PORT 3
lrFEH
OSH
HSLTIME (HI)
Hso_nME (HI)
5
04H
HSLTIME (LO)
HSO_TlME (LO)
4
EXTERNAL MEMORY
OR I/o
03H
AD_RESULT (HI)
HSI_MODE
3
02H
AD_RESULT (LO)
AD_COMMAND
2
01H
RO (HI)
RO (HI)
1
OOH
RO (LO)
RO (LO)
0
(WHEN READ)
13
2072H - 207FH
RESERVED
CHIP CONFIGURATION BYTE
12
RESERVED
11
10
201aH
201 2H - 201 7H
INTERRUPT VECTORS
9
2000H
L
INTERNAL RAM
REGISTER FILE
STACK POINTER
SPECIAL FUNCTION REGISTERS
(WHEN ACCE~SED AS DATA MEMORY)
0100H
OOFFH
OOOOH
(WHEN WRITIEN)
270090-6
Figure 2. 8X9XBH Memory Map
15-2
int'eL
8X9XBH
PACKAGING
The S096SH is available in 4S-pin, 64-pin and 6S-pin packages, with and without AID, and with and without onchip ROM or EPROM. The S096SH numbering system is shown in Figure 3. Figures 5-10 show the pinouts for
the 4S-, 64- and 6S-pin packages. The 4S-pin version is offered in a Dual-In-Line package while the 6S-pin
versions come in a Plastic Leaded Chip Carrier (PLCC), a Pin Grid Array (PGA) or a Type "S" Leadless Chip
Carrier.
Factory Masked
ROM
68-Pin
ANALOG
64-Pin
48-Pin
User Programmable
CPU
EPROM
68-Pin
64-Pin
48-Pin
68-Pin
8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH
NO ANALOG 8396BH
64-Pin
OTP
48-Pin
68-Pin
64-Pin
48-Pin
8795BH 8797BH 8797BH
8096BH
Figure 3. 8X9X Packaging
Package Designators:
N = PLCC
C = Ceramic DIP
A = Ceramic Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP
Package Type
Prefix Designators:
T = Extended Temperature
L = Extended Temperature with 160 Hours Burn-in
BJa
Blc
6SL PGA
35"C/W
10"C/W
6SLPLCC
37"C/W
13"C/W
6SL LCC
2S"C/W
14"C/W
64L Shrink DIP
56"C/W
-
4SL Plastic DIP
3S"C/W
19"C/W
48L Ceramic DIP
26"C/W
6.S"C/W
Flgur!:! 4. 8X9XBH Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240S00) for a description of Intel's thermal impedance test methodology.
15-3
•
intel~
EA
ACH3/PO.3
ACH 1/PO.1
ACHO/PO.O
ACH2/PO.2
ACH6/PO.6/PMODE.2
ACH7 /PO. 7/PMODE.3
ACH5/PO.5/PMODE. 1
ACH4/PO.4/PMODE.0
ANGND
VREF
VpD
EXTINT /P2.2/PROG
RESET
RxD/P2. 1/PALE
TxD/P2.0/PVER/SALE
P1.0
P1.1
P1.2
P1.3
P1.4
HSI.O/SID.O
HSI. 1/SID. 1
HSO.4/HSI.2/SID.2
HSO.5/HSI.3/SID.3
HSO.O/PACT
HSO.1
P1.5
P1.6
P1.7
P2.6
HSO.2
8X9XBH
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Vee
Vss
XTAL1
XTAL2
ALE/ADV
RD
ADO/P3.0
AD1/P3.1
AD2/P3.2
AD3/P3.3
AD4/P3.4
AD5/P3.5
AD6/P3.6
AD7/P3.7
AD8/P4.0
AD9/P4.1
AD10/P4.2
AD11/P4.3
AD12/P4.4
AD13/P4.5
AD14/P4.6
AD 15/P4. 7
T2CLK/P2.3
READY
T2RST/P2.4
BHE/WRH
WR/WRL
PWM/P2.5/PDO/SPROG
P2.7
Vpp
Vss
HSO.3
270090-56
Figure 5. 64-Pin Shrink-DIP Package
15-4
inteL
1P~[g!bmMlOOO~~w
8X9XBH
Pins Facing Down
17 15 13 11
9
7
5
3
8
6
4
18 19 16 14 12 10
2
68
67 66
20 21
68-PIN
GRID ARRAY
65 64
26 27
TOP VIEW
61 60
28 29
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
59 58
22 23
24 25
30 31
63 62
57 56
55 54
32 33
34 36 38 40 42 44 46 48 50 53 52
35 37 39 41 43 45 47 49 51
270090-4
Figure 6. 68-Pin PGA Package
Description
Description
PGA
Description
PGA
1
ACH7 IPO.7 IPMODE.3
24
AD6/P3.6
47
P1.6
P1.S
PGA
2
ACH6/PO.6/PMODE.2
25
AD7/P3.7
48
3
ACH2/PO.2
26
AD8/P4.0
49
HSO.1
4
ACHO/PO.O
27
AD9/P4.1
50
HSO.O/PACT
5
ACH1/PO.1
28
AD10/P4.2
51
HSO.5/HSI.3/SID.3
6
ACH3/PO.3
29
AD11/P4.3
52
HSO.4/HSI.2/SID.2
7
NMI
30
AD12/P4.4
53
HSI.1/SID.1
8
EA
31
AD13/P4.5
54
HSI.O/SID.O
9
Vee
32
AD14/P4.6
55
P1.4
10
Vss
33
AD15/P4.7
56
P1.3
P1.2
11
XTAL1
34
T2CLK/P2.3
57
12
XTAL2
35
READY
58
P1.1
13
CLKOUT
36
T2RST/P2.4
59
P1.0
14
BUSWIDTH
37
BHE/WRH
60
TXD/P2.0/PVERISALE
15
INST
38
WR/WRL
61
RXD/P2.1/PALE
16
ALE/ADV
39
PWM/P2.5/PDO/SPROG
62
RESET
17
RD
40
P2.7
63
EXTINTIP2.2/PROG
18
ADO/P3.0
41
Vpp
64
VPD
VREF
19
AD1/P3.1
42
Vss
65
20
AD2/P3.2
43
HSO.3
66
ANGND
21
AD3/P3.3
44
HSO.2
67
ACH4/PO.4/PMODE.0
68
ACH5/PO.5/PMODE.1
22
AD4/P3.4
45
P2.6
23
AD5/P3.5
46
P1.7
Figure 7. PGA Function Pinouts
15-5
•
intel~
8X9XBH
ACHS/PO.S/PNOOE.l
ADO/P3.0
ACH4/PO.4/PMOOE.O
ADI/P3.1
ANOND
AD2/P3.2
AD3/P3.3
VREF
VPD
AD4/P3.4
68-PIN
LEADLESS CHIP CARRIER
TYPE "B"
(EPROtA ONLY)
EXTI NT/P2.2/PROO
RESET
RXD/P2.1/PALE
TXO/P2. O/PVER/SALE
AD5/P3.5
AD6/P3.6
AD7/P3.7
AD8/P4.0
TOP VIEW
Pl.D
AD9/P4.1
LOOKING DOWN ON
COtAPONENT SIDE
OF' PC BOARD
Pt.l
Pl.2
Pl.3
ADI0/P4.2
AD11/P4.3
ADI2/P4.4
P1.4
ADI3/P4.5
HSI.O/SIO.D
ADI4/P4.6
HSI.1/SID.l
HSO.4/HSI.2/SID.2
ADI5/P4.7
52
34
T2CLK/P2.3
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
270090-5
Figure 8. 68-Pln LCC Package
15-6
intel~
8X9XBH
ACH5/PO.5/PIoIODE.l
ADO/P3.0
ACH4/PO.4/PIoIODE.0
AD1/P3.1
ANGND
AD2/P3.2
AD3/P3.3
VREf
S8-PIN
PLCC
VpD
EXTINT/P2.2/PROG
AD4/P3.4
AD5/P3.5
iffii'
AD6/P3.6
RXD/P2.1/PALE
AD7/P3.7
TXD/P2.0/PVER/5ALE
AD8/P4.0
TOP VIEW
Pl.0
AD9/P4.1
Pl.l
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
Pl.2
Pl.3
Pl.4
H51.0/5ID.0
AD10/P.4.2
ADll/P4.3
ADI2/P4.4
ADI3/P4.5
ADI4/P4.6
H51.1/5ID.l
ADI5/P4.7
T2CLK/P2.3
H51.2/H50.4/5ID.2
27 28 29 30 31 32 33 34 35 38 37 38 39 40 41 42 43
g
5!
~~
VI a. :z:
00(
III
;;:
. a:: ..... ...5! '"
~
": co
~~~l~~"
d >cn>Q.~f~a~ ~
VI
is
:z: :z:
II:
:z: :z:
~I;
I~ ~/:!
..
'"
iii
:z:
......
:::IE
~o
6i g
....'"
......
l
270090-3
Figure 9. 68-Pin PLCC Package
15·7
8X9XBH
RXD/P2. l/PALE
RESET
TXD/P2.0 /PVER/SALE
2
EXTINT /P2.2/PROG
HSI.O/SID.O
3
VpD
HSI.1 /SID. 1
4
VREF
HSI.2/HSO.4/SID.2
5
ANGND
HSI.3/HSO.5/SID.3
6
ACH4/PO.4/PMODE.O
HSO.O/PACT
7
ACH5/PO.5/PMODE.1
HSO.1
8
ACH7 /PO. 7/PMODE.3
HSO.2
9
ACH6/PO.6/PMODE.2
HSO.3
10
EA
VSS
11
Vpp
12
PWM/P2.5/PDO/SPROG
13
XTAL1
WRL/WR
14
XTAL2
WRH/BHE
15
ALE/ADV
READY
16
RD
AD15/P4.7
17
ADO/P3.0
AD14/P4;6
18
AD1/P3.1
AD13/P4.5
19
AD2/P3.2
AD12/P4.4
20
AD3/P3.3
AD11/P4.3
21
AD4/P3.4
AD10/P4.2
22
AD5/P3.5
AD9/P4.1
23
AD6/P3.6
AD8/P4.0
24
AD7/P3.7
48-PIN
DIP
Vee
Vss
270090-2
Figure 10. 48-Pln DIP Package
15·8
intel .
8X9XBH
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are two Vss pins, both of which must be connected.
VPD
RAM standby supply voltage (5V). This voltage must be present during normal operation.
In a Power Down condition (i.e. Vee drops to zero), if RESET is activated before Vee
drops below spec and VpD continues to be held within spec., the top 16 bytes in the
Register File will retain their contents.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the
analog portion of the AID converter and the logiC used to read Port O. Must be
connected to use AID or Port O.
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential·
asVss·
VPP
Programming voltage for the EPROM devices. It should be + 12.75V for programming
and will float to 5V otherwise. The pin should not be above Vee for ROM and CPU
devices. This pin must be left floating in the application circuit for EPROM devices.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT*t
Output of the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency. It has a 33% duty cycle.
RESET
Reset input to the chip. Input low for a minimum 10 XTAL1 cycles to reset the chip. The
subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-statetime RESET sequence.
BUSWIDTH*t
Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the
bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0
an a-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an a-bit bus. If this pin is left
unconnected, it will rise to Vee.
NMI*t
A positive transition causes a vector to external memory location OOOOH.
INST*t
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle.
EA
Input for memory select (External Access). EA equal to a TIL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TIL-low causes accesses to these locations to be directed to off-chip
memory. EA equal to 12.75V causes the device to enter the Programming Mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes high at the end of the bus cycle. ALE/ ADV is activated only during external
memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory
reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCA. WR will go low
for every external write, while WRL will go low only for external writes where an even byte
is being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE
will go low for external writes to the high byte of the data bus. WRH will go low for
external writes where an odd byte is being written. BHE/WRH is activated only during
external memory writes.
15-9
8X9XBH
PIN DESCRIPTIONS (Continued)
Symbol
READY
\
Name and Function
Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge
of CLKOUT, the memory controller goes into a wait mode until the next positive transition
of CLKOUT occurs with READY high. When the external memory is not being used,
READY has no effect. Internal control of the number of wait states inserted into a bus
cycle held not ready is available in the, CCA.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSLO, HSL1, HSI.2 and
HSL3. Two of them (HSL2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO,1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0:1=
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
.
Port 1t
8-bit quasi-bidirectional I/O port.
Port 2t
8-bit multi-functional port. Six of its pins are shared with other functions in the 8096BH, the
remaining 2 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Ports 3 and 4 are also
used as a command, address and data path by EPROM devices operating in the
Programming Mode. •
PMODE
Determines the EPROM programming mode.
PACT
A low signal in Auto Programming Mode indicates that programming is in progress. A high
signal indicates programming is complete.
PVAL
A low signal in Auto Programming Mode indicates that the device programmed correctly.
SALE
A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid
programming address/command information (output from master).
SPROG
A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid
programming data (output from master).
SID
ASSigns a pin of Ports 3 and 4 to each slave to pass programming verification.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates that Ports 3 and 4 contain valid programming address/command
information (input to slave).
PROG
A falling edge in Slave Programming Mode indicates that Ports :3 and 4 contain valid
programming data (input to slave).
.
PVER
A high Signal in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates the byte programmed correctly.
PVAL
A high signal in Slave Programmjn!!l Mode indicates the device programmed correctly.
PD~
A low signal in Slave Programming Mode indicates that the PROG pulse was applied for
longer than allowed.
"Not available on Shnnk-DIP package
tNot available on 48-pin device
:j:Port 0.0.1.2.3 not available on 48-pin device
15-10
infel~
8X9XBH
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias - 55·C to + 125·C
Storage Temperature .......... -60·C to + 150·C
Voltage from EA or Vpp
to VSS or ANGND ............ -0.3V to + 13.0V
Voltage from Any Other Pin to
VssorANGND ............. -0.3Vto +7.0V(1)
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Average Output Current from Any Pin ....... 10 rnA
Power Dil';sipation(2) .................. : .... 1.5W
NOTES:
1. This includes Vpp and EA on ROM and CPU only
devices.
2. Power dissipation is based on package heat
transfer limitations, not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
Parameter
Min
Max
Units
TA
Ambient Temperature Under Bias Commercial Temp.
0
+70
·C
TA
Ambient Temperature Under Bias Extended Temp.
-40
+85
·C
Vcc
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50'
V
Fosc
Oscillator Frequency
6.0
12
MHz
VpD
Power-Down Supply Voltage
4.50
5.50
V
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
Icc
Vcc Supply Current Commercial Temp.
240
rnA
Icc
Vcc Supply Current Extended Temp.
270
rnA
ICCl
Vcc Supply Current (TA ~ 70·C)
185
rnA
IpD
VPD Supply Current
1
rnA
IREF
VREF Supply Current Commercial Temp.
8
rnA
IREF
VREF Supply Current Extended Temp.
10
rnA
VIL
Input Low Voltage
+0.8
V
-0.3
15-11
Test Conditions
All Outputs
Disconnected.
Normal operation
and Power-Down.
•
8X9XBH
DC CHARACTERISTICS (Continued)
Symbol
Parameter
Min
Max
Units
Vee + 0.5
V
Test Conditions
VIH
Input High Voltage (Except RESET,
NMI, XTAL1)
2.0
VIHl
Input High Voltage, RESET Rising
2.4
Vee + 0.5
V
VIH2
Input High Voltage, RESET Falling
(Hysteresis)
2.1
Vee + 0.5
V
VIH3
Input High Voltage, NMI, XTAL1
2.2
Vee + 0.5
V
III
Input Leakage Current to each pin of
HSI, P3, P4, and to P2.1.
±10
,...A
Vin = OtoVCC
ILll
DC Input Leakage Current to each pin
of PO
+3
,...A
Vin =
o to Vee
IIH
Input High Current to EA
100
,...A
VIH = 2.4V
IlL
Input Low Current to each pin of P1,
and to P2.6, P2.7 Commercial Temp.
-125
,...A
VIL = 0.45V
IlL
Input Low Current to each pin of P1,
and to P2.6, P2.7 Extended Temp.
-150
,...A
VIL = 0.45V
IILl
Input Low Current to RESET
-2
rnA
VIL 0= 0.45V
IIL2
Input Low Current P2.2, P2.3, P2.4,
READY, BUSWIDTH
-50
,...A
VIL = 0.45V
VOL
Output Low Voltage on QuasiBidirectional port pins and P3, P4 when
used as ports
0.45
V
IOL = O.SmA
(Note 1)
VOll
Output Low Voltage on QuasiBidirectional port pins and P3, P4 when
used as ports
0.75
V
IOL = 2.0 rnA
(Notes 1, 2, 3)
VOl2
Output Low Voltage on Standard
Output pins, RESET and Bus/Control
Pins
0.45
V
IOL = 2.0 rnA
(Notes 1, 2, 3)
VOH
Output High Voltage on QuasiBidirectional pins
2.4
V
IOH=-20,...A
(Note 1)
VOHl
Output High Voltage on Standard
Output pins and Bus/Control pins
2.4
V
IOH = -200,...A
(Note 1)
IOH3
Output High Current on RESET
-50
Cs
Pin Capacitance (Any Pin to VSS)
-0.25
10
,...A
VOH = 2.4V
pF
FTEST = 1.0 MHz
NOTES:
,
1. Quasi-bidirectional pins include those on Pl, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR,INST and ADO-15.
2. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V.
IOL on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 rnA
IOL on standard output pins and RESET: 8.0 rnA
IOL on Bus/Control pins: 2:0 rnA
3. During normal (non-transient) operation the following limits apply:
Total IOL on Port 1 must not exceed 8.0 rnA.
TotaiiOL on P2.0, P2.6, RESET and all HSO pins must not exceed 15 rnA.
TotailOL on Port 3 must not exceed 10 rnA.
TotaiiOL on P2.5, P2.7, and Port 4 must not exceed 20 rnA. '
15-12
infel·
8X9XBH
AC CHARACTERISTICS
Test Conditions: Load Capacitance on Output Pins = 80 pF
TIMING REQUIREMENTS (The system must meet these specifications to work with the 8X9XBH.)
Symbol
Parameter
Min
Max
0(1)
Units
TCLYX(2,3)
READY Hold after CLKOUT Edge
TLLYV
End of ALE/ ADV to READY Valid
hLYH
End of ALE/ ADV to READY High
TYLYH
Non-Ready Time
TAVDV(4)
Address Valid to Input Data Valid
5 Tosc - 120(6)
ns
TRLDV
RD Active to Input Data Valid
3 Tosc - 100(6)
ns
TRHDX
Data Hold after RD Inactive
0
TRHDZ
RD Inactive to Input Data Float
0
TAVGv(2,4)
Address Valid to BUSWIDTH Valid
TLLGX(2,3)
BUSWIDTH Hold after ALE/ ADV Low
TLLGV(2,3)
ALE/ ADV Low to BUSWIDTH Valid
TRLPV
Reset Low to Ports Valid
2 Tosc
+ 40
ns
2 Tosc - 70
ns
4 Tosc - 80
ns
1000
ns
ns
Tosc - 25
2 Tosc - 125
Tosc
+ 40
ns
ns
ns
Tosc - 75
ns
10 Tosc
ns
NOTES:
1. If the 48-pin or 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge
has occurred at 2 Tesc + 66 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. Pins not bonded out on 64-pin devices.
3. Pins not bonded out on 48-pin devices.
4. The term "Address Valid" applies to ADO-16, BHE and INST.
6. If wait states are used, add 3 Tesc· N where N = number of wait states.
•
15-13
intel .
8X9XBH
TIMING RESPONSES (MCS·96 devices meet these specs.)
Symbol
Parameter
Min
Max
Units
FXTAL
Oscillator Frequency
6.0
12.0
MHz
Tosc
Oscillator Period
83
166
ns
0(4)
120(4)
ns
3 TOSC<3)
3 TOSC<3)
ns
Tosc - 35
Tosc + 10
ns
-30
+15
ns
Tosc - 25
Tosc + 45
ns
Tosc - 30
Tosc + 35(5)
ns
TOHCH
XTAL1 Rising Edge to Clockout Rising Edge
TCHCH(1,4)
CLKOUT Period(3)
TCHCL(1,4)
CLKOUT High Time
TCLLH(1, 4)
CLKOUT Low to ALE High
TLLCH(4)
ALE! ADV Low to CLKOUT High(1)
TLHLL
ALE! ADV High Time
TAVLL(6)
Address Setup to End of ALE! ADV
Tosc - 50
TRLAZ(7)
RD or WR Low to Address Float Commercial Temp.
TRLAZ(7)
RDor WR Low to Address Float Extended Temp.
TLLRL
End of ALE!ADV to RD or WR Active
Typ. = 0
ns
10
ns
25
ns .
ns
Tosc - 40
TLLAX(7)
Address Hold after End of ALE! ADV
Tosc - 40
ns
TWLWH
WR Pulse Width
3 Tosc - 35(2)
ns
TaVWH
Output Data Valid to End of WR!WRL!WRH
3 Tosc - 60(2)
ns
TWHax
Output Data Hold after WR!WRL!WRH
Tosc - 50
ns
TWHLH
End of WR!WRLlWRH to ALE! ADV High
Tosc - 75
ns
TRLRH
RD Pulse Width
3 Tosc - 30(2)
ns
TRHLH
End of RD to ALE! ADV High
Tosc - 45
TCLLL(4)
CLOCKOUT Low(1) to ALE! ADV Low
Tosc - 40
TRHBX(4)
RD High to INST(1), BHE, AD8·15 Inactive
Tosc - 25
Tosc + 30
ns
TWHBX(4)
WR High to INST(1), BHE, AD8·15 Inactive
Tosc - 50
Tosc + 100
ns
THLHH
WRL, WRH Low to WRL, WRH High
2 Tosc - 35
2 Tosc + 40
ns
lLLHL
ALE! ADV Low to WRL, WRH Low
2 Tosc
2 Tosc + 55
ns
TaVHL
Output Data Valid to WRL, WRH Low
- 30
Tosc - 60
ns
Tosc + 35
ns
ns
NOTES:
1. Pins not bonded out on 64·pin devices.
2. If more than one wait state is desired, add 3 TOSC for each additional wait state.
3. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3 Tosc ± 10 ns if TOSC is constant and
the rise and fall times on XTAL1 are less than 10 ns.
4. CLKOUT, INST, and BRE pins not bonded out on 48-pin and 64-pin devices.
5. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
6. The term "Address Valid" applies to ADO-15, BRE and INST.
7. The term" Address" in this definition applies to ADO-7 for 8·bit cycles, and ADO-15 for 16-bit cycles.
15·14
infel"
8X9XBH
WAVEFORM--SYSTEM BUS TIMINGS
XTAL1
CLOCKOUT
REAOY
--- •.'.. - - - - - - - ..
--~---------
•'to ________ •
•',. _.
SHE, INST
.
~----~----~----------------~---{~-------------.
!14.---TWLWH ---~
ADB-15 ~(~1l)____~::::::::::::::~V!A~LI~D:::::::::::::::)~~~:~:~::::::::::~:~:~:~:~:::::
270090-47
II
NOTES:
1. 8-bit bus only.
2. 8-bit or 16-bit bus and write strobe mode selected.
3. When ADV selected.
4. 8- or 16-bit bus and no write strobe mode selected.
WAVEFORM--BUSWIDTH * TIMINGS
XTAL1
CLKOUT
SUSWIDTH - - - - + - - {
ALE/ ADV _______
J
ADDRESS/DATA--------~~~~~:)~---------(!D~AT~A~IN~--------------270090-35
• Buswidth is not bonded out on 48- and 64-pin devices.
15-15
8X9XBH
EXTERNAL CLOCK DRIVE
Min
Max
Units
Oscillator Frequency
6
12
MHz
High Time
25
TOLOX
Low Time
30
TOLOH
Rise Time
15
ns
TOHOL
Fall Time
15
ns
Symbol
Parameter
1/TOLOL
TOHOX
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270090-48
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up. This is due to interaction
between the amplifier and its feedback capacitance. Once the external Signal meets the VIL and VIH specifications the
capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
Cl
Vss
11~1- ~--tXTALI
~
.......
8X9X
XTAL2
4.7K r--------,
>o-......---f XTAL 1
EXTERNAL
CLOCK INPUT
clock driver
8X9X
Quartz Crystal or
Ceramic Resonator
270090-58
no connect
XTAL2
NOTE:
270090-59
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and Vss. When
using crystals,' Cl = 30 pF and C2 = 30 pF. When
using ceramic resonators, consult manufacturerer for
recommended capacitor values.
AC TESTING INPUT, OUTPUT WAVEFORMS
U = : > ( 2.0> TEST POINTS
O.B
0.45
<
2.0
O.B
AC TESTING FLOAT WAVEFORMS
VLOAO +O.20V
~
VLOAD
V LOAO -O.20 V
270090-49
AC Testing inputs are driven at 2.4V for a Logic "I" and 0.45V for
a Logic "0". Timing measurements are made at 2.0V for a Logic
"I" and 0.8V for a Logic "0".
VOH -O.20V
>TI~INGp~~gENCE<
VOL +0.20 V
270090.,.51
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs, and Begins to Float
when a 200 mV change from the Loaded VOHIVOL Level occurs
IOLIIOH:': ± 8 mAo
15-16
intel·
8X9XBH
MINIMUM HARDWARE CONFIGURATION CIRCUITS
fLOAT
Vpp
VpD
48 LEAD
DEVICES
VREF
EA
VCC ....~~...,
270090-53
270090-52
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: Load Capacitance = 80 pF
Symbol
Parameter
Min
TXLXL
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TQVXH
Output Data Setup to Clock Rising Edge
TXHQX
Output Data Hold After Clock Rising Edge
Max
Units
ns
8 Tosc
TXHQV
Next Output Data Valid After Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold After Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
4 Tosc - 50
4 Tosc
+
50
ns
2 Tosc - 70
ns
2 Tosc
2 Tosc
+
+ 50
_
ns
0
5 Tosc
Power Supply RIM Tim.
_5.5VOC
Vrx;
_4.5VOC
XTAL
___ Start Time from Powlr Supply RI •• to Ext.rnal Output Low
111111111 1111111111111111111111111111111111111111111111111111111111111111111111111111111111
)f
RESET
HSO.O-HSO.3.
P2.0. P2.5
--
to Int.rnal
-I f-t- External
R.lea •• Tim.
10 STATE TIMES
I
PORT 3 1:-4
WITH PULLUPS
TRLPV = 10XTAL CYCLES
External RESET Low to
Port Valid Time
I
IADDRESSe ADDRESS
2018H
CCB
fiRST BUS rETCH CYCLE
-
RESET FUNCTION REGISTERS
I
20aOH
PROGRAM
START
I
TOTAL 8X9XBH RESET TIME
270090-60
15-17
ns
ns
200
WAVEFORM-T RLPV
-
ns
3 Tosc
ns
•
intet
8X9XBH
WAVEFORM-5ERIAL PORT-5HIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
r"""l.r """l.r """l.r """l.r .""l.r """l.r """l.r """l.r
TXLXl--J
TXD
TQVXH
-!
I-
TXLXH-I
TXHQV
~
-I
II
TXHQZ-l
RXD
(OUT)
RXD--~r--.'-~r-~I--'r~.r-~,~~r--.r-~r-~I~'r~.~~,r-~r~.r-
(IN)
270090-36
AID CONVERTER SPECIFICATIONS
AID Converter operation is verified only on the 8097BH, 8397BH, 809SBH, 839SBH, 8797BH, 879SBH.
The absolute conversion accuracy is dependent on the accuracy and stability of VREF.
See the MCS-96 AID Converter Quick Reference for definitions of AID Converter terms.
Parameter
Typical'
Resolution
Minimum
Maximum
Units"
1024
10
1024
10
Levels
Bits
0
±4
LSBs
Absolute Error
Full Scale Error
Zero Offset Error
-O.S ±O.S
LSBs
±O.S
LSBs
0
±4
LSBs
> -1
+2
LSBs
0
±1
LSBs
Non-Linearity
Differential Non-Linearity
Notes
Channel-to-Channel Matching
Repeatability
±0.2S
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBI"C
LSBI"C
LSBI"C
-60
dB
1,3
Feedthrough
-60
dB
1
VCC Power Supply Rejection
-60
dB
1
SK
n
4
2
Off Isolation
Input Series Resistance
1K
0
3.0
Sample Delay
3 Tosc - SO
3 Tosc + SO
/LA
ns
Sample Time
12 Tosc - SO
12 Tosc + SO
ns
2
pF
DC Input Leakage
Sampling Capacitor
NOTES:
• These values are expected for most devices at 25'C.
•• An "LSB", as used here, is defined in the MCS-96 AID Converter Quick Reference and has a value of approximately
5 mY.
1. DC to 100 KHz.
2. For starting the AID with an HSO Command.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
1S-18
int:eL
8X9XBH
EPROM SPECIFICATIONS
EPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
°C
TA
Ambient Temperature during Programming
20
30
Vee. VPD. VREF(1)
Supply Voltages during Programming
4.5
5.5
V
9.0
13.0
V(2)
12.50
13.0
V(2)
VEA
Programming Mode Supply Voltage
Vpp
EPROM Programming Supply Voltage
Vss. ANGND(3)
Digital and Analog Ground
0
0
V
Fose 1
Oscillator Frequency during Auto and Slave Programming
6.0
6.0
MHz
Fose2
Oscillator Frequency during Run-Time Programming
6.0
12.0
MHz
NOTES:
1. Vee. VPD and VREF should nominally be at the same voltage during programming.
2. VEA and VPP must never exceed the maximum voltage for any amount of time or the device may be damaged.
3. Vss and ANGND should nominally be at the same voltage (OV) during programming.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
TAVLL
ADDRESS/COMMAND Valid to PALE Low
0
Tose
TLLAX
ADDRESS/COMMAND Hold After PALE Low
80
Tose
TDVPL
Output Data Setup Before PROG Low
0
Tose
TpLDX
Data Hold After PROG Falling
80
Tose
TLLLH
PALE Pulse Width
180
Tose
TpLPH
PROG Pulse Width
250 Tose
TLHPL
PALE High to PROG Low
250
Tose
TpHLL
PROG High to Next PALE Low
600
Tose
TpHDX
Data Hold After PROG High
30
Tose
TpHVV
PROG High to PVER/PDO Valid
500
Tose
hLVH
PALE Low to PVER/PDO High
100
Tose
TpLDV
PROG Low to VERIFICATION/DUMP Data Valid
100
Tose
TSHLL
RESET High to First PALE Low (not shown)
2000
Tose
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Ipp
Parameter
Vpp Supply Current (Whenever Programming)
15-19
100 J.Ls +
144 Tose
•
8X9XBH
WAVEFORM-EPROM PROGRAMMING
PORTS 3,4
PALE--_
PROG---~---~~-,
PORTS 3,4
PVER
_"';';';;;';;;'...J
PDO
_ _ _oJ
VALID
VALID
270090-43
occurs within 9 states after the first, the events
will be entered separately with time-tags at least
one count apart. If the second event enters the
FIFO coincident with the "skipped" time-tag situation (see B above) the time tags will be at least
two counts apart.
8X9XBH ERRATA
Devices covered by this data sheet (see Revision
History) have the following errata.
1. INDEXED, 3 OPERAND MULTIPLY
The displacement portion of an indexed, three operand (byte or word) multiply may not be in the range
of 200H thru 17FFH inclusive. If you must use these
displacements, execute an indexed, two operand
multiply and a move if necessary.
3. RESERVED LOCATION 2019H
2. HSI FIFO OPERATION
4. RESERVED LOCATION 201CH
The High Speed Input (HSI) has three deviations
from the specifications. Note that "events" are defined as one or more pin transitions. "Entries" are
defined as the recording of one or more events.
A. The resolution is nine states instead of eight
states. Events occurring on the same pin more
frequently than once every nine states may be
lost.
B. A mismatch between the nine state HSI resolution and the eight state hardware timer causes
one time-lag value to be skipped every nine timer
counts. Events may receive a time-tag one count
later than expected.
C. If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register,
leaving the FIFO empty again. The next event
that occurs will be the first event loaded into the
empty FIFO. If the first two events into an empty
FIFO (not counting the Holding Register) occur
coincident with each other, both are recorded as
one entry with one time-tag. If the second event
Reading reserved location 201CH, either internally
or externally, will return "201 C" as data.
The 1990 Architectural Overview recommended that
address 2019H be loaded with OFFH. The recommendation is now 20H.
5. SERIAL PORT SECTION
Serial Port Flags-Reading SP_STAT may not
clear the TI or RI flag if that flag was set within two
state times prior to the read. In addition, the parity
error bit (RPE/RBB) may not be correct if it is read
within two state times after RI is set. Use the following code to replace ORB sp~mage, SP_STAT.
SP_READ: LDB TEMP, SP_STAT
ORB SP_lMAGE, TEMP
JBS TEMP,5,SP_READ; if TI is
15-20
set then read again,
JBS TEMP,6,SP_READ; if RI is
set then read again
ANDB SP_lMAGE,#7FH; clear
false RBB/RPE
ORB SP_lMAGE, TEMP; load
correct RBB/RPE
int:eL
8X9XBH
DATA SHEET REVISION HISTORY
This data sheet (270090-010) is valid for devices
marked with an "E" at the end of the topside tracking number. Data sheets are changed as new device
information becomes available. Verify with your local
Intel sales office that you have the latest version
before finalizing a design or ordering devices.
The difference between this data sheet (-010) and
the previous one (-009) is the IOl/iOH for float waveform testing changed from ± 15 mA to ± 8 mA (this
data sheet).
The following differences exist between (-009) data
sheet and (-008).
1. The Express (extended temperature and burn-in
options) were added to this data sheet. The
8X9XBH Express data sheet (270433-004) is
now obsolete.
2. Changes were made to the format of the data
sheet and the SFR descriptions were removed.
No specification changes made.
3. Added Reserved Location 201 CH errata.
The following differences exist between the -008
data sheet and the -007 data sheet.
1. The -007 data sheet was valid for devices
marked with a "D" at the end of the top side
tracking number.
2. The following errata were removed: RESET and
the Quasi-Bidirectional Ports, Software RESET
Timing, and Using T2CLK as the source for Timer2.
3. The HSI FIFO Operation errata definition was
changed to match change in the HSI FIFO Operation.
The following differences exist between the -007
data sheet and the -006 data sheet.
1. TeelH changed from Min = - 20 ns, Max =
+25 nsto Min = -30 ns, Max = +15 ns.
2. TXHQX changed from Min = 2 Tose - 50 ns to
.
Min = 2 Tose - 70 ns.
3. TOlOX changed from Min = 25 ns to Min =
30 ns.
4. An errata was added changing the recommendation for address 2019H from OFFH to 20H.
5. The power supply sequencing section has been
deleted. The information is in the Hardware Design Information.
6. The method of identifying the current change indicator was added to the differences between the
-005 and -004 data sheets:
7. A bug was not documented in the -004 data
sheet and was fixed before the -005 data sheet.
Information on the bug was added to the difference between the -005 and -004 data sheets.
Differences between -006 and -005 data sheets.
1. All EPROM programming mode information has
been deleted and moved to the Hardware Design
Information chapter.
2. Shrink-DIP package information has been added.
3. A new RESET timing specification has been added for clarity.
4. Software Reset pin timing information has been
added.
5. HSO IOl specifications have been improved so
that all HSO pins have the same drive capability.
6. Port 3 and Port 4 pin descriptions were clarified,
indicating the necessity of pullup if the pins are
used as ports.
7. HSI FIFO overflow description added.
Differences between the -005 and the -004 data
sheets.
1. The -005 data sheet corresponds to devices
marked with a "D" at the end of the topside
tracking number. The -004 data sheet corresponded to devices which are not marked with a
"D",
2. Much of the description of device functionality
has been deleted. All of this information is already in the MCS-96 Architectural Overview.
3. The AID converter specification for Differential
Non-linearity has been changed to be a minimum
of > -1 Isbs to a maximum of + 2 LSBs.
4. 8X9XBH errata section. The JBS and JBC on
Port 0 errata has been fixed on the latest device
stepping.
5. 8X9XBH errata section. The errata for the 48-pin
devices has been fixed on the latest device stepping.This errata caused the upper 8 bits on the
Address/Data bus to be latched when resetting
into an 8-bit external memory system.
6. 8X9XBH errata section. An errata existed which
caused the device to be held in RESET for extended periods of time with the internal RESET
pin pulled down internally. The condition occurred when the XTAL inputs were driven before
Vee was stable and within the data sheet specification. The condition was worse at cold. This errata was not documented in the -004 data sheet.
It has been fixed on the latest device stepping.
7. 8X9XBH errata section. Errata 3 and 4 have been
added to the errata list. These errata exist for all
steppings of the device.
15-21
II
intel~
8X9XBH
Differences between the -004 and the -003 data
sheets.
1. The bus control figures and bus timing diagrams
were modified to more accurately describe their
operation. In particular the 8-bit bus modes now
reflect the use of Write Strobe Mode.
2. Additional text was added to the Analog/Digital
description of the conversion process to clarify its
operation and usefulness.
3. Text was added to the interrupt description section to indicate the maximum transition speed of
the input signal relative to the CPU's state timing.
A figure was included to graphically demonstrate
the interrupt response timing.
4. The pin descriptions were modified to indicate
that Vpp must normally float in the application.
5. The input low voltage specification (VIL 1) was deleted and is covered by the VIL specification.
6. A suggested minimum configuration circuit was
added to the material.
7. The AID Converter Specifications for Differential
Non-Linearity has been corrected to be a maximum of + 2 LSB's.
8. The EPROM programming section figures were
corrected to indicate the correct interface to a
2764A-2. A reset circuit was added to these figures and the signal PVAL (Port 3.X and Port 4.X)
is now identified as the valid signal for program
verification in the Auto Programming Mode. Text
was added to this section to reference the requirement of using the Auto Configuration Byte
Programming Mode for 48-lead devices. Figure
22A was edited for corrections to the text, and
now indicates PVER (Port 2.0). The EPROM circuits were' corrected to show 6 MHz operation
for programming devices from internal microcode.
9. The protected memory section was edited to indicate that the CPU will enter a "JUMP ON
SELF" condition when ROM/EPROM dump
mode is complete.
10. An 8X9XBH ERRATA section was added.
11. This REVISION HISTORY was added.
15-22
8097JF/8397JF/8797JF
COMMERCIAL/EXPRESS
HMOS MICROCONTROLLER
8797JF: an 8097JF with 16 Kbytes of On-Chip EPROM
8397JF: an 8097JF with 16 Kbytes of On-Chip ROM
Byte Register File
• 232
256 Bytes XRAM for Code
• 10-Bit AID Converter with S/H
• Five 8-Bit I/O Ports
Interrupt Sources
• 20Pulse-Width
Output
• ROM/EPROMModulated
Lock
• Run-Time Programmable
EPROM (OTP)
ii
•
•
Extended Temperature Available
•
•
•
High Speed I/O Subsystem
Full Duplex Serial Port
Dedicated Baud Rate Generator
iii 6.25 J-Ls 16 x 16 Multiply
J-Ls
Divide
• 6.25
16-Bit Watchdog Timer
32116
•
•
•
Four 16-Bit Software Timers
Two 16-Bit Counter/Timers
• Extended Burn-In Available
The MCS-96 family of 16-bit microcontrollers consists of many members, all of which are designed for highspeed control functions. The MCS-96 family members produced using Intel's HMOS-III process are described
in this data sheet.
The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the
instruction set. With a 12 MHz input frequency the 8097 JF can do a 16-bit addition in 1.0 !-,-S and a 16 x 16-bit
multiply or 32/16 divide in 6.25 !-'-S. Instruction execution times average 1 to 2 !-'-S in typical applications.
Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external.events at preset times. The high-speed output unit can
simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once.
The on-chip AID converter includes a Sample and Hold, and converts up to 8 multiplexed analog input
channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 !-'-S.
Also provided on-chip are a serial port, a Watchdog Timer and a pulse-width modulated output signal.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the temperature range of - 40°C to + 85°C. Unless otherwise noted, the specifications are
the same for both options.
With the extended burn-in option, the burn-in is dynamic for a minimum time of 160 hours at 125°C with Vee
5.5V ± 0.5V, following the guidelines in MIL-STD-883, Method 1015.
=
See the Packaging information for extended temperature and extended burn-in designators.
15-23
July 1992
Order Number: 270795-006
II
infel~
8X97JF
FREQUENCY
PORT 0 PORT 1
HSI
PORT 2
ALl FUNCTIONS
HSO
270795-1
Figure 1. 8X97JF Block Diagram
OFTH . - - - - - - - - - - - - - . . , 255
POWER-DOWN
RA"
orOH
240
OEFH t - - - - - - - - - - - - - ; 2••
FffFH
INTERNAL
REGISTER FILE
(RA"J
EXTERNAL Io4EI.40RY
OR I/O
t-____________;6000H
5F'fF'H
1-_______...:.____-I2080H
1-____
____-I2072H 1-___....;,;;;;;;,;....;,;;;;,.;,.,;,;;;...:.___-I2070H ...;;,;;;,;;;~...:.
207FH
2071H
1-____________-t2030H- 206f'H
1-____________-t2020H - 202FH
t-_~~~~~~~~~--;201CH - 201FH
t-____-::-:-::~..;...-....;.--;201AH - 201BH
t-__~~~~~~~~--;201.H
t------::-:-::~:'"'""----;
2018H
t - - - - - - - - - - - - - ; 2012H - 2017H
I-____...:....;,....;,._____-I0"'H
1-____________-I0l00H
oorFH
______________
~
_ _ _ _ _ _ _ _ _ _ _ ___J0000H
270795-2
Figure 2. 8X97JF Memory Map
15-24
intet
8X97JF
PACKAGING
The 8097JF is available in 54-pin and 58-pin packages, with and without on-chip ROM or EPROM. The 8097JF
numbering system is shown in Figure 3. Figures 5-5 show the pinouts for the 54- and 58-pin packages. The
54-pin version is offered in a Shrink-DIP package while the 58-pin versions come in a Plastic leaded Chip
Carrier (PlCC).
8X97JF PACKAGING
Factory
Masked ROM
58-Pin
8397JF
I
I
User Programmable
CPU
64-Pin
68-Pin
8397JF
8097JF
I
I
OTP
54-Pin
68-Pin
8097JF
8797JF
I
I
64-Pin
8797JF
Figure 3. The 8097JF Family Nomenclature
Package Designators:
N = PLCC
U = Shrink DIP
Package Type
Prefix Designators:
T = Extended Temperature
L = Extended Temperature with 160 hrs Burn-in
°ja
°jC
68l PlCC
3rC/W
13°C/W
64l Shrink DIP
56°C/W
-
Figure 4. 8X97JF Thermal Characteristics
All thermal impedance data is approximate for static air conditions a 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
II
15-25
8X97JF
....
.,;
o.
"-
'"
..;
C
0
:::E
o.
"....
CD
.,;
o.
"N
..;
C
0
N
0
.,; .,;
o.
o.
"""CO
N
0
:::E
o.
.,;
o.
;
.,;
'"o.
"-
'"u
'" '" '" '" '" '"
:J:
U
:J:
U
:J:
U
:J:
U
:J:
U
:J:
'i
Z
::;
0
'" ....'><"
>0 >'"
li:'i
N
....
::>
><
'"-'
.,
-'
0
U
:J:
....
....
~
'"
'"
C
iii
II)
::>
'"
II)
W
-'
I~
ACH5/PMODE.1/PO.5
ADO/P3.0
ACH4/PMODE.O/PO.4
AD1/P3.1
ANGND
AD2/P3.2
VREF
AD3/P3.3
VpD
AD4/P3.4
8X97JF
68-PIN
PLOC
EXTINT /PRoG/P2.2
RESET
AD5/P3.5
AD6/P3.6
RXD/PALE/P2.1
AD7/P3.7
TXD/PVER/SALE/P2.0
AD8/P4.0
PLO
AD9/P4.1
TOP VIEW
LOOKING DOWN ON
COMPONElNT SIDE
OF PC BOARD
Pl.1
Pl.2
Pl.3
AD10/P4.2
AD11/P4.3
AD12/P4.4
Pl.4
AD13/P4.5
HSI.O/SID.O
AD14/P4.6
HSI.1/SIO.1
AD15/P4.7
HSI.2/HSO.4/SID.2
T2CLK/P2.3
27
28
29
30
31
32
'"
~
0
"!
"!
":
II)
ci
Vi
""'II)0
:J:
:J:
c::
o.
c::
33
34
35
36
37
38
'"0
'"
>'"
>"-
"-
....
CD
N
o.
II)
II)
:J:
:J:
N
0
N
o.
0
0II)
:J:
"-
39
40
41
"'o.N
"-
~
~
~
I~ I~
42
...N
o.
"....
~.
43
c>-
'"w
'"
"....
~
"l
Vi
:J:
:::E
~
o.
270795-3
Figure 5. S8-Pin PLCC Package
15-26
intel~
8X97JF
EA
vee
ACH3/PO.3
Vss
ACH1/PO.l
XTAL 1
ACHO/PO.O
XTAL2
ACH2/PO.2
ALE/ADV'
ACHS/PO.S/Pt.lODE.2
Ro
ACH7/PO.7/Pt.lODE.3
ADO/P3.0
ACHS/PO.S/Pt.lODE.l
AD1/P3.1
ACH4/PO.4/Pt.lODE.O
AD2/P3.2
ANGND
AD3/P3.3
VREf
AD4/P3.4
VpD
ADS/P3.S
EXTINT /P2.2(PRciG
ADS/P3.S
RESET
AD7/P3.7
RXD/P2.1/PALE
ADS/P4.0
TXD/P2.0/PVER/SALE
AD9/P4.1
PLO
AD10/P4.2
PLl
ADll/P4.3
PL2
AD12/P4.4
PL3
AD13/P4.S
PL4
AD14/P4.6
HSI.O/SID.O
AD15/P4.7
HSI.l/SID.l
T2CLK/P2.3
HSO.4/HSI.2/SID.2
READY
HSO.S/HSI.3/SID.3
T2RST/P2.4
BHE/WRH
HSO.O/PACT
iVR/WRL
HSO.l
PLS
PWt.l/P2.S/PDO/SPROG
Pl.6
P2.7
Pl.7
Vpp
P2.S
Vss
HSO.2
HSO.3
27079S-4
Figure 6. Shrink·DIP Package
15-27
8X97JF
PIN DESCRIPTIONS
Symbol
Vee
Name and Function
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are two VSS pins, both of which must be connected.
VpD
RAM standby supply voltage (5V). This voltage must be present during normal operation.
In a Power Down condition (Le., Vee drops to zero), if RESET is activated before Vee
drops below spec and VPD continues to be held within spec., the top 16 bytes in the
Register File will retain their contents.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the
analog portion of the AID converter and the logic used to read Port O. Must be connected
to use AID or Port o.
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp
Programming voltage for the EPROM devices. It should be + 12. 75V for programming and
will float to 5V otherwise. It should not be above Vee for ROM or CPU devices. This pin
must be left floating in the application circuit for EPROM devices.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT*
Output of the internal clock generator. The frequency of CLKOUT is
frequency. It has a 33% duty cycle.
RESET
Reset input to the chip. Input low for a minimum of 10 XTAL 1 cycles to reset the chip. The
subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-statetime RESET sequence.
SUSWIDTH'
Input for bus width selection. If CGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If SUSWIDTH is a 1, a 16-bit bus cycle occurs. If SUSWIDTH is a 0 an
8-bit cycle occurs. If GGR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left
unconnected, it will rise to Vee.
% the oscillator
NMI'
A positive transition causes a vector to external memory location OOOOH.
INST*
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFF to be directed to on-chip ROM/EPROM. EA
equal to a TTL-low causes accesses to these locations to be directed to off-chip memory.
EA = + 12.75V causes the device to enter the Programming Mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CGR. Soth pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory
reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCA. WR will go low
for every external write, while WRL will go low only for external writes where an even byte
is being written. WR/WRL is activated only during external memory writes.
SHE/WRH
Sus High Enable or Write High output to external memory, as selected by the GGA. SHE
will go low for external writes to the high b~f the data bus. WRH will go low for external
writes where an odd byte is being written. SHE/WRH is activated only during external
memory writes.
'Not available on Shrink-DIP Package
15-28
intel~
8X97JF
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
READY
Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge
of CLKOUT, the memory controller goes into a wait mode until the next positive transition
of CLKOUT occurs with READY high. When the external memory is not being used,
READY has no effect. Internal control of the number of wait states inserted into a bus
cycle held not ready is available in the CCR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
Port 1
8-bit quasi-bidirectional I/O port.
Port 2
8-bit multi-functional port. Six of its pins are shared with other functions in the 8096JF, the
remaining 2 are quasi-bidirectional. These pins are also used to input and output control
signals on EPROM devices in Programming Mode.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pull-ups. Ports 3 and 4 are also
used as a command, address and data path by EPROM devices operating in the
Programming Mode.
PMODE
Determines the EPROM programming mode.
PACT
A low signal in Auto Programming Mode indicates that programming is in progress. A high
signal indicates programming is complete.
PVAL
A low signal in Auto Programming Mode indicates that the device programmed correctly.
SALE
A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid
programming address/command information (output from master).
SPROG
A falling edge in Auto Programming Mode indicates that Ports 3 and 4 contain valid
programming data (output from master).
SID
Assigns a pin of Ports 3 and 4 to each slave to pass programming verification.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates that Ports 3 and 4 contain valid programming address/command
information (input to slave).
PROG
A falling edge in Slave Programming Mode indicates that Ports 3 and 4 contain valid
programming data (input to slave).
PVER
A high signal in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates the byte programmed correctly.
PVAL
A high signal in Slave Programming Mode indicates the device programmed correctly.
PD~
A low signal in Slave Programming Mode indicates that the PROG pulse was applied for
longer than allowed.
15-29
..
intel .
8X97JF
ELECTRICAL CHARACTERISTICS'
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias ................. - 55·C to + 125·C
Storage Temperature .......... - 60·C to + 150·C
Voltage from EA or Vpp
to VSS or ANGND ............ -0.3V to + 13.0V
Voltage from Any Other Pin to
Vss or ANGND ............. -0.3V to + 7.0V(1)
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The.
specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Average Output Current from Any Pin ....... 10 mA
Power Dissipation(2) ....................... 1.5W
NOTES:
1. This includes Vpp and EA on ROM and CPU only
devices.
2. Power dissipation is based on package heat
transfer characteristics, not device pow~r consumption.
OPERATING CONDITIONS
(All characteristics specified in this data sheet apply to these operating conditions unless otherwise noted.)
Parameter
Min
Max
Units
TA
Symbol
Ambient Temperature Under Bias Commercial Temp.
0
+70
·C
TA
Ambient Temperature Under Bias Extended Temp.
-40
+85
·C
Vcc
Digital Supply Voltage
4.50
'5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
Fosc
Oscillator Frequency
6.0
12
MHz
Vpo
Power-Down Supply Voltage
4.50
5.50
V
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
Ice
Vee Supply Current Commercial Temp.
300
mA
Ice
Vce Supply Current Extended Temp.
330
mA
Ice
Vce Supply Current (TA :?: 70·C)
245
mA
Ipo
Vpo Supply Current
1
mA
IREF
VREF Supply Current Commercial Temp.
8
mA
IREF
VREF Supply Current Extended Temp.
10
mA
VIL
Input Low Voltage'
-0.3
+0.8
V
VIL1
Input Low Voltage, RESET Commercial Temp.
-0.3
+0.8
V
VIL1
Input Low Voltage, RESET Extended Temp.
-0.3
+0.7
V
15-30
Test Conditions
All Outputs
Disconnected
Normal operation
and Power-Down
inteL
8X97JF
DC CHARACTERISTICS (Continued)
Symbol
Min
Max
VIH
Input High Voltage (Except RESET, NMI, XTAL 1)
Parameter
2.0
Vee + 0.5
Units Test Conditions
V
VIH1
Input High Voltage, RESET Rising
2.4
Vee + 0.5
V
VIH2
Input High Voltage, RESET Falling (Hysteresis)
2.1
VCC + 0.5
V
VIH3
Input High Voltage, NMI, XTAL 1 Commercial Temp.
2.2
Vcc + 0.5
V
VIH3
Input High Voltage, NMI, XTAL 1 Extended Temp.
2.3
Vcc + 0.5
V
lu
Input Leakage Current to each pin of
HSI, P3, P4, and to P2.1
±10
/l-A
IU1
DC Input Leakage Current to each pin of PO
+3
IIH
Input High Current to EA
100
IlL
Input Low Current to each pin of P1,
and to P2.6, P2.7 Commercial Temp.
IlL
Input Low Current to each pin of P1,
and to P2.6, P2.7 Extended Temp.
11L1
Input Low Current to RESET
IIL2
VIN
=
OtoVcc
/l-A
VIN
VIH
-125
/l-A
VIL
=
=
=
0 to VCC
/l-A
0.45V
-150
/l-A
VIL
=
0.45V
-2
mA
VIL
-50
/l-A
VIL
=
=
0.45V
Input Low Current P2.2, P2.3, P2.4,
READY, BUSWIDTH
VOL
Output Low Voltage on Quasi-Bidirectional
port pins and P3, P4 when used as ports
0.45
V
IOL = O.SmA
(Note 1)
VOL1
Output Low Voltage on Quasi-Bidirectional
port pins and P3, P4 when used as ports
0.75
V
IOL = 2.0 mA
(Notes 1, 2, 3)
VOL2
Output Low Voltage on Standard Output
pins, RESET and Bus/Control Pins
0.45
V
IOL = 2.0mA
(Notes 1, 2, 3)
VOH
Output High Voltage on Quasi-Bidirectional
pins
2.4
V
IOH = -20/l-A
(Note 1)
VOH1
Output High Voltage on Standard Output
pins and Bus/Control pins
2.4
V
IOH = -200/l-A
(Note 1)
IOH3
Output High Current on RESET
-50
Cs
Pin Capacitance (Any Pin to VSS)
-0.25
10
2.4V
0.45V
=
/l-A
VOH
pF
FTEST
2.4V
=
1.0 MHz
NOTES:
1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INST and ADO-15.
2. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V.
IOL on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOL on standard output pins and RESET: 8.0 mA
IOL on Bus/Control pins: 2.0 mA
3.During normal (non-transient) operation the following limits apply:
Total IOL on Port 1 must not exceed B.O mA.
Total IOL on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mA.
Total IOL on Port 3 must not exceed 10 niA.
TotaiiOL on P2.5, P2.7, and Port 4 must not exceed 20 mAo
15-31
8X97JF
AC CHARACTERISTICS
Test Conditions: Load Capacitance on Output Pins = 80 pF
TIMING REQUIREMENTS (The system must meet these specifications to work with the 8X97JF)
Symbol
Min
Parameter
TCLYX(3)
READY Hold after CLKOUT Edge
TLLYV
End of ALE! ADV to READY Valid
TLLYH
End of ALE! ADV to READY High
Max
0(1)
2 Tosc
TYLYH
Non-Ready Time
TAVDV(2)
Address Valid to Input Data Valid
TRLDV
RD Active to Input Data Valid
TRHDX
Data Hold after RD Inactive
0
TRHDZ
RD Inactive to Input Data Float
0
TAVGV(2,3)
Address Valid to BUSWIDTH Valid
TLLGX(3)
BUSWIDTH Hold after ALE! ADV Low
TLLGV(3)
ALE! ADV Low to BUSWIDTH Valid
TRLPV
Reset Low to Ports Valid
Tosc
+ 40
Units
ns
2 Tosc - 70
ns
4Tosc-8O
ns
1000
ns
5 TOSC - 120(4)
ns
3 Tosc - 100(4)
ns
ns
Tosc - 25
ns
2 Tosc - 125
ns
+ 40
ns
Tosc - 100
ns
10 TOSC
ns
NOTES:
1. If the 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has
occurred at 2 Tase + 55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. The term "Address Valid" applies to ADO-15, SHE and INST.
3. Pins not bonded out on 64-pin devices.
4. If wait states are used, add 3 Tase • N where N = number of wait states.
15-32
int:et
8X97JF
TIMING RESPONSES (8X97JF devices meet these specs.)
Symbol
Parameter
Min
Max
Units
FXTAL
Oscillator Frequency
6.0
12.0
MHz
Tosc
Oscillator Period
83
166
ns
TOHCH(3)
XTAL 1 Rising Edge to Clockout Rising Edge
0
120
ns
TCHCH(3)
CLKOUT Period
3 Tosd2)
3 Tosd2)
ns
TCHCL(3)
CLKOUT High Time
TCLLH(3)
CLKOUT Low to ALE High
TLLCH(3)
ALE/ ADV Low to CLKOUT High
Tosc - 25
TLHLL
ALE/ ADV High Time
Tosc - 30
TAVLL(5)
Address Setup to End of ALE/ ADV
Tosc - 50
TRLAZ(6)
RD or WR Low to Address Float Commercial Temp.
TRLAZ(6)
RD or WR Low to Address Float Extended Temp.
TLLRL
End of ALE/ ADV to RD or WR Active
Tosc - 35
- 30
Typ. = 0
Tosc
+
+
15
10
+ 45
+ 35(4)
Tosc
Tosc
ns
ns
ns
ns
ns
10
ns
25
ns
Tosc - 40
ns
TLLAX(6)
Address Hold after End of ALE/ ADV
Tosc - 40
ns
TWLWH
WR Pulse Width
3 Tosc - 35(1)
ns
TQVWH
Output Data Valid to End of WR/WRL/WRH
3 Tosc - 60(1)
ns
TWHQX
Output Data Hold after WR/WRLlWRH
Tosc - 50
ns
TWHLH
End of WR/WRL/WRH to ALE/ ADV High
Tosc - 75
ns
TRLRH
RD Pulse Width
3 Tosc - 30(1)
ns
TRHLH
End ofRD to ALE/ ADV High
Tosc - 45
TCLLL(3)
CLOCKOUT Low to ALE/ ADV Low
Tosc - 40
TRHBX(3)
RD High to INST, SHE, AD8-15 Inactive
Tosc - 25
TWHBX(3)
WR High to INST, SHE, AD8-15 Inactive
Tosc - 50
THLHH
WRL, WRH Low to WRL, WRH High
2 Tosc - 35
TLLHL
ALE/ ADV Low to WRL, WRH Low
2 Tosc - 30
TQVHL
Output Data Valid to WRL, WRH Low
Tosc - 60
ns
+ 35
Tosc + 30
Tosc + 100
2 Tosc + 40
2 Tosc + 55
Tosc
ns
ns
ns
ns
ns
III
ns
NOTES:
1. If more than one wait state is desired, add 3 Tosc for each additional wait state.
2. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3 Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTALt are iess than 10 ns.
.
3. CLKOUT, INST and BHE pins not bonded out on 64-lead package.
4. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
5. The term "Address Valid" applies to ADO-15, BHE and INST.
6. The term" Address" in this specification applies to ADO-7 for 8-bit cycles, and ADO-15 for 16-bit cycles.
15-33
infel .
8X97JF
WAVEFORM-SYSTEM BUS TIMINGS
XTALl
CLOCKOUT·
READY
... _------•'~..;.
BHE, INST·
AD8
VALID
'. _____________ _
-1S -J(~1L)----_....--IXTAL 1
clock driver
8X9X
Quartz Crystal or
Ceramic Resonator
no connect
270795-5
NOTE:
Keep oscillator components close to chip and use short, direct
traces to XTAL I, XTAL2 and Vss. When using crystals, CI ~
30 pF and C2 ~ 30 pF. When using ceramic resonators, consult
manufacturer for recommended capacitor values.
AC TESTING INPUT, OUTPUT WAVEFORMS
2.4
0.45
=x:.
2.0> TEST POINTS
O~
<
2.0
O~
XTAL2
270795-6
FLOAT WAVEFORMS
x:=
270795-23
AC Testing inputs are driven at 2.4V for a Logic "I" and OA5V for
a Logic "0". Timing measurements are made at 2.0V for a Logic
"I" and O.BV for a Logic "0".
270795-24
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs, and Begins to Float
when a 200 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH ~ ± B mAo
MINIMUM HARDWARE CONFIGURATION CIRCUITS
270795-25
270795-26
15-36
intel·
8X97JF
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: Load Capacitance = 80 pF
Symbol
Parameter
Min
TXLXL
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
Max
ns
8 Tose
TOVXH
Output Data Setup to Clock Rising Edge
TXHOX
Output Data Hold After Clock Rising Edge
TXHOV
Next Output Data Valid After Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold After Clock Rising Edge
TXHOZ
Last Clock Rising to Output Float
4 Tose - 50
Units
4 Tose + 50
ns
ns
3 Tose
ns
2 Tose - 70
2 Tose +50
ns
2 Tose +200
ns
0
ns
5 Tose
ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
RXD
---"'~--"'~-"I--"I--"r--"F----"~--"'~-"r~• ..------"~--"'~-"r~•
..------"
(IN)-J''--'
270795-21
' - - - - - - - - - - - - - - - '
15-37
II
intel~
8X97JF
AID CONVERTER SPECIFICATIONS
The absolute conversion accuracy is dependent on the accuracy and stability of VREF.
See the MCS-96 AID Converter Quick Reference for definitions of AID Converter terms.
Parameter
Typical'
Resolution
Minimum
Maximum
1024
10
1024
10
Levels
Bits
0
±4
LSBs
Absolute Error
Full Scale Error
Zero Offset Error
Units"
-0.5 ±0.5
LSBs
±0.5
LSBs
0
±4
LSBs
> -1
+2
LSBs
0
±1
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Notes
LSBs
Repeatability
iO.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBI"C
LSBrC
LSBrC
-60
,
dB
1,3
Feedthrough
-60
dB
1
Vee Power Supply Rejection
-60
dB
1
5K
n
4
0
3.0
/LA
3 Tase - 50
3 Tase + 50
ns
12 Tase + 50
ns
2
pF
Off Isolation
Input Series Resistance
1K
DC Input Leakage
Sample Delay
Sample Time
12 Tase - 50
Sampling CapaCitor
2
NOTES:
• These values are expected for most devices at 25°C.
•• An "LSB", as used here, is defined in the MCS-96 AID Converter Quick Reference and has a value of approximately
5mV.
1. DC to 100 KHz.
2. For starting the AID with an'HSa Command.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through intemal MUX, to sample capacitor.
15-38
inteL
8X97JF
OTP EPROM SPECIFICATIONS
EPROM PROGRAMMING OPERATING CONDITIONS
Parameter
Min
Max
Units
TA
Symbol
Ambient Temperature during Programming
20
30
C
Vee. VPD.
VREF(l)
Supply Voltages during Programming
4.5
5.5
V
VEA
Programming Mode Supply Voltage
9.0
13.0
V(2)
12.50
13.0
V(2)
0
0
V
Vpp
EPROM Programming Supply Voltage
Vss. ANGND(3)
Digital and Analog Ground
FOSC TEST POINTS
0.45
--A
0.8
<
FLOAT WAVEFORMS
>C
2.0
0.8.
270532-25
270532-26
For Timing Purposes a Port Pin is no Longer Floa1ing when a
200 mV change from Load Voltage Occurs, and Begins to Float
when a 200 mV change from the Loaded VOHIVOl Level occurs
IOl/IOH:> ± 8 rnA.
AC Testing inputs are driven at 2.4V for a Logic "'" and OA5V for
a Logic "a". Timing measurements are made at 2.0V for a Logic
"'" and 0.8V for a Logic "a".
II
MINIMUM HARDWARE CONFIGURATION CIRCUIT
Vpp
VpD
ANGND
48 LEAD
DEVICES
VREf
Eli
Vcc
Vss 1
Vss 2 XTAL 1
FLOAT
"'-+--'
XTAL2
270532-42
15-53
intet
8098/8398/8798
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: Load Capacitance = 80 pF
Symbol
Parameter
Min
Serial Port Clock Period
TXLXL
Max
Units
ns
8 Tase
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TOVXH
Output Data Setup to Clock Rising Edge
TXHOX
Output Data Hold After Clock Rising Edge
TXHOV
Next Output Data Valid After Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold After Clock Rising Edge
TXHOZ
Last Clock Rising to Output Float
4Tase-5O
4 Tase + 50
ns
ns
3 Tase
ns
2 Tase - 70
2 Tase +50
ns
2 Tase + 200
ns
0
ns
5 Tase
ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
RXD
(IN) _-''-.:=::,.'----1'-'--''.::I,_J''---''--','-------I'L..:::..J'-_I'------1'---_''~J'____'
270532-23
15-54
intet
8098/8398/8798
AID CONVERTER SPECIFICATIONS
The absolute conversion accuracy is dependent on the accuracy and stability of VREF.
See the MCS-96 AID Converter Quick Reference for definition of AID Converter Terms.
Parameter
Typlcal'(1)
Resolution
Minimum
Maximum
Units"
1024
10
1024
10
Levels
Bits
0
±4
LSBs
Absolute Error
Full Scale Error
Zero Offset Error
-0.5 ±0.5
LSBs
±0.5
LSBs
0
±4
LSBs
> -1
+2
LSBs
0
±1
LSBs
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBI"C
LSBI"C
LSBI"C
-60
Off Isolation
Notes
dB
1,3
Feedthrough
-60
dB
1
Vee Power Supply Rejection
-60
dB
1
4
1K
5K
n
0
3.0
/LA
Sample Delay
3 rose - 50
3 Tose + 50
ns
Sample Time
12 Tose - 50
12 Tose + 50
ns
Input Series Resistance
DC Input Leakage
Sampling Capacitor
2
pF
2
NOTES:
• These values are expected for most parts at 25"C.
•• An "LSB", as used here, is defined in the MCS-96 AID Converter Quick Reference and has a value of approximately
5 mV.
1. DC to 100 KHz.
2. For starting the AID with an HSO Command.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capaCitor.
15-55
II
8098/8398/8798
EPROM SPECIFICATIONS
EPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Min
Max
Units
TA
Ambient Temperature during Programming
Parameter
20
30
·C
Vee. VPD. VREF(1)
Supply Voltages during Programming
4.5
5.5
V
VEA
Programming Mode Supply Voltage
9.0
13.0
V(2)
Vpp
EPROM Programming Supply Voltage
12.50
13.0
V(2)
Vss. ANGND(3)
Digital and Analog Ground
0
0
V
Fose 1
Oscillator Frequency during Auto and Slave Programming
6.0
6.0
MHz
Fose 2
Oscillator Frequency during Run-Time Programming
6.0
12.0
MHz
NOTES:
1. Vee. VPD and VREF should nominally be at the same voltage during programming.
2. VEA and Vpp must never exceed the maximum voltage for any amount of time or the device may be damaged.
3. Vss and ANGND should nominally be at the same voltage (OV) during programming.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
TAVLL
ADDRESS/COMMAND Valid to PALE Low
0
Tose
TLLAX
ADDRESS/COMMAND Hold After PALE Low
80
Tose
TDVPL
Output Data Setup Before PROG Low
0
Tose
TPLDX
Data Hold After PROG Falling
80
Tose
TLLLH
PALE Pulse Width
180
TpLPH
PROG Pulse Width
250 Tose
TLHPL
PALE High to PROG Low
250
Tose
TPHLL
PROG High to Next PALE Low
600
Tose
TpHDX
Data Hold After PROG High
30
Tose
TpHVV
PROG High to PVER/PDO Valid
500
Tose
hLVH
PALE Low to PVER/PDO High
100
Tose
TpLDV
PROG Low to VERIFICATION/DUMP Data Valid
100
Tose
TSHLL
RESET High to First PALE Low (not shown)
2000
Tose
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Ipp
Parameter
Vpp Supply Current (Whenever Programming)
15-56
Tose
100 J.l-s +
144 Tose
intel·
8098/8398/8798
WAVEFORM-EPROM PROGRAMMING
PORTS 3,4
PALE--.......
PROG-----~-----~~~
PORTS 3,4
PVER
_ _ _J
VALID
PDO
_ _ _J
VALID
270532-37
Devices covered by this data sheet (see Revision
History) have the following errata.
fined as one or more pin transitions. "Entries" are
defined as the recording of one or more events.
A. The resolution is nine states instead of eight
states. Events occurring on the same pin more
frequently than once every nine states may be
lost.
B. A mismatch between the nine state HSI resolution and the eight state hardware timer causes
one time-tag value to be skipped every nine timer
counts. Events may receive a time-tag one count
later than expected.
C. If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register,
leaving the FIFO empty again. The next event
that occurs will be the first event loaded into the
empty FIFO. If the first two events into an empty
FIFO (not counting the Holding Register) occur
coincident with each other, both are recorded as
one entry with one time-tag. If the second event
occurs within nine states after the first, the
events will be entered separately with time-tags
at least one count apart. If the second event enters the FIFO coincident with the "skipped" timetag situation (see B above) the time-tags will be
at least two counts apart.
1. INDEXED, 3 OPERAND MULTIPLY
3. RESERVED LOCATION 2019H
The displacement portion of an indexed, three operand (byte or word) multiply may not be in the range
of 200H thru 17FFH inclusive. If you must use these
displacements, execute an indexed, two operand
multiply and a move if necessary.
The 1990 Architectural Overview recommended that
address 2019H be filled with hex value OFFH. The
recommendation is now 20H.
DIFFERENCES BETWEEN THE
8X9XBH AND 8X98
1. CCB.1 must be set to a logical 0 on the BX9B.
2. The following BX9XBH pins and corresponding
functions are not available on the BX9B:
BUSWIDTH
CLKOUT
INST
NMI
Port 0.0-0.3 (ACHO-3)
Port 1.0-1.7
Port 2.6
Port 2.7
P2.3 (T2CLK)
P2.4 (T2RST).
8X98 ERRATA
4. RESERVED LOCATION 201CH
2. HSI FIFO OPERATION
The High Speed Input (HSI) has three deviations
from the specifications. Note that "events" are de-
Reading reserved location 201CH, either internally
or externally, will return "201C" as data.
15-57
II
8098/8398/8798
The followirigdifferences 'exist between the -005
data sheet and the -004 data sheet.
1. Most of the functional description has been removed. This information is in the MCS-96 Architectural Overview.
2. Information on programming the Chip Configuration Register has been added.
5. SERIAL PORT SECTION
Serial Port Flags-Reading SP_STAT may not
clear the TI or RI flag if that flag was set within two
state times prior to the read. In addition, the parity
error bit (RPE/RB8) may not be correct if it is read
withiri two state times after RI is set. Use the following code to replace ORB sp_image, SP_STAT.
SP _READ: LDB TEMP, SP _STAT
ORB SP_IMAGE, TEMP
JBS TEMP, 5, SP_READ; if
TI is set then r~ad again
JBS TEMP, 6; SP_READ: if
RI is set then read again
ANDB SP_IMAGE,#7FH; clear
false RB8/RPE
ORB SP_IMAGE, TEMP; load
correct RB8/RPE
3. TXHQX changed from Min = 2 Tose - 50 ns to
Min = 2 Tose - 70 ns.
4. TOLOX changed from Min = 25 ns to Min =
30 ns.
5. Added AC timings specifications to clarify Write
Strobe Mode specifications.
\
6. The differences between the 8X9XBH and the
8X98 have been added.
7. An errata has been added changing the recommendation for address 2019H from OFFH to 20H.
DATA SHEET REVISION HISTORY
This data sheet (270532-008) is valid for devices
with an "E" at the end of the topside tracking number, Oata sheets are changed as new device information becomes available. Verify with your local
Intel sales office that you have the latest version
before finalizing a design or orderirig devices.
The difference between -007 and -008 is the IOl/loH
for the float waveform testing changed from
± 15 mA to ± 8 mAo
The following differences exist between <-007) data
sheet and the (-006).
1. The Express (extended temperature and burn-in
options) were added to this data sheet. The 8X98
Express data sheet (270914-002) is now obsolete.
2. Changes were made to the format of the data
sheet and the SFR descriptions were removed.
No specification changes were made.
3. Added Reserved Location 201 CH errata.
The following differences exist between the -006
data sheet and the -005 data sheet.
1. The -005 data sheet was valid for devices
marked with a "0" at the end of the top side
tracking number.
2. The following errata were removed: RESET and
the Quasi-Bidirectional Ports, Software RESET
Timing, and Using T2CLK as the source for Timer2.
3. The HSI FIFO Operation errata definition was
changed to match a change in the HSI FIFO operation.
Oifferences between the -004 and -003 data sheets.
1. All EPROM programming mode information has
been moved to the Hardware Oesign Information
Chapter.
2. CCB RESET FETCH and JBS/JBC on Port 0 anamolies have been corrected on the current steppings of the 8X98.
3. New information regarding T2CLK and new information about RESET of the Quasi Ports have
been added to the Errata section.
4. The Extended Reset errata has been eliminated
on the silicon and in the data sheet.
5. HSI Mode register is undefined until the user
code initializes this register.
6. Minimum ONL us now> -1 LSB.
7. HSI FIFO overflow description added.
Oifferences between the -002 and -003 data sheets.
1. All 8798 EPROM information has been added as
a complete section after the Analog Section.
2. The chip configuration byte values now indicate
the use of WRITE STROBE with 8-bit systems.
Write Strobe design text was added to the explanation.
3. The interrupt information now includes a worst
case timing diagram.
4. The EPROM 8798 was added as necessary
throughout the text.
5. NMI pin information was deleted.
6. Reset Register Status was added and the state
of the HSO pins after RESET.
7. A diagram of the Interrupt Pending Register is
now included.
15-58
8098/8398/8798
8. A diagram of the PSW Register was added.
9. VIL1 was deleted. This was a RESET pin characteristic that has been improved to match the other characteristics.
15-59
10. The Differential Non-Linearity specification in
the AID converter specifications was corrected
to read + 2 LSBs.
11. Power On Reset - New information on Extended Reset Time was added to the Errata Section.
8XC 196KB Data Sheets
16
•
intel®
80C196KB10/83C196KB10/80C196KB12/83C196KB12
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
83C196KB - 8 Kbytes of Factory Mask-Programmed ROM
80C196KB - ROM less
Duplex Serial Port
• Full
High Speed I/O Subsystem
• 16-Bit Timer
16-Bit Up/Down Counter with Capture
• Pulse-Width-Modulated
Output
• Four 16-Bit Software Timers
• 10-Bit A/D Converter with Sample/Hold
• HOLD/HLDA
• 10 MHz and 12BusMHzProtocol
Available
• Extended Burn-In Available
•
of On-Chip ROM Available
• 8232Kbytes
Byte Register File
• Register-to-Register Architecture
• 28 Interrupt Sources/16 Vectors
• 2.3 p.s 16 x 16 Multiply (12 MHz)
• 4.0 p.s 32/16 Divide (12 MHz)
• Powerdown and Idle Modes
• Five 8-Bit I/O Ports
• 16-Bit Watchdog Timer
• Dynamically
Configurable 8-Bit or
• 16-Bit Buswidth
• Extended Temperature Available
II
The 80C196KB 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller family.
The 80C196KB is compatible with the 8096BH and uses a true superset of the 8096BH instructions. Intel's
CHMOS process provides a high performance processor along with low power consumption. To further reduce
power requirements, the processor can be placed into Idle or Powerdown Mode.
The 80C196KB has a 232-byte register file and an optional 8 Kbyte of on-chip ROM. Bit, byte, word and some
32-bit operations are available on the 80C196KB. With a 12 MHz oscillator a 16-bit addition takes 0.66 J-ts, and
the instruction times average 0.5 J-ts to 1.5 J-ts in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter. Also provided on-chip are an
AID converter, serial port, watchdog timer and a pulse-width-modulated output signal.
The 80C196KB10 and 83C196KB10 have a maximum guaranteed frequency of 10 MHz. The 80C196KB12
and 83C196KB12 have a maximum guaranteed frequency of 12 MHz. All references to the 80C196KB also
refer to the 80C196KB10, 83C196KB10, 80C196KB12 and 83C196KB12 unless otherwise noted.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the temperature range of -40°C to + 85°C. With the extended burn-in option, the burn-in is
dynamic for a minimum time of 160 hours at 125°C with Vcc = 5.5V ±0.5V, following the guidelines in MILSTD-883, Method 1015. The specifications which are different for the extended temperature and extended
burn-in devices are listed in this data sheet. Otherwise, the commercial specifications apply for both.
MCS@-96 is a registered trademark of Intel Corporation.
16-1
November 1991
Order Number: 270918-002
III
BOC196KB10/83C196KB10/80C196KB12/83C196KB12
YREF
ANGND
r-~--~
:p-------------------CrPU_ _ _""I
I
I
i-r--""T..I :
I
I
I
I
I
CONTROL
SIGNALS
--........
} ~~~:
BUS
~
PORT 4
1+---1--
A/D
HSO
270918-1
Figure 1. 80C196KB Block Diagram
OFFFFH
EXTERNAL MEMORY OR 1/0
40DOH
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
20BOH
RESERVED
2040H
UPPER 8 INTERRUPT VECTORS
2030H
ROMIEPROM SECURITY KEY
2D20H
RESERVED
2019H
CHIP CONFIGURATION BYTE
2018H
RESERVED
2014H
LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3 AND PORT 4
1FFEH
EXTERNAL MEMORY OR 1/0
D100H
INTERNAL DATA MEMORY· REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
Figure 2. Memory Map
16·2
DDOOH
80C196KB10/83C196KB10/80C196KB12/83C196KB12
PACKAGING
,
The 80C196KB is available in a 68-pin PLCC package, an 80-pin QFP package and a 68-pin PGA package.
Contact your local sales office to determine the exact ordering code for the part desired.
Package Designators: N
=
68-pin PLCC, S
=
80-pin QFP and A
=
68-pin PGA.
Prefix Designators: T = extended temperature, L = extended temperature with extended burn-in.
Thermal Characteristics
Package
Type
PGA
PLCC
QFP
°ja
°jc
28°C/W
35°C/W
85°C/W
3SC/W
12°C/W
-
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
PGA
Plee
Description
PGA
Plee
Description
PGA
Plee
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
ACH7/PO.7
ACH6/PO.6
ACH2/PO.2
ACHO/PO.O
ACH1/PO.1
ACH3/PO.3
NMI
EA
Vee
Vss
XTAL1
XTAL2
CLKOUT
SUSWIDTH
INST
ALE/ADV
RD
ADO/P3.0
AD1/P3.1
AD2/P3.2
AD3/P3.3
AD4/P3.4
AD5/P3.5
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
AD6/P3.6
AD7/P3.7
AD8/P4.0
AD9/P4.1
AD10/P4.2
AD11/P4.3
AD12/P4.4
AD13/P4.5
AD14/P4.6
AD15/P4.7
T2CLK/P2.3
READY
T2RST/P2.4
SHE/WRH
WR/WRL
PWM/P2.5
P2. 7IT2CAPTURE
Vpp
Vss
HSO.3/SID3
HSO.2/SID2
P2.6/T2UP-DN
P1.7/HOLD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
P1.6/HLDA
P1.5/BREQ
HSO.1
HSO.O
HSO.5/HSL3
HSO.4/HSL2
HSL1
HSLO
P1.4
P1.3
P1.2
P1.1
P1.0
TXD/P2.0
RXD/P2.1
RESET
EXTINT/P2.2
VSS(l)
VREF
ANGND
ACH4/PO.4
ACH5/PO.5.
NOTE:
1. This pin was formerly the Clock Detect Enable pin. This function is not guaranteed to work. This pin must be directly
connected to V55.
16-3
•
intel~
80C196KB10/83C196KB10/80C196KB12/83C196KB12
~OO[gIbO~OOO~OOW
Pins Facing Down
17 15 13 1 1
9
7
5
3
1
18 19 16 14 12 10
8
6
4
2
20 21
22 23
24 25
67 66
A80C196KB
68-PIN
GRID ARRAY
30 31
32 33
65 64
63 62
61 60
26 27
28 29
68
TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
59 58
57 56
55 54
34 36 38 40 42 44 46 48 50 53 52
35 37 39 41 43 45 47 49 51
270918-2
Figure 3. 58-Pin Package (Pin Grid Array-Top View)
16-4
BOC196KB10/B3C196KB10/BOC196KB12/B3C196KB12
"":
CD
N
0
I"-
:J:
U
0
II..
II..
II..
~
c c c
, , "
0
II..
CD
N
:J:
U
:J:
U
0
:J:
U
~
, ,...,
II..
:J:
0
II..
l-
~
:J:
U
N
~
u
:J:
..J
..J
« «
1111- IIII
2
« « « « « « z I~ ;}l > x 'x
u
~
0
~
..J
U
I-
c
ri
III
I-
III
:::l
III
~
~!ru[gI6DIMlDOO~!ruW
I~
,
....
« I~
..J
ACH5/PO.5
ADO/P3.0
ACH4/PO.4
AD1/P3.1
ANGND
AD2/P3.2
VREF
AD3/P3.3
N80C196KB
68-PIN
PLCC
VSS
EXTINT/P2.2
RESET
AD4/P3.4
AD5/P3.5
AD6/P3.6
RXD/P2.1
AD7/P3.7
TXD/P2.0
AD8/P4.0
PLO
AD9/P4.1
Plol
AD10/P4.2
TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
P(2
P1.3
P1.4
HSI.O
ADll/P4.3
AD12/P4.4
AD13/P4.5
AD14/P4.6
HSI.l
AD15/P4.7
HSI.2/HSO.4
T2CLK/P2.3
32 33 34 35 36 37 38 39 40 41
0
ci III It! "": zc
ci ci III
II..
II..
II..
I
10
,
III
:J:
~
III
:J:
:J:
~
~
I~I~I~ ~
:J:
CD
iii
....
0::
III
C
..J
:J:
..J
..., III 11.. .... 10
0::
ci III >11.. :::l
ci
N
III III >
N
:J:
:J:
III..
«
U
N
0
I:J:"
,
N
l-
N
-t
,II..I~
lI:
~
~ >c
~ N «
....
10:: ,....
I~
0:: ~
I-
II..
0::
~!Q
N
I-
l"-
II..
N
II..
270918-3
Figure 4. 68-Pln Package (PLCC-Top View)
16-5
•
intel .
80C196KB10/83C196KB10/80C196KB12/83C196KB12
IPJOOI§11.0IMlOOO£OOW
T2CLK/P2.3
AD1/P3.1
VSS
REAOY
T2RST/P2.4
BHE/WRH
WR/WRL
PWW/P2.S
P2.7/T2CAPTURE
SSOC196KB
Vpp
SO-PIN QFP
Vss
Vss
HSO.3
vee
TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
ACH3/PO.3
P2.6/T2UP-DN
ACHI/PO.1
ACHO/PO.O
ACH2/PO.2
ACH6/PO.6
ACH7/PO.7
N.C.
ACHS/PO.S
41
ACH4/PO.4
N
N
0-
-;::.
Z
;:::
~
~
......
~
'"
";
0
N
0-
...N
1>1i
1!:
~ .......
Q
;. ii:"!
"! "! ~ "!
iii
ii: ii: ii: ii: iii
%
%
270918-5
Figure 5. SO-Pin Quad Flat Pack (QFP)
16-6
intel"
80C196KB10/83C196KB10/80C196KB12/83C196KB12
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are two Vss pins, both of which must be connected.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp
Timing pin for the return from powerdown circuit. Connect this pin with a 1 iJoF capacitor to
Vss. If this function is not used, connect to Vee. This pin is the programming voltage on the
EPROM device.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency. It has a 50% duty cycle.
RESET
Reset input and open-drain output. Input low for at least 4 state times to reset the chip. The
subsequent low-to-high transition re- synchronizes CLKOUT and commences a 10-state-time
sequence in which the PSW is cleared, a byte read from 2018H loads eCR, and a jump to
location 2080H is executed. Input high for normal operation. RESET has an internal puliup.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST is
valid throughout the bus cycle. INST is activated only during external memory accesses and
output low for a data fetch.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROWEPROM. EA ~ual to a
TTL-low causes accesses to these locations to be directed to off-chip memory. EA must be
tied low for the 80C196KB ROM less device.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCA. BHE = 0
selects the bank of memory that is connected to the high byte of the data bus. AO = O'selects
the bank of memory that is connected to the low byte of the data bus. Thus accesses to a
16-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only
(AO = 1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the
pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only
during 16-bit external memory write cycle~.
16-7
II
inteJ~
80C196KB10/83C196KB10/80C196KB12/83C196KB12
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is
low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until. the
next positive transition in CLKOUT occurs with READY high. When the external memory is
not being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle held not ready is available through configuration of CCR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSLO, HSL1, HSL2 and HSL3.
Two of them (HSL2 and HSL3) are shared with the HSO Unit. The HSI pins are also used as
the SID in Slave Programmfng Mode on. the EPROM device.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on the
EPROM device.
Port 1
8-bit quasi-bidirectional 110 port.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KB.
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Available as 1/0 only on the
ROM and EPROM devices.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSR. 7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREO
Bus Request output activated when the bus controller has a pending external memory cycle.
Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. The TxD function is
enabled by setting IOC1 5. In mode 0 the pin is used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin functions as input or output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt. EX11NT is selected as the
external interrupt source by setting IOC1.1 high.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.
PWM
Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM is
determined by the value loaded into the PWM-CONTROL register (17H).
I
T2UP-DN
The T2UP-DN pin controls the direction of Timer2 as an up or down counter. The Timer2 upl
down function is enabled by setting 1002.1.
T2CAP
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15).
16-8
inteL
80C196KB10/83C196KB10/80C196KB12/83C196KB12
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature
Under Bias ................. - 55°C to + 125°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature .......... -65°C to + 150°C
Voltage On Any Pin to VSS ........ -0.5V to + 7.0V
Power Dissipation(1) ....................... 1.5W
NOTE:
1. Power Dissipation is based on package heat transfer,
not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
Description
Min
Max
Units
TA
Ambient Temperature Under Bias
0
+70
°C
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
Fose
Oscillator Frequency 12 MHz
3.5
12
MHz
Fose
Oscillator Frequency 10 MHz
3.5
10
MHz
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Description
Min
Typ(7)
Max
-0.5
Units
VIL
Input Low Voltage
VIH
Input High Voltage (Note 1)
0.8
V
0.2 Vee + 0.9
Vee + 0.5
V
VIH1
Input High Voltage on XTAL 1
0.7 Vee
VIH2
Input High Voltage on RESET
Vee + 0.5
V
2.6
Vee + 0.5
V
VOL
Output Low Voltage
0.3
0.45
1.5
V
V
V
VOH
Output High Voltage
(Standard Outputs)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
NOTES:
1. All pins except RESET and XTAL1.
2. Holding these pins below VIH in Reset may cause the part to enter test modes.
16-9
Test Conditions
= 200 p.A
= 3.2mA
= 7 mA
IOH = - 200 p.A
IOH = -3.2 mA
IOH = -7 mA
IOH = -10 p.A
IOH = -30 p.A
IOH = -60 p.A
IOL
IOL
IOL
..
int'et
80C196KB10/83C196KB10/80C196KB12/83C196KB12
DC CHARACTERISTICS
Symbol
(Continued)
Min Typ(7)
Description
Max
Units
III
Input Leakage Current (Std. Inputs)
±10
/LA
ILI1
Input Leakage Current (Port 0)
+3
/LA
0< VIN < VREF
ITl
1 to 0 Transition Current (QBD Pins)
-650
/LA
VIN
III
Logical 0 Input Current (QBD Pins)
-50
/LA
VIN
Illl
Logic~ I~t Current in Reset (Note 2)
(ALE, RD, WR, BHE, INST, P2.0)
-1.2
rnA
VIN '7' 0.45 V
40
55
rnA
5
rnA
300
Test Conditions
o<
VIN < Vcc - 0.3V
=
=
Hyst
Hysteresis on RESET Pin
Icc
Active Mode Current in Reset
IREF
AID Converter Reference Current
2
IIDlE
Idle Mode Current
10
22
.rnA
ICCl
Active Mode Current
15
22
rnA
XTAL1
Vcc
IpD
Powerdown Mode Current
RRST
Reset Pull up Resistor
Cs
Pin Capacitance (Any Pin to VSS)
2.0V
0.45V
rnV
5
6K
50
/LA
50K
n
10
pF
XTAL1 = 12 MHz
Vcc = Vpp = VREF
=
FTEST
=
5.5V
=
5.5V
3.5 MHz
Vpp
=
=
=
VREF
1.0 MHz
NOTES:
(Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs. include ADO-15, RD, WR, ALE, §RE, INST, HSO pins, PWM/P2.5, ClKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VQ!:L specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, 12ClK/P2.3 and
T2RST IP2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOl on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOHon Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is ±3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOl: 29 mA
IOH is self limiting
HSO, P2.0, RXD, RESET IOl: 29 mA
IOH: 26 mA
P2.5, P2. 7, WR, BHE
IOl: 13 mA
IOH: 11 mA
ADO-AD15
IOl: 52 mA
IOH: 52 mA
RD, ALE, INST-ClKOUT IOl: 13 mA
IOH: 13 mA
7. Typicals are based on a limited .number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.
60r---~r---~-----'
40 I------f-------:Jr"--...,..j Icc TYPICAL (7)
Icc 30 I-----f---F----:J-""---j
rnA
10 I------:t..-'<=-......,--:=..,..j IIDLE TYPICAL
Icc Max = 3.88 x FREQ + 8.43
IIDlE Max = 1.65 x FREQ + 2.2
4t.4Hz
8t.4Hz
12t.4Hz
.REQ
Figure 6. Icc and IIDLE vs Frequency
16-10
270918-24
int'eL
80C196KB10/83C196KB10/80C196KB12/83C196KB12
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, Fosc = 10/12 MHz
The system must meet these specifications to work with the 80C196KB:
Symbol
TAVYV
hLYV
Max
Units
Address Valid to READY Setup
80C196KB10/83C196KB10
80C196KB12/83C196KB12
2 Tosc - 90
2 Tosc - 85
ns
ns
ALE Low to READY Setup
80C196KB10/83C196KB10
80C196KB12/83C196KB12
Tosc - 80
Tosc - 72
ns
ns
Description
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TLLYX
READY Hold after ALE Low
TAVGV
Address Valid to Buswidth Setup
hLGV
ALE Low to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
80C196KB10/83C196KB10
80C196KB12/83C196KB12
Min
No upper limit
Notes
ns
ns
(Note 1)
2 Tosc - 40
ns
(Note 1)
2 Tosc - 85
ns
Tosc - 70
ns
0
Tosc - 30
Tosc - 15
0
ns
3 Tosc - 70
3 Tosc - 67
ns
ns
(Note 2)
RD Active to Input Data Valid
80C196KB10/83C196KB10
80C196KB12/83C196KB12
Tosc - 30
Tosc - 23
ns
ns
(Note 2)
TCLDV
CLKOUT Low to Input Data Valid
Tosc - 50
ns
TRHDZ
End of RD to Input Data Float
Tosc - 20
ns
TRXDX
Data Hold after RD Inactive
TRLDV
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2 Tasc x n, where n = number of wait states.
III
16-11
80C196KB10/83C196KB10/80C196KB12/83C196KB12
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, Fosc = 10/12 MHz
The 80C196KB will meet these specifications:
Symbol
FXTAL
Tosc
Min
Max
Units
Notes
Frequency on XTALl
80C196KB10/83C196KB10
80C196KB12/83C196KB12
Description
3.5
3.5
10
12
MHz
MHz
(Note 2)
(Note 2)
I1FXTAL
80C196KB10/83C196KB10
80C196KB12/83C196KB12
100
83
286
286
ns
ns
40
110
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
Tosc - 10
Tosc+ 10
ns
TCLLH
CLKOUT Falling Edge to ALE Rising
-5
15
ns
lLLCH
ALE Falling Edge to CLKOUT Rising
-15
15
ns
lLHLH
ALE Cycle Time
lLHLL
ALE High Period
Tosc - 10
TAVLL
Address Setup to ALE Falling Edge
Tosc - 20
ns
4 Tosc
Tosc+ 10
TLLAX
Address Hold after ALE Falling Edge
Tosc - 40
ns
ALE Falling Edge to RD Falling Edge
Tosc - 40
ns
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
TOVWH
Data Stable to WR Rising Edge
80C196KB10/83C196KB10
80C196KB12/83C196KB12
(Note 5)
ns
TLLRL
TRLAZ
(Note 3)
ns
2 Tosc
5
30
ns
Tosc - 5
Tosc + 25
ns
(Note 5)
Tosc
Tosc + 25
ns
(Note 4)
10
ns
25
ns
ns
Tosc - 10
0
ns
ns
Tosc - 30
Tosc - 23
-10
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
Tosc - 30
10
ns
Tosc + 5
ns
TWHOX
Data Hold after WR Rising Edge
Tosc - 10
TWHLH
WR Rising Edge to ALE Rising Edge
Tosc - 10
TWHBX
BHE, INST Hold after WR Rising Edge
Tosc - 10
ns
TRHBX
BHE, INST Hold after RD Rising Edge
Tosc - 10
ns
TWHAX
AD8-15 Hold after WR Rising Edge
Tosc - 50
ns
TRHAX
AD8-15 Hold after RD Rising Edge
Tosc - 25
ns
(Note 5)
(Note 5)
ns
Tosc + 15
ns
(Note 4)
NOTES:
Tosc = 83.3 ns at 12 MHz; Tosc = 100 ns at 10 MHz.
1. Customers whose applications require an 83C196KB to meet the 80C196KB specifications listed above should contact an
Intel Field Sales Representative.
2. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
3. Typical specification, not guaranteed.
4. Assuming back-to-back bus cycles.
5. When using wait states, add 2 Tosc x n, Where n = number of wait states.
16-12
intel .
BOC196KB 1O/B3C 196KB 1O/BOC196KB 12/B3C 196KB 12
1P>!ru~I!:.OrMIOOO~!ruW
System Bus Timings
XTALI
CLKOUT
ALE
BUS
WRITE
BUS
-<
I
_
BHE,INST
ADDR~SOUT>_~.
ADDRESS
VALID
I
ADO-IS
ADDR~S
OUT
270918-25
•
16-13
int'et
80C196KB10/83C196KB10/80C196KB12/83C196KB12
~OO[g[bO~OOO~OO't1
READY Timings (One Wait State)
XTALI
CLKOUT
ALE
READY
TRLRH + 2 Tose
---..,~_ _ _ _ _ _ __
READ
BUS
TRLDV + 2 Tose ~
......- - - - - - - . . . . : . . . TAVDV + 2Tose - - - - - - 1
J--~~
ADDRESS OUT
{ DATA ) ) ) ) ) ) ) ) - - - ~l--.I.I.I.1.UJ
-<~------')
~.
WRiTE
i
BUS
TWLWH + 2 Tose
'.
TQVWH + 2 Tose
ADDRESS OUT
DATA OUT
d
ADDRESS
270918-26
Buswidth Timings
XTAL 1
270918-27
16-14
infel·
80C196KB10/83C196KB10/80C196KB12/83C196KB12
HOLD/HLDA TIMINGS
Description
Symbol
Min
Max
Units
Notes
ns
1
THVCH
HOLD Setup
TCLHAL
CLKOUT Low to HLDA Low
-15
15
ns
TCLBRL
CLKOUT Low to BREQ Low
-15
15
ns
THALAZ
HLDA Low to Address Float
THALBZ
HLDA Low to BHE, INST, RD, WR Float
TCLHAH
CLKOUT Low to HLDA High
-15
15
ns
TCLBRH
CLKOUT Low to BREQ High
-15
15
ns
THAHAX
HLDA High to Address No Longer Float
-5
ns
THAHBV
HLDA High to BHE, INST, RD, WR Valid
-20
ns
CLKOUT Low to ALE High
-5
TCLLH
85
20
ns
ns
15
ns
NOTE:
1. To guarantee recognition at next clock.
CLKOUT"'\. r \ . r~
THV:=i1-
BUS - { ' - -_ _ __
BHE,INST
Rii.WR
ALE
\
\
\
\
,,
~r-!____. .II~!---_T_cL_LHh---_-270918-28
16-15
II
inial.,
80C196KB10/83C196KB10/80C196KB12/83C196KB12
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TxLX~
Oscillator Frequency
80C196KB10
80C196KB12
3.5
3.5
10.0
12.0
MHz
MHz
Oscillator Frequency
80C196KB10
80C196KB12
100
83
286
,286
ns
ns
TXHXX
High Time
32
ns
TXLXX
Low Time
32
ns
TXLXL
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270916-29
An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
vee
C1
Vss
·11~1-~r----1'XTAL1
EXTERNAL
CLOCK INPUT
BOC196KB
_I 4.7~·
XTALt
clock driver
XTAL2
no connoct-
80C196KB
XTAL2
Quartz Crystal or
Ceramic Resonator
270916-37
270916-36
• Required if TTL driver used.
Not needed if CMOS driver is used.
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and Vss. When
using crystals, C1 = C2 ::::: 20 pF. When using ceramic
resonators, consult manufacturer for recommended capacitor values.
16-16
infel .
80C196KB10/83C196KB10/80C196KB12/83C196KB12
AC TESTING INPUT, OUTPUT WAVEFORMS
2 . 4 - y 2.0> TEST POINTS
0.45
--.1\ 0.8
<
2.0
FLOAT WAVEFORMS
V--
0.8-A--
270918-30
AC Testing inputs are driven at 2.4V for a Logic "1'" and 0.45V for
a Logic "0'" Timing measurements are made at 2.0V for a Logic
"1'" and 0.8V for a Logic "0".
270918-31
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the Loaded VOHIVOL Level occurs
IOL/loH ~ ± 15 mAo
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
. - High
A
- Address
HA
- HLDA
L
- Low
B
- BHE
L
- ALE/ADV
V
- Valid
BR
- BREQ
Q
- DATA OUT
X
- No Longer Valid
C
- CLKOUT
R
Z
- Floating
D
- DATA IN
W
- RD
- WR/WRH/WRL
G
- Buswidth
X
- XTAL1
H
- HOLD
Y
- READY
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-5HIFT REGISTER MODE
Symbol
Parameter
Min
TXLXL
Serial Port Clock Period (BRR ~ 8002H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR ~ 8002H)
TXLXL
Serial Port Clock Period (BRR = 8001 H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)
2 Tose - 50
TOVXH
Output Data Setup to Clock Rising Edge
2Tose -50
TXHOX
Output Data Hold after Clock Rising Edge
2 Tose -50
TXHOV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHOX
Input Data Hold after Clock Rising Edge
TXHOZ
Last Clock Rising to Output Float
Max
ns
6 Tose
4 Tose -50
4 Tose +50
ns
ns
4 Tose
2 Tose +50
ns
ns
ns
2 Tose +50
ns
Tose +50
ns
0
ns
1 Tose
16-17
Units
ns
..
intel .
80C196KB10/83C196KB10/80C196KB12/83C196KB12
[P)OO~I6D~DOO£OOW
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REgiSTER MODE
r-- --I
---l...r ---l...r ---l...r ---l...r ---l...r ---U- ---U- ---U- .
-! II
'-1
II
TXLXL
TXD
TQyXH
RXD
TXLXH-I
TXHQY
-I
TXHQZ-l
(OUT)
RXD
(IN)
270918-35
16-18
int:eL
80C196KB10/83C196KB10/80C196KB12183C196KB12
A TO D CHARACTERISTICS
There are two modes of AID operation: with or without clock prescaler. The speed of the AID converter
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 8 MHz. The conversion times with the prescaler turned on or off is
shown in the table below.
The converter is ratiometric, so the absolute accuracy is directly dependent on the accuracy and stability
of VREF. VREF must be close to Vee since it supplies
both the resistor ladder and the digital section of the
converter.
See the MCS-96 AID Quick Reference for definition
of AID terms.
Conversion Time
Clock Prescaler On
IOC2.4 = 0
Clock Prescaler Off
IOC2.4 = 1
158 States
26.33 f.Ls @ 12 MHz
22.75 f.Ls
91 States
@
8 MHz
AID CONVERTER SPECIFICATIONS
Parameter
Typical(1)
Minimum
Maximum
Units'
512
9
1024
10
Levels
Bits
0
±4
Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity Error
0:25 ±0.50
LSBs
LSBs
-0.25 ±0.50
LSBs
1.5 ±2.5
Differential Non-Linearity Error
0
±4
LSBs
> -1
+2
LSBs
0
±1
LSBs
Channel-to-Channel Matching
±0.1
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBrC
LSBrC
LSBrC
-60
Off Isolation
Feedthrough
-60
Vee Power Supply Rejection
-60
Notes
Input Series Resistance
DC Input Leakage
1K
5K
0
3.0
dB
2,3
dB
2
dB
2
n.
4
f.LA
Sample Time: Prescaler On
Prescaler Off
15
8
States
States
Sampling Capacitor
3
pF
NOTES:
'An "LSB", as used here. has a value of approximately 5 mY.
1. Typical values are expected for most devices at 25'e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
16-19
II
inteL
80C196KB10/83C196KB10/80C196KB12/83C196KB12
1W1m!gI!..D~DOO~ImW
EXTENDED TEMPERATURE/EXTENDED BURN-IN ONLY SPECIFICATIONS
Symbols
Description
Min
Units
Max
mV
RESET
Hysteresis
Hysteresis on RESET Pin
TBD
Ipo
Powerdown Mode Current
TBD
mA
hLYV
ALE Low to READY Setup
Tose - S5
ns
hLGV
ALE Low to BUSWIDTH Setup
Tose - SO
ns
TAVOV
Address Valid to Input Data Valid
3 Tose - SO
ns
Tose - 25
ns
,
TRLOV
RD Low to Input Data Valid
TLHLL
ALE High Period
Tosc - 12
TRHAX
ADa-AD15 Hold after RD Rising
Tose - 50
THALAZ
HLDA Low to Address Float
-25
ns
THALBZ
HLDA Low to SHE, INST,
RD, WR Float
-30
ns
THAHBV
HLDA High to BHE, INST,
RD, WRValid
AID Absolute
Error
Absolute Error
Tose
+
12
ns
ns
-25
ns
±S
LSBs
If the first two events into an empty FIFO (not
including the Holding Register) occur in the same
internal phase, both are recorded with one timetag. Otherwise, if the second event occurs within
9 states after the first, its time-tag is one count
later than the first's. If this is the "skipped" time
value, the second event's time-tag is 2 counts
later than the first's.
If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register
after a state times, leaving the FIFO empty again.
If the second event occurs after this time, it Will
act as a new first event into an empty FIFO.
FUNCTIONAL DEVIATIONS
1. The DJNZW instruction is not guaranteed to be
functional. The instruction, if encountered, will
not cause an unimplemented opcode interrupt.
(The opcode for DJNZW is OE1 Hex.) The DJNZ
(byte) instruction works correctly and should be
used instead.
2. The CDE function is not guaranteed to work. The
CDE pin must be directly connected to Vss.
3. The HSI unit has two errata: one dealing with resolution and the other with first entries into the
FIFO.
The HSI resolution is 9 states instead of a states.
Events on the same line may be lost if they occur
faster than once every 9 state times.
There is a mismatch between the 9 state time
HSI resolution and the a state time timer. This
causes one time value to be unused every 9 timer
counts. Events may receive a time-tag one count
later than expected because of this "skipped"
time value.
4. The serial port Framing Error flag fails to indicate
an error if the bit preceding the stop bit is a 1.
This is the case in both the a-bit and 9-bit modes.
False framing errors are never generated.
5. The serial port RI flag is not generated after the
first byte is received. The problem does not occur
if the baud rate is reloaded after each reception.
S. If the unsigned divide instruction (byte or word) is
the last instruction in the queue .as HOLD or
READY is asserted, the result may be incorrect.
1S-20
intel·
80C196KB10/83C196KB10/80C196KB12183C196KB12
DATA SHEET REVISION HISTORY
This data sheet (270916-002) is valid for devices marked with a "B" at the end of the top side tracking number.
Data sheets are changed as new device information becomes available. Verify with your local Intel sales office
that you have the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet and the previous version (-001).
1. The commercial and Express (extended temperature and extended burn-in) devices were combined in this
data sheet. The Express only data sheet (270760-002) is now obsolete.
2. The EPROM devices were removed from this data sheet. They are now in a separate data sheet (270909).
3. The 60C196KB devices were removed from this data sheet. Only the 60C196KB10, 63C196KB10,
60C196KB12 and 63C196KB12 devices are now covered.
4. Changes were made to the format of the data sheet and the SFR. descriptions were removed.
5. Two errata were added: the serial port RI flag and the DIVIDE during HOLD/READY.
6. Three specifications for the extended temperature and extended burn-in devices were changed: VIH2 Min
was changed from 2.4V to 2.6V, T XHCH Min was changed from 35 ns to 40 ns, and T HVCH Min was changed
from 90 ns to 65 ns.
,The -001 data sheet integrated the 67C196KB (order number 270590-003) and the 63C196KB/60C196KB
(order number 270634-003) data sheets. The following differences exist between the -001 data sheet and
each of the above mentioned data sheets.
1. The status of the data sheet was upgraded from ADVANCE INFORMATION to PRELIMINARY.
2. The warning about the ABSOLUTE MAXIMUM RATINGS was reworded and a notice of disclaimer was
added to the electrical specifications section.
3. VIH2 was increased from 2.2V to 2.6V.
4. 11L1 was increased from - 950 p.A to -1.2 mA. This change was documented in the previous revision of the
data sheets but the DC Characteristics table did not reflect the change.
5. Maximum Ipo specification was added to the DC table and Ipo note was deleted.
111
16-21
80C198/83C198/80C194/83C194
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
83C198 - 8 Kbytes of Factory Mask-Programmed ROM
80C198 - ROM less
232 Byte Register File
• Register-to-Reglster
Architecture
• 28 Interrupt Sources/16
• 2.3 ,..,s 16 x 16 Multiply (12Vectors
• 4.0 ,..,s 32/16 Divide (12 MHz)MHz)
•
and Idle Modes
• Powerdown
16-Blt Watchdog Timer
• 8-Blt External Bus
• Extended Temperature Available
•
Duplex Serial Port
• Full
Speed I/O Subsystem
• High
16-Bit Timer
• 16-Blt Counter
• Pulse-Width-Modulated Output
• 16-Blt Software Timers
• Four
10-Bit A/D Converter with Sample/Hold
• Extended
Burn-In Available
•
The 80C198 is the low cost member of the CHMOS MCS®-96 microcontroller family. Intel's CHMOS process
proVides a high performance processor along with low power consumption. To further reduce power requirements, the processor can be placed into Idle or Powerdown Mode.
The 83C198 is an 80C198 with 8 Kbytes on-chip ROM. In this document, the 80C198 will also refer to the
83C198, 80C194 and 83C194 unless otherwise stated. Bit, byte, word and some 32-bit operations are available on the 80C198. With a 12 MHz oscillator a 16-bit addition takes 0.66 p.s, and the instruction times average
0.5 p.s to 1,5 P.s in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or counter. Also provided on-chip are an AID
converter, serial port, watchdog timer and a pulse-width-modulated output signal.
The 80C194 and 83C194 do not have the on-chip AID converter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the temperature range of - 40·C to + 85·C. With the extended burn-in option, the burn-in is
dynamic for a minimum time of 160 hours at 125·C with Vcc = 5.5V ±0.5V, following the guidelines in MILSTD-883, Method 1015. The specifications which are different for the extended temperature and extended
burn-in devices are listed 'in this data sheet. Otherwise, the commercial specifications apply for both.
MCS@·96 is a registered trademark of Intel Corporation.
16-22
October 1991
Order Number: 270815-003
80C198/83C198/80C194/83C194
VREF
ANGND
.--------------------
r-~--~~ :CPrU______,
I
I
.....r--""T... :
I
I
I
I
CONTROL
SIGNALS
I
PORT 3
---......,1/
} ~~~:
BUS
PORT 4
HSI
A/D
HSO
270815-1
Figure 1. 80C198/80C198 Block Diagram
OFFFFH
EXTERNAL MEMORY OR 1/0
117161514131211 10 ICHIP CONFIGURATION REGISTER
4000H
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
L..::OWERDOWN MODE ENABLE
20BOH
RESERVEO
'---0
2040H
UPPER BINTERRUPT VECTORS
ADDRESS VALID STROBE SELECT
2030H
(ALE/ ADV)
ROMIEPROM SECURITY KEY
2020H
(lRCO) )INTERNAL READY CONTROL
RESERVED·
2019H
(IRC1)
201BH
(LOCO) }
(LOCI) PROGRAM LOCK MODE
CHIP CONFIGURATION BYTE
MODE
RESERVED
2014H
270815-7
LOWER B INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
Figure 3. Chip Configuration (2018H)
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY OR 1/0
0100H
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER. RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
OOOOH
Figure 2. Memory Map
16-23
..
intel~
80C198/83C198/80C194/83C194
PACKAGING
The 80C198 and 83C198 are available in a 52-pin PLCC package and an 80-pin OFP package. Contact your
local sales office to determine the exact ordering code for the part desired.
Package Designators:
N = 52-pin PLCC
S = 80-pin OFP
Prefix Designators:
T = Extended temperature
L = Extended temperature and extended burn-in
Package Type
8ja
8jc
PLCC
35°C/W
12°C/W
QFP
85°C/W
-
Figure 4. 8XC198 Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for description of Intel's thermal impedance test methodology.
a
....
() >VJ
~
.
...'"
..J
X
~lii
> !!:
0
,,; ,,;
I~.......
0..
0..
0
;:;
.. .. .
'"
..J
..............
I~
Q
ACH5/PO.5
AD2/P3.2
ACH4/PO.4
AD3/P3.3
ANGND
AD4/P3.4
VREF
AD5/P3.5
vss
AD6/P3.6
inteJ®
EXTINT/P2.2
RESET
RXD/P2.1
N80C198
TXD/P2.0
TOP VIEW
41
AD7/P3.7
AS/P4.0
A9/P4.1
A 10/P4.2
A 11/P4.3 .
HSI.O
HSI.1
A 12/P4.4
HSO.4/HSI.2
A13/P4.5
HSO.5/HSI.3
A 14/P4.6
.
'..." .'" ''"" :;;:
III
III
0
.... Q>0 0 -:%' c::i >1Il :tOll I~
'"0.. ....0..
0 VI
VI
0..
Q.
VI
> '"
:t: :t:
:t:
....... '" ....... .......
.......
Oll
III
'"
'"
:t:
,.,
::>
0..
VI
...'"'"
..J
()
...'"
Figure 5. 52-Pin PLCC Package
16-24
270815-2
intel .
80C198/83C198/80C194/83C194
.... ....
'"a..
,.; ,.; ,.;
'"
,.;
'-
...'"
0
III
~
'.... '.... '-
... ... ...'"
0
0
0
.'" . . .'" .. .
.... ....
co .....
"! "': "! -:
....
a.. a.. .... .... a.. a.. a.. a.. a.. a..
a..
a..
'''''''CO
..... '0
.... '-
'"
a.. a.. a..
'"
>'"
... ... ... '-...en
0
0
CO
;:
... ...'" ;:'" ... ...'"
64
AD1/P3.1
ADO/P3.0
Ro
ALE/AoV
INST
VSS
N.C.
XTAL2
XTALI
80C198/83C198
80C194/83C194
80-PIN QFP
VSS
VSS
Vee
Vee
EA
TOP VIEW
VSS
N.C.
N.C.
N.C.
N.C.
ACH6/PO.6
ACH7/PO.7
N.C.
ACH5/PO.5
T2CLK/P2.3
63
VSS
62
READY
61
T2RST/P2.4
60
N.C.
59
WR
58
PWt.t/P2.5
57
N.C.
56
Vpp
55
VSS
54
VSS
53
HSO.3
52
Vee
51
VSS
50
HSO.2
49
N.C.
48
N.C.
47
N.C.
46
N.C.
45
HSO.l
44
HSO.O
43
HSO.5/HSI.3
42
VSS
41
HSO.4/HSI.2
ACH4/PO.4
0
:z
:z
"...
...
"-
'"a.. -?'"
::' >'" N
'fIII
:z
;::
...
...
f-
II>
'"
...
X
0
'" :i.; :z~ :i.; :i.; :i.; iii"! iii
N N >'"
a.. a..
:l: :l:
''0
0
x
'"
x
0-
270815-4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 6. SO-Pin QFP Package
16-25
II
intel~
80C198/83C198/80C194/83C194
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (SV).
Vss
The PLCC package has S Vss pins and the QFP package has 12 Vss pins. All must be
connected to circuit ground.
VREF
Reference voltage for the AID converter (SV). VREF is also the supply voltage to the
analog portion of the A/D converter and the logic used to read Port O. Must be
connected for AID and Port 0 to function.
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential
as Vss.
Vpp
Timing pin for the return from powerdown circuit. Connect this pin with a 1 J-LF capacitor
to Vss. If this function is not used, connect to Vee. This pin is the programming voltage
on the EPROM device.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
RESET
Reset input to and open-drain output from the chip. Input low for at least 4 state times to
reset the chip. The subsequent low-to-high transition commences the Reset Sequence
in which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to location
2080H is executed. Input high for normal operation. RESET has an internal pull up.
INST
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to off-chip
memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select
for external memory. ALE/ ADV is activated only during external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory
reads.
WR
Write output to external memory. WR will go low for every external write.
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. When the external memory is not being used, READY has no effect. Internal
control of the number of wait states inserted into a bus cycle held not ready is available
through configuration of CCA.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSLO, HSL1, HSL2 and
HSL3. Two of them (HSL2 and HSL3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSOA and HSO.S. Two of them (HSOA and HSO.S) are shared with the
HSI Unit.
PortO
4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on
the EPROM device.
Port 2
Multi-functional port. All of its pins are shared with other functions in the 80C198.
16-26
intel·
80C198/83C198/80C194/83C194
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups. Available as I/O only
on the ROM and EPROM devices.
TxD
The TxD pin is used for serial port transmission in Modes 1,2 and 3. The TxD function is
enabled by setting IOC1 5. In mode a the pin is used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. The RxD function is enabled by
setting SPCON.3. In mode a the pin functions as input or output data.
EXTINT
A positive transition on the EXTINT pin will generate an external interrupt. EXTINT is
selected as the external interrupt source by setting IOC1.1 high.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled
by setting IOCO.03 T2RST is enabled as the reset source by clearing 10CO.S.
PWM
Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM
is determined by the value loaded into the PWM-CONTROL register (17H).
II
16-27
infel~
80C198/83C198/80C194/83C194
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias ................. - 55°C to + 125°C
Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin to Vss ........ -0.5V to + 7.0V
Power Dissipation(1) ....................... 1.5W
NOTE:
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
1. Power dissipation is based on package heat transfer, not
device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
Description
Min
Max
Units
0
+70
·C
TA
Ambient Temperature Under Bias Extended Temp.
-40
+85
°C
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
Fose
Oscillator Frequency
3.5
12
MHz
TA
Ambient Temperature Under Bias Commercial Temp.
,
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Description
Min
Max
Units
-0.5
0.8
V
VIL
Input Low Voltage
VIH
Input High Voltage (Note 1)
VIH1
Input High Voltage on XTAL 1
0.7 Vee
Vee + 0.5
V
VIH2
Input High Voltage on RESET
2.6
Vee + 0.5
V
VOL
Output Low Voltage
0.3
0.45
1.5
V
V
V
VOH
Output High Voltage
(Standard Outputs)
III
Input Leakage Current (Std. Inputs)
ILl1
Input Leakage Current (Port 0)
IlL 1
Logical 0 Input Current in Reset (Note 2)
(ALE, RD, WR, INST, P2.0)
Hyst
Hysteresis on RESET Pin
0.2 Vee + 1.0 Vee + 0.5
= 200 p,A
= 32mA
= 7 mA
IOH = - 200 p,A
IOH = -3.2mA
IOH = -7 mA
IOL
IOL
IOL
p,A
o<
+3
p,A
0< VIN < VREF
-1.2
mA
VIN
±10
300
NOTE:
1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the part to enter test modes.
16-28
V
V
V
V
Vee - 0.3
Vee - 0.7
Vee- 1.5
Test Conditions
mV
VIN < Vee - 0.3V
=
0.45 V
int:eL
80C198/83C198/80C194/83C194
DC CHARACTERISTICS (Continued)
Symbol
Description
Min
Typ(6)
Max
Units
Test Conditions
XTAL1 = 12 MHz
Vcc = Vpp = VREF
Icc
Active Mode Current in Reset
40
55
mA
IREF
AID Converter Reference Current
2
5
mA
IIDLE
Idle Mode Current
10
22
mA
ICC1
Active Mode Current
15
22
mA
XTAL1
Vcc
IpD
Powerdown Mode Current
RRST
Reset Pullup Resistor
Cs
Pin Capacitance (Any Pin to VSS)
5
6K
50
,...A
65K
n
10
pF
=
FTEST
=
5.5V
=
5.5V
3.5 MHz
Vpp
=
=
=
VREF
1.0 MHz
NOTES:
(Notes apply to all specifications)
1. Standard Outputs include ADO-15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXD/P2.0 and
RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open·drain outputs.
2. Standard Inputs include HSI pins, EA, READY, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on Standard Output pins: 10 mA
4. Maximum current per bus pin (data and control) during normal operation is ± 3.2 mAo
5. During normal (non·transient) conditions the following total current limits apply:
HSO, P2.0, RXD, RESET
IOL: 29 mA
IOH: 26 mA
P2.5, WR
IOL: 13 mA
IOH: 11 mA
ADO-AD15
IOL: 52 mA
IOH: 52 mA
RD, ALE, INST
IOL: 13 mA
IOH: 13 mA
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.
60
Icc MAX
50
Icc TYPICAL (6)
40
Icc
rnA
30
IIDLE MAX
20
10
IIDLE TYPICAL
0
4MHz
8 MHz
12MHz
FREQ
lee Max = 3.88 x FREQ + 8.43
IIDLE Max = 1.65 x FREQ + 2.2
Figure 7. Icc and IIDLE vs Frequency
16-29
270815-22
80C198/83C198/80C194/83C194
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
= 100 pF, Rise and fall times = 10 ns, Fosc = 12 MHz
The system must meet these specifications to work with the 80C198/83C198:
Symbol
Description
TAVYV
Address Valid to Ready Setup
hLYV
ALE Low to READY Setup
TYLYH
Non READY Time
hLYX
READY Hold after ALE Low
Min
Max
Units
2 Tosc - 85
ns
Tosc - 70
No upper limit
Tosc - 15
Notes
ns
ns
2 Tosc - 40
ns
(Note 1)
TAVDV
Address Valid to Input Data Valid
3 Tosc - 60
ns
(Note 2)
TRLDV
RD Active to Input Data Valid
Tosc - 23
ns
(Note 2)
TRHDZ
End of RD to Input Data Float
Tosc- 2O ·
ns
TRXDX
Data Hold after RD Inactive
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2 Tasc x n, where n = number of wait states.
The 80C198/83C198 will meet these specifications:
Symbol
Min
Max
Units
Notes
Frequency on XTAL1
3.5
12
MHz
(Note 1)
Tesc
I/FXTAL
83
286
ns
TLHLH
ALE Cycle Time
TLHLL
ALE High Period
Tosc - 10
TAVLL
Address Setup to ALE Falling Edge
Tesc - 20
ns
TLLAX
Address Hold after ALE Falling Edge
Tosc - 40
ns
TLLRL
ALE Falling Edge to RD Falling Edge
Tesc - 30
ns
TRLRH
RD Low Period
Tosc - 5
Tosc + 25
ns
(Note 4)
Tesc
Tosc + 25
ns
(Note 3)
10
ns
FXTAL
Description
ns
4 Tosc
Tesc+ 1O
(Note 4)
ns
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
Tesc - 10
ns
TOVWH
Data Stable to WR Rising Edge
Tosc - 23
ns
(Note 4)
TWLWH
WR Low Period
Tosc - 30
ns
(Note 4)
TWHOX
Data Hold after WR Rising Edge
Tesc - 2.5
TWHLH
WR Rising Edge to ALE Rising Edge
Tesc - 10
TWHBX
INST Hold after WR Rising Edge
Tesc - 10
ns
TRHBX
INST Hold after RD Rising Edge
Tosc - 10
ns
TWHAX
AD8-15 Hold after WR Rising Edge
Tosc - 50
ns
TRHAX
AD8-15 Hold after RD Rising Edge
Tesc - 25
ns
Tesc + 5
ns
Tosc + 15
ns
NOTES:
1. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
2. Typical specification, not guaranteed.
.
3. Assuming back-to-back bus cycles.
4. When using wait states, add 2 T asc x n, where n = number of wait states.
16-30
(Note 3)
intet
80C198/83C198/80C194/83C194
System Bus Timings
BUS
ADDRESS OUT
TAVOV
WRITE
BUS
-<
ADDRESS OUT
DATA OUT
ADDRESS
I
VALID
BHE,INST
A8-15
r-
TRHAX ...
TWHAX
ADDRESS OUT
270815-23
READY Timings (One Wait State)
XTALI
•
ALE \
READY
_+________.. 1-0>----
J::========~
TRLRH + 2 Tose
-.....J
----~--I
TRLDV + 2 Tose
TAVDV + 2Tose
)
(
DATA
I
~
TWLWH
r---
+ 2Tose
TQVWH
+ 2Tose
»»»)
-J
~
~__________~~~~________D_~_A_OU_T______~X
ADDRESS
~------
1
270815-24
16-31
infel·
80C198/83C198/80C194/83C194
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max·
Units
1/TXLXL
Oscillator Frequency
3.5
12.0
MHz
TXLXL
Oscillator Period
83
286
ns
TXHXX
High Time·
32
ns
TXLXX
Low Time
32
ns
TXLXH
Rise Time
10
ns
TXHXL .
FaUTime
10
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270815-25
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
. interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
Cl
'$II~ ........
~
Vee
+---I XTAL 1 80C198
EXTERNAL
CLOCIS'INPUT
XTAL2
.-
f
4.7K·
XTALI
clock driver
Quartz Crystal or·
Ceramic Resonator
80C198
no connect- XTAL2
270815-29
270815-30
NOTE:
• Required if TTL. driver used.
Not needed il CMOS driver is used.
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and Vss. When
using crystals, C1 = 20 pF and C2 = 20 pF. When
using ceramic resonators, consult manufacturer for recommended capacitor values.
16-32
intel~
80C198/83C198/80C194/83C194
AC TESTING INPUT, OUTPUT WAVEFORMS
2.4==:>( 2.0> TEST POINTS
O.B
<
0.45
2.0
O.B
FLOAT WAVEFORMS
x==
270815-26
270815-27
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the .Loaded VOHIVOL Level occurs
IOL/loH ~ ± 15 rnA.
AC Testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic
., 1" and 0.8V for a Logic "0".
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
- High
A
L
- Low
D
- DATA IN
V
- Valid
L
- ALE/ADV
X
- No Longer Valid
Q
- DATA OUT
Z
- Floating
R
RD
W
- WR
X
- XTAL1
Y
- READY
Address
•
16-33
intel·
80C198/83C198/80C194/83C194
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol
Parameter
Min
Max
Units
TXLXL
Serial Port Clock Period (BRR ~ 8002H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR ~8002H)
TXLXL
Serial Port Clock Period (BRR = 8001 H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)
2 Tose - 50
TQVXH
Output Data Setup to Clock Rising Edge
2 Tose -50
ns
TXHQX '
Output Data Hold after Clock Rising Edge
2 Tose -50
ns
TXHQV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHOX
Input Data Hold after Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
ns
6 Tose
4Tose-5O
ns
4 Tose + 50
ns
4 Tose
ns
2 Tose + 50
ns
2 Tose +50
ns
Tose +50
-
0
ns
ns
1 Tose
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
RXD - - , . , - - . . , - , I""----,.~__,. •.--.,. r~.'------" ~-,. ,r----.. .'---"r~.'------" ~__,. •. - -....
(IN)_.J'_1'tc_I'-----''___-'''----''~-'' ....~1'-__''_'~.'_~,''_'_'~cl'_____''·.''_'''
270815-28
16-34
int:el.
80C198/83C198/80C194/83C194
A TO D CHARACTERISTICS
There are two modes of AID operation: with or without clock prescaler. The speed of the AID converter
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 8 MHz. The conversion times with the prescaler turned on or off is
shown in the table below.
The converter is ratiometric, so the absolute
accuracy is directly dependent on the accuracy and
stability of VREF. VREF must be close to Vcc since it
supplies both the resistor ladder and the digital section of the converter.
The 80C194/83C194 does not have an AID converter.
See the MCS-96 AID Quick Reference for definition
of AID terms.
Conversion Time
Clock Prescaler On
IOC2.4 = 0
Clock Prescaler Off
IOC2.4 = 1
158 States
26.33 p.s @ 12 MHz
91 States
22.75 p.s @ 8 MHz
AID CONVERTER SPECIFICATIONS
Typical(1)
Parameter
Minimum
Maximum
Units'
512
9
1024
10
Levels
Bits
9
±4
LSBs
Resolution
Absolute Error
Full Scale Error
0.25 ±0.50
Zero Offset Error
LSBs
-0.25 ±0.50
Non-Linearity Error
Notes
LSBs
1.5 ±2.5
Differential Non-Linearity Error
0
±4
LSBs
>-1
+2
LSBs
0
±1
LSBs
Channel-to-Channel Matching
±0.1
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBI"C
LSBI"C
LSBI"C
-60
Off Isolation
dB
2,3
Feedthrough
-60
dB
2
Vcc Power Supply Rejection
-60
dB
2
Input Series Resistance
\
DC Input Leakage
1K
5K
n
0
3.0
p.A
Sample Time: Prescaler On
Prescaler Off
15
8
States
States
Sampling Capacitor
3
pF
NOTES:
'An "LSB", as used here; has a value of approximately 5 mY.
1. Typical values are expected for most devices at 25'C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capaCitor.
16-35
4
infel~
80C198/83C198/80C194/83C194
EXTENDED TEMPERATURE/EXTENDED BURN-IN ONLY SPECIFICATIONS
Symbol
Description
Min
Max
Units
RESET Hysteresis
Hysteresis on RESET Pin
IPD
Powerdown Mode Current
TBD
mA
hLYV
ALE Low to READY Setup
Tose - 65
ns
TAVDV
Address Valid to Input Data Valid
3 Tose - 60
ns
TRLDV
RD Low to Input Data Valid
Tose - 25
ns
hHLL
ALE High Period
TRHAX
AD8-15 Hold after RD Rising
AID Absolute Error
Absolute Error
TBD
Tose - 12
mV
Tose + 12
Tose - 50
+6
1. The DJNZW instruction is not guaranteed to be
functional. The instruction, if encountered, will
not cause an unimplemented opcode interrupt.
(The opcode for DJNZW is OE1 Hex.) The DJNZ
(byte) instruction works correctly and should be
used instead.
There is a mismatch between the 9 state time
HSI resolution and the 8 state time timer. This
causes one time value to be unused every 9 timer
counts. Events may receive a time-tag one count
later than expected because of this "skipped"
time value.
LSBs
If the first two events into an empty FIFO (not
including the Holding Register) occurs within 9
states after the first, its time-tag is one count later
than the first's. If this is the "skipped" time value,
the second event's time-tag is 2 counts later than
the first's.
If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register
after 8 state times, leaving the FIFO empty again.
If the second event occurs after this time, it will
act as a new first event into an empty FIFO.
FUNCTIONAL DEVIATIONS
2. The HSI unit has two errata: one dealing with resolution and the other with first entries into the
FIFO.
The HSI resolution is 9 states instead of 8 states.
Events on the same line may be lost if they occur
faster than once every 9 state times.
ns
ns
3. The serial port Framing Error flag fails to indicate
an error if the bit preceding the stop bit is a 1.
This is the case in both the 8-bit and 9-bit modes.
False framing errors are never generated.
4. The serial port RI flag is not generated after the
first byte is received. The problem does not occur
if the baud rate is reloaded after each reception.
5. If the unsigned divide instruction (byte or word) is
the last instruction in the queue as HOLD or
READY is asserted, the result may be incorrect.
16-36
intel·
80C198/83C198/80C194/83C194
REVISION HISTORY
This data sheet (270815-003) is valid for devices
marked with a "8" at the end of the top side tracking
number. Data sheets are changed as new device
information becomes available. Verify with your local
Intel sales office that you have the latest version
before finalizing a design or ordering devices.
The following differences exist between this data
sheet and the previous version (-002).
1. The Express (extended temperature and extended burn-in) devices were added to this data
sheet.
2. Changes were made to the format of the data
sheet and the SFR descriptions were removed.
3. Four errata were added: the CDE pin, the HSI
resolution, the serial port framing error flag, the
serial port RI flag and the DIVIDE during HOLD/
READY.
4. One specification for the extended temperature
and extended burn-in devices was changed: VIH2
Min was changed from 2.4V to 2.6V.
Differences between -002 and the -001 version of
the 80C198 data sheet.
1. Vss pin description was altered to reflect the correct number of pins.
2. VIH2 Min was changed from 2.2V to 2.6V.
3. Max Ipo was added and the Ipo note was deleted.
For more detailed Information on the 80C198, refer to the 80C196KB User's Guide, order number
270651. The 80C196KB User's Guide applies to
the 80C198 except for the design considerations
listed above. Because the 80C198 is a reduced
pin count version, some80C196KB features are
not available and are listed here:
1. PORT 1. PORT1 is a quasi-bidirectional port.
A. HOLD/HLDA. This feature is multiplexed on
PORT1.5-.7 and is not available.
2. The AID converter loses four of its input channels, ACHO-3.
3. T2CAPTURE (P2.7) Timer2 Capture feature is
not available.
4. T2UP/DN (P2.6) The Timer2 UP/DOWN feature
is not available.
5. CLKOUT
6. NMI
7. 8USWIDTH
8.8HE
9. PACT
16-37
8XC196KB/8XC196KB16
, COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
•
•
•
•
•
•
•
•
•
•
•
a Kbytes of On-Chip ROM/OTP
Available
•
232 Byte Register File
Duplex Serial Port
• Full
High Speed I/O Subsystem
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
1.75 ,...,s 16 x 16 Multiply (16 MHz)
3.0 ,...,s 32/16 Divide (16 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
16-Bit Watchdog Timer
12 MHz and 16 MHz Available
Dedicated 15-Bit Baud Rate Generator
•
•
•
•
•
•
•
•
Dynamically Configurable a-Bit or
16-Bit Buswidth
16-Bit Timer
i6-Bit Up/Down Counter with Capture
Pulse-Width-Modulated Output
Four 16-Bit Software Timers
10-Bit A/D Converter with Sample/Hold
HOLD/HLDA Bus Protocol
Extended Temperature Available
The 8XC196KB is a 16-bit microcontroller available in three different memory varieties: ROM less (80C196KB),
8K ROM (83C196KB) and 8K OTP (One Time Programmable-87C196KB). The 8XC196KB is a high performance member of the MCS-96 microcontroller family. The 8XC196KB has the same peripheral set as the
8096BH and has a true superset of the 8096BH instructions. Intel's CHMOS process provides a high performance processor along with low power consumption. To further reduce power requirements, the processor can
be placed into Idle or Powerdown Mode.
Bit, byte, word and some 32-bit operations are available. on the 80C196KB. With a 16 MHz oscillator a 16-bit
addition takes 0.50 JA-s, and the instruction times average 0.37 JA-s to 1.1 JA-s in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or up/down counter. Also provided on-chip are an
AID converter, serial port, watchdog timer and a pulse-width-modulated output signal.
The 8XC196KB has a maximum guaranteed frequency of 12 MHz. The 8XC196KB16 has a maximum guaranteed frequency of 16 MHz. All references to the 80C196KB also refer to the 80C196KB16; 83C196KB, Rxxx;
87C196KB and 87C196KB16 unless otherwise noted. The ROM device does not have a speed indicator at the
end of the device name. Instead it has a ROM code number.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of O·C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the temperature range of - 40·C to + 85"C.
Package Designators: N
ed Temperature.
= 68-pin PLCC, S = 80-pin QFP (commercial only). Prefix Designators: T = Extend-
16-38
October 1992
Order Number: 270909-004
int:eL
VREF
8XC196KB/8XC196KB16
ANGND
CONTROL
SIGNALS
l ~~~:
BUS
~--t-I/
PORT 4
1+---1--
ALTERNATE
FUNCTIONS
HSO
270909-1
Figure 1. 8XC196KB Block Diagram
II
16-39
8XC196KB/8XC196KB16
Table 2. 8XC196KB Memory Map
PROCESS INFORMATION
Description
This device is manufactured on P629.0 and 629.1, a
CHMOS "I-E process. Additional process and reliability information is available in Intel's Components
Quality and Reliability Handbook, Order Number
210997.
L
~
External Memory or I/O
x ~c
-1 l! §!$.J! ~D"'''SP''d'
No Mark
=12 t.4Hz
16'" 16WHz
Address
OFFFFH
04000H
Internal ROM/EPROM or External
Memory (Determined by EA)
3FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
Word Addressable Only
1FFFH
1FFEH
External Memory
1FFDH
0100H
232 Bytes Register RAM (Note 1)
OOFFH
0018H
CPU SFR's (Notes 1, 3)
0017H
OOOOH
K8 Product ramlly
CHt.40S Technology'
Program Wemary Options:
7
=[PROt-! (Note
1)
L -_ _ _ _ _ _ _ Package Type Options:
N = U-lltad PL.CC
S::: BO-Iead Qrp
L -_ _ _ _ _ _ _ _ _ rempefature and Burn-In Options:
No Mark"" DoC - 70 0
e Ambient
with
Intel Standard Burn-In
270909-2
EXAMPLE:
N87C196KB16
is
68-Lead
PLCC
OTPROM, 16 MHz.
For complete 'package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 2. The 8XC196KB Nomenclature
Table 1. Thermal Characteristics
Package
Type
°la
Ole
PLCC
35°C/W
13°C/W
QFP
70°C/W
4°C/W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions .and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel's thermal impedance test methodology.
NOTES:
1. Code executed in locations OOOOH to OOFFH will be
forced external.
2. Reserved memory locations must contain OFFH unless
noted.
3. Reserved SFR bit locations must contain O.
4. Refer to 8XC196KB quick reference for SFR descrip·
tions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
.
16-40
infel·
8XC196KB/8XC196KB16
.., ...
L..i ..J
Q
o 0
2 2
a.. a..
..............
,.... co N
Q
o
C
...
tf'J
0 0 0 0 0
a.. a.. a.. a.. a.. a..
..........................................
,....
q)
N O ' " rt)
:::z:: :z::
:z:: ::z: :::z::
:::z::
~ ~ ~ ~ ~ ~ ~ 1L!i
ACH5/PO.5/PIoIODE.l
ADO/P3.0
ACH4/PO.4/PIoIODE.0
AD1/P3.1
ANGND
AD2/P3.2
VREF
AD3/P3.3
N8XC196KB
68-PIN
PLCC
VSS
EXTINT /P2.2!PROG
RESET
AD4/P3.4
AD5/P3.5
AD6/P3.6
RXD/P2. 1!PALE
AD7/P3.7
TXD/P2.0/PVER
AD8/P4.0
PLO
AD9/P4.1
Pl.l
TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
Pl.2
Pl.3
Pl.4
HSI.O/SID.O
AD10/P4.2
ADll/P4.3
ADI2/P4.4
ADI3/P4.5
ADI4/P4.6
HSI.l/SID.l
ADI5/P4.7
HSI.2/HSO.4/SID.2
T2CLK/P2.3
272829 30 3132 33 34 35 36 37 38 39 40 41 4243
..,
... ..,
.
z
0
>d II! "! ": QI d d >cn::-~
ci d UI
N ~ ai ~ Q
~"'~~~
a.. a.. a.. a.. UI UI ~
iii UI
%
a.. a.. I..J
-< is
..................... :::> :0:: %
....... %
II<
"'d
UI
:0::
.......
"!
iii
I~ I~ Ii
...
0-
.......
CD
'"
a..
:0::
1.1.1
0::
:::>
~
~
~
a..
0::
~
I:::E:
;;
...c:§
~
....
'"
....
N
a..
-;:.
~
...
0-
a..
270909-3
Figure 3. 58·Pin Package (PLCC Top View)
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROM less
(SOC196KB) doesn't use any of the programming pins.
16-41
•
int'el..
8XC196KB/8XC196KB16
..,
.."'" "..'" "..... "..,..,.. ".. """ ".. "..... """ "-.. "...'" "..,'""" ".. "..
'"
.. .. ..'" ..'" .. .. .. ..
c
c
c
1/1
..; ..; u "! ..;
~ 0.. 0.. ><.J ~ 0..
0..
AD1/P3.1
GO
Q
0
Q
C C C C C C
0..
0..
0
0..
0..
0..
0..
Ill'"
"w ,VI
•
~>~
"
~...
>81~a:
Z
;::
..,x
0
....
....
0.. 0..
~ "">
..,a:
"! "!
III 0
III
•
>0..
0..
0..
Q
X
a:
~
a:: a:: a::
HSO.4/HSI.2/SID.2
0
ci ci
Vi Vi
"Vi "Vi
~
:I:
:I:
C
~
270909-4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 4. 80-Pln QFP Package
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the prOgraming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PR G. The ROMless
(80C196KB) doesn't use any of the programming pins.
16-42
int'et
8XC196KB/8XC196KB16
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are three Vss pins, all of them must be connected.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential as
Vss. Connect Vss and ANGND at chip to avoid noise problems.
Vpp
Programming voltage. Also timing pin for the return from power down circuit.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is
frequency. It has a 50% duty cycle.
RESET
Reset input to and open-drain output from the chip. Input low for at least 4 state times to reset
the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a
10-state-time RESET sequence.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
% the oscillator
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/OTPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ALE/ ADV is activated only during external memory
accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCA. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external writes
where an odd byte is being addressed. BHE/WRH is activated only during external memory
writes.
READY
Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of
CLKOUT, the memory controller goes into a wait mode until the next positive transition in
CLKOUToccurs with READY high. When the external memory is not being used, READY has
no effect. Internal control of the number of wait states inserted into a bus cycle (held not
ready) is available in the CCA.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
16-43
..
8XC196KB/8XC196KB16
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
PortO
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
.
Port 1
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Pins P2.6 and P2.7 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional 110 ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
HLDA
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BRSQ
Bus Request output activated when the bus controller has a pending external memory
cycle. Enabled by setting WSR.7.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is
used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or
output data.
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST
A rising edge on the T2RST pin will reset Timer2.
PWM
The pulse width modulator output.
T2UP-DN
The T2UPDN pin controls the direction of Timer2 as an up or down counter.
T2CAPTURE
A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register.
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
SID
Slave 10 Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
PROG·
Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
PACT
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
PVAL
Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.
PVER
Program Verification. Used in Slave Programming and Auto CLB Programming Modes.
Signal is low after rising edge of PROG if the programming was not successful.
AINC
Auto Increment. Active low Signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
Ports 3
and 4
(Programming
Mode)
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory. Should have pullups to Vee when used in slave
programming mode.
16-44
inteL
axe 196KB/axe 196KB 16
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature
Under Bias ................. - 55°C to + 125°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature .......... -65°C to + 150°C
Voltage On Any Pin to vss ........ - 0.5V to + 7.0V
Power Oissipation(1) ....................... 1.5W
NOTE:
1. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias
0
+70
°C
V
Vee
Digital Supply Voltage
4.50
5.50
VREF
Analog Supply Voltage
4.50
5.50
V
Fose
Oscillator Frequency 12 MHz
3.5
12
MHz
Fose
Oscillator Frequency 16 MHz
3.5
16
MHz
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Description
VIL
Input Low Voltage
VIH
Input High Voltage(1)
VIH1
Input High Voltage on XTAL 1
VIH2
Input High Voltage on RESET
VOL
Output Low Voltage
VOH
Output High Voltage
(Standard Outputs)
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)
III
Input Leakage Current (Std. Inputs)
Min
Max
Units
-0.5
0.8
V
Test Conditions
+ 0.5
V
0.7 Vee
Vee + 0.5
V
2.6
Vee + 0.5
V
0.3
0.45
1.5
V
V
V
IOL = 200/l-A
IOL = 3.2 rnA
IOL = 7 rnA
Vee - 0.3
Vee - 0.7
Vee - 1;5
V
V
V
IOH = -200/l-A
IOH = -3.2 rnA
IOH = -7 rnA
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
IOH = -10/l-A
IOH = -30/l-A
IOH = -60/l-A
0.2 Vee + 0.9 Vee
±10
/l-A
o < VIN
< Vee < VREF
ILI1
Input Leakage Current (Port 0)
+3
/l-A
0< VIN
ITL
1 to 0 Transition Current (aBO Pins)
-650
/l-A
VIN = 2.0V
IlL
Logical 0 Input Current (QBO Pins)(4)
-50
/l-A
VIN = OA5V
NOTE:
All pins except RESET and XTAL1.
16-45
..
0.3V
iniaL
8XC196KB/8XC196KB16
DC CHARACTERISTICS (Continued)
Symbol
Description
Min
Typ(7)
Max
Units
11L1
Logical 0 Input Current in Reset
ALE, RD, INST
-7
rnA
VIN
=
Test Conditions
0.45V
IIH1
Logical 1 Input Current
on NMI Pin
100
p.A
VIN
=
2.0V
,
Hyst.
Hysteresis on RESET Pin
ICC
Active Mode Current in Reset
50
60
rnV
rnA
IREF
AID Converter Reference Current
2
5
rnA
IIDLE
Idle Mode Current
10
25
rnA
300
XTALl = 16MHz
VCC = Vpp = VREF
ICC1
Active Mode Current
15
25
rnA
XTAL1
IpD
Powerdown Mode Current
5
30
p.A
VCC
RRST
Reset Pullup Resistor
Cs
Pin Capacitance (Any Pin to VSS)
6K
50K
n
10
pF
=
FTEST
=
5.5V
=
5.5V
3.5 MHz
Vpp
=
=
=
VREF
1.0 MHz
NOTES:
(Notes apply to all specifications)
1. QSD (Quasi-bidirectional) pins include Port 1, P2.6 and P2:7.
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VQ!:L specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, SUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and
T2RST/P2.4.
4. Maximum current per pin must be externally limited to the following .values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: lOrnA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: lOrnA
5. Maximum current per bus pin (data and control) during normal operation is ±3.2 rnA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOL: 29 rnA
IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 rnA
IOH: 26 rnA
P2.5, P2.7, WR, SHE
IOL: 13 rnA
IOH: 11 rnA
ADO-AD15
IOL: 52 rnA
IOH: 52 rnA
RD, ALE, INST -CLKOUT IOL: 13 rnA
IOH: 13 rnA
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.
60.------.-------.------,-----~
50~----~------~------~~--~
40~----~------~~----~~--~
ICC
mA
30r-----~~~---b~----~----~
Idle Max
Idle Typical
FREQUENCY
lee Max = 3.88 x FREQ + 8.43
IIDLE Max = 1.65 x FREQ + 2.2
Figure 6_ Icc and IIDLE vs Frequency
16-46
270909-5
intet
8XC196KB/8XC196KB 16
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
= 100 pF, Rise and fall times = 10 ns, Fosc = 12/16 MHz
The system must meet these specifications to work with the 87C196KB:
Symbol
Description
TAVYV
Address Valid to READY Setup
hLYV
ALE Low to READY Setup
TYLYH
NonREADY Time
TCLYX
READY Hold after CLKOUT Low
TLLYX
READY Hold after ALE Low
TAVGV
Address Valid to Buswidth Setup
hLGV
ALE Low to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
RD Active to Input Data Valid
TCLDV
CLKOUT Low to Input Data Valid
TRHDZ
End of RD to Input Data Float
TRXDX
Data Hold after RD Inactive
Min
Max
Units
2 Tosc - 75
ns
Tosc - 60
ns
No upper limit
Notes
(Note 3)
ns
0
Tosc - 30
ns
(Note 1)
Tosc - 15
2 Tosc - 40
ns
(Note 1)
2 Tosc - 75
ns
Tosc - 60
ns
3 Tosc - 55
ns
(Note 2)
Tosc - 23
ns
(Note 2)
Tosc - 50
ns
Tosc - 20
ns
0
0
(Note 3)
ns
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2 Tosc x n where n = number of wait states.
3. These timings are included for compatibility with - 90 and BH products. They should not be used for newer high·speed
designs.
III
16-47
intel~
8XC196KB/8XC196KB16
AC CHARACTERISTICS (Continued)
Test Conditions: Capacitive load on ~II pins = 100 pF, Rise and fall times = 10 ns, Fosc = 12/16 MHz
The 87C196KB will meet these specifications:
Symbol
Description
Min
Max
Units
Notes
3.5
12.0
MHz
(Note 2)
(Note 2)
FXTAL
Frequency on XTAL 1 12 MHz
FXTAL
Frequency on XTAL 1 16 MHz
3.5
16.0
MHz
Tosc
1IFxTAL 12 MHz
83.3
286
ns
Tosc
1IFxTAL 16 MHz
62.5
286
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
+20
+ 110
ns
TCLCL
CLKOUT Cycle Time·
TCHCL
CLKOUT High Period
ns
2 Tosc
Tosc - 10
Tosc+ 10
ns
TCLLH
CLKOUT Falling Edge to ALE Rising
-10
+10
ns
TLLCH
ALE Falling Edge to CLKOUT Rising
-15
+15
ns
TLHLH
ALE Cycle Time
TLHLL
ALE High Period
Tosc - 10
TAVLL
Address Setup to ALE Falling Edge
Tosc - 20
ns
TLLAX
Address Hold after ALE Falling Edge
Tosc - 40
ns
Tosc - 35
YLLRL
ALE Falling Edge to RD Falling Edge
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
TOVWH
Data Stable to WR Rising Edge
ns
4 TosC
Tosc+ 10
ns
+4
+25
ns
Tosc- 5
Tosc + 25
ns
(Note 3)
Tosc
Tosc + 25
ns
(Note 1)
+5
ns
ns
Tosc - 10
0
+25
ns
ns
Tosc - 23
-5
+15
ns
Tosc + 5
ns
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
Tosc - 15
TWHOX
Data Hold after WR Rising Edge
Tosc - 15
TWHLH
WR Rising Edge to ALE Rising Edge
Tosc - 15
TWHBX
SHE, INST HOLD after WR Rising Edge
Tosc - 15
ns
TRHBX
SHE, INST HOLD after RD Rising Edge
Tosc -;- 10
ns
TWHAX
AD8-15 hold after WR Rising Edge
Tosc - 30
ns
TRHAX
AD8-15 hold after RD Rising Edge
Tosc - 25
ns
(Note 3)
(Note 3)
ns
Tosc + 10
ns
NOTES:
1. Assuming back-to-back bus cycles.
2. Testing performed at 3.5 MHz, however, the device is static .by design and will typically operate below 1 Hz.
3. When using wait states, all 2 Tosc+ n where n = number of wait states.
16-48
(Note 3)
ns
(Note 1)
intel .
8XC196KB/8XC196KB 16
System Bus Timings
XTALI
CLKOUT
TCLLH
ALE
BUS
BUS
--<_
ADDRESS OUT
_
I
BHE,INST
DATA OUT
I
ADDRESS
TRHBX.
TWHBX
VALID
~
I
ADS-15
r
»«
rTRHAX.
TWHAX
ADDRESS OUT
270909-6
•
16-49
8XC196KB/8XC196KB16
READY Timings (One Wait State)
_+_______ 1 + - - - 1+----------..:...
ADDRESS OUT
TRLRH + 2Tose
----i..;...-------
--+l
TRLDV + 2Tose
TAVDV + 2Tose
~
{tD~AT~A~)~~~»~~W»-------
)
I
_~~~~~~~~~~~~~~~~~~:.::--------TW-LW-H-+-2t-o-se-4
I==l
r
TAVWH + 2Tose
ADDRESS
~---A-DD-RE-S-S-OU-T----~>~"(~--------D-AT-A-O-UT--------~X
I
~-----270909-7 "
Buswldth Bus Timings
XTALI
~:,: ~ "~~ Jr-,,:,'"
BUSWIDTH. _""!"""_ _ _ _ _ ~,---------------
r---
BUS
TAVGV
~
I
-<\.,____~>--<\.,----~»)------------270909-B
16-50
intel~
8XC196KB/8XC196KB 16
HOLD/HLDA Timings
Symbol
Description
THVCH
HOLD Setup
Min
Max
55
15
Units
Notes
ns
(Note 1)
TCLHAL
CLKOUT Low to HLDA Low
ns
TCLBRL
CLKOUT Low to SREQ Low
15
ns
THALAZ
HLDA Low to Address Float
10
ns
THALBZ
HLDA Low to SHE, INST, RD, WR Float
10
ns
TCLHAH
CLKOUT Low to HLDA High
-15
15
ns
TCLBRH
CLKOUT Low to SREQ High
-15
15
ns
THAHAX
HLDA High to Address No Longer Float
-15
ns
THAHAV
HLDA High to Address Valid
0
ns
THAHBX
HLDA High to SHE, INST, RD, WR No Longer Float
-20
ns
THAHBV
HLDA High to SHE, INST, RD, WR Valid
TCLLH
CLKOUT Low to ALE High
0
ns
-5
15
ns
NOTE:
1. To guarantee recognition at next clock.
Maximum Hold Latency
Bus Cycle Type
Latency
Internal Access
1.5 States
16-Sit External Execution
2.5 States
a-Bit External
4.5 States
CLKOUT
BUS
- - { ' - -_ _ __
BHE,INST
Rii,WR
ALE
~l-l
-----I1l-5_ _ _T_C_LL_H-h"'l'-______
270909-9
16-51
intel..
8XC196KB/8XC196KB16
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
l/TxLXL
Oscillator Frequency 12 MHz
3.5
12.0
MHz
l/TxLXL
Oscillator Frequency 16 MHz
TXLXL
Oscillator Period 12 MHz
TXLXL
Oscillator Period 16 MHz
TXHXX
High Time
21.25
TXLXX
Low Time
21.25
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
3.5
16
MHz
83.3
286
ns
62.5
286
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270909-10
An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications, the capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
Cl
Vss
II{I-'-"'+-~
XTAL1
8XC196KB
4.7KO
EXTERNAL
CLOCK INPUT
XTAL2
r------......
~:)-"----1 XTAL1
clock driver
8XC196KB
Quortz Crystol
no connect
270909-11
XTAL2
NOTE:
270909-12
Keep oscillator components close to chip and use
short, direct traces to XTAL 1, XTAL2 and Vss. When
using crystals. C1 = 20 pF, C2 = 20 pF. When using
ceramic resonators, consult manufacturer for recommended circuitry.
• Required if open-collector TTL driver used
Not needed if CMOS driver is used.
16-52
inteL
8XC196KB/8XC196KB16
FLOAT WAVEFORMS
AC TESTING INPUT, OUTPUT WAVEFORMS
2.4
0.45
V
2.0> TEST POINTS
-1\0.8
< 0.8~
V2.0
270909-13
AC Testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0".
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded VOHIVOL Level occurs
IOL/IOH = ± 15 mA.
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
- High
A
- Address
HA
- HLDA
L
- Low
B
- BHE
L
- ALE/ADV
V
- Valid
BR
- BREQ
Q
- DATA OUT
X
- No Longer Valid
C
CLKOUT
R
- RD
Z
- Floating
D
- DATA IN
W
- WR/WRH/WRL
G
- Buswidth
. - HOLD
X
- XTAL1
Y
- READY
H
•
16-53
int:eL
8XC196KB/8XC196KB16
State times are calculated as follows:
10-BIT AID· CHARACTERISTICS
.
At a clock speed 016 MHz or less, the clock prescaler should be disabled. This·is accomplished by setting IOC2.4 = 1.
At higher frequencies (greater than 6 MHz) the clock
prescaler should be enabled (IOC2.4 = 0) to allow
the comparator to settle.
2
state time = XTAL1
The converter is ratiometric, so the absolute accuracy is directly dependent on the accuracy and stability
of VREF. VREF must be close to Vee since it supplies
both the resistor ladder and the digital section of the
converter.
The table below shows two different clock speeds
See the MCS-96 AID Converter Quick Reference
and their corresponding AID conversion and sample
for definition of AID terms.
times.
Example Sample and Conversion Times
Sample Time
at Clock
Speed
(p.s)
Conversion
Time
(States)
15
1.875
156.5
19.6
8
2.667
89.5
29.8
AID Clock
Prescaler
Clock Speed
(MHz)
Sample Time
(States)
IOC2.4 = 0 -- ON
16
IOC2.4 = 1 -- OFF
6
Conversion
Time at
Clock Speed
(p.s)
AID CONVERTER SPECIFICATIONS
Parameter
Typical(1)
Minimum
Maximum
Units·
1024
10
1024
10
Levels
Bits
0
±3
LSBs
Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity Error
0.25 ±0.50
LSBs
-0.25 ±0.50
LSBs
1.5 ±2.5
Differential Non-Linearity Error
0
±3
LSBs
>-1
+2
LSBs
0
±1
LSBs
Channel-to-Channel Matching
±0.1
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBrC
LSBrC
LSBrC
-60
Off Isolation
dB
Notes
2,3
Feedthrough
-60
dB
2
Vee Power Supply Rejection
-60
dB
2
4
Input Series Resistance
DC Input Leakage
Sampling Capacitor
750
1.2K
n
0
3.0
p.A
3
pF
NOTES:
"An "LSB", as used here, has a value of approximately 5 mY.
1. Typical values are expected for most devices at 25°e.
2. De to 100 KHz.
3. Multiplexer Break-Before·Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
16-54
infel·
8XC196KB/8XC196KB16
EPROM SPECIFICATIONS
EPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
TA
Ambient Temperature During Programming
20
30
C
Vee. VPD. VREF(1)
Supply Voltages During Programming
4.5
5.5
VEA
Programming Mode Supply Voltage
12.50
13.0
V
V(2)
Vpp
EPROM Programming Supply Voltage
12.50
13.0
V(2)
Vss. ANGND(3)
Digital and Analog Ground
0
0
V
Fose
Oscillator Frequency 12 MHz
6.0
12.0
MHz
Fosc
Oscillator Frequency 16 MHz
6.0
16.0
MHz
NOTES:
1. Vee. VPD and VREF should nominally be at the same voltage during programming.
2. VEA and Vpp must never exceed the maximum voltage for any amount of time or the device may be damaged.
3. Vss and ANGND should nominally be at the same voltage (OV) during programming.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description .
Min
Max
Units
TSHLL
Reset High.to First PALE Low
TLLLH
PALE Pulse Width
40
Tose
TAVLL
Address Setup Time
0
Tose
TLLAX
Address Hold Time
50
TLLVL
PALE Low to PVER Low
60
Tose
TpLDV
PROG Low to Word Dump Valid
50
Tose
TpHDX
Word Dump Data Hold
50
Tose
TDVPL
Data Setup Time
0
Tose
TpLDX
Data Hold Time
50
Tose
TpLPH
PROG Pulse Width
40
Tose
TpHLL
PROG High to Next PALE Low
120
Tose
TLHPL
PALE High to PROG Low
220
Tose
TpHPL
PROG High to Next PROG Low
120
Tose
TpHIL
PROG High to AINC Low
0
Tose
TILIH
AINC Pulse Width
40
Tose
TILVH
PVER Hold after AINC Low
50
Tose
TILPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Low
1100
Tose
Tose
Tose
90
16-55
Tosc
8XC196KB/8XC196KB16
DC EPROM PROGRAMMING CHARACTERISTICS
Description
Vpp Supply Current (When Programming)
NOTE:
Do not apply Vpp until Vee is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
PORTS
ADDR/COMMAND
3/4
PVER
270909-15
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
--J
PORTS
3/4
"-
I--- TSHLL
ADDR/COMMAND
I
"-
J
-
t-
TpLDV -
\
T1LPL
ADriR
L
~VER
<:VER BITS/WD DUMP )
-
,
-
TpHDX
I-
II
~
ADDR + 2
BITS/WD DUMP
r-tTPLDV -
\
~
TpHDX
'+-
II
TpHPL -
\
270909-16
16·56
8XC196KB/8XC196KB16
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
RESET
J
PORTS
----«ADDR/COMMAND>--<....~DA~T~A...J)~-------«
ADDR
3/4
ADDR+ 2
DATA
>--
PALE
PROG
PVER
AINC
270909-17
AC CHARACTERISTIC5-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol
Parameter
Min
Max
Units
TXLXL
Serial Port Clock Period (BRR ~ 8002H)
TXLXH
Serial Port Clock Falling Edge to'Rising Edge (BRR ~ 8002H) 4 Tose - 50 4 Tose + 50
ns
TXLXL
Serial Port Clock Period (BRR = 8001 H)
ns
TXLXH
Serial Port Clock Falling Edge to Rising Edge (BRR = 8001 H) 2 Tose - 50 2 Tose + 50
ns
TOVXH
Output Data Setup to Clock Rising Edge
2 Tose -50
ns
TXHOX
Output Data Hold after Clock Rising Edge
2 Tose -50
ns
TXHOV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold after Clock Rising Edge
TXHOZ
Last Clock Rising to Output Float
ns
STose
4 Tose
2 Tose +50
Tose +50
ns
0
ns
2 Tose
1S-57
ns
ns
II
intel·
8XC196KB/8XC196KB 16
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
270909-18
instruction. Use another long word register and set it
equal to zero. See tech bit MC0692.
FUNCTIONAL DEVIATIONS
Devices marked with an "E", "F"or "G" have the
following errata.
REVISION HISTORY
1. High Speed Inputs
The High Speed Input (HSI) has three deviations
from the specifications.
NOTE:
"Events" are defined as one or more pin transitions. "Entries" are defined as the recording of
one or more events.
A. The resolution is nine states instead of eight
states. Events occurring on the same pin more
frequently than once every nine state may be
lost.
B. A mismatch between the nine state HSI resolution and the eight state hardware timer .causes
one time-tag value to be skipped every nine timer
counts. Events may receive a time-tag one count
later than expected.
C. If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register,
leaving the FIFO empty again. The next event
that occurs will be the first event loaded into the
empty FIFO. If the first two events into an empty
FIFO (not counting the Holding Register) occur
coincident with each other, both are recorded as
one entry with one time-tag. If the second event
occurs within 9 states after the first, the events
will be entered separately with time-tags at least
one count apart. If the second event enters the
FIFO coincident with the "skipped" time-tag situation (see B above) the time-tags will be at least
two counts apart.
This data sheet (270909-004) is valid for devices
with an "E", "F" or "G" at the end of the top side
tracking number. Data sheets are changed as new
device information becomes available. Verify with
your local Intel sales office that you have the latest
version before finalizing a design or ordering devices.
The following differences exist between this data
sheet (270909-004) and (270909-003):
1. The
ROM
(80C196KB),
and
ROMless
(83C196KB) were combined with this data sheet
resulting in no specification differences.
2. The description of the prescalar bit for the AID
has been enhanced.
3. THAHBVMIN was -15 ns (270909-003). Now
THAHBVMIN is -20 ns (270909-004).
4. TXHQZMAX was 1 TOSC (270909-003). Now
TXHQzMAX is 2 TOSC (270909-004). This should
have no impact on designs uSing synchronous
'serial mode O.
5: The change indicators for the 80C196KB are
"E", "F" and "G". Previously there was only one
change indicator "E". The change indicator is
used for tracking purposes. The change indicator
is the last character in the FPO number. The FPO
number is the second line on the top side of the
device.
.
The following differences exist between (-003) and
version (-002).
2. CMPL with RO
Using CMPL with register 0 can set incorrect flags.
Don't use register 0 with the compare long (CMPL)
16-58
1. The 12 MHz and 16 MHz devices were combined in this data sheet. The 87C196KB 12 MHz
only data sheet (272035-001) is now obsolete.
int:eL
8XC196KB/8XC196KB 16
2. Changes were made to the format of the data
sheet and the SFR descriptions were removed.
3. Added IIH1.
4. Changed TCHWH Min from - 10 ns to - 5 ns.
3. The -002 version of this data sheet was valid for
devices marked with a "8" or a "D" at the end
of the top side tracking number.
5. Changed TCHWH Max from
4. The OSCILLATOR errata was removed.
5. An errata was not documented in the -002 data
sheet for devices marked with a "8" or a "D".
This is the DIVIDE DURING HOLD/READY errata. When HOLD or READY is active and DIV/
DIV8 is the last instruction in the queue, the divide result may be incorrect.
6. TXCH was changed from Min
20 ns.
= 40 ns to Min =
7. T RLCL was changed from Min = 5 ns to Min =
4 ns.
9. IIL1 was changed from Max
-7 mAo
20 ns to
7. Changed T WHQX Min from TOSC
Tosc - 15 ns.
10 ns to
8. Changed TWHLH Min from TOSC
Tosc - 15 ns.
10 ns to
9. Changed TWHLH Max from TOSC + 15 ns to
Tosc + 10 ns.
10 ns to
10. Changed TWHBX Min from TOSC
Tosc - 15 ns.
11. Changed T HVCH Min from 85 ns to 55 ns.
12. Remove T HVCH Max.
= -6 mA to Max =
10. T HAHBV was changed from Min
Min = -15 ns.
+ 10 ns to + 15 ns.
6. Changed T WLWH Min from TOSC
Tosc - 15 ns.
13. Changed TCLHAL Min from - 10 ns to - 15 ns.
= -10 ns to
14. Changed T CLHAL Max from 20 ns to 15 ns.
15. Changed TCLBRL Min from - 10 ns to - 15 ns.
16. Changed T CLBRL Max from 20 ns to 15 ns.
Differences between the -002 and -001 data sheets.
17. Changed T HAHAX Min from - 10 ns to - 15 ns.
1. The -001 version of this data sheet was valid for
devices marked with a "C" at the end of the top
side tracking number.
18. Added HSI description to Functional Deviations.
2. Added 64L SDIP and 80L QFP packages.
19. Added Oscillator description to Functional Deviations.
111
16-59
8XC198
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
8 Kbytes of OTPROM
•
•
•
•
•
•
•
•
•
8 Kbytes of On-Chip OTPROM or ROM
232 Byte Register File
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
1.75 Ils 16 x 16 Multiply (16 MHz)
3.0 Ils 32/16 Divide (16 MHz)
Powerdown and Idle Modes
·16-Bit Watchdog Timer
8-Bit External Bus
•
•
•
•
•
•
•
•
•
16 MHz Standard
Full Duplex Serial Port
High Speed 1/0 Subsystem
16-Bit Timer
16-Bit Counter
Pulse-Width-Modulated Output
Four 16-Bit Software Timers
10-Bit A/D Converter with Sample/Hold
Extended Temperature Available
The 8XC198 family offers low-cost entry into Intel's powerful MCS®-96 16-bit microcontroller architecture.
Intel's CHMOS process provides a high performance processor along with low power consumption. To further
reduce power requirements, the processor can be placed into Idle or Powerdown Mode.
The 8XC198 is the 8-bit bus version of the 8XC196KB. The prefixes mean: 80 (ROMless), 83 (ROM), 87 (OTP)
One Time Programmable. The ROM and OTP are available in 8 Kbytes.
.
Bit, byte, word and some 32-bit operations are available on the 8XC198. With a 16 MHz oscillator a 1(3-bit
addition takes 0.50 p.s, and the instruction times average 0.37 P.s to 1.1 p.s in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or counter. Also provided on-chip are an AID
converter, serial port, watchdog timer and a pulse-width-modulated output signal.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of DoC to + 70°C. Wth the extended temperature range option, operational characteristics are
guaranteed over the temperature range of - 40°C to + 85°C.
MCS®-96 is a registered trademark of Intel Corporation.
16-60
October 1992
Order Number: 272034-003
intet
8XC198
VREF
ANGND
CONTROL
SIGNALS
l ~~f:
BUS
---rv
PORT 4
272034-1
Figure 1. 87C198 Block Diagram
OFFFFH
CHIP CONFIGURATION REGISTER
EXTERNAL MEMORY OR 1/0
4000H
POWERDOWN MODE ENABLE
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
SET TO 0
2080H
RESERVEO
SET TO 0
2040H
UPPER 8 INTERRUPT VECTORS
' - - - - - ADDRESS VALID STROBE SELECT
(ALE / Ai5V)
2030H
ROMIOTP SECURITY KEY
2020H
(IRCO) }INTERNAL READY CONTROL
....._ _ _ _ (IRC1)
MODE
RESERVED
2019H
CHIP CONFIGURATION BYTE
(LOCO) }
'--_ _ _ _ _ _ _ (LOC 1) PROGRAM LOCK MODE
2018H
RESERVED
2014H
272034-7
LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
Figure 3. Chip Configuration (2018H)
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY OR 1/0
0100H
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY
OOOOH
Figure 2. Memory Map
WARNING:
Reserved memory locations must not be written or read. The contents and! or function of these locations may change with
future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly.
16-61
inteL
8XC198
PACKAGING
The 8XC198 is available in a 52-pin PLCC package and an 80-pin QFP package. Contact your local sales
office to determine the exact ordering code for the part desired.
Package Designators:
N = 52-pin PLCC
S = BO-pin QFP
Thermal Characteristics
Package Type
°Ja
°Je
PLCC
40·C/W
QFP
70·C/W
4·C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See the Intel Packaging Handbook (Order Number
240800) for a description of Intel's thermal impedance test methodology.
'"cW '"L.Jc
o 0
'"a.. '"a..
"- "o..... '"0
a..
o
~
a..
a..
~
a..
"- ".....
'"
:r: :r:
~ ~ 1L:5
~
"o "~
... c...
c
ACH5/PO.5/PIAOOE. 1
AD2/P3.2
ACH4/PO.4/PIAODE.O
AD3/P3.3
ANGNO
AD4/P3.4
VREF
AD5/P3.5
infel®
Vss
EXTINT/P2.2/PROG
RESET
AD6/P3.6
AD7/P3.7
A8/P4.0
RXO/P2.1!PALE
TOP VIEW
A9/P4.1
TXO/P2.0/PVER
87C198
Al0/P4.2
HSI.O/SID.O
A 11/P4.3
HSI. 1/SIO. 1
A12/P4.4
HSO.4/HSI.2/SID.2
A 13/P4.5
HSO.5/HSI.3/SIO.3
A14/P4.6
0
'" "''''
'" .
:r: :r:
:r:
0 0 >
0
(I)
(I)
(I)
0
(I)
:r:
'"
'"
>
a..
a.. on•
'"
a..
>
"-
'"a..
~
I~
.....
~ ......'" "-N'" "-...
>c
a..
".
N
a..
"I(I)
'"'"
I-
'"<.>
'"
..J
a..
on
:;;:
I-
272034-2
Figure 4. 52-Pin PLCC Package
NOTE:
The above pinout diagram applies to the OTP (B7C19B) device. The OTP device uses all of the programming pins shown
above. The ROM (83C19B) device only uses programming pins: AINC, PALE, PMODE.n and PROG. The ROMless (BOC19B)
doesn't use any of the programming pins.
16-62
intel .
8XC198
N
...;
n.
......
N
0
,..,
...
...
'" ,..,
",0
0
0
. . . . .... .,.., .....'" "..
N
on
...; ...; ...;
n. n. n.
...... ...... ......
on
"n.
......
"«
...;
'" ...;
n.
......
<.:> '"
<.:>
0
« > « « « > «
0
,..,
0
on
n.
n.
n.
n. n.
......
......
......
...... ...... ......
0
N
on
......
......
C
C
0 0 0 C C c
n.
n.
n.
« « « « « « « «
T2CLK/P2.3
AD1/P3.1
ADO/P3.0
VSS
RD#
READY
ALE
T2RST /P2.4/ AINC
INST
N.C.
VSS
WR
N.C.
PWM/P2.5
XTAL2
N.C.
XTAL 1
Vpp
VSS
VSS
INTEL
87C198
80-PIN OFP
VSS
Vee
Vee
IT
VSS
HSO.3
Vee
VSS
TOP VIEW
VSS
HSO.2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
HSO.l
ACH6/PO.6/PMODE.2
HSO.O
ACH7 /PO. 7/PMODE.3
N.C.
HSO.5/HSI.3/SID.3
ACHS/PO.5/PMODE. 1
VSS
ACH4/PO.4/PMODE.O
HSO.4/HSI.2/SID.2
c
z
"«z
'" '" I"
... '"
>0::.
>
0
D:::
n.
......
N
N
<.:> ...
<.:> ...
>
...
VI
'"
n.
;:::.
Z
;::
...x
u u u u u
~~
'"
ci ci
>'"
:Z :Z :Z :Z :Z Vi
Vi
......
N N
n.
Vi
Vi ::t:
~
0
n.
......
......
C
C
0
......
~
::t:
x x
'" ...
272034-4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 5. SO-Pin QFP Package
NOTE:
The above pinout diagram applies to the OTP (67C196) device. The OTP device uses all of the programming pins shown
above. The ROM (63C196) device only uses programming pins: AINC, PALE, PMODE.n and PROG. The ROMless (60C196)
doesn't use any of the programming pins.
16-63
III
8XC198
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
The PLGG package has 5 Vss pins and the QFP package has 12 Vss pins. All must be
connected to digital ground.
VREF
Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the
analog portion of the AID converter and the logic used to read Port O. Must be·
connected for A/D and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential
asVss·
Vpp
Programming Voltage. Also, timing pin for the return from powerdown circuit.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
RESET
Reset input to and open-drain output from the chip. Input low for at least 4 state times to
reset the chip. The subsequent low-to-high transition commences the 10-state Reset
Sequence.
INST
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.
EA
Input for memory select (External Access). EA equal to a TIL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TIL-low causes accesses to these locations to be directed to off-chip
memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by GGA. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory
reads.
WR
Write output to external memory. WR will go low for every external write.
READY
Ready input to lengthen external memory cycles. When the external memory is not
being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle held not ready is available through configuration of GGR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the
HSI Unit.
Port 0
4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on
the EPROM device.
16-64
8XC198
PIN DESCRIPTIONS (Continued)
Symbol
NCime and Function
Port 2
Multi-functional port. All of its pins are shared with other functions in the 80C198.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with
the multiplexed address/data bus which has strong internal pullups. Available as
I/O only on the ROM and EPROM devices.
TxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In mode 0 the
pin is used as the serial clock output.
RxD
Serial Port Receive pin used for serial port reception. In mode 0 the pin functions
as input or output data.
EXTINT
A positive transition on the EXTINT pin will generate an external interrupt.
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator
input.
T2RST
A rising edge on the T2RST pin will reset Timer2.
PWM
The PWM output.
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the
part is operating.
SID
Slave 10 Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE
Programming ALE Input. Accepted by the 87C196KB when it is in Slave
Programming Mode. Used to indicate that Ports 3 and 4 contain a command/
address.
PROG
Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
PVAL
Program Valid. This signal indicates the success or failure of programming in the
Auto Programming Mode. A zero indicates successful programming.
PVER
Program Verification. Used in Slave Programming and Auto CLB Programming
Modes. Signal is low after rising edge of PROG if the programming was not
successful.
AINC
Auto Increment. Active low signal indicates that the auto increment mode is
enabled. Auto Increment will allow reading or writing of sequential EPROM
locations without address transactions across the PBUS for each read or write.
PORTS 3 and 4
(when programming)
Address/Command/Data Bus. Used to pass commands, addresses, and data to
and from slave mode 87C196KBs. Used by chips in Auto Programming Mode to
pass command, addresses and data to slaves. Also used in the Auto Programming
Mode as a regular system bus to access external memory. Should have pullups to
VcC<15 kfi).
16-65
8XC198
ELECTRICAL CHARACTERISTICS
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
under Bias .................. -.55°C to + 125°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These .are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature .......... - 65°C to, + 150°C
Voltage on Vpp or EA to
VssorANGND .............. -0.3Vto +13.0V
Voltage on Any Other Pin to VSS .. - 0.5V to + 7.0V
Power Dissipation(1) ....................... 1.5W
NOTE:
1. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias
0
+70
°C
V
Vee
Digital Supply Voltage
4.50
5.50
VREF
Analog Supply Voltage
4.50
5.50
V
Fose
Oscillator Frequency 16 MHz
3.5
16
MHz
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
Description
Min
Max
Units
-0.5
0.8
V
VIL
Input Low Voltage
VIH
Input High Voltage (1)
0.2 Vee + 0.9
Vee + 0.5
V
VIH1
Input High Voltage on XTAL 1
0.7 Vee
Vee + 0.5
V
VIH2
Input High Voltage on RESET
2.6
Vee + 0.5
V
VOL
Output Low Voltage
0.3
0.45
V
V
V
VOH
Output High Voltage
(Standard Outputs)
III
Input Leakage Current (Std. Inputs)
±10
ILl1
Input Leakage Current (Port 0)
11L1
Logical 0 Input Current in Reset
(ALE, RD, INST)
Hyst
Hysteresis on RESET Pin
Hi
V
V
V
Vee - 0.3
Vee - 0.7
Vee- 1.5
300
NOTE:
1. All pins except RESET and XTAL1.
16-66
Test Conditions
= 200 p,A
= 32 mA
= 7mA
IOH = -200p,A
IOH = -3.2 mA
IOH = -7mA
IOL
IOL
IOL
p,A
o<
+3
p,A
0< VIN < VREF
-6
mA
VIN
mV
VIN < Vee - 0.3V
= 0.45 V
inteL
8XC198
DC CHARACTERISTiCS (Continued)
Symbol
Description
Min
Typ(6)
Max
Units
Test Conditions
60
rnA
XTAL1 = 16 MHz
Vcc = Vpp = VREF = 5.5V
Icc
Active Mode Current in Reset
50
IREF
AID Converter Reference Current
2
5
rnA
IIDLE
Idle Mode Current
10
25
rnA
rnA
XTAL1 =3.5 MHz
/LA
Vcc = Vpp = VREF = 5.5V
ICC1
Active Mode Current
15
25
Ipo
Powerdown Mode Current
5
30
RRST
Reset Pullup Resistor
Cs
Pin Capacitance (Any Pin to VSS)
6K
50K
n
10
pF
FTEST = 1.0 MHz
NOTES:
(Notes apply to all specifications)
1. Standard Outputs include ADO-15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXO/P2.0 and
RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
2. Standard Inputs include HSI pins, EA, READY, RXO/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on Standard Output pins: 10 mA
4. Maximum current per bus pin (data and control) during normal operation is ± 3.2 mA.
5. During normal (non-transient) conditions the following total current limits apply:
HSO, P2.0, RXD, RESET
IOL: 29 mA
IOH: 26 mA
P2.5, WR
IOL: 13 mA
IOH: 11 mA
ADO-AD15
IOL: 52 mA
IOH: 52 mA
RD, ALE, INST
IOL: 13 mA
IOH: 13 mA
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.
60~----~-------r------~----~
50~----~-------+------~~--~
40r------+-------t~~~~~--_4
Icc
mA
..
30~-----+~~---b~----+-----~
20~-----+~~---r----~~~--~
ICC Max = 3.88 x FREQ + 8.43
IIDLE Max = 1.65 x FREQ + 2.2
fREQUENCY
Figure 8.
Icc and IIDLE vs Frequency
16-67
272034-22
intel~
8XC198
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
=
=
12/16 MHz
Max
Units
Notes
2 TOSG - 75
ns
100 pF, Rise and fall times
=
10 ns, FOSG
The system must meet these specifications to work with the 87C198:
Symbol
Description
TAVYV
Address Valid to Ready Setup
TYLYH
Non READY Time
TLLYX
READY Hold after ALE Low
TAVDV
Address Valid to Input Data Valid
TRLDV
RD Active to Input Data Valid
TRHDZ
End of RD to Input Data Float
TRXDX
Data Hold after RD Inactive
Min
No upper limit
TOSG - 15
0
NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2 Tosc x n, where n = number of wait states.
16-68
2 TOSG - 40
ns
ns
(Note 1)
3 TOSG - 55
ns
(Note 2)
TOSG - 23
ns
(Note 2)
TOSG - 20
ns
ns
8XC198
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
=
100 pF, Rise and fall times
=
=
12/16 MHz
Units
Notes
10 ns, Fose
The 87C198 will meet these specifications:
Symbol
Description
Min
Max
FXTAL
Frequency on XTAL1 12 MHz
3.5
12
MHz
(Note 1)
FXTAL
Frequency on XTAL1 16 MHz
3.5
16
MHz
(Note 1)
Tose
1IFXTAL 12 MHz
83.3
286
ns
Tose
1IFxTAL 16 MHz
62.5
286
ns
hHLH
ALE Cycle Time
hHLL
ALE High Period
Tose - 10
TAVLL
Address Setup to ALE Falling Edge
Tose - 20
TLLAX
Address Hold after ALE Falling Edge
Tose - 40
ns
TLLRL
ALE Falling Edge to RD Falling Edge
Tose - 35
ns
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
ns
4 Tose
Tose - 5
Tose
Tose+ 10
(Note 3)
ns
ns
Tose + 25
ns
(Note 3)
Tose + 25
ns
(Note 2)
5
ns
TRLAZ
RD Low to Address Float
hLWL
ALE Failing Edge to WR Falling Edge
Tose - 10
ns
TOVWH
Data Stable to WR Rising Edge
Tose - 23
ns
(Note 3)
TWLWH
WR Low Period
Tose - 15
Tose + 5
ns
(Note 3)
Tose + 10
TWHOX
Data Hold after WR Rising Edge
Tose - 15
ns
TWHLH
WR Rising Edge to ALE Rising Edge
Tose - 15
ns
TWHBX
INST Hold after WR Rising Edge
Tose - 15
ns
hLBX
INST Hold after ALE Rising Edge
Tose - 10
ns
TRHBX
INST Hold after RD Rising Edge
Tose - 10
ns
TWHAX
AD8-15 HoldafterWR Rising Edge
Tose - 30
ns
TRHAX
AD8-15 Hold after RD Rising Edge
Tose - 25
ns
NOTES:
1. Testing performed at 3.5 MHz. How!3ver, the part is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. When using wait states, add 2 Tesc x n, where n = number of wait states.
16-69
(Note 2)
infel .
8XC198
System Bus Timings
XTALI
ALE
BUS
WRITE
BUS
-<
I
BHE,INST
VALID
I
A8-IS
ADDRESS OUT
272034-23
16-70
8XC198
READY Timings (One Wait State)
XTAL1
ALE
READY
--+--------"'1. ...
f-----
TRLRH + 2Tose
--I
1----- TRLDV + 2 Tose
1 - - - - - - - - - - TAVDV + 2Tose ----~-~
~--A-DD-RES-S-OU-T---}~------------~(~DA-TA-)~»~»m»~-------
1
"'"":f_ol-':::::-TQ-VW-H-+-2-To-se-~
_+_______.......~f-o.>----
I
TWLWH + 2 Tose
~:::::AD:D:R:ES:S:O:UT::::::~~(~_____D_A_TA_OU_T_____J)(~__A_D_DR_E_SS__
I
272034-24
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TxLXL
Oscillator Frequency 12 MHz
3.5
12.0
MHz
1/TxLXL
Oscillator Frequency 16 MHz
3.5
16.0
MHz
TXLXL
Oscillator Period 12 MHz
83.3
286
ns
TXLXL
Oscillator Period 16 MHz
62.5
286
ns
TXHXX
High Time
21.25
TXLXX
Low Time
21.25
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272034-25
An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.
16-71
•
intele
8XC198
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
Cl
Vss
11~1-"""~--IXTAL1
~
4.7K"
87C198
EXTERNAL
CLOCK INPUT
XTAL2
clock driver
no connect
Quartz Crystal or
C.ramlc R.sonator
272034-32
AC TESTING INPUT, OUTPUT WAVEFORMS
0.45
<
- - " O.B
2.0
O.B
87C198
XTAL2
272034-33
NOTE:
Keep oscillator components close to chip and use
short direct traces to XTAL 1, XTAL2 and Vss. When
using crystals, C1 = 20 pF, C2 = 20 pF. When using
ceramic resonators consult manufacturer for recommended capacitor values.
2.4~ 2.0> TEST POINTS
r--------t
>4:>-+---1 XTAL 1
NOTE:
"Required if open collector TTL driver used. Not needed if CMOS driver is used.
FLOAT WAVEFORMS
V
A-
272034-26
AC Testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0".
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded VOHIVOL Level occurs
IOL"OH = ± 15 mA.
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
- High
A
L
- Low
D
DATA IN
V
- Valid
L
- ALE/ADV
X
- No Longer.Valid
Q
Z
- Floating
R
- RD
W
- WR
X
- XTAL1
Y
- READY
16-72
- Address
DATA OUT
8XC198
State times are calculated as follows:
10-81T AID CHARACTERISTICS
At a clock speed of 6 MHz or less, the clock prescaler should be disabled. This is accomplished by setting IOC2.4 = 1.
state time = _2_
IXTAL1
At higher frequencies (greater than 6 MHz) the clock
prescaler should be turned on (IOC2.4 = 0) to allow
the comparator to settle.
The converter is ratiometric, so the absolute accuracy is directly dependent on the accuracy and stability
of VREF. VREF must be close to Vee since it supplies
both the resistor ladder and the digital section of the
converter.
The table below shows two different clock speeds
and their corresponding AID conversion and sample
times.
See the MCS-96 AID Converter Quick Reference
for definition of AID terms.
Example Sample and Conversion Times
Sample Time
at Clock
Speed (,...s)
Conversion
Time
(States)
15
1.875
156.5
19.6
8
2.667
89.5
29.8
AID Clock
Prescaler
Clock Speed
(MHz)
Sample Time
(States)
IOC2.4 = 0 --.. ON
16
IOC2.4 = 1 --.. OFF
6
Conversion
Time at Clock
Speed (,...s)
AID CONVERTER SPECIFICATIONS
Parameter
Typlcal(1)
Minimum
Maximum
Units'
1024
10
1024
10
Levels
Bits
0
±3
LSBs
Resolution
Absolute Error
Full Scaie Error
Zero Offset Error
Non-Linearity Error
0.25 ±0.50
LSBs
-0.25 ±0.50
LSBs
1.5 ±2.5
Differential Non-Linearity Error
0
±3
>-1
+2
LSBs
0
±1
LSBs
LSBs
Channel-to-Channel Matching
±0.1
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBI"C
LSBI"C
LSBI"C
-60
Off Isolation
Feedthrough
-60
Vee Power Supply Rejection
-60
Notes
Input Series Resistance
DC Input Leakage
750
1.2K
0
3.0
dB
2,3
dB
2
dB
2
n
4
,...A
Sample Time: Prescaler On
Prescaler Off
15
8
States
States
Sampling Capacitor
3
pF
NOTES:
'An "LSB", as used here, has a value 01 approximately 5 mV.
1. Typical values are expected lor most devices at 25'C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Belore-Make Guaranteed.
4. Resistance Irom device pin, through internal MUX, to sample capaCitor.
16-73
•
8XC198
EPROM SPECIFICATIONS
EPROM PROGRAMMING OPERATING CONDITIONS
Parameter·
Min
Max
TA
Symbol
Ambient Temperature during Programming
20
30
Vee. VPD. VREF(l)
Supply Voltages during Programming
4.5
5.5
VEA
Vpp
PrQgramming Mode Supply Voltage
12.50
13.0
V
V(2)
EPROM Programming Supply Voltage
12.50
13.0
V(2)
0
0
V
6.0
16.0
MHz
·Vss.
ANGND(3)
Fose
Digital and Analog Ground
Oscillator Frequency 16 MHz
Units
DC
NOTES:
1. Vee. VPD arid VREF should nominally be at the same voltage during programming.
2. VEA and Vpp must never exceed the maximum voltage for any amount of time or the device may be damaged.
3. Vss and ANGND should nominally be at the same voltage (OV) during programming.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
Units
TSHLL
Reset High to First PALE Low
TLLLH
PALE Pulse Width
40
Tose
TAVLL
Address Setup Time
0
Tose
50
TLLAX
Address Hold Time
lLLVL
TpLDV
PALE Low to PVER Low
1100
Tose
Tose
Tose
PROG Low to Word Dump Valid
60
50·
TpHDX
Word Dump Data Hold
50
Tose
TDVPL
Data Setup Time
0
Tose.
TpLDX
Data Hold Time
50
Tose
TpLPH
PROG Pulse Width
40
Tose
TpHLL
PROG High to Next PALE Low
120
Tose
lLHPL
TpHPL
PALE High to i5'FiOO Low
220
Tose
PROG High to Next P'RC5G Low
120
Tose
TpHIL
i5'FiOO High to AINC Low
0
Tose
TILIH
AINC Pulse Width
40
Tose
TILVH
PVER Hold after AiNC Low
50
Tose
TILPL
AINC Low to PROG Low
170
TpHVL
PRO'G High to PVER Low
Tose
90
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description.
Ipp
Vpp Supply Current (When Programming)
16-74
Tose
Tose
intel.
8XC198
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
---'
j
I;TAVLL"
PORTS
"
3/~
f+--
ADDR/COt.4t.4AND"'
TSHLL
TLLAX -
DATA
,
TDVPL .. TpLDX "
\
I
I--
"' ~ ADDR/COt.4t.4AND
TLLLH - -
I-
,
_
TLHPL --
TpLPH
-00
.. TpHLL ..
I
.....
i+" TLLVL
\
PVER
i+-- TpHVL 272034-28
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
--i
I
PORTS
ADDR/COt.4t.4AND
3/4
"'
I - - TSHLL -
~
TpLDV -
\
,
T1LPL
ADDR
I
VER BITS/WD DUMP
I---
.....
TpHDX
-I-
I-
\
If
~
ADDR+2
VER BITS/WD DUMP
TpHDX
TpLDV --
-
-
II
I
TpHPL -
~
272034-29
16-75
intel~
8XC198
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
PORTS
3/4
-----«
ADDR/CO~~AND
>---<
ADDR
DATA
ADDR+ 2
)>---------«
DATA
>--
272034-30
16-76
int'eL
8XC198
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol
Parameter
Min
~
8002H)
Max
Units
TXLXL
Serial Port Clock Period (BRR
ns
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR ~ 8002H)
TXLXL
Serial Port Clock Period (BRR = 8001 H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)
2 Tosc - 50
TQVXH
Output Data Setup to Clock Rising Edge
2 Tosc - 50
ns
TXHQX
Output Data Hold after Clock Rising Edge
2 Tosc - 50
ns
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold after Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
6 Tosc
4Tosc-5O
4 Tosc
+ 50
2 Tosc
+ 50
ns
4 Tosc
2 Tosc
Tosc
ns
+ 50
+ 50
ns
ns
ns
0
ns
2 Tosc
ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
TXO···U
TQVXH-j
I-
RXD
(OUT)
RXD
(IN)
272034-31
'-------:-------------'
16-77
II
I
intel .
8XC198
FUNCTIONAL DEVIATIONS
REVISION HISTORY
Devices marked with an "E", "F", or "G" have the
following errata.
This data sheet (272034·003) is valid for devices
marked with an "E", "F", or "G" at the end of the
top side tracking number. Data sheets are changed
as new device information becomes available. Verify
with your local Intel sales office that you have the
latest version before finalizing a design or ordering
devices.
1. HIGH SPEED INPUTS
The High Speed Input (HSI) has three deviations
from the specifications.
NOTE:
"Events" are defined as one or more pin transitions. "Entries" are defined as the recording of
one or more events.
The following differences exist between this data
sheet and the previous version (-002).
A. The resolution is nine states instead of eight
states. Events occurring on the same pin more
frequently than once every nine states may be
lost.
2. The description of the AID converter prescalar
bit was improved.
1. This data sheet added the ROMless and ROM
devices 80C198 and 83C198 respectively.
B. A mismatch between the nine state HSI resolution and the eight state hardware timer causes
one time-tag value to be skipped every nine timer
counts. Events may receive a time· tag one count
later than expected.
C. If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register,
leaving the FIFO empty again. The next event
that occurs will be the first event loaded into the
empty FIFO. If the first two events into an empty
FIFO (not counting· the Holding Register)""Oc"CUr
coincident with each other, both are recorded as
one entry with one time·tag. If the second event
occurs within 9 states after the first, the events
will be entered separately with time-tags at least
one count apart. If the second event enters the
FIFO coincident with the "skipped" time·tag situ·
ation (see B above) the time-tags will be at least
two counts apart.
2. CMPL with RO
Using CMPL with register 0 can set incorrect flags.
Don't use register 0 with the compare long instruction. Use another long word register and set it equal
to zero. See Techbit MC0692.
16-78
8XC 196KC Data Sheet
17
8XC196KC
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
•
•
•
•
•
•
•
•
•
•
•
•
87C196KC-16 Kbytes of On-Chip EPROM
80C196KC-ROMless
16 MHz Operation
Dynamically Configurable a-Bit or
16-Bit Buswidth
232 Byte Register File
Full
Duplex Serial Port
256 Bytes of Additional RAM
•
•
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
1.75 fLs 16 x 16 Multiply (16 MHz)
3.0 fLs 32/16 Divide (16 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
16-Bit Watchdog Timer
Extended Temperature Available
Speed I/O Subsystem
• High
i6-Sit Timer
Up/Down Counter with Capture
• 316-Bit
Pulse-Width-Modulated Outputs
• Four i6-Bit Software Timers
iii
III
•
.
•
8- or 10-Bit AID Converter with
Sample/Hold
HOLD/HLDA Bus Protocol
OTP One-Time Programmable Version
The 80C196KC 16·bit microcontroller is a high performance member of the MCS®-96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 MHz operation and an optional
16 Kbytes of ROM/EPROM. Intel's CHMOS IV process provides a high performance processor along with low
power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip EPROM. In this document, the 80C196KC will refer to
all products unless otherwise stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of O°C to + 70°C. With the extended (Express) temperature range option, operational characteristics are guaranteed over the temperature range of - 40°C to + 85°C. Unless otherwise noted, the specifications are the same for both options.
See the Packaging information for extended temperature designators.
II
MCS®-96 is a registered trademark of Intel Corporation.
17-1
November 1991
Order Number: 270942·002
8XC196KC
VREf
ANGND
CONTROL
SIGNALS
PORT 3
} ~2~:
BUS
PORT -4
1+--01-r;;;;;;;::1-..,....-I-.
L.;~.;J----II-.
PWMl
PWM2
HSO
270942-1
Figure 1. 80C196KC Block Diagram
OFFFFH
EXTERNAL MEMORY OR 110
6000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
2080H
RESERVED
PTSVECTORS
205EH
2040H
UPPER INTERRUPT VECTORS
2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE 0
20l8H
RESERVED
20l4H
LOWER INTERRUPT VECTORS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY
200H
ADDITIONAL RAM
100H
REGISTER FILE AND
EXTERNAL PROGRAM MEMORY
Figure 2. Memory Map
17-2
o
intel~
8)(C196KC
Process Information
This device is manufactured on PX29.5, a CHMOS IV process. Additional process and reliability information is
available in Intel's Components Quality and ReliabJ7ity Handbook, order number 210997.
Table 1. Prefix Identification
Device
Commercial
QFP
Commercial
PLCC
Express
PLCC
BOC196KC
SBOC196KC
NBOC196KC
TNBOC196KC
B7C196KC
SB7C196KC'
NB7C196KC'
TNB7C196KC'
'OTP Version
Package Designators: N = 68-pin PLCC, S = 80-pin QFP
Prefix Designators: T = Extended Temperature
Table 2. Thermal Characteristics
Package
Type
°ja
°jc
PLCC
35°C/W
13°C/W
QFP
42°C/W
-
All thermal data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and applications. See the Intel Packaging Handbook (Order Number 240BOO) for a
description of Intel's thermal impedance test methodology_
•
17-3
8XC196KC
ACH5/PIolODE.l/PO.5
P3.0/ADO
ACH4/PIolODE.O/PO.4
P3.1/ADI
ANGND
P3.2/AD2
VREF
P3.3/AD3
VSS
EXTINT/PROG/P2.2
P3.4/AD4
Rffi'f
RXD/PALE/P2.1
TXD/PVER/P2.0
68-PIN PLCC
N8XC196KC, TN8XC196KC
P1.0
Pl.l
Pl.2
PWIolI/Pl.3
PWIol2/P1.4
HSI.O
P3.5/AD5
P3.6/AD6
P3.7/AD7
P4.0/ADB
P4.1/AD9
TOP VIEW
Looking Down on
Component Side
of PC Board
HSI.l
P4.2/AD10
P4.3/ADII
P4.4/ADI2
P4.5/ADI3
P4.6/ADI4
P4.7/ADI5
P2.3/T2CLK
HSI.2/HSO.4
270942-2
Figure 3. 68-Lead PLCC Package
17-4
infel·
8XC196KC
'"'"
«
......
..;
'"
n.
.
'"«'" «'" «'"'"
......
...... ......
'" ..;'"n. ..;n. ..;'"n.
>'"
..
U
~
- ~ '" ! '"
'" '" '"'" c c '" '" '" c
'"n. n. ...n. n. ...n.'" ...n. n. n. ...n. n.
'"'"
«
......
..;
....
0
IX)
..
« « « « « « « « «
......
';c- ...... ...... ...... ...... ...... ......
.... ......
0
..;
'" ... ...'" '" .......
...
AD1/P3.1
P2.3/T2CLK
0
ADO/P3.0
Rii
VSS
READY
ALE!ADV
61
INST
P2.4/T2RST / AINC
BHE,/WRH
BUSWIDTH
WR/WRL
CLKOUT
P2.5/PWt.40·
aD-PIN QFP
XTAL2
P2.7/T2CAPTURE;PAC'f
XTAL1
Vpp
saXC196KC
Vss
Vss
Vss
Vss
Vee
HSO.3
TOP VIEW
Vee
vee
EA
51
Looking Down on
Component Side
of PC Board
Nt.41
ACH3/PO.3
Vss
HSO.2
P2.6/T2UP-DN/CPVER
ACH1/PO.1
P1.7/HOLD
ACHO/PO.O
P1.6/HLDA
ACH2/PO.2
P1.5/8REQ
ACH6/Pt.40DE.2/PO.6
HSO.1
ACH7/EXTINT /Pt.40DE.3/PO. 7
HSO.O
N.C.
HSO.5/HSI.3
ACH5/Pt.40DE.1/PO.5
Vss
41
ACH4/Pt.40DE.O/PO.4
'"zz
(!)
«
... '" '"
~.
'" >
>0::.
Ii
......
z>x
;::
...
U
...
UI>i:l
>
'"
0
'" 0
N N >'"
-n..
n. n.
......
~'" '"
f!j
>
n.
x
'"
......
-: "l "! "": "'!
0:: 0:: n. n. iii
';c- ...... '"
;0
'"n. '";0'"n.
HSO.4/HSI.2
iii
'"
x
>270942-40
Figure 4. S8XC196KC 80·Pin QFP Package
17·5
II
intel .
8XC196KC
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (5V).
Vss
Digital circuit ground (OV). There are three Vss pins, all of which must be connected.
VREF
Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
Vss·
Timing pin for the return from powerdown circuit. Connect this pin with a 1 ,...F capacitor to
Vss and a 1 Mn resistor to Vee. If this function is not used Vpp may be tied to Vee. This pin
is the programming voltage on the EPROM device.
Vpp
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency.
RESET
Reset input and open drain output.
BUSWIDTH
Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle.INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal high causes. memory accesses to
locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA equal to low
causes accesses to those locations to be directed to off-chip memory, Also used to enter
programming mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADVis activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the CCA. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external
writes where an odd byte is being written. BHE/WRH is activated only during external
memory writes.
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3..
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,.
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
PortO
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
Port 1
8-bit quasi-bidirectional I/O port.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.
Pins 2.6 and 2.7 are quasi-bidirectional.
17-6
8XC196KC
PIN DESCRIPTIONS (Continued)
Symbol
Ports 3 and 4
Name and Function
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD
Bus Hold input requesting control of the bus.
HLDA
Bus Hold acknowledge output indicating release of the bus.
BREQ
Bus Request output activated when the bus controller has a pending external memory
cycle.
PMODE
Determines the EPROM programming mode.
PACT
A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
PVAL
A low signal in Auto Programming Mode indicates that the device programmed correctly. A
high signal in Slave Programming Mode indicates the device programmed correctly.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
indicates that ports 3 and 4 contain valid programming address/command information
(input to slave).
PROG
A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave) ..
PVER
A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
indicates the byte programmed correctly.
AINC
Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
17-7
8XC196KC
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. It is valid for the devices indicated in
the revision history. The specifications are subject to
change without notice.
Ambient Temperature
Under Bias ................. - 55°C to + 125°C
Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin to vss ...... -O.5V to + 7.0V(1)
Voltage from EA or
Vpp to Vss or ANGND ................ + 13.00V
Power Dissipation ....................... 1 .5W(2)
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress. ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
NOTE:
1. This includes Vpp and EA on ROM or CPU only devices.
2. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias Commercial Temp.
0
+70
°C
TA
Ambient Temperature Under Bias Exteni:led Temp.
-40
+85
°C
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.00
5.50
V
Fose
Oscillator Frequency
8
16
MHz
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
(Over Specified Operating Conditions)
Description
Max
Units
-0.5
0.8
V
0.2Vec + 1.0
Vee + 0.5
V
0.7Vcc
Vee + 0.5
V
Vee + 0.5
Min
VIL
Input Low Voltage
VIH
Input High Voltage (Note 1)
VIH1
Input High Voltage on XTAL 1
VIH2
Input High Voltage on RESET
2.2
VHYS
Hysteresis on RESET
150
VOL
Output Low Voltage
Vou
Output Low Voltage
in RESET on P2.5(Note 2)
VOH
Output High Voltage
(Standard Outputs)
Vee - 0.3
Vec - 0.7
Vee- 1.5
17-8
Typ
Test Conditions
V
IOL
= 5.0V
= 200 p.A
= 2.8 mA
= 7 mA
= +0.4 mA
IOH
IOH
IOH
= - 200 /LA
= -3.2 mA
= -7 mA
mV
Vce
0.3
0.45
1.5
V
V
V
IOL
IOL
IOL
0.8
V
V
V
V
intel~
8XC196KC
DC CHARACTERISTICS
Symbol
(Over Specified Operating Conditions) (Continued)
Description
Min
Typ
Max
Units
Test Conditions
VIH
=
=
=
=
Vee - 1.5V
mA
VIN
=
0.45V
+100
/LA
VIN
=
Vee
Input Leakage Current (Std. Inputs)
±10
/LA
o<
VIN < Vee - O.3V
IU1
Input Leakage Current (Port 0)
±3
/LA
0< VIN < VREF
ITL
1 to 0 Transition Current (QBO Pins)
-650
/LA
VIN
Logical 0 Input Current (QBO Pins)
/LA
VIN
=
=
2.0V
IlL
=
0.45V
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)
IOH1
Logical 1 Output Current in Reset.
Do not exceed this or device
may enter test modes.
11L1
Logical 0 Input Current in Reset.
Maximum current that must be
sunk by external device to
ensure test mode entry.
IIH1
Logical 1 Input Current.
Maximum current that external device
must source to initiate NMI.
lu
Vee - 0.3
Vee - 0.7
Vec - 1.5
V
V
V
IOH
IOH
IOH
-0.8
mA
-6.0
-70
-10 /LA
-30/LA
-60/LA
=
5.5V
0.45V
-70
/LA
VIN
50
70
mA
AID Converter Reference Current
2
5
mA
XTAL1 = 16MHz
Vee = Vpp = VREF
Idle Mode Current
15
30
mA
15
TBO
/LA
Vee
65K
n
Vce
10
pF
11L1
Ports 3 and 4 in Reset
lee
Active Mode Current in Reset
IREF
IIDLE
IpD
Powerdown Mode Current
RRST
Reset Pull up Resistor
Cs
Pin Capacitance (Any Pin to VSS)
6K
=
=
Vpp
=
VREF
5.5V, VIN
=
=
5.5V
=
5.5V
4.0V
NOTES:
1.
2.
3.
4.
5.
All pins except RESET and XTAL1.
Violating these specifications in Reset may cause the part to enter test modes.
Commercial specifications apply to express parts except where noted.
QSD (Quasi·bidirectional) pins include Port 1, P2.6 and P2.7.
Standard Outputs include ADO-15, RD, WR. ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open·drain outputs.
6. Standard Inputs include HSI pins, READY, SUSWIDTH, NMI, RXD/P2.1, EXTINTIP2.2, T2CLK/P2.3 and T2RST IP2.4.
7. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on quasi·bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
8. Maximum current per bus pin (data and control) during normal operation is ± 3.2 mA.
9. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOL: 29 mA
IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 mA
IOH: 26 mA
P2.5, P2.7, WR, SHE
IOL: 13 mA
IOH: 11 mA
ADO-AD15
IOL: 52 mA
IOH: 52 mA
RD, ALE, INST -CLKOUT IOL: 13 mA
IOH: 13 mA
17-9
•
int:eL
8XC196KC
70
r--~.------,--.,...-...."
Icc Max
50 t----+----f7'<----;.,I ICC Typ
mA
o~--~~-~--~
16
10
ICC Max = 3.88 x FREQ + 8.43
IIDLE Max = 1.65 x FREQ + 2.2
Froq (MHz)
270942-17
Figure 5. Icc and IIDLE vs Frequency
AC CHARACTERISTICS
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, Fosc = 16 MHz
The system must meet these specifications to work with the 80C196KC:
Symbol
Description
TAVYV
Address Valid to READY Setup
hLYV
ALE Low to READY Setup
TYLYH
Non READY Time·
TCLYX
READY Hold after CLKOUT Low
Min
Max
Units
2 Tosc - 68
ns
Tosc - 70
ns
No upper limit
Notes
ns
0
Tosc - 30
ns
(Note 1)
Tosc - 15
2 Tosc - 40
ns
(Note 1)
2 Tosc - 68
ns
Tosc - 60
ns
hLYX
READY Hold after ALE Low
TAVGV
Address Valid to Buswidth Setup
TLLGV
ALE Low to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
3 Tosc - 55
ns
(Note 2)
TRLDV
RD Active to Input Data Valid
Tosc - 22
ns
(Note 2)
TCLDV
CLKOUT Low to Input Data Valid
Tosc - 50
ns
TRHDZ
End of RD to Input Data Float
Tosc
ns
TRXDX
Data Hold after RD Inactive
0
0
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC • N, where N = number of wait states.
17·10
ns
ns
infel .
8XC196KC
AC CHARACTERISTICS
(Continued)
For user over specified operating conditions.
Test Conditions: Capacitive load on all pins
=
100 pF, Rise and fall times
=
10. ns, Fosc
=
16 MHz
The80C196KC will meet these specifications:
Symbol
FXTAL
Description
Frequency on XTAL1
Tosc
I/FxTAL
Min
Max
Units
Notes
8
16
MHz
(Note 1)
62.5
125
ns
20
110
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Falling Edge to ALE Rising
-5
15
ns
hLCH
ALE Falling Edge to CLKOUT Rising
-20
+15
ns
hHLH
ALE Cycle Time
TLHLL
ALE High Period
Tosc - 10
TAVLL
Address Setup to ALE Falling Edge
Tosc - 15
TLLAX
Address Hold after ALE Falling Edge
Tosc - 40
hLRL
ALE Falling Edge to RD Falling Edge
Tosc - 30
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
ns
2 Tosc
Tosc - 10
Tosc+15
ns
4 Tosc
4
Tosc+10
ns
30
ns
ns
(Note 4)
Tosc +.25
ns
(Note 2)
5
ns
ns
Tosc - 10
0
25
ns
15
ns
(Note 4)
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
Tosc - 20
ns
TWHQX
Data Hold after WR Rising Edge
Tosc - 25
ns
TWHLH
WR Rising Edge to ALE Rising Edge
Tosc - 10
TWHBX
SHE, INST after WR Rising Edge
Tosc - 16
ns
TWHAX
AD8 -15 HOLD after WR Rising
Tosc - 30
ns
TRHBX
SHE, INST after RD Rising Edge
Tosc - 10
ns
TRHAX
AD8-15 HOLD after RD Rising
Tosc - 30
ns
Tosc - 23
-10
Tosc + 15
ns
NOTES:
1. Testing performed at a MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus eycles.
3. a-Bit bus only.
4. If wait states are used, add 2 T asc • N, where N = number of wait states.
17-11
(Note 4)
ns
ns
Tosc - 5
Tosc
ns
(Note 4)
(Note 2)
(Note 3)
(Note 3)
•
intel~
8XC196KC
System Bus Timings
XTAL 1
CLKOUT
ALE
BUS
BUS
-<~
ADDRESS OUT
I,
DATA OUT
I
~\l(...._AD_D_R_ES_S_ _ _ __
LTRHBX ..
iTwHBX
BHE.INST
VALID
AD8-1S
ADDRESS OUT
270942-18
17-12
8XC196KC
READY Timings (One Wait State)
XTALI
CLKOUT
ALE
READY
--1--------'" 1-00-----
TRLRH + 2TOSC
TRLDV + 2TOSC
t=======~
ADDRESS OUT
TAVDV + 2TOSC
----1~--------
-l
-----1-:--.. . . . . . .
}-
-{ DATA
_+________~f-.!----
»»»)_---
1
I
TWLWH + 2Tosc
r-__________~~I~.------~-V-WH-+-2-~-S-C-~
~---AD-D-RE-S-S-O-UT----~~~(~I_______D_A_TA_OU_T_ _ _ _ _ _-J)(~__A_D_D_RE_SS___
270942-20
Buswidth Timings
XTALI
"~~ ~ "~: J~ "~:" '
~r----------------------I
8USWIDTH
--"I"'I.--T-AV-GV---j-
8US
-<~
____________~~___~)r---------270942-35
17-13
intet
8XC196KC
HOLD/HLDA Timings
Symbol
Description
Min
Max
Units
Notes
ns
(Note 1)
THVCH
HOLD Setup
TCLHAL
CLKOUT Low to HLDA Low
-15
15
ns
TCLBRL
CLKOUT Low to SREQ Low
-15
15
ns
THALAZ
HLDA Low to Address Float
10
ns
THALBZ
HLDA Low to SHE, INST, RD, WR Weakly Driven
15
ns
TCLHAH
CLKOUT Low to HLDA High
-15
15
ns
TCLBRH
CLKOUT Low to SREQ High
-15
15
ns
THAHAX
HLDA High to Address No Longer Float
-15
ns
THAHBV
HLDA High to SHE, INST, RD, WR Valid
-10
ns
TCLLH
CLKOUT Low to ALE High
55
-5
15
ns
NOTE:
1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD
Description
Min
Max
Weak Pullups on ADV, RD,
WR, WRL, SHE
50K
250K
VCC
=
5.5V, VIN
=
0.45V
Weak Pull downs on
ALE,INST
10K
50K
Vcc
=
5.5V, VIN
=
2.4
17-14
Units
intel .
8XC196KC
BUS
BHE.INST
Rii. iii
ALE
--<"'____
,,
~!-I
____
~!ljol
lh. . -----
_ _ _ _TC_L_LH
270942-36
Maximum Hold Latency
Bus Cycle Type
Internal Execution
1.5 States
16-Bit External Execution
2.5 States
a-Bit External Execution
4.5 States
•
17-15
8XC196KC
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TxLXL
Oscillator Frequency
8
16.0
MHz
TXLXL
Oscillator Period
62.5
125
ns
TXHXX
High Time
20
TXLXX
Low Time
20
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270942-21
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
vee
C1
Vss
II
rC . .
EXTERNAL
CLOCK INPUT
-6-Ir---I XTAL1 8XC196KC
--
f
4.7K·
XTAL 1
clock driver
XTAL2
BXC196KC
no connect- XTAL2
Qucrtz Crystcl or
Ceramic Resonator
270942-42
270942-41
NOTE:
NOTE:
"Required if TTL driver used.
Not needed if CMOS driver is\ used.
Keep oscillator components close to chip and use
short, direct traces to XTAl1, XTAL2 and Vss" When
using crystals, C1 = C2 '" 20 pF. When using ceramic
resonators, consult manufacturer for recommended capacitor values.
AC TESTING INPUT, OUTPUT WAVEFORMS
2 . 4 - y - 2.0> TEST POINTS
0.45
---f\ 0.8
<
2.0
FLOAT WAVEFORMS
V-
0.8.A--
270942-22
AC Testing inputs are driven at 2.4V for a Logic "1" and 0.45V for'
a Logic "0" Timing measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0".
270942-23
For Timing Purposes a Port Pin is no Longer Floating when a'
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH = ±15 mAo
17-16
intel~
8XC196KC
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
ALE/ADV
Conditions:
Signals:
L-
H- High
A-
Address
BR-BREQ
BHE
R-
L-
Low
B-
V-
Valid
C- CLKOUT
W- WR/WRH/WRL
X-
No Longer Valid
z-
Floating
0- DATA
G- Buswidth
y- READY
H- HOLD
Q- Data Out
X-
RD
XTAL1
HA- HLDA
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol
Parameter
Min
~
TXLXL
Serial Port Clock Period (BRR
8002H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR ~ 8002H)
TXLXL
Serial Port Clock Period (BRR = 8001 H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)
2 Tose -50
TOVXH
Output Data Setup to Clock Rising Edge
2 Tose - 50
2 Tose - 50
Max
Units
ns
6 Tose
4 Tose -50
ns
4 Tose +50
ns
4 Tose
TXHOX
Output Data Hold after Clock Rising Edge
TXHOV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHOX
Input Data Hold after Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
ns
2 Tose +50
ns
ns
ns
2 Tose + 50
Tose +50
ns
0
ns
ns
1 Tose
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
rS_ER_I_A_L_P_O_R_T_W_A_V_E_F_O_R_M_-S
__H_I_FT
__
R_E_G_IS_
T_E_R_M_O_D_E______________________________
r- --j
TXO---Lr ---Lr ---Lr ---Lr ---Lr ---Lr ---Lr ---Lr
II
II-j
-l
I"
(O~~) --TXLXL
TQVXH-j
TXLXH-l
1
TOVxH-j
TXHQV
2
1=
j-TXHQX
3
:j
4
5
TXHQZ-l
6
7
j-TXHOX
RXD--"'--"
(IN) _~'_J '-_I'--~''__----'' ____J'. ____',~__',
._~''___I'---._. 1'--- --""----' '''------' ,'----.--' ' - - - ' ' - -
270942-24
17-17
~
IIIiIII
in1:et
A
8XC196KC
to D CHARACTERISTICS
The AID converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
10-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature Commercial Temp.
TA
Ambient Temperature Extended Temp.
0
-40
+70
+85
5.50
5.50
'c
'c
Vcc
Digital Supply Voltage
VREF
Analog Supply Voltage
TSAM
Sample Time
TCONV
Conversion Time
Fosc
Oscillator Frequency
4.50
4.00
3.0
10
8.0
V
V
,...s(1)
,...s(1)
20
16.0
MHz
NOTE:
ANGND and Vss should nominally be at the same potential, O.OOV.
1. The value of AD_TIME is selected to meet these specifications.
10-BIT MODE AID CHARACTERISTICS (Over Specified Operating Conditions)
Parameter
Typlcal(1)
Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity
Repeatability
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009,
0.009
DC Input Leakage
LSBs
LSBs
0
0
±3
+2
±1
LSBs
LSBs
LSBs
LSBs
LSBfOC
LSBfOC
LSBfOC
dB
dB
dB
750
ANGND -,0.5
0
Voltage on Analog Input Pin
Notes
LSBs
-60
-60
Input Series Resistance
Sampling Capacitor
Levels
Bits
-60
Off Isolation
Vec Power Supply Rejection
Units·
1024
10
±3
>-1
±0.1
±0.25
Feedthrough
Maximum
1024
10
0
0.25 ± 0:5
0.25 ± 0.5
1.0 ± 2.0
Differential Non-Linearity Error
Channel-to-Channel Matching
Minimum
3
1.2K
n
VREF + 0.5
V
±3.0
,...A
pF
1,2
1
1
4
5,6
NOTES:
'An uLSB" as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for AID glossary of terms).
1. These values are expected for most parts at 25'C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to ± 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
,7. All conversions performed with processor in IDLE mode.
17-18
int'eL
8XC196KC
8-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature Commercia! Temp.
Ambient Temperature Extended Temp.
+70
+85
·C
TA
0
-40
Vcc
Digital Supply Voltage
4.50
5.50
V
4.00
5.50
VREF
Analog Supply Voltage
TSAM
Sample Time
TCONV
Fosc
·C
V
,...s(1)
Conversion Time
2.0
7
20
,...s(1)
Oscillator Frequency
8.0
16.0
MHz
NOTE:
ANGND and Vss should nominally be at the same potential, O.OOV.
1. The value of AD_TIME is selected to meet these specifications.
8-BIT MODE AID CHARACTERISTICS
Parameter
Typical
Resolution
Absolute Error
Full Scale Error
±0.5
Zero Offset Error
±0.5
(Over Specified Operating Conditions)
Minimum
Maximum
Units·
256
8
256
8
Levels
Bits
0
±1
LSBs
LSBs
LSBs
0
> -1
Non-Linearity
Differential Non-Linearity Error
Channel-to-Channel Matching
±1
LSBs
+1
LSBs
±1
LSBs
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
LSBI"C
LSBI"C
LSBI"C
-60
Off Isolation
Feedthrough
Vcc Power Supply Rejection
-60
-60
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
Notes
dB
2,3
dB
2
2
dB
750
1.2K
o.s
Vss - 0.5
VREF + 0.5
V
0
±3.0
,...A
3
4
5,6
pF
NOTES:
'An "LSBn as used here has a value of approximately 20 mY. (See Embedded Microcontrollers and Processors Handbook
lor AID glossary of terms).
1. These values are expected lor most parts at 2SoC but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Belore-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
S. These values may be exceeded il pin current is limited to ± 2 mA.
6..Applying voltages beyond these specilications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
17-19
•
intel~
8XC196KC
EPROM SPECIFICATIONS
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature During Programming
20
30
C
Vee
Supply Voltage During Programming
4.5
5.5
V(1)
VREF
Reference Supply Voltage During Programming
4.5
5.5
V(1)
VPP
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
Fose
Oscillator Frequency During Auto and Slave
Mode Programming
6.0
8.0
MHz
Fose
Oscillator Frequency During
Run-Time Programming
6.0
12.0
MHz
NOTES:
1.
2.
3.
4.
Vce and VREF should nominally be at the same voltage during programming.
Vpp and VEA must never exceed the maximum specification, or the device may be damaged.
Vss and ANGND should nominally be at the same potential (OV).
Load capacitance during Auto and Slave Mode programming = 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
TSHLL
Description
Min
. Reset High to First PALE Low
Max
Units
1100
Tose
50
Tose
Address Setup Time
0
Tose
Address Hold Time
100
TLLLH
PALE Pulse Width
TAVLL
TLLAX
TpLDV
PROG Low to Word Dump Valid
50
Tose'
TpHDX
Word Dump Data Hold
50
Tose
TDVPL
Data Setup Time
0
Tose
TpLDX
Data Hold Time
400
Tose
TpLPH(1)
PROG Pulse Width
50
Tose
TpHLL
PROG High to Next PALE Low
220
Tose
TLHPL
PALE High to PROG Low
220
Tose
TpHPL
PROG High to Next PROG, Low
220
Tose
TpHIL
PROG High to AINC Low
0
Tose
TILIH
AINC Pulse Width
240
Tose
TILVH
PVER Hold after AINC Low
50
Tose
TILPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Valid
Tose
Tose
220
Tose
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
17-20
infel~
8XC196KC
DC EPROM PROGRAMMING CHARACTERISTICS
Description
Symbol
Vpp Supply Current (When Programming)
Ipp
NOTE:
'Jpp must be within 1V of Vee while Vee
Vee> 4.5V.
< 4.5V. Vpp must not have a low impedance path to ground of Vss while
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
-J
l'
I;.TAVLL . ,
PORTS
"
3/4
ADDR/COMMAND
~ TSHLL
-'
DATA
-'
~ ADDR/COMMAND
TDVPL ~ TpLDX ...
TLLAX -
\
/
\
I-
- - TLLLH -
TLHPL -+
-
TpLPH -
.. TpHLL ...
I
\
\
PVER
_ TpHVL -
270942-27
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
---i
I
PORTS
ADDR/COI.II.IAND
3/4 .
_ TSHLL -
,
ADDR
I
VER BITS/WD DUI.IP
~
TpLDV -
/
T1LPL
-
,
.....
TpHDX
I-
4TPLDV -
,
If
I---
ADDR+ Z
VER BITS/WD DUI.IP
""II - -
TpHDX
I-
If
TpHPL _
~
270942-28
17-21
•
inteL
8XC196KC
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
PO~/~
-«
____
ADDR/COMMAND
>---<
ADDR
ADDR
)>-__~~
DATA
ADDR + 2
DATA
>--
270942-29
80C196KB TO 80C196KC DESIGN
CONSIDERATIONS
1. Memory Map. The 80C196KC has 512 bytes of
RAM/SFRs and 16K of ROM/EPROM. The extra
256 bytes of RAM will reside in locations 100H1FFH and the extra 8K of ROM/EPROM will reside in locations 4000H-5FFFH. These locations
are external memory on the 80C196KB.
2. The CDE pin on the KS has become a Vss pin on
the KC to support 16 MHz operation.
3. EPROM programming. The 80C196KC has a different programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code on page
99 of the 80C196KC User's Guide, order number
270704-003.
4. ONCETM Mode Entry. The ONCE mode is entered on the 80C196KC by driving the TXD pin
low on the rising edge of RESET. The TXD pin is
held high by a pullup that is specified at 1.4 mA
and remain at 2.0V. This Pullup must not be overridden or the 80C196KC will enter the· ONCE
mode.
5. During the bus HOLD state, the 80C196KC weakly holds RD, WR, ALE, SHE and INST in their
inactive states. The 80C196KB only holds ALE in
its inactive state.
6. A RESET pulse from the 80C196KC is 16 states
rather than 4 states as on the 80C196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
80C196KC ERRATA
1. NMI during PTS skips an address: When an NMI
interrupts a PTS routine, the first byte of the instruction following completion of the PTS cycle is
lost. This results in incorrect code execution.
Workaround: NMI must be disabled using ex1ernal
hardware during any PTS activity.
2. QBD port glitch. There isa strong negative glitch
on all QBD Port pins (P1.x and P2.6, P2.7) synchronous with the first falling edge of CLKOUT.
This glitch lasts about 10 ns, and only occurs one
time following initial application of Vee. The time
for the pin to return to Vee may be several microseconds, depending on pin loading capacitance.
Workaround: External systems and devices
should be disabled from responding to this glitch
until after the first CLKOUT falling edge has occurred.
3. Divide error during HOLD or READY. The result of
a signed divide instruction may be off by one if
executed while the device is held off the bus by
HOLD or READY and the queue is empty. Specific timings of HOLD or READY gOing active or inactive must be met. Workaround for HOLD: disable HOLD during signed divide operations (using
hardware or software). Workaround for READY:
problem will only occur if unlimited wait state
mode is selected, and 14 or more wait states are
inserted.
4. The HSI unit has two errata: one dealing with resolution and the other with first entries into the
FIFO.
17-22
intel®
8XC196KC
The HSI resolution is 9 states instead of 8 states.
Events on the same line may be lost if they occur
faster than once every 9 state times.
There is a mismatch between the 9 state time HSI
resolution and the 8 state time timer. This causes
one time value to be unused every 9 timer counts.
internal phase, both are recorded with one timetag. Otherwise, if the second event occurs within
9 states after the first, its time-tag is one count
later than the first time tag. If this is the "skipped"
time value, the second event's time-tag is 2
counts later than the first's.
If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register
after 8 state times, leaving the FIFO empty again.
If the second event occurs after this time, it will
act as a new first event into an empty FIFO.
Events may receive a time-tag on one count later
than expected because of this "skipped" time value.
If the first two events into an empty FIFO (not
including the Holding Register) occur in the same
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a "D" or "E" at the end of the topside tracking number. Data sheets
are changed as new device information becomes available. Verify with your local Intel sales office that you
have the latest version before finalizing a design or ordering devices.
The following are the important differences between the -001 and -002 versions of data sheet 270942.
1. Express and Commercial devices are combined into one data sheet. The Express only data sheet
270794-001 is obsolete.
2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps.
3. Added programming pin function to package drawings and pin descriptions.
4. Changed absolute maximum temperature under bias from O°C to
+ 70°C to
- 55°C to
+ 125°C.
5. Replaced VOH2 specification with IOH1 and 11L1 specifications.
6. Added IIH1 specification for NMI pulldown resistors.
7. Added maximum hold latency table.
8. Added external oscillator and external clock circuit drawings.
9. Changed Clock Drive T XHXX and T XLXX Min spec to 20 ns.
10. Fixed Serial Port T XLXH specification.
11. Added 8- and 10-bit mode AID operating conditions tables.
12. Specified operating range for sample and convert times.
13. Added specification for voltage on analog input pin.
14. Put operating conditions for EPROM programming into tabular format.
The following differences exist between data sheet 270942-001 and 270741-003.
1. ONCE MODE VIL errata removed.
2. VREF Min changed from 4.5V to 4.0V.
The following differences exist between the -002 and -003 versions of data sheet 27074.11. 80-Pin QFP package added, 68-pin Cerquad package deleted.
2. The following DC Characteristics were added:
VHYS RESET Hysteresis spec added
IIL1, AD BUS in RESET current Max added
17-23
•
int:eL
8XC196KC
DATA SHEET REVISION HISTORY (Continued)
3. The following AC Characteristics were changed:
TAVYV Max from 2Tosc-75 to 2Tosc-68
TAVGV Max from 2Tosc-75 to 2Tosc-68
TWLWH Min from T osc-30 to T osc-20
TXHCH Min changed from 30 ns to 20 ns
T HALBZ Max changed from 10 ns to 15 ns
4. Under 10-bit AID Characteristics:
Sample Time/Convert Time Testing Conditions added.
Typical values added for Full Scale Error, Zero Offset Error; Non-Linearity and Channel-to-Channel Matching.
Max Absolute Error changed from
Max Non-Linearity changed from
± 8 to ± 3 LSBs
± 8 to ± 3 LSBs
5~ Under 8-bit Mode AID Characteristics:
± 2 to ± 1 LSBs
± 2 to ± 1 LSBs
Typical Full Scale Error changed from ± 1 to ± 0.5 LSBs
Typical Zero Offset Error changed from ± 2 to ± 0.5 LSBs
Max Absolute Error changed from
Max Non-Linearity changed from
6. The minimum frequency at which the device is tested was changed to 8.0 MHz from 3.5 MHz. Thus, data
sheet specifications are guaranteed from 8 MHz to 16 MHz. However, the device is static and will function
below 1 Hz.
7. The T2CONTROL (T2CNTC) SFR was renamed IOC3.
8. ONCE MODE VIL errata added. Other errata removed.
9. The A-Step device corresponding to data sheet 270741-002 had bits IOC1.4 and IOC1.6 reversed. The
problem was corrected in the B-1 Step device corresponding to data sheet 270741-003.
The following are the important differences between the -001 and -002 versions of data sheet 270741. Please
review this revision history carefully.
1. The 83C196KC (ROM) was added to the product line.
2. The OTP version of the EPROM was added to the product line.
3. HOLD/HLDA Specifications were added.
4. The IOL test condition on Vou has changed to -0.5 mA from -0.4 mA.
5. The IOH test condition VOH2 has changed to 0.8 mA from 1.4 mAo
6. BMOVi errata was added.
7. Errata was added for the HSI resolution and first event anomalies.
8. Errata was added for the serial port Framing Error anomaly.
17-24
8XC 196KD Data Sheets
18
•
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I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
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I
8XC196KD/8XC196KD20
COMMERCIAL CHMOS MICROCONTROLLER
87C196KD-32 Kbytes of On-Chip OTPROM
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16 MHz and 20 MHz Available
1000 Byte Register RAM
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
Peripheral Transaction Server
1.4 J-ts 16 x 16 Multiply (20 MHz)
2.4 J-ts 32/16 Divide (20 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
16-Bit Watchdog Timer
Full Duplex Serial Port
High Speed I/O Subsystem
16-Bit Timer
16-Bit Up/Down Counter with Capture
3 Pulse-Width-Modulated Outputs
Four 16-Bit Software Timers
8- or 10-Bit A/D Converter with
Sample/Hold
HOLD/HLDA Bus Protocol
OTP One-Time Programmable Version
Dynamically Configurable 8-Bit or
16-Bit Buswidth
The 8XC196KD 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller family.
The 8XC196KD is an enhanced 80C196KC device with 1000 bytes RAM, 16 MHz operation and an optional
32 Kbytes of ROM/EPROM. Intel's CHMOS III-E process provides a high performance processor along with
low power consumption.
The 8XC196KD has a maximum guaranteed frequency of 16 MHz. The 8XC196KD20 has a maximum guaranteed frequency of 20 MHz. Unless otherwise noted, all references to the 8XC196KD also refer to the
8XC196KD20.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
II
MCS@-96 is a registered trademark of Intel Corporation.
18-1
June 1992
Order Number: 272145-002
intel .
VREf
8XC196KD/8XC196KD20
ANGND
CONTROL
SIGNALS
PORT 3
l ~~~:
BUS
"'---1-1/
PORT 4
HOLD
HLDA
BREQ
1--+-+
rc;:;;;:T"1Il-----tI-+
L..:;;;.;.;J.-----tl-+
AID
PWM I
PWM2
ALTERNATE
, 272145-1
Figure 1. 8XC196KD Block Diagram
87C196KD ENHANCED FEATURE SET
OVER THE 87C196KC
IOC3 (OCH HWIN1 READ/WRITE)
1. The 87C196KD has twice the RAM and twice the
OTPROM space of the 87C196KC.
2. The vertical windowing scheme has been extended to allow a" 1000 bytes of register RAM to be
windowed into the lower register file.
S. A CLKOUT disable bit has been added to the
IOCS SFR. This can be used to reduce noise in
systems not requiring the CLKOUT signal.
RSV·
RSV·
RSV"
RSV·
272145-2
NOTE:
"RSV-Reserved bits must be = 0
Figure 2. 87C196KD New SFR Bit
(CLKOUT Disable)
18·2
int:el.
8XC196KD/8XC196KD20
Table 3. 32-Byte Windows
8XC196KD VERTICAL WINDOWING
MAP
Address to
Remap
Table 1. 128-Byte Windows
Address to
Remap
Device
Series
WSR Contents
03BOH
KD
X001 0111B
0300H
KD
X001 0110B
02BOH
KD
X001 0101B
0200H
KD
X001 0100B
01BOH
KC,KD
X001 0011B
0100H
KC,KD
X001 0010B
OOBOH
KC,KD
X001 0001B
OOOOH
KC,KD
X001 OOOOB
Window
In
=
=
=
=
=
=
=
=
03COH
KD
KD
03AOH
KD
16H
03BOH
KD
15H
0360H
KD
14H
0340H
KD
13H
0320H
KD
12H
0300H
KD
11H
02EOH
KD
10H
02COH
KD
02AOH
KD
0280H
KD
0260H
KD
03BOH
KD
0340H
KD
0300H
KD
02COH
KD
0280H
KD
0240H
KD
0200H
KD
01COH
KC,KD
01BOH
KC,KD
0140H
KC,KD
0100H
KC,KD
OOCOH
KC,KD
OOBOH
KC,KD
0040H
KC,KD
OOOOH
KC,KD
WSR Contents
=
X010 1110B =
X010 1101B =
X010 1100B =
X010 1011B =
X010 1010B =
X0101001B =
X010 1000B =
X0100111B =
X010 0110B =
X0100101B =
X010 0100B =
X0100011B =
X010 0010B =
X010 0001B =
X010 OOOOB =
X010 1111B
KD
03COH
Table 2. 64-Byte Windows
Device
Series
03EOH
17H
Lower Register File: 80H-FFH
Address to
Remap
Device
Series
0240H
KD
2FH
0220H
KD
2EH
0200H
KD
2DH
01EOH
KC,KD
2CH
01COH
KC,KD
2BH
01AOH
KC,KD
2AH
0180H
KC,KD
29H
0160H
KC,KD
28H
0140H
KC,KD
27H
0120H
KC,KD
26H
0100H
KC,KD
25H
OOEOH
KC,KD
24H
OOCOH
KC,KD
23H
OOAOH
KC,KD
22H
OOBOH
KC,KD
21H
0060H
KC,KD
20H
0040H
KC,KD
0020H
KC,KD
OOOOH
KC,KD
Window in Lower Register File: COH-FFH
Window
1B·3
In
WSR Contents
=
X1011110B =
X1011101B =
X1011100B =
X1011011B =
X101 1010B =
X1011001B =
X1011000B =
X101 0111 B =
X101 0110B =
X101 0101B =
X101 0100B =
X101 0011 B =
X101 0010B =
X101 0001B =
X101 OOOOB =
X100 1111B =
X100 1110B =
X100 1101 B =
X100 1100B =
X100 1011B =
X100 1010B =
X100.1001B =
X100 1000B =
X1000111B =
X1000110B =
X1000101B =
X1 00 01 OOB =
X1000011B =
X100 0010B =
X1000001B =
X100 OOOOB =
X101 1111 B
Lower Heglster File: EOH-FFH
5FH
5EH
5DH
5CH
5BH
5AH
59H
5BH
57H
56H
55H
54H
53H
52H
51H
50H
4FH
4EH
4DH
4CH
4BH
4AH
49H
48H
47H
46H
45H
44H
43H
42H
41H
40H
II
intel .
8XC196KD/8XC196KD20
Table 5. 8XC196KD Memory Map
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS '
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
L
~
1
x ~c
- l!!!!S!1 ~D"l"SP"d'
No Mark = 16 MHz
20= 20WHz
KD Product Family
Description
External Memory or 110
9FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
Word Addressable Only
1FFFH
1FFEH
External Memory
1FFDH
0400H
1000 Bytes Register RAM (Note 1)
03FFH
0018H
CPU SFR's (Notes 1, 3)
0017H
OOOOH
Program Wemory Options:
7 = EPROM (Note 1)
S = BD-Iead QFP
S9 = aD-lead SQrp
' - - - - - - - - - - - Temperature and Burn-In Options:
No Wgrk= OOC - 700 e Ambient with
Int.1 Standard Burn-In
272145-19
EXAMPLE:
N87C196KD20
is 68-Lead
PLCC
OTPROM, 20 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196KD Family Nomenclature
Table 4. Thermal Characteristics
Package
Type
8Ja
8Jc
PLCC
35°C/W
13°C/W
QFP
56°C/W
12°C/W
SQFP
TBD
TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel's thermal impedance test methodology.
OFFFFH
OAOOOH
Internal ROM/EPROM or External
Memory (Determined by EA)
CHIIIQS Technology
' - - - - - - - - - Package Type Options:
N = 64-lead PlCC
Address
NOTES:
1. Code executed in locations OOOOH to OSFFH will be
forced external.
2. Reserved memory locations must contain OFFH unless
noted.
S. Reserved SFR bit locations must contain O.
4. Refer to 8XC196KC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents andlor function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
18-4
intet
~[Q)W~OO©[§ DOOIP@OO~~iiD@OO
8XC196KD/8XC196KD20
....
::t:
U
«
-;::.
z
~
'"
::t:
U
......
..,'" ......N«
..;
..;
0
0
...'" .........'":::E
......
::IE
N
::t:
<.>
«
'"
::t:
<.>
......
~
N
X
<.>
'"
::t:
~
«
......
......
....
...0 0...'" ...0 ...'"0 ...0 ...'"0
::;
:i
z
III
1L:l
>'d >111
N
....I
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....
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§il
....I
<.>
::c
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iIII
:::>
'"
....
III
~
~
'"
«
....I
I~
ACHS/Pt.lODE.l/PO.S
P3.0/ADO
ACH",/Pt.lODE.O/PO.4
P3.1/ADI
ANGND
P3.2/AD2
P3.3/AD3
VREF
68-PIN PLCC
N87C196KD
VSS
EXTINT /PROG/P2.2
P3.4/AD4
P3.S/ADS
P3.6/AD6
RESET
P3.7/AD7
RXD!PALE/P2.1
TOP VIEW
TXD/PVER/P2.D
P4.0/AD8
P4.1/AD9
Pl.D
Pl.1
P4.2/AD10
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
Pl.2
PWt.l.l/Pl.3
P4.3/ADll
P",.4/ADI2
PWI.l.2/Pl.4
P4.S/ADI3
HSI.O
P",.6/ADI4
HSI.l
P4.7/ADIS
P2.3/T2CLK
HSI.2/HSO.4
on
g '"g
::t:
......
"l
iii
::t:
::t:
0
III
::t:
"l
"!
~
Ii:
Ii:
iL
Ii I~ I}
'"
...
......
N
...'"'">
N
0
III
::t:
<.>
......
z
'"0
III
::c
III
>111
...
....
~'"'"~
:::>
.......
«
0
I
...
:::>
on
::- N... ...N ~
......
'":::E I~
;I:
0.
...
~ N...
Ii
~....
>co
«
'"'"
III
'"....
N
u
....N
N
....
Figure 4. S8-Pin PLCC Package
18-5
272145-3
III
8XC196KD/8XC196KD20
P2.3/T2CLK
AD1/P3.1
ADO/P3.0
Vss
RD
REA.DY
P2.4/T2RST /AiNC
ALE/AoV
INST
BHE!WRH
WRjWR[
BUSWIDTH
P2.S/PWM.O
BO-PIN OFP
SB7C196KD
CLKOUT
XTAL2
XTALI
P2.7/T2CAPTURE/PACT
Vpp
Vss
VSS
VSS
Vss
Vec
HSO.3
TOP VIEW
vee
Vee
EA
Vss
Nt.fl
HSO.2
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
ACH3/PO.3
ACH1/PO.1
ACHO/PO.O
P2.S/T2UP-DN/CPVER
Pl.7 /HOLD
P1.6/HLDA
Pl.S!BiiEQ
ACH2/PO.2
HSO.l
ACH6/PMODE.2/PO.6
HSO.O
ACH7/EXTINT/Pt.fODE.3/PO.7
HSO.5/HSI.3
N.C.
ACHS/Pt.fODE.1/PO.5
Vss
ACH4/PMODE.O/PO.4
HSO.4/HSI.2
Q
z
"z..:
...
II>N
>~ >'" ~
~...
,!ll~ ~... ~'"
Z
;::
..J
...
:: 6:
Q
~
!llC!
>
-0..
-:
"! "l "of; C!
iii
0.. 0.. iii
............ :r :r
0:: 0::
-::i :::i
N
~
0..
~
0..
1;] ~
15
272145-4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 5. aD-Pin QFP Package
18-6
intel~
OXC196KD/OXC196KD20
... c
... '"
en
~
'"
~
c
... '" '"
c
'"
..J
'" «'" « «'" « "«
« « «
« « « « « « « «
''- ''':::- '- '- ':::- '- '- '- '-..; '-CD..; '- '-'"'"" V>
0
CD
0
U U ... ... '" '" ... '"
..; ..; ..; ..;
..; ..; ..; ..;
'"
"
"..; N >V>
0.
0.
0.
0.
0.
0.
0.
0.
Z Z 0. 0. 0. 0. 0. 0. 0. 0. 0.
0
0
0
0
0
'"
Ro
0
CD
0
z
'- '«
0
ci ci
0
:::E
0.
0
:::E
0.
'" ...:I:
'- ':I:
U
U
« «
...w
Vl
V>
~ >
'"•
UI'"w"
U
>
'"
0.
'-
I~''z""
VI
W
""
Vl
0
N N >Vl
0.
0.
'- '-
I~'- '->""w
;::
X
w
0.
0
x
c
x
0
'":
0.
0.
~
a::
~
"":
0
~
Vl
V>
in in
in >
:J: :J:
'- '':>i :>i
0
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a::
'"
'"' '"'
0.
0.
:J:
...
VI
:J:
"" '""
272145-20
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 6. aD-Pin SQFP Package
..
18-7
int'eL
8XC196KD/8XC196KD20
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (SV).
Vss
Digital circuit ground (OV). There are three Vss pins, all of which must be connected.
VREF
Reference voltage for the AID converter (SV). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for AID
and Port to function.
°
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
XTAl1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
Output of the oscillator inverter.
GLKOUT
Output of the internal clock generator. The frequency of GLKOUT is
frequency:
% the oscillator
RESET
Reset input and open drain output.
BUSWIDTH
Input for buswidth selection. If GGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a an
8-bit cycle occurs. If GGR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 9FFFH to be directed to on-chip ROM/EPROM. EA equal low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by GGA. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADV is activated only during
external memory accesses.
°
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the GGR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the GGA. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external
writes where an odd byte is being written. BHE/WRH is activated only during external
memory writes.
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. When the external memory is not being used, READY has no
effect.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.S. Two of them (HSO.4 and HSO.S) are shared with the HSI Unit.
18-8
infel .
8XC196KD/8XC196KD20
~[Q)W~OO©[§ OOOIP©OOIMl~ii"O©OO
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
PortO
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
Port 1
8-bit quasi-bidirectional 110 port.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KD.
Pins 2.6 and 2.7 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups.
HOLD
Bus Hold input requesting control of the bus.
HLDA
Bus Hold acknowledge output indicating release of the bus.
BREQ
Bus Request output activated when the bus controller has a pending external memory
cycle.
PMODE
Determines the EPROM programming mode.
PACT
A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates that ports 3 and 4 contain valid programming address/command
information (input to slave).
PROG
A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave).
PVER
A high signal in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates the byte programmed correctly.
CPVER
AINC
' Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
Auto Increment. Active low input enables the auto increment mode. Auto increment allows
reading or writing sequential EPROM locations without address transactions across the
PBUS for each read or write.
II
18-9
infel .
8XC196KD/8XC196KD20
ELECTRICAL CHARACTERISTICS
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. It is valid for the devices indicated in
the revision history. The specifications are subject to
change without notice.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature
Under Bias ..•.•............ - 55·C to + 125·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Condiiions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature ....•..... - 65·C to + 150·C
Voltage On Any Pin to Vss
Except EA and Vpp .......... -0.5V to + 7.0V(1)
Voltage from EA or
Vpp to Vss or ANGND ..•.•.. -0.5V to + 13.00V
Power Dissipation ....................... 1.~W(2)
NOTES:
1. This includes Vpp and EA on ROM or epu only devices.
2. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias Commercial Temp.
0
+70
·C
V
Vee
Digital Supply Voltage
4.50
5.50
VREF
Analog Supply Voltage
4.00
5.50
V
ANGND
Analog Ground Voltage
Vss - 0.4
Vss + 0.4
V(1)
Fose
Oscillator Frequency (8XC196KD)
8
16
MHz
Fose
Oscillator Frequency (8XC196KD20)
8
20
MHz
NOTE:
1. ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
VIL
(Over Specified Operating Conditions)
Description
Input Low Voltage
Min
Max
Units
-0.5
0.8
V
0.2 Vee + 1.0
Vee + 0.5
Test Conditions
VIH
Input High Voltage (Note 1)
VHYS
Hysteresis on RESET
VIH1
Input High Voltage on XTAL 1
0.7 Vee
Vee + 0.5
V
VIH2
Input High Voltage on RESET
2.2
Vee + 0.5
V
VOL
Output Low Voltage
0.3
0.45
1.5
V
V
V
VOL1
Output Low Voltage
in RESET on P2.5 (Note 2)
O.S
V
VOH
Output High Voltage
(Standard Outputs) (Note 4)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
IOH
IOH
IOH
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)
(Note 3)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
IOH
IOH
IOH
18-10
V
mV
300
Vee
=
=
=
=
IOL =
IOL
IOL
IOL
5.0V
200/LA
2.SmA
7mA
+0.4mA
= - 200 /LA
= -3.2mA
= -7mA
= -10/LA
= -30/LA
= -60/LA
8XC196KD/8XC196KD20
DC CHARACTERISTICS
Symbol
(Over Specified Operating Conditions) (Continued)
Description
Min
IOH1
Logical 1 Output Current in Reset
on P2.0. Do not exceed this or
device may enter test modes.
-0.8
11L1
Logical 0 Input Current in Reset
on P2.0. Maximum current that
must be sunk by external device
to ensure test mode entry.
IIH1
Logical 1 Input Current. Maximum
current that external device must
source to initiate NMI.
III
Typ
Max
Units
Test Conditions
rnA
VIH
=
Vcc - 1.5V
-12.0
rnA
VIN
=
0.45V
+200
""A
VIN
=
2.4V
Input Leakage Current (Std.
Inputs) (Note 5)
±10
""A
o<
VIN < Vcc - 0.3V
ILl1
Input Leakage Current (Port 0)
±3
""A
0< VIN < VREF
ITL
1 to 0 Transition Current (QBD
Pins)
-650
""A
VIN
=
2.0V
IlL
Logical 0 Input Current (QBD Pins)
-70
/LA
VIN
11L1
AD Bus in Reset
-70
/LA
VIN
=
=
0.45V
Icc
Active Mode Current in Reset
65
75
rnA
XTAL1 = 16 MHz
Vcc = Vpp = VREF
=
5.5V
80
92
rnA
XTAL1 = 20 MHz
Vcc = Vpp = VREF
=
5.5V
IIDLE
Idle Mode Currel')t (8XC196KD)
17
25
rnA
XTAL1 = 16MHz
Vcc = Vpp = VREF
=
5.5V
IIDLE
Idle Mode Current (8XC196KD20)
21
30
rnA
XTAL1 = 20 MHz
Vcc = Vpp = VREF
=
5.5V
IpD
Powerdown Mode Current
8
'15
""A
Vcc
IREF
AID Converter Reference Current
2
5
rnA
Vcc
RRST
Reset Pullup Resistor
65K
n
Vcc
Cs
Pin Capacitance (Any Pin to VSS)
10
pF
(8XC196KD)
Icc
Active Mode Current in Reset
(8XC 196KD20)
6K
=
=
=
0.45V
Vpp
Vpp
=
=
VREF = 5.5V
VREF
5.5V, VIN
=
=
5.5V
4.0V
NOTES:
1. All pins except RESET and XTAL1.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
4. Standard Outputs include ADO-15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
5. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
6. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self ,limiting
IOH on Standard Output pins: 10 mA
7. Maximum current per bus pin (data and control) during normal operation is ±3.2 mAo
8. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOL: 29 mA
IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 mA
IOH: 26 mA
P2.5, P2.7, WR, BHE
IOL: 13 mA
IOH: 11 mA
ADO-AD15
IOL: 52 mA
IOH: 52 mA
RD, ALE, INST-CLKOUT IOL: 13 mA
IOH: 13 mA
18-11
a.
8XC196KD/8XC196KD20
100
ICC Max
90
/
80
/"
70
rnA
//
60
50
/. V"
40
10
V/"
D
30
20
ICC Typ
~
IL
~
o Fo 4.0
--
~
,...-- ~
8.0
12.0
16.0
'DLE Max
'DLE Typ
20.0
Freq (MHz)
272145-5
ICC Max = 4.13 X Frequency + 9 mA
Icc Typ = 3.50 X Frequency + 9 mA
I'DLE Max = 1.25 X Frequency + 5 mA
I'DLE Typ = 0.88 X Frequency + 3 mA
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. Icc and IIDLE vs Frequency
AC CHARACTERISTICS
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, Fosc = 16 MHz
The system must meet these specifications to work with the 80C196KD:
Symbol
Description
TAVYV
Address Valid to READY Setup
hLYV
ALE Low to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
hLYX
READY Hold after ALE Low
TAVGV
Address Valid to Buswidth Setup
TLLGV
ALE Low to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
Min
Max
Units
2 Tosc - 68
ns
Tosc - 70
ns
No upper limit
Notes
(Note 3)
ns
0
Tosc - 30
ns
(Note 1)
Tosc- 15
2 Tosc - 40
ns
(Note 1)
2 Tosc - 68
ns
Tosc - 60
ns
(Note 3)
,
ns
0
3 Tosc - 55
ns
(Note 2)
RD Active to Input Data Valid
Tosc - 22
ns
(Note 2)
TCLDV
CLKOUT Low to Input Data Valid
Tosc - 45
ns
TRHDZ
End of RD to Input Data Float
Tosc
ns
TRXDX
Data Hold after RD Inactive
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tasc • N, where N = number of wait states.
3. These timings are included for compatibility with. older - 90 and BH products. They should not be used for newer high·
speed designs.
18-12
int:eL
axe 196KD/axe 196KD20
AC CHARACTERISTICS
(Continued)
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, FOSC = 16/20 MHz
The 80C196KD will meet these specifications:
Symbol
FXTAL
Description
Frequency on XTAL 1 (8XC196KD)
FXTAL
Frequency on XTAL 1 (8XC196KD20)
Tosc
I/FxTAL (8XC196KD)
Tosc
I1FXTAL (8XC196KD20)
TXHCH
XTAL 1 High to CLKOUT High or Low
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
Min
Max
Units
Notes
8
16
MHz
(Note 1)
8
20
MHz
(Note 1)
62.5
125
ns
50
125
ns
+20
+ 110
ns
ns
2 Tosc
Tosc - 10
Tosc+ 15
ns
TCLLH
CLKOUT Falling Edge to ALE Rising
-5
+15
ns
TLLCH
ALE Falling Edge to CLKOUT Rising
-20
+15
ns
TLHLH
ALE Cycle Time
TLHLL
ALE High Period
TosC - 10
TAVLL
Address Setup to ALE Falling Edge
Tosc - 15
TLLAX
Address Hold after ALE Falling Edge
Tosc - 35
ns
TLLRL
ALE Falling Edge to RD Falling Edge
Tosc - 30
ns
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
ns
4 Tosc
+4
Tosc+ 10
+30
ns
ns
Tosc + 25
ns
(Note 2)
+5
ns
+25
ns
+15
ns
ns
(Note 4)
TOSC - 23
-5
TWLWH
WR Low Period
Tosc - 20
ns
TWHQX
Data Hold after WR Rising Edge
Tosc - 25
ns
TWHLH
WR Rising Edge to ALE Rising Edge
Tosc - 10
TWHBX
SHE, INST after WR Rising Edge
Tosc - 10
ns
TWHAX
AD8-15 HOLD after WR Rising
Tosc - 30
ns
TRHBX
SHE, INST after RD Rising Edge
TOSC - 10
ns
TRHAX
AD8-15 HOLD after RD Rising
Tosc - 25
ns
Tosc + 15
ns
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are Lised, add 2 Tase • N, where N = number of wait states.
18-13
(Note 4)
(Note 4)
ToSC - 10
0
..-
ns
TOSC - 5
Tosc
-I
(Note 4)
(Note 2)
(Note 3)
(Note 3)
intel..
8XC196KD/8XC196KD20
£@W£OO©[g OOOIP@OOIMl~jj'O@OO
System Bus Timings
XTALI
CLKOUT
ALE
BUS
AD_D_R_ES_S_O_U_T~_),,)({
BUS - { , ,_ _ _
I
DATA OUT
I
})((
ADDRESS
....- - - - - - - -
LTRHBX •
fTwHBX
BHE,INST
ADS-IS
VALID
ADDRESS OUT
272145-6
18-14
inteL
~[Q)W~OO©~ OOOIP@!ruIMl~iiO@OO
8XC196KD/8XC196KD20
READY Timings (One Wait State)
XTAL 1
CLKOUT
ALE
READY
_+_______.." f-oo--,----
TRLRH + 2Tose ----:~-------_
READ
BUS
-<
lRLDV + 2 lose
TAVDV + 2 Tose
ADDRESS OUT
I
-<
~
(
DATA
I
WRITE
BUS
)
ADDRESS OUT
I
{
IWI
lWLWH + 2 Tose
TQVWH + 2 Tose
DATA OUT
d
»»»)
X
ADDRESS
272145-7
Buswidth Timings
XTAL 1
272145-8
18-15
8XC196KD/8XC196KD20
HOLD/HLDA TIMINGS
Symbol
Description
Min
Max
Units
Notes
ns
(Note 1)
THVCH
HOLD Setup
+55
TCLHAL
CLKOUT Low to HLDA Low
-15
+15
ns
TCLBRL
CLKOUT Low to SREQ Low
-15
+15
ns
THALAZ
HLDA Low to Address Float
+15
ns
THALBZ
HLDA Low to SHE, INST, RD, WR Weakly Driven
+20
ns
TCLHAH
CLKOUT Low to HLDA High
-15
+15
ns
TCLBRH
CLKOUT Low to SREQ High
-15
+15
ns
THAHAX
HLDA High to Address No Longer Float
-15
THAHBV
HLDA High to SHE, INST, RD, WR Valid
-10
+15
ns
TCLLH
CLKOUT Low to ALE High
-5
+15
ns
ns
NOTE:
1. To guarantee recognition al next clock.
DC SPECIFICATIONS IN HOLD
Description
Min
Max
Weak Puliups on ADV, RD,
WR, WRL,SHE
50K
250K
VCC
=
5.5V, VIN
=
0.45V
Weak Pulidowns on
ALE,INST
10K
50K
Vcc
=
5.5V, VIN
=
2.4
Units
BUS - { \ ._ _ __
BHE,INST
RD,WR
ALE
\
______~_LL_H~t=-~s-~______~i1-51
~
\
___________
272145-9
18-16
iniaL
8XC196KD/8XC196KD20
~[Q)W~OO©[§ OOOIF@~~~iiO@OO
MAXIMUM HOLD LATENCY
Bus Cycle Type
Internal Execution
1.5 States
16-Bit External Execution
2.5 States
8-Bit External Execution
4.5 States
EXTERNAL CLOCK DRIVE (8XC196KD)
Symbol
Parameter
Min
Max
Units
8
16.0
MHz
62.5
125
ns
1/TXLXL
Oscillator Frequency
TXLXL
Oscillator Period
TXHXX
High Time
20
ns
TXLXX
Low Time
20
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
EXTERNAL CLOCK DRIVE (8XC196KD20)
Symbol
Parameter
Min
Max
Units
1/TxLXL
Oscillator Frequency
8
20.0
MHz
TXLXL
Oscillator Period
50
125
TXHXX
High Time
17
TXLXX
Low Time
17
TXLXH
Rise Time
8
ns
TXHXL
Fall Time
8
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272145-10
•
18-17
intel~
8xe 196KD/8xe 196KD20
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
Cl
vee
Vss
II {
-+--T---I XTAL 1
t-
BXC196KD
. - 14.7K*
EXTERNAL
CLOCK INPUT
XTAL2
XTALI
clock driver
Quartz Crystal or
8XC196KD
no connect- XTAL2
Ceramic Resonator
272145-13
272145-14
NOTE:
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and Vss. When
using ceramic crystals, C1 = 20 pF, C2 = 20 pF.
When using ceramic resonators consult manufacturer
for recommended capacitor values.
-Required if TTL driver used.
Not needed if CMOS driver is used.
AC TESTING INPUT, OUTPUT WAVEFORMS
2.4
0.45
~ 2.0> TEST POINTS
<
- - " 0.8
2.0
0.8
FLOAT WAVEFORMS
V-~
272145-11
AC Testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic
"1" and O.BV for a Logic "0".
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs, and Begins to Float
when a 150 mV change from the Loaded VOHIVOL Level occurs
IOL/IOH ~ ±15 mAo
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H- High
L- Low
V- Valid
A- Address
B- BHE
C- CLKOUT
0- DATA
G- Buswidth
H- HOLD
HA-HLDA
xz-
No Longer Valid
Floating
18-18
L- ALE/ADV
BR-BREQ
R- RD
W- WR/WRH/WRL
X- XTAL1
Y- READY
Q- Data Out
intel~
8xe 196KD/8xe 196KD20
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE 0)
Symbol
Parameter
Min
Units
4 Tosc +50
ns
TXLXL
Serial Port Clock Period (BRR
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR ;:0: 8002H)
TXLXL
Serial Port Clock Period (BRR = 8001 H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)
2 Tosc -50
TQVXH
Output Data Valid to Clock Rising Edge
2 Tosc - 50
ns
TXHQX
Output Data Hold after Clock Rising Edge
2 Tosc - 50
ns
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX
Input Data Hold after Clock Rising Edge
TXHQZ
Last Clock Rising to Output Float
;:0:
8002H)
Max
ns
6 Tosc
4 Tosc -50
ns
4 Tosc
2 Tosc +50
2 TosC + 50
ns
ns
Tosc +50
ns
0
ns
1 Tosc
ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-5HIFT REGISTER MODE (MODE 0)
272145-15
•
18-19
intel~
8XC196KD/8XC196KD20
A to D CHARACTERISTICS
The AID converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
10-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature Commercial Temp.
0
+70·
°c
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.00
5:50
V
ANGND
Analog Ground Voltage
VSS - 0.40
Vee + 0.40
V
/Ls(1)
1.0
TSAM
Sample Time
TeONV
Conversion Time
10
20
/Ls(1)
Fose
Oscillator Frequency (8XC196KD)
8.0
16.0
MHz
Fose
Oscillator Frequency (8XC196KD20)
8.0
20.0
MHz
NOTE:
1. The value of AD_TIME is selected to meet these specifications.
10-BIT MODE AID CHARACTERISTICS (Over Specified Operating Conditions)
Parameter
Typical(1)
R.esolution
Minimum
Maximum
Units'
1024
10
1024
10
Levels
Bits
0
±3
LSBs
Absolute Error
Full Scale Error
0.25 ± 0.5
LSBs
Zero Offset Error
0.25 ± 0.5
LSBs
Non-Linearity
1.0 ± 2.0
Differential Non-Linearity Error
0
±3
LSBs
> -1
+2
LSBs
0
±1
LSBs
Channel-to-Channel Matching
±0.1
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBrC
LSBrC
LSBrC
-60
Off Isolation
Notes
dB
2,3
2
Feedthrough
-60
dB
Vee Power Supply Rejection
-60
dB
2
750
1.2K
n
4
ANGND - 0.5
VREF + 0.5
V
5,6
0
±3.0
/LA
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
3
pF
NOTES:
'An "LSB" as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for AI D glossary of terms.)
1. These values are expected for most parts at 25'e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to ± 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
18-20
int:et
8XC196KD/8XC196KD20
8-BIT MODE AID OPERATING CONDITIONS
Description
Min
Max
Units
TA
Symbol
Ambient Temperature Commercial Temp.
0
+70
·C
Vee
Digital Supply Voltage
4.50
5.50
V
V
VREF
Analog Supply Voltage
4.00
5.50
ANGND
Analog Ground Voltage
Vss -0040
Vss + 0040
TSAM
Sample Time
TeoNv
Conversion Time
7
20
/LS(1)
Fose
Oscillator Frequency (8XC109KD)
8.0
16.0
MHz
Fose
Oscillator Frequency (8XC196KD20)
8.0
20.0
MHz
1.0
V
/Ls(1)
NOTE:
1. The value of AD_TIME is selected to meet these specifications.
8-BIT MODE AID CHARACTERISTICS
Typical(1)
Parameter
(Over Specified Operating Conditions)
Minimum
Maximum
Units·
256
8
256
8
Levels
Bits
0
±1
LSBs
Resolution
-
Absolute Error
Full Scale Error
±0.5
Zero Offset Error
±0.5
LSBs
LSBs
0
±1
LSBs
>-1
+1
LSBs
±1
LSBs
Non-Linearity
Differential Non-Linearity Error
Notes
Channel-to-Channel Matching
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
LSBrC
LSBrC
LSBrC
-60
dB
2,3
Feedthrough
-60
dB
2
Vee Power Supply Rejection
-60
dB
2
n
4
5,6
Off Isolation
750
1.2K
Vss - 0.5
VREF + 0.5
V
0
±3.0
/LA
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
3
pF
NOTES:
• An "LSB" as used here has a value of approximately 20 mY. (See Embedded Microcontrollers and Processors Handbook
for AID glossary of terms).
.
• 1. These values are expected for most parts at 25·e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if pin current is limited to ±2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
18-21
•
intel .
8XC196KD/8XC196KD20
EPROM SPECIFICATIONS
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature During Programming
20
30
Vee
Supply Voltage During Programming
4.5
5.5
C
V(1)
VREF
Reference Supply Voltage During Programming
4.5
5.5
V(1)
Vpp
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
Fose
Oscillator Frequency during Auto and Slave
Mode Programming
6.0
8.0
MHz
Fose
Oscillator Frequency during
Run-Time Programming (8XC196KD)
6.0
16.0
MHz
Fose
Oscillator Frequency during
Run-Time Programming (8XC196KD20)
6.0
20.0
MHz
NOTES:
1. Vee and VREF should nominally be at the same voltage during programming.
2. Vpp and VEA must never exceed the maximum specification, or the device may be damaged.
3. Vss and ANGND should nominally be at the same potential (OV).
4. Load capacitance during Auto and Slave Mode programming = 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)
Symbol
Description
Min
Max
Units
TSHLL
Reset High to First PALE Low
1100
Tose
TLLLH
PALE Pulse Width
50
Tose
TAVLL
Address Setup Time
0
Tose
TLLAX
Address Hold Time
100
Tose
TpLDV
PROG Low to Word Dump Valid
50
Tose
TpHDX
Word Dump Data Hold
50
Tose
TDVPL
Data Setup Time
0
Tose
TpLDX
Data Hold Time
400
Tose
TpLPH(1)
PROG Pulse Width
50
Tose
TpHLL
PROG High to Next PALE Low
220
Tose
TLHPL
PALE High to PROG Low
220
Tose
TpHPL'
PROG High to Next PROG Low
220
Tose
TpHIL
PROG High to AINC Low
TiLtH
AINC Pulse Width
0
Tose
240
Tose
Tose
TILVH
PVER Hold after AINC Low
50
TILPL
AINCLow to PROG Low
170
TpHVL
PROG High to PVER Valid
NOTE:
Tose
220
.
Tose
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
18-22
int:eL
8XC196KD/8XC196KD20
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Vpp Supply Current (When Programming)
Ipp
NOTE:
Do not apply Vpp until Vee is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
---I
j;.TAVlL
PORTS
1/
'"
3/4
-
+j
ADDR/COMMAND
TSHLL
/7"
/
TLLAX -
\
DATA
TOVPL
'"
/
/~
f4- TpLOX ..
\
I
_ _ TLLLH--oo
ADDR/COMMAND
~ TLHPL "" I-- TpLPH -
\
1+ TpHLL ..-
V
\
PVER
I-- TpHVL 272145-16
NOTE:
P3.0 must be high ("1 ")
II
18-23
intel~
8XC196KD/8XC196KD20
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
---J
I
PORTS
/"
3/4
t- -
TpLDV -
I - TSHLL -
\
/
\
T1LPL
ADDR
I
......VER BITS/WD DUt.4P'
ADDR/COt.4t.4AND "-
TpHDX
r-
H-TPLDV -
/
---
~
ADDR+ 2
fVER BITS/WD DUt.4P
\
TpHDX
-
-
1I
TpHPL -
\
272145-17
NOTE:
P3.0 must be low ("0")
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND
AUTO INCREMENT
ADDR
-«
PO:;! _ _ _ _
ADDR/COt.4t.4AND>----<
DATA
ADDR
)>--......~
ADDR + 2
DATA
>--
PVER
• 272145-18
18-24
8XC196KD/8XC196KD20
3. Changed OFP Package 8JA to 56°C/W from
42°C/W.
8XC196KC TO 8XC196KD DESIGN
CONSIDERATIONS
4. Changed VHYS to 300 mV from 150 mY.
1. Memory Map. The 8XC196KD has 1024 bytes of
RAM/SFRs and 32K of OTPROM. The extra 512
bytes of RAM reside in locations 0200H to
03FFH, and the extra 16 Kbytes of OTPROM reside in locations 6000H to 9FFFH. On the
87C196KC these locations are always external,
so KC code may have to be modified to run on
the KD.
5. Changed Icc Typical specification at 16 MHz to
65 rnA from 50 rnA.
6. Changed Icc Maximum specification at 16 MHz
to 75 rnA from 70 rnA.
7. Changed IIOLE Typical specification to 17 rnA
from 15 rnA.
8. Changed IIOLE Maximum specification to 25 rnA
from 30 rnA.
2. The vertical window scheme has been extended
to include all on-chip RAM.
3. IOC3.1 controls the CLKOUT signal. This bit must
be 0 to enable CLKOUT.
4. The 87C196KD has a different autoprogramming
algorithm to support 32K of on-chip OTPROM.
9. Changed Ipo Typical specification to 8 p.A from
15 p.A.
10. Added Ipo Maximum specification.
11. Changed T CLOY Maximum specification to
Tasc - 45 from Tasc - 50.
12. Changed T LLAX Minimum specification to
Tasc - 35 from T asc - 40.
13. Changed TCHWH Minimum specification to - 5
from -10.
XC196KD ERRATA
8XC196KD
14. Changed TRHAX Minimum specification to
Tasc- 25 from Tasc - 30.
None known.
15. Changed T HALAZ Maximum specification to
+ 15 from + 10.
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a "B" at the
end of the topside tracking number. Data sheets are
changed as new device information becomes available. Verify with your local Intel sales office that you
have the latest version before finalizing a design or
ordering devices.
The following are important differences between the
272145-001 and 272145-002 data sheets:
16. Changed T HALBZ Maximum specification to
+20 from +15.
17. Added T HAHBV Maximum specification.
18. Changed TSAM for 10-bit mode to 1 p.s from
3 p.s.
19. Changed TSAM for 8-bit mode to 1 p.s from 2 p.s.
20. Changed IIH1 test condition to VIN = 2.4V from
5.5V.
1. Added 20 MHz specifications.
21. Changed IIH1 maximum specification to + 200
p.A from + 100 p.A.
2. Added 80-lead SOFP package pinout.
22. Removed NMI from list of standard inputs.
23. Updated Icc and IIOLE vs frequency graph.
24. Updated note under DC EPROM Programming
Characteristics.
25. Changed IU1 maximum specification to -12
rnA from -6 rnA.
III
18-25
8XL196KD
COMMERCIAL CHMOS MICROCONTROLLER
87L196KD-32 Kbytes of On-Chip OTPROM
to 3.6V Operation
• 3.0V
16 MHz Operation
• 1000 Byte Register RAM
• Register-to-Register Architecture
• 28 Interrupt Sources/16 Vectors
• Peripheral Transaction Server
• 1.75 ,..,s 16 x 16 Multiply (16 MHz)
• 3.0 ,..,s 32/16 Divide (16 MHz)
• Powerdown and Idle Modes
• Five8-Blt I/O Ports
•
• 16-Bit Watchdog Timer
Configurable 8-Blt or
• Dynamically
16-Bit. Buswidth
Duplex .Serlal Port
• Full
High Speed I/O Subsystem
• 16-Bit Timer
• 16-Bit Up/Down Counter with Capture
• 3 Pulse-Width-Modulated Outputs
• Four 16-Blt Software Timers
• 8- or 10-Blt A/D Converter with
• Sample/Hold
Version
• OTP One-Time
Programmabl~
The 8XL196KD 16-bit microcontroller is a high performance member of the MCS®-96 microcontroller family.
The 8XL196KD is an enhanced 80C196KC device with 3.3V operation, 1000 bytes RAM, 16 MHz operation
and an optional 32 Kbytes of ROM/EPROM. Intel's CHMOS III-E process provides a high performance processor along with low power consumption.
Four high-speed capture inputs are· provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or up/down counter.
MCSaD·96 is a registered trademark of Intel Corporation.
18·26
October 1992
Order Number: 272254-001
int:el.
VREF
8XL196KD
ANGND
CONTROL
SIGNALS
} ~~~:
BUS
--....."
PORT 4
r;;;::;:;;;-""--I~. PWM 1
~';;';';..I----1I-. PWM2
AID
HSI HSO
PORT 1
272254-1
Figure 1. 8XL 196KD Block Diagram
87L 196KD ENHANCED FEATURE SET
OVER THE 87C196KC
1. The 87l196KD has twice the RAM and twice the
OTPROM space of the 87C196KC.
2. The vertical windowing scheme has been extend·
ed to allow all 1000 bytes of register RAM to be
windowed into the lower register file.
FUNCTIONAL DIFFERENCES
BETWEEN THE 8XC196KD AND THE
8XL196KD
1. The HOlD/HlDA bus protocol is not supported
on the 8Xl196KD.
2. The ClKOUT disable bit (IOC3.1) is not support·
ed on the 8Xl196KD.
.
3. Run·time programming is not supported on the
8Xl196KD.
II
18·27
intel.,
8XL196KD
Table 3. 32-Byte Windows
8XL 196KD VERTICAL WINDOWING
MAP
Address to
Remap
Table 1. 12S·Byte Windows
Address to
Remap
Device
Series
0380H
KD
X001 0111B
KD
X001 0110B
0280H
KD
X001 0101B
0200H
KD
X001 0100B
0180H
KC,KD
X001 0011 B
0100H
KC,KD
X001 0010B
0080H
KC,KD
X001 0001B
OOOOH
KC,KD
X001 OOOOB
=
=
=
=
=
=
=
=
X1011111B
KD
X1011110B
17H
03AOH
KD
X1011101B
16H
0380H
KD
X1 0111 OOB
15H
0360H
KD
X1011011B
14H
0340H
KD
X101 1010B
13H
0320H
KD
X1011001B
12H
0300H
KD
X101 1000B
11H
02EOH
KD
X101 0111B = 57H
10H
02COH
KD
X101 0110B = 56H
02AOH
KD
X101 0101B = 55H
0280H
KD
X101 0100B = 54H
0260H
KD
X101 0011B = 53H
0240H
KD
X101 0010B = 52H
0220H
KD
Xi01 0001B= 51H
Table 2. 64·Byte Windows
Device
Series
03COH
KD
0380H
KD
0340H
KD
0300H
KD
02COH
KD
0280H
KD
0240H
KD
0200H
KD
01COH
KC,KD
0180H
KC,KD
0140H
KC,KD
0100H
KC,KD
OOCOH
KC,KD
0080H
KC,KD
0040H
KC,KD
OOOOH
KC,KD
WSR Contents
=
X010 1110B =
X010 1101 B =
X010 1100B =
X010 1011 B =
X010 1010B =
X010 1001B =
X010 1000B =
X010 0111 B =
X010 0110B =
X0100101B =
X010 01 OOB =
X0100011B =
X010 001 OB =
X0100001B =
X010 OOOOB =
X010 1111 B
=
=
=
=
=
=
=
=
KD
03COH
Window In Lower Register File: 80H-FFH
Address to
Remap
WSR Contents
03EOH
WSR Contents
0300H
Device
Series
2FH
5FH
5EH
5DH
5CH
5BH
5AH
59H
58H
2EH
0200H
KD
X101 OOOOB = 50H
2DH
01EOH
KC,KD
X100 1111B = 4FH
2CH
01COH
KC,KD
X100 1110B = 4EH
2BH
01AOH
KC,KD
X100 1101B = 4DH
2AH
0180H
KC,KD
X100 1100B = 4CH
29H
0160H
KC,KD
X100 1011B =4BH
28H
0140H
KC,KD
X100 1010B = 4AH
27H
0120H
KC,KD
X1001001B = 49H
26H
0100H
KC,KD
X100 1000B = 48H
25H
OOEOH
KC,KD
X1000111B = 47H
24H
OOCOH
KC,KD
X1000110B = 46H
23H
OOAOH
KC,KD
X100 0101B = 45H
22H
0080H
KC,KD
X100 0100B = 44H
21H
0060H
KC,KD
X100 0011 B = 43H
20H
0040H
KC,KD
X100 001 OB = 42H
0020H
KC,KD
X100 0001B = 41H
OOOOH
KC,KD
X100 OOOOB = 40H
Window In Lower Register File: COH-FFH
Window in Lower Register File: EOH-FFH
18·28
inteL
8XL196KD
Table 5. 8XL 196KD Memory Map
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
Y
~
x ~L
~D"".SP
•• d'
~ Not.4ark=16t.1Hz
KD Product Family
Description
Address
External Memory or I/O
OFFFFH
OAOOOH
Internal ROM/OTPROM or External
Memory (Determined by EA)
9FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
Port 3 and Port 4
Word Addressable Only
1FFFH
1FFEH
External Memory
1FFDH
0400H
1000 Bytes Register RAM (Note 1)
03FFH
0018H
CPU SFR's (Notes 1, 3)
0017H
OOOOH
3.3V CHt.40S Technology
Program t.lemory Options!
7 = EPROM (Note 1)
' - - - - - - - - - - Package Type Options:
=
=
N 58-leod fLee
s 80-lead QFP
S8 = SO-lead sQrp
' - - - - - - - - - - - Temperature and Burn-in Options:
No t.lark = OOC - 700C Ambient with
Intel Standard Burn-in
272254-2
EXAMPLE: NB7l196KD is 6B·Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240BOO).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 2. The 8XL 196KD Family Nomenclature
Table 4. Thermal Characteristics
Package
Type
8ja
8jc
PLCC
35°C/W
13°C/W
OFP
56°C/W
12°C/W
SOFP
TBD
TBD
All thermal impedance data IS approximate for static air
conditions at1 W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240BOO) for a
description of Intel's thermal impedance test methodology.
NOTES:
1. Code executed in locations OOOOH to 03FFH will be
forced external-.
2. Reserved memory locations must contain OFFH unless
noted.
3. Reserved SFR bit locations must contain O.
4. Refer to BXC196KC for SFR descriptions.
5. WARNING: Reserved memory locations must not be •
written or read. The contents and/or function of these 10·
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
18-29
"
intet
~~©[Q)QlJ©1J ~~~~D~W
8XL196KD
..
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"....
z
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... "-'"
0
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Q
0
Q
0
::E
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0..
0..
.. .. .. ..
'"'" '" '" '"'"
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U
U
U
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00..
U
Si
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liJ
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III
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X
X
U
....
'"Q
~
en
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CD
I~
....
en "~
~
«
I~
ACHS/PMODE.1/PO.S
P3.0/ADO
ACH4/PMODE.O/PO.4
P3.1/AD1
ANGND
P3.2/AD2
VREF
P3.3/AD3
S8-PIN PLCC
N87L 196KD
Vss
EXTINT IPRoG/P2.2
P3.4/AD4
P3.S/ADS
RESET
P3.S/ADS
RXO/PAIT/P2.1
P3.7/AD7
TOP VIEW
TXO/PVER/P2.0
P4.0/AD8
P4.1/AD9
PLO
P4.2/AD10
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
PL1
PL2
PWM.1/PL3
P4.3/AD11
P4.4/AD12
P4.S/AD13
PWM.2/PL4
HSI.O
P4.S/AD14
HSI.1
P4.7/A015
P2.3/T2CLK
HSI.2/HSO.4
27
28
0
29
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'"~ '" '"
"iii
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30
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31
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32
33
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38
VI
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u
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u
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N
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Figure 3. 6S-Pin PLCC Package
18-30
39
0-
"0
:oi
~
0-
41
I~
I~
42
...
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0..
I~·
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43
>-
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en
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272254-3
intel~
8XL196KD
N
Cl
...
...
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"- "- "~
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<
Cl
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Cl
Cl
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a.
Cl
<
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en
Cl
<
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Cl
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Cl
<
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Cl
Cl
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... ...a. ...a. ...a. ......a. ...a. a.... ...a.
"- ""- "- "- "- "~ "r-- "0
N
~ ,,;
"' '" r-'"
a.
AD1/P3.1
P2.3/T2CLK
ADO/P3.0
VSS
RD
READY
ALE/ADV
P2.4/T2RST / AINC
INST
BHE/WRH
BUSWIDTH
WR/WRL
CLKOUT
80-PIN QFP
S87L196KD
XTAL2
P2.5/PWM.O
P2. 7/T2CAPTUREjPAcT
XTAL 1
Vpp
VSS
VSS
VSS
VSS
Vee
HSO.3
TOP VIEW
Vee
Vee
Eli
VSS
NMI
HSO.2
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
ACH3/PO.3
ACH l/PO.l
ACHO/PO.O
P2.6/T2UP-DN/CPVER
Pl.7
Pl.6
Pl.5
ACH2/PO.2
ACH6/PMODE.2/PO.6
HSO.l
ACH7 /EXTINT /PMODE.3/PO. 7
HSO.O
N.C.
HSO.5/HSI.3
ACH5/PMODE. 1/PO.5
Vss
ACH4/PMODE.O/PO.4
HSOA/HSI.2
Vl
N
'"
w
Vl
•
Vl 0
LU
z ""
N
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a. N
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LU
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Cl ">-Z
x Cl
x
Cl
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LU
0
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a.
;;:
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~ "N
~
a.
~
iii iii
:z: :z:
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a.
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272254-4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 4. BO-Pin QFP Package
II
18-31
8XL196KD
Rii
READY
ALE/ADV
P2.4/T2RST / AINC
INST
BHE/WRH
BUSWIDTH
WR.!WRC
CLKOUT
P2.5/PWM.O
80 PIN SQFP
XTAL2
P2. 7 /T2CAPTURE/PACT
SB87L196KD
XTAL1
Vpp
VSS
Vss
Vss
Vss
vee
vee
EA
51
TOP VIEW
HSO.3
Vee
Vss
NMI
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD
N.C.
ACH3/PO.3
ACH1/PO.l
HSO.2
P2.6/T2UP-DN/CPVER
PI.7
PI.6
ACHO/PO.O
PI.5
ACH2/PO.2
HSO.l
ACH6/PMODE.2/PO.6
HSO.O
ACH7/PMODE.3/PO.7
HSI.3/HSO.5
"'"
en
en '"•
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~
"-
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UII-...en
U ...
>
en
en
>
0
•
0::
a..
'"
Z
;::
r:i
272254-5
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 5. SO-Pin SQFP Package
18·32
intel .
8XL196KD
PIN DESCRIPTIONS
Symbol
Name and Function
Vee
Main supply voltage (3.3V).
Vss
Digital circuit ground (OV). There are multiple Vss pins, all of which must be connected.
VREF
Reference voltage for the AID converter (3.3V). VREF is also the supply voltage to the
.analog portion of the AID converter and the logic used to read Port O. Must be connected
for AID and Port 0 to function.
ANGND
Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·
Vpp
Timing pin for the return from powerdown circuit. This pin also supplies the programming
.
voltage on the EPROM device.
XTAL1
Input of the oscillator inverter and of the internal clock generator.
XTAL2
GLKOUT
Output of the oscillator inverter.
. Output of the internal clock generator. The frequency of GLKOUT is
frequency.
% the oscillator
RESET
Reset input and open drain output.
BUSWIDTH
Input for buswidth selection. If GGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If GGR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA
Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 9FFFH to be directed to on-chip ROM/EPROM. EA equal low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by GGR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ALE/ ADV is activated only during
external memory accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the GGR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
Bus High Enable or Write High output to external memory, as selected by the GGR. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external
writes where an odd byte is being written. BHE/WRH is activated only during external
memory writes.
READY
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. When the external memory is not being used, READY has no
effect.
HSI
Inp'uts to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
18-33
infel .
8XL196KD.
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
PortO
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter.
Port 1
8-bit quasi-bidirectional I/O port.
Port 2
8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KD.
Pins 2.6 and 2.7 are quasi-bidirectional,
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
PMODE
Determines the OTPROM programming mode.
PACT
A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
PALE
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates that ports 3 and 4 contain valid programming address/command
information (input to slave).
PROG
A falling edge in Slave Programming Mode indicates that ports 3 and 4' contain valid
programming data (input to slave).
PVER
A high signal in Slave Programming Mode and Auto Configuration Byte Programming
Mode indicates the byte programmed correctly.
CPVER
Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
AINC
Auto Increment. Active low input enables the auto increment mode. Auto increment allows
reading or writing sequential EPROM locations without address transactions across the
PBUS for each read or write.
18-34
int:eL
8XL196KD
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on
products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is available.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias ................. - 55°C to + 125°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin to Vss
Except EA and Vpp .......... -0.5V to + 7.0V(1)
Voltage from EA or
Vpp to Vss or ANGND ....... - 0.5V to + 13.00V
Power Dissipation ....................... 1.5W(2)
NOTES:
1. This includes Vpp and EA on ROM or epu only devices.
2. Power dissipation is based on package heat transfer lim.
itations, not device power consumption.
TARGETED OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias
0
+70
°C
V
Vee
Digital Supply Voltage
3.00
3.60
VREF
Analog Supply Voltage
3.00
3.60
V
Vss - 0.3
Vss + 0.3
V(1)
8
16
MHz
ANGND
Analog Ground Voltage
Fose
Oscillator Frequency
NOTE:
1. ANGND and Vss should be nominally aLthe same potential.
TARGETED DC CHARACTERISTICS
Symbol
Description
(Over Specified Operating Conditions)
Min
Max
Units
VIL
Input Low Voltage
-0.3
0.8
V
VIL1
Input Low Voltage on QuasiBidirectional Pins
-0.3
+0.7
V
VIL2
Input Low Voltage on Reset
-0.3
+0.6
V
Vee + 0.3
VIH
Input High Voltage (Note 1)
2.0
VHYS
Hysteresis on RESET
150
VIH1
Input High Voltage on XTAL 1
0.7 Vee
Vee + 0.3
V
VIH2
Input High Voltage on RESET
2.2
Vee + 0.3
V
0.4
V
VOL
Output Low Voltage
VOL1
Output Low Voltage
in RESET on P2.5 (Note 2)
VOH
Output High Voltage
(Standard Outputs) (Note 4)
2.4
VOH1
Output High Voltage
(Quasi-bidirectional Outputs)
(Note 3)
2.4
18-35
V
mV
0.8
Test Conditions
Vee
=
3.3V
=
=
2.0 mA
IOL
V
IOH
=
-2.0 mA
V
IOH
=
-30 p.A
V
IOL
+0.4 mA
..
int:el..
8XL196KD
TARGETED DC CHARACTERISTICS
Symbol
Description
(Over Specified Operating Conditions) (Continued)
Min
Typ
Max
Units
Test Conditions
mA
VIH
=
2.0V
TBD
mA
VIN
=
0.45V
Logical 1 Input Current. Maximum
current that external device must
source to initiate NMI.
TBD
/LA
VIN
=
2.0V
Input Leakage Current (Std. Inputs)
(Note 5)
±10
/LA
o<
VIN < Vcc - 0.3V
±3
/LA.
0< VIN < VREF
-650
/LA
VIN
IOHl
Logical 1 Output Current in Reset
on P2.0. Do not exceed this or
device may enter test modes.
IIl2
Logical 0 Input Current in Reset on
P2.0. Maximum current that must
be sunk by external device to
ensure test mode entry.
IIHI
Iu
lUI
Input Leakage Current (Port 0)
ITl
1 to 0 Transition Current (QBD Pins)
TBD
=
=
=
1.2V
III
Logical 0 Input Current (QBD Pins)
-70
/LA
VIN
11L1
AD Bus in Reset
-70
/LA
VIN
Icc
Active Mode Current in Reset
30
40
mA
XTAL1 = 16MHz
Vcc = Vpp = VREF
IIDlE
Idle Mode Current
10
15
mA
XTAL1 = 16MHz
Vcc = Vpp = VREF
IpD
Powerdown Mode Current
8
15
/LA
Vcc
IREF
AID Converter Reference Current
2
5
mA
Vcc
RRST
Reset Pullup Resistor
65K
11
Cs
Pin Capacitance (Any Pin to VSS)
10
pF
6K
=
=
0.40V
0.40V
Vpp
Vpp
=
=
VREF
VREF
=
3.6V
=
=
=
3.6V
3.6V
3.6V
NOTES:
1. All pins except RESET.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. QSD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
4. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, ClKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
5. Standard Inputs include HSI pins, READY, SUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2ClK/P2.3 and T2RST/P2.4.
6. Maximum current per pin must be externally limited to the fOllowing values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
7. Maximum current per bus pin (data and control) during normal operation is ±3.2 mAo
8. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
10L: 29 mA
IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 mA
IOH: 26 mA
P2.5, P2.7, WR, SHE
10L: 13 mA
IOH: 11 mA
ADO-ADI5
IOL: 52 mA
IOH: 52 mA
RD, ALE, INST-ClKOUT IOL: 13 mA
IOH: 13 mA
18-36
infel .
8XL196KD
50,---,----,----,---,
45r---~--_+----+_--~
40 r---~---+----+--,...,ICC Max
35r---~--_+--~~--~
30
rnA
r---~--~"'---_t__--~
ICC Typ
25r-~~--_+--~~--~
20~--~--~"'---_t__--~
15
r-~~--_+----+_===_,..j
IDLE Max
IIOLE Typ
10
5~~~~=+----+_--~
OL---~--~----~--~
o
4.0
8.0
12.0
16.0
FREQUENCY (101Hz)
272254-6
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 6. Icc and IIDLE vs Frequency
TARGETED AC CHARACTERISTICS
For use over· specified operating conditions.
Test Conditions: Capacitive load on all pins
= 100 pF,
Rise and fall times
= 10 ns,
Fosc
= 16 MHz
The system must meet these specifications to work with the SOL 196KD:
Symbol
Description
TAVYV
Address Valid to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
Min
Max
2 Tosc - 90
No upper limit
a
Units
ns
ns
Tosc - 30
ns
2 Tosc - 68
ns
a
(Note 1)
ns
3 Tosc - 60
ns
(Note 2)
(Note 2)
TRLDV
RD Active to Input Data Valid
Tosc - 30
ns
TCLDV
CLKOUT Low to Input Data Valid
Tosc - 50
ns
TRHDZ
End of RD to Input Data Float
Tosc
ns
TRXDX
Data Hold after RD Inactive
a
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC • N, where N = number of wait states.
18·37
Notes
ns
8XL196KD
TARGETED AC CHARACTERISTICS (Continued)
For use over specified operating conditions.
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, Fosc = 16 MHz
The 80L 196KD will meet these specifications:
Symbol
Description
Min
Max
Units
Notes
(Note 1)
FXTAL
Frequency on XTAL1
8
16
MHz
Tosc
II FXTAL
62.5
125
ns
+20
+ 110
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Falling Edge to ALE Rising
TLLCH
ALE Falling Edge to CLKOUT Rising
TLHLH
ALE Cycle Time
ns
2 Tosc
Tosc - 10
Tosc+ 15
ns
-10
+33
ns
-20
+15
ns
ns
4 Tosc
hHLL
ALE High Period
Tosc - 14
TAVLL
Address Setup to ALE Falling Edge
Tosc- 15
Tosc+ 1O
ns
TLLAX
Address Hold after ALE Falling Edge
Tosc - 40
ns
TLLRL
ALE Falling Edge to RD Falling Edge
Tosc - 42
ris
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
hLWL
ALE Falling Edge to WR Falling Edge
TCLWL
CLKOUT Low to WR Falling Edge
TQVWH
Data Stable to WR Rising Edge
+4
+30
(Note 4)
ns
Tosc - 5
ns
(Note 4)
Tosc
Tosc + 37
ns
(Note 2)
+5
ns
ns
Tosc - 17
0
+25
ns
(Note 4)
Tosc - 23
-10
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
Tosc - 20
TWHQX
Data Hold after WR Rising Edge
Tosc - 33
TWHLH
WR Rising Edge to ALE Rising Edge
Tosc - 10
TWHBX
BHE, INST after WR Rising Edge
Tosc - 10
ns
TWHAX
AD8-15 HOLD after WR Rising·
Tosc - 30
ns
TRHBX
BHE, INST after RD Rising Edge
Tosc - 10
ns
TRHAX
AD8-15 HOLD after RD Rising
Tosc - 30
ns
+15
ns
ns
ns
Tosc + 19
ns
NOTES:
1. Testing performed at a MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
.
3. a-Bit bus only.
4. If wait states are used, add 2 Tosc • N, where N = number of wait states.
18-38
(Note 4)
(Note 2)
(Note 3)
(Note 3)
inteL
8XL196KD
System Bus Timings
XTALI
CLKOUT
ALE
BUS
ADDRESS OUT
TAVDV -.;.1_ _ _ _ _ __
BUS
--<_
ADDRESS OUT
_
DATA OUT
~,,(_ _A_D_D_RE_S_S_ _ _ __
L TRHBX ..
I
iTwHBX
BHE,INST
VALID
AD8-15
ADDRESS OUT
272254-7
II
18-39
intel~
8XL196KD
READY Timings (One Wait State)
XTAL I
CLKOUT
ALE
READY
_+_______""\ ""0----!.----
TRLRH + 2Tose ----j~--------
-l
-----\--Pl
TRLDV + 2 Tose
1----------..:.. TAVDV + 2 Tose
~--A-DD-RES-S-OU-T--~)~------------~(~-M-TA~»~)»~>>~-------
I
J
r-_________~~~I~.:::::-~-V-WH-+-2-~-s-e-~
~.
TWLWH + 2 Tose,
~---A-DD-R-ES-S-O-UT---~}~U~~------DA-T-A-O-UT-------JX~___A_D_D_RE_SS___
272254-8
Buswidth Timings
XTAll
"': ~
BUSWIDTH
.~
J~ ,~:"")
~'---~,---\.-
~
I ~-----------------------
--~I.----T-AV-GV-~-BUS
-<'-_________..JH\..,__-J)>-------------272254-9
18-40
intet
8XL196KD
EXTERNAL CLOCK DRIVE (8XL 196KD)
Symbol
Parameter
Min
Max
Units
1/TXLXL
Oscillator Frequency
8
16.0
MHz
62.5
125
TXLXL
Oscillator Period
TXHXX
High Time
20
TXLXX
Low Time
20
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272254-10
•
18-41
intaL
8XL196KD
EXTERNAL CRYSTAL CONNECTIONS
II{. .. . .
EXTERNAL CLOCK CONNECTIONS
Cl
Vss
-T---IXTALI
4.7K* , . . . - - - - - - - ,
8XL196KD
EXTERNAL
CLOCK INPUT
XTAL2
~:>-""--I XTAL'
clock driver
no connect
Quartz Crystal
8XL196KD
XTAL2
272254-11
272254-12
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL 1, XTAL2 and Vss. When
using ceramic crystals, Cl = 20 pF, C2 = 20 pF.
When using ceramic resonators consult. manufacturer
for recommended circuitry.
NOTE:
'Required if TIL driver used.
Not needed if CMOS driver is used.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
2.4 = x , . S ___ TEST POINTS - , . 5 > < =
0.40
272254-13
AC Testing inputs are driven at 2AV for a Logic "I" and OAOV for
a Logic "0" Timing measurements are made at 1.5V for a Logic
"'" and for a Logic "0",
272254-14
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs, and Begins to Float
when a 150 mV change from the Loaded VOHIVOL Level occurs
IOL/IOH ~ ±15 rnA.
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
H- High
L- Low
V- Valid
X- No Longer 'Valid
Floating
z-
Signals:
A- Address
B- BHE
C- CLKOUT
D- DATA
G- Buswidth
H- HOLD
HA-HLDA
18-42
L- ALE/ADV
BR-BREQ
R- RD
W- WR/WRH/WRL
X- XTAL1
Y- READY
Q- Data Out
8XL196KD
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE 0)
Symbol
Parameter
Min
Max
Units
ns
TXLXL
Serial Port Clock Period (BRR ::2: 8002H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR ::2: 8002H)
TXLXL
Serial Port Clock Period (BRR = 8001 H)
TXLXH
Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)
2 Tose -50
TOVXH
Output Data Valid to Clock Rising Edge
2 Tose - 50
ns
TXHOX
Output Data Hold after Clock Rising Edge
2 Tose - 50
ns
TXHOV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHOX
Input Data Hold after Clock Rising Edge
TXHOZ
Last Clock Rising to Output Float
6 Tose
4 Tose -50
4 Tose +50
ns
ns
4 Tose
2 Tose +50
2 Tose + 50
ns
ns
Tose +50
ns
0
ns
1 Tose
ns
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0)
272254-15
18-43
8XL196KD
A to D CHARACTERISTICS
The AID converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
TARGETED 10-BIT MODE AID OPERATING CONDITIONS
Symbol
Description'
Min
Max
Units
TA
Ambient Temperature Commercial Temp.
0
+70
°c
Vee
Digital Supply Voltage
3.0
3.6
V
VREF
Analog Supply Voltage
3.0
3.6
V
ANGND
Analog Ground Voltage
Vss - 0.30
Vee + 0.30
TSAM
Sample Time
1.0
TeONv
Conversion Time
10
20
p.s(l)
Fose
Oscillator Frequency
8.0
16.0
MHz
V
p.s(l)
NOTE:
1. The value of AD_TIME is selected to meet these specifications.
TARGETED 10-BIT MODE AID CHARACTERISTICS (Over Specified Operating Conditions)
Parameter
Typical(l)
Resolution
Minimum
Maximum
Units'
1024
10
1024
10
Levels
Bits
0
±3
LSBs
Absolute Error
Full Scale Error
0.25 ± 0.5
LSBs
Zero Offset Error
0.25 ± 0.5
LSBs
Non-Linearity
1.0 ± 2.0
Differential Non-Linearity Error
0
±3
LSBs
> -1
+2
LSBs
0
±1
LSBs
Channel-to-Channel Matching
±0.1
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBrC
LSBrC
LSBrC
-60
Off Isolation
Notes
dB
2,3
Feedthrough
-60
dB
2
Vee Power Supply Rejection
-60
dB
2
750
1.2K
n
4
ANGND - 0.3
VREF + 0.3
V
5,6
0
±3.0
p.A
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
3
pF
NOTES:
·An "LSS" as used here has a value of approxiimately 3 mY. (See Embedded Microcontrollers and Processors Handbook
for AID glossary of terms.)
1. These values are expected for most parts at 25'e but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Sreak-Sefore-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These valu·es may be exceeded if the pin current is limited to ± 2 mAo
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
18-44
int:et
8XL196KD
TARGETED 8-BIT MODE AID OPERATING CONDITIONS
Description
Min
Max
Units
TA
Ambient Temperature Commercial Temp.
0
+70
DC
Vee
Digital Supply Voltage
3.0
3.6
V
VREF
Analog Supply Voltage
3.0
3.6
V
ANGND
Analog Ground Voltage
Vss -0.30
Vss + 0.30
V
Symbol
TSAM
Sample Time
TeONv
Conversion Time
Fose
Oscillator Frequency
/Ls(1)
1.0
7
20
/Ls(1)
8.0
16.0
MHz
NOTE:
1. The value of AD_TIME is selected to meet these specifications.
TARGETED 8-BIT MODE AID CHARACTERISTICS
Parameter
Typical(1)
Resolution
(Over Specified Operating Conditions)
Minimum
Maximum
Units'
256
8
256
8
Levels
Bits
0
±1
LSBs
Absolute Error
Full Scale Error
±0.5
LSBs
Zero Offset Error
±0.5
LSBs
0
±1
LSBs
> -1
+1
LSBs
±1
LSBs
Non-Linearity
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
LSBrC
LSBrC
LSBrC
-60
Off Isolation
Notes
dB
2,3
Feedthrough
-60
dB
2
Vee Power Supply Rejection
-60
dB
2
1.2K
n
4
VSS - 0.3
VREF + 0.3
V
5,6
0
±3.0
/LA
750
Input Series Resistance
Voltage on Analog Input Pin
DC Input Leakage
Sampling Capacitor
pF
3
NOTES:
'An "LSB" as used here ha.s a value of approximately 12 mV. (See Embedded Microcontrollers and Processors Handbook
for AID glossary of terms).
1. These values are expected for most parts at 25'C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if pin current is limited to ± 2 rnA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
18-45
III
intel .
8XL196KD
OTPROM SPECIFICATIONS
TARGETED OPERATING CONDITIONS DURING PROGRAMMING
Symbol
Description
Min
Max
Units
TA
Ambient Temperature During Programming
20
30
C
Vee
Supply Voltage During Programming
4.5
5.5
V(1)
VREF
Reference Supply Voltage During Programming
4.5
5.5
V(1)
Vpp
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
Fose
Oscillator Frequency during Auto and Slave
Mode Programming
6.0
8.0
MHz
NOTES:
1. Vee and VREF should nominally be at the same voltage during programming.
2. Vpp and VEA must never exceed the maximum specification, or the device may be damaged.
3. Vss and ANGND should nominally be at the same potential (OV).
4. Load capacitance during Auto and Slave Mode programming = 150 pF.
AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)
Symbol
TSHLL
Description
Min
Reset High to First PALE Low
Max
Units
1100
Tose
TLLLH
PALE Pulse Width
50
Tose
TAVLL
Address Setup Time
0
Tose
TLLAX
Address Hold Time
100
TpLDV
PROG Low to Word Dump Valid
TpHDX
Word Dump Data Hold
TDVPL
Data Setup Time
0
Tose
TpLDX
Data Hold Time
400
Tose
TpLPH(1)
PROG Pulse Width
50
Tose
TpHLL
PROG High to Next PALE Low
220
Tose
TLHPL
PALE High to PROG Low
220
Tose
TpHPL
PROG High to Next PROG Low
220
Tose
TpHIL
PROG High to AINC Low
0
Tose
TILIH
AINC Pulse Width
240
Tose
TILVH
PVER Hold after AINC Low
50
Tose
TILPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Valid
Tose
50
Tose
50
Tose
Tose
220
Tose
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
18-46
intel"
8XL196KD
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Vpp Supply Current (When Programming)
Ipp
NOTE:
Do not apply Vpp until Vee is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
--I
~ TAVLL . ,
PORTS
"
1/
3/4
-
/--<
-I'
ADDR/COMMAND"'
TSHLL
TLLAX -
DATA
/,
,~
TDVPL ~ TpLDX ..
I
\
I---
ADDR/COMMAND
TLLLH -
\
I+-
TLHPL -+ I - TpLPH -
\
•
TpHLL "
/
\
PVER
_ TpHVL -
272254-16
NOTE:
P3.0 must be high ("1 ")
III
18-47
8XL196KD
SLAVE
PRO~RAMMING
MODE IN WORD DUMP WITH AUTO INCREMENT
--I
,
PORTS
/
3/4
I
ADDR/COMMAND /
~TSHLL-
ADDR
I
~ ....
TpLDV -
TpHDX
ADDR
+2
,VER BITS/WD DUMP ~
,VER BITS/WD DUMP/
4-
I-
TpLDV - -
TpHDX
f--
\
\
TILPL
/
--
\
V
- - TpHPL -
\
272254-17
NOTE:
P3.0 must be low ("0")
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND
AUTO INCREMENT
ADDR
PORTS
3/4
-----«
ADDR/COMMAND>---<
DATA
ADDR
)>---_~
ADDR + 2
DATA
>--
PALE
PVER
AINC
272254-18
18-48
inteJ~
8XL196KD
8XL 196KD ERRATA
None known.
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a "8" at the
end of the topside tracking number. Data sheets are
changed as new device information becomes available. Verify with your local Intel sales office that you
have the latest version before finalizing a design or
ordering devices.
•
18-49
8XC 196KR Data Sheet
19
8XC196KR/KQ/JR/JQ
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
87C196KR/KQ/JR/JQ-16 Kbytes of On-Chip OTPROM
80C 196KR/KQ/JR/JQ-ROMless
•
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS 16-Bit CPU
16 MHz Operating Frequency
Programmable 16-Bit Timer/
• Two
Counters with Prescale, Cascading,
Up to 488 Bytes of On-Chip Register
RAM
Standard and Quadrature Counting
Inputs
256 Bytes of Additional RAM
(Code or Data RAM)
10 High-Speed Capture/Compare (EPA)
•• Two
Dedicated High Speed Compare
Register-Register Architecture
8 Channel/10-Bit A/D with Sample/Hold
Registers
•
•
•
•
•Ii 3
•
•
37 Prioritized Interrupt Sources
Two Flexible 16-Bit Timer/Counters
Up to Seven 8-Bit (56) I/O Ports
Quadrature Counting Inputs
Full Duplex Serial I/O Port (SIO) and
Full Duplex Synchronous Serial I/O
Port (SSIO) with Dedicated Baud Rate
Generators
Flexible 8-/16-Bit External Bus
Programmable Bus (HOLD/HLDA)
1.75 /-Ls 16 x 16 Multiply
Interprocessor Communication Slave
Port
Pins/Package
/-Ls 32116 Divide
Extended Temperature Available
Watchdog Timer
Device
High-Speed Peripheral Transaction
Server (PTS)
68-Pin and 52-Pin PLCC Packages
OTPROM
Reg RAM
Internal RAM
I/O
EPA
510
5510
AID
87C196KR
68 P PLCC
16K
512
256
56
10
Y
Y
8
87C196KO
68 P PLCC
12K
384
128
56
10
Y
Y
8
87C196JR
52 P PLCC
16K
512
256
41
6
Y
Y
6
87C196JO
52 P PLCC
12K
384
128
41
6
Y
Y
6
80C196KR
68 P PLCC
0
512
256
56
10
Y
Y
8
80C196KO
68 P PLCC
0
384
128
56
10
Y
Y
8
80C196JR
52 P PLCC
0
512
256
41
6
Y
Y
6
80C196JO
52 P PLCC
0
384
128
41
6
Y
Y
6
The 87C196KR/KO/JR/JO devices represent the 4th generation of MCS®-96 products implemented on Intel's advanced 1 micron process technology. These products are members of the 80C196 family of devices
and the instruction set is the same as that of the 80C196KC. The 87C196JR is a 52-lead version of the
87C196KR device, while the 87C196KO/ JO are memory scalars of the 87C196KR/ JR.
The MCS-96® family members are all high-performance microcontrollers with a 16-bit CPU. The 87C196KR is
composed of the high-speed (16 MHz) core as well as the following peripherals: up to 16 Kbytes of on-chip
EPROM, up to 512 bytes of Register RAM, 256 bytes of Code RAM, an eight-channel 10-bit analog to digital
converter, an (8096 compatible) asynchronous/synchronous serial I/O port, an additional synchronous serial
1/0 port, 10 modularized multiplexed capture and compare channels (called the Event Processor Array), a
sophisticated prioritized interrupt structure with the programmable Peripheral Transaction Server (PTS).
19-1
September 1992
Order Number: 270912·004
•
int:el.,
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~@W~OO©[§ OOOIr@OOIMl~'iiO@OO
Additional register space is allocated for the EPA and can be windowed into the lower Register RAM area.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of O·C to + 70·C. With the extended (Express) temperature range option, operational characteristics are guaranteed over the temperature range of - 40·C to + 85·C. Unless otherwise noted, the specifications are the same for both options.
See the prefix identification for extended temperature designators.
XTAL1
--------
XTAl2
-------------------------------------------.
.------------------------.
: ....-----,
-------
I
I
I
I
I
Vee
Vss
Vss
'--_--1-,-- Vss
I
I
I
~-_----~!+
I
CONTROL SIGNALS
L-_ _ _ _~-I--...---++ADDR/DATA
:L---r--....
._---- -----
BUS
Vm
ANGND
..,
o
g
270912-1
Figure 1. Block Diagram
OFFFF.H
06000H
External
Memory
05FFFH
02080H
Internal ROM/EPROM
or External Memory
0207FH
0205EH
Reserved
0205DH
02040H
PTS Vectors
0203FH
02030H
Interrupt
Vectors (upper)
0202FH
02020H
ROM/EPROM
Security Key
0201FH
Reserved
0201BH
Reserved (must contain 20H)
0201AH
CCB1
02019H
Reserved (must contain 20H)
NOTES:
02018H
CCBO
02017H
02014H
Reserved
02013H
02000H
Interrupt
Vectors (lower)
01FFFH
01 FOOH
Internal SFRs
01EFFH
00500H
External
Memory
004FFH
00400H
Internal RAM
003FFH
00200H
External
Memory
001FFH
18H
Register File
17H
OOH
CPU SFR's
_
1. Reserved memory locations must contain OFFH unless noted.
2. Reserved SFR bit locations must contain OH unless noted.
3. WARNING: Reserved memory locations must not be written or read. The contents and/or function of these locations may
change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not
function properly.
19-2
intel®
aXC196KR/aXC196KQ/aXC196JR/aXC196JQ
~@W~If{]©~ OOO[P@~[M]~'iJ'O@OO
Process Information
The 8XC196KRI JR/KQI JQ is manufactured on PX29.5, a CHMOS IV process. Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook, Order Number 210997.
Table 1. Prefix Identification
*T
Device
Commercial
PLCC
Express
PLCC
80C196KR
N80C196KR
*TN80C196KR
80C196JR
N80C196JR
*TN80C196JR
80C196KQ
N80C196KQ
*TN80C196KQ
80C196JQ
N80C196JQ
*TN80C196JQ
87C196KR
N87C196KR
*TN87C196KR
87C196JR
N87C196JR
*TN87C196JR
87C196KQ
N87C196KQ
*TN87C196KQ
87C196JQ
N87C196JQ
*TN87C196JQ
= Extended Temperature, no burn-In.
Table 2. Thermal Characteristics
Package
8ja
8jc
52-Lead PLCC
35°C/W
12°C/W
68-Lead PLCC
35°C/W
13°C/W
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will
change depending on operating conditions and application. See Intel Packaging Handbook, (Order Number
240800) for a description of !ntel's thermal impedance test methodology.
19-3
III
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
I~ ~
"~~ I,@
~
~~ "" ....
>Z
C
~ t;; < 0::
< ;; I>: ...J
VI
"...
~@W~OO©~ OOO~@OO~~ii'O©OO
I>:
::;
N
...J
;; U
VI VI
0
'"
VI
0
U
VI
c
;:
"... " " ... "'"
N
on
..; ..; ..;
'" 0- VIVI "!0.on ..;0. "..;'"0. ..;0. >V'JVI !;(< ....X< ..;0. 0...;'" ..;0.on "..;0. ..;0.
0. 0. 0. ,:- >
" "
BUSWIDTH· Ips. 7
P6.2/T lCLK
AD IS/P4. 7
P6 •.1/EPA9
ADI4/P4.6
P6.0/EPA8
P 1.0/EPAO/T2CLK
ADI3/P4.S
ADI2/P4.4
ADll/P4.3
AD10/P4.2
AD9/P4.1
AD8/P4.0
68-PIN
PLCC
87C196KR/87C196KO
80C196KR/80C196KO
P1.1/EPA 1
P1.2/EPA2/T2DIR
Pl.3/EPA3
P1.4/EPA4
P1.S/EPAS
AD7/P3.7
TOP VIEW
P1.6/EPA6
AD6/P3.6
Component Side
of PC Board
Pl.7/EPA7
ADS/P3.S
VREF
AD4/P3.4
ANGND
AD3/P3.3
PO. 7 /PtdODE.3/ ACH7
AD2/P3.2
PO.6/PtdODE.2/ ACH6
AD1/P3.1
PO.S/PtdODE.l / ACHS
ADO/P3.0
PO.4/PtdODE.O/ ACH4
270912-2
NOTE:
°In earlier versions of documentation these pins were referred to as:
INTOUT - INTINTOUr
BREQ-INTB
BUSWIDTH - BUSW
RQ[ij- HLD
Figure 2. Package Diagrams
19-4
intet
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~[Q)W~~©[§ O~~@!rufi'lil~li'O@OO
I~......
...'"
..J
......
o
0..
'"
>0... >(f)
•
~
'" .......X
..J
>'"
AD14/P4.6
P6.1/EPA9
AD13/P4.5
P6.0/EPAB
AD12/P4.4
P1.0/EPAO
AD11/P4.3
AD10/P4.2
AD9/P4.1
ADB/P4.0
8XC196JR/JQ
52-PIN
PLCC
AD7/P3.7
TOP VIEW
AD6/P3.6
Component Side
of PC Boord
AD5/P3.5
P1.1/EPA1
P1.2/EPA2
P1.3/EPA3
VREf
ANGND
PO.7 /PMODE.3/ ACH7
PO.6/PMODE.2/ ACH6
AD4/P3.4
PO.5/PMODE.1 / ACH5
AD3/P3.3
PO.4/PMODE.0/ ACH4
AD2/P3.2
PO.3/ACH3
270912-3
NOTE:
'In earlier versions of documentation these pins were referred to as:
INTOUT - INTINTOUT
BREQ-INTB
BUSWIDTH - BUSW
HOLD- HLD
Figure 2. Package Diagrams (Continued)
19-5
int:eL 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~@W~OO©[§ OOOlr@OOIMl~liO@OO
PIN DESCRIPTIONS
Symbol
Name and Function
(+ 5V).
Vee
Main supply voltage
Vss
Digital circuit ground (OV). There are three Vss pins, all of which MUST be
connected.
VREF
Reference for the AID converter (+ 5V). VREF is also the supply voltage to the
analog portion of the AID converter and the logic used to read Port O. Must be
connected for AID and Port 0 to function.
ANGND
Reference ground for the AID converter. Must be held at nominally the same
potential as Vss.
Vpp
Programming voltage for the OTPROM parts. It should be + 12.5V for
programming. It is also the timing pin for the return from powerdown circuit. If this
function is not used, Vpp must be tied to Vee.
ACHO-ACH7/PORTO
Analog inputs to the on-chip AID converter.
AINC
Input to automatically increment the address when in Programming mode.
ALE/ ADV /P5.0
Address Latch Enable or Address Valid output, as selected by CCA. Both p~
options allow a latch to demultiplex the address/data bus. When the pin is ADV, it
goes inactive (high) at the end of the bus cycle. When the pin is ALE, the address
can be latched on the falling edge. ALE/ ADV is active only during external memory
accesses. Can be used as standard I/O when not used as ALE.
BHE/WRH/P5.5
Byte High Enable or Write High output, as selected by the CCR. BHE = 0 selects
the bank of memory that is connected to the high byte of the data bus. If the WRH
function is selected, the pin will go low if the bus cycle is writing to an odd memory
location. BHE/WRH is only valid during 16-bit external memory cycles. Can be
used as standard I/O when not uSl3d as BHE/WRH.
BREQ/P2.3
Bus Request output activatl3d when the bus controller has a pl3nding I3xternal
memory cycll3. Can be used as standard I/O when not uSl3d as BREQ.
BUSWIDTH/P5.7
Input for bus width sell3ction. If CCR bit 1 = 1 and CCR 1 bit 2 = 1, this pin
dynamically controls the Bus width of the bus cycle in progress. If BUSWIDTH is
low, an S-bit cycle occurs. If BUSWIDTH is high, a lS-bit cycll3 occurs. Can bl3 used
as standard I/O whl3n not used as BUSWIDTH.
CLKOUT/P2.7
Output of the internal clock genl3rator. The frl3quency is % the oscillator frequl3ncy.
It has a 50% duty cycle. Can be used as standard I/O whl3n not uSl3d as CLKOUT.
CPVER
Cumulative Program Verify output. Indicates when all EPROM locations program
correctly.
EA
Input for ml3mory sell3ct (External Access). EA = 1 causes memory accl3ssl3S from
locations 2000H to 5FFFH to be dirl3ctl3d to on-chip EPROM/ROM. EA = 0 causes.
all memory accl3sses to be dirl3cted to off-Chip memory. EA = + 12.5V causes
execution to begin in the Programming Mode. EA is latched at reset.
EPAO-7/PORT1
EPAS-9/PS.0-S.l
Event Processor Array pin for High Speed capture and compare. EPAO and EPA2
also function as T2CLK and T2DIA. Can be used as standard I/O when not used as
EPA or T2 clock functions.
EXTINT /P2.2
A positive transition on this pin causes a maskable interrupt vector through memory
location 203CH. May be used as standard I/O if not used as EXTINT.
HLDAlP2.S
Bus Hold Acknowledge output indicating release of the bus. Can be used as
standard I/O when not used as HLDA.
HOLD/P2.5
Bus Hold input requesting control of the bus. Can be used as standard I/O when
not used as HOLD.
19-5
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
£IQ)W£OO©[§ OOO!F@OOIi!Al£'U'O@OO
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
INST/P5.1
Output high during an external memory instruction fetch. INST is valid throughout
the bus cycle. INST is low otherwise. Can be used as standard I/O when not used
as INST.
INTOUT /P2.4
Interrupt output indicating that a pending interrupt requires use of the external bus.
Can be used as standard I/O if not used as INTOUT.
NMI
A positive transition causes a non-maskable interrupt vector through memory
location 203EH. If not used, this pin should be tied to Vss. May be used by Intel
Evaluation boards.
PACT
Output that indicates when the device is currently programming itself. Not active
during slave programming.
PALE
Input to latch the address during programming modes.
PMODE.0-PMODE.3
Programming mode select inputs.
PORTO
8-bit high impedance input-only port. Also used as AID converter inputs. Port 0 pins
should not be left floating. These pins are also used as inputs by EPROM parts to
select the Programming Mode.
PORT1
.'
8-bit bidirectional standard I/O port. All of its pins are shared with the EPA .
PORT2
8-bit bidirectional standard I/O port. All of its pins are shared with other functions
(TxD, RxD, EXTINT, SREQ, INTOUT, HOLD, HLDA, CLKOUT).
PORT3
PORT4
8-bit bidirectional standard I/O with open drain outputs. These pins are shared with
the multiplexed address/data bus which uses strong internal pullups.
PORT5
8-bit bidirectional standard I/Q..port. All of its pins are shared with other functions
(ALE/ ADV, INST, WR/WRL, RD, SLPINT, SHE/WRH, READY, SUSWIDTH).
PORT6
8-bit bidirectional standard I/O port. All of its pins are shared with other functions
(EPA8, EPA9, T1CLK, T1DIR, SCO, SDO, SC1, SD1).
PROG
Programming mode enabl.e input.
PVER
Program Verify output. Goes high after a byte/word is programmed to indicate a
successful operation.
RD/P5.3
Read signal output to external memory. RD is low only during external memory
reads. Can be used as standard I/O when not used as RD.
READY/P5.6
Ready input to lengthen external memory cycles. If READY = 1, CPU operation
continues in a normal manner. If READY = 0 with the appropriate timings, the
memory controller inserts wait states until the next positive transition of CLKOUT
occurs with READY = 1. Can be used as standard I/O when not used as READY.
RESET
Reset input to and output from the chip. Held low for at least 16 state times to reset
the chip. The subsequent low to high transition resynchronizes CLKOUT and
commences a 10-state time sequence. Input high for normal operation. RESET has
an internal pullup.
RXD/P2.1
Receive data input pin for the Serial I/O port. Can be used as standard I/O if not
used as RXD.
SLPCS
Slave port chip select input pin. Can be used as standard I/O if not used as SLPCS.
SLPINT /P5.4
Slave Port Interrupt Output pin. Can be used as standard I/O when not used as
SLPINT.
SSI0/P6.4-6.7
(SCO, SDO, SC1, SD1)
Synchronous Serial I/O pins. SCO/SC1 serve as clock pins and SDO/SD1 are data
pins. Can be used as standard I/O if not used for serial I/O.
19-7
II
infel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~@W~OO©[g OOOW:©OOIMl~iiO©OO
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
T1CLK/P6.2
TIMER1 Clock input. The timer increments or decrements on both positive and negative
edges. Can be used as standard 1/0 when not used as T1CLK.
T1DIR/P6.3
TIMER1 Direction input. The timer increments when this pin is high and decrements when
this pin is low. Can be used as standard 1/0 when not used as T1 DIR.
T2CLK/P1.0
TIMER2 Clock input. The timer increments or decrements on both positive and negative
edges. Can be used as standard 1/0 when not used as T2CLK.
T2DIR/P1.2
TIMER2 Direction input. The 'timer increments when this pin is high and decrements when
this pin is low. Can be used as standard 1/0 when not used as T2DIR.
TXD/P2.0
Transmit data output pins for the Serial 110 port. Can be used as standard 1/0 if not used
as TXD.
WR/WRL/P5.2
Write and Write Low output to external memory. WR will go low for every external write.
WRL will go low only for external writes where an even byte is being written. WR/WRL is
active only during external memory writes. Can be used as standard 110 when not used as
WR/WRL.
XTAL1
Input of the oscillator inverter and the internal clock generator. This pin should be used
when using an external clock source.
XTAL2
Output of the oscillator inverter.
19-8
intel" 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS**
~[Q)W~OO©(§ OOOIr@Iru~~'U'O@OO
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. It is valid for the devices indicated in
the revision history. The specifications are subject to
change without notice.
Storage Temperature .......•.. -60·Cto +150·C
Ambient Temperature
under Bias .................. - 55·C to + 125·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage from Vpp or EA to
Vss or ANGND .............. -0.5V to + 13.0V
Voltage from Any Other Pin
to VSS or ANGND ............. -0.5V to + 7.0V
This includes Vpp on ROM and CPU devices.
II
Power Dissipation .......................... 1.0W
(based on PACKAGE heat transfer limitations,
not device power consumption)
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature under Bias Commercial Temp.
0
+70
·C
TA
Ambient Temperature under Bias Extended Temp.
-40
+85
·C
Vee
Digit~1
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
Fose
Oscillator Frequency
4
16
MHz(4)
Supply Voltage
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
(Over Specified Operating Conditions)(9)
Parameter
Min
Typ(6)
Max
Units
VIL
Input Low Voltage
(All Pins)
-0.5V
0.3 Vee
V
VIH
Input High Voltage
0.7 Vee
Vee + 0.5
V
VOL
Output Low Voltage
(Outputs Configured
as Push/Pull)
0.3
0.45
1.5
V
V
V
VOH
Output High Voltage
(Outputs Configured
as Push/Pull)
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
= 200 /LA(3, 5)
= 3.2 rnA
= 7.0 rnA
IOH = - 200 /LA(3, 5, 8)
IOH = -3.2 rnA
IOH = -7.0 rnA
VOH2
Output High Voltage
in RESET
Vee - 1V
V
IOH = -15 /LA(1, 7)
III
Input Leakage Current
(Std. Inputs)
ILit
Input Leakage Current
(Port O-AiD Inputs)
IIH
Input High Current
(NMI)
±1
19-9
Test Conditions
IOL
IOL
IOL
±10
/LA
Vss
< VIN < Vee
±3
/LA
Vss
< VIN < VREF
+175
/LA
Vss
< VIN < Vee
- 0.3V(2)
- 0.3V(10)
infel. 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
£IIDW£OO©~ OOOIF@OOrMl£'U'O@OO
DC CHARACTERISTICS (Over Specified Operating Conditions)(9) (Continued)
Symbol
Parameter
Min
Typ(6)
Max
Units
Test Conditions
75
rnA
XTAL1 = 16 MHz,
Vee = Vpp = VREF = 5.5V
(While Device in Reset)
Icc
Vee Supply Current
60
IREF
AID Reference Supply
Current>
2
5
rnA
IIOlE
Idle Mode Current
15
30
rnA
Ipo
Powerdown Mode
Current(6)
50
RRST
Reset Pull up Resistor
Cs
Pin Capacitance
(Any Pin to VSS)
Rwpu
Weak Pullup Resistance (Approx)
6K
TBD
XTAL1 = 16 MHz,
Vee = Vpp = VREF
Vee
/l-A
= Vpp =
65K
n
10
pF
FTEST
n
(6)
150K
= 5.5V
VREF = 5.5V
= 1.0 MHz
NOTES:
1. All BO (Bidirectional) pins except INST and elKOUT. BO pins include Port1, Port2, Port3, Port4, Port5 (as a port), and
Port6.
2. Standard Input pins include XTAL1, "EA, RESET, and Port 1/2/3/4/5/6 when setup 'as inputs.
3. All Bidirectional 1/0 pins when configured as Outputs (Push/Pull).
4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz.
5. Maximum IOl/lOH currents per pin will be characterized and published at a later date.
6. Typlcals are based on limited number of samples and are not guaranteed. The values listed-are at room temperature and
VREF = Vcc = 5.0V.
7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6)..
6. This specification applies to P3/4 only when used as an address bus supplying the address.
9. All voltages are referenced relative to Vss. When used, Vss refers to the device pin.
10. Worst case is at upper limit of test conditions.
Icc vs 'Frequency
80 .-----'"T"----.-----~
Icc WAX
70~---~~---~-~~~
60~---~----~~---~
50 t_------+--.,---::;.,;c-t_----::OIIi1cc typical
Icc
(mA)
40t_----+--:~~-t_~~-~
30 t----~'----=,,-.t-----Ilidl. WAX
~dl.
20
typical
10~---~~~~--F=~--~
O~---~----~---~
4101Hz
10 101Hz
NOTES:
ICC Max = 3.88 X FREQ + 13.43
lidle Max = 1.65 X FREQ + 2.2
19-10
16 101Hz
270912-4
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
£[Q)W£OO©~ OOO~@OOIMJ£'TI'O@OO
AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns.
The system must meet these specifications to work with the 87C196KR/KQ/JR/JQ:
Symbol
Parameter
Min
TAVYV
Address Valid to READY Setup
hLYV
ALE Low to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TLLYX
READY Hold after ALE Low
Max
Units
2 Tosc-75
ns(2)
Tosc-70
ns(2)
No Upper Limit
TAVGV
Address Valid to Buswidth Setup
TLLGV
ALE Low to Buswidth Setup
TCLGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
ns
0
Tosc-30
ns(1,2)
Tosc-15
2 Tosc-40
ns(1,2)
2Tosc-75
ns(2)
Tosc-60
ns(2)
ns(2)
0
3 Tosc-55
ns
TRLDV
RD Active to Input Data Valid
Tosc-22
ns
TCLDV
CLKOUT Low to Input Data Valid
Tosc-50
ns
TRHDZ
End of RD to Input Data Float
Tosc
ns
TRXDX
Data Hold after RD Inactive
0
NOTE:
1. If max is exceeded. additional wait states will occur.
2. Does not apply to JR/JQ.
19-11
ns
intel ~
8XC196KR/8XC 196KQ/8XC 196JR/8XC196JQ
&[Q)W&OO©[g OOOIP©OOIMJ&irO©OO
AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns.
The 87C196KR/KQ/JR/JQ will meet these specifications.
Symbol
Min
Max·
Units
Oscillator Frequency
4.0
16.0
MHz(1)
Tosc
Oscillator Period (1 /Fxtal)
62.5
250
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
20
110
ns(2)
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
Tosc-10
Tosc+15
ns
TCLLH
CLKOUT Falling Edge to ALE Rising
-10
15
ns
TLLCH
ALE/ ADV Falling Edge
to CLKOUT Rising
-20
15
ns
TLHLH
ALE/ ADV Cycle Time
FXTAL
Parameter
ns
2 Tosc
ns(5)
4 Tosc
TLHLL
ALE/ ADV High Period
Tosc-10
TAVLL
Address Setup to ALE/ ADV
Falling Edge
Tosc-15
ns
TLLAX
Address Hold after ALE/ ADV
Falling Edge
Tosc-40
ns
TLLRL
ALE/ ADV Falling Edge to
RD Falling Edge
Tosc-30
ns
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to
ALE/ ADV Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE/ ADV Falling Edge
to WR Falling Edge
TCLWL
CLKOUT Low to
WR Falling Edge
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
4
Tosc+10
30
ToSc+25
ns(3)
5
ns
ns
Tosc-10
-5
25
ns
ns
Tosc-23
-10
ns
ns(5)
Tosc-5
Tosc
ns
15
ns
ns(5)
TWLWH
WR Low Period
Tosc-30
TWHQX
Data Hold after WR Rising Edge
Tosc-25
ns
TWHLH
WR Rising Edge to ALE/ ADV
Rising Edge
Tosc-10
ns(3)
TWHBX
SHE, INST Hold after WR Rising Edge
TWHAX
AD8-15 Hold after WR Rising Edge
TRHBX
SHE, INST Hold after RD Rising Edge
TRHAX
AD8-15 Hold after RD Rising Edge
TBVLL
SHE Valid to ALE Falling Edge
Tosc+15
Tosc-10
ns
Tosc-10
ns(6)
Tosc-30(4)
ns
Tosc -15
ns(6)
NOTES:
1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. a-bit bus only.
5. If wait states are used, add 2 Tasc x n, where n = number of wait states.
6. Does not apply to JRI JQ.
19-12
ns(6)
Tosc-30(4)
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~[Q)W~~©~ OOO[f@OO[MJ~iiO@OO
System Bus Timing
XTALl
CLKOUT
ALE
TAVLL ---+---
TLLWL - - ' " - -
ADDRESS OUT
BHE,INST
VALID
TWHAX or TRHAX
AD8-15
ADDRESS OUT
270912-5
Buswidth Timings
XTALl
CLKOUT
ALE
Ro
BUS
ADDRESS OUT
DATA
TCLYX
TYLYH
READY
TAVYV
TAVGV
BUSWIDTH
270912-6
19-13
intel .
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~[Q)W~OO©[g OOOIF@OOIMl~'iiO@OO
HOLD/HLDA Timings
Symbol
Description
Min
Max
65
Units
Notes
ns
(1,2)
THVCH
HOLD Setup
TCLHAL
CLKOUT Low to HLDA Low
-15
15
ns
(2)
TCLBRL
CLKOUT Low to BREQ Low
-15
15
ns
(2)
TAZHAL
H!-DA Low to Address Float
25
ns
(2)
TBZHAL
HLDA Low to BHE, INST, RD, WR Weakly Driven
25
ns
(2)
TCLHAH
CLKOUT Low to HLDA High
-15
15
ns
(2)
TCLBRH
CLKOUT Low to BREQ High
-15
15
ns
(2)
THAHAX
HLDA High to Address No Longer Float
-15
ns
(2)
THAHBV
HLDA High to BHE, INST, RD, WR Valid
-10
ns
(2)
TCLLH
CLKOUT Low to ALE High
-10
15
ns
NOTE:
1. To guarantee recognition at next clock.
2. Does not apply to JR/JQ.
HOLD LATENCY
Max
Internal Access
1.5 States
16-Bit External Execution
2.5 States
a-Bit External Execution
4.5 States
DC SPECIFICATIONS IN HOLD
Parameter
Min
Max
Units
Weak Pullups on ADV, RD, WR, WRL, BHE
50K
250K
VCC = 5.5V, VIN = O.45V
Weak Pulldowns on ALE, INST
10K
50K
VCC = 5.5V, VIN = 2.4V
BUS
-<"'_____
BHE,INST
Rii,WR
ALE
~rS
_ _ _ _-ISSr-_ _ _T_CL_LH
h------270912-7
19-14
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~[Q)W~OO©[§ OOO~@OOIMl~'iiO@OO
EXTERNAL CLOCK DRIVE
Min
Max
Units
1/TXLXL
Oscillator Frequency
Parameter
4.0
16
MHz
TXLXL
Oscillator Period (T ose)
62.5
250
ns
TXHXX
High Time
0.35 Tosc
0.65 Tosc
ns
TXLXX
Low Time
0.35 Tosc
0.65 Tosc
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
Symbol
EXTERNAL CLOCK DRIVE WAVEFORMS
270912-8
EXTERNAL CRYSTAL CONNECTIONS
II{I-. .
EXTERNAL CLOCK CONNECTIONS
Vee
Cl
Vss
..I,---I
XTALI
8XCI96KR/KQ/JR/JQ
EXTERNAL
CLOCK INPUT
~ 4.7K·
"'"
clock driver
XTAL2
XTALI
8XC196KR/KQ/JR/JQ
no connect- XTAL2
Quartz Crystal
270912-16
270912-17
• Required if TTL driver used.
Not needed if CMOS driver is used.
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and VSS. When
using quartz crystals, typically C1 ::::: 22 pF and C2 :::::
22 pF. When using ceramic resonators, consult manufacturer for recommended circuitry.
19-15
II
inteL 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
AC TESTING INPUT, OUTPUT WAVEFORMS
~[Q)W~OO©~ OOO!F@OOIMl~'iiO@OO
FLOAT WAVEFORMS
INPUTS
OUTPUTS
O~~:: =><=JEST PO+ <::::
>C
270912-10
270912-9
NOTE:
NOTE:
For Timing Purposes a Port Pin is no longer floating
when a 150 mV change from Load Voltage Occurs and
Begins to Float when a 150 mV change from the Loading VOHIVOl Level occurs IOl/lOH ,;; 15 mA.
AC Testing Inputs are driven at 3.5V for a logic "1" and
0.45V for a logic "0". Timing measurements are made
at 2.0V for a logic "1" and O.BV for logic "0".
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H- High
L-Low
A- Address
B-BHE
V-Valid
X- No Longer Valid
Z- Floating
L- ALE/ADV
Q- Data Out
R-RD
W- WR/WRH/WRI
BR- BREQ
C-CLKOUT
0- DATA
X- XTAL1
Y- READY
G- Buswidth
H- HOLD
HA-HLDA
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE (MODE 0)
SERIAL PORT TIMING'-SHIFT REGISTER MODE (Over Specified Operating Conditions)
Test Conditions: Load Capacitance = 100 pF
Symbol
Min
Parameter
TXLXL
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TQVXH
Output Data Setup to Clock Rising Edge
TXHQX
Output Data Hold after Clock Rising Edge
TXHOV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHOX
Input Data Hold after Clock Rising Edge
TXHOZ
Last Clock Rising to Output Float
Max
ns
8 Tosc
4 Tosc-SO
4 Tosc+SO
ns
ns
3 Tosc
ns
2 Tosc-SO
2 Tosc+SO
ns
2 TOSC+2OO
ns
0
ns
STosc
19-16
Units
ns
inlet
8XC196KRI8XC196KQ/8XC196JR/8XC196JQ
~1ID\Yl~OO©~ OOO[F@OOIMl~iiO@OO
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE (MODE 0)
SERIAL PORT WAVEFORM-5HIFT REGISTER MODE
TXO---l..r
TQVXH
-!
I-
RXO
(OUT)
RXO--~,~~·r--~T~~,,-~~.~.,---~.I~~C'"
(IN)
270912-14
ATOD
AID CONVERTER SPECIFICATION
The speed of the AID converter in the 10-bit or a-bit
modes can be adjusted by setting the AD_TIME
special function register to the appropriate value.
The AD_TIME register only programs the speed at
which the conversions are performed, not the speed
it can convert correctly.
After a conversion is started, the device is placed in
the IDLE mode until the conversion is complete.
Testing is performed at VREF = 5.12V.
The converter is ratio metric, so absolute accuracy is
dependent on the accuracy and stability of VREF.
There is an AD_TEST register that allows for conversion on ANGND and VREF as well as zero·offset
adjustment. The Absolute Error listed is WITHOUT
doing any adjustments.
19-17
II
intel. 8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
£IIDW£OO©rg OOOIF©mi~£"jj'O©OO
1G-SIT AID OPERATING CONDITIONS(1)
Description
Min
Max
Units
TA
Ambient Temperature Commercial Temp.
0
+70
·C
TA
Ambient Temperature Extended Temp.
-40
+85
·C
VCC
Digital Supply Voltage
4.50
~.50
V
VREF
Analog Supply Voltage
4.50
5.50(2}
Symbol
V
,...s(3)
TSAM
Sample Time
2.0
TCONV
Conversion Time
16.5
19.5
,...s(3)
4
16
MHz
Oscillator Frequency
Fosc
NOTES:
1. ANGND and Vss should nominally be at the same potential.
2. VREF must not exceed Vee by more than +0.5V.
3. The value of AD_TIME is selected to meet these specifications.
10-BIT MODE AID CHARACTERISTICS (Over Specified Operating Conditions)
Parameter
Typical (1)
Resolution
Absolute Error
Full Scale Error
Min
Max
Units·
1024
10
1024
10
Level
Bits
0
±3
LSBs
: 0.25 ±0.5
Zero Offset Error
0.25 ±0.5
Non-Linearity
1.0 ±2.0
LSBs
LSBs
±3
LSBs
> -0.5
+0.5
LSBs
Channel-to-Channel Matching
±0.1
0
±1
LSBs
Repeatability
±0.25
0
LSBs
Temperature Coefficients:
Offset
Fullscale
Differential Non-Linearity
0.009
0.009
0.009
-60
LSB/C
LSB/C
LSB/C
dB(2,3)
Differential Non-Linearity
Off Isolation
Feedthrough
-60
Vee Power Supply Rejection
-60
dB(2)
dB(2)
Input Series Resistance
Voltage on Analog Input Pin
Sampling Capacitor
750
1.2K
ANGND - 0.5
VREF + 0.5
0(4) .
V
pF
2
DC Input Leakage
0
±3
,...A
NOTES:
·An uLSB", as used here, !:las a value of approximately 5 mV. (See Embedded Microcontrollers and ProCessors Handbook
for AID glossary of terms).
.
1. These values are expected for most parts at 25°C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal multiplexer, to sample capaCitor.
19-18
intel ~
8XC196KR/8XC 196KQ/8XC 196JR/8XC 196JQ
~IIDW~OO©~ OOOrr@OO!Ml~iiO@OO
8·BIT AID OPERATING CONDITIONS(1)
Symbol
Description
Min
Max
Units
TA
Ambient Temperature Commercial Temp.
0
+70
·C
TA
Ambient Temperature Extended Temp.
-40
+85
·C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50(2)
TSAM
Sample Time
2.0
TCONV
Conversion Time
16.5
19.5
p.s(3)
Fosc
Oscillator Frequency
4
16
MHz
V
p.s(3)
NOTES:
1. ANGND and Vss should nominally be at the same potential.
2. VREF must not exceed Vee by more than +0.5V.
3. The value of AD_TIME is selected to meet these specifications.
a-BIT MODE AID CHARACTERISTICS
(Over Specified Operating Conditions)
The 8-bit mode trades off resolution for a faster conversion time. The AD_TIME register must be used when
performing an 8-bit conversion.
Parameter
Typ(1)
Resolution
Absolute Error
Full Scale Error
±0.5
Zero Offset Error
±0.5
Non-Linearity
Differential Non-Linearity Error
Minimum
Maximum
Units·
256
8
256
8
Levels
Bits
0
±2
LSBs
LSBs
LSBs
0
±2
LSBs
> -1
+1
LSBs
±1
LSBs
Channel-to-Channel Matching
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
LSBI"C
LSBI"C
LSBI"C
Feedthrough
-60
VCC Power Supply Rejection
-60
Input Series Resistance
Voltage on Analog Input Pin
Sampling Capacitor
DC Input Leakage
dB(2,3)
-60
Off Isolation
dB(2)
dB(2)
750
1.2K
ANGND - 0.5
VREF + 0.5
n
V
pF
2
0
NOTES:
'An "LSB", as used here, has a value of approximately 20 mV.
1. Typical values are expected for most devices at 25°C.
2. DC to 100 KHz.
3. Multiplexer Break-Belore-Make Guaranteed.
4. Resistance Irom device pin, through internal multiplexer, to sample capacitor.
19-19
±3
p.A
Notes
•
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
b:\@Wb:\OO©[g OOO!;s'@OO[M]b:\'U'O@OO
OTPROM PROGRAMMING
OPERATING CONDITIONS DURING PROGRAMMING(3)
Symbol
TA
Description
. Ambient Temperature during Programming
Min
Max
Units
20
30
·C
Vee
Supply Voltage during Programming
4.5
5.5
V(1)
VREF
Reference Supply Voltage during Programming
4.5
5.5
V(1)
Vpp
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
Fose
Oscillator Frequency during Auto and
Slave Mode Programming
6.0
8.0
MHz
Fose
Oscillator Frequency during
Run-Time Programming
6.0
12.0
MHz
NOTES:
1. Vcc and VREF should nominally be at the same voltage during programming.
2. Vpp and VEA must never exceed the maximum specification, or the device may be damaged.
3. Vss and ANGND should nominally be at the same potential (OV).
AC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
Units
TAVLL
Address Setup Time
0
Tose
TLLAX
Address Hold Time
100
Tose
TDVPL
Data Setup Time
0
Tose
TpLDX'
Data Hold Time
400
Tose
TLLLH
PALE Pulse Width
50
Tose
TpLPH
PROG Pulse Width(1)
50
Tose
TLHPL
PALE High to PROG Low
220
Tose
TpHLL
PROG High to Next PALE Low
220
Tose
TpHDX
Word Dump Hold Time
TpHPL
PROG High to Next PROG Low
220
hHPL
PALE High to PROG Low
220
TpLDV
PROG Low to Word Dump Valid
TSHLL
RESET High to First PALE Low
TpHIL
PROG High to AINC Low
TILIH
TILVH
50
Tose
Tose
Tose
50
1100
Tose
.
Tose
0
Tose
AINC Pulse Width
240
Tose
PVER Hold after AINC Low
50
Tose
TILPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Valid
Tose
220
NOTE:
1. This specification is for the word dump mode. For programming pulses use 100 !,-s.
19-20
Tose
intel ~
~@WL~di~l©~ OOO~©OO!Mlb\jj'n©oo
8XC 196KR/8XC196KQ/8XC196JR/8XC196JQ
DC OTPROM PROGRAMMING CHARACTERISTICS
Parameter
Units
Vpp Programming Supply Current
mA
Symbol
Ipp
NOTE:
Do not apply Vpp until Vee is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
RESET
--J
~DVPL~
r-TAVLL--j
~ ADDRESS/CO~~AND
PORTS
3/4
-
TLLLH -
I+-
ADDRESS/CO~~AND
\
If
\
-
.(
~
r---- TpLDX -
TLLAX
TSHLL
PALE
P2.1
"
DATA
TLHPL . - -
PROG
P2.2
TpLPH
TpHLL -
II
\
!--TpHVL VALID •.!
\ -,.
PVER
P2.D
TLLVH
270912-11
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
RESET
--I
PORTS
3/4
/
ADDRESS/COMt.lAND
- TSHLL PALE
P2.1
I
"-
\
-
TpHDX
l-
I--
ADDR + 2
VER BITS/WD DUMP ,) i - -
I-
V
\
PROG
P2.2
AINC
P2.4
~
TpLDV -
T1LPL
I
ADDR
"""VER BITS/WD DUMP /
-!-TPLDV -
\
TpHDX
I-
II
TpHPL -
[\
270912-12
19-21
•
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
£@W£OO©[g OOOIF@OO[M)£'TI"O@OO
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE
WITH REPEATED PROG PULSE AND AUTO INCREMENT
PO~/~
PALE
P2.1
PROO
P2.2
PVER
P2.0
____--«
ADDRESS/COMMAND
>---<
DATA
)>-__-:-_____-«
DATA
>--
--------~\
j
'-----f
-----------------~
----------------------~-----r-~~~-------
AINC
P2.4
3. P2.7 (CLKOUT)
87C196KR/87C196JR ERRATA
1. IOH2
Current devices do not meet the test condition
for VOH2 of ":"'15 pA Instead the devices are
guaranteed to source a minimum of -6 pA
87C196KR/87C196JR DESIGN
CONSIDERATIONS
1. EPA Timers
Special care must be taken when resetting/writing the EPA timers. This is more of a software
technique than a device errata. For example:
The EPA timers do not generate a "time valid"
signal when the counter is either reset or written. This means that if a compare event is programmed in the EPA/Compare channel for a
value of "OOOOH" (when reset) or equal to a
written value, the compared event will NOT happen. However, if the timers are allowed to increment/decrement to that value, that compare
event WILL occur.
2. Port 6.4, 6.5, 6.6, 6.7
The user is not allowed to modify the P6_REG
register when these pins are configured as Special Function P6_MODE.x = 1). During software manipulation of these registers, it is a good
practice to first change the P6_MODE register,
then modify the P6_REG register when switching from SF to LSIO.
19-22
Port 2.7 (CLKOUT) does not operate in open
drain mode.
.
4. Current versions of the 8XC196KQ/ JQ are fabricated with 16K of internal OTPROM, 512 bytes
of register RAM, and 256 bytes of internal RAM.
The memory map of the 8XC196KQ/ JQ is identical to the 8XC196KR/JR. However, the extra
memory locations are not tested and should not
be used. Intel may disable this extra memory on
future versions of the 8XC196KQ/JQ. Any software that relies on reading or writing these locations may not function correctly on future devices.
Two steps the user should always incorporate to
insure future compatibility are:
A) The program must contain a jump to a location greater than 16K before the 12K boundary is reached. This is necessary only if greater
than 12K of program memory is required and
portions of the program executes from internal OTPROM.
'
8) Use program memory from 12K to 16K only if
EA is tied to ground. Never use data memory
from 180H to 1FFH or from 480H to 4FFH.
inlet
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
52-LEAD DEVICES
Intel offers a 52-lead version of the 87C196KR device: the 87C196JR and 87C196JQ devices.
It is important to point out some functionality differences because of future devices or to remain software consistent with the 68-lead device. Because of
the absence of pins on the 52-lead device some
functions are not supported.
52-Lead Unsupported Functions:
Analog Channels 0 and 1
INST Pin Functionality
SLPINT Pin Support
HLD/HLDA Functionality
External Clocking/Direction of Timer1
WRH or BHE Functions
Dynamic Buswidth
Dynamic Wait State Control
The following is a list of recommended practices
when using the 52-lead device:
(1) External Memory. Use an 8-bit bus mode only.
There is neither a WRH or BUSWIDTH pin. The
bus cannot dynamically switch from 8- to 16-bit
or vice versa. Set the CCB bytes to an 8-bit only
mode, using WR function only.
(2) Walt State Control. Use the CCB bytes to configure the maximum number of wait states. If the
READY pin is selected to_be a system function,
the device will lockup waiting for READY. If the
READY pin is configured as LSIO (default after
RESET), the internal logic will receive a logic
"0" level and insert the CCB defined number of
wait states in the bus cycle. DON'T USE IRC =
"111" .
~@W~OO©[g OOO!F©OOIMl~'iiO©OO
(3) NMI Support. The NMI is not bonded out. Make
the NMI vector at location 203Eh vector to a
Return instruction. This is for glitch safety protection only.
(4) Auto-Programming Mode. The 52-lead device
will ONLY support the 16-bit zero wait state bus
during auto-programming.
(5) EPA4 through EPA7. Since the JR and JQ devices use the KR silicon, these functions are in
the device, just not bonded out. A programmer
can use these as compare only channels or for
other functions like software timer, start and
AID, or reset timers.
(6) Slave Port Support. The Slave port can still be
used on the 52-lead devices. The only function
removed is the SLPINT output function.
(7) Port Functions. Some port pins have been removed. P5.7, P5.6, P5.5, P5.1, P6.2, P6.3, P1.4
through P1.7, P2.3, P2.5, PO.O and PO.1. The
P>e-REG, P>e-MODE, and P>e-DIR registers
can still be updated and read. The programmer
should not use the corresponding bits associated with the removed port pins to conditionally
branch in software. Treat these bits as RESERVED.
Additionally, these port pins should be setup internally by software as follows:
1. Written to P>e-REG as "1" or "0".
2. Configured as Push/Pull, P>e-DIR as "0".
3. Configured as LSIO.
This configuration will effectively strap the pin
either high or low. DO NOT Configure as
Open Drain output "1'; or as an Input pin.
This device is CMOS.
19-23
II
intet
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
~[Q)W~OO©~ OOO~©OOIMl~'iJO@OO
16. Changed External Clock min/max, highllow
times from percentage to ratio of TOSC
17. Removed NMI from standard inputs (Note 2 under DC Characteristics),
REVISION HISTORY
This data sheet (270912-003) supercedes 270912002 and is valid for devices with a "C" at the end of
the topside tracking number. Data sheets are
changed as new device information becomes available. Verify that you have the latest version before
finalizing a design or ordering devices.
18. Removed VOL1 spec
19. Removed TCLBV
20. Added JQ/KQ design consideration
1. Removed the following errata:
Slave Programming Mode
Data sheet 270912-002 supercedes 270912-001
and is valid for devices with an "A" at the end of the
topside tracking number.
EP~MASK1/EP~PEND1
BMOVI
PTS and Other Interrupts
1. Removed:
CPU features descriptions
Serial Port Framing Error
Peripheral features descriptions
SFR Operation (placed in Quick Reference)
Remap Mode on EPA3
AID Abort
SFR Maps (placed in Quick Reference)
PTSINMI Conflict
SFR Bit Maps (placed in Quick Reference)
Data Output Register Cleared
IlL in DC Characteristics
Divide Error during HOLD/READY
SIO Mode 0
TCLHAL Max and TCLBRH Max
Incorrect Sample and Convert time table from
8-bit AID
EPAIPV Multiplied by Two
2. Added:
(These were fixed on the C-step)
Express options
Bullets on front page
Memory Map
2. Moved the following from Errata to Design Considerations:
EPA Timers
Port 6.4, .6.5, 6.6, 6.7 (and reworded)
Process Information
P2.7 (CLKOUT)
Prefix Identification
Oscillator Noise Sensitivity
Thermal Characteristics
Programming functions to pin-out and pin descriptions
Ambient Temperature under Bias to Absolute
Maximum Ratings
3. Added New Errata:
IOH2 (also existed on A-step)
4. Added SLPCS to Package Diagrams.and Pin Descriptions
Note relating to Power Dissipation in Absolute
Maximum Rating
Notes 8 and 9 to DC Characteristics
5. Added T BVLL
6. Added IIH for NMI
7. Added notes to AC Characteristics identifying
specifications that do not apply to JR/JQ
TCLBV to AC Characteristics
Title to Buswidth timing diagram
8. Changed TCLLH from - 5 ns to -10 ns under
HOLD/HLDA Timings
T YLYH to Buswidth timing diagram
, Hold latency spec
9. Changed T HVCH from 55 ns to 65 ns
10. Changed TAZHAL from 10 ns to 25 ns
External Crystal Connection diagram
External Clock Connection diagram
11 . Changed T BZHAL from 10 ns to 25 ns
12. Changed Icc (max) from 70 mA to 75 mA
13. Changed ICC formula from (3.88
to (3.88X Freq + 13.43)
1O-bit AID Operating Conditions Table
x Freq + 8.43)
14. Changed VOH2 test point from - 50 p.A to
-15 p.A
Title to 10-bit and 8-bit mode AID Characteristics
Voltage on Analog Input Pin specification
Sampling Capacitor typical value
Note 4 to 10-bit and 8-bit AID Specifications
15. Changed Note 1 in DC parameters
8-bit AID Operating Conditions Table
19-24
intel~
8XC196KR/8XC196KQ/8XC196JR/8XC196JQ
Off Isolation, Feedthrough, Vcc Power Supply
Rejection, Input Series Resistance, Voltage on
Analog Input Pin, Sampling Capacitor and DC Input Leakage to 8-bit AID specifications
Notes 1, 2 and 3 to EPROM Programming Conditions
New Errata (Items 10 to 16)
3. Changed:
Title of data sheet from "8XC196KR/KQ/ JR/ JQ
16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER" to "8XC196KR/KQ/ JR/ JQ
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER"
Several bullets on cover sheet
Register RAM numbers in table on front page to
match device
Operating conditions to tabular format
Note 1 in DC Characteristics to include Ports 3
and 4
o to Vss for III and ILl1· in DC Characteristics
~@W~OO©[§ OOOfP@OOIi"il~trO@OO
Format of symbols in AC Characteristics
TCLCH to TCLLH in System Bus Timing diagram
TXLXL Max from 286 ns to 250 ns
TXHXX from Tosc - 44 ns to 35%/65%
TXLXX from T OSC - 44 ns to 35%/65%
TXLXH from Tosc - 50 ns to 10 ns
TXHXL from T OSC - 50 ns to 10 ns
AC Testing Input, Output Waveform
Introductory text on A to D Characteristics and
Converter Specification
DC Input Leakage from ± 1 /LA to ±3 /LA inA/D
Specifications.
Power Dissipation from 0.5W to 1.0W.
Wording in Float Waveform from 100 mV to
150 mV.
EPROM Programming Characteristics to Operating Conditions table.
Data sheet (270912-001) is valid for devices with an
"A" at the end of the topside tracking number. This
is the first version of the data sheet.
19-25
II
I
8XC 196NT/8XC 196NQ
and 8XC 196KT Data Sheets
20
II
8XC196NT/8XC196NQ
CHMOS MICROCONTROLLER WITH
1 MBYTE LINEAR ADDRESS SPACE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•3
•
High Performance CHMOS 16-Bit CPU
Oscillator Fail Detection Circuitry
High Speed Peripheral Transaction
Server (PTS)
Up to 32 Kbytes of On-Chip EPROM
Up to 1 Kbyte of On-Chip Register RAM
Two Dedicated 16-Bit High-Speed
Compare Registers
Up to 512 Bytes of Additional RAM
(Internal RAM)
10 High Speed Capture/Compare (EPA)
Register-Register Architecture
Fu" Duplex Synchronous Serial I/O
Port (SSIO)
4 Channel/10-Bit A/D with Sample/Hold
37 Prioritized Interrupt Sources
•
Two Flexible 16-Bit Timer/Counters
Up to Seven 8-Bit (56) I/O Ports
Quadrature Counting Inputs
Fu" Duplex Serial I/O Port
Flexible 8-/16-Bit External Bus
(Programmable)
Dedicated Baud Rate Generator
Interprocessor Communication Slave
Port
Programmable Bus (HOLD/HLDA)
1.75 p.s 16 x 16 Multiply
Selectable Bus Timing Modes for
Flexible Interfacing
p's
32/16 Divide
68-Pin Package
Device
x
Pins/Package
EPROM
Reg
RAM
Code
RAM
Address
Space
I/O
EPA
A/D
8XC196NT
68P PLCC
32K
1K
512
1 Mbyte
56
10
4
8XC196NQ
68P PLCC
12K
360
128
1 Mbyte
56
10
4
=
7 EPROM Device
The 8XC196NT 16-bit microcontroller is a high performance member of the MCS(r)-96 microcontroller family.
The 8XC196NT is an enhanced 8XC196KR device with 1 MbytE! linear address space, 1000 byte register
RAM, 512 bytes internal RAM, 16 MHz operation and an optional 32 Kbytes of ROM/EPROM. Intel's
CHMOS III-E process provides a high performance processor along with low power consumption.
The 8XC196NT has a maximum guaranteed frequency of 16 MHz. Unless otherwise noted, all references to
the 8XC196NT also refer to the 8XC196NQ.
Ten high-speed capture/compare modules are provided. As capture modules event times with 250 ns resolution can be recorded and generate interrupts. As compare modules events such as toggling of a port pin,
starting an AID conversion, pulse width modulation, and software timers can be generated. Events can be
based on the timer or up/down counter.
20-1
October 1992
Order Number: 272267-001
8XC196NT/8XC196NQ
VREF
ANGND
32K ON-CHIP
ROM/EPROM
(OPTIONAL)
PORT 5
CONTROL
SIGNALS
A/O PORTO
272267-1
Figure 1. 8XC196NT Block Diagram
All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operation conditions and application. See the Intel Packaging Handbook (order
number 240800) for a description of Intel's thermal
impedance test methodology.
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
Table 1. Thermal Characteristics
Package
Type
PLCC
°JC
°JA
36.5°C/W
13°C/W
1~c
-T~ ~
1
!! §
!"::!
Device Speed:
No Mark
= 16 MHz
NT Product Family
CHMOS Technology
Program ""emory Options:
7 ::: EPRO~ (Note 1)
L -_ _ _ _ _ _ _ _ _ _
Package Type Options:
=68-lead PLee
N
L
_ _ _ _ _ _ _ _ _ _ _ Temperature end Burn-in Options:
No l.Iark =
70 0 C Ambient with
Int.l Standard Burn-in
ooe -
272267-2
EXAMPLE: N87C196NT is 68·Lead PLCC OTPROM, 16 MHz.
For complete package dimensional data. refer to the Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable (OTPROM) only.
Figure 3. The 8XC186NT Familly Nomenclature
20-2
8XC196NT 18XC196NQ
8XC196NT Memory Map
Address
Description
FFFFFFH
FFAOOOH
External Memory
FF9FFFH
FF2080H
Internal EPROM or External Memory (Determined by EA Pin)
RESET at FF2080H
FF207FH
FF2000H
Reserved Memory (Internal EPROM or External Memory)
(Determined by EA Pin)
FF1FFFH
FF0600H
External Memory
FF05FFH
FF0400H
Internal RAM (Identically Mapped into 00400H-005FFH)
FF03FFH
FF0100H
External Memory
FFOOFFH
FFOOOOH
Reserved for ICE
FEFFFFH
100000H
External Memory for future devices
OFFFFFH
OAOOOH
984 Kbytes External Memory
09FFFH
02080H
Internal EPROM or External Memory (Note 1)
0207FH
02000H
Reserved Memory (Internal EPROM or External Memory)
(Notes 1, 3, and 6)
01FFFH
01FEOH
Memory Mapped Special Function Registers (SFR's)
01FDFH
01 FOOH
Internal Special Function Registers (SFR's) (Note 5)
01EFFH
00600H
External Memory
005FFH
00400H
Internal Code or Data RAM
(Address with Indirect or Indexed Modes)
003FFH
Register RAM
00100H
OOOFFH
0001BH
Register RAM
00017H
OOOOOH.
CPU SFR's
'.
II
Upper Register File (Address with Indirect or
)
Indexed Modes or through Windows.) (Note 2)
)
Lower Register File
(Address with Direct,
Indirect, or Indexed
Modes.) (Notes 2,4)
NOTES:
1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA = H. Otherwise they are external
memory.
2. Code executed in locations OOOOOH to 003FFH will be forced external.
3. Reserved memory locations must contain OFFH unless noted.
4. Reserved SFR bit locations must be written with O.
5. Refer to 8XC196NT for SFR descriptions.
6. WARNING: The contents or functions of reserved memory locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these locations may not function properly.
7. The 8XC196NT internally uses 24 bit address, but only 20 address lines are bonded out allowing 1 Mbyte external
address space.
20-3
int'eL
8XC196NT/8XC196NQ
8XC196NT/NQ EXTENDED ADDRESSING INSTRUCTIONS
There are 9 new instructions which have been implemented to support extended addressing in the 8XC196NT
family.
For the following examples, wreg is a word register, treg is a 32-bit register (only the lower 24 bits are used for
addressing) which must be long word aligned (divisable by 4), and XXX is a 24 cbit offset. wreg and treg must
be located in the lower register file.
ELD
Extended Load. May be used in the following addressing modes:
ELD wreg,[treg]
Indirect Mode
ELD wreg,[treg] +
Indirect Autoincrement Mode
ELD wreg,XXX[treg]
Extended Indexed Mode
ELDB
EST
ESTB
EBMOV
EBMOVI
EJMP
EBR
Extended Load Byte. May be used in the following addressing modes:
Indirect Mode
ELDB wreg, [treg]
ELDB wreg, [treg] +
Indirect Autoincrement Mode
ELDB wreg,XXX[treg] Extended Indexed Mode
Extended Store. May be used in the following addressing modes:
EST wreg, [treg]
Indirect Mode
EST wreg, [treg] +
Indirect Autoincrement Mode
EST wreg,XXX[treg]
Extended Indexed Mode
Extended Store By1e. May be used in the following addressing modes:
ESTB wreg,[treg]
Indirect Mode
ESTB wreg,[treg] +
Indirect Autoincrement Mode
ESTB wreg,XXX[treg] Extended Indexed Mode
Extended Block Move (non-interruptable). For the following example, ereg is a quad-word (64-bit)
register, which must be aligned on quad word boundary (divisable by 8). The source of the block is
a 24-bit address at location ereg, and the destination of the block is a 24-bit address at location
ereg + 4. wreg is a word register containing the number of words to move. ereg and wreg must be
in the lower register file.
EBMOV ereg, wreg
Interruptable Extended Block Move. Identical to EBMOV except EBMOVI is interruptable.
EBMOVI ereg, wreg
Extended Jump. Functional in 24-bit mode only (MODE16 = 0). This is an unconditional relative
jump. The distance from the end of this instruction to the target label is added to the 24-bit
program counter, effecting the jump. The target label may be anywhere in the 1 Mby1e address
,space.
EJMP any_label
Extended Branch. Indirect unconditional jump functional in 24-bit mode only (MODE16 = 0). The
24-bit prograrn counter is loaded with the 24-bit address contained in trego Program execution
continues at the address specified in trego
EBRI [treg]
20-4
intel~
ECALL
8XC196NT18XC196NQ
Extended Call. Functional in 24-bit mode only (MODE16 = 0). The contents of the 24-bit program
counter are pushed on the stack in two words (32 bits). Then the distance from the target label is
added to the 24-bit program counter, effecting the call. The target label may be anywhere in the 16M
address space.
ECALL any_subroutine
NOTES:
The new extended instructions support 24-bit addressing, but the 8XC196NT only supports accessing
1 Mbyte external memory.
When operating in the 24-bit mode (MODE16
0), all calls, returns, and interrupts always push/pop
4 bytes on the stack. Extra state times are required for this operation, so code using these instructions will
execute slower than code in 16-bit mode.
Location OOH (the "zero" register) will always be read as zero, even when read as double word.
I~ I~
.....
~
.... >-e
""-< III~ """"a::
...............
"'"
I~~~
'"lI'i '"ari
Il.
Il.
,..,
u-i
Il.
C U
....I
0.
III
~ >III
X
0
e
0
'"
15
III III III III ....
,..,
.... ..;
62.5
TXHCH
XTAL 1 High to CLKOUT High or Low
+20
TOFD
Clock Failure to Reset Pulled Low(6)
4
TCLCL
CLKOUT Period
ns
ns
40
p,s
ns
2 Tosc
TCHCL
CLKOUT High Period
Tosc - 10
Tosc + 30
ns
TCLLH
CLKOUT Low to ALE/ ADV High
-20
+15
ns
TLLCH
ALE/ ADV Low to CLKOUT High
-20
+15
ns
ns(5)
TLHLH
ALE/ ADV Cycle Time
TLHLL
ALE/ ADV High Time
Tosc - ,10
TAVLL
Address Valid to ALE Low
Tosc - 25
ns
TLLAX
Address Hold After ALE/ ADV Low
Tosc - 40
ns
"fLLRL
ALE/ADV Low to RD Low
Tosc - 30
ns
TRLCL
RD Low to CLKOUT Low
TRLRH
RD Low Period
TRHLH
RD High to ALE/ ADV High
TRLAZ
RD Low to Address Float
"fLLWL
ALE/ ADV Low to WR Low
Tosc - 10
TCLWL
CLKOUT Low to WR Low
-20
4 Tosc
+4
rOSC + 10
+40
Tosc
+ 25
+5
TOVWH
Data Valid before WR High
Tosc - 23
TCHWH
CLKOUT High to WR High
-10
ns
ns(5)
Tosc - 5
Tosc
ns
ns(3)
ns
ns
+25
ns
ns
+15
ns
ns(5)
TWLWH
WR Low Period
Tosc - 30
TWHOX
Data Hold after WR High
Tosc - 25·
ns
TWHLH
WR High to ALE/ ADV High
Tosc - 10
ns(3)
TWHBX
SHE, INST Hold after WR High
Tosc - 15
ns
ns(4)
Tosc + 15
TWHAX
AD8 -15 Hold after WR High
Tosc - 30
TRHBX
SHE, INST Hold after RD High
Tosc - 10
ns
TRHAX
AD8-15 Hold after RD High
Tosc - 30
ns(4)
NOTES:
1.
2.
3.
4.
5.
Testing performed at 8.0 MHz, however, the device is static oy design and will typically operate below 1 Hz.
Typical specifications, not guaranteed.
Assuming back-to-back bus cycles.
8-bit bus only.
If wait states are used, add 2 Tasc x n, where n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 Tasc to specification.
6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H. NTINO customer OROM codes need to equate location
2016H to the value OCDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H
as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit
enables oscillator fail detection.
20-12 .
int'et
8XC196NT18XC196NQ
BUS MODE 0 and 3-8XC196NT SYSTEM BUS TIMING
XTAL1
CLOCKOUT
ALE/ADV
RD
BUS READ
ADDRESS OUT
1-----+-- TAVDV
TLLWL
BUS WRITE
--i--
ADDRESS OUT
I-------<~- TWHBX or TRHBX
BHE, INST
BHE, INST VALID
I-'"------<~- TWHAX or TRHAX
AD8 -AD15
ADDRESS OUT AD8-AD15 VALID 8-BIT BUS MODE
272267-5
·If mode 0 operation is selected, add 2 T asc to this time.
20-13
infel .
8XC196NT/8XC196NQ
8XC196NT MODE 0 and 3-READY TIMINGS (ONE WAIT STATE)
XTALI
CLKOUT
ALE
READY
TRLRH + 2 Tose
r- TRHDX
'I
DATA
IN
»}»»)>C
)
(
~~::::~A~DD~R~~S~O~U~T::::::>-------------------C::!~~::~~~
TAVOV + 2 Tose
BUS READ
W.
BUS WRITE
~.
~
TWLWH + 2 Tose
I
::X~::::::A:DD:RE:SS:O:U:T: : : : : :)«~~
I-
TQVWH + 2 Tose
DATA OUT
x::::
272267-6
'If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 Tasc to these specifications.
MODE 0 and 3-8XC196NT BUSWIDTH TIMINGS
XTAL 1
c:'::: ~,.....----,{,=.~
'= /
,
,'------
~:.:::::::::::::::::::::::::::::::~
BUSWIDTH
I----
BUS WRITE
t:
' ____I
::x
TAVGV·-----l
ADDRESS OUT
){«(
DATA OUT
x::::
ADDRESS OUT
X- - - _....
272267-7
'If mode 0 selected, add 2 Tasc to these specifications.
20-14
inteL
8XC196NT18XC196NQ
BUS MODE 1-AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns.
The system must meet these specifications to work with the 8XC196NT.
Symbol
Parameter
TAVYV
Address Valid to Ready Setup
hLYV
ALE Low to READY Setup
TYLYH
Non READY Time
Min
Max
Units
2 Tosc - 75
ns
1.5 Tosc - 70
ns
No Upper Limit
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
0
ns
TOSC - 30
ns(1)
2 TOSC - 75
ns
1.5 Tosc - 60
ns
ns
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
0
3 TOSC - 60
ns(2)
TRLDV
RD active to input Data Valid
2 Tosc - 44
ns(2)
TCLDV
CLKOUT Low to Input Data Valid
Tosc - 60
ns
TRHDZ
End of RD to Input Data Float
Tosc
ns
TRHDX
Data Hold after RD High
0
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tase x n, where n = number of wait states.
20·15
ns
axc 196NTlaXC196NQ
BUS MODE 1-AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns.
The 8XC196NT will meet these specifications
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL 1
B.O
16.0
MHz(1)
Tosc
XTAL1 Period (1/FxTAJ
62.5
125
ns
+20
110
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
ns
2 Tosc
Tosc - 10
Tosc + 27
ns
ns
TCHLH
CLKOUT HIGH to ALE/ ADV High
0.5 Tosc - 10
0.5 Tosc + 15
TCLLL
CLKOUT LOW to ALE/ ADV Low
0.5 Tosc - 25
0.5 Tosc + 15
TLHLH
ALE/ ADV Cycle Time
TLHLL
ALE/ ADV High Time
TAVLL
Address Valid to ALE Low
TLLAX
Address Hold After ALE/ ADV Low
TLLRL
ALE/ ADV Low to RD Low
0.5 Tosc - 10
TRLCL
RD Low to CLKOUT Low
Tosc - 10
TRLRH
RD Low Period
TRHLH
RD High to ALE/ ADV High
TRLAZ
RD Low to Address Float
TLLWL
ALE/ ADV Low to WR Low
0.5 Tasc - 10
TCLWL
CLKOUT Low to WR Low
Tasc - 25
TOVWH
Data Valid before WR High
TCHWH
CLKOUT High to WR High
TWLWH
WR Low Period
TWHOX
Data Hold after WR High
4 Tosc
Tosc - 10
ns
ns(5)
Tosc + 10
ns
0.5 Tosc - 20
ns
Tasc - 40
ns
ns
Tosc + 30
2 Tosc - 20
0.5 Tasc
0.5 Tasc + 25
ns(3)
+5
ns
ns
Tasc + 25
ns
ns
2 Tasc - 23
-10
ns
ns(5)
+15
ns
ns(5)
2 Tasc - 20
0.5 Tasc - 25
ns
0.5 Tasc - 10
ns(3)
TWHLH
WR High to ALE/ ADV High
TWHBX
SHE Hold after WR High
Tasc - 15
TWHIX
INST Hold after WR High
0.5 Tasc - 15
TWHAX
ADB-15 Hold after WR High
0.5 Tasc - 30
ns(4)
TRHBX
SHE Hold after RD High
Tasc - 32
ns
TRHIX
INST Hold after RD High
0.5 Tasc - 32
TRHAX
ADB-15 Hold after RD High
0.5 Tasc - 30
0.5 Tasc + 10
NOTES:
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 Tasc x n, where n = number of wait states.
20-16
ns
ns(4)
8XC196NT/8XC196NQ
MODE 1-8XC196NT SYSTEM BUS TIMING
XTALl
CLOCKOUT
ALE/ADV
III
RD
BUS READ
ADDRESS
TAVDV
TLLWL
------1·1
1----0-++---- TWLWH
BUS WRITE
BHE
-----ADDRESS OUT
'"",_0__--- TOVWH
-----I
----+-l_-+-Ii+-
TWHOX
DATA OUT
SHE VALID
1+---'_ TWHAX' TRHAX
AD8 - AD15
~------------------------~--~
ADB-AD15 VALID B-BIT BUS MODE
1--1_ TWHIX' TRH1X
INST
=:=J(=================IN=ST=V=A=L1=D==============~===X~
20-17
____
_
272267-8
8XC196NT/8XC196NQ
MODE 1-8XC196NT READY TIMINGS (ONE WAIT STATE)
XTALl
CLKOUT
ALE
----'
READY
TRLRH + 2 Tose
RD
'I
(
TAVDV + 2 Tose
~~~~~~~~»X
BUS READ
)
ADDRESS OUT
~.
WR
I
H
BUS WRITE
)«~~
ADDRESS OUT
~
TWLWH + 2 Tose
r
»»»»»
DATA I~
TaVWH + 2 Tose
DATA OUT
>--
272267-9
MODE 1-8XC196NT BUSWIDTH TIMINGS
XTAL1
CLKOUT
ALE
J
\
/
/
\
I---
TLLGV
BUSWIDTH
I'
BUS WRITE
}-{
TAVGV
ADDRESS OUT
6,=
--1
~
xm
/
\
/
/
\
x:
,I
DATA OUT
}-{
ADDRESS OUT
)«~~
272267-10
20-18
intel~
8XC196NT18XC196NQ
BUS MODE 2-AC CHARACTERISTICS (Over Specified Operating Conditions)
= 100 pF, Rise and Fall Times = 10 ns.
Test Conditions: Capacitance Load on All Pins
The system must meet these specifications to work with the 8XC196NT.
Symbol
Parameter
TAVYV
Address Valid to Ready Setup
TLLYV
ALE Low to READY Setup
TYLYH
Non READY Time
Min
Max
Units
2.5 Tosc - 75
ns
1.5 Tosc - 70
ns
No Upper Limit
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
RD active to input Data Valid
TCLDV
CLKOUT Low to Input Data Valid
TRHDZ
End of RD to Input Data Float
TRHDX
Data Hold after RD High
0
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC x n, where n = number of wait states.
20-19
Tosc - 30
2.5 Tosc - 75
ns
1.5 Tosc - 60
ns
3.5 Tosc - 55
ns(2)
2 Tosc - 44
ns(2)
Tosc - 60
ns
0.5 Tosc
ns
0
0
ns
ns(1)
ns
ns
8XC196NT18XC196NQ
BUS MODE 2-AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns.
The 8XC196NT will meet these specifications
Symbol
FXTAL
Parameter
Frequency on XTAL 1
Min
Max
Units
8.0
16.0
MHz(l)
Tosc
XTAL 1 Period (1 /FXTALl
62.5
125
ns
TXHCH
XTAL 1 High to CLKOUT High or Low
+20
+85
ns
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TCHLH
CLKOUT HIGH to ALE/ ADV High
TCLLL
CLKOUT LOW to ALE/ ADV Low
ns
2 Tosc
Tosc + 27
ns
0.5 Tosc - 10
0.5 Tosc + 15
ns
0.5 Tosc - 25
0.5 Tosc + 15
Tosc - 10
ns
ns(5)
hHLH
ALE/ ADV Cycle Time
hHLL
ALE/ ADV High Time
Tosc - 10
TAVLL
Address Valid to ALE Low
Tosc - 15
ns
TLLAX
Address Hold After ALE/ ADV Low
Tosc - 40
ns
hLRL
ALE/ ADV Low to RD Low
0.5 Tosc - 10
TRLCL
RD Low to CLKOUT Low
Tosc - 10
TRLRH
RD Low Period
2 Tosc - 20
TRHLH
RD High to ALE/ ADV High
0.5 Tosc - 5
TRLAZ
RD Low to Address Float
hLWL
ALE/ ADV Low to WR Low
0.5 Tosc - 10
TCLWL
CLKOUT Low to WR Low
Tosc - 22
4 Tosc
Tosc + 10
ns
ns
Tosc + 30
ns
ns(5)
0.5 Tosc + 25
ns(3)
+5
ns
ns
Tosc + 25
ns
ns
TOVWH
Data Valid before WR High
2 Tosc - 25
TCHWH
CLKOUT High to WR High
-10
TWLWH
WR Low Period
2 Tosc - 20
ns(5)
TWHOX
Data Hold after WR High
0.5 Tosc -25
ns
TWHLH
WR High to ALE/ ADV High
0.5 Tosc - 10
TWHBX
SHE Hold after WR High
+15
0.5 Tosc + 10
Tosc - 15
ns
ns(3)
ns
I
TWHIX
INST Hold after WR High
0.5 Tosc -15
TWHAX
AD8-15 Hold after WR High
0.5 Tosc - 30
ns(4)
ns
TRHBX
SHE Hold after RD High
Tosc - 32
TRHIX
INST Hold after RD High
0.5 Tosc - 32
TRHAX·
AD8-15 Hold after RD High
0.5 Tosc - 30
NOTES:
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 TOSC x n, where n = number of wait states.
20-20
ns(4)
intel~
8XC196NT/8XC196NQ
MODE 2-8XC196NT SYSTEM BUS TIMING
XTAL1
CLOCKOUT
ALE/ADV
II
BUS READ
ADDRESS OUT
-----+I.1
TAVDV
TLLWL
1+-----0-\+-----'-- TWLWH - - - - - I
WR
BUS WRITE
r---------
------------~--~
,---------------ADDRESS OUT
""100-----
TQVWH ----11-_1-- TWHQX
DATA OUT
BHE VALID
1--11-- TWHAX' TRHAX
ADS - AD15
r-------------------------~~
AD8 - AD 15 VALID 8-BIT BUS MODE
1--11-- TWH1X' TRH1X
INST
==:J(=================IN=ST=V=A=LI=D==============~==~X~
272267-11
____
20-21
8XC196NT18XC196NQ
MODE 2-8XC196NT READY TIMINGS (ONE WAIT STATE)
XTALI
CLKOUT
ALE
READY
TAVYV
RD
I;
mX
BUS READ
~-~============_TRL_RH_+_2_~_os_e~~~_-~-_-_-_-_-_-_-_:?~J-----
I
X
(
)
DATAIN
»)X,-__
__
~;.:=~~~~~~_-_-_-_T_WL_WH_+_2_T_ose_-_-_-_-_-_~~~~-~!--\------- TQVWH +2Tose -----~+I
WR
BUS WRITE
'i
TAVDV + 2 Yose '
ADDRESS OUT
ADDRESS OUT
X«< ______D_AT_AO_U_T______
u.~
~)~)U~~__
272267-12
MODE 2-8XC196NT BUSWIDTH TIMINGS
XTALI
CLKOUT
ALE
J
\
/
/
\
I- TLLGV ---I
/
/
\
x::
~
BUSWIDTH
iBUS WRITE
t.".
\
/
X
T.vGV
ADDRESS OUT
)«~~
,I
DATA OUT
mx
272267-13
20-22
in1:et
8XC196NT18XC196NQ
BUS MODE 0, 1, 2, and 3-HOLD/HOLDA TIMINGS (Over Specified Operation Conditions)
= 100 pF, Rise and Fall Times = 10 ns.
Test Conditions: Capacitance Load on All Pins
Symbol
Parameter
Min
Units
Max
ns(l)
THVCH
HOLD Setup Time
+65
TCLHAL
CLKOUT Low to HLDA Low
-15
+15
ns
TCLBRL
CLKOUT Low to SREQ Low
-15
+15
ns
TAZHAL
HLDA Low to Address Float
+25
ns
TBZHAL
HLDA Low to SHE, INST, RD, WR Weakly Driven
+25
ns
TCLHAH
CLKOUT Low to HLDA High
-25
+15
ns
TCLBRH
CLKOUT Low to SREQ High
-25
+25
ns
THAHAX
HLDA High to Address No Longer Float
-15
ns
THAHBV
HLDA High to SHE, INST, RD, WR Valid
-10
ns
NOTE:
1. To guarantee recognition at next clock.
8XC196NT HOLD/HOLDA TIMINGS
A~
CLKOUT\
~
TH~tl-
HOLD
~+--~r_-....I
LAT~~~~
BREQ
BUS
BHE, INST,
RD,WR
ALE
::::)(--------------;-t:=---;J---~~-__H_(====::J
---------,--iI~1
' l~'-
r--t:::::::::'::z':
THc..AL_BZ_ _ _ _ _
,
,
r-\.
-----J
~r_l-----il!_l------J
272267-14
20-23
..
intel .
8XC196NT18XC196NQ
AC CHARACTERISTICS-SLAVE PORT
SLAVE PORT WAVEFORM--(SLPL = 0)
\~
________________________-JI
""TSRHAV
-
ALE/AI ~
X
TSRLRH
"-
I
TSRLDV
TSWLWH
TSAYWL
"-
TSRHDZ
~
r
TSWHQX
272267-15
SLAVE PORT TIMING--(SLPL = 0,1,2,3)
Symbol
Parameter
Min
Max
Units
TSAVWL
Address Valid to WA Low
50
ns
TSRHAV
AD High to Address Valid
60
ns
TSRLRH
AD Low Period
Tosc
ns
TSWLWH
WA Low Period
Tosc
ns
TSRLDV
AD Low to Output Data Valid
TSDVWH
Input Data Setup to WA High
TSWHQX
TSRHDZ
60
ns
ns
WA High to Data Invalid
20
30
AD High to Data Float
15
ns
NOTES:
1. Test Conditions: Fose = 16 MHz, Tose = 60 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
20·24
ns
intet
8XC196NT18XC 196NQ
AC CHARACTERISTICS-SLAVE PORT (Continued)
SLAVE PORT WAVEFORM-(SLPL
1)
=
.r-==\.
TSRHEH
TSELLL
I
r-'
ALE
TSRLRH
TSLLRL
TSRHDZ
TSRLDV
P3
L
TSAVLl
J
TSLLAX "
I
TSOVWH
TSWHOX
TSWLWH
"
272267-16
SLAVE PORT TIMING-(SLPL = 1,2,3)
Symbol
TSELLL
Max
Units
Parameter
Min
CS Low to ALE Low
20
ns
60
ns
TSRHEH
RD or WR High to CS High
TSLLRL
ALE Low to RD Low
Tosc
ns
TSRLRH
RD Low Period
Tosc
ns
TSWLWH
WR Low Period
Tosc
ns
TSAVLL
Address Valid to ALE Low
20
ns
TSLLAX
ALE Low to Address Invalid
20
TSRLDV
RD Low to Output Data Valid
ns
60
ns
TSDVWH
Input Data Setup to WR High
20
ns
TSWHQX
WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
NOTES:
1. Test Conditions: Fose = 16 MHz, Tose = 60 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
20-25
•
int'et
8XC196NT/8XC196NQ
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
4
16
MHz
62.5
250
ns
x
x
Tose
0.65 Tose
ns
Tose
1/TxLXL
Oscillator Frequency
TXLXL
Oscillator Period (Tosel
TXHXX
High Time
0.35
TXLXX
Low Time
0.35
0.65 Tose
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272267-17
AC TESTING INPUT, OUTPUT WAVEFORMS
INPUTS
OUTPUTS
3.SVJ\E
)
O.4SV
FLOAT WAVEFORMS
2.0V
)
TEST POINTS (
O.BV
TIMING REFERENCE
POINTS
<
272267-19
For timing purposes a Port Pin is no longer floating
when a 150 mV change from load voltage occurs and
begins to float when a 150 mV change from the loading
VOHIVOl level occurs IOl/lOH ,,; 15 mA.
272267-18
Ae Testing inputs are driven at 3.5V for a logic "1" and
0.45V for a logic "0". Timing measurements are made
at 2.0V for a logic "1" and O.BV for logic "0".
20-26
int:et
8XC196NT/8XC196NQ
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE
272267-20
II
AC CHARACTERISTICS-SERIAL PORT-SHIF"r REGISTER MODE
SERIAL PORT TIMING-8HIFTING REGISTER MODE
Test Conditions: T A = -40·C to + 125·C; Vee = 5.0V ± 10%; Vss
Symbol
Parameter
=
O.OV; Load Capacitance
Min
TXLXL
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
Max
TQVXH
Output Data Setup to Clock Rising Edge
TXHQX
Output Data Hold after Clock Rising Edge
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX(1)
Input Data Hold after Clock Rising Edge
TXHQZ(1)
Last Clock Rising to Output Float
Tose
+ 50
1. Parameters not tested.
20-27
Units
ns
3 Tose
ns
2 Tose - 50
ns
2 Tose
2 Tose
+ 50
+ 200
ns
ns
0
ns
5 Tose
NOTE:
pF
ns
BTose
4Tose-5O
=
ns
intel .
8XC196NT18XC196NQ
A to D CHARACTERISTICS
The AID converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
10-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
DC
TA
Ambient Temperature
0
+70
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V(1)
TSAM
Sample Time
1.0
Conversion Time
10
15
,..,s(2)
4.0
16.0
MHz
TeONV
. Oscillator Frequency
Fose
,..,s(2)
NOTES:
1. VREF must be within O.SV 01 Vee.
2. The value 01 AD_TIME is selected to meet these specifications.
10-BIT MODE AID CHARACTERISTICS (Using Above Operating Conditions)(6)
Parameter
Typ·(1)
Resolution
Absolute Error
Full Scale Error
0.25 ±0.5
Zero Offset Error
0.25 ±0.5
Non-Linearity
Min
Max
Units·
1024
10
1024
10
Level
Bits
0
±3.0
LSBs
LSBs
LSBs
1.0 ±2.0
±3.0
LSBs
LSBs
-0.75
+0.75
Channel-to-Channel Matching
±0.1
0
±1.0
Repeatability
±0.25
0
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
Differential Non-Linearity
LSB/C(1)
LSB/C(1)
LSB/C(1)
Feedthrough
Vee Power Supply Rejection
-60
dB(1,2)
dB(1,2)
1.2K
n(4)
0
±3.0
ANGND -0.5
VREF + 0.5
,..,A
V(S)
Input Resistance
DC Input Leakage
dB(1,2,3)
-60
Off Isolation
-60
LSBs
LSBs(1)
750
±1.0
Voltage on Analog Input Pin
Sampling Capacitor
3.0
·An ULSBn as used here has a value 01 approximately 20 mV.
NOTES:
1. These values are expected lor most parts at 2Soe, but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer break-belore-make is guaranteed.
4. Resistance Irom device pin, through internal MUX, to sample capacitor.
5. Applying voltages beyond these speCifications will degrade the accuracy 01 other channels being converted.
6. All conversions performed with processor in IDLE mode.
20-28
pF
int:et
8XC196NT/8XC196NQ
8-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
Ambient Temperature
0
+70
°C
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V(1)
TSAM
Sample Time
TeONv
Conversion Time
Fose
Oscillator Frequency
TA
,...s(2)
1.0
7
20
,...s(2)
4.0
16.0
MHz
NOTES:
1. VREF must be within O.SV of Vee.
2. The value of AD_TIME is selected to meet these specifications.
8-BIT MODE AID CHARACTERISTICS
Parameter
(Using Above Operating Conditions)(6)
Typ*(1)
Resolution
Absolute Error
Full Scale Error
±0.5
Zero Offset Error
±0.5
Differential Non·Linearity
±0.25
0.003
0.003
0.003
Units'
256
8
256
8
Level
Bits
0
±1.0
LSBs
LSBs
Channel·to·Channel Matching
Repeatability
Max
LSBs
Non·Linearity
Temperature Coefficients:
Offset
Full Scale
Differential Non·Linearity
Min
0
±1.0
LSBs
-0.5
+0.5
LSBs
0
±1.0
LSBs
LSBs(1)
0
LSB/C(1)
LSB/C(1)
LSB/C(1)
dB(1.2,3)
-60
Off Isolation
Feedthrough
-60
dB(1,2)
Vee Power Supply Rejection
-60
dB(1,2)
Input Resistance
DC Input Leakage
±1.0
Sampling Capacitor
1.2K
0
±3.0
,...A
VREF + 0.5
VIS)
ANGND - 0.5
Voltage on Analog Input Pin
3.0
pF
'An "LSS" as used here has a value of approximately 20 mY.
NOTES:
1. These values are expected for most parts at 2S'e, but are not tested or guaranteed.
2. DC to 100 KHz.
3.
4.
5.
6.
n(4)
750
Multiplexer break·before·make is guaranteed.
Resistance from device pin, through internal MUX, to sample capacitor.
Applying voltage beyond these speCifications will degrade the accuracy of other channels being converted.
All conversions performed with processor in IDLE mode.
20·29
•
intel~
8XC196NT/8XC196NQ
EPROM SPECIFICATIONS
OPERATING CONDITIONS
Min
Max
Units
!A
Ambient Temperature During Programming
Description
20
30
'C
Vee
Supply Voltage During Programming
4.5
5.5
V(1)
VREF
Reference Supply Voltage During Programming
4.5
5.5
V(1)
Vpp
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
Fose
Oscillator Frequency during Auto
and Slave Mode Programming
6.0
8.0
MHz
Fose
Oscillator Frequency during
Run-Time Programming
6.0
16.0
MHz
Symbol
I
L
NOTES:
1. Vee and VREF should nominally be at the same voltage during programming.
2. Vpp and VEA must never exceed the maximum specification, or the device may be damaged.
3. Vss and ANGND should nominally be at the same potential (OV).
4. Load capacitance during Auto and Slave Mode programming = 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)
Symbol
Parameter
Min
Max
Units
TAVLL
Address Setup Time
0
Tose
TLLAX
Address Hold Time
100
Tose
TDVPL
Data Setup Time
0
Tose
TpLDX
Data Hold Time
400
Tose
TLLLH
PALE Pulse Width
50
Tose
TpLPH
PROG Pulse Width(2)
50
Tose
lLHPL
PALE High to PROG Low
220
Tose
TpHLL
PROG High to next PALE Low
220
TpHDX
Word Dump Hold Time
TpHPL
PROG High to next PROG Low
220
TLHPL
PALE High to PROG Low
220
TpLDV
PROG Low to Word Dump Valid
TSHLL
RESET High to First PALE Low
TpHIL
PROG High to AINC Low
Tose
50
Tose
Tose
Tose
50
Tose
1100
Tose
0
Tose
T'LiH
AINC Pulse Width
240
Tose
T,LVH
PVER Hold after AINC Low
50
Tose
T'LPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Valid
Tose
220
Tose
NOTES:
1. Run·time programming is done with Fose = 6.0 MHz to 10.0 MHz, Vee, VPD, VREF = 5V ±0.5V, Te = 25'e ±5'e and
Vpp = 12.5V ± 0.25V. For run·time programming over a full operating range, contact factory.
3. This specification is for the word dump mode. For programming pulses use Modified Quick Pulse Algorithm.
8XC196NT18XC196NQ
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Units
Ipp
Vpp Programming Supply Current
mA
NOTE:
Do not apply Vpp unti Vee is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
•
--J
I- TAVLL ----I
----
PALE
P2.1
PROG
P2.2
PVER
P2.0
AiNC
P2.4
272267-23
8XC196NT/NQ ERRATA
workaround:
The following is a list of all known functional deviations for 8XC196NTINa devices. C-step devices
can be identified by a special mark following the
eight digit FPO number on the top of the package.
For C-step devices, this mark is a HC".
1. Base-indexed ELD, ELDB, EST, ESTB instructions: The ELD, ELDB, EST, ESTB instructions
using the base-indexed addressing mode do not
function when executed from external memory.
For example:
LD
LD
ELD
ELD 20h, #Ob1000h[RO]
;30-32h forms pointer
;to extended memory
;this mode works
correctly
2. 24-bit mode auto-increment across 64K boundaries. When in 24-bit mode (MODE16 = 0), the
auto increment addressing mode does not increment correctly across 64K boundaries.
;does not work
20-32
30h, # 1000h
32h, #OOObh
20h, [30h]
8XC196KT
COMMERCIAL CHMOS MICROCONTROLLER
•
•
•
•
•
•
•
•
•
•
•
High Performance CHMOS 16-Bit CPU
Up to 32 Kbytes of On-Chip EPROM
Up to 1 Kbyte of On-Chip Register RAM
Up to 512 Bytes of Additional RAM
(Internal RAM)
Register-Register Architecture
8 Channel/10-Bit AID with Sample/Hold
37 Prioritized Interrupt Sources
Up to Seven 8-Bit (56) I/O Ports
Full Duplex Serial I/O Port
Dedicated Baud Rate Generator
Interprocessor Communication Slave
Port
•
Selectable Bus Timing Modes for
Flexible Interfacing
•
•
•
Oscillator Fail Detection Circuitry
High Speed Peripheral Transaction
Server (PTS)
Two Dedicated 16-Bit High-Speed
Compare Registers
10 High Speed Capture/Compare (EPA)
• Full
Duplex Synchronous Serial I/O
•
•
•
•
•
•
•
•
Port (SSIO)
Two Flexible 16-Bit Timer/Counters
Quadrature Counting Inputs
Flexible 8-/16-Bit External Bus
(Programmable)
Programmable Bus (HOLD/HLDA)
1.75 p,s 16 x 16 Multiply
3 p,s 32/16 Divide
68-Pin PLCC Package
Pins/Package
X
=
Address Space
6B-Pin PLCC
7 EPROM Device
64 Kbyte
The. BXC196KT 16-bit microcontroller is a high performance member of the MCS®-96 microcontrolier family.
The 8XC196KT is an enhanced BXC196KR device with 1000 byte register RAM, 512 bytes internal RAM,
16 MHz operation and an optional 32 Kbytes of ROM/EPROM. Intel's CHMOS III-E process provides a high
performance processor along with low power consumption.
The BXC196KT has a maximum guaranteed frequency of 16 MHz.
Ten high-speed capture/compare modules are provided. As capture modules event times with 250 ns resolution can be recorded and generate interrupts. As compare modules events such as toggling of a port pin,
starting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be
based on the timer or up/down counter.
20-33
October 1992
Order Number: 272266-001
II
inteL
VREF
8XC196KT
ANGND
32K ON-CHIP
ROM/EPROM
(OPTIONAL)
PORTS
CONTROL
SIGNALS
PORT 2/
HOLD CONTROL
A/D PORTO
272266-1
Figure 1. 8XC196KT Block Diagram
x
XX _8
'-c7
G
X C
~~§!S~ ~
I
Device Speed:
No Mark = 16 MHz
KT Product Family
CHMOS Technology
' - - - - - - - - - - - Program Memory Options:
7 = EPROM (Not. 1)
' - - - - - - - - - - - - - - Package Type Options:
N 68-lead PLCC
=
' - - - - - - - - - - - - - - - - Temperature end Burn-in Options:
No Mark = OOC - 70°C Ambient with
Intel Standard Burn-in
272266-2
EXAMPLE: N87C196KT is 68-Lead PLCC OTPROM.
For complete package dimensional data, refer to the Intel Packaging Handbok (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable (OTPROM) only.
Figure 2. The 8XC196KT Family Nomenclature
20-34
intaL
8XC196KT
8XC196KT Memory Map
PROCESS INFORMATION
FFFFH 24 Kbytes External Memory
AOOOH
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
9FFFH
2080H
Table 1. Thermal Characteristics
Package
Type
0ja
0je
PLCC
36.5°C/W
13°C/W
Internal EPROM or External Memory
207FH Reserved Memory (Internal EPROM
2000H or External Memory)(4, 5)
1FFFH Memory Mapped Special Function
1FEOH Registers (SFR's)
1FDFH Internal Special Function
1FOOH Registers (SFR's)(4)
All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operation conditions and application. See the Intel Packaging Handbook (Order
Number 240800) for a description of Intel's thermal
impedance test methodology.
1EFFH External Memory
0600H
05FFH Internal Code or Data RAM (Address
0400H with Indirect or Indexed Modes)
03FFH
Register RAM
0100H
OOFFH
Register RAM
0018H
0017H
OOOOH
CPU SFR's
)
Upper Register File
(Address with Indirect or
Indexed Modes or through
Windows)(1)
)
Lower Register File
(Address with Direct,
Indirect, or Indexed
Modes)(1,3)
NOTES:
1. Code executed in locations OOOOH to 03FFH will be
forced external.
2. Reserved memory locations must contain OFFH unless
noted.
3. Reserved SFR bit locations must be written with O.
4. Refer to 8XC196KT for SFR descriptions.
5. WARNING: The contents or functions of reserved memory locations may change with future revisions of the device. Therefore, a program that relies on one or more of
these locations may not function properly.
20-35
intel·
~OO~IbOIMlOOO~OOW
8XC196KT
on
on
on a..
a.. ......
0
"!
~~~
I'" . . .
I~ ffi I~
on
a..
a.
a.
>
l-
on zii:
I~~ ......a..on ......a..~ ......'"...J
...
III '"
III...J
> < !:
'" ~ ona..
U>
I-
""
-...J
111<
'"
...J
~
>VJ !;( ><
""
0 ;:; c0 00 is
;:::
......
'"..... ~U> ~on ......'" ........,
...
cD cD Q.
cD Q.
cD Q.
cD
a.. a..
BUSWIDTH/P5.7
P6.2/TlCLK
AD15/P4.7
P6.1/EPA9
AD14/P4.6
P6.0/EPA8
AD13/P4.5
Pl.0/EPAO/T2CLK
AD12/P4.4
Pl.l/EPAl
ADll/P4.3
P 1.2/EPA2/T2DIR
8XC196KT
AD10/P4.2
Pl.3/EPA3
68-PIN
PLCC
TOP VIEW
P1.4/EPA4
Component Side
of PC Boord
Pl.7/EPA7
A09/P4.1
AD8/P4.0
AD7/P3.7
AD6/P3.6
AD5/P3.5
P1.5/EPA5
P1.6/EPA6
VREF
AD4/P3.4
ANGND
AD3/P3.3
PO.7/ACH7
AD2/P3.2
PO.6/ACH6
AD1/P3.1
PO.5/ACH5
ADO/P3.D
PD.4/ACH4
It;;~
'"
~ I~ >el
Z
u c
>u t'!:
.......
0
c
'"
:::-
'" '"
Q.
Q.
..,
I-~Ii~ ;:::.'" ~ :::- ...... ........,
>< z
..... :)
..J
C
~ 8i ~ ~ ~
~ tI! -
Q.
~ ~ :::>
~ ~ ~
~ ~
Q.
Q.
.....
0
'"
0
%
0
0
i0
<
'"<
%
0
%
0
<
'"
0
0
0
0
Q.
Q.
Q.
Q.
...J
0
272266-3
20-36
int:et
8XC196KT
PIN DESCRIPTIONS
Symbol
Name and Function
(+ 5V).
Vee
Main supply voltage
VSS, VSSio VSSI
Digital circuit ground (OV). There are multiple VSS pins, all of which MUST be
connected.
VREF
Reference for the AID converter (+ 5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for
AID and Port 0 to function.
Vpp
Programming voltage for the EPROM parts. It should be + 12.5V for programming. It
is also the timing pin for the return from powerdown circuit.
ANGND
Reference ground for the AID converter. Must be held at nominally the same
potential as VSS.
XTAL1
Input of the oscillator inverter and the internal clock generator.
XTAL2
Output of the oscillator inverter.
P.27/CLKOUT
Output of the internal clock generator. The frequency is % the oscillator frequency. It
has a 50% duty cycle. Also LSIO pin.
RESET
Reset input to and open-drain output from the chip.
P5.7/BUSWIDTH
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an
a-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is "0" and
CCR 1 bit 2 is "1 ", all bus cycles are a-bit, if CCR bit 1 is "1" and CGR 1 bit 2 is "0", all
bus cycles are 16-bit. CCR bit 1 = "0" and CGR 1 bit 2 = "0" is illegal. Also an LSIO
pin when not used as BUSWIDTH.
NMI
A positive transition causes a non maskable interrupt vector through memory location
203EH.
P5.1I1NST
Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is active only during external memory
fetches, during internal EPROM fetches INST is heldlow. Also LSIO when not INST.
EA
Input for memory select (External Access). EA equal to a high causes memory
accesses to locations 2000H through 9FFFH to be directed to on-chip EPROM/ROM.
EA equal to a low causes accesses to these locations to be directed to off-chip
memory. EA = + 12.5V causes execution to begin in the Programming Mode. EA is
latched at reset.
HOLD
Bus Hold input requesting control of the bus.
HLDA
Bus hold acknowledge output indicating release of the bus.
BREQ
Bus request output activated when the bus controller has a pending external memory
cycle .
. P5.01 ALEI ADV
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive (high) at the end of the bus cycle. ADV can be used as a chip
select for external memory. ALEI ADV is active only during external memory
accesses. Also LSIO when not used as ALE.
P5.3/RD
Read signal output to external memory. RD is active only during external memory
reads or LSIO when not used as RD.
P5.2/WR/WRL
Write and Write Low output to external memory, as selected by the GCR, WR will go
low for every external write, while WRL will go low only for external writes where an
even byte is being written. WR/WRL is active during external memory writes. Also an
LSIO pin when not used as WR/WRL.
20-37
inteL
8XC196KT
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
P5.5/SHE/WRH
Syte High Enable or Write High output, as selected by the CCA. SHE = 0 selects the
bank of memory that is connected to the high byte of the data bus. AO = 0 selects
that bank of memory that is connected to the low byte. Thus accesses to a 16-bit
wide memory can be to the low byte only (AO = 0, SHE = 1), to the high byte only
(AO = 1, SHE = 0) or both bytes (AO = 0, SHE = 0). If the WRH function is selected,
the pin will go low if the bus cycle is writing to an odd memory location. SHE/WRH is
only valid during 16-bit external memory write cycles. Also an LSIO pin when not
SHE/WRH.
P5.6/READY
Ready input to lengthen external memory cycles, for interfacing with slow or
dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a
normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory
controller goes into a wait state mode until the next positive transition in CLKOUT
occurs with READY high. When external memory is not used, READY has no effect.
The max number of wait states inserted into the bus cycle is controlled by the CCR/
CCR1. Also an LSIO pin when READY is not selected.
P5.4/SLPINT
Dual function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin.
P6.2/T1CLK
Dual function I/O pin. Primary function is that of a bidirectional /10 pin, however, it
may also be used as a TIMER1 Clock input. The TIMER1 will increment or
decrement on both positive and negative edges of this pin.
P6.3/T1DIR
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it
may also be used as a TIMER1 Direction input. The TIMER1 will increment when
this pin is high and decrements when this pin is low.
PORT1/EPAO-7
P6.0-6.1/EPA8-9
Dual function I/O port pins. Primary function is that of bidirectional I/O. System
function is that of High Speed capture and compare. EPAO and EPA2 have yet
another function of T2CLK and T2DIR of the TIMER2 timer/counter.
PORT 0/ ACHO-7
8-bit high impedance input-only port. These pins can be used as digital inputs and/or
as analog inputs to the on-chip AID converter. These pins are also used as inputs to
EPROM parts to select the Programming Mode.
P6.3-6. 7 /SSIO
Dual function I/O ports that have a system function as Synchronous Serial I/O. Two
pins are clocks and two pins are data, providing full duplex capability.
PORT 2
8-bit multi-functional port. All of its pins are shared with other functions.
PORT 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
20-38
intel~
8XC196KT
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Storage Temperature .......... - 60 DC to + 150DC
Voltage from Vpp or EA to
Vss or ANGND .............. -0.5V to + 13.0V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage from Any Other Pin
to Vss or ANGND .............. -0.5 to +7.0V
This includes Vpp on ROM and CPU devices.
Power Dissipation .......................... 0.5W
OPERATING CONDITIONS
Symbol
TA
Parameter
Min
Max
Units
Ambient Temperature Under Bias
0
+70
DC
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
Fose
Oscillator Frequency
4
16
MHz (Note 4)
NOTE:
ANGND and Vss should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
(Under Listed Operating Conditions)
Max
Units
Icc
Vee Supply Current
Parameter
90
mA
IREF
AID Reference Supply Current
5
mA
IIDlE
Idle Mode Current
40
mA
75
= 5.5V
p.A Vee = Vpp = VREF = 5.5V(6.11)
IpD
Powerdown Mode Current
Vil
Input Low Voltage (all pins)
Typ
Min
50
-0.5V
0.3 Vee
Test Conditions
XTAL 1 = 16 MHz,
Vee = Vpp = VREF = 5.5V
(While device in Reset)
XTAL1 = 16MHz,
Vee = Vpp = VREF
V
For PORTO(10)
VIH
Input High Voltage
0.7 Vee
Vee + 0.5
V
For PORTO(10)
VIHl
Input High Voltage XTAL 1
0.7 Vee
Vee + 0.5
V
XTAL 1 Input Pin Only(l)
Vee + 0.5
V
RESET input pin only
0.3
0.45
1.5
V
V
V
IOl
IOL
IOl
VIH2
Input High Voltage on RESET
Val
Output Low Voltage
(Outputs Configured as
Complementary)
VOH
Output High Voltage
(Outputs Configured as
Complementary)
0.7 Vee
V
V
V
Vee - 0.3
Vee - 0.7
Vee - 1.5
= 200 p.A(3.5)
= 3.2mA
= 7.0mA
IOH = -200p.A(3.5)
IOH = -3.2 mA
IOH = -7.0mA
lu
Input Leakage Current (Std. Inputs)
±10
p.A
Vss
< VIN < Vee
IUl
Input Leakage Current (Port 0)
±3
p.A
Vss
III
Logical 0 Input Current
-70
p.A
VIN
< VIN < VREF
= 0.45V(1)
20-39
•
intel~
8XC196KT
DC CHARACTERISTICS
Symbol
(Under Listed Operating Conditions) (Continued)
Parameter
Min
VOH1
SLPINT (P5.4) and HLDA (P2.6)
Output High Voltage in RESET
2.0
VOH2
Output High Voltage in RESET
Vcc- 1V
Cs
Pin Capacitance (Any pin to Vss)
Rwpu
Weak Pullup Resistance
Typ
Max
Units
V
10
150K
Test Conditions
IOH
=
0.8 mA(7)
V
IOH
=
-6 p.A(1)
pF
ftest
=
1.0 MHz(6)
.n
(Note 6)
NOTES:
1. All SD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly
pulled high in resel. SD pins include Portl, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6).
2. Standard input pins include XTAL 1, EA, RESET, and Port 1/2/5/6 when setup as inputs.
3. All bidirectional I/O pins when configured as Outputs (Push/Pull).
4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz.
5. Maximum IOLIIOH currents per pin will be characterized and published at a later date.
6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
VREF = Vee = 5.0V.
7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).
8. When PO is used as analog inputs, refer to AID specifications for this characteristic.
9. For temperatures < 100'C typical is 10 p.A.
8XC196KT ADDITIONAL BUS TIMING MODES
The 8XC196KT devices have 3 additional bus timing modes for external memory interfacing.
MODE 3:
Mode 3 is the standard timing mode..
MODE 0:
Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus cycles.
MODE 1:
Mode 1 is the long R/W mode. This mode advances RD and WR signals by 1 T OSC creating a 2 T OSC RD/WR
low time. ALE is also advanced by 0.5 T OSC but ALE high time remains 1 T osc.
MODE 2:
Mode 2 is the long R/W mode with Early Address. Mode 2 is similar to Mode 1 with respect to RD, WR, and
ALE signals. Additionally, the address is output on the bus 0.5 T OSC earlier in the bus cycle.
20-40
intel~
8XC196KT
XTAL
CLKOUT
ALE
MODE (3) _ _ _ _-I
ALE
MODE(1,2) ___ _
--------~~---~---~,~~
AD
MODE (3) ________ .. I'----+---.J,~W
AD --------~J,-----,I~-~
MODE(l) ______ _
•
AD - - - - - MODE (2)
RD 8c WR
MODE (3)
RD 8c WR
MODE (1,2)
•
-----+----1----4
-----+------.1
Data Drive
272266-4
Detailed MODE 1,2,3, Comparison
20-41
int:el.,
8XC196KT
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T"
for time. The characters in a pair indicate a signal
and its condition, respectively. Symbols represent
the time between the two signal/condition points.
Conditions:
H-High
L-Low
V-Valid
X-No Longer
Valid
Z-Floating
Signals:
A-Address . HA-HLDA
L-ALE/ADV
B-BHE
BR-BREQ
Q-DataOut
C-CLKOUT RD-RD
D-DATA
W-WR/WRH/WRI
G-Buswidth X-XTAL1
H-HOLD
Y-READY
BUS MODE 0 AND 3 AC CHARACTERISTICS
Test Conditions: Capacitance Load on All Pins
=
(Over Specified Operating Conditions)
100 pF, Rise and Fall Times = 10 ns.
The system must meet these specifications to work with the 8XC196KT.
Symbol
Parameter
TAVYV
Address Valid to Ready Setup
hLYV
ALE Low to READY Setup
Min
TYLYH
Non READY Time
TeLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
Max
Units
2 Tose - 75
ns(3)
Tose - 70
ns(3)
No Upper Limit
0
ns
Tose - 30
ns(1)
2 Tose - 75
(1s(2,3)
Tose - 60
ns(2,3)
3 Tose - 55
ns(2)
TeLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
0
TRLDV
RD active to input Data Valid
Tose -,. 30
ns(2)
TeLDV
CLKOUT Low to Input Data Valid
Tose - 60
ns
TRHDZ
End of RD to Input Data Float
Tose
ns
TRHDX
Data Hold after RD High
0
ns
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tosc x n, where n = number of wait states.
3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the
specification.
'
20-42
intel"
8XC196KT
BUS MODE 0 AND 3 AC CHARACTERISTICS
(Continued)
Test Conditions: Capacitance Lqad on All Pins
=
(Over Specified Operating Conditions)
100 pF, Rise and Fall Times
=
10 ns.
The BXC196KT will meet these specifications
Symbol
Min
Max
Units
FXTAL
Frequency on XT AL 1
Parameter
4.0
16.0
MHz(1)
.250
ns
40
j.Ls
Tosc - 10
Tosc + 30
ns
+15
ns
Tosc
XTAL 1 Period (1/FXTALl
62.5
TXHCH
XTAL 1 High to CLKOUT High or Low
+20
TOFD
Clock Failure to Reset Pulled Low(6)
4
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Low to ALE/ ADV High
-20
-20
ns
ns
2 Tosc
TLLCH
ALE/ ADV Low to CLKOUT High
TLHLH
ALE/ ADV Cycle Time
hHLL
ALE/ ADV High Time
Tosc - 10
TAVLL
Address Valid to ALE Low
Tosc - 25
ns
TLLAX
Address Hold After ALE/ ADV Low
Tosc - 40
ns
TLLRL
ALE/ ADV Low to RD Low
Tosc - 30
TRLCL
RD Low to CLKOUT Low
+4
TRLRH
RD Low Period
TRHLH
RD High to ALE/ ADV High
TRLAZ
RD Low to Address Float
TLLWL
ALE/ ADV Low to WR Low
+15
Tosc + 10
-20
TCLWL
CLKOUT Low to WR Low
Data Valid before WR High
Tosc - 23
TCHWH
CLKOUT High to WR High
-10
ns
ns(5)
Tosc + 25
ns(3)
+5
ns
ns
Tosc - 10
TQVWH
ns
ns
+40
Tosc - 5
Tosc
ns
ns(5)
4 Tosc
+25
ns
ns
+15
ns
ns(5)
TWLWH
WR Low Period
Tosc - 30
TWHQX
Data Hold after WR High
Tosc - 25
ns
TWHLH
WR High to ALE/ ADV High
Tosc - 10
ns(3)
TWHBX
SHE, INST Hold after WR High
Tosc - 15
ns
TWHAX
ADB-15 Hold after WR High
Tosc - 30
ns(4)
TRHBX
SHE, INST Hold after RD High
Tosc - 10
ns
Tosc - 30
ns(4)
TRHAX
ADB-15 Hold after RD High
Tosc + 15
NOTES:
1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 Tosc x n, where n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 Tose to specification.
6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H. KT customer QROM codes need to equate location 2016H
to the value OCDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H as a flag
to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit enables oscillator fail
detection.
20-43
•
8XC196KT
BUS MODE 0 AND 3 8XC196KT SYSTEM BUS TIMING
XTAL1
CLOCKOUT
ALE/ADV
RD
BUS READ
ADDRESS OUT
1-----+--
TAVDV
TLLWL
--t--
WR
BUS WRITE
ADDRESS OUT
1-----+- TWHBX or TRHBX
BHE, INST
BHE. INST VALID
I----_~- TWHAX
ADS - AD15
or TRHAX
ADDRESS OUT AD8-AD15 VALID 8-BIT BUS t.lODE
272266-5
• If mode 0 operation is selected. add 2 T OSC to this time ..
20-44
intel .
8XC196KT
MODE 0 AND 3 8XC196KT READY TIMINGS (ONE WAIT STATE)
XTALl
CLKOUT
ALE
READY
TRLRH + 2 Tose
RD
r--
'I
( DATA IN })})})»>C
~::====~A~DD~R~ES~S~OU~T::====~------------------~C::!~~==~~~~
>
TAVDV + 2 lose
BUS READ
WR
~.
I
TWLWH + 2 Tose
TQVWH + 2 Tose
'I
BUS WRITE ::::X:::::::A:DD:R:ES:S:OU:T:::::::>«~~
~
DATA OUT
TRHOX
C
272266-6
"If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 Tosc to these specifications.
8XC196KT BUSWIDTH TIMINGS
XTALl
CLKOUT
ALE
~
~"~'-1 t:,~
\
I
J
'-
X X
BUSWIDTH
:::x
TAVGV·---l
ADDRESS OUT
>«~~
DATA OUT
'-~
VALID
I---
BUS WRITE
/
X
ADDRESS Our
x:::
272266-7
'If mode 0 selected, add 2 Tasc to these specifications.
20-45
II
infel·
8XC196KT
BUS MODE 1-AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 hs.
The system must meet these specifications to work with the 8XC196KT.
Symbol
Parameter
TAVYV
Address Valid to Ready Setup
TLL'r'V
ALE Low to READY Setup
TYLYH
Non READY Time
Min
Max·
Units
2 Tosc - 75
ns
1.5 Tosc - 70
No Upper Limit
0
ns
ns
Tosc - 30
ns(l)
2 Tosc - 75
nd
Tl.50SC - 60
ns
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
3 Tosc - 60
ns(2)
TRLDV
RD Active to input Data Valid
Tosc - 44
ns(2)
TCLDV
CLKOUT Low to Input Data Valid
Tosc - 60
ns
TRHDZ
End of RD to Input Data Float
Tosc
ns
TRHDX
Data Hold after RD High
ns
0
0
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tosc X n, where n = number of wait states. If mode 0 is selected, one wait state minimum
is always added. If additional wait states are required, add 2 Tosc to the specification.
20-46
intet
8XC196KT
BUS MODE 1-AC CHARACTERISTICS (Over Specified Operating Conditions)
= 100 pF, Rise and Fall Times = 10 ns.
Test Conditions: Capacitance Load on All Pins
The 8XC196KT will meet these specifications
Symbol
Parameter
Min
Max
Units
4.0
16.0
MHz(1)
250
ns
FXTAL
Frequency on XTAL 1
Tosc
XTAL 1 Period (1/FXTAU
62.5
TXHCH
XTAL 1 High to CLKOUT High or Low
+20
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
ns
ns
2 Tosc
Tosc - 10
Tosc + 27
ns
TCLLL
CLKOUT Low to ALE/ ADV Low
TLHLH
ALE/ ADV Cycle Time
TLHLL
ALE/ ADV High Time
Tosc - 10
TAVLL
Address Valid to ALE Low
Tosc - 20
ns
TLLAX
Address Hold After ALE/ ADV Low
Tosc - 40
ns
TLLRL
ALE/ ADV Low to RD Low
0.5 Tosc.- 10
ns
TRLCL
RD Low to CLKOUT Low
Tosc - 10
TRLRH
RD Low Period
2Tosc - 20
TRHLH
RD High to ALE/ ADV High
0.5 Tosc - 25
0.5 Tosc+ 15
0.5 Tosc
ns
ns(5)
4 Tosc
Tosc + 10
Tosc +30
ns
ns
ns(5)
0.5 Tosc + 25
ns(3)
+5
ns
TRLAZ
RD Low to Address Float
TLLWL
ALE/ ADV Low to WR Low
0.5 Tosc - 10
TCLWL
CLKOUT Low toWR Low
Tosc - 25
TOVWH
Data Valid before WR High
2 Tosc - 23
TCHWH
CLKOUT High to WR High
-10
TWLWH
WR Low Period
TWHOX
Data Hold after WR High
0.5 Tosc - 25
ns
TWHLH
WR High to ALE/ ADV High
0.5 Tosc - 10
ns(3)
TWHBX
SHE Hold after WR High
Tosc - 15
TWHIX
INST Hold after WR High
0.5 Tosc - 15
TWHAX
AD8-15 Hold after WR High
0.5 Tosc -.30
ns(4)
TRHBX
SHE Hold after RD High
Tosc - 32
ns
TRHIX
INST Hold after RD High
0.5 Tosc -' 32
TRHAX
AD8-15 Hold after RD High
0.5 Tosc - 30
ns
Tosc + 25
ns
ns
+15
ns
ns(5)
2 Tosc - 20
0.5 Tosc + 10
ns
ns(4)
NOTES:
1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 T esc x n, where n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 Tesc to specification.
20-47
II
8XC196KT
MODE 1-8XC196KT SYSTEM BUS TIMING
XTAL1
CLOCKOUT
'--~-TCLLL
TCHLH
ALE/ADV
I- TAVLL.-I-=~
----n"ft
BUS READ
ADDRESS OUT
TLLWL
1+----\4-----
BUS WRITE
,..-----'"\
ADDRESS OUT
TWLWH - - - - + I
'""'____- - - TQVWH
----1_-1_
TWHQX
DATA OUT
BHE VALID
AD8 - AD15
AD8 -AD15 VALID 8-BIT BUS MODE
1--1_ TWHIX'
INST
TRHIX
:::JK:::::::::::::::::IN:ST:V:A:LlD:::::::::::::::~::~X~___
272288-8
20-48
int'eL
8X.C196KT
MODE 1-8XC196KT READY TIMINGS (ONE WAIT STATE)
XTALl
CLKOUT
ALE _ _oJ
READY
T""VYV
~-:============_TRL_RH_+_2_T_OS_C_-_-~_-_-~~_-_-~_--=?1----
RD
TAVDV + 2 lose
mm~mx
BUS READ
)
ADDRESS OUT
(
»»»»»
DATA IN
~.============_T_WL_W_H+_2_T_OS_C_-_-_-_-_-_-_-_-_-.....
~~!-___
WR
H
BUS WRITE
------+l~
I
1
~. - - - - - - TQVWH + 2 TOSC
_ _ _ _ _ _ _D_A_TA_O_UT_ _ _ _ _ _ _ _
oJ}__
X«(
~~
ADDRESS OUT
272266-9
MODE 1-8XC196KT BUSWIDTH TIMINGS
XTAL1
CLKOUT
ALE
J
\
I
\I
/
TLLGV---j
BUSWIDTH
I-
BUS WRITE
>-<
TAVGV
ADDRESS OUT
)«~~
L,o~
~
.1
DATA OUT
20-49
I
I
\
/
\
x:
>-<
ADDRESS OUT
)«~~
272266-10
II
8XC196KT
BUS MODE 2-AC CHARACTERISTICS (Over Specified Operating Conditions)
= 100 pF, Rise and, Fall'Times = 10 ns.
Test Conditions: Capacitance Load on All Pins
The system must meet these specifications to work with the 8XC196KT.
Symbol
Min
Parameter
TAVYV
Address Valid to Ready Setup
TLLYV
ALE Low to READY Setup
TYLYH
Non READY Time
Max
Units
2.5 Tasc - 75
ns
1.5 Tasc- 70
ns
No Upper Limit
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
RD Active to Input Data Valid
TCLDV
CLKOUT Low to Input Data Valid
TRHDZ
End of RD to Input Data Float
TRHDX
Data Hold after RD High
0
Tasc - 30
2.5 Tasc - 75
ns
T1.5 asc - 60
ns
3.5 Tasc - 55
ns(2)
2 Tasc - 44
ns(2)
Tasc - 60
ns
0.5 Tasc
ns
ns
0
0
ns
ns(1)
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tosc x n, where n = number of wait states. If mode 0 is selected, one wait state minimum
is always added. If additional wait states are required, add 2 Tosc to the specification.
20·50
8XC196KT
BUS MODE 2-AC CHARACTERISTICS (Over Specified Operating Conditions)
= 100 pF, Rise and Fall Times = 10 ns.
Test Conditions: Capacitance Load on All Pins
The BXC196KT will meet these specifications
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL 1
B.O
16.0
MHz(1)
Tosc
XTAL 1 Period (1/FxTALl
62.5
125
ns
+20
+B5
ns
TXHCH
XT AL 1 High to CLKOUT High or Low
TCLCL
CLKOUT Period
TCHCL
CLKOUT High Period
TCLLL
CLKOUT Low to ALE/ ADV Low
TLHLH
ALE/ ADV Cycle Time
TLHLL
ALE/ ADV High Time
TOSC - 10
TAVLL
Address Valid to ALE Low
Tosc - 15
ns
TLLAX
Address Hold After ALE/ ADV Low
Tosc - 40
ns
TLLRL
ALE/ ADV Low to RD Low
0.5 Tosc - 10
ns
TRLCL
RD Low to CLKOUT Low
Tosc - 10
TRLRH
RD Low Period
2Tosc - 20
TRHLH
RD High to ALE/ ADV High
0.5 Tosc-5
TRLAZ
RD Low to Address Float
TLLWL
ALE/ ADV Low to WR Low
0.5 Tosc - 10
TCLWL
CLKOUT Low to WR Low
Tosc - 22
Tosc - 10
Tosc + 27
ns
0.5 Tosc-25
0.5 Tosc+ 15
ns
Data Valid before WR High
2 Tosc - 25
TCHWH
CLKOUT High to WR High
-10
WR Low Period
TWHOX
Data Hold after WR High
ns(5)
4 Tosc
TOVWH
TWLWH
ns
2 Tosc
Tosc + 10
Tosc +30
ns
ns
ns(5)
0.5 Tosc + 25
ns(3)
+5
ns
ns
Tosc + 25
ns
ns
+15
ns
ns(5)
2 Tosc - 20
0.5 Tosc - 25
ns
0.5 Tosc - 10
ns(3)
TWHLH
WR High to ALE/ ADV High
TWHBX
BHE Hold after WR High
Tosc - 15
TWHIX
INST Hold after WR High
0.5 Tosc - 15
TWHAX
ADB-15 Hold after WR High
0.5 Tosc - 30
ns(4)
TRHBX
BHE Hold after RD High
Tosc - 32
ns
TRHIX
INST Hold after RD High
0.5 Tosc - 32
TRHAX
ADB-15 Hold after RD High
0.5 Tosc - 30
0.5 Tosc + 10
ns
ns(4)
NOTES:
1. Testing performed at B.O MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. a-bit bus only.
5. If wait states are used, add 2 Tose x n, where n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 Tose to specification.
20-51
inteL
8XC196KT
MODE 2-8XC196KT SYSTEM BUS TIMING
XTAL1
CLOCKOUT
ALE/ADV
BUS READ
TLLWL
1-.=;.-=-+----- TWLWH
BUS WRITE
BHE
----I
ADDRESS OUT
BHE VALID
f--l-
AD8 - AD15
TWHAX ' TRHAX
r-----------------------------~--~
AD8 -AD15 VALID 8-BIT BUS MODE
1---+1_ TWH1X ' TRH1X
INST
===:J(=================I=NS=T=V=AL=ID===============~===~)(~____
_
272266-11
\
20-52
intel~
8XC196KT
MODE 2-8XC196KT READY TIMINGS (ONE WAIT STATE)
XTAL1
CLKOUT
ALE
READY
TAVYV
~
RD
mx
BUS READ
ADDRESS OUT
~
I
X
(
)
WR
BUS WRITE
-I
T,WDV + 2 Tose
ADDRESS OUT
DATA IN
TOVWH + 2 Tose
xm
»>X
~
TWLWH + 2 Tose
I
II
I
TRLRH + 2 Tose
»>X
DATA OUT
272266-12
MODE 2-8XC196KT BUSWIDTH TIMINGS
XTAL1
CLKOUT
ALE
J
I
\
I
\
I.
TLLGV
"'----j
\
I
/
\
x=
~
BUSWIDTH
I'
BUS WRITE
t,~
/
X
TAVGV
ADDRESS OUT
XS~~
·1
DATA OUT
~~>X
272266-13
20-53
intel"
8XC196KT
BUS MODE 0, 1, 2, and 3 HOLD/HOLDA TIMINGS (Over Specified Operation Conditions)
Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns.
Symbol
Min
Parameter
Max
Units
ns(l)
THVCH
HOLD Setup Time
+65
TCLHAL
CLKOUT Low to HLDA Low
-15
+15
ns
TCLBRL
CLKOUT Low to SREQ Low
-15
+15
ns
TAZHAL
HLDA Low to Address Float
+25
ns
TBZHAL
HLDA Low to SHE, INST, RD, WR Weakly Driven
+25
ns
TCLHAH
CLKOUT Low to HLDA High
-25
+15
ns
TCLBRH
CLKOUT Low to SREQ High
-25
+25
ns
THAHAX
HLDA High to Address No Longer Float
-15
ns
THAHBV
HLDA High to SHE, INST, RD, WR Valid
-10
ns
NOTE:
1. To guarantee recognition at next clock.
8XC196KT HOLD/HOLDA TIMINGS
BUS
L,i-----tt<====:x::
=:x--------------:-r=---~---
i:j:r------I'"'\______
---------';..-;! '
HALBZ
BHE,INST,
RD, WR
ALE
--------":',--I! ,
....::'~.i..'_
,
,
~r-j---~!llr_------J
272266-14
20-54
intel .
8XC196KT
AC CHARACTERISTICS-SLAVE PORT
SLAVE PORT WAVEFORM-(SLPL
\~
=
0)
________________________-J/
HTSRHAV
ALE/A 1
)
TSRLRH
TSRLDV
TSRHDZ
P3
TSDVWH
TSAVWL
TSWHQX
TSWLWH
"
272266-15
SLAVE PORT TIMING-(SLPL = 0,1,2,3)
Symbol
Min
Parameter
Max
Units
TSAVWL
Address Valid to WR Low
50
ns
TSRHAV
RD High to Address Valid
60
ns
TSRLRH
RD Low Period
Tosc
ns
TSWLWH
WR Low Period
Tosc
ns
60
ns
TSRLDV
RD Low to Output Data Valid
TSDVWH
Input Data Setup to WR High
20
ns
TSWHQX
WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
NOTES:
1. Test Conditions: Fose = 16 MHz, Tose = 60 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
20-55
•
8XC196KT
AC CHARACTERISTICS-SLAVE PORT (Continued)
SLAVE PORT WAVEFORM-(SLPL = 1)
TSELLL
TSRHEH
.1
J
\.
/
ALE
TSLLRL
TSRLRH
TSRLDV
TSRHDZ
P3
I
TSAVLL
TSLLAX
I
TSDVWH
TSWHQX
TSWLWH
,I
~
272266-16
SLAVE PORT TIMING-(SLPL = 1, 2, 3)
Symbol
Parameter
Min
CS Low to ALE Low
20
ns
TSRHEH
RD or WR High to CS High
60
ns
TSLLRL
ALE Low to RD Low
ToSC
ns
TSRLRH
RD Low Period
Tosc
ns
TSWLWH
WR Low Period
Tosc
ns
TSAVLL
Address Valid to ALE Low
20
ns
TSLLAX
ALE Low to Address Invalid
20
ns
TSRLDV
AD Low to Output Data Valid
TSDVWH
Input Data Setup to WRHigh
TSELLL
Max
Units
60
ns
20
ns
TSWHQX
'. WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
NOTES:
1. Test Conditions: Fosc = 16 MHz, Tosc = 60 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
20-56
int'et
8)(C196KT
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
4
16
MHz
62.5
250
ns
1/TxLXL
Oscillator Frequency
TXLXL
Oscillator Period (Tosc)
TXHXX
High Time
0.35 x Tosc
0.65 Tosc
ns
TXLXX
Low Time
0.35 x Tosc
0.65 Tosc
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
II
272266-17
AC TESTING INPUT, OUTPUT WAVEFORMS
INPUTS
OUTPUTS
3 . S V J"< E .
I
O.4SV
FLOAT WAVEFORMS
2.0V
)
TIMING REFERENCE
POINTS
<
TEST POINTS'
O.8V
272266-19
For timing purposes a Port Pin is no longer floating
when a 150 mV change from load voltage occurs and
begins to float when a 150 mV change from the loading
VOHIVOL level occurs IOL/IOH ,; 15 mAo
272266-18
AC Testing inputs are driven at 3.5V for a logic "1" and
0.45V for a logic "0". Timing measurements are made
at 2.0V for a logic "1" and 0.8V for logic "0".
20-57
8XC196KT
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-5HIFT REGISTER MODE
RESET
~TSHll
<.
ORTS
3/4
.1
ADDRESS/COMMAND
I
"
-'
~
TplDV -
\
PAl~
1'2.1
ADDR
--
TpHDX
T1lPl
'(VER BITS/WD DUMP) ~
-
\
PROG
P2.2
ADDR + 2
I
(.VER BITS/WD DUMP
rc-
/
\
I--
TpHDX
r+TPlDV -
TpHPl -
\
AINC
1'2.04-
272266-22
AC CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFTING REGISTER MODE
Test Conditions: TA = -40°C to + 125°C; Vee = 5.0V ± 10%; VSS = O.OV; Load Capacitance
Symbol
TXLXL
Parameter
Min
Serial Port Clock Period
Max
Serial Port Clock Falling Edge to Rising Edge
TOVXH
Output Data Setup to clock Rising Edge
TXHOX
Output Data Hold after Clock Rising Edge
TXHQV
Next Output Data Valid after Clock Rising Edge
TOVXH
Input Data Setup to Clock Rising Edge
TXHDX(1)
Input Data Hold after Clock Rising Edge
TXHOZ(1)
Last Clock Rising to Output Float
4Tose-5O
Tose
+ 50
ns
2 Tose - 50
2 Tose
+ 50
+ 200
20-58
ns
ns
0
ns
5 Tose
NOTE:
1. Parameters not tested.
ns
ns
3 Tose
2 Tose
Units
ns
8 Tose
TXLXH
= pF
ns
intet
8XC196KT
A TO D CHARACTERISTICS
The AID converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF.
10-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
·C
TA
Ambient Temperature
0
+70
Vee
Digital Supply Voltage
4.50
5.50
V
5.50
V(l)
VREF
Analog Supply Voltage
4.50
TSAM
Sample Time
1.0
TeONv
Conversion Time
10
15
,..,s(2)
Fose
Oscillator Frequency
4.0
16.0
MHz
,..,s(2)
NOTES:
1. VREF must be within 0.5V of Vcc.
2. The value of AD_TIME is selected to meet these specifications.
10-BIT MODE AID CHARACTERISTICS (Using Above Operating Conditions)(6)
Parameter
Typ*(1)
Resolution
Absolute Error
Full Scale Error
0.25 ±0.5
Zero Offset Error
0.25 ±0.5
Non-Linearity
Min
Max
Units'
1024
10
1024
10
Level
Bits
0
±3.0
LSBs
LSBs
LSBs
1.0 ±2.0
±3.0
LSBs
-0.75
+0.75
LSBs
±0.1
0
±1.0
LSBs
Repeatability
±0.25
0
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
Differential Non-Linearity
Channel-to-Channel Matching
LSBs(1)
LSB/C(1)
LSB/C(1)
LSB/C(l)
dB(1,2,3)
-'-60
Off Isolation
Feedthrough
-60
dB(1,2)
Vce Power Supply Rejection
-60
dB(1,2)
Input Resistance
DC Input Leakage
±1.0
Voltage on Analog Input Pin
750
1.2K
0.(4)
0
±3.0
ANGND - 0.5
VREF + 0.5
,..,A
V(5)
Sampling Capacitor
3.0
• An "LSB" as used here has a value of approxImately 20 mV.
NOTES:
1. These values are expected for most parts at 25"e, but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer break-before-make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted:
6. All conversions performed with processor in IDLE mode.
20-59
pF
intel·
8XC196KT
a-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature
0
+70
'C
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
TSAM
Sample Time
TeONV
Conversion Time
Fose
Oscillator Frequency
V(l)
jJ.s(2)
1.0
7
20
jJ.s(2)
4.0
16.0
MHz
NOTES:
1. VREF must be within O.SV of Vee.
2. The value of AD_TIME is selected to meet these specifications.
a-BIT MODE AID CHARACTERISTICS
Parameter
(Using Above Operating Conditions)(6)
Typ*(l)
Resolution
Absolute Error
Full Scale Error
±0.5
Zero Offset Error
±0.5
Differential Non-Linearity
±0.25
0.003
0.003
0.003
Units'
256
8
256
8
Level
Bits
0
±1.0
LSBs
LSBs
Channel-to-Channel Matching
Repeatability
Max
LSBs
Non-Linearity
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
Min
0
±1.0
LSBs
-0.5
+0.5
LSBs
0
±1.0
LSBs
LSBs(l)
0
LSB/C(l)
LSB/C(l)
LSB/C(l)
dB(l,2,3)
-60
Off Isolation
Feedthrough
-60
dB(l,2)
Vee Power Supply Rejection
-60
dB(l,2)
750
Input Resistance
DC Input Leakage
±1.0
Voltage on Analog Input Pin
Sampling Capacitor
1.2K
0(4)
0
±3.0
jJ.A
ANGND - 0.5
VREF + 0.5
VIS)
3.0
pF
'An ULSS n as used here has a value of approximately 20 mY.
NOTES:
1. These values are expected for most parts at 2S'e, but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer break-before-make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.
6. All conversions performed with processor in IDLE mode.
20-60
8XC196KT
EPROM SPECIFICATIONS
OPERATING CONDITIONS
Symbol
Min
Max
Units
TA
Ambient Temperature during Programming
Description
20
Vee
Supply Voltage during Programming
V(1)
VREF
Reference Supply Voltage during Programming
4.5
4.5
30
5.5
5.5
V(1)
Vpp
Programming Voltage
12.25
V(2)
VEA
EA Pin Voltage
12.25
12.75
12.75
Fose
Oscillator Frequency during Auto
and Slave Mode Programming
6.0
B.O
MHz
Fose
Oscillator Frequency during
Run-Time Programming
6.0
16.0
MHz
°C
V(2)
NOTES:
1.
2.
3.
4.
Vee and VREF should nominally be at the same voltage during programming.
Vpp and VEA must never exceed the maximum specification, or the device may be damaged.
Vss and ANGND should nominally be at the same potential (OV).
Load capacitance during Auto and Slave Mode programming = 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)
Symbol
Min
Parameter
Max
Units
TAVLL
Address Setup Time
0
Tosc
TLLAX
Address Hold Time
Data Setup Time
100
0
TOSC
TDVPL
TpLDX
Data Hold Time
400
Tosc
TLLLH
PALE Pulse Width
50
Tosc
TpLPH
PROG Pulse Width(2)
Tose
TLHPL
PALE High to PROG Low
50
220
TpHLL
PROG High to next PALE Low
220
TpHDX
Word Dump Hold Time
TpHPL
PROG High to next PROG Low
220
TLHPL
PALE High to PROG Low
220
TpLDV
PROG Low to Word Dump Valid
TSHLL
RESET High to First PALE Low
1100
ToSC
TpHIL
PROG High to AINC Low
Tose
TILIH
AINC Pulse Width
TILVH
PVER Hold after AINC Low
0
240
50
TILPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Valid
Tosc
Tose
Tosc
50
Tosc
TOSC
Tose
50
TOSC
Tose
Tosc
Tose
220
Tose
NOTES:
1. Run-time programming is done with Fosc = 6.0 MHz to 10.0 MHz, Vee, VPD, VREF = 5V ±0.5V, Te = 25°C ±5°C and
Vpp = 12.5V ±0.25V. For run-time programming over a full operating range, contact factory.
2. Programming specifications are not tested, but guaranteed by design.
3. This specification is for the word dump mode. For programming pulses use Modified Quick Pulse Algorithm.
20-61
..
intel"
8XC196KT
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Ipp
Vpp Programming Supply Current
Max
200
Units
mA
NOTE:
Don not apply Vpp until Vee is stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
---'
3/4
ADDRESS/COMMAND
[
-
_
TLLLH -
-
ADDRESS/COMMAND
_ TpLDX -
\
P2.1
I----<
DATA
. 1 TLLAX
_ TSHLL
PALE
I--
TDVPL
!--TAVLL-J
,J
PORTS
\
T
pLPH
TpHLL -
TLHPL --
PROG
I
P2.2
_TpHVL PVER
"
-
P2.0
TLLVH
VALID
/
272266-21
NOTE:
P3.0 must be HIGH ("1")
SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT
RESET
~
TSHLL
PORTS
3/4
'I
I
ADDRESS/COMMAND
TpLDV ---
PALE
P2.1
"
PROG
P2.2
T'LPL
AINC
P2.4
ADDR
I
VER BITS/WD DUMP
f--
--"
-
TpHDX
f--
ADDR + 2
VER BITS/WD DUMP
..f
I-
"
TpLDV --
TpHDX
~
~
V
TPHPL - -
\
272266-22
NOTE:
P3.0 must be LOW ("0")
20-62
8XC196KT
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
PORTS
3/4
PALE
-----« ADDRESS/CO~~AND )>-----«
--------------~\
P2.1
PROG
P2.2
PVER
P2.0
AINC
P2.4
DATA
)>---------«
DATA
)>----
I
'----'
-------------------------~
-------------------------~--------~~~~~--------
----------------------------------------------~~
272266-23
8XC196KT ERRATA
The following is a list of all known functional deviations for aXC196KT devices. C-step devices can be
identified by a special mark following the eight digit
FPO number on the top of the package. For C-step
devices, this mark is a "C".
1. The following reserved op-codes do not generate
the unimplemented op-code interrupt: 1Ch, 1Dh,
1Eh,1Fh,E3h,E4h,E6h,Eah,E9h,EAh,EBhand
F1h.
20-63
8XC 196MC Data Sheet
21
8XC196MC
INDUSTRIAL MOTOR CONTROL
MICROCONTROLLER
87C196MC 16 Kbytes of On-Chip OTPROM*
83C196MC 16 Kbytes of On-Chip ROM
Performance CHMOS 16-Bit CPU
• High
16 Kbytes of On-Chip OTPROM/ROM
• 488
bytes of On-Chip Register RAM
• Register
Architecture
• Up to 53 toI/ORegister
Lines
• Peripheral Transaction Server (PTS)
• with 11 Prioritized Sources
Processor Array (EPA).
• -Event
4 High Speed Capture/Compare
•
16-Bit Timers with Quadrature
• Two
Decoder Input
3-Phase Complementary Waveform
• Generator
13 Channel 8/10-Bit A/D with Sample/
• Hold
with Zero Offset Adjustment H/W
14 Prioritized Interrupt Sources
• Flexible 8/16-Bit External Bus
• 1.75,...s 16 x 16 Multiply
• 3 ,...s 32/16 Divide
• Idle
• and Power Down Modes
Modules
- 4 High Speed Compare Modules
Extended Temperature Standard
The 8XC196MC is a 16·bit microcontroller designed primarily to control 3 phase· AC induction and DC brushless motors. The 8XC196MC is based on Intel's MCS®-96 16-bit architecture and is manufactured with Intel's
CHMOS process.
The 8XC196MC has a three phase waveform generator specifically designed for use in "Inverter" motor
control applications. This peripheral allows for pulse width modulation, three phase sine wave generation with
minimal CPU intervention. It generates 3 complementary non-overlapping PWM pulses with resolutions of
0.125 ,.,.S (edge trigger) or 0.250 ,.,.S (centered).
The 8XC196MC has 16 Kbytes on-Chip OTPROM/ROM and 488 bytes of on-chip RAM. It is available in three
packages; PLCC (84-L), SDIP (64-L) and EIAJ/QFP (80-L).
Note that the 64-L SDIP package does not include P1.4, P2.7, P5.1 and the CLKOUT pins.
Operational characteristics are guaranteed over the temperature range of - 40·C to
+ 85·C.
The 87C196MC contains 16 Kbytes on-chip OTPROM. The 83C196MC contains 16 Kbytes on-chip ROM. All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted.
·OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package
and cannot be erased. It is user programmable.
21-1
September 1992
Order Number: 270948-004
8XC196MC
ANGND
NMI
---------------------.
16
CPU
16K ON-CHIP
ROM/OTPROM
(OPTIONAL)
PORT 5
CONTROL
SIGNALS
ADDR/
DATA
BUS
PORT"
EXTINT
A/D PORT 0/1
EPA
PORT 2
PORT 6
270946-1,
NOTE:
Connections between the standard 110 ports and the bus are not shown.
Figure 1. 87C196MC Block Diagram
21-2
int:eL
8XC196MC
PROCESS INFORMATION
8XC196MC Memory Map
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability information is available in Intel's Components Quality
and Reliability Handbook, Order Number 210997.
Description
x.q
!!
~
External Memory or I/O
x ~c
~
~D"i"S""'d'
L--.:
Address
OFFFFH
06000H
Internal ROM/EPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201CH
Reserved. Must Contain 20H
(Note 5)
201BH
CCB1
201AH
Reserved. Must Contain 20H
(Note 5)
2019H
CCBO
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Lower Interrupt Vectors
2013H
2000H
SFR's
1FFFH
1FOOH
External Memory
1EFFH
0200H
488 Bytes Register RAM (Note 1)
01FFH
0018H
CPU SFR's (Notes 1, 3)
0017H
OOOOH
No Nark= 16t.tHz
Me Product family
CHt.tOS Technology
ProgrQm Memory Options:
7 = EPROM (Note 1)
:5 ROM
=
' - - - - - - - - - - Package Type Options:
N = B4-lead Plee
5 = SO-lead OFP
U = 54-lead SOIP
' - - - - - - - - - - - Temperature and Burn-In Options:
No Mark = _.. ooC to +B50C Ambient with
Intel Standard BUrn-in
270946-16
EXAMPLE: N87C196MC is 84-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196MC Family Nomenclature
Thermal Characteristics
Package
Type
81a
81c
PLCC
35°C/W
13°C/W
QFP
56°C/W
12°C/W
SDIP
TBD
TBD
All thermal Impedance data IS approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel's thermal impedance test methodology.
NOTES:
1. Code executed in locations OOOOH to 03FFH will be
forced external.
2. Reserved memory locations must contain OFFH unless
noted.
3. Reserved SFR bit locations must contain O.
4. Refer to 8XC196KC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and! or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
21-3
intel"
8XC196MC
P5.6/READY
Vss
P5.4
P5.0/ALE
EXTINT
Vpp
P5.3!RD
VSS
XTAL 1
PS.5!BHE
XTAL2
P5.2!WR
P5.7/SUSW
P6.6/PWMO
• P4.6/AD14
P6.7/PWMI
• P4.5/AD13
P2.6/COMPARE2/CPVER
• P4.7/AD15
P2.5/COMPARE 1!PtiCr
Vee
P2.4/COMPAREO/liiNc'
P4.4/AD12
P2.3/CAPCOM3
P4.3/ADll
P2.2/CAPCOM2/PROG
P4.2/AD10
P4.1/AD09
P4.0/ADOB
INTEL
8XC196MC
P2. 1/CAPCOM l/PALE
P2.0/CAPCOMO/PVER
PO.O/ACHO
PO.l/ACHl
P3.7/AD07
P3.6/AD06
PO.2/ACH2
P3.5/AD05
PO.3/ACH3
P3.4/AD04
PO.4/ ACH4/PMODE.O
P3.3/AD03
PO.5/ ACH5/PMODE. 1
P3.2/AD02
VREF
P3.1/ADOI
AGND
P3.0/ADOO
PO.6/ACH6/PMODE.2
PO. 7 / ACH7 /PMODE.3
RESET
NMI
P1.0/ACHB
P1.1/ACH9
EA
Vss
P1.2/ACH10
Vee
P1.3/ACHll
P6.5/WG3
P6.0;WG1
P6.4!WG3
P6.1/WGI
P6.3/WG2
P6.2!WG2
270946-2
NOTE:
"The pin sequence is correct.
The 64-Lead SDIP package does not include the following pins: P1.4/ACH12,P2.7/COMPARE3, P5.1I1NST,
CLKOUT.
Figure 2. 64-Lead Shrink DIP (SDIP) Package
21-4
intel"
8XC196MC
...'">
D-
U
"...
N
;0,
~~
'" ;0,
"iii
....
D-
...J
N
0
iii u
D-
...
<
~~
on
"- ".
'"
iii iii
Z
D-
D-
....
en
Z
0:
>-
0
C
...<
"- '"
",": "
ID
iii
>VI ~ D>"-'"
D-
...iii
D-
....Z
;::
...
X
:;
N
...J
<
'" ~
< ....
>VJ
X
:::i
;0,
:::i
;0,
D-
D-
U
U
Z
U
Z
U
"..; "..;.... "N
ID
Z
<
D:::i
0
D-
ID
D-
D-
P4.7/AD15
P2.5/COMPAREI /PACT
P4.6/AD14
P2.4/COMPAREO!AiNC
NC
Vee
P4.5/AD13
71
NC
CLKOUT
P2. 7 /COMPARE3
P4.4/AD12
P2.3/CAPCOMP3
P4.3/ADll
P2.2/CAPCOMP2/PROG
INTEL
P4.2/AD10
P4.1/AD09
NC
NC
8XC196MC
P4.0/ADOB
P2.1/CAPCOt.lPl/PALE
NC
Top view looking down
NC
on component side
P3.7/AD07
P2.0/CAPCOt.lPO/PVER
NC
PO.O/ACHO
of PC board
P3.6/AD06
PO. l/ACH 1
P3.5/AD05
PO.2/ACH2
P3.4/AD04
PO.3/ACH3
P3.3/AD03
PO.4/ ACH4/Pt.lODE.O
P3.2/AD02
PO.5/ ACH5/Pt.lODE. 1
P3.1/ADO1
VREF
P3.0/ADOO
AGND
NC
PO.6/ ACH6/Pt.lODE.2
I~
:i ~ I~ en en <.J rt) Itt)
Z
::' >VI ~ ~ ~
.
c; Ie;
" >'""'~"
""
on ... "
""
..; ..; ..;
..; ..; '"
..;
N
;0,
;0,
D-
o.
-
;0,
0
:J:
u
:J:
u
< <
a. a. a. "! "!
N
a.
;0,
0
"0:: "
D-
'" N
"'_
'"::I:
:J: U
>
u
<
co
:J:
U
< <
'"
..;
C
0
:::i
"o."": " ""! "....a.
D-
D-
:J:
U
<
"ei....
D-
270946-3
NOTE:
NC means No Connect. Do not connect these pins.
Figure 3. 84-Lead PLCC Package
21-5
intel·
8XC196111lC
P5.2!WR
PS.7/PWlotl
P5.7/BU5W
P2.s/eOlotPARE2/CPVER
P4.7/ADI5
P2.5/COlotPAREI/PACT
P4.S/ADI4
SI
vee
P2.4/COlotPAREO,lAiNe
NC
NC
P4.S/ADI3
CLKOUT
P2. 7/COlotPARE3
P4.4/ADI2
P2.3/CAPCOIIP3
P~.2/CAPCOlotP2/PROG
P4.3/ADII
P4.2/ADIO
P4.I/AD09
P4.0/ADoa
P3.7/AD07
INTEL
8XC196t.1C
NC
54
NC
P2. I /CAPCOlotP I /PALE
Top view looking
P2.0/CAPCOlotPO/PVER
P3.S/ADOS
down on
P3.5/AD05
component side of
PO.O/ACHO
P3.4/AD04
PC board
PO.I/ACH!
51
NC
P3.3/AD03
PO.2/ACH2
P3.2/AD02
PO.3/ACH3
P3, !/ADO!
PO.4/ACH4/PlotODE.O
P3.0/ADDO
PO:S/ACH5/PlotODE.!
VREf
NC
RESET
AGND
Nlotl
PO.S/ACHS/PIIODE.2
EA
41
PO.7 /ACH7 /PIIODE.3
270946-4
NOTE:
NC meims No Connect. Do not connect these pins.
Figure 4. 80-Lead Shrink EIAJQFP (Quad Flat Pack)
21-6
inteL
PIN DESCRIPTIONS
8XC196MC
(Alphabetically Ordered)
Symbol
ACHO-ACH12
(PO.0-PO.7, P1.0"':P1.4)
ANGND
ALE/ ADV(P5.0)
BHE/WRH (P5.5)
Function
Analog inputs to the on·chip AID converter. ACHO-7 share the input pins
with PO.0-7 and ACH8-12 share pins with P1.0-4. If the A/D is not used,
the port pins can be used as standard input ports.
Reference ground for the A/D converter. Must be held at nominally the
same potential as Vss.
Address Latcn Enable or Address Valid output, as selected by CCA. Both
options allow a latch to demultiplex the address/data bus on the signal's
falling edge. When the pin is ADV, it goes inactive (high) at the end of the
bus cycle. ALE/ ADV is active only during external memory accesses. Can be
used as standard I/O when not used as ALE/ ADV.
Byte High Enable or Write High output, as selected by the CCR. BHE will go
low for external writes to the high byte of the data bus. WRH will go low for
external writes where an odd byte is being written. BHE/WRH is activated
only during external memory writes.
BUSWIDTH (P5.7)
Input for bus width selection. If CCR bits 1 and 2 = 1, this pin dynamically
controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an
8·bit cycle occurs. If it is high, a 16·bit cycle occurs. This pin can be used as
standard I/O when not used as BUSWIDTH.
CAPCOMPO-CAPCOMP3
(P2.0-P2.3)
The EPA Capture/Compare pins. These pins share P2.0-P2.3. If not used
for the EPA, they can be configured as standard I/O pins.
Output of the internal clock generator. The frequency is % of the oscillator
frequency. It has a 50% duty cycle.
The EPA Compare pins. These pins share P2.4-P2.7. If not used for the
EPA, they can be configured as standard I/O pins.
External Access enable pin. EA = 0 causes all memory accesses to be
external to the chip. EA = 1 causes memory accesses from location 2000H
to 5FFFH to be from the on·chip OTPROM/QROM. EA = 12.5V causes
execution to begin in the programming mode. EA is latched at reset.
CLKOUT
COMPAREO-COMPARE3
(P2.4-P2.7)
EA
EXTINT
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH. The input may be selected to be a
positive/negative edge or a high/low level using WG_PROTECT (1 FCEH).
INST (P5.1)
INST is high during the instruction fetch from the external memory and
throughout the bus cycle. It is low otherwise. This pin can be configured as
standard I/O if not used as INST.
A positive transition on this pin causes a non·maskable interrupt which
vectors to memory location 203EH. If not used, it should be tied to Vss. May
be used by Intel Evaluation boards.
8·bit high impedance input·only port. Also used as A/D converter inputs.
PortO pins should not be left floating. These pins also used to select
programming modes in the OTPROM devices.
NMI
PORTO
PORT1
PORT2
PORT3
PORT4
PORT5
5·bit high impedance input·only port. P1.0-P1.4 are also used as AID
converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock
input and direction select respectively.
8·bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O
pins (CAPCOMPO-3 and COMPAREO-3).
8·bit bidirectional I/O ports with open drain outputs. These pins are shared
with the multiplexed address/data bus which uses strong internal pull ups.
8·bit bidirectional I/O port. 7 of the pins are shared with bus control signals
(ALE, INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard
I/O.
21·7
infel"
8XC196MC
PIN DESCRIPTIONS
(Alphabetically Ordered) (Continued)
Symbol
Function
8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave
Form Generator outputs. Can be used as standard output ports.
PORT6
PWMO, PWM1
(P6.6, P6.7)
Programmable duty cycle, Programmable frequency Pulse Width Modulator
pins. The duty cycle has a resolution of 256 steps, and the frequency can vary
from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as
standard output if PWM is not used.
RD (P5.3)
Read signal output to external memory. RD is low only during external memory
reads. Can be used as standard 1/0 when not used as RD.
Ready input to lengthen external memory cycles. If READY = 0, the memory
controller inserts wait states until the next positive transition of CLKOUT
occurs with READY = 1. Can be used as standard 1/0 when not used as
READY.
Reset input to and open-drain output from the chip. Held low for at least 16
state times to reset the chip. Input high for normal operation. RESET has an
Ohmic internal pullup resistor.
READY (P5.6)
RESET
T1CLK
(P1.2)
Timer 0 Clock input. This pin has two other alternate functions: ACH1 0 and
P1.2.
Timer 0 Direction input. This pin has two other alternate functions: ACH11 and
P1.3.
The programming voltage is applied to this pin. It is also the timing pin for the
return from Power Down circuit. Connect this pin with a 1 p.F capacitor to Vss
and a 1 Mn resistor to Vee. If the Power Down feature is not used, connect
the pin to Vee.
3 phase output signals and their complements used in motor control
applications. The pins can also be configured as standard output pins.
Write and Write Low output to external memory. WR will go low every external
write. WRL will go low only for external writes to an even byte. Can be used as
standard 1/0 when not used as WR/WRL.
T1DIR
(P1.3)
Vpp
WG1-WG3/WG1-WG3
(P6.0-P6.5)
WR/WRL (P5.2)
XTAL1
Input of the oscillator inverter and the internal clock generator. This pin should·
be used when using an external clock source.
Output of the oscillator inverter.
XTAL2
PMODE
(PO.4-7)
Determines the EPROM programming mode.
PACT
(P2.5)
A low signal in Auto Programming mode indicates that programming is in
process. A high signal indicates programming is complete.
A falling edge in Slave Programming Mode and Auto Configuration Byte
Programming Mode indicates that ports 3 and 4 contain valid programming
addresslcommand information (input to slave).
PALE
(P2.1)
PROG
(P2.2)
A falling edge in Slave Programming Mode begins programming. A rising edge
ends programming.
PVER
(P2.0)
A high signal in Slave Programming Mode and Auto Configuration Byte
Programming Mode indicates the byte programmed correctly.
CPVER
(P2.6)
AINC
(P2.4)
I
Cumulative Program Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.
Auto Increment. Active low input enables the auto increment mode. Auto
increment will allow reading or writing of sequential EPROM locations without
address transactions across the PBUS for each read or write.
21-8
8XC196MC
ABSOLUTE MAXIMUM RATINGS
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature
Under Bias .................. - 40°C to + 85°C
Storage Temperature .......... - 65°C to + 150°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage from EA or Vpp
to Vss or ANGND .................... + 13.00V
Voltage on Vpp or EO
to Vss or ANGND .............. -0.5V to 13.0V
Voltage on Any Other Pin
to Vss or ANGND ......... " -0.5V to +7.0V(1)
Power Dissipation ....................... 1.5W(2)
NOTES:
1. This includes Vpp and EA on ROM or epu only devices.
2. Power dissipation is based on package heat transfer limitations, not device power consumption.
OPERATING CONDITIONS
Symbol
TA
Description
Min
Max
Units
Ambient Temperature Under Bias
-40
+85
°C
Vee
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.00
5.50
V
Fose
Oscillator Frequency
8
16
MHz
NOTE:
ANGND and Vss should be nominally at the same potential. Also Vss and VSS1 must be at the same potential.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
(Over Specified Operating Conditions)
Min
Max
Units
Test Conditions
VIL
Input Low Voltage
-0.5
0.3 Vee
V
VIH
Input High Voltage
0.7 Vee
Vee + 0.5
V
VOL
Output Low Voltage
Port 2 and 5, P6.S, PS.7,
CLKOUT
0.3
0.45
1.5
V
V
V
IOL c= 200 JJ-A
IOL = 3.2mA
IOL = 7 mA
VOL1
Output Low Voltage on Port 3/4
1.0
V
IOL=15mA
VOL2
Output Low Voltage on
Port 6.0-6.5
0.45
V
IOL = 10 mA
VOH
Output High Voltage
Vee - 0.3
Vee - 0.7
Vee- 1.5
V
V
V
IOH = -200 JJ-A
IOH = -3.2mA
IOH = -7 mA
Vth+-Vth-
Hysteresis Voltage Width on
RESET and All Input Pins except
Port 3, Port 4 and Port 5 besides
P5.3
0.2
V
Typical
21-9
8XC196MC
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
(Over Specified Operating Conditions) (Continued)
Min Typ
Max
Units
III
Input Leakage Current on All Input
Only Pins
±10
IJ-A
OV
< VIN < Vee-0.3V (in RESEn
ILl1
Input Leakage Current on PortO
and Port1
±3
IJ-A
OV
< VIN < VREF
IlL
Input Low Current on SD Ports
(Note 1)
-70
IJ-A
VIN = 0.3 Vee
111l
Input Low Current on P5.4 and
P2.6 during Reset
-7
rnA
0.2 Vee
IOH
Output High Current on P5.4 and
P2.6 during Reset
rnA
0.7 Vee
lee
Active Mode Current in Reset
50
70
rnA
IREF
AID Conversion ReferenceCurrent
2
5
rnA
XTAL1 = 16 MHz,
Vee = Vpp = VREF = 5.5V
IIDL
Idle Mode Current
15
30
rnA
IpD
Power-Down Mode Current
5
50
IJ-A
RRST
RESET Pin Pullup Resistor
65k
n
Cs
Pin Capacitance (Any Pin to VSS)
10
pF
-2
6k
NOTES:
1. BD (Bidirectional ports) include:
P2.0-P2.7, except P2.6
P3.0-P3.7
P4.0-P4.7
PS.0-PS.3
PS.S-PS.7
2. During normal (non-transient) conditions. the following tolal current limits apply:
P6.0-P6.S
P3
P4
PS, eLKOUT
P2, P6.6, P6.7
IOL:
IOL:
IOL:
IOL:
IOL:
40 rnA
90 rnA
90 rnA
3S rnA
63 mA
IOH:
IOH:
IOH:
IOH:
IOH:
28 mA
42 mA
42 rnA
3S mA
63 rnA .
21-10
Test Conditions
Vee = Vpp = VREF = 5.5V
FTEST = 1.0 MHz
8XC196MC
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H -High
A -Address
L
L
B -BHE
BR-BREO
-Low
-ALE/ADV
V -Valid
C -CLKOUT
R -RD
X -
D -DATA
W -
WR/WRH/WRL
G -
X -
XTAL1
No Longer Valid
Z - Floating
Buswidth
H -HOLD
Y -READY
HA-HLDA
0 - Data Out
AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, Fosc = 16 MHz.
The system must meet the following specifications to work with the 87C196MC:
Symbol
Parameter
FXTAl
Frequency on XTAL1
Tosc
1/FXTAl
TAVYV
Address Valid to READY Setup
TllYV
ALE Low to READY Setup
TYlYH
Not READY Time
TClYX
READY Hold after CLKOUT Low
TllYX
READY Hold after ALE Low
TAVGV
Address Valid to BUSWIDTH Setup
TllGV
ALE Low to BUSWIDTH Setup
TClGX
Buswidth Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
Max
Units
Notes
8
16
MHz
3
62.5
125
ns
2 Tosc - 75
ns
Min
Tosc - 70
No Upper Limit
0
Tosc - 15
ns
Tosc - 30
ns
1
2 Tosc - 40
ns
1
2 Tosc - 75
ns
Tosc - 60
ns
3 Tosc - 55
ns
2
2
RD Active to Input Data Valid
Tosc - 22
ns
Tosc - 50
ns
Tosc
ns
TClDV
TRHDZ
End of RD to Input Data Float
TRXDX
Data Hold after RD Inactive
0
4
ns
0
TRlDV
CLKOUT Low to Input Data Valid
4
ns
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 TOSC • N, where N = number of wait states.
3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
4. These timings are included for compatibility with older -90 and BH products. They should not be used for newer highspeed designs.
21-11
8XC196MC
AC ELECTRICAL CHARACTERISTICS (Continued)
Test Conditions: Capacitive load on all pins = 100 pF, Rise an,d fall times = 10 ns, Fosc = 16 MHz.
The 87C196MC will meet the following timing specifications:
Symbol
Parameter
Min
Max
Units
30
110
ns
TXHCH
XTAL 1 to CLKOUT High or Low
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Falling Edge to ALE Rising
-5
15
ns
TLLCH
ALE Falling Edge to CLKOUT Rising
-20
15
ns
ns
2 Tosc
Tosc - 10
hHLH
ALE Cycle Time .
hHLL
ALE High Period
Tosc - 10
Tosc
+ 15·
ns
ns
4 Tosc
Tosc
+ 10
TAVLL
Address Setup·to ALE Falling Edge
Tosc - 15
ns
Address Hold after ALE Falling
Tosc - 40
ns
TLLRL
ALE Falling Edge to RD Falling
Tosc - 30
TRLCL
RD Low to CLKOUT Falling Edge
TRLRH
RD Low Period
TRHLH
RD Rising Edge to ALE Rising Edge
TRLAZ
RD Low to Address Float
TLLWL
ALE Falling Edge to WR Falling
TCLWL
CLKOUT Low to WR Falling Edge
TQVWH
Data Stable to WR Rising Edge
TCHWH
CLKOUT High to WR Rising Edge
TWLWH
WR Low Period
Tosc - 5 .
Tosc
ns
30
Tosc
Tosc
+ 25
+ 25
5
25
.
ns
3
ns
1
ns
ns
ns
Tosc - 23
-10
ns
ns
Tosc - 10
0
15
ns
Tosc - 30
ns
TWHQX
Data Hold after WR Rising Edge
Tosc - 25
ns
TWHLH
WR Rising Edge to ALE .Rising Edge
Tosc - 10
TWHBX
BHE, INST Hold after WR Rising
Tosc - 10
ns
TWHAX
AD8-15 Hold after WR Rising
Tosc - 30
ns
TRHBX
BHE, INST Hold after RD Rising
Tosc - 10
ns
TRHAX
ADB-15 Hold after RD Rising
Tosc - 30
ns
NOTES:
1. Assuming back to back cycles.
2. 8-bit bus only.
3. If wait states are used, add 2 Tosc'N, where N = number of wait states.
21-12
3
ns
TLLAX
4
Notes
Tosc
+ 15
ns
3
1
2
2
8XC196MC
SYSTEM BUS TIMINGS
XTAL1
CLKOUT
XHCH
T
1= TCLLH~
==1 . . .____
~
CHCL
T
_ _ _ _ _ _ _ _ ___101
TLLCH
--I
f.-
ALE
•
BUS
ADDRESS OUT
BUS
r--
~---------------
r--
~
RHBX
'----- T
TWHBX
BHE, INST
~'-----------------VA-L-ID-----------------
1_
AD8-15
RHAX
TWHAX
T
~'--------------A-D-DR-E-S-S-O-UT-------------
----------270946-5
21-13
8XC196MC
READY TIMINGS (One Walt State)
XTAl1
ClKOUT
ALE
ClYX
T
(~IN)
READY
TRlRH
+ 2TOSC
TRLOV + 2TOSC
TAVDV + 2Tase
BUS
ADDRESS OUT
DATA IN
TWlWH + 2Tase
TRlDV + 2Tosc
ADDRESS OUT
BUS
-l
DATA OUT
270946-6
BUSWIDTH TIMINGS
XTAL1
~: ~ 'llGvC~J
_/----J\~/-~
.~ I- t-- ClGX
T
BUSWIDTH
BUS
(MIN)
---I
---------------------~--------------~
~ TAVGV
~~--------------~>-<~--~)~------------------------ 270946-7
21-14
8XC196MC
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TxLXL
Oscillator Frequency
B
16.0
MHz
62.5
125
ns
TXLXL
Oscillator Period
TXHXX
High Time
22
TXLXX
Low Time
22
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
EXTERNAL CRYSTAL CONNECTIONS
ns
ns
EXTERNAL CLOCK CONNECTIONS
Cl
Vss
II
('
XTAL 1
" i\
.1.
\
~~
4.7K' . - - - - - - - . ,
EXTERNAL
axc 196MC
CLOCK INPUT
">c)--<~--I
XTAL 1
clock driver
XTAL2
no connect
aXC196MC
XTAl2
Quartz Crystal
270946-14
270946-15
, Required if TTL driver used.
Not needed if CMOS driver is used.
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTALt, XTAL2 and Vss. When
using crystals, Cl = 20 pF, C2 = 20 pF. When using
ceramic resonators, consult manufacturer for recommended circuitry.
EXTERNAL CLOCK DRIVE WAVEFORMS
270946-S
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.
=x
x=
AC TESTING INPUT, OUTPUT WAVEFORMS
3.5V
O.... 5V
2.0
0.8
>
TESTPOINTS
<
2.0
0.8
FLOAT WAVEFORMS
V LOAO +O.l v , -_ _ _ _ _ __'\,
v LOAO
270946-9
AC Testing inputs are driven at 3.5V for a Logic "1" and OA5V for
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOH/VOL Level occurs
IOl/loH ~ ,;; ± 15 mA.
a Logic "0". Timing measurements are made at 2.0V for a Logic
"I" and O.SV for a Logic "0".
21-15
intet
8XC196MC
TCONY = Conversion time, /Ls
Fosc = Processor frequency, MHz
8 = a for a-bit conversion
8 = 10 for 10-bit conversion
CONY = Value loaded into AD_TIME
bits 0-5
A TO D CHARACTERISTICS
The sample and conversion time of the AID converter in the a-bit or 10-bit modes is programmed by
loading a byte into the AD_TIME Special Function
Register. This allows optimizing the AID operation
for specific applications. The AD_TIME register is
functional for all possible values, but the accuracy of
the AID converter is only guaranteed for the times
specificed in the operating conditions table.
The value loaded into AD_TIME bits 5, 6, 7 determines the sample time, TSAM, and is calculated using the following formula:
SAM = (TSAM x Fosd - 2
a
CONY must be in the range 2 through 31.
The converter is ratiometric, so absolute accuracy is
dependent on the accuracy and stability of VREF.
VREF must be close to VCC since it supplies both the
resistor ladder and the analog portion of the converter and input port pins. There is also an AD_TEST
SFR that allows for conversion on ANGND and
VREF as well as adjusting the zero offset. The absolute error listed is WITHOUT doing any adjustments.
AID CONVERTER SPECIFICATION
TSAM = Sample time, /Ls
Fosc = Processor frequency, MHz
SAM = Value loaded into AD_TIME
bits 5, 6, 7
SAM must be in the range 1 through 7.
The value loaded into AD_TIME bits 0-5 determines the conversion time, TCONY, and is calculated
using the following formula:
The specifications given assume adherence to the
operating conditions section of this data sheet. Testing is performed with VREF = 5.12V and 16.0 MHz
operating frequency. After a conversion is started,
the device is placed in the IDLE mode until the conversion is complete.
CONY = (TCONY x Fosd - 3 _ 1
28
21-16
intel~
8XC196MC
10-BIT MODE AID OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
Ambient Temperature
-40
+85
·C
Vee
Digital Supply Voltage
4.50
5.50
V
5.50
V(1)
TA
VREF
Analog Supply Voltage
TSAM
Sample Time
1.0
TeONV
Conversion Time
10.0
20.0
/J-s(2)
Fose
Oscillator Frequency
8.0
16.0
MHz
4.00
/J-s(2)
NOTES:
ANGND and Vss should nominally be at the same potential.
1. VREF must be within 0.5V of Vee.
2. The value of AD_TIME is selected to meet these specifications.
10-BIT MODE AID CHARACTERISTICS
Parameter
(Over Specified Operating Conditions)
Typical(1)
Resolution
Absolute Error
Min
Max
Units'
1024
10
1024
10
Levels
Bits
0
±4
LSBs
Full Scale Error
0.25 ±0.5
LSBs
Zero Offset Error
0.25 ±O.S
LSBs
Non-Linearity
1.0 ±2.0
Differential Non-Linearity
±4
LSBs
>-1
+2
LSBs
±1.0
LSBs
Channel-to-Channel Matching
±0.1
0
Repeatability
±0.2S
0
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
LSBs
LSB/C
LSB/C
LSB/C
dB(2,3)
-60
Off Isolation
Feedthrough
-60
dB(2)
Vee Power Supply Rejection
-60
dB(2)
Input Series Resistance
Sampling Capacitor
DC Input Leakage
2K
0(4)
ANGND - 0.5
VREF + 0.5
V(5,6)
0
±3.0
750
Voltage on Analog Input Pin
3
pF
±1
/J- A
NOTES:
"An "LSB", as used here has a value of approximately 5 mY. (See Embedded Microcontrollers and Processors Handbook
for AID glossary of terms).
1. These values are expected for most parts at 25'e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to ± 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
21-17
•
8XC196MC
8-BIT MODE AID OPERATING CONDITIONS
Description
Min
Max
Units
TA
Symbol
Ambient Temperature
-40
+85
'C
Vec
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.00
5.50
W)
TSAM
Sample Time
TeONv
Conversion Time
7.0
20.0
p.s(2)
Fose
Oscillator Frequency
8.0
16.0
MHz
p.s(2)
1.0
-NOTES:
ANGND and Vss should nominally be at the same potential.
1. VREF must be within O.SV of Vee.
2. The value of AD_TIME is selected to meet these specifications.
8-BIT MODE AID CHARACTERISTICS
Parameter
(Over the Above Operating Conditions)
Typlcal(1)
Resolution
Absolute Error
Full Scale Error
±0.5
Zero Offset Error
±0.5
Min
Max
Units'
256
8
256
8
Level
Bits
0
±1
LSBs
LSBs
LSBs
0
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
±1
LSBs
>-1
+1
LSBs
0
±1.0
LSBs
Repeatability
±0.25
LSBs
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
LSB/C
LSB/C
LSB/C
dB(2,3)
-60
Off Isolation
Feedthrough
-60
Vce Power Supply Rejection
-60
dB(2)
dB(2)
750
Input Series Resistance
Voltage on Analog Input Pin
VSS- 0.5
Sampling Capacitor
3
DC Input Leakage
±1
2K
n(4)
VREF + 0.5
V(S,6)
pF
0
±3.0
p.A
NOTES:
'An uLSB" as used here, has a value of approximately 20 mY. (See Embedded Microcontrollers and Processors Handbook
for AID glossary of terms).
1. These values are expected for most parts at 2S'C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break,Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to ±2 mAo
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
21-18
8XC196MC
EPROM SPECIFICATIONS
OPERATING CONDITIONS
Description
Symbol
TA
Ambient Temperature during Programming
Min
Max
20
30
Units
°C
Vee
Supply Voltage during Programming
4.5
5.5
V(1)
VREF
Reference Supply Voltage during Programming
4.5
5.5
V(1)
Vpp
Programming Voltage
12.25
12.75
V(2)
VEA
EA Pin Voltage
12.25
12.75
V(2)
Fose
Oscillator Frequency during Auto
and Slave Mode Programming
6.0
B.O
MHz
Tose
Oscillator Frequency during
Run-Time Programming
6.0
12.0
MHz
..
NOTES:
1. Vee and VREF should nominally be at the same voltage during programming.
2. Vpp and VEA must never exceed the maximum specification, or the device may be damaged .
3. Vss and ANGND should nominally be at the same potential (OV).
4. Load capacitance during Auto and Slave Mode programming = 150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Min
Parameter
Max
Units
1100
Tose
TSHLL
Reset High to First PALE Low
TLLLH
PALE Pulse Width
50
Tose
TAVLL
Address Setup Time
0
Tose
TLLAX
Address Hold Time
100
TpLDV
PROG Low to Word Dump Valid
50
Tose
TpHDX
Word Dump Data Hold
50
Tose
TDVPL
Data Setup Time
0
Tose
400
Tose
50
Tose
Tose
TpLDX
Data Hold Time
TpLPH(1)
PROG Pulse Width
TpHLL
PROG High to Next PALE Low
220
Tose
TLHPL
PALE High to PROG Low
220
Tose
TpHPL
PROG High to Next PROG Low
220
Tose
TpHIL
PROG High to AINC Low
0
Tose
TILIH
AINC Pulse Width
240
Tose
TILVH
PVER Hold after AINC Low
50
Tose
TILPL
AINC Low to PROG Low
170
TpHVL
PROG High to PVER Valid
Tose
220
Tose
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
21-19
8XC196MC
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Vpp Supply Current (When Programming)
Ipp
NOTE:
.
Do not apply Vpp until Vee is stable and within' specifications and the oscillator/clock has stabilized or the device may be
damaged.
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
----J
1
I;TAVLL~
PORTS
"
3/4
-
TSHLL
ADDR/COt.4t.4AND
,
J
TLLAX -+
;+--
DATA
TDVPL
I
TLLLH
- - - i+-
TLHPL
• TpLDX '"
,
-+0
J'~ ADDR/COt.4t.4AND
-
\
TpLPH -
1* TpHLL ...
1/
PVER
,
! - TpHVL -
2709461-11
NOTE:
P3.0 must be high ("1 ")
21-20
infel .
8XC196MC
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
---J
I
PORTS
ADDR/COt.lt.tAND
"
3/1,
- TSHLL -
,
ADDR
/
f-
TpLDV -
-
,
TILPL
TpHDX
I-
...j-TPLDV - .
,
II
I---
ADDR+2
I
VER BITS/WD DUt.lP ~ ~
(;VER BITS/WD DUt.lP )
f-o-
TpHDX
I-
II
TpHPL -
~
270946-12
NOTE:
P3.0 must be low ("0")
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
iiffiTJ
PORTS
3/4
PALE
(
ADDR/COt.lt.tAND
>--<
ADDR
DATA
>
G!!:>-<
DATA
>-
'------1
-
PROG
ADDR+2
ADDR
TpHPL ....
. \....!l...J ~
PVER
\
T1LPL - '
-
-
PH
J
-
\
~ FOR
VAUD
PH
VALID FOR P1
I-II
T1LVH
----'
_T1L1H
AiNC
-
21-21
\ --'1
TpHIL
-
270946-13
8XC196MC
3. EXTINT function description now includes
WG_PROTECT (1 FCEH) as the name and address of the register used to select positive/negative or high/low detection for EXTINT.
4. The memory range 01 FOOH-01 FBFH was added
to the SFR map as RESERVED.
5. IlL changed from - 60 poA to -70 poA.
87C196MC DESIGN
CONSIDERATIONS
When an indirect shift during divide occurs the upper
3 bits of the shift count are not masked completely.
If the shift count register has the value 32.n where n
= 1, 3, 5 or 7, the operand will be shifted 32 times.
This should have resulted in no shift taking place.
6. IREF changed from 5 mA to 2 mA maximum and
the typical specification was removed.
7. The READY description of the READY TIMINGS
(One Wait State) graphic was modified to denote
the shifting of the leading edge of READY versus
frequency. At 16 MHz the falling edge of READY
occurs before the falling edge of ALE.
DATA SHEET REVISION HISTORY
. This data sheet (270946-004) is valid for devices
with a "B" at the end of the topside tracking number.
Data sheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before finalizing a design or ordering devices.
8. AC Testing Input, Output Waveform was
changed to reflect inputs driven at 3.5V for a
Logic "1" and .45V for a Logic "a" and timing
measurements made at 2.0V for a Logic "1"
and 0.8V for a Logic "a".
The following important differences exist between
this data sheet (270946-002) and the previous version (270946-003):
1. The data sheet was reorganized to standard format.
2. Added 83C196MC device.
3. Added package thermal characteristics.
4. Added note on missing pins on SDIP package.
5. Removed SFR maps (now in user's manual).
9. Float Waveform was changed from IOL/IOH =
± 15 mA to IOL/IOH s: ± 15 mA
10. AD_TIME register for 10-bit conversions was
changed from OC7H to OD8H .. The number of
sample time states was changed from 24 to 25
states, the conversion time states was changed
from 80 to 240 states, and the total conversion
time for AD_TIME = D8H replaced the total
conversion time for AD_TIME = C7H.
6. Added note on TLLYV and T LLGV specifications.
7. Changed 10-bit mode TCONV (MIN) to 10.0 pos
from 15.0 pos.
8. Changed 10-bit mode TCONY (MAX) to 20.0 pos
from 18.0 pos.
9. Changed VREF (MIN) in 8- and 10-bit mode to
4.0V from 4.5V.
The following important differences exist between
data sheet 270946-003 and the previous version
(270946-002):
1. The data sheet title was changed to better reflect
the purpose of the 87C196MC as an AC Inverterl
bc Brushless Motor Control Microcontroller.
2. The standard temperature range for this part now
covers - 40·C to + 85·C.
11. The number of sample time states for an 8-bit
conversion was changed from 20 states to 21
states.
12. There is a single entry in the ERRATA section of
this version of the data sheet concerning the
results of an indirect shift during divide.
The following important differences exist between
this data sheet (270946-002) and the previous version (270946-001):
1. TA Ambient Temperature Under Bias Min
changed from -20·C to -40·C.
2. IREF AID Conversion Reference Current Max
changed from 5 mA to 2 mAo
3. Testing levels changed from TTL values to
CMOS vaJues.
4. AID Input Series Resistance Max changed from
.
1.2 K!l to 2 K!l.
21-22
MCS®--96 Development
Support Tools
22
ICETM-196KD/HX IN-CIRCUIT EMULATOR
REAL-TIME IN-CIRCUIT EMULATION FOR MCS®-96
MICROCONTROLLERS
Intel's ICETM-196KD/HX In-Circuit Emulator (lCE) is an easy-to-use, full-featured tool to
help you develop, integrate, and test your MCS-96 microcontroller-based products.
The ICE-196KD/HX supports all component variations offered in the following Intel
MCS-96 families: 8xC196KD, 8xC196KC, 8xC196KB, 8xC198, and 8xC194.
The emulator supports all component types as differentiated by ROM, EPROM, and
ROMless; as well as components differentiated by temperature, reliability screenings,
package types, and speeds (up to 20 MHz). Precise and reliable emulation is assured due
to the emulator's matching of the component's electrical and timing characteristics.
FEATURES
• Real-time, Transparent, In-Circuit
Emulation at Speeds up to 20 MHz
• On-Circuit Emulation (ONCE) for
Emulating Surface-Mounted 8xC196
Devices
• Execution and BUB Breaks (including
Breaks on Internal Events and
"Fastbreaks")
• Execution and Bus Trace
o Internal and External Bus Event
Recognition
• 128 Kbytes of Zero-Waitstate, Mappable
ICE Memory
• Source-Level, Symbolic Debugging
• Full-Color, Windowed, Easy-to-Use
Interface (with Pull-Down Menus, PopUp Help, Hypertext Browsing, Function
Keys, ... )
• Stand-Alone Operation and Self-Test
Diagnostics
• Hosted on IBM PC XTs, ATs, PS/2s and
100% Compatible Machines (Serial
Connection from PC to Emulator at up to
57.6 Kbaud) ,
·IBM PCI AT is a registered trademark of International Business Machines.
22-1
September 1992
Order Number: 280902-003
infel"
FEATURES
SOPHISTICATED, POWERFUL
CAPABILITIES
• Conditional arming and disarming of break
specifications (2-state state machine).
• Conditional arming and disarming of trace
specifications.
• Ability to reprogram break and trace
specifications during emulation.
• Break and trace REGISTERS for storing
complex break/trace definitions for reuse.
Event Recognition
To aid the debugging process, the ICE-196KD/
HX user has access to very sophisticated event
recognition capabilities. Triggering can occur
based on:
• Instruction Fetches
• Execution Addresses
• External Data Reads or Writes at a range
of addresses
• Internal/External Data Reads or Writes at
a specific address
• Internal/External Data Reads or Writes at
a specific value
• Internal/External Data Reads or Writes at
a range of values
• Signals from an External Device (causing
an asynchronous break)
• CLIPSIN Status (8 external Clips
available), or
• Trace Buffer Full Events
Compound triggers may be constructed
through AND/OR combinations of events.
Specifically:
• OR combinations of execution/bus events
• OR combinations of bus/bus events
• AND combinations of bus/bus events
The trace buffer is accessible during
emulation. The buffer can contain up to 2048frames of information such as:
• Addresses
• Opcodes in Hex and Mnemonic Formats
• Operands in Hex and Symbolic Formats
• Bus Address/Data
• Processor Status Bits
• Logic Clips Information
In addition, the ICE-196KD/HX offers the
following break and trace features:
• Recognizes up to 255 execution addresses;
either specific addresses or address ranges.
• FASTBREAKS: emulation is immediately
broken only for the duration of a requested
memory access (typically 25 )Ls at 20 MHz).
• A deferred FASTBREAK option: a
F ASTBREAK is honored only after
reaching a specified address.
Execution Control
• Single-step execution of machine
instructions, high'levellanguage statements,
or procedure call blocks.
• Functions to disassemble/assemble memory
in the form of machine instructions and to
display/modify program variables and
special function registers.
• Symbolic referencing to memory locations
and information in trace and memory
disassembly displays.
System Resources
• The 128 Kbytes of mappable, zero-waitstate
ICE memory can be used to:
• Execute and debug programs before target
hardware exists
• Simulate non-existent or non-working target
memory
• Overlay target EPROM space (avoiding the
inconvenience of programming EPROMs).
• Event counters.
• To aid performance analysis, an event timer
records the time from/to specified events
while an emulation timer records the total
duration of emulation.
• Synchronized multi-emulator start and
break signals and a trigger out signal for
synchronization with an external logic
analyzer or other device are available.
• Eight external logic input lines may be used
to trigger an action in the emulator. The
status ofthe external lines is captured in the
trace buffer.
• The user may qualify events with an
external input SYSIN line.
• A SYSOUT output may be used to stimulate
an action in the target system based on a
recognized event.
22-2
int:eL
FEATURES
Easy To Use
Genuine Intel Tools
For ease of use and learning, the
ICE-196KD/HX emulator can be operated via
a command line interface or with Intel's
windowed user interface. The command line
style (with syntax guide) is compatible with
previous emulators, while the windowed
interface has the same look and feel as other
Intel emulators and software debuggers.
The ICE-196KD/HX emulator provides the
most comprehensive support for Intel's
MCS-96 family of microcontrollers. When you
trust your component selection to Intel, why
trust its emulation to someone else?
Windows and Pull-Down Menus
To augment its development tools, Intel offers
field application engineering expertise, hotline
technical support, and on-site service.
Intel also offers software support which
includes technical software information,
automatic distributions of software and
documentation updates, iCOMMENTS
publication, remote diagnostic software, and a
development tools troubleshooting guide.
Intel's standard 90-day Hardware Support
package includes technical hardware
information, telephone support, warranty on
parts, labor, material, and on-site hardware
support.
Intel Development Tools also offers a 30-day,
money-back guarantee to customers who are
not satisfied after purchasing any Intel
development tool.
Worldwide Service, Support, and
Training
Each window presents a different view ofthe
system. Select and move between a
COMMAND LINE window, a SOURCE
window, a REGISTER window, a TRACE
window, a MEMORY window, or a WATCH
window (where user variables are displayed).
In addition, a CUSTOM window can perform
user-defined functions. Within each window,
option menus, pop-up fill-in-the-blank forms,
and scroll keys control the view. As expected,
windows may be added, sized, zoomed to full
screen, or removed completely.
Help at Your Fingertips
Both indexed and context sensitive help is
available. A hypertext capability lets you easily
move between help subjects. In addition, a Key
Reference Line displays a list of the currently
active function keys as well as brief help text
for menus and forms.
Source Level Debugging
Source level debugging with Intel's C-96,
ASM-96, and PL/M-96 is synergistic with the
windowed user interface. For example, simply
use a pull-down menu to load the program.
Then set a breakpoint at a souce line by
pointing to the line of code in the SOURCE
window and pressing a function key. Set trace
specifications by using a pop-up, fill-in-theblank form. With the current execution
location highlighted, simply press a function
key to begin emulation.
22-3
..
SPECIFICATIONS
Host Requirements
Target Considerations
Emulator requires an IBM PC AT, XT, PS/2 or
100% compatible machine with 640 Kbytes of
RAM and a hard disk running DOS 3.3 or 5.0.
The acceptable target Vcc range is 4.5V to
5.5V and the maximum Vcc power
consumption of the processor is 1.5W at
20 MHz.
Electrical Characteristics
Power supply: 100V -120V or 200V -240V
50 Hz or 60 Hz
5 amps (AC max) @ 120V
2 amps (AC max) @ 240V
Electrical Considerations
The emulator processor's user-pin timings and
loading are identical to the 8xC196KD
component except as follows:
" Additional pin capacitance (approximate):
" Target Interface
12 pf (30 pf max)
Board (TIB)
" pin 32 (P1.7IHOLD#) 70 pf
" pin 63 (INST)
60 pf
" pin 16 (RESET#)
325 pf
" all pins when using
10 pf
adapter with a
flexible cable (ex.
KADPTCA68PLCC)
• DC loading:
Pin 1 (V cd may draw an additional 5 mA
(15 mA worst case @ 5.5V) due to power
sensing circuitry.
Sensing circuitry may also draw
approximately ± 0.1 rnA (maximum) DC
current from any 8xC196KD output pin.
• AC timings:
• pin 32 (PI. 7/HOLD #) degraded 1 ns
" pin 63 (INST) if
degraded 1 ns
jumper E5-E6 is
installed
degraded 15 ns
" pin 16 (RESET#)
Environmental Characteristics
Operating temperature: 1O·C to 40·C
Operating humidity:
maximum 85%
relative humidity,
non-condensing
Processor Module Dimensions
1\4-'-"'--~'I
~~.~r:"'~T~~ \
',:~. ~1.
'--------..-Ll~Ll
10- •. '-+1
3
TAAGET INTERFACI! BOARD
C
FLEX CABLE
PlCCPROBE
280902-5
Physical Characteristics
Target Probe
Width:6.9cm (2.7")
Height: 3.0cm (1.2" )
Length: 1I.Ocm (4.34")
Emulator Chassis
Power Supply
Width: 34cm (13%") Width: 18cm (7'/.")
Height: 12cm (4'/2")
Height: 10cm (4")
Depth: 27cm (10%" ) Depth: 28cm (11") .
Weight: 3.2 kg (7 lb.)
Weight: 7kg (15 lb.)
Probe Cable Length: 40 cm (17" )
Serial Cable Length: 3.65m (12')
22-4
int:eL
ORDERING INFORMATION
Emulators
D86PLM96NL DOS·hosted PL/M cross·
compiler. Architectural
extensions support all MCS·96
components. Optimized for
real·time, embedded
applications.
D86ASM96NL DOS-hosted macro assembler.
Supports all MCS·96
components.
Order Code
Description
PICE196KDHXDZ Complete, fully·featured
emulator kit. Contains all
required emulator
hardware and software to
execute stand·alone or in·
target. Kit includes:
NOTE: All software tool packages include a relocaterllinker
(Rlr96), an object-to-hex converter (OR), a floating
point arithmetic library (FPAlr96), and a librarian
(LIB-96).
• emulator base chassis
and serial cable
• external power supply
and power cord
Target Adapters
• Emulation Control
Board (ECB II)
Order Code
KADPT52PLCC
Description
target: 52·lead PLCC
components (socketed)
KADPTCA68PLCC target: 68-lead PLCC
components (socketed)
KADPTONC68PLCC target: 68·lead PLCC
components (surface·
mounted 8xC196
components)
KADPTCA68PGA
target: 68·lead PGA
components (socketed)
KADPT64SDIP
target: 64·pin "shrink"·
DIP components
(socketed)
I196ADPTCA80Q
complete probe cable
assembly for 80·lead
QFP(EIAJ) component
for minimal signal
degradation
converter for existing
I196CONV80Q
PLCC probe to 80·lead
QFP (EIAJ) component
• ICE Base Board (IBB II)
• Break/Trace Board
(BTB)
• 64 Kbyte Optional
Memory Board (OMB)
• CLIPSIN and
CLIPSOUT pods
• Crystal Power
Accessory (CPA) (used
for diagnostics and
stand·alone operation)
• Target Interface Board
(TIB) fitted with a
68·lead PLCC adapter
• PC host software
(featuring iWHI: Intel's
Windowed Human
Interface)
• all user documentation
NOTE: host software is delivered on 5'/." high density (1.2
Mb) and 3'/," standard (720 Kb) density diskettes
Software Tools
Order Code Description
D86C96NL DOS·hosted "CC" cross compiler
closely conforming to ANSI C
standards, with architectural
extensions to support all MCS·96
components. Optimized for real·
time embedded applications.
22·5
ICETM-196KD/PC IN-CIRCUIT EMULATOR
280917-1
REAL-TIME IN-CIRCUIT EMULATION FOR MCS®-96
MICROCONTROLLERS
Intel's ICE-196KD/PC In-Circuit Emulator is a low-cost, PC-card form factor emulator
that delivers real-time, high-level debugging capabilities to help you develop, integrate,
and test your MCS-96 microcontroller-based products.
The ICE-196KD/PC emulator supports all component variations offered in the following
Intel MCS-96 families:
• 8xC196KD
• 8xC194
• 8xC196KC
• 8xC198
• 8xC196KB
The emulator supports all component types as differentiated by ROM, EPROM, and
ROMless; as well as components differentiated by temperature, reliability screenings,
package types, and speeds (at up to 16 MHz).
FEATURES
• Real-time, transparent, in-target
emulation at speeds up to 16 MHz
• Execution breaks (3 specific or 1 range
breakpoint)
• Execution trace (2048 frame trace buffer)
• 64 Kbytes of zero-waitstate, mappable
ICE memory
• Source-level, symbolic debugging
• Stand-alone operation and self-test
diagnostics
• Hosted on IBM PC XTs, ATs, PS/2 Model
30s, and 100% compatibl~ machines
• 30 Day money back guarantee
22-6
August 1992
Order Number: 280917'()03
intel~
FEATURES
REAL-TIME EMULATION
SYMBOLIC SUPPORT AND
SOURCE CODE DISPLA Y
The ICE-196KD/PC emulator provides realtime, transparent in-circuit emulation for all
components in the 8xC196KD, 8xC196KC,
8xC196KB, 8xC198, and 8xC194 microcontroller families. Running in-circuit, the
emulator is able to operate at up to 16 MHz for
all target processors.
The ICE-196KD/PC emulator connects to your
target via a 16" (40 cm) flex cable. A 68-lead
PLCC target adapter is included with the ICE196KD/PC emulator. Other target adapters
supporting other package types are available
separately (see "Ordering Information").
Full C-96, PL/M-96, and ASM-96 language
symbolics (including variable typing and
scope), are supported by the ICE-196KD/PC
emulator. As an example, source-level,
symbolic debugging affords you the
convenience of
• setting breakpoints symbolically
go til line # 25
• referencing memory symbolically
display MY---ARRA Y length
MY---ARRA y.-sIZE as characters
You can browse through your original source
code, and optionally, the high-level "C" or
PL/M source will be displayed when
breakpoints are reached.
MAPPABLE MEMORY
The ICE-196KD/PC emulator contains
64 Kbytes of zero-waitstate ICE memory that
can be used to:
• execute and debug programs before target
hardware exists
• simulate non-existent or non-working target
memory
• overlay target EPROM space (saving time
and bother by avoiding the need to program
EPROMs).
The ICE memory can be set up as READONLY, WRITE-ONLY, or READ/WRITE.
STANDALONE OPERATION
FOR SOFTWARE DEBUGGING
Code can be downloaded for execution on the
target system. Or, by using the supplied
Crystal Power Accessory (CPA) and mappable
ICE memory), code can be downloaded and
executed in the emulator itself. This capability
allows you to prototype and debug your target
software prior to hardware availability.
VERSATILE AND POWERFUL
HOST SOFTWARE
TRACE BUFFER
The ICE-196KD/PC emulator contains a 2048
frame trace buffer for keeping a history of
actual instruction execution. The trace buffer
can be conditionally turned off to collect a user
specified number of trace frames. Trace
information can be displayed as disassembled
assembly instructions, or as disassembled
assembly instructions intermixed with the
original high-level language source code.
BREAKPOINTS
Three execution address breakpoints or one
address range breakpoint can be active at any
one time. The ICE-196KD/PC emulator allows
any number of breakpoints to be defined and
activated when needed.
The ICE-196KD/PC emulator host software
features on-line help, a command line syntax
guide, a built-in editor (for creating/ editing
PROCs, editing source, or viewing the trace
buffer), an assembler/disassembler, and a
macro command language (for building
command procedures).
To augment its development tools, Intel offers
field application engineering expertise and
hotline technical support.
Intel Development Tools also offers a 3O-day,
money-back guarantee to customers who are
not satisfied after purchasing any Intel
development tool.
22-7
II
intel·
SPECIFICATIONS
HOST REQUIREMENTS
TARGET CONSIDERATIONS
The ICE-196KD/PC emulator is hosted on IBM
PC XTs, ATs, PS/2 Model30s, and 100%
compatible machines with 640 Kbytes of RAM
and a hard disk running DOS 3.3 or 5.0.
Though the emulator card plugs into a single
8-bit PC slot, two slots should be reserved for
clearance.
The acceptable target Vcc range is 4.5V to
5.5Vand the maximum Vcc power
consumption of the processor is 1.5W at
16 MHz.
When entering or exiting emulation, the ICE196KD/PC emulator will use two bytes on the
user stack to store the current instruction
pointer.
ELECTRICAL
CONSIDERATIONS
• Additional pin capacitance:
all pins
60pF
all pins when using an
'70pF
adapter with flexible cable
(ex: KADPTCA68PLCC)
• Cable propagation delay:
best case '
5.5 ns
11.0 ns
worst case
• Operating frequency: 3.5 MHz to 16 MHz
,
(CPA runs at 16 MHz
only)
ENVIRONMENTAL
CHARACTERISTICS
Operating temperature: 1000C to 40"C
Operating humidity:
maximum 85%
relative humidity,
non-condensing
ORDERING INFORMATION
order code
description
PICE196KDPC Complete emulator kit.
Contains all required emulator
hardware and software to
execute stand-alone or intarget. Kit includes:
• Emulator controller board
(PC-card form factor)
• TargetJnterface Board (TIB)
fitted with a 68-lead PLOC
adapter
• Crystal Power Accessory
(CPA) (required for
diagnostics and stand-alone
operation)
• PC host software
• All user documentation
NOTE: Host software is delivered on 5-'/," (360 Kb) and
3-'/,' (720 Kb) diskettes
SOFTWARE TOOLS
order code
D86C96NL
description
DOS-hosted, closely
conforming ANSI "C" crosscompiler. Architectural
extensions support all MCS-96
components. Optimized for
real-time, embedded
applications.
D86PLM96NL DOS-hosted PL/M crosscompiler. Language features
allow direct architecture
access. Optimized for real-time,
embedded applications.
D86ASM96NL DOS-hosted macro assembler.
Supports all MCS-96
components.
NOTE: All software tool packages include a relocater/linker
(RL.96), an object-to-hex converter (OH), a floating
point arithmetic library
After a moment, the PC sould display the
iECM96 monitor screen.
NOTE: If users have a 25-pin serial port it will
be necessary to make a 25-pin to 9-pin adaptor
(see Users Manual for details).
HARDWARE OVERVIEW
The Evaluation Board is delivered with a
MCg-96 microcontroller, 8 K-words and 8K
bytes of user code/data memory, a UART for
host communications and analog-input
filtering with a precision voltage reference.
Al.so included, is programmable chip-select,
bus-width and wait-state-counter logic which
allows you to custom tailor the board to look
like your own system. The board's physical
dimensions are 6'1." x 7%" with an overall
height of %" . There are six main sections to
the board: Processor, Memory, Host Interface,
Digital 110, Analog Inputs and Decoding.
MEMORY
There are five 28-in memory sockets provided
on each board: U1, U6, U8, U13, U14. The
sockets are designed to support byte-wide,
JEDEC-pinout, memory devices of various
types and sizes, i.e., 8K x 8 gRAM or 16K x 8
EPROM. U1 and U8, U6 and U13 are
connected as two 16-bit memory banks and
U14 is connected as an 8-bit memory bank.
HOST INTERFACE
The PC host interface is accomplished with the
82510 UART (U20) connected to P1 via RS-232
drivers. The UART resides in the address
range 1EOOH-1EFFH. Therefore, register 0 in
the UART would be at address 1EOOH of the
MCg-96 microcontroller, register 1 would be at
1E01H, register 2 would be at 1E02H, etc., up
to register 7 at 1E07H. The registers will
repeat again with register 0 at 1E08H due to
the limited decoding granularity of the EPLD.
Pin 12 of the UART, OUT1#, is used to tell the
PC host when the MCg-96 microcontroller is
executing user code by a true level on the Ring
Indicator input of the host serial port.
DIGITAL I/O
With the exception of the NMI input, which is
used by the Host Interface, all Digital 1/0
functions of the MCg-96 microcontrollers are
available to users. There are eight LEDs onboard Iil.ong with buffer/drivers which allow
users to quickly observe the state of Port 1,
HgO.O and P2.5/PWM. The TxD and RxD pins
of the MCg-96 microcontroller (Port 2.0 and
Port 2.1) are connected to RS-232 bufferl
drivers, which are connected to P2. All of the
1/0 signals are available on JP2.
22-17
II
intel·
EV80C196KX EVALUATION BOARDS
ANALOG INPUTS
The Port 0 inputs of the MCS-96
microcontroller double as both digital and
analog inputs. Each board includes circuitry to
make the analog inputs easier to use. A
precision voltage source for VREF is provided
on board (U3 and U4) which can be carefully
adjusted by trimming RP1. Also, jumper shunt
E4 allows VREF to be connected to Vcc instead
of the output of U3. By removing E4 entirely
an off board reference can be connected to JP1.
By removing jumper shunt E2, ANGND can be
isolated from V88. Protective clamping diodes
are installed on each channel. RC networks are
provided i:nsockets (to allow users to change
the input impedance to match their
application) on all of the analog input
channels. If Port 0 is to be used as a digital
input, it is recommended that the capacitors be
removed, and the resistors replaced with wires.
For additional connection information, refer to
Figure 1. The ground and power planes
beneath the analog circuitry (D1, D2, R3, C2,
U3, U4, JP1 and the analog connections on the
8OC196KX. board) are isolated from the digital
power and ground planes of the board to keep
noise from the analog inputs.
.
272222-2
Figure 1. Block Diagram of the EV80Cl96KX Board
Even
BytesI.C.
Odd
BytesLC.
Enable
Signal
0
U8
U1
CEO
8K x IS-Bit Monitor
EPROM from O-FFH
and lDOOH-lDFFH
I
U13
U6
CE1
8K x IS-Bit ROMsim/RAM
from 2000H-5FFFH
2
U14
U14
CE2
8K x 8-Bit ROMsim/RAM
from 6000H-7FFFH
Bank
No.
..
22-18
Memory Type
intet
EV80C196KX EVALUATION BOARDS
DECODING
The decoding logic on each board serves three
purposes; to provide Chip-Enable signals to
memory and peripheral devices, to select the
bus width for the device(s) being accessed and
to provide wait states for slow devices. This
section is provided should users need to modify
the memory configuration of the board. It is
not necessary to understand this section for
normal usage of the board.
The heart of the decoding logic is U12, a 24-pin
5AC312 Intel EPLD or a C22VlO
programmable logic array which is socketed to
allow easy changes. For the sake of
convenience it will be referred to as "the
EPLD" throughout this text. The EPLD uses
latched addresses A8-A15 along the CLKOUT,
HLDA #, RESET# and STALE (Stretched
ALE) from the MCS-96 microcontroller as
decode inputs.
There are 4 enable outputs from the EPLD, all
of which are low-level true, however only one
should be true at a time to avoid bus
contention. They are decoded from the address
lines, and an internally-latched signal called
MAP. MAP is cleared when the RESET#
input is true, and set when the Monitor
EPROMs are accessed in the address range
1DOOH-1DFFH. MAP will always be set when
the board is in the USER mode.
The BUSWIDTH output of the EPLD, pin 16, is
fed into the buswidth pin of the MCS-96
microcontroller. Therefore, it is driven low for
accesses to 8-bit memory and high for accesses
to 16-bit memory. As shipped, it goes low
simultaneously with CE2 or CS510 as these are
the only areas of memory mapped as 8-bit.
Programmed into the EPLD is a 3-bit waitstate machine clocked by the rising edge of
CLKOUT from the MCS-96 microcontroller.
The transition sequence of the wait-state
machine is controlled by the current state of
the machine and inputs to the EPLD.
CEO
Pin 21
(Address Range 2000H-27FF
and Not Map) or Address
Range OH-FFH or Address
Range lDOOH-lDFFH
Enables Memory in U1 and UB
(Monitor EPROM as Shipped)
CE1
Pin 22
(Address Range 2000H-27FFH
and Map) or Address
Range 2S00H-5FFFH
Enables Memory in U6 and U13
(User H)·Bit ROMsim/RAM as Shipped)
CE2
Pin 15
(Address Range 6000H-7FFFH)
Enables Memory in U14
(User 8-Bit ROMsim/RAM as Shipped)
CS510
Pin 14
(Address Range 1EOOH-1EFFH)
Enables U20, the 82510 UART,
Which is Used for Host Communications
Wait
States
Enable
Signal
Memory Region in
User Mode
ROMsim/RAM
0
CE1
2000H-5FFFH
ROMsim/RAM
0
CE2
6000H-7FFFH
Monitor EPROM
1
CEO
OOOOH-OOFFH,
lDOOH-lDFFH
82510UART
2
CS510
1EOOH-1EFFH
Unimplemented
0
N/A
0100H-1CFFH,
COOOH-FFFFH
Unimplemented
1
N/A
8000H-BFFFH
Memory Type
22-19
II
intel~
EV80C196KX EVALUATION BOARDS
JPl Analog Input Connector
2x25 Pin Molex 39·51·2604 or Equiv.
ANGND- 1
VREF 3
ANGND- 5
ANGND- 7
9
VREF ANGND-ll
ANGND-13
VREF - 1 5
ANGND-17
ANGND-19
VREF -21
ANGND-23
VREF - 2 5
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
2 4 6 B 1012 14 16 1B 20 22 24 26 -
ANALOG
VREF
ANALOG
ANALOG
VREF
ANALOG
ANALOG
VREF
ANALOG
ANALOG
VREF
ANALOG
ANGND
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
272222-3
Figure 2
JP2 110 Expansion Connector
2x25 Pin Molex 39·51·5004 or Equiv.
1 THRU 49 -
vss
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
2 4 6 B 1012 14 16 18 20 22 24 26 2B 30 32 34 36 3B 40 42 44 46 48 50 -
P1.0 BIDIRECTIONAL
Pl. 1 BIDIRECTIONAL
P1.2 BIDIRECTIONAL
P1.3 BIDIRECTIONAL
P 1.4 BIDIRECTIONAL
P1.5/BREQ# BIDIRECTIONAL
P1.6/HLDQ# BIDIRECTIONAL
PI. 7/HOLD# BIDIRECTIONAL
P2.0/TXD OUTPUT
P2.1/RXD BIDIRECTIONAL
P2.2/EXTINT INPUT
P2.3/T2CLK INPUT
P2.4/T2RST INPUT
P2.5/PW~ OUTPUT
P2.6/T2UPDN BIDIRECTIONAL
P2. 7/T2CAPTURE BIDIRECTIONAL
HSO.O OUTPUT
HSO.l OUTPUT
HSO.2 OUTPUT
HSO.3 OUTPUT
HSI.O INPUT
HSI. I INPUT
HSI.2/HSO.4 BIDIRECTIONAL
HSI.3/HSO.5 BIDIRECTIONAL
Vee
272222-4
Figure 3
22·20
infel .
EV80C196KX EVALUATION BOARDS
JP3 Memory-I/O Expansion Connector
2x30 Pin Molex 39-51-6004 or Equiv.
1
3
5
7
9
11
13
15
17
19
Vss
A8 OUTPUT
21
A9 OUTPUT
23
25
Al0 OUTPUT
All OUTPUT
27
29
A12 OUTPUT
31
A13 OUTPUT
A14 OUTPUT
33
A15 OUTPUT
35
37
Vss
39
CLKOUT OUTPUT
RD# OUTPUT
41
BIDIRECTIONAL PI.5/BREQ# OUTPUT - 43
45
ALE OUTPUT
NMI INPUT
47
RESET# OUTPUT
49
51
DISABLE
BIDIRECTIONAL PI.6/HLDA# OUTPUT -53
-12VDC .
55
57
Vss
59
Vee
Vee
AD OUTPUT
Al OUTPUT
A2 OUTPUT
A3 OUTPUT
A4 OUTPUT
A5 OUTPUT
A6 OUTPUT
A7 OUTPUT
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
2 4 6 8 1012 14 16 18 20 22 24 -:
26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 -
Vee
DO BIDIRECTIONAL
01 BIDIRECTIONAL
02 BIDIRECTIONAL
03 BIDIRECTIONAL
04 BIDIRECTIONAL
05 BIDIRECTIONAL
06 BIDIRECTIONAL
07 BIDIRECTIONAL
Vss
08 BIDIRECTIONAL
09 BIDIRECTIONAL
010 BIDIRECTIONAL
011 BIDIRECTIONAL
012 BIDIRECTIONAL
013 BIDIRECTIONAL
014 BIDIRECTIONAL
015 BIDIRECTIONAL
VSS
Vss
WR#OUTPUT
BHE#OUTPUT
USERREADY INPUT
INST OUTPUT
P2.2/EXINT BIDIRECTIONAL
NO CONNECTION
HOLD# INPUT/PI.7 BIDIRECTIONAL
+12VDC
VSS
Vee
II
212222-5
Figure 4
JP4 Power Supply Connector
4 Pin Molex 26-03-3041 or Equiv.
FLAG
-"""~'","'H~
·+12VDC
+5VDC-Vss
272222-6
Figure 5
These evaluation boards may be purchased through your local Intel distributor or Intel sales
office. Call 1-800-468-8118 for more information (U.S. and Canada).
22-21
EV80C196KR EVALUATION BOARD
272078-1
Low Cost Code Evaluation Tool
Intel's EV8OC196KR evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. T~e board features the
80C196KR advanced, CHMOS·, single chip, 16-bit microcontroller, the newest member of
the industry standard MCS@-96 family. The board allows the user to take full advantage
of the power of the MCS-96. The EV80C196KR provides zero wait state, 16 MHz
execution of a user's code. Plus its memory (ROMsim) can be reconfIgured to match the
user's planned memory system, allowing for exact analysis of code execution speeds in a
particular application.
Popular features such as a symbolic debug, single line assembler I disassembler, singlestep program execution and sixteen software breakpoints are standard on the
EV8OC196KR. Intel provides a complete code development environment using assembly
language (ASM-96) as well as Intel's high-level languages such as iC-96 or PL/M-96 to
accelerate development schedules.
The evaluation board is hosted on an IBM PC·· or BIOS-compatible clone, already a
standard development solution in most oftoday's engineering environments. The source
code for the on-board monitor (written in ASM-96) is public domain. The program is about
1 Kbyte and can.be easily modifIed to be included in the user's target hardware. In this
way, the provided PC host software can be used throughout the development phase.
'CHMOS is a patented Intel process.
"IBM PC, XT, AT and DOS are registered trademarks o£Internationai Business Machines Corporation.
22-22
October 1991
Order Number: 272078-001
intet
EV80C196KR EVALUATION BOARD
EV80C196KR Features
Concurrent Interrogation of
Memory and Registers
• Zero Wait State 16 MHz Execution Speed
• 24 Kbytes of ROMsim
• Flexible Wait State, Buswidth, Chip-Select
Controller
e Totally CMOS, Low Power Board
• Concurrent Interrogation of Memory and
Registers
• Sixteen Software Breakpoints
• Two Single-Step Modes
• High-Level Language Support
• Symbolic Debug
• Single Line Assembler/Disassembler
• RS-232C Communications Link
The monitor for the EV80C196KR allows the
user to read and modify internal registers and
external memory while the user's code is
running on the board.
Sixteen Software Breakpoints
There are sixteen breakpoints available which
automatically substitute a TRAP instruction
at the breakpoint location. The substitution
occurs when execution is started. If the code is
halted or a breakpoint is reached, the user's
code is restored to the ROMsim.
Full Speed Execution
The EV80C196KR executes the user's code
from on-board ROMsim at 16 MHz with zero
wait states. By changing crystals on the
80C196KR, any slower execution speed can be
evaluated. The board's host interface timing is
not effected by this crystal change.
24 Kbytes ofROMsim
High-Level Language Support
The board comes with 24 Kbytes of SRAM to
be used as ROMsim for the user's application
code and as data memory if needed. 16 Kbytes
of this memory are configured as sixteen-bit
wide and 8 Kbytes are configured as eight-bit
wide. The user can therefore evaluate the
speed of the part executing from either bus
width.
The host software for the EV80C196KR board
is able to load absolute object code generated
by ASM-96, iC-96, PL/M-96 or RL-96, all of
which are available from Intel.
Symbolic Debug
The host has a single-line assembler, and a
disassembler, that recognize symbolics
generated by Intel software tools.
Flexible Memory Decoding
By changing the Programmable Logic Device
(PLD) on the board, the memory can be made
to look like the memory system planned for the
user's hardware application. The PLD controls
the bus width ofthe 80C196KR and the chipselect inputs on the board with 256-byte
boundaries of resolution. It also controls the
number of wait states (zero to four) generated
by the 80C196KR during a memory cycle.
Totally CMOS Board
The EV80C196KR board is built totally with
CMOS components. Its power consumption is
therefore very low, requiring 5 volts at only
300 rnA. If the board LEDs are disabled, the
current drops to only 165 rnA. The board also
requires ± 12 volts at 15 rnA.
Two Steps Modes
There are two single-step modes available. The
first stepping mode locks out all interrupts
which might occur during the step. The second
mode enables interrupts, and treats subroutine
calls and interrupt routines as indivisible
instructions.
RS-232C Communications Link
The EV80C196KR communicates with the host
using an Intel 82510 UART provided on the
board. This frees the on-chip UART ofthe
80C196KR for the user's application.
Personal Computer Requirements
The EV80C196KR Evaluation Board is hosted
on an IBM PC, XT, AT" or BIOS-compatible
clone. The PC must meet the following
minimum requirements.
• 512 Kbytes of Memory
• One 360 Kbyte Floppy Disk Drive
• PC DOS" Version 3.1 or later
• A Serial Port (COM1 or COM2) at 9600 Baud
• ASM-96 or PL/M-96
• A text editor such as AEDIT
22-23
II
EV80C196MC EVALUATION BOARD
272215..01
LOW COST CODE EVALUATION TOOL
Intel's EV8OC196 evaluation board provides a hardware environment for code execution
and software debugging at a relatively low cost. The board features the 8OC196MC
advanced, CHMOS', 16-bit microcontroller, the newest member of the industry standard
MCS®-96 family. The board allows the user to take full advantage of the power of the
MCS-96. The EV80C196MC provides zero wait-state, 16 MHz execution of a user's code.
Plus, its memory (ROMsim) can be reconfigured to match the user's planned memory
system, allowing for exact analysis of code execution speeds in a particular application.
Popular features such as a symbolic single line assembler/disassembler, single-step
program execution, and sixteen software breakpoints are standard on the EV80CI96MC.
Intel provides a complete code development environment using assembler (ASM-96) as
well as high-level languages such as Intel's iC-96 or PL/M-96 to accelerate development
schedules.
The evaluation board is hosted on an IBM PC" or BIOS-compatible clone, already a
standard development solution in most of today's engineering environments. The source
code for the on-board monitor (written in ASM-96) is public domain. The program is about
lK, and can be easily modified to be included in the user's target hardware. In this way,
the provided PC host software can be used throughout the development phase.
·CHMOS is a patented Intel process.
··EBM PC, XT, AT and DOS are registered trademarks of International Business Machines Corporation.
22-24
October 1992
Order Number: 272215-001
int:eL
FEATURES
EV80C196MC FEATURES
TOTALLY CMOS BOARD
• Zero Wait-State 16 MHz Exection Speed
• 24 Kbytes of ROMsim
• Flexible Wait-State, Buswidth, Chip Select
Controller
• Totally CMOS, Low Power Board
• Concurrent Interrogation of Memory and
Registers
• Sixteen Software Breakpoints
• Two Single-Step Modes
• High-Level Language Support
• Symbolic Debug
• RS-232-C Communication Link
The EV80C196MC board is built totally with
CMOS components. Its power consumption is
therefore very low, requiring 5V at only
300 rnA. If the on-board LEDs are disabled, the
current drops to only 170 rnA. The board also
requires ± 12V.
CONCURRENT
INTERROGATION OF MEMORY
AND REGISTERS
The monitor for the EV80C196MC allows the
user to read and modify internal registers and
external memory while the user's code is
running in the board.
FULL SPEED EXECUTION
The EV80C196MC executes the user's code
from on-board ROMsim at 16 MHz with zero
wait-states. By changing crystals on the
80C196MC, any slower execution speed can be
evaluated. The board's host inteface timing is
not affected by this crystal change.
SIXTEEN SOFTWARE
BREAKPOINTS
24 Kbytes OF ROMsim
The board comes with 24 Kbytes of SRAM to
be used as ROMsim for the user's code and as
data memory if needed. 16 Kbytes of this
memory are configured as sixteen bits wide,
and 8 Kbytes are configured as eight bits wide.
The user can therefore evaluate the speed of
the part executing from either buswidth.
FLEXIBLE MEMORY
DECODING
By changing the Programmable Logic Device
(PLD) on the board, the memory on the board
can be made to look like the memory system
planned for the user's hardware application.
The PLD controls the buswidth of the
80C196MC and the chip-select inputs on the
board. It also controls the number of waitstates (zero to three) generated by the
80C196MC during a memory cycle. These
features can all be selected with 256 byte
boundaries of resolution.
There are sixteen breakpoints available which
automatically substitute a TRAP instruction
for a user's instruction at the breakpoint
location. The substitution occurs when
execution is started. Ifthe code is halted or a
breakpoint is reached, the user's code is
restored in the ROMsim.
TWO STEP MODES
There are two single-step modes available. The
first stepping mode locks out all interrupts
which might occur during the step. The second
mode enables interrupts, and treats subroutine
calls and interrupt routines as one indivisible
instruction.
HIGH·LEVEL LANGUAGE
SUPPORT
The host software for the EV80C196MC board
is able to load absolute object code generated
by ASM-96, iC-96, PL/M-96 or RL-96, all of
which are available from Intel.
22-25
intel .
FEATURES
SYMBOLIC DEBUG
PERSONAL COMPUTER
REQUIREMENTS
The host has a Single Line Assembler, and a
Disassembler, which recognize symbolics
generated by Intel software tools.
RS-232-C COMMUNICATION
LINK
The EV80C196MC communicates with the host
using an Intel 82510 UART provided on board.
The EV80C196MC Evaluation Board is hosted
on an IBM PC, XT, AT" or BIOS compatible
clone. The PC must meet the following
minimum requirements:
• 512 Kbytes of Memory
• One 360 Kbyte Floppy Disk Drive
• PC DOS" 3.1 or Later
• A Serial Port (COM1 or COM2) at 9600 Baud
• ASM-96, iC-96 or PLlM-96
• A text editor such as AEDIT
P1
,
RS·232
BUFFERS
8OC196MC
CPU
CHIP
SELECT
BUSWIDTH
READY
LOGIC
'1
I
ADDRESS
ANALOG INPUT
DIGITAL 110
ANALOG
DIGITAL
110
-M-
PORTO
PORT 1.2
HSO,HSI '
DATA
CONTROL
BT032K
X16
RAM EPROM
BT032K
X 16
RAMEPROM
BT032K
XB
RAMEPROM
82510
UART
I--
272215-2
Block Diagram of the 80C196MC Board
22-26
MCS®-51 and MCS-96
Packaging Information
23
III
int'el.
October 1991
MCS®-51 and MCS®-96
Packaging Information
Order Number: 272118-001
23-1
II
MeS-51 and MCS-96 Packaging Information
PAGE
CONTENTS
- Product Identification Codes ................................................................ 23-3
40-Lead Plastic DIP ........................................................................ 23-4
40-Lead Cerdip ............................................................................. 23-5
44-Lead QFP ............................................................................... 23-6
48-Lead Plastic DIP ........................................................................ 23-7
48-Lead Ceramic DIP ....................................................................... 23-8
64-Lead Plastic Shrink DIP ................................................................. 23-9
68-Lead LCC ........................................................................... '... 23-10
68-Lead PGA ............................................................................. 23-11
80-Lead QFP .............................................................................. 23-12
.
.
1OO-Lead PQFP ........................................................................... 23-13
44/52/68/84-Lead PLCC ................................................................. 23-14
23-2
int:eL
MCS-51 AND MCS-96 PACKAGING INFORMATION
Intel Product Identification Codes
T
Up to 15 Alphanumeric Characters
for Device Types
Up to 6 Alphanumeric Characters to
Show Customer Specific Requirements
Package Type
A
Ceramic Pin Grid Array
C
D
KU
Ceramic Dual In-Line Package
Cerdip Dual In-Line Package
Plastic Quad flatpack Package, fine Pitch, Die Up
Plastic Leaded Chip Carrier
Plastic Dual In-Line Package
I'l
P
R
Ceramic Leadless Chip Carrier
S
U
Quad flatpack Package
Plastic Dual In-Line Package (Shrink)
Q
T
Indicates extended operating temperature range (-40 0 C to +85 0 C) express product with 160 :!: 8 hr •• dynamic
burn-in.
Indicates commercial temperature range (OOC to 70°C) express product with 160:!: 8 hrs. dynamic burn-In
Indicate. extended temperature range (-40 0 C to +85 0 C) express product without burn-in.
272118-12
EXAMPLES:
NBOC196KR
LNB7C54
PLCC, 16 MHz, Commercial Temperature Range
PLCC, 12 MHz, Extended Temperature Range (Express)
23-3
MCS-51 AND MCS-96 PACKAGING INFORMATION
40-LEAD PLASTIC DUAL IN-LINE PACKAGE (TYPE N)
PIN #1
INDICATOR
AREA
-DoUn
E
272118-1
Family: Plastic Dual In-Line Package
Symbol
Millimeters Approx'
Inches Approx'
A
5
0.2
0
53
2.1
E
16
0.6
e1
2.5
0.10
L
3
0.1
"For exact dimenSions consult the Packaging Handbook (# 240800).
23-4
MCS-51 AND MCS-96 PACKAGING INFORMATION
40-LEAD CERDIP DUAL IN-LINE PACKAGE (TYPE D)
DunU
'
:
IN~~~OR
PIN 1/1
,
~
\,'
'-
E
272118-2
Family: Cerdlp Dual In-Line Package
Symbol
Millimeters Approx'
Inches Approx'
A
5.8
0.2
0
53
2.1
E
16
0.6
91
2.5
0.10
L
3
0.1
'For exact dimensions consult the Packaging Handbook (#240600).
23-5
&I
inteL
MCS-S1 AND MCS-96 PACKAGING INFORMATION
44-LEAD QUAD FLATPACK PACKAGE (TYPE S)
VARIATION: SQUARE
o
o
E
272118-3
Family: Quad Flatpack Package
Symbol
Millimeters Approx'
A
3
0
13
E
13
e1
0.8
"For exact dimenSions consult the Packaging Handbook (#240800).
23-6
infel~
MCS-51 AND MCS-96 PACKAGING INFORMATION
48-LEAD PLASTIC DUAL IN-LINE PACKAGE (TYPE N)
PIN #1
INDICATOR
AREA
-DoUn
E
272118-4
Family: Plastic Dual In-Line Package
Symbol
Millimeters Approx'
Inches Approx'
A
5
0.2
0
62
2.5
E
16
0.6
91
2.5
0.1
L
3
0.1
'For exact dimensions consult the Packaging Handbook (#240800).
23·7
int'eL
MCS-51 AND MCS-96 PACKAGING INFORMATION
48-LEAD CERAMIC DUAL IN-LINE PACKAGE (TYPE C)
ill'rn,nU
::
\
PIN {l1
INDICATOR
AREA
I
'
E
,
.
272118-5
Family: Ceramic Side Braze Dual In-Line.
-.
Symbol
Millimeters Approx'
Inches Approx'
A
6(1)
0.2(1)
A
7(2)
0.3(2)
D
62
2.5
E
16
0.6
91
2.5
0.1
L
3
0.1
NOTES:
1. Solid LID
2. EPROM LID
'For exact dimensions consult the Packaging Handbook (# 240800).
23-8
MCS-51 AND MCS-96 PACKAGING INFORMATION
64-LEAD PLASTIC DUAL IN-LINE PACKAGE (SHRINK) (TYPE U)
PIN #1
INDICATOR
AREA
-~iWW~
+-r
PLANE
SEATING
PLANE
~
~
.,~ Q
I
A
272118-6
Family: Plastic Dual In-Line Package
Symbol
Millimeters Approx'
Inches Approx'
A
6
0.3
D
59
2.3
E1
18
0.7
61
1.8
0.07
L
3
0.1
"For exact dimenSions consult the Packaging Handbook (#240800).
23-9
inteL
MCS-S1 AND MCS-96 PACKAGING INFORMATION
S8-CERAMIC LEAD LESS CHIP CARRIER (TYPE R)
VARIATION: B
r
4
C '=:1
TERMINAL #1
E
LJtr:m:mr:JlDlD:o:t:!f==*
272118-7
Family: Ceramic Leadless Chip Carrier
Symbol
Millimeters Approx'
Inches Approx'
A
3
0.1
D
25
1.0
E
25
1.0
e
1.3
0.05
L
1
0.1
• For exact dimensions consult the Packaging Handbook (# 240800).
23-10
int:eL
MCS-51 AND MCS-96 PACKAGING INFORMATION
G8-LEAD CERAMIC PIN GRID ARRAY PACKAGE (TYPE A)
SEATING
PLANE
272118-8
Family: Ceramic Pin Grid Array Package
Symbol
Millimeters Approx'
Inches Approx'
A
5
0.2
D
30
1.2
91
2.5
0.1
L
2
0.1
• For exact dimensions consult the Packaging Handbook (# 240800).
23-11
intel~
MCS-51 AND MCS-96 PACKAGING INFORMATION
SO-LEAD QUAD FLATPACK PACKAGE (TYPE S)
VARIATION: RECTANGULAR
~----------~D------------~
PIN 1
272118-9
Family: Quad Flatpack Package
Millimeters Approx·
Symbol
A
3
0
25
E
19
e1
0.8
• For exact dimensions consult the Packaging Handbook (# 240800).
23-12
inteL
MCS-51 AND MCS-96 PACKAGING INFORMATION
100-LEAD PLASTIC QUAD FLATPACK PACKAGE (TYPE KU)
A
I-
272118-10
Family: Plastic Quad Flatpack (0.025 Inch (0.635mm) Pitch)
Symbol
Description
Inches Approx'
Millimeters Approx'
A
Package Height
0.2
5
D,E
Terminal Dimension
0.9
23
'For exact dimensions consult the Packaging Handbook (#240800).
23-13
MCS-51 AND MCS-96 PACKAGING INFORMATION
42/52/68/84-LEAD PLASTIC LEADED CHIP CARRIER (TYPE N)
272118-11
Family: Plastic Leaded Chip Carrier-Square
44-Lead
Symbol
Millimeters Approx'
Inches Approx'
A
5
0.2
0
18
0.7
E
18
0.7
Family: Plastic Leaded Chip Carrier-Square
Millimeters Approx'
Symbol
68-Lead
52-Lead
Inches Approx'
84-Lead
68-Lead
52-Lead
84-Lead
A
5
5
5
0.2
0.2
0.2
0
26
21
31
1.0
0.8
1;2
E
26
21
31
1.0
0.8
1.2
"For exact dimensions consult the Packaging Handbook (# 240800).
23-14
NORTH AMERICAN SALES OFFICES
ALABAMA
GEORGIA
Intel Corp.
600 Boulevard South
Suite 104-1
tlntel Corp.
20 Technology Parkway
Suite 150
Norcross 30092
Tel: (800) 628-8686
FAX: (404) 605-9762
Huntsville 35802
Tel: (800) 628-8686
FAX: (205) 883-3511
ARIZONA
tlntal Corp.
410 North 44th Street
Suite 500
Phoenix 85008
Tel: (800) 628-8686
FAX: (602) 244-0446
CALIFORNIA
Intel Corp.
1 Sierra Gate Plaza
Suite 2Boe
Roseville 95678
Tel: (800) 628-8686
FAX: (916) 782-8153
tlntal Corp.
9665 Chesapeake Dr.
Suite 325
San Diego 92123
Tel: (800) 628-8686
FAX: (619) 292-0628
*tlntel Corp.
400 N. Tustin Avenue
Suite 450
Santa Ana 92705
Tel: (800) 628-8686
TWX: 910-595-1114
FAX: (714) 541-9157
*tlntel Corp.
San Tomas 4
2700 San Tomas Expressway
2nd Floor
Santa Clara 95051
Tel: (800) 628-8686
TWX: 910-338-0255
tlntal Corp.
15260 Ventura Boulevard
Suite 360
Sherman Oaks 91403
Tel: (800) 628-8686
FAX: (818) 995-6624
COLORADO
*tlntel Corp.
600 S. Cherry SI.
Suite 700
Denver 80222
Tel: (800) 628-8686
TWX: 910-931-2289
FAX: (303) 322-8670
CONNECTICUT
tlntal Corp.
103 Mill Plain Road
Danbury 06811
Tel: (800) 628-8686
FAX: (203) 794-0339
FLORIDA
tlntal Corp.
600 Fairway Drive
Suite 160
Deerfield Beach 3344 1
Tel: (800) 628-8686
FAX: (305) 421-2444
tlntal Corp.
5850 T .G. lee Blvd.
Suite 340
Orlando 32822
Tel: (800) 628-8686
FAX: (407) 240-8097
tSales and Service Office
*Fiald Application Location
ILLINOIS
*tlntel Corp.
Woodfield Corp. Center III
300 N. Martingale Road
Suite 400
Schaumburg 60173
Tel: (800) 628-8686
FAX: (708) 706-9762
INDIANA
tlntel Corp.
8910 Purdue Road
Suite 350
Indianapolis 46268
Tel: (800) 628-8686
FAX: (317) 875-8938
MARYLAND
·tlntel Corp.
10010 Junction Dr.
Suite 200
Annapolis Junction 20701
Tel: (800) 628-8686
FAX: (410) 206-3678
MASSACHUSETTS
*tlntel Corp.
Westford Corp. Center
5 Carlisle Road
2nd Floor
Westford 01886
Tel: (800) 628-8686
TWX: 710-343-6333
FAX: (508) 692-7867
MICHIGAN
tlntel Corp.
7071 Orchard Lake Road
Suite 100
West Bloomfield 48322
Tel: (800) 628-8686
FAX: (313) 851-8770
MINNESOTA
tlntal Corp.
3500 W. 80th SI.
Suite 360
Bloomington 55431
Tel: (800) 628-8686
TWX: 910-576-2867
FAX: (612) 831-6497
*tlntel Corp.
2950 Express Dr., South
Suite 130
Islandia 11722
Tel: (800) 628-8686
TWX: 510-227-6236
FAX: (516) 348-7939
tlntel Corp.
300 Westage Business Center
Suite 230
Fishkill 12524
Tel: (800) 628-8686
FAX: (914) 897-3125
*tlntel Corp.
20515 SH 249
Suite 401
Houston 77070
Tel: (800) 628-8686
TWX: 910-881-2490
FAX: (713) 988-3660
UTAH
OHIO
·tlntel Corp.
3401 Park Center Drive
Suite 220
Dayton 45414
Tel: (800) 628-8686
TWX: 810-450-2528
FAX: (513) 890-8658
·'nte, Corp.
Four Commerce Park Square
~~~~~;~;J~~ l~~d.,
*tlntel Corp.
12000 Ford Road
Suite 400
Dallas 75234
Tel: (800) 628-8686
FAX: (214) 484-1180
SUite 600
Tel: (800) 628-8686
FAX: (216) 464-2270
OKLAHOMA
Intel Corp.
6801 N. Broadway
Suite 115
.
Oklahoma City 73162
Tel: (800) 628-8686
FAX: (405) 840-9819
OREGON
tlntel Corp.
15254 N.W. Greenbrier Pkwy.
Building B
Beaverton 97006
Tel: (800) 628-8686
TWX: 910-467-8741
FAX: (503) 645-8181
PENNSYLVANIA
·tlntel Corp.
925 Harvest Drive
Suite 200
Blue Bell 19422
Tel: (800) 628-8686
FAX: (215) 641-0785
tlntel Corp.
428 East 6400 South
Suite 104
Murray 84107
Tel: (800) 628-8686
FAX: (801) 268-1457
WASHINGTON
tlntel Corp.
2800 156th Avenue 5£
Suite 105
Bellevue 98007
Tel: (800) 628-8686
FAX: (206) 746-4495
Intel Corp.
408 N. Mullan Road
Suite 105
Spokane 99206
Tel: (800) 628-8686
FAX: (509) 928-9467
WISCONSIN
Intel Corp.
400 N. Executive Dr.
Suite 401
Brookfield 53005
Tel: (800) 628-8686
FAX: (414) 789-2746
CANADA
BRITISH COLUMBIA
Intel Semiconductor of
Canada, ltd.
999 Canada Place
Suite 404, #11
Vancouver V6C 3E2
Tel: (800) 628-8686
FAX: (604) 844-2813
ONTARIO
;b'3t~~~~rBenter
tlntal Semiconductor of
Canada, Ltd.
2650 Queensview Drive
Suite 250
Ottawa K2B SH6
Tel: (800) 628-8686
FAX: (613) 820-5936
tlntel Semiconductor of
Canada, Ltd.
190 Attwell Drive
Suite SOD
Rexdale M9W 6H8
Tel: (800) 628-8686
FAX: (416) 675-2438
Blvd.
Suite 610
Pittsburgh 15235
Tel: (800) 628-8686
FAX: (412) 829-7578
NEW JERSEY
SOUTH CAROLINA
·tlnte1 Corp.
Lincroft Office Center
125 Half Mile Road
Red Bank 01701
Tel: (800) 628-8686
FAX: (908) 747-0983
Intel Corp.
100 Executive Center Drive
Suite 109,8183
Greenville 29615
Tel: (800) 628-8686
FAX: (803) 297-3401
NEW YORK
TEXAS
·'nte'
tlntel Corp.
8911 N. Capital of Texas Hwy.
Suite 4230
Austin 78759
Tel: (800) 628-8686
FAX: (512) 338-9335
QUEBEC
Corp.
850 Crosskeys Office Park
Fairport 14450
Tel: (800) 628-8686
TWX: 510-253-7391
FAX: (716) 223-2561
tlntel Semiconductor of
Canada, Ltd.
1 Rue Holiday
Suite 115
Tour East
Pl. Claire H9R 5N3
Tel: (800) 628-8686
FAX: 514-694-0064
CG/SALEl101992
NORTH AMERICAN DISTRIBUTORS
ALABAMA
Arrow/Schwaber Electronics
Avnet Computer
1361 B Wes1190th Stre.,
Gardena 90248
Tel: (310)217-6630
FAX: (310) 327-53B9
Hamiiton/Avnet
Avnet Computer
1175 Bordeaux Drive
Sunnyvale 94089
Tel: (406) 743-3454
FAX: (406) 743-3346
1015 Henderson Road
Huntsville 35816
Tel: (205) 637-6955
FAX: (205) 695-0126
4960 Corporate Drive, #135
Huntsville 35805
Tel: (205) 637-7210
FAX: (205) 630-B404
~9T~oSes~~prg~a~:~~, #120
Huntsville 35805
Tel: (205) 830-9526
FAX: (205) B30-9557
Pioneer Technologies Group
4635 Universl1y Square, #5
Huntsville 35816
Tel: (205) B37-9300
FAX: (205) B37-9356 ,
ARIZONA
Arrow/Schwaber Electronics
2415 W. Erie Drive
Tempe 652B2
Tel: (602) 431-0030
FAX: (602) 431-9555
Avnet Computer
1626 S. Edwards Drive
Tempe 652B1
Tel: (602) 902-4642
FAX: (602) 902-4646
Hamilton/Avnet
1626 S. Edwards Drive
Tempe 652B1
Tel: (602) 902-4700
FAX: (602) 902-4747
Wyle Laboratories
Hamllton/Avnet
3170 Pullman Street
Costa Mesa 92626
Tel: (714) 641-4182
FAX: (714) 641-4149
Hamilton/Avnet
1175 Bordeaux Drive
Sunnyvale 94069
Tel: (408) 743-3300
FAX: (406) 745-6679
Hamilton/Avnet
~~5oy!e~r~~t2~venue
Tel: (61~ 571-7540
FAX: (619) 277-6136
Hamilton/Avnet
21150 Callfa St
Woodland Hills 91367
Tel: (616) 594-0404
FAX: (616) 594-6233
Hamilton/Avnet
755 Sunrise Avenue, #150
Roseville 95661
Tel: (916) 925-2216
FAX: (916) 925-3476
Pioneer Technologies Group
134 Rio Robles
San Jose 95134
Tel: (408) 954-9100
FAX: (408) 954-9113
4141 E. Raymond
Phoenix 85040
Tel: (602) 437-20B6
FAX: (602) 437-2124
Ploneer'Standard
217 Technology Dr., #110
Irvine 92718
Tel: (714) 753-5090
FAX: (714) 753-5074
CALIFORNIA
Pioneer Standard
5650 Canoga Ave" #400
Woodland Hills 91367
Tel: (616) 883-4640
FAX: (616) 683-9721
Arrow Commercial Systems Group
1502 Crocker Avenue
Hayward 94544
Tel: (510) 4B9-5371
FAX: (510) 391-1742
Arrow Commercial Systems Group
14242 Chambers Road
Tustin 92680
Tel: (714) 544-0200
FAX: (714) 454-4203
Arrow/Schwaber Electronics
26707 W. Agoura Road
Calabasas 91302
Tel: (616) 6BO-9666
FAX: (616) 660-4667
Arrow/Schwaber Electronics
9511 Ridgehaven Court
~:I~ ~If~o5~~~£:00
FAX: (619) 279-0662
Arrow/Schweber Electronics
1180 Murphy Avenue
San Jose 95131
Tel: (408) 441-9700
FAX: (406) 453-4610
Wyle Laboratories
2951 Sunrise Blvd., #175
Rancho Cordova 95742
Tel: (916) 83B-5262
FAX: (916) 636-1491
Wyle Laboratories
9525 Chesapeake Drive
San Diego 92123
Tel: (619) 565-9171
FAX: (619) 365-0512
Wyle Laboratories
3000 Bowers Avenue
Santa Clara 95051
Tel: (408) 727-2500
FAX: (406) 727-7359
Wyle Laboratories
17872 Cowan Avenue
Irvine 92714
Tel: (714) 663-9953
FAX: (714) 251-0365
Wyle Laboratories
26010 Mureau Road, #150
CsIabasas 91302
Tel: (818) 980-9000
FAX: (616) 860-5510
Wyle Laboratories
451 E. 124th Avenue
Thornton 80241
Tel: (303) 457-9953
FAX: (303) 457-4631
Hamilton/Avnet
3425 Corporate Way, #G
Duluth 30136
rei: (404) 623-5475
FAX: (404) 623-5490
CONNECTICUT
Pioneer Technologies Group
4250 C. Rivergreen Parkway
Dulu1h 30136
Tel: (404) 623-1003
FAX: (404) 623-0665
Arrow/Schweber Electronics
12 Beaumont Road
Wallingford 06492
Tel: (203) 265-7741
FAX: (203) 265-7986
Avnet Computer
55 Federal Road, #103
Danbury 06810
Tel: (203) 797-26BO
FAX: (203) 791-2696
Hamllton/Avnet
55 Federal Road, #103
Danbury 06610
Tel: (203) 743-9799
FAX: (203) 797-0373
Pioneer·Standard
2 Trap Falls Rd" #101
Shelton 06484
Tel: (203) 929-5600
FAX: (203) 929-9791
FLORIDA
Arrow/Schweber Electronics
400 Fairway Drive, #102
Deerfield Beach 33441
Tel: (305) 429-6200
FAX: (305) 426-3991
Arrow/Schweber Electronics
~k~~~~~~~:6#3101
Tel: (407) 333-9300
FAX: (407) 333-9320
Avnet Computer
541 S, Orlando Ave" #203
Mal11an 32751
Tel: (407) 539-26B6
FAX: (407) 539-2065
Hamllton/Avnet
5371 N,W, 33rd Ave" #204
Ft Lauderdale 33309
Tel: (305) 733-6300
FAX: (305) 464-6369
Hamllton/Avnet
3247 Tech Drive
St. Petersburg 35805
Tel: (813) 573-4346
FAX: (613) 572·0633
Hamilton/Avnet
7079 University Boulevard
Winter Park 32792
Tel: (407) 657-3300
FAX: (407)676-4414
Pioneer Technologies Group
337 Northlake Blvd" #1000
Alta Monte Springs 32701
~'j&}(U~Nj4~ggg5
:~~n~~rM~~~~~~awes Group
Deerfield Beach 33442
Tel: (305) 426-6677
FAX: (305) 481-2950
ILLINOIS
Arrow/Schweber Electronics
1140 W. Thorndale Rd.
Itasca 60143
Tel: (706) 250·0500
FAX: 708-250-0916
Avnet Computer
1124 Thorndale Avenue
Bensenville 60106
Tel: (708) 860-6573
FAX: (706) 773-7976
Hamllton/Avnet
1130 Thorndale Avenue
Bensenville 60106
Tel: (708) 660-7700
FAX: (706) 660-6532
MTI Systems
1140 W. Thorndale Avenue
11asca 60143
Tel: (706) 250-6222
FAX: (706) 250,6275
Pioneer·Standard
2171 'Executive Dr., #200
Addison 60101
Tel: (708) 495-9660
FAX: (708) 495-9631
INDIANA
Arrow/Schwaber Electronics
7108 Lakeview Parkway West Dr.
Indianapolis 46268
Tel: (317) 299-2071
FAX: (317) 299-2379
Avnet Computer
655 W, Carmel Dr" #120
Carmel 46032
Tel: (317) 575-6029
FAX: (317) 844-4964
Hamilton/Avnet
485 Gradls Drive
Carmel 46032
Tel: (317) 644-9533
FAX: (317) 844-5921
Pioneer-Standard
9350 Priority Way West Or.
Indianapolis 46250
Tel: (317) 573-0660
FAX: (317) 573-0979
IOWA
Hamilton/Avnet
2335A Blalrsferry Rd" N,E,
Cedar Rapids 52402
Tel: (319) 362-4757
FAX: (319) 393-7050
GEORGIA
KANSAS
Arrow/Schweber Electronics
9801 Legler Road
Lenexa 66219
Tel: (913) 541-9542
FAX: (913) 752-2612
COLORADO
Arrow Commercial Systems Group
3400 C. Corporate Way
Dulu1h 30136
Tel: (404) 623-6625
FAX: (404) 623-8602
Arrow/Schweber Electronics
6 Cromwell, Suite 100
Irvine 92718
Tel: (714) 836-5422
FAX: (714) 454-4203
Arrow/Schweber Electronics
61 Inverness Or. East, #105
Englewood 80112
Tel: (303) 799-0256
FAX: (303) 799-4303
Arrow/Schweber Electronics
4250 E. Rivergreen Pkwy., #E
Dulu1h 30136
Tel: (404) 497-1300
FAX: (404) 476-1493
Avnet Computer
15313 W. 95th Street
Lenexa 61219
Tel: (913) 541-7989
FAX: (913) 541-7904
Avnet Computer
3170 Pullman Street
Costa Mesa 92626
Tel: (714) 641-4179
FAX: (714) 641-4170
Hamilton/Avnet
9605 Maroon Circle, #200
Englewood 80112
Tel: (303) 799-7600
FAX: (303) 799-7601
Avnet Computer
3425 Corporate Way, #G
Duluth 30136
Tel: (404) 623-6400
FAX: (404) 476-0125
Hamilton/Avnet
15313 W. 95th Street
Overland Park 66215
Tel: (913) 868-1055
FAX: (913) 541-7951
Arrow/Schweber Electronics
46834 Kato Rd., Suite 103
Fremont 94538
Tel: (510) 440-2661
FAX: (510) 490-1064
CG/SALE/101992
NORTH AMERICAN DISTRIBUTORS (Cpntd.)
KENTUCKY
Hamilton/Avne!
1847 Mercer Rd., #G
Lexington 40511
Tel: (606) 288-4911
FAX: (606) 288-4936
MARYLAND
Arrow/Schweber Electronics
9800J Patuxent Woods Dr.
Columbia 21046
Tel: (301) 596-7800
FAX: (301) 596-7821
Arrow Commercial Systems Group
200 Perry Parkway
Gaithersburg 20877
Tel: (301) 670-1600
FAX: (301) 670-0188
Avne! Computer
7172 Columbia Gateway Dr.
Columbia 21046
Tel: (301) 995-3571
FAX: (301) 995-3515
Hamilton/Avne!
7172 Columbia Gateway Dr.• #F
Columbia 21046
Tel: (301) 995-3554
FAX: (301) 995-3553
*North Atlantic Industries
Systems Division
7125 River Wood Dr.
Columbia 21046
Tel: (301) 312·5800
FAX: (301) 312-5850
Pioneer Technologies Group
9100 Gaither Road
Gaithersburg 20877
Tel: (301) 921-0660
FAX: (301) 921-4255
MASSACHUSETTS
Arrow Commercial Systems Group
250 Upton Drive
Wilmington 01887
Tel: (508) 658-7100
FAX: (508) 658-0977
Arrow/Schweber Electronics
25 Upton Dr.
Wilmington 01887
Tel: (508) 658-0900
FAX: (508) 694-1754
Avne! Computer
100 Centennial Drive
Peabody 01960
Tel: (508) 532-9822
FAX: (508) 532-9887
Hamilton/Avnet
10 0 Centennial Drive
Peabody 01960
Tel: (508) 531-7430
FAX: (508) 532-9802
Pioneer-Standard
44 Hartwell Avenue
Lexington 02173
Tel: (617) 861-9200
FAX: (617) 863-1547
Wyle Laboratories
15 Third Avenue
Burlington 01803
Tel: (617) 272-7300
FAX: (617) 272-6809
MICHIGAN
Arrow/Schweber Electronics
19880 Haggerty Road
Livonia 48152
Tel: (800) 231-7902
FAX: (313) 462-2686
Hamilton/Avnet
41650 Garden Brook Rd., #100
Novi 48375
Tel: (313) 347-4270
FAX: (313) 347-4021
Pioneer-Standard
13485 Stamford Ct.
Livonia 48150
Tel: (313) 525-1800
FAX: (313) 427-3720
MINNESOTA
ArrowfSchweber Electronics
10100 Viking Drive, #100
Eden Prairie 55344
Tel: (612) 941-5280
FAX: (612) 829-8007
Avnet Computer .
9800 Bren Road, East
Minnetonka 55343
Tel: (612) 829-0025
FAX: (612) 944-0638
Hamilton/Avnet
9800 Bren Road, East, #410
Minnetonka 55343
Tel: (612) 932-0600
FAX: (612) 932-0613
Pioneer-Standard
7625 Golden Triange Dr., #G
Eden Prairie 55344
Tel: (612) 944-3355
FAX: (612) 944-3794
MISSOURI
Arrow/Schweber Electronics
2380 Schuetz Road
St. Louis 63146
Tel: (314) 567-6888
FAX: (314) 567-1164
Avnet Computer
741 Goddard Avenue
Chesterfield 63005
Tel: (314) 537-2725
FAX: (314) 537-4248
Hamilton/Avnet
741 Goddard
Chesterfield 63005
Tel: (314) 537-4265
FAX: (314) 537-4248
NEW HAMPSHIRE
Avnet Computer
2 Executive Park Drive
Bedford 03102
Tel: (800) 442-8638
FAX: (603) 624-2402
NEW JERSEY
Arrow/Schweber Electronics
4 East Stow Rd., Unit 11
Marlton 08053
Tel: (609) 596-8000
FAX: (609) 596-9632
Arrow/Schweber Electronics
43 Route 46 East
Pine Brook 07058
Tel: (201) 227-7880
FAX: (201) 227-2064
Avnet Computer
1B Keystone Ave., Bldg. 36
Cherry Hill 08003
Tel: (609) 424-8962
FAX: (609) 751-2502
. Hamilton/Avnet
1 Keystone Ave., Bldg. 36
Cherry Hill 08003
Tel: (609) 424-0110
FAX: (609) 751-2611
Pioneer-Standard
14A Madison Rd.
Fairfield 07004
Tel: (201) 575-3510
FAX: (201) 575-3454
NORTH CAROLINA
NEW MEXICO
Arrow/Schweber Electronics
5240 Greensdairy Road
Raleigh 27604
Tel: (919) 876-3132
FAX: (919) 878-9517
Alliance Electronics, Inc.
10510 Research Ave., SE
Albuquerque 87123
Tel: (505) 292-3360
FAX: (505) 275-6392
Avnet Computer
2725 Millbrook Rd., #123
Raleigh 27604
Tel: (919) 790-1735
FAX: (919) 872-4972
Avnet Computer
7801 Academy Rd., SE
Bldg. 1, Suite 204
Albuquerque 87109
Tel: (505) 828-9722
FAX: (505) 828-0364
Hamilton/Avnet
5250-77 Center Dr. #350
Charlotte 28217
Tel: (704) 527-2485
FAX: (704) 527-8058
Hamilton/Avnet
7801 Academy Rd., NE
Bldg. 1, Suite 204
Albuquerque 87108
Tel: (505) 828-1058
FAX: (505) 828-0360
NEW YORK
Arrow/Schweber Electronics
3375 Brighton Henrietta Townline Rd.
Rochester 14623
Tel: (716) 427-0300
FAX: (716) 427-0735
Arrow/Schweber Electronics
20 Oser Avenue
Hauppauge 11788
Tel: (516) 231-1000
FAX: (516) 231-1072
Avnst Computer
933 Motor Parkway
Hauppauge 11788
Tel: (516) 434-7443
FAX: (516) 434-7459
Avnet Computer
2060 Townline Rd.
Rochester 14623
Tel: (716) 272-9110
FAX: (716) 272-9685
Hamilton/Avnet
3510 Spring Forest Drive
Raleigh 27604
Tel: (919) 878-0819
FAX: (919) 954-0940
~~oo~eL~S~eu~~~~~o~l~: ~l~~P
Charlotte 28273
Tel: (704) 527-8188
FAX: (704) 522-8564
~~~~e~e~i~~~~~~~~~~r~~~8
Durham 27713
Tel: (919) 544-5400
FAX: (919) 544-5885
OHIO
Arrow Commercial Systems Group
284 Cramer Creek Court
Dublin 43017
Tel: (614) 889-9347
FAX: (614) 889-9680
Arrow/Schweber Electronics
6573 Cochran Road, #E
Solon 44139
Tel: (216) 248-3990
FAX: (216) 248-1106
Hamilton/Avnet
933 Motor Parkway
Hauppauge 11788
Tel: (516) 231-9800
FAX: (516) 434-7426
ArTOw/Schweber Electronics
8200 Washington Village Dr.
Centerville 45458
Tel: (513) 435-5563
FAX: (513) 435-2049
Arrow Commercial Systems Group
120 Commerce
Hauppauge 11788
Tel: (516) 231-1175
FAX: (516) 435-2389
Avnet Computer
7764 Washington Village Dr.
Dayton 45459
Tel: (513) 439-6756
FAX: (513) 439-6719
Hamilton/Avnet
2060 Townline Rd.
Rochester 14623
Tel: (716) 475-9130
FAX: (716) 475-9119
Avnet Computer
2 Summit Park Dr., #520
Independence 44131
Tel: (216) 573-7400
FAX: (216) 573-7404
Hamilton/Avnet
103 Twin Oaks Drive
Syracuse 13120
Tel: (315) 453-4000
FAX: (315) 453-4010
Hamilton/Avnet
7760 Washington Village Dr.
Dayton 45459
Tel: (513) 439-6633
FAX: (513) 439-6711
MTI Systems
1 Penn Plaza
250 W. 34th Street
New York 10119
Tel: (212) 643-1280
FAX: (212) 643-1288
Hamilton/Avnet
2 Summit Park Dr., #520
Independence 44131
Tel: (216) 573-7400
FAX: (216) 573-7404
Pioneer-Standard
68 Corporate Drive
Binghamton 13904
Tel: (607) 722-9300
FAX: (607) 722-9562
MTI Systems Sales
23404 Commerce Park Rd.
Beachwood 44122
Tel: (216) 464-6688
FAX: (216) 464-3564
Avnet Computer
41650 Garden Brook Rd. #120
Novi 48375
Tel: (313) 347-4067
FAX: (313) 347-1820
Hamilton/Avnet
10 Lanldex Plaza West
Parsippany 07054
Tel: (201) 515-5300
FAX: (201) 515-1600
Pioneer-Standard
60 Crossway Park West
Woodbury, Long Island 11797
Tel: (516) 921-8700
FAX: (516) 921-2143
Pioneer-Standard
4433 Interpoint Boulevard
Dayton 45424
Tel: (513) 236-9900
FAX: (513) 236-8133
Hamilton/Avnet
2876 28th Street, S.W., #5
Grandville 49418
Tel: (616) 531-0345
FAX: (616) 531-0059
MTI Systems Sales
43 US Rt 46
Pine brook 07058
Tel: (201) 882-8780
FAX: (201) 882-8901
Pioneer-Standard
840 Fairport Park
Fairport 14450
Tel: (716) 381-7070
FAX: (716) 381-8774
Pioneer-Standard
4800 E. 131 st Street
Cleveland 44105
Tel: (216) 587-3600
FAX: (216) 663-3906
*Se11 Certified Small Business per Federal Acquisition Regulations
CG/SALE/l01992
NORTH AMERICAN DISTRIBUTORS (Contd.)
OKLAHOMA
Avnet Computer
Arrow/Schwaber electronics
12111 East 51st Street, #101
Houston 77008
Arrow Commercial Systems Group
14360 S.E. Eastgate Way
BeUevue 98007
Zentronics
11400 Bridgeport Rd., #108
Richmond V6X 1T2
Tel: (713) 867-7580
FAX: (713) 861-6851
Tel: (206) 643-9992
FAX: (206) 643-9709
Tel: (604) 273-5575
FAX: (604) 273-2413
Hamilton/Avnet
Hamilton/Avnet
ONTARIO
Tel: (512) 832·4306
FAX: (512) 832·4315
Tel: (206) 241-8555
FAX: (206) 241·5472
Hamilton/Avnet
4004 Beltline, Suite 200
Dallas 75244
Avnet Computer
17761 N.E. 78th Place
Redmond 96052
Tulsa 74146
Tel: (918) 252-7537
FAX: (918) 254-0917
Hamilton/Avnet
12121 E. 51s1 St., #102A
Tulsa 74146
Tel: (918) 252-7297
FAX: (918) 250-8763
OREGON
Almae/Arrow electronics
1885 N.w. 1691h Place, #106
Beaverton 97006
Tel: (503) 629·8090
FAX: (503) 645·0611
Arrow Commercial Systems Group
1885 N.W. 1691h Place
Beaverton 97006-7312
Tel: (503) 629·8090
FAX: (503) 645·0611
Avnst Computer
9150 Southwest Nimbus Ave.
Beaverton 97005
Tel: (503) 627-0900
FAX: (503) 526·6242
Hamilton/Avnet
9409 Southwest Nimbus Ave.
Beaverton 97005
Tel: (503) 627·0201
FAX: (503) 641-4012
Wyle Laboratories
9640 Sunshine Court
Bldg. G, Suite 200
Beaverton 97005
Tel: (503) 643·7900
FAX: (503) 646-5466
PENNSYLVANIA
Avnet Computer
213 Executive Drive, #320
Mars 16046
Tel: (412) 772-1888
FAX: (412) 772-1890
Hamilton/Avnet
213 Executive, #320
Mars 16046
Tel: (412) 772-1881
FAX: (412) 772·1690
Pioneer·Standard
259 Kappa Drive
Pittsburgh 15238
Tel: (412) 782-2300
FAX: (412) 963·8255
Pioneer Technologies Group
500 Enterprise Road
Keith Valley Business Center
Horsham 19044
1235 North Loop WeS1, #525
1826·F Kramer Lane
Austin 78756
Tel: (214) 308-8105
FAX: (214) 308·8141
Hamilton/Avnet
1235 North Loop West, #521
Houston 77008
Wyle Laboratories
15385 N.E. 901h Streel
Redmond 98052
Pioneer-Standard
18260 Kramer Lane
Austin 78758
WISCONSIN
Tel: (512) 835-4000
FAX: (512) 835-9829
Pioneer-Standard
13785 Beta Road
Dallas 75244
Tel: (214) 263-3168
FAX: (214) 490-6419
Pioneer-Standard
10530 Rockley Road, #100
Houston 77099
Tel: (713) 495-4700
FAX: (713) 495·5642
Wyle Laboratories
1810 Greenville Avenue
Richardson 75081
Tel: (214) 235-9953
FAX: (214) 6~4.5064·
Arrow/Schweber Electronics
200 N. Patrick Blvd., #100
Brookfield 53045
Tel: (414) 792-0150
FAX: (414) 792-0156
Avnet Computer
20875 Crossroads Circle, #400
Waukesha 53186
Tel: (414) 784·8205
FAX: (414) 784-6006
Hamllton/Avnet
28875 Crossroads Circle, #400
Waukesha 53186
Tel: (414) 784·4511
FAX: (414) 784-9509
Pioneer-Standard
120 Bishop Way #163
Brookfield 53005
Wyle Laboratories
4030 West Braker Lane, #420
Austin 78759
Tel: (414) 784·3480
FAX: (414) 784·8207
Tel: (512) 345-8853
FAX: (512) 345-9330
ALASKA
Wyle Laboratories
11001 South Wilcrest, #100
Houston 77099
Tel: (713) 879·9953
FAX: (713) 879-4069
Avnet Computer
1400 West Benson Blvd., #400
~~I~~~h~~e2~~~~8399
FAX: (907) 277-2639
UTAH
Arrow/Schweber Electronics
1946 W. Parkway Blvd.
Sal1 Lake Cily 84119
Tel: (801) 973-6913
FAX: (801) 972-0200
Avnet Computer
TEXAS
Hamilton/Avnet
Arrow/Schweber Electronics
10899 Kinghurst Dr., #100
Houston 77099
Tel: (206) 867-0160
FAX: (206) 867·0161.
Tel: (206) 881·1150
FAX: (206) 881-1567
Tel: (215) 674-4000
FAX: (215) 674-3107
Tel: (214) 380·6464
FAX: (214) 248·7208
Aedmonq 98052
Tel: (713) 861-8517
FAX: (713) 861-6541
1100 E. 6600 South, #150
Sail Lake Cily 64121
Tel: (801) 266-1115
FAX: (801) 266-0362
Arrow/Schweber Electronics
3220 Commander Drive
Carrollton 75006
17761 N.E. 781h Place, #C
1100 Eas16600 Soulh, #120
Salt Lake Cily 84121
Tel: (801) 972-2800
FAX: (801) 263-0104
Wyle Laboratories
1325 West 2200 South, #E
West Valley 84119
Tel: (801) 974·9953
FAX: (801) 972-2524
CANADA
ALBERTA
Avnet Computer
1081144 29th Ave., NE
Calgary T2E 7Pl
Tel: (403) 291·3284
FAX: (403) 250-1591
Zentronics
6815 8th Street N.E., #100
Calgary T2E 7H7
Arrow Commercial Systems Group
1093 Meyerside Dr" Unit 2
Mississauga, Ontario
LST lM4
Tel: (416) 670-7784
FAX: (416) 670-7781
Arrow/Schwaber electronics
36 Antares Dr., Unit 100
Nepean K2E 7W5
Tel: (613) 226·6903
FAX: (613) 723·2018
Arrow/Schweber Electronics
1093 Meyerside, Unit 2
Mississauga L5T 1M4
Tel: (416) 670·7769
FAX: (416) 670·7781
Avnst Computer
151 Superior Blvd.
Mississuaga LST 2L 1
Tel: (416) 795-3895
FAX: (416) 795-3855
Avnet Computer
190 Colonnade Road
Nepean K2E 7J5
Tel: (613) 727-2000
FAX: (613) 727-2020
Hamilton/Avnet
151 Superior Blvd.
Mississauga LST 2L 1
Tel: (416) 795-3835
FAX: (416) 564-6036
Hamilton/Avnet
190 Colonnade Road
Nepean K2E 7J5
Tel: (613) 226-1700
FAX: (613) 226-1184
Zentronlcs
1355 Meyerside Drive
Mississauga LST lC9
Tel: (416) 564-9600
FAX: (416) 564·8320
Zentronics
155 Colonnade Rd., South
Unit 17/18
Nepean K2E 7Kl
Tel: (613) 226-6840
FAX: (613) 226·6352
QUEBEC
Arrow/Schweber Electronics
1100 St. Regis Blvd.
Dorval H9P 2T5
Tel: (514) 421-7411
FAX: (514) 421-7430
Arrow Commercial Systems Group
500 Ave Street Jean Baptiste
Quebec City 2GE 5R9
Tel: (416) 871·7500
FAX: (418) 871-6816
Tel: (403) 295-8838
FAX: (403) 295-8714
Avnet Computer
2795 Rue Halpern
SI. Laurent H4S 1P8
BRITISH COLUMBIA
Tel: (514) 335-2483
FAX: (514) 335-2490
Almae-Arrow Electronics
8544 Baxter Place
Burnaby V5A 4T8
Hamilton/Avnet
2795 Rue Halpern
SI. Laurent H4S 1P8
Tel: (713) 530-4700
FAX: (713) 568-8518
WASHINGTON
Tel: (604) 421·2333
FAX: (604) 421-5030
Avnet Computer
4004 BeJtline, Suite 200
Dallas 75244
Almae/Arrow Electronics
14360 S.E. Eastgate Way
Bellevue 98007
Hamilton/Avnet
8610 Commerce Court
Burnaby V5A 4N6
Zentronics
520 McCaffrey Street
S1. Laurent H4T 1Nl
Tel: (214) 308-8168
FAX: (214) 308·8129
Tel: (206) 643-9992
FAX: (206) 643·9709
Tel: (604) 420-4101
FAX: (604) 420·5376
Tel: (514) 737·9700
FAX: (514) 737·5212
Tel: (514) 335·1000
FAX: (514) 335-2481
CG/SALE/l01992
UNITED STATES
Intel Corporation
2200 Mission College Boulevard
P.O. Box 58119
Santa Clara, CA 95052-8119
JAPAN
Intel Japan K.K.
5-6 Tokodai, Tsukuba-shi
Ibaraki, 300-26
FRANCE
Intel Corporation S.A.R.L.
1, Rue Edison, BP 303
78054 Saint-Quentin-en-Yvelines Cedex
UNITED KINGDOM
Intel Corporation (U.K.) Ltd.
Pipers Way
Swindon
Wiltshire, England SN3 lRJ
GERMANY
Intel GmbH
Domacher Strasse 1
8016 Feldkirchen bei Muenchen
HONG KONG
Intel Semiconductor Ltd.
10/F East Tower
Bond Center
Queensway, Central
CANADA
Intel Semiconductor of Canada, Ltd.
190 Attwell Drive, Suite 500
Rexdale, Ontario M9W 6H8
CG/020392
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