1993_Intel_Memory_Products 1993 Intel Memory Products

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lNlEL.

Founded in 1968 to pursue the integration of large numbers of
transistors onto tiny silicon chips, Intel's history has been marked by
a remarkable number of scientific breakthroughs and innovations. In
1971, Intel introduced the 4004, the first microprocessor. Containing
2300 transistors, this first commercially-available computer on a chip
~~s considered primitive compared with today's million-plus transistor
products.
Innovations such as the microprocessor, the erasable programmable read-only memory (EPROM) and the dynamic random access
memory (DRAM) revolutionized electronics by making integrated
circuits the mainstay of both consumer and business computing
products.
Over the last two and a half decades, Intel's business has
evolved arid today the company's focus is on delivering an extensive
line of component, module and system-level building block products
to the computer industry. The company's product line covers a broad
spectrum, and includes microprocessors, flash memory, microcontrollers, a broad line of PC enhancement and local area network
products, multimedia technology products, and massively parallel
supercomputers. Intel's 32-bit X86 architecture, represented by the
Intel386™ and Intel486™ microprocessor families, are the de facto
standard of modern business computing and installed in millions of
PCs worldwide.
Intel has over 25,000 employees located in offices and manufacturing facilities around the world. Today, Intel is the largest semiconductor company in the United States and the second largest in the
world.

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'CG/092792

MEMORY PRODUCTS

1993

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for a~y errors which may
appear in this document nor does it make a commitment to update the Information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
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CHMOS and HMOS are patented processes of Intel Corp.
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©INTEL CORPORATION 1993

CG·110392

int:et
DATA SHEET DESIGNATIONS
Intel uses various data sheet markings to designate each phase of the document as it
relates to the product. The marking appears in the upper, right-hand corner of the data
shlnnect signals. (The lower the capacitance,
the higher the inherent speed of the device.) The
glass layer is then/patterned with contact holes and
placed in a high 'temperature furnace. This furnace
step smooths the glass surface and rounds the contact edges to provide uniform metal coverage. Metal
(usually aluminum or aluminum/silicon) is then depOSited on the wafer and the interconnect patterns·
and external bonding pads are defined and etched
(Figure 6). The wafers then receive a low temperature (approximately 500'C) alloy that insures good
ohmic contact between the aluminum and· diffusion
or poly.

296102-9
EPROM/FLASH MEMORY CELL

Figure 7. Double Poly Structure
After fabrication is complete, the wafers are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will op~rate properly both at low temperature and at conditions found in actual, operation. Circuits that fail
these tests are inked to distinguish them from good
circuits. From here the wafers are sent from assembly where they are sawed into individual circuits with
a paper-thin diamond blade. The inked circuits are
then separated out and the good Circuits are sent on
for packaging.
Packages fall into two categories-hermetic and
non-hermetic. Hermetic packages are Cerdip, where
two ceramic halves are sealed with a glass fritt, or
ceramic with soldered metal lids. An example of hermetic package assembly is shown in Table 1. Nonhermetic packages are molded plastics.
The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal lid. The base is placed on a heater block and a
metal alloy preform is inserted. The die is placed on
top of the preform which bonds it to the package.
Once attached, wires are bonded to the circuit and
then connected to the leads. Finally the package is
placed in a dry inert atmosphere and the lid is soldered on.

296102-8

Flgure.6. Complete Circuit (without passivation)
At this point the circuit is fully operational, however,
the top metal layer is very soft and easily damaged
by handling. The device is also susceptible to contamination or attack from moisture. To prevent this
the wafers are sealed with a passivation layer of silicon nitride or a silicon and phosphorus oxide composite. Patterning is done for the last time opening
up windows only over the bond pads where external
connections will be made.

The cerdip package consists of a base, lead frame,
and lid. The base is placed on a heater block and
the lead frame placed on top. This sets the lead
frame in glass attached to the base. The die is then
attached and bonded to the leads. Finally the lid is
placed on the package and it is. inserted in a seil!
furnace where the glass on the two halves melt together making a hermetic package.

This completes basic fabrication sequence for a single poly layer process. Double poly processes such
as those used for high density Dynamic RAMs,
EPROMs, flash memories, and EEPROMs follow the
same general process flow with the addition of gate,
poly deposition, doping, and interlayer dielectric process modules required for the additional poly layer
(Figure 7). These steps are performed right after the
active areas have been defined (Figure 3) providing
the capacitor or floating gate storage nodes on
those devices.

In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead
frame and bonded out to the leads with gold wires.
The frame then goes to an injection molding machine and the package is formed around the lead
frame. After mold the excess plastic is removed and
the leads trimmed.

1-3

INTEL MEMORY TECHNOLOGIES

After assembly, the individual circuit!! are retested at
an elevated operating temperature to assure critical
operating parameters and separated according to
speed and power consumption into individual specification groups. The finished circuits are marked and
then readied for shipment.

PHOTOLITHOGRAPHY
The photo or masking technology is the most impor-.
tant part of the manufacturing flow if for no other
reason than the number of times it is applied to each
wafer. The manufacturing proce~s gets more complex in order to make smaller and higher performance circuits. As this happens the number of masking steps increases, the features get smaller, and
the tolerance required becomes tighter. This is
largely because the minimum size of individual pattern elements determine the size of the whole circuit, effecting its cost and limiting its potential complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-10 microns (1 micron = 10- 6
meter ~ 1/25,000 inch). The n-channel processes
of the mid 1970's brought this down to approximately 5 microns, and today minimum geometri~s of one
micron are in production. This dramatic reductiOn

The basic process flow described above may make
VLSI device fabrication sound straightforward, however, there are actually hundreds of individual operations that must be performed correctly to complete a
working circuit. It usually takes well over two months
to complete all these operations and the many tests
and measurements involved throughout the manufacturing process. Many of these details are responsible for ensuring the performance, quality, and reliability you expect from Intel products. The following
sections will discuss the technology underlying each
of the major process elements mentioned in the ba.
sic process flow.

Table 1. Typical Hermetic Package Assembly
Flow

ProcassIMaterial.

Typical Item .

Frequency

Criteria

Wafer
Ole saw, wafer break
Ole wash and plate
Ole visual Inspection

--<>

Ole attach
(Process monitor)

t--<>

1._

2. _

t-o

Passivation, metal

OAgate

Post die attach visual
Wire bond
(Process monitor)
Post bond Inspection
OAgate
Seal and Mark
(Process monitor)
Temp cycle

Watout

..

100% of die
Every lot

Dn6, LTPD= 5%

4 x loperatorlshift

0111 LTPD=20%

100% of devices
Orientation, lead

dreSSing, etc.
,

4 x /operatorl
machlnelshift
100% devices

All previous Items

every lot

1/129, LTPD=3%

Cap align, glass
integrity, moisture

4 x nurnaeelshilt

0/15, LTPD=15%

lOx to mil std.
863 cond.C

1/11, LTPD=20%

Hermeticity check
(Process monitor)

FIG leak

100% devices

Lead Trim
(Process monitor)

Burrs, etc. (visual)
Fine leak

4 x Istation/shlft
2 x Istationlshlft

External visual

Solder voids, cap
alignment, etc.

100% devices

QAgate

All previous items

All lots

Class test
(Proeess monitor)

Run standards
(good and reject)
Calibrate every
system using
"autover" program

Every 4Ii hrs.

0115, LTPD=15%
1/129, LTPD=3%

1/129, LTPD-3%

Mark and Pack
·FlnaIOA

(See attached)
.

NOTES:
1. Units for assembly reliability monitor..
2. Units for product reliability monitor.

1-4·

296102-11

inteL

INTEL MEMORY TECHNOLOGIES

in feature size was achieved using the newer high
resolution photo resists and optimizing their processing to match improved optical printing systems.

DIFFUSION
The picture of clean room garbed operators tending
furnace tubes glowing cherry red is the one most
often associated with IC fabrication. These furnace
operations are referred to collectively as diffusion
because they employ the principle of sold state diffusion of matter to accomplish their results. In MOS
processing, there are three main types of diffusion
operations: predeps, drives, and oxidations.

A second major factor in determining the size of the
circuit is the registration or overlay error. This is how
accurately one pattern can be aligned to a previous
one. Design rules require that space be left in all
directions according to the overlay error so that unrelated patterns do not overlap or interfere with one
another. As the error space increases the circuit size
increases dramatically. Only a few years ago standard alignment tolerances were 2 ± 2 microns; now
advanced Intel processes have reduced this dramatically due mostly to the use of advanced projection
and step and repeat exposure equipment.

Predeposition,or "predep," is an operation where a
dopant is introduced into the furnace from a solid,
liquid, or gaseous source and at the furnace temperature (usually 900°C-1200°C) a saturated solution is
formed at the silicon surface. The temperature of the
furnace, the dopant atom, and rate of introduction
are all engineered to give a specific dose of the dop/ant on the wafer. Once this is completed the wafer is
given a drive cycle where the dopant left at the surface by the predep is driven into the wafer by high
temperatures. These are generally at different temperatures than the predeps and are designed to give
the required junction depth and concentration profile.

The wafer that is ready for patterning must go
through many individual steps before that pattern is
complete. First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good resist adhesion. The thick
photoresist liquid is then applied and the wafer is
spun flat to give a uniform coating, critical for high
resolution. The wafer is baked at a low temperature
to solidify the resist into gel. It is then exposed with a
machine that aligns a mask with the new pattern on
it to a previously defined layer. The photo-resist will
replicate this pattern on the wafer.

Oxidation, the third category, is used at many steps
of the process as was shown in the process flow.
The temperature >and oxidizing ambient can range
from 800°C to 1200°C and from pure oxygen to mixtures of oxygen and other gases to steam depending
on the type of oxide required. Gate oxides require
high dielectric breakdown strength for thin layers
(between 0.01 and 0:1 micron) and very tight control
over thickness (typically ± 0.005 micron or less than
± 1/5,000,000 inch), while isolation oxides need to
be quite thick and because of this their dielectric
breakdown strength per unit thickness is much less
important.

Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The
positive resists require much tighter control of exposure and development but yield higher resolution
patterns than negative resistance systems.
The wafer is now ready to have its pattern etched.
The etch procedure is specialized for each layer to
be etched. Wet chemical etchants such as hydrofluoric acid for silicon oxide or phosphoric acid for
aluminum are often used for this. The need for
smaller features and tighter control of etched dimensions is increasing the use of plasma etching in fabrication. Here a reactor is run with a partial vacuum
into which etchant gases are introduced and an
electrical field is applied. This yields a reactive plasma which etches the required layer..

The properties of the diffused junctions and oxides
are key to the performance and reliability of the finished device so the diffusion operations must be extremely well controlled for accuracy, consistency
and purity.

ION IMPLANT
Intel's high performance products require such high
accuracy and repeatability of dopant control that
even the high degree of control provided by diffusion
operations is inadequate. However, this limitation
has been overcome by replacing critical predeps
with ion implantation. In ion implantation, ionized
dopant atoms are accelerated by an electric field

The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechanics, optics, organic chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics.

1-5

intel·

INTEL MEMORY TECHNOLOGIES

and implanted directly into the wafer. The acceleration potential determines ,the depth to which the
, dopant is implanted.
'

The fabrication of modern memory devices is a long,
complex process where each step must be monitored, measured and verified. Developing a totally
new manufacturing process for each new product or
even product line takes a long time and involves significant risk. Because of this, Intel has developed
process families, such as HMOS, on which a wide
variety of devices can be made. These families are
scalable so that circuits need' not be totally redeSigned to meet your needs for higher performance,(1) They are evolutionary so that development
time of new processes and products can be reduced
without compromising Intel's commitment to consistency, quality, and reliability.

The charged ions can be counted,electrically during
implantation giving very tight control over dose. The
ion implanters used to perform this are a combination ofhigh vacuum system, ion source, mass spectrometer, linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see
that this important technique requires a host of sophisticated technologies to support it.

THIN FILMS

The manufacture of today's MOS memory devices
requires a tremendous' variety of technologies and
manufacturing techniques, many more than could be
mentioned here. Each requires a team of experts to
design, ,optimize, control arid maintain it. All these
people and thousands of others involved in engineering, deSign, testing and production stand behind
Intel's products.

\

Thin film depositions make up most of the features
on the completed circuit. They include the silicon nitride for defining isolation, polysilicon for the gate
and interconnections, the glass for interlayer dielectric, metal for interconnection and external connections, and passivation layers. Thin film depOSitions
are done by two main methods: physical deposition
and chemical vapor depOSition. Physical deposition
is most common for deposition metal. Physicaldepositions are performed in a vacuum and are accomplished by vaporizing the metal with a high energy
electron beam and redepositing it on the wafer or by
sputtering it from a target tathe wafer under an electric field.

Because of these extensive requirements, most
manufacturers have not been able to realize their
needs for custom circuits on high performance, high
reliability processes. To address this Intel's expertise in this area is now available to industry through
the silicon foundry; Intel supplies design rules and '
support to design and debug circuits. This includes
access to Intel's n-well CHMOS technology. Users,
of the foundry can now benefit from advanced technology without developing processes and IC manufacturing capability themselves.

Chemical.vapor deposition can be done at atmospheric pressure or under a moderate vacuum. This
type of depOSition is performed when chemical gases react at the wafer surface and deposit a solid film
of thereactiori product. These reactors, unlike t~eir
general industrial counterparts, must be controlled
on a microscale to provide exact chemical and physical properties for thin films such as silicon dioxide,
silicon nitride, and polysilicon.
'
,

(1)R. Pashley, K. Kokkonen, E. Boleky, R. Jecmen, S. Liu,
and W. Owen, "H-MOS Scales Traditional Devices to Higher Performance Level," Electronics, August 18,1977.

1-6

--

Flash Overview

2

intel·

Flash Memory Overview

The ideal memory system optimizes density, nonvolatility, fast readability and cost effectiveness. While traditional memory technologies may individually exhibit
one or more of these desired characteristics, no single
, memory technology has achieved all of them without
major tradeoffs-until the introduction of Intel Flash
Memory.

ROM (read-only memory) is a mature, high density, nonvolatile, reliable and low cost memory technology widely used in PC and embedded applications. Once it is m~nufactured however, the
contents of a ROM can never be altered. Additionally, initial ROM programming involves a timeconsuming mask development process that requires
stable code and is most cost-effective in high volumes.

WHAT IS FLASH MEMORY?
Easy updatability makes .flash memory clearly more
flexible than ROM in most applications.

Introduced by Intel in 1988, ETOX'rM flash memory is
a high-density, truly nonvolatile and high performance
read-write memory solution also characterized by low
power consumption and extreme ruggedness and high
reliability. The cost trend of Intel Flash Memory components continues to decline sharply due to: (1) manufacturing economies inherent in ETOX, Intel's industry-standard EPROM-based flash . technology, (2)·
increases in memory density, and (3) rapid growth in
production volume.

SRAM (static random-access memory) is a highspeed, reprogrammable memory technology which
is limited by its volatility and relatively low density.
As a volatile memory technology, SRAM requires
constant power to retain its contents. Built-in battery backup is therefore required when the main
power source is turned off. Since battery failure is
an inevitable fact of life, SRAM data loss is an everpresent danger. Additionally, SRAM requires four
to six transistors to store one bit of information.
This becomes a significant limitation in developing
higher densities-effectively keeping SRAM cost
relatively high.

A comparison between Intel Flash Memory and other
solid-state memory technologies underscores the fact
that flash offers a design solution with distinct advantages. These advantages are key to future product differentiation for many applications requiring firmware
updates or compact mass storage (Figure 1).

Figure 1_ Intel Flash Memory vs Traditional Memory Technologies
Memory
Flash
SRAM
DRAM

Inherently
One
In-System Code
Hands
High
Low
Byte
NonTransistor
Reand Data
Blocking
off
Density Power
Alterable
Volatile
Cell
Writable Storage
Updates
",

+ Battery
+ Disk

",

",

",

",

EEPROM

",

OTP/EPROM

",

",

",

",

Masked ROM

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

",

OMS-DOS and Windows are registered trademarks of Microsoft Corporation.

2-1

Order Number: 296101-004

FLASH MEMORY OVERVIEW

In contrast, Intel flash memory is inherently nonvolatile, and the single transistor cell design of Intel's
ETO~TM manufacturing process is extremely scalable,
~llowmg the development of continuously higher densities and steady cost· improvement over SRAM
(Figure 2).

Intel
EEPROM
ETOXTM Flash
Transistors
Cell Size
(i-Micro Lithogrpahy)
Cycling Features

..

.3

'"!>!
U)

~

500

faa
50
20
fa

0.1%

5%

-DRAM (dynamic random access memory) is a volatile memory known for its density and low cost.
Because of its volatility, however, it requires not
only a constant power supply to retain. data, but
also an archival storage technology, such as disk, to
back it up.

200

>~

2
38p.

Figure 3

fOOO

u

1
15p.

i!i

"

Partnered with hard disks for permanent mass storage,
DRAM technology has provided a low-cost, yet space
and power-hungry solution for today's PCs.
2.0

f.5

f.2

1.0

0.8

0.7 0.6 0.5

With ETOX process technology, Intel manufactures a
flash memory cell that is 30% smaller than equivalent
DRAM cells. Flash memory's scalability offers a price
advantage. as well, keeping price parity with DRAM;
and also becoming more attractive as a hard disk replacement in portable systems as densities grow· and
costs decline.

t.fiNIt.fUW fEATURE SIZE (1')

296101-1

Figure 2

-

EPROM (electrically programmable read-only
memory) is a mature, high-density, .nonvolatile
technology which provides a degree of updatability
not found in ROM. An OEM may program
EPROM as needed to accommodate code changes
or varying manufacturing unit quantities. Once programmed, however, the EPROM may only be
erased by removing it from the system and then
exposing the memory component to ultraviolet
light-an impractical and time-consuming procedure for many OEMs and a virtually impossible
task for end-users.

Intel flash memory combines advantages from each of
these memory technologies. In embedded memory' applications, flash memory provides higher-performance
and more flexibility than ROM and EPROM, while
providing higher density and better cost effectiveness
than battery-backed SRAM and EEPROM. Moreover,
the true nonvolatility and low power consumption
characteristics of flash memory make it a compelling
alternative to DRAM in many applications.

Unlike EPROM, flMh memory is electrically re-writac
ble within the host system, making it a. much more
flexible and easier to use .alternative. Flash memory off~rs OEMs not only high density and nonvolatility, but
higher functionality and the ability to differentiate their
systems.
-

ETOXTM III TECHNOLOGY
Unlike other approaches to flash memory, Intel ETOX
is a proven technology. As its name suggests, ETOX
(or "EPROM tunnel oxide") technology evolved from
EPROM. With 95% process compatibility with
EPROM, ETOX taps experience gained from a mature
high-volume manufacturing base pioneered by Intel in
the 19708..

EEPROM (electrically erasable programmable
read-only memory) is nonvolatile and electrically
byte-erasable. Such byte-alterability is needed in
certain applications but· involves a more complex
cell structure, and significant trade-offs in terms of
limited density, lower reliability and higher cost,
making it unsuitable as a mainstream memory.

Data retention and lifetime reliability statistics for
ETOX III flash are equivalent to those of EPROM.
Representing the third generation of Intel flash memory technology, the ETOX III 0.8p. process provides
< 100 FITS (failures in time) @ 55°C in a specification
that delivers 100,000 write cycles per block. This capability significantly exceeds the cYcling requirements of
even the most demanding applications.

Unlike EEPROM, Intel flash memory technology utilizes .a one-transistor cell,. allowing higher densities,
scalability, lower cost, and higher ri~liabi1ity, while taking advantage of in-system, electrical erasability (Figure 3).
2-2

FLASH MEMORY OVERVIEW

For example, code storage for embedded control programs used in standard computer applications is infrequently updated. Twenty-year system lifetimes may require fewer than 100 rewrites. Even routinely-changed
data tables (used in navigational computers and black
box controllers) only require about 1,000 write cycles
over a 20-year period. The most demanding flash memory application of all, archival data storage in PC applications, typically requires about 5,000 write cycles in 20
years.

Intel's 28FOOIBX I Mbit Boot Block flash component,
featuring a sectored architecture, has been widely accepted in embedded code storage applications, particularly in PC BIOS and cellular communications. By
adopting Boot Block for their products, over 20 PC
manufacturers have gained added flexibility and the
ability to differentiate in a highly competitive market.
End users also benefit from the ability to upgrade BIOS
software quickly and securely. The blocked architecture allows the OEM to store critical system code securely in the lockable "boot block" of the device that
can minimally bring up the system and download to
other locations of the device to initialize the system.
The hardware boot locking feature guarantees that even
if the power is disrupted during a BIOS update, the
system will be able to recover immediately.

ETOX flash memory's simple single-transistor cell
structure makes it smaller than other flash cells, allowing designers to create highly integrated systems which
are more reliable and cost-effective than those based on
more complex and less mature flash technologies. The
inherent scalability of ETOX III Flash Memory and
high-volume manufacturing is enabling a corresponding downtrend in flash cost.

In response to customer requests for speed, density, low
power, surface-mount options and an industry-standard
upgrade path for portable computing and telecommunications, Intel more recently introduced the 2 Mbit
28F200BX and 4 Mbit 28F400BX Boot Block products.

Flash memory has added a new dimension to nonvolatile 'memory applications. Embedded systems, such as
PC BIOS, hard disk drive controllers and cellular telephone applications take advantage of the easy update
capability, high density and high performance of Intel
Flash Memory. Today's new generation of portable
computers require the optimum combination of performance, size, weight, low power and shock resistance.
Whether implemented in memory cards, solid state
disks or at the component level, Intel's Flash Memories
are also enabling a whole new generation of mobile
computers.

These products offer 60 ns performance; two surface
mount packages: 4O-lead TSOP (X8 only) and 44-lead
PSOP; and a proprietary Boot Block architecture simi~
lar to the 1· Mbit Boot Block device. The Boot Block
stores the code necessary to initialize the system, while
parameter blocks can be used to store manufacturing
product code, setup parameters, and frequently updat- .
ed code such as system diagnostics. The main operating
code is stored in the main blocks. Both devices are
available in a x16/x8 ROM-compatible pin-out in
44-lead PSOP surface mount packaging. These pinouts
and packages allow an easy upgrade from 2 Mb to
4 Mb, since only one address is added to the 4 Mb
device.

IMPLEMENTING INTEL FLASH
MEMORY
Today, Intel continues to serve both updatable nonvolatile memory applications as well as the rapidly emerging solid-state mass storage applications with flash
memory solutions tailored to meet the needs' of these
markets.

Solid-State Mass Storage
This major application segment requires very high density memory, automated programming and high-perforniance erase/write capability at a very low cost per
bit. Erasing and writing portions of the code or data is
much more frequent in solid'state mass storage than in
updatable firmware applications.

Updatable Code Storage
Code and data storage comprise the updatable nonvolatile memory applications that require high performance, high density, and easy update capability. Because
these applications are not updated as frequently as solid-state mass storage applications, erase/write cycles
are not as critical as integration and performance requirements. This application segment is served effectively with full chip-erase or Boot Block products.

Intel's symmetrically blocked 8 Mbit 28F008SA FlashFile™ memory is the highest density nonvolatile read/
write solution for solid-state mass storage. What's
more, it is the first flash memory device optimized for
solid-state storage of software and data files.
The 28F008SA is packaged in an advanced 4O-lead
TSOP (thin, small outline package) 'or 44-lead PSOP
(plastic SOP) to provide the extremely small form factor required for today's handheld, pen-based and sub-

• Based on 10MB card design, 5,000 cycle yields 50, 000 MB of stored
data, which far exceeds most usage environments and file system
methodologies.

2-3

FLASH MEMORY OVERVIEW
ty, size and perform~nce oftheir systems, as well as the
disk media themselves.

notebook portable computers. The compactness of'an
8 Mbit device ina TSOP package allows for high-density flash arrays to be inCluded both on a system motherboard for direct execution of user programs or operating systems, as well as. memory cards for transportable
program and file storage.

Yet the disk drive is an electro-mechanical system with
inherent limitations. Any mechanical hardware is much
more vulnerable than solid state semiconductor technology to the shock, vibration, and impurities that portable PCs encounter during normal use. Hard disk
drives can typically withstand up to lOGs of operating
shock; Intel FlashFile memory, with no moving parts,
can withstand as much as l000Gs. Additionally, Intel's
Series 2 Memory Cards feature approximately 1.6 million hours mean time between failure (MTBF). Such
endurance and reliability is essential for many of today's truly mobile handheld palmtop and notebook
sized PCS, particularly within applications requiring extreme data integri.ty.

Memory Cards
Intel's fanlily of flash memory cards provides the most
reliable and rugged form of removable memory media.
High density, true nonvolatility, rewrite flexibility, and
proven cost effectiveness make Intel Series 1 Flash
Memory Cards the ideal medium for storing and updat"
ing application code as well as capturing data.
For file storage applications that require high performance, .ruggedness, long battery life, small size and light
weight, Intel's Series 2 Flash Melllory Cards in
4-Mbyte, 10-Mbyte and 20-Mbyte densities provide the
best solution. Based on Intel's 8-Mbit FliishFile memory components, the Series 2 card's block-erase functionality and high density take full advantage of flash filing
systems like Micros9ft°'s Flash File System software to
provide full disk emulation in the form of removable,
nonvolatile storage. The cards conform to the
PCMCIA 2.0/J~IDA 4.1 68-pin standards and are
compatible with Intel's Exchangeable Card Architecture (ExCATM) to ensure system-to-system interoperabililty.

Power consumption is another major consideration for
today's mobile PC designer and user. The drive typically requires anywhere from 3 watts to as many as
8 watts of power to run-which means rapid drain of
the system's batteries. Compare ~his to flash memory in
a hard disk configuration. It consumes less than one
two-hundredth the average PQwer of a comparable
magnetic disk drive bas.ed on the typical user model. At
the chip level, the 8 Mbit FlashFile Memory component has a DEEP POWERDOWN mode that reduces
power consumption to less than 0.2 ,..,A.
Additional shortcomings of disk drives are their size,
weight and floor costs. Magnetic drives do noi scale
well, that is, it becomes increasingly difficult to improve or even retain density as platter size shrinks.
Thus, every reduction in' driv~ size requires complete
retooling and costly learning. Also, the complex controller. circuitry provides a' price floor under which
ma~etic drives cannot drop. Since. flash is scalable, at
some point in the near future, small magnetic drives are
lii<:ely to become more expensive per Mbyte than flash
cards and are certain to have less capacity.

THE IMPETUS BEHIND THE "SOLIDSTATE" DISK
Because the disk-based PC is so prevalent and eminently familiar to both designers and end-users, .many of
today's portable systems still rely on it as their primary
medium. At the same time, disk drive manufacturers
have made great strides toward improving the reliabili-

Average Seek Time
Latency
Data Transfer Rate
Read:
Write:
Total Time to Access
(1 Kbyte File)

Disk/DRAM

Flash

. 28.0ms

0

B.3ms

0

8 Mbits/sec.
8 Mbits/sec.
... Now Read from RAM

106.7 Mbits/sec.
1 Mbitlsec.
Direct Processor Access

Figure 4
/

2-4

,

0.077 ms

.37.3 ms

infel~

FLASH MEMORY OVERVIEW

From a performance standpoint, disk-based systems
still require some form of supplementary memory that
is directly executable. Typically, DRAM is used for executable code storage and data manipulation. Data
from the disk is downloadable into the DRAM cache
before users can access the information. Then when a
"save" operation is desired, the data is uploaded from
DRAM back into the disk. This download/upload process slows down system throughput while the redundant memory media produce even more system overhead in the form of added space, power consumption
~nd weight (Figure 4).

Specifically, two recent developments allow this
achievement: DOS in ROM-executable form (DOS was
formerly designed to be stored on disk and then downloaded to/executed out of RAM); and a file system designed for flash memory technology that allows the devices to erase blocks of memory instead of the whole
chip.
ROM-executable DOS provides several benefits to both
system manufacturers and ultimately end users. First,
since most of the operating system is composed of fixed
code, the amount of system RAM required to execute
DOS is reduced from 50K to 15K, thereby conserving
system space and power. Secondly, DOS can now be
permanently stored in and executed from a single
ROM-type of device-flash memory-so systems come
ready to run. Lastly, users enjoy "instant on" performance since the traditional disk-to-DRAM boot function
and software downloading steps are eliminated.

Today's PCs are typically configured with
4 Mbytes-8 Mbytes of DRAM backed up by at least a
4O-Mbyte disk. FlashFile memory fully supports this
system configuration when used simply as a magnetic
drive replacement; Instructions and data are still
swapped to DRAM, but at a faster rate. Plus execution
speed can be enhanced if the DRAM is replaced with
SRAM.

For example, by storing application software and operating system code in a Resident Flash Array (RFA),
users enjoy virtually instant-on performance and rapid
in-place code execution. An RFA also protects against
software obsolescence because it is in-system updatable.
Resident software, stored in flash rather than disk, extends battery life and increases system reliability.

In the solid-state computer, the "DRAM + magnetic
hard drive" is replaced by a "flash memory +
SRAM". The key to this architecture is the ability to
eXecute-In-Place (XIP). Program instructions stored in
flash memory are read directly by the processor. Results are written directly to the flash memory. Compute-intensive operations that require the fastest memory access and byte-alterability can use high-speed
SRAM or pseudo SRAM. Some of the system DRAM
can be replaced by low-cost flash and a small part of
the DRAM can be replaced by SRAM. The flash memory space is made even more storage efficient through
the use of compression techniques which may offer up
to 2: I compression.

Since erasing and writing data to flash memory is a
distinctly different operation than rewriting information to a disk, new software techniques were necessary
to allow flash to emulate disk functionality. File management software like Microsoft*'s Flash File System
(FFS) allows Intel's Flash Memory components and
flash cards to emulate the file storage capabilities of
disk. Microsoft's FFS transparently handles data swaps
between flash blocks similar to the way MS-DOS handles swaps between disk sectors. Under FFS, the user
may input a MS-DOS or Windows' command without
regard for whether a flash memory or magnetic disk is
installed in the system. The FFS also employs wear-leveling algorithms that prevent any block from being cycled excessively, thus assuring millions of hours of reliability. Flash filing systems make the management of
flash memory devices completely transparent to the
user.

SOFTWARE DEVELOPMENTS
POSITION FLASH FOR PORTABLE
APPLICATIONS
The majority of today's portabie computers and supporting software programmers are designed to run using Microsoft's MS-DOS' disk operating system. MSDOS was developed to allow broad-based compatibility
between systems and software and to optimize the sectoring scheme inherent to disk technology.

CONCLUSION
Intel's Flash Memory, based on a block-erase architecture, divides the flash memory into segments that are
loosely analogous to the-zones recognized in MS-DOS.
Thanks to recent software developments, flash memory
can effectively serve as the main memory within portable computers, providing user functions virtually identical to, and even improved over, those of disk-based systems.

Intel Flash Memory presents an entirely new memory
technology alternative. As a high-density, nonvolatile
read/write technology, it is exceptionally ~ell-suited to
serve as a solid-state disk or a cost-effective and highly
reliable replacement for DRAMs and battery-backed
static RAMs. Its inherent advantages over these technologies make it particularly useful in portable systems
that require the utmost in low power, compact size, and
ruggedness while maintaining high performance and
full functionality.
2-5

FLASH MEMORY OVERVIEW

Intel Flash Memory offers:
• Inherent Nonvolatility: Unlike static RAMs, no
backup battery is required to ensure data retention.
In contrast to DRAMs, flash requires no disk to
provide backup storage of data, programs or files.
• Cost-Effective High Density: Today, Intel flash
memories cost about the same as DRAMs and
about one fourth of SRAMs on a per-bit basis. The
broad acceptance of flash is driving manufacturing
volumes up and costs down at an unprecedented
rate, allowing flash to soon compete on a cost basis
even with disk drive within the notebook, sub-notebook and palmtop markets.
• Solid-State Performance: Because it is a semiconductor technology, flash memory consumes much
less power, is much lighter in weight and is smaller
and more shock-resistant and reliable than disk
drives. Mobile computers no longer have to drain
the battery to run a disk.drive motor or accommodate the disk assembly's added bulk and weight.
Now users no longer have to be threatened with the
possibility of losing their data after a disk crash
when conditions become unusually rough.
• Direct Execution: Since no disk-to-DRAM download step, seek or latency times are incurred with

flash memory, users enjoy significantly higher speed
program and file access, as well as systems that turn
on instantly to wherever the user left off.
• Easy Updatability: Unlike other nonvolatile memory technologies-ROM that can never be altered after it is manufactured or EPROM that can only be
erased by removing it from the system and exposing
it to ultraviolet light-flash can be erased and reprogrammed electrically while resident in the host system!
• Software Compatibility: With Flash File System
software and ROM-executable versions of the disk
operating system (DOS), complete software compatibility between a user's desktop and portable system
is ensured.
.
• Exchangeable Card Architecture (ExCATM):
Through Intel's ExCA card interface standard, Intel's flash memory cards meet all specifications of
PCMCIA 2.0, ensuring interchangeability between a
host of PCMCIA-compatible systems.
• Family of Products: Intel Flash Memory products
are currently available in component densities up to
8 Mbits, and in 4-Mbyte, lO-Mbyte and 20-Mbyte
memory cards. Additionally, Intel offers Boot Block
devices in densities up to 4 Mbits.

2-6

Flash Memory
Components

3

28F256A
256K (32K x 8) CMOS FLASH MEMORY
•

Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase

•

Quick-Pulse Programming Algorithm
-10,..,s Typical Byte-Program
- 0.5 Second Chip-Program

•

•

•

12.0V ±5% Vpp

•

High-Performance Read
- 120 ns Maximum Access Time

•

CMOS Low Power Consumption
-10 mA Typical Active Current
- 50 ,..,ATyplcal Standby Current
- 0 Watts Data Retention Power

Noise Immunity Features

- ± 10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing

100,000 Erase/Program Cycles Typical

•

Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface

II Integrated Program/Erase Stop Timer

•

ETOXTM II Flash Nonvolatile
Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience

•

JEDEC-Standard Pinouts
-32-Pln Cerdlp
- 32-Lead PLCC
(See Packaging Spec., Order # 231369)

Intel's 28F256A CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F256A adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F256A increases
memory flexibility, while contributing to time and cost savings.
The 28F256A is a 256-kilobit nonvolatile memory organized as 32,768 bytes of 8 bits. Intel's 28F256A is
offered in 32-pin plastic dip and 32-lead PLCC. Pin assignments conform to JEDEC standards.
Extended erase and program cycling capability is designed into Intel's ETOXTM II (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the
28F256A performs a minimum of 10,000 erase and program cycles well within the time limits of the QuickPulse Programming and Quick-Erase algorithms.
Intel's 28F256A employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 120 ns access time provides no-WAlT-state performance
for a wide range of microprocessors and microcontrollers. Typical standby current of 50 p.A translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address
and data pins, from -1V to Vee + 1V.
. With Intel's ETOX II process base, the 28F256A levers years of EPROM experience to yield the highest levels
of quality, reliability, and cost-effectiveness.

3-1

September 1992
Order Number: 290243-005

intel~

28F256A

Vee
vss

---.
---.

J

vpp

"I

T

STATE
CONTROL

---.

r

COMMAND
REGISTER

ERASE VOLTAGE
SWITCH

I

it

I

INPUT/OUTPUT
BUFFERS

TO ARRAY
SOURCE

e-

"'-

,-

I--

.II
~

INTEGRATED PROGRAM
/ERASE STOP TIMER ~ PGM VOLTAGE
SWITCH

)

I

CHIP ENABLE
OUTPUT ENABLE
LOGIC

'7

STB

DATA
LATCH

~

Y-GATING

,
~

•

STB
- Al4

'II.

:J:

Y-DECODER

3

~

'ii'l'l
290243-3

290243-2

Figure 2. 28F256A Pin Configurations

3-2

intel·

28F256A

Table 1. Pin Description
Symbol

Type

Name and Function

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.

DOo-D07

INPUT/
OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state OFF when the chip is deselected or the outputs are disabled. Data
is internally latched during a write cycle.

CE

INPUT

CHIP ENABLE activates the device's control logic, input buffers,
decoders, and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.

OE

INPUT

OUTPUT ENABLE gates the devices output through the data buffers
during a read cycle. OE is active low.

WE

INPUT

WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse. Note: With Vpp·"; 6.5V,
memory contents cannot be altered.

Ao-A14
I

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command register,
erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 10%).

Vss

GROUND.

NC

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

APPLICATIONS
The 28F256A flash memory provides nonvolatility
along with the capability to typically perform over
100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F256A an innovative al- .
ternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of Gode and datatables are required, the 28F256A's reprogrammability and nonvolatility make it the obvious and ideal
replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-DRAM download process. This results in a dramatic enhancement of performance and substantial reduction of power consumption-considerations particularly important in
portable equipment. Flash memory increases flexibility with electrical chip-erasure and in-system update capability of operating systems and application
code. With updatable BIOS, system manufacturers
can easily accommodate last-minute changes as revisions are made.

cal media. Often in these environments, power interrupts force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communications
protocols and primary applications are flash-resident
in each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F256A provides higher performance,
lower power consumption, instant-on capability, and
allows an "execute in place" memory hierarchy for
code and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh environments where extreme temperatures and shock
can cause disk-based systems to fail.
Theneed for code updates pervades all phases of a
system's life-from prototyping to system manufacturing to after-sale service. The electrical chip-erasure and reprogramming ability of the 28F256A allows in-circuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while· adding greater test, manufacture, and
update flexibility.

In diskless workstations and terminals, network triiffic reduces to a minimum and systems become instant-on. Reliability exceeds that of electromechani-

Material and labor costs associated with code
changes increases at higher levels of system inte-

3-3

in1et

28F256A

gration-the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revision to EPROM-based code requires the removal of EPROM components or entire boards. With the
28F256A, code updates are implemented locally via
an edge-connector, or remotely over a communications link.

chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simpli.ties memory,to-processor interfacing. Figure 3 depicts two 28F256As tied to the 80C186 system bus.
The 28F256A's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.

For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for. battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.

With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility, the
28F256A is a functional superset of one or more of .
the alternatives: EPROMs, EEPROMs, battery
backed static RAM, or disk. EPROM-compatible
read specifications, straightforward interfacing, and
in-circuit alterability offer designers unlimited flexibility to meet the high standards of today's deSigns.

Flash memory's electrical chip-erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical

Vee

Vee

80CI86
SYSTEM BUS
A1-A 15

---------+1

D08-00 15 +---------I~
0°0-007

+---,-------1

MCSO

---------+1

BHE---\

WR
Ao----f

iiii--------....
290243-4

Figure 3. 28F256As In a80C186 System

3-4

intel .

28F256A

PRINCIPLES OF OPERATION

Write Protection

Flash memory augmerits EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F256A introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supply during erasure and programming; and maximum
EPROM compatibility.

The command register is only active when Vpp is at
high voltage. Depending upon the application, the
system deSigner may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VpPL, the contents of the register default to the read command,
making the 2BF256A a read-only memory. In this
mode, the memory contents cannot be altered.

In the absence of high voltage on the Vpp pin, the
28F256A is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and inteligent
IdentifierTM operations.

Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write
lockout voltage VLKO. (See Power Up/Down Protection). The 28F256A is designed to accommodate eitherdesign practice" and to encourage optimization
of the processor-memory interface.

The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory contents-inteligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.

The two-step program/erase write sequence to the
Command Register provides additional software
write protection.

BUS OPERATIONS

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-maChine which
control the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming and erase qperations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the inteligent Identifier codes, or output
data for erase and program verification.

Integrated Program/Erase Stop Timer
Successive command write cycles define the duration of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated 'program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for.maximum program/erase timing
,specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates. a program or erase operation, the device en-'
ters an inactive state and remains inactive until receiving the appropriate verify or reset command.

Read
The 28F256A has two control functions, both of
which must be logicall~ctive, to obtain data at the
outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Refer to AC read timing Vliaveforms.
When Vpp is high (VPPH) , the read operations can
be used to access array data, to output the inteligent
Identifier codes, and to access data for program/
erase verification. When Vpp is low (Vppu, the read
, operation can access only the array data.

. Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.

Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 2BF256A's .circuitry
,and substantially reduces device power consump'tion. The outputs are placed in a high-impedance

3-5

,

infel .

28F256A

state, independent of the Output-Enable signal. If
the 28F256A is deselected during erasure, program~
ming, or program/erase verification, the device
draws active current until the operation is terminated.

plied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the device.
The command register itself does not occuPy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.

intellgent Identifier Operation
The inteligent Identifier operation outputs'the manufacturer code (89H) and, device code (89H). Pro'gramming equipment automatically matches the device with its proper erase and programming algorithms. With Chip-Enable and Output-Enable ata
logic low level,rising Ag to high voltage VID (see
D.C. Characteristics) activates the operation. Data
read from locations OOOOH and 0001 H represent the
manufacturer's code and the device code, respectively.

The command register is written by bringing, WriteEnable to.a logic-low level (VIU, while Chip-Enable is ,
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched' on the riSing
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refe'r to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.

The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F256A is erased and reprogrammed in the target system. 'Following ,a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the, device code (89H).

COMMAND DEFINITIONS
When low voltage is applied to theVpp pin, the con,
tents of the command register default to OOH, enabling read-only operations..
Placing high voltage on the Vpp pin enables,read/
write operations. Device operations are selected by
writing specific data p~tterns into the command register. Table 3 defines these 28F256A register com'
mands.

Write
Device erasure and programming are accomplished
via the command register, when high voltage is ap-

Table 2. 28F256A Bus Operations'
Pins

Vpp(1)

Ao

Ag

CE

OE

WE

DQo-DQ7

Operation

~

VPPL

Ao

Ag

VIL

VIL

VIH

Data Out

Output Disable

VPPL

X(7)

X

VIL

VIH

VIH

Tri-State

0
Q

Standby

VPPL

X

X

VIH

X

X

Tri-State

CC
\
11:.

inteligent 10 Manufacturer(2)

VPPL

VIL

VID(3)

VIL

VIL

VIH

inteligent 10 Device(2)

VPPL

VIH

VID(3)

VIL

VIL

VI/i

Data = 89H

Read

VPPH

Ao

Ag

VIL

VIL

VIH

DataOut(4)

Ow

Output Disable

VPPH

X

X

VIL

VIH

VIH

Tri-State

11:11:

Standby(5)

VPPH

X

X

VIH

X

X

Tri-State

Write

VPPH

Ao

Ag

VIL

VIH

VIL

z

III

....

~t:

==

Read

NOTES:
1,. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence.
Refer,to Table 3. All other addresses low.
3. VIO is the inteligent Identifier high voltage. Refer to D.C. Characteristics.
4. Read operations with Vpp = VPPH may access array data or theinteligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

')

3-6

Data 0:= 89H

Data In (6)

intel~

28F256A

Table 3. Command Definitions

Command

First Bus Cycle
Second Bus Cycle
Bus
Cycles
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
Write

X

3

Write

X

90H

Read

(4)

(4)

2

Write

X

20H

Write

X

20H

Read Memory

1

Read inteligent 10 Codes
Set-Up Erase/Erase(S)

OOH

Erase Verify(S)

2

Write

EA

AOH

Read

X

EVO

SetcUp Program/Program(5)

2

Write

X

40H

Write

PA

PO

Program Verify(5)

2

Write

X

COH

Read

X

PVO

Reset(7)

2

Write

X

FFH

Write

X

FFH

NOTES:
1. Bus operation are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA= Address of memory location to be. programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification. (Mfr = 89H, Device = B9H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of the Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Head. inteligent ID command, two read operations access manufacturer and device codes.
5. Figure 4 illustrates the Quick·Pulse Programming Algorithm.
6. Figure 5 illustrates the Quick-Erase Algorithm.
7. The second bus cycle must be followed by the desired command register write.

tiplexing high voltage onto address lines is not a desired system-design practice.

Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.

The 28F256A contains an inteligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOHretrieves the. manufacturer code 89H. A read cycle
from address 0001 H returns the device code B9H.
To terminate the operation, it is necessary to write
another valid command into the register.

The. default contents of the register upon Vpp power-up is OOH. This default value. ensures that no spurious alternation of memorycbntents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F256A, the device powers-up
and remains enabled for reads until the command
register .contents are changed. Refer to the AC
Read Characteristics and Waveforms for specific
timing parameters.

Set-Up Erase/Erase Commands
Set-up Erase is a command-only operation that
stages the device for electrical erase of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register. To commence Chip-erasure, the erase command (20H)
must again be written to the register. The erase operation begins with the rising edge of the Write-Enable pulse and terminate with the rising edge of the
next Write-Enable pulse (i.e., Erase-Verify CorTimand).

inteligent Identifier Command
Flash memories are intended for.use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system~ PROM programmers typically access signature
codes by raising A9 to a high voltage. However, mul-

'"

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
3-7

intel..

28F256A

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.

Erase-Verify Command!

Program Verify Command

The erase command erases all of the bytes of the
array in parallel. After each erase operation, all bytes
must be verified. The erase verify operation is initiatedby writing AOH into the command register. The
address for the byte to be verified must be supplied
as it is latched on the falling edge of the Write-Enable pulse. The register write terminates the erase
operation with the rising edge of its Write-Enable
.
pulse.

The 28F256A is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at
random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.

The 28F256A applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.

The 28F256A applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4,
the 28F256A Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.

The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte' does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-Up
Erase/Erase.) Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g., Program Set-Up) to the command
register. Figure 5, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F256A.
Refer to 'AC Erase Characteristics and, Waveforms
for specific timing parameters.

Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.

Set-Up Program/Program Commands

EXTENDED ERASE/PROGRAM
CYCLING

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up operation.

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.

Once the program set"up, operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write"Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the,
next rising edge of Write-Enable, used to write the

Intel has deSigned extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increaSing memory cell size or complexity. First, an

3-8

int:eL

28F256A

advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower then EEPROM. The lower electric·
field greatly reduces oxide stress and the probability
of failure-increasing time to wear out by a factor of
100,000,000.
.
The 28F256A is specified for a minimum of 10,000
program/ erase cycles. The device is programmed
and erased using Intel's Quick-Pulse Programming
and Quick-Erase algorithms. Intel's algorithmic approach uses a series of operations (pulses), along
with byte verification, to completely and reliably
erase and program .the device.

performed with Vpp at high voltage. Figure 4 illus.
trates the Quick-Pulse Programming algorithm.

QUICK-ERASE ALGORITHM
Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F256A is erased when shipped from the factory.
Reading FFH data from the device would immedi-.
ately be followed by device programming.
For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately one-half second.

For further reliability information, see Reliability Report RR-60 (ETOX II Reliability Data Summary).

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 5 illustrates the Quick-Erase algorithm.

QUICK-PULSE PROGRAMMING
ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 /ks duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is

3-9

intel~

28F256A

Bus
Operation

Command

Standby

Comments

Wait for Vpp ramp
to VPPH (= 12.0V) (1)
Initialize pulse-count

Write

Set-Up
Program

Data = 40H

Write

Program

Valid address/data

Program(2)
Verify

Duration of Program
operation (tWHWH1)
Data = COH; Stops (3)
Program Operation

Standby
Write
Standby

tWHGL

Read

Read byte to verify
programming

Standby

Compare data output
to data expected

Write

Read

Standby

290243-5

NOTES:
1. See DC Characteristics for the value of VPPH and VPPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional)
after the register is written with the Read command.
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Figure 4. 28F256A Quick-Pulse Programming Algorithm

3-10

Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
toVppd1)

intel .

28F256A

Bus
Operation

Command

Standby

Comments

Wait for Vpp ramp
to VPPH (= 12.0V) (1)
Use Quick-Pulse
Programming (Fig. 4)

Initialize Addresses,
Erase Pulse Width,
and Pulse Count
Write

Set-Up
Erase

Data = 20H

Write

Erase

Data = 20H

Erase
Verify(2)

Duration of Erase
operation (tWHWH2)
Addr = Byte to verify;
Data = AOH; Stops
Erase Operation (3)
tWHGL

Standby
Write

Standby
Read

Read byte to verify
erasure

Standby

Compare output to FFH
increment pulse count

Write

Read

Standby

Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
toVppd1)

290243-6

NOTES:
1. See DC Characteristics for the value of VPPH and VpPL.
2. Erase Verify is performed only after chip-erasure. A final
readlcompare may be performed (optional) after. the register is written with the Read command.

3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.

Figure 5. 28F256A Quick-Erase Algorithm
3-11

28F256A

DESIGN CONSIDERATIONS

Vpp Trace on Printed Circuit Boards

Two-Line Output Control

Programming flash memories, while they reside in
the target smith, requires that the printed circuit
board designer pay attention to the VPP pin power
supply trace. Use similar trace widths and layout
considerations given the Vee power bus. Adequate
VPP supply traCes and decoupling will decrease VPP
voltage spikes and overshoots.

Flash memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation,
.
and

Power Up/Down Protection

b. complete assurance that output bus contention
will not occur.

The 28F256A is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F256A is indifferent as to which power supply, Vpp or Vee, powers
up first. Power supply sequencing is not required.
Internal circuitry in. the 28F256A ensures that the
command ,register is reset to the read mode upon
power up.

To efficiently use these two control units, an address-decoder output should drive chip-enable,
while the system's read signal controls all flash
memories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.

Power Supply Decoupling

A system designer must guard against active writes
for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences.

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (led issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

28F256A Power Dissipation

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 /LF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F256A does not consume any power to retain
code or data when the system is off. Table 4 illustrates the power dissipated when updating the
28F256A.

Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 /LF electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

Table 4. 28F256A Typical Update Power Dissipation(4)
Power Dissipation
Notes
(Watt-Seconds)

Operation
Array Program/Program Verify

0.043

1

Array Erase/Erase Verify

0.083

2

One Complete Cycle

0.169

3

NOTES:

1. Formula to calculate typical Program/Program Verify Power = [Vpp x # Bytes x typical # Prog Pulses (tWHwH1 x
IpP2 typical + tWHGL X IpP4 typical)) + [Vcc x # Bytes X typical # Prcig Pulses (tWHWH1 x ICC2 typical + tWHGL X
ICC4 typical)].
_
. .
' .
2. Formula to calculate typical Erase/Erase Verify Power = [V (lpP3 typical x tERASE typlcal.+ IpP5 typical x tWHGL x
# Bytes») + [VcC Vee

Vpp:5: Vee

IpP2

Vpp Programming Current

1,2

8.0

,30

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current .

1,2

4.0

20

mA Vpp= VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
P~ogram Verify in Progress

Ipps

Vpp Erase Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

2.0

+ 0.5

V
V

VIH

Input High Voltage ,

VOL

Output Low Voltage

VOH1

Output High Voltage

VIO

Ag inteligent Identifier
Voltage

110

Ag inteligent Identifier
Current

VPPL'

Vpp During Read-Only
Operations

0.00

6.5

V

VPPH

Vpp During Read/Write
Operations

11AO

12.60

V

VLKO

Vee Erase/Write Lock Voltage

Vee

0.45
2.4
11.50
1,2

13.00
90

2.5

200

V

IOL =5.8mA
Vee = Vee min

V

IOH = -2.5 mA
Vee = Veemin

V
p.A Ag = VID

V
3-14

Note: Erase/Program are
Inhibited when Vpp = VPPL

intel·

28F256A

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Limits

Notes

Unit

Typlcal(4)

Min

Test Conditions

Max

III

Input Leakage Current

1

±1.0

/LA Vee = Vee max
VIN = Vee or Vss

ILO

Output Leakage Current

1

± 10.0

/LA Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

50

100

/LA Vee = Vcemax
CE = Vee ±0.2V

lee1

Vee Active Read Current

1

10

30

mA Vcc. = Veemax CE = VIL
f = 6 MHz, louT = 0 mA

lee2

Vee Programming Current

1,2

1.0

10

mA Programming in Progress

leca

Vee Erase Current

1,2

5.0

15

mA Erasure in Progress

leC4

Vee Program Verify Current

1,2

5.0

15

mA Vpp = VPPH
Program Verify in Progress

lee5

Vcc Erase Verify Current

.. 1,2

5.0

15

mA Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

1

IpP1

Vpp Read Current, 10
Current, or Standby Current

1

±10.0
90

200

/LA Vpp::;; Vee
/LA

±10.0

Vpp >Vee
Vpp::;; Vee

IpP2

Vpp Programming Current

1,2

8.0

30

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

20

mA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

.. 1,2

2.0

5.0

mA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Vol~age

-0.5

VIH

Input High Voltage

0.7Vee

VOL

Output Low Voltage

VOH1

Output High Voltage

0.8
Vee

+ 0.5

0.45

•

0.85Vee

VOH2

V
V
V

IOL = 5.8mA
Vee = Vee min

V

IOH = -2.5 mA,
Vee = Vee min
IOH = 100 /LA,
Vee = Vee min

Vee -0.4

VIO

As inteligent Identifier
Voltage

110

As inteligent Identifier
Current

11.50

13.00

1,2

90

3·15

200

V
/LA As

= VIO

int:et

28F256A

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Unit

Test Conditions
Note: Erase/Program are
Inhibited when VPP = VPPL

Typlcal(4) Max

Min
VPPL

VPP During Read-Only
Operations

0.00

6.5

V

VpPH

VPP During Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock Voltage

CAPACITANCE(3) T ;= 25°C, f
Symbol

Parameter

=

2.5

V

1.0 MHz

Notes

Limits
Min

Unit

Max

ConditIons

CIN

Address/Control
Capacitance

3

6

pF

VIN = OV

COUT

Output Capacitance

3

12

pF

VOUT =OV

NOTES FOR DC CHARACTERISTICS AND CAPACITANCE:
1. All currents are in RMS ul)less·otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T = 25°C, These currents·
are valid for all product versions (Packages and Speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.

AC TESTING INPUT/OUTPUT WAVEFORM

.

AC TESTING LOAD CIRCUIT
/

2.4
INPUT 0.45

OUTPUT

l:~
~~

2.0 » _
TEST
_POINTS
_ _ _ __

~0::;;.8~

Q~:~

_ _...X:....;:""x_t

lN914

3.3k
DEVICE
UNDER
TEST

»TEST POINTS
290243-7-

AC Testing: Inputs are driven at .2.5V for a logic "1" and 0.45 for a
logic "0". Testing measurements are made a12.0 for a logic "1"
and 0.8 for a logic "0". Rise/Fall lime ,;; 10 ns.

CL=I00pF
CL Includes Jig Capacitance

AC Test Conditions
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................... 0.45 and 2.4
Input Timing Reference Level .......... 0.8 and 2.0
Output Timing Reference Level ......... 0.8 and 2.0

3-16

.'

1
-

OUT
CL

= 100pf'
290243-8

28F256A

AC CHARACTERISTICS Read-Only Operations
Versions

Notes

Symbol

Characteristic

28F256A·120
Min

Max

120

tAVAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

tAVQV/tACC

Address Access Time

tGLQV/taE

Output Enable
Access Time

tELQX/tLZ

Chip Enable to Output
in LowZ

2,3

tEHQZ

Chip Disable to Output
in High Z

2

tGLQX/taLZ

Output Enable to Output
in LowZ

2,3

tGHQZ/tOF

Output Disable to Output
in HighZ

2

tali

Output Hold from Address,
CE, or OE Change

tWHGL

Write Recovery Time
before Read

28F256A·150
Min

150
120
120
50

1,2

ns

150
150
55
0

0
55

55

ns
ns

ns
ns

35

30

ns

ns

0

0

Unit

Max

ns

0

0

ns

6

6

,...s

NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3. Guaranteed by design.
Vee POWER-UP

STANDBY

DEVICE AND
ADDRESS SELEC1lON

• OUTPUTS ENABLED

DATA

Y~UD

STANDBY

AODRESSES STABLE

ADlJRESSES

( - - - - - - - t.v.y (toe> - - - - - - . . , . . - (

twHOL
iiE(W)

VAUD OUTPUT

5.0. J .
Vee ..

0.

290243-9

Figure 6. AC Waveform for Read Operations

•

28F256A

AC CHARACTERISTICS-For Write/Erase/Program Operations(1)
Versions
Characteristic .

Symbol

28F256A-150

28F256A-120

Notes

Min

Min

Max

Unit

Max

150

ns

0

0

ns

60

60

ns

50

50

ns

10

10

ns

6

6

/ks

0

0

/ks

Chip Enable Set-Up
Time before Write

20

20

ns

tWHEH/tCH

Chip Enable Hold Time

0

0

ns

tWLWH/twP

Write Pulse Width

60

60

ns

tWHWL/tWPH

Write Pulse Width High

20

20

ns

tWHwH1

Duration of
Programming Operation

3

10

10

tWHWH2

Duration of
Erase Operation

3

9.5

9.5

ms

tVPEL

Vpp Set-Up Time to
Chip Enable Low

2

1.0

1.0.

/ks

120

tAVAV/tWC

Write CYc:le Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tDVWH/tDS

Data Set-Up Time

tWHDX/tDH

Data Hold Time

tWHGL

Write Recovery Time
before Read

tGHWL

Read Recovery Time
before Write

tELWL/tCS

2

.,

..

/ks
.

!

NOTES:
1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to AC Charac.
teristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter

Notes

Chip Erase Time

1,3,4

Chip Program Time

1,2,4

28F256A-120
Min

Erase/Program Cycles

1,5

10,000

28F256A-150

Typ

Max

1

10

0.5

3

100,000

Min

10,000

Unit

Typ

Max

1

10

0.5

3

100,000

sec
sec
cycles

NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Dala taken at 2S"C,
12.0V Vpp, at 0 cycles.
.
2. Minimum byte programming time excluding system overhead is 16 fLs program + 6 fLs write recovery), while maximum is
400 fLs/byte (16 fLs x 2S loops allowed by algorithm). Max chip programming is specified lower than the worst case allowed
by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming Prior to Erasure.
4. Excludes System-Level Overhead.
S. Refer to RR-60 "ETOX:' II Flash Memory Reliability Data Summary for typical cycling data and failure rate calculations.

3-18

infel~

28F256A

99.9

/v

99

, ..

/

90

V ....

L

80

,

70
60
50
40

.',

30
20

",.

,f../
.(/

V

/

95

,/

V

,

/

,,

,,

,

...

10

0.1
0.5

0.630.750.881.01.1 L3

2.5

3.8

5.0

Chip Program Time (sec)
- - - 12V; 10 kc; 23"C
-------11.4V; 10 kc; 70"C
- - - - 12V; 100 kc; 23"C

290243-10

Figure 7. 28F256A Typical Programming Capability

1~

I

IS

!

,;
6

/
15

!

I

/

;

1.25

/

1

'." .- -'

~

5

1.0

I

.'

,

/
O~

.I
I

0.5

o

20

/V

J

I

.'
10

,,

I

0.75
6

.- -- --

"

30

.a

50

,
-.
60

,,
,,

I

J
./

70

60

90

100

110

120

130

TEMP (OC)
- - 1 k Cycl.s
----- 10k Cycles

---- 100k Cycles ,

Figure 8. 28F256A Typical Program Time at 12V
3-19

290243-11

28F256A

99.9

I

'/
,
I ,, 'it
,I' •

99

95

V

90
80
70

/

~ 60
...
50

8

'/

,",

,,

,','

/

40
30

/

,,.

,,

/

If '/

'

I

20

V

10

,

"

,~'

I , '1,' '

5

I,.,'/ i

28F2S••-120/150

I I, III

,01/

O.1
D.3

OS 0.7

1

~-200

2
3
4 5 6 78910
CHIP ERASE TIME (ne)

20

- - - 12V, 10 ke, 230C
----I'.4V, 10 ke, O"C
-------12V' 100 ke, 230C

290243-12

Figure 9. 28F256A Typical Erase Capability

1.8

1.6

"'. ,

"

0' 1.2

!
...
i!...

'.
i'. r-... .'. '

.

1.0

a..
5o.a

o

"

..

'. "

'r--. "- '. '.

'. .

.

I'.. ....... '.

0.8

D.2

.

I·...

10

20

30 40 50

60

'. ....

r--.. .... ' . '.

70

80

"

r--. .... ~ ' .

90 100 110 120 130 140

TEMP (OC)
_lkCy.1n
----- 10k Cy.itI
-100kCyaln

Figure 10. 28F256A Typical Erase Time at 12.0V
3-20

290243-13

_.

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAMMING

PROGRAM
VERlrY
COMMAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

l

{< VVVVVJ;
ADDRESSES

."

eg'l

...

CE (E)

CD

=-"

l>
0

;:1
<

-...

DE (6)

CD

0

3

CIJ

ro
.....

-

III

0....

WE

(Vi)

"........
0

CQ

.,u

I I~J I ~

DI

3
3

~'I
0

DATA (DO)

'0
CD

...
DI

fl

s.ov
Vee
ov

12V
vpp
VpPL

290243-14

N

CO
"11

N

en
en
:J>

_.
Vee POWER-UP .Ie
STANDBY

SET-UP ERASE
COMMAND

ERASE COMMAND

ERASING

ERASE
VERIFY
COMMAND

ERASE
VERIFICATION

STANDBY/ ,.
VCC POWER-DOWN
A

< (JO{)OU

l
~

) A

ADDRESSES

CE (E)
."

~i

c....
CD

.....
N

1.1
0

DE (Q)

:e
III

<
CD

c.l

N
I\)

~

0
....
3

-

WE

(iii)

1/1

....0

IT!

....
III

~JJ

I

~~11-1 \

1/1

CD

gI

DATA (DQ)

CD

ao·

:l
1/11

5.0V
Vee
OV

12V
Vpp
VpPl

290243-15

N

Q)

."
N
C1I

en

~

28F256A

ALTERNATIVE CE-CONTROLLED WRITES
Versions
Sy~bol

28F256A-120

Notes
Characteristic

Min

Max

28F256A-150

Min

Unit

Max

150

ns

0

0

ns

80

80

ns

50

50

ns

10

10

ns

6

6

/Ls

0

0

/Ls

Write Enable Set-Up Time
before Chip-Enable

0

0

ns

tEHWH

Write Enable Hold Time

0

·0

ns

tELEH

Write Pulse Width·

1

70

70

ns

tEHEL

Write Pulse Width High

20

20

ns

tVPEL

Vpp Set-Up Time

2

1.0

1.0

/Ls

tAvAV

Write Cycle Time

tAVEL

Address Set-Up Time

tELAX

Address Hold Time

tDVEH

Data Set-Up Time

tEHDX

Data Hold Time

tEHGL

Write Recovery Time
before Read

tGHEL

Read Recover Time
before Write

tWLEL

120

2

to Chip-Enable Low
NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip· Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (with a longer Write-Enable timing waveform) all set-up, hold and
inactiye Write-Enable times should be measured relative to the Chip,Enable waveform.
2. Guaranteed by design.

3·23

_.,
PROGRA..
Vee POWER-UP a,

STANDBY

SO-UP PROGRA ..
CO....AND

PROGRA.. CO....AND
LATCH ADDRESS a, DATA

PROGRAIIMING

VERIFY

PROGRA..

CO....AND

VERIFICATION

STANDBY/
" Vee POWER-DOWN

tAt 00000,11

€:
•

ADDRESSES

~
"C

;1
....

iEeE)

54

>

;:
3

!

DE (0)

I

CE (ii)

l;

Co)

0

~"~

...0'

i"ji;

N
CIt

~

;

"

DATA (DO)

:I
:I

5"

CQ

i

i0"
~

\:LQV
(tCE)
s.OV
.. Vee

OV

III
"12V

Vpp
VppL

-J

~~PEL

.

\

-

'--,

290243-16

int:el..

28F256A

ORDERING INFORMATION

Ip121SIF121Sl s 1AI-11121 0 1

~

LPACKAGE
P 32-PIN PLASTIC DIP
N 32-LEAD PLCC

=
=

VALID COMBINATIONS:
P2SF2S6A-120
P28F256A-150

L

ACCESS SPEED ens)
120 ns
IS0no

, 290243-17

N28F256A-120
N28F256A-150

ADDITIONAL INFORMATION
ER-20,
ER-24,
RR-60,
AP-316,
AP-325,

"ETOX II Flash Memory Technology"
"Intel Flash Memory"
"ETOX II Flash Memory Reliability Data Summary"
"Using Flash Memory for In-System Reprogramming
Nonvolatile Storage"
"Guide to Flash Memory Reprogramming"

Order Number
294005
294008
293002
292046
292059

REVISION HISTORY
Number

Description

004

Removed Preliminary Classification.
Removed 200 ns speed bin.
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000.
Clarified AC and DC test conditions.

005

Corrected AC waveforms.

3-25

.
28F512
.'
512K (64K x 8) CMOS FLASH MEMORY

• Electrical Chip-Erase
•
• 100,000 Erase/Program
•
•
Power Consumption
•
Active Current
Flash
- 1 Second Typical Chip-Erase

Quick-Pulse Programming Algorithm
-10 ""s·Typical Byte-Program
- 1 Second Chip-Program

•
• -±

Command Register Architecture for
Mlcroprocessor/Microcontroller
Compatible Write Interface

Noise Immunity Features
10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing

Cycle Typical

12.0V ± 5% Vpp

High-Performance Read
- 120 ns Maximum Access Time

CMOS Low
- 10 mA Typical
- 50 ""A Typical Standby Current
- OW Data Retention Power

•

•

ETOXTM " Nonvolatile Flash
Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience

•

JEDEC-Standard Pinouts
- 32-Pln Plastic Dip
- 32-Lead PLCC

Integrated Program/Erase Stop Timers

(See Packaging Spec., Order #231369)

•

Extended Temperature Options

Intel's 28F512 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F512 adds electrical Chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F512 increases
memory flexibility, while contributing to time- and cost-savings.
The 28F512 is a 512-kilobit nonvolatile memory organized as 65,536 bytes of 8 bits. Intel's 28F512 is offered
in 32-pin plastic dip or 32-lead PLCC packages. Pin assignments conform to JEDEC standards for byte-wide
EPROMs .
. Extended erase and program cycling capability is designed into Intel's ETOX II (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric f,ield combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F512
performs a minimum of 10,000 erase and program cycles well within the time limits of the Quick-Pulse ProgrammingTM and Quick-Erase™ algorithms.
Intel's 28F512 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 120 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. MaXimum standby current of 100 p.A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX II process base, the 28F512 levers years of EPROM experience to yield the highest leliels of
quality, reliability, and cost-effectiveness.

3-26

November 1992
Order Number: 290204-007

inteL

28F512

C-+
s--+

I

P

---+
-+

rt

_I INPUT/OUTPUT
I BUFFERS

.1 ERASE VOLTAGEI

STATE
CONTROL
COt.tt.tAND
REGISTER
INTEGRATED
STOP
TIt.tER

SWITCH

TI

..

TO ARRAY
SOURCE

~

I--

A.

"4

PGt.t VOLTAGE I
SWITCH

CHIP -ENABLE
OUTPUT ENABLE
LOGIC

'"

+

Y-DECODER
STB
15

r-

:I:

"
Y

3
VI

~

.
'"cc

X-DECODER

7STB

r-+
r-+
•
•
•
•
r-+

DATA
LATCH

Y-GATING

524,288 BIT
CELL t.tATRIX

+-

290204-1

Figure 1. 28F512 Block Diagram

3-27

28F512

Vee
WE

~

~

Co)

..: ..: z

NC
A14
A13

A7

A8

A6

A9
Al1 '

A4

;: JlI~

0

z

A,...
A13 .

As

A8

N28F"512
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW

Ag

OE

A3

A10

A2

OE

CE

AI

A10

DQ7 .' '
DQa

All

AO

CE

000

DQ7

DQS .
DQ4

GraphIc Not to Scale

DQ3

o.

N

in

to')

....

U')

CD

cg;:>gggg

290204-3
290204-2

Figure 2. 28F512 pin Configurations
Table 1. Pin Description
Symbol

Type

Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle ..

Ao-AI5

INPUT

DQo-DQ7

INPUTIOUTPUt . DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.

CE

INPUT

CHIP ENABLE: Activates the device's controllo~ input buffers,
decoders and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.

OE

INPUT

OUTPUT ENABLE: Gates,the devices output through the data buffers
during a'read cycle. OE is active low.

WE

INPUT

WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse.
Note: With Vpp s: 6.5V, memory contents cannot be altered.

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V, ± 10%)

Vss

GROUND

NC

NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.

3-28

infel .

28F512

APPLICATIONS
The 28F512 flash memory provides nonvolatility
along with the capability to typically perform over
100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F512 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and datatables are required, the 28F512's reprogrammability
and nonvolatility make it the obvious and ideal replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable BIOS, system manufacturers can easily accommodate last-minute changes as
revisions are made.

circuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F512, code updates are implemented locally
via an edge-connector, or- remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for. data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medicai instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.

In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for a" networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.

Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit we" with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F512s tied to the 80C186 system bus.
The 28F512's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.

For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F512 flash memory offers a solid
state alternative in a minimal form factor. The
28F512 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy. for code and
data table reading. Additiona"y, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
. disk-based systems to fail. -

With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F512 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.

The need for code updates pervades a" phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F512 allows in-

3-29

28F512

Vee

Vee

80C186
SYSTEM BUS

Vee

Vee

Al-A16~---------.I Ao-A 15

000-007

+----------1
28F512

28F5l2
MCS1 _ _ _ _ _~---~

cr

t---+I

cr

>-----.. WE
I--~WE

AO

Ri'i----------....

i5E

1---+1 i5E
290204-5

Figure 3. 28F512 in a 80C186 System
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.

PRINCIPLES OF OPERATION
. Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F512 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power sup~
plies during erasure and programming; and maxi(mum EPROM compatibility.

Integrated Stop Timer
Successive command write cycles define the duration of program and erase operations; specifically,
the program or erase time durations are normally
terminated by .associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and' erase .pulse
durations are minimums only. When the stop timer
terminates a program or erase operation, the device
enters an inactive state and remains inactive until
receiving the appropriate verify or reset command.

In the absence of high voltage on the Vpp pin, the
28F512 is a read-only memory. Manipulation of the
external. memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure ~nd programming of the device. All
functions associated with altering memory contents-Intelligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.

Write Protection
The command register is only active when Vpp is at
high voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available' only when memory
updates are desired. When Vpp = VPPL, the contents of the register default to the read command,
making the 28F512 a read-only memory. In this
mode, the memory contents cannot be altered.

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,

3-30

intel.,

28F512

Table 2. 28F512 Bus Operations
Pins

Vpp(1)

Ao

Ag

CE

Read

VpPL

Ao

Ag

Output Disable

VPPL

X

X

OE

WE

VIL

VIL

VIH

Data Out

VIL

VIH

VIH

Tri-State
Tri-State

DOO-D07

Operation

READ-ONLY

READ/WRITE

Standby

VpPL

X

X

VIH

X

X

Intelligent Identifier (Mfr)(2)

VPPL

VIL

VIO(3)

VIL

VIL

VIH

Data = 89H

VIL

VIL

VIH

Data = B8H

VIL

VIH

DataOut(4)

Intelligent Identifier (Device)(2)

VpPL

VIH

VIO(3)

Read

VPPH

Ao

Ag

VIL

VpPH

X

X

. VIL

VIH

VIH

Tri-State

VPPH

X

X

VIH

X

X

Tri-State

Ao

.Ag

VIL

VIH

VIL

Data In(6)

. Output Disable
Standby(5)
Write

VPPH

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses .Iow.
3,VID is the Intelligent Identifierhigh voltage, Refer to DC Characteristics.
4. Read operations with Vpp= VPPH may access array data or the Intelligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby),
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

Output Disable

Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly

With Output-Enable at a logic-high level (VIH), output
from the device is disabled; Output pins are placed
in a high-impedance state;

available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection). The 28F512 is designed to acc.ommodate either design practice, and to encourage optimization
of the processor-memory interface.

Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F512's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable· signal.
If the 28F512is deselected during erasure, programming, or program/erase verification, the
device draws active current until the operation is
terminated.

The two-step ·program/erase write sequence to the
Command Register provides additional software
write protection.
BUS OPERATIONS
Read
The 28F512 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
, (OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.

Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B8H). Programming .equipment automatically matches thedevice· with .its proper erase· and programming algorithms.

When Vpp is high (VPPH), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
erase verification. When Vpp is low (VppLl, the read
operation can only access the array data.

3-31

intel·

28F512

With Chip-Enable and Output-Enable at a logic low
level, raising A9to high voltage VID (see DC,Characteristics) activates the operation. Data read'from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F512 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B8H).'

used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VIU, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
, Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.

Write

COMMAND DEFINITIONS

Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The cOntents of the register
serve as input to the internal state-machine. The
state-machine, ,outputs dictate the function of the
device.

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.

The command register itself does not occupy an addressable memory location. The register is a latch

'Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F512 register
commands.

Table 3_ Command Definitions
Command

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operatlon(1) Address(2) Data(3) Op~ratlon(1) Address(2) Data(3)
Write

X

OOH

3

Write

X

90H

Read

(4)

(4)

2

Write

X

20H

Write

X

20H

Read Memory

1

Read Intelligent Identifier Code(4)
Set-up Erase/Erase(S)
Erase Verify(S)

2

Write

EA

AOH

Read

X

EVD

Set-up Program/Program(6)

2

Write

X

40H

Write

PA

PD

Program Verify(6)

2

Write

X

COH

Read

X

PVD

Reset(7)

2

Write

X

FFH

Write

X

FFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. 10 = Data read from location IA during device identification (Mfr = 89H, Device = B8H).
EVD = Data read from location EA during erase verify.
,
PO = Data to be programmed at location PA. Data is latched on the risi.ng edge of Write-Enable.
pVD = Data read from location PA during,program verify. PA is latched on the Program command. ,
4. Following the Read Intelligent 10 command. two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Quick-Erase™ algorithm.
6. Figure 4 illustrates the Quick-Pulse Programming™ algorithm.
7. The second bus cycle must be followed by the desired command register write.

3-32

28F512

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.

Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.

The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F512, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for speCific timing
parameters.

The 28F512 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are era,sed.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.

Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising AS to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
"

In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 5, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure" of the 28F512.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.

"

The 28F512 contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated" by writing
SOH into the command register. Following the command write, a read cycle from address 00001:"1 retrieves the m!'lnufacturer code of 8SH. A read cycle
from address 0001 H returns the device code of
B8H. To terminate the operation, it is necessary to
write another valid command into the register.

Set-up Program/Program Commands
Set-up Erase/Erase Commands

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.

"Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched" on the rising
edge of the Write-Enable pulse. The rising"edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable," used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up follQwed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
3-33

intel .

28F512
,

greatly reduces oxide stress and the probability of
failure-increasing time to wearout by a factor of
100,000,000.
.

Program-Verify Command
The 28F512 is programmed on abyte-by-byte basis.
Byte programming may occu(sequentially or at random. Following each programming operation,the
byte just programmed must be verified.

The 28F512 is specified for a minimum of 10,000
program/erase cycles. The device .is programmed
and erased using Intel's Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic
approach uses a series of operations (pulses), along
with byte verification, to completely and reliably
erase and program the device.

The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.

For further information, see Reliability Report RR-SO
(ETOX-II Reliability Data Summary).

. The 28F512 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
th~ programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4,
the 2817512 Quick-Pul~e Programming algorithm,iIlustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.

QUICK-PULSE PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 p.s duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify oli the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 4 illustrates the Quick-Pulse Programming algorithm.

Reset Coinniand
QUICK-ERASE ALGORITHM

A reset command is provided as a means to safely
abort the er.ase- or program-command sequences.
Followil')g either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of mlilmory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with· a read of memory contents; The
28F512 is erased when shipped from the factory.
Reading FFH data from tlie device would immediately be followed by device programming. .

EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some SUp"
pliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. Howev.
er, re9undancy requires that cell size be doubledan expensive solution.

For devices being erased and .reprogrammed, uniform and reliable erasure is ensured by fir~t programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately one second.

Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling' reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide Increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one~tenth
that of common EEPROMs, minimizing the probability of oxide defects iii the region. Finally, the peak
electric field during erasure is approximately 2 MV/ ' .
cm lower than EEPROM. The lower electric field

Erase executiorithen continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to· the erased state. EraSe
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that. stored address location. Erasure typically.occurs in one second. Figure 5 illustrates the Quick-Erase algorithm.

3-34

intel~

28F512

Bus
Operation

Command

Standby

Comments

Wait for VPP Ramp to VPPH(1)

Initialize Pulse-Count

= 40H

Write

Set-up
Program

Data

Write

Program

Valid Address/Data

Duration of Program
Operation (tWHWH1)

Standby
Write

Program(2)
Verify

Data = COH; Stops Program
Operation(3) .

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write

Standby

Read

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VPPL(1)

290204-6
NOTES:
1. See DC Characteristics for value of VPPH and VPPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.

3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de·
vice.

Figure 4_ 28F512 Quick·Pulse Programming Algorithm

3·35

28F512

Bus
Operation

Comments

Command

Entire memory must = OOH
before erasure

Use Quick-Pulse
. Programming™ Algorithm
(Figure 4)
Standby

WaitforVpp Ramp to VpPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data = 20H

Write

Erase

Data = 20H

Duration of Erase Operation
(tWHWH2)

Standby
Write

Erase(2)
Verify

Standby

tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Read

Standby

290204-7
NOTES:
1. See DC Characteristics for value of VPPH and VPPL.
2. Erase Verify is performed only after chip-erasure. A
final read I compare may be performed (optional) after
the register is written with the read command.

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppd1)

3. Refer to principles of operation.
.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 5. 28F512 Quick-Erase Algorithm

3-36

int'et

28F512

DESIGN CONSIDERATIONS

Power Up/Down Protection
The 28F512 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F512 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing is not required. Internal circuitry in the 28F512 ensures that the command register is reset to the read mode on power
up.

Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while. deselected devices maintain the low
power standby condition.

. A system designer must guard against active writes
for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of· memory contents only
occurs after successful completion of the two-step
command. sequences.

28F512 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F512 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F512.

Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (IcC> issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

Table 4. 28F512 Typical Update
Power Dissipation(4)

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 JLF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.

Notes

Power Dissipation
(Watt·Seconds)

Array Program/
Program Verify

1

0.085

Array Erase/
Erase Verify

2

0.092

One Complete Cycle

3

0.262

Operation

Place the high-frequency, low-inherent-inductan~e
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 JLF electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace .inductance, and will supply
charge to the s~aller capacitors as needed.

NOTES:
,
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x Typical # Prog Pulses
(tWHWHl x IpP2 Typical + tWHGL x IpP4 Typical)) +
[Vcc x # Bytes X Typical # Prog Pulses (tWHWHl x
ICC2 Typical + tWHGL x ICC4 Typical).
2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp(lpP3 Typical x .tERASE Typical + IpP5 Typical x
tWHGL x # Bytes)] + [Vcc(lcC3 Typical x tERASE Typical + ICC5 Typical x tWHGL x # Bytes»).
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited
number of samples from production lots.

Vpp Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

3·37

28Fs12

Vpp Supply Voltage with
.
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2, 3)

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read .................. O·C to + 70·C(1)
During Erase/Program ......... O·C to + 70·C(1)

Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)

Operating Temperature
During Read ............... -40·C to + 85·C(2)
During Erase/Program ...... -40·C to + 85·C(2)

Output Short Circuit Current ............. 100 mA(4)
NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Temperature Under Bias ....... -10·C to + 80·C(1)
Temperature Under Bias ....... -50·Cto +95·C(2)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Storage Temperature .......... - 65·C to + 125:C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2. 3)

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
3. Minimum De input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum De voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
4. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 r,s.
5. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS
Symbol

Limits

Parameter

Comments

Unit

Min

Max

TA

Operating Temperature(l)

0

70

·C

For Head-Only and
Read/Write Operations
for Commercial Products

TA

Operating Temperature(2)

-40

+85

·C

For Read-Only and
Read/Write Operations
for Extended Temperature Products

Vee

Vee Supply Voltage

4.50

5.50

V

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
Symbol

Parameter

Notes

Limits
Min

Typ(4)

Max

Unit

Test Conditions

III

Input Leakage Current

1

±1.0

p.A

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±10.0

p.A

Vee = Vee Max
VOUT = Vee or Vss

lees

Vee Standby Current

1

0.3

1.0

mA

Vee = Vee Max
CE = VIH

leel

Vee Active Read Current

1

10

30

mA

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Curtent

1,2

1.0

10

mA

Programming in Progress

lee3

Vee Erase Current

1,2

5.0

15

mA

Erasure in Progress

lee4

Vee Program Verify
Current

1,2

5.0

15

mA

Vpp = VpPH
Program Verify in Progress

.

3-38

int'et

28F512

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
(Continued)

Symbol

Parameter

Limits

Notes
Min

iee5

Vee Erase Verify Current
Vpp Leakage Current

1

IpPl

Vpp Read Current, Standby
Current, or ID Current

1

Test Conditions

Max

5.0

15

mA

Vpp = VPPH
Erase Verify in Progress

±10.0

/LA

Vpp:S:; Vee

200

/LA

Vpp> Vee

1,2

ipps

Unit

Typ(4j

90

±10.0

Vpp:S:; Vee

IpP2

Vpp Programming Current

1,2

8.0

30

mA

Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

30

mA

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

mA

Vpp = VPPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

mA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0 ..8

V

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOHl

Output High Voltage

VID

Ag Intelligent Identifier Voltage

110

Ag Intelligent Identifier Current

VPPL

Vpp during Read-Only
Operations

VPPH

Vpp during Read/Write
Operations

VLKO

Vee Erase/Write. Lock Voltage

Vee

+ 0.5

0.45
2.4
11.50
1,2

..

-

V
V

IOL = 5.8mA
Vee = Vee Min

V

IOH = -2.5 mA
Vee = Vee Min

13.00

V

200

/LA

90

0.00

6.5

11.40

12.60

2.5

V·

V

Ag = VID

NOTE: Erase/Program are
Inhibited when Vpp = VPPL

-

V

DC CHARACTERISTICS-CMOS COMPATIBLE--Commercial Products
Symbol

Parameter

Limits

Notes
Min

Typ(4j

Unit

Test Conditions

""ax

III

Input Leakage Current

1

±1.0

/LA

Vee = Vee Max
VIN = Vee or VSS

ILO

Output Leakage Current

1

±10.0

/LA

Vee = Vee Max
VOUT = Vee or Vss

lees

Vee Standby Current

1

50

100

p.A

Vee = Vee Max
CE = Vee ±0.2V

leel

Vee Active Read Current

1

10

30

mA

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

.
3-39

infel~

28F512

DC CHARACTERISTICS-CMOS COMPATIBLE-Commercial Products (Continued)
Symbol

Parameter

Limits

Notes
Min

Unit

Typ(4)

Max

Test Conditions

lee2

Vee Programming
Current

1,2

1.0

10

mA

Programmirig in Progress

lee3

Vee Erase Current

1,2

5.0

15

mA

Erasure in Progress

lee4

Vee Program Verify
Current

1,2

5.0

15

mA

Vpp";' VPPH
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

15

mA

VPP=VPPH
Erase Verify in Progress

Ipps

VPP Leakage Current

1

±10.0

/LA

VPP::;; Vee

IpP1

VPP Read Current, ID
Current, or Standby
Current

1

200

/LA

Vpp> Vee

±10.0

VPP Programming
Current

1,2

IpP3

VppErase Current

1,2

IpP4

VPP Program Verify
Current

IpP5

VPP Erase Verify Current

IpP2

90

8.0

VPP::;; Vee

30

mA

VPP = VPPH
Programming in Progress

4.0

30

mA

Vpp"; VPPH
Erasure in Progress

1,2

2.0

5.0

mA

VPP = VPPH
Program Verify in Progress

1,2

2.0

5.0

mA

VPP = VPPH
Erase Verify in Progress

0.8

V

/

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

Output High Voltage

Vee

+ 0.5

0.45
0.85 Vee

V
V

V

Vee - 0.4

VOH2

IOL = 5.8mA
Vee = Vee Min
IOH = -2.5 mA,
Vee = Vee Min
IOH = -100 /LA,
Vee = Vee Min

I

VID

Ag Intelligent Identifier
Voltage

liD

Aglntelligent Identifier
Current

VpPL

VPP during Read-Only
Operations

VpPH
VLKO

11.50

13.00

V

Ag = VID

200

/LA

Ag = VID

0.00

6.5

V

VPP during Read/Write
Operations

11.40

12.60

V

Vee Erase/Write Lock
Voltage

2.5

1,2

90

V

3-40

NOTE: Erase/Program
are Inhibited when
VPP = VPPL

28F512
,

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Extended Temperature
Products .
Symbol

Parameter

Limits

Notes
Min

Typ(4)

Unit

Test Conditions

Max

III

Input Leakage Current

1

±1.0

/LA Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±10.0

/LA Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

0.3

1.0

rnA Vee = Vee Max
CE = VIH

lee1

Vee Active Read Current

1

10

30

rnA Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA

lee2

Vee Programming Current

1,2

1.0

30

rnA Programming in Progress

lee3

Vee Erase Current

1,2

5.0

30

rnA Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

30

rnA Vpp = VPPH
Program Verify in Progress

lee5

Vee Erase Verify Current

1;2

5.0

30

rnA Vpp = VpPH \
Erase Verify in Progress

Ipps

Vpp Leakage Current

1

IpP1

Vpp Read Current, Standby
Current, or 10 Current

1

90

±10.0

/LA Vpp ~ Vee

200

/LA Vpp > Vee

±10.0

Vpp

~

Vee

IpP2

Vpp Programming Current

1,2

8.0

30

rnA Vpp = VpPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

30

rnA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

rnA Vpp = VPPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

rnA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VID

Ag Intelligent Identifier Voltage

0.8
Vee

+ 0.5

0.45
2.4
13.00

11.50
1,2

V
V
V

IOL = 5.8 rnA
Vee = Vee Min

V

IOH = -2.5 rnA
Vee = Vee Min

V

110

Ag Intelligent Identifier Current

VPPL

Vpp during Read-Only
Operations

0.00

6.'5

V

VPPH

Vpp during Read/Write
Operations

-11.40

12.60

V

VLKO

Vee Erase/Write Lock Voltage

90

2.5

3-41

500

/LA Ag

V

= VID

NOTE: Erase/Program are
Inhibited when Vpp = VPPL

28F512

DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
. ' . .
.
Products
Symbol

Parameter

,

. Limits

Notes

Typ(4)

Min

Unit

Test Conditions

Max

III

Inpot Leakage Current

1

±1.0

fJ.A

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±10.0

fJ.A

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

50

100

fJ.A

Vee = Vee Max
CE = Vee ±0.2V

lee1

Vee Active Read Current

1

10

50

mA

Vee
f

= Vee Max, CE = VIL
= 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

1,2

1.0

10

mA

Programming in Progress

Ices

Vee Erase Current

1,2 '

5.0

15

mA

Erasure in Progress

leC4

Vee Program Verify
Current

1,2

5.0

30

mA

Vpp = VPPH
Program Verify in Progress

lees

Vee Erase Verify Current

1,2

5.0

30

rnA

VPP = VPPH
Erase Verify in Progress

Ipps

VPP Leakage Current

1

IpP1

VPP Read Current, 10
Current, or Standby
Current

1

90

±10.0

fJ.A

VPP ~ Vee

200

fJ.A

Vpp> Vee

±10.0

VPP ~ Vee

IpP2'

VPP Programming Current

1,2

8.0

30

mA

Vpp = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

4.0

30

mA

VPP = VPPH
Erasure in Progress

IpP4

VPP Program Verify
Current

1,2

2.0

5.0

mA

VPP ~ VPPH
Program Verify in Progress

Ipps'

VPP Erase Verify Current

1,2

2.0

5.0

mA

VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

V

VIH

input High Voltage

0.7 Vee

VOL

Output Low Voltage

Vee

+ 0.5

0.45

3-42

V
V

IOL = 5.8mA
Vee ~ Vee Min

infel .

28F512

DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products (Continued)
Symbol

Parameter

Limits

Notes
Min

VOH1

Output High Voltage

Unit

Test Conditions

V

IOH = - 2.S mA,
Vee = Vee Min

Max

0.8SVee

IOH = -100,...A,
Vee = Vee Min

Vee - 0.4

VOH2
VIO

Typ(4)

Ag Inteiligent Identifier Voltage

11.S0
1,2

90

13.00

V

110

Ag Intelligent Identifier Current

SOQ

,...A

VPPL

VPP during Read-Only Operations

0.00

6.S

V

VPPH

VPP during Read/Write Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock Voltage

2.S

As = VIO
Ag

= VIO

NOTE: Erase/
Program
are Inhibited
when
VPP = VpPL

V

CAPACITANCE TA = 2SoC, f = 1.0 MHz
Symbol

Parameter

Limits

Notes
Min

CIN

Address/Control Capacitance

3

8

pF

COUT

Output Capacitance

3

12

pF

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = S.OV, VPP = 12.0V, T
currents are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, bl,lt based on a limited number of samples from production lots.

3-43

Conditions

Unit
Max

= OV
VOUT = OV
VIN

=

+2S'C. These

infel .

28F512

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.4 ~• .r'::"':"---~------

1.3V

INPUT
0.45

lN914

~:~

>

3.3K

TEST POINTS

1--......-0() OUT

290204-B

AC Testing: Inputs are driven at 2.4V for a logic "1" and O.4SV for
a logic "0". Testing measurements are made at 2.0V for a logic
"1" and O.BV for a logic "0". Rise/Fall time,; 10 ns.

290204-9
CL = 100 pF
CL includes Jig Capacitance

AC TEST CONDITIONS
Input Rise an.d F,all Times (10% to 90%) •..•.. 10!ls
Input Pulse Levels ~ .......•.. ,.•.•. 0.45Vand 2.4V
Input Timing Reference Level ....•.• O.BV and 2.0V
Output Timing Reference Level ...•.. O.BV and 2.0V

AC CHARACTERISTICS-Read-Only Operations
Verslons(l)
Notes
Symbol
tAVAV/tRC

Characteristic

N28F512-120
TN28F512-120
P28F512-120
TP28F512-120
M,in

Read Cycle Time

N28F512-150
P28F512-150

Max

Min

120

Unit

Max

150

ns

tELov/tcE

Chip Enable Access Time

120

150

ns

tAVOV/tACC

Address Access Time

120

150

ns

tGLOV/tOE

Output Enable Access Time

55

ns

tELOX/tLZ

Chip Enable to Output in Low Z

,tEHOZ

Chip Disable ,to Output in High Z

tGLOX/tOLZ

Output Enable to Output in Low Z

tGHOZ/tOF

Output Disable to Output il') High Z

2

tOH

Output Hold from Address, CE, or
OEChange

2,4

tWHGL

Write Recovery Time before Read

50
2,3

0

2
' 2,3

55

'NOTES:
1. Model number prefixes: N= PLCC, P = POIP, T = Extended Temperature.

3-44

35
)

ns
ns

0
30

6

2. Sampled, not 100% tested.
, 3. Guaranteed by design.
4. Whichever occurs first.

55

0

0

ns

0

ns

0

'ns

6

,..,S

:S" .

c[
•

Vee POWER-UP

STANDBY

DEVICE AND
ADDRESS SElECTION

ADDRESSES

OUTPUTS ENABLED

DATA VALID

STANDBY

ADDRESS STABLE

-I

t AVAV (t RC)

~
~

Vcc POWER-DOWN

. CE (El

CIl
9l

~

=e

=
!.

DE (G)
N

~
~ 3

at

c.l

U1

I-

II

...cr

i
g

;Jl
....

-I

N

WE (w)
~LOV (toE>

I---- tELOV (teE>

-1

~LOX (toLZ)-j

CD

iil

f

1 twHGL 1

toH

tELOX (tLZ)

DATA (DO)

s.OV

~J

Vee

· , 1_
. t
1

HIGHZ

-

--

\\~\\4~-~

VALID OUTPUT

(tAct>

( tI ( ( l
HIGH Z

AVOV

~
290204-10

28F512

AC CHARACTERISTICS-Write/Erase/Program Operatlons(1)
Versions

,

Symbol

Notes

Characteristic

tAVAV/tWC

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

28F512-120
Min

28F512-150
Min

Max

Unit

Max

150

ns

0

0

ns

60

60

ns

120

tDVWH/tDS

DataSet-up Time

50

50

ns

tWHDX/tDH

Data Hold Time

10

10

ns

tWHGL

Write Recovery Time before Read

6

6

/Ls

tGHWL

Read Recovery Time before Write

0

0

/Ls

20

20

ns

tELWL/tCS

2

Chip Enable Set-Up Time before Write

tWHEH/tCH

Chip Enable Hold Time

0

0

ns

tWLWH/tWP

Write Pulse Width

60

60

ns
ns

20

20

tWHWH1

Duration of Programming Operation

3

10

10

/Ls

tWHWH2

Duration of Erase Operation

3

9.5

9 ..5

ms

tVPEL

Vpp Set-Up Time to Chip Enable Low

2

1.0

1.0

tWHWL/tWPH Write Pulse Width High

-

/Ls

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
'
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating ,the need for a maximum
specification.'
, ;
.
'

'

\

ERASE AND PROGRAMMING PERFORMANCE
limits

"

Parameter

Notes

Min

Typ

Chip Erase
Time

1,3,4

1

Chip Program
Time

1,2,4

1

Erase/Program '
Cycles

1,5

TN/TP28F512-120(6)

N/P28F512:120, 150

10,000

Max

,

100,000

Min

Unit

Typ

Max

10

l'

10

Sec

6.25

1

6.25

Sec

1,000

Cycles

NOTES:
1, "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25·C, 12.0V
Vpp at 0 cycles.
2. Minimum byte programming time excluding system overhead is 16 /Ls (10 /Ls program + 6 /Ls write recovery), while
maximum is 400 /LsI byte (16 /Ls x '25 loops allowed by algorithm). Max chip programming time is specified lower than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte,
3. Excludes OOH Programming Prior to Erasure,
'4. Excludes System-Level Overhead.
5, Refer to RR-60 "ETOX II Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Extended temperature products

3-46

intel~

28F512

v

3.75
35
315

V

]: 2.75

...

~ ~

~
~2.25
"-

;;j

.JII'
1.75
1.5
115

II

...... i-'"

~

/

V
..... ... ..
/' )1'

V

/

I

I

I

/

,"
",

I

V

J
V

1

10

20

30

40

50

60

70

00

90

100

110 120 130

TEMP (OC)
--.1k Cycles
·';'--10k Cycles
--_.. - lOOk Cycles

290204-14

Figure 7. 28F512 Typical Program Time at 12V
99.9

/::

//
99

j

95

60

30
20
10

o. 1

.(. ....

..
.
.
,.

/

.

.
... .
.
/

/

.'

.

, //

L

70
60
50
40

..f.·'"

/

/

90

""

..

1.25 1.5 1.752 2.252.5

7.5

10

Chip Program Time (sec)

- - - 1 2 V ; 10 kc; 230(:
·-----·11.4V; 10 kc; 70°C
- - - - 12V; 100 kc; 23°C

Figure 8. 28F512 Typical Programming Capability
3-47

290204-15

infel .

28F512

1.9

,.

1.8
1.7

\

1.6

,

..

1.5
~

1.4

!...

1.3

..,

'"

1=

... 1.2

~

..is
...

'.

,,

1.1

"i'..

1.0

o.9

,
,

,.

,
1'-•

,,

"

" ,

" ,
" ,

'"

0.8
0.7

r-.... "-

" "

...........

o.6
0.5

..... ,
"

,

...... " .

r-

o

10

20

30

40

50 60

70

TE~P

eo

90 100 110 120 130 140

(OC)

_.-1kCycles
.~-. 10k, Cycles
----- lOOk Cycles

290204-16

NOTE:
Does not include Pre-Erase program.

Figure 9. 28F512 Typical Erase Time at 12V
99.9

99

I

95

/

90

I

BO

,jil , "
' ,
,'1

,/,
/~'

/ ,'/

70

/ '

~ 60
'" 40
30

,

,"

I

.. 50

I 1/

~

/ , ,'/

20

I

10

I "
I,

1

O. 1
0.3

/;"
if

2BF512-120/150

,!i"
0.5

0.7

I I III
1

~-200

2
3
4 5 6 7 B 9 10
CHIP ERASE TI~E ( ••c)
- - - 12V; 10 kc; 230C
_ •• 11.4V; 10 kc; OOC
•••••• - 12V; 100 kc; 230C

NOTE:
Does not include Pre-Erase program.

Figure 10. 28F512 Typical Erase Capability
3-48

20

290204-17

Vee POWER-UP 6<
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS .t DATA

PROGRAMMING

PROGRAM VERIFY
COMMAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

l
8

V1H
ADDRESSES
VIL

V1H

fl
....

=-)0:eDI
0

<
CD

......
......

cr:
VIL

V1H

OE
V1L

0

3

Co)

,j,..
co

1/1

V1H

0

WE

'U

.
0

I\)

CD

"'11

....
(II

I\)

VIL

a::I
DI

3
3
5"

a::I

0

..

'U

-fl

V1H
DATA
V1L

CD
DI

S.OV
Vee

ov

12.0V
Vpp
VpPL

290204-19

intel .

28F512

ALTERNATIVE CE-CONTROLLED WRITES
Versions
Symbol

Characteristic

tAVAV

Write Cycle
Time

tAVEL

Notes

28F512-120,
Min

28F512-150
Min

Max

Unit

Max

120

150

ns

Address SetUpTime

0

0

ns

tELAX

Address Hold
Time

80

80

ns

tDVEH

Data Set-Up
Time

50

50

ns

tEHDX

Data Hold
Time

10

10

ns

tEHGL

Write
Recovery Time
before Read'

6

6

J.l.s

tGHEL

Read
Recovery Time
before Write

0

0

J.l.s

twLEL

Write Enable
Set-UpTime
before Chip
Enable

0

0

ns

tEHWH

Write Enable
Hold Time

0

0

ns

tELEH

Write Pulse
Width

' 70

70

ns

tEHEL

Write Pulse
Width High

20

20

ns

tVPEL'

VppSet-Up
Time to Chip
Enable Low

1.0

1.0

J.l.s

2.

1

2

,

NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
2. Guaranteed by design.

3-50

l
8

Yee POWER-UP
STANDBY

a:

SET-UP ERASE
COMMAND

V,.

ERASE COMMAND

ERASING

ERASE VERIFY
COMMAND

ERASE
VERIFICATION

STANDBY/
Vee POWER-DOWN

Jtt

000 A

ADDRESSES
V"

V,.
"II

.i!i
c

...ii1

!"

V,.

==

V,L

0

V,.

:a:n

i.

Cf
UI 3

...

CE
V"

..-

OE

III

Wi'

0

V,L

,

I T
N

CD

...

"11
CII

N

m

il
III

V,.

0

DATA

CD

V,L

CD

"g

il

=
0
:J

S.OY

III

Vee

OV
\YPEL

12.0V
Vpp
VppL

290204-20

_.

SET-UP PROGRAt.I
COt.lt.lAND

Vee POWER-UP &:
STANDBY
V1H

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAMt.lING

PROGRAM VERlry
COt.lt.lAND

PROGRAM
VERIFICATION

STANDBY!
Vee POWER-DOWN
E}()()(JA

€:
8

ADDRESSES
V1L

"TI

0

c

V1H

~

...

It

~

l>

..

WE
V1L

;:;

It

~

DI
It

l>
0

:e

V1H

DE
VIL

DI

-..
<

It

CAl

0

U.
3
I\)

-....

~

V1H

...""
(II

CE

1/1

0

'V
0
112

iil

3
3
3"

N

V1L

V1H

DATA
V1L

112

0

..

'V

It
DI

0"
~

11/

s.OV
Vee
OV
tYPEL
12.0V

I-

Vpp
VpPl

290204":21

intel·

28F512

Ordering Information

r

ITI P 121al F 1511 121-11 1210 I
LpACKAGE
IL---ACCESS SPEED (ns)
.
P 32-PIN PLASTIC DIP
120 ns
N 32-LEAD PLCC
150 n.

.

=
=

TEMPERATURE
T = EXTENDED (-40°C TO +85 0 C)
BLANK COMMERCIAL (ooC TO +70 0 C)

=

290204-13

Valid Combinations:
P28F512-120

N28F512-120

TP28F512-120

P28F512-150

N28F512-150

TN28F512-120

ADDITIONAL INFORMATION

Order Number

ER-20, "ETOXTM II Flash Memory Technology"

294005

ER-24, "Intel Flash Memory"

294008

RR-60, "ETOXTM II Flash Memory Reliability Data Summary"

293002

, AP-316, "Using Flash Memory for In-System Reprogrammable
Nonvolatile Storage"

292046
292059

AP-325 "Guide to Flash Memory Reprogrammirig"

REVISION HISTORY
Number

-

Description

006

Removed 200 ns speed bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC test conditions

007

Corrected AC Waveforms
Added Extended Temperature devices; TP28F512-120, TN28F512-120

3-53

28F010
1024K (128K, x 8) CMOS FLASH MEMORY
Electrical Chip-Erase
• -Flash1 Second
Typical Chip-Erase
• Quick-Pulse Programming Algorithm
~ 10 ,.,.s Typical Byte-Program
- 2 Second Chip-Program
• 100,000 Erase/Program Cycles Typical
• 12.0V ±,5% Vpp
High-Performance Read
- 90 ns Maximum Access Time
CMOS Low Power Consumption
-10 mA Typical Active Current
- 50 ,.,.A Typical Standby Current
- 0 Watts Dat~ Retention Power
Integrated Program/Erase Stop Timer

•
•

Register Architecture for
• Command
Mlcroprocessor/Mlcrocontroller
Compatible Write Interface
, Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum La~ch-Up Immunity
through EPI Processing

•

'.

•

•

ETOXTM " Nonvolatile Flash
Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience
JEDEC-Standard Pinouts
- 32-Pln Plastic Dip
- 32-Lead PLCC
- 32-Lead TSOP
(See Packaging Spec" Order # 231369)

• Extended Temperature Options
Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 2!3F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases
memory flexibility, while contributing to time- and cost-savings.

a

The 28F010 is
1024-kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel's 28F01O. is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
.
Extended erase and program cycling capability is designed into Inte,l's ETOX II (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field com·
bine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F010
performs a minimum of 10,000 erase and program cycles well within the time limits of the Quick-Pulse Programming and Quick-Erase algorithms.
! .
Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 90 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 ,...A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX II process base, the 28F01 0 levers years of EPROM experience to yield the highest levels of
quality, reliability, and cost-effectiveness.

3-54

November 1992
Order Number: 290207-008

infel .

28F010

Vee -+
Vss --+
VpP

--+

r

'I

ERASE VOLTAGE
SWITCH

1 I'

1

n

. J INPUT/OUTPUT

.I

BUFFERS

'"
- f--

TO ARRAY
SOURCE

STATE
CONTROL
COMMANO
REGISTER
INTEGRATED
STOP TIMER

~

PGM VOLTAGE
SWITCH

I

I

CHIP ENABLE
OUTPUT ENABLE
LOGIC

STB

DATA
LATCH

II

+
Y-DECODER
STI1

Ao-A 16

..
..

is
j

!a
'"
g

...

r---+

Y-GATlN~

f---+

•

X-DECODER

•
•
•
r---+

1,048,576 BIT
CELL MATRIX

~
290207-1

Figure 1, 28F010 Block Diagram
Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A16

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally

000-007

INPUT/OUTPUT

DATA INPUTIOUTPUT: Inputs data during memory write cycles;

latched during a write c y c l e . '

.

outputs data during memory read cycles. The data pins are active high
and float totri-state OFF when the chip is deselected or ~he outputs
are disabled. Data is internally latched during a write cycle.
CE

INPUT

CHIP ENABLE: Activates the device's controllo~ input buffers,
decoders and sense amplifiers. CE is active low; E high deselects the
memory device an!freduces power consumption to standby levels.

OE

INPUT

WE

INPUT

OUTPUT ENABLE: Gates tlie devices output thr()ugh the data buffers
during a read cycle. OEis active low.

.

WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
. and data is latched on the rising edge ofthe WE pulse..
Note: With Vpp S; 6.5V, memory contents cannot be altered.

Vpp

ERASE/pROGRAM POWER SUPPLY for writing the command
register, erasing the entire array,or programming bytes in the array..

Vee

DEVICE POWER SUPPLY (5V ±10%)

Vss

GROUND

.NC

NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.

3-55

infel .

28F010

28F010
Vpp

Vc'c

A1•

WE

A 1S

NC

A12

A1•

A7

A 1•

A.

As

,AS

Ag

A.

A11

A.

DE-

A2

A10

A1

CE

AO

0°7

00 0

D0.

0°1

0°5

0°2

DO,

VSS

D0.

~

1- ;; >'t >HI~ '"z

I
A7

A1•

AS
• AS
A.
A.

Au
As

N2aF010
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW

Ag
A11

DE

A2
A1

A10

AO

CE

00 0

0°7

290207-3
290207-2

A11
Ag

1

AS
, AU

DE'

0

,A 1•
NC

A 10

CE

STANDARD PINOUT
E28F010
32-LEAD TSOP
0.31" X 0.72"
TOP VIEW

WE
Vee
Vpp
A 1S
A 15
A12
A7
A.
As
A.

07
D.
05
0,

21

D.
Vss
O2
01
Do
Ao
A1
A2
A.

290207-17

liE
-'10

CE
~

De
Da

~\7

•

0,

Os
Vss
Dz
0,

Do

-'11

At
As

3

10
11
12

REVERSE PINOUT
F2BF010
32-LEAD TSOP
0.31" x 0.72"
TOP VIEW

-'15
-'1,
Ne

WE
Vee
Vpp
-'1e'
-'15
-'12

~

-'1

13
14

~
As

15
16

As

Ao

As

A.

290207-18

Figure 2. 28F010 Pin Configurations

3-56

intel~

28F010

Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F010, code updates are implemented locally
via an edge-connector, or remotely over a communcation link.

APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to typically perform over
, 100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F010 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and datatables are required, the 28F010's reprogrammability
and nonvolatility make it the obvious and ideal replacement for EPROM.

For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
.

Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as
revisions are made.

Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
Chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a,new "blank slate".

In diskless workstations and terminals, network traffic reduces to a 'minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extenqed re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and prfmary applications are flash-resident in
each terminal.

A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 4 depicts two 28F010s tied to the 80C186 system bus.
The 28F010's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.

For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F010 flash memory offers a solid
state alternative in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.

The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F01 Os. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of todaY's designs.

The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F010 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.

3-57

intel"

28F010

NI

I
nnnnnnnnnnnnnnnrt-~~~lflnLJ,UJ,nllrt-~nnl,U,Llnln~~u,.un

o

IL ~II

I(

,."
i')

0

,."
i')

0:>

0

0:>

...,
0

-

0

0

...,

I-'-

0

nnnnnnnnnnnnnnnr

0

I-'-

CIJ
N

0

I-'-

0

I-'-

-

...,
0:>
...,

-

CIJ
N

~

>

...,
0:>
...,

0

i')

I-'-

0
~

0

I-'-

0

CIJ
N

CIJ
N

~

"'-'

0

0

i')

0

"'-'

0

00

00

uuuuuuuuuuuuuuuu UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUU

Figure 3. TSOP Serpentine Layout

3-58

int:eL

28F010

Vee

Vee

80C186
SYSTEM BUS

Vee
A1-A 17

0°0- 0 °7

Vee

----------+I Ao-A 16
~--------~
28F010

MCSl AND

MC§2----------+I
8HE

CE

28F010

1---+1 CE

) - - - - - + 1 WE

AO

1---+1 WE

~----------~DE

1---+1

DE

290207-4

Figure 4. 28F010 in a 80C186 System
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the inteligent Identifier codes, or output
data for erase and program verification.

PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
iQ-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
28F010 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and inteligent
Identifier™ operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering, memory contents-inteligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.
'

Integrated Stop Timer
Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until re, ceiving the appropriate verify or reset command.

Write Protection
The command register is only active when Vpp is at
high voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VPPL, the con-

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data

3-59

intel"

28F010

Table 2 28F010 Bus Operations
Pins

Vpp(1)

Ao

Ag

CE

OE

WE

VpPL

Ao

As

VIL

VIL

VIH

Data Out

DQo-DQ7

Operation

Read·

READ-ONLY

Output Disable

VpPL

X

X

VIL

VIH

VIH

Tri-State

Standby

VpPL

X

X

VIH

X

X

Tri-State

VIL

VID(~)

VIL

VIL

VIH

Data =89H

VIL

VIL

VIH

Data = B4H

VIL

VIL

VIH

DataOut(4)

Intelligent Identifier (Mfr)(2)

READ!WRITE

VPPL

Intelligent Identifier (Device)(2)

VPPL

VIH

VID(3)

Read

VpPH

Ao

As

Output Disable

VpPH

X

X

VIL

VIH

VIH

Tri-State

Standby(5)

VpPH

X

X

VIH

X

X

Tri-State

Write

VpPH

Ao

As

VIL

VIH

VIL

Data In(6)

NOTES:

_

1. Refer to DC Characteristics. When Vpp = VpPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VIO is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

tents of the register default to the read command,
making the 28F01 Oa read-only memory. In this
mode, the memory contents cannot be altered.

erase verification. When Vpp is low (VPPL), the read
operation can only access the array data.

Or, the system designer may choose to "hardwire"

Output Disable

Vpp, making the high voltage supply constantly

With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.

available. In this case, all Command Register functions are inhibited .whenever Vce is below the write
lockout voltage VLKO. (See Power Up!Down Protection) The 28F010 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.

Standby

With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F010's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal.
If the 28F010 is deselected during erasure, programming, or program! erase verification, the
device draws active current until the operation is
terminated.
'

The two-step program! erase write sequence to the
Command Register provides additional software
write protections.
BUS OPERATIONS
Read

The 28F01 0 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is' the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Refer to AC read timing waveforms.

Intelligent Identifier Operation

The intelligent Identifier operation outputs the manufacturer Code (89H) and device code (B4H). Programming equipment automatically matches the device with its proper erase and programming algorithms.

When Vpp is high (VPPH), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program!

3-60

infel .

28F010

used to store the command, along with address and
data information needed to execute the command.

With Chip-Enable and Output-Enable at a logic low
level, raising AS to high voltage VID (see DC Characteristics) activates the operation. Data read from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectiVely.

The command register is written by bringing WriteEnable to a logic-low level (VII)' while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microproc- '
essor write timings are used.

The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F010 is erased and reprogrammed in the target system. Following a write of SOH to the command register, a read from address location OOOOH
outputs the manufacturer code (8SH). A read from
address 0001 H outputs the device code (B4H).

Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.

Write

COMMAND DEFINITIONS

Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F010 register
commands.

The command register itself does not occupy an addressable memory location. The register is a latch

Table 3_ Command Definitions
Command

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operation(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)

Read Memory

1

Write

X

OOH

Read Intelligent Identifier
Codes(4)

3

Write

X

SOH

Read

(4)

Set-up Erase/Erase(5)

2

Write

X

20H

Write

X

20H

Erase Verify(5)

2

Write

EA

AOH

Read

X

EVD

(4)

Set-up Program/Program(6)

2

Write

X

40H

Write

PA

PD

Program Verify(6)

2

Write

X

COH

Read

X

PVD

Reset(7)

2

Write

X

FFH

Write

X

FFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. 10 = Data read from location IA during device identification (Mfr = a9H, Device = B4H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.,
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read inteligent 10 command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase Algorithm.
6. Figure 5 illustrates the Quick-Pulse Programming AlgOrithm.
7. The second bus cycle must be followed by the desired command register write.

3-61

int:et

28F010

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.

Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.

The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard"wired to the 28F01 0, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.

The 28F010 applies an internally-generated margin
voltage to the addressed byte. ReadingFFH from
the addressed byte indicates that all bits in the byte
are erased.
The 'erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.

Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target sys.tem. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.

In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase algorithm; illustrates how commands and bus operations are combined to perform electrical erasure of the 28F010.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.

The 28F010 contains an Intelligent Identifier. operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
B4H. To terminate the operation, it is necessary to
write another valid command into the register.

Set-up Program/Program Commands
Set-up Erase/Erase .Commands

Set-up program is a command-only operation that
stages tlie device for byte programming. Writing 40H
into the command register performs the set-up
operation.

Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation· is performed
by writing 20H to the command register.

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e;, Erase-Verify Command).
.
This two-step sequence of set-up followed byexecution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
3-62

intel"

28F010

field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.

Program-Verify Command

The 28F01 0 i~fprogrammed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.

The 28F010 is specified for a minimum of 10,000
program/erase cycles. The device is programmed
and erased using Intel's Quick-Pulse Programming
and Quick-Erase algorithms. Intel's algorithmic ap~
proach uses a series of operations (pulses), along
with byte verification, to completely and reliably
erase and program the device.

The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.

For furt~er information, see Reliability Report RR-60.
QUICK-PULSE PROGRAMMING ALGORITHM

The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F010 Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.

The Quick-Pulse Programming algorithm uses programming 'operations of 10 J.l,s duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 5 illustrates the Quick-Pulse Programming algorithm.

Reset Command

QUICK-ERASE ALGORITHM

A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.

Intel's-Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F010 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.

For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately two seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 6 illustrates the Quick-Erase algorithm.

Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower than EEPROM. The lower electric

3-63

infel·

28F010

Bus
Command
Operation

Standby

Comments

Wait for Vpp Ramp to VpPH(1)

Initialize Pulse-Count

Set-up
Program

Data

Write

Program

Valid Address/Data
. Duration of Program
Operation (tWHWH1)

Standby
Write

Program(2) Data = COH; Stops Program
Operation(S)
Verify

St~ndby

twHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write
Standby

290207-5
NOTES:
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with th~ Read command.

= 40H

Write

Read

Data '= OOH, Resets the
R~ister for Read Operations
Wait for Vpp Ramp to Vppd1)

3. Refer to principles of operation.

4_ CAUTION: The algorithm MUST BE ·FOLLOWED
to ensure proper and reliable operation of the device.

Figure 5_ 28F010 Quick-Pulse Programming Algorithm

3-64

intel·

28F010

Bus
Command
Operation

Comments

Entire Memory Must = OOH
Before Erasure

Use Quick-Pulse
Programming Algorithm
(Figure 5)
Standby

WaitforVpp Ramp to VPPH(1)

Initialize Addresses and
Pulse-Count
Write

Set-up
Erase

Data = 20H

Write

Erase

Data = 20H

Standby

Duration of Erase Operation
(tWHWH2)
Erase(2)
Verify

Standby

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)
tWHGL

Read

Read Byteto Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Write

Read

Standby

290207-6
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Erase Verify is performed only atter chip-erasure. A
final read/compare may be performed (optional) atter
the register is written with the read command.

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VppL<1)

3. Refer to principles of operation.

4. CAUTION: The algorIthm MUST BE FOLLOWED
to ensure proper and reliable operation of the de.
vIce.

Figure 6. 28F010 Quick-Erase Algorithm
3-65

intel .

28F010
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

DESIGN CONSIDERATIONS
Two-Line Output Control

Vpp Trace on Printed Circuit Boards

Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
'

Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected 'devices maintain the low
power standby condition.

Power Up/Down Protection
The 28F010 is designed to offer protection against,
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing is not required. Internal circuitry in the 28.F010 ensures that the command register is reset to the, read mode on power
up.

Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (IcC> issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these'peaks.
Two-line control and proper decoupling capacitor
selection 'will suppress transient voltage peaks.
Each device should have a 0.1 J-tF ceramic capacitor
connected between Vee and Vss, and between VPP
and Vss.

A system designer must guard against active writes
, for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The Control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences.

28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption nor only during
device operation, but also for data retention during
system, idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F010.

Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 J-tF electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss.The bulk capacitor will overcome voltage slumps caused by printed-

Table 4. 28F010 Typical Update Power Dlsslpation(4)
Notes

Power Dissipation
(Watt-Seconds)

Array Program/Program Verify

1

0.171

Array Erase/Erase Verify

2

0.136

One Complete Cycle

3

0.478

Operation

NOTES:
1. Formula to calculate typical Program/Program Verify Power = [Vpp x
# Bytes x typical # Prog Pulses (tWHWH1 x IpP2 typical .+ tWHGL XlpP4
typical)) + [Vcc x # Bytes x typical # Prog Pulses (tWHWH1 x ICC2 typical
+ tWHGL X 1CC4 typical).
2. Formula to calculate typical Erase/Erase Verify Power = [Vpp (VPP3 typical
x tERAsEtypical + IpP5 typical x tWHGL X # Bytes)] + [VCC (ICC3 typical x
tERASE typical + ICC5 typical x, tWHGL x # Bytes)].
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited number of samples
from production lots.

3-66

intel .

28F010

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
. During Read .................. O°C to + 70°C(1)
During Erase/Program ......... O°C to + 70°C(1)
Operating Temperature
.
During Read ............... -40°C to + 8S·C(2)
During Erase/Program ...... -40·C to + 8S·C(2)
Temperature Under Bias ....... -1 O·C to + 80·C(1)
Temperature Under Bias ....... - So·C to + 9S·C(2)
Storage Temperature .......... -6S·C to + 12S·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(3)
Voltage on Pin Ae with
.
Respect to Ground ....... - 2.0V to + 13.SV(3, 4)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(3, 4)
Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(3)
Output Short Circuit Current ............. 100 mA(5)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

NOTES:
1. Operating Temperature is for commercial product defined by this specification.
2. Operating Temperature is for extended temperature products. as defined by this specification.
3. ¥inimum DC input voltage is -O.SV. During transitions, inputs may undershoot to - 2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + O.SV, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
4. Maximum DC voltage on Ae or Vpp may overshoot to + 14.0V for periods less than 20 ns.
S. Output shorted for no more than one second .. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Limits

Parameter

Unit

Min

Max

Comments

TA

Operating Temperature

0

70

·C

For Read-Only and
Read/Write Operations
for Commercial Products

TA

Operating Temperature

-40

+8S

·C

For Read-Only and
Read/Write Operations for
Extended Temperature Products

Vee

Vee Supply Voltage (10%)

4.S0

S.SO

V

Vee

Vee Supply Voltage (S%)

4.7S

S.2S

V

. For 28F01 0-90VOS Only

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
Symbol

Parameter

Limits

Notes
Min

Typlcal(4)

Unit

Test Conditions

Max

Ju

Input Leakage Current

1

±1.0

/LA

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±10

/LA

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

0.3

1.0

mA

Y.s;"e = Vee Max
CE = VIH

lee1

Vee Active Read Current

1

10

30

mA

Vee = Vee Max, CE = VIL
f = 6 MHz; lOUT = 0 mA

3-67

28F010

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
(Continued)
Parameter

Symbol

Limits

Notes

Min Typical(4)

Unit

Test Conditions

Max

lee2

Vee Programming Current

1,2

1.0

10

mA Programming in Progress

leC3

Vee Erase Current

1,2

5.0

15

mA Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

15

mA Vpp = VPPH, Program
Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

15

mA Vpp = VPPH, Erase
Verify in Progress

IpPS

Vpp Leakage Current

1

IpP1

VppRead Current
or Standby Current

1

\ ±10
90

p.A Vpp s Vee

200

p.A Vpp

±10.0

> Vee

Vpp s Vee

IpP2

Vpp Programming Current

1,2

8.0

30

mA Vpp = VPPH '
Programming in Progress

IpP3

Vpp Erase Current

1,2

6.0

30

mA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

mA Vpp = VPPH, Program
Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2,0

5.0

mA Vpp = VPPH, Erase
Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VID

A9 Intelligent Identifer Voltage

liD

A9 Intelligent Identifier Current

VPPL

Vpp during Read-Only
Operations .

0.00

6.5

V

VPPH

Vpp during Read/Write
Operations

11.40

12.60

V

VLKO

Vce Erase/Write Lock Voltage

0.8
Vee

+ 0.5

,0.45
2.4
13.00

11.50
90

1,2

V

200

2.5

V
V

IOL = 5.8mA
Vee = Vee Min

V

IOH = -2.5 mA
Vee = Vec Min

V
p.A A9 = VID
NOTE: Erase/Program are
Inhibited when Vpp = VPPL

,

V
I

DC CHARACTERISTICS-CMOS COMPATIBLE-Commercial '. Products
Symbol

Parameter

limits

Notes
Min

Typical(4)

Unit

Test Conditions

Max

III

Input Leakag~ Current

1

±1.0

p.A

Vee = Vec Max
VIN = VeeorVss

ILO

Output Leakage Current

1

±10

p.A

Vcc = Vee Max
VOUT ,;" Vee or Vss

Ices

Vce Standby Current

1

50

100

p.A

Y.s:t.e = Vce Max
CE = Vee ±0.2V

lec1

Vec Active Read Current

1

10

30

mA

Vee = Vec Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

3-68

28F010

DC CHARACTERISTIC5-CMOS COMPATIBLE-Commercial Products (Continued)
Symbol

Parameter

Umlts

Notes
Min

Typlcal(4)

Test Conditions

Unit
Max

lee2

Vee Programming Current

1,2

1.0

10

rnA Programming in Progress

lee3

Vee Erase Current

1,2

5.0

15

rnA Erasure in Progress

1CC4

Vee Program Verify Current

1,2

5.0

15

rnA Vpp = VPPH, Program
Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

15

rnA Vpp = VpPH, Erase
Verify in Progress

Ipps

Vpp Leakage Current

1

IpP1

Vpp Read Current, 10
Current or Standby Current

1

90

IpP2

Vpp Programming
Current

1,2

8.0

30

rnA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

6.0

30

rnA Vpp = VpPH
Erasure in Progress

I",P4

Vpp Program Verify
Current

1,2

2.0

5.0

rnA Vpp = VPPH, Program
Verify in Progress

IpP5

Vpp Erase Verify
Current

1,2

2.0

5.0

rnA Vpp = VpPH, Erase
Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

±10

/LA Vpp

200

/LA Vpp> Vee

±10

0.8
Vee

+ 0.5

0.45
0.85 Vee

Output High Voitage

Vpp

VID

Ag Intelligent Identifer
Voltage

110

Ag Intelligent Identifier
Current

VPPL

Vpp during Read-Only
Operations

VPPH
VLKO

13;00

Vee

V
V

V

11.50

S;

Vee

V

Vee - 0.4

VOH2

S;

IOL = 5.8 rnA
Vee = Vee Min
IOH

= -2.5 rnA, Vee = Vee Min

IOH

= -100 /LA, Vee = Vci:; Min

V

200

/LA Ag = VID

0.00

6.5

V

Vpp during Read/Write
Operations

11.40

12.60

V

Vee Erase/Write Lock
Voltage

2.5

1,2

90

V

3-69·

NOTE: Erase/Programs are
Inhibited when Vpp = VPPL

intel .

28F010

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Extended, Temperature
Products
Symbol

Parameter

Limits

Notes

Min Typlcal(4)

Unit

Test Conditions

'Max

III

Input Leakage Current

1

±1.0

/LA Vcc = Vee Max
VIN = Vcc or Vss

ILO

Output Leakage Current

1

±10

Ices

Vee Standby Current

1

0.3

1,0

ICCl

Vee Active Read Curr~nt

1

10

30

ICC2

Vee Programming Current

1,2

1.0

30

/LA Vee ='Vcc Max
VOUT = Vee or Vss .
mA YQ.e = Vee Max
CE ,= VIH
!
mA Vee = Vee Max, CE = \tIL
f = 6 MHz, lOUT = 0 mA
mA Programming in Progress

5.Q

30

mA Erasure in Progress

1CC4

Vee Erase Current
Vcc Program VerifyCurrent

1,2
1,2

5.0

30

mA Vpp = VPPH, Program
Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

30

rnA VPP = VPPH, Erase
Verify in Progress

Ipps

VPP Leakage Current
VPP Read Current
or Standby Current

1
1

±10

IpPf

90

200
±10.0

/LA VPP s: Vcc
/LA Vpp> Vee

IpP2

Vpp Programming Current

1,2

8.0

30

VPP Erase Current

1,2

6.0

30

mA VPP = VPPH
, Erasure in Progress

IpP4

VPP Program Verify Current

1,2

2.0

5.0

IpP5

VPP Erase Verify Current

1,2

2.0

5.0

mA VPP = VPPH, Program
Verify in Progress
mA VPP = VPPH, Erase
Verify in Progress

VIL

Input Low. Voltage

-0.5

VIH
VOL

Input High Voltage

2.0

lee3

,lpP3

0.8

"

Output High Voltage

VIO

A9 Intelligent Identifer Voltage

2.4
11.50

110

A9 Intelligent Identifier Current

VPPL

VPP during Read-Only
Operations

1,2
0.00

90

,6.5

VPPH

VPP during Read/Write
Operations

11.40

12.60

VLKO

Vcc Erase/Write Lock Voltage

2.5

V

Vee + 0.5 V
0.45
V IOL = 5.8mA
Vee = Vee Min
V IOH = -2.5mA
Vee = Vee Min
13.00
V

Output Low. Voltage

VOHl

VPP s: Vee
mA VPP = VPPH
Programming in Progress

.-

3-70

500

/LA A9 = VIO
V NOTE: Erase/Program are
Inhibited w.hen VPP = VPPL
V
V

intel . '

28F010

DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products
Symbol

Parameter

Notes
Min

Limits
Typleal(4)

Unit

Test Conditions

Max

III

Input Leakage
Current
.

1

±1.0

IJ-A Vee = Vee Max
VIN = Vee or Vss

IlO

Output Leakage
Current

1

±10

IJ-A Vcc = Vee Max
VOUT = Vee or Vss

lees

Vee Standby
Current

1

50

100

IJ-A Ys;..e = Vee Max
CE = Vee ±0.2V

lee1

Vee Active Read
Current

1

10

30

ICC2

Vee Prograinming
Current

1,2

1.0

10

mA Vee = Vee Max, CE = Vil
f = 10 MHz, lOUT = 0 rnA
mA Programming in Progress
I

lee3

Vee Erase Current

1,2

5.0

leC4

Vee Program Verify
Current

1.2

5.0

30
.. 30

ICC5

Vcc Erase Verify
Current

1,2

5.0

30

Ipps

Vpp Leakage Current

1

IpP1

Vpp Read Current,
10 Current or
Standby Current

1

IpP2

Vpp Programming
Currant

1,2

8.0

30

rnA Vpp = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

6.0

30

rnA Vpp = VpPH
Erasure in Progress

IpP4

VPP Program Verify
Current

1,2

2.0

5.0

rnA VPP = VPPH, Program
Verify in Progress

IpP5

VPP Erase Verify
Current

1,2

2.0

5.0

rnA Vpp = VpPH, Erase
Verify in Progress

Vil

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

0.7 Vee

V

VOL

Output Low Voltage

Vee + 0.5
0.45

VOH1

Output High Voltage

±10
90

200

rnA Erasure in Progress .
rnA Vpp = VPPH. Program
Verify in Progress
inA VPP = VpPH, Erase
Verify in Progress
IJ-A Vpp ~Vcc
IJ-A Vpp> Vcc

±10

Vpp

V

0.85 Vee
V

Vcc - 0.4

VOH2
-.

VIO

Aglntelligent Identifer
Voltage

110

As Intelligent Identifier
Current

11:50

13.00
90

1,2

3-71

500

~

Vcc

IOl = 5.8 rnA
Vee = Vee Min
IOH = -2.5 rnA,
Vee = Vee Min
IOH = -100 IJ-A,
Vee = Vee Min

V
IJ-A Ag

= VIO

intel .

28F010

DC CHARACTERISTICS-CMOS. COMPATIBLE-Extended Temperature
Products (Continued)
Symbol

Parameter

Limits

Notes
Min

Typlcal(4)

Unit

Test Conditions
NOTE: Erase/Programs are
Inhibited when Vpp = VPPL

Max

VPPL

Vpp during Read-Only
Operations

0.00

6.5

V

VPPH

Vpp during Read/Write
Operations

11.40

12.60

V

VLKO

Vcc Erase/Write Lock
Voltage

2.5

CAPACITANCE TA = 25c C, f
Symbol

V

= 1.0 MHz

Parameter

Limits

Notes
Min

CIN
COUT

Address/Control Capacitance
. Output Capacitance

Unit

Conditions

Max

3

8

pF

VIN = OV

3

12

pF

VOUT = OV

'.

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = S.OV, Vpp = 12.0V, T = 2S'C. These currents
are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
'3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of semples 'from production lots.

3-72

intel~

28F010

AC TESTING INPUT/OUTPUT WAVEFORM
For 28F010·120, 28F010·150

TX~:~> ptf~is

2.4--I-NP-U.....

i

0.45

<

AC TESTING INPUT/OUTPUT WAVEFORM
For 28F010·90V05

~.5 - TES~:POINTS - ~.5

2.0 OUTPUT
0.8

::: --IN-P-U"'T

290207-7

290207-8

AC test inputs are driven at VOH (2.4 VTn) for a Logic
"1" and VOL (0.45 VTTU for a Logic "0". Input timing
begins at VIH (2.0 VTTU and VIL (0.8 VTTU. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) <10 ns.

AC test inputs are driven at 3.0V for a Logic "1" and
O.OV for a Logic "0". Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
90%) <10 ns.

AC TESTING LOAD CIRCUIT
For 28F010·120, 28F010·150

AC TESTING LOAD CIRCUIT
For 28F010·90V05

.!:~

.!:~
~ .. lN914

I

DEVICE
UNDER
TEST

CL = 100 pF
CL includes Jig Capacitance

~

I

1

11---+--0 OUT

IG.

RL = 3.3 Kn

OUTPUT

DEVICE
UNDER
TEST

CL=30pF.
CL includes Jig Capacitance
RL = 3.3 Kn

290207-22

II' lN914

1
1--+-0 OUT

I

iG.
290207-23

AC TEST CONDITIONS
For 28F010·120, 28F010·150

AC TEST CONDITIONS
For 28F010·90V05

Input Rise and Fall Times (10% to 90%) ...... 10 ns

Input Rise and Fall Times (10% to 90%) •...•. 10 ns

Input Pulse Levels ................ 0.45V and 2.4V

Input Pulse Levels ............. , ... O.OV and 3.0V

Input Timing Reference Level ....... 0.BVand 2.0V

Input Timing Reference Level ................ 1.5V

Output Timing Reference Level .....• O.BV and 2.0V

Output Timing Reference Level .•......•..... 1.5V

Capacitive Load .......................... 100 pF

Capacitive Load ........................... 30 pF

Vcc Supply Tolerance ...................... 10%

Vcc Supply Tolerance ....................... 5%

3-73

intel .

28F010

AC CHARACTERISTICS-Read-Only Operations-Commercial and Extended
Temperature Products
28F010-90V05(3,4)

Versions
Symbol

Notes
Characteristic

Min

Max

28F010-120

28F010-150

Min

Min

Max

120

90

Unit

Max

150

tAVAV/tRC

Read Cycle Time

tELQv/tCE

Chip Enable
Access Time

90

120

150

ns

tAVQV/tACC

Address Access Time

90

120

150

ns

tGLQV/tOE

Output Enable
Access Time

40

50

55

ns

tELQX/tLZ

Chip Enable to
Output in Low Z

2,3

tEHQZ

Chip Disable to
Output in High Z

2

tGLQX/tOLZ

Output Enable to
Output in Low Z

2,3

tGHQZ/tDF

Output Disable to
Output in High Z

2

toH

Output Hold from
Address, CE,
orOEChange

1,2

tWHGL

Write Recovery Time
before Read

0

0
55

0

0
55

0
30

ns

ns

55
0

ns

35

30

ns

ns

0

0

0

ns

6

6

6

IJ-s

NOTES:
1. Whichever occurs first. .
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. See AC Test Conditions.

3-74

_.

l
~

VCC POWER-UP

X

X

X

DEVICE AND
ADDRESS SELECTION

STANDBY

X

OUTPUTS ENABLED

DATA VALID

STANDBY

ADDRESSES

ADDRESS STABLE

,I

tAVAy(tRC)

""c..

if£

Vee POWER-DOWN

X

CE (E)

CD

;"'I

1:;

-.~

CD

c.>

OE (G)
I\)

0

-.

CD

3
.!.J
01 1/1

I,

'11

....oo

I t WHGL -tl-------t

0

:::D

WE (Vi)

CD
AI

a.
0

"..

toH

CD
AI

g:

:J
1/1

DATA (DO)

~j
~

HIGHZ

~_ t AyQy

.

11

.

\\lli\\\4-~_ _ ..

VALID OUTPUT

(t
)
ACC

HIGH Z

~
290207-9

intel .

28F010

AC CHARACTERISTICS-Write/Erase/Program Operations(1)Commercial and Extended Temperature Products
Versions
Symbol
tAvAV/twc
tAVWL/tAS

Notes

28F010-90V05(2,4)
Min

Characteristic
Write Cycle Time
. Address Set-Up Time

Max

28F010-120(4)
Min

Max

28F010-150(4)
Min

Max

Unit

90

120

150

ns

0

0

0

ns

tWLAX/tAH

Address Hold Time

50

60

60

ns

tDVWH/tDS

Data Set-Up Time

50

50

50

ns

tWHDXltDH

Data Hold Time

10

10

10

ns

tWHGL

Write Recovery Time
before Read

6

6

6

p.s

tGHWL

Read Recovery Time
before Write

0

0

0

p.s

tELWL/tcs

Chip Enable Set-Up
Time before Write

20

20

20

ns

tWHEH/tcH

Chip Enable
Hold Time

0

0

0

ns

tWLWH/twp

Write Pulse Width2

50

60

60

ns

tWHWL/twPH

Write Pulse
Width High

20

20

20

ns

tWHWH1

Duration of
Programming
Operation

3

10

10

10

p.s

tWHWH2

Duration of
Erase Operation

3

9.5

9.5

9.5

ms

tVPEL

Vpp Set-Up Time
to Chip Enable Low

2

1.0

1.0

1.0

p.s

2

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.
4. See AC Test Conditions.

ERASE AND PROGRAMMING PERFORMANCECommercial and Extended Temperature Products
Parameter

Notes
Min

Limits
Typ

Unit
Max

Chip Erase Time

1,3,4

1.0

10

Chip Program Time

1,2,4

2

12.5

Erase/Program Cycles

1,5

10,000

6

1,000

100,000

Sec
Sec
Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25'C. 12.0V
Vpp, at 0 cycles.
2. Minimum byte programming time excluding system overhead is 16,..sec (10 ,..sec program + 6 ,..sec write recovery),
while maxim!Jm is 400 ,..sec/byte (16 ,..sec x 25 loops allowed by algorithm). Max chip p~ogramming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes OOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60 "ETOX II Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Extended Temperature Products.
3-76

intel .

28F010

99.9

1I

99

/

/-::
,

1/

J'

90

V/

/
,

70

,

60

50
40

,

30

"

/, /

/

80

"

,/,/

V-

95

""

/

,

,,

,
,,

,,

,,

11,"-

20

,I'

,

10

5

0.1
2

2.5

3

3.544.55

10

15

20

ChIp Program Tlmo (Soc)
- - - 12V; 10 ke; 23C
-------11.4V; 10 ke: 70C
- - - - 12V; 100 ke; 23C

290207-13

Figure 8. 28F010 Typical Programming Capability
75

/

V

Ii!w

I

55

I

"'"
~
C>
~

45

'"
is
35

1/
2

V

o

/

10

/

-'

V'
~ i-'

V

,
,,

",

20

30

'"'

50

60

70

)1'

J

"T

",

",' 1-" ."

J

V
III

90

100110 120

IlO

TEMP (C)
- - 1 k Cycles
---- 10k Cyel..
----- lOOk Cycles

Figure 9. 28F010 Typical Program Time at 12V
3-77

290207-14

intel .

28F010

.,

99.9

" ~.
,,/,-

.

99

l

V , .,
,

95

".'

90

V ,

80

/

70

' I

I , ,/

~ 60
0:
.. 50
::I! 40

N

I

/ 'i

::>

(,) 30
/

20

I

//i

10

/1/
if ,1,.,1

5

28F01Q-200

28F010-120/150

r-

'i

1

t7

O. 1
0.5

0.7

2345678910

CHIP ERASE
--'-

TI~E

20

30

(SEC)

12V:l0kc:23C
1'.4V; 10 kCjOC
12V;100 kc;23C

.---~.

290207-15

Figure 10. 28F010 Typical Erase Capability
3.2
3.0

i\

"

i\
'i\.

2.8
2.6

[;l

...
...'">=

~

2.4

~

In

,

2.2

~,

In

g 2.0
e,

:z:
(,)

1.8

~

".
~

1.6

". I"..

","

"-

I"- r-..... " ....
......
...... .. ....
r--.. ~ ...... ....

1.4
1.2
1.0

~

.........

o

10

20

30

.j()

50

60

70

.TE~P

80

""

"""

I-

90 100 110 120 130 140

(<>C)

- - 1 k Cycr"
_ ..... 10k Cycles
._-_. 100k Cycles

290207-16

Figure 11. 28F010 Typical Erase Time at 12V

3·78

SET -UP PROGRAt.I
COt.lMAND

Vee POWER-UP &
STANDBY

PROGRAt.I COt.lt.lAND
LATCH ADDRESS & DATA

PROGRAMMING

PROGRAM
VERIFY
COMt.lAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

.k

A

l
@

ADDRESSES

rS'1
c:

...

CE(E)

CD

....
~

~

::EI
DI

-...
-......

DE (G)

<
CD
0

3

t.)

1/1

o!.J 0
<0

WE (Vi)

"'II

0

...DI

ca

I

I

~

H

r4 1

I ,~,
I I

I

\

3
3

~·I
0

DATA (00)

"tJ
CD

-...~·I
DI

S.OV
Vee
ov
t VPEL
12.0V

I--

vPP
VpPL

290207-10

I\)
CI)

"11
0

~

0

_.

Vee POWER-UP at
STANDBY

SET-UP ERASE
COt.lt.fAND

ERASE COMt.lAND

ERASING

ERASE
VERlrY
COt.lt.fAND

ERASE
VERIFICATION

STANDBY/
Vee POWER-DOWN
A

ADDRESSES

0

A

l
8

28F010

ALTERNATIVE CE·CONTROLLED WRITES
Versions
Symbol

Characteristic

Notes

28F010·90V05(2)
Min

28F010·150

Min

Min

Max

Unit
ns

0

0

ns

80

80

ns

50

50

ns

10

10

ns

6

6

6

/Ls

0

0

0

/Ls

0

0

0

ns

0
70

ns

Write Cycle Time

tAVEL

Address Set-Up Time

0

tELAX

Address Hold Time

80

tovEH

Data Set-Up Time

50

tEHOX

Data Hold Time

10

tEHGL

Write Recovery Time
before Read

tGHEL

Read Recovery Time
before Write

tWLEL

Write Enable Set-Up
Time before
Chip Enable

tEHwH

Write Enable Hold Time

tELEH

Write Pulse Width

tEHEL

Write Pulse Width High

tVPEL

Vpp Set-Up Time to

120

Max

150

90

tAVAV

2

Max

28F010·120

ns

0

0

1

70

70

20

20

20

ns

2

1.0

1.0

1.0

/Ls

Chip Enable Low
NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to. the Chip-Enable waveform.
2. Guaranteed by design.

3-81

_.

;!!Z

~~
::JnI

i- .
~I

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COIolIolAND

PROGRAM COMIolAND
LATCH ADDRESS &: DATA

PROGRAMIolING

PROGRAM
VERIFY
COIolIolAND

PROGRAIoI
VERIFICATION

STANDBY/
Vec POWER-DOWN

l
8

ADDRESSES

0

0-

~

iii'

c.

...

~

~

WE (E)

(1)

~
>
;:; 5'
.,CD com
:::I
III

III

CD

0
III

>

0

~

CD

0.,
Co
3
I\J
1/1
U)

u;
Or (G)

"0
"0

'<

8"
(1)

N

iil
m
(1)

0

CI)

~
....
o

CE (W)

"0

....
0.,.
~
'tJ

a.,

(1)

::J

9'

IC

III

3
3

DATA (DQ)

s·

IC

0

'tI
CD

.,

III

' 0'
:::I
1/1

S.OV
Vee
OV

12.0V
Vpp
VpPl

290207-19

intel .

28F010

ORDERING INFORMATION
ITlp121 a lr101l1 0 1-11121 0 1

JL

TEMPERATURE
T = EXTENDED (-40 0 C to +a5 0 C)
BLANK = COMMERCIAL (OOC to +70 0 C)
.

L,--J
L ACCESS SPEEO (ns)

PACKAGE
P = 32-PIN PLASTIC DIP'
N = 32-LEAD PLCC
E STANDARD 32-LEAD TSOP
r
REVERSE 32-LEAD TSOP

=
=

120 ns
150 ns

290207-20

VALID COMBINATIONS:
P28F010-120
N28F010-120 TN28F010-120
'
P28F010-150
N28F010-150
N28F010-eOV05
E28F010-120
E28F010-150

F28F010-120
F28F010-150

TE28F010-120
TF28F010-120

ADDITIONAL INFORMATION
Order
Number
ER-20,

"ETOXTM ,II Flash Memory
Technology"

294005

ER-24,
RR-60,

"Intel Flash Memory"
"ETOXTM II Flash Memory
Reliability Data Summary"
"Using Flash Memory for
In-System
Reprogrammable
Nonvolatile Storage"
"Guide to Flash Memory
Reprogramming" .

294008
293002

AP-316,

AP-325

292046

292059

REVISION HISTORY
Number

Description

007

Removed 200 ns Speed Bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC Test Conditions
Added "dimple" to F TSOP Package
Correcte~ Serpentine Layout

008

Corrected AC Waveforms
Added Extended Temperature Options

3-83

28F020
2048K (256K x 8) CMOS FLASH MEMORY'
• Flash Electrical Chip-Erase
- 2 Second Typical Chip-Erase
• Quick-Pulse Programmlng™ Algorithm
-10 p.s Typical Byte-Program
- 4 Second Chip-Program
•

100,000 Erase/Program Cycles Typical

• 12.0V ± 5% Vpp
• High-Performance Read "
- 80 ns Maximum Access Time
• CMOS Low Power Consumption
-10 mA Typical Active Current
- 50 p.A Typical Standby Current
- 0 WaHs Data Retention Power
• Integrated Program/Erase Stop Timer

•

Command Register Architecture for
Microprocessor/Mlcrocontroller
Compatible Write Interface
, • Noise Immunity Features
- ±10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing
• ETOXTM Nonvolatile Flash Technology
- EPROM-Compatible Process Base
- High~Volume Manufacturing
Experience
• JEDEC-Standard Pinouts
- 32-Pin Plastic Dip
- 32-Lead PLCC
- 32-Lead TSOP
(See Packaging Spec., Order "231369)

• Extended Temperature Options
Intel's 28F020 CMOS Jlash memory offers the most cost-effective and reliable alternative for read/write
'random access nonvolatile ,memory. The 28F020' adds electrical chip-erasure and reprogramming to, familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F020'increases
memory flexibility, while contributing to time- and cost-savings. '
'
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of 8 bits., Int~I's 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
'
Extended erase and program cycling capability is designed into Intel's ETOXTM (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliablE:! cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F020
performs a minimum of 10,000 erase and program cycles well within the time limits of the Quick-Pulse Programming and Quick-Erase algorithms.
Intel's 28F020 employs advanced CMOS Circuitry for systems requiring high:performance access speeds, low
power consumpti0rl, and immunity to noise. Its 80 nanosecond access time provides no-WAlT-state performance for a wide range .of microprocess~rs and microc6ntrollers. Maximum standby current of 100 p.A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX process base, the 28F020 levers years' of EPROM experience to yield the highest levels of '
quality, reliability, and cost~effectiveness.
'

3-84

November 1892
Order Number: 280245-00&

intel .

28F020

U

-+-

s--+

I

r

---+

J INPUT/OUlPUT
I BUFFERS

.1 ERASE VOLTAGE

P

STATE
CONTROL

COMMAND
REGISTER
INTEGRATED
STOP TIMER

SWITCH

1I

~

TO ARRAY
SOURCE

-

".
I--

A

~
PGM VOLTAGE
SWITCH

I

I

CHIP ENABLE
OUlPUT ENABLE
LOGIC

STB

DATA
LATCH

~
Y-DECODER
. STB
A17

:r

"
•

3
VI
VI
W

a:
c
c

1----+

Y-GATING

1----+
X-DECODER

«

•
•
•
•
---+

2,097,152 BIT
CELL MATRIX 

000

0

290245-3
290245-2

1
2
3
4·
5
6
7
8
9
10
11
12
13
14
15
16

0

Of
A IO

CE
STANDARD PINOUT
E28F'020
32-LEAD TSOP
8mmx20mm
TOP VIEW

I?

D.
D.
D.'
Os

vss
O2

01
Do

Ao
AI
A2
As

290245-4

Or

~o

CE
0,

0.

Os

D.

0.

vss

0,
0,

~I

\7
REVERSE PINOUT
F2SF020
32-LEAD TSOP
8mmx20mm
TOP VIEW

""""

~3
~.
~7

WE
v""
vpp
~.
~.
~2

Do
Ao

A,

A3

A.

~
A2

At
As

290245-5

Figure 2. 28F020 Pin Configurations

3-86

infel"

28F020

Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F020, code updates are implemented locally
via an edge-connector, or remotely over a communcations link.

APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to typically perform over
100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F020 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and datatables are required, the 28F020's reprogrammability
and nonvolatility make it· the obvious and ideal replacement for EPROM.

For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.

Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as
revisions are made.

Flash memory's electrical chip erasure, byte programmability and complete. nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank sl.l1te".

In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds· that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.

A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 4 depicts two 28F020s tied to the 80C186 system bus.
The 28F020's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.

For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F020 flash memory offers a solid
state alternative in a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.

The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mmthickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F020s. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of tqday's deSigns.

The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F020 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.

3-87

intet

28F020

nnnnnnnnnnnnnnnl}-~~~ln¥J+lnllfL'lnlr ~nn~nln~I~~

o

IIL~11

1"'1

t-.>

0

1"'1

....
CO
N
....

00
...,

0

t-.>

0

0

0
N

t-.>

N
0

00
...,

nnnnnnnnnnnnnnnn

0
....
CO

0

t-.>

....N

0

llI.-r-.~<
...,
t-.>
00
...,

...,

0
N
0

...,

....

0

CO
N

t-.>

0

....
CO,

0

IJJ

t-.>

IJJ

0

0
N
0

t-.>,

00

00

N

00

UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUL UUUUUUUUUUUUUUUU

Figure 3. TSOP Serpentine Layout

3-88

intel .

28F020

Vee

Vee

80C186
SYSTEM BUS
A1-A1S

---------+i

Vee

Vee
Ao-A17

OQO~DQ7 +------~-_I

28F020

28F020
AODRESS DECODED _ _ _ _ _ _ _ _ _~
CHIP SELECT
BHE

>-----N

CE
WE,

AO

RD ________....... OE

1--"'"

WE

290245-6

Figure 4. 28F020 in a 80C186 System
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.

PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F020 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.

Integrated Stop Timer
Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program! erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.

In the absence of high voltage on the Vpp pin, the
28F020 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory con"
tents-Intelligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.

Write Protection
The command register is only active when Vpp is at
high volt~ge. Depending upon the application, ttie
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VpPL, the contents of the register default to the read command,
making the 28F020 a read-only memory. In this
mode, the memory contents cannot be altered.

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
3-89

intel.,

28F020

Table 2 28F020 Bus Operations
Pins

Vpp(1)

Ao

Ag

CE

OE

WE

VIL

VIL

VIH

Data Out

DOO-D07

Operation
VPPL

Ao

Ag

Output Disable

VPPL

X

Standby

VPi'L

X

X
·X

Read
READ-ONLY

READ/WRITE

VIL

VIH

VIH

Tri-State

VIH

X

X

Tri-State

VIL

VIL

VIH

VPPL

VIH

VIO(3)

VIL

VIL

VIH

= 89H
Data = SDH

Read

VPPH

Ao

Ag

VIL

VIL

VIH

DataOut(4)

Output Disable

VPPH

X

X

VIL

VIH

VIH

Tri-State

Standby(5)

VpPH

X

X

VIH

X

X

Tri-State

Write

VPPH

Ao

Ag

VIL

VIH

VIL

Data In(6)

Ihtelligent Identifier (Mfr)(2)

VPPL

VIL

VIO(3)

Intelligent Identifier (Device)(2)

Data

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written o(erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VIO is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
.
6. Refer to Table 3 for valid Data-In during a write operation.
.
7. X can be VIL or VIH.

Or, the system designer may choose to "hardwire"

When Vpp is high (VPPH), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
erase verification. When Vpp is low (VpPU, the read
operation can only access the array data.

Vpp, making the high voltage supply constantly

available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection.) The 28F020 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.

Output Disable

With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.

The two step program/erase write sequence to the
Command Register provides additional software
write protection.

Standby

BUS OPERATIONS

With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F020's circuitry
and substantially reduces device p()wer consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal.
If the 28F020 is deselected during erasure,. programming, or program/erase verification, the
device draws active current until the operation is
terminated.

Read

The.28F020 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.

3-90

int:eL

28F020

Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (8SH) and device code (SOH). Programming equipment automatically matches the device with its proper erase and programming algorithms.
With Chip-Enable and Output-Enable at a logic low
level, raising AS to high voltage VID (see DC Characteristics) activates the operation. Data read from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and 'device-codes can also be
read via the command register, for instances where
the 28F020 is erased and reprogrammed in the target system. Following a write of SOH· to the command register, a read from address location OOOOH
outputs the manufacturer code (8SH). A read from
address 0001 H outputs the device code (SOH).

The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VIU, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.
COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F020 register
commands.

Write
Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.

Table 3. Command Definitions
Command

Read Memory

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)

X

OOH

Write

X

90H

Read

(4)

(4)

Write

X

20H

Write

X

20H

1

Write

Read Intelligent Identifier Codes(4)

3

Set-up Erase/Erase(S)

2

Erase Verify(S)

2

Write

EA

AOH

Read

X

EVD

Set-up Program/Program(S)

2

Write

X

40H

Write

PA

PO

Program Verify(S)

2

Write

X

COH

Read

X

PVO

Reset(?)

2

Write

X

FFH

Write

X

FFH

NOTES:

1. Bus operations are defined in Table 2.
2. IA = . Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. 10 = Data read from location IA during device identification (Mfr = 89H, Device = BDH).
EVD = Data.read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write·Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4.. Following the Read Intelligent 10 command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase™ AlgOrithm.
6. Figure 5 illustrates the Quick-Pulse Programming™ Algorithm.
7. The second bus cycle must be followed by the desired command register write.

3-S1

infel .

28F020

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

Read Command
While Vpp is high, for erasure and programming,
'memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered. .

Erase-Verify Command
The erase command erases all bytes of the.array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on .the falling edge of the' Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.

The default contents of the register upon Vpp power"up is O·OH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is'
hard-wired to the 28F020, the device powers-up and
'remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.

The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
.the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to .
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.

Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising AS to a high voltage. However, multiplexing high voltage onto address lines is not a desired system':design practice.

In the case where the data read is notFFH, another
erase' operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set,up) to the command
register. Figure 6, the Quick-Erase™ algorithm, iIIus"
trates how commands and bus operations are combined to perform electrical erasure of the 28F020.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.

The 28F020 contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
SOH into the command register. Following the command write, a read cycle from address OOOOH retrieves fhe manufacturer code of 8SH. A read cycle
from address 0001 H returns the device code of
SOH. To terminate the operation, it is necessary to
write another valid command into the register.

Set-up Program/Program Commands
Set-up Erase/Erase Commands
Set-up Erase is a' command-only operation that.
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
.
Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the. Write-Enable pulse. Data is internally latched on the iising
edge of the Write-Enable pulse. The rising. edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specifiC timing
parameters.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and termh1ates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
. high voltage is applied to theVpp pin. In the absence
3-S2

infel .

28F020

field greatly reduces oxide stress and the probability
of· failure-increasing time to wearout by a factor of
100,000,000.

Program-Verify Command
The 28F020 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last progra~med. No new address information
is latched.
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F020 Quick-Pulse Programming™· algorithm,
illustrates how commands are combined with bus
operations to perform byte programming. Refer to
AC Programming Characteristics and Waveforms for
specific timing parameters.

Reset Command

The 28F020 is specified for a minimum of 10,000
. program/erase cycles. The device is programmed
and erased using Intel's Quick-Pulse Programming
and Quick-Erase algorithms. Intel's algorithmic approach uses a series of operations (pulses), along
with byte verification, to completely and reliably
erase and program the device.
For further information, see .Reliability Report RR-60.

QUiCK-PULSE PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 fl.sduration. Each operation is followed by a byte verification to determine
when the addressed byte has bee·n successfully programmed. The algOrithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or· second operation. The entire
.sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 5 illustrates the Quick-Pulse Programming algorithm.

. QUICK-ERASE ALGORITHM

A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
.

Intel's Quick-Erase algOrithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algOrithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memorY contents. The
28F020 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.

.EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing .cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.

. For devices being erased and reprogrammed, uniform .and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algOrithm, in approxi~
mately four seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through .the .array to
the last address, or until data other than. FFH is encountered. With each erase operation, an increasing
number of. bytes verify to the erased state. Erase
efficiency maybe improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in two seconds. Figure 6 illustrates the Quick-Erase algorithm.

Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MVlcm lower than EEPROM. The lower electric
3-93

infel· .

28F020

Bus
Command
Operation

Standby

Comments

Wait for VPP Ramp to VPPH(1)

Initialize Pulse-Count

= 40H

Write

Set-up
Program

Data

Write

Program

Valid Address/Data
Duration of Program
Operation (tWHWH1)

Standby
Write

Program(2) Data = COH; Stops Program
Operation(3)
Verify

Standby

twHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write
Standby

Read

Data = OOH, Resets the
Register for Read Operations
.Wait for VPP Ramp to VppL!1)

290245-7

3. Refer to principles of operation.

NOTES:
1. See DC Characteristics for the value of VPPH and
VPPL·
...
2. Program Verify Is oniyperformed after byte program- .
mingo A final read/compare may be performed (optional) after the register Is written with the Read command.

4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
.

Figure 5. 28F020 Qulck·Pulse Programming Algorlthin

3·94

int:et

28F020

Bus
Operation

Command

Comments

Entire Memory Must = OOH
Before Erasure

Use Quick-Pulse
Programming™ Algorithm
(Figure 5)
Standby

Wait forVpp Ramp to VPPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data = 20H

Write

Erase

Data = 20H

Standby

Write

Duration of Erase Operation
(tWHWH2)
Erase(2)
Verify

Standby
Read

. Read Byte to Verify Erasure

Standby

Write

Compare Output to FFH
Increment Pulse-Count

Read

Standby

290245-8
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Erase Verify is performed only after chip'erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)
tWHGL

Data =OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VPPL(1)

3. Refer to principles of operation.

4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 6. 28F020 Quick-Erase Algorithm

3-95

28F020

Power Up/Down Protection

DESIGN CONSIDERATIONS
Two-,-Ine Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
'
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip~enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, ,while deselected devices maintain the low
power standby condition.

Power Supply Decouplin9
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in'three supply current (Icc> issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

The 28F020 is designed to offer protection against
accidental erasiJre or programming during power
transitions. Upon power-up, the ,28F020 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing Is not required.
Internal circuitry in the 28F020 ensures that the
command register is reset to the read mode on power up.
A system designer must guard against active writes
for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The con·
trol register architecture provides an added level of
protection since alteration of memoiy contents only
occurs after successful completion of the two-step
command sequences.

28F020 Power Dissipation
When'designing portable systems, deSigners must
consider battery power consumption riot only during
, device operation, but also for data retention during
system idle time. Flash, nonvolatility increases the
usable battery life' of your system' because the
28F020 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F020.

Table 4. 28F020 Typical
Update Power Dlsslpatlon(4)

Two-line control and proper decoupling capaCitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 p.F ceramic capaCitor
connected between Vee and Vss, and between Vpp
and Vss.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 p.F electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

Operation'

Notes

Power Dissipation
(Watt-SSConds)

Array Program/Program Verify

1

0.34

Array Erase/Erase Verify

2

0.37

One cOmplete Cycle

3

1.05

NOTES:
,
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x typical # prog Pulse
(twHWH1 x IpP2 typical + twHGL X IpP4 typical)] + [Vcc
x # Bytes x typical # Prog Pulses (twHWH1 x ICC2 typical + tWHGL X 1CC4 typical)).
2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp (lpP3 typical x tERASE typical + IpP5 typical x
twHGL X # Bytes)] + [Vcc (Icca typical x tERASE typical
+,ICC5 typical X twHGL X # Bytes)].
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.,
,
4. ''Typlcals''are not guaranteed but based' on a limited
number of samples from 28F020·150 production lots. '

Vpp Trace on Printed Circuit Boards '
Programming flash-memories, while they' reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use Similar trace widths and
layout considerations given the Vee power bus. Adequate VPP supply traces anddecoupling will decrease Vpp voltage spikes and overshoots.

3-96

int:eL

28F020

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet The specifications are subject to change without notice.

Operating Temperature
During Read ........... ; ...... O°C to + 70°C(1)
During Erase/Program ......... O°C to + 70°C(1)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Operating Temperature
During Read ............... - 40°C to + 85°C(2)
During Erase/Program ...... - 40°C to + 85°C(2)
Temperature Under Bias ....... -10°C to

+ 80°C(1)

Temperature Under Bias ....... - 50°C to + 95°C(2)
Storage Temperature .......... -65°C to + 125°C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2. 3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .•.. - 2.0V to

+14.0V(2. 3)

Vee Supply Voltage with
Respect to Ground ... ; ...... - 2.0V to + 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product as defined by this specification.
3. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
.
4. Maximum DC voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Limits

Parameter

Unit

Min

Max

Comments

TA

Operating Temperature(1)

0

70

°C

For Read-Only and
Read/Write Operations
for Commercial products

TA

Operating Temperature(2)

-40

+85

°C

For Read-Only and
Read/Write Operations for
Extended Temperature Products

Vee

Vee Supply Voltage (10%)

4.50

5.50

V

Vee

Vee Supply Voltage (5%)

4.75

5.25

V

For 28F020-80V05 Only

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
Symbol

Parameter

Limits

Notes
Min

Typ(4)

Unit

Test Conditions

Max

III

Input Leakage Current

1

±1.0

p.A

Vee = Vee Max
VIN = VeeorVss

ILO

Output Leakage Current

1

±10

p.A

Vee = Vee Max
VOUT = Vee or VSS

3-97

intel~

28F020

. DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial
Products (Continued)
Symbol

Parameter

Limits

Notes
Min

Unit

Typ(4)

Max

Test Conditions

Ices

Vee Standby Current

1

0.3

1.0

rnA Vee = Vee Max
CE = VIH

leel

Vee Active Read Current

1

10

30

rnA Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA

lee2

Vee Programming Current

1,2

1.0

10

rnA Programming in Progress

lee3

Vee Erase Current

1,2

5.0

15

rnA Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

15

rnA Vpp = VPPH,
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

15

rnA Vpp = VPPH,
Erase Verify in Progress

Ipps

Vpp Leakage Current

1

IpPl

Vpp Read Current, 10 Current
or Standby Current

1

90

±10

/LA Vpp ~ Vee

200

/LA Vpp

30

rnA Vpp = VPPH
Programming in Progress

10

30

rnA Vpp

2.0

5.0

rnA Vpp = VPPH,
Program Verify in Progress

5.0

rnA Vpp ~ VPPH,
Erase Verify in Progress

IpP2

Vpp Programming Current

1,2

8

IpP3

Vpp Erase Current

1,2

IpP4

Vpp Program Verify Current

1,2

IpP5

Vpp Erase Verify Current

1,2

2.0

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOHl

Output High Voltage

VID

Ag Intelligent Identifer
Voltage

liD

Ag Intelligent Identifier
Current

VPPL

Vpp during Read-Only
Operations

0.00

6.5

V

VpPH

Vpp during Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock Voltage

0.8
Vee

+ 0.5

0.45
2.4
11.50
1,2

13.00
90

2.5

3-98

> Vee

Vpp ~ Vee

±10

200

=

VPPH

V
V
V

IOL == 5.8 rnA
Vee = Vee Min

V

IOH = -2.5mA
Vee = Vee Min

V
/LA Ag

V

=

VID

NOTE: Eyase/Program are
Inhibited when Vpp = VpPL

intel .

28F020

DC CHARACTERISTICS-CMOS COMPATIBLE-Commercial Products
Symbol

Parameter

Notes

Limits
Min

Typ(4)

Max

Unit

Test Conditions

III

Input Leakage Current

1

±1.0

}J-A Vee = Vee Max
VIN = Vee or VSS

ILO

Output Leakage Current

1

±10

}J-A Vee = Vee Max
VOUT = VeeorVss

Ices

Vee Standby Current

1

50

100

}J-A Vee ~ Vee Max
CE = Vee ±0.2V

lee1

Vee Active Read Current

1

10

30

mA Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

1,2

1.0

10

mA Programming in Progress

lee3

Vee Erase Current

1,2

5.0

15

mA Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

15

mA VPP = VPPH, Program
Verify in Progress

lee5

Vee Erase Verify
Current

1,2

5.0

15

mA VPP =VPPH,
. Erase Verify in Progress

Ipps

VPP Leakage Current

1

IpP1

VPP Read Current,
10 Current or
Standby Current

1

IpP2

VPP Programming
Current

1,2

8

30

mA VPP = VPPH,
Programming in Progress

IpP3

VPP Erase Current

1,2

10

30

mA VPP = VPPH,
Erasure in Progress

IpP4

VPP Program Verify
Current

1,2

2.0

5.0

mA VPP = VPPH,
Program Verify in Progress

IpP5

VPP Erase Verify
Current

1,2

2.0

5.0

mA VPP = VPPH,
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

90

±10

}J-A VPP::;; Vee

200

}J-A VPP

±10

0.8
Vee

+ 0.5

0.45

VOH1

VPP ::;;Vee

V
V
V

0.85 Vee

V

Output High Voltage
VOH2
Ag Intelligent Identifer
Voltage

lID

Aglntelligent Identifier
Current

VPPL

VPP during Read-Only
Operations

VpPH
VLKO

13.00

11.50
1,2
I

90

IOH = - 2.5 mA,
Vee = Vee Min

200

V
}J-A Ag = VIO

0.00

6.5

V

VPP during Read/Write
Operations

11.40

12.60

V

Vee Erase/Write Lock
Voltage

2.5

V

3-99

IOL = 5.8mA
Vee = Vee Min

IOH = -100 }J-A,
Vee"" Vee Min

Vee - 0.4

VIO

> Vee

NOTE: Erase/Programs are
Inhibited when Vpp = VPPL

intel~

28F020

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE......ExtendedTemperature
Products
Symbol

Parameter

Limits

Notes

Typ(4)

Min

Unit

Test Conditions

Max

III

Input Leakage Current

1

± 1.0

p,A Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±10

p,A Vee = Vee Max
VOUT == Vee or Vss

lees

Vee Standby Current

1

0.3

1.0

rnA Vee = Vee Max .
CE = VIH

lee1

Vee Active Read Current

1

10

30

rnA Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA

lee2

Vee Programming Current

1[2

1.0

30

rnA Programming in Progress

lee3

Vee Erase Current

1,2

5.0

30

rnA Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

30

rnA Vpp ==VPPH,
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

30

rnA VPP = VPPH,
Erase Verify in Progress

Ipps

VPP Leakage Current

IpP1

IpP2

1

VPP Read Current, 10 Current
or Standby Current

..

1

90

±10

p,A Vpp -;;,Vee

200

p,A Vpp> Vee

±10
1,2

. Vpp Programming Current

8

30

VPP -;;, VGe

,

!

rnA Vpp = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

10

30

rnA VPP

IpP4

VPP Program Verify Current

1,2

2.0

5.0

rnA Vpp = VPPH,
Program Verify in Progress

IpP5

VPP E~ase Verify Current

1,2

2.0

5.0

rnA VPP

=

=

VPPH

VPPH,

Era~e Verify in Progress
.

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VIL

0.8 .
Vee

+ 0.5

0.45
2.4

V
V,
IOL = 5.8 rnA
Vee = Vee Min

V

IOH = -2.5 rnA
Vet = Vee Min

.
11.50

13.00

VID

Ag Intelligent Identifer
Voltage

liD

Ag Intelligent Identifier
Current

VPPL

VPP during Read-Only
Operations

0.00

6;5

V

VPPH

VPP during Read/Write
Operations

11.40

·12.60

V

VLKO

Vee Erase/Write Lock Voltage

1,2

90

1'.2.5
3-100

500

•..

V

V
p,A Ag

V

=

VID

NOTE: Erase/Program are
Inhibited when VPP = VPPL

inteL

28F020

DC CHARACTERISTICS-CMOS COMP.ATIBLE-Extended Temperature
Products
Symbol

P~rameter

Notes

Limits
Min

Typ(4)

Max

Unit

Test Conditions

III

Input Leakag~ Current

1

±1.0

jJ-A Vee = Vee Max
VIN = Vee or VSS

ILO

Output Leakage Current

1

±10

jJ-A Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

50

leel

Vee Active Read Current

1

10

lee2

Vee Programming Current

1,2

lee3

Vee Erase Current

1,2

lee4

Vee Program Verify Current

1,2

lee5

Vee Erase Verify
Current

1,2

IpPS

VPP Leakage Current

1

IpPl

VPP Read Current,
ID Current or
Standby Current,

1

IpP2

VPP Programming
Current

1,2

8

30

rnA VPP = VpPH,
Programming in Progress

IpP3

VPP Erase Current

1,2

10

30

rnA VPP = VPPH,
Erasure in Progress

IpP4

VPP Program Verify
Current

1,2

2.0

5.0

rnA Vpp = VPPH,
Program Verify in Progress

IpP5

VPP Erase Verify
Current

1,2

2.0

5.0

mA VPP = VPPH,
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL-

Output Low Voltage

/ 100

jJ-A Vee = Vee Max
CE = Vee ±0.2V

50

mA Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

1.0

10

mA Programming in Progress

5.0

30

rnA Erasure in Progress

5.0

30

rnA VPP = VpPH, Program
Verify in Progress

5.0

30

mA VPP = VPPH,
Erase Verify in Progress

90

±10

jJ-A VPP

200

jJ-A Vpp> Vee

±10

0.8
Vee

+ 0.5

0.45

VOHl

VPP

Output High Voltage

V

V

IOL = 5.8mA
Vee = Vee Min
IOH = - 2.5 mA,
Vee = Vee Min
IOH = -100 jJ-A,
Vee = Vee Min

VIO

As Intelligent Identifer
Voltage

11.50

110

As Intelligent Identifier
Current

13.00

VPPL

VPP during Read-Only
Operations

0.00

6.5

V

VPPH_

VPP during Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock
Voltage

2.5

90

3-101

Vee

V

Vee - 0.4

1,2

S;

Vee

V

0.85 Vee

VOH2

S;

500

V
jJ-A As

V

=

\(10

NOTE: Erase/Programs are
Inhibited when VPP = VPPL

intel~

28F020

CAPACITANCE TA

= 25'C , f = 10 MHz

Symbol

Parameter

Limits

Notes
Min

Unit

Max

Conditions

CIN

Addressl Control Capacitance

3

8

pF

VIN

COUT

Output Capacitance

3

12

pF

VOUT

= OV
= OV

NOTES for DC Characteristics and Capacitance:

1. All currents are in RMS unless otherwise noted. Typical values at Vce =5.0V, Vpp = 12.0V, T = 25'C. These currents
are valid for all product versions (packages and speeds).·
2. Not 100% tested: Characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based. on a limited number of samples from production lots.

TESTING CHARACTERISTICS FOR
28F020-90, 28F020-150, 28F020-200

TESTING CHARACTERISTICS FOR
28F020-80V05

ACTESTING INPUT/OUTPUT WAVEFORM

AC TESTING INPUT/OUTPUT WAVEFORM

.~~:

_IN_PU_T--JX

:::>

...

2 .•

TE+ POINTS<

OUTPUT

::: -IN-P-UT-,.""5)(-TEST

~0INTS-Xi'5

290245-21

290245-22

AC test inputs are driven at VOH (2.4 VnLl for a Logic.
"1" and VOL (0.45 VnLl for a Logic "0". Input timing
begins at VIH (2.0 VnLland VIL (O.B VnLl. Output tim'ing ends at VIH and VIL. Input rise and fall times (10%
to 90%) ,,;10 ns.

AC test inputs are driven at 3.0V for a Logic "1" and
O.OV for a Logic "0". Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
90%) ,,;10 ns.

AC TESTING LOAD CIRCUIT

AC TESTING LOAD CIRCUIT
1.3V

1.3V

-r-

:~

~~

... ~ 1N914

DEVICE
UNDER
TEST

OUTPUT

~Rt.

DEVICE
UNDER
TEST

1---1---.:...0 OUT

1N914

Rt.
1 - - - - + - - - 0 OUT

..

290245-23

290245-24

CL = 100 pF
CL includes Jig Capacitance
RL = 3.3 k!1

CL = 30 pF
CL includes Jig Capacitance
RL = 3.3 k!1

AC TEST CONDITIONS

AC TEST CONDITIONS

Input Rise and Fall Times (10% to 90%) ...... 10 ns

Input Rise and Fall Times (10% to 90%) ...... 10 ns

Input Pulse Levels .................... 0.45 and 2.4

Input Pulse Levels .................... 0.0 and 3.0

Input Timing Reference Level .......... 0.8 and 2.0

Input Timing Reference Level ................. 1.5

Output Timing Reference Level ......... 0.8 and 2.0

Output Timing Reference Level ................ 1.5

Capacitive Load .......................... 100 pF

Capacitive Load ............................ 30 pF

VccSupplyTolerance .........•............ 10%

VCC Supply Tolerance ... ; ...... .- ............ 5%

3-102

_.

AC CHARACTERISTICS-Read-Only Operations-Commercial Products
28F020-80V05(4,5)

Versions

. Symbol

o
(0)

28F020-150(4)

28F020-200(4)

Min

Min

Unit
Notes

Min

Max

80

Min

Max

Max

' 150

90

Max

200

tAVAV

tRC

Read Cycle Time

tELQV

tCE

Chip Enable Access Time

80

90

150

200

ns

tAVQV

tACC

Address Access Time

80

90

150

200

ns

tGLQV

tOE

Output Enable Access Time

60

ns

tELQX

tLZ

Chip Enable to Output Low Z

tELQZ

tHZ

Chip Disable to Output High Z

tGLQX

tOLZ

Output Enable to Output Low Z

tGHQZ

tDF

Output Disable to Output in
HighZ
Output Hold from Addresses,
CE or OE Change

tOH

~

Parameter

28F020-90(4,5)

Write Recovery Time before
Read

tWHGL
--

-

---

--

NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3, Guaranteed by design.
4. See AC Test Conditions.
5. Preliminary Information.

40

35
2,3
2
2,3

55
0

2
1,2

0

0

55
0

0

ns

55

0

30

35
0

ns
ns

40
0

•

ns

0

55
0

30
0

55
0

l

ns
ns
1'1)
0)

6

6

6

6

.

fLs

."
C
1'1)

C

_.

l
@

Vcc POWER-UP

X

X

X

DEVICE AND
ADDRESS SELECTION

STANDBY

X

OUTPUTS ENABLED

DATA VALID

STANDBY

ADDRESS STABLE

ADDRESSES

t AVAV (t RC )
."

i5

.,c

Vcc POWER-DOWN

X

,

I

cr (E)

(D

:"I

»

0

::e
DI
<

!!.
0

DE (G)

.,

N

...

Q

....., 3
0
III
CoJ

./>.

.,

~

"TI

I.

1 t WHGL 1

'1

N
Q

0

:II

WE (Vi)

(D

DI

a.

r-tElOV

0

'0

t GlOX (tOlZ) ~

.,
(D

::!:
0

::J
III

tOH

tElOX (t lZ )

DI

DATA (DO)

HIGH Z

VALID OUTPUT

I

I---

s.OV

~J

VCC

tAVOV (tACe>

HIGH Z

I'~'~"1'"------~

~

290245-11

_.

AC CHARACTERISTICS-Write/Erase/Program Operations(1)-Commercial Products
Versions
, Symbol
tAvAv/twc

.~
o

01

. Characteristic

2SF02D-SOV05(4, 5)

2SF020-90(4, 5)

2SF020-150(4)

2SF020-200(4)

Min

Min

Notes
Min

Max

80

Write Cycle Time

Min

90

Max

150

Max

Unit

Max

200

Address Set-Up Time

0

0

0

0

ns

tWLAX/tAH

Address Hold Time

45

45

60

75

ns

tOVWH/tOS

Data Set-Up Time

45

45

50

50

ns

tWHOX/tOH

Data Hold Time

10

10

10

10

ns

tWHGL

Write Recovery Time before
Read

6

6

6

6

/A-s

tGHWL

Read Recovery Time before
Write

0

0

0

0

/A-s

tELWL/tcs

Chip Enable Set-UpTime before
Write

15

20

20

20

ns

tWHEH/tCH

Chip Enable Hold Time

0

0

0

0

ns

tWLWH/twp·

WHte ~Ise Width

45

45

60

60

ns

tWHWL/twPH

Write Pulse Width High .

20

20

20

20

ns

tWHWH1

Duration of Programming
Operation

3

10

10

/A-s

tWHWH2

Duration of Erase Operation

3

tVPEL

Vpp Set-Up Time to Chip Enable
Low
-- --- - - - -

2

,

•

ns

tAVWL/tAS

2

l

~

"T\
Q

10

~

9.5
1

10
9.5

9.5

9.5

ms

1

1.0

.1.0

/A-s

---------

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maXimum specification.
4. See AC Test Conditions.
5. Preliminary Information.

I\)

Q

28F020

ERASE AND PROGRAMMING PERFORMANCE-Commercial Products
Parameter

Notes

,

Limits
Min

Typ

Max

Unit

Chip Erase Time ,

1,3,4

2

30

Sec

Chip Program Time

1,2,4

4

25

Sec

Erase/Program Cycles

1,5

10,000

100,000

Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25°C, 12.0V
Vpp at 0 cycles.
'.
'
.
2. Minimum byte programming time excluding system overhead is 16 /Lsec (10 /Lsec program + 6 /Lsec write recovery),
while maximum is 400 /Lsec/byte (16 jLsec x 25 loops allowed by algorithm), Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program Significantly faster than the worst case
byte.
'
3. Excludes OOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
.
5. Refer to RR-60, 69 "ETOX Flash Memory Reliability Data Summaries" for typical cycling data and failure rate calculations.

AC CHARACTERISTICS-Read-Only Operations--Extended Temperature
Products
Versions
Symbol

Notes

Characteristic

tAvAV/tRc

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

28F020-90(4)

28F020-150

Min

Min

Max

90

Max

150
90

Unit
ns

I

150

ns

tAVQV/tACC

Address Access Time

90

150

ns

tGLQV/tOE'

Output Enable Access Time

55

55

ns

55

ns

35

ns

tELQX/tLz

Chip Enable to Output in Low Z

2,3

tEHQZ

Chip Disable to Output in High Z

2

tGLQX/tOLZ

Output Enable to Output in Low Z

2,3

tGHQZ/tOF

, Output Disable to Output in High Z

2
. 1,2

tOH

Outpu,t Hold from Address, CE, or OE
Change

tWHGL

Write Recovery Time before Read

3-106

0

0
55

0

ns

0
35

ns

0,

0

ns

6

6

/Ls

intel~

28F020

AC CHARACTERISTICS-Write/Erase Program Operation(1)-Extended
Temperature
Versions
- Symbol

Characteristic

tAVAv/twc

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAx/tAH

Address Hold Time

tDVWH/tDS

Data Set-Up Time

28F020-90(4)

28F020-150

Min

Min

Notes

Unit
Max

90

Max

150

ns

0

0

ns

60

60

ns

50

50

ns

tWHDx/tDH

Data Hold Time

10

10

ns

tWHGL

Write Recovery Time before Read

6

6

f.Ls

tGHWL

Read Recovery Time before Write

0

0

f.Ls

tELWL/tCS

Chip Enabl,e Set-Up Time before Write

20

20

ns

tWHEH/tCH

Ehip Enable Hold Time

0

0

ns

tWLWH/tWP

Write Pulse Width

60

60

ns

tWHWL/twPH

Write Pulse Width High

20

20

ns

tWHWH1

Duration of Programming Operation

3

10

10

f.Ls

tWHWH2

Duration of Erase Operation

3

9.5

9.5

ns

tVPEL

Vpp Set-Up Time to Chip Enable Low

2

10.0

10.0

f.Ls

2

NOTES:

1. Read timing characteristics during readlwrite operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the. programmingl erase operations, thereby eliminating the need for a maximum
specification.
4. Preliminary Information.
ERASE AND PROGRAMMING PERFORMANCE-Extended Temperature
Limits
Parameter

28F020-90(6)

Notes
Min

Chip Erase Time

1,3,4

Chip Program Time

1,2,4

Erase/Program Cycle

1,5

10,000

28F020-150

Typ

Max

2

30

4

25

100,000

Min

1,000

Unit

Typ

Max

2

30

4

25

Sec
Sec
Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25°C, 12.0V
Vpp.

2. Minimum byte programming time excluding system overhead is 16 P.s (10 p.s program + 6 p.s write recovery), while
maximum is 400 p.s/byte (16 P.s x 25 loops allowed by algorithm): Max chip programming time is specified lower than the.
worst case allowed by the programming algorithm, since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60, "ETOX Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Preliminary Information.
'

3-107

intet

28F020

99.9

/

99

/

95

90
C
u

m

80

(

P
0

b
a
b
I
I
I
t
Y

70

/

,
,,

,,

,

.

,(,''',,
,

./
, "
,, "
,,

, ./ , ,
,
// ,
,
" ,,
,,

..

/

40

/'

I

60
50

,/,,

,,

/

/

I

,

v
I

,V ,
,
I' , ,,
,,

30
20

I
I

10
I
I

5

I

0.1

4

5

6

7

8

9

10

20

30

ChIp Program TIme (Sec)
. . . - - - - 12V; 10kc; 23C
----~--1L4Y; 10kc: 70C
- - - - 12V; 100kc; 23C
290245-12

Figure 8. 28F020Typicai Programming Capability
(applies to 28F020-150, 28F020-200 only).

3-108

int:el..

28F020

15

.

/

14

/

13

.1'
12
C
h
I

P

V

11

/1

P
0

10

~/:

9
r

a
m

9

T

f..-"
~

I
m

e

V·· ....

/"

8

S
e
c
7

I
i

6

li

,,

,
,,

I

,,
,, ,
,

,,

.'
10

20

30

. .'.'

/

I

40

..' .'

50

.,

.'

60

70

I

I

-Y
80

/

1/

I

,.1
o

I

I

5

4

I

.... - ,._.-

/
90

I

/
V
100

110

120

130

Temp (C)
- - - 1 k Cycles
-------10k Cycles
- - - - lOOk Cycles
290245-13

Figure 9. 28F020 Typical Program Time at 12V
(applies to 28F020-150, 28F020-200 only)

3-109

infel .

28F020

99.9

/,/

"

99

I

90

V

C
u

m
p
0

b

80

60

a
b
i

50

I
I
t
Y

40

/

,,'1"1

/

I

I

I I
I

II,

,I

"

:'

I

/

20

I
I
I

,

I'

,'/
I

J

I

I

I

30

I
I

I

;'

'

,'/

II

70

,,','/'

/

/

/'

/' ./

I
95

,. ,I

,'/'

/,1
•

/.: !
i

10

/ :'!
~/I
I

5

,

II.
l.
,

U~
0.1

1

2

3

4

5

6

7 8 910

20

30

40

50

Chip Erase Time (Sec)
- - - 12V; 10ke;' 23C
- - -- - - - 12V; 100ke; 23C
- - - - - 11.4V; 10ke; OC
290245-14

NOTE:
Does not include Pre-Erase Program.

Figure 10_ 28F020 Typical Erase Capability
(applies to 28F020-150, 28F020-200 only)

3-110

int'et

28F020

5.2
5.0

,

i\

\.

4.8

1\,

4.6

\

4.4

C
h

\

4.2

'\

I
p

4.0

,,
,,

E

a
s
e
T
i

m

3.8
3.6

,

,,

3.4 "-

"'"

e
S
e
c

'\,

3.2

2.8
2.6

"'.

,,
.

.....

3.0

,

,,
"

,

. ..

'""""

. .. ..

.......

'"

...

r--........

.

'""'..

..

"-

"

'-...... ........ . . . . .
. ....
I'-.......
..
~
....... r--

2.2
2.0

,'"

. .
..

...........

2.4

""

o

10

20

30

40

50

60

70

80

90

100

110

120

130

Temp (C)
- - - 1k Cycles
••••••• 10k Cycles
_ . _ - lOOk Cycles

NOTE:
Does not include Pre·Erase Program.

Figure 11. 28F020 Typical Erase Time at 12.0V
(applies to 28F020·150, 28F020·200 only)

.3·111

290245-15

Vee POWER-UP
STANDBY

a:

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND·
LATCH ADDRESS a: DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

IN:

U

0

l
•

ADDRESSES

~I

...c
CD

CE (E)

...

!"
~

n

!ll
<
a-...

liE (G)

CD

3

Cf
.....
.....

!II

...a.1\)"
a

WE (Vi)

ICI

/

I

\ r \ r~ 1

'v'

I I

I

I

N

\

D;

3
3

il

DATA (DQ)

0

'a
CD

-~I
D;

S.OV
Vee.

ov:
12.0V

IvPEL
I-

·Vpp
VPPL

290245-16

C»

"TI
0
N
0

_.

Vee POWER-UP
STANDBY

a:

SET-UP ERASE
COIotIotAND

ERASE COIotIotAND

ERASING

ERASE
VERIFY
COIotIotAND

ERASE
VERIFICATION

STANDBYI
Vee POWER-DOWN

A

i

A

l
8

ADDRESSES

CE~)
I

."

aI:

....iiJ
Co)

;"1

DE (G)

()

~.

-•
~

...
~
.... 3
0

Co)

-......

U

WE (W)

0

'"
I
III

~I

...

.,i

-

..,-

II~_"J I

"-

DATA (DQ)

CD

:J

5.0V
Vee
OV
\vPEL

12.0V

J-.

VpPL

290245-17

N
C»
."
Q
N
Q

_.

ALTERNATIVE CE-CONTROLLED WRITES
Versions
Symbol

./>.

28F020-90(4,5)

Characteristic

Min

Max

Min

Max

28F020-150
Min

Max

28F020-200
Min

Unit

Max

tAVAV

Write Cycle Time

80

90

150

200

ns

tAvEL

Address Set-Up Time

0

0

0

0

ns

tELAX

Address Hold Time

60

70

80

95

ns

tOVEH

Data Set-Up Time

50

50

50

50

ns

tEHOX

Data Hold Time

10

10

10

10

ns

tEHGL

Write Recovery Time before Read

tGHEL

Read Recovery Time before Write

tWLEL

Write Enable Set-Up Time before Chip
Enable

2

6

6

6

6

J.ts

0

0

0

0

J.ts

0

0

0

0

ns

0

0

0

0

ns

tELEH

Write Pulse Width

1

60

60

70

80

ns

tEHEH1

Duration of Programming Operation

3

10

10

10

10

ns

tEHEH2

Duration of Erase Operation

3

9.5

9.5

9.5

9.5

ns

tEHEL

Write Pulse Width High

20

20

20

20

ns

tVPEL

.Vpp Set-Up Time to Chip Enable Low

2

1

1

1.0

1.0

J.ts

tVPEL

Vpp Set-Up Time to Chip Enable Low

6

10.0

10.0

10.0

10.0

J.ts

tEHWH

~

28F020-80V05(4,5)
Notes

\

Write Enable Hold Time

NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and. Write-Enable. In systems where Chip-Enable defines the write pulse
width (within a longer Write-Enable timing waveform) all set-up, hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum specification.
4. See AC Test conditions.
5. Preliminary Information.
6. Extended Temperature Products.

l
~

N

(XI

~
o

N

_.

j

>z

~o
~-oj

.,:::Jm..

Vee POWER-UP /I<
STANDBY

~


l!!en
0

0

=e
III

~

~

...

0

3
c.n UI

...
...0
...III

0

"'II

"0
"0

DE (G)

-<
8"


5.0V
Vee
OV

12.0V
Vpp
VpPL

290245-16

intel~

28F020

ORDERING INFORMATION

I. I E 12 18 1rio 121 a1-1 8 10 I aIvi alsi

.J~

TEMPERATURE RANGE
T'" EXTENDED (-40 0 C TO +SSOC)
BLANK'" COMMERCIAL (DOC TO +70 0 C)

~I
L

PACKAGE'
'.
P '" 32-PIN PLASTIC DIP
N. '" 32-LEAD PLCC .
E "'STANDARD 32-LEAD TSOP
f'" REVERSE 32-LEAD TSOP

. LPROLIFERATION CODE
ACCESS SPEED ( )
.
80
ns

90~:

1S0 ns'
200ns
290245-19

VALID COMBINATIONS:
P2BF020-150
P2BF020-200

N2BF020-150
N2BF020-200

TN2BF020-90

TN28F020-.150

E2BF020-150
E2BF020-200

F2BF020-150
F2BF020-200

TE2BF020-90
TF2BF020-90

TE28F020-150
TF28F020-150

ADDITIONAL INFORMATION
ER-20,

"ETOXTM Flash Memory
Technology"

ER-24,

"Intel Flash Memory"
"ETOXTM III Flash Memory
Technology"

ER-28,

REVISION HISTORY
. Order
Number
294005

Removed'Preliminary
Classification. Clarified AC and DC
test conditions. Added "dimple" to F
TSOP package. Corrected
serpentine layout.

-005

Added -80V05, -90 ns speed grades.
Added extended temperature
devices. Corrected AC Waveforms.

294008

"ETOXTM Flash Memory
Reliability, Data Summary"

293002

AP-316,

"Using Flash Memory for In. System Reprogrammable
Nonvolatile Storage"

292046

"Guide to Flash Memory
Reprogramming"

Description

'-004

294012

RR-60,

AP-325

Number

292059

3-116

infel®

28F001 BX-T 128F001 BX-B
1M (128K x 8) CMOS FLASH MEMORY

•

High Integration Blocked Architecture
-OneSKB Boot Block w/Lock Out
- Two 4KB Parameter Blocks
- One 112KB Main Block

•

10,000 Erase/Program Cycles Minimum
Per Block

••
•
•
•

Simplified Program and Erase
- Automated Algorithms via On-Chip
Write State Machine (WSM)
SRAM-Compatible Write Interface
Deep-Powerdown Mode
- 0.05 ,..,A lee Typical
- O.S ,..,A Ipp Typical
12.0V ±5% Vpp

•
•
•
•

High-Performance Read
- 120 ns Maximum Access Time
- 5.0V ± 10% Vee

•

Extended Temperature Options

Hardware Data Protection Feature
-- Erase/Write Lockout during Power
Transitions
Advanced Packaging, JEDEC.Pinouts
...... 32-Pin PDIP
-- 32-Lead PLCC, TSOP .
ETOXTM II Nonvolatile Flash
Technology.
...... EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience

Intel's 28F001 BX-B and 28F001 BX-T combine the cost-effectiveness of Intel standard Flash Memory with
features that simplify write and allow block erase. These devices aid the system designer by combining the
functions of several components into one, making boot block flash an innovative alternative, to EPROM and
EEPROM or battery-backed static RAM. Many new and existing designs can .takeadvantage of the
28F001 BX's integration of blocked architecture, automated electrical reprogramming, and standard processor
interface.
The 28F001 BX-B and 28F001 BX-T are 1,048,576-bit nonvolatile memories organized as 131,072 bytes of
8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment
conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming. The 28F001 BX-T's block locations provide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel's
MCS-186 family, 80286, i386™, i486™, i860™ and 80960CA. With exactly the same memory segmentation,
the 28F001 BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory,
such as Intel's MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless
otherwise noted, the term 28F001 BX can refer to either device throughout the remainder of this document.
The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations bf the 28F001 BX. Intel's 28F001 BX employs advanced CMOS circuitry for systems requiring highperformance access speeds, .Iow power consumption, and immunity. to noise. Its 120 ns access time provides
no-WAlT-state performance for a wide. range of microprocessors and microcontrollers. A deep-powerdown
mode lowers power consumption to 0.25 fJ-W typical through Vee, crucial in laptop computer, handheld instru-.
mentation and other low-power applications. The PWD power control input also provides absolute data protection during system powerup or power loss.
Manufactured on Intel's1-micron ETOX II process base, the 28F001 BX builds on years of EPROM experience
to yield the highest levels of quality, reliability, and cost-effectiveness.

3-117

September .1992
Order Number: 290406-004

28F001 BX-T 128FOO 1BX-B

r-~-,~~JL----cr

I+-+.....----WE

...........- - - ' - - - O E

L.,~-rJ------PWD

Vpp

_GHD

290406-1

Figure 1. 28F001~~ Block Diagram
Table 1.Pin Description
Symbol
Ao-A16
DOo-DO?

\

Type

Name and Function

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.

INPUT/
()UTPUT

DATA INPUTS/OUTPUTS: Inputs data and commands during memory write
cycles; outputs data during memory, Status Register and Identifier read cycles. The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.

CE

INPUT

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE is active low; CE high deselects the memory device and
redlices power consumption to standby levels.

PWD

INpUT

POWER DOWN: Puts the device in deep powerdown mode. PWD is active low;
PWD ~ates normal operation. PWD = VHH allows programming of the boot
block. PWD also locks out erase or ~rite operations when active low, providing data
protection during power transitions.

OE

INPUT

OUTPUT ENABLE: Gates.the device's outputs through the data buffers during a
read cycle. OEis active low. OE = VHH (pulsed) allows programming of the boot
block.

WE

INPUT

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
is active low. Addresses and data are latched on the rising edge of the WE pulse.

Vpp

ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or
programming bytes of each block. Note: With Vpp <: VPPL max, memory contents
cannot be altered.

Vee

DEVICE POWER SUPPLY: (5V

GND

GROUND
3-118

±10%)

infel"

28F001J;lX-T/28F001BX-B

28F010
Vpp

A1S
A1S
A12
A7
As
As
A4
A3
A2
Al
Aa
DOa
DOl
D02
GND

28F010
Vee

V"
A,.

WE

A'5

PWD

A'2
A7

A,.

A.
A5

As
Ag

A.
A,

ill:

A2
A,

cr

A13

A"
AlO
D0 7

AO
DOo
DO,
D02
GND

DOs
DOs
DO.
DO,

VCC

WE
NC
A14"
A13
As
A9
All
OE
Ala
CE
D07
DOs
DOs
D04
D03

290406-2

Figure 2. DIP Pin Configuration

28F010

28F010

All

ill'

Ag
AS

~
CE
D07
DO.
D05
DO.
D03

A,.
NC
A'3

~

Vee

GND

A,.

V"

D02
DO,
DOo

A'5
A'2
A7

Ao

Ae

A,
A2

A5
~

A3

290406-3

Figure 3. TSOP Lead Configuration

3-119

intet

28F001BX-T/28F001BX-B

28F010
28F001BX(128Kx8)

~4-

N28F001BX
32 LEAD PLCC
O.450"xO.550"

TOP VIEW

CE DO-,-

290406-4

Figure 4. PLCC Lead Configuration

APPLICATIONS
The 28F001 BX flash 'boot block' memory augments
the non-volatility, in-system electrical erasure and
reprogrammability of Intel's standard flash memory
by offering four separately erasable blocks and integrating a state machine to control erase and program functions. The specialized blocking architecture and automated programming of the 28F001 BX
provide a full-function, non-volatile flash memory
ideal for a wide range of applications, including PC
boot/BIOS memory, minimum-chip embedded program memory and parametric data storage. The
28F001 BX combines the safety of a hardware-protected 8-KByte boot block with the flexibility of three
separately reprogrammable blocks (two 4-KByte parameter blocks and one 112-KByte code block) into
one versatile, cost-effective flash memory. Additionally, reprogramming one block does not affect code
stored in another block, ensuring data integrity.

The flexibility of flash memory reduces costs
throughout the life cycle of a design. During the early
stages of a system's life, flash memory reduces prototype development and testing time, allowing the
system designer to modify in-system software electrically versus manual removal of components. During production, flash memory provides flexible firmware for just-in-time configuration, reducing system
inventory and eliminating unnecessary handling and
less reliable socketed connections. l:.ate in the life
cycle,- when software updates or code "bugs" are
often· unpredictable and costly, flash memory reduces update costs by allowing the manufacturers to
send floppy updates versus a technician. Alternatively, remote updates over a communication link are
possible at speeds up to 9600 baud due to flash
memory's fast programming time.

3-120

28F001BX-T/28F001BX-B

Reprogrammable environments, such as the personal computer, are ideal applications for the
28F001 BX. The internal state machine provides
SRAM-Iike timings for program and erasure, using
the Command and Status Registers. The blocking
scheme allows BIOS update in the main and parameter blocks, while still providing recovery code in the
boot block in the unlikely event a power failure occurs during an update, or where BIOS code is corrupted. Parameter blocks also provide convenient
configuration storage, backing up SRAM and battery
configurations. EISA systems, for example, can
store hardware configurations in a flash parameter
block, reducing system SRAM.
Laptop BlOSs are becoming increasingly complex
with the addition of power management software
and extended system setup l1creens. BIOS code
complexity increases the potential for code updates
after the sale, but the compactness of laptop designs makes hardware updates very costly. Boot
block flash memory provides an inexpensive update
solution for laptops, while reducing laptop obsolescence. For portable PCs and hand-held equipment,
the deep powerdown mode dramatically lowers sys-

Vpp

80Cl88
SYSTEM BUS
ALE
AI6

Vpp

Vpp

A7 • AI6

...J

-

PORT PIN
ALE

Ao -A7

28FOOIBX-T

ADO - AD-,
SYSTEM RESET

DOc - D07

WE

Ro

OE

UCS

cr

Aa - AI5

28FOO1BX-B

PWD

WR

vee

80CSl
SYSTEM BUS

Vee

:I:

>-

The 28F001 BX gives the embedded system designer several desired features. The internal state machine reduces the size of external code dedicated to
the erase and program algorithms, as well as freeing
the microcontroller or microprocessor to respond to
other system requests during program and erasure.
The four blocks allow logical segmentation of the
entire embedded software: the 8-KByte block for the
boot code, the 112-KByte block for the main program code and the two 4-KByte blocks for updatable
parametric data storage, diagnostic messages and
data, or extensions of either the boot code or program code. The boot block is hardware protected
against unauthorized write or erase of its vital code
in the field. Further, the powerdown mode also locks
out erase or. write operations, providing absolute
data protection during system powerup or power
loss. This hardware protection provides obvious advantages for safety related applications such as
transportation, military, and medical.. The 28F001 BX
is well suited for minimum-chip embedded applications ranging from communications to automotive.

Vee

,!
- !
Ao '" ~
0

tem power requirements during periods of slow operation or sleep modes.

000 -D~

ADo - AD-,

PWD

SYSTEM RESET

WE

WR
RD

Aa - AI5

OE

PSEN

As - A,s

As - A,s

Vee

cr

~
Vee

MCS

A - A
2Kx8
10 SRAM
a
CS

WR

WE

Ro

OE

ADo - AD-,

Ao -A7 ~
W R - - - - -.....

Do - D7

PSEN

290406-5

ADo - AD-,

Figure 5. 28F001BX-T in a 80C188 System

------+l0E .
Do -_
D-, _....
L-.

290406-6

Figure 6. 28F001BX-B in a 80C51 System

3-121

in1'el ~

28F001 BX-T128F001 BX-B

PRINCIPLES OF OPERATION

Data Protection

The 28F001 BX introduces on-chip write automation
to, manage write and erase functions. The write state
machine allows for: 100% TTL-level control inputs;
fixed power supplies during erasure and programming; minimal processor overhead with RAM-like
write timings, and maximum EPROM compatiblity.

Depending on the application, the system designer
may choose to make the Vpp power supply switchable (available only when ,memory updates are required) or hardwired to VPPH. When Vpp = VPPL,
memory contents cannot be altered. The 28F001 BX
Command Register architecture provides protection
from unwanted program or erase operations even
when high voltage is applied to Vpp. Additionally,.all
functions are disabled whenever Vc~below the
write lockout voltage VLKO, or when PWD is at VIL.
The 28F001 BX accommodates either design practice and encourages optimization of the processormemory interface.

After initial device powerup, or after return from
deep' powerdown mode (see Bus Operations), the
28F001 BX functions as a read-only memory. Manipulation of external memory-control pins yield standard EPROM read, standby, output disable or
inteiigent Identifier operations. Both Status Register
and inteligent Identifiers can be accessed through
the Command Register when Vpp = VPPL.
This same subset of operations is also available
when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp enables successful erasure
and programming of the device. All functions associated with altering memory .contents-program,
erase, status, and inteligent Identifier-are accessed
via the Command Register and verified through the
Status Register.

The two-step program/erase write sequence to the
Command Register provides additional software,
write protection.

Commands are written using standard microprocessor write timings. Register contents serve as input to
the WSM, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase
operations. With the appropriate command written to
the register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output program and erase status for verification.
Interface software to initiate and poll progress of internal program and erase can be stored in any of the
28F001 BX blocks. This code is copied to, and executed from, system RAM during actual flash memory
update. After successful completion of program
and/or erase, code execution out of the 28F001 BX
is again possible via the Read Array command.
Erase, suspend/resume capability allows system
software to suspend block erase and read datalexecute code from any other block.,
.

lFFFF
8-KByte BOOT BLOCK

1 EOOO
lDFFF

10000
lCFFF
lCOOO
lBFFF

4-KByte PARAMETER BLOCK
4-KByte PARAMETER BLOCK

112-KByte MAIN BLOCK

00000

Figure 7. 28F001BX-T Memory Map
lFFFF

112-KByte MAIN BLOCK

Command Register and Write
Automation
An on-chip state machine controls block erase and
byte program, freeing the system processor for other
tasks. After receiving the erase setup and erase
confirm commands, the state machine controls
block pre-conditioning and erase,returning progress
via the Status Register. Programming is similarly
controlled, after destination address and expected
data are supplied. The program algorithm of past Intel Flash memories is now regulated by the state
machine, including program pulse repetition where
required and internal verification and margining of
data.
3-122

04000
03FFF
03000
02FFF
02000
01FFF

4-KByte PARAMETER BLOCK
4-KByte PARAMETER BLOCK

8-KByte BOOT BLOCK

00000

Figure 8. 28F001BX-B Memory Map

intel~

28F001 8X-T /28F001 8X-8

(000-007) direction control, and when active
drives data from the selected memory onto the 1/0
bus. PWD and WE must also be at VIH. Figure 12
illustrates read bus cycle waveforms.
'

BUS OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.

Output Disable
With OE at a logic-high level (VIH), the device outputs are disabled. Output pins (000-007) are
placed in a high-impedance state.

Read
The 28F001 BX has three read modes. The memory
can be read from any of its blocks, and inform13.tion
can be read from the intelligent identifier or the
Status Register. Vpp can be at either VPPL or VPPH.

Standby
CE at a logic-high level (VIH) places .the 28F001 BX
in standby mode. Standby operation disables much
of the 28F001 BX's circuitry and substantially reduces device power consumption. The. outputs (000007) are placed in a high-impedance state independent of the status of OE. If the 28F001 BX is deselected during erase or program, the device will continue functioning and consuming normal active power until the operation is completed.

The first task is to write the appropriate read mode
command to the Command Register (array, intelligent identifier, or Status Register). The 28F001 BX
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The 28FOOtBX has four control pins, two of which
must be logically active to obtain data at the outputs.
Chip Enable (CE) is the device selection control, and
when active enables the. selected memorY device.
Output Enable (OE) is the data input/output

Table 2. 28F001BX Bus Operations
Mode
Read

Notes

PWD

CE

OE

WE

Ag

Ao

Vpp

1,2,3

VIH

VIL

VIL

VIH

X

X

X

DOUT

X

X

HighZ

DQO-7

Output Disable

VIH

VIL

VIH

VIH

X

Standby

VIH

VIH

X

X

X

X

X

HighZ

VIL

X

X

X

X

X

X

HighZ

VIH

VIL

VIL

VIH

VIL

X

89H
94H,95H
DIN

Deep Power Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write

4

. VID

4,5

VIH

VIL

VIL

VIH

VID

VIH

X

6,7,8

VIH

VIL

VIH

VIL

X

X

X

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL, memory contents can be read but not programmed or erased.
2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for Vpp,
3. See DC Characteristics for VPPL, VpPH, VHH and VID voltages.
4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3, A1-AS,
A10- A16 = VIL·
5. Device ID = 94H for the 28F001 BX-T and 95H for the 28F001 BX-B.
6. Command writes involving block erase or byte program are successfully. executed only when Vpp = VpPH.
7. Refer to Table 3 for valid DIN during a write operation.
.
8. Program or erase the boot block by holding PWD at VHH or toggling OE to VHH' See AC Waveforms for Program/Erase
Operations.

3-123

infel~

28F001BX-T/28F001BX-B

Deep Power-Down

P.w

The 28F001 BX offers a 0.25
Vee powerdown
feature, entered when PWD is at VIL. During read
modes, PWD-Iow deselects ~he memory, places output drivers in a high-impedance state and turns off
all internal circuits: The 28F00113X requires time
tpHQV (see AC Characteristics-Read Only Operations) after return from powerdown until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The Command
Register is reset to Read Array, and,the Status Register is cleared to value BOH, upon return to normal
operation.
During erase or program modes, PWD low will abort
either operation. Memory contents of the block being altered are no longer valid as the data will be
partially programmed or erased. Time tPHWL after
PWD goes to logic-high (VIH) is required before another command can be written.
.

Intelligent Identifier Operation
The ihtelligent identifier operation outputs the manufacturer code, 89H; and the device code, 94H for the
28F001 BX-T and 95H for the 28F001 BX-B. Programming equipment or the system CPU can then
automatically match the device with its proper erase
and programming algorithms.

used to store the command and address and data
information needed to execute the command. Erase
Setup and Erase Confirm commands require both
appropriate command data and an address within
the block to be erased. The Program Setup Command requires both appropriate command data and
the address ofthe location to be programmed, while
the Program command consists ~f the data to be
written and the address of the location to be progmmmed.
The Command Register is written by bringing WE to
a 10gic~low level (VIL) while CE is low. Addresses
and data are ,latched on the rising edge of WE. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the AC Waveform for Write Operations, Figure 13, for specific timing parameters.

COMMAND DE,FINITIONS
When VPPL is applied to, the Vpp pin, read operations from the Status Register, intelligent identifiers,
or array blocks are enabled. Placing VPPH on Vpp
enables successful program and erase operations
as well.
Device operations are selected by writing specific
commands into the Command Register. Table 3 defines these 28F001 BX commands.

PROGRAMMING EQUIPMENT

Read Array Command

CE andOE at a logic low level (VILl, with Agat high
voltage VID' (see DC Characteristics) activates this
operation. Data, read. from locations OOOOOH and
00001 H represent the manufacturer's code and the
device code respectively. '

Upon initial device powerup and after exit from deep
powerdown mode, the 28F001 BX defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command Register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the Command Register contents are altered. Once the internal write state machine has started an erase or program operation, the
device will not recognize the Read Array command,
until the WSM has completed its operation. The
Read Array command is functional when Vpp' =
VPPL or VPPH·

IN-SYSTEM PROGRAMMING

The manufacturer- and device-codes can also be
read via the Command Register. Following a write of
90H to the Command Register, a read from address
location OOOOOH outputs the manufacturer code
(89H). A read from address 00001 H outputs the device code (94H for the 28F001 BX-T and 95H for the
28F001 BX-B). It is not necessary to have high voltage applied to Vpp to read the intelligent identifiers
from the Command Register.

Write
Writes to the Command Register allow read of device data and intelligent identifiers. They also control,
inspection and clearing of the Status Register. Additionally, when Vpp' = VPPH, the Command Register
controls device erasure and programming. The contents of the register serve as input to the internal
state machine.

Intelligent Identifier Command for'
In-System Programming
The 28F001 BX contains an intelligent identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated bY writing
90H into the Command Register. Following the command write, a read cycle from address OOOOOH retrieves the manufacturer code of 89H. A read cycle
from address 00001 H returns the device code of
94H (28F001 BX-T) or 95H (28F001 BX-B). To terminate ,the operation, it is necessary to write another
valid command into the register. Like the Read Array
command, the intelligent identifier command is functional when Vpp = VPPL or VPPH.

The Command Register itself doeS not occupy an
addressable memory location. The register is a latch
3-124

intel .

28F001 BX-T/28F001 BX-B

Table 3. 28F001BX Command Definitions
Bus
Second Bus Cycle
First Bus Cycle
Cycles Notes
Req'd
Operation Address Data Operation Address Data

Command
Read Array/Reset

1

1

Write

X

FFH

Intelligent Identifier

3

2,3,4

Write

X

90H

Read

IA

110

3

Write

X

70H

Read

X

SRD

Write

X

SOH

Write

BA

20H

Write

BA

DOH

Write

X

BOH

Write

X

DOH

Write

PA

40H

Write

PA

PO

,

Read Status Register

2

Clear Status Register

1

Erase Setup/Erase Confirm

2

Erase Suspend/Erase Resume

2

Program Setup/Program

2

2

2,3

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
BA = Address within the block. being erased.
PA = Address of memory location to be programmed,
3. SRD = Data read from Status Register. See Table 4 for a description of the Status Register bits.
PD = pata to be programmed at location PA. Data is latched on the rising edge of WE.
liD = Data read from inteligent Identifiers.
4. Following the intelligent identifier command, two read operations access manufacture and device codes.
5. Commands other than those. shown above are reserved by Intel for future device implementations and should not be
used.

Read Status RegisterCommand .
The 28F001 BX contains a Status Register which
may be read to determine when a program or'erase
operation is complete, and whether that operation
completed successfully. The Status Register may be
read at any time by writing the Read Status Register
command (70H) to the Command Register. After
writing this command,' all .subsequent read operations output data from the Status Register, until another valid command is written to the' Command
Register. The contents of the Status Register are
latched on the falling edge of OE or CE; whichever
occurs last in the read cycle. OE or CE must be
toggled to VIH before further reads to update the
Status Register latch .. The Read Status Register
command functions when Vpp = VpPLor VPPH.

reset by the Clear Status Register command. These
bits indicate various failure conditions (see Table 4).
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes or
erasing multiple blocks in sequence). The Status
Register may then be polled to determine if an error
occurred during that series. This adds flexibility to
the way the device may be used. '
Additionally, the Vpp Status bit (SR.3), when set to
"1", MUST be reset by system software before further byte programs or block erases are attempted.
To clear the Status Register, the Clear Status Register command (SOH) is written to the CommandReg~
ister. The Clear Status Register command is functional when Vpp = VPPL or VPPH'

Clear Status Register Command
The .Erase Status and Program Status bits are set to
"1" by the Write State Machine and can only be

3-125

int'et

28F001BX-T/28F001BX-B

Table 4. 28F001BX Status Register Definitions

WSMS

ESS

ES

PS

VPPS

R

7

6

5

4

3

2,

SR.? = WRITE STATE MACHINE STATUS
1= Ready
0' = Busy

R

R

o

NOTES:
.
The Write State Machine Status Bit must first be checked
to determine program or erase completion, before the
Program or Erase Status bits are checked for success.

SR.6 = ERASE SUSPEND STATUS
1 =, Erase Suspended
o =, Erase In Progress/Completed

If the Program AND Erase Status bits are set to "1 s" dur'
ing an erase attempt, an improper command sequence
was entered. Attempt the operation again.

SR.5 = ERASE STATUS
1 =. Error in Block Erasure
o = Successful Block Erase

If Vpp low status is detected, the Status Register'must be
cleared before another program or erase operation is attempted.

SR.4 = PROGRAM STATUS
1 = Error in Byte Program
. 0 = Successful Byte Program

The Vpp Status bit, unlike an AID COnverter, does not
provide continuous indication of Vpp level. The WSM interrogates the Vpp level only after the program or erase
command sequences. have been entered and informs the
system if Vpp .has not been switched on. The Vpp .Status
bit is not guaranteed to' report accurate feedback between VpPL and VPPH.

SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
SR.2-SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
.
These bits are reserved for future use and should be
masked out when polling the Status Register.

the Vpp Status bit will. be set to "1". Erase attempts
while VpPL < Vpp < VPPH produce spurious results
and should not be attempted.

Erase Setup/Erase Confirm
Commands
Erase is executed one block at a time,. initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command
Register, followed by the Erase Confirm command
(DOH). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all. handled internally by the Write State Machine,
invisible to the system. After receiving the two-command erase sequence, the 28F001 BX automatically
outputs Status Register data when read (see Figure
10; Block Erase Flowchart) ..The CPU can detect the
completion of the erase event by checking the WSM
Status bit of the Status Register (SR.7).
When the Status Register indicates that erase is .
complete, the Erase Status bit should be checked. If ,
erase error is detected, the Status Register should
be cleared. The Command, Register remains in Read
Status Register Mode until further commands are is,sued to it.
This two-step sequence of set-up followed byexecution ensures that memory contents are not accidentally erased. Also, block erasure can only occur
when Vpp = VPPH. In the absence of this high voltage, memory contents are protected again'st erasure. If bl.ock erase is attempted While Vpp = VPPL,

Erase Suspend/Erase Resume
Commands
The Erase Suspend Command allows erase sequence interruption in order to read data from .another block of memory. Once the erase sequence is
started, writing the Erase Suspend command (BOH)
to the 'Command Register requests that the WSM
suspend the erase sequence at a predetermined
point in the erase algorithm. The 28F001 BX continues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling
the WSM Status and Erase Suspend Status bits will
determine when the erase operation has. been suspended (both will be set to "1s").
At this point, a Read Array command can be written
to the Command Register to read data from blocks
other than that which is suspended. The only othc
er valid commands at this time are Read Status Register (70H) and Erase Resume (DOH), at which time
the WSM will continue with the erase sequence. The
Erase Suspend Status and WSM Status bits of the
Status Register will be cleared. After the Erase Re~
sume command is written tO'it, the 28F001 BX automatically outputs Status Register data when read
(see Figure· 11; Erase Suspend/Resume Flowchart).

3-126

intel .

28F001 BX-T128F001 BX-B

Program Setup/Program Commands
Programming is executed by a two-write sequence.
The program Setup command (40H) is written to the
Command Register, followed by a second write
specifying the address and data (latched on the rising edge of WE) to be programmed. The WSM then
takes' over, controlling the program and verify algorithms internally. After the two-command program
sequence is written to it, the 28F001 BX automatically outputs Status Register data when read (see figure 9; Byte Program Flowchart). The CPU can detect
the completion of the program event by analyzing
the WSM Status bit of the Status Register. Only the
Read Status Register command is valid while programming is active.
When the Status Register indicates that programming is complete, the Program Status bit should be
checked. If program error is detected, the Status
Register should be cleared. The internal WSM verify
only detects errors for "1 s" that do not successfully
program to "Os". The Command Register remains in
Read Status Register mode until further commands
are issued to it. If byte program is attempted while
Vpp = VPPL, the Vpp Status bit will.be set to "1 ".
Program attempts while VPPL < Vpp < VPPH produce spurious results and should not be attempted.

The 28F001 BX-B and 28F001 BX-T are specified for
a minimum of 10,000 program/erase cycles on each
of the two parameter blocks, main block and boot
block.

ON-CHIP PROGRAMMING
ALGORITHM
The 28F001 BX integrates the Quick-Pulse programming algorithm of prior Intel Flash devices on-chip,
using the Command Register, Status Register and
Write State Machine (WSM). On-chip integration
dramatically simplifies system software and provides
processor-like interface timings to the Command
and Status Registers. WSM operation, internal program verify and Vpp high voltage presence are monitored and reported via appropriate Status Register
bits. Figure 9 shows a system software flowchart for
device programming. The entire sequence is performed with Vpp at VPPH. Program abort occurs
when PWD transitions to VIL, or Vpp drops to VPPL.
Although the WSM is halted, byte data is partially
programmed at the location where programming
was aborted. Block erasure or a repeat of byte programming will initialize this data to a known value.

ON-CHIP ERASE ALGORITHM
EXTENDED ERASE/PROGRAM
CYCLING
.
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled; an
expensive solution.
Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electrical field is onetenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally, the
peak electric field during erasure is approximately 2
Mv/cm lower than EEPROM. The lower electric field
greatly reduces oxide stress and the probability of
failure; increasing time to wearout by a factor of
100,000,000.

As above, the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally, including all preconditioning of block data. WSM operation, erase success and Vpp high voltage presence
are monitored and reported through the Status Register. Additionally, if a command other than Erase
Confirm is written to the device after Erase Setup
has been written, both the Erase Status and Program Status bits will be set to "1 ". When issuing the
Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 10 shows a
system software flowchart for block erase.
Erase typically takes 1-4 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows interrupt of this erase operation to read data
from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 11.
The entire sequence is performed with Vpp at VPPH.
Abort ,occurs whenPWD transitions to VIL or Vpp
falls to VPPL, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.

3-127

28F001 BX·T/28F001 BX·B

BOOT BLOCK PROGRAM AND
ERASE
,The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the device, if needed. Therefore, additional "lockout" protection is provided to guarantee data integrity. Boot
block program and erase operations are enabled
through high voltage VHH on either PWD or OE, ?nd
the normal program and erase command sequences
are used. Reference the AC Waveforms for Program/Erase.
If boot block program or, erase is attempted while
PWD is at VIH, either the Program Status or Erase
Status bit' will be set to "1", reflective of the opera-

tion being attempted and indicating boot block lock.
Program/erase attempts while VIH < PWD< VHH
produce spurious results and should not be attempted.
In-System Operation
For on-board programming, the PWD pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, PWD
must transition to VHH. Hold PWD at this high voltage throughout the program or erase interval (until
aftE!r Status Register confirm of successful completion). At this time, it can return to VIH or VIL.

Bus
Operation

Command

Comments

Write

Program
Setup

Data = 40H
Address = Byte to be
Programmed

Write

Program

Data to be programmed
Address = Byte to be
Programmed
Status Register Data.
Toggle OE or CE to update
Status Register
CheckSR.7
1 = Ready, 0 = Busy

Read
Standby

Repeat for subsequent bytes.
Full status check can be don~ after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.

FULL STATUS CHECK PROCEDURE
Bus
Operation

Command

Comments

Standby

Check SR.3
1 = Vpp Low Detect

Standby

CheckSR.4
1 = Byte Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290406-7

SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes 'are
programmed before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 9. 28F001BX Byte Programming Flowchart
3-128

intel~

28F001 BX-T/28F001 BX-B

BUB

Operation

Command

Comments

Write

Erase
Setup

Data ~ 20H
Address ~ Within Block to be erased

Write

Erase

Data ~ DOH
Address = Within 810ck to be erased
Status Register Data.
Toggle DE or CE to update Status Register

Read

Standby

Check SR.7
1 ~ Ready, 0

~

Busy

Repeat for subsequent blocks.
Full status check can be done after each block or after a sequence Of
blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.

FULL STATUS CHECK PROCEDURE
BUB

Operation

Vpp Range

Command

Comments

Standby

Check SR.3
1 ~ Vpp Low Detect

Command Sequence
Error

Standby

Check SR.4, 5
Both 1 ~ Command Sequence Error

Block Erase
Error

Standby

CheckSR.5
1 ~ Block Erase Error

Error

SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
290406-8

SA.5 is only cleared by the Clear Status Register Command, in cases
where multiple blocks are erased before full status is checked.
If error is detected, clear the Status Register before attempting retry or
other error recovery.

Figure 10. 28F001BX Block Erase Flowchart

3-129

int:et

28F001BX·T/28F001BX·B

Bus
Operation

Command

Comments

Write

Erase
Suspend

Data = BOH

Write

Erase
Status Register

Data = 70H

Standby/
Read

Read Status Register
CheckSR.7
1 = Ready, 0 = Busy
Toggle OE or CE to
Update Status Register

Standby

CheckSR.6
1 = Suspended

Erase Has
Completed

Write

Read Array

Read

Write

Data = FFH

Read array data from
block other than that
being erased.
Erase Resume

Data = DOH

290406-9

Figure 11. 28F001 ex Erase Suspend/Resume Flowchart
date multiple memory connections. Three-line control provides for:

Programming Equipment
For PROM programming equipment that cannot
bring PWD to high voltage, OE e!:Qvides an alternate
boot block access mechanism. OE must transition to
VHH a minimum of 480 ns before the initial program/
erase setup command and held at VHH at least
480 ns after program or erase confirm commands
are issued to the device. After this interval, OE can
return to normal TTL levels.

DESIGN· CONSIDERATIONS
Three-Line Output Control
Flash memories are often used in larger memory arrays. Intel provides three control inputs to accommo-

a} lowest possible memory power dissipation
b} complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CE, while OE should be connected to all memory devices and the system's
READ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode. Finally,
PWD should either be connected to Vcc if unused,
or tied to the system RESET.
.

3-130

intel"

28F001 BX·T/28F001 BX·B

Power Supply Decoupling
Flash memory power switching characteristics require careful device coupling. System designers are
interested in 3 supply current issues; standby current
levels (Iss), active current leve,ls (Ieel and transient
peaks producted by falling and rising edges of CEo
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress transient voltage peaks. Each device
should have a 0.1 p.F ceramic capacitor connected
between its Vee arid GND, and between its Vpp and
GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to the device. Additionally, for every 8 devices,
a 4.7 p.F electrolytic capacitor should be placed at
the array's power supply connection between Vee
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.

Vpp Trace on Printed Circuit ,Boards
Programming flash memories, while they reside in
the, target system, requires that the printed circuit "
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given to the Vee power bus.
Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

Vee, Vpp, PWD Transitions and the
Command/Status Registers
Programming and erase completion are not guaranteed if Vpp drops below VPPH. If the Vpp Status bit of
the Status Register (SR.3) is set to "1", a Clear
Status Register command MUST be issued before
further program/erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
(SR.5) Status bits of the Status Register will be set
to "1" if error is detected. PWD transitions to VIL
during program and erase also abort the operations.
Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or PWD transitions to VIL, clear the Status Register to initial value 80H.
The' Command' Register latches commands as issue.£Lby system software and is not altered by Vpp
or CE transitions or WSM actions. Its state upon
powerup, after exit from Deep Power Down or after
Vee transitions below VLKO, is FFH, or Read Array
Mode.

3-131

After program or erase is complete, even after Vpp
transitions down to VPPL, the Command Register
must be reset to read array mode via the Read Array
command if access to the memory array is desired.

Power Up/Down Protection
The 28F001 BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, the 28F001 BX is
indifferent as to which power supply, Vpp or Vee,
powers up first. Power supply sequencing is not required. Internal circuitry in the 28F001 BX ensures
that the Command Register is reset to Read Array
mode on power up.
A system designer must guard against spurious
writes for Vee volt~s above VLKO when Vpp is
active. Since both WE and CE must be low for a
command write, driving either to VIH will inhibit
writes. The Command Register architecture provides
an added level of protection since alteration of memory contents only occurs after successful completion
of the two-step command sequences.
Finally, the device is disabled, until PWD is brought
to VIH, regardless of the state of its control, inputs.
This provides an additional level of protection.

28F001BX Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases usable battery life because the 28F001 BX does not
consume any power to retain code or data when the
'
system is off.
In addition, the 28F001 BX's Deep Power Down
mode ensures extremely low power dissipation even
when system power is applied. For example, laptop
and other PC applications, after copying BIOS to
DRAM, can lower PWD to VIL, producing negligible
power consumption. If access to the boot code is
again needed, as in case of a system RESET, the
part can again be accessed, following the tpHAV
wakeup cycle required after PWD is first raised back
to VIH. The first address presented to the device
while in powerdown requires time tpHAV, after PWD
transitions high, before outputs are valid. Further accesses' follow normal timing. See AC Characteristics-Read-Only Operations and Figure 12 for more
information.
'

28F001BX·T/28F001BX·B

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read .................... O°C to 70°C(1)
During Erase/Program ........... O°C to 70°C(1)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Operating Temperature
During Read ............... - 40°C to + 85°C(2)
During Erase/Progrqm ...... - 40°C to + 85°C(2)
Temperature under Bias ......... -10°C to 80°C(1)
Temperature under Bias ....... - 20°C to + 90°C(2)
Storage Temperature ............. - 65°C to 125°C
Voltage on Any Pin
(except Ag, PWD, OE, Vee and Vpp)
with Respect to GND .......... - 2.0Vto 7.0V(3)
Voltage on Ag, PWD, and OE
with Respect to GND ....... - 2.0V to 13.5V(3, 4)
Vpp Program Voltage
with Respect to GND
During Erase/Program .. , ... - 2.0V to 14.0V(3, 4)
Vee Supply Voltage
with Respect to GND .......... - 2.0V to 7.0V(3)
Output Short Circuit Current ............. 100 mA(5)
NOTES:

1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
3. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may ,undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee +0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
4. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods <20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS
Symbol

Parameter

Min

Max

TA

Operating Temperature(1)

0

70

°c

TA

Operating Temperature(2)

-40

85

·C

Vee

Supply Voltage

4.50

5.50

V

DC CHARACTERISTICS
Symbol

Vee

=

5.0V ±10%, TA

Parameter

Notes

Unit

=

Min

O·Cto +70·C

Typ

Max

Unit

Test Conditions

IlL

Input Load Current

1

±1.0

/J- A

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

/J- A

Vee = Vee Max
VOUT = VeeorGND

lees

Vee Standby Current

1.2

2.0

mA

Vee = Vee Max
CE = PWD = VIH

30

100

/J- A

Vee = Vee Max
CE = PWD = Vee ±0.2V

0.05

1.0

/J- A

PWD

leeD

Vee Deep PowerDown Current

1

3-132

=

GND ± 0.2V

int:et

28F001 BX-T/28F001 BX-B

DC CHARACTERISTICS
Symbol

Vee

;=

5.0V ± 10%, T A = O·C to

Parameter

Notes Min Typ

+ 70·C (Continued)
Unit

Max

Test Conditions

leeR

Vee Read Current

1

13

30

rnA Vee = Vee Max, CE = VIL
f = 8 MHz, lOUT = 0 rnA

leep

Vee Programming Current

1

5

20

rnA Programming in Progress

IeeE

Vee Erase Current

leeES

Vee Erase Suspend Current

Ipps

1

6

20

rnA Erase in Progress

1,2

5

10

rnA Erase Suspended
CE = VIH

Vpp Standby Current

1

±1

±10

p.A Vpp::'; Vee

90

200

p.A Vpp> Vee

IpPD

Vpp Deep PowerDown Current

1

0.80

1.0

p.A PWD

Ippp

Vpp Programming Current

1

6

30

rnA Vpp
Programming in Progress

IpPE

Vpp Erase Current

1

6

30

rnA Vpp = VPPH
Erase in Progress

IpPES

Vpp Erase Suspend Current

1

90

300

p.A Vpp = VPPH
Erase Suspended

liD

A91ntelligent Identifier Current

1

90

500

p.A A9

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

= GND
= VPPH

0.8
Vee

+ 0.5

2.4

V
V

Vee = Vee Min
IOL = 5.8 rnA

V

Vee = Vee Min
IOH = 2.5 rnA

11.5

13.0

V

0.0

6.5

V

Vpp during Prog/Erase Operations

11.4 12.0

12.6

V

Vee Erase/Write Lock Voltage

2.5

PWD, OE Unlock Voltage

11.4

A9 Intelligent Identifier Voltage

VPPL

Vpp during Normal Operations

VPPH
VLKO
VHH

DC CHARACTERISTICS

3

VID

V

0.45

VID

=

± 0.2V

V
12.6

Vee = 5.0V ±10%, TA = -40·Cto

Boot Block Prog/Erase

+ 85·C

Max

Unit

IlL

Input Load Current

1

±1.0

p.A

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

p.A

Vee = Vee Max
VOUT = VeeorGND

lees

Vee Standby Current

1.2

2.0

rnA

Vee = Vee Max
CE = PWD = VIH

30

150

p.A

Vee = Vee Max
CE = PWD = Vee ±0.2V

Symbol

Parameter

Notes

Min

Typ

V

3-133

Test Conditions

28F0018X;.T128F0018X-8

DC CHARACTERISTICS
Symbol

vcc

= 5.0V

±10%, TA

=

-,40"Cto +S5°C(Continued)

Notes Min Typ

Parameter

Max

Unit

Test Conditions

= GND ± 0.2V

ICCD

VCC Deep PowerDown (;urrent

1

0.05

2.0

p,A PWD

ICCR

Vcc Read Current

1

13

35

mA Vcc = Vec Max, CE = VIL
f = SMHz, IOUi' = 0 mA

Iccp

Vcc Programming Current

1

5

20

mA Programming in Progress

ICCE

Vee Erase Current

1

6

20

mA Erase in Progress

ICCES

VCC Erase Suspend Current

1,2

5

10

mA Erase Suspended
CE = VIH

IpPS

Vpp Standby Current

1

±1

±10

p,A Vpp:'; VCC

90

400

p,J1. Vpp> VCC

= GND ± 0.2V

Ippo

Vpp Deep PowerDown Current

O.SO

1.0

p.A PWD

Ippp

Vpp Programming Current

1

6

30

p,A Vpp = VPPH
Programming in

IpPE

VPP Erase Current

1

6

30

mA Vpp = VPPH
Erase in Progress

IpPES

VPP Erase Suspend Current

1

90

400

p,A VPP = VPPH
Erase Suspended

110

As Intelligent Identifier Current

1

90

500

p,A As

VIL

Input Low Voltage

-0.5

O.S

V

/ VIH

Input High Voltage

2.0

Vee + 0.5

V

0.45

V

VCC = VccMin
IOL = 5.SmA

V

Vee = Vcc Min
IOH = 2.5mA

.1

VOL

Output Low Voltage

VOH

Output High Voltage

2.4

VIO

As Intelligent Identifier Voltage

11.5

V

0.0

6.5

V

11.4 12.0

12.6

V

VPPL

VPP during Normal Operations

VPPH

VPP during Prog/Erase Operations

VLKO

Vce Erase/Write Lock Voltage

2.5

VHH

PWD, DE Unlock Voltage

11.4

CAPACITANCE(4)
Symbol

3

13.0

= VIO

V
12.6

V

Boot Block Prog/Erase

TA = 25°C, f = 1 MHz

Max

. Unit

CIN·

Input Capacitance

S

pF

VIN = OV

COUT

Output Capacitance

12

pF

VOUT = OV

NOTES:

Progre~s

Parameter

Conditions

. .

1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, TA = 25'C. These currents·
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. II the 28F001 BX is read while in Erase Suspend mode,current draw is the
sum.ol leeEs and ICCR.
,
3. Erase/Programs are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and VPPL.
4. Sampled, not 100% tested.

3-134

int:eL

28F001 BX-T /28FOO 1BX-B

AC INPUT/OUTPUT REFERENCE WAVEFORM

2.4 ___IN_P_UT_-",X
0.45

~:~ > TES/~OINTS <

AC TESTING LOAD CIRCUIT

X

SS

1.3V

~:~ OUTPUT

1N914

290406-10

RL

A.C. test inputs are driven at VOH (2.4 VTn) for a Logic "1" and VOL (0.45
Vnd' for a Logic "0". Input timing begins at VIH (2.0 Vnd and VIL (O.B
Vnd. Output timing ends at VIH and VIL. Input rise and fall times (10% to
900/~) < 10 ns.
. .

1--+--0 OUT

290406-11

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 k!1

AC CHARACTERISTICS-Read-Only Operations(1)
E28FOO1BX~120

Versions(2)

Symbol

N28FOO1BX-120
P28FOO1BX-120

Vee ±10%

Parameter

Notes

Read Cycle Time

Max

120

tAVAV

tRC

tAVOV

tACC

Address to Output Delay

tELOV

tCE

CE to Output Delay

tpHOV

tPWH

PWD High to Output Delay

tGLOV

tOE

OE to Output Delay

3

tELOX

tLZ

CE to Output Low Z

4

tEHOZ

tHZ

CE High to Output High Z

4

tGLOX

tOLZ

OE to Output Low Z

4

tOF

OE High to Output High Z

4

tOH

Output Hold from
Addresses, CE or OE
Change, Whichever is First

4

tGHOZ

Min

3

E28FOO1BX-150
TE28FOO1BX-150
N28FOO1BX-150
TN28FOO1BX-150
P28F001 BX-150
Min

Max.
ns

150
120

150

ns

120

150

ns

600

600

ns

50

55

ns

0

ns

0
55

0

55

30
0

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. Model Number Prefixes: E = TSOP (Standard Pinout), N = PLCC, P = PDIP, T = Extended Temperature.
3. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
4. Sampled, not 100% tested.

3-135

ns·
ns

0
30

0

Unit

ns
ns

_.

::l

~

V,H

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

c(

STANDBY

( A A A A X AlL
ADDRESSES STABLE

ADDRESSES (A)
V,L
\-

'AYAY

\.\

V,H

CE (e)
."

I

iQ.

...

c::

CD

....
>
0

!"

V,H

:IE
Dl

V,L

...30
...0

V,H

-

U)

0)

...oo

tD

<
CD

-~

N
CI
."

liE (G)

><

~
......

WE (w)
V,L

a.
0

"C
CD

-

o
o

toH

::tI

.CD
Dl

N
CI
."

...

.

tD

V,H
HIGH Z

DATA (0/0)

iii
\Cr

VALID OUTPUT

><

HIGH Z

tD

V,L

I-

:::J

'AYQV

·1

(/I

s.OV

Vee
GND

IH
PWD(P)V

I'

J

"'"

.1

~

.~

V,L

290406-12

infel .

28F001BX-T/28F001BX-B

AC CHARACTERISTICS-Write/Erase/Program Operations(1)

I

Versions
Symbol

Vee

Notes

tAVAV

twc

Write Cycle Time

tPHWL

tps

PWD High Recovery to WE Going Low

tELWL

tcs

CE Setup to WE Going Low

tWLWH

.twP

WE Pulse Width

tPHHWH tpHS

28FOO1BX-120 28FOO1BX-150

±10%

Parameter

2
2
3
4

PWD VHH Setup to WE Going High

tVPWH

tvps

YPP Setup to WE Going High

tAVWH'

tAS

Address Setup tQ WE Going High

tOVWH

tos

Data Setup to WE Going High

tWHOX

tOH

Data Hold from WE High

tWHAX

tAH

Address Hold from WE High

tWHEH

tCH

CE Hold from WE High

tWHWL

tWPH

WE Pulse Width High

2

tWHQV1

Duration of Programming Operation

5,6,7

tWHQV2

Duration of Erase Operation (Boot)

tWHQV3

Duration of Erase Operation (Parameter)

5,6,7
5,6,7
5,6,7

tWHQV4

Duration of Erase Operation (Main)

tWHGL

Write RecovElry before Read

tQWL'

tVPH

Vpp Hold from Valid SRD

taVPH

tpHH

PWD VHH Hold from Valid SRD

2,6
2, 7
2

Boot-Block Relock Delay

tpHBR

Min

Max

120
480
10
50

Min

150
480
10
50
100
100
50
50
10
10
10
50
15
1.3
1.3
3.0
0
0
0

100
100
50
50
10
10
10
50
15
1.3
1.3
3.0
0
0
0
100

Unit

Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
,...s
sec
sec
sec
,...s
ns
ns

100

ns

PROM Programmer Specifications
Versions
Symbol
tGHHWL
tWHGH

I
I

I

Vee

28FOO1BX-120 28FOO1BX-150

±10%

Parameter

DE VHH Setup to WE Going Low
DE VHH Hold from WE High'

Notes

Min

2,8
2,8

480
480

Max

Min

480
480

Unit

Max
ns
ns

NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for.Read-Only Operations.
2. Sampled, not 100% tested.
3.-Refer to Table 3 for valid AIN for byte programming or block erasure. '
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
~. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
flash memory, including byte program and verify (programming) and block. precondition, precondition verify, erase and erase
verify (erasing).
6. Program and erase durations are measured to completion (SR.7 = 1). Vpp should be held at VPPH until determination of
program/erase success (SR.3/4/5 = 0).
'
7. For boot block, programming and erasure, PWO should be held at VHH until determination of program/erase success
'
(SR.3/4/5 = 0).
B. Alternate boot block access method.

3-137

inial .

28F001 BX-T/28F001 BX-B

ERASE ANQ PROGRAMMING PERFORMANCE
Parameter

Notes

28FOO1BX-120
Min

Typ(1)

28FOO1BX-150
Max

Min

Typ(1)

Max

Unit

Boot Block Erase Time

2

2.10

14.9

2.10

.14.9

Sec

Boot Block Program Time

2

0.15

0.52

0.15

0.52

Sec

Parameter Block Erase Time

2

2.10

14.6

Sec

Parameter Block Program Time

2

. 2.10
. 0.07

14.6
0.26

Sec

2

3.80

20.9

0.07
3.80 .

0.26.

Main Block Erase Time

20.9

Sec

Main Block Program Time

2

2.10

7.34

2.10

7.34

Sec

Chip Erase Time

2

10.10

65

10.10

65

Sec

Chip Program Time

2·

2.39

8.38

2.39

8.38

Erase/Program Cycles (per Block)

10,000

100,000

NOTES:

1. 25°C. 12:0 Vpp.
2. Excludes System-Level Overhead.

3-138

10,000

100,000

Sec
Cycles

intel .

28F001 BX-T/28F001 BX-B

99.9

,,/., "

vV
99

1/

95

80

,,' "

-/,,#

70

V,,"

/

I

,
~'

,

60
50
40

/

30

"

~/.#,,##
' ,

/

/

90

"

20

II ,

10

:"

,..

, "

"

"

.

0.1

2

2.S

3

3.5 4 4.5 5

10

15

20

Chip Program Time (Sec)
- - - 12V, 10 kc, 23C
.. - - - - - - 1 f.4Vj 10 kc: 70C
- - - - 12Vi 100 kCi 23C

290406-19

Figure 13. 28F001BX Typical Programming Capability
7.5
I

.'

,/
6.5

,
/

/
I

.::l

5.5

,
I

w
;=

"

.5~

I

4.5

I

/

.....

.;'
.~

/

,.,

,1/

3.5

,,

.' .- V.'
/

I

,I

J

I
I
I
I.

I

2.5

2

.
o

i

I

10

20

30'

40

50

I

I

60

V
70

80

90

100

110 120 130

TEMP (C)
- - 1k Cycles
• - _. 10k Cycles
- - - 10Dk Cycles

290406-20

Figure 14. 28F001BX Typical Programming Time at 12)1
3-139

intel .

28F001 BX-T/28F001 BX-B

,y

99.9

,

99

I
95
90

,,

,

,I

V ,, /

80

/

70
50

30

I

20

1/;#

I~

I

40

I' ,

"

60

,'/

I 1/
I

/ li

10

III

",""
'I

1

'I

J7

O. 1
0.5

0.7

4

5 6' 7 8 9 10

20

30

MAIN BLOCK ERASE TIME (SEC)

12V; 10 kc;23C
11.4V;10 kc;OC
12V;100 kc;2~C

------

290406-21

Figure 15. 28F001BX Typical Erase Capability

3.2

3.0

,
\

,,

2.8

\
2.6

,

,

2.4

,
2.2

2.0

1.8

1.6

,

,,

,

,,
,,

" "-

,

1.4

,
,,

i'- r-...

"

,,

. . . r-.,

1.2

1.0
OW

W

~

~

,,

,

~

~

ro

,

....
"I'

,

r-.,

~

"

~

,

........

t- t-

1001W1W1~~

TEMP (DC)
_1kC),cles
----10k Cycles,

- - - 10ak Cycles

Figure 16. 28F001BX Typical Erase Time at 12V
3-140

290406-22

_.

Vee POWSI-UP
~ STANDBY

WRITE PROGRAM OR
ERASE SETUP COMMAND

WRITE
VALID ADDRESS ~ DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

::l

c[

WRITE READ ARRAY
COMMAND

VIH

@

ADDRESSES (A)
VIL
VIH

cr (E)
VIL

!!

VIH

CQ

C

~

(II

Or (G)

-"

;-.s

VIL

»
0

:e
1\1

~
~

N
CD

'TI

o

VIH

....o

WE (W)

III

~
....
0

~
......

VIL

~

3
....
0
~

:e::!.

..
(II

N
CD

VIH

'TI

o
o....

DATA (D/a)

III

VIL

0

I-

'tJ
(II
~

VHH

1\1

::!:
0
::I
!II

I

PWD (p) 6.5V
VIH

><
I

III

-llpHHwH

/

VIL
tyPWH
VpPH

Vpp (v) VpPL

VIH

VIL

D) ' ) / \ / \ Of) /) /) () () () ()

1\ (\ 'J
290406-13

intel~

28F001BX·T/28F001BX·B

WRITE PROGRAM OR
WRITE
ERASE SETUP COMMAND· VALID ADDRESS AND DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
VHH

OE (G)

VIH
VIL

WE (W)

VIH

---c;-

VIH

DATA (O/Q)
VIL

(

DJN

READ STATUS
REGISTER DATA

;J

-U

VIL

AUTOMATED PROGRAM
OR ERASE DELAY

'---.J

H

DJN

)}-----------~55s-------~{~__S_~A_~_I~_A_J}____
290406-15

Figure 18. Alternate Boot Block Access Method Using OE

3-142

intel~

.

28F001 BX-T 128F001 BX-B

ALTERNATE CE-CONTROLLED WRITES(1)

I

Versions
Symbol

28FOO1BX-120

Vee±10%

Parameter

28FOO1BX-150
Min

Max

Unit

Max

Notes

Min

120

150

ns

2

480

480

ns

twc

Write Cycle Time

tpHEL

tps

PWD High Recovery to CE Going Low

tWLEL

tws

WE Setup to CE Going low

0

0

ns

tELEH

tcp

CE Pulse Width

70

70

ns

tpHHEH

tPHS

PWD VHH Setup to CE Going High

2

100

100

ns

tVPEH

tvps

VPP Setup to CE Going High

2

100

100

ns

tAVEH

tAS

Address Setup to CE Going High

3

50

50

ns

tDVEH

tDS

Data Setup to CE Going High

4

50

50

ns

tEHDX

tDH

Data Hold from CE High

10

10

ns

tEHAX

tAH

Address Hold from CE High

15

15

ns

tEHWH

tWH

WE Hold from CE High

0

0

ns

tEHEL

tEPH

CE Pulse Width High

25

25

ns

tAVAV

{

tEHOV1

Duration of Programming Operation

5,6

15

15

,""s

tEHOV2

Duration of Erase Operation (Boot)

5,6

1.3

1.3

sec

tEHOV3

Duration of Erase Operation (Parameter)

5,6

1.3

1.3

sec

tEHOV4

Duration of Erase Operation (Main)

5,6

3.0

3.0

sec

tEHGL

Write Recovery before Read

0

0

,""S

tOVVL
tOVPH
tpHBR

tVPH

VPP Hold from Valid SRD

2,5

0

0

ns

tpHH

PWD VHH Hold from Valid SRD

2,6

0

0

ns

2

Boot-Block Relock Delay

100

10

ns

PROM Programmer Specifications
Versions
Symbol

I

28FOO1BX-120

28FOO1BX-150

Notes

Min

Min

Vee ±10%

Parameter

Max

Max

Unit

tGHHEL

OE VHH Setup to CE Going Low

2, 7

480

480

ns

tEHGH

OE VHH Hold from CE High

2, 7

480

480

ns

NOTES:
1. Chip-EnabiE! Controlled WritE!s: WritE! operations arE! driven by the valid combination of CE and WE. In systems where CE
dE!fines the write pulsE! width (within a longer WE timing waveform). all set-up, hold and inactive WE times should be measured relativE! to the CE waveform.
2. Sampled. not 100% tested.
3. Refer to TablE! 3 for valid AIN for byte programming or block erasure.
4. Refer to TablE! 3 for valid DIN for byte programming or block erasure.
5. Program and eraSE! durations arE! measured to completion (SR.7 = 1). Vpp should bE! held at VpPH until determination of
program/E!rasE! success (SR.3/4/5 = 0).
6. For boot block programming and erasurE!, PWD should bE! hE!ldat VHH until dE!termination of program/erase success
(SR.3/4/5 = 0).
7. AlternatE! boot block access method.

_.

Va: POWER-UP
I: STANDBY

WRITE PROGRAM OR
ERASE SETUP COMMAND

~WRITE

~ VAUD

ADDRESS I: DATA (PROGRAII)
_OR ERASE CONFIRM COMMAND

AUTOMATED PROGRAM

READ STATUS

WRITE READ ARRAY

OR ERASE DELAY

REGISTER DATA

COMMAND

l..

V.H
ADDRESSES (A)

V.H

il
c

iE(W)
V,l

C;

--I...
~

~

'aiel
V,H

liE (G)

if

,-

V/L

;:,

1\1
CD
~

~

8....

fa!aVl,2,3,4

V,H

CE (E)

ID

0

...
~

t

~

VIL

I\)

CD

~I

0'
...
0

"II

Q
Q

HIGH Z

DATA (D/Q)
~

....

~

V,L

~

;:;:
CDI

CD

V.H

VHH

I'

ID

-'I"'HHO!

"CI

CD

il
0

Piii (p) 6.5V
V,H

;:,

II'

V,l

'vP£H
VPPH

Vpp (V) VPPL

V,H ~
V/L

290406-16

infel .

.28F001 BX-T128F001 BX-B

ORDERING INFORMATION

r

y,

l~CESSn.

PACKAGE
E STANDARD 32 LEAD TSOP
N 32 LEAD PLCC
P 32-PIN PLASTIC DIP

SPEED (ns)
120
150 ns

T TOP BOOT DEVICE
.
B BOTTOM BOOT DEVICE

TEMPERATURE RANGE
T= EXTENDED (-40°C \0+8S 0C)
BLANK = COMMERCIAL (OOC \0 +70 0 C)

VALID COMBINATIONS:
E28F001 BX·T120
N28F001 BX·T120
E28F001BX·T150
N28F001BX·T150
TE28F001 BX·T150 TN28F001 BX·T150
E2BF001BX·B120
E2BF001BX·B150
TE2BF001BX·B150

290406-18

P28F001 BX·T120
P28F001BX:T150

N28F001BX·B120
P28F001BX·B120
N28F001BX·B150
P28F001BX·B150
TN28F001BX·B150'

ADDITIONAL INFORMATION
ER·20 "ETOXTM II Flash Memory
Technology"
RR·60 "ETOXTM II Flash Memory
R~liability Data Summary"

Order
Number
294005
293002

Ap·316 "Using Flash Memory for In·
System Reprogrammable
Nonvolatile Storage"
Ap·341 "Designing an Updatable BIOS
Using Flash Memory"

Order
Number
292046

292077

REVISION HISTORY·
Number
·004

Description
Removed Preliminary classification.
Latched address A16 in Figure 5.
Updated Boot Block Program and Erase section: "If boot block program or erase is attempted
while PWD is at VIH. either the Program Status or Erase Status bit will be set to "1",
reflective of the operation being attempted and Indicating boot block lock."
Updated Figure 11. 28F001 BX Erase Suspend/Resume Flowchart
Added DC Characteristics typical current values
Combined Vpp Standby current and Vpp Read current into one Vpp Standby current spec with
.two test conditions (DC Characteristics table)
Added maximum program/erase times to Erase and Programming Performance table.
, Added Figures 13-16
Added ExtE;lnded Temperature proliferations

3·145

28F200BX-T/B,28F002BX-T/B
2 MBIT (128K x 16, 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
•

x8/x16 Input/Output Architecture
- 28F200BX-T, 28F200BX-B
- For High Performance and High
Integration 16-bit and 32-bitCPUs

• x8-only Input/Output Architecture
- 28F002BX-T 28F002BX-B
- For Space Constrained 8-bit
Applications
• Optimized High Density Blocked
Architecture
-One 16 KB Protected Boot Block
- Two 8 KB Parameter Blocks
- One 96 KB Main Block
- One 128 KB Main Block
- Top or Bottom Boot Locations
•

Extended Cycling Capability
-100,000 Block Erase Cycles

•

Automated Word/Byte Write and
Block Erase
- Command User Interface
- Status Registers
- Erase Suspend Capability

•

SRAM-Compatible Write Interface

•

Very High-Performance Read
- 60/80 ns Maximum Access Time
-30/40 ns Maximum Output Enable
Time

•

Low Power Consumption
- 20 rnA Typical x8 Active Read
Current
;..... 25 rnA Typical x16 Active Read
Current

• Deep P()wer-Down/Reset Input
- 0.2 p,A Icc Typical
- Acts as Reset for Boot Operations
• Extended Temperature Operation
- - 40°C to + 85°C
• Write Protection for Boot Block
• Industry Standard Surface Mount
Packaging
- 28F200BX: JEDEC ROM Compatible
44-Lead PSOP
.
56-Lead TSOP
;,... 28F002BX: 40-Lead TSOP
•

• Automatic Power Savings Feature
- 1 rnA Typical Icc Active Current in
Static Operation

12V Word/Byte Write and Block Erase
-Vpp == 12V ±5% Standard
- Vpp = 12V ± 10% Option

•

ETOXTM III Flash Technology
-5V Read

•

•

Independent Software Vendor Support
- SystemSoft*. Flash BIOS
.

Hardware· Data Protection Feature
- Erase/Write Lockout during Power
Transitions

·SystemSoft is a trademark of SystemSoft Corporation.

3-146

November 1992
Order Number: 290448-002

int:eL

28F200BX-T/B,28F002BX-T/B

Intel's 2 Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 2 Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very high speed, low power, an industry standard ROM compatible pinout and surface mount
packaging. The 2 Mbit flash family allows for an easy upgrade to Intel's 4 Mbit Boot Block Flash Memory
Family.
The Intel 28F200BX-T/B are 16-bit wide flash memory offerings. These,high density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BX-T and 28F200BX-B are
2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.
The Intel 28F002BX-T /B are 8-bit wide flash memories with 2,097,152, bits organized as 262,144 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F200BX-T /28F002BX-T provide block locations compatible with
Intel's MCS-186 family, 80286, i386™, i486™, i860™ and 80960CA microprocessors. The 28F200BX-B/
28F002BX-B provide compatibility with Intel's 80960KX and 80960SX families as well as other embedded
microprocessors.
.
. The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 60 ns, these 2 Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down
mode lowers the total Vee power consumption to 1 p.W typical. This is critical in handheld battery powered
systems. For very low power applications using a 3.3V supply, refer to the Intel 28F200BX-TL/BL, 28F002BXTLlBL 2 Mbit Boot Block Flash Memory Family datasheet.
Manufactured on Intel's 0.8 micron ETOXTMIII process, the 2 Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 2 Mbit density level.

3-147

28F200BX·TIB, 28F002BX·TIB

1.0 PRODUCT FAMILY OVERVIEW
Throughout this datasheet the 28F200BX refers to '
both the 28F200BX-T and 28F200BX-B devices and
28F002BX refers to both, the 28F002BX-T and
28F002BX-B devices. The 2 Mbit flash memory family refers to both the 28F200BX and 28F002BX products. This datasheet comprises the specifications for'
four separate products in the 2 Mbit flash memory
family. Section 1 provides an overview of the 2 Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F200BX and 28F002BX' products respectively.
Section 4 combines a descriptioll of the family's
principles of operations. Finally Section 5 describes
the family's operating specifications.
PRODUCT FAMILY
x8/x16 Products

x8~Only

28F200BX-T

28F002BX-T

28F200BX-B

2~F002BX-B

Products

1.1 Main Features
The 28F2'OOBX/28F002BX boot block fla!jlh memory
family is a very high performance 2 Mbit (2,097,152
bit) memory family organized as either 128 KWords
(131,072 words) of 16 bits each or 256 Kbytes
(262,144 bytes) of 8 bits each.
Five Separately Erasable Blocks including a hardware·lockable boot block (16,384 Bytes), two parameter blocks (8, 192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of
131,072 Bytes) are included on the 2 Mbit family. An
erase operation erases one of the main blocks in
typically 2.4 seconds, and the boot or parameter
blocks in typically 1.0 second. Each block can be '
independently erased and programmed 100,000
times.
The Boot Block is located at either the top
(28F200BX-T, 28F002BX-T) or' the bottom
(28F200BX-B, 28F002BX-B) of the address map in
order to accommodate different microprocessor protocols for boot code location. The hardware lockable boot block provides th'e most secure code storage. The boot block, is intended to store the kernel,
'code required for booting-up a system. When the
PWD pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the PWD pin is at or below 6.5V
the boot block is locked and program and erase operations to the boot block are ignored.

The 28F200BXproducts are available in the ROM I
EPROM compatible pinout and housed in the 44Lead PSOP (Plastic Small Outline) package and the
56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4. The
28F002BX products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon. troller and the internal' operation of the 28F200BX
and 28F002BX flash products. I
Program and Erase Automation allows program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) autQmatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the 28F200BX family and in byte
increments for the 28F002BX family typically within
9 ,...S which is a 100% improvement over current
flash memory products.
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the'desired program or erase operation.
Maximum Access Time of 60 ns (TACC)is achieved
over the' commercial temperature range (O·C to
70·C), 5% Vee supply voltage range (4.75V to
5.25V) and 30 pF output load. Refer to Figure 19;
TAee vs Output Load Capacitance. for larger output
loads. Maximum Access Time of 80 ns (TACC) is
achieved over the commercial temperature range,
10% Vee supply range (4.5V t05.5V) and 100 pF
output load.
Ipp maximum Program current Is 40 mA for x16
operation and 30 mA for x8 operation. Ipp Erase
current is 30 mA maximum.,Vpp erase and programming voltage Is 11.4V to 12.6V (Vpp = 12V
±5%) under all operating conditions. As an option, Vpp can also vary between 10.8V to 13.2V (Vpp
= 12V ±10%) with a guaranteed number of 100
block erase cycles.
Typical Icc Active Current of 25 mA is achieved
for the x16 products (28F200BX), typical Icc Active
Current of 20 mA is achieved for the x8 products
(28F200BX, 28F002BX). Refer to the lee active current derating curves in this datasheet.
The 2 Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs. Once the device is ac-

3-148

int:el.

28F200BX-T /B, 28F002BX-T /B

cessed to read array data, APS mode will immediately put the memory in static mode of operation
where Icc active current is typically 1 mA until the
next read is initiated.
When the CE and PWO pins are at Vcc and the
BYTE pin (28F200BX-only) is at either Vec or GNO
the CMOS Standby mode is enabled where Icc is
typically 50 IJ-A.
A Deep Power-Down Mode is enabled when the
PWO pin is at ground minimizing power consumption
and providing write protection during power-up conditions. Icc current during deep power-down mode
is 0.20 IJ-A typical. An initial maximum access time
or Reset Time of 300 ns is required from PWO
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recognized. When PWO is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to PWO to reset the memory to normal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
2 Mbit family and the PWO functionality for data protection, when the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until PWO returns to its normal
state.
For the 28F200BX, Byte-wide or Word-wide Input/Output Control ~ssible by controlling the
BYTE pin. When the BYTE pin is at a logic low the
device is in the byte-wide mode (x8) and data is read
and written through 00[0:7]. During the byte-wide
mode, 00[8:14] are tri-stated and 0015/ A -1 becomes the lowest order address pin. When the
BYTE pin is at a logic high the device is in the wordwide mode (x16) and data is read and written
through 00[0:15].

1.2 Applications
The 2 Mbit boot block flash· family combines high
density, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility and versatility will reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component
handling during the production phase. During the
product life cycle, when code updates or feature en-

hancements become necessary, flash memory will
reduce the update costs by allowing either a userperformed code change via floppy disk or a remote
code change via a serial link. The 2 Mbit boot block
flash family provides full function, blocked flash
memories suitable for a wide range of applications.
These applications include Extended PC BIOS,
Digital Cellular Phone program and data storage,
Telecommunication boot/firmware, and various·
other embedded applications where both program
and data storage are required.
Reprogrammable systems such as personal computers, are ideal applications for the 2 Mbit flash
products. Portable and handheld personal computer
applications are becoming more complex with the
addition of power management software to take advantage of the latest microprocessor technology,
the availability of ROM-based application software,
pen tablet code for electronic hand writing, and diagnostic code. Figure 1 shows an example of a
28F200BX-T application.
This increase in software sclphistication augments
the probability that a code update will be required
after the PC is shipped. The 2 Mbit flash products
provide an inexpensive update solution for the notebook and handheld personal computers while extending their product lifetime. Furthermore, the
2 Mbit flash products' power-down mode provides
added flexibility for these battery-operated portable
designs which require operation at very low power
levels.
The 2 Mbit flash products also provide excellent design solutions for Digital Cellular Phone and Telecommunication switching applications requiring high
performance, high density storage capability coupled with modular software designs, and a small
form factor package (x8-only bus). The 2 Mbit's
blocking scheme allows for an easy segmentation of
the embedded code with; 16 Kbytes of HardwareProtected Boot code, 2 Main Blocks of program
code and 2 Parameter Blocks of 8 Kbytes each for
frequently updatable data storage and diagnostic
messages (e.g. phone numbers, authorization
codes). Figure 2 is an example of such an application with the 28F002BX-T.
These are a few actual examples of the wide range
of applications for the 2 Mbit Boot Block flash memory family which enable system designers to achieve
the best possible product design. Only your imagination limits the applicability of such a versatile product
family.

3-149

28F200BX-T/B,28F002BX-T/B

12V
.
82360SL
Controllar

XD7

GPIO
RESET

GPIO
RESET
PWRGOOD

XDIR

-l\.J"*, 1
. _.

--L-.r'"!

I

Vpp
Switch

Vpp

28F200BX-T

5V

80386SL

5V

GPIO

ROMI6/ii

290448-4

Figure 1. 28F200BX Interface to INTEL386SLTM Microprocessor Sup!!rset

"

r-

A,6:17

As-A,s
ALE
AIlo-A~

ADDRESS
LATCHES
LE

~

A

IV-

T"

~

ADDRESS
LATCHES
LE

~

::1J

:-----1

I J~

000 -D~ Ao -A,7

80C188EB '

CE

UCS
1[
Vpp
GENERATOR

P1.X

I

PWD

WR

WE

Rii

OE

RESIN

L

SYSTEM RESET

28FOO2BX-T

Vpp

+-

290448-24

Figure 2. 28F002BX Interface to INTEL 80C188EB 8-Blt Embedded Microprocessor

intel .

28F200BX-T IB, 28F002BX-T IB

1.3 Pinouts
The 28F200BX 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in
Figure 3 with an upgrade to the 28F400BX (4 Mbit
flash family). Furthermore, the 28F200BX 56-Lead
TSOP pinout shown in Figure 4 provides density upgrades to the 28F400BX and to future higher density
boot block memories.

The 28F002BX 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density
upgrade to the 28F004BX 4 Mbit Boot Block flash
memory.

2SF400BX
Vpp
DU
A17
A7
As
As
~
A3
A2
A1
Ao
CE
GND
OE
DQo
DQs
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11

2SF400BX

DOg

0013

DQ2

DQs

DQ3

DQ4

PWD
WE
As
A9
A10
A11
A12
A13
A14
A1S
A1S
BYTE
GND
DQ1S/A-1
DQ7
DQ14
DQs
DQ13
DQs
DQ12
DQ4

DC!, 1

Vee

Vee

PWD

WE
Ne

As

~
A,o
All
A4

A12
A,3

A,

Ao
CE
GND

OE

PA28F200BX
44 LEAD PSOP
0.525" X 1.110"
TOP VIEW

A,4
A,s
A,6

BYTE
GND
Dc!'s/A..l
DIq

DOo

!KIa

DC!, 4

DC!,

DOs

DC!, 2

290448-25

Figure 3. PSOP Lead Configuration for xS/x16 2SF200BX

3-151

intel .

28F200BX-T/B,28F002BX-T/B '

28F400BX

NC
NC
AIS
A14
A13
A12
All

28F400BX

NC
NC

~O

~S

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 .
24
25
26 .
27
28

A14
~3
~2

All

·A1Q

~O

Ag
As
NC
NC
WE
PWD
NC
NC

AS
NC
NC
WE
PWD
NC
NC

Vpp

Vpp

DU
NC
A17
A7

DU
NC
NC
A7

As

As

As

As
A4
A3
A2
AI
NC

As
A4
A3
A2
A1
NC

28F200BX
56-LEAD TSOP
14mm X 20mm
TOP VIEW

56
55
54
53
52
51.
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
A16
BYTE
GND
D0,5/ L l
DC?
DQ14
DOs
00,3
DQS
00,2
DQ4

NC
~
BYTE
GND
DQ1S/A-l
DQ7
DQ14
DQS
DQ13
DQS
DQ12
DQ4

Vee
Vee

Vee
Vee

00,1.
DQ3
DQ10
DQ2
DQg
DQ1
DOs
000
OE
GND
CE

DQll
DQ3
DQ10
DQ2
DQg
DQl
DQs
DQo
OE
GND
CE

Ao

Ao

NC
NC

NC
NC

29044S-.3
Figure 4. TSOP Lead Configuration for x8/x16 28F200BX

28F004BX

A16
AIS
Al4
Al3
A12
Ali
Ag
As

WE

PWD
VPP
'DU
As
A7
A6
As
A4
A3
A2
AI

28FOO4BX

A16
~s
~4

A13
~2

A,1

As
As

WE
PWD
Vpp

DU
NC
A7

As

As
A4
A3
A2
Al

10
2.
3
4
5
6
7
8·
9
10
11
12
13
14
15
16
17
18
19
20

28F002BX
.40- LEAD TSOP
10mm X 20mm
TOP VIEW
'

.

40
39
38
37
36
35
34
33
32
31
30
·'29
28
27
26
25
24
23
22
21

~7
GND
NC
NC
A,o
DC?
DOs
DQs
DQ4
Vee
Vee

NC
DQ!
DQ2
DO,
000
OE
GND
CE .

Ao

A17
GND
NC·
NC ,
AHI
DQ7
DQ6
DQs
DQ4

Vee
Vee

NC
DQ3
DQ2
DQl
.DQo
()E

GND

·ce
Ao
29044S-20

Figure 5. TSOP Lead Configuration for x8 28FOO2BX

\

3-152

intel~

28F200BX-T IB, 28F002BX-T IB

1.4 Pin Descriptions for the x8/x16 28F200BX
Symbol

Type

Name and Function

Ao-A16

I

ADDRESS INPUTS for memory addresses; Addresses are internally latched
during a write cycle,

Ag

I

ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device 10's. When BYTE is at a
logic low only the lower byte of the signatures are read. 0015/ A-1 is a don't care
in the signature mode when BYTE is low.

000-007

I/O

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
durinQErogram command. Inputs commands to the Command User Interface
when CE and WE are active. Data is internally latched during the write and
program cycles. Outputs array, intelligent identifier and.Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.

008- 0015

I/O

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
.during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE = "0"). In
the byte-wide mode 0015/ A -1 becomes the lowest order address for data output
on 000-007'

CE

I

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels. If CE and PWO are high, but not at
a CMOS high level, the standby current will increase due to current flow through
the CE and PWO input stages.

PWO

I

POWER-DOWN: Provides three-state control. Puts the device in deep powerdown mode. Locks the boot block from program/erase.
When PWO is at logic high level and equals 6.5V maximum the boot block is
locked and cannot be programmed or erased.
When PWO
or erased.

=

11.4V minimum the boot block is unlocked and can be programmed

When PWO is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM i*3 reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions.
PWO terminates any internally timed erase or program activities when it is taken to
a logic low. PWD activates the CE input stage and requires 300ns recovery time to
transition from deep power-down to valid data on the outputs or 215 ns delay
before the device can recognize valid inputs.
OE

I

OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE is active low.

WE

I

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
is active low. Addresses and data are latched on the rising edge of the WE pulse.

BYTE

I

BYTE ENABLE: Controls whether the device operates in the byte-wide mode (x8)
or the word~wide mode (x16). BYTE pin must be controlled at CMOS levels to
meet 100 /A-A CMOS current in the standby mode. BYTE = "0" enables the bytewide mode, where data is read and programmed on 000-007 and 0015/A-1
becomes the lowest order address that decodes between the upper and lower
byte. 008-0014 are tri-stated during the byte-wide mode. BYTE = "1" enables
the word-wide mode where data is read and programmed on 000-0015.

Vpp

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.

Vee

DEVICE POWER SUPPLY (5V ± 10%, 5V ± 5%)

GNO

GROUND: For all internal circuitry.

NC

NO CONNECT: Pin may be driven or left floating.

OU

DON'T USE PIN: Pin should not be connected to anything .
. 3-153

intel .

28F200BX-T/B,28F002BX-T/B

1.5 Pin Descriptions for x8 28F002BX
Type

Name and Function

Ao-A17

Symbol

I

ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.

As

I

ADDRESS INPUT: When As is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.

DOo-DO?

I/O

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
command. Inputs commands to the command user interface
when CE and WE are active. Data is internally latched during the write and program
cycles. Outputs array, intelligent identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.
during~rogr'am

CE'

I

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels. If CE and PWD are high, but not at a
CMOS high level, the standby current will increase due to current flow through the
CE and PWD input stages.

PWD

I

POWERDOWN: Provides Three-State control. Puts the device in deep powerdown
mode. Locks the Boot Block from program/erase.
When PWD is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
When PWD = 11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When PWD is at a logic low level the Boot Block is locked, the deep powerdown
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions.
PWD terminates any internally timed erase or program activities when it is taken to
a logic low. PWD activates the CE input stage and requires 300 ns recovery time to
transition from deep powerdown to valid data on the outputs or 215 ns delay before
the device can recognize valid inputs.,

DE

I

OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. DE is active low.

WE

I

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE is
active low. Addresses and data are latched on the rising edge of the WE pulse.

Vpp

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.

Vee

DEVICE POWER SUPPLY (5V ± 10%, 5V ± 5%)

GND

GROUND: For all internal circuitry.

NC

NO CONNECT: Pin may be driven or left floating.

DU

DON'T USE PIN: Pin should not be connected to anything.

3-154

N

•

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::::s

:co €:
8

."
N

g

~~

UJ

><

::e
o:::rJ

."

~

,e
UJ
<
-i

...

G

s»
~
!ill

BYTE

o~

::e
I

_

g
><

~

Co)

m

...

~e:

8l-!

e

m

CE
WE

."

DE

0

PWD

:::rJ

g

G

0

~

-i
0

~

:

0'

~

2
I»
C!!
DI
3

'- •.
...,-..,6

em

Y-GATING/SENSING
><

><

9"9

~m ~CD

iriiffi liiei
><1;; ><1;;

~~

J:. ~

:.""

:.""

Vpp

~~
...

g

5at

IZ

:;c
'"

w~

!;:g

~

~

0

0

m

><

~
.....

m
N
CO
"'1'1

g
N

~

•.
~

m

~

~

l§!
~

-I

~

."

~at

~

~

~;(

0

-

&::\

-'"

Z

ffiiil

I",

~iJ

~

"iiiI

290448-1 I

@
aID
~

~

C::lJ
=
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::2

intel"

28F2008X-T /8, .28F0028X-T /8

2.1 28F200BX Memory Organization

2.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F200BX
(1 x 128 Kbyte block and 1 x 96 Kbyte block). See/
the following section on Block Memory Map for the
address location of these blocks for the 28F200BX-T
and 28F200BX-B products.

2.1.1 BLOCKING
The 28F200BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F200BX is
a random read/write memory, only erasure is performed by block.

2.1.2 BLOCK MEMORY MAP
Two versions of the 28F200BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F200BX-T
memory map is inverted from the 28F200BX-B
memory map.

2.1.1.1 Boot Block Operation and Data
Protection
The 16. Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when PWD is not at 12V. The boot block .can
be erased and written when PWD is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block for the 28F200BX-T and
28F200BX-B.

2.1.2.1 28F200BX-B Memory Map
The 28F200BX-B device has the 16. Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F200BX-B the first 8 Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8 Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96 Kbyte main block resides in memory space from
04000H to OFFFFH. The 128 Kbyte main block resides in memory space from 10000H to 1FFFFH
(word locations). See Figure 7.
(Word Addresses)

2.1.1.2 Parameter Block Operation
The 28F200BX has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not· have the hardware write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when deal- .
ing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
28F200BX-T and 28F200BX-B.

1FFFFH

128 Kbyte MAIN BLOCK
10000H
OFFFFH

96 Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK
OOOOOH

Figure 7. 28F200BX-B Memory Map

3-156

28F200BX-T/B,28F002BX-T/B

2.1.2.2 28F200BX-T Memory Map
The 28F200BX·T device has the 16 Kbyte boot
block located from 1EOOOH to 1FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the 28F200BX-T the first
8 Kbyte parameter block resides in memory space
from 1DOOOH to 1DFFFH. The second 8 Kbyte parameter block resides· in memory space from
1COOOH to 1CFFFH. The 96 Kbyte main block resides in memory space from 10000H to 1BFFFH.
The 128 Kbyte main block resides in memory space
from OOOOOH to OFFFFH as shown in Figure 8.

(Word Addresses)

1FFFFH
16 Kbyte BOOT BLOCK

1EOOOH
1DFFFH
1DOOOH
1CFFFH
1COOOH
1BFFFH

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

96 Kbyte MAIN BLOCK

10000H
OFFFFH
128 Kbyte MAIN BLOCK

OOOOOH

Figure 8.

3-157

28F2qOBX-T Memory Map

28F200BX-T/B,28F002BX-T/B

3.0 28F002BX BYTE-WIDE PRODUCTS DESCRIPTION

I~ I~ It'S I~

>'5:.

~0018 NIV~
]!A8~-Sll

'"z
~

~

~0018 NIV~
]!A8~-96

!;l

~ ~------------~
l'
~0018 ~]ll~V~Vd
>]lA8~-S

~0018 ~]l]~V~Vd
]lA8~-S

Figure 9. 28F002BX Byte-Wide Block Diagram

3-158

int'eL

28F200BX-T/B,28FQ02BX-T/B

3.1 . 28F002BX Memory Organization.

3.1.1.3 Main Block Operation

3.1.1 BLOCKING

The 28F002BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F002BX is
a random read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection

The .16 Kbyte bQot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when PWD is not at 12V. The boot block
can be erased and programmed when PWD is held
at 12V for the duration of the erase or program operation. This allows customers to change the boot
code when necessary w~ile still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F002BX-T and 28F002BX-B.

Two main blocks of memory exist on the 28F002BX
(1 x 128 Kbyte block and 1 x 96 Kbyte block). See
the following section on Block Memory Map for
address location of these blocks for the
28F002BX-T and 28F002BX-B ..
3.1.2 BLOCK MEMORY MAP

Two versions of the 28F002BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F002BX-T
memory map is inverted from the 28F002BX-B
memory map.
3.1.2.1 28F002BX-B Memory Map

The 28F002BX-B device has the 16 Kbyte boot
block located from OOOOOH ,to 03FFFH. to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F002BX-B the first 8 Kbyte parameter block resides in memory from 04000H to 05FFFH. The second 8 Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96 Kbyte main
block resides in memory space from 08000H to
1FFFFH. The 128 Kbyte main block resides in memory space from 20000H to 3FFFFH. See Figure 10.

, 3FFFFH

3.1.1.2 Parameter Block Operation

The 28F002BX has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provtde
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F002BX-T and 28F002BX-B.

128 Kbyte MAIN BLOCK
20000H
1FFFFH
96 Kbyte MAIN BLOCK
08000H
07FFFH
8 Kbyte PARAMETER BLOCK
06000H
05FFFH
04000H
03FFFH

8 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK

OOOOOH

Figure 10_ 28F002BX-B Memory Map

3-159

intel"

28F200BX·T IB, 28F002BX·T IB

family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.

3.1.2.2 28F002BX·T Memory Map

The 28F002BX-T device has the 16 Kbyte boot
block located from 3COOOH to 3FFFFH to accommodate those microprocessors that boot from the
top of the address map. In the 28F002BX-T the first
8 Kbyte parmeter block resides in memory space
from 3AOOOH to 3BFFFH. The second 8 Kbyte parameter block resides in memory space from
38000H to 39FFFH. The 96 Kbyte main block resides in memory space from 20000H to 37FFFH.
The 128 Kbyte main block resides in memory space
from OOOOOH to 1FFFFH.

The CUI allows for 100% TTL-level control inputs,
fixed power supplies during erasure .and programming, and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin; the
2 Mbit boot block flash family will only successfully
execute the following commands: Read Array, Read
Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or
through the standard EPROM A9 high voltage acGess (VIO) for PROM programming equipment.

3FFFFH
16 Kbyte BOOT BLOCK
3COOOH
3BFFFH
3AOOOH
39FFFH
38000H

37FFFH

The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

,
96 Kbyte MAIN BLOCK

20000H

1FFFFH

The purpose of the Write State Machine (WSM) is to
complEitely automate the write· and. erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE interface to the data and address latches, as
. well as system software requests for status while the
WSM is in operation.

128 Kbyte MAIN BLOCK
OOOOOH

Figure 11. 28F002BX·T Memory Map

4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
'

4.1 28F200BX Bus Operations

Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 2 Mbit·flash

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.

3-160

intel·

28F~OOBX-T/B,

28F002BX-T/B

Table 1. Bus Operations for WORD-WIDE Mode (BYTE = VIH)
Notes

PWD

CE

OE

WE

Ag

Ao

Vpp

1,2,3

VIH

VIL

VIL

VIH

X

X

X

DOUT

Output Disable

VIH

VIL

VIH

VIH

X

X

X

HighZ

Standby

VIH

VIH

X

X

X

X

X

HighZ

Mode
. Read

DQO-15

Deep Power-Down

9

VIL

X

X

X

X

X

X

HighZ

Intelligent Identifier (Mfr)

4

VIH

VIL

VIL

VIH

VIO

VIL

X

0089H

4,5

VIH

VIL

VIL

VIH

VIO

VIH

X

2274H
2275H

6,7,8

VIH

VIL

VIH

VIL

X

X

X

DIN

Intelligent Identifier (Device)
. Write

Table 2. Bus Operations for BYTE-WIDE Mode (BYTE = VIL)
Mode
Read

Notes

PWD

CE

OE

WE

Ag

Ao

A-1

Vpp

DQO-7

DQ8-14

1,2,3

VIH

VIL

VIL

VIH

X

X

X

DOUT

HighZ

X

X

X

HighZ·

HighZ

Output Disable

, VIH

VIL

VIH

VIH

X
·X

VIH

VIH

X

X

X

X

X

X

HighZ

HighZ

Deep Power-Down

9

VIL

X

X

X

X

X

X

HighZ.

Intelligent Identifier (Mfr)

4

VIH

VIL

VIL

VIH

VIO

VIL

X

X· HighZ
X 89H

4,5

VIH

VIL

VIL

NIH

VIO ·VIH

X

X

74H
75H

HighZ

6,7,8

VIH

VIL

VIH

VIL

X

X

DIN

HighZ

Standby

Intelligent Identifier:
(Device)
Write

X

X

NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See OC characteristics for VPPL, VPPH, WtH, VtO voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1";A17 = X.
5. Device 10. = 2274H for 2BF200BX-T and 2275H for 2BF200BX-B ..
6. Refer to Table 4 for valid DIN during a write operation.
,
7. Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VPPH.
8. To write or erase the boot block, hold PWD at VHH.
9. PWO must be at GND ±O.2V,to meet the 1.2 p.A maximum deep power-down current.

i

3-161

HighZ.

28F200BX-T

IB; 28F002BX-T IB

4.2 28F002BX Bus Operations
Table 3. Bus Operations

Mode'
Read

Notes

PWD

CE

OE

WE

Ag

Ao,

Vpp

1,2,3

VIH

VIL

VIL

VIH

X

X

X

DOUT

VIH

VIIi

X

X

X

HighZ

X

X

X

X

X'

HighZ

X

X

X

X

X

HighZ.

VIL

VIH

VID

VIL

X

89H

VID

VIH

X

7CH
7DH

X

X

X

Output Disable

VIH

VIL,

Standby

VIH

VIL

VIH
(X

VIH

,vIL

Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device) :
Write

9
4
4,5
6,7,8

,

:

VIH

VIL

VIL

VIH

'VIH,

VIL

VIH:

VIL

"

DQO-7

"

Dil"';

NOTES:
1. Flefer to DC Characteristics.
' '
,,2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC chara~teristics for VPPL, VPPH, VHH, Vio voltages.
"
4. Manufacturer and Device codes may also be, accessed via a CUI write sequence.A1~A16 =' X.
5. Device 10= 7CH for 28F002BX-T and 7DH for 28F002BX-B.
"
~. Refer toTable 4 for valid DIN during a write operation.
' '
,
7., Command writes for Block Erase or bytE! program are only executed when Vpp = VPPH.
8. Program or erase the Boot block by holding PWD at VHH.
',.
"
9. PWD must b~ a~ GND ±O.2~ to Illeet the 1.2 /LA maximum deep power-~owncurrent.

. 4.3 Read Operations
The 2 Mbit boot block flash family ha~ three user ,
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be dis-'
cussed in detail, in the "Write Ope~ations" section.,

po~er-up

SU~PIY

During
conditions (VCC
ramping),it
takes a maximum of 600 ns from when Vce is at
4.5V minimum to valid data on the outputs.
.

(00[0:15] ,or 00[0:7]) are ti"i-stated. Data input is
then controlled by WE.

4.3.1.2 Input Control
With WE at logic-high level (VIH), input to the device
is disabled; Data IriputlO~t pins (00-[0:15] or
.00[0:7]) are contrql,ledby OE '

..

'

4.3;2, ,INTELLIGENT, IDENTIFIERS
4.3.1 READ ARRAY

28F200BX Products
If the\ memory is riot in.the Read Array m~de, it i~ :
The manufacturer and device codes are read via the
necessary to write the appropriate read mode com. CUI or by taking the 1\9 pin to 12V. Writing 90H to'
mand to the CUI. The 2, Mbitbootblock fla!?h family
,the CUI places the device into Intelligent Identifier
has three,control functions, all of which must be logiread mode. A read of location OOOOOH outputs the,
cally active, to obtain data at the outputs. Chip-Enmanufacturer's identification code, 0089H, and loca"
able CE is the device selection control. Power-Down
tion 00001Houtputs the device code; 2274H for,
PWD is the device power control. Output-Enable OE
28F200BX-T, 2275H for 28F200BX-B. When BYTE
is the DATA INPUT/OUTPUT (00[0:15] or 00[0:7])
is at a logic low only the lower bYte of the above
direction control and when active is used to drive
signatures is read and 0015/A-1 is Ii "don't care"
data from the selected memory on to the 110 bus.
during Intelligent Identifier mode. A read array command must be, written to, the CUI to return to the
4.3.1.1 Output Control
read array mode.
With OE at logic-high level (VIH), the output from the
device, is disabled and datainputloutput pins

intel .

28F200BX-T IB, 28F002BX-T IB

28F002BX Products

4.4.1 BOOT BLOCK WRITE OPERATIONS

The manufacturer and device codes are also read
via the CUI or by taking the AS pin to 12V. Writing
SOH to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH outputs the manufacturer's identification code, 8SH,
and location 00001 H outputs the device code; 7CH
for 28F002BX-T, 7DH for 28F002BX-B.

In the case of Boot Block modifications (write and
erase), PWD is set to VHH = 12V typically, in addition to Vpp at high voltage. However, if PWD is not at
VHH when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, .refer to
Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.

4.4 Write Operations

4.4.2 COMMAND USER INTERFACE (CUI)

Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
intelligent identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and -the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Maohine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to "hard-wire" Vpp to 12V. The 2 Mbit boot block
flash family is designed to accommodate either design practice. It is recommended that PWD be tied to
logical Reset for data protection during unstable
CPU reset function as described in the "Product
Family Overview"section.

The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which'will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
'
current state.
4.4.2.1 Command Set
Command
Codes

Device Mode

00
10
20
40
50
70
SO
BO
DO
FF

Invalid/R.eserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array

4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 2 Mblt
boot block flash family commands.

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intaL

28F200BX-T IB, 28F002BX-T IB

Table 4. Command Definitions
Command

Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data

Read Array/Reset

1

1

Write

X

FFH

Intelligent Identifier

3

2,4

Write

X

90H

Read

IA

110

3

Write

X

70H

Read

X

SRD

Write

X

50H

Read Status Register

2

Clear Status Register

1

Erase Setup/Erase Confirm

2

5

Write

BA

20H

Write

BA

DOH

Word/Byte Write Setup/Write

2

6, 7

Write

WA

40H

. Write

WA

WD

Erase Suspend/Erase Resume

2

Write

X

BOH

Write

X

DOH

Alternate Word/Byte Write Setup/Write

2

6, 7

Write

WA

10H

Write

WA

WD

NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. 110 = Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
6. PA = Address to be programmed.
PO = Data to be programmed at location PA.
1. Either 40H or 10H command is valid.
8. When writing commands to the device, the upper data bus [008-0015] = X (28F200BX-only) which is either Vee or
Vss to avoid burning additional current.

Invalid/Reserved

Read Status Register (70H)

These are unassigned commands. It is not recommended that the customer use any·commandother
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.

This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.

Read Array (FFH)

The device automatically enters this mode after program or erase has completed.

This single write command points the read path at
the array. If the host CPU performs a CE/OE controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Head Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
Inteligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address AO is used in this mode, all
other address inputs are ignored).

Clear Status Register (50 H)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
,more efficient to query the· status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.

3-164

intet

28F200BX-T/B,28F002BX-T/B

Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin .execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the ProgramStatus and Erase Status bits of the
Status Register to a "1 ", place the device into the
Read Array state, and wait for another command.
. Erase Confirm (DOH)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status· Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE is toggled low. Status Register data can
only be updated by toggling either OE or CE low.
. Erase Suspend (BOH)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will set
an output that directs the WSM to suspend Erase
operations, and then return to responding to only
Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend .
state, it will set an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CUI will not respond to any other commands. The wsM will also set the WSM Status bit to
a "1". The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input

control pins, with the exclusion of PWD. PWD will
immediately shut down the WSM and the remainder
of the chip. During a suspend operation, the data
and address latches will remain closed, but the address pads are able to drive the address into the
read path.
Erase Resume (DOH)
This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effe9t in all
other conditions.
4_4.3 STATUS REGISTER
The 2 Mbit boot block flash family contains a status
register which may be read to determine when a program or erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing this command, all subsequent Read operations output data
from the status register until another command is
. written to the CUI. A Read Array command must be
written to the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode for the 28F200BX. In the word-wide
mode the upper byte, 00[8:15] is set to OOH during
a Read Status command. In the byte-wide mode,
00[8:14] are tri-stated and 0015/ A -1 retains the
low order address function.
It should be noted that the contents of ttie status
register are latched on the falling edge of OE or CE
whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE or OE must be toggled with
each subsequent status read, or the completion of a
program or erase operation will -not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation: The WSM sets
status bits "Three" through "Seven". and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five". These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.

3-165

intel..

28F200BX-T/B,28F002BX-T/B

4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions

I

WSMS lESS

7

6

ES

PS

5

4

R

3

2

R

o

NOTES:

Write State Machine Status bit must first be checked to '
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.

SR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
SR.6 = ERASE SUSPEND STATUS
1 -= Erase Suspended
o = Erase in Progress/Completed

When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command.is issued.

SR.S = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase

When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify. .

SR.4 = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program

When this bit is set to "1", WSM has attempted but failed
to Program a byte or word.

SR.3= Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= VppOK

The Vpp Status bit, unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM interrogates the Vpp level only after the byte write or block
erase command sequences have been entered and informs the system if Vpp has not been switched on. The
Vpp Status bit is not guaranteed to report accurate feedback between VPPL and VPPH.

SR.2-SR.0
MENTS

RESERVED FOR FUTURE ENHANCE-

These bits are reserved for future use and should be
masked out when polling the Status Register.

4.4.3.2 Clearing the Status Register

4.4.4 PROGRAM MODE

Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various faiiure conditions. By aliowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in, sequence). The status register may then be read to
determine if an error occurred during that programming or erasUre series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.

Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state ma~
chine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memory word (byte), and _
2. Verify that the desired bits are sufficiently programmed
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1 "s, there will be no
change of the memory cell content and no error bc- curs.
Simiiar to erasure, the status register indicates
whether programming is complete. Whiie the pro- '
gram sequence is executing, bit 7 of the status register is a "0". The status register can be polled by

3-166

inteL

28F200BX-T/B, 28F002BX-T/B·
\

toggling either CE or OE to' determine when the program sequence is complete. Only the Read Status
Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status regis-'
ter is set to a "1" to indicate a Program Failure. If Bit
3 is set then Vpp was not within acceptable limits,
and the WS~ will not execute the programming sequence.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is. completed; however, it
must be recognized that reads from the memory,
stll-tus register, or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read ..

a

Figur~12 shows system software flowchart for device byte programming operation. Figure 13 shows a
,similar flowchart for device word programming operation··(28F200BX-only).

4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A[12:16] for the
28F200BX or A[12:17] for the 2~F002BX, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is is- .
sued. Block erasure results in all bits within the block
being set to "1".
. The WSM will execute a sequence of internally
timed events to:
'
1. Program all bits within the block
2. Verify that all bits within the block are sufficiently
programmed.
3. Erase all bits within the block and
4. VeritY that all bits within, the block are sufficiently
erased
.
While the erase sequence is executing, Bit 7 of the
status register is a "0".
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
,after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a "1" to indicate

an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before at- ,
tempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase

Since an erase operation typically requires 1 to 3
seconds to complete, an. Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequencEl is started,.writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se- I
quence at a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which,is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detailing the operation.
.
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE to ViH and the
active current is now a maximum of 10 mA. If the
chip is enabled while in this mode by taking CE to
VIL, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other than
the block being erased, tne Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase'sequence and complete erasing the block. As
with the end of 'erase, the status register must be
read, cleared, and the next instruction issued in order to continue.
4.4.6' EXTENDED CYCLING

Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 2 Mbit
boot block flash .family is designed for 100,000 pro- '
gram/erase cycles on each of the five blocks. The
combination of low electric fields, clean oxide processing and minimized oxide area per memory cell'
subjected to the tunneling electric field, results in
very high cycling capability.

3-167

infel"

28F200BX"T/B,28F002BX~T/B

; Bus
Operation

Command

Comments

Write

Setup
Program

Data =40H
Address =' Byte to be
'programmed ,

Write

Program

Data to be programmed
Address = Byte to be
programmed

Read

Status Register Data.
Toggle DE or CE to update
Status Register

Standby

CheckSR.7
1 = Ready, 0 = Busy

Repeat for subsequent bytes.
Full 'status check can be done, after each byte or after a
~equence of bytes.

Write FFHafter the last byte programming operation to
reset the device to Read Array Mode.

290448-6

Full Status Check Procedure

Bus
Operation
Vpp Range

Error

Byt. Program
Error

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

CheckSRA
1 =' Byte Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
SFlA is only cleared by the Clea.r Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.

290448-7

If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 12. Automated Byte Programming Flowchart

3-168

intel~

28F200BX-T IB, 28F002BX-T IB

Bus
Operation

Command

Comments

Write

Setup
Program

Data = 40H
Address = Word to be
programmed

Write

Program

Data to be programmed
Address = Word to be
programmed

Read

Status Register Data.
Toggle DE or CE to update
Status Register

Standby

Check SR.7
1 = Ready, 0 "= Busy

Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.

Write FFH after the last word programming operation to
reset the device to Read Array Mode.

290448-8

Full Status Check Procedure

Bus'
Operation
Vpp Range

Error

Byte Program
Error

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

Check SRA
1 = Word Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290448-9

SRA is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
~ attempting retry or other error recovery.

Figure 13. Automated Word Programming Flowchart

3-169

int:et

28F200BX.T IB, 28F002BX·T IB

Bus
Operation

Comments

Command

Write

Setup'
Erase

Data = 20H
Address = Within block to be
erased

Write

Erase

Data = DOH
Address ~ Within block to be
erased

Read

Status Register Data.
Toggle OE or CE to update
Status Register

Standby

Check SR.?
1 := R·eady, 0 = Busy

Repeat for subsequent blocks.
Full status check can be done aftE1r each block or after a
sequence of blocks.

Write FFH after the last block erase operation to reset the
device to Read Array Mode.

290448-10

Full Status Check Procedure
Bus
Operation

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

Check SRA,5
Both 1 = Command Sequence
Error

Standby

CheckSR.5
1 = Block Erase Error

SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
,290448-11
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is ·checked.
If error is detected, dear the Status Register before
, attempting retry or other error recovery.

Figure 14,Automated Block Erase Flowchart

3-170

inteL

28F200BX-T IB, 28F002BX-T IB

Bus
Operation

Write

Comments

Command.

Erase
Suspend

Data

= BOH

Read

Status Register Data.
Toggle OE or CE to update
Status Register

Standby

Check SR.7
1 = Ready

Standby

CheckSR.6
1 = Suspended

Write

Read Array

Read

Write

Data

= FFH

Read array data from block
other than that being
erased.

Erase Resume

Data

= DOH

290448-12

Figure 15. Erase Suspend/Resume Flowchart
maximum ICC current is 3 mA and typical Icc current
is 1 mA. The device stays in this static state with
outputs valid until a new location is read.

4.5 Power Consumption .
4.5.1 ACTIVE POWER
With CE at a logic-low level and PWO at a logic-high
level, the device is placed in the active mode. The
device Icc current is a maximum of 6Q mA at
10 MHz with TTL input signals.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power feature during active mode of operation. The 2 Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device's power consumption by entering the APS mode where

4.5.3 STANDBY POWER
With CE at a logic-high level (VIH), and the CUI in
read.mode, the memory is placed in standby mode
where the maximum ICC standby current is 100 p.,A
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(00[0:15] or 00[0:7]) are placed in a high-impedance state independent of the status of the OE sig.
nal. When the 2 Mbit boot block .flash family is deselected during' erase or program functions, the devices will continue to perform the erase or program
function and consume program or erase active power until program or erase is completed.

3-171

in1:et

28F200BX-T/B,28F002BX-T/B

4.S.4DEEP POWER-DOWN

The 2 Mbit boot block flash family supports a typical
lee of 0.2 IJ-A in deep power-down mode. One of the
target markets for these devices is in portable equipment where the power consumption of the machine
is of prime importance. The 2 Mbit boot block flash
family has a PWD pin which places the device in the
deep power-down mode. When PWD is at a logic-'
low (GND ±0.2V), all circuits are turned off and the
device typically draws 0.2 IJ-A of Vee current.
During read modes, the PWD pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a minimum of400 nsto access valid data (tpHQV)'

VIH, regardless of the state of its control inputs. This
feature provides yet another level of memory protection.

4.7 Power Supply Decoupling
Flash memory's power switching characteristics re~
quire careful device decoupling methods. System
designers are interested in 3 supply current issues:
.. Standby current levels (Ices)
.. Active current levels (leeR)
... Transient peaks produced by falling and riSing
, edges of CEo
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 IJ-Fceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.

During erase or program modes, PWD low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the PWD function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2 IJ-A current level.
. PWD transitions to VIL or turning power off to the.
device will clear the status register.

4.6 Power-Up Operation

4.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS

Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
designer. The Vpp pin supplies the flash memory
cell's current for programming and erasing. One
should use similar trace widths and layout considerations given to the Vee power supply trace. Adequate Vpp supply traces and decoupling will de. crease spikes and overshoots.

The 2 Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions. Upon power~
up the 2 Mbit boot block flash family is indifferent as
to which power supply, Vpp or Vee, powers-up first.
Power suppy sequencing is not required.
The 2 Mbit boot block flash family ensures the CUI is
reset to the read"mode on power-up.

4.7.2 Vee. Vpp AND PWD TRANSITIONS

In addition, on power-up the user must either drop
CE low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
active. Since both WE and GE must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally, the device is disabled until PWD is brought to

The CUI latches commands as issued by system
software and is not altered by Vpp.or CE transitions
or WSM actions. Its state upon power-up, after exit
from deep power-down mode or after Vee tran" sitions beloW VLKO (Lockout voltage), is Read Array
mode.
'
'
After any word/byte write or block erase operation is
complete and even after Vpp transitions down to
VpPL, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.

3-172

intel"

28F2008X-T18, 28F0028X-T 18

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are sullject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.

Commercial Operating Temperature
During Read .................... O°C to 70°C(1)
During Block Erase
and Word/Byte Write ............... O°C to 70°C
Temperature Under Bias....... -10°C to + 80°C

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Extended Operating Temperature
During Read ................. - 40°C to + 85°C
During Block Erase
and Word/Byte Write ......... - 40°C to + 85°C
Temperature Under Bias .... " . -40°C to + 85°C
Storage Temperature .......... -65°C to + 125°C
Voltage on Any Pin
(except Vee and Vpp)
with Respect to GND ........ -2.0V to +7.0V(2)
Voltage on Pin PWD or Pin Ag
with Respect to GND ..... :.... 2.0V to + 13.5V(2, 3)
Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND ........ - 2.0V to + 7.0V(2)
Output Short Circuit Current.. ........... 100 mA(4)
NOTES:

1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns.
Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V for
periods < 20 ns.
'
3. Maximum De voltage on Ag or Vpp may overshoot to 6 + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. 10%. Vee specifications reference the 28F200BX-60/28F002BX-60 in their standard test configuration, and the
28F200BX-80/28F002BX-80.
6. 5% Vee specifications reference the 28F200BX-60/28F002BX-60 in their high speed test configuration.

OPERATING CONDITIONS
Symbol

Parameter

Notes

Min

Max

Units

0

70

°C

TA

Operating Temperature

Vee

Vee Supply Voltage (10%)

5

4.50

5.50

V

Vee

Vee Supply Voltage (5%)

6

4.75

5.25

V

DC CHARACTERISTICS
Unit

Input Load Current

1

±1.0

!LA

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

!LA

Vee = Vee Max
VOUT = Vee or GND

Parameter

Notes

Min

Test Condi~ion

Max

III

Symbol

3-173

Typ

intel.,

28F200BX-T/B,28F002BX-T/B

DC CHARACTERISTICS (Continued)
Symbol
Ices

Parameter
Vee Standby Current

IceD

Vee Deep Power-Down Current

leeR

Vee Read Current
for 28F200BX Word-Wide
Mode

leeR·

Vee Read Current for
28F200BX Byte-Wide Mode
and 28F004BX

Notes Min Typ
1,3

1

0.20

1,5,
6

1,5,
6

Max

Unit

Test Condition

1.5

rnA Vee = Vee Max
CE = PWD = VIH

100

p,A Vee = Vee Max
CE = PWD = Vee ±0.2V
28F200BX:
BYTE = Vee ±0.2Vor GND

P

p,A PWD = GND ± 0.2V

60

rnA Vee = Vee Max, CE = GND
f = 10 MHz,lOUT = 0 rnA
CMOS Inputs

65

rnA Vee = Vee Max, CE = VIL
f= 10 MHz, lOUT = 0 rnA
TTL Inputs

55

rnA Vee = Vee Max, CE = GIIJD
f = 10 MHz, lOUT = 0 rnA
CMOS Inputs

60

rnA Vee = Vee Max, CE = VIL
f =10 MHz,lOUT = 0 rnA
TTL Inputs

70

rnA Word Write in Progress

Icew

Vee Word Write Current

1

leew

Vee Byte Write Current

1

60

rnA Byte Write in Progress

IeeE

Vee Block Erase Current

1

30

rnA Block Erase in Progress

leeES

Vee Erase Suspend Current

10

rnA Block Erase Suspended,
CE = VIH

1,2

5

Ipps

Vpp Standby Currerit

1

±10

p,A Vpp";: Vee

IpPD

Vpp Deep Power-Down Current

1

5.0

p,A PWD = GND ± 0.2V

'pPR

Vpp Read Current

1

200

p,A Vpp> Vee

Ippw

Vpp Word Write Current

1

40

rnA Vpp = VPPH
Word Write in Progress

Ippw

Vpp Byte Write Current

1

30

rnA Vpp = VPPH
Byte Write in Progress

IpPE

Vpp Block Erase Current

1

30

rnA Vpp = VPPH
Block Erase in Progress

IpPES

Vpp Erase Suspend Current

1

200

p,A Vpp = VPPH
Block Erase Suspended

110

Aglntelligent Identifier Current

1

500

p,A Ag = VID

VID

Ag Intelligent Identifier Voltage

11.5

13.0

V

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vee +0.5

V

VOL

Output Low Voltage

0.45

V

3-174

Vee = Vee Min
IOL =S.8rnA

intel..

28F200BX-T IB, 28F002BX-T IB

DC CHARACTERISTICS
Symbol

(Continued)

Parameter

VOH

Output High Voltage

Notes

Min

Typ

Max

2.4

Unit
V

VpPL

Vpp during Normal Operations .

3

0.0

6.5

V

VpPH

Vpp during Erase/Write Operations

7

11.4

12.0

12.6

V

VPPH

Vppduring Erase/Write Operations

8

10.8

12.0

13.2

VLKO

Vee .Erase/Write Lock Voltage

2.0

VHH

PWD Unlock Voltage

11.5

Test Condition
Vee = Vee Min
IOH = -2.5mA

V
V

13.0

V

Boot Block Write/Eras'e

. EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol

Parameter

TA

Operating Temperature

Vee

Vee Supply Voltage (10%)

Notes

5

Min

Max

Units

-40

+85

'C

4.50

5.50

V

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

III

Input Load,Current

1

±1.0

/LA

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

/LA

Vee = Vee Max
VOUT = VeeorGND

lees

Vee Standby Current

1,3

1.5

mA

Vee = Vee Max
CE =·PWD = VIH

100

/LA

Vee = Vee Max
CE = PWD = Vee ±0.2V
28F200BX:
BYTE = Vee ± 0.2V or GND

B

/LA

PWD = GND ±0.2V

70

mA

Vee = Vee Max, CE = GND
f = 10MHz, lOUT = 0 mA
CMOS Inputs

75

mA

Vee = Vee Max, CE = VIL
f = 10 MHz, lOUT = 0 mA
TTL Inputs

65

mA

Vee = Vee Max, CE = GND
f = 10 MHz, lOUT = 0 mA
CMOS Inputs

70

mA

Vee = Vee Max, CE = VIL
f = 10 MHz, lOUT = 0 mA .
TTL Inputs

,
IceD

Vec Deep Power-Down Current

leCR

Vee Read Current
for 28F200BX Word-Wide
Mode

leeR

Vee Read Current for
2BF200BX Byte-Wide Mode
and 2Bj=004BX

1

0.20

1,5,
6

1,5,
6

3-175

intel .

28F200BX-T IB, 28F002BX-T IB

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol

Parameter

Notes

Min

Typ

Max

Unit

(Continued)

Test Condition

Ipps

Vpp Standby Current

1

±10

/LA Vpp:S; Vee

IpPD

Vpp Deep Power-Down Current .

1

5.0

/LA

PWD.=·GND ±0.2V

IpPR

Vpp Read Current

1

200

/LA

Vpp> Vee

Ippw

Vpp Word Write Current

1

40

mA Vpp = VPPH
Word Write in Progress

Ippw

Vpp Byte Write Current

1

30

mA Vpp = VPPH
Byte Write in Progress

IpPE

Vpp Block Erase Current

1

30

mA Vpp = VPPH
Block Erase in Progress

IpPES

Vpp Erase Suspend Current

1

200

/LA Vpp = VpPH
Block Erase Suspended

110

As Intelligent Identifier Current

1

500

/LA As = VIO

VIO'

As Intelligent Identifier Voltage

11.5

13.0

V

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

VOL

Output LowVoltage

VOH

Output High Voltage

VPPL

Vpp during Normal Operations

VPPH
VPPH
VLKO

Vee Erase/Write Lock Voltage

2.0

VHH

PWD Unlock Voltage

11.5

Vee
'.

+ 0.5

0.45

2.4

V
V

Vee = Vee Min
IOL = 5.8mA

V

Vee = Vee Min
IOH = -2.5 mA

3

0.0

6.5

V

Vpp during Erase/Write Operations

7

11.4 12.0

12.6

V

Vpp during Erl:i,se/Write Operations

8

10.8 12.0

13.2

V

13.0

V

3-176

-

V
Boot Block Write/Erase

28F200BX-T IB~ 28F002BX-T IB

CAPACITANCE(4,9)
Symbol

TA

= 25°C, f = 1 MHz
Typ

Max

Unit

CIN

Input Capacitance

Parameter

6

8

pF

Condition

VIN

COUT

Output Capacitance

10

12

pF

VOUT

= OV
= OV

NOTES:
1. All currents are in RMSunless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).
2. leeES is specified with the device deselected; If the device is read while in Erase Suspend Mode, current draw is the sum
of leeEs arid leeR.
3.Block Erases and Word/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and
VPPL·
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces leeR to less than 1 mA typical in static operation.
6, CMOS Inputs are either Vee ±0.2V or GND ±0.2V.ITL Inputs are either VIL or VIH.
7. Vpp = 12.0V ± 5% for applications requiring 100,000 block erase cycles.
B. Vpp = 12.0V ± 10% for applications requiring wider Vpp tolerances at 100 block erase cycles.
9. For the 2BF002BX, address pinAlO follows the COUT capacitance numbers.

STANDARD TEST CONFIGURATION(1)
STANDARD A.C. INPUT/OUTPUT REFERENCE WAVEFORM,

STANDARD A.C. TESTING
LOAD CIRCUIT

2.4 - - _ ~2"::"0---H"--- ~2."::"0--OUTPUT
INPUT
.
TEST POINTS
0.45 _ _ _.I ",0:;;;.8_ _ _
_ _.1 "'0:;;;.8_ _ _ __

>

~~

<

- r1.3V

~ ~ IN914

290448-14

A.C.test inputs are driven at VOH (2.4 VTTU for a Logic "1" and VOL
(0.45 VTTU for a logic "0". Input timing begins at VIH (2.0 VTTU and VIL
(O.B VTTU. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) < 10 ns.

Rt.
DEVICE
UNDER
TEST

1'1.

OUT

290448-13

CL = 100pF
CL Includes Jig Capacitance
RL = 3.3KU

HIGH SPEED TEST CONFIGURATION(2)
HIGH SPEED A.C. INPUT/OUTPUT REFERENCE WAVEFORM

::: --I-NP-UT""X' •5 -

TEST:~INTS-

XI.S

',HIGH SPEED A.C. TESTING
LOAD CIRCUIT
1.3V

OUTPUT

IN914

290448-22

A.C. test inputs are driven at 3.0V for a Logic "1" and O.OV for a logic "0".
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
(10% to 90%) < 10 ns.
NOTES:
1. Testing characteristics for 2BF200BX·60/2BF002BX·60 in standard test config·
uration and 2BF200BX·BO/2BF002BX·BO.
2. Testing characteristics for 2BF200BX·60/2BF002BX·6Q in high speed test can·
figuration.

DEVICE
UNDER
TEST

1--+---0 OUT

290448-21
CL~30pF

CL Includes Jig Capacitance
RL = 3.3 KU

inteL

28F200BX-T IB, 28F002BX-T IB

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol

Parameter

Min

Notes

Iccw

Vcc Word Write Current

Iccw

Vcc Byte Write Current

ICCE

Vcc Block Erase Current

ICCES

Vcc Erase Suspend Current

1
1
1
1,2

Typ

Max

Unit
mA

Word Write in Progress

mA

ByteWrite in Progress

mA

Block Erase in Progress

5

75
65
40
10

Test Condition

mA

Block Erase Suspended,
CE =VIH

AC CHARACTERISTIC~Read Only 'Operations(1)
Vee ±5%
Versions
Symbol
tAVAV tRC

Parameter

28F200BX-60(4)
28F002BX-60(4)
Notes

'Max

Min

CE to Output Delay

OE to Output Delay

tELOX tLZ'

CE to Output Low Z

'.

tEHQZ tHz

CE High to Output
HighZ

tGLOX tOLZ OEto Output Low Z
tGHOZ tOF ' OE High to Output
HighZ
tOH

. tELFL
tELFH

2
3
3
3
3

±

10%
28F200BX-8()(5)
28F002BX-80(5)

Max

Min

70

2

tpHOV tPWH PWD High to
Output Delay
tGLQV tOE

Min

60,

Read Cycle Time

tAVOV tACC Address to
Output Delay
tELOV tCE

Vee
. 28F200BX-60(5)
28F002BX-60(5)

Unit

Max

80

ns

60

70

80

ns

60
300

70
300

80
300

ns

40

ns

30

35

0

0
,20

0

0

0

0
25

20

ns

30

25

ns

ns
ns

30

ns

,

3

CEto BYTE
Switching
Low or High

3

5

5

5

ns

3;6

60

70

80

ns

3

20

25

30

ns

tFHOV

BYTE Switching
High to
Valid Output Delay

tFLOZ

BYTE Switching
Low to
Output HighZ

0

.

Output Hold from
Addresses,
CE or, OE Change,
Whichever is First

0

0

ns·

'.

NOTES:
,
'
1. See A.C: Input/Output Reference Waveform for timing measurements.
2,QE may be delayed up to tCE-tOE after the falling edge of CEwithout impact on tCE'
3. Sampled. not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
6. tFLOV' BYTE switching low to valid output delay, will be equal tp tAvOV. measured from the time 00151 A7 becomes valid.

3-178

intal.

28F200BX-T IB, 28F002BX-T IB

EXTENDED TEMPERATURE OPERATIONS
AC CHARACTERISTICS-Read Only Operations(1):
T28F200BX-9O(4)
T28FOO2BX-9O(4)

Versions
Symbol

Parameter

tAVAV

tRC

Read Cycle Time

tAVQV

tACC

Address to
Output Delay

tELQV

' tCE

Notes

Min

90

CE to Output Delay

2

Unit

Max
ns

90

ns

90

ns

300

ns

45

ns

35

ns

tpHQV

tPWH

PWDHighto
Output Delay

tGLQV

toE

OE to Output Delay

2

tELQX

tLZ

CE to Output Low Z

3

tEHQZ

tHZ

CE High to Output
HighZ

3

tGLQX

toLZ

OE to Output Low Z

3

tOF

OE High to Output
HighZ

3

toH

Output Hold from
Addresses,
CE or OE Change,
Whichever is First

3

tELFL
tELFH

CEtoBYTE
Switching
Low or High

3

5

ns

tFHQV

BYTE Switching
High to
Valid Output Delay

3,5

90

ns

3

35

ns

tGHQZ

, tFLQZ

BYTE Switching
Low to
Output High Z

0

ns

0

ns

35
0

ns
ns

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tee-toe after the falling edge'of CE without impact on tee.
3. Sampled, not 1qO% tested.
4. See Standard Test Configuration.
5. tFLQV, BYiE switching low to valid output delay, will be equal to tAVQV, measured from the time D05tAl becomes valid.

3-179

--

Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

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ADDRESSES STABLE

ADDRESSES (A)
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75

75

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65
60
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7

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1 2

3

4

290448-26

5

6 7

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1
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9 10 11 12 13 14 15 16

Figure 18. lee (RMS) vs Frequency
(Vee = 5.5V) for x8 Operation

100
95
90
85

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290448-27

Figure 17. lee (RMS) vs Frequency
(Vee = 5.5V) for x16 Operation

0-'°"

-I-c--

~25OC

FREQUENCY (MHz)

FREQUENCY (MHz)

'"
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--0- OOC

1
1

5

9 10 11 12 13 14 15 16

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--028F200BX/28F002BX-60
~
~ 28F200BX/28F002BX-80

55
50
100

150

OUTPUT CAPACITANCE

200

250

(pr)
290448-28

Figure 19. T Aee vs Output Load
Capacitance (Vee = 4.5V, T = 70°C)

3-181

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290448-29

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intel~

28F200BX~T IB,

A.C. CHARACTERISTICS

28F002BX-T IB

For WE-Controlled Write Operaiions(1)
Vee ±5%

Version~

Symbol
tAVAV

twc

.

Parameter

28F200BX-SO(9)
28F002BX-SO(9)

Notes

Write Cycle Time

Min

Max

Vee
28F200BX-SO(10)
28F002BX-SO(10)

Min

60

70
215

tPHWL

tps

PWDHigh .
Recovery to
WE Going Low

215

tELWL

tcs

CE Setup to WE
Going Low

0

0

6,8

, 100

100

5,8

100

tPHHWH tPHS PWD VHH Setup to
WE Going High

Max

±

10%
28F200BX-80(10)
28F002BX-80(10)

Min

80
215 .

Unit

Max.
ns
ns

0

ns

100

ns

100

100

ns

,

tVPWH

tvps Vpp Setup to WE
Going High

tAVWH

tAS

Address Setup to
WE Going High

3

50

50

50

ns

tOVWH

tos

Data Setup to WE
Going High

4

60

60

60

ns

tWLwR

twp

WE Pulse Width

50

50

50

ns

tWHOX

tOH

Data Hold from
WE High

4

0

0

a

ns

tWHAX

tAH

Address Hold
from WE High

3

10

10

10

ns.

tWHEH

tCH

CE Hold from
WEHigh

,10

10

10

ns

tWHWL

twPH. WE Pulse
Width High

10

20

30

ns

tWHOV1

Duration of
Word/Byte Write
Oper?ltion

2,5

6

6

6

JJ-s

tWHOV2

Duration of Erase
Operation (Boot)

2,5,6

0.3

0.3

0.3

s

tWHOV3

Duration of Erase
Operation
(Parameter)

2,5

0.3

0.3

0.3

s

tWHOV4

Duration of Erase
Operation (Main) .

2,5,6

0.6

q.6

0.6

s

5,8

0

0

0

ns

tOWL

tVPH Vpp Hold from
. ValidSRD

3-183

.intel· '

·28F200BX·T IB, 28F002BX~T IB

AC CHARACTERISTICS

ForWE-Controlled Write Operations(l) (Continued)
Vee ±5%
28F200BX-60(9) .'
28F002BX·SO(9)

Versions
Symbol

Parameter

Notes

Min

6,8

0

tavPH tpHH PWDVHHHold
from Valid SAD
tpHBR

Boot-Block
Aelock Delay

Vee ± 10%
28F200BX-SO(10)
28F002BX·SO(10) .

Max

Min

28F200BX-80(10)
28F002BX-S0(10)

Max

Min

0

7,8

Unit

Max

0

100

ns

100

100

ns

NOTES:.
.
.' .
...
.
•1., Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to A.C.
characteristics during Read Mode:.
.
•
.
.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled Internally which includes verify and margining operations.
' .
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7=; 1):
6. For Boot Block Program/Erase, J5W[5 should be held at VH~ until operation completes successfully.
7. Time tpHBR is required for successful relocking of the Boot Block.
8. Sampled but not 100% tested.
.'
_ _
9. See High Speed Test Configuration.'
.
10. See Standard Test-Configuration.

BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp = 12.0V ±5%
Parameter

28F200BX-60
28F002BX-60
Typ(1) Max

Notes
Min

1.0

7

s

2.4

14

2.4

14

s

2

1.2

4.2

1.2

4.2

s

2

0.6

2.1

0.6

2.1

s

2

1.0

Main Block
Erase Time

2

-Main Block Word
Program Time .-

Unit

7

Boot/Parameter
Block Erase Time

Main Block Byte
Program Time

Min

28F200BX·80 •
28F002BX·80
Typ(1)
Max

,, .

,

NOTES:
.1. 25'C
2. Excludes .System-Level Overhead.

BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp = 12.0V ± 10%
Parameter

28F200BX·60
28F002BX·60 .
. Typ(1)
Max

Notes
Min

Boot/Parameter .
Block Erase Time

2

Main Block
Erase Time

. 28F200BX·80
28F002BX·80
Typ(1)
Max _
Min

.5.8

40

2

14

60

.14

Main Block Byte
Program Time

2

6.0

20

Main Block Word
- Program Time

2

3.0

10

\

NOTES:_
1. 25'C
2. Excludes System-Level Overhead.

3"184

,

5.8

Unit

40

s

60

s

6.0

20

s

3.0

10

,

,

s

28F200BX-TIB, 28F002BX-TIB

EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS For WE-Controlled Write Operations(1):
T28F200BX-90(9)
T28FOO2BX-90(9)

Verslons(4)
Symbol

Parameter

Notes

Min

Unit

Max

tAVAV

twc

Write Cycle Time

90

ns

tPHWL

tps

PWD High Recovery to
WE Going Low

210

ns

tELWL

les

CE Setup to WE Going Low

0

ns

tpHHWH

tpHS

PWD VHH l:1etup to WE Going High

6,8

100

ns

tvps

Vpp Setup to WE Going High

5,8

100

ns

tAvWH

tAS

Address Setup to WE Going High

3

60

ns

tOVWH

tos

Data Setup to WE Going High

4

60

ns

tWLWH

twp

WE Pulse Width

60

ns

tWHOX

tOH

Data Hold from WE High

4

0

ns

·tWHAX

tAH

Address Hold from WE High

3

10

ns

tWHEH

tCH

CE Hold fromWE High

10

ns

tWHWL

tWPH

WE Pulse Width High

\ tVPWH

Duration of Word/Byte
Write Operation

tWHOV1

. Duration of Erase Operation (Boot)

tWHOV2

Duration of Erase
Operation (Parameter)

tWHOV3

Duration of Erase Operation (Main)

tWHOV4
tOWL·

tVPH

taVPH

tpHH

tpHBR

.

Vpp Hold from Valid SRD
PWD VHH Hold from Valid SRD

,

' Bobt"Block Relock Delay

30

ns

2,5

7

p.s

2,5,6

0.4

s

2,5

0.4

s

2,5,6

0.7

s

5,8

0

ns

6,8

0

7,8

,

ns
100

ns

NOTES:

1. Read timing characteristics during write and erase operations are the sam·e as during read-only operations. Refer to A.C.
characteristics during Read Mode.
.
. .
2. The,on-chip WSM completely automates· program/erase operations; program/erase algorithms are now controlled internally which includes veritY and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to·command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRO data (successful operation, SR.7=1).
6. For 800t Block Program/Erase, PWO should be held ·at VHH until operation completes successfully.
7..Time tpHBR is required for successful relocking of the Boot Block. .
8. Sampled but not 100% tested.
.
., 9. See Standard Test Configuration.

3-185

28F200BX-T/B; 28F002BX-T/B

EXTENDED TEMPERATURE OPERATION
•
'
...
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE: Vpp
Parameter'

=

12 OV -+ 5% .

T28F200BX-90
T28FOO2BX-90

Notes
Min

Typ(1)

Unit
Max

; Hi.5

Boot/Parameter
Block Erase Time

2

1.5

Main Block
Erase Time

2

3.0

18

s

Main Block Byte
Program Time

2

1.4

5.0

s

Main Block Word
Program Time'

2

0.7

2.5

s

NOTES:
1. 25'C, 12,OV. Vpp.
2. Excludes System-Level Overhead.

s

,

I

,

_.

Vee POWER-UP
WRITE PROGRAM OR
'" STANDBY
ERASE SETUP COMMAND

WRITE
VAliD ADDRESS'" DATA (PROGRAM)
OR ERASE CONfiRM COMMAND

AUTOMATED PROGRAM
OR ERASE DELAY

l

WRITE READ ARRAY
COMMAND

READ STATUS
REGISTER DATA

~

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PP
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290448-16

©

~

28F200BX-T /B; 28F002BX-T /B

AC CHARACTERISTICS
FOR CE-CONTROLLED WRITE OPERATIONS(1,9)
I
Vee± 10%
Vee ±5%
28F200BX-60(10) 28F200BX-60(11) 28F200BX-80(11)
28F002BX-60(10) 28F002BX-60(11) 28F002BX-80(11) Unit

Versions
,

Symbol

Parameter

tAVAV

twc Write Cycle Time

tpHEL

tps

tWLEL

tws WE Setup to CE
Going Low

PWD High A~covery
to CE Going Low

tpHHEH tpHS PWD VHH Setup to
CE Going High

Max

Max

Min

Max

SO

70

80

ns

215

215

215

ns

0

0

ns

100

100

ns

"

O'
S,8

Min

100

.'

100

100

100

ns

Address Setup to ,
CE Going High

3

50

50

50

ns

tos

Data Setup to CE
Going High

4

60

SO

SO

ns

tcp

CE Pulse Width

50

50

50

ns

4

0

0

0

ns

3

10

10

10

ns

tvps Vpp Setup to CE
Going High

tAVEH

tAS

tbVEH
tELEH

tEHOX tOH Data Hold from
CE High
tAH

Address Hold
fromCE High

10

10

10

ns

10

20

30

ns

2,5

S

6

S

,/Ls

2,5,S

0.3

0.3

0.3

s

tEHWH tWH WE Hold from CE High
tEHEL

Min

5,8

tVPEH

tEHAX

Notes

tCPH CE Puls.e
Width High

tEHQV1

Duration of Word/Byte
Programming
Operation

tEHQV2

Duration of Erase
Operation (Boot)

tEHQV3

Duration of Erase
Operation (Parameter)

2,5

0.3

0.3

0.3

s

tEHQV4

Duration of Erase
Operation (Main)

2,5

O.S

O.S

O.S

s

tQWL

tVPH Vpp Hold from
Valid SAD

5,8

0

0

0

taVPH

tpHH PWDVHH Hold
from Valid SAD

S,8

d

0

0

tpHBR

Boot-Block Aelock Delay

7

100

100

,

ns
ns

100

ns

NOTES:

1, Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE In systems where CE
defines the write pulse-width (within a longer WE timing waveform), all set-up, hold and inactive WE time should be mea:
.
sured relative to th!l CE w a v e f o r m . '
2,3,4,.5,6,7,8: Refer to A.C, Characteristics notes for WE-Controlled Write Operations,
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to A.C,
Characteristics during Read, Mode,
" .
10, See High Speed Test Configuration.
11, See Stand.ard Test Configuration,

3-188

int:et

28F200BX-T/B,28F002BX-T/B

EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR CE-CONTROLLED WRITE OPERATIONS(1,9)
T28F200BX-90(10)
T28FOO2BX-90(10)

Versions
Symbol

Parameter

Notes

Min

Unit

Max

90

ns

210

ns

0

ns

6,8

100

ns

Vpp Setup to CE
Going High

5,8

100

ns

tAS

Address Setup to
CE Going High

3

60

ns

tOVEH

tos

Data Setup to CE
Going High

4

60

ns

tELEH

tcp

CE Pulse Width

60

ns

tEHOX

tOH

Data Hold from
CE High

4

0

ns

tEHAX

tAH

Address Hold
from CE High

3

10

ns

tEHWH

tWH

WE Hold from CE High

10

ns

tCPH

CE Pulse
Width High

30

ns

2,5

7

/ls

2,5,6

0.4

s

tAVAV

twc

Write Cycle Time

tpHEL

tps

PWD High Recovery
to CE Going Low

tWLEL

tws

WE Setup to CE
Going Low

tpHHEH

tPHS

PWD VHH Setup to
CE Going High

tVPEH

tvps

tAVEH

tEHEL
tEHQV1

Duration of Word/Byte
Programming
Operation

tEHQV2

Duration of Erase
Operation (Boot)

tEHQV3

Duration of Erase
Operation (Parameter)

2,5

0.4

s

tEHQV4

Duration of Erase
Operation (Main)

2,,5

0,7

s

tQWL

tVPH

Vpp Hold from
Valid SRD

5,8

0

ns

tQVPH

tpHH

PWDVHH Hold
from Valid SRD

6,8

0

ns

tpHBR

Boot-Block Relock Delay

7

100

ns

NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE in systems where CE'
defines the write pulse-width (within a longer WE timing wavefo,rm), all set-up, hold and inactive WE time should be measured relative to the CEo waveform.
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics for WE-Controlled Write Operations:
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.

3-189

_.
Vee POWER-UP
WRITE PROGRAM OR
&: STANDBY
ERASE SETUP COMMAND

!!

.

10
C
CD

~

WRITE
VAliD ADDRESS 8< DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

-AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

c(

WRITE READ ARRAY
COMMAND

@

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VIH
DATA (D/Q)
Vil

0

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CD

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::I
III

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0
0

~

J:::-:~H.!...,J---' -----------------

l§J

~

6.SV
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~

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..

IiiiiI

Vil

~
©

::I

tVPEH

2-

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"iiiJ

VpPH

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VPP (V)

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290448-17

©
~

intel .

28F200BX-TIB, 28F002BX-TIB

ORDERING INFORMATION
I
·'-1_ _ _-----'I

OPERATING TEMPERATURE
T
= EXTENDED TEMP
. BLANK:= COMMERCIAL TEMP

'Valld Combinations:
E2BF200BX-60
PA2BF200BX-60
E2BF200BX-BO ,
PA2~F200BX-BO

121al r Iii 0I 0I B I X 1-161 0I
Y
.
PACKAGE
ACCESS SPEED (~.)
E = STANDARD 56 LEAD TSOP'
60 ns·

IE

~.

= 44

PA

:~~:

LEAD PSOP

TE2BF200BX-T90
TE2BF200BX-B90

290448-1 a

TPA2BF200BX-T90
TPA2BF200BX-B90

·IIEI2IalrloI012IBlxl-lsI01
,.-_""';":-~---JI ~

OPERATING TEMPERATURE
T
= EXTENDED TEMP
BLANK = COMMERCIAL TEMP

PACKAGE
E' = STANDARD 40 LEAD TSOP

~
. ACCESS SPEED (ns)
50 ns
ao ns
90 ns

290448-23

Valid Combinations:·
E2BF002BX-60
TE2BF002BX-T90 .
E2BF002BX-BO
• TE2BF002BX-B90

Order Number

ADDITIONAL INFORMATION

290451

.. 28F400BX/28F004BX Datasheet
28F200BXL/28F002BXL Datasheet

290449

28F400BXL/28F004BXL Datasheet

290450

AP-363 "Extended Flash BIOS Design f.or Portable Computers"

292098

ER-28"ETdx~11I Flash MemorY Technology"
ER-29 "The InteI2/4-Mbit Boot Block Flash Memory Family"

204012

REVISION HISTORY
Number
~002

Description
Removed -70 speed bin
Integrated -70 characteristics into - 60 speed bin
Added Extended Temperatllre characteristics
Modified BYTE Timing Diagram
Improved tPHQV, PWD High to Output Delay and
tpHEL, PWD High Recovery to CE going low
specifications .

3-191

294013

,infel®
.

,28F200BX-Tl/BL, 28F002BX-TL/BL
2 MBIT(128K x 16, 256K x 8) LOW POWER BOOT BLOCK
FLASH MEMORY FAMILY
.

.. Low Voltage Operation for Very Low
Power Portable Applications
- VCC = 3.3V ± 0.3V
• xS/x16 Input/Output Architecture
...:.. 2SF200BX·TL, 2SF200BX·BL
- For High Performance and High
Integration 16·bit and 32·blt CPUs
• xS·only Input/Output Architecture
- 2SF002BX·TL, 2SF002BX·BL
- For Space Constrained S·blt
Applications
• Optimized High Density Blocked
Architecture
,... One 16 KB Protected Boot Block
,... TwoS KB Parameter Blocks .
- One 96 KBMaln Block
- One 12S KB Main Block
-Top or Bottom Boot Locations

II VeryHlgh·Performance Read
-150 ns Maximum Access Time
- 65 ns Maximum Output Enable Time
W Low Power Consumption
-10 mA Typical xSActlve Read
Current
-12 mA Typical x16 Active Read
Current
fi

iI

m
Iiill

• Extended Cycling Capability
-10,000 Block Erase Cycles
• Automated Word/Byte Write and Block
Erase
- Command User InterfaCe
....:. Status Registers
- Erase Suspend Capability
• SRAM·Compatlble Write Interface' .
• Automatic Power Savings Feature
- O.S mA Typical Icc Active Current in
Static Operation

III
III
•

Deep Power·Down/Reset Input
- 0.2 /LA Icc Typical
- Acts as Reset for Boot Operations
Write Protection for Boot' Block
Hardware' Data Protection Feature ,.
- Erase/Write Lockout during Power
Transitions
Industry Standard Surface Mount
Packaging
- 2SF200BX·L: JEDEC ROM Compatible
44·Lead PSOP
56·Lead TSOP
- 2SF002BX·L: 40·Lead TSOP .
12V Word/Byte Write and Block Erase'
- Vpp = 12V ± 5% Standard
ETOXTM III Flash Technology
-3.3V Read
Independent Software Vendor Support
- SystemSoft* Flash BIOS

'SystemSoftO is a trademark of SystemSoft Corporation,

3.-192

November 1992
Order Number: 290449-002

infel .

28F200BX-TL/BL, 28F002BX-TL/BL

Intel's 2 Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes
block-selective erasure, automated write and erase operations and standard microprocessor interface. The
2 Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16
input/output control, very low power, very high speed, an industry standard ROM compatible pinout and
surface mount packaging. The 2 Mbit Low Power Flash Family opens a new capability for 3V battery-operated
portable systems and allows for an easy upgrade to Intel's 4 Mbit Low Power Boot Block Flash Memory
Family.
The Intel 28F200BX-TL/BL are 16-bit wide flash memory offerings. These high density flash memories pro~ide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BX-TL and 28F200BX-BL are
2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.
The Intel 28F002BX-TLlBL are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F200BX-TL/28F002BX-TL provide block locations compatible with
Intel's low voltage MCS-186 family, i386™, i486TM microprocessors. The 28F200BX-BLl28F002BX-BL provide compatibility with Intel's80960KX and 80960SX families as well as other low voltage embedded microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 150 ns, these 2 Mbit flash devices are very high performance low power memories
which interface to a wide range of low power microprocessors and microcontrollers. A deep power-down mode
lowers the total Vee powerconsumption to 0.66 p.W. This is critical in handheld battery powered systems such
as Handy Phones. For very high speed applications using a 5V supply, refer to the Intel 28F200BX-T/B,
28F002BX-T /B 2 Mbit Boot Block Flash Memory Family datasheet.
Manufactured on Intel's 0.8 micron ETOXTM III process, the 2 Mbit low power flash memory family provides
world class quality, reliability and cost-effectiveness at the 2 Mbit density level.

3-193

intet

28F200BX-TLlBL, 28F002BX-TL/BL

1.0 PRODUCT FAMIL YOVERVIEW
Throughout this datasheet 28F200BX-L refers to
both the 28F200BX-TL and 28F200BX-BL devices
and 28F002BX-L refers to both the 28F002BX-TL
and 28F002BX-BL devices. The 2 Mbit flash family
refers to both the 28F200BX-L and 28F002BX-L
products. This datasheet comprises the specifications for four separate products in the 2 Mbit flash
memory family. Section 1 provides a[l overView of
the 2 Mbit flash memory family including applications, pinouts and pin descriptions. Sections 2 and 3describe in detail the specific memory organizations
for the 28F200BX-L and 28F002BX-L products respectively. Section 4 combines a description of the
family's principles of operations. Finally, section 5
describes the family's operating specifications.
PRODUCT FAMILY
xB/x16 Products

xB-Only Products

28F200BX-TL
28F200BX-BL

28F002BX-TL
28F002BX-BL

1.1 Main Features
The 28F200BX-L/28F002BX-L low power boot
block flash memory family is a very low power and
very high performance 2 Mbit (2,097,152 bit) memory family organized as either 128 Kwords (131,072
words) of 16 bits each or 256 Kbytes (262,144
bytes) of 8 bits each.
Five Separately Erasable Blocks including a Hardware·Lockable boot block (16,384 Bytes), two pa- rameter blocks (8,192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of
131,072 Bytes) are included on the 2 Mbit family. An
erase operation erases one of the 5 blocks in typically 3.4 seconds and the boot or parameter blocks
in typically 2.0 seconds, independent of the remaining blocks. Each block can be independently erased
and programmed 10,000 times.
The Boot Block is located at either the top
(28F200BX-TL, 28F002BX-TL) or the bottom
(28F200BX-BL, 28F002BX-BL) of the address map
in order to accommodate different microprocessor
protocols for boot code location. The hardware
lockable boot block provides the most secure code

storage. The boot block is intended to store the kernel code required for booting-up a system. When the
PWD pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the PWD pin is at or below4.1 V
the boot block is locked and program and erase operations to the boot block are ignored.
The 28F200BX-L products are available in - the
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2 mm
thick) package as shown in Figures 3 and 4. The
28F002BX-L products are available in the 40-Lead
TSOP (1.2 mm thick) package as shown in Figure 5.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the 28F200BX-L
and 28F002BX-L flash products.
Program and Erase Automation allow program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings -necessary for program
and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the 28F200BX-Lfamily and in
byte increments for the 28F002BX-L family typically
within 11 J.ts.
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of 150 ns (TACe) is
achieved over the commercial temperature range
(O°C to + 70°C), over Vee supply voltage range
(3.0V to 3.6V, 4.5V to 5.5V) and 50 pF output load.
Ipp Program current is 40 mA for x16 operation
and 30 mA for xB operation. Ipp Erase current is
30 mA maximum. Vpp erase and programming
voltage is 11.4V to 12.6V (Vpp = 12V ±5%) under all operating conditions.
Typical Icc Active Current of 12 mA is achieved
for the x16 products (28F200BX-L), typical Icc Active Current of 10 mA is achieved fori the x8 prod"
ucts (28F200BX-L, 28F002BX-L). .

.'
3-194

intaL

28F200BX-TL/BL, 28F002BX-TL/BL

The 2 Mbit flash family is also designed with an Automatic Power Savings (APS) feature to minimize
system battery current drain and allow for extremely
low power designs. Once the device is accessed to
read the array data, APS mode will immediately put
the memory in static mode of operation where Icc
active current is typically 0.8 mA until the next read
is initiated.
When the CE and PWD pins are at Vcc and the
BYTE pin (28F200BX-L-only) is at either Vcc or
GND the CMOS Standby mode is enabled where
Icc is typically 40 /LA.
A Deep Power-down Mode is enabled when the
PWD pin is at ground minimizing power consumption
and providing write protection during power-up conditions. Icc current during deep power-down mode
is.0.20 J.LA typical. An initial maximum access time
or Reset Time of 700 ns is required from PWD
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 580 ns until
writes to the Command User Interface are recognized. When PWD is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to PWD to reset the memory to normal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the 2 Mbit
family and the PWD functionality for data protection,
after the CPU is reset and even if a program or erase
command is issued, the device will not recognize
any operation until' PWD returns to its normal state.

duction flow, reducing system inventory and costs,
and eliminating component handling during the production phase. During the product life cycle, when
code updates or feature enhancements become
necessary, flash memory will reduce the update
costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 2 Mbit boot block flash family provides full function, blocked flash memories suitable
for a wide range of applications. These applications
include Extended PC BIOS, Handy Digital Cellular
Phone program and data storage and various other
portable embedded applications where both program and data storage are required.
Reprogrammable systems such as Notebook and
Palmtop computers, are ideal applications for the
2 Mbit low power flash products. Portable and
handheld personal computer applications are becoming more complex with the addition of power
management software to take advantage of the latest microprocessor technology, the availability of
ROM-based application software, pen tablet code
for electronic handwriting, and diagnostic code. Figure 1 shows an example of a 28F200BX-TL application.
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 2 Mbit low power flash
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 2 Mbit flash products' deep power-down mode
provides added flexibility for these battery-operated
portable designs which require operation at extremely low power levels.

1.2 Applications

The 2 Mbit low power flash products also provide
excellent design solutions for Handy Digital Cellular
Phone applications requiring high density storage,
high performance capabilities coupled with low voltage operation, and a small form factor package (x8only bus). The 2 Mbit's blocking scheme allows for
an easy segmentation of the embedded code with;
16 Kbytes of Hardware-Protected Boot code, 2 Main
Blocks of program code and 2 Parameter Blocks of
8 Kbytes each for frequently updatable data storage
and diagnostic messages (e.g., phone numbers, authorization codes). Figure 2 is an example of such an
application with the 28F002BX-TL.

The 2 Mbit low power boot block flash family combines high density, 3V operation, high performance,
cost-effective flash memories with blocking and
hardware protection capabilities. Its flexibility and
versatility will reduce costs throughout the product
life cycle. Flash memory is ideal for Just-In-Time pro-

These are a few actual examples of the wide range
of applications for the 2 Mbit Low Power Boot Block
flash memory family which enables system designers to achieve the best possible product design.
Only your imagination limits the applicability of such
a versatile low power product family.

For the 28F200BX-L, Byte-wide or Word-wide Input/Output Control is possible by controlling the
BYTE pin. When the BYTE pin is at a logic low the
device is in the byte-wide mode (x8) and data is read
and written through DQ[0:7]. During the byte-wide
mode, DQ[8:14] are tri-$tated and DQ15/A-1 becomes the lowest order address pin. When the
BYTE pin is at a logiC high the device is in the wordwide mode (x16) and data is read and· written
through OQ[O:15].

3-195

28F200BX-TLlBL, 28F002BX-TL/BL

12Y

-r-\...1 ~ ~

GPIO
82360SL

XD7

.

RESET --L,...r""1

Controller

GPIO
XDIR

I

-~

Ypp
'Switch

Ypp
SAO- 16
80386SL

ROMCSO

OE

MEMRD
MEMWR

WE
GPIO

3Y

ROM16/a

290449-6

Figure 1. 28F200BX-TL Interface to INTEL386SLTM 3.3V Microprocessor Superset

"

A16: 17

~

ADDRESS
LATCHES
LE

Aa -AI5
ALE
ADo-A~

80L188EB
UCS

"

liU

.ADDRESS
LATCHES
LE

fll
tdJ

L

DQo-D~

CE

f2Y
P1.X

---, I

Ypp
GENERATOR

-

I

PWD

WE

R1i

OE

L

SYSTEM RESET

28FOO2BX-TL

Ypp

WR

RESIN

~t

Ao-Al l

~

290449-22

Figure 2. 28F002BX-TL Interface to INTEL 80L 188EB, Low Voltage 8·Bit Embedded Microprocessor

3·196

infel·

28F200BX-TL/BL, 28F002BX-TL/BL

1.3 Pinouts
The 28F200BX-L 44-Lead PSOP pinout follows the
industry standard ROM/EPROM pinout as shown in
Figure 3 with an upgrade to the 28F400BX-L
(4 Mbit low power flash family). Furthermore,
the 28F200BX-L 56-Lead TSOP pinout shown in

Figure 4 provides density upgrades to the
28F400BX-L and to future higher density boot block
memories.
The 28F002BX-L 40-Lead TSOP pinout shown in
Figure 5 is 100 % compatible and has a density upgrade to the 28F004BX-L 4 Mbit Low Power Boot
Block flash memory.

28F400BX·L

28F400BX·L

DU

ffi
WE

A17
Ai

log

As
Ag

Ato
Atl

Al0
Al1

At2
At3

A12

vpp

As

Av
As

. A..
A3
A2
Al

Ao
~

GND

Ao
CE
GND

OE

PA28F200BX-L
44 LEAD PSOP
0.525" X 1.110"
TOP VIEW

PWD

WE

A13

At.

A14

At5

Al~
A16

At6

BYTE

BYTE

GND

GND

00,5/A.. 1

D01S/A-l

DOo

DOo

Da,

DO?

DOs

DOs

DO,.

DOl
DOg

00,
DOg

DIIt!

D014
D06

D02
·0010

~
00,0

00,3
DOg

D013
DOs

00,2

D03

D~

IX4

D012
D04

0011

00,1

Vee

Vee

290449-24.

Figure 3. PSOP Lead Configuration for x8/x16 28F200BX·L

3-197

intel .

28F200BX-TL/BL, 28F002BX-TL/BL

28F400BX-L
NC
NC
A,S
A'4
A,S
A'2
. All
A'0
Ag
As
NC
NC

WE
PWD
NC
NC
Vpp
DU
NC
Al7
A7
,A6
As
A4
As
A2
Al
NC

~@\VI~OO©~ OOO[F@OOIMl~"iiO@OO

I

NC
NC
A,S
-'I.
A'3
-'12
-'II
-'10
Ag

As

NC
NC
WE

PWD
NC
NC
Vpp
DU
Ne
NC
A7

As

As
A4
A3
A2
-'I
NC

~O

·3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

28F200BX-L
56-LEAD TSOP
14mm X 20mm
TOP VIEW

56
55
54
53
52
51
50
49
48'
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
-'16 .
BYTE
GND
DO, 5 /A-l
Deq
DO, 4
DOt;
DO'3
DOS
DO, 2
DO.
Vee
Vee
DO, 1
D03
DO, 0
D02
DOg
DO,
DOs
DOo
OE
GND
CE

Ao

NC
NC

28F400BX-L
NC
A'6
BYTE
GND
DO,S/A-,

D07
DO'4
D06
DO,S
DOs
DO'2
D04
Vee
Vee
DOl1
DOs
DOlO
D02
DOg
DO,
DOs
DOo
OE
GND
CE
Ao
NC
NC
290449-4

Figure 4. TSOP Lead Configuration for x8/x16 28F200BX-L .
28FOO4BX-L
A'6
A,S
A'4
A,S
A'2
All

As
As
WE
PWD
Vpp
DU
A,a
A7

As

As
~

As
A2
A,

28FOO4BX-L
-'16
-'Is
A,.
-'13
-'12
-'II
Ag

~
WE
PWD
Vpp
DU
NC
A7

As

As

~O

3·
4
5
6
7
8
9

10
11
12
13
14

28FOO2BX-L
40-LEAD TSOP
10mm X 20mm
TOp·VIEW

15
16

.A4

17

A3
A2
A,

18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
. 26
25
24
23
22
21

-'17
GND
NC
NC
-'10
Deq
DOs
DOs
D04
Vee
Vee
Ne
D03
D02

Do,
DOo
OE
GND
CE

Ao

A'7
GND
NC
NC
A'0
D07
DOa
DOs
D04
Vce
Vee
NC
DOs
D02
DO,
DOo
OE
GND
CE
Ao
290449-5

Figure 5. TSOP Lead Configuration for x828FOO2BX-L

3-198

int'et

28F200BX-TL/BL, 28F002BX-TL/BL

1.4 Pin Descriptions for xS/x16 28F200BX-L
Symbol

Type

Name and Function

Ao-A16

I

ADDRESS INPUTS fOr memory addresses. Addresses are internally latched
during a write cycle.

Ag

I

ADDRESS INPUT: When Ag is at12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's. When BYTE is at a
logic low only the lower byte of the signatures are read. 0015/ A -1 is a don't care
in the signature mode when BYTE is low.

I/O

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
command. Inputs commands to the command user interface
when CE and WE are active. Data is internally latched during the write and
program cycles. Outputs array, intelligent identifier and Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.

DOO-DO?

during~rogram

008- 0015

I/O

-

DATA INPUT/OUTPUTS: Inputs array data on the second CE and WE cycle
during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE = "0"). In
the byte-wide mode 0015/ A -1 becomes the lowest order address for data output
on DOo-DO?

CE

I

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels. If CE and PWD are high, but not at
a CMOS high level, the standby current will increase due to current flow through
the CE and PWD input stages.

PWD

I

POWER-DOWN: Provides Three-State control. Puts the device in deep powerdown mode. Locks the boot block from program/erase.
When PWD is at logic high level and equals 4.1 V maximum the boot block is
locked and cannot be programmed or erased.
When PWD
or erased.-

=

11.4V minimum the boot block is unlocked and can be programmed

When PWD is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions.
PWD terminates any internally timed erase or program activities when it is taken to
a logic low. PWD activates the CE input stage and requires 700 ns recovery time to
transition from deep power-down to valid data on the outputs or 580 ns delay
before the device can recognize valid inputs.
OE

I

OUTPUT ENABLE: Gates the device's outputs through the data buffers cluring a
read cycle. OE is active low.

WE

I

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE
is active low. Addresses and data are latched on the rising edge of the WE pulse.

3-199

intel"

28F200BX·TL/BL, 28F002BX·TL/BL

1.4 Pin Descriptions for x8/x16
Symbol
BYTE

Vpp

Type

I

28F200BX-L(Continued)
Name and Function

BYTE ENABLE: Controls whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE = "0" enables the byte-wide mode, where data is
read and programmed on DOO-D07 and D015/ A-1 becomes the lowest order
address that decodes between the upper and lower byte. D08-D014 are tri-stated
during the byte-wide mode. BYTE = "1" enables the word-wide mode where data is
read and programmed on DOO-D015.
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp

< VPPLMAX memory contents cannot be altered.

Vee

DEVICE POWER SUPPLY (3.3V

± 0.3V, 5V ± 10%)

GND

GROUND: For all internal circuitry.

NC

NO CONNECT: Pin may be driven or left floating.

DU

DON'T USE PIN: Pin should not be connected to anything.

3-200

infel~

28F200BX-TL/BL, 28F002BX-TL/BL

1.5 Pin Descriptions for x8 28F002BX-L
Type

Name and Function

Ao-A17

I

ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.

Ag

I

ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode AD decodes between the manufacturer and device ID's.

I/O

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle
duringErogram command. Inputs commands to the command user interface
when CE and WE are active. Data is internally latched during the write and program
cycles. Outputs array intelligent identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.

Symbol

DOO-D07

CE

I

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels.

PWD

I

POWER·DOWN: Provides Three-State control. Puts the device in deep powerdown mode. Locks the Boot Block from program/erase.
When PWD is at logic high level and equals 4.1V maximum the Boot Block is locked
and cannot be programmed or erased.
When PWD = 11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When PWD is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions.
PWD terminates any internally timed erase or program activities when it is taken to
a logic low. PWD activates the CE input stage and requires 700 ns recovery time to
transition from deep power-down to valid data on the outputs or 580 ns delay before
the device can recognize valid inputs.

DE

I

OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. DE is active low.

WE

I

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE is
active low. Addresses and data are latched on the rising edge. of the WE pulse.

Vpp

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp

< VPPLMAX memory contents cannot be altered.

Vee

DEVICE POWER SUPPLY (3.3V ±0.3V, 5V ± 10%)

GND

GROUND: For all internal circuitry

NC

NO CONNECT: Pin may be driven or left floating

DU

DON'T USE PIN: Pin should not be connected (to anything

3-201

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intel~

28F200BX-TL/BL, 28F002BX-TL/BL

2.1 28F200BX-L Memory Organization

2.1.1.3 Main Block Operation

,2.1.1 BLOCKING
The 28F200BX-L uses a blocked array architecture
to provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written.to the CUI. The 28F200BX-L
is a random read/write memory, only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16 Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when PWD is not at 12V. The boot block can
be erased and written when PWD is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block for the 28F200BX-TL and
28F200BX-BL.

Two main blocks of memory exist on the
28F200BX-L (1 x 128 Kbyte block and 1 x 96 Kbyte
blocks). See the following section on Block Memory
Map for the address location of these blocks for the
28F200BX-TL and 28F200BX-BL products.
2.1.2 BLOCK MEMORY MAP
Two versions of the 28F200BX-L product exist to
support two different memory maps of the array
blocks in order to accommodate different microprocessor protocols for boot code location. The
28F200BX-TL memory map is inverted from the
28F200BX-BL memory map.
2.1.2.1 28F200BX-BL Memory Map
The 28F200BX-BL device has the 16 Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the
bottom of the address map at OOOOOH. In the
28F200BX-BL the first 8 Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8 Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96 Kbyte main block resides in memory space from
04000H to OFFFFH. The 128 Kbyte main block resides in memory space from 10000H to 1FFFFH
(word locations). See Figure 7.
(Word Addresses)

2.1.1.2 Parameter Block Operation
The 28F200BX-L has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic .information. The
parameter blocks can also be used to store additional boot or main code. The parameter blocks however, do not have the hardware Write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus reg-ularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F200BX-TL and 28F200BX~BL.

lFFFFH

126 Kbyte MAIN BLOCK
10000H
OFFFFH
96 Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH

,
6 Kbyte PARAMETER BLOCK
6 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK
OOOOOH

Figure 7. 28F200BX·BL Memory Map

3-203

intet

28F200BX-TL/BL, 28F002BX-TL/BL

2.1.2.2 28F200BX-TL Memory Map

(Word Addresses)

The 28F200BX-TL device has the 16 Kbyte boot
block located from 1EOOOH to 1FFFFH to accommodate those microprocessors that boot from. the top
of .the address map. In the 28F200BX-TL the first
8 Kbyte parameter block resides in. memory space
from 1DOOOH to 1DFFFH. The second 8 KbytepaJameter block resides in memory space from
1COOOH to 1CFFFH. The 96 Kbyte main block resides in memory space from 10000H to 1BFFFH.
The 128 Kbyte main block resides in memory space
from OOOOOH toOFFFFH as shown below in Figure
8.

1FFFFH
16 Kby1e BOOT BLOCK
1EOOOH
1DFFFH
1DOOOH
1CFFFH
1COOOH
1BFFFH

8 Kby1e PARAMETER BLOCK
8 Kby1e PARAMETER BLOCK

96 Kby1e MAIN BLOCK
10000H
OFFFFH
128 Kby1e MAIN BLOCK
OOOOOH

Figure 8. 28F200BX-TL Memory Map

3-204

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28F200BX-TL/BL, 28F002BX-TL/BL

See the following section on Block Memory Map for
the address location of these, blocks for ·the
28F002BX·TL
and 28F002BX·BL.
,

3.1 28F002BX-L Memory Organization
3.1.1 BLOCKING

The 28F002BX·L uses a blocked array architecture
to provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad·
I dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F002BX·L
is a random read/write memory. only erasure is per·
formed ,by block.'

3.1.2 BLOCK MEMORY MAP

Two versions of the 28F002BX·L product exist to
support two different memory maps of the array
blocks in order to aC90mmodate different microproc·
essor protocols for boot code location. The
28F002BX·TL memory map is inverted from the
28F002BX·BL memory map ..
3.1.2.1 28F002BX~BL Memory Map

3.1.1.1 Boot Block Operation and Data
Protection

The 16 Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow·
er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block fr.om beil'lg programmed
or erased when PWD is not at 12V. The boot block
can be erased and programmed when PWD is held
at 12V for the duration of the erase or program oper·
ation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F002BX·TL and 28F002BX·BL.

The 28F002BX·BL device has the 16 Kbyte boot
block located from OOOOOH to 03FFFH to accommo·
date those microprocessors that boot from the bot·
tom of the address map at OOOOOH. In the'
28F002BX·BL the first 8 KbytE1 parameter block reo
sides in memory from 04000H to 05FFFH. The sec·
ond 8 Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96 Kbyte main
block .resides in memory space from 08000H to
1FFFFH. The 128 Kbyte main block resides in memo
ory space from 20000H to 3FFFFH. See Figure 10.

3FFFFH

128 Kbyte MAIN BLOCK
20000H
1FFFFH

3.1.1.2 Parameter Block Operation

The 28F002BX·L has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to pro·
vide storage for frequently updated system parame· '
ters and configuration or diagnostic'information. The
parameter blocks can also be used to'store addition·'
al boot or main code. The parameter blocks howev·
er; do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map sec·
tion for address locations of the parameter blocks
·fQf the 28F002BX·TL and 28F002BX·BL.
3.1.1.3 Main Block Operation

Two main blocks of memory exist on the
28F002BX·L (1 x 128 Kbyte block and 1 x 96 Kbyte
block).
.

3·206

96 Kbyte MAIN BLOCK
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK

OOOOOH

Figure 10. 28F002BX-BL Memory Map

intel"

28F200BX-TL/BL, 28F002BX-TL/BL

3.1.2.2 28F002BX-TL Memory Map

The 28F002BX-TL device has the 16 Kbyte boot
block located trom 3COOOH to 3FFFFH to accommodate those microprocessors that boot from the
top of the address map. In the 28F002BX-TL the first
8 Kbyte parameter block resides in memory space
from 3AOOOH to 3BFFFH. The second 8 Kbyte parameter block resides in memory space from
38000H to 39FFFH. The 96 Kbyte main block resides in memory space from20000H to 37FFFH.
The 128 Kbyte main block resides in memory space
from OOOOOH to 1FFFFH.

16 Kbyte BOOT BLOCK

3COOOH
3BFFFH

38000H

In the absence of high voltage on the Vpp pin, the
2 Mbit flash family will only successfully execute the
following commands: Read Array, Read Status Register, Clear Status Register and Intelligent Identifier
mode. The device provides standard EPROM read,
standby and output disable operations. Manufacturer Identification and Device Identification data can
be accessed through the CUI or through the standard EPROM A9 high voltage access (VID) (for
PROM pr0grammer equipment).
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.

3FFFFH

3AOOOH
39FFFH

The CUI allows for fixed power supplies during erasure and programming, and maximum EPROM com~
patibility.

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

37FFFH

The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.

96 Kbyte MAIN BLOCK
20000H

1FFFFH
128 Kbyte MAIN BLOCK

OOOOOH

Figure 11. 28F002BX-TL Memory Map

4.1 28F200BX-L Bus Operations

4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 2 Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.

3-207

intel~

28F200BX-TL/BL, 28F002BX-TL/BL

Table 1. Bus Operations for WORD-WIDE Mode (BYTE = VIH)
Mode

Notes

PWD

CE

OE

WE

Ag

Ao

Vpp

X

X

DOUT

DQO-15

V'H

V'L

V'L

V'H

X

Output Disable

V'H

V'L

V'H

X

X

X

HighZ

Standby

V'H

V'H

X

V'H
X

X

X

X

HighZ

V'L

X

X

X

X

X

X

HighZ
0089H

Read

1,2,3

Deep Power·Down

9

Intelligent Identifier (Mfr)

4

V'H

V'L

V'L

V'H

V'D

V'L

X

4,5,
10

V'H

V'L

V'L

V'H

V'D

V'H

X

2274H
2275H

6,7,8

V'H

V'L

V'H

V'L

X

X

X

D'N

Intelligent Identifier (Device)
Write

Table 2. Bus Operations for BYTE-WIDE Mode (BYTE = VIL)
Mode
Read

Notes

PWD

CE

OE

WE

Ag

1,2,3

V'H

V'L

V'L

V'H
V'H

Ao

A-1

X

X

X

X

X

X

Vpp

DQO-7

DQS-14

X

DOUT

HighZ

HighZ

HighZ

V'H

V'H

X

X

X

X

X

X
X

HighZ,

HighZ

Deep Power·Down

9~

V'L

X

X

X

X

X

X

X

HighZ

HighZ

Intelligent Identifier
(Mfr)

4

V'H

V'L

V'L

V'H

V'D

V'L

X

X

89H

HighZ

Intelligent Identifier
(Device)

4,5

V'H

V'L

V'L

V'H

V'D

V'H

X

X

74H
75H

HighZ

6,7,8

V'H

V'L

V'H

V'L

X

X

X

X

D'N

HighZ

Output Disable
Standby

Write

V'H

V'L

V'H

,

NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for contra' pins and addresses, VPPL or VPPH for Vpp.
3. See DC characteristics for VPPL, VPPH,- VHH, VIO voltages;
4. Manufacturer and Device codes may also be accessed via a CPU write sequence. A1-A16 = VIL.
5. Device ID = 2274H for 28F200BX-TL and 2275H for 28F200BX-BL.
6. Refer to Tab'e 4 for valid DIN during a write operation.
7. Command writes for B'ock Erase or Word/Byte Write are on'y executed when Vpp = VPPH.
8. To write or erase the boot b'ock, hold PWD at VHH.
9. PWD must be at GND ± O.2V to meet the 1.2 /LA maximum deep power-down current.
10. The device 'D codes are identical to those of the 28F2100BX 5V versions.

3-208

28F200BX-TL/BL, 28F002BX-TL/BL

4.2 '28F002BX-L Bus Operations
Table 3. Bus Operations
Mode
Read

Notes

PWD

CE

1,2,3

VIH

VIL

VIH

VIL

Output Disable
Standby
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write

WE

Ag

Ao

Vpp

DQO-7

VIL

VIH

X

X

X

DOUT

VIH

VIH

X

X

X

HighZ

OE

VIH

VIH

X

X

X

X

X

HighZ'

9

VIL

X

X

X

X

X

X

HighZ

4

VIH

VIL

VIL

VIH

VID

VIL

X

89H

4,5

VIH

VIL

VIL

VIH

VID

VIH

X

7CH
7DH

6,7,8

VIH

VIL

VIH

VIL

X

X

X

DIN

NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VpPH for Vpp.
3. See DC characteristics for VPPL, VPPH, VHH, VIO voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. Al-A17 = VIi..
5. Device 10 = 7CH for 28F002BX-TL and 7DH for 28F002BX-BL.
6. Refer to Table 4 for valid DIN during a write operation.
7. Commanil writes for Block erase or byte program are only executed when Vpp = VPPH.
8. Program or erase the Boot block by holding PWD at VHH.
9. PWD must be at GND ±0.2V to meet the 1.2/loA maximum deep power-down current.
10. The device 10 codes are identical to those of the 28F002BX 5V versions.

4.3.1.2 Input Control

4.3 Read Operations
The 2 Mbit flash family has three user read modes;
Array, Intelligent Identifier,and Status Register.
Status Register read mode will be discussed in detail
in the "Write Operations" section.
During power-up conditions (Vee supply ramping), it
takes a maximum of 700 ns from Vee at 3.0V minimum to obtain valid data on the outputs.
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode com'mand to the CUI. The 2 Mbit flash family has three
control functions, all of which must be 10gicall}'Jlctive, to obtain data at the outputs. Chip-Enable CE is
the device selection control. Power-Down PWD is
the device power control. Output-Enable DE is the
DATA INPUT/OUTPUT (00[0:15] or 00[0:7]) direction control and when active is used to drive data
from the selected memory on to the I/O bus.

With WE at logic-high level (VIH), input to the device
is disabled .. Data InputlO~ut pins (DQ[0:15] or
00[0:7]) are controlled by OE.
4.3.2 INTELLIGENT IDENTIFIERS
28F200BX-L Products'
The manufacturer and device codes are read via the
CUI or by taking the Ag pin to 12V. Writing 90H to
the CUI places the device into Intelligentldentifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, and location 00001H outputs the device code; 2274H for
28F200BX-TL, 2275H for, 28F200BX-BL. When
BYTE is ~t a logic low only the lower byte of the
above signatures is read and 0015/A-1 is a "don't
care" during Intelligent Identifier mode. A read array
command must be written to the CUI to return to the
read array mode.

4.3.1.1 Output Control
With OE at logic-high level (VIH), the output from the
device is disabled and data input/output pins
(00[0:15] or 00[0:7]) are tri-stated. Data input is
then controlled by WE. ,
3-209

28F200BX-TL/BL, 28F002BX-TL/BL

28F002BX-L Products

4.4.1 BOOT BLOCK WRITE OPERATIONS

The manufacturer and device codes EIre also read
via the CUI or by taking the Ag pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH
outputs the manufacturer's identification code, 89H,
and location 00001H outputs the device code; 7CH
for 28F002BX-TL, 7DH for 28F002BX-BL.

In the case of Boot Block modifications (write and
erase), PWD is set to VHH = 12V typically, in addition to Vpp at high Voltage. However, if PWD is not at
VHH when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, refer to
Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.

4.4 Write Operations

4.4.2 COMMAND USER INTERFACE (CUI)

Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply pOints the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full com.
mand set The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power supply
switchable,' available only when memory updates
are desired. The system designer can also choose
to "hard-wire" Vpp to 12V. The 2. Mbit flash family'is
designed to accommodate either design practice. It
is recommended that PWD be tied to logical Reset
for data protection during unstable CPU reset function as described in the. "Product Family Overview"
section.

The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write ,path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 ' Command Set
Command
Codes

Device Mode

00
10
20
40
50
70
90
BO
DO
FF

Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array

. 4.4.2.2 Command Function Descriptions
Device' operations are selected by writing specific
commands into the CUI. Table 4 defines the 2 Mbit
flash family commands.

3-210

intel .

28F200BX-TUBl, 28F002BX-Tl/Bl

Table 4. Command Definitions
Command

Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data
1

1

Write

X

Intelligent Identifier

3

2,4

Write

X

90H

Read

IA

liD

Read Status Register

.2

3

Write

X

70H

Read

X

SRD

Read Array

FFH

Clear Status Register

1

Write

X

50H

Erase Setup/Erase Confirm

2

5

Write

BA

20H

Write

BA

DOH

Word/Byte Write
Setup/Write

2

6, 7

Write

WA

40H

Write

WA

WD

Erase Suspend/Erase Resume

2

Write

X

BOH

Write

X

DOH

Alternate Word/Byte Write
Setup/Write

2

Write

WA

10H

Write

WA

WD

2,3,7

NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRO = Data read from Status Register.
4. 110 = Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
'
6. WA = Address to be written.
WO = Data to be written at location WA.
7. Either 40H or 10H commands is valid.
When writing commands to the device, the upper data bus [008-0015] = X (28F200BX-L-only) which is either Vcc or
VSS to avoid burning additional current.

a.

Invalid/Reserved

Read Status Register (70H)

These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel re- '
serves the right to redefine these codes for future
functions.

This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents ofthe status register, regardless of the address presented to the device.

Read Array (FFH)

The device automatically enters this mode after program or erase has completed.

This single write command points the read path at
the array. If the host CPU performs a CE/OE controlled read immediately following a two-write sequence that started the WSM,then the device will
output status register contents.' If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.

Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address AO is used in this mode, all
other address inputs are ignored).
3-211

Clear Status Register (SOH)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.

intet

28F200BX-TL/BL, 28F002BX-TL/BL

tinue to run, idling in the SUSPENO state, regardless
of the state of all input control pins, with the exclusionof PWO. PWO low will immediately shut down
the WSM and the remainder of the chip.

Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.

Erase Resume (DOH)

Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
'the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
. an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits· of the
Status Register to a "1", place the device into the
Read Array state, and wait for another command.
Erase Confirm (DOH)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE is toggled low. Status Register data can
only be updated by toggling either OE or CElow.
Erase Suspend (BOH)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been. executed, the CUI will initiate the WSM to suspend Erase operations, and then
return to responding to only Read Status Register or
to the Erase Resume commands. Once the WSM
has reached the Suspend state, it will set an output
into the CUI which allows the CUI to respond to the
Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other commands. The WSM will also
set the WSM Status bit to a "1 '!. The WSM will con-

This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
4.4.3 STATUS REGISTER
The 2 Mbit flash family contains a status register
which may be read to determine when a program or
erase operation is complete, and whether that operation completed successfully. The status register
may.be read at any time by writing the Read Status
command to the CUI. After writing this command, all
subsequent Read operations output data from the
status register until another command is written to
the CUI. A Read Array command must be written to
the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (xS) or wordwide (x16) mode for the 2SF200BX-L. In the wordwide mode the upper byte, 00[S:15] is set to OOH
during a Read Status command. In the byte-wide
mode, 00[S:14] are tri-stated and 001s/A-l retains the low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OE or CE
whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE or OE must be toggled with
each subsequimt status read, or the completion of a
program or erase operation will not be evident.

The Status Register is the interface between the microprocessor and. the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The. WSM sets
status bits "Three" through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five" .. These bits can only be
cleared by the controlling. CPU through the use of
the Clear Status Register command.

3-212

28F200BX-TL/BL, 28F002BX-TL/BL

4.4.3.1 Status Register Bit Definition
Table 5. Status Register DefinitIons

I

WSMS lESS
7

6

ES

PS

5

4

vP~s I
3

R
2

I

R

,R

o

NOTES:
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
• success.

SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
o = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed

When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command is issued.

SR5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase

When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify.

SR.4 = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program

When this bit is set to "1 ", WSM has attempted but failed
to Program a byte or word.

SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK

The Vpp Status bit unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM interrogates the Vpp level only after the byte write or block
erase command sequences have been entered and informs the system if Vpp has not been switched on. The
Vpp Status bit is not guaranteed to report accurate feedback between VPPL and VPPH.

SR2-SRO = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked out when polling the Status Register.

4.4.3.2 Clearing the Status Register

4.4.4 PROGRAM MODE

Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status regi,ster, or Intelligent Identifier.

Program is executed by a two-write sequence. The
Program Setup command is written to the CUI, followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. program the desired bits of the addressed memory word (byte), and
2. verify that the desired bits are sufficiently programmed.
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1 "s, there will be no
change of the memory cell content and no error occurs.

3-213

28F200BX-TL/BL, 28F002BX-TL/BL

Similar to erasure, the status register indicates
whether programming is complete. While -the program sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
toggling either CE or OE to determine when the program sequence is complete. Only the Read Status
Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If
Bit 3 is set then Vpp was not within acceptable limits,'
and the WSM will not execute the programming sequence.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot beaccomplished until the CUI is given the appropriate
. command. A Read Array command must first be given before memory contents can be read.
Figure 12 shows a system software flowchart for de- vice byte programming operation. Figure 13 shows a
similar flowchart for device word programming operation (28F200BX-L-only).
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A[12:16] for the
28F200BX-L or A[12:17] for the 28F002BX-L, identifying the block to be erased. These addresses are
latched internally when the Erase Confirm command
is issued. Block erasure results in all bits within the
block being set to "1'.'.
The WSM will execute a sequence of internally
timed events to:
1. program all bits within the block
2. verify that all bits within the block are sufficiently
programmed
3. erase all bits within the block and
4. verify that all bits within the block are sufficiently
erased
While the erase sequence is executing, Bit 7 of the
status register is a "0".
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.

If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit.5 of the status register is set to a "1" to indicate
an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 2 to 5
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase sequence at a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detailing the operation.
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE to VIH and the
active current is now a maximum of 6 mA. If the chip
is enabled while in this mode by taking CE to VIL, the
Erase Resume command can be issued to resume
the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in order to continue.

3-214

28f200BX-TL/BL, 28F002BX-TL/BL

4.4.6 EXTENDED CYCLING

Intel has designed i extended cycling capability into
its ETOX III flash memory technology. The 2 Mbit
flash family is designed for 10,000 program/erase

cycles on each of the five blocks. The combination
of low electric fields, clean oxide processing and
minimized oxide area per memory cell subjected to
the tunneling electric field, results in very high cycling capability.

Bus
Operation

Command

Comments

Write

Setup
Program

Data = 40H
Address = Byte to be
programmed

Write

Program

Data to be programmed
Address = Byte to be
programmed

Read

Status Register Data.
Toggle OE or CE to update
Status Register

Standby

Check SR.7
1 = Ready, 0 = Busy

Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.

Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290449-8

Full Status Check Procedure
Bus
Operation

Comments

Standby

Check SR.3
1 = V pp Low Detect

Standby

Check SRA
1 = Byte Program Error

vpp Range

Error

Byte Program
Error

Command

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.

290449-9

If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 12. Automated Byte Programming Flowchart

3-215

28F200BX-TL/BL, 28F002BX-TL/BL

Bus
Operation

Command

Comments

Write

Setup
Program

Data = 40H
Address = Word to be
programmed

Write

Program

Data to be programmed
Address = Word to be
'Programmed

Read

Status Register Data.
Toggle DE or CE to update
Status Register

Standby

CheckSR.7
1 = Ready, 0

= Busy

Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.

Write FFH after the last word programming operation to
reset the device to Read Array Mode.

290449-10

Full Status Check Procedure

Bus
Operation
Vpp Range

Error

Word Program

Error

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

CheckSR.4
1 = Word Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290449-11

SRA is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 13. Automated Word Programming Flowchart

3-216

infel~

28F200BX-TL/BL, 28F002BX-TL/BL

Bus
Operation

Command

Comments

Write

Setup
Erase

Data = 20H
Address = Within block to be
erased

Write

Erase

Data = DOH
Address = Within block to be
erased

Read

Status Register Data.
Toggle DE or CE to update
Status Register

Standby

CheckSR.7
1 = Ready, 0

= Busy

Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.

Write FFH after the last block erase operation to reset the
device to Read Array Mode.

290449-12

Full Status Check Procedure
Bus
Operation
Vpp Range

Error

Command Sequence
Error

Block Erase
Error

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Detect

Standby

Check SR.4,5
Both 1 = Command Sequence
Error

Standby

CheckSR.5
1 = Block Erase Error

SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290449-13
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
'
before full status is checked.
If error is detected, clear tbe Status Register before
attempting retry or other error recovery.

Figure 14. Automated Block Erase Flowchart
3-217

inteL

28F200BX-TL/BL, 28F002BX-TL/BL·

Bus
Operation

Write

Command

Erase
Suspend

Comments

Data = BOH

Read

Status Register Data.
Toggle OE or CE to update
Status Register

Standby

Check SR.7
1 = Ready

Standby

Check SR.6
1 = Suspended

Write

Read Array

Read array data from block
other than that being
erased.

Read

Write

Data = FFH

Erase Resume

Data = DOH

Figure 15. Erase Suspend/Resume Flowchart

4.5 Power Consumption
4.5.1 ACTIVE POWER
With CE at a logic-low level and PWD at a logic-high
level, the device is placed in the active mode. The
, de~ice Icc current is a maximum of 22 mA at 5 MHz.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power feature during active mode of' operation. The 2 Mbit
flash family of products incorporate Power Reduction Control (PRC) circuitry which basically allows
the device to put itself into a low current state when
it is not being accessed. After data is read from the

memory array, PRC logic controls the device's power consumption by entering the APS mode where
typical Icc current is 0.8 mA and maximum Icc current is 2 mA. The device stays in this static state with
outputs valid until a new memory location is read.
4.5.3 STANDBY POWER
With CE at a logic-high level {VI H), and the CUI in
read mode, the memory is placed in standby mode
where the maximum Icc standby current is 120 Il-A
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(DO[0:15] or 00[0:71) are placed in a high-impedance state independent of the status of the OE sig-

3-218

int:eL

28F200BX·TL/BL, 28F002BX·TL/BL

nal. When the 2 Mbit flash family is deselected during erase or program functions, the devices will continue to perform the erase or program function and
consume program or erase active power until program or erase is completed.

ory contents can only occur after successful completion of the two-step command sequences. Finally
the device is disabled until PWD is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.

4.5.4 DEEP POWER·DOWN

The 2 Mbit flash family supports' a typical lee of
0.2 /LA in deep power-down mode. One of the target
markets for these devices is in portable equipment
where the power consumption of the machine is of
prime importance. The 2 Mbit flash family has a
PWD pin which places the device in the deep powerdown mode. When PWD is at a logic-low (GND
± 0.2V), all circuits are turned off and the device typically draws 0.2 p.A of Vee current.
Doring read modes, the PWD pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a minimum of 700 ns to access valid data (tpHQV)'
During erase or program modes, PWD low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the PWD function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2 /LA current level.
PWD transitions to VIL or turning power off to the
device will clear the status register.

4.6 Power-Up Operation
The 2 Mbit flash family is designed to offer protection against accidental block erasure or programming during power transitions. Upon power-up the
2 Mbit flash family is indifferent as to which power
supply, Vpp or Vee, powers-up first. Power supply
sequencing is not required.
The 2 Mbit flash family ensures the CUI is reset to
the read mode on power-up.
In addition, on power-up the user must either drop
CE low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
active. Since both WE and CE must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level.of protection since alteration of mem-

4.7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
• Standby c~rrent levels (lees)
• Active current levels (lecR)
• Transient peaks produced by falling and rising
edges of CEo
Transient current magnitudes depend on the device
outputs' capacitive and induqtive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 p.F ceramic capacitor
connected between each Vce and GND, and between its Vpp and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS

Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
designer. The Vpp pin supplies the flash memory
cell's current for programming and erasing. One
should use similar trace widths and layout considerations given to the Vee power supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots.
4.7.2 Vee. Vpp AND PWD TRANSITIONS

The CUI latches commands as issued by system
software and is not altered by Vpp or CE transitions
or WSM actions. Its state upon power-up, after exit
from deep power-down mode or after Vce transitions below VLKO (Lockout voltage), is Read Array
mode.
After any word/byte write or block erase operation is
complete and even after Vpp transitions down to
VPPL, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.

3-219

int:et

28F200BX-TL/BL, 28F002BX-TL/BL

5.0 OPERATING SPECIFICATIONS

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.

Absolute Maximum Ratings
Operating Temperature
During Read .................... O°C to 70°C(1)
During Block Erase and
Word/Byte Write ................... O°C to 70°C
Storage Temperature .......... - 65°C to

+ BO°C
+ 125°C

Voltage on Any Pin
(except Vee and Vpp)
with Respect to GND ........ -2.0V to

+ 7.0V(2)

Temperature Under Bias ......... -1 O°C to

• WARNING: StreSSing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Voltage on Pin PWD or Pin Ag
with Respect to GND ....... - 2.0V to 13.5V(2, 3)
Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... -2.0V to

+ 14.0V(2, 3)

Vee Supply Voltage
with Respect to GND ........ -2.0V to

+ 7.0V(2)

Output Short Circuit Current ............. 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns.
Maximum De voltage on input/output pins is Vcc + O.SV which, during transitions, may overshoot to Vcc + 2.0V for
periods < 20 ns.
3. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Ae Specifications are valid at both voltage ranges. See De eharacteristics table for voltage range-specific specifications.

OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Unit

0

70

DC

TA

Operating Temperature

Vee

Vee Supply Voltage

5

3.00

3.60

Vee

Vee Supply Voltage

5

4.50

5.50

D.C. CHARACTERISTICS
Symbol

Notes

,

V
V

Vee = 3.3V ±0.3V

Parameter

Max

Unit

III

Input Load Current

1

±1.0

/1- A

Vee = Vee Max
VIN = Vee or GND

ILa

Output Leakage Current

1

±10

/1- A

Vee = Vee Max
VOUT = Vee or GND

lees

Vee Standby Current

45

120

/1- A

Vee = Vee Max
CE = PWD = Vee ±0.2V

45

120

/1- A

Vee = Vee Max
CE = PWD = VIH

0.20

1.2

/1- A

PWD

leeD

Vee Deep Power-down Current

Notes

Min

1,3

1

3-220

Typ

Test Condition

=

GND ±0.2V

intet

28F200BX-TL/BL, 28F002BX-TL/BL

D.C. CHARACTERISTICS
Symbol
leeR

leeR

vee = 3.3V ±0.3V (Continued)

Parameter

Notes

Vee Read Current for
28F200BX-L Word-Wide Mode

1,5,
6

Vee Read Current for
28F002BX-L Byte-Wide Mode

Min

Typ

1,5,6

Max

mA Vee = Vee Max, CE = GND
f = 5.MHz, lOUT = 0 mA
CMOS Inputs

22

mA Vee = Vee Max, CE = VIL
f = 5 MHz, lOUT = 0 mA
TTL Inputs

20

mA Vee = Vee Max, CE = GND
f= 5 MHz, lOUT = mA
CMOS Inputs

20

mA Vee = Vee Max, CE = VIL
f = 5 MHz, lOUT = 0 mA
TTL Inputs
mA Word Write in Progress

Vee Word Write Current

1

30

leew

Vee Byte Write Current

1

30

leCE

Vee Block Erase Current

1

20

leCES

VCC Erase Suspend Current

3

Test Condition

22

Icew

1,2

Unit

6

mA Word/Byte Write in Progress
"mA Block Erase in Progress
mA Block Erase Suspended,
CE = VIH

IpPS

Vpp Standby Current

1

±10

iJ- A Vpp:::; Vee

Ippo

Vpp Deep Power'down Current

1

5.0

iJ- A

PWD = GND ± 0.2V
Vpp> Vee

IpPR

Vpp Read Current

1

200

iJ-A

Ippw

Vpp Word Write Current

1

40

mA Vpp = VPPH
Word Write in Progress

Ippw

Vpp Byte Write Current

1

30

mA Vpp = VPPH
Byte Write in Progress

IpPE

Vpp Block Erase Current

1

30

mA Vpp = VPPH
Block Erase in Progress

IpPES

VPP Erase Suspend Current

1

200

iJ- A Vpp = VPPH
Block Erase Suspended

110

Ag Intelligent Identifier Current

1

VID

Ag Intelligent Identifier Voltage

11.4 12.0

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

VPPL

VPP during Normal Operations

0.0

4.1

V

VPPH

VPP during Erase/Write
Operations

11.4 12.0

12.6

V

VLKO

Vee Erase/Write Lock Voltage

2.0

VHH

PWD Unlock Voltage

11.4 12.0

500

iJ-A

13.0

V

-0.5

0.6

V

2.0

Vee+ 0.5

V

0.4

V

Vee = Vee Min
IOL =.2mA

V

Vce = Vee Min
IOH = -2mA

2.4
3

3-221

Ag = VIO

V
13.0

V

Boot Block Write/Erase

iniaL

28F200BX-TL/BL, 28F002BX-TL/BL

CAPACITANCE(4)
Symbol

TA = 25°C, f = 1 MHz

Parameter

Typ

Max

Unit

Condition

=

CIN

Input Capacitance

6

8

pF

VIN

COUT

Output Capacitance

10

12

pF

VOUT

OV

=

OV

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 3.3V, VPP = 12.0V, T = 25'e. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when VPP = VpPL and not guaranteed in the range between VPPH and
VPPL·
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 2 mA in static operation.
6. CMOS Inputs are either VCC ±0.2V or GND ±0.2V. TTL Inputs are.either VIL or VIH.

D.C. CHARACTERISTICS Vee
Symbol

= 5.0V ±10%(4)

Max

Unit

III

Input Load Current

1

±1.0

rnA

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

rnA

Vee = Vee Max
VOUT = Vee or GND

lecs

Vec Standby Current

1.5

/LA

Vee = Vee Max
CE = PWD = VIH

100

/LA

Vee = Vee Max
CE = PWD = Vee ±0.2V

Parame.ter

Notes

Min

Typ

Test Condition

=

leCD

Vee Deep Power-down
Current

1

1.2

/LA

PWD

lecR

Vce Read Current for
28F200BX-L Word-Wide
Mode

1

45·

rnA

Vec = Vee Max, CE = GND
f = 5 MHz, lOUT = 0 rnA
CMOS Inputs

45

rnA

Vee = Vee Max, CE = VIL
f = 5 MHz, lOUT = 0 rnA
TTL Inputs

40

rnA

Vee = Vee Max, CE = GND
f = 5 MHz, lOUT = 0 rnA
CMOS Inputs

40

rnA

Vee = Vee Max, CE = VIL
f = 5 MHz, lOUT = 0 rnA
TTL Inputs

leeR

Vee Read Current for
28F200BX-L Byte-Wide
Mode

1

GND. ±0.2V

leew

Vee Word Write Current

1

70

rnA

Word Write in Progress

leew

Vee Byte Write Current

1

60

rnA

Byte Write in Progress

IeeE

Vee Block Erase Curre!')t

leeES

Vee Erase Suspend Current

Ipps
IpPD

1

30

rnA

Block Erase in Progress

1,2

10

rnA

Block Erase Suspended,
CE = VIH

Vpp Standby Current

1

±10

/LA

Vpp:S;; Vee

Vpp Deep Power-down
Current

1

5.0

/LA

PWD

3-222

=

GND ±0.2V

infel~

28F200BX-TL/BL, 28F002BX-TL/BL

D.C. CHARACTERISTICS vcc
Symbol

= 5.0V ±10% (Continued)

Parameter

Notes

Min

Typ

Max

Unit

IpPR

VPP Read Current

1

200

/-t A

Vpp

Ippw

VPP Word Write Current

1

40

mA

Vpp = VPPH
Word Write in Progress

Ippw

VPP Byte Write Current

1

30

mA

Vpp = VPPH
Byte Write in Progress

IpPE

VPP Block Erase Current

1

30

mA

VPP = VPPH
Block Erase in Progress

IpPES

VPP Erase Suspend Current

1

200

/-t A

VPP = VPPH
Block Erase Suspended

VIL

Input Low Voltage

-0.5

0.8

V

2.0

VCC+ 0.5

V

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

VPPL

VPP during Normal Operations

VPPH

VPP during Erase/Write
Operations

VLKO

Vcc Erase/Write Lock Voltage

2.2

VHH

PWD Unlock Voltage

11.4

.0.45
2.4
3

0.0
11.4

Test Condition

>

Vcc

V

VCC = VCC Min
IOL = 5.8 mA

V

Vee = VCC Min
IOH = -2.5 mA

6.5

V

12.0

12.6

V

12.0

13.0

V
V

Boot Block Write/Erase

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T = 25·C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erase/Byte Writes are inhibited when VPP =' VPPL and not guaranteed in the range between VPPH and VPPL'
4. All parameters are sampled, not 100% tested.

A.C. INPUT/OUTPUT REFERENCE WAVEFORM

A.C. TESTING LOAD CIRCUIT
2.;3':::'

-.... lN914
3.0
0.0

1.5INPUTX_TEST:+NTS~Xl.5 OUTPUT

Rt.
290449-15

A.C. test inputs are driven at 3.0V for a Logic "1" and O.OV for a logic "0".
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
(10% to 90%) < 10 ns.

DEVICE
UNDER
TEST

OUT

1.'- 1-

29044~-16

CL = 50 pF
CL Includes Jig Capacitance
RL = 3.3 KO

3-223

28F200BX-TL/BL, 28F002BX-TL/BL

A.C. CHARACTERISTIC5-Read-Only Operations(1) vcc=
Versions
Symbol
tAVAV
tAVQV
tELQV

tRC
tACC
' tCE

3.3V ±0.3V, 5.0V ±10%(3)

28F200BX-L 150
28F002BX-L 150

Parameter

Notes

Read Cycle Time

Min
150

Address to Output Delay

2

CE to Output Delay

Unit

Max
ns
150

ns

150

ns

700

ns

65

ns

tpHQV

tpWH

PWD High to Output Delay

tGLQV

tOE

OE to Output Delay

2

tELQX

tLZ

CE to Output Low Z

3

tHZ

CE High to Output High

tGLQX

toLZ

OE to Output Low Z

3

tGHQZ

tDF

OE High to Output High Z

3

tOH

Output Hold from Addresses,
CE or OE Change,
Whichever is First

3

tELFL
tELFH

CE to BYTE Switching
Low to High

3

5

ns

tFHQV

BYTE Switching High
to Valid Output Delay

3,4

150

ns

tFLQZ

BYTE Switching Low
to Output High Z

3

45

ns

tEHQZ

Z

..

0

ns
55

3
0

ns
ns

45
0

ns
ns

NOTES:

1. See A.C. Input/Output Reference Waveform for timing measurements.
2. OJ: may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. tFLOV. BYTE switching low to valid output delay will be equal to tAVOV. measured from the time DQ1S/A-1 becomes
valid.

3-224

Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

VIH

STANDBY

-

ADDRESSES (A)

-

-

~I

Vee POWER-DOWN

'1II111....;..,_.,................_--~

l
8

ADDREsses STABLE
VIL
I\)

,.

1·1

IAVAV

CCI

~

VIH

Q
Q

!'!I
u:a

VIL

=
.!t
C

....

VIH

.r

CE

(E)

...CD
C

SJI

~

OE

m
I\)

CCI
."

(G)

P
:E

Q

VIL

Q
I\)

m

~

....
0

CD
to:)

~

I\J
U1

...

:I

~

VIH

WE

C
m
r-

(W)

III

....
0

VIL

...

'oH

:II

CD

DI

VIH

Do

0

'0

HIGH Z

DATA (D/Q)

...
CD

Io_------

VIL

~

VALID OUTPUT

0

I AVQV

HIGH Z

~

.,

:::s

I/J,

~

5.0V
Vee
GND

~

~
{§!

©

J

Iiiiil
0=

tpHQV

~

,I

"iii)

\

PWD (p)

@

:w
~
~

VIL

290449-17

e::J

©
~

intel~

28F200BX-TL/BL, 28F002BX-TL/BL

V'H

ADDRESSES (A)

ADDRESSES STABLE

V'L
t,.,VAV

V'H

FE

(e)
V'L
IAVPL = '<

V1H

.......

<
CD

~

..,0
3

1/1

..,0

OE

r-

m

.r

(G)
V1L

N

QI)

I-

AI

..::e
::::!.

c.:l

N
I\J
co

CD
Dl
::I
Il.

tWHQV1.2,3,4

•

."

o
o

I

V1H

N

WE (w)

m

><

V1L

~

r-

.......

..,m

AI
1/1

CD

0

'g

CD

iiJ

m
r-

VIH
DATA (D/a)
VIL

=
0
::I
1/1

~I(,
0

a..,

2-

~

..::e

::::!.
CD

!!!,

~

~

S.5V
VIH

~

©

PWD (p)
VIL

CD

Il.

©

VHH

VpPH

IiiiiI

i--l

~

tVPWH

'1iil

©

VpPL
VPP (V) V1H

a:eJ
~

V1L

C:::J

~

290449-18

©
~

int:eL

28F200BX·TL/BL, 28F002BX·TL/BL

A.C. CHARACTERISTICS FOR CE·CONTROLLED WRITE OPERATIONS
vcc = 3.3V ±0.3V, 5.0V ±10%
28F200BX.L 150
28F002BX·L 150

Versions
Parameter

Symbol

Notes

Min

Unit

Max

150

ns

1

p,s

0

ns

200

ns

tAVAV

twc

Write Cycle Time

tpHEL

tps

PWD High Recovery to CE Going Low

tWLEL

tws

WE Setup to CE Going Low

tpHHEH

tpHS

PWD VHH Setup to CE Going High

6,8

. tVPEH

tvps

Vpp Setup to CE Going High

5,8

200

ns

tAVEH

tAS

Address Setup to CE Going High

3

95

ns

tOVEH

tos

Data Setup to CE Going High

4

100

ns

tELEH

tcp

CE Pulse Width

100

ns

tEHOX

tOH

Data Hold from CE High

4

0

ns

tEHAX

tAH

Address Hold from CE High

3

10

ns

tEHWH

tWH

WE Hold from CE High

10

ns

tEHEL

tCPH

CE Pulse Width High

50

ns

2,5,6

6

p,s

tEHQV1

Duration of Word/Byte Programming
Operation (Boot)

tEHQV2

Duration of Erase Operation (Boot)

2,5,6

0.3

s

tEHQV3

Duration of Erase Operation (Parameter)

2,5,6

0.3

s

tEHQV4

Duration of Erase Operation (Main)

2,5,6

0.6

s

tQWL

tVPH

Vpp Hold from Valid SRD

5,8

0

ns

tQVPH

tpPH

PWD VHH Hold from Valid SRD

6,8

0

tpHBR

,

7

Boot-Block Relock Delay

ns
200

ns

NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE in systems where CE
defines the write pulse-width (within a longer WE timing waveform), all set-up, hold and inactive WE time should be measured relative to the CE waveforms.
2, 3, 4, 5, 6, 7, 8: Refer to At characteristics for WE-controlled write operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
.
characteristics during read mode.

3-230

_.

Vee POWER-UP
WRITE PROGRAM OR
"STANDBY
ERASE SETUP COMMAND

J!
cc

c

iil
.....

!D

»

;...
::J

III

~

1>
P

f
o

3
0...
III

cu

:e~

CJ.)

III

r\:>

.....

WRITE
VALID ADDRESS" DATA (PROGRAM)
OR ERASE CONFIRM COMMAND

AUTOMATED PROGRAM
OR ERASE DELAY

READ STATUS
REGISTER DATA

l

WRITE READ ARRAY
COMMAND

@

VIH
ADDRESSES (A)
VIL

N

(II)

."
N

VIH

o
o

WE (w)

III

VIL

X
~
r
......

VIH

III

VIL

rN

VIH

o
o

DE (G)

(II)

."
N

IT (E)

III

~

VIL

r
......

CD

::J
Q.

'"iil
III

CD

o

III

r

VIH
DATA (D/a)

VIL

~

"0

...CD

g.
::J

III

~I

oo
a
2iD

(§

~

VHH

~

6.5V
VIH

©

PWD (p)

IiiiiI

VIL

~

IVPEH

'iii!

VpPH

©

Q.

:e

VPP (V)VPPL
VIH

.!!!.

VIL

3:
CD

2&
~
~

,N\/\t\MN\/YY\/\

C::{]
290449-19

©
~

28F200BX-TL/BL, '28F002BX-TL/BL

ORDERING INFORMATION

IElzlslFlololzlBlxl-ILll15lol
PACKAGE
E = STANDARD 56 LEAD TSOP
PA = 44 LEAD PSOP

~ ACCESS SPEED (ns)

~

150 ns

PACKAGE
E = STANDARD 40 LEAD TSOP

150 ns

290449-21

290449-20

VALID COMBINATIONS:
E28F002BX·L 150

VALID COMBINATIONS:
E28F200BX·L 150 PA28F200BX·L 150

Additional Information
28F200BX/28F002BX Datasheet
28F400BX/28F004BX Datasheet
28F400BXLl28F004BXL Datasheet

Order Number
290448
290451
290450

Ap·363 "Extended Flash BIOS Design for Portable Computers"
Ap·357 "Power Supply Solutions for Flash Memo~"
ER·28 "ETOX·III Flash Memory Technology"
ER-29 "The Intel 2/4 Mbit Boot Block Flash Memory Family"

292098
292092
294012
294013

REVISION HISTORY
Number

~ ACCESS SPEED (ns)

Description

·001

Original Version

-002

Modified BYTE AC Timings
Modified tovwH parameter
for AC Characteristics
for Write Operations

3·232

28F400BX-T/B,28F004BX-T/B
4 MBIT (256K x16, 512K x8) BOOT BLOCK FLASH
MEMORY FAMILY
• xS/x16 Input/Output Architecture
- 2SF400BX-T, 2SF400BX-B
- For High Performance 'and High
Integration 16-bit and 32-bit CPUs

•

Very High-Performance Read
- 60/S0 ns Maximum Access Time
- 30/40 ns Maximum Output Enable
Time

• xS-only Input/Output Architecture
- 2SF004BX-T, 2SF004BX-B
- For Space Constrained S-bit
Applications

•

Low Power Consumption
- 20 rnA, Typical xS Active Read
Current
-25 rnA Typical x16 Active Read
Current

•

Deep Power-Down/Reset Input
- 0.2 p.A Icc Typical
- Acts as Reset for Boot Operations

• Optimized High Density Blocked
Architecture
-One 16 KB Protected Boot Block
- Two S KB Parameter Blocks
- One 96 KB Main Block
-Three 12S KB Main Blocks
- Top or Bottom Boot Locations
•

Extended Cycling Capability
-100,000 Block Erase Cycles

• Automated Word/Byte Write and Block
Erase
- Command User Interface
- Status Registers
- Erase Suspend Capability

• Extended Temperature Operation
- - 40°C to + S5°C
• Write Protection for Boot Block
• Hardware Data Protection Feature
- Erase/Write Lockout During Power
Transitions
•

Industry Standard Surface Mount
Packaging
- 2SF400BX: JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
- 2SF004BX: 40-Lead TSOP

•

12V Word/Byte Write and Block Erase
-Vpp = 12V ±5% Standard
- Vpp = 12V ± 10% Option

•

ETOXTM III Flash Technology
-5V Read

• SRAM-Compatible Write Interface
• Automatic Power Savings Feature
- 1 rnA Typical Icc Active .current in
Static Operation

3-233

November 1992
Order Number: 290451·002

infel"

28F400BX-T/B,28F004BX-T/B

Intel's 4. Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes blockselective erasure, automated write and erase operations and standard microprocessor interface. The 4 Mbit
Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input!
output control, very high speed, low power, an industry standard ROM compatible pinout and surface mount
packaging. The 4 Mbit flash family is an easy upgrade from Intel's 2 Mbit Boot Block Flash Memory Family.
The Intel 28F400BX-T/B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either 8-bitor 16-bit applications. The 28F400BX-T and 28F400BX-B are
4,194,304-bit non-volatile memories organized as either 524,288 bytes or 262, 144 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
'
standard ROM IE PROM pinout.
The Intel 28F004BX-TIB are 8-bit wide flash memories with 4,194,304 bits organized as 524,288 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
wordlbyte write and block erasure. The 28F400BX-T128F004BX-T provide block locations compatible with

Intel's MCS-186 family, 80286, i386™, i486™, i860™ and 80960CA microprocessors. The 28F400BX-BI
28F004BX,S provide compatibility with Intel's 80960KX and 80960SX families as well as other embedded
microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 60 ns, these 4 Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down
mode lowers the total Vee power consumption to 1 p,W. This is critical in handheld battery powered systems.
For very low power applications using a 3.3V supply, refer to the Intel 28F400BX-T IB, 28F004BX-TIB 4 Mbit
Boot Block Flash Memory Family datasheet.
Manufactured on Intel's 0.8 micron ETOXTM III process, the 4 Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4 Mbit density level.

3-234

28F400BX· T IB, 28F004BX·T IB

1.0

44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4. The
28F004BX products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.

PRODUCT FAMILY OVERVIEW

Throughout this datasheet the 28F400BX refers to
both the 28F400BX-T and 28F400BX-B devices and
28F004BX refers to both the 28F004BX-T and
28F004BX-B devices. The 4 Mbit flash memory family refers to both the 28F400BX and 28F004BX products. This datasheet comprises the specifications for
four separate products in the 4 Mbit flash memory
family. Section 1 provides an overview of the 4 Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F400BX and 28F004BX products respectively.
Section 4 combines a description of the' family's
principles of operations. Finally Section 5 describes
the family's operating specifications.
Product Family
X8/X16 Products

X8-0nly Products

28F400BX-T

28F004BX-T

28F400BX-B

28F004BX-B

The Command User Interface (CUI) serves 'as the
interface between the microprocessor or microcontroller and the internal operation of the 28F400BX .
and 28F004BX flash products.
Program and Erase Automation allows program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
.' Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
. and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed.in word or
byte increments for the 28F400BX family and in byte
increments for the 28F004BX family typically within
9
which is a 100% improvement over current
flash memory products.

""S

The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.

1.1 Main Features
The 2BF400BX/28F004BX boot block flash memory
family is a very high performance 4 Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144, words) of 16 bits each or 512 KBytes
(524,288 bytes) of 8 bits each.
Seven Separately Erasable Blocks including a
Hardware-Lockable boot block (16,384 Bytes),
Two parameter blocks (8,192 Bytes each) and
Four main blocks (1 block of 98,304 Bytes and 3
blocks of 131,072 Bytes) are included on the 4 Mbit
family. An erase operation erases one of the main
blocks in typically 2,4 seconds and the boot or parameter blocks in typically 1.0 seconds independent
of the remaining blocks. Each block can be independently erased and programmed 100,000 times.
The Boot Block is located' at either the top
(28F400BX-T, 28F004BX-T) or the bottom
(28F400BX-B, 28F004BX-B) of the address map in
order to accommodate different microprocessor protocols for boot code location. The hardware lockable boot block provides the most secure code storage. The boot block is intended to store the kernel
code required for booting-up a system. When the
PWD pin is between 11,4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the PWD pin is at or below 6.5V
the boot block is locked and program and erase operations to the boot block are ignored.

Maximum Access Time of 60 ns (TACC) is achieved
over the commercial temperature range (O°C to
70°C), 5% Vee supply voltage range (4.75V to
5.25V) and 30 pF output load. Maximum Access
Time of 70 ns (TACC) is achieved over the commercial temperature range, 10% Vee supply range (4.5V
to 5.5V) and 100 pF output load.
Ipp maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation. Ipp Erase
current is 30 mA maximum. Vpp erase and programming voltage is 11.4V to 12.6V (Vpp = 12V
± 5%) under all operating conditions. As an option, Vpp can also vary between 1O.8V to 13.2V (Vpp
= 12V ± 10%) with a guaranteed number of 100
block erase cycles.
Typical Icc Active Current of 25 mA is achieved
for the X16 products (28F400BX). Typical Icc Ac·
tive Current of 20 mA is achieved for the X8 products (28F400BX, 28F004BX). Refer to the Icc active
current derating curves in this datasheet.

The 4 Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allows for
very low power designs. Once the device is accessed to read array data, APS mode will immediately put the memory in static mode of operation
where Icc active current is typically 1 mA until the
next read is initiated.

The 28F400BX products are available in the ROMI
EPROM compatible pinout and housed in the
3-235

28F400BX-T IB, 28F004BX-T IB

When the CE and PWD pins are at Vee and the
BYTE pin (28F400BX-only) is at either Vee or GND
the CMOS Standby mode is enabled where Icc is
typically 50 p.A.
A Deep Power-Down Mode IS enabled when the
PWD pi'; is at ground minimizing power consumption
and providing write protection during power-up con-,
ditions. Icc current during deep power-down mode
is 0.20 p.A typical. An initial maximum access time
or ,Reset Time of 300 ns is required from PWD
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User' Interface are recognized. When PWD is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system. Reset
pin can be tied to PWD to reset the memory to normal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
4 Mbit family and the PWD functionality for data protection, when the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until PWD returns to its normal
state.
'
For the 28F400BX" Byte-wide or Word-wide Input/Output Control is possible by controlling the
BYTE pin. When ,the BYTE pin is at a logic low the
device is in the byte-wide mode (x8) and data is read
and written through 00[0:7]. During the byte"wide
mode, 00[8:14] are tri-stated and D015/A-1 becomes the lowest order address pin. When the
BYTE pin is at a logic high the device is in the wordwide 'mode (x16) anl:l, oata is read and written
through 00[0:15].

1_2 ' Applications
The 4 Mbit boot block flash family combines high
density, high performance, cost-effective ,flash memories with blocking and hardware protection capabilities. Its flexibility and versatility will reduce costs
througl:lout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component
handling during the production phase.
During the, product life cycle, when code updates or
feature enhancements become necessary, flash
memory will reduce the update costs by allowing ei-

ther a user-performed code change via floppy disk
or a remote code change via a serial link. The 4 Mbit
'boot block flash family provides full function,
blocked flash memories suitable for a wide range of
applications. These, applications include Extended
PC BIOS and ROM-able applications storage, Digital Cellular Phone program and data storage, Telecommunication boot/firmware; Printer firmware/
font storage and various other embedded applications where both program and data storage are required.
Reprogrammable systems such as personal computers, are ideal applications for the 4 Mbit flash
products. Portable and handheld personal computer '
applications are becoming more complex with the
addition of power management software to take advantage of the latest microprocessor technology,
the availability of ROM-based application software,
pen tablet code for electronic hand writing, and diagnostic code. Figure 1 shows an example of a '
28F400BX-T application.
This increase' in, software sophistication augments
the probability that a code update will be required,
after the PC is shipped. The 4 Mbit flash products
provide an inexpensive update solution for the notebook and handheld personal computers while extending their, product lifetime. Furthermore, the
4 Mbit flash products' power-down mode provides
added flexibility for these batterY-operated portable
designs which require operation, at very low power '
levels.
'
The 4 Mbit flash products also provide excellent design solutions for Digital Cellular Phone and Telecommunication switching applications requiring high
'performance, high density storage capability cou-,
pled with modular software deSigns, and a small
form factor package (X8-only bus). The 4 Mbit's
blocking scheme allows for an easy segmentation ,of
the embedded code with; 16 Kbytes of HardwareProtected Boot code, 4 Main Blocks of program
code and 2 Parameter Blocks of 8 Kbytes each for
,frequently updatable data storage and d,agnostic
messages (e.g., phone numbers, authorization
codes). Figure 2 is an example of such an application with the 28F004BX"T.
These are a few actual ,examples of the wide range
of applications for the 4 Mbit Boot Block flash memory family which,enable system designers achieve
the best possible product deSign. Only your imagination limits the applicability of such a versatile product
family.

3-236

int'el..

28F400BX·T/B, 28F004BX·T/B

12V

82360SL
Conlroller

GPIO~*,~

. _.

XD7

RESET~
.

I

Vpp
Swilch

Vpp

5V
80386SL

+5V

GPIO

ROMI6/8

290451-4

Figure 1. 28F400BX Interface to INTEL386SLTM Microprocessor Superset

I\.

A,6:1S

As-A,s
ALE
ADo-A~

80C188EB

~

rru

UCS '

"

T I\.

1[

Pl.X

ADDRESS
LATCHES
LE

ADDRESS
LATCHES
LE

~
~

r-ll'

DOc-DO, Ao-A,s

CE
Vpp
GENERATOR

I

PWD

WE

Rii

OE

L

SYSTEM RESET

28FOO4BX-T

Vpp

WR

RESIN

-~ 7

*-

290451-24

Figure 2. 28F004BX Interface to,INTEL 80C188EB 8·Bit 'Embedded Microprocessor

3·237

intel~

28F400BX-T/B,28F004BX-T/B

1.3 Pinouts
The 28F400BX 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in
Figure 3. Furthermore. the 28F400BX 56-Lead
TSOP pinout shown in Figure 4 provides density upgrades to future higher density boot block memories.

. The 28F004BX 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density
upgrade for the 2 Mbit Boot Block flash memory or
the 28F002BX.

27C4OO

27C400

NC
NC
A17
A7
A6
A5
A4
A3
A2
A1
Ao
CE
GND
OE
DOo
DOs
D01
D09
D02
D010
D03
D011

vpp

DO.

NC
NC
As
A9
A10
Al1
A12
A13
A14
A15
A16
BYTElVpp
GND
D015/A -1
D07 .
D014
D06
D013
D05
D012
D04

Vee

Vee

FWD

DU

WE

A,7

A8

A7

As

As
As

A"

A.

A,2

A3

A,3

A2
A,

Ao
CE
GND

DE

A,o

PA28F400BX
44 LEAD PSOP
0.525" X 1.110"
TOP VIEW

A,.
A,s
A,6
BYTE
GND
DQ,s/A..,
. D~

000
DQs

DQ,.

DQ,

DOs

DOg

0°,3
DQs

DQ2
0°,0
DQ3

DQ"2

DO"

290451-25

Figure 3. PSOP Lead Configuration for x8/x16 28F400BX

3-238

int'et

28F400BX-T IB, 28F004BX-T IB

Ne

A,.

BYTE
GNO
OQ'5/A..,

DC?

00104

DOg

28F400BX
56-LEAD TSOP
14mm x 20mm
TOP VIEW

OQ'3
OQ5
OQ12
OQ,

Vee
Vee

DO, ,
003
OQ10
OQ 2

DOg
OQ,

DOg

000

m:

290451-3

Figure 4. TSOP Lead Configuration for x8/x16 28F400BX

A,7
GNO
Ne
Ne

A,o

OOJ

28F004BX
40-LEAD TSOP
10mm x 20mm
TOP VIEW

DOg
OQ5
OQ,

Vee
Vee
Ne
OQ3
OQ2

00,

000
Ol'

290451-20

Figure 5. TSOP Lead Configuration for x8 28F004BX

3-239

28F400BX-T/B,28F004BX-T/B
1.4 28F400BX Pin Descriptions
Symbol

Name and Function

Type

Ao-A17

I

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write
cycle.

Ag

I

ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this mode Ao
decodes between the manufacturer and device ID's. When BYTE is at a logic low only the
lower byte of the signatures are read. DQ15/ A-l is a don't care inthe signature mode when
BYTE is. low.

DQo-DQ7

110

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle durin~
program command. Inputs commands to the command user interface when CE and WE are.
active. Data is internally latched during the write and program cycles. Outputs array,
intelligent identifier and Status Register data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled.

DQa-DQ15

110

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle during a
program command. Data is internally latched during the write arid program cycles. Outputs
array data. The data pins float to tri-state when the chip is deselected or the outputs are
disabled as in the byte-wide mode (BYTE = "0"). In the byte-wide mode DQ15/ A-l
becomes the lowest order address for data output on DQO-DQ7.

CE

I

CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense
amplifiers. CE is active low; CE high deselects the memory device and reduces power
consumption to standby levels. If CE and PWD are high, but not ata CMOS high level, the
standby current will increase due to current flow through the CE and PWDinput stages.

PWD

I

POWER-DOWN: Provides three-state control. Puts the device in deep power-down mode.
Locks the boot block from program/erase.
When PWD is at logic high level and equals 6.5V maximum the boot block is locked and
cannot be programmed or erased.
When PWD = 11.4V minimum the boot block is unlocked and can be programmed or
erased.
When PWD is at a logic low level theboot block is locked, the deep power-down mode is
enabled and the WSM is reset preventing any blocks from being programmed or erased,
therefore providing data protection during power transitions.
PWD terminates any internally timed erase or program activities when it is taken to a logic
low. PSD activates the CE input stage and requires 300 ns recovery time to transition from
deep powerdown to valid data on the outputs or 215 ns delay before the device can
recognize valid inputs.

OE

I

OUTPUT ENABLE: Gates the device's outputs through th~ data buffers during a read cycle.
OE is active low.

WE

I

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE is active
low. Addresses and data are latched on the rising edge of the WE pulse.

BYTE

I

BYTE ENABLE: Controls whether the device operates in the byte-wide mode (x8) or the
word-wide mode (x16). BYTE pin must be controlled at CMOS levels to meet 1 OOA CMOS
current in the standby mode. BYTE = "O"enables the byte:wide mode, where data is read
,
and programmed on DQo-DQ7 and DQ15/ A -1 becomes the lowest order address that
decodes between the upper and lower byte. DQe-DQ14 are tri-stated during the byte-wide
mode. BYTE = "1" enables the word-wide mode where data is read and programmed on
DQO-DQ15·

Vpp

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming
data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.

Vee

DEVICE POWER SUPPLY (5V ± 10%, 5V ± 5%)

GND

GROUND: For all internal circuitry.

NC

NO CONNECT: Pin may be driven or left floating.

DU

DON'T USE PIN: Pin should not be connected to anything.

3-240

int'et

28F400BX·T IB, 28F004BX·T IB

1.5 28F004BX Pin Descriptions
Symbol

Type

Name and Function

Ao-A1B

I

ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.

A9

I

ADDRESS INPUT: When A9 is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.

I/O

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle'
during a program command. Inputs commands to the command user interface when
CE and WE are active. Data is internally latched during the write and program
cycles. Outputs array, intelligent identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.

CE

I

CHIP ENABLE: Activates the.device's control logic, input buffers, decoders and
sense amplifiers. CE is active low; CE high deselects the memory device and
reduces power consumption to standby levels. If CE and PWD are high, but not at a
CMOS high level, the standby current will increase due to current flow through the
CE and PWD input stages.

PWD

I

POWER DOWN: Provides Three-State control. Puts the device in deep power-down
mode. Locks the Boot Block from program/erase.

DOo-D07

When PWD is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
When PWD = 11.4V minimum the Boot Block is unlocked and can be ~rogrammed
or erased.
When PWD is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power transitions.
PWD terminates any internally"!!med erase or program activities when it is taken to a
logic low. PWD activates the CE input stage and requires 300 ns recovery time to
transition from deep power-down to valid data on the outputs or 215 ns delay before
the device can recognize valid inputs.
OE

I

OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE is active low.

WE

I

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE is
active low. Addresses and data are latched on the rising edge of the WE pulse.

Vpp

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
NOTE: Vpp < VPPLMAX memory contents cannot be altered.

Vee
GND
NC
DU

DEVICE POWER SUPPLY (SV ± 10%, SV ±S%)
GROUND: For all internal circuitry .
. NO CONNECT: Pin may be driven or left floating.
DON'T USE PIN: Pin should not be connected to anything.

3-241

N

b

N

Q)

_.

::::J

c[
8

"II
~
0
0

r------DOa -:.DOts /A.. 1

OJ

><

:e
0
::u

C
.....

!!
c

co

OJ

-<

ill

BYTE

!»

-N
01

....

~

....

I\)

N
CIt

C

ID

=e
0

liE
PWD

C

!!

g

-m
CO

;;
:I

c:

.Do

OJ

><
I

-I
......

OJ

(')

en

CD

~

0

"11

Q
Q

.....

.f

g,

I

-I
......

,!II

m
"0
::u

....a.

OJ

><

I

CE
WE

><

U)

"11

.Do

Q
Q

,Fit

:§

"'1'1
0
0

N
CIt

Ao - -'17

""

0
0
--'

""--'00

~'" ~'"

~~

",,,,,
... 0
>-0

"'''''
"'''''
>-0
>-0
... 0

... 0

>-'" >-'" >-g
"'--'
"'--'
""CD "'--'
""CD
""'"
"''''
"",,,,... "''''
"",,,,.... !i:l'"
'%
~~ J,~ c:,~
..,2 ..,2

..'" ..'".
0

OJ

><
"tI

:n

0

C

!!
r:::

...
(!)

01

-I
......

rn

0

""m
)(
m

-

r\:, '<
.j>.

.-of

CJ)

."
0
0

UJ

m

C

!D
N
co

POWER
REDUCTION
CONTROL

(!)

~
Co

"'00 "

c:
0

IC

I\)
CI)

."

~

~m
I\)
CI)

CE

:n

."
0
0

WE

.-of

"'"
m

Of

(5

PWD

Z

!-----,

=ti

><
I

-I
......

m

(!)

m

gl

'"C

;"

...

IC

I»

3

Y-GATING/SENSING

AO - A,s

Vpp

"go "go
"'''
"'''
"'0
>--0
>--0
>--0
" "'''
>--0
>-0
>-0
>-0
>->-"''''
>-...,
CD""
>-'" "''''
>-'"
'" ..., "",
"'...,
"",
"",
CD '"
"''''
" >-- "" >-""'''' cb ~~ Ncb~.. Nch~..

.. .

I'"

I'"

Iz

OJ'" OJ'" ~~
'"0: '"0:

N"
-'" -'" -'"

~

I§
""'"GND

~
~

©

IiiiiI

~

'1iiI

@
290451-19

2EJ
~
~

C::{j

©
~

28F400BX·T IB, 28F004BX·T IB

3.1 28F004BX Memory Organization

3.1.2 BLOCK MEMORY MAP

3.1.1 BLOCKING

The 28F004BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array wh~n an address is given within the block address range and the Erase Setup and Erase Confirm
commands,are written to the CUI. The 28F004BX is
a random read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection

The 16 Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by ,
preventing the boot block from being programmed
or erased when PWD is not at 12V. The boot block
can be erased and programmed when PWD is held
at 12V for the duration of the erase or program operation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BX-T and 28F004BX-B.

Two versions of the 28F004BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BX-T
memory map is inverted from the 28F004BX-B
memory map.
3.1.2.1 28F004BX-B Memory Map

The 28F004BX-B device has the 16 Kbyte boot
block located from OOOOOH to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F004BX-B the first 8 Kbyte parameter block resides in memory from 04000H to 05FFFH. The second 8 Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96 Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128 Kbyte main block reside in
memory space from 20000H to 3FFFFH, 40000H to
5FFFFH and 60000H to 7FFFFH. See Figure 10.

7FFFFH

128 Kbyte MAIN BLOCK
60000H
5FFFFH
128 Kbyte MAIN BLOCK

3.1.1.2 Parameter Block Operation

The 28F004BX has 2 parameter blocks (8 KBytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot.or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F004BX-T and 28F004BX-B.

40000H
3FFFFH
128 Kbyte MAIN BLOCK
20000H
1FFFFH
96 Kbyte MAIN BLOCK
08000H
07FFFH
06oaOH
05FFFH
04000H
03FFFH

, 8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK

3.1.1.3 Main Block Operation
ooaOOH

Four main blocks of memory exist on the 28F004BX
(3 X 128 KByte blocks and 1 x 96 KByte blocks).
See the following section on Block Memory Map for
the address location of these blocks for the
28F004BX-T and 28F004BX-B.

3-246

Figure 10. 28F004BX-B Memory Map

28F400BX-T/B,28F004BX-T/B

4.0

3.1.2.2 28F004BX-T Memory Map

The 28F004BX-T device has the 16 Kbyte boot
block located from 7COOOH to 7FFFFH to accommodate those microprocessors that boot from the
top of the addres.s map. In the 28F004BX-T the first
8 Kbyte parameter block resides in memory space
from 7AOOOH to 7BFFFH. The second 8 Kbyte parameter block resides in memory space from
78000H to 79FFFH. The 96 Kbyte main block resides in memory space from 60000H to 77FFFH.
The three 128 Kbyte main blocks reside in memory
space from 40000H to 5FFFFH, 20000H to 3FFFFH
and OOOOOH to 1FFFFH.

7FFFFH
16 Kby1e BOOT BLOCK

7COOOH
7BFFFH
7AOOOH
79FFFH
78000H

8 Kbyte PARAMETER BLOCK
8 Kby1e PARAMETER BLOCK

77FFFH
96 Kby1e MAIN BLOCK
60000H

5FFFFH
128 Kby1e MAIN BLOCK
40000H

3FFFFH
128 Kbyte MAIN BLOCK
20000H

1FFFFH
128 Kby1e MAIN BLOCK

OOOOOH

PRODUCt FAMILY PRINCIPLES
OF OPERATION

Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 4 Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
The CUI allows for 100% TTL-level control inputs,
fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
4 Mbit boot block flash family will only successfully
execute the following commands: Read Array, Read
Status Register, Clear Status Register and .Intelligent Identifier mode. -The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or
through the standard EPROM Ag high voltage ac- .
cess (VID) for PROM programming equipment.
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.

4.1

28F400BX Bus Operations

Figure 11. 28F004E!X-T Memory Map

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the.flash
memory conform to standard microprocessor bus
cycles.

3-247

int:et

28F400BX·T IB, 28F004BX·T IB

Table 1. Bus Operations for WORD·WIDE Mode (BYTE = VIH)
Mode
Read

Notes

PWD

CE

1,2,3

VIH
VIH

Output Disable
Standby

OE

WE

Ag

Ao

Vpp

VIL

VIL

VIH

X

X

X

DOUT'

VIL

VIH

VIH

X

X

X

HighZ

VIH

VIH

X

X

X

X

X

HighZ

VIL

X

X

X

X

X

X

HighZ
0089H

DOO-15

Deep Power-Down

9

Intelligent Identifier (Mfr)

4

VIH

VIL

VIL

VIH

VID

VIL

X

4,5

VIH

VIL

VIL

VIH

VID

VIH

X

4470H
4471H

6,7,8

VIH

VIL

VIH

VIL

X

X

X

.DIN

,

Intelligent Identifier (Device)
Write

Table 2. Bus Operations for BYTE·WIDE Mode (BYTE = VIL)
Mode
Read

PWD . CE

Notes
1,2,3

.Output Disable
Standby

OE

WE

Ag

Ao

A-1

Vpp

PO O-7

D08-14

VIH

VIL

VIL

VIH

X

X

X

'X

DOUT

HighZ

VIH

VIL

VIH

VIH

X

X

X

X

HighZ

HighZ

VIH

VIH

X

X

X·

X

X

X

HighZ

HighZ

VIL

X

X

X

X

X

X

X

HighZ

HighZ

X

89H

HighZ

Deep Power·Down

9

Intelligent
Identifier (Mfr)

4

VIH

VIL

VIL

VIH

VII)

VIL

X

4,5

VIH

VIL

VIL

VIH

VID

VIH

X

X

70H
71H

HighZ

6,7,8

VIH

VIL

VIH

VIL.

X

X

X

X

DIN

HighZ

Intelligent
Identifier (Device)
Write

NOTES:
1. Refer to DC Characteristics.
2. X can beVL, VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC Characteristics for VPPL, VPPH, VHH, VIC voltages.
4. Manufacturer and Device codes may also ~e accessed via a CUI write sequence. A1-A17 = X.
5. Device ID = 4470H for 28F400BX-T and 4471H for 28F400BX-B.
6. Refer to Table 4 for valid DIN' during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when Vpp. = VPPH. '
8. To write or erase the boot block, hold PWD at VHH.
9. PWD must be at GND ±O.2V to meet the 1.2"A maximum deep power-down current.

,

\

3-248

infel~

28F400BX·T IB, 28F004BX·T IB

4.2 28F004BX Bus Operations
Table 3. Bus Operations
Mode

Notes

PWD

CE

OE

WE

Ag

Ao

Vpp

X

X

DOUT

DQO-7

VIH

VIL

VIL

VIH

X·

Output Disable

VIH

VIL

VIH

VIH

X

X

X

HighZ

Standby

VIH

VIH

X

X

X

X

X

HighZ

Read

1,2,3

Deep Power-Down

9

VIL

X

X

X

X

X

X

HighZ

Intelligent Identifier (Mfr)

4

VIH

VIL

VIL

VIH

VID

VIL

X

89H

4,5

VIH

VIL

VIL

VIH

VID

VIH

X

78H
79H

6,7,8

VIH

VIL

VIH

VIL

X

X

X

DIN

Intelligent Identifier (Device)
Write

NOTES:
1. "Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC Characteristics for VPPL, VpPH, VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence, A1-A1B
5. Device 10 = 78H for 28F004BX-T and 79H for 28F004BX-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block erase or byte program are only executed when Vpp = VPPH.
6. Program or erase the Boot block by holding PWD at VHH.
9. PWD must be at GND ±O.2V to meet the 1.2).LA maximum deep power-down current.

=

X.

4.3 Read Operations

4.3.1.2 Input Control

The 4 Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be discussed in detail in the "Write Operations" section.

With WE at logic-high level (VIH), input to the device
is disabled. Data Input/Output pins (DO[0:15] or
DO[0:7]) are controlled by OE.

During power-up conditions (Vcc supply ramping), it
takes a maximum of 600 ns from when VCC is at
4.5V minimum to valid data on the outputs.
4.3.1 READ ARRAY
If the memory is not in the Read Array mode,it is
necessary to write the appropriate read mode command to the CUI. The 4 Mbit boot block flash family
has three control functions, all of which must be logically active, to obtain data at the outputs. Chip-Enable CE is the device selection control. Power-Down
PWD is the device power control. Output-Enable OE
is the DATA INPUT10UTPUT (DO[0:15] or DO[0:7])
direction control and when active is used to drive
data from the selected memory on to the 1/0 bus.

4.3.2 INTELLIGENT IDENTIFIERS
28F400BX PRODUCTS
The manufacturer and device codes are read via the
CUI or by taking the A9 pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, and location 00001 H outputs the device code; 4470H for
28F400BX-T, 4471H for 28F400BX-B. When BYTE
,is at a logic low only the lower byte of the above
signatures is read and D0151 A-1 is a "don't care"
during Intelligent Identifier mode. A read array command must be written to the memory to return to the
read array mode.
28F004BX PRODUCTS

4.3.1.1 Output Control
With OE at logic-high level (VIH), the output from the
device is disabled and data input/ output pins
(DO[0:15] or DO[0:7] are tri-stated. Data input is
then controlled by WE.

The manufacturer and device codes are also read
via the CUI or by taking the Ag pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH outputs the manufacturer's identification code,. 89H,
and location 00001 H outputs the device code; 78H
for 28F004BX-T, 79H for 28F004BX-B.

3-249

infel~

28F400BX-T/B,28F004BX-T/B

4.4 Write Operations
Commands are written to the CUI using standard microprocessor write timings.' The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For aprogram
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
Aft€r the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor' issues another command.

However, if PWD is not at VHH when a program or
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for Status Register Definitions) is set to indicate the failure to com, plete the operation.
4.4.2 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section., After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CUI,to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes

The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power' supply
switchable, available only when memory updates
are desired. The system designer can also choose
to "hard"wire" Vpp to 12V. The 4 Mbit boot block
flash family is designed to accommodate-either design practice. It is recommended that PWD be tied to
logical Reset for data protection during unstable
CPU reset function as described in the "Product
Family Overview" section.

00
10
20
40
50
70
90
BO
DO
FF

Device Mode

Invalid/Reserved
, Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array

4.4.2.2 Command Function Descriptions

'4.4.1 BOOT BLOCK WRITE OPERATIONS

In the case of Boot Block modifications (write and
erase), PWD is set to VHH = 12V typically, in addition to Vpp at high voltage;

Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 4 Mbit
boot block flash family commands.

3-250

int:et

28F400aX-T IB, 28F004BX-T IB
Table 4. Command Definitions
Command

Bus Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data

Read Array

1

1

Write

X

r::FH

Intelligent Identifier

3

2,4

Write

X

90H

Read

IA

110

3

Write

X

70H

Read

X

SRD

Write

X

50H

Read Status Register

2

Clear Status Register

1

Erase Setup/Erase Confirm

2

5

Write

BA

20H

Write

BA

DOH

Word/Byte Write Setup/Write

2

6, 7

Write

WA

40H

Write

WA

WD

Write

X

BOH

Write

X

DOH

6, 7

Write

WA

10H

Write

WA

WD

Erase Suspend/Erase Resume

2

Alternate Word/Byte
Write Setup/Write

2

NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. 110 = Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
6. WA = Address to be written.
WD = Data to be written at location WD.
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus [0°8-0°15] = X (28F400BX-only) which is either Vee or Vss
to avoid burning additional current.

Invalid/Reserved

Read Status Register (70H)

These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.

This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.

Read Array (FFH)

The device automatically enters this mode after program or erase has completed.

This single write command points the read path at
the array. If the host CPU performs a CE/OE controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address Ao is used in this mode, all
other address inputs are ignored).

3-251

Clear Status Register (50H)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.

intet

28F400BX·T IB, 28F004BX·T IB

Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to ac-'
commodate efforts to achieve an industry standard
command code set.
Program

The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)

Prepares the CUI ,for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI wi,lI set
both the Program Status and Erase Status bits of the
Status Register to a "1 ", place the device into the
Read Array state, and wait for another command.
Erase Confirm (DOH)

If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE is toggled low. Status Register data can
only be updated by toggling either OE or CE low.
Erase Suspend (BOH)

This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will set
an output that directs the WSM to suspend Erase
operations, and then return to responding to only
Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend
state, it will set an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CUI will not respond to any other commands. The WSM will also set the WSM Status bit to
a "1". The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input

control pins, with the exclusion of PWD. PWD will
immediately shut down the WSM and the remainder
of the chip. During a suspend operation, the data
and address latches will remain closed, but the address pads are able to drive the address into the
•
read path.
Erase Resume (DOH)

This command will cause the CUI to clear the Suspend state and set the WSM Statl;ls bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
.
4.4.3 STATUS REGISTER

The 4 Mbit boot block flash family contains a status
register which may be read to determine when a program or erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing this command, all subsequent Read operations output data
from the status register until another command is
written to the CUI. A Read Array command must be
written to the CUI to return to the Read Array mode.
The status register bits are output on DO[O:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode for the 28F400BX. In the word-wide
mode the upper byte, DO[8:15] is set to OOH during
a Read Status command. In the byte-wide mode,
DO[8:14] are tri-stated and D015/A-1 retains the
low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OE or CE
whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. GE or OE must be toggled with
each subsequent status read, or the completion of a
program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status' of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing !he desired operation. The WSM sets
status bits "Three" through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five". These bits can only be
Cleared by the controlling CPU through the use of
the Clear Status Register command.

3-252

intel·
4~4.3.1

28F400BX-T IB, 28F004BX-T IB

Status Register Bit Definition
Table 5. Status Register Definitions

IWSMS lESS
7

6

ES

5

pslvppsl
4

3

RI R I R
2

I

o

NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy

Write State Machine Status bit must first be checked to
determine byte/word program or block erase comple·
tion, before the Program or Erase Status bits are
checked for success,

SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed

,When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit reo
mains set to "1" until an Erase Resume command is
issued.

SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase

When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still
unable to successfully perform an erase verify.

SR.4 = PROGRAM STATUS
1 ,= Error In Byte/Word Program
o = Successful Byte/Word Program

Whim this bit is set to "1", WSM has attempted but
failed to Program a byte or word.

SR.3 = Vpp STATUS ,
1 = Vpp Low Detect; Operation Abort
0= Vpp OK

The Vpp Status bit unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM
interrogates the Vpp level only after the byte write or
block erase command sequences have been entered
and informs the system if Vpp lias not been switched
on. The Vpp Status bit is not guaranteed to report accurate feedback between VpPL and VPPH. '

SR.2-SR.0 = RESERVED FOR
FUTURE ENHANCEMENTS

These bits are reserved for future use 'and should be
masked out when polling the Status Register.

4.4.3.2 Clearing the Status Register

4.4.4 PROGRAM MODE

Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the' system software to control
the resetting of these bits, several operations may
be performed' (such as cumulatively programming
several bytes or erasing multiple' blocks in sequence). The status register may then be read to
determine if an error occurred during that'programc
ming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the quI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.

Program is executed by a two-write, sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a' sequence of internally ,timed
events to:
'
1. Program t~e desired bits of the addressed memory word (byte), and
2. Verify that the desired bits are sufficiently programmed.'
,
Programming of the memory results in specific bits
within a byte or word being changed to a "0'''.
If the user attempts to program "1"s, there will be no
change of the memory cell content and no error occurs.

3-253

intel .

28F400BX-T IB, 28F004BX-T/B

Similar to erasure, the status register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
toggling either CE or DE to determine when the program sequence is complete. Only the Read Status
Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whetl')er the program operation was
successful, should be checked. If- the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If,
Bit 3 is set thenVpp was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register, should be, cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be accomplished until the CUI is, given the appropria~e
command. A Read Array command must first be given before memory contents can be read.
Figure 12 shows a system software flowchart for device byte programming operation. Figure 13 shows a
similar flowchart for device word programmingoperation (28F400BX-only).
'
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A[12:17j for the
28F400BX or A[12:18j for the 28F004BX, identifying
the block to be erased. These addresses are latched
\ internally when the Erase Confirm ,command is issued. Block erasure results in all bits within the block
'
being set to "1".
The WSM will execute a sequence of internally
timed events to:
1. Program alltiits within the block
'2. Verify that all bits within the block ,are sufficiently
'
programmed

While the erase sequence is executing, Bit 7 of the
status register is a /'0".
When 'the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bits of the status register is set to a "1" to indicate
an Erase Failure, and Bit3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
, be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 14 shows a system software 'flowcharffor
Block Erase operation.
'
4.4.5.1 Suspending and Resuming Erase
Since an, erase operation typically requires 1 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase sequence at a predetermined point In the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can'be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detailing the operation.

3. Erase all bits within the' block and
4. Verify that all bits within the block are sufficiently
erased

3-254

intaL

28F400BX-T/B,28F004BX-T/B

During Erase Suspend mode, the chip can go into a
pseudo·standby mode by taking CE to VIH and the
active current is now a maximum of 10 mAo If the
chip is enabled while in this mode by taking CE to
VIL, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other ~han
the block being erased, the Erase Resume com·
mand must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in or. .
der to continue.

4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capat,>ility into
its ETOX III flash memory technology. The 4 Mbit
boot block flash family is designed for 100,000 program/ erase cycles on each of the seven blocks. The
combination of low electric fields, clean oxide processing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.

3-255

intel~

28F400BX-T IB, 28F004BX-T IB

Bus
Operation

Comments

Command

Write

Setup
Program

Data = 40H
Address = Byte to be
programmed

Write

Program

Data to be programmed
Address = -Byte to be
programmed

Read

Status Register Data.
Toggle DE or CE to update
Status Register

Standby

Check SR.7
1 = Ready, 0

= Busy

RepeaHor subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.

Write FFH after the last byte programming operation to
reset the device to Read Array Mode.

290451-6

Full Status Check Procedure

Bus
Operation
Vpp Range
Error

Byte Prog ra m

Error

Command

Comments

Standby

CheckSR.3
1 = V pp Low Detect

Standby

CheckSR.4
-1 = Byte Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
SRA is only cleared by the Clear Status Register
Command, incases where multiple byt'?s are programmed
before full status is checked.

290451-7

If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 12. Automated Byte Programming Flowchart

3-256

intel .

28F400BX·T IB, 28F004BX·T IB

Bus
Operation

Command

Comments

Write

Setup
Program

Data = 40H
Address = Word to be
programmed

Write

Program

Data to be programmed
Address = Word to be
programmed

Read

Status Register Data.
Toggle DE or CE to update
Status Register

Standby

CheckSR.7
1 = Ready, 0 = Busy

Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.

Write FFH after the last word programming operation to
reset the device to Read Array Mode.

290451-8

Full Status Check Procedure

Bus
Operation

. Comments

Command

Vpp Range
Error

Standby

Check SR.3
1 = Vpp Low Detect

Word Program
Error .

Standby

CheckSR.4
1 = Word Program Error

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290451-9

SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 13. Automated Word Programming Flowchart

3-257

intel·

28F400BX·T IB, 28F004BX·T IB

Bus
Operation

Commsnd

Comments

Write

Setup
Erase

Data = 20H
Address = Within block to be
, erased

Write

Erase

Data = DOH
Address = Within block to be
erased

Read

Status Register Data.
Toggle (5E or CE to update
Status Register

Standby,

CheckSR.7
1 = Ready, 0

= Busy

Repeatfor subsequent blocks.
, Full status check can be done afier each block or afier a
sequenCe of blocks.

Write FFH afier the his! block erase operation to reset the
device to Read Array Mode.

290451-10

Full,Status Check Procedure
Bus
Operation

Command

Comments

Standby

CheckSR.3
1 = Vpp Low Deiect

Error

Standby

Check SR.4,5
Both 1 = Command Sequence
Error

Block Erase

Standby

CheckSR.5
1 = Block Erase Error

Command Sequence

Error

SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Wriie State
Machine.
290451-11

SI'l.5 is only cleared by the Clear Status Register
Command, in cases where rriultlple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 14. Automated Block Erase Flowchart

3-258

int:el.,

28F400BX·T/B,28F004BX~T/B

Bus
Operation

Write

Command

Erase
Suspend

Comments

Data = BOH

Read

Status Register Data.
Toggle OE or CE to update
Status Register

Standby

CheckSR.7
1 = Ready

Standby

CheckSR.6
1 = Suspended

Write

Read Array

Read array data from block
other than that being
erased.

Read

Write

Data = FFH

Erase Resume

Data = DOH

290451-12

Figure 15. Erase Suspend/Resume Flowchart
~aximum Icc current is 3 mA and typical Icc current
IS 1 mAo The device stays in this static state with
outputs valid until a new location is read.

4.5 Power Consumption
4.5.1 ACTIVE POWER
With CE at a logic-low level and PWO at a logic-high
level, the device is placed in the active mode. The
device Icc current is a maximum 60 mA at 10 MHz
with TTL input signals.
4.5.2 AUTOMATIC POWER SAVINGS
Automa~ic Pow~r Savings (APS) is a low pwer feature dunng actIve mode of operation. The 4 Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is
not being accessed. After data is read from the
memory. array, PRC logic controls the device's power consumption by entering the APS mode where

4.5.3 STANDBY POWER
With CE at a logic-high level (VI H), and the CUI in
read mode, the memory is placed in standby mode
w~ere the ~aximu.m Icc standby current is 100 /LA
wIth CMOS Input sIgnals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(00[0:15] or 00[0:71) are placed in a high-impedance state independent of the status of the OE signal. When. the 4 Mbit boot block flash family is deselected dunng erase or program functions, the devices w!1I continue to perform the erase or program
functl?n and consume program or erase active power untIl program or erase is completed.

3-259

in1et

28F400BX-T IB, 28F004BX-T IB

4.7 Power Supply Decoupling ,

4.5.4 DEEP POWERDOWN
The 4 Mbitboot block, flash family supports a typical
lee of 0.2 p.A in deep power·down mode. One of the'
. target markets for these devices is in portable equip·
ment where the power consumption of the machine.
is of prime importance. The 4 Mbit boot block flash
family has a PWD pin which places the device in the
deep powerdown mode. When PWDis at a logic·low
(GND ± 0.2V), all circuits are turned off and the device typically draws 0.2 p.A of Vee current.
During read modes, the PWD pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a minimum of 400 ns to access valid data (tpHQV)'
During erase or program modes, PWD low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the PWD function. As in the read mode
above, all internal circuitry is turned off to ,achieve
the 0.2 p.A current level.
PWD transitions to VIL or turning power off to ·the
device will clear the status register.

4.6 Power-up Operation
The 4 Mbit boot block .flash family is deSigned to
offer protection against accidental.block erasure or
programming during power transitions. Upon powerup the 4 Mbit boot block flash family is indifferent as
to which power supply, Vpp or Vee, powers-up first.
Power supply sequencing is not required.
The 4 Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
.
In addition, on power-up the user must either drop
CE low or present· a new address to ensure valid
data at the outputs.
'
. A system designer must guard against spurious
writes for Vee volt~s above VLKO when Vpp is
active. Since both WE and CE must be low for a
command write, driving either signal to VIH will inhibit
writes to thei device. The CUI architecture provides
an added level of protection since alter~tion of memory contents can only occur after successful completion of the two-step command sequences, Finally
the 'device is disabled until PWD is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another .level of memory protec' . '
tion.

Flash memory's power switching characteristics re. quire careful device decoupling methods. System
deSigners are Interested in 3 supply current issues:
• Standby current levels (lees)
• Active current levels (leeR)
• Transient peaks produced "by falling and rising
edges of CEo
'
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 .p.F ceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, lowinherent inductance capacitors should be placed 'as
close as possible to the package leads.

4.7.1 Vpp TRACE ON PRINTED CIRCUIT
.

BOARDS

Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
designer. The Vpp pin supplies the flash memory
cells current for programming and erasing. One
should use similar trace widthS and layout considerations given to the Vee power, supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots.

4.7.2 Vee, Vpp AND PWD TRANSITIONS.
The CUI latches commands as .issued by system
software and is not altered by Vpp or CE transitions
or WSM actions. .Its state upon power-up, after exit
from deep power-down mode or after Vee transitions below VLKO (Lockout voltage), is Read Array
mode.
After any word/byte write or block era~e operation is .
complete and even after Vpp transitions down to
VPPL, the CUI must be reset to Read Array mod~ via
the Read Array, command when accesses to the
flash memory are desired;

3-260

intel .

28F400BX-T/B,28F004BX-T/B

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on·
products in the sampling and initial production phases
of development. The specificatiOnS are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet be·
fore finalizing a design.

Commercial Operating Temperature
During Read .................•.. O·C to 70·C(1.l
During Block Erase
.
and Word/Byte Write ........•...... O·C to 70·C
Temperature Under Bias ....... -1 O·C to + 80·C
Extended Operating Temperature
During Read ................. - 40·C to
During Block Erase
and Word/Byte Write ......... - 40·C to
Temperature Under Bias ..•.. .-. -40·C to

+ 85·C

+ 85·C
+ 85·C

Storage Temperature .•........ - 65·C to

+ 125·C

Voltage on Any Pin
(except Vee and Vpp)
with Respect to GND .•....•. - 2.0V to

+ 7.0V(2)

Voltage on Pin PWD or Pin A9
'with Respect to GND ..... - 2.0V to

+ 13.5V(2, 3)

Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... - 2.0V to

+ 14.0V(2,3)

Vee Supply Voltage
.
with Respect to GND ...•.... - 2.0V to

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings"may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 7.0V(2)

Output Short Circuit Current. ; •..•..•...• 100 mA(4)
NOTES:

1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns.
Maximum De voltage on ·input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V for
periods <20 ns.
3. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. 10% Vee specifications reference the 28F400BX·60/28F004BX·60 in their standard test configuration, and the
28F400BX·80/28F004BX·80.
6. 5% Vee specifications reference the 28F400BX·60/28F004BX·60 in their high speed test configuration.

OPERATING CONDITIONS
Symbol

Parameter

Notes

. Min

Max

Units

0

70

·C

TA

Operating Temperature

Vee

Vee Supply Voltage (10%)

5

4.50

5.50

V

Vee

Vee Supply Voltage (5%)

6

4.75,

5.25

V

DC CHARACTERISTICS
Symbol

Parameter

Notes

Min

Typ

Max

Unit

III

Input Load Current

1

±1.0

,...A

Vec= Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

,...A

Vee = Vee Max
VOUT = VceorGND

3-261

Test Condition

28F400BX-T IB, 28F004BX-TIB

DC CHARACTERISTICS (Continued)
Symbol
lees

Para""eter
Vee Standby Current

Icco

Vcc Deep Powerdown Current

ICCR

Vcc Read Current
for 28F200BX Word-Wide
Mode

ICCR

Vcc Read Current for
28F200BX Byte-Wide Mode
and 28F004BX

Notes Min Typ
1,3

1

0.20

1,5,
6

1,5,
6

Max

Unit

1.5

rnA

Vcc = Vcc Max
CE = PWD = VIH

100

p.A

Vee = Vcc Max
CE = PWD ~ Vcc ±0.2V
28F200BX:
BYTE = Vcc ±0.2V .or GND

1.2

PWD = GND ± 0.2V

60

p.A
rnA

65

rnA

55

rnA

Vcc = Vcc Max, CE = GND
f = 10 MHz,.I0UT = 0 rnA
CMOS Inputs

60

rnA

Vcc = Vee Max, CE = Vil
f = 10 MHz,lOUT = 0 rnA
TIL Inputs/

rnA
rnA
rnA
rnA

Word Write in Progress

Iccw

Vcc Word Write Current

1

70

Iccw

Vcc Byte Write" Current

1

60

ICCE

Vcc Block Erase Current

1

30

ICCES

Vee Erase Suspend Current

Ipps

Vpp Standby Current

1

±10

Ippo

Vpp Deep PowerDown Current

1

5.0

1,2

5

10

Test.Condltlon

Vcc = Vcc Max, CE = GND
f = 10 MHz, lOUT = 0 rnA
CMOS Inputs
Vcc = Vcc Max,CE = Vil
f = 10 MHz, lOUT := 0 rnA
. TIL Inputs

Byte Write in Progress
Block Erase in Progress
Block Erase Suspended,
CE = VIH

IpPR

Vpp Read Current

1

200

Ippw

Vpp Word Write Current

1

40

p,A
p.A
p.A
rnA

Ippw

Vpp Byte Write Current

1

30

rnA

Vpp = VPPH
Byte Write in

IpPE

Vpp Block Erase Current

1

30

rnA

Vpp = VpPH
Bloc~ Erase in Progress

IpPES

Vpp Erase Suspend Current

1

200

p.A

Vpp =;' VpPH
Block Erase Suspended

110

1

500

p.A Ag = VIO.

VIO

Ag Intelligent Identifier Current
Ail Intelligent Identifier Voltage

11.5

13.0

V

Vil

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vec+ 0.5

V

Val

Output Low Voltage

0.45

V

3-262

Vpp

s: Vcc

PWD

= GND ± 0.2V

Vpp> Vee
Vpp = VPPH
Word Write in Progress
Progre~s

Vee = VeeMii'l
IOl = 5.8 rnA

intel .

28F400BX-T IB, 28F004BX-T IB

DC CHARACTERISTICS (Continued)
Symbol

Parameter

Notes

Min

Typ

Unit

Max

VOH

OiJtput High Voltage

2.4

VPPL

Vpp during Normal Operations

3

0.0

6.5

V

VPPH

Vpp during Erase/Write Operations

7

11.4

12.0

12.6

V

VPPH

Vpp during Erase/Write Operations

8

10.8

12.0

13.2

V

VLKO

Vee Erase/Write Lock Voltage

2.0

VHH

PWD Unlock Voltage

11.5

V
13.0

V

EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol

Parameter

TA

Operating Temperature

Vee

Vee Supply Voltage (10%)

Notes

5

Test Condition
Vee = Vee Min
IOH = -2.5 mA

V

Boot Block Write/Erase

,

Min

Max

Unit

-40

85

·C

4.50

5.50

V

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol

Parameter

Notes Min

Typ

Max

Unit

Test Condition

III

Input Load Current

1

±1.0

p,A

Vee = Vee Max
VIN = Vee or GND

ILO

Output Leakage Current

1

±10

p,A

Vee = Vee Max
VOUT = Vee or GND

Ices

Vee Standby Current

1.5

rnA

Vee =. Vee Max
CE = PWD =VIH

100

p,A

Vee = Vee Max
CE = PWD = Vee ±0.2V
28F400BX:
BYTE = Vee ±0.2VorGND

8

p,A

PWD = GND ±2V

IceD

Vee Deep Power-Down Current

. 1,3

1

0.20

3-263

infel~

28F400BX-T IB, 28F004BX-T IB

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol
ICCR

lecR

Parameter
VCC Read Current for
28F400BX Word-Wide Mode

Vee Read Current for
28F400BX Byte-Wide Mode
and 28F004BX

Notes

Min

Typ

1,5,
6

1,5,
6

Max

Unit

Test Condition

70

rnA

Vee = Vce Max, CE = GND
f = 10 MHz, lOUT = 0 rnA
CMOS Inputs

75

rnA

Vee = Vec Max, CE = VIL
f = 10 MHz, lOUT = 0 rnA
TTL Inputs

65

rnA

= Vee Max, CE = GND
10 MHz, lOUT = 0 rnA
CMOS Inputs

Vee

f
70

rnA

= Vee Max, CE = VIL
10 MHz, lOUT = 0 rnA
TTL Inputs
Vee

f

c

_ 75

=

=

leew

Vee Word Write Current

1

lecw

Vee Byte Write Current

1

65

rnA

Byte Write in Progress

lecE

Vee Block Erase Current

1

40

rnA

Block Erase in Progress

lecES

Vee Erase Suspend Current

10

rnA

Block Erase Suspended,
CE = VIH

Ipps

Vpp Standby Current

1

±10

p.A

Vpp

IpPD

Vee Deep Power-Down Current

1

5.0

p.A

PWD

1,2

5

rnA

Word Write in Progress

s: Vee
= GND

± 0.2V

IpPR

Vpp Read Current

1

200

p.A

Vpp> Vee

Ippw

Vpp Word Write Current

1

40

rnA

Vpp = VPPH
Word Write in Progress

Ippw

Vpp Byte Write Current

1

40

rnA

Vpp = VPPH
Byte Write in Progress

3-264

intel~

28F400BX·T IB, 28F004BX·T IB

DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

IpPE

VPP Block Erase Current

1

30

rnA VPP = VPPH
Block Erase in Progress

IpPES

VPP Erase Suspend Current

1

200

/LA VPP = VPPH
Block Erase Suspended

1

110

Ag Intelligent Identifier Current

VIO

Ag Intelligent Identifier Current

11.5

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

VPPL

VPP during Normal Operations

VPPH

500

/LA Ag

13.0

V

0.8

V

Vee

+ 0.5

0.45
2.4

V
V

Vee = Vee Min
IOL = 5.8 rnA

V

Vee = Vee Min
IOH = -2;5 rnA

3

0.0

6.5

V

VPP during Erase/Write Operations

7

11.4 12.0

12.6

V

VPPH

VPP during Erase/Write Operations

8

10.8 12.0

13.2

V

VLKO

Vee Erase/Write Lock Voltage

2.0

VHH

PWD Unlock Voltage

11.5

CAPACITANCE(4)
Symbol

= VIO

V

13.0

V

Boot Block Write/Erase

TA =.25'C,f = 1 MHz

Parameter

Typ

Max

Unit

Condition

CIN

Input Capacitance

6

8

pF

VIN = OV

COUT

Output Capacitance

10

12

pF

VOUT = OV

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25'e. These currents
are valid for all product versions (packages and speeds).
.
2. leeEs is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of leeEs and leeR.
3. Block Erases and Word/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in .the range between VpPH and
VpPL·
4. Sampled, not 100% tested..
.
5. Automatic Power Savings (APS) reduces leeR to less than 1 inA typical in static operation.
6. eM OS Inputs are either Vee ±0.2V or GNO ±0.2V. TTL Inputs are either VIL or ViH.
7. Vpp = 12.0V ± 5% for applications requiring 100,000 block erase cycles.
.
8. Vpp = 12.0V ± 10% for applications requiring wider Vpp tolerances at 100 block erase cycles.
g. For the 28F004BX address pin AlO follows the eOUT capacitance numbers.

3-265

I
I

intel .

28F400BX-T IB, 28F004BX-T IB

STANDARD TEST CONFIGURATION(1)
STANDARD
AC TESTING LOAD CIRCUIT

STANDARD
AC INPUT/OUTPUT REFERENCE WAVEFORM

1.3V

X::: >

2.4 --INP-U""T
0.45

Trd POINTS

<

I

lN9l.
2.0

OUTPUT

0.8

290451-14

AC test inputs are driven at VOH (2.4 VnLl for a Logic "1" and VOL
(0.45 VnLl for a logic "0". Input timing begins at VIH (2.0 VnLl and VIL
(0.8 VnLl. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) < 10 ns.

1-~_-oOUT

290451-13

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 KO .

HIGH SPEED TEST CONFIGURATION(2)
HIGH SPEED
AC TESTING LOAD CIRCUIT

HIGH SPEED
AC INPUT/OUTPUT REFERENCE, WAVEFORM

X1.S-+--,TES;~INTS-Xl.S

::: ---INP-,U""T

,

lN9l4

OUTPUT'

290451-22

,

J--~_-oOUT

ACtest inputs are driven at 3.0V for a Logic "1" and O.OV for a logic "0".
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
(10% to.90%) < 10 ns.
290451-21

CL=30pF
CL Includes Jig Capacitance
RL = 3.3KO
NOTES:

1. Testing characteristics for 28F400BX·60/28F004BX·60 in standard test configuration and 28F400BX·80/28F004BX·80.
2. Testing characteristics for 28F400BX·60/28F004BX~60 in high speed test configuration.

j,

3·266

28F400BX-T IB, 28F004BX-T IB

AC CHARACTERISTICS-Read Only Operations(1)
. 28F400BX-60(4)
28F004BX-60(4)

± 5%

Vee
Versions
Vee
Symbol

28F400BX-60(S)
28F004BX·60(S)

± 10%

Parameter

Notes

Min

tAVQV tACC Address to
Output Delay
CE to Output Delay

tELQV tCE

2

tpHQV tpwH PWD High to
Output Delay
tGLQV tOE

OE to Output Delay

2

tELQX tLz

CE to Output Low Z

3

tEHQZ tHz

CE High to Output
HighZ

3

tGLQX tOLZ OE to Output Low Z

Max

60

Read Cycle Time

tAVAV tRC

3

Min

Max

70

28F400BX-80(S)
28F004BX-80(S)
Min

Unit

Max

80

ns

60

70

80

ns

60

70

80

ns

300

300

300

ns

40

ns

30

a

35

a
20

a

a
25

a

30

a

ns

3

Output Hold from
Addresses,
CE or OE Change,
Whichever is First

3

tELFL
tELFH

CEtoBYTE
Switching
Low or High

3

5

5

5

ns

tFHQV

BYTE Switching
High to Valid
Output Delay

3,6

60

70

80

ns

tFLQZ

BYTE Switching
Low to
Output High Z

3

20

25

30

ns

tOH

I

0

25

ns

OE High to Output
HighZ

tGHQZ tDF

20

ns

30
0

0

ns
ns

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
6. tFLOV, BYTE switching low to valid output delay, will be equal to tAVOV, measured from the time DQ15/ A.1 becomes valid.

\

3-267

intel~

28F400BX-T/B,28F004BX-T/B

EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS-Read Only Operations(1)
T28F400BX-90(4,5)
T28FOO4BX-80

Versions
Symbol

Parameter

Notes

Min

90

tAvAV

tRC

Read Cycle Time

tAVQV

tACC

Address to
Output Delay

tELQV

tCE

tpHQV

tpWH

tGLQV

tOE

OE to Output Delay

tELQX

tLZ

CE to Output Low Z

tEHQZ

tHZ

CE High to Output
HighZ

tGLQX

tOLZ

OE to Output Low Z

3

tOF

OE High to Output·
HighZ

3

tOH

Output Hold from
Addresses,
CE or OE Change,
Whichever is First

3

tELFL
tELFH

CEto BYTE
Switching
Low or High

3

5

ns

tFHQV

BYTE Switching
High to Valid
Output Delay

3, 5

90

ns

tFLQZ

BYTE Switching
Low to
Output High Z

3

35

ns

tGHQZ

ns

90

ns

CE to Output Delay

90

ns

PWEiHighto
Output Delay

300

ns

45

ns

2

0

ns

35
0
35
0

ns
ns

See AC Input/Output Reference Waveform for timing measurements.
OE may be delayed up to tCE-tOE aflerthe falling edge of CE without impact on tCE'
Sampled. hot 100% tested.
See Standard Test Configuration.
tFLQV. BYTE switching low to valid output delay. will be equal to tAVQV from the time OQ15/ A-1 becomes valid.

3-268

ns
ns

NOTES:

1.
2.
3.
4.
5.

Unit

Max

_.
Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

VIH

STANDBY

Vee POWER-DOWN

---~

ADDRESSES (A)

ADDRESSES STABLE
VIL

-

I'

-

_-----II

I' I

t AVAV

I\)
Oi)

VIH

CE

."

""

o
o

(E)

:!11
(Q

ED

VIL

><

...

~
......

C

...!1'
CD

>
~

50

VIH

OE

I\)
Oi)

(G)

."

o
o

VIL

::E
III

"'ED"

<
CD

Ul

N
0>

<0

0'
...

-...
3

><

VIH

~
......

WE (W)

ED

1/1

VIL

0

taH

JJ

CD

III

VIH

C.

0

...

'1J

HIGH Z
DATA (0/0)

CD

VALID OUTPUT

l

VIL

III

~------

O·
:l
1/1

l

HIGH Z

~

t AVOV

~

5.DV
Vee
GND
V
IH

~
(§J

©

1

Iiiiil

"'HOV

~
©

"iii!

-I

~

~

PWD (p)

~

VIL .;..J

290451-15

~

©
~

28F400BX-T IB, 28F004BX-T IB

75

75

70
65
60

It'

55
50

<-

....

45

5

40

u
.9

35

V

25
j

20
10

5

70

1/

65
60

V

~

.~

55

V

I)

50

<-

L/

30

15

V

5

/

l,)

45

17

40

r

u
_u
35

-0- OOC

~I-

30

~250C

~I-

25

-&-70 o C

~t-

20

~
~

I

V-

10

1

5

,-'-

~25OC

1-'-

-&-70 o C 1-1-

l/

15

-0- OOC

I

II

1

1 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

FREQUENCY (MHz)

FREQUENCY (MHz)

290451-27

290451-26

Figure 18. Icc (RMS) vs Frequency
(Vee = 5.5V) for x8 Operation

Figure 17. ICC (RMS) vs Frequency
(Vee = 5.5V for x16 Operation

100
95

/

90
85
'(;j'

-5
.U
u

....'"

~

80
75
70

~

65
60

/'"

~

C

. /V

./
..,....-I v

./

. /V

-0- 28F400BX/28F004BX-60
~ 28F400BX/28F004BX-80

55
50
30 50

100

150

200

250

OUTPUT CAPACITANCE (pF)

Figure 19. TAce vs Output Load Capacitance

3-270

290451-28

_.

::J
DEVICE
ADDRESS SELECTION

STANDBY
VIH

."

iFi

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CD

AOORESSES (A)

c

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DATA VALID

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CE

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o

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DATA (D/O)
VIL

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(I)

~

J:-:~HEH:::l _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _

l§1

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VHH

O·

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til

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VIH

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ffiiil

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PP

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(I)

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290451-17

©
~

infel .

28F400BX-TIB, 28F004BX-TIB

ORDERING INFORMATION

I
OPERATING TEMPERATURE
T
= EXTENDED TEMP
BLANK COMMERCIAL TEMP

=

I

~KAGE

~ ACCESS SPEED (ns)
:~~:'

E = STANDARD 56 LEAD TSOP
PA
44 LEAD PSOP

=

90 ns
290451-18

VALID COMBINATIONS:'

E28F400BX·60
E28F400BX·80

PA28F400BX·60
PA28F400BX·80 ,

TE28F400BX,T90
TE28F400BX·B90

TPA28F400BX·T90
TPA28F400BX·B90

I IE121slr1010141Blxl-161ol
O~r-E-RA-T-IN-G-TE-M-PE-R-AT-U-RE--II ~KAGE
T
BLANK

= EXTENDED TEMP
= COMMERCIAL TEMP

E
PA

~ ACCESS SPEED (ns)

= STANDARD 56 LEAD TSOP
= 44 LEAD PSOP

:~~:

90 ns

290451-30

VALID COMBINATIONS:

E28F004BX·60
E28F004BX·80

TE28F004BX·T90
TE28F004BX·B90

ADDITIONAL INFORMATION

Order Number
290448

28F200BX/28F002BX Datasheet
28F200BXL/28F002BXL Datasheet

290449

28F400BXL/28F004BXL Datasheet

290450

I

Ap·363 "Extended Flash BIOS Design for Portable Computers"
ER.,28 "ETOX·III Flash Memory Technology"

292098
204012

ER·29 "The Intel2/4·MBit Boot Block Flash Memory Family"

294013

REVISION HISTORY
Number

Description

,001

Original Version

·002

Removed ~70 speed bin.
Integrated ·70 characteristics into ·60 speed bin.
Added Extended Temperature characteristics.
Modified BYTE Timing Diagram.

28F008SA
8 MBIT (1 MBIT x 8) FLASH MEMORY

•
•

•
•
•

High-Density Symmetrically Blocked
Architecture
- Sixteen 64 KByte Blocks
Extended Cycling Capability
-100,000 Block Erase Cycles
- 1.6 Million Block Erase
Cycles per Chip
Automated Byte Write and Block Erase
- Command User Interface
- Status Register
System Performance Enhancements
- RY /BY Status Output
- Erase Suspend Capability
Deep-Powerdown Mode
- 0.20 J.LA Icc Typical

•
•
•
•
•
•

Very High-Performance Read
- 85 ns Maximum Access Time
SRAM-Compatible Write Interface
Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions
Industry Standard Packaging
- 40-Lead TSOP, 44-Lead PSOP
ETOXTM III Nonvolatile ~Iash
Technology
-12V Byte Write/Block Erase
Independent Software Vendor Support
- Microsoft* Flash File System (FFS)

Intel's 28F008SA 8 Mbit FlashFile™ Memory is the highest density nonvolatile read/write solution for solid
state storage. The 28F008SA's extended cycling, symmetrically blocked architecture,fast access time, write
automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The 28F008SA brings new capabilities to portable
computing. Application and operating system software stored in resident flash memory arrays provide instanton, rapid execute-in-place and protection from obsolescence through in-system software updates. Resident
software also extends system battery life and increases reliability by reducing disk drive accesses.
For high density data acquisition applications, the 28F008SA offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can
take advantage of the 28F008SA's nonvolatility, blocking and minimal system code requirements for flexible
firmware and modular software designs.
The 28F008SA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write. The 28F008SA memory map consists of 16 separately erasable 64 Kbyte blocks.
Intel's 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity. Its 85 ns access time provides superior performance when compared with magnetic storage media.
A deep powerdown mode lowers power consumption t01 p.W typical thru Vcc, crucial in portable computing,
handheld instrumentation and other low-power applications. The PWD power control input also provides
absolute data protection during system powerup/down.
Manufactured on Intel's 0.8 micron ETOX process, the 28F008SA provides the highest levels of quality,
reliability and cost-effectiveness~

·Microsoft is a trademark of Microsoft Corporation.

3-281

October 1992
Order Number: 290429-003

infel"

28F008SA

PRODUCT OVERVIEW
The 28F008SA is a high-performance 8. Mbit
(8,388,608 bit) memory organized as 1 Mbyte
(1,048,576 bytes) of 8 bits each. Sixteen 64 KByte
(65,536 byte) blocks are included on the 28F008SA.
A memory map is shown in Figure 6 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can
be independently erased and written 100,000 cycles. Erase Suspend mode allows system software
to suspend block erase to read data or execute
code from any other block of the 28F008SA.
The 28F008SA is available in the 4()-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and 44lead PSOP (Plastic Small Outline) packages. Pinouts are shown in Figures 2 and 4 of this specifica~~

.

The Command User Interface serves as the interface between the microprocessor or microcontroller
and the internal operation of the 28F008SA.
Byte Write and Block Erase Automation allow
byte write and block erase operations to be executed using a two-write command sequence to the
Command User Interface. The internal Write State
Machine (WSM) automatically executes the algorithms .and timings necessary for byte write and
block erase operations, including verifications,
thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in
byte increments typically within 9 p,s, an 80% improvement over current flash memory products. Ipp
byte write and block erase currents are 10 mA
typical, 30 mA maximum. Vpp byte write and
block erase voltage is 11.4V to 12.6V.

The Status Register indicates ~the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation.
The RYIBY output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
for example). Status polling using RY IBY minimizes
both CPU overhead and system power consumption. When low, RY IBY indicates that the WSM is
performing. a block erase or byte write operation.
RY IBY high indicates that the WSM is ready for new
commands, block erase is suspended or the device
is in deep powerdown mode.
Maximum access time is 85 ns (tACC) over the commercial temperature range (O°C to + 70°C) and over
Vee supply voltage range (4.5Vto5.5Vand 4.75V to
5.25V). Icc active current (CMOS Read) is 20 mA
typical; 35 mA maximum at 8 MHz.
When the .CE and PWD pins are at Vee, the Icc·
CMOS Standby mode is enabled.
. A Deep Powerdown mode is enabled when the
PWD pin is at GND, minimizing power consumption
and providing write protection. Icc current in deep
powerdown is 0.2~ typical. Reset time of 400 ns
is required from PWD switching high until outputs
are valid to read attempts. Equivalently, the device
has a wake time of 1 p,s from PWD high until writes
to the Command User Interface are recognized by
the 28F008SA. With PWD atGND, the WSM is reset
and the Status Register is cleared.

3-282

_.

£
8

DOo - DC?

!!
a

CE

...CD

C

COI.tI.tAND
USER
INTERFACE

:'"

u).

i\,
CD
U)

UI

0'
n

WE

N

CO
"'II
0
0
CO

Of
PWD

~

tn

~

)0

a

iil
3

RY!BY

Ao-A19 _
Vpp

+- vee
+-GND

II

"@

:w
IiiiiI

290429-1

F
c=

~

c=

~

~

:w
~

intel..

28F008SA

.Table 1. Pin Description
Symbol
Ao-A19.

Type
INPUT

Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during awrite cycle.

INPUTIOUTPUT

DATA INPUT/OUTPUTS: Inputs data and cdmmands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.

CE

INPUT

CHIP ENABLE: Activates the device's control logic, input buffers,
decoders, and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.

PWD

INPUT

POWERDOWN: Puts the device in deep powerdown mode. PWD is
active low; PWD high gates normal operation. PWD also locks out block
erase or byte write operations when active low, providing data
protection during power transitions.

OE

INPUT

OUTPUT ENABLE: Gates the device's outputs through the data buffers
during a read cycle. OE is active low.

WE

INPUT

WRITE ENABLE: Controls writes to the Command User Interface and
array blocks. WE is active low. Addresses and data are latched on the
rising edge of the WE pulse.

DOC-D07

RY/BY

OUTPUT

READYIBUSY: Indicates the status of the internal Write State Machine.
When low, it indicates that the WSM is performing a block erase or byte
write operation. RYIBYhigh indicates that the WSM is ready for new
commands, block erase is suspended or the device is in deep
powerdown mode. RYIBY is .always active and does NOT float to tristate off when the chip is deselected or data outputs are disabled.

Vpp

BLOCK ERASE/BY"fE WRITE POWER SUPPLY for erasing blocks of
the array or writing bytes of each block.
NOTE:
With Vpp < VPPLMAX, memory contents cannot be altered.

Vee

DEVICE POWER SUPPLY (5V ± 10%, 5V ± 5%)

GND

GROUND

3-284

int'eL

28FOO8SA

~ffi1[§[bO[M]OOO~ffi1W

Standard Pinout
~9
A1S
AI?

1
2
3

NC
NC

0

WE
DE

~6
A1S

RY/BY

~4

DO?
D06

A13

STANDARD PINOUT
E28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW

A12

CE
Vee
Vpp

10
11

PWD

~1
~o
Ag

DOs
D04
Vee
GND
GND
D03
D0 2

As

DOl
DOo

A?

Ao

As

Al
A2

As
A4

21

A3

290429-2

Reverse Pinout
NC
NC

WE
DE
RY/BY
D~

D06
DOs
D04
Vee
GND
GND
D03
D02
DOl
DOo

Ao
A,

~V
3
4
5
6
7

10
11
12
13
14
15
16
17
18

~9
~s

0

AI?

~6
A1S
Al4

REVERSE PINOUT
F28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW

~3
Al2
32

CE

31
30
29

Vee
Vpp

28
27
26
25
24
,23
22
21

A2
A3

PWD
All
A10

Ag
As
A?

As
As
A4

290429-3

Figure 2. TSOP Lead Configurations

3-285

28F008SA

o

o
1"1
N

1"1
N

 < :::
0."5

>m;

AC TESTING LOAD CIRCUIT(1)
1.3V

POIHTS

<:::

2.0

lN914

OUTPUT

0.8

290429-11
OUT

AC test inputs are driven at VOH (2.4 Vnu for a Logic "1" and VOL (0.45 Vnu for a Logic
"0". Input timing begins at VIH (2.0 VnL) and VIL (0.8 Vnu. Output timing ends at VIH and
VIL. Input rise and fall times (10% to 90%) < 10 ns.

CL = 100 pF
CL Includes Jig
Capacitance
RL = 3.3 kfi

HIGH SPEED
AC INPUT/OUTPUT REFERENCE WAVEFORM(2)

290429-12

HIGH SPEED
AC TESTING LOAD CIRCUIT(2)
1.3V

290429-17

OUT

AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0". Input timing
begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) < 10 ns.

CL = 30 pF
CL Includes Jig
Capacitance
RL = 3.3 kfi

290429-18

NOTES:
1. Testing characteristics for 28F008SA-85 in Standard configuration, and 28F008SA-120.
2. Testing characteristics for 28F008SA-85 in High Speed configuration.

AC CHARACTERISTICS-Read-Only Operations(1)
Versions

Symbol

-

I
I

Vcc±5%

28F008SA-85(4)
28F008SA-85(5)

Vcc± 10%

Parameter

Notes

tAVAV

tRC

Read Cycle Time

tAVQV

tACC

Address to Output Display

tELQV

tCE

CE to Output Delay

tpHQV

tpWH

PWD High to Output Delay

tGLQV

tOE

OE to Output Delay

2

tELQX

tLZ

CE to Output Low Z

3

tEHQZ

tHZ

CE High to Output High Z

3

tGLQX

tOLZ

OE to Output Low Z

3

tGHQZ

tDF

OE High to Output High Z

3

tOH

Output Hold from
Addresses, CE or OE
Change, Whichever is First

3

Min

Max

85

2

Min

Min

Unit

Max

120

ns

85

90

120

ns

85

90

120

ns

400

400

400

ns

40

45

50

ns

0

0
55

0

0
55

0
30

0

Max

90

28F008SA-120(5)

30
0

ns
ns

0
30

0

ns
55

ns
ns

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE'
3. Sampled, not 100% tested.
4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

3-301

_.
j

Vee POWER-UP

OEVICE AND
ADDRESS SELECTION

STANDBY

,"M'=<~

OUTPUTS ENABLED

DATA VALID

---

I

STANDBY

Vee POWER-DOWN

I I~

ADDRESSES STABLE

--t AVAV

V'H

FE

(E)

---

Vll--'

"II'

iii

...II
c

...

?

):0

V'H

OE (G)

0

---

V1L ...,

==
<

III

II

0'
l.:! ...
0

V1H

c.:I

I\)

3

....

iYE(W)

...

0

J

I,

V'l

XI

1

II
III

a.

VOH

0

'a
II

...
III

".J=:1
tl I I It

HIGH Z
DATA (D/Q)

I.

VOL

0:I

III

j
VALID OUTPUT

.,--

I\)
01)

"'II
0
0
01)

0

>

1

-t\ \ \I\.

HIGH Z

t AVOV

5.0V
Vee

GND

~(')..

•

J

"'HOV _ _ _ _ _ _ _

.,

'\§)
\

2.ID
IffiiI
IF
=
~

~

V,l _

290429-13

~
~

~

intet

28F008SA

AC CHARACTERISTICS-Write Operations(1)

l Vcc±5%
I Vcc±10%

Versions
Symbol

Parameter

tAvAV

twc

Write Cycle Time

tPHWl

tps

PWD High Recovery to
WE Going Low

tElWl

tcs

CE Setup to WE Going
Low

Notes

2

. 28FOO8SA-85(7)
28FOO8SA-85(8)
Min

Max

Min

Max

28FOO8SA-120(8)
Min

Unit

Max

85

90

120

ns

1

1

1

p-s

10

10

10

ns

tWlWH

twp

WE Pulse Width

40

40

40

ns

tVPWH

tvps

VPP Setup to WE GOing
High

2

100

100

100

ns

tAvwH

tAS

Address Setup to WE
Going High

3

40

40

40

ns

tDvwH

tDS

Data Setup to WE Going
High

4

.40

40

40

ns

tWHDX

tDH

Data Hold from WE High

5

5

5

ns

tWHAX

tAH

Address Hold from WE
High

5

5

5

ns

tWHEH

tCH

CE Hold from WE High

10

10

10

ns

tWHWl

tWPH

WE Pulse Width High

30

30

ns
100

tWHOV1

Duration of Byte Write
Operation

5,6

6

6

6

p-s

tWHOV2

Duration of Block Erase
Operation

5,6

0.3

0.3

0.3

sec

tWHGl

Write Recovery before
Read

0

0

0

p-s

0

0

ns

tVPH

VPP Hold from Valid SRD,
RY/BY High

2,6

0

100

ns

tWHRl

tOWl

100

30

WE High to RY /BY Going
Low

I

NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for yalid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard
Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and
erase verify (block erase) .
. 6. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY = VOH). Vpp should be held at
VPPH until determination of byte write/block erase success (SR.3/4/5 = 0)
7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
.
8. See AC InputfOutput Reference Waveforms and AC Testing Load Circuits for testing ~haracteristics.

3-303

28F008SA

BLOCK ERASE AND BYTE WRITE PERFORMANCE
Parameter

Notes

28FOO8SA·120

28FOO8SA·85
Min

Typ(1)

Max

Min

Typ(1)

Max

Unit

Block Erase Time

2

1.6

10

1.6

10

sec

Block Write Time

2

0.6

2.1

0.6

2.1

sec

NOTES:
1. 25°C. 12.0 Vpp.
2. Excludes System. Level Overhead.

3~304

WRITE
Vee POWER-UP WRITE BYTE WRITE OR VALID ADDRESS a: DATA (BYTE WRITE) AUTOMATED BYTE WRITE
a: STANDBY ERASE SETUP CO.... AND
OR ERASECONFIR.. CO....AND
OR ERASE DELAY

ADDRESSES(A~H~

....

\l

READ STATUS·
REGISTER DATA

l

WRITE READ ARRAY
COM ..AND

'~

L

8

VIL
twHAX

VIH

.CE (E)
.VIL
twHGL

l!

ID
C

...

Co)

!-...

1

iiE(G)

CD
....
....

~

;

VIH
VIL

WE

I.

V,H
(W)

twHQV1,2

-I

V,L

~

;g

0

~ 3
UI

...0'

==
=

e
Q

V,H
DATA (D/a) _ _n_"'_n..;;L~__
V.
IL

I-_"
(I

CD

0

1...

a0'
:::I

VOH
RY!BY (R)
VOL

1/1

V,H
PWD (p)
V,L

"@)
'vPWH

5eJ
IiiiiI

IcwvL

'VppH

IF
c:::>
~
c:::I

Vpp (V) VPPL
V,H
V,L

~

IMI\MN\MN\fY'M'Y

~
290429-14 .

~

infel .

28F008SA

ALTERNATIVE CE-CONTROLLED WRITES

I Vcc±5%
I Vcc± 10%

Versions

Symbol

Parameter

tAVAV

twe

Write Cycle Time

tpHEL

tps

PWD High Recovery to CE
Going Low

Notes.

2

28F008SA-85(6)
28F008SA-85(7)
Min

Max

Min

Max

28F008SA-120(7)
Min

Unit·

Max

85

90

120

ns

1

1

1

fLs

tWLEL

tws

WE Setup to CE Going Low

0

0

0

ns

tELEH

tcp

CE Pulse Width

50

50

50

ns

tVPEH

tvps

Vpp Setup to CE Going
High

2

100

100

100

ns

tAVEH

tAs

Address Setup to CE Going
High

3

40

40

40

ns

tOVEH

tos

Data Setup to CE Going
High

4

40

40

40

ns

tEHOX

tOH

Data Hold from CE High

5

5

5

ns

tEHAX

tAH

Address Hold from CE High

5

5

5

ns

tEHWH

tWH

WE Hold from.CE High

0

0

0

ns

tEHEL

tEPH

CE Pulse Width High

25

25

-25

ns

tEHRL

CE High to RY IBY Going
Low

tEHOVl

Duration of Byte Write
Operation

5

6

6

6

fLs

tEHOV2

Duration of BlocK Erase
Operation

5

0.3

0.3

0.3

sec

tEHGL

Write Recovery before
Read

0

0

0

fLs

0

0

0

ns

tOWL

tVPH

Vpp Hold from Valid SRD,
RYIBY High

100

2,5

100

100

ns

NOTES:
.
i. Chip.Ena,ble Conirolled Writes: Write operations are driven by the valid combination of CE and WE. In systems where CE
defines the writ~ pulsewidth (within a longer WE timing waveform), all setup, hold and inactive WE times should be mea·
sured. relative to ttie CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table. 3 for val.id AIN for byte write or block erasure.
4. Refer to T~ble 3 for valid DIN for byte write or block erasure.
5. Byte write. and block erase durations are measured to completion (SR.? = 1, RYIBY = VOH). Vpp should be held at
VpPH until determination of byte write/blockerase success (SR.31 4/5= 0)
.
6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing charClcteris·
tics.
?, See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

3·306

WRITE
Vee POWER-UP WRITE BYTE WRITE OR VALID ADDRESS a: DATA (BYTE WRITE) AUTOMATED BYTE WRITE
a: STANDBY ERASE SETUP COMMAND
OR ERASE CONFIRM COMMAND
OR ERASE DELAY

READ STATUS
REGISTER DATA

l

WRITE READ ARRAY
COMMAND

V1H

8

ADDRESSES (A)
V1L

VIH

ViE(w)

ic

iiJ

!'J

='

V1H

l;
0

-.J

liE (G)
V1L

!.
II
(.)

'rHGL
VI.H

~

S'
...

Co)

VIL

'rHQVI.2

CE (E)
V1L

I

:IE

:!CD
....
0

...

:I

...ct

~
CD

0

'U
CD

~

o

CIt

V1H

~

DATA (D/o)

V1L
VOH
RY!BY (R)
VOL

ill
e;
0

='

'"

V1H

PWD (p)
V1L

"@
iyPEH

2.ID
IiiiiI

'cIVVL

VppH

IF
c::I

~
c::I
zg

VPP (V) VpPL

V1H

~

V1L

290429-15

~

intel~

28F008SA

ORDERING INFORMATION

JEl2lalFlololalslAI-l alsJ
LACCESS SPEED (ns)

TcKAGE
E = STANDARD 40 LEAD TSOP
F = REVERSE 40 LEAD TSOP
PA = 44 LEAD PSOP

VALID COMBINATIONS
E2BFOOBSA-B5
F2BFOOBSA-B5
E2BFOOBSA-120
F2BFOOBSA-120

as ns
120 ns
290429-16

PA2BFOOB5A-B5
PA2BFOOB5A-120

ADDITIONAL INFORMATION
Order
Number
290435

28F008SA-L Datasheet
AP-359

"28F008SA Hardware Interfacing"

292094

AP-360

"25F008SA Software Drivers"

292095

AP-364

"28F008SA Automation and Algorithms"

292099

ER-27

"The Intel 28F008SA Flash Memory"

294011

ER-28

"ETOXTM III Flash Memory Technology"

290412

REVISION HISTORY
Number
002

Description
Revised from Advanced Information to Preliminary
Modified Erase Suspend Flowchart
Removed -90 speed bin
Integrated -90. characteristics into -85 speed bin
Combined Vpp Standby current and Vpp Read
current into one Vpp Standby current spec with two
test conditions (DC Characteristics table)
Lowered VLKO from 2_2V to 2_0V.

3-308

intel·

APPLICATION
NOTE

AP-316

October 1992

Using Flash Memory for
In-System Reprogrammable·
No""Yolatile Storage

SAUL ZALES
.. DALE ELBERT
APPLICATIONS ENGINEERING
INTEL CORPORATION

Order Number: 292046-004
3-309

USING FLASH MEMORY
. FOR IN-SYSTEM
REPROGRAMMABLE
NONVOLATILE STORAGE

CONTENTS

PAGE

1.0 INTRODUCTION ...................
1.1 PROM Programmer vs SystemProcessor Controlled
Programming .................
1.2 Information Download and
Upload .......................
Version Updates (Download) ....
Data Acquisition (Upload) .......
2.0 DEVICE FEATURES AND ISW
APPLICATION
CONSiDERATIONS ..............
2.1 Flash Memory Pinouts ..........
2.2 Command Register
Architecture ..................
Simplified Processor Interface ..
Command Register Reset· ......

3-312

3-312
3-312
3-312
3-312

3~313

3-313
3-315
3-315
3-316

Data Protection on Power
Transitions ................... 3-316
2.3 Vpp Specifications.; ............ 3-317

3.0 HARDWARE DESIGN FORISW ...
3.1 Vpp Generation .................
3.1.1 Regulating Down from
Higher Voltage ..........
3.1.2 Pumping 5V up to 12V .....
3.1.3 Absolute Data Protection Vpp OnlOff Control .....
3.1.4 Writes and Reads during
Vpp Transitions .........
3.1.5 Other Vpp
Considerations ..........
3.1.6 Vpp Circuitry and Trace
Layout ..................

3-317
3-317
3-317
3-317
3-318
3-318
3-318
3-319

3.2 Communications - Getting Data
to and from the Flash
Memory ...................... 3-319

4.0 SOFTWARE DESIGN FOR ISW .... 3-319
4.1 System Integration - Boot Code
Requirements ................ 3-319
4.1.1 ISW Flag Check ........... 3-320
4.2 Communication Protocols and
Flash Memory ISW ........... 3-320
4.3 Data Accumulation Software
Techniques ................... 3-321

3-310

CONTENTS

PAGE

4.4 Reprogramming Routines ....... 3-321
4.4.1 Quick-Erase Algorithm .... 3-321

CONTENTS

PAGE

Algorithm Timing Delays .. 3-321

APPENDIX A:
ON BOARD PROGRAMMING DESIGN
CONSIDERATIONS ................. 3·327

High Performance Parallel
Device Erasure ......... 3-322

APPENDIX B:
Vpp GENERATION CiRCUiTS ......... 3·337

4.4.2 Quick-Pulse Programming
Algorithm .. : ............ 3-323
Algorithm Timing Delays .. 3-323

APPENDIX C:
LIST OF DC-DC CONVERTER
COMPANIES ........................ 3·341

High Performance Parallel
Device Programming .:. 3-323
4.4.3 Pulse Width Timing
Techniques ............. 3-324

APPENDIX 0:
DETAILED PARALLEL ERASE FLOW
CHART .............................. 3·342

Software Methods and
Examples .............. 3·324

APPENDIX E:
DETAILED PARALLEL
PROGRAMMING FLOW CHART .... 3-344

Hardware Methods ........ 3·324

5.0 SYSTEM DESIGN EXAMPLE: AN
80C186 DESIGN ................. 3·325

APPENDIX F:
DETAILED SYSTEM SCHEMATICS ... 3·346

6.0 SUMMARY ......................... 3·326

3·311

AP-316

NOTE:
See Appendix A for OPB design considerations.

1.0 INTRODUCTION
Intel's ETOXTM II (EPROM tunnel oxide) flash memory technology uses a single-transistor cell to provide
in-system 'reprogrammable nonvolatile storage. Reprogramming entails electrically erasing all bits in parallel
and then randomly programming any byte in the array.
This new technology offers designers alternatives· for
two of industry's needs: 1) a cost-effective means of
updating program. code; and 2) a solid-state approach
for non-volatile data accumulation or storage.
This application note:
• introduces you to the concepts of in-system writing;
• discusses the hardware and software considerations
for reprogramming flash memories- in-system;
• offers a checklist for integrating Intel's flash memories into microprocessor- or microcontroller"based
systems; and
• shows an example of an 80C186 design which incorporates flash memory.

1.1 PROM Programmer vs SystemProcessor Controlled
Programming
While soldered to a printed circuit board, one of two
sources controls flash memory reprogramming: 1) a
PROM programmer connected to the board, or 2) the
system's own central processing unit (CPU). These are
called on-board programming (OBP), an" in-system
writing (ISW), respectively. With OBP, the PROM
programmer supplies the programming voltage (Vpp)
and the programming intelligence; with ISW, Vpp is
generated locally and the system itself drives the reprogramming process. Both methods offer a variety of benefits. However this application note focuses on ISW.

1.2 Information Download and Upload
ETOX II flash memory technology programs extremely· quick, permitting "on-the-fly" programming with
unbuffered 19.2K baud data input. The remote ISW
system handles the serial communication link for the
host interface, as well as the flash memory reprogram"
mingo

Version Updates (Download)
Flash memories enable code version updates using sim-'
pIe hardware designs. Beyond the basic system, a local
Vpp supply is all that is'needed for remote code download.
A central host computer can download program code
to many remote systems. Flash memory offers this capability without the drawbacks orother technologies. It
is solid-state and nonvolatile, thus eliminating mechanical component wear-out (common with disk drives)
and the risk of losing updates (a concern with batterybacked RAM). These aspects of flash 'memory offer
major advantages hi automated factories, remote systems, portable equipment and other applications. Finally, flash memories provide this capability at a much
lower cost than byte-alterable EEPROM and batterybacked SRAM.

Data Acquisition (Upload)
Intel's flash memories allow single-byte programming
for data accumulation applications. Aremote data-logger uploads its information to a central host via serial
link. The flash memory device is then in-system erase"

On~Board ~rogramming

In·System Writing

· ...
ii
o IDD
II

. 292046-1

•

V~""

~/~

'-----.s:----"""'-

REMOTE SYSTEM

.

FILE SERVER

292046-2,

Figure 1. These diagrams Illustrate OBP and ISW.ln OBP, a PROM programmer updates a system's
flash memory. The ISW diagram shows a host updating remote flash memory via serial link. The
remote system performs the flash reprogramming with its own CPU.

Intel's ETOX flash memory process has patents pending.

3-312

intel~

AP-316

for resumption of data acquisition. This is useful in an
advanced electrical power meter, for example. It could
be configured to track and monitor power usage and
report the data to a central computer for billing and
utility management. This reduces the cost of manual
door-to-door meter reading.

2.0 DEVICE FEATURES AND ISW
APPLICATION CONSIDERATIONS

2.1 Flash Memory Pinouts
The 32-pin DIP memory site is forward-compatible
from the 256K bit to the 2 Mbit flash memory density.
It fits into the 27COIO Mbit EPROM pinout and requires no multiplexed pins. Also, with just a single circuit'board jumper trace, a 28-pin EPROM can be
placed in the lower pins of the 32-pin flash memory
site. (See Figures 2A llnd 2B, Flash Memory Pinouts.)
For more information on intertechnology pin compatibility see Ap Brief AB-25.

This section gives a brief overview of Intel's flash memory features and explains how they facilitate ISW design.
Byte-Wide Flash Memory in 32-Pin DIP

~

1M (f28Kx8)
512K (64Kx8)
256K (32Kx 8)

NC..!; 2

32 I=lvcc
31 I=l WE

NC..!; 3

30 I::J NC 1- ~ A17

VPPC: 1

+
~

A16

+

r- A15

&

2M (256K x 8)

A12J:: 4

29 I=lA14

A7f 5

28 I=l A13

A6..!; 6

27

A5..!; 7

26

A4 J:: 8
A3

C9

32 PIN DIP
0.800" WIDE 25
TOP VIEW .24

:J
:J
:J
:J

A8
A9
All
OE

A2..!; 10

23 PAlO

Al..!; 11

22 P CE

AO j:: 12

21 PD07

C

20 I=l 006

000

13

DOl..!; 14

19 I::JD05

D02j:: 15

18 I=l 004

Vssj:: 16

17 I=l 003
292046-26

Figure 2A. Flash Memory Pinouts

3-313

inteL

AP-316

Byte~Wlde Flash Memory In 32-Pln PLCC
2M. (256K X 8)
1M (128K X 8)

.

A16
A15

512K (64K X 8)
256K (32K X 8)

A12

NC

NC

Vpp

Vee

WE

0

A14
A13
AS

32-LEADPLCC

A9

0.450" x 0.550"

All

TOP VIEW

Of
Al0

CE
D07

292046-27

Figure2B. Flash Memory Pinouts

3-314

intel .

Ap·316

Table 1. Command Register Instructions
Command

Bus
Cycles
Req'd

First Bus Cycle

Second Bus Cycle

Operaatlon

Addr(1)

Data(2)

Operatlon

Addr(1)

Data(2)
Valid

Read Memory(3)

1

Write

X

OOH

Read

Valid

Read inteligent Identifier

1

Write

X

90H

Read

OO/01H

10.

Set·Up Erase/Erase

2

Write

X

20H

Write

20H

Erase Verify

2

Write

EA

AOH

Read

X
X

Set-Up Program/Program

2

Write

X

40H

Write

PA

PO

Program Verify

2

Write

COH

Read

X

PVO

Reset(3)

2

Write

X
X

FFH

Write

X

FFH

NOTES:.
'
1. Addresses are latched on the falling edge of the Write-Enable pulse.
EA = Address of memory location to be read during erase verify.
PA = Address of memory. location to be read during program verify.
2. EVD = Data read from location EA during erase verify.
PO = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
3. The second bus cycle must be followed by the next desired command register write, given the proper delay

EVO

tim~s.

at system speeds. Once placed in the read mode· no
further action is required on the command register for
subsequent read operations.

2.2 Command Register Architecture
Simplified Processor Interface
Intel's command register architecture simplifies the
processor interface. The command register allows CE\,
WE\, and OE\ to have standard read/write functionality. All commands such as "Set-up Program" or "Program Verify" can be written with standard system tim-·
ings. Raising Vpp to 12V enables the command register
for memory read/write operation, while lowering Vpp
below Vee + 2V restores the device to a read only
memory.
Writing to the register toggles an internal state-machine. The state-machine output controls device functionality. Some commands require one write cycle,
while others require two. The command register itself
does not occupy an addressable memory location. The
register simply stores the command, along with address
and data needed to execute the command. With this
architecture, the device expects the first write cycle to
be a command and does not corrupt data at the specified address. Table I contains a list of command register instructions.
The following sections describe the commands in relation to device operation. For more information on the
command register see the appropriate flash memory
data sheets, and Section 4.4 "Rqlrogramming Routines".

Read Memory Command-oOH
This command allows for normal memory read operations with Vpp turned on. After writing the command
and waiting 6 ,""S, the CPU can read from the memory

Read intellgent Identifier Command-90H
Most PROM programmers read the device's inteligent
Identifier to select the proper programming algoritlim.
On EPROMs, raising A9 to tp,e Vpp level configures
the device for this pUrpose. siitce this is unacceptable
in-system, you can read the flash memory inteligent
Identifier by first writing command 90H. Follow this
by reading address 0000 and OOOIH for the manufacturer and device ID. Reset the device with the Read
Memory command after you have read the identifier.

Set-Up Erase/Erase Commands-20H
Write this command (20H) twice in succession to initiate erasure. The first write cycle sets up the device for
erasUre. The device starts erasing itself on the sec~nd
command's rising edge of Write-Enable. Erasure' is
stopped when the CPU issues the Erase Verify cOmmand or when the device's integrated stop timer times
out. Integrated stop timers provide a safety net for
complex system environments. In these environments,
s/w timer accuracy may be difficult to achieve. Some
method of timing is still required, however the timer
need only meet a minimum specification (10 ms). This
is far easier than calibrating a timer to meet both a
minimum and maximum specification (10 ms
±500 ,""s).

NOTE:
Prior to erasure, it is necessary to program all bytes to
the same level (data = OOH). See the Quick-Erase algorithm for more details.

3-315

intel.

AP-316

device executes this command on the rising edge of
Write-Enable. The program Verify command stages the
device for verification of the byte last programmed. No
new address information is latched.

Erase Verify Command-AOH

The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified to see if they erased. Write the Erase Verify command (AOH)to stop erasure and setup verification.

The flash memory applies an internally-generated reference voltage to the addressed byt!;. Wait 6 p,s for the
internal voltages to settle before reading the data at the
address programmed. Reading valid data indicates that
the byte programmed successfully.

Alternatively, you may allow the internal stop timer to
halt erasure. You must still issue the Erase Verify command to set up verification.
The device latches the address to be verified on the
falling edge of WE\ and the actual command on the
rising edge. Wait 6 p,s before reading the data at the
address specified on the previous write cycle.

Command Register Reset-FFH

Flash memories reset to the read mode during powerup, and remain in this mode as long as Vpp is less than
Vee + 2V. If your system leaves Vpp turned-on during a system reset, then incorporate a command register
device reset into the hardware initialization routines.
This is necessary because the CPU might be controlling
programming or erasure' when the system reset hits.

The flash memory applies an internally-generated reference voltage to the addressed byte. Reading OFFH from
the addressed byte in this mode indicates that all bits in
the byte are erased with sufficient margin to Vee and
temperature fluctuations.

Write the reset command (OFFH) twice in succession
to reset the device. The double write is necessary' because of the state-machine reprogramming structure.
For example, suppose the system is reset after a Set-up
Program command. The flash memory state machine
expects the next write cycle to contain valid address
and data for programming, followed by another write
cycle for program verification. The first Reset command will be mistaken for program data but will not
corrupt the existing data. This is because the command
(data = OFFH)is a null condition for flash memory
programming. Only data bits programmed to zero pull
charge onto the memory cell and change the data. The
second write cycle actually resets the device to the read
function. Following the second reset cycle, you can
write the next command (Read, Program Set-up, Erase
Set-up, etc.).

If the location is erased, then repeat the Erase Verify

procedure for the next address location. Write the command prior to each byte verification to latch the byte's
address. Continue this process for each byte in the array until a byte does not return OFFH data, or the last
address is accessed.
In the case where the data read is not OFFH, perform
'another erase operation. (Refer to Set-up Erase/Erase).
Continue verifying from the address of the last verified
byte. Once you have accessed the last address, erasure
is complete and you can proceed to program the device.
Terminate the erase verify operation by writing another
valid command (e.g., Program Set-up).,
Set-up Program/Program Commands-40H

Write this command (40H) twice in succession to initiate programming. The first write cycle sets up the device for programming. The device latches address and
data on the falling and rising edges of the second write '
cycle, respectiyely. It also begins programming on the
rising edge. You stop the programming operation by
issuing the Program Verify command, or by allowing
the' integrated program stop timer to time out. This
timer works similiar to the erase stop timer. Again, a
minimum specification replaces a tougher minimum/
maximum combination (10 p,s-25 p,s).
Program Verify Command-COH

Flash memory devices program on a byte-by-byte basis.
After each programming operation, the byte just programmed must be verified. Write the Program Verify
command (COH) to stop programming and set-up verificatjon. Should your software allow the integrated stop
timer to halt programming, the software must resume
the algorithm with the Program Verify command. The

If the Vpp supply is turned off upon system reset, the
software reset is not required. The flash memory will
reset itself automatically when Vpp powers down. ,
Data Protection on Power TransitionI!'

The command register architecture offers another benefit in addition to simplified processor interface-during
system power-up and power-down it protects data from
corruption by unstable logic. Erasure or programming
require Vpp to be greater than Vee + 2V and the
proper command sequence to be initiated. For example
the CPU must write the erase command twice in succession. The odds of this occurring randomly are slim.
Additionally, should Vpp ramp to 12V prior to Vee
ramping past 2.5V,)he device will lock out all spurious
writes and internally block 12V from the flash memory
cells. For even greater security, you can switch Vpp as
discussed in Section 3.13.
'

3-316

inteL

AP-316,

• limited amount of RAM for variable storage (i.e.,
stacks, buffers, and other changing parameters)
• data import capability (i.e., serial line, LAN, floppy
disk)
o flash memory for nonvolatile code or data storage
needs
• Vpp generator or regulator

2.3 Vpp Specifications
Flash memories, like EPROMs, require a 12V externally-generated power supply for reprogramming. Intel's
Vpp specifications 12.0V ±O.6V (5%) is compatible
with most off-the-shelf (or available in-system) power
supplies. (Note, Section 3.1 discusses Ypp generation
techniques, and Appendix B shows different circuit alternatives.)
It is essential to use the specified Vpp when reprogramming the flash memory device. Once the command to
erase, program, or ve.rify is issued, the device internally
derives the required voltages from the Vpp supply. The
command register controls selection of internal reference circuitry tapped off of Vpp. An improper Vpp level causes the references to be wrong, degrading the performance of the part.
.

(When programming u.v. EPROMs, Vee is raised to
6.5V. On flash memories, the Vpp reference circuitry
and command register architecture provide the same
function while keeping Vee and Vpp at static levels.
An incorrect Vee level during U.V. EPROM programming poses similar hazards to improper Vpp levels on
flash memories.)
The hardware design section discusses various methods
for generating Vpp.

3.0 HARDWARE DESIGN FOR ISW
Covered in this section are the following:
• Description of ISW -specific functional system
blocks including memory requirements

All of the functional blocks in Figure 3 are typical of
any embedded or reprogrammable system with the exception of the Vpp generator. Some microcontrollers
have on-chip EP /ROM, RAM and a serial port. With
these devices, implementation of the ISW capability requires little additional hardware.
The next section discusses Vpp generation techniques
and communications design considerations.

3.1 Vpp Generation
A static Vpp is needed to reprogram flash memories.
The Vpp voltage can be generated by:
1) regulating it down from a higher voltage;
2) pumping it up from a lower voltage (i.e., charge
pump, DC/DC converter, etc.); or
3) designing or specifying the system's 12V supply
with the required ISW tolerances and specifications.
Sufficient current for reprogramming should be considered when selecting your Vpp generation option. Parallel reprogramming for flash memory in 16-bit or 32-bit
systems will require, respectively,2X or 4X additional
current capability.
3.1.1 REGULATING DOWN FROM HIGHER
VOLTAGE

• Vpp generation techniques
• Communication Considerations

Vpp is obtained from a higher voltage by using a linear
regulator. Given the higher voltage, regulation offers
the least expensive method of generating V pp. Standard
three terminal 12V ± 1%, ±2%, ±4% non-adjustable
regulators are available off-the-shelf. Some regulators
have on/off control built-in. (See Appendix B, Vpp Circuit # 1.) All regulators require a minimum input voltage greater than the output voltage. (See Appendix B,
Vpp Circuit #2 and #3.)
.
3.1.2 PUMPING 5V UP T012V

292046-6

Figure 3. System Block Diagram
System Level Hardware Requirements for ISW:

• processor or controller
• limited .amount EP/ROM . or other flash memory
devices for boot code, communications s/w, and reprogramming algorithms

Vpp can be obtained by pumping Vee and regulating it
to the proper voltage. A voltage charge-pump can be
designed and built by using a charge-pump integrated
circuit and some discrete components (see Appendix B,
Vpp Circuit #4) or by using a monolithic DC/DC con.
verter (see Appendix A, Vpp Circuit #5).
When using adjustable circuits containing discrete components, design the output voltage so it falls within the
Vpp specifications for all corners of the components'

3-317

int'et

AP-316

~kew (i.e., Vee ± 10%; Rx ±I I %, Ry ± I %, etc.). Include the resistors' temperature coefficients in the calculation matrix. Note that each of the various components can add error to the Vpp supply.
The monolithic DC/DC converter shown in Appendix
B Circuit # 5 fits into a 24-pin socket. It offers the
advantages of close temperature tracking and ease of
implementation. It has also been characterized at temperatures and meets all the Vpp specifications. Appendix C contains a partial list of vendors selling DC/DC
converters.
Most DC/DC converters are only 50-60% efficient, so
heat dissipation may be a concern. Some discrete boost
circuits such as Appendix B, Circuit #4, offer much
higher efficiency (70-85%). Circuit #4 as shown can
supply 200 mAo Smaller inductor and capacitor component values and higher frequency boost convertors can
be used where less power is required; For example, designs which reprogram one or two' flash memories'
simultaneously might use the LTll72. (Contact Linear
Technologies for more information.)
In all Vpp generation methods, a capacitor on the input
voltage terminals reduces the output noise voltage.
Some power supplies (Appendix B, Circuits # 3 and
# 4) specify a large-valued capacitor to decrease the Effective Series Resistance (ESR). Place a 0.1 ,..,F capacitor within 0.25 inches of each flash memory's Vpp input (in addition the one on the Vpp generator's input).
NOTE:
The ESR is inversely proportional to the capacitance
value and the rated working voltage. To. lower the
ESR choose a capacitor with a large capacitance and a
high working voltage (i.e., above looV).
3.1.3 ABSOLUTE DATA PROTECTIONVpp ON/OFF CONTROL

With Vpp below Vee +2V or Vee below 2.5V,
internal. circuitry disables the command register' and
eliminates the possibility of inadvertent erasure or
programming. Switching theVpp supply' off provides the secondary benefits of improved power and
thermal. management.
There are two ways to switch Vpp on and off:
I) directly switch the Vpp generator's output, or
2) switch the input voltage supplying the regulation
circuit.
Any switching· circuit will cause a voltage drop, so
choose a switch with this drop in mind. Some power
supplies have asymmetrical tolerances on 12V (i.e.
+ 5%, -4%). Flash memory allows the 12V supply to
drop as low as - 5%. The I % difference between the
supply and the device requirement allows the switch to
have an ON resistance voltage drop of 0.12V. Continuing with this example, assume the system only repro~
grams one flash memory at a time. The current through '

the switch into the flash is Ipp = 30 mAo Solving for
the allowable resistance across the switch: R = V/1 =
(0.12V)/(30 mA) ~ 4 Ohms. See Figure 4. Example
Voltage Drop Across Switch. Note, one can reduce the
effective Ros (ON) by placing 2 or more FETs in parallel if necessary.

Ipp

=30 rnA

Vpp

= (12V-4%)

- (30rnA)(4,ll)

= 11.4V = 12V-5%

292046-38

Figure 4

Controlling the input voltage of a DC/DC convertor
with a MOSPOWER FET is another straightforward
approach. (See Appendix B, Circuit #5.) Choose the
FET switch carefully. It should have a very low on-resistance to minimize the voltage divider effect of the
converter and FET switch. If the voltage across the
FET switch is too high, the converter will not have the
proper input voltage to meet its specifications. Always
design the. switching circuit with sufficient margin to
maximum Vpp and Vee load currents.
3.1.4 WRITES AND READS DURING Vpp
TRANSITIONS

After switching Vpp off, the CPU can read from the
flash memory without waiting for the capacitors on
Vpp to bleed off. To do this, write the Read Memory
command prior to issuing the Vpp_OFF instruction.
Alternatively, the device resets automatically ,to read
mode when Vpp drops below Vee + 2V.
Raising Vpp to 12V enables the command register. You
must wait 100 ns after Vpp achieves its steady state
value before writing to the command register. Remember that the steady state Vpp settling time depends on
both the power supply slew rate I}nd the capacitive load
on the Vpp bus.
3.1.5 OTHER Vpp CONSIDERATIONS

The Vpp pin is an MOS input which can be damaged
by electrostatic discharge (ESD). In OBP applications,
an external power source supplies Vppand then is removed. Electrostatic charge can build up on the floating Vpppin. You can solve this problem by one of two
means: I) tie the pin to Vee through a diode and pullup resistor (Figure 5a) or through a resistor to ground
(Figure 5b). With either approach use a 10 K!1 or larger resistor to minimize Vpp power consumption.

3-318

AP-316

3.2 Communications-Getting Data to
and from the Flash Memory

Vpp Plno::!:! 14 ~vcc
c
R = 10kll vpp

J.

The flash memory does not care about the origin of the
data to be programmed. The data could be downloaded
from a serial link, parallel link, disk drive, or generated
locally as in data accumulation applications.

292046-7

a.Vpp Tied to Vee for OBP

Vpp Pln;f lOVPP
292046-6

b. Vpp Tied to Ground

Figure 5
.NOTE:
Typically EPROMs require Vpp to be within one diode drop of Vee for optimal standby power consumption. Either approach can be used with the. flash memory.

ISW applications do not require this ESD protection as
most regulators and charge pumps contain a voltage
divider on the output stage. A divider provides a resistive path to ground even with the supply turned off,
(Note: check the schematics of the Vpp supply chosen.)
However, if you directly switch the Vpp supply, add
the resistor to ground; the switch isolates the Vpp pin
and allows charge to build up.
3.1.6 Vpp CIRCUITRY AND TRACE LAYOUT

You should layout Vpp circuitry and traces for high
frequency operation since programming power characteristics.exhibit an AC current component. Use the following standard power supply design rules:
• Keep leads as. short as possible and use a single
ground point or ground plane (a ground plane eliminates problems).
• Locate the resistor network (or a regulator) as close
as possible to the adjustment pin to minimize noise
pick-up in the feedback loop. The. resistor divider
network should also be. as short as possible to mini..
.
mize line loss.
• Keep. all high current loops to. a minimum length
using copper connections that areas wide as possible. (This will decrease the inductive impedance
which otherwise causes noise spikes.)
• Place the voltage regulator as close to the flash
memory as practical to avoid an output ground
loop. Excessive lead length results in an error voltage across the distributed line resistance.
• Separate the input capacitor return from the regula"
tor load return line. This eliininates an' input ground
loop, which could result in excessive output ripple.

While most systems communicate via serial link, sending a font io a printer's flash memory is an example of a
. parallel interface. In either format, designers must decide whether or not to buffer the incoming data; Errorfree serial protocols will require buffering for reconstruction of information packets. With equal capacity
of RAM and flash meinory in a system, the download
time would only be limited by the speed of the communication link.
Both worst case and typical analysis must be done for
real time download and un-buffered programming. The
maximum transmission rate is J9.2K baud assuming
worst case programming times. The time between characters at 19.2K baud is 520 Ils; the worst case byte
programming time is approximately 0.5 IDS (including
software overhead). Typical byte programming takes
16 Ils which allows for much higher unbuffered transmission rates. However, a single byte can take up to the
full 400 Ils specified time (plus software overhead), so
you should not base transmission rate on typical program!ping times.
Partial buffering or FIFO schemes can also be implemented to increase transmission rates. An argument for
buffering is reduction of interconnect time and costs.

4.0 SOFTWARE DESIGN FOR ISW
Covered in this section are the following software requirements:
• system integration of ISW
• reprogramming considerations for single- and multiple-flash'inemory based designs.

4.1 System Integration~Boot Code
Requirements
Boot code in remote systems should contain various
ISW -specific procedures in addition to standard initialization and diagnostic routines.
The most dependable boot code for remote version updates contains some basic communicatioris capability
and the ISW reprogramming algorithms. Thus; a datalink disruption while reprogramming would be recoverable. For manufacturing flexibility, this boot memory
.
could be an OBP 256K flash memory.

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intel"

AP-316

1. Bootstrap, and reset flash memory;
2. Check "HOST_INT" and "VALID_AP"
flags:
If HOST_INT is inactive andVALID~P
= 4150H, jump to application start address;
3. IfVALID~P<>4150H, loop and wait
for host (the link probably went down during
update);
4. When "HOST~NT" is active, vector to
hostinteraction code.
(See next section.)

292046-9

Figure 6. Example of ISW Integration to the Boot Sequence

An alternative to. storing these routines in a separate
boot device is storing them in the flash memory containing the program .code. Prior to erasure, the CPU
would transfer the ISW routines to system RAM and
execute from there. This typ~of approach is suitable for
battery-operated equipme'!-t or systems \Yith back-up
power supplies.
The communication Iirik could be disrupted during reprogramming, leaving the device in an unknownconfiguration. Therefore, the boot code should reset the flash
memory and check two ISWflags. The following section discusses the flag check concept.
.
4.1.1 ISW FLAG CHECK

After resetting the flaSh memories and initializing other
system components, the CPU should check the communications link for a host interrupt. We will call this
the HOST_INT flag. Had the communication link
gone down prior to completion of downloading, then
the host would have to .re-establish contact to complete
the task.
Assuming no HOST~NT request has been made, the
boot protocol then checks a data sequence in the .flash
memory si~fying a valid application (VALID~P).
You program this sequence into the memory array after
confirmation of a successful download. If a download is
. interrupted midway through erasure or programming,
then the VALiD~P flag locations will not contain
the VALID~P code. On the next system bootstrap
the.CPU recognizes this and holds up system boot until
valid code is programmed. In Figure 6 an example flag
protocol uses the VALID~P sequence of 4150H
(ASCII codes for HAP").

structions and program code. This protocol· can be· as
simple as a ·read-back technique or as complex as an
error-free transmission protocoL (See Figure 7 for possible system-level flash memory instructions.)
A simple read-back technique optimizes download for
boot code memory needs and ease. of implementation.
The embedded CPU echoes the flash memory instruction(i.e., Erase or Program) to thebost, and waits for a
confirmation prior to execution. After programming
the update, the remote system checks the update by
transmittingit back to the host for confirmation. The
remote system then programs the. VALID~P sequence. Note that programming and reading back
64 Kbytes at 19.2K baud takes about 0.57 minutes per
direction:
(65,536 bytes) • (10 bits/byte) • (1 sec/19.2 Kbits) •
(1 min/SO sec) = 0.57 minutes.

Implementing either software- or· hardware-based error-free communications protocol improves transmission efficiency. It eliminates the possibility of errant
data being programmed if not buffered and checked,
and optimizes the download process for transmission
time; Additionally, file compression and decompression
routines can improve the transmission rate.
General ISW InstructIons Include:
. STATUS CHECK
INITIATE REPROGRAMMING
..
.
MOVE ISW. ROUTINES FROM FLASH MEMORY TO RAM
(If not resIdent In separate boot memory)
Data accumulatlon~speclflc commands Include:
RETRIEVE DATA
ERASE FLASH MEMORY

Figure 7. Sample System-Level
ISW Instruction Set

4.2 Communication Protocols and.,
Flash Memory ISW
.The remote download communications protocol must
guarantee accurate. transmission of flash· memory in-

3-320

AP-316

Status Check
The host should request a status update from the remote system prior to sending a reprogramming instruc,tion. Depending on the response, the host may break.
the link and reconnect later, or it may send an erasure
or data-upload command. This type of handshaking is
necessary when system downtime for reprogramming
might not be acceptable. An example of this is an automated factory where robots handle caustic chemicals.

NOTE:
Contact your nearest sales office for details.
If you prefer to implement the algorithms yourself, they
are outlined in the device data sheets. Command register instructions required for the various operations are
included in the data sheet flow charts.
The following sections describe both single-device and
multiple-device parallel reprogramming implementations.

4.3 Data Accumulation Software
Techniques

4.4.1 .Qulck~Erase Algorithm.

Data can be accumulated in a remote environment with
flash memory and then uploaded to a host computer for
manipula:tion. You can adapt various standard datalogging techniques for use with flash memory. With
any technique, you determine the next available memory location by reading for erased data (OFFH). This'
, address would only be located once on system bootstrap and then reciilled from RAM and incremented as
needed. '
Given arepeatili.g data string of known length and
composition, program start and stop codes at either end
of the string. Do not pick OOH or OFFHdata for these
codes because they are used during erasure. The start
and stop codes enable the CPU to differentiate between
available memory for logging and logged data equal,to
OOH or OFFH.
'
For non-regular data input, you can address this same
issue by programming the logged data followed by the
variable identifier. Again, do not pick OOH or OFFH
data for the variable identifiers.
With any technique, the host computer separates and
manipulates the data after the ,uploading operation.

4.4 Reprogramming Routines
Intel's, ETOX, flash memories provide a cost-effective
updatable, non-volatile code storage medinm. The reliability and operation of the ,device is based on the use of
specified erasure and programming algorithms.

Flash memories chip-erase iill bits in the array in parallel. The erase time depends on the Vpp voltage level
(11.4V-12.6V), temperature, and number of erase/
write cycles on the part. See the device data sheets for
specific parametric influences on reprogramming times.

Note that prior to erasing a flash memory device the
processor must program all locations to GOH. This equalizes the charge on all memory cells insuring uniform and
reliable erasure.
Algorithm Timing Delays
The Quick-Erase algorithm hasthree different time delays:
1) The first is an assumed delay when Vpp first turns
on. The capacitors on the Vpp bus cause an RC
ramp. After switching on Vpp, the delay required is
proportional to the number of flash memory devices
times 0.1 p.F/deVice. Vpp must reach its final value
100 ns before the CPU writes to the command register. Systems that hardwire Vpp to the device can
eliminate this delay.
2) The second delay is the "Time Out TEW" function,
where TEW is the erase timing 'width, The function
occurs after writing the erase command (the second
time) and before writing the erase-verify command:
The erase-verify command or the integrated stop
timer internally stops erasure.
.
TEW for ETOX II flash memories is a minimum of
10 ms. This delay can be either software or hard- .
ware controlled. Either way, the minimum nature of
the timing specification allows for interrupt-driven
timeout routines. Should the interrupt latency be
longer than the minimum delay specification, the
stop timer halts erasure.

,

Intel offers reprogramming software drivers to make it
easy for you to design, and implement flash memory
applications. The software is designed around the CPUfamily architectures and requires minimal modification
to defme your system parameters. For example, you
supply .th~ memory width (8-bit, 16-bit, or 32-bit), system timing, and a subroutine for control of Vpp. '

3) The third delay in the erase algorithm is a 6 p.s time
,out between writing the erase verify command and '
reading for OFFH. During this delay, the internal
voltages of the memory array are changing.from the

\
/

3-321

AP-316

erase levels to the verify levels. A read attempt prior
to waiting 6 fJ.s will give false data-it will appear
that the chip does not erase. Repeatedly trying to
erase verify the device without waiting 6 fJ.s will
cause over-erasure. This delay is short enough that
it is best handled with software timing. Again, note
that the delay specification is a minimum.

High Performance Parallel Device Erasure
In applications containing more than one flash memory, you can erase each device seriaIJy or you can reduce
total· erase time by implementing a paraIJel erase algorithm.7 You save time by erasing all devices at the same
time. However, since flash memories may erase at different rates, you must verify each device separately.
This can be done in a word-wise fashion with the command register Reset command and a special masking
algorithm.
.
Take for example the case of two-device (paraIJel) erasure. The CPU first writes the data word erase command 2020h twice in succession. This starts erasure.
After 10 ms, the CPU writes the data word verify command AOAOh to stoP. erasure and setup erase verifica-

tion. If both bytes are erased at the given address, then
the CPU increments the address (by 2) and then writes
the verify command AOAOh again. If neither byte is
erased, then the CPU issues .the erase sequence again
without incrementing the address.
Suppose at the given address only the low byte verifies
FFh data? Could the whole chip be erased? The answer
is yes. Rather than check the rest of the low byte addresses independently of the high byte, simply use the
reset command to mask the low byte from erasure and
erase verification on the next erase loop.. In this example the erase command would be 20FFh and the verify
command would be AOFFh. Once the high byte verifies
at that address, the CPU modifies the command back
to the default 2020h and AOAOh, increments the address by 2,.and writes the verify command to the next
address.
See Figure 8 for a conceptual view of the parallel erase
flow chart and Appendix D for the detailed version.
These flow charts are for 16-bit systems and can be
expanded for 32-bit designs.

RAISE: Vpp
PROGRAM ALL DEVICES TO OOh
RESET ALL VARIABLES
ISSUE ERASE COMMAND -----';--------,
TIME OUT
VERIFY COMMAND
[

BOTH DEVICES ERASED

IY
N LAST ADDRESS

Iy

DONE

....!::!.... MASK·

HI-OR LO-BYTE
COMMANDS
LAST PULSE

Iy

-'!-

ERROR

• YOU MASK THE DEVICE BY SUBSTITUTING A RESET COMMAND
FOR THE ERASE & VERIFY COMMANDS. THAT WAY THE
ERASED BYTE IDLES THROUGH THE NEXT ERASE LOOP.

292046-28

Figure 8_ High Performance Parallel Eras\:Ire (Conceptual Overview)

7. Parallel Erasure and Programming require appropriate choice' of Vpp supply to support the increased power consumption.

intel~

AP-316

• The second delay is the "Time Out 10 /-l.s" function,
which occurs after writing the data and before writing the program:verify command. This write command internally stops programming. The section entitled "Pulse Width Timing Techniques" gives 86family assembly code for generating a 10 /-l.s timer
routine.

4.4.2 Quick-Pulse Programming Algorithm
Flash memories program with a modified version of the
Quick-Pulse Programming algorithm used for U.V.
EPROMs. It is an optimized closed-loop flow consisting of 10 /-l.s program pulses followed by byte verification. Most bytes verify after the first pulse, although
some may require more passes through the pulse/verify
loop. As with V.V. EPROMs, this algorithm guarantees a minimum of ten years data retention. See the
device data sheets for more details on the programming
algorithm.

Algorithm Timing Delays
The Quick-Pulse Programming algorithm has three different time delays:
•. The first and third-Vpp set-up and verify set-up
delays-are the same as discussed in the erasure section. In this case the third delay is for the transition
between writing the Program Verify command and
reading for valid data.

High Performance Parallel. Device Programming
Software for word- o.r double-word programming can
be written in two different manners. The first method
offers simplicity of design and minimizes software overhead by using a byte programming routine on each device independently. Here you increment the address by
2 or 4 when addressing 1 of 2 or 4 devices, respectively.
The second method offers higher performance by programming the word or. double-wor~ data in parallel.
This method manipulates the command register instructions for independent byte control. See Figure 9
for conceptual 2-device parall,el programming flow
chart and. Appendix E for the detailed version.

Ad:r~::/~:1a

Gel
Word
Resel Command and
Counler VarlableB
ProgramOala
, Word

_-----_+-----,

1

TlmeOrl0!'.

Slop Programming with
Program verily command

1 .
1

N
Mask HI Dr LoByie
Dala Word Programmed?-+Incremenl Pulse Counler
y LaBI PulBe?
N

I

0:_,
y

iN

.

.

Wrlle Read command Wrlle Read command
LowerVpp
LowerVpp
Program .Error
Programming Complete

.

.

292046-11

'You mask the device by substituting a Reset command for the Program and Verify commands. That way, the programmed bytes do not get further prog~ammed on subsequent pulses.

Figure 9. Parallel Programming Flow Chart (Conceptual Overview)

3-323

AP~316

NOTE:
Word or double-word programming assumes 2 or 4
8-bit flash memory devices.

LOOP instruction takes 16 clock cycles to execute per
pass. It decrements the CX register on each pass and
jumps to the specified operand until CX equals zero.

Parallel Programming Algorithm Summary:
• Decreases programming time by programming 2
flash memories (16 bits) in parallel. The algorithm
can be expanded for 32-bit systems.
• Eliminates tracking of high/low byte addresses and
respective number of program pulses by directing
the CPU to write data-words (16-bit) to the command register.
• Maintains word write and word read operations.
Should a byte on one device program prior to a byte
on the other, the CPU continues to write word-commands to both devices. However, it deselects the
verified byte with software commands. An alterna.tive is to independently program high and low bytes
using hardware select capability.

When writing a delay loop consider all instructions between the. start and end of the' delay. If a. macro is
written that delays 10 JLs, add the clock cycles for all
instructions in the macro.
Here is an example of a 10 JLs delay and the calculation
of the constant required for a 10 MHz .8OCI86.
WAIT__ IO JLs:
push cx
mov cX,DELA Y
loop $
pop cx
I. Start to End

;10 clock cycles
;4 clock cycles
;see calculation
; 10 clock cycles

10 JLs/cycle time
= 10 JLs/IOO ns

100 cycles

4.4.3 Pulse Width Timing Techniql!es

2. Loop Instruction = 100-24 cycles
= 76 cycles

Software or hardware methods can beused to generate
the timing required for erasure and programming. With
either method you should use an in-circuit emulator
(ICETM) and an oscilloscope to verify proper timing.
Also remove the flash memory device from the. system
during initial algorithm testing.

.3. Loop Cycles

= 76
= (15 X [DELAY

-11 + 5)

4. Solving for DELAY = 6

Software Methods and Examples

Software loops are easily constrncted using a number of
techniques. Timing loops need to be done in assembly
language so that the number of clock cycles can be
obtained from the instructions.
In order to calculate a delay loop three thi~gs are needed-.
I) processor clock speed,
2) clock cycles per instruction, and
3) the duration of the delay loop.
As an example, the 80CI86 divides the input clock by
2. With a 20 MHz input clock the processor's. internal
clock runs at 10 MHz. This translates to. a 100. ns cycle
; time. Delays can be made by loading the CX register .
with a count and using the LOOP lnstruction. The

Hardware Methods

Using an Internal Timer~
Many microcontrollers and some microprocessors have
on-chip timers. At higher input clock speeds these internal timers have a resolution of I JLs or better. The
timers are loaded with a count and then enabled. The
timer starts counting, and when it reaches the terminal
count a bit is set. The CPU executes a polling algorithm
that checks the timer status. Alternatively, a timer-controlled interrupt can be used. After the timer has been
set and the interrupt enabled, the CPU can be programmed towaitin idle mode or it could continue executing until the timed interrupt.

3-324

infel .

AP-316

One thing to take into account when using interrupts is
the time required for the CPU to re~ognize and interrupt request (interrupt latency). This is important when
figuring the timer value; because the time seen by the
part will be the programmed delay plus the minmum
interrupt latency time.

Boot

Application

MCSO

LCS

5.0 SYSTEM DESIGN EXAMPLE:
A~ 80C186 DESIGN
A general purpose controller and/or data acquisition
system was built to demonstrate 86-based ISW. The
80C186 CPU drives the system, which contains
16 Kbytes of EPROM (two 27C64's), 64 Kbytes of
flash memory (two 28F256A's), 64 Kbytes of SRAM
(two 32K x 8's) three 8-bit ports (82C55A), one serial
port (82510), and a 5V to 12.0V DCIDC converter.
Three 74HC573's demultiplex the address/data bus
,and latch the byte high enable line (BHE) and the
status lines (if needed). Two data transceivers
(74HC245) simulate the worst case data path for a system requiring added drive capability. Ifthe tr~sceivers,
are not needed they can be replaced with wired headers.
See Appendix F fcir detailed schematics parts list, and
changes for the 28F512 or 28FOl.O.
,

,

The8OC186 reset (output) drives the reset input on the
82510, 82C55A, and the OE\ inputs on the address
latches and data transceivers. The reset line' goes mactive 5 clock cycles before the first code fetch: Also, the'
CPU's write signal is split into byte-write-high and
byte-write-Iow to allow for byte or word writes.
The 8OC186 has on-chip memory and peripheral chip
selects. Two of the memory chip selects are dedicated.
One is the Upper Chip Select (UCS, dedicated for the
boot area) and the second is the Lower Chip Select
(LCS, for the interrupt vector table area). See the memory map in Figure 10.

Version update code,
Data Accumulation storage,
etc.
40000H

RAM

Using an ExteniaI TimerExternal timers can take many forms. One popular example is the 82C54 (CHMOS Programmable Interval
Timer) which has three 16-bit timers on-chip. One timer can be used' as a prescaler for the others so that a
count of 2·32 can be, achieved as with the 80C186 internal timers.

FCOOOH

UCS

The, 80C186 has three 16-bit timers on-chip. Timer #2
can be a prescaler for the other two timers, which extends timers #0 and # 1 range out to 2·32.' By using
two timers, lOlls pulses and 10 ms pulses' can be easily
achieved.

Initialize H/W, Cotnm,
flash memory algo's, etc.

Vector table, Stack,
Buffers, etc.
0000

Figure .10. 80C186 Memory Map

The permanent code was placed in an EPROM in the
UCSmemory segment; this code includes routines for
hardware initialization, communications, data uploading and downloading, erasure and programming algorithms, I/O drivers, ASCII to binary conversion 'tables,
etc. This would be useful for systems reconfigured for
different communication protocols as the last step prior
to shipment.
Code and constants that might change are placed in th~
, 64 Kbytes of flash memory. Application examples include operating systems, code for rapidly advancing
biomedical'technologies such as blood test software, engine-control code, and parameters,character, fonts for
printers, postage rates, etc. The RAM is used for the
interrupt table, stack, variable data storage, and buffers.
The, three 8-bit ports on the 82C55A peripheral controller can, be used for control and/or data acquisition.
It powers-up with all port pins high. Similarly, all port
pins go high after, warm resets as well. Because the pins
are high after a power-up/reset, an open cplleetor invertor was used to control the MOSPOWER switch
which in turn controls Vpp. You must drive the FET
switch to one rail or the other to guarantee its low onresistance. Vpp is turned off during power-up or reset
as a hardware write protection solution. The DCIDC
converter supplies Vpp.
The 82510 is a flexible single channel CHMOS UART
offering high integration. The device qff-Ioads the system and CPU of many tasks associated with asynchrono~s serial communications.
'

3-325

infel·

AP·316

The part can "be used as a basic serial port for the hOst
serial link, or can .be configured to support high speed
modem applications. For more info~ation on the
82510 see the 82510 data sheet and AP-401 "Designing
. with the 82510 Asyn"hronous Selial Controller".
Software was wntten' to download code and data pa.rameters (code updates) from a PC to the denio board
through .the PC's COM! port (serial port). The system
also can upload data (remote data acquisition) to the
PC via the same link.
Once the download code and' data has been programmed it can not be lost, even if power should fail.
,This is because Intel's ETOX 11 flash memory technology is based on EPROM technology and does not heed
power to retain data.
.
The end result: rugged, solid staie, low power nonvola~

tile storage.

6.0 SUMMARY
Intel's flash memories offer designers cost-effective. al"
ternatives 'for' remote version updates ·or for reliable
data accumulation in the field or factory. Designers will
also benefit from time savings in any kind of code development-no 15 minute waits for U.V. EPROM erasure.
This appliCation note covers the basics of in-sysrilm
writing to flash memories and can be used as 'a check
list for systems other than the 8OC186 design shown~
The basic concepts remain the same: a CPU controls'
the reprogrammingoperatioris; a f2V supply must be
applied to the flash memory for erasure and, programming; and a communications link ,connects the'host.to
the remote. system and supplies the· code to be programmed.
'

'

\

\.

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APPENDIX A
ON-BOARD .PROGRAMMING DESIGN
CONSIDERATIONS

3-327

AP·316

This appendix:
• outlines the design considerations associated with
on-board programming, and the improvements afforded by Intel's flash memory;
,
• offers guidelines for converting current 64K
EPROM OBP tlesigns;
• designs 1m 8-bit system for on-board programming;
• suggests some 16-bit flash design considerations;
and offers information on OBP equipment and vendors.

INTRODUCTION
On-board programming' (OBP) with Intel's flash
memory provides designers with cost reduction capabilities for alterable code storage designs. When used in
conjunction .with on-board programming, flash memory presents opportunities for savings in two areas:
greater testability in the factory, which translates to
improved outgoing quality and reduced return rate; and
quicker, more reliable field updates, which translates to
decreased product support cost:

1. With on-board programming, non-volatile memory is programmed while socketed or soldered on the application board,
rather than before hand as a discrete component. This programming method is also called in-module or in-circuit programming, and has been practiced by some major corporations since 1981. See sidebar. on following pages for more information
on U.V. EPROM OSP usage. .
.

HOST APPLICATION
(Printer Shown Here)

BOARD-PROGRAMMER

-(

)
292046-29

On-Board Programming Manufacturing Example-A printer is customized via OBP for international markets:
1. printer assembly completed, diagnostics code programmed and tested, and unit stored in inventory; 2. order
arrives for printer with foreign langUage font; 3. diagnostics code flash-erased, and desired font programmed; 4.
printer ships to customer.

INTEL'S FLASH MEMORY-DESIGNED
TO MEET YOUR OSP NEEDS

5 Volt Vee Erasure and Programming
.
Verification

Intel's flash memory simplifies OBP code updates by
offering. designers the command register architecture.
As described in section 2.2, this architecture offers the
full reliability of EPROM off-board programming
without the hassles of elevating Vce.

Unlike EPROM' OBP, flash !Demory enables Vcc to·
remain at S.OV throughout all operations. Internal circuitry derives the erasure and programming· verification
levels from the voltage on Vpp rather than from Vcc.
These verify modes enable use of a single Vcc bus for
the entire board, as opposed to th~ two buses needed for
U.V. EPROM OBP. (See sidebar entitled EPROM
OBP).

3-328

intel .

Ap·316

programming control and access. The PGM and WE
lines can be common if the board programmer can give
the appropriate timings to either type of device.

REPLACING CURRENT EPROM OBP
DESIGNS WITH FLASH MEMORY
Hardware Considerations

Software Considerations

A slight hardware modification is required to adapt
most of the current EPROM OBP designs for use with
Intel's flash memory. Simply convert the EPROM
memory sites from 28 to 32 pins. All other board-design cirteria used for EPROM OBP apply to flash
memory as well. (For discussions of these criteria see
section entitied New OBP Designs).
Standard EPROM OBP requires the board designer to
bus PGM to the edge connector. With flash memories'
command register architecture, this same trace enables
electrical erasure and pro~ming, only now the line
is called Write Enable (WE). The timing for WE is
similar to that of read accesses, ~Ithough that is handled via software changes.
Another potential hardware change is on the board
programmer side of the design-the Vpp supply. Many
EPROMs program with 12.S-13.0V Vpp supplies. Intel's ETOX II flash memory requires IJ.4-12.6V Vpp.
This change should not be an issue since the Vpp supply on many board programmers is programmable.
Mixed memory systems containing both conventional
U.V. EPROM and flash memories require special consideration. This type of memory design requires separation of the Chip Enable (CE) control lines between the
EPROM and flash devices. to allow for independent re-

Manufacturers who program EPROMs on-board today
will need new board-programmer software to take advantage of flash memory's feature set, specifically software for the Quick-Erase and Quick-Pulse Programming algorithms.

Benefits of Converting Your EPROM OBP
Design to Flash
The most pressing reason to convert from a standard
EPROM to flash memory is the total cost savings. To
appreciate this, you must consider your way of doing
business at the board and system levels-from the factory to installation and repair in the field. In the factory, boards can be tested with a diagnostics program in
the flash memory and then erased and reconfigured for
shipment in the same step. Improved testing will decrease the probability of field failures and costly customer returns. Simplified test and rework methods will
decrease your inventory holding costs. Also, if in the
process of converting to flash memory you include the
ability to OBP via a cable-connector, service calls for
code updates will be quicker, more reliable, and cost
less money. Your serviceman would simply connect the
programming equipment to the system without dismantling it to remove the EPROMs. (See section entitled
The System/Board-Programmer H/W Connection for
details.)

3-329

Ap·316

NEW cBP DESIGNS
Design Considerations
As with EPROM in-circuit programming, flash memory board programming requires the use of a board-programmer. UiIlike. U.V. erasure for standard EPROM
OBP, electrical erasure enables flash memory OBP
without removing the board from the system.

We will look at designing a board that is to remain powered-up in the system during erasure and reprogramming. The key concept is to design the board in such a
way that the programmer can take control of the system
during code updates. The implementation of such a design is straightforward, easy, and suited to automated
production assembly.

Taking Control
The board~programmer needs to tak.e control of the
system's address bus, data bus, control lines, etc. to
update the code without damaging the system. (See
Figure 2. System to Bqard-Programmer Interface.)
Taking control simply means isolating the rest of the
system from these lines.
Various methods of isolating the memory from the system include using tristate buffers, latches, or even the
capabilities designed into microprocessors (,...P) and microcontrollers (,...C). For example, Intel's .86-based ,...p
family has .HLD/HLDA signals that were set-up for
mulyprocessor system designs .where bus control is a
major concern. The HLD signal, when acknowledged,
tristates the address, data, and control lines. Although
not designed for multiprocessor environments, Intel's
MCSIll>-Sl and MCS-96 microcontroller families have
Reset capabilities to help simplify this same task.

One issue to be aware of when using a CPU's reset
control function is that it may switch from the reset to
active condition at a non-standard logic level. This only
presents· a problem if the address/data buffer takes
longer to activate than the CPU, and the CPU attempts
to fetch code from a memory device isolated from it.
One approach to insure successful programming takeover (Le. without bus contention) is to have the boardprogrammer's lines in a high impedance state during
connection to the system. Once connection to the system has been secured, the serviceman could hit a button
on the board-programmer to start the system takeover
procedure. Then when total control has been established, the programmer would commence with erasure
and reprogramming.
.
Aside from the flash device's isolation from the system,
various CPU control lines (MEMRD, WE, PSEN, etc.)
may need isolation as well. If active during Reset, these
lines may put the CPU into an unspecified state. When
designing a board for OBP, check ·the ,...C/,...p data
sheets carefully for any special reset conditions.

Printed Circuit Board Guidelines for
Vee and Vpp
.
Programming. conventional EPROM and flash memories takes 30 rnA of current on Vee and Vpp, due to
the nature of hot-electron injection. Most of the charge·
transfers to the memory cell's floating gate in a short
current spike during the first pulse. Y bu should design
both the Vee and Vpp traces with A.C. current spikes
in. mind. Wherever possible, limit the inductance by
widening the two traces. Bypass capacitors (0.1,...F)
should be placed as close as possible to the memory
device's Vee and GND pins, as well as the devices Vpp
and GND pins. The capacitor on .vcc decreases the
power supply droop. The capacitor on Vpp supplies
added charge, and filters and protects the memory from
high frequency over-voltage spikes2.

2. For Ii complete discussion of electrical noise, grounds, power supply distribution and decoupling see Ap-74-High Speed
Mem()ry System Design Using the 2147H, and A,P-125-Dt[lsigning Microcontroller Systems for Electrically Noisy Environ-.
ments.

3-330

infel·

,AP·316

SYSTEM CARD

<-------------A15
A14
A13
A12

Address Bus for
Chip Enables
and Flash Memory
Address Inputs

BOARD-PROGRAMMER

--

0

0

0

0

0

0

0

~

AO
D7

0

0

0

0

Device Address
Lines

}

Data L,lnes

Do

Do
PSI
PS 2

{

RESET
Sys_ Interface ' MEMWR
Cont~ol Lines
MEMEN
,
"
MEMRD
WE
Vpp
GND

CE -

Decoder Enable Line
Read Control Line
WE - Erase/Program Lines
Vpp - Programming Power

OE -

GND

-----:--------->

<----~-------~-

NOTE:

High Order Address
Line for Memory
Select

A 15
A14
A 13
A12

0'

{

Data Bus for
Input/Output

--------~----->

292046-30

,

During normal system read operation, all interface traces are left open-circuited. Some of the lines have pull-downs or
weak pull-ups to insure proper device operation.

Figure 2. System to Board·Programmer Interface

3-331

AP-316

'At first all of these. alternatives 'may seem expensive or
superfluous, but keep in mind that the cost of a single'
cable and programmer gets amortized over the total
, number of systems programmed.

The System/Board-Programmer Hardware
Connection
In most U.V. EPROM OBP applications, designers use
the board's ·edge-connector as the programmer. interface. This approach is the lowest cost solution for standard EPROM technology because U.V. erasable.devices require system disassembly for erasure anyway. With
flash memory, you can eliminate the system dismantling and Capitalize on the erase feature by adding a
cable connector to the board for reprogramming purposes. The connector should extend from. the board
through the system's chassis, and should be easy to
reach by a serviceman.

AN 8-BIT BUS DESIGN EXAMPLE

Various types of cables exist on the market that could
be used to connect programming equipment to the sys- .
tem. The key design consideration when choosing the
type of cable is elimination of all· transient noise that
would interfere with the programming or erasure P!Ocess.
Three types of noise interference and methods to diminish the noise are as follows:
'
1. line to line cross-talk (due to board-programmer's
drivers that drive sharp step functions on adjacent
address lines); solved with either ribbon cables, having alternate lines grounded, or with braided twistedpairs that have aground line for each active signal;
'2. programmer line-driver-to-board impedance 'mismatches leading to transmission line effects, of signal
reflection, and interference; solved by limiting cable
length, decreasing programmer switching speed (or
allowing longer settling time between .address
switches) or by using matched line drivers 'on the
programmer and high impedance buffers on the
board end, or by using series termination resistors on
the driving end of the cable (i.e.":-'board-programmer
end, with the exception of the bi-directional data bus
which needs series resistors at both ends);
3. rf pick-up in electrically noisy environments; use either shielded. cable such as coax, ribbon cable with
solid copper ground plane, or a new type ·that has
recehtly become available called Flex cable.
. Braided twisted-pair cables when kept under three feet
in length genenlIly reduce cross-talk to acceptable levels. This type of cable offers, the most cost-effective solution which works well in most applications. Depend\ ing on the environment, the programmer and your de"
~ign, you may 'need a combination of solutions, such as
braided twisted-pairs with series termination.

An example of an in-circuit reprogrammable controller
board is an SOC31, two 2SF256A's and some glue
chips. (See. Figure 3. for a system block diagram. See
Appendix A. for a detailed system schematic.)3 The
important issues for erasure and reprogramming are as
follows:
1. the board-programmer must have uncontested access
and control of the flash memory array; and ,
2. the microcontroller must be reset (un-active) during
the erasure and programming cycles.

SY$TEM DESIGN
Bus Control Circuitry
The SOC31 has an active-high reset pin, which tristates
the address and data bases. Route this line (RESET) to
the programming connector. Tie the OE pins on the
low-order address latch (74HCT573), and the PSEN
,buffer-enable (74HCT125)4 together, and route that
line MEMWR5 to another pin on the programmer-interface connector.
'
During normal system operations when the,..,C reads
program code from the 2SF256 devices, the pull-down
on MEMWR keeps the 'addreSS latches and PSEN buffer active. During flash memory OBP,' the board-programmer drives MEMWR active-high, which disables
these outputs, and isolates the address bus and PSEN
from the programming signals.
'The board~programm.er must independently control the
RESET and MEMWR' traces beCause they disable at
different VIL values (2.5V for RESET vs O.SV for
MEMWR). If controlled by the same 5V supply, on
power-up ot after a.reset condition the ,..,C would try to
execute code while still isolated from its code sourcespecifically before the address latches andPSEN buffer
activate.'

Address Decode Circuitry
This liesign shows two 2SF256A flash memories. Systems with more than one memory device typically de, code the CPU's high-order address to select a particular device.

3. Note that the flow-through latch on the data bus is not needed with the 80C31 , but is drawn as an example for CPU's that
"
can not tristate their data bus.
4. The isolation buffer is required on PSENin this design becallse tlie 80C31 goes into unspecified states when the Reset
'
"
and PSEN lines are active simultanequsly. To avoid any possible p~oblems, buffer PSEN.
,5. MEMWR = > bus isolation control of PSEN and the data bus.
o

3"332

RESET -

~I

CE
~~
"=~

N

-==

I

AI5

CE

Ae-.... 5
!!
c

(0

c;

cp

~;r

~. :3

to)

III

g

7

B

-

AI5
IS

Ao--'1.4 .

. J.

2BF256A
• Port 3
ALE
ADo-AI?

L

B

Lotch

Q

D

-

Do-I?

~pp
OE

OE
BOC31

~~

B

. I

I'D

PSEN

cfl

;

f

OE

CRT
Int.rface

WE
WE
Vpp
Vpp

,.
L

J:o

l'
>-- MEt.lWR
PS2

>---

t.lEMRD

Of

I

-:.::-

. L

Q Flow

±
.::L.
-

Ao--'I .4

~ J.~

""

WE

;I\"

2

IS
f

• Port I

~

•

MEiiEN

R.I.t

l

PSI

CE
15

.OE

Ao--'l.4

Through
Lotch

Prol ammer
Edg'
Con clor

WE

Dr-Vpp

2BF256A

-:r
.::L.

B
Do- I?

Do-I?

.4?
.-= -

GNC

292046-31

...en
Co)

infel .

AP-316

This is accomplished as illustrated. When Al5 is low,
the lower 32K bytes .are selected. The output of the
inverter drives the other. 28F256A's chip enable. This
type of memory architecture 'promotes power savings
by disabling all memories 'but the one being addressed.
To accomplish this two-line memory control architecture, route the inverter's input Al5 to the 80C31 and to
the programmer interface connector. s The board-programnier .90ntrois the inverter's output enable with
MBMEN.9 The MEMEN llile performs the function
normally performed by CE in component programming. When driven to a logic "I" level MEMEN pulls
.the inverter's output high. This deselects all memory
devices controlled by that I.C. During normal read and
standby operations, the pull-down on MEMEN keeps
the decoder enabled.

Erasure and Programming Control Circuitry
In this design, Vpp and WE are active only during reprogramming. At other times, the two inputs would be
inactive. Simply tie the WEJine to Vee through a pullup resistor. The pull-up limits the current to the board
programmer during reprogramming. (Recall that WE
is active low.) Flash memories allow Vppto be at 12V,
Vee or ground. for read' operations. This design ties
Vpp to Vcc through a diode and resistor to allow for
EPROM OBP compatibility. If .this option is not required, simply tie Vpp to ground through a currentlimiting pull-down resistor.

Returning Control to the Host System
.The board~prograinmer should' return system-control
to the host processor in an organized manner. ,First it
should 10wer.Vpp from 12V to 5V,or ground. Then.the
board programmer should place its address and data

buses into a high impedance state. Next PS2, which
controls MEMWR should be, tristated thus disabling
the PSEN/Address latch isolation. Finally the board~
programmer should switch PSI, which drives the ~
SET line to reactivate the p.C. This sequence guarantees that the p.C will begin operation at a known pro,
gram code location.

16-BIT BUS DESIGN
CONSIDERATIONS
AD. example of anOn-Board programmable 16-bit system board would be an ,80CI86 nlicroprocessor, two
28FOI0 flash mC!Dories,. RAM, and some glue chips.
The basic hardware design considerations would be the
same as those In the previously discussed 8-bit bus example.
'

,
There are a few issiles with 16-bit designs that do not'
arise in 8-bit designs. For the ,programmer to take con~
trol of the system, it must tristate and reset the p.P as
well as tristate the bus buffers and latches. The HOLD
and RESET lines of Intel's 86-based family of microprocessors' have been, designed with bus isolation in
mind for use in multiprocessor systems.
,

,

The designer has two options f~r erasing and programming the high and low bytes of the flash memory array
independently.1) The designer ~ route two ,WE lines to the programmer connector~BYTE HIGH WE and BYTE
LOW WE.
.
2) The reprogramming software can follow the masking
procedure shown in section 4.4. This method allows a
common WE line for the high and low bytes. ,

8. Note'the lack of isolation buffers betWeen the 80C31's high order'addresses (Port 2) arid the board-programmer interface,
compared'to the latch separating the low order addresses (Port 0) and the interface. 1r:J this deSign example, we make use of
the 80C31's ability to tristate these ports, so no isolation Is needed for any of the addresses. The latch on Port 0 is for the
time-multiplexed address! data architecture of this microcontroller, and not specifically for isolation.
9. MEMEN = me,:"oryenable, ~ctive low.
' , '

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....

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CONNECTOR

, 00
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n.
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292046-32

AP-316

OBP EQUIPMENT AND VENDORS
If you are considering OBP for your next design, and
have not used on-board programming before, you will
need to choose a board-programmer vendor. Various
suppliers offer OBP systems; therefore, it is well worth
it to send out requests for programming support bids. If
your production volume justifies the purchase of more
than one board-programmer, you may· want to negotiate a non-recurring engineering charge for development
cost, followed by variable costs for additional units.
Most vendors offer a variety of basic systems, designed
to easily adapt to your needs. Systems can be purchased
that program either single boards 'serially, or a number
of boards in parallel. Light-weight OBP equipment designed for field reprogramming can also be obtained
from some of the vendors~
Most companies win work directly with you at the beginning of your design phase to ensure OBP compatibility. If your design is beyond the definition stage, the
programmer manufacturer will request a copy of your
schematics or block diagrams under non-disclosure.
The vendor haS an OBp· design specialist that will
check the design for OBP compatibility. Any potential
problems ·will be located and corrected at this early
stage.
Every board's ~chitecture is different (i.e., based on
different central processing units (CPU), decoqing
schemes, buffering methodologies, interface connectors,
and types and densities of memories). Vendors write
custom software modules for each application. Also,
the .vendor or the board designer· typically builds an
.interface jig. to connect the board's edge connector to
the programmer. This choice is often left as a decision
for the designer. .

Partial List'" of Companies Seiling
Board·Programmers
.
Following are a few of the companies who offer onboard programming solutions today:
Data I/O Corp.
Digelec
Elan Digital Systems
Oliver Advanced Engineering, Inc.
Stag Microsystems, Inc.
·This list is intended for ex~ple only, and in no way
represents all companies that support on-board programming. Intel Corporation assumes no responsibility for circuity other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.

SUMMARY
• On-board programming (OBP) 1!.as been around
since 1981.
• Designing a board for OBP can be .easily done by
working with a board-programmer vendor'S OBPdesign-specialist during the initial design phase.
• In-circuit alterable code storage can be easily implemented by using flash memory and it's features.
,. Time and money savings can be realized in a' number of ways by taking advantage of flash memory
OBP:
< > Decreased board costs. and improved reliability
from elimination of EPROM sockets;
< > Decreased· manufacturing costs from elimination
of board eraser depreciation costs, recurring U.V.
light bulb and energy experises;
I
< > Decreased inventory expense from simplified test
and rework methods (one-step diagnostics, erasure, and board configuration);
< > Decreased product costs base!! on decreased
board-handling loss;
< > Improved board diagnostics and testability leading
to higher quality and .decreased customer returns;
and
< > Quicker, more reliable field code updates.

3~336

infel"

AP-316

APPENDIX B
Vpp GENERATION CIRCUITS
Circuit
Circuit
Circuit
Circuit
Circuit
Circuit

# I-Regulation from a higher voltage
#2-Regulation from a higher voltage
# 3-Regulation from a higher voltage
#4-5V to 12V Boost
# 5-5V to 12V Boost
#6-Monolithic DC/DC Convertor

For more detailed information on Vpp generation circuits, see AP-357 titled Power Supply Solutions for Flash
Memory (Order Number 292092).

Circuit #1
Down Conversion
(From 14.0V-26.0V to 12.00V)
Vln

In

Vout

Oul

Vee

LM2391CT

Rl

R3
On/Off

vpp

Gnd

Adj
~

Enable

t

;;:r:-

C2

R2
Cl

. --------------== :r---------.
vout -';:1"i-l
______________
-: ________ ------..1
I

1.20v (R1/R2

~

292046-12

COMPONENTS

COST'

LM2391CT
R1 = 20 K!l, 1%
R2 = 180K!l, 1%
R3 = 10K!l
C1 = 0.1,.,.F
C2 = 100,.,.F

$0.75
0.045
0.045
0.02
0.02·
0.15
$1.03

NOTES:
-The LM2391 offers an enable pin for added data protection.
-The drop out voltage is 0.6V.
-R3 is NOT required if Vpp enable is driven by a CMOS device.
'Cost approximations assume 10,000 piece quantity.

3-337

AP-316

Circuit #2
Down Conversion
(From 16.00V-26.00V to 12.00V)
,Vln}--......--lln

LM-317
,

Vout

. ~ Rl

Voltage Reguletor

S
. , '-'

Adl

1%

I

Cl

='=

-o

OUlI-....,...-....

L--_ _- ' - . .

C2

_,.

,.

COMPONENTS

COSTO

LM-317
Rl = 1240,1%
R2 = 10700,1%
C1=O.1/-LF
C2 = 100/-LF

0.40
0.045
0.045
0.02
0.15

292046-13

$0.66

NOTES:
U.';·317 requires a minimum VIN-VOUT = 3.0V
·Cost approximations assume 10,000 piece quantity.

Circuit #3
Down Conversion
(From. 15.0V -40.0V to 12.00V)
Vln > - - + - - - I l n

LT1Q85

YoUl
OUlf-+-----4"-O

VoHage Regulator
Adl

Cl

=~

I

~ 111

S

1%

C2

"'-'-

L--_ _ _. .

_

. R2S

1%?

rVout-;;;"1~25v-(Fi"1iR2-+--1)1

L. _____________________________________ ..I

.•
292046-14

COMPONENTS

COSTO

LT-l085
Rl =1240,1%
R2 = 10700,1%
Cl=10/-LF
C2 = 10/-LF

2.50
0.045
0.045
0.10
(i,10
$2.79

NOTES:
LT-1085 requires a millimumVIN-VOUT = 1.5V
°Cost approximatjons assume 10,000 piece quantity.

3-338

,intel·

'AP-316 '

Circuit #4
Up Conversion
(From 5V to 12.0V)
5V

, ,I

Vpp
~~----~-----oOUWUT

200mA MAX

Vpp
COMMAND

292048-33

COMPONENTS,
LT1072
, R1 = 10.7k, 1%
R2 = 1.24k, 1%
R3 = 1k~5%
R4= 120k,5%
R5 = 270k,5%
C1 =1 ",F
C2=1",F
C3=10",F
'L1=150",H
Q1 = 2N3904

COST·
1.82
0.045
0.045
0.02
0.02
0.02
0.10
0.10
0.15
1.00
0.10

VppOUT
12.0V

$3.42

NOTES:
Drive Vpp COMMAND low to turn on'the circuit.
·Costapproximations assume 10,000 piece quantity.

3-339

R1

R2

10.7k 1.24k

R••Jator
Tolerance
1%

intel .

AP-316

Circuit #5
Up Conversion Circuit
(From 5.0V to 12.{)V)

S.OOv
+5v
24 +5,!,

Valor
PM7006

GND GND

v+
v+
v-

11

vppOut

14
10

v;~

13

, Vpp'
Enable :>-"'---!"-'

292046-16

COMPONENTS'

COST"

PM7006
C1 "" 0.1 ftF
Buz11A

$6.25
0.05
2.59
$6.69

NOTES:
1. The capacitor decreases output noise to 140 mV pk-pk.
2. We added the Buz11A Mospower nFET to enable/disable the converter. This control minimizes power consumption
,
' ,
, , " ,,:
which under full load can reach 600 mAo
3. The voltage drop across the switch is O.W. Due to this drop the PM7006 will not maintain the Vppspec with 10%
,.
fluctuations in Vee supply.
"Cost approximations assume 10,,000 ,piece quantity.

infel .

AP-316

APPENDIX C
LIST* OF DC-DC CONVERTER-COMPANIES
AT&T MICROELECTRONICSt
3000 Skyline Drive
Mesquite, TX 75149
Tel: (800) 526-7819
Fax: (214) 284-2317

CORP.~

SHINDENGEN AMERICA, INC.t
2649 Townsgate Rd., Suite 200
Westlake Village, CA 91361
Tel: (800) 634-3654
Fax: (805) 373-3710

BURR-BROWN CORP. t
P.O. Box 11400
Tucson; AZ 85734
Tel: (800) 548-6132
Fax: (602) 741-3895
LINEAR TECHNOLOGY
1630 McCarthy Blvd.
Milpitas, CA 95035
Tel: (408) 432-1900
Fax: (408) 434-0507
MAXIM INTEGRATED
120 San Gabriel Drive
Sunnyvale, CA 94086
Tel: (408) 737-7600
Fax: (408) 737-7194

NATIONAL SEMICONDUCTOR
Mt. Prospect, IL 60056
Tel: (800) .628-7364
Fax: (800) 888-5113

CORP.~

PRODUCTS~

MOTOROLA INC.~
2100 E. Elliot Rd.
Tempe, AZ 85284
Tel: (800) 845-6686

SILICONIX INC.~
2201 Laurelwood Rd.
Santa Clara, CA 95056
Tel: (800) 554-5565
Fax: (408) 727-5414
TOKO AMERICA, INC. t
1250 Feehanville Drive
Mount Prospect, IL 60056
Tel: (708) 297-0070
Fax: (708) 699-7864
VALOR ELECTRONICSt
6275 Nancy Ridge Dr.
San Diego, CA 92121
Tel: (619) 458-1471

'This list is intended for reference only, and in no way represents all companies that support power conversion
products. Since this industry develops many new solutions each year, Intel recommends that the designer contacts
the vendors for the latest products. Intel will continue to work with the industry to develop optimum solutions for
power conversion. Intel Corporation assumes no responsibilities for circuitry other than circuitry embodied in Intel
products. No other circuit patent licenses are implied.
. tMonolithic Solutions
---~,....""'"
LX 1 J+-+.J
NC

.-----=H VRE'

L-"-__
U2=
t.tTD3055

~

In,5%

j:TL

..

LBO
LBI
GND

.-.-.-~ Vpp @ 250 rnA

In,5%

MAX65BESD

C4
O.II'F

Dl

I

OPTIONAL
FILTER

.. _-------

MBRS120T3
C2

+

292092-6

Figure 5·1. Maxim MAX658 3V to 5V Converter (250 mAl
Optimal Attributes

• Highest Efficiency
• 250 rnA Output Current Capability
• Low Shutdown Current
Main Features

•
•
•
•
•
•
•
•

Input Voltage Range: 2.0V to 3.IV
Output Voltage: 5V ± 10%
Output Current Capability: Up to 250 rnA
Typical Efficiency: 85%
18 KHz Operation
Shutdown Mode On Chip
Low Quiescent Current at Shutdown: 80 p.A typical
Rise Time from shutdown: 25 ms typical

The MAX658, available from Maxim Integrated Products in a 14-pin surface mount package, is a good high
current solution for obtaining Vee from a pair of
NiCd/alkaline cells. The entire solution, however, is
not 100% surface mountable. It uses a high current
through-hole inductor and a large through-hole filter
capacitor at the output. Voltage spikes may be present
in the output due to incorrect layout, excessive output
filter capacitor ESR (Equivalent Series Resistance) and
diode switching transients. The optional RC filter circuit is recommended in order to eliminate any sharp
transients. Applications assistance and an eval.uation
kit are available from Maxim.

3-413

intel·

,

AP-357

Table 5-1. Parts LIst for the MAX658 3V to 5V Converter
Value/Type

Part #

Ref

Source

Cost'

U1

MAX658

SMPSIC

C1

UPR1A471 MPH

470 fJ-F/1OV
LowZ

Nichicon
(708) 843-7500 .

$0.12

C2

267M1602-105-MR-720

1 fJ-F/16V
Tantalum

Matsuo
(714) 969-2491

$0.15

C3

GRM40X7R102M050AD

1 nF

Murata Erie
(404) 436-1300

$0.03

C4

GRM40Z5U104M050AD

0.1 fJ-F

Murata Erie
(404) 436-1300

$0.06

R1, R2

9C08052A 1ROOJLR

10,5%

Philips
(817) 325-7871

$0.04

D1

MBRS120T3

Schottky Diode

Motorola
(800) 521-6274

$0.30

L1

LCM1812R-102K

1.0 mH
Chip Inductor

Inductor Supply Inc.
(800) 854-1881

$0.22

\

Maxim
(408) 737-7600

$2.45

L2

RCH110-330

33fJ-H

Sumida
(708) 956-0666

$0.40

U2

MTD3055E

NFET

Motorola
(800) 521-6274

$0.70

Total Cost

$4.47

'Cost estimates based on published 10K unit pricing at the time this application note was written.

5.2 Linear Technology LT1110-5: Vee

@

150 mA

SHUTDOWN - - - - - - - - - - ,

VIN (2.0V-3.1V)
R2

+ Cl .

.I.

Rl

22 }IF/l0V
TANT

3k,5%

-------.
Ul,5%

L1 47}1H
(SUMIDA CD54-330)

..........~-Vpp @ 150mA
FB t-;..-.........- -......
SET
AO
GND
Ul,5%
C3
LT1110-5
O.l}1FI

Dl

OPTIONAL
FILTER

_

._------

MBRS120T3

292092-9

FIgure 5-2. LInear Technology LT1110-5 3V to 5V Converter (150 mAl
3-414

intet

AP-357

•
•
•
•
•

Optimal Attributes

• Smallest Size
• Low Shutdown Current
• All Surface Mount

Typical Efficiency: 76%
60 KHz Operation
Shutdown Mode Using External Components
Low Quiescent Current at Shutdown: 16 J-tA typical
Rise Time from Shutdown: 4 ms typical

The LT1110-5 from Linear Technology is a fixed 5V
version of the converter shown for the 12V design in
Section 4.1.

Main Features
• Input Voltage Range: 2.0V to 3.IV
• Output Voltage: 5V ±5%
• Output Current Capability: Up to 150 mA

Table 5-2 Parts List for the LT1110-5 3V to 5V Converter
Part #

Ref

Value/Type

Source

Cost"

U1

LT1110-5CS8

SMPS IC

Linear Tech
(408) 954-8400

$2.60

C1

267M1002- 226-MR-720

22 J-tF/10V
Tantalum Chip

Matsuo
(714) 969-2491

$0.23

C2

267M1602- 476-MR-720

47 J-tF/16V
Tantalum Chip

Matsuo
(714) 969-2491

$0.47

C3

GRM40Z5U104M050AD

0.1 J-tF

Murata Erie
(404) 436-1300

$0.06

D1

MBRS120T3

Schottky Diode

Motorola
(800) 521-6274

$0.30

L1

CD75-330

33 J-tH

Sumida
(708) 956-0666

$0.38

R1

9C08052A3001JLR

3 KO, 5%

Philips
(817) 325-7871

$0.02

R2

9C08052A 1002J LR

10KO,5%

Philips
(817) 325-7871

$0.02

R3,R4

9C08052A 1 ROOJLR

10,5%

Philips
(817) 325-7871

$0.04

U2

MMBT4403LT1

PNP Transistor

Motorola
(800) 521-6274

$0.09

Total Cost

$4.21

"

·Cost estimates based on published 10K unit pricing at the time this application note was written.

6.0

DOWN-CONVERTING TO 12V

The ability to down-convert to 12V from a higher voltage is often needed (as in the telecommunications environment). This section presents some good solutions for
obtaining Vpp from a higher voltage.

3-415

intel .

AP-357

6.1 Maxim Integrated Products MAX667
. -_ _ _ _ _ _ _ _

.....- - Vpp

~~---

+ Cl

Rl
402k,l%

Ul

1
DO
2
OUT
3
4

..I.

47 p.r/16V

IN
LBO
SET
LBI
GND SHDN
R2
47.5k,l%

MAX667
SHUTDOWN - - . . . , . . . - - -......

292092-10

Figure 6·1, Maxim MAX667 12V Linear Voltage Regulator

• Output Current Capability: Up to 120 rnA
o Typical Efficiency: 70%

Optimal Attributes

o Small Size
• Ultra Low Shutdown Current
• All Surface Mount
• Very Low Dropout

• Shutdown Mode On Chip
• Low Quiescent Current at Shutdown: 0.2 p.A
Typical
• Rise Time from Shutdown: Less than 0.1 ms Typical

Main Features·

o Input Voltage Range: 12.1V to 16.5V
o Output Voltage: 12V ± 5%
Table 6·1 Parts List for the MAX667 12V Step Down Converter
Value/Type

Source

Cost·

U1

MAX667CSA

SMPS ICSOS Package

Maxim
(40S) 737-7600

$2.10

C1

267M 1602-476-MR-720

7 p.F/16V
Tantalum

Matsuo
(714) 969-2491

$0.47

R1

9COS053A4023J LR

402 Kfi,1%

Philips·
(S17) 325-7S71

$0.03

R2

9COS053A4752JLR

47.5 Kfi,1%

Philips

$0.03

Total Cost

$2.63

Ref

Part #

·Cost estimates based on published 10K unit pricing at the time this

3-416

applic~tion

note was written.

AP-357

6.2 Linear Technology Corporation LT1111-12

VIN (16V-30V)

Cl
+
15}LF/35V 'T'
TANT ...L.

Rl
150n
Ul

i

1+-.....- -....- - -

ILIt.t

t - - -3o-1 VIN

Vpp

+ C2

'---~4:-tSWI

,......-....;:.t SW2

47 }LF/16V

Dl
MBRS140T3
D2
totBRS 140T3

292092-11

Figure 6-2. Linear Technology LT1111-12 Step Down Switcher
Optimal Attributes

Main Features

• High Efficiency
,. All Surface Mount

• Input Voltage Range: 16V,to 30V
• Output Voltage: 12V ± 5%
• Output Current 'Capability: Up to 120 rnA
• Typical Efficiency: 80%

Table 6-2. Parts List for the LT1111-12 12V Step Down Converter
Ref

Part #

Source

Cost·

_ SMPS IC·
S08 Package

Value/Type

Linear Tech
(408) 432·1900

$2.20

U1

LT1111-12

C1

267M3502-225·MR·720

2.2/LF/35V
Tantalum

Matsuo
(714) 969·2491

$0.28

C2

267M 1602·476·MR·720

47/LF/16V
Tantalum

Matsuo
(714) 969·2491

$0.47

R1

9C08052A 1500JLR

150n,5%

Philips
(817) 325·7871

$0.02

L1

COR105·470

47/LH

Sumida
(708) 956·0666

$0.38

01,02

MBRS140T3

Schottky ~iode

Motorola
(800) 521·6274

$0.60

Total Cost

$3.95

..

'Cost estimates based on published 10K Unit pricing at the time this application note was written.

3-417

intet

AP~357

6.3 National Semiconductor LM2940CT-12
LM2940CT-12
VIN (13V-26V) -

.....-1

t-.....- '

Vpp

+ C2
22},r/16V

292092-12

Figure 6-3. National LM2940CT-12 12V Linear Regulat~r
Optimal Attributes

• Lowest Cost
Main Features

• Input Voltage Range: 13V to 26V
• Output Voltage: 12V ± 3% ,
• Output Current Capability: lA

The LM2940CT-12 is a low drop-out linear regulator
from National Semiconductor. This is a good low cost
fixed 12V output solution. The part is offered in a standard TO-220 plastic. package. The input capacitor is
required only if the regulator is located far away from
the input power supply filter, and the output capacitor
must be at least 22 poP in order to maintain stability.

Table 6-3. Parts List for the LM2940CT-12 Step Down Converter
Ref

Part #

U1

LM2940CT-12

C1

GRM43-2Z5U4 74M050AD

C2

267M 1602-226-MR-720

Value/Type

Source

Cost·

Voltage Reg TO-220

National
(408) 721-5000

$0.95

.0.47 poF/50V

Murata Erie
(404) 436-1300

$0.07

22 poF/16V
Tantalum

Matsuo
(714) 969-2491

$0.28

Total Cost

$1.30

·Cost estimates based on published 10K unit pricing atthe time this application note was written.

3-418

int:eL
7.0

AP-357

8.0 SUMMARY

OBTAINING Vpp FROM 12V
UNREGULATED

In systems like the desktop computer, a 12V supply
exists but may not be regulated to ± 5%. If this voltage
is used as the Vpp source for flash memory, it may well
degrade the write/erase performance of the memory, or
adversely affect its reliability. Fortunately, in most of
the situations where a 12V unregulated (or not regulated to within 5%) supply exists, a 5V supply also exists
in the system (the desktop computer is a good example). It is recommended in such caSes that the existing
5V supply be used to obtain the 12V ± 5% rail. This
approach is more economical, more efficient, and provides space savings over a buck-boost topology that
takes unregulated 12V and regulates it to ± 5%.
In the rare case where a 5V supply is not present, modular solutions exist that will regulate the unregulated
12V supply to ± 5%. However, these are bulky and
expensive. Moreover, many of them require that a minimum load be maintained in order to stay in regulation.
One such solution in presented in Appendix A.

For battery powered applications, the author views the
discrete switching regulator Ie solution asa better
choice than the modular solution. The lower cost, higher efficiency, and smaller size/height associated with
discrete solutions justify the small additional design effort required to incorporate them in flash memory applications. In applications where the primary source of
power is a wall power outlet, or in applications where
the flash memory will be written to infrequently, efficiency and quiescent current take on secondary importance. In such cases, it may be acceptable to use a 12V
regulated (to within ±5%) tap from the system supply.
Alternatively, the ability to easily design-in modular solutions may outweigh the disadvantages of lower efficiency and increased cost. For those users wishing to
incorporate modular solutions, Appendix A provides
some of the lower cost solutions from this industry segment.

3-419

int'el..

AP-357

APPENDIX A
MODULAR SOLUTIONS
Modular s~lutions may work well in non-battery powered situations where the efficiency of the power supply
converter is not critical. These are also advantageous in
that they usually do not need any external components
and there is no converter design involved. However, the
type and quality of the discrete components used in
these hybrid solutions is open to question. This is not
true in the case of the discrete converter designs presented in the earlier sections, where the quality of the
cOl)1ponents used are under the control of the system
design engineer. Hence, even though modular solutions
offer the convenience of a single package and ease of
testability, the quality/reliability of comparably priced
modular solutions may be questionable.
Some modular solutions suited to flash memory applications are presented below, with a brief description of
each. Sources for obtaining these are listed in Appendix

B.

A.1

International Power/Newport
Components NMF0512S

The NMF0512S is a 5V to 12V hybrid power module
that has an output current capability of SO rnA. Output
tolerance is ± 5%. It is equipped with a shutdown pin
which can be used to switch Vpp off. However, power
dissipated in the shutdown mode is relatively high
(about 100 mW). The part is small in size and measures
0.76 in. (19.5 mm) x 0.4 in. (9.S mm) x 0.4 in. (9.S mm),
and costs about $7.90 in 10K quantities (at the time
this application note was written). Typical efficiency of
conversion is 62%.

A.2 Xentek NPSC-0512S
The Xentek NPSC-0512S is a IW power module that
converts 5V to Vpp and will source up to SO rnA of
continuous current. However, it uses two external filter
capacitors-one at the input and one at the output. The
input filter capacitor is 47 /LF/IOV, and the output filter capacitor is 100 /LF/16V. Size of the solution (converter alone) is 0.S7 in. (22 mm) x 0.39 in. (10 mm) x
0.79 in. (20 mm). The NPSC-0512S does not have a
shutdown mode. The part costs around $5.00 in 10K
quantities (at the time this application note was written). Typical efficiency of conversion is 60%.

A.3 Shindengen America Inc.
HDF-0512D
The HDF-0512D module from Shindengen will convert
unregulated 12V to 12V ± 5%. This part is a dual output part (± 12V), but only the + 12V line is used .. The
conversion efficiency is high (75% typical), and the
part will provide a regulated Vpp voltage from input
voltages as low as SV, and as high as 16.5V. A minimum load of 5 rnA needs to be maintained to guarantee
. regulation. Size of the solution is 1.75 in. (44 mm) x
0.43 in. (11 mm) x O.S in. (20 mm). Cost is approximately $10.00 in quantities of .10K (at the time this
application note was written).

3-420

_.
Ref
iF

3.1

Vendor
Name

Part iF

Maxim

MAX732

InputC
(Volts)

OulputV OutputC
(Volts)
(rnA)

4V-7V

12V, 4%

120

iF ExtComp

Effie
(%)
90

(Note 1)

100%
ISHDN RTlme
Cost PC Area Height
SHDN?
(Note 4) (Note 5)
SMD? (Note 2) (Note 3) , (In)

5; D, L, 3C

Yes

$3.93

0.56

0.18

Yes

LT111Q..12

5V,10%

12V, 5%

120

76

7; D, L, T, 2R, 2C

Yes

$4.58

0.45

0.20

Yes

16p.A

1 ms

O'C, +70'C

LT1109-12

5V,10%

12V,5%

60

84

4; D, L, 2C

Yes

$3.61

0.38

0.18

Yes

375p.A

1 ms

O'C, +70'C

3.4 Motorola

MC34063A

5V,10%

12V,5%

120

75

11; D, L, T, 3C, 5R

Yes

$2.25

0.49

0.18

Yes

25p.A

2ms

O'C, +70'C

LT1110-12

2V-3.1V

12V, 5%

30

70

7; D, L, T, 2R, 2C

Yes

$4.71

0.45

0.18

Yes

16p.A

4ms

O'C, +70'C

4.2 Maxim

MAX732

1.8V-4V

12V, 4%

30

87

9; D, L, 7C,

Yes

$4.80

0.7

0.18

Yes

45p.A

25ms

O'C, +70'C

4.3 Maxim

MAX732

1.8V-4V

12V,4%

60

85

8;D, L,6C,

No

$4.15

1.11

0.49

Yes

45p.A

75ms

O'C, +70'C

.' MAX658

.2V-3.1V

5V,5%

250

85

7; D, 2L, T, 3C

No

$4.47

0.92

0.39

Yes

80p.A

25ms

O'C, +70'C

2V,-3.1V

5V,5%'

150

76

7; D, L, T, 2R, 2C

Yes

$4.72

0.45

0.20

Yes

16p.A

1 ms

O'C, +70'C

12.1V-16V 12V, 5%

250

75

3;2R,C

Yes

$2.73

0.25

0.15

Yes

0.2p.A

0.1 ms

O'C, +70'C

12V, 5%

120

80

6; 2D, L, 2C, R

Yes

$3.95

0.78

0.2

No

N/A

N/A

O'C, +70'C

Linear Tech

Maxim

5.2 Linear Tech

LTlll0-5

6.1

MAX667

Maxim

6.2 Linear Tech

LT1111-12

16V-30V

6.3 National

LM2940CT-12

13V-26V

12V,3%

lA

No

$1.30

0.5

0.18

No

N/A

N/A

O'C, +70'C

A.l International NMF0512S
Power

5V,10%

12V, 5%

80

62

0

No

$7.90

0.3

0.40

Yes

20 rnA

10 p.s

-40'C, + 70'C

A.2 Shindengen HDF1212D

8V-16.5V

12V, 5%

120

77

0

No

$10.00

0.76

0.80

No

N/A

N/A

-10'C, + 70'C

5V,10%

12V, 5%

80

60

2;2C

No

$5.50

0.34

0.79

No

N/A

N/A

-10'C, + 70'C

121VIN 2;2C

c.l

A.3 Xentek

NPSC-0512S

l
8

O'C, +70'C

3.2 UnearTech

5.1

~

1 ms

3.3 Linear Tech

4.1

.l>.

70 p.A

Temp

NOTES:
1. # External components. 0: Diode, L: Inductor, C: Capacitor, R: Resistor, T: Transistor.
2. Cost. Cost estimates assume 10K quantities, based on published pricing at the time this application note was written.
3. PC Area. PC Aarea is conservatively estimated as 2.0x (area of all components). Where actural layouts are presented, the lower value is given. Note
that this estimate is for a single sided board, and area can be reduced considerably if both sides of the board are utilized.
4. I Shdn. Current consumed by supply at shutdown. Output settles to VCC at shutdown, so some additional flash Vpp leakage/standby will exist.
5. R Time . .Rise time from shutdown state. Erase/Writes should not be attempted till Vpp level has risen to valid level after shutdown is disabled.

o
c:
lJ
<
m
-<

o."
0»
0"tJ

."tJ

c:m

Z
-0
0z><
0m
-t

"tJ

lJ

m
m

o

z

-t

m

o

»
"a
I

(0)

U1
..,.

infel .

Ap·357

APPENDIX C
.
SOURCES/CONTACTS FOR RECOMMENDED
DC-DC CONVERTERS
Linear Technology Corporation
Recommended· Products:
-

LTl110-12 (DC-DC Converter IC)

-

LTl110-5 (DC-DC Converter IC)

-

LTl109-12 (DC-DC Converter IC)

-

LTlIII-12 (DC-DC Converter IC)

In U.S.A.:
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Tel: (408) 432-1900
Fax: (408) 432-0507
In Europe (U.K.):
III Windmill Road
Sunbury
Middlesex TWI6 7EF
U.K.
Tel (44)(932) 765688
Fax (44)(932) 781936
In Asia (Japan):
4F Ichihashi Bldg
1-8-4 Kudankita Chiyoda-ku
Tokyo 102 Japan
Tel (81) (03) 3237-7891
. Fax (81) (03) 3237-8010

In Europe (U.K.):
Maxim Integrated Products (UK), Ltd.
Tel: (44) (734) 845255
In Asia (Japan):
Maxim Japan Co., Ltd.
Tel: 81 (03) 3232-6141

Motorola Semiconductor Inc.
Recommended Product:
-

In U.S.A.:
616 West 24th Street
Tempe, AZ 85282
Tel: (800) 521-6274
In Europe (U.K.):
Tel: (44) (296) 395-252
In Asia (Japan):
Tel: (81) (3) 440-3311

National Semiconductor
Recommended Product:
-

Maxim Integrated Products
Recommended Products:
-

MAX732 (DC-DC Converter IC)

-

MAX658 (DC-DC Converter IC)

-

MAX667 (DC-DC Converter IC)

In U.S.A.:
120 San Gabriel Drive
Sunnyvale, CA 94086
Tel (408) 737-7600
Fax (408) 737-7194

MC34063AD (DC-DC Converter IC)

LM2940CT-12 (Voltage Regulator IC)

In the U.S.:
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052
Tel: (408) 721-5000
In Europe:
National Semiconductor (UK) Ltd.
The Maple, Kembrey Park
Swindon, Wiltshire SN26UT
U.K ..
Tel: (07-93) 61414i
Fax: (07-93) 697522

intel"

Ap·357

In Asia:
National Semiconductor Japan Ltd.
Sanseido Bldg. 5F
4-15 Nishi Shinjuku
Shinjuku-ku
Tokyo 160 Japan
Tel: (81) (3) 299-7001
Fax: (81) (3) 299-7000

In Europe:
Shindengen Magnaquest U.K. Ltd.
Unit 13, River Road,
Barking Business Park,
33 River Road, Barking,
Essex IGl1 ODA
Tel: (44) (81) 591-8703
Fax: (44) (81) 591-8792
In Asia:
2-1,2-Chome Ohtemachi
Chiyoda-ku
Tokyo 100
Japan
Tel: (81) (3) 279-4431
Fax: (81) (3) 279-6478

Newport Components!
International Power
Recommended Product:
-'- NMF0512S (5V -12V Converter Module)
In U.S.A.:"
International Power Sources
200 Butterfield Drive
Ashland, MA 01721
Tel: (508) 881-7434
Fax: (508) 879-8669

Xentek Inc.
Recommended Product:
-

In U.S.A.:
760 Shadowridge Drive
Vista, CA 92083
Tel: (619) 727-0940
Fax: (619) 727-8926

In Europe:·
Newport Components
4 Tanners Drive
Blakelands North
Milton Keynes MK14 5NA
Tel: (0908) 615232
Fax: (0908) 617545

Shindengen Electric Co. Ltd.
Recommended Product:
- HDF0512D (12V unreg. to 12V reg. converter
module)
~In

the U.S.:
2649 Townsgate Road # 200,
.Westlake Village, CA 91361
Tel: (800) 634-3654
Fax: (805) 373-3710

NPSC0512S (5V-12V Converter Module)

In Europe (Germany):
Xentek, Inc.
c/o Taiyo Yuden GMBH.
Obermaierstrasse 10,
D-85oo Nurnberg 10
Federal Republic of Germany
Tel: (49) (911) 350-8400
Fax: (49) (911) 350-8460
In Asia (Japan):·
Xentek, Inc,
c/o Taiyo Yuden., Ltd .
6-16-20, Ueno, Taito-ku
Tokyo 110
Japan
Tel: (81) (3) 3837-6547
Fax: (8\) (3) 3835-4752

3-423

AP-357

APPENDIX D
CONTACTS FOR DISCRETE COMPONENTS
Matsuo Electric Co., Ltd.
Matsuo's 267 series surface mount· tantalum chipcapacitors are recommended by Maxim and Linear Technology for input an,d output filter capacitors on their
DC-DC converters. Part #s are included on the .parts
list that accompanies most solutions. If alternate
"equivalents" are required, choose high reliability, low
ESR (Equivalent Series Resistance) and low ESL
(Equivalent Series Inductance) type tantalums, which
help in keeping output ripple and switching noise to a
minimum.
In U.S.A.: /
2134 Main St., Ste. 200
Huntington Beach, CA 92648
Tel: (714) 969-2491
Fax: (714) 960-6492

In,u.S.A.:
637 East Golf Road
Suite 209
Arlington Heights, IL 60005
Tel: (708) 956-0666
Fax: (708) 956-0702
In Asia:
4-8 Kanamachi 2-chome,
Katsushika-ku,
Tokyo 125
Japan
Tel: (81) (03) 3607-5111
Fax: (81) (03) 3607-5428

Coiltronix Inc.

In Europe:
Steucon - Center II MergenthaUeralle 77 .
D-6236 EschbenlTs.
Federal Republic of Germany
Tel: 6196-470-361
Fax: 6196-470-360

Coiltronix is recommended as a good alternate source
for surface mount inductors. The CTX series offered by
Coiltronix is well suited to DC-DC converter applications. These are shielded, and have' a .toroidal core.
However, they are bigger in size and currently much
more expensive (7X to 8X) than the Sumida. varieties
recommended in the solutions herein. The equivalent
part numbers are:

In Asia:
Oak Esaka Bldg.
10-28· Hiroshiba-Cho
Suita-shi
Osaka 564
Tel: (06) 337-6450
Fax: (06) 337-6456

Sumida CD54~470 - Coiltronix CTX50-1 .
Sumida CD54-180 - Coiltronix CTX20-l
Sumida CD54-220 - Coiltronix 'CTX20-l
Sumida CD75-470 - Coiltronix CTX50-2
Sumida CDRI05-470 - Coiltronix CTX50-2

Sumida Electric Co. Ltd.
Sumida CD series surface mount inductors are recommended by Maxim, Linear Technology for their miniature size and relatively low cost. These are well suited
to low power. DC-DC converter applications. Contact
Sumida Electric directly for procuring these. The part
# s are included in the parts list that accompanies most
solutions. In applications where noise (EMI) is a concern, shielded varieties are also offered by Sumida.

In U.S.A.:
Coiltronix Inc.
984 S.W. 13th Court
Pompano Beach, FL 33069
Tel: (305) 781-8900
Fax: (305) 782-4163

In U.K.:
Microelectronics Technology Ltd.
Great Haseley Trading Estate
Great Haseley
Oxfordshire OX9 7PF
U.K.
Tel: (08) 44 278781
Fax: (08) 44 278746

3-424

AP-357

In Asia:
Serial System Mktg. '
Poh Leng Bldg., #02.,01
21 Moonstone Lane
Singapore 1232
Tel: 2938830
Fax: 2912673

In Europe:
Philips Components Ltd.
Mullard House
Torrington Place
London WCIE 7HD
Tel: (44) 71 580 6633
Fax: (44) 71 636 0394

Coilcraft
Coilcraft .is also recommended as a good alternate
source for surface mount inductors. The N2724-A
shielded series is well suited to DC-DC converter applications. These are bigger and currently. more expensive
(2x to 3x) than the Sumida: inductors ~ecommended in '
the solutions. Contact Coilcraft directly for any applications assistance or for procurem~t of these parts.
The equivalent part numbers are:

In Asia:
Philips K.K.
Philips Bldg. 13-37
Kohnan 2-chome
Minato-Ku Tokyo 108
Tel: .(81) 3 740-5028
Fax: (81) 3 740-5035

SlIiconix-Logic Level PFETs
Siliconix. offers low-"on" resistance logic level PFETs
(Si9400, and Si9405) that can be used for switching a
DC-DC converter into a shutdown state by ~sing these
switches on the high side of the input to the converter
"
(see Appendix E).

Sumida CD54-470 -+ Coilcraft N2724-A 47 ""H
Sumida CD54-180 -+ .Coilcraft N2724-A 18 ""H
Sumida CDRI05-470 -+ Coilcraft N2724~A47""H
, In the US:
. 1102 Silver Lake Road
Cary, IL 60013
Tel: (708) 639-6400
Fax: (708) 639-1469

In the US:
2201 Laurelwood Road
P.O. Box 54951
Santa Clara, CA-95056-9951
Tel: (408) 988-8000
Fax: (408) 727-5414

In Europe:
21 Napier Place
Wardpark North
Cumbemauld .
Scotland G68 OLL
Tel: 0236 730595
Fax: 0236 730627

In Europe:
Weir House
Overbridge Square, Hambridge Lane'
Newbury, Berks'RG14 5UX
Tel: (0635) 30905
Fax: (0635) 34805

In Asia:
Block 101, Boon Keng Road
#06-13/20
Kallang Basin Industrial Estate
, Singapore 1233
Tel: 2966933
Fax: 296446,3

In Asia:
Room 709, Chinachem Golden Plaza
77 Mody Road .
,TST East Kowloon '
Tel: (852) 724-3377
Fax: (852) 311-7909

Philips Components,
. ,

J

,

'

Philips Components 'is recommended as a good source
for surface mount (SMD) resistors (standard 9C series,
and 9B (MELF) series). Part #s are included in the
parts list that accompanies most of the solutions in the
application note. Many alternate sources exist.
'
In the US:
2001 W. Blue Heron Blvd.
P.O. Box 10330
Riviera Beach, FL 33404
Tel: (407) 881-3200,
Fax: (407) 881~3304

3-425

intel~

AP-357

APPENDIX E
OTHER DESIGN CONSIDERATIONS
E.1

sistance". of 0.2fi (at a gate drive of 4.SV). It is important to have as low lin "on" resistance as possible, since
the peak currents and start-up currents into the supply
are high. Care must be taken to ensure that the DC-DC
conversion process is not .affected after accounting for
the drop in input voltage across the PFET.

Vpp Valid Handshake Logic

It is often desirable ,to have, along with the Vpp solution, a handshake signal (using extra hardware) that is
asserted as long as the voltage level on Vpp is valid.
The following schematic illustrates a good way of
achieving this. This handshake signal could be used to
determine when it is suitable to perform writes!erases
on the flash device. The circuit shown uses a precision
zener voltage reference and a comparator, along with
bias resistors, to monitor the voltage level on Vpp. The
point at which the comparator trips must be set after
careful consideration of the variation in the refererice
voltage and. the tolerances on the bias resistors. The
worst case conditions on these variations must guarantee that the handshake signal is asserted when Vpp is at
its worst case lower-end level (lIAV). Care must be
taken to use the exact same components as specified in
order to maintain the tight tolerance on the trip level of
the output signal.

E.3 Working of the Discrete Step Up
Switching Regulator
This section presents a brief overview of the operation
of discrete step up switching regulators, and presents
issues that the user needs to be concerned with while
designing these solutions i~to the system.,
The four most basic elements of' a discrete switching
regulator power supply are:
1. The SMPS IC (which includes the switch control
element and logic, along with the power switch itself),
.
2. An inductor for storage and transfer of energy between the input and output,
3. A switching diode to direct the inductor energy to
"catch", or channel, the inductor energy to the output, and
4. An output filter capacitor.

E.2 Obtaining Shutdown Using Logic
LevelPFETs
.
Low "on" resistance logic level PFETs can be used on
the high side of the input to the DC-DC converters to
obtain shutdown. Onesuch part istheSi940S from Siliconix Inc. The device is part of the "little foot" series,
and is available in an S08 (8-pin surface mount) package. The Si940S is a logic level PFET with an "on re-

Vee

Vpp

Rl
107k,O.1%

R4
2.2M

R3
lOOk

5%

'>---

Vpp VALID

Ul .

R2
12.4k,O.1%

01

01:LlNEAR TECHNOLOGY CORP LT1004-1.2
U1:LlNEAR RECHNOLOGY CORP LT 10 17CNS

FigureE-1.Vpp Valid Handshake Circuit

3-426

292092-13

infel~

AP-357

. In the boost configuration where the output voltage is .
greater than the input voltage, the basic switching power supply configuration is as shown in Figure E.2:

'---1,,"""-~-""'--

your

292092-14

Figure E-2. Working oHhe Step-Up
Switching Regulator

The power switch SW can be turned on and off; the
control for it is derived from a feedback mechanism
that senses the output voltage. While the switch is
turned on, the inductor stores energy as the current
flows through it from the input supply. The peak current through the inductor IL can be approximated as
(VINIL • tON); where tON is the on time of the switch.
During this time, the energy is supplied by the input
voltage, VL = VIN. The output is isolated from the
inductor via the reverse-biased diode, and the load current is supplied by the output filter capacitor. When the
switch turns off, the energy stored in the inductor appears as a rapidly increasing voltage across the inductor. As soon as this voltage reaches a value equal to the
output voltage plus the voltage drop across the diode,
the diode switches on and current starts to flow
through the diode. This diode current supplies the load
current while also at the same time charging up the
output filter capacitor to the output voltage.
The switch is controlled by sensing the output voltage
via a feedback mechanism-usually a pair of resistors.
This sense voltage is gated via a comparator whose output acts as a control signal to an oscillator. The oscillator output controls the switch.
The power into the inductor PL can be approximated
as:

and the power into the load PLOAD (out of the inductor) can be approximated as.
PLOAO

=

(VOUT

+

Vo -

VIN) • lOUT

The peak currents through the inductor is usually several times higher than the load current, is mostly of the
value of the load current and builds up during time
tON' On most of the solutions presented here, peak operating currents lie in the range of 500 mA to 1.2A.
Though this may seem high, most of this in-rush of
energy is transferred to the output, and little is lost to
heat due to the efficient energy storage characteristic of
indu~tors. Note that since the peak currents are high,
the. mput voltage source must be capable of providing this current, and the current capability of the
input source must not be calculated simply as
(VOUT • IOUT)I(VIN • Eft). A large bypass capacitor
at the input pin of the converter is hence also necessary
on all designs.
Some of the solutions presented in this application note
are of the fixed duty cycle or fixed on time type (e.g.
LT1110-12, LTll09-12, MC34063A), whereas some of
them vary the duty cycle depending on the load current
(e.g. MAX732, MAX658). These latter ones provide
higher efficiencies.

Inductor Selection
The choice of an inductor is crucial to the design of the
power supply system. To begin with, the inductor value
must be low enough to supply the peak currents needed
when the input voltage VIN, as well as the on time ton,
are at their worst case low value. On the other hand
the inductor value must be high enough so that th~
peak currents at the worst case high values do not exceed the maximum peak currents that can be handled
by the switch. Furthermore, once the value has been
picked, the physical inductor that is chosen for the job
must be able to handle these peak currents, and must
not saturate. This is done by picking an inductor whose
DC current rating is more than the worst case peak
current that will be required by the operation of the
device. The other characteristic to consider is the resistance of the inductqr. In order to keep losses to a minimum, it is essential that· the resistance of the coil is a
minimum. Thus, it is important to use the inductors
specified in the parts list that accompanies the solutions. These have been carefully chosen after reviewing
the requirements. Alternate inductors may be used, as
long as they are "equivalent".

EMI Concerns
Since the switching regulators presented in this application note switch at frequencies between 60 KHz and
200 KHz, there exists a potential for EMI. In cases
where EMI may be a problem, shielded inductors can
be used. This will reduce EMI significantly. Shielded
versions of the inductors specified are readily. available.
Contact the vendor directly for these.

3-427

intel"

AP·357.

Output Switching Noise
Output switching noise has several sources. The most
significant one is the IR drop through the ESR (Equivalent Series Resistance) of the output filter capacitor.
This is caused by switching current pulses from· the
inductor. There is also noise in the form of switching
spikes riding on the DC output. This is due to the output filter capacitor's ESL (Equivalent Series Inductance), current spikes in the ground trace and rectifier
turn-on transients.
It is important to use low ESR and low ESL output and
input filter capacitors. Proper layout is also essential in

order to avoid spikes in the output. The safest solution
is to use a filter circuit at the output. LC filters are not
recommended, because of the transient nature of the
load currents on flash devices. An RC filter is recommended on most solutions as an option. Two In resistors are used in parallel to avoid causing a significant
drop across the resistance. This method is inexpensive
and assures that the spikes riding on the output waveform are contained to within the 5% tolerance requirement on Vpp.
In addition, care must be taken to keep the leads from
the output of the solution to all flash devices as short as
possible. Use of a 0.1 p,F capacitor at the Vpp pin of
each flash device is highly recommended.

3-428

intel .

AP-357

,
APPENDIX F
PC LAYOUTS FOR SOME RECOMMENDED SOLUTIONS
F.1

Maxim Integrated Products
MAX732

The double-sided layout presented below (Figure F-l)
has been designed for the MAX732 5V -12V converter
solution (Section 3.1). It is a double sided layout and
has been designed for the parts specified in the parts list
that accompanies the solution. Contact Maxim for any
additiona1layout assistance.

F.2 Linear Technology Corporation
LT1110-12
The single-sided layout presented below (Figure F-2)
can be used to implement the LTlllO-12 5V to 12V

converter (Section 3.2), the LTlllO-12 3V-12V converter (Section 4.1), or the LTlllO-5 3V to 5V cOnverter (Section 5.2). The lay.out has been designed for the
parts that are specified in the parts list that accompanies these solutions. Contact Linear Technology for any
additiona1layout assistance.

F.3 Linear Technology Corporation,
LT1109-12
The single-sided layout presented below (Figure F-3)
can be used to implement the LTlI09-12 5V -12V converter solution (Section 3.3). The layout has been designed for the parts that are specified in the parts list
that accompanies the solution. Contact Linear Technology for any additiona1layout assistance.

Surface Mount Drilling Guide (1X Scale)

(Component Placement Diagram)

292092-16

292092-15

.•

(1 X Scale Bottom Side Trace View)

(1X Scale Top Side Trace View)

:'~

~l..
r~

REV A ,

..

'MAXIM
292092-17

Figure F·1

3-429

292092-18

intel . ·

AP-357

(2X Scale Component Placement Diagram)

(2X Scale Trace View)

VR1

D

R2

I \e21

292092-20

292092-19

.. (1X Scale Trace View)

(1X Scale Component Placement Diagram)

Ii~~,

292092-22

Figure F-2

',I'

3-430

AP-357

(2X Scale Trace View)

(2X Scale Component Placement Diagram)

@]

8m
@]

292092-25

292092-26

(1X Scale Trace View)

i

(1X Scale Component Placement Diagram)

@J

o

(0=
@]
292092-27

292092-28

Figure F-3

'i .'.

3-431

. APPLICATION
, NOTE

AP-359

.• ,August 1992

28F008SA
. Ha~dware Interfacing

BRIAN DIPERT

MCD MARKETING 'APPLICATIONS
"

Order Number: 292094-002
3432

28F008SA Hardware Interfacing
CONTENTS

PAGE

CONTENTS

PAGE

1.0 INTRODUCTION ................... 3·434

ADDITIONAL INFORMATION .......... 3-440

2.0 HARDWARE INTERFACING ....... 3-435
2.1 Vpp (Byte Write/Block Erase
Voltage) .......................... 3-435
Vpp Generation Circuits . '.... : .... 3-436
Controlling Vpp to2BFOOBSA
Component(s) ; ................. 3-436
2.2 RY /BY (Ready/Busy) Output .... 3-437
2.3 PWD (Powerdown) Input ....... ; . 3-437
Deep Powerdown Mode ... ; .. ; .. ; 3-437
Write Protection .............. ; ... 3-438
2.4 WE (Write Enable) Input ......... ~-438
2.5 High Densitylln2 Layout ......... 3-438
2.6 Power Supply Decoupling ........ 3-439
. 2.7 High Speed Design Techniques .. 3-440
2.B Example Bus Interfaces .......... 3-440

APPENDIX A: Intel386TM SL PI Bus
Inte.rface .............................. 3-441
APPENDIX B: Intel486™ SX Local CPU
Bus Interface ....... ; ............... 3-442

f

3-433

I',

AP-359

1.0

• Automated Byte Write and Block Erase
- Command User Interface
- Status Register

INTRODUCTION

The 28F008SA FlashFile™ Memory is. a .. veryhigh
performance 8 Mbit (8,388,608 bit) memory, organized
as I Mbyte (1,048,576 bytes) of 8 bits each .. The
28F008SA contains sixteen 64 Kbyte (65,536 byte)
blocks, each block separately eraseable and capable of
.100,000 byte write-block erase cycles. On-chip automation dramatically simplifies software algorithms, and
frees the system microprocessor to service higher priority tasks during component data update. An enhanced
system interface allows switching the 28FOO8SA into a
. deep powerdown mode during periods of inactivity, and
gives a hardware indication of the status of the internal
Write State Machine. High-speed access time allows
minimal wait-state interfacing to microprocessor buses,
and advanced packaging provides optimum densityl
in 2.

• System Performance Enhancements
- RY/BY Status Output
~ Erase Suspend. Capability
• Deep Powerdown Mode .
--' . 0.20 /-,-A ICC Typical
• Very High Performance Read
- 85 ns Maximum Access Time
• SRAM-Compatible Write Interface
• Hardware Data Protection.Features
- EraseIWrite Lockout. during Power Transitions
• Industry Standard Packaging
- 40 Lead TSOP, 44 Lead PSOP I
• ETOXTM III Nonvolatile Flash Memory
Technology
- 12V Byte Write/Block Erase

Features of the 28FOO8SA include:
• High-Density Symmetrically Blocked Architecture;
- Sixteen 64 Kbyte Blocks
• Extended Cycling Capability
100,000 Block Erase Cycles
1.6 Million Block Erase Cycles per Chip

...
CPU
I

.

...

,....

DRAM

,....

I

CACHE

CPU

DISK

CACHE

Today's Memory Paradigm

I

...

[

~
FLASH

CACHE

I

DRAM

The Future, Using Flash Memory

292094-1

Figure 1. The 28F008SA Revolutionizes the Architecture of Computing

3-434

int:et

AP-359·

0"0 - DO,

r-~~~+4-l---CE
14--+_---iE
~_----OE

~~~~--------~--P.D

r:::'}-;:===:::;-+

OV/"
Vpp

292094-2
FI~ure

2. 28F008SA Block Diagram

Traditional system architectures combine slow, high
density nonvolatile mass storage (such as a disk drive)
and fast, volatile memory (such as DRAM) to fully
address system requirements. As· Figure 1 illustrates,
flash memory combines the best features of both the
above memory technologies, making a "disk/DRAM"
approach to system architecture unnecessary and ultimately wasteful. Flash memory is rapidly approaching
DRAM in both cost and performance (especially in
cached systems), while adding capabilities (such as nonvolatility), that DRAM cannot claim. The 28FOO8SA
will be the building block memory of choice for emerging computing markets, whether integrated in a memory card or disk drive form factor, or resident on the
system motherboard.
This application note discusses hardware interfacing of
the 28FOO8SA flash memory to system designs. The
28FOO8SA datasheet (order number 290429) is a valuable reference document, providing in-depth device
technical specifications, package pinouts and timing
waveforms. Additionally, companion application note
AP-360, "28FOO8SA Software Drivers" (order number
292095) provides example ASM-86 and "C" routines
for controlling the 28FOO8SA. AP-364 "28FOO8SA Automation and Algorithms" discusses in-depth operation
of the 28FOO8SA Write State Machine and internal algorithms, emphasizing how they interface to system
software and hardware. AP-360 and AP-364 should be
reviewed in conjunction with this application note and
the 28FOO8SA datasheet for a complete understanding
of this device.

2.0 HARDWARE INTERFACING
Figure 2 shows a block dia&!!.m of the 28FOO8SA and
its internal contents. The CE (chip enable) and OE
(output enable) inputs have comparable enable and
read functions to those of other memory technologies
such as SRAM. Similarly, Vee is the component power
supply (5V ± 10%), while GND should be connected·
to system ground. Address inputs allow the system to
select a specific byte for reading or writing!erasing, and
the 8-bit data bus transfers information to and from the
28FOO8SA. The other control lines (WE, PWD,
RY/BY and Vpp) are discussed below.

2.1 Vpp (Byte Write/Block Erase
Voltage)
The Vpp input supplies high voltage to the 28FOO8SA
to enable byte write and block erase. Vpp is specified at
12V ± 5% (11.4V -12.6V). Attempting to byte write or
block erase the 28FOO8SA beyond the 5% 12V tolerance is not recommended. Vpp above 12.6V can potentially result in device damage, and Vpp below II.4V
dramatically lengthens write/erase time and compromises data reliability. The 28FOO8SA is guaranteed to
prevent byte write and block erase attempts with Vpp
below 6.5V, and in this situation it reports a "low Vpp
error" through the component Status Register (see
AP-360, AP-364 or the 28FOO8SA datashe~t).

3-435

intet

AP-359

Vpp Generation Circuits

12V is often already present in systems, used to power
the hard drive, display, RS-232 circuitry, flash BIOS
update, etc. If it meets the tolerance and current capability requirements of the 28FOO8SA, such a power supply could be used directly as" the 28FOO8SA update
voltage source. However, 12V is sometimes not present
or otherwise required, and in such cases, the 28FOO8SA
Vpp must be derived from existing voltages and sup:
plies.
Fortunately, flash memory's rapidly increasing popularity has driven ever-improving 12V converter availability in the market. These solutions derive a regulated
12V from a wide range of input voltages, and offer varied levels of integration and current delivery capability.
In general, the input for 12V converters should come
from the unregulated system power source, particularly
in battery-powered systems.

PWD is at VIL (see section 2.3). This provides data
protection during system powerup, when the minimally-loaded Vpp supply often ramps to 12V before Vee
(and therefore control inputs to the device) are stable.
For additional data protection, the system designer can
choose to make the Vpp supply switchable via a GPIO
(General Purpose Input/Output) line, enabling 12V to
the 28FOO8SA only during byte write or block erase
attempts. A switchable Vpp also minimizes power consumption by both the flash memory components and
the 12V supply or converter (due to efficiency losses).
Many 12V converters integrate an ENABLE input,
eliminating external circuitry. If such an input is not
available, a low drain-source resistance MOSFET
switch such as the Motorola MTD4P05 can be used at
the 12V supply output. An example schematic for this
switch is shown in Figure 3. The calculations below
show that the low drain-source resistance of the
MTD4P05 will keep a 12V input within the 5% tolerance required by the 28F008SA.

Table I lists and briefly describes several 12V generation solutions available at the time this document was
published. This is by no means an exhaustive list, and
does not reflect any specific recommendation by Intel
Corporation. For in-depth information on power supply solutions for flash memory, reference Intel application note AP-357 (order number 292092), available
through your local Intel sales office or distributor.

RDS

=

O.SIl

Ipp = SO rnA

. (worst case, two components being byte written or
block erased)
!:J. VSWITCH DROP

= (SO

rnA X O.SIl)

=

0.04V

12V

Controlling Vpp to 28F008SA Component(s)

Once .12V is available in the system, how is it controlled? One approach is to hard-wire 12V from the
supply directly to the Vpp inputs of each 28FOO8SA in
the system. The advantage here is in design simplicity
and board space savings. The 28FOO8SA Command
User Interface architecture and two-step byte write/
block erase command sequences provide protection
from unwanted .data alteration even with high voltage
present on Vpp. All 28FOO8SA functions are disabled
with Vee below lockout voltageVLKO (2.2V), or when

10K

GPIO
10K

292094-3

Figure 3. Vpp Switch Schematic

Table 1. 12V Conversion Solutions for Vpp
Manufacturer

Part
Number

Input
(V)

Package

Current
Output

Total
Components
Needed

Est.
Cost
(10K)

Maxim

MAX732

4 to 7.5

16S0lC

120 mA

9

$3.93

Linear Technology

LT1110-12

4.5 to 5.5

S08

120 mA

11

$4.58

Linear Technology

LT1109-12

4.5 to 5.5

S08

60mA

8

$3.61

Motorola

MC34063A

4.5 to 5.5

S08

120 mA

15

$2.25

Maxim

MAX667

12.1'to 16.5

S08

120 mA

4

Linear Technology

LT1111-12

16 to 30

S08

120 mA

7

$3.95

National Semiconductor

LM2940CT-12

13 to 26

TO-220

1A

3

$1.30

3-436

."

$2.63

infel"

AP-359

2.2 RY /BY (Ready/Busy) Output
The 28FOO8SA offers similar automated byte writel
block erase capabilities to those first seen in the
28FOOIBX Bootblock flash memory family, introduced
by Intel in May of 1991. It enhances these capabilities
via the RY/BY output, which provides hardware indication of internal Write State Machine (WSM) operation. RY/BY is a full CMOS output, constantly driven
by the 28FOO8SA and not tristated if the device CE or
OE inputs are brought to VIR. RY/BY's default state
after device powerup is VOH. It transitions low to VOL
when a byte write or block erase sequence is initiated by
system software, and RY/BY's rising edge (return to
VOH) alerts the system to byte write or block erase
completion., RY/BY also goes to VOH after the
28FOO8SA is put in Erase Suspend or Deep Powerdown
modes.

iffi---M
WR---M
cs---M

Ao---M
INT
00 - 7 - - -

292094-4

Figure 4. EPLD·Based RY IBY Implementation
+5V
10K

RY /BY is intended to interface the 28FOO8SA to a system microprocessor rising-edge-triggered interrupt input. In a multiple-chip memory array, external EPLD
logic or an interrupt controller can be used to combine
and prioritize RY/BYs into one system interrupt (see
Figure 4). The system can then, using a flash memory
"activity table" set up in RAM, poll the individual
28FOO8SA Status Registers to determine which device
has returned "ready", or read the RY/BY inputs directly at the EPLD, as shown.
Figure 5 provides an alternative method for connecting
multiple RYIBY s to one interrupt input. The diode/resistor combination converts the 28FOOSSA full CMOS
output into an open-drain "wired-OR" equivalent. Any
RY/BY at VOL will drive the interrupt input low, and
this .!!!Eut is pulled high by the resistors when all
RY/BYs are at VOH. It is important in a design like
this to use diodes with low forward voltage drops, so
that the 28FOO8SA VOL (0.45Y) plus the diode voltage
drop is still less than or equal to the destination input
VIR (O.SY). For the schematic shown in Figure 5, the
equation is:
VOL

+

VDIODE = 0.45 VMAX

+

O.3V = O.75V :;;; O.8V

Note that should the system connect RY/BY to an interrupt, disable that interrupt prior to suspending erase,
as RY IBY will transition to VOH when the device is
suspended.

t.tB0301

INT-...........---1

t.tB0301

t.tB0301

292094-5

Figure 5. "Wired-OR" RY IBY Implementation

2.3 PWD (Powerdown) Input
Deep Powerdown Mode
The PWD input, when driven to VILby the system,
switches the 2SFOOSSA into a deep powerdown mode
with negligable power consumption. This feature integrates the Vee power FET often used with low power
designs. Power consumption thru~c is typically
1 JL W in deep .powerdown mode. PWD-Iow deselects
the memory, places output drivers for DO-7 in a high~
impedence state and turns off a majority of internal
circuits. RY/BY is driven to VOH while in deep
powerdown mode. Depending on the flexibility desired,
system designers can choose to put either the entire
flash device array into deep powerdown mode, or any
individual components via selective input control. The
28FOO8SA requires a "wakeup" time after PWD returns to VIH before it can be successfully written
(tPHWV or outputs are valid to read attempts (tPHQV)'

3-437

inteL

Ap·359

Write Protection

Since PWD = VIL deselects the 2SFOOSSA, this input
can be used not only as a means of entering deep powerdown mode but also as an active-high "chip enable"
to block spurious writes during system power transitions. Figure 6 shows one possible PWD implementation, controlled by a GPIO line for power management
and by a system POWER GOOD for power sequencing
protection. In this design, the 5V monitoring circuit
begins functioning at Vee = I V, and will enable the
device only after Vee transitions above 4.6V (and system control signals are therefore stable). As Vee drops
below 4.6V during system powerdown, PWD protection is again activated.
Vee

PWD (TO 2BFOOBSA)
Under-Voltage
Sensing Circuit

292094-6

Figure 6. PWD Gating

2.4 WE (Write Enable) Input
When flash memory is written, the result can range
from a 2SFOOSSA that is placed in "read intelligent
identifier" or "read Status Register" niodes to alteration of nonvolatile flash memory contents. System
hardware can prevent spurious writes to flash memory
by application software or an op~rating system by gating the system WE to flash memory components to
enable writes only when desired.
Figure 7 shows a simple design that gates WE with a
GPIO line, enabling writes to the 2SFOOSSA only when
the GPIO is a"O". The GPIO is initialized to "I" on
system powerup and the BIOS, a dedicated update software routine, a special keyboard sequence, switch on
the back of the system or jumper on the system motherboard can then control the GPIO. This circuit ensures
that flash memory contents are as permanent as
"ROM" unless alteration is 'specifically desired.

WR(FROM SYSTEM)
GPIO

=D-.-( .' )
WE TO 28F008SA

292094-7

Figure 7. WE Gating

2.5 High DensityIIn 2 Layout
Figure S shows an S Mbyte flash memory array using
TSOP (Thin Small Outline)-packaged 2SFOOSSAs in
standard (E) and' reverse. (F) configurations. A layout
like this is used in Intel's Series II Flash Memory Cards
(in densities to 20 Mbytes) and provides optimum array
density for available board space.
Address and data lines are connected to all components
in parallel. OE and WE are similarly connected. Section 2.7 of this document discusses alternate methods of
implementing these signals for highest speed reads and
writes in large memory arrays.
Component RY/BYs are shown ,as not connected in
Fig,ureS. They can be leftunu~ed, in which case the
system software will substitute. polling of component
Status Registers for hardware interrupt, or RY/BYs
can be implemented as described in section 2.2.
CEs are also not connected, intended to be individually
driven by system chip enable decoding logic. This provides capability to read from and write to the array on a
byte-by-byte basis. In ax 16-only system, upper and
lower byte 2SFOOSSAs can have their CEs bused together if desired.
Finally, Vee, Vpp and PWD are connected in parallel
to all components. Section 2.6 discusses bypass capacitor filtering of sup.E!r..Y.0ltage inputs, while section 2.3
provides uses for PWD. If desired, individual component, component pair, etc. selective powerdown control
can be substituted for the global control shown in
Figure S.
In space-constrained designs, a' multiple-layer partial
"serpentine" trace layout at the edges of the 2SFOOSSA
array may .be implemented, with a full serpentine layout within the array as in Figure 8.

int:eL

AP-359

·1
VSBOOJBl3.

V~9OOJBlJ

0
0

0

6

;

E28FOO8SA

~i
r;::==
r;:::=
r;::=
r;::

r--

F28F008SA

'===

'""==
;::::::

>----

r--

rr

Ir
IL ~

§

...:::

...::==

>----

-

0
0

VSBOOJBl3

I---

II

D

It

I

E28FOO8SA

-'=
-=
====

>----

...::=
~

VSBOOJBlJ

IL

0

f'-'-

F28F008SA

-

;

§

292094'-8

FigureS. TSOP Serpentine Layout

Assumptions:

2.6 Power Supply Decoupling
Both the Vee and Vpp inputs to each 28F008SA
should be decoupled at the package leads to provide
noise immunity and supply current for transient cure
. rent spikes during read, byte write and block erase. Additional bulk capacitance for groups of flash memories .
overcomes voltage slump caused by PC board trace inductances. Calculations for individual component and
bulk capacitors (one per 8 devices) are shown below.

I = 35 mA ~er device (Veel, therefore
I = 17.5mA per device input (Veel
I "" 30 mA per device (Vpp)

dv = O.1V (O.2V peak·peak)
dt=20ns

Per-Component-Input Decoupling Capacitor (Ved:
C = I dtldv = (17.5 mA x 20 ns)/O.1V = 3.5 nF

Basic Equation:
I = C dv/dt

4x margin = 4

x

3.5 nF = 14 nF

Standard Equivalent = 0.01 ,..,F

3-439

NOTE:
Calculations above assume that each 28FOO8SA is
driving CMOS inputs (with correspondmg highimpedance and I).egligible input current requirements). If
28FOO8SA outputs are driving non-CMOS inputs,
larger per-component capacitance may be needed to
supply 'current while outputs are switching., '
'B\ilkCapacitor (Vee):

C=
,

10 x (Total of Decoupling Capacitors)

Bulk Capacitor (4 Mbyte array) = 10 x (8
;= 0.8,..,F

X 0.Q1 ,..,F),
I

Standafcl Equivalent = 1 ,..,F '

Per-Component Decoupling Capacitor (Vpp):

C = I dtldv = (30 mAx

20 ns)/O.1V == S nF

• Minimize address, b~s loading from the microprocessor to the memory array. Multiple address latches
feeding subsets of the array speed address input, to '
each 28FOO8SA and 'CE decoding by external logic.
•

,Similarly~

drive the memory array with multiple ,
OES and WEs. Most EPLD and discrete logic timing is specified at a 30" pF load, which equates to
driving 4 28FOO8SAinputs at maximum input' capacitance. Anything' more than this may severely
impact the logic's propagation delay.
• Finally, remember that each 28FOO8SA, when read,
drives not only the system microprocessor or trans-'
ceiver but also any other flash memory components
connected to the common data bus. Each 28FOO8SA
data output is specified at 12 pF, and the 28F008SA
read timings are tested at either 30 pF or 100 pF of
loading, depending on the chosen speed bin.
For large flash arrays where sequential data can be distributed on many devices, hardware interleaving provides additional performance.
'

4xmargin = 4 x SnF = 24nF
Standard Equivalent = 0.033 ,..,F

2.8, ,Example Bus Interfaces
Appendix
~hows hardware interface to the Intel386TMSL PI bus, and Appendix B shows interface to
the Intel486™SX 10ca1CPU bus; Both interfaces incorporate techniques' described, in sections 2.1-2.7 of
this document. These designs are intended to be examples which can be modified to suit requirements of the
end system.
\,

A,

2.7 High Speed DeslgnTechnlqu~s"
The 28FOO8SA's f~t read access, and' command write
specifications make it a naiural choice for high performance memory arrays. The following tips willopti'mize the memory interface for optimum read/write
speed. The common recommendation in 'iill instances
centers around minimizing fanout and, capacitive 'bus
loading to allow highest switching speed, 'lowest rise
,and fall times, and therefore, greatest performance.

ADDITIONAL INFORMATION
Order Number
AP-357
AP"360
AP-364
ER-27
ER-28

28F008SA Datasheet ,
28F008SA-L Datasheet
"Power Supply Solutions for Flash Memory"
,"28F008SA SoftWare Drivers"
"28F0083A Automation and Algorithms"
"The Intel 28F008SA Flash Memory"
"ETOXTM-III Flash MemoryTechnology"

3-440

290429
, '290435
292092
292095
292099
294011
294012

infel·

Ap·359

APPENDIX A
Int,1386™SL PI BUS INTERFACE
I2V

5"'-16 •
LA,7 20

-

.... --:
SAo-16'~ r
L"'7-20

SAo.
LA21 - 22
LATCH --,.:,
~

SBHE
PSTART
80381SL

-r

~r---::!
..
pPLD

pw!iO
PW/R
FLSHDCS

::!

<

'"

.GO

0

TO OTHER

0
....
GO

m ••i ..••

-+-

WR

N

WE

RD

RV/Bvl

Ts
-.3

.... ~SOo-15

RV/Bv

AI '"

Il00-7

SOo-7 .

SOo-7J,.

--

PWO

\

iii
",

CE'

<

'"0

::: Vpp .

,,
,,
,

~ -iz.-Lrr- ~
-_.~RESET
•

GO

....
GO

O~

N

WE
OE
RV/Bvl

.oil

~

..
~
....
.... ,
p",
".,,

"'v,

,,

1·11,

",
",,

PWD

000-7

S08-15

~

~

82360SL
Controller

Ao-l~:i:_----,.... .......
.. ~",: :

cs, .

VGACS

INT

.....
...... ,
",
..
,:,.

OE

~

PRDV

/

Ao-l~:i:_----'
. •.•••
......
~::
."
",
",
"
",
",,

CE .•••

CSL1
CSHI

~

PCND

Vpp

Switch:

~

RESET.-t
PWRGOOO -t

WR

RY!iY, '
RV!iY2
EPLD(s)

~}
~
~
.

R'!iY

FROM OTHER

. m .....·•

~PWO
,

~} TO';~Ea
f::2.F..... ·
,PAIRS

.

292094-9

NOTE:
The DRAM interface is not shown. for graphic simplicity.

3-441

AP-359

APPENDIXB
Intel486™ SX LOCAL CPU BU,S INTERFACE

12V
Vpp
Switch

r\-~
t___ f'.--I-

GPIO
RESET

o/e
Int.14B6T111SX

w/R

-----oofI

I-""/IO""=-O

LO,-31
Trans~

eeiv"

292094-10

NOTE:
The DRAM interface is not shown. for graphic simplicity:

REVISION HISTORY
Description

Number

-002

Added 1OK resistor to FET output. Figure 3.
Added AP-364 references.

3-4.42

APPLICATION
NOTE

AP-360

November 1992

28F008SA
Software Drivers·

BRIAN DIPERT
MCD MARKETING APPLICATIONS

Order Number: 292095·002

3·443

28F008SA Software Drivers
,CONTENTS

PAGE

1.0 INTRODUCTION . .................. 3-445
2.0 ASM86 ASSEMBLY DRIVERS ..... 3-446
3.0 "C" DRIVERS ..................... 3-450

CONTENTS

PAGE

ADDITIONAL INFORMATION ......... 3-464

int'et

Ap:"360

1.0 INTRODUCTION
This application note provides example software code
for byte writing, block erasing and otherwise controlling Intel's 2SFOO8SA S Mbit symmetrically blocked
FlashFile™ Memory family. Two programming lan~
guages are provided; high-level "C" for multi-platform
support, and ASM-S6 assembly. In many cases, the
driver routines can be inserted "as is" into the main
body of code being developed by the. system software
engineer. The text accompanying each routine describes
the existing code and suggests area for possible alteration to fit specific applications. These explanations,
along with in-line commenting, minimize driver modification efforts.

Companion product datasheets for the 2SFOOSSA and
28FOOSSA-L are valuable reference documents. Datasheets should be reviewed in conjunction with this application note for a complete understanding of the devices. AP-359, "2SFOOSSA Hardware Interfacing" is
the hardware-oriented application note equivalent for
these devices and can also be referenced.
The internal automation of the 2SFOOSSA makes software timing loops unnecessary and results in platformindependent code. This software is designed. to be executed in any type of memory and with all processor
clock rates. "C" code can be used with many microprocessors andmicrocontrollers, while ASM-S6 assembly code provides the smallest code "kernal" for Intel
microprocessors and embedded processors.

3-445

intel .

AP-360

2.0 ASM-86 DRIVERS
Copyright Intel Corporation, 1992
Brian Dipert, Intel Corporation, February 8, 1992, Revision 1.0
Re,vision History: Rev 1.0
The following code controls byte write of data to a single 28F008SA (x8 write)
DS:[SI] points to the data to be written. ES:[DI] is the location to be written
In protected mode operation. DS and ES reference a descriptor
Register AX is modified by this procedure
WRIrE.SETUP
EQU
40H
READ.ID
EQU
90H
INTEL.ID
EQU
89H ,
DEVICE.ID
EQU
OA2H
DEVICE.ID2
EQU
OA1H
READY
EQU
80H
W.ERR.FI.AG
EQU
lOH
VPP .FI.AG
EQU
OBH
Insert code here to ramp Vpp and disable component /PWD input. If a string of bytes is
to be written at one time. Vpp ramp to 12V and ID check need only occur once.
before the first byte is written
MOV
AX.
'Address 0 for target 28F008SA·segment'
; Initialize poin~er to 2BFOOOBSA address 0
MOV
ES.
AX
MOV
DI.
'Address o for target 28FOOBSA·offset·
READ.ID
; Write Inteligent Identifier command
MOV
BYTE PTR ES:[DI].
BYTE PTR ES: [DI] ,
INTEL.ID
; Does manufacturer ID read correctly? '
CMP
W.BU_ID.ERR
JNZ
MOV
DI.
'Address 1 for target 28FOOBSA·offset"
,; Initialize pOinter ,to 28FOOBSA address 1
CMP
BUE PTR ES: [DI] • DEVICE.ID
; Does device ID read correctly?
JZ
W.BYT.ID.PASS
CMP
BYTE PTR ES:[DI].
JNZ
W.BYT.ID':ERR
W.BU.ID.PASS:
MOV
MOV
MOV
MOV
MOV
MOV
W.BYT.LOOP:
TEST
JZ

AX,

"Byte write destination address·segment"
; Initialize pointer to byte write dest. address

ES.
AX
DI.
"Byte write destination
BUE ,PTR ES:[DI].
WRITE.SETUP;
AL.
DS:[SI]
;
ES: [01]. AL
;

address·offset'
Write byte write setup command
Load AL with data to write
Write to device

BYTE PTR ES: [DI] •
W.BYT.LOOP

READY

; Read 28FOOBSA Status Register
; Loop until bit 7
1

TEST
JZ

BYTE PTR ES:[DI].
W.BYT.CONT

(W.ERR.FLAG OR VPP .FI.AG)

TEST
,JNZ

BYTE PTR ES:[DI].
W.BU.ERR

W.ERR.FI.AG

TEST
JNZ

ES:[DI]. VPP.FLAG
W.BYT.VPP

=

Success!

Check Status Register bit 4
Jump if
1. Byte Write Error

=

Cheok Status Register bit 3
Jump it
1. Vpp Low Error,

=

W.BYT.ID.ERR:
Insert code to service improper devioe ID read error here.
Is 2BFOOBSA /PWD input disabled? Is Vee applied to the 2BFOOBSA?
W.BYT.ERR:

.

Insert code to service byte write error here

W.BYT.VPP:
Insert code to service byte write Vpp low erro'r here

W.BYT.CONT:
Code continues from this point •••••

This routine writes a byte of data to a single 28FOO8SA. Note the use of BYTE PTR notation to force x8 accesses. If
a string ofbyteil is to be written at one time, the Vpp ramp up, PWD disable and device ID checks need only be done
before the first byte write attempt. Additionally, when writing multiple bytes at once, examination of bits other th~
bit 7 (WSM Status) need only occur after the last byte write has completed. The Status Register retains any error bits
until the Clear Status Register command is written.

3-446

AP-360

The following code controls byte write of data to a pair of 28F008SAs (x16 write)
DS:[SI] points to the data to be written, ES:[DI] is the location to be written
In protected mode.operation, DS and ES reference a descriptor
Register AX is modified by this procedure
WRITE. SETUP
EQU
40H
READ.ID
EQU
90H
INTEL.ID
EQU
89H
DEVICE.ID
EQU
OA2H
DEVICE.ID2
EQU
OA1H
READY
EQU
80H
W.ERR.FLAG
EQU
lOH
VPP.FLAG
EQ~
08H
Insert code here to ramp Vpp and disable component /PWDinputs. If a string of words is
to ,be written at on~ time~ Vpp ramp to 12V and ID check need only occur once,
before the first word is written
MOV
AX,
"Address 0 for'target 28F008SA·segment"
; Initialize pointer to 28F008SA address 0
ES,
AX
MOV
DI,
"Address 0 for· target 28F008SA·offset"
MOV
ES: [DI],
((READ.ID SHL 8) OR READ.ID)
MOV
; Write Inteligent Identifier command
ES: [DI] ,
«INTEL.ID SHL 8) OR INTEL.ID)
CMP
; Does manufacturer ID read correctly?
JNZ
W.WRD.ID.ERR
MOV
DI,
"Address 1 for target 28F008SA·offset"
; Initialize pointer to 28F008SA address 1
CMP
ES: [DI],
((DEVICE.ID SHL 8) OR DEVICE.ID)
; Does device ID read ,?orrectly?
JZ
W.WRD.ID.PASS
CMP
ES: [DI] , «DEVICE.ID2 SHL 8) OR DEVICE.ID2)
W.WRD.ID.ERR
JNZ
W.WRD.ID.PASS:
MOV
MOV
MOV
MOV
MOV
MOV
W.WRD.LOOP:
TEST
JZ

AX,

"Byte write destination address-segment"
; Initialize pointer to byte write dest. address

ES,
DI,
ES:[DIJ,
AX,
ES:[DIJ,

AX
"Byte write destination address-offset"
«WRITE.SETUP SHL 8) OR WRITE~SETUP)
; Write byte write setup command
DS:[SI]
Load AX with data to write
AX
; Write to devices

ES:[DIJ,
«READY SHL 8) OR READY) ; Read 28F008SA Status Registers
W.WRD.LOOP
; Loop 'until bit 7 = 1
ES: [DIl. « (W.ERR.FLAG OR VPP.FLAG) SHL 8) .OR (W.ERR.FI.AG OR VPP.FLAG))
W.WRD.CONT
Success!

Ax,

MOV
TEST
JNZ
,TEST
JNZ

ES: [DIJ
AL,
W~ERR.FLAG
W.WRD.ERR
AH,
W.ERR •.FLAG
W.WRD.ERR

Load Status Register data into'AX
Check Status Register bit 4 (low byte)
Jump i f
1
Check Status Register bit 4 (high byte)
Jump if
1

TEST
JNZ
TEST
JNZ

AL,

Check Status Register bit :5 (low byte)
Jump if
1
Check Status Register bit :5 (high byte)
Jump.if
1

VPP.FLAG

W.WRD~VPP

AH,
VPP.FLAG
W.WRD.VPP

=
=
=
=

W.WRD.ID.ERR:
Insert code to service improper device ID ~ead, error,here.
Are 28F008SA /PWD inputs disabled? Is Vee applied t~ the 28F008SAs?
W.WRD.ERR:

Insert code to service byte write error here
W.WRD.VPP:
Insert code to service byte write Vpp low error here
W.WRD.CONT:
. Code continues from this point •••••

This routine writes a word of data to a pair of 28FOO8SAs. Note that all constants have been "OR'd" for parallel
read/write of two devices at once. If a string of words is to be written at one time, the Vpp ramp up, PWD disable
and device ID checks need only be done. before the first word write attempt. Additionally, when writing mUltiple
words at once, examination of bits other than bi~ 7 (WSM Status) need only occur after the last word write has
completed. The Status Register retains any error bits until the Clear Status' Register command is written.

3-447

Ap·360
The, following code controls block erase .of a single 2BFOOBSA (':8 block erase)
ES: [DI] points to the bloak to be erased
In pratected mode operation. ES,references
descriptor
Register AX is modified by this p,rocedure
ERASE. SETUP
EQU
20H
ERASE. CONFIRM
EQU
ODOH
READ.ID
EQU
90H
INTEL.ID
EQU
B9H
DEVICE.ID
EQU
OA2H
DEVICE.ID2
EQU
OAIH
READY
EQU
80H
E.ERR.FLAG
EQU
20H
E.CMD.FLAG
,EQU
30H
VPP.FLAG
EQU
08H
Insert code here to ramp Vpp and disable component /PWD input. If a string of blockS'is
to be erased at one time. Vpp ramp to 12V and ID check need only occur once.
before.the first block is erased
MOV
AX.
"Address 0 for target 28FOOBSA·segment"
; Initialize pointer to 2BFOOBSA addr.ess 0
MOV
ES.
AX
Dr,
-Address o for target 28F008SA·offset"
MOV
BYTE PTR ES: [DI],
READ.ID
; Write Inhligent Identifier command
MOV
BYTE PTR ES:[DI].
INTEL.ID
; Does manufacturer ID read correctly?
CMP
JNZ
E.BYT.ID.ERR
'Address I for target.2BFOOBSA.offset"
MOV
DI.
; Initialize pointer to 2BFOOBSA address I
BYTE PTR ES:[DI].
DEVICE.ID ; Does device ID read correctly? .
CMF
JZ
E.BYT.ID.PASS
CMF
,BYTE PTR ES: [DI].
JNZ
E.BYT.ID.ERR

a

E.BYT.ID.PASS:
MOV

AX.

MOV
MOV
MOV
MOV
E.BYT.LOOP:
TEST
JZ

BYTE PTR ES:[DI].
E.BYT"LOOP

READY

TEST
JZ

BYTE PTR ES:[DI].
E.BYT.CONT

(E.CMD.FLAG OR VPP.FLAG)

TEST
JNZ

BYTE PTR ES:[DI].
E.BYT.CMD.ERR

E.CMD.FLAG

Check Status Register bits 4 and 5
Jump if
I

TEST
JNZ

BYTE PTR ES:[DI].
E.BYT.ERR

E.ERR.FLAG

Check Status Register bit 5
Jump if
I

TEST
JNZ

BYTE PTR ES:[DI].
E.BYT.VPP

VPP.FLAG

Check Status Register bit 3
Jump if
I

"Block erase destination address.segment"
; Initialize pointer to. block erase dest .address
ES.
AX
DI.
'Block erase destination address·offset'
BYTE PTR ES:tDI].
ERASE. SETUP
; Write bloak erase setup aommand
BYTE PTR ES:[DI].
ERASE. CONFIRM : Write block erase confirm· command
; Read 2BFOOOBSA Status. Register
; Loop until bit 7
I

=

Success!

=

=
=

E~BYT~ID.ERR:

Insert code to service improper device ID read error here.
Is 28FOOBSA /PWD input disabled? Is Vee applied t·o the 2BFOOBSA?
E.BYT.CMD.ERR:
Insert oode to 'service block erase command sequence error here
(setup followed by a command other than confirm)
E.BYT.ERR:
Insert code to service block erase error here
E.BYT.VPP:
Insert code to service block erase Vpp low error here
E.BYT.CONT:
Code continues from this point •••••

This routine erases a block of a single 28FOOSA. Note the use of BYTE PTR notation to force x8 accesses. If a string
of blocks is to be erased at one time, the. Vpp ramp up, PWD disable and device ID checks need only be down before
the first block erase attempt. Additionally, when erasing multiple blocks at once, examination of bits other than bit 7
(WSM Status) need only occur after the last block erase has completed. The Status Register retains any error bits
until the Clear Status Register command is written.

3-448

intel·

Ap·360

The following oode. oont.rols blook erase ot a pair of 28F008SAs (xIS blook erase)
ES. [DI] point.s .t.o t.he blooks t.o be erased
In prot.eoted mode operation. ES references· a descriptor
Register AX is modified by t.his prooedure
ERASE. SETup·
EQU·
20H
ERASE. CONFIRII
EQU
ODOH
READ.ID
EQU
90H
INTEL.ID
EQU
89H
DEVICE.ID
EQU
OA2H
DEVICE.ID2
EQU
OAIH
READY
EQU
80H
E.ERR.FLAG
EQU
20H
E.CND.FLAG
EQV
30H
VPP.FLAG
EQU
08H
Insert oode here to ramp Vpp and disable component /PWD inputs. If a string of blocks. is
t.o be erased at one time. Vpp ramp t.o 12V and ID oheck need only ooour onoe.
before the first block pair is erased
MOV
AX.
"Address 0 for t.arget 28FOOBSA.segment"
; Initialize pointer to 28F008SA address 0
MOV
AX
ES.
MOV
DI.
"Address 0 for target. 28F008SA·offset"
ES.[DI]. «READ.ID SHL 8) OR READ.ID)
MOV
; Write Inteligent Identifier command
CMP
ES.[DI]. «INTEL.ID SHL 8) OR INTEL.ID)
; Does manufaoturer ID read correctly?
JNZ
E.WRD.ID.ERR
MOV
DI.
"Address 1 for target 28F008SA·offset"
; Initialize pointer to 28F008SA address 1
CMP
ES.[DI]. «DEVICE.ID SHL 8) OR DEVICE.ID)
;. Does device ID read oorreotly?
JZ
E.WRD.ID.PASS
CMP
ES. [DI] • «DEVICE.ID2 SHL 8) OR DEVICE.ID2)
JNZ
E.WRD.ID.ERR
E.WRD.ID.PASS.
MOV
MOV
MOV
MOV
MOV
E.WRD.LOOP.
TEST
JZ

"Blook erase destination address·segment"
; Initialize pointer to blook erase deat. address
ES •.
AX
"Block erase destination address·ottset"
DI.
ES.[DIl. «ERASE.SETUP SHL 8) OR ERASE. SETUP)
; Write block erase setup oommand
ESI[DI] .. «ERASE.CONFIRII SHL 8) OR ERASE.CONFIRII)
.
; Write block erase confirm oommand
AX.

ES. [01] • «READY SHL 8) OR READY) ; Read 28F008SA Status Registers
E.WRD.LOOP
; Loop until bit 7
1

=

TEST'
JZ

ES.[DI]. « (E.CND.FLAG OR VPP.FLAG) SHL 8) OR (E.CMD.FLAG OR VPP.FLAG))
E.WRD.CONT
; Suocess! .

MOV
TEST
JNZ
TEST
JNZ

AX.
ES.[DI]
AL.
E.CND.FLAG
E.WRD.CMD.ERR
AH.
E.CND.FLAG
E.WRD.CND.ERR

TEST
JNZ
TES:!:
J.NZ

AL.
E.ERR.FLAG
E.WRD.ERR
AH.
E.ERR.FLAG
E.WRD':'ERR

Cheok· Status Register bit. 5 (low byt.e)
Jump it = 1
Cheok St.atus Register bit 5 (high byte)
Jump if = 1

TEST
JNZ
TEST
JNZ

AL.
VPP.FLAG .
E.WRD.VPP
AH.
VPP.FLAG
E.WRD.VPP

Cheok St.at.us ·Regist.Br bit. :5 (low byt.e)
Jump it = 1
Cheok Stat.us Regist.er i>1t. :5 (high byte)
Jump i t = 1

; Load Stat.us Regist.er data int.o AX
Cheok Stat.us Reg bits 4 and 5 (low byte)
Jump if
1
Cheok St.at.us Regist.er bits 4 and 5 (high byt.e)
1
Jump i t

=
=

E.WRD.ID.ERR.
Insert 004e to servioe improper devioe ID read error here.
Are 28F008SA /PWD inputs disabled? Is Voo applied to the 28F008SAs?
E.WRD.CIID.ERR'
..
.
I
Insert. code to servioe block erase oommand sequence error here
(setup tollowed by a oommand other than oOntirm)
E.WRD.ERR.
Insert oode to servioe blook erase error here
E.WRD.VPP.
;
Insert oode to servioe blook erase Vpp low error here
E.WRD.CONT.
Code oont.inues from this point •••••

3-449

infel·

AP·360

This routine erases a block pair of two 28FOO8SAS. Note that all constants have been "Ok'd" for parallel readlwrlte
of two devices at once. If a string of block pairs is to be erased at one time, the Vppramp up, PWD disable and
device ID checks need only be done before the first block pair erase attempt. Additionally, when erasing multiple
black pairs at oilce, examination of bits other than bit 7 (WSM Status) need only'occur after the last block pair erase
has completed. The Status Register retains any error bits until the Clear Status Register command is written.

3.0

'C' DRIVERS

/.
/.
,.
(.
1*
/.
/.
/.
,.
/.
,.
'"
,.
,.
/.
/.
/.
,.
'"
/"
,.
/.
,.
,.
,.
,.

1*

,.
/.
,.
/.
,.
,.
/.
,.
,.
,.

'I'

*'"

*'

lit. "'. '" '"

lie ............ "' ... '" lie ... "'. III lit '" lit '" "' ...... lit ... "' ... '" lit. "' •• ~ '" lit
"'* '" '" '" lit lit "' ... "'. '" "' ...... "'. lit "' ................. '" lit '" '"
Copyrisht Intel Corporation, 1992
./
Brian Dipert, Intel Corporation, May 7, 1992, Revision 2.1
./
The tollowing drivers control the Command and Status Registers ot the 28F008SA Flash
./
Memory to drive byte write, block erase, Status Register resd and clear and
./
array read algorithms. Sample Vpp and /PWD control blocks are also included,
./
as are example programs combining drivers into tull algorithms
./
The functions listed below are included:
./
erasbgn(): Begins block erasure
.,
erassusp(): Suspends blook, erase to allow reading data'trom a block ot the
.,
28F008SA other than that being erased
.,
erasres () ,: Resumes block erase i t suspended
./
end(): Polls the Write State Machine to determine it block erase or byte write
./
,have completed
,
.,
eraschk():,Executes tull status check atter block,erase oompletion
./
writebB!l(): Begins byte write
"
wrltechk(): Executes tull status check atter byte write oompletion
.,
idread (): Reads and returns the manufaoturer and device IDs of the target
"/
28F008SA
./
statrd (): Reads and returns the oontents' at the Status Register
"/
statclr(): Clears the' Status Register
.,
rdmode (): Puts the 28F008SA in Reac;\ Array mode
, ,
'
./
rdbyte (): Reads and returns a specified byte tram the target 2BFOOBSA
'i
YplluP{): Enables hish voltage, Vpph
./
l'Ppdown() : Disables Vpph
./
pwden(): Enables active 10... Signal ,PWD
./
pwddis () :' Disables active low signal 'PWD'
"/

1* _.... '" '" "' •• ,. '" '" '" '" '" '" "' •• '" '" '" '" '" '"

*'

~

Ad'dresses are transterred to funotions as pOinters to tar bytes (ie long integers). An
alternate approach is,to create a, global array the size ot the 2BF008SA and
located ·over" the 2BFOOBSA in the system 'memory map. AcceSSing specitic
locations ot the 28FOOBSA 1s then accomplished by paSSing the chosen function
an oftset, trom the array basBversus a specitic address. D1tferent
microprooessor arch~tectures .,111 require different arraY,definitions; ie,for
the xB6 architecture, define it as 'byte eightmeg[16][10000]" and pass each
tunction TWO otfsets to aooess a speoitio location. MCS-96 architectures are
limited to "byte eightmeg[lOOOO]"; aiternate approaches such as USing port pins
tor paging will be required to aooess the tull flash array

./

"/
./
./
.,
./
./
./
./
"/

.;

/.
To create a tar pointer, a function suoh as iIK_FP () oan be used, given a segment and
" o f f s e t in the x86 architecture. I use Turbo-C; see your oomp11er reference
/.
manual for a,dditional intormation.

'* . "'....'"

lit ale III lit '" lit III

* *•••• *

*' lit '" lit"'. III lit *."' •• lit lit ...... "' ... "' ... lit * lit lit '" '" lit lit ... lit III lit *' '" '" "' ... "' ••••• * III • • • • *•• :. III. *•• III • • • • • • • • • • • ~'. * *••

1* *' III. **.* III III. III III. III _ III III III ~ • • • __ • /II • • • • • *' •••••••• /II. * * *. * •• * ••• * * ~ *"'. **. *. III •

•.••.••

./
./
./

III III

*/

* *. * * * *•• III * * •• * •• ~ **••••,. *** *I

/.
/.
/.
,.

Revision History: Rev 2.1

,.

Chariges From Revision 1.0 to Revision 2.0: '
Added alternate 2BF008SA device ID to routine idread()

' . ,
./
./
./
./
/.
Changes from 2.0 to 2.1: Revised the Erase Suspend 'algorithm to remove potential
.,
l'
"intinite loop" caused by theWSM going "ready" after the system reads the
./
/.
Status Regi~ter, and before the system issues the Erase Suspend 90mmand
./
/* * III III * * * *. * '* ••• III III. * '* * * •• III * •• * * ** * * * .,* ** *. * •• *. * ** •• '* * ~. *•• *III. * ** *. III III. III III. * ••• * III • • * •• * III * * * * * III. * *. *. *. *. * I
typedef,

unsigned char byte;

..'

'

3-450

infel . '

AP-360

'/*** •• ************************************************ ************************************************1
/.
/"
'"
/*

, Funotion: Main
. '
Description: The following code shows examples of byte write and blook
erase algorithms that oan be modified to fit the specific application and
hardware design

* /-

*/
"/
' "/

/*********************** •• ***************************************************************.************/

main()

I

/.
/.
/*
/"
/*

/*

,

,

byte far "address;,
byte data, sta.tus ;
The following code gives an example of a possible byte write algorithm.
Note that Vpp does not need to be cyoled between byte writes when a string of byte
'writes oocurs. Ramp Vpp to 12V before the first byte write and leave at 12V until after
completion of the last byte write. Doing so minimizes Vpp ramp up-down delay and
maximizes byte write throughput
r
vppup() ;
'INSERT SOFTWARE DELAY FOR VPP RAMP IF REQUIRED"
pwddis () ;
address
OXxxxxxL;
data
='OXyy;
i f (wrltebgn(data,address) = '1)
"RECOVERY CODE-POWER NOT APPLIED (ID CHECK FAIL)'
else

./
"/
"/
"/
"/
./

=

,.

./

I
while (end (8:status) )
switoh (wrUechk(status»
I
.case 0:

break;

case 1:

/.

"RECOVERY. CODE-VPP LOW DETECT ERROR"
break;

"/

"RECOVERY CODE-BYTE WRITE ERROR"

"/

case 2:
/.

break;

statclr() ;
vppdown();

This "C" routine gives an example of combining lower-level functions (found in following pages) to complete a byte
write. Routines vppup( ) and pwddis( ) enable the 28FOO8SA for byte write. Function writebgn( ) issues a byte write
sequence to the deVice, end() detects byte write cO,mpletion via Status Register bit 7, and writechk() analyzes Status
Register bits 3-6 to determine byte write success. If a string of bytes is to be written at one time, Vpp ramp up and_
PWD disable need only be done before the first byte write attempt. Additionally, when writing multiple bytes at
once, examination of bits other than bit 7 (WSM Ready) need only occur after the last byte write has completed. The
Status Register retains any error bits until the Ciear Status Register command is written.
.

. , 3-451

int:et
/*
/*

/*

/*
/*
/*

/*

AP-360

The following code gives an example of a possible block erase algorithm.
Note that Vpp does not need to be cycled between block erases when a string of block
erases occurs. Ramp Vpp to 12V before the first block erase and leave at 12V until after
completion of the last block erase. Doing so minimizes Vpp ramp up-down delay and
maximizes block erase throughput
.
vppup() ;
"INSERT SOFTWARE DELAY FOR VPP RAMP IF REQUIRED"
pwddis() ;
address
= OXxxxxxL;
i f (erasbgn(address) == 1)
"RECOVERY CODE-POWER NOT APPLIED (ID CHECK FAIL)"

*/
*/

*/

*/
*/

*/

*/

else

I
while (end(&status) )
switch (eraschk(status))

I
case 0:
break;

case 1:

"RECOVERY CODE-VPP LOW DETECT ERROR"

/*

0/

break;
case 2:

"RECOVERY CODE-BLOCK'ERASE ERROR"

/*'

*/

break;

case 3:

"RECOVERY CODE-ERASE SEQUENCE ERROR"

/*

break;

*/

statclr() ;
vppdown() ;

This "C" routine gives an example of combining lower-level functions (found in following pages) to complete a block
erase. Routines vppup() and pwddis( ) enable the 28FOO8SA for block erase. Function erasbgn( ) issues a block erase
sequence to the device, end() detects block erase completion via Status Register bit 7, and eraschk() analyzes Status
Register bits 3-6 to determine block erase success. If a string of blocks is to be erased at one time, Vpp ramp up and
PWD disable need only be done before the first block erase attempt. Additionally, when erasing multiple blocks at
once, examination of bits other than bit..7 (WSM Ready) need only occur after the last block erase has completed.
The Status Register retains any error bits until the Clear Status Register command is written.

3-452

int'et ·

Ap·360

/*****************************************************************************************************/
f*
f*
f*
1*
1*
f*
f*

Function: Erasgbn
Description: Begins
Inputs:
blckaddr:
Outputs: None
Returns: 0 = Block
1 = Block
Device Read Mode on

erase of a block.
System address within the block to be erased
erase successfully initiated
erase not. initiated (ID check error)
Return: Status Register (ID if returns 1)

*f
*f
*f
*f
*f
*f
*f

/*****************************************************************************************************/
#define
#define

ERA SETUP
ERASCONF

OX20
OXOO

/* Erase Setup command
/* Erase Confirm command

*f
*f

int erasbgn(blckaddr)

f* blckaddr is an address within the block to be erased

byte far *blckaddr;

*f

byte mfgrid.deviceid;
if (idr.ad (&mfgrid .Il:deviceid) =;=1) 1* ID read error; device not powered up?
return (1);
.
'*blckaddr
ERASETUP;
f* Write Erase Setup command to block address
*blckaddr
ERASCONF;
f* Write Erase Confirm command to block address
return (0);

=
=

*f

*/

*f

Routine erasbgn( ) issues a block erase command sequence to a 28FOO8.SA. It is passed the deSired system address for
the block to be erased. After calling idread(). it writes the erase command sequence at the specified address. It
returns "0" if block erase initiation was successful. and "I" if the ID read fails (device not powered up or PWD not
disabled).

3-453

AP·360
"
,
/* "" III •• III III III III. III III. III III III ~ III III •.~ III. *III "" ~ if! ***"" *"" all III III III *"" "" "" ~ III III **. "" "" III "" III III "" "" 1/1 "" * * "" "" * **.. "" "" *"" III "" *"" ... "" **.• *. III "" 111.* lit "" *"" "" * "" .. * III III * "" "" .. I
'*
Function I Erassusp
,.
Desorlptlon: Suspends block erase to read from another block
,.,
/*
Inputs:
None
\
•J
,.
Outputs: None
•i
,.
Returns: 0= Block erase suspended
.,
,.
1 = Error ; Write State llachlne not busy' (block erase suspe'nd not posslble)
.,
,.'
Devloe Read Mode on Return: Status Reglster
'
.,

*'

I*·*********~*****·********************·**:************ ** •• ********************************************/

,t'

#deflne
#detlne

RDYMASK
WSMRDY

OXBO
OXBO

#derlne

SUSPMASK

OX40

#detlne

ESUSPYES

OX40

#detlne
#detlne

STATREAD
SYSADDR

OX70,
0

#det1ne

SUSPCMD

OXBO

,.
,.
,.
,.
,.,
,.
,.

'*

,.
'/*
,.
,.

Mask to ls01ate the WSM Status blt of the ,Status Reglster
Status Reglster value after masklng, slgnlfylng that
the WSM ls nO,longer busy
Mask to ls01ate the erase suspend status blt of the
,
Status Register
Status Register value after masking, Signifying 'that
block erase has been suspended
Read Status Register command
This ,constant oan be initialized t,o any address within
the memory map of the target 2BFOOBSA and is
alterable depending on the system architeoture
Erase Suspend command

.,.,
.,.,'
.,.,
.,.,
.,.,
.,.,

'

lnt,' erassus~ ()
byte. far 'stataddr;

'*
'*
'*

stataddr = (byte far *)SYSADDR; ,
'stataddr = SUSPCMD;
Wrlte Erase Suspend ooimnand to the devloe,
,. Wrlte Read Status'Reglster command •• neoessary ln case
'stataddr = STATREAD';
erase ls already oompleted
while
stataddr I: RDYMASiq != WSMRDY)
/*' Will remaln ln while loop until blt 7 of the Status
Register goes to 1', signlfylng that
,I'
the WSMis no longer busy
It «.~tlitaddr I: SUSPIlASK) = ESUSPYES)
return' (0) ;
/* Erase ls suspended •• return code ·0·
return (1);
,
"Erase has already completed;' suspend not posslble.
Error code 11111
/*

«.

'J

,. Polnter varlable used to wrlte commands to devloe

,.,
.,.,
.,
.,
'".,
.,
.,*'

Routine erassusp() issues the erase suspend command to a 28FOO8SA. It first makes' s~re the WSM is truly busy,
then issues the erase suspend command and polls ,Status Register bits 7 and 6 until they, indicate erase suspension. It
returns "0" if block erase was successful, and "1" if the ,WSM was not busy when suspend was attempted.

3·454

infel·

AP·360

/******** •••••••••••••••••••••••••••• III • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • _ • • • _ • • • • • • • • • • • • • • • • • • • • • • • • • • */
,.
,.
,.
,.
'* ,
'*
,.

• Function: Erasres
Desoription: Resumes block erase previously suspended
Inputs:
None
Outputs: None
Returns: 0 = Block erase resumed
1 = Error; Blook erase not suspended when tunotion called
Device Read lIode on Return: Status Register

/ •••••••• ** ••••••••••• t ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

#detine
#detine

RDYllASK
WSIIRDY

OXBO
OXBO

#define

SUSPIIASK

OX40

#detine

ESUSPYES

OX40

II'detine
II'detine

SrArREAD
SYSADDR

OX70
0

#define

RESUMCIID

OXDO

,.,.,.
,.,.
,.

lIask to isolate the WSII Status bit of the Status Register
Status Register value, after masking, signifying that the
WSM is no longer busy
Mask to isolate the erase suspend status bit of the
Status Register
Status Register value after masking, signifying that
block erase has been suspended
,. Read Status Register command
'" rhis constant can be initialized to any address within
the memory map of the target 2BFOOBSA and is
alterable dependin'g, oil the system arohi taoture
Erase Resume oommand

.,
"'
.,
"/
.,
"'
.,

*'
*'
*'
*'
*'

.,
.,
*'
"'

,"
,*,"

.,
.,
"'

,. Pointer variable used to write ao.....nds to device

.,

,.

"'

int erasres()
byte tar *stataddr;
stataddr
'stataddr

= (byte far *) SYSADDR; ,

= SrArREAD;

if' ((*stataddr I: SUSPMASK)

'
,. Write Read Status Register command to 2BFOOBSA

return, (1) ;
,. Block erase noi 'suspended. Error code '1'
*stataddr
RESUIICIID;
'* Write Erase Resume command to the device
.hile (( *stataddr I: SUSPMASK)
ESUSPYES)
'" Will remain in while loop until bit 6 of the Status
Register goes to 0, signifying block
,.
erase resumption
while (( *stataddr I: RDYIlASK)
WSIIRDY)
,. Will remain in ..h~le loop until bit 7 ot the Status
,.
Register goes to 0, signifying that the WSII is
,.
once again busy
return (0);

=

"'

1= ESUSPYES)

=

'*

=

"'
"'

*'
*'

"'
"/

*i

"'

,I

Routine erasres( ) issues the erase resume command to Ii 28FOO8SA. It first makes sure the WSM is truly suspended,
then issues the erase resume command and polls Status Register bits 7 and 6 until the indicate WSM resumption. It
returns "0" if block erase resume was successful, and "I" if the WSM was not suspended when resumption was
attempted. '

3-455

infel·

AP-360

I···*·····*·····*······*·····*···*···········~····*·~***.* •... ~***** •• *•• *.*.*** ••••• *•••* ••*•• *** ••••••• ,
/*

/*

/*
/*
/*
/*

Function: End
Desoription: Cheoks to see if the WSM is'busy (is byie write/block erase oompleted?)
Inputs:
lIone
Outputs:
statdata: Status Register data read from devioe
Returns:
0 Byte Write/Blook Erase completed
1 = Byte.Write/Block Erase still in progress
Device Read Mode on Return: Status Register

=

*/
*/
*/
*/
*/

*/
*/
, ••••••••••••••• ** ...................... ** •• **.** •••••••••••••• * •••••••••••••••••••••••• ** •••••••••••••••• III I
"de.fine
RDYMASK
OX80
/* Mask to isolate the WSM Status bit of the Status
*/
"de tine
WSMRDY
. OX80
/* Register value after masking, signifying that the
.*/
/*
WSM is no longer busy
.
*/
"define
STUREAD
OX70
/* Read Status Register command
*/
"de tine
SYSADDR
.0'
/* This constant oan be initialized to any address wi thin./
/.
the memory map of the target 28F008SA and is
"/
/*
alterable depending on the system arohitecture ./

/*

.int end (statdata)
byte *stat4.ata;

byte far .stataddr;

/" Allows' Status Register data to be passed back to the
,.
main program for further analysis

"/
*/

/" Pointer variable used to write oommands

0/

~o

device

stataddr
= (byte far O)SYSADDR;
/. Write Read.Status Register aommand to 28F008SA
./
*stataddr
STATREAD;
it «(*statdata °stataddr) "RDYMASK) 1= WSMRDY)
return (1);
.,. Byte write/blook erasure still in progress ••• oode ',1' 0/
return (0);
/" Byte write/block erase attempt completed ••• oode '0'
./

=

=

Routine end( ) detects completion of byte write or block erase operations of a 28FOO8SA. It passes back the Status
Register data it reads from the device. It also returns "0" if Status Register bit 7 indicates WSM "Ready", and "I" if
indication is that the WSM is still "Busy".
.

3-456

intel .

AP-360

i*. *' .. *' *' *' *' *' "' .. *' *' .... *' *' *' .. '" *' *' *' *' '" *' *' ....... *' *' ..
,.
'"
,.
,.
'"
'"

*.'. *' *"" ..

III III

** .... "" ..... *.... *' .... *' *' .... III III .. *' "" "" .. *.. 111

*'. " . *'

III "" "".

*' "" *' .. *' * ..! .. *' .. *' *' .. *' *'.

'"
'"
,.
'"
'"

Function: Erasohk
'
Description: Completes tull Status Register check tor blook erase (proper oommand
sequenoe, Vpp low detect, blook erase suooess). This routine assumes that blook
erase oompletion has already been oheoked in tunction end(), and theretore does
not check the WSM Status bit ot the Status Register
Inputs:
statdata: Status Register data read in tunotion end
Outputs: lione
Returns: 0 Blook erase oompleted suocesstully
1 Error; Vpp low, deteot
2 Error; Blook erase error
3 Error; Improper oommand sequenoing
Device Read Mode on Return: Same as when entered

#detine

ESEQllASK

OX30

#detine

ESEQFAIL

OX30

#detine

EERRMSK

OX20

#detine

ERASERR

OX20

#detine
#define

VLOWMASK
VPPLOW

OXOS
OXOS

'*

=
=
=
=

/ .......................................... ** ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

,0 Mask
,0

to isolate the erase and byte write status bits ot
the Status Register
Status Register value atter masking it block erase
oommand sequenoe error has been deteoted
Mask to isolate the erase status bit ot the
Status Register
Status Register value atter masking it block erase error
has been deteoted
Mask to isolate the Vpp status bit of the Status Register
Status Register value atter masking it, Vpp low
has been deteoted
1*

,","
,","
,.,.,"
,*

int eraschk(statdata)

,.
'"

byte statdata;

it «statdata I: VLOWMASK)
, return (1);
it «statdata I: EERRMSK)
return (2);
,
it «statdata I: ESEQllASK)
return (3);
return (0);

=

Status Register data that has been already read trom the
2SFOOSSA in tunotion end ()

VPPLOW)
,. Vpp low deteot error, return code "I"

= ERASERR)
=

,. Block erase error deteot, return oode "2"
ESEQFAIL)
'" Blook erase command sequenoe error, return code "3"
,. Blook erase suooess, return oode "0"
'

*'

.,
"'
"'
"'
"'
"'
•i

*'
*'
*'
"'"'
"'"'0,
.,.,*'
"'*,
"'
"'
"'
"'

*'*'
"'
"'
"'
.,

Routine eraschk( ) takes the Status Register data read in end( ) and further analyzes it. It returns "0" if block erase
was successful, "I" ifVpp low error was detected, "2" if block erase error was reported and "3" if an erase command
sequence error was found (erase setup followed by a command other than erase confirm). This is useful after a block
or string of blocks has been erased, to check for successful completion.

3·457

infel·

AP-360

,*,.. *' .....* Function:
** .......................... ** .. * *........
Wri tebgn
III""" 101 ..

III .. """"""""

** *.... * ... * 1/1 ...... *,*""" *...... *...... ~ ............ *...... III .... ** "' .. ** ........ */

*'0,
*'

'"

,~

Description,: Begins byte write sequence
Inputs:
wdata: Data io be written into the device
waddr: farget address to be written

'*
'*

,.

/*

o-wtputs:

0 Byte write successfully initiated
1 :: Byte write not ini.tiated (ID check error)
Device Read Moile on'Return: Status Register (ID i t returns 1)

/* ~ III .. *** III ............................ ~. ,*""" ~ ...... *.... ** ...... *.... '" *.. ,. ...... III ~ .. *................. *.. ** ..

#detine

SEfUPCIID

OX40

int write,bgn(wdata,waddr)
byte wdata;
byte tar °waddr;
(

.. I
.,
.,

=

~eturns:

1*
'"

.,

l~Qne'

*.

*0,

*' .. III ...... **. III *..................... I

cOlllJllSnd

.,

Data to be written into the 28F008SA
,. waddr is the destination aildress for the data
,.
to b~ written

.,.,"'

,. Byte' Wri te

Set~p

III ..........

'*

,

byte mfgrid,deviceid;

'*

if (idread (imfgrid,Adeviceid) ==1)
Device ID read error ••• powered up?
return (1);
'waddr
= SEfUPCIID;
Write Byte'Write Setup command and destination address
'waddr
wata;
Write byte wrtte data and destination address
return (Il) ';

''**

=

"'
.,
.,

*'

/* *....... *' .......... ~ III .................... ~ • • '" '" '" "'" III .. "'" "' ................ ** ....... ** .. "' ......................... *..... III. **......................... **., .......
,.
Function: Writechk
'
.,
,.
Description: Compietes full Status Register check for byte ,write (Vpp low detect, byte
.j
write'sucoess). fhi.s routine assumes that byte write oompletion has already'
./
,.
be~n ohecked in,funotion end() and therefore does not check the WSK Status
.,
,.
bit ot the Status Register
.,
,.
Inputs:
statdata: Status Register data read in funotion end().,
,.
Outputs: N o n e '
.,
,.
Retj!rns: 0 Byte wri to oomploted suooessfully
./
,.
1 :. Erl'or; Vpp low detect
.,
/.
2 Error; Byte write error
.,
Device Read Mode on Return: Status Register
,
I~.*""""""" "' ...... III ................., .................. *~ .................. "' .................... ~ ...... "' .... *•• *...........'..... *•• * * *** * * *••• *•• *•• *. * /

'*

=

=

'*

#define

WEl!Rl!SK

OXlO

#define

WRIrERR

OX10

#iIetine

VLOWIIASK OX08

""etine

VPPLOW

OX08

*'

,.
,.
,.
,.
/*
,.
,.
,.

Mask to isolate the byte write error'bit of the
" Status Register '
Stat.us Register value after masking it byte write error
has been detected'
Mask to isolate the Vpp status bit of the
Status Register
Status Register value after masking i t Vpp low
has been detected

.,
.,

,*'

*'
*'

.,
.,
.,

int writeohk(statdata)
byte statdata;

,'*

1* Status Register data that has been already read from the
28F008SA in function end ()

'*

i t « statdata A VLOWMASK) == VPPLOW)

return (1);
Vpp low detect error, return code "1"
it « statdata A WElUU!SK) == WRITERR)
return (2);
,.'BYte w~ite error detect, return code "2"
return (0);
'/* Byte/string write sucaess, return code ·0·

*'

./

.,
.,*'

Routine writebgn( ) issues a byte write command sequence to a 28FOO8SA. It is passed the desired system addr~ for
the byte to be written, as well as the data to be written there. After calling idread( ), it writes the byte write Command
sequence ilt the specified address. It returns "0" if byte write initiation was successful, and "I" if the ID read fails
'
'
(device not powered up or PWD not 4isabled).
Routine writechk( ) takes the Status Register data read in end( ) and further analyzes it. It returns "0" if byte write
was successful, "1" if Vpp low error was detected, and "2" if byte write error was reported. This is useful after a byte
or string of bytes has been written, to check for successful completion.'
,

3-458

inteL

Ap·360

/"'************************.********************"'****** *********'*~*************************************I

/*
/*
1*
/*

Function: Idread
Description: Reads the manufacturer and device IDs from the target 2BFOOBSA
Inputs:
None
Outputs: mfgrid: Returned manufacturer ID
deviceid: Returned device ID
Returns: 0 = ID read correct
1 = Wrong or no ID
Device Read Mode on Return: inteligent Identifier

"
"
"
*/

/*
"
1*
"
1*
"
1*
"
" /* *** ** ** * * >II *' * * **** * '" * '" **'" * '" '" *"'*'" * ** .. **** *** ** '" *'" "'''' '" '" '" "'''' "'**,"''''''' * "'''' '" '" '" * "'*'" '" '" * '" * * "'''' * . . '" '" '" '" * *"'*'" *"'''''''*''' *"'''' '" '" /
#define

MFGRADDR

0

"

/*
on the system architecture
"
1* Address "1' for the target 28F008SA ••• alterable depending *'

#define

DEVICADD

1

#define
#define
#define
#define

IDRDCOMM
INTELID
DVCID
DVCID2

OX90
OXB9
OXOA2
OXOAl

"

.

Address "0' for the target 2BFOOBSA ••• alterable depending "
on the system architecture

1* Inteligent Identifier command
"
"

Manufacturer ID for Intel devices
Device IDs for 28FOOBSA

*'*'
*'*'

int idread(mfgrid,deviceid)
byte *mfgrid;
byte *deviceid;

/* The manufactUrer ID read by this function, to be
transferred back to the calling program
The device ID read by this function, to be transferred
back to the calling function
/*

/*
"

byte far 'tempaddr;
/* Pointer address variable used to read IDs
tempaddr
(byte far *)MFGRADDR;
'tempaddr = IDRDCOMM:
" Write inteligent Identifier command to an address within
1*
the 28F008SA memory map (in this case 00 hex)
'mfgrid
*tempaddr:
/* Read mfgr ID, tempaddr still points at address '0'
tempaddr
(byte far *)DEVICADD; '* Point to address '1' for the device specific 10
. *deviceid = *tempaddr:
/* Read device 10.
if «'mfgrid != INTELID)
«*deviceid!= DVCID) &!o (*deviceid != DVCID2)))
return (1):
/* 10 read error: device powered up?
return (0);

*'
*'*'

"
"

*'
*'
*'
*'
*'
*'

Routine idread() issues the Intelligent Identifier command to a 28FOO8SA. It passes back the manufacturer and
device IDs it reads. In addition, it returns "0" if the IDs read matched those expected for the 28FOO8SA or
28FOO8SA-L, and "1" if either the manufacturer or device JDs did not match.

3-459

intel·

AP-360

'*..

*.

III * * .... *_.... III ...... *. . III *III ••.• III III III * III III III III lie III ... III III III III III * * III 11= *.* lie;' ... III *.. III" '" III" III 101 .". *III III '" *
* .... II: ** * ... III ...... ; ............ 101 11= .... '• • • • III ... *III III ...... ", II< III ... J
/"
Funct,ion: !itatrd
./
/*
Description: Returns contents 01' the target 28F008SA Status Register
*/
/*
~ Inputs:
None'
"
.'
*/
/*
Outputs: statdata: Returned Status Register data
*/
1*,
Returns; Nothing
*/
/*
Device Read Mode on Return: Status Register
"
*/
/* ...... III III III III III ...... ., *............ *. . *.:*"'''''''''' *...... III ... "'" III ... III III III *• ., ...... ~ III . . III ......... ",,,, III .................. III'" I I I I ... "' ••• *' ...... *. . III"''''''''''''''''''''''''''''''''''''''' 1/1 $:",,,, *........... I I *III
#detine
SnrREAD OX70
'* Read Status, Register command
"/
#detine
SYSADDR
0
/" rhis constant can be ini tial'ized to any address wi thin
"/
- '
/*
the memory map 01' the target 28F008SA an~ is
*/
/*
alterable d~pending on the syst!m'arohitecture
*/,

*'

*.

int statrd(statdata)
byte *statdata;

/*, Allows Status Register data to be passed back to ',the
, /*
calling program tor turther analysis '

byte tar *stataddr;
stataddr
'stataddr
*statdata
return;

/* Pointer variable used to write commands to device

= (byte tar
= SrArREAD;

=

*)SYSADDR;
/* Write Read Status Register command to 28F908SA
*stataddr;,

*/

*/

;,/,
*/

/ •• *** ••• ***.** •••••••• ** •• ****.*** ......... **.**.***** ********·*·*·*·*·*******··** .. **·*~****·*··*·····I

/"
/*
/*
/*
/*
/*

'*

,*/
./
*/
./
*/
,
*'
III ............... III ................ III III *,* *. . III ... *. . III ...... III III III III"'''' III ... " . III ...... "'''' III III ~ ... *............... III ... '" III ... *........... '" "' ....... III III '" III III III ... III ...... * !II *. * III III III III III III • • "''''''' .111. III ... III"'''' I

#detine
#detine

Function: Statcl'"
"
. '
Description: Clears the 28F008SA Status'Register
Inputs:
None
Outputs: None
Returns: Nothing
Device Read Mode on Return: Array
SrArCLER
SYSADDR

OX50
0

/. Clear Status Register command
/" rh1s constant can be initialized to any address~within
/.
'the memory map 01' the target'28F008SA and is
/*
__ alterable depending on the system architecture

./
./
./
"/

/* Pointer variable used to wri'te commands to device

"/

int statclr ()
byte tar "stataddr;
stataddr
'stataddr
return;

= (byte

=

tar *)SYSADDR;
SrArCLER;,
/. Write Clear Status Register'command to 28F008SA

,*/

Routine statrd( ) reads a 28FOO8SA Status Register. It issues the Read Status Register command and passes back the
'
data it obtains.
Routinestatclr() issues the Clear Status Register command to ~ 28FOO8SA. This routine is required after analyzing
Status Register contents in routines like eraschk( ) and writechk(). The 28FOO8SA Status Register retains state of
, bits 3-6 until they are cleared by the' Clear Status Register command.
'

AP-360

,*************** ••• *********************************** **********="'*************************************1
/0

/"
/"
1*
/.
1*
/.
/"

Function: Rdmode
Descriptioh: Puts the target 28F008SA in Read Array Mode. This function might be used. for
example. to prepare the system for return to code exeoution out of the Flash
memory after byte 'write or block erase algorithms have been exeouted off-chip
Inputs:
None.
.
Outputs: None
Returns: Nothing
Device Read Mode an Return: Array

"/
"/
"/
./
"/
"/
"/
*/

#define
#define

RDARRAY
Sy'SADDR

/* Read Array command
/* This constant can be initialized to any address within
/0the memory map of the target 28F008SA and 1s
/"
alterable depending on the system arohiteoture

*/
"/
"/

/" Pointer variable used to write commands to the devioe

"/

I********··**********::t'***~********·*********·********* ************************************************'
OXFF'
0

./

int rdmode ( )
byte far "tempaddr;
tempaddr
*tempaddr
return;

= (byte far
=RDARRAY;

*) SYSAllDR;
/" Write Read Array command to 28F008SA

*/

,**** •• **********************.**.******************************************************:IIC.****************/

/.
/*
/*
/*
/*
/.
/.

Function: Rdbyte
Description: Reads a byte of data from a specified address and returns it to the
calling program
Inputs:
raddr: Target address to be read from
Outputs: rdata: Data at the specified address
Returns: N o t h i n g '
Device Read Mode on Return: Array

*/
./
*/
./
./
./
./

J***************************************************** *****************~********'9I*********************1

#define

RDARRAY

OXFF

int rdbyte (rdata,raddr)
byte ordata;
byte far *raddr;
*raddr
*rdata'
return;

=RDARRAY;
= .raddr;

/* Read array command

"/

/" Returns data read from the device at specified address
/* Raddr is the target address to be read from

*/

/*. Write read array command to an address within the
/.
28F008SA (in this case the target address)
/. Read from the specified address and.store·

./

*/

./
./

Routine rdmode( ) .simply puts a 28FOO8SA in Read Array mode. This is useful after byte write and' block erase
operations, to return the 28FOO8SA to its "normal" mode of operation. After block erase or byte write, the
28FOO8SA will continu~ to output Status Register data until the Read Array command IS .issued to it, for example.
Routine rdbyte( ) not only pJits the 28FOO8SA i~ Read Array mode, it also read; a byte of data. It is passed the
desired system byte .address, and passes back the data at' that address.

3-461

AP~360
,

,

/* .......... ** .. III" ~ .. *...'... *' 101"""'' ' *' .. * +: *' '* *' . . *' ....... *...... *' *' .. lie ......... """"""'''''' ~* .. *' ...... *' .. *' .... **' "' . . *' ...... *' .. *' . . *' *.'" III" *. . *' . . *' *' .. *............. *.. ., *..... I

''**,

, '*
'*
'*

''**
''**
',0*
'*
'*

*'*'
*'*'
0,
*'

Function: Vppup
,
Description: Ramps tile Vpp supply 'to the target 28F008SA to enable' byte write or block
erase. This routine can be tailored to the individual system architecture. For
purposes, of this example, I assumed that 'a system Control Register existed at
'system address 20000 he", dth the 'f,ollowins definitions:
'

'*

Bit 7: Vpph

''

Control~

Bit 6: FWD Control:

Bi ts 5-0: Undefined

1
0
1
0

=Enabled
=
=Disabled,
PowerDown Enabled
= PowerDown

*'
*'
*'
*'
*'

Disabled

*'0,
*'*'

Inputs:
None
Outputs: None
*'
/*
Returns: Nothing
/*
Device Read Mode' on Return: As existed b'efore entering the function. Part is now ready for
program or erase
*'
.I***********.**************************~************** ************************************************/
'*

#define
#define

VPPHIGH
SYSCADDR

.*'*'

'* Bit 7 = 1, Vp~ elevated to Vpph
Assumed system Control Register Address

'*

OX80
OX20000

1nt vppup()

contaddr
*contaddr

=' (byte far

= *contaddr

return;
.

*'0,
*'*'

'* Pointer variable used to write da~a 'to the system
'*
-Control Rsgister

byte far *contaddr';

'

*)

I

SYSCADDR ;
VPPHIGH;

'*

.

'*

llead current Con~rol Register, data, 'OR' with
constant to, 'ramp Vpp
.

'

,

.

.

,(

,;

'"',

/* ......... *** *' *...... *............ ole ......... *.*'" *........ * *' ....'.............. *If!"'" *' *.................. *III"''''''''''''''''''''''''''' * ~ ........ 11< ....... "'''''''''''''''''''''' **. . *...... *..................... ~.*"'''' *........ I
'*
'*

,'''***
''**,

',0*

1*

*'*'
*'*'
*'*'
0,

Funotion: Vppdown
Desoription: Ramps down the Vpp supply to the'target'28FOOBSA to disable, byte write,blook
erase. See above for a description of the assumed system Control Register.
*J' ,
Inputs:
None
"
' * '
Outputs: None
Returns: Nothing
Device Read ,Made on Return: As existed before entering the funotion. Part now has hiSh Vpp *'
disabled. If 'byte write or block erase was 'in progress when this funotion was
oalled, it will complete unsuccessfully,with Vpp law error in the
Status Register.
'

/* *********** ••• *••••• *** 11:****** ** ** **** ***.*~* ****** ** *.* *** **. . **"'**** *. . ** *** **~ ****** ******* ******** * *I

#define
#define

V~PDWN

SYSCADDR

OX7F
OX20000

'*

,. Bit 7 = 0, Vpp lowered, to Vppl
Assumed system Control, Regi'ster Address

tnt vppdown ()
byte

fa~ 'contad~r;

'*

,.I'
contaddr
*ooritaddr
return;

=:

Pointer variable used t,~ .wri te ,data to
Contrpl Register

.,
.,.,*'

~he sys~em

(byte far *)SYSCADDR;
'contaddr a: VPPDWN; /* Read current CO!;ltrol Register data, "AND" with
constant to lower Vpp

',*

Functions vppup() and vppdown() give eXimlples of how to control via software the hardware that enables or
disables 12V Vpp to a 28FOO8SA. The actual hardware implementation ch.osen will drive any modification of these
~~

,

Ap·360

*'
*'*'
*'*'
*'*'
*'
"',

/* III * III III III III III III 101 III III III. III **. III III III III III III III *' III III III III III III III III III. III III III III III III 111.,.101. * III III III ~ III III III .. III III III III III III III III" *III III III III. III III III *III III *III III III III III III III ~ III • • III III III" III III III III III" III
Function: Pwden
'
'*'
Description: Toggles the 28F008SA ,PWD pin low to put the device in Deep PowerDown mode.
See above tor a description ot the assumed system Control Register.'
'*
Inputs:
None
'
*'
1*
Outputs: None
"'
1*
Returns: Nothing
*'
Device Read Mode on Return: The part is powered down. It byte write or block erase was in
,.
progress when this tunction was aalled, it will abort with resulting partially
'"
written or erased data. Recovery in the torm ot repeat ot byte write or block
,.
erase will be required onae the part transitions aut ,at powerdowo, to
'*
initialize data to a known state.
'
*'

''/***

'

'*

~***

•••••••••••••••••••••••••.•••••• III • • • • • • • • • • • • • • • • • • • • • • • • • • **~ III **•••••• III III *•••••••••••••••• *•• III III • • *

#detine
#detine

PWD
SYSCADDR

OX40
OX20000

=

'*

'* Bit 6
1, ,PWD enabled
Assumed system Control Register Address

int pwden()
byte tar *contaddr;
contaddr
*oontaddr

'*

'* Pointer .variable used to write data to the system
Control Register

(byte tar *) SYSCADDR ;
I PWD; ,. Read current Control Register data, 'OR' with constant
,.
to enable Deep PowerDowo

= *contaddr

return;

*'
"'*'

/* * III III III III III ~ III III. III III III *III III III III III III III III III III III III III III. ~ III" III *' III III III III III III '" III III III III III III III III III III III *III *' III III III III. III III III III III III III III III III III III III III III'" III III "' ... '" III III *. III "' .. III III'" III III III III *. III III *I
Function: Pwdd1S
.,
.Desoription: Toggles the 28F008SA ,PWD pin high to transition the part aut ot Deep
*'
'"
PowerDown. See above tar a description at the assumed system Control Register.,
"'
Inputs:
None
'*
Outputs: None
Returns: Nothing
'*
Device Read Made an. Return: Read Array made. Law voltage is removed tram the ,PWD pin.
*'
,.
28F008SA output pins w111 output valid data time tPH~V atter the ,PWD pin
'*
transitions high' (reterence the datasheet AC Read Characteristics) assuming
"'
valid states on all ather control and power supply pins.

'*
'*
'*
'*
)~

*'*'
*'

/* _. III III III III III. III III III • • • III • • • III • • III" III'" III • • III III III" III III'" III III III III III III

#define
#define

PWDOFF
SYSCADDR

OXBF
OX20000

'*

**
III

III III • • III

* III III III III III III • • III III III 111" III III III III III III III III III III III * III III III.

*.

III III III III III III., III

* III III III *.•

Bit 6 = 0, ,PWD disabled
'* Assumed system Control Regist.er Address

lnt pwddi s ()

,I
byte tar
aontaddr
*contaddr

*~ontaddr;

=

=

'*

'* Painter variable used to write data to the system
Control Register

(byte far *) SYSCADDR;
*aontaddr • PWDOFF; '* Read current Control Register data, 'AND' .ith
,.
'constant to disable Deep PowerDoWD

return;

*'
*'
***
"'*'

* *"1.

."'"
.,.,

Functions pwden( ) and pwddis( ) give examples of how to Control via software the hardware that enables or disables
a 28FOO8SA PWD input. The actual hardware implementation chosen will drive any modification of these routines.

3·463

infel·

Ap·360

ADDITIONAL INFORMATION

';~.

. 28F008SA Datasheet
28F008SA-L Datasheet
, AP-359 "28F008SA Hardware Interfacing"
AP-364 "28F008SA Automation and Algorithms"
ER-27
"The Intel 28F008SA Flash Memory"
"ETOXTM-III Flash Memory Technology"
ER-28

Order Number'
290429
290435
292094
292099
294011
294012

REVISION HISTORY
Number

Description

002

Revised Erase Suspend Algorithm in "C" Drivers.

3-464

. intel·

APPLICATION
NOTE

AP-363

September 1992 .

.Extended Flash Bios Design
For Portable Computers

SALIMFEDEL
SENIOR APPLICATIONS ENGINEER

Order Number: 292098-002
3-465

EXTENDED FJ,.ASH BIOS DESIG"
,FOR PORTAB.LE COMPUTERS
CONTENTS

PAGE

CONTENTS

PAGE

1.0INTFIODUCTION ................... 3·467

5~O SOFTWARE DESIGN
CONSIDERATIONS ........... , ..... 3~478

2.0 PC BIOS TODAY AT THE
128 KBYTE CODE SIZE LIMIT ...... 3·467

'?1 16KBytes Recovery Code ....... 3~480
5.2 2~F200BX Reprogramming ...... 3-480
5.3 pqwer ~anagement .... ; ........ 3·480

3.0 WHY BIOS CODE WILL GROW
8EYOND 128 KBYTES .... : ......... 3·467
3.1 Advanc~d Power Management .. 3·469
'3.2 Optimize New Portable
Applications ...................... 3·469
3.3 Putting Microsoft* MS· DOS 5.0
Oper~ting System ROM Version into
the BIOS C~ip .; .... : .... ,.: .. : .... ,3·469
3.4 Relocated Resident VGA Code:
VIDEO BIOS ...................... 3-469
4.0 HARDWARE DESIGN FOR A
25~ KBYTE BIOS; ..... ; ." ......... 3·470
4.1 Intel 28F200BX/Q02BX Boot Block
Flas~ M",mory Family .......... ~ .. 3·470
4.2 InteI38"SLTM, Microprocessor
Superset Platform OvEirview ....... 3-471
4.3 Programming the Intel386,SLTM '
Regi~terS ........ ; .... : ;:.......... 3-476
4.4 The ISA Sliding Window ......... 3-477
4;5 The 28F200BX·T/2~FQ02BX.T in
the 1 MByte DOS Memory:Map . ~ .. 3·478

,6.0 DESIGNING

A 3.3V'SYSTEM

...... 3·4131

'6.1 LoltY Voltage Chips ............... 3·481
6.2 pqwer Savings and Improved
Battery Life ..... ; ................. 3·481
7.0 CONCLUSiONS .................... 3·481
7.1 Benefits of Extended Flash
,BIO,S ':: ............, ...... '; ........ 3·481
REFER~NCES ...... '................... 3·462

APPENDIX ~ ...•...................... 3·483
ApPENDIX B .......................... 3-484
~PPENDIX ~

............•......... , ... 3-489

APPENDIX D .......................... 3-493

°MicrollOft isa regl"terad trademark of Microsoft Corporation.

3-466

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AP-363
I

1.0

INTRODUCTION

PC BIOS has been migrating to Flash-based designs
with the introduction of highly optimized Flash memory architectures. The first phase of this shift in 'paradigm was from ROM/EPROM-based BIOS to Bulk
Erase Flash memory-based BIOS to provide for in-system updatable BIOS and hence an easy update capability when BIOS changes are required.
The second. phase improved the basic flash design to
migrate towards boot block flash memory architecture
with the Intel 28FOOIBX Flash memory. This improvement enabled the implementation of additional features
and provided a true design capability for portllble PC
BIOS.
The third phase of this paradigm shift now starting to
evolve, deals with the need to grow beyond the traditional BIOS space limit of 128 KBytes imposed by the
original PC architecture to accommodate the advanced
features of today's portable and desktop systems.
This application note describes in detail this third phase
in BIOS hardware and software implementation. Specifically it will investigate why BIOS needs to grow beyond the 128 KByte code size. Then, a design example
using the Intel 28F200BX Boot Block Flash memory in
an InteJ386SLTM-based portable system will be explained in terms of both harClware and software viewpoints. Finally, low voltage PC BIOS designs incorporating 3.3V components are described.

2.0

PC BIOS TODAY AT THE
128 KBYTE CODE SIZE LIMIT

The Basic Input/Output System (BIOS) code is the
lowest system level software which manages the interaction between all hardware components (CPU, ChipSets and I/O) with all software modules (Operating
Systems and Applications Code). BIOS manages many
functions in a PC, such as Power-On Self Test (POST),
input vector creation, I/O services and system initialization. Therefore BIOS is the essential interface layer
for full system functionality and compatibility.
The original PC architecture, developed in 1981, put
restrictions on the size and mapping of the BIOS code
which was then a very simple piece of software (on the
order of 32 KBytes for the original BIOS code). It was
located at the top of the PC's (8088) memory map
which at the time was a maximum of 1 MByte. .

Then in 1984, the PC AT (80286) BIOS was expanded
another 32 KBytes for a total of 64 KBytes. Subsequently, towards the late 1980s, more elaborate BIOS
set-up utilities started to be an integral part of the BIOS
code. In addition, personal computer manufacturers designed custom features into their BIOS code to offer
more system flexibility. This increase in code complexity expanded the AT BIOS code another 64 KBytes (for
a total of 128 KBytes) to occupy the total BIOS reserved space in the I MByte memory map.
.In the DOS memory map, BIOS is mapped down from
the top of the 1 MByteaddress space (FOOOOH to
FFFFFH). Additional BIOS code space is available for
future enhancements from EOOOOH to EFFFFH. The
next 256 KBytes in the DOS memory map are reserved
for adapter space to accommodate add-in boards (for
enhanced graphics cards for instance). Finally the remaining 640 KBytes are reserved for the user to load .
his/her applications for execution. See Figure 1 for a
graphical description.

3.0

WHY BIOS CODE WILL GROW
BEYOND 128 KBYTES

As advances in computer design affect both desktop
systemS (with the addition of EISA and SCSI capabilities) and portable systems (with the addition of advanced power management capability and I/O cards),
the need for larger amounts of non-volatile memory
space becomes evident.
A Notebook or a Palmtop computer design, for instance, may put the operating system, the system management code, set-up or utility programs into the nonvolatile memory area to conserve precious RAM space
for applications.
Additionally, Video BIOS can also be mapped into the
Flash BIOS area as in the case of the Inte1386SL Microprocessor Superset.
Therefore, to implement advanced capabilities and provide new.features (as described above) into powerful
mobile computers, the 128 KByte BIOS code size limit
had to be removed as it shall be explored in the next
section.
The BIOS of today and the future must adapt to the
new requirements of portable PC designs and take advantage of the new capabilities of low power PC chipsets and I/O devices to achieve the highest performance
and longest battery life at the lowest system cost.

3-467

infel .

AP-363

FFFFFH
(1024K)

1 MBYTE DOS MAP
BIOS CODE

.1

EFFFFH
(960K)
EOOOOH
DFFFFH

(896K)

.

ADDITIONAL BIOS SPACE

,,
ADAPTER SPACE
AND GRAPHIC SPACE

,,

,,

,,

AOOOOH

,,

INTEL 28F001BX-T
BOOT BLOCK FLASH
MEMORY MAP

8K

BOOT RECOVERY CODE

4K

PARAMETER BLOCK

4K
',112 K.
"

,,

, PAR~METER

BLOCK

MAIN BIOS CODE.

(640K)
USER AREA
I

I

OOOOOH

292098-1

Figure 1. 128 KByte BIOS Code Segmentation in 1 MByte DOS Memory Map',
,I

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.

.

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3.1

AP-363

Advanced Power Management

High integration CPUs and chip-sets such as the
Inte1386SL Microprocessor SuperSet allow for the design of light, small form factor portable computers with
long battery life.
BIOS is the ideal place for implementing the new power
management techniques available with the Inte1386SL
Microprocessor Superset. BIOS software vendors have
implemented APM code for the latest generation of
Notebook PCs.
This added level of functionality imposed on the BIOS
code increases the need for larger code space beyond
the traditional 128 KByte BIOS implementations seen
in today's portable systems.
APM code typically requires an additional 32 KByte of
code space beyond the basic 64. KByte standard BIOS.
Therefore, with the addition of APM, BIOS code grows
to 96 KBytes.

3.2 Optimize New Portable
Applications

and character recognition .interface code. These new
features require the implementation of additional BIOS
code (may be 16 KBytes to 32 KBytes).
To take full advantage of Desktop system capabilities
and performance while still having a portable computer
to take on the road, docking station designs were conceived. This added level of complexity for the portable
computer increases the code required in a basic system
BIOS.

3.3 Putting Microsoft MS-DOS 5.0
Operating System ROM Version
into the BIOS Chip
Additionally, MS-DOS 5, ROM version is now becoming a standard in virtually all diskless sub-notebook,
notebook and pen PC implementations. Many factors
contribute to this approach. Chief among them is the
reduced disk access and the resulting longer battery
life. Another factor is the instant boot capability which
is essential in certain applications.
Today's MS-DOS 5, ROM version occupies 64. KBytes
of code space as specified from the Microsoft Product
Descriptidn.

With the implementation of I/O card capabilities for
non-volatile file storage (with flash memory "cards) and
the ability to communicate over a telephone line (with
modem cards), mobile computers have truly become
powerful tools on the road.
.
The establishment of a common PC card standard for
full system compatibility is described in the PCMCIA
Standard release 2.0 (Personal Computer. Memory
Card International Association). Intel has developed a
similar 'set of specifications fully compatible with the
PCMCIA release 2.0 standard called the Exchangeable
Card Architecture (ExCA). In order to implement
ExCA capability in a portable computer, additional
BIOS code called So~ket Services is required to manage
the system I/O card functionality. To implement the
ExCA specifications, socket services needs an additional 16 KByte of code space.
Furthermore, in the pen-based PC applications, there
are even greater BIOS requirements to design-in unique
features such as: pen extensions, touchscreen capability

3.4 Relocated Resident VGA Code:
VIDEO BIOS
As described above'in section 3.0, video BIOS can also
be mapped into the system Flash BIOS memory allowing the entire system non-volatile storage requirements
to be satisfied with one Flash device. Resident VGA
BIOS code takes approximately another 32 KBytes of
memory space.
In summary, adding all the above code siZe requirements, the resulting BIOS storage area increases from
the initial 128 KByte requirement to somewhere between 208 KBytes (without pen extensions) to 240
KBytes (including a pen input capability).
There are already portable designs today which have
filled a 256 KByte code space to accommodate some of
the above mentioned needs.

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4.0

4.1

AP-363

• Two, 8 KBytes Parameter Blocks
• One, 96 KByte Main Block
One, 128 KByte Main Block
• 8-bit oniy ,operation and packaging for space sensitive applications (28F002BX)

HARDWARE DESIGN FOR A
256 KBYTE BIOS
Intel 28F200BX/002BX Soot Block
Flash Memory Family

Building upon the wide acceptance of the
Intel28F001BX 1 Mbitflash memory for BIOS designs,
a new family of higher density flash componentsis now
available to solve the PC designer's need of implementing extended BIOS code beyond 128 KBytes.
These new flash memories at the 2 Megabit density levels, are structured around the same boot block architecture as the Intel 28FOOIBX and are therefore compatible. They provide block erasure capability, boot code
hardware protection and very low power consumption
as in the case of the 28FOOIBX.
In addition, they incorporate new features to simplify
the device interface and allow the system designer to
optimize platform designs.
These new features are summarized as follows:
• User selectable 8-bit or 16-bit read/write operation
(28F200BX)
• 60 ~s access time performance
• 16 KBytes Boot Block space which is hardware protected

In this section, we will describe these new features in
more detail and discuss their system applicability.
The blocking scheme, while still of the boot block typ.e,
is expanded by defining additional blocks .(2 main
blocks) to allow for software modularization and a selfcontained design.
As the size of the BIOS code stored in anyone device
grows' due to the complexity and high int~gration of
chip-sets, so does the "kernel" code stored In the boot
section. The boot and parameter blocks were accordingly doubled in size in comparison to the 28FOOIBX
device. The two parameter blocks of 8 KBytes each
allow the PC designer to store BIOS extensions or Battery-Backed SRAM configuration data (CM~SRAM,
EISA configuration parameters). The two main blocks
are used to store the main BIOS code in modular fashion if so desired for future easy updates. These main
blocks can also.be used to store ROM-executable Operating System software such as MS-DOS 5, ROM version or drivers and utilities. Refer to Figure 2 for the
block locations for both the 28F200BX-T and
28FOO2BX-T.

(Word Addresses)

(Word Addresses) .

,1FFFFH

3FFFFH
16 KByte BOOT BLOCK

16 KByte BOOT BLOCK

1EOOOH
1DFFFH
1DOOOH
1CFFFH,
1COOOH
1BFFFH

3COOOH
3BFFFH
8 KByte PARAMETER BLOCK

3AOOOH
39FFFH

.8 KByte PARAMETER BLOCK

8 KByte PARAMETER BLOCK
8 KByte PAPf-METER BLOCK

38000H
37FFFH
96 KByte MAIN BLOCK

96 KByte MAIN BLOCK

10000H
OFFFFH

20000H
1FFFFH
128 KByte MAIN BLOCK

128 KByte MAIN.BLOCK

OOOOOH

OOOOOH

Valid Address-es in X16 Mode (BYTE = 1): AO-A16
Valid Addresses in X8 Mode (BYTE = 0):
A-1 (lowest order address) and AO-A16

,

28F200BX-T Top Boot Map

28F002BX-T Top Boot Map

Figure 2. 28F200BX-T/002BX·T Memory Maps

3-470

AP-363

In addition, the 28F200BX/OO2BX devices incorporate
new capabilities desired by today's sophisticated PC designer.
The byte-wide or word-wide feature available as a designer-selectable option gives the ability to interface to
an 8-bit or 16-bit wide bus. The performance and hardware goals of some systems may require 16-bit BIOS
data bus. A system with a small amount of RAMaIid a
large amount of flash memory-based operating system
code for example, may require a 16-bit BIOS data bus
to maintain a high performance level of operation;

The 28F200Bx/OO2BX devices incorporate an internal
Write State Machine, Command User Interface and a
Status Register to fully control the program and erase
operations and greatly simplify the user write and erase
algorithms and hence the update code procedure. They
also include' an erase suspend feature which allow the
system to service interrupts and access the device during BIOS code updates (refer to appendix B).
Finally, the 28F200BX/OO2BX, 2 Megabit devices have
an equivalent 4 Megabit boot block flash memory family of devices called the 28F400BX/OO4BX, allowing for
easy density upgrade and total compatibility between
systems using both types of memories. Refer to the documentation mentioned in the reference section of this
application note~

The high access speed of these new devices, which for
the first time break the 60 ns barrier, is another big
advantage the PC designer can fully exploit to increase
system performance and acceptance ill the marketplace.
For example, a PC designer may choose to execute
BIOS directly out of flash memory instead of shadow- ,
ing to system RAM as well as execute MS-DOS 5,
ROM version out of flash for instant-on capability and
to achieve better overall system performance.
Block eraSllre allows independent modification of code
and data and maximum flexibilty in production as well
as after'the system is shipped. The boot block, which is
hardware protected, insures that minimal BIOS code is
present to always boot up the system successfully. The
16 KByte boot block is protected from alteration during system power excursions ~igh voltage pin. This
write protection pin called PWD, has to transition to
12V with the normal Vppvoltage pin to allow for boot
block write and erase operations.
If systems are designed with the ability to switch PWD
to high voltage (12V), guaranteed full non-volatility of
the boot code is achieved. This feature always guarantees system recovery from power failure and provides
the security needed for the end user when performing
BIOS code updates.
To meet the crucial needs of lower power consumption,
the 28F200BX/OO2BX devices incorporate a deep-power down current mode activated through the PWD pin
under the TTL/CMOS level control. When this pin
'transitions to ground the' device typically consumes
1 microwatt through the Vcc supply pin.

Figure 3 is a block diagram description of the
28F200BX/OO2BX products.

4.2 Intel386SLTM Microprocessor
, Superset Platform Overview
This design example focuses primarily on how to interface the Intel 28F200BX-T or 28FOO2BX-T Boot Block
Flash memories to the Intel386SL Microprocessor Su, perset in a 16-bit wide or an 8-bit wide configuration
respectively. This is an extended BIOS design, example
which demonstrates how the barrier of the 128 KBytes
BIOS size memory is eliminated. Figure 4 shows an
interface diagram of the Intel 28F200BX-T Boot Block
Flash memory (128 K x 16) to the Inte1386SL Microprocessor superset. Figure 5 shows an equivalent interface diagram of the Intel 28FOO2BX-T Boot Block flash
memory (256 K x 8) to the Intel386SL Microprocessor
Superset;
The Intel386SL Microprocessor Superset Flash BIOS
interface supports up to 256 KBytes of Flash BIOS (a 2
MEGABIT Flash memory device} to enable the system
designer to meet specific' design goals as described in
'
section 3 above.
The Intel386SL Microprocessor Superset supports the
following features:'

In addition, the 28F200Bx/OO2BX devices include an
Automatic Power Savings feature during active mode
of operation. This feature allows the memory chip to
put itself in a very low current state when it is enabled
but not accessing a new memory location. '

3-471

• Up to 256 KBytes Flash BIOS
.- VGA B~OS mapping into system BIOS
• 8-bit or 16-bit BIOS interface
• Programmable number of flash wait states for read
access (from zero' to fifteen Wait-States to optimize
the system performance)
• BIOS shadowing mechanism

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:!92098-2

infel .

AP·363

Flash BIOS size configurations in the Intel386SL Microprocessor Superset system are controlled by programming certain registers located in the normal I/O
address space, namely:

BIOS device. In the case of a single Flash BIOS device,
only ROMCSO is needed to drive the CE chip Select
signal of the flash memory.

• EBCICR: External Bus Unit Configuration
Register 1 located at 300H
• ROMCS-1)EC: ROM Chip Select Decode register
located at Index 2FH
• ISAWINDOW: ISA Window control register located at BOOH

In the diagram of Figure 4 note the following:
• BYTE signal is set high to enable 16-bit operation of
the flash device.
• The highest order system address line SA16 is inverted when FLIP signal becomes active at boot-up
time to relocate the boot kernel code at the top of
the 1 MByte memory map for the system to boot
from it. (See section 4.5).
• ROMI6/S is setbigh to enable 16-bit bus operations.
.

When a 256 KByte Flashi:nos configuration ·is programmed into the Intel386SL Microprocessor Superset,
128 KBytes are directly accessible in the EOOOOHFFFFFH address range. The other 128 KBytes are decoded at the top of the 16th or· 32itd Megabyte of the
Intel386SL superset address space, i.e., either:
FCOOOOH-FDFFFFH or IFCOOOOH-IFDFFFFH.
'{his extra ROM space is accessed by programming the
ISA sliding control register to point to one of these two
areas and then accessirig the ISA sliding window in the
DOOOOH-DFFFFH address range (64 KBytes). This
mechanism allows complete access of the 256 KBytes
of BIOS code without having to enter the Intel386SL
protected mode.
The BIOS code size is used to internally decode the
ROM address space and generate two chip select signals: ROMCSO and ROMCS1, to control the Flash

• PWD signal is gated by the PWROOOD signal (for
reset when power fails) and by system RESET signal.
• Vpp supply voltage is switched to the flash device
only when BIOS updates are required.
In addition: to the above considerations, note the following in Figure 5:
•. The highest order system address line SA 17 is also
inverted when FLIP signal becomes active at system
boot-up time.
• ROMI6/S is set low to enable 8-bit only bus operations.

3-473

intel .

AP-363

+1.2V

I62~N6TgiLrM I

Si.lOUT i

X07

ISA
~=-------..,
PERIPHERAL I-X~D;.;;E;.;.N_ _ _ _ _...,
I/o
XDIR

-+.~.\ :_.~
I

I

Vpp
Switch

1-----,

Vpp

INTEL
80386SLlM

+5V

CPU

Vee

+5V

+5V
ROMI6!8

292098-3

LEGEND:
XDEN = X-BUS DATA ENABLE
XDIR = X-BUS DATA DIRECTION
SMOUT1,2 = SYSTEM MANAGEMENT OUTPUT CONTROLS
ROMCSO = ROM CHIP SELECT FOR SYSTEM FLASH BIOS
MEMR = MEMORY READ
MEMW = MEMORY WRITE
FLIP = BOOT BLOCK MEMORY MAPPING SIGNAL
ROM 16/8 = ROM 16 BITS OR 8 BITS
SD[6:0), SD[15:8] = SYSTEM DATA BUS
SAO-16 = SYSTEM ADDRE§@:,BUS
XD7 = X-BUS DATA BIT 7
PWRGOOD = POWER SUPPLY POWER GOOD SIGNAL

Figure 4. Intel386SL TM Microprocessor Superset with the 28F200BX-T Flash BIOS Chip

3-474

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AP-363

+12V

INTEL
82360SL'"
ISA
PERIPHERAL

SMOUT1-J~~

XD?

I

I

..

_01

Vpp

I/o

Switch

Vpp

INTEL
80386SL'"

+5V

CPU

ROM1S/ii

GND
292098-4

LEGEND:
XDEN = X-BUS DATA ENABLE
XDIR = X-BUS DATA DIRECTION
SMOUT1,2 = SYSTEM MANAGEMENT OUTPUT CONTROLS
ROMCSO = ROM CHIP SELECT FOR SYSTEM FLASH BIOS
MEMR = MEMORY READ
MEMW = MEMORY WRITE
FLIP = BOOT BLOCK MEMORY MAPPING SIGNAL
ROM 16/8 = ROM 16 BITS OR 8 BITS
SD[6:0] = SYSTEM DATA BUS
SAO-17 = SYSTEM ADDRESS BUS
XD7 = X-BUS DATA BIT 7
PWRGOOD = POWER SUPPLY POWER GOOD SIGNAL

Figure 5_ Intel386SLTM Microprocessor Superset with the 28F002BX-T Flash BIOS Chip

3-475

inlel..

AP-363·

4.3 . Programming the Intel386SL TM
Registers

ROMCS-PEC

ISA SLlDlt.rG WINDOW PROGRAMMiNG:
ISAWINDOW

When the ISA window is enabled, any access to the
area of memory from' DOOOOH to· DFFFFH is remapped. according to the upper address field specified
in the ISA WINDOW control register: To use the ISA
sliding window mechanism, the ISA.WINDOW enable
bit Bit 15 of the ISAWINDOW control register must be'
set. See the diagram below for a definition of the
ISAWINDOW register:
ISAWINDOW

o

15

UPPER ADDRESS (A23-A16)

' - - - - - - - - - - - - ' - - EODIS'
BIOS256KEN

L.._ _- ' -_ _ _ _ _ _ _

L.._ _ _ _ _ _~_ ____'_

ENABLE

ROM256KEN.

292098-6

LOVGA
Low VGA BIOS mapped into system
BIOS.
Bit I:HIVGA
High VGA' BIOS mapped into system
BIOS.
Bit 2:
. ROM25~KEN
256 KByte ROM enable. When this bit is
set, the Intel 82360SL wiII properly assert
XDEN and route XD7 through SD7 properly for accesses to the-following ranges:
E
while the WSM is executing the internal byte write algorithm in Byte Write mode. The 2SFOOSSA automatically outputs Status Register data when in Byte Write
mode.
Erase Setup,

The 2SFOOSSA transitions to Erase Setup ,mode after it
receives the Erase Setup command. If the 2SFOOSSA is
read in Erase Setup mode, it outputs Status Register
data.

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AP-364

Table 3. Write State Machine Current/Next States

Byte
Write

Read
Array

Byte

VOH

Erase
Setup

Clear
Status

(20H)

(SOH)

Erase
Setup

Read
Array

Read 10
(90H)

Read 10

Byte Write
Setup
Byte Write
(Not
Complete)

Erase
Setup
Erase
Command
Error
Erase
(Not
Complete)

Erase
Suspend
to Arr~y

VOH

Read
Status
Read
Identifier

VOH

10

Read
Array

Write
Setup

. NOTE:
1. State.transitions labeled "Reserved" are set aside by.lntel Corporation for potential future device implementations. Command sequences to access these states should not be attempted.

3-505.

AP·364

Erase

Read Status

After the 2SFOO8SA is placed in Erase Setup mode,
write of the Erase Confirm command transitions the
-WSM to Erase mode, wheie the. specified address. is
decoded into one of 16 blocks to be erased. Immediately, the WSM eiamineS Vpp, and if it detects an invalid
level, it halts with Vpp error mdication in the Status
Register (bit 3 = 'T'). Bit 7 of the status Register is
"0", and the RY/BY output is driven to VOL> while the
WSM is executing the internal block erase algorithm in
. Erase mode. The 2SFOOSSA automatically outputs
Status Register data when in Erase .mode.

Erase Command Error
This is the other possible transition mode after Enise
Setup, and occurs when an invalid command (anything
b:ut . Erase Confinn/Resume)is written to. the
2SFOOSSA as the second .in the two-comttllindblock
erase sequence. In this mode, the WSM does not attempt a block erase, and it returns an error indication
to the system by setting both bits 4 and. 5 of the Status
Register to" I". The 2SFOOSSA automatically outputs
Status. Register data when in Erase Command Error
mode.
.

Erase Suspend to StatuslArray
Whi1e'the WSM is busy executing an internal block
ewe algorithm, it can be placed iii. erase suspend by
writing the Erase Suspend command. After receiving
lind decoding· this command, the WSM suspends block
erase, drives the RY/BY output to VOH, sets bits 6 and
7 of the Status Register to "I" and transitions to "Eras,e
Suspend to Status" mode. The 2SFOOSSA automatiCally outputs Status Register data when in "Erase Suspend
.
to Status" mOde.
The oilly validcommalid: other than Read Status and
Erase Resume at this time is Read Array, which tran- .
sitions the WSM to "Erase Suspend to Array" mode.
As the name implies, the 28FoOSSA outputs array data;
ilot Status Register contents, in this mode.. While in.
both Erase Suspend modes, Vpp must remain at VPPH
for erase to complete successfully when resumed:
Writing the Erase Resume (same ali Erase Confirm)
command to the 2SFOOSSA transitionS the WSM out of
Erase Suspend and back to EraSe. In colijjinction with
this, the WSM returns RY/BY to VOL and resets bits 6
and 7 of the WSM to "0".

As the ilame implies, the 2SFOOSSA automatically outputs Status Register contents when read in Read Status
mode. If system software writes the Clear Status commarid at this point, the WSM resets the Status Register
to its default value and transitions to Read Array
mode.
.

Read Identifier'
The 2SFOOSSA outputs its manufacturer identifier of
S9H when read from address OOOOOH when in Read
. Identifier mode. Similarly, a read from address OOOOIH
returns the device identifier A2H. Using this information, the system can automatically match the device
with its proper block erase and byte write algorithms.
Reads from addresses other than OOOOOH and OOOOIH
are not supported by Intel, arid consistent results of
such reads are not docuinented, guaranteed. or recommended.
.

2.6 Block.Erase as a Background
Task
As inentioned earlier, the internal WSM block erase
algorithm typically takes 1.6 seconds to complete.
Proper implementation of block erase from a hardware
and software standpoint, however, can mask this delay,·
by taking advantage of the 28FOOSSA's intemalautomation and full-featured system interface. Execution of
block erase as a backgroimd task, with higher priority
read and write functions in the foreground, is 'the key.
The recommended scenario' includes an "intelligent';
operating system routine which can keep track of
"busy" devices in the 2SFOOSSA array. After initiating
-block erase oli these components, the operating system
is free to concentrate on reads and writes; or any other
pending requests that demand its attention. The
28FOOSSA RY/BY output alerts the systein wh~
block erase completes, and the operatirig system acts on
.this completion in the resulting interrupt service routine.
Hardware interrupt via the RY/BY output is a recom. mended technique for block erase. Ho\vever, this meth~
od should be evaluated closely for alerting the system to
byte write completion. The WSM typically completes a
byte write attempt in9 ,..,s, Ii much shorter time than
that consumed in .many CPU interrupt latencies. In
stich cases, software polling of the 2SFOOSSA Status
.Register to detect WSM "ready", versus hardware interrupt, will result in highest byte. write perfortnance.
Reference AP-359, "2SFOOSSA Hardware Interfacing",
for circuit implementations _that not _only combine
RY/BYs into a common INT, but also allow RY/BY
masking if desired.

3-506

intel..

AP-364

ADDITIONAL INFORMATION
Order
Number
28F008SA Datasheet

290429

28F008SA-L Datasheet

290435

AP-359
AP-360
ER-27
ER-28

"28F008SA Hardware
Interfacing"
"28F008SA Software
Drivers"

292094

"The Intel 28F008SA Flash
Memory"
"ETOXTM-III Flash Memory
Technology"

294011

292095

294012

REVISION HISTORY·
Number
002

Description
Page 3-502: Erase Command Error: In this mode, the WSM does not attempt a block erase,
and it returns an error indication to the system by setting both bits 4 and 5 of the Status
Register to "1".

3-507

intel·

APPLICATION
NOTE

AP-371

October 1992

,

(

Designing Flash Card Readiness
,
into Today'sSystems

GARY FORNI
FLASH CARD APPLICATIONS GROUP.

Order Number: 292109-001
3-508

Designing Flash Card Readiness into Today's Systems
CONTENTS

CONTENTS

PAGE

PAGE

1.0 STANDARDS ...................... 3-510

4.0.UPGRADABILlTV .................. 3-513

2.0 HARDWARE, ...................... 3-510

4.1 Example 1 ....................... 3-513
4.2 Example 2 ....................... 3-513

3.0 SOFTWARE ....................... 3-511

5.0 CONCLUSiON ..................... 3-514
APPENDIX A: WHERE TO GO FOR
MORE INFORMATION .............. 3-515

3-509

AP-371

This application note was created to infonn the OEM
how to make his system Flash card ready.
A number of requests have come in from customers
\vho are adding PC~.fCIA slots to theii systems and
want to include the capability to upgrade to flash cards
and Microsoft's Flash File System (FFS). This summary discusses how to include flash card upgradability in
systems being designed today.
This guide is divided into four areas: standards, hardware, software, and upgrades.

1.0 STANDARDS
PCMCIA revision 2.0 sets the standard for the physical
and electrical characteristics of memory and I/O PC
cards. Unfortunately, what it doesn't do is set the standard for the host system's architecture. That's where
the ExCATM (Exchangable Card Architecture) specification comes in. ExCA specifies the minimum requirements for what the host system must provide. The
ExCA specification covers both the hardware and software requirements of the system. The recommendations in this design guide follow the ExCA requirements.

2.0 HARDWARE
While software can be upgraded at a later date, either
in the factory, or in the field; hardware typically cannot. That's why ii's so important that aii of the hardware necessary to support flash cards be designed into a
system up front.
. Fortunately, ExCA compliant hardware is available today. The Intel 82365SL PC Card Interface Controller
(PCIC) is ExCA compliant andhas rapidly become the
PC Card controller standard.
The PCIC interfaces the ISA bus to the PCMCIA sock-.
et, and handles interrupt steering, memory and I/O
window mapping, and power management. A schematic for creating two fully buffered sockets is found in the
82365SLTM datasheet and is included here as
Figure 1,(1)
Writing and erasing Flash cards requires Vpp = 12V,
with Ipp = 60 rnA minimum. Remember, when choosing a voltage converter, other devices (video, etc) may
also require 12V, so take care to pick one that will
supply all of your simultaneous needs. For more information and numerous examples on power conversion
read Application 'Note 357 Power Supply Solutions for
Flash Memory.

74ACT16245

50[0:15]

SA[O:ll]

SLOT

SA[l:9]

A

(A)
SO[O:16]
LA[17:23]
ISA CTRL
IRO[2:5,9:12,14,15]

82365SL

SYS CTRL
PORT

CTRL
(I)
(I)

....J

a::

I-- I--

....

SLOT

0

a::  ~
RnA

196d'M
KAlKB
PROCESSOR

-

I _

-

-

-

, ,

-

-

IMAGING AND
COMMUNICATION

I

~lsp~ay_Lls!

'_B_a~B~ffe~

,I

s ~A

FONTCARDI
CARTRIDGE
INTERFACE

82961KD
PRINTER
COPROCESSOR

'BOISE"
PARALLEL
SERIAL
LOCALTALK

NElWORK

Figure 2. Flash Memory, A Key Element In Leading Edge Laser Printers

2.1 System Code Memory
The system code memory stores the software
that is executed by the embedded processor to
run and control the laser printer. This includes
code to interface the processor with the input!·
output, coprocessor, print drum and motor
subsystems. System code memory also includes a large amount of software devoted to,
emulating various printer description languages .. The most commonly known PDLs are
BostScript* (pioneered by Adobe and currently at version iO) and PCL* (Printer Control Language, pioneered by Hewlett Packard
and currently at versi9n 5). Beyond these two
"industry standards", dozens of additional
proprietary "languages" have been developed
by various hardware and software ·vendors.
Depending on the complexity and capabilities
of the Iilser printer and the number of supported emulations, system code size varies. ·It
ranges from as little as 256 KBytes for an

entry-level personal printer to several MBytes
for powerful high-end network laser printers.
The traditional memory technology used to
store system code is high density ROM (for
nonvolatility) shadowed to DRAM on system
powerup (for fast read access time);
Flash memory, when used for system code .
storage, combines the nonvolat1lity and high
density of ROM' with the fast read performance of DRAM, making the ROM/DRAM
redundancy unnecessary, Additionally, the
in-system upgradeability of flash memory
makes laser printers flexible and updateable
both in the manufacturing line at your factory ,
and once the system is in the hands of the end
customer. Although the per-device cost of
flash memory is higher than that of ROM,
flash memory's upgradeability can result in a
lower system cost through Ii laser printer's
operating lifetime.

3-519

infel®

AB·29

Flash memory eliminates costly inventory of
ROMs, ROMs that must be scrapped if an
enhanced software version is released or a
software. "bug" is discovered. Using flash
memory, one hardware design can service
mUltiple markets via simple "end-of-line" programming as the system leaves the factory.
Additionally, diagnostic code can be programmed on the assembly line for full system
debug, and replaced with the final software
version later in the manufacturing flow.
. Today, upgradeability once a system reaches
the customer's hands is achieved via propri. etary, costly add-in ROM cards. These emulation modules connect to the host system
through low-perfprmance interface buses.
Updating the local code memory in the printer
requires a technician visit, is very costly to the
customer, and is therefore rarely done. ·The
result can be a less-than-optimized system
with subpar
.performance, and a,I dissatisfied .
.
customer that will not consider your company
for his/her next printer purchase!.
Flash memory's in-system reprograinming
makes system code upgrade as simple as running an "UPDATE" ritility on, the host computer, and can be done by the customer at his/
her PC using a diskette sent by the printer
manufacturer, or a file downloaded from.a .
OEM computer bull~tin board service. Con, figuring the printer with,thfj exact emulations' .
needed is equally straightforward. Customer
service is perhaps. the supreme differentiator
in multiple-sourcemarkets~ As companies
focus more and more on the customer and the
service aspects of their business, they
turn
to flash memory as,.a means of readily and

will

economically achieving their goals.
Intel's BootBlock flash memory product line
has been specifically defined to meet the
specific requirements of high-density embedded code storage and execution. These devices are also available in ROM-compatible
pinouts. This allows printer OEMs to achieve
quick time-to-market with rev. 0 software
(updateable once initial systems are in customer hands) and later convert their designs to
ROM if desired, once final production code is
stable. For further information on these products, reference the Additional Information
section at the conclusion of this application
brief.

2.2 Font Storage
Today's laser printers ship from the factory
with a number of "resident" fonts stored in
nonvolatile ROM. The density of this memory
varies with the end market for the printer. A
"Roman" set of resident typefaces requires
anywhere from 1-2 MBytes of storage., Japanese "Kanjil" fonts, on the other hand, require
upwards of 5 MBytes per typeface. A minimum-configured laser printer for the Japanese
market therefore needs 10-20 MBytes of res ident font memory. Additional permanent font
storage is often available through ROM font
cartridges, similar to the "emulation" fonts·
mentioned earlier. Finally, software such as
Adobe Type Manager* and Microsoft*
TrueType* downloads font iriformation to the
printer, storing it in volatile DRAM. 'This
latter temporary font data· is lost when the
pnnteris turned off or reset. Resets can occur,
for example, each time the printer output jams,
or when the paper supply is depleted;,

3-520

AB·29

Computer users are more and more outgrowing the capabilities of the resident ROM fonts
stored in their laser pririters,. or available
through the ROM expansion font cartridges.
ATM and TrueType are enabling these users
to customize their documents by varying not
only font size and attributes, but also the font
typefaces themselves. Many corporations have
developed custom fonts for use by their employees for a consistent documentation "look
and feel". These unique typefaces are not a
part of the resident standard typeface set.
Finally, not only fonts, but also graphic bitmaps
(corporate logos .. bitmapped signatures, etc)
and page layout templates are being integrated
into desktop-published documents. All of this
non-resident information must be repeatedly
downloaded from the host computer to the
printer DRAM after each printer poweroff or
reset. Since this' download is accomplished
via the serial or parallel connection, print
performance is dramatically and negatively
impacted, especially noticeable in a networked
printer;rrrangement.
.Flash memory, with its unique set of attributes,
.combines the best qualities of today' s font and
template storage solutions while incorporating none of their weaknesses. Like DRAM, it
is in-system updateable and has comparable
per-device cost at higher densities. Like ROM,
it is nonvolatile. Like both of these technologies, it is a very dense storage medium, available in sIzes up to IMByte per component, and
20MBytes per card, at the time this application
note was written. Where extremely high densitymemory is needed, as in the case of Kanjii
font storage, flash memory components have
an over 200,OOOx first read access advantage
and an over 14x data transfer performance
advantage over hard disk drives. The performance of a printer computing subsystem is

significantly hindered by the slow access time
of a HDD. Flash memory, with its sub-lOOns
read speed, is the superior solution.
A resident high-density array of flash memory
is coupled directly to the CPU local bus for
highest performance. It allows the customer
to exactly configure the printer font, bitmap
graphic and page, template information for his!
her specific applicatiolls. This data is downloaded to the printer once, a,nd from that point
on is always available for use, even after the
printer is turned off or reset. If expanded
printer usage (as in a network environment)
. requires additional resident "font" storage in
the future, easy density upgrade is enabled by
designing in a PCMCIA/ExCATMmemory-I!
o card socket, again interfacing directly to the
embedded processor bus. Plugging in a flash
memory card means no printer disassembly is
required!
Intel's FlashFileTM flash memory component .and Series 2 flash memory dud lines
combine the high density and high performance required for resident "font" storage .
For further information on these products,
reference the Additional Information section
at the conclusion of this application brief.
2.3 Image Storage and Manipulation
The temporary graphic memory subsystem·
stores the image to be printed as it is "constructed" by the processor from data provided
by the host computer. Optimum characteristics of this memory include full "real-time"
bit-level alteration, infinite rewrite capability
and fast read/write performance. Nonvolatility
is not required in this area of the memory
subsystem. Therefore, DRAM will continue
to' be the memory of choice for temporary
image storage.

3-521

AB·29

3.0 SUMMARY
This application brief has discussed the various memory subsystems in today's laser printers, and their operating characteristics. Flash
memory is an exciting new approach that
offers the very real potential to significantly
improve your next· generation laser printer
designs. Its capabilities are superior to traditional solutions in the system code and font

memory areas, and enable laser printers that
are more expandable, more flexible, higher
performance and easier to use than ever
before. The end result is a satisfied customer,
a customer that will choose your product over
a competitor's, and a customer that will remain loyal to your company far into the future.

ADDITIONAL INFORMATION
For additional information oil the Intel flash memory products mentioned in this article, please
reference the· following documents, available through your local Intel sales representative.
BootBlock Components
28F001BX Datasheet
28F200BX/28F002BX Datasheet
28F400BX/28F004BX Datasheet
ER-26 "The Intel 28FOOIBX-T and 28FOOIBX-B Flash Memories"
ER-29 "The Intel 2/4 Mbit BootBlock Flash Memory Family"

Order Number
290406
290448
290451
294010
294013

FlashFile Components
28F008SA Datasheet
AP-359 "28F008SA Hardware Interfacing"
AP·360 "28F008SA Software Drivers"
AP-364 "28F008SA Automation and Algorithms"
ER-27 "The Intel 28F008SA Flash Memory"

Order Number
290429
292094
292095
292099
294011

FlashFile Series 2 Cards
Series 2 Flash Memory Card Datasheet
AP-361 "Implementing the Integrated Registers of the Series 2
Flash Memory Card"

Order Number
290434
292096

General Flash Information
AP-357 "Power Supply Solutions for Flash Memory"
ER-20 "ETOXTM II Flash Memory Technology"
ER-28 "ETOXTM III Flash Memory Technology"

Order Number
292092
294005
294012

Microsoft and TrueType are trademarks of Microsoft Corporation. Adobe Type Manager and
PostScript are trademarks of Adobe Systems Incorporated. PCL is a trademark of Hewlett
Packard Corporation. ETOX, FlashFile and ExCA are trademarks of Imel Corporation.

3-522

infel·

ENGINEERING
REPORT

ER-20

September 1991

ETOXTMII Flash Memory
Technology

JASON ZILLER
PRODUCT ENGINEERING

Order Nomber: 294005-006
3-523

ETOXTM II FLASH MEMORY
TECHNOLOGY

CONTENTS

PAGE

INTRODUCTION ....................... 3-525
ETOX II FLASH MEMORY CELL ...... 3-525
MEMORY ARRAY
CONSIDERATIONS ................. 3-525
ETOX II FLASH MEMORY
RELIABILITY . ....................... 3-525
SUMMARY ............................ 3-526

3-524

intet

ER-20

INTRODUCTION

MEMORY ARRAY CONSIDERATIONS

Intel's ETOXTM II (EPROM tunnel oxide) flash memory technology is derived from the CHMOS" III-E
EPROM technology. It replaces ultraviolet erasability
with a non-volatile memory cell that is electrically erasable in bulk array form. Intel flash memory combines
the EPROM programming mechanism with EEPROM
erase, producing a versatile memory device that is highly reliable and cost effective. This report describes the
fundamentals of the ETOX II flash memory cell in
comparison to the standard EPROM, and gives insight
into its operation in a system environment.

The ETOX II flash memory cells have the same array
configuration as standard EPROM, thereby matching
EPROM in density. Also, identical peripheral circuitry
for normal access achieves the same read performance
as the Intel CHMOS III-E EPROMs.
,

The ETOX II flash memory cell is nearly identical in
size to CHMOS III-E EPROM. This allows comparable densities. The primary difference between ETOX II
flash memory and EPROM cells is the flash memory
cell's thinner gate oxide, which permits the electrical
erase capability. (See Photo 1.)

ETOX II FLASH MEMORY CELL
Intel's ETOX II flash memory cell is composed of a
single transistor with a floating gate for charge storage,
like the traditional EPROM. (See Figure 1.) In contrast, conventional two-transistor EEPROM cells are
typically much larger. Intel produces ETOX II flash
memory devices on 1.0,.., photolithography.
The ETOX II cell's programming mechanism is identical to the EPROM; that is, hot channel electron injection. The device programming mode forces the cell's
control gate and drain to a high voltage while leaving
the source grounded. The high drain voltage generates
"hot" electrons that are swept across the' channel.
These hot electrons collide with other atoms along the
way, creating even more free electrons. Meanwhile, the
high voltage on the control gate attracts these free electrons across the lower gate oxide into the floating gate,
where they are trapped. (See Figure 2.) Typically, this
process takes less than 10 ,..,s.
Flash memory's advantage over EPROM is electrical
erasure, discharging the floating gate without ultraviolet light exposure. The erase mechanism is an
EEPROM adaptation which uses "Fowler-Nordheim"!
tunneling. A high electric field across the lower gate
oxide' pulls electrons off the floating gate. The erase
mode routes the same external voltage used for programming to the source of the memory cell, while the
gate. is grounded and the drain is left disconnected.
(Figure 3.)

Intel flash memory's programming circuitry is also
identical to Intel's EPROM designs. Row decoders
drive the selected wordline to high voltage, while input
data combined with column decoders determine the
number of bitlines that are gated to high voltage. This
provides the same byte programmability. as an
EPROM. Intel Flash Memories, offer the efficient
Quick-Pulse Programming algorithm that is featured
on advanced EPROMs.
.
Array erase is unique to flash memory technology. Unlike conventional EEPROMs, which use a select transistor for individual byte erase control, flash memories
achieve much higher density with single transistor cells.
Therefore, the erase mode supplies' high voltage to the
sources of every cell simultaneously, performing a full
array erasure. A programming operation must be performed before every erase to equalize the amount of
charge on each cell. Then Intel's Quick-Erase™ algorithm intelligently erases the array down to the appropriate minimum threshold level required to read all
"ones" data. This procedure ensures a tight distribution
of erased cell thresholds throughout the array.

ETOXTM II FLASH MEMORY
RELIABILITY
The reliability of Intel's CHMOS ETOX II flash memory process is equivalent to its sister EPROM technology. The ETOX II and EPROM processes share the
same data retention characteristics. Preliminary qualification data shows that 1 Megabit flash memories produced on the ETOX II process provide at least 10,000
program and erase cycles (typical 100,000) with no cycling failures due to oxide stress or breakdown. This
extended cycling capability is attributed to improvements in tunnel oxide processing and advantages inherent in the ETOX II cell approach.
'

1M. Lenzlinger, E.H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown Si02," Journal of Applied Physics, Vol. 40
(1969), p. 278.
'Intel's ETOX II flash memory process has patents pending.
"CHMOS is a patented process of Intel Corporation.

3-525

ER·20

SUMMARY
ETOX II flash memory technology is the optimal combination of EPROM and EEPROM technologies. Intel's new ETOX II flash· memory process offers extended cycling capability with the density and manufacturability of EPROMs. From an application standpoint,
flash memory technology provides' the capability to
improve overall system quality throughout the product

development and manufacturing stages. Also, flash
memory density is ideally suited for applications requiring version updates of entire programs which, in turn,
suit the "flash" characteristics of erasing the entire array at once. in addition, individual byte programming
allows for data acquisition. Flashmemory devices produce on the ETOX II process provide a high density,
low cost solution to many system memory storage requirements which were previously unavailable.

,

Table I

Normalized Cell Size
Programming:
Mechanism

EPROM

ETOX 11 Flash
Memory

EEPROM

1.0

1.2-1.3

3.0

Hot Electron
Injection
Byte
< 10JLs

Tunneling
Byte
Sms

Tunneling
Bulk Array
< 1 Sec.

Tunneling
Byte
Sms

Resolution
Typ. Time

Hot Electron
Injection
Byte
< 100 JLs

Erase:
Mechanism
Resolution
Typ. Time

UV Light
Bulk Array
20 Min.

,

294005-1

Figure 1.ETOX 11 Flash Memory Cell Layout (Top View)

SELECT GATE

294005-2

Figure 2. ETOX 11 Flash Memory Cell during Programming (Side View)

3-S26

ER·20

294005-3

Figure 3. ETQX II Flash Memory Cell during Erase (Side View)

PHOTO 1

294005-4

294005-5

ETOX II Cell

CHMOS III·E EPROM Cell

(50,000 x Magnification)

(50,000 x Magnification)

3·527

infel·

ER-24

ENGINEERING
REPORT

August 1992

Intel Flash Memory

28F256A
28F512
28F010

28F020

Order Number: 294008-006
3-528

Intel Flash Memory

28F256A,28F512,28F010,28F020
CONTENTS

PAGE

CONTENTS

PAGE

INTRODUCTION ....................... 3-530

DEVICE RELIABILITY ................. 3-531

TECHNOLOGY OVERVIEW ........... 3-530

SUMMARY . ........................... 3-532

DEVICE ARCHITECTURE ............. 3-530

3-529

ER-24

INTRODUCTION

DEVICE ARCHITECTURE

Intel's ETOXTM II (EPROM tunnel oxide) Flash
Memory adds electrical chip erasure and reprogramming to EPROM non-volatility and ease of use. Advances in tunnel oxides and photolithography have
made it possible to develop a double-polysilicon singletransistor read/write random access nonvolatile memory, capable of greater than 10,006 reprogrammin~ cycles (typical 100,(00). Intel Flash Memory electn~y
erases all bits in the array matrix via electron tunneling.
The EPROM programming mechanism of hot electron
injection is ~mployed for electrical byte programming.
A command port interface, internal margin voltage
generation; power up/down protection and address and
data latches augment standard EPROM circuitry to
optimize Intel's Flash Memory for microprocessor-controlled reprogramming.

Command Port
Orie feature which differentiates Intel's Flash Memory
is the command port architecture, illustrated in Figure
2.
The command port simplifies microprocessor control of
the erase, erase verify, program, program verify, and
read operations, without the need for additio~al control
pins or the multiplexing of high voltage With ~nt~ol
functions. On-chip address and data latches mmlmlze
system interface logic and free the system bu~ during
erase and program operations; High voltage (12V) on
the Vpp pin enables the command port. In the absence
of this high voltage, the command port defaults to the
read operation, inhibiting erasure or programming of
the device.

Read timing parameters on Intel's 28F256A, 28F512,
28FOIO and 28F020 are equivalent to those of CMOS
EPROMs, EEPROMs, and SRAMs. The 90 nS, 120 ns
and 150 ns access times result from a memory cell current of approximately 50 pA, low resistance poly-silicide wordlines, advanced scaled periphery transistors,
and an optimized data-out buffer.

EPROM Cell
SECOND lEVEL

+VG

POlYSlllCON '" "'~

... 'lI.

fiRST lEVEL

POlYSILICON

~
3~5X :1f=GATE

(flOATING)

Vs

,

+VD

Yl f

'TECHNOLOGY OVERVIEW

N+_.1

Intel's ETOX II flash memory technology is derived
from its standard CMOS EPROM process base. Using
advanced 1.0 p.m double-polysilicon n-well CMOS
technology, Intel Flash Memory employs a 3.8 p.m x
4.0 p.m single transistor cell, affording equivalent array
density as comparable EPROM technology. The flash
memory cell structure is identical to the EPROM structure, except for the thinner gate (tunnel) oxide. Figure
1 compares the flash memory cell to the EPROM cell.
High quality tunnel oxide un?er the' single floati~g
polysilicon gate promotes electncal erasure. All cells m
the array are 'simultaneously erased via FowlerNordheim tunneling. Applying 12V on the sourcejunctions and grounding the select gates erases the entire
array in 'one second (typical). Programming is ac<;om"
plished with the standard EPROM ~~han~sm of hot,
electron injection from the cell dram Junction to the
floating gate. Programming is initi~ted by bringing both
the select gate and the cell drain to high voltage: Prograniming occurs at a rate of 10 p.s pulses per byte.

OXIDE

N+

P-SUBSTRATE

294008-1

Flash Memory Cell

P-SUBSTRA'{E

294008-2

Figure 1:EPROM Cell vs. Flash Memory Cell
/

The, command port consists of a command register,
command decoder;md state l!ltch, the data-in latch;
and the address latch. The command decoder output
directs the operation ()f the high voltage flash-erase
switch, program voltage generator, and the erase/program verify voltage generator.
'
Functions 'are selected via the command port in a microprocessor write cycle controlled by the Chip-Enable
and Write-Enable pins. Contents of the address latch
are updated on the falling edge of Write-Enable. The
rising edge of Write-Enable latches the C()mmand and
data registers, and initiates operations.

3-530

intel .

ER-24

Erasure
Erasure is achieved through a two-step write sequence.
The erase set-up code is written to the command register in the first cycle. The erase confirmation code is
written in the second cycle. The rising edge of this second Write-Enable pulse initiates the erase operation.
The command decoder triggers the high voltage flasherase switch, connecting the 12V supply to the source
of all bits in the array, while all wordlines are grounded. Fowler-Nordheim tunneling results in the simultaneous erasure of all bits.
The array source switch, shown in Figure 3, switches
high ~oltage onto the source junctions. During erasure,
the high voltage latch formed by Ms through Ms enables transistor MIS. Transistor MIS pulls the array
source up to 12V. Transistor MI6 pulls the source to
ground during read and program operations.
To obtain fast erase times, the device must supply the
grounded gate breakdown current which occurs on the
sources of the memory array. The upper boundary for
current sourcing capllbility of MIS is set by the maxi, mum allowable substrate current. If Vpp is raised to
, 12V before Vee is above approximately 1.8V, the low
V<;:c detect circuit formed by transistors M I to ~
dnves the node LOW Vee to 9V. Transistors M9 to
M II then force the erase circuit into a non-erase state
with MIS off and MI6 on. When Vee rises above 1.8V,
the chip' will be reset into the read state.
Writing the erase verify code into the command register
terminates erasure, latches the address of the byte to
verify, and sets the internally-generated erase margin
voltage. The microprocessor then accesses the output
from the addressed byte using standard read timings.
The verify procedure repeats for all addresses. Should a
byte require more time to reach the erased state, another erase operation is applied. The erase and verify operations continue until the entire array is erased.

Programming
Programming follows a similar flow. The program setup command is written to the command register on the
first cycle. The second cycle loads the address and data
latches. The rising· edge of the second Write-Enable
pulse initiates programming by 'applying high voltage to
the gates and drains of the pits to be prograntmed..

3-531

Writing the program verify command .to the register ,
terminates the programming operatiOli and applies the
program verify voltage to the newly prograntmed byte.
Again, the .addressed byte can be read using standard
microprocessor read timings. Should the addressed byte
require more time to reach the prograntmed state, the
programming operation and verification are repeated
until the byte is programmed.

DEVICE RELIABILITY

Cell Margining
Erase and program verification ensure the data retention of the newly altered memory bits. The cell margining performed in the Quick-Pulse Prograntming and
Quick-Erase algorithms is'more reliable than historical
overpulsing schemes as margining tests the amount of
charge stored on the floating gate.
\

Intel's 28F256A through 28F020 Flash Memories employ a unique circuit to internally generate the erase
and program verify voltages. Figure 4 shows a simplified version of the circuit. The circuit consists of a high
voltllge switch and the verify voltage generator. Transistors MI through ~ constitute the high voltage
switch which disconnects Vpp from the resistor when
the device is not in the verify mode. The verify voltage
generator includes a resistor divider and a buffer. Internal margin voltage generation maintains microprocessor compatibility by eliminating the need for external
reference voltages.

Erase/Program Cycling
One of the most significant aspects of Intel Flash Memory is its capability for a minimum of 10,000 erase/program cycles (typical 100,000). Destructive oxide breakdown has been a limiting factor in extended cycling of
thin oxide EEPROMs. Intel's ETOX II nash memory
technology extends cycling performance through: improved tunnel oxide processing, that' increases charge
carrying capability ten-fold; reduced oxide area under
stress minimizing probability of oxide defects in the region; and reduced oxide stress due to a lower peak electric field (lower erase voltage than EEPROM).

ER-24

A typical cell erase/program margin (Vt)is shown as a
function of reprogramming cycles in Figure 5. After
10,000 reprogramming cycles, a 2.5V program read
margin exists, ensuring reliable data retention. Accelerated retention ;'ba..'------.......

Verify Generator

High Voltage Switch

294008-8

Figure 4. Erase/Program Verify Generator

3-533

ER-24

10.5 t-

PROGRAM Vt MAX

9 t-'

-

PROGRAM Vt MIN

7.5 t-

g
~

:>

PROGRAM READ MARGIN
Vee MAX,

6 t-

'-

. Vee MIN
4.5 tERASE Vt MAX

ERASE READ MARGIN

3 tERASE'Vt MIN

1.5 t-

o
10

100
1000
10000
NUMBER OF' CYCLES

100000

1M
294008-7

Figure 5: 1M Array Vt vs Cycles

99.99
99.9

~

'-"

...

99

Q

In

...~
...-'~
...
~
::>

90
50

·0

10

::E

0.1

::>
0

0.01
0.001
0
ERASE Vt (VOLTS)
294008-8

Figure 6. Erase Vt Distribution vs Cycling

3·534

intel~

ER-24

8
7.5
7
6.5
6
5.5
5
4.5
~
a
4
~
;;- 3.5
3
en
..:
IX
2.5
2
1.5
~

..,
..,

..,
en
..:
..,IX
>..:

IX
IX

..:
ERASE CELL Vt VERIFY LEVEL

1

FAST ERASE BIT

0.5
0

ERASE TIME (mS)
294008-9

Figure 7. Array Erase Vt vs Erase Time

3-535

intel .

ER-24

294008-3

Figure 8. 28F256A Die Photograph

3-536

int:el..

ER-24

294008-10

Figure 9. 28F512 Die Photograph

3-537

ER·24

294008-11

Figure 10! 28F010 Ole Photograph

3-538

· intel·

ER·24

294008-12

Figure 11. 28F020 Die Photograph

3·539

intel·

ER-24

Byte-Wide Flash Memory In 32-Pin DIP

/~

...+

~6
~

,...

C
C
+
~5 NC C
Aj2 C
A7 C
As C
As C

256K (32KxB)

Vpp

1

NC

2

32 ::J Vee
31 ::J WE
30 ::J NC
29 ::J Aj4

3

4
5
7
9

A2

10
11

23 ::J Ajo
22 ::J CE

12

21 ::J D~
20 ~DOe
19 ::J 005
lB bDQ4

_I::

DQ2
Vss

f-+

~7

32 PIN DIP 26 ::JAg
0.800" WIDE 25 ::J Aj 1
24 ::J OE
TOP VIEW

A3

DO,

-

2B ~Aj3
27 ::JAs

6

A4C 8

C
C
Aj C
AoC
000 C

~~ ..

~-,

·512K (64Kx B)

13
14
15

C
C 16

17

P DQ3

Figure 12. Flash Memory Pinouts

3-540

294ooB-17

intel~

ER-24

Byte-Wide Flash Memory in 32-Pin PLCC
21.t (2S6K x 8)
1M (128K

x 8)

S12K (64K X 8)
2S6K (32K X 8)

A,2

NC

NC

Vpp

Vee

WE

A,4

A13

As
Ag
A,1

OE
A,o

CE
D~

14

15

16

17

18

19

20

DO,

DQ2

Vss

DQ3

DQ4

DQs

DOs

294008-18

Figure 13. Flash Memory Pinouts

3-541

intet

ER-24

Byte-Wide Flash Memory in 32-Lead TSOP

/

E28F020
E28F010

-'11

-'11

As

As

As
AI'
Au
-'17

A.
-'1,
At,
NC

WE

WE

vee
vpp

vee
vpp

AI,
Als
AI2
A7

-'1,
Ats
AI2
A7

As

As
As

As
A.

'"
Of;

10

31

STANDARD PINOUT
Ole Up "E"
32 LEAD TSOP
8 mm X 20 mm
TOP VIEW

10
11

21

A.

Of;

A10

-'10

CE

CE

DO,
DQ,
Dlls
DQ.
DO,
GND
002
DO,
000

00,
DQ,
DQs
DQ.
DO, '
GND
002
DOl
000

Ao

Ao

AI
A2
A,

At
A2
A,

294008-19

F28F020
F28F010
Of;

Of;

-'10

AIO

CE

CE

00,

00,

00"

00"
00"

DOs
DO. DO.
DO, 00.
GND GND
D02 .D02

\1

0

REVERSE PINOUT
Ole Down "F"
32 LEAD TSOP
8 mm X 20 mm
TOP VIEW

Al1

-'11

As

As

As
A13
AU
NC

As
At,
At.
-'17

WE

WE

vee
vpp

vee
vpp
-'1,
Ats
-'12
A7

00,

00,

DOo

000

Ao

Ao

A16
-'15
AI2
A7

At
A2
A,

At
A2
A,

As

As

As
A.

AS
A.

294008-20

Figure 14. Flash Memory Pinouts

3-542

int'et

ER-24

Columns are number 0 through 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Right Half Array
104 105 106 107
Blo~ Bl3S4

left Half Array
100 101 102 103
- Bl3S4 +- BlO

Array Organization:
Address
A14

A12

0
0
0
0
0
0
0
0

0
0
0
0
0
0
_0
0

1
1
1

1
1
1
1

•

•

1

Bitlines

A2

A1

Ao

0
.0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

o.

1
1
1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

A10

•

•

•

•

A3

1
0
1
0
1
0
1

100& 107

101 & 106

102& 105

103& 104

Bl384
BL385
BL386
BL387
BL388
BL389
BL390
BL391

BL256
BL257
BL258
BL259
BL260
BL261
BL262
BL263

BL128
BL129
BL130
BL131
BL132
BLi33
BL134
BL135

BLo
BL1
BL2
BL3
BL4
BL5
BLs
BL7

BL508
BL509
BL510
BL511

BL380
BL:i81
BL382
BL383

BL252
BL253
BL254
BL255

BL124
BL125
BL126
BL127

•

•

•

•

•

Figure 15. 28F256A Bitline Decoding
Row

X Address
A7

A6

As

A4

A13

A11

Ag

As

Wl

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

XLo
XL1
XL2
XL3
XL4
XL5
XL6
XL7
XL8
XL9
XL10
XL11
XL12
XL13
XL14
XL15

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

XL16
XL17
XL18
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL28
XL29
XL30
XL31

1

1

1
1

, 1
1
1
0
0
0
0
0
0
0
0

Figure 16. 28F256A Wordline Decoding

3-543

int:et

ER-24

Row

X Address

A7

A6

As

A4

A13

. A11

Ag

As

WL

0

0

1

0

0

0

0

0

XL32

0

0

1

1

1

1

XL47

0

0

1

1

1

XL4s

0

•

•

•
1

•

1

1

1

•

•

•

•

•

•••

0

•

1

•

1

0

0

0

0

XL63

0

1

0

0

0

•

•

•

0

XL64

•

0

0

•

1

1

XL79

1

XLSO

•

•

•

0

•

0

1

0

0

0

1

0
0

•

0

1

•

•

1

1

1

1

•

0

0

0

0

XL95

1

1

0

0

0

0

0

XL234

•

•

•

1

1

XL249

1

1

XL250

0

0

XL255

•

1

0

1

1

1

1

1

1

•

•

1

1

•

1

•

0

1

•••

•

1

1

•

1

1

1

•

•••

•

•

1

•

•

•

•

•

•1 .

•

1

•

•

•

0

•

•••
•••
•••

Figure 16. 28F256A Wordline Decoding (Continued)
Bit Map for
Array Organization

R

r---r--'r--'~-,

,---r---r---r--.

o

W

S
E 1/00 1/01 1102 1/03
L
E

L-__L-__L-__

WLO
WL1
WL2·
WL3

•
•

•

1/04 1/05 1/06 1/07

WL252
WL253
WL254
WL255

C
T
S

One Output

L-~

BLO BL 1 BL2 ... BL127

COLUMN SELECTS

Figure 17. 28F256A Bit Map

3-544

infel .

ER-24

Columns are numbered 0 through 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:

A14
A15
0
0
0
I···· 0
0
0
0
0
0
0
0
0
0
0
0
0

•

1
1
1
1

--

•

1
1
1
1

A3
0
--1
0
1
0
1
0
1

.'

Address
A10
0
0
0
0
0
0
0
0

•

0
1
0
1

1
1
1
1

A2
0
0
0
0
0
0
0
0

•

A1
0
~-O--

0
0
1
1
1
1

•

AO
0
O'
1
1
0
0
1
1

•

Left Half Array
Right Half Array
02 03
06 07
00 01
04 05
Bltllnes
100/7
101/06
102/05
103/04
Bl384
Bl256
Bl128
BlO
B[257
Bl385
BL129
Bl1
Bl386
Bl258
Bl130
Bl2
Bl387
Bl259
Bl3
Bl131
Bl260
Bl4
Bl388
Bl132
Bl389
Bl261
Bl133
Bl5
Bl390
Bl262
Bl134
Bl6
Bl391
Bl263
Bl135
Bl7

•

1
1
0
Bl508
1
1
Bl509
0
1
1
1
Bl510
1
1
1
Bl511
Figure 18. 28F512 Bitllne Decoding

•

Bl380
Bl381
Bl382
Bl383

•

Bl252
Bl253
Bl254
Bl255

•

BL124
BL125
BL126
Bl127

X-DECODING: Wordlines are numbered 0 through 511 beginning at the top of the array.

A12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

X Address
A5
A4
A13
A11
0
0
0
0
'0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1.
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
Figure 19. 28F512 Wordline Decoding
3-545

A9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0,
1
1
0
0
1
1
0
0
1
1
0
0

A8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Row
WL
XlO
Xl1
Xl2
Xl3
Xl4
Xl5
Xl6
Xl7
Xl8
Xl9
XL10
Xl11
Xl12
XL13
Xl14
XL15
XL16
XL17
XL18
Xl19
Xl20
Xl21
Xl22
Xl23
Xl24
Xl25
XL26
Xl27
Xl28
Xl29
Xl30
Xl31

intel .

ER-24

X-DECODING: Wordlines are number 0 through 511 beginning at the top of the array.
X Address
A12

A7

A6

0

0

0

•

•

0

0

0

0

0

0

0

0

0

0

0

•
•

•
•

0

0

0

0

•

0

1

•

1
1

•

1

•

A4

A13

A11

A9

A8

WL

1

0

0

0

0

0

XL32

1

1

1

' XL47

1

XL48

•

•

•

1

0

1

1

•

•

•
1

1

0

0

1

•

•

1

0

1

0

•

Row

A5

1

1

•

•

1

1

0

0

0

0

XL63

0

0

0

0

XL64

1

1

1

XL79

1

XL80

•

•

0

•

1

•

1

1

1

•

•

•

•

•

•

•
1

•

•
•

•

•

•
1

0

0

0

0

XL95

•

•

•

•

0

1

0

1

1

1

0

0

0

0

6

XL480

1

1

1

0

1

1

1

1

XL495

1

1

1

1

1

XL496

0

XL511

•
•
1

•

•

•

•

•

1

•

1

1

•

•

•

1

1

•

1

•

•

0

0

0

•
•

•

.'

Figure 19_ 28F512 Wordline Decoding (Continued)
Bitmap for
One Output

Array Organization

R

WLO
WL1
WL2
WL3

°

W

S
E 1100 1/01 1102 1103
L
E
C
T
S

•

•

1/04 1/05 II0a 1/07

•

WL508
WL509
WL510
WL511

~--~--~~~~

Column Selects

BLO BL 1 BL2 ... BL 127
Figure 20. 28F512 Bit Map

3-546

intel .

ER-24

Columns are number 0 thrQugh 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Left Half Array
100 101 102 103
BL384 +- BLo

Array Organization:
Address
A16

A15

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
.0

1
1
1
1

1
1
1
1

1
1
1
1

•

•

Bitllnes

A2

Al

Ao

A3

100& 107

101 & 106

102& 105

103& 104

0
0
O.
0
0
.0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

BL3B4
BL3B5
BL3B6
BL3B7
BL3BB
BL3B9
BL390
BL391

BL256
BL257
BL25B
BL259
BL260
BL261
BL262
BL263

BL12B
BL129
BL130
BL13l
BL132
BL133
BL134
BL135

BLo
BLl
BL2
BL3
B4
BL5
BLs
BL7

1
1
1
1

1
1
1
1

0
0

0

1
1

0

BL50B
BL509
BL5l0
BL5ll

BL3BO
BL3Bl
BL3B2
BL3B3

BL252
BL253 :
BL254
BL255

Al0

•

Right Half Array
104 105 106 107
BLo- BLa84

•

•

1
1
1
1

•

•

•

1
1

•

•

•

BL124
BL125
BL126
BL127

Figure 21. 28F010 Bitline Decoding
X Address

Row
WL

·0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

XLo
XL1
XL2
XL3
XL4
XLs
XLe
XL7
XLB
XL9
XL10
XLll
XL12
XL13
XL14
XL15

1
1
1
1
1
1
1
1

1
1
1
1

1
1

0

0
0

0

1
1

0

0
0

0

1
1

0

0
0

0

1
1

0

0
0

0

A12

A7

A6

A5

A4

A13

All

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0

0
0
0
0
0
0
0
0

0
0
0
0

o·
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Ag

As

A14

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
0
0

Figure 22. 28F010 Wordllne Decoding
3-547

1
1
1.
1
1
1
1

1
1
1
1
1
1
1
1
1

XL16
XL17
XL1B
XL19
XL20
XL2l
XL22
XL23
XL24
XL25
XL26
XL27
XL2B
XL29
XL30
XL3l

intel .

ER-24

X Address
A14

A12

In

A6

0

0

0

0

A5
1 ..

0

0

0

0

•

•
1

0

0

0

O·

1

•
•

•
•

•

•

0

0

0

0

0

0

•

•

0

'.
0

0
1

•

0
0

•

0

1,

•

1

1

1

1

•
1

•
1

·
0

I

0

1

•

.'

Ag

As

WL.

0

0

0

XL32

0

1

1

1

1

XL47

1

1

1

1

1

XL48

•

•

•

•

•

1

0

·0

0

0

XL63

1

0

0

0

0

0

•

•

0

XL64

•

1

XL79

1

XL80

•

•

1

0

0

1

0

1

•
1

1

•

1

1

•

1

•

•

•

•

1

1

•

•

1

1

1·

1

•

•

•

•••

1

1

'1

A11

0

0

1

•

A13

0

•

•

0

A4

•

•

•

Row

•

•

•••

•••

•••

0

1

0

0

0

0

XL95

1

0

0

0

0

0

XL992

1.

1

1

1

XL1007

1

XL1008

0

XL1023

•
1
1

•
1

•

0

1

•
1

•

•

1

•

1

•

1

•

0

•

0

0

•
•

•••

•••

Figure 22. 28F010 Wordllne Decoding (Continued)

Bit Map for
One Output
WLO
WL1.
WL2
WL3

•
•
•

WL1020
WL1021
WL1022
WL1023

COLUMN SELECTS

BLO BL1 BL2 ... BL 127

Figure 23. 28F010 Bit Map

3-548

inteL

ER-24

Columns are number 0 through 511 beginning with the column nearest the X·decoder.
Outputs are grouped as follows:
Left Half Ar.ray
100 101 102 lOa
BL384 ~ BLo

Array Organization:

Right Half Array
104 105 lOs 107
BLo~ BL384
Bltllnes

Address
A1S

A1S

Al0

A2

Al

Ao

A3

100& 107

101 & lOs

102& 105

103& 104

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
O·
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

BL384
BL385
BL386
BL387
BL388
BL389
BL390
BL391

BL256
BL257
BL258
BL259
BL260
BL261
BL262
BL263

BL128
BL129
BL130
BL131
BL132
BL133
BL134
BL135

BLo
BLl
BL2
BL3
BL4
BL5
BL6
BL7

1
1
1

1
1
1
1

1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

BL50B
BL509
BL510
BL511

BL380
BL3Bl
BL3B2
BL383

BL252
BL253
BL254
BL255

BL124
BL125
BL126
BL127

•

~

•

•

•
1

1

•

•

•

•

•

•

•

Figure 24. 28F020 Bitllne Decoding
Row

X Address
A17

A14

A12

A7

As

As

A4

A13

All

Ag

A8

WL

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

XLo
XLl
XL2
XL3
X4
XL5
XLs
XL7
XL8
XL9
XL10
XLll
XL12
XL13
XL14
XL15

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

XL16
XL17
XL18
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL2B
XL29
XL30
XL31

Figure 25. 28F020 Wordline Decoding

3·549

intel~

ER-24

Row

X Address

A17

A11
0

Ag

As

WL

0

A13
0

0

0

XL32

0

1

1

1

1

XL47

1

XL48

A14
0

A12

A7

A6

As

0

0

0

,.

A4

1

0

0

0

0

0

1

0

0

0

0

0

•

•

•

•

0

•

•

•

•

•

1

•

•••

1

0

0

0

0

XL63

0

0

0

XL64

1

1

XL79

1

1

XL80

•

0

0

0

0

0

0

0

1

0

0

0

•

•

•

•

•

•

•

•

1

•

0

•

•

1

•
1

•

1

1

•

0

•

,

•

•

•

•

•••

0

0

1

0

0

0

0

0

1

0

•

•

•

•

•
1

0

0

0

0

XL95

0

0

0

0

0

XL992

•

•

1

XL1007

0

0

0

1

•

0

0

•

1
1

0

0

1

0

1

1

1

1

•
1

1

1

1

•

•
1

1

1

1

1

0

•

•

1

1

•

•

1

1

1

1

•

•

•

1
1

•

1

1

•

•

1

1

1

1

1

•••

1

1

0

0

0

0

XL2016

1

XL2031

1

XL2032

1

•

1

XL1008

•

XL1023

1

1

1
0

1

1

..1
0

1

•

•••

1

•

•

\

0

1

•

1

•

•••

0

•

•

1

•

1

•

1

•

1:

•
1

•

1

•

•

0

•

1

•

1

•

1

•

1

1

1

•••

0

•

1

•

0

•

0

•

1

•

0

1

•
1

•

•

1

•

1

1

1

.1

1

•

•

0

•

0

0

•
•

0

•••
•••
XL2047

Figure 25. 28F020 Wordline Decoding (Continued)
Bit Map for
One Output

Array Organization

R

r---~--'----r~-'

r--~---'----r---'

°

W

S
E 1/00 1/01 1/02 1/03

WLO
WL1
WL2
WL3

•
•

1/04 1/05 I/0s 1/07

L

E
C

•

WL2043
WL2045
WL2046
WL2047

T

S
COLUMN SELECTS

BLO BL 1 BL2 ... BL127

Figure 26. 28F020 Bit Map

3-550

intel·

ENGINEERING
REPORT

ER-26

August 1992

The Intel 28F001BX-T and
28F001BX-B Flash Memories

BRIAN DIPERT
OWEN JUNGROTH
MEMORY COMPONENTS DIVISION

Order Number: 294010-002
3-551

The Intel 28F001BX-T and 28F001BX-B Flash Memories
CONTENTS

PAGE

INTRODUCTION ....................... 3-553
TECHNOLOGY OVERVIEW ........... 3-553
DEVICE ARCHITECTURE ............. 3-554
Write State Machine and
. Command/Status Registers ... : ...... 3-554
Internal Oscillator ...................... 3-555
Supply Voltage Sensing ................ 3-555
Erasure ................................ 3-556

CONTENTS
PAGE
. Programming ........................... 3-557
Power Down ........................... 3-557
DEVICE RELIABILITY ................. 3-558
Cell Margining .......................... 3-558
Erase/Program Cycling ................. 3-559
SUMMARY ............................ 3-559

3-552

infel .

ER-26

INTRODUCTION
Intel's 28FOOIBX ETOXTMII (EPROM tunnel oxide)
flash memories add selective block erasure, an integrated Write State Machine and powerdown capability to
Intel's standard flash memory product line. Flash
memory enhances EPROM non-volatility and ease of
use through electrical erasure and reprogramming. Advances in tunnel oxides and' photolithography have
made it possible to develop a double-polysilicon singletransistor read/write random access nonvolatile memory, capable of greater than 10,000 reprogramming cycles (typically 100,(00). The 28FOO1BX flash memories
electrically erase all bits in a block matrix via electron
tunneling.' The EPROM ,programming mechanism of
hot electron injection is employed for electrical byte
programming.

ing advanced 1.0 ,...m double-polysilicon n-well CMOS
technology, the 131,072 x 8 bit flash memories employ'
a 3.8 ,...m x 4.0 ,...m single transistor cell, affording
equivalent array density as comparable EPROM technology. The flash memory cell structure is identical to
the EPROM structure, except for the thinner gate (tunnel) oxide. Figure 1 compares the flash memory cell to
the EPROM cell.

EPROMCen
SECOND LEVEL
POLYSILICON

+VG

I

~

I

VS

FIRST LEVEL
POLYSILICON
(FLOATING)

+VD
,GATE OXIDE

A cOmmand Register/Status Register interface to a
Write State Machine, internal margin voltage generation, power up/down protection and address/data
latches augment standard EPROM circuitry to optimize Intel's 28F001BX family for microprocessor-controlled reprogramming.

N+
P-SUBSTRATE
294010-1

Flash Memory Cen
Read timing, parameters are equivalent to those of
CMOS EPROMs, EEPROMs and .SRAMs. The 120 ns
access time results from a memory cell current of approximately 50 ,...A, low resistance poly-silicide wordlines" advanced scaled periphery transistors and an optimized data-out buffer.
The dense one-transistor cell structure, coupled with
high array efficiency, yields a one megabit die measur- ,
ing 235 by 268 mils.

SEcoND LEVEL
POLYSILlcoN

+VG

I

~.

I

FIRST LEVEL
POLYSILICON
(FLOATING)

- .........

GATE OXIDE
;.;;.;;;;~~~-

P-SUBSTRATE
294010-2

Figure 1. EPROM Cen vs. Flash Memory Cen

TECHNOLOGY OVERVIEW
,Intel's ETOX II flash memory technology is derived
from its standard CMOS EPROM process base. Us-

'I
I

I

3-553

ER-26

HiglJ. quality tunnel oxide under the' single floating
. polysilicon gate proinotes electrical erasure. All cells of
a given block are sb;nultaneously erased via FowlerNordheim tunneling. Applying 12.V .on the' block
source junctions and grounding the select gates erases a
given block. The intel11al Write State Machine (WSM)
controls the erase algorithm, including block pre-programming before erasure. WSM-controlled erasure, including internal pre-programming, takes 2.1 seconds
typical for each parameter block and the boot block,
block. ,
and 3.8 sec. typical for the

main

Programming is accomplished with the standard
EPROM mechanism of hot electron injection from the
cell drain junction to the floating gate. Programming is
initiated by bringing both the select gate and the cell
drain to high voltage. The internal WSM regulates the

internal program algorithm after the correct command
sequence is written to the 28FOOIBX. Typical program
time is 18 ILs per byte.

DEVICE ARCHITECTURE
Write State Machine and Commandl
Status Registers
Intel's 28FOOIBX flash memories contain an on-chip
Write State Machine that automatically controls erase
and program algorithms, dramatically simplifying user
interface. Figure 2 shows the 28FOOlBX block dia-

gram.

r-~~~~1----~

I+-+...... ___--WE
~

-----0[

1+-.....

L-~~-1~---~~PIro
Vpp

_GND

294010-3

Figure 2. 28F001BX Block Diagram

3-554

infel"

ER-26

The WSM simpifies microprocessor control of the
erase, program, Status Register read/clear, ID read and
array read operations, without the need for additional
control pins or the multiplexing of high voltage with
control functions. The WSM, with its integrated oscillator, performs a majority, of the standard flash memory program and erase algorithms automatically. This
makes system timers no longer necessary and frees the
system to service interrupts or perform other functions
during device erase or program. On-chip address and
data latches minimize system interface logic and free
the system bus. The Write State Machine accepts array
read, ID read and Status Register read and clear commands whenever power is applied to the 28FOOIBX.
High voltage (12V) on Vpp additionally enables successful program and erase.

Figure 3 shows how the oscillator period varies with
temperature and supply voltage. The circuit works for ,
supply voltages outside the normal operating conditions and for military temperatures.
700

Internal Oscillator
The Write State Machine is designed using clocked logic circuits. An on chip ring oscillator generates the
clock signals. The frequency of a standard ring oscillator varies with processing, temperature and supply voltage. The improved design used on the 28FOOIBX mini. mizes these variations.

650

c
0

600

'"

550

~
0-

0:

0

~
....I
....I

500

U

'"

0

The WSM consists of a Command Register, Status
Register, State Machine, oscillator, command decoder,
data latch and address latch. The command decoder
output feeds the State Machine, enabling the high voltage flash-erase switch, 'program voltage generator and
erase/program verify voltage generator.
Functions are selected via the Command Register in a
micro.£!9cessor write cycle controlled by the Chip Enable (CE) and Write Enable (WE) pins. The rising edge
of WE latches the address and data-in registers, and
initiates an operation. Status Register contents are driven to the outputs on the falling edge of CE or Output
Enable (OE), whichever occurs last in the read cycle.

~

-5

450

4.0

4.5

5.0

5.5

6.0

6.5

Vee (Volts)

294010-4

Figure 3. Internal Oscillator Frequency
vs Supply Voltage and Temperature

Supply Voltage Sensing
The circuit that generates LOWVcc and LOWVpp is
shown in Figure 4. Power supply voltages Vee and
Vpp are divided down and compared to it reference
voltage. If the reference voltage is greater than the divided power supply voltage, the LOWVcc or
LOWVpp signal will be pulled high. The VREF level
generated by the voltage reference is independent of the
supply voltage to the first order.

The switching current of each stage in the ring oscillator is set by a current reference. This reference current
varies linearly with Vee. The trip point of each ring
oscillator inverter also varies linearly with Vee. These
two effects essentially cancel each other out and the
resulting oscillator period is proportional to RC, with
only a small dependence on Vee.

LOW Vee

LOW Vpp

The value of R is set by an on chip resistor. The value
of C is set by the gate capacitance of the inverters in the
ring oscillator. Process variations in the values are reduced by trimming the period of each oscillator during
manufacturing. The resistor is the only source of temperature variation.

3-555

294010-5

Figure 4. Low Power Detector Circuit

intel-

ER-26

The poSitive power supply to the circuit is provided by
MI and M2. The source of MI and M2 will be pulled
up to the maximum of (VPP-VTN) and (VCC-VTW).
VTN is the threshold of an implanted N channel device,
about O.9V. VTW is the threshold of a native N channel
device, about OV. This scheme ensures that the circuit
will work regardless of the applied supply voltages.

block. The address is latched and dec.oded internally by
the 28FOOIBX, and erase of the desired block is subsequently enabled. The rising edge of this. second WE
.Dulse initiates the erase operation. The boot·block will
~ot erase unless the PWD or OE signal is brought to
high voltage VHH.

The LO'YVcc signal not only goes to the erase circuits,
but also to the programming circuits and to the control
logic to prevent any accidental writes to the array. The
LOWVpp signal goes to the Write State Machine. If
Vpp is detected.as being low during a write, .the low
V~p bit will be set in the Status Register.

Erasure
Erasure is achieved ihrough a two-step write sequence.
The erase setup code is written to the Command Register in the first cycle. The erase confirm <;ode is written
in t!te second cycle., The block to be erased is specified
by writing both commands to any address within the

LOW Vee

The State Machine triggers the high voltage flash-erase
switch, connecting the 12V supply to the source. of all
bits in the specified block, while all wordlines are
grounded. The organization of the block source
switches is shown in Figure 5. Fowler-Nordheim tunneling results in the simultaneous erasure of all bits in
the addressed block.
T~e block source switch controls the. source voltage of
the bits in a particular block. This circuit is shown in
Figure 6. During erase, M2 is off and MI pulls the
source to Vpp. When not in erase, MI is off and M2
pulls the source to ground. The high voltage latch
formed by M4-M7 converts the low voltage ERASE
signal to a high voltage signal that turns MI off or on.

>------------.,
BLOCK
SELECT
LATCHES
AND.
DECODERS

PARAMETER 1
SOURCE

ERASEBB

HIGH
VOLTAGE
DETECTORS

MAIN BLOCK
SOURCE

PARAMETER 2
SOURCE
BOOT BLOCK
SOURCE

LOCK
OUT
LOGIC

294010-6

Figure 5. Array Erase Blocking

3-556

intel .

ER·26

lotI

_ _ _...-.. BLOCK
SOURCE
LOW Vee >--;j~--------+---'"

EAASE>-------~----------~~~ ~~------~

294010-7

Figure 6. Block Source Switch
The tunneling that occurs during erase requires only a
small amount of current. However, the grounded gate
initial erase current that occurs on the source of every
bit in the array is large: :M:l is made large enough to
supply this current and still keep the voltage on the
source high enough for fast erase time.

ed verify voltage) continue until .the byte is programmed. System software, polling the Status Register,
is informed of programming state thru specific status
bits.

Power Down
The LOWVee signal protects the array from being
erased when Vpp is at a high voltage but Vee is a low
voltage. When this occurs, M3will pull the block
source to ground. The high voltage latch will be forced
into the state that turns MI off by M8.
After receiving the erase command sequence, the WSM
automatically controls block precondition (program-'
ming of all bytes to DOH within the chosen block), erase
pulses and pulse repetition, timeout delays and byte-bybyte verification of all block addresses using the internally-generated erase margin voltage. The internal
erase and verify operations continue until the entire
block is era~ed. System software need only poll the
Status Register to determine when the WSM has successfully completed the erase algorithm.

Programming
Programming follows a similar flow. The program setup command is written to the Command Register on
the first cycle. The second cycle loads the address and
data latches. The rising edge of the second WE pulse
initiates programming by applying high voltage to the
gates and drains of the bits to be programmed.
As with erasure, the WSM controls program pulses and
pulse repetition, timeout delays and byte verification.
Program and program verify (at th~ internally-generat-

The 28FDOIBX has a deep power down mode that reduces lee and Ipp ~ically 0.05 p.A and 0.8 p.A,
respectively. When PWD is low~ the part is in deep
'power down mode. When PWD is high, the part can be
placed in an active or standby mode by state of the CE
·pin.
The deep power down mode is similar' to the standby
mode except that more circuits are turned off. This
means that much less power is consumed; it also means
that it takes longer for the part to transition into the
-active mode.
'
A diagram of the power down circuit is shown in Figure 7. The TTL buffer formed by Ml-M3 enables the
low power detect circuits, the redundancy address flash
bits and the CE TTL buffer formed by M4-M6. In
previous Intel flash chips these circuits were always enabled. The time for these circuits to tum on determines'
the PWD access time and write specifications.
PWD will function properly with TTL level inputs.
However, to get the lowest possible power consumption, full CMOS levels should be used. If voltage on the
gate of M3 raises above its threshold voltage of 0.9V, it
will tum on arid draw current. Input voltages in the
0.7-0.9 range could cause enough subthreShold conduction in M3 to exceed the deep power down current
specification. This is why the input voltage for PWD is
specified as GND ±0.2V.

3-557

\'

infel"

ER-26

DEVICE RELIABILITY
~
U""pnininn
........
_ II
.......
1::1 ...... =:1

NI

LOW POWER
DETECT
REDUNDANCY

N2

N3

.>4;)---1

TO THE REST
Of
THE CHIP

Erase and program verification ensure the data retention of the newly altered memory bits. The cell margining performed by the WSM during the verify phase of
the automated algorithms is more reliable than historical EEPROM schemes, as margining tests the amount
of charge stored on the floating gate.
Intel's 28FOOlBX flash memories employ a unique circuit to internally generate the erase and program verify
voltages. Figure 8 shows a simplified version of the circuit. The circuit consists of a high voltage switch and
the verify voltage generator. Transistors Ml through
M4 constitute the high voltage switch which disconnects Vpp from the resistor when the device is not in
the verify mode. The verify voltage generator includes a
resistor divider and a buffer. Internal margin voltage
generation maintains microprocessor compatibility by
eliminating the need for external reference voltages.

294010-8

Figure 7. Power Down Circuits

.------------------~-----~---------------

VERifY
VOLTAGE

ENABLE

,I

VERifY GENERATOR

HIGH VOLTAGE SWITCH

.---------~--------------~----------------.
Figure 8. Erase/Program Verify Generator

3-558

294010-9

infel .

ER·26

Erase/Program Cycling
One of the most significant aspects of 28FOOIBX flash
memories is their capability for a minimum of 10,000
erase/program cycles (typically 100,000 per block). Destructive oxide breakdown has been a limiting factor in
extended cycling of thin oxide EEPROMs. Intel's
ETOX II flas~ memory technology extends cycling performance, through:
• Improved tunnel oxide processing that increases
charge carrying capability tenfold;
• Reduced oxide area under stress minimizing probability of oxide defects in the region; and
• Reduced oxide stress due to a lower peak electric
fieId (lower erase voltage than EEPROM).
A typical cell erase/program margin 01V is shown as a
function of reprogramming cycles in Figure 9. After
10,000 reprograming cycles, a 2.5V program read margin exists, ensuring reliable data retention. Accelerated
retention bake experiments, for devices cycled 10,000
times, show minimal program Vt shift.

10.5
9.0

Reliable erase/program cycling also requires proper selection of the erase Vt maximum and maintenance of a
tight Vt distribution. The maximum erased Vt is Set to
3.2V via the internal erase algorithm and erase verify
circuits. Superior oxide quality gives an erased Vt dis~
tribution width that improves slightly with cycling
(Figure 10). The tight erase Vt distribution gives ari
order of magnitude of erase time margin to the fastest
erasing cell.
.

SUMMARY
Intel's ETOX II flash memory technology is a breakthrough in adding electrical chip-erasure to high-density EPROM technology. Intel's 28FOOIBX family enhances Intel's standard flash memory line by adding
block erase capability, Write State Machine-controlled
program and erase and deep powerdown mode. Micro~
processor-compatible specifications, straightforward interfacing and in-circuit selective alterability using simple software command sequences allow designers to
easily augment memory flexibility and satisfy the need
for nonvolatile storage in today's designs.

l-

PROGRAMVt MAX

I--

lI-

-

I--

PROGRAM Vt MIN

I-'lI--

7.5
".....,

>
........

>'

6.0

li-- '

I--

PROGRAM READ MARGIN

lI-

Vee 'MAX

I--

l-

I-

4.5

Vee MIN

l-

I-"-

ERASE READ MARGIN

I--

3.0

ERASE Vt MAX

lt-"
;-

-

1.5

~

-

0.0

ERASE Vt MIN

''--

I-- .

I

I

I

I

I

I

I

10

100

1000

10000

100000

1M

NUMBER OF" CYCLES
294010-11

Figure 9. Block Vt vs Cycles

,.
3-559

infel .

ER·26

99.99
........

~
.......
c

99.9
99

I.&J

(I)

<1:

c:::
I.&J

(I)

90
50

..J
..J
I.&J
(.)

10

I.&J

1.0

<1:

0.1

>
j:::

ERASE Vt·

@

1 CYCLES

..J
;:)

:::::;:
;:)
(.)

0.01
0.001
0.0
1.5

1.75

2.0

2.25

2.5

2.75

3.0

3.25

ERASE Vt (V)

294010-10

Figure 10. Erase Vt Distribution vs Cycling

7.5
6.5
6

5.5

iu
>' 3.5
w

a

3

2.5
2
1.5
0.5

fOOO

2000

3000

4000

ERASE TIME (mS)

Figure 11. Block Erase Vt vs Erase Time

3-560

5000

294010-25

ER-26

294010-15

Figure 12. 28F001BX Die Photograph

3-561

ER·26

Pin Names
vpp

vee·

-'16

WE

-'Is

Ao-AI6
000"':OQ7

Address Inputs

eE

Chip Enable

Daia Inputs/Outputs

-'12

-'I ..

J5WI)

Power Down

~

-'13

OE

Output Enable

As
As

As

~

Write Enable

Ag

Vpp

Program/Erase Power Supply

A..

-'II

Device Power Supply

A3
.A2

FE

Vee
GNO

Ground

-'10

DO,

FE
IX?
DOs
DOs

D02
GND

DQ3

-'I

Ao
DOo

oa.
294010-12

~

-'13
-'I ..
PWD

WE

Vee
Vpp
-'16

A,s

~As

As

A4

1
2
3
4
5
6
7
8
9
10
11
12 .
13
14
15
16

32
31
30
29
28

O.
E2S'FOO rBX
3.2 LEAD TSOP
Smm X .20mm
TOP VIEW

27
26
25
24
23
22
21
20
19
18

17

DE
-'10
CE

~
DOs

Do..
D%

GND
D~

DO,

DOo

~A2
A3

294010-13

Figure 13. 28F001BX Pinout Configurations

.~

A4
A3
A2

A,4

0

As
As

A,3
As
N28F001BX
32 LEAD PLCC
0.450" x 0.550"
TOP VIEW

Ag
A,1

FE

AI

A,o

Ao

FE
IX?

DOo

g g'

~

gg" 'l

~

294010-14

Figure 14. 28FOO1BX Pinout Configurations
3-562

ER-26

Columns are number 0 through 511 beginning with the column nearest the X-decoder. Outputs are grouped as
follows:
Right Half Array
104 105 lOs 107
BLs4- BLs11

Left Half Array
100 101 102 103
BLs11- BLs4

Array Organization
(Main Block):
Address

Bitllnes
' 102& 105

A16

A1S

A14

A13

A12

A1

Ao

100& 107

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0

0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

B400
B401
B402
B403
B404
Bl40S
Bl406
Bl407

Bl2BB
Bl2B9
Bl290
Bl291
Bl292
Bl293
' Bl294
Bl29S

Bl17S
Blm
BL178
BL179
Bl180
Bl1B1
Bl1B2
Bl1B3

BLe4
BLes
BLes
BLe7
Bl6B
BlB9
Bl70 ,
Bl71

1
1
1
1

1
1
,1
1

0
0
0
0

1
1
1
,1

1
1
1
1

0
0

0
1
0
1

BlsOB
Bls09
Bls10
BlS11

Bl396
Bl397
Bl39B
Bl399

Bl2B4
Bl2BS
Bl286
Bl287

Bl172
Bl173
Bl174
Bl17S

•

•

•

•

•

•

1
1

•

101 & lOs

•

•

103& 104

•

•

Figure 15. Bitline Decoding (Main BloCIc, 28F001BX-T)
,

Array Organization
(Parameter Block 1):

Right Half Array
100-107
BLo- BL31
Bitllnes

Address
A16

A1S

A14

A13

1
1
1
1

1
1

1

1

1
1

0
0
0
0

1

1

A12

A1

Ao

100

0
0
0
0

0
0
1

0
1
0

1

1

Blo
Bl1
Bl2
BLa

101

102

103

104

105

lOs

107

Bl4
Bls
Bl6
Bl7

Bl8
Bl9
Bl10
Bl11

BL12
Bl13
Bl14
Bl1S

Bl16
Bl17
Bl18
Bl19

BL20
BL21
Bl22
BL23

Bl24
Bl2S
Bl26
.Bl27

Bl28
Bl29
Bl30
Bl31

.Figure 16. Bitline Decoding (Parameter Block 1, 28F001BX-T)

Array Organization
(Parameter Block 2):

Right Half Array
100-107
BL32- BLs3

Address

Bitlines

A1S

A1S

'A14

A13

A12

A1

Ao

100

101

102

103

104

105

lOs

107

1
1
1
1

1

1
1
1
1

0
0
0
0

1
1
1
1

0
0

0
1

1
1

0
1

Bl32
Bl33
BLa4
Bl3S

Bl36
Bl37
Bl38
Bl39

B40
Bl41
Bl42
B43

Bl44
Bl4S
B46
Bl47

B48
Bl49
Blso
Bls1

Bls2
Bls3
Bls4
Blss

Bls6
Bls7
Bls8
Bls9

BLeo
BLe1
BLe2
Bl63

1
1
1

Figure 17. Bitline Decoding (Parameter Block 2, 28F001BX-T)
NOTES:,

.

1. Bitline decoding listed is for 28F001BX-T. To convert to 28F001BX-B. invert polarity of
becomes 1 1 1 1 1 0 0 ) . '

3-563

add~esses

.

A1S-A12 (i.e. 0000000

ER~26

Left Half Array
107-100
BLa-Bl&3

Array Organization
(Boot Block):

Address

Bitlines

A1&

A1S

A14

A13

A12

A1

Ao

107

10&

105

104

103

102

101

100

1
1
1

1
1
.1
1
1
1
1

1

1
'1
1
1
1

0 ,
0
'0
0
1

0
0
1.

0

BLo
BLl
BL2
BLa
B4_
BL5
BL6
BL7

BLa
BL9
BL10
BLll
BL12
BL13
BL14
BL15

BL16
BL17
BL18
BI.:19
BL20
BL21
BL22
BL23

BLM
BL25
BL26
BL27
BL28
BL29
BL30
BLal

BL32
BL33
BLa4
BL35
BLa6
BL37
BLa8
BL39

B40
B41
B42
B43
B44
B45
B46
B47

B48
B49
BL50
BL51
BL52
BL53
BL54
BL55

BL56
BL57
Bl58
BL59
BLso
BL61
BLa2
BLss

1
1
1
1
1

1
1
1
1
1
1
1 .

1

1

1
1
1

1
1

1

0

1

1

0
0

0

1
1

0
1

1

Figure 18. BltUne Decoding (Boot Block, 28F001BX-T)
.NOTE:
1. Bitline decoding listed is for 28F001BX·T. To convert to 28F001BX·B, invert polarity of addresses A16-A12 (i.e. 0000000
, becomes 1111100).

Row

XAddress •
A11

A10

Ag

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.
0
0
0
0
0
0
0

0
0
0
0

0.
0.
'0.

0.

0
0
0
0
0
0'
0
0
0
0
0.
0
0.
0.
0
0.
0
0
0
0.
0
0
0.
0
·0
0,
0,
0
0
0
0
0

0
0.

0
0
0
0
0

0.

0
0
0
0
0
0
0
0
0
0
0.
0.

0.
0
0.
0.
0.
0.
0
0
0
0
0

o.
0
0

:

As

Ai

A&

A5

A4

,A3

A2

WL

0
0
0
0
0
0
0
0
0
0
0.
0
0.
0.
0
,0.

0
0
0,
0

0
0
0
0

0
0
0
0
0
0
0
0
1
1

0
0
1
1
0
0
1

0
1
0,
1
0

XLo
XLt
XL2
XLa
X4
XL5
XL6
XL7
XLa
XL9
XL10
XLl1
XL 12
XL1S
_XL14
XL15

1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1

1

1

1

0.
0
0
0

0.

0.
0
0
0
0
0
,0.
0
0.
0.
0
0.
1

0
0.
0
0
0
0.
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0.
.0
0
0
0.
0
0
0.
0
0
0
0
0
0
0
0
0
00

0.

0.

0.
0.

1

1
1
1
1
1

1

1

1
1
1
1
1

1
1
1

1
1
1

0.
0
0.

1
1
1

1

0.
0
0.
0
0.

1
0
0
0
0

1

1
1

1

.

1

0
0
1

1
0.
0
1
1
1

1
0
0.

1

0

1

1

1
0
0

0

1
1

0
0
1
1
0
0

Figure 19. Wordline Decoding (28F001BX~T and 28F001BX-B)

3-564

1

0
1
0
1
0
1
0
1
0
1
1'
0

1

0
1

0
1
0.
1

0
1'
0

XL16
XL17
XL18
XL19
XL20
XL21
XL22
XL2S
XL24
XL25
XL26 .
XL27
XL28
XL29
XLao
XLSl .

infel .

ER-26

X Address

Row

A11

A10

Ag

As

A7

As

As

A4

A3

A2

WL

0

0

0

0

1

0

0

0

0

0

XL32

0

0

0

0

1

0

1

1

1

1

X47

0

0

0

0

1

1

1

1

1

1

X4a

0

0

0

0

1

1

0

0

0

0

XLe3

0

0

0

1

0

•

•

•

•

•

•

•

I

•

•
•
•

•
•

•

•

•

•

•

•

•

•

•

•••
•••

•

0

•

0

0

0

0

XLe4

*

•

•

•

•••

•

0

0

0

1

0

0

1

1

1

1

XL79

0

0

0

•

.

•

•

1

•

0

1

1

1

1

1

XLao

*

•

•

•

•

•

•

•••

0

0

0

1

0

1

0

0

0

0

XL9S

1

1

1

1

1

0

0

•

..

0

0

0

XL992

1

1

1

1

1

0

1

1

1

1

XL1007

1

1

1

1

1

1

1

1

1

1

XL100a

1

1

1

1

1

1

0

0

0

0

XL1023

.

•

•

•

•

•

•
•

•

•

•

•

•

•

•

•

•

•••

•

•••

Figure 19.Wordline Decoding (28F001BX-Tand 28F001BX-B) (Continued)

Array Organization

..

~w

!

en

Main
Bloqk

~

100

...I

0

Main
Block
101

Main
Block
102

Main
Boot
Block . Block
103
100-7

Param Param
1 Block 2 Block
100-7 100-7

Main
Block
104

Main
Block

Main
Block

Main
Block

105

106

107

a::
COLU~N

SELECTS

Figure 20. Array Organization

REVISION HISTORY
Number

Description

002

Swapped Figures 9 and 10
Added Figure 11

3-565

intel·

ER-27

ENGINEERING
. REPORT

November 1992

The Intel· 28F008SA
Flash Memory

ALAN BUCHECKER
JERRY KREIFELS
MEMORY COMPONENTS DIVISION,

Order Number: 294011-001

3-566

The Intel 28F008SA Flash Memory
CONTENTS

PAGE

INTRODUCTION ....................... 3-568
TECHNOLOGY OVERVIEW ........... 3-568
DEVICE ARCHITECTURE ............. 3-569
Array Organization ..................... 3-569
Write/Erase Automation ................ 3-569
Command User Interface (CUI) ......... 3-570
Write State Machine (WSM) ............. 3-570
Status Register ......................... 3-571
Ready/Busy Indication (RY /BY) ........ 3-571
Internal Oscillator ...................... 3-571
Supply Voltage Sensing ................ 3-571
Power Down ........................... 3-572
Block Erase ............................ 3-573
Erase Suspend/Resume .. ~ ............ 3-574
Byte Write .............................. 3-574

CONTENTS

PAGE

DEVICE CHARACTERiZATION ........ 3-575
AC and DC Parameters .... ; ............ 3-575
Energy/Power Consumption ............ 3-575
Byte-Write/Block-Erase Times ......... 3-575

DEVICE RELIABILITY ................. 3-575
Byte-Write/Block-Erase Cycling ........ 3-575
Data Protection ........................ 3-576
SUMMARY ............................ 3-576
OTHER REFERENCES ................ 3-576
SUPPLEMENTARY INFORMATION ... 3-577

3-567

intel..

ER·27

INTRODUCTION

TECHNOLOGY OVERVIEW

The ETOXTM-III (EPROM tunnel oxide) 28F008SA is
a high-density product offering from Intel's second generation of flash memory devices. This 1,048,576 x 8
memory with its symmetrical blocking (16 blocks x
64 Kbytes), very high cycling endurance, on-chip
write/erase automation, and erase-suspend/resume capability can be termed a block-alterable non-volatile
RAM. In addition to selective block erasure, integrated
Command User Interface (CUI), Write State Machine
(WSM), Status Register, and deep power-down capability, the 28F008SA adds a dedicated READY/BUSY
output (RY/BY). This new feature provides immediate
hardware signaling of byte-writelblock-erase completion and erase-suspend/resume actuation.

Intel's ETOX-III flash memory technology incorporates advances from ETOX-I fu,d ETOX-II processes

and leverages over two decades of EPROM manufacturing experience. Using advanced 0.8 p-m double-polysilicon N-well/P-well CMOS technology, the 1,048,576
x 8-bit flash memory employs a 2.5 p-m x 2.9 p-m single-transistor cell affording array density equivalent to
comparable EPROM technology, and twice that of Intel's ETOX-II process. The ETOX-III flash memory
cell is identical to EPROM, with an additional source
implant which optimizes erase performance. Figure I
shows a cross-section of the flash memory cell.

Flash memories combine inherent non-volatility with
in-system alterability of device contents. Advances in
process control have allowed development of a doublepolysilicon single-transistor flash memory capable of
100,000 write/erase cycles per block. The 28F008SA
electrically erases all bits in a block via electron tunneling. The EPROM programming mechanism of hotelectron injection is employed for high-performance
electrical byte write as required for file and data storage
applications.

High-quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells
within the selected block are simultaneously erased via
Fowler-Nordheim tunneling. Applying 12V to block
source junctions and grounding the select gates erases
all cells within that block. The. internal WSM controls
the automated block-erase algorithm, including preerase conditioning (i.e., pre-programming all block bits)
and margin verification, in response to user requests
relayed by the CUI. WSM-controlled block erasure, including pre-programming, typically requires 1.6 seconds.

The Command User Interface and Status Register interface to power-up/down protection, address/data
latches, and the Write State Machine (which in tum
controls internal byte write, block erase, cell-margin
circuits, and the dedicated READY/BUSY status output). These features augment prior flash memory circuitry to optimize Intel's 28F008SA for microprocessor-controlled byte write and block erase.

Byte write is accomplished with the standard EPROM
mechanism of channel hot-electron injection from the
cell drain junction to the floating gate. Bringing both
the select gate and the cell drain to high voltage initiates programming. The WSM regulates .the internal
byte-write algorithm, including margin verification, after the correct command sequence is written and decoded. Byte write typically requires 9 p-s.

Read timing parameters are comparable to those of
CMOS DRAMs, SRAMs, EPROMs, and EEPROMs.
The 85 ns access time results from a memory cell-current of approximately 70 p-A, low-resistance polysilicide wordlines strapped with metal, advanced scaled
periphery transistors, and an optimized data-out buffer.
The dense one-transistor cell structure, coupled with
high array efficiency, yields a one-megabyte die measuring 539 by 286 mils.

SECOND LEVEL
POL YSILICON

+VG

~

I

VS

r

FIRST LEVEL
POLYSILICON
(FLOATING)
+VD
GATE OXIDE

N+

294011-1

Figure 1. Flash Memory Cell

3-568

inteL

ER-27

Addresses A9-Ao select one of 1024 rows. while A19
selects upper or lower decoder. Row address lines are
decoded sequentially for selection. Row address bitmaps are listed in Table 3.

DEVICE ARCHITECTURE
Array Organization
The 28FOO8SA is a 1,048,576 x 8 memory comprised of
2048 rows by 8192 columns. Array layout is segmented
as four quadrants, each 1024 rows by 2048 columns.
Access time is reduced by limiting column length to
1024 cells. The polysilicon row is strapped in metal
every 512 columns to reduce wordline delay. Two row
decoders run vertically between quadrants, and column
decoders run horizontally between quadrants: Figure 2
shows block placement and array organization. A die
photo of the chip is shown in Figure 30.

Columns are numbered 0-8191 from left to right, top
to bottom. Addresses A19-A16 select one of 16 blocks,
while A1S-AIO select eight of the 512 columns within
that block. These ten address lines are also decoded
sequentially to access all 8192 columns. Block address
bitmaps are listed in Table 4; column address bitmaps
are listed in Table 5.

Each quadrant is subdivided into four 64-Kbyte blocks.
Each block source is electrically isolated from the
source of other blocks. This allows individual block
erase without altering data in the remaining IS blocks.

Intel's 28FOO8SA contains an on-chip Command User
Interface, Write State Machine, Status Register, and
address/data latches to dramatically simplify user interface. This combination of functional U11its reduces
microprocessor control complexity of byte-write, blockerase, erase-suspend/resume, Status Register read/
clear, ID read, and array read operations. Figure 3
shows the 28FOO8SA block diagram.

Write/Erase Automation

Each block is further subdivided into eight Input/Outputs. Data for 1/00 is stored in the left-most 64 columns, with the next 64 storing data for I/O\> etc.
Rows in the upper quadrants are iiumbered 0-1023
from top to bottom; lower quadrant rows similarly
1024-2047.

BLOCK 0
00000OFFFF

BLOCK 1
100001FFFF

BLOCK 2
200002FFFF

BLOCK 3
300.003FFFF

...'"c

BLOCK 4·

BLOCK 5

BLOCK S

BLOCK 7

c

400004FFFF

500005FFFF

60000SFFFF

700007FFFF

§
~

'"
COLUMN DECODER

COLUMN DECODER

BLOCK 8

BLOCK 9

BLOCK 10

BLOCK 11

800008FFFF

900009FFFF

AOOOOAFFFF

BOOOOBFFFF

'"...c
§
c

~

BLOCK 12

BLOCK 13

BLOCK 14

BLOCK 15

COOOOCFFFF

00000DFFFF

EOOOOEFFFF

FOOOOFFFFF

'"
294011-2

Figure 2. 28F008SA Block Placement and Array Organization

3-569

intel~

ER·27

Command User Interface (CUI)
The CUI consists of a command decoder and command
register. User requests are decoded and lakhed in a
microprocessor write cycle controlled by Chip Enabie
(CE) and Write Enable (WE). Status Register read/
clear, ID read, and array read commands are directly
handled by the CUI. The. CUI also accepts byte-write,
block-erase, and erase-suspend/resume commands.
WE's rising edge latches address, command and data-in
registers, and requests WSM initiation of the selected
operation. These on-chip address, command, and data
latches controlled by the CUI minimize system interface logic, and free the system bus.

Write State Machine (WSM)
The WSM processes byte-write, block-erase, and erasesuspend/resume requests received from the CUI. The
WSM rejects byte-write and block-erase requests if the
WSM is currently busy, if Vpp is not at high voltage
(I2V), or if the Low Vpp Status Register flag is set (Le.,
not cleared from a previous low-voltage condition).

The WSM consists of an integrated oscillator and control circuitry. It generates signals which control the
by te-write, block-erase, erase-suspend/resume, and verify circuits. It also receives feedback from these circuits
aiiowing Status Register update. The. WSM and associated circuits perform the equivalent of first-generation
flash memory program and bulk-erase algorithms automatically. This eliminates the need for system timers,
and frees the microprocessor to service interrupts or
perform other functions during device byte-write or
block-erase operatiC:)-";"'-I

TO THE REST
OF
THE CHIP

294011-5

Figure 5. Power-Down Circuits

infel"

Figure 6. Array Erase Blocking

Block Erase
Block erasure is achieved by a two·step write sequence.
The erase-setup code is written to the CUI in the first
cycle. Erase confirm is written in the second cycle. The
address supplied with the erase-confirm command is
latched and decoded internally by the 28FOO8SA; erase
is subsequently enabled in that block. The second WE
rising edge initiates the operation (WE-controlled
write).
The WSM triggers the high-voltage flash-erase switch
connecting the 12V supply to the source of all bits in
the specified block, while all wordlines are grounded.
Figure 6 shows organization of the block source
switches. Fowler-Nordheim tunneling results in simultaneous erasure of all bits in the selected block.
The block source switch controls the source voltage of
all bits in a particular block. This circuit is shown in
Figure 7. During block erase, M2 is off and Ml pulls
the source to Vpp. When not in erase, M 1 is off and M2

pulls the source to ground. The high-voltage latch
formed by M4-M7 converts the low-voltage ERASE
signal toa high-voltage signal that controls Ml.
The tunneling that occurs during block erase requires
only a small amount of current. However, the initial
current required to charge the block's large source capacitance to the erase voltage is significant. Ml is sized
to limit this current yet still apply sufficient source voltage to achieve fast block-erase time.
The LOWVee signal protects the array from erasure
when Vpp is at a high voltage but Vee is below the
write/erase lockout voltage (VLKO). When this occurs,
M3 pulls the block source to ground. The high-voltage
latch is forced by M8 into the state that turns M 1 off.
Vpp is continually monitored during all phases of the
block-erase operation. If Vpp falls below the trip point
of its high-voltage detect circuitry, erasure will not ocC
cur (or halts) and Status Register Vpp status (SR.3),
block-erase status (SR.5) and WSM status (SR.7) bits
are set to "I".

t.ll

r-----t-+
LOW

BLOCK
SOURCE

vee ~...---------'---~

ERASE ~----------4I--I ~>O"""----I

294011-7

Figure 7. Block Source Switch
3-573

ER·27

If SR.3 (Low Vpp) is set, WSM operation is inhibited.
The WSM will not execute further byte-write or blockerasure sequences until the Status Register has been
reset by system software. Byte-write or block-erase requests with error flags SR.4or SR.S set are not inhibited, but the system loses the ability to determine ,success.
The clear Status Register command resets these bits.
After receiving the block-erase command sequence, the
WSM automatically controls block pre-condition (programming all bytes to OOH within the chosen block),
erase pulses and pulse repetition, timeout delays, and
byte-by-byte verification of all block addresses (sequentially checked via the address counter) using an alternative sensing reference to verify margin. The internal
erase and verify operations continue until the entire
block is erased~ A read cycle applied to the part following the, block-erase command sequence outputs Status
Register contents; system software can poll the Status
Register to determine when block erase is complete,
and if it was successful. Alternately, the system can
monitor RY/BY until that output is driven high, and
then poll the Status Register to determine success. Following block erasure, the device remains in Status Register read mode; a read-array command must be written
to the device to access array data.
If the erase-setup command is followed 'with a command other than erase conf1l'm, the' device will not
erase. The WSM sets both byte-write status arid blockerase status bits in the Status Register to indicate an
invalid sequence.

,Erase Suspend/Resume
Erase suspend allows the system to interrupt block
erase to read data from another array block. The ability
to suspend erase and read data from another block offers the flexibility required for file system applications.
Upon receiving the erase-suspend command, the CUI
requests that the WSM pause at one of several. predetermined points in the algorithm. Upon reaching a sus-,
pend point, the WSM sets SR.6 (erase-suspend status)
and SR.7 to "I", and drives the RY/BY pin high. The
system must poll the Status Register to determine if the
suspend has been processed or the block erase bas actually eompleted. Block-erase completion is indicated by
SR.6 cleared to "0" and SR.7 set to "I". Read bus
cycles default to Status Register read after issuing the
erase-suspend command.

Once suspended, the WSM asserts a signal to the CUI
which allows response to the read-array, read-status,
and erase-resume commands. The system can write the
read-array command allowing read access to blocks
oth~ than that which is suspended. The WSM continues to run idling in a suspended state, regardless of all
control inputs except PWD. PWD driven low immediately shuts down.... the WSM, aborting the suspended
erase operation. .
The erase-resume command must be issued upon completion of reads from other array blocks to continue
block-erase operation. The WSM then clears SR.6 and
SR.7, drives RY/BY low, and resumes erase operation
from the suspension point. Read cycles following the
erase-resume command output Status Register data.

Byte Write
Byte write follows a flow similar to block erase. The
byte-write setup command is first writ~en to the CUI. A
second write cycle loads address and data latches. The
rising edge of the second WE' pulse requests that the
WSM initiate activity, applying high voltage to the
gates and drains of all bits to be written. Unlike block
erase, byte write will proceed regardless of what data is
applied on the second CUI write cycle; however, applying data FFH does not modify memory contents.
Like block erase, ,the WSM controls program pulses
and pulse repetition, timeout delays and byte verification. Byte write and verify (with alternate sensing reference and internally-generated verify voltage) continue
until the byte is written. Internal byte-write verify
checks that all bits written to zero have been correctly
modified; it does not check bits specified as one. Byte
write cannot change existing zeros to ones; this can
only be aCcomplished by erase.
Read bus cycles following byte write operations output
Status Register data. System software, polling the
Status Register, is informed of status through bits SR.3,
SR.4,and SR.7. The RY/BY outputean also be monitored to determine' completion. The read-array command must be wntten to the CUI following byte write
to access array data.
In a scenario similar to that described under block erasure, byte write does not ocCur (or balts) if Vpp is detected low. In such a case SR.3, SR.4, and SR.7' are set
high, and no further writes can take place until the
Status Register is cleared by the clear Status Register
command.

3-574

infel"

ER-27

Table 2. Byte-Write and Block-Erase
Performance vs Previous Devices

DEVICE CHARACTERIZATION

Device

AC and DC Parameters
Figures 9 through 24 show graphs of several device
parameters as a function of temperature and supply
voltage. The graphs illustrate that the 28F008SA has
significant margin to data sheet specifications.
In particular, note Figure 9 which shows typical read
performance tAVQV (tACe) of the 28FOO8SA as a function of Vcc and ambient temperature. tELQV (tcE) in
Figure 10 and tGLQV (tOE) in Figure 11 are also of
particular interest. Access times tAVQV, tELQV, and
tGLQV are specified and tested with an output load of
100 pF; additional output load capacitance slows device
operation.
Table 1 shows typical supply currents at room temperature for several operating modes.
Table 1 RMS Current Values
Mode

lee
Ipp
(Vee = 5.0V,
(Vpp = 12V)
CMOS Inputs)

Read

20mA

100 IJ-A

Byte Write

10mA

12mA

Block Erase

10mA

12mA

Standby

40IJ-A

100 IJ-A

0.20IJ-A

0.07 IJ-A

Deep Power-Down

Byte-Write Block-Erase Erase Time
Time
Timet # Bytes per Kbyte

Second-Generation Flash Memory Devices(1)
28F008SA
28F001BX

9 IJ-s
18 IJ-s

1.5s/64K
3.8s/112K
2.1s/8K
2.1s/4K

23ms
34ms
256ms
513 ms

First-Generation Flash Memory Devlces(2)
28F020

.16.5 IJ-s

6.8s/256K

27ms

28F010

16.5 IJ-s

3.9s/128K

30ms

28F512

16.5 IJ-s

2.4s/64K

37ms

28F256A

16.5 IJ-s

1.6s/32K

51 ms

NOTES:
1. Typical measured time.
2. Times calculated based on typical erase and precondition pulse requirements, with minimum write timings. Calculations are described in Figure 8.

Figure 27 shows block-write and block-erase times at
O·C and 70·C over cycling.

DEVICE RELIABILITY
Byte-Write/Block-Erase Cycling

EnergyIPower Consumption
The system designer is primarily concerned with power
consumption during block erase and byte write. Typical
curves for Icc and Ipp during block erase are shown in
Figure 25. Icc and Ipp for byte write are illustrated in
.Figure 26.

Byte-Write/Block-Erase Times
The 28F008SA advances byte-write and block-erase
performance compared to previous flash memories. The
on-chip algorithm is improved over the 28FooIBX to
take advantage of process enhancements. This improvement is most apparent when compared to first-generation flash parts with externally controlled algorithms.
First-generation device times shown in Table 2 assume
optimal system overhead, and as such are absolute best
case.

One of the most important reliability aspects of the
28F008SA is. its capability of 100,000 write/erase cycles
per block. Destructive oxide breakdown has been a limiting factor in extended cycling of thin-oxide
EEPROMs. Intel's ETOX-III flash memory technology extends cycling performance through:
• Improved tunnel-oxide processing that increases
charge-carrying capability tenfold .
• Significantly reduced oxide area under stress that
minimizes probability of oxide defects in the region.
• Reduced oxide stress due to a lower peak electric
field (lower erase voltage than EEPROM).
Reliable byte-writelblock-erase cycling requires proper
selection of the maximum erase threshold voltage (Vt),
and maintenance of a tight distribution. Maximum
erase Vt is set to 3.4V via the internal block-erase algorithm and verify circuits. Tight eraseVt distribution
gives an order of magnitude of erase-time margin to the
fastest erasing cell, with virtually identical erase Vt distributions at 1 and 10,000 cycles (Figure 28). Program
Vt distribution is similarly consistent over cycling (Figure 29).

3-575

infel .

ER-27

28FOO8SA array architecture enhances cycling capability by reducing gate disturb conditions on cells in unrelated blocks during byte write and erase pre-conditioning. First, only one of the two row decoders is active at
any time (selected by AI9)' Rows in the other two
quadrants are grounded. Secondly, two separate internally-switched voltages supply the left and right quadrants. Only one supply (selected by block address A 18)
is switched to programming voltages while the other
remains at read voltages. This A19-A18 row decoding
ensures that during byte write, 12 of the 16 blocks have
a gate voltage below that required for programming.

Data Protection
The 28FOO8SA offers protection against accidental
block erasure or byte write during power transitions.
Internal circuitry creates a device insensitive to Vpp/
Vee supply power-up sequencing. Vpp :s; VPPL locks
out byte-write and block-erase circuits. Vee :s; VLKO
disables CUI command writes, resets the CUI to array
read mode, and holds the WSM. inactive. The system
designer must still guard against spurious command
writes for Vee> VLKO when Vpp > VPPL.
Several strategies are available to prevent data modification in the 28FOO8SA. The CUI provides a degree of
software write protection since memory alteration occurs only after successful completion of a two-step
write sequence. WE and CE must both go active to
perform this sequence; driving either high inhibits command/data writes. Secondly, the system can place the
device in deep power-down mode (PWD = VII) to
disable command writes, reset the CUI to array read

mode, and hold the WSM inactive, effectively protecting array data. Finally, the system designer may hardwire Vpp to VpPH, or switch it to VPPH only when
memory updates are required. Since byte-write and
block-erase circuits are disabled by Vpp :s; VPPL, Vpp
switching adds another level of data security.

SUMMARY
The 28FOO8SA is the first flash memory with features
optimized for solid-state systems and file storage. These
features include symmetrical block-erase, automation
of byte write and block erase, erase suspend for data
read, a deep power-down mode, a write/erase Status
Register. and a dedicated RY/BY status pin. With simple microprocessor interfacing and software command
sequences. the 28FOO8SA is the non-volatile storage solution of choice for today's designs.

OTHER REFERENCES
Related documents of interest to readers of this engineering report:
28FOO8SA Data Sheet (order #290429)
28FOO8SA-L Data Sheet (order #290435)
Ap·359 "28FOO8SA Hardware Interfacing"
(order #292094)
AP-360 "28FOO8SA Software Drivers"
(order #292095)
AP-364 "28FOO8SA Automation and Algorithms"
(order #292099)
ER-28 "ETOXTM III Flash Memory Technology Engineering Report" (order #294012)

3-576

ER-27

SUPPLEMENTARY INFORMATION
FORMULA:

b =
n =
,w =
v =
p =

100

# bytes in a block (256K, 128K, 64K, 32K)
# of erase pulses required (90 pulses)

90

time for a write cycle (150 ns, tAVAV)
time to verify (6055 ns, tWHGL + tGLQV)
program pulse width (10 /Ls, tWHWHI) one
pulse programming assumed
e = erase pulse width (10 ms, tWHwHV

80
~

..s"
>
a
>

..

Precondition and precondition verify time is:
b (2w

70

~

+ P + v)

60
50

Erase/verify, each loop where some byte does not
pass verify:
(n - 1) (2w

+

+ v)

e

4.5

5.0

5.5

6.0

Vee (V)

Last erase pulse:
(1) (2w

+

294011-8

e)

Figure. 9. tAVQV (tACC) vs Vec and Temperature

Passing erase-verify, all bytes:
b(w

+ v)

Total time can be summarized as:
b (3w

+ P+

+

2v)

n (2w

+

e

+ v)

- (v)

or substituting in, times for write, verify, program
and erase pulse widths:
b (22:56 x 10- 6) + n (10.006355 x 10- 3)
- (6.055

x

10- 6) Seconds

Figure 8. Erase Time Calculations for
First-Generation Flash Memories
110
34
100

32

90

30
28

~

..s"

80

'in'

..s

>

g

..iI'

g

70

..9

26
24
22

60

20

50

18
4.5

5.9

5.5

6.0

4.5

Vee (V)

5.0

5.5

6.0

Vee (V)

294011-9

294011-10

Figure 10. tELQV (tCE) vsVCC and Temperature

Figure 11. tGLQV (tOE) vs VCC and Temperature

3-577

infel·

1

ER-27

161--~o;:~

-10~---+~~+_~~----~

ffi

-12r-~~~~+_--~----~

:r

j

121--""100;;;::-

-16~L--+----+_--~----~
-18~--~----~--~----~

-4.5

5.0

5.5

6.0

4.0

-4.5

Vee (V)

5.0

5.5

6.0

Vee (V)

294011-11

294011-12

Figure 12. tovwH (tos WE)
VB Vee and Temperature

Figure 13. tEHOX (toH CE)
VB Vee and Temperature
-2,---,----,----,---,

28~--r--~--'--~
26r-~~~--+_--~----~

24 ir---+',,"
22r-~-+--~~--~----~

20 1---"""";;:18 1-.,---+---"""1..---/-""'""",:-1

]
:r

J

-;;..5

16f3~~----+-~~----:-l

14

::;:

r----+"""'~T-"'--~C30~~

;

-10r----+~--+_~~----~

12~~-+---~~~----~

10r----+..:::o.......
8r----+--.,--~~~----~

-14~~-+----+_--~----~

61_-~--1_-~~~
-16~--~----~--~----~

-4.5

5.0

5.5

6.0

4.0

Vee (V)

4.5

5.0

5.5

6.0

Vee (V)

294011-13

294011-14

Figure 14; tAVWH (tAS WE)
VB Vee and Temperature

Figure 15. tWHAX (tAH WE)
vs Vee and Temperature

3-578

intel .

ER-27

24

2

22

0

20

-55°C
-2

18

-;;;-

16

i!i
>

14

.s

-<

-;;;-

.5

...

-4

x

:J:

12

-<

10

-6
-8
-10

4.5

5.0

5.5

6.0

4.5

Vee (V)

5.0

5.5

294011-15

294011-16

Figure 16. tAVEH (tAS CE)vs
Vee and Temperatu~e
22

"-

18

-;;;-

14

'"----

.5 12
:J:

~

-'

J-

10
8

60

'-125°C

.....

....

65

I

" " =s.J.

16

Figure 17. tAHEX (tAH CE)
vs Vee and Temperature,

I

"-

20

55

~

____ ooc -

6.0

Vee (V)

~

'"

.5

I'.....

-'
a:

50
45

:J:

J-

-55°C

40

I

6

10 ns IS LIMIT
OF MEASUREMENT
HARDWARE

4
2

30

I

o
4.0

35

4.5

5.0

5.5

4.5

6.0

Vee (V)

5.0

5.5

6.0

Vee (V)
294011-17

294011-18

Figure 19. tWHRL vs Vee and Temperature

Figure 18. tWLWH (twp)
vs Vee and Temperature

3-579

ER·27

1.40

2.0

1.35

1.9
1.8

1.30

:8

'>

,~

....
:> 1.25

2· 1.6

2

:::E

:::E

1.20

-

>Q

1.5

.Q

1.15

1.4

1.10

1.3

••5

5.0

5.5

6.0

••5

5.0

5.5

6.0

Vee (V)

Vee (V)

294011-19

294011-20

Figure 20. Dynamic VIL
Vee and Temperature

Figure 21. Dynamic VIH
vs Vee and Temperature

VS

3·580

ER-27

70

13
12

60

11
50

'<
.5
..J

1=

'<
.5
III
0

.0

9

::E

<>

:J:

.S>

10

:J:

.S>

30

8

7
20

6

•.5

5.0

5.5

6.0

•. 5

Vee (V)
294011-21

32r----+--~~~~r---~

28r----+----~--~~~~

26r----+~~~--~r---~

204~~~----+---~~--~

.§ 22 1----+--

18 \0000""'--+-16~--_+~~9_--~r---~

•.5

5.0

6.0

Figure 23. IOH CMOS vs Vee and Temperature
(VOH = Vee - O.4V)

3.r---~~------~r--=~

...

5.5

294011-22

Figure 22. IOH TTL vs Vee and Temperature
(VOH = 2.4V)

~

5.0

Vee (V)

5.5

6.0

Vee (V)
294011-23

Figure 24. IOL vs Vee and Temperature
(VOL = O.45V)

3·581

infel .

ER-27

16mA

I

I---

ICC ERASE

It

2mA

l .J

IDIV

.. tit.

~fII

IU....... .Ii

III

1t14

lVW WIll. All iIIIIJI.

-4mA
-200mS

1.8S

200ms/DIV

16mA

294011-24

I

I--- Ipp ERASE

~

2mA

IDIV

.n

'.

IIJ

-4mA
-200mS

II

-'11111"

III

I'll

IIII "-

-

~

200ms/DIV

Figure 25. Icc and Ipp under Block-Erase Operation

3-582

1.8S

294011-25

infel .

ER-27

16mA

ICC PROG

2mA

IDiV

-

.iA.t

....

I",

"'"

,IlIlJJ I.h."

-4mA
-21-'5

294011-26

294011-27

Figure 26. Icc and Ipp ",nder Byte-Write Operation

3-583

ER-27

5.0
4.0

'"

c

z

l:l

'"

/

3.0

0

2.0

---

1.0 -

V/

OOC ERASE . - -

V~

70°C ERASE

70°C BLOCK WRITE
OOC BLOCK WRITE

0.0
100

1,000

5,000

10,000

II--

100,000

CYCLES

Figure 27. Write and Erase Times 'YS Cycling

3-584

294011-28

intel .

ER·27

28F008SA Erased Vt Dist. vs Cycling; Vpp

12; T

=

I.

5
«
III
0

'/

90

II<

...>
"-

50

;::

10

«
....

::>
:0
::>

u

Room

=

I

99.999
>- 99.99
99.9
99
iii

-~1. '?'

AFTER 10k PiE CYCLES

If,

BEFORE
CYCLING

'f

0.1
0.01
0.001

Ih

294011~29

Figure 28. Erase Vt vs Cycles
28F008SA Programmed Vt Dist. vs Cycling; Vpp = 12; T= Room
99.999

...

>- 99.99
:; 99.9

iii

99

0

90

«
III

./

V

'-

II<

..."->
;::

:5

::>
:0
::>

u

J

I

/

50
AFTER 10k_
PiE CYCLES

10 0.1
0.01
0.001
5.0

5.5

6.0

-f

J

I

'~ ___ BEFORE. _

I
IL

6.5

-

J
7.0

CYCLING

7.5

Figure 29. Program Vt vs Cycles

3-585

/
./

8.0

8.5

294011-30

ER-27

294011-31

Figure 30. 278F008SA Ole Photo

3-586

ER-27

Az

14

I<,

15

Vec
CE
1<,2
AU
1<,4
1<,5
1<,6
1<,7
A,B
AI9
NC
NC
NC
NC
WE

Au

16

DE

DOo
DO,
DQ2

17

RY/Bv

18

DIq

10
2

1<"

3
41

1<,0
Ag

As

6

A,

7

As

8

As
A4
NC
Ne
A3

D~

GND
GND

PAI8FOO8SA

10 44 LEAD PSOP
11 0.15115" x 1.110"
TOP

VIEW

12

13

19

31

Pin Names
Ao-A'9
000-007
CE
PWD
OE
WE
RY/BY
Vpp
Vee

GND

D~

DQs
DQ4
vee
294011-32

Figure 31. PSOP Lead Configuration

3-587

Address Inputs
Data Inputs/Outputs
Chip Enable
Power Down
Output Enable
Write Enable
Ready/Busy
Write/Erase Power Supply
Device Power Supply
Ground

infel·

ER·27

Standard Pinout
~'9

1

A,s
~7
~6
~5
~4
~3
~2

~

DOe

STANDARD PINOUT
E28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW

Vee
Vpp
PWD

As

WE
FE
RY!iY

CE

~1
~o

Ne
Ne

0

15

D05
D04

Vee
GND
GND
D~

D02

00,

As

DOo

~

Au

As

~'

As

A2
A3

A4

294011-33

Reverse Pinout
Ne
Ne

WE
FE
RY!iY
~

DOe

DOs

D04

Vee
GND
GND
~
~
~

DOo
Au
~
A2
A3

~\7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

REVERSE PINOUT
F28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW

0,40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

~9
~s
~7
~6

A,5
~4

~3
~2

CE
Vee
Vpp

Wo
~1
~o

As
As

~

As
As
A4

294011-34

Figure 32. TSOP Lead Configuration

3·588

intel .

ER-27

Wordlines are numbered sequentially from top to bottom. Addresses A9-Ao sequentially decode wordlines: block
address A19 selects between upper and lower row-decoder. Wordlines 0-1023 serve the left and right quadrants at
top of device; 1024-2047 serve the lower quadrants.

Table 3. Row Address Bitmap
Wordllne

A19

A9

As

A7

A6

As

A4

A3

A2

A1

AO

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

1
2-

0

0

0

0

0

0

0

0

0

1

1

3

0

0

0

0

0

0

0

0

1

0

0

4

0

0

0

0

0

0

0

0

1

0

1

5

0

0

0

0

0

0

0

0

1

1

0

6

0

0

0

0

0

0

0

0

1

1

1

7

0

0

0

0

0

0

0

1

0

0

0

8

0

0

0

0

0

0

0

1

0

0

1

9

0

0

0

0

0

0

0

1

0

1

0

10

0

0

0

0

0

0

0

1

0

1

1

11

0

0

0

0

0

0

0

1

1

0

0

12

0

0

0

0

0

0

0

1

1

0

1

13

0

0

0

0

0

0

0

1

1

1

0

14

0

0

0

0

0

0

0

1

1

1

1

15

0

0

0

0

0

0

1

0

0

0

0

16

0

0

0

0

0

0

1

•

•

•

•

•

0

0

0

0

0

0

1

1

1

1

1

31

0

•

•

•

•

•

•

•

•

•

•

•

0

1

1

1

1

1

1

0

0

0

0

1008

0

1

1

1

1

1

1

•

•

•

•

•

0

1

1

1

1

1

1

1

1

1

1

1023

1

0

0

0

0

0

0

0

0

0

0

1024

1

0

0

0

0

0

0

•

•

•

•

•

1

0

0

0

0

0

0

1

1

1

1

1039

1

0

0

0

0

0

1

0

0

0

0

1040

1

•

•

•

•

•

•

•

•

•

•

•

1

1

1

1

1

1

1

1

1

1

1

2047

3-589

intel .

ER-27

Blocks are numbered sequentially right to left. top to bottom. Columns within a block are numbered left to right.
I/Os within a block are numbered from 0-7 left to right. '
Table 4. Block Address B!tmap
Block

Columns

A19

A18

A17

A16

0

0

0

0

0

0-511

0

0

~O

1

1

512-1023

0

0

1

0

2

1024-1535

0

0

1

1

3

1536-2047

0

1

0

0

4

2048-2559

0

1

0

1

5

2560-3071

0

1

1

0

6

3072-3583

0

1

1

1

7

3584095

1

0

0

0

8

4096-4607

1

0

0

1

9

4608-5119

1

o·

1

0

10

5120-5631

1

0

1

1

11

5632-6143

1

1

0

0

12

6144-6655

1

1

0

1

13

6656-7167

1

1

1

0

14

7168-7679

1

1

1

1

15

7680-8191

Columns are numbered from left to right across the top quadrants. and left to right across the bottom quadrants.
Addresses A15-AIO sequentially count columns. Columns are listed for block 0; other blocks are counted similarly.
Table 5. Column Address Bitmap
Column In
A15

A14

A13

A12

A11

A10

1/00

1/0 1

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

0
1
2
3
4

64
65
66
67
68

1
1

1
1

•

•

•

1
1

•

1
1

•

1
1

•

0
1

•

62
63

•

126
127

3~590

1/02
128
129
130
131
132

•

190
191

1/03
192
193
194
195
196

1/04

1/05

1/06

1/07

256
257
258
259
260

320
.321
322
323
324

384
.385
386
387
388

448
449
450
451
452

254
255

318
319

382
383.

•

•

•

•

446
447

•

510
511

ENGINEERING
REPORT

ER-28

October 1992

./.

ETOXTM III Flash Memory
Te.chnology

ALAN BUCHECKER
MARK NEWMAN
MEMORY COMPONENTS DIVISION

Order Number: 294012-002
3·591

ETOXTM III Flash Memory Technology
CONTENTS

PAGE

INTRODUCTION . .......... : ........... 3-593
ETOXTM III FLASH MEMORY CELL ... 3-593
Cell Processing ...... , ................. 3-594
Byte Write .............................. 3-594
Block Erase ............................ 3-595
ETOXTM III PROCESS
CHARACTERISTICS ................ 3-595
Write/Erase Performance with Voltage
and Temperature .................... 3-595
Write/Erase Cycling .................... 3-596
Process Variation ...................... 3-597
Electrical Testing ....................... 3-~97

CONTENTS

PAGE

ETOXTM III MEMORY ARRAY
CONSIDERATIONS ................. 3-597
28F008SA Array Architecture ........... 3-597
28F008SA Byte-Write Operation ........ 3-597.
28F008SA Block-Erase Operation ...... 3-597
28F008SA Cell Voltage Threshold ...... 3-597
FLASH VS. OTHER SEMICONDUCTOR
MEMORY TECHNOLOGIES ......... 3-598
SRAM and DRAM .............. : ....... 3-600
EPROM ................................. 3-601
EEPROM ......... '.' ................... 3-601
NAND ....................... : ....... ;. 3-602
SUMMARY ..................... , ...... 3-602
OTHER REFERENCES .......... ~ ..... 3-602
APPENDIX A ...................... : ... 3-603

3-592

infel ...

ER-28

INTRODUCTION
. Intel's ETOXTM III (EPROM tunnel oxide) Flash
. Memory technology builds on previous flash and
EPROM processes spanning over two decades of manufacturing experience. This third-generation process
produces devices based on O,S/Lm photolithography.
Intel's Flash Memories combine EPROM programming with EEPROM-like in-system electrical erasure.
This functionality, experience and technology yield a
versatile non-volatile memory that is highly reliable and
cost effective.
ETOX III cell integrity enables applications requiring
100,000 write/erase cycles. New designs incorporate·array blocking schemes and on-chip automation of write
and erase to simplify customer designs and software
interface. These features combine with existing Intel
Flash Memory technology to produce a device that can
be termed a block-alterable non-volatile RAM. Access
time (tACe) and die size decrease via this smaller photolithography, making new Intel Flash Memories competitive with DRAM in read speed and cost.

The Intel 2SFooSSA S-Mbit Flash Memory is the first
ETOX III product offering. This report references the
2SFooSSA to explain device-level concepts, and ends by
highlighting important flash memory application
trends.

ETOXTM III FLASH MEMORY CELL
ETOX III is a O.S /Lm double-polysilicon N-well and
powell CMOS process. This lithographic advance improves memory cell/array compaction more than twofold over its predecessor, the 1.0 /Lm ETOX II process.
ETOX III-aided compaction allows for a 4x product
density growth given current packaging constraints.
Second-generation device architecture (see APpendix
A) and O.S /Lm geometries increase byte-write and read
access performance by 2x over ETOX II products.
Double-metal technology enhances these improvements
by aiding die size compaction, and wordline strapping.
EPI wafer processing, which reduces latch-up, also factors into this performance boost by shrinking transistor
layout.

This report describes the fundamentals of Intel's ETOX
III Flash Memory cell:-It~rovides insight into device
reliability and perforinan~ enhancements based on
ETOX III advances, and Compares other semiconductor memory technologies.

3-593

inteL

ER-28

Cell Processing
Intel's single-transistor Flash Memory cell stores
charge on a floating polysilicon gate. Dimensions of 2.5
p.m by 2.9 p.m make an ETQX III cell measuring 7.25
p.m 2. ,Cell layout locates the polysilicon select gate
above the floating gate (Figure I). Tungsten silicide, deposited on the select gate, reduces wordline resistance.
Two dielectrics isolate metal-I from the select gate.

Inter-poly dielectrics of oxide and nitride isolate the
floating gate from the select gate. A very thin tunnel
oxide (- IOOA) separates the floating gate from its silicon interface. Both the 'floating and select gates have

additional isolation between them and their respective
source/drain regions. A deeper source diffusion prevents breakdown during erase operations. In the array
metal-2 straps the wordline to enhance access times. As
with ETOX I and ETOX II, metal-I carries bitline data
to the sense amps and routes voltages to cell sources.

294012-18

Figure 1. ETOXTM '" Flash Memory Cell (Side View)

Byte Write
Writing data to an addressed byte transitions selected
cells from the "I" (erased or no charge) state to the "0"
(charged) state. This involves a programming mecha- '
nism called chimnel hot-electron injection. When programming (Figure 2), a cell's select gate (wordline) connects to the external programming supply voltage (Vpp
at 12Y). The drain (bitline) sees an intermediate level
(-Vpp/2), while the source is atground. Vpp on the
select 'gate capacitively, couples to the floating gate
through the intervening dielectric. This coupling raises
the floating gate to a programming voltage, inverting
the channel underneath.

The channel electrons now have a higher drift velocity,
with resulting increased kinetic energy. Collisions between these electrons and substrate atoms heat the silicon lattice. At the programming bias voltage, the electrons cannot transfer their kinetic energy to the atoms
fast enough to maintain a thermal balance. They become "hotter," and many scatter toward the tunnel oxide. These electrons overcome the 3.leV (electron voltage) turmel oxide barrier and accumulate onto the floating gate.

3-594

int"el.

ER-28

While biased in this. fashion, electrons .tunnel off the
floating gate. They pass through the thin oxide to the
source, lowering that cell's Vt. During a read operation,
the resulting "I" at the output corresponds to an "on"
cell discharging its bitline through the grounded source.

VD =Vpp

I

SELECT GATE

Erase automation sets the internal Vpp pulse to 10 ms.
The WSM provides sufficient 10 ms pulses, and automatically verifies all memory cells in a given block.
This optimized pulse width enhances block-erase time
and cycling endurance.
294012-2

ETOXTM III PROCESS
CHARACTERISTICS

Figure 2. ETOXTM III Flash Memory Cell
during Programming (Side View)
The electrons stored on the floating gate raise the turnon voltage threshold (Vt> of that cell. During device
read operations this transistor remains in the off state.
A "0" results at the output because the "oft" cell does
not pass current, causing the bitline to electrically stay
at/pull-up to the Vcc read voltage.
The internal programming pulse on ETOX III is 4 ,...S
(excluding WSM overhead), reduced from 10 ,...S on·
ETOX II d~vices. This optimized pulse width yields
faster byte-write times and greater cycling reliability.
Like previous ETOX products, the automated WSM
allows for the occasional byte requiring more than one
pulse.

Block Erase
During erasure, electrons are pulled off selected memory cells simultaneously. :rile erase process ("FowlerNordheim" tunneling) starts by routing Vpp to the
source, ground to the select gate, and floats the drain
(Figure 3).

Intel leverages over two decades of EPROM/flash
technology and manufacturing experience to produce
reliable memory products. Refined processing techniques inherent to new Intel memory technologies and
continuous improvements in process control ensure
tunnel oxide qUality. A scaled substrate EPI thickness
reduces product latch-up. Doubie-metal technology requires improved planarlzation processing, which in
tum enhances moisture performance. Additionally, decreases in defect density show lasting cell integrity in
cycling and data retention.

Write/Erase Performance with Voltage
and Temperature
Voltage affects byte-write and block-erase performance.
Maximum Vpp improves byte-write and block-erase
times. Figure 4 shows little difference in block-write
time versus Vpp, but visible differences in block-erase
performance. A secondary and negligible effect results
from the operating supply voltage (Vcd. Byte-write
and block-erase times are guaranteed to specification
across minimum and maximum voltage levels.
Temperature also affects byte-write and block-erase
performance. Low temperatures cause block-erase
times to increase and byte-write times to improve (Fig"
ure 4). When cold, the breakdown voltage at the source
lowers, clamping the external voltage applied for block
erase. This nets a lower potential between the source
and gate, slowing the tunneling process. Increased erase
time results from the WSM prpviding extra pulseS. Although electron mobility decreases at hotter temperatures, typical cells still require only one programming
.
pulse.

294012-3

Figure 3. ETOXTM !II Flash Memory Cell
during Erase (Side View) .

3-595

intet

ER-28

From a performance perspective, an intrinsic mechanism occurs in long-term cycling that cause byte-write
and block-erase times to increase (Figure 5), but still
conform to specification. Specifically, hot electrons
from programming trap in the tunnel oxide near the
drain junction. This creates a negatively-charged barrier, slowing hot-electron injection. Similarly, erase times
increase due to charge trapping near the source junction, making tunneling less efficient. The robustness of
ETOX III minimizes these effects. Write and erase
times remain consistent over the first 10,000 cycles, and
typically double as the device nears 100,000 cycles.

Write/Erase Cycling
Intel designs extended cycling capability into its ETOX
III products. For example, the 28FOO8SA is designed
for 100,000 write/erase cycles on each .of its sixteen
64-Kbyte blocks. Low electric fields, advanced
low-defect oxides, and minimal oxide area per cell combine to greatly reduce oxide stress and the probability
of failure.

2.3
2.2

T
I
M
E

2.1

2.0

ERASE TIME, Vpp = 11.4 Volts

1.9
1.8
1.7

I
N

1.6
1.5
1.4

S
E
C

1.3

0

1.0
0.9

N
0
S

1.2
1.1
WRITE TINE, Vpp
WRITE TINE, Vpp

0.8
0.7
0.6

WRITE TINE, Vpp

= 11.4 Volt.

= 12.0 Volt.

= 12.6 Volts

0.5
0

10

15

20

25

30

35

40

45

50

55

60

65

70

TEMPERATURE (CELCIUS)

294012-4

Figure 4. 28F008SA Block Write and Erase TImes vs Temperature and Vpp

5.0

T
I
M
E
I
N
S
E
C
0
N

0

4.0

3.0

2.0

ooe

Block Erase

70°C Block Erase
1.0

70°C Block Write

S

Qoe Block Write

100

I

I

1,000

5,000

10,000

CYCLES

Figure 5. WrIte and Erase Times vs Cycling

3-596

100,000

294012-5

ER-28

Process Variation

28F008SA Array Architecture

Intel's .process control of ETOX III critical cell dimensions keep write and. erase electrical characteristics on
target with little variance. This capability produces devices with consistent byte-writelblock-erase times making product performance predictable.

Figure 6 illustrates the 2SFOOSSA. Sixteen equal
64-Kbyte blocks make up this S,33S,6OS-bit memory
array. Each block consists of 512 columns by 1024
rows. Columns in each block are further subdivided
into eight input/outputs, each containing 64 columns.
Typical block-erase and block-write times for this device are 1.6 and 0.6 seconds. Typical byte-write time,
including WSM overhead, is 9 ,...s. .

Over the processes lifetime, internal cell dimensions
may exhibit some small variance. The primary process
variable affecting erase is tunnel oxide thickness. Channellength (Left") has the largest impact on programming. Outgoing product testing ensures performance to
specification regardless of these minor variances.

28F008SA Byte-Write Operation
During byte write, column address decoding determines which eight bitlines of a target block connect to
the intermediate programming voltage (- Vpp/2).
Row decoding determines wordline drive to Vpp. For
example, writing a byte of data in block 0 sets that one
wordline to Vpp. Address selection sets all other wordlines in the array to ground. Array decodingllayout
and cell durability assure device performance and reliability, and long-term data retention.

Electrical Testing
Electrical testing provides added value to Intel Flash
Memory products. This elaborate testing gives insight
to device characteristics and ensures product longevity.
Moreover, flash reliability qualifications assure product
performance and long-term durability.

28F008SA Block-Erase Operation

Electrical erase at wafer and package test allow high
confidence of detecting oxide defects. This electrical
testing also ensures that outgoing products perform to
specified temperature extremes. Optimization of
ETOX III process and designs, developed from previous ETOX generations and continuous data collection,
yield a very manufacturable and cost-effective technol-

ogy.

Erasing a block involves simultaneous erasure of all bits
in that block. For example, erasing block 0 sets all
block 0 sources to Vpp and all block 0 wordlines to
ground. Address decoding drives all other wordlines,
bitlines and sources in the array to ground. This eliminates the possibility of corruption to data stored in nonselected blocks.

.

28F008SA Cell Voltage Threshold

ETOXTM III FLASH MEMORY
ARRAY CONSIDERATIONS

Efficient blocking layout and optimized decoding result
in smaller die size. Blocking tightens program and erase
Vts by dividing process variation into smaller regions.
The internal WSM algorithms and their associated program/erase and verify circuits also keep Vt variations
to a minimum. This design for manufacturing approach
increases product stability.

Intel Flash Memory architecture has evolved from bulk
arrays (full-chip electrical erase), to array segmentation
referred to as blocking. Blocking divides the device
memory array into smaller sections that function as individually-erasable units.

W

Q

o

~
Q

I
.IIJICI(

a

BLOCK 1

BLOCK 2

BLOCK 3

X

BLOCK.

BLOCK 5

BLOCK.!

BLOCK 7

Y-DECODE

Y-DECODE

....
§
Q

Q

BLOCK B

BLOCK 9

BLOCK 10

BLOCK 11

I
X

BLOCK 12

BLOCK 13

BLOCK,.

BLOCK 15

294012-6

Figure 6. Intel 28F008SA Memory Array Layout

3-597

int'et

ER·28

FLASH VS. OTHER SEMICONDUCTOR
MEMORY TECHNOLOGIES
Intel's scaling advances in flash memory nlanufacturing
and design provide optimal cell/array compaction. In
roughly twenty years, Intel non-volatile memory densi-

ty has gone from 2,048 bits to 8,388,608 bits, a 4096x
increase. Figure 7 compares other memory types· to
show relative density progression. The fast ramp in
ETOX flash memory density resuits from iis simHarity
to EPROM.

64M

32M

16M

8M

4M

2M

1M
~

I-

iii

S12K

Z

UJ

0
~

2S6K

a:::
0

:::IE

UJ

128K

:::IE
64K

32K

16K

8K

4K

2K

1970

1974

1978

1982

1986

1990

1994

1998

PRODUCTION YEAR
294012-7

Figure 7. Memory EvolutIon

3-598

ER-28

portionally). The memory cost per bit learning curve
shows flash in a strong position. This curve, shown in
Figure 9, reflects how Intel's experience reduces cost
for increased memory density.

Figure 8 illustrates the relationship between cell sizes of
different memory types and minimum geometries. As
dimensions scale, certain memory types become cellsize
limited (Le. some components cannot shrink pro-

1000
500

......
'".3.....

200
100

N

iii

-'
-'
.....
(.)

50
20

>a::
0

:::::E
.....

10

:::::E

'2.0

1.6

1.2

1.0

.8

.7

.6

.5

MINIMUM rEATURE SIZE Cu)

294012-8

Figure 8. Memory Cell Size Trends

------- ... .... ....

.... ...... ......

......
EEPRO;

-----

EPROM

1988

1989

1990

1991

1992

Figure 9. Memory Cost/Bit Learning Curves

3-599

1993

1994

294012':9

infel .

ER·28

Since the late 1980s, a new memory sub-system has
arrived on the market, offering an alternative to highdensity file system media. Intel's Series 2 Flash Memory Cards take advantage of the 28FOO8SA and its second-~eneration architecture to provide card densities of

up to 20 Mbytes and new functionality. This relatively
new technology offers a solid-state file system (Figure
10) that will double in density with new ETOX generations.

256

640

:cos
""

128

320

~

64

160

c

32

80

"2

.
.3
.
.

n

CD

'iii
c::

~

-.,

C

CD
::l

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40

16

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CD

co

c::
c::

20

PI


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CD

10

4
'91

'92

'93

'94

'95

'96

'97

'98

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2940.12-10

2000

Figure 10. ETOX Component and Memory Card Density Over Time
currents and read operations. Charge storage requirements limit size reduction of the capacitor, which in
turn limits memory array compaction. With smaller
geometries, DRAM cell structures are more complex,
requiring more process manufacturing steps.

294012-11

.Figure 11. Six-Transistor SRAM Cell Schematic

294012-12

Figure 12. Stacked DRAM Cell (Side View)

SRAM and DRAM
SRAM and DRAM have fast read/write speeds. Both
are volatile memories requiring continuous power to
retain data. Standard SRAMs (Figure II) require four
to six transistors for each flip-flop cell. This greatly
reduces memory capaCity per unit area, raising product
cost for a given density.
DRAM requires constant refresh of the capacitor-like
storage mechanism (Fjgures 12 and 13) due to leakage

C:=J

\,,----J_:ID------...
294012-13

Figure 13. Trenched DRAM Cell (Side View)

3-600

inteL

ER-28

Most DRAMs require a read parity bit for two reasons.
First, alpha particle strikes can disturb cells by ionizing
radiation, resulting in lost data. Second, when reading
DRAM, the cell's storage mechanism capacitively
shares its charge with the bitline through a select transistor. This creates a small voltage differential to be
sensed during read access. This low voltage differential
can also be influenced by nearby bitline voltages and
device noise.
ETOX III floating-gate technology electrically isolates
the substrate from the charge storage mechanism. Unlike DRAM, floating-gate charge determines cell Vts,
which in turn controls bitline voltages. This allows
flash memory read sensing to easily detect cell Vts. A
current swing of 70 Il-A, from strong cell Vts, make
bitline voltage transitions a key factor to fast read
speeds.
Most DRAMs require high active power consumption.
Charge storage requirements and read signal strength
constrain DRAM cell compaction. Low-power ETOX
III flash memory has a simple single-transistor cell with
only minor scaling limitations through the year 2000.
This results in a mainstream memory that does not
need power to retain data.

Intel's ETOX III technology employs double-metal
processing to strap wordlines in metal for improved
read performance. This advance is not likely to appear
on EPROM because it would block even more UV
light. Since flash memory electrically erases, it eliminates these concerns. Moreover, flash electrical erasure
eliminates the UV window and its associated cost, and
allows for the most advanced and innovative plastic
surface-mount packaging solutions.

EEPROM
Conventional two-transistor EEPROM cells (Figures
15 and 16) limit layout density. This is primarily due to
the second transistor (bit select) and associated decoding required for single byte program and erase capability. Technology design requirements make EEPROM
cells, like triple poly, significantly larger than flash.
Typical, EEPROM technologies are more complex,
making wafer manufacturing difficult and expensive.

-----J

EPROM
Intel's EPROM and Flash Memory cells share a common stacked-gate profile (Figure 14), with two basic
differences relating to their respective erase mechanisms. EPROM requires ultraviolet light to erase; flash
erases electrically. For this reason, flash has a thinner
cell oxide to allow Fowler-Nordheim tunneling, and a
deeper source junction to prevent breakdown during
erase.

(~-)

)

294012-15

Figure 15. Flotox EEPROM Cell (Side View)

P

C__-..C

)

294012-14

9

294012-16

Figure 16. Triple j)oly EEPROM Cell (Side View)

Figure 14. EPROM Cell (Side View)

EPROM technologies that migrate toward smaller geometries make floating-gate discharge (erase) via UV exposure increasingly difficult. One problem is that the
width of metal bitlines cannot reduce proportionally
with advancing process technologies. EPROM metal
width requirements limit bitline spacing, thus reducing
, the amount of high-energy photons that reach charged
cells. EPROM products built on submicron technologies will face longer UV exposure times.
3-601

Because of their traditional application, EEPROMs use
a very high internal voltage (17V to 30Y) to achieve fast
program and erase times. These high voltages and resulting electric fields cause cell oxides to breakdown,
shortening cycling life and degrading cell thresholds.
Additionally, this high voltage stresses periphery transistors. Intel's Flash Memories are more akin to
EPROM; both use a significantly lower voltage around
12V.

intet

ER-28

NAND
Futuristic types of EEPROM (Figure 17) that have
shifted from highly-manufacturable NOR-gate architectures, appear to provide ETOX-like density on "Ii per
cell basis and potential use in similar applications. A
closer examination reveals internal positive and negative charge pumping. When applied across a memory
cell, the dual charge pumps net a high voltage that
cause oxide stress. These stacked~gate cells program
and erase via tunneling. They program from the substrate to the floating gate, and erase in the reverse bias.
Bit Line

Select Gate 1 ---I--I---~;""'---

Control Gate 8

---++I--~E----

CG7----~~----~-------

however the first read always remains slow. Fast write
times require a page buffer for full wordline programming. Several wordlines erase at once, setting the block
size. Product scaling becomes limited from high-voltage
requirements on periphery transistors and isolation
technology. Compared to EEPROM, the NAND approach improves array compaction at the expense of
more complex decoding and periphery circuitry.

SUMMARY
Intel's technology advances result in products that are
more efficient, more reliable, less expensive and higher
performance. Submicron geometries and double-metal
technology allow considerable memory array compaction, providing increased read and byte-write performance. Design compaction also improves with EPI wafers that reduce latch-up, allowing closer transistor layout. Strong cycling endurance results from the quality
of the thin low-defect tunnel oxide, and the electrical
characteristics of internal program and erase operations. Cycling, voltage and temperature exhibit only a
small influence on byte-write and block-erase speeds.
Products built on Intel's CMOS ETOX III Flash Memory technology require minimal power consumption
during writes, erasure, read, and low-power sleep or
standby modes.

CG6---++I--~E----

CG5----~H+----~-------

CG4----~~----~-------

CG3----~~----~-------

CG2----~~----~-----

Intel Flash 'Memory products designed on ETOX III
will satisfy many different applications. The Thin SmallOutline Package (TSOP) provides customers with high
memory density in the smallest footprint. Some applications for ETOX III flash products include memory
cards, solid-state drives, non-volatile operating systems;
high-performance system storage, data acquisition, and
application and embedded code storage. The solid-state .
nature of flashresults in imprOVed ruggedness over mechanical rotating media. With blocking, applications
can perform background erase to optimize system performance. Today,. Intel's technological advances in
flash memory are driving cost to parity with DRAM.
This steep decline in the price learning curve enables
new classes of systems and system architectures.

CG1--~~---~------

OTHER REFERENCES
Select Gale 2 - - - -......--~;.....---

294012-17

Related documents of interest to readers of this engineering report:
28FOO8SA Data Sheet (Order No: 290429)

Figure 1iEIght Cell NAND Configuration

Series 2 Memory Card Data Sheet (Order No. 290434)

Layout of the NAND array groups eight cells as a set,
each set requires two select transistors to control bitline
acceSs. Due to this NAND configuration, the read path
goes through other cells making access slow. Increased
read speed requires an internal SRAM page buffer,

ER-27,: The Intel 28FOO8SA Flash Memory (Order No.
294011)

infel~

ER·28

APPENDIX A
First-generation flash devices, like the 28F020, use externally-controlled algorithms for byte write and bulk
erase. These algorithms require that customer software
control:
• Cell pulse widths, and pulse repetition where required.
• Erase preconditioning (Le. pre-programming all
cells before erase). .
• Timeout delays to allow cell voltages to transition
from program or erase levels to read verify levels.
• Read compare operations to determine success.
Second-generation architectures, like that on the
28FOO8SA, contain an internal Write State Machine
(WSM) to simplify software development. This WSM
pro.vides internal control of all of these first-generation

requirements, as well as reporting on activity progress/
success through the internal Status Register. A dedicated output on the 28FOO8SA allows immediate hardware signaling of WSM activity status. The Command
User Interface (CUI) provides customer control.
The other major architectural feature of second-generation devices is array segmentation, also referred to as
"blocking". First-generation products erase in bulk.
This means that all cells in the array erase simultaneously. Second-generation "sectored" architectures divide the array into separately-erasable block segments.
This provides logical segmentation of customer code,
and allows reads of other device blocks while one is
erasing (Le. via the erase-suspend/resume commands).

3-603

intel·

ENGINEERING
REPORT

ER-29·

November 1992

The Intel 2/4 Mbit Boot Block
Flash Memory Family

ALAN BUCHECKER
PETER HAZEN
MEMORY COMPONENTS DIVISION

Order Number: 294013-001
3-604

The Intel 2/4 Mbit Boot Block Flash Memory Family
CONTENTS

PAGE

INTRODUCTION . ...................... 3-606
Word/Byte-Wide Versions .............. 3-606
Byte-Wide Versions .................... 3-606
TECHNOLOGY OVERVIEW .........•. 3-606
DEVICE ARCHITECTURE ............. 3-607
Array Organization ..................... 3-607
Block MemorY Maps .. ~ ................ 3-608
Write/Erase Automation ................ 3-608
Command User Interface (CUI) ......... 3-608
Write State Machine (WSM) ............ 3-611
Status Register ......................... 3-612
Internal Oscillator ...................... 3-613 .
Supply Voltage Sensing ................ 3-613
Deep Power-Down and Device Reset ... 3-613
Automatic Power Savings .............. 3-614
Block Erase ............................. 3-614
Erase Suspend/Resume ............... 3-616
Word/Byte Write ...... ~ ................ 3-616

CONTENTS

PAGE

DEVICE CHARACTERIZATION ........ 3-616
A.C. and D.C. Parameters .............. 3-616
Energy/Power Consumption ............ 3-617
Word/Byte-Write and Block-Erase
Times ................................ 3-617
DEVICE RELIABILITY ................. 3-617
Word/Byte-Write and Block-Erase
Cycling ............................... 3-611
Data Protection ........................ 3-618
SUMMARY ............................ 3-618
OTHER REFERENCES .......... ...... 3-618

3-605

ER-29

INTRODUCTION
The ETOXTM III (EPROM tunnel oxide) 2/4 Mbit
family of Intel boot block Flash Memories are a continuation of boot-top Itlld boot-bottom architectures first
introduced in the I Mbit 28FOOIBX-T and
28FOOIBX-B devices. Top (-T) and bottom (-B) boot
block offerings provide compatibility for micl,'oprocessors that boot from high or low memory addresses.
All versions of this new family provide a 16 Kbyte
hardware-protected boot block, two 8 Kbyte p~ameter
blocks and a 96 Kbyte main block. The 2 Mbit products have an additional 128 Kbyte main block, while
4 Mbit offerings contain three additional 128 Kbyte
main blocks.
.
Flash memories combine inherent non-volatility with
in-system alterability of device contents. Selective block
erasure allows manipUlation of data contents within
one of the seven (or five) mini-aiTay segments without
affecting data stored in ,the other six (or four). Advances in process control have allowed development of
a double-polysilicon single-transistor flash memory capable of 100,000 write/erase cycles per block. The
2/4 Mbit boot block family electrically erases all bits in
a block via electron tunneling. The EPROM programming mechanism of hot-electron injection is employed,
for high-performance electrical word/byte write as required for computing and embedded applications.
An integrated Command User Interface (CUI) simplifies microprocessor control of device operations (word/
byte write, block erase, erase suspend/resume; Status
Register read/clear, array read and device identifier
read). The internal Write State Machine (WSM) controls all functions and circuits associated with word/
byte-write and block-erase operations, including pulse
widths and repetition, timeout delays, erase preconditioning and margined verifications. The WSM continually updates the internal Status Register during these
functions. The Status Register is read via outputs
DQo-DQ, providing feedback of WSM activitieS.
The CUI and Status Register interface to power-up/
down-protection circuitry, address/data latches and the
WSM. This interface augments first-generation flash
memory circuitry to optimize Intel's 2/4 Mbit boot
block f!lII1ily for microprocessor-controlled wordlbyte
.write and block erase.
A deep-power-down mode enables extremely low power consumption to augment reduced-power standby operation. An automatic power savings' feature reduces
Icc during read mode.

A 60 ns access time (tACc) results from a memory cell
current of approximately 70 p.A, low-resistance polysilicide wordlines strapped with metal, advanced scaled
periphery transistors and improved circuit techniques.
The dense one-transistor cell structure, coupled with
high array efficiency, yields a 4 Mbit die measuring 295
by 331 mils and a 2 Mbit die measuring 295 by 221
mils.

Word/Byte-Wide Versions
Intel's 28F400BX is a 4,194,304-bit non-volatile memory organized as either 262,144 words (256K x 16) or
524,288 bytes (512K x 8). A dedicated BYTE control
input provides selection of the desired input/output
(I/O) configuration (either x16 or x8) for read operations and data writes.
Intel's 28F200BX is a 2,097, 152-bit non~volatile memory organized as either 131,072 words (128K x 16) or
262,144 bytes (256K x 8). This device also provides
BYTE control of I/O configuration.
Initial offerings of the 28F400BX and 28F200BX are in
the 44-lead Plastic Small-Outline Package (PSOP).
These products will also be offered in 56-lead Thin'
Small-Outline Package (TSOP). '
.

.Byte-Wide Versions
Intel's 28FOO4BX is a 4, 194,304-bit non-volatile memory arranged as 524,288 bytes (512K x 8). Intel's
28FOO2BX is a 2,097,152-bit non~volatile memory arranged as 262,144 bytes (256K x 8).
With lower pin counts compared to their'x8/xl6 equivalents, the 28F004BX and 28FOO2BX allow housing in
the smaller 4O-lead TSOP.

TECHNOLOGY OVERV.lEW
Intel's ETOX III Flash Memory technology incorporates advances from ETOX I and ETOX II processes,
and leverages over two decades of EPROM manufacturing experience. Using advanced 0.8 p.m double-poly·silicon N-wel1/P-well CMOS technology, the 2/4 Mbit
boot block flash memories employ a 2.5 p.m x 2.9 p.m
.single-transistor cell affording array density equivalent
to comparable EPROM technology, and twice that of
Intel's ETOX II procesS. The ETOX III flash memory
cell is identical to 0.8 p.m EPROM, except for an additional source implant which optimizes erase performance. Figure 1 shows a cross-section of the flash memory,cell.

3-606

ER·29

SECOND LEVEL
POL VSILICON

Each array plane is divided into eight I/Os for the
28F400BX/200BX. The upper plane consists of the
high-byte I/Os (DQs-DQ1S), while the lower plane
consists of the low-byte I/Os (DQo-DQ7)' During
byte-wide operation (BYTE = "0") the high-byte I/Os
are multiplexed through the low-byte I/Os via A-I
decoding. Data for 1/00 is stored in the left-most 256
columns (or 128 columns for the 28F200BX) of the
lower plane, with the next 256 columns (or 128) storing
data for I/O\> etc. Data for 1/08 is stored in the leftmost 256 (or 128) columns of the upper plane, with the
next 256 (or 128) columns storing data for 1/09, etc.

FIRST LEVEL
POLVSILICON
(FLOATING)

GATE OXIDE

294013-1

Figure 1. Flash Memory Cell

High-quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells
within the selected block are simultaneously erased via
Fowler-Nordheim tunneling. Applying 12V to block
source junctions and grounding the select gates erases
all cells within that block. The internal WSM controls
the automated block-erase algorithm, including preerase conditioning (i.e. pre-programming all block bits)
and margin verification, in response to user requests
relayed by the CUI. WSM-controlled block erasure, including pre-programming, typically ranges from 1.0 to
2.4 seconds depending on the size of the block selected.
Wordlbyte write is accomplished with the standard
EPROM mechanism of channel hot-electron injection
from the cell drain junction to the floating gate. Bringing both the select gate and the cell drain to high voltage initiates programming. The WSM regulates the internal wordlbyte-write algorithm, including margin
verification, after the correct·· command sequence is
written and decoded. Wordlbyte write typically requires 9 fJ:s.

DEVICE ARCHITECTURE
Array Organization
Layout of the 2/4 Mbit boot block family is· segmented
as two array planes (see Figure 2). This organization
allows improved access times via minimal internal busing, thus balancing the need for high speed with the
requirement of small die size for cost-effective solutions. In the 4 Mbit family, each array plane is 1024
rows by 2048 columns. For the 2-Mbit family, each
array plane is 1024 rows by 1024 columns. Access time
is reduced by limiting column length to 1024 cells. The
polysilicon rowis strapped in metal every 512 columns
to reduce wordline delay. Two row decoders run vertically along-the array plane sides, and column decoders
run horizontally between amiy planes. Figure 36 shows
a die photo of the 4 Mbit family.

For the dedicated byte-wide products (28FOO4BX/
002BX), data for a given 110 is divided between the
upper and lower array planes as decoded by AlO. Data
for 1/00 is stored in the left-most 256 columns (or 128
columns for the 28FOO2BX) of both the upper and lower planes, with the next 256 columns (or 128) in each
plane storing data for I/O\> etc.
Since each I/O is a grouping of adjacent columns (256
or 128), the independently-erasable blocks (seven or
five) are segmented within each I/O. Each I/O in the
4 Mbit family is divided into seven blocks; including a
16 Kbyte boot block, two 8 Kbyte parameter blocks,
one 96 Kbyte main block and three 128 Kbyte main
blocks. Each I/O in the 2 Mbit family is divided into
five blocks; including a 16 Kbyte boot block, two
8 Kbyte parameter blocks, one 96 Kbyte main block
and one 128 Kbyte main block. Each block source is
electrically isolated from the sources ()f the other six (or
four) blocks. This allows individual block erase without
altering data in the other blocks.
Addresses A9-Ao select one of 1024 rows. Row address lines are decoded sequentially for selection. Table
3 lists row address bitmaps.
Columns are decoded by AIS-AlO for the 28FOO4BX,
A17-:-AlO for the28F400BX and 28FOO2BX, and A16AIO for the 28F200BX. 4 Mbit family columns are
numbered 0-255 for each I/O, and 2 Mbit columns are·
numbered 0-127 for each I/O. Table 4 lists column
address bitmaps.

3-607

infel .

ER-29

'"...0

I/O 8

Q

f:l

c

~

0

'"

I

0"

0"

I/o 11

I/O 12

"~'I 0"

0"

I/o 13

I/o 1411/0 151

"'I "'I "'I "'I
0"

0"

0"

I/O 5
(I/O 5)·

I/o 6
(I/O 6)·

I/O 7
(I/O 7)·

COLUMN DECODER

I/o 6

f:l
Q

(I/O 0)·

Q

I/o 10

"'1 "'I 'V, "~'I

...'"
0

I/o 9

I/o 1
(I/O 1).

I/o 2
(I/o 2)·

I/o 3
(I/O 3)·

I/o 4
(I/O 4)·

~

0

'"
294013-2

Figure 2. 2/4 Mbit Boot Block Family Array Organization ((1/0#)* Denotes 28F004BX/002BX I/0s)

Block Memory Map
. Top (-T) and bottom (-B) boot block offerings have
block address maps which are inverted from one another .to provide compatibility for microprocessors that
boot from high or low memory addresses. Figures 3, 4,
5 and 6 show 28F400BX-TIB, 28F200BX-TIB,
28FOO4BX-TIB and 28FOO2BX-TIB memory maps.
The addresses shown in Figures ·3 and· 4 for the
28F400BX-TIB and 28F200BX-TIB, decode two bytes
of data. A-I decodes between the two bytes when
BYTE is low.

Write/Erase Automation
Intel's 2/4 Mbit boot block Flash Memories contain an
on-chip Command User Interface. Write· State Machine, Status Register and address/data latches to dramatically simplify user interface. This combination of
functional . units reduces microprocessor control

complexity of wordlbyte-write block-erase, erase-suspend/resume, Status Register-read/clear, ID-read and
array-read operations. Figures 7 and 8 show
28F400BX/200BX and 28FOO4BX/OO2BX block diagrams.

Command User Interface (CUI)
. The CUI consists of a command decoder and command
register. User requests are decoded and latched in a
microprocessor write cycle controlled by Chip Enable
(CE) and Write Enable (WE). Status Register-read/
clear, ID-read and array-read commands are directly
handled by the CUI. The CUI also accepts wordlbytewrite, block-erase and erase-suspend/resume commands. WE's rising edge latches address, command and
data-in registers, and· requests WSM initiation of the
selected operation. These on-chip address, command
and data latches, controlled by the CUI, minimize system interface logic and free the system bus.

3-608

·infel .

ER·29

28F400BX·T

28F400BX·B

3FFFFH

3FFFFH
16 Kbyte BOOT BLOCK

3EOOOH
3DFFFH

128 Kbyte MAIN BLOCK
8 Kbyte PARAMETER BLOCK
30000H
2FFFFH

3DOOOH
3CFFFH
3COOOH
3BFFFH

8 Kbyte PARAMETER BLOCK
128 Kbyte MAIN BLOCK
96 Kbyte MAIN BLOCK

20000H
1FFFFH

30000H
2FFFFH

i 28 Kbyte MAIN BLOCK
128 Kbyte MAIN BLOCK
10000H
OFFFFH

20000H
1FFFFH

96 Kbyte MAIN BLOCK
04000H
03FFFH

128 Kbyte MAIN BLOCK

8 Kbyte PARAMETER BLOCK
10000H
OFFFFH

03000H
02FFFH

8 Kbyte PARAMETER BLOCK

02000H
01FFFH

128 Kbyte MAIN BLOCK

16 Kbyte BOOT BLOCK
OOOOOH

OOOOOH

Figure 3. 28F400BX-T /B Memory Maps
28F200BX-B

28F200BX-T
1FFFFH

1FFFFH
16 Kbyte BOOT BLOCK
1EOOOH
1DFFFH
1DOOOH
1CFFFH
1COOOH
1BFFFH

128 Kbyte MAIN BLOCK
8 Kbyte PARAMETER BLOCK
10000H
OFFFFH

8 Kbyte PARAMETER BLOCK

96 Kbyte MAIN BLOCK
96 Kbyte MAIN BLOCK

04000H
03FFFH

10000H
OFFFFH

03000H
02FFFH
02000H
01FFFH

128 Kbyte MAIN BLOCK

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK
OOOOOH

OOOOOH

Figure 4. 28F200BX-T /B Memory Maps

3-609

ER-29

28Fo04BX-T

28FOO4BX-B

7FFFFH

7FFFFH

6 Kbyte BOuT BLOCK
7COOOH
7BFFFH
7AOOOH'
79FFFH
78000H
77FFFH

128 Kbyte MAIN BLOCK
8 Kbyte PARAMETER BLOCK
60000H

5FFFFH

8 Kbyte PARAMETER BLOCK

128 Kbyte MAIN BLOCK
98Kbyte MAIN BLOCK
40000H
3FFFFH

aoOOOH
5FFFFH

128 Kbyte MAIN BLOCK
128 Kbyte MAIN BLOCK
20000H
1FFFFH

40000H
3FFFFH

98 Kbyta MAIN BLOCK
128 Kbyte MAIN BLOCK
08000H
07FFFH
20000H
1FFFFH

06000H
05FFFH
04000H
03FFFH

128 Kbyte MAIN BLOCK
OOOOOH

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

18 Kbyta BOOT BLOCK

OOOOOH

Figure 5; 28FOO4BX-T/B Memory Maps
28FOO2BX-T

28Fo02BX-B

3FFFFH

3FFFFH
16 Kbyte BOOT BLOCK

3COOOH
3BFFFH
3AOOOH
39FFFH
38000H
37FFFH

12& Kbyte MAIN BLOCK
8i(byta PARAMETER BLOCK
20000H
1FFFFH

8 Kbyte PARAMETER BLOCK

98 Kbyte MAIN BLOCK
96 Kbyta MAIN BLOCK

08000H
07FFFH

20000H
,1FFFFH

06000H
05FFFH
04000H
03FFFH

128 Kbyte MAIN BLOCK

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

16 Kbyte BOOT BLOCK
OOOOOH

OOOOOH

Figure 6. 28F002BX-T/8 Memory Maps

3-610

intel .

ER·29

This eliminates the need for system timers, and frees
the microprocessor to service interrupts or perfonn other functions during device wordlbyte-write or blockerase operations.

Write State Machine (WSM)
The WSM processes word/byte-write, block-erase and
erase-suspend/resume requests received from the CUI.
The WSM rejects word/byte-write and block-erase requests if the WSM is currently busy,if Vpp is not at
high voltage (12V) or if the Low Vpp Status Register
flag is set (i.e. not cleared from a previous low-voltage
condition).
The WSM co~sists of an integrated oscillator and control circuitry. It generates signals which control the
word/byte-write, block-erase, erase-suspend/resume
and verify circuits. It also receives feedback from these
circuits, allowing Status Register update.· The WSM
and 'associated circuits perform the equivalent of firstgeneration flash memory program and bulk-erase algorithms automatically.

The WSM provides feedback to the CUI to determine
when a given command is valid. Although nearly all
commands are available when· the WSM is inactive,
only status read is valid while the WSM perfornls a
wordlbyte-write operation. During block erase, only
the read-status and erase-suspend commands are avail.able. Read-array, read-status, and erase-resume commands are valid with the WSM in an erase-suspended
state. Invalid operations are interpreted as the read-array command when the WSM is inactive or erase suspended, and as the read-status command when the
WSM is active in word/byte write or block erase.

r-~-'~4-~----cr

1+---1.....- - - - WE
1+---01>------ DE
Lr-.....,~-------PWO

.. - ;"7 (28F4008X)
Ao - ;.,. (28F200BX)

294013-3

Figure

r. 28F400BX/200BX Block Diagrams

3-611

in1:et

ER-29

Secondly, allowing system software to control reset
,adds flexibility to the way this device may be used. The
CPU may write several wordslbytes, or erase several
blocks back-to-back, .while po!!ing SR.7 to determine
when the next wordlbyte-write or block-erase command can be given. When all wordslbytes are written,
or all blocks erased, the system polls the other status
flags to determine if all operations were successful, or if
an error occurred. While other approaches require the
controlling microprocessor to watch for non-completion of write or erase within a specified time to indicate
an error, this implementation requires no external system timers or software timing loops. As such, the system can reduce its polling overhead while still identifying any potential error conditions.

Status Register
The internal Status Register contains a full complement
of activity status bits. These bits and their meaning
"I/O" are:
SR.7: WSM status (READY/BUSy)
SR.6: Erase-suspend status (ERASE SUSPENDED/
ERASE IN PROGRESS or COMPLETED)
SR.5: Block-erase status (ERROR/SUCCESS)
SR.4: Wordlbyte-write status (ERROR/SUCCESS)
SR.3:.Vpp status (LOW/OK)
All bits are set by the WSM, and read via the CUI. The
WSM can only set SR.3, SR.4 and SR.5; it cannot clear
them. They remain set until the CUI processes a clear
Status Register command. There are two reasons for
operating in. this fashion. First is synchronization; the
WSM does not know when the host CPU has read the
Status Register, therefore does not know when to clear
it.

Status Register contents are driven to device outputs on
the falling edge of CE or Output Enable (O~ whichever occurs last in the read cycle. CE or OE must be
toggled to update Status Register contents.

r-~-'~l-Ll----CE

.....-I~~---iE

....~~----iii'

~~~-1~--~---PWD

.. - A"
.. - :."

(2",0049X)
(28,0029X)

g

5:m:
~~
~

v.,
~

~ ~~ 5~
~ ~:
: :~ ~!

..
~

i5
I
-.
~m

oo

~

,

;~

_OHD

294013-4

Figure 8_ 28F004BX/002BX Block Diagrams

3-612

infel .

ER-29

Internal Oscillator
The WSM is designed using clocked logic circuits. An
on-chip ring oscillator generates the clock signals. The
frequency ofa standard ring oscillator varies with processing, temperature and supply voltage. A proven design used on the 28FOOIBX-T/B, 28FOO8SA and
2/4 Mbit boot block family minimizes these variations.
The switching current of each stage in the ring oscillator is controlled by a current reference which varies
linearly with Vee. The trip point of each ring oscillator
inverter also varies linearly with Vee. These two effects
offset each other, and the resulting oscillator period is
proportional to RC with only a small dependence on
Vee·
An on-chip resistor sets the value of R. The gate capacitance of the inverters in the ring oscillator sets the
value of C. Process variations in these values are reduced by trimming the period of each oscillator during
manufacturing. The resistor is the only source of temperature variation.

Supply Voltage Sensing
Figure 9 shows. the LOWVee and LOWVpp generation circuits. Power supply voltages (Vee and Vpp) are
divided down and compared to a reference voltage. If
VREF is greater than the divided power supply voltage,
the LOWVee or LOWVpp signal is driven high. The
generated VREF level is supply-voltage independent to
the first order.
Positive power to the circuit is supplied by MI and M2.
MI and M2 sources are pulled up to the higher of
(Vpp - VttJ or (Vee - Vtw)· Vtn is the threshold of
an implanted N-channel device, about 0.9V. Vtw is the
threshold of a native N-channel device, about OV. This
scheme ensures that the circuit works regardless of the
applied, supply voltages.

If LOWVee is active, the CUI will not accept user
writes and resets to an array-read condition. The WSM
is similarly reset by LOWVee. The LOWVpp signal is
used by the WSM; ifVpp drops below the high-voltage
detector trip point during word/byte write or block
erase, the Status Register'S low Vpp bit is set and WSM
operation halts. The system must clear the Status Register before any subsequent word/byte-write or blockerase operations can succeed.

Deep Power-Down and Device Reset
The 2/4 Mbit boot block family incorporates a deeppower-down mode that reduces Icc an~ to typically 0.20 /LA and 0.07 /LA respectively. PWD low selects
deep power-down. When PWD is high, the device can
be placed in an active or standby mode depending on
CE's state.
Deep power-down is similar to standby except that all
circuits excluding the PWD buffer are turned off. This
mode greatly reduces power consumption, but requires
more time to transition the device into an active mode.
A read wake-up time (tPHQV) is required from PWD
switching high until output and sense circuitry become
fully functional and data can be read from the part.
Similarly, a write wake-up time (tpHwd is needed before the CUI recognizes writes. After this interval normal operation is restored; the CUI is reset to read-array
mode and the Status Register is cleared to 80H.
Figure 10 shows a diagram of the power-down circuit.
The TTL buffer formed by MI-M3 disables the lowpower detect circuits, the redundancy-address flash bits
and the CE TTL buffer formed by M4-M6. These circuits were always enabled in first-generation Intel flash
architectures. Tum-on delays of these circuits determine PWD access time and write specifications.

The LOWVee signal is used by the wordlbyte-write
and block-erase circuits, as well as the CUI and WSM.

LOW POWER
DETECT
REDUNDANCY

CHIP INTERNAL
RESET
N2

LOW Vee

LOW Vpp

294013-5

294013-6

Figure 9_ Low-Power Detector Circuit

Figure 10. Power-Down and Reset Functions
3-613

intel .

ER-29

PWD functions properly with TTL-level inputs. However,to attain IQwest possible power consumption, full
CMOS levels must be used. If the voltage on the gate of
M3 rises above its 0.9V threshold, M3 will tum on and
draw current. Input voltages in the 0.7V..,.0.9V range
could cause enough current· conduction in M3 to exceed the Icc deep-power-down current (IcCD) specification. This is why PWD's input voltage is specified as
GND ±0.2V.
PWD also functions as a hardware reset to the WSM
and CUI. If PWD is driven low ("0") during word/
byte write, block erase, or erase suspend, that operation
is aborted leaving the addressed memory locations in an
unknown state. The Status Register is cleared, and CUI
is set to array read. The aborted operation (wordlbyte
write or block erase) must be repeated with PWD inactive to obtain a valid condition in the memory array.
PWD reset should be restricted to system reset only (as
in the case of power supply failure), and.should not be
used as a standard. means to terminate wordlbyte-write
or block-erase operations. NOTE: Use the erase-suspend command to read another block (see the "Erase
Suspend/Resume" section).
This use of PWD during system reset is important with
automated write/erase devices. When the system comes
out of reset it expects to read from the flaSh memory.
Automated flash memories provide status information
when accessed during write/erase modes. If CPU reset occurs with no flash memory reset, proper CPU
initialization would not occur because the flash memory. would be providing the status information instead of
array data. Intel's Flash Memories allow proper CPU·
initialization following a system reset through the use
of the PWD input.

a

Automatic Power Savings
The 2/4 Mbit boot block flash memories include an
automatic .power-savings feature, that reduces ICC dur..
ing read mode. Within one access time (tACC or tcE>
after an address or CE switches, Icc automatically
powers down from the 60 rnA Icc CMOS specification
(or 65 rnA TTL specification) to less than I rnA. IcC
remains below I rnA until either CE or an address is
switched, or until the device is taken out of read mode.
This feature provides significant power savings for applications that access the device slower than theirspecified read access times.

Block Erase
Block erasure is achieved by a two-step write sequence.
The erase-setup code is written to the CUI in the first
cycle. Erase confirm is written in the second cycle. The
address supplied with the erase-confirm command is
latched and decoded internally by the device; erase is
subsequently enabled in that block. The second WE rising edge initiates the operation (WE-controlled write).
The WSM triggers the high-voltage flash-erase switch
connecting the 12V supply to the source of all bits in
the specified block, while all wordlines are grounded.
Figure 12 shows organization of the block source
switches. Fowler-Nordheim tunneling results in simultaneous erasure of all bits in the selected block.
The block source switch (shown in Figure II) controls
the source voltage of all bits in a particular block. During block erase, M2 is off and MI pulls the source to
Vpp. When not in erase, MI is off andM2 pulls the
source to ground. The high-voltage latch formed by
M4-M7 converts the low-voltage ERASE signal to a
high-voltage signal that controls Ml.

1.11

...----+-+ BLOCK
SOURCE
LOW Vee

)-6----------+----1

ERASE >----------_~_I ~'O---_I

294013-7

Figure 11_ Block Source Switch
3-614

infel"

ER-29

BOOT BLOCK
SOURCE

PARAMETER BLOCK 0
SOURCE

PARAMETER BLOCK 1
SOURCE

MAIN BLOCK 0
SOURCE

MAIN BLOCK 1
SOURCE

2 Mb

MAIN BLOCK 2
SOURCE

MAIN BLOCK 3
SOURCE

4Mb I

294013-8

Figure 12. Array Erase Blocking

The tunneling that occurs during block erase requires
only a small amount of current. However, the initial
current required to charge the block's cumulative
source capacitance to the erase voltage is large. Supply
decoupling design practices minimize the system impact of the source charging.
The LOWVee signal protects the array from erasure
when Vpp is at a high voltage, but Vee is below the
write/erase lockout voltage (VLKO). When this occurs,
M3 pulls the block source to ground. The high-voltage
latch is forced by M8 into the state that turns MI off.
Vpp is continually monitored during all phases of the
block-erase operation. If Vpp falls below the trip point
of its high-voltage detect circuitry, erasure will not occur (or halts) and Status Register Vpp status (SR.3),
block-erase status (SR.5) and WSM status (SR.7) bits
are set to "I".
.
If SR.3 is set (Low Vpp), WSM operation is inhibited.
The WSM will not execute further wordlbyte-write or
block-erasure sequences until the Status Register has
been reset by system software. Wordlbyte-write or
block-erase requests with error flags SR.4 or SR.5 set
are not inhibited, but the system loses the ability to
determine success. The clear Status-Register .command
resets these bits.

After receiving the block-erase command sequence, the
WSM automatically controls block pre-condition (programming all words to OOOOH within the chosen block),
erase pulses and pulse repetition, timeout delays, and
word-by-word verification of all block addresses (sequentially checked via the address counter) using an
alternative sensing reference to verify margin. The internal erase and verify operations continue until the entire block is erased. A read cycle applied to the part
following the block-erase command sequence outputs
Status Register contents; system software can poll the
Status Register to determine when block erase has successfully completed. Following block erasure, the device remains in Status Register read block erasure, the
device remains in Status Register read mode; a read-array command must be written to the device to access
array data.
If the erase-setup command is followed with. a command other than erase confirm, the device will not
erase. The WSM sets both wordlbyte-write status and
block-erase status bits in the Status Register to indicate
an invalid sequence.

3-615

inlet

ER-29

Erase Suspend/Resume
Erase suspend allows the system to interrupt block
erase to read data from another array block. The ability
to suspend erase and read data from another block offers the flexibility required for embedded applications.
Upon receiving the erase-suspend command. the CUI
requests that the WSM pause at one of several predetermined points in the algorithm. Upon reaching a suspend point, the WSM sets SR.6 (erase~suspend status)
and SR.7 to "1". The system must poll the Status Register to determine if the suspend has been processed or
the block erase has actually completed. Block-erase
completion is indicated by SR.6 cleared to "0" and
SR.7 set to "1". Read bus cycles default to Status Register read after issuing the erase-suspend command.
Once suspended, the WSM asserts a signal t~ the CUI
which allows response to the read-array, read-status,
and erase-resume commands. The system can write the
read-array command allowing read access to blocks
other than that which is suspended. The WSM continues to run, idling in a suspended state, regardless of all
control inputs except PWD. PWD driven low immediatelyshuts down the WSM, aborting the suspended
erase operation.
The erase-resume command must be issued upon completion of reads from other array blocks to continue
block-erase operation. The WSM then clears SR.6 and
SR.7, and resumes erase operation from the suspension
point. Read cycles following the erase-resume command output Status Register data.
See the appropriate data sheet (as listed under the
"Other References". heading of this document) for a
description of eratta relating to Erase Suspend/Resume.
Word/Byte Write

Wordlbyte write follows a flow similar to block erase.
The wordlbyte-write-setup command is first written to
the CUI. A second write cycle loads address and data
latches. The rising edge of the second WE pulse requests that the WSM initiate activity, applying high
voltage to the gates and drains of all bits to be written.
Unlike block erase, wordlbyte write will proceed regardless of what data is applied on the second CUI
write cycle; ,however writing data FFFFH (or FFH)
does not modify memory contents.

wordlbyte-write verify checks that all 'bits written to
zero have been correctly modified; it does not check
bits specified as one. Wordlbyte write cannot change
existing zeros to ones; this can only be accomplished by
erase.
Read bus cycles following wordlbyte-write operations
output Status Register data. System software, polling
the Status Register, is informed of status through bits
SR.3, SR.4, and SR.7, The read-array command must
be written to the CUI following wordlbyte ·write to
access array data.
In a scenario similar to that described under block erasure, wordlbyte write does not occur (or halts) ifVpp is
detected low. In such a case SR.3, SR.4, and SR.7 are
set high, and no further writes can take place until the
Status Register is cleared by the clear Status Register
command.

DEVICE CHARACTERIZATION
AC and DC Parameters
Figures 14 through 35 show graphs of several device
parameters as a function of temperature and supply
voltage,
In particular, note Figure 14 which shows typical read
performance tA VQV (tACe) of the 28F400BX, which is
representative of the 2/4 MBit boot block flash family,
as a function of Vcc and ambient temperature. tELQV
(tCE) in Figure 15and tGLQV (tOE) in Figure 16 are
also of particular interest. Access times tAVQV, tELQV,
and tGLQV are specified and tested with an output load
of 100 pF; decreased output load capacitance improves
device operation.
Table 1 shows typical supply currents for several oper.
ating modes.

Like block erase, the WSM controls program pulses
and pulse repetition, timeout delays andwordlbyte verification. Wordlbyte write and verify (with alternate
sensing reference and internally-generated verify volt"
age) continue until the wordlbyte is written. Internal

3-616

Table 1 RMS Current Values

Mode

ICC
(Vee = 5.0V,
CMOS Inputs)
x8

x16

Ipp
(Vpp = 12V)

Read (6 MHz)

23mA

25mA

100 jJ.A

Write

20mA

22mA

10mA

Block Erase

15 mA

15 mA

12 mA

Standby

50jJ.A

SOjJ.A

100 jJ.A

Deep Power·Down 0.20jJ.A 0.20jJ.A

0.07 jJ.A

intel.

ER-29

Energy/Power Consumption

DEVICE RELIABILITY

The system designer may be concerned with power consumption during block erase and word/byte write. Figure 32 shows Icc and Ipp during block erase. Figure 33
shows Icc and Ipp during word/byte write.

Word/Byte-Write and Block-Erase
Cycling

Word/Byte-Write and Block-Erase
Times
The 2/4 Mbit boot block family and 28FOO8SA advance word/byte-write and block-erase performance
compared to previous flash memories. The on-chip algorithm is improved over the 28FOOIBX to take advan.tage of process enhancements. This improvement· is
most apparent when compared to first-generation flash
parts with externally controlled algorithms. First-generation device times shown in Table 2 assume optimal
system overhead, and as such are absolute best case.

One of the most important reliability aspects of the
2/4 Mbit boot block family is its capability of 100,000
write/erase cycles per block. Destructive oxide breakdown has been a limiting factor in extended cycling of
thin-oxide EEPROMs. Intel's ETOX Flash Memory
technology extends cycling performance through:
• Improved tunnel-oxide processing that increases
charge-carrying capability tenfold.
• Significantly reduced oxide area under stress that
minimizes probability of oxide defects in the region.
• Reduced oxide stress due to a lower peak electric
field (lower erase voltage than EEPROM).

Table 2. Word/Byte-Write and Block-Erase
Performance vs Previous Devices
Device

Word/ByteWrite Time

Block-Erase
Time/ # Bytes

Erase Time
per Kbyte

SECOND-GENERATION FLASH MEMORY DEVICES(l)
2BF400BX

9 JJ.s

2.4s/12BK

19 ms

2BFOO4BX

9 JJ.s

2.2s/96K

23 ms

2BF200BX

9 JJ.s

1.0s/16K

63 ms

2BFOO2BX

9 JJ.s

1.0s/BK

125 ms

2BFOOBSA

9 JJ.s

1.5s/64K

23ms

2BFOO1BX

1B JJ.s

3.Bs/112K
2.1s/BK
2.1s/4K

34ms
256ms
513 ms

FIRST-GENERATION FLASH MEMORY DEVICES(2)
2BF020

16.5 JJ.s

6.Bs/256K

27ms

2BF010

16.5 JJ.s

3.9s/12BK

30ms

2BF512

16.5 JJ.s

2.4s/64K

37ms

2BF256A

16.5 JJ.s

1.6s/32K

51 ms

NOTES:
1. Typical measured time.
2. Times calculated based on typical erase and precondition pulse requirements,
with minimum write timings. Calculations are described in Figure 13.

3-617

ER-29

Reliable wordlbyte-write and block-erase cycling requires proper selection of the maximum erase threshold
voltage (Vt), and maintenance of a tight distribution.
Maximum erase Vt is set to 3.4V via the internal blockerase algorithm and verify circuits. Tight erase Vt distribution gives an order of magnitude of erase-time
margin to the fastest erasing cell, with virtually identical erase Vt distributions at I and 10,000 cycles (Figure
34). Program Vt distribution is similarly consistent over
cycling (Figure 35).

Data Protection
The 2/4 Mbit boot block family offers protection
against accidental block erasure -or wordlbyte write
during power transitions. Internal circuitry creates a
device insensitive to Vpp/Vee supply power-up/down
sequencing.
Vpp ~ VPPLMAX locks out wordlbyte-write and
block-erase circuits. Vee ~ VLKO disables CUI command writes, resets the CUI to array-read mode, and
holds the WSM inactive. The system designer must still
guard against spurious command writes for Vee >
VLKO when Vpp < VPPLMAX.

SUMMARY
Intel's 214 Mbit boot block Flash Memory family contains features that optimize this product group for computing and embedded applications. These features include hardware-implemented write/erase protection of
the boot block, specialized array blocking, dedicated
x8 and x8/16 user-configurable versions, automation
of wordlbyte write and block erase, erase suspend for
data read, deep-power-down/automatic-power-savings
modes and a write/erase Status Register. With simple
microprocessor interfacing and software command sequences, this family is the non-volatile computing and
embedded solution of choice for today's designs.

OTHER REFERENCES
Related documents of. interest to readers of this engineering report:
28F400BX-T/B, 28FOO4BX-T/B; "4 Mbit Flash Memory Family" Data Sheet (Order #290450)
28F400BX-TL/BL, 28FOO4BX-TL/BL; "4 Mbit Flash
Memory Family!' Data Sheet (Order #290451)

Several strategies are available to prevent data modification in the 2/4 Mbit family. The CUI provides a degree of software write protection since memory alteration occurs only after successful completion of a twostep write sequence. WE and CE must both go active to
perform this sequence; driving either high inhibits command/data writes. Secondly, the system can place the
device in deep-power-down mode (PWD = VId to
disable command writes, reset the CUI to array-read,
mode, and hold the WSM inactive, effectively protecting array data and providing a way to reset the flash
memory during system reset conditions. Finally, the
system designer may switch Vpp to VPPH when memory updates are required.

28F200BX-T/B, 28FOO2BX-T/B; "2 Mbit Flash Memory Family" Data Sheet (Order #290448)
28F200BX-TL/BL, 28FOO2BX-TL/BL; "2 Mbit Flash
Memory Family" Data Sheet (Order #290449)
ER-28 "ETOXTM III Flash Memory Technology" Engineering Report (Order #294012)
AP-341 "Designing an Updatable BIOS Using Flash
Memory" (Order #292077)
AP-363 "Extended Flash BIOS for Portable Computers" (Order #292098)

3-618

infel~

ER-29

SUPPLEMENTARY INFORMATION
FORMULA:
b =
n =

# bytes in a block (256K, 128K, 64K, 32k)

75

# of erase pulses required (90 pulses)

70

w = Time for a write cycle (150 ns, tAVAV)
v = Time to verify (6055 ns, tWHGL + tGLQV)
p = Program pulse width (10 ,...s, tWHWH1)
one pulse programming assumed
e = Erase pulse width (10 ms, tWHWH2)

65

~

60

Cii'
.5
()
()

-<

Precondition and precondition verify time is:

55
50
45

'"
I"

"'I~

...........

40

"

"'A... ~ r--....,
I'-,

'R.

35

~ r-.
"'I'--, i-.....

... re-

~

N

I-I~

30
4.0 4.2 4.4 4.6 4.B 5.0 5.2 5.4 5.6 5.B 6.0
Vee (V)

+ e)

294013-9

Passing erase-verify, all bytes:
b (w

-- --

.::::: ,.... I-w.
r--...

.",.

Last erase pulse:
(1) (2w

~100oe

"'''a

b(2w+p+v)

Erase/verify, each loop where some byte
does not pass verify:
(n -1) (2w + e + v)

-0- -40°C
-0- ooe
-lr- B50e

Figure 14. tAVQV (tAee)
va Vee and Temperature

+ v)

Total time can be summarized as:
b (3w + P + 2v) + n (2w + e + v) - (v)

or substituting in times-for write, verify,
program and erase pulse' widths:
b (22.56 x 10- 6) + n (10.006355 x 10- 3) (6.055 x 10- 6) Seconds

Figure 13. Erase Time Calculations for
First-Generation Flash Memories
80
75
70

28

~

,,~

65

45
40
35

26
24

~100oe

22

~ i'w

60

1'\\ :::-. r----.

Cii'
.5 55

'" 50
..Y

-0- -40°C
-0- ooe
-lr- 85°C

"'" r-s...
"-

"

!'.::t.

-

'lL....:

""'--t ~ --

-

..9

~ ..........

b

~

~ s.....

Cii'
.5

-v-

1B

14
12

r--t

-0- -40°C
-0- ooe
-lr- B50e

.~~
I~

~100oe

~

20

.16

"--1

~

'\.

"\ ~

i'\.

"

"-

~~
........

I&-

~ :t:- t--

r'B. '"~ ~
""'1:1 - - I

I'--.... iPL

..

_

10
4.0 4.2 - 4.4 4.6 4.B 5.0 5.2 5.4 5.6 5.B 6.0

30
4.0 4.2 4.4 4;6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

Vee (v)

Vee (V)

294013-11

294013-10

Figure 16. tGLQV (tOE)
vs Vee and Temperature

Figure 15. tELQV (teE)
va Vee and Temperature

3·619

intel .

ER-29

~~tl

--I:1t- 85°C
-"r1- 1OooC

4U

I

38
...... .".
36
~
,..... 34
(I)
"'- ~
-5 32
~
til 30
f':
..9 28
I'....
"""'I
I'e..
26 ........
'E I-.
24
e.......
'15 __
22
20
S18
16
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

'"

""

-

rs..

....,

... r--

-..

r-

-14
-16
-18

~

-20

V

le- I-"'""'"

It-f"

a.-

I-a"
~

.- j,..e-

~
-22
I-'"""
-24 Ir'"
. / i""
Vi' -26
~ I--:;::. ~
-5 -28 ./'"
.....,
:r:
. / .......
-30
..9
A. V
V
-32
,
......
..".
-34
::,...
-36
/.
-38
-o--40 OC
//
-40
-0- OOC
-42
~850C
-44
....Jf1- 100°C
-46
4.0 4.2 4.4 4.6. 4.8 5.0 5.2 5.4 5.6 5.8 6.0

--

....

,

-

Vee (V)

Vee (V)

294013-13

294013-12

Figure 18. tWHoX (tOH WE)
vs Vee and Temperature

Figure 17. tOVWH (tos WE)
vs Vee and Temperature
40
38
36
"i'.. ~
34
v.i'..
32
i'..,;
30
28
...........
26
'"""24

-6

-0- -40°C

'" "

Vi'

-5
til

-<

22
20

~85°C

-12

r---,
-'1'...

"

.........

..... p....",

rs r-....

Vi'

...... I-l::I-...

-

-5

...... ...::-

""&

Ill..

..,...J l -

-10

....Jf1- 100°C

:r:

-14
-16

-< -18

~

It--""'
V

V ru-

-22

18
~
16
"""'" -~~
14
4.0 4.2 4.4 4.6 4.8 5.0 5.2 ·5.4 5.6 5.8 6.0

-24

~

l...eV

b-'

/

K"'

IA'I"

....... ~

I-- f.--'

V

~

-20

re- I--

-

~

-8

-0- OOC

L.A
~ :.----1"
,....-v

t::- / '

~

-0- -40°C
-0- OOC

~V

~85OC·

111'

....Jf1- 100°C

-26
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.86.0
Vee (V)

Vee (V)
294013-14

294013-15

Figure 20. tWHAX (tAH WE)
vs Vee and Temperature

Figure 19. tAvWH (tAS WE)
vs Vee and Temperature

3-620

infel·

ER-29

-14
~
-16
--'
-18
rB'"
~ Fe"
-20
V
...... V
.-22
Ir'"
~
-24
.lifT
......
~
III
-"
c -26 V
I:.W"
-28
:r
~ r'"
,....
.S' -30
k
-32
/ir
-34
.... r
-36
-38 ....... I
-0- -40°C
-40 ·1/
-0- OOC
-42
-lir- 85°C
/
-44
~100oC
-46
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

46
-0- -40°C
44 ~
-o-ooC
42 I'.
-lir- 85°C
40
~100oC
38
~ l".
36
"'lI t'-....
34
.....,
'iii'
="
c
32
.....
fA..... r'iIIII ·30
r'A.
I""..
.S' 28
.......
I"'&..
26
~N
..........
24
.......
22
""'-E
20
........ Is..
18
16
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

,

, .....

--

r--..

"

r-.....
r-...

re.

-

-

....

.....

-..,

vee (V)

Vee (V)

294013-17

294013-16

Figure 22. tEHOX (tDH eE)
va Vee and Temperature

Figure 21 •. tOVEH (tos eE)
va Vee and Temperature
40
38
36
34

'iii'
c

.....
III

..:<

-6

" ."

....,

-0- -40°C
-0- OOC
-lir- 85°C

-12

32
30
~
28
..........
a....;: ~
26
r--..... .........
"R..
24
......,
.........
'"8.
22
~
"S..
20
""'B """""'&- f-18
S16
"-of
14
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

...

....

....

-..

..... EI"'"

-10

~100oC

..... ...'1--

..... .:.

-8

-14
......
III

-

..s

'./ V

-16

:r
~
-< -18

-20
-22

--

-24

e- ~
./

,B""' .....

V

-

~~

,.....

~

l,..e V
,ItT

/. ~

.,;..Ar ~
.....,

..... ~

h V
7"

~

.......- ~

....

-o-.,.40 OC
-0- OOC
-lir- 85°C
~100oC

-26

4.0 4.2 4.4 4.6 4.8' 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)

Vee (v)
294013-18

294013-19

Figure 24. tEHAX (tAH eE)
va Vee and Temperature

Figure 23. tAVEH (tAS eE)
va Vee and Temperature

3-621

il1tel.

ER·29

-55

60
-D- -40°C
-0- OOC

55
50

.....111
..s
...

45

J

40
35
30

25

" r:: ...

~850C

~

"-

........ ......

'"

~

'<

~~

..... .....
~ ""iiI

--

~~

-40
-35

I:

-30

'"

•.9

~ ....:

..... 'e.

-';'-100 o C

.....E
.....

...: ::----. ~

[a....

~e5OC

-45

-';'-1'OOoC

~

-D--40oC
-o-OoC

-50

-25
-20

-

-.:.."""

-15

t'--t
20
4.04.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

V
~
,....e ...AIV
",.

V

./

V

~~

~

r

V

V

III

~
~

rtF

Vee (V)
294013-21

Figure 26.IOH TTL
va Vee and Temperature

......

'"E
.....

...
•.9

t""'"

........

-

.

-9.5

.......

-

-9.0

'<
-5

-D--40oC -o-OoC
....jjr- 85°C -';'-100 o C ....

-' ~

::...

-D- -40°C

V.

... .....

:::I

.... -,........
....

....... r-'

ct-"

~

~ A I-11
I-~
10
4.0. 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

t::::: ~

Vee (V)

4.i

~

-

........:

~ ;;,...I

-4.0
. -3.5
. .' 4.0

.-

....-' ~

~-5.0

-4.5

----

~

~ J:Io"

-7.5
-7.0

~ -6.5
(J -6.0
::c
•.9 -5.5

-

.,....-I

-0- OOC

-8.5 ....jjr- 85°C
-8.0 :-9-1000C~

..A-'

1t-'t:J"

sY

~

~

-

..a-

~

.., ~

-10
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

Figure 25. tWLWH (twp)
va Vee and Temperature

J:I

/'

~ f*'

294013-20

~

./

...A~ ~

( Vee (V)

23
22
21
20
19
18
17
16
15
14
13
12

IL

,...

r: t:;:.

-'r

4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0

Vee (V)
29~13-23

294013-22

Figure 27. IOL va Vee and Temperature
.
(VOL = O.45V) ,

.. Figure 28.IOH CMOS va Vee and Temperature

3·622

intel·

EA·29

75

75

70
65

./

60

.)r

50
~

45

u
_u

40
35

Jr

25

./

20
10

60

~

V

..)r'

55

~

/

50

~

./

30

15

65

~

55

-5

70

V

-5
Jl

V
-0- OOC

, -<>- 25°C
-IJ.- 70°C

r- rr- rr- r-

~~

45
40
35

~

30
25

.

)r
.)11'

20

15

It'

10

~

-0- OOC r--0- 25°C r-IJ.- 70°C r-

-

't'"

'

5

5
1 2 3 4 5 6 7 8 9 10 11 12 13 1415 16

1 2 3 4 5

FREQUENCY (t.4Hz)

FREQUENCY (t.4Hz)
294013-24

294013-25

Figure 29. Icc (RMS) vs Frequency
" x16 Operation

Figure 30. Icc (RMS) vs Frequency
,
x8 Operation

100
95
90
85

'M'

80

..~

75

-S

6 7 8 9 10 11 12 13 14 15 16

70
65
60

./'"

/
~

/

~
./

. / r"
. / r"'"

. /V

~ ~ ~ 28F400BX!28FOO4BX-70
~

28F400BX!28F004BX-80

55
50
30 50

100

150

200

250

OUTPUT CAPACITANCE (pF)
294013-26

Figure 31. Access Time vs Output Loading

3-623

ER-29

4smA
1

SmA
/DIV

-SmA
-200mS

1.8S

200mS/DIV

294013-27

36mA
Ipp ERASE

4mA
/DIV

..

1\ .

,111

-4mA
-200mS

-

~

lMl

.......

L

200mS/DIV

1.8S
294013-28

Figure 32. Icc and Ipp during Block-Erase Operation

3-624

ER·29

1BOmA

I

ICC WRITE

-

20mA
. /DIV

I"

I

\

I

-

'"

./

-20mA
-1 }£S

""'

~

.....

,

9 }£S

1 }£S/DIV

294013-29

.o45mA

I

Ipp WRITE

5m A
/0IV

, ~-

It

'-J

Iff
A

~

'"
1 }£S/DIV

9 }£S
294013-30

Figure 33. Icc and Ipp during Word-Write Operation

3·625

intel·

ER~29

Erased Vt Dlst. vs Cycling; Vpp

=;=

12V; TA = Room

99.999
>- 99.99
t99.9
::J
99

'I

I I

m

0

90

II

UJ

50

I

«
CD

0::
0..

>

i=

«
...J

AFTER 10k_
~
PiE CYCLES

,

10

::::>
~

::::>

u

1
0.1
0.001

~
.

.

,

0'r

lP r

.

I

,

~ BEFORE
CYCLING

,

0.00.20.40.60.81.0,1.2 1.4 1.6,1.82.02.22.42.62.83.03.23.4

V (V)
294013-31

Figure 34. Typical PrOCess Data for Erase Vt vs Cycles
Programmed Vt Dlst. vs Cycling; Vpp = 12V; TA == Room
j

99.999
>- 99.99
~'

m

«CD

I

99.9
99

UJ

>
i=
«
...J

50

~

u

/

'(
I
I---

AFTER 10k '
P
CYC~ES--

IE

10

/

'/~ r- BEFORE

rJ

1
0.1
,0.001

II
I

0.0

5.5

6.0

CYCLING -

I1

)

::::>

::::>'

/

./

, 090
0::
0..

~

I

I

~

6.5
7.0
V (V)

7.5

8.0

'8.5
294013-32

Figure 35. Typical Process Data for Program Vt vs Cycles

3-626

ER-29

294013-33

Figure 36. 28F400BX/28F004BX Ole Photoaraph

3·627

."

ER-29

Pin Nam••

Ao- A17

Address Inputs

000-0015

Data Inputs/Outputs

tm'E

Byte Enable

.~

. Chip Enable

PWD

Power-Down/Reset

rn:

Output Enable

WE
Vpp
Vee

Write/Erase Power Supply

GND

Ground

DU

Don't Use

NC

No Internal ConneCtion

Write Enable
Device Power Supply

28F2008X

28F2008X

Vpp
DU
NC
A7

.

~
. A2
Al

J5Wt)

WE

WE

Ae
As.

As.

As
'-4

Wo

"'0

A4

"'"'2,

7

"'.
"'5
"'.

AJ
AJ

"'4

'"

Ao
CE

CE

iffi

GND

GND

GND

OE
000
008
001
oog
002
0010
D~
0011

As

Ag
Al0
All
A12
A13
A4
As

Au
liE

DOt5 / "-,
00.

oQ.,

oa.
DOt
oa.

As
BYTE
GND
OO15/A -l

. DOt4

oa.

DOt.
DCls '.

~

DOt 0

DOt 2

DCls

D<4
vee

D!It,

Figure 37. PSOP Lead Configuration

3-628

~
0014
oos
0013
005
DQ12
DQ4

Vee

intel·

ER-29·

28F200BX
NC
NC
A,S
A'4
A'3
A'2
All
A'0

Ne
Ne
A,s
A,.A,3
A,2
A,1
A,o

NC
NC

Ne
Ne
WE
PWD
Ne
Ne
Vpp
DU
Ne
A,7

As
As

WE

J5Wl)
NC
NC

Vpp
DU
NC
NC
A7

As
As

~

As

As
As

As

~

A.A3

A2
Al
NC

A,
Ne

Aa

~

~O
3
4
5
6
7
8
9
10
11
12

NC

A,6
BYTE.
GHD
DQ1S/A_l

IX?
00,.~
DQ13
DQs
00,2·
DQ.Vee
Vee
DO,l
DQ3
00,0
002

28F400BX
56 - LEAD TSO P.. 44
14
43
15
42
16 14mm X 20mm 41
17
40
TOP VIEW
18
39
13

19
20
21
22
23
24
25
26
27
28

28F200BX

·NC

56
55
54
53
52
51
50
49
,48
47
46
45

Vee
Vee
DOll
DOa
0010
002
009
001
008

DOg

38
·37
36
35
34
33
32
31
·30
29

~

GND
DO,S/A-,
007
D014
006
DO'3
D05
DO'2
004

DO,
DOg
DOo

~
rn:

Of
GND

GND

CE

Ao

Ao

Ne
Ne

NC
NC
294013-35

28FOO2BX
AlB
A15
A14
A13
A12
All

As

~

,

J5WD
Vpp
DU
NC
A7

As
As
A4
As
A2
Al

28FOO2BX
~6
~S
~4
~3
~2
~,

As

~

WE
PWD
Vpp
DU

~8
~

As
As

,1.4
,1.3
,1.2

~

~O
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

28FOO4BX
40-LEAD TSOP
10mm X 20mm
TOP VIEW

40
39
38
37
3&
3.5
34
33
32
31

30
29
·28
27
21i
25
24
23
22
21

~7
GND
Ne
Ne

~O

D~

·aoe
DOs
DQ4
Vee
Vee
Ne
DQ3
DQ2
DO,

000
Of
GND

CE
Ao

A17
GND
NC
NC
AID
D07

DOs
D05
D04

Vee
Vee

NC
DOs
D02
DOl

~

GND
CE

An
294013-36

Figure 38. TSOP Lea~ Configuration

3·629

intet

. ER-29

Addresses A9-Ao seq~entially decode wordlines. Wordlines 0-lO23 serve the upper and lower array planes.
Table 3. Row Address Bitmap
A.;

4ft
....

A2

Al

....u

A_

\a'oidllne

0

'0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

0

2

0

0

0

1

1

3

0

0

1

0

0

4

0

0

1

0

1

5

0

0

1

1

0

6

AI!

As

A7

As

0

0

0

0

0

0

0

0

0

0

0

0

9

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

. As

0

0

0

0

0

0

0

1

1

1

7

0

0

0

0

0

0

1

0

0

0

8

0

0

0

0

0

0

1

0

0

1

9

0

0

0

0

0

0

1

0

1

0

10

0

0

0

0

0

0

1

0

1

1

11

0

0

, 0

0

0

0

1

1

0

0

12

0

0

0

0

0

0

1

1

0

1

13

0

0

0

0

0

0

1

1

1

0

14

0

0

0

0

0

0

1

1

1

1

15

0

0

0

0

1.6

0

0

0

0

0

1

0

0

0

0

0

1

•

•

•

•

•

0

0

0

0

0

1

1

1

1

31

•

•

•

•

•

•

•

•

..

1

•

•

1

1

1

1

1

1

0

0

0

0

1008

1

1

1

1

1

1

•

•

•

•

•

1

1

1

1

1

1

1

1

1

1

1023

3·630

infel·

ER-29

Columns for each block are distributed throughout the array in each I/O. For the 28F400BX/200BX, each I/O
contains 8 columns for the boot block, 4 columns each for parameter block 0 and parameter block 1,48 columns for
main block 0 and 64 columns for each of the remaining main blocks (main block 1 for the 28F200BX and main block
1-3 for the 28F400BX)/or a total of 256 columns per output.

NOTE: 28F400BX = Complete Table, 28F200BX = Shaded Area Only

3-631

ER-29

Columns for each block are distributed throughout the array in each I/O. For the 28FOO4BX/OO2BX, each I/O
contains 16 columns for the boot block, 8 columns each for parameter block 0 and parameter block 1,96 columns for
main block 0 and 128 columns for each of the remaining main blocks (main block 1 for the 28FOO2BX) and main
.
block 1-3 for the 28FOO4BX for a total of 256 columns per output.

NOTE: 28F004BX = Complete Table, 28F002BX = Shaded Area Only

3-632

RELIABILITY
REPORT

RR-60

November 1992

ETOX™II Flash Memory
Reliability Data Summary .

Order Number: 293002-008
3-633

ETOX™II Flash Memory Reliability Data Summary
CONTENTS

PAGE

THE IMPORTANCE OF
RELIABILITY ........................ 3-635

CONTENTS

P,A,GE

RELIABILITY DATA SUMMARy ....... 3-640

Quality =1= Reliability .................... 3-635

P/N28F256A .......................... 3-641

Monitor Program ....................... 3-635

P/N28F512 ............................ 3-643

ETOXTMII FLASH MEMORY
TECHNOLOGY OVERVIEW ......... 3-635

P/N/E 28F010 ...... ; .................. 3-646

Similarities with EPROM ................ 3-636

PIN/E 28F020 ......................... 3-649

Differences from EPROM .............. 3-636

APPENDIX A. FAILURE RATE
CALCULATIONS FOR 60% UPPER
CONFIDENCE LEVEL ............... 3-652

-

Erase/Write Cycling .................... 3-637

ETOXII FLASH MEMORY RELIABILITY
TESTING ............................ 3-637
Failure Rate Calculations ............... 3-638

APPENDIX B. FLASH MEMORY BIT
MAPS AND DIE PHOTOGRAPHS ... 3-657

3-634

RR-60

THE IMPORTANCE OF RELIABILITY
Reliability of the non-volatile memories in your end
product is critical to your total system reliability. The
use of Intel flash memories can make a difference. Reliability is not just tested, but designed into each component Intel manufactures.

Quality =1= Reliability
A quality component is one that meets your specification when received and tested. A'reliable component
continues to meet your specification even years after
you have shipped your product.
CONSIDER QUALITY VS. RELIABILITY

The true cost of any component involves more than just
the purchase price. The true component cost encompasses the initial purchase price, cost of rework during
system production, and the cost of field repairs due to
component failures. "Rework" costs during system
production are incurred prior to shipment of your end
product, and are a function of the quality of the component you purchase.,
'
R~pair .costs incurred in the field after end product
shipments, are a function of the reliability of the components. In addition to the increasing real cost of a
system field service call, there is the intangible cost of a
poor reliability reputation to the end use of your prod,uct. These costs depend upon the reliability of the components you purchase. Thus, reliability may impact
costs during the system lifetime more than the initial
quality of the components!

In-circuit reprogrammability of flash memories enables
the addition of production line testing and system level
screening. This capability, along with the inherent reliability of Intel flash components, provides your systems
with significant reliability enhancements. Soldering the
flash memory directly to the board enhances contact
integrity. Since flash memories do not have to be removed for reprogramming, reliability risk due to handling is eliminated upon device installation. In addition,
single socket testing reduces component handling during incoming inspection.

Monitor Program
Reliability is designed into each'component Intel manufactures. From the moment the design is put to paper,
stringent reliability standards must be met at each step
for a product to bear the Intel name.

Designing-in reliability, however, is only the beginning.
Ongoing tests must be conducted to ensure that the
original reliability specifications remain as valid in vol.ume production as they were when the device was first
qualified.
Intel's Reliability Monitor Program, devised to measur~ and control device reliability· in production, is
~vallable to our customers. The Monitor Program subJects all of Intel's technologies to a 48 hour dynamic
burn-in' at 125°C (with a portion of these devices continued for a 1000 hour lifetest) and provides answers
about device reliability that are not generally available
from limited testing programs. When test rejects are
encountered, failure analysis is performed on each
failed part. Isolating the fault and determining the failure mechanism is a critical part of the Monitor Program.
The primary objective is to deliver reliable, quality devices .. Actions .that Intel takes to meet this objective
may Include a process or design change, or added reliability screen. Each decision is made with our customers in mind so that they receive the parts-and the performance-that they ordered by specifying Intel. Reliability qualification assures that all new production materi~ meets Intel's reliability standards. The Reliability
Momtor Program ensures that these high standards are
continually maintained over the duration of a device's
life. This reliability improves the lifetime reputation of
your product, reducing the required number of field
service calls.

ETOX™II FLASH MEMORY
TECHNOLOGY OVERVIEW
Intel's ETOXTMH (EPROM tunnel oxide) flash memory technologies' consist of a non-volatile memory cell
that electrically erases in bulk array form. Derived
from Intel's CHMOS" H-E EPROM technology,
ETOXH flash memory technology combines the
EPROM program mechanism with the EEPROM
erase mechanism. The memory cell. is composed of a
s~ng1e transistor with a floating gate for charge storage,
like the conventional EPROM. The primary difference
between flash memory and EPROM cells is the flash
memory cell's thinner gate oxide, which enables the
electrical .erase capability. This report compares and
contrasts ETOXH technology and EPROM reliability,
describes Intel's flash reliability testing methodology,
and summarizes the reliability data of Intel's flash
memories.

'Intel's ETOXII flash memory process has patents pending.
"CHMOS is a patented process of Intel Corporation,

3-635

intet.

RR-60

VD :s VPP

n + DRAIN

DEPLETION
REGION

293002-1

Figure 1. ETOXTMII Flash Memory Cell during Programming (Side View)

n + DRAIN

293002-2

Figure 2. ETOX™u Flash Memory Cell during Erase (Side View)

Similarities with EPROM

Differences from EPROM

When in program mode, a flash memory behaves exactly like a conventional EPROM. A high drain voltage
generates "HOT" electrons that are: swept across the
channel. High voltage on the control gate attracts these
free electrons across the lower gate oxide into the floating gate, where they are trapped. See Figure 1. Thus,
ETOXII flash memory cells exhibit the same reliability
characteristics· as conventional EPROMs during program mode even with a thinner oxide. When in read
mode, a flash memory behaves just like an EPROM. .

With respect to functionality,the major difference between flash memory technology and EPROM technology lies with the erase mechanism. For EPROM cells,
ultraviolet light neutralizes the charge on the floating
gate, thus erasing the cell. For ETOXII flash memory
cells, an electric field across the lower gate oxide pulls
electrons off the floating gate to the source region, thus
erasing the cell. See Figure 2. This erase mechanism is
an EEPROM adaptation using "Fowler-Nordheim"(1)
tunneling..The electric field during erase is the only
new stress compared to EPROM that may impact overall reliability.

3~636

infel·

RR-60

Erase/Write Cycling
Failure mechanisms traditionally associated with cycling electrically erasable memories include charge loss
due to defective bits, destructive oxide breakdown, and
electron trapup. .ETOXII flash memory technology
minimizes these failure mechanisms by improvements
in process technology, reducing the electric field stressing the gate oxide, and using efficient erase/write algorithms to control programming and erasure.
OXIDE QUALITY
Thin oxides used in tunnelling have been a reliability
concern for electrically erasable memories. The quality
of the ETOXII tunnel oxide is approximately 10 times
better than that ·of other tunnel oxide approaches. This
breakthrough in tunnel oxide quality results from explicit process improvements and through the implicit
advantages of the ETOXII flash cell approach.
OXIDE BREAKDOWN
Oxide breakdown, due to erase/write cycling, has also
been a major reliability concern for thin oxide
tunnelling. ETOXII technology addresses this concern
by reducing the amount of stress placed on the tunnel
oxide during programming and' erasure. First, erasing
the flash cell involves tunnelling only through the gate/
source overlap, thus reducing the area under stress.
This, coupled with the improvement in oxide quality,
lowers the probability of an oxide defect. Secondly, the
flash cell is erased using a lower-voltage eraSe pulse,
resulting in lower stress on the tunnel oxide. This lower
electric field across the tunnel oxide (lOMV/ern versus
12MV/cm) yields a theoretical wear out time 108 times
longer than other EEPROM approaches.
ELECTRON TRAPUP
The phenomenon of electron trapup, the gradual reduction of electron mobility through the tunnel oxide, results in increasing program and erase times as cycling
occurs. The program and erase algorithms must apply
more pulses to add charge to or bleed charge off the
floating gate to ensure data retention and integrity.
This is seen as a failure to program or erase within the
algorithm's allowed time and not as a hard failure. The
Quick-Pulse Programming™ and Quick-Erase™ algorithms maintain an efficient program and erase time for
the specified number of cycles listed in the flash memory data sheets:

ETOXII FLASH MEMORY RELIABILITY
TESTING
Intel flash memories undergo comprehensive testing to
insure electrical reliability. This testing is done at qualification and during ongoing monitor checks.
Information on flash memory reliability testing procedures follows.
High Temperature S.ZSV Dynamic Lifetest-This test
is used to accelerate failure mechanisms by operating
the devices at an elevated temperature of 12SoC. During the test, the memory is sequentially addressed and
the outputs are exercised, but not monitored or loaded.
A checkerboard data pattern is used to simulate random patterns expected during actual use. Results of
lifetesting have been summarized along with the failure
analysis.
In order to best determine long-term failure rate, all
devices used for lifetesting are subjected to standard
INTEL testing. The 48 hour burn-in results are an indication of infant mortality and are not included in the
failure rate calculation. (See Figure 3 for typical burnin bias and timing diagrams.)
High Temperature High Voltage Dynamic LifetestThis test is used to accelerate oxide breakdown failures.
The test setup is identical to the one used for the dynamic lifetest except Vee is increased. The acceleration
factor due to this test can be found in the failure rate
prediction tables. This data plus the standard dynamic
lifetest data are used to calculate the 0.3 eV failure rate
(See Figure 4 for typical bias and timing diagram).
Data Retention Bake--This test is used to accelerate
charge loss from the floating gate. The test is performed
by subjecting devices containing a 98% programmed
pattern to a 2SO"C bake with no applied bias. In addition to data retention, this test is used to detect mechanical reliability problems (e.g., bond integrity) and
process instability.
Temperature Cycle--This test consists of cycling the
temperature of the chamber housing the subject devices
from -6SoC to + ISO"C and back. One thousand cy- .
cles are performed with a complete cycle taking 20 minutes. This test is to detect mechanical reliability problems and microcracks.

3-637

intel..

RR·60

ESD Testing-This test is performed to validate the
product's tolerance to Electro Static Discharge damage.
All pro~ucts !ncorporate ESD protection networks on
appropnate pIns.
Two types of tests are performed. FirSt, all devices are
tested using Mil STD 883 test criteria. In addition, a
charged device test is performed to further validate protection occurring during mechanical handling.
Erase/Write Cycling (ETOXn Flash MemorieslThis test consists of repeatedly programming the device
to an all.OOH pattern and then erasing to all OFFH
data. Worst case voltage levels are used to maximize
charge transfer to and from the floating gates. Cycling
is used to ensure devices meet reprogrammability requirementsas well as precondition for other reliability
stresses.
.

Vee

Vee

1/07
1/06
1/05
1/04
1/03

1/00
1/01
1/02

85/85 Test
During the 8S·C/8S% relative humidity test, the devices are subjected to a high temperature,high humidity
environment. The object of the test is to accelerate failure mechanisms through an electrolytic process. This is
accomplished through a combination of moisture penetration of the plastic, voltage potentials and contamination which, if present, would combine with the moisture to act as an electrolyte.

293002'-13

OE = +5.25V, R = 1 kn, Vee = +5.25V,
PGM = +5.25V
Vpp = 5.25V,
Vss = GND, CE = GND

AO~

~1.J

Steam.
Steam stressing performed at 121·C, 2atm. accelerates
moisture penetration through the plastic package material to the surface of the die. The objective ofthis test is
to accelerate failures of the device as a result of moisture on the die. surface. Corrosion, as typically seen in
plastic encapsulated devices, is a very minor contributor to the Flash failure mechanisms. Due to the floating gate storage cell composition, Flash memories have
a distinctive failure mode which requires special considerations and solutions.
The floating gate itself is a highly phosphorous doped
structure on which electrons are stored, thus creating
the non-volatile memory cell. Plissivation defects or
marginalities can allow moisture penetration to a single
Flash cell causing oxide deterioration, thus showing up
as a charge loss failure. This becomes the predominant
failure mode for Flash product, opposed to corrosion
which historically has been the dominant plastic mode
of failure. Intel has developed a proprietary, multi-layer
passivation which has successfully solved this problem.

A16
293002-3

Binary Sequence from Ao to A16

Figure 3. 28F010 Burn-In Bias
and Timing Diagrams

Failure Rate Calculations
Failure rate calculations are given for each relevant activationenergy. Failure rate calculations are made using the appropriate energy (2,3,4,5) and. the Arrhenius
Plot as shown in Figure 5'. The total equivalent device
hours at a given temperature can be determined. The
failure rate is then calculated by dividing the nulllber of
failures by the equivalent device hours and is expressed
as a %/1000 hours. To arrive at a confidence level associated failure rate, the failure rate is adjusted by a
factor related to the number of device hours using· Ii
chi-square distribution. A conservative estimate of the
failure rate is obtained by including zero failures at
0.3 eV.

NOTE:
·The activation energies for various failure mechanisms are listed in Table 1. The methodology for calculating failure rates is detailed in Appendix A.
3-638

int:et

RR·60

I

Vpp

vee

A16

WE

A15

NC

A12

A14

A7

A13

A6

A8

AS

A9

A4

All

A3

OE

A2

Al0

I

I

1'··1

I.GoY

I

I

10'

I

.j

/

10'

I

I

<

'"5!0

~"

i~
"'0-

Al

CE

AO

1/07

/

/

10'

1/06

1/01

1/05

/

z'"

llif:

/

~

/

Ij"
<-

"!i
iii"

/

L

0<

1/00

uoY/

10'

~E

1/02

1/04

Vss

1/03.

~

8<

293002~14

// V

10'

All Outputs Floating
Vss = CE = DE = GND
Vee = Vpp = PGM = 5.25V

I

l

10'

AO~

I

/
'"

V
./

~

1//

~
200 115 150

125

100

75

50

25

TEMPERATURE 'C

293002-4
A16

Figure 5. Arrhenius Plot

293002-5

Binary Sequence from Ao to A16

Table 1. Failure Mechanism Activation
Energies Relevant to ETOXII Flash Memories

Figure 4, 28F010 Lifetest Bias
and Timing Diagram

Failure Mode

eV

Oxide

0.3

SBCL/SBCG/MBCLlMBCG

0.6

Contamination
Speed Degradation

1.0
0.3-1.0

Intrinsic Charge Loss

1.4

Contact Spiking

0.8

A typicallifetest bias and timing diagram is shown in
Figure 4.

3-639

intel .

RR·60

RELIABILITY DATA SUMMARY

References

The following data is an accumulation of recent qualification and monitor program results. Failure rate calculation methods listed in Appendix A were used to arrive at the tabularized failure rates.

1. M. Lenzlinger.E. H. Snow, "Fowler-Nordheim tun-

In reviewing the reliability data as presented, questions
may arise as to why lot sizes often decrease from one
test to another without a corresponding number of
identified failures. This is due to a variety of factors.
Many tests require smaller sample sizes and as a result
all parts from a previous test do not necessarily flow
through to a succeeding test.
In addition, various parts are pulled from a sample lot
when mechanical or handler failures occur. These "failures" are not a result of the specific test just completed
but are nonetheless removed from the sample lot size
and are not included in any failure rate calculation. It
can also happen that a particular test is done incorrectly, through human error or faulty test equipment and
"invalid" failures are put aside for retesting at a later
date, decreasing the lot size for a succeeding test. If
these parts are found to be truly defective, they are
treated as failures and.listed. If they test out properly,
they are removed from any calculation data base.

2.

3.
4.

5.
6.

7.

neling into thermally grown Si02". Journal of Applied Physics, Vol. 40 (1969), p. 278.
S. Rosenberg, D. Crook, B. Euzent, "16th Annual
Proceedings of the International Reliability Physics
Symposium", pp. 19-25, 1978.
S. Rosenberg, B. Euzent, "HMOS Reliability" Reliability Report RR-18, Intel Corporation, 1979.
R. M. Alexander, "Calculating Failure Rates from
Stress Data, April 1984 International Reliability
Physics Symposium.
"EPROM Reliability DATA Summary" Reliability
Report RR-3S, Intel Corporation, 1985.
"E2PROM and NVRAM Reliability DATA Summary" Reliability Report RR-59B, Intel Corporation, 1986.
E.S. Anolick, G.R. Nelson, "Low Field Time Dependent Dielectric Integrity", 1979 International
Reliability Physics Symposium, pp. 8-12.

NOTE:
The methodology for calculating failure rates is detailed in Appendix A.

3-640

RR-60

28F256A
The Intel 28F256A is a 256-Kbit bulk-erasable flash memory.
Number of Bits:
262,144
Organization:
32,768 X 8
PinOut:
32-Lead PDlP (P)/32-Lead PLCC (N)
Die Size:
228 X 141 mils

ETOXII Flash Memory
Process:
Technology:
CMOS
Cell Size:
3.8 X 4.0 fLM
Programming Voltage Options:
12.0V ±5%

Table 1. Reliability Data Summary
Burn-In

Year
1990

125°C DynamIc Llfetest

7.0Y Dynamic Llfetest

Program/Erase

48 Hrs.

168 Hrs

500 Hrs

1KHrs

2KHrs

48Hrs

168 Hrs

10K

0/300

1/300

0/298

1/295

0/294

3/3004

1/2996

1/408
0/300

1991

0/374

0/374

1/374

0/372

0/2040

0/2039

1992

01725

01724

01722

0/689

1/8955

0/8942

Total

0/1399

1/1398

1/1394

1/1356

4/13999

1'/13977

A

F

B

C

0

0/294

11708
E

Table 2. Additional Qualification Tests-PLCC (N)
Year

140°C Data Retention Bake

Temperature Cycling

48Hrs

168 Hrs

500Hrs

1KHrs

200 Cycles

500 Cycles

1kCycies

1992

0/525

0/525

0/525

0/523

0/638

0/633

0/633

Total

0/525

0/525

0/525

0/523

0/638

0/633

0/633

1990
1991

Year
1990
1991
1992
Total

168 Hrs

85°C/85% RH
500Hrs

1KHrs

Steam
168 Hrs

0/450
0/450

0/449
0/449

0/449
0/449

0/640
0/640

3-641

RR·60

Table 3. Additional Qualification Tests-PDIP (P)
Thermal Shock

Temperature Cycling

Year

200 Cycles

SOOCycle.s

1i0'

0/650

0/210

0/210

Total

01750

01750

01750

0/1580

0/1580

Steam
1K Hrs

168 Hrs

0/210

0/210

0/815

0/1580

0/210

0/913

0/98

Table 4. Additional Qualification TestS-TSOP (E)
Year

Temperature Cycling
200 Cycles

500 Cycles

Thermal Shock
1KCycies

50 Cycles

200 Cycles

500 Cycles

1990

0/234

0/232,

0/232

0/233

0/233

0/233

Total

0/234

0/232

0/232

0/233

0/233

0/233

85·C/85% RH

Year

Steam

168 Hours

500 Hrs

1K Hrs

2KHrs

168 Hrs

1990

1/385

0/383

1/383

0/382

0/446

Total

1/385

0/383

1/383

0/382

0/446

K

J

3-647

RR·60

PIN/E28F010 Failure Rate Prediction
12S·C Actual
Device Hours
B.2BE
4.0BE

+ 06
+ 06

Equivalent Hours

Ea
(eV)

Fa!!
SS·C

0.3 BI
0.3 + VAF

#

5.36E
6.B6E

70·e

+ 07
+ OB

3.37E
4.32E

+ 07
+ OB

TOTAL 0.3 eV Failures =
B.2BE
4.0BE

+ 06
+ 06

0.6BI
0.6 HVELT

3.46E
1.70E

+ OB
+ OB

1.37E
6.73E

+ OB
+ 07

TOTAL 0:6 eV Failures =
B.2BE
4.0BE

+ 06
+ 06

1.0BI
1.0 HVELT

4.1BE
2.06E

+ 09

+ 09

B.B9E
. 4.3BE

+ OB
+ 08

TOTAL 0.8 eV Failures =

Fail Rate

%/1K Hours
SS·C

70·C

0.0016

0.0025

0.0007

0.0016

B
2
10
0
2
2
0
0
0

Combined Failure Rate:
FITs:

0.0001

0.0001

0.0024
24

0.0042
42

Voltage Acce!. Factor (VA F)
for HVELT on this process is = 26.0
Failure Analysis:

A. l-Bond pad leakage

J. l-Isb

B. 3-Bond pad leakage
2-Speed failure
C.3-lsb
2-Single bit charge loss
D. 2-Single bit charge loss
E. 2-lsb
F. l-Cluster bit charge loss (passivation damage)
G.l-Isb
H. l-Single bit charge loss
1-0utput leakage
I. l-Isb
1-0utput leakage

K. l-Input leakage-pass after bake
L. 1,Single bit charge loss
l-Isb
M. l-Input leakage
1-0pens
N. 2-Single bit charge loss \
O. 9-Dual column (metal filaments)
2-Erase pushout
l-Isb
3-Spurious program
2-0xide breakdown
l-Poly defect
2·Slow to program
P. l-Delamination

,

3-648

,

infel .

. RR-60

P/N/E28F020
The Intel 28F020 is a2048-Kbit bulk-erasable flash memory.
Number of Bits:

2 (512 X 2048)

PinOut:

32-pin PLCC/PDlP/TSOP

Die Size:

258 X 423·miis

ETOXTMII Flash MeD;lory

Process:

2,097,152

Organization:

Technology:

CMOS

Cell Size:

3.8 X 4.0,...M

Programming Voltage:

12.0V ±5%

Table 1. Reliability Data Summary
Year

Burn·ln

12SoC Dynamic Lifetest

6.SV Dynamic Llfetest

48 Hours 168 Hrs SOO Hrs 1KHours 2KHrs

168 Hrs SOOHrs 1KHrs 2KHrs

48Hrs

1990

0/588

0/588

0/587

0/585

2/485

0/883

1/878

0/871

0/869

01713

1991

0/288

0/288

0/286

0/286

2/186

0/433

0(432

0/431

0/431

0/281

0/374

0/374

0/374

0/374

0/298

0/876

0/876

0/873

0/871

4/671

0/1690

1/1684

0/1676 0/1674 0/1292

1992
Total

A

B

Table 1A. Reliability Data Summary
Program/Erase

Year

7.0V Dynamic Llfetest

10K

48Hrs

168 Hrs

1990

6/2244

1/2859

0/2858.

1991

2/1029

1/2859

0/2854

1992

0/533

0/2997

1/2993

Total

8/3806

2/8715

1/8705

C

0

H

Table 2. Additional Qualification Tests-PLCC (N)
Year
1990

Thermal Shock

Temperature Cycling
200 Cycles

SOOCycies

1KCycies

SO Cycles

200 Cycles

SOOCycies

0/382

0/380

0/380

0179

0179

0178

0179

0179

0178

1992

0179

0/77

0177

Total

0/461

0/457

0/457

Year

8soC/8S0/0 RH .

Steam

168 Hours

SOO Hrs

1KHrs

2KHrs

168 Hrs

336Hrs

1990

1/325

0/324

0/324

0/250

1/229

0/228

1992

0/50

. 0/50

0/42

Total

1/375

0/374

0/366

0/80
0/250

1/309
F

E

3-649

0/228

RR-60

Table 3. Additional Quallfleatlon Test&-PDIP (P)
140"C Data Retentl~n Bake

Year

. 48 Hours

1se Houra

500 HOiirs

19!J1

Oi226
0/226

0/226
'0/226

Total

0/452

0/452

0/226
01226
0/452

1990

Temperature Cycling

Year
1990
1991
T6tal

Thermal Shock

2QOCycies

SOOCycles

:tKCycles

SO~cles

. 200Cy~les

SOOCycies

0/474
0/234
01708

0/474
0/234

16/474

01474
0/233

0/473
0/233

0/399

01706.

0/399

91708

0/234

161708

01707

-

G

Year
168 Hours
1990
1991
Total

0/395
0/245
0/640

'.

8S0C185% RH

Steam

SOOHrs

1KHrs

2KHrs

168 Hrs

0/389
0/245
0/634

0/389
0/245
0/634

0/144
0/245
0/389

0/415
0/189
0/604

,

3-650

infel· .

RR·60

Table 4. Additional Qualification Tests-TSOP (T)
Temperature Cycling

Year

Thermal Shock

200 Cycles

SOD Cycles

1KCycies

SO Cycles

200 Cycles

SOOCycies

1990

0/233

0/231

0/231

0/234

0/231

0/231

Total

0/233

0/231

0/231

0/234

0/231

0/231

Year

8S·C/8S% RH
168 Hours

-Steam

SOO Hrs

1KHrs

168 Hrs

1990

0/382

0/382

0/382

0/387

Total

0/382

0/382

0/382

0/387

P/N/E 28F020 Failure Rate Prediction
12S·C Actual
Device Hours

Activation
Energy
(eV)

1.04E
1.05E
2.89E

+ 06
+ 06
+ 06

0.3 eV HVLT
0.3 eV ELT
0.3eVHVLT

1.05E
2.89E

+ 06
+ 06

0.6eV ELT
0.6eVHVLT

+ IME
+ VAF

Equivalent
Hours
SS·C·
6.26E
6.79E
4.86E

#

Fail
700C

+ 08
+ 06
+ 08

3.94E
4.27E
3.06E

+ 08
+ 06
+ 08

+ 07
+ 08

1.73E
4.76E

=

1
4
1

=

5

TOTAL 0.6 eV Failures
1.05E
2.89E

+ 06
+ 06

1.0eVELT
1.0eV HVLT

.

5.29E
1.46E

+ 08
+ 09

1.13E
3.10E

+ 08
+ 08

TOTAL 1.0 eV Failures

=

Failure Analysis:
A. 4-Single bit charge loss (0.6 eV)
B. 1-lsb (0.3 eV)
C. 2-Dual column
6-Higher erase time
D.2-lsb
E. 1-0pen output
F.1-lsb
G. 16-Leakage due to thin film crackin~esign fix in place for 1991
H. 1-Single bit charge gain

3-651

70·C

0.0002

0.0003

0.0039

0.0097

0

o ..
0

Combined Failure Rate:
FITs:
VAF = Voltage Acceleration Factor of 26 (@6.5V)
IME = Voltage Acceleration Factor of 93 (@7.0V)

5S·C
0
0
1

+ 07
+ 07

TOTAL 0.3 eV Failures
4.39E
1.21E

Failure Rate
%/1K Hours
(60% U.C.L)

0.0001

0.0003

0.0042
42

0.Q103
103

infel·

RR-60

APPENDIX'A
FAILURE RATE CALCULATIONS FOR
60% UPPER CONFIDENCE LEVEL
Step 1. Accumulate data from 48 hours of bum-in through Iifetest of each lot. (Note: 48-hour bum-in results

measure infant mortality and are not included in the failure rate calculation.)
Step 2. Determine the failure rate mechanism for each failure and assign an activation energy

each failure mechanism. (See Table 1 below.)

 correspOnding to

.

Table 1. Failure Mechanisms Activation
Energies Relevant to ETOXTMII Flash Memories
Failure Mode.

Activation
Energy

Defective Big Charge Gain/Loss
Oxide Breakdown
Silicon Defects
Contamination
Intrinsic Charge Loss

0.6eV
0.3eV
0.3eV
1.0 eV-1.2 eV
1.4eV

Step 3. Calculate the total number of device hours from 48 hours of bum-in through lifetest.

Example: 12SoC Bum-IniLifetest and a 2 lot sample
# failures
total # devices

48 Hours

168 Hours

500 Hours

1KHours

2KHours

Lot #1
Lot #2

0/1000
0/221

1/1000
0/201

0/999
1/201

0/998
1/100

0/994
0/99

Totals

0/1221

111201

1/1200

1/1098

0/1093

Device Hours = (Number of Devices) (Number of Hours)
Total Device Hours = 1201 (168 hrs - 48 hrs) + 1200 (500 hrs- 168 hrs)

+ 1098 (1000 hrs - 500 hrs)+ 1093 (2000 hrs - 1000 hrs)
= 1201 (120 hrs) + 1200 (332)+ 1098 (500 hrs)

+ 1093 (1000 hrs)
= 2.185 X 106 Device Hours

3-652

RR-60

Step 4. Use EA tables to find the equivalent device hours at a desired temperature for each activation energy (failure
mechanism), or use the Arrhenius relation.

[~~A]

R = Aexp

= 8.617 X 10- 5 eVI"K
= proportionality constant
= mean rate to failure

K
A
R
EA = activation energy
T = Temperature in Kelvin

~here

(Boltzman's Constant)

A1 = A2 = A for the same failure mechanism (i.e., same EA)

Where R1 and R2 are rates for

I!. normal operating temperature and an elevated temperature respectively
R1 = R2

x exp [EA
K

(.!.. -.!..) ]
T2

T1

However, since rate (R) has the units (_.1_), we can think in terms of time to one failure or MTBF.
' .
time
Thus,
R1

= -1
t1

wheret1

= MTBFat sametemperatureT1
and

R2
.

= -t21

where t2

= MTBF at same temperature T2

Thus the Arrhenius Relation becomes:

or

We then define the Acceleration Factor as:
A.F.

= !! = exp [EA
t2

K

(.!.. -.!..) ]
T1

T2

For example: For EA = 0.6 eV, T 2 = 398°K, T 1 = 328°K
t1 = 41.7 t2

Therefore, one hour at 125°C is the equivalent to 41.7 hours at 55°C fora failure mechanism of activation enllrgy
EA = 0.6 eV. Then 41.7 is the thermal acceleration factor for time.

3-653

intel .

RR-60

,
NOTE:
The Arrhenius Plot is simply In (Acceleration Factor) vs. IITemperature normalized for an MTBF (tv of one
hour at 2SO"C (TV. This plot can also be used to determine the acceleration factor between two temperatures .
(other than 2SO"C).
For example: For a 0.3 eV failure at 12SoC, the acceleration factor is 8.1 relative to a 0.3 eV failure at 2SO"C. For a
0.3 eV failure at 2SoC, the acceleration factor is IS2 relative to 2SO"C. Therefore, the acceleration factor between
12SoC
2SoC is:

and

A.F. =

!! =
12

152 = 18.7
8.1

Step 5. Organize the burn-inllifetest data by EA, Total Device Hours at theburn-inllifetest temperature T2, Ther. mal Acceleration Factors for each failure mechanism (EA>, Number of Failures for each failure mechanism:,
and the calculated equivalent device hours at the desired operating temperature TI.

NOTE:
The rise in junction temperature due to the thermal resistivity of the package (81A> must be added to the desired
and actual burn-in/lifetest temperatures.
Ttes!

Total
Device Hrs

EA(eV)

@

= TJ + TA = 9JA (IV-@ TAl + TA

T2

T.D.H.
T.D.H.
T.D.H.

0.3
0.6
1.0

Acceleration
Factors

# Fall

X
Y
Z

N1
N2
Na

Equivalent
Hours@T1

X (T.D.H.)
Y(T.D.H.) .
Z(T.D.H.)

The failure rates for individual failure m.echanisms and the total combined failure rate can be predicted using the
data table and the following formula:.
0/0 fail/1 K hrs. = X2 ~~ a) (105)
.

,

.

Where X2 (n, ex) is the value of the chi squared distribution for n degrees of freedom and confidence level of a. T is
the total equivalent device hours at T I. The total combined rate is just the sum of the individual failure rates for each
.
, failure mechanism..
For a 60% UCL, the aJ>ove formula converts to the following:# Failures

% fall/1K hours 60% UCL
0.915 x 105/T
2.02 x 105 /T
3.105 X 105 /T
4.17 X 105/T

o

1
2
3

3 < # < 15

> 15

1.049 (# failures for a particular EA)
. Equivalent hours @ T1
(0.2533

+ {(4 X

# failed)

4T

3-654

+ 1.0305 [105]

+ 3) 2 [

5]
10

infel·

RR·60

Example 1:
Assume for this example, that Icc active is.57 rnA at TA
Also assume that

'hi..

=

125'C and ICC active is 60 rnA at TA

=

55·C.

= 35·C/W.

Then,
T2 = (35°C/W) (57 rnA) (5V)

+

125°C

;:: 135°C = 408°K
T1 = (35°C/W) (60

mAl (5V) +

55°C

;:: 65°C = 338°K

EA(eV)

Actual Device
HourS @ 12S'C

Acceleration
-for 135"C to 6S'C

' Equlvllient
Hours
atSS'C

II, Fall

SS',C
% Falll
1KHrs'

0.3
0.6
1.0

2.185 x 106
2.185 x 106
2.185 x 106

5.85
34.18
359.93

1.278 x 107
7.468 x 107
7.864 x 108

0
2
1

0.0081
0.0042
0.0003

Total Combined Failure Rate =

-

0.0126
126 FITs

Example 2:,
Assumethat an additional lot of 800 flash devices is burned in using a 6.5V lifetest. Using Table 2 below, a voltage
acceleration factor of 55 results from a 20% over:stress (5.5V to6.5V).

Device Hours = 800 (48 hrs - 0 hrs)

+ 800 (168 hrs

- 48 hrs)

+ 799 (500 hrs

- 168 hrs)

= 3.997 x 105

Table 2. Time-Dependent Oxide Failure Accelerations
Supply
Voltage
(Volta)

Oxide
Thickness
(A)

Operating
Stress
(MY/cm)

10%

20%

SO%

1,00%

HMOS*E

5

700

0.714

3.2

10

320

99,500

HMOS* liE

5

400

1.25

7.5

55

23,700

5.6

ETOXTMII

5

235

2.15

3.9

26

910

8.3

Type

ASSUMES:
1. No Bias Generators
2. Depletion Loads

3·655

Acceleration Factor at _ % Over StreSs

x
x

108
105

RR·60
Since this voltage accelerated stress is used to predict an oxide bre8kdown failure rate, the S.SV bum-inIlifetest SS·C
, hours for EA = 0.3 eV are added to the 6.SV bum-inIlifetest SS"C equivalent hours as follows:
125"C
Burn-ln/Lifetest

EA (eY)

Actual Device
Hours@ 12S·C

Acceleration Factors
for 135"C to 85"C

Equivalent
Hours
@S5"C

0.3
0.3

2.185 X 106
3.997 X 105

5.85
(5.85 X 55)

' 1.278 X 107
1.286 X 1()8 ,

5.5V
6.5V

,

Total Equivalent EA

= 0.3 eV Device Hours =

The following failure rate predictions include the total equivalent SS·C,
I

EA(eV)
0.3

0.3

+ 55(1)
0.6
1.0

Actual Device
Hours@ 12S·C
2.185' X
3.997 X
2.185 X
2.185 X

Acceleration Factors
' for 135"C to 85"C

106
105
106
106

5,85
(5.85 X 55)
34.18
359.93

EA

1.414X1()8

= 0.3 eV device hours found above:

Equivalent
Hours
@S5"C

'*' Fall

-

-1

1.414 X 1()8
7.468 X 107
7.864 X 1()8

S5"C

NOTE:

1. The notation O~3

-

' 0.0015
0.0042
0.0003

2
1

Total Combined Failure Rate

'" Falll
1KHr'a

=
=

0.0060
60 FITs

_
+ 55 is used to 'show that 6.5V and 5.5V bum-iii lifetest equivalent hours have been combined.

i

3-656

infel·

RR-60

APPENDIX B
FLASH MEMORY BIT MAPS AND DIE PHOTOGRAPHS

3-657

intel·

RR-60

Columns are numbered 0 through 255 beginning with the column nearest the X-decoder.
Outpu~s

are grouped as fo!loV:/s:

Quadrant
Decoding

.
'

(,

LEFT HALF
ARRAY
0001 0203

Column
Decoding

•

\(

RIGHT HALF
ARRAY
04,050607

'\

A4

A3

A2

A1

AO

A10

00/07

01/06

02/05

03/04

0
0
0
0
0
0
0
0

0
1
1
0
0
1
1
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Bl192
BL193
BL194
BL195
BL196
Bl197
BL198
BL199

BL128
Bl129
Bl130
Bl131
Bl132
Bl133
Bl134
Bl135

Bl64
Bl65
Bl66
Bl67
Bl68
Bl69
Bl70
Bl71

BlO
BL1
Bl2
Bl3
Bl4
Bl5
Bl6
Bl7

1
1
1
1
1
1
1
1'

0
1
1
0
0
1
1
0

1
1
'1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Bl248
BL249
Bl250
Bl251
Bl252
BL253
Bl254
Bl255

Bl184
Bl185
Bl186
Bl187
Bl188
Bl189
Bl190
Bl191

Bl120
Bl121
BL122
Bl123
Bl124
Bl125
Bl126
Bl127

Bl56
Bl57
Bl58
Bl59
Bl60
Bl61
Bl62
Bl63

•
•
•

,

28F256A Bltllne Decoding

3-658

int:et

RR-60

X-DECODING: Wordlines are numbered 0 through 511 beginning at the top of the array
WL

A14

A13

A12

A7

AS

A5

A11

WLO
WL1
WL2
WL3

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
1.

0
1
0
1

WL508
WL509
WL510
WL511

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

<

A9

A8

28F256A Wordllne Decoding
ARRAY ORGANIZATION

BITMAP FOR
ONE OUTPUT

R
0
W
S
E
L
E
C
T
S

1100

1101

1102

1/03

1/04

1/05

1/06

1/07

x511
x510
x509
x508

x3
x2
x1
xO
yOy1 y2 ... y64

COLUMN SELECTS
.

28F256A Bit Map

3·659

intel .

RR·60

293002-16

28F256A Die Photograph

3·660

intel~

RR-60

28F512 (C) Bltllne Decoding
Address

Bltllnes

A14

A15

A10

A2

A1

AO

A3

10017

101/6

102/5

103/4

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
·0
1
0
1
0
1

BL384
BL385
BL386
BL387
BL388
BL389
BL390
BL391

BL256
BL257
BL258
BL259
BL260
BL261
BL262
BL263

BL128
BL129
BL130
BL131
BL132
BL133
BL134
BL135

.. .

.. .

BLO
BL1
BL2
BL3
BL4
BL5
BL6
BL7

0
1
0
1

BL508
BL509
BL510
BL511

BL380
BL381
BL382
BL383

BL252
BL253
BL254
BL255

BL124
BL125
BL126
BL127

...

...

. ..

.. .

.. .

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

"

.

., .

0
0
1
1

. ..

. ..

28F512 (C) Wordline Decoding

X Address

Row

A12

A7

A6

A5

A4

A13

A11

A9

A8

WL

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

XLO
XL1
XL2
XL3
XL4
XL5
XL6
XL7
XL8
XL9
XL10
XL11
XL12
XL13
XL14
XL15

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

XL16
XL17
XL18
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL28
XL29
XL30
XL31

3-661

6
0
0

infele

RR-60

28FS12 (C) Wordllne Decoding (Continued) .
X Address

Row

A12

A7

A6

AS

A4

A13

A11

A9

A8

WL

0

0

0

1

0

0

0

0

0

XL32

,

· ..

1

1

1

1

XL47

1

0
1 •

1

1

1

1

XL48

0

1

1

0

0

0

0

XL63

0

1

0

0

0

0

0

0

XL64

0

0

1

0

0

1

1

1

1

XL79

0

0

1

0

1

1

1

1

1

XL80

0

0

1

0

1

0

0

0

0

XL95

1

1

1

1

0

0

0

0

0

XL480

1

1

1

1

0

1

1

1

1

XL495

1

1

1

1

.1

1

1

1

1

XL496

1

1

1

1

1

0

0

0

0

XL511

0

0

0

1

0

0

0

0

0

0

· ..
· ..
· ..
· ..

3-662

· ..

RR-60

293002-17

28F512 Die Photo

3-663

. RR-60

2SF010 (A, B,C) Bltllne Decoding
Bltllnes

Address
A16

0.
0.
0.
0.
0.
0.
.0.
0.

A15

A10

A2

A1

AO

0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
1
1
1
1

0.
0.
1
1
0..
0.
1
1

A3

(00/7

'101/6

10215

i03/4

.0.
1
0.
1
0.
1
0.
1

Bl384
Bl385
Bl386
. Bl387
Bl388
Bl389
BL390.
Bl391

BL256
Bl257
Bl258
Bl259
BL260.
BL261
Bl262
BL,263

Bl128
Bl129
BL130.
BL131
Bl132
Bl133
Bl134
Bl135

BLo.
BL1
BL2
Bl3
Bl4
Bl5
Bl6
BL7

Bl50.8
Bl50.9
Bl51 0.
' Bl511

Bl380.
Bl381
Bl382
Bl383

Bl252
Bl253
. Bl254
Bl255

Bl124
"Bl125
Bl126
Bl127

...

...

. ..

...

...

...

...

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

0..'
0.
1
1

0.
1
0.
1

'

. ..

...

. ..

. ..

2SF010 (A, B, C) Wordllne Decoding
Row

X Address
A14

A12

A7

A6

. A5

0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.'
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
Q
0.
0.
0.
0.

0.
0.'
0.
0.
0.
0.
0.
0.
0.
0.
0..
0..
0.
0.
0.
0.'

0.
0.
0.
0.
0.
. 0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0..
0.
0.
0.
.0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.
0.

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0.

0.
0.
0.
0.
0.'
.0.
0.

A4

3-664

. A13

A11

A9

AS

0.
0.
0.
0.
0.
0.
0.
0.
1
1
1
1
1
1
1
.1

0.
0.
0.
0.
1
1
1
1
0.
0.
0.
'0.
1
1
1
1

0.
0.
1
1
0.
0.
1
1
0.
0.
1
1
0.
0.
1
1

0.
1
0.
1
0.
1
0.
1
0.
1
0.
1
0.
1
0.
1

Xlo.
Xl1
Xl2
Xl3
Xl4
Xl5
Xl6
Xl7
Xl8
Xl9
Xl10. ,
Xl11
Xl12
Xl13
Xl14 .
Xl15

1
1
1 .
1

1
1
1
1
0.
0.
0.
0.
1
1
1
1

1 .
1
0.
0.
1
1
0.
0.
1
1
0.
0.
1
1
0.
0.

1

Xl16'
Xl17
Xl18
Xl19
Xl20.
Xl21
Xl22
XL23
Xl24
Xl25
XL26
Xl27
Xl28
XL29
Xl30.
XL31

1

1
1
1
,0.
0.
0.
0.
0.
0.

0.
0.

0.

0.

0.

0.

0.
1
0.
1

0.
1
0.
1
0.
1
0.
1
.0.
1
0.

WL

inteL

RR·60

28F010 (A, B, C) Wordline Decoding (Continued)
X Address

Row

A14

A12

A7

A6

AS

A4

A13

A11

A9

AS

WL

0

0

0

0

1

0

0

0

0

0

XL32

0

0

0

0

1

0

1

1

1

1

XL47

0

0

0

0

1

1

1

1

1

1

XL48

0

0

0

0

1

1

0

0

0

0

XL63

0

0

0

1

0

0

0

·0

0

0

XL64

0

0

0

1

0

0

1

1

1

1

XL79

0

0

0

1

0

1

1

1

1

1

XL80

0

0

0

1

0

1

0

0

0

0

XL95

1

1

1

1

1

0

0

0

0

0

XL992

1

1

1

1

1

0

1

1

1

1

XL1007

1

1

1

1

1

1

1

1

1

1

XL1008

1

1

1

1

1

1

0

0

0

0

XL1023

...
...

...
...
...

Bit Map for
One Output

Array Organization

~~~~~~~~

~~~~~~~~

R

WLO
WL1
WL2
WL3

°

W

S
E 1/00 1/01 1/02 1/03
L
E
C

T
S

...

~~L-

1/04 1/05 II0s 1/07

..••

WL1020
WL1021
WL1022
WL1023

__L -__L-~

COLUMN SELECTS

BLO BL1 BL2 ... BL127

28F010 Bit Map

3-665

int:eL

RR-60

293002-18

28F010 Die Photo

3-666

int:el..

RR-60

2SF020 Bltllne Decoding
Address
A16

A15

Bltllnes

A10

A2

A1

AO

A3

100/7

101/6

102/5

103/4

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
. 1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

BL3B4
BL3B5·
BL3B6
BL3B7
BL3BB
BL3B9
BL390
BL391

BL256
BL257
BL25B
BL259
BL260
BL261
BL262
BL263

BL12B
BL129
BL130
BL 131
BL132
BL133
BL134
BL135

BLO
BL1
BL2
BL3
BL4
BL5
BL6
BL7

BL252
BL253
BL254
BL255

BL124
BL125
BL126
BL127

0
0
0
0
0
0
0
0

0
0
0
0
;0
0
0
0

. ..

. ..

.. .

.. .

.. .

.. .

. ..

.. .

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

BL50B
BL509
BL510
BL511

BL3BO
BL3B1
BL3B2
BL3B3

.. .

.. .

...

2SF020 Wordllne Decoding
Row

X Address

' WL

A17

A14

A12

A7

A6

A5

A4

A13

A11

A9

AS

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0

0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

XLO
XL1
XL2
XL3
XL4
XL5
XL6
XL7
XLB
XL9
XL10
XL11
XL12
XL13
XL14
XL15

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1 .

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
O.
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

XL16
XL17
XL1B
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL2B
XL29
XL30
XL31

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
3·667

infel .

RR-60

2SF020 Wordline Decoding (Continued)
A13
0

A11
0

A9
0,

AS
0

Row
WL
XL32

0
1

1
1

1
1

1
1

1
1

XL47
XL48

1
0

1
0

0
0

0
0

0
0

'0
0

XL63
XL64

1
1

O'
0

0
1

1
1

1
1

1
1

1
1

XL79
XL80

0
1

1
1

0
1

1
0

0
0

0
0

0
0

0
0

XL95
XL992

1
1

1
1

1
1

1
1

0
1

1
1

1
1

1
1

1
1

XL1007
XL1008

1
0

1
0

1
0

1
0

1
1

1
0

0
0

0
0

0
0

0
0

XL1023
XL1056

1
1

0
0

0
0

0
0

0
0

1
1

0
1

1
1

1
1

1
1

1
1

XL1071
XL1072

1
1

0
0

0
0

0
0

0
1

1
0

t
0

0
0

0
0

0
0

0
0

XL1087
XL1088

1
1

0
0

0
0

0
0

1
1

0
0

0
1

1
1

1
1

1
1

1
1

XL1103
XL1104

1
1

0
1

0
1

0
1

1
1

0
1

1
0

0
0

0
0

0
0

0
0

XL1119
XL2016

1
1

1
1

1
1

1
1

1
1

1
1

0
1

1
1

1
1

1
1

1
.1

XL2031
XL2032

1

1

1

1

1

1

1

0

0

0

0

XL2047

X Address
AS
'A4
1
0

A17
0

A14
0

A12
0

A7
0

A6
0

0
0

0
0

0
0

0
0

0
0

1
1

0
0

0
0

0
0

0
0

0
1

0
0

0
0

0
0

0
0

0
0

0
1

0
1

0
0

1
1

0
1

'"

W

L
E

C
T
S

,

...

...

...
...

...
...
...

...

...
'"

WLO'
WL1
WL2
WL3

o

S
E 1/00 1/01 1/02 1/03

...

Bit Map for
One Output

Array Organization
,

R

'.

'"

1/04 1/05 I/0s 1/,07

•
•
•

WL2044
WL2045
WL2046
WL2047

COLUMN SELECTS

BLO BL1 BL2 ... BL127

2SF020 Bit Map .
3-668

intet

RR-60

293002-19

28F020 Die Photo
3-669

intel-

RR-69 .

RELIABILITY
REPORT

November 1992

28F008SA
Reliability Summary

Order Number: 293008-002
3-670

28F008SA Reliability Summary
CONTENTS

PAGE

CONTENTS

INTRODUCTION .................. ..... 3-672

ROOM TEMPERATURE HIGH
VOLTAGE OPERATING
LlFETEST ........................... 3-675

QUALITY IRE LIABILITY
VERIFICATION ...................... 3-672
SUMMARY OF RESULTS . ............. 3-672
10KBYTE-WRITE/BLOCK-ERASE
CYCLING ............................ 3-673

PAGE

HIGH TEMPERATURE STORAGE
(BAKE) .............................. 3-675
STEAM (AUTOCLAVE) ................ 3-675
TEMPERATURE CyCLE ............... 3-676

QUALITY VALIDATION SUMMARY ... 3-673
THERMAL SHOCK .................... 3-676
INFANT MORTALITY EVALUATION
SUMMARy .......................... 3-674
HIGH TEMPERATURE OPERATING
LlFETEST ........................... 3-674

ELECTROSTATIC DISCHARGE ....... 3-676
LATCH-UP .............. , ............. 3-677
DATA REPORTING FORMAT . ........ 3-677

3-671

infel .

RR-69

INTRODUCTION
The 28FOO8SA is manufactured at D2 in Santa Clara,
California on ETOXTM III process 620, and assembled
at l'..iitsui, Japan. The 28FOO8SA is packaged in 4O-jead
TSOP die up (E) and die down (F) packages and 44"
lead PSOP. The typical Icc is lOrnA at a nominal Vee
of 5.0V and an ambient temperature of + 70·C. All
readouts in this qualification were done on a Genesis II
production tester.

All of the stress tests were conducted on units that
completed the full manufacturing flow. In all cases, a
failure is defined as failure to meet any data sheetparameter. Stress test readouts for electrical test endpoinis are done on the same equipment used for electrical test in commercial product manufacturing. Stresses
with endpoints other than electrical test have explanations of the endpoints in the stress descriptions.

SUMMARY OF RESULTS
This report contains the preliminary qualification data
for the 28FOO8SA and is intended to give a status of the
certification.

QUALITYIRELIABILITY
VERIFICATION

TESTI
STRESS
RESULTS RESULT
1. 10K WrltelErase Cycllng:(1)
0/1099
oDPM·

DATA
SET
E28F008SA

2. Quality Validation:

2/4424

This report is designed to provide a detailed description
of the methods used to verify that the 28FOO8SA meets
or exceeds Intel's stringent quality and reliability requirements. Each test is described and the results are
presented. The reliability of a device is generally defined as the probability that the device will perform its
intended function under the specified operating conditions throughout its life. To determine· a device's reliability, Intel subjects sample lots of the device to a vari.
ety of stress tests..
The evaluations performed for the TSOP
(E/F28FOO8SA) included the following:
10K Byte-WritelBlock-Erase Cycling(1) Quality
Validation
Infant Mortality Eyaluation (IME)
High Voltage Temperature Operating Lifetest
(HVTOL)
Room Temperature High Voltage Operating Lifetest
(RTHVOL)
High Temperature Storage (Bake)
Steam (autoclave)
Temperature Cycle (TIC)
Thermal Shock (TIS)
Electrostatic Discharge (ESD)
Latch-Up
NOTE:
1. Data collectionin progress for lOOK cycle specifica.
tion.
Stress lots containing die up material are. designated
with an "E", lots with die down material with an "F".
Cycled devices are denoted with a "C", the uncycled
units with a "U".

452 DPM

E28F008SA
F28F008SA

·3. Infant Mortality Evaluation:
24 hrs, 6.5V
0/2265
0 DPM

E28F008SA
F28F008SA

after 24 hr PSI'

4. High Temperature Operating Llfetest:
168 hrs
1/2247
445 DPM E28F008SA
F28F008SA

5. Room Temperature High Voltage Operating
Llfetest:
168 hrs

.

0/143

E28F008SA

6. High Temperature Storage (140·C Bake):
1000 hrs.
4/438
0.91 %
E28F008SA
7. Steam (autoclave):
0/806
168 hrs

0.00%

F28FOOBSA

8. Temperature Cycle (TIC):
1000 Cycles
0/248

0.00%

E28F008SA
F28F008SA

0.00%

E2BFOOBSA
F28FOOBSA

Condition "C"

9. Thermal Shock (TIS):
0/249
200 Cycles
Condition "C"

10. Electrostatic Discharge ESD:
No Failures

11. Latch-Up:
No Failures

E28FOOBSA
F28F0085A

E28F008SA
F28F008SA

'PBI = Production Burn In
NOTE:
1. Data Collection in progress for 100K cycle specification.

3-672

int'et

RR-69

10 KBYTE-WRITE/BLOCK-ERASE
CYCLlNG(1)

QUALITY VALIDATION SUMMARY

This test checks for any writing or erasure problems
over 10,000 write/erase cycles at ambient temperatures
of both + 70°C and O°C. A sample of cycled units are
then submitted for further testing in reliability stresses.
Table 1a
10,000 W/E Cycling
+700C
Lot

*"

10K Cycles

1EC
2EC
3EC
4EC

0/165
0/172
01 38
0/172

Totals

0/547

Quality Validation is done after the production flow to .
verify the Production Test/Inspection Test guardbands, temperature range and test repeatability. This
evaluation is performed on units which have seen standard production testing. Subsequent testing is done utilizing a special test tape which exercises the part at the
worst case voltage and timing conditions. This testing is
. done at three temperatures to ,guarantee full functionality at all datasheet conditions. This evaluation best represents a customer's worst case incoming EDPM for
the product.
Table 2
Lot
1EC
1EU
2EC
2EU
3EC
4EC
4EU
5EU
6EU
1FU
2FU

Table 1b
10,000 W/E Cycling
O°C
Lot*"

10K Cycles

1EC
2EC
3EC
4EC

0/172
0/169
01 39
0/172

Totals

0/552

Totals

NOTE:
1. Data Collection in progress from 100K cycle specifics~ion.

Quality Validation
80°C

Room

O°C

11 337 B
,
01 77
11 340 A
01 472
01 77
01 344
0/1006
01 724
01 587
01 230
01 230

01 336
01 77
01 339
01 472
01 77
01 344
0/1006
01 724
01 587
01 230
01 230

01 336
01 77
01 339
01 472
01 77
01 344
0/1006
01 724
0/587
01 230
01 230

2/4423

0/4422

0/4422

Failure Analyala Summary:
10
Qty
Deacrlptlon
A
1
Vee min failure
B
1
. Isb CMOS failure. Leakage = 152 p.A,
Spec = 100p.A

3-673

intel..

RR·69

INFANT MORTALITY EVALUATION
SUMMARY

HIGH TEMPERATURE OPERATING
LIFETEST

Infant mortality evaluation (IME) data is used to predict the' product early life failure' rate. The data is aiso
used to determine the required burn-in time. Burn~in is
used in production as needed to' ensure that the early
life failure rate goals are met.

High temperature lifetest is a, dynamic life test per~
formed to accelerate failure mechanisms in the infant
mortality (early life) and random failure/wear-out portion of a product's life curve. This is' done to predict
field reliability. In this test, failure mechanisms are accelerated by functionally exercising the device at an elevated ambient teinperature of + 125°C and aVec of
6.5V. During the test the memory is sequentially addressed and the outputs arc exercised but not monitored or loaded. A checkerboard data pattern is used to
simulate random patterns expected during actual use.
Then all devices used for lifetesting are subjected to
standard Intel testing.

The units are functionally exercised at 6.5V at an e1e- '
vated ambient temperature of 125°C for 48' hours. During the test the memory is sequentially addressed and
the outputs are exercised but not monitored or loaded.
A checkerboard data pattern is used to simulate random patterns expected during actual use. Then all units
used for infant mortality evaluation are subjected to
standard Intel testing.
'

Table 4. High Voltage Electrical Life Test
(Vee = 6.5V, T = 125°C, DynamiC)

, Table 3_ Infant Mortality Evaluation
(Vee = 6.5V, T = 125°C)
Lot #

12 Hrs

18,Hrs

0/63 .
01 63
11 215 A 01 211
01 193
0/193
01 216 B 01 215
01 77
01 77
11 481 C
01 481
01 217
01 217
01 206 0
01 208
01 497
01 497
01 55
01 55
01 55
01 55

fEU
1EC
2EU
2EC
3EC
4EU
4EC
5EU
6EU
1FU
2FU

Totals 1/2277

1/2270

24 Hrs,

01
01
01
01
01
01
01

D

E
F
G

1
2
1
2
1

1EU
1EC
2EU
2EC
3EC
4EU
4EC
5EU
6EU
1FU
2FU

01 63
211 E 0/210
193 F 01 191
215
01 215
77 G 01 76
480
01 480
217
0'1 217
0/206
01 206
01 497
01 497
01 55
01 55"
01 55
0/ 55
63

0/2269

Invalid Test Fallout Summary:
ID
Qty
Description
A
3
EOS due to mis-socketing
B

Lot #

48Hrs

EOS due to mis-socketing
Lost in handler
Passed retest
EOS due to mis-socketing
EOS due to mis-socketing

Totals

1

"500 Hr

63

01 63
01 55
01. 110

210
191

",

200

0/

76

01
01
01
01
01
01
01

479
217
206
497
55
53

1/2247

A

55
76

110
55

205
250
55
53

0/1087

1K Hr

01
01
01
01
11
01
01
01
01
01
01

63
55

108
55
76

110
55

204
250
55

'53

1/1084

0/2265
Failure Analysis Summary:
ID 'Qty
Ae
Description
A
1
0.3
Isb over spec limit
B

1

0.6

Single bit change loss

NOTE:

• Sample size decreased due to capacity constraints.

Failure Analysis Summary:
ID
Qty
Description
A
1
Isb> 100 /LA spec limit.

C

01
01
01
01
01
01
11
01
01
01
01

120 Hr

Fails opens/shorts testing

3-674

B

inleL

RR-69

STEAM (AUTOCLAVE)

ROOM TEMPERATURE HIGH
VOLTAGE OPERATING LIFETEST
In this test, failure mechanisms are accelerated by functionally exercising the device at the ambient temperature (25°C) while maintaining aVec of 6.SV. During
this test the memory is sequentially addressed and the
outputs are exercised, but not monitored or loaded. A
checkerboard data pattern is used. to simulate random
patterns expected during actual use. This data with the
voltage acceleration factors and the standard dynamic
lifetest data is used to calculate the failure rate. .

Table 5. Electrical Life Test
(Vee = 6.5V, T = 25°C)
Lot

#

1EC
2EU
2EC
4EU
4EC
3EU
Totals

48Hr
17
27
15
28
28
28

168 Hr
0/ 17
0/ 27
0/ 15
0/ 28
0/ 28
0/ 28

0/17
0/ 27
0/ 15
0/ 28
1/ 28
0/ 28

0/143

0/143

1/143

0/
0/
·0/
0/
0/
0/

500Hr

A

The Steam stress accelerates moisture penetration
through the plastic packaging material to the surface of
the die. The objective of the test is to accelerate the
problems found in very moist environments. Failure
mechanisms typically seen from this stress include corrosion, passivation defects, leakage and contamination.
Passivation defects or marginalities can allow moisture
penetration to a single FLASH cell causing oxide deterioration resulting in a charge loss failure.· The test
chamber is maintained at a temperature of 121°C and
an absolute pressure of two atmospheres. The devices
contain 98% + programmed pattern. After the stress
the units are subjected to standard Intel testing.

1000 Hr·
0/ 17
0/ 27
0/ 15
0/ 28
0/ 27
0/ 28
0/142

Failure Analysis Summary:
Ae
Description
ID
Qty
A
1
0.3
Power failure

HIGH TEMPERATURE STORAGE
(BAKE)
A 140°C bake, with no applied voltage, is performed to
determine the effect of high temperature storage without electrical bias. The bake evaluation accelerates failure mechanisms such as bond degradation and process
wear-out mechanisms such as ionic contamination.
This stress also checks contact integrity. The test is
conducted as per the specification Mil-Std-883C method 1008.2.

Table 6. Data Retention Bake
(Plastic, T = 140°C)
Lot #
1EC
2EU
2EC
4EU
4EC
5EU

72 Hr
0/ 71
0/ 75
0/ 71
0/ 75·
1/ 71 A
0/ 75

Totals 1/438

168 Hr
0/ 71
0/ 75
0/ 71
0/ 75
0/ .70
0/ 75

500 Hr
0/ 71
0/ 75
1/ 71 B
0/ 75
0/ 70
0/ 75

1000 Hr
1/ 71 C
0/ 75
0/·71
0/ 75
1/ 70 0
0/ 75

0/437

1/437

2/436

Failure Analysis Summary:
ID
Qty
Description
Single bit charge 1055 Vee max = 5.5V
A
1
8
1
Single bit charge 1055 Vee max = 5.0V
C
1
Single bit charge 1055 Vee max = 4.9V
o
1
Single bit charge 1055 Vee max = 5.3V

3-675

Table 7. Steam
Lot #

96 Hr

168 Hr

4EU
5EU
6EU
1FU
2FU
7EU
8EU

0/ 80
0/ 81
0/ 83
0/ 66
0/ 74
0/397
0/ 45

0/ 73
0/ 76
0/ 76
0/ 66
0/ 74
0/396
0/ 45

Totals

0/826

0/806

in1:et

RR-69

TEMPERATURE CYCLE

ELECTROSTATIC DISCHARGE

Temperature cycling is performed to evaluate the mechanical integrity of the device when exposed to temperature extremes. Mechanicai failure mechanisms
such as package cracking, die cracking, thin film cracking, bond wire lifting and die attach problems are accelerated by this stress. Temperature cycling also checks
for changes in electrical characteristics due to mechanical displacement or rupture of conductors and insulating materials. Other effects can include delamination of
finishes and degradation of package integrity. In this
stress, the devices are alternately exposed to - 6S·C to
+ ISOOC (condition C). The tinits must be transferred
between temperatures within one minute and must
reach the specified temperature within fifteen minutes.
The units must be at that temperature for a minimum
of ten minutes. Heating and coolillg are done by convection. This test is conducted in conformance with
specification Mil-Std-833C method' IOIO.S. The endpoint for this str:ess was 1000 cycles.

Electrostatic discharge (ESO) testing is done to measure a device's sensitivity to damage caused by ESD
due to mechanical or human handling.

Table 8. Temperature Cycle
(-65·C to + 150·C)
Lot #

200
Cycle

500
Cycle

1K.
Cycle

4EU
5EU
1FU
2FU

0/ 80
0/ 80
0/44
0/45

0/80
0/ 79
0/ 44
0/45

0/
0/
0/
0/

Totals

0/248

0/248

0/248

Human handling is modeled in specification Mil-Std883 method 3015 testing. This type of event occurs
when a: person transfers a charge from their body into a
device.
Military specification testing is done with an automated
STAG ESO tester. A 100 pF capacitor is discharged
into the device through a 1.5 KO resistor. The units are
stressed to both polarities and are zapped a minimum
of three times for each polarity. The following pin combinations are used:
• Each pill with· respect to electrically discrete groups
of Vee pins. All other pins are left floating.
• Each pin with respect to electrically discrete groups
of GNO pins. All other pins are left floating.
• All supply pins with respect to each electrically discrete supply. All other pins left floating.
A failure is defined as any failure to meet data sheet
specifications. Electrostatic discharge is a function of
die design. Package differences have secondary impact
on ESO performance.

80
79
44
45

Table 10. ESD Military Test

THERMAL SHOCK
Thermal shock is a liquid to liquid stress used to evaluate device resistance to sudden extreme changes in temperature. Thermal shock can result in die, package or
thin film cracking, and delamination. Bond wire lifting
and die attach problems are also accelerated by this
stress. Thermal shock uses the same temperature ranges
as temperature cycling, -6S·C to 1500C (condition C),
but the units must be transferred between temperatures
within ten seconds and are immersed in the specified
temperature for five minutes. The.test is conducted in
conformance with specification Mil-Std-883C method
lOlLS. The endpoint for this stress was 200 cycles.

,

Table 9. Thermal Shock
( - 65·C to 150·C)

+

Lot #

50
Cycle

200
Cycle

500
Cycle

4EU
5EU
1FU
2FU

0/ 80
0/ 80
0/ 45
0/44

0/
0/
0/
0/

0/80
0/ 80
0/ 45
0/44.

Totals

0/249

0/249

80
80
45
44

0/249
3-676

Lot #

+2000Y

-2000Y

4EU
1FU
2FU

0/ 10
0/ 10
0/ 10

0/ 10
0/ 10
0/ 10

Totals

0/ 30

0/ 30

int:el..

RR-69

LATCH-UP

DATA REPORTING FORMAT

, Latch-up is caused by parasitic transistor turn-on, creating a current path from power to ground, This condition' is characterized by a sudden increase in supply
current to the device. During Latch-up testing, the Vee
voltage is monitored for a sudden drop due to loading.
The following iatch-up tests were performed on this
device at + 125°C:
• Vee Latch-Up
In this test the Vee voltage is increased up to IOV.
A 50n. series resistor is used to prevent excessive
current flow in the case of latch-up.
• Vpp Latch-Up
In this test the Vpp voltage, is increased up to 14V.
• I/O Latch-Up
In this test a high input voltage is applied to the I/O
pins. This voltage is slowly increased up to + BV for
the positive polarity, and down to - 2V for the negative polarity.

Rejects/Sample Size
Rejects
= Valid failures
Sample size = Total units minus valid and invalid rejects
RULE #1
Invalid failures are not included in the sample size.
RULE #2
Only valid failures are reported as rejects.
EXAMPLE:
Raw data looks like the following:
o Hr
48 Hr
100 units put on stress 1/100
(A)

Latch-up is a function of process and die design. Package differerces have secondary impact on latch-up performance.
'
Table 11. CMOS Latch-Up Test
Input

Output

Vpp

Vee

+/-

+/-

+

+

4EU
1FU
2FU

0/ 15
0/ 15
0/ 15

0/ 15
0/ 15
0/ 15

0/ 15
0/ 15
0/ 15

0/ 15
0/ 15
0/ 15

Totals

0/ 45

0/ 45

0/ 45

0/ 45

Lot #

168 Hr

500 Hr

2/99
(8)

1/97

NOTES:
A. 1-Blown unit (Electrical Overstress) [INVALID]
B. 1-Tacc failure [VALID]
1-Vcc open (reverse socketing) [INVALID]
C. 1-Unit dropped during board unload [INVALID]

Data reported:
48 Hr

168 Hr

500 Hr

0/99

1/98

0/96

(A)

(8)

(C)
A. 1-Blown unit Invalid due to electrical overstress
B. 1-Tacc failure
1-Vcc open Invalid due to reverse socketing
C. '1-Unit dropped during board unload

3-677

(C)

A 90ns lOOK Erasel
Program Cycle Megabit
FlashMemory
by Virgil Niles Kynett, Jim Anderson, Greg Atwood, Pat Dix, Mick Fandrich, Owen Jungroth, Susan Kao, Jerry A. Kreifels, Stefan Lai,
Ho-Chun Liou, Benedict Liu, Richard Ladenquai, WehcJuei Lu, Roy Pavlof/. Daniel Tang, J.C. Tzeng, George Tsau, Branislav Vajdic,
Gauram Verma, Simon Wang, Steven Wells, Mark Winston; and Lisa Yang

ABSTRACT
Using advanced 1.0pm CMOS technology, a 245 mil square
131072 X 8 device has been fabricated with a 3.8pm X 4,Opm
,cell, The memory exhibits a 90ns read access time with It 900ms
electrical array erase and lOps/byte program time. The device
has been optimized for in-system microprocessor-controlled reprogramming with endurance performance greater than IOO,OOOerase/ "
program cycles. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses.
ADVANCES in photolithography have made it possible to develop
an ,electrically erasable reprogrammable 90ns I Mb flash memory
which is capable of greater than 100,000 erase/program cyCles. '
This 1Mb memory implements a command port and an internal
reference voltage generator,' allowing microprocessor-controlled
reprogramming t I).
The 900s access time results from a high memory cell current
(95pA). low resistance poly-silicide wordlines. advanced scaled

1989 IEEE. Reprinted, with permission, from
1989 IEEE loternall....1Solid-State area;", Cooference Digest or Tecbnlcal Papers,
New York, NY, February 15-17, 1989,

@

periphery transistors, and a di/dt optimized datao 100 A

N-WeIiCMOS

Read Current

Epi on P+

Terase
Tprog

Tox

= 250 A

Leff N+P

= 95"A

= 900ms
= 1O"s/byte

= 0.9"m

Device

Die Size: 60116 mils'
Organized: 12SK X S

Xjn

= 0.3"m

Access Time: 90ns

Xjp

= O.e"m

Active Power: SmA
Standby Power: 4"A
Package: 32-pin Cerdip

3-679

~

TYPICAl:ARRAV ERASE

TIM~

TYPICAL BYTe PROGRAM TIME

~

600

w

~

500

Ii!

ffi

400
300
10

200
100

10

10000

100
1000
NUMBER OF CYCLES

100000

Figure 4. Erase/program time vs. cycling

99.99

....

l

"

~

"

a
~

Figure 2. 1Mb die photograph

~

90

10

!i!

3
However, to build a manufacturable 1Mb flash memory, it is
essential to be able to control the memory array erase Vt. The key
is the. proper selection of the erase Vt maximum and maintenance
of a tight Vt distribution. The maximum erased Vt is set to 3.2V
via the erase algorithm and the internal erase verify circuits [31.
Good oxide quality gives an erased Vt distribution width that does
not change appreciably with cycling (Figure 5). The tight erase Vt
distribution gives an order of magnitude of erase time margin to
the fastest erasing cell (Figure 6).

~

.01
.001

1.5

1.75

2.0
2.25
2.50
ERASE VI (VOLTS)

2.75

3.0

3.25

Figure 5. Erase Vt distribution VS. cycling

ARRAY ERASE

ERASE ceLL VI VERIFY LEVEL

~SLOW ERASE :~:lCAL ERASE BITS
FAST ERASE BIT

ERASE CEU VI MINUMUM
10

laO

1000

10000

100000

1000

1000000

2000

3000

4000

6000

ERASE TIME (mS)

NUMBER OF CYCLES'

Figure 3. Array Vt vs. cyles

Figure 6. Array erase Vt profile vs. erase time

3-680

Array erase is executed by switching high voltage onto the source
junction of all cells and grounding all select lines. The array source
switch, shown in Figure 7, switches high voltage onto the source
junctions. Transistor MI6 is a very large device which pulls the
source to ground during read and program modes. During erase
mode, the high voltage latch formed by M5-M8 enables transistor
MIS, which then pulls the array source up to J2V. To obtain fast
array erase times, this device must be made large enough to supply
the grounded gate breakdown current which occurs on the sources
of the memory array. The upper boundary on MIS current sourcing capability is set by the maximum allowable substrate current.
If VPP is raised to 12V before VCC is above approximately l.8V,
the low VCC detect circuit formed by MI-M4 drives the node
LOWVCC to 9V. Transistors M9-MII then force the erase circuit
into a non-erase state with MIS off and MI6 on. When VCC rises
above l.8V, the chip will be reset into a read state.
Redundancy circuits consist of two flash memory cells combined
with a cross-coupled bias and sense circuit ensuring low power
consumption (Figure 8). When either M7 or M8 is programmed,
the latch no longer draws power. By setting the levels of CLA'MP
and BIAS to Vt and 2Vt respectively, the Band BB levels are held
to approximately one Vt. The signals F and FB along with the
address signal drive the inputs to the XNOR circuits. The MATCH
signals for all column addresses are combined to create the full
match signal which enables a redundant column.
In summary, a 90ns 1Mb flash memory has been developed
through the ability to scale the flash memory cell onto a standard
CMQS l.O!,m technology. This memory has been optimized for
in-system micropro~essor-controlled reprogramming for more than
100,000 erase/program cycles.

ARRAY
SOURCE

ERASE-,r----j-----......J

Figure 1. Array source switch

BIAS----+t--=----j
MATCH

REFERENCES
[1] V. Kynell el aI., "An In-System Reprogrammable 256K CMOS Flash
Memory," in ISSCC Dig. Tech. Papers, Feb. 19BB, pp. t32-t33, 345.
[2] G. Canepa et al., "A 90ns 4Mb CMOS EPROM," in ISSCC Dig, Tech. Papers,
Feb. t9BB, pp.120-t21, 323.
[3] V. Kynelt at al., "An In-System Raprogrammable'32K X B CMOS Flash
Mem0!Y'" IEEE J. Solid-State Circuits, vol. 23. pp. 1157-1163, Oct 19BB.

CLAMP _ _ _ _" -_ _ _ _..J
ADDRESS------~---....J

Figure 8_ Redundancy circuits

3-681

ARTICLE REPRINT

AR-472

SILICON BITS
Stan Baker

The Memory Driver

ca. ,· . :

The primary driving force behind the personal
computer revolution has been memory, not
microprocessors. While one cannot give all
the credit in one place, and microprocessors
and software have their essential roles, the
architectures and viability of these small computers has been due mostly to memory technologies-both semiconductor and magnetic.
That situation continues and more memory trends are afoot that
wiD force computer systems in new directions in the near future.
DRAMs are running out of the economic gas that has propelled the
memory costs downward, not only leaving the door open for other
memory technologies but demanding they enter.
Today's memory technologies are bubbling with new possibilities that will further revolutionize systems. At the heart of
the changes will be nonvolatile devices. And the major player
there will be flash technology.
The initial personal computers could have been made with CPUs
that were not fully integrated, using gate arrays, LSI discrete logic
or 2901 bit-slice architectures. But they could not have been made
without low-cost, dense DRAM chips and low-cost floppy disk
drives. The success of PCs then gave the economic stimulus to
miniaturize hard disks which stimulated the PC business further.
The center of the computing universe is the data, not the
processing engine. And the data is in the memory. And the
ideal memory is nonvolatile.
Besides changing systems, the nonvolatile technologies will
also alter the architecture of the semiconductor business internationally, with large scale impact on trade, political, and macro-economic issues. The leaders in the nonvolatile technologies are American companies. And they will not license their
technology so readily as in the past.
There is a host of possibilities from flash, EPROM, EEPROM, battery backing, magnetic, optical, and the more remote ferroelectric technologies. Ferroelectric comes the closest to being the ideal nonvolatile RAM, but it is the furthest
from reality. However, flash is here and, for the first time,
promises to bring nonvolatile devices into the processing heart
of computing systems in a big way.
Flash memories can have smaller cells than DRAMS and
will be able to get more benefit from the latest lithographic
and other processing equipment than DRAMs will. With only a
year on the market the bit-count of.flash devices has caught
up with EPROMs and DRAMs, all now at 1 megabit per chip.
The 1-Mbit flash device just introduced by Intel has a die of
60,000 square mils. Current 1-Mbit DRAMs are larger, at
about 70,000 square mils, and 256 kilobit SRAMs use about
75,000 square mils. 1-Mbit EEPROMs are about double, on
the order of 130,000 square mils.
Flash will continue to track EPROM densities and soon outstrip even DRAMs, according to Richard Pashley, general
manager of Intel's nonvolatile memory business. The only
memory technologies that continue to track lithography in
their cell size are EPROMs and flash devices.

Flash devices can be read as rapidly as EPROMs or DRAMs.
But writing into them takes tens of microseconds per byte. And
they are bulk erased in tens to hundreds of milliseconds.
Such long erase and write times may seem extremely limiting
at first thought. But actually, the bulk of program and data storage does not need fast erase/write. That is why magnetic storage is so important. And that is what has some flash memory .
marketeers so excited--especially at Intel, which is nowhere in
the DRAM and SRAM businesses, but the world leader in
EPROMs. For flash devices are very similar to EPROMs.
Consider this example. If a computer were constructed with
megabytes of fast volatile RAM directly serving the CPU, that
can be erased and rewritten t:apidly, massive blocks of nonvolatile flash RAM can take the place of magnetic storage backing that volatile memory. A few 4-Mbit flash chips will carry
more data than most floppy disks.
That backup storage will significantly speed-up system performance and eliminate electro~mechanical reliability problems,
as well as lots of weight and
power drain. The flash devices that has put the most corporate
can also be used to reduce the commitment-money and taJentamount of volatile RAM, be- behind flash. At Intel, flash technolcause some is used to store pro· ogy plays !iirectly off its EPROM
grams and data that seldom technology in which Intel is still the
needs to be erased and changed. world leader.
Such write-seldom sections of
memory can be updated in a sec- A passion for fl....
ond or so, which is less than According to Pashley, "flash is
would irritate a human operator. the way Intel will get back in the
read-write memory bllsiness." In
Fitting in this scenario, future Pashley, Intel and perhaps the inmicroprocessors will have more dustry has its flash champion, and
and more memory on their die. the success of any new technolThat will be a good place for the ogy depends on having the capafast RAM, made even faster by ble individuals that have the faith
eliminating the inter-package wir- and lead the charge.
ing. And these internal RAMs will
Pashley was the pioneer of
be organized to match the processing characteristics of the scaling, the technique of shrinking
CPU which is not the case now MOS devices that is fundamental
with discrete RAMs. The flash to the evolution of more and more
and EPROM devices can then dense MOS ICs. His process at
connect directly to the micropro- Intel was termed "HMOS."
cessor package, eliminating disAt the recent ISSCC in New
crete DRAMs and SRAMs.
York Intel described its 1-Mbit
Memory companies everywhere flash memory chip. Seeq Techare working on flash devices. But nology and National SemiconSeeq Technology and Intel were ductor, who are jointly working
the first to market. Since then, on flash devices, described a 1Texas Instruments and Toshiba Mbit as well. And Texas Instruhave introduced versions. But Intel ments described its latest
seems to be the only one supplying flash, a 256k device that uses
in significant volume, and it's Intel only a single 5-V supply.

3-682

ARTICLE
REPRINT

AR-478

December 1989

Flash Memories:
The Best Of Two
Worlds

By

RICHARD D. PASHLEY
STEFAN K. LAI
INTEL CORPORATION

1989 Intel Corp.
Reprinted from IEEE Spectrum with permission.

3·683

Order number 295040-001

Flash memories:
the best of two worlds
Filling a niche between conventional EPROMs and EEPROMs, these dense memories
offer the latter's reprogramming convenience at relative cost advantages
In evolving from a concept paper in 1984 to megabit
devices only five years Illter, flash memories have
moved up the transistor-density curve faSter than any
previous semiconductor memory IC. They are based
on the technology of either erasable programmable
ROMs (EPROMs) or electrically erasable programmable ROMs (EEPROMs), and in price and functionality fall somewhere between the two, suiting any
applications that require the former's denser storage plus the latter's ability to be reprogrammed without removal from a system. They also share these memories' nonvolatility and fast read access.
Those flash devices more akin to EPROMs cost less and promise rapid device and price scaling; their suppliers include Intel
Corp., Santa Clara, Calif.; Seeq Technology Inc., San Jose, Calif.;
and Tokyo's Toshiba Corp. The others, which utilize the more
complex EEPROM technology, are slightly more expensive but
provide more flexible reprogramming. They are made by Texas
Instruments Inc., Houston, Texas, and sampled by Atmel Corp.,
San Jose, Calif., among others.
Of these three types of reprogrammable memory, EPROMs
remain the best choice for applications where data almost never
needs changing. Otherwise, flash memory devices should be considered. Although the average EPROM may sell for about $7,
and a flash memory for about $25, the differential is wiped out
by the expense of a single reprogramming. The in-system
reprogramming of a flash device may cost as little as $1,whereas pulling an EPROM out of a system to erase it by exposure to
20 minutes of ultraviolet (UV) light may cost over $80 when equipment, downtime, and labor are factored in.
Meanwhile, EEPROMs should remain popular wherever it is
necessary to erase bytes selectively. But flash products, which are
erased in their entirety or section by large section, might do better for updating stored logic, when this must be done more than
once but less often than in main memory, cache memory, or
registers. Reprogramming costs are similar, but flash memories
are less than half the price of EEPROMs.
Flash memories may even oust some battery-backed static
RAMs (SRAMs), a bulky combination. In laptop computers, the
flash device would occupy less space, .at a lower cost per bit, and
eliminate the dependency of memory on battery power.
Most flash memories have the same pinout as EPROMs, so
that substituting them in a system requires primarily software alterations. (The densest flash ICs may have a few extra pins, however.) Furthermore, whereas a flash memory will nearly always
be surface-mountable, that is not the case for some applications
of EPROMs, whose packages include a window that must be accessible to UV reprogramming equipment. A flash-for-EEPROM
swap, though, will almost certainly require rerouting the printed circuit, because flash memories may be up to four times denser.
Also, flash ICs closer to EEPROM technology need only a 5-

volt supply, whereas those closer to EPROMs require
a 12-V one as well, to drive the high-energy electrons
that write data into them. This kind also requires
a multistep algorithm that verifies erasure. Its makers
say that the I2-V supply helps protect the IC against
accidental erasure; those that supply 5-V-only versions counter that there are software techniques that
may be employed to render such an accident too rare
to be worth consideration ..
The choice between the two flash memory types
is sometimes determined by the application. In small embedded
controller systems, missiles, or remote battery-powered systems,
a 5-V-only flash memory is preferable. On the other hand, a 12V supply is already available in some systems, such as desktop
personal computers and laser printers.
With software of all kinds becoming more complex, the likelihood of changes to it, to update it or eliminate bugs, increases
proportionately. That, in turn, argues for efficiently reprogrammabie nonvolatile memories, and bodes well for the popularity
of flash memory.
Consider the basic I/O system of a PC. It is typically stored
in ROMs or PROM. Flash memory would allow the changing
of I/O system code over a network or modem within minutes.
Also, portable computer systems' hard-disk drives may be
replaced by flash memory modules offering lower cost, size, and
weight, plus the greater reliability of solid state.
The operating system for an IBM PC AT or an Apple Macintosh is big enough as a rule to need storing on magnetic hard disk.
With each year, however, flash ICs become more economical for
greater amounts of storage; up to 2M bytes of flash memory are
available with a new laptop from Psion Inc., Watertown, Conn.,
for example [see photo). As this trend continues, flash ICs may
supplant hard-disk drives of small capacity (up to 10 megabytes)
in systems that could use a small, reliable memory with low power

Richard D. Pashley and Stefan K. La; Intel Corp.

3-684

Defining ter~s
Electron trapping: the accumulation of electrons In imperfec·
tions in silicon dioxide, so that negative charge builds up and
delays erasure of programmable memory devices.
Fowler-Nordheim tunneling: a quantum mechanical process
in which electrons tunnel through a thin dielectric from (or
to) a floating gate to (or from) a conducting channel-the
erase mechanism in flash memories and the program and
erase mechanism in electrically erasable programmable
ROMs (EEPROMs).
Hot·electron Injection: in this context, the injection into the
memory cell's floating gate by a vertical electric field of elec·
trons with excess energy acquired from a high source·to-drain
channel electric field.
Nonvolatile memory: memory that does not lose stored bits
after power is switched off (includes ROMs, PROMs, EPROMs,
EEPROMs, and flash memories).

IEEE SPECTRUM DECEMBER 1989

The MC400 laptop computer from Psion Inc., Watertown, Conn., uses flash memory modules to replace
disk drives. The computer hasjour module slots, and
each module contains jour Intel 128K-bit flash ICs
in plastic leaded chip-carriers jor a total of 2M bits
of memory. The primary requirement for switching
from disk to solid-state memory is rewriting the operating system's memory management code. Psion also
makes an accessory that lets the user plug the MC400's
modules into any IBM Corp. or compatible personal
computer.

consumption. In such cases, though, another software modification becomes necessary. Data is stored in serial form on hard
disk, and must be reformatted into bytes before it can be sent
to RAM. Data stored on flash ICs is already in byte format, and
operating systems are being rewritten to accommodate this.
At present, the programs for embedded controllers, such as
those that operate automobiles and production machinery, are
kept in other forms of nonvolatile memory. But flash ICs could
serve here, too. And they coulwJer·Nord· increasingly the I·Mbit·and·higher chips
helm floating·gate structure. With access are being produCed in the new TSOP
tim€s of 170 ns, the device can be pro- (thin smaIl-outline) packages. Its small
grammed 1 byte at a time or iil the page form fuctor of 20 by 8 by 1.2 mm makes
mode from 2 to 64 bytes at a time. At TSOP ideal for the Hash-oud marlret as
the 256K level, n is using a 1.5·p.m well as other embedded applications. It
ACEE P1'OCe5S and will scale down to also is desirable for .surfuce.mounted
1.0-p.m for the l·Mbit part. 11's 4-Mbit boards. Another possibility comes
prototype uses 0.8-p.m tcrlmology. .
White Technology Inc. The Phoenix
While flash device vendolS refine de. company's WFI024KB-150 is an 8-Mbit
vice technology and tusSle over the Hash·memory module packaged in a 34right approach, they are also taking pin, hermetically sealed metal package. It
hard aim at those beckoning sockets. Is built with eight l·~it Hash chips, or·
Last month, Intel introduced the first· ganized as 1 Mbyte by 8, and assembled
flash·memory·based Ie card in 1· and .on a thick·film subsIIate. Each of Its eight
4-Mbyte sizes aimed at laptop, note· pages can be erased a page at a time.
book, and palm·top computelS. eard The device is guaranteed for 10,000
densities should converge rapidly to- e!lISe/progI3lll cycles.
ward th
f hard disks d
t1y
Meanwhile, cell sizes for Hash memoose 0
an grea
ries are shrinking !apidly under the asexceed those of floppy disks in the late sault of new approaches to cell.structure
1990s, the company says.
design. Intel radically trims size with a
The Intel cards are intended for ap· new contactless single-transistor cell. At
plications in updatable application the upcoming IntelIlationai Electron· Decode, application-code and data·file vices Meeting, company researcheIs will
storage, and data acquisition. They will describe their Flash Am:y. Contactless
be competing with existing memory· EPROM (FACE) technology, which Iecard technology, which includes ex· duces the area of the E10X cell by 55%
pensive batter:y·backed·RAM cards, un· to 8.4 p.m'. That reduction Is based on
alterable ROM cards, and one-time--pro- 1.0-p.m design rules. At O.8-p.m, the cell
grammable EPROM cards. They are un· can be almost halved again to 2.48 ILrn'.
surpassed as a disk replaceinent in
Also
,...••
portable PCs, says Jim Weisenstein.
. , In.
at IEDM, 1bshiba Corp. will
tel Hash
show a NAND-structured memory cell of
's
. ·memory-card manager in Fal· only 2.3 p.m' (0.6j1offi design rules). The
som, Calif. Reduced power consump- cell can achiere ·1&Mbit and Jarger Hash
tion, resistance to shock, a doubling in memories, 1bshiba sa"". M1tsublshi
write speed, and 3.5 .times faster readl~
time are among the benefits he cites.
Corp. has ~ a single-translstor,
stacked-gate cell of only 3.6 p.m' in a 1&
Meanwhile, MiatJ&>ft Corp. of Red- Mbit Hash. It uses O.&p.m design rules
mond, Wash., has Issued a Flash File and:idlleves 5·Y-on!y programming and
System that rims as a software driver erasure by a iJnique negat!ve-""....biaslng
under MS-DOS. It effeaiveIy makes the e:asing condition. II
...-

from

3-699

ARTICLE
REPRINT

AR-494
November 1990 .

LAPTOP VENDORS dOli
THE FLASH BANDWAGON

AIRIS'S VH-286 USES FLASH TO STORE BIOS, BUT THAiS JUST THE
BEGINNING OF THE APPLICATION POSSIBILITIES ,:ji!/!ratltmtMI

W

memOIY," he says, "why
ropy them to an lntennediate DRAM fust? As la!ger
caches mlgrate lnto the
cenlllli processing unit, the

HEN
TIlE
foundern of
Aid<; Computer
_ _ _ COIp. left 'h!nith Data Systems In 1988
to start a new notebook-

perfonnance chanlcterlstla;

MVMOfl ~~P:Xew~

~~~~

all entrepreneurs must,
companies are haocI. at
that their product strategy
work leve1lngthe COnvellhad to stand out In a
tiona! three-tier memory
auwd. Flash memory
architecture by means of
technology (see p. 44) will
flash-based "silkon disks."
play a major role In Aid<;'s
Among them is Psion
strategy when the fust VHInc. The Watertown,
286 computers start rolling
Conn., company employs
off the production line thls
small llash-based modules
month. But Aid<; is unlikeas replarements for lIoppy
Iy to be alone fur long.
disks. And at least one
Flash is versatile-it leIS
'~.~~~.~~~m
company-SunD1sk Corp.
clever systems houses
The BIOS in Aim's laptops is stoml in a bank 0/flash
of Santa Clara, Callf_-is
such as Aid<; play with Inmemory. With TeIeROM, BIOS can he updak!d by modem.
bulldlng a flash-~ SlDrnovative marketing tech.
age system to rep"""" WIn- .
niques as well as advanced technology. requested for the updating scheme. In chester drives. Flash could everJ. be used
For Chicago-based Aid<;, the bright idea particular, provisions must be made for to SlDre appllcations software, but CXl5t
is ThieROM, says Steve Valentar, engi- the possibiliry that system power may and rellability In massive read/erase/
neering vice president. All Aid<; comput- be lost durlng the BIOS update. "You write environments continue to be Jnhlb.
ern have built-in modems,· and bv com-. have to be sure you have enough itolS to widespread acceptance.
. binlng that capability with a bimk of BIOS available at.all times to boot the
Besides the advantages to laptop
flash memory that stores system BIOS, system," Valentor says. Airis purchases and notebook end-usern, flash offers
Aid<; can offer users a highly desired rea- its flash chips from Seeq Technology considerable advantages In manufacturrure: instantly updatable BIOS. Simply Inc., San Jose, Callf., because they offer ing, says John Wagner, manager of 'h!by dialing into Aid<;'s bulletin board, us- a sector-erase feature that helps imple- nith .Data Systems' Portable Products
ern will be able to update their BIOS fur ment the fail-safe updating procedure. Development Group, Mt. Prospect, m.
a nominal charge.
Storing BIOS is just the beginning fur Although ZenIth has not yet impleSoftware-updatable BIOS ensures flash applications. John Wharton, a con- mented flash, it is studying the technolcompanbility with the latest reatures and tnburing editor to the Microprocessor ogy closely in part because of manufdcsoftware. There are, fur example, undoc- Report, a Sebastapol, Calif.-based news- turing issues. "PIocIucing a machine Ieumented reatures In mM Corp.'s VGA letterisays there is more to come. Con- quires several stages of firmware deVeIgraphics specification, says Valentor. As ventiona! PCmemory systems are orga- opment," he says, "and using flash
these are revealed and utilized In new nized on three-levels: rotaring mass SlDr- memory would let us implement the
applications software, Aid<; users will stay age, dynamic random-access memory, latest velSion in the final stages of mancompanble with a phone call.
and static RAM cache, he says. ~ level ufdcturing. You can also include the
Airis dedicated 128 Kbytes of flash to adds expense In the furm of control log- latest BIOS and system configuration
BIOS updating: 32 for system BIOS, 32 ie, lnterCOnnects, access time, and reli- on a floppy."
for video BIOS,and 64 to a program ability. "If executable progta1llS and data
Psion is already using flash as a flopto update the BIOS. Patents have been are all already on-line in moderately fust py-drive stan(i-in. Its Flash Packs use 1
© 1990 INTEL CORPORATION
Reprinted with permission from Electronics Magazine, November 1990

3-700

Order Number: 295058-001

Mbyte of Intel Coxp. flash chips and
measure about 1 by 2 in., says Brian
James, marketing suppon manager.
Flash Packs can be used as rewritable
storage or as a medium for applications programs. Right now, users must
download applications programs from
a desktop PC to the Psion notebook
computer, but licensing agreements
with major software houses should be
in place by 1991 that will make memo·
ry-card versions of popular MS-DOS
software avai1able. Price is high: $650
for a I-Mbyte card.
- The most conrroversial application
for flash is mass storage. Whether it
will one' day supplant Wlflchesters de·
pends on the ba1ance of the technolo·
gy's strengths and weaknesses. For
notebooks, laptops, and ponables,
flash will save valuable real estate, says
Zenith's Wagner. But just as Imponant
is its form·factor flexibility.
"Flash devices can fit into unusual
space configurations within the cabi··
net. You don't have to lock up space
for a drive early in the design cycle,"
he says. They are also immune to the

read/write· head failures of rotating me·
dia, he says, and are at least 10 times

faster than rotating media.
LASH'S BIG DRAWBACK IS
cost: a 20·Mbyte flash·based
storage device would cost an outra·
geous '4,800 at today's prices, says Air·
is's Valentor. That compares with an
OEM price of $300 for a 25·in Win·
chester. But Valentor points out that
the access·time differential between sili·
con and rotating media must be traded
off against the cost differential.
"Using data-compression teehniques,
you can reduce the numbet of chips
needed to store a given amount of data
and still deliver performance better
than or equal to hard-disk storage," he
says. "In the next two years, we could
stan to see flash drives at about twice
the cost of rotating memory, and that
will make flash's form·factor and per·
formance advantages more attractive."
Flash's advantage in power consumption speaks directly to the con·
cerns of ponable PCs. Somewhat sur·
prisingly, power consumption is
"about a wash in access mode," says

F

3-701

Wagner, but in nonaccess mode, the
disk continues to spin while flash goes
to near zero. "You have to look at the
peak voltage [12· or 5-V erase, depending on vendor] and how many times
you use it," Wagner says. "Changing
BIOS does not happen often, so it is
not an issue there, but in mass storage,
erases happen much more frequently."
Though the biggest market inhibitor
is cost, flash also has a reliability issue
to deal with, and Airis is. taking a waitand·see posture on mass storage. "At
this point in time," says Valentor, "I do
not believe the pans have the number
of reprogramming cycles needed for a
hard·disk replacement, but there is not
a fundamental. inhibitor to longer life,
and I expect to see their longevity Improve." Intel's chips lead the pack with
100,000 erase and reprogram cycles,
but Valentor points out that a ponable
or laptop running a spreadsheet program, for example, reads and writes to
the same portion of the disk. This
means that in a flash·based device
some chips would be used much more
than others. II

ARTICLE
REPRINT

AR-495

November 1990

Store Data
in a Flash

©1990 INTEL CORPORATION
Reprinted with permission from Byte Magazine, November 1990

3-702

Order Number: 295059-001

STATE OF THE ART

MAGNETIC VS. OPTICAL

Store Data
in a Flash
Flash-memory ICs offer new options
for personal computer storage
Walter Lahti and Dean McCarron

N

ormaJly, you'd
think of a flash
.flood as a natural
disaster, something that could pick you up
and carry you away. But the
flood of flash memory that is
about. to reach the personal
computer world will be a positive event. It will carry the
power to expand. the reaches
of personal computing.
Flash memory is a nonvolatile memory IC. Born of the
blending of EPROM and
EEPROM, the flash IC is
functionally and technologically the offspring of these
parents (see the text box "Do
You Remember?" on page
312). It is reportedly named
for the speed with which it
canbe reprogrammed.
While flash and EPROM
memory cells usually contain
a single transistor, a DRAM.
cell typically contains a transistor and a capacitor, an EEPROM cell
two transistors, and a static RAM
(SRAM) cell four or six transistors. Obviously, the more cells, the more real estate (silicon) a memory requires. And,
real estate is always expensive.

Advantages or Flash
Flash's two significant attributes, nonvolatility and DRAM-like speed, are
ILWSTRATION: JOE GAST © 1990

Ideal for solid-state "disk" drives. Flashbased disks are very fast compared to
most available disk drives (see figure 1).
In 120 nanoseconds, you can access data
stored in flash memory, while ittakes 15
to 30 milliseconds to access data stored
on today' s typical hard disk. In some implementations, such as in portable computers, the speed advantage of flash over
disk drives is even greater.
3-703

Today, a personal computer's hard disk drive is one
of its most power-hungry
components~ When you use a
desktop machine, you may
not notice this power consumption. But the power a
battery-operated portable can
supply is limited-and hard
disk drives use up that power
quickly. Most portables today
require fairly sophisticated
power management facilities
to extend the amount of time
the machine can be used.
A portable's power management facility often turns
off the hard disk drive if -it
isn't being used. While this is
great for extending a portable's limited battery life, it is
terrible for performance.
When the power comes back
on, the disk drive's motor can
take several.seconds to bring
it up to speed before disk I/O
can begin. A flash-based disk
needs no warm-up. When you turn on the
power, the data is immediately available.
With no waiting, you experience no loss
in performance.
In addition to achieving power savings
from an "instant-on" flash disk, you also
realize savings from not having to operate power-hungry motors and servos. A
I-megabyte flash disk requires a maxim\lm of only 1.2 watts while operating.

STATE

OF THE ART

STORE DATA IN A FLASH

no'you Remember?
here are two kinds of memory: volT atile
and nonvolatile . Memory such
as DRAM is called volatile if it forgets
what it had stored when you turn off
your computer's power. Memory such
as ROM is called nonvolatile if it retains
its data whether or not your computer's
power is on. As all users who have ever
turned off their computers before saving
files .to disk can tell you, the DRAM
used in your personal computer to store
programs and data cannot relain infor.
mation without power.
DRAM, however, is reprogrammabie; the information it contains can
be changed. When you load a new file,
the new information replaces the old.
ROM, though, is not reprogrammablethe programs and data in ROM are permanent, and you can't change them.
In the early '1970s, the only semiconductor memory available was DRAM,
its cousin static RAM-which is also
volatile-and ROM. The choices open
to computer designers were using memory that was reprogrammable but lost
information without power, and using
memory that always retained information but could never be changed. What
designers really needed was memory
that could be reprogrammed in the system and that also retained its contents
when the power was off.
A few years after DRAM· became
available, a new kind of memory known
as electrically programmable read-only
memory, or EPROM, was introduced.
EPROM is reprogrammable and nonvolatile.But it has one drawback. In
order to reprogram EPROM chips, you
have to remove them, expose them to
high-intensity ultraviolet light for as
long as 20 minutes, reprogram them,
and then replace them in your' computer.
Thus, EPROM fell short of being the
ideal memory. Today, because vendors
find them easier to program, EPROM
chips are largely used as replacements
for your personal computer's ROM.
Electrically erasable programmable
read-only memory, or EEPROM, was
introduced in the late 1970s. EEPROM

The lowest-power hard disk drives today
require about 3 W.
The fact that flash-based disks have no
moving parts carries with it yet another
advantage-reliability. While hard disk

(like EPROM) is reprogrammable and
nonvolatile, and it can also be easily reprogrammed within the computer.
Still, there. are drawbacks. EEPROM
is slow and expensive' and doesn't hold
very much data. Today, you can store 1
megabit of data in an ordinary DRAM
chip. You can access the data in 80
nanoseconds, and it costs $5. In contrast, it takes 150 ns to access a 1-Mb
EEPROM, which costs $265.
In the mid-1980s, Toshiba Semiconductorinvented flash memory. About
the same time, Intel and Seeq Semiconductor were also working on flash memory. While each manufacturer built its
flash memory differently, they operate
similarly.
Like both EPROMs and EEPROMs,
flash memory is nonvolatile and reprograritmable. But it has none of the faults
of these other types of memory. Unlike
EEPROM, it is inexpensive: Today, a
I-Mb flash memory costs about $15.
Unlike EPROM, flash memory can be
reprogrammed electrically while it is
, embedded in the system-either by you
or via system software.
Still, one drawback remains. With
DRAM, you can change a single bit at a
time, 'but with flash memory, you can
change only a sector (consisting of mul-

tiple bytes) at a time. While constraints
of sector-level reprogrammability prevent it from replacing your computer's
DRAM, flash memory is well suited to
other applications.
The type of storage that hard and
floppy disk drives provide' resembles
that of flash memory. Disks are nonvolatile-they hold onto data with or
without power. And disks are reprogrammable-you can change the files
whenever you want to. The similarities
between flash memory and disk storage
led to the building of "disks" based on
the concept of flash memory.
A flash disk isn't a disk drive at all;
there are no disks or moving parts. A
flash disk is a set of flash-memory parts
mounted in a credit-card-size package
that acts as a hard disk. This same set of
parts could be mounted on a board inside a machine. The difference between
the two is that one is removable storage
and one is fixed storage. A flash disk
emulates a disk drive.
A flash disk is built from one or more
flash-memory ICs and some controlling
logic devices. For example, to build a
5 12K-byte flash disk, you could connect
four I-Mb flash-memory ICs and place
them on a small card. Psion has used
this principle with its flash disk (see the
photo).
Flash disks operate fairly simply. At
the hardware level, the computer simply
sends digital read or write signals to the
disk with the address of the information.
If it is a read signal, ·the disk responds
with the requested information. If it is a
write signal, the disk takes information
from the computer and stores it.
In addition to flash-disk hardware,
you also need software to manage the
files on a flash disk. This file-system
software handles creating and deleting
files, changing the file sizes, and formatting the flash disk. Microsoft has
worked with Intel to create the Microsoft flash file system, a standard MSDOS-compatible flash-disk interface
that makes it much easier for vendors to
use flash disks in their computers.

drives have become remarkably tough,
on occasion they still do crash.
Flash-based storage is very reliable because a flash disk is as tough as the rest of
the electronic hardware in a personal

computer. It takes a lot for a flash disk to
fail: The flash memory must be damaged
physically, through destruction of the device package, or electrically, by an extreme electric shock or a power spike.

Psion uses four Intel I -Mb
flash-memory ICs in its credit-cardsize solid-state disk.

3-704

STATE OF THE ART

STORE DATA IN A FLASH

Disadvantages of Flash
Flash memory's extremely high speed,
low power, and high reliability would
seem to make it the ideal storage technology. Unfortunately, there are two significant drawbacks to flash disks. The most
severe limitation is its cost. A conventional40-MB hard disk drive costs about
$320, or $8 per megabyte. Today, a 1megabit flash Ie costs $15. Eight flash
Ies are needed per megabyte of flash
disk, making a flash disk cost about $120
per megabyte.
Thus, you would have to pay about
$4800 for a 4O-MB flash disk, or about
15 times what an ordinary hard disk
drive would cost.· Because of this present
inequality, the first mass-produced
flash-based disks probably will store less
than 40 MB. In the future, flash-based
disk prices will certainly decline, making large amounts of flash-disk storage
more affordable. In a few years, you
should only have to pay about $600 for a
4O-MB flash disk.
The other problem with flash disks is
that they can't compare with hard disks
in density. The highest-density flash
memory available today stores 2 Mb per
Ie-you would need 160 of these Ies to
produce a 4O-MB disk. Like all memories, flash memory is expected to grow in
density, so eventually far fewer Ies will
be needed.

Figure 1: Flash
disks are 125,000
to 250,000 times
faster than today's
hard disk drives.
However, they are
limited to up to 40
MB in capacity,
whereas-hard disk
drives can store
from5MBto 1
gigabyte.
Ideal for Laptops and Palmtops

Laptop and notebook computers are the
ideal applications for flash disks. With
current hard disk drives, you must carry
around heavy batteries, deal with short
amounts of work time, or suffer from
hard disk drives operating at floppy disk
drive speeds. Flash disks will answer all
your critical needs for laptop and notebook computers by providing speed,
rugged construction, and low power
Two Flavors
Manufacturers currently offer flash de- consumption.
'
vices in two programming flavors: those
You can also benefit from flash memthat require a 5-volt power supply, and ory in other implementations. Flash will
those that require a 12-V supply. With let you update your laptop's ROM with
both erasure and programmability possi- the latest versions of DOS, or any other
ble at 5 V, only one power supply is re- operating system, whenever you want to.
quired at the system level. The benefits of Laptops save space on disks and in RAM
this feature are reduced system-compo- by placing the operating system in ROM.
nent cost and space savings. Thus, flash The problem with this is that you can't
is ideal for portable-computing applica- update the operating system without retions.
placing the entire ROM-an expensive
The 5-V flash cell is generally a mod- proposition. Thus, laptops often use old
ified two-transistor (or split-gate) deriva- but reliable versions of DOS. Using an
tive of EEPROM and is packaged with a old version of DOS may mean that your
different pin-out than the 12-V varieties. computer won't need a ROM replaceFive-volt programming lets a system ment in the near future, but it may not
interface with the device in much the run recently written programs, either.
One thing lacking in palmtop comsame way it would with SRAM. Therefore, for some applications, a flash de- puters, such as the Poqet PC and Atari
vice can replace SRAM, particularly in Portfolio, is small, convenient mass storsystems that use SRAM with battery age. Without any optional peripherals,
backup.
their storage is limited to programs on
While both 12-V and 5-V flash mem- ROM cards and memory-expansion
ory can be used as an SRAM replace- cards that lose their contents when they
ment, the 5-V feature becomes more de- are removed. With flash-based memory
sirable for portable equipment· where no cards, you can put your own programs
extern!\1 12-V power is available and the and data onto the card, modify them at
addition of a 12-V power supply is not' will, and not worry about losing the infeasible.
formation when you remove the card.

3-705

These features make flash-memory
cards the logical choice for the palmtop's
missing "floppy disk drive ...

Laser Printers
If you use a laser printer, you can benefit
significantly by using flash memory instead of ROM. In laser printers, ROM
stores programs and fonts. ROM replacements are expensive because printercontrol language programs have become
large and are subject 'to frequent upgrades and improvements. Using a laser
printer equipped with flash memory instead of ROM to store control-language
programs, you can reprogram your
printer's control language yourself at no
cost and without replacing any ROM.
Currently: laser-printer font-storage
options leave much to be desired. You
have three.choices. You can download a
font to the printer each time it is needed,
wasting your time and the laser printer's
memory. You can place a font in a ROM
cartridge and plug it into the printer, but
you are limited to a selection of only a
few fonts out of the hundreds available.
Or you can store a font on a dedicated
hard disk connected to the printer.
But when you use flash memory inside
your printer, you only have to download a
font once and it remains in your printer
until you choose to delete it from the
printer's memory. Because you decide
which fonts are stored in the printer's
memory, you can really personalize
them according to your preferences. You
no longer have to buy cartridges that
come with a half-dozen fonts just to get
the one font you need.

STATE

OF

THE

ART

STORE DATA IN A FLASH

Fabrication Techniques
Flash devices are manufactured using designs and processes similar to those used
for EPROM and EEPROM, so the technology is evolutionary rather than revolutionary. Because manufacturers have Figure 2: Aflashdealt with similar products, they will be memory cell is
able to climb the learning curve much basically one
more rapidly than if the technology were memory bit (on or
completely new. Thus, vendors planning off). An array of
to produce flash memory should be able up to 4 million
to attain manufacturing costs close to, flashcmemory
but perhaps not equal to, those enjoyed cells can be
by EPROM.
connected to form
However, flash devices are a bit more aflash Ie.
complex and more silicon-hungry than
EPROM devices. The most common
flash chip is an array of single-transistor sector or the entire chip.
memory cells and looks much like an
Because the flash device does. not reEPROM (see figure 2). It is slightly quire UV light for erasure, the chip does
larger than an EPROM of equal density not need to be housed in an expensive ceto allow for the command port and pe- ramic window package such as that reripheral circuitry that supports the in- quired for an EPROM. Therefore, flash
system rewrite function and provides an is also an excellent candidate for surfaceon-chip processor interface.
mount technology.
The typical EEPROM chip is made of
The advantage of surface mount is that
an array of two-transistor cells to enable there is less distance between the device
bit-level erase/reprogram. For any given and the board. This reduction can lead to
density, it requires much more silicon improved reliability, beller system perthan either the EPROM or flash cell. Be- formance, and higher board density, as
cause a major cost determinant in any IC well as reduced cost. Also, the flash deis the silicon required, the EEPROM is a vice can readily be packaged in memorymore expensive part.
card configuration and handled as if it
were a floppy disk, which is important to
Erasing and Reprogramming
the portable computer world.
In terms of reprogrammability, the flash
The total cost of using flash memory
IC falls somewhere between the tradi- can be considerably lower than that for
tional EPROM and EEPROM (see figure EEPROM and, with some applications,
3). A major difference between flash close to that for EPROM-about $6.50
memory and EPROM is that flash does for a I-Mb EPROM versus over $250 for
not require ultraviolet light for erasure, a similar-size EEPROM. On a comparaas does the traditional EPROM. While
flash resides in your system, you can
electrically erase it in much the same
way as you would an EEPROM.
The energy needed to discharge or
erase the gate in a typical EPROM is derived from UV light, a requirement that
makes it difficult and time-consuming to
erase an EPROM. In a typical flash IC or
EEPROM, energy resident in the system
can be used to erase a group of memory
cells or the entire chip. This feature
makes it easy and fast to erase a flash IC Figure 3:
in the system.
Technology tradeYou generally cannot erase a flash IC offsfor
on a byte-level basis as you can with the semiconductor
EEPROM, but some flash ICs can be nonvolatile
erased on a sector-level basis. Flash ICs memories. As
are usually reprogram mabie by hot elec- programming
tron injection, a solid-state physics pro- flexibility
cess that uses the energy in the system. It increases, so do
is possible to program on a byte level, but device complexity
because it is not possible to erase on a and cost.
byte basis, reprogramming is limited to

3-706

ble device-density basis, flash·memory's
$15 average selling price is much lower
than the EEPROM's and greater than the
EPROM's. With flash, application solution's are possible that would be impractical with either the UV -light erasure
EPROM or the pricey EEPROM.
The law of the semiconductor jungle is
that over time, all device types see improved performance and reach ·greater
density levels. At the same time that silicon real estate is minimized, costs are
significantly reduced. By 1994, the cost
of a megabyte of flash memory is expected to move from its current level of
about $120 to about $15.

Flash in the Pan?
Unless developers are able to overcome
the current limitations of flash disks, you
will probably continue to use hard disk
drives on your desktop computer for
mass storage. Hard disk drives are inexpensive and fairly reliable, and they can

STATE OF THE ART

STORE DATA IN A FLASH

LaPIOPand
notebook computers are
the ideal applications
for flash disks.

-

store plenty of data. Although singleuser personal computers will probably
continue to include hard disk drives,
eventually network servers will probably
offer both hard disk drives and flash·
disks on-board.
On many servers, you frequently access files, such as programs, that are
rarely changed. Flash disks are ideally
suited to perform this service. You can
store seldom-changed program files on
flash disks, relieving the burden on the
server. By doing so, the server's response to program load requests will be
far faster than if the files were stored on a
hard disk.

3-707

Flash memory combines the advantages of an EPROM's low cost with an
EEPROM's ease of reprogramming.
These advantages will allow flash memory to make significant contributions to
personal computers. Portable computers
will be the first to benefit from this new
technology, as flash-based disks increase their speed, operating time, and
ruggedness .•
Walter Lahti and Dean McCarron are
vice presidents of In-Stat (Scottsdale,
AZ), a company that provides market research for the electronics industry. They
can be reached on BIX clo "editors . ..

ARTICLE
REPRINT

AR-497

January, 1991

Designing With
Flash Memory

By
MARKUS A. LEVY

© INTEL CORPORATION,.1991

Reprinted with permission from Circuit Cellar INK

3-708

Order Number: 295061-001

FEATURE
ARTICLE
_ _.. Markus A. Levy

Designing with
Flash Memory
Is There· a New Alternative to EEPROM and SRAM?

Flash memory (in general) is capturing market share from other memory technologies. It is replacing EPROMs that were traditionally used for code storage
because. along with equivalent nonvolatility. it also allows In-system updates. Battery-backed SRAMs that once were used for data acquisition. parameter storage.
and even solid-state disks are now targets for the inherently nonvolatile and lowercost flash memory devices. Many notebook computer OEMs conclude that low
power. light weight. and reliability are most easily obtained with a completely solidstate machine. Flash· memory has achieved a density ramp from 256K bits to 2
megabits in two years. Combined with a special flash file system from Microsoft. flash
memory can even replace the mechanical disk drive.
With the design described in this write interface. Erase. program. veriarticle. you have a platform demon- fications, and other operations are
strating flash memory's functionality initiated by issuing the proper comand flexibility. Applications range mand to the flash memory device.
from data acquisition through an I/O Twelve volts must be applied on Vpp
port, to a OOS-compatible, solid-state . for the command register to respono
disk. But first, a few essentials.
to writes and execute the operation.
The 12V requir~ment doubles as an
EPROM AND BEYOND
added security feature for data integrity. If you are familiar with other
. Derived from an EPROM proceSs memory subsystems, designing with
base, Intel's E'IOX-II flash memory flash memory isas simple as any other
technology has similar nonvolatility, technology.
reliability, and array densities. In fact,
In addition to discrete compothe flash memory cell is identical to nents, Intel offers flash memory in
the EPROM structure, except for the SIMM and IC memory card formats..
thinner gate (tunnel) oxide. This is This design will use these modules, so
where the similarities end. The thin- I'~e included some pertinent inforner gate oxide enables flash memory mation. The 512K-byte x 16 Intel Flash
to be erased and reprogrammed in- SIMM (SM28F001AX) is based on an
circuit, typically 100,000 times. The 80-pin JEDEC standard that accomname "flash" is derived from its one- modates density upgrades and pres~.
second chip-level erase and microsec- ence detect (a hard-wired ID that indiond-level byte-write times versus the cates SIMM density and speed). The
slower, millisecond-level byte-write eight I-megabit flash memory devices
times for conventional EEPROMs.
on this module are paired up as high
Flash memory devices have a and low bytes. Theyare selected using
command register architecture that the SIMM's write enable high and low
provides a micronrocessor-compatible (~WEH and ~WEL) signals.
3-709

Intel'slC memory card adheres to
the Personal Computer Memory Card
International Association (PCMCIA)
standard. This standard specifies
physical, electrical, information structure, and data format characteristics
of the card. Most impressive is the
size, measuring 85.6 mm x 54.0 mm x
3.3 mm. Its 68-pin interface includes
26 address lines used to directly address 64 megabytes. All buffering and
chip-level decoding is contained
within the card, greatly simplifying
the board-level design. Intel's flash
memory card is available with one
and four megabytes. These cards will
continue to grow in density, becoming more and more competitive as
disk drive replacements.
MEMORY METHODS

Three fundamental addressing
methods can be implemented when
interfacing a flash memory array to a
system bus: linear, I/O, and paged.
Eachmethodhasitsbenefitsanddrawbacks. A linearly addressed memory
array is mapped directly into the. sys-

tern's memory space and allows the
highest perfonnance. However, the
memory array would be insufficiently
small in systems having limited
memory space, as with the 8086. But
this method is practical in an 80386 (or
other 32-bit processor) family system
with a large memory space available.
An I/O-mapped memory array
uses one address-an I/O port-to
transfer data. This method requires
the least amount of system memory
space but also yields the lowest perfonnance.
. A page-mapped memory system
is a hybrid of these two approaches. It
allows a very large memory imay with
a minimal system interface. A page is
a moveable window into the total
memory array. It selectively opens

different portions of the array by wri ting a page number to the decoding
circuitry. This page rangesin size from
8K to 64Kbytes. Analogous to a cache,
a larger page size requires less frequent switching. Although switching
pages represents a performance degradation, this can provide the optimal
balance between performance and
memory space availability within the
system.
Our design is based on this pagemapped technique. A 64K-byte page
size reduces the decoding circuitry.
The PCI AThas been chosen as the
execution platfonn, but with minor
modifications to the control signals,
any microprocessor environment can
be used. Before beginning this design,
it would be helpful to reacquaint

I

. Address

rio

Data

Presence Detect

Decode

110 Control

I· Vpp Enable

System
Bus

Vpp
Generator

Page
Select I>-

,.

Intel
Flash
Memory
Array
and
Xceivers

Vpp

Chip Enable (CE\)
Memory
Decode

Read (RDI), WEL, WEH
Transceiver Select

Figure l-.1he subsystems In a flash memory board design include memory decode, 110,

and a 72V generator.

3-710

yourself wi th the basics of the AT I/O
channel bus.
The subsystems within this design (Figure 1) are the memory decode
circuitry, I/O and its associated decode logic, and a 12V generator for
Vpp' The Intel flash memory resides in
four SIMMs. The board handles an
upgrade path to 16M bytes, based on
4M-byte SIMMs.
ADDRESS DECODING

Flash memory addresses can be
decoded in one of two ways: rowcolumn and conventional decoding
using separate chi p enables. The rowcolumn approach of Figure 2is appropriate if you are motivated to reduce
board traces. In row-column decoding, rows are Output Enables ("OE),
Write Lows ("WRL), and Write Highs
("WRH); and columns ate Chip Enables ("CEl.
Although the
SM28FOO1AX uses only four chip
enables, eight are provided since fourmegabyte SIMMs could consist of sixteen 2-megabit flash memory devices.
Page selection, discussed in more
detail later, is acc;omplished by
writing the page number through an
8-bit I/O port to a.latch. This will
allow access to 256 64K-byte pages.
Page signals, PO-P2, are directly connected to A15-A17 on each SIMM.
They decode pages on the device
level. The row-column signals are derived by decoding page signals P3-P7.
.. They .enable components on the
SIMMs.
The row-column approach, however, suffers from simultaneous selec-

PO,PU'2

741138'
P3

3TO.OECODEA

"

:k

__+-____-+t.~==j[if--1f~;;;:~,c=~~,~,~;,~,~,~,~,~,~~

.

P7--JPI..----

:

.

-:

:

,

. .
:

:

:

:

:

,

,

,

Figure 2-Row-column addressing can be used to reduce board traces.

TOSIMMO
SOCKET

TOSIMMl
SOCKET

SMEMRII
SMEMW.

TOSIMM2
SOCKET

TO SIMM3
SOCKET

Figure 3-Uslng separate chip enables trades off board complexity for low power usage.

TOSIMMO

TOSIMM1

TOSIMM2

TO SIMM3

Figure 4-A simple buffering scheme is used to connect the memory to the system bus.

3-711

PCMCIA STANDARD
MEMORY CARD

.:.A:::0-;.:,15::..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..,AO-15
CSLI (Chip Select Low)
. MEMOECOOE'
CSHI (Chip Select High)
74x273

0;,;;0..;,-7_ _ _ _ _ _ _ _ _-;00-7 00-7 ~Al:.:6~-2::.3_ _-I A16-23

lOW'

.>-------i>'CLK
CLR

10 PAGE NUMBER

CONTROL SIGNALS

""""IC~dICuIIJ)

RESET.

Figure 5-Movlng some buffering onto a separate memory card reduces the amount of
necessary Interface hardware.

Figure 6-DIP switches are used to set the board's address in the PC's I/O space.

tion of eight parallel device chip enables. The conventional, separate chip
enable decoding method has lower
power consumption. Using this
method (Figure 3), upper page signals, P6 and P7, decode which SIMM
is selected.
Page selection becomes more
complicated when accounting for
density upgrades. To understand this
there are two things to keep in mind:
each SIMM socket .handles a maxi-

mum of 64 pages, (i.e., 4-megabyte
SIMMs), and A17 is used on a 2-megabitdevicebutisa "No Connect" on the
l-megabit part. A "No Connect" pin
implies that page selection will not be
con tiguous with SIMMs less than four
megabytes in size. Accommodating
noncontiguous pages increases software complexity. Regardless of the
page decoding method, a jumper
scheme rearranges the page signals
and accommodates density upgrades.

3-712

According to Figure 2, the jumper
settings are as follows:
1-MByte SIMM-J7, J2, J9, J4
2-MByte SIMM (16 x 28 FOlO)J7, J1, J3, J5
2-MByte SIMM (8 x 28 F020)J7, J1, J9, J3
4-MByte SIMM (16x 28 F020)J8, JI, J6, J3
Figure 4 shows the buffering required for system bus interfacing. The
PC II 0 channel bus is limited to two
TTL loads on anyone line. The "A"
transceivers are connected directly to
the I/O channel bus. Additionally,
each SIMM has its own pair of "B"
transceivers to reduce capacitive loading that results from tying more than
eight flash memory devices together.

VPPENI
IOR4J
Read to determine
Vpp status r----~J__,

MUA120

.--_---<......,~ Vpp

,a,,,
.........

r---------~----RESET
(from system bus)

RESET'

SIMPLIFIED DECODING HARDWARE
You are not limited to using
SIMMs in your design. The.same basic
techniques will work for discrete components or other module types, sudI'
as memory cards. The ICmemorycard
provides the simplest solution with
its integrated decoding. Writing the

Figure 7-A regulated boost Converter made from LInear Technology's LTl072 supplies
the 12 V necessary for programmIng.

page number through an 1/ 0 port to a
latch accomplishes the same page selection as before, but now the "data"
translates directly into memory card
address inputs AI6-A23. This eliminates the entire decoding structure

3-713

shown in Figure 2 or 3. The IC card
itself also contains the "B" transceiver
buffering. This results in the hardware reduction shown in Figure 5.
You will want to purchase a springloaded connector from Fujitsu, AMP,

I

RESET.,~
MC34064P

UNDERVOLTAGE
SENSING CIRCUIT

~

Vee

74.138
P3

~t=

P

r

3 TO 8 DECODER

:

VO
VI
V2
V3
V<
V5

-

C

GI

MEMDEcODE. - - - c G2A

V6
Y7

G2B

CEO#
CElt
CE2.
CEJII
CE4I
CE5I
CE6I
CE7.

GND
Chip Enables will not be active until Vee • 4.6 volts.
At this point. signals ar~ stable and involuntary writes will not occur.

Figure 8-An MC34064P undervoftage sensor /s used to dsable all writes to memory when
the power starts to fa/I.

or lIT Cannon to use with the memory card, laying out your board so that
the memory card can be retrieved out
the back of your Pc. Pushing the button ()n the connector ejects the memorycard for data security or transport.

byte boundary within the DOS 1megabyte range, but only the adapter
ROM area between COOOOH and
EOOOOH will alleviate compatibility
problems.Using additional inputs on
the "Memory Decode Enable" 74x521
and an 8-input DIP switch allows
I/O PORTS ON THE PAGE MEMORY window placement above 1M byte.
BOARD
Simply connect address lines A2G-A23
to input pins P4-P7, respectively. The
The page-selecting I/O port Presence Detect (PD) pins from all
mentioned is one of eight ports il) this . four SIMMs are wire ORed together
page memory board design. The into the 74x244. This eliminateshav74x521 comparator'sinputsbegin with ing to read each SIMM's PD pins sepaA3 to simplify the decoding circuitry rately, but SIMMs must be installed
for the I/O port addresses. This places with equivalent density and speed.
The page number is written and
the base I/O port on an even 8-byte
boundary. Use discretion when set- read through the same I/O port.
ting the switch to avoid conflict in the Minimal circuitry ensures that the
AT environment. I recommend using system powers up at page zero. The
I/O addresses between 300H and page memory board's *RESET signal
318H because. this area is assigned for connected to the CLR input of the
prototype cards.
74x273 latch accomplishes this task.
Listed in the order in which they
appear on the 74x138 decoder in Fig- Vpp GENERATION
ure6, the eightI/Oports in this design
are: BIG-BI3 (accesses the board's idenWhy is V generation necessary
tifiers); the window address within on this flaSh 4~mory board wl1.en the
the system's memory space; the AT I/O channel already has a 12-V
SIMM's presence detect; the V ena-. supply? True IBM-compatible PCs
bling register; and the page nlimber specify the necessary ±5% 12-V supreading and writing ports~
ply tolerance. However, some systems
I didn't diagram the board's iden- have wider 12-V supply tolerances.
tifier circuitry because the implemen- Local12V generation via the circuitry
tation is extremely simple. It consists described below ensures fast, reliable
of four identical units made up of a flash memory operation.
74x244 and an 8-input DIP switch. The
Linear Technology's LTl072
four enables, BIG-BI3,from the I/O switching regulator, a 5cV-to-12-V
decoder connect to the corresponding feedback regulated boost convertor,
unit'senable. The I/O space is scanned is the heart of the V generator (Figfor the identifiers to locate the board. ure 7). A l00-1lf cap~citor at the outThe user-selectable page window put handles up to 200 rnA, necessary
address can be placed on any 64K- for software that programs or erases
3-714

Eft'

to fully charge to 12 V. Reducing the
output capacitance value and limiting
the number of flash memory components accessed simultaneously decreases the ramp time. The diode,
MUR120, prevents inductor current
absorption from the charged output
capacitor. During system power-up,
spurious noise may generate writes
which are actually the sequence of
flash memory commands that initiate
erasure or programming. Disabling
V until voltages stabilize provides
pi;~er-up protection. The Motorola
MC34064P is an undervoltage sensing circuit that begins functioning
when Vcc is above 1 volt. BetweeJ1 1
and 4.6 volts, theMC34064P's *RESET
output or AT system RESET clears the
74x74. While the 74x74 remains cleared
(or *Q = 1), the 2N3904 is on, the VC
input of the LTl072 isO volts, and the
VOLTAGE SWITCH (VSW) output is
off. Writing a one to the Vpp enable
latch forces *Q low, turning off the
transistor. This puts the VC input at 5
V, and VSW output generates 12 V.
You do not need the circuitry just
described if your system's 12-V supply meets the V specifications. However, because ~ftware may accidentally (or coincidentally) generate a
viliid flash memory command to a
flash memory address, install a swi tch
to turnoff V when notin use. A lowresistance PFET (Motorola MTD4P05)
performs this duty.
The possibility of spurious writes
to the flash memory devices during
power-up still exists. Again, the same
undervoltage sensor(MC34064) solves
this problem. The *RESET output becomes the 74x138 decoder's activehigh enable. This controls the chip or
write enables for the flash memory
devices (Figure 8).

A FEW ADDITIONAL POINTERS

Figure 9-The flash erase algorithm.

eight flash devices simultaneously.
Turning Vp off when not in use conserves po~er, but this capacitance
value requires approximately 100 ms

Ground *MEMCS16 so the PCI
AT recognizes your board with a 16bit bus width. The original design
operated in both 8- and 16-bit systems. This flexibility is accomplished
with additional decoding that multiplexes the high data bus onto the lower
data bus. Again, the IC memory card
automatically conforms to either bus
3-715

width because the extra decoding is
handled internally.
As with any circuit design, it is
important to follow good design principles.For example: decouple power
supplies with O.1-J,LF capacitors between Vcc and Vos of every device; and
short board traces help minimize noise.

SOFTWARE
Hardware without software is like
a computer without a processor. Therefore, understanding program and
erase algorithms is the first step towards functional flash memory. Recall from our earlier discussion that
operations on flash memory are software controlled using the internal
command register architecture. I have
included the complete algorithms
(Figures 9 and 10). [Editor's Note:

Software for this article is available on the
Circuit Cellar BBS and Software On Disk
#18. Seepage 92 for downloading and ordering infonnation.} After working the
Intel flash memory hotline, I would"
like to discuss the common mistakes.
The best piece of advice that I can
give is please follow the algorithms.
Many people unsuccessfully try their
own custom versions. There are no
cutting comers. Starting with the basics, let me elaborate a few points about
the algorithms:
1) Flash is programmed to a binary zero by adding charge to the
transistor's floating gate. Contrarily,
charge removal erases the cell to a
binary one. During the erase operation, the device is "flashed"'as charge
is simultaneously and equally pulled
off the floating gate of every memory
cell. The device must be preprogrammed to all zECros before erasure
so an already erased cell is not further
depleted of charge.
2) Prior to writing any command,
switch on V and allow ample ramp
.
for proper
pp
•
D roppIng
.
tIme
operatIon.
V below 7.5 volts from within any
o~ration, places thedevicein the read
mode. Similarly, abort an operation
by issuing two consecutive reset
commands (FFH) followed by the read
command (DOH).
3) Closely observe delay times to
achieve the highest performance and

"permanent" whenitmatches the data'
being programmed.

USING YOUR PAGE MEMORY
BOARD AS A DATA RECORDER

Figure IO-7he nash programming algorithm.

reliability. Use the STI instruCtion in
the software drivers to avoid system
interrupts during these delays.
Execute eLI once the corresponding
verify command is issued.
4) The verify operation internally
creates marginal conditions to ensure
accurate and reliable results. The 6-!J,s
slew time delay following the verify
command allows the margin voltages
to settle. In the verify mode, programmed data is guaranteed to be

There is a nearly endless list of
data recording applications, including digital imaging, digital photography, point-of-sale terminals, patient
monitors, and flight recorders. The
page memory board is appropriate
for many data recording applications
where an I/O port ofthe PC/ ATaccumulates data_
The programming algorithm
demonstrates the byte programming
capability of flash memory. In other
words, once the device is erased, bytes
reprogram randomly. In some recording applications, data is received in
packets. A pointer determines where
to begin programming the next free
location within the flash memory.
Interleaving increases write performance by using the idle time during the 1O-!J.S program delay. Addresses are offset such that each successive data byte gets written in different devices, looping back in time to
issue the verify command. Reading
the data back would be done in a
similar fashion.
Word-wise, or parallel, program. ming of two devices provides an
additional means of increasing write
performance. Note that flash memory
devicesmayprogramatdiffcrentrates.
Therefore, the original algorithm must
be modified during the verify.operation. If only one byte of the word has
verified, the program command and
data are sent again to the unverified
byte. Mask the command sent to the
device that verified to maintain wordwise programming. A mask is· the
substitution of'a reset command for
the program and verify commands.
That way, the programmed bytes do
not get further programmed on subsequent pulses.
The page memory board will
perform these software techniques.
However, first write the software that
determines the location and capacity
of the board. First, scan the I/O space
for the board's identifier. The location
of the first identifier byte is also the

3-716

base address for the eight I/O ports.
Using the proper offset, read the I/O
port that enables the base-memory
address transceiver. For SIMMs, calculate the memory capacity by first
reading the Presence Detect pins, followed by reading the individual flash
memory device identifiers. Alternatively, read the Card Information
Structure in the PCMCIA standard
memory card for the capacity.
The preceding steps will confirm
the basic functionality of your hardware. Practice programming the flash
devices with data from a RAM-based
array. For example:

; Software to read in ASCII test
; pattern to program into flash

DATA_ARRAY SEGMENT
DB
DB

'ASCII test pattern to
'be stored in flash'

DATA_ARRAY ENDS
CODE SEGMENT
mov ax, DATA_ARRAY
mov
mov

ds, ax
si,O

mov

ex, size STORE_IN_FLASH

more_input:
mov

aI, [siJ

call FLASH_PROGRAM
inc si
loop more_input

SOURCE
Inlel Uterature: (BOO) 548-4725

Data sheels
SM2BFOOIAX
IMaJOIFL
4MaJOIFL
2BF020

1 M-byte SIMM
1 M-byte IC memory card
4 M-byte IC memory card
2 M-bit device

#290244
#290399
#290388
#290245

Application noles
AP325, Guide 10 Rash Memory Reprogramming
AP343, High-Density Applications Using Intel Rash Memory

J

#292059
#292079

Now the fun begins. Once you've
put your Hash Paged Memory Board
together and tried it out, imagine converting it into a solid-state disk. It's
been done using software drivers from
Microsoft. In an upcoming article, we
will discuss the structure of the Microsoft Hash File System and show you
how to interface it to your board.
Finally, I would strongly suggest
that beforeatt~mpting this design, you
obtain the appropriate flash memory
literature from Intel (see the source
box).

+

Markus Levy is an application engineer at
Intel Corporation in Folsom, California, and
holds a B.S.E.E from California State University. His specialties include software and hardware implementations of solid-state disks in
portable computers. His favorite away-fromwork pastimes include home remodeling,
swimming, and parenting.

intel·
BOOT BLOCK FLASH:
THE NEXT GENERATION
INTRODUCTION

2.000..--------------~-,

Flash memory offers a whole new dimension to nonvolatile memory applications because of its high density
and cost-effectiveness. Embedded systems, such as PC
BIOS, hard disk drive controllers and laser printers,
were among the first applications to utilize. the e~sy
update capability of Flash, allowing system dIfferentIation and upgradeability. In 1992, Intel introduced a ~e­
ries'of high-density Flash Memory Cards based on Its
8-Mbit FlashFile™ component, 'products that are enabling truly portable computing capability with diskless, solid-state mass storage. Intel also added two flash
memory products designed specifically to serve more
traditional embedded and portable applications, offering both high performance and low power consumption
options in an architecture specifically designed for these
applications storage requirements.

MARKET GROWTH DATA
In the four years since Intel first introduced its
256-Kbit flash devices, the worldwide demand has
quadrupled annually, with 1992 market demand forecasted to exceed $270 million. Flash is expected to continue double-digit growth through the upcoming years
while other memory technologies are relatively flat or
increasing only slightly. By 1994, the flash mar~et is
expected to exceed $1 billion (Figure 1). The pnmary
reasons for this growth are well acknowledged bycustomers: flexibility, nonvolatility, low power and cost~ef­
fectiveness. As a result of this seemingly insatiable demand for flash, the memory density treadmill that allowed DRAMs and EPROMs to double every 18
months has accelerated faster than ever before. Intel's
introdu~tion of an 8-Mbit component two years after its
2-Mbit product is evidence of the flash memory's rapid
. advancement.
Intel's first generation of flash devices~ ranging in density from 256-Kbit through 2-Mbit densities, were rapidly adopted into code storage' applications which formerly used EPROM or EEPROM. In 1991, Intel ~ntro­
duced the first I-Mbit Boot Block flash memory m response to direct customer requests. As ~ result. of continuing to improve and develop an mnovatlve and
broad product line, Intel held an 85% share ofthe $130
million 1991 market.

1.500

Source Dataquest: January 1992
Figure 1

INTEL SERVING TWO PRIMARY
APPLICATIONS
Today, Intel fla~h is serving two major application segments: updatable code storage and solid-state. mass
storage (Figure 2). Code and data storage compnse the
updatable non-volatile memory applications that require li'igh performance, high density and easy update
capability. These applications are infrequently upd~ted'
when compared to solid-state mass storage' apphcations. In this case, erase/write performance is not as
critical as integration and performance requirements.
This application segment is served effectively with full
chip-erase or boot block products.
The second major application segment is solid-state
mass storage that requires very high density, automated
programming and high performance erase/write capability at a very low cost per bit. Erasing and writing
portions of the code or data is much more frequent in ,
- solid-state mass storage than in updatable firmware applications. In April of 1992, Intel i~trodu~d t~e
8-Mbit FlashFile component whose archItecture IS optimized for data file storage. Its symmetrically blocked
architecture and automated 'write/erase features gave
programming flexibility for a high-performance, soli~­
state memory system. The compactness of an 8-Mblt
device in a TSOP package allows for high-density flash
arrays to be included on a system motherboard as well

3-7.18

BOOT BLOCK FLASH

1
1
1
·1

Memory
Card 1

SOLID
STATE ,.
•••••••
MASS
STORAGE

I liB
4 liB

~

,. • • • • • • • •

UPDATABLE CODE . . . . .
STORAGE

II

1989

1991

1990

1993
297137-2

Figure 2
as in memory cards. Intel also offers a second generation of flash memory cards designed to serve the portable mass storage market that are based on the new
8-Mbit FlashFile component. Memory cards add the
feature of removability and system upgradability in an
industry-standard PCMCIA/ExCATM format. While
flash cards and FlashFile components serve solid-state
mass storage applications directly, both can be used in
updatable code storage applications as well.
By developing product's to fit both of these application
segments, Intel strives to serve the needs of a broader
base of customer applications with the best nonvolatile
memory solutions.

BOOT BLOCK UPDATE
The 28FOOIBX I-Mbit Boot Block flash component introduced in June 1991 featured a sectored architecture
that has been widely accepted in embedded code storage applications, particularly PC BIOS and cellular
communications. Over 20 PC manufacturers use this
device in their products, including Compaq, Dell and
Zenith Data Systems. The Boot Block architecture gave
the manufacturer added flexibility and the ability to
differentiate. End users also benefit from the ability to
upgrade BIOS software quickly and securely. It is possible for the manufacturer to upload BIOS updates to
an electronic bulletin board where the end-user gets the

upgrade for the price of the call. The blocked architecture allows the OEM customer to store critical system
code securely in the boot block of the device that can
minimally bring up the system and download to other
locations of the device to initialize the system. The
hardware boot locking feature guarantees that even if
the power is disrupted during a BIOS update, the system will be able to recover immediately.
The success of the I-Mbit Boot Block device has resulted in over 150 designs with annual shipments to exceed
1.5 million units worldwide in 1992.

EXTENDING THE BOOT BLOCK
PRODUCT LINE: 2- AND 4-MEGABIT
.
FLASH DEVICES
Once the Boot Block architecture became established in
the marketplace, customers quickly began to ask for
more features and enhanceni.ents:speed,density, low
power, surface-mount options and an industry-standard
upgrade path. These requests were based on the need to
expand features in portable computing and communication products.
The 2-Mbit 28F200BX and 4.Mbit 28F400BX are Intel's newest additions to the flash Boot Block product
line. These products offer 60 ns performance, two surface-mount packages, and a Boot Block architecture

3-719

BOOT BLOCK FLASH

similar to the I-Mbit Boot Block device: one lockable
Boot Block, two parameter blocks, and the balance of
the device is divided into main blocks. the Boot Block
securely stores the basic boot code required to initia1ize
the system that caiI be pro\ecied by the hardware-locking feature, ensuring basic system operating code protection. The two parameter blocks· can. be used for a
variety of purposes: manufacturing product code, setup
parameters and storing frequently updated data such as
system diagnostics. The 28F200BX contains one
16 Kbyte Boot Block, two 8 Kbyte parameter blocks,
one 96 Kbyte and one 128 Kbyte main block (Figure
3a). The 28F400BX contains all of the blocks of the
28F200BX plus two additional 128 Kbyte main. blocks
(Figure 3b). Top and bottom Boot Block versions are
available for both densities. Both devices are in the
x16/x8 user-selectable organization of the Industrystandard, ROM-compatible pin-out in 44-lead PSOP
surface mount package. This pinout and package allow
an easy upgrade from 2-Mbit to 4-Mbit since only one
address is added at the top of the device package. Forty-lead TSOP x8-only versions are also available for
both of these devices, providing high density in the
smallest form factor. A 56-lead TSOP. xl6/x8 version
will be available for applications -requiring x16 organization in a TSOP package.

APPLICATION REQUIREMENTg....;.PCs
Notebook computer manufacturers today are competing to produce the lightest weight, slimmest an~ longest
battery life- products possible. Minimizing board size
via reduced chip count is the flISt improvement the new
flash devices provide. BIOS in portable systems has
grown beyond the I-Mbit density to accommodate
more sophisticated power management and additional
system features, such asPCMCIA card slots.. For example, the i386TM SL architecture allows the expansion
of BIOS beyond 128 Kbytes (I-Mbit) with internal registers for hardware paging. A new generation of BIOS
support for low-power portable computers has been developed by SystemSoft and other. vendors which supports the 28F200BX and the 28F400BX. In PC BIOS
applications, the main blocks of the Boot Block devices
are used for power management code, video drivers,
and ROM-executable code, such as MS-DOS·. The arrangement of the blockS for PC BIOS applications
based on Intel i386 and i486TM microprocessors is with
the Boot Block on top. Other microprocessors and microcontrollers, such as the Intel· 80960KXlSX and the
Motorola 68000 series, use the bottom Boot Block version of the memory map. Many PC manufacturers have
also moved to a x16 organization of their BIOS for

1FFFFH

3FFFFH
16 Kbyte BOOT BLOCK _

1EOOOH
1DFFFH

16 Kbyte BOOT BLOCK
3EOOOH
3DFFFH

8 Kbyte PARAMETER BLOCK

1DOOOH
1CFFFH

3DOOOH
3CFFFH

8 Kbyte PARAMETER BLOCK

·lCOOOH
1BFFFH

3COOOH
3BFFFH

96 Kbyte MAIN BLOCK

8 Kbyte PARAMETER BLOCK
8 Kbyte PARAMETER BLOCK

96 Kbyte MAIN BLOCK

10000H
OFFFFH

30000H
2FFFFH

"

128 Kbyte MAIN BLOCK

128 Kbyte MAIN BLOCK
20000H
1FFFFH

·OOOOOH

Figure 3a. 28F200BX·Top Boot
128 Kbyte MAIN BLOCK

,
10000H
OFFFFH
128 Kbyte MAIN BLOCK

OOOOOH

FIgure 3b. 28F400BX·Top Boot
3-720

Intel·

BOOT BLOCK FLASH

higher performance and are using 2-Mbit flash components in parallel to accomplish x16 performance. Other
manufacturers have decided to forego x16 and use the
I-Mbit Boot Block and a I-Mbit bulk-erase 28FOI0
flash memory to contain their power management code.
The 28F200BX solves both of these problems in a compact, single-chip solution. The 28F400BX provides a
higher density solution for high performance systems
today, as well as a future upgrade for systems currently
requiring only 2 megabits.

APPLICATION REQUIREMENTSTELECOMMUNICATIONS/EMBEDDED
Similar to personal computers, cellular telephone applications use the hardware-lockable block to store basic
initialization code to wake up the system and establish
basic· communication with the host base station. The
small parameter blocks are ideal for frequently updated
code such as the user's phone directory, re-dial and the
activation code necessary to enable user-desired features. The main block contains the code for dynamically managing the cellular communications and executing
the voice algorithms. The density requirement for the
main code storage has increased significantly in recent
years with the conversion to digital cellular transmission, particularly in Europe and Japan. Most cellular
designs execute code directly from ROM rather than
downloading· to RAM. Typical microcontrollers used
are: Intel 80C186, Zilog Z8080 and Siemens 80166, all
operating in the 8 MHz-13 MHz range. The Motorola
68000 senes 16-bit microcontrollers used in some digital cellular designs utilize the x16 and high speed capabilities of these new Boot Block devices. Flash access
times ranging from 75 ns to 120 ns produce 0 to 1 waitstate performance. The high-performance 60 ns access
time of the 2-Mbit and 4-Mbit Boot Block flash allows
zero wait state performance in cellular telephones and
other embedded control applications.
Low power has always been a strength of flash due to
its inherent nonvolatility, a characteristic that eliminates battery drain required to maintain information
stored in volatile RAM wheri the power is off. When
flash is 'in use, its active power requirement is very low:
typical IcC = 35 mA, and standby current is 0.1 mAo
The hallmark of this newest generation of flash is low
power and high performance. Formerly these features
were mutually exclusive, but through advanced circuit
development, an automated power saving feature in the
device reduces IcC to II low DC level within one access
time; 5 mA typical. This significant reduction of the
active current time relates directly to the extension of

battery life in systems which continuously execute code
directly from flash, such as cellular telephones and portable instrumentation.
For optimum system power conservation, future systems are being designed today to operate at 3.3V rather
than 5V. Intel will a.lso offer 3.3V versions of the
2-Mbit and 4-Mbit ~oot Block devices with Icc active
= 10 mA, and tACC performance = 150 ns.
An alternative design a.pproach of a "5V-only" (programming voltage = operating voltage = 5V) flash
memory has been proposed to eliminate the need for a
12V programming supply. While this proposal would
eliminate the need for a. 12V supply component in a 5Vonly environment, it would not provide a low power
solution as every fla,sh component would carry the die
size cost and power Qverhe~d of on-chip voltage pump- .
ing. Intel's approach is to first bring the operating voltage to 3.3V, in line with what system designers requested as their first prioqty for the next generation of portable computers and cellu\a.r phones. The focus of lowering the read voltage is also congruent with the usage
model for embedded !lPplications of "read often, write
few" operation. The 12V programming voltage requirement is more efficiently met with a voltage pump from
a vendor such· as Ma.xim. (Inexpensive voltage pumps
for 3.3V to 12V are currently available.) The use of a
separate voltage pump is significantly more cost-efficient in systems wh~re more than one flash device is
used, as cost and sp"ce is amortized over multiple devices.

CONCLUSION
Intel continues to serve both updatable non-volatile
memory applications !Is well as the rapidly emerging
solid-state mass stora,ge market with solutions tailored
to meet their particula.r needs .. The new 2-Mbit and
4-Mbit Boot Block devices offer high performance and
low power options for updatable code applications. The
Boot Block architectll,e is compatible with. all major
microprocessors and microcontrollers. As with all Intel
flash products, their low power consumption and small
suiface mount packaging make the 2-Mbit and 4-Mbit
Boot Block flash me!Uories ideal for a wide variety of
handheld portable applications.

NOTE:
FlashFile, ExCA, i38.6 !lnd i486 SL are trademarks of
Intel Corporation.
.,
• MS-DOS is a registered trademark of Microsoft Corporation.

3-121

November 1992

. Intel FlashFile™ Memory
The Key to Diskless
Mobile pes

JANET WOODWORTH
MEMORY COMPONENTS DIVISION

Order Number: 297115-001
3-722

in1:el~

INTEL FlashFileTM MEMORY

INTRODUCTION

ENTER FLASH MEMORY

As the PC evolves into what is truly a "personal" computer-one that can be held in your hand.:..-a completely different system memory architecture will emerge.
Step aside ROM, DRAM, floppy disk, and hard disk;
Intel's FlashFile™ memory is here. FlashFile memory
will finally make it possible to build a thin, 2-pound
notebook computer that runs for many hours on a few
AA batteries. But before these mobile PCs are built,
designers must learn some new ways to configure system memory.

Because Intel's ETOXTM III flash memory cell is
30-percent smaller than equivalent DRAM cells, the
company expects it to track DRAM density closely.
Intel's new 28F008SA FlashFile Memory' can store
8 megabits, or one megabyte, of data today. Flash
memory is more scalable than DRAM due to its simple
cell structure, so as DRAM technology shrinks towards
0.25 microns and 64 megabits, flash will pace and ultimately overtake DRAM's technology treadmill. In
fact, expect to see 256-Mbit flash memory by the end of
the '90s.

In April 1992, Intel introduced a new flash memory
architecture with a combination of functionality and
price that redefines mobile computing. This new architecture, when implemented in new system memory configurations, enables nonvolatile executable system
memory and removable file and program' storage.
Intel's new flash architecture lets designers create a
portfolio of products that will clearly differentiate them
from their competition.

WHY A NEW MEMORY
ARCHITECTURE?
The ideal memory system is:
• Dense (stores lots of code and. data in a small
amount of space and weighs very little)
•
•
•
•

Fast (lets you read and write data quickly)
Inexpensive (low cost per megabyte)
Nonvolatile (data remains when power is removed)
Power Conscious (prolongs battery life and reduces
heat)
• Reliable (retains data when exposed to extreme temperature and mechanical shock)
Since PCs were introduced over 10 years ago, designers
have grappled with how to construct memory systems
that offer all these attributes. They have wisely elected
to use to optimum combination of solid~state memory
and magnetic storage, i.e., DRAMs plus magnetic hard
disks. DRAMs are dense and inexpensive, yet slower
than the processors they serve, and they are volatile.
SRAMs are used in caching schemes to compensate for'
DRAM's slowness. While SRAMs keep pace with today's high-performance microprocessors, they are not
as dense as DRAM, are inherently more expensive, and
volatile. Magnetic hard disks are very dense,. inexpensive on acost-per-megabyte basis, and nonvolatile, but
they are painfully slow, power hungry and subject to
damage from physical shock.

FLASH MEMORY IS FAST
Don't be misled by technology-to-technology' speed
comparisons. Designing your system memory around
flash will break the code/data bottleneck created by
connecting a mechanical memory such as disks to a
high-performance electronic. system. For instance, data
seek time for a 1.8" magnetic hard disk is 20 ms, plus
an 8 ms average rotational delay, while flash is less than
0.1 ms. At the chip level, current read speeds for flash
.are about 90 ns. Thus, downloading from flash to systl!m RAM or directly executing from flash will dramatically enhance system speed.

FLASH MEMORY IS INEXPENSIVE
At the 8-Mbit density, Intel flash pricing matches
DRAM and Intel expects to continue decreasing price
as both densities and volumes increase.

FLASH IS NONVOLATILE
Unlike SRAM or pseudo-SRAM (SRAM with built-in
battery), flash needs no battery backup. Further, Intel's
flash devices retain data typically for over 100 years,
well beyond the useful lifetime of even the most advanced computer.

FLASH IS POWER CONSCIOUS
FlashFile Memory in a hard-disk drive configuration
consumes less than one two-hundredth the average
power of a comparable magnetic disk drive based on
the typical user model. At the chip level, the 28F008SA
has a DEEP POWERDOWN mode that reduces power
consumption to less than 0.2 ,..,A.

FLASH IS RUGGED AND RELIABLE
On average, today's hard-disk drives can withstand up
to 10 Os of operating shock; Intel FlashFile memory
can withstand as much as 1000 Os. FlashFile compo3-723

infel·

INTEL FlashFlleTr.t MEMORY

nents can operate at up to 70"C while magnetic drives
are limited to SSOC. Intel FlashFile memory can be cycled 100,000 times .per block or segment. By employing
wear-leveling techniques, a 20-Mbyte flash array can
provide over 30 million hours before failure.

Flash-based solid-state disks, intended to replace magnetic hard disks in certain applications, with IDE interfaces will be "plug compatible" with existing systems
that are already designed with IDE magnetic drives in
mind.

WHY NOW?

3. Flash File System

Flash memory is not a new technology. Intel has been
the flash technology and market leader since 1988.
Then why hasn't flash taken the mobile PC market by
storm yet? Why now?

Intel has worked very closely with Microsoft· to implement a DOS flash memory extension called Flash File
System (FFS) that transparently handles swapping of
data between flash blocks, much as DOS now handles
swaps between disk sectors. With Flash File System,
the user inputs a DOS comand and doesn't need to
think about whether a magnetic disk or a flash memory
is being used. Flash File System employs wear leveling
algorithms that prevent any block from being cycled
excessively, thus ensuring millions of hours of use
across multiple chips.

One reason that 1992 is the pivotal yearfor flash-based
systems is the sharply increased demand for highly mobile computers. The other reason is that a number of
key capabilities, in development for· some time, reached
maturity together.

1. Intel Introduces FlashFlle™
Memory

4. Off-the-Shelf Hardware Interface

MS-DOS·, the ubiquitous operating system for PCS,
was developed specifically to optimize the sectoring
scheme inherent to disk technology. Intel's first generation "bulk-erase" flash required that all of the chip be
erased before data could be re-written: a natural fit for
updatable firmware and data acquisition, but not for
data file storage or disk emulation. Intel F1ashFile
memory, based on a block-erase architecture, divides
the flash memory space into segments that are somewhat analogous to the zones recognized by MS-DOS.
For instance, the Intel 28F008SA contains sixteen identical, individually-erasable, 64-Kbyte blocks. This organization has been carefully optimized to maximize cycling capability while preserving the smallest granularity possible. The ability to segment block memory into
individual segments allows disk-like data-file storage.

2. Standardization of Delivery System
and Interface
. Thanks to work by the Personal Computer Memory
Card International Association (PCMCIA), and the
Japanese Electronics Industry Development Association (JEIDA), there is now· an internationallyrecognizedstandard for memory cards. PCMCIA cards are
the size of a business card but about four times as thick.
Intel is widely promUlgating its Exchangeable Card Architecture (ExCATM), a hardware and software implementation of the PCMCIA system interface. When
used with the proper BIOS, ExCA/PCMCIA-compatible cards will be completely interchangeable between
systems and vendors, and can be equated to solid-state
floppy disks, albeit with many advantages.

The introduction of the Intel 8236SSLTM PC Card Interface Controller provides a ready-made interface between the PC's ISA bus and up to two PCMCIA sockets. It is a key component for memory and 110 card
implementations since the designer is relieved from
building the interface from scratch.

5. Cost Reductions
Magnetic drives do not scale well; that is, it becomeS
increasingly difficult to improve or even retain density
as platter size shrinks. Thus, every reduction in drive
size requires complete retooling and costly learning.
Also, the complex controller circuitry provides a price
floor under which magnetic drives cannot drop. Since
flash i~ scalable, at some point in the near future, small
magnetic drives are likely to become more expensive
per megabyte than flash cards and are certain to have
less capacity. But even today, the value of a particular
memory technology is a result of more than just dollars
per megabyte .

3-724

Notes market analysis expert Dataquest:
"The question is, "Can you put a floppy disk drive
in a palmtop PC to take advantage of the cost disparity (between disk and flash)?" The answer is,
'No.' There is not enough power (or space). The
issue then, is not cost. Here, the removable storage
medium dictates· the product's capabilities and its
success or failure in the marketplace.· Without a
memory card, a palmtop is nothing more than an
electronic organizer. It is the memory card that
transforms a palmtop into a full-fledged personal
computer." ... Nick Samaras, SAMS Newsletter.

INTEL FlashFlle"T:M MEMORY

All of the aforementioned features, Intel FlashFile
memory's block-erase architecture, PCMCIA standards, ExCA, Flash File System, 82365SLISAPCMCIA interface controller and reduced costs, are
deliverables ... now. And not a moment too soon
based on the tremendous market opportunity created
by the increasing demand for truly mobile computers.
Dataquest predicts that the worldwide sale of portable
PCS will increase from six million units in 1992 to nearly 30 million units in 1995. While laptop PCs are only
expected to increase by about two million units,. notebooks; pen-based, and handheld PCS will increase from
three million units in 1992 to nearly 25 million in 1995,
an eight-fold increase. This extraordinary growth will
be greatly assisted by FlashFile memory.

ENABLING THE TRULY MOBILE
COMPUTER
In the world of the desktop PC, DRAM is used for
executable code storage and data manipulation. Since
DRAM is volatile, if power is lost, both programs and
data are lost, hence the,need for a nonvolatile magnetic
hard disk. With the addition of the hard disk, programs
and data are stored on the hard disk and swapped in
and out of DRAM as needed. Some part of the DRAM
is reserved for use as a register to store temporary results during compute-intensive operations. Today's PCS '
are typically configured With 4 megabytes of DRAM
, and at least a 4O-Mbyte disk. .
FlashFile memory fully supports this system configurat!-on when used simply as a magnetic drive replacement.
Instructions and data are still swapped to DRAM ·but
at a much faster rate. Plus, executiOn speed can be enhanced if the DRAM is replaced with SRAM.
In the solid-state computer, the "DRAM + magnetic
hard drive" are replaced by a "flash memory +
SRAM". The key to this architecture is the ability to
eXecute-InP1ace (XIP); Program instructions stored in
the flash memory are read directly by the processor.
Results are written directly to the flash memory. Compute-intensive operations that require the fastest memory and byte-alterability use high-speed sRAM or pseudo SRAM. Most of what we now think of as the
"DRAM" is replaced by low-cost flaSh and only a relatively small part of the DRAM is replaced by SRAM.

'The flash memory sp'ace is made even more storage-efficient through the lise of compression techniques
which offer at least 2:1 compression. ·For example, one
20-Mbyte flash card that uses 2:1 compression offers
the same storage asa 4O-Mbyte hard disk!
The advantages of a flash-based computer include:
•
•
•
•
•

Blazingly fast speed
Instant-on and instant-resume
Ultra-light PC (2-4 Ibs.)
Very secure data retention
Flexible firmware

As you can see, by changing the system memory architecture to a flash-based one, designers will be able to
build a new generation of PCs that roeets the needs of
the computer user of both today and tomorrow..
Progress has been made'toward implementing this approach with the introduction of Hewlett-Packard's successful HP95LX DOS-compatible palmtop. MS-DOS
and Lotus 1-2-3- are stored in ROM. Internally, pseudo~static RAM is used, and a PCMCIA memory socket
is provided. Lotus 1-2-3 was re-written to allow ROMbased storage so it could execute in place. Other ROM"
executable versions of popular operating systems are
expected to be available shortly.

DESIGNING YOUR SYSTEM WITH
FLASHFILE MEMORY
Details of the three Intel flash applications and implementations-flash cards, silicon disks, and Resident
Flash Array (RFA)-are presented below.

APPLICATION NUMBER 1: MEMORY
CARDS
Memory cards are the most rugged and reliable of the
removable memory media. A card can be slipped into a
shirt pocket and moved from location to location. With
high-density flash cards, you can download files from
the desktop and use the card in your notebook or palmtop.

3-725

INTEL FlashFlleTP,'I. MEMORY

Memory cards have b~. around for :some time. The
first cards to be introduced were ROM-only cards used
in video games and pocket organizers. These were produced in various formats· prior· to the formation of
PCMCIA and JEIDA .. Later. cards included batterfbacked SRAM and EEPROM. NeitheJ;'became very
popular due to their. high cost of $500-$600 per megabyte and limited capacity. F1ash.clird~ overcome the
cost barrier and they are certain to be multiply sourced,
assuring aYaiiability and· Competitive pricing. A
2();Mbyte flash card has three times the real storage
density of a 20-Mbyte I.S" magnetic drive
(0.95 Mbyte/cm3 vs 0.34 Mbyte/cm3) and it has 10
times the weight density (2 Mbyte/gm vs 0.21 Mbytel
gm), The PCMCIA has complete industry support, and
enhanced versions, such as PCMCIA Version 2.0, are
designed to be backward-compatible with earlier versions.
As part of its flash product family, Intel's new Series 2
memory cards are the first to utilize chips processed on
its O.S-micron flash teChnology,Storing up to 20 megabytes, these cards are designated Series 2 to differentiate them from the earlier bulk-erase flashcards. The
cards consist of 4 to 20, 2SFOOSSA TSOP' F1ashFile
memory devices. Each 2SFOO8SA contains 16 distinct,
individually-erasable, 64-Kbyte bloCks. Therefore, each
card Contains from 64 to 320 blocks.
With the release ofPCMCIA Version 2.0 in September
of 1991, the PCMCIA-compatible field grew somewhat
larger. The PCMCIA interface grew from memoryonly to one that supports many types of I/O devices.
Intel's system-level implementation of PCMCIA 2.0,
called ExCA, ensures that if there are two ExCA sockets available, one can be used for a flash ,memory card
and one for a modem; and the cards may be interchanged.
How difficult is it to design-in an ExcA socket? Not
very. Intel's open ExCA specification details the system
implementation. Other than the. physical incorporation
of the socket and card, the only required hardware is an
ISA-to-PCMCIAinterface such as Intel's 82365SL
chip, and 'an ExCA compliant B.OS from vendors like

SystemSoft, Award and Phoenix. You'll also need a
flash file management system like Microsoft's Flash
File System. Intel's block-erase architecture, along with
the DOS Filing System and ExCA BIOS, makes it easy
to incorporate ExCA features. In addition, ExCA-compliant systems will allow system-to-system interoperability much like floppy disks.,

APPLICATION NUMBER 2:
FLASH-BASED S()LlD STATE DISK
The implementation of block-erase flash as. a "solidstate disk" (SSD) is ·something of a misnomer. It is not
a diSk at all,' rather a flash module that has the same
form, fit and function asa 2.5" or smaller magnetic
drive.
-

.

A flash-based SSDimplementation is the most direct
route-to adapting flash to an existing design. A built-in
IDE interface would make it plug-compatible. But
what a difference a silicon disk will make! A 1.8" drive
typically uses one watt-hourlhour while a silicon diSk
uses as little as 0.035 watt-hourlhour. Thi~ kind of
power savings makes it possible to reduce battery size
and weight considerably. Or, consider reliability. We've
already discussed differences in susceptibility to shock
and temperature extremes. In addition, an SSD theoretically has. a mean-time-between-failure (MBTF) of
250,000 hours, C9mpared to 100,000 hours for the magnetic drive.
With all these advantages, when should you .use memory cards and when is use of a flash-based SSD prefer. .
able?
First and foremost, the SSD is considered to be installable while memory cards are removable and transportable. In other words, the SSD is meant to be installed
and then left alone, while memory cards are designed
for constant removal and reinsertion. In operation, the
only change a user would notice in a notebook computer equipped with a flash-based SSD is. that access speed
is unprecedented. .

3-726

infel·

INTEL FlashFllelM MEMORY

The flash-based solid-state drive is one very good way
to get to market early with flash technology. In February 1992, Conner Peripherals, Inc., and Intel announced the signing of a joint product and technology
development contract focused on designing and bringing to market proprietary FlashFile memory-based
SSD storage products.
/
Incidentally, manufacturers of magnetic drives are
starting to take notice. In a manner much like the tail
wagging the dog,' 1.8" magnetic hard disks with
PCMCIA interl'aces ~e currently being developed.

APPLICATION NUMBER 3:
RESIDEJIIT FLASH A~RAY
The one approach that offers totally new capabilities is
the Resident Flash Array (RFA). This is an arrangement of from 8 to 20, 8-Mbit FlashFile memories. In
the long term, it replaces some of the motherboard's
DRAM; This is the approach'that is applicable to all
levels of ,PC, from desktop to palmtop. For near-term
, applications, however, RFA is an ideal way of making
code or ROM-executable operating systems such as
DOS or Windows· updatable to protect the end-user's
'software investment. Also, when used as a resident ap-

plication program and data-file storage medium on the
local memory bus, RFA provides a high-perl'ormance,
low-power solution.
The Resident Flash Array provides the highest possible
perl'ormance of any option, especially since the processor can be closely coupled to ~t; and hence, would not
be encumbered by IDE or PCMCIA interl'aces, or even
the ISA bus itself. The flash memory and the processor
will sit side-by-side.
The proliferation of flash memory card-based systems
will accelerate the process of converting disk-oriented
applications to a flash-executable orientation. Those
manufacturers who elect to be early adopters of Intel
FlashFile memory'will be able to develop a new generation of PC--the truly "personal" computer you can
hold in your hand.
NOTE:
ETOX, ExCA and FlashFile are trademarks of Intel
COrporation.
"Microsoft and MS-DOS are registered trademarks;
Windows is a trademark of Microsoft COrporation.
·Lotus and 1-2-3 are registered trademarks of Lotus
Development Corporation.

3-727

intel·

SOP PHYSICAL DIMENSIONS

1.0 SOP Case Outlines for Intel's 32-, 40-, 56-Lead TSOP and 44-Lead PSCP
Packages
.
.

.

; .32-Lead Thin Small Outline Package (TSOP)

o

o
~------------D----------~----~

~--------~--~----Hd---------------~
A

J
~
~T--j~--------~----~~

SEE DETAIL A

DETAIL A

297186-1

Symbol

,

Package Height
Standoff
Package Body Thickness
Lead Width
Lead Thickness
Package Body Length
Package Body Width
Pitch
Terminal Dimension
Lead Tip Angle
Lead Tip Length
Lead Count
NOTES:
Gull Wing Length
Seating Plane Coplanarity
Lead to Package Offset

Min
A
A1
A2
B
C
D

E

0.050
0.96
0.150
0.10
18.35
7.95

Hd

Max
1.20

Min

1.01
0.200
0.15
18.40
8.00
0.50
20.00
3°
0.330
32

1.06
0.250
0.20
18.45
8.05

0.0019
0.0378
0.0059
0.0039
0.7224
0.3130

20.10
5°
0.350

0.7835
1°
0.0118

0.600

0.800

0.20

·0.25

0.950
0.100
0.30

e

L

Millimeters
Typ

19.90
1°
0.300

N

Inches
Typ

Max
0.0472

0.0398
0.0079
0.0059
0.7244
0.3150
0.Q196
0.7874
3°
0.0130
32

0.0417
0.0098
0.0079
0.7264
0.3169

0.0236

0.0314

0.0079

0.0098

0.0374
0.0039
0.0118

0.7913
5°
0.0138

Figure 1-1. 32-Lead TSOP Package Drawing and Specifications
3-728

Order Number: 297186-001

infel .

SOP PHYSICAL DIMENSIONS

40·l;,ead Thin Small Outline Package (TSOP)

o

11
E

SEE DETAIL B

o
~------------D----------------~

~------------------Hd----------------~
SEE DETAIL A

297186-2

Millimeters

Symbol

Min

Typ

Inches
Max

Min

Typ

Max
0.0472

Package Height

A

1.20

Standoff

A1

0.050

Package Body Thickness

A2

0.965

0.995

1.025

0.0379

0.0391

0.0403

Lead Width

B

0.150

0.20

0.250

0.0059

0.0078

0.0096

Lead Thickness

C

0.120

0.127

0.134

0.0046

0.0049

0.0052

Package Body Length

D

18.20

18.40

18.60

0.7165

0.7244

0.7322

Package .Body Width

E

9.80·

10.00

10.20

0.3858

0.3937

0.4015

Pitch

e

Terminal Dimension

Hd

19.80

·20.00

20.20

0.779S

0.7874

0.7952

Lead Tip Angle



1°

3°

So

1°

3°

So

Lead Tip Length

L

0.300

0.330

0.3S0

0.0118

0.0130

0.0137

Lead Count

N

0.019

0.50

0.0196

40

40

NOTES:
Gull Wing Length

·0.600

0.800

Seating Plane Coplanarity
Lead to Package Offset

0.9S0

0.0236

0.0314

0.100
0.20

0.2S

0.30

0.0079

0.0098

.'

Figure 1·2. 40·Lead TSOP Physical Dimensions and Specifications
3-729

0.0374
0.0039
0.0118

SOP PHYSICAL DIMENSIONS

56-Lead Thin.Small Outline Package (TSOP)
#1

U

#56

o

o

SEE DETAIL B

o
'29

~--------------_Hd------------~
A ~,...._ _ _ _ _ _ _ _ _ _ _ _~~. SEE. DETAIL A

~j----~------~~ .
DETAIL B

DETAIL A

~lC~

L-+4#

297186-3

Inches

Millimeters

Symbol
Min

Typ

Max

Min

Typ

1.20

···Mlix

Package Height

A

Standoff

A1

0.050

0.0472

Package Body Thickness

A2

0.965

0.995

1.025

0.0379

0.0391

0.0403

Lead Width

B

0.100

0.150

0.200

0.0039

0.0059

0:0079

Lead Thickness

C

0.120

0.127

0.134

0.0047

0.0049

0.0053

Package Body Length

D

18.20

18.40

18.60

0.7165

0.7244

0.7322

Package Body Width

E

13.80

14.00

14.20

0.5433

0.5511

0.5590

Pitch

e

Terminal Dimension

Hd

19.80

20.00

20.20

0.7795

0.7874

Lead Tip Angle



1°

3°

5°

1°

3°

5~

Lead Tip Length

L

0.300

0.330

0.350

0.0118

0.0130

0.0137

Lead Count

N

0.0019

0.0196

0.50

56

0.7952
.

56

NOTES:
Gull Wing Length

0.600

0.800·

Seating Plane Coplanarity
Lead to Package Offset

0.950

0.0236

0.0314

0.0079

0.0098

0.20

0.25

0.30

Figure 1-3. 56-Lead TSOP Package Drawings and Specifications

3-730

0.0374
0.0039

0.100

0.0118

intel~

SOP PHYSICAL DIMENSIONS

44·Lead Plastic Small Outline Package (PSOP)
23

297166-4

MIllimeters

Symbol
Min
Package Height

Typ

A

Inches
Max

Min

Typ

Max
0.103

2.62

Standoff

A1

0.13

0.225

0.35

0.005

0.009

0.013

Package Body Thickness

A2

2.17

2.30

2.45

0.085

0.091

0.097

Lead Width

B

0.35

0.40

0.50

0.014

0.016

0.020

Lead Thickness

C

0.13

0.150

0.20

0.005

0:006

0.008

Package Body Length

D

Package Body Width

E

Pitch

e

Terminal Dimension

He

Lead Tip Angle



Lead Tip Length

L1

Lead Count

N

28.20

28.70

1.100

1.130

13.10

13.30

13.50

0.516

0.524

0.531

15.70

16.00

16.30

0.618

0.630

0.642

0.029

0.032

0.033

1.27

0.050

8'

8'
0.75

0.80

0.85

44

44

NOTES:
Gull Wing Length

1.30

1.35

Seating Plane Coplanarity

1.40

0.051

0.053

0.10

Figure 1·4. 44·Lead PSOP Physical Dimensions and Specifications

3-731

0.055
0.004

int:et

SOP PHYSICAL DIMENSIONS

2.0 SOP Board Footprints
A typical land pad diagram for the 32-Lead TSOP package is shown in

Figur~

2-1.

""'I'---------20.8(819)--------.jtl

f ii
~

:

~~~

c:J"7T ~
c:J I.:=.
c:J
c:J
c:J
c:J
0

c:J
c:J
c:J
c:J
c:J
c:J

L
?
.:=.

c:J-1~

c:J-r'::'

.~

~
1.40 (55) -l

Dimensions in mm (mil)
Scal.:
= 1 mm

"H

;

I297186-5,

Figure 2-1. Typical TSOP Land Pad Diagram

Similar land pad diagrams can be constructed for the 4O-lead and 56-lead TSOP packages. The 4O-lead land pad
diagram can be constructed by adding four leads to both sides of the 32-lead land pad diagram, while maintaining
the spacing between the lead footprints. The total footprint width becomes 9.8Omm instead of 7.8Omm used with the
32-lead package. With the 56-lead package, 12 leads are added to both sides of the 32-lead land pad diagram, while
maintaining the spacing between the lead footprints. The total footprint width becomes 13.80mm instead of the
7.80mm used with the 32-lead package.

3-732

infel .

SOP PHYSICAL DIMENSIONS

A typical land pad diagram for the 44-Lead PSOP is shown in Figure 2-2.

I'

t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J

'"....Co
....

'I

16.9 (665)

"

...<;

~

t:::J
t:::J

~-.l;
t:::Jt
t:::J
t:::J
t:::J
t:::J
t:::J
t::I

E

-.l ~

t:::Jt~

~

t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J
t:::J

H

Sealo:
=1 mm
Dimonsions in mm (mil.)

1.7(66)

-I

~
297186-6

Figure 2-2. Typical PSOP Land Pad Diagram

3.0 SOP Component Volume and Weight
Table 3-1 shows the component volume and weight of the SOP package family.

Table 3-1. SOP Component Weight and Volume
Package

Max Height

Max Volume

Average Weight

32-Lead TSOP

1.20mm

194.2mm3

O.37gms

40-Lead TSOP

1.20mm

247.2mm3

O.47gms

56-Lead TSOP

1.20mm

344.2mm3

O.65gms

2.62mm

1.225.7 mm3

186gms

44-Lead TSOP

3-733

infel·

PRODUCT BRIEF

Intel Blocked Flash Memory 28F001 BX-B/28F001BX-T
Intel's 28FOOlDX·B and 28FOOIBX·T combine
the cost·effectiveness of Intel standard flash
memory with features that simplify write and
allow block erase. These devices aid the system
designer by combining the functions of several
components into one, making blocked flash
memory an innovative alternative to EPROM
and EEPROM or battery·backed static RAM.
Many new and existing designs can take
advantage of the 28FOOIBX's integration of
blocked architecture, automated electrical
reprogramming and standard processor interface.

Product Highlights
• High·Integration Blocked Architecture
- One 8 Kb Boot Block w/Lock Out
- Two 4 Kb Parameter Blocks
- One 112 Kb Main Block
- Min 10,000 Cycles/Block

296913-1

Intel 28F001BX Flash Memories

• Simplified Program and Erase
- Automated Algorithms Via On·Chip Write State
Machine
• Deep·Powerdown Mode
- 0.05 ,..,A Icc Typical
- .0.8 ,..,A Ipp Typical
• High·Performance Read
- 120 ns Maximum Access Time
• .Hardware Data Protection Feature
- EraseIWrite Lockout During Power Transitions
• Advanced Packaging,JEDEC Pinouts
- 32·Pin PDIP
- 32·Lead PLCC, TSOP
o Extended Temperature Option
- -40°C to +85°C

1FFFF

1FFFF

8KByte
BOOT BLOCK

1EOOO
1DFFF

112 KByte
MAIN BLOCK

10000
1CFFF

1COOO

4 KByte
PARAMETER BLOCK
4 KByte
PARAMETER BLOCK

1BFFF

04000
03FFF
03000
02FFF
02000
01FFF

4 KByte ,
PARAMETER BLOCK

112 KByte
MAIN BLOCK

4KByte
PARAMETER BLOCK

8 KByte
BOOT BLOCK
00000

28F001BX·B
Memory Map

,00000

28F001BX·T
Memory Map

MCS@-186 is a registered trademark of Intel Corporation.
i386™, i486TM and i860TM are trademarks of Intel Corporation.

3-734

August 1992 '
Order Number: 296913-003

int:eL

PRODUCT BRIEF
,

Product Description
The 28FOOIBX-B and 28FOOIBX-T 1 Mbit (128K x 8)
blocked flash memories augment the nonvolatility, insystem electrical erasure and reprogrammability of Intel's standard flash memory. They offer four separately
erasable blocks and integrate a state machine to control
erase and program functions. The tailored blocking architecture and automated programming of the
28FOO1BX family provide a full-function, nonvolatile
flash memory ideal for a wide range of applications,
including PC boot/BIOS memory, minimal-chip embedded program memory and parametric data storage.

.

The 28FOOIBX family combines the safety of a hardware-protected 8 Kbyte boot block with the flexibility
of three separately reprogrammable blocks, (two .4
Kbyte parameter blocks and one 112 Kbyte code block)
into one versatile, cost-effective flash memory. Additionally, reprogramming one block does not affect code
stored in another block, ensuring data integrity.
The 28FOOIBX-T's block locations provide compatibility with microprocessors and microcontrollers that
boot froni. high memory, such as Intel's i386™,
i486™, i860™, 80960CA and MCS@-186 families.
The 28FOO1BX-B memory map is tailored for bottomboot devices such as Intel's MCS-S1, MCS-196,
80960KA/KB and 80960SA/SB microcontrollers.

3-735

intel·

PRODUCT BRIEF

Intel 2-Megabit Boot Block Flash Memory
28F200BX-T IB, 28F002BX..T IB
Intel's 28F200BX-T/B, 28FuOllix.Tlii prODuct
family is a new addition to the Boot Block Flash
Memory product .line. This product family is
manufactured on Intel's third generation
ETOXTM flash process. The boot block
architecture in the 2 Megabit density is
particularly well-suited for portable PC BIOS
and updateable firmware appUcations. The
28F200BX/28F002BX family allows block
selective erasure, automated \vrlte and erase
operations and standard niicruprocessor
interface. High-performance actess·times of60ns
and 80ns provide zero-wait-state operation with a
wide range of microprocessors lfud
microcontrollers.

297139-1

Product Highlights

Product Description

• High-Integration Blocked Architecture
- One. 16 KB Boot Block w/Lock Out
- Two 8 KB Parameter :81ocks
- One 96 KB Main Block
- One 128 KB Main Block
• Hard'Xare Data Protection Feature
.• Top and Bottom Boot Versions Available
• High' Performance 60nsand ~OIiS Read Access
Times
• Vpp = 12V ± 10% (Option)
• x8 or xl6 User Configurable I/O Control
• Icc Active = 20 mA (Typical)
• Deep-Powerdown Mode (0.2 /-LA Typic~l) .
• Automatic Power Savings Feature
. • 3.3V versions
• 100,000 Write-Erase CycleslBlock
. • Write and Erase Automation
• Industry Standard Surface Mount Packages
- 4O-Ld TSOP (x8 only); - M-Ld PSOP;
- 56-Ld TSOP
• Easy upgrade path to 4 Megabits

The 28F200BX-T/B and 28F002BX-TIB Flash Memories are components of a 2 Mbit (2,097,152 bit) family
of flash memory devices, each organized as either
262,144 bytes or 131,072 words. These flash memory
devices combine the safety of a hardware-lockable 16
Kbyte boot block with the flexibility of separately reprogrammable blocks (two 8 Kbyte parameter blocks,
one 96 Kbyte main block and one 128 Kbyte main
block). The specialized blocking architecture, highspeed performance, xl6 organization, and smail surface
mount packaging provide a full-function, nonvolatile
flash memory ideal for a wide range of applications,
including PC BIOS, Telecommunications, Portable Instrumentation, Office/Factory Automation Equipment.
The 28F200BX-T and the 28FOO2BX-T (top boot) devices offer block locations that provide compatibility
with microprocessors and microcontrollers that boot
from high memory, such as Intel's i386™, i486™,
i860™, 80960CA and MCS@-186 families. The
28F200BX-B and the 28FOO2BX-B (bottom boot) devices are tailored for microprocessors and microcontrollers that boot· from low memory, such as Intel's
MCS-51, MCS-196, 80960KX and 8096QSX microcontrollers.

3-736

Order Number: 297139-001

infel..

PRODUCT BRIEF

FEATURES
. -

BENEFITS

High-Integration Blocked Architecture

-

Modular code development/updates

-

Top Boot and Bottom Boot Architecture

-

Easy interface with wide range of processors

-

xB or x16 User Configurable Bus Operation

-

Interfaces with high-end processors

-

60 ns Read Access Time

-

DRAM-like access times

-

Automated Byte-Write/Block Erase

-

Simplifies design, frees processor for higher priority tasks

-

Erase Suspend Capability

-

Enables data/code access during erase

-

Automatic Power Savings Feature

-

Saves active power without reducing performance

-

0.2 !LA Low Power Sleep Mode

-

Extends battery life

3-737

intel·

PRODUCT BRIEF

Intel 4-Megabit Boot Block Flash Memory
28F400BX-T IB, 28F004BX~T IB
Intel's 2SF400BX-TIB, 2SF004BX-TIB product
family is a new addition to the Boot Block Flash
Memory product line. Manufactured on Intel's
third generation ETOXTM flash process, the
2SF400BX/2SF004BX offers the most highly
integrated and highest performance solution for
updatable firmware. The 2SF400BX/2SF004BX
family allows block selective erasure, automated
write and erase operations and standard
microprocessor interface. High-performance
access times of 60 ns and SO ns provide zerowait-state operation with a wide range of
microprocessors and microcontrollers. In-system
update and upgrade flexibility eliminate the risk
of software obsolescence.

297140-1

Product Highlights

Product Description

• High-Integration Blocked Architecture
- One 16 KB Boot Block w/Lock Out

The 28F400BX-TIB, 28FOO4BX-TIB Flash Memory
Family is a 4 Mbit (4,194,304 bit) family offlash
memory devices, each organized as either 524,288 bytes
or 262,144 words. These flash memory devices combine
the safety ofa hardware-lockable 16 Kbyte boot block
with the flexibility of separately reprogrammable blocks
(two 8 Kbyte parameter blocks, one 96 Kbyte main
block and three 128 Kbyte main blocks). The tailored
blocking architecture, high-speed performance, x16
organization and small surface mount packaging
provide a full-function, nonvolatile flash memory ideal
for a wide range of applications, including
Telecommunications, Portable Instrumentation,
Office/Factory Automation Equipment, and High-end
PC boot/BIOS.

-

Two 8 KB Parameter Blocks

-

One 96 KB Main Block
Three 128 KB Main Blocks

• Hardware Data Protection Feature
• Top and Bottom Boot Versions Available
• High Performance 60 ns/80 ns Read Access Time
• Vpp = 12V ± 10% (Option)
• x8 or x 16 User Configurable I/O Control
• ICC A~tive = 20 mA (Typical)
• Deep-Powerdown Mode (0.2 /LA Typical)
• Automatic Power Savings Feature
• 100,000 Write-Erase Cycles/Block
• Write and Erase Automation
• Industry Standard Surface Mount Packages
- 4O-Ld TSOP (x8 only); 44-Ld PSOP;
56-Ld TSOP
• Easy upgrade path from 2 Megabit
• Extended Temperature Operation

The 28F400BX-T and the 28Fo04BX-T (top boot) .
devices offer block locations that provide compatibility
with microprocessors and microcontrollers that boot
from high memory, such as Intel's i386™, i486™,
i860™, 80960CA and MCS®-186 families. The
28F400BX-Band the 28FOO4BX-B (bottom boot)
devices are tailored for microprocessors and,
microcontrollers that boot from low memory, such as
Intel's MCS-51, MCS-196, 80960KX and 80960SX
microcontrollers.

3-738

Order Number: 297140-001

PRODUCT BRIEF

Features
-

High-Integration Blocked Architecture

-

Top Boot and Bottom Boot Architecture
x8 or x16 User Configurable Bus Operation
60 ns Read Access Time
Automated Byte-Write/Block Erase

-

Erase Suspend Capability
Automatic Power Savings Feature

-

0.2 fJ-A Low Power Sll:\ep Mode

Benefits
Modular code development/updates
Easy interface with wide range of processors
Interfaces with high-end processors
DRAM-like access times
Simplifies design, frees processor for higher priority
tasks
Enables data/code access during erase
Saves active power without reducing performance
-

3-739

Extends battery life

int:el.

PRODUCT BRIEF

Intel 2SFOOSSA (S-Megabit) FlashFile ™ Memory
intei's symmetricaiiy biocked 28F008SA is the
first flash memory optimized for solid state and
data me storage. Manufactured on Intel's third
generation ETOXTM flash process, the
28F008SA offers the most cost-effective solution
for read/write nonvolatile random access system
memory. Combined with me management
software, such as Microsoft's* Flash File
System,the 28F008SA's symmetrically blocked
architecture and extended cycling provide highperformance disk emulation capability. The
28F008SA provides new opportunities for system
differentiation. High-performance access times
of 85/90/120 ns provide instant-on performance
for resident application and operating system
software. In-system update and upgrade
flexibility eliminate the risk of software
obsolescence.
297107-1

Product Highlights

Product Description

• Symmetrically Blocked Architecture

The 28FOO8SA is a high performance 8 Mbit (8,388,608
bit) flash memory, organized as 1 Mbyte (1,048,576
bytes) of 8 bits each. The 28FOO8SA contains sixteen
64 Kbyte (65,536 byte) blocks. Each block is separately
erasable and capable of 100,000 byte write-block erase
cycles. On-chip automation dramatically simplifies
software algorithms, and frees the system
microprocessor to service higher priority tasks. An
enhanced system interface allows switching the
28FOO8SA into a deep powerdown mode during periods
of inactivity, and gives a hardware indication of the
.
status of the internal Write State Machine. High-speed
access times allow minimal wait-state interfacing to
microprocessor buses. Advanced TSOP packaging
(standard and reverse pinouts) provides optimum
density/in2.

• High Performance 85 ns Read Access Time
• 100,000 Write-Erase Cycles/Block
• 0.2 p,A Sleep Mode Typical
• Byte-Write and Block-Erase Automation
• RYIBY Status Output
• Erase Suspend Capability
• Industry Standard 4O-Ld TSOP and 44-Ld PSOP
Packaging

ExCA and ETOX are trademarks of Intel Corporation.
"Microsoft is a trademark of Microsoft Corporation.

3-740

Order Number: 297107-001

intel .

PRODUCT BRIEF

Features

Benefits

- Solid State, Symmetrically Blocked Architecture

- High-performance, reliable, disk emulation capability, allows code partitioning

- 85 ns Read Access Time

- Instant-on performance for application and operating system software

- 0.2 ,...A Low Power Sleep Mode

- Extends battery life

-100,000 Write-Erase Cycles/Block

- More reliable than disk

- Automated Byte-Write/Block-Erase

- Simplifies design, frees processor for higher priority
tasks

- Erase Suspend Capability

- Enables data/code access during erase

- RY /BY Status Output

/

- Hardware indication ofWSM, allows interrupt system notification for background erase completion

3-741

intel·

PRODUCT BRIEF

Intel Flash Memory· Evaluation Kit II (0, FLASHEVAL2)
intei's Flash Memory Evaiuation Kit II proVides
the system designer with a cost-effective .
prototyping tool for programming and erasing
Intel flash memory products. Its software .
upgrade capability enables Intel to provide
programming support for new flash memories
conincident with their introduction. The Flash
Memory Evaluation Kit's modular design
provides compatibility with future Intel flash
memory packages and form factors thru
hardware adapter upgrade modules. This kitis a
significant enhancement to the Intel Flash
Memory Evaluation Kit I, adding support for
new devices and providing new software with
easy user interface, additional capabilities and
on-line help.
Upgrade Modules Available
D, FLASHEVAL 3 - Supports Series I Memory Card
+ 1 MBSIMM
D, FLASHEVAL 4 - Supports 28FOO8SA
D, FLASHEVAL 5 - Supports 28F400BX/
28FOO4BX

296997-1

Intel Flash MemorY Evaluation Kit II

Kit Contents

Kit Description

• (1) PC·AT" IPC·XT" Add·ln Driver Board with

The Intel Flash Memory Evaluation Kit II is a PCdriven flash memory programming solution. With this
kit, a system designer can program and erase Intel's
flash memory components directly, and flash memory
cards, SIMMs and advance packaged components
using separately available hardware adapters.

DIP ZIF Connector
• (1) User's Manual
• Sample Flash Memory Devices, Including:
(1) 28F512
(I) 28F256A
(I) 28FOIO
(I) 28F020
(I) 28FOOIBX·B
(I) 28FOO1BX·T
• (1) 5.25" Floppy Disk with iFLASH2 Software

• Technical Documentation Describing Intel's Flash
Memory Products
• Registration Card

The kit's Users Guide provides software and hardware
installation instructions and an overview of software
features.
The provided iFLASH2 programming software
incorporates a graphical, mouse-driven (optional) user
interface. On-line help guides the user through the
extensive kit capabilities without need to access
instruction manuals. As new flash memories are
introduced by Intel, software upgrades will update the
installed customer base with the added code.
Technical documentation includes device datasheets,
application notes and reliability information. Together,
these documents provide a complete description of the
technology and important design considerations.

·PC-XT and PC-AT are trademarks of International Business Machines, Inc.

3-742

Order Number: 296997-()01

infel·

PRODUCT BRIEF

Intel 28F008SA (8-Megabit) FlashFile™ Memory
Evaluation Module D, FLASHEVAL4
Intel's 28F008SA FlashFile Memory Evaluation
Module provides system designers with a costeffective prototyping tool to evaluate the
functionality and benefits of Intel's 28F008SA.
This evaluation module is a hardware adapter
board upgrade to the Intel Flash Memory
Evaluation Kit II (D, FLASHEVAL2). The
module supports the 28F008SA in 40·1ead TSOP
(standard and reverse pinouts) and 44-lead
PSOP packages.

Kit Contents

Kit Description

• 28F008SA Adapter Board with:
4O·ld TSOP Socket ("E", Standard Pinout)
4O-ld TSOP Socket ("F", Reverse Pinout)
44-ld PSOP Socket

The 28FOO8SA Evaluation Module, used with Intel's
Flash Memory Evaluation Kit, provides the hardware,
software and system interface necessary to evaluate and
integrate Intel's 8 Mbit Flash Memory into your next
design.

• 28FO08SA Samples:
(1) E28F008SA
(1) F28F008SA
(1) P A28F008SA
• 5.25" Floppy Disk with iFlash2 Software
(Version 2.1)

The module provides instructions to install the
28FOO8SA adapter board. Technical documentation
includes 28FOO8SA datasheets, engineering reports and
application notes. Together, they provide a complete
description of the technology and important design
considerations.

• Technical Documentation Describing Intel's
28FO08SA FlashFile Memory
• Flash Memory Evaluation Kit II Installation Guide
and User's Manual with 28F008SA Adapter Board
Installation Instructions
• Manual Vacuum Wand
• Registration Card

*FlashFile is a trademark of Intel Corporation.
3-743

Order Number: 297117-001

intel·

PRODUCT BRIEF

Intel 28F400BXl28F004BX Flash Memory
Evaluation Module D, FLASHEVAL5
Intel's 28F400BX/,28F004BX Memory
El;aluation Module provides system designers
with a cost-effective prototyping tool for writing
and erasing this flash memory device. This
evaluation module is a hardware adapter board
upgrade to the Intel Flash Memory Evaluation
Kit II (D, FLASHEVAL2) which supports the
4 megabit flash memory in 40-lead TSOP and
44-lead PSOP packages.

297152-1

Kit Contents

Kit Description

• 28F400BX/28F004BX Adapter Board with:
4O-ld TSOP Socket
44-ld PSOP Socket

The 28F400BX/28FOO4BX Evahiation Module, used
with Intel's Flash Memory Evaluation Kit, provides
the hardware, software and system interface necessary
to evaluate and integrate Intel's 4 Mbit Flash Memory
into your next design.

• 28F400BX and 28F004BX Samples:
(1) E28FOO4BX-T (40-ld TSOP, Top boot)
(1) E28F004BX-B (40-ld TSOP, Bottom boot)
(1) PA28F400BX-T (44-ld PSOP, Top boot)
(1) PA28F400BX-B (44-ld PSOP, Bottom boot)
• 5.25" Floppy Disk with iFlash2 Software (Version
2.3)

The module provides instructions to install the
28F400BX/28FOO4BX adapter board. Technical
documentation includes 28F400BX/28FOO4BX
datasheets, engineering reports and application notes.
Together, they provide a complete description of the
technology and important design considerations.

• Technical Documentation Describing Intel's
28F400BX/28F004BX Flash Memory device
• Flash Memory Evaluation Kit II Installation Guide
and User's Manual with 28F400BX/28F004BX
Adapter Board Installation Instructions
• Manual Vacuum Wand
• Registration Card

3-744

Order Number: 297152·001

Flash Memory Systems

\

.

4

iMC001FlKA
1-MBYTE FLASH MEMORY CARD

•
•
•

•
•
•

..
..
..

Inherent Nonvolatllity (Zero Retention
Power)
- No Batteries Required for Back-Up
Over 1,000,000 Hours MTBF
- More Reliable than, Disk
High-Performance Read
- 200 ns Maximum Access Time
CMOS Low Power Consumption
- 25 mA Typical Active Current (X8)
- 400 ,..,A Typical Standby Cur,rent

•

Flash Electrical Zone-Erase
- 1 Second Typical per' 128 kByte Zone
- Multiple Zone Erase> 128 kB/s

Write Protect Switch to Prevent
Accidental Data Loss
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
ETOXTM II Flash Memory Technology
- 5V Read,12V Erase/Write
- High-Volume Manufacturing
Experience
PCMCIA/JEIDA 68-Pin Standard
- Byte- or Word-Wide Selectable

II Independent Software & Hardware

Vendor Support
-Integrated System Solution Using
Flash Filing Systems

Random Writes to Erased Zones
-10 ,..,s Typical Byte Write

Intel's iMC001 FLKA Flash Memory Card is the removable solution for storing and transporting important user
data and application code. The combination of rewritability and nonvolatility make the Intel Flash Memory Card
ideal for data acquisition and updatable firmware applications. Designing with Intel's Flash Memory Card
enables OEM system manufacturers to produce portable and dedicated function systems that are higher
performance, more rugged, and consume less power.
The iMC001 FLKA conforms to the PCMCIA 1.0 international standard, providing compatibility at the hardware
and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the memory card's
address OOOOOH with a format utility. This information provides data interchange functional compatibility. The
200 ns access time allows for "execute-in-place" capability, for popular low-power microprocessors. Intel's
1-MByte Flash Memory Card operates in a byte-wide and word-wide configuration providing performance/
power options for different systems.
Intel's Flash Memory card employs Intel's ETOXTM II Flash Memories. Filing systems, such as Microsoft's'
Flash File System (FFS), facilitate data file storage and card erasure using a purely nonvolatile medium in the
DOS environment. Flash filing systems, coupled wi~h the Intel Flash Memory Card, effectively create an ali-silicon nonvolatile read/write random access memory system that is more reliable and higher performance than
disk-based memory systems.

'Microsoft is a trademark of Microsoft Corp.
ExCA is a trademark of Intel Corporation.

4-1

October 1992
Order Number: 290399-003

intel .

IMC001FLKA

r-T

f41~~~~~~~~~_54_.o-,,:I:-f0..;,.I_m_m:_-_-_-_-_-_- .....:+1·1

3.3 :1:0.1mm

t'--------~~--------~--r

E
E
OJ

..
o

co

::i
E

,§.

.5
:::E
C!
0

tl~J1

'-

I

I

FRONT SIDE

00000000000000000000000000000000
00000000000000000000000000000
BACK SIDE

290399-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

GNO
03
04
05
Os
07
CEl
AlO
OE
All
A9·
As
A13
A14
WE
NC
VCC

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

VPPl
A1S
A15
A12
A7
As
A5

~
A3
A2
Al
Ao
Do
01
02
WP
GNO

GNO
COl
011
012
013
014
015
CE2
NC
NC
NC
A17
A1S
A19
NC
NC
VCC

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

VPP2
NC
NC
NC
NC
NC
NC
NC
NC
REGl
BV022
BV012
Os
09
010
CO2
GNO

NorES:
1. REG = register memory seleCt = No Connect (NC), unused. When REG is brought low, PCMCIAlJEIDA standard
card information structure data is expected. This is accomplished by formatting the card with this data.
2. iWD = battery detect voltage = Pulled high through pull-up resistor.

Figure 1.IMC001FLKA Pin Configuration

4-2

iMC001FLKA

Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A19

I

ADDRESS INPUTS for memory locations. Addresses are internally latched during
a write cycle.

00-0 15

1/0

DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs,data
during memory read cycles. The data pins are active high and float to tri-stat~
OFF when the card is deselected or the outputs are disabled. Data is internally
latched duri l1 g a write cycle.

CE1, CE2

I

CARD ENABLE: Activates the card's high and low byte control logic, input_
buffers, zone decoders, and associated memory devices. CE is active low; CE
high deselects the memory card and reduces power consumption to standby
levels.

OE

I

OUTPUT ENABLE: Gates the cards output through the data buffers during a read
cycle. OE is active low.

WE

I

WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
NOTE: With Vpp :::::6.5V, memory contents cannot be altered.

VPP1, VPP2

ERASE/WRITE POWER SUPPLY for writing the command register, erasing the
entire array, or writing bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 5%).

GNO

GROUND

COl, CO2

0

CARD DETECT: The card is detected when COl and C02 = ground.

WP

0

WRITE PROTECT: All write operations are disabled with WP = active high.
NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

NC
BV01, BV02

0

BATTERY VOLTAGE DETECT: Not Required.

,

4·3

'~

iMC001FLKA

eEIV RS
AND
BUFFERS
WP

~

~
1!!!...-

WE
OE

~

'tt~,
0-0
I
I

• _-

I
I

~ WRITE PROTECT
SWITCH

Ao

Ao-A 16

-

A1-A 19

..

ADDRESS
BUFFERS
AND
DECODERS

CE2
CE 1

CEH o-CEH 3
CELo- CEL3

28f010
~ Ao-A 16 0 0-0 7

r- CE ZO
r- WE
r- OE

--COl
REG

q

28f010

r-

--

I-OE
Vss Vee VpP2

I I I
""" Ao-A 16 00-07

BOV 1

I I I
r-

""" Ao-A 16 08-0 15

r-CE
r- WE Z2

r-CE
r- WE Z3

I-OE

I-OE

Vss Vee VpP1

I

BVO

I

r-

r-CE
Z1
r- WE

Vss Vee VpP1

CARD DETECT

""" Ao-A 16 0 8-0 15

I

•
••

r-

Vss Vee VpP2

I

I

I

•

•
•

Vee
BATTERY VOLTAGE
DETECT

290399-2

Figure 2. IMC001FLKA Block Diagram

4-4

int:et

IMC001FLKA

iMC001 FLKA consumes no power when the system
is off. In addition, the iMC001 FLKA offers a considerable cost and density advantage over memory
cards based on static RAM with battery backup.

. APPLICATIONS
The iMC001 FLKA Flash Memory Card allows for the
storage of data and application programs on a purely solid-state removable medium. System resident
flash filing systems, such as Microsoft's Flash File
System, allow Intel's ETOX II highly reliable Flash
Memory Card to effectively function as' a physical
disk drive.
User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
substantial reduction of active power consumption,
size, and weight--consideratioris particularly important in portables and dedicated systems. The
iMC001 FLKA's high performance read access time
and command register microprocessor write interface allows for use .of the flash memory system in an
"execute-in-place" architecture. This configuration .
eliminates .the need for the redundancy associated
with DRAM and Disk memory system architectures.
ROM based operating systems, such as Microsoft's
MS~DOS ROM Version allow for "instant-on" capability. This enables the design of systems that boot,
operate, store data files, and execute application
code from/to purely nonvolatile memory.
The PCMCIAlJEIDA 68-pin interface enables the
end-user to transport data and application code between portables ahd host systems. Intel Flash PC
cards provide durable nonvolatile memory storage
protecting valuable user code and data.
For systems currently using a static RAM/battery
configuration
for' data
acquisition,
the .
iMC001FLKA's inherent nonvolatility eliminates the
heed for battery backup. The .concern for battery
failure no longer exists, an important consideration
for portable computers and medical instruments,
both
requiring
continuous
operation.
The

4-5

The flash memory card's electrical zone-erasure,
byte writability, and complete' nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the designer the flexibility to
selectively rewrite zones of data while saving other
zones for infrequently updated look-up tables, for
example.

PRINCIPLES OF OPERATION
Intel's Flash Memory Card combines the functionality of two mainstream memory technologies: the rewritability of RAM and the nonvolatility of EPROM.
The flash memory card consists of an array of individual memory devices,' each of which defines a
physical zone. The iMC001 FLKA's lTIemory devices .
erase as individual blocks, equivalent in .size to the
128 kByte zone. Multiple zones can be erased simultaneously provided sufficient current for the appropriate number of zones (memory devices). Note,
multiple zone erasure requires higher current from
both the Vpp and Vee power supplies. Erased zones
can then be written in bit~ or byte-at-a-time fashion
and read randomly like RAM. Bit level write capability also supports disk emulation.
In the absence of high voltage on the VPP1/2 pins,
the iMC001 FLKA remains in the read-only mode.
Manipulation of the external memory card-control
pins yields the standard read, standby, and output
disable operations.
The same read, standby, and output disable operations are available when high voltage is applied to
the VPP1/2 pins. In addition, high voltage on VPP1/2

infel .

iMC001FLKA

enables erasure and rewriting of the accessed
zone(s). All functions associated with altering zone
contents-erase, erase verify, write, and write verify-are accessed via the command register.

the card is properly loaded. Note that the two pins
are logated at opposite ends of the card. Each CO
output should be read through a port bit. Should only
one of the two bits show the card to be present, then
the system should instruct the user to re-insert the
card squarely into the, socket. Card detection can
also tell the system whether or not to redirect drives
in the case of system booting. C01/2 is active low,
internally tied to ground.

Commands are written to the internal memory register(s), decoded by zone size, using standard microprocessor write timings. Register contents for a given zone serve as input to that zone's internal statemachine which controls the erase and rewrite circuitry. Write cycles also internally latch addresses and
data needed for write and erase operations. With the
appropriate command written to the register(s), stan-'
dard microprocessor read timings output zone data,
or output data for erase and write verification.

Write Protection
The flash memory card features three types·of write
protection. The first type features a mechanical
Write Protect Switch that disables the circuitry that
control Write Enable to the flash devices. When the
switch is activated, WE is forced high, which disables any writes to the Command Register. The second type of write protection is based on tlie
PCMCIAI JEIOA socket. Unique pin length assignments provide protective power supply sequencing
during hot insertion and removal. The third type operates via software control through the Command
Register when the card resides in its connector. The
Command Register of each zone is only active when
VPP1/2 is at high voltage; Oepending upon the application, the system designer may choose to make
VPP1/2 power supply switchable-available only
when writes are desired. When VpP1/2 =. VPPL, the
contents of the register default to the read command, making theiMC001 FLKA a read-only memory
card. In this mode,the memory contents cannot be
altered.

Byte-Wide or Word-Wide Selection
The flash' memory card can be read, erased, and
written in a byte-wide or word-wide mode. In the
word-wide configuration VPeL and/orCE1 control
the LO-Byte while VPP2 and CE2 control the HI-Byte
(Ao= don't care).
Read, Write, and Verify operations are byte- or wordoriented, thus zone independent. Erase Setup and
Begin Erase Commands are zone dependent such
that commands written to any address within a 128
kByte zone boundary initiate the erase operation in
that zone (or two 128 kByte zones under word-wide
operation).
Conventional x8 operation uses CE1 active-low, with
CE2 high, to read or write data through· the 00-07
only. "Even bytes" are accessed whenAo is low,
corresponding to the low byte of the completex16
word. When Ao is high, the "odd byte" is accessed
by transposing the high byte of the complete x16
word onto the 00-07 outputs. This odd byte corresponds to data presented on 08-015 pins in x16
mode.

The system designer may choose to leave VPP1/2 =
VPPH, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited w,henever Vee is below the write
lockout voltage, VLKO. (See the section on Power
Up/Oown Protection.) The iMC001 FLKAis designed
to accommodate either design practice, and to encourage optimization of the processor-memory card
interface.

Note that two zones logically adjacent in x16 mode
are multiplexed through 00-07 in x8 mode and are
toggled by the Ao address. Thus, zone specific
erase operations must be kept discrete in x8 mode
by addressing even bytes only for one-half of the
zone pair, then addressing odd bytes only for the
other half.

BUS OPERATIONS
Read
The iMC001 FLKA has two control functions, both of
which must be logically active, to obtain data at the

Card Detection
The flash memory card features two card detect pins
(C01/2) that allow the host system to determine if

4-6

intel·

IMC001FLKA

outputs. Card Enable (CE) is the power control and'
should be used forh!9!:!. and/or low zone(s) selection. Output Enable (OE) is the output control and
should be .used to gate data from the output pins,
independent of accessed zone selection. In the
byte-wide configuration, only one CE is r~ired.
The word-wide configuration requires both CEs active low.
.

Write
Zone erasure and rewriting are accomplished via the
Command Register, when high voltage is applied to
VPP1/2. The contents of the register serve as input
to that zone's internal state-machine. The state-machine outputs dictate the function of the targeted
.zone.

When VPPl/2 is high (VPPH), the read operations
can be used to access zone data and to access data
for write/erase verification. When VpPl/2 is low
(Vppu, only read accesses to the zone data are allowed.

The Command Register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The Command Register is written by bringing Write
Enable to a logic-low level. (VII), while Card Enable(s) is/are low. Addresses are latched on the failing edge of Write Enable, while data is latched on
, the rising edge of the Write Enable pulse. Standard
microprocessor write timings are used.

Output Disable
With Output Enable at a logic-high level (VIH), output
from the card is disabled. Output pins are placed in a
high-impedance state.

.Refer to AC Write Characteristics and the Erase/
Write Waveforms for specific timing parameters.

Standby
With one Card Enable at ~ logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only the zone correspond.!!!g to the selected address within the upper or
lower eel ,2 bank is active at a time. (NOTE: ~ must
be low to select the low half of the x16 word when
CE2 =1 1 and CE1 = 0.) AU other zones are deselected, substantially reducing card power consumption. For deselected banks, the outputs are placed in
a high-impedance state, independent of the Output
Enable signal. If the iMC001 FLKA is deselected during erasure, writing, or write/erase verification, the
accessed zone draws active durrent until the operation is terminated.

Intellgent Identifier Command
The manufacturer- and device-codes can be read
via the Command Register, for instances where the
iMC001 FLKA is erased and rewritten ina universal
reader/writer. Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the memory device code (B4H).
.

COMMAND DEFINITIONS
When low voltage is applied to the Vpp pins(s), the
contents of the zone Comm/lnd Register(s) default
to OOH, enabling read-only operations.
Placing high voltage. on the Vpp pines) enable(s)
read/write operations. Zone, operations are selected
by writing specific data patterns into the Command
Register. Tables 3 and 4 define these iMC001 FLKA
register commands for both byte-wide and word.wide configurations.
All commands written to the Command Register require that the zone address be valid or the incorrect
, zone will receive the command. Any Command/
Data Write or Data Read requires the correct valid
address.

4-7

infel .

iMC001FLKA

Table 2 Bus Operations
Pins
Operation
Read (x8)

[1,71

[1,71

VPP2

VPP1

8

VPPL
VPPL

Notes

Ao

CE2

CE1

OE

WE

08-0 15

00-0 7

VPPL

VIL

VIH

VIL

VIL

VIH

Tri-state

Data Out-Even

VPPL

VIH

VIH

VIL

VIL

VIH

Tri-state

Data Out-Odd

Data Out

Tri-state

Read (x8)

9

C
0

Read (x8)

10

VPPL

VPPL

X

VIL

VIH

VIL

VIH

"D
I'G
GI

Read (x16)

11

VpPL

VPPL

X

VIL

VIL

VIL

VIH

Data Out

Data Out

X

X

X

VIH

VIH

Tri-state

Tri-state

>-

.

II:

GI

:e3:

......

"D
I'G
GI

II:

Output Disable

VPPL

VPPL

Standby

VPPL

VPPL

X

VIH

VIH

X

X

Tri-state

Tri-state.

VPPX

VPPH

VIL

VIH

VIL

VIL

VIH

Tri-state·

Data Out-Even

Read (x8)

3,8

Read (x8)

3,9·

VpPH

Vppx

VIH

VIH

VIL

VIL

VIH

Tri-state

Data Out-Odd

Read (x8)

10

·VpPH

VpPX

X

VIL

VIH

VIL

VIH

Data Out

Tri-state

Read (x16)

3,11

VpPH

VPPH

X

VIL

VIL

VIL

VIH

Data Out

Data Out

5,8

VpPX

VPPH

VIL

VIH

VIL

VIH

VIL

Tri-state

Data In-Even

Write (x8)

9

VPPH

Vppx

VIH

VIH

VIL

VIH

VIL

Tri-state.

Data In-Odd

Write (x8)

10

VPPH

Vppx

X

VIL

VIH

VIH

VIL

Data In

Tri-state

Write (x16)

11

VPPH

VPPH

X

VIL

VIL

VIH

VIL

Data In

Data In

Standby

4

VpPH

VPPH

X

VIH

VIH

X

X

Tri-state

Tri-state

VPPH

VPPH

X

X

X

VIH

VIL

Tri-state

Tri-state

Write (x8)

• Output Disable
NOTES:

1. Refer to OC Characteristics. When VPP1/2 = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may be accessed via a command register write sequence. Refer to Table 3. All other
addresses l o w . .
3. Read operations with VpP1/2 = VpPH may access array data or the inteligent Identifier codes;
4. With VpP1/2 at high voltage, the standby current equals Icc + Ipp (standby).
5. Refer to Table 3 for valid Oata-In during a write operation.
6. X can be VIL or VIH.
7. Vppx = VPPH or VPPL.
.
8. This x8 operation reads or writes the low byte of the x16 word on 000-7, i.e., Ao low reads "even"byte in x8 mode.
9. This x8 operation reads or writes the high byte of the x16 word on 000-7 (transposed from 008-15), i.~., Ao high reads
"odd" byte in x8 mode.
.
10. This x8 operation reads or writes the high byte of the x16 on 008-15. Ao is "don't care".
11 . .Ao is "don't care", unused in XIS mode. High and low bytes are presented simultaneously. .

4-8

intal.

IMC001FLKA

Table 3. Command Definitions Byte-Wide Mode
Command

Bus
First Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2)

Read Memory

Second Bus Cycle
Data(~)

Operatlon(1) Address(2) Data(3)

1

Write

RA

OOH

Read inteligent
Identifier Codes

4

3

Write

IA

SOH

Read

Set-Up Erase/Erase

5

2

Write

ZA

20H

Write

ZA

20H

Erase Verify

5

2

Write

EA

AOH

Read

EA

Eve

Set-Up Write/Write

6

2

Write

WA

40H

Write

WA

we

Write Verify

6

2

Write

WA

COH

Read

WA

wve

Reset

7

2

Write

ZA

FFH

Write

ZA

FFH

Table 4. Command Definitions Word-Wide Mode
Command

Bus
Firat Bus Cycle
Second Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)

Read Memory

1

Write

RA

OOOOH

Read inteligent
Identifier Codes

4

3

Write

IA

SOSOH

Read

Set-Up Erase/Erase

5

2

Write

ZA

2020H

Write

ZA

2020H

Read

EA

Eve

Write

WA

we

Erase Verify

5

2

Write

EA

AOAOH

Set-Up Write/Write

6

2

Write

WA

4040H

Write Verify

6

2

Write

WA

COCOH

Read

WA

wve

Reset

7

2

Write

ZA

FFFFH

Write -

ZA

FFFFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of, memory location to be read during erase verify.
RA = Read Address
WA = Address of memory location to be written.
ZA = Address of 128 kByte zones involvEKI in erase operation.
Addresses are latched on the' falling edge of the Write Enable pulse.
3. 10 = Data read from location IA during device Indentification. (Mfr = 89H, Device = B4H).
EVD = Data read from locetion EA during erase verify.
WD = Data to be written at location WA. Data is latched on the rsing edge of Write Enable.
WVD = Data read from location WA during write verify. WA is latched on the Write oommand.
4. Following the Read Intellgent 10 command, two read operations access manufacturer and device podes.
5. Figure 5 illustrates the Erase Algorithm.
6. Figure 6 illustrates the Write Algorithm.
7. The seCond bus cycle must be followed by the desired command register write.
8.The Reset command operation on Zone Basic to Reset entire Card, requires reset Write cycles to each zone.

4-9

infel .

iMC001FLKA

Read Command

Erase-Verify Command

While VpP1/2 is .high, for .erasure and writing, zone
memory contents can be accessed via the read
command. The read operation .is initiated by writing
OOH (OOOOH for the word-wide configuration) into the
zone Command Register(s). Microprocessor read·
cycles retrieve zone data. The accessed zone remains enabled for reads until the Command Register(s) contents are altered.

The erase command erases all of the bytes of the
zone in parallel. After each erase operation, a!! b~ttes
in the zone. must be individually verified. In bytemode operations, zones are segregated by Ao in
odd and even banks; erase and erase verify operations must be done in complete passes of evenbytes-only then odd-bytes-only. See the Erase Algorithm for byte-wide mode. The erase verify operation
is initiated by writing AOH (AOAOH for word-wide) into
the Command Register(s). The address for the
byte(s) to be verified must be supplied as it is
latched on the falling edge of the Write Enable
pulse. The register write terminates the erase operation with the rising edge of its Write Enable pulse.

The default contents of each zone's register(s) upon .
VPP1/2 power-up is OOH (OOOOOH for word-wide).
This default value ensures that no spurious alteration of memory card contents occurs during the
VPP1/2 power transition. Where the VpP1/2 supply is
left at VPPH, the memory card powers up and remains enabled for reads until the command Register
contents of targeted zones are changed. Refer to
the AC Read Characteristics and Waveforms for
specific timing parameters.

The enabled zone applies an internally-generated
margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the
byte are erased. Similarly, reading FFFFH from the
addressed word indicates that all bits inthe word are
erased.

Intellgent Identifier Command
The erase-verify command must be written to the
Command Register prior to each byte (word) verification to latch its address. The process continues
for each byte (word) in the zone(s) until a byte (word)
. does not return FFH (FFFFH) data, or the last address is accessed.

Each zone of the iMC001 FLKA contains an inteligent Identifier to identify memol)' card device characteristics. The operation is initiated by writing 90H
(9090H for word-wide) into the Command Registeres) with zone address.. Following the command
write, a read cycle from address OOOOOH retrieves
the manufacturer code 89H (8989Hforword-wide).
A read cycle from address 0002H returns the device
code B4H (B4B4H for word-wide). To terminate the
operation, it is necessary to write another valid com~
mand into the register(s).

In the case where the data read is not FFH(FFFFH),
another erase operation is performed. (Refer to SetUp Erase/Erase.) Verification then resumes from the
address of the last-verified byte (word). Once all
bytes (words) in the zone(s) have been verified, the
erase step is complete. The accessed zone can now
be written. At this point, the verify operation is. terminated by writing a valid command (e.g., Write SetUp) to the Command Register. The Erase algorithms
for byte-wide and word-wide configurations illustrate
how commands and bus operations are combined to
perform electrical erasure of the iMC001 FLKA. Refer to AC Erase Characteristics and Waveforms for
specific timing parameters.

Set-Up Era$e/Erase Commands
Set~Up Erase stages the targeted zone(s) for electrical erasure of all bytes in the zone. The set-up erase
operation is performed by writing 20H to the Command Register (2020H for word-wide) with zone address.

To commence zone-erasure, the erase command
(20Hor 2020H) must again be written to the registeres) with zone address. The erase operation begins .
with the rising edge of the Write-Enable pulse and
terminates with the rising edge of the next Write-En-. .
able pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that zone memory contents are not accidentally erased. Also, zone-erasure can only occur
when high voltage is applied to the VPP1/2 pins. In
the absence of this high voltage, zone memory contents are protected against erasure. Refer to AC
Erase Characteristics and Waveforms for specific
timing parameters.
4-10

Set-Up Write/Write Commands
Set-Up write is a command-only operation that
stages the targeted zone for byte writing. Writing
40H (4040H) into the Command Register(s) performs the set-up operation.

infel·

IMC001FLKA

Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched on the rising edge of.
the Write Enable pulse. The rising edge of Write Enable also begins the write operation. The write operation terminates with the next rising edge of Write
Enable, which is used to write the verify command.
Refer to AC Write Characteristics and Waveforms
for specific timing parameters.

come without increasing memory cell size or complexity. First, an advanced tunnel oxide increases
the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric
field minimizes the probability of oxide defects in the
region. The lower electric field greatly reduces oxide
stress and the probability of failure.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10 ,...s
duration. Each operation is followed by a byte or
word verification to determine when the addressed'
byte or word has been successfully written. The algorithm(s) allows for up to 25 write operations per
byte or word, although mos~ bytes and words verify
on the first or second operation. The entire sequence of writing and byte/word verification is performed with Vpp at high voltage.

Write Verify Command
..

The iMCO01 FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur
sequentially or at random. Following each write operation, the byte or word just written must be verified.
The write-verify operation is initiated by writing COH
(COCO H) into the Command Register(s) with correct
address. The register write(s) terminate(s) the write
operation with the rising edge of its Write Enable
pulse. The write-verify operation stages the accessed zone(s) for verification of the byte or word
last written. The zone(s) apply(ies) an internaliy-generated margin voltage to the byte or word. A microprocessor read cycle outputs the data. A successful
comparison between the written byte or word and
true data means that the byte or word is successfully
written. The write operation then proceeds to the
next desired byte or word location; The Write algorithms for byte-wide .and word-wide configurations illustrate how commands are combined with bus operations to perform byte and word writes. Refer to
AC Write Characteristics and Waveforms for specific
timing parameters.

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zone(s).
Erasure begins with a read of memory zone contents. Reading FFH (FFFFH) data from the accessed zone(s) can be immediately followed by writing to the desired zon~(s).
For zones being erased and rewritten, uniform and
reliable erasure is ensured by first writing all bits in
the accessed zone to their charged state (data =
OOH byte-wide, OOOOOH word-wide). This is accomplished, using the write algorithm, in approximately
two seconds per 'zone.

Reset Command

Erase execution then continues with an initial erase
operation. Erase veification (data = FFH byte-wide,
FFFFH word-wide) begins at address OOOOOH and
continues through the zone to the last address, or
until data other than FFH (FFFFH) is encountered.
(Note: byte-wide erase operation requires separate
even- and odd-address passes to handle the individual 128 kByte zones.) With each erase operation, an
increasing number of bytes or words verify to the
erased state. Erase efficiency may be improved by
storing the address of the last byte or word verified
in a register(s).· Following the next erase operation,
verification starts at that stored address location.
Follow this procedure until all bytes in the zone are
erased. Then, re-start the procedure for the next
zone or word-wide zone pair. Erasure typically occurs in one second per zone.

A reset command is provided as a means to safely
abort the erase- or write-command sequences. Following either set-up command (erase or write) with
tWo consecutive writes of FFH (FFFFH or wordwide) will safely. abort the operation. Zone memory
contents will not be altered. A valid command must
then be written to place the accessed zone in the
desired state:
.

EXTENDED ERASE/WRITE CYCLING
Intel has designed extended cycling capability into

its ETOX II flash memory technology enabling a
flash memory card with a MTBF that is approximately 20 times more reliable than rotating disk technology. Resulting. improvements in cycling reliability

4-11

infel·

IMC001FLKA

(

START)

INITIALIZE SIZE
AND NUMBER OF' ZONES
ZONE L=O
ZONE H=1

290399-3

Figure 3. Full Card Erase Flow

4·12

infel .

iMC001FLKA

Bus
Operation

Command

Standby

Comments

Wait for Vpp Ramp
to VpPH (= 12.0V)(2)

Initialize Pulse-Count

Write

Set-Up
Write

Data = 40H +
Valid Address

Write

Write

Valid Address/Data

Duration of Write
Operation (tWHWH1)

Standby
Write

Write(3)
Verify

Standby

tWHGL

. Read

Read Byte to Verify Write
Operation at
Valid Address
Compare Data Output
to Data Expected

Standby

Write

Data = COH + Valid
Address; Stops(4)
Write Operation

Read

Standby

Data = ~OH.
Resets the Register for
Read Operations
Wait for Vpp Ramp·
to VPPL(2)

290399-4
NOTES:
1. CAUTION: The algorithm MUSTBE FOLLOWED to ensure proper and reliable·operation of the device.
2. See D.C. Characteristics for the value of VPPH and VpPL.
3. Write Verify is only performed after a byte write operation. A final read/compare may be performed (optional) after the
register is written with the Read command.
4. Refer to principles of operation.

Figure 4. Write Algorithm for Byte-Wide Mode

4-13

intel~

iMC001FLKA

Bus

Operation

Command

Standby

Comments

Wait for VPP Ramp
to VPPH (= 12.0V)(2)
Use Write Operation
Algorithm
Initialize Even/Odd
Addresses,
Erase Pulse Width,
and Pulse Count

Write

Set-Up
Erase

Data = 20H

+ Address

Write

Erase

Data = 20H

+ Address

Standby
Write

Duration of Erase
Operation (tWHWH2)
Erase
Verify(3)

Addr = By1e to Verify;
Data = AOH; Stops

Standby

Erase Operation(4) tWHGL

Read

Read By1!l to Verify
Erasure at Address

Standby

Compare Output to FFH
Increment Pulse Count

Write

Read

Standby

Data = OOH, Resets the
Register for Read.
Operations
Wait for VPP Ramp
to VPPL(2)

290399-5
NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and VPPL.
3. Erase Verify is only performed after chip erasure. A final read/compare may be performed (optional) after the register
is written with the Read command.
4. Refer to principles of operation.

Figure 5. Erase Algorithm for Byte-Wide Mode
4-14

inteL

iMC001FLKA

Comments
Wait for Vpp ramp to VpPH

ADRS = Address to Write
W_DAT = Data Word to Write
Initialize Data Word Variables:
V_OAT = Valid Data
W_COM = Write Command
V_COM = Write Verify Command
PLSCNT_HI = HI Byte Pulse Counter
PLSCNT_LO = LO Byte Pulse Counter
FLAG = Write Error Flag

PLSCNT _HI = 0
PLSCNLLO= 0
FLAG = 0

Write Set-Up Command
Address needs to be Valid

High/Low Byte
Compare &: Mask
Subroutine

Write
See Write Verify and Mll;sk Subroutine
Write Verify Command
F_OAT

=

Flash Memory Data

Compare Flash Memory Data to Valid Data
(Word Compare): If Not Equal, Check for
Write Error Flag. If Flag Not Set, Compare
High and Low Bytes in the Subroutine.

Check Buffer of 110 Port for More Data to
Write.

Reset Device for Read Operation.
Turn offVpp.

290399-6

Figure 6. Write Algorithm for Wqrd-Wide Mod.e

4-15

infel~

iMC001FLKA

Comments

To Look at the LO Byte. Mask· the
HI Byte with 00.
Y-DAT=(V_DAT OR OOFFH)
W_COM = (w _COM OR OOFFH)
V_COM = (V_COM OR OOFFH)

If the LO Byte Verifies. Mask the
LO Byte Commands with the Reset
Command (FFH)
If the LO Byte Does Not Verify.
then Increment its Pulse Counter
and Check for Max Count.
FLAG = 1 Denotes a LO Byte
Error.

Repeat the sequence for the HI
Byte.
.
V_OAT = (V_OAT OR FFOOH)
W_COM = (W _COM OR FFOOH)
V _COM = (V _COM OR FFOOH)

FLAG = 2 Denotes a HI Byte
Error. FLAG = 3. Denotes both a HI
and LO Byte Errors. FLAG = 0
Denotes No Max Count Errors;
Continue with Algorithin.

290399-7

·Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_DAn. the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 7. Write Verify and Mask Subroutine for Word·Wide Mode

4-16

infel~

IMC001FLKA

Comments

Walt for Vpp to stabilize.

Use Write Operation Algorithm in x8 or x16
Configuration.
Initialize Variables:
PLSCNT_HI = HI Byte Pulse Counter
PLSCNT_LO = LO Byte Pulse Counter
FLAG = Erasure Error Flag
ADRS = Address
LCOM = Erase Command
. V_COM = Verify Command

=

FLAG 0
E-COM = 2020H
V_COM = AOAOH

Erase Set-Up Command
Start Erasing
Duration of Erase Operation.

Erase Verify Command Stops Erasure.
See Block Erase Verify and Mask Subroutine

When Both Devices at ADRS Are Erased, F_
DATA = FFFFH. If Not Equal, Increment the
Pulse Counter and Check for Last Pulse.

y

Reset Commands Default to
(LCOM = 2020H) (V_COM
before Verifying Next ADRS.

= AOAOH)

Reset Device for Read Operation.
Turn Off Vpp.

290399-8

NOTES:
x16 Addressing uses A1-A19 only.

Ao =

0 throughout word-wide operation.

Figure 8. Erase Algorithm for Word· Wide Mode

4-17

infel~

iMC001FLKA

Comments
This subroutine Reads the
Data Word (F_OAT A). it then
masks the HI or LO Byte of the
Erase and Verify Commands
from Executing during the Next
Operation.
If both HI and LO Bytes Verify,
then Return.
Mask· the HI Byte with OOH.

E_COM = (E_COM or OOffH)
V_COM = (V_COM or OOffH)

If the LO Byte Verifies Erasure,
then Mask· the Next Erase
and Verify Commands with
FFH(RESET).
If the LO Byte Does Not Verify,
then Increment its Pulse
Counter and Check for Max
Count. FLAG = 1 Denotes a
LO Byte Error.

Repeat the Sequence for the
HI Byte.

E_COM = (E_COM or ffOOH)
V_COM = (V_COM or ffOOH)

FLAG =:= 2 Denotes a HI Byte
Error. FLAG = 3 Denotes both
HI and LO Byte Errors. FLAG
= 0 Denotes no Max Count
Errors; Continue with
Algorithm.

290399-9

*Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_DAT), the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 9. Erase Verify and Mask Subroutine for Word-Wide Mode

4-18

intel"

iMC001FLKA

SYSTEM DESIGN CONSIDERATIONS
Three-Line Control
Three-line control provides for:
a. the lowest possible power dissipation and,
b. complete assurance that output bus contention
will not occur.

The card connector should also have a 4,7 fLF electrolytic capacitor between Vee and Vss, as well as
between VPP1IVpP2 and Vss. The bulk capacitors
will overcome voltage slumps caused by printed-~ir­
cuit-board trace inductance, and will supply charge
to the smaller capacitors as needed.

Power Up/Down Protection
The PCMCIAlJEIDA socket is specified, via unique
Pin lengths, to properly sequence. the power supplies to the flash memory card. This assures that hot
insertion and removal will not result in card damage
or data loss.

To efficiently use these three contrQ!Jnputs, an address-decoder output should drive CE1,2~hile the
system's Read signal controls the card OE signal,
and other parallel zones. This, coupled with the internal zone decoder, assures that only enabled
memory zones have active outputs, while deselected zones maintain the low power standby condition.

Power-Supply Decoupling

Each zone in the iMC001 FLKA is designed to offer
protection against accidental erasure or· writing,
caused by spurious system-level signals that may
exist during power transitions. The card will powerup into the read state.

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues-standby, active and transient current peaks, produced by
falling and rising edges of CE1/2. The capacitive and.
inductive loads on the card and internal flash memory zones determine the magnitudes of these peaks.

A system designer must guard against active writes
for Vee vol~es above VLKO when Vpp iSl;lctive.
Since both WE and CE1, 2 must be low for a command write, driving either to VIH will inhibit. writes.
With its control register architecture, alteration· of
zone contents only occurs after successful completion of the two-step command sequences.

Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC001 FLKA features on-card ceramic decoupling
capacitors connected between Vee and Vss, and
between VPP1IVPP2 and Vss.

While these precautions are sufficient for most applications, it is recommended that Vee reach its steady
state value before raising VPPl/2 above Vee +
2.0V. In addition, upon powering-down, VpP1/2
should be below Vee + 2.0V, before lowering Vee.

4-19

intel .

IMC001FLKA

ABSOLUTE
MAXIMUM RATINGS·
,

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature '
During Read ......•......•..•• 0'Cto +60'C(1)
During Erase/Write ..•..•.•...••• O'C to + 60'C
Temperature under Bias ..•.•.... -1 O'C to + 70'C
Storage Temperature! .•......... -30'C to + 70'C
Voltage on Any Pin with
Respect to Ground •.••....•. - 2.0V to + 7.0V(2)

• WARNING: Stressing the device beyond the "Absolute

,A,,1sximurn Ratings" tTtay cause periilsnen! damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

VPP1IVPP2 Supply Voltage
with Respect to Ground
during Erase/Write .•.... : - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage with
Respect to Ground ..•...•... - 2.0V to + 7.0V(2)
NOTES:

1. Operating temperature is for, commercial product defined by this specification.
2. Minimum De input voltage Is '-O.SV. During transitions, inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + O.SV, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum DC input voltage on VPP1IVPP2 may overshoot to + 14.0V for periods less than ,20 ns.

OPERATING CONDITIONS
Symbol
TA

Limits

Parameter
Operating Temperature

Min

Max

O.

60

Unit

Comments

·C

For Read-Only and
Read/Write Operations

Vec

Vee Supply Voltage

4.75

5.25

V

VPPH

Active VPP1> VpP2
Supply Voltages

11.40

12.60

V

VPPL

Vpp during Read Only
Operations

0.00

6.50

V

4-20

iMC001FLKA

DC CHARACTERISTICS-Byte Wide Mode
Symbol

Parameter

Limits

Notes
Min

Typ

Max

Unit

Test Conditions

III

Input Leakage Current

1

±1.0

±20

p,A

Vee = Vec Max
VIN = Vcc or Vss

ILO

Output Leakage Current

1

±1.0

±20

p,A

lecs

Vce Standby Current

1

0.4

o.s

mA

= Vcc Max
Your = VccorVss
Vee = Vec Max
CE = Vcc = ±0.2V
CE = VIH, Vce = Vec Max
Vee = Vec, Max CE = VIL
f = 6 MHz, lOUT = 0 mA

4

7

mA

25

50

mA

Vee

lec1

Vee Active Read Current

1,2

lec2

Vee Write Current

1,2

5.0

15.0

mA

Writing in Progress

lec3

Vee Erase Current

1,2

10.0

20.0

rnA

Erasure in Progress

lec4

Vee Write Verify Current

1,2

10.0

20.0

rnA

Vpp = VPPH
Write Verify in Progress

lecs

Vee Erase Verify Current

1,2

10.0

20.0

rnA

Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±SO

p,A

Vpp::; Vec

IpP1

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

s.o

30

rnA

Vpp = VPPH
Write in Progress

IpP3

Vpp Erase Current

1,3

10

30

rnA

Vpp = VpPH
Erasure in Progress

IpP4

Vpp Write Verify Current

1,3

2.0

5.0

rnA

Vpp = VPPH
Write Verify in Progress

Ipps

Vpp Erase Verify Current

1,3

2.0

5.0

rnA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

O.S

V

VIH

Input High Voltage

2.4

VOL

Output Low Voltage

VOH1

Output High Voltage

VPPL

Vpp during Read-Only
Operations

0.00

VPPH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write Lock
Voltage

2.5

1
0.4

O.S

rnA

±o.os

Vee

+ 0.3

Vpp> Vec
Vpp::; Vec

V
V

IOL = 3.2 rnA
Vee = Vce Min.

V

IOH = -2.0 rnA
Vec = Vce Min

6.5

V

Note: Erase/Write are
Inhibited when Vpp = VPPL

12.60

V

0.40
3.S

V

NOTES:
1. Ali currents are in RMS unless otherwise noted. Typical values at Vee = S.OV. Vpp = 12.0V. T = 2Soe.
2. 1 chip active and 7 in standby for byte-wide mode.
3. Assumes 1 Vpp is active.

4-21

infel·

IMC001FLKA

DC CHARACTERISTIC&;'-Word Wide Mode
Symbol

Parameter,

Notes

Limits
Min

Typ

Max

Unit

Test Conditions
:
~

"

III

Input Leakage Current

1

±1.0

±20

/LA Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage
Current

1

±1.0

±20

!LA

Vee = .Vee Max
VOUT = Vee or \Iss

Ices

Vee Standby Current

1

0.4

0.8

mA

Vee = Vee Max,
CE = Vee ±0.2V

4

7

mA

Vee = Vee Max, CE = VIH

40

80

mA

Vee = Vee, MaxCE = VIL
f = 6 MHz, lOUT = 0 mA

I

'

ICC1

Vce Act!ve Read Current

1,2

lee2

Vee Write Current'

1,2

5.0

25

mA

Writing in Progress

lee3

Vee Erase Current

1,2 '

15.0

30

mA

Erasure in Progress

1CC4

Vee ~rite Verify Current

1,2

15.0

30

mA

Vpp = VPPH,
Write Verify in Progress

lee5

Vee Erase Verify Current

1,2

15.0

30

mA

Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±80

/LA

Vpp

IpP1

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

16

60

mA

Vpp = VPPH
Write in Progress

IpP3

Vpp Erase Current

1,3

20

60

mA

Vpp = VPPH
Erasure In Progress

IpP4

Vpp Write Verify Current

1,3

5.0

12

mA

Vpp = VPPH
Write Verify in P~ogress

IpP5

Vpp Erase Verify Current

1,3

5.0

12

mA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Vol,tage

-0.5

0.8

V'

VIH

Input High Voltage

2.4

VOL

Output Low Voltage

VOH1

Output High Voltage

3.8

VPPL

Vpp d,uring Read-Only
Operations

0.00

V~PH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write Lock
Voltage

2.5

1
0.7

1.6

mA

±0.16

Vee

+ 0.3

0.40

~

Vee

Vpp:?: Vee
Vpp

~

Vee

V
V

IOL = 3.2mA
, Vee =,Vee Min

V

IOH = -2.0mA
Vee = Vee Min

6.5

V

Note: Erase/Write are
Inhibited when Vpp = VPPL

12.60

V
V

NOTES:

,

1. All currents are In RMSunless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T= 25°e.,
2. 2 chips active and 6 in standby for word-wide mode.
'
3. Assumes 2 VppS are active.,
4-22

intel·

IMC001FLKA

CAPACITANCE T

= 25°C, f = 1.0 MHz

Symbol

Parameter

Limits

Notes
Min

Unit

. Conditions
VIN = OV

Max

CIN1

Address Capacitance

40

pF

CIN2

Control Capacitance

40

pF

VIN = OV

COUT

Output Capacitance

·40

pF

VOUT = OV

CliO

1/0 Capacitance

40

pF

VI/O = OV·

AC TEST CONDITIONS.
Input Rise and Fall Times (10% to 90%) ..•.•. 10 ns
Input Pulse Levels •.•••••.••.•..••. VOL and VOH1
Input Timing Reference Level ••.•.....• VIL and VIH
Output Timing Reference Level •.•...•. VIL and VIH

AC CHARACTERISTICS-Read-Only Operations
Symbol

Parameter

Notes

. Min
200

Max

Unit

tAVAV/tRC

Read Cycle Time

2

tELQV/tcE

Chip Enable Access Time

2

200

ns

tAVQV/tACC

Address Access Time

2

200

ns

lGLQV/toE

Output Enable Access Time

2

100

ns

tELQX/ t L2

Chip Enable to Output in Low Z

2

lEHQZ

Chip Disable to Output in High Z

2

tGLQX/toL2

Output Enable to Output in Low Z

2

lGHQZ/tOF

Output Disable to Output in High Z

2

toH

Output Hold from Address,
CE, or OE Change
.

tWHGL

Write Recovery Time before Read

NOTES:
1. Whichever occurs first.
2. RiselFall time :s; 10 ns.

4·23

ns

5

ns
60

ns

.5

ns
60

1,2

5

2

5

ns

-

ns
,...s

_.

vee POWER-UP/ STANDBY

ADDRESSES

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED-

\f\N\I\N\l\i

l

•

STANDBY/
Vee POWER-DOWN

DATA VALID

S!
ADDRESS STABLE

\I\XX

IAVAV(IRC>

~I

CI

J

\

CE (E)

- c:-

;;

...p

:.
o.

.,.

r

Of

.,

(1;)

J

..::u
i.1

~

tELQV(tcE)
tGLQX (tOLZ)
I - - tELQX (tlZ)

TIIIIA

HIGH Z

DATA (DQ)

VALID OUTPUT

\""T\ \/,

HIGH Z

:::I

III
t AVQV

5~;;

j

(tACC)

'~
290399-10

NOTE:-·
CE refers to "Ci:'1. 2--

0
....
"'1'1

~

lGLQV(toE)

1

i

g

,..

.1

WE (ii)

I0
0

L

I
-tGHQZ (tDr)

t WHGL

~ III~

;

5

IMC001FLKA

AC CHARACTERISTICS-For Write/Erase Operations
Symbol

Notes

Min

tAVAV/twc

Write Cycle Time

1,2

200

ns

tAVWL/tAS

Address Set-Up Time

1,2

0

ns

tWLAX/tAH

Address Hold Time

1,2

100

ns

Data Set-Up Time

1,2

80

ns

Data Hold Time

1,2

30

ns

tOVWH/tOS
. tWHOX/tOH

Parameter

Max

Unit

tWHGL

Write Recovery Time before Read

1,2 .

6

,..,s

tGHWL

Read Recovery Time before Write'

1,2

0

,..,s

tWLOZ

Output High-Z from Write Enable

1,2

5

tWHOX

Output Low-Z from Write Enable

1,2

tELWL/tcs

Chip Enable Set-Up Time before Write

1,2

40

ns

tWHEH/tcH

Chip .Enable Hold Time

1,2

0

ns

tWLWH/twp

Write Pulse Width

1,2

100

ns

tWHWL/twPH

Write Pulse Width High

1,2

20

ns

tWHWH1

Duration of Write Operation

1,2,3

10

,..,s

tWHwH2

Duration of Erase Operation

1,2,3

9.5

ms

tVPEL

Vpp Set-Up time to Chip Enable Low

1,2

100

ns

ns

60

ns

NOTES:

1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to A.C. Characteristics for Read-Only Operations.
2. Rise/Fall time ~ 10 ns.
3. The integrated stop timer terminates the write/erase opera~ons, thereby eliminating the need for a maximum specification.

ERASE/WRITE PERFORMANCE
Typ

-

Notes

Zone Erase Time

1,3,4

1.0

10

sec

Zone Write Time

1,2,4

2.0

12.5

sec

5

106

MTBF

Min

. Max

Parameter

Unit

Hrs

NOTES:

1. 25°C, 12.0V Vpp.
2. Minimum byte writing time excluding system overhead is 16 ILs (10 ILs program
+ 6ILs write recovery), while maximum is 400 ILs/byte (161Ls x 25 loops allowed
by algorithm). Max chip write time is specified lower than the worst case allowed by
the write algorithm since most bytes write significantly faster than the worst case
byte.
3. Excludes OOH writing Prior to Erasure.
4. One zone equals 128 kBytes.
5. MTBF = Mean Time Between Failure, 50% failure point for disk drives.

4-25

_.

l

WRITE
Vee POWER-UP

a:

STANDBY

SET-UP WRITE
COMMAND

WRITE COMMAND

LATCH ADDRESS

a:

VERIfY

DATA

COWWAND

WRmNG

WRITE
VERIFICAnON

STANDBY/
Vee POWER-DOWN

@

ADDRESSES

cr (E)

.."

I

iE
I:

...
CD

DE (G)

:-'

~

N
m

f;1
~
<
CD
....
0

.1-l I- 'GHWL I-- 'WHWL --I
WE

..~I

~'WHWHI

'1'

t WHGL

i

(Vi)

o
c

1-1 I-- 'WHOX

....... n

1-1 I-- 'WHOX

...."TIc

1-1 I-- 'WHOX

r

0'

~I

DATA (DO)

~

HIGH Z

:1

iD

(=40",OH for word wide mode)

(:COCOH for word wid. mode)

0

-..

'a
CD
DI

5.0V

0

Vee

:I

1/1

OV

12.0V
Vpp
YpPl

2'90399-11

NOTE:
CE refers to CE1, 2

Vee POWER-UP
STANDBY

a:

l-

ERASE

SET-UP ERASE
CO .... AND

ERASE
VERlflCAnON

VERIFY
ERASE CO ....AND

ERASING

CO .....AND

STANDBY/
Vee POWER-DOWN

•

ADDRESSES

CE (E)

i.c

I

~I

at (G)

'~"
~

t
....

I..

ViE(w)

0

J

~

:I

tWHDX

(II

.

0'
m

i

0
0

0
....
on

tWHDX

r"

DATA (DQ)

"»

HIGH Z·.

iii

:I

0

..

'V
CD

5.0V

II

Vee
OV

. 12.0V
Vpp

vpPL
290399-12

NOTE:
eE refers to eE1, 2

IMC001FLKA

ALTERNATIVE CE-CONTROLLED WRITES
Symbol

Parameter

tAvAV

Write Cycle Time

tAVEL

Address Set-Up Time

tELAX
tOVEH

Notes

Min

Max

Unit

200

ns

0

ns

Address Hold Time

100

ns

Data Set-Up Time

80

ns

tEHOX

Data Hold Time

30

ns

tEHGL

Write Recovery Time before Read

6

JJ.s

tGHEL

Read Recovery Time before Write

0

JJ.s

tWLEL

Write Enable Set-Up Time before Chip-Enable

0

ns

tEHWH

Write .Enable Hold Time

tELEH

Write Pulse Width

tEHEL
I

tpEL

0

ns

100

ns

Write Pulse Width High

20

ns

Vpp Set-UpTime to Chip-Enable Low

100

ns

1

NOTES:

1. Chip Enable Controlled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable. In
systems where Chip'Enable defines the write pulse width (with a longer Write Enable timing waveforms) all set-up, ho.ld and
inactive Write Enable times should be measured relative to the Chip Enable waveform.

4-28

_.

l

PROGRAM

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COMUAND

PROGRAM COMMAND
LATCH ADDRESS I:. DATA

PROGRAMMING

VERIFY
COMMAND

PROGRAM

VERIFICATION

STANDBY/
Vee POWER-DOWN

3

ADDRESSES

"'II

WE (E)

iFi

...
CD

r:::

T I.

....

.T

~.
-oJ!
tWlEl~tEHWH
L.-

t EHWH

~

...~

or (G)

~

I»

----1f---+·..
I·~-tEHGl---+I

i"
CD
>
0
.j>.

'"

<0

i:

CE (W)

n
o

~

-

t EHOX

CD

...3

0

-......

DATA (DQ)

III

o
......
r

t Glay (tOE)
t GlaX (t OlZ)

."

~

HIGH Z

0

(=4040H in word .Id. mode)

:E

(=COCOH in word wid. mode)

t Elax (tlZ )
tElay (teE)

;::;:
CD

5.0V

0

'a

...I»

Vee

CD

OV

c!:

0

~

III

12.DV

;-tyPEL~

\

Vpp
V pPL

290399-13

NOTE:

CE refers to GEl. 2

infel~

iMC001FLKA

ORDERING INFORMATION
Ii IMICloloIIIFILIKIAI.I$.IBlxlxlxlxlxl

l2:'

OMER IDENTIFIER

REVISION

K=WORO-WIDE
ARCH ITECTURE
FL= FLASH
001 = 1 MEGABYTE
DENS ITY IN MEGABYTES

MC= MEMORY CARD
I=INTEL

290399-14

Order Number

ADDITIONAL INFORMATION
ER-20, "ETOX II Flash Memory Technology"
RR-60, "ETOX II Flash Memory Reliability Data Summary"
AP-343, "Solutions for High Density Applications using Flash Memory"
RR70, "Flash Memory Card Reliability Data Summary"

294005
293002
292079
293007

REVISION HISTORY
,

Number

Description

03

-Removed PRELIMINARY
-Removed ExCA Compliance Section
-Clarified need for Valid Address during commands
-Corrected Vpp = VPPH in Erase Algorithm
-Increased ICC2-lcC5 D.C. current specs for both byte wide and word wide modes
-Revised and updated Application Section discussion
-Changed order number
-Corrected Erase Algorithm Pulse count to 3000

4-30

iMC002FLKA
2-MBYTE FLASH MEMORY CARD
• Inherent Nonvolatlllty (Zero Retention
Power)
- No Batteries Required for Back-up

• Write Protect Switch to Prevent
Accidental Data Loss
• Command Register Architecture for
Mlcroprocesssor/Mlcrocontroller
Compatible Write Interface

• Over 1,000,000 Hours MTBF
- More Reliable than Disk
• High-Performance Read
- 200 ns Maximum Access Time
• CMOS Low Power Consumption
- 25 mA Typical Active Current (X8)
- 400 p,A Typical Standby Current
• Flash Electrical Zone-Erase
- 2 Seconds Typical per 256 kByte
Zone
- Multiple Zone-Erase
• Random Writes to Erased Zones
-10 p,s Typical Byte Write

• ETOXTM II Flash Memory Technology
-5V Read, 12V Erase/Write
- High-Volume Manufacturing
Experience
.• PCMCIA/JEIDA 68-Pln Standard
-- Byte- or Word-wide Selectable
• Independent Software & Hardware
Vendor Support
-Integrated System Solution Using
Flash Filing Systems

Intel's iMC002FLKA Flash Memory Card i$ the removable solution for storing and transporting important user
data and application code. The combination of rewritability and nonvolatility make the Intel Flas\l Memory Card
ideal for data acquisition and updatable firmware applications. Designing with Intel's. Flash Memory Card
enables OEM system manufacturers to produce portable and dedicated function systems that are higher
performance, more rugged, and consume less power.
The iMC002FLKA conforms to the PCMCIA ·1.0 international standard, providing standardization at the hardware and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the memory
card's address OOOOOH with a format utility. This information provides data interchange functional capability.
. The 200 ns' access time allows for "execute-in~place" capability, for popular low-power microprocessors.
Intel's 2-MByte Flash Memory Card operates in a. byte-wide and word-wide configuration providing performance/power options for different systems.
Intel's Flash Memory card employs Intel's ETOXTM II Flash Memories. Filing systems, such as Microsoft's·
Flash File System (FFS), facilitate data file storage and card erasure using a purely nonvolatile medium in the
DOS environment. Flash filing systems, coupled with the Intel Flash Memory Card, effectively create an ali-silicon nonvolatile read/write random access memory system that is more reliable and higher performance than
.
disk-based memory systems.

• Microsoft is a trademark of Microsoft Corp.
ExCATM is a trademark of Intel Corporation.

4-31

October 1982·
Order Number: 280412-002

intel~

iMC002FLKA

r-T
fl

3.3 !, 0.1 mm

,
fr--~--~----~

I,
I,
"

E

I,

E

-5
c

-5
c

':i

':i

0

I,

0

g

d

tl

Jl:

I

tJ

I,
"

'-

I

FRONT SIDE

34 •

I

1

~
68 •

U

35

BACK SIDE

290412-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

GNO
\ 03
04
05
Os
07
CEl
AlO
OE
A11
A9
As
A13
A14
WE
,NC
Vee

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

VPPl
A16
A15
A12
A7
As
A5
A4
A3
A2
Al
Ao

Do
01
02
WP
GNO

GNO
COl
011
012
013
014
015
CE2
NC
NC
NC
A17
A1S
A19
A20
NC
Vee

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

VPP2
NC
NC
NC
NC
NC
NC
NC
NC
REGl
BV022
BV012
Os
09
010
CO2
GNO

NOTES:

1. REG = register memory select = No Connect (NC), unused. When REG is brought low, PCMCIAlJEIOA standard
card information structure data is expected. This is accomplished by formatting the card with this data.
2. BVl5 = battery detect voltage = Pulled High through Pull-Up Resistor.
.
Figure 1.IMC002FLKA Pin Configurations

4-32

intel·

IMC002FLKA

Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A20

I

ADDRESS INPUTS for memory locations. Addresses are internaily latched during
a write cycle.

00- 0 15

I/O

DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data
during memory read cycles. The data pins are activ~ high and float to tri·state
OFF when the card is deselected or the outputs are disabled. Oata is internally
latched during a write cycle.

eEl, CE2

I

CARD ENABLE: Activates the card's high and low byte control logic, input
buffers, zone decoders, and associated memory devices. CE is active low; CE
high deselects the memory card and reduces power consumption to standby
levels.

OE

I

OUTPUT ENABLE: Gates the cards output through the data buffers during a read
cycle; DE is active low.

WE

I

WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
NOTE:
. With Vpp ~ 6.SV, memory contents cannot be altered.
ERASE/WRITE POWER SUPPLY for writing the command register, erasing the
entire array, or writing bytes in the array.

VPP1, VPP2
Vee

DEVICE POWER SUPPLY (SV ± S%).

GNO

GROUND

COl, CO2

0

CARD DETECT. Thecard is detected at COl/2 = ground.

WP

0

WRITE PROTECT. All write operations are disabled with WP = active high.
NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

NC
BV01, BV02

0

BATTERY VOLTAGE DETECT. NOT REQUIRED.

4-33

•

IMC()()2FLKA

DO-~5

Da-~5

~

~
~
WP .

r==

I/O TRANSCEIVERS·
AND
BUFFERS
WP

'~~
0--0
I
I

Ao

Do-17
WE
OE

.

!.

,
I

• _ - \... WRITE PROTECT .
SWITCH
Ao-~7

~-~O

ADDRESS
BUFFERS.
AND
DECODERS

C~

CE,

CEHO~CEH3

CE~-CEL3

28F'020

Do-17 r-

Ao-~7

-CE
REG

WE

C~

q

28F'020
I-

ZO,

-WE

-O'E

-

CARD DETECT

O'E
Vss Vee VpP2

1 1 .1

I I I

CE

-WE

'

Do-17 r-

Z2

BVD

CE
-

WE

Da-~5 0004

Z3

OE

Vss Vee VpP1

I

I- Ao-~7

'.

-O'E
. BDV,

Z1

Vss Vee VpP1

I- AO-~7

,

Ao":~7 Da-~5

CE

I

I

•••

Vss Vee Vpp2

I

I

I

••
•

Vee
BATTERY VOLTAGE
DETECT

290412-2

Figure 2.IMC002FLKA Block Diagram

4-34

inial.

iMC002FLKA

ous operation. The iMC002FLKA consumes no power when the system is off. In addition, the iMC002FLKA offers a considerable cost and density advantage over memory cards based On static RAM with
battery backup.

APPLICATIONS
The iMC002FLKA Flash Memory Card allows.for the
storage of data and application programs on a purely solid-state removable medium. System resident
flash filing systems, such as Microsoft's Flash File
System, allow Intel's ETOX II highly reliable Flash
Memory Card to effectively function as a physical
disk drive.

The flash memory card's electrical zone-erasure,
byte writability, and complete nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the designer the· flexibility to
selectively rewrite zones of data while saving other
zones for infrequently updated look-up tables, for
example.

User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
substantial reduction of active power consumption,
size, and weight-considerations particularly important in portables and dedicated systems. The
iMC002FLKA's high performance read access time
and command register microprocessor write interface allows for use of the flash memory system in an
"execute-in-place" architecture. This configuration
eliminates the need for the redundancy associated
with DRAM and Disk memory system architectures;
ROM based operating systems, such as Microsoft's
MS-DOS ROM Version allow for "instant-on" capability. This enables the design of systems that boot,
operate, store data· files, and execute application
code from/to purely nonvolatile memory.
The PCMCIAlJEIDA 68-pin interface with flash filing
systems enables the end-user to transport data and
application code between portables and host systems. Intel Flash PC cards provide durable nonvolatile memory storage· protecting valuable user· code
and data.
For systems· currently using a static RAM/battery
configuration for data acquisition, the iMC002FLKA's
inherent nonvolatility eliminates the need for battery
backup. The concern of battery failure no longer exists, an important consideration for portable computers and medical instruments, both requiring continu-

PRINCIPLES OF OPERATION
Intel's Flash Memory Card combines the functionality of two mainstream memory technologies: the rewritability of RAM and the nonvolatility of EPROM.
The flash memory card consists of an array of individual memory devices, each of which defines a
physical zone. The iMC002FLKA's memory devices
erase as individual blocks, equivalent in size to the
256 kByte zone. Multiple zones can be erased simUltaneously provided sufficient current for the appropriate number of zones (memory devices). Note,
multiple zone erasure requires higher current from
both the Vpp and Vee power supplies. Erased zones
can then be written in bit- or byte-at-a-time fashion
and read randomly like RAM. Bit level write capability also supports disk emulation.
In the absence of high voltage on the VPP1;2 pins,
, the iMC002FLKA remains in the read-only mode.
Manipulation of the external memory card-control
pin yields the standard read, standby, and output
disable operations.
The same read, standby, and output disable operations are available when high voltage is applied to
the VPP1;2 pins. In addition, high voltage on VPP1;2

4-35

intel·

IMC002FLKA

enables erasure and rewriting of the accessed
zone(s). All functions associated with altering zone
contents-erase, erase verify, write, and write. verify-are accessed via the command register.
Commands are written to the internal memory register(s), decoded by zone size, using standard microprocessor write timings. Register contents for.a given zone serve as input to that zone's internal state-:
machine which. controls the erase and rewrite circuitry. Write cycles also internally latch addresses and
data needed for write and erase operations. With the
appropriate command written to the register(s), standard microprocessor read timings output zone data,
or output data for erase and write verification.

Card Detection
The flash memory card features two card detect pins
(CD1@thataliowthe host system to deterrnine,ifthe
card is properiy loaded. Note that the two.e!!!!I are
located at oPPosite ends of the card. Each CO out~
put should be read through a port bit. Should .only
one of the two bits show the card to be present, then
the system should instruct the user to re-insert the
card squarely into the socket.· Card detection can
also tell the system whether or not to redire.ct drives
in the case of system booting. CD1/2 is active low,
internally tied to ground.

Write Protection.
Byte-wide or Word-wide Selection
The flash memory card can. be read, erased, and
written in a. byte-wide or word 7wide mode. In the
word-wide configuration Vpasnd/oreE'1 .control
the LO-Byte while VpP2 and CE2 control the HI-Byte
(Ao= don't care).
Read, Write, and Verify operations are byte- or Wordoriented, thus zone independent. Erase Setup and
Begin Erase Commands are zone dependent such
that commands written to any address within a 256
kByte zone boundary initiate the.erase operation in
that zone (or two 256 kByte zones under word-wide
operation).
Conventional x8 operation uses CE1 active-low, with
CE2 high, to read or write data through the 00-07
only. "Even bytes" are. accessed whenAo is low,
corresponding t<;l the low byte of the complete x16
word. When Ao is high, the "odd byte" is accessed
. by transposing the high byte' of the complete x16
word onto the 00...;.07 outputs. This odd byte corresponds to data presented on 08-015 pins in x16
mode.
Note that two zones logically adjacent in x16 mode
are multiplexed through 00-07 in x8 mode and are
toggled by . the Ao address. Thus, zone specific
erase operations must be kept discrete in x8 mod.e
by addressing even bytes only for one-half of the
zone pair,· then addressing odd bytes only for the
other half.

The flash memory card features three types of write
protection. The first type features a mechanical
Write Protect Switch that disables the circuitry that
control Write Enable to the flash devices. When the
switch is activated, WE is forced high, which dis. abies any writes to the Command Register. The second type of write protection is based on the
PCMCIAlJEIOA socket. .Unique pin length assign7
ments· provide protective power supply sequencing
during hot insertion and removal. The third type op- .
erates via software control through the Command
Register when the card resides in its connector. The
Command Register of eaqh zone is only active when
VPP1/2 is at high voltage. Depending upon the application, the system designer may choose to make
VPP1/2 power supply switcllable-available only
when writes are desired. When VPP1,.2 0;= VPPL, the
c(mtents of the register default to the read command, making the iMC002FI-KA a read~only memory
. card. In this mode, the memory contents cannot be
.
altered. .
The syStem designer may chooseto leave VPP1j2 =
. VpPH, making the high voltage· supply constantly
available. In this case,.all Command Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO. (See the section on PQwer
Up/Down Protection.) The iMC002FLKA is deSigned
to accommodate either design practice, and to encourage optimization of the processor-memory card
interface.

4-36

IMC002FLKA

BUS OPERATIONS

Intelligent Identifier Command
The manufacturer- and device-codes can be read
via' the Command Register, for instances where the
iMC002FLKA .is erased and rewritten in a universal
reader/writer. Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the memory device code (SOH).

Read
The iMC002FLKA has two control functions, both of
which must be logically active, to obtain data at the
. outputs. Car!:! Enable (CEl is the power control and
should be used for h!9!l ~nd/or low zone(s) selection. Output Enable (OE) IS the output control and
, should ·be used to gate d~ta from the output pins,
independent of accessed zone selection. In the
byte~wide configuration, only one CE is rsiJired.
The word-wide cOnfiguration requires both CEs ac.
tive low. .,

Write'
Zone erasure and rewriting are accomplished via the
Command Register, when high voltage is applied to
Vpp1~.The contents ofthe register serve as input to
that zone's internal state-machine. The state-machine outputS dictate the function, of the targeted
zone.

When VPP1~ is high'(VPPH), t~e read operations can
be used to access zone data and to access data for
write/erase verification. When VPP1~ is low (Vppu,
only read accesses to the zone data are allowed;

The Command Register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the co'mmand.

OutlJut Pisable
With Output Enable at a logic-high level (VI H), output
from the card is disabled. Output pins are placed in a
high-impedance state. .

The Command Register is written by bringing Write
Enable to a logic-low level (VIU, while Card Enable(s) is/are 19W. Addresses are latched on the failing edge of Write ~nable, while data is latched on
the rising edge ~f the Write Enable pulse. Standard
microprocessOr write timings are used.

Standby
With one Card Enable at a logic-high leVel, the.
standby operation disables orie-half of the x16 output's read/write buffer. Further, only the zone correspondJr1g to the selected address within the upper or
lower CEv.z bank is active at a·time. (NOTE: A{J must
be low to select the low half of the x16 word when
CE2=1 and CE1 = 0.) All other zones are deselected, substantially reducing card power consumption; For deselected banks, the outputs are placed in
a high-impedance state, independent of the OiJtput
Enable signal If the iMC002FLKA is deselected during erasure, writing, or write/erase verification, the
accessed zone draws active current until the operation is terminated.

Refer to AC Write Charcteristics and the Erase/
Write Waveforms for specific timing parameters.

COMMA"D DEFINITIONS
When low voltage i~ applied to the Vpp pin(s), the
contents of the zone Command Register(s) default
to ·OOH, enablin~ read-,only operations.
Placing high voltage on the Vpp pin(s) enable(s)
read/write operations. Zorie operations are selected
by writing specific data patterns into the Command
Register. Tables 3 and 4 define these iMC002FLKA
regi"ter commands for both byte-wide and wordwide configurations, .
.
All commands written to the Command Register require that the zone address be v~lid or the incorrect
. zone will receive the· command. Any· Command/
Data Write .or Data Read· requires the correct valid
..
,
address.

4-37

infel·

IMC002FLKA

Table 2. Bus Operations
Pins

[1,7]
VPP2

[1,7]
VPP1

AO

CE2

CE1

8

VPPL
VPPl

VPPL Vn':
VPPL. . V,H

V,H

9

V,H

10

VPPL

VPPL

X

11

VPPL

VPPL

X

Notes

Operation·
Read (xS)

~
z Read (x8)

0

Q Read (x8)
0(
Read (x16)
1&1
II:

~
II:

Output Disable

VPPL

VPPL

X

Standby

VpPL

VPPL

X

Read (x8)

3,8

VPPX

Read (x8)

3,9

VPPH

Read (xS)

10

Read (x16)

3,11

~. Write (x8)

Q
0(

1&1

II:

OE

WE

Da-D15

Do-D7

V,L

V,L

V,H

Tri-state

Data Out-Even

V,L

V,L

V,H

Tri-state

Data Out-Odd

V,L

V,H

V,L

V,,·I

Data Out

Tri-state

V,L

V,L

V,H

Data Out

X

V,L
X

V,H

V,H

V,H
X

V,H 'Tri-state
X

Tri-state

Tri-state
Data Out-Even

Data Out
Tri-state

VPPH
Vppx

V,L

V,H

V,L

V,L

V,H

Tri-state

V,H

V,H

V,L

V,L

V,H

Tri-state

Data Out-Odd

VPPH

VPPX

X

V,L

V,H

V,L

V,H

Data Out

Tri-state·

VPPH

VPPH

X

V,L

V,L

V,L

V,H

Data Out

Data Out

VPPH
Vppx

V,L

V,H

V,L

V,H

V,L

Tri-state

Data In-Even

V,H

V,L

V,H

V,L

Tri-state

Data In-Odd

V,L

V,H

V,H

V,L

Data In

Tri-state

5,8

VPPX
VPPH

Write (x8)

9

Write (xS)

10

VPPH

VPPX

V,H
X

Write (x16)

11

VPPH

VPPH

'X

V,L

V,L

V,H

V,L

Data In

Data In

4

VPPH

VPPH

X

V,H

V,H

X

X

Tri-state

Tri-state

VPPH

VPPH

X

X

X

V,H

V,L

Tri-state

Tri-state

. Standby
Output Disable

NOTES:
1. Refer to DC Characteristics. When VPP1J2 = VPPL memory contents. can be read but not written or eras.ed.
2. Manufacturer and device codes may be. accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. Read Qperatioils with VPP1J2 = VPPH may access array data or the inteligent Identifier codes.
4. With VPP1/2 at high voltage, the standby current equals Icc + Ipp (standby).
.
5. Refer to Table 3 for valid Oata·ln during a write operation.
.
6. X can be VIL or V I H . ·
. .
7. Vppx = VPPH or VPPL.
S. This xS operation reads or writes the low byte of the x16 word on 000-7, i.e., Ao low reads "even" byte in xS mode.
9. This x8 operation reads or writes thelJigh byte of the x16 word on 000-7 (transposed from 000-15), i.e., Ao high reads
"odd" byte in xS mode.
10. This xS oPeration reads or writes the high byte of the x16 on 000-15. Ao is "don't care."
11. Ao is "don't care;" unused in x16 mode. High and low bytes are presented simultaneously.

4-38

infel·

IMC002FLKA

Table 3. Command Definitions Byte-Wide Mode
Command

Bus
First Bus Cycle
Second Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Addre88(2) Data(3)

Read Memory

2

1

Write

RA

OOH

IA

90HT

Read

ZA

20H

Write

Read Intelligent 10 Codes

4

3

Write

Set·up Erase/Eras~

5

2

Write

Erase Verify

5

2

Write

EA

AOH

Set-up Write/Write

6

2

Write

WA

40H

6

2

Write

WA

COH

2,7,8 . 2

Write

ZA

FFH

Write Verify
Reset

COmmand

ZA

20H

Read

EA

EVO

Write

WA

WO

Read

WA

WVO

Write

ZA

FFH

Table 4. Command Definitions Word-Wide Mode
I
,
Bus
First Bus Cycle
Second Bus Cycle
Notes Cycles
Req'd Operatlon(1) Addre88(2) Data(3) Operatlon(1) Addre88(2) Data(3)

Read Memory

2

1

Write

RA

OOOOH

Read Intelligent 10 Codes

4

3

Write

IA

9090H

Read

Set-up Erase/Erase

5

2

Write

ZA

2020H

Writ'e

ZA

2020H

Erase Verify

5

2

Write

EA

AOAOH

Read

EA

EVO

Set-up Write/Write

6

2

. Write

WA

4040H

Write

WA

WO

Write Verify

6

2

Write

WA

COCOH

Read·

WA

.WVO

2,7,8

2

Write

ZA

FFFFH

Write

ZA

FFFFH

Reset

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
RA = Read Address
.
WA= Address of memory location to be written.
ZA = Address of 256 kByte zones involved in erase or Reset operations.
Addresses are latched on the falling edge of the Write Enable pulse.
3. 10 = Data read from location IA during device Identification. (Mfr = 89H, Device = BDH).
. EVD = Data read from location EA during erase verify.
WD = Data to be written at location WA. Data is latched on the rising edge of Write Enable.
WVD = Data read from locetlon WA during write verify. WA Is latched on the Write command.
4. Following the Read Intelligent 10 command, two read operations access manufacturer and device codes.
5. Figure 5 Illustrates the Erase Algorithm.
.
6. Figure 6 Illustrates the Write Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8. The Reset command operates on a zone basis. To reset the entire card requires reset write cycles to ea~h zone.

4-39

infel .

IMC002FLKA

tents are protected against erasure. Refer to AC
Erase Characterstics and Waveforms for specific
'
timing parameters.

Read Command
While VPP1.1.! ,is high, for erasure and writing, zone
memory contents ,can be accessed via the read
command. The, read operation is initiated by writing
OOH (OOOOH for the word-wide configUration) into the
zone Command Register(s). Microprocessor read
cycles retrieve zone data. The accessed zone remains enabled for reads until the Command Registeres) contents are altered.'
,

Erase-Verify Command
,

The erase command erases all of the bYtes of the
zone in parallel. After each erase operation, all bytes
in the zone must be individually verified. In bytemode, operations, zones are segregated, by Ao in
odd and even banks; ,erase and erase verify operations must be done in complete passes of evenbytes-only then odd-bytes-only. Seethe Erase Algorithmfor byte-wiele mode. The erase verify operation
is initiated by writing AOH (AOAOH for word-wide) into
the Command Register(s). The address for the
byte(s) to, be verified must be supplied as it is
latched on the falling edge of the Write Enable
pulse. The register write terminates the erase operation with the rising edge of its Write Enable pulse.

The default contents of each zone's register(s) upon
VPP1j2 power-up is OOH (OOOOOH for word-wide).
This default value ensures that no spurious alteration of memory card contents occurs during the
VPP1.1.! power transition. Where'the VPP1.1.! supply is
left at VPPH, the memory' card powers-up and remains enabled for reads until the command Register,
contents of targeted zones are changed. Refer to '
the AC 'Read Characteristics and Waveforms for
'
specific timing parameters.

The enabled zone applies an internally-generated
margin voltage to the addressed byte. ~eading FFH
from the addressed bYte indicates that all bits in the
byte are erased. Similarly, reading FFFFH from the
addressed word indicates that all bits in the word are
erased.'
','

Intelligent Identifier Command
Each zone of the iMC002FLKA contains an Intelligent Identifier to identify memory card device characteristics. The operation is initiated by writing 90H
(9090H for word:'wide) into the Command Registeres) with zone address. Following the command
write, a read cycle from address OOOOOH retrielies
the manufacturer code 89H (8989Hfor,word-wide).
A read cycle from address 0002H returns the device
code BOH (BOBOH for word-wide). To terminate the
operation, it'is necessary to write another'valid command into the register(s).

Set-up Erase/Erase Commands
Set~up

Erase stages the targeted zone(s) for electrical erasure of all bytes in the zone. The set-up erase
operation is performed by writing 20H to the Command Register (2020H for word-wide) with zone'address.'
,
'
To commence zone-erasure, the erase command
(20H or 2020H) must again be written to the regist~r(s) with zone address. The erase operation begins
with the rising edge of the Write-Enable pulse and
terminates with the rising edge of the neXt Write-Enable pulse (i.e., Erase-Verify Command with zone
address).

The erase~verify command must be written to the
Command Register prIor to each byte (word)veriflcation to latch its ,address. The process continues,
for each byte (word) in thezone(s) until a,byte (word)
does not return FFH (FFFFH) data, or the last address is accessed.
',
,,'
In the case where the data read is not FFH (FFFFH),
another eraseopetation is performed. (Refer to Setup Erase/Erase.) Verification then resumes from the
address of, the last-verified byte (word). Once all
bytes (words) in the zone(s), have been verified, the
erase step is complete. The accessed zone can now
be written. At this point, the verify operation is terminated'by writing a valid command (e.g., Write ,Setup) to the Command Register: The Erase algorithms
for byte-vyid!3 :and word-wide configurations illustrate
" how commands and bus operations are combined to
perform electrical erasure of the iMCC002FLKA. Re"
fer to AC Erase Characteristics and Waveforms for
specific timing parameters.
"

Set-up Write/Write Commands
Set-up write is a command-only operation that
stages the' targeted zone for byte writing., Writing
40H (4P40H) into the Command Register(s). performs the set-up operation.

This two-step sequence ohet-up followed by execution ensures that zone memory contents are not accidentally' erased., Also, zone-erasure can only occur
when high voltage is applied to the VPP1.1.! pins. In
the absence of this highlloltage, zone memory con-

4-40

IMC002FLKA

Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched Qn the rising edge of
the Write Enable pulse. The rising edge of Write Enable also begins the write operation. The write operation terminates with the next rising edge of Write
Enable, which is used to write the verify command.
Refer to AC Write Characteristics and Waveforms
for specific timing parameters.

two consecutive writes of FFH (FFFFH for wordwide) will safely abort the operation. Zone memory
contents will not be altered. A valid command must
then be written to place the accessed zone in the
desired state. '

EXTENDED ERASE/WRITE CYCLING

Write Verify Command
The iMC002FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur'
sequentially or at random. Following each write operation, the byte or word just written must be verified.
The write-verify operation is initiated by writing COH
(COCO H) into the Command Register(s) with correct
address. The register write(s) terminate(s) the write
operation with the rising edge of its Write Enable
pulse. The write-verify operation stages the accessed zone(s) for verification of the byte or word
last written. The Ione(s) apply(ies) an internally-generated margin voltage to the byte or word. A microprocessor read cycle outputs the data. A successful
comparison between the written byte or word and
true data means that the byte or word is successfully
written. The write operation then proceeds to the
next desired byte or word location. The Write algorithms for byte-wide and word-wide configurations illustrate how commands are combined with bus operations to perform byte and word writes. Refer to AC Write Characteristics and Waveforms for specific
timing parameters.
.

Reset Command

a

A reset command is provided as means to safely
abort the erase-, or write-command sequt;lnces. Following either set-up command (erase or write) with

Intel has deSigned extended cycling capability into
its ETOX II flash memory technology enabling a
flash memory card with a MTBF that is approximately 20 times more reliable than rotating disk technology. Resulting improvements in cycling reliability
come without ,increasing memory cell size or complexity. First, an advanced tunnel oxide increases
the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric
field minimizes the probability of oxide defects in the
region. The lower.electric field greatly reduces oxide
stress and the probability of failure.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10 ,..,S
duration. Each operation is followed by a byte or
word verification to determine when the addressed
byte or word has been successfully written. The algorithm(s) allows for up to 25 write operations per
byte or word, although most bytes and words verify
on the first or second operation. The entire sequence of writing and byte/word verification is per'
formed with Vpp at high voltage.

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zone(s).
Erasure begins with a read of memory zone contents. Reading FFH(FFFFH) data from the accessed zone(s) can be immediately followed by writing to the desired zone(s).
.

4-41

intel·

IMC002FLKA

For zones being erased and rewritten, uniform and
reliable erasure is ensured by first writing all bits in
the accessed zone to their charged state (data =
OOH byte-wide, OOOOOH word-wide) . .This is accomplished~ using the write algorithm, in approximately
four seconds per zone.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH byte-wide,
FFFFH word-wide) begins at address OOOOOH and
continues through ,the ,zone to the last address, or
until data other than FFH (FFFFH) is encountered.

(Note: byte;wide erase operation requires separate
even- and odd-address passes to handle the individual256 kByte zones.) With each erase operation, an
increasing number of bytes or words verify to the
eiased sUite. Erase efficiency maybe improved by
storing the address of the last byte or word verified
in a register(s). Following the next erase operation,
verification starts at the stored address location. Follow this procedure until all bytes in the zone are
erased. Then, re-start the procedure for the next
zone or word-wide zone pair. Erasure typically oc- .
curs in two seconds per zone.

INITIALIZE SIZE
AND NUMBER OF ZONES
ZONE L= 0
ZONE H = I

290412-3

Figure 3. Full Card Erase Flow

4-42

intel .

IMC002FLKA

Bus
Operation

Command

Standby

Comments
Wait for Vpp ramp
to VpPH (= 12.0V) (2)
Initialize pulse-count

Write

Write

+

Set-up

Data = 40H

Write

Valid Address

Write

Valid address/data

Standby

Duration of Write
operation (tWHWH1)

Write

Data = COH + Valid Address;
Stops(4) Write Operation

Write(3)
Verify

Standby

tWHGL

Read

Read byte to verify Write
Operation at Valid Address

Standby

Compare data output
to data expected

Write

Data = OOH, resets the

Read

register for read
operations.
Standby

Wait for Vpp ramp
to VPPL(2)

,'

I

290412-4

)

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and
VPPL·

3. Write Verify is only performed after a byte write operation. A final read/compare may be performed (optional) after the register is written with the Read command.
4. Refer to principles of operation.

Figure 4. Write Algorithm for Byte-Wide Mode

4·43

intele

IMC002FLKA

Bus
Operallon

Comments

COmmand

Standby

Wait for Vpp ramp to VPPH (= 12.0V)(2)

Use with Write Operation Algorithm
InHialize even/odd Addresses. Erase Pulse
Width. and Pulse Count

Write

Set·up
Erase

Data = 20H

+ Address

Write

Erase

Data = 20H

+ Addrass

Standby

Write

Duration of Erase operation (tWHWH21

Erase
Verify(3)

Addr = Byte to verily;
Data = AOH; Stops

Standby

Erase Operalion(4) twHGL

Read

Read byte to verify erasure at address

Standby

Compares output to FFH increment pulse
count

,

Write

Standby

Read

Data = ~OH. resets the register for read
operations.
WaitforVpp ramp to VPPL(2)
..

290412-5

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and

3. Erase Verify is only performed after a chip erasure. A
final read/compare may be performed (optional) after
the register is written with the Read command.
4. Refer to principles of operation.

VPPL·

Figure 5. Erase Algorithm for Byte-Wide Mode

4-44

infel·

iMC002FLKA

Comments

Wait for Vpp ramp to VPPH
AORS = address to write
W_OAT = data word to write
Initialize Data Word Variables:
V_OAT = valid data
W_COM = Write Command
V_COM = Write Verify Command
PLSCNT.-HI = HI Byte Pulse Counter
PLSCNT_LO = LO Byte Pulse Counter
FLAG = Write Error Flag
Write Set-up Command
Address needs to be Valid
Write
.

PLSCNLHI,= 0
PLSCNLLO=O
FLAG 0

=

High/Low Byte
Compore It Mask
Subroutine

See Write Verify and Mask Subroutine
Write Verify Command

F_OAT

"
= flash
memory data

Compare flash memory data to valid data
(word compare). If not equal, check for
Write Error flag. If Flag not set, compare
High and Low Bytes In the Subroutine•.

Check buffer of 110 port for more data to write

Reset device for read operation
TumoffVpp

•
290412-6

Figure 6. Write Algorithm for Word·Wlde Mode

4·45

int'el.,

iMC002FLKA

Comments

To look at the LO Byte,
Mask" the HI Byte with
00
LOAT = (V_OAT OR OOFFH)
OR OOFFH)
V_COlA = (V _COlA OR OOFFH)

w_Cot.. = (W _COlA

If the LO Byte verifies,
mask the LO Byte
commands with the reset
command (FFH)
If the LO Byte does not
verify, then increment its
pulse counter and check
for max count
FLAG = 1 denotes a LO
Byte error
Repeat the sequence for
the HI Byte

LOAl = (LOAT OR FFOOH)
W_COlA = (W _COlA OR FFOOH)
LCOIA = (LCOIA OR FFOOH)

FLAG = 2 denotes a HI
Byte error
FLAG = 3 denotes both
a HI and LO Byte errors.
Flag = 0 denotes no
max count errors;
continut? with algorithm.

290412-7

• Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_OAT), the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 7. Write Verify and Mask Subroutine for Word-Wide Mode

4-46

IMC002FLKA

Comments

Wait for Vpp to stabilize.

Use Write operation algorithm in x8 or x16
configuration

Initialize Variables:
iNITIALIZE:
PLSCNT _Hi = 0
PLSCNLLO=O
ADRS = 0

PLSCNT_HI ~ HI Byte Pulse Counter
PLSCNT_LO = LO Byte Pulse Counter
FLAG = Erasure error flag
ADRS = Address
LCOM = Erase Command
V_COM = Verify Command

=

FLAG 0
E-COt.4 = 2020H
LCOt.4=AOAOH

Erase Set-up Command
Start Erasing

Duration of Erase Operation

Erase Verify Command stops erasure
See Block Erase Verify & Mask Subroutine

y

When both devices at ADR!; are erased, F_
DATA = FFFFH.lf not equal, increment the

pulse counter a,nd check for last pulse
Reset commands default to
(LCOM = 2020H) (V_COM = AOAOH)
before verifying next ADRS

Reset device for read operation
TumoffVpp

290412-8

NOTE:
X16 Addressing uses A1-A20 only. Ao = 0 throughout word-wide operation.

Figure.S. Erase Algorithm for Word-Wide Mode

4-47

in1eL

iMC002FLKA

Comments
This subroutine reads the data
word (F_DATA). It then masks
the. HI or lO Byte of the Erase
and Verify commands from
executing during the next
operation.
If both HI and lO Bytes verify.
then return.
Mask' the HI Byte with OOH.

E_COM = (E_COM or OOffH)
LCOM = (LCOM or OOffH)

If the lO Byte verifies erasure.
then mask' the next erase and
verify commands with FFH
(RESEn.

If the lO Byte does not verify.
then increment its pulse counter
and check for max count. FLAG
= 1 denotes a LO Byte error.

Repeat the sequence for the HI
Byte.
CCOM = (E_COM or FFOOH)
LCOM = (LCOM or FfOOH)
Flag = 2 denotes a HI Byte error.
Flag = 3 denotes both a HI and
lO Byte errors. FLAG = 0
denotes no maX count errors;
continue with algorithm.

290412-9

"Masking can easily and efficiently be done in assembly languages. Simply loael word registers with the incoming data
(F_DAn. the program commands and the verify commands. Then manipulate the HI orlO register contents.

Figure 9. Erase Verify and Mask Subroutine for Word-Wide Mode

4-48

intaL

IMC002FLKA

The card connector should also have a 4.7 ,.,.F electrolytic capacitor between Vee and Vss, as well as
between VPP1IVPP2 and Vss. The bulk capacitors
will overcome voltage slumps caused by printed-circuit-board trace inductance, and will supply charge
to the smaller capacitors as needed.

SYSTEM DESIGN CONSIDERATIONS··
Three-Line Control
Three-line control provides for:
a. the lowest possible power dissipation and.
b. complete assurance that output bus contention
will not occur.

Power Up/Down Prot,ectlon
The PCMCIA/JEIDA socket is specified, via unique
Pin lengths, to properly sequence the power supplies to the flash memory card. This assures that hot
insertion and removal will not result in card damage
or data loss.

To efficiently use these three control inputs, an address-decoder output should drive CE1. ~hile the
system's Read signal controls the. card OE signal,
and other parallel zones. This, coupled with the internal zone decoder, assures that only enabled
memory zones have active outputs, while deselected zones maintain the low power standby condition.

Power-Supply Decoupllng

Each zone in the iMC002FLKA is designed to offer
protection against accidental erasure or writing,
caused by spurious system-level signals that may
exist during power transitions. The card will powerup into the read state.

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues-standby, active and transient cu~nt peaks, produced by
falling and rising edges of CE1;2. The capacitive and
inductive loads on the card and internal flash memory zones determine the magnitudes of these peaks.

A system designer must guard against active writes
for Vee vol~es above VLKO when Vpp is active.
Since both WE and CE1 2 must be low for a command write, driving either to VIH will inhibit writes.
With its control register architecture, alteration of
zone contents only occurs after successful completion of the two-step command sequences.

Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC002FLKA features on-card ceramic decoupling
capacitors connected between Vee and Vss, and
between VPP1IVPP2 and Vss.

While these precautions are sufficient for most applications, it is recommended that Vee reach its steady
state value before raising VPP1;2 above Vee + 2.0V.
In addition, upon powering-down, VPP1;2 should be
below Vee + 2.0V, before lowering Vee.

4-49

infel .

IMC002FLKA

Absolute Maximum Ratings·

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read .................. O·C to '+ 60·C(1)
During Erase/'vVrite .............. O°c. to + 60°C

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratll1g5" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
.

Temperature Under Bias ......... -10·Cto +70·C
Storage Temperature ............ - 30·C to + 7Q·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
VPP1IVpP2 Supply Voltage with
Respect to Ground
During Erase/Write ....... - 2.0V to + 14.0V(2, 3)

Vec Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -O.SV. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + O.SV, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC input voltage on VPP1IVPP2 may overshoot to + 14.0V for periods less than 20 ns.

OPERATING CONDITIONS
Symbol
TA
Vee
VPPH
VPPL

Limits

Parameter
Operating Temperature
Vee Supply Voltage
. Active VPP1,VPP2
Supply Voltages
Vpp During Read Only
Operations

Min

Max

0

60

Unit

. Comments

. ·C

For Read-Only and
Read/Write Operations

4.75

5.25·

V

11.40

12.60

V

0.00

6.50

V

DC CHARACTERISTICS-Byte Wide Mode
Symbol
III
I·ILO
lecs

Parameter

Notes

Limits
Min

Typical

Max

Unit

Test Conditions

Input Leakage Current

1

±1.0

±20

p.A

Vee = Vee max
VIN = VeeorVss

Output Leakage Current

1

±1.0

±20

p.A

Vee = Vee max
VOUT = Vee or Vss

Vee Standby Current

1

0.4

0.8

rnA

Vee = Vee max
CE1 = CE2 = Vee ±0.2V

4

7

rnA

Vee = Vee max
CE1 = CE2 = VIH

25

50

rnA

Vee = Vee max CE = VIL
f = 6 MHz, lOUT = 0 rnA

lec1

Vee Active Read Current

1,2

lec2

Vce Write Current

1,2

5.0

15.0

rnA

Writing in Progress

ICC3

Vee Erase Current

_ 1,2

10.0

20.0

rnA

Erasure in Progress

leC4

Vee Write Verify Current

1,2

10.0

20.0

rnA

Vpp =VPPH
Write Verify in Progress

...

4-50

intet

IMC002FLKA

DC CHARACTERISTICS-Byte Wide Mode (Continued)
Symbol

Parameter

Notes

Limits
Min

1,2

Typical

Max

10.0

20.0

Unit

Test Conditions

lees

Vee Erase Verify Current

Ipps

Vpp Leakage Current

IpP1

Vpp Read Current
or Standby Current

1,3

0.4

IpP2

Vpp Write Current

1,3

B.O

30

mA

Vpp = VpPH
Write in Progress

IpP3

Vpp Efase Current

1,3

10

30

mA

Vpp = VpPH
Erasure in Progress

IpP4

Vpp Write Verify Current

1,3

2.0

5.0

mA

Vpp = VPPH
Write Verify in Progress

Ipps

Vpp Erase Verify Current

1,3

2.0

5.0

mA

Vpp = VpPH
Erase Verify in Progress

1

mA

Vpp = VpPH
Erase Verify in Progress

±BO

J£A

Vpp

O.B

mA

Vpp> Vee

±O.OB

Vpp

,

s
s

Vee

Vee

VIL

Input Low Voltage

-0.5

O.B

V

VIH

Input High Voltage

2.4

Vee ± 0.3

V

VOL

Output Low Voltage

0.40

V

IOL = 3.2mA
Vee = Vee min

VOH1

Output High Voltage

3.B

V

IOH = -2~OmA
Vee = Vee min

VPPL

Vpp During Read-Only
Operations

0.00

6.5

V

Note: Erase/Write are
Inhibited when Vpp = VPPL

VPPH

Vpp During Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock
Voltage

2.5

V

NOTES:
1. All currents are. in RMS unless otherwise noted. Typical values at Vee = S.OV. Vpp = 12.0V, T = 25°C.
2. 1 chip active and 7 in standby for byte-wide mode.
3. Assumes 1 Vpp is active.

DC CHARACTERISTICS-Word Wide Mode
Symbol

Parameter

Limits

Notes
Min

Unit

Typical

Max

Test Conditions

III

Input Leakage Current

1

±1.0

±20

J£A

Vee = Vee max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±1.0

±20

J£A

Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

0.4

0.8

mA

Vee = Vee max
CE1 =
= Vee ±0.2V

4

7

mA

ru

Vee = Vee max
VIH

CE1 = CE2 =
4-51

-

inY~

iMC002FLKA

DC CHARACTERISTICS-Word Wide Mode (Continued)
Symbol

Parameter

Limits

Notes

•• 1-

.Wlill

Typical

Max

Test Conditions

Unit

lee1

Vee Active Read Current

1,2

40

BO

mA Vee = Vee max CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Write Current

1,2

7.0

25

mA Writing in Progress

lec3

Vcc Erase Current

1,2

15

30

mA Erasure in Progress

lee4

Vec Write Verify Current

1,2

15

30

mA Vpp = VPPH
Write Verify in Progress

lecs

Vee Erase Verify Current

1,2

10

30

mA Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±BO

/LA

1.6

mA

IpP1

Vpp Read Current

1
1,3

0.7

±0.16

or Standby Current
IpP2

Vpp Write Current

1,3

Vpp:5': Vee
Vpp

> Vee

Vpp:5': Vee·

16

.60

mA

Vpp';" VPPH
Write in Progress
Vpp = VPPH
Erasure in Progress

/

IpP3

Vpp Erase Current

1,3

20

60

mA

IpP4

Vpp Write Verify Current

1,3

5.0

12

mA Vpp = VPPH
Write Verify in Progress

Ipps

Vpp Erase Verify Current

1,3

5.0

12

mA Vpp = VPPH
Erase Verify in Progress

,

VIL

Input Low Voltage

-0.5

O.B

V

VIH

Input High Voltage

2.4

Vee ± 0.3

V

VOL

Output Low Voltage

0.40

V

IOL = 3.2 mA
Vee = Vee min

VOH1

Output High Voltage

3.B.

V

IOH = -2.0mA
Vec = Vec min

VpPL

Vpp During Read-Only
Operations

0.00

6.5

V

Note: Erase/Write are
Inhibited when Vpp =. VPPL

VPPH

Vpp During Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock
Voltage

2.5

V

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee
2. 2 chips active and 6 in standby for word-wide mode.
3. Assumes 2 VpPS are active.

4-52

= S.OV, Vpp = 12.0V. T = 2S'e.

intel~

iMC002FLKA

CAPACITANCE T
Symbol

=

25°C, f = 1.0 MHz

Parameter

Notes

Limits
Min

Max

Unit

Conditions

CIN1

Address Capacitance

40

pF

VIN = OV

CIN2

Control Capacitance

40

pF

VIN = OV

COUT

Output Capacitance

40

pF

VOUT = OV

CliO

1/0 Capacitance

40

pF

VIIO = OV

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................. VOL and VOH1
Input Timing Reference Level .......... VIL and VIH
Output Timing Reference Level ........ VIL and VIH

AC CHARACTERISTICS-Read-Only Operations
Symbol

Characteristic

Notes

. Min

2

200

Max

Unit

tAvAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

2

200

ns

tAVQV/tAcc

Address Access Time

2

200

ns

tGLQV/tOE

Output Enable Acces.s Time

2

tELQx/tLZ

Chip Enable to Output
in LowZ

2

tEHQZ

Chip Disable to Output
in High Z

2

tGLQX(tOLZ

Output Enable to Output
in LowZ

2

tGHQZ/tDF

Output Disable to Output
in HighZ

2

toH

Output Hold from Address,
CE, or OE Change

tWHGL

Write Recovery Time
before Read

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time ~ 10 ns.

4-53

ns

100

ns
ns

5
60
5

ns
ns

60

ns

1,2

5

ns

2

6

IJos

infel .

IMC002FLKA

Vee POWER-UP!
STANDBY

AOOR~S~

'\J\.J\XJ\J\J\J.f

DEVICE AND
ADDRESS SEltCTION

OUTPUTS ENA'LED

DATA VALID

-II

)KvXvXVXVXyXVX\lX1.F____________________A_DM_~_S_~~A-k-[--------------__S!~-----'1L-~~~~~~~
I------------'..A'(...,)------------I

....OL+-----I

+ ______________

DATA (00) _____...:;.::::'G.::.%::....____

5~:
ov

~

VAUD OUTPUT

J

\.

290412-10
NOTE:

CE refers to GEl,

2.

Figure 10. AC Waveforms for Read Operations

4-54

infel·

IMC002FLKA

AC CHARACTERISTICS-For Write/Erase Operations
Symbol

Characteristic

Notes

Min

Max

Unit

tAVAV/tWC

Write Cycle Time

1,2

200

ns

tAVWL/tAS

Address Set-up Time

1,2

0

ns

tWLAX/tAH

Address Hold Time

1,2

100

ns

tOVWH/tOS

Data Set-up Time

1,2

80

ns

tWHOX/tOH

Data Hold Time

1,2

30

ns

.tWHGL

Write Recovery Time before Read

1,2

6

,...s

tGHWL

Read Recovery Time before Write

1,2

0

,...s

tWLOZ

Output High-Z from Write Enable

·1,2

5

ns

tWHOZ

Output Low-Z from Write Enable

1,2

tELWL/tcs

Chip Enable Set-up Time before Write

1,2

tWHEH/tcH

Chip Enable Hold Time

tWLWH/tWP
tWHWL/tWPH

60

ns

40

ns

1,2

0

ns

Write Pulse Width

1, :2

100

ns

Write Pulse Width High

1,2

20

ns

tWHWH1

Duration of Write Operation

1,2,3

10

,...s

tWHWH2

Duration of Erase Operation

1,2,3

9.5

ms

tvPEL

Vpp Set-up Time
to Chip Enable Low

1,2

100

ns

NOTES:
. 1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to A.C. Characteristics for Read-Only Operations.
2. Rise/Fall time s: 10 ns.
3. The integrated stop timer terminates the write/erase operations, thereby eliminating the need for a maximum specifiction.

ERASE/WRITE PERFORMANCE
Parameter

Notes

Zone Erase Time
Zone Write Time
MTBF

Typ

Max

Unit

1,3,4

2.0

30

sec

1,2;4

4.0

25

sec

5

106

Min

Hrs

NOTES:
1. 25'C, 12.0V Vpp.
2. Minimum byte writing time excluding system overhead is 16 ,."S (10 ,."S program + 6 ,."S write recovery), while maximum is
400 ,."s/byte (16,."s x 25 loops allowed by algorithm). Max chip write time is specified lower than the worst case allowed by
the write algorithm since most bytes write significantly faster than the worst case byte.
3. Excludes OOH writing Prior to Erasure.
4. One zone equals 256 kBytes.
.
5. MTBF - Mean Time between Failure, 50% failure point for disk drives.

4-55

IMCOO2FLKA

Vee I'OWER-:'UP I:
STANDBY

.........

SET-UP WRITE

WII11t
YERIfY

WRIlE,COMIllAND.
LATCH ADDRESS a DATA

WlI1IIIG

........

vee

STANDBYI
POWER~DOW'"

ADDRESSES

Of (0)

liE (W)

••T•.(DO).

'.,5.0Y
Vee

OV

lZ.0V
Vpp

V....

290412-11

NOTE:

~ refers to Ci:1, 2.

FlgLire 11. AC Waveforms for Write Operations

4-56

intel .

IMC002FLKA

Vcc POWER-UP a

sa-up ERASE

STANDBY

COMMAND

ERASE
ERASE COWWAHD

. ERASINO

VERIFY
CONWAHD

ERASE
V[II:lrlCATIOH

STANDBY/
Vcc POWER-OOWN

ADDRESSES

Of (0)

WE (W)

DATA (DQ)

5.DV

Vee
OV

V__
12.0V

VPPL

290412-12

NOTE:
CE refers to CE1, 2.

Figure 12. AC Waveforms for Erase Operations

4-57

intel"

IMC002FLKA

ALTERNATIVE CE-CONTROLLED WRITES
Symbol

Characteristic

Notes

Min

Max

Unit

tAVAV

Write Cycle Time

tAVEL

Address Set-up Time

tELAX

Address Hold Time

tOVEH

Data Set-up Time

80

ns

tEHoX

Data Hold Time

30

ns

tEHGL

Write Recovery Time before Read

6

,""S

tGHEL

Read Recovery Time before Write

0

,""S

tWLEL

Write Enable Set-Up Time
before Chip-Enable

0

ns

tEHWH

Write Enable Hold Time

0

ns

tELEH

Write Pulse Width

100

ns

tEHEL

Write Pulse Width High

20

ns

tpEL

Vpp Set-up Time
to Chip Enable Low

100

ns

1

200

ns·

0

ns

100

ns

NOTES:
1. Chip Enable Controlled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable. In
systems where Chip Enable defines the write pulse width (with a longer Write Enable timing waveform) all set-up, hold and
inactive Write Enable times should be measured relative to the Chip Enable waveform.

intel .

iMC002FLKA

PROGRAW

Vee POWER-UP I:

SET-UP PROGRAM

STANDBY

COMMAND

PROGRAM CO....AND
LATCH ADORESS I: DATA

YERln
PROCRANWING

CO.......ND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

290412-13

NOTE:

CE refers to CEl, 2.
Figure 13. Alternate AC Waveforms for Write Operations·

4-59

intel·

IMC002FLKA

ORDERING INFORMATION
II liIMlciblo.iIFltlk'AI
I islBlxlxlxlxlxl
..

IL~"

IDENTIF'IER
A '= REVISION

=

K' WORD-WIDE
ARCHITECTURE

\

F'L= F'LASH
002 = 2 MEGABYTE
DENSITY IN MEGABYTES
MC

=MEMORY CARD

I = INTEL
PACKA,GE PLACEHOLDER

ADDITIONAL INFORMATION
ER-20. "ETOX II Flash Memory Technology"
RR-60. "ETOX II Flash Memory Reliability Data Summary"
AP-343. "Solutions for High Density Applications using Flash Memory"
RR-70. "Flash Memory Card Reliability Data Summary"

290412-14

ORDER NUMBER
294005
293002
292079'
293007

REVISION HISTORY
Number
-002

Description
- Removed Preliminary
.... Removed ExCA Compliance Section
- Clarified need for Valid Address du'ring commands
- Corrected Vpp = VPPH in Erase Algorithm
- Increased ICC2-ICC5 D.C. current sp~cs for both Byte Wide and Word Wide modes
- Revised and Updated Application Section discussion
- Changed order number

4-60

iMC004FLKA
4-MBYTE FLASH MEMORY CARD
Nonvolatility (Zero Retention
• Inherent
Power)

•
•
•
•

•

Write Protect Switch to Prevent
• Accidental
Data Loss
Command Register Architecture for
• Microprocesssor/Microcontrolier
Compatible Write Interface
II Flash Memory Technology
• -ETOXTM
5V Read, 12V Erase/Write

- No Batteries Required for Back-up
Over 1,000,000 Hours MTBF
- More Reliable ,than Disk
High-Performance Read
- 200 ns Maximum Access Time
CMOS Low Power Consumption
- 40 mA Typical Active Current (XS)
- SOO ,..,A Typical Standby Current
Flash Electrical Zone-Erase
- 2 Seconds Typical per 256 kByte
Zone
- Multiple Zone-Erase
Random Writes to Erased Zones
-10 ,..,s Typical Byte Write

- High-Volume Manufacturing
Experience
6S-Pin Standard
• -PCMCIA/JEIDA
Byte- or Word-wide Selectable
Software Hardware
• Independent
Vendor Support
&

-Integrated System Solution Using
Flash Filing Systems

Intel's iMC004FLKA Flash Memory Card is the removable solution for storing and transporting important user
data and application code. The combination of rewritability and nonvolatility make the Intel Flash Memory Card
ideal for data acquisition and updatable firmware applications. Designing with Intel's Flash Memory Card
enables OEM system manufacturers to produce portable and dedicated function systems that are higher
performance, more rugged, and consume less power.
The iMC004FLKA conforms to the PCMCIA1.0 international standard, providing standardization at the hardware and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the memory
card's address OOOOOH with a fo~mat utility. This information provides data interchange functional capability.
The 200 ns access time allows for "execute-in-place" capability, for popular low-power microprocessors.
Intel's 4-MByte Flash Memory Card operates in a byte-wide and word-wide configuration providing performance/power options for different systems.
Intel's Flash Memory card employs Intel's ETOX II Flash Memories. Filing systems, such as Microsoft's· Flash
File System (FFS), facilitate data file storage and card erasure using a purely nonvolatile medium in the DOS
environment. Flash filing systems, coupled with the Intel Flash Memory Card, effectively create an all-silicon
. nonvolatile read/write random access memory system that is more reliable and higher performance than diskbased' memory systems.

• Microsoft is a trademark of Microsoft Corp.
ExCA1M is a trademark of Intel Corp~rporation.

4-61

October 1992
Order Number: 290388-003

iMC004FLKA

I'y;

54.0:1: 0.1 mm

I,

r-T

'I

r-

~

3.3:1: 0.1 mm

r,

,,~

E
E

..'"
N

0

.;

E

"'

E

,5

5

.E:>!

.E:>!

q

q

0

0

tl

J1:

I

1

gpooooooooooooooooooooooooooooooSg
00000000000000000000000000000000
68

/-

I

FRONT SIDE

34 •

t

\.:

l J

35

BACK SIDE

2903118-1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

GND
D3
D4
D5
De
D7
CE1
Al o

DE
A11
Ae
Aa
A13
A14
WE
NC
Vee

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

VPPl
Ale
A15
A12
A7
A6
A5
A4
A3
A2
A1
Ao
Do
D1

-

D2
WP
GND

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

GND
CDl
D11
D12
D13
D14
D15
CE2
NC
NC
NC
A17
Ala
Ale
A20
A21
Vee

NOTES:

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

VPP2
NC
NC
NC
NC
NC
NC
NC
NC
REG1
BVD22
BVD12
Da
De
DlO
CD2
GND

1. REG = register memory select = No Connect (NC), unused. When REG is brought low, PCMCIAlJEIDA standard
card information structure data is expected. This is accomplished by formatting the card with this data.
2. BVD = battery detect voltage = Pulled high through pull up resil?tor.
Figure 1.IMC004FLKA Pin Configurations

4-62

intel~

IMC004FLKA

Table 1. Pin Description
Symbol

Type

Ao-A21

I

00- 0 15

lID

Name and FLinctlon
ADDRESS INPUTS for memory locations. Addresses are internally
latched during a write cycle.

DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the card is deselected or the outputs
are disabled. Data is internally latched during a write cycle.

CE1, CE2

I

CARD ENABLE: Activates the card's high and low byte control ~ic,
input buffers, zone decoders, and associated memory devices. CE is
active low; CE high deselects the memory card and reduces power
consumption to standby levels.

DE

I

WE

I

OUTPUT ENABLE: Gates the cards output through the data buffers
during aJead cycle. DE is active low.

WRITE ENABLE controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse.
NOTE:
With Vpp

.~

6.SV, memory contents cannot be altered.

VPP1, VPP2

ERASE/WRITE POWER SUPPLY for writing the command register,
eraSing the entire array, or writing bytes in the array.

Vee

DEVICE POWER SUPPLY (SV ±S%).

GNO

GROUND

COl, CO2

0

CARD DETECT. The card is detected when COl and C02 = ground.

WP

0

WRITE PROTECT. All write operations are disabled with WP = active
high.

NO INTERNAL CONNECTION to device. Pin may be driven or left

NC

floating.
BV01, BVD2

0

BATTERY VOLTAGE DETECT. NOT REQUIRED.

4-63

intel~

iMC004FLKA

=-~
W~

~.

-

CE!VERS
AND
BUFFERS
WP

I

VIE
OE

'~~,
0-0-0
I
I

I
I

• _- ""-- WRITE PROTECT
SWITCH
AO-A 17
AD
A1-A21

ADDRESS
BUFFERS
AND·
DECODERS

CE2
CE 1

CEH O-CEH 3
CELO-CEL3

28F020
~

AO-Al i

f-CE
REG

---

r- WE

~
-

f-OE

CD 1

00 -07

ZO

-

JI I
.

BDV 1

Z1

Vss Vee VpP2

00-07

-

Z2

Vss Vee VpP1

I

BVD

r-

f-OE

~ Ao-A 17

f-CE
f- WE
I-OE

~ AO-A17 08-0 15

f-CE

r- WE

Vss Vee VpP1

CARD DETECT

28F020

I

I

•
••

JJ1
~ Ao-A17 08-0 15

f-CE
f- WE
rOE

r

Z3

Vss Vee VpP2

I

I

I

•
•

•

Vee
BATTERY VOLTAGE
DETECT

GND
Ve
VpP1
Vp
290388-2

Figure 2. iMC004FLKA Block Diagram

4-64

intel·

IMC004FLKA

APPLICATIONS
The iMC004FLKA Flash Memory Card allows for the
storage of data files and application programs on a
purely solid-state removable medium. System resident flash filing systems, such as Microsoft's Flash
File System, allow Intel's ETOX II highly reliable
Flash Memory Card to effectively function as a physical disk drive. The Intel Flash Memory Card in conjunction with flash filing systems provides an innovative alternative to both fixed hard disks and floppy
disks in DOS-compatible portable PCs.
User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
. substantial reduction of active power consumption,
size, and weight--considerations particularly important in portable PCs and equipment.· The
iMC004FLKA's high performance read access time
and command register microprocessor write interface allows for use of the flash memory system in an
"execute-in-place" architecture. This configuration
eliminates the need for the redundancy associated
with DRAM and Disk memory system architectures.
ROM based operating systems, such as Microsoft's
MS-DOS ROM Version allow for "instant-on" capability. This enables the design of PCs that boot, operate,· store data files, and execute application code
from/to purely nonvolatile memory.
Flash write performance is often 50% higher than
hard disks for typical user file storage. This equates
to ten times more performance when compared to
"spun-down" disks, the common practice for portable machines.

The Microsoft Flash File System enables the storage and modification of data files by utilizing a linked
list directory structure that is evenly distributed along
with the data across the memory card. The linked list
approach minimizes file fragmentation losses by using variable-sized data structures rather than th~
standard sector/cluster method of disk-based systems;
The integration of the PCMCIAlJEIDA 68-pin interface with flash filing systems enables the end-user
to transport user files and application code between
portable PCs and desktop PCs with memory card
Reader/Writers. Intel Flash PC cards provide durable nonvolatile memory storage for Notebook PCs
on the road, facilitating simple'transfer back into the
desktop environment.
.
For sYl?tems currently using a static RAM/battery
configuration
for
data
acquisition,
the
iMC004FLKA's inherent nonvolatility eliminates the
need for battery backup. The concern of battery failure no longer exists, an important consideration for
portable computers and medical instruments, both
requiring continuous operation. The iMC004FLKA
consumes no power when the system is off. In addition, the iMC004FLKA offers a considerable cost
and density advantage over memory cards based on
static RAM with battery backup.
The flash memory card's. electrical zone-erasure,
byte writability, and complete nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the designer the flexibility to
selectively rewrite zones of data while saving other
zones for infrequently updated look-up tables.

PRINCIPLES OF OPERATION

Flash filing systems enable the storage and modification of data files by allocating flash memory space
·intelligently, thus minimizing the number of rewrite
cycles. This management function allows the user to
rewrite reliably to the flash memory card many more
times than a fixed or floppy disk which concentrate
rewrite operations into .small fixed portions of the
medium.
.

Intel's Flash Memory Card combines the functionality of two mainstream memory technologies: the rewritability of RAM and the nonvolatility of EPROM.
The flash memory card consists of an array of. individual memory devices, each· of which defines a
physical zone. The iMC004FLKA's memory devices
erase as individual blocks, equivalent in size to the
256 kByte zone. Multiple zones can be erased simUltaneously provided sufficient current for the appro-·
priate number of zones (memory devices). Note,
multiple zone erasure requires higher current from
both the Vpp and Vee power supplies. Erased zones
can then be written in bit- or byte-at-a-time fashion
and read randomly like RAM. Bit level write capability also supports disk emulation.

Flash filing systems implement Intel's Flash Memory
Card as a re~irected disk drive; similar to structures
used in local area networks. This enables the end
user to interact with the flash memory card in precisely the same way as a magnetic disk.· Filing systems that run under popular operating systems, such
as MS-DOS, can use the installed base of application s9ftware.

4-65

iMC004FLKA

In the absence of high voltage on the VPP1,.2 pins;
the iMC004FLKA remains in the read-only mode.
Manipulation, of the external memory card-control
pin yields the standard read, standby, and -output
- disable, operations.
The same read, standby, and output disable operations are available when high voltage is, applied to
the VPP1,.2 pins. In addition, high voltage 6n VPP1;2
enables erasure and rewriting of the accessed
zone(s). All functions associated with altering zone
contents--erase, erase verify, write, and write verify-are accessed via the, command register.
Commands are written to the internal memory register(s), decoded by zone size, using standard microprocessor write timings. Register contents for a given zone serve as input to that zone's internal statemachine which controls the erase and rewrite circuitry. Write cycles also internally latch addresses and'
data needed for write and erase operations. With the
appropriate command written to the register(s), stan'dard microprocessor read timings output zone data,
or output data for erase and write veri(ication.

,Byte-wide or Word-wide Selection
The flash memory card can be read, erased, and
written in a byte-wide or word-wide mode. In the
word-wide configuration VPfLand/or CE1 control
the lO-Byte whileVpP2 andCE2 control the HI-Byte
(Ao = don'teare).
Read, Write, and Verify operations are byte- or wordoriented, thus zone independent. Erase Setup and
Begin Erase Commands are zone dependent such
that commands written to any address within a 256
kByte zone boundary initiate the erase operation in
that zone (or two 256 kByte zones under word-wide
operation).
Conventional x8 operation uses CE1 active-low, with
CE2 high, to read or write data through the 00-07
only. "Even bytes" are accessed when Ao is low,
corresponding to the low byte of the complete x16
word. When Ao i~ high, the "odd byte" is accessed
by transposing, the high byte of the complete x16
word onto the 00-07 outputs. This odd byte corresponds to data presented on 08-015 pins in x16
mode.

Note that two zones logically adjacent in x16 mode
are multiplexed through 00-0] in x8 mode and are
toggled by the Ao address. Thus, zone. specific
erase operations must be kept discrete in x8 mode
by addressing even bytes only for one-half of the
zone pair, then addressing odd bytes only for the
other half.

Card Detection
The flash memory card features two card detect pins
(C01!2> that allow the host system to determine if the
card is properly loaded. Note that the two ~ are
located at opposite ends of the card. Each CO output should be read through a port bit. Should only
one of the two bits show the card to be present, then
the system should instruct the user to re-insert the
card squarely into the socket. Card detection can
also tell the system whethlilr or -not to redirect drives
in the case of system booting. CD1,.2 is active low,
,
internally tied to ground.

Write Protection
The flash memory card features three types of write
protection. The first type features a mechanical
Write Protect Switch that disables the circuitry that
control Write Enable to the flash devices. When the
switch is activated, WE is forced high, which disables any writes to the Command Register. The second type of write protection is based on the
PCMCIAlJEIOA socket. Unique pin length assignments provide protective power supply sequencingduring hot insertion and removal. The third type operates via software control through the Command
Register when the card resides in its connector. The
Command Register of each zone is only active when
VPP1,.2 is at high voltage. Depending upon the application, the system designer may choose to make
VPP1,.2 power supply switchable-available only
when writes are desired. When VPP1t2 = VPPL, the,
contents of the register default to the read command, making the iMC004FlKA a read-only memory
card. In this mode, the memory contents cannot be
altered.
"
The system designer may choose to'leave VPP1;2 =
VPPH, making the high voltage supply constantly
available. In this case, all'Commaild Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO. (See the section on Power
Up/Oown Protection.) The iMC004FlKA is designed
to accommodate either deSign practice,and to en_ courage optimization of the processor-memory card
interface.
'

4-66

infel·

iMC004FLKA

reader/writer. Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the memory device code (SOH).

BUS OPERATIONS
Read
The iMC004FLKA has two control functions, both of
which must be logically active, to obtain data at the
outputs. Card Enable (CE) is the power control and
should be used for h!9.!! and/or low zone(s) selection. Output Enable (OE) is the output control and
should be used to gate data from the output pins,
independent of accessed zone selection. In the
byte-wide configuration, only one CE is r~uired.
The word-wide configuration requires both CEs active low.

Zone erasure and rewriting are accomplished via the
Command Register, when high voltage is applied to.
VPP1,!.!' The contents of the register serve as input to
that zone's internal state-machine. The state-machine outputs dictate the function of the targeted
zone.

When VPP1,t.! is high (VPPH), the read operations can
be used to access zone data and to access data for
write/erase verification. When VPP1,t.! is low (Vppu,
only read accesses to the zone data are allowed.

The Command Register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.

Write

With Output Enable at a logic-high level (VIH),output
from the card is disabled. Output pins are placed in a
high-impedance state.

The Command Register is written by bringing Write
Enable to a logic-low level (VIU, while Card Enable(s) is/are low. Addresses are latched on the failing edge of Write Enable, while data is latched on
the riSing edge of the Write Enable pulse. Standard
microprocessor write timings are used.

Standby

Refer to AC Write Charcteristics and the Erase/
Write Waveforms for specific timing parameters.

Output Disable

With one Card Enable at a logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only the zone correspond.!!!g to the selected address within the upper or
lower CE1,t.! bank is active at a time. (NOTE: Aomust
be low to select the low half of the x16 word when
CE2 = 1 and CE1 = 0.) All other zones are deselected, substantially reducing. card power consumption. For deselected banks, the outputs are placed in
a high-impedance state, independent of the Output
Enable Signal. If the iMC004FLKA is deselected curing erasure, writing, or write/erase verification, the
accessed zone draws active current until the operation is terminated.

COMMAND DEFINITIONS
When low. voltage is applied to the Vpp pines), the
contents of the zone Command. Register(s) default
to OOH, enabling read-only operations.
Placing high voltage on the Vpp pines) enable(s)
read/write operations. Zone operations are selected
by writing specific data patterns into the Command
Register. Tables 3 and 4 define these iMC004FLKA
register commands for both byte-wide and wordwide configurations.
All commands written to the Command Register require that the Zone Address be valid or the incorrect
zone will receive the command. Any Command/
Data Write or Data Read requires the correct Valid
Address.

Intelligent Identifier Command
The manufacturer- and device-codes can be read
via the Command Register, for instances where the
iMC004FLKA is erased and rewritten in a universal

4-67

infel .

IMC004FLKA

Table 2. Bus Operations
Pins

Notes

Operation
.~

z

Cj)
.~

w

a:

[1,7]

[1,7]

VPP2

VPP1

. VPPL

VPPL

Read (x8)

8

Read (x8)

9

VPPL

VPPL

Read (x8)

10

VPPL

Read (x16)

11

Output Disable
Standby

AO

CE2

CE1

DE

WE

08-0 15

00-07

VIL

VIH

VIL

VIL

VIH

Tri-state

Data Out-Even
Data Out-Odd

VIH

VIH

VIL

VIL

VIH

Tri-state

VPPL

X

VIL

VIH

VIL

VIH

Data Out

Tri-state

VPPL

VPPL

X

VIL

VIL

VIL

VIH

Data Out

Data Out

VPPL

VpPL

X

X

X

VIH

VIH

Tri-state

Tri-state

VPPL

VPPL

X

VIH

VIH

X

X

Tri-state

Tri-state

VPPX

VPPH

VIL

VIH

VIL

VIL

VIH

Tri-state

Data Out-Even
Data Out-Odd

Read (x8)

3,8

Read (x8)

3,9

VPPH

VPPX

VIH

VIH

VIL

VIL

VIH

Tri-state

VPPH

VPPX

X

VIL

VIH

VIL

VIH

Data Out

Tri-state

X

VIL

VIL

VIH

Data Out

Data Out

Read (x8)

10

Read(x16)

3,11

VPPH

VPPH

:t

Write (x8)

5,8

VPPX

VPPH

VIL

VIH

VIL

VIH

VIL

Tri-state

Data In-Even

w

Write (x8)

9

VPPH

VPPX

VIH

VIL

VIH

VIL

Tri-state

Data In-Odd

a: Write (x8)

VIH

...a:w
"Qc(

VIL

10

VpPH

VPPX

X

VIL

VIH

VIH

VIL

Data In

Tri-state

Write (x16)

11

VPPH

VpPH

X

VIL

VIL

VIH

VIL

Data In

Data In

Standby

4

VPPH

VPPH

X

VIH

VIH

X

X

Tri-state

Tri-state

VPPH

VPPH

X

X

X

VIH

VIL

Tri-state

Tri-state

Output Disable

NOTES.
1. Refer to DC Characteristics. When VPP1,1.! = VPPL memory contents can be read but not written or erased.
2. Manufacturerand device codes may be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. Read operations with VPP1,1.! = VPPH may access array data or the Intelligent Identifier codes.
4. With VPP1,1.! at high voltage, the standby current equals Icc + Ipp (standby).
. .
5. Refer to Table 3 for valid Data-In during a write operation.
6. X can be VIL or VIH.
7. VpPX = VPPH or VPPL.
8. This x8 operation reads or writes the low byte of the x16 word on 000-7, I.e., Ao low readsueven" byte in x8 mode.
9. This x8 operation reads or writes the high byte of the x16 word on 000-7 (transposed from 008-15), i.e., Ao high reads
"odd" byte in x8 mode.
.
'
10. This x8 operation reads.or writes the high byte of the x16 on 008-15. Ao is "don't care."
11. Aois "don't care," unused in x16 mode. High and low bytes are presented simultaneously.

4-68

infel·

IMC004FLKA

Table 3. Command Definitions Byte-Wide Mode
Command

Bus
Second Bus Cycle
first Bus Cycle
Notes Cycles
Req'd Operatlon(1) Address(2) Da~(3) Operatlon(1) Addres~(2) Data(3)

Read Memory

1

Write

.

RA

OOH

Read Intelligent 10 Codes

4

3

Write

IA

90HT

Read

Set-up Erase/Erase

5

2

Write

ZA

20H

Write

. ZA

20H

Erase Verify

5

2

Write

EA

AOH

. Read

EA

EVO

Set-up Write/Write

6

2

Write

WA

40H

Write

WA

WO

Write yerify ,

6

2'

Write

WA

COH

Read

WA

WVO

Reset

7

2

Write

ZA

FFf1

Write

ZA

FFH

Table 4. Command Definitions Word-Wide Mode·
C!)mmand

Bus
First Bus Cycle
Seco"d Bus Cycle
Notes Cycles
Req'd Operatlon(1) Ad~rel"I(2) Data(3) Operatlon(1) Addrelia(2) Data(3)

Read Memory

1

Write

RA

OOOQH

Read Intelligent 10 Codes

4

3

Write

IA

IJ09QH

R",ad

Set-up Erase/Erase

5

2

Write

ZA

2920H

Write

ZA

2020H

Erase Verify

5

2

Write

EA

MAOH

Read

EA

EVO

Set-up Write/Write

6

2

Write

WA

4040H

Writ~

WA

WO

Write Verify

6

2

Write

WA

COCPH

Read

WA

WVO

Reset

7

.2

Write

ZA

FFFFH

Write

ZA

FFFFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code. 01 H for device code.
EA = Address of memorY location to be read during erase verify.
RA = Read.Address
. .
WA = Address of memory location to be written.
ZA = Address of 256 kByte zones involved in erase operation..
.Addresses are latched on the falling edge of the Write Enable pulse.
3. 10 = Data read from location IA during device identification. (Mfr. = 89H. Device = BOH).
EVO = Data read from location EA during erase verify.
WO, .= Data to be written af location WA. Data is latched on the rising edge of Write Enable.
WVO = Olitaread from locationWA during write verify. WA is latched on the Write command.
4. Following the Readlntellgent 10 command. two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Er'ase Algorithm.'
. .
6. Figure 6 illustrates the Write Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8. The Reset command operation on a zone basic. To. reset entire Card. requires reset write cycles to each zone. .

4-69

infel .

IMC004FLKA

tents are protected against erasure. ,Refer to AC
Erase Characterstics and Waveforms for specific
timing pararreters.

, Read Command
While VPP1,..2 is high, for erasure and writing" zone
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH (OOOOH for the word-wide configuration) into the
zone Command Register(s). Microprocessor read
cycles retrieve zone data. The accessed ,zone remains enabled for reads until the Command Registeres) contents are altered.

: Erase-V~rlfy Command
The erase command erases all of the bytes of the
zone in parallel. After each erase operation,all bytes
in the zone must be individually verified. In ,bytemode, operations, zones are segregated by Ao in
odd and even banks; erase and erase verify operations must be done in complete passes of evenbytes-only then odd-bytes-only. See the Erase Algorithm for byte-wide mode. The erase verify operation
is initiated by writing AOH (AOAOH for word-wide) into
the Command Register(s). The address for the
byte(s) to be verified must be supplied as it is
latched on the falling edge of the Write Enable
pulse. The register write terminates the erase operation with the risi~g edge of its Write Enable pulse.

The default contents of each zone's register(s) upon
VPP1,..2 power-up is OOH (OOOOOH for word-wide).
This default value ensures that no spurious alteration of memory card contents occurs during the
VPP1,..2 power transition. Where the Vpp1,..2 supply is
left at, VPPH, the memory card powers-up and remains enabled for reads until the command Register
contents of targeted zones are' changed. Refer to
the AC Read Characteristics and Waveforms for
' ,
specific timing parameters. ,

The enabled zone applies an internally-generated
margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the
byte are erased. Similarly, reading FFFFH from the
addressed word indicates that a/l bits in the word are
erased.
'

Intelligent Identifier Command
Each zone of th~ iMC004FLKA contains an Intelligent Identifier to identify memory card device characteristics. The operation is initiated by, writing 90H
(9090H for word-wide) into the Command Regis-,
teres) with Zone Address. Following the command
write, a, read cycle from address OOOOOHretrieves
'the manufacturer ,code 89H (8989H for word-wide).
A read cycle from address 0002H returns the device
code BOH (BOBOH for word-wide). To terminate the
operation, it is necessary to write another valid command into the register(s).

The erase-verify command must be written to the
Command Register' prior to each byte, (word) verification to latch its address. The process continues
for each byte (word) in the zone(s) until a byte (word)
does not return FFH (FFFFH) data, or the last address is accessed.
'
.
,
In the case where the data read is not FFH(FFFFH),
another erase operation is performed. (Refer to Setup Erase/Erase.) Verification then resumes from the
address of the last-verified byte (word). D.nce all
bytes (words) in the zone(s) have been verified, the
erase step is complete. The accessed zone can now
be written. At this pOint, the verify operation is terminated by writing a valid command (e.g., Write Setup) to the Command Register. The Erase algorithms
for byte-wide and word-wide configurations illustrate
how commands and bus operations are combined to .
perform electrical erasure of the iMC001 FLKA. Refer to AC Erase Characteristics and Waveforms for
specific timing parameters.

Set-up Erase/Erase Commands
Set-up Erase stages the targeted zone(s) for electrical erasure of all bytes in the zone. The set-up erase
operation is performed by writing 20H to the Command Register (2020H for word-wide) with Zone Address.
I,
To commence zone-erasure,' the erase command
(20H or 2020H) must again be written to the registeres). The erase operation begins with the rising
edge of the Write-Enable pulse and te~minates with
the rising edge of 'the next Write-Enable pulse (i.e.,
Erase-Verify Command).
'
.

Set-up Write/Write Commands

This two-step sequence of set-up followed byexecution ensures that zone memory contents are not accidentally erased: Also, zone-erasure can only occur
when high voltage is applied to the VPP1,..2 pins. In
the absence of this high voltage, zone memory con-

Set-up write is a command-only operation, that,
stages the targeted zone for byte writing. Writing
40H (4040H) into the Command Register(s) performs the set-up operation.

4-70

IMC004FLKA

Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched on the rising edge of
the Write Enable pulse. The rising edge of Write Enable also begins the write olleration. The write operation terminates with the next rising edge of Write
Enable, which is used to write the verify command.
Refer to AC Write Characteristics and Waveforms
for specific timing parameters.

Write Verify Command
The iMC004FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur
sequentially or at random. Following each write operation, the byte or word just written must be verified.

two consecutive writes of FFH (FFFFH for word,wide) will safely abort the operation. Zone memory
contents will not be altered. A valid command must
then be written to place the accessed zone in the
desired state.

EXTENDED ERASE/WRITE CYCLING
Intel hl;lS designed extended cycling capability into
its ETOX II flash memory technology enabling a
flash memory card with a MTBF that is approximately 20 times more reliable than rotating disk technology. Resulting improvements in cycling reliability
come without increaSing memory cell size or complexity. First, an advanced tunnel oxide increases
the charge carrying ability ten-fold. Second, the ox,ide area per cell subjected to the tunneling electric
field minimizes the probability 'of oxide defects in the
region. Jhe lower electric field greatly reduces oxide
stress and the probability of failure.

The write-verify operation is initiated by writing COH
(COCOH) into the Command Register(s) with the correct address. The register write(s) terminate(s) the
write operation with the rising edge of its Write Enable pulse. The write-verify operation stages the accessed zone(s) for verification of the byte or word
last written. The zone(s) apply(ies) an internally-generated margin voltage to the byte, or word. A microprocessor read cycle outputs the data. A successful
comparison between the written byte or word and
true data means that the byte or word is successfully
written. The write operation then proceeds to the
next desired byte or word location. The Write algorithms for byte-wide and word-wide configurations illustrate how commands are combined with bus operations to perform byte and word writes. Refer to
AC Write Characteristics and Waveforms for specific
timing parameters.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10 ,..,S
duration. Each operation is followed by a byte or
word verification to determine when the addressed
byte or word has been successfully written. The aigorithm(s) allows for up to 25 write operations per
byte or word, although most bytes and words verify
on the first or second operation. T,he, entire sequence of writing and byte/word verification is performed witj'l Vpp at high voltage.

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algo-,
rithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zone(s).

Reset Command
A reset command ,is provided as a means to safely
abort the erase- or write-command sequence~. Following either set-up command (erase or write) with

Erasure begins with a read of memory zone contants. Reading FFH ,(FFFFH) data from' the accessed zone(s) can be immediately followed by writing to the desired zone(s).

4-71

intel .

iMC004FLKA

(Note: byte-wide erase operation requires separate
even- and odd-address passes.to handle the individual256 kByte zones.)With each erase operation, an
increasing number of bytes or words verify to the.
erased state. Erase efficiency may be improved by
storing the address of the last byte or word verified
in aregister(s). Following the next erase operation,
verification starts at the stored address location. Follow this. procedure until all bytes in. the zone are
erased .. Then, re-start the procedure for the 'next
zone or word-wide zone pair. Erasure typically occurs in two seconds per zone.

For zones being erased and rewritten, uniform and
reliable erasure is ensured by first writing all bits in
the accessed zone to their charged state (data ==
OOH byte-wide, OOOOOHword-wide). This is accomplished. using the write a!,gorithm, in approximately
four seconds per zone.
Erase execution then continues. with an initial erase.
operation. Erase verification (data = FFH byte-wide,
FFFFH word-wide) begins at address OOOOOH and
continues through the zone to the last address, or
until data other than FFH (FFFFH)· is encountered.

INITIALIZE SIZE
AND NUMBER OF ZONES
ZONEL = 0
ZONE H=1

290388-3

Figure 3. Full Card Erase Flow

4-72

infel·

IMC004FLKA

Bus
Operation

Command

comments

Wait for Vpp ramp
to VPPH (= 12.0V) (2)

Standby

Initialize pulse-count
Write

Set-up
Write

Data = 40H
+ Valid Address

Write

Write

Valid address/data

Write(3)
Verify

Duration of Write
Operation (twHWH1)
Data = COH at Valid
Address; Stops (4)
Write Operation
tWHGL

Standby
Write

Standby
Read

Read byte to verify
Write Operation
at Valid Address

Standby

Compare data output
to data expected

Write

Read

Standby

Data = OOH, resets the
register for read
.
operations.
Wait for VPP ramp
to VPPL(2)

290388-4

NOTES:

3. Write Verify is only performed af1$r a byte write operation. A final read/compare may be performed (optional) after the register Is written with the Read command.
4. Refer to principles of operation.

1. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and·
VPPL·

Figure 4. Write Algorithm for Byte-Wide Mode

4-73

IMCOO4FLKA

Ius
0pentI0n

c:-.m.

ComIMlld

Walt for Vpp ramp to VPPH (= 12.0y)(2)

Standby

Uaewllh Write ciper8tion Algorithm
,.

Inltlafrze evenIOdd Addnosaea. Erase Pulse
WIdth. and Pulse COunt .

Write

Set-up

Data = 20H

+ Address

Data = 20H

+ Address

Erase
Write

Erase

Duration 01 Erase operation (twHWH2l

Standby

Write

Erase
Vertry(3)

Addr = Byte to verify,
Data = AOH: Stops

Standby

Erase 0peratJ0n(4) iwHGL

Read

Read byte to WIiIy 8IIISII'8 at address .

Stanca,y

COmpares output to FFH Increment pulse
count

..

Write

Standby

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED to
ensure proper and reliable operation of the device.
2. See DC Characteristics for the value of VPPH and
VPPL·

Read

Data = OOH. _the register for read
operations.

Walt for Vpp ramp to VPPL(2)

3. Erase Verify is only performed after a chip erasure. A
final read/compare may be performed (optional) after
the register is written with the Read command.
4. Refer to principles Of. operaticn.

FIgure S. E..... Algorithm for lyte-WldeMode

4-74

IMC004FLKA

Comment.

Wait for Vpp ramp to VPPH
ADRS = address to write
W.JJAT = data word to write
Initialize Data Word Variables:
V.JJAT = valid data
'II_COM = Write Command
V~COM = Write Verify Command
PLSCNT_HI = HI Byte Pulse Counter
PLSCNT-LO = LO Byte Pulse Counter
FLAG = Write Error Rag
Write Set-up Command
Address needs to be Valid
Write

PLSCNT _HI = 0
PLSCNT _LO = 0
FLAG = 0

High/Low Byte
Compore It Mask
Subroutine

See Write Verify and Mask Subroutine

Write Verify Command

F_OAT

= flash memory data

Compare flash memory data to valid data
(word compare). If not equal, check for
Write Error flag. If Flag not set, compare
High and Low Bytes in the Subroutine.

Check buffer of 1/0 port for more data to write

Reset device for read operation

TumoflVpp

290388-6

Figure 6. Write Algorithm for Word-Wide Mode

4-75

intel .

IMC004FLKA

Comments
To look at the LO Byte,
Mask'the HI Byte with
00
W_COM = (W _COM OR OOFFH)
V_OAT = (LOAT OR OOf'Fi'!)
V_COM = (v _COM OR OOFFH)

If the LO Byte verifies,
mask the LOByte
commands with the reset
command (FFH)
If the LO Byte does not'
verify, then increment its
pulse counter and check
for max count
FLAG = 1 denotes a LO
Byte error
Repeat the sequence for
the HI Byte

W_COM = (W _COM OR FFOOH)
V_OAT = (V_OAT OR FFOOH)
V_COM = (V_COM OR FFOOH)

FLAG = 2 denotes a HI
Byte error
FLAG = 3 denotes both
a HI and LO Byte errors.
Flag = 0 denotes no
max count errors;
continue with algorithm.

290388-7

'Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_DAT), the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 7. Write Verify and Mask Subroutine for Word·Wlde Mode

4-76

iMC004FLKA

Comments

Wait for Vpp to stabilize.

Use Write operation algorithm in x8 or x16
configuration

INITIALIZE:
PLSCNLHI=O
PLSCNLLO= 0
ADRS= O'

Initialize Variables:
PLSCNT_HI ~ HI Byte Pulse Counter
PLSCNT_LO ~ LO Byte Pulse Counter
FLAG = Erasure error flag
ADRS ~ Address
E_COM ~ Erase Command
V_COM ~ Verify Command

FLAG = 0
LCOM=2020H
V _COM = AOAOH

Erase Set·up Command
Start Erasing

Duration of Erase Operation

Erase Verify Command stops erasure
See Block·Erase Verify & Mask Subroutine

When both devices at ADRS are erased, F_
DATA ~ FFFFH.1f not equal, incrementthe
pulse counter and check for last pulse

Reset commands default to
(E-COM ~ 2020H) (V_COM
before verifying next ADRS

Reset device for read operation
Turn offVpp

290388-8

NOTE:
X16 Addressing uses A1-A21 only. Ao = 0 throughout word-wide operation.

Figure 8. Erase Algorithm for Word-Wide Mode

4-77

~

AOAOH)

int:eL

iMC004FLKA

Comments
This subroutine. reads the data
word (F_OAT A). It then masks
the HI or LO Byte of the EraSe
and Verify commands from
executing during the next
operation.
If both HI and LO Bytes verify,
then return.
Mask' the HI Byte with OOH.

CCOM = (E_COM or OOFFH)
V_COM = (Y-COM or OOFFH)

If the LO Byte verifies erasure,
then mask' the next erase and
verify commands with FFH
(RESEn.
Ifthe LO Byte does not verify,
then increment its pulse counter
and check for max count. FLAG
= 1 denotes a LO Byte error.

Repeat the. sequence for the HI
Byte.
E_COM = (E_COM or FFOOH)
V_COM = (V_COM or FFOOH)

Flag = 2 denotes a HI Byte error.
Flag = 3 denotes both a HI and
LO Byte errors. FLAG = 0
denotes no max count errors;
continue with algorithm.

290388-9

'Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F_DAn, the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 9. Erase Verify and Mask Subroutine for Word-Wide Mode .

4-78

intel~

iMC004FLKA

The card connector should also have a 4.7 /J-F electrolytic capacitor between Vee and Vss, as well as
between VPP1IVPP2 and Vss. The bulk capacitors
will overcome voltage slumps caused by printed-circuit-board trace inductance, and will supply charge
to the smaller capacitors as needed.

SYSTEM DESIGN CONSIDERATIONS
Three-Line Control
Three-line control provides for:
a. the lowest possible power dissipation and.
b. complete assurance that output bus contention
will not occur.

Power Up/Down Protection
The PCMCIA/JEIDA socket is specified, via unique
Pin lengths, to properly sequence the power supplies to the flash memory card. This assures that hot
insertion and removal will not result in card damage
or. data loss.

To efficiently use these three contr.2!Jnputs, an address-decoder output should drive CE1, 2.!....'!'!hile the
system's Read signal controls the card OE signal,
and other parallel zones. This, coupled with the internal zone decoder, assures that only enabled
memory zones have active outputs, while deselected zones maintain the low power standby condition.

Power-Supply Decoupling

Each zone in the iMC004FLKA is designed to offer
protection against accidental erasure or writing,
caused by spurious system-level signals that may
exist during power transitions. The card will powerup into the read state.

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues-standby, active and transient current peaks, produced by
falling and rising edges of CE1;2. The capacitive and
inductive loads on the card and internal flash memory zones determine the magnitudes of these peaks.

A system designer must guard against active writes
for Vee vol~es above VLKO when Vpp is active.
Since both WE and CE1, 2 must be low for a command write, driving either to VIH will inhibit writes.
With its control register architecture, alteration of
zone contents only occurs after successful comple.tion of the two-step command sequences.

Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC004FLKA features on-card ceramic decoupling .
capacitors connected between Vee and Vss, and
between VPP1IVPP2 and Vss.

While these precautions are sufficient for most applications, it is recommended that Vee reach its steady
state value before raising VPP1;2 above Vee + 2.0V.
In addition, upon powering-down, VPP1;2 should be
below Vee + 2.0V, before lowering Vee.

4-79

intele

iMC004FLKA

Absolute Maximum Ratings*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
DurinQ Read .................. O·C to + SO·C(1)
During Erase/Write .............. O·C to + SO·C
Temperature Under Bias ......... -1 O·C to

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 70·C

Storage Temperature ............ -30·C to + 70·C
Voltage on Any Pin with
Respect to Ground .......... -2.0V to +- 7.0V(2)
VPP1IVPP2 Supply Voltage with
Respect to Ground
During Erase/Write ....... - 2.0V to

+ 14.0V(2, 3)

Vee Supply Voltage with
Respect to Ground .......... - 2.0V to

+ 7.0V(2)

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0:5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC input voltage on VPP1IVPP2 may overshoot to + 14.0V for periods less than 20 ns.

OPERATING CONDITIONS
Symbol

Limits

Parameter

Min

Max

0

60

Unit

Comments

·C

For Read-Only ana
Read/Write Operations

TA

Operating Temperature

Vee

Vee Supply Voltage

4.75

5.25

V

VPPH

Active VPP1, VPP2
Supply Voltages

11.40

12.60

V

VPPL

Vpp During Read Only
Operations

0.00

6.50

V

DC CHARACTERISTICS-Byte Wide Mode
Symbol

Parameter

Notes

Limits
Min Typical Max

Unit

Test Conditions

III

Input Leakage Current

1

±1.0

±20

/LA

Vee = Vee max
VIN = VeeorVss

ILO

Output Leakage Current

1

±1.0

±20

/LA

Vee = Vee max
VOUT = Vee or Vss

lees

Vee Standby Current

1

0.8
4

7

mA

lee1

Vee Active Read Current

1,2

40

70

mA

lee2

Vee Write Current

1,2

5.0

15

mA

Writing in Progress

ICC3

Vee Erase Current

1,2

10

20

mA

Erasure in Progress

Ice4

Vee Write Verify Current

1,2

10

20

mA

Vpp = VPPH
Write Verify in Progress

4-80

1.6 '. mA

= Vee max, CE = Vee
CE = VIH, Vee = Vee max
Vee = Vee max CE = VIL
f = 6 MHz, lOUT = 0 mA
Vee

±0.2V

IMC004FLKA

. DC CHARACTERISTICS-Byte Wide Mode (Continued)
Symbol
. Ices

Parameter

Notes

Vee Erase Verify Current

1,2

Limits
Min

Unit

Test Conditions

Typical

Max

10

20

mA

Vpp = VPPH
Erase Verify in Progress

±BO

fJ-A

Vpp::;; Vee

1.6

mA

Vpp> Vee

Ipps

Vpp Leakage Current

1

IpP1

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

B.O

30

mA

Vpp = VPPH
Write in Progress

IpP3

Vpp Erase Current

1,3

10

30

mA

Vpp = VPPH
Erasure inProgress

IpP4

Vpp Write Verify Current

1.3

3.0

6.0

mA

Vpp = VPPH
Write Verify in Progress

Ipps

Vpp Erase Verify Current

1,3

3.0

6.0

mA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

O.B

V

VIH

Input High Voltage

2.4

Vee ± 0.3

V

VOL

Output Low Voltage

0.40

V

IOL = 3.2mA
Vee = Vee min

VOH1

Output High Voltage

3.B

V

IOH = -2.0mA
Vee = Vee min

VPPL

Vpp puring Read-Only
Operations

0.00

6.5

V

Note: Erase/Write are
Inhibited when Vpp = VPPL

VPPH

Vpp During Read/Write .
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock
Voltage

0.7

±O.OB

Vpp::;; Vee

2.5

V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at Vee = S.OV. Vpp = 12.0V. T = 25°e.
2: 1 chip active and 15 in standby for byte-wide mode.
3. Assumes 1 Vpp is active.

DC CHARACTERISTICS-Word Wide Mode
Symbol

Parameter

Notes

.Limits
Min Typical Max

Unit

Test Conditions

III

Input Leakage Current

1

±1.0

±20

fJ-A

Vee = Vee max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±1.0

±20

fJ-A

Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

O.B

1.6

mA

Vee

4

7

mA

CE

4-B1

= Vee max, CE = Vee ±0.2V
= VIH, Vee = Vee max

IMC004FLKA
.

,

DC CHARACTERISTICS-word Wide Mode (cOntinued)
Symbol
ICCl

Parameter

Not8s

Vee Active Read Current

1,2

Limits
Min

Typ!ca!

Max

50

100

Unit
rnA

Test Conditions
Vee = veernaxei; = VIL
== 6 MHz, lOUT = 0 rnA

f

ICC2

Vcc Write Current

1,2

5:0

25

rnA Writing in Progress

ICC3

Vcc Erase Current

1,2

15

30

rnA

Erasure in Progress

ICC4

Vcc Write Verify Current

1,2

15

30

rnA

VPP = VPPH
Write Verify in Progress i

ICC5

Vee Erase Verify C~rrent

1,2

15

30

rnA

VPP = VPPH
Erase Verify in Progress

Ipps

VPP Leakage Current

±160

p.A

Vpp:S: Vcc

3.0

rnA

VPP >Vcc

IpPl

1
1,3

VPP Read Current

1.5

or Standby Current

· .. ..
:~.

±.16

VPP :S:Vee

IpP2

VPP Write Current

1,3

17

63

rnA

VPP ='VPPH
Write in Progress

IpP3

VPP Erllse Current

1,3

20

60

rnA

Vpp= VPPH
Erasure in Progress

IpP4

VPP Write Verify Current

1,3

5.0

12

rnA

VPP = VPPH
Write Verify in progress

IpP5

VPP Erase Verify Current

1,3

5.0

12

rnA VPP ;=VPPH
Erase Verify in Progress

VIL

Input Low Voltage

',"'.

-0.5

O.B

V

2.4

Vee ± 0.3

V

0.40

V

IOL= 3.2 rnA
Vee =:Vccrnin

V

IOH =-2.0mA
Vcic = Vee rnin
Note: Erase/Write are ,
Inhibited when VPP ;= VpPL

VIH

Input High Voltage

VOL

Output Low Voltage

VOHl

Output High Voltage

3.B

VPPL

.VPP During Read-Only
Operations

0.00

6.5

V

VPPH

Vpp During Read/Write
Operations

11.40

12.60

V

VLKO

Vec Erase/Write Lock
Voltage

2.5

,

V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25°C.
2.2 chips active and 14 in standby for ~rd-wlde mode.
3. Assumes 2 Vpps are active.

4-82

"

IMC004FLKA

CAPACITANCE T
Symbol

= 25°C, f = 1.0 MHz

Parameter

Notes

Limits
Min

Max

Unit

Conditions

CIN1

Address Capacitance

40

pF

VIN= OV

CIN2

Control Capacitance

40

pF

VIN = OV

COUT

Output Capacitance

40

pF

VOUT = OV

CliO

1/0 Capacitance

40

pF

VI/O = OV

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................. VOL and VOH1
Input Timing Reference Level .....•.... VIL and VIH
Output Timing Reference Level ........ VIL and VIH

AC CHARACTERISTICS-Read-Only Operations
Notes

Min

tAvAV/tRC

Read Cycle Time

2

200

tELQV/tcE

Chip Enable Access Time

2

200

ns

tAVQV/tACC

Address Access Time

2

200

ns

tGLQV/toE

Output Enable Access Time

2

100

ns

tELQXltLZ

Chip Enable to Output
in LowZ

2

tEHQZ

Chip Disable to Output
in High Z

2

tGLQXitoLZ

Output Enable to Output
in LowZ

2

tGHQZ/tOF

Output Disable to Output
in High Z

2

toH

Output Hold from Address,
~, or OE Change

tWHGL

Write Recovery Time
before Read

Symbol

Characteristic

NOTES:
1. Whichever occurs first.
2. 'Rise/Fall Time ~ 10 ns.

4-83

Max

Unit
ns

ns

5

60
5

ns
ns

60

ns

1,2

5

ns

2

6

,""S

IMC004FLKA

Vee POWER· UP!

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENAILED

DATA VALID

SrANOBY/
Vee POWER-DOWN

ADDRESS STAILE

I-------------·AYAY(·.<)------------oj

at (0)
twHQL+-----i
WE(;;)

+ ____.....___.(J

DATA (DQ) _ _ _ _:;:HIC:::H~Z'__ _

!-----·AYQY(·ACC)----.f
5.0Y

Vcc
OY

J

290388-10

NOTE:

OJ: refers to rn:1, 2..
Figure 10. AC Waveforms for Read Operations

4·84

infel .

iMC004FLKA

AC CHARACTERISTICS-For Write/Erase Operations
Symbol
tAVAV/tWC

Characteristic

Notes

Min

Write Cycle Time

1,2

200

Max

Unit
ns

tAVWL/tAS

Address Set-up Time

1,2

0

ns

tWLAX/tAH

Address Hold Time

1,2

100

ns

tOVWH/tOS

Data Set-up Time

1,2

80

ns

tWHOX/tOH

Data Hold Time

1,2

30

ns

tWHGL'

Write Recovery Time before Read

1,2

6

p's

tGHWL

Read Recovery Time before Write

1,2

0

p.s

twLOZ

Output High-Z from Write Enable

1,2

5

tWHOZ

Output Low-Z from Write Enable

1,2

tELWL/tCS

Chip Enable Set-up Time before Write

1,2

tWHEH/tCH

Chip Enable Hold Time

1,2

0

ns

tWLWH/tWP

Write Pulse Width

1,2

100

ns

tWHWL/tWPH

Write Pulse Width High

1,2

20

ns

tWHWH1

Duration of Write Operation

1,2,3

10

p.s

tWHWH2

Duration of Erase Operation

1,2,3

9.5

ms

tVPEL

Vpp Set-up Time
to Chip Enable Low

1,2

100

ns

ns
60

ns
ns

40

NOTES:
1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time S; 10 ns.
3. The integrated stop timer terminates the writeleraseoperations, thereby eliminating the need for a maximum specifiction.

ERASE/WRITE PERFORMANCE
Typ

Max

Unit

2.0

30

sec

1,2,4

4.0

25

5

10(6)

Parameter

Notes

Zone Erase Time

1,3,4

Zone Write Time
MTBF

Min

NOTES:
1. 25'C, 12.0\1 Vpp.

sec

,

Hrs

2. Minimum byte writing time excluding system overhead is 16 ,,"S (10 ,,"S program + 6 ,,"S write recovery), while maximum is
400 ,,"s/byte (16 ,,"S x 25 loops allowed by algorithm). Max chip write time is specified lower than the worst case allowed by
the write algorithm since most bytes write significantly faster than the worst case byte.
3. Excludes OOH writing Prior to Erasure.
4. One zone equals 256 kBytes.
5. MTBF - Mean Time between Failure, 50% failure point for disk drives.

4-85

intel .

iMC004FLKA

WRITE
Vee POWER-UP I::
STANDBY

SET-UP WRITE

COWMANO

WRITt
VERIF'ICAnOH

WRITE: COMMAND
LATCH ADDRESS a: DATA

ADDRESSES

Or

(0)

WE

(Vi)

DATA (DQ)

5.0\1

Vee
OV

290388-11

NOTE:
CE refers to

CE1, 2.
Figure 11. AC Waveforms for Write Operations

4-86

intel·

iMC004FLKA

ERASE
Vee POWER-UP .t
STANDBY

VERIFY

SET-UP [RASE

COMMAND

[RASt CO ....AND

ERASING

C~""AND

ERASE
YERIFICAnON

STANDBY/
Yee POWER-DOWN

ADDRESSES

Ci

(E)

OE (0)

WE(W)

DATA (DD)

5.0V

Vee
OV

1Z.0V
V••
V pPL

290388-12

NOTE:

~ refers to CE1, 2.

Figure 12. AC Waveforms for Erase Operations

4-87

infel .

iMC004FLKA

ALTERNATIVE CE-CONTROLLED WRITES
Symbol

Characteristic

Notes

Min

Max

Unit

200

ns

tAVAV

Write Cycle Time

tAVEL

Address Set-up Time

0

ns

tELAX

Address Hold Time

100

ns

tDVEH

Data Set-up Time

80

ns

tEHDX

Data Hold Time

30

ns

.

tEHGL

Write Recovery Time before Read

6

fJ.s

tGHEL

Read Recovery Time before Write

0

fJ.s

tWLEL

Write Enable Set-Up Time
before Chip-Enable

0

ns

tEHWH
tELEH

Write Enable Hold Time

1

: Write Pulse Width

0

ns

100

ns

tEHEL

Write Pulse Width High

20

ns

tpEL

Vpp Set-up Time
to Chip Enable Low

100

ns

NOTES:

.'.

. '

1. Chip Enable Controlled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable. In
systems where Chip Enable defines the write pulse width (with a longer Write Enable timing waveform) all set-up, hold and
inactive Write Enable times should be measured relative to the Chip Enable waveform.

4-88

inial..

IMC004FLKA

PROGRAM
Vee POWER-UP

a::

STANDBY

SET-UP PRDORAI.!

COIolIrolAHD

PROGRA'" COMMAND
LATCH ADDRESS 6: DATA

PROGRAMMING

VERIFY

PROGRA"

COMMAND

VERIFICATION

STANOBYI
Vee POWER-DOWN

ADDRESSES

1=-+--..,..r

tEHW~WH

OE (0)

-'-+---+l---t[HGL

CE (W)

DATA (DQ)

5.0V

Vee
OV

12.0V

Vpp
VpPL

290388-13

NOTE:

CE refers to GEl, 2.
Figure 13. Alternate AC Waveforms for Write Operations

4·89

int:et

iMC004FLKA

ORDERING INFORMATION

lil:IB'~I~IKlQIAQI'I~1

,

. 'L

CUSTOMER IDENTIFIER
A= REVISION
K = WORD-WIDE
ARCHITECTURE

'-------FL

=FLASH

L . . - - - - ' - - - - - 0 0 4 = 4 MEGABYTE
DENSITY IN MEGABYTES
' - - - - - - - - - - - M C = MEMORY CARD

'--------------i = INTEL
' - - - - - - - - - - - - , - . = PACKAGE PLACEHOLDER

ADDITIONAL INFORMATION
ER-20, "ETOX II Flash Memory Technology"
RR-60, "ETOX II Flash Memory Reliability Data Summary"
AP-343, "Solutions for High Density Applications using Flash Memory"
RR-70, "Flash Memory Card Reliability Data Summary"

REVISION HISTORY
Number

Description

03

Removed PRELIMINARY
Removed ExCA Compliance Section
Clarified need for Valid Address during Commands
Corrected Vpp = VPPH in Erase Algorithm
Increased ICC2-lcC5 D.C. Current Specifications for
both Byte-Wide and Word-Wide modes.
Revised and updated Application Section discussion
Changed order number

4-90

290388-14

ORDER NUMBER
294005
293002
292079
293007

SERIES 2 FLASH MEMORY CARDS
iMC004FLSA, iMC010FLSA, iMC020FLSA
4, 10 and 20 Megabyte Capacities
Reliability
• PCMCIA
• Solid-State
2.0/JEIDA 4.1 68-Pin Standard
Intel FlashFile™ Architecture
• - Hardwired Card Information
• High-Performance Read Access
• - 200 ns Maximum
Structure
- Byte- or Word-Wide Selectable
High-Performance Random Writes
•
ExCATM Compatible for System-toTypical Word Write
- 10
• System
Inter-Operability
Erase Suspend to Read Command
•
Component Management Registers for
...;.. Keeps Erase as Background Task
• Card
Status/Control and Flexible
Nonvolatility (Zero Retention Power)
System Interface
•
- No Batteries Required for Back-up
Erase/Write
• -Automatic
ETOXTM III 0.8/-,- Flash Memory
Monitored with Ready/Busy Output
•
Technology
Power-Down Modes
- 5V Read, 12V Erase/Write
• -CardDeep-Sleep
for Low Power
- High-Volume Manufacturing
Applications
Experience
• Mechanical Write Protect Switch
,

/-,-S

Intel's Series 2 Flash Memory Card facilitates high-performance disk emulation in mobile PCs and dedicated
equipment. Manufactured with Intel's ETOX III 0.8jJ-, FlashFile Memory devices, the Series 2 Card allows code
and data retention while erasing and/or writing other blocks. Additionally, the Series 2 Flash Memory Card
features low power modes, flexible system interfacing and a 200 ns read access time. When coupled with
popular low-power microprocessors, like Intel's 386SLTM, these cards enable high-performance implementations of mobile computers and systems.
Series 2 Cards conform to the Personal Computer Memory Card International Association (PCMCIA 2.0)/Japanese Electronics Industry Development Association (JEIDA 4.1) 68-pin standard, providing electrical and
physical compatibility. The Series 2 Flash Memory Card is also compatible with Intel's Exchangeable Card
Architecture (ExCA), an open hardware and software system implementation of PCMCIA Release 2.0 that
allows inter-operability from system to system, independent of manufacturer.
Data file management software, such as Microsoft's' Flash File System (FFS), provide data file storage and
memory management, much like a disk operating system. Intel's Series 2 Flash Memory Cards, coupled with
flash file management software, effectively provide a removable, all-silicon mass storage solution with higher
performance and reliability than disk~based memory architectures.
Designing with Intel's FlashFile Architecture enables OEM system manufacturers to design and manufacture a
new generation of mobile PCs and dedicated equipment where high performance, ruggedness, long battery
life and lighter weight are a requirement. For large user groups in workstation environments, the Series 2
Cards provide a means to securely store user data and backup system configuration/status information.

ExCA, ETOX, FlashFile, and i386SL are trademarks of Intel Corporation.
Microsoft is a trademark of Microsoft Corporation.

4-91

October 1992
Order Number: 290434-002

SERIES 2 FLASH MEMORY CARDS

Table 1. Series 2 Flash Memory Card Pinout
Pin

Signal

I/O

Function

Signal

35

GND

I/O

Data Bit3

36

CD1

0

004

I/O

Data Bit 4

37

0011

I/O

Data Bit 11

005

I/O

Data Bit 5

38

0012

I/O

Data Bit 12

5

DOs

I/O

Data Bit6

39

0013

I/O

Data Bit 13

6

007

I/O

Data Bit 7

40

0014

I/O

Data Bit 14

7

CE1

I

41

0015

I/O

Data Bit 15

8

A10

I

Address Bit 10

42

CE2

9

OE

I

Output Enable

43

NC

10

An

I

Address Bit 11

44

RFU

GND

2

003

3
4

Card Enable 1

Active

I/O

Pin

Ground

1

LO

LO

Function

I

Card Detect 1

Card Enable 2

11

A9

I

Address Bit 9

45

RFU

As

I

Address Bit 8 .

46

A17

I

Address Bit 17

13

A13

I

Address Bit 13

47

A1S

I

. Address Bit 18

14

A14

I

Address Bit 14

48

A19

I

Address Bit 19

15

WE

I

Write Enable

LO

49

A20

I

Address Bit 20

16

RDY/BSY

Ready-Busy

.HI/LO

50

A21

I

Address Bit 21

17

Vee

Supply Voltage

51

Vee

18

VPP1

Supply Voltage

52

VpP2

Supply Voltage
Supply Voltage

19

A1S

I

Address Bit 16

A22

I

20

A15

I

Address Bit 15

54

A23

I

Address Bit 23

21

A12,

I

Address Bit 12

55

A24

I

Address Bit 24

22

A7

I

Address Bit 7

56

A25

No Connect

23

As

I

Address Bit 6

57

RFU

Reserved

24

A5

I

Address Bit 5

58

RST

I

25

A4

I

Address Bit 4

59

WAIT

0

26

A3

I

Address Bit 3

60

RFU

27

A2

I

Address Bit 2

61

REG

I

Register Select

28

A1

I

Address Bit 1

62

BVD2

Ao

I

Address Bit 0

63

BVD1

0
0

Batt. Volt Det 2

29

Data Bit8

Address Bit 22

Reset

HI

Extend Bus Cycle

LO

Reserved

30

000

I/O

Data Bit 0

DOs

I/O

31

001

I/O

Data Bit 1

65

009

I/O

Data Bit 9

32

002

I/O

Data Bit 2

66

0010

I/O

Data Bit 10

33

WP

0

67

CO2

34

GND

68

GND

4-92

0

LO

Batt. Volt Det 1

64

HI

LO

Reserved

53

Write Protect

LO

Reserved

12

Ground

Active

Ground

Card Detect 2
Ground

LO

intel .

SERIES 2 FLASH MEMORY CARDS

Table 2. Series 2 Flash Memory Card Pin Descriptions .
Symbol
Ao-A25

000-0015

Type

Name and Function

I

ADDRESS INPUTS: Ao through A25 are address bus lines which enable direct
addressing of 64 megabytes of memory on a· card. Ao is not used in word access
mode. A24 is the most significant address bit. Note: A25 is a no-connect but
should be provided on host side.

I/O

DATA INPUT/OUTPUT: 000 through 0015 constitute the bidirectional data bus.
0015 is the most significant bit.

CE1, CE2

I

CARD ENABLE 1,2: CE1 enables even bytes, CE2 enables odd bytes.
Multiplexing Ao, CE1 and CE2 allows a-bit hosts to access all data on 000
through 007. (See Table 3 for a more detailed description.)

OE

I

OUTPUT ENABLE: Active low signal gating read data from the memory card.

WE

I

WRITE ENABLE: Active low signal gating write data to the memory card.

ROY/BSY

0

READY/BUSY OUTPUT: Indicates status of internally timed erase or write
activities. A high output indicates the memory card is ready to accept accesses. A
low output indicates that a device(s) in the memory card is (are) busy with
internally timed activities. See text for an alternate function (READY-BUSY MODE
REGISTER).

C01 & C02

0

CARD DETECT 1, 2: These signals provide for correct card insertion detection.
They are positioned at opposite ends of the card to detect proper alignment. The
signals are connected to ground internally on the memory card and will be forced
low whenever a card is placed in the socket. The host socket interface circuitry
shall supply 10K or larger pull-up resistors on these signal pins.

WP

0

WRITE PROTECT: Write Protect reflects the status of the Write-Protect switch on
the memory card. WP set high = write protected, providing internal·hardware
write lockout to the flash array..
WRITE/ERASE POWER SUPPLY: (12V nominal) for erasing memory array
blocks or writing data in the array. They must be 12V to perform an erase/write
operation. VPP1 supplies even byte Erase/Write voltage and VPP2 suppUes the
odd byte Erase/Write voltage.

VpP10 VPP2

CARD POWER SUPPLY (5V nominal) for all internal circuitry .

.Vee
GNO

I

GROUND for all internal circuitry.

REG

I

REGISTER SELECT provides access to Series 2 Flash Memory Card registers
and Card Information Structure in the Attribute Memory Plane.

RST

I

RESET from system, active high. Places card in Power-On Default State. RESET
pulse width must be ~ 200 ns.

WAIT

0

WAIT (Extend Bus Cycle) is used by Intel's I/O cards and is driven high.

BV01, BV02

0

aATTERY VOLTAGE DETECT: Upon completion of the power on reset cycle,
these signals are driven high to maintain SflAM-card compatibility.

RFU

RESERVED FOR FUTURE USE

NC

NO INTERNAL CONNECTION. Pin may be driven or left floating.

4-93

int'eL

SERIES 2 FLASH MEMORY CARDS

~~~<15~:~1--~~1~~~:~~::~>

~

1______________

______

~____11

WE
OE

RDY!BsY
RST
A<25:0>

REG

______

RY /BY< 19:0>
CARD
CONTROL
LOGIC

PWD<9:0>

Ce:,
C~

WAIT
BVI4

~
A<19:0>
WP

CE<19:0>
WP

v~j

~
-

2SrOOSSA

~ ~9-Ao

WE
OE

Vee

GND

RY!8Y

WE

1--1I--

DEVICE 1

OE
PWD
GND

PWD
VpP1

~-DOo

CE

Vee

VpP2

CARD
DETECT

I-

A19 -Ao

RY!8Y
DEVICE 2

Vee

GND

I

,

l

I

··
·I

I
~9-Ao

I-- CE
I-- WE
~

I-

~-DQo ~

CE

WE
OE

GND

'- f-

RY!8Y
DEVICE 0

Co,

J

D~-DQO ~

CE
WRITE-PROTECT
SWITCH

2SrOOSSA
~ ~9-Ao

'- l-

I-

D~~DQO J ~

GND

Vee

I

I

DEVICE 3

I

··
·

I
CE

VpP2

I

I

I

WE

I--

D~~DQO U
I--

RY!8Y

f--

I--~

,

Vee

··
·

Au ~Ao

I..-PWD
VpP1

RY!8Y

PWD
GND

I

OE

~-DOo

WE
OE

PWD
VpP1

RY!8Y
DEVICE 1S

~9-Ao

CE

I--

DEVICE 19

OE
PWD
GND

Vee

VpP2

Vee
VpP1
VpP2

290434-3

Figure 1. Detailed Block Diagram. The Card Control Logic Provides
Decoding Buffering and Control Signals.
4-94

int:eL

SERIES 2 FLASH MEMORY CARDS

tile memory storage .for mobile PCs on the road, facilitating simple transfer back into the desktop environment.

APPLICATIONS
Intel's second generation Series 2 Flash Memory
Cards facilitate high performance disk emulation for
the storage of data files and application programs on
a purely solid-state removable medium. File management software, such as Microsoft's Flash File
System, in conjunction with the Series 2 Flash Memory Cards enable the design of high-performance
light-weight notebook, palmtop, and pen-based PCs
that have the processing power of today's desktop
computers.
Application software stored on the flash memory
card substantially reduces the slow disk-to-DRAM
download process. Replacing the mechanical disk
results in a dramatic enhancement of read performance and substantial reduction of power consumption, size and weight-considerations particularly
important in portable PCs and equipment. The Series 2 Card's high performance read access time allows the use of Series 2 Cards in an "execute-in-'
place" (XIP) architecture. XIP eliminates redundancy
associated with DRAM/Disk memory system architectures. Operating systems stored in Flash Memory
decreases system boot or program load times, enabling the design of PCs that boot, operate, store
data files and execute application programs from/to
nonvolatile memory without losing the ability to perform an update.
File management systems modify and store data
files by allocating flash memory space intelligently.
Wear leveling algorithms, employed to equally distribute the number of rewrite cycles, ensure that no
particular blqck is cycled excessively relative to other blocks. This provides hundreds of thousands of
hours of power on usage.

For systems currently using a static RAM/battery
configuration for data acquisition, the Series 2 Flash
Memory Card's nonvolatility eliminates the need for
battery backup. The concern for battery failure no
longer exists, an important consideration for portable computers and medical instruments, both requiring continuous operation. Series 2. Cards consume
no power when the system is off, and only 5 /1A in
Deep-Sleep mode (20 Megabyte card). Furthermore,
Flash Memory Cards offer a considerable cost and
density advantage over memory cards based on
static RAM with battery backup.
Besides disk emulation, the Series 2 Card's electrical block-erasure, data writability, and inherent nonvolatility fit well with data accumulation and recording needs. Electrical block-erasure provides design
flexibility to selectively rewrite blocks of data, while
saving other blocks for infrequently updated parameters and lookup tables. For example, networks and
systems that utilize large banks of battery-backed
DRAM to store configuration and status benefit from
the Series 2 Flash Card's nonvolatility and reliability.

SERIES 2 ARCHITECTURE
OVERVIEW

file management software enables the user to
interact with the flash memory card in precisely the
same way as a magnetic disk.

The Series 2 Flash Memory Card contains a 2 to 20
Megabyte Flash Memory array consisting of 2 to 20
28F008SA FlashFile Memory devices. Each
28F008SA contains sixteen individually-erasable, 64
Kbyte blocks; therefore, the Flash Memory Card
contains from 32 to 320 device blocks. It also contains two Card Control Logic devices that manage
the external interface, address decoding, and component management logic. (Refer to Figure 1 for a
block diagram.)

For example, the Microsoft Flash File System enables the storage and modification of data files by
utilizing a linked-list directory structure that is evenly
distributed along with the data throughout the memory array. The linked-list approach minimizes file
fragmentation losses by using variable-sized data
structures rather than the standard sector/cluster
method of disk-based systems.

To support PCMCIA-compatible word-wide access,
devices are paired so that each accessible memory
block is 64 KWords (see Figure 2). Card logic allows
the system to write or read one word at a time, or
one byte at a time by referencing the high or low
byte. Erasure can be performed on the entire block
pair (high and low device blocks simultaneously), or
on the high or low byte portion separately.

Implementation of Intel's Exchangeable Card Architecture (ExCA) enables the user to transport files
and application programs· between portable and
desktop PCs via memory card Reader/Writers. Series 2 Flash Memory Cards provide durable nonvola-

Also in accordance with PCMCIA specifications this
product supports byte-wide operation, in which the
flash array is divided into 128K x 8 bit device blocks.
In this configuration, odd bytes are multiplexed onto
the low byte data bus.

Thi~

4-95

SERIES 2 FLASH MEMORY CARDS

015

SERIES 2 CARD

x 16 mod.
xB mode

Even Byte'

,"

..

.. ..

...r----------.

.....

.,,'

'OddByt.,

•

--------~,...",.

"",,""!"

....

" "

,

_i#Ei

x 16 mode

x 8 mode

,,

,,

,,

,,

,

290434-1

Figure 2. Memory Architecture. Each Device Pair Consists of Sixteen 64 KWord Blocks.
Series 2 Flash Memory Cards offer additional features over the Bulk Erase Flash Card product family
(refer
to
iMC001 FLKA,
iMC002FLKA
and
iMC004FLKA data sheets). Some of the more notable enhancements include: high density capability,
erase blocking, internal write/erase automation,
erase suspension to read, Component Management
Registers that provide software control of devicelevel functions and a deep-sleep mode. '

Write/erase automation simplifies the system software interface tothe card. A two-step command sequence initiates write or erase operations and provides additional data security. Internal device circuits
automatically execute the algorithms and timings
necessary for data-write or block-erase operations,
including' verifications 'for long-term data integrity.
While performing either data-write or block-erase,
the memory card interface reflects this by bringing
its ROY lBSY (Ready/Busy) pin low~ This output
goes high when the operation. completes. This feature reduces CPU overhead and allows software
polling or hardware interrupt mechanisms. Writing
memory data is achieved in single byte or word ,increments, typically in 10 /Ls.
i

Erase blocking facilitates solid-state storage applications by allowing selective memory reclamation. Multiple 64, Kbyte blocks may be simultaneously erased
within the memory card as long as not more than
one block per device is erasing. This shortens the
total time required for erasure, but requires additional supply, current. A block typically requires 1.6 seconds to erase. Each memory block can be erased
and completely written 100,000 times.

Read access time is 200ns or less over the O·C'to
'
60·C temperature range.
The deep-sleep mode reduces power consumption
to 5 /LA to help extend battery life of portable host
systems. Activated through software control, thiS
mode optionally affects ,the entire flash array (Global
PowerOown Register) or specific device pairs (Sleep
Control Register). I
,

Erase suspend allows the system to temporarily interrupt a i:llock erase operation. This mode permits
reads from alternate device blocks while that same
device contains an erasing block. Upon completion
of the read operation, erasure of the suspended
block must be resumed.
'

4-96

intel .

SERIES 2 FLASH MEMORY CARDS

PCMCIA/JEIDA INTERFACE

BATTERY VOLTAGE DETECT

The Series 2 Flash Memory Card interface supports
the PCMCIA 2.0 and JEIDA 4.1 68-pin card format
(see Tables 1 and 2). Detailed specifications are described in the PC Card Standard, Release 2.0, September 1991, published by PCMCIA. The Series 2
Card conforms to the requirements of both Release
1 and Release 2 of the PC Card Standard.

PCMCIA requires two Signals, BVDland BVD2, be
supplied at the interface to reflect card battery condition. Flash Memory Cards do not require batteries.
When the power on reset cycle is complete, BVDl
and BVD2 are driven high to maintain compatibility.

CARD DETECT
Series 2 Card pin definitions are equivalent to the
Bulk-Erase Flash Card except that certain No Connects are now used. A22 through A24, RST (Reset),
and ROY /BSY (Ready/Busy) have pin assignments
as set by the PCMCIA standard.

Two Signals, COl and C02, allow the host to determine proper socket seating. They reside at opposite
ends of the connector and are tied to ground within
the memory card.

NOTE· The READYIBUSY signal is abbreviated as
RDYIBSY by PCMCIA-(card levelj and as RYIBY by
JEDEC (component levelj.

DESIGN CONSIDERATIONS
The Series 2 Card consists of two separate memory
planes: the Common Memory Plane (or Main Memory) and the Attribute Memory Plane. The Common
Memory Plane resides in the banks of device pairs
and represents the user-alterable memory space. '

The outer· shell of the Series 2 card meets all
PCMCIAlJEIDA Type 1 mechanical specifications.
See Figure 19 for mechanical dimensions.

The Component Management Registers (CMR) and
the hardwired Card Information Structure (CIS) reside in the Attribute Memory Plane within the Card
Control Logic, as shown in Figure 3. The Card Control LogiC interfaces the PCMCIA connector and the
internal flash memory array and performs address
decoding and data control.

WRITE PROTECT
A mechanical write protect switch provides the
card's memory array with internal write lockout. The
Write-Protect (WP) output pin reflects the status of
this mechanical switch. It outputs a high signal (VOH)
when writes are disabled. This switch does not lock
out writes to the Component Management Registers.

COMPONENT MANAGEMENT REGISTERS
AlTRIBUTE MEMORY PLANE

NOT USED
(OOO4200H)

,;

,;

,;

,;

,;

,;

,;

"

FUNCTION

CIS ADDRESS

4142H - 41 FEH

RESERVED

4140H

READY-BUSY t.lODE (INTEL)

4136H-413EH

RESERVED

4130H-4134H

READY-BUSY STATUS (INTEL)

COt.lPONENT t.lANAGEt.lENT

4126H - 412EH

RESERVED

REGISTERS

4120H - 4124H

READY-BUSY t.lASK (INTEL)

411CH - 411EH

RESERVED

4118H - 411AH
4106H-4116H

RESERVED

(OOO4000H)
NOT USED
(OOOOOD8H)
HARDWIRE.D PCt.lCIA CIS
(OOOOOOOH)
Attribute Memory Plane
accessible with
REG (pin 61) = VIL

,,
,,
,,

,,
,,
,

,

SLEEP CONTROL (INTEL)

4104H

WRITE PROTECTION (INTEL)

4102H

RESERVED

4100H

CARD STATUS (INTEL)

4004H - 40FEH
4002H

RESERVED
GLOBAL POWER DOWN (PCt.lCIA)

4000H

SOFT RESET (PCt.lCIA)

290434-2
INTEL
PCMCIA

=
=

Performance Enhancement Register
Defined In PCMCIA Release 2.0

Figure 3. Component Management Registers Allow S/W Control of Components within Card

4-97

SERIES 2 FLASH MEMORY CARDS

ADDRESS DECODE
Address decoding provides the decoding logic for
the 2 to 20 Device Chip Enables and the elements of
the Attribute. Memory Plane. REG selects between
the Common Memory Plane (REG = VI H) and the
.
Attribute Memory Plane (REG =. VILl,

NOTE:
The Series 2· Card has active address inputs Ao to
A24 implying that reading and writing to addresses
beyond 32 Megabytes causes wraparound. Furthermore, reads to illegal addresses (for example, between 20 and 32 Meg on a· 20 Megabyte card) re.
turns OFFFFh data.
The 28F008SA devices, storing data, applications or
firmware, form the Common Memory Plane accessed individually Or as device pairs. Memory is linearly mapped in the Comll)on Memory Plane. Three
memory access modes are available when accessing the Common Memory Plane: Byte-Wide, Word
Wide, and Odd-Byte modes.
Additional decoding selects the hardwired PCMCIA
CIS and Component Management Registers
mapped in the Attribute Memory Plane beginning at
address OOOOOOH.
.

The 512 memory-mapped even-byte CMBs are linearly mapped beginning at address 4000H in the Attribute Memory Plane.

DATA CONTROL·
Data Control Logic selects the path and direction for
accessing the Common or Attribute Memory Plane.
It controls any of the PCMCIA-defined Word-Wide,
Byte-Wide or Odd-Byte modes for either reads or
writes to these areas. As shown in Table 3, input
pins which determine these selections are REG, Ao
through A24, WE, OE, CE1, and CE2. PCMCIA specifications allow only even-byte access to the Attribute
Memory Plane.
.
In Byte-Wide mode, bytes contiguous in software actually alternate between two device blocks of a device pair. Therefore, erasure of one device block
erases every other contiguous byte. In accordance
with the PCMCIA standard for memory configuration,
the Series 2 Card does not support confining contiguous bytes within one flash device when in by-8
mode.

4-98

infel·

SERIES 2 FLASH MEMORY CARDS

Table 3. Data Access Mode Truth Table
Function Mode

REG CE2 CE1 Ao OE WE

VpP2

VPP1

D1s-Da

,~-Do

HIGH-Z

HIGH-Z

COMMON MEMORY PLANE
STANDBy(1)

X

H

H

BYTE READ

H

H

H

H

WORD READ

H

ODD-BYTE READ

H

BYTE WRITE

X

X

X

VPPL(2) VPPL(2)

L

L

L

H

VPPL(2) VPPL(2)

HIGH-Z

EVEN-BYTE

L

H

L

H

VPPL(2) VpPL(2)

HIGH-Z

ODD~BYTE

L

L

X

L

H

VPPL(2) VPPL(2)

ODD-BYTE

EVEN-BYTE

L

H

X

L

H

VPPL(2) VPPL(2)

ODD-BYTE

HIGH-Z

VPPH

X

EVEN-BYTE

VPPH

X

ODD-BYTE

H

H

L

L

H

L

H'

H

L

H

H

L

VPPH

WORD WRITE

H

L

L

X

H'

L

VpPH

VpPH

' ODD-BYTE

EVEN-BYTE

ODD-BYTE WRITE

H

L

H

X

H

L

VPPH

VPPL(2)

ODD-BYTE

X

L

L

L

H

X(2)

X(2)

HIGH-Z

EVEN-BYTE

X(2)

VPPH

ATTRIBUTE MEMORY PLANE
BYTE READ

L

H

L

H

L

H

L

H

X(2)

HIGH-t

INVALID

WORD READ

L

L

L

X

L

H

X(2)

X(2)

INVALID
DATA(3)

EVEN-BYTE

ODD-BYTE READ

L

L

H

X

L

H

X(2)

X(2)

INVALID
DATA(3)

HIGH-Z

BYTE WRITE

L

H

L

L

H

L

X(2)

X(2)

X

EVEN-BYTE

X(2)

X

INVALID
OPERATION(3)

L

H

L

H

H

L

X(2)

WORD WRITE

L

L

L

X

H

L

X(2)

X(2)

INVALID
OPERATION(3)

EVEN-BYTE

ODD-BYTE WRITE

L

L

H

X

H

L

X(2)

X(2)

INVALID
OPERATION(3)

X

NOTES:
1. Standby mode is valid in Common Memory or Attribute Memory access.
,
2. To meet the low power speCifications, Vpp = VpPU however VPPH presents no reliability problems.
3. Odd-Byte data are not valid during access to the Attribute Memory Plane.
4. H = VIH, L = VII., X = Don't Care.

4-99

SERIES 2 FLASH MEMORY CARDS

HARDWIRED CIS'

PRINCIPLE.S OF OPERATION
Intel's Series 2 Flash Memory Card provides electrically-alterable, non-volatile, random-access storage.
!ndividua! 28FooeSA devices uiilize a Command
User Interface (CUI) and Write State Machine
(WSM) to simplify block-erasure and data write operations.

The card's structure description resides in the .evenbyte locations starting at OOOOH. and going to the
.' CIS ending tuple (FNULL) within the Attribute Memory Plane. Data included in the hardwired CIS consists of tuples. Tuples are a variable-length list of
data blocks describing details such as manufacturer's name, the size of each memory device and the'
number of flas~ devices within the card ..

COMMON MEMORY ARRAY
Figure 4 shows the Common Memory Plane's organization. The first block pair (64 KWords) of Common Memory, referred to as the Common Memory
Card Information Structure Block, optionally extends
the hardwired CIS in the Attribute Memory Plane for
additional card information. This may be written during initial card formatting for OEM customization.
Since this CIS Block is part of Common Memory, its
data can be altered. Write access to the Common
Memory CIS Block is controlled by the Write Protect
Control Register which' may be activated by system
software after power-up. Additionally, the entire
Common Memory plane (minus the Common Memory CIS Block) may be software write protected. Note
that the Common Memory CIS Block is not ~of
the Attribute Memory Plane.. Do not assert REG to
access the Common'Memory CIS Block.

COMPONENT MANAGEMENT
REGISTER.S (CMRs)
The CMRs in the Attribute Memory Plane provide
special, software-controlled functionality. Card Coritrol Logic includes circuitry to access the CMRs.
REG (PCMCIA, pin 61) selects the Attribute Memory
Plane (and therefore the CMRs) when equal to VIL.
CMRs are classified into. two categories: those defined by PCMCIA R2.0 and those included by Intel
(referred to as Performance Enhancement Registers) to enhance the interface between the host system and the card's flash memory array. CMRs (See
Figure 3) provide seven control functions-ReadyBusy Interrupt Mode, Device Ready-Busy Status,
Device Ready-J;lusy Mask, Deep-Sleep Control,
Software-controlled Write Protection;. Card Status
and Soft Reset.

Device Pair 9

SOFT RESET REGISTER (PCMCIA)
(CONFIGURATION OPTION)
The SOFT RESET REGISTER (Attribute Memory
Plane Address 4000H, Figure 5) is defined in the
PCMCIA Release 2.0 specification as the Configura'
tion Option Register.
Bit 7. is the soft reset bit (SRESET). Writing a 1 to
this bit initiates card reset to the power-on default
state (see Side Bar page 11). This bit must be
cleared to use the CMRs or to ac~ss the devices.
I

Figure 4. Common Memory Plane. Use
the Optional Common Memory Plane
CIS for Custom Card Format Information.

SRESET implements in software what the reset pin
implements in hardware. On power-up, the card automatically assumes default conditions. Similar to
the reset pin (pin. 58), this bit clears at the end of a
power-on reset cycle or a system reset cycle.
Bits 0 through .6 are not used by this memory card,
but power up as zeroes for PCMCIA compatibility.

4-100

infel .

SERIES 2 FLASH MEMORY CARDS

SOFT RESET REGISTER
(CONFIGURATION OPTION REGISTER)
(Read/Write Register)
ADDRESS

BIT 7

4000H

SRESET

1 = RESET, CLEAR TO ACCESS CARD

Figure 5. SOFT RESET REGISTER (PCMCIA). Sets the MemorY Card In the Power-On Default State.

Global PowerDown Register (PCMCIA)
(Configuration and Status)

.

The Global PowerDown Register (Attribute Memory
Plane Address 4002H, Figure 6) is referred to as the
Configuration and Status Register in the PCMCIA
Release 2.0 specification.
Bit 2 (Pwrbwn) controls global card power-down.
Writing a 1 to this bit places each device within the
card into "Deep-Sleep" mode. Devices in DeepSleep are not accessible. Recovery from powerdown requires 500 ns for reads and 1 /Ls for writes.
The PWRDWN bit defaults to 0 on card power-up or
reset. Setting or clearing this bit has no affect on the
bit settings of the Sleep Control Register. .
The remaining Global PowerDown Register bits are
defined for Intel's family of I/O cards and are driven
low for compatibility.

GLOBAL POWER-DOWN REGISTER
(CONFIGURATION AND STATUS REGISTER)
(Read/Write Register)
1

= POWER DOWN

Figure 6. GLOBAL POWER-DOWN REGISTER (PCMCIA). The PWRDWN
Bit Enables Power-Down of All Flash Memory Devices.

4-101

int'et

SERIES 2 FLASH MEMORY CARDS

CARD STATUS REGISTER
(Read Only Register)
ADDRESS

BIT 7

BITS

BIT5

BIT4

BIT3

BIT2

BITl

BITO

4100H

ADM

ADS

SRESET

CMWP

PWRDWN

CISWP

WP

RDY/B'SV

Figure 7_ CARD STATUS REGISTER (Intel) Provides a Quick Review of the Card's Status
Reset with 1 indicating reset. When this bit is zero,
the flash memory array and CMRs may be accessed, otherwise clear it via the SRESET REGISTER.

CARD STATUS REGISTER (INTEL)
The Read-Only, CARD STATUS REGISTER (Attribute Memory Plane Address 4100H, Figure 7) returns generalized status of the Series 2 Card and its
CMRs:

Bit. 6 (ADS, ANY DEVICE SLEEP) is the "ORed"
value of the SLEEP CONTROL REGISTER. Powering down any device pair sets this bit.

Bit 0 (RDYIBSy) reflects the card's RDY IBSY
(Ready-Busy) output. Software pOlling of this bit provides data-write or block-erase operation status. A
zero indicates a busydevice(s) in the card.

Bit 7 (ADM, ANY DEVICE MASKED) is the "ORed"
value of the READYIBUSY MASK REGISTER.
Masking any device sets this bit.

Bit 1 rt-JP) reports the position of the card's Write
Protection switch with 1 indicating write protected. It
reports the status of the WP pin.
Bit 2 (CISWP) reflects whether the Common Memory CIS is write protected using the WRITE PROTECT
REGISTER, with 1 indicating write protected.
Bit 3 (PWRDWN) reports whether the entire flash
memory array is in "Deep-Sleep" (PowerDown)
mode, with 1 indicating "Deep-Sleep". This bit reflects the PWRDWN bit of the GLOBAL POWERDOWN REGISTER. Powering down a/l device pairs
individually (using the Sleep Control Register), also
sets this bit.

WRITE PROTECTION REGISTER
(INTEL)
The WRITE PROTECTION REGISTER (Attribute
Memory Plane Address 4104H, Figure 8) selects
whether the optional Common Memory CIS and the
remaining Common Memory blocks are write protected (see Figure 4).
Enable Common Memory CIS write protection by
writing a 1 to the CISWP Bit (bit 0).
Enable write protection of the remaining Common
Memory blocks by writing a 1 to the CMWP Bit (bit

1).

.

Bit 4 (CMWP) reports whether the Common Memory
Plane (minus Common Memory CIS) is write protected via the WRITE PROTECT REGISTER with 1 indicating write protected.

In the power-on default state, both bits are O. and
therefore not write protected.

Bit 5 (SRESET) reflects the SRESET bit of the SOFT
RESET REGISTER. It reports that the card is in Soft

Reserved bits (2-7) have undefined values and
should be written as zeroes for future compatibility.

•

4-102

"

.... \In •••• ~'''.,,,',

.,,,,oj, .... _ •. _., ........J

SERIES 2 FLASH MEMORY CARDS

WRITE PROTECTION REGISTER
(Read/Write Register)

1 = WRITE PROTECT

Figure 8. WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption

SLEEP CONTROL REGISTER (INTEL)
Unlike the GLOBAL POWERDOWN REGISTER,
which simultaneously places all flash memory devices into a Deep-Sleep mode, the SLEEP CONTROL
REGISTER (Attribute Memory Plane Address
4118H-411AH, Figure 9) allows selective powerdown control of Individual device pairs.
Writing a 1 to a specific bit of the SI,..EEP CONTROL
REGISTER places the corresponding device pair
into the "Deep-Sleep" mode. Devices in De8p-SI96P
are not accessible. On cards with fewer than
20 Megabytes (10 device pairs), writing a one to an
absent device pair has no affect and reads back as
zero.
This· register contains all zeroes (i.e., not in DeepSleep mode) when the card powers up or after a
hard ·or soft reset. Furthermore, the Global PowerDown Register has no affect on the contents of this
register; Therefore, any bit settings of the Sleep

Control Register will remain unchanged after returning from a global power down (writing a Zero to the
PWRDWN bit of the Global PowerDown Register).

READY-BUSY STATUS
REGISTER (INTEL)
The bits in the Read-only, READY-BUSY Status
Register (Attribute Memory Plane Address 4130H4134H, Figure 10) reflect the status (READY = 1,
BUSY = 0) of each device's RY /BY output A busy
condition indicates that a device is currently processing a data-write or block-erase operation.
These bits are logically "AND-ed" to form the
Ready/Busy output (RDY/BSY, pin 16) of the
PCMCIA interface. On memory cards with fewer
than 20 devices, unused Device RY /BY Status Register bits appear as ready.

SLEEP CONTROL REGISTER
(Read/Write Register)

DEVICES

411BH

011

1 = SELECTED DEVICE PAIR IN POWER-DOWN MODE
Figure 9•.SLEEP CONTROL REGISTER (Intel) Allows Specific Devices to be Put Into Power-Down Mode

4-103

SERIES 2 FLASH MEMORY CARDS

-=tI:'A"V

~I.~"

",.;,,,,,LoII -gU~ I

~

...I '"a .........
IU~

~

~ ............. - - -

nl:.\.'IIl~

Il:.n

(Read/Write Register)

4132H

4130H

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

15

14

13

12

11

10

9

DEVICE

8

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

7

6

5

4

3

2

a

,
1 = DEVICE READY, 0 = DEVICE BUSY
Figure 10. READY·BUSY STATUS REGISTER (Intel) Provides
Operation Status qf All Flash Memory Devices

READY~BUSY

In an unmasked condition (MASK REGISTER bits =
0), any device RY /BY output going low pulls the
card's ROY /BSY output to V,L (BUSY). In this case,
all devices must be READY to allow the card's
ROY /BSY output to be ready (V,H). This is referred
to as the PCMCIA READY-BUSY MODE. An alternate type of READY-BUSY function is described in
the next section, READY-BUSY MODE REGISTER.

MASK REGISTER

(INTEL)
The bits of the Read/Write READY-BUSY MASK
REGISTER (Attribute Memory Plane Address
4120H-4124H, Figure 11) mask out the corresponding "AND-ed" READY-BUSY STATUS REGISTER
bits from the PCMCIA data bus (ROY /BSY, pin 16)
andthe CARD STATUS REGISTER RDY/BSY Bit
(bit 0).

READY·BUSY MASK
(Read/Write Register)
ADDRESS
4124H

4122H

4120H

BIT3

BIT2

BIT1

BITO

DEVICE

DEVICE

DEVICE

DEVICE

19

18

17

16

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

15,

14

13

12

11

10

9

8

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

DEVICE

7

6

5

4

3

2

1 = MASK ENABLED'
Figure 11. READY·BUSY MASK REGISTER (Intel) Essential for Write Optimization

4-104

a

SERIES 2 FLASH MEMORY CARDS

If the READY-BUSY MASK REGISTER bits are set
to ones (masked condition), the ROY /BSY output.
and the CARD STATUS REGISTER RDY/BSY bit
will reflect a READY condition regardless of the
state of the corresponding devices. The READYBUSY MASK REGISTER does not affect the
READY-BUSY STATUS REGISTER allowing software polling to determine operation status.
Unmasked is the default condition for the bits in this
register. On memory cards with fewer than 20 devices, unused device mask bits appear as masked.

READY-BUSY MODE REGISTER
(INTEL)
The READY-BUSY MODE REGISTER (Attribute
Memory Plane Address 4140H, Figure 12) provides
the selection of two types of system interfacing for
the busy-to-ready transition of the card's ROY /BSY
pin:
1. The standard PCMCIA READY-BUSY MODE, in
which the card's ROY /BSY signal generates a
low-to-high transition (from busy to ready) only
after all busy devices (not including masked
devices) have completed their data-write or blockerase operations. This may result in a long interrupt latency.
2. A High-Performance mode that generates a lowto-high (from busy-to-ready) transition after each
device becomes ready. This provides the host

system with immediate notification that a specific
device's operation has completed and that device may now be used. This is particularly useful .
in a file management application where a block
pair, containing only deleted files, is being erased
to free up space so new file data may be written.
Enabling the HIGH-PERFORMANCE READY·BUSY
MODE requires a three step sequence:
1, Set all bits In the READY/BUSY MASK REGISTER. This prevents ready devices from triggering
an unwanted interrupt when step 3 is performed.
2. Write 01H to the READY-BUSY MODE REGISTER. This sets the MODE bit.
3. Write 01 H to the READY-BUSY MODE REGISTER. This clears the RACKbit.
The MODE and RACK bits must be written in the
prescribed sequence, not simultaneously. The
card's circuitry is designed purposely in this manner
to prevent an initial, unwanted busy-to-ready transition. Note that in Step 2, writing to the RACK bit is
a Don't Care.
When the High-Performance Mode is enabled, specific READY-BUSY MASK bits must be cleared after
an operation is initiated on the respective devices.
After each device becomes ready, the ROY /BSY pin
makes a low-to-high transition. To catch the next device's completion of an operation, the RACK bit
must be cleared.

READY-BUSY MODE REGISTER
(Read/Write Register)

MODE = READY-BUSY MODE
PCMCIA MODE
1 = HIGH PERFORMANCE

o=

RACK = READY ACKNOWLEDGE CLEAR TO
. SET UP RDY IBSY PIN, THEN CLEAR AFTER
EACH DEVICE BECOMES READY TO ACKNOWLEDGE TRANSITION.

Figure 12. High Performance Ready-Busy Mode REGISTER (Intel)
Used to Trigger a Ready Interrupt for Each Device

4-105

infel· '

SERIES 2 FLASH MEMORY CARDS

, PRINCIPLES' OF DEVICE OPERATION
individual 28FOO8SA devices include a Command
User Interface (CUI) and a Write State Machine
(WSM) to manage write and erase functions in each
device block.
The CUI serves as the device's"nterface to the Card
Control Logic by directing commands to the appropriate device circuitry (Table 4). It allows for fixed
power supplies during block erasure and data writes.
The CUI handles the WE interface into the device
data and i address 'latches, as well as system software requests for status while the WSM is operating.
The CUI itself, does, not occupy an addressable
memory, location. The CUI provides a latch used to
store the command and address and data information needed to execute the command. Erase Setup
and Erase C9nfirm commands require both appropriate command data and, an address within the block
to be erased. The Data Write Setup command requires both appropriate command data and the address of the location tei be .written, while the Data,
Write command consists of the data to be written
and the address of the location to be writteri~

The CUI initiates flash memory writing and erasing
operations only when Vpp is at 12V. Depending on
the application; the system designer may choose to
make the Vpp power supply switchable (available
when wiites,and erases are requiredj or hardwired to
VPPH. When Vpp = VPPL, power savings are incurred and memory contents cannot be altered. The
CUI architecture provides protection from unwanted
write and erase operations even when high voltage
is applied to Vpp. Additionally,all functions are disabled whenever Vee is below the write lockout voltage VLI

CE Setup Time on Power-Up
First Access after Reset

4-120

...

ns
ns

0

ns

500

ns

1

ms

500

ns

_.

l
~

Vce POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

VIH

-

I·

"1'1

...

-

----'I

'1

tAVAV

VIH

C

....

Vee POWER-DOWN

ADDRESSES STABLE
VIL

CD

STANDBY
---~I

ADDRESSES (A)

iii

DATA VALID

FE

!»

_

VIL

~

_

_

'

'YVVVVVVVVVVV'
I

0

I\)

::e

."

~

~:::t

VIH

CD

0'
~ ...
....

-...

OE

(G)

~ 3

_

VIL

_

_

' 

~

~

~

SERIES 2 FLASH MEMORY CARDS

COMMON AND ATTRIBUTE MEMORY, AC CHARACTERISTICS: CE·ControUed Write Operatlon.(1) ,
Symbol
JEDEC

PCMCIA

Parameter

Note.

Min

Max

Unit

2QO
120
20
140
100
140
60
30
30
6

jJ.s

tEHOV1

Duration of
Data Write

'Duration of Data Write Operation

1
1
1
1
1
1
1
1
1
1
1

tEHOV2

Duration of
Erase

Duration of Block Erase Operation

1

0.3

sec

Vpp Hold from Operation Complete

Write Recovery before Read

1,2
1

0
10
1

' ns

th (OE·WE)

Write Cycle Time

tAvAV

twc

tELEH

tw(WE)

Chip Enable Pulse Width

tAVEL

tsu (A)

Address Setup Time

tAVEH

tsu (A·WEH)

Address Setup Time for CE

tVPEH

tvps

Vpp Setup to CE Going High

tWLEH

tsu (CE·WEH)

Write Enable Setup Time for CE

tDVEH

tsu(O.WEH)

Data Setup Time for CE

tEHDX

Itt (D)

Data Hold Time

teHAX

tree (WE)

tEHRL

!aWL
tEHGL
tPHEL

Write Recover Time
CE High to RDY/BSY

Powerdown Recovery to CE Going Low'

ns
ns
ns
ns
ns
ns
ns
ns
ns

120

ns

ns
jJ.s

NOTES:'

1. Read timing characteristics during erase and data write operations are the same as during read·only operations. Refer to
AC Characteristics for Read·Only operations.
2. Refer to text on Data·Write and Block·Erase Operations.

4·124

WRITE
Vee POWER-UP WRITE BYTE WRITE OR VALID ADDRESS II< DATA (BYTE WRITE) AUTOMATED BYTE WRITE
/t·STANDBY
ERASE SETUP COMMAND
OR ERASE CONfiRM COMMAND
OR ERASE DELAY
V,H
ADDRESSES (A)

~+f----""::::""

READ STATUS
REGISTER DATA

l

WRITE READ ARRAY
COMMAND

&

V,L

ItHAX

V,H

WE (W)
V,L

."

....

!&i

ItHGL

c

CD

V,H

CE

V,L

.

V,H

>
;:;

:::I

I\)

I\)

~

.

:J:

i!:
m
i!:

DATA (D/a)
V,L

0

:E

."

V,H

0

.....3

~

tJ)

I\)

CD

iii

tJ)

V,L

>
0
:E

....<

m

:II

CE (E)

CD

01

tJ)
ItHOVI,2

CD

!

(G)

!»

o:II

VOH

-<

RDY!BsY (R)

;:;

(')

VOL

>
:II

V,H

tJ)

CD

0

.

"'C

CD

I\)

C

PWD (p)
V,L

0'
:::I

(/)

VpPH

Vpp (v)

i---I

t VPEH

'@

VpPL
V,H
V,L

NOTE:
As shown, PWD is a carry-over from the component-level diagram; this signal is generated in the card by the ASIC by writing
to the appropriate register.

2&

Iiiiil

IF'
290434-23

~

~
~

2&
~

SERIES 2 FLASH MEMORY CARDS

r=/:WPS
Surfaca A

&.

TP
-L

2x T

-l r-

C MIN

L:I: O.OOB

~MIN&

S MIN

T&

WiO.004

X:I: 0.002 (

Y:I: 0.002

0.294
(10.0)

3.370
(B5.60)

0.394
(10.0)

O.llB
(3.0)

0.065
( 1.65)

2.126
(54.0)

0.039
(1.00)

0.063
(1.60)

&.
fA.
3

POLARIZATION KEY LENGTH.
INTERCONNECT AREA TOLERANCE = :1:0.002
SUBSTRATE AREA TOLERANCE = :1:0.004
MILLIMETERS ARE IN PARENTHESIS

0:

Figure 19. Series 2 Flash Memory Card Package Dimensions
4-126

290434-24

intel"

SERIES 2 FLASH MEMORY CARDS

t

j.-

0.037 (0.94) MIN

PIN INSERTION

290434-25

Figure 20. Card Connector Socket

SOCKET CONTACT

PIN

~
2.

PIN/SOCKET CONTACT AREA
MILLIMETERS ARE IN PARENTHESIS

0
290434-26

L1 MAX

0.020
(0.5)

L2

L3REF

Pin Type-See Table 1
Detect 0.059 (1.5) ± 0.039
General 0.084 (2.1) ±0.064
Power
0.098 (2.5) ± 0.078

0.024
(0.6)

Figure 21. Pin/Socket Contact Length with Wipe

4-127

intel~

SERIES 2 FLASH MEMORY CARDS

Table 5. Capacitance TA
Symbol

= 25°C, f = 1.0 MHz
Commercial

Characteristics

Min
CIN

COUT

Unit

Max

Address/Control Capacitance (Ao-As, CE1, CE2)

30

pF

Address/Control Capacitance (Ag-A24, all others)

20

pF

Vee, Vpp

2

,...F

Output Capacitance

20

pF

ORDERING INFORMATION
iMC020FLSA,SBXXXXX
WHERE:

i

=

MC
020

= MEMORY CARD
= DENSITY IN MEGABYTES

INTEL

(004,010,020 AVAILABLE)
FLASH TECHNOLOGY
= BLOCKED ARCHITECtURE
S
= REVISION
A
SBXXXXX = CUSTOMER IDENTIFIER
FL

=

ADDITIONAL INFORMATION
AP·361 "Implementing the Integrated Registers of the Series 2 Flash Memory Card"
AP·364 "28F008SA Automation and Algorithms"
28F008SA FlashFile™ Memory Data Sheet
ER·27 "The Intel 28F008SA Flash Memory"
ER·28 "ETOXTM III Flash Memory Technology"
AP·359 "28F008SA Hardware Interfacing"
AP·360 "28F008SA Software Drivers"
iMC001 FLKA 1·Mbyte Flash Memory Card
iMC002FLKA 2·Mbyte Flash Memory Card
iMC004FLKA 4·Mbyte Flash Memory Card

ORDER NUMBER
292096
292099
290429
294011
294012
292094
292095
290399
290412
290388

REVISION HISTORY
Number
02

,

Description

Added 150 ns TUPLE, Deleted 250 ns TUPLE
Corrected Global Power Register Address to 4002H
Corrected Write Protection Register Address to 41 04H
Corrected Ready-Busy Mode Register Address to 4140H
Icc Standby Byte Wide Mode MAX/TYP Increased
Added Power-On Timing Spec
Added First Access after Reset Spec
Changed Advanced Information to Preliminary

4-128 '

intelap

iSM001FLKA
1 MBYTE (512K x 16) CMOS FLASH SIMM

• -High-Performance
120 ns Maximum Access Time

II Standard 80-Pln Insertable Module

-16.67 MB/s Read Transfer Rate
m 10,000 Rewrite Cycles Minimum/
Component
Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase
16 p's Typical Word Write
- Up to 1 Mb/s Write Transfer Rate

..

••

•

• Inherent Non-volatility
- No Batteries or Disk Required for
Back-up
- OW Data Retention Power
CMOS Low Power Consumption
- 20.3 mA Typical Active Current
- 0.4 mA Typical Standby Current

•

- 0.050 Centerline Lead Spacing
- Upgrade Path through 128M bytes
Hardware Presence Detect
II Command Register Architecture for
Microprocessor/Mlcrocontroller
Compatible Write Interface
II Noise Immunity Features
- ± 100/0 Vee Tolerance
- Maximum Latch-Up Immunity
Through EPI Processing
II 12.0V ± 5% Vpp

..

Integrated
,. Program/Erase Stop Timer
III ETOXTM II Nonvolatile Flash
Technology
- High-Volume Manufacturing
Experience

Intel's iSM001 FLKA Flash SIMM (Single In-Line Memory Module) is targeted at high-density read/write nonvolatile memory. The iSM001FLKA enables you to optimize board space; to offer incremental memory.expansion similar to today's DRAM; and to assure continued access to today's and tomorrow's surface-mount
technologies. Intel's iSM001 FLKA offers a reliable sold"state alternative for mass storage. The flash memory
module is also ideal for high performance code and data storage as well as data recording and accumulation.
The iSM001FLKA, composed of eight 1 Mb flash memories in plastic leaded chip carrier (N28F010), is organized as 524,288 words of 16 bits. The PLCCs are mounted, four to a side, together with 0.1 ,...F decoupling
capacitors on an 80-pin standard, low-profile module.
Extended erase and program cycling capability is designed into Intel's ETOXTM II (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional nonvolatile memory.
Intel's iSM001 FLKA Flash SIMM employs advanced CMOS circuitry for systems requiring high-performance
access speeds, low power consumption, and immunity to noise.. Its 120 ns access time provides no WAIT
state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of
0.8 mA translates into power savings when the memory module is deselected. Finally, the highest degree of
latch-up protection is achieved through Intel's unique EPI processing. Prevention of latch-Up is provided for
stresses up to 100 mA on address and data pins, from -1V to Vee + 1V.

4-129

October 1992
Order Number: 29024+006

int'et

iSM001FLKA

PO , -P07 {73-79} ~
00S-00'5 (62 55)

-

[lOa-DO; (70-63'
Ao-A ,S (52-36)

CEo (24)
CE, (23)
CE2 (22)
CE3 (21)
OE (4)

WEH

(5)
(6)

WEL ,.;..

~ Ao-A ,S 00-07

..... f-

CE

.

•

- -

OE

WE

Vss Vee Vpp

Vss Vee Vpp

J I
Ao-A '6 00-07

CE

WE

Vss Vee Vpp

I I

Vpp

~
(3)

=f

..

*

c7

CE

OE
WE

Vss Vee Vpp

Vss Vee Vpp

..

I II

Ao-A'6' 00-07

Co .. ·

I I I
Ao-A '6 °S-0'5

WE

OE

(2)

..

OE

CE

Vee

CE

Vss Vee Vpp

-

(2s)
(s4)

Ao-A ,S °S-0'5 ~

OE

CE

(1 )

I I

WE

Ao-A '6 00-07

Vss (80)

.

..

OE

.I
,

CE

OE

WE

,

•

Ao-A '6 °S-0'5 ~

"""

I I I
Ao-A '6 °S-0'5

CE

OE

WE

WE

Vss Vee Vpp

Vss Vee Vpp

I

-

-

I

=r =r
Co .. ·

c7

~
290244-1

Figure 1.ISM001FLKA Functional Block Diagram

4-130

infel .

iSM001FLKA

1-1'-'- - - - - - - 4.65" ------~___+l·1

~111~~~g~~Q~~g.!uu.~;.~1
FRONT VIEW'

Ttl&:'
0.33"

.... so
32-LEAD
a O 0 0
rc'--___
' __0_0__' __O_O___O_O_D
___~__::_::_::·_::_a
...... 1i' (55~LXC~50 MILS)
1

1 Mblt

0.05"+0.004/-0.003-11- SIDE VIEW

BACK VIEW

290244-2

Figure 2. iSM001FLKA Pin Configurations
Table 1. Pinout

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

18
19
20

VSS
Vee
Vpp
OE
WEH
WEL
NC
RES
RES
RES
RES
RES
RES
RES
RES
RES
NC
NC
NC
NC

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

CE3
CE2
CE1
CEO

Vss
RES
RES
RES
RES
NC
NC
NC
NC
NC
NC
A16
A15
A14

41

A11

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
,58

A10

59
60

A13 '
A12

4-131

Ag
As
A7
A6
A5

A4
A3
A2

61
62
63
64
65
66
67
68
69
70

OOg
OOs
007
006
005
004
003
002
001
000

Vpp
Vee

0014

71
72
73
74
75
76

0013

77

P05

0012

78
79
80

P06

A1
Ao

RES

Vss
0015

0011
0010

P01
P02
P03
P04

P07

Vss

int:el..

ISM001FLKA

Table 2. Pin Description
Symbol
Ao-A1S

Type
INPUT

Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.

INPUT/
OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data
during memory read cycles. The data pins are active high and float to tri-state
OFF when the chip is deselected or the outputs are disabled. Data is internally
latched during a write cycle.

CEo-CE3

INPUT

CHIP ENABLE: Activates each device's control logic, input buffers, decoders,
and sense amplifiers. Each line is unique to one set of 2 devices (word). CEx is
active low; CEx high deselects the mem0.!YEevice and reduces power
consumption to standby levels. Only one CEx may be active at a time.

OE

INPUT

OUTPUT ENABLE: Gates the devices outputs through the data buffers during a
read cycle. OE is active low.
'

WEH;WEL

INPUT

WRITE ENABLE controls writes to the control register and the array.
(WEH = High Byte; WEL = Low Byte)
Write enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
NOTE: With Vpp :;;; 6.5V, memory contents cannot be altered.

000- 0015

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing
the entire array, or programming bytes in the array (12V ± 5%).

Vee

DEVICE POWER SUPPLY: (5V

Vss

GROUND.

NC

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

'

± 10%).

Pin

Function

17

CE7

18

CEs

19

CE5

20

CE4

30

A22

31

A21

32

, A20

33 .

A19

34

A18

35

A17

..

.
.'

RES

RESERVED for future product enhancements.

P01..;.P07

PRESENCE DETECT: Denotes word depth (512K) and access time of device.
See Table 3, "Presence Detect "PO" Pins" on Page 5.

4·132

intel .

ISM001FLKA

Table 3. Presence Detect "PD" Pins
MODULE CAPACITY IDENTIFICATION
MODULE CAPACITY

PD6

PD2

PD1

NO MOOULE

0

0

0

WORD DEPTH
256K/32M

0

0

S

512K/64M

0

S

0

1M/128M

0

S

S

2M/256M

S

0

0

4M/512M

S

0

S

8M/1G

S

S

0

16M/2G

S

S

S

MODULE SPEED IDENTIFIC~TION
MAXIMUM
ACCESS
TIME

PD7

PD5

PD4

S

S

300ns

S
·S

S

S

0

250ns

S

S

0

S

S

S

0

0

S

0

S

S

150 ns

S

0

S

0

135ns

S

0

0

S

>300ns

200 ns
185 ns

..

PD3
I

S

120 ns

S

0

0

0

100ns

0

S

S

S

85ns

0

S

S

0

70ns

0

S

0

S

60 ns

0

S

0

0

50 ns

0

0

S

S

40ns

0

0

S

0

?Ons

0

0

0

S

NO

0

0

0

0

o -

OPEN CIRCUIT ON MODULE
S == SHORT CIRCUIT TO GROUND ON MODULE
NO = NOT DEFINED

4-133

,
/

infel .

ISM001FLKA

SINGLE IN-LINE MEMORY MODULE
BOARD
PC substrate: Glass Epoxy [0.05 H +0.004/-0.003
nominal thickness]. ihe iSM001 FLKA low-profile
SIMM mounts easily between expansion slots. See
Appendix A fora list of 80-pin socket suppliers.

APPLICATIONS
With high density, nonvolatility, and extended cycling
capability, Intel's iSM001 FLKA flash SIMMs offer an
innovative alternative to disk and battery-backed.
.
static R A M . '
Primary applications and operating systems can be
stored in flash, eliminating the slow disk-to-DRAM
download process. Performance is dramatically enhanced and power consumption is reduced-a consideration particularly important in portable equipment. Flexibility is increased with, Flash's electrical
chip erasure allowing in-system updates to operating
sy~tems and application code.,
',
In diskless workstations and terminals, network traffic is reduced to a minimum and systems are instanton. Reliability exceeds that of' electro-mechanical
media:. Often in these environments, power glitches,
force extended re-boot periods for all networked ter~
minals. This mishap is no longer an issue if boot '
code, operating systems, communication protocols
and primary applications are flash-resident in each
'
terminal.

.

.

For embedded systems that rely on dynamic RAMI " "
disk for main system memory or nonvolatile backup
storage, Flash SIMMs provide a solid state alterna"
tive in aminimal form factor. Flash memory provides
higher performance, lower power consumption and
instant-on capability. Additionally, flash is more rug"
ged and reliable in harsh environments where extreme temperatiJres and shock can cause disk-,
based systems to fail.
For systems' currently using a 'high-density static
RAM/battery configuration for ,code updates and
data accumulation, flash memory's inherent nonvolatility eliminates the need for battery backup. The
possibility of battery failure is removed. This consideration is important for portable equipment and medical instruments, both requiring continuous' performance. In addition, flash memory offers a four-to-one
cost advantage over SRAM.
Flash memory's electrical chip erasure, byte repro~
grammability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip~erasure gives the designer a "blank-slate" in
which to log or record data. Data can be periodically
off-loaded for analysis-erasing the slate and repeat'
ing the cycle.

Flash SIMMs add additional flexibility to designers
by offerir'!g end-users incremental expansion memO, . ry.A~ code requirements grow oras memory prices
drop, 'your customers have the, option of adding
more memory.

PRINCIPALS OF OPERATION
The iSM001 FLKA operates as eight N28F010 flash
memories connected as shown in the Functional
Block Diagram on Page 2.
The iSM001FLKA, organized as 512K x 16, can also
be configured for 8- and 32-bit systems.' For
32~bit systems, add a second SIMM to your design
, as currently done with DRAM. For byte-wide operation, buffer the SIMMs 000-007 and 008-0015
lines With an octal transceiver; then, tie the buffered
outputs together to form the 8-bit bus. Decode the
transceiver's enable input with an address line.
The iSM001 FLKA features hardware presence detect pins to facilitate memory design. The presence
detect pins (PD1-PD7)indieate module word depth
and maximum access speed (see Ta:ble 3 on the
previous page). The pins allow memory-specific
wait-state gen,eration upon system initialization. To
use the presence capability, pull-up the PD1-PD7
I!nes through a pull-up 'resistor. ,Read the lines
through a port and select the appropriate memory
depth and speed from a PO data ta:ble.
I~ the ab~ence of high .voltage ~m the modules Vpp
pins, the ISM001 FLKA IS a read-only memory array.
Manipulation of the mOcfule's control pins yields
standard read, standby and output disable functions.

Read, standby and output disable operations are
also available when high voltage is applied to the
Vpp pins. In addition, high voltage on the Vpp pins
enables erasure and programming of the module's
devices. All functions associated with altering the
memory contents of one or more devices-erase,
erase verify, program and program verify-are accessed via each flash device's command register.
Commands are written to a device's command register using standard microprocessor write 'timings.
Register cOntents serve as input to the devices internal state-machine which controls the erase and
programming circuitry. Write cycles to a device also
internally latch addresses and data, needed for programming or erase operations. With the appropriate
command written to a device's register, standard microprocessor read timings output array data, access
the intaligent identifier codes, or output data. for
erase and program verification.

4-134

ISM001FLKA

Table 4. Bus Operations
Pins

Vpp(1)

CE

OE

WE

VPPL

VIL

VIL

VIH

Data Out

VIH

VIH

Tri-State
Tri-State

DQO-DQ15

Operation
Read
READ-ONLY

READ/WRITE

Output Disable

VPPL

VIL

Standby

VPPL

VIH

X

X

VIL

VIL

VIH

DataOut(3)

Read

VPPH

Output Disable

VPPH

VIL

VIH

VIH

Tri-State

Standby(4)

VPPH

VIH

X

X

Tri-State

Write

VPPH

VIL

VIH

VIL

Data In(5)

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes are accessed via a command register write sequence. Refer to Table 5. All other addresses are l o w . '
.
3. Read operations with VPP = VpPH may access array data or the inteligen! IdentifierTM codes.
4. With VPP at high voltage, the standby current equals Icc + Ipp (standby).
5. Refer to Table 5 for valid Data-In during II write operation.
6. X can be VIL or VIH.

Integrated Stop TlmerSuccessive command write cycles define the duration of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated· 'program or erase.verify
commands. An integrated stop timer provides simplified timing control over these operations; thus elimi~
nating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until re-.
ceiving the appropriate verify or reset command.

Write Protection
A device's command register is only active when
Vpp is at high voltage. Depending upon the applica-

tion, the system designer may choose to make the
Vpp power supply switchable-available only when
memory updates are desired. When Vpp = VPPL,
the contents of. the register defaultto the read command, making the iSM001 FLKA a read-only memory. In this mode, the memory contents cannot be
altered.
Or, the-system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this instance, all operations are performed in conjunction with the command register.
The iSM001 FLKA is designed to accommodate either design practice, and to encourage optimization
of flash's processor-memory interface.
The following section first discusses byte-wide organization, building a basic understanding of byte-wide

bus operations, command definitions, and programming and erasure algorithms. The section concludes
with performance enhancements for both 16- and
32-bit systems.

BUS OPERATIONS
Read
Each of the iSM001 FLKA's flash memory devices
has two control functions, both of which must be
logically active, to obtain data. Chip-Enable (Q:x) is
the power control and should
used for device
selection. Four chip enables (CEo-CEa) control the
array's eight devices. Each line is unique to one set
of two devices (word). Only one Q:x may be active
at a time.

be

Output-Enable (OE) is the output control and should
be used to gate data from a device to the output pins
on the module, independent of device selection.
One DE line serves the iSM001FLKA's flash devices. Figure 7 illustrates read timing waveformli\.
When the Vpp lines are high (VPPH), a read operation can be used to access array data, to output a '
. device's inteligent identifier™ code, and to access a
device's data for program/erase verification. When
Vpp is low {Vppu, a read operation can only access
array data.
.

Output Disable
With the iSM001 FLKA's Output-Enable pin at a logic-high level (VIH), outputs from all devices are disabled. They are placed in a high-impedance state.

4-135

infel .

iSM001FLKA

STANDBY
With Chip-Enable at a logic-high level, the standby
operation disables most of the deselected devices
circuitry and substantially reduces device power
consumption. Tile outputs of the deselected devices
are place in a high-impedance state, independent of
the Output-Enable signal. If a word is deselected
during erase, programming, or program/erasure verification, the device draws active current until the operation is terminated.

Intelligent Identifier Operation
The intelligent identifier operation outputs the selected devices' manufacturer code (89H) and device
code (B4H). The manufacturer code and device
code are read via the devices' command register.
Following a write of 90H to a device's command register, a read from address location OOOOH outputs
the manufacture' code (89H) .. A read from address
0001 H outputs the device code (B4H).

Adevice's command register itself does not occupy
an, addressable memory location. The register is a
latch used to store the command, along with address and data information needed to execute the
command.
Two write enable lines are provided, WEH and
WEL, allowing selective write control of upper
and lower bytes_
.
A device's command register is written by selecting
the device (Chip-Enable low), then bringing WriteEnable (WEH or WEll to a logic-low level (VILl. If
both WE lines are a logic low, both upper and lower
bytes are written. Addresses are latched on the failing edge of the Write-Enable signal, while data is
latched on the rising edge of the Write-Enable pulse.
Standard microprocessor write timing are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.

COMMAND DEFINITIONS

Write
Erasure and programming is accomplished via each
device's command register, when high voltage is applied to the Vpp pins. The contents of each device's
register serve as input to its internal state-machine.
The state machine outputs dictate, the function of
each device.

When low voltage is applied to the module's Vpp
pins, the contents of all devices' command registers
default to OOH, enabling read-only operations.
Placing high voltage on the module's Vpp pins allows read/write operation on selected.devices. Operations are selected by writing specific data patterns to the device(s) command register. Table 5 defines these register commands:

Table 5_ Command Definitions
Command
Read Memory
Read Intelligent Identifier Codes(4)
Set-up Erase/Erase(S)
Erase Verify(S)
Set-up Program/Program(6)
Program Verify(6)
Reset(7)

Bus
First Bus Cycle
Second Bus Cycle .
Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)
1

3
2
2
2
2
2

X
X
X

Write
Write
Write
Write
Write
Write
Write

EA

X
X
X

OOH
90H
20H
AOH
40H
COH
FFH

Read
Write
Read
Write
Read
Write

(4)

X
X
PA

NOTES:
1. Bus operations are defined in Table 4.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to beread during erase verify.
PA = Address,of memory locationto be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = ,Data read from location IA during device identification (Mfr = 89H, Device B4H).
. EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 4 illustrates the Quick-Erase™ Algorithm.
6. Figure 3 illustrates the Quick-Pulse Programming™ Algorithm.,
7. The second bus cycle must be followed by the desired command register write.

4-136

X
X

(4)
20H
EVO
PO
PVO
FFH

in1"el .

ISM001FLKA
with the rising edge of the next Write-Enable pulse
(i.e., Erase-Verify Command).

Read Command
While Vpp is high, for erasure and programming, the
selected devices memory contents can be accessed
via the read command. The read operation is initiated by writing OOH into the command register of each
device. Microprocessor read cycles retrieve array
data. The selected devices remain enabled for reads
until their command register contents are altered.
The default contents of each device;s command
register upon Vpp power-up is OOH. This default value ensures that no spurious alteration to the
iSM001 FLKA's memory contents occurs during the
Vpp power transition. Where the Vpp supply is hardwired to the iSM001 FLKA's Vpp pins, all eight devices power-up and remain enabled for reads until their
command-register contents are changed. Refer to
the AC Read Characteristics and Waveforms for
specific timing parameters.

. Intelligent Identifier Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system.
Each flash memory device contains an Intelligent
identifier operation. The operation is initiated by writing 90H into the command register. Following the
command write, a read cycle from address OOOOH
retrieves the manufacturer code of 89H. A read cycle from address 0001 H returns the device code of
B4H. To terminate the .operation, it is necessary to
write another valid command into the register.
The intelligent identifier and the Presence Detect
pins give you complementary information. While the
PO pins denote speed a.nd depth, the intelligent
identifier operation gives you manufacture and device data

Set-Up Erase/Erase Commands
Set-up Erase is a command-only operation that
stages a selected device for electrical erasure of all
bytes in its array. The set-up erase operation is performed by writing 20H to the command register.
To commence Chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of a
Write-Enable pulse (WEH or WEll and terminates

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pins. In the
absence of this high voltage, memory contents are
protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

Erase-Verify Command
The erase command erases all bytes of the selected
device(s) in parallel. After each erase operation, all
bytes must be verified. The erase verify operation is
initiated by writing AOH into the command register of
the device. The address for the byte to be verified
must be supplied as it is latched on the falling edge
of a Write-Enable pulse. The register write terminates the erase operation with the rising edge of its
Write-Enable pulse.
.
Each 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte of the device until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes of
the device have been verified, the erase step is
complete. The device can be programmed. At this
point, the verify operation is terminated by writing a
valid command (e.g., Program Set-up) to the command register of the device. Figure 4, the QuickErase™ algorithm, illustrates how commands and
bus operations are combined to perform electrical
erasure of each 28F010. Refer to AC Erase. Characteristics and Waveforms for specific timing parameters.

Set-Up Program/Program Commands
Set-up program is a command-only operation that
stages·a device for byte programming. Writing 40H
into the command register of the device performs
the set-up operation.

+137

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ISM001FLKA

Once the prograiTlset-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on·'the falling edge of the Write-En. able pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of. Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.

EXTENDED ERASE/PROGRAM CYCLING
EEPROM pycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literaiiy tear apart the
oXid~ at defect regions. To combat this, some
suppliers have implemented redundancy schemes,
reducing pycling failures to insignificant levels. However, redundancy. requires that cell size be doubled-an expensive solution.
'

Program-Verify Command
Each 28F010 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at
random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the commaridregister of the device. The
register write terminates the programming operation
with the rising edge of its~Write-Enable pulse. The
program~verify operationst gesthe device for verification of the byte last progr mmed. No new address
information is latched.
.' ,
Each 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read' pycle
outputs the data. A successful comparison between
theprcigrammed byte and true data mearis that the
byte is successfully programmed. Programming then
proceeds' to the next desired byte location. Figure 3,
the Quick-Pulse Programming™ algorithm (8-bit
Systems), illustrates how commands are combined
with bus operations to', perform byte programming.
Refer' to ACProgrammirig Characteristics' and
Waveforms for specific timing parameters.

Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences to
a device. Following either set-up command .(erase or
program) with two consecutive writes of FFH will
safely abort the operation. Memory contents will not
be altered. A valid command must then be written to
place the device in the desired state..

Intel has designed extended CYCling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oXide increases the charge carrying ability ten-fold. Second, the oXide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally; the peak
electric field .during erasure is approximately
2 MVlcm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.
Each of the iSM001 FLKA's eight 28F010s is specified for a minimum of 10,000 program/erase cycles.
Each device is programmed and erased using Intel's
Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a series of
operations (pulses), along with byte verification, to.
completely and reliably erase and program the davice.
For further information; see Reliability Report RR-60
(ETOX II Reliability Data Summary).
QUICK-PULSE .PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm' uses programming operations of 10 p.s duration. Each operation is followed by' a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence. of programming .and byte verification is
performed with Vpp at high voltage. Figure 3 illustrates the Quick-Pulse Programming algorithm for
8-bit systems.

4-138

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ISM001FLKA

QUICK·ERASE ALGORITHM
Intel's Quick·Erase algorithm yields fast and reliable
electrical erasure of memory· contents. The algo·
rithm employs a closed·loop flow, similar to the
Quick-Pulse Programming™ algorithm, to simulta-.
neously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
iSM001 FLKA is erased when shipped from the fac·
tory. Reading FFH data from each device would im·
mediately be followed by device programming.

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data otl1er than FFH is en·
countered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure. typically occurs in one sec·
ond. Figure 4 illustrates the Quick-Erase algorithm
for a-bit systems.
.

For devices being erased and reprogrammed, uni·
form and reliable erasure is ensured by first pro·
gramming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approxi·
mately two seconds.

4-139

ISM001FLKA

Bus
Command
Operation

Standby

Comments

Walt for Vpp Ramp to VPPH(1)

Initialize Pulse-Count

Write

Set-up
Program

Data = 40H

Write

Program

Valid Address/Data

Standby
Write

Duration of Program
Operation (twHWH1)
Program(3) Data = COH; Stops Program
Verify
Operation(4)

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected
/

Write

Standby

Read

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VpPL(2)

290244-3

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
2. See DC Characteristics for value of VPPH and VPPL.

3. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written .with the Read command.
4. Refer to principles of operation

Figure 3. Quick-Pulse Programming Algorithm (a-Bit Systems)

4·140

inteL

iSM001FLKA

Bus
Command
Operation

Comments

Entire Memory MU,st
Before Erasure

=

OOH

Use Quick-Pulse
Programming™ Algorithm
(Figure 4)
Standby

Wait for VPP Ramp to VPPH(2)

Initialize Addresse~ and
Pulse-Count

Write

Set-up
Erase

Data

=

20H

Write

Erase

Data

=

20H

Duration of Erase Operation
(twHWH2)

Standby

Standby

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(4)
tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Write

Erase(3)
Verify

Read

Standby

290244-4
NOTES:
,
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
2. See DC Characteristics for value of VPPH and VPPL.

Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp to Vppd2)

I

3. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
4. Refer to principles of operation.

Figure 4. Quick-Erase Algorithm (a-Bit Systems)
4-141

iSM001FLKA

HIGH PERFORMANCE PARALLEL
DEVICE ERASURE

HIGH PERFORMANCE PARALLEL
DEVICE PROGRAMMING

Total erase time for the iSM001 FLKA is reduced by
implementing a paraiiei erase aigorithm (Note ij.
You save time by erasing all devices at the same
time. However, since flash memories may erase at
different rates, you must verify each device separately. This can be done in a word-wise fashion with
the command register Reset command and a special masking algorithm.

Software for word- or double-word programming can
be written in two different manners. The first method
offers simplicity of design and minimizes software
overhead by using a byte programming routine on
each device independently (using host CPU's byte
addressing mode). The second method offers higher
performance by programming the word or doubleword data in parallel. This method manipulates the
command register instructions for independent byte
control. See Figure 6 for conceptual 2-device parallel programming flow chart and Appendix C for the
detailed version. Here you can use the host CPU's
appropriate word- or double-word addressing modes
(Le., incrementing by 2- or 4-byte addresses, respectively).

Take for example the case of two-device (parallel)
erasure. The CPU first writes the data word erase
command 2020h twice in succession. This starts
erasure. After 10 ms, the CPU writes the data word
verify command AOAOh to stop erasure and setup
erase verification. If both bytes are erased at the
given address, then the CPU increments the address (by 2) and then writes the verify command
AOAOh again. If neither byte is erased, then the CPU
issues the erase sequence again without incrementing the address.

NOTE:
Word or double-word programming assumes 2 or 4
8-bit flash memory devices.
Parallel Programming Algorithm Summary:

Suppose at the given address only the low byte verifies FFh data? Could the whole chip be erased? The
answer is yes. Rather than check the rest of the low
byte addresses independently of the high byte, simply use. the reset command to mask the low. byte
from erasure and erase verification on the next
erase loop. In this example the erase command
would be 20FFh and the verify command would be
AOFFh. Once the high byte verifies at that address,
the CPU modifies the command back to the default
2020h and AOAOh, increments the address by 2, and
writes the verify command to the next address.
See Figure 5 for a conceptual view of the parallel
erase flow chart and Appendix B for the detailed version. These flow charts are for 16-bit systems and
can be expanded for 32-bit designs.

NOTE:
1. Parallel Erasure and Programming require appropriate choice of Vpp supply to support the increased power consumption.

4-142

• Decreases programming time by programming 2
flash memories (16 bits) in parallel. The algorithm
can be expanded for 32-bit systems.
• Eliminates tracking of highllow byte addresses
and respective number of program pulses by directing the CPU to write data-words (16-bit) to the
command register.
• Maintains word write and read operations. Should
a byte on one device program prior to a byte on
the other, the CPU continues to write word-commands to both devices. However, it deselects the
verified byte with· software commands. An alternative is to independently program high and low
bytes using hardware select capability (byte-addressing mode of host CPU).

intel~

iSM001FLKA

RAISE Vpp
PROGRAM ALL DEVICES TO DOh
RESET ALL VARIABLES
ISSU,E ERASE COMMAND - - - - - - - . . ,
TIME OUT
VERIFY COMMAND
[

.J!...

BOTH DEVICES ERASED
MASK·
,HI-OR LO-BYTE
Y
COMMANDS

I

N LAST ADDRESS

LAST PULSE

I

IY

~

Y
ERROR

DONE

290244-5

·You mask the device by substituting a Reset command for the Erase and Verify commands. That way, the erased byte
idles through the next erase loop.

Figure 5. High Performance Parallel Erasure (Conceptual Overview)

RAISE Vpp
GET ADDRESS/DATA WORD
--- RESET COMMAND AND
COUNTER VARIABLES
PROGRAM DATA - - - - - - - - - - - - - - - . . ,
WORD

!
!

TIME OUT 10).'s

STOP PROGRAMMING WITH
PROGRAM VERIFY COMMAND

!
!

N
MASK HI OR LO BYTE
DATA WORD PROGRAMMED? - - INCREMENT PULSE COUNTER
Y

N

LAS~ PjULSE?

~MOREDATA?

Y

!N.

WRITE READ COMMAND
LOWER Vpp
PROGRAMMING COMPLETE

WRITE READ COMMAND
LOWER Vpp
PROGRAM ERROR

290244-6

·You mask the device by substituting a Reset command for the Program and Verify commands. That way; the programmed bytes do not get further programmed on subsequent pulses.

Figure 6. Parallel Programming Flow Chart (Conceptual Overview)

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ISM001FLKA

DESIGN CONSIDERATIONS

Power Up/Down Protection

Two-Line Output Control
Two-line control provides for:
a. the. lowest possible memory power dissipation
'
.
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while' the system's read signal controls all flash. memories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power- standby condition.

Power Supply Decoupling

The iSM001 FLKA is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, each 28F010 is
indifferent as to which power supply, Vpp or Vee,
powers up first. Power supply sequencing is not required. Internal circuitry in each 28F010 ensures that
the command register is reset to the read mode on
power up.
'
A system designer must guard against active writes
for Vee v0!!!9.es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the .two-step
command sequences.

Power Dissipation

Flash-memory power-switching characteristics require careful device decoupling. System ,designers
are interested in three supply current .(leC> issuesstandby, active,' and transient current peaks pro-duced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-lin~

control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iSM001 FLKA features a 0.1 ,...F ceramic· capacitor
connected between Vee and Vss, and between Vpp
and Vss.
-

When designing portable systems, designers must·
consider battery power consumption not only during
device operation, but also for ~ata retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because each
·28F010 does not consume any power to retain code
or data when the system is off. Table 4 iliustrates the
power dissipated when updating each 28F010.
Table 4. 28F010 Typical Update Power
Dlsslpatlon(4)

Also, a 4.7 ,...F tantalum capacitor decouple~ the array's power supply between Vee and Vss and between Vppand Vss. The bulk capacitors will overcome voltage slumps caused by printed-circuit~
board trace inductance, and will supply charge to
the smaller capacitors as needed.

Operation
Array Program/Program Verify(l)

Power
Dissipation
.(Watt-8econds)
_ 0.171

Array Erase/Erase Verify(2)

0.136

One Complete Cycle(3)

0.478

NOTES:

Vpp Trace on Printed Circuit Boards
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The two Vpp pins supply current for programming. Use similar trace widths and layout considerations given the Vee power bus. Adequate Vpp
supply traces and decoupling will decrease Vpp voltage spikes and overshoots. Be sure to connect both
module Vpp inputs to your 12V supply.

1. Formula to calculate typical Program/Program Verify
. Power. = [Vpp x {I Bytes x typical {I Prog Pulses
(tWHWH1 X IpP2 typical + twHGL X IpP4 typical») + [Vcc
X {I Bytes X typical {I Prog Pulses (twHWH1 X ICC2 typical + tWHGL X ICC4 typical).
,2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp (VPP3 typical X tERASE typical + IpP5 typical X
twHGL X {I Bytes») + [Vcc (IC03 typical X tERASE typical
+ ICC5 typical X tWHGL X {I Bytes)).
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals are not guaranteed but based on a limited
number of samples taken from production lots.

4-144

infel .

ISM001FLKA

ABSOLUTE MAXIMUM RATINGS'"
Operating Temperature
During Read .................. 0·Cto +70·C(1)
During Erase/Program ........... O·C to + 70·C
Temperature Under Bias ......... -1 O·C to + BO·C
Storage Temperature .......... - SO·C to + 100·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to

NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These a,re stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

'+ 14.0V(2, 3)

Vee Supply Voltage with
Respect to Ground .......... -'-2.0V to + 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + O.SV;which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS
Symbol

Limits

Parameter

TA

Operating Temperature

Vee

Vee Supply Voltage

Unit

Comments

70

·C

For Read-Only and
Read/Write Operations

5.50

V

Min

Max

0
4.50

4-145

'-'

infel~

ISM001FLKA

DC .CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Notes

Limits

M!n

Typ

Ma~

Unit

Test Conditions

III

Input Leakage Current

3

±8.0

p,A

Vee = Vcc Max
VIN = Vee or Vss

ILO

Output Leakage Current

:3

±40.0

p,A

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1,3

8.0

rnA

Vee = Vee Max
CE = VIH

lee1

Vee Active Read Currtlnt

2,3

26

66

rnA

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lec2

Vee Programming Current

2,3

8.0

26

rnA

Programming in Progress

ICC3

Vee Erase Current

2,3

16.0

36

rnA

Erasure in Progress

lec4

Vee Program Verify Current

2,3

16.0

36

mA

Vpp = VpPH
Program Verify in Progress

lecs

Vee Erase Verify Current

2,3

16.0

36

rnA

Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

3

±80

p,A

Vpp ~ Vee

IpP1

Vpp Read Current
or Standby Current

3

IpP2

Vpp Programming Current

0.7

2,3

1.6

rnA

Vpp> Vee

±80

p,A

Vpp ~ Vee

16.5

61.2

rnA

Vpp = VpPH
Programming in Progress

.
IpP3

Vpp Erase Current

2,3

12.5

61.2

rnA

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

2,3

4.5

11.2

mA

Vpp = VPPH
Program Verify in Progress

Ipps

Vpp Erase Verify Current

2,3

4.5

11.2

rnA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

2.4

VPPL

Vpp during Read-Only
Operations

0.00

VpPH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write
Lock Voltage

Vee

+ 0.5

0.45

V
V

IOL = 5.8 rnA
Vee = Vee Min

V

IOH =-2.5mA
Vee = Vcc Min

6.5

V

NOTE: Erase/Program are

12.60

V

Inhibited when Vpp = VPPL

2.5

V

NOTES:

1. Vee standby current for 8 devices..
2. Calculations assume only the 2 devices of the 16-bit word are enabled. The remaining 6 devices are in standby.
Current will be higher if interleaving is used.
3. All currents are in RMS unless otherwise noted. Typical values at Vce = S.OV, Vpp = 12.0V, T = 2s'e. These currents
are valid for all product versions (packages and speeds).
4-146

intel .

iSM001FLKA

DC CHARACTERISTICS-CMOS COMPATIBLE·
Symbol

Parameter

Notes

Limits
Min

Typ

Max

Unit

Test Conditions

III

Input Leakage Current

3

±8.0

p.A Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

3

±40.0

p.A Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1,3

0.4

0.8

rnA

lee1

Vee Active Read Current

2,3

20.3

60.6

rnA Vee = Vee Max, CE = VIL
f =6 MHz, lOUT = 0 rnA

lee2

Vee Programming Current

2,3

2.3

20.6

rnA Programming in Progress

lee3

Vee Erase Current

2,3

10.3

30.6

rnA Erasure in Progress

leC4

Vee Program Verify Current

2,3

10.3

30.6

rnA Vpp = VPPH
Program Verify in Progress

lees.

Vee Erase Verify Current

2,3

10.3

30.6

rnA Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±80

p.A Vpp ~ Vee

IpP1

Vpp Read Current
or Standby Current

1.6

rnA Vpp> Vee

3

0.7

Y.s;;p

= VeeMax
CE = Vee ±0.2V

±80

p.A Vpp ~ Vee

IpP2

Vpp Programming Current

2,3

16.5

61.2

rnA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

2,3

12.5

61.2

rnA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

2,3

4.5.

11.2

rnA Vpp = VPPH
Program Verify in Progress

Ipps

Vpp Erase Verify Current

2,3

4.5

11.2

rnA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

0.8
Vee

+ 0.5

0.45

V
V
V

VOH1
Output High Voltage

0.85 Vee

V

VPPL

Vpp during Read-9nly
Operations .

0.00

6.5

V

VPPH

Vpp during Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write
Lock Voltage

2.5

IOH = - 2.5 rnA,
Vee = Vee Min
IOH = -100 p.A,
Vee = Vee Min

Vee - 0.4

VOH2

IOL = 5.8 rnA
Vee = Vee Min

NOTE: Erase/Program are
Inhibited when Vpp = VPPL

V

NOTES:
1. Vcc standby current for 8 devices.
2. Calculations assume only the 2 devices of the 16-bit word are enabled. The remaining 6 devices are in standby.
Current will be higher if interleaving is used.
3. All currents are in RMS unless otherwise noted. Typical values at Vcc = S.OV, Vpp = 12.0V, T = 2Soe. These currents
.
are valid for all product versions (packages and speeds).

4-147

intel..

iSM001FLKA

CAPACITANCE(1} TA = 25°C, f = 1.0 MHz
Symbol
CINl

Limits

Unit

Conditions

Parameter

Notes

Address Capacitance

2

60

pF

VIN =OV

pF

VIN = OV

pF

VOUT = OV

Max

Min

CIN2

Control Capacitance

2

65

COUT

Output Capacitance

2

55

NOTES:
.
1. Trace capacitance calculated, not measured.
2. Address and control capacitance of a typical device is 6 pF.
3. Output capacitance of a typical device is 12 pF.

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................ 0.45V and 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V

AC CHARACTERISTIC5-Read-Only Operatlons(2)
Versions
Symbol

Characteristic

ISMOO1FLKA·120

Notes

Min

3

Max

ISMOO1FLKA·200
Min

Max

200

tAVAV/tRC

Read Cycle Time

120

tELQV/tCE

Chip Enable
Access Time

120

tAVQV/tACC

Address Access
Time

tGLQV/tOE

Output Enable
Access Time

tELQXltLZ

Chip Enable to
Output in Low Z

3

tEHQZ

Chip Disable to
Output in High Z

3

tGLQXltoLZ

Output Enable to
Output in Low Z

3

tGHQZ/tOF

Output Disable to
Output in High Z

4

toH

Output Hold from

3

Unit
ns

200

ns

120

200

ns

50

60

ns

..

0

0
55

0

ns
55

0
30

ns
·ns

40

ns

0

0

ns

6

6

/Ls

Address,~,

or <:>E Change
tWHGL

Write Recovery
Time before
Read

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time s; 10 ns.
3. Not 100% tested: Characterization data available.
4. Guaranteed by design.
I

4·148

_.

l
~

Vee POWER-UP

X

X

X

DEVICE AND
ADDRESSc SELECTION

STANDBY

X

OUTPUTS ENABLED

DATA VALID

STANDBY

Vee POWER-DOWN

X
ADDRESS STABLE

ADDRESSES

---.-t AVAV (t RC)

---------------1

::!!

~
Cil

CE (E)

:"'I
~

o

i

.!..


0

WE

en

tGHQZ

I WHGL

i:
Q

(lor)

1/1

....

Q

(iii)

"11

r
l>

"IJ

'"

I GLQV (IOE)

0

...

C

t ........ "

II)

3

2-

::J

C

DATA (DQ)

0

'U

..

...CD
II)

II

S.OV
Vee
OV
I VPEL
120V

i---

Vpp
v pPL

290244-12

l
•

ADDRESSES .

CE (E)

::!I
CI
c

;

....
~

l;1

DE (G)

~
<

.jIo.

.!.

tWHWL (tWPH)

!.
0

3

~ ~

.

tWHWH2

M(W)

0

tGLQV (Io~

m

L-- t.,..f t V

iii
1/1

en

!c;HQZ
(tDr)

tWHGL

i:

~

L-- twDX

CD

il

I

DATA (00)

HIGH Z

:I
1/1

5.DV
Vee
OV
IyPE!.

120V
. Vpp

~

- r-'-..

VPPL

290244-13

...
0
0

"'II

r

~

)10

intel .

ISM001FLKA

ALTERNATIVE CE-CONTROLLED WRITES
28F010-120

Versions
Symbol

tAVAV

Characteristic

Notes

Min

120

Write Cycle Time

Max

28FO 10-200
Min

200

Unit

Max

ns

tAvEL

Address Set-Up Time

0

0

ns

tELAX

Address Hold Time

80

95

ns

tDVEH

Data Set-Up Time

50

50

ns

tEHDX

Data Hold Time

10

10

ns

tEHGL

Write Recovery Time
before Read

6

6

,..,S

tGHEL

Read Recovery Time
before Write

0

0

fJ-s

tWLEL

Write Enable Set-Up Time
before Chip Enable

0

0

ns

tEHWH

Write Enable Hold Time

tELEH

Write Pulse Width

1

0

0

ns

70

80

ns
ns
fJ-s

tEHEL

Write Pulse Width High

20

20

tVPEL

Vpp Set-Up Time to Chip
Enable Low

1.0

1.0

NOTE:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4-155

_.

~~
aloof

i!!l
~

Vee POWER-UP I:
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM CO....AND
LATCH ADDRESS I: DATA PROGRAM ..ING

PROGRA..
VERIFY

PROGRA..
VERIFICATION

CO.. MAND

aI

61
fl

.,.
-

ID

c

;

,....

-•...
~

•::J

III

l;

i"
~
0)

icr

3
III

-a...
0

'V

STANDBY/
Vee POWER-DOWN

---*

•. ===A

~.

g,
-al

Co

::E
::I.

Ii

WE (E)

=!
~.

::I

IC

'"

!!!.

l!l

~

OE (G)

'0

-<

us~

Sal

,.

iiaI
0

~

tEHEH

.,.

t EHGL

'~

CE(W)

i0

::I

DATA (DO)

HIGH Z

5'

ID

0

•
io·

::J

III

~J

~.

12.DV
Vpp

PPL
V

g....

.,.r~

~DX

!"

iii

'a

•

ADDRESSES

ID

:I
:I

l

290244-19

intel .

iSM001FLKA

APPENDIX A
PARTIAL LIST(1) OF SO-PIN SIMM SOCKET COMPANIES

AMP INCORPORATED
HARRISBURG, PA 17105
(800) 522-6752
BURNDY CORPORATION
51 RICHARDS AVENUE
NORWALK, CT 06856
(203) 838-4444
MOLEX
2222 WELLINGTON COURT
LISLE, IL 60532
(708) 969-4550
NOTES:
1. This list is intended for example only, and in no way represents all companies that support SO-pin SIMM Sockets. Intel
Corporation assumes no responsibility for circuitry other than circuitry embodies in an Intel product. No other circuit patent
licenses are implied.
.
2. Socket reliability data can be obtained from the above companies upon request.

4-157

ISM001FLKA

APPENDIX B
PARALLEL ERASE FLOW CHART

COMMENTS

Wait for Vpp to stabilize.
Use Quick-Pulse Programming
algorithm.
INITIALIZE:
TEW

Initialize Variables:
.TEW = Erase duration (width)
PLSCNT = Pulse Counter
ADRS = Address
E......COM = Erase Command
V_COM = Verify Command

=10m.

PLSCNT = 0
ADRS = 0
LCOM = 2020H
V_COM. AOAOH

=

Er~se Set-up Command
Start Erasing
Duration of Erase Operation.

Erase Verify Command stops
erasure.
See next page for subroutine.

When both devices at ADRS are
erased. F~ATA= FFFFH.
If not equal. increment the pulse
counter and checkJor last pulse.
Reset commands to default
(E......COM == 2020H.
V_COM = AOAOH)
before verifying next ADRS.

Reset devices for read operation.
Turn off Vpp.

290244-14

4-158

infel .

iSM001FLKA

Device Erase Verify and Mask Subroutine
COMMENTS
This subroutine reads the data word
(F_DATA). It then masks the HI or
LO Byte of the Erase and Verify
commands from executing during
the next operation.

If both HI and LO bytes verify, then
return.

Mask" the HI Byte with OOH.

If the LO Byte verifies erasure, then
mask" the erase and' verify
commands with OOFFH(Reset).

Mask" the LO Byte with OOH.

If the HI Byte verifies erasure, then
mask" the erase and verify
commands with FFOOH(Reset).

290244-15

NOTE:
"Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming flash
data (F_DATA), the erase commands and the verify commands. Then manipulate the HI or LO register contents.

4-159

infel .

iSM001FLKA

APPENDIX C
PARALLEL PROGRAMMING FLOW CHART

COMMENTS

Wait for Vpp ramp to VPPH
PLSCNT = Pulse Counter
ADRS = address to program
P_DAT = data word to program
Initialize Data Word Variables:
V_DAT = valid data
P_COM = Program Command
V_COM = Verify Command

Program Set-up Command
xx = Address don't care
Program
See next page for subroutine
Program Verify Command

F_DA T = flash memory data
Compare flash memory data
to valid data (word compare). If not
equal, increment pulse counter
and check for last pulse. II not last
pulse, compare High and Low
Byte.

Check buffer or 1/0 port lor
more data to program.
Reset device for read operation.

Turn off Vpp.

290244-16

4-160

ISM001FLKA

Program Verify and Mask Subroutine
COMMENTS

MASK· the HI Byte with OOH.

>--1"

P_COM
V_OAT
V_COM

=(P _COM OR OOFFH)

= (V_OAT OR DOFFH)
= (V_COM OR OOFFH)

If the LO Byte Verifies, then;
mask· the program and verify
command with OOFFH
(RESEn.

Mask· the LO Byte with OOH.

>--1"

P_COM
V_OAT
V_COM

= (p_COM OR FFOOH)
FrOOH)
= (V _COM OR FFOOH)

= (LDAT OR

If HI Byte Verifies, then mask·
the program and erase
command with FFOOH
(RESEn.

290244-17

NOTE:
·Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming flash
data (F_DATA), the erase commands and the verify commands. Then manipulate the HI or LO register contents.

4·161

iSM001FLKA

Ordering Information

r

L

I

L

REVISION

ACCESS SPEED (ns)
120 ns
.
200ns

' - ARCHITECTURE
K=x16
' - FL
-

= FLASH

DENSITY (t.4B)
001
1 t.4EGABYTE

=

PACKAGE
St.4 80-PIN SIt.4t.4

=

'-INTEL

290244-18

Valid Combinations: .
iSM001 FLKA-120
iSM001 FLKA-200

ADDITIONAL INFORMATION

Order Number

ER-20, "ETOXTM II Flash Memory Technology"

294005

ER-24, "The Intel 28F01 0 Flash Memory"

294008

RR-60, "ETOXTM II Flash Memory Reliability Data Summary"

293002

AP-316, "Using Flash Memory for In-System Reprogrammable
Nonvolatile Storage"

292046

AP-325, "Guide to Flash Memory Reprogramming"

292059

AP-343, "Flash Memory -

292079

A Mass Storage Medium"

REVISION HISTORY
Number

Description

-006

Correct Name change
Change order number

4-162

iSM002FLKA
2 MBYTE (1024K x 16) CMOS FLASH SIMM
High-Performance
• -150
ns Maximum Access Time

•
•
•
•
•

-13.3 MB/s Read Transfer Rate
10,000 Rewrite Cycles Minlmuml
Component
Flash Electrical Chip-Erase
- 2 Second Typical Chip-Erase
16 J.ls Typical Word Write
- Up to 1 Mb/s Write Transfer Rate
Inherent Non-volatility
- No Batteries or Disk Required for
Back-up
- OW Data Retention Power
CMOS Low Power Consumption
- 20.3 mA Typical Active Current
- 0.4 mA Typical Standby Current

•
•
•
•-

Standard 80-Pin Insertable Module
- 0.050 Centerline Lead Spacing
- Upgrade Path through 128M bytes
Hardware Presence Detect
Command Register Architecture for
Microprocessor/Microcontrolier.
Compatible Write Interface
Noise Immunity Features
± 10% Vee Tolerance
- Maximum Latch-Up Immunity
Through EPI Processing.
12.0V ± 5% Vpp

•
Program/Erase Stop Timer
• Integrated
ETOXTM II Nonvolatile Flash
• Technology
- High-Volume Manufacturing
Experience

Intel's iSM002FLKA flash SIMM (Single In-Line Memory Module) is targeted at high-density read/write nonvolatile memory. The iSM002FLKA enables you to optimize board space; to offer incremental memory expansion
similar to today's DRAM; and to assure continued access to today's and tomorrow's surface-mount technologies. Intel's iSM002FLKA offers a reliable sold-state alternative for mass storage. The flash memory module is
also ideal for high performance code and data storage as well as data recording and accumulation.
The iSM002FLKA, composed of eight 2 Mb flash memories in plastic leaded chip carrier (N2BF020), is organized as 1,04B,576 words of 16 bits. The PLCCs are mounted, four to a side, together with 0.1 JLF decoupling
capacitors on an BO-pin standard, low-profile module.
.
Extended erase and program cycling capability is designed into Intel's ETOXTM II (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional nonvolatile memory.
Intel's iSM002FLKA flash SIMM employs advanced CMOS circuitry for systems requiring high-performance
access speeds, low power consumption, and immunity to noise. Its 150 ns access time provides no WAIT
state performance for a wide range of microprocessors and micro<:ontrollers. Maximum standby current of
O.B mA translates into power savings when the memory module is deselected. Finally, the highest degree of
latch-up protection is achieved through Intel's unique EPI processing. Prevention of latch-up is provided for
stresses up to 100 mA on address and data pins, from - 1V to Vee + 1V.

4-163

October 1992
Order Number: .290465-001

ISM002FLKA

po, -p~ (73-79) •
DOs-DO, 5 (62-55)
DOo-1X? (70-63)

,

Ao-At7 (52-35)
CEo

(24)
(23)

~
CE2 (22)
. CE3 (21)
OE (4)

"

(5)

WEii
(6)
WEi. .;..

--

~ Ao-At7
l - CE

°o-~ ~

-

OE

... Ao-At7
-

WE
Vss

Vee

Vpp

Vss

I I I
~

Ao-AI7

Oo-~

Vpp

Vss

Ao-AI7

... Ao-AI7

°o-~ ~

WE

Vss vee

Vpp

Vss

I
Ao-At7

°o-~

-

!-

CE
OE

(54)
(80)

(2)
Vee
Vpp

~
(3)

*ea ... *<7

I

Vpp

vee

I I I
Ao-At7

08-0,5

CE
OE

-

WE

WE

Vss

08-0,5 ~

CE
OE

WE

Vss

Vpp

vee

J

CE
OE

Ctsr

l-

WE

I I I

(1)

08-0,5

CE
OE

Vss vee

0-

Vpp

Vee

... Ao-At7

~

WE

~

I-

I I I

CE
OE

~

°S-0,5

CE.
OE
WE

vee

Vpp

Vss

vee

Vpp

I

"

T Co '"

:: ~<7

~
290465-1

Figure 1.ISM002FLKA Functional Block Diagram

4-164

infel .

ISM002FLKA

I.

-I

·uS"

~l DooDooDooD'~

11 '"

, ==~Ol

1111 11111111 lllIIlUi'" II 1111 II W II "'III 1111,11 1111111 ""'""" II 8

~

FRONT VIEW
0.33"

, 00'
0 000 00"
0
O

1....-_ _
" ...;..'- : - -_ _ _ _'_'_ _
'

....

T'l'
----I--*---h
80

0 1II;:li~ 0

0.7"

_0_11_1111_11

BACK VIEW

0.05" + 0.004/-0.003

32-LEAD
1 IAbit
PLCC
,'(550 x 450 IAILS)

-II-

SIDE VIEW
290465-2

Figure 2. ISM002FLKA Pin Configurations
Table 1. Pinout

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17'

18
19
20

VSS
Vee
Vpp
OE
WEH
WEL
NC
RES
RES
RES
RES
RES
RES
RES
RES
RES
NC
NC
NC
NC

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

CE~

CE2

GET,
CEO

Vss
RES
RES
RES
RES
NC
NC
NC
NC
NC
A17
A16
A1S
A14
A13
A12

4·165

61
62
63
64
65

DOg

As

66

004

As

67
68
69
70
71
72
73
74
75
76

003

Vpp
Vee

0013

77

POs

0012

P06

0011

78
79

0010

80

Vss

A11
A10
Ag
Aa
A7

~

A3
A2
A1
Ao

RES

Vss
0015
,0014

OOa
007
006
005

002
001
000

P01
P02
P03
P04

P07

iniaL

iSM002FLKA

Table 2. Pin Description
Symbol

Ao-A17

Type

Name and Function

INPUT

ADDRESS INPUTS for memory addresses. Addresses 8i9 intsfnaiiy iatched
during a write cycle.

INPUT/
OUTPUT

DATA INPUT/OUTPUT: Inputs data.during memory write cycles; outputs data
during memory read cycles. The data pins are active high and float to tri-state
OFF when the chip is deselected or the outputs are disabled. Data is internally
latched during a write cycle. .

CEo-CEa

INPUT

CHIP ENABLE: Activates each device's control logic, input buffers, decoders,
and sense amplifiers. Each line is unique to one set of 2 devices (word). CEx is
active low; CEx high deselects the memo!ypevice and reduces power
consumption to standby levels. Only one CEx may be active at a time.

OE

INPUT

DOO-D015

..

WEH;WEL

INPUT

OUTPUT ENABLE: Gates the devices outputs through the data buffers durin!;! a
read cycle. OE is active low.
WRITE ENABLE controls writes to the control register and the·array.
(WEH = High Byte; WEL = Low Byte)
Write enable is active low. Addresse~are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
NOTE: WithVpp ~ 6.5V, memory contents cannot be altered.

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command. register, erasing
the entire array, or programming bytes in the array (12V ± 5%) ..

Vee

DEVICE POWER SUPPLY: (5V ± 10%).

Vss

GROUND.

NC

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.
Pin

Function

17

CE7

18

CEe

19

CE5

20

CE4

30

A22

31

A21

32

A20

33

A19

34

A18

,
RES

RESERVED for future product enhancements.

PD1-PD7

PRESENCE DETECT: Denotes word depth (512K) and access time of device.
See Table 3, "Presence Detect "PD" Pins" on Page 5.

4-166

ISM002FLKA

Table 3. Presence Detect "PD" Pins
MODULE CAPACITY IDENTIFICATION
MODULE CAPACITY
WORD DEPTH

PD6

NO MODULE
256K/32M
\

PD2

PD1

0

0

0

0

0

S

512K/64M

0

S

0

1M/128M

0

S

S

2M/256M

S

0

0

4M/512M

S

0

S

8M/1G

S

S

0

16M/2G

S

S

S

MODULE SPEED IDENTIFICATION
MAXIMUM
ACCESS
TIME

PD7

PD5

PD4

>300ns

S

S

S

S

300ns

S

S

S

0

250ns

S

S

0

200ns

S

S

0

S
.. 0

185ns

S

0

S

S

150ns

S

0

S

0

135ns

S

0

0

S

120ns

S

0

0

0

100ns

0

S

S

S

85ns

0

S

S

0

PD3

70ns

0

S

0

S

·60ns

0

S

0

0

50ns

0

0

S

S

40ns

0

0

S

0

30ns

0

0

0

S

ND

0

0

0

0

o

= OPEN CIRCUIT- ON MODULE
S = SHORT CIRCUIT TO GROUND ON MODULE
NO = NOT DEFINED

4·167

infel"

iSM002FLKA

SINGLE IN-LINE MEMORY MODULE
BOARD
PC substrate: Glass Epoxy [0.05" +0,004/-0.003
nominai thickness]. The iSM002FLKA low-profile
SIMM mounts easily between expansion slots. See
Appendix A for a list of 80-pin socket suppliers.

APPLICATIONS
With high density, nonvolatility,and extended cycling
capability, Intel's iSM002FLKA flash SIMMs offer an
innovative alternative to disk and battery-backed
static RAM.
Primary applications and operating systems can be
stored in flash, eliminating the slow disk-to-DRAM
download process. Performance is dramatically enhanced and power consumption is reduced-a consideration particularly important in portable equipment. Flexibility is increased with Flash's electrical
chip erasure allowing ir;l-system updates to operating
systems and application code.
In diskless workstations and terminals, network trafe
fic is reduced to a minimum and systems are instanton. Reliability exceeds that of electro-mechanical
media. Often in these environments, power glitches
force extended re-boot periods for all networked terminals. This mishap is no longer an issue if boot
code, operating systems, communication protocols
and primary applications are flash-resident in each
terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, Flash SIMMs provide a solid state alternative in a minimal form factor. Flash memory provides
higher performance, lower power consumption and
instant-on capability.' Additionally, flash is more rugged and reliable in harsh environments where extreme temperatures and shock can cause diskbased systems to fail.
For systems currently using a high-density static
RAM/battery configuration for code updates and
data accumulation, flash memory's inherent nonvolatility eliminates the need for battery backup. The
possibility of battery failure is removed. This consideration is important for portable equipment and med~
ical instruments, both requiring continuous performance. In addition, flash memory offers a four-to-one
cost advantage over SRAM.
Flash memory~s electrical chip erasure, byte reprogrammability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank-slate" in
which to log or record data. Data can be periodically
off-loaded for analysis-erasing the slate and repeating the cycle.

Flash SIMMs add additional flexibility to designers
by offering end-users incremental expansion memory. As code requirements grow or as memory prices
drop, your customers have the option of addino
more memory.
.. . .
~

PRINCIPALS OF OPERATION
The iSM002FLKA operates as eight N28F020 flash
memories connected as shown in the Functional
Block Diagram on Page 2.
The iSM002FLKA, organized as 1024K x 16, can
also be configured for 8e and 32-bit systems. For
32-bit systems, add a second SIMM to your design
as currently done with DRAM. For byte-wide operation, buffer the SIMMs DOo-DO? and 008-0015
lines with an octal transceiver; then, tie the buffered
outputs together to form the 8-bit bus. Decode the
transceiver's enable input with an address line.
The iSM002FLKA features hardware presence detect pins to facilitate memory design. The presence
detect pins (PD1-PD7) indicate module word depth
and maximum access speed (see Table 3 on the
previous page). The. pins allow memory-specific
wait-state generation upon system initialization. To
use the presence capability, pull-up the PD1-PD7
lines through a pull-up resistor. Read the lines
through a port and select the appropriate memory
depth and speed from a PO data table.
In the absence of high voltage on the modules Vpp
pins, the iSM002FLKA is a read-only memory array.
Manipulation of the module's control pins yields
standard read, standby and output disable functions.
Read, standby and output disable operations are
. also available when high voltage is applied to the
Vpp pins. In addition, high voltage on the Vpp pins
enables erasure and programming of the module's
devices. All functions associated with altering the
memory contents of one or more devices-erase
erase verify, program and program verify-are ac~
cessed via each flash device's command register.
Commands ar~ written to a device's command register· ~sing standard microprocessor write timings.
Register contents serve as input to the devices internal' state-machine which controls the erase and
programming circuitry. Write cycles to a device also
internally latch addresses and data needed .for programming or erase operations. With the appropriate
command written to a device's register, standard microprocessor read timings output array data, access
the inteligent identifier codes, or output data for
erase and program verification.

4-168

intel .

ISM002FLKA

Table 4. Bus Operations
Pins

Vpp(1)

CE

()E

WE

DQO-DQ15

Read

VPPL

VIL

VIL

VIH

Data Out

Output Disable

VPPL

VIL

VIH

VIH

Tri-State

Standby

VPPL

VIH

X

X

Tri-State

Read

VPPH

VIL

VIL

VIH

DataOut(3)

Output Disable

VPPH

VIL

VIH

VIH

Tri-State

Standby(4)

VPPH

VIH

X

X

Tri-State

Write

VPPH

VIL

VIH

VIL

Data In(5)

Operation
READ-ONLY

READ/WRITE

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes are accessed via a command register write sequence. Refer to Table 5. All other ad·
dresses are low.
'
3. Read operations with Vpp = VPPH may access array data or the intellgent IdentHier™ codes.
4. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
5. Refer to Table 5 for valid Data·ln during a write operation.
6. X can be VIL or VIH.

~ Integrated Stop Timer
Successive command write cycles define the duration of program and erase operations; specifically, .
the, program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state ,and remains inactive until receiving the appropriate verify or reset command. '

Write Protection
A device's command register is only active when
Vpp is at high voltage. Depending upon the application, the system designer, may choose to make the
Vpp power supply switchable-available only when
memory updates are desired. When Vpp= VPPL,
the contents of the register default to the read command, making the iSM002FLKA a read-only memory. In this mode, the memory contents cannot be
altered.
'
Or, the system deSigner may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this instance, ,all operations are performed in conjunction with the command register.
The iSM002FLKA is designed to accommodate either deSign practice, and to encourage optimization
of flash's processor-memory interface.
'
The following section first discusses byte-wide organization, building a basic understanding of byte-wide "

bus operations, command definitions, and programming and erasure algorithms. The section concludes
with performance enhancements for both 16- and
32-bit systems.

BUS OPERATIONS
Read
Each of the iSM002FLKA's flash memory devices
has two control functions, both of which must be
logically active, to obtain data. Chip-Enable COEx> is
the power control and should, be used for device
selection. Four chip enables (CEo-CE3) control the
array's eight devices. Each line is unique to one set
of two devices (word). Only one CEx may be active
ata time.
'
Output-Enable (OE) is the output control and should'
be used to gate data from a device to the output pins
on the module, independent of device selection.
One OE line serves the iSM002FLKA's flash d.evices. Figure 7 illustrates read timing waveforms.
When the Vpp lines are high (VPPH), a read operation can be used to access array data, to output a
device's inteligent identifier™ code, and to access
device's data for program/erase verification. When
VPP is low (Vppu, a read operation can only access
array data.
.

a

Output Disable
With the iSMoo2Fi.KA'~ Output-Enable pin at a logic-high level (VIH), outputs from all devices are dis~
abled. They are placed in ,a high-impedance state.

4-169

intel..

ISM002FLKA

A device's command register itself does not occupy
an addressable memory location. The register is a
latch used to store the command, along with address and data information needed to execute the
command.

STANDBY
With Chip-Enable at a logic-high level, the standby
operation disables most of the deselected devices
circuitry and substantially reduces device powai
consumption. The outputs of the deselected devices
are place in a high-impedance state, independent of
the Output-Enable signal. If a word is deselected
during erase, programming, or program/erasure verification, the device draws active current until the operation is terminated.

TwO write enable lines are provided, WEH and
WEL> allowing selective write control of upper
and lower bytes.

Intelligent Identifier Operation .
The intelligent identifier operation outputs the selected devices' manufacturer code (89H) , and device
, code (SOH). The manufacturer code and device
code are read via the devices' command register.
Following a write of 90H to a device's command reg"
ister, a read from address location OOOOH outputs
the manufacture code (89H). A read from address
0001 H outputs the device code (SOH).

A device's command register is written by selecting
the device (Chip-Enable low), then bringing WriteEnable (WEH or WEu to a logic-low level (V,U. If
both WE lines are a logic low, both upper and lower
bytes are written. Addresses are latched on the failing edge of the Write-Enable Signal, while data is
latched on the rising edge of the Write-Enable pulse.
Standard microprocessor write timing are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.
.

COMMAND DEFINITIONS

Write
Erasure and programming is accomplished via each
device's command register, when high vpltage is applied to the Vpp pins. The contents of each device's
register serve as input to its internal state-machine.
The state machine outputs dictate the function of
each device.

When low voltage is applied to the module's Vpp
pins, the contents of all devices' command registers
. default to OOH, enabling read-only operations.
Placing high voltage on the module's Vpp pins allows read/write operation on selected devices. Operations are selected by writing specific data patterns to the device(s) command register. Table 5 defines these register commands.

Table 5. Command Definitions
Command
Read Memory
Read inteligent identifierTM Codes(4)
Set-up Erase/Erase(5)
~rase Verify(5)
~et-up Program/Program(6)
Program Verify(6)
Reset(7)

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1 Address(2 Data(3

1
3
2
2
2
2
2

Write
Write
Write
Write
Write
Write
Write

X
X
X
EA

X
X
X

OOH
90H
20H
AOH
40H
COH
FFH

Read
Write
Read
Write
Read
Write

(4)

X
X
PA

NOTES:
1. Bus operations are defined in Table 4.
2. IA = Identifier address: OOH 'for manufacturer code; 01 H for device code.
EA = Address of memory location to ,be read during erase verify:
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. 10 =; Data read from location IA during device identification (Mfr = 89H, Device BDH).
EVD = Data read from location EA during erase verify.
PO = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the 'Read intelligent 10 command, two read operations access manufacturer and device codes.
5; Figure 4 illustrates the Quick-Erase™ Algorithm.
6. Figure 3 illustrates the Quick-Pulse Programmlng™ Algorithm.
7. The second bus cycle must be followed by the desired 90mmand register write.
4~170

X
X

(4)
20H
EVO
PO
PVO
FFH

intel·

iSM002FLKA

with the rising edge of the next Write-Enable pulse
(i.e., Erase-Verify Command) .

Read Command
. While Vpp is high, for erasure and programming, the
selected devices memory contents can be accessed
via the read command. The read operation is initiated by writing OOH into the command register of each
device. Microprocessor read cycles retrieve array
data. The selected devices remain enabled for reads
until their command register contents are altered.
The default contents of each device's command
register upon Vpp power-up is OOH. This default value ensures that no' spurious alteration to the
iSM002FLKA's memory contents occurs during the
Vpp power transition. Where the Vpp supply is hardwired to the iSM002FLKA's Vpp pins, all eight devices power-up and remain enabled for reads until their
.command-register contents are changed. Refer to
the AC Read Characteristics and Waveforms for
speCific timing parameters.

Intelligent Identifier Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system.
.
Each flash memory device contains an intelligent
Identifier operation. The operation is initiated by writing 90H into the command register. Following the
command write, a read cycle from address OOOOH
retrieves the manufacturer code of 89H. A read cycle from address 0001 H returns the device code of
BDH. To terminate the operation, it is necessary to
write another valid command into the register.
The intelligent Identifier and the Presence Detect
pins give you complementary information. While the
PD .' pins denote speed and depth, the intelligent
Identifier operation giveS you manufacture and de~
vice data.
.

Set-Up Erase/Erase Comm..ands
Set-up Erase is a command-only operation that
stages a selected device for electrical erasure of all
bytes in its array. The set-up ~rase operation is per'formed by writing 20H to the command register.
,

.

This two-step sequence of set-up followed by execu, tion ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pins. In the
absence of this high voltage, memory contents are
protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.
.

Erase-Verify Command
The erase command erases all bytes of the selected
device(s) in parallel. After each erase operation, all
bytes must be verified. The erase verify operation is
initiated by writing AOH into the command register of
the device. The address for the byte to be verified
must be supplied as it is latched on the falling edge
of a Write-Enable pulse. The register write terminates the erase operation with the rising edge of its
Write-Enable pulse.
.
. Each 28F020 applies an Internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte of the device until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes of
the device have been verified, the erase step is
complete. The device can be programmed. At this
point, the verify operation is terminated by writing a
valid command (e.g., Program Set-up) to the command register of the device. Figure 4, the QuickErase™ algOrithm, illustrates how commands arid
bus· operations are combined to perform electrical
erasure of each 28F020. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

Set-Up Program/Program Commands

To commence c.hip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge' of a
Write-Enable pulse (WEH or WEd' and terminates

Set-up program is a command-only operation that
stages a device for byte programming. Writing 40H
into the command register of the device performs
the set-up operation.

4-171

intel .

ISM002FLKA

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write~Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
I
parameters.

Program-Verify Command
Each 28F020 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at
random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register of the device. The
register write terminates the programming operation
with the rising edge of its Write-Enable pulse. The
program~verify operation stages the device for. verification of the byte last programmed. No new address
information is latched.
Each 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 3,
the QuiCk-Pulse Programming algorithm (8-bit Systems), illustrates how commands are Combined with
bus operations to perform byte programming. Refer
to AC Programming Characteristics and Waveforms·
for specific timing parameters.

Reset Command
. A reset command is provided as a means to safely
abort the erase- or p.rogram-command sequences to
a device. Following either set-up command (erase or
program) with two consecutive writes of FFH will
safely abort the operation. Memory contents will not
be altered. A valid command must then be written to
place the device in the desired state.

EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some
suppliers have implemented redundancy schemes,
reducing cycling failures to insignificant levels~ However, redundancy requires that cell size be doubled-an expensive solution.
Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in CYCling reliability. come without in~
creasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxid~ defects in the region. Finally, the peak
electric field during erasure is approximately
2 MVlcm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure--lncreasing time to wearout by a factor of
100,000,000.
Each of the iSM002FLKA's eight 28F020s is specified for a minimum of 10,000 program/erase cycles.
Each device is programmed and erased using Intel's
Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a series of
operations (pulses), along with byte verification, to
completely and reliably erase and program the device.
For further information, see Reliability Report RR-60
(ETOX II Reliability Data Summary).

QUICK-PULSE PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10,..,s duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence· of programming and byte verification is
performed with Vpp at high voltage. Figure· 3 illustrates the· Quick-Pulse Programming algorithm for
8-bit systems.

4-172

intel·

ISM002FLKA

QUICK-ERASE ALGORITHM
Intel's Quick-Erase' algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs' a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
iSM002FLKA is erased when shipped from the factory. Reading FFH data from each device would immediately be folloYfed by device programming.

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 4 illustrates the Quick-Erase algorithm
for a-bit systems.

For devices being erased and reprogrammed, uni_form and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse 'Programming algorithm, in approximately two seconds.

4-173

iSM002FLKA

Bua
Operation Command

Standby

Commenta

Wait for Vpp Ramp to VPPH(1)

Initialize Pulse-Count

Write

Set·up
Program

Data = 40H

Write

Program

Valid Address/Data

Standby
Write

Duration of Program
Operation (twHWH1)
Program(3) Data = COH; Stops Program
Verify
Operation(4)
,

Standby

twHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

,
"

Write

Standby

Read

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VpPL(2)

290465-3

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED
to enaure proper and reliable operation of the device.
2. See DC Characteristics for value of VPPH and VPPL.

3. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.
4. Refer to principles of operation

Figure 3. QUick-Pulse Programming Algorithm (a-Bit Systems)

4~174

int'et

iSM002FLKA

Bus
Command
Operation

Comments

Entire Memory Must
Before Erasure

= OOH

Use Quick-Pulse
Programming™ Algorithm
(Figure4)
Wait for Vpp Ramp to VPPH(2}

$tandby

Initialize Addresses and.
Pulse-Count
Write

Set-up.
Erase

Data

= 20H

Write

Erase

Data

= 20H

Duration of Erase Operation
(tWHWHV

Standby

Standby

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(4}
twHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Write

Erase(3)
Verify

Read

Standby

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VPPL(2}

290465-4

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the davice.
2. See DC Characteristics for' value of VPPH and VPPL.

3. Erase Verify is performed only after Chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
4. Refer to principles of operation.

Figure 4. Quick-Erase Algorithm (a-Bit Systems)

4-175

int:eL

iSM002FLKA

HIGH PERFORMANCE PARALLEL
DEVICE ERASURE

HIGH PERFORMANCE PARALLEL
DEVICE PROGRAMMING

Total erase time for the iSM002FLKA is reduced by
impiementing a paraiiei erase aigorithm (Note 1).
You save time by erasing all devices at the same
time." However, since flash memories may erase at
different rates, you must verify each device separately. This can be done in a word-wise fashion with
the command register Reset command and a special masking algorithm.

Software for word- or double-word programming can
be written in two different manners. The first method
offers simplicity of design and minimizes software
overhead by using a byte programming routine on
each device independently (using host CPU's byte
addressing mode). The second method offers higher
performance by programming the word or doubleword data in parallel. This method manipulates the
command register instructions for independent byte
control. See Figure 6 for conceptual 2-device parallel programming flow chart and Appendix C for the
detailed version. Here you can use the host CPU's
appropriate word- or double-word addressing modes
(Le., incrementing by 2- or 4-byte addresses, respectively).

Take for example the case of two-device (parallel)
erasure. The CPU first writes the data word erase
command 2020h twice in succession. This starts
erasure. After 10 ms, the CPU writes the data word
verify command AOAOh to stop erasure and setup
erase verification. If both bytes are erased at the
given address, then the CPU increments the address (by 2) and then writes the verify command
AOAOh again. If neither byte is erased, then the CPU
issues the erase sequence again without incrementing the address.

NOTE:
Word or double-word programming assumes 2 or 4
a-bit flash memory devices.

Parallel Programming Algorithm Summary:
Suppose at the given address only the low byte verifies FFh data? Could the whole chip be erased? The
answer is yes. Rather than check the rest of the low
byte addresses independently of the high byte, simply use the reset command to mask' the low byte
from erasure and erase verification on the next
erase loop. In this example the erase command
would be 20FFh and the verify command would be
AOFFh. Once the high byte verifies at that address,
the CPU modifies the command back to the default
2020h and AOAOh, increments the address by 2, and
writes the verify command to the next address.
See Figure" 5 for a conceptual view of the, parallel
erase flow chart and Appendix B for the detailed version. These flow charts are for 16-bit systems and
can be expanded for 32-bit designs.
.
NOTE:
1. Parallel Erasure and Programming require appropriate choice of Vpp supply to support the increased power consumption.

4-176

• Decreases programming time by programming 2
flash memories (16 bits) in parallel. The algorithm
can be expanded for 32-bit systems.
• Eliminates tracking of high/low byte addresses
and respective number of program pulses by directing the CPU to write data-words (16-bit) to the
command register.
• Maintains word write and read operations. Should
a byte on one device program prior to a byte on
the other, the CPU continues to write word-commands to both devices. However, it deselects the
verified byte with software commands. An alternative is to independently program high and low
bytes using hardware select capability (byte-addressing mode of host CPU).

int'et

ISM002FLKA

RAISE Vpp
PROGRAM ALL DEVICES TO OOh
RESET ALL VARIABLES
ISSUE ERASE COMMAND
TIME OUT
VERIFY COMMAND
[

I

BOTH ~VICES ERASED

~

N LAST ADDRESS

MASK'
HI-OR LO-BYTE
COMMANDS
LAST PULSE

Iy

Iy

DONE

..!!.-

ERROR

290465-5

'You mask the device by substituting a Reset command for the Erase and Verify commands. That way, the erased byte
idles through the next erase loop.

Figure 5. High Performance Parallel Erasure (Conceptual Overview)

-

RAISE Vpp
GET ADDRESS/DATA WORD
RESET COMMAND AND
COUNTER VARIABLES
PROGRAM DATA - - - - - - - - - - - - - - - . . . ,
WORD

~

TIME OUT 10 J.I.'

~

STOP PROGRAMMING WITH
PROGRAM VERIFY COMMAND

~

DATA WORD PROGRAMMED?

d

Y

N
-

MASK HI OR LO BYTE
INCREMENT PULSE COUNTER
N
LAST PULSE? - - - - - '

']

MORE DATA?

~N

WRITE READ COMMAND
LOWER Vpp
PROGRAMMING COMPLETE

WRITE READ COMMAND
LOWER Vpp
PROGRAM ERROR

290465-6

'You mask the device by substituting a Reset command for the Program and Verify commands. That way, the programmed bytes do not get further programmed on subsequent pulses.

Figure 6. Parallel Programming Flow Chart (Conceptual Overview)

4-177

intel .

iSM002FLKA

DESIGN CONSIDERATIONS

Power Up/Down Protection.
The iSM002FLKA is designed to offer proteCtion
against accidental erasure or programming during
power transitions. Upon power-up, each 28F020 is
indifferent as to which power supply, Vpp or Vee,
powers up first. Power supply sequencing is not required. Internal circuitry in each 28F020 ensures that
the command register is reset to the read mode on
powerup~
,

Two-Line Output Control
Two-line control provides for:
a. the lowest possible memory power dissipation
,and,
"
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read Signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.

Power Supply Decoupling

A system designer must guard against active writ~s
for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
'write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences. ,

Power Dissipation'

Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested. in three supply current (IcC> issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnit,..des of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iSM002FLKA features a 0.1 ,...F ceramic capacitor
connected between Vee and Vss; and between Vpp ,
and Vss.
,

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because each .
28F020 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating each 28F020.
Table 4. 28F020 TyplcatUpdate Power
Dlsslpatlon(4)
Operation

Also, a 4.7 ,...F tantalum capacitor decouples the array's power supply between Vee and Vss 'and between Vpp and Vss. The bulk capacitors will overcome voltage slumps caused by printed-circuitboard trace inductance, and will supply charge to
the smaller capacitors as needed.

Power
Dissipation
(WaH-8econds)

Array Program/Program Verify(l)

0.34

Array Erase/Erase Verify(2)

0.37

One Complete Cycle(3)

1.05

NOTES:

Vpp Trace on Printed, Cir,cuit Boards
Programming flash memories, while they reside in
the target system, requires that the printed.circuit
board designer pay attention to the VPP power supply trace. The two Vpp pins supply current for programming. Use similar trace widths and layout considerations given the Vee power bus. Adequate Vpp
supply traces and decoupling will decrease Vpp voltage spikes and overshoots. Be sure to connect both .
module Vpp inputs to your 12V supply.

1. Formula to calculate typical Program/Program Verify
Power = [Vpp ,x "" Bytes x typical "" Prog Pulses
(tWHWHl x IpP2 typical + twHGL x IpP4 typical)) + [Vee
,x "" Bytes x typical"" Prog Pulses (twHWHl x 1002 typ,ical + tWHGL X ICC4 typical]. .
'
2•. Formula to calculate typical Erase/Erase Verify Power
= [Vpp (VPP3 typical X tERASE typical + IpP5 typical X
twHGL X "" Bytes)) + [Vcc (lCC3 typical x tERASE typical
+ lee5 typical x twHGL X "" Bytes»).
.
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals are not guaranteed but based on a limited
number of samples taken from production lots.

4-178

intel .

iSM002FLKA

ABSOLUTE MAXIMUM RATINGS·

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read ........... ~ ...... 0·Cto +70·C(1)
During Erase/ Program ........... O·C to + 70·C
Temperature Under Bias ......... -1 O·C to + SO·C
Storage Temperature .......... -50·C to + 100·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Vpp Supply Voltagl3 with
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Output Short Circuit Current. ............ 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is - 0.5V. During transitions, inputs may undershoot to· - 2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than orie output shorted at a time.
OPERATING CONDITIONS

Symbol

Limits

Parameter

TA

Operating Temperature

Vee

Vee Supply Voltage

Unit

Comments

70

·C

For Read-Only and
Read/Write Operations

5.50

V

Min

Max

0
4.50

4-179

ISM002FLKA

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
. Symbol

Parameter

Notes

III

Input Leakage Current

3

ILO

Output Leakage Current

3

Iccs

Vee Standby Current

1,3

ICC1

Vcc Active Read Current

2,3

lee2

Vee Programming Current

2,3

lee3

Vee Erase Current

2,3

ICC4

Vee Program Verify Current

2,3

lecs

Vee Erase Verify Current

2,3

Limits

M!n

.....

Tun

Max

Unit

Test Conditions

±8.0

Jl-A

Vcc = Vcc Max
VIN = Vccor Vss

±40.0

Jl-A

Vcc = VccMax
VOUT = VccorVss

8.0

mA

Vcc = Vcc Max
CE = VIH

66

mA

Vcc = Vcc Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

8.0

26

mA

Programming in Progress

16.0

36

mA

Erasure in Progress

16.0

36·

mA

VPP = VpPH
Program Verify in Progress

16.0

36

mA

VPP = VPPH
Erase Verify in Progress

I

26

Ipps

VPP Leakage Current

3

±80

Jl-A

VPP ~ Vce

IpP1

VPP Read Current
or Standby Current

3

0.7

1.6

mA

VPP > Vee

±80

p.A

VPP ~ Vee

IpP2

VPP Programming Current

2,3

16.5

61.2

mA

Vpp = VPPH
Programming in Progress

IpP3

VPP Erase Current

2,3

20.5

61.2

mA

VPP = VPPH
Erasure in Progress

IpP4

VppProgram Verify Current

2,3

4.5

11.2

mA

VPP = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

2,3

4.5

11.2

mA

VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

2.4

VPPL

VPP during Read·Only
Operations

0.00

VPPH

VPP during Read/Write
Operations

11.40

VLKO

Vce Erase/Write
Lock Voltage

Vee

+ 0.5

0.45

2.5

V
V

IOL = 5.8mA
Vcc = Vcc Min

V

IOH = -2.5 mA
Vec = Vcc Min

6.5

V

NOTE: Erase/Program are
Inhibited when VPP = VPPL

12.60

V
V

NOTES:
1. Vee standby current for 8 devices.
2. Calculations assume only the 2 devices of the 16·bit word are enabled. The remaining 6 devices are in standby.
Current will be higher if interleaving Is used.
3. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25'C. These currents
are valid for all product versions (packages and speeds).

4·180

inteL

iSM002FLKA

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Notes

Limits
Min

Typ

Max

Unit

Test Conditions

III

Input Leakage Current

3

±8.0

/LA Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

3

±40.0

Ices

Vee Standby Current

1,3

0.4

0.8

/LA Vee = Vee Max
VOUT = Vee or Vss
rnA Ys..e = Vee Max
CE = Vee ±0.2V

lee1

Vee Active Read Current

2,3

20.3

60.6

rnA Vee

lee2

Vee Programming Current

2,3

2.3

20.6

rnA Programming in Progress

lee3

Vee Erase Current

2,3

10.3

30.6

rnA Erasure in Progress

lee4

Vee Program Verify Current

2,3

10.3

30.6

rnA Vpp = VpPH
Program Verify in Progress

lee5

Vee Erase Verify Current

2,3

10.3

30.6

rnA Vpp = VPPH
Erase Verify in Progress

IpPS

Vpp Leakage Current

±80

IpP1

Vpp Read Current
or Standby Current

/LA Vpp"; Vee
rnA Vpp> Vee

3

0.7

1.6
±80

= Vee Max, CE = VIL
f= 6 MHz,lOUT = 0 rnA

/LA Vpp"; Vee
rnA Vpp = VPPH
Programming in Progress

IpP2

Vpp Programming Current

2,3

16.5

61.2

IpP3

Vpp Erase Current

2,3

20.5

61.2

rnA Vpp = VpPH
Erasure in Progress

IpP4

Vpp Program Verify Current

2,3

4.5

11.2

rnA Vpp = VpPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

2,3

4.5

11.2

rnA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

0.8
Vee

+ 0.5

0.45

V
V
V

VOH1
Output High Voltage

0.85 Vee

V

IOH = - 2.5 rnA,
Vee = Vee Min
IOH = -100/LA,
Vee = Vee Min

Vee - 0.4

VOH2

IOL = 5.8 rnA
Vee = Vee Min

VPPL

Vpp during Read-Only
Operations

0.00

6.5

V

VPPH

Vpp during Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write
Lock Voltage

NOTE: Erase/Program are

Inhibited when Vpp

= VPPL
)

2.5

V

NOTES:

1. Vcc standby current for 8 devices.
2. Calculations assume only the 2 devices of the 16-bit word are enabled. The remaining 6 devices are in standby.
Current will be higher if interleaving is used.
3. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25'e. These currents
are valid for all product versions (packages and speeds).
4-181

intel .

ISM002FLKA

CAPACITANCE(1) TA
Symbol

= 25°C, f = 1.0 MHz

Limits

Parameter

Notes

CIN1

Address Capacitance

2

60

pF

CIN2

Control Capacitance

2

65

pF

COUT

Output Capacitance.

2

55

pF

Max

Min

Unit

Conditions

= OV
VIN = OV
VOUT = OV
VIN

NOTES:
1. Trace capacitance calculated, not measured.
2; Address and control capacitance of a typical device is 6 pF.
3. Output capacitance of a typical device is 12 pF.

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................ 0.45Vand 2.4V
Input Timing Reference Level ...•..• 0.8V and 2.0V
Output Timing Reference Level .•.•.. 0.8V and 2.0V

AC CHARACTERISTIC5-Read-Only Operations(2)
Versions
Symbol
'.

tAVAV/tRC
tELQV/tCE
, tAVQV/tACC

,

Notes

Characteristic
. Read Cycle Time

3

Address Access
.Time

Unit
ns

150

ns

150

ns

55

ns

I

Output Enable
Access Time

tELQX/tLZ

Chip Enable to
Output in Low Z

3

tEI;IQZ

Chip Disable to
Output in High Z

3

tGLQX/tOLZ

Output Enable to
Output in Low Z

3

tGHQZ/tOF

Output Disable to
Output in High Z

4

Output Hold from
Address, CE,
orOEChange

3

tWHGL

Max

150

Chip Enable
Access Time

tGLQVf.tOE

• tOH

ISMOO2FLKA·150
Min

Write Recovery
Time before
Read

NOTES:
1. Whichever occurs first.
10 ns.
3. Not 100% tested: Characterization data available.
4. Guaranteed by design.
.

2: Rise/Fall Time s:

4-182

0

ns
55

0

ns
ns

35.

ns

0

ns

6

,""S

I

l
•

Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

ADDRESSES

OUTPUTS ENABLED

DATA VALID

STANDBY

Vee POWER-DOWN

ADDRESS STABLE

t AVAV (~)

l!

CD
C

;

CE (E)

-

:"

:..
0

---

:e

-...

!
!

(lD
(0)

ens:::

DE (G)

g

0

-...
:I
III

I.

1

'wHGL

N
"TI

aI

1

r

0

:D

~

II

~LOV ('oE)

I»

a.

I+-- nov

0

"!....

0'

'I

(tCE)

~LOX ('oLZ)--l

II

::J
III

""

WE (iii)

'oH

trLOX (tu)

HIGH Z

DATA (DO)

VALID OUTPUT

II - s.OV

Vee

ov

J.

HIGH Z

'~'
lr~--

1'........
'
t AVOV (tAee)

:

---- - - -

~

L
290465-7

ISM002FLKA

AC CHARACTERISTICS-Write/Erase/Prograrri Operatlons(1,2)
Versions

ISMOO2FLKA·150

Symbol
tAVAV/twc

Characteristic

Notee

Write Cycle Time

M!n

M:x

Unit

150

ns

iAVWL/tAS

Address Set-up Time

0

ns

tWLAX/tAH

Address Hold Time

60

ns

tOVWH/tOS

Data Set-up TIme

50

ns

tWHOX/tOH

Data Hold Time

10

ns

tWHGL

Write Recovery Time
b~fore Read

6

/Ls

IGHWL

Read Recovery
Time before Write

0

".S

tELWL/tcS

Chip Enable Set-up
TIme before Write

20

ns

tWHEH/tcH

Chip Enable
Hold Time

0

ns

IWLWH/tWP

Write Pulse Width

tWHWL/twPH

Write Pulse
Width High

IWHWH1

Duration of
Programniing
Operation

tWHWH2

Duration of Erase
Operation

tVPEL

Vpp Set-up Time to
Chip Enable Low

60

ns

20

ns

3

10

/Ls

3

9.5

ms

1.0

/Ls

2

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time:$; 10 ns.
.
3. The integrated stop timer terminates the program/erase operations, thereby eliminating the need for a maximum specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter

Notes

28F020·150
Min

Chip Erase Time

1,3,4

Chip Program Time

1,2,4

Erase/Program Cycles

1,5

10,000

Unit

Typ

Max

2

30

4

25

100,000

Sec
Sec
Cycles

NOTES:
1. Typicals are not guaranteed, but based on a limited number of samples from production lots. Data taken at 2S·C, 12.0V
Vpp.
.
.
2. Minimum byte programming time excluding system overhead is 16 ".S (10 ".S program + 6 J.lswriterecovery), while
maximum is 400 J.ls/byte (16 J.ls x 25 loops allowed by algorithm). Max chip programming time is specifiedlower.than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
. ..
..
5. Refer to RR-60 "ETOXTMII Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.

4"184

intel .

ISM002FLKA

99.9

V
/

99

/

95

90
C
u
m

/V

80

0

b
a
b

70

/

I/'

, ,
I' ,,
If ,,"
,

30
20

10

,

,/

,,
,
,

/

,,

,,

,
" ,,
,

60

40

Y

/
//'

,(,

,
,,
,
,

,(;/
./.,,/
,
/'

, ./

50

'

V

I

P

/

it

,

,

"
5

0.1

<4

5

6

7

8

9

10

20

30

40

Chip Program Time (Sec)
- - - 12V; 10ke; 23C
• - - - - -. 11.4v; 10ke: 70C
- - - - 12V; 100ke; 23C
290465-6

Figure 8. 28F020 Typical Programming Capability

4-185

intel~

iSM002FLKA

15

I I II ' I I I I I I II
14

II

13

V
V

12
C
h

P

11

P
0

10

9
r

a
m

9

T

I--- ~
./'

,

I

m

•

, 8

S
7

/

6

V'"

V
V

,/

lL

,

,I

,,
I

5

,•

o

10

,,
I

,
,

. .. ..."
20

30

40

50

....... ...
"
"

,

4

I

I

,',
60

I

I

80

V

II

I

V

70

L

I'

,
,,

-

I

V

/

L
V

','

90

100

110

,

120

130

Temp (C)
- - - lk Cycles
- ••••• - 10k Cycles
_ . _ - lOOk Cycles
290465-9

Flg~re

9. 28F020 Typical Program Time at 12V

4-186

ISM002FLKA

99.9

/,/" "1'

,. ,I

1/

99

'I

95
90

p

o
b

V
/ ,, "v

80
70

'I

/ /'11 "
j

60
50

II

I

",

,

,I

I

y

"

" II

J

a
b

"

' ,I

I

C
u

m

,/

V
,",,'/'
,
i)

J

30

I

/

20

I

I

,'/,

'I

•

ji •I

I ,:'.I

10
5

'V:'/
,,
1/
,.

:j

,

I

•

:~

0.1

1

2

3

4

5

6

7 B 910

20

30

40

50

Chip Era •• Time (Sec)
- - - - 12V; 10ke; 23C'
• - -- - - . 12V; 100ke; 23C
- - - - 11.4V; 10ke; OC
290465-10

NOTE:
Does not include Pre-Erase Program.

Figure 10_ 28F020 Typical Erase Capability

4-187

intel.

ISM002FLKA

5.2

5.0

1\

\,

4.8

\,

4.6

\

4.4

C
h

\

4.2

'\

I

P

4.0

E
r

a

•

3.8

i

S

3.4

,,

......

,

r\.

"'"

3.2

......

8

c

'\,

..,

3.6

T
m
e

~

3.0

'\.
,

,,

~

,...

...

~

2.8

'"

1',

"

1"- ...

... ......
... ...

~

2.6

.......

.... .
.
~ 1'0.. ....
.........

2.4

.......... ~

r"-..

.,

i'
.. ..
.... .
.. .... ....
...........
i'
~

--r--..

2.2

2.0

........

... ...

o

10

20

30

40

50

60

70

80

90

100

110

120

130

Temp (C)
- - - - lk.Cycles
••••••• 10k Cycles
_ •• lOOk Cycl ••

NOTE:
Does not include Pre-Erase Program.

Figure 11. 28F020 Typical Erase Time at 12.0V

4-188

290465-11

_.

Vee POWER-UP II:
STANDBY

SET-UP PROGRAM·
COMMAND

PROGRAM COMMAND
LATCH ADDRESS II: DAtA

PROGRAMMING

::::s

PROGRAM
VERlrY
COMMAND

PROGRAM
VERIfiCATION

STANDBY/
Vcc POWER-DOWN

Jg

•

A

c[
8

ADDRESSES

~I
c

CE (E)

iil

....
~

~

~I

...
3
...

Or (G)

CD

0

~

!

(XI

IO

0

~

Ci)

"'HOZ

'wHGL

i:

(lor)

III

0
0

iiE(ii)

N

"r-

'V

a

CD

~

iii

.....-

'"

"'LOV (IoE)

3>

3
3

il

DATA (DO)

0

'a

CD
~
III

I:!:

il

s.ov
vcc
OV
IyPEL
120V

I--

vPP
VpPL
290465-12

. Vee POWER-UP

.sTANDBY

a:

SET-UP ERASE

COMMAND

ERASE COMMAND

ERASING

ERASE
VERIFY
COMMAND

ERASE
VERIFICATION

STANDBY/
Vee POWER-DOVIN

--*
ADDRESSES

•

•

A

l
•

int:el.,

iSM002FLKA

ALTERNATIVE CE-CONTROLLED WRITES
28F020-150

Versions
Symbol

Characteristic

Notes

Min

Max

Unit

tAVAV

Write Cycle Time

tAVEL

Address Set-Up Time

0

ns

tELAX

Address Hold Time

80

ns

tDVEH

Data Set-Up Time

50

ns

tEHDX

Data Hold Time

10

ns

tEHGL

Write Recovery Time
before Read

6

,...s

tGHEL

Read Recovery Time
before Write

0

,...S

tWLEL

Write Enable Set-Up Time
before Chip Enable

0

ns

tEHWH

Write Enable Hold Time

0

ns

tELEH

Write Pulse Width

70

ns

tEHEL

Write Pulse Width High

20

ns

tVPEL

Vpp Set-Up Time to Chip

1.0

,...s

150

1

ns

Enable Low
NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4-191

_.
>z

"0

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STANDBY

DI ••

f

f

:!!

~

CiJ

~
CD
...

i

CD

ol>
~

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'

ar

A'

"

ADDRESSES

~

ViE (E)

~

~
'!2.

Or (G)

I-

<1>.

3 .g

FE

'tHEH

.01-

en

'tHGL

i:
o
o

(Vi)

N
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c8

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o

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PROGRAM
VERIFICATION

§.

~
0

CD

PROGRAM
VERIFY
COMMAND

PROGRAMMING

::!

III

<

PROGRAM COMMAND
LATCH ADDRESS'" DATA

l[

IG
C

...f'-

SET-UP PROGRAM
COMMAND

.~

-::I

-!I'

;

DATA (00)

HIGH Z

2.

:::J
IG

o

I

S,OV

Vee

is"

if

OV

\

12,OV
Vpp

""

VPPL

29C1465":14

infel~

ISM002FLKA

APPENDIX A
PARTIAL LIST(1) OF SO-PIN SIMM SOCKET COMPANIES

AMP INCORPORATED
HARRISBURG, PA 17105
.
(800) 522-6752
BURNDY CORPORATION
51 RICHARDS AVENUE
NORWALK, CT 06856
(203) 838-4444
MOLEX
2222 WELLINGTON COURT
LISLE, IL 60532
(708) 969-4550
NOTES:
1. This list is intended for example only, and in no way represents all companies that support SO-pin SIMM Sockets. Intel
Corporation assumes no-responsibility for circuitry other than circuitry embodies in an Intel product. No other circuit patent
licenses are implied.
2. Socket reliability data can be obtained from the above companies upon request.

4-193

ISM002FLKA

,APPENDIX B
PARALLEL ERASE FLOW CHART·
COMMENTS

Walt for Vpp, to stabilize.
Use Quick-Pulse Programming
algorithm.
INITIALIZE:
TEWIII 10m,
PLSCNT 0
ADRS
0
LCOI! = 2020H
V _COM = AOAOH

Initialize. Variables:
TEW = Erase duration (width)
PLSCNT = Pulse Counter
ADRS = Address
LCOM = Erase Command
V_COM = Verify Command

=

=

Erase Set-up Command
Start Erasing

Duration of Erase Operation.

Erase Verify Command'stops
erasure.
. ,
See next page for subroutine.

When both devices at ADRS are
erased, F-"ATA = FFFFH.
If not equal, increment the pulse
counter and check for last pulse.
Reset commands to default
(LCOM= 2020H,
V_COM = AOAOH)
before verifying next·ADRS.

Reset deVices for read operation.
TumoffVpp.

290465-15

4-194

infel·

ISM002FLKA

Device Erase Verify and Mask Subroutine
COMMENTS
This subroutine reads the data word
(F_DATA). It then masks the HI or
LO Byte of the Erase and Verify
commands from executing during
the next operation.

If both HI and LO bytes verify, then
return.

Mask" the HI Byte with OOH.

> __.... LCOM
''-COM

=(LCOM OR OOrrH)

If the LO Byte verifies erasure, then
mask" the erase and verify
commands with OOFFH(Reset).

= (LCOM OR OOrrH)

Mask" the LO Byte with OOH.

If the HI Byte verifies erasure, then
mask" the erase IlI1d verify
commands with FFOOH(Reset).

2s04s5-16

I

NOTE:

"Masking cali easily and efficiently be done in assembly languages. Simply load word registers with the incoming flash
data (F-DATA), the erase commands and the verify commands. Then manipulate the HI or LO register contents.

4·195

ISM002FLKA

APPENDIXC
PARALLEL PROGRAMMING ,FLOW CHART

COMMENTS

Wait for Vpp ramp to VPPH
PLSCNT = Pulse Counter
AORS = address to program
P...;,OAT = data word to prograni
Initialize Data Word Variables:
V_OAT = valid data
P_COM = Program Command
V_COM = Verify Command
Program Set,up Command
xx = Address don't care
Program
See next page for subroutine
Program Verify Command

F_OAT = flash memory data
Compare flash memory data
to valid data (word compare). If not
equal, increment pulse counter
and check for last pulse. If not last
pulse, compare High and Low
Byte.

Check buffer or 1/0 port for
more data to program.
Reset device for read operation.
Turn off Vpp.

290465-17

4-196

ISM002FLKA

Program Verify and Mask Subroutine
COMMENTS

MASK" the HI Byte with OOH.

P_COlA = (p _COlA OR OOFFH)
LOAT = (LOAT OR OQFFH)
V_COlA
(V_COlA OR OOFFH)

=

If the LO Byte Verifies, then
mask" the program and verify
command with OOFFH
(RESET).

Mask" the LO Byte with OOH.
P_COlA = (p _COlA OR FfO'OH)
LOAT
(LOAT OR FFOOH)
LeOlA = (LeOlA OR FFOOH)

=

If HI Byte Verifies, then mask·
the program and erase
command with FFOOH
(RESET):

290465-18

NOTE:
"Masking can easily and efficiently be done in assembly languages. Simply load word registers with tlie incoming flash
data (F_DATA), the erase commands and the verify commands. Then manipulate the. HI or LO register contents.

4-197

intel .

ISM002FLKA

Ordering Information
,
IIISIMI 0 1012IFILIKIAI-11I

L

r

s I01
I

L

REVISION

ACCESS SPEED (no)
1S0nl

' - ARCHITECTURE
K=. 16
~

FL = FLASH

' - DENSITY (MB)
002 = 2 MEGABYTE
'-- PACKAGE
SM = SO-PIN SIMM
'-INTEL

290465-19

Valid Combinations:
iSM002FLKA-150

ADDITIONAL INFORMATION

Order Number
294005
294008
293002
292046

ER-20, "ETOXTM 1/ Flash Memory Technology" .
ER-24, "The Intel 28F020 FlashMemory"
RR-60, "ETOXTM II Flash Memory Reliability Data Summary"
AP-316, "Using Flash Memory for In-System REiprogrammable
Nonvolatile Storage"
AP-325, "Guide to Flash Memory Reprogramming"
AP-343, "Flash Memory - A Mass Storage Medium"

292059
292079

\

4-198

APPLICATION
NOTE

AP-343

September 1992

Solutions for High Density
Applications
Using Intel Flash Memory

MARKUS A. LEVY
DALE ELBERT .
APPLICATIONS ENGINEERING
INTEL CORPORATION

Order Number: 292079-004
4-199

Solutions For High Density Applications
Using Intel Flash Memory
CONTENTS

CONTENTS

PAGE

INTRODUCTION . ...................... 4-201
ADVANCED PACKAGING .............
Plastic Leaded Chip Carrier (PLCC) .....
Thin Small Outline Package (TSOP) ....
Memory Cards .........................
Single In-Line Memory Module (SIMM) ..
HARDWARE DESIGN
IMPLEMENTATIONS ................
Design Example-A Paged-Mapped
Memory Board .......................
Optional Board Features ...............
Initializing Software for the Paged
Memory Board .......................
Linear Addressing ......................
I/O Addressing .........................
Capacitive Loading .....................

PAGE

SOFTWARE DESIGN
IMPLEMENTATIONS ................ 4-230
Data Recording ........................ 4-230
Interleaving ; ........................... 4-230
Write-Once-Read-Many (WORM)
Drives ...... ; ........................ 4-234
Disk Emulation ........ ; ................ 4-235
Creating a Bootable Drive ................ 4-238 .

4-201
4-201
4-202
4-204
4-206

4-209

WHY FLASH?-CHARACTERISTICS
OF INTEL FLASH MEMORY ........ 4-238

4-209

Power Consumption Comparison .
(Watts) .............................. 4-238 ,
Data Access Time ...................... 4-238

4-220
4-224

Reliability .................... ; ......... 4-239

4-226

Weight ................................. 4-240

4-227
4-229

SUMMARY ............................ 4-240
APPENDIX A ..•....................... 4-241

SCHEMATICS ......................... 4-247

4-200

AP·343

INTRODUCTION
Mass storage encompasses many different technologies.
Though commonalities exist, mass storage strives for
nonvolatility, low cost per bit, and high density. Disk
drives provide the best known example. However,
many environments now require higher performance
and reliability with lower power consumption, even at
the expense of capacity. Flash memory uniquely meets
these demands.
Flash memory can be used as a mass storage medium in
applications including factory automation, notebook
computers, high-end workstations, point of sale terminals, and data acquisition systems. Even desktop computers benefit from solid-state storage. The motivation
to incorporate flash memory in any of these applications becomes obvious to the system designer who understands flash memory's benefits and density projections.
In an effort to understand these benefits, this document
includes both conceptual and application oriented discussions. These discussions will b~ kept to a minimum
with the real focus being on specific design techniques
and considerations.

ADVANCED PACKAGING
Mass storage is synonymous with high density. Disk
drives have increased the bit density of the rotating media via material improvements and closer tolerances.
For semiconductors, density requires advanced packag-

ing as well as higher capacity silicon (improved photolithography). Intel's Flash Memory devices ate based on
the company's EPROM Tunnel Oxide (ETOXTM)
technology that enables the high degree of scaling required to achieve high density.
Intel offers the high density flash memories in several
package types. The standard packages are the Plastic
Dual In-line Package (PDIP), the Plastic Leaded Chip
Carrier (PLCC), and the Thin Small Outline Package
(TSOP). Advanced modular packaging in the form of
PCMCIA compatible memory cards and Single In-line
Memory Modules (SIMM) provide the total solution.

Which package is best for your application?

Plastic Leaded Chip Carrier (PLCC)
The engineer striving to reduce board space is already
using surface-mounted technology, such as PLCC. The
PLCC is seen frequently on PC add-in cards and motherboards. Compared to the DIP, PLCC uses as little as
35% the overall board space. Its small size, compared
to the DIP, is attributed to the terminal center-to-center spacing-50 mils versus 100 mils-as well as its
four-sided pinout. No drilling or lead-cutting is necessary as leads are soldered directly to pads on the circuit
board. The PLCC's 50-mil pad pitch is compatible with
most circuit board manufacturing equipment. Additionally, components can be mounted on both sides of
the board. However,the four-sided PLCC generally requires the use of a multi-layered board to layout conductor traces for maximum compaction.

4-201

AP-343

Thin Small Outline, Package (TSOP)
When overall space constraints are critical, the TSOP is
the best choice. This is best exemplified by IC memory
cards. Low height is the key attribute of the TSOP,
measuring 1.2 mm versus 3.5 mm for the PLCC. (Mechanical drawings in Appendix.) State-of-the-art center-to-center terminal spacing of 0.5 mm yields a smaller package and narrower conductor traces than the
PLCC or DIP. In comparison, the volume of the TSOP
is 172.8 mm 3 versus 656.3 mm 3 for the PLCC and
1872.3 mm3 for the DIP.

The TSOP is available in standard and reverse pin configurations (Figure 1). Pins are located on only' two
ends of the package. This approach simplifies trace layout while reducing the number of board layers because
traces can be routed out the non-leaded sides of the
devices. Very dense board layouts are accommodated
because. components can literally be laid out end-to-end
and .side-by-side. Figure 2 displays an optimal layout
best utilizing the TSOP's attributes. The close spacing
allows one bypass capacitor to be used for two devices
(provided they are not simultaneously selected). This
optimal component layout can be mirror-imaged
through the board to easily double the memory capacity.

~1

~

As

A10
~.

As
~3
~.
~7

~
~

%

WE
~

STANDARD PINOUT

Vpp

E28F020

O.
~
Vss

A16

02

~5

~

A12

DO

3

A

_

~
~

______________________________

~

________________

~

~

~
Al
~

~
A6
~ __
A.

All

As

REVERSE PINOUT
F28F020

A8
A13
A1•
A17
WE

Vce
Vpp

A16
A 15
A12

A7
A6

As

--~----------------------------------------------~~~
292079-17
Figure 1. 28F020 32-Lead TSOP-Standard a~d Reverse Pinouts

4-202

AP·343

07:0.:197:.:1

07:0.:187:3

~

0

0

---

0

~

====-

E28f020

Ir

F28F020

r;:=

---

IFr
~

,[

c...::::::

07:0.:197:.:1
1\

0

0
E28F020

~
~
~
~
~
~
~

======-

'---

07:0.:197:3

1

~

==-

-==-

0

F28F020

292079-18

Figure 2. TSOP Optimal Layout: Highest Density Configuration (Conceptual)

4·203

infel·

AP·343

Memory Cards
Many laptop and notebook computer manufacturers
are pursuing the IC memory card to, incOrporate a removable'mass storage medium. This is an ideal application for the Intel Flash Memory TSOP, due to the'
package's minimal height.

Solld·State Memory Alternatives '
ROM and SRAM are currently the dominant IC card
memory technologies. ROM has the advantage of being
inexpensive, but is not changeable. When newer software revisions (e.g. Lotus' 123, Wordstar**, etc.) are
available, the user must buy a new ROM card for each
upgrade. Intel Flash Memory's reprogrammability
minimizes the User's expense and the OEM's inventory
risk.
SRAM is reprQgriunmable but batteries 'are required to
maintain data, risking data loss. Like magnetic disks,
'flash memory is truly nonvolatile ,and thus has virtually

iDf'inite storage time with power off (10 years minimum,
100 years typical). Additionally, SRAM is expensive
and not a high density, solution. Intel Flash Memory
provides a denser, more cost effective and reliable solution.
,System level cost is about the same for Intel Flash
Memory and SRAM + batteryFlash memory requires 12V for programming and erasing. Ifa 12V supply is not available, SV can easily be
boosted. (See Application Note AP-316.) SRAM +
battery requires battery state detect circuitry.
Card level costdift'erences are substantial (Figure 3)SRAM must have a battery to retain data; It also requires a Vcc monitor and Write Lockout circuitry. Intel's Flash Memory only requires Write Lockout circuitry (switching Vpp to OV is an alternative write protect). This leads to increased area for memory components. More importantly, Intel's Flash Memory density
is 4 times ~t of static RAM, yielding for lower ,cost
per bit.
' ,

CARD LEVEL

Botto.,.
Hlghor,Denslllo.
Increased Area

SYSTEM LEVEL
Voltago
conve ...lon
5V-12V

FLASH

Botto.,.
Slolo
Dotlct
Circuli

,SRAM

for ...mory

Component.

Vee Monitor

Circuit.,
Wrlto
Lockout

Circuli

WrIt.
Lockout
Circuit

Denoilioo

FLASH

SRAM

Lower

292079-23

, Figure 3. Support Circuitry Cost Comparison

'LOTUS~ Is a registered trademark of LOTUS Development Corporation.
is a registered trademark of MICROPRO.

"WORDSTAR~

4-204

int:el..

Ap·343

Designing a PCMCIA/JEIDA Standard

Memory Card
Choosing among IC card design options depends on
card architecture (standardization), memory capacity,
data bus width, card intelligence, Vpp generation, and
reliability.

What are the advantages of a standardized memory card
pinout?
From the computer system's viewpoint, a standardized
pinout enables the use of multiple third-party memory
cards. This ensures competitive pricing and wide avllilability. From the memory card point of view, standardization allows use in a· variety of systems.
The Personal Computer Memory Card International
Association/Japan Electronic Industry Development
Association (pCMCIA/JEIDA) 68-pin format is the
emerging Ie memory card standard. Several proprie-

tary formats are also available from their respective
manufacturers, but these same manufacturers now offer
PCMCIA/JEIDA versions. The PCMCIA/JEIDA
standard specifies physical, electrical, information
structure, and data format characteristics of the card.
This standard accommodates either 8- or l6-bit data
bus widths.
.
The following 2 Mbyte memory card design provides a
byte-addressable interface using ·8-28F020s (2· Mbit,
256k x 8 devices) as shown in Figure 8. While TTL
equivalent interfacing is shown, most cards will use
gate arrays to reduce chip count. Address lines Al8
and A19 are decoded with a 2-to-4 decoder (74HC139)
to generate high and low byte chip select signals for
each of the 4 pairs of flash memory devices (one pair =
high and low ~. The PCMCIA/JEIDA format
specifies inputs CSL and CSH (along with the AO address line) which select the low and high byte, respectively.

HIGH

LOW

74HC244

ADDRESSES

(Octal Buff.r)

---.:r.....

AO ...

D~~~~+-----­

CD

292079-24

Figure 4. Decoding for PCMCIA/JEIDA ~tandard Bus Interface

4-205

Ap·343

According, to the PCMCIA/JEIDA standard, the
memory card is designed with the flexibility to have
both an 8-bit or a 16-bit interface, dependent upon the
machine it is plugged into. When the memory card is
plugged into an8-bit system, the high byte transceiver
is multiplexed to the,low byte of the system. In Figure
4, the highlighted transceiver (#2), maps the upper
byte to the lower byte of the data bus (i.e., DS-IS to
DO-7)' Signals are decoded according to the truth table
in the Appendix. (1,2, and 3 denote transceiver numbers of Figure 8.)
One can. double the memory capacity and select from
among 8 pairs of flash memory devices by using a 3 to 8
decoder with inputs A IS-20' Notice that additional
transceivers are not needed to support the additional
data fanout. (See section on capacitive loading.)

a binary 1 and Shorts as a binary 0 .. Before implementing the presence detect feature, define your system
criteria:

How many modules will be used?
Decide how much total memory your system is to con'tain. The limit is dictated by the space available, as well
as cost.

Flash memory SIMMs can easily accommodate different
memory capacities and speeds. Could your system handle mismatched SIMMs?
There are two basic design implementations for interpreting presence detect information. The first approach
requires that matching SIMMs are used. The PD pins
of all SIMMs are tied to one transceiver that is read as
'
an I/O port (FigureS).

Single In-Line Memory Module (SIMM)
The SIMM is optimal where minimized board space
and upgrade capability are required. Compared to using 8 discrete PLCCs plus capacitors (3019.4mm2), the
equivalent memory capacity SIMM (926.1mm2) consumes 70% less motherboard real estate.
The SIMM can be built as an 80-pin, 0.050 mil centerline lead spaced, insertable module designed with a
16-bit wide. data bus interface. The SIMM pin configuration allows convenient implementation: .
• No Address or Data Bus Multiplexing-RAS# and
CAS # are not needed;
• Reserved' Pins-For product expansion' and enhancements: Upgrade capability to 128 Mbytes;
• Presence Detect Eliminates· Jumpering-Simplifies
user installation.
The 80-pin definition of the flash memory SIMM includes 7 pins for Presence Detect (PD). (See Appendix). The PD pins are read to determine module memory capacity and speed of the devices. The PD pins are
either Open circuit or Shorted to ground. By attaching
a pull-up resistor to each pin, Open circuits will read ,as

Invalid reads occur if the user installs mismatched
SIMM configurations. Any PD pin shorted to ground
makes an open circuit pin appear as a binary zero (0).
Mixing module speeds is acceptable, but the PD pins
reflect the slower module.
The second approach, allowing any mixture of flash
SIMMs, requires more hardware and software for interpretation. The PD pins from each SIMM have separate
transceivers, resistors, and I/O ports (Figure 6). Flexibility is increased at tile expense of board real estate.

Assume your system accommodates several SIMMs but
complete population is not needed. Can the system handle empty sockets?
SIMM upgrade capability is not limited to increases in
memory density. A system may be designed with several SIMM sockets on the circuit board. To keep initial
end-customer costs down, the system ships with only
one SIMM installed. This provides the option of populating the empty sockets ata later time. The PD pins
are designed to eliminate jumper or software setups by
the end-user when: SIMM upgrades are made.

4-206

intel .

AP-343

+5

'-T

I~ch

PD lin. I. attached to a

.eparate 100k resistor tted to

,

+5V.

292079-19

Figure 5. All SIMMs Should Reflect the Same PO Configuration
+5

I/O PORT_I Enabl.

+5

+5

+5

I/O PORL2 Enable

I/O PORL3 Enable

I/O PORT_4 Enabl.

+5

100J

'

I~ch

PD lin. I. attached to a
.eparate lOOk ...Istor tlod to
+5V.

292079,-20

Figure 6. Multiple 1/0 Transceivers Are Needed if Mismatched SIMMs Are Used

Using the previous scenario, will it matter which socket is
used? In other words, what is the installation procedure?
With respect to the PD feature, it does not matter
which sockets are full. (However, most designers re, quest that sockets are filled in Sequential order to mini, mize hardware and softwear requirements.) To explain
this, look again at the bit-level interpretation of the PD
pins. An empty socket also appears as an open circuit.
Your software can determine a full (or empty) socket in
one of two ways:
Method One (Figure 5)-Reading the PD pins is insufficient. An empty socket will reflect the value of the
, . full socket. Your software will have to read the, chip

level device identifier hardwired in each flash memory device. (See Intel Flash Memory data sheets regarding inteligent identifiers.) Reading an invalid device
identifier from a SIMM address signifies an empty
socket. Software demonstrating the use of this method
to determine memory capacity is discussed further in
the section on "Verifying Paged Memory Board Functionality" .
Method Two (Figure 6)-Each SIMM's PD pins are
read separately. Reading
ones (the result of all Open
.circuits) signifies an empty socket. The chip level device
identifiers should still be read to establish the number
of flash memory devices on the SIMM.

4-207

all

AP-343

Presence Detect for WAIT-State
Interpretation
Using Method One or Method Two from above"the
device speed information is read from the pins. This
information can be interpreted by software to issue the
proper commllIld to the system's programmable
WAIT-state generator. By guaranteeing, the use of
matchirigSIMMs, the WAIT-state generator would not
have to be reprogrammed each time a different SIMM
is accessed.
A hardware driver alternative implements an 85C220
EPLD configured with an internal counter (Figure 7).
The rising edge of the clock, following Chip Enable
going active, latches the count value derived from the
PD speed pins (Figure 8).

Each subsequent rising edge of the clock input decrements the counter; A READY signal is output to the
CPU (or the system's READY logic circuitry) when
the count reaches zero (0). The READY signal remains
active until LOAD (Chip Enable, CE) goes inactive at
the. completion of the bus cycle.
The clock signal for the internal'EPLD count~r is derived directly from the CPU, therefore the count rate
and WAIT-states will be system dependent. An EPLD
Advanced Design File was generated to demonstrate
this application. (See Appendix A.) This is a straightforward approach until designing systems, such as power-saving laptops, that have changeable system clock
rates.

CPU CLOCK DETERMINES COUNTER RATE
ClK
EPlD
D85C22D-SO
INP 2
1/0.1 INP3
INP"
INPs INPs

""

-

CLOCK
READY

CPU

~

PD3
PO"
PD~

PI?
SIMMs

l'
ADDRESSES

DECODE
lOGIC

CHIP ENABLES

,292079-21

Figure 7. WAIT·State Generator Using an EPLDCoriflgured as a Counter

ClK

It-_ _ _p_Dn_= PD3.·PD4. PD5; PD7

lOAD

(CE)
PDn

0[3:0)

2'
2

0

Tl =7n.
T2 =5.5 no
T3=Ono

nREADY

292079-22

Figure 8. Timing for SIMM Presence Detect WAIT~State Generator
4-208

intel .

AP-343

ranging in size from 8 Kbytes to 64 Kbytes. (LIM-EMS
use four to twelve 16 Kbyte pages.)

HARDWARE DESIGN
IMPLEMENTATIONS
Paged, linear, and I/O are the three fundamental addressing methods that can be used for accessing an array of memory devices. Linear addressing offers the
fastest and most direct access to a memory array. It
consumes the largest portion of the system's memory
and is only practical in a 386™ microprocessor (or
other 32-bit processor) family system because of the
large memory space available above 1 Mbyte. The I/O
mapped memory array consumes the smallest amount
of the system address space but has the lowest performance. A page-mapped memory array, also called a sliding AT window, is a hybrid of the linear and I/O designs. The memory array is usually very large relative
to the system interface, consisting of pages typically

Design Example-A Paged-Mapped
Memory Board
A paged design employs addressing techniques similar
to the Lotus-Intel-Microsoft expanded memory specification (LIM-EMS). It allows access to one or more
sections (or pages) of the flash memory array at a time.
This minimal interface is particularly useful within the
DOS 1 Mbyte memory space. The DOS map (Figure 9)
shows 128 Kbytes of memory space available in the
Optional I/O Adapter ROM area. LIM-EMS, LAN,
the flash memory design discussed in the following sections, and other accessory cards can use this area.

1000000H (16IotByt ••)
EXTENDED
IotEIotORY
100000H (1IotByt.) ,
PC/XT/AT PS/2
ROIot-BIOS
FOOOOH (960k)
PC/AT PS/2
ROIot-BIOS
.

EOOOOH (896k)

./'

PAGE IotEIotORY BOARD CAN
BE INSTALLED
WITHIN THIS
128 Kbyt. AREA ............

OPTIONAL I/O
ADAPTER ROIot
COOOOH (768k)
DISPLAY
BUFFERS
AOOOOH (640k)
APPLICATIONS
DEVICE DRIVERS
DOS
OOOOOH

Figure 9. DOS Memory Map

4-209

292079-25

infel·

AP-343

onent numbers shown with the -following diagrams correlate with the actual schematics in the appendix.) A
page size of 64 Kbytes is uSed. Depending 'on the system's configuration. memory contention may require a
smaller page size. (Note that the LIM EMS 4.0 standard uses 4 contiguous 16. Kbyte pages. Multiple pages
can exist as space permits.).

Figure 10 shows the block diagram of the page-mapped
flash memory board design. (Except for.the addressing
method. all the functional components of this board
could be used on a linear or VO mapped flash memory
array.) This PC-Ar** compatible design. example
consists of a flash memory array (using SIMMs) and
the corresponding memory and I/O decoding. Vpp
generation. and the interface to the system bus. (Comp-

,

1
ADDRESS

I/o

DATA

DECODE

PRESENCE DrnCT

I/o CONTROL

~

SELECT

Vpp ENABLE

vpp
GENERATOR

SYSTEM
BUS

FLASH
MEMORY
SIMMs

vpp

I

MEMORY CONTROL

I

..

CHIP ENABLE

MEMORY
DECODE

RD iffi

(CE)

WEH

TRANSCEIVER SELECT

. 292079-26

Figure 10. Page-Mapped Flash Memory Board
NOTE:
A similar hardware platform using Intel Flash Memory Cards is contained and described in the Hardware Reference Manual
that can be ordered separately through Intel literature (Order Number 296871).

***PC-ATIII> Is a registered trademark of International Business Machine Corporation.

4-210

int'et

AP-343

The Decoding Scheme
The Intel Flash Memory on this board is installed in 4
SIMM sockets. With a fully populated board, the memory capacity ranges from 4 Mbytes to 16 Mbytes depending on the SIMM density used.
~ending

on the density, up to ei~ chip enables,
are used on a SIMM (4 CEs for 8-chip, 8
CEs for 16-chip SIMMs). Standard decoding techniques generate separate chip enables, output enables,
and write enables. This method has the disadvantage of
having to accommodate a large number of traces. The
C~-CE7'

addressing scheme incorporated in this design minimizes the number of board traces neeed to selectindividual devices. Device selection is made on a row-column: basis where: rows are Output Enables (OEs),
Write Lows (WRLs), and Write Highs (WRHs) and
columns are Chip Enables (CEs). (For low-powered
systems, this method may be unacceptable because each
chip enable activates a maximum of 8 components.)
These signals are generated by decoding the page lines
P3-P7 (Figure II, U22). (See Page Number section.)
Pages within a component are selected by tying Po, PI
and P2, respectively, into pins 37 (AI5), 36 (AI6), and
35 (A17) on the SIMM (Pin 35 is a no-connect (NC».

74F138
3 TO 8 DECODER
CEo

;-A
-8

YO
Yl

,-c

Y2

-S
Fo

Y3

U22

Vee

Y4

Gl

Y5

G2A

Y6

G28

Y7

74139

P6 - A

YO

P7 - 8

Yl
Y2

U24B
R~G

Y3

CE7

I-

OEo
OE,

74139
YO
Yl

U28A Y2
Y3

L----

CS z

A,6- Z3

00- 7

lOW

AO- tS

°0-7

SELECTS PAGES

At 6-23

ClK
ClR

T

10 PAGE
NUMBER
(from I/O decode circuitry.
RESET
not shown)
'(forces page zero on power up)
292079-29

Figure 13. Memory Card Interfacing

4-213

intel·

AP·343

The page inputs to the "Chip Enable" decoder (Figure
14, U22) are redefined as follows:
P3 = P3, P4 = P2, P5 = GND,
P6

= P4, and P7 = P5.

For a better understanding, you should verify the bit
combinations while stepping through the first few
pages. Notice that the sequencing of page numbers does
not correspond linearly with the Chip Ell8bles. This is
not significant because the data is read the same way it
is written.
Chip

Page
Number.

Enable

0,1,2,3
4,5,6,7
8,9,10,11
12,13,14,15

0
2
1
3

NOTE:
Linear Page Selection Results In
Nonlinear Chip Enable.
74F138
3 TO 8 DECODER
PIN ARRANGEMENT
AFTER JUMPERING

P3

YO~------------------------------------'
YI~--------------------------------

...

U22

ENABLES FOR HIGH AND LOW BYTES

PO
PI
P2
292079-30

Figure 14. Component Selection Relative to Page Number tor 1 Mbyte SIMM .

4·214

int:el..

, AP-343

1/0 Decoding
Multiple functions can be implemented with I/O decoding access. Some examples include: reading the current window address, reading the presence detect'pins,
enabling Vpp, and reading/writing the page number.
The eight consecutively addressed I/O ports on this
board (4 reserved for optional features) are located at a
user-selectable address. This base I/O port address is
setup on an 8-byte boundary by using A3-to as inputs
to the 74F521 comparator (Figure 15, U30). When any
of the eight consecutive I/O port addresses matches the
dip switch settings (and AEN is low), the comparator
outputs the I/O Decode Enable (to decoder U31).

AEN (address enable), the chip select for the 74F521
comparator, is supplied 1:>Y the PC I/O channel. It distinguishes processor bus cycles from DMA bus cycles.
A high on AEN indicates that a DMA (or DRAM
refresh) cycle is in progress and we must stay off the
bus. The enables for the 74F138 10DECODER (U31)
are provided by 10DECODE ENABLE along with the
"ANDing" of lOR and lOW. This decoder selects the
I/O ports that access the page window address, the
SIMM presence detect pins, the Vpp Enable, and the
page number. Each of these I/O ports are described in
detail:

74F521
COMPARATOR
SWITCH

- - - - I PO

~~~§PlP3P2
P4

===1P5
=
P6
P7

G

00

U30

USER SELECTS ONE OF 256
ADDRESSES

02
01
03
04

05
06
07

P=Q IO-----~-, 10 DECODE ENABLE

AEN
ADDRESS INPUTS BEGIN AT A BECAUSE
(ADDRESS
10 PORT RANGE OCCUPIES 8 CONTI~OUS ADDRESSES
ENABLE)

74F138
3 TO 8 DECODER
yok>~~~------

Yl

C

k>~~~....;.----­

Y2k>~~~------

U31
Vee

Y3
Y4 k>...:R:::EA:::D:...W::.:I~NDO=W~A:::D::::DR:::E:::S::.S__
Y5

READ PRESENCE DETECT PINS

Y6t>~V~P~PE~N~_ _ _ _ ___

Y7

READ

RITE PAGE NUMBER

292079-31

NOTE:
"Discussed in Board Identifier section of optional features.

Figure 15. User Selectable I/O Base Address for 1/0 Decoding

4-215

AP"343

The Window Address
The user-selectable window address can be set up on
any 64K boundary below 1 Mbyte. (The memory window should be placed between COOOOh and EOOOOh to
be DOS compatible.) A DIP switch (connected to a
transceiver for reading) and the four address lines A1619 are the inputs to the 74FS21 comparator (Figure 16,
U21). There are 16 possible window addresses. The
comparator outputs the "Memory Decode Enable"

signal when an address is selected that is within the
64 Kbyte window. This signal (with AEN low) allows
board level memory decode.
The location of this 64 Kbyte window can be moved
l;Ibove 1 Mbyte by addingA20_23 to the comparator's
inputs P4 to P7 of the 74F521. Bits D4-7 of the data
bus can be connected to the comparator's pins Q4 to Q7
to allow reading of the full base memory address.

READ AS 10 PORT

74FS21
CO~PARATOR

A I6 - - - - t P O

USER SELECTS 16 POSSIBLE
BASE ADDRESSES ON
64 kBYTE BOUNDARIES

PI
P2
P3

A17

A 18
A19

P4
";-+---1 PS
GND

U21

P6
P7

GND (AEN°)
AtN (BRDRST') """';--01
(ADDRESS ENABLE)

G
292079-32

°NOTE:
Ignore the contents within parentheses. This is used for section on master/slave configuration.

Figure 16. User selects Base Memory Address

4-216

infel~

Ap·343

. generate their own 12V· power supply. However, it
should not be used if its regulation is greater than 5%.)
On power-up, system reset, or when Vee is below 4.5V,
Vpp is forced off. It is enabled (or disabled) by writing
to the I/O port address (Figure 15, U31) that generates
the VPPEN signal. This on/off capability is essential
for battery-operated equipment and eliminates the need
for WE filtering (as discussed below). (See Intel data
sheet for Vpp standby current.) The VPPEN signal·
"ORed" with the system I/O write, lOW, functions as
the clock signal for the 74HC74 D-flip ~(Figure 17,
U42A). The D-input is latched when lOW goes high.
Writing a one or a zero turns Vpp on or off, respectively.

Presence Detect
The method shown earlier in Figure 3, is used to configure the PD pins in this design. SIMMs can be added
incrementally only in similar densities. The SIMM PD
pins are read by selecting the appropriate I/O address
that enables the 74F245 transceiver.

vpp Generation
Vpp is generated locally (on this board) to ensure a
stable, switchable 12V (±5%) supply. (Many systems

:c

Road to dotermln,j.0_ _ _ _
Vpp status

Vee

5.6V

......_ _~+_Vpp
(12V. 200 mA)

I

270k

OJ-..itJIIv--_--.....{

CLK

RESET
(Vpp Off ON POWER-UP)

100 }'f

GND

CL

GND

GND

RESET
r - - - - - - - - - - - - - - - - ( I r o m system bua)

292079-34

Figure 17. Vpp and RESET Generation

4-217

AP-343

Linear Technology's LTl072"(U4l) switchhtg reguiator '
is used as a SV to l2Vboost converter. The FB input
regulates the voltage outPut. The 1O.7k and 1.24k resistors are used to establish the correct reference voltage
to obtain l2V. The 100 ,..,F capacitor at the output is
used to himdle up to 200 mAo (See Linear Technology's
LTI072 data sheet for more information.) Typically
this will be much more than needed and a smaller capacitor can be used. However, this will accommodate
interleaving of 8 components but may not be practical
in a battel1'-operated system. (See section on interleaving in the Software Design. Implementation chapter.)
Additionally, sufficient time should be allowed when
switching Vpp on. The delay is a factor of the load on
die line and the quality of the passive components chosen. The diode, MUR120, keeps the inductor from absorbing current from the charged output capacitor. The
S.6V zener diode ensures' that when Vpp is less than
S.6V, the Vpp output is held at OV. (This is optional if
Vpp'S; SV is tolerable.)

During system power-up, some probability, exists. that
noise may generate spurious 'writes which are actually
the sequence of flash memory commands that initiate
erasure or programming. Power-up protection in this
design is provided by disabling Vpp until voltages have
stabilized. The Motorola component, MC34064P
(U44), is an undervoltage sensing circuit that begins
functioning when Vee is above IV. Between IV and
4.6V, the RESET output is active. The RESET output
or a system RESET clears the 74HC74 (U42A), keeping Vpp offwhen Vee is less than 4.6V. Alteinatively,
this s~, or .!.!upply's "POWERGOOD" signal, may
gate WE or CE, as is. common with battery-backed
SRAM or EEPROM designs. As an example, the
RESET output of the MC34064P can be tied to the
active-high enable of the decoder' to disable any CBs
until Vee = 4.6V, as shown in Figure 18.

Vee

RESET
I/C34064P

•.u.~

,

,

l'Ok

UNDERVOLTAGE
SENSING CIRCUIT

A3
A4

As

74HC138
3 TO 8 DECODER
A
YO
B
Yl
C

r-

Y2 rY3 ...
Y4 rYS ...
.I/EI/DECODE

*

Gl
G2A
G2B

GND

Y6

Y7

292079-35

Chip Enables will not be active until Vee = 4.6V.
At this point, signals are stable and involuntary writes will not occur.

Figure 1S.'Protectlng the Circuit from Involuntary Erasure and Programming.
Use an ~ndervoltage Sensing Circuit, or a System's "POWERGOOO" Signal, to Control Chip Enables

\

4·218

intel·

AP-343

How is Vpp Switched on (Refer to Figure 17):

Latching a one into the 74HC74 D-input (U42A) puts
a zero on the output Q. This turns off the transistor
2N3904. When the 2N3904 is off, the VC input of the
LTI072 (U41) is 5V and the VOLTAGE SWITCH
(VSW) output generates 12V.
/

Page Number Selection and Reading
It is standard practice to use an I/O port to generate
the page number for this type of memory array. The
potential number of pages that can be selected is determined by the size of the data bus as well as the amount
of decoding the system can practically handle..In this
design, this I/O port allows selection of 256 64-Kbyte
pages, for a total of 16 Mbytes of flash memory. The

page number is written to the 74F273, Octal D-Type
Flip-Flop (Figure 19, U37). It is latched by the rising
edge clock signal derived by the "ORing" of the corresponding 74Fl38 decode signal (I/O PAGE NUMBER) and the system lOW.
Page zero is automatically selected on power-up because the 74F273 clear input is connected to RESET
(generated as part of the Vpp circuitry). This feature
ensures that the board will power up in page zero.Given the proper software, this board can. be turned into
the system's bootable drive. (See section on Software
Design Implementations.)
The current page number can be obtained by reading
the same I/O port. The I/O decoder output, 1(0
PAGE NUMBER, "ORed" with the system lOR, produces the signal enabling the 74F245 bus transceiver
(that is tied to the output of the 74F273).

74F273
(OCTAL D-TYPE FLIP-FLOP)

10 DATA 0-7-

00

01
02
03
04
05
06
07

lOW
10 PAGE
NUMBER

-:J'
-/

U37

ClK
ClR

I

RESET
(FOR STARTUP AT PAGE ZERO)
' - - AO

......-

.

lOR
10 PAGE
NUM8ER

-- "

:::J

.".

QO
QI
Q2
Q3
Q4
Q5
Q6
Q7

..

AI
A2
A3
A4
AS
A6
A7

U38

80
81
82
83
84
85
86
87

t--

c'

G

.g:- DIR
74F245
, (OCTAL 8US TRANSCEIVER)
292079-36

Figure 1.9. Selecting or Reading Page Number .

intel .

AP·343

Design Considerations

Optional Board Features

The SIMMs high and low bytes are enabled by WEH
and i WEL. respectively. Using a high and low byte
. transceiver for each SIMM limits the capacitive loading
and prevents performance degradation of the data bus.
(This becomes important when upgrading to flash
memory SIMMs that have 16 components. See section
on capacitive loading.) Also. the PC ~/O channel bus
specification requires that no more than 2 TIL-loads be
present on any one line. Therefore. the SIMM transceivers must be routed through two additional transceivers at the PC bus interface (refer to· "Switchable
Data Bus Width" section). In this paged memory board
design. the SIMM transceivers are enabled by a 2 to 4
decoder which uses page pins P6 and P7 as decOde signals. The enable for the decoder is supplied by the
MEMDECODE signal; transceivers are disabled Unless
an address within the 64 Kbyte page is accessed.

So far we have described the componenis reQuired to
design a functional flash memory array. Optional features can be added to make this board more versatile in
an application environment:

Swltchable Data Bus Width
This feature allows the board to execute,in a PC XTo .
(8-bit bus) or a PC AT system (l6-bit bus). Memory
card designs for adopting the PCMCIA/JEIDA format
must include similar provisions as shown earlier. At the
PC-I/O channel interface. (for use in an 8"bit systein).
an extra transceiver is uS,ed to redirect the upper, data
bus (DS-Is) to the lower data bus (Figure 20. U9). The,
16BITsignal is generated from a ground on the PC AT
I/O channel extension; it will be high (because of the
pull-up resistor) when a PC XT is used. (The 16BIT
signal can be read by software through the 8th bit of the
Presence Detect port.)

An extra transcelyer Is used to redirect
the upper dota ,bus to the lower data bu.

, I LOW a-16-BIT I

-

Do
PO
D,
PI
D2
P2
D3
P3
D4
P4.
Ds
P5
D6
P6
I>? P7

U10

I

00
01
02
03
04
05
06
07

----? P7

I

00
01
02
03
04
05

U9

06
07

D8
D9
Dl0
DII
DI2
D'3
D'4
D'5

G
DIR
74F'245

Do-D,s

00
01

U11

02
03
04
05
06
07

LOW a-16-BrT
'

,

G
116-BIT
DIR.

/f

-,

"-

HIGHa-BIT~

I

Ao

~~DECliiiE

EM DECODE

,74.245
16-BIT

/f

~

f=ry
......J

lOR

St.iEi.tR

'rom
ground
ofAT
16BIT 10
channel

10k
TI

292079-37

Figure 20. 110 Channel Transceiver Interface for 8- or 16-Blt Data ,Bus Selection
·PCXT" is a registered trademark of International Business Machine Corporation.

4-220

infele

AP-343

Access to, a word (2 bytes) requires two bus cycles to
generate two addresses in an 8-bit system. As an example referring to Figure 20, when accessing a memory
word at address zero (0):
1681T = 1, MEMDECODE = 0;

During access to the low byte ~ AO = 0, so the signal
"LOW 8/16 BIT" is active;
During access to the high byte signal "HIGH 8 BIT" is active.

AO = I, so the

The circuitry at the SIMM transceiver interface determineS whether to, use the Bus High Enable (SBHE)
signal or Ao to select the high byte. The 16BIT signal
selects the "A" or "B" inputs of the 74F157 multiplexer (Figure 21, U27). Regardless of the bus size, the
WRL signal is generated on a system memory write
(SMEMW) to an even address (AO = 0). During a 16bit write, the WRH signal is generated by a system
memory write to the high bus (BHE). However in an 8bit system, where SBHE is absent, the WRH signal is
generated by a system memory write to an odd addressed byte (Ao = 1).

The high byte from the SIMM is multiplexed onto the
low byte of the system bus.

TO WRL DECODER ENABLE

TO WRH DECODER ENABLE
1Y

2A

Aol----.....

2Y

2B

LOW BANK

U27
PC Xl
3A

)
)

TRANSCEIVER BANK DECODERS

3Y

HIGH BANK

GND
PC AT

(not present on PC XT)

4Yi------NC

MEMDECODE

(from addreiss comparator)
GND

74F157
, (MULTIPLEXER)
292079-38

Figure 21. 8- or 16-81t Data Bus Selection at the SIMM Transceiver Interface

4-221

bank is selected by an odd address (Ao= I) in conjunction with theMEMDECODEsignai.

The eight transceivers for the four· SIMMs are selected
by signals TO-7. Even(fo. T2' T4; T6) and odd (T],T3.
Ts. T7) numbered signals decode for the .SIMM low
and high bytes. respectively. The .signals TO":'7 are derived by decoding P6 and·P, (Figure 22; U24A) and the.
.transceiver bank decoders (Figure 21. U27).

Master/Slave Configuration
This feature allows the system to accommodate more
than :one board. The board reset signal. BRDRST. of
Figure 23 is used to enable the board. The comparator
(Figure 16. U21) that generates the MEMORY DBCODE ENABLE must be reconfigUred:
1. ABN is connected to P7;
2.BRDRSTis connected to the chip enable.G.

For a 16-bitsystem.the MBMDBCODE signaIselects
both the low and high·banks. For an 8-bit sy~tem. the
low bank is selected by generating an even address (Ao
= 0) in conjunction with the MBMDECODEsignal;
Since SBHB is absent (in an 8-bit system); the high

TRANSCEIVER BANK DECODER

T (0-7)

. (LOW BANK)

(to SIMM
tronscelve.,)

TRANSCEIVER BANK DECODER
(HIGH BANK)
292079-39

Figure 22. Transceiver Selection at the SIMM Interface

r~----------~~-_jJl~-_-_-_-_-_-_-_VPPEN
iOii
74F32
I/o DATA 1-----......,---_---~

1---------------------.....

74F125

t-~M~AS::.:TE~R:.;B:::O:::A~RD::.··_·__+_··_'-oJPlp.l-

U45A

.....--Rffii'

JUMPER
I

....-------10

74F74

(from Vpp gonoratlon
circuitry)

01---------",

(D-TYPE POsITIVE EDGE

. TRIGGERED. rLlP-rLOP)

IOw-------r....
VPPEN
)-----------D elK

QI-----------------.....j~ BRDRST

74F32

t-__S:::L::::AV:,:E;.lB;:::0;::.AR::,:D:.-______-oJP12
FUNCTION
MASTER BOARD

SHORT JUMPERS
JPll,JPf3

SLAVE BOARD

JP12,JP14

(to BASE MEMORY
.ADDRESS 74F521
COMPARATOR ENABLE)

JUMPER
Vee

JP14
JUMPER

Y

~

292079-40

Figure .23: MasterlSlave Configuration for Multiple Boards

4-222

AP-343

The jumper settings determine if the board is "active"
on system reset (BRDRST will be' low). The Master/Slave port is shared with Vppenble; therefore to
change the "active" status of tile. board, write to the
VPPEN I/O port. Software should first read.this port
to determine the status of "Vpp Enable", then use the
appropriate mask technique t9 activate or: deactivate
the b o a r d . '
.

The hardware consists of 4 DIP switches and associated 74F245 transceivers (Figure 24, U33-U36). Each
switch is read by selection of its I/O .address (Figure IS,
1,lse Blo-BI3). The DIP switches can be replaced by
EPLDs that permanently "hardwire" the settings. In
this, case, the identifier is changed by reprogramming
the EPLDs.
~ero-Wait-State

Board Identifier

Selection

The zero-WAIT selection feature is only applicable in a
PC AT system. Driving a low input to the OWS pin of
the PC I/O channel within 21.5 ns of MEMR or
MEMW going low keeps, the system from inserting the
standard WAIT-states into the I/O channel bus cycle.
On the page memory board, the OWS signal is generated by the Boolean equation: .

The board identifier, occupying 4 additional I/O ports,
is'.used .for two functions:
1. To locate the board within the system I/O space, and
2. To identify the board version to 'assure the software
matches the hardware.
''
. , . . , . ,:. ,

(SMEMW • SMEMR)

+

MEMDECODE = OWS.

I/o DATAO_7

8

(To system bus
transoelver)

SWITCH 0
PO

QO

SWO

PI

Ql

SWl

P2

Q2,

SW2

P3

Q3

SW3

Q4

SW4

Q5

SW5

P6.

Q6

SW6

P7

Q7

SW7,

P.
P5

U35

Blo

,lOS

74F24S

PS

U32

SWO

Ql

SWl

Q2

SW2

Q3

SWl

Q4

SW4

QS

SWS

P6

Q6

SW6

P7

Q7

SW7

.QO

SWO
SWl

GND

8

74F24S

SWITCH 1
QO

I/o

P3

10.
P4
105

QO

BI2

GND

B10-3 com. from

SWITCH 2

10 0
PO
10 1
Pl
10 2
P2
10 3

SWITCH 3

SWO

PO

Ql

SWl

Pl

Ql

Q2

SW2

P2

02

SW2

Q3

SW3

P3

03

SWl

Q4

SW4

P4

04

SW4

QS

SWS

PS

QS

SWS

, Q6

SW6

P6

Q6

SW6

Q7

SW7

P7

Q7

SW7

decoder

U34

U33

G

BI3

DIR
GND

74F24S

GND

74F24S

\

NOTE:
DIP switches can be replaced with EPLDs.

Figure 24 •. Hardware IJsed to,Loc:ate and Identify Page Memory Board

4-223

292079-41

intel·

AP-343 ,

Next, the Window B~e Address 110 port is used to
lOcate ,the "page" in DOS's memory spa~. It is then
necessary to determine the density of iheSIMM~ and
the total m~ory available.
'

Initializing SoftWare for the Paged
Memory Board'
"
(The assembly language software is included in the Ap',' '
. "
pendix.)

L~catlng

In the following sections, algorithms will be shown that
verify the page-memory board's functionality. To access this board, first find the location of the base I/O
address. From Figure IS, the board's I/O ports are accessed as offsets of the I/O base address:
Board Identifier n
@ Base AddreSs + 'n
, (n == 0, I, 2, 3)
WindoW Base Adcrress
@ Base AddresS + 4
PresenCe Detect Pins
@ Base Address +5
Master/Slave and VpPEN @ Base Address + 6
Page Number
@ Base Address + 7

Use the board i!ientifiers to locate the base I/O addreSs.
The Software reads I/O lqcations until the correct byte
sequence i~ found' (Figure 25). Some discretion should'
be made when choosing the board's I/O address. (See
table of I/O poi:t usage in Appendix.) The:.,C XI and
PC AT specification Iillocates 32 I/O ports at 0300hto
031Fh for prototype cards. We will use this Sddress
range for, this example. Bectluse the I/O ports for the
paged-memory ~ard inUst begin on an 8-byte boundary, tJte 9nly possible base addresses are 300h, 308h,
310h,318h.

NO

NO

NO

NO

BOARD LOCATED

the Base 1/0 Address

PORT..,PTR =PORTJ'RT + S'

PORT..PTR = PO~TJ'TR + 7'

PORTJ'TR =PORLPTR

+,'

PORTJ'TR =PORTJ'TR + 5'

• This step Is perform.db.caus. the I/O ports
for this board must begin on an S-byt. boundary

292079-42

Figure 25. locating the Page-Memory Board

4-224'

intel ~

Ap·343

Locating the Base Memory Address

Determining Memory Capacity

The base memory address gives the location of the page
within the system's memory space. The address switch
settings for A16-A19 are read from the correct I/O
port, Base Address + 4 (Figure 15). After reading
these address lines they are stored in the ES segment
register used as a pointer to access that memory segment. A16-A19 must be shifted into the upper nibble of
the ES register.to allow proper address generation.

SHIFLREG=l
SOCKETS = 0
PAGE#=O
READ PRESENCE DETECT PINS
MASK OFF UNUSED BITS
PUT PDS IN BIT POSITION 2

First ensure the board is set to read from Page O. The
PD pins are read and translated, using a lookup table of
SIMM densities, to a functional value. Then the device
identifiers should be read to determine:
1. The number of components on each SIMM;
2. the number of SIMMs installed on the board;
! 3. and which sockets are used.

Initialize variables.

Only interested inSIMM density info.
Combine density info bits within byte.
The value will be 2.3, or 4 verifying
the presence of a 1,2, or 4 Mbyte SIMM.

Density is stored as multiples of 1 Kbyte.
Determine individual component density.
Lor 2,Mbit Intel flash memory devices on SIMM.

DIVIDE SIMM .DENSITY BY DEVICE DENSITY

SIMM socket is full
"Sockets" used as a bit map.
As an example, if SOCKETS = OFh,
all 4 sockets are full.

SHIFLREG = SHIFLREG • 2

Derives component count on SIMM.
Move binary 1 to next bit address.
To access next SIMM location.
NO .

Check all sockets.

ALL SOCKETS ACCOUNTED FOR
292079-43

Figure 26. Determining SIMM and Component Densities and Locations

4-225

intel .

AP-343

Linear Addressing
Linear addressing directly maps the flash memory array into the system's memory space. "Instantaneous
Access" of the entire array is the obvious advantage
over paging. Additionally, the decode circuitry is simplified. Figure 27 shows an example for accessing 16
Intel Flash Memory 28F020s arranged in a 4 Mbyte
linear array.
The number of address lines used, as well as the decoder type (2 to 4, 3 to 8, etc.), is determined by the flash
memory device size. The address lines A I - A 18
are used for byte .selection within each device
(256 Kbytes • 8).

The decodes for the individual devices can be designed
in a row-column method similar to that used for the
page memory board. An alternative design uses an individual chip enable for each of the· 16 devices.
The enable for the 74HC138 (3 to 8 decoder) is governed by a 74F521 comparator, System address inputs
to the comparator are chosen to locate this array on a
4 Mbyte boundary. (The array base address could be
located on a non-4 Mbyte boundary but this would add
to the decoding complexity.) With the inputs chosen in
this example (A22-A23), the array base address will be
between address 0 and 12 Mbytes to confme this memory array within the PC AT defined address space of
,16 Mbytes. AI9-A21 are inputs to the decoder which
generates one of the eight chip enables (CE). (Use a
74F245 transceiver for the data bus of every 8 flash
memory devices. The address lines also need butTering
when connected to a PC bus.)

HIgh and low byte •• Iectlon
A22 and A23 are

system addre•• Inpul.

P=Q

---------'"

TO 16- 28F020'.

CEo
CE I
CE2
CE3
CE.
C~

CE6
CE7
74F138
GND

ENABLE

AI - AI8

TO 28F020s
74F245
292079-44

Figure 27. Linear Addressing Hardware Block Diagram

4-226

AP-343

I/O Addressing
From the standpoint of the system's address space usage, I/O addfessing provides a conservative solution.
As an example, four gigabytes of a flash memory array
can be addressed through only two 1/0 ports. An 110
write sends the flash memory addresses out on the data
bus. This "data" is latched (using '574s) and made
available to the flash memory devices and decoding circpitry (Figure 28). A third 1/0 port, used as an enable
for the flash memory device decoder and transceivers,
helps conserve power when the array is not being accessed.

Relative to linear addressing, 1/0 addressing generally
has limited access speed capability because of the 110
"bottleneck". Read speed can be increased to match
linear addressing by replacing the '574 latches with
'191 counters.
In the following circuit example, decoding for 1/0 is
accomplshed with a 74F138, 3 to 8 decoder (Figure 29,
Ul). The base address for these 1/0 ports is on an
8-byte boundary. When anyone of the 8 110 ad-------~

p[ij

)------+i'U
74F138
3 TO 8 DECODER

SAo

5',

•

SA,

Ul
)----.CLOCK....PULSE

10-------------":-----------+ v,,'"

OIP SWITCH
TO SET

U2

I/O BASE
ADDRESS

P=Q

7""521

COMPARATOR

292079-46

Figure 29. I/O Decode and Enable Circuitry
4-227

intel .

AP-343

An I/O write to the first and second ports generates
parallel load signals, PLo and PLI. These signals latch
the "data" (addresses) into the 4-bit counters (Figure
30, U3-UlO). This latched data represents the address
for the flash memory devices.

A read or write from the selected flash memory address
is performed when the third I/O port is accessed (Figure 29, Ul); this generates an enable for the fla,sh memory device decoder and associated transceivers (Figure
31, To and TI)'

TO 1628F020'.

TRANSCEIVER
BUFFERED
DATA BUS

GND

GND

Do

DjO

."---D~ A
• '---0":"... B

OA - + Ao
QB - + A,

C

OC --+"' A2
QD - + A,

-+

."-_...::.'...... 0

~

RCO

r- ~

CLOC1<-PULSE\..

l

DO
D/U
1"--"'0::",~A
O2 B
---0 C
1"-_..:.'..::.'...... 0

~

r"""'DilJ
QA - + A.
.'---Io_~..:;.:... B
OB - + A5

-

0

~

QC - + A.
QD - + A7

-~ C

."---'......:.":....1 0

'---

~

--+-

D.
."--'--~"-I C
1"--1-""':"'-10

Ag

QC-+A,O
00 - + Al1

::]

-

D""

OA - + A'2

C oc

,,-..,L..,;..:;'5U 0

E

A,.

00 - + A15

f-+ A2 •

r--+ A25
r--+ A2.

!--+ A27

Rcon

~

."--'-_0.:.:'2..... A

QA

f-+ A28

,QB

r--+ A2.

'--1--.:..::..... D

QC
QD

ROO

!--+ A31

E

I'--I-...;~.:.:::~B
0'5

RCO!----'

L-------+---fi'l
CP

-+

OA
OB
OC
00

~

0:: B OB :.-.....,. A13

-

~

8 -I A
1"--1-..,0::..
1'--1-...;0:...-Ie
."--'-_D.;.:,O..... C
11-1 0
1"--1-_0':':

-~

~

."---'_~..:;'2:....1 A

Rcon

-~

'---

"

f-+
C
OC " . . A22
00 f-+ A23
OA
A20
OB L-... A21

~

QA - + A8
OD

!--+ ",.

~

ROOl

~

_'---Io_jj"":;'.'" B

C

Vee

ROOn

.,,--,-_0.::..
...... A
5 -IB
1'--1-";.;;0.::..

'---~

• "---'_~..::.8...... A

f-+ A16
f-+ A'8

r--+ A17

~~-~~-~~

."---'_0.;:.
....... A

."---'_D..:.7...... C

QA
OB
QC
00

C

f-+ A,o

+----I--Ii'l
U6

-

'74Hci'9;"

CP

Ul0

74HCi'9i
292079-47

NOTE:
Ao-Asl are inputs to flash memory devices. Only address lines Ao-A1B are used for the
28F020s.

Figure 30. Counter Circuitry

4-228

GND

292079-48

NOTE:
All counters are configured in the UP count
mode.

infel·

AP-343

.~------------------~--------------------WEL

_$0
.
lOW

•
BHE

~-----------------------------------------------------WEH

o0-07
TO TRANSCElVER
BUFFERED
DATA BUS

AO
AI
A2
A3
A4
AS
A6
A7

:-0

TO

BO
Bl
B2
B3
B4
B5
B6
B7

FDa
FO,
F02
F03
F04
FOS
FDs

,

F~

G

1""'- DIR

74F245
(TRANSCEIVER)

DATA
ENABLE

AO
AI
A2
A3
A4
AS
A6
A7

74F125

'10

T1

BO
Bl
B2
B3
B4
B5
B6
B7

FOs
FOg
FO '0
FOil
FD'2
FO '3
FD'4
FO 'S

G
Os-0 ,5
TO TRANSCElVER
BUFFERED
DATA BUS

DIR

TO DATA BUS OF
FLASH MEIilO RY
DEVICES .

74F245
(TRANSCEIVER)
292079-49

NOTE:
The 16-28F020's are arranged as a 16-bit word configuration. WE[ and WEH are for the low and high bytes, respective-

ly.

Flglire 31. Transceiver Enable Circuitry

The fourthI/O port activates the circuitry that obtains
very high performance from an I/O board. A read from
the fourth I/O port address generates the clock signal
for the 74HC191s, CLOCK-PULSE. The counter increments on the· rising edge of the clock (read signal),
selecting the next flash memory address. This rising .
edge occurs at the end of the I/O read cycle and the
data has already been read. This method is analogous
to address pipelining. It is perfect for a "string" read
because continuous reads from the fourth I/O port automatically increments the address to access the next
word of data stored in the flash memory array.

Capacitive Loading.
Capacitive ·Ioading is animportaDt consideration for a
solid-state mass storage device. If proper buffering
techniques are not followed, performance degradation
..
will occur.
The specifications for Intel's Flash Memory devices are
based ona test capacitive load of 100 pF. Each data line
contributes 12 pF, therefore 8 devices connected to one
data transceiver will not experience speed derating
(12 pF • 8 = 96 pF). Additional flash memory devices

4-229

infel .

AP·343

on that transceiver will increase the loading seen by any
one device.
'
Degradation is calculated as follows (Q = Amount of
Charge, T = Time, C ==, Capacitance, V = Voltage, ,
and I = CUrrent):
'
COULOMBS LAW STATES:
Q = IAT

AND GIVEN THE RELATION:

v=

AQ/C -

1= CAVIAT
\

FROM THIS RELATION, THE CHANGE IN ACCESS TIME CAN BE EXPRESSED 'IN TERMS OF
CAPACITIVE LOAD:
'
AT';'C AVII

For example, using four SIMMs, each with 8 components in a 16-bit configuration (4 components on high
byte and 4 components on low byte), each Intel Flash
~emory device sees a load of 15 devices (12 pF • 15 =
, 180 pF). This loading is 80 pF inexcess of the device
'
specification so therefore: '
Time

_ Additional

x (Vee - VoLl

Change - Capacitance
=

0 F

BpX

IOL

(5.0 - 0.4)V
5.BmA

= 64,s
n

disks will also be replaced by Intel's Flash Memory
when higher reliability, lower power consumption,
higher performance"and lighter weight are required.

Interleaving
Although the basic concept of data recording is ~
from system to system, variations in implementation
exist. For instance, some applications require high-.
speed data acquisition. Data programming rates are improved considerably by employing interleaving techniques. The majority of time spent programming or
erasing a flash memory deviCe results from the delay
,times ·in the software algorithms. (It is advised to review the standard algorithms fIrSt. See any Intel Flash
Memory data sheet for Quick-Pulse ProgrammingTM
algorithm.) Interleaving takes advantage of these delay
tim~ to begin programming consecutive devic~.
There are hardware and software mechanisms for interl~ving. The flash memory lIl'fl!.y for hardware interleaving requires special decoding techniques (Figure
32). Contrary to linear decoding, the syStem address
lines Ao-A3 are decoded to provide the chip select signals and individual bytes are selected with the address
lilies A4-A20' (For the Intel 28FOIO.) This decoding
technique allows software to automatically access sequential devices by writing or reading sequential memory addresses. (Data accumulated with program interleaving will not be stored consecutively within a single
device.)
The interleaving algorithm to program the 2 Mbyte
flash memory array iS,shown in Figure 34 and 35. The
basic goal is to utilize the delay times. To simplfy the
algorithm for this discussion, the data will be programmed on a byte-wide basis. Word-wide and double
word-wide techniques, discussed l~ter, will further in-,
crease programming speeds.
'

(Reflecting worst case conditions.)

SOFTWARE DESIGN
IMPLEMENTATIONS "
Each hardware implementation discussed above can be '
used in several types of mass storage applications. The
general categories include: data recoders, Write-OnceRead-Many (WORM) drives' for" storing' application,
programs and fixed da~, and magnetic disk emul,ators.

Data Recording
The' applications for data recording represent' an endless list. Examples include digital imaging, digital photography, point-of-sale terininals, patient monitors; and
flight recorders. These systems will use Intel Flash
Memory as a' more economical and reliable' replaCement for SRAM + battery. Aliematively, mechanical

During niulti-component programming, the number of
pulses required could vary between different devices.
Code is reduced if the programming loop doeS not have
to selectively "decide" if a byte has programmed correctly (verified). HQwever, continual programming of a
programmed byte is not necessary and should be avoided. This is done by masking the command sent to that
particular device. ,The RAM table in Figure 33 is used
as a data and flash memory Command buffer. After a
"programme4 bYte has verified, its associated data and
Commands in the RAM table are written with the value
OFFH (RESET comJIllUld for IDtel flash meinory). The
data is also written as an OFFH since this is null pro'
gram data.

4-230

int'el.

Ap·343

A 4: 20) WORD SELECT

74F154
CHIP
SELECTS

AO
Al
A2

"'3

A
B

C
D

0
1
2
3
4
5

Connection of Pins
at the Device Level

6

7
8

System
Address

-+

Device
Pin

A4
As

-+
-+

Ao

A20

-+

A16

9

10
11
12
13
14
15

AI

292079-S0

Figure 32. Hardware Interleaving Block Diagram

2

DEVICE#
DATA

D

1T

3
A'

4
I INP

5

'u

6
T'

F

7

~

n

1/

0 'M

10

n+l n+2
Ip 0 'R T

PROGRAM COMMAND 40H 40H 40H 40H 40H 40H 40H

40H 40H 40H

VERIFY COMMAND COH COH COH COH COH COH COH

COH COH COH

VERIFY DATA

D AI T AI

10rl~DIFr

o

M

A ,

0 ~ E

)
292079-S1

NOTE:
n = 14 for the example shown in text.

Figure 33. RAM Array Used as Data Buffer and Command Mask Storage

4·231

infel .

AP-343

COUNTO=SIZLOF _COt,jPONENT
PTR 1= 1ST ADDRESS OF FLASH t,jEt,jORY ARRAY

~~~~.~~~0
LOAD RAM TABLE (AS SHOWN IN FIGURE 30)
FLAG =OFFFFH
STORLPTR= PTR 1
COUNT 1=MAX-PROGRAt,j_TRIES

FLAG used as indicator for successful byte program
verify.

~~~==~0
COUNT2= # _OF_COMPONENTS
PTR2=lST ADDRESS OF RAM TABLE DATA
PTR3= 1ST ADDESS OF RAt,j TABLE PROGRAM_COMt,jAN
PTR4= 1ST ADDRESS OF RAM TABLE VERIFY-COMMAND
PTR5= 1ST ADDRESS OF RAt,j TABLE VERIFY-DATA

MAX PROGRAM TRIES = 25
16 components for this example.
Initialize pOinters.

CONTENTS AT PTR1=CONTENTS AT PTR3
CONTENTS AT PTR1=CONTENTS AT PTR2
INCREMENT PTR1, PTR2, and PTR3
COUNT2=COUNT2 - 1

Program command to flash device.
Program data to flash device.
To get to next byte location.

NO

All components gone through?

PTR 1=STORL PTR
COUNT2= #_OF _COt,jPONENTS

CONTENTS AT PTR1=.CONTENTS AT PTR.
INCREMENT PTR1 AND PTR.
COUNT2 = COUNT2 - 1

Verify command to flash device.

NO

~~-----------'__N~O~______-.tA

292079-53

Figure 35. Program Interleaving Algorithm (Continued)

infel·

AP-343

Software and hardware interleaving are very similar.
Software interleaving is performed using conventional
decoding and addressing methods. Instead of incrementing flash memory addresses by one to access the
next byte (as with hardware decoding), the address is
incremented by the size of the component. While allowing the use of "general-purpose" (non-interleaved)
hardware, software interleaving requires reading back
the data in the same, non-sequential fashion as was
used for recording.

ly consumes 9 mA (1 mA ICC and 8 mA Ipp) while
programming or erasing; this translates to about 100
mW. If interleaving with 16 devices, about 144 mA (16
devices • 9 mAl or1.6W, is drawn. Battery powered
systems will have a practical limit on the number of
components in the interleaving loop. Failure to accommodate these current levels, resulting ,in Vpp voltage
drop, will compromise programming and erase reliability.

Interleaved erase is useful for erasing an array of flash
memory devices. This approach greatly reduces the total subsystem format time. As specified in the erase
algorithm, each erase pulse requires a 10 ms delay. (See
Quick-Erase™ algorithm in Intel F1ash Memory data
sheet.) Without interleaving, the processor is idle dur- '
ing this delay time./As with program interleaving, this
time is used to begin the erasure of consecutive devices,
thereby reducing the overall erase time.

Wrlte-Qnce-Read-Many (WORM)'
Drives

Further program and erase time can be saved by supplementing the byte-wide algorithm with 16- or 32-bit
interleaving. Extra data and commands are added to
the RAM Mask Table. The major difference in the algorithms involves the verify operation. Depending on
the bus width, 2 or 4 bytes are verified simultaneously
as shown in Figure 36 (for a 16-bit algorithm).

Power Requirements for Interleaving
Current consumption is an important consideration for
interleaving. During programming, each device typical-

>"':"M

~~----...

The optical disk is an example of a typical, WORM
drive application. Its strengths are extremely high densities and low cost per bit. However, it is an unacceptable solution for a low powered, lightweight laptop
computer system. It is this environment' that sOlid-state
drives otTer the greatest benefit. Solid-state ROMs have
historically been used in laptop systems to store software programs that seldom change. When the software
does change, the ROM "application hardfile" is discarded and a new one is programmed.
'
•
Unlike the ROM drive, Intel Flash Memories can be
reused and reprogrammed in a true WORM fashion. A
computer
can load favorite software programs on
the flash memory drive. Adding revised programs to
the drive is accomplished by writing to the next free
space or by erasing and reprogramming the entire
drive. Software drivers can be written to implement this
functionality in most operating systems.

user

PROGRAILCOWMAND~PROGRAII_COIIIIAND

OR OOFFH)
VERIFY_COIlIlAND YERIFY_COIlIlAND OR OOFFH)
, YERIFY..DATA VERIFY_DATA OR OOF'FH)

PROGRAlLCOIlIlAND=$PROGIWLCOIlIlAND OR F'FOOH)
YERIfY_COIlMAN
IFY_COWIlAND OR FF'OOH)
VERIFY_DATA ERIFY..DATA OR F'FOOH)

292079-64

NOTES:
1. MASK the HI Byte with ooH.
2. If the LO Byte verifies, then mask the data. program. and verify command with OOFFH (RESET).
, 3. Mask the LO Byte with OOH.
'
4. If HI Byte verifies. then mask the data. program. and verify command with OOFFH (RESET).
Figure 36. 16-Blt Masking for Verity Operation
"-'234

intal.

AP-343

Disk Emulation
Microsoft has a flash memory tile system for DOS. It
stores and retrieves data or application programs in a
manner that, to the end user, appears similar to a disk
drive. New mes are written sequentially from beginning
of memory. However, when the disk is full, it reclaims
memory ,space for storing additional files.

37). If the drive has been declared as a flash memory
disk, a built-in redirector services the call. (This is very
similar for networked drive accesses.) Otherwise, if the
drive letter is that of a floppy or hard disk, the call is
handled by the standard DOS tile system. The File System provides the link between DOS and the Flash
Memory and Hardware device driver. It changes DOS
tile system commands into a form understood by this
unique file structure.

When an application accesses a disk through INT 21H,
the MS-DOS· kernel checks the drive letter (Figure

Purchased
through
Microsoft

INTEL
FLASH MEMORY
SOLID-STATE
DISK
292079-55

Figure 37. Disk Interface Levels

°M8-00S. and Microsoft. are registered trademarks of Microsoft Corporation.

4-235

infel .

AP·343

The Flash File System Driver is the "intelligence" of
this file system. It searches for:
1. A Boot Record that identifies the file system and
version, and locates the start of the data area;
2. The Root Directory Entry Record and many Directory and File Entry Records.
The file system driver is independent of the hardware
interface to the flash memory disk. The hardware device driver, developed by the OEM or BIOS software
vendor, interfaces the flash memory disk to the flash
file system. It is responsible for the low level calls to the
Intel flash memory devices. The actual implementation
of the interface is dependent on the hardware configuration of the disk (I/O, paged, and linear addressing are
examples).
To minimize fragmentation losses and allow arbitrary
extension of files, the flash memory file system uses
variable sized blocks rather than the standard sector/
cluster method of more traditional file systems. The
fundamental structure employed to offer this flexibility
is based on linked list concepts; files are chained together using address pointers located within directory entries for each file.
Files and directories are written to the flash memory
disk using sequentially free memory locations-a stack,
like operation (Figure 38). Furthermore, file sizes can
be variable, abandoning the traditional sector/cluster

approach of DOS. When "the stack" is full, (containing
deleted files), the intelligent software algorithm performs a cleanup operation to reclaim the "dirty" space.
File and subdirectory information is attached to the beginning of each file, unlike the standard DOS approach
of directory and. FAT placement. As directory and file
entries are added, they are located by building' a linkedlist. Besides containing the customary fields (e.g., name,
extension, time, date of creation, etc.), a directory and.
file entry contains a status byte and various pointers
used for the linked-list process. The status byte, besides
indicating whether a file/subdirectory exists or is deleted, is also used to signify valid sibling and/or child
pointers and to determine if a directory entry pertains
to a file or a directory.
When a directory or file is requested or added, the flash
memory disk is searched beginning at the head of the
linked-list. The chain is followed from pointer to pointer until the correct entry is found. If the search arrives
at the chain's end (an FNULL is encountered), the system responds analogously to DOS with a "File not
found" message.
This linked-list chain consists of two basic types of
pointers: sibling and child. Sibling pointers are used to
locate directories or files at the same hierarchial level.
Child pointers are used to locate subdirectories or the
first file of a particular directory. The following examples elaborate these concepts.

292079-56

Figure 38. FFS Storage

4-236

infel·

AP·343

In Figure 39, Directories B and C are subdirectories of
Directory A. SPec~c811y, Directory C is a sibling of
Directory B and both are children of Directory A.
FNULL indicates the !md of th~ chain.

is a va:lid or deleted file. The directory information of a
deleted file is used for pointers of the linked list and the
search would proceed until the most reCent version is
found.

figure ~ shows t~o files (File A and File B) added to
a directory (DirClltory A). Fi\e A; ~d File B are at the
same level, therefore they are'siblings. A file's file ,entry
cOntains
ext~nt ,lOcation pointerthilt indicates the
startoqts data area."
",
,

A key point to be made for using this method of file
storage is that the user is in control of the rate in which
the disk becomes full; using the flash memory disk predominantly for application code, storage and non-temporary data files reduces the frequency of "cleanup",
However, flash memory will typically perform 100,000
cycles and eliminates reliability concerns when used as
Ii hard or floppy disk replacement.

an

When a: file appe&rs multiple times (because of deleted
v~fsions) on the flash memory disk, the file system
mllst frnd ~e most recent version. The status byte contan.s bit fje1jis that in~~te whether that particular file
.

'1-;

i

'

~

. .

. •

DIRECTORY ENTRY At-:~~..
'---~
Child Pointer,
DIRECTORY ENTRY B

(Subdlrect~ry cif A)

Slblin
Pointer

DIRECTORY ENTRY C
(Subdirectory of A)

Slblin

STORAGE ON DISK
FNULL
DIRECTORY ENTRY C

~~i~~er

DIRECTORY ENTRY B
DIRECTORY ENTRY A

Data

Sibling
Pointer

Areci
ROOT DiR
Pointer ,",",--~---

292079-57

Figure 39. Directory Arrangement

DIRECTORY ENTRY A

Sibling
Pointer

I

FNULL

Child! Pointe.

FILE 'ENTRY B

,

Sibling
!'olnter

FILE ENTRY C

Chlldl~oint.r 1~e~t ~tl~n Pointer

I',

,

fNULL

',. ••.

Sibling
Pointer

'I Extent Location

1 ' '

FILE B File size. are varloble
DATA,,' '
)lASS

,

FNULL

1

Poi ntar

FILEC
DATA

..........

VACATIONS

STOIWlE

.,NOTE

292079-58

Figure,. 40~ File Arrangement
""
",

4-237

int:eL

Ap·343

Creating a Bootable Drive

Active
Modes

The startup time of the PC can be decreased by booting
froma flash memory disk instead of the magnetic disk.
To do this, a "disk4mage" is installed on the flash
memory disk which is located' in the. system memory
space between COOOOH andEOOOOH (Figure 10). (The
"disk image" contains the Boot Record, Directory, and
FAT.) This memory space is referred· to' as EXPllnsion
ROM. During the system Power-On-Self-Test (POST),
the system searches this memory area for the ROM
adapter signature, 055AAh, marking the beginning of
the disk image. Once this signature is. found, the
BOOTSTRAP process begins. The software to create
and install this "disk image" is available as a product
from Microsoft Corporation as ROM executable MSDOS.
'

WHY' FLASH?
CHARACTERISTICS OF INTEL FLASH
MEMORY
Power consumption, weight, performance, and reliability are the key criteria for a system design. The discussion of Intel flash memory as a mass storage medium
would not be complete without a performance analysis
and comparison to other technologies.

(Based on typical performance characteristics. The
20 Mbyte Flash Memory disk is based on the use of 8028F020s. Only two of the forty devices are acbessed at a
time, the remainder are in standby mode.)

INTEL
Flash Memory
(20 Mbytes)

0.05
(Same as Standby)

Read

3.5-4.0

0.15

Write

3.5-4~0

0.25

1.5

Power Savings

0.05
(Same as Standby)

Standby
Spinup
(from Standby)

0.1-0.5

0.05

9.3

0

For a battery-powered system, 3-4 hours of operation
is unacceptable. Battery longevity is achieved by using,
Intel Flash Memory solid-state storage as a disk replacement. The following table relates battery life and
the different functions ,of disk operation. A "AA" battery with a capacity of 2215 mAH is used for the comparison. Obviously, 'for a truly accurate representation,
other components of the system should be included.
But from the data storage point of view, the flash memory disk will operate many more hours than the hard
disk drive on a set of batteries.
/

Hours of Operation for a "AA" Battery
(Based on Data from Previous Table
and 2215 mAH Battery Capacity)

Portability of a computer demands battery longevity
and consequently minimal power consumption. Small
form factor disk drives are being designed specifically
for the size and power requirements of laptops.

Power Consumption Comparison
(Watts)

1.7-2.0

Ready

Power Consumption

A drive has three basic operating modes: active; power
savings, and standby. The active mode consists of reading, writing, and ready. Ready condition allows "instantaneous" transitions into the read or write states. In
the power-savings mode only the drive motor continues
to run. Standby shuts off all functionality except for the
circuitry needed to "spin-up" the drive. From .the
standby mode, extra' power and considerable time, is
required to "spin-~p" the disk.

Hard Disk Drive
(2.5" • 20 Mbytes)

Read

Hard Disk Drive
(2:5" • 20 Mbytes)

INTEL
Flash Memory
(20 Mbytes)

0.83

22.15

Write

0.83

13.29

Standby

6.64

66.45

Data Access Time
Reading data from a magnetic disk is a very slow process compared to a solid-state disk (SSD). Disk transfer
time is' lengthy due to four time components: spin-up,
seek time, latency. and data transfer time. Spin-up is a
. factor to consider for battery-powered systems, where
most disk accesses are begun from the standby mode.
During the seek time, the arm is repositioned to the
. correct track. Latency is the delay from arm repositioning'until the first sector of the transfer moves under the

4-238

intel"

AP-343

read/write head. This is dependent on the speed of rotation. The actual transfer of data is the third component. The standard SCSI interface transfers data between 5 Mbits and 10 Mbits per second, with which
flash memory compares very favorable.
For this example it is reasonable to assume a transfer
rate of 1.0 Mbytes per second. Using a full word-wide
(xI6) bus bandwidth (120 ns access speed of the device), flash achieves a transfer rate of 16.6 Mbytes per
second.
Read Speed Comparisons
Hard Disk
(Standard
SCSI
Interface)
Seek Time

28ms

Latency

8.3ms

Floppy
Disk

Flash Memory
(16-Blt Bus,
120ns
Access)

0

Transfer Rate 1.0 Mbyte/s 62 Kbyte/s 16.6 Mbyte/s
Total for
10 Kbyte File

46.54ms

261.3 ms

The vagueness of the test procedures makes it difficult
to compare the MTBF for a flash memory solid-state
disk and a hard disk. Based on the fact that disk usage
is 80% reads and 20% writes, a reasonable comparison
can be made. (What is not taken into account is that
disks are an 'infinite' write, but finite read medium.
Continuous reading causes reduced magnetic field
strength, a failure mechanism hidden by re-writing the
disk.)
Intel's Flash Memory typically performs 100,000
erase/program cycles. (Failure does not occur at this
point. The only noticeable change is a gradual increase
in program and erase times.) Assume a flash memory
disk size of 4 Mbytes that functions like a WORM
drive; it is erased and reused after filling.

0
100ms

One method uses the overall mean failure. The MTBF
of all critical components is computer analyzed and the
lowest one is selected. A second method tests 100
drives. The hours of the first ones to fail are multiplied
by the number of drives. How many reads or writes are
performed? Is the disk stopped and started during the
process? Standard answers do not exist.

0.62 ms

(Floppy disk drive specifications combine access into
one category.)
In this example, the flash memory disk has 75 times the
read performance over the hard disk. Smaller files result in even greater differences. Additionally, the 5 second spin-up of the hard disk gives the flash memory
disk over 8,000 times the performance!
A byte will typically program in Intel Flash Memory in
one pulse. (See Intel Flash Memory Data sheet for programming algorithm.) Based on this and the parameters used in the example above, a 10 Kbyte file is written to the flash memory disk in 87.04 ms. Because
writes to a hard disk typically begin from spin-down,
the flash memory disk is still over 50 times faster. Since
reads are 80% of disk access, flash memory's user-perceptible performance advantage is substantial.

Based on a typical disk MTBF of 50,000 hours and the
80/20% division, 10,000 hours are used for writing
files. Assume the average file size written to disk is
10 Kbytes. A 4 Mbyte flash disk can store approximately 400 x 10 Kbyte files (4 Mbyte/IOK = 408)
before erasure is necessary.
These 400 files could be writen to the disk 40 X 106
, times - (400 files X 100,000 cycles =40 X 106). The
result is that within a 10,000 hour period, one 10 Kbyte
file could be written once every 0.9 seconds.
10,000 hburs x 3600 Seconds = 0.9 Seconds
40 x 106 Files
1 Hour
File

It would be more realistic (although still extremely ag-.

gressive) to assume that this 10 Kbyte file is written to
this disk every 10 minutes. At 100,000 cycles, 40 X 106
files will have been written. The MTBF can be calculated as follows:
40 X 106 Files x 10 Minutes x ~ = 6.6 X 106 Hours
File
60 Minutes

Reliability
The definition of hard disk mean-time-before-failure
(MTBF) is extremely ambiguous. There are no industry-wide standards for making a reliable calculation.
Disk drive manufacturers choose whichever method
best suits their product's reliability perception.

This is an MTBF of over 6 million hours! (See Reliability Report RR60 for more details.)
A flash memory solid-state disk outlasts its mechanical
counterpart by at least two orders of magnitude, especially if head parking problems and limited start/stop
cycles of the mechanical disk are taken into account.

4-239

AP-343

Weight

SUMMARY

Lowering the power consumption of your portabie system also lowers the weight. Reduced battery demands
mean smaller and lighter batteries and power suppiles.
Weight savings is also gained by the proper choice of
the mass storage medium. The small 20 Mbyte 2.5"
disk drives weigh between 9 and 21 ounces. The equivalent capacity of flash memory using 80-2.Mbit TSOPs
(which individually weigh 1.16 x 10- 2 ounces) weighs
0.93 ounces plus the weight of the circuit board. (See
section on Intel flash memory packaging.) This difference is critical when the computer weight requiremerit
is under five (5) pounds.

The advent of Intel Flash Memory has led to the evolution of solid-state mass. storage. This application note
has provided the building blocks that ,will allow the
innovative manufacturer to remain on the forefront of
technology.
• Advanced packaging, such as the TSOP, Ie memory cards, and SIMM, is necessary for high-density
applications.
• Intel Flash Memory allows flexible system interfacing by using I/O, paged, or linear addressing methods.
• Software variations enable an unlimited number of
mass storage applications for Intel Flash Memory.
• Intel Flash Memory offers superior performance
over the magnetic disk.

4-240

int:et

AP-343

APPENDIX A

28F020 TSOP Dimensions

tlW

I

z~ ttl

9j

I;l
-B-

S-t-

-

!~

~!

~

~

~

§

I

E

I

D
Ho

, --,
(

I

:dfl!
:\

-- ,

I

~
~

I ro:5ol

~
L

~

:::.j I-- AI

-$-10.07@ I c I A® - B® I
1-$-10.D7@ c A®- B®I
1-$-10.07@ c A®-B®I
-

tW

B

-IBI

DETAIL A

1-$-1°.05 @1c 1A® - B® 1

DETAIL B

Description

\

Min

292079-60

Dimensions In mm
Nom
Max

A

Package Height

A1

Standoff

0.05

A2

Package Body Height

0.96

1.01

1.06

B

Lead Width

0.15

0.20

0.30

1.20

C

Lead Thickness

0.10

0.15

0.20

D

Package Body Length

18.20

18,40

18.60

E

.

tr
~

~IA

' - SEE DETAIL A

Symbol

~
I_SEE
2 DETAIL B

. Package Body Width

7.80

8.00

8.20

HD

Terminal Dimension

19.80

20.00

20.20

0.30

0.33

0.35

L

Lead Tip Length

N

Lead Count

y

Seating Plane Coplanarity

0.00

Z

Lead to Package Offset

0.20

0.25

0.30

0

Lead Tip Angle

1

3

5

32
0.10

28F020 TSOP Physical Dimensions Drawings and Specifications

4-241

int:et

Ap·343

32-Lead TSOP to DIP adapter sockets are available
from the following vendor:

TSOP Sockets and Wands
32-Lead TSOP test sockets are available from the following vendors:
Enplas,'
Part Number: OTS-32-0.5-02
Distributed by:
Tesco International Inc.
1825 S. Giant Street, Suite 745
San Mateo, CA 94402
(415) 572-1683

California Integration Coordinators Inc.,
Part Numbers: CIC-32TS-32D-AG-ENP-GANG-S,
CIC-32TS-32D-AG-ENP-GANG-R
656 Main Street
Placerville, CA 95667
(916) 626-6168
Emulation Technologies,
Part Numbers: AS-32-32-01TS-GENP-GANG-R
(F Version-Reverse),
AS-32-32-01TS-GENP-GANG-S
(E Version-Standard)
2344 Walsh Ave., Bldg. F
Santa Clara, CA 95051
(408) 982-0660
Suction wands for transferring units are available from
the following vendor:
H-Square.Corp.
1289-H Reamwood Avenue
Sunnyvale, CA 94089

4-242

·

AP-343

21

CE3

41

22

CE2

42

3

VSS
Vee
Vpp

7

NC

27

NC

47

8

RES

28

NC

48

9

RES

29

NC

49

10

RES

30

NC

50

11

RES

31

NC

51

12

RES

32

NC

52

All
Al0
Ag
As
A7
A6
A5
A4
Aa
A2
Al
Ao

23

CE1

43

4

OE

24

CEO

44

5
6'

WEH

25

VSS

45

WEL

26

NC

46

13

RES

33

NC

53

RE$

14

RES

34

NC

54

15

RES

35

NC

55

16

RES

36

17

RES

37

A16
A15
A14
Ala
A12

1
2

18

RES

38

19

RES

39

20

RES

40

009
008

63

007

64

006

65

005

66

004

67

003

68

002

69

001

70

000

71
72

Vpp
Vee

73

P01

VSS

74

P02

0015

75

P03

56

0014

76

P04

57

0013

77

P05

58

0012

78

P06

59

0011

79

P07

60

0010

80

VSS

Figure 43. 1 Mbyte SIMM Pinout

4-243

61
62

intel·

Ap·343

I·

4.65"

.

------------1·1

FRONT VIEW

0.33"

&"'D:':'D::'D:':'I~::"""""""~I± ~~5!~~C'm,
II

BACK VIEW

--I I-0.05"

SIDE VIEW
292079-61

Figure 44. 1 Mbyte SIMM Dimensions
Module Speed Identification .

Module Capacity Idenfltlcatlon
Module Capacity
Word Depth

PD6

PD2

PD1

Maximum
Access Time

PD7

PDS

PD4

PD3

No Module

0

0

0

>300 ns

5

5

5

5

256K/32M

0

0

5

300 ns

5

5

5

0

512K/64M

0

5

5

5

0

5

0

5

0
.5

250ns

1M/128M

200ns

5

0

0

2M/256M

5

0

0

185 ns

5
5

0

5

5

4M/512M

5

0

5

150 ns

5

0

5

0

135 ns

S

0

0

5

120 ns

5

0

0

0

100 ns

0

5

5

5

85ns

0

5

5

0

70 ns

0

5

0

5

60 ns

0

5

0

0

50 ns

0

0

5

5

40ns

0

0

5

0

30 ns

0

0

0

S

NO

0

0

0

0

8M11G

5

S

0

16M/2G

5

S

S

NOTE:
These PD pins are JEDEC defined, not future product commitments.

o=

Open Circuit On Module
S = Short Circuit to Ground on Module
ND = Not Defined

4-244

inteL

AP-343

EPLD ADF for Presence Detect WAIT-State Generator
PLFG Applications
1-800-323-EPLD
Intel Corp.
June 6, 1990
U999
002
85C220
Pre-loadable wait state down counter/READY generator
OPTIONS: TURBO
ON

=

PART: 85C220
INPUTS: CLK@l, nLOAD@2, PD7@3, PD6@4, PD5@5, PD4@6
OUTPUTS: nREADY@19, Q3@18, Q2@17, Ql@16, QO@15, nDL@14
NETWORK:
CLK: INP(CLK)
% System clock input %
nLOAD
INP(nLOAD)
% Load count input %
PD7
INP (PD7)
% PD[7 :4] Wait state %
PD6
INP(PD6)
% count size inputs %
PD5
INP(PD5)
% to lookup table %
PD4
INP(PD4)
nREADY, nREADY
RORF(nREADYd,CLK,GND,GND,VCC) % /READY Output %

=
=
=
=
=

=

=
=
=
=

Q3,Q3
RORF (Q3d,CLK,GND,GND,VCC)
Q2,Q2
RORF (Q2d,CLK,GND,GND,VCC)
Ql,Ql
RORF (Qld,CLK,GND,GND,VCC)
QO ,-QO = RORF (QOd, CLK, GND, GND, VCC)
nDL,nDL
RORF (nDLd,CLK,GND,GND,VCC)
EQUATIONS:
QOd
QOEQN * !READY * !COUNT_ZERO
+ QO • (READY + !LOAD)
+ XO • LOAD • !READY • COUNT_ZERO;
QOEQN = !QO;

=

Qld

% counter outputs •• • %
% not externally %
% necessary %

% count if not ready %
% hold if ready %
% read inputs on LOAD %

=

Q1EQN • !READY • !COUNT_ZERO
+ Ql • (READY + !LOAD)
+ Xl • LOAD • !READY • COUNT_ZERO;
Q1EQN
Ql • QO + !Ql • !QO;

=

Q2d

=

Q2EQN • !READY • !COUNT_ZERO
+ Q2 • (READY + !LOAD)
+ X2 • LOAD,' !READY' COUNT_ZERO;
Q2EQN
Q2 • (Ql + QO) + !Q2' !Ql' !QO;

=

Q3d

=

Q3EQN • !READY • !COUNT_ZERO
+ Q3 • (READY + !LOAD)
+ X3 • LOAD • !READY • COUNT_ZERO;
Q3EQN
Q3 • (Q2 + Ql + QO) + !Q3 • !Q2' !Ql • !QO

nREADYd'
nDLd

=
= !Q3

• !Q2 • !Ql • LOAD • !nDL;

= nLOAD;

% Anticipate
% to provide
% hold until
% taken away

EPLD ADF for Presence Detect WAIT-State Generator

4-245

counter %
READY%
LOAD is%
%

intet

AP-343

=

COUNT_ZERO
!Q.3 • .!Q.2 •
LOAD
NLOAD' ;
READY
nREADY' ;

=

!Q.l •

!Q.O;

=

X3
X2
Xl
XO

=
=
=
=

BCNT
7CNT
6CNT
5CNT
4CNT
3CNT
2CNT

GND;
3CNT;
BCNT + 7CNT
5CNT;

=
=
=
=
=
=
=

PD7
!PD7
!PD7
!PD7
!PD7
!PD7
!PD7

•
•
•
•
•
•
•

% Wait State Scrambler %
.% lookup table %
+

!PD6
PD6
PD6
PD6
PD6
!PD6
!PD6

6CNT

•
•
•
•
•
•
•

+

!PD5
PD5
PD5
!PD5
!PD5
PD5
PD5

5CNT;

•
•
•
•
•
•
•

!PD4;
PD4;
!PD4;
PD4;
!PD4;
PD4;
!PD4;

END$

EPLD ADF for Presence Detect WAIT-State Generator (Continued)
Decoding Truth Table for "Multiplexing" Data Bus of PCMCIA/JEIDA Memory Card
System Bus Width

Data Transfer

CSH

CSL

Ao

1

2

3

B or 16

None

1

1

x

1

1

1

-'

8 or 16

Lo-Byte

1

0

0

0

1

1

8

Hi-Byte to Lo-Byte

1

0

1

1

0

1

16

Hi-Byte

0

1

1

0

Low and High Byte

0

0

x
x

1

16

0

1

0

NOTE:

References Figure 8 in Memory'Card Section.

4-246

AP·343

PAGE MEMORY BOARD
SCHEMATICS

,/

4·247

.

_.

II

~

tti~g~ A

I/O CH CKI

I . , :~ET
~ IROg

5DS A.c.

::::::ti-SV
B ORQ2

SI).i.A
S03 A6

-H

-f2V

~ ~~V
8f 1 ~:~l.tW#

L=:IH
~

B~4

1/0 CH

5A19 A12

SA19

lOW,
IORI

SA18 Al
SA17 :::

SAI7

816 DACK3,

SAI6

~ OR03

B~3

CLK

SAl. AI
SAI3 A18
SA12 A19

SAl1

IRQ7

SAtD

IRQ6

AlD

1

SAg :2

=m:g:
::m
~

A16

SA1S

DACKt#
1
DROt
~ REfRESH,
21

~~ A~O
R~~ ~

SI.fEt.lR#

::IU

i

A~

S02

507
50.
5
5
5
SD2
501

~~A4

~ IR03
DACK21
B28 TIC
~ BAlE

5.4.5
SA4
SAl

~ GNI}.~~~

~ ~,
SAO

SAS

.4.2

7
8

~

50(0 .• 1.)
50(0.• 15)
SA(O•• I.)

S 0 .. 19 -

SSHE,
IORI
lOW,

'EN
M£WCStS,

Al8

RESET
OND

SAl
SAl
SA"
SAl

OWS
.,Y

SA12

...--- I> 5UE.R,

SAIl
SAID

5.'
5 ••
5.7
6

l

SOCKETS

I/O lk MOl DECODE

JAfBl
GND

r--

SMrwWI

LD(0•• 15)
LA(0 .• 1')
p(0•.7)
1CE(0••7)
#WRL(0••3)
,WRH(O. .3)

Lo(O •• I.)
LA(O.• I')
P(0.•7)
ICE(0..7)

'Ro(O••3)
Po(O•. 6)
T(0••7)

'Ro(O..3)
Po(O.•6)
T(0 ••7)

1WRl(0•.3)
#WRH(O..3)

Ypp
-- RESET,
KA(O .. IS)

Ypp
RESET,
KA(O •• IS)
.5Y

r--

jlOND

jl16srr,

I

••

SAl
S

1
5'0

:.

l'

/

~

CONNECTOR PC-XT-IO

~

CD

w

~
01

JC/Dl
MEWCS'S,

~ I/oesl.,
~ IROtO
~ IRQl1
(ROI2

--R!

:::I ::~!~

~ CACKD,

~ g~51
o

DRQS
DACK7,
ORa7
06 +SY

$.

iii

LA23
LA22
LA21
LA20
LAl'
LAI.
LA17
MDIRI
MEWI
SDB

IORQS
1 [)ACK6,

r

SBHE Cl

~R#

I

SDR C12
SOlO 1
SOU C14
S012 1
SOU 1

~g~;

g!

SnR
0
5 11
S 1
13
014
1

CONNECTOR PC-AT-to

?BYPASS CAP'S

L .5Y
--FOND

I.

292079-16

l

Vee

~

•

~

51.. 101-1-2

GND

I 1(0••7
I R~ET#
I

LA(0;.19

<

LDlO .. 15

RESET#

GNDI

o

A(0 •• 14)

,

0(0 .. 15)
#RD(0 ..3)

I l¥CElO..7

#CE(0 ..7)

l#wRH 0 ..3

i

+5VI

I ;IIRDlO..3

I #wKL 0 .. 3

ee

T(0 ••7)

#WEL(0 •• 3)

-

#WEH(0 •• 3)

"

[ Vpp

Vpp

<

PD(0..6)

P 0 ..1»)

:J>

1»
Co)

P(0 ••7)

I PO..

Ao

Co)

51...._3_4

T(0..7)
RE5ET#

KA 0 .. 15

A(0 .. 14)
0(0 .. 15)
#RD(0 .. 3)
#CE(O ••7)
#WEL(0 .. 3)
#WEH(0 .. 3)
Vpp

+5VI

PD(0 ..6)

GNDI

P(0 ••7)
292079-15

AP-343

UI7
SAO
IAI
SAI,.--4 IA2
IA3
,-~*
IA4
SA4
II
SA5
13 2AI
SA6
15 2A2
SA7
17 2A3
2A4
-

:u

~

:

'"

gt

LA(0 .. 19)
IYI
IY2
IY3
IY4
2YI
2Y2
2Y3
2Y4

18

LAO
LAI .......
ITi""LA2
12
LA3
9
LA4
7
LA5
5
LA6
.L LA7""",

m

UI9
SAO
'--SAl
'-SA2
'--SA3
, - SA4
SA5
SA6
SA7

IG
2G

19

GNO

r

74F244

I

UI8
2
4 IAI
6 IA2
IA3
8
IA4
2AI
15 2A2
17 2A3
2A4

SA8
SA9
SAIO
SAIl

~::~-;I~

UI68
74F125
[ SMEMI!L...r

SA 4
SAI5

1l

f

IYI
IY2
IY3
IY4
2YI
2Y2
2Y3
2Y4

18
16
14
12
9
7
5
3

GNO

LAS'
LA9
LAIO
LAII
LAI2
LAI3
LAI4
LAI5

lAl
IA2
IA3
IA4
2AI
2A2
2A3
2A4

IYI
IY2
IY3
IY4
2YI
2Y2
2Y3
2Y4

~~
14
12
9
7
5
3

KAO
KAI

~

,

....

~

....IiA5

KA6

...2L

IG
2G
74F244
U20

SA8
SA9
,-SAIO
"-SAIl
, - SAll.
SAI3
SAIo4
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2G

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GN:

2
4
6
8
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13
15
17

2
4
6
8
I
13
15
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IA2
1A3
1M
2AI
2A2
2A3
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IYI
IY2
IY3
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2YI
2Y2
2Y3
2Yo4

18
KA8
16 ...J::!!.9
KAIO......
12
KAII
9
KAI2
7 ...J::!!.13
5
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KAI§.....,

I"f4

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2G
fI

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---

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.......

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UI28

704F08

I

1
3...(
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r.-::, 17
+I
2.AI 81 18

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SOl
S02
S03

2
GNO

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6
7
8
9

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I DlR

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Vet:.

um-J

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-

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4 A3 83 IS
5 A4 84 14
6 AS BS 13
B A6 86 12
9 A7 B7 II
AB BB
19
G

LOB .....
81
82 16' ffi'o~~
4A383~
~ Ao4 B4 14 LLOl21
6 AS B5 13
3
7 A6 B6 12 121
LOlo4
8 A7 B7 II
AB

LO~

BB

glR

'"74rn5'

LD(O •• IS)

'--

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L09
LOIO
LOll

r.-::, ~

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3 A2

r-'+

r

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UII

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<:SD(O •• !.:!.

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S06
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LOI
82 16
L02
83 IS
L03
B4 14 L04
85 13
LOS
B6 12
L06
87 II
L07
BS

LOW S/16 BIT
HIGH B BIT
16 BIT

tg:~"",
LOIo4......
LOl.:o

•

r

Vet:.
9
RIH
10k

4-250

..
t-

-

I-

intel .

Ap·343

Vee

MEM DECODE

a:

SIN"

L.

OC[(0 •• 7)
LA(0 •• 19)

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AEN

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SHE#

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..!J.!!,

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P(0 •• 7)
W(D •• 3)

-

OWS
BRDRST#

1691T'"
SNEt.tW#
SNEMR#

;--

• WEMDECOD[1Il

GNDI~
GND

L

I/o DECODE ..~

~ +SV

Vpp

SA(0 .• 19)

.~
.[SET

IOR#

P(0 ••7)

IOW#

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AEN

8RDRST#

RESET

PD(0 •• 6)

IOD(0 •• 15)

10. .
10.W'

16BIT#

RESEn"
10DECODEO

~~GND

~

I--

In

-

GND

U13A

KAO

LOW 8/16 BIT

3

IOOECODE#
W,2

--cr-rr?:
U12A

MENDECOD[#

74F08

2

~

HIGH 8 BIT
12

~'
U138
........

16 BIT
6

~

16 BIT#!!

292079-2

4-251

intet

Ap·343

1000 ..7
00

.. 7
10DD
1001
1002
10 3
1004
100S
1006
1007
100
Vee

4
S
•6
7
B
9

A2
A3
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03
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lB
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16
IS
14
13
12
11

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1

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1000
1001
1002
1003
1004
100S
1006
1007

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74f12S

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.............

~
~ AI 01

2

101

3

BIOR#

2
3
4
S
6
7
B
9
19

~
AI Bl
A2 02
A3 B3
A4 B4
ASBS
A6 B6
A7 B7
ABBB

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lB
17
16
IS
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13
12
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J

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1

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g'R

GNo
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74f12S

'"i""""'""
...............

S

6

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13

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SA 0 .. 19

U31
SAO
SAl
SA2

1
2
3

A
B
C

, Vee

~
~

Gl
G2A
G2B

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Yl
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Y3
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YS
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Y7

IS

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13
12

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11
10
9
7

I

I

PoETECT
PAGE.EN

74f13B
CO

PS2
U30
2
4
'-6
'-B
11
'---;3
IS

'--lZ.

74F32

r.:::mc>

~

SA3
SA4
SA
SA6
SA
SAB
SA9
SA10

3

..§.
7
9
12
14
16
18

PO
PI
P2
P3
P4
PS
P6
P7

p=o

00
01
02
03
04
05
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07
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d

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JUMPER

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GNo

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SWBS
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j! SWBI

I! SWB2
~SWB3

j!

1'1

f;.J

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.
292079-3

4-252

AP·343

SW 01P-8

U36

1000
2
1001
3
1002
4
1003
5
1004
6
1005
7
100
8
1007
9
102
19

7,""7,
A2
A3
A4
AS
A6
A7
A8

B2
B3
B4
B5
B6
B7
B8

SWBI
SWB2
SWB3
SWB4
SWB5
SWB6
SWB7
SWB8

+5VI
GHO I

1000
1001
1002
1003
1004
1005
1006
1007

~

r:h.

~'R
£:'77F245
1

1000
2
I 01
1002
5
1003
6
1004
7
1005
8
10
1007
9
103
19

!

1

18
15
14
13
12
11

+5VI
GilD I

10DO
1001
1002
1003
1004
1005
1006
1007

~

110

~'R

...
I

r;;-;;-

PSO
PSI
PS2
PS3
PS4
PS5
PS6
PS7

WIHDOW ADDRESS

rr
tt-

Bl 18
B2 17

~

B3 '~
B4 14
B5 13
B6 12

A3
6 A4
7 AS
8 A6

9
19

:~ :~

'-

L

VOLTAGE GEHERATOR

~ lORN

RESET,

10WN

Vpp

100(0••7)

+5V I

3

Pi)

11

PSO
PSI
PS2
PS3
PS4
PS5
PS6
PS7

~'R

2 74r32

WO
WI
W
W3

(READ PAGE #)

~

2 Al
3 A2

ro7ill45

I

~

l2
18
3 A2 B2 17
4 A3.B3 16
~ A4 B4: 5
7 ASBS
8 A6B6
9

13 ~
14 06
17 07
18 DB
11
CLK
1
CLR

1

BIORII
BlOW'
P EH

1000
101
102
1003
1004
105
1006
10

2
01 5
02 6
03 9
g~ 1
06 15
07 16
08 19

01
02
8 03

U38
Vee

SWBI
SWB2
SWB3
SWB4
SWB5
SWB6
SWB7
SWB8

'~

B2
B3
B4
B5
B6

:~ :~

U32

~

~

£:'77F245

--

!7

SW 01P-8

~
Al Bl
A2
A3
A4
AS
A6

(WRITE PAGE #)

U37
Vee

18
17
16
15
14
13
12
11

VppEH#
RESET

BRORST#
GHO I

6

RESET

~VCC

11.

:e;J
BRDRST'i

GNO

5 74r32

W(0 ••7)

:~ :~:if:

W 0 ••7

~G

r

GHO

OIR

'74rn5
PO(0 ••6)
PO 0 •• 6

PS7

JPl

P7

~

.~W~
PSS
JP2

PS6

JP3

P6

~W~:J
PS4

. JPt

/

~

A2
A3
A4
AS
A6

B2
B3
B4
B5
B6

17
16
15
14
:3

~ :~

11

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ro'77F245

.

JP7

2~18
3
4
5
6

9
P DETECT 19

POO
POI
P02
P03
P04
P05
P06

~

1

~MPER
PS4

U39

10DO
1001
1002
1003
1004
1005
1006
1007

~WPER

PRESEHCE
DETECT

P(0 ••7) ,
P 0 •• 7

P4

~W~:J
PS2

JP8

JUWPER

292079-4

4-253

AP-a43

P(O ..71
sUEURI

>

•• 1

LAO
704r32

U21
PO P=O
PI
P2 .
P3
P4
PS
P6
P7

19

U1SB
11

74r32
U23A
1
2

00
01
02
03
04
OS
06
07
R

74r32

G
704rS21

704r32

II

8

Vee
1
6

1
S
R2A
10k

1
4
R2B
10k

2

1
3
R2C
10k

3

8
R2D
10k

4

WO
WI
W2
W3

SW DlP-4

GND

T2

Vee

~
~

GND

8

T3

292079-9

4-254

intel~

AP-343

P(O .. 7)
A
B
C
Gl
G2A
G2B

YO
Yl
Y2
Y3
Y4
Y5
Y6

Y7

74f138

JP10

11

JUMPER

11

T6

T7

292079-10

4-255

int'el..

AP·343

I KA(0 .. 14)
I-

00Q(0 •• 15)

08
09
010
011
012
013
014
015
T5

,.!!!.AI Bl 18
A2
A3
A4
AS
A6
A7
A8

B2
B3
94
B5
B6
B7
B8

17
16
15
14
13
12
11

c
cO
0
0
c
0
c
c

8
9
10
11
12
13
14
15

DO
01
02
03
04
05
06
07

gill

I

2
3
4
5
6

~
AI Bl

A2 82
A3 B3
A4 B4
AS B5
7 A6 B6
8 A7 B7
9 ASB8
19
1

r"74rn5

T4
0 •• 15

2
3
4
5
6
7
8
9
19
1

18
17
16
15
14
13
12
"

cO
0
cO
cO
0
.c
cO
00

0
1
2
3
4
5
6
7

d
d
dO
d
d
d
d
d

0
1
2
3

g'R

r"74rn5
#RD2

I

.OJ
dDO(0 •• 15)

08

T7
T6

D9

~

010
011
012
013
01.
015

4
5
6
7
8
9

.!!!.AI
A2
A3
A4
AS
A6
A7
AS

Bl
B2
B3
B4
B5
86
B7
BS

19

Ir

1

g'R

7Tr24s"

18
17
16
15
I.
13
12
11

dO
d
d
d
d
d
d
dO

8
9
10
11
12
13
I.
15

00
01
02
03
O.
05
06
07

2
3
4
5
6
7
S
9

~

~
AI Bl
A2 B2
A3 B3
A4 B4
AS B5
A6 B6
A7 B7
ASBS

18
17
16
15
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13
12
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•
5
6
7

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OIR

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Vee

~~======~T================

IIIWEHCO ..3)
I IIWELCO •• 3)

~~--------------------------------------------------------------



i

'P

....

Co)

Co)

1IASIER BOARD

OO~-'r-----------------------~~-----------------------1

... 11

o
JUMPER
O=OFF
1 =ON

IODI

SlAVE BOARD

v:

JP12

o C
JUMPER

JP1.

U292079-11

infel .

AP-343

C17

0.1 ).IF
CIS

O.I).1F.
C35

0.1 ).IF

C36

0.1 ).IF
C47

0.1 ).IF

292079-13

VCC

1
5

RB

RO

10k

10k

~

GNO

GNO

292079-14

4-261

infel·

Ap·343

Range

'Ueage

1/0 Port Usage for peAT
Range

USage

OOOO-OOOfh

DMA Controller 1, 82S7A

OS90-0S9Sh

Cluster (Adapter 0)

0020-0021h

Interrupt Controller 1, 8259A

OSaO-OSa9h

asc Communications (Primary)

OSbO-OSbfh

Monochrome/Parallel Printer
Adapter

OScO-OScfh

EGA (Primary)

0040-005fh

Programmable Timer, 8254

OO~-OO6fh

Keyboard Controller, 8042

0070-007fh

CMOS Real~Time Clock, NMI
Mask

OSdO-OSdfh

CGA

0080-009fh

DMA Page RegisterS, 74LS612

OSfO-OSf7h

Floppy Disk Controller

Interrupt Controller 2, 8259A

OSf8-0Sffh

Serial Communications (COM 1)

06e2-06eSh

Data Acquisition (Adapter 1)

00aO-OOa1h
OOcO-OOdfh

. DMA Controller 2, 82S7 A

OOfO-OOffh

Math Coprocessor

0790-079Sh

CluSter (Adapter 1)

01fO-01f8h

Fixed Disk

Oae2-0aeSh

Data Acquisition (Adapter 2)

0200-02Ofh

.Game ControHer.

Ob90-0b9Sh

Cluster (Adapter 2)

0278-027fh

Parallel Printer Port 2

Oee2-0eeSh

Data Acquisition (Adapter S)

02bO-027dfh

EGA (Alternate)

1S90-1S9Sh Cluster (Adapter S)

02e1h

GPIB (Adapter 0)

2S90-2S9Sh

Cluster (Adapter 4)

02e2-02eSh

Data Acquisition (Adapter 0)

42e1h

GPIB (Adapter 2)

02f8-02ffh

Serial Communications (COM2)

62e1h

GPIB (Adapter 3)

OSOO-OS1fh

Prototype Card

82e1h

GPIB (Adapter 4)

OS60-0S6fh

f'C Network

a2e1h

GPIB (Adapter.5)

OS78-0S7fh

Parallel Printer Port 1

c2e1h

. GPIB (Adapter 6)

OS80-0S8ch

SOLC Communications

e2e1h

GPIB (Adapter 7)

4·262

intel .

AP-343

ASSEMBLY LANGUAGE CODE FOR PAGED BOARD

:***************************************************************************
:Locating the Base I/O Address.
:BOARD_NOT_FOUND is an error procedure and is not shown.
BRD_IDO
Window_Base
Presence_Detect
VPPEN

Page_Number

dw
dw
dw
dw
dw

mov dX,02F8h
KEEP_LOOKING:
add dX,8
cmp dX,318
jg board_not_found
in al,dx
.cmp al,ODh
jne KEEP_LOOKING
inc dx
in al,dx
cmp al,OAh
jne KEEP_LOOKING
inc dx
in al,dx
cmp al,Olh
jne KEEP_LOOKING
inc dx
in al,dx
cmp al,OEh
jne KEEP_LOOKING
:FOUND-Good Job!
sub dX,3
mov BRD_IDO,dx

4 dup (?)
?
?
?
?
:Set port pointer to 02F8H.
:First valid address after adding.
:Port pointer
.8 less than highest port address?
:Hey, you forgot to install the board!!!

=

:Read port data into al register.
:Does register
1st identifier value?
:Not, equal ~ Not located yet .

=

:Does register

= 2nd

identifier value?

;Does register

= 3rd

identifier value?

=

:Does register
last identifier value?
:TOO BAD, you almost had it!
:Restored to base address.
:Save the value in RAM.
Locating the Base I/O Address

NOTE:
A review of 8086 asembly language programming fundamentals might be necessary at this point.

4-263

intet.

Ap·343 .

;Locating th'e Base Memory Address

;***************************************************************************
;This Information is loaded into a segment register to access data

,
.***************************************************************************
mov ax,O
mov dx,Window_Base
in al,dx
mov bx,256
mul ax
mov es,ax

;Clear register
;Port pointer = I/O to read base memory address
;Read port
;Shifts address information left.
;es used as segment register for board.

4-264

int'et

Ap·343

;***************************************************************************
;Determining Memory Capacity

.

Density_Lookup_Table dw ?,?,Offfh,7ffh,03ffh
DENSITY dw ?
mov ax,O
mov dX,Page_Number
mov al,O
out dX,al
mov dX,Presence_Detect
in al,dx
and al,23H
cmp al,20H
jng skip_or
or al,4

;Clears register.
;Port pointer accesses page number.
;Write a zero to page number hardware.
;Port pointer accesses presence detect pins.
;Clears all but density information.
;Checks if PD6 is set.
;If greater than 20H, set bit 2 of al.

;Go to density lookup table, translate value from PD pins, store in RAM
;variable DENSITY. Density value must be 2, 3, or 4 to be valid.
skip_or:
cmp al,4
je okay'
cmp al,3
je okay
cmp al,2'
je okay
jmp Unknown_Device
;Invalid or no SIMMs present, routine not shown.
;Base address of density lookup table stored in bx register.
mov bX,offset Density_Lookup_Table
mov si, ax
;si register will be p·ointer into density table
;Density values for IM-4M, multiples of 1 Kbytes, stored in lookup table.
movax,[bx+si]
;Density read into ax register
mov DENSITY,ax
;Read the device identifier. Use the es segment register for the base
;address of the memory.
;28FOIO
OB4h,28F020
OBDh
mov aX,DENSITY
;Put RAM held density info into ax.
mov bX,l
moves: [bx] ,90H
;Write ID command.
;Read device identifier.
mov bX,es: [bx]
cmp bX,OB4h
je IMEG

=

=

Determining Memory Capacity
)

4-265

infelSj

AP·343.

cmp bx,OBDh
je 2MEG
jmp Unknown_device

;If other than 28F010 or· 28F020.

;Divide SIMM density by component density to determine number of components
ion SIMM.
!MEG:
mov bx,3FFh
div ax
jmp NEXT_OPERATION

;Divide ax/bx, # of components stored in al.

2MEG:
mov bx,7FFh
div ax
jmp NEXT_OPERATION
;Read from the·next SIMM location to verify its presence.
;As an example, assume that the SIMM's density· is 1 Mbyte.
;A 1 Mbyte SIMM has 16 pages.
mov dx,Page_Number
mov al,16
;Swi tch to Page 16 for next SIMM lo·cation.
out dX,al
m!lv bx,l
;Write ID·Command to first device of next SIMM.
mov ex: [bxJ ,90R
mov ax,esHbx]
;Read the identifier. Invali.ddata = empty socket
;Repeat the process for all SIMMs.

;*************************************************.**************************
Determining Memory Capacity (Continued)

4-266

APPLICATION
NOTE

AP-361

October 1992

Implementing the
Integrated Registers
of the .
Series 2 Flash Memory Card

MARKUS LEVY
SENIOR TECHNICAL APPLICATIONS ENGINEER

Order Number: 292096-002
4-267

Implementing the Integrated Registers of the
Series 2 Flash Memory Card
CONTENTS

PAGE

INTRODUCTION ....................... 4-269
SERIES 2 COMPONENT
MANAGEMENT REGISTERS ........ 4,270

PCMCIA Release 2.0 Defined .......... 4-270
Soft Reset Register .................... 4-270
Global Powerdown Register ............ 4-272
Performance EnhancementRegisters .. 4-273
Sleep Control Register ................. 4-273

CONTENTS

PAGE
Ready-Busy Status Register ..... : ...... 4-274
Ready-Busy Mask Register ............. 4-276
Ready-Busy Mode Register ...... , ...... 4-277
Write Protection Register ............... 4-280
Card Status Register ................... 4-281
SUMMARY ................' ............ 4-282
GLOSSARY ........................... 4-283
RELATED DOCUMENTS .............. 4-283

4-268

infel .
ASICs link the flash memory devices with the
PCMCIA-specified electrical interface. These ASICs
handle buffering, decoding and all control signals. They
also contain the CMRs and hardwired Card Information Structure (CIS) used by system software to enhance device-level functions.

INTRODUCTION
Intel's first generation flash memory cards(1) forever
changed the vision of solid-state storage. Electrically
rewritable, non-volatile, reliable, yet economical in high
densities, these cards provided a unique solution for the
portable computing industry demanding such media.
The second generation of flash memory- cards provide
even higher densities, lower power consumption and a
higher level of functionality. The Series 2 Flash Memory Card delivers a major technology breakthrough by
supporting densities up to 20 MBytes(2), an integrated
memory control register set (Component Management
Registers orcMRs) and PCMCIA 2.0/ExCATM com~
pliance.

The OEM has many hardware and software alternatives for using the Series 2 Card. From a hardware perspective, the Intel 82365SL offers the most practical
solution for controlling the PCMCIA socket in a PC
solid-state drive application. This component, called
the PC Card Interface Controller, provides the ExCA
compliant hardware interface between the host system
and the Series 2 Cards (and all other ExCA-compliant
cards). As shown in Figure 1, the fundamental glue
logic consists of a Vpp generator and Vee control, a
latching transceiver and address and decode signal buffers. Embedded systems not requiring an ExCA-compliant socket, can provide proper card signals with discrete circuitry.

Intel's 8-Megabit FlashFile™ Memory, 28FOO8SA,
provides the foundation for the Series 2 Flash Memory
Card. Its properties include data-write and block-erase
automation, sixteen 64 KByte, separately-erasable
blocks, a Ready/busy output pin, and a Powerdown
mode. Within the Series 2 Card, high-functionality

Interfacing the Series 2 Card to the 82365SL

-X

SO(15:8)

J. so (7:0)

SO(15:0)

co (15:8)

,-;. C

CD (7:0)

V
R G\~

J..

~.

.....--

-.

OIR

S

EXT OIR

L
0

-B

SA (11:0)

T

U

..J

0

'"

1-«
%10«

82365SL

c.>c

so (7:0)

.....
ENABLE

F
F

A
f---

,-

r

CAROCTRL/STAT /INTR

SA (16:0)
LA (23:17)

CONTROL
CAOOR (25: 12)

ISACTRL
IRQ

PWRCTRL

Vpp GENERATOR

PWR

'1

SYSCTRL

Vee

PORT

292096-1

·This solution requires minimal glue logic.

Figure 1. The 82365SL Establishes ExCATM Compatibility with Minimal Glue Logic
NOTES:
1. The Bulk-Erase iMC001 FLKA, iMC002FLKA, and iMC004FLKA (One, Two and Four Megabytes, respectively).
2. Higher density cards may be realized in the future as component densities go beyond 8 Megabits.

4-269

intet

AP-361

Series 2. Flash Memory Card

I
I

REG\

ASICS
ATTRIBUTE MEMORY PLANE

-J>o--

- - - - - - - - - - - - - -

HARDWIRED CARD
INFORMATION
STRUCTURE

COMPONENT
MANAGEMENT
REGISTERS

FLASH DEVICES
I

- - - PLANE
-- - ---- - - MEMORY
- - - - -COMMON
28FOO8SA

28FOO8SA

28FOO8SA

28FOO8SA

28FOO8SA

~

I"""SrATUS"
REGISTER

r-sTA-TUS"
REGISTER

tsrATUS"
REGISTER

r--sTATUS"
REGISTER

tsrATUs"
REGISTER

28FOO8SA

28FOO8SA

28FOO8SA

28FOO8SA

28FOO8SA

::!iiI-'

r-sTA-TUS
REGISTER

STATUS
REGISTER

r--sTATus
REGISTER

STATUS"
REGISTER

r--sTATUS"
REGISTER

~I...I

"U
~i~
~~

,

292096-2

Operation Status Available at ASIC and Component Levels

Figure 2. Selecting the Attribute or Common Memory Planes

Computer systems using the Series 2 Card as a solidstate disk drive employ file management software, such
as Microsoft's' Flash File System with ExCA software.
_This software capitalizes on the architectural benefits of
flash memory. It includes drivers that interface directly
to the Series 2 Card. Beyond specifying the hardware
architecture, ExCA provides a software solution that
consists of modular software pieces designed for easy
adaptation to the various hardware platforms and
memory technologies. The various pieces of the ExCA
system may be obtained from your BIOS vendor. Essentially, this means that a system OEM is relieved of
having to implement the integrated registers of the Series 2 Flash Memory Card.
This application note supplements the information contained in the Series 2 Flash Memory Card Data Sheet.
It benefits OEMs developing their own Series 2 Flash·
Memory Card software pieces, including custom flash
file management software and software for embedded
systems running non-DOS applications. Specifically, it
describes the software aspects of implementing. the
card's CMRs which provide software control of many
28FOO8SA functions, elevating the system designer
above device-level issues used by higher-level file system software.

SERIES 2 COMPONENT
MANAGEMENT REGISTERS
The CMRs optimize the Series 2 Flash Memory Card's
performance by supplying a software-controlled interface to the individual devices within the card. As shown
in Figure 2, they are accessed as memory-mapped 1/0
in the Attribute Memory. Plane by pulling the card's
Register Select pin low (REG, pin 61)(3). CMRs can be
divided into two basic categories; those defined by the
PCMCIA Release 2.0 specification and Intel defined
"Performance Enhancement Registers".

PCMCIA RELEASE 2.0 DEFINED

Soft Reset Register
(Configuration Option Register)

During card operation, it may be necessary to place the
cardjnto a known state by resetting the 28FOO8SA-level Status Registers and the CMRs in the ASICs to their
power-on conditions (Figure 3). Specifically, in the
NOTE:
3. No switch-over setup-time from Common Memory

is needed when PCMCIA timing requirements are
met.

4-270

intet

AP·361

Component Managment Registers(4)
Defined by the PCMCIA R2.0 specification
• Soft Reset Register (S)-(RIW)
• Global Powerdown Register (6)-(RIW)
PERFORMANCE ENHANCEMENT REGISTERS designed to deliver control benefits tied
directly to the Intel 28FOO8SA:
•
•
•
•
•
•

Sleep Control Registers-(RfW)
Ready-Busy Status Registers-(RO)
Ready-Busy Mode Registers-(RIW)
Ready-Busy Mask Registers-(RfW)
Write Protection Registers-(RIW)
Card Status Register-(RO)

ASICs, this reset affects the PwrDwn bit (Global Powerdown Register), the Sleep Control Register, the
Ready-Busy Mode Register, the Ready-Busy Mask
Register, and the CISWP and CMWP bits (Write Protection Register). There are several ways to enter power-on status:
1. Issuing a hardware reset, with a complete system reset or socket reset through the interface hardware,
affects the entire system Or the Series 2 Card, respectively.
2. During normal operation of many portable systems,
such as those employing the 386SLTM microprocessor, tremendous power savings are realized by entering a suspend state. In this state, power to the card's
socket is removed. After reapplying power, the card
automatically attains its power-on status. Therefore,
before removing power from the Series 2 Card, system software must save the contents of the Component Management Registers. It should also be pointed out, that a startup period must elapse to allow all
internal circuitry to stabilize before accessing the
card. This time period depends on host system power
supply capabilities. (7)

3. The third method utilizes a software-controlled
mechanism built into the Series 2 Card. This option,
activated with the Soft Reset Register, provides a
simple approach for placing the card in its power-on
state without time delay.
The Soft Reset Register (Figure 4) contains a soft reset
(SRESET) bit that performs a function similar to the
hardware reset invoked by the card's RESET pin (RST,
pin 58)(8). Achieve the reset condition by issuing a twostep write sequence to the SRESET bit (i.e. toggling
from 0 to 1 and back to 0).
During reset (SRESET = 1), the ASICs drive the flash
memory array into the deep-sleep mode. This aborts
any device operations in progress and resets each device's Status Register. After initiating a soft reset, the
SRESET bit must be cleared (zero) to enable access to
the flash memory array or write to another CMR. The
host system can clear this bit by writing in a zero or
issuing a hardware reset.

Power-On Conditions'

ALL DEVICES IN STANDBY MODE.
SOFTWARE WRITE-PROTECT DISABLED.
ALL DEVICES' READY/BUSY OUTPUTS UNMASKED.
PCMCIA-READY/BUSY MODE ENABLED.
READY/BUSY OUTPUT PIN GOES TO READY.
NOTE:

Generated by Hardware Reset or Toggling SRESET Bit.
Figure 3
NOTES:
4. R ~ READ, W = WRITE, RO = READ ONLY
5. Referred to as Configuration Option Register by PCMCIA R2.0.
6. Referred to as Configuration and Status Register by PCMCIA R2.0.
7. As specified by PCMCIA Release 2.0.
.
8. Soft reset puts all devices into power-down mode and requires a recovery time after returning from soft reset (500 ns for
reads and 1 ,.s for writes).

4-271

infel"

AP-361

Soft Reset Register
(Configuration Option Register)
PCMCIA-Defined
CIS
ADDRESS

BIT7

4000H

SRESET

BITO

• Toggle SRESET to reset and return to standby-mode .
• For power-on default, SRESET =

o.

Figure 4. Useful for placing the card Into a known state

The other two fields (not implemented with the Series 2
Card), defined in this register by the PCMCIA R2.0
specification, include the Configuration Index and the
LevIREQ. After powerup or soft reset, the Configuration Index contains zeros to maintain compatibility as a
Memory-Only Interface. The LevlREQ bit is hardwired
to zero.

system aimed at power conservation looks to shut down
portions of system circuitry not in use (i.e. the solidstate drive not accessing files, the screen's backlight
when the keyboard has not been touched in a certain,
amount of time, etc.). Powering down the entire socket
achieves a minimal power usage status. However, the
powerup recovery time from this approach produces
varying delays.

GLOBAL POWERDOWN REGISTER

The Series 2 Card offers the optimal solution with the
Global Powerdown Register (Figure 5). Writing a one
(I) to the Power-Down Bit (PwrDwn, bit 2) of this
register puts all internal devices into the Deep-Sleep
Mode by pulling every device's PWD input low(9). In
the Deep-Sleep mode, a 20 Megabyte Series 2 Card consumes 90% less current versus the standby mode current(10).

PCMCIA R2.0 Defined
(Configuration and Status Register)

The portable system designer strives to minimize power
consumption in every conceivable way. Solid-state storage devices using Intel Flash Memory deliver significant power consumption reductions (when compared to
the mechanical disk) and therefore play an important
part of the system design considerations. The portable

When the host system drives the two card enable pins
high(11), the Series 2 ASIC circuitry blocks system-level
address and data signals from the internal devices. Additionally, latching address buffers and data transceiv-

Global Powerdown Register
(Configuration Option Register)
PCMCIA·Deflned

• Powerdown places all devices into Deep-Sleep mode.
• Write zeros to maintain PCMCIA compatibility.
• PWRDWN = 0 after reset.

Figure 5
NOTES:
9. The remaining fields in this register (Changed, SigChg, IOisS, Audio, Intr and Rsvd) are tied low in the Series 2 Card for
PCMCIA compatibility and for simplifying software masking.
'
10.!.QQ§ = 30 /LA V~CSL = 0.2 /LA; refer to '2BFOOBSA Data Sheet. The ASICs consume 1 /LA.
11. CE1 (pin 7) and CE2 (pin 42) = VIH

4-272

intel..

AP-361

SAMPLE 80X86 CODE TO HANDLE RECOVERY-PERIOD TIMING
GLOBAL_PWD
NOT_PWRDWN

EQ.U
EQ.U

MOV AX, MEM_CARD_BASE
MOV ES, AX
MOV DI, GLOBAL_PWD

4002H
OH

;Global PowerDown Register

;Load card address'
;Pointer setup

;Software assumes alrpady in REG# mode access
MOV BYTE PTR ES:[DI], NOT_PWRDWN ;Clears PWRDWN bit
MOV CX, RECOVERY_TIME
FOR_A_WHILE:
LOOP FOR_A_WHILE

;Based on speed of processor

Figure 6. Assembly Language Code for Returning from "Deep-Sleep" Mode

ers on the host side eliminate address and data signal
switching at the Series 2 Card input buffers further reducing power consumption levels. In other words, to
achieve the lowest power consumption levels, these signals should not be floated or tristated.
After clearing the PwrDwn bit, the device-recovery
times must be met before accessing the flash memory.
As shown in Figure 6, the recovery period can be implemented using a simple software algorithm(l2).

successful status (Status Register = 80H) indicating
the need for software drivers to use the powerdown
function intelligently.

PERFORMANCE ENCHANCEMENT
REGISTERS

Sleep Control Register
(Performance Enhancement Register)

Prior to entering the Powerdown Mode, your software
must check operation status for data-writes or blockerases in progress(13). Any operations in progress will
be terminated when powering down the flash array.
The 28FOO8SA does not maintain Status Register contents in the Powerdown Moej,e. Therefore, when the
card returns to standby' mode, all devices will report

The powerdown functionality of the Global Powerdown
Register has a global affect on all devices. In many
solid-state storage applications, reading or writing files
only requires access to select device pairs and the remaining devices could be kept in Deep-Sleep status until needed.

Sleep Control Registers
Performance Enhancement Register

BIT 5

ADDRESS

BIT 4

BIT 3

{:lIT 1

BITO

411AH

\ DEVICES DEVICES
18/19
16/17

4118H

DEVICES DEVICES
2/3
0/1

• For reset, all devices powered up (bits = 0).
• On cards less than 20 megabytes, absent devices read as "O"s.
• Bits cleared to zero by SRESET and RESET.
Flgu~e

7. Allows Selective Powerdown of Devices within the Series, 2 Card

NOTE:
12. PCMCIA does not specify a maximum recovery time. Recovery times, varying for different card technologies, must be
handled on a case-by-case basis.
13. Polling the individual device's Status Register, the Ready/Busy Status Register, or the RDY/BSY bit in the Card Status
Register.

4-273

int'eL

AP-361

2SFOOSSA Status Register Bit Definition

BIT 7
WSM
STATUS

BIT6
ERASE
SUSPEND
STATUS

BIT5
ERASE
STATUS

BIT4
WRITE
STATUS

BIT3
vpp

STATUS

Figure S. Read during Write or Erase Operations to Determine Status
The Sleep Control Register (Figure 7) offers this option; each bit provides power down for a specific device
pair. Except for the global vs individual affect, this register functions identically to the Global Powerdown
Register. The global powerdown can be enabled while
individual devices are sleeping. Disabling the global
PWRDWN does not affect prior bit settings of the
Sleep Control Register.

READY-BUSY STATUS REGISTER
Performance Enhancement Register

In many applications using the Series 2 Card, the card
will be in the Standby Mode a large percentage of the
time. This avoids device recovery times associated with
complete socket power off or entering the Deep-Sleep
Mode. In the Standby Mode, the Sleep Control Register offers the greatest advantage over the Global Powerdown Register. With the capability of controlling individual device pairs, a power savings improvement of
approximately 16 times (based on typical current values) will be seen. This is derived from the following
information:
• 28FOO8SA devices in Deep-Sleep; Icc = 0.2 /LA,
Ipp = 0.1 /LA.
• 28FOO8SA devices in Standby; Icc = 30 /LA,
Ipp = 1 /LA..
• ASICs in S'tandby and Sleep; Icc = 1 /LA.
• With device-pair control, unaccessed devices remain
in Deep Sleep.
Although the other operating modes (read, data-write,
or block-erase) also exPerience power savings by using
the Sleep Control Register, the effects are not as significant relative to the higher current requirements of
those modes.
When using the Sleep Control Register, software must
account for the same device-recovery time of the global
powerdown method. To access files (or data) that span
multiple device pairs (and experience uninterrupted access), software can perform a "look-ahead" function to
determine which device pairs must be powered up.

The automated data-write and block-erase capability of
the Intel 28FOO8SA FlashFile Memory results in a significant performance improvement. Furthermore, automation simplifies system-level interfacing as the user
only delivers the proper command and monitors the
operation's READY/BUSY status. Referring to the
28FOO8SA Data Sheet (or Figure 8), operation status
can be obtained from the device's Status Register or
RY/BY pin. The device's Status Register allows software polling for ready status in addition to write and
erase status. The RY/BY pin can be used to generate
an interrupt when making a busy to ready transition.
Regardless of the method used for determining ready
status, the Status Register should be read to determine
whether an operation was successful.
In the Series 2 Card, where mUltiple devices are present
and mUltiple simultaneous operations can occur, software polling each device's Status Register requires extra software and time. Furthermore, thePCMCIA interface only has one RDY/BSY pin which obviously
prevents 20 devices from hooking their individual
RY/BY out to the system. The ASICs within the card
take these signals and feed them into the BUSY Status
Register (Figure 9). This facilitates multiple device-pair
operations by allowing an analysis of all devices simultaneously. After initiating the data-write and blockerase operations, the system can switch the card to the
Attribute Memory Plane to access these registers. Alternatively, each device's RY/BY signal funnels into a
single "wired or" signal that becomes the PCMCIARDY/BSY pin driving an interrupt or polled through
an I/O port.
When performing single device pair operations, Ready/
Busy status should be accessed directly from the Status
Register of the flash memory devices for the following
reasons: 1) A device's Status Register must be read anyway to determine the result of an operation; 2) This
saves several instructions required to switch to the Attribute Memory Plane.

4-274

int:eL

AP-361

Ready-Busy Status Register
Performance Enhancement Register
CIS
ADDRESS
4134H

BIT3

BIT2

DEVICE
19

DEVICE
18

BIT 1

BITO

DEVICE DEVICE
17
16

4132H

DEVICE
15

DEVICE
14

DEVICE
13

DEVICE
12

DEVICE
11

DEVICE DEVICE DEVICE
10
9
8

4130H

DEVICE
7

DEVICE
6

DEVICE
5

DEVICE
4

DEVICE
3

DEVICE
2

DEVICE DEVICE
0

• Each bit corresponds toa device's RY IBY signal .
• Devices not present (i.e. < 20 Megabytes) return ready status.

Figure 9. Monitors Individual Device's RY /BY Pins

Example for Monitoring Ready/Busy Status

(Assume ES contains memory card base address)

RDY-BSY-STATUS
DEVICE_O
DEVICE_l
DEVICE_2
DEVICE_3
DEVICE_4
DEVICE_5
XOR AX, AX
MOV DI, RDY_BSY_STATUS

EQU
EQU
EQU
EQU
EQU
EQU
EQU

4130H ;Register address
;5.ettings in register for specific devices
OlH
02H
04H
08H

lOH
20H
;Zero AX Register

;Insert code to start write operation in first 3 Device Pairs
:i.e. Devices 0, I, 2, 3, 4, 5.
OR
OR
OR
OR
OR
OR

AX,
AX,
AX,
AX,
AX,
AX,

DEVICE_O
DEVICE_l
DEVICE_2
DEVICE_3
DEVICE_4
DEVICE_5

:Assume card already in REG mode.
TEST BYTE PTR ES:[DI]. AX
:Zero flag cleared when programming
;devices are ready~

4-275

intel .

AP-361

tions perform well as background tasks because the interrupt latency constitutes a small fraction of the total
time.

READY-BUSY MASK REGISTER
Performance Enhancement Register
As described earlier, completion of a data-write or
block-erase operation can be determined by attaching
the card's RDY/BSY pin into a system interrupt. This
frees the host system to perform alternate tasks after
initiating an operation. In other words, device-level automation allows Series 2 Card operations' to become
background tasks.
Occasions exist where the interrupt generated from a
device becoming ready produces unacceptable latency
times. For instance, data-write operations, completing
in only 10 ,""S, realize a performance penalty dealing
with interrupt latencies longer than the write time itself. The data-write operations would achieve a higher
level of performance by using software polling techniques(14). On the other hand, block-erase operations
typically require one second.· Therefore, these opera-

The above discussion implies. that the system interrupt
should be disabled for data-writes and enabled for
block-erases. What if an application requires simultaneous writes' and erases? The Series 2 Flash Memory
Card handles this situation with its Ready-Busy Mask
Register (Figure 10). Setting the appropriate mask bits
in the Ready-Busy Mask Register blocks the corresponding device's RY/BY signals. With a device's
mask bit set, the card's RDY/BSY pin and Card Status
Register (bit 0) always reflect a ready condition, regardless of the operation status. Figure 11 displays a conceptual mask circuit for a single device. The mask settings have no effect on the card's Ready-Busy-Status
Registers (providing direct access to each device's
RY/BY output) or the Device Status Register. This
allows software polling in the usual manner.

Ready~Busy Mask RegIster
Performance Enhancement Register

CIS
ADDRESS

BIT3

BIT2

. BIT1

BITO

4124H

DEVICE DEVICE DEVICE DEVICE
19
18
17
16

4122H

DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE
8
15
14
13
12
11
10
9

4120H

DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE DEVICE
0
1
7
6
5
4
3
2
1 = MASKED
Figure 10. Allows Masking of IndIvidual DevIce's Ready/Busy Signals
selectln~

the Appropriate Device to Mask

Assume the register set DI:DX contains a 32-bit physical address into SERIES 2 card.
Each device pair represents 2 Megabytes (i.e. 200000H).

MOV OL, 5 ;Load shift count
SHR DI, OL ;Result in DIis device pair number to mask.
;Now determine whether to mask device pair for word operations or use Bit 0 of
the DX portion to determine high or low device (odd or even) for byte
operations.
NOTE:
14. Polling the individual device's Status Register, the Ready/Busy Status Register, or the RDY/BSY bit in the Card Status
, Register.

4-276

intaL
Single Device Representation of ROY IBSY Mask and Status

o
oo
o

READ IN READY/BUSY
STATUS REGISTER

.-2-8-fO-O-8-SA--.....,;DE~V~IC:;.:E~=~"""""

COt.4BINE WITH ALL DEVICE
OUTPUTS TO PRODUCE CARD
INTERfACE AND CARD STATUS
REGISTER READY/BUSY

~~_ _... READY/BUSY

o

o
o
o
o

o
o
o
o
o

MASK ENABLE
l=t.4ASKED

292096-3

• Each device has a ReadylBusy (RY IBY) output.
• When mask enabled, devices always appear ready.
• RYIBY available in RDY-BSY Status Register.

Figure 11. The Ready-Busy Mask is Very Useful for Write Optimization

READY-BUSY MODE REGISTER
Performance Enhancement Register
The PCMCIA specification for the Ready/Busy interface states that "the RDY/BSY line is driven low by the
memory card to indicate that the memory-card circuits
are busy and unable to accept a data-transfer operation." Contrary to the PCMCIA specification, devicelevel data-write and block-erase automation enables the
Series 2 Card to perform multiple operations simultaneously. USing· the PCMCIA-specified method of
ROY/BSY functionality for multiple device operations,
the RDY/BSY interrupt does not notify the system until all devices finish because busy devices hold the
ROY/BSY signal low, as shown in Figure 12. Multiple
block erases (typical block erase time of 1 second) could
present an unacceptable pushout if system software
waits for the first available "clean" block to write data.

The Series 2 Card offers an alternative Ready/Busy
mode (High-Performance Ready!Busymode, alias
"Levy"-mode) removing the performance impact of the
PCMCIA mode. Circuitry internal to the ASIC catches
every "READY-going" edge from each device. After
an individual device becomes ready (Ready/Busy signal
goes high), the system has the opportunity to immediately service the interrupt. System software must now
toggle the CLEAR bit (bit 1) in the Ready-Busy Mode
Register (Figure 14) to reactivate the Ready/Busy signal. Figure 13 demonstrates the resulting waveform.
The Series 2 Card powers up in the PCMCIA-mode.
Switching into the High Performance mode requires a
two step process, as shown in Figure 15. ASIC circuitry
design prevents being able to write a zero to the RACK
bit on the same cycle as entering the High"Performance
ROY /BSY Mode. This intentional design technique
eliminates the possibility of receiving a noise generated
RDY/BSY rising edge, which would trigger an unwanted interrupt.

4-277

infel .

AP-361

PCMCIA-Defined RDYIBSY Waveform for Multiple Device Operations
First operation finishes
DEVICE 0 RY!BY

-'L___..(...-

Interrupt __
latency
,

DEVICE 1 RY!BY

DEVICE 2 RY!BY
PCMCIA RDY!BsY

i

---,L________ , .....- - ~I-

Interrupt occurs

292096-4

Figure 12. PCMCIA-Deflned RDY IBSY Waveform for Multiple-Device Operations
High-Performance RDYIBSY for Multiple Device Operations.

DEVICE

0 RY!BY - ' ' ' '_ _-4

DEVICE 1 RY!BY
DEVICE 2 RY!BY
(Masked)
RDY!BsY SIGNAL

I :

,

------+': --,'
r'.(;,,3----1
...
" _ _"",,,

t'. i=I....._~_____
~~'

292096-5

MASK BIT .~RDY/BSY
RY!BY ~ (PCMCIA-Interface)

292096-6

NOTES:
1. Device 0 operation completes. RDY IBSY generates system interrupt. A masked RY IBY is zero. Unmasking
simultaneously or after RY IBY going high, still enables a low-to-high transition on RDYIBSY to generate interrupt.
2. Software clears bit 1 of Ready-Busy Mode Register pulling RDY/BSY signallow.
3. Last device operation completes. Masked ROYIBSYsignal does not generate interrupt. Software must poll to
detect operation completion of masked device(s).

Figure 13. High-Performance Mode Catches Each Device Going Ready

4-278

infel .

AP-361

Ready/Busy Mode Register
Performance Enhancement Register

• Mode = ReadylBusy Mode
o = PCMCIA Mode
1 = High-Performance Mode
• RACK = Ready Acknowledge Bit
Clear this bit after receiving ready status to prepare for next device's ready transition
• Register defaults to PCMCIA Mode for power on or reset. In PCMCIA Mode, RACK is a Don't Care

Figure 14. To Prevent Accidental Ready Transitions, a Three Step
Sequence must be Followed to Enter Hlgh·Performance Mode
As discussed in the previous section, the block-erase
operation benefits from the interrupt capabilities of the
RDY/BSY signal. However, if your software only erases one device pair at any time, the PCMCIA-RDY/
BSY Mode will be sufficient for two reasons: 1) Both
devices started simultaneously will complete the erase
operation almost at the same time; 2) in 16-bit access
mode, both devices of the pair must be erased before
writing.

To block-erase in multiple devices:
1. Be sure to mask all devices (in Ready/Busy Mask
Register).
2. If not already done, place the Series 2 Card in the
High-Performance Mode (refer to Figure 15).
3. Issue the bloc!c-erase command sequence to the appropriate devices.

Enabling Hlgh·Performance Ready/Busy Mode
Prevents ready devices from triggering an unwanted rising edge, and generating an interrupt after clearing RACK bit.

Write a one (1) to the Mode bit of the RY IBY Mode Register.

Write a zero (0) to the RACK bit of the RY IBY Mode Register. The hardware
requires this sequence to eliminate unwanted interrupts caused by signalbounce.
292096-7

Figure 15. Entering Hlgh·Performance Mode

4-279

infel .

AP-361

4. Unmask appropriate Ready-Busy Mask Register
bits. The circuitry catches devices with already completed erase operations with the conceptual setup
shown in Figure 13. Use a RAMcbased variable or
register for an erase-block queue to monitor erasing
devices.
The interrupt service routine (ISR) can be as simple as
removing the erase block from the queue. It could also
be used to notify the system that this block is free to
use. Regardless of the ISR impiementation, it should
include the following basic procedures:
1. Set all RY/BY masks in the Ready-Busy Mask Register. This prevents additional interrupts within the
ISR (i.e. prevent re-entrant interrupt). Keep track of
mask setup to reinstate before ISR exit.
2. Check the queue of erasing devices and read. the
Ready-Busy Status Register to determine which device completed the operation.

3. Service the erased block(s). Even though one erased
block generated the interrupt, more blocks may have
completed erasing at this point.
4. Clear RACK in the Ready-Busy Mode Register.
S. Before exiting the ISR, reset the mask. This
"catches" devices that went. ready during the ISR
and will cause are-entrant ISR. However, at this
point in the ISR, this will not affect system or softc
ware integrity.
.

WRITE-PROTECTION REGISTER
The Series 2 Card contains a PCMCIA-defined, hardwired Card Information Structure (CIS) accessed in the
Attribute Memory Plane. This data structure provides
fundame!ltal, unchanging information pertaining to the
card. It includes card size, type of components, access
speed, etc. Situations exist where the user needs to include custom-format information, such as card partitioning and operating system specific information.

DIAGRAM OF COMMON MEMORY PLANE
13fffffH
1200000H

DEVICE' PAIR 9

,

DEVICE' PAIR 8

1000000H

OEOOOOOH

DEVICE: PAIR 7

OCOOOOOH

DEVICE ,PAIR 6

OAOOOOOH

DEVICE, PAIR 5

,

0800000H
0600000H

O"OOOOOH
0200000H

28f008SA

DEVICE' PAIR 4

,
. DEVICE: PAIR 2
,
DEVICE' PAIR 3

DEVICE, .PAIR 1

"E0
~

'"

co

"'-""
J,8

_lD

OOOOOOOH

28f008SA

DEVICE, PAIR 0

,
OPTIONAL CIS
MEMORY BLOCK
292096-8

• The first block pair of the first device pair is the common memory CIS; write protect using CISWP bit of Write
.
Protection Register.
• Write protect the remaining 159 block pairs using the CMWP bit of the Write Protection Register.

FiSJure 16. The WRITE PROTECT REGISTER Blocks Writes
to the Two Sections of the Common Memory Plane

4-280

intel"

AP·361

The CIS Write Protect Bit (CISWP, bit 0) prevents
writes to the Common Memory CIS blocks. When software determines that this block of memory contains
valid, custom-format information (contains PCMCIA
tuple data structure), the CISWP Bit could be set to
prevent accidental data corruption by another application. Note that if an End-User format utility is provided, this software must be careful not to destroy the
custom format information which could be accessed if
the CISWP Bit was deactivated. The Common Memory Write Protect Bit (CMWP, bit 1) prevents writes to
the remainder of the Common Memory Plane (i.e. minus the Common Memory CIS blocks). To "software"write-protect the entire Common Memory Plane, both
bits must be set.

This information can be loaded in the Common Memory CIS during card format (refer to Figure 16). Typically, once this information is written, it would' rarely
change. The Series 2 Card provides a means of locking
this area of memory,. as well as the remainder of the
Common Memory array with the Write Protection
Register (Figure 17). The Write Protection Register
has an advantage over the mechanical write protect
switch in that it allows software to control user write
access to the card's data (the mechanical switch can be
easily switched off enabling card writes). For example,
a pen-based system may use this feature to protect its
read-only operating system stored within the Series 2
Card.

Write Protection Register
Performance Enhancement Register

• CISWP = Common Memory CIS Write Protect
• CMWP = Common Memory Write Protect
• "1" = Write Protected

Figure 17. Provides a Software Implementation of the Write Protect Switch

CARD STATUS REGISTER
Performance Enhancement Register
This (Read-Only) register provides quick access to generalized conditions within the Series 2 Card (Figure
18). It provides a shorthand method for checking the
following functions:
•
•
•
•
•
•

Ready/Busy Status
Ready/Busy Masking
Deep-Sleep Modes
Setting of Mechanical Write-Protect Switch
Software Write Protect Status
Soft Reset Status

Where the RY /BY Bit (bit 0, Card Status Register)
displays the operation status of the cumulative devices
within the card, the Ready-Busy Status Registers reflects the status of each individual device. Bit 0 (RDY/
BSy) mirrors the card's RDY/BSY (Ready/Busy) output pin, also reflecting any Ready/Busy masking conditions. Two circumstances warrant the use of this bit: 1)
When the hardware interrupt triggered by the RDY /
BSY pin produces an unacceptably long latency period,
this bit should be software polled instead to increase
performance; 2) When multiple devices have datawritelblock-erase operations in progress, reading this
cumulative Ready/Busy status will be quicker than
reading multiple status registers within each device.
However, when the application requires immediate access to each device as it finishes an operation, individual Device Status Registers or the card's Ready-Busy
Status Register must be used.

4-281

I

infel .

AP-361

Card Status Register
Performance Enhancement Register

•
•
•
•
•
•
•
•

RDY /BSY == Reflects PCMCIA interface RDY /BSY pin, 0 = busy
WP = Mechanical Write Protect Switch, 0 = off
CISWP =' Common Memory CIS Write Protect, 0 = off
PWRDWN = Powerdown Reflects PWRDWN in Global Power Down Reg, 1 = Power Off
CMWP = Common Mode Write Protect, 0 = Off
SRESET = Soft Reset Reflects SRESET in SOFT RESET Reg, 1 = Soft Reset
ADS = Any Device Pair Powered Down, OR'd Condition of Sleep Control Reg, 1 = Power Off
ADM = Any Device Masked, OR'd Condition of Ready-Busy Mask Reg, 1 = Masked

Figure 18. Provides Generalized Card and Device Information
Bit I reflects the card's mechanical switch position (1
= Write Protected). This switch disables any writes to
the card. Two software strategies can be implemented
for this bit: I) Assume the card's Write-Protect switch
is off. Attempt to write to the card and only check the
Write-Protect status if the data-write fails (which it will
if the switch is on); 2) Check the switch first to avoid
the possibility of failing a data"write. The choice depends on the application. For a solid-state disk continuously updating files, the former is more appropriate because the Write-Protect switch will probably be off.
Bits 2 (CISWP= Common Memory CIS) and 4
(CMWP = Common Memory Write Protect) are direct (Read Only) inputs'from the Write-Protect Register. These bits should be checked in a manner similar to
that for Bit I (WP). For more detail refer to the WriteProtection Register section.

The SRESET Bit (bit 5) provides a (Read-Only) version
of the SRESET Bit in the Soft Reset Register (I
Locked in soft reset state).

SUMMARY
The Series 2 Flash Memory Card delivers the hardware
capabilities required for implementing a solid-state
storage device. Software engineers will find the features
of this card both flexible and powerful when coupled
with flash-optimized filing systems, such as Flash File
System from Microsoft. This application note has discussed the various methods of using the Component
Management Registers to facilitate designs incorporating the SERIES 2 card.

The PwrDwn Bit (bit 3) provides a (Read Only) version
of the PwrDwn Bit in the Global Powerdown Register
(I = PwrDwn). Only the Attribute Memory Plane is
available with the Powerdown feature enabled, allowing
access to the Component Management Registers ..

4-282

• PCMCIA-Defined Registers provide generalized assistance for memory card interfacing.
• Performance Enhancement Registers boost software
control over the card's internal flash memory devic~
es.

infel~

AP-361

GLOSSARY

non-changing information about the SERIES 2 Card
(i.e. density, speed).

Attribute Plane: Memory plane within the card selected bY'pulling the REG pin low. This random access
memory contains the CIS and Component Management Registers.

Levy Mode: alias for the High-Performance mode for
Ready/Busy notification.

Block-Erase: Erasing sections of a single flash memory
device.

Personal Computer Memory Card International Association (PCMCIA): The organization formed to promote interchangeability of IC cards by providing a
standardized mechanical, electrical and metaformat interface.

Bulk-Erase: Erasing the entire flash device simultaneously.
Common Memory: The memory card's main memory
array.
Common Memory-Card Information Structure: The
first block pair of the first device pair. Useful for storing custom format information, such as partitioning of
the card.
Component Management Registers (CMR): Memory'mapped I/O registers used to control device-level functions.
Deep-Sleep Mode: A special very low power mode useful for saving power when not accessing the flash memory components.
.
Device-Pair: Arrangement of the S-bit 2SFOOSSA devices in the SERIES 2 card in a word-wide manner.
ExCA: System Implementation (hardware and software) of PCMCIA R2.0.

Performance Enhancement Registers: MemoryMapped I/O registers included by Intel in the Series 2
Card to boost performance by providing software control of the internal 2SFOOSSA functions.
Ready/Busy: Indicator used to determine when a data~rite or block-erase operation has completed. SymbolIzed by RY/BY for the 28FOO8SA and RSY/BSY at
the Series 2 Card interface.
Status Register: A register internal to a 2SFOOSSA
FlashFile™ Memory device used to determine write
and erase operation status.

RELATED DOCUMENTS
2SFOOSSA, 8 Megabit, FlashFile™ Memory Data
Sheet
Series 2 Flash Memory Card Data Sheet
82365SL, PC Card Interface Controller Data Sheet
PCMCIA PC Card Standard Release 2.0
Exchangeable Card Architecture Specification

Hardwired Card Information Structure (CIS): Embedded into the Attribute Memory Plane. to describe

4-283

infel·

RELIABILITY
REPORT

RR-70

August 1992

Flash Memory Card
Quality/Reliability Data Summary

Order Number: 293007-002
4-284

Flash Memory Card
QualityIReliability Data Summary
CONTENTS·

PAGE

INTRODUCTION ....................... 4-286
QUALITY ASSESSMENT .............. 4-286
RELIABILITY STRESS ................ 4-286
MECHANICAL STRESSES ............ 4-289

CONTENTS

PAGE

APPENDIX A .......................... 4-291
External Dimensions ................... 4-292
Pin Configurations ...................... 4-292
Pin Descriptions ........................ 4-293
Functional Block Diagram .............. 4-294

CONTAMINATION ... .................. 4-289
CARD CARE SUGGESTIONS . ......... 4-289
DATA SUMMARy ..................... 4-290

. 4-285

intel .

RR-70

INTRODUCTION/SCOPE
Quality and Reliability: The
Cornerstone of Business
In the world of electronic hardware, no facet is more
important to the user of a system than the reliability of
its individual components and subsystems. Being the
leader in FLASH, we are proud of the continuous quality and reliability leadership position in the marketplace we have maintained.
In the spirit of service to our customers and their cus- '
tomers, this publication has been assembled for your
convenience and reference. The scope of this document
is limited to Intel's latest Flash Card Products consisting of the 11214 Meg densities. The FLASH device
specific product/process reliability summaries can be
found in RR-60. The data provided herein is the product of just one of Intel's qualification and reliability
monitoring systems. The purpose of this report is to
-supplement Intel's Quality and Reliability handbook
with product specific data. For additional information,
please contact your Field Sales or Customer Quality
Engineer.

Quality versus Reliability
The traditional concepts segregating quality from reliability is one of time. Quality is a measure of the ability
of a product to meet performance expectations at a single point in .time. This "point in time" is usually interpreted as your initial board power-up or incoming inspection. Reliability, on the other hand, is a measure of
a product's ability to maintain its "time zero" quality
throughout its life cycle. A reliability failure usually
occurs after your product has shipped to your customer.
The cost of poor quality can be objectively totalled
within your organization. It includes the cost of detection and in-house repair. However, the cost of poor
reliability has a much higher cost. Besides an inherently
higher repair cost per defective unit, reliability failures
create customer concern about design and/or workmanship standards used in the manufacture of the
product. Loss of goodwill with your customers can
have many long term ,negative effects on your business.
Therefore, Intel advocates that you make reliability a
key consideration for. the selection of your system's
components.

The Roots of Reliability
The manufacture of a reliable VLSI semiconductor device using a modem technology is a dynamic and evolutionary process. Success of this process is highly dependent upon the interplay between knowledgeable and experienced manufacturing engineers, materials physi-

cists, and responsible/responsive management. Only
the correct ,combination can consistently deliver high
volumes of reliable product. In this model, the experienced process engineer selects and defines the stresses
to be performed and the performance criteria to be met,
utilizing appropriate statistical tools and limits. The
materials physicist then determines the root causes of
failure, if and when failure occurs, and provides effective solutions and or containment recommendations.
'Finally, management provides the resources for the entire process from initial monitor to root cause corrective action.

MONITORS: THE CONTROL
MECHANISM OF RELIABILITY
A Com'prehensive Program is the Key
Intel has developed and implemented many types of
reliability monitoring systems. Since continuous delivery of reliable product is of paramount importance,
most of the monitors are in-line and are designed to
provide as close to "real time" feedback on the reliability of the product in-process as possible;· The monitors '
are located throughout the fab, assembly and test areas.
The data from these monitors are an indication of process health and overall statistical control. They are not
necessarily directly correlatable to the reliability of the
product that will ship to your location. For this reason,
a final finished product monitor which randomly selects product is used as the yardstick to measure the
success of our factory in meeting your customer's reliability goals.

QUALITY ASSESSMENT
All new cards undergo a full temperature range quality
test assessment. This involves a specific sample size of
product to be 100% temperature range tested. The
quality goal to be met is consistent with the Intel Corporate stated quality goals.

RELIABILITY STRESS
ELT Extended Life Test'
ELT is performed on programmed cards.
Vee = S.2SV and the stress temperature is held to a
maximum of 85°C due to card and connector thermal
considerations. It is functionally exercised in a sequential addressing pattern and outputs are exercised but
not loaded. See Figure I for the typical bias and timing
conditions. The end point electrical tests are conducted
within a fixed period of time to worst case data sheet
parameters. The Memory Components Division also
periodically takes variables data on selected data sheet
parameters to monitor the stability of the process.

4-286

int:eL

RR-70

ELT Configuration
Device: Memory Card
Stepping:
Description: 1 Meg, 2 Meg, and 4 Meg
Technology: CHMOS III

GND

1

N/e
N/e
N/e
N/e
N/e

2
3

Configuration Type: ELT
Temperature: 8S'C
Package: Memory Card

68 GND
67 GND

F
L

66 Hie
65 Hie
64 Hie

A

4

s

5

H

6

GND

7

hi

A10

a

hi

GND

9

0

A11 10

E

e
A

A1414

D

R

Vee 15

N/e

16

Vee 17
GND 18
A16 19
A15 20

Vee

Hie
60 Hie
59 N/e
58 Hie
'57 N/e
56 Hie
55 N/e
54 Hie
53 N/e

R
Y

A13 13

Vee

62
61

A09 11
Aoa 12

63

ELl

52 GHD
B

51

I
A
S

Vee

50 A21
49 A20

A1221

48 A19

A0722

47 A18

A06 23

46 A17

A05 24

45

A04 25

44

N/e
N/e
N/c

A03 26

43

A02 27

42 GHD

N/e
N/e
N/e
Hie
N/e

A01 28

41

AOO 29

40

N/e
N/e

30

39

31

38

Hie

32

37

N/e

33

36 GHD

GND 34

35 GND

293007-2

dption Pins: All option pins parallel to each other, programmable to

A,6
Binary Sequence from

Ao

Vee

to A,6

293007-1

Figure 1. Typical ELT Bias and Timing Sequence

4-287

intel"

RR-70

ESD
ESD Testing...,...This test is performed to validate the
products tolerance to Electro Static Discharge damage.
All products incorporate ESD protection networks on
appropriate pins. Three types of ESD testing were performed. Mil Spec to ± 2K, charged device to ± 1.5 KV
and Case Zapping to ± 2 KV. The cards contain internal spring connections to ensure the case lids are
grounded.

GND

68GND

1

..A/IIIr 2
GND ..A/IIIr 3
+5 ..A/IIIr 4

liDOS

GND.iM- 5

1/006

..A/IIIr 8

1/007

+5

+5

F

67 GND

L

66 .iM- +5

A
S
H

64.iM- +5
63 +5

+5

7

~

GND

8

~

61 Nle

+5

9

0
R

60 Nle

E

Temperature Cycling (TIC)

GND 10

Temperature, cycling evaluates !lot only the card's mechanical ability to remain a closed memory card system
but further evaluates the mechanical solder joint integrity of card assembly process. IK cycles of -40°C to
+ 85°C cycling are required with 20 minutes/cycle.
Electrical endpoints are tested across the data sheet
temperature range.

GND 12

e

+5 13

A

GND 14

0

Y

62 +5

59 Nle
58 Nle

+511

R

57 Nle
56 Nle
55 Nle
54 Nle

+5 15

Nle 16

THB

+5 17

53 Nlc
52 GND

GND18

B
I

51 +5

+5 19

A

50 +5

Moisture Resistance (85°C/85% RH)

GND 20

During the 85/85 test the cards are subjected to a high
temperature, high humidity environment. The objective
is to accelerate corrosion failure mechanisms thru an
electrolytic process. This is accomplished through a
combination of moisture penetration of the plastic,
voltage potentials and contamination which, if present,
would combine with the moisture to act as an electrolyte. See Figure 2 for typical 85/85 Bias Diagram.

GND 22

s

+521

49 GND
48 +5
47 GND

+523

46 +5

GND 24

45 Nle

+525

44 Nle

GND 26

43 N/e

+527

42 +5

41.iM- +5

GND 28
+529
GND

65.iM- GND

40.iM- GND

..A/IIIr 30

39 .iM- +5

+5~31

1/001

38.iM- GND

..A/IIIr 32

1/002

37

GND

..A/IIIr +5

Nle 33

36 GND

GND 34

35 GND

293007-3

NOTE:
All resistors are 10

K~

1/4W 5%.

Figure 2. Typical 85/85 Baislng

4-288

inteJ"

RR·70

MECHANICAL STRESS

Externalllnternal Dimensions

Vibration

External case and connector dimensions are verified to
specification. Internal examinations are performed for
device alignment and solder joint quality.

Test is done to evaluate memory cold surface mount
(SM) reliability. Test condition: SSH2 for 2 hours.

CONTAMINATION
Drop Test
This test is to simulate the conditions a flash memory
card could be subjected to if inadvertently dropped.
The test consists of 10 repeated drops from an elevation
of 4 feet to a tile floor in the X, Y and Z orientation.
Lid popping or frame/card damage are not allowed.
Testing is followed by visual examination and ambient
electrical/function testing.

lonograph
Internal PC Band components are evaluated using an
ionograph for ionic content: PC B· without cases/
frames are emersed in the ionograph fluid and ionic
contamination levels are measured. The cards are required to contain less than 15 fLgm/sq. in. NaClor
equivalent.

Pressure/Crush Test

Visual Flux Residue

This test is to simulate the effect of a crushing force
applied to the card. This condition could be as a result
of inadvertently sitting on the card while in a persons
pocket. The test consists of a 100 kg load for a duration
of 40 seconds pressed thru a rubber pad on top or bottom surface of the card. Stressing is followed by a ambient electrical/functional test.

Memory cards are visually examined at lOx for SMT
.process flux residues. This examination gives an indication of the throughness of the PCB cleaning step after
IR reflow processing.

CARD CARE SUGGESTIONS
Several simple precautions should be observed when using/storing your flash memory card.

Socketing Test
This test verifies the connectors life expectancy of the
card. It simulates repeated insertion/removal into a
system. It is 10k insertions duration.

Connector Opening
Keep this area free of dirt, food and moisture. The
connector holes could become clogged/obstructed
and possible damage to the main system male connector could result.

Switch Test
The flash memory card incorporates a write protect
slide switch. The switch is cycled for endurance to lk
cycles.

.Bend/Flex Test
This test is to simulate the effect inadvertent flexure or
bending of the card. It consists of five consecutive scan
twists in both the X-Z and Y -Z directions. Ambient
electrical/function testing is performed to verify the·
card.

4-289

Storage
When possible keep the card in a cool dry place.
Laying the card in bright, hot sunlight could cause
the card to warp making system insertion difficult.
Store the card in its protective sleeve when not in
use. This will help keep the connector clean.·
Never sit on, drop or emerse the card in water.

RR-70

QUALIFICATION SUMMARY
1, 2 & 4 MB FLASH MEMORY CARD
Test

Level III

Condition

ELECTRICAL
TempQV

-10·C/+70·C, 5V±10%, <500 DPM

ELT

85·C, 1K hours, 5.25V

NR

@

60%

NR

Mil Spec ±2KV

0/5

Charged Device ± 1.5 KV

0/5

Case Zap ± 2 KV

0/5

TIC

- 40·C to + 85·C, 1K Cycles

0/66

85/85

1K Hours at Alternate Pin Bias

0/66

Vibration

55 Hz, 2 Hour

0/10

Drop

4' to Tile Floor X, Yand Z, 10X

0/10

Pressure

100 kg Load, 40s thru 2 mm Rubber Sheet

0/10

Socketing

10K Insertions

0/10

Switch

1K Cycles

0/10

Bend

0.5 cm Twist, 5X

0/10

Connector

Dimensionsper Spec

0/10

External

Dimensions per Spec

0/10

Internal

Visual Solder Joint-Device Alignment

0/10

< 15 ,...gm/Sq. In. MaCI Equivalent

0/10

Flux Residue

0/10

ESD

ENVIRONMENTAL

MECHANICAL

CONTAMINATION
I

lonograph
Visual

'I

ASIC
Failure Rate (% 1k Hrs)

0.0018

TIC

Condition C 2K Cycles

0/254

TIS

Condition C 1K Cycles

0/233

85/85

85·C/85% RH 2K Hours

0/382

Steam

121·C 2ATM 336 Hours

0/446

ELT

125·C 1K Hours

0/284

ASIC
E/F 28F010 TSOP

NOTES:
All samples equalJy divided from 3 manufacturing lots.
NR = Not Required if same assembly factory
• = Fully populated card

4-290

infel·

RR·70

APPENDIX A

. 4-291

int:et

RR-70

External Dimensions
3.3:i:O.1 mm

S.4.0iO.1 mm

"

E

.5

c

:i

'"~

I

"

I
I
I
I
I
I
I
I
I
I
I

r-

E

.5

c

:i

'"

IJ
rRONT SIDE

304 •

[J

-I I-

1

.lggggggggggggggggggggggggggggggggg~L_U

68-

3S

BACK SIDE

293007-4

,

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

GNO
03
04
Os
06
07
CE1
A10
OE
An
Ag
As
A13
A14
WE
NC
Vcc

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

VPP1
A16
A1S
A12
A7
A6
As
A4
A3
A2
A1
Ao
00
01
02
WP
GNO

35
36
37
38
39
40 '
41
42
43
44
45
46
47
48
49
50
51

GNO
C01
011
012
013
014
01S
CE2
NC
NC
NC
A17
A1S
A19
A20
A21
VCC

"

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

VPP2
NC
NC
NC
NC
NC
NC
NC
NC
REG1
BV022
BV012
Os
Og
010
CO2
GNO

NOTES:
1. REG = Register Memory Select = No Connect (NC), unused, When
is brought low, PCMCIAlJEIDA standard
card information structure data is expected. This is accomplished by formatting the card with this data.
2. BVD = Battery Detect Voltage = No Connect (NC), unused.

m

Pin Configurations

intel·

RR-70

Pin Description
Symbol

Type

"ame and Function
ADDRESS INPUTS for memory locations. Addresses are internally latched
during a write cysle.

Ao-A21

INPIJT

00-015

INPUTI
OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data
during memory read cycles. The data pins are active high and float to tri-state
OFF when the card is dElselected or the outputs are disabled. Oata is
internally latched during a write cycle.

CE1,CE2

INPUT

CARD ENABLE: Activates the card's high and low byte control logic, input_
buffers, zone decoders, and associated memory devices. CE is active low; CE
high deselects the memory card and reduces power consumption to standby
levels.

OE

INPUT

OUTPUT ENABLE: Gates the carQs output through the data buffers during a
read cycle. OE is active low.

WE

INPUT

WRITE ENABLE: Controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
NOTE: With Vpp S; 6.5V, memory contents c:annot be altered.•
ERASE/WRITE POWER SUPPLY for writing the command register, erasing
the entire array, or writing bytes in the array.
.

, VpP1, VPP2
Vee

DEVICE POWER SUPPLY: (5V ± 5%)

GNO

GR()UND

C01, CO2

OUTPUT

CARD DETECT: The c~rd is detected at C01. 2 = Ground.

WP

OUTPUT

WRITE PROTECT: All write operations are disabled with WP = active high.

NC
BV01, BV02

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.
OUTPUT

BATTERY VOLTAGE DETECT. NOT REQUIRED.

4-293

infel .

RR-70'

Block Diagram
00-015

Os-DIS

I/o TRANSCEIVERS
AND
BurFERS
WP

WE
OE
WP

~--~

00

-17

WE

1

•~I
- - "I\.!RITE PROTECT

-=

-A21
CE2

c!:,

\

SWITCH
Ao-~7

Ao
~

!

OE

ADDRESS
BUFFERS
AND
DECODERS

CEHo CE~'

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4-294

ARTICLE
REPRINT

AR-484

May 1990

PC Standard
in the Cards

BY TOM WOLFE

© 1990 Inlel Corporalion, 1990
Reprinted with permission from EETimes, May 1990

Order Number 295048-001

4-295

AGREEMENT AT HAND FOR Ie-BASED STORAGE MEDIUM

PC standard in the cards
By DAVID LAMMERS

Tokyo - Agreement could be imminent on a Japan-V.S. standard
for the "PC Card," a 2 x 3-inch
IC-based card to be used as a'
removable data-storage medium
for portable computers.
Expectations are high that this
transPacific standard will do for notebook and laptop computers what
MS-DOS, the floppy disk and the
IBM PC did for desktop machines:
allow software to be sold for, and
data to be exchanged over, a medium compatible across a broad
range of portables from a long list
of manufacturers worldwide.
With notebook and low-end laptops expected to constitute half of
Japan's PC market by 1994-and
perhaps a third of PC sales around
the world by then-approval of
the standard is especiaUy important to V.S. computer and software companies. Proponents of
the PC Card concept hope that,
with the standard approved, software vendors will quickly begin
porting applications to the cards
and users here and in Japan will
embrace the new technology.
The PC Card standard is being
forged by the Personal Computer
Memory Card International Asso-

dation (PCMCIA) and the MIT!affiliated Japan Electronics Industry Development Association
GEIDA) , which includes about 40
major Japanese companies. The
70-member PCMCIA includes
nearly aU of the personal com put er industry's movers and shakers,
with IBM, Lotus Development
Corp. and Microsoft Corp. playing particularly active roles.
Today and tomorrow in Seattle, Microsoft will host the May
meeting of the PCMCIA, at which
. members are expected to approve a draft agreed to in Tokyo
on May 10 by PCMCIA members
and the memory card working
group of JEIDA. The agreement
specifies the JEIDA V. 4.0 format, 68-pin card; the DOS file
format; a means for the system to
know. what kind of card it is dealing with; and other hardware and
system-software specifications.
It's expected that Poqet Computer's (Sunnyvale, Calif.) Poqet
PC,a palmtop unit that accepts
the IC cards, will spearhead penetration of the V.S. market.
Dan Stemglass, founder of Databook Inc. (Ithaca, N.Y.), which
manufactures a series of IC-card
reader/writers and programmers,
said: "What's going to drive the

4-296

market first are portable systems, starting with the Poqet. We
stiD have to see how much of the
market will be penetrated by the
handheld-type computers. Then,

FuJitsu's version of the
credlt-card-size 'PC Card.'

PC Card standard drafted
if everyone owns a handheld, IC
cards might be used in desktops." ,
A host of notebook machines
coming to market in Japan is ex·
pected to fuel use of the new
cards there.
Last week at the Japan Busi·
ness Show, NEC Corp., Fujitsu
Ltd. and Mitsubishi Electric
Corp. all introduced powerful new
notebook computers that include
IC readerlwriters compatible with
the new 68·pin standard. Fujitsu
offered a half dozen appliCations in
ROM-based IC card format, along
with various data file cards using
SRAMs.

How standard came about
Tokyo - The people who hammered out the IC card standard
between Japan and the United States described it as an exercise
in quick compromises-and a demonstration that good will exists
in abundance between Japan and America.
Basically, the standard took most of the hardware specifications developed over the past five years by the Japanese and
added software standards prompted by the U.S.'s Personal
Computer Memory Card International Association (PCMCIA).
Fujitsu Microelectronics memory card manager John Reimer
said Poqet Computer executives realized a. year ago that a
standard for the cards
would expand the software
base for their pahntop machine. Reimer-described
as "the. driving force" behind the formation of the
PCMCIA-sent out letters
in June 1989 about the new
association and got quick
acceptance from U.S. companies. About 70 companies joined PCMCIA.
Late last year, the
Americans sent a letter to
the Japan Electronic Industry Development Association OEIDA), an associ· Reimer: Instigator.
ation that focuses on
personal computers. The
JEIDA working committee, already five years in existence, sent
10 Japanese representatives to the PCMCIA's January meeting,
in Dallas.
Japanese and American executives began crossing the ocean
each month, attending each other's meetings. The Americans,
accustomed to voting on issues after a period of discussion,
worried that the Japanese would "want to keep talking, talking,
talking, until they reached a consensus," Reimer said.
Instead, the Japanese accepted U.S, proposals about the pin
lengths for the 68-pin connector; Japanese software companies-including Microsoft Japan, Just Systems and Ascii Corp.provided important input to the software discussions.
-David Lammers

N_ notebook wlIYe
Those A-4-sized systems are in the
6-1b. (2.7 kg) range, similar in size
to the popular "Dynabook" from
Toshiba. One model of NEC's
PC98 Note is also the first built
around Intel's 386SX processor,
partly because it expects that users
of notebook computers will want to
run the same Windows interface
they use on their desktops.
Though the Dynabook does not
include an IC card slot, future
Toshiba systems will. Both the
chairman of the JEIDA working
group and the software subcom·
mittee are Toshiba executives.
. Though several companies are
developing. notebook machines in
the United States, the portable
field here is currently focused on
the larger, heavier laptop PCs,
like those made by Zenith Data
Systems (now part of the Bull
Group), Compaq and Tandy.
But that could change. Accord·
ing to Japanese sources, IBM
Corp. is expected late this year to
introduce a notebook computer,
now under development at IBM
Japan, that would use IC cards
manufactured at a new IBM
plant in Toronto. By using the
PC Card, IBM might try to
leapfrog its competitors and
make a comeback in portables,
just as it's trying to do in workstations. The June meeting of
the PCMCIA will be hosted by
IBM in Toronto.
For now, hopes for the PC
Card's success in the U.S. market
rest mainly with the Poqet computer. Poqet is pioneering IC card
use with versions of Lotus 1·2-3,
an integrated package called
A1phaWorks from Alpha Software
(Burlington, Mass.), and other

4-297

applications. The system it now
uses is upward·compatible with
the new standard.
John Reimer, the Fujitsu Microelectronics (San Jose, Calif.)
memory card manager who
serves as the PCMCIA's chairman,said he got interested in IC
cards because of Fujitsu's investment in Poqet Computer. Fujitsu
is doing back·up manufacturing
for Poqet in Japan and is a card
supplier to Poqet.
Reimer said he expects the
success of Poqet's $2,()()() system
to drive demand for IC cards in
the United States for the time
being. But, he said, ultimately,
"every executive will want to
have some kind of notebook com·
puter," and that will create the
market for IC cards.

Not an expansion card
The PC Card should not be con·
fused with the memory expansion
cards that some vendors offer for
adding DRAM to laptops. Partly
to avoid confusion with these
DRAM cards, PCMCIA uses the
name "PC Card" and has developed a logo that will mark the
cards that comply to the standard.
PC· Cards, rather than being
analogous to add-on memory,
are actually a form of removable
media, like the 3%·inch dis·
kettes being used in today's
laptops. Like floppies, they

NEWS.

Japan/U.S. PC Card standard at hand
not only store programs and data
but will allow dissimilar notebook
machines to share that data,
thanks to the standard. Further,
by using PC Cards, notebook
computers could exchange data
with pocket computers or even
with new versions of the electron,
ic organizers which have sold millions in Japan, but have been
based to date on proprietary card
schemes.
IC cards are seen as the key to
eventually replacing floppy disk
drives in notebook computers.
Ryozo Yamashita, an ASCII Corp.

target date. With the PC Card, he
noted, the system CPU can directly access the memory on the
card itself. "That will eliminate
the huge memory needed on the
main unit," he said.
Once a large installed base of
hardware is on the market, more
software will be ported to PC
Cards, he said. However, software companies are cautious because of the high cost of putting
software into silicon. A 1-Mbyte
ROM card that costs $50-70 now
may come down to half that over
the next year, as 8- and 16-Mbit

Dynabook engineer Teny Moore (left), key figure In standards
development, with president Dan Stemglass and PC Card.
(Tokyo) engineering vice president, attended several PCMCIA
meetings in the United States and
said he grew tired of carrying the
six-pound Dynabook along in his
rucksack.
"With a floppy disk drive in the
computer, there is not much
more than can be done to reduce
the weight. And a floppy drive
consumes a lot of power."
But before the ubiquitous floppy is designed out of notebook
computers, software companies
must port more software to PC
Cards. Yamashita said he believes
the market will be driven first by
the Poqet computer (though he
believes the Poqet keyboard
needs improvement) and later
this year by less expensive portable computers.
"By the end of tins year tbe IC
memory card will be used as the
primary media on pocket-type
computers from many companies," Yamashita said, with the
fall Comdex show in November a

mask ROM chips proliferate. But
compared with distributing applications .on floppies, ROM IC
cards are a big financial risk, especially for the thousands of small
software companies.
Japan's software houses, including ASCII, have a lot of experience selling Nintendo game software stored in ROM, Yamashita
said. But Nintendo software can
sell in millions of units, while the
computer. market is marked. by
higher prices but smaller unit volumes. The big merit of IC card
software, he said, is that it cannot
be copied by individuals, giving
software companies the incentive
to strive for potentially higher
margins.
One other potential hurdle for
getting software into PC Cards
could be settled at this week's
PCMCIA meeting. There, Microsoft and Lotus Development
Corp.; two of the biggest promot. ers of the standard, will try to
work out their differences on how

to implement "execute in place"
(XIP). XIP pennits a small system to run software stored on a
PC Card and access memory on
the same card, rather than relying
solely on the system's memory.
XIP is an important issue for the
optimal execution of large programs adapted to IC cards, such
as Lotus 1-2-3 running on the Poqet system. The issue brings to
the IC card level a bigger issue:
how to get around the 640-kbyte
barrier of the original PC architecture while maintaining PC compatibility, said Yoshinobu Akimoto, an
engineer at Miq-osoft Japan.
Mike Dreyfoos, chief engineer
of Microsoft's MS-DOS division,
who is active in the PCMCIA, and
Jim Prelack, a Lotus Development executive who serves as
president of PCMCIA, are both
said to be taking a "market oriented" approach toward resolving
the snag.
An informal meeting on the XIP
issue, held here May 14, resulted
in some progress, sources here
said. Even without an immediate
agreement on XIP, companies
can take the basic standard and
begin porting software and building IC card-based hardware.
"Both companies [Lotus and
. Microsoft] realize we've got to
get the show on the road," said
Fujitsu's' Reimer.

U.S. to get the Jump
T. Slngeta, a senior staff manager
at Microsoft Japan, said the U.S.
market may adopt the software
cards faster than the Japan market. In Japan, Fujitsu, NEC and
other companies all support proprietary versions of MS-DOS,
making applications incompatible.
That fracture is continuing down
to the notebook and palmtop systems, which will support proprietary versions of MS-DOS.
"The big' issue is not only the
high cost of the [IC card-based]
software, but having to support
different cards for the different
architectures here in Japan," Shigeta said.
He believes the data cards will
sell well in Japan. "The importance of this standard is that notebook-, laptop- and desktop-type
computers will be able to exchange data on the cards."
He predicted small ISVs will
maintain a cautious stance toward
IC card-based software. The lack
of software support hashurt pte-

4-298

vious attempts to market IC cardonly notebook computers, including NEC's "UltraLite," sold in the
U.S. market, Epson's "Note Ex"
ecutive" and Sharp's "Brain."
Asked if Microsoft will port its
applications to the cards, Shigeta
said, "I can't say anything explicit,
but from the level of our activity in
JEIDA and PCMCIA, you can see
that we see a bright·future in IC
memory cards."
Ryosuke Takahashi heads up
the five-person IC card team at
DuPont Japan Ltd. As a neutral
player in between Japan's competing electronics companies, DuPont buys memories, has them
assembled by third-party suppliers and markets the IC cards to
Japan's computer makers. Du"
Pont. also supplies most of the
two-piece. (header and female)
connectors used in the JEIDA format cards.
A 1988 market study done by
DuPont and Nomura Research institute predicted that the IC card
market in Japan would grow by a
33 percent compound average
growth tate, rising to about $1
billion in 1995. That's about five
times larger than the total expected for 1990, and the Japan market
estimate preceded the unexpected joint standard with the U.S .
In about two years, when flash
EPROM-based cards are in wider
use, the price of most of the cards
will drop to half, Takahashi said.
Now, a 512-kbyte SRAM card is
sold to OEMs for about 40,000
yen, or about $240.
Takahashi believes that palmtop-size computers will be the
biggest market for the next couple of years, with most notebook
computers continuing to use floppy disk drives. Beyond that,
some companies may migrate to
IC card-based notebooks, sans
floppy drive.
But other markets will be important. Already, robots and measurement equipment, laser printers, and medical equipment use
ICcards. "My personal view is
the digital still cameras will be a
big market for IC cards in years to
come, replacing film," Takahashi
said. Toshiba and Fuji Film already have a camera on the market that uses IC cards, and Sony
may change from a floppy to a
card based still camera. The FBI
put in a major order for Sony's
camera last week.

ASCII's Yamashita Said a potentiaHy huge market for IC cards
is in distribution of specialized information. A number ofJapanese
software, printing and publishing
companies have initiated the International Card Media Publishing
Association. Stock exchange data
and financial news, train timetables and other fonns of changec
able data could be stored on IC
cards. One idea is to provide
vending machines that would
download data on to a card at a
train kiosk or newsstand.
"When Dash memory gets
cheap enough, then you might
,stop by and download certain'
kinds of news and view it on the
train; information could be persona1ized," Yamashita Said.
The way to look at IC cards is
as the next step in the evolution of
computer media, from paper tape
to magnetic tape and f10ppylhardl
optical disks, and now to a siliconbased media, he Said.
Mask ROMs normally are used
to store software in IC cards. The
market for Nintendo game cartridges has helped drive the price
of a I-Mbyte ROM card down to
about $60 to $70. That may drop
by half over the next year.
Before IC cards become popular the cost of data storag~ cards
must come down, an area where
Dash EPROMs are expected to
playa key role.
"AU of the PCMClA members
exPect that Dash will replace a
good chunk of the SRAM-based
cards," Said Reimer, noting that
Intel Corp., Texas Instruments,

Inc. and Toshiba Corp.-the larger companies in the Dash memory
6eld-are active members of
PCMClA. Fujitsu and other Japanese companies have major Dash
development efforts under way.
William Howe, president of intel Japan, Said IC-card related
product announcements from intel, based on Dash EPROMs, "are
not very far away." Though he
said Japanese semiconductor
comPanies have accelerated their
own Dash development efforts,
they are turning to Intel for Dash
EPROMs to be built into IC
cards.

T

akemae said flash
memories will
make an impact on
card pricing, probably
beginning next year.

Ie

"In the last few months the
interest from our customers in
Dash (for use in IC cards) has
increased by an order of magnitude. It's not just. Company A or
Company B; it's everybody,"
Howe said.
Though flash is considerably
more expensive than EPROM
memory now, Howe said he ex.pects the price 'to come down to
10 to 15 percent above the tags
on EPROMs, and far less than the
price of SRAMs now used in IC
data cards.

Yoshihiro Takemae, a Fujitsu
Ltd. semiconductor manager who
served as chairmim of the JEIDA
hardware subcommittee, said
Dash memories will make an impact on IC card pricing, probably
beginning next year. The PC
Card pin layout scheme reserves
pin No.' 18 for programming the
card, which would accommodate
the 12 volts needed to electrically
rewrite a Dash memory.
While research: continues into
ways in which sectors of a Dash
EPROM can be selectively
erased, Takemae said, "I think
that deletions can better be bandled by the software. People
should think about the format and
handling of the IC memory card
just as they think about floppy
disks now."
The hardware specifications included a write-protect switch, the
position of the battery, a greenyenow-red light system to indicate the strength of the battery,
and a variety of electrical.specifications, aU of which can be obtained from the PCMClA once
the standard is published.
The decision to move from 60pin cards, which had !>een used by
several Japanese companies, had
been agreed upon earlier by the
JEIDA group in its V 3.0 specifications.
The cards are about 3.3 mm
thick, so that four-layer, doublesided cards can be housed. Fujitsu and other companies have
been putting 20 to 24 chips on the
double-sided cards, using TSOP
(thin smaU-outline packages), an
emerging fonn of surface-mount
packaging, Reimer Said.

4-299

Takemae Said the most difficult
issue facing the hardware group
was how to deal with "hot insertionlhot removal," i.e., pulling out
a card while the system is sliD
operating, which can result in data
loss. A major future issue is how
to develop an 110 specification so
that interface cards can be built
into portable computers, "talking
to" fax machines, telephones and
pagers, printers, and other external devices.
Yamashita, of ASCII, and Terry Moore at Databook worked together to develop the META card
interface format, with input from
Dreyfoos of Microsoft.
META is a header format that
tens the system what kind of card
(such as an application or data
card) is in the slot, what kind of
semiconductor memory-and
how much of it-is on the card,
and so on.
"We reaDy have worked hard
so the consumer can just plug in
the card and make it look like a
floppy disk. We want this to be a
consumer product," Stemglass
Said.

ARTICLE
REPRINT

AR-490
August 1990

COMPUTER TECHNOLOGY REVIEW. MASS STORAGE - - - - - - - ' - - - - - - - " ' - - - - - - -

Flash Memory Operates 10-20 Times Longer
by Markus Levy
Major technology changes in
the 1990's will place new
demands on memory devices.
Mainframe computing performance is now available in
a laptop PC, and hand-held
solid-state calculators have
become sophisticated organizers. The convergence of these
two trends has led to the evolution of the notebook PC and the
emergence of Flash memory.
With a minimum battery life
of 20 hours and weight not
exceeding five lbs, the completely solid-state notebook PC
will reliably handle all performance requirements of the
traveler. Flash memory helps
make the design goals of the
notebook computer a reality by
replacing the majority of the
memory technologies in the
system. Psion, a leader in the
notebook computer market,
has created a product in which
Flash memory is used for BIOS, '
OS, and secondary storage. This
completely solid-state, DOScompatible machine weighs
only 4.5 lbs and operates on

eight AA batteries for 25 hours.
To incorporate rapidly improving power management
techniques for battery-powered
systems, the BIOS must be software updatable - remotely over
a modem or with a floppy disk
sent by the OEM. As such, the
EPROM no longer fulfills its
classic role for code storage.
However, designed with a similar memory cell structure
based on ETOX technology
(EPROM Tunnel Oxide), Intel
Flash memory provides equivalent reliability and nonvolatility
with the added advaritage of one
sec, chip-level, electrical erasability (hence the name 'flash').
Flash memory can occupy the
EPROM's socket with minor
hardware modifications, primarily, 12V (Vpp) and write
enable '(W/E) must be supplied
to enable the software controlled erase and program
operations.
lraditionally, when the computer boots up, the operating
system (namely DOS) is read
from the disk and downloaded
to DRAM. Digital Research and

Microsoft offer ROM-executable
versions of DOS. Originally
designed for the unchangeable
ROM, this product now accommodates Flash memory which
can easily be reloaded with
newer revisions without removal from the system. Flashexecutable DOS benefits the
notebook computer because it
reduces the system RAM
required for DOS from 70K to
15K, reflecting both power and
component savings. Additionally, the system bootup is
almost instantaneous, commonly referred to as 'instanton,'
Solid State Secondary
Storage
Solid-state secondary storage
has had the greatest overall
impact on the notebook computer (See Fig). In this environment, the power consumption,
reliability, size, and weight of
the mechanical disk drive is
unacceptable. For example, the
acti.ve and standby modes of the
small form factor (2 1/2-in.), 20
Mbyte disk drive typically consume 4W and 0.5W, respec,

© INTEL CORPORATION, 1990.
Reprinted with permission from Computer Technology Review.

tively. As a comparison, the
active and standby modes of the
equivalent capacity of Flash
memory, consisting of. low
power CMOS circuitry, typically
consume only 0.15W and
0.04W, respectively. Obviously,
for a truly accurate analysis,
other components of the system should be included, but
from the data storage point of
view alone, the Flash memory
disk will operate' 10-20 times
longer than the mechanical
disk on a set of batteries.
Reliability issues will always
exist with mechanical media in
any type of portable equipment
because of shock and vibration,
but it is difficult to perform a
theoretical analysis on this
subject. Suffice' it to say, that
from. an MTBF standpoint (as
measured by disk drive manufacturers under normal operat·
ing conditions), a mechanical
disk will typically run .50,000
hours. A. Flash memory device
(capable of 100,000 erasel
program cycles) should can· .
tinue to function past 1.6 million
hours - a difference of two

Order Number: 295054·001

4-300

COMPUTERTECHNOLOGYREVI~

•

MASSSTORAGE--------------------~----------------------------

Flash Memorv Should Offer 1.6 Million Hr MTBF
orders of magnitude.
Size and weight are also critical factors in the notebook
computer. Two Mbits of Flash
memory is now available in a
thin small outline package
(TSOP) with a height of l2 mm.
Minimally, 16 of these tiny packages can be put into a pocketsized IC memory card (IS,789
cm'vs 2IS,384 cm' for the 2 112in. mechanical disk drive)
to make up a four Mbyte disk,
an adequate supply of memory
for the notebook computer.
Flash memory is not the only
technology used as a solid-state
alternative to .secondary storage. ROM and battery-backed
SRAM driVes are actually more
common because of familiarity.
However, each has inherent
drawbacks. ROMs have historically been used in laptop systems to store unchangeable,
preloaded software programs.
To upgrade with software revisions, the ROM application
hardfile is discarded and a new
card is purchased-an undesirable E!l(pense for the user.
Battery-backed SRAMs enable the flexibility to continuously modify files. SRAMs are
used both as floppy and hard
drive replacements, only where
very low densities are required.
Besides not being practical for
high-density applications,
SRAMs also draw concern from
unpredictable battery life.
Unlike the ROM drive, flash
memories 'can be reprogrammed many times. Unlike
SRAMs, the single transistor
memory cell of flash (compared
to 4-6 transistors for SRAM) is

Fig Whereas in Workstations Flash memory is used as cache for the OS and code. the laptop uSes Flash memory for direct
execution.

very scalable for photolitho- on linked-list techniques, this
graphic processes, promoting ,Dos-compatible file system"
very high density devices. In an with superior performance over
environment where high den- the mechanical disk, takes
sity is synonymous with sec- advantage of the chip-level
ondary storage, flash will out- erasability of Flash memory.
sell and outlast volatile SRAMs
Although we have only disbecause of cost and reliability cussed Flash memory applicaadvantages.
tions in the notebook computer,
its usage spreads well beyond.
Using Flash memory
BIOS modification in desktop
The adoption of Flash mem- computers is' also unavoidable
ory in a solid-state disk comes due to increasing system comwith the design challenge of plexity. Primarily aimed at fixinterfacing a bulk-erasable ing bugs" this technique also
memory with a file system alleviates compatibility probrequiring byte-level alterability. lems that might arise from the
The simplest solution is to use a installation of the myriad of
ROM-like approach and use the add-in boards and software
drive as an application hardfile packages. In addition, the OEM
with the extra benefit of being can promote upgrade service
able to erase and reuse the as a market distinction, as done
disk. Microsoft has made major by NCR and Olivetti.
advances over this approach by
Flash memory ,disks are usedeveloping a special file system ful as application caches in
it calls Flash File System. Based . high-end systems because of

4-301

'their. nonvolatility and RAMdisk equivalent access speeds.
Many types of industrial equipment are using Flash memory
for code storage and data accumulation, replacing all forms of
disk drives, both mechanical
arid solid·state.
Flash memory will continue
to play a dominant role in the
evolution of the notebook computer as well as every other
application requiring a nonvolatile, reprogrammable, reliable, high density, and low cost
memory. The flexibility of this
new memory technology is
driving costs down and generating an important alternative to
disk memory. •
Markus Levy is technical marketing engineer at Intel Corp.
(Folsom, CA).

ARTICLE
REPRINT

AR-498

Nonvolatile,
in-circuitreprogrammable
•
.memories

C

ompute. r designers abandoned
core memory in the early
1970s because silicon memory
(RAMsand EPROMs) offered equal
or better performance for less
money. However, system designers
also lost something in the bargain.
Semiconductor RAMs furnish vola.
tile memory; they remember only
as long as they receive power.
EPROMs need no power to retain
their contents but you can't reprogram an EPROM without first erase
ing it for 20 minut.es under a UV
lamp. Consequently, disk drives
now fill the nonvolatile memory'
needs of many computer systems.
Unfortunately, disk drives also
have liabilities. Tiley are much
larger and heavier than ICs, they're
more easily damaged and slower
than semiconductor memory, they
require a relatively complex disk.
controller, and they consume a lot
of power: Disk drives may make no
sense at all in small, portable, or
embedded floP-based systems. Recognizing the inherent limitations of
EPROMs and disk drives for nonvolatile storage, the makers of parallel-access, in-circuit-reprogrammable, nonvolatile memory ICs
plan to restore non volatility to your
processor's main memory, as in the
days' of core. These vendors are

Vendors of nonvolatile,
iil-circuit-reprogrammable,
. semiconductor memories want you to replace
electromechanical memory components, such as
DIP switches and disk
drives, with chips. To
spur your move toward
silicon, Ie vendors are
rapidly expanding nonvolatile memory capacities beyond 1M bits
and slashing the
cost p~r bit.

Steven H Leibson,
Senior Regional Editor

© INTEL CORPORATION, 1991
Reprinted with permission from EDN

pushing device capacities beyond
'1M bits (to 16M bits for hybrid modules) and dropping costs to $101
megabit as a' means of swaying you
to their way of thinking.
When you decide to use some
form of nonvolatile memory IC in
your next design, you immediately
confront a. range of technology
choices. You can pick from batterybacked static RAMs (SRAMs), non-.
volatile RAMs, EEPROMs, and
flash EEPROMs. Your choice will
depend on several factors including
how much nonvolatile memory you
need, how often you need to change
the nonvolatile memory's contents,
and how much you're willing to
spend. The selection guide in Table 1
can help you choose the type of device that best suits your needs.
Choosing a particular device within
a given device type then becomes
a somewhat simpler problem. Unfortunately, none of the nonvolatile-memory technologies listed in
Table 1 offers the ideal nonvolatilememory characteristics of unlimited
endurance,' fast storage times, and
low cost. All exhibit some form of
wearout failure and all require that
you make soine compromises.
If you need nonvolatile storage
that closely mimics the infinite
read/write characteristics of RAM,
Order Number: 295062-001

4-302

then battery-backed SRAMs may
well be your best choice. These devices work just like SRAM because
they're built with SRAM chips. In
addition t'o the RAMs, these devices incorporate one or two batteries and a power-management circuit
that switches over from system
power to battery power when necessary.
Table 2 lists battery-backed
SRAMs offered by two vendors:
Dallas Semiconductor and SGSThomson. These companies offer
products whose capacities range
from 2k to 128k bytes. Some of the
products listed also incorporate an
electronic time-of-day clock and
calendar. The products' integral battery allows the clock and calendar
to keep track of the time and date
even when a system is turned off.
However, the integral battery is
not just an asset, it is also the technology's main liability. Batteries
die. Table 2 lists the minimum number of years you can expect the battery to last for each device. Most
of these products retain data for
about a decade. After the battery
is drained, the SRAM will operate
as a RAM, but the product's nonvolatile abilities disappear.
The batteries in battery-backed

The battery-backed
SRAM's integral
battery is not only
an asset, it is also
the technology's
main liability.
SRAMs cannot be recharged, so
you must replace the entire device
to restore nonvolatile memory to
your system. If you prefer to provide your own battery (perhaps one
that's rechargeable), SGS-Thomson
offers the MK48C02, which is a 2kbyte SRAM with integrated power
management. The' device has separate battery pins, which allow you,
to connect a backup power source
to the RAM in addition to the normal power supply. The 48C02 costs
less than $10 (1000).
Other types of nonvolatile semiconductor memories based on floating-gate electron storage (nonvolatile RAMs, EEPROMs, and flash
EEPROMS) feature much longer
data retention than battery-backed
SRAMs. Although most of the data
sheets for these floating-gate devices claim 10-year data retention,
the technology is actually much better. In fact, Xicor's nonvolatile

4-303

RAM and EEPROM data sheets
specify 100-year retention times.
Most nonvolatile-memory vendors
will readily negotiate longer retention-time specs, if your application
requires them. Apparently, many
of these vendors don't want you to
think that you're paying extra for
the longer retention' specs so they
use the de facto "industry standard"
spec of 10 years.
You should also be aware of the
difference in retention-time specifications between floating-gate memory products and battery-backed
SRAMs. The retention-time clock
for floating-gate memories starts
when you store data in the IC. For
battery-backed' memories, the retention-time spec refers to the
elapsed time since the device was
, first powered up.
If the limited life of a battery concerns you, but you still need infinite
read/write capabilites, consider using nonvolatile RAM for your nonvolatile memory. By merging
SRAM and EEPROM arrays on one
chip, nonvolatile, RAMs do not require a battery and provide many
of the same advantages provided by
battery-backed SRAMs. While the
system supplies power, the nonvolatile RAM's SRAM array pro-

Nonvolatile, in-circuitreprogrammable memories

vides unlimited read/write capabilities.· At any time, you can transfer
the entire contents of the RAM array to the EEPROM array with one
.command. You can also transfer
information stored in the nonvolatile RAM's EEPROM array to its
RAM array with one command. In
addition, nonvolatile RAMs automatically transfer their EEPROM's
contents to their RAM array when
power is applied.
Is 27 years long enough?
Like any floating-gate memory
technology, the nonvolatile RAM's
EEPROM array accepts only a limited number of changes before it To hold the BIOS In Its VH-286 notebook PC, Alrus Computer Corp (Chicago, ILl uses a flash
will fail. However, as Table 3 EEPROM from Seeq, which allows the company to change Its BIOS over the telephone ,Ia a
shows, that limit is at least 10,000 modem.
storage cycles. If you only transfer
the RAM array to the EEPROM
Unfortunately, if you use the to design, so you may need to initiarray when shutting the system nonvolatile RAM to save data prior ate transfers more frequently in
down, that limitation should not to the loss of system power, you'll case the system's power vanishes
represent much of a problem. For need circuitry that can foresee the unexpectedly. If so, 10,000-cycle
a product that is switched off once power loss sufficiently early enough and even lOO,OOO-cycle endurance
a day, the 1O,000-cycle nonvolatile to complete the data transfer from may become a real limitation. HowRAMs should last more than 27 . RAM to EEPROM. Such predictive ever, if you only need to store infreyears.
circuitry can be tough or impossible quently updated items, such as con-

4-304

figuration information or calibration
data, the nonvolatile RAM may be
a perfect choice.
Nonvolatile RAMs meld the infinite read/write capabilities of RAM
with the nonvolatile stqrage of
EEPROM. This combination offers
more flexibility than other types of
nonvolatile semiconductor memory,
but you must pay for this flexibility.
Smaller nonvolatile RAMs only cost
a few dollars, so they are frugal replacements for DIP switches, jumpers, and other mechanical contriv,ances often used to store small
amounts of semipermanent data on
a board, However, the nonvolatile
RAM's relatively hfgh cost per bit
makes it unattractive for large storage requirements. Further, the inherent complexity of the nonvolatile
RAM's combined static-RAMI
EEPROM cell limits the amount of
memory that an IC vendor can fabricate on one IC using nonvolatile
RAM cells. For these two reasons,
you can buy only relatively small
nonvolatile RAMs. Siintek's 16kand 64k-bit parts offer significantly

For a product that is
switched off once a
day, the 10,000·
cycle nonvolatile
RAMs should last
more than 27 years.
more storage space than nonvolatile
RAMs from other vendors. Even
so, 8k bytes doesn't seem to go as
far these days as it once did.
If you can restructure your design requirements so that you don't
need unlimited read/write capabilities, you can conceptually eliminate
the nonvolatile RAM's SRAM.
You then end up with a part that
is all EEPROM. Full-featured
EEPROMs offer more capacity at
a lower cost per bit thkn nonvolatile
RAMs. Table 4 lists a large sample
of available full-featured EEPROMs.
(N ote: Table 4 lists only bit-parallel
EEPROMS. EDN plans to cover
serial EEPROMs later this year.)
Restructuring your design requirements can be easier than you

4-305

might think because a full-featured
EEPROM differs from an EEPROM
array of a nonvolatile RAM in one
key aspect: You can change individual storage locations in a fullfeatured EEPROM independently.
Consequently, you can write to one
storage cell of a full-featured
EEPROM several thousand times
without reducing the endurance of
the device's other memory locations. So, if your application
- changes stored information frequently, but doesn't change the
same locations each time, the relatively limited endurance of fullfeatured EEPROMs may pose no
problems. Alternatively, if you
don't need to use an EEPROM's
full capacity, you can adopt a
scheme that uses only part of the
EEPROM's memory until you near
the endurance limits and then
switches to a different section of the
device. One of the EEPROM's memory locations can serve as a pointer
to the section currently in use.
Nonvolatile RAMs can be faster
than EEPROMs for mUltiple-byte

Nonvolatile, in~circuit·
reprogrammable memories

storage operations, but you can
overcome this problem as well. Because the nonvolatile RAM fills its
entire EEPROM array in one storage cycle, it has a high "effective
storage rate" per byte. Some dataacquisition and real-time processing
applications that use nonvolatile
storage to record data at periodic
intervals can't tolerate the milliseconds-long intervals between each
store operation if the storage time
exceeds the sampling interval. Nonvolatile RAMs circumvent this
problem by allowing the application
to accumulate data in the IC's RAM
array and then store all of the accumulated data in one operation.
Pages save storage time
Some full-featured EEPROMs
have page buffers that can store a
contiguous page of memory locations in one operation. EEPROM
. page sizes range from 32 to 128
bytes; Using the page-write feature, you can accumulate a page
worth of data and then store that
page in the EEPROM in about the
same time required to store 1 byte.
The full-featured EEPROM's page
buffer, therefore, provides advantages similar to those of the nonvolatile RAM's RAM array.
This page-write feature works
similarly for all vendors' full-featured EEPROMs that have page
buffers. The EEPROM senses the
first write cycle and starts an internal timer. If another write cycle occurs before the timer reaches a predetermined value (usually 100
fLsec), the additional byte enters
the page buffer, the timer resets,
and the EEPROM postpones the
actual storing of the information in
the EEPROM array. Thus you can
quickly fill .the EEPROM's page
buffer without activating the milliseconds-long storage cycle.
When you stoP. writing to the
page buffer, the timer times out and
the EEPROM stores the entire

Fig 1-Two EEPROM sections allow this Xlcor XC88C64 to store data and provide read capability
simultaneously. This feature may allow you to reduce the number of memory devices In your
design to one.

page in one operation. This scheme
effectively reduces the time required to store an individual byte
by the reciprocal of the page size.
For example, if an EEPROM stores
64 bytes from its page buffer in one
cycle, the "effective" time required
to store 1 byte is 1/64 of the pagewrite storage time.
You can't use just one
Most full-featured EEPROMs
have another shortcoming that complicates their use: They don't respond to read cycles while periorming a store operation; the
"'EEPROM's contents become inaccessible for several msecs at a time.
If you store executable code in an
EEPROM with this trait, your
processor will not be able to fetch
instructions from the EEPROM
while it is storing information. Consequently, you cannot use just a
full-featured EEPROM to store
your code in systems that modify
the code space because access to
the code will be interrupted for
long periods of time. You can solve
this problem by combining an
EPROM and an EEPROM, or
two EEPROMs. If you use two
EEPROMs, be certain to initiate
4-306

store operations in only one device
at a time. You can also solve this
prob lem using one of Xicor's
X88C64s, which incorporates two
independent EEPROM arrays (Fig
1). This device allows access to one
of its EEPROM arrays while it is
storing data in the other.
The X88C64 represents the latest
step in the evolution of full-featured
EEPROM design. 'Early EEPROMs
were hard to use because they in"
corpora ted no address or data
latches to hold values during the
iong store operations, they required
high programming voltages, they
were sensitive to power-supply
transitions when a system was powered up or down, and they required
external timing circuitry or software to control the store cycle.
As the IC vendors developed expertise with EEPROM technology,
they eliminated these design obstacles by adding circuitry to. the
EEPROMs.
However, the circuitry added for
each new feature also adds cost to
the device. Because of their cost per
bit, full~featured EEPROMs pose
no great threat to disk drives. By
paring the full-featured EEPROM
to the barest essentials, many ven-

dors of full-featured EEPROMs
now offer a relatively new type of
device, the flash EEPROM, which
will gi,ve both EPROMs and disk
drives some competition. Table 5
lists flash EEPROMs offered by
some sources.

To make flash EEPROMs inexpensive, some IC designers remove
all circuitry that isn't absolutely
necessary. You get a less exp!,)nsive
memory IC, but you also assume
more responsibility for programming and erasing the device. For

4-307

example, many flash EEPROMs
lack on-chip charge pumps and require an external 12V source for
programming and erasing operations. Full-featured EEPROMs and
flash devices from Atmel, Catalyst,
and Texas Instruments generate

Nonvolatile, in-circuitreprogram mabie memories

the necessary programming and
erase voltages internally.
You can view the requirement for
an external supply of 12V as both
. a liability and an asset. Certainly
it's something extra that you must
supply. However, you don't neces-

sarily need or want to design that
extra power supply into your product. If you want to allow flash
EEPROM programming only under
certain, controlled conditions, you
can put the 12V supply in a programming station instead of the

4-308

product itself. A cable can carry the
12V along with the programming
signals. This scheme ensures that
no inadvertant device programming can occur while your product
is in use.
To save transistors, most flash

Nonvolatile, in-circuitreprogrammable memories

EEPROMs also lack the circuitry
which allows you to erase individual
locations. When you erase them,
they erase completely. However,
you don't always need to erase a
flash EEPROM before writing to
it. You can always write to an
erased, but as-yet-unwritten, location, which results in'a write time

comparable to that of a full-featured
EEPROM. However, once you've
written to a location, you must
erase most flash EEPROMs entirely before you can rewrite that
same location. Thus the flash
EEPROM's rewrite time can be
very long indeed.
.Flash EEPROMs from Catalyst,

4-309

Philips Components-Signetics,
Seeq, and Texas Instruments allow
you to erase individual memory sectors and Atmel's flash products
(dubbed PEROMs for programmable, erasable ROMs) automatically
erase a location before writing new
bits into that .location. Sector erasure cart save your application time

Nonvolatile, in-circuitreprogram mabie memories

because most flash erasure algo'rithms require you to write zeros
into each location before erasing the
part. Each write operation takes
hundreds of ....secs or msecs to complete, so writing to the smaller
number of locations contained in a
sector can mean faster erasure
times.

one piece of code that can program
and erase several types of flash
memory. When you're implementing the programming. and erasure
algorithms, you must be careful to
plan for inadvertent resets, long delays caused by interrupts, and any
othereventswhich may distract the
host CPU and disrupt the proper
timing of flash operations. Remember, failure to time the erasure
properly can permanently damage
some flash EEPROMs.
Despite these liabilities, you

will still want to consider flash
EEPROMs for your nonvolatile
memory requirements because they
cost less per bit than the other
types of nonvolatile, in-circuitreprogrammable semiconductor
memories. The cost for 1M-bit flash
memories has dropped by a factor
of 10 inthe past year and most flash
EEPROM vendors state that they
will overtake the nonvolatile-mem- .
oryprice leader, the EPROM, in
the near future. In fact, some computer manufacturers, such as Airus

Erase flash EEPROMs carefully
Writing zeros into each memory
location charges each of the flash
EEPROM's memory cells to the
same electrical potential (a charged
cell represents a logical zero) so that
subsequent erasure will drain an
equal amount of free electrons from
each cell. Failure to equalize the
charge in each flash-EEPROM cell
prior to erasure can result in the
overerasure of some cells by dislodging bound electrons in the floating gate and driving them out.'
When a floating gate becomes depleted in this way, the affected
transistor can RO longer be turned
off; overerasure literally destroys
some flash EEPROMs. Flash
EEPROMs from Seeq are not sensitive to overerasure because the devices' split-gate cell design inherently precludes such problems. As
a result, Seeq's flash EEPROM erasure algorithm does.not require you
to write zeros to all locations before
erasing.
Most flash EEPROMs also lack
built-in timing circuits so your host
CPU must time the programming
and erasure algorithms. This feat
isn't always as easy as you may
think. Fig 2 illustrates the complexity of Intel's programming algorithm. FlashEEPROMs are relatively new, so the algorithms for
programming and erasing the parts
vary from vendor to vendor. However, there is an industry-standard
identification sequence for flash
EEPROMs, so your software can F112-Tlle fllsh EEPROM's.lo. Plrt cost d.lIl.ds .Iotlle.r prlc.: Til., r,,,llr•• lIost CPU to
determine what vendor's part it's e.ecate I fllrl, cOllpll. prlllr.lll1ln, 111.rltlili IS IIIlstr.ted II, tills pro,r••• II, fl••curt
dealing with' if you want to write for Iltel's 28F010 1M·blt flisil dewlce.

4-310
i

Nonvolatile, in-circuitreprogrammable memories

(Chicago, IL) and Solbourne (Longmont, CO), are already using flash
EEPROMs instead of EPROMs to
store executable code in their products. The cost advantages of incircuit reprogramming already outweigh the part-cost differential between EPROMs and EEPROMs if
the EPROMs must be changed just
once. The labor cost incurred by
opening a product and changing the
EPROMs tilts the balance in favor
of flash memory.
In addition, flash EEPROMs allow you to eliminate the IC so~ket
that you often use with EPROMs
just in case you need to change your
code. Elimination of the socket further reduces the parts-cost difference between EPROMs and flash
EEPROMs and boosts system reliability because sockets can be one
of the least reliable parts of a
system. You can solder flash
EEPROMs directly onto your circuit board and still accommodate
code changes through in-circuit
reprogramming.
EPROM replacement represents
a big market for flash EEPROMs
because all IJ.P-based and many
microcontroller-based systems contain at least a few EPROMs that
flash devices can replace one for
one. However, flash EEPROM vendors, such as Intel and Toshiba,
have set their sights on an even bigger market. They will eventually
replace. a large number of disk
drives with flash EEPROMs as
well. At first glance, that goal
seems more like an impossible
dream than a realistic marketing
plan. Disk drives are well established as the storage medium of
choice for a range of computer systems. So was core memory before
. semiconductor RAM appeared. No
. technology in the electronics industry lives forever.
To overtake disk drives, flashmemory vendors must first overcome a few obstacles. For example,

flash EEPROMs do not exactly
match the characteristics and capabilities of disk drives so they cannot
exactly replace them. Read/access
times are much faster for flash devices than for disk drives, which is
a real advantage. Storage times can
also be much faster for flash
EEPROMs, but they can also be
much slower if you need to erase
them before writing new information. hi addition, flash EEPROM
vendors aren't yet. ready to match
the low.cost per bit you achieve
with disk drives. However, they
are preparing for the battle.
As part of that preparation, Intel
recently introduced two plug-in
memory cards based on its flash
EEPROMs. The company's 1Mbyte iMC001FLKA and 4M-byte
iMCOO4FLKA cards measure 85.6 x
54 x 3.3 mm and conform to the 68pin' specification developed by the
Personal Computer Memory Card
International Association. Because
memory cards do not work like disk
drives, Intel has worked with Microsoft (Redmond, WA) to develop
a FlaSh File System that allows a
DOS~based computer to store and
retrieve files from Intel's memory
cards. The 1M- and 4M-byte cards
sell for $298 and $1198 (1000),
respectively. A developers' kit con,taining a 1M-byte memory card, an
IBM PC interface board,and an
evaluation copy of Microsoft's Flash
File System costs $499.95. At today's prices, flash EEPROMs
clearly do not threaten disk drives
for most applications. However, if
your design must meet rugged or
low-power requirements, these
memory cards give you a viable
alternative to consider.
As usual, IC technology refuses
to stand still. In the past year, flash
EEPROM prices dropped by an order of magnitude.. That change occurred without any increase in device density. As flash EEPROM
vendors start doubling and redou4-311

bling device capacities, they plan to
drop the cost-per-bit of their products until they compete with disk
drives. If this plan still seems
overly ambitious to you, consider
this: More than one IC vendor plans
to make the flash EEPROM its IC
technology driver in the 1990s.
ElM

AR-7bO

ARTICLE'
REPRINT

FLASH
MEMORY CARDS
This breakthrough technology enables the mass production of a cost-effective,
high-density in-system alterable nonvolatile memoI}'.

alterable nonvolatile memory.
This ideal combination of characteristics provide the basis for a memory
card that redefines the functionality
and performance of portable PCs and
equipment. ,Enter the flash memory
card. (See Figure 1).

What About. Disk
Technology?
From harid-held' and notebook PCs
to data collection terminals to
calculators, there exists the need for a
solid-state maSs storage technology
that consumes less power, weighs
less, lasts longer and provides higher
performance than. disk-based technology. A high-density flash memory card
provides these advantages over small
form factor hard disk drives. Figure 2
compares Intel's 4MB Flash Memory
Card with a 2.5"Hard Disk Drive.
The disk-to-DRAM or SRAM serial
download process becomes one of the

P

ortable computer and handheld
equipment designers are
continually called upon to
develop products that have
the same functionality and perform·
ance of desktop systems. At odds with
these market requirements are the
system characteristics of small size,
light weigh~, low power consumption,
high reliability and ruggedness.

Aboutthe Author:
Typically, it is the memory storage
media of these systems that has the
largest impact on system functionality
and performance.
A solid·state memory technology
that addresses these seemingly
competing . requirements is flash
memory. This breakthrough technology enables the mass production of a
cost-effective, high-density in-system

© 1991 INTEL CORPORATION
Reprinted with p.ermission from Memory Card Magazine, MarchiApril1991

4-312

Lou Hebert is the Senior Product
Marketing Engineer in the Flash Memory
Operation of the Memory Components
Division. of Intel. He has been involved in
IC-related work for 10' years, the last 5
of which have been with Intel. Hebert
received his BSEE Degree, from the
University of Californiilat Santa Barbara
in 1980, and an MBA Degree from
California State University at Sacramento
in 1985.

Order Number 295065-001

Better Solution Than
Other Solid-State
Alternatives

ADVANTAGES OF FLASH MEMORY CARDS VS. HARD DISK DRIVES

•
•
•
•

•
•
•

Fjgure2.~

Characteristic

Flash Card

Performance

250 nanoseconds

2.5" Hard Disk Drlva
20 miliseconds

Power (Actl.... e/Standby)

250mW/SmW

3W/SQOmW

Weight

28 Grams

150 Grams

Size

0.95 Cubic Inch

6 Cubic Inches

Mechanical Shock

>5005

5Gs

Reliability (MTBF)

1 x 10 'Hours

1 x 10 'Hours

____________________________________________

largest performance inhibitors. Portable disk-based systems incur an
additional performance hit when disk
drives are powered down and then
brought back up again to conserve
battery power. Disk seek and access
times increase when power management software idles disk drives to save
precious system battery life. Using a
flash memory card as a ROM-disk or
application cache increases readperformance by a factor of more than
100 times. In addition, a flash memory
card allows for execute-in-place (XIP)
for code execution and data reading.
Here, the CPU takes advantage of
flash memories parallel architecture
and random access to execute code
directly from the flash memory card.
This architecture increases performance of low-end systems.
Power consumption is one of the
most important design factors for
portable, battery-operated PCs and
equipment. Flash memory cards
consume hundreds of miliwatts of
power in the active mode compared to
watts for disk drives .. Flash memory
cards consume less power in the
standby mode and power-up much
quicker into the active mode. Using
low-power CMOS technology provides
the designer with the option of
designing in smaller commercial
batteries or providing longer operating
periods with -larger, rechargeable
battery packs.

~

Some portable applications simply
cannot accommodate the weight and
volume consumed by a conventional
disk drive. In contrast, flash memory
cards are approximately one-fifth the
weight and consume one-sixth the
volume of the smallest hard disk
drives.
Lastly, ruggedness is a very
important reliability concern, especially in the portable environment.
Mechanical by nature, disk drives wear
out faster than solid-state technology.
Being solid-state, flash memory cards
tolerate a larger mechanical shock and
operate longer than disk drives by at
least a factor of ten.

Other existing solid-state cards
(SRAM, OTP/EPROM, EEPROM)
already address the disadvantages of
disk-based technology. However, the
other memory card technologies do
not address all of the requirements of
the portable computing market. Why
then, are flash memory cards more
beneficial? The flash memory card
provides the best combination of
attributes not available from other
solid-state memory technologies.
These characteristics include highdensity, low power consumption,
rewritability, nonvolatility, costeffectiveness and the ability to store
both code and data. It is this
combination of properties that enable
the design of higher performance
systems with more functionality.

Different Approaches
Lead to System Level
Tradeoffs
There exist approximately four
major approaches to flash memory
technology: 1) Intel's ETOXTM
(EPROM Tunnel Oxide) approach, 2)
the triple-poly approach, 3) the
stepped gate approach and 4) the
tunnel oxide approach. ETOX and
stepped gate are based on EPROM
technology, Tunnel Oxide is an

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______________________________________.______

4-313

~

EEPROM derivitive, and Triple Poly
is a hybrid of several technologies.
Also, ETOX is in high volume
production today. Figure 3 illustrates
the characteristics of these four flash
. memory technology approaches.
Flash memory or Pseudo Flash
memory technologies require algorithmic software control for erase!
write operations and cannot perform
individual byte-alterability.
Differences between the various
approaches lie with cell size, erase and
write times and algorithms, power
supply requirements and endurance
(number of program and erase cycles).
Tradeoffs existing between these
variables have a large impact on
overall system functionality and
performance. Thus, the designer must
carefully analyze these differentia tors
to determine which technology best
meets the requirements of the target
application.
For example, larger applications
programs suggest higher-density mass
storage. The smallest cell size and the
least amount of overhead circuitry on
the silicon chip· will provide the most
cost -effective, high-density memory
device and card. Intel's ETOX
approach (5-volt read!12-volt erase!
write) provides the smallest flash
memory cell size when compared to
the alternative technologies. The
stepped gate, tunnel oxide and
triple-poly approaches have larger cell
sizes than the ETOX approach. These
approaches achieve the same density
levels over time, but at a larger
die-area and thus cost penalty.
Tradeoffs come with density as
well. The ETOX, stepped gate, and
Triple~Poly approaches require a V1'1'
12-volts for era.se!write operations at
the cell level. This requires a 12-volt
power supply or some form of DC to
DC 12-volt conversion. Though
12-volts seems inconvenient, economics show this technique to be the" most
cost-effective. Indeed, the cost of the
12-volt power supply amortizes
quickly when using large amounts of
mass storage memory.
The five-volt-only tunnel oxide
approach provides convenience, but
limits density on each individual

device. The approach uses on-chip
charge-pumps to convert systemsupplied 3- or 5-volts to an even
higher internal voltage (18-22 volts)
than the fixed,
lower 12-volt
techniques. The on-chip charge-pumps
reduce usable space for additional
memory cell locations for a given
device area. This, in tum, reduces
overall density capability and lowers
cos t-effectiveness for a given photolithography. Software write-protect
schemes consume additional area
offsetting the 5-volt benefit. In
essence, the combination of larger cell
sizes, on-chip charge pumps and
software write-protect circuitry limit
memory device and thus, memory
card density.
Lastly, flash memory cards used for
data recording and data file storage
require high endurance or cycling
capability (the ability to erase and
rewrite memory card contents many
times). The key to high endurance lies
with the quality of the tunnel oxide,
the magnitude of the electric field
placed across the tunnel oxide and
whether or not the cell erases and
writes through the same oxide region.
The stepped gate and tunnel oxide
approaches perform erase and write
operations through the same junction.
The triple-poly and tunnel oxide
approaches use high voltage (18-22
Microsoft's Flash File System
operates as a redirected drive under
ROM-executable MS-DOS. More efficient than disk-based sectoring, this
filing system Uses a linked-list structure
that distributes files and locator pointers
throughout the entire flash memory
card. This, in tum, optimizes the use of
the available memory locations. Interfacing flash memory technology into the
DOS world allows access to the huge
library of DOS application software.
Figure 4 illustrates a system implementation model interfacing Microsoft's
Flash File System to a flash memory
card.
This marriage of innovative filing
software and flash memory card
technology lays the foundation for
_powerful system architectures that do
not have to rely on disk technology for
high-density nonvolatile storage.

4-314

volts) at the cell level placing higher
stress across the charge transfer
junction. These factors increase the
probability of oxide wearout over time
and reduce endurance capability.
.Intel's ETOX approach erases and
writes through separate junctions arid,
with 12-volts, places a lower electric
field across the oxide. The 12-voltinduced electric field reduces the
stress on the oxide junction orders of
magnitude less than the triple-poly or
tunnel oxide approaches .
Designers need to weigh the pros
and cons of each flash memory
approach as they relate to the'
requirements of the target application.
Further, the approach selected will
effect system implementation.

. Straightforward System
Implementation
In the memory card form factor,
flash memory excels in four application
areas: 1) Updatable application and
firmware code storage, 2) Data
acquisition and recording, 3) Data file
and data table storage and 4) as a code
and data transport media between host
and target systems. Given the
advantages provided by flash memory
cards, how do designers implement
flash memory cards lnto . today' s
portable designs?
Applications that require memory
.card removal for transport to another
system ·need a standardized interface.
The PCMCIA!JEIDA (Personal Computer Memory Card International
Association!Japanese Electronics Industry Development Association) standards organizations prescribe such a
standard for interfacing solid-state
memory and 110 cards. Defined as a
68-pin hardware interface, today's
versions of the standard allow for
SRAM, ROM and FLASH memory
card densities up to 64MBs. 'Systems
. can distinguish between these cards
via a Card Information Structure (CIS)
stored on each individual memory
card.
The level of participation in the
standards committees by major
systems, hardware and software
companies lends credence to the

standards effort and reduces risk for
those implementing the standard. The
interchangeability of the three different types of memory cards, along with
an upgrade path, reduces risk for
OEMs as well as end-users.
OEMs implementing the PCMCIAI
JEIDA interface into a design incur low
cost as well. Indeed, the OEM need
only supply interfacing hardware and
software for the flash memory card.
The compatibility of memory interfacing within the PCMCIA/JEIDA
standard leaves the option open as to
which density of flash memory card
best fits the application.
Hardware implementations also
require software drivers (erase and
write algorithms) that· allow the
system to erase and write to the flash
memory card. These low-level software drivers interface the system bus
and higher-level operating software to
the flash memory card via the
PCMCIA/JEIDA hardwflre interface.
PCMCIA/JEIDA specifies unique
pin length assignments for protective
power supply sequencing, allowing
"hot" insertion. For those designs
implementi~g 12-volt power supplies,
the 12-voltpower supply can be
. switched on and off to conserve
battery life. Some flash memory cards
provide a Vpp lockout feature that
provides code/data protection while
power supply levels stabilize.
File management schemes, such as
Microsoft's Flash File System, allow
the storage and retrieval of data files .
on flash memory cards in MS-DOS'
based systems. (See sidebar.)

SYSTEM IMPLEMENTATION MODEL

(

(
I

ROM EXECUTABLE oos
FLASH ALiNG SYSTEM
(REDIRECTED DRIVE)

I

HAROWARE DEPENDENT LOW·LEvel DRIVERS

1_ _
I

I

APPLICATION SOFTWARE

SYSTEM BIOS SOFTWARE

_

HIW !HTERFACE: PCMCIAlJEIDA 88-PIN

I

j

FLASH
MEMORY
CARD

Figure 4. L-____________________________________________

memory cards should approach
low-density disks drives sometime in
the 1996 timeframe. To illustrate,
figure 5 shows the OEM price
comparison between flash memory
cards and small form factor hard disk
drives at the 40MB density.

The Solid-State "Disk"
Technology of the Future
Cost -effective flash memory cards
used as mass storage may very well
change the architecture of the PC as it
is known today: Flash memory cards
provide the "dream come true" for

disk-based users: a removable hard
disk or, from another viewpoint, a
high-density floppy disk. The additional benefits associated with solidstate technology allow for new levels
of performance and functionality in
notebook PCs and portable equipment.
Indeed, with ever-increasing densities
and 'steep cost-learning curves, flash
memory cards provide a breakthrough
in the development of revolutionary
new products.
0
• MS-DOS is a registered trademark of
Microsoft Corporation.

FLASH MEMORY CARD VI. MINI HARD DISK DRIVE
40 MByte Capacity

Can Flash Memory Cards
Catch Disk Technology?
Moving notebook PC and portable
equipment designs to the next level of
functionality and performance requires
". a removable solid-state mass storage
medium. With the ideal combination of
attributes, flash memory cards extend'
the capabilities of portable disk-based
designs. Further, solid-state technology scales at a faster rate than
disk-based technology allowing highvolume learning .and· cost reduction:
As such, the density and. cost of flasq

'00

1994

1995

1996

1997

Figure5.L-_______~
__""_'_~
__~_~_'~
___·_I,"_~_~
__· ____________________~

4-315

AR-701

ARTICLE
REPRINT

eXecute-ln-Place
Programs stored in cards can be executed directly by the processor when the
appropriate mapping methods are employed.
.

M·

S-DOS computers typically
execute programs from
system RAM space.
Often, these programs are
loaded from magnetic-based, serialtransfer, 110 media like floppy or.hard
disks, or sometimes tape drives.
Since memory cards are computerreadable random-access devices,
programs stored in cards can be
executed directly by the. processor
when the. appropriate mapping methods are employed (see figure 1).
An eXecute-In-Place (XIP) working

group within the Personal Computer
Memory Card Industry Association
(PCMCIA)
technical committee
developed some basic concepts and a
list of requirements that lay the
implementation groundwork. Two
basic goals are:
- Low-Cost XIP Hardware
- "Lowest Common Denominator"
Compatibility Approach
Although laptop, notebook, and
palmtop systems have a great deal of
latitude supplying memory space for
XIP within the regions of the first

megabyte of memory, desktop systems do not: Typical ISA, EISA, and
MCA systems have many constraints
that complicate freeing regions larger
than 64Kbytes for XIP. Therefore,
XIP should be defined to work in the
"lowest common denominator" configuration. If a. system can supply
extra memory regions for XIP beyond
the "lowest common denominator"
configuration then that is optional.
This enables XIP applications to run
on either a desktop or a laptop. The
minimal 64Kbyte XIP configuration
minimizes system costs with its low
complexity and by supporting 1Mbyteconstrained systems. In order to meet
these goals, the XIP requirements
were defined as follows:

Requirement 1
A system supporting XIP must be
able to allow the mapping of an XIP
memory block 011 a 16K byte boundary
of system address space. Typically,
these 16Kbyteboundaries will be
above the 640Kbyte user-application
address range. However, this is not
mandated.

About the Author
Don Verner is a Senior Technical
Marketing Engineer for the Flash Memory
Operation of the Memory Components
Division of Intel. He has been involved
with the electronics industry for the last 7
years, the last two years with Intel. He
receiVed his. BSET Degree from Purdue
University.

Figure 1.

© 1991 INTEL CORPORATION
Reprinted with permission from Memory Card Magazine, March/April1991

4-316

Order Number 295066-001

Requirement 2
A system supporting XIP must be
able to simultaneously map a minimum
of four 16Kbyte pages into the system
address space.

Requirement 3
A system supporting XIP mapping
must be able to map the minimum of
four 16Kbyte pages contiguously.
Taken together, requirements 1
through 3 imply that the system be
able to support mapping of four
16Kbyte pages into a 64Kbyte page
frame. This minimum page frame
must be able to start on a 16Kbyte
boundary within the. processor address
space.
This requirement exactly matches a
minimal Lotus-Intel-Microsoft (LIM)
implementation usually referred to· as
the LIM 3.2 page frame.

partition should start on an unwritten
device. This prevents an erasure
of one partition destroying data
in another partition. If the XIP
partition ends without filling up a
chip-erasable device, the whole device
is still considered part of the XIP
partition.
The granularity of the XI? pages,
the processor address boundaries
where the pages can be mapped, and
the page's physical address boundaries within the PC memory card
simplify the design of the mapping
hardware.

Requirement 6
XIP must be compatible with LIM
4.0. That is to say, the presence of

Requirement 4
XIP memory mapping hardware will
view the 64Mbyte physical address
space of PCMCIA PC memory Gard as
4096 regions that are each 16Kbytes
long. Each 16Kbyte region is call a
"page." Obviously, every page starts
on a 16Kbyte boundary (See figure 2,
XIP Memory Card Address Map).
A minimal XIP mapping hardware
implementation must be able to map
any four of the 4096 pages in the PC
memory cards partition into the
processor's address space.

Requirement 5
Since a PC memory card can be
"partitioned" into several file systems
and an XIP partition, the previous
requirements have a side effect on the
physical location of an XIP partition
within a card. An XIP partition within
a PCMCIA compliant card must start
and end on a 16Kbyte physical address
boundary within the card. Only one
XIP partition is allowed per memory
card.
For cards that have individual,
chip-erasable devices, like Intel's
IMbyte and 4Mbyte flash memory
cards, an XIP partition should
not overlap devices that contain
another partition. Instead, the XIP

4-317

the XIP driver and XIP applications in
a system must not "break" either the
LIM 4.0 driver or applications that
depend on LIM 4.0.

Summary
The XIP specification made
tremendous progress over the past
year as evidenced by the clean,
complete-draft s~owing at the March
PCMCIA meeting. There is good
consensus between Japanese Electronics Industry Development Association
UEIDA) and PCMCIA on the XIP
specification. Only minor changes
need to be made to the final draft for
inclusion in the May pre-release of
PCMCIA Release 2.0 specification.
D

AR-702

ARTICLE
REPRINT

FEATURE
ARTICLE
_

MarlcusLevy

Interfacing Microsoft's
Flash File System
Using Flash Memory Under MS-DOS

Idiscusse~

information on all the clusters that are
allocated, free or unusable. It is an
arrayofclusterpoiniers and each entry
hasa one-to-one correspondence with
a cluster on the disk.
Grouping sectors to form clusters
increases efficiency in terms of the
memory required to manage the FAT~
A cluster can consist of a
different number of sec- ,
tors. Four sectors (or 2048
bytes) per cluster isiypical
on a hard disk. The larger
the cluster or allocation
unit, the more potential of
wasting space for files not
User Datal
sized to a multiple of the
number of bytes in a clusDirectory Area
ter. For instance, a 20-byte
file stored on a disk with a
cluster size of 2048 bytes,
A LOOK A1STANDARD MSwastes 2028 bytes.
,
Following the FAT is
DOS
the root directory. Directory entries consist of the
At the highest level, applications make requests to the Figure 1- Flash files are located by following linked-list pointers file name, attributes; time,
date, file size, initial clusMS-DOS function dispatcher within each file and directory entrY.
ter number, and reserved
through interrupt 21h. Arguments identifying the Service desir~ from the requested logical sector to bytes. When allocating space to a file,
the initial cluster number is updated
and its options arc typically passed in the physical location on the device.
For each block device, MS-DOS to point to the initial cIilster number
registers. To relieve application programs of the necessity of managing maintains'four'areas: a boot reCord, a ,used by the file. The value at that
disk storage space, MS-DOS provides File Allocation Table (FAT), a root location in the FAT points to the next
a file system manager. This series of directory, and a data area. The boot cluster used by the fiie or contains an
MS-DOS services keeps track of disk' reco,rd isthe first section on the disk. It end-of-file marker. Thus, the allocastorage using file and directory struc- contains a structureknownas the BIOS tion chain is a forward linked list.
tures.
Parameter Block (BPB) supplying MS- When extending a file and another
All block-device accesses by MS- DOS with information about the disk, cluster is requjred, MS-DOS replaces
DOS arc made through a standard- including sector size, sectors per clus- the end-of-file marker with a pointer
ized device driver. MS-DOS makes ter, number of FATs, directory size to the next cluster, which is set to an
erid- of-file marker.
requestslo a block device by passing (number of files), and so on.
'
Ah increase in file size, or any,
a data' structure, called a request
MS-DOS requires each disk to
header, to the, device driver. The re- 'have a FAT to keep track of sector/ type of file revision, results in a bytequest header contains the desired cluster allocation. The FAT contains alterable modification to tile disk di-

Back in issue 18:
the design for a flash ~emory array
based upon a PC/ AT add-in board
employing SIMMs or IC memory
cards. Now we arc ready to tum your
flash memory platform into a DOScompatible solid-state disk. In this
article I'll show you how to interfa'ce
Microsoft's special Flash File
System (FFS) so you can store
and retrieve files on this nonvolatile solid-state disk.
Before discussing the
structural clements and benefitsofthe FFS,let'sreview some
basic standard MS-DOS concepts. This will provide themotivation for implementing a
special file system for flash
memory.

command and required arguments
and is located by the device driver
using a special routine, typically
named "Stra tegy." For a read or write
request, the logical sector to start the
access and the number of logical sectors to transfer arc provided. The
device ?river performs translations

© 1991 INTEL CORPORATION
Reprinted with permiSsion from Circuit Cellar, Inc., June/July 1991

4-318

Order Number: 295067-001

rectory .. In addition to file
size change, modifications
include time of last change,
date, attributes, and file renaming.

sibling and/or child
pointers and if a directory
entry pertains to a file or a
directory.
When a directory or
Redirector
file is requested, the flash
THE NEED FOR AN ALTERmemory S5D is searched
NATIVE FILE SYSTEM
beginning at the head of
the linked list. The chain
is followed from pointer
Recall that flash memHigh·LeV8lDrivers
to pointer until the corory is a bulk-erase memPurchased
through Microsoh
rect entry is found. If the
ory. The FATand directory
structures created for the
search arrives at the
byte-alterable magnetic
chain's .end (an FNULL
disk are not ideal for a flash
identifier is encountered),
memory solid-state disk
the system responds
Low-L....l Driver
In Ihls
(55D). Updating a FAT or
analogously to MS-DOS
Miele
directory entry requires
with a "File not found"
complete erasure of the
message.
When deleted ver-·
flash memory components
containing the changing
sions of a file appear on
bytes. It is possible to imthe flash memorySSD, the
plement a flash memory Figure 2-A two·level archifecfure provides a consisfenf applicafion file system finds the most
disk based on this ap- interface while allowing for a variety of flash·memory hardware plat- recent version. The status
proach, but the write la- forms.
byte contains bit fields
tency times are unacceptthat indicate whether a
alile for general use. When a file' is
Files and directories are written particular file is valid or deleted. The
added, deleted, or modified, the di- to the flash memory 55D using se- directory information of a deleted file
rectory could be. copied to a RAM quentially free memory locations--a is still used for pointers of the linked
buffer and modified to reflect the stack-like operation (Figure 1). When list and the Search proceeds until it
change. After the flash memory de- the "stack" is full, thedesired files are finds the most recent and valid vervice tha t contains this directory is copied to another disk and the current sion.
erased, the modified directory is cop- disk is erased for reuse.
ied back.
File and subdirectory information FLASH FILE SYSTEM: ARCHITECTURE
Disk imaging is another method is attached to the beginning of each OVERVIEW
of implementing the standard MS- file, unlike the standard MS-DOS apDOS FAT scheme on a flash memory proach of directory and FAT placeThe Rash File System consists of
S5D. Using this method, files are first ment. As directory and file entries are two components: IFS. SYS (Installable
copied to a floppy disk. Then a special added, they are located by building a File System) and FEFS. SYS (Flash
utili ty performs a disk copy transfer- linked list. Besides containing the stan- EPROM Filti System). When an appliring the FAT, directory, and all files to dard fields (e.g., name, extension, time, cation accesses a disk through interthe flash memory SSD. This approach date of creation), a directory or file rupt 21h, the MS-DOS kernel checks
is useful for building an application entry contains a status byte and vari- the drive letter. If the drive has been
cache that is FAT file system compat- ous pointers used for the linked-list declared as a flash memory 5SD,
ible, but all flexibility is lost.
structure. The status byte, besides IF S . S YS intercepts the request
Microsoft has developed a special indicating whether a file/ subdirectory through a proprietary interrupt 2Fh
file system utilizing the attributes of exists or is deleted, also signifies valid redire~tor interface and passes it to
flash memory. To minimize fragmentation losses and allow arbitrary ex- Character De)llce Header
tension of files, the flash memory file
; Pointer to Next Device Driver
Block Header
system uses variable-sized blocks OW
o
rather than the sector/cluster method OW
; Attributes (CHAR, IOCTL control)
1100000000000000B
of standard MS-DOS file systems. This OW
; Offset of Strategy Procedure
Strategy
flexibility is provided by employing a OW
; Offset of Interrupt Procedure
OW
Interrupt
linked-list structure; that is, chaining DB
; Device Name Used by.FEFS to Locat~ the LLD
'FIFIDEV£:'
files together using address poin~ers
located within directory entries for Figure 3-1he Flash Ria System doesn'f use a FAT and directory structure, but Is uses a
each file.
characfer device driver wfllch must contain' the proper header. '
~iscussed

/'

4-319

there is enough here quirements of the flash memory comfor you to understand ponents, as well as routines used to
the LLD software that provide a V turn-off delay.
Maosoft
Requested
The prog;.amming and erase voltcan be obtained from
LLDMAI~ ASM
Procedures
the Circuit Cellar BBS. age, V ,is generated on the pageAlso, if you have no memoi): board using a DC-DC conPMBASM
Corrvnancls
INIT
intentions of imple- verter. When this converter is switched
InrtliIJization
Cod.
LLDTICKASM
menting a DOS-com- on, it takes anywhere from 20 to 100
patible SSD, many of milliseconds for V to arrive at a stable
PV8ASM
INIT
the device primitives voltage. This tirJ~ depends on the
RESIDENT
Hwdware
LLDMAIN ASM
from the low-level amount of capacitive loading and the
Anembly
Speoftc
Procedures
Md
driver can be extracted circuit used, as some have faster start
INIT
»
I.Jnking
PMB,ASM
Code to
for any type of flash times. If you are designing your hardLocata Bowd
ware for a desktop system, Vp can rememory application.
LLOTICKASM
The LLD consists main switched on. However~ in batof three components: tery-powered systems, V should be
llQTICKASM
/
an, MS-DOS device switched off when not in"~se to conRESIDENT
~~~~:t!t~~:':;J
TirTlM
driver, the procedures serve pqwer. To accommodate these
Procedures
called by Microsoft's applications, I have written a proceINIT I - - - - { j
FFS, and the page- dure to generate a Vp tum-off delay.
TtmeConstmts
memory board hard- This is similar to that for a floppy disk
ware-specific proce- in that after two seconds of nonuse,
~igure 4- The INiT portion of the device, driver is used only
dures. I have written V is switched off. If several blocks of
once. ot initialization. then "discarded.·
the LLD in several d~~a are being written consecutively,
the FEFS. SYS driver. FEFS·. SYS modules to simplify any modifications your software will not have to delay
implements the FFS logic, developing necessary to accommodate hardware waiting for V to ramp up every time
and maintaining the linked'list struc- variations. The module LLDMAIN . ASM a new block written.
tures.
The V turn-off delay is calcucontains the MS-DOS interface rouThe Microsoft FFS is implemented tines, the Microsoft-requested proce- lated by i~~talling an interrupt lCh
as a two-level architecture, where dures, 'and special Intel-extended (time-of-day dock) filter. This'interIFS. SYS and FEFS. SYS represent procedures. PMS . ASMcontains proce- rupt is generated every 18.2 millisecthe high-level driver communicating dures specific to the page-memory onds. Before servicing the original
with a low-level driver (LLD) that is board. hardware, such as setting the interrupt, our filter increments a count
hardware specific (Figure 2). This page number and turning on V . All value. When that count value reaches
architecture provides a consistent the functions contained in this P~od­ 36, the procedure to tum V pp off is
.
application program interface while ule control the I/O functions on the called.
,allowing for a variety of flash memory board. LLDTICK.ASM contains proSince the LLD is an install able
hardware platforms.
cedures associated with the timing re- device driver, it requires a standard
The, LLD implements a set of
One Megabyte Intel
device plimiti ves for use by the highFlash Memory Card
level driver. This is not that different
from the FAT file system as we know
AO·1S
AO·1S
it. In that environment, MS-DOS imAddress as a 64K Page
plements a high-level, FAT file system
LATCH
driver interacting with a set of device
QO r..i
AlB
primitives implemented as interrupt
A17
01 roil
AlB
02 ~
13h.
~
LLDMA-IN ASM

RESIDENT

DevICe Header

Intel·E:rIe~d

Uso Group Oira:tiva to Link and
l.oc.1Iaa.:.hSCLK

10 Page Num ber

r.I

(Irom tlO decode circuitry)

Figure 5-Device density is dynamically determined.
with page numbers beyond the valid size of the
device handled by page wrapping.

4-320

Selecting Page Numbers Greater th~n
15, Outputs to the Memory C,ard's
No-Connect Pins
On Higher Density Memory Cards,
These No-Connect Pins Are Used for
Additional Address Inputs

MS-DOS-<:ompatible interface that
provides a request header and entry
points intn the Strategy and Interrupt
procedures..This portion of code primarily performs the initialization of
the device driver.
Unlike the magnetic disk, the FFS
does not implement a FAT and directory structure with sectors. Therefore,
it is designed as a character device
driver rather thana block device driver
and must contain a character device
driver header (Figure 3). During installation of the character device, MS005 passes a command number in a
request header to the Interrupt procedure which dispatches a call to the
InitDriverroutine(commandzero).
This procedure is performed only
once, immediately after the device
driver .is loaded into memory. The
ini tialization procedure of the character device, Ini tDri ver, is primarily
responsible for locating the pagememory board, computing the time
constants for the flash memory program and erase algorithms, and determining the quantity of flash memory
available.

INITIALIZATION
Recall from the page-memory·
board design that the first four I/O
ports are read to obtain the board's
signature. A procedure, SearchPMB,
called by InitDriver,readssequential I/O ports until finding this signature. When the signature is found, the
base port address is stored in a memory location to be used for future I/O
port access. If the board is not present,
the driver aborts its installation and
returns the system memory to M5DOS. This is done by passing an offset
of zero back to MS-DOS in the INIT
request header. Each of the three
modules (LLDMAIN. ASM, PMB. ASM,
LLDTICK. ASM) are divided into a
RESIDENT and an INIT segment.
These segments are joined using the
group directive to ensure they are
linked and loaded consecutively in
memory. Using this technique, if the
page-memory board is found, the
end ing offset of the resident portion of
the device driver is passed back to
MS-DOS (Figure 4). This "throws

4-321

One-and four-megabyte card den- the device size. Comparison against a
sities areavailable today, but the page- table of IDs versus densities allows
memory board's card socket handles the calculation of the page number
up to 64 megabytes (based on the needed to access the next component.
Theoretically, this process would
Personal Computer Memory Card
International Association, PCMCIA, continue, adding up the total number
specifications). Assume that a one- of components and multiplying that
megabyte card has been instaIled number by the component size to cal(although oursoftware doesn't know culate the total module density.
this yet) containing eight one-megabit However, the page-memory board
components (28FOlO). The first step in ! responds to setting the page register
determining the module's density is beyond the valid page range of the
reading the flash memory device ID flash memory installed (Figure 5). For
from offset zero of page zero to obtain example, the one-megabyte memory
card accommodates sixteen (numbered 0-15) 64K-byte pages. Pages 0,
GetPhyChar PROe NEAR
16, 32, and so on, access the same
ASSUME CS:PROG, DS:PROG, ES:N.oTHING
memory location because of the wrapCALL
TurnVppON
Turn Vpp ON for READID CMD
around phenomenon. This inaccuXOR
AX,AX
AX contains page number
rately determines an infinite module
CALL
SetPage
Rout ine to set page
size. How does our software know
MOV
ES, FrameSeg
Point to page frame segment
when to stop? Notice in the code
XOR
01,01
Point to start of· device
(Listing 1) that the first device (page
MOV
ES:WORD PTR[DI], (READID_CMD SHL 8.1 OR READID CMD
zero) is left in the READ_ID mode.
MOV
AX,-ES: [01]
: Read manufacturer's ID
Looping through the rest of memory,
CMP
AX, (INTEL ID SHL 8) OR, INTEL IO ; Intel Devices?
a wrap-around is detected when the
GPC2
- ; Yes, cont inue JE
GPCl:
device ID is alread y present in the first
MOV
ES:WORD PTR[DIL (READ CMD SHL 8) OR READ_CMD
location of the device. This condition
STC
Indicate- error and exit
JMP
GPCExit
is used to terminate the loop.
GPC2 :
Besides ini tialization, the MS-DOS
MOV
BX,2
num of 64K pages/device
for 1 Meg devices·
device driver for FFS supports IOCTL
reads and writes. The device driver
----- Compute total size of media
uses the IOCTL commands to return
XOR
AX,AX
Clear regs for accumulation
control information to the program
MOV
CX,AX
Count nurn of device pairs
SHL
BX,l
regarding the de,vice. FFS issues the
2 Devices' per 16 bits
GPC3 :
IOCTL commands to get and set the
INC
CX
Count num of device pairs
ADD
AX-, ax
entry point for the low-level driver.
Point to next device pair
CALL
SetPage
Se lect page for next device
Unlike block devices, character deAlready in READ 10 mode?
CMP
ES:WORD PTR [OIL (INTEL ID SHL 8) OR INTEL ID
vices are located with a file open reJNE
GPC4
; No, Cont i-nue
quest. When FEFS . SYS installs,itlinks
JMP
GPC5
; Yes, We re done
GPC4 :
into the low-level driver by opening
MOV
ES :WORD PTR [OIL (READID CMD SHL 8) OR READID_CMD
the file FIFIDEV£ (£ is the British
Intel Devrces?
eMP
ES:WROD PTR [OIL (INTEL 10 SHL 8) OR INTEL- ID
Pound Sterling or IBM extended ASCII
JNE
GPC5
9Ch), and performing an IOCTL read
; Set READ mode and check next device
toobtain the pointer to the entry of the
MOV
ES:WORD PTR [OIL (READ_CMD SHL 8) OR READ_CMD
low-level driver.
JMP
GPC3
GPC5 :
Character,devices do not support
MOV
ES :WORD PTR [OIL (READ CMD SHL 9) OR READ_CMD
drive letters. You must use a "pseudo; Get num -of device pairs
MOV
AX,CX
SHL
block" device header during driver
AX, 1
: Compute number of devices
MOV
BX,2
; Multiply by number of 64k. pages
installation to reserve OOS letters for
MUL
BX
MOV
TotalSizeHi, AX ; .Set tota-l size
use by the FFS (Listing 2). After the
MOV
TotalSiz~LO, 0 ; Size is always a mUltiple of 64k
character device installs, the blockGPCExi t :
CALL
TurnVppOFF
; Turn off Vpp
device driver links the device driver
. into the device driver chain. Drive
RET
GetPhyChar ENDP
letters are established by providing
fake BPB information in the block
Listing 1- Page wrap-around Is detected by leaving the nrst device encountered in device driver headerto pass back to
MS-DOS.
RfAOJO mode. When a preexisting 10 is found. the program knows to stop looping.

away" the INIT portion which is not
needed after initialization.
The page-memory board has four
sockets for Intel Flash Memory single
in-linememorymodules(SIMMs). The
hardware functions with one or more
sockets populated, so during initialization the available memory must be
determined. Similarly, with the Intel
Flash Memory Card, an interesting
situation is faced in accommodating
dcnsi ty varia tions. This is best understood using the memory card as an
example.

I

4-322

; Block Device Header use to set up drive letters with MS-DOS

By issuing the IOCTL read
command, FEFS. SYS obtained the
entry point to the low-level driver,
which has been named FlashEntry.
The FlashEntry procedure is to the
FFS what the Interrupt procedure is to
an MS-DOS device driver. It determines a command's validity before
dispatching. FlashEntry handles
cal\s from FEFS . SYS and applications
that communicate directly with the
flash me.nory, such as a formatter.
When writing the procedures to
handle the FE:FS . SYscommands,itis
important to follow the entry and exit
protocols. This is analogous to interrupt routines expecting parameters
and status information to be passed
within certain registers. Take for example the procedure ReadLogBloc k
that reads a block of data from the
flash memory SSD into a buffer. FFS is
informed by MS-DOS that the destination buffer is located at ES:BX. The
CX register contains the number of
bytes to read. A 32-bit pointer into
flash memory is supplied by D1:DX.
The unit number is passed in the AL
register. Upon return from this procedure, the carry flag is expected to have
the status of the operation, whether it
was successful or unsuccessful.
There are thirteen procedures,
including ReadLogBlock, that are
defined by the Microsoft FFS technical specification. To more fully comprehend the file system, a brief discussion of each is helpful:
GetMediaCheck-Determines
media status (same, changed, missing, unknown).
ReadLogBlock-Read a block of
data at a logical address (which must
be converted to a physical address).
Wr i teLogBlock-Writesa block
of data 

BPB

<512,1,1,2,128,1024, DF8H, 2>

Dummy values
Dummy values

listing 2 - To reseNe an M~DOS ctive letter. a different header must be used dUring ctiver
installation. The new header acts li/(e a bloc/( device. rather than a character device.

Fi rstF ree-Finds the first nonFFh byte from the end of the SSD and,
as a result, finds the first available
space.

4-323

SetMediaCB-Registersa procedure as the call-back procedure which
is called by the LLD when a flash
memory card is inserted or removed

Q

Latch

Inlerrupt

10_s:s~e~_

.

.

(2)

. .

. Card Detect

.

SmlNG I)P THE PAGE NUMBER

Card Detect

,,
"" (3)

P

"~

.. ,

........ .
(5)

••••.

:J=-j ---(4)-- -~FEF~ I]

1""1C<:::::L==ow=.L=ev=e'=bn=·ve=r::::;::1

(1) • ·CaRl is Removed or Reinserted
(2) • System is NOlilied of Inlerrupl
(3) • Syslem Vectors to Inlerrupl RoUline in LLD
(4) • LLD NoliliOs FEFS Through Call>ack Interlaoe lhal Media Has Changed
(5) • FEFS Requesls LLD to Perlorm a Media Inlerrogalion
Figure 6-The Call-back Interface supports changeable media In a system usfng Rash

Cards.

.

(sec the discussi.on on Removable Media).
GetMediaCB~Returns the 'pres~
entmedia call-back proccdurepointer ..
If zero is returned, no media call-back
procedure exists.
WriteLogByte-Write a byte of
data.

the SSD. A zero value returned indicates no erase call-back procedure has
been registered.

ReadLogByte-Read a byte of
data.
SetEraseCB-Registersaprocedure  issuesstandby, active,andtransient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

A system designer must guard against active writes
for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
\ occurs after successful completion of the two-step
command sequences.

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have aO.1 /LF ceramic capacitor
connected between Vee andVss, and between Vpp
and Vss.

28F256A Power Dissipation
When deSigning portable systems, deSigners must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F256A does not consume any power to retain
code or data when the system is off. Table 4 illustrates .the power .diSSipated when updating the
28F256A.

Place· the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 /LF electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

5-12

infel .

A28F256A

Table 4. 28F256A Typical Update Power Dissipatlon(4)
Operation

Power Dissipation
(Watt-Seconds)

Notes

Array Program/Program Verify

0.043

1

Array Erase/Erase Verify

0.083

2

One Complete Cycle

0.169

3

NOTES:
1. Formula to calculate typical Program/Program Verify Power = [Vpp X # Bytes X typical # Prog Pulses (tWHWHl X IpP2
typical +twHGL X IpP4 typical)] + [Vcc X # Bytes X typical # Prog Pulses (tWHWHl X ICC2 typical + tWHGL x ICC2
typical)].·
_ .
.
2. Formula to calculate typical Erase/Erase Verify Power = [Vpp (lPP3 typical X tERASE typical + IpP5 typical X tWHGL X
# Bytes)] + [VCC(lCC3 typical X tERASE typical + ICC5 typical X tWHGL X # Bytes)].
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. "Typicals" are not guaranteed. but based on a limited number of samples from production lots.

5-13

A28F256A

Vcc Supply Voltage with
Respect to Ground ••...•...• - 2.0V to + 7.0V(2)
Ol,ltput Short Circuit Current ..•.•........ 100 mA(4)
Maximum Junction Temperature (TJ) . ~ .•...• 140°C

ABSOLUTE MAXIMl)M RATINGS'"
Operating Temperature
During Read .....•........ - 40·C to + 125·C(1)
During Erase/Program •...... -40"C to + 125·C
Temperature Under Bias ....• .' .. -40·C to + 125·C
Storage Temperature .......... -65·C to + 150·C
Voltage on Any Pin with
Respectto Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
.
Respect to Ground .....•. - 2;OV to + 13.5V(2.3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... -2.0V to + 14.0V(2. 3)

NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing ths diMee beyond the "Absolute
. Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond t!)e
"Operating Conditions" is not recommanded.and extended exposure beyond the "Operating Conditions"
may affect devica reliability.

NOTES:

1. Operating temperature is for automotive product defined by this specification.
.
2. Minimum DC input voltage is -0.5V. During transitions. inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V. which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum DC voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
4.. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Umlts

Parameter
Min

Max

Unit

Comments
For Read-Only and
Read/Write Operations

TA

Operating Temperature

-40

+125

·C

Vcc

Vcc Supply Voltage

4.50

5.50

V

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
...

Symbol

.-

Parameter

Notes
Min

Umlts

Typical

Unit
Max

Test Conditions
,

III

Input Leakage Current

1

±1.0

".A

Vce..= Vcc Max
VIN = Vcc or Vss

ILO

Output Leakage CLirrent

1

±10

".A

Vec = Vcc Max
VOUT = Vce or Vss

Ices

Vcc Standby'Current

1

1.0

mA

Vcc = VccMax
~=VIH

ICC1

Vee Active Read Current

1

10

30

mA

Vcc = Vcc Max, ~ = VIL
f = 6 MHz, lOUT = OmA

ICC2

\ Vee Programming Current

1,2

1.0

30

rnA

Programming in Progress

Icca

Vee Erase Current

1,2

5~0

30

mA

Erasure in Progress

ICC4

Vec Program Verify Current

1,2

5.0

30

mA

Vpp = VPPH
Program Verify in Progress

ICC5

Vee Erase Verify Current

1,2

5.0

30

mA

Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±10

".A

Vpp S:Vce

.

1

5-14

intel"

A28F256A

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Unit

Min Typical
IpP1

VPP Read Current or
Standby Current

IpP2

Test Conditions

Max

1

90

200

Vpp Programming Current

1,2

8.0

30

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

30

mA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

p.A Vpp = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VIO

Ag Intelligent Identifer Voltage

110

Vee 10 Current

±10

0.8
Vee

+ 0.5

0.45
2.4
11.50
1

Vpp 10 Current

p.A Vpp> Vee
p.A Vpp s Vee

V
V
V

IOL = 2.1 mA
Vee = Vee Min

V

IOH = -2.5mA
Vee = Vee Min
Ag = VIO

13.00

V

10

30

mA

90

500

p.A

VPPL

Vpp during Read-Only Operations

0.00

6.5

VpPH

Vpp during Read/Write Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

2.5

Ag = VIO

V NOTE: Erase/Program are
Inhibited when Vpp = VpPL
V
V

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Notes

Limits

Unit

Test Conditions

Min Typical Max

III

Input Leakage Current

1

±1.0 p.A Vee = Vee Max
VIN = VccorVss

ILO

Output Leakage Current

1

±10 p.A Vcc = Vec Max
VOUT = VCC or Vss

Ices

Vee Standby Current

1

50

100

p.A Vcc = Vee Max
CE = Vce ±0.2V

ICC1

Vee Active Read Current

1

10

30

mA Vec = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

i

lec2

Vce Programming Current

1,2

1.0

30

mA Programming in Progress

lee3

Vcc Erase Current

1,2

5.0

30

mA Erasure in Progress

lec4

Vcc Program Verify Cur~ent

1,2

5.0

30

mA Vpp = VpPH Program Verify in Progress

ICC5

Vcc Erase Verify Current

1,2

5.0

30

mA Vpp = VPPH Erase Verify in Progress

5-15

A28F256A

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Umlts'

Notes
Min

IpPS

Vpp Leak,age Current

IpP1

Vpp Read Current or
Standby Current

i

Typical

1

Unit
±10

1

Test Conditions

Max

90

p.A Vpp

200

p.A

±10

S;

Vee

Vpp> Vee
Vpp

S;

Vee

IpP2

Vpp Programming Current

1,2

8.0

30

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp'Erase Current

1,2

4.0

30

·mA Vpp == VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

rnA Vpp = VPPH
Program Verify in Progress

Ipps

Vpp Erase Verify Current

1,2

2.0

5.0

!VIL

Input Low Voltage

-0.5

!ViH

Input High Voltage!

0.7 Vee

!VOL

Output Low Voltage

iVOH1

0.8
Vee

+ 0.5

0.45

Output High Voltage

V
V
V IOL =2.1 mA
Vee Vee Min

=

loti =:' -2.5mA,
V
Vee = Vee Min

0.85 Vee

IVOH2

' mA Vpp ",=VPPH
Erase Verify in Progress

IOH = -100 pA,
Vee = Vee Min

Vee -.0.4

!VIO

Ag Intelligent Identifer
Voltage

110

Vee 10 Current

1

10

30

rnA Ag,,= 10

110

Vpp 10 Current

1

90

500,

jJ,A Ag = 10

!VPPL'

Vppduring
Read-Only Operations

0.00

6.5

!VPPH

Vpp during Read/
Write Op~rations

11.40

12.60

iVLKO

11.50

13.00

,V

V NOTE: Erase/Programs arE
Inhibited when Vpp =: VPPL
V Vpp = 12.0V

,-

Vee Erase/Write Lock Voltage

2.5 .

V

CAPACITANCE(3) TA = 25°C, f = 1.0 MHz
Symbol

Umlts

Parameter
Min

CIN

Address/Control Capacitance

COUT

Output Capacitance

Unit

Conditions

Max
8

pF

VIN == OV

12

pF'

Vour= OV
\

N~.

.>

,1. All currents are in RMS unless otherwise noted. Typical values at Vee = S.OV; v.pp = 12.0V, T- = 2S'e.
2. Not 100% tested: characterization data available.
.
3. Sampled. not 100% tested.
4. "Typicals" are not guaranteed. but are based on a limited mimber. of samples frO!Tiproductiori jots.

5-16

A28F256A

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels .•.............. 0.45V and 2.4V
Input Timing Reference Level ....... O.BV and 2.0V
Output 'Timing Reference Level ••.•.. O.BV and 2.0V
AC TESTING INPUT/OUTPUT WAVEFORM
2.4V-"m~--

AC TESTING LOAD CIRCUIT

_ _ _ __

1.3V

INPUT
O.45V....l~;.;....-------

OUTPUT

1N914
3.3K

2.0V >TEST POINTS

O.BV

1-+-0 OUT
290168-8

~ CL=l00pF

AC Testing: Inputs are driven at 2.5V for a logic "1" and 0.45V for
a logic "0". Testing 'measurements are made at 2.0V for a logic
"1" and 0.8V for a logic "0". Rise/Fall time s: 10 ns.

290168-9

CL = 100 pF
CL includes Jig Capacitance

AC CHARACTERISTICS-Read-Only Operatlons(2)
Versions
Symbol

Characteristic

Notes

28F256A·120

28F256A·150

Min

Min

Max

Max

Unit

tAVAV/tRC

Read Cycle Time

tELQV/tcE

Chip Enable
Access Time

120

150

ns,

3,

ns

150

120

tAVQV/tACC

Address Access Time

120

150

ns

tGLQV/toE

Output Enable
AccessT!me

50

55

ns

tELQX/tLZ

Chip Enable to
Output in Low Z

3

tEHQZ

Chip Disable to
Output in High Z

3

tGLQX/toLZ

Output Enable to
Output in Low Z

3

tGHQZ/tOF

Output Disable to
Output in High Z

4

Output Hold from

1,3

toH

O'

0

55

50

35

30

ns
ns

0

0

Address,~,

ns

ns

0

0

ns

6

6

","S

" or OE Change
twHGL

Write Recovery Time
before Read

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time :!f: 10 ns.
3. Not 100% tested: characterization data available.
4. Guaranteed by design;
5-17

l.
Vcc POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

. DATA VALID

J

ADDRESSES

ADDRESSES STABLE

,
/.

STANDBY
---

\.

---

'

Vee POWER-DOWN

·1

tAVAV(tRC)

'TI

ac
...CD

cr (E)

,

_ _ _ _ _ _ _ _ _J

:"I

~

~

-...
~

DE (G)

0

(XI

-..

t WHGL

I.

0

WE

DI

;!l.

oj

----

;

::u
CD

~

---'

,

3
':!:. (II.

~

\

(W)

a.
0

toH

"C
CD

iil

=
0
:s

~

,

DATA (DQ)

HIGH Z

(j«(((
I'})}}P

(II

/.
S.OV /
VCC

.

, ), ,b

tAVOV(tACC)

--OUTPUT VALID

---

d{ { (- J
q«('1

•I
"-

OV
290168-10

intel .

A28F256A

AC CHARACTERISTICS-Write/Erase/Program Operations(1,3)
Versions

28F256A-120

Symbol

Characteristic

Notes

tAVAV/twc

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tOVWH/tOS

Data Set-up Time

tWHOX/tOH

Data Hold Time

tWHGL

Write Recovery Time
before Read

tGHWL

Read Recovery Time
before Write

Min

28F256A-150

Max

Min

Max

Unit

120
0
60
50
10
6

150
0
60
50
10
6

,...s

0

0

,...s

2

20

20

ns

0
80
80 '

0
80
80

ns

2
2

ns

2

ns
ns
ns
ns
ns

tELWL/tcs

. Chip Enable
Set-Up Time before Write

tWHEH/tCH

Chip Enable Hold Time

tWLWH/twp

Write Pulse Width

tELEH

Alternative Write
Pulse Width

tWHWL/twPH

Write Pulse Width High

tWHWH1

Duration of
Programming Operation

4

20
10

20
10

,...s

tWHWH2

Duration of
Erase Operation

4

9.5

9.5

ms

tVPEL

VppSet-Up
Time to Chip Enable Low

1.0

1.0

ms

ns

ns

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
'2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
3. Rise/Fall time ,;; 10 ns.
4. The integrated stop timer terminates the programming/ erase operations, thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Parameter

limits

Notes
Min

. Chip Erase Time
Chip Program Time
Erase/Program Cycles

1,3,4,6
1,2,4
1,3,5

1,000

Unit

Typ

Max

1

60

0.5
100,000

3.1

,

Comments

Sec

Excludes OOH Programming
Prior to Erasure

Sec

Excludes System-Level Overhead

Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at
T = 25·C, Vpp = 12.0V, Vee = 5.0V.
2. Minimum byte programming time excluding system overhead is 16 J.Ls (10 J.Lsprogram + 6 ,...S write recovery), while
maximum is 400 J.Ls/byte (16 J.Ls x 25 loops allowed by algorithm). Max chip programming time is specified lower than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the WOfSt case byte.
3. Excludes OOH Programming prior to erasure:
4. Excludes system-level overhead.
5. Refer to RR-60 "ETOX Flash Memory Reliability Data Summary" for typical cycling data and failure rate 'calculations.
6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at
T = -40·C, 1,000 cycles, Vpp = 11.4V, Vee = 4.5V.

5-19

intet

A28F256A

99.9

/.." ,"
,/,/

//
99

/

95

J

80

/

70
60
50
40

0

/

::I

(,)

V
, ,,
,

/

,,

,,

I'"

,
/' ,

30
20

,

.
:

10

-

' "

././

/

90

....
,.

V

..-

0.1
0.5

0.630.750.881.01.1 1.3

'2.5

Chip Program

3.8

5.0

nm. (••c)

- - - 1 2 V ; 10 kc; 23°C
·-----·11.4V; 10 kc; 700C
- - - - 12V; 100 kc; 230C

290168-14

Figure 8. 28F256A Typical Programming Capability
See Note 1, Page 5-19
.
1.9

i

1B

,

,I

/

'.

1.6

/'
15

./

i

..o

.

.1

..... .... -'

1.0

/

0.75

03

/

,,

/

0.9

0.6

.I

i

i

I

,,

~~

~

~

~

-

~

,

~ro

I

-- -'
/

I

j

,

I

o w.

I

I

/
,/

ro

00

00

~

m

~

~

TEMP (OC)
- 1 k Cycles
----- 10k Cycles

- - 100k Cycl••

290168-15

Figure 9. 28F256A Typical Program Time at Vpp = 12.0V
5·20

A28F256A

99.9

~

V
,V
,, ,

99

V

95

i/ ," ,

90
80

70

/

60
50
40

,

/

V

30

I

20

'

J ,'.~'

/

'/
,

,'

,.

.'/

/ .~"
I ,' ,

10

i,' I

"

if
,'1"

"

O.1
0.3

0.5

0.7

1

2

3

4

5 6 7 89 10

20

CHIP ERA5E TIWE (sec)
- - - 1 2 V . 10 kc: 230C
_ •• 11.4V: 10 kc: COC
·-----·12V, 100 kc, 230C

290168-16

Figure 10. 28F256A Typical Erase Capability
See Note 1, Page 5-19

1.8

1.6

\

~

'.

!...

,,

~

>=

"

,,

... 1.0

g
!!.

U

' . I·...

1.2

0.8

"

~

"

....

'. .,

, , '.
"

'.

,

'.

'.

0.4

.', "

.
r--.. ....... ........ ...:,:,.
.......

r...... ....... '.

·0.6

'

'

0.2

o

10

20

30

40

50

60

70

80

90 100 110 120 130 140

TEWP (OC)
--lkC),cln
•• _-. 10k Cycles

--1ook Cycles

Figure 11. 28F256A Typical Erase Time at Vpp

5·21

290168-17
=

12.0V

_.
Vee POWER-UP &:
STANDBY

PROGRAM COMMAND
LATCH ADDRESS
&: DATA

SET- UP PROGRAM
COMMAND

PROGRAMMING

VERIFY
COMMAND

PROGRAM
VERIFICATION

l

STANDBY /
Vee POWER-OOWN

@

ADDRESSES

'"11

cr (E)

iEi
c

iil

....

.

~

~

OE (G)

~

I'

<
CD

...30-

Cf
I\)
I\)

WE

....
0

0

'til
CD
DI

...

g:
~

1/1

t WHGL

tWLWH (twp)

t

t

~LoV.

I--

STATE
CONTROL
COMMAND
REGISTER

~
'

I
PGM VOLTAGEJ
SWITCH

CHIP ENABLE
OUTPUT ENABLE
LOGIC

~
I

"a-A 15

3\

::t:

3
VI

!:l
IX
c
c

...

DATA
LATCH

~

Y-DECODER
STB

:;.STB

X-DECODER

r---+
r---+

•
•
•
•

Y-GATING

524.288 BIT
CELL MATRIX

~

t---+
290265-1

Figure 1. 28F512 Block Diagram

AUTOMOTIVE TEMPERATURE FLASH
MEMORIES

Speed
Versions

The 'Intel Automotive FLASH Memories have received additional processing to enhance product
characteristics. The automotive temperature range
is -40·C to + 1.25°C during the read/write/erase/
program operations.

5-26

Packaging Options
Plastic DIP

PLCC

"120

AP

AN

-150

AP

AN

intaL

A28F512

28F512

...

vpp
Ne

vee

A ,S

NC

A'2

A,~

A7

A7

AI3

A&

As

As

AS

As

Ag

A~

A~

All

A3

A3

OE

A2

A2

A ,O

A,

~o

~

WE

« z

$~I~

0

z
A,~

Au

28F512
32 - LEAD PLCC
x 0.550"
TOP VIEW

0.~50"

A8
Ag

A11

OE
A,O

A,

CE

AO

CE

Ao

007

DQo

DQ7

000

00&

DQ,

OOs

002

oo~

Vss

003

290265-3
290265-2

Figure 2. 28F512 Pin Configurations
Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A15

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.

DQo-DQ7

INPUT/OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
arid float to tri·state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.

CE

INPUT

CHIP ENABLE: Activates the device's controlloQ!s. input buffers,
decoders and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.

OE

INPUT

OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE is active low.

WE

INPUT

WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse.
Note: With Vpp ::;; 6.5V, memory contents cannot be altered.

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 10%)

Vss

GROUND

NC

NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.

5·27

intel·

A28F512

APPLICATIONS
The 28F512 flash-mem~ry adds ~Iectrical chip-era,sure and reprogrammabillty to EPROM non-volatility
and ease of use. The 28F512 is ideal for storing
,code or data-tables in applications where periodic
updates are required. The 28F512 also serves as a
dense, non"olatile data acquisition and storage medium.
.
The need for code updates pervades all phases of a
system's life-from prototyping to system manufacture to after-sale service. In the factory, during prototyping, revisions to control code necessitate ultraviolet erasure and reprogramming of EPROM-based
prototype codes. The 28F512 replaces the 15- to
20-minute ultraviolet erasure with one-second electrical erasure. Electrical chip-erasure and reprogramming occur in the same workstation or PROMprogrammer socket.
Diagnostics, performed at subassembly or final as. sembly stages, often requi~e the socketing of
EPROMs, Socketed test codes are ultimately reo,
placed with EPROMs containing the final program.
With electrical chip-erasure and reprogramming, the
28F512 is soldered to the circuit board. Test codes
are programmed Into the 28F512 as it resides on the
circuit board. Ultimately, the final code can be downloaded to the device. The 28F512's in-circuit alterability eliminates, unnecessary handling and less-reliable socketed connections; while adding greater
test flexibility.
Material and labor costs associated with code
changes increase,at higher levels of system integration-the most costly being code updates after sale. .

5-28

Code "bugs", or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM~based code require the removal of
EPROM components or entire boards.
DeSigning with the in-circuit alterable 28F512 eliminates socketed memories, reduces overall material
costs, and drastically cuts the labor costs associated with code updates. With the 28F512, code updates are implemented locally via an edge-connector, or remotely over a serial communication link.
The,28F512'S electrical chip-erasure, byte reprogrammability, and complete nonvolatility fit well with
data accumulation needs. Electrical chip-erasure
gives the designer a "blank-slate" in which to log
data. Data can be periodically off-loaded for analysis-erasing the slate and repeating the cycle. Or,
multiple device~ can maintain a "rolling window" of
accumulated data. '
With high denSity, nonvolatility, and extended cycling
capability, the 28F512 offers an innovative alternative for mass storage:
Integrating main memory and backup storage functions into directly executable flash memory boosts
system performance, shrinks system size, and cuts
power consumption. Reliability exceeds that of elec~
tromechanical media, with greater durability in ex-'
treme environmental conditions.
A high degree of on-Chip fe~ture integration simplifies memory-to-processor interfacing: Figure 3 depicts two 28F512s tied to the 80C186 system bus.
The 28F512's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.·

int'el..

A28F512

Vee

vee

80C186
SYSTEM BUS

Vee
A,-A'6

"'0-A'5

00S-00'5

Vee
"'0-A'5

0°0-0°7

000 -007

000-007
28F5l2

28F5l2
'MCSl

CE

BHE

CE

WE

ViR

WE

"'0
Rii

Of

Of
290265-4

Figure 3~ 28F512 in an 80C186 System

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.

With cost-effective in-system reprogramming and
extended cycling capability, the 28F512 fills the
functionality gap between traditional EPROMs and
EEPROMs.
EPROM-compatible
specifications,
straightforward interfacing, and in-circuit, alterability
allows designers'to easily augment memory flexibility and satisfy the need for updatable nonvolatile
storage in today's designs.

PRINCIPLES OF OPERATION
FlaSh-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F512 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.

Integrated Program/Erase Stop Timer
Successive command write, cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Program and erase pulse durations
are minimums only. When the stop timer terminates
a program or erase operation, the device enters an
inactive state and remains inactive until receiving the
appropriate verify or reset command.

In the absence of high voltage on the Vpp pin, the
28F512 is a read-only memory. Manipulation ofthe
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage isapplied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory contents-Intelligent Identifier, erase, erase verify; program, and program verify-are accessed via the
command register.
'

Write Protection
The command register is only alterable when Vpp is
at high voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When high voltage is removed,
5-29

intel .

A28F512

Table 2. 28F512 Bus Operations
Pins

Vpp(1)

Ao

A9

CE

OE

WE

VPPL

Ao

Ag

VIL

VIL

VIH

Data Out

Output Disable

VPPL

X
X

VIH

VIH

Tri-State

VPPL

X
X

VIL

Standby

VIH

X

X

Tri-State

VIL

VIO(3)

VIL

VIL

VIH

Data = 89H

VIL

VIL

VIH

Data = B8H

VIL

VIL

VIH

DataOut(4)

DQo-DQ7

Operation
Read

READ-ONLY

Intelligent Identifier (Mfr)(2)

READ/WRITE

VPPL

Intelligent Identifier (Device)(2)

VPPL

VIH

VID(3)

Read

VPPH

Ao

Ag

Output Disable

VPPH

VIL

VIH

VIH

VPPH

X
X

Tri-State

Standby(S)

X
X

VIH

X

X

Tri-State

Write

VPPH

Ao

Ag

VIL

VIH

VIL

Data In(6)

NOTES:
1. VPPL may be ground, a no-connect with a resistor tied to ground, or ,;;: 6.SV. VPPH is the programming voltage specified
for the device. Refer to D.C. Characteristics. When Vpp = VppL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessE1d via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
S. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

When Vpp is low (VpPU, the read only operation is
active. This permits reading the data in the array and
outputting the Intelligent Identifier codes (see Table
2). When Vpp is high (VpPH), the default condition of
the device is the read only mode. This allows reading the data in the array. Further functionality is
achieved though the Command Register as shown
in Table 3.

the contents of the register default to the read coinmand, making the 28F512 a read-only memory.
Memory contents cannot be altered.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this instance, all operations are performed in conjunction with the command register.
The 28F512 is designed to accommodate. either design practice, and to encourage optimization of the
processor-memory interface.

Output Disable
With Output-Enable at a logic~high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.
'

The two-step program/erase write sequence to the
Command Register provides additional software
write protection.

Standby

BUS OPERATIONS

With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F512's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal. If
the 28F512 is deselected during erasure, programming, or program/etase verification, the device
draws active current until the operation is terminated.

Read
The 28F512 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Figure 6 illustrates read timing waveforms.

Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B8H). Pro5-30

intel·

A28F512

gramming equipment automatically matches the device with its proper erase and programming algorithms.
With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage VID (see DC Characteristics) activates the operation. Data read from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for .instances where
the 28F512 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B8H).
Write
Device erasure and programming arEl accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents 'of the register
serve as input to the ,internal state-machine. The
state-machine outputs dictate the function of the
device.

The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (V1l), while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Eljable" while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to A.C. Write Characteristics and the Erasel
Programming Wavefornisfor specific timing
parameters.
COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
Placing high voltage on theVpp pin enables readl
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F512 register
commands.

Table 3. Command Definitions
Command
Read Memory

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)
1

Write

X

OOH

Read Intelligent Identifier Code(4) , 2

Write

X

90H

Read

IA

10

Set-up Erase/Erase(5)

Write

X

20H

Write

X

20H

2

Erase Verify(5)

2

Write

EA

AOH

Read

X

EVD

Set-up Program/Program(6)

2

Write

X

40H

Write

PA

PO

Program Verify(6)

2

Write

X

COH

Read

X

PVD

Reset(7)

2

Write

X

FFH

Write

X

FFH

NOTES:
'
1. BUB operations are defined in Table 2.'
2. IA = IdentHler address: OOH for manufacturer code, 01 H fdr device code.

EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
'3.10 = Data read from location IA during device Identification (Mfr = 89H, Device = BSH).
EVD 7 Data read from location EA during erase verify.
,
PO = Data to be programmed at location PA. Data is latched on the risingeqge of Write-Enable.
PVD =' Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent 10 command, two read operations access manufacturer and device codes.
5, Figure 5 illustrates the Qulck-Erase™ algorithm.
"
6. Figure 4 Illustrates the Quick-Pulse Programmlng™ algorithm.
7. The second, bus cycle must be followed by the desired command 'register write.

int:el.,

A28F512

high voltage is applied to the Vpp pin. In the absence
of this high voltage, memory conte,nts are protected
against erasure. Refer to A.C. Erase Characteristics
and Waveforms for specific timing parameters.

Read Command

While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.

Erase-Verify COmmand

The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The' address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse. '

The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F512, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the A.C. Read
Characteristics and Waveforms for specific timing
parameters.

The 28F512 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.

Intelligent Identifier Command

The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte, in the array until a byte does not return FFH
data, or the last address is accessed.

Flash-memories are intended for use in applications
where the local CPU ,alters memory contents. As
such, manufacturer- and device'codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
The 28F512 contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address ,OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
B8H. To terminate the operation, it is necessary to
write another valid command into the register.

In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once, all bYtes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 5, the Quick-Erase™ algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F512.
Refer to A.C. Erase Characteristics and Waveforms
for specific timing parameters.

Set-up Erase/Erase Commands

Set-up Program/Program Commands

Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the riSing edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).

Once, the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable' also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used, to write the
program-verify command. Refer to A.C.Program-

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when

5-32

infel .

A28F512

ming Characteristics and Waveforms. for specific
timing parameters.

ty of oxide defects in the region. Finally, the peak
electric field during erasure is approximately 2 MV/
cm lower than EEPROM. The .lower electric field
greatly reduces oxide stress and the probability of
failure-increasing time to wearout by a factor of
100,000,000.

Program-Verify Command
The 28F512 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.

The device is programmed and erased using Intel's
Quick-Pulse Programming. and Quick-Erase algorithms. -Intel's algorithmic approach uses a series of
operations (pulses), along with byte verification, to
completely and reliably erase and program the device.

The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation. with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.

QUICK-PULSE PROGRAMMING ALGORITHM

The 28F512 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data melms that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4, .
the 28F512 Quick-Pulse'Programming™ algorithm,
illustrates how commands' are combined with bus
operations to perform byte programming. Refer to
A.C. Programming Characteristics and Waveforms
for specific timing parameters.

The Quick-Pulse Programming algorithm uses programming operations of 10 ,..,S duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programmil1g and byte verification is
performed with Vpp at high voltage. Figure 4 illustrates the Quick.Pulse Programming algorithm.
QUICK-ERASE ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop floVl', similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge. from all bits in the array.

Reset Command
A reset command is provided as a means to safely
abort the erase- or program·command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.

Erasure: begins with a read of memory contents. The
28F512 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers haile implemented redundancy schemes, reducing cycling failures to insignificant lev~ls. However, redundancy requires that cell size be doubled- .
an expensive ~olution.
.
Intel has designed extended cycling capability into
its ETOX-II flash memory technology; Resulting im~
provements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probabili-

5-33

For devices being erased and. reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
QuiCk-Pulse Programming algorithm, in approximately one second.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encounte~ed. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in cine seconds. Figure 5 illustrates the Quick-Erase algorithm.

A28F512

Bus
Command
Operation

Standby

Comments

Waitfor VPP Ramp to VPPH(1)

Initialize Pulse-Count

Write

Set-up
P.rogram

Data = 40H

Write

Program

Valid Address/Data

Standby
Write

Program(3)
Verify

Data = COH; Stop~ Program
Operation(2)
-

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write

Standby

290265-5
NOTES:
1. See DC Characteristics for value-of VpPH. The VPP
power supply can be hard-wired to the device or
switchable. When VPP is switched, VpPL may be
ground, no-connect with a resistor tied to ground, or
less than 6.5V. Refer to Principles of Operatibn.
2. Refer to Principles of Operation.

Duration of Program
Operation (twHWH1)

Read

Data = OOH, Resets the
Register for Read Operations
Wait forVpp Ramp to VppL(1)

3. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 4. 28F512 Quick-Pulse Programming Algorithm

5-34

infel .

A28F512

Bus
Command
Operation

Comments
Entire memory must
before erasure

=

OOH

Use Quick-Pulse
Programming Algorithm
(Figure 4)
Standby

Wait for Vpp Ramp to VPPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data

=

20H

Write

Erase

Data

=

20H

Standby
Write

Duration of Erase Operation
(tWHWH2)
Erase(3)
Verify

Standby

tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Read

Standby

290265-6
NOTES:
1. see DC Characteristics for value of VPPH. The Vpp
power supply can be hard-wired to the device or
switchable. When Vpp is switched, VPPL may be
. ground. no-connect with a resistor tied to ground. or
less than 6.5V. Refer to Principles of Operation.
2. Refer to Principles of Operation.

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(2)

Data = OOH, Resets the
Register for Read Operations
Wait forVpp Ramp to VPPL(1)

3. Erase Verify is performed only after Chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-

vice..

Figure 5. 28F512 Quick-Erase Algorithm

5-35

infel .

A28F512

Place the high-frequency, low-inherent-inductance _
capacitors as close as possible to the devices. Also,'
for every eight devices;' a 4:7 p.F electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printed- ,
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
.

DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power' dissipation
and,
"
b. complete assurance that output bus contention
, will not occur.

Vpp Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
Qoard designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

To efficiently use these two control inputs, an addr~ss-decoder output ,should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power ,standby condition.

Power Up/Down Protection
Power Supply Decoupllng

The 28F512 is designed to offer protection against
accidental erasure or programming, caused by spurious system-level signals that may exist during power
transitions. Also, with its control register architecture, alteration of memory contents only occurs after
successful completion of the two-step command sequences. Power supply sequencing is not required.
Internal circuitry of the' 28F512 ensures that the
command register architecture is reset to the read
mode on power up.

Flash memory power-switching characteristicsrequire careful device decoupling. System designers
are interested in three supply current (lee) issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
,
Two-line control and proper decoupling capacitor
selection. will suppress' transient voltage peaks.
Each device should have a 0.,1 p.F ceramic capacitor
,connected between Vee and Vss, and between Vpp
and Vss.
'

I

A system designer must guard against active writes
for Vee voltages above the VLIVce

±10

,."A

VPP

s:

Vce
Vee

int:eL

A28F512

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
\

Symbol

Parameter

Notes

Limits
Min

Typ

Max

Unit

Test Conditions

IpP2

VPP Programming
Current

1,2

8.0

30

mA

VPP = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

4.0

30

mA

VPP = VpPH
Erasure in Progress

IpP4

VPP Program Verify
Current

1,2

2.0

5.0

mA

VPP = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify
Current

1,2

2.0

5.0

mA

VPP = VpPH
Erase Verify in Progress

VIL

Input Low Voltage

..,..0.5

VIH

Input High Voitage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VID

As inteligent Identifier
Voltage

lID

Vee 10 Current

0.8
Vee

+ 0.5

0.45

V

IOL = 2.1 rnA
Vee = Vee Min

V

IOH = -2.5 mA
Vee = Vee Min

13.00

V

As = VID

10

30

mA

As = VID

90

500

J-tA

2.4
11.50
1

VPP 10 Current

V
V

VpPL

VPP during Read·Only
Operations

0.00

6.5

V

VpPH

VPP during Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write Lock
Voltage

2.5

NOTE: Erase/Program are
Inhibited when VPP = VPPL

V

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Notes

limits
Min Typ Max

Unit

Test Conditions

III

Input Leakage Current

1

±1.0 J-tA Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

1

±10

J-tA Vee = Vee Max
VOUT = Vee or Vss

lees

Vee Standby Current

1

50

100

J-tA Vee = Vee Max
. CE = Vee ±0.2V

lec1

Vcc Active Read Current

1

10

30

mA Vcc = Vec Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

ICC2

Vce Programming Current

1,2

1.0

30

mA Programming in Progress

lec3

Vcc Erase Current

1,2

5.0

30

mA Erasure in Progress

ICC4

Vcc Program Verify Current

1,2

5.0

30

mA VPP = VPPH Program Verify in Progress

ICC5

Vcc Erase Verify Current

1,2

5.0

30

mA VPP = VPPH Erase Verify in Progress

5·39

..

int:el.

A28F512

DC CHARACTERISTIC8-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Ipps

Vpp Leakage Current

1

IpP1

Vpp Read Current or
Standby Current

1

,

,Typ

Min

Unit

Test Conditions

,.,

Max
±10

90

200

/LA
/LA

±10

Vpp S;'Vee
Vpp> Vee'
Vpp S; Vee

IpP2

Vpp Programming Current

1,2

8.0

30

mA

Vpp = VPPH
PrOgramming in Progress

Ipp~

Vpp Erase Current

1,2'

4.0

30

mA

Vpp =VPPH
Erasure in Progress

IpP4

Vpp Program Verify
Current

1,2

2.()

5.0

mA

Vpp= VPPH
Program Verify in ProgreS$

IpP5

Vpp Program Erase Verify
Current

1,2

2.0

5.0

mA

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

Output High Voltage

0.8
Vee

V

+ 0.5

0.45
0.85 Vee

VIO

A9 Intelligent Identifier
Voltage

110

Vee 10 Current

1

110

Vpp 10 Current

1

VPPL

Vpp during Read-Only
Operations

0.00

VPPH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write Lock.
Voltage

2.5

"

V
V

IOL = 2.1 rnA
Vee = Vee Min

V

IOH = - 2.5 mA,
Vee = Vee Min
IOH = -100 /LA,
Vee = Vee Min

Vee - 0.4

VOH2

"

11.50

13.00

V

10

30

rnA

A9 = 10

90

500

rnA

A9 = 10

6.5

V

NOTE: Erase/Programs are
Inhibited when Vpp = VPPL

V

Vpp = 12.0V

'

'

12.60

V

CAPACITANCE(3) TA = 25°C, f = 1.0 MHz
Symbol

Limits

Parameter
Min

Unit

Conditions

Max

CIN

Address/Control CapaCitance

8

pF

COUT

Output Capacifance '

12

pF

: VIN = OV
VOUT = OV

NOTES:
1. All currents are il'1RMS unless otherwise noted. Typical values' at Vee = 5.0V, Vpp = 12.0V, T = 2SOC.
2. Not 100% tested: characterization data available.
'
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but are based on a limited number of samples from production lots.

5-40

intet

A28F512

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.4V

.!:~

INPUT
O.4SV

~~1N914
2.0V>

OUTPUT

O.BV

I

TEST POINTS

3.3K

DEVICE
UNDER

290265-7

AC Testing: Inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Testing measurements are made at 2.0V for a logic
"1" and 0.8V for a logic "0". Rise/Fall time,;: 10 ns.

TEST

It--+-o OUT
I

i

CL=100pF

290265-8
CL = 100pF
CL Includes Jig Capacitance

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) .•..•. 10 ns
Input Pulse Levels ................ 0.45Vand 2.4V
. InputTiming Reference Level .....•. 0.BVand 2.0V
Output Timing Reference Level ...... O.BV and 2.0V

AC CHARACTERISTICS-Read-Only Operations(2)
Versions
Symbol

Characteristic

Notes
3

Max

120

28F512·150
Min

Max

150

Unit

tAVAV/tRC

Read Cycle Tip1e

tELQV/tCE

Chip Enable
Access Time

120

150

ns

ns

tAVQV/tACC

Address Access Time

120

150

ns

tGLQV/tOE

Output Enable
Access Time

50

55

ns

tELQXltLZ

Chip Enable to
Output in Low Z

3

Chip Disable to
Output in High Z

3

tGLQXltOLZ

Output Enable to
Output in Low Z

3

~HQZ/tDF

Output Disable to
Output in High Z

4

tOH

Output Hold from
Address, CE,
or OE Change(1)

3

'tEHQZ

tWHGL

0

0

55

Whichever occurs first.
Rise/Fall Time ~ 10 ns.
Not 100% tested characterization data available.
Guaranteed by design.

5-41

ns
ns

0
30

Write Recovery Time
before Read

ns

O·
50

NOTES:
1.
2.
3.
4.

28F512·120
Min

35

ns

0

0

ns

6

6

/J-s

_.

(:
~

Vcc POWER-UP

STANDBY'

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED

DATA VALID

J

ADDRESSES

STANDBY
---

\.

----

'

VCC POWER-DOWN

ADDRESSES STABLE

,
,.

tAVAy{tRC)

-,

:!!

ID
C

iil

CE (E)

,

~

---

'

---

'

l;
~

!.
0'1
J,..
I\)

DE (G)'

,

~
3

I'

.

1/1

~

:u

::a.

t WHGL

, WE (W)

~

N

\.

g

!0-

~

""en

.,

toH
II""b
DATA (00)

HIGH Z

~«

«(

I')}}}P
I-

~./

Vee

OV

tAVQy(tACC)

-I

dcce,1
OUTPUT VALID

q«''1

,
290265-9

A28F512

AC CHARACTERISTICS-Write/Erase/Program Operations(1, 3)
Versions

Notes

Symbol

Characteristic

tAVAv/twc

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tOVWH/tOS

Data Set-up Time

tWHOX/tOH

Data Hold Time

tWHGL

Write Recovery Time
before Read

tGHWL

Read Recovery Time
before Write

tELwL/tCS

Chip Enable
Set-UpTime before Write

28F512-120
Max

Min

28F512-150
Min

Unit

Max

120
0
60
50
10
6

150
0
60
50
10
6

p.s

0

0

p.s

2

20

20

ns

0
80
80

ns

ns

2

ns
ns
ns
ns
ns

tWHEH/tcH

Chip Enable Hold Time

tWLWH/twp

Write Pulse Width(2)

2

tELEH

Alternative Write(2)
Pulse Width

2

0
80
80

tWHWL/twPH

Write Pulse Width High

tWHWH1

Duration of
Programming Operation

4

20
10

20
10

p's

tWHWH2

Duration of Erase Operation

4

tVPEL

VppSet-Up
Time to Chip Enable Low

9.5
1.0

9.5
1.0

ms

ns
ns

ms

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
. .
3. Rise/Fall time"; 10 ns.
4. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits

Parameter
Min
Chip Erase Time
Chip Program Time
Erase/Program Cycles

1,000

Notes

Unit

Comments

Typ

Max

1

60

1,3,4,6

Sec

Excludes OOH Programming
Prior to Erasure

1
Hio,oOO

6.25

1,2,4
1,5

Sec

Excludes System-Level Overhead

Cycles

NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at
T = 25·C, Vpp = 12.0V, Vee = 5.0V.
2. Minimum by1e programming time excluding system overhead is 16
(10
program + 6
write recovery), while
x 25 loops allowed by algorithm). Max chip programming time is specified lower than the
maximum is 400 ",s/by1e (16
worst case allowed by the programming algorithm since most by1es program significantly faster than the worst case by1e.
3. Excludes OOH programming prior to erasure.
.
4. Excludes system-level overhead.
5. Refer to RR-60 "ETOX Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at
T = -40·C, 1,000 cycles, Vpp = 11.4V, Vce = 4.5V.

"'S

"'S

5-43

"'S

"'S

A28F512

99.9

/

,/

/'

99

V
,

L

1.25

,

/

,
,,

/

,.'
20

~

«I

50

60

-- .LV

70

110

L,

20

V '
,,

,

.

..

II"

:

,

10

I

5

)

J

" ,,

30

-'

.//
,
V/

L

50
40

v

1

V

1
10

I

I

1

60

,,

/

IS

80

/:: .....

,,~,/

V

L

90

70

~

1]5

lL

95

/

t
... ..l-v

/

.1
90

100

110

120

1

1~

TEMP(OC)

1.25 1.5 1.752 2.252.5

7.5

5

to

ChIp Program TIm. ( •• c)

-1kCyc:les
----10k Cycles
--_. lOOk Cycles

- - - 12V; 10 kc; 23"C
••••••• tt.4V; to kc; 70"C
_ •• 12V; 100 kc; 23"C

290265-17

290265-18

Figure 7, 28F512 Typical Program Time at 12V

Figure 8. 28F512 Typical Programming Capability

See Note 1, Page 5'43.

5-44

int:eL

A28F512

99.9

1.9
1.9

'.

1.7

\

1.6

[\

1.5

1.3

::IE

>=

,

,,

1

:;:

.1

u

1.0

,

"

"-

o.9

70

,

f'

"

,,

,

,

,

.......

r-..

"

"

5

"

,

"t- ,.........

o.6

0

.

"

"

.

1

ro

10

20

30

«I

50

60

70

TE~P

so

o.1
0.3

90 100 110 120 130 1«1

/ ,

,"
,'1

/ , 0'/
,,

0

,

,,

o.7

.5

I

0

b..

0.9

I

0
0

,

,,

"r,.I
/ 'L
' ,
I

80

,,

/ ,",

//1
:t

' .t"
0.5

0.7

3
CHIP ERASE TI~E

(OC)

- - l k Cycles
- - - - 10k Cycles
._-_. tOOk Cycles

,

,,',

/

90

"

,,

... 1.2

..a

V,'11,

95

.

"U' 1.4

~

IJ~ , "

99

4 5 6 78910

(s.c)

- - - 1 2 V ; 10 kc; 230C
- - - - 11.4V; 10 kCi ooc
------- 12V; 100 kc; 230C

290265-19

290265-20

NOTE:
Does not include Pre-Erase program.

NOTE:
Does not include Pre-Erase program.

Figure 9. 28F512 Typical Erase Time at 12V

Figure 10. 28F512 Typical Erase Capability

See Note 10 Page 5-43.

5-45

20

_.

Vee POWER-UP
STANDBY

a:

PROGRAY COIlIlAND
LATCH ADDRESS
a: DATA

SET- UP PROGRAM
COMMAND

PROGRAIIMING

VERIFY
COMMAND

PROGRAM
VERIFICATION

€:

STANDBY /
Vee POWER-DowN

~

ADDRESSES

CE (E)

"...c

iii
CD
....

:'"

liE (G)

)10

-~rl-t~P~('"'~ ~

0

:e
DI

~

...0'

1

.1.

tWHGL

WE (W)

3

1/1

~
N

~ ...0'

m

CD
."

en

'V

«3

DATA (OO)

CO

iii

HIGH Z

/

I

I~

~

3

2.

~

....

-g;&,!~'oIP~

N

\aOx Vee

±10 p.A Vpp:5: Vee
5-61

inteL

A28F010

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

limits

Notes

~In Typical

.

Unit

Test Conditions

Max

IpP2

VPP Programming Current

1,2

B.O

SO

mA VPP = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

4.0

SO

mA VPP = VPPH
Erasure in Progress

IpP4

VppProgram Verify Current

1,2

2.0

5.0

mA VPP = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

1,2

2.0

5.0

mA VPP = VPPH
Erase Verify in Progress

Vil

Input Low Voltage ..

VIH

Input High Voltage

VOL

Output Low Voltage

VOH1

Output High Voltage

VIO

Ag Intelligent Identifer Voltage

110

Vee ID Current

-0.5

O.B

2.0

V

0.45

V
V

2.4
11.50
1

VPP ID CURRENT

1S.00
SO

mA

90

500

/LA

VPP during Read-Only Operations

0.00

6.5.

VpPH

VPP during Read/Write Operations

11.40

12.60

Vee Erase/Write Lock Voltage

IOl = 2.1 mA
Vee = Vee Min

'.
.

IOH;'" -2.5mA
Vee = Vec Min

V Ag

10

VPPl

VlKO

V

+ 0.5

Vee

Ag

=

VID

=

VIO

.

V NOTE: Erase/Program are
Inhibited whenVpp = VpPl
V
V

2.5

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

limits

Notes
Min

Typical

Unit

Test Conditions

Max

III

Input Leakage Current

1

±1.0

/LA

Vee = Vee Max
VIN = VccorVss

ILO

Output Leakage Current

1

±10

/LA

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1

50

100

/LA

Vee = Vee Max
CE = Vee ±0.2V

lee1

Vee Active Read Current

1

10

SO

mA

Vee = Vee Max, CE = Vil
f = 6 MHz, lOUT = 0 mA

'.

lee2

Vee Programming Current

1,2

1.0

SO

mA

Programming in Progress

lee3

Vee Erase Current

1,2

5.0

SO

mA

Erasure in Progress

IpPS

VPP Leakage Current

1

±10

/LA

VPP::;; Vee

IpP1

VPP Read Current or
Standby Current

1

/LA

Vpp> Vee

90

200
±10

5-62

VPP::;; Vee

intel·

A28F010

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Paramllter

-Notes

Limits
Min

Typical

Max

Unit

Test Conditions

IpP2

VPP
Programming
Current

1,2

B.O

30

mA

VPP = VPPH
Programming in Progress

IpP3

VPP Erase
Current

1,2

4.0

30

rnA

VPP = VPPH
Erasure in Progress

IpP4

VPP Program
Verify Current

1,2

2.0

5.0

rnA

VPP = VPPH Program
Verify in Progress

IpP5

VPP Erase Verify
Current

1,2

5.0

5.0

rnA

VPP = VPPH
Erase Verify in Progress

VIL

Input Low
Voltage

-0.5

O.B

V

VIH

Input High
Voltage

0.7 Vee

VOL

Output Low
Voltage

VOH1

Output High
Voltage

Vee

+ 0.5

0.45

V
V

O.BSVee

V

VIO

As Intelligent
Identifier Voltage

110

Vee 10 Current

IOH = -2.5 rnA,
Vee = Vee Min
IOH = -100 p.A,
Vee = Vee Min

Vee - 0.4

VOH2

IOL = 2.1 rnA
Vee = Vee Min

11.50

13.00

V

1

10

30

rnA

As

1

90

= 10
= 10

110

VPP 10 Current

500

Jl.A

As

VPPL

VPP during ReadOnly Operations

0.00

6,5

V

NOTE: Erase/Programs
are Inhibited when
Vpp = VPPL

VPPH

Vppduring
Read/Write
Operations

11.40

12.60

V

VLKO

Vee Erase/Write
Lock Voltage

CAPACITANCE(3) TA
Symbol

2.5

= 25°C, f =

V

1.0 MHz
Limits

Parameter
Min

Unit

Conditions

Max

CIN

Address/Control Capacitance

e

pf

VIN = OV

CoUT

Output Capacitance

12

pF

VOUT = OV

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T= 25°C.
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but are based on a limited number of samples from production .lots.

5-63

.infel.

A28F010

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2~4V

1.3'1 :.

INPUT
O.4SV

lN914

3.3K·

2.0V __
O.BV .--- TEST POINTS

OUTPUT

.....--+---0 OUT'

I

290266-7

.

Ci.=100pF

AC Testing: Inputs are driven at2.4V for a logic "1" and 0.4SV for
a logic "0". Testing measurem~nts are made at 2.0V for a logic
"1" and O.BV for a logic "0". Rise/Fall time.,:; 10 ·ns.

290266-B
Ci. = 100 pF
CL includes Jig Capacitance

AC TEST CONDITIONS'
Input Rise and Fall Times (10% to 90%) .•... slO ns
Input Pulse Levels ........... ; ..•. 0.45Vand 2.4V
Input Timing Reference Level ....... O.BV and 2.0V
Output Timing Reference Level •. '.... O.BV and 2.0V

AC CHARACTERISTIC5-Read;.Only Operations(2)
Versions
Symbol
tAVAV/tRC
tELQV/tCE
tAVQV/tACC .

Notes

~haracteristic

•Read Cycle Time

3

28F010~150

Min
150

Chip Enable Access Time
• Address A9cess Time

tGLQV/toE

Output Enable
Access Time

tELQX/tLZ

Chip Enable to
Qutput in Low Z

3

tEHQZ

Chip Disable to
Output in High Z

3

lGLQX/tOLZ

Output Enable to
Output in Low Z

3

tGHQZ/tOF

Output Disable to
Output in High Z

'4

tOH

Output Hold from Address,
CE, or OE Change

1,3

tWHGL

Write Recovery Time
before Read

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time :s; 10 ns.
3. Not 100% tested: Characterization data available.
4. Guaranteed by design.

5-64

Max

Unit
ns

150

ns

150

ns

55 .

ns

0

ns
55

0

ns.
ns

'.
35

ns

0

ns

6

JJ.s

l
•

Vee POWER-UP

STANDBY

ADDRESSES

DEVICE AND
ADDRESS SELECTION

.

OUTPUTS ENABLED

DATA VALID

ADDRESSES STABLE

,

I·

ic

ii1

STANDBY

---

\.

---

'

Vee POWER-DOWN

·1

tAVAy(tRC)

CE (E)
,

!»

---

'

---

'

~
.=5

!

OE (G)

en ~
cD :3
en lit

,
\.

~

2J

i

twHGL
J

---

:::s

~
....
Q

\.

WE (Vi)

~

i

~

-I

toH
DATA (00)·

II""b

---

d({(J

(I

OUTPUT VALID
---

q ( , , '1

(1« «

HIGH Z

lit

1\

I-

~/
VCC
OV

tAYOy(tACC)

> > )

)

I>

-I

,
290266-9

·intel~

A28F010

AC CHARACTERISTICS-Write/Erase/Program Operations(1,3)
Versions

28F010-150

Notes
Characteristic

Symbol

Min

Unit

Max

150

ns

0

ns

tAVAV/twc

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAXltAH

Address Hold Time

60

ns

tOVWH/tOS

Data Set-up Time

50

ns

tWHoXltOH

Data Hold Time

10

ns

tWHGL

Write Recovery Time before Read

6

p.s

0

,p.s

20

ns

0

ns

2

tGHWL

Read Recovery Time before Write

tELwL/tcs

Chip Enable
Set-Up Time before Write

tWHEH/tCH

Chip Enable Hold Time

tWLWH/twp

Write Pulse Width(2)

2

80

ns

tELEH

Alternative Write(2)
Pulse Width

2

80

ns

tWHWL/twPH

Write Pulse Width High

tWHWH1

Duration of Programming Operation

4

10

p.s

tWHWH2

Duration of Erase Operation

4

9.5

ms

tVPEL

Vpp Set-Up
Time to Chip Enable Low

1.0

ms

2

20

..

ns

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
.
2. Chip-Enable Controlled Writes: Writ~operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip~Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
3. Rise/Fall time s: 10 ns.
4. The internal stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum specification.
. .

ERASE AND PROGRAMMING PERFORMANCE
Parameter

Limits

Notes
Min

Chip Erase Time
Chip Program Time
Erase/Program Cycles

1,3,4,6
1,2,4
1,5

,

..

1,000

Unit

Typ

Max

1

60

2

12.5

100,000

Comments

Sec

Excludes OOH Programming
Prior to Erasure

Sec

Excludes System-Level Overhead

Cycles

NOTES:
1. "Typicals" are riot guaranteed, but based on a limited number of samples taken from production lots. Oata taken at
T = 25·C, Vpp = 12.0V, Vee = 5.0V.
.
2. Minimum byte programming time excluding system overhead is 16 ,..sec (10 ,..sec program + 6 ,..sec write recovery),
while maximum is 400 ,..sec/byte (16 ,..sec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program Significantly faster than the worst case
byte..
3. Excludes OOH programming prior to erasure.
4. Excludes system-level overhead.
5. Refer to RR-60 "ETOX Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.
6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at
.
T = -40·C, 1,000 cycles, Vpp = 11.4V, Vee == 4.5V.

5-66

intel .

A28F010

99 .9 .

,

.5

,/V
9

/

5

V

a /
7
a
a
a
a
a
a I

L

"

,

7

7,,'
,
,

,

,/.,/''/'

.I

Y

' "

/

a

",."

,,

,,

6

/

l/ ""

./

,, "
5

.

,

....1--...

15

.

l,l

10

/

-

,I

, "

2.5
1

3

3.5 4 4.5 5

15

10

.

2

20

"
o w

~

,
I

,

/1

1

.... ..-

V'

1/

5

2.5

/

~

~

~

ro ro

,

_.

/1'

"

/

I
/
~

~

~

~

~

~

TEMP (e)

Chip Program TIme (Sec)

- - l k eyel..

-.- - 1 2 V : 10 ke: 23e
• ••••• -11.4V: 10 ke: 70e
- - - - 12V: 100 ke: 23e

. - - . 10k eyel" ,
- - - 10ak Cycle.

290266-18

290266-17

Figure 8. 28F010 Typical Program Tlme.at 12V

Figure 7. 28F010,TyplcalRrogrammlng Capability
See Note 1, Page 5-66.

5-67

A28F010

99

1,1
95

90

V

80

70
60
50
40

,

20

0.1

0.5 0.7

~

, '. "

.
(.-

.

f\

,l~1

\.

aU

...

II>

,

~2.2

~2.0

,"/

~

U1.8

1.15

'I

"

1.4

11
1

1\

2.6

',

,,.

1.2

3

,

2.8

1IL
Iii

10

1

L

I l/
I '

30

5

/
IL
:..L

V'

'3.2

4 5 6 78910

20

"

r\

f'

".

l'

f'.
"

r--.. f'..

,1'-

.... ....
.....

" r-::

~

"'1""

r-..

~ ~~.;

........

~

.

T""-I"-

1.0

30

o

CHIP ERASE nME (SEC)

'12V; 10 kc;23C
11.4V;10 kc;OC
•••••• 12V;100,kc;UC

10 20 30 40 50 60 70 80 80 100 110 120 130 140
TEMP ("1:)
-lkeyclll
----10k Cycle.
'-I00kCyclo.

290266-19

290266-20

Figure 9. 28F010 Typical Erase CapabilitY
See Note 1; Page 5·66.

Figure 10. 28FO~OTyplcal Er:aseTlme at 12V

5·68

_.

Vee POWER-UP at
STANDBY

PROGRAII COMMAND
LATCH ADDRESS
at DATA

SET- UP PROGRAM
COMMAND

PROGRAMMING

VERIFY
COMMAND

PROGRAM
VERIFICATION

l

STANDBY I
Vee POWER-DOWN

•

ADDRESSES

"ft

..

CE (E)

~

c:

...
CD

:-"

~

OE (el)

=e

-..
~

CD

0

:I

....
"

M(W)

'0'"
~
CO
0

fa

DATA (DO)

:3

fa

0

'a
CD

i

:::J

'"

....o

HIGH Z

iil

~.

E
~

tOH

tELQX(tLZ)
tELQy(tcE>

5.0V
Vee
OV

tYPEL

YpPH
Vpp
VpPL

Alternative Write Timing

tELEH

CE(E)

WE (Vi)

\

/

290266-14

_.
Vee POWER-UP
STANDBY

a:

SET- UP ERASE
COMMAND

ERASE VERIFY
COMMAND

ERASURE

ERASE COMMAND

ERASE
VERIF1CAnON

STANDBY /
Vee POWER-DOWN

€:
~

ADDRESSES -

CE (E)

i

~

...iii
~

lil

-..~
-..

OE (G)
tWHWH2

CD

t WHGL

'GHQZ\'DFI

~ 1/13
0

at

"11

....0
0

WE(W)

0

t WLWH (twp) .
..
t
-. (t ) toLQvCtoE)
WLWH WP
I
tOVWH (tos)
tovwH(tos)l
toLQX(toLZ)
twHOX (tDH)
_r-tWHDX(tDH)

1--.r-

m

iii
1/1
CD

0

'U
CD

-

~
~

0

DATA (DO)

HIGH Z

iii

tELQX(tLZ)

0'

::::II
1/1

tELQy(tcE)

5.0V

Vee

OV

)

VpPH
Vpp

1--

r

\
!

,

..

VpPL - - - "
290266-15

infel .

A28F010

Ordering Information
IAlpl2lslrlolll01-lllsl01

LJLf

L...-~

LpACKAGE
P P-DIP
N 32-LEAD PLCC

=

-AUTOMOTIVE TEMP
-40"<: to + 125°C

L------ACCESS SPEED (ns)
150ns
290266-16

Valid Combinations;
AP28F010-150

AN28F010-150

ADDITIONAL INFORMATION

Order Number

ER-20, "ETOXTMII Flash Memory Technology"

294005

ER-24, "The Intel 28F010 Flash Memory"

294008

RR-60, "ETOXTM Flash Memory Reliability Data Summary"

293002

AP-316, "Using Flash Memory for In-System Reprogrammable
Nonvolatile Stora:ge"

292046

AP-325, "Guide to Flash,Memory Reprogramming"

292059

REVISION HISTORY
Description
Changed Erase/Program Cycles to 1,000 minimum

5-71

A27C256
256K (32K x 8) CHMOS EPROM
Automotive
Extended Automotive Temperature
• Range:
-40°C to + 125°C

•
•
•
•

CHMOS/NMOS Mlcrocontroller and
Microprocessor Compatible
- Universal 28 Pin Memory Site, 2-line
Control
120 ns Maximum Access Time
CMOS and TTL Compatible
Low Power
- 30 mA Max. Active
-100 p.A Max. Standby

Programming
• -FastQuick-Pulse
Programming Algorithm

•
•

-:- Programming Time as Fast as 4
Seconds
Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum Latch-up Immunity through
EPI Processing
Available in 28-Pin Cerdlp Package
- 28-Pin Plastic Dip Package
- Compact 32-Lead PLCC

Intel's A27C256 is a 5V only, 262,144-bit Erasable Programmable Read Only Memory, organized as 32,768
words of 8 bits. Its standard pinouts provide for simple upgrades to 512 Kbits in the future in both DIP and
SMT.
The A27C256 is ideal in embedded control applications based on advanced 16-bit CPUs. Fast 120 ns access
times allow no-wait-state operation with the 12 MHz 80286. The A27C256 also excels in reprogrammable
environments where the system designer must strike an optimal density/performance balance. For example,
bootstrap and diagnostic routines run 1-wait-state on a 16 MHz 386TM microprocessor.
Intel offers. two DIP profile options to meet your prototyping and production needs. The windowedceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
In addition to the JEDEC 28-pin DIP package, Intel also offers a 32-lead PLCC version of theA27C256. This
one-time-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The A27C256 is equally at home in both TTL and CMOS environments. The Quick-Pulse programming algorithm improves speed as much as 100 times over older methods, further reducing cost for system manufacturers.
.
DATA OUTPUTS
0 0 -0,

Vee 0...---.

GND_

Ao-AI4 {

ADDRESS
INPUTS

212,144 BIT

CEll MATRIX
290120-1

Figure 1. Block Diagram

5-72

September 1992
Order Number: 290120-005

infel·

A27C256

PIn Names
Ao-A15

00-0 7
OE
CE

PGM
NC
DU

27512

271281. 27841.

27C512 27C128 27C84
A,S
A'2
A7

Vpp

A'2
A7

27321. 2716

ADDRESSES
OUTPUTS
OUTPUT ENABLE
CHIP ENABLE
PROGRAM
NO CONNECT
DON'T USE

A27C256

2718

27321.

A7

27512

27C84 27C128 27C512

Vee
J5GFJ

Vpp

A'2
A7

27C64 271281.

A7

Vee

Vee

NC

As
Ag

As

As

Ae

Ag

Vee

Vee

J5GFJ

Au

A'3
As
Ag

A,:!
As
Ag

As

As

As

As

As

A5

A5

A5

A5

A5

Pv.

Pv.

A4

Vpp

A3

A3

DE

A"
DElVpp

A"
DE

A"

A3

Pv.
Aa

A4

A3

DE

A"
DElVpp

A2

A2

A2

A2

A2

A,o

A,o

A,o

A,o

A,o

A,

A,

A,

A,

A,

'OE

a:

C!:

C!:

'OE

07

07

07

07

Os

Os

06

05

04
03

Ao

Ao

Ao

Ao

Ao

07

00

00

00

00

Os

0,

0,

00
,0,

0,

0,

05

Os
05

02

O2

02

02

02

04

04

04

05
04

GND

GND

GND

GND

GND

03

03

03

03

290120-2

FIgure 2. DIP PIn ConfiguratIon
27C,",

o

32 LEAD PLCC

0.450" X 0.550"
(11.430 X 13.970)
(1otILLlMETERS)
TOP VIEW

290120-3

FIgure 3. PLCC Lead ConfIguratIon

5-73

05

intel .

A27C256

AUTOMOTIVE TEMPERATURE
EPROMs
The Intel AUTOMOTIVE EPROM family receives additional processing to enhance product characteristics. AUTOMOTIVE processing is available for several densities allowing the appropriate memory size
to match system requirements. AUTOMOTIVE
EPROMs are available with 168 ±8 hour, 125·C
dynamic burn-in using Intel's standard bias configuration. This processing meets or exceeds most industry burn-in .specifications. The AUTOMOTIVE
product family is available in-40·C to 125·C operating temperature range versions. Like all Intel
EPROMs, the AUTOMOTIVE EPROM family is inspected to 0.1 % electrical AQL. This allows reduction or elimination of incoming testing.
'

Vee

D-~"

D-~"o.

~

Options
Speed

07
Os
Os

"
290120-4
l:5E= +5V R = 1 KO vee = +5V
'
Vpp = +?VGND = OV· CE = GND

Packaging
CerDIP

PLCC

PDIP

-120V10

AD

AN

AP

-200V10

AD

' AN

AP

30

H

~.

.

AoILnS
.AtrLJ

•
Au

'

290120-5

Binary Sequence from Ao to A14

Burn-In Bias and Timing Diagrams

5-74

infel·

A27C256

ABSOLUTE MAXIMUM RATINGS·

NOTICE: This is a production data sheet. The specifications are subject to charige without notice.

Operating Temperature •..•.....•• -40°C to 125°C
Temperature Under Bias ..•..•..•• -40°C to 125°C
Storage Temperature ..••.•..•.... - 65°C to 150°C

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is' not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Voltage on Any Pin (except Ag, Vee and Vpp)
with Respect to GND •.•.. , ..••••. - 2V to 7V(2) .
Voltage on Ag with
Respect to GND •..•..•..•.••.. - 2V to 13.5V(2)
Vpp Supply Voltage
with Hespect to GND •.••••..•.. - 2V to 14.0V(2)
Vee Supply Voltage with
Respect to GND •.•••••..•..••.• - 2V to 7.0V(2)
Maximum Junction Temperature (TJ) ~ ••..•.. 140°C

READ OPERATION DC CHARACTERISTICS(1) Vee = 5.0V ±100/0'
Symbol

Parameter

ILl

Input Load Current

ILO

Output Leakage Current

ISB

Vee Standby Current

lee

Vee Operating Current

Ipp

Vpp Operating Current

,

Notes

Min

7

Typ
0.Q1

Max

Unit

Test Conditions

1.0

p.A

VIN = OV to Vee

. ±10

p.A

VOUT = OVtoVee

1.0

mA

CE = VIH

100

p.A

CE = Vee ±0.2V

3

30

mA

CE = VIL
f = 5 MHz

3

200

p.A

Vpp = Vee

4,6

100

mA

0.8

V

los

Output Short Circuit Current

VIL

In'put Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

Vee

+ 0.5

0.45
2.4
5

Vee - 0.7

Vee

V
V

IOL=2.1 mA

V

10H = -:- 400 p.A

V

NOTES:
1. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins isVee + 0.5V which, during transitions. may overshoot to Vee + 2.0V
for periods <20 ns.
.
.
2. Maximum active power usage is the sum Ipp + Icc. Maximum current value is with outputs 00 to 07 unloaded.
3. Output shorted for no .more than one second. No more than one output shorted at a time.
4. Vpp may !Ie connected directly to Vee. or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
5. Sampled. not 100% tested.
6. Typical limits are at Vee = 5V. TA = 25°e.

5-75

•

infel .

A27C256

READ OPERATION AC CHARACTERISTICS(1) VCC= 50V ± 10%
Versions
Symbol

Parameter

Vee ±10%

A27C256-120V10

Notes

Min

Max

A27C256-200V10
Min

Unit

Max

tACC

Address to Output Delay

120

200

ns

tCE

CE to Output Delay

2

120

200

ns

tOE

OE to Output Delay

2

55

75

ns

tOF

OE High to Output High Z

3

30

55

ns

toH

Output Hold from Addresses. CE or
OE Change-Whichever is First

3

0

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tce-toe after the falling edge of CE without impact on tee.
3. Sampled. not 100% tested.

5-76

0

ns

intel .

A27C256

AC WAVEFORMS
V,H _ _ _ _ __
ADDRESS
VALID

ADDRESSES

V,L-----V,H

--------i-'"

V,H

--------i----""'\.

V,L

'OF

V,H
O~

_ _ _ _ _ _ _~HI~OH~Z_ _ _ _ _~~~~

HIOHZ

290120-6

CAPACITANCE(1) TA
Symbol

= 25°C,

f = 1.0 MHz

Parameter

Max

Units

CIN

Address/Control Capacitance

6

pF

VIN

COUT

Output Capacitance

12

pF

VOUT

Conditions

=

OV

=

OV

NOTE: .
1. Sampled, not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM

2.4

AC TESTING LOAD CIRCUIT
1.3V
--

2.0>
0.8

___
TEST POINTS

~

~

2.0
OUTPUT

t lN914

,.;;;0',;;,8_ __

0.45

290120-7
DEYICE
UNDER
TEST

AC test inputs are driven at VOH (2.4 YTn) for a logic "1" and
YOL (0.45 YTTU for a logic "0". Input timing begins at YIH (2.0
YTTU and YIL (0.8 YTTU. Output timing ends at YIH and YIL. Input
rise and fall times (10% to 90%) ~10 ns.

CL ~ 100 pF
CL Includes Jig Capacitance
RL ~ 3.3 Kfl

5-77

1 1\
OUT

1<1--

290120-8

intel .

A27C256

DEVICE OPERATION
The Mode Selection table lists A27C256 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and Ag during Intelligent Iden~fier Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode

Notes

CE

OE

Ae

Ao

Vpp

Vee

X

Outputs

VIL

VIL

X

Vee

Vee

DOUT

Output Disable

VIL

VIH

X

X

Vee

Vee

HighZ

Standby

VIH

X

X

VCC

Vee

HighZ

VIH

X

X

Vpp

Vcp

DIN

X

Vpp

Vcp

Dour

Read

Program

1

2

VIL

.X

Program Verify

VIH

VIL

X

Program Inhibit

VIH

VIH

X

X

Vpp

Vcp

HIGHZ·

Intelligent Identifier
-Manufacturer

2,3

VIL

VIL

VIO

VIL

Vee

Vee

89H

Intelligent Identifier
-Device

2,3,4

VIL

VIL

VIO

VIH

Vee

Vee

8DH

NOTES:
1.X can be VIL or VIH.
2. See DC Programming Characteristics for Vcp, Vppand VIO voltages.
3. A1-Aa,Al0-14 = VIL'
4. Programming equipment may also refer to this device as the A27C256A. Older devices may have device 10 = eCHo

To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control.line. This assures that only selected memory devices have active .outputs while
deselected memory devices are In Standby Mode.

Read Mode
The A27C256 has two control functions, both must
be enabed to obtain data at the o~ts. CE is the
power control and device select.· OE controls the
output buffers to gate data to the outputs. With addresses stable, the address access time (tAee)
equals· the delay from CE to output (teE). Outputs
display valid data toE after OE's falling edge, assuming tAeeand tCE times are met.

Standby Mode
StandbLMode substantially reduces Vee current.
When CE = VIH, the outputs are in a high impedance state, Independent of C5E.

Vec must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur

5-78

intel·

A27C256
allows upgrade using the Vpp pin. Systems designed
for 256 Kbit program memories today can be upgraded to 512 Kbit in the future with no circuit board
changes.
.

Program Mode
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "O's" into the desired bit locations. Although only "O's" are programmed, the data word
can contain both "1's" and ·"O's". Ultraviolet light
erasure is the only way to change "O's" to "1's".

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current IEivels (lcd, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-Line Control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,.,.F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,.,.F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk ca-.
pacitor will overcome voltage slumps caused by PC
board trace inductances.
.

Program Mode is enter1:ld when Vpp is raised to
12.75V. Data is introduced ~applying an B-bit word
to the output pins. Pulsing CE low while DE = VIH
programs that data· into the device.

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V a substantial pro~m margin is ensured. The verify is performed with
CE at VIH. Valid data is available toE after DE falls
low.

Program Inhibit
Program Inhibit Mode allows parallel pr29!amming
of multiple EPROMs with different data. CE-high inhib~rogramming of non-targeted devices. Except
for CE and DE, parallel EPROMs may have common
inpu~.

Intelligent Identifier Mode
The Intelligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programryling equipment to automatically match a
device with its proper programming algorithm.
This mode is activated When ~rogrammer forces
12V + 0.5Von Ag. With CE, OE, A1-As, and A10A14 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
.Angstroms (A). It should be noted that sunlight and
certain flourescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 ,.,.W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently
damaged if the integrated dose exceeds
7258 Wsec/cm 2 (1 week @ 12000 ,.,.W/cm2).

UPGRADE PATH
Future upgrade to the 512 Kbit density is easily accomplished due to the standardized pin configuration of the A27C25e. A jumper between A15 and Vee

5-79

A27C256

290120-9

Figure 4. Quick-Pulse Programming Algorithm

Quick-Pulse Programming ~Igorithm

The entire program pulse/byte verify sequence is
performed with Vpp. = 12.75Vand Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee == Vpp ;", 5.0V.

The QuiQk~Pulse' Programming algorithm programs
Intel's A27C256. Developed to substanti~IIy reduce
programming throughput, this algorithm can program
the A27C256 as fast as 4 seconds. Actual programming time depends on program!TIer overhead ..

a

The Quick-Pulse programming algorithm employs
100 p.S pulse followed by a byte verification to determine when the addressed byte has been sucessfully
programrn~. The algorithm terminates if 25 attempts fail to program a .byte.
'

In addition to the Quick-Pulse Programming' Algorithm, the A27C256 has also been characterized for
the' Quick-Board Programming Al99rithm. Th~
Quick-Board Programming Algorithm was developed
for specific automotive applications using Intel's 1.0 '
micron EPROM products. Contact the factory or an
automotive sales representative for any information
, regarding the Quick-Board Programming AI~orithm:·.

5-80

A27C256

DC PROGRAMMING CHARACTERISTICS TA = 25°C ±5°C
Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

1.0

II-A

= VIL or VIH
CE = VIL
CE = VIL

III

Input Load Current

Icp

VCC Program Current

1

30

rnA

Ipp

Vpp Program Current

1

50

rnA

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2.4

6.5

V

VOL

Output Low Voltage (Verify)

0.45

V

IOL

VOH

Output High Voltage (Verify)

V

IOH

VIO

Ag Intelligent Identifier Voltage

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

3.5
11.5

12.0

12.5

V

2,3

12.5

12.75

13.0

2

6.0

6.25

6.5

V
,V

AC PROGRAMMING CHARACTERISTICS(4) TA = 25°C
Symbol

Parameter

Notes

Min

VIN

= 2.1 rnA
= -2.5 rnA

;I:: 5°C

Typ

Max

Unit

tvcs

Vcp Setup Time

2

2

,...S

tvps

Vpp Setup Time

2

2

II-s

tAS

Address Setup Time

2

II-s

tos

Data Setup Time

2

II-s

tpw

CE Program Pulse Width

95

tOH

Data Hold Time

2

toES

OE Setup Time

toE,

Data Vali~ from ~ ,

toFP

OEHighto
Output High Z

tAH

Address Hold Time

100

105

II-s

2
5
5,6

0
0

II-s
II-s

150

ns

130

ns

,...S

4. See AC Input/Output Reference Waveform for timing
measurments.
'5. toE and tOFP are device characteristics but must. be accommodated by the programmer.
6. Samp,led, not 100% tested.

NOTES:
1. Maximum current value is with outputs 00 to 07 unloaded.
2. Vcp must be applied simultaneously or before Vpp and
, removed simultaneously or after Vpp.
3. When programming, a 0.1 f.LF capacitor is required
across Vpp and GNO to suppress spurious voltage transients which can damage the device.

5-81

'V

:a

8:a
l>

• II

Program'.

I

I-

Program
Verify

•I

l
•

i:
i:

.Read Verify

Z

Q
12...

-+.r--.-;.:....:.:::~f--....;.---

v..

. Addr... ¥IL ~

Ao =V1L

4

At -""",,0-14 .YIl

".

ADDRESS VAUD.-

I

~:

ADDRESS VAUD

~

~
cg
<
rn

v,.

:a

...

en

Data

i:

+---+1-III---+--+--+-...

. 12.75V

~
I\l

ADDRESS STABLE

"..

.....

v.:·ov

J

.~~:

•

Vee

I .

~.

I.·· I I

~
....
n
N
g:

I I I '

~.~
C[
VL

\'IN

O£

,

...
290120-10

A87C257
256K (32K x 8) CHMOS LATCHED EPROM
Automotive

Automotive Temperature
• Extended
Range: -40·C to + 125·C
Mlcrocontroller and
• CHMOS/NMOS
Microprocessor Compatible

•
•
•

Programming
• -FastQuick-Pulse
Programming Algorithm

•

- 87C257-lntegrated Address Latch
- Universal 28 Pin Memory Site, 2-lIne
Control
120 ns Maximum Access Time
CMOS and TTL Compatible
Low Power
- 30 rnA Max. Active
-100 ,...A MAx. Standby

•

- Programming Time as Fast as 4
Seconds
Noise Immunity Features .
,..... ± 10% Vee Tolerance
- Maximum Latch-up Immunity
Through EPI Processing
Available in 28-Pin Cerdip Package
- Compact 32 Lead PLCC
(See Packaging Spec., Order" 231369)

Intel's 87C257 CHMOS EPROM is a 256K-bit 5V only memory organized as 32,768 8-bit word!? It employs
advanced CHMOS"III-E circuitry for systems requiring low power, high speed performance, and noise immuni. ty. The 87C257. is optimized for compatibility with multiplexed address/data bus microcontrollers such as
Intel's 16 MHz 80C51 , 80C152, 80C252, and 8 MHz 80C196.
The 87C257 incorporates latches on all address inputs to minimize chip count, reduce cost, and simplify
design of multiplexed bus systems. The 87C257's internal address latch allows address and data pins to be
tied directly to the processor's multiplexed address/data pins. Address information (inputs Ao-A14) is latched
early in the memory-fetch cycle by the falling edge of the ALE input. Subsequent address information is
ignored while ALE remains low. The EPROM can then pass data (from pins 00-07) on the same bus during
the last part of the memory-fetch cycle.
The 87C257 is offered in a ceramic DIP and PLCC packages, providing flexibility in prototyping and R&D
environments. The 87C257 employs the Quick-Pulse Programming™ Algorithm for fast and reliable programming.
Intel's EPI processing achieves the highest degree of· latch-up protection. Address and data pin latch-Up
prevention is provided for stresses up to 100 mA from -1 V to Vcc + 1V.
.
In order to meet the rigorous environmental requirements of automotive applications, Intel offers the 87C257
in extended Automotive temperature range,· Operational characteristics are guaranteed over the range of
- 40·C to + 125·C ambient.
"HMOS and CHMOS are patented processes of Intel Corporation.
DATA OUTPUTS
0 0-0 7

OUTPUT ENABLE
PROGLOGIC

OUTPUT BUFFERS

CHIP ENABLE
ALE

Ao-A,~

ADDRESS LATCH ENABLE
Y DECODE

Y-GATING

X DECODE

262,144 BIT
CELL MATRIX

ADDRESS
INPUTS

290142-1

Figure 1. Block Diagram

5-83

August 1992
Order Number: 290142-004

infel·

A87C257

Pin Names
Ao-A14
00-0 7
OE
CE
ALElVpp
N.C.
D.U.

87C257

87C64
Vpp
A12
A7
A6
As
~

Aa
A2
A1
Ao
00
01
02
Gnd

ADDRESSES
OUTPUTS
OUTPUT ENABLE
CHIP ENABLE
Address Latch
EnablelVpp
NO CONNECT
DON'T USE
87C64

ALE/V"
Atl
A7

Vee
At.
At3

VCC
PGM
N.C
As
Ag
A11

Ae

Ae
Ae
A4

A.
An

A,

OE

AI
At
Ao
00
Ot
02
GND

AtO

DE

A10

~

ALE/~

07

07
Os
05
04
03

Oe
0&
O.
03
290142-2

Figure 2. DIP Pin Configuration
~~""

.

.

Intel "Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent.

32 LEAD PLCC

.'

,

0.450" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)

TOP VIEW

290142-11

Figure 3. PLCC Lead Configuration
NOTE:
Intel "Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent.

5-84

A87C257

AUTOMOTIVE TEMPERATURE
EPROMs
Intel automotive EPROMs have received additional
processing to enhance product characteristics. The
automotive temperature range is - 40·C to + 125·C
during operating modes.

AUTOMOTIVE OPTIONS
Versions
Packaging Options

Speed
Versions

Cerdlp

PLCC

-120V10

AD

AN

°1

-200V10

AD

AN

°2

vee

Vee

°7
°6

°0

Os
°4
°3
290142-3

DE = SV R = 1 KO Vee = +SV
ALElVpp = + SV Vss = GND CE = GND
PGM

= +sv

30 JJ.s

H

A
nn r
0...1 LJ LJ

290142-4
Binary Sequence from Ao to A14

Burn-In Bias and Timing Diagrams

5-85

int:el.

A87C257

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature During
Read ..•..••..•..••..•..... -40'Cto + 12S'C

Maximum Junction Temperature (TJ) •....••• 140'C

Storage Temperature ..•.•.. ,... - 6S'C to + 150'C

Maximum Thermal Resistance
Junction to Ambient (OJA):
Cerdip . ; •.•..•.......••........•..•.. 40·C/W

Voltage on any Pin with
Respectto Ground ..........••. - 2V to + 7V(1)

NOTICE: This is a production data sheet. The specifications are subject to chang~ without notice.

Voltage on A9 with
Respect to Ground •...•..... - 2V to + 13.SV(1)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions".
may affect device reliability.

Temperature Under Bias ..•..... -40'C to + 12S'C

Vpp Supply Voltage with Respect to Ground
During Programming ..•...•.. - 2V to + 14.0V(1)
Vee Supply Voltage with
Respect to Ground •..••.••..•. -2Vto +7.0V(1)

READ OPERATION
DC CHARACTERISTICS

TIL and NMOS Inputs -40'C ~ TA ~ + 12S'C
Typ(2)

Max

Units

III

Input Load Current

0..D1

±1.0

p.A

VIN = OV.5.5V

ILO

Output Leakage Current

0.D1

±10

p.A

VOUT = OV. 5.5V

ISB

Vee Current Standby
with Inputs-

10

mA

CE = ALE = VIH

1.0

mA

CE = VIH. ALE = VIL

30

mA

CE = VIL. ALE

0.8

V

Symbol

Parameter

Notes

I Switching
I Stable

lecl

Vec Current Active

4

VIL

Input Low Voltage (± 10% Supply)

1

VIH

Input High Voltage (± 10% Supply)

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

-0.5
2.0

Vee

+ 0.5

0.45
2.4

DC CHARACTERISTICS
Symbol

Min

5

Test Condition

= VIH
f = 5 MHz. lOUT = 0 mA

V
V

10L = 2.1 mA

V

10H = -400 p.A

100

mA

Typ(2)

Max

Units

0.D1

±1.0

p.A

0.D1

±10.0

p.A

VOUT = 05. 5.5V

6

mA

CE = ALE = VIH

100

p.A

CE = VIH. ALE = VIL

15

mA

CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA

CMOS Inputs - 40'C ~ T A ~ + 12S'C

Parameter

Notes

Min

III

Input Load Current

ILO

Output Leakage Current

ISB

Vee Current Standby Switching
with InputsStable

3

leel

Vee Current Active

4

VIL

Input Low Voltage (± 10% Supply)

-0.2

VIH

Input High Voltage (± 10% Supply)

0.7 Vee

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

I

I

0.8
Vee

+

0.4

,

Vee - 0.8
5

100

Test Condition
VIN = 5.5V

V
0.2

V
V

10L = 2.1 mA

V

10H = -2.5mA

mA

NOTES:
1. Minimum DC input voltage is -0.5V. During transitions. the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Typical limits are at Vee = 5V. TA = + 25'C.
3. CE is Vec ±O.2V. All other inputs can have any value within spec.
4. Maximum current value is with outputs 00 to 07 unloaded.
5. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
.
S-86

intel~

A87C257

READ OPERATION
AC CHARACTERISTICS(1)

I Vee ±10%

Versions
Symbol

-40·C:::; TA:::; +125·C

Characteristic

87C257-120V10

87C257-200V10

Min

Min

Max

Units

Max

tACC

Address to Output Delay

120

200

ns

tCE

CE to Output Delay

120

.200

ns

toE

OE to Output Delay

55

75

ns

tDF(2)

OEHigh to Output High Z

30

40

ns

tOH(2)

Output Hold from Addresses, CE or
OE Change-Whichever is First

0

0

tLL

Latch Deselect Width

50

50

ns

tAL(2)

Address to Latch Set-Up

15

15

ns

tLA

Address Hold from LATCH

30

30

ns

tLOE

ALE to Output Enable

30

30

ns

NOTES:

ns

AC CONDITIONS OF TEST

1. See AC Testing Input/Output Waveforms for timing measurements. ,
2. Guaranteed and sampled.

Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels .................... VOL to VOH
Input Timing Reference Level ................ 1.5V
Output Timing Reference Level ........ VIL and VIH

AC WAVEFORMS

(2)

+-____

VIH _ _ _ _

t LOE --~-tOE

~---""

OE
VIL

1------tAcc-------+l

OUTPUT VIH _ _ _ _
VIL

HIGH Z
~---------....!:2l_!_-{:§~~~~~!Hr-

290142-5

NOTES:

1. This parameter is only sampled and is not 100% tested.
2. OE may be delayed up to tCE-toE alter the falling edge of CE without impact on tCE.

5-87

intel"

A87C257

CAPACITANCE(1) TA = 25°C, f = 1.0 MHz
Symbol

Parameter

Max Units Conditions

CIN

Address/Control Capacitance

6

pF

VIN = OV

COUT

Output Capacitance

12

pF

VOUT = OV

NOTE:
1. Sampled. Not 100% tested.
AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT
.L~

:OH~.5

_ TEST

Ol

~~lN914

~~IN1S ::::::X~I~ OUTPUT
DEVICE
UNDER
TEST

290142-6

3.3k.ll

I-

-

AC testing inputs are driven at VOH for a Logic "I" and VOL for a
Logic "0". Timing measurements are made at VIH for a Logic "I"
and VIL for a Logic "0".

OUT
Cl
290142-7

CL = 100 pF
CL Includes Jig Capacitance

DEVICE OPERATION
Table 1 lists 87C257 operating modes. Read mode requires a single 5V power supply. All input levels are TTL
or CMOS except Ag in Intelligent Identifier mode and Vpp.
Table 1. Mode Selection
Pins

CE

OE

Ag

Ao

ALE/
Vpp

Vee

VIL

VIL

X(1)

X

X

5.0V

Dour

VIL

VIH

X

X

X

5.0V

HighZ

Standby

VIH

X

X

X

X

5.0V

HighZ

Programming

VIL

VIH

X

X

(Note 4)

(Note 4)

DIN

X

(Note 4)

(Note 4)

DOUT

Mode
Read
Output Disable

-

Outputs

Program Verify

VIH

VIL

X

Optional Program
Verify

VIL

VIL

X

X

Vee
(Note 4)

(Note 4)

DOUT

VIH

VIH

X

X

(Note 4)

(Note 4)

HighZ

VIL

X

Vee

89H

VIH

X

Vee

24H

,

Program Inhibit
Intelligent Identifier(3)
-Manufacturer

VIL

VIL

VH(2)

Intelligent Identifier(3)
-87C257

VIL

VIL

VH(2)

NOTES:
1. X can be VIL or VIH.
2. VH = 12.0V ±0.5V.
3. AI-As. Al0-12 = VIL. A13-14 = X.
4. See Table 2 for Vcc and Vpp programming voltages.

5-88

intet

A87C257

Read Mode

Two Line Output Control

The 8.7C257 has two control functions; both must be
logically active to obtain data at the outputs. Chip
Enable (CE) is the power control and the device-select. Output enable (OE) gates data to the output
pins by controlling the output buffer. When the address is stable (ALE = VIH) or latched (ALE = VIU,
the address access time (tACe) equals the delay
from CE to output (tCE). OU.!e!!ts display valid data
tOE after the falling edge of OE, assuming tACC and
tCE times are met.

EPROMs are often used in larger memory arrays.
Intel provides two contol inputs to accommodate
multiple memory connections. Two-line control provides for:
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory-array devices and the
system's READ control line. This assures that only
selected memory devices have active outputs while
deselected memory devices are in low-power standby mode.

The 87C257 reduces the hardware interface in multiplexed address-data bus systems. Figure 4 shows a
low power, small board space, minimal chip
87C257/microcontroller design. The processor's
multiplexed bus (ADo-7) is tied to the 87C257's address and data pins. No separate address latch is
needed because the 87C257 latches all address inputs when ALE is low.

SYSTEM CONSIDERATIONS

The ALE input controls the 87C257's internal address latch. As ALE transitions from VIH to VIL, the
last address present at the address pins is retained.
The OE control can then enable EPROM data onto
the bus.

Vss vee RST

EPROM power switching characteristics require
careful device decoupling. System designers are interested in three supply current (ICC) issues-standby current levels, active current levels, and transient
current peaks produced by falling and rising edges
of Chip Enable. Transient current magnitudes depend on the device outputs' capacitive and inductive
loading. Two-Line Control and proper decoupling capacitor selection will suppress transient voltage
peaks. Each device should have a 0.1 ,...F ceramic
capacitor connected between its VCC and GND. This
high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device.
Additionally, for every eight devices, a 4.7 ,...F electrolytic capacitor should be placed between Vcc and
GND at the array's power supply connection. The
bulk capacitor will overcome voltage slumps caused
by PC board trace inductances.

Vee vss

L--~CE

1----"""ALE
I - - - -...... OE

PROGRAMMING MODES

290142-8

Caution: Exceeding 14Von Vpp will permanently
damage the device.

Figure 4. 80C31 with 87C257
System Configuration

Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word

Standby Mode
The standbLmode substantially reduces VCC current. When CE = VIH, the standby mode places the
outputs in a high impedance state, independent of
the OE input.

5-89

int:et

A87C257

functions in the 25°C ± 5°C ambient temperature
range required during programming.

can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
The programming mode is entered when Vpp is
raised to its programming voltage (see Table 2).
Data is programmed by applyi~an 8-bit word to the
output pins (00-7). Pulsing CE to TIL-low while
OE = VIH will program data. TIL levels are required
for address and data inputs.

ERASURE CHARACTERISTICS (FOR'
CERDIP EPROMS)
Exposure to light of wavelength shorter than 4000
Angstroms (A) begins EPROM erasure. Sunlight and
some fluorescent lamps have wavelengths in the
3000-4000A range. Constant exposure to room-level fluorescent light can erase an EPROM in about 3
years (about 1 week for direct sunlight). Opaque labels over the window will prevent unintentional erasure under these lighting conditions.

Program Inhibit

.

The Program Inhibit mode allows parallel programming of multiple EPROMs with different data. With
Vpp at its programming voltage, a CE-Iow pulse programs the desired EPROM. CE-high inputs inhibit
programming of non-targeted devices. Except for CE
and OE, parallel EPROMs may have common inputs.

The recommended erasure procedure is exposure
to 2537A ultraviolet light. The minimum integrated
dose (intensity x exposure time) is 15 Wsec/cm 2 .
Erasure time using a 12000 p.W/cm 2 ultraviolet
lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 7258
Wsec/cm 2 (1 week @12000 p.W/cm 2 ). High intensity UV light exposure for longer periods can cause
permanent damage.

Program Verify
With Vpp and Vee at their programming voltages, a
verify (read) determines that bits' are correctly programmed. The verify is performed with CE = Yu:t
and OE = VIL. Valid data is available tOE after OE
falls low.

I

CHMOS NOISE CHARACTERISTICS
System reliability is enhanced by Intel's CHMOS
EPI-process techniques. Protection on each data
and address pin prevents latch-up; even with 100
mA currents and voltages from -1V to Vee + 1V.
Additionally, the Vpp pin is designed to resist latchup to the 14V maximum device limit.
.

Intelligent Identifier Mode
The Intelligent Identifier Mode will determine an
EPROM's manufacturer and device type. Programming equipment can automatically match a device
with its proper programming algorithm.
This mode is activated when programming equipment forces 12V ± 0.5V on the EPROM's A9 address line. With A1-Ae, A10-A12 = VIL (A13-14 are
don't care), address line Ao = VIL will present the
manufacturer's code and Ao = VIH the device code
(see Table 1). When A9 = VH, ALE need not be
toggled to latch each identifier address. This mode

5-90

/

int'eL

A87C257

290142-9

.Figure 5; Quick-Pulse Programming Algorithm

Alternate Programming

Quick-Pulse Programming Algorithm

Intel's 27C256 Quick-Pulse Programming algorithms
will' also program the 87C257. By overriding a check
for the Intelligent Identifier, older or non-upgraded
PROM programmers can program the 87C257. See
Intel's 27C256 data sheets for programming waveforms of these alternate algorithms.

The Quick-Pulse Programming algorithm programs
Intel's 87C257 EPROM. Developed to substantially
reduce production programming throughput time,
this algorithm can program a 87C257 in under four
seconds. Actual programming time depends on the
PROM programmer used.

In addition to the Quick-Pulse Programming Algorithm the 87C257 has also been characterized for
the 'Quick-Board Programming Algorithm. The
Quick-Board Programming Algorithm was developed
for specific automotive applications using Intel's 1.0
micron EPROM products. Contact the factory or an
automotive sale representative for any· info~mation
regarding the Quick-Board Programming Algorithm.

The Quick-Pulse Programming algorithm uses a 100
microsecond initial-pulse followed by a byte verification to determine when the addressed byte is correctly programmed.' The algorithm terminates if 25
100""s pulses fail to program a byte. Figure 5 shows
the Quick-Pulse Programming algorithm flowchart.
The entire program-pulse/byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
When programming is complete, all bytes should be
compared to the original data with Vee = 5.0V.
5-91

intel .

A87C257

DC PROGRAMMING CHARACTERISTICS TA

= 25°C ±5°C

Table 2

Symbol

Limits

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

lee2(3)

Vee Supply Current

IpP2(3)

Vpp Supply Current (Program)

VID
Vpp(1)

Ag Intelligent Identifier Voltage

Vec!1)

Test Conditions

Min

Max

Unit

1.0

p,A

-0.2

0.8

V

2.0

Vee

+ 0.5

0.4

= VIL or VIH

V
V
V

Vee - 0.8

VIN

' 30

rnA

50

rnA

11.5

12.5

V

Programming Voltage

12.5

13.0

V

Supply Voltage During Programming

6.0

6.5

V

= 2.1 rnA
IOH = -400p,A
IOL

CE

= VIL

AC PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C; see Table 2 for Vee and Vpp voltages.

Symbol

Limits

Parameter
Min

Typ

Conditions

Max

Unit

tAS

Address Setup Time

2

p,s

tOES

OE Setup Time

2

p,s

tDS

Data Setup Time

tAH

Address Hold Time

2

p,s

'0

p,s
p,s

tDH

Data Hold Time

2

tDFP(2)

OE High to
Output Float Delay

0

tVPS(1)

Vpp Setup Time

2

tves(1)

Vee Setup Time

2

tpw

CEProgram Pulse Width

95

tOE

130

ns
p,s

'.

p,s

Data Valid from OE

100

105

p,s

150

ns

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. This parameter. is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
3. The maximum current value is with outputs 00 to 07 unloaded.

5-92

I' intelligent
identifier II. intelligent. identifier II'
Manufacturer
DeVIC.

12.0V - -- - - V
Address

-,,_----..;.-4-----_
=
ADDRESS

Ao =V1L

IH

VALID

Ao V1H
~-8' ~O-12

=V1L

Blank ~h.Ck

Illegal Bit Check

III

Pr

og

ram

_"

Prog~am
Verify

III

R.~d

Verify

•

I

C)

:a
ADDRESS VALID

ADDRESS STABLE

.. __ .. ___ ... _._

~L---~----~~----~~~~~~..;.~,------------J~--------~~~~~~+_------~~~~~~~-'
, V1H

Data

c[
3

~
~

~.

z
C)
~
~

V1L

<
m

1~75V-----------­

ALE/Vpp V1H -

"0:a

_.

::::s

--..r-----+-------~--.),

."

0

:a
~
en

6~::---;--------1--------7--~

:J>

V1H

U1

cO

(0)

....
n
01)

..

CE

I\)
(II

....

V1L
VIH

\..

DE
V1L

290142-10

NOTES:
1. The input timing reference level is VIL = 0.8V and VIH = 2V.
2. toE and toFP are device characteristics but must be accommodated by the programmer.
3. To prevent device damage during programming, a 0.1 J-LF capacitor is required between Vpp and ground to suppress spurious voltage transients.
4. During programming, the address latch function is bypassed whenever Vpp = 12.75V or A9 = VH. When Vpp and A9 are at TIL levels, the address latch function is
enabled, and the device functions in read mode.
5. Vpp can be 12.75V during Blank Check and Final Verify; if so, CE must be VIH.

A87C257

nDnI:D''''~

' ... I:",rua
A .... "' ...
vn .......
I lUI,.

" ' • • .,. ......... '-iI .....

L

III
A

L~

0

B

171 C 121 S 171-ll 1210 IV 11 10 1

.

t

.

:I:

Acce•• Speed (n.)
120 n.

Package
0= Cerdip
N = PLCC
~

~ Voltage
Tolerance (%)
Vee =S.OV
10%

Automotive Temperature: -40°C to + 12SoC

Valid Combinations:
AD87C257 ·120V1 0 AN87C257 ·120V1 0
AD87C257 ·200V1 0 AN87C257 ·200V1 0

REVISION HISTORY
Number

Description

004

Added the 120 ns speed bin

290142-12
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:05 15:33:08-08:00
Modify Date                     : 2013:08:06 18:29:48-07:00
Metadata Date                   : 2013:08:06 18:29:48-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:adb7b7f6-a19d-1840-a4ce-5c226088c9a3
Instance ID                     : uuid:8475b92a-7f8f-e444-8547-d59aa8bb5def
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 1218
EXIF Metadata provided by EXIF.tools

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