1993_Linear_ASIC_Databook 1993 Linear ASIC Databook

User Manual: 1993_Linear_ASIC_Databook

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4CXXJ60

LINEAR APPLICATION
SPECIFIC IC's
DATABOOK
1993 Edition

Audio Circuits

•

Radio Circuits

•

Video Circuits

•

Display Drivers

•

Clock Drivers

•

Frequency Synthesis

•

Special Automotive

•

Special Functions

•

Surface Mount
Appendices/Physical Dimensions

&II
l1li

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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR COR
PORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected t~ result in a significant injury to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be reason
ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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without notice, to change said circuHry or specifications.

·1

~National

~ Semiconductor

Product Status Definitions
Definition of Terms
Data Sheet Identification

Product Status

Definition

Formative or
In Design

This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.

First
Production

This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
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is printed for reference information only.

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improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

iii

Table of Contents
Alphanumeric Index .......................................................... .
Additional Available Linear Devices ............................................ .
Cross Reference by Part Number .............................................. .
Industry Package Cross Reference Guide ....................................... .

viii
xii
xxvi
xxxviii

Section 1 Audio Circuits
Audio Circuits Definition of Terms .............................................. .
Audio Circuits Selection Guide ................................................ .
LM380 Audio Power Amplifier ................................................. .
LM,;383 7 Watt Audio Power Amplifier ........................................... .
LM3~4 5 Watt Audio Power Amplifier ........................................... .
LM386 Low Voltage Audio Power Amplifier ...................................... .
LM388 1.5-Watt Audio Power Amplifier ......................•........•..........
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array .............. .
LM390 1 Watt Battery Operated Audio Power Amplifier ........................... .
LM391 Audio Power Driver .................................................... .
LMM1 Low Voltage Audio Power Amplifier ...................................... .
LM832 Dynamic Noise Reduction System DNR .................................. .
,... LM833 Dual Audio Operational Amplifier ........................................ .
- LM837 Low Noise Quad Operational Amplifier ................................... .
-LM1 035/LM1 036 Dual DC Operated TonelVolume/Balance Circuits ............... .
...... LM1037 Dual Four-Channel Analog Switch ...................................... .
_ LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement
Facility ................................................................... .
- LM1131A Dual Dolby B-Type Noise Reduction Processor ......................... .
..... LM1151 Dolby B-Type Noise Reduction System ................................. .
LM1875 20 Watt Power Audio Amplifier ......................................... .
LM1877 Dual Power Audio Amplifier ........................................... .
- LM1894 Dynamic Noise Reduction System DNR ................................. .
LM1896/LM2896 Dual Power Audio Amplifiers .................................. .
LM2877 Dual 4 Watt Power Audio Amplifier ..................................... .
LM2878 Dual 5 Watt Power Audio Amplifier ..................................... .
LM28V9 Dual 8 Watt Audio Amplifier ........................................... .
LM3875 High Performance 40 Watt Audio Power Amplifier ........................ .
LM3876 High Performance 40 Watt Audio Power Amplifier ........................ .
LMC835 Digital Controlled Graphic Equalizer .................................... .
LMC1982 Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable
Ste~eo Inputs ............................................................. .
LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable
Stere61nputs .................................•............................
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel
Input~Selector ............................................................. .

1-3
1-4
1-7
1-11
1-15
1-20
1-25
1-31
1-39
1-44
1-55
1-67
1-75
1-84
1-90
1-100
1-106
1-116
1-121
1-122
1-128
1-133
1-141
1-149
1-156
1-163
1-170
1-171
1-172
1-187
1-198
1-209

Section 2 Radio Circuits
Radio Circuits Definition of Terms. . . . .. .. . . . . . . . . . . . . . . . . . . .. .. . . . . . .. . . .. .. . . . .
Radio Circuits Selection Guide ...............................................•.
LM1211 Broadband Demodulator System .......................................
LM1596/LM1496 Balanced Modulator-Demodulators....... ......................
lM1865 Advanced FM IF System. .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. .. . . . .. . .
LM1868 AM/FM Radio System. . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . .
.. LM3089 FM Receiver IF System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'" LM3189 FM IF System ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
..,....LM3361 A Low Voltage/Power Narrow Band FM IF System. . . . . . . . . . . . . . . . . . . . . . . . .

iv

2-3
2-4
2-6
2-16
2-21
2-35
2-43
2-49
2-56

Table of Contents (Continued)
-.

Section 3 Video Circuits
Video Definition of Terms. . . . . . . . . . . . . . . . . . .. . ... .. . . . . . . . . ... . .. . .. . .. .. .. . .. .
Video Circuits Selection Guide .................................................
LH4266 SPDT RF Switch......................................................
LM1044 Analog Video Switch... .. ............... ................. .............
LM1201 Video Amplifier System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1202 230 MHz Video Amplifier System .......................................
LM1203 RGB Video Amplifier System...........................................
LM1203A 150 MHz RGB Video Amplifier System .................................
LM1203B 100 MHz RGB Video Amplifier System...... ........ ...................
LM1204 150 MHz RGB Video Amplifier System .... , ...................... '" .. .. .
LM1391 Phase-Locked Loop...................................................
LM1823 Video IF Amplifier/PLL Detector System .... , ............................
LM 1881 Video Sync Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54ACT174ACT715. LM1882 Programmable Video Sync Generators................
LM2416/LM2416C Triple 50 MHz CRT Drivers..... ........... ...................
LM2418 Triple 30 MHz CRT Driver... ...........................................
LM2419 Triple 65 MHz CRT Driver..............................................
Section 4 Display Drivers
Display Drivers-Introduction.................... ..............................
Display Drivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .
DS8187 Vacuum Fluorescent Display Driver...... . ..............................
DS75491 MOS-to-LED Quad Segment Driver..... ........... ....................
DS75492 MOS-to-LED Hex DigitDriver............ ........... ...................
DS55494/DS75494 Hex Digit Drivers ...........................................
MM5450/MM5451 LED Display Drivers.........................................
MM5452/MM5453 Liquid Crystal Display Drivers .................................
MM5480 LED Display Driver ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5481 LED Display Driver ......................... . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5483 Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM548416-Segment LED Display Driver........................................
MM5486 LED Display Driver ...................................................
MM58201 Multiplexed LCD Driver ..............................................
MM58241 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58242 High Voltage Display Driver............ ......... ......................
MM58248 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58341 High Voltage Display Driver..... ....... ...............................
MM58342 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58348 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3909 LED Flasher/Oscillator... .... .........................................
LM3914 Dot/Bar Display Driver ................................................
LM3915 Dot/Bar Display Driver ................................................
LM3916 Dot/Bar Display Driver................................................
Section 5 Clock Drivers
Clock Drivers-Selection Guide ................................................
* MH0007/MH0007C DC Coupled MOS Clock Drivers
DS0025C Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS0026/DS0056 5 MHz Two Phase MOS Clock Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75325 Memory Driver......................................................
DS75361 Dual TIL-to-MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75365 Quad TIL-to-MOS Driver ........................... . . . . . . . . . . . . . . . . . .

'See Appendix G

v

3-3
3-5
3-7
3-14
3-23
3-36
3-52
3-66
3-82
3-83
3-101
3-106
3-113
3-121
3-133
3-137
3-141
4-3
4-4
4-6
4-17
4-17
4-20
4-22
4-28
4-35
4-39
4-43
4-46
4-49
4-54
4-60
4-65
4-70
4-75
4-80
4-85
4-90
4-97
4-112
4-130
5-3
5-4
5-8
5-16
5-29
5-34

Table of Contents (Continued)
Section 6 Frequency Synthesis
Frequency Synthesis-Introduction . .. . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . .. .. . . . .. .
Frequency Synthesizers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8615/DS8616 130/225 MHz Low Power Dual Modulus Prescalers .......... . . . . .
DS8673/DS8674 Low Power VHF/UHF Prescalers ...............................
DS89088 AM/FM Digital Phase-Locked Loop Frequency Synthesizer...............
DS8911 /DS8913 AM/FM/TV Sound Up-Conversion Frequency Synthesizers. . . . . . . .
MM5368 CMOS Oscillator Divider Circuit ................................... . . . . .
MM5369 Series 17 Stage Oscillator/Divider..................................... .
MM5437 Digital Noise Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 7 Special Automotive
Automotive Standard Products Selection Guide ..................................
LM903 Fluid Level Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1042 Fluid Level Detector....................... ............................
LM1815 Adaptive Sense Amplifier..............................................
LM1819 Air-Core Meter Driver ........................ , .........................
LM1830 Fluid Detector..... ....... ......................... ...................
LM1921 1 Amp Industrial Switch.......... ......................................
LM1946 Over/Under Current Limit Diagnostic Circuit........... ...................
LM1949 Injector Drive Controller................... ............................
LM1950 750 rnA High Side Switch..............................................
LM1951 Solid State 1 Amp Switch..................................... .........
LM1964 Sensor Interface Amplifier....................... ... .. ............... ..
LMD18400 Quad High Side Driver........ ........... .................. .........
Section 8 Special Functions
Special Function Circuits Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0006/DH0006C Current Drivers .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0008 High Voltage, High Current Driver. ................... .. .................
DH0011A High Voltage High Current Driver................ ... ...................
DH0035/DH0035C PIN Diode Drivers...........................................
DH0034 High Speed Dual Level Translator. . . . . . . . . . . . . . .. . .. . . . .. .. . .. . .. . . . . . . .
* LH0091 True RMS to DC Converter
LH0094 Multifunction Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM122/LM322/LM3905 Precision Timers .......................................
LM194/LM394 SuperMatch Pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM195/LM295/LM395 Ultra Reliable Power Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . .
LM555/LM555C Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM556/LM556C Dual Timers ..................................................
LM565/LM565C Phase Locked Loops..........................................
LM566C Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5671LM567C Tone Decoders ...............................................
LM1851 Ground Fault Interrupter ...............................................
LM2240 Programmable Timer/Counter..........................................
LM2907/LM2917 Frequency to Voltage Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3045/LM3046/LM3086 Transistor Arrays..... ................................
LM3146 High Voltage Transistor Array...... ................. ............... ....
LMC555 CMOS Timer. . . . . . . . . .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . .
LMC567 Low Power Tone Decoder .. . . . . . . . . . . . . . . . . . . .. . . .. .. .. . . . .. . .. . . . . . . .
LMC568 Low Power Phase-Locked Loop. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .
LP395 Ultra Reliable Power Transistor ..........................................

·s.. Appendix G
vi

6-3
6-5
6-6
6-10
6-13
6-21
6-30
6-33
6-36
7-3
7-4
7-10
7-17
7-21
7-29
7-35
7-40
7-51
7-59
7-64
7-72
7-76
8-3
8-6
8-10
8-14
8-17
8-20
8-24
8-33
8-45
8-53
8-64
8-72
8-76
8-84
8-88
8-94
8-101
8-110
8-124
8-129
8-134
8-137
8-141
8-145

Table of Contents (Continued)
Section 9 Surface Mount
Surface Mount .•....................................... . . . . . . . . . . . . . . . . . . . . . .
Section 10 Appendices/Physical Dimensions
Appendix A General Product Marking and Code Explanation .......................
Appendix B Device/Application Literature Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C Summary of Commercial Reliability Programs. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix D Military Aerospace Programs from National Semiconductor. . . . . . . . . . . . . .
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . .
Appendix F How to Get the Right Information from a Datasheet . . . . . . . . . . . . . . . . . . . . .
Appendix G Obsolete Product Replacement Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

·See Appendix G

vii

9-3
10-3
10-4
10-11
10-13
10-22
10-27
10-31
10-33

Alpha-Numeric Index
54ACT715 Programmable Video Sync Generator ............................................ 3-121
74ACT715 Programmable Video Sync Generator ..•......................................... 3-121
DH0006 Current Driver ................................................................••, ., .". 8-6
DH0006C Current Driver ..............•..................................................... 8-6
DH0008 High Voltage, High Current Driver .. , ......• , .•...................................... 8-10
DH0011 A High Voltage High CurrentDriver ...••............................................. 8-14
DH0034 High Speed Dual Level Translator ................................................... 8-20
DH0035 PIN Diode Driver ...•............................................................. '. 8-17
DH0035C PIN Diode Driver .............., .••..........••...... '............•...•.......•.... 8-17
DS0025C Two Phase MOS Clock Driver ...•.•...........•.................................... 5-4
DS0026 5 MHz Two Phase MOS Clock Driver ..................................... , ......... ; . 5-8
DS0056 5 MHz Two Phase MOS Clock Driver .........•....................................... 5-8
DS8187 Vacuum Fluorescent Display Driver .............•..................................... 4-6
DS8615 130 MHz Low Power Dual Modulus Prescaler .......................................... 6-6
DS8616225 MHz Low Power Dual Modulus Prescaler .......................................... 6-6
DS8673 Low PowerVHF/UHF Prescaler ...••............................................... 6-10
DS8674 Low PowerVHF/UHF Prescaler ..........•.•....................................... 6-10
DS89088 AM/FM Digital Phase-Locked Loop Frequency Synthesizer ........................... 6-13
DS8911 AM/FM/TV Sound Up-Conversion Frequency Synthesizer ............................. 6-21
DS8913 AM/FM/TV Sound Up-Conversion Frequency Synthesizer ............................. 6-21
DS55494 Hex Digit Driver .................................................................. 4-20
DS75325 Memory Driver ........................•...•..................................... 5-16
DS75361 Dual TIL-to-MOS Driver ...................•...................................... 5-29
DS75365 Quad TIL-to-MOS Driver ......................................................... 5-34
DS75491 MOS-to-LED Quad Segment Driver ................................................ 4-17
DS75492 MOS-to-LED Hex Digit Driver ...................................................... 4-17
DS75494 Hex Digit Driver .....•............................................................ 4-20
* LH0091 True RMS to DC Converter
LH0094 Multifunction Converter .....................•...........•.......................... 8-24
LH4266 SPDT RF Switch .....•.•.•....•....•............................................... 3-7
LM122 Precision Timer .................................................................... 8-33
LM194 SuperMatch Pair ................................................................... 8-45
LM195 Ultra Reliable Power Transistor ............•......................................... 8-53
LM295 Ultra Reliable Power Transistor .....••............................................... 8-53
LM322 Precision Timer •................................................................... 8-33
LM380 Audio Power Amplifier .............................•................................. 1-7
LM383 7 Watt Audio Power Amplifier ........................................................ 1-11
LM384 5 Watt Audio Power Amplifier .....•...•............•................................. 1-15
LM386 Low Voltage Audio Power Amplifier .................•................................ 1-20
LM388 1.5-Watt Audio Power Amplifier ...................................................... 1-25
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array ........................... 1-31
LM390 1 Watt 8attery Operated Audio Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
LM391 Audio Power Driver ..............•..............•................................... 1-44
LM394 SuperMatch Pair .....••............•........•...................................... 8-45
LM395 Ultra Reliable Power Transistor ........•.•..............•............................ 8-53
LM555 Timer ....................••••............•....................................... 8-64
LM555C Timer ...........•...•........................................................... 8-64
LM556 Dual Timer ...•.•.............••.............•...•................................. 8-72
LM556C Dual Timer .....••.••............•.•............................................. 8-72
LM565 Phase Locked Loop ...•..............................•............................. 8-76
LM565C Phase Locked Loop ........................•..................................... 8-76

viii

Alpha-Numeric

Index(continUed)

LM566C Voltage Controlled Oscillator ..........................................•. : .....•.... 8-84
LM567 Tone Decoder ............................................................•........ 8-88'
LM567C Tone Decoder ...............................•.........................•......... 8-88
LM831 Low Voltage Audio Power Amplifier ................•.............................•... 1-55
LM832 Dynamic Noise Reduction System DNR ............................................... 1-67
LM833 Dual Audio Operational Amplifier ..................................................... 1-75
LM837 Low Noise Quad Operational Amplifier ................................................ 1-84
LM903 Fluid Level Detector ................................................................. 7-4
LM1035 Dual DC Operated TonelVolume/Balance Circuit ..................................... 1-90
LM1036 Dual DC Operated TonelVolume/Balance Circuit ..•...........•.................... " 1-90
LM1037 Dual Four-Channel Analog Switch ................................................. 1-100
LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement
Facility ............................................................................... 1'-106
LM1042 Fluid Level Detector ...................................••...•..•.......•........... 7-10
LM1044 Analog Video Switch .............................................................. 3-14
LM1131A Dual Dolby B-Type Noise Reduction Processor ..................................... 1-116
lM1151 Dolby B-Type Noise Reduction System ............................................. 1-121
LM1201 Video Amplifier System ............•..............................••............... 3-23
LM1202 230 MHz Video Amplifier System ................................................... 3-36
LM1203 RGB Video Amplifier System ............................................•.......... 3-52
LM1203A 150 MHz RGB Video Amplifier System ............................................. 3-66
LM1203B 100 MHz RGB Video Amplifier System ............................................. 3-82
LM1204 150 MHz RGB Video Amplifier System ..........•.................................... 3-83
LM1211 Broadband Demodulator System ..................................................... 2-6
LM1391 Phase-Locked Loop ............................................................. 3-101
LM1496 Balanced Modulator-Demodulator .................................................. 2-16
LM1596 Balanced Modulator-Demodulator .................................................. 2-16
LM1815 Adaptive Sense Amplifier .......................................................... 7-17
LM1819 Air-Core Meter Driver ............................................•...............•. 7-21
LM1823 Video IF Amplifier/PLL Detector System ............................................ 3-106
LM1830 Fluid Detector .............................................•...................... 7-29
LM1851 Ground Fault Interrupter ........................................................... 8-94
LM1865 Advanced FM IF System ....................................•...................... 2-21
LM1868 AM/FM Radio System ...................•..........•. ; .........•.................. 2-35
LM1875 20 Watt Power Audio Amplifier .................................................... 1-122
LM1877 Dual Power Audio Amplifier ....................................................... 1-128
LM 1881 Video Sync Separator ............................................................. 3-113
LM1882 Programmable Video Sync Generator .............................................. 3-121
LM1894 Dynamic Noise Reduction System DNR ............................................ 1-133
LM 1896 Dual Power Audio Amplifier .....•..........................•.........•............ 1-141
LM19211 Amp Industrial Switch ............................................................ 7-35
LM1946 Over/Under Current Limit Diagnostic Circuit .......................................... 7-40
LM1949 Injector Drive Controller ........................................................... 7-51
LM1950 750 mA High Side Switch ......................•...............•................... 7-59
LM1951 Solid State 1 Amp Switch .......................................................... 7-64
LM1964 Sensor Interface Amplifier ......................................................... 7-72
LM2240 Programmable Timer/Counter ..................................................... 8-101
LM2416 Triple 50 MHz CRT Driver ......................................................... 3-133
LM2416C Triple 50 MHz CRT Driver .....................................•................. 3-133
LM2418 Triple 30 MHz CRT Driver .................•............•...•.•.................•.. 3-137
LM2419 Triple 65 MHz CRT Driver ......................................................... 3-141
'See Appendix G

ix

Alpha-Numeric

Index(ContinUed)

LM2877 Dual 4 Watt Power Audio Amplifier ...........................•.....••....•......... 1-149
LM2878 Dual 5 Watt Power Audio Amplifier .......•......•...•.•••..••.•..•...•.••.••••.•.•. 1-156
LM2879 Dual 8 Watt Audio Amplifier .......................•...............•..•.........•.. 1-163
LM2896 Dual Power Audio Amplifier .............•.........................•...•.......••.. 1-141
LM2907 Frequency to Voltage Converter ......•........•..•..•••••••.•.•.••..•...•...•••... 8-110
LM2917 Frequency to Voltage Converter .................................•........•..•..•.. 8-110
LM3045 Transistor Array ..............•......•.....•.•...•..••.....•..•..••••.....•..•.•. 8-124
LM3046 Transistor Array •....................................••..••.•..•.••.•••.•......•. 8-124
LM3086 Transistor Array ...........................................••...............•.... 8-124
LM3089 FM Receiver IF System ...........................•.........•..•...•..•.•..•....... 2-43
LM3146 High Voltage Transistor Array ........•......•...•...•.•.•.••......••.•.......•...• 8-129
LM3189 FM IF System ......................................•............•..•............... 2-49
LM3361 A Low Voltage/Power Narrow Band FM IF System ..............•...•................. 2-56
LM3875 High Performance 40 Watt Audio Power Amplifier ......•.•.....•••..•.•..•..••••..... 1-170
LM3876 High Performance 40 Watt Audio Power Amplifier .................•...•........••.•.. 1-171
LM3905 Precision Timer ...............•...................•.........•..•.....••...•..•.... 8-33
LM3909 LED Flasher/Oscillator .............................•.•..•...•..•...•.•..•......•.. 4-90;
LM3914 Dot/Bar Display Driver .........................................•.•...............• 4-97
LM3915 Dot/Bar Display Driver ..........•..........•....•....•..•.•.....•.....••..•.••... 4-112
LM3916 Dot/Bar Display Driver ......................•..•........•.........•........••.••. 4-130
LMC555 CMOS Timer .........•...........................•............•........•........ 8-134
LMC567 Low Power Tone Decoder ...............•...........••.......•...•..•..•..••.•... 8-137
LMC568 Low Power Phase-Locked Loop .................•.•...••...........•......•••..••. 8-141
LMC835 Digital Controlled Graphic .Equalizer .....•.•............................•........... 1-172
LMC1982 Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo
Inputs ......................•.•....•.....................•..... ! • • • • • • • • • • • • • • • • • • • • • 1-187
LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo
Inputs ..................................................•.....•..•..••••..••.•••••..• 1-198
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel
Input-Selector ...............................................•..•...•.•.•...•..•...... 1-209
LMD18400 Quad High Side Driver .................••.....•...•.•..•...........•............ 7-76
LP395 Ultra Reliable Power Transistor ...........•.............•...•........•.....••.•..••. 8-145
* MH0007 DC Coupled MOS Clock Driver
* MH0007C DC Coupled MOS Clock Driver
MM5368 CMOS Oscillator Divider Circuit ..........................•..•.....•......•......... 6-30
MM5369 Series 17 Stage Oscillator/Divider ......................•.••..•••.••................ 6-33
MM5437 Digital Noise Source .........................•...•.....•.....••.••.•...•.•..•..... 6-36
MM5450 LED Display Driver ................•...........•......•.•..•...•..•.....•••...•..• 4-22
MM5451 LED Display Driver ...........................•..............•.....••...•.•..•.... 4-22
MM5452 Liquid Crystal Display Driver .....................•...•.......••••.•.••.••.••.•.•..• 4-28
MM5453 Liquid Crystal Display Driver ...........•........•........•..•...•••••••• , •.•...•..• 4-28
MM5480 LED Display Driver ........•.............•..••............••.•••..•......•.••.•..• 4-35
MM5481 LED Display Driver ....•...•..............•.....................•..••.....•.•.•... 4-39
MM5483 Liquid Crystal Display Driver .........•.....•.•..........•....••••••.••.•..•..••...• 4-43
MM5484 16-Segment LED Display Driver ...........•...•..•.•.....•..•..•..•.....•••....•... 4-46
MM5486 LED Display Driver ....................................•..•....•...........•.••... 4-49
MM58201 Multiplexed LCD Driver ......................................•.••••..••.•.••...•. 4-54
MM58241 High Voltage Display Driver ...............•.....................•..••.••.••••••.•• 4-60
MM58242 High Voltage Display Driver .........•...........•..•..•..•.•••••.••••••.••••..••.• 4-65
MM58248 High Voltage Display Driver ...................................•.•........••....... 4-70
MM58341 High Voltage Display Driver ...............•...•.....•..•..•..•..•.•••..•.•••••..•. 4-75
"See Appendix G

x

Alpha-Numeric Index (Continued)
MM58342 High Voltage Display Driver .................................................... , .. 4-80
MM58348 High Voltage Display Driver ....................................................... 4-85

"See Appendix G

xi

Additional Available Linear Devices
ADC0800 8·Bit A/D Converter ........................................ Section 2
ADC0801 8·Bit,...P Compatible A/D Converter .......................... Section 2
ADC0802 8·Bit ,...p Compatible AID Converter ....•..................... Section 2
ADC0803 8·Bit ,...p Compatible AID Converter .......................... Section 2
ADC0804 8·Bit ,...p Compatible AID Converter .......................... Section 2
ADC0805 8·Bit ,...p Compatible AID Converter •......................... Section 2
ADC0808 8·Bit ,...p Compatible AID Converter with 8·Channel Multiplexer .. Section 2
ADC0809 8·Bit ,...p Compatible AID Converter with 8·Channel Multiplexer .. Section 2
ADC0811 8·Bit Serial 110 AID Converter with 11·Channel Multiplexer ...... Section 2
ADC0816 8·Bit ,...p Compatible AID Converter with 16·Channel
Multiplexer ..........•..•.........................•............... Section 2
ADC0817 8·Bit ,...p Compatible AID Converter with 16·Channel
Multiplexer ...•.....•.•...•....................................... Section 2
ADC0819 8·Bit Serial 110 AID Converter with 19·Channel Multiplexer ...... Section 2
ADC0820 8·Bit High Speed ,...p Compatible AID Converter with Track/Hold
Function ......................................................... Section 2
ADC0831 8·Bit Serial 110 A/D Converter with Multiplexer Options ......... Section 2
ADC0832 8·Bit Serial 110 AID Converter with Multiplexer Options ......... Section 2
ADC0833 8·Bit Serial 110 AID Converter with 4·Channel Multiplexer ....... Section 2
ADC0834 8·Bit Serial 110 AID Converter with Multiplexer Options ......... Section 2
ADC0838 8·Bit Serial 110 A/D Converter with Multiplexer Options ......... Section 2
ADC0841 8·Bit,...P Compatible AID Converter .......................... Section 2
ADC0844 8·Bit ,...p Compatible AID Converter with Multiplexer Options ..... Section 2
ADC0848 8·Bit ,...p Compatible AID Converter with Multiplexer Options ..... Section 2
ADC0851 8·Bit Analog Data Acquisition and Monitoring System ........... Section 1
ADC0852 Multiplexed Comparator with 8·Bit Reference Divider ........... Section 2
ADC0854 Multiplexed Comparator with 8·Bit Reference Divider ........... Section 2
ADC0858 8·Bit Analog Data Acquisition and Monitoring System ........... Section 1
ADC0881 8-Bit 20 MSPS Flash AID Converter ...........•.............. Section 2
ADC0882 8·Bit 20 MSPS Flash AID Converter .......................... Section 2
ADC08031 8·Bit High·Speed Serial 110 AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function ....•.....•...... Section 2
ADC08032 8·Bit High·Speed Serial I/O AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function ...............•. Section 2
ADC08034 8·Bit High·Speed Serial 110 AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function ................. Section 2
ADC08038 8·Bit High·Speed Serial 110 AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function ................. Section 2
ADC08061 500 ns AID Converter with S/H Function and Input Multiplexer .. Section 2
ADC08062 500 ns AID Converter with S/H Function and Input Multiplexer .. Section 2
ADC08064 500 ns AID Converter with S/H Function and Input Multiplexer .. Section 2
ADC08068 500 ns AID Converter with S/H Function and Input Multiplexer .. Section 2
ADC08131 8·Bit High·Speed Serial 110 AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function ................. Section 2
ADC08134 8·Bit High·Speed Serial 110 AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function ................. Section 2
ADC08138 a·Bit High·Speed Serial 110 AID Converter with Multiplexer
Options, Voltage Reference, and Track/Hold Function: ................ Section 2
ADC08161 500 ns AID Converter with S/H Function, 2.5V Bandgap
Reference, and Input Multiplexer .••...••............................ Section 2

xii

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Data Acquisition
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Data Acquisition
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Data Acquisition
Data Acquisition
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Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition:
I

Data Acquisition I
Data Acquisition',
Data Acquisition
Data Acquisition

i

Additional Available Linear Devices (Continued)
ADC08164 500 ns AID Converter with S/H Function, 2.5V Bandgap
Reference, and Input Multiplexer .................................... Section 2
ADC08168 500 ns AID Converter with S/H Function, 2.5V Bandgap
Reference, and Input Multiplexer .................................... Section 2
ADC08231 8-Bit 2 ,..,s Serial 1/0 AID Converter with MUX, Reference, and
Track/Hold ....................................................... Section 2
ADC08234 8-Bit 2 ,..,s Serial I/O AID Converter with MUX, Reference, and
Track/Hold ....................................................... Section 2
ADC08238 8-Bit 2 ,..,s Serial I/O AID Converter with MUX, Reference, and
Track/Hold ....................................................... Section 2
ADC1001 1O-Bit ,..,p Compatible AID Converter ......................... Section 2
ADC1005 1O-Bit ,..,p Compatible AID Converter ......................... Section 2
ADC102110-Bit,..,P Compatible AID Converter ......................... Section 2
, ADC1025 1O-Bit ,..,p Compatible AID Converter ......................... Section 2
., ADC1 031 1O-Bit Serial 110 AID Converter with Analog Multiplexer and
, Track/Hold Function .............................................. Section 2
: ADC1 034 1O-Bit Serial 110 A/D Converter with Analog Multiplexer and
Track/Hold Function .............................................. Section 2
ADC1038 1O-Bit Serial I/O A/D Converter with Analog Multiplexer and
Track/Hold Function .............................................. Section 2
ADC1061 10-Bit High-Speed ,..,P-Compatible AID Converter with
Track/Hold Function .............................................. Section 2
ADC1205 12-Bit Plus Sign,..,p Compatible AID Converter ................ Section 2
ADC1210 12-Bit CMOS AID Converter ................................. Section 2
ADC1211 12-Bit CMOS AID Converter ................................. Section 2
ADC1225 12-Bit Plus Sign,..,p Compatible AID Converter ................ Section 2
ADC1241 Self-Calibrating 12-Bit Plus Sign ,..,P-Compatible AID Converter
with Sample/Hold ................................................. Section 2
ADC1251 Self-Calibrating 12-Bit Plus Sign AID Converter with
Sample/Hold ..................................................... Section 2
ADC3511 3%-Digit Microprocessor Compatible AID Converter ........... Section 2
ADC3711 3%-Digit Microprocessor Compatible AID Converter ........... Section 2
ADC10061 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2
ADC10062 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2
ADC10064 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2
ADC1 0154 10-Bit Plus Sign 4 ,..,s ADC with 4- or 8-Channel MUX,
Track/Hold and Reference ......................................... Section 2
ADC1 0158 10-Bit Plus Sign 4 ,..,s ADC with 4- or 8-Channel MUX,
Track/Hold and Reference ......................................... Section 2
ADC10461 10-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2
ADC10462 1O-Bit 600 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2
I ADC10464 1O-Bit 600 ns AID Converter with Input Multiplexer and
I
Sample/Hold ..................................................... Section 2
ADC10662 1O-Bit 360 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2

xiii

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Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
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Data Acquisition
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Data Acquisition
Data Acquisition
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Data Acquisition

Additional Available Linear Devices (Continued)
ADC10664 1O-Bit 360 ns AID Converter with Input Multiplexer and
Sample/Hold ..................................................... Section 2
ADC10731 1O-Bit Plus Sign Serial I/O AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC1073210-Bit Plus Sign Serial I/O AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC10734 10-Bit Plus Sign Serial I/O AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC10738 10-Bit Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC10831 10-Bit Plus Sign Serial 110 AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC10832 10-Bit Plus Sign Serial I/O AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC1083410-Bit Plus Sign Serial I/O AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC10838 10-Bit Plus Sign Serial I/O AID Converter with MUX,
Sample/Hold and Reference ....................................... Section 2
ADC12030 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converter with
MUX and Sample/Hold ............................................ Section 2
ADC12032 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with
MUX and Sample/Hold ...................•........................ Section 2
ADC12034 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with
MUX and Sample/Hold ............................................ Section 2
ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O AID Converter with
MUX and Sample/Hold ............................................ Section 2
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID
Converter with Sample/Hold ....................................... Section 2
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit Plus Sign AID
Converter with Sample/Hold ....................................... Section 2
ADD3501 3Yz-Digit DVM with Multiplexed 7-Segment Output .............. Section 2
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output .............. Section 2
AF100 Universal Active Filter ...........•.•........................... Section 7
AF151 Dual Universal Active Filter ..................................... Section 7
AH0014 Dual DPST-TIL/DTL Compatible MOS Analog Switch ............ Section 8
AH0015 Quad SPST Dual DPST-TIL/DTL Compatible MOS Analog
Switch ..................................•........................ Section 8
AH0019 Dual DPST-TIL/DTL Compatible MOS Analog Switch ............ Section 8
AH5009 Monolithic Analog Current Switch .............................. Section 8
AH5010 Monolithic Analog Current Switch .............................. Section 8
AH5011 Monolithic Analog Current Switch .... , ......................... Section 8
AH5012 Monolithic Analog Current Switch .............................. Section 8
AH5020C Monolithic Analog Current Switch ; ........................... Section 8
AN-450 Small Outline (SO) Package Surface Mounting MethodsParameters and Their Effect on ProdUct Reliability ..................... Section 7
CD4016B Quad Bilateral Switch ....................................... Section 8
CD4051B Single 8-Channel Analog Multiplexer/Demultiplexer ............ Section 8
CD4052B Dual4-Channel Analog Multiplexer/Demultiplexer .............. Section 8
CD4053B Triple 2-Channel Analog Multiplexer/Demultiplexer ............. Section 8
CD4066B Quad Bilateral Switch ....................................... Section 8
CD4529BC Dual 4-Channel or 8-Channel Analog Data Selector .........•. Section 8

xiv

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\
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Data Acquisition
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Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition :
Data Acquisition;
Data Acquisition,

I

Additional Available Linear Devices (Continued)

i

I

DAC0800 8-Bit 01 A Converter ........................................ Section 3
DAC0801 8-Bit 01 A Converter ........................................ Section 3
DAC0802 8-Bit 01 A Converter ........................................ Section 3
DAC0806 8-Bit 01 A Converter ........................................ Section 3
DAC0807 8-Bit 01 A Converter ........................................ Section 3
DAC0808 8-Bit 01 A Converter ........................................ Section 3
DAC0830 8-Bit IJ.P Compatible Double-Buffered 01 A Converter ........... Section 3
DAC0831 8-Bit IJ.P Compatible Double-Buffered 01 A Converter ........... Section 3
DAC0832 8-Bit IJ.P Compatible Double-Buffered 01 A Converter ........... Section 3
DAC0854 Quad 8-Bit Voltage-Output Serial 01 A Converter with Readback .. Section 3
DAC0890 Dual 8-Bit IJ.P-Compatible 01 A Converter ...................... Section 3
DAC1000 IJ.P Compatible, Double-Buffered 01 A Converter ............... Section 3
DAC1001 IJ.P Compatible, Double-Buffered 01 A Converter ............... Section 3
DAC1002 IJ.P Compatible, Double-Buffered 01 A Converter ............... Section 3
DAC1006 IJ.P Compatible, Double-Buffered 01 A Converter ............... Section 3
DAC1007 IJ.P Compatible, Double-Buffered 01 A Converter ............... Section 3
DAC1008 IJ.P Compatible, Double-Buffered 01 A Converter ............... Section 3
DAC1020 1O-Bit Binary Multiplying 01 A Converter ....................... Section 3
DAC1021 1O-Bit Binary Multiplying 01 A Converter ....................... Section 3
DAC1022 10-Bit Binary Multiplying 01 A Converter ....................... Section 3
DAC1208 12-Bit IJ.P Compatible Double-Buffered 01 A Converter .......... Section 3
DAC1209 12-Bit IJ.P Compatible Double-Buffered 01 A Converter .......... Section 3
DAC1210 12-Bit IJ.P Compatible Double-Buffered 01 A Converter .......... Section 3
DAC1218 12-Bit Multiplying 01 A Converter ............................. Section 3
DAC1219 12-Bit Multiplying 01 A Converter ............................. Section 3
DAC1220 12-Bit Binary Multiplying 01 A Converter ....................... Section 3
DAC1221 12-Bit Binary Multiplying 01 A Converter ....................... Section 3
DAC1222 12-Bit Binary Multiplying 01 A Converter ....................... Section 3
DAC1230 12-Bit IJ.P Compatible Double-Buffered 01 A Converter .......... Section 3
DAC1231 12-Bit IJ.P Compatible Double-Buffered 01 A Converter .......... Section 3
DAC1232 12-Bit IJ.P Compatible Double-Buffered 01 A Converter .......... Section 3
DAC1265 Hi-Speed 12-Bit 01 A Converter with Reference ................ Section 3
DAC1266 Hi-Speed 12-Bit 01 A Converter .............................. Section 3
DM2502 Successive Approximation Register ........................... Section 2
DM2503 Successive Approximation Register ........................... Section 2
DM2504 Successive Approximation Register ........................... Section 2
DP7310 Octal Latched Peripheral Driver ............................... Section 5
DP7311 Octal Latched Peripheral Driver ............................... Section 5
DP831 0 Octal Latched Peripheral Driver ............................... Section 5
DP8311 Octal Latched Peripheral Driver ............................... Section 5
DS1631 CMOS Dual Peripheral Driver ................................. Section 5
DS1632 CMOS Dual Peripheral Driver ................................. Section 5
DS1633 CMOS Dual Peripheral Driver ................................. Section 5
DS1634 CMOS Dual Peripheral Driver ................................. Section 5
DS2001 High CurrentlVoltage Darlington Driver ......................... Section 5
DS2002 High CurrentlVoltage Darlington Driver ......................... Section 5
DS2003 High CurrentlVoltage Darlington Driver ......................... Section 5
DS2004 High CurrentlVoltage Darlington Driver ......................... Section 5
DS3631 CMOS Dual Peripheral Driver ................................. Section 5
DS3632 CMOS Dual Peripheral Driver ................................. Section 5
DS3633 CMOS Dual Peripheral Driver ................................. Section 5

Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PbwerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs

Additional Available Linear Devices (Continued)
DS3634 CMOS Dual Peripheral Driver •................................ Section 5
DS3654 Printer Solenoid Driver ....................................... Section 5
DS3658 Quad High Current Peripheral Driver ........................... Section 5
DS3668 Quad Fault Protected Peripheral Driver ......................... Section 5
DS3669 Quad High Current Peripheral Driver ........................... Section 5
. DS3680 Quad Negative Voltage Relay Driver ........................... Section 5
DS9665 High Current/Voltage Darlington Driver ......................... Section 5
DS9666 High CurrentlVoltage Darlington Driver ...........•.....•....•.. Section 5
DS9667 High CurrentlVoltage Darlington Driver .....•......•.........•.. Section 5
DS9668 High CurrentlVoltage Darlington Driver ......................... Section 5
DS55451 Series Dual Peripheral Drivers ................................ Section 5
DS55452 Series Dual Peripheral Drivers ................................ Section 5
DS55453 Series Dual Peripheral Drivers ................................ Section 5
DS55454 Series Dual Peripheral Drivers ................................ Section 5
DS75450 Series Dual Peripheral Drivers .•......•....•.................. Section 5
DS75451 Series Dual Peripheral Drivers ................................ Section 5
DS75452 Series Dual Peripheral Drivers ................................ Section 5
DS75453 Series Dual Peripheral Drivers ....................•.•.......•. Section 5
DS75454 Series Dual Peripheral Drivers ................................ Section 5
HS7067 7-Amp, Multimode, High Efficiency Switching Regulator ..•....... Section 3
LF111 Voltage Comparator •.......................................... Section 3
LF147 Wide Bandwidth Quad JFET Input Operational Amplifier ............ Section 1
LF155 Series Monolithic JFET Input Operational Amplifiers •.............. Section 1
LF156 Series Monolithic JFET Input Operational Amplifiers ...•..........• Section 1
LF157 Series Monolithic JFET Input Operational Amplifiers .....•......... Section 1
LF198 Monolithic Sample and Hold Circuit .............................. Section 6
LF211 Voltage Comparator .••..................•..........•.....•..•. Section 3
LF298 Monolithic Sample and Hold Circuit. ............................. Section 6
LF311 Voltage Comparator ........................................... Section 3
LF347 Wide Bandwidth Quad JFET Input Operational Amplifier ......•..... Section 1
LF351 Wide Bandwidth JFET Input Operational Amplifier ................. Section 1
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ............ Section 1
LF398A Monolithic Sample and Hold Circuit ..•......................... Section 6
LF411 Low Offset, Low Drift JFET Input Operational Amplifier ............. Section 1
LF412 Low Offset, Low Drift Dual JFET Operational Amplifier ............. Section 1
LF441 Low Power JFET Input Operational Amplifier ...•....••...•..•.... Section 1
LF442 Dual Low Power JFET Input Operational Amplifier .............•... Section 1
LF444 Quad Low Power JFET Input Operational Amplifier ................ Section 1
LF451 Wide-Bandwidth JFET Input Operational Amplifier .........•...•..• Section 1
LF453 Wide-Bandwidth Dual JFET Input Operational Amplifier •....•...... Section 1
LF11201 Quad SPST JFET Analog Switch .............................. Section 8
LF11202 Quad SPST JFET Analog Switch .............................. Section 8
LF113;31 Quad SPST JFET Analog Switch ...............•.............. Section 8
LF11332 Quad SPST JFET Analog Switch .......••..•..•...•..•.•..•... Section 8
LF11333 Quad SPST JFET Analog Switch .............................. Section 8
LFt3006 Digital Gain Set. ............................................ Section 6
LF13007 Digital Gain Set. ............................................ Section 6
LF13201 Quad SPST JFET Analog Switch ...............•..•..•.••..... Section 8
LF13202 Quad SPST JFET Analog Switch ....•......................... Section 8
LF13331 Quad SPST JFET Analog Switch .............................. Section 8
LF13332 Quad SPST JFET Analog Switch .•......••...••..•......•..•.. Section 8

xvi

PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
OpAmps
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition .
Data Acquisition .
Data Acquisition .
Data Acquisition
Data Acquisition
Data Acquisition:

Additional Available Linear Devices (Continued)
LF13333 Quad SPST JFET Analog Switch .............................. Section 8
LF13508 8-Channel Analog Multiplexer ................................ Section 8
LF13509 4-Channel Analog Multiplexer ................................ Section 8
LH0002 Buffer ...................................................... Section 2
LH0003 Wide Bandwidth Operational Amplifier .......................... Section 1
LH0004 High Voltage Operational Amplifier ............................. Section 1
* LH0020 High Gain Operational Amplifier ............................... Section 6
* LH0022 High Performance FET Operational Amplifier .................... Section 6
LH0023 Sample and Hold Circuit ...................................... Section 6
LH0024 High Slew Rate Operational Amplifier .......................... Section 1
LH0032 Ultra Fast FET-Input Operational Amplifier ...................... Section 1
LH0033 Fast and Ultra Fast Buffers ................................... Section 2
LH0036 Instrumentation Amplifier ..................................... Section 4
LH0041 0.2-Amp Power Operational Amplifier .......................... Section 1
LH0042 Low Cost FET Operational Amplifier ............................ Section 1
LH0043 Sample and Hold Circuit ...................................... Section 6
* LH0044 Series Precision Low Noise Operational Amplifiers ............... Section 6
* LH0052 Precision FET Operational Amplifier ............................ Section 6
LH0053 High Speed Sample and Hold Amplifier ......................... Section 6
* LH0061 0.5 Amp Wide Band Operational Amplifier ....................... Section 6
* LH0062 High Speed FET Operational Amplifier .......................... Section 6
LH0063 Fast and Ultra Fast Buffers ................................... Section 2
LH0070 Series BCD Buffered Reference ............................... Section 4
LH0071 Series Precision Buffered Reference ........................... Section 4
* LH0075 Positive Precision Programmable Regulator ..................... Section 8
* LH0076 Negative Precision Programmable Regulator .................... Section 8
* LH0082 Optical Communication Receiver/Amplifier ..................... Section 6
* LH0086 Digitally-Programmable-Gain Amplifier ................. , ........ Section 6
LH0101 Power Operational Amplifier ................................... Section 1
LH 1605 5 Amp, High Efficiency Switching Regulator ..................... Section 3
LH2003 100 MHz Video Line Driver .................................... Section 2
LH2033 100 MHz Video Line Driver .................................... Section 2
* LH2101A Dual High Performance Operational Amplifier .................. Section 6
* LH2108 Dual Super Beta Operational Amplifier .......................... Section 6
* LH211 0 Dual Voltage Follower ........................................ Section 6
LH2111 Dual Voltage Comparator ..................................... Section 3
* LH2201A Dual High Performance Operational Amplifier .................. Section 6
* LH2210 Dual Voltage Follower ........................................ Section 6
LH2211 Dual Voltage Comparator ..................................... Section 3
* LH2301A Dual High Performance Operational Amplifier .................. Section 6
* LH2308 Dual Super Beta Operational Amplifier .......................... Section 6
* LH231 0 Dual Voltage Follower ........................................ Section 6
LH2311 Dual Voltage Comparator ..................................... Section 3
LH4001 Wideband Current Buffer ..................................... Section 2
LH4002 Wideband Video Buffer ....................................... Section 2
* LH4003 Precision RF Closed Loop Buffer .............................. Section 6
• LH4006 Precision RF Closed Loop Buffer .............................. Section 6
• LH4008 Fast Buffer ................................................. Section 6
, LH4009 Fast Buffer ................................................. Section 6
LH4010 Fast FET Buffer ............................................. Section 6
LH4011 Fast Open Loop Buffer ....................................... Section 6
OSee Appendix G

xvii

Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
OpAmps
OpAmps
Data Acquisition
OpAmps
OpAmps
OpAmps
Data Acquisition
Data Acquisition
PowerlCs
Power ICs
OpAmps
OpAmps
OpAmps
Power ICs
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps

Additional Available Linear Devices (Continued)
.•
•
•
•

LH4012 Wideband Buffer ............................................ Section 6
LH4033C Fast and Ultra Fast Buffer Amplifiers .......................... Section 6
LH4063C Fast and Ultra Fast Buffer Amplifiers .......................... Section 6
LH4101 Wideband High Current Operational Amplifier ................... Section 6
LH41 04 G-MIL Fast Settling High Current Operational Amplifier ........... Section 1
• LH41 05 Precision Fast Settling High Current Operational Amplifier ......... Section 6
• LH4106 ± 5V High Speed Operational Amplifier ......................... Section 6
• LH4117 Precision RF Amplifier. ....................................... Section 6
LH4118 G-MIL Current Feedback Wide Band RF Amplifier ................ Section 1
• LH4124C High Slew Rate Operational Amplifier ......................... Section 6
• LH4141 C 0.2 Amp Power Operational Amplifier .............•........... Section 6
• LH4161 High Speed Operational Amplifier .............................. Section 6
• LH4162 Dual High Speed Operational Amplifier ......................... Section 6
* LH4200 General Purpose GaAs FET Amplifier .......................... Section 6
LH4860 Super Fast 12-Bit Track-Hold Amplifier ......................... Section 6
* LH7001 Positive/Negative Adjustable Regulator ........................ Section 8
LH7070 Series Precision BCD Buffered Reference ...................... Section 4
LH7071 Series Precision Binary Buffered Reference .....•............... Section 4
LM10 Operational Amplifier and Voltage Reference ...... " .....•.......• Section 1
LM 11 Operational Amplifier ................... : ....................... Section 1
LM 12L 150W Operational Amplifier .................................... Section 1
LM 12L 150W Operational Amplifier .................................... Section 4
LM34 Precision Fahrenheit Temperature Sensor, ................•...... Section 5
LM35 Precision Centigrade Temperature Sensor ........................ Section 5
LM78G 4-Terminal Adjustable Regulator ..... , ............. , ..........• Section 1
LM78LXX Series 3-Terminal Positive Regulators ........................ Section 1
LM78MG 4-Terminal Adjustable Voltage Regulator .. , ................... Section 1
LM78MXX Series 3-Terminal Positive Regulator .......... , .......... , ..• Section 1
LM78S40 Universal Switching Regulator Subsystem ..................... Section 3
LM79LXXAC Series 3-Terminal Negative Regulator ....................•. Section 1
LM79MXX Terminal Negative Regulators ............................... Section 1
LM79XX Series 3-Terminal Negative Regulators ...................•.... Section 1
LM101A Operational Amplifier ............. , .......................... Section 1
LM102 Voltage Follower ...... , ..... , .................•..........•.•• Section 2
LM104 Negative Regulator ........................................... Section 1
LM105 Voltage Regulator, ............ , .... , ......................... Section 1
LM106 Voltage Comparator ........................... , .............. Section 3
LM107 Operational Amplifier .......................................... Section 1
LM 108 Operational Amplifier ..... , ................... , ................ Section 1
LM109 5-Volt Regulator. ............. , ............................... Section 1
LM110 Voltage Follower ............................................. Section 2
LM111 Voltage Comparator .......................................... Section 3
LM 112 Operational Amplifier .......................................... Section 1
LM113 Reference Diode ............................................. Section 4
LM117 3-Terminal Adjustable Regulator ................................ Section 1
LM117HV 3-Terminal Adjustable Regulator ............................. Section 1
LM 118 Operational Amplifier .......................................... Section 1
LM119 High Speed Dual Comparator .................................. Section 3
LM120 Series 3-Terminal Negative Regulator ........................... Section 1
LM121 Precision Preamplifier ......................................... Section 4
LM123 3-Amp. 5-Volt Positive Regulator ............................... Section 1
·Se. Appendix G

xviii

OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
PowerlCs
Data Acquisition
Data Acquisition
OpAmps
OpAmps
OpAmps
PowerlCs
Data Acquisition
Data Acquisition
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
OpAmps
OpAmps
PowerlCs
PowerlCs
OpAmps
OpAmps
OpAmps
PowerlCs
OpAmps
OpAmps
OpAmps
Data Acquisition
PowerlCs
PowerlCs
OpAmps
OpAmps '
PowerlCs
OpAmps'
Power ICs

Additional Available Linear Devices (Continued)
LM 124 Low Power Quad Operational Amplifier .......................... Section 1
LM125 Voltage Regulator ............................................ Section 1
LM126 Voltage Regulator ............................................ Section 1
LM 129 Precision Reference .......................................... Section 4
LM131 Precision Voltage-to-Frequency Converter ....................... Section 2
LM133 3-Amp Adjustable Negative Voltage Regulator ................... Section 1
LM 134 3-Terminal Adjustable Current Source ........................... Section 4
LM135 Precision Temperature Sensor ................................. Section 5
LM136-2.5V Reference Diode ........................................ Section 4
LM136-5.0V Reference Diode ........................................ Section 4
LM137 3-Terminal Adjustable Negative Regulator ....................... Section 1
LM137HV 3-Terminal Adjustable Negative Regulator (High Voltage) ....... Section 1
LM138 5-Amp Adjustable Regulator ................................... Section 1
LM139 Low Power Low Offset Voltage Quad Comparator ................ Section 3
LM140 Series 3-Terminal Positive Regulator ............................ Section 1
LM 140L Series 3-Terminal Positive Regulator ........................... Section 1
LM143 High Voltage Operational Amplifier .............................. Section 1
LM144 High Voltage, High Slew Rate Operational Amplifier ............... Section 1
LM145 Negative 3-Amp Regulator ..................................... Section 1
LM146 Programmable Quad Operational Amplifier ....................... Section 1
LM 148 Quad 741 Operational Amplifier ................................ Section 1
LM149 Wide Band Decompensated (Av(MIN) = 5) ...................... Section 1
LM 150 3-Amp Adjustable Power Regulator ............................. Section 1
LM158 Low Power Dual Operational Amplifier ........................... Section 1
LM160 High Speed Differential Comparator ............................. Section 3
LM161 High Speed Differential Comparator ............................. Section 3
LM168 Precision Voltage Reference ................................... Section 4
LM169 Precision Voltage Reference ................................... Section 4
LM185 Adjustable Micropower Voltage Reference ....................... Section 4
LM185-1.2 Micropower Voltage Reference Diode ....................... Section 4
LM185-2.5 Micropower Voltage Reference Diode ....................... Section 4
LM193 Low Power Low Offset Voltage Dual Comparator ................. Section 3
LM 194 Supermatch Pair ............................................. Section 1
LM196 10-Amp Adjustable Voltage Regulator ........................... Section 1
LM199 Precision Reference .......................................... Section 4
LM201A Operational Amplifier ........................................ Section 1
LM204 Negative Regulator ........................................... Section 1
LM205 Voltage Regulator ............................................ Section 1
LM206 Voltage Comparator .......................................... Section 3
LM207 Operational Amplifier .......................................... Section 1
LM208 Operational Amplifier .......................................... Section 1
LM210 Voltage Fo"ower ............................................. Section 2
LM211 Voltage Comparator .......................................... Section 3
LM212 Operational Amplifier .......................................... Section 1
LM218 Operational Amplifier .......................................... Section 1
LM219 High Speed Dual Comparator .................................. Section 3
LM221 Precision Preamplifier ......................................... Section 4
LM224 Low Power Quad Operational Amplifier .......................... Section 1
LM231 Precision Voltage-to-Frequency Converter ....................... Section 2
LM234 3-Terminal Adjustable Current Source ........................... Section 4
LM235 Precision Temperature Sensor ................................. Section 5
·See Appendix G

xix

OpAmps
PowerlCs
PowerlCs
Data Acquisition
Data Acquisition
Power ICs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Power ICs
PowerlCs
Power ICs
OpAmps
PowerlCs
PowerlCs
OpAmps
OpAmps
Power ICs
OpAmps
OpAmps
OpAmps
PowerlCs
OpAmps
OpAmps
OpAmps
Data: Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
Power ICs
Data Acquisition
OpAmps
PowerlCs
Power ICs
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
Data Acquisition
Data Acquisition

Additional Available Linear Devices(continUed)
LM236-2.5V Reference Diode .........••................•............ Section 4
LM236-5.0V Reference Diode ........................................ Section 4
LM239 Low Power Low Offset Voltage Quad Comparator ................ Section 3
LM246 Programmable Quad Operational Amplifier ...............•....... Section 1
LM248 Quad 741 Operational Amplifier ................................ Section 1
LM258 Low Power Dual Operational Amplifier ........................... Section 1
LM261 High Speed Differential Comparator ............................. Section 3
LM268 Precision Voltage Reference ................................... Section 4
LM285 Adjustable Micropower Voltage Reference ....................... Section 4
LM285-1.2 Micropower Voltage Reference Diode ....................... Section 4
LM285-2.5 Micropower Voltage Reference Diode ....................... Section 4
LM293 Low Power Low Offset Voltage Dual Comparator ................. Section 3
LM299 Precision Reference .......................................... Section 4
LM301A Operational Amplifier ........................................ Section 1
LM302 Voltage Follower ............................................. Section 2
LM304 Negative Regulator ........................................... Section 1
LM305 Voltage Regulator ............................................ Section 1
LM306 Voltage Comparator .......................................... Section 3
LM307 Operational Amplifier .......................................... Section 1
LM308 Operational Amplifier .......................................... Section 1
LM309 5-Volt Regulator .........................•.................... Section 1
LM310 Voltage Follower ...................•......................... Section 2
LM311 Voltage Comparator .......................................... Section 3
LM312 Operational Amplifier .......................................... Section 1
LM313 Reference Diode ............................................. Section 4
LM317 3-Terminal Adjustable Regulator ................................ Section 1
LM317HV 3-Terminal Adjustable Regulator ............................. Section 1
LM317L 3-Terminal Adjustable Regulator .............................. Section 1
LM318 Operational Amplifier ..................•....................... Section 1
LM319 High Speed Dual Comparator .................................. Section 3
LM320 Series 3-Terminal Negative Regulator ........................... Section 1
LM320L Series 3-Terminal Negative Regulator .......................... Section 1
LM321 Precision Preamplifier ......................................... Section 4
LM323 3-Amp, 5-Volt Positive Regulator ......................•........ Section 1
LM324 Low Power Quad Operational Amplifier .......................... Section 1
LM325 Voltage Regulator ............................................ Section 1
LM326 Voltage Regulator ............................................ Section 1
LM329 Precision Reference .......................................... Section 4
LM330 3-Terminal Positive Regulator .................................. Section 2
LM331 Precision Voltage-to-Frequency Converter ....................... Section 2
LM333 3-Amp Adjustable Negative Voltage Regulator ................... Section 1
LM334 3-Terminal Adjustable CUlTent Source ........................... Section 4
LM335 Precision Temperature Sensor ................................. Section 5
LM336-2.5V Reference Diode ........................................ Section 4
LM336-5.0V Reference Diode ........................................ Section 4
LM337 3-Terminal Adjustable Negative Regulator ....................... Section 1
LM337HV 3-Terminal Adjustable Negative Regulator (High Voltage) ....... Section 1
LM337L 3-Terminal Adjustable Regulator .......•...................... Section 1
LM3385-Amp Adjustable Regulator ................................... Section 1
LM339 Low Power Low Offset Voltage Quad Comparator ...........•.... Section 3
LM340 Series 3-Terminal Positive Regulator .........•.................. Section 1
-See Appendix 0

xx

Data Acquisition
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
Data Acquisition
OpAmps
OpAmps
PowerlCs
PowerlCs
OpAmps
OpAmps
OpAmps
PowerlCs
OpAmps
OpAmps
OpAmps
Data Acquisition
PowerlCs
PowerlCs
PowerlCs
OpAmps
OpAmps
PowerlCs
PowerlCs
OpAmps
Power ICs
OpAmps
PowerlCs
PowerlCs
Data Acquisition
PowerlCs
Data Acquisition
PowerlCs
Data Acquisition '
Data Acquisition •
Data Acquisition ,
Data Acquisition •
PowerlCs'
PowerlCs,
PowerlCs:
PowerlCs.
OpAmpsr
PowerlCs

Additional Available Linear Devices(ContinUed)
LM340L Series 3-Terminal Positive Regulator ............•.............. Section 1
LM341 Series 3-Terminal Positive Regulator ............................ Section 1
LM342 Series 3-Terminal Positive Regulator ............................ Section 1
LM343 High Voltage Operational Amplifier .............................. Section 1
LM344 High Voltage, High Slew Rate Operational Amplifier ............... Section 1
LM345 Negative 3-Amp Regulator ..................................... Section 1
LM346 Programmable Quad Operational Amplifier ....................... Section 1
LM348 Quad 741 Operational Amplifier ................................ Section 1
LM349 Wide Band Decompensated (Av(MIN) = 5) ...................... Section 1
LM350 3-Amp Adjustable Power Regulator ............................. Section 1
LM358 Low Power Dual Operational Amplifier ........................... Section 1
LM359 Dual, High Speed, Programmable Current Mode (Norton) Amplifier .. Section 1
LM360 High Speed Differential Comparator ............................. Section 3
LM361 High Speed Differential Comparator ............................. Section 3
LM368 Precision Voltage Reference ................................... Section 4
LM368-2.5 Precision Voltage Reference ............................... Section 4
LM369 Precision Voltage Reference ................................... Section 4
LM376 Voltage Regulator ............................................ Section 1
LM385 Adjustable Micropower Voltage Reference ....................... Section 4
LM385-1.2 Micropower Voltage Reference Diode ....................... Section 4
LM385-2.5 Micropower Voltage Reference Diode ....................... Section 4
LM392 Low Power Operational AmplifierlVoltage Comparator .........•.. Section 1
LM393 Low Power Low Offset Voltage Dual Comparator ................. Section 3
LM394 Supermatch Pair ............................................. Section 1
LM396 10-Amp Adjustable Voltage Regulator ........................... Section 1
LM399 Precision Reference .......................................... Section 4
LM431 A Adjustable Precision Zener Shunt Regulator .................... Section 1
LM604 4-Channel MUX-Amp ......................................•.. Section 1
LM607 Precision Operational Amplifier ................................. Section 1
LM611 Operational Amplifier and Adjustable Reference .................. Section 1
LM612 Dual-Channel Comparator and Reference ....................... Section 3
LM613 Dual Operational Amplifier, Dual Comparator, and Adjustable
Reference ....................................................... Section 3
LM613 Dual Operational Amplifier, Dual Comparator, and Adjustable
Reference ....................................................... Section 1
LM614 Quad Operational Amplifier and Adjustable Reference ............. Section 1
LM615 Quad Comparator and Adjustable Reference ..................... Section 3
LM621 Brushless Motor Commutator .........•........................ Section 4
LM627 Precision Operational Amplifier ................................. Section 1
LM628 Precision Motion Controller ............................•..•.... Section 4
LM629 Precision Motion Controller .................................... Section 4
LM637 Precision Operational Amplifier ................................. Section 1
LM675 Power Operational Amplifier ............................•...... Section 1
LM709 Operational Amplifier .......................................... Section 1
LM710 Voltage Comparator .......................................... Section 3
LM715 High Speed Operational Amplifier ............................... Section 1
LM723 Voltage Regulator ..........................................•. Section 1
LM725 Operational Amplifier .................................•........ Section 1
LM741 Operational Amplifier ........................•.....•........... Section 1
LM747 Dual Operational Amplifier ..................................... Section 1
. LM748 Operational Amplifier .........................................• Section 1
'See Appendix G

xxi

Power ICs
PowerlCs
PowerlCs
OpAmps
OpAmps
Power ICs
OpAmps
OpAmps
OpAmps
Power ICs
OpAmps
OpAmps
OpAmps
OpAmps
Data Acquisition
Data Acquisition
Data Acquisition
PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
OpAmps
PowerlCs
Data Acquisition
Power ICs
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
PowerlCs
OpAmps
Power ICs
PowerlCs
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
PowerlCs
OpAmps
OpAmps
OpAmps
OpAmps

Additional Available Linear Devices(continUed)
LM759 Power Operational Amplifier ................................... Section 1
LM760 High Speed Differential Comparator ............................. Section 3
LM1201 Video Amplifier System .................•..................•.• Section 1
LM1202 230 MHz Video Amplifier System ....................•........• Section 1
LM1203 RGB Video Amplifier System .................................. Section 1
LM1203A 100 MHz RGB Video Amplifier System ........................ Section 1
LM1414 Dual Differential Voltage Comparator .......................... Section 3
LM1458 Dual Operational Amplifier .................................... Section 1
LM1524D Regulating Pulse Width Modulator ............................ Section 3
LM1558 Dual Operational Amplifier .................................... Section 1
LM1575 Simple Switcher 1A Step-Down Voltage Regulator ............... Section 3
LM1575HV Simple Switcher 1A Step-Down Voltage Regulator ............ Section 3
LM1577 Simple Switcher Step-Up Voltage Regulator .................... Section 3
LM1578A Switching Regulator ........................................ Section 3
LM1801 Battery Operated Power Comparator ........................... Section 3
LM1875 20 Watt Power Audio Amplifier ................................ Section 1
LM1877 Dual Power Audio Amplifier ................................... Section 1
LM1921 1 Amp Industrial Switch ...................................... Section 6
LM1950 750 rnA High Side Switch ..................................... Section 6
LM 1951 Solid State 1 Amp Switch ..................................... Section 6
LM2524D Regulating Pulse Width Modulator ............................ Section 3
LM2574 Simple Switcher 0.5A Step-Down Voltage Regulator ...•......... Section 3
LM2574HV Simple Switcher 0.5A Step-Down Voltage Regulator ........... Section 3
LM2575 Simple Switcher 1A Step-Down Voltage Regulator ............... Section 3
LM2575HV Simple Switcher 1A Step-Down Voltage Regulator ............ Section 3
LM2576 Simple Switcher3A Step-Down Voltage Regulator ............... Section 3
LM2576HV Simple Switcher 3A Step-Down Voltage Regulator ............ Section 3
LM2577 Simple Switcher Step-Up Voltage Regulator .................... Section 3
LM2578A Switching Regulator ........................................ Section 3
LM2877 Dual 4 Watt Power Audio Amplifier ............................. Section 1
LM2878 Dual 5 Watt Power Audio Amplifier ..................•.......... Section 1
LM2879 Dual 8 Watt Audio Amplifier ......•............................ Section 1
LM2900 Quad Amplifier .............................................. Section 1
LM2901 Low Power Low Offset Voltage Quad Comparator ............... Section 3
LM2902 Low Power Quad Operational Amplifier ......................... Section 1
LM2903 Low Power Low Offset Voltage Dual Comparator ................ Section 3
LM2904 Low Power Dual Operational Amplifier ..............•........... Section 1
LM2924 Low Power Operational AmplifierlVoltage Comparator ........... Section 1
LM2925 Low Dropout Regulator with Delayed Reset ..................... Section 2
LM2926 Low Dropout Regulator with Delayed Reset ..................... Section 2
LM2927 Low Dropout Regulator with Delayed Reset ..................... Section 2
LM2930 3-Terminal Positive Regulator ................................. Section 2
LM2931 Series Low Dropout Regulators ............................... Section 2
LM2935 Low Dropout Dual Regulator ...............•.................. SeCtion 2
LM2936 Ultra-Low Quiescent Current 5V Regulator ...................... Section 2
LM2937 500 rnA Low Dropout Regulator ............................... Section 2
LM2940/LM2940C 1A Low Dropout Regulators ......................... Section 2
LM2941 I LM2941 C 1A Low Dropout Adjustable Regulators ................ Section 2
LM2984 Microprocessor Power Supply System ......................... Section 2
LM2990 Negative Low Dropout Regulator .............................. Section 2
LM2991 Negative Low Dropout Adjustable Regulator ...•.•............... Section 2
OSee Appendix G

·xxii

OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Power ICs
OpAmps
PowerlCs
Power ICs
Power ICs
PowerlCs
OpAmps
OpAmps
OpAmps
PowerlCs
PowerlCs
PowerlCs
Power ICs
Power ICs
PowerlCs
Power ICs
Power ICs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Power ICs
Power ICs
PowerlCs
PowerlCs
Power ICs
PowerlCs
Power ICs
PowerlCs
PowerlCs
Power ICs
PowerlCs
Power ICs
PowerlCs

Additional Available Linear Devices(continUed)
LM3080 Operational Transconductance Amplifier ....................... Section 1
LM3301 Quad Amplifier .............................................. Section 1
LM3302 Low Power Low Offset Voltage Quad Comparator ............... Section 3
LM3303 Quad Operational Amplifier ................................... Section 1
LM3401 Quad Amplifier .............................................. Section 1
LM3403 Quad Operational Amplifier ................................... Section 1
LM3524D Regulating Pulse Width Modulator ............................ Section 3
LM3578A Switching Regulator ........................................ Section 3
LM3875 High Performance 40 Watt Audio Power Amplifier ................ Section 1
LM3900 Quad Amplifier .............................................. Section 1
LM3911 Temperature Controller ...................................... Section 5
LM3999 Precision Reference ......................................... Section 4
LM4040 Precision Micropower Shunt Voltage Reference ................. Section 4
LM4041 Precision Micropower Shunt Voltage Reference ................. Section 4
LM4136 Quad Operational Amplifier ................................... Section 1
LM4250 Programmable Operational Amplifier ........................... Section 1
LM4431 Micropower Shunt Voltage Reference .......................... Section 4
LM6118 Fast Settling Dual Operational Amplifier ........................ Section 1
LM6121 High Speed Buffer ........................................... Section 2
LM6125 High Speed Buffer ........................................... Section 2
LM6161 High Speed Operational Amplifier .............................. Section 1
LM6162 High Speed Operational Amplifier .............................. Section 1
LM6164 High Speed Operational Amplifier .............................. Section 1
LM6165 High Speed Operational Amplifier .............................. Section 1
LM6181 100 mA, 100 MHz Current Feedback Amplifier .................. Section 1
LM6218 Fast Settling Dual Operational Amplifier ........................ Section 1
LM6221 High Speed Buffer ........................................... Section 2
LM6225 High Speed Buffer ........................................... Section 2
LM6261 High Speed Operational Amplifier .............................. Section 1
LM6262 High Speed Operational Amplifier .............................. Section 1
LM6264 High Speed Operational Amplifier .............................. Section 1
LM6265 High Speed Operational Amplifier .............................. Section 1
LM6313 High Speed, High Power Operational Amplifier .................. Section 1
LM6321 High Speed Buffer ........................................... Section 2
LM6325 High Speed Buffer ........................................... Section 2
LM6361 High Speed Operational Amplifier. ............................. Section 1
LM6362 High Speed Operational Amplifier .............................. Section 1
LM6364 High Speed Operational Amplifier .............................. Section 1
LM6365 High Speed Operational Amplifier .............................. Section 1
LM6685 Ultra Fast Single Latched Comparator .......................... Section 3
LM6687 Ultra Fast Voltage Comparator ................................ Section 3
LM7800 Series 3-Terminal Positive Regulator ........................... Section 1
LM9140 Precision Micropower Shunt Voltage Reference ................. Section 4
LM12454 12-Bit + Sign Data Acquisition System with Self-Calibration ..... Section 1
LM12458 12-Bit + Sign Data Acquisition System with Self-Calibration ..... Section 1
LM13080 Programmable Power Operational Amplifier .................... Section 1
LM13600 Dual Operational Transconductance Amplifier with Linearizing
Diodes and Buffers ................................................ Section 1
LM18293 Four Channel Push-Pull Driver ............................... Section 4
LM18298 Dual Full-Bridge Driver ...................................... Section 4
LMC660 CMOS Quad Operational Amplifier ............................ Section 1

"see Appendix G
xxiii

OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Power ICs
Power ICs
OpAmps
OpAmps
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Power ICs
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
Power ICs
Power ICs
OpAmps

Additional Available Linear Devices (Continued)
LMG662 CMOS Dual Operational Amplifier ............................. Section 1
LMC6022 Micropower CMOS Dual Operational Amplifier ....•.•••..•...•. Section 1
LMC6024 Micropower CMOS Quad Operational Amplifier .•.......•...... Section 1
LMC6032 CMOS Dual Operational Amplifier ............................ Section 1
LMC6034 CMOS Quad Operational Amplifier ........................... Section 1
LMC6041 CMOS Single Micropower Operational Amplifier ....•......•.... Section 1
LMC6042 CMOS Dual Micropower Operational Amplifier ................. Section 1
LMC6044 CMOS Quad Micropower Operational Amplifier .......•......•. Section 1
LMC6061 Precision CMOS Single Micropower Operational Amplifier •..•... Section 1
LMC6062 Precision CMOS Dual Micropower Operational Amplifier ........ Section 1
LMC6064 Precision CMOS Quad Micropower Operational Amplifier •....... Section 1
LMC6081 Precision CMOS Single Operational Amplifier ....•.......•..... Section 1
LMC6082 Precision CMOS Dual Operational Amplifier ...........•....... Section 1
LMC6084 Precision CMOS Quad Operational Amplifier .•.•....•••........ Section 1
LMC6482 CMOS Dual Rail-to-Rail Input and Output Operational Amplifier .. Section 1
LMC6484 CMOS Quad Rail-to-Raillnput and Output Operational Amplifier .. Section 1
LMC7660 Switched Capacitor Voltage Converter ......•.........•......• Section 3
LMD18200 3A. 55VH-Bridge ...................•......•.•.......••.... Section 4
LMD18201 3A. 55VH-Bridge .......................................... Section 4
LMD18400 Quad High Side Driver ......•..................•.....••••.. Section 6
LMF40 High Performance 4th-Order Switched Capacitor Butterworth
Low-Pass Filter ................................................... Section 7
LMF60 High Performance 6th-Order Switched Capacitor Butterworth
Low-Pass Filter .............................................•..•.. Section 7
LMF90 4th-Order Elliptic Notch Filter .................................. Section 7
LMF100 High Performance Dual Switched Capacitor Filter ................ Section 7
LMF120 Mask Programmable Switched Capacitor Filter .................. Section 7
LMF380 Triple One-Third Octave Switched Capacitor Active Filter ......... Section 7
LP124 Low Power Quad Operational Amplifier ..........•..•...•.....•.• Section 1
LP265 Micropower Programmable Quad Comparator .•....•.•.....•..... Section 3
LP311 Voltage Comparator ............•........•......•.•............ Section 3
LP324 Low Power Quad Operational Amplifier .......................... Section 1
LP339 Ultra-Low Power Quad Comparator ...•...............••......•.. Section 3
LP365 Micropower Programmable Quad Comparator ...............•.... Section 3
LP2902 Low Power Quad Operational Amplifier ..........•......•....... Section 1
LP2950 5V Adjustable Micropower Voltage Regulator ......•.........•... Section 2
LP2951 Adjustable Micropower Voltage Regulator ..•.•............•..... Section 2
LP2952 Adjustable Micropower Low-Dropout Voltage Regulator ........... Section 2
LP2953 Adjustable Micropower Low-Dropout Voltage Regulator .•.•.....•• Section 2
LP2954 5V Micropower Low-Dropout Voltage Regulator ...•••.•...••..... Section 2
LPC660 Low Power CMOS Quad Operational Amplifier .................. Section 1
LPC661 Low Power CMOS Operational Amplifier ........................ Section 1
LPC662 Low Power CMOS Dual Operational Amplifier ........•.•....•.•. Section 1
MF44th Order Switched Capacitor Butterworth Lowpass Filter .•....•.•... Section 7
MF5 Universal Monolithic Switched Capacitor Filter ...................... Section 7
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ..•••....... Section 7
MF8 4th Order Switched Capacitor Bandpass Filter ...................... Section 7
MF10 Universal Monolithic Dual Switched Capacitor Filter ..•.•.....••••.. Section 7
MM54C905 12-Bit Successive Approximation Register ....•...•.......... Section 2
MM54HC4016 Quad Analog Switch ..................•.....••••..••••• Section 8
MM54HC4051 8-Channel Analog Multiplexer •.......••.....•••..••..•.. Section 8
osee Appendix G

xxiv

OpAmps
OpAmps
OpAmps
.0pAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
Power ICs
PowerlCs
·PowerlCs
PowerlCs
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
OpAmps
PowerlCs
PowerlCs
PowerlCs
PowerlCs
PowerlCs
OpAmps
OpAmps
OpAmps
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition

!

Additional Available Linear Devices (Continued)
MM54HC4052 Dual 4-Channel Analog Multiplexer ....................... Section a
MM54HC4053 Triple 2-Channel Analog Multiplexer ...................... Section a
MM54HC4066 Quad Analog Switch ................................... Section a
MM54HC4316 Quad Analog Switch with Level Translator ................ Section a
MM74C905 12-Bit Successive Approximation Register ................... Section 2
MM7 4HC4016 Quad Analog Switch ....•.............................. Section a
MM74HC4051 a-Channel Analog Multiplexer ........................... Section a
MM74HC4052 Dual4-Channel Analog Multiplexer ....................... Section 8
MM74HC4053 Triple 2-Channel Analog Multiplexer ...................... Section 8
MM74HC4066 Quad Analog Switch ................................... Section 8
MM74HC4316 Quad Analog Switch with Level Translator ................ Section 8
OP07 Low Offset, Low Drift Operational Amplifier ........................ Section 1
TL081 Wide Bandwidth JFET Input Operational Amplifier ................. Section 1
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier ............ Section 1

·s.. Appendix G
xxv

Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
OpAmps
OpAmps
OpAmps

..
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Cross Reference by Part Number

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A complete interchangeability list of Linear IC's offered by most Integrated Circuit Manufacturers is listed in this section, and
references the nearest National Semiconductor Corporation direct replacement or recommended replacement with either an
improved or functional replacement.
The following companies are included in this cross reference:
Analog Devices
Burr Brown
Cherry
Elantec
Fairchild (NSC)

Part Number

Harris (GE/RCAllntersil)
Hitachi
Linear Technology Corp.
Maxim
Motorola

NSC
Part Number

Part Number

Philips
Precision Monolithics Inc.
Raytheon
Samsung
SGS Thompson

NSC
Part Number

Part Number

Signetics
Siliconix
Texas Instruments
Toshiba
Unitrode
NSC
Part Number

ANALOG DEVICES

ADOO42
AD101A
AD201A
AD301A
AD5035

LHOO42
LM101A
LM201A
LM301A
LHOO42

I
S

AD590
AD590
AD590
AD6ll
AD624

LM135
LM34
LM35
LF441
LM363

S
S
S
I
S

AD7542
AD7545
AD7545
AD7545
AD7548

DAC12l0
DAC1208
DAC1209
DAC1?10
DAC1230

S
S
S
S
S

AD506
AD509
AD521
AD521
AD522

LHOO22
LHOOO3
LHOO36
LM363
LHOO38

S
S
S
S
S

AD650
AD651
AD654
AD673
AD707

LM331
LM331
LM331
ADC0841
LM607

S
S
S
S
I

AD7548
AD7548
AD7552
AD7552
AD7575

DAC123l
DAC1232
ADC1220
ADC1225
ADC0820

S
S
S
S
S

AD524
AD537
AD546
AD546
AD548

LM363
LM331
LPC660
LPC662
LF441

S
S
I
D

AD7ll
AD7l2
AD741
AD746
AD7502

LF4ll
LF4l2
LM741
LM6218
LF13509

S
S
D
I
S

AD7576
AD7578
AD7578
AD7820
AD7821

ADC0820
,...
ADC1205
ADC1225
ADC0820
ADC08061

S
S
S
D
I

AD549
AD549
AD562
AD563
AD565A

LPC660
LPC662
DAC1266
DAC1265
DAC1265

I
S
S
S

AD7523
AD7523
AD7523
AD7524
AD7524

DAC0830
DAC0831
DAC0832
DAC0830
DAC0831

S
S
S
S
S

AD7824
AD7828
AD844
AD846
AD847

ADC08064
ADC08068
LM6l8l
LM6l8l
LM6l6l

I
D

AD566A
AD567
AD573
AD581
AD582

DAC1266
DAC1230
ADC1005
LHOO70
LF398

S
S
S
I
S

AD7524
AD7533
AD7533
AD7533
AD7541

DAC0832
DAC1020
DAC102l
DAC1022
DAC12l8

S
D
D
D
S

AD848
AD849
AD96685
AD96687
ADDAC-08

LM6l64
LM6l65
LM6685
LM6687
DAC0800

D
D

AD583
AD588
AD589M
AD589U
AD590

LF398
LM369
LM385
LM185
LM134

S
S

AD7541
AD7541A
AD7541A
AD7542
AD7542

DAC12l9
DAC12l8
DAC12l9
DAC1208
DAC1209

S
S
S
S
S

ADDAC-08
ADDAC-08
ADOP07
HTC-0300

DAC0801
DAC0802
LM607
LH4860

D
D
I
S

I
S

The following notations are appended to assist you In finding the best option.

S - NSC Similar Device

I - NSC Improved Device

xxvi

D - NSC Direct Replacement

D

...

(")

Part Number

NSC
Part Number

Part Number

NSC
Part Number

Part Number

BURR-BROWN

~
fI)

NSC
Part Number

::a
CD

CHERRY

CD

3507
3507
3507
3507
3510

LHOO03
LMl18
LM6361
LM709
LM10l

S
S
S
S
S

OPAlll
OPA121
OPA121
OPA121
OPA156

LH0052
LF441 A
LH0022
LH0042
LF156

S
S
S
S
S

3510
3510
3510
3510
3533

LM107
LMl12
LM725
LM748
LH0033

S
S
S
S
S

OPA21
OPA21
OPA2111
OPA2111
OPA2111

LM108A
LMll
LF353
LF412A
LF442A

S
S
S
S
S

3542
3550
3551
3551
3553

LH0042
LM6361
LH0024
LM6361
LHOO02

S
S
S
S
S

OPA2111
OPA2111
OPA2111
OPA2111
OPA2111

LH2011
LH2101A
LH2108A
LM1558
LM358

S
S
S
S
S

3553
3554
3571
3572
3573

LH0063
LH0032
LM675
LH0021
LM675

S
S
S
S
S

OPA2111
OPA2111
OPA27
OPA27
OPA37

LM2904
LM747A
LH0044
LM627
LM637

S
S
S
S
S

3580
3580
3580
3606A6
3606A6

LHOO04
LMl43
LM144
LH0084
LH0086

S
S
S
S
S

OPA404
OPA404
OPA404
OPA511
OPA541

LF444A
LM837
LMC660
LM675
LH010l

S
S
S
S
S

3626
3629
AOC80
OAC7541A
OAC7541A

LH0036
LH0038
AOC1280
A07521
A07531

S
S
S
S
S

OPA541
OPA602
OPA605
OPA605
OPA633

LM12
LF4ll
LHOO05
LH0032
LH0033

S
S
S
S
S

OAC7541A
OAC7541A
OAC811
HOS-l00
HI-508

OAC1218
OAC1219
ADC1230
LH0033
LF13508

S
S
S
S
S

OPA633
PGA100/l02
PGA200/201
SHC298
SHC298

LH4001
LH0086
LH0084
LF298
LH0043

S
S
S
0
S

HI-509
INA10l
INA101HP
INA102
INA102

LF13509
LM163
LM363
LH0038
LM363

S
S
S
S
S

SHC5320
SHC80
SHC85
SHC85
VFC32

LH0053
LF398
LF398
LH0053
LM131/331

0
S
S
S
S

CS-189
CS-2907
CS-2917
CS-925
CS-935

LM1819
LM2907
LM2917
LM2925
LM2935

S
0
0
S
S

EHA2500
EHA2502
EHA2505
EHA251 0
EHA2512

LM6161
LM6161
LM6361
LM6161
LM6161

S
S
S
S
S

EHA2515
EHA2520
EHA2522
EHA2525
EHA2600

LM6361
LM6164
LM6164
LM6364
LM6161

S
S
S
S
S

EHA2602
EHA2605
EHA2620
EHA2622
EHA2625

LM6161
LM6361
LM6164
LM6164
LM6364

S
S
S
S
S

EL2006
EL2006C
EL2020
ELHOO02
ELH0021

LM6161
LM6261
LM6181
LHOO02
LH0021

S
S

ELH0032
ELH0033
ELH004l
ELH010l

LH0032
LH0033
LH004l
LH010l

0
0
0
0

= NSC SImilar Device

I

= NSC Improved Device

xxvii

D

= NSC Direct Replacement

CD
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ELANTEC

The lollowlng notations ara appandecl to aaaist you In IIndlng the bast option.
S

CiJ
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c

0
0

3

C"
CD

...

xxviii

...0

Part Number

NSC
Part Number

Part Number

NSC
Part Number

Part Number

0

NSC
Part Number

0
0

::D

!!.
CD

HARRIS (GE/RCAllntersil)
(Continued)
ADC0804
CA08l
CA08l
CA082
CA082

ADC0804
LF4ll
TL08l
LF412
TL082

D

CA084
CA084
CA124
CA139
CA139A

LF147
LF347
LM124
LM139
LM139A

5
5

CA1458
CA1558
CA158
CA158A
CA224

LM1458
LM1558
LM158
LM158A
LM224

0
0
0
0
0

CA239
CA239A
CA258
CA258A
CA301A

LM239
LM239A
LM25B
LM258A
LM301A

0
0
0
0
0

CA307
CA3l 05
CA3ll
CA324
CA3290

LM307
LM675
LM3ll
LM324
LM393

0

CA339
CA339A
CA3401
CA358
CA35BA

LM339
LM339A
LM3401
LM358
LM358A

0
0
D
0
D

CA741
CA747
CA748
DG201
DG211

LM741
LM747
LM748
LF13201
LF13201

D
0
0
0
0

DG212
HA-OP07
HA2400
HA2404
HA2405

LF13202
LM607
LM604
LM604
LM604

0
I

5
0

5
0

D
0
0

5
0
D

5

5
5
5

HA2406
HA2420
HA2420
HA2500
HA2502

LM604
LH0023
LH0043
LM6l6l
LM6161

5
5
S
S
S

HA5l4l
HA5l42
HA5l44
HA5l60
HA5160

LM4250
LF442
LF444
LF357
LH0062

5

HA2505
HA251 0
HA251 0
HA251 0
HA2512

LM6361
LM118
LM3l8
LM6161
LM6l61

5
5
5
5
5

HA5162
HA5170
HA5l70
HA5170
HA5170

LHOO62
LF151
LF155
LF156
LF157

5
5
5
5
5

HA2515
HA2520
HA2520
HA2522
HA2522

LM6361
LM6l64
LM6ll3
LM6l64
LM6113

5
S
5
S
5

HA5170
HA5170
HA5l80
HA51BO
HA5180

LF355
LF356
LH0022
LHOO42
LH0052

5
5
5
5
5

HA2525
HA2525
HA2529
HA2530
HA2535

LM6364
LM6313
LM6313
LH0024
LH0024

5
5
5
5
5

HF-l0
HF-201
HF-300
HI-20l
HI-508

MF10
LF1320l
AH5020
LF1320l
LF13508

0
0

5

HA2540
HA2541-2
HA2541-5
HA2542
HA2620

LH0032
LM6l6l
LM6361
LH0032
LH4l 04

5
5
5
5
S

HI-509
HI-56l8
HI-56l8
HI-56l8
HI-561B

LF13509
DAC0800
DACOB06
DAC0807
DAC0808

5
5
5
5
S

HA2620
HA2622
HA2625
HA2640
HA2640

LM6l64
LMl18
LM31B
LHOO04
LM143

5
5
5
5
5

HI-565A
HI-5660
HI-5680
HI-5685
HI-5685

DAC1265
DAC1266
DAC1280
DAC1200
DAC1285

0
0

5
5
5

HA2640
HA2645
HA2645
HA4741
HA5002

LMl44
LM343
LM344
LM348
LHOO02

5
5
5
5
5

HI-5687
HI-5687
HI-5690
HI-5695
HI-5697

DAC120l
DAC1285
DAC1280
DAC1285
DAC1285

5
5
5
5
5

HA5033
HA5020
HA5l 02
HA5l 04
HA5l35

LH0033
LM6181
LM833
LM837
LM637

5

HI-574
HI-574
HI-574
HI-574
HI-674

ADC1080
ADC1210
ADC12ll
ADC1280
ADC1080

5
5
5
5
5

I

5
5
5

The following notallon8 are appended to eeelst you In IIndlng the belli option.
S - NSC Similar Device

I - NSC Improved Device

xxix

D - NSC Direct Replacement

Cil

0
0

:::I

5
5

'<

0

5

(')

CD

0'

-...
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S»

Z

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3

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E
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Z

1::

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e4D

4D

a:

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e

0

Part Number

NSC
Part Number

Part Number

HARRIS (GE/RCAllntersil)
(Continued)

NSC
Part Number

Part Number

LINEAR TECHNOlOGY
CORP.

HI-674
ICH8530
ICL7114
ICL7114
ICL7660

ADC1280
LH0101
ADC1205
ADC1225
LMC7660

S
S
S
S
0

LF155
LF155A
LF156
LF156A
LF198

LF155
LF155A
LF156
LF156A
LF198

0
0
.0
0
0

ICL8069
ICL8069
IH5009
IH5010
IH5011

LM313
LM385·1.2
AH5009
AH5010
AH5011

0
0
0
0
0

LF198A
LF355A
LF356A
LF398
LF398A

LF198A
LF355A
LF356A
LF398
LF398A

0
0
0
0
0

IH5012
IH6106
IH6206
LM741

AH5012
LF13508
LF13509
LM741

0
0
0
0

LF412A
LH0070
LH21 08
LH2108A
LM10

LF412A
LH0070
LH21 08
LH2108A
LM10

0
0
0
0
0

LM101A
LM107
LM108
LM108A
LM111

LM101A
LM107
LM108
LM108A
LM111

0
0
0
0
0

LM117
LM117HV
LM118
LM119
LM123

LM117
LM117HV
LM118
LM119
LM123

0
0
0
0
0

LM129
LM129A
LM134
LM136
LM137

LM129
LM129A
LM134
LM136
LM137

0
0
0
0
0

LM137HV
LM138
LM150
LM185
LM199

LM137HV
LM138
LM150
LM185
LM199

0
0
0
0
0

LM234
LM308A
LM311
LM317
LM317HV

LM234
LM308A
LM311
LM317
LM317HV

0
0
0
0
0

HITACHI
HA12012
HA12411
HA12412
HA12413
HA12417

LM833
LM3089
LM3189
LM1868
LM1863

S
0
S
S
S

HA13421A
HA1374
HA1389
HA1394
HA1397

LM18293
LM2877
LM384
LM2879
LM1875

S
S
S
S
S

HA17082
HA17082A
HA17084
HA17084A
HA17094

LF353
LF412
LF347
LF347B
LM2904

HA17301
HA17324
HA17339
HA17358
HA17393

LM3301
LM324
LM339
LM358
LM393

HA17458
HA17741 .
HA17747
HA17901
HA17902
HA17903

LM458
LM741
LM747
LM2901
LM2902
LM2903

LM318
LM319
LM323
LM329
LM329A

LM318
LM319
LM323
LM329
LM329A

0
0
0
0
0

LM334
LM336
LM337
LM337HV
LM338

LM334
LM336
LM337
LM337HV
LM338

0
0
0
0
0

LM350
LM385
LM399
LM399A
LT1001

LM350
LM385
LM399
LM399A
LH0044

0
0
0
0
0

LT1001
LT1003
LT1003
LT1003
LT1004

LM607
LM123
LM323
LM337
LM113

S
S
0
0

LT1004
LT1004
LT1005
LT1008
LT1008

LM185
LM385
LM2935
LM108
LM308

0
0
S
0
0

LT1009
LT1009
LT1010
LT1011
LT1012

LM136
LM336
LHOO02
LM311
LM312

0
0
S
0
0

LT1013
LT1014
LT1014
LT1019
LT1020

LM358
LM324
LM348
LM368
LP2951

0
0
0
0
S

LT1021
LT1022
LT1029
LT1031
LT1033

LM369
LF356
LM336
LH0070
LM133

0
0
0
0

The followtng notallon. are appended 10 .....1you In flndlng Ihe best opllon.
S

= NSC SImilar Device

I

= NSC Improved DevIce

xxx

D

NSC
Part Number

= NSC Direct Replacemenl

I

0

Part Number

NSC
Part Number

Part Number

LINEAR TECHNOLOGY
CORP. (Continued)

NSC
Part Number

Part Number

a

NSC
Part Number

(I)
(I)

LT1033
LT1033
LT1034
LT1038C
LT1038M

LM137
LM333
LM385
LM396
LM196

S
0
0
S
S

LT1055
LT1056
LT111
LM317HV
LT117

LF355
LF356
LM111
LM317HV
LM117

0
0
0
0
0

LT118
LT119
LT123
LT123A
LT1223

LM118
LM119
LM123
LM123A
LM6181

0
0
0
0
I

LT137
LT150
LT1524
LT311
LT317

LM137
LM150
LM15240
LM311
LM317

0
0
0
0
0

LT317A
LT318
LT319
LT323
LT323A

LM317A
LM318
LM319
LM323
LM323A

0
0
0
0
0

LT337
LT338
LT338A
LT350A
LT3524

LM337
LM338
LM338A
LM350A
LM35240

0
.0
0
0
0

LTC1059
LTC1060
LTC1099
REF-01
SG1524

MF5
MF10
ADC0820
LM368
LM15240

0
0
0
S

SG3524

LM35240

A0565
A0566
A07523
A07523
A07523

OAC1265
OAC1266
OAC0830
OAC0831
OAC0832

0
0
S
S
S

LF444
LM101
LM108
LM109
LM11

LF444
LM101
LM108
LM109
LM11

0
0
0
0
0

A07524
A07524
A07524
A07533
A07533

OAC0830
OAC0831
OAC0832
OAC1020
OAC1021

S
S
S
0
0

LM111
LM117
LM123
LM124
LM137

LM111
LM117
LM123
LM124
LM137

0
0
0
0
0

A07533
A07541
A07541
A07542
A07542

OAC1022
OAC1218
OAC1219
OAC1208
OAC1209

0
S
S
S
S

LM139
LM140
LM148
LM150
LM158

LM139
LM140
LM148
LM150
LM158

0
0
0
0
0

A07542
A07545
A07545
A07545
A07548

OAC1210
OAC1208
OAC1209
OAC1210
OAC1230

S
S
S
S
S

LM193
LM201
LM208
LM209
LM211

LM193
LM201
LM208
LM109
LM211

0
0
0
0
0

A07548
A07548
A07820
ICL7642
MAX480

OAC1231
OAC1232
AOC0820
LMC6044
LMC6041

S
S
0
S
S

LM217
LM223
LM224
LM237
LM239

LM117
LM123
LM224
LM137
LM239

0
0
0
0
0

LM248
LM250
LM258
LM285
LM2900

LM248
LM150
LM258
LM285
LM2900

0
0
0
0
0

LM2901
LM2902
LM2903
LM2904
LM293

LM2901
LM2902
LM2903
LM2904
LM293

0
0
0
0
0

LM2931
LM301
LM307
LM308
LM309

LM2931
LM301
LM307
LM308
LM309

0
0
0
0
0

MOTOROLA
A0562
A0563
OAC-08
OAC-08
OAC-08

OAC1266
OAC1265
OAC0800
OAC0801
OAC0802

S
S
0
0
0

LF347
LF351
LF353
LF355
LF356

LF347
LF351
LF353
LF355
LF356

0
0
0
0
0

LF357
LF411
LF412
LF441
LF442

LF357
LF411
LF412
LF441
LF442

0
0
0
0
0

The following notations are appended to assist you In finding the best option.
S

= NSC S1mUar Device

I

= NSC Improved Device

xxxi

D

= NSC Direct Replacement

-.
:D

MAXIM

CD
CD
CD
:::::II

~

go

'<

-..-:
Z

C

3

.i

...
CII

.a
E

~

Z

1:
as
a.
>-

.a

CII
C,)

c

!
J!!
CII
a::

=
2

0

NSC

Part Number

NSC

Part Number

Part Number

NSC

Part Number

Part Number

Part Number

MC79MXXA
MC79XX
MC79XX
MC79XXA

LM79MXX
LM320-XX
LM79XX
LM320-XX

.1

/LA723
/LA741
1J-A747
AOCOB03
AOCOB04

LM723
LM741
LM747
AOCOB03
ADCOB04

0
0
0
0
0

AOCOB05
AOCOB20
AM26LS30
CA30B9
OAC-OB

AOCOB05
AOCOB20
083691
LM30B9
OACOB01

0
0
0
0
0

OAC-OB
OAC-08
ICM7555
LF198
LF224

OACOBOO
OAC0802
LMC555
LF198
LM224

0
0
0
0
0

LF298
LF398
LM111
LM119
LM124

LF298
LF398
LM111
LM119
LM124

0
0
0
0
0

LM139
LM139A
LM15B
LM193
LM193A

LM139
LM139A
LM15B
LM193
LM193A

0
0
0
0
0

LM211
LM219
LM224
LM239
LM239A

LM211
LM219
LM224
LM239
LM239A

0
0
0
0
0

LM25B
LM2901
LM2903
LM293
LM293A

LM258
LM2901
LM2903
LM293
LM293A

0
0
0
0
0

MOTOROLA (Continued)
LM311
LM317
LM323
LM324
LM337

LM311
LM317
LM323
LM324
LM337

0
0
0
0
0

MC1596
MC1709
MC1710
MC1723
MC1741

LM1596
LM709
LM710
LM723
LM741

D

LM339
LM340-XX
LM34B
LM350
LM35B

LM339
LM340-XX
LM34B
LM350
LM35B

0
0
0
0
0

MC1747
MC174B
MC3301
MC3302
MC3307B

LM747
LM74B
LM3301
LM3302
LMB33

0
0
0
0
8

LM3B5
LM3900
LM393
LMB33
MC1391

LM3B5
LM3900
LM393
LMB33
LM1391

0
0
0
0
0

MC33079
MC3346
MC3346
MC3356
MC3356

LMB37
LM3046
LM3146
LM30B9
LM31B9

8
0
I
8
8

MC140B
MC140B
MC140B
MC1414
MC1436

OACOB06
OACOB07
OACOBOB
LM1414
LM343

0
0
0
0
I

MC3361
MC34001
MC34001
MC34001
MC34002

LM3361A
LF351
LF353
LF411
LF412

I

MC1437
MC14442
MC14444
MC145040
MC145041

LH2301
AOC0829
ADC0830
AOC0811
AOC0811

8
8
8
8
0

MC34004
MC3401
MC341 0
MC3412
MC3456

LF347
LM3401
OAC1020
OAC1265
LM556

I
0
0
8
0

MC1455
MC1456
MC1458
MC146B
MC1488

LM555
LM212
LM1458
LM325
081488

0
8
0
8
0

MC35001
MC35002
MC351 0
MC4741
MC7812

LF411
LF412
OAC1020
LM348
LM7812

I
I
0
0
0

MC14B9
MC1496
MC1508
MC1514
MC1536

081489
LM1496
OACOB08
LM1514
LM143

0
0
0
0
I

MC7815
MC7824
MC78LXX
MC78LXXA
MC78MXX

LM7815
LM7824
LM78LXX
LM78LXXA
LM341-XX

0
0
0
0
0

MC1537
MC1537
MC1556
MC1558
MC1568

LH2101
LH2201
LM112
LM1558
LM125

8
8
8
0
8

MC78MXX
MC7BXX
MC78XXA
MC79LXX
MC79LXX

LM7BMXX
LM78XX
LM340A-XX
LM320L-XX
LM79LXXA

0
0
0
0
0

0
0
0
0

PHILIPS

The foll_lng notaUana are appended to assist you In finding the beat option.
S

~

NSC Similar Device

I

~

NSC Improved Device

xxxii

D

~

I

D

NSC Dlract Replacement

.

n
Part Number

NSC
Part Number

Part Number

NSC
Part Number

Part Number

0

••:2J

NSC
Part Number

CD

PHILIPS (Continued)
LM311
LM319
LM324
LM324A
LM339

LM311
LM319
LM324
LM324A
LM339

LM339A
LM358
LM393
LM393A
MC1408

LM339A
LM358
LM393
LM393A
OAC0807

0
0
0
0
0

AOC-910
ADC-91 0
AMP-01
AMP01
BUF-03

AOC1025
AOC1061
LHOO38
LM363
LHOO33

S
S
S
S

MC1408
MC1458
MC1488
MC1488
MC1489

·OAC0808
LM1458
051488
0514C88
051489

0
0
0

BUF-03
CMP-08
CMP-08
OAC-02
OAC-02

LHOOO2
LM260
LM360
OAC1020
OAC1021

S
S
5
5
5

OAC-02
OAC-03
OAC-03
OAC-03
OAC-05

OAC1022
OAC1020
OAC1021
OAC1022
OAC1020

S
5
5
5
5

0
0
0
0
0

0
0

SG2524
SG3524

LM2524
LM3524

0
0

PRECISION
MONOLITHICS INC.

I

MC1489A
MC1489A
MC1496
MC1508
MC1596

051489A
0514C89A
LM1496
OAC0808
LM1596

0
0
0

MC3302
MC3403
NE4558
NE5034
NE5118

LM3302
LM3403
LM833
AOC0841
OAC0830

0
0
5
5
5

OAC-05
OAC-05
OAC-08
OAC-08
OAC-08

OAC1021
OAC1022
OAC0800
OAC0801
OAC0802

5
5
0
0
0

NE5119
NE541 0
NE5532
NE5532
NE555

OAC0830
OAC1020
LM833
LM833
LM555

S
5
0
0
0

OAC-100
OAC-100
OAC-100
OAC-1408
OAC-1408

OAC1020
OAC1021
OAC1022
OAC0806
OAC0807

5
5
5
5
5

NE556
NE565
NE566
NE567
5A532

LM556
LM565
LM566
LM567
LM2904

0
0
0
0

OAC-1408
OAC-312
OAC-888
OAC-888
OAC-888

OAC0808
OAC1266
OAC0830
OAC0831
OAC0832

5
0
5
5
5

5A534
5E529
5E5537
5E555
5E556

LM2902
LM161
LF398
LM555
LM556

MAT02
MAT02AH
MUX-08E
MUX-24E
OP-05

LM394
LM194H
LF13508
LF13509
LM607

S
5
0
0
S

5E567
5G1532

LM567
LM1524

I

I
5
0
0
0

LM607
OP07
LF411
LF412
LM607

OP02
OP04
OP06
OP08
OP09

LM741
LM747
LM725
LM101
LM4136

S
S
S
S
S

OP11
OP11
OP14
OP14
OP14

LM324
LM348
LM1458
LM1558
LM358

S
5
5
5
5

OP15
OP15
OP15
OP160
OP177

LF351
LM301
LM310
LM6181
LM607

5
5
5

OP215
OP22
OP221
OP221
OP42

LF353
LM4250
LM2904
LM358
LHOO62

5
5
5
5
5

OP42
OP421
OP421
OP421
OP421

LM318
LM2902
LM324
LM3303
L2902

5
5
S
5
5

OP421
OP43
OP43GP
OP471
OP471

LP324
LM348
LF441ACN
LM149
LM837

5
S
5
5
5

OP490
OP77
OP97
PM0820
PM1008

LMC6044
LM607
LM311
ADC0820
LM308

S
S
5
0
0

0

The following notations are appended to assist you In finding the best option.
S

= NSC Similar Device

I

= NSC Improved Device

xxxiii

D

I

OP-07
OP-07
OP-15
OP-215
OP-77

= NSC Direct Replacement

0

Cit

i~

n

.,
CD
0'

I

I
5

'<

::a.
Z

c

:I

.

0'
CD

.

CD

.a
E
~

Z

Part Number

NSC
PartN"mber

1:

PRECISION
MONOLITHICS INC.

~

(Continued)

:.
CD

Co)

C

~

.;a::

.a
II)

(J

Part Number

NSC
Part Number

REF·43
5MP10
5MP10
5MP11
5MP11

LM136
LF398
LHOO43
LF398
LHOO23

SSM2139
SSM221 0
5W.Q6
5W-201
5W-202

LM833
LM394
LF13333
LF13201
LF13202

Part Number

0
5
5
5
5

PM1012
PM111
PM119
PM139
PM139A

LM312
LM111
LM119
LM139
LM139A

5

PM148
PM155
PM155A
PM156
PM156A

LM148
LF155
LF155A
LF156
LF156A

0
0
0
0
0

RAYTHEON

PM157
PM157A
PM208
PM208A
PM211

LF157
LF157A
LM208
LM208A
LM211

0
0
0
0
0

DAC-08
DAC-10
DAC-10
DAC-8012
DAC-6012

DAC0800
DAC-1020
DAC-1021
DAC-1220
DAC-1221

5
5
5
5
·5

PM219
PM248
PM308
PM308A
PM319

LM219
LM248
LM308
LM308A
LM319

0
0
0
0
0

LH2101A
LH2111
LM101A
LM111
LM124

LH2101A
LH2111
LM101A
LM111
LM124

0
0
0
0
0

PM339A
PM355
PM355A
PM356
PM356A

LM339A
LF355
LF355A
LF356
LF356A

0
0
0
0
0

LM139
LM148
LM2900
LM301A
LM324

LM139
LM148
LM2900
LM301A
LM324

0
0
0
0
0

PM357
PM357A
PM725
PM741
PM747

LF357
LF357A
LM725
LM741
LM747

0
0
0
0
0

LM339
LM348
LM3900
LP365
RC1458

LM339
LM348
LM3900
LP365
LM1458

0
0
0
0
0

PM7533
PM7533
PM7533
PM7541
PM7541

DAC1020
DAC1021
DAC1022
bAC1218
DAC1219

0
0
0

LM1558
LM348
LM348
LM325
LM326

0

5
5

RC1558
RC4156
RC4157
RC4195
RC4195

REF.Q1
REF·01
REF-02
REF.Q3
REF-03

LM368
LM369
LM368·5.0
LM336
LM385-2.5

5
5
5
5
5

RC714
RC741
RC747
REF·01
REF.Q1

!-M607
LM741
LM747
LHOO70
LM368

0
0
0
0

5
5

0
0
0

5
5
5
5

0
0
5
5

REF·01
REF.Q2
REF-02
REF.Q3

LM369
LM336·5.0
LM368-5
LM368·5

I
5
5

KA219
KA2803
KA2807
KA301
KA319

LM219
LM1851
LM1851
LM301
LM319

0

KA331
KA3524
KA431
KA710
KA78S40

LM331
LM3524D
LM431
LM710
LM78S40

0
0
0
0
0

KF347
KF351
KF442
LM224A
LM239

LF347
LF351
LF442
LM224A
LM239

0
0
0
0
0

LM248
LM258A
LM2901
LM2902
LM2903

LM248
LM258A
LM2901
LM2902
LM2903

0

LM2904
LM293
LM311
LM324
LM324A

LM2904
LM293
LM311
LM324
LM324A

0
0
0
0
0

LM3302
LM339A
LM348
LM358A
LM393

LM3302
LM339A
LM348
LM358A
LM393

0
0
0
0
0

LM393A
LM741
MC1458
MC78LXX
MC78MXX

LM393A
LM741
LM1458
LM78LXX
LM78MXX

0
0
0
0
0

SAMSUNG

Tbe following notations are appended to assist you In findIng tile best option.
S

= NSC SImIlar DevIce

I

= NSC Improved Device

xxxiv

D

NSC
Part Number

= NSC DIrect Replacement

5
5

0
0

5

0
0
0

0

Part Number

NSC
Part Number

Part Number

NSC
Part Number

Part Number

a

:::::u

NSC
Part Number

SAMSUMG (Continued)
MC78XX
MC79MXX
MC79XX
NE555
NE556

LM78XX
LM79MXX
LM79XX
LM555
LM556

D
D
D
D
D

SGSTHOMPSON
p.A741
p.A748
L293
L4940
L4941

LM741
LM748
LM18293
LM2940
LM2940

D
D
D
S
S

L78MXX
L78S05
L78XX
L78XX
L7912

LM78MXX
LM323
LM340-XX
LM78XX
LM7912

D

L79XX
L79XX
LF198
LF255
LF256

LM320-XX
LM79XX
LF198
LF255
LF256

D
D
D
D
D

LF257
LF298
LF351
LF353
LF355

LF257
LF298
LF351
LF353
LF355

D
D
D
D
D

LF355A
LF356
LF356A
LF357
LF357A

LF355A
LF356
LF356A
LF357
LF357A

D
D
D
D
D

LF398
LM101A
LM109
LM117
LM123

LF398
LM101A
LM109
LM117
LM123

D
D
D
D
D

LM124
LM124A
LM134
LM135
LM137

LM124
LM124A
LM134
LM135
LM137

D
D
D
D
D

I
D
D
D

LM139
LM139A
LM148
LM158
LM158A

LM139
LM139A
LM148
LM158
LM158A

D
D
D
D
D

LM334
LM335
LM336
LM336B
LM339

LM334
LM335
LM336
LM336B
LM339

D
D
D
D
D

LM1837
LM193
LM193A
LM201A
LM208

LM1837
LM193
LM193A
LM201A
LM208

D
D
D
D
D

LM339A
LM346
LM348
LM358
LM358A

LM339A
LM346
LM348
LM358
LM358A

D
D
D
D
D

LM211
LM218
LM219
LM223
LM224

LM211
LM218
LM219
LM223
LM224

D
D
D
D
D

LM393
LM393A
NE555
NE556
SE555

LM393
LM393A
LM555
LM556
LM555

D
D
D
D
D

LM224A
LM234
LM235
LM236
LM239

LM224A
LM234
LM235
LM236
LM239

D
D
D
D
D

SG556
SG2524
SG3524
SG3525
SG3527

LM556
LM2524
LM3524
LM3525
LM3527

D
D
D
D
D

LM239A
LM246
LM248
LM258
LM2901

LM239A
LM246
LM249
LM258
LM2901

D
D
D
D
D

TSA2040
TS272
TS274
TS27L2
TS27L4

LM1875
LMC662
LMC660
LPC662
LPC660

S
S
S
S
S

LM2902
LM2903
LM2904
LM293
LM2930

LM2902
LM3903
LM2904
LM293
LM2930

D
D
D
D
D

TS27M2
TS27M4

LMC662
LMC660

S
S

LM2931A
LM301A
LM308
LM308A
LM311

LM2931A
LM301A
LM308
LM308A
LM311

D
D
D
D
D

p.A723
p.A741
p.A747
ADC0801
ADC0802

LM723
LM741
LM747
ADC0801
ADC0802

D
D
D
D
D

LM318
LM319
LM323
LM324
LM324A

LM318
LM319
LM323
LM324
LM324A

D
D
D
D
D

ADC0803
ADC0804
ADC0805
ADC0820
CA3089N

ADC0803
ADC0804
ADC0805
ADC0820
LM3089

D
D
D
D
D

SIGNETICS

The following notations are appended to asalat you In finding the best option.
S

= NSC Similar Device

I

= NSC Improved Device

xxxv

D

= NSC Direct Replacement

-...
CD
CD
CD
~

n

CD

~
."
I»

:::.
Z

C

3

0"

...

CD

...

!

E
~

Z

1::

Part Number'

NSC
Part Number

Part Number

SIGNETICS (Continued)

NSC
Part Number

Part Number

NSC
Part Number

SILICON IX

CIS

a.
~
CD

()

C

!CD
CD

a:

I

0

OAC-08
OAC-08
OAc-08
ICM7555
LF198

OAC0800
OAC0801
OAC0802
LMC555
LF198

0
0
0
0
0

OG201
OG202
OG211
OG212
OG508

LF13201
LF13202
LF13201
LF13202
LF13508

0
0
0
0
0

LM158
LM185
LM193
LM201
LM207

LM158
LM185
LM193
LM201
LM207

0
0
0
0
0

LF298
LF398
LM2901
LM2903
LM311

LF298
LF398
LM2901
LM2903
LM311

0
0
0
0
0

OG509

LF13509

0

LM211
LM217
LM218
LM224
LM237

LM211
LM217
LM218
LM224
LM137

0
0
0
0
0

LM319
LM324
LM339
LM358
LM393

LM319
LM324
LM339
LM358
LM393

0
0
0
0
0

LM239
LM248
LM258
LM2900
LM2901

.LM239
LM248
LM258
LM2900
LM2901

0
0
0
0
0

MC1408
MC1458
MC1496
NE5034
NE5118

OAC0807
LM1458
LM1496
AOC0841
OAC0830

0
0
0

LM2902
LM2903
LM2904
LM2907
LM2917

LM2902
LM2903
LM2904
LM2907
LM2917

0
0
0
0
0

NE529
NE532
NE5410
NE5517
NE5537

LM361
LM358
OAC1020
LM13600
LF398

S

LM293
LM2930
LM2931
LM301
LM307

LM293
LM2930
LM2931
LM301
LM307

0
0
0
0
0

NE555
NE565
NE566
NE567
SA532

LM555
LM565
LM566
LM567
LM2904

0
0
0
0

LM317
LM318
LM324
LM330
LM337

LM317
LM318
LM324
LM330
LM337

0
0
0
0
0

SA534
SE5118
SE529
SE532
SE541 0

LM2902
OAC0830
LM161
LM158
OAC1020

I
S
S
S
S

LM339
LM348
LM358
LM385
LM3900

LM339
LM348
LM358
LM385
LM3900

0
0
0
0
0

SE566
SE567
SG3524

LM566
LM567
LM3524

0
0
0

LM393
LP111
LP211
LP239
LP2901

LM393
LP311
LP311
LP339
LP339

S
S

0
S

0
0

I

TEXAS INSTRUMENTS
UA2240
,...A709
,...A723
,...A741
,...A747

LM2240
LM709
LM723
LM741
LM747

0
0
0
0
0

,...A748
,...A78LXX
,...A78MXX
,...A78XX
,...A79MXX

LM748
LM78LXX
LM78MXX
LM78XX
LM79MXX

0
0
0
0
0

,...A79XX
ADC0803
ADC0804
AOC0805
AOC0808

LM79XX
AOC0803
AOC0804
ADC0805
AOC0808

0
0
0
0
0

ADC0809
ADC0820
AOC0831
AOC0832
AOC0834

AOC0809
AOC0820
ADC0831
ADC0832
ADC0834

0
0
0
0
0

AOC0838
LF198
LF347
LF351
LF353

ADC0838
LF198
LF347
LF351
LF353

0
0
0
0
0

LF398
LF411
LF412
LM101A
LM107

LF398
LF4l1
LF412
LM101A
LM107

0
0
0
0
0

LM108
LM111
LM124
LM139
LM148

LM108
LM1l1
LM124
LM139
LM148

0
0
0
0
0

lbe following notation. are appended to aS8Ist you In finding the bast option.
S

= NSC Similar Device

I

= NSC Improved Device

xxxvi

D

= NSC Direct Replacement

0
S
'S
S
S

n
Part Number

NSC
Part Number

Part Number

TEXAS INSTRUMENTS
(Continued)
LP311
LP339
LT1004
LT1009
MC1458
MC155
MC3303
MC3403
MC79LXX
MF10

LM1558
LM3303
LM3403
LM79LXX
MF10

Part Number

TLC14
TLC1541
TLC20
TLC252
TLC254

MF4-100
ADC1031
MF10
LMC662
LMC660

0

0
0
0
0
0

TLC25L2
TLC25M2
TLC25M4
TLC27L2
TLC27L4

LMC662
LMC662
LMC660
LMC6042
LMC6044

S
S
S

0
0
0
0
0

TLC27L7
TLC27M2
TLC27M4
TLC271
TLC272

LMC6062A
LMC682
LMC660
LMC6041
LMC6032

0
0
0

TLC274
TLC277
TLC339
TLC532
TLC533

LMC6034
LMC6082A
LP339
ADC0829
ADC0829

TLC540
TLC541
TLC545
TLC546
TLC549

ADC0811
ADC0811
ADC0819
ADC0819
ADC0831

S

TLC555

LMC555

0

TA7133
TA7140
TA7230
TA7232
TA7233

LM1391
LM386
LM1877
LM2896
LM2877

S
S
S
S
S

TA7268
TA7269
TA7282
TA7283
TA7313

LM1875
LM2878
LM2896
LM2896
LM386

S
S
S
S
S

TA7338
TA7366
TA7367
TA7370
TA7504

LM390
LM3914
LM3914
LM3361
LM741

S
S
S
S

TA75061
TA75062
TA75064
TA75071
TA75072

LF441
LF442
LF444
LF351
LF353

0
0
0
0
0

LP311
LP339
LM385
LM336
LM1458

NSC
Part Number

MF4
NE555
NE555
NE592
OP07

MF4
LM555
LM556
LM592
OP07

OP27
OP37
RC4136
RC4558
SA555

LM627
LM63
LM4136
LM833
LM555

SA556
SE2524
SE3524
SE555
SE556

LM556
LM2524D
LM3524D
LM555
LM556

SE592
TL061
TL062
TL064
TL071

LM592
LF441
LF442
LF444
LF351

TL071
TL072
TL072A
TL074
TL0808

LF411
LF353
LF412
LF347
ADC0808

TL0809
TL081
TL082
TL084
TL087

ADC0809
TL081
TL082
LF347
LF411

TL088
TL287
TL288
TL317
TL431

LF411
LF412
LF412
LM317
LM431

S
S
S

TL592
TLC04
TLC0820
TLC10
TLC1225

LM592
MF4
ADC0820
MF10
ADC1225

0
0
0
0
0

0
I
I

0
0
0
I

S

0
S
S

I
I
S
S

I
I
S
S

0
S

0
0
S

TOSHIBA

I

0
0
D
D

I
S

0
0

0

a

NSC
Part Number

I

:II

TA75074
TA75092
TA75092
TA75339
TA75339

LF347
LM2902
LM324
LM2901
LM339

TA75358
TA75358
TA75393
TA75393
TA75458

LM2904
LM358
LM2903
LM393
LM1558

TA7555
TA7612
TA7613
TA7630
TA7640

LM555
LM3914
LM1868
LM1036
LM1868

S
S
S
S

TA76524
TA7654
TA7667
TA7688
TA7758

LM3624
LM3914
LM3915
LM1896
LM1868

S
S
S
S
S

TA7769
TA78LXX
TA78MXX
TA78XXX
TA79LXXX

LM1896
LM78LXX
LM78MXX
LM78XX
LM79LXX

S

TA79XXX
TA8117
TA8119
TA8202
TA8211

LM79XX
LM1868
LM1896
LM1877
LM2878

S
S
S
S

TC9154

LMC1982

S

L293
UCH7
UC137
UC150
UC1524

LM18293
LM117
LM137
LM150
LM1524D

0
0
0
0

UC2524
UC317
UC337
UC350
UC3524

LM2524D
LM317
LM337
LM350
LM3524D

UC78XX
UC78XX
UC79XX
UC79XX

LM340-XX
LM78XX
LM320-XX
LM79XX

I
S

0
0
0
I

0
0
0

fCil
:::a
a
a"

'<

-:

::l
Z

C

:I

a"
CD
~

0
0
0
0
0

UNITRODE

I

0
0
D

I

0
0
0
0

The following notations are appended to ....81 you In flndlnll the beat option.
S - NSC Similar Davlce

I - NSC Improved DevIce

D - NSC DIrac! Replacement

xxxvii

~~-

.-~---.

~--

.. ----.

...

_-----

----------

rIJ

Industry Package Cross-Reference Guide

NSC

CJ
MmV

~=

~
In

@

CJ
~

?

0

D
m

NSC

p.A

Signetics

Motorola

TI

AMD

Spraque

0

R

4/16 Lead
Glass/Metal DIP

0

0

I

L

Glass/Metal
Flat Pack

F

F

Q

F

F,
5

F

TO-99, TO-100, TO-5

H

H

T,
K,
L,
DB

G

L

H

B-, 14- and 16-Lead
Low Temperature
Ceramic DIP

J

F

U

J

0

H

P

A,
B,
M

R,
0

(Steel)
K5

K
T0-3

KC

K

OA

K

N

T,'
P

N,
V

P

K

(Aluminum)

B-, 14- and 16-Lead
Plastic DIP

'With dual-in-Une formed leads
"With radically formed leads

xxxviii

P,

N

NSC

f~

~;

~=~
I

TO-202
(0-40, Ourawatt)

TO-220
3-&5-Lead
TO-220
11-, 15- & 23-Lead

NSC

p.A

Signetics

Motorola

TI

AMD

Sprague

P

T

U

KC

U

T

Low Temperature
Glass Hermetic
Flat Pack

W

F

TO-92
(Plastic)

z

W

M

5

5

F

W

F

P

LP

0

0

L

OW

LW

G

0

bUUUUUd

RRRRRRRRRR

SO

(Narrow Body)
(Wide Body)

WM

)

•

1::1 1::1 IH:I I:H::I 1::1 1::1 1::1 1::1

bJOOUUtR:R:RJ

xxxix

5,
0

U

'a

"5
CJ
u
Co)
c
!u
';
a:

NSC

NSC
p.A

S1gnetlcs

Motorola

TI

AMD

Spraque

PCC

V

Q

A

FN

FN

L

EP

LCC
Leadless Ceramic
Chip Carrier

E

L1

G

U

FKI
FG/FH

L

EK

•

(I)

2

(.)
U

a»
as

~

Co)

l.

. tnIlilIIDDJ
~

:;:,
'a

oS

II~~~~~~~II

xl

Section 1
Audio Circuits

III

Section 1 Contents
Audio Circuits Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Circuits Selection Guide .......................................................
LM380 Audio Power Amplifier. . . . . . . . . .. .. . . . . . ... .. .. .. . . . . .. .. .. . .. . .. .. .•. .. . .. . . .
LM383 7 Watt Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM384 5 Watt Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM386 Low Voltage Audio Power Amplifier. .. . . .. ..... .. .. .. . . .•.. . . .. . ..•. .. .... ... ..
LM388 1.5-Watt Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array. . . . . . . . . . . . . . . . . . . . .
LM3901 Watt Battery Operated Audio Power Amplifier..................................
LM391 Audio Power Driver..........................................................
LM831 Low Voltage Audio Power Amplifier............................................
LM832 Dynamic Noise Reduction System DNR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM833 Dual Audio Operational Amplifier....... ........................................
LM837 Low Noise Quad Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .
LM1035/LM1036 Dual DC Operated TonelVolume/Balance Circuits......................
LM1037 Dual Four-Channel Analog Switch............................................
LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement Facility.
LM1131A Dual Dolby B-Type Noise Reduction Processor.. .. .. .. .. .. . .. • ... .. .. .. .. ... ..
LM1151 Dolby B-Type Noise Reduction System........................................
LM1875 20 Watt Power Audio Amplifier...............................................
LM1877 Dual Power Audio Amplifier..................................................
LM1894 Dynamic Noise Reduction System DNR ..................•....................
LM1896/LM2896 Dual Power Audio Amplifiers.........................................
LM2877 Dual 4 Watt Power Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2878 Dual 5 Watt Power Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM2879 Dual 8 Watt Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3875 High Performance 40 Watt Audio Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3876 High Performance 40 Watt Audio Power Amplifier. . . . . . . . . . . . . . . . • • . . . . . . . . . . . . .
LMC835 Digital Controlled Graphic Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMC1982 Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo
Inputs. . . .. .. .. .. .. .. . . . . . . . .. . . .. . . . . . . . . .. .. ... . ... .. . .. .. ... . .. .•. .. . . . . .. ... .
LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo
Inputs...........................................................................
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel
Input-Selector ...................................................................

1-2

1-3
1-4
1-7
1-11
1-15
1-20
1-25
1-31
1-39
1-44
1-55
1-67
1-75
1-84
1-90
1-100
1-106
1-116
1-121
1-122
1-128
1-133
1-141
1-149
1-156
1-163
1-170
1-171
1-172
1-187
1-198
1-209

~National

~ Semiconductor

Audio Circuits
Definition of Terms
Amplifier

the audio channel. Dolby level provides this reference and
corresponds to a specified tape flux density when recorded
with a 400 Hz tone. For reel to reel and eight track cartridge
tapes this is 185 nWb/m, and for cassettes Dolby level is
200 nWb/m.

Class A
A class A transistor audio amplifier refers to an amplifier
with a single output device that has a collector flowing for
the full 360' of the input cycle.

Large-8ignal Voltage Gain
The ratio of the output voltage swing to the change in input
voltage required to drive the output from zero to this voltage.

ClassB
The most common type of audio amplifier that basically consists of two output devices each of which conducts for 180'
of the input cycle.

Output Resistance
The ratio of the change in output voltage to the change in
output current with the output around zero.

ClassC
In a class C amplifier the collector current flows for less than
180'. Although highly efficient, high distortion results and
the load is frequently tuned to minimize this distortion (primarily used in R.F. power amplifiers).

Output Voltage Swing
The peak output voltage swing, referred to zero, that can be
obtained without clipping.

Class 0
A switching or sampling amplifier with extremely high efficiency (approaching 100%). The output devices are used as
switches, voltage appearing across them only while they are
off, and current flowing only when they are saturated.

Power Bandwidth
The power bandwidth of an audio amplifier is the frequency
range over which the amplifier voltage gain does not fall
below 0.707 of the flat band voltage gain specified for a
given load and output power.
Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 6 dB below the rated output. For example, an amplifier rated at 60 watts with
';:0.25% THD, would make its power bandwidth measured
as the difference between the upper and lower frequencies
at which 0.25% distortion was obtained while the amplifier
was delivering 30 watts.

Crossover Distortion
Distortion caused in the output stage of a class B amplifier.
It can result from inadequate bias current allowing a dead
zone where the output does not respond to the input as the
input cycle goes through its zero crossing point. Also for
IICs an inadequate frequency response of the output PNP
device can cause a turn-on delay giving crossover distortion
for negative going transition through zero at the higher audio frequencies.

Power Supply Rejection
The ratio of the change in input offset voltage to the change
in power supply voltages producing it.

DolbyB
Dolby B is a simplified version of the Dolby A professional
quality noise reduction system. The amplitude of low level
signals over a selected frequency range is increased prior to
recording to enhance them above tape noise. On playback
the original levels are restored causing a corresponding reduction in the audible tape noise. The major difference with
Dolby A which used four frequency bands, is the use of a
single variable frequency band with a cut-off frequency that
increases in the presence of high level high frequency signals.

Slew Rate
The internally limited rate of change in output voltage with a
large amplitude step function applied to the input.
Supply Current
The current required from the power supply to operate the
amplifier with no load and the output at zero.
Thermal Resistance (RTH)
An analogy for heat transfer where the ability of a heat conductive system to transfer heat is described in similar terms
to those used in an electrical system for power dissipated in
a resistor with a given applied voltage. The thermal resistance is given by the temperature differential
established when a given amount of power is being dissipated (8 = T1 - T2/Po) with units of ·C/watt.

Dolby Level
Because of the complementary nature of the Dolby B noise
reduction system, the audio channel between the encoder
and the decoder must have a fixed gain such that the decoding signal level is within 2 dB of the encoding signal
level. Also if recordings are interchangeable the signals in
the noise reduction system must be related to the levels in

1-3

II

~National
Semlconduclor

Audio Circuits Selection Guide
Preamplifiers/Systems
Application
Portable

Package

Voltage
Range

Equivalent
Input Noise

THO

PSR

Input
Coupling

Notes

Home

Auto

LM833
(Note 1)

•

•

8 Pin DIP
8 Pin SO

±5V-±15V

0.5/LV

0.0020/0

100dB

DC

Low Noise
DualOpAmp

LM837
(Note 1)

•

•

14 Pin DIP
14 Pin SO

±5V-±15V

0.5/LV

0.0020/0

100dB

DC

Low Noise
Quad Op Amp
Drives SOOO Load

Audio Power Amplifiers
Application

•

LM380
LM383

•

LM384

Power·

Package

Portable Home Auto

80
8 Pin DIP
14 Pin DIP

•
•
•

40

@

Voltage

20

2.5W

14.4V

Yes

0.20/0

22V

Yes

0.250/0

Single Fixed Gain

8 Pin DIP
8 Pin SO

0.33W

SV

0.20/0

Single 4V Operation
20 mW Quiescent

0.10/0

Single 4V Operation
Min Externals

0.20/0

Single Includes
Transistor
Array

5.5W 8.SW

•

14 Pin DIP

2.2W

12V

LM389

•

18 Pin DIP

0.33W

SV

LM831

•

16PinDIP
1SPinSOlC

O.44W

LM1877
LM2877

•
•

•
•

Single Protected

Yes

0.250/0 3/LV

SV

Yes

0.20/0

Single Battery
Operation

10-100W

6OV-100V

Yes

0.010/0 3/LV

Single Shutdown Pin,
Thermal Protected
Power Driver

14 Pin DIP

3W

20V

0.050/0 2.5/LV

Dual 6V-24V

11 Pin SIP

4.5W

20V

0.070/0 2.5 /LV

Dual Flexible
Application

1S Pin DIP

•
•

Yes

2/LV

3V

14 Pin DIP

•

LM391

Single See AN-S9
Fixed Gain

5.5W

LM388

•

0.20/0

Notes

14 Pin DIP

5 Pin TO-220

•

LM390

bl THO. Input Singlel
rl gea e
Noise. Dual

18V

LM38S

•

B ·d

1W

Dual

1.8V-6V

I

i
I

1-4

Audio Power Amplifiers
Application

(Continued)
Power·

Package

all

Portable Home Auto
LM1896

•

•

•

14 Pin DIP

LM2896

•

•
•

•

11 Pin SIP

LM2878
LM12

@

411 20. Voltage
1.1W

Bridgeable THO·

6V

Yes

Input Singlel
Noise' Oual

0.1 %

1.4 !LV

Dual

Notes
Low AM
Radiation, 3V Op

9V

Yes

0.1 %

1.4 !LV

Dual

No Pops, 3-15V Op

22V

Yes

0.15% 2.5 !LV

Dual

6V-32V

50W 85W

±30V

Yes

0.01 %

9 !LV

Single Power Op Amp;
SeeAN-446

25W

±25V

0.015%

3,..V

Single Low Distortion
AtH. Power

2.5W

11 Pin SIP

5.5W

•

4-Pin TO-3

LM1875

•

5 Pin TO-220

LM2879

•

11 Pin TO-220 8W

28V

Yes

0.05% 2.5 !LV

Dual

6V-32V

'Note that all values shown are typical. Please refer to datesheets for test conditions.

Audio Controls
Application

Package

Voltage
Range

20 Pin DIP

8V-18V

18 Pin DIP

5V-25V

Portable Home Auto
LM1035/
LM1036

•

•

LM1037

•

•

LM13600
(Note 1)
LM13700

•

•

·•

•

•

•

LM3080
(Note 1)

•

•

•

8 Pin DIP

•

•

24 Pin DIP

•

•

LM1040

LMC835

•

Volume
Signal to
THO
Control Range Noise
BOdB

Separation

BOdB

0.05%

75dB

Dual DC Controlled
TonelVolume/Balance

100dB

0.04%

100dS

DC Audio Switch

0.5%

100dS

Dual Transconductance
Amplifiers

16 Pin DIP ±2V-±18V
16PinSO
16 Pin DIP
16 Pin SO

Transconductance
Amplifier

±2V-±18V
9V-16V

Notes

75dB

80dB

0.06%

28 Pin DIP ±2.5V-±8V ±12dB/Sand

114dB

•

75dS

Dual DC Controlled
TonelVolume/Balance
Stereo Enhancement
7 Band Stereo
Graphic Equalizer
MICROWIRETM
Controlled; See AN-435

LMC1982

•

28 Pin DIP

7V-15V

80 dB

95dB

0.008%

BOdB

2 Stereo Inputs Volume/
Tone/Fade/Select
Enhanced Stereo Loudness
Comp. 1M Controlled

LMC1983

•

28 Pin DIP

7V-15V

80dB

95dB

0.008%

80 dB

3 Stereo Inputs Volume/
~one/Fade/Select

Loudness Compo
1M Controlled
LMC1992

•

•

28 Pin DIP

7V-15V

BOdB

'Oistorlicn determined by external op amps.
Note 1: Oatesheet in Operational AmplHiers Oalabook.

1-5

105dB

0.03%

95dB

4 Stereo Inputs Volume/
Tone/Fade/Select
MICROWIRETM
Controlled

II

Noise Reduction
Application

Package

Portable Home Auto
LM1131
LM1894
LM832

•
•
•

•
•
•

•
•

Voltage
Range

NR
Type

SV-20V

Encoding Singlel Decode
NR
Effect" Required Duall
SIN'

Notes

Dolby®

10dB

Ves

Dual

90 dB

14 Pin DIP, SO 4.SV-18V DNR®

12dB

No

Dual

76 dB

NSCSystem

DNR®

10dB

No

Dual

72 dB

See AN-384, 386, 390

18 Pin DIP

14 Pin DIP, SO 1.SV-9V

'Note that all values shown are typical; Please refer to datasheets for test conditions.
CNRe is a registered trademark of National Semiconductor Corporation.
Colby"' Is a registered tradarnark of Dolby Laboratories Licensing Corporation.

1-6

DC Switched

~National

~ Semiconductor

LM380 Audio Power Amplifier
General Description
A selected part for more power on higher supply voltages is
available as the LM384. For more information see AN-69.

The LM380 is a power audio amplifier for consumer application. In order to hold system cost to a minimum, gain is
internally fixed at 34 dB. A unique input stage allows inputs
to be ground referenced. The output is automatically self
centering to one half the supply voltage.
The output is short circuit proof with internal thermal limiting.
The package outline is standard dual-in-line. A copper lead
frame is used with the center three pins on either side comprising a heat sink. This makes the device easy to use in
standard p-c layout.

Features
•
•
•
•
•
•
•
•

Wide supply voltage range
Low quiescent power drain
Voltage gain fixed at 50
High peak current capability
Input referenced to GND
High input impedance
Low distortion
Quiescent output voltage is at one-half of the supply
voltage
• Standard dual-in-line package

Uses include simple phonograph amplifiers, intercoms, line
drivers, teaching machine outputs, alarms, ultrasonic drivers, TV sound systems, AM-FM radio, small servo drivers,
power converters, etc.

Connection Diagrams (Dual-In-Line PackaSles, Top View)
BVPASS 1

'4 v.

NDN·INVERTINO INPUT 2

13 Ne

Ne ,

11 GND

,

*

INVERTING INPUT 3

• Me

INVERTING INPUT •
GND 1

•

, >,

MUlotNVERTING INPUT 2

'.]

oaNu{:

• BYPASS

•

VOUT

I GND

GND "

V OUT

TLlH/6977 -2

Order Number LM380N·8
See NS Package Number N08E

TUH/6977-,

Order Number LM380N

See NS Package Number N14A

Block and Schematic Diagrams
LM380N
BVPASS

. - - - - - - - - - - - -. .----1_0>,1141

v.

....

,

INPUT

r-_ _ _"'2S~·""""----J---_~-o~~TPUT

aN. al.
TUH/6977-3

BYPASS

III

LM380N-8
BYPASS >,

...
"

'NPUT

VOUT

'.UT
al.

-,.Itl

1--.....-0".
121

01.

TUH/6977-4
171 GND

(3.4.5.10.11,12)

al.

TLlH/6977-5

1-7

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
22V
Peak Current
1.3A
Package Dissipation 14-Pin DIP (Notes 6 and 7)
S.3W
1.67W
Package Dissipation S-Pin DIP (Notes 6 and 7)

Input Voltage
Storage Temperature
Operating Temperature
Junction Temperature
Lead Temperature (Soldering, 10 sec.)
ESD rating to be determined

±0.5V
-55·Cto + 150·C
O"Cto +70"C
+ 150"C
+26O"C

Electrical Characteristics (Note 1)
Symbol

Parameter

POUT(RMS)

Output Power

Conditions
RL =

sn, THO =

Min

3% (Notes 3, 4)

Typ

Max

Units

50

60

VIV

2.5
40

W

Av

Gain

VOUT

Output Voltage Swing

ZIN

Input Resistance

THO

Total Harmonic Distortion

(Notes 4, 5)

0.2

%

PSRR

Power Supply Rejection Ratio

(Note 2)

3S

dB

Vs

Supply Voltage

BW

Bandwidth

RL =

sn

14

Vp-p

150k

n

10
POUT = 2W; RL =

10

Quiescent Supply Current

VOUTO

Quiescent Output Voltage

ISlAS

Bias Current

sn
S

Inputs Floating

22

7

25

9.0

10

100

Short Circuit Current
1.3
Isc
Note 1: Vs = ISV and TA = 25'C unless otherwise specified.
Note 2: Rejection ratio referred to the output with CSYPASS = 5,..F.
Note 3: With device Pins 3, 4, 5, 10, 11, 12 soldered into a 'h." epoxy glass board with 2 ounce copper foil with a minimum surface of 6 square inches.
Note 4: CaVPASS = 0.47 ,..fd on Pin 1.
Note 5: The maximum junction temperature of the LM380 is t 50'C.
Note 6: The package is to be derated at 15'C/W junction to heat sink pins for 14-pln pkg; 75'C/W for S-pin.

Heat Sink Dimensions

,y
3~"

~

r- '"---1
1.5

I

I

I

I

I

I
I
I
I

I

I
I

~

TT
1.5"

J

1.55

j

Staver Heat Sink #V-7
Staver Company
41 Saxon Ave.
P.O. Drawer H
Bayshore, NY 11706
Tel: (516) 666·8000
Copper Wings
2 Required
Soldered to
Pins 3, 4, 5,
10,11,12
Thickness 0.04
Inches

--l0.25!-TL/H/6977 -6

1-8

V
Hz

100k

mA
V
nA
A

Typical Performance Characteristics
Maximum Device Dissipation vs
Ambient Temperature
10
9

I I I

I

I I I

I
.,....

INFINnt HEAT SINK

111

STA~lvJ- 6 liN. SQ.
,COPPER WINGS

'I':LER

~
3SCC/J!

~
~CC~

FREE AIR

o

2 IN. SQ.
COPPER FOIL (P.C. IIOARO)

o

so

10 20 30 40

60 70 80 90 100

TA-AMBIENT lIMPERATURE (CC)
Note: 2 oz••opper 101, IIng...."d.d PC board••

3.5

LEVEL

i...

r;;. ~ ,:... -.

I.D

i

1.5

12V
lDV

..
!.

!

"-

,...

U

1.0

0.5

./

"":'"

'"
~.

~

/

"'ill.... I-

::
r;-'
JIIU: .

"1% B I-~I-

iiI-

i."
i

!

3.0

/
/.f""

2.5

I.!;.v
,.

2.0

1.5

16

1.D

~

0.5 1.0 1.5 'Z.O

Z.S U

'"

I

o 0.5

3.5 4.8

7.1

,

i

5.•

-......

,......

2.0

12

14

I.

16

10

..

1.0

~

-,~

20

1\. an

t; 7.0

~
~

1.4
1.2

;; I.. 1-+++1-+-++1+-+-1
1-+t+I-+-++t+-+-l
D.

IDO 200

500

I

!

D••

V

-~ r- ... ~ 181.

iii

11/

u

0.2

~ 0.1

2k

0.6

1.0

5.

.L,~

2.1

I.D

Po - OUTPUT _ER (WATTS)

lOll 2!H1

.
~.
~

III

I I

P1 AfEI

IS

10

0.1

0.2

wi

1

WI'

POUT· ZW

300'
0
10

50dS

6,R

100

310'

" " I
''''' 10010

"

1M

10M

lOd.

II
I

11111
11111

....

UdS

I I
_Ivc~ • IV
0.3

120'

I\-IIi"

10

A
2.F

lL
V

0.'

OUTPUT POWER (WATTS)

lDd.

F::

"

U7p.F

II!III

I I

I/~"'" ~'3%THO
1\ ~ 40ul

...

III

20

2Ddl

1,.,.1"

..

~!~

25

Supply Decoupling vs
Frequency

'T~O

/

Vc. -IIV

FREQUENCY 1Hz)

I I
I 1/

1 I
0.2

i
C
'"
>

/

10.3

w

2.0
1.0

0

II

Device Dissipation vs
Output Power

is

0.1

••

.

LE,VEL,

Output Voltage Gain and
Phase vs Frequency

30

~

~u
c

~~.

:--'" ~~~t:!t

40
36

~
~

e

lIfl

I-

• 0.5 1.0 1.5 2.' 2.5 3.0 15 .... 4.5 5.0

I-+++I-+-++I+:~v= In

l..;'

....

-

0.5

1-+t+I-+-++t+-+--i

0.5

COPHRWINGS
SEE FIG. PAGE 4

: ....

~

FREDUENCY 1Hz)

NUTSINK "TWO

:: I.D
; 5.0

6

1.8

22

Ycc= uv

I.'

•

1.0

l:l

U

'"

1kHz

211

~

Total Harmonic Distortion
vs Output Power

=

1.5

z

y. SUPPLY VOLTAGE IV)

l

'"~

ii5

....-....-,...,...---....---r.....,....-...,.......,

lW'

10

~

5!

OUTPUT POWER (WATTS)

~ O.21!!.r~9:M::j=~~~~II~
L

1.0
•.0

LEVEL

I .• 1.5 2.0 2.5 3.0 3.5 4.0 •. 5 5.1

- :: -jiTlf-i

3.0

~

3% OIST.

Total Harmonic Distortion
vs Frequency

!

4.0

i,

~~~'-tt
"1%

II

",2.1

S 2.0

OUTPUT POWER (WATTSI

T.=25"C-

1.0

-I":

OIST .

2.•

10.0
9.0

V,> A"

Device Dissipation vs Output
Power-160 Load

u

LEVEL

Power Supply Current vs
Supply Voltage
.... '.0

~r-.

l-

0.5

OUTPUT POWER IWATTSI

C
.!

r-.

I-

12Vr,: !"

u

o

•

-

3.'

3%01ST.

3.0

TUH/6977-'2

Device Dissipation vs Output
Power-80 Load

Device Dissipation vs Output
Power-40 Load

NO

.Y~l~I~APACltm

11111111
D.'

10Hz

100Hz

1kHz

III

'.k"z

FREQUENCY

TUH/6977-7

1-9

•

Typical Applications
Phono Amplifier

CRYSTAL

CARTRIDGE

TlIH/6977 -8

Bridge Amplifier

TlIH/6977-9

Intercom

v,

LISTEN

I

*,t.F!

TILl

~

R_TE~,:,

_
I
L__________________________
I

I
I

~

-FDR STABILITY WITH

HIBH CURRE.' LOADS

TlIH/8977-10

Phese Shift Oscillator

'!!iUHa:

T"T"T.1
":"

-:"

":"

TlIH/6977-11

1-10

~National

~ Semiconductor

LM383/LM383A 7 Watt Audio Power Amplifier
General Description

Features

The LM383 is a cost effective, high power amplifier suited
for automotive applications. High current capability (3.5A)
enables the device to drive low impedance loads with low
distortion. The LM383 is current limited and thermally protected. High voltage protection is available (LM383A) which
enables the amplifier to withstand 40V transients on its supply. The LM383 comes in a 5-pin TO-220 package.

•
•
•
•
•
•
•
•
•

High peak current capability (3.5A)
Large output voltage swing
Externally programmable gain
Wide supply voltage range (5V-20V)
Few external parts required
Low distortion
High input impedance
No turn-on transients
High voltage protection available (LM383A)

• Low noise
• AC short circuit protected

Equivalent Schematic
5

........H ......;,40

L-~~~

__

+INPUT

~

__

~

______

~

__

~

__

~

____

~

____________________

Vs

VOUT

•
~3~GNO

-INPUT
TL/H17145-1

Connection Diagram
Plastic Package
6 SUPPLY VOLTAGE

o

4 OUTPUT
3 GROUND
2 INVERTING INPUT
1 NON·INVERTING INPUT
TUH/7145-2

Order Number LM383T or LM383AT
See NS Package Number T05B

1-11

Absolute Maximum Ratings
Input Voltage

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for svailability and specifications.
Peak Supply Voltage (SO ms)
LM383A (Note 2)
LM383

40V
25V

Operating Supply Voltage

20V

Output Current
Repetitive
Non-repetitive

3.5A
4:5A

Conditions

100 (40 dB), RL

Typ

Max

7.2

8

V

45

80

rnA

20

5

= 40dB
= 13.2V, f = 1 kHz
= 40, THD = 10%
= 20, THD = 10%
= 13.8V, f = 1 kHz
= 40, THD = 10%
= 20, THD = 10%
= 14.4V, f = 1 kHz
= 40, THD = 10%
= 20, THD = 10%
= 1.60, THD = 10%
= 16V, f = 1 kHz
= 40, THD = 10%
= 20, THD = 10%
= 1.60, THD = 10%
Po = 2W, RL = 40, f = 1 kHz
Po = 4W, RL = 20, f = 1 kHz
Rs = 500,f = 100Hz
Rs = 500, f = 1 kHz
RS = 0, 15 kHz Bandwidth
Rs = 100 kO, 15 kHz Bandwidth

Bandwidth

Gain

Output Power

Vs
RL
RL
Vs
RL
RL
Vs
RL
RL
RL
Vs
RL
RL
RL

Input Noise Current

40, unless otherwise specified

6.4

Input Resistance

Input Noise Voltage

=

260"C

Min

Excludes Current in Feedback Resistors

Supply Voltage Range

Ripple Rejection

- 6O"C to + 15O"C

Lead Temperature (Soldering, 10 sec.)

DC Output Level

THD

O"Cto +70"C

Storage Temperature

D

Quiescent Supply Current

15W

Operating Temperature

Electrical Characteristics Vs = 14.4V, TTAB = 25 C,Av =
Parameter

±0.5V

Power Dissipation (Note 3)

4.8
7

30

Units

V

150

kO

30

kHz

4.7
7.2

W
W

5.1
7.8

W
W

5.5
8.6
9.3

W
W
W

7
10.5
11

W
W
W

0.2
0.2

%
%

40
44

dB
dB

2

p,V

40

pA

Note 1: A 0.2 p.F capacitor in series with a HI resistor should be placed as close as possible to pins 3 end 4 for stability.
Note 2: The LM383 shuts down above 25V.
Note 3: For operating at elevated temperatures, the device must be derated based on a 150'C maximum junction temperature and a thermal resisiance of 4"C/W
Junction to case.

1-12

Typical Performance Characteristics
Power Dissipation vs
Output Power

Device Dissipation vs
Ambient Temperature
11

.
i

co

S

T

14
12

1r7~'--r-.--r-~~
tFljTE jEAT II'~-

rl

a

I I I I
I I I I
I

W H H

~

o

m DO n DO

4

..

~

m

c

21

-30

i:

--40

1111

5 -so

i
..

12

I

~

~

100

........

30

~

II

o

lk

10k

o

I

4 6 8 11 12 U 11 11 20

FREQUENCY (Hz!

VSUPPLY (VI

Distortion vs Frequency

Distortion vs Output Power

~Ho'.,~
RL

....

10

10

I
I

f- AV ' 1DO
VS"UV
f-RL -4

~21L

I
VI

10

8

co

1'/
o

40

-80
1M

Output Power vs
Supply Voltage

"
"
14

50

ill

.~

--

FREQUENCY (H,'

20

C
.!
I-

~

lOOk

11110

8 W 12 U 11 11

E~CL'uois C~RR'ENi IN
FEEo8ACK RESISTORS f - - f -

RS'SO

-1.

~
~

I"

10
0
100

146

Supply Current vs
Supply Voltage

. ~ -20

l"-

DO
41
30

I I

o

70
;;;

.-"1HO-1011

OUTPUT POWER !WI

Supply Ripple Rejection
vs Frequency

II

I

111214

OUTPUT POWER !WI

I.
II
7'

V

V~'2JV- r- ..... ~

i""" ,THO - 3%

I VS',5V
:1/ 1/ ~
~~V

Open Loop Gain
vs Frequency

,.co
...co

-

II

TA - AMIIENT TEMPERATURE rCI

w

RL -2
14
12

t- J.c~ HElT II,!;" ......

il:co

....
~

II

-

1~cJ HEA~ SlJK
J

II

!!!co

I
•C

Power Dissipation vs
Output Power

.o{L' 4

o

I

D._ r1.5W~: I:;;

I

'"

o 1:=:I:::I::I:I:I:I:III==='='!&WlIJ

4 I I W 12 U 11 11 20

0.1

o

II

10

50 loa 100 5DD lk Ik

OUTPUT POWER (W)

VSUPPLY IVI

Output Swing vs
Supply Voltage

Distortion vs Frequency
10

10
f-AV"00
VS' 14.4V
f-RL =2

~L~~ ~

II

1
~

i
I
l-

Z.5W~~

I

5k 10k 28Ic

FREQUENCY (Hz!

o

18
14

RL-4 7

II
10

V

I

~

&

~ ......RL·I_f-

liP

o
20

10 lao 200 5ID 1k 2k

Sk 10k 10k

o

FREQUENCY (HzI

I

4

8 I 10 II 14 16 II 10
VSUPPLY (VI
TL/HI7145-4

1-13

•

Typical Applications
Single Amplifier

TLlH17145-3

16W Bridge Amplifier

Vs

Vs

lUV

lUV

lhF
SIGNAL
INPUT.

.......J

1M

lOOk

TL/H17145-5

Component Layout
Single Amplifier
Vs

RL

= 20V
= 40

Healsink from:
Staver Company

41 Saxon Ave.
P.O. Drawer H

Bay Shore, .NY 11706
Tel: (516) 666-8000

TL/H17145-6

1-14

IIZI National
~ Semiconductor

LM384 5 Watt Audio Power Amplifier
General Description

Features

The LM384 is a power audio amplifier for consumer application. In order to hold system cost to a minimum. gain is
internally fixed at 34 dB. A unique input stage allows inputs
to be ground referenced. The output is automatically selfcentering to one half the supply voltage.

•
•
•
•
•
•
•
•

The output is short-circuit proof with internal thermal limiting. The package outline is standard dual-in-line. A copper
lead frame is used with the center three pins on either side
comprising a heat sink. This makes the device easy to use
in standard p-c layout.
Uses include simple phonograph amplifiers. intercoms. line
drivers. teaching machine outputs. alarms. ultrasonic drivers. TV sound systems. AM-FM radio. sound projector systems. etc. See AN-69 for circuit details.

Schematic Diagram

Wide supply voltage range
Low quiescent power drain
Voltage gain fixed at 50
High peak current capability
Input referenced to GND
High input impedance
Low distortion
Quiescent output voltage is at one half of the supply
voltage
• Standard dual-in-line package

r----------------....-----...-O

V.(4)

.5
25k

OUTPUT

fB)
BYPASS

.5

fH

t--t--o+IN

-INn..._--'

fBI

(2)

150k

fl,4. 5, 10, 11, 12)
(7) GNO

GND
TL/HI7B43-3

1-15

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
28V
Peak Current
1.3A

Power Dissipation (See Notes 3 and 4)
Input Voltage
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec.)

1.67W
±0.5V
-65·Cto + 150"C
O·Cto +70"C
26O"C

Electrical Characteristics (Note 1)
Symbol

Parameter

ZIN

Input Resistance

IBIAS

Bias Current

Av

Gain

POUT

Output Power

Conditions

Min

Typ

Max

150

kO

100

Inputs Floating

THO = 10%, RL = 80

40

50

5

5.5

Units

nA

60

VIV
W

10

Quiescent Supply Current

8.5

VOUTO

Quiescent Output Voltage

11

V

BW

Bandwidth

450

kHz

V+

Supply Voltage

Isc

Short Circuit Current (Note 5)

1.3

A

PSRRRTO

Power Supply Rejection Ratio
(Note 2)

31

dB

POUT = 2W, RL = 80
12

THO
Total Harmonic Distortion
POUT = 4W, RL = 80
Note 1: V+ ~ 22V and TA ~ 25"C operating with a Staver V7 heat sink for 30 seconds.
Nole 2: Rejection ratio referred to the output with CSYPASS ~ 5 p.F, lreq ~ 120 Hz.
Note 3: The maximum lunction temperature 01 the LM384 is 150'C.
Nole 4: The package is to be derated at t 5'C/W lunction to heat sink pins.
Note 5: Output is fully protected against a shorted speaker cond~ion at all voHages up to 22V.

26

0.25

Heat Sink Dimensions
Staver "V7" Heat Sink
Staver Company
41 Saxon Ave.
P.O. Drawer H
Bay Shore. N.Y.
Tel: (516) 686-8000

~16

'''1

l' \\\\\\\\
"ppp..
1.35

~v;S

1---

15
.
TL/HI7843-4

1-16

25

1.0

mA

V

%

Typical Performance Characteristics
Device Dissipation va
Ambient Temperature
12.0

..
(

',,,,,

10.0

;:

f

I

''''''

.,." ......

1.0

Thermal Resistance vs
Square Inches
90

.......

''''''EO''

~~t... f-

r',:~ ::';i1-!;!~!;~ ~';'2~~
~5'~"~ ..." ~

'.0

. '~"
t"" .""

w
u

~

'.0
2.8

10

!....

10

!Ii:

78

w

i.
I.
~

60

30 '8

50

&0

70

80

vcc • 2Iv
R, -8

lllIlI

........

r- r--

i

21

~

3l
4J.
;rr

V

IrIF

NOCA~

.-

II

o

Total Harmonie Distortion
vs Frequency

...:;;
..
i
..iii

d.•

III
II.

~

I

u

ii

I'"

c

'"

0.3

0.2

I.~
1111l1li

III

1"111111""

2W

E

RL -8

~

18

IDle

1M

lotio

Power Supply Current vs
Supply Voltage
2A

..... .-

(

!"
f

I
w

~
l!:

2.2
2.0
1.1
1.6
U
1.2
I .•
0.1
D.&
GA

0.2
1.

22

SUPPLY VOLTAGE IVI

2&

iATSINK

10k
1.
100
FREQUENCY IHzl

111M

Device Dissipation vs
Output Power-160 Load

10

1.

STAVER "yr'

FREQUENCY IHzl

OUTPUT POWER IWI

II

~
~Vcc -22V

0.1

~

;!:
1.0

tOk

"

FREQUENCY fHl)

u

'0

111111111

100

10

~~V~~ ··J7!.IJ~IAT Sl~K

8

t-

41/IF

to ,/

o

.0 I"'TTTI11"-m,II1II'""'M'

I

111111

31

Output Voltage Gain vs
Frequency

tI~~~TMmr--~-nTMn

I

:!!

...

........

'1

SQUARE tNCHES OF COPPER FOIL
P.C. BOARO HEAT SINK

Total Harmonic Distortion
vs Output Power

...:;;
..
i

,

40

T. - AMBtENT TEMPERATURE r'cl

~

...

\
\

50

30

20

Supply Decoupling vs
Frequency

lOOk

Device Dissipation vs
Output Power-80 Load
6

r-- ~

121VI

MV

tf

uv ......... 1'0.

r-7'~
r-o";
16V

V

1'0.

--

~ ~Y

,,'

"

"" '"' olr.

MY

uv

II

C>-~

.,.17" ~

I ..... ~OY [2'..,.

3% OIST. LEVEL

LEyEL_

~;.JJ

I I
~~ t:: '10%IDIST.I LEVE~_
I I I I I
"vr' HEAT SINK

r-- - - STAYER "V7" HEAT SINK

STAYER
1

311

OUTPUT POWER IWl

2

3

4

5

6

7

8

9 10

OUTPUT POWER IWI

Device DISSipation vs
Output Power--40 Load

OUTPUT POWER 11'11

TUHI7843-5

1-17

~

CD
CO)

~

r---------------------------------------------------------------------------------,
Block and Connection Diagrams
Dual·ln·Llne Package

BYPASS

BYPASS 1

14 Vs

NDN·INVERTING INPUT Z

13 NC

Vs

121

11 GND'

Vour

10
I

INVERTING INPUT 6
GND

GND 7

GND

NC

Vour

TUHI7843-1

"Heatsink Pins

TUH/7843-2

Top View
Order Number LM384N
See NS Package Number N14A

Typical Applications
Typical 5W Amplifier
+22V

V,N

......

11111~t----

8n

TUHI7843-6

Bridge Amplifier
8.1~F

,~

V.

TUHI7843-7

1-18

r----------------------------------------------------------------------,~

iii:

Typical Applications (Continued)

!

Intercom

v.

l.lpF

b.

Co
":' 51IpF

LISTEN

•

LISTEN

T1 ·25:1

PALK

I
I

I
I
I
_
II
L
~
I __________________________
I
'For stability with
high current loads

TL/HI7843-8

Phase Shift Oscillator

v.

lk

' .. 4kHz

l' l' l'
D.lpF

D.lpF

D.l~F
TL/HI7843-9

\

1-19

!

=s ~

National

~ Semiconductor

LM386 Low Voltage Audio Power Amplifier
General Description
The LM386 is a power amplifier designed for use in low
voltage consumer applications. The gain is internally set to
20 to keep external part count low, but the addition of an
external resistor and capacitor between pins 1 and 8 will
increase the gain to any value up to 200.
The inputs are ground referenced while the output is automatically biased to one half the supply voltage. The quiescent power drain is only 24 milliwatts when operating from a
6 volt supply, making the LM386 ideal for battery operation.

Features
•
•
•
•

Battery operation
Minimum external parts
Wide supply voltage range
Low quiescent current drain

4V-12V or 5V-18V
4mA

•
•
•
•
•

Voltage gains from 20 to 200
Ground referenced input
Self-centering output quiescent voltage
Low distortion
Eight pin dual-in-line package

Applications
•
•
•
•
•
•
•
•

AM-FM radio amplifiers
Portable tape player amplifiers
Intercoms
TV sound systems
Line drivers
Ultrasonic drivers
Small servo drivers
Power converters

Equivalent Schematic and Connection Diagrams
Dual-In-Llne and Small Outline
Packages

r----------------------------------------------t--------~~~

GAIN

GAIN

-INPUT -r-..--I .....

BYPASS

+INPUT

v.
VOUT

GNO

-INPur

TLlH/6976-2

Top View

4
L--4--~----------------__~-4----~--------~~--------~~G.O
TL/H/6976-1

Order Number LM386M-1,
LM386N-1, LM386N-3 or LM386N-4
See NS Package Number
M08Aor N08E

Typical Applications
Amplifier with Gain = 200

Amplifier with Gain = .20
Minimum Parts

v.

v,.

I~)"

I
~PASS
-,-

~

10

':'

':'
TL/H/6976-4

TLlH/6976-3

1-20

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (LM386N·1, -3, LM386M·1)
15V
Supply Voltage (LM386N-4)
22V
1.25W
Package Dissipation (Note 1) (LM386N)
(LM386M)
0.73W
Input Voltage
±0.4V
-65·Cto + 150"C
Storage Temperature
Operating Temperature
O"Cto +70"C

Electrical Characteristics
Parameter

Junction Temperature
+ 150"C
Soldering Information
Dual-ln·Une Package
Soldering (10 sec)
+26O"C
Small Outline Package
+215·C
Vapor Phase (60 sec)
Infrared (15 sec)
+ 220"C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods 01 soldering surface mount devices.

TA = 25·C
Conditions

Operating Supply Voltage (Vs)
LM386N-1, -3, LM386M-1
LM386N-4

Min

Typ

4
5

Quiescent Current (Ia)

Vs = 6V, VIN = 0

Output Power (POUT)
LM386N-1, LM386M-1
LM386N-3
LM386N-4

Vs = 6V, RL = 80, THO = 10%
Vs = 9V, RL = 80, THO = 10%
Vs = 16V, RL = 320, THO = 10%

4
250
500
700

Max

Units

12
18

V
V

8

mA

325
700
1000

mW
mW
mW

Voltage Gain (Av)

Vs = 6V,I = 1 kHz
10 ,..F from Pin 1 to 8

26
46

dB
dB

Bandwidth (BW)

Vs = 6V, Pins 1 and 8 Open

300

kHz

Total Harmonic Distortion (THO)

Vs = 6V, RL = 80, POUT = 125 mW
f = 1 kHz, Pins 1 and 8 Open

0.2

%

Power Supply Rejection Ratio (PSRR)

Vs = 6V, f = 1 kHz, CBYPASS = 10,..F
Pins 1 and 8 Open, Referred to Output

50

dB

Input Resistance (RIN)
50
kO
Vs = 6V, Pins 2 and 3 Open
250
nA
Input Bias Current (IBIAS)
Note 1: For operation in ambient temperatures above 25"C. the device must be derated based on a 150"C maximum junction temperature and 1) a thermal
resistance of 80"C/W iunction to ambient for the dual·in·line package and 2) a thermal resistance of 170"C/W for the amall outline package.

Application Hints
GAIN CONTROL
To make the LM386 a more versatile amplifier, two pins (1
and 8) are provided for gain control. With pins 1 and 8 open
the 1.35 kO resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 1 to 8, bypassing the 1.35 kO resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be set to any value from 20
to 200. Gain control can also be done by capacitively coupiing a resistor (or FEn from pin 1 to ground.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 5 (paralleling the internal 15 kO resistor). For 6 dB effective bass boost: R .. 15 kO, the lowest
value for good stable operation is R = 10 kO if pin 8 is
open. If pins 1 and 8 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9.

INPUT BIASING
The schematic shows that both inputs are biased to ground
with a 50 kO resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM386 is higher than 250 kO it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kO, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
When using the LM386 with higher gains (bypassing the
1.35 kO resistor between pins 1 and 8) it is necessary to
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,..F capacitor or a short to ground depending on the de source resistance on the driven input.

1-21

~

Typical Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency

Quiescent Supply Current
vs Supply Voltage

--

I

I-

i..

I- -~

B

ii
:!!

I-

HmrHioHlt+lilllllH+I+IHH

iO

II

!
i

i

•

~~~~~~OO-H*~

I

7

I

I

10

11

,.

IZ

sumv VOLTAGE evOlTSI

Voltage Gain vs Frequency

.
;;

z.a

ii

4U

10

I. ,. I.

11
I

I~

R, =11'

POUT" 12& mW

co

1.4
1.2

Av

..

i

11

D.I
0.1

i •

1M

10 50 lat 2. iOl

1.2

is

1.8
fA
fA

t.Z

........

. / Vs-IV

./

~

I

.J

~THO

~ " . lEVEL

_ v.-tv

1.1

I

J .... ,BTHO

lEVEL

t.Z
D.3
fA
OUTPUT POWER CWI

II

i

I

I~

"

Zk

~

i

1
I
D••'

Ik 1Il10 ZIIIo

Device Dissipation vs Output
Power-80 Load
2.1
1.1

v.Lzv- I---

1.4

iiii
!" ...

Vs=IV
RL -Iu
'·1kHz

G.l1

...

1.8

FREOUENCV CHII

I
I

1.1

Distortion vs Output Power

;!

....

O.Z

Device Dissipation vs Output
Power-40 Load

1.1

4i17891111'Z

;;

=DdB ce ... - 01

~

-

4 f-

11

'.0
u

.!. I-

I

!!
II

I I

I

1.6

FREQUENCV CHII

z.o

I

I'

SII"l VVOL lAGE evOl TSI

I

V. =IV

co

i
..•.cco~

31

>

~

~~

Distortion vs Frequency

!! '.1

;

1k

~

~~
.;'! ~

Ie

FREQUENCV CHII

II

3
!!
cco
w
co

......::

~
co
w

zo HtHllll'1fttHfll--tt
'0

I

R';,-~ ~

11

~

4U

i ~~~Tm~~~~~

4

I

Peak-to-Peak Output Voltage
Swing vsSupply Voltage-

a.5

..

i

I I I

I I I

1.1

'r~

co 1.4

Ii

I

I.Z
1.1

D.I

I ...
"u
t.Z
I

"I I

1/

I.a

Device Dissipation vs Output
Power-160 Load

-,
I

V,a12Y

rt~ "'V.-~ I
ffJ' YJ.-I!I..,J:.::~THO
~

LEVEL

IBTHO

*

I ' " D.Zt.3fAUO.IUa.tD.lI.8

D D.Z DA D.5 fA 1.1 1.2 1.4 1.1 I.t Z.I

OUTPUT POWER CWI

OUTPUT POWER CWI

1-22

TUH/6976-5

Typical Applications (Continued)
Amplifier with Gain = 50

Low Distortion Power Wienbrldge Oscillator
311

v.

ELDEMA

Vo

CF-5-ZI58

I-UHz

TL/H/6976-6

Uk

a.lloF

T
TL/H/6976-7

Amplifier with Bass Boost

Square Wave OSCillator

v.
V.

+~r"
I
Ion

Ik
1= 1kHz

TUH/6976-8

TUH/6976-9

Frequency Response with Bass Boost
21
26
25

iii
:!!

24

C

23

z

CD

III

22

CD

......
c

21

'">

20

II"

I\.

J

I

I

\

\

19

~

......

18
11

20

50 100 200 500 lk 2k

5k 10k 20k

FREQUENCY (Hz)
TUH/6976-IO

1-23

CD

~

Typical Applications

(Continued)

AM Radio Power Amplifier
Cc

FRDM~

Vso-+-...,

DETECTOR ..,....,

FERRITE
BEAD

=

+1
250pF

+

*D.Os"F

all

SPEAKER

":"

TUH/6976-11

Note 1: Twist supply lead and supply ground very tlghUy.

Note 4: R1Cl band IimHs input signals.

Note 2: Twist speaker lead and ground very tighUy.

Note 5: All components must be spaced very close to IC.

Note 3: Ferrite bead is Ferroxcube K5·001'()OI/3B with 3 turns of wire.

1-24

~National

~ Semiconductor

LM388 1.5 Watt Audio Power Amplifier
General Description
The LM388 is an audio amplifier designed for use in medium
power consumer applications. The gain is internally set to
20 to keep external part count low, but the addition of an
external resistor and capacitor between pins 2 and 6 will
increase the gain to any value up to 200.
The inputs are ground referenced while the output is automatically biased to one half the supply voltage.

Features
•
•
•
•
•

Minimum external parts
Wide supply voltage range
Excellent supply rejection
Ground referenced input
Self-centering output quiescent voltage

•
•
•
•

Variable voltage gain
Low distortion
Fourteen pin dual-in-line package
Low voltage operation, 4V

Applications
•
•
•
•
•
•
•
•
•

AM-FM radio amplifiers
Portable tape player amplifiers
Intercoms
TV sound systems
Lamp drivers
Line drivers
Ultrasonic drivers
Small servo drivers
Power converters

Equivalent Schematic and Connection Diagrams
Dual-In-Line Package

14

Vs
14

BYPASS

15k

Vs

GAIN

13
Your

. .!
II

GAIN
-INPUT

-INPUT

TL/H/7846-2

Top View
3.4.5.
10.11.12
GNU
TL/HI7846-1

1-25

Order Number LM388N-1
See NS Package Number N14A

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

Input Voltage

-65'Cto +15O"C

Operating Temperature

15V

Package Dissipation 14-Pin DIP (Note 1)

±0.4V

Storage Temperature

8.3W

O"Cto +70"C

Junction Temperature

15O"C

Lead Temperature (Soldering, 10 sec.)

26O"C

Electrical Characteristics TA = 25'C, (Figure 1)
Symbol

Parameter

Conditions

Vs

Operating Supply Voltage
LM388

10

Quiescent Current
LM388

VIN = 0
Vs = 12V

POUT

Output Power (Note 2)
LM388N-1

R1
Vs
Vs

Voltage Gain

Av

Min

Typ

Bandwidth

THO

Total Harmonic Distortion

PSRR

Power Supply Rejection Ratio
(Note 3)

RIN

Input Resistance
Input Bias Current

12

V

23

mA

16

= R2 = 1800, THO = 10%
= 12V,RL = 80
= 6V, RL = 40
Vs = 12V, f = 1 kHz

1.5
0.6

2.2
0.8

23

26
46

= 12V,Pins2and60pen
Vs = 12V, RL = 80, POUT = 500 mW,
f = 1 kHz, Pins 2 and 6 Open
Vs = 12V, f = 1 kHz, CBYPASS = 10 p.F,
Vs

IBIAS

Units

4

10 p.Ffrom Pins 2t06
BW

Max

30

dB
dB

300

kHz

0.1

Pins 2 and 6 Open, Referred to Output
10
Vs

W
W

= 12V, Pins 7 and 8 Open

%

1

50

dB

50

kO

250

nA

Note 1: Pins 3. 4. 5, 10. 11. 12 at 25'C. Derate at 15'C/W above 25'C case.
Note 2: The amplifier should be in high gain for full swing on higher supplies due to Input voltage limitations.
Note 3: If load and bypass capacitor Bra retumed to Vs (F1(JUf9 2), rather than ground (Figurrll), PSRR is typically 30 dB.

Typical Performance Characteristics
Maximum Device DI88lpatlon vs
Ambient Temperature
10

.

i

co
1=

i

co

!

9

•
•
7

5

4=~

3
2

1
D

II

10

I I I I

ii

IIIFINITEftEATSIIIIC

I I
I I
I I

FREE AI

Power Supply Rejection Ratio
(Referred to the Output) va
Frequency

Quiescent Supply Current vs
Supply Voltage

"!""CIW
HIN. 0.

C.~E~;.IL

==:

IT""
r-1C; i::i~:'L ~7.J.r.; If.!:tII ZI 3D 40 .1 II 71 II II 1.
T. - AMBIENT TEII'ERATURE rCI
N...: 2 ... coppor foil."'_ PUallll.

1

i..

..

:!!

•co

41

Ii

i

..

:!a:

30

a:

./

ZO

I/'

10

V-

~
iii
a:

V-

I

D

..

4

II
1.
I
SUPfLYVOLTA8EM

ID

11"
1.~

31

V

m

V.-1ZV

Av o 2ldB

.&oF

II

za
10

11111

,~

41

D

0

ll~F

V

I'

l'

I.

l'

1.

FREQUENCY (Hz)

I.
Tl/HI7846-5

1-26

Typical Performance Characteristics
Peak-to-Peak Output Voltage
Swing vs Supply Voltage

(Continued)

Voltage Gain vs Frequency

IDr--'~-,--~---.~~

an

I~~_,'~ij

so

J ..

i

~

II

II:

co

..I.=
Ii
co

~

-

r-

c

ZI

'"

1111

SUPPLY VOLTAGE IV)

..=

II

..

D." 21

1M

1.1 ' 0.81

-

1.1

~
'1.0

~v.~v

I. , •• 20.

r--,---,---,--...,..--,

..

Z.I

1--+-+-+---+--1

~

1.D1-:::;ii.t"'d--+

i.

/. ~ fT V~i 12V

-

ri-f51 1011111 III Il 2k

co

~~~~ \
~

'"'!-1"

2.1

i

II1!1THO
LEVEL

r--..

Av' ZIII

Device Dissipation vs
Output Power-80 Load

VI-fIV

'-1kHz
Cu-D

/
"

FREOUENCY IHI)

Device Dissipation vs Output
Power-40 Load

;!

S
=

10111<

RL -10

~
Ii=
Ii
.== 1.0
II

o.z I"-

FREDUENCY 1Hz)

Distortion vs Output Power

i!

1.

lk

1

I"

D.6
0.4

L.~

o

10

V.-12V
RL =3r!
·D·O.5W

i!!!i

10

II

10
I

;::

.Il~-!

30

Distortion vs Frequency

i!

s·av

~

..

1.5

III

11

POWER DUTPUT IWl

OUTPUT POWER IWl

DUTPUT POWER IWl

Device Dissipation vs
Output Power-160 Load
Z.I

..

i

2

i

I

~

z.o

II

1.&
1.0

..

~12V
~ 1.5
~.-.

!liTHO
LEVEL
IIIITHOrvuf
V.-IV

~_

o

00.51.01.52.02.1

OUTPUT POWER IWl

TL/HI7846-6

Application Hints
GAIN CONTROL
To make the LM388 a more versatile amplifier, two pins (2
and 6) are provided for gain control. With pins 2 and 6 open,
the 1.35 kO resistor sets the gain at 20 (26 dB). If a capacitor is put from pins 2 to 6, bypassing the 1.35 kO resistor,
the gain will go up to 200 (46 dB). If a resistor is placed in
series with the capacitor, the gain can be set to any value
from 20 to 200. A low frequency pole in the gain response is
caused by the capacitor working against the external resistor in series with the 1500 internal resistor. If the capacitor
is eliminated and a resistor connects pins 2 to 6 then the

output dc level may shift due to the additional dc gain. Gain
control can also be done by capacitively coupling a resistor
(or FEn from pin 6 to ground, as in Figure 7.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 6 to 13 (paralleling the internal 15 kO resistor). For 6 dB effective bass boost: R '" 15 kO, the lowest
value for good stable operation is R = 10 kO if pin 2

1-27

Application Hints (Continued)
is open. If pins 2 and 6 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9 VIV.

beta is the value required for the current in R 1 and R2:
(R1

INPUT BIASING

+ R2)

=

Po (Vs/2) -

VBE
lOMAX

Good design values are VBE = 0.7V and Po = 100.

The schematic shows that both inputs are biased to ground
with a 50 kO resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM388 is higher than 250 kO it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kO, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.

Example: 1 watt into 80 load with Vs = 12V.
lOMAX
(R1

+ R2)

=~
- PO = 500mA
RL

= 100 (12/2) - 0.7) = 10600

0.5

To keep the current in R2 constant during positive swing
capaCitor CB is added. As the output swings positive CB lifts
R1 and R2 above the supply, maintaining a constant voltage
across R2. To minimize the value of CB, R1 = R2. The pole
due to CB and R1 and R2 is usually set equal to the pole
due to the output coupling capacitor and the load. This
gives:

When using the LM388 with higher gains (bypassing the
1.35 kO resistor between pins 2 and 6) it is necessary to
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,..F capacitor or a short to ground depending on the dc source resistance on the driven input

4Co Co
CB"'-""-

Po

.25

Example: for 100 Hz pole and RL = 80; Co = 200 ,..F and
CB = 8 ,..F, if R1 is made a diode and R2 increased to give
the same current, CB can be decreased by about a factor of
4, as in Figure 4.

BOOTSTRAPPING

For reduced component count the load can replace R1. The
value of (R1 + R2) is the same, so R2 is increased. Now CB
is both the coupling and the bootstrapping capacitor (see
Figure 2).

The base of the output transistor of the LM388 is brought
out to pin 9 for Bootstrapping. The output stage of the amplifier during positive swing is shown in Rgure 3 with its
extemal circuitry.
R1 + R2 set the amount of base current available to the
output transistor. The maximum output current divided by

Typical Applications
RI
Vs

Va

510

IDk~""-""I

TLlHI7846-3

TLlHI7846-4

FIGURE 1. Load Returned to Ground
(Amplifier with Gain = 20)

FIGURE 2. Load Returned to Vs
(Amplifier with Gain = 20)

1-28

Typical Applications

(Continued)

~

r----...-O v•

r.

~OV'

F_. ._ . .

14

Rl

R2

TlIHI7848-7

FIGURE 3

Tl/HI7848-8

FIGURE 4. Amp"ler with Gain = 200 and Minimum CB
Vs

m

270

22,.F
V,N

22"F

270

= 411

Vs- 6V

RL

Vs - 12V

RL-

TlIHI7848-9

PO-l.OW
Po=4W

eo

FIGURE 5. Bridge Amp
610
Z1
21

.

24
Z3

ow

zz

j
g

;,.
CD

~::...--....-~.....~ I-~~Ovo

II

II
II
I.
II
17

I

I

"

I\,
~

~

"
II

50 lID III III Ik

a

110 Ilk 2ft

FREQUENCY (HII

TlIH/7848-11

FIGURE
TlIHI7846-IO

FIGURE 6a. Amplifier with Bass Boost

1-29

ab. Frequency Respon. .
with Ba.. Boost

•

Typical Applications (Continued)

..-------,

vso-~.-

2.7

3.4.5
10.11.12

TALK

TALK

..

--------.....,~---o LISTEN

REMOTE

TL/H/7846-12

FIGURE 7. Intercom

510

Cc

FROM........j
DETECTOR

""I
10ilF
FERRITE
BEAD

4.7

TLlHI7846-13

FIGURE 8. AM Radio Power Amplifier
Note 1: Twist supply lead and supply ground very tightly.

Note 4: RICI band limits input signals.

Note 2: Twist speaker lead and ground vsry tighUy.

Note 5: All components must be spaced very close to IC.

Note 3: Ferrite bead is Ferroxcube KS'()OI'()OI/38 with 3 tums of wire.

1-30

~National
~ Semiconductor

LM389 Low Voltage Audio Power Amplifier
with NPN Transistor Array
• Low quiescent current drain
• Voltage gains from 20 to 200
• Ground referenced input
• Self-centering output quiescent voltage
• Low distortion
Transistors
• Operation from 1 ,.A to 25 mA
• Frequency range from DC to 100 MHz
• Excellent matching

General Description
The LM389 is an array of three NPN transistors on the same
substrate with an audio power amplifier similar to the
LM386.
The amplifier inputs are ground referenced while the output
is automatically biased to one half the supply voltage. The
gain is internally set at 20 to minimize external parts, but the
addition of an external resistor and capacitor between pins
4 and 12 will increase the gain to any value up to 200.
The three transistors have high gain and excellent matching
characteristics. They are well suited to a wide variety of applications in DC through VHF systems.

Applications
•
•
•
•
•
•
•

Features
Amplifier
• Battery operation
• Minimum external parts
• Wide supply voltage range

AM-FM radios
Portable tape recorders
Intercoms
Toys and games
Walkie-talkies
Portable phonographs
Power converters

Equivalent Schematic and Connection Diagrams

,

r-------------------~--_.-O~

•

"
-INPUT

TUH/7847-1

Dual-In-Llne Package
s••

•

~

~

VOUT

V.

~

"

'''All GAIl

n

~

~

~

u

-II

Cl

.1

£1

EI

Order Number LM389N
See NS Package Number N18A

1-31

TL/HI7847-2

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

260"C

Lead Temperature (Soldering, 10 sec.)

15V

Collector to Emitter Voltage, VCEO

12V

Collector to Base Voltage, VCSO

15V

Package Dissipation (Note 1)

1.S9W

Collector to Substrate Voltage, VCIO
(Note 2)

Input Voltage

±0.4V

Collector Current, Ic

25mA

Emitter Current, IE

25mA

Storage Temperature

-65'Cto + 150"C

Operating Temperature

O"Cto +70'C

Junction Temperature

Symbol

I

Base Current, Is

150'C

Electrical Characteristics TA =
Parameter

15V

5mA

Power Dissipation (Each Transistor) TA ,;: + 70'C

150mW

25'C

I

Conditions

I

Min

I

Typ

I

Max

I

Unita

AMPLIFIER
Vs

Operating Supply Voltage

IQ

Quiescent Current

4

POUT

Output Power (Note 3)

Av

Voltage Gain

Vs = 6V, f = 1 kHz
10 p.F from Pins 4 to 12

6

Vs = 6V, VIN = OV
THD = 10%

Vs = 6V, RL = SO
Vs = 9V,RL = 160

250

325
500

23

26
46

12

V

12

mA
mW
mW

30

dB
dB

BW

Bandwidth

Vs = 6V, Pins 4 and 12 Open

250

THD

Total Harmonic Distortion

Vs = 6V, RL = 80, POUT = 125 mW,
f = 1 kHz, Pins 4 and 12 Open

0.2

PSRR

Power Supply Rejection Ratio

Vs = 6V, f = 1 kHz, CSYPASS = 10 p.F,
Pins 4 and 12 Open, Referred to Output

RIN

Input Resistance

ISlAS

Input Bias Current

Vs = 6V, Pins 5 and 16 Open

VCEO

Collector to Emitter
Breakdown Voltage

Ic = 1 mA, Is = 0

VCSO

Collector to Base
Breakdown Voltage

Ic=10p.A,IE=0

VCIO

Collector to Substrate
Breakdown Voltage

Ic = 10 p.A, IE = Is = 0

VESO

Emitter to Base
Breakdown Voltage

IE = 10 p.A,lc = 0

HFE

Static Forward Current
Transfer Ratio (Static Beta)

Ic=10p.A
Ic=1mA
Ic=10mA

hoe

Open-Circuit Output Admittance

Ic = 1 mA, VCE = 5V, f = 1.0 kHz

20

VSE

Base to Emitter Voltage

IE = 1 mA

0.7

0.85

V

IVSE1-VSE21

Base to Emitter Voltage Offset

IE = 1 mA

1

5

mV

VCESAT

Collector to Emitter
Saturation Voltage

Ic = 10 mA, Is = 1 mA

0.15

0.5

V

CES

Emitter to Base Capacitance

VES = 3V

1.5

pF

CCS

Collector to Base CapaCitance

Vcs = 3V

2

pF

CCI

Collector to Substrate
Capacitance

VCI = 3V

3.5

pF

hIe

High Frequency Current Gain

Ic = 10 mA, VCE = 5V, f = 100 MHz

30
10

kHz
3.0

%

50

dB

50

kO

250

nA

12

20

V

15

40

V

15

40

V

6.4

7.1

100

100
275
275

TRANSISTORS

1.5

7.8

V

p.mho

5.5

Note 1: For operation in ambient temperatures above 25'C, the devi09 must be derated based on a 150"C maximum junction temperature and a thermal resistance
of 66'C/W junction to ambient.
Note 2: The collector of each transistor is isolated from the substrate by an integral diode. Therefore. the collector voltage should remain posHive with respect to
pin 17 at all times.
Note 3: If Oscillation exists under some load condHions. add 2.70 and 0.05 p.F series network from pin 1 to ground.

1-32

Typical Amplifier Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output)
vs Frequency

Quiescent Supply Current
vs Supply Voltage
10

60

- -

~
~~

~

-~

'0

~

3D

>

!

::l

&

5

9

7

10

11

~
w

20

'zc"

10

'"

3D

'"

~>

Vs=6V

1.4
1.2

Ay =26dB(C•. 12 =0)

In
u

1.0

i;:!!

0.8
0.&

~

0.'
0.2

S

iii

e

e
10k

101lle

1.0

....
=
e

~

0.1

";:::f

0.&
0.5

S

1.4

"
~

0.3
I.Z

z

iii
w

\

it""Vs ·9V \

~w

LE,VEL

"~

,I

0.1
0.1

0.2

i..
~

Vs=6W ~~E~EL
3% OIST.

./

0.3

5

0

D.'

OUTPUT POWER (WArnl

"
0.5

0.8
0.1
0.1
0.8
0.5
0.4
0.3
0.2
0.1

7

8

9

10

12

11

SUPPL Y VOLTAGE (VOL TSI

9
8

Vs "6V

RL "Iu
f= 1 kHz

r--

-

~

~

J

u

.."
;;;

e

~

g....

10'

,

1.0

II

J"D%DIST.

~ .........

Z

;:::

0
0.001

5k 10k 20k

0.01
0.1
POWER OUT (WATTSI

v!.

1-.

,'2V

·~AiIMJM

~~CONTINUOUS

~~ ;....

DISSIPATION

, ,

r-,IL ~;!.v;. .Jt-1I%DIST.LEVEL
~Vs'&Y l.£~
f/[

3"DIST.
LEVEL

,,

,--+-

0.1 0.2 0.3 0.' D.5 0.& 0.1 0.8 0.8 1.0
OUTPUT POWER (WATTSI

1.0

Device Dissipation vs Output
Power-160 Load

Device Dissipation vs Output
Power-80 Load

,

J

•

FREQUENCY (Hzl

r-Vs~u/ \ \ MAXIMUM
- ~- ~....... ~~ONTINUOUS
DISSlrATION
L

.

20 50 100 200 500 lk 2k

Device Dissipation vs Output
Power-40 Load

• r--

Distortion vs Output Power

!!

o

1M

'" .!.-

10

~~u: 8:Z12s'mw I I

FREQUENCY (Hd

0.9
0.8

,

1.8
1.8

~

10

lk

lOOk

Distortion vs Frequency
2.0

'"";:::

20

100

10k

10

~

~

/.
~r'

~ ~ f-

>

100

!!

"""BI
c! !!~~-

.0

~

~

FREOUENCY (Hz)

C!.~!I!I!lo,J

50
iO

..
..'"....
~.
~

12

Voltage Gain vs Frequency
r-nrrnm.......mn.,....,.,.",...,.....,rrmml

R';,'~ ~

~

SUPPL V VOL TAGE (VOL lSI

60

10

~

~

I

Peak-to-Peak Output Voltage
Swing vs Supply Voltage

::;

50

t;

;;;

0.5

~

.~
z

;::

V.:.;.!~
D.'
0.3

f

~

w
u

0.2

~ 0.1

"

/

//b

l:rg~/ r- I~OIST.
"
LEVEL
V l~~
,.,.' _3%0IST.
LEVEL
Vs =IV
I

'

0.1 0.2 0.3 0.4 0.5 0.60.7 0.8 0.9 1.0

OUTPUT POWER (WATTSI

TUH/7847-3

1-33

II

;

:5

Typical Transistor Performance Characteristics

i..
S
..

Forward Current Transfer Ratio
vs Collector Current
500

250

400

;;
.! 200

I-

~

g;

tOO

i--"

0

~

~

~

OYNAM;s..

.... 280

l5
~

.
.
..'"-=

IUD

w

3GO

.
I

I1 )~~~I!ml~11

Ie =101•

w

~

Open Circuit Output Admittance
VB Collector Current

Saturation Voltage vs
Collector Current

0.1

8.01

Tile II -

1611

g;

....
:1

i

-;

50

u

o

I

0.01

10

M••I

i..

100

c

E

I.

0.1

COLLECTOR CURRENT (mAl

0.1

COLLECTOR CURRENT (..AI

1.1

IILI

COLLECTOR CURRENT (mAl
TLlHI7847-4

High Frequency Current Gain
vs Collector Current

Noise Current vs Frequency

Noise Voltage vs Frequency

20

II
I

IUD

la

~

:!
w

14

,.~

1O

..

!!lco

'"

~....

12

,.

:I!

1O

c

.

•

co

'"

I

FREQUENCY (Hzl

18

..
...
..

14

"..

:l

.L.

508

C~ ~

co 400

B
....

380

==
co

210

I

110

.I

°°

/

,

o

o

FREQUENCY (Hzl

g08 and Coe vs Collector
Current

7111
1 6ICI

t

".

.I

0.1 L....JL...UoWLIL.-......u.wll-......u.wu
10
100
Ik
IUk

"i

,..

!....

~
~
w

I

8lIO

VeE "'SV
'·IOOMH.

~

18

12
10

V

200

I

-

180

~

..e:=

120

~
~

~
::;

Va..
'i 10.7 MHz

...

I

-

VeE-SV ._

10

Ie - COLLECTOR CURRENT (mAl

12

~

°

1

~ 140

8

~

80

I

60
40

I

20

.!

C......

180

co

o

28

I

~

/

,/

/

,..

........

~

:/'

I

10

I

10

Ie - COLLECTOR CURRENT (mAl

10k
7k

18

12

c
:;I
c

S
~

S
I.. ..
~
"'

;0

::;

!

I

o

I. r"
14

VeE -IV
'-IMHz

/

4

1"121418

Contours of Constant NOise
Figure

g08 and Coe vs Collector
Current

."" 1'"

2

Ie - COLLECTOR CURRENT (mAl

4k
2k

700

200

lDO
12

IW 2kHz
f-1MHz

~a

""

Ik

;;:
co 4DO
I

rl

4d~=~
8d

~2.B

~4d.

l'l1)
..l(J~

'Ida

,1;;
0.1

0.3

1.0

3.0

10

Ie - COLLECTOR CURREIIT (mAl
TLlH17847-5

1-34

Application Hints
bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,...F capacitor or a short to ground depending on the dc source resistance of the driven input.

Gain Control
To make the LM389 a more versatile amplifier, two pins (4
and 12) are provided for gain control. With pins 4 and 12
open, the 1.35 kO resistor sets the gain at 20 (26 dB). If a
capacitor is put from pin 4 to 12, bypassing the 1.35 kO
resistor, the gain will go up to 200 (46 dB). If a resistor is
placed in series with the capacitor, the gain can be set to
any value from 20 to 200. A low frequency pole in the gain
response is caused by the capacitor working against the
external resistor in series with the 1500 internal resistor. If
the capacitor is eliminated and a resistor connects pin 4 to
12, then the output dc level may shift due to the additional
dc gain. Gain control can also be done by capacitively coupling a resistor (or FET) from pin 12 to ground.

Supplies and Grounds
The LM389 has excellent supply rejection and does not require a well regulated supply. However, to eliminate possible high frequency stability problems, the supply should be
decoupled to ground with a 0.1 ,...F capacitor. The high current ground of the output transistor, pin 18, is brought out
separately from small signal ground, pin 17. If the two
ground leads are returned separately to supply then the parasitic resistance in the power ground lead will not cause
stability problems. The parasitic resistance in the signal
ground can cause stability problems and it should be minimized. Care should also be taken to insure that the power
dissipation does not exceed the maximum dissipation of the
package for a given temperature. There are two ways to
mute the LM389 amplifier. Shorting pin 3 to the supply voltage, or shorting pin 12 to ground will turn the amplifier off
without affecting the input signal.

Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 1 to 12 (paralleling the internal 15 kO resistor). For 6 dB effective bass boost: R '" 15 kO, the lowest
value for good stable operation is R = 10 kO if pin 4 is
open. If pins 4 and 12 are bypassed then R as low as 2 kO
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9VIV.

Transistors
The three transistors on the LM389 are general purpose
devices that can be used the same as other small signal
transistors. As long as the currents and voltages are kept
within the absolute maximum limitations, and the collectors
are never at a negative potential with respect to pin 17,
there is no limit on the way they can be used.
For example, the emitter-base breakdown voltage of 7.W
can be used as a zener diode at currents from 1 ,...A to
5 mA. These transistors make good LED driver devices,
VSAT is only 150 mV when sinking 10 mAo
In the linear region, these transistors have been used in AM
and FM radios, tape recorders, phonographs and many other applications. Using the characteristic curves on noise
voltage and noise current, the level of the collector current
can be set to optimize noise performance for a given source
impedance. Some of the circuits that have been built are
shown in Figures 1-7. This is by no means a complete list
of applications, since that is limited only by the designers
imagination.

Input Biasing
The schematic shows that both inputs are biased to ground
with a 50 kO resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM389 Is higher than 250 kO it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kO, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input, 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
When using the LM389 with higher gains (bypassing the
1.35 kO resistor between pins 4 and 12) it is necessary to

Vs

~I.7LL(Lll

~~~14
LOCAL OSC
& MIXER

1ST
If

-(13
15

2ND
If

DETECTOR

OUTPUT AMPLIfiER 10 SPEAKER
TUH/7847-6

FIGURE 1. AM Radio

1-35

II

Application Hints (Continued)

.

...

t-------~~------_1~----~------_P~------~,~~~------~-1~.o,y

,

HE""

'"

])

...
""

...

All switches in record mode
Head characteristic 280

~H/3OOll

Ul

TUH17847-7

FIGURE 2. Tape Recorder

,,,.
5.•

-'IV

T'·'·'

TLlHI7847-8

FIGURE 3. Ceramic Phono Amplifier with Tone Controls

1·36

Application Hints (Continued)
FM
DETECTOR

OUTPUT

+IZV

.
'7",

+

T

VOL

TL/HI7847-9

FIGURE 4. FM Scanner NOise Squelch Circuit
V.

ON RATE

11-7Hd

1&

tl2W

FRED
(251-1510 Hz)

II

1= _ _
' __

O.69R1Cl

Ik

TLlHI7847 -10

FIGURE 5. Siren
+IZV

I.

Ik

+IIV

I.

Uk

"

2.111.

• Tremolo Iraq. ,;; 211" (R : 10klC
TLlHI7847-11

FIGURE 6. Voltage-Controlled Amplifier or Tremolo CIrcuit

1-37

=
:::&

Application Hints (Continued)

...I

12V

v.

NC

TL/H17847-12

FIGURE 7. Noise Generator Using Zener Diode

1-38

~National

~ Semiconductor

LM390 1 Watt Battery Operated Audio Power Amplifier
General Description
The LM390 Power Audio Amplifier is optimized for 6V, 7.5V,
9V operation into low impedance loads. The gain is internally set at 20 to keep the external part count low, but the
addition of an external resistor and capacitor between pins
2 and 6 wil increase the gain to any value up to 200. The
inputs are ground referenced while the output is automatically biased to one half the supply voltage.

•
•
•
•

Applications
• AM-FM radio amplifiers
• Portable tape player amplifiers
•
•
•
•
•
•
•

Features
• Battery operation

• 1W output power
• Minimum external parts
• Excellent supply rejection
• Ground referenced input

Self-centering output quiescent voltage
Variable voltage gain
Low distortion
Fourteen pin dual-in-line package

Intercoms
TV sound systems
Lamp drivers
Line drivers
Ultrasonic drivers
Small servo drivers
Power converters

Equivalent Schematic and Connection Diagrams

.

,

" v,

lOOT

Dual-In-Llne Package

STR..

•

BYPASS

14 Vs

I

GAIN

13
VOUT

GND

GAIN

-INPUT

-'NPUT

+INPUT

TL/H/7848-2
3,4,i,
to,11,12
GND

TLlH/7S48-1

1-39

Order Number LM390N

See NS Package Number N14A

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
10V
Package Dissipation 14-Pin DIP (Note 1)
8.3W

Input Voltage
Storage Temperature
Operating Temperature
Junction Temperature
Lead Temperature (Soldering, 10 sec.)

±0.4V
- 65'C to + 150'C
O'Cto +70'C
150'C
260'C

Electrical Characteristics TA = 25'C, (Figure 1)
Symbol

Conditions

Parameter

Min

Typ

Vs

Operating Supply Voltage

10

Quiescent Current

Vs = 6V, VIN = 0

POUT

Output Power

Vs = 6V, RL = 4n, THO = 10%

0.8

1.0

Av

Voltage Gain

Vs = 6V, f 1 kHz
10 ,...Ffrom Pin 2 to 6

23

26
46

Max

4
10

Units

9

V

20

rnA

30

dB
dB

W

BW

Bandwidth

Vs = 6V, Pins 2 and 6 Open

300

THO

Total Harmonic Distortion

Vs = 6V, RL = 4n, POUT = 500 mW
f = 1 kHz, Pins 2 and 6 Open

0.2

PSRR

Power Supply Rejection Ratio

Vs = 6V, f = 1 kHz, CBYPASS = 10 ,...F,
Pins 2 and 6 Open, Referred to Output
(Note 2)

50

dB

50

kn

250

nA

10

Input Resistance

RIN

Input Bias Current
Vs = 6V, Pins 7 and 8 Open
Note 1: Pins 3, 4, 5, 10, 11, 12 at 25'C. Above 25'C case, derate at 15'C/W junction to case. or 85'C/W junction to ambient.
Nota 2: If load and bypass capacitor are returned to Vs (F/{JUre 2), rather than ground (Figure 1), PSRR is typically 30 dB.

IBIAS

kHz
1

%

Typical Performance Characteristics
Maximum Device Dissipation
vs Ambient Temperature

10

.'"

i

;:

f

iii
is
~

"

~

J.Ll

9
8
7
&

12

'"

5

l'IIi'c/w

4 ~ C0'rjIOIL

r-

FflEE AIR

~ r-r;;;;2/~'L ~;7.JZ::;

I&°t/W

..

./

6

o 10 20 30 40 51 80 78 80 80 108
T. - AMBIENT TEMPERATURE rc)

°4

50

~

40

>

30

.

ill

ZO

~

10

t

4
2

r-

~

z

V

5
7
6
SUPPLY VOLTAGE (V)

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

60
iD

l/V

8

~
...""
iT"""'" ~g: f--

3

l/~

10

II. ~._ ~

SlAVERY7

2

V

14

IN!!.!!I~EATSINK

I I
I

16

Quiescent Supply Current vs
Supply Voltage

HIJ~~

~I
I"F

9

Peak-to-Peak Output Voltage
Swing vs Supply Voltage
RL ~"

8

""f
~

~

I...-

7

6
&

RL ·an

Voltage Gain vs Frequency
80

;7k""
~~

i7S ~ ......

50

40

W i-".: ......
... 4~ ~~4n

ZO

co

10

...c
c:
>

~

30

( I

3
2
1

I
4

5

6
7
a
SUPPLY VOLTAGE (VI

9

0
100

IIIII~

II

10
~ 8.0
" 4.0

.
.
.
..I"

Ii

CZ,8"'0"F

I~!~~J

~

I
10

100

i!

1.0
0.8

,.c

D.4

...co
1M

0.1

100.

Distortion vs Frequency

PO~T .1&OOlmW
f-1 kHz

I

"

............. AJ-ZOO

-,..

I~

;:! 0.2 boo.

10k
1l1li.
FREQUENCY (Hz)

1k
10k
FREQUENCY (Hzl

2.0

~

.

AV'Z6dS

III

No.. : 2 oz, topper filii. single...... PC hInI.

8

II

I~

I

0
8

~

O.&.F

II"

~v=~O

20 50 1l1li 200 500 1k 2k
FREQUENCY (Ht)

/

/
610

10k

ZtIk

TL/H/7B4B-5

1-40

Typical Performance Characteristics

'II!

~

6.0
f=1 kHz
10'0~"
VS=6V

J.O

~;;;

CI

u

~

1.0
0.3

il!
~

~

...
;:::

~ ~~'II~~II

2

1.2

~

:~:~~

r-+-ff~~~~~~
0.1 ,---'-W-UJJ."--'-...L.-I..u..LW
0.3 0.6 1.0
0.01
0.03 0.06 0.1

Device Dissipation vs
Output Power an Load

Device Dissipation vs
Output Power 40. Load

Distortion vs Output Power

£

(Continued)

1.0

0.8

~

0.4

..
~

II

0.8

i

;;;

V~.Jv ~

VS·7.5V
..-

V
I-I-.IL

0.8

~t
,,r' ,

r--

0.7

THb.\}

0.6

', ~rll"'-

"

0.5

0.1

0
0

OA

POWER OUTPUT IWI

o.a

1.2

1.6

2.0

'If
ITH~·TI

~

"

0.2

o

~'~ ....

VS'6V

0.3

0.2

THO'3%P

VS· 7.5V

V-" 1

0.4

VTi

I I
V~ .Jv 11

o

0.2

I I
I I
0.'

0.6

0.8

OUTPUT POWER IWI

OUTPUT POWER IWI

TL/H/7848-8

Application Hints
Gain Control
To make the LM390 a more versatile amplifier, two pins (2
and 6) are provided for gain control. With pins 2 and 6 open,
the 1.35 kn resistor sets the gain at 20 (26 dB). If a capacitor is put from pin 2 to 6, bypassing the 1.35 kn resistor, the
gain will go up to 200 (46 dB). If a resistor is placed in series
with the capacitor, the gain can be set to any value from 20
to 200. A low frequency pole in the gain response is caused
by the capaCitor working against the external resistor in series with the 1500. internal resistor. If the capacitor is eliminated and a resistor connects pin 2 to 6 then the output dc
level may shift due to the additional dc gain. Gain control
can also be done by capacitively coupling a resistor (or
FEn from pin 6 to ground, as in Figure 7.
Additional external components can be placed in parallel
with the internal feedback resistors to tailor the gain and
frequency response for individual applications. For example,
we can compensate poor speaker bass response by frequency shaping the feedback path. This is done with a series RC from pin 6 to 13 (paralleling the internal 15 kn resistor). For 6 dB effective bass boost: R "" 15 kn, the lowest
value for good stable operation is R = 10 kn if pin 2 is
open. If pins 2 and 6 are bypassed then R as low as 2 kn
can be used. This restriction is because the amplifier is only
compensated for closed-loop gains greater than 9 VIV.

bypass the unused input, preventing degradation of gain
and possible instabilities. This is done with a 0.1 ,..F capacitor or a short to ground depending on the dc source resistance on the driven input.
Bootstrapping
The base of the output transistor of the LM390 is brought
out to pin 9 for Bootstrapping. The output stage of the amplifier during positive swing is shown in Figure 3 with its
external circuitry.
R1 + R2 set the amount of base current available to the
output transistor. The maximum output current divided by
beta is the value required for the current in R1 and R2:
(R1

+ R2)

=

flo (Vs/2) - VBE

lOMAX
Good design values are VBE = 0.7V and flo = 100.
Example 0.8 watt into 40. load with Vs = 6V.

10 MAX =
(R1

+ R2) =

/?

100

Po

- - = 632 mA

RL

(!6/~~6;20.7)

= 3640.

To keep the current in R2 constant during positive swing
capacitor CB is added. As the output swings positive CB lifts
R1 and R2 above the supply, maintaining a constant voltage
across R2. To minimize the value of CB, R1 = R2. The pole
due to CB and R1 and R2 is usually set equal to the pole
due to the output coupling capaCitor and the load. This
gives:

Input Biasing
The schematic shows that both inputs are biased to ground
with a 50 kn resistor. The base current of the input transistors is about 250 nA, so the inputs are at about 12.5 mV
when left open. If the dc source resistance driving the
LM390 is higher than 250 kn it will contribute very little
additional offset (about 2.5 mV at the input, 50 mV at the
output). If the dc source resistance is less than 10 kn, then
shorting the unused input to ground will keep the offset low
(about 2.5 mV at the input 50 mV at the output). For dc
source resistances between these values we can eliminate
excess offset by putting a resistor from the unused input to
ground, equal in value to the dc source resistance. Of
course all offset problems are eliminated if the input is capacitively coupled.
When using the LM390 with higher gains (bypassing the
1.35 kn resistor between pins 2 and 6) it is necessary to

CB""4CC ",,CC

flo

25

Example: for 100 Hz pole and RL = 40.; Cc = 400,..F and
CB = 16 ,..F, if R1 is made a diode and R2 increased to give
the same current, CB can be decreased by about a factor of
4, as in Figure 4.
For reduced component count the load can replace R1. The
value of (R1 + R2) is the same, so R2 is increased. Now CB
is both the coupling and the bootstrapping capacitor (see
Figure 2).

1-41

Ir---------------------------------------------------------------~

,-,

:!I

Typical Applications
IV

BV

TUH/7848-4

TUHI784B-9

FIGURE 2. Load Returned to Supply
(Amplifier with Gain = 20)

FIGURE 1. Load Returned to Ground
(Amplifier with Gain = 20)

r----...-oVs
HI

~

14

r.

_ovs

F_. ._ . .

H2

Tl/HI7848-7

FIGURE 3

TUHI7848-B

FIGURE 4. Amplifier with Gain = 200 and Minimum Ca
IV

120

120

FIGURE 5. 2.5W Bridge Amplifier

1·42

TUHI7848-9

Typical Applications (Continued)
Vs

27
180

.
~

24

C

23

......
z

c

470,.F

I

~

+TvO

o.os"F

2.

c:::I

>

25

22
21

I

\

1

,
\..

20
II

i"--

I.

RL

17
20

2.7

\.

I

58 100 200 500 1k 2k . 5k 10k 20k

.

FREQUENCY (Hzl
TL/HI7B48-11

':"

':"
TUHI7B48-10

FIGURE 6(b). Frequency Response
with Bass Boost

FIGURE 6(a). Amplifier with Bass Boost
6Vo--1~""'---,

TALK

TALK

MASTER

II

REMOTE

TLlH/7848-12

FIGURE 7. Intercom
180

Cc
FROM......j
DETECTOR

"I

Rl
10k

~'k~~~~t-----~~
!50"1JF
In
SPEAKER

~O.',.F

'::"
TL/H/7B48-13

FIGURE 8. AM Radio Power Amplifier
Note 1: Twislsupply lead and supply ground very tightly.
Note 2: Twisl speaker lead and ground very tightly.
Nol. 3: Ferrite bead is Ferroxcube KS-001'()OI13B with 3 turns of wire.

Note 4: Rl Cl band limits input signals.
Note 5: All components must be spaced very close to IC.

1-43

~

r--------------------------------------------------------------------------------,

:5= ~ National
~ SemIconductor

LM391 Audio Power Driver
General Description

Features

The LM391 audio power driver is designed to drive external
power transistors in 10 to 100 watt power amplifier designs.
High power supply voltage operation and true high fidelity
performance distinguish this IC. The LM391 is internally protected for output faults and thermal overloads; circuitry providing output transistor protection is user programmable.

•
•
•
•
•
•
•

±50V max
0.01%
3,..V
90 dB

High Supply Voltage
Low Distortion
Low Input Noise
High Supply Rejection
Gain and Bandwidth Selectable
Dual Slope SOA Protection
Shutdown Pin

Equivalent Schematic and Connection Diagram
~--~--~----------._----------t_----------_1~--1_-o15

v+

21i1c

26k

'---+_0 a

OUTPUT SOURCE

>-....----+--010 + I LIMIT
"".i-+--o 11 +SOA

+---------+-0.

OUTPUT SENSE

~"I-+--o 12 -SOA

1+----+-0 13 -I LIMIT

...------...--------+-0 5

OUTPUTSIIK

21i1c

21i1c

L-____~~----~~----~~--------------~~~16

vTLlHI7146-1

Dual-In-Une Package
v-

+IN

v+

-IN

SHUTDOWN

COMPC

-I LIMIT

RIPPLE C
SINK

-SOA DIODE

alAS

+SOA DIODE

BIAS

+1 LIMIT
OUTPUT SENSE

SOURCE

TLlHI7146-2

Top View
Order Number LM391N-100
See NS Package Number N16A

1-44

Absolute Maximum Ratings
Shutdown Current (Pin 14)

If Military/Aerospace specified devices are required,
plesse contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
LM391N-100

Parameter

-65'Cto + 15O'C

Storage Temperature

O"Cto +70"C

Lead Temp. (Soldering, 10 sec.)

Supply Voltage less 5V

Electrical Characteristics TA =

1.39W

Operating Temperature

±50Vor + 100V

Input Voltage

1 mA

Package Dissipation (Note 1)

26O"C

25'C (The following are forV+ = 90% V+MAXandV- = 90% V-MAX.)
Conditions

Min

Quiescent Current
LM391N-100

Current in Pin 15
VIN = 0

Output Swing

Positive
Negative

Drive Current

Source (Pin 8)
Sink (Pin 5)

Typ

Max

5

6

V+ - 5
V- + 5

V+ -7
V- + 7

Noise (20 Hz-20 kHz)

Input Referred
Input Referred

Total Harmonic Distortion

f = 1 kHz
f = 20kHz

mA
mA

70

3

",V

90

dB

0.01
0.10

Intermodulation Distortion

60 Hz, 7 kHz, 4:1

Open Loop Gain

f = 1 kHz

mA
V
V

5
5

Supply Rejection

Units

1000

Input Bias Current

0.25

%
%

0.01

%

5500

VIV

0.1

1.0

!LA

5

20

mV

Input Offset Voltage
Positive Current Limit VBE

Pin 10-9

650
650

mV
mV

Negative Current Limit V BE

Pin9-13

Positive Current Limit Bias Current

Pin 10

10

100

Negative Current Limit Bias Current

Pin 13

10

100

!LA
!LA

Pin 14 Current Comments
Minimum pin 14 current required for shutdown is 0.5 mA, and must not exceed 1 mAo
Maximum pin 14 current for amplifier not shut down is 0.05 mA.
The typical shutdown switch point current is 0.2 mAo
Note 1: For operation in ambient temperatures above 25"C, the device must be derated based on a 150'C maximum Junction temperature and a thermal resistance
of 90'C/W junction to ambient

Typical Applications
If'

t

Rft

::t

r-.

CI

-

THERMAL
SWITCH,

j,..j-

R
TH

r-"D-t.h
":"

OPEN

...1!

~

"LRf2

5

HE

...AR~
,/

;;F'CC~
...A RA

"'~

C~B

-.!'

v-

RE

Il 9

"'~

RIN

.~

54

LM391

~.

CIN

~
.
~

L

+*

to

f7

"RO
iCO

":"

TUH/7146-3

FIGURE 1. LM391 with External Components--Protection Circuitry Not Shown
1-45

•

Typical Performance Characteristics
Total Harmonic Distortion vs
Frequency (RL
aO)

2111

..

100

I

81

0:

~

0.18

RL"411

0.14

V

./

80

..

!;
:: 2:~ ~ I-""
fo0

tlO

./

V

I-

D.1'
0.08

5
iii
e

70

101

Ii
52

*

...
C

."
.......
:=

'\..

61

MI0: 0
.. I:!

50

0.08

90

I
I

29

IE
Li!!

lD

•

100

'\...
lk

10k

IIOk

1M

10M

fREQUENCY (HERTZ)

20

51

Total Harmonic Distortion vs
AB Bias Current

I

DA

NEJTlV~ sJPPLY

80

60

50 100200 500 lk 2. It 10.2Ok
fREQUENCY (HERTZ)

POSITIVE SUPPLY

WITH CR

~o:

'\..

AV=2D

0.14

0.1

t ..
~
70

411 Cc' IpfWlTH
1 MIl RESISTOR
3D

L

0.12

Input Referred Power Supply
Rejection vs Frequency

I

80

J

j!: D.18

20 50 180288 580 1k 210 Ik 10k 20k
fREQUENCY (HERTZ)

CC-5pf

J

Av-201l!

a D.ZO

AV'20

0.D2

Open Loop Gain va Frequency
90

1
1

'.32
0.21

I

O.M

1
1

I

V

D••

. / RL=11l

=

OAG
0.38

l°.24

=

>40
.20
t30
SUPPLY VOLTAGE (VOLTS)

180

I
I

Av-2DD1

l8.12

./
./

I
I

0.18

1

a 120
b

1.20

I
I

! liD
1'1611
..E1411

TotalHarmonie Distortion vs
Frequency (RL
40)

=

Output Power vs Supply Voltage

"'I"

W1TH.OUTCR

1 1
1 1

I'\. I'\.

I\.

20 10 1111200 501 lk 2k It 10k 20k
CR - Cc fREIlUENCY (HERTZ)

......

l

f!20~H'

0.3

1.2~
0.1 \
0
0

""I

RL-41l
RVIIl

10 1& 20 2& 3D 3& 4D 4& &0
AI 81AS CURRENT (MILLIAMPS)

TUHI7146-4

Pin Descriptions
Pin No.

Pin Name

Comments

1
2
3
4
5
6

+ Input
-Input
Compensation
Ripple Filter
Sink Output
BIAS
BIAS
Source Output
Output Sense
+ Current Limit
+SOADiode
-SOADiode
- Current Limit
Shutdown
V+
V-

Audio input
Feedback input
Sets the dominant pole
Improves negative supply rejection
Drives output devices and is emitter of AB bias VBE multiplier
Base of VBE multiplier
Collector of VBE multiplier
Drives output devices
Biases the IC and is used in protection circuits
Base of positive side protection circuit transistor
Diode used for dual slope SOA protection
Diode used for dual slope SOA protection
Base of negative side protection circuit transistor
Shuts off amplifier when current is pulled out of pin
Positive supply
Negative supply

7
8
9

10
11
12
13
14
15
16

~

!

I
i

1-46

External Components (Figure 1)
Component

Typical Value

CIN

l,...F

Comments
Input coupling capacitor sets a low frequency pole with RIN.
1
27TRINCIN

fL =
RIN

lOOk

Sets input impedance and DC bias to input.

RI2

lOOk

Feedback resistor; for minimum offset voltage at the output this should be equal to RIN.

Rll

5.1k

Feedback resistor that works with RI2 to set the voltage gain.
Av = 1

Ct

10,...F

Cc

5pF

+~
Rll

Feedback capacitor. This reduces the gain to unity at DC for minimum offset voltage at the
output. Also sets a low frequency pole with Rll.
1
fL=--27TRllC,
Compensation capacitor. Sets gain bandwidth product and a high frequency pole.
GBW =

1
f = GBW
27T5000Ce' h
Av
Max fh for stable design :::: 500 kHz.

RA

3.9k

AB bias resistor.

RB

10k

AB bias potentiometer. Adjust to set bias current in the output stage.

CAB

O.l,...F

Bypass capacitor for bias. This improves high frequency distortion and transient response.

CR

5pF

Ripple capacitor. This improves negative supply rejection at midband and high frequencies.
CR, if used, must equal Ce.

Reb

1000

Bleed resistor. This removes stored charge in output transistors.

Ro

2,70

Output compensation resistor. This resistor and Co compensate the output stage. This value
will vary slightly for different output devices.

Co

O.l,...F

Output compensation capacitor. This works with Ro to form a zero that cancels f{3 of the
output power transistors.

RE

0.30

Emitter degeneration resistor. This resistor gives thermal stability to the output stage
quiescent current. IRC PW5 type.

RTH

39k

Shutdown resistor. Sets the amount of current pulled out of pin 14 during shutdown.

C2,C'2

1000 pF

Compensation capacitors for protection circuitry.

XL

1oo115,...H

Used to isolate capacitive loads, usually 20 turns of wire wrapped around a 100, 2W resistor.

1-47

•

~ r-----------------------------------------------------------------------------------------~

~

:5

Application Hints
To prevent thermal runaway of the AB bias current the following equation must be valid:

GENERALIZED AUDIO POWER AMP DESIGN
Givens:

Power Output

8JA

Load Impedance

8JA is the thermal resistance of the driver transistor, junction to ambient, in ·C/W.

Bandwidth
The power output and load impedance determine the power
supply requirements. Output signal swing and current are
found from:
VOpeak = ~2 RL Po

IOpeak =

~2PO
~

RE is the emitter degeneration resistance in ohms.
Pmin is that of the output transistor.

(1)

VCEOMAX is the highest possible value of one supply from
equation (3).

(2)

K is the temperature coefficient of the driver base-emitter
voltage, typically 2 mVl·C.
Often the value of RE is to be determined and equation (5)
is rearranged to be:

Add 5 volts to the peak output swing (VOp) for transistor
voltage to get the supplies, i.e., ± (Vop + 5V) at a current
of Ipeak' The regulation of the supply determines the unloaded voltage, usually about 15% higher. Supply voltage will
also rise 10% during high line conditions.

+ 5)(1 + regulation)(1.1)

RE ~ 8JA (VCEOMAX) K
(6)
PMIN + 1
The maximum average power dissipation in each output
transistor is:

(3)

J5DMAX = 0.4 POMAX
The power dissipation in the driver transistor is:

The input sensitivity and output power specs determine the
required gain.
Ay

(5)

where:

Input Impedance

max supplies ::::: ±(VOpeak

s: RE (.8MIN + 1)
VCEOMAX(K)

Input Sensitivity

~ ~Po RL

= VORMS
(4)
VIN
VINRMS
Normally the gain is set between 20 and 200; for a 25 watt,
8 ohm amplifier this results in a sensitivity of 710 mV and 71
mV, respectively. The higher the gain, the higher the THD,
as can be seen from the characteristics curves. Higher gain
also results in more hum and noise at the output.

J5DRIYER(MAX) =

(7)

J5DMAX

(8)
... MIN
Heat sink requirements are found using the following formulas:
-Q--

8 s: TJMAX - TAMAX
JA Po
8SA

The desired input impedance is set by RIN. Very high values
can cause board layout problems and DC offsets at the output. The bandwidth requirements determine the size of Ct
and Cc as indicated in the external component listing.

s: 8JA -

8JC - 8cs

(9)

(10)

where:
TjMAX is the maximum transistor junction temperature.
T AMAX is the maximum ambient temperature.

The output transistors and drivers must have a breakdown
voltage greater than the voltage determined by equation (3).
The current gain of the drive and output device must be high
enough to supply IOpeak with 5 mA of drive from the LM391.
The power transistors must be able to dissipate approximately 40% of the maximum output power; the drivers must
dissipate this amount divided by the current gain of the outputs. See the output transistor selection guide, Table A.

8JA is thermal resistance junction to ambient.
eSA is thermal resistance sink to ambient.
8JC is thermal resistance junction to case.
8cs is thermal resistance case to sink, typically 1·C/W for
most mountings.

1-48

Application Hints (Continued)
PROTECTION CIRCUITRY
The protection circuits of the LM391 are very flexible and
should be tailored to the output transistor's safe operating
area. The protection V-I characteristics, circuitry, and resistor formulas are described below. The diodes from the output to each supply prevent the output voltage from exceeding the supplies and harming the output transistors. The output will do this if the protection circuitry is activated while
driving an inductive load.

resistor is set to limit the current to less than 1 mA (the
absolute maximum). This resistor with the capacitor gives a
time constant of RC. The turn-ON delay is approximately 2
time constants.
Example:
Amplifier with maximum supply of 30V, like the 20W, 80
example in the data sheet, requiring a delay of 1 second.
Time delay = 2 RC
MaxV+
R=-1 mA

TURN-ON DELAY
It is often desirable to delay the turn-ON of the power amplifier. This is easily implemented by putting a resistor in series
with a capacitor from pin 14 to ground. The value of the

So:
R = 30k. Solving for C gives 16.7 /LF. Use C = 20 /LF with
a 30V rating.

Protection Circuitry with External Components

Protection Characteristics

v+_.....- ...~.........,

RE

OUTPUT

RE
VeE
TLlHI7146-6

II

Cz IS FOR STABILITY ~ llIOGpF

y--......- .....- ......TL/H17146-5

Protection Circuit ReSistor Formulas (Va = V+)
Type of Protection

RE.R'

R1. R'1

R2. R'2

R3. R '3

Current Limit

RE =!.
IL

Not Required

Short

Not Required

Single Slope SOA
Protection

RE =!.
IL

R1 =R2

(VM - -

1 kO

Not Required

Dual Slope SOA
Protection
(VB = V+)

RE =!.
IL

R1 =R2

(VM - 

Note:  is the current limit VBE voltage. 650 mV. Assumptions: V'
transistors.

--

> > . YM > > . V' is the load supply voltage. VM is the maximum rated VeE of the output

1-49

,..
~

...:E

,-------------------------------------------------------------------------------------,
OSCILLATIONS" GROUNDING
Most power amplifiers work the first time they are turned on.
They also tend to oscillate and have excess THO. Most oscillation problems are due to inadequate supply bypassing
and/or ground loops. A 10 JoLF, 50V electrolytic on each
power supply will stop supply-related oscillations. However,
if the signal ground is used for these bypass caps the THO
is usually excessive. The signal ground must return to the
power supply alone, as must the output load ground. All
other grounds--bypass, output R-C, protection, etc., can tie
together and then return to supply. This ground is called
high frequency ground. On the 40W amplifier schematic all
the groun~s are labeled.
Capacitive loads can cause instabilities, so they are isolated
from the amplifier with an inductor and resistor in the output
lead.

Application Hints (Continued)
TRANSIENT INTERMODULATION DISTORTION
There has been a lot of interest in recent years about transient intermodulation distortion. Matti Otala of University of
Oulu, Oulu, Finland has published several papers on the
subject. The results of these investigations show that the
open loop pole of the power amplifier should be above 20
kHz.
To do this with the LM391 is easy. Put a 1 MO resistor from
pin 3 to the output and the open loop gain is reduced to
about 46 dB. Now the open loop pole is at 30 kHz. The
current in this resistor causes an offset in the input stage
that can be cancelled with a resistor from pin 4 to ground.
The resistor from pin 4 to ground should be 910 kO rather
than 1 MO to insure that the shutdown circuitry will operate
correctly. The slight difference in resistors results in about
15 mV of offset. The 40W, 80 amplifier schematic shows
the hookup of these two resistors.

AB BIAS CURRENT
To reduce distortion in the output stage, all the transistors
are biased ON slightly. This results in class AB operation
and reduces the crossover (notch) distortion of the class B
stage to a low level, (see performance curve, THO vs AB
bias). The potentiometer, Re, from pins 6-7 is adjusted to
give aoout 25 mA of current in the output stage. This current
is usually monitored at the supply or by measuring the voltage across RE.

BRIDGE AMPLIFIER
A switch can be added to convert a stereo amplifer to a
single bridge amplifer. The diagram below shows where the
switch and one resistor are added. When operating in the
bridge mode the output load is connected between the two
outputs, the input is VIN #1, and VIN #2 is disconnected.

Typical Applications (Continued)
Bridge Circuit Diagram
--.5.1k

5.a

lOOk

lOOk

I
TLlHI7146-7

Output Transistors Selection Guide
Table A.
Power
Output

Driver Transistor

Output Transistor

PNP

NPN

PNP

NPN

20W@80
30W@40

MJE711
MJE171
043C8

MJE721
MJE181
042C8

TIP42A
2N6490

TIP41A
2N6487

40W@80
60W@40

MJE712
MJE172
043C11

MJE722
MJE182
042C11

2N5882

2N5880

1-50

Application Hints (Continued)
A 20W, SO; 30W, 40 AMPLIFIER
Givens:
Power Output

Solving for Ct:

1
7.8,...F;use10,...F
2'IT f1 L
The recommended value for Cc is 5 pF for gains of 20 or
larger. This gives a gain-bandwidth product of 6.4 MHz and
a resulting bandwidth of 320 kHz, better than required.
The breakdown voltage requirement is set by the maximum
supply; we need a minimum of 58V and will use 60V. We
must now select a 60V power transistor with reasonable
beta at IOpeak, 3.87A. The TIP42, TIP41 complementary pair
are 60V, 60W transistors with a minimum beta of 30 at 4A.
The driver transistor must supply the base drive given 5 mA
drive from the LM391. The MJE711, MJE721 complementary driver transistors are 60V devices with a minimum beta of
40 at 200 mAo The driver transistors should be much faster
(higher fT) than the output transistors to insure that the R-C
on the output will prevent instability.
To find the heat sink required for each output transistor we
use equations (7), (9), and (10):
Po = 0.4 (30) = 12W
(7)
150"C - 55°C
(JJA:;;;
12
= 7.9"C/WforTAMAX = 55°C (9)

Ct;;, - R
f =

20W into 80
30W into 40

Input Sensitivity
Input Impedance
Bandwidth

1VMax
100k
20 Hz-20 kHz ± 0.25 dB

Equations (1) and (2) give:
20W/80
Vop = 17.9V
lOp = 2.24A
30W/40
VOP = 15.5V
lop = 3.87A
Therefore the supply required is:
± 23V @ 2.24A, reducing to ...
±21V @ 3.87A
With 15% regulation and high line we get ± 29V from equation (3).
Sensitivity and equation (4) set minimum gain:
~20 x 8
Av ;;, - 1 - = 12.65

We will use a gain of 20 with resulting sensitivity of 632 mY.
Letting RIN equal100k gives the required input impedance.
For low DC offsets at the output we let Rf2 = 100k. SOlving
for Rf1 gives:

(JSA :;;; 7.9 - 2.1 - 1.0 = 4.8°C/W

(10)

If both transistors are mounted on one heat sink the thermal
resistance should be halved to 2.4°C/W.
The maximum average power dissipation in each driver is
found using equation (8):
12
PoRIVER(MAX) = 30 = 400 mW

Rf2 = 100k
100k
Rh = 20 _ 1 = 5.26k; use 5.1k
The bandwidth requirement must be stated as a pole, i.e.,
the 3 dB frequency. Five times away from a pole gives 0.17
dB down, which is better than the required 0.25 dB. Therefore:

Using equation (9):
155 - 55

(JJA :;;; ~ = 23rC/W

20
fL="5=4HZ
fh = 20k x 5 = 100kHz

1-51

•

~

~

~

...J

r------------------------------------------------------------------------------------------,
Application Hints (Continued)
Since the free air thermal resistance of the MJE711,
MJE721 is 100"C/W, no heat sink is required. Using this
information and equation (6) we can find the minimum value
of RE required to prevent thermal runaway.
100 (30)(0.002) R
E~
30,+ 1
- 0.190

The data points from the curve are:
VM = 60V, VB = 23V, IL = 3A, I~ = 7A
Using ·the dual slope protection formulas:
0.65
RE = -3- = 0.220

(6)

R2 = lk

We must now use the SOA data on the TIP42, TIP41 transistors to set up the protection circuit. Below is the SOA
curve with the 40 and BO load lines. Also shown are the
desirEid protection lines. Note the value of VB is equal to the
supply voltage, so we ,use the formulas in the table.

60 - 0.65)
RI = lk (
0.65
:::: 91k
,
23
)
(
Rs = 1k 7(0.22) _ 0.65 - 1 :::: 24k
Note that an RE of 0.220 Satisfies equation (6). The final
schematic of this amplifier is below. If the output is shorted
the current will be 1.BA and VeE is 23V. Since the input is
AC, the average power is:

D_C. SOA ofT1P42, TIP41
Translstora
8~~---r--~~._~--,

short f5D = 1f2(l.B) (23) :::: 21 W
This power is greater than was used in the heat sink calculations, so the transistors will overheat for long-duration
shorts unless a larger heat sink is used.

DL-~

D

____

10

~~~~~~~

20

VeE (VOLTS)
TL/H17146-8

Typical Applications (Continued)
2OW-SO, 30W-40 Amplifier with 1 Second Turn-oN Delay
V+--t---------------~~~._------~--_.~

I

9U

5.1k

-21 V TO -29V

V-~~--------6_----~~----~--~...J
Tl/HI7148-9

• Additional protection for LM391 N; Schottky diodes and R ..

1-52

loon.

r-----------------------------------------------------------------------------, r
!Ii:
Application Hints (Continued)
~
....
Since a heat sink is required on the driver, we should invesA 40W/80, 60W/40 AMPLIFIER
tigate the output stage thermal stability at the same time to
optimize the design. If we find a value of RE that is good for
the protection circuitry, we can then use equation (5) to find
the heat sink required for the drivers.
The SOA characteristics of the 2N5882, 2N5880 transistors
are shown in the following curve along with a desired protection line.

Given:
Power Output

40W/80
60W/40
1VMax
100k
20 Hz-20 kHz ± 0.25 dB

Input Sensitivity
Input Impedance
Bandwidth
Equations (1) and (2) give:

to

40W/80
VOPeak = 25.3V
IOPeak = 3.16A
60W/40
VOPeak = 21.9V
IOPeak = 5.48A
Therefore the supply required is:
±30.3V@3.16A,reducingto ...
±26.9V @ 5.48A

SOA 2N5882, 2N5880

•\
~

\
~

'\

With 15% regulation and high line we get ±38.3V using
equation (3).
The minimum gain from equation (4) is:

~

.'\:" ...-

'" ~.

t

The input impedance and bandwidth are the same as the 20
watt amplifier so the components are the same.

,.....

~.

o
o U H H

RIN = 100k
Cc = 5pF
Rft = 5.1k
Rf2 = lOOk
Ct = 10,..F
The maximum supplies dictate using 80V devices. The
2N5882, 2N5880 pair are 80V, 160W transistors with a minimum beta of 40 at 2A and 20 at 6A. This corresponds to a
minimum beta of 22.5 at 5.5A (IOpeak>. The MJE712,
MJE722 driver pair ara 80V transistors with a minimum beta
of 50 at 250 rnA. This output combination guarantees IOpeak
with 5 rnA from the LM391.

40 LOAD
f-IOLOAO

~
~I\.
~ !2"HOTECTION
~~

I"< \

Av;;' 18
We select a gain of 20; resulting sensitivity is 900 mV.

SOA

----

~

\

~

~
H

~

n H

VCE (VOLTS'
TUHI7146-10

The desired data points are:
VM = 80V
Va = 47V
IL = 3A
I~ = 11A
Since the break voltage is not equal to the supply, we will
use two resistors to replace R3 and move Va.
Circuit Used

v,

Output transistor heat sink requirements are found using
equations (7), (9), and (10):
= 0.4 (60) = 24W
(7)

Po

6JA

s:

200 - 55
-2-46SA

= 6.O"C/WforTAMAX = 55"C

s: 6.0 -

1.1 - 1.0 = 3.9"C/W

HE

(9)
(10)

For both output transistors on one heat sink the thermal
resistance should be 1.9"C/W.
Now using equation (8) we find the power dissipation in the
driver:
_
24
(8)
PDRIVER = 20 = 1.2W
6JA

150 - 55

s: -1-.2- =

79"C/W

TUHI7146-11

Thevenin Equivalent

(9)

Where: RTH = R~

HE

II R~

VTH=V-[~]
R~ + R~

TL/HI7146-12

1-53

~

~

::s

r------------------------------------------------------------------------------------------,
Application Hints (Continued)
The easiest way to solve these equations is to iterate with
standard values. If we guess R~ = 62k, then R~ = 47.12k;
use 47k. The Thevenin impedance comes out 26.7k, which
is close enough to 25.55k.
Now we will use equation (5) to determine the heat sinking
requirements of the drivers to insure thermal stability:

The formulas for RE, RI , and R2 do not change:
0.65
RE = SA = 0.220
RI = 1k 80 - 0.65 = 120k
0.65
The formula for R3 now gives RTH when the V+ in the formula becomes VB.
RTH = R2

kR~B_

8
JA

8SA';;; 57 - 6 - 1 = 50'C/W
(10)
This is the required heat sink for each driver. For low TIM
we add the 1 MO resistor from pin 3 to the output and a
910k resistor from pin 4 to ground. The complete schematic
is shown below.
If the output is shorted, the transistor voltage is about 28V
and the current is 5A. Therefore the average power is:
short j5[) = %(28) 5 = 70W

= 1k [11 (0.2;;- 0.65 - 1] = 25.55k

VTH is the additional voltage added to the supply voltage to
get VB.
VTH = -(VB - V+) = -(47 - 30) = -17V
Now we must find R~ and R~ using the Thevenin formulas.
Putting VTH, V-, and RTH into the appropriate formulas reduces to:
and

(5)

This value is lower than we got with equation (9), so we will
use it in equation (10):

 - 1]

R~ = 0.76 R~

,;;; 0.22 (20 + 1) ::: 57"C/W
40 (0.002)

25.55k = R~

This is much larger than the power used to calculate the
heat sinks and the output transistors will overheat if the output is shorted too long.

II R~

Typical Applications (Continued)
40w·ao, 6OW·40 Amplifier
27VT03tV
41k

T1D~F

12k

120~

-.

680
114003

S.lk

SHUTDOWN

.10
'High Frequency Ground
-27VTO-3tV

"Input Ground
•• "Speaker Ground

TUH/7146-13

Note: All Grounds Should be Tied Togelher
Only al Power Supply Ground.

t Additional protection for LM391 N; Schottky diodes and R '" 1000.

1-54

~National

~ Semiconductor

LM831 Low Voltage Audio Power Amplifier
General Description

Features

The LMB31 is a dual audio power amplifier optimized for
very low voltage operation. The LMB31 has two independent amplifiers, giving stereo or higher power bridge (BTL)
operation from two- or three-cell power supplies.
The LMB31 uses a patented compensation technique to reduce high-frequency radiation for optimum performance in
AM radio applications. This compensation also results in
lower distortion and less wide-band noise.
The input is direct-coupled to the LMB31, eliminating the
usual coupling capacitor. Voltage gain is adjustable with a
single resistor.

•
•
•
•
•

Low voltage operation, 1.BV to 6.0V
High power, 440 mW, BO, BTL, 3V
Low AM radiation
Low noise
LowTHD

Applications
•
•
•
•

Portable tape recorders
Portable radios
Headphone stereo
Portable speakers

Typical Application
Dual Amplifier with Minimum Parts

LM831

1&kQ
16kQ

R

Av
2

+IN
3

-IN

10k ~---------'

TL/H/6754-1
AV~46 dB.BW~250

POUT

~

Hz to 35 kHz

220 mW/Ch.RL

1-55

~

40

Absolute Maximum Ratings
1.3W (M Package)
1.4W (N Package)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Power Dissipation (Note 1), PD
Operating Temperature (Note 1), Topr

Supply Voltage, Vs

Storage Temperature, Tslg

7.5V
±0.4V

Input Voltage, VIN

+ 85'C
+ 150'C
+ 150'C
+ 260'C

- 40'C to
- 65'C to

Junction Temperature, Tj
Lead Temp. (Soldering, 10 sec.), T l

Electrical Characteristics
Unless otherwise specified, TA = 25'C, Vs = 3V, f = 1 kHz, test circuit is dual or BTL amplifier with minimum parts.
Symbol

Parameter

Conditions

Vs

Operating Voltage

10

Supply Current

VIN = 0, Dual Mode
VIN = 0, BTL Mode

Vos

Output DC Offset

VIN = 0, BTL Mode

RIN

Input Resistance

Av

Voltage Gain

Typ

Tested Limit

Unit (Limit)

3
3

1.8
6

V(Min)
V(Max)

5
6

10
15

mA(Max)
mA(Max)

VIN = 2.25 mVrms , f = 1 kHz,
Dual Mode

+ 200 mVrms @ f

= 1 kHz

10

50

mV(Max)

25

15
35

k(Min)
k(Max)

46

44
48

dB (Min)
dB (Max)

PSRR

Supply Rejection

Vs = 3V

46

30

dB (Min)

POD

Power Out

Vs = 3V, Rl = 40,
10% THO, Dual Mode

220

150

mW(Min)

PODl

Power Out Low, Vs

Vs = 1.8V, Rl = 40,
10% THO, Dual Mode

45

10

mW(Min)

POB

Power Out

Vs = 3V, Rl = 80,
10% THO, BTL Mode

440

300

mW(Min)

POBl

Power Out Low, Vs

Vs = 1.8V, Rl = 80,
10% THO. BTL Mode

90

20

mW(Min)

Sep

Channel Separation

Referenced to Vo = 200 mVrms

52

40

dB (Min)

Ie

Input Bias Current

1

2

",A (Max)

EnO

Output Noise

Wide Band (250 - 35 kHz)

250

500

",V (Max)

THO

Distortion

Vs = 3V, Po = 50 mW,
f = 1 kHz, Dual

0.25

1

% (Max)

Note 1: For operation in ambient temperatures above 25°C. the device must be derated based on a 1500C maximum junction temperature and a thennal resistance
of 98'C/W iunctlon to ambient lor the M package or 9!Y'C/W junction to ambient lor the N package.

Connection Diagram
Dual-In-Line Package

8TLR

Ay +INPUT
-INPUT

'-'

..!.
2

-

-

2. ...,

~ Av

13

~tt

BYPASS

15

r- ~

4

..! ~
POWER GROUND ...!
SIGNAL GROUNO .!.
OUTPUT ..!. rBOOTSTRAP

~

.Eo

+INPUT
-INPUT
BOOTSTRAP

11
POWER GROUND

.!!!.
..!.

OUTPUT
POWER SUPPLY
TL/H/6754-2

Top View
Order Number LM831M or N
See NS Package Number M16B or N16E

I
1-56

Typical Performance Characteristics
Supply Current vs Supply Voltage

PSRR vs Supply Voltage
80

10
NO SIGNAL

70
60

~L:1:.

:r

r

2 kHz,S kHz

50

_if'

1 kHz

I-if'

400Hz

:-1/'
20

1011Hz

~

DUAL MODE

I"""

'"

40
30

DUAL MODE

10

RAV=O, CBW=O
VSWINB s 200mVRMS

I-'

o

o

0.5

1

1.5

2 2.5 3 3.5 4
SUPPLY VOLTAGE IV)

4.5

5

5.5

200Hz

6

1.5

Supply Current vs Temperature

2.5

3.5
4
4.5
SUPPLY VOIIADE (V)

5.5

PSRR vs Supply Voltage
80
70

BTL M~OE

~

""

:--

DUAL JDDE

.....

60

...... ...

~

:--

r

r-.. "

~

50
~

40

-

-:;; I!~ ::".,..,

30

VCc s3V

DUAL MODE

10

-50

-25

25
50
TEMPERATURE

100

75

125

1.5

2.5
2.25

1.25

~

V
V

1.5

1/

V

v

70

1 kHz

V

~
iii

Ii

i

o

05

1 1.5

2

50
1110kHZ
40

AOOHZ

30
20

CHr Cj.B

2.5 3 3.5 4
SUPPLY VOLTAGE

DulL MODE
CH·A TO CH·B
Vour=20~ mV

10

0.25

o

5.5

60

J
~.

0.5

3.5
4
4.5
SUPPLY VOIIAGE IV)

80

V
1/

0.75

2.5

Separation vs Supply Voltage

2.75

"
li!

I

F-l kHz

DC Output vs Supply Voltage
3

1.75

4OOC

VSMN. = 200mVRMS

o

E

QAIN-34 dB
IRAV-24OO, caw-no pF)

Tr-

20

~NOStAL

GAIN=46 dB
(RAV=OO. Caw-O pFI

4.5

5

5.5

o

6

1.5

2.5

3.5
4
'.5
SUPPLY VOLTAGE IV)

5.5
TLlH/6754-4

1-57

.- r---------------------------------------------------------------------------------,
CO)

CD

~

Typical Performance Characteristics (Continued)
Power Output va Supply Voltage

Separation va Frequency

: :::::11:11111::111:11
:
UJllt.

- -

u

I 11111

BTL.

,

50 H-+tH#-++tll,w_2401l.C.. _270PFI - -

!
i!i
i

!

50

~~Ull~~~~~+=~;t~~~~~

V

=:O~.~..-. pfl

=

!

-..

40 ~it~~-r~~~-r;"tffi~~
30

//

i.

0.1

I

0.05

co

HjlffH#-+-H-!+IfIH--H-H~fI---1
::~3V. ~~'A TO CH'B-!+IfIH--H-H~fI---1

10

/

0.2

20

50 100

200 500 lK 2K
FREQUENCY tHzI

5K

, .,/
"

DUAL.RL-411

......

=

..""".

~RL-Jo- -

~

I

Jl

fl

0.02

I

VOUT-IUD mV

OL..J..J...U..LJ.I---I-I..J....LLLW..--1.....J...LJ.U.I.LL.....J

-

'.lkHz
THD-l0%

0.01

10K 20K

1.5

2.533.544.1
SUPPlY VOLTAGE tVI

5.5

Power OUtput va Temperature

Gain va Frequency
10

6G~~mr-r~Mmr-~Tr

75rttH~-+-HK#m-++++
rort~~~++~~++~

15 r++H~-+-H~m--r+++

6G r++H~-+-H~m--r+++

!

i

55 r++H~-+-+iGA'N_4I dB
-Oll. Cew-O~PFI _

50

40

35
30

i

JR••

Ioo-~IIII

45

I IIII

=F'..rHifII

~

-IH-~HII

ru~~'~~I~
111I!:11I~1~1i"t1++HI11'"1~lM
GAIN-3UB' ""

I

I-

25 1-h9f~~-+tR•• -2401l. Caw-2ro pFI

!:

~

0.1

U
0.1

-Il-+ttI1lW

0.01

Vet-3V
DUAL MDOE-+-t+tItIlt-+t-Hiffilt-HtHtIII

0.02

,-an

mM OE

10
20

50 100 200

Yt:c-3V.

THD-fO%

O ..............WI--'-...u..........L.-..L..L..L.UWL-L...u.oWIII

Ul
-10

500 lK 2K 5K lDK 20K 50K lOOK
FREOUEHCY tHzI

I

-21

75
25
10
TEMPERATURE t·CI

101

121

500

1II1II

Bandwidth va BW Capacitance
50

,

40

"'

"'

10
DUALMOOE
Vee-IV. RL-40

8AlNj4l., I

o
lD
FREOUEHCV tHzI

20

10

100

20D

8W CAPACITOR tpFI

TUH/6754-5

1-58

Typical Performance Characteristics (Continued)
Dual Mode, RL = 4n Distortion vs Frequency

Dual Mode, RL

!z

.-to""

0.2

is

~

GAIN-4& dB
(Ro,-OD. Cow-O pFI

0.5

52

:;;
1Ji

I

J

~:~::::U~~ Cow ~ 270 pFI ~

0.1

1111

0.2

DUAL MODE. RL - 40
Vee -1.8 TO 6V
PoUT-50 mW ICONST.1

0.01
20

50 100

200

500 lK
FREQUENCY (HzI

ZK

5K 10K ZOK

ZO

Distortion vs Power Output (Note 2)

~

~

0.5

~
:;;

~

~ 0.2

~

0.1

=

1 kHz

0.1

DUAL MODE

0.2

I T'"~

0.2

S!

0.1

iiiis

O.OS

i

.••';'

.~

0.5

ieii

;;..-

O.S

0.01
0.001 0.002 0.005 0.01 0.02 O.OS 0.1
POWER OUTPUT (WATTI

1

~l

l!t:·)O~

0.005

emS'
,4V

::
~

/-

0.5
0.2

e-

I !!
:!l
I
0.1

;;;

O.OS

0.02
0.01

O.OOS

:D~ ~L

'RL~~I~R\;~1IrHZ:

0.001
0.001 0.0020.00S 0.01 0.02 0.05 0.1 0.2 O.S 1
POWER OUTPUT (WATTI

0.002
2

O.S

1

1111
tHii~3%.

0.01

0.002

0.2

Power Dissipation vs Power Output

ill 0.02

~

Vcc=3V, Rl=80

C,w-Ro,-O,",

Power Dissipation vs Power Output

~

10kHz

0.2

0.02

0.01
0.001 0.002 0.005 0.01 0.02 O.OS 0.1
POWER OUTPUT IWATTI

z

5K 10K

0.05

Vcc-3V, RL=40

-CjWjRj'itllll

i:

500 lK 2K
FREQUENCY IHzI

0.5

DUAL MODE

0.02

100 200

10

io- 10 kHz

0.05

50

Distortion vs Power Output (Note 2)

10

is

.§

P~I=

DUAL MODE. RL -80
Vee-l.B TO 6V
PoUT=5M~ (CO~STil

0.02

0.01

1

.JA"
I

GAiN:':U dB
(Ro, = 2400. Caw-270

0.05

0.02

~

an Distortion vs Frequency

GAIN-46 dB
(R",,-OO, CIW=O pFI

0.5

0.1

0.05

~
;::

=

10

10

•

.Vlto-lo'!,
V-

~ ~;~~~~~:~I1lI:,.n,

0.001
0.0010.002 O.OOS 0.01 0.02 0.05 0.1 0.2 O.S
POWER OUTPUT IWATTI

S

e-·

',:.~.'

1

TLlH/6754-6

1·59

II

Typical Performance Characteristics (Continued)
Device Dissipation vs Ambient Telllperature

BTL Mode, RL = SO Distortion vs Frequency
10

U

..

;; 0.5

~

-

GAIN 46 dB

~

1.6

i
if

i

~ 0.2

I

BAIN-a. dB
(R" - 24on. Caw - 270 PI') ~

0.05

50

100 200
500 lK 2K
FREQUENCY (Hzl

5K

10K

O.B

o

Distortion vs Power Output (Note 2)

,

o

10

2D

30 40 50 60 70 BO
AMBIENT TEMPERATURE ('CI

90

100

Supply Current vs Power Output
100D

-

500
2DO

~~

l

!
~

0.5

~~

......

o.B

201(

10

!z

"",

0.2

~Uli~OIl"lf (Co~STjl
20

FREE AIR
9O'CIW

0.4

BTL MODE, RL. Bn
Vcc=I.B TO 6V

0.02

~

1.2

5!

(RAV·on, CBW-O pFI

0.1

1.4

z

...

1 kHz

0.2

~

..=
II:

0.1

~

100

50
2D

10

0.05

'"

rBTL MODE
0.02

Vee-3V, RL=80
CBW-=RAV=O

0.01
0.001 0.002 0.005 0.01 0.02 0.05 0.1
POWER OUTPUT (WATTI

0.2

0.5

1

1

f~?rl"

0.0010.0020.0050.010.020.050.1 0.2 0.5 1
POWER OUTPUT (WATTI

2

5 10

Power Dissipation vs Power Output
2

v..lJ
Vcc-5Y

0.5

~

~

",

z

5!

1.00"::

0.2

if

~

0.1

~

0.05

iii'

~

~'"

Vcc-4¥

I
THD!3~

Vcc-3Y

~".

Vee-2V

1HO':'10%

0.02

BTL MODE
RL-an, 1,;,11,~HZ
0.01
0.0010.0020.0050.010.02 0.05 0.1 0.2 0.5
POWER OUTPUT (WATTI

Note 2: 1 kHz curve is measured with 400 Hz-30 kHz
1

Fi~er.

2
TLlH/6754-7

1-60

Typical Applications
BTL Amplifier with Minimum Parts

80

Av

+IN

Z

3

+

VIN],

10"~

lOl~
TL/H/6754-B

AV

= 52 dB, BW = 250 Hz to 25 kHz
POUT

= 440 mW, RL = 81l

BTL Amplifier for Hi-Fi Quality

•
330 pF

TLlH/6754-9

AV

= 40 dB, BW = 20 Hzto20 kHz
POUT = 440 mW, RL = 81l
(Dynamic Range Over 80 dB)

1-61

..-

~

Typical Applications (Continued)
Dual Amplifier for HI-Fi Quality
0.33,.,

~

&GOpf

+n
- .~

r¥

AV
•

+IN
3

2400

~'J.

22~

J-----'

10

TL/H/6754-10

= 34 dB, BW = 50 Hz 10 20 kHz
POUT = 220 mW ICh, RL = 40

Av

(Dynamic Range Over 80 dB)

Low-Cost Power Amplifier (No Bootstrap)
0.33,.1'

,P:

~':i
10k

I

'12Ok

+1

+

10fX

'77,h

,.

15

BYP Av

"

+IN

13
-IN

'-LM831

"

asp

1&OJ'F

3.

11~

GND

+

Vo

~~

9

...

47"d~

~

*120k

r-R

1f]+

1

A,

•

+IN

-IN

3

4

FP'
ps~
5

8ND

Vo

In Jh •

+

;1;0.33,.1'

~.

10k
TUH/6754-11

POUT

= 150 mW/Ch, BW = 300 Hz to 35 kHz
BTL Mode is also possible

'For 3-ce1l applications, 1he 120k resistor should be changed to 20K.

1-62

r-----------------------------------------------------------~~

LM831 Circuit Description Refer to the external component diagram and equivalent schematic.
The power supply is applied to Pin 9 and is filtered by resistor R1 and capacitor CSY on Pin 16. This filtered voltage at
Pin 16 is used to bias all of the LM831 circuits except the
power output stage. Resistor Ro generates a biasing current
that sets the output DC voltage for optimum output power
for any given supply voltage.

co
Co)

....

The capacitor CNF on Pin 2 provides unity DC gain for maximum DC accuracy.
02 provides voltage gain and the rest of the devices buffer
the output load from 02'S collector.
Bootstrapping of Pin 5 by CBS allows maximum output
swing and improved supply rejection.

Feedback is provided to the input transistor 01 emitter by
R6 and R7.

R5 is provided for bridge (BTL) operation.

External Component Diagram

¥t.~~"'~'-(GRO-U-N-DFO_R_B_TL...
I _ _- ,

e"

~F~~

18
15
BYP Av

14
+IN

13
-IN

LMB31

1m

¥t.

"'J--------'
TL/H/6754-12

1-63

II

LM831

....

I:

LM831 Equivalent Schematic

CD

w
.....

o

~.

C

::;:

12

0,

~

BOOTSTRAP (AI

BOOTSTRAP (BI
'"

"

"

""

R2 >5011

5011

BYPASS

¥SUPPLY

35011

160

••

n

05

(I)

~.

l.
o

~

:s

i'"

1
~

~

16k

OUTPUT (B)

1006

r

1

16k

I~

~511

15

131

R6

R7

I

r:=

~

I

'OU~:T(A)

4

-INPUT (B) -INPUT (AI

141 3
+INPUT(BI +INPUT(AI'RB
24k

11
POWER GROUND (B)

24k

Q1

.'_R9_ _-I

23k

6

SIGNAL GROUND

POWER GROUND (A)
TUH/6754-13

r!!I:

External Components (Refer to External Component Diagram)
Component

CD

Min

Max

Co

Required to stabilize output stage.

Comments

0.33,...F

1,...F

Cc

Output coupling capacitors for Dual Mode. Sets a low-frequency pole in
the frequency response.
1
fL=--21TCcRL

100,...F

10,000,...F

Cas

Bootstrap capacitors. Sets a low-frequency pole in the power BW.
Recommended value is
C _
1
as - 10-21T-fL-RL

22,...For
(short Pins
4& 12t09)

470,...F

Cs

Supply bypass. Larger values improve low-battery performance by
reducing supply ripple.

47,...F

10,000,...F

Cay

Filters the supply for improved low-voltage operation. Also sets
turn-on delay.

47,...F

470,...F

CNF

Sets a low-frequency response. Also affects turn-on delay.
1
fL =
21T-CNF-(RAV + 80)

10,...F

100,...F

0.1,...F

1,...F

In BTL Mode, CNF on Pin 15 can be reduced without affecting the
frequency response. However, the turn-on "POP" will be worsened.
CaTL

Used only in the Bridge Mode. Connects the output of the first amplifier to
the inverting input of the other through an internal resistor. Sets a lowfrequency pole in one-half the frequency response.
1
fL =
21T.CaTL·16k

Caw

Improves clipping waveform and sets the high-frequency bandwidth.
Works with an internal 16k resistor. (This equation applies for RAV ".
For 46 dB application, see BW-Caw curve.)
f _
1
H - 21T.Caw.16k

RAV

Used to reduce the gain and improve the distortion and signal to noise. If
this is desired, Caw must also be used.

TypicalAv

See table below

o.

See table below

Caw

RAY
Min

Max

46 dB

Short

Open

4700pF

40dB

82

100 pF

4700pF

34dB

240

270pF

4700pF

28 dB

560

500pF

4700pF

1-65

....w

~

~

r-------------------------------------------------------------------------------------,
Printed Circuit Layout for LM831 N (Foil Side View) Refer to External Component Diagram

A·CH INPUT

TLlH/6754-14

Not.: Power ground pattern should be as wide as possible. Supply bypass capacitor should be as close to the IC as possible. Output compensation capscitors
should also be close to the IC.
.

1-66

~National

~ Semiconductor

DYNAMIC NOISE REDUCTION SVS1EM

LM832 Dynamic Noise Reduction System DNR®
General Description

Features

The LM832 is a stereo noise reduction circuit for use with
audio playback systems. The DNR system is noncomplementary, meaning it does not require encoded source material. The system is compatible with virtually all prerecorded
tapes and FM broadcasts. Psychoacoustic masking, and an
adaptive bandwidth scheme allow the DNR to achieve 10
dB of noise reduction. DNR can save circuit board space
and cost because of the few additional components required.
The LM832 is optimized for low voltage operation with input
levels around 30 mVrms.
For higher input levels use the LM1894.

•
•
•
•
•
•
•
•
•

Low voltage battery operation
Non-complementary noise reduction, "single ended"
Low cost external components, no critical matching
Compatible with all prerecorded tapes and FM
10 dB effective tape noise reduction CCIR/ARM
weighted
Wide supply range, 1.5V to 9V
150 mVrms input overload
No royalty requirements
Cascade connection for 17 dB noise reduction

Applications
•
•
•
•

The DNA. system is licensed to National Semiconductor Corp. under U.S. patent 3,678,416
and 3,753,159.
A trademark and licensing agreement is required for the use of this product

Headphone stereo
Microcassette players
Radio cassette players
Automotive radio/tape players

Order Number LM832M See NS Package M14A
Order Number LM832N See NS Package N14A

Application Circuit
L

INPUT
FROM SOURCE
SELECTOR 18.-----......,
TAPE PREAMP. STEREO I
FM DEMODULATOR. MONO
AM DETECTOR. ETC.
sw

L

r----------..::::::::;::::::~-~~~~ME
CONTROL

C1

39nf

R3
2k

ON

~f

3 C3

v+

~22nF

Cl
lOp.!'

R

+

..

sJ~:~-------

FROM
SELECTOR

R

~~-----------------~ME
CONTROL

FIGURE 1. Component Hook-up for Stereo DNR System

1-67

"TLlH/5176-1

•

Abtjiolute Maximum Ratings
Soldering Information
• Dual-In-Line Package
Soldering (10 seconds)
260"C
• Small Outline Package
Vapor Phase (60 seconds)
215°C
Infrared (15 seconds)
220"C
See AN-450 "Surface Mounting Methods and Their Effects
on Products Reliability" for other methods of soldering surface mount devices."

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
>

Supply Voltage
Power Dissipation (Note 1)
Input Voltage
Storage Temperature
Operating Temperature (Note 1)

10V
1.2W
1.7Vpp
-65 to + 150"C
-40 to +85°

DC Electrical Characteristics TA =

25°CVcc = 3.0V

Symbol

Conditions

Min

Typ

Max

1.5

3.0

9.0

V

2.5

4.0

mA

5.0

8.0

mA

0.36

0.5

V

0.65

0.8

V

0.50

0.65

0.8

V

Pin 4, Pin 11

0.20

0.35

0.50

V

Output Voltage (2)

Pin 5 Stereo Mode

0.15

0.28

0.40

V

VOUT(3)

Output Voltage (3)

Pin 5 Monaural Mode, DC Ground Pin 14

0.10

0.20

0.30

V

VOUT(4)

Output Voltage (4)

Pin 8

0.25

0.40

0.60

V

VOUT(5)

Output Voltage (5)

Pin 10 BW = Max, Note 2

1.00

1.27

1.50

V

VOUT(6)

Output Voltage (6)

Pin 10 BW = Min, Note 2

0.50

0.65

0.75

V

Vos

Output DC Shift

Pin 4, PIN 11; Change BW Min to Max

1.0

3.0

mV

Parameter

VOP
Icd1)

Operating Voltage

Supply Voltage for Normal Operation

Supply Current (1)

Pin 9to GNDO.1 ",F, BW=Min, Note 2

Icd2)
VIN(1)

Supply Current (2)

DC GND Pin 9 with 2k, BW = Max, Note 2

Input Voltage (1)

Pin 2, Pin 13

0.20

VIN(2)

Input Voltage (2)

Pin 6

0.50

VIN(3)

Input Voltage (3)

Pin 9

VOUT(1)

Output Voltage (1)

VOUT(2)

Units

AC Electrical Characteristics
Symbol

I

Parameter

MAIN SIGNAL PATH (Note 3)

I

Conditions

I

Min

I

Typ

I

Max

I

Units

Av
C.B.

Voltage Gain

VIN = 30 mVrms, f = 1 kHz, BW = Max, Note 2

-1.0

0.0

+1.0

dB

Channel Balance

VIN= 30 mVrms, f= 1 kHz, BW=Max, Note 2

-1.0

0

+1.0

dB

fMIN

Min Bandwidth

0.1 ",F between Pin 9 - GND

600

1000

1500

Hz

fMAX
THO

Max Bandwidth

DC Ground Pin 9 with 2k

24

30

46

kHz

Distortion

VIN=30 mVrms, f=1 kHz, BW=Max, Note 2

0.07

0.5

MVIN

Max Input Voltage

THD=3%, f= 1 kHz, BW= Max Note 2

120

150

%
mVrms

SIN

Signal to Noise

REF = 30 mVrms, BW = Max, CCIRIARM

60

68

ZIN
C.S.

Input Impedance

Pin 2, Pin 13

14

20

Channel Separation

Ref = 30 mVrms, f = 1 kHz, BW = Max, Note 2

40

68

dB

PSRR

PSRR

VRIPPLE=50 mVrms, f= 100 Hz

40

55

dB

dB
26

kO

CONTROL PATH
Avsum(1)

Summing Amp Gain (1)

VIN=30 mVrms at Rand L, f= 1 kHz

-3.0

-1.5

Avsum(2)

Summing Amp Gain (2)

DC Ground Pin 14, f= 1 kHz

-9.0

-6.0

0.0
-3.0

Av 1st

Gain Amp Gain

Pin 6 to Pin 8

25

30

35

dB

ZIN 1st

Input Impedance

Pin 6

28

40

52

kO

AVPKD

Peak Detector Gain

AC In, DC Out; Pin 9 to Pin 10

25

30

35

VIV

ZINPKD
VRPKD

Input Impedance

Pin 9
Pin 10, Change BW Min to Max

500

800

1100

0

0.5

0.62

0.8

Output DC Change

Nota 1: For operation in ambient temperature above 25°C, the device must b

~
E

~ ~-0.8%)- r--

............ 1-000-

30
20

10

o

-25

o

25

50

75

TEMPERATURE (OC)
TUH/SI76-11

FIGURE 11. Change in main signal path
maximum bandwidth vs temperature

1-70

~

40

r-

JWITHOUT

30

l!;

20

~

10

19 kHz
PlLOT_

I-

100

FIGURE 9. Frequency response .
for various Input levels

!...

50

o

10k
TL/H/SI76-9

TL/H/SI76-8

FIGURE 8. Output vs frequency
and control path signal

i;'
:!!.

I

N= ,30.d~_

~ -3~

S

60

"'0=10dB I
-Od8

10

10k

TLlH/SI76-7

TUH/SI76-6

FIGURE 5. Output level
change vs supply voltsge

S

10k

TUH/SI76-4

-80

~ -10

100
lk
FREQUENCY (Hz)

FIGURE 4. Power supply
rejection ratio vs frequency

i!'

Vee (V)

.

-60
-70
-BO

20

-70

-

6

1-H~1f-t+1#H#-++H#1!I-I

-90

MAXIMUM BW

~ -40
-50
-60

o

iil
!Ill
12

10k

lllIlN.I.
r~:~:~~M I..Q'

-10
-20

MINIMUMBW - - I -

"'0=30 mVrms '=400 Hz
REF 1 AT Vee = 3V AND MAX BW

1-H+H+It-H-Hi!liI-++HtlIH-I

TL/H/S176-3

-4

co -10
-12
-14
-16

1-H+I*1f-t+1#H#-++H#1!I-I

I-H~lf-I+!I#H#-++H#I!I-I

FIGURE 3. Channel separation
vs frequency

I I
MAXIMUM BW

-2

..

'-

lk
FREQUENCY (Hz)

TL/H/5176-2

FIGURE 2. Supply current
vs supply voltsge

!

I-HttfttH-ttttH+H-t+HttII-I

E-50H+~-+~~++~~

1-60

I

VRIPPLE =500 mVnns
NOMINAL BW
-I-++i++iIH

;a

Ii
!'i
~

10
0
;- -10
~ -20
-30
'" -40

i

0 Vifj =30lIIVrms

i(l
lk
10k
FREQUENCY (Hz)

lOOk

TL/H/SI76-10

FIGURE 10. Gain of control
path vs frequency

Circuit Operation
The LM832 has two signal paths, a main signal path and a
bandwidth control path. The main path is an audio low pass
filter comprised of a gm block with a variable current, and a
unity gain buffer. As seen in Figure 1, DC feedback constrains the low frequency gain to Ay = -1. Above the cutoff
frequency of the filter, the output decreases at -6 dB/oct
due to the action of the 0.022 ,..F capacitor.
The purpose of the control path is to generate a bandwidth
control signal which replicates the ear's sensitivity to noise
in the presence of a tone. A single control path is used for
both channels to keep the stereo image from wandering.
This is done by adding the right and left channels together
in the summing amplifier of F/{/ure 1. The R1, R2 resistor
divider adjusts the incoming noise level to slightly open the
bandwidth of the low pass filter. Control path gain is about
60dB and is set by the gain amplifier and peak detector
gain. This large gain is needed to ensure the low pass filter
bandwidth can be opened by very low noise floors. The capacitors between the summing amplifier output and the
peak detector input determine the frequency weighting as
shown in the typical performance curves. The 1 ,..F capacitor at pin 10, in conjunction with internal resistors, sets the
atteck and decay times. The voltage is converted into a
proportional current which is fed into the gm blocks. The
bandwidth sensitivity to gm current is 70 Hz/,..A. In FM
stereo applications a 19 kHz pilot filter is inserted between
pin 8 and pin 9 as shown in Figure 16.

acts as an integrator and is unable to detect it. Because of
this, signals of sufficient energy to mask noise open the
bandwidth to 90% of the maximum value in less than 1 ms.
Reducing the bandwidth to within 10% of its minimum value
is done in about 60 ms: long enough to allow the ambience
of the music to pass through, but not so long as to allow the
noise floor to become audible.
3. Reducing the audio bandwidth reduces the audibility of
noise. Audibility of noise is dependent on noise spectrum, or
how the noise energy is distributed with frequency. Depending on the tape and the recorder equalization, tape noise
spectrum may be slightly rolled off with frequency on a per
octave basis. The ear sensitivity on the other hand greatly
increases between 2 kHz and 10kHz. Noise in this region is
extremely audible. The DNR system low pass filters this
noise. Low frequency music will not appreciably open the
DNR bandwidth, thus 2 kHz to 20 kHz noise is not heard.

Application Hints
The DNR system should always be placed before tone and
volume controls as shown in F/{/ure 1. This is because any
adjustment of these controls would alter the noise floor
seen by the DNR control path. The sensitivity resistors R1
and R2 may need to be switched with the input selector,
depending on the noise floors of different sources, i.e., tape,
FM, phono. To determine the value of R1 and R2 in a tape
system for instance; apply tape noise (no program material)
and adjust the ratio of R 1 and R2 to slightly open the bandwidth of the main signal path. This can easily be done by
viewing the capaCitor voltege of pin 10 with an oscilloscope,
or by using the circuit of Figure 12. This circuit gives an LED
display of the voltage on the peak detector capaCitor. Adjust
the values of R 1 and R2 (their sum is always 1 kfi) to light
the LEOs of pin 1 and pin 18. The LED bar graph does not
indicate Signal level, but rather instantaneous bandwidth of
the two filters; it should not be used as a signal-level indicator. For greater flexibility in setting the bandwidth sensitivity,
R1 and R2 could be replaced by a 1 kO potentiometer.
To change the minimum and maximum vaiue of bandwidth,
the integrating capaCitors, C3 and C10, can be scaled up or
down. Since the bandwidth is inversely proportional to the
capaCitance, changing this 0.022 ,..F capacitor to 0.015 ,..F
will change the typical bandwidth from 1 kHz-30 kHz to 1.5
kHz-44 kHz. With C3 and C10 set at 0.022 ,..F, the maximum bandwidth is typically 30 kHz. A double pole double
throw switch can be used to completely bypass DNA.
The capacitor on pin 10 in conjunction with internal resistors
sets the atteck and decay times. The atteck time can be
altered by changing the size of C9. Decay times can be
decreased by paralleling a resistor with C9, and increased
by increaSing the value of C9.

Normal methods of evaluating the frequency response of
the LM 832 can be misleat;ling if the input signal is also
applied to the control path. Since the control path includes a
frequency weighting network, a constant amplitude but varying frequency input signal will change the audio signal path
bandwidth in a non-linear fashion. Measurements of the audio signal path frequency response will therefore be in error
since the bandwidth will be changing during the measurement. See Figure 9 for an example of the misleading results
thet can be obtained from this measurement approach. Although the frequency response is always flat below a single
high-frequency pole, the lower curves do not resemble single pole responses at all.
A more accurate evaluation of the frequency response can
be seen in F/{/ure 8. In this case the main signal path is
frequency swept while, the control path has a constant frequency applied. It can be seen that different control path
frequencies each give a distinctive gain roll-off.

PSYCHOACOUSTIC BASICS
The dynamic noise reduction system is a low pass filter that
has a variable bandwidth of 1 kHz to 30 kHz, dependent on
music spectrum. The DNR system operates on three principles of psychoacoustics.
1. Music and speech can mask noise. In the absence of
source material, background noise can be very audible.
However, when music or speech is present, the human ear
is less able to distinguish the noise--the source material is
said to mask the noise. The degree of masking is dependent on the amplitude and spectral content (frequencies) of
the source material, but in general multiple tones around 1
kHz are capable of providing excellent masking of noise
over a very wide frequency range.
2. The ear cannot detect distortion for less than 1 ms. On a
transient basis, if distortion occurs in less than 1 ms, the ear

When measuring the amount of noise reduction of DNR in a
cassette tape system, the frequency response of the cassette should be flat to 10 kHz. The CCIR weighting network
has substantial gain to 8 kHz and any additional roll-off in
the cassette player will reduce the benefits of DNR noise
reduction. A typical signal-to-noise measurement circuit is
shown in Figure 13. The DNR system should be switched
from maximum bandwidth to nominal bandwidth with tape
noise as a signal source. The reduction in measured noise is
the signal-to-noise ratio improvement.

1-71

II

~ r-------------------------------------------~--------------------------~----------------_,

~

~

Application Hints (Continued)
2.2,.F

A~:~~~--------------------~--~

620
620

'TUH/5176-12

FIGURE 12. Bar Graph Display of Peak Detector Voltage

TL/H/5176-13

FIGURE 13. Technique for Measuring SIN Improvement of the DNR System
CASCADE CONNECTION
Additional noise reduction can be obtained by cascading the
DNR filters. With two filters cascaded the rollof! is 12 dB per
octave. For proper operating bandwidth the capacitors on
pin 3 and 12 are changed to 15 nF. The resulting noise
reduction is about 17 dB.

L INPUT

----1

Figure 15 shows the monaural cascade connection. Note
that pin 14 is grounded so only the pin 2 input is fed to the
summing amp and therefore the control path.
Figure 14 shows the stereo cascade connection. Note that
pin 14 is open circuit as in normal stereo operation.

r------------L

+

~47pF...L

1 pF

":'

OUTPUT

39 nF

v+---t~--~--_+~--~--~~--~--~~------.

T

15nF

+

Rl*

1/Af

RINPUT

W

----1

'Rl + R2

= 1 kll (refer to application hints)

FIGURE 14. Stereo Cascade Connection

1-72

TL-l_/Af________ ROUTPUT
TUH/5176-14

Application Hints (Continued)

r------------

OUTPUT

2k

39 nF

ON

r-~~____~~__~~____~____~~____~____~~~~F~:
V+-i---t

I N P U T - - - - - -.....

'Rl + R2

~

TLlH15176-15

1 kll (refer to application hints)

FIGURE 15. Monaural Cascade Connection
FMSTEREO
When using the DNR system with FM stereo as the audio
source, it is important to eliminate the ultrasonic frequencies
that accompany the audio. If the radio has a multiplex filter
to remove the ultrasonics there will be no problem.
This filtering can be done at the output of the demodulator,
before the DNR system, or in the DNR system control path.

Standard audio multiplex filters are available for use at the
output of the demodulator from several filter companies.
Figure 16 shows the additional components L1, C15 and
C16 that are added to the control path for FM stereo applications. The coil must be tuned to 19 kHz, the FM pilot
frequency.
~---------~L~I-----LOOO""
4.7mK

C16
15nF

II
FROM FM MPX
'Rl+R2~1

~~---6-1!Il~

1,.1'

R INPUT

----1

Kil

(refer to application hints)

~---------------ROOOPUT

+

TLlH15176-16

FIGURE 16. FM Stereo Application
FOR FURTHER READING
Tape Noise Levels

Noise Masking
1. "Masking and Discrimination", Bos and De Boer, JAES,
Volume 39, #4,1966.

1. "A Wide Range Dynamic Noise Reduction System"
Blackmer, 'dB' Magazine, August-September 1972, Volume
6, #8.

2. "The Masking of Pure Tones and Speech by While
Noise", Hawkins and Stevens, JAES, Volume 22, # 1, 1950.
3. "Sound System Engineering", Davis, Howard W. Sams
and Co.
4. "High Quality Sound Reproduction", Moir, Chapman Hall,
1960.

2. "Dolby B-Type Noise Reduction System", Berkowitz and
Gundry, Sert Journal, May-June 1974, Volume 8.
3. "Cassette vs Elcaset vs Open Reel", Toole, Audioscene
Canada, April 1978.
4. "CCIRI ARM: A Practical Noise Measurement Method",
Dolby, Robinson, Gundry, JAES, 1978.

5. "Speech and Hearing in Communication", Fletcher, Van
Nostrand, 1953.
1-73

LM832 Simple Circuit Schematic

i...

-

:::

n

,...
=

~

rf1

'"'

,,10

I

,...

'1.

).r1'

I

'-'

I

,...

-e.

"iN"""'\.

~

'-'

,

--

-~

rsc

J.

-

...,

)..-1"

~

..

\..

_zg
i

--'"

il

lD~i

~

-

..!
III

~

1...t

~

.10

-i

r"'\

'-'

Y

r::v
-

L

~

N

i.
1-74

l

_zill

..

. r"'\
'-'

y
S

--"o...L

r:yY'

¥
I"":'"

ifg

~!""

T

Y
...
-

~
,...

~

'-'

I!

~

~

l).~

~
,...

X

\.~

A

.

~

J......
..!Cl
1.~

7

;:

u

-

A

'-'

.

. Ii

•

r------------------------------------------------------------------.r

~

~National

E

~ Semiconductor

LM833 Dual Audio Operational Amplifier
General Description

Features

The LM833 is a dual general purpose operational amplifier
designed with particular emphasis on performance in audio
systems.

• Wide dynamic range

This dual amplifier IC utilizes new circuit and processing
techniques to deliver low noise, high speed and wide bandwidth without increasing external components or decreasing
stability. The LM833 is internally compensated for all closed
loop gains and is therefore optimized for all preamp and
high level stages in PCM and HiFi systems.
The LM833 is pin-for-pin compatible with industry standard
dual operational amplifiers.

Schematic Diagram

7 V/p.s (typ)
5 V/p.s (min)
15 MHz (typ)
10 MHz (min)
120 kHz
0.002%
0.3 mV

• High slew rate
• High gain bandwidth product
•
•
•
•

Wide power bandwidth
Low distortion
Low offset voltage
Large phase margin

60"

Connection Diagram

(1/2 LM833)

+VCC"-B_ _ _....._ _ _ _......_ _......_

>140 dB
4.5 nV/./Hz

• Low input noise voltage

...._ _...._ _....- - ,

OUlA

+Vcc

-INA

OUlB

360

+INA ......-

-INB

......

L--t=-+INB
TL/H/5218-2

Order Number LM833M or LM833N
See NS Package Number
M08A or NOSE

TL/H/5218-1

Typical Application RIM Preamp
33 ~F

rrr---~I

I

PHONO
CARTRIDGE:

I

I
I
I

470
47k

IL":'___ ..1I

16k

200k

390

TUH/5218-3

A.,

~

En

~

SIN

35 dB

f

0.33,.V
90 dB

A Weighted, VIN

~

~

1 kHz

A Weighted
@f~1kHz

1-75

~

10 mV

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260"C
Small Outline Package
Vapor Phase (60 seconds)
21S'C
220"C
Infrared (1S seconds)
See AN-4S0 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

Supply Voltage
36V
Vee-VEE
±30V
Differential Input Voltage (Note 1) VIO
±1SV
Input Voltage Range (Note 1)
VIC
SOOmW
Power Dissipation (Note 2)
Po
Operating Temperature Range
-40 - 8S'C
TOPR
-60 - 1SO"C
Storage Temperature Range
TSTG

DC Electrical Characteristics (TA =
Symbol

ESD tolerance (Note 3)

1600V

2S'C, Vs = ±1SV)
Typ

Max

Units

0.3

S

mV

Input Offset Current

10

200

nA

Input Bias Current

SOO

1000

nA

Parameter

Vas

Input Offset Voltage

los

18

Min

Conditions
Rs = 10.0

Av

Voltage Gain

RL=2k.o,Vo= ±10V

VOM

Output Voltage Swing

RL=10k.o
RL = 2 k.o

VCM

Input Common-Mode Range

CMRR

Common-Mode Rejection Ratio

VIN = ±12V

PSRR

Power Supply Rejection Ratio

Vs = 1S-SV, -1S- -SV

IQ

Supply Current

Vo = OV, Both Amps

AC Electrical Characteristics (TA =

90

110

dB

±12
±10

±13.S
±13.4

V
V

±12

±14.0

V

80

100

dB

80

100

dB

S

8

mA

2S'C, Vs = ± 1SV, RL = 2 k.o)
Conditions

Min

Typ

SR

Slew Rate

RL = 2kO

S

7

V/p,s

GBW

Gain Bandwidth Product

f

10

1S

MHz

Symbol

Parameter

=

100kHz

Design Electrical Characteristics (TA = 2S'C, Vs
The following parameters are not tested or guaranteed.
Symbol

Parameter

AVoslIH

Average Temperature Coefficient
of Input Offset Voltage

THO

Distortion

=

RL = 2 k.o, f = 20-20 kHz
VOUT = 3 Vrms, Av = 1

en

Input Referred Noise Voltage

Rs

Input Referred Noise Current

f

PBW

Power Bandwidth

Vo

fu

Unity Gain Frequency

M

Phase Margin

=

=

Units

2

p,VI'C

0.002

0/0

4.S

nVl.JHz

0.7

pA/.JHz

=

120

kHz

Open Loop

9

MHz

Open Loop

60

deg

-120

dB

Input Referred Cross Talk
f
Note 1: If supply voltage is less than ± 15V, H is equal to supply voltage.
Note 2: This is the permissible value at TA :;;; 85'C.
Note 3: Human body model, 1.5 kll in series with 100 pF.

1 kHz

Typ

1 kHz

=

100.0, f

Units

±1SV)

Conditions

in

Max

27 Vpp , RL = 2 k.o, THO';;: 10/0

= 20-20 kHz

1-76

Typical Performance Characteristics
Maximum Power
Dissipation
vs Ambient Temperature

Input Bias Current vs
Supply Voltage

Input Bias Current vs
BOO Ambient Temperature

_1000

800

Vs= ±15V

I

700

~ BOO

.!~; =;

-

~ 600

ffi

l-

~ 300

......

300

200

~

200

;s

500
L-- '.,.,- ~
~ 400

iE
~

200

~

0

=>

-,

-50

,,

50
100
TEMPERATURE ("C)

~

~

7
6
1 . .-

5

0 25 50 75 100 125
TEMPERATURE ("C)

DC Voltage Gain
vs Supply Voltage
120

120

~

VS=±15V
RL=2 kll

r- ~Ioo.

r--

-.

~

110

~

100

~

.
0

".

BO
-50 - 25 0

20

25

Gain Bandwidth Product
vs Ambient Temperature

Voltage Gain" Phase
vs Frequency
100

iz
:c
...coco
~

g

-...

Vs= ±15V
Rt 2 D

r

"' BAIN
BO

PHAS~-

I'

60

"

40

~~

,

30

~

-60

-150

1

,.3!
'"
m

-90

"

-~O

10 100 lk 10k lOOk 1M 10M
FREQUENCY (Hz)

.

~

-30

Vs= ±15V
'=100 kHz

....
=>

0
0

-;

IE

ill,.,

I;

1"""" -120 .§

20

o

75 100 125
TUH/5218-8

TUH/5218-7

120

50

TEMPERATURE ("C)

20

:z:

~
lI!
CD
z
:c
co

..... r---.

10

-r- "-

I--

o
-50 -25

0 25 50 75 100 125
TEMPERATURE ("C)
TL/H/5218-11

TLlH/5218-10

1-77

20

TUH/5218-8

DC Voltage Gain
vs Ambient Temperature

10
15
SUPPLY VOLTAOE (± V)

10
15
SUPPLY VOLTAGE (± V)

TL/H/5218-5

0

o

400

o

-50 -25

I

o

io-.

500

100

o

Supply Current vs
Supply Voltage
TA=25"C
RL=OO --

~
'"
=>

~

TL/H/5218-4

10
9

....

100

150

-

~ 600

i
=

BOO

TA=25"C

700

90

TA=25"C
RL=2 kO

~ f-"

-

Typical Performance Characteristics (Continued)
Slew Ratev8
. Ambient Temperature

,.. ,

10

l

~

~

~
'"

Slew Ratev8
Supply Voltage

Vs= ±15V
9 RL=2knAII=l .
8
FALUNG;;
~
7

' 'd$f

6
5
4
3
2
1

..n..~

+

10

9
RL=2kn
8 AII-l

l

Ii
'"
~
'"

Yo

....

Q

+1

J

FALUNG

".~

6
5
4
3
2
1
0

-50 -25 0 25 50 75 100 125
TEMPERATURE (OC)

..n..~

+

.

~

~
co
...,..
f;

6

10

~
~

0

.
i
!;

.......

-5
-10

l"""'-

-15

10
15
SUPPLY VOLTAGE (± V)

10

15

Vs= ±15V
RL=10kn

20

iii

:e.

'"

IE
u

80

-

8D

r-

40

r-

20

I

~VD~

13

VoM

r-

0
100

_

2lt

....
lk

,

2

-~
'" ....
10k lOOk 1M
FREOUENCY (Hz)

--

11

-

r1
+

0.1

"-

~ 0.01

....

Va

2k

fi

I

l'

Vo=3 Vlms

-

1
Yo~1

0.001
10M

!

8D

i'

10

100

lk
10k
FREGUENCY (Hz)

TL/H/521B-19

VIm.
lOOk

TL/H/5218-20

1-78

10M

-

Vs= ±15V

,,

,-PSRR
6~

40
20

RL=2 kn -

~
i!!i

+PSRR
100

'"

DI8tortion V8 Frequency

Vo-

lOOk
1M
FREGUENCY (Hz)

TUH/5218-15

'"
If

N'W

\ ....

10k

PSRR V8 Frequency

12

1

~.~

lk

120

TLlH/5218-17

I I

100

, ,

14

CMR V8 Frequency
Vs- f15V

\

100

2D

Maximum
Output Voltage V8
Ambient Temperature

TLlH/5218-16

120

\

10

::>

10
-50 -25 0 25 50 75 100 125
TEMPERATURE (OC)

-20
5

...
...coi

Va

2k

TL/H/5218-14

...~

",.,...

5

15

SUPPLY VOLTAGE (± V)

15

~

2D

,..~

0
5

Maximum
Output Voltage V8
2D Supply Voltage
15

!!j

co

Vs= ±15V
RL=2kn
THD"l"

25

5

TL/H/5218-13

TA-25°C
RL=10kll

~

7

~

2k

Power Bandwidth
3D

1A=25°C ,

0
100

lk

10k lOOk 1M
FREGUENCY (Hz)

10M

TLiH/5218-18

Typical Performance Characteristics (Continued)
Spot Noise Voltage
vs Frequency
10

Spot NOise Current
10

~~~,t
I"-

Va

±15V

~:8~requency

100

TA-25'C
Va +15V

I'l
6;:;-

m~

~B 0.5
Ill.~

If$
~

z~

... z
......
I.""

Input Referred Noise Voltage
vs Source Resistance

~~~~!!~~~I

, . . . . .NT

...DllA1JDI~~~' WEIG~T1
~

~

0.2 t+-++-H-++-+-ir-+-+i
lOOk

0.1 L..L......L..J......l---'-....L...-J......J..J....L...L..I
10
100
lk
10k
lOOk
FREQUENCY (Hz.

TUH/5218-21

TLlH/5218-22

1
10

1l1li
lk
10k
FREQUENCY (Hz.

Nonlnverting Amp

,~

0.1
1l1li

LJ83~

1A =25'C
Va=±15V
lk
10k
lOOk
SOURCE RESISTANCE (0)

1M

TUH/5218-23

Nonlnverting Amp

TIME (0.2 pl/DIY.

TIME (2 pl/DIY)
TUH/5218-24

TLlH/5218-25

Inverting Amp

TIME (2 pl/DIY)
TL/H/5218-26

Application Hints
Capacitive loads greater than 50 pF must be isolated from
the output. The most straightforward way to do this is to put
a resistor in series with the output. This resistor will also
prevent excess power dissipation if the output is accidentally shorted.

The LM833 is a high speed op amp with excellent phase
margin and stability. Capacitive loads up to 50 pF will cause
little change in the phase characteristics of the amplifiers
and are therefore allowable.

1-79

•

Noise Measurement Circuit
Complete shielding is requlred to prevent .induced pick up from external
sources. Always check with oscilloaoope for power line noise.
+Vcc -VEE

> .....-:t'Il-ovo
AVERAGE RESPONDING
AC VOLT MmR

~----

__

------~'\~

________________

~.

RIAA PREAMP
3& dB, 1~1 kHz

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

FLAT AMP. 40 dB +40 dB
TLlH/~218-27

Total Gain: 115 dB @f = 1 kHz
Input Referred Noise Voltage: en = VO/S60,OOO (V)

RIM Preamp Voltage Gain, RIM
Deviation vs Frequency
50

;;-

i

90 ¥o=OdBv

.....

VIN-l0mV

f"'O

35.0 dB, '=1 kHz

i

30

~

20

!i!

10

~

Flat Amp Voltage Gain vs
Frequency

IIII1I11I1
itHIIIIIIII!IIIIIIIIII
:!!.

co

20

100

lk

60

!i!

50
40

~

40

70

i

30
20
10

'10k 20

100

lk

10k

lOOk

FREOUENCY (HzI

FREOUENCY (HzI

TL/H/5218-29

TL/H/5218-28

1·80

r-----------------------------------------------------------------------------'r

i:

Typical Applications

C»

~

NAB Preamp Voltage Gain
70 vs Frequency

NAB Preamp

1Jttm~t:+1~.Y!N
10 mY
34.5=dB,
1=1 kHz
60 ..
;;o' 50
~

......
z

Vo

C

~

co

'"

Av = 34.5

F = 1 kHz
En = 0.38,.V

20
10
0
20

A Weighted

200k

40
30

100

lk
FREQUENCY (Hz)

10k 20k
TL/H/5218-31

200

+
47 pF
TUH/5218-30

Balanced to Single Ended
Converter

Adder/Subtracter

Sine Wave OSCillator

R

V2

-Yv"-'"

Vo

V2-Yv",,""+i
Va

Vo

V3-Yv"-..

Vl-Yv"-.....

R

V4-Yv'\f-"
Vo

= VI +

V2 - V3 - V4

•

TUH/5218-32

1=_1_

o

Second Order High Pass Filter
(Butterworth)

2".RC

Second Order Low Pass Filter
(Butterworth)
Cl
0.022 pF

Rl
11k

Va
Vo

TL/H/5218-36

TL/H/5218-35

HRI = R2

IIC1=C2=C

R2

C2=2!.
2

= 20Rl

Illustration is 10

=R

= 1 kHz
Illustration is fa

1-81

=

1 kHz

~ ~--------------------------------------------------------------------------------,

:3
:::::&
....

Typical Applications (Continued)
State Variable Filter
R2
10k

Cl
0.01 pf

Rl
16k

R2
10k

Rl
16k

VaP

VtiP

R2

RO
556

':'

10k
TLlH/5218-37

1
2".C1Rl'

1 ( 1+-+R2
R2) ABP~QALP~QALH~R2
2
RO RG'
RG

lo~---Q~-

Illustration is 10

~

1 kHz, Q

~

10, Asp

~

1

AC/DC Converter
Cl
10pf

R5

20k
'R3
10k

R2

20k

R4
20k

01

IS1588
Vo~IV,"1

02

IS1588

R8
15k

R7
6.2k
':'

TLlH/5218-38

2 Channel Panning Circuit (Pan Pot)

Line Driver
R2

3.41Rl
51k

Rl
15k

Rl
15k

Rl

VJ-wy.-....

-+_.,

O,70~:~ ~_ _

Rl

Rl

15k

15k

t--+-Vo

Yo.

TLlH/5218-39

TLlH/5218-40

1-82

Typical Application (Continued)
Tone Control

I
IL

Rl
11k

v,

BOOST -BASS-CUT
R2
lOOk

Cl
0.05 pi'

I

= 27TR2CI' ILB = 27TRICI

1 - _1_ 1

-

:=-::::--:-::~-::=:::

H - 27TR5C2' HB - 27TCRI + R5 + 2R3)C2

Rl
11k

Illustration is:
IL = 32 Hz, IL8 = 320 Hz
IH = 11 kHz, IHB = 1.1 kHz

Cl

D.DSpI'

20dB---.......
17 dB -----"k.

R3
11k

3 dB ----+--,~
C2

v.

D.DD5,F
R5
3.61<

R4
50Dk

-20dB---J

BOOST - TIIOLE-CUT

TUH/5218-41

IHB

IH
TUH/5218-42

Balanced Input Mlc Amp

v,

R4
10k

R3
10k

IIR2

= R5,R3 = R6,R4 = R7

vo=

2R2)
R4
( 1+
- -(V2-VI)
RI
R3

10 Band Graphic Equalizer

Illustration is:
VO = 101(V2 - VI)

r
':'

Rl
200

CUT

R2
10k

v.

R5
10k

A6
10k

v,

,

-

3k

Yo

II

R7
10k

I

':'

V2

L

TL/H/5218-43

':'

fo(Hz)

Cl

C2

Rl

R2

32
64
125
250
500
1k
2k
4k
8k
16k

0.12p.F
0.056p.F
0.033p.F
0.015p.F
8200pF
3900pF
2000pF
1100pF
510pF
330pF

4.7p.F
3.3p.F
1.5p.F
0.82p.F
0.39p.F
0.22p.F
0.1p.F
0.056p.F
0.022p.F
0.012p.F

75kO
68kO
62kO
68kO
62kO
68kO
68kO
62kO
68kO
51kO

5000
5100
5100
4700
4700
4700
4700
4700
5100
5100

At volume 01 change

= ± 12 dB

a=

1.7

Reference: "AUDIO/RADIO HANDBOOK", National Semiconductor, 1980, Page 2-61

1-83

~ ~National
~ Semiconductor
LM837 Low Noise Quad Operational Amplifier
General Description

Features

The I-M837 is a quad operational amplifier designed for low
noise, high speed and wide bandwidth performance. It has a
new type of output stage which can drive a 6000. load, making it ideal for almost all digital audio, graphic equalizer, preamplifiers, and professional audio applications. Its high performance characteristics also make it suitable for instrumentation applications where low noise is the key consideration.

• High slew rate
• Wide gain bandwidth product
•
•
•
•
•
•

The LM837 is internally compensated for unity gain operation. It is pin compatible with most other standard quad op
amps and can therefore be used to upgrade existing systems with little or no change.

Power bandwidth
High output current
Excellent output drive performance
Low input noise voltage
Low total harmonic distortion
Low offset voltage

10 Vlp.s (typ)
8 Vlp.s (min)
25 MHz (typ)
15 MHz (min)
200 kHz (typ)
±40mA
>6000.
4.5 nV/JHz
0.0015%
0.3 mV

Schematic and Connection Diagrams
114 Quad

r-----------~----------------.__ov~

Dual-In-Line Package

I-.....---t--OOUT

OUT1
-IN 1
+IN1-:-1-=;;;....I
v~

+IN2 -:-If-=~
-IN2
OUT2
TUH/9047-2

Top View

L-__~--------~----------~--~~~v~
TUH/9047-1

1-84

Order Number LM837M or LM837N
See NS Package Number M14A or
N14A

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

VcclVEE

±18V
±30V

Differential Inpu1 Voltage (Note 1)

VID

Common Mode Input Voltage
(Note 1)

VIC

±15V

Power Dissipation (Note 2)

PD

1.2W(N)
830 mW (M)

Operating Temperature Range

TOPR

- 40'C to

Storage Temperature Range

TSTG

- 60'C to

VOS

215'C
220'C

ESD rating is to be determined.

25'C, Vs = ±15V

Parameter
Inpu1 Offset Voltage

260'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" lor other methods 01 soldering surlace mount devices.

+ 85'C
+ 150'C

DC Electrical Characteristics TA =
Symbol

Soldering Inlormation
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

Condition

Min

Typ

Max

Units

0.3

5

mV

10

200

nA

500

1000

Rs = 500

los

Input Offset Current

18

Input Bias Current

Av

large Signal Voltage Gain

RL = 2 kO, VOUT = ±10V

VOM

Output Voltage Swing

VCM

Common Mode Input Voltage

CMRR

Common Mode Rejection Ratio

VIN = ±12V

PSRR

Power Supply Rejection Ratio

Vs = 15 - 5, -15 -

Is

Power Supply Current

RL =

nA

90

110

dB

RL = 2kO

±12

±13.5

V

RL = 6000

±10

±12.5

V

±12

±14.0

V

80

100

dB

80

100

AC Electrical Characteristics TA =

-5

Four Amps

dB

10

15

mA

25'C, Vs = ±15V
Min

Typ

SR

Slew Rate

RL = 6000

8

10

V//Ls

GBW

Gain Bandwidth Product

1= 100 kHz, RL = 6000

15

25

MHz

Symbol

Parameter

00,

Condition

Design Electrical Characteristics TA =
Symbol

Max

Units

25'C, Vs = ± 15V (Note 3)

Parameter

Condition

= 25 Vp.p, RL = 6000, THD < 1 %

Min

Typ
200

Max

Units

PBW

Power Bandwidth

Vo

en1

Equivalent Input Noise Voltage

JISA, Rs = 1000

0.5

kHz
/LV

en2

Equivalent Input Noise Voltage

1= 1 kHz

4.5

nV/,fHz

in

Equivalent Input Noise Current

1= 1 kHz

0.7

pAl,fHz

THD

Total Harmonic Distortion

Av = 1, VOUT = 3Vrms,
I = 20 - 20 kHz, RL = 6000

0.0015

%

Iu

Zero Cross Frequency

Open loop

12

MHz

m

Phase Margin

Open loop

45

deg

Input-Relerred Crosstalk

1=20-20kHz

l:.vos/t:..T

Average TC of Input Offset Voltage

-120

dB

2

/LV/'C

Note 1: Unless otherwise specHied the absolute maximum input voltage is equal to the power supply voltage.
Note 2: For operation at ambient temperatures above 25'C, the device must be derated based on a 15O'C maxlmum junction temperature and a thermal
resistance, iunction to ambient, as follows: LMB37N, 9O'C/W; LMB37M, 15fY'C/W.
Note 3: The following parameters are not tested or guaranteed.

1-85

•

~

co

:i

Detailed Schematic
1/4 QUAD

OUT

ANOTHER
CH.

,...----...-..

TLlH/9047 -9

1·86

,-----------------------------------------------------------------------------,
Typical Performance Characteristics
Maximum Power Dlll8lpatlon vs
Ambient Temperature

g
iI

!i

Ili
I!I

I

i

Normalized Input Bias Current
vs Supply Voltage
1.5

2.0
1.8
1.8
1.4
1.2

o.a
o.a

"

IIpIcg

~o

I

~

....

- -

lD
0.9

0.5

o

25 !lO 75 lC11 125 1!lO

10

lENPERAlURE (Ge)

! ::
i

~

-

,.

8

11
9

o

10

15

I

I

~

.........
i"o-""

10

~

~-i

5

5
0

l~oc

~

I
I!!

tVOI/AX

<:>

14

Go

15

~

~.

11

:
-VOI/AX

-15

-14

--

-15
-!lO -25 0

25 50 75 lC11 125 150

AII81EIIT TEMPERAlURE (OC)

i

5

~

....

-5

15

...........

........ ......

-10
-15
-20

10

20

o

10

15

SUPPLY VOLTAGE (iV)

Power Bandwidth
50

VS=iI5V.I\=6000

VS=i15V.R L=8004
TA-25"C·1HD

.e
III

1\ -

:Ii
C>

......'"
~

OUT

"

K

V

...
J
Tlt.iE (0.1 /.Is/flV)

TIME (0.1 ms/DIY)
TLiH/9047-6

Large Signal Non-Inverting

Large Signal Inverting

TA = 2so C,RL = 600n, Vs = ±1SV

TA = 25°C, RL = 600n, Vs = ± 1SV

~

.I

I
J

TL/H/9047-7

,

1

,

\

L

\
.I

1

I

I

\

I

,

1

\

TIME (1 /.Is/DIY)

TIME (1 /.Is / DIY)
TLiH/9047-8

TLiH/9047-9

1-89

•

~National

~ Semiconductor

LM1035/LMt036 Dual DC Operated
Tone/Volume/Balance Circuits
General Description

Features

The LM1035/LM1036Is a DC controlled tone (bass/treble),
volume and balance circuit for stereo applications in car radio, TV and audio systems. An additional control input allows loudness compensation to be simply effected.

•
•
•
•
•

Four control inputs provide control of the bass, treble, balance and volume functions through application of DC voltages from a remote control'system or, alternatively, from
four potentiometers which may be biased from a zener regulated supply provided on the circuit.

Wide supply voltage range, 8V to 18V
Large volume control range, 75 dB typical
Tone control, ±15 dB typical
Channel separation, 75 dB typical
Low distortion, 0.06% typical for an Input level of
1 Vrms (0.3 Vrms for LM1036)
• High signal to noise, 80 dB typical for an input level of
1 Vrms (0.3 Vrms for LM1036)
• Few external components required

Each tone response is defined by a single capaCitor chosen
to give the desired characteristic.

Block and Connection Diagram
Dual-in-Une Package

INTERNAL SUPPLY DECOUPLE

..1.J==::;-'7---,

INPUT 1
18 TREBLE CAPACITOR 2

TREBLE CAPACITOR 1

17 ZENER VOLTAGE

TREBLE CONTROL INPUT
AC BYPASS 1
BASS CAPACITOR 1

BASS CAPACITOR 2

LOI/DNESS COMPENSATION
CONTROL INPUT

BASS CONTROL INPUT

OUTPUT 1

OUTPUT 2
12 VOLUME CONTROL INPUT

BALANCE CONTROL INPUT
GND
TOP VIEW

Order Number LM1035N or ~M1036N
See NS Package Number N20A

1-90

TlfHf5142-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
LM1036
16V
LM1035
20V
Control Pin Voltage (Pins 4,7,9,12,14)
Vee

O·Cto +700C

Operating Temperature Range
Storage Temperature Range

- 65·C to + 1500C

Power Dissipation

1W

Lead Temp. (Soldering, 10 seconds)

2600C

Electrical Characteristics Vee = 12V, TA = 25·C (unless otherwise stated)
Parameter
Supply Voltage Range

Min

Max

Units

I
I

LM1036

9

16

V

LM1035

8

18

V

45

mA

5

V
mA

Supply Current

35

Zener Regulated Output
Voltage
Current

Pin 17

Maximum Output Voltage
LM1036

Pins 8,13; f= 1 kHz
Vee = 9V, Maximum Gain
Vcc=12V

Maximum Output Voltage
LM1035

Typ

Conditions
Pin 11

5.4

Pins 8,13; f= 1 kHz
Vcc=8V
Vcc=12V
VCC=18V

0.8
1.0

Vrms
Vrms

1.3
2.5
3.5

Vrrns
Vrms
Vrms

1.3

1.1
1.6

Vrms
Vrms

2.5

Vrrns

30

kO

0.8

2

Maximum Input Voltage
LM1036 (Note 1)

Pins 2, 19; f= 1 kHz, Vee = 9V
Flat Response, Vee = 12V
Gain = -10dB

Maximum Input Voltage
LM1035 (Note 1)

Pins 2,19; f= 1 kHz
Flat Response

2

Input Resistance

Pins 2,19; f= 1 kHz

20

Output Resistance

Pins 8, 13;f = 1 kHz

Maximum Gain

V(Pin 12)=V(Pin 17);
f= 1 kHz

Volume Control Range

f= 1 kHz

Gain Tracking
Channel1-Channel2

f= 1 kHz
o dB through -40 dB
-40 dB through -60 dB

Balance Control Range

Pins8,13;f=1 kHz

l
1

0

20
-2

0

LM1036

70

75

dB

LM1035

70

80

dB

1
2

2

3

dB

dB
dB

1
-26

-20

dB
dB

Bass Control Range
(Note 2)

f=40 Hz, Cb = 0.39 ,...F
V(Pin 14) = V(Pin 17)
V(Pin 14)=OV

12
-12

15
-15

18
-18

dB
dB

Treble Control Range
(Note 2)

f= 16 kHz, CI,=0.01 ,...F
V(Pin 4)=V(Pin 17)
V(Pin4)=OV

12
-12

15
-15

18
-18

dB
dB

Total Harmonic Distortion
LM1036

f= 1 kHz, VIN=0.3 Vrrns
Gain=O dB
Gain = -30dB

0.06
0.03

0.3

%
%

Total Harmonic Distortion
LM1035

f=1 kHz, VIN=1 Vrms
Maximum Gain

0.05

0.2

%

1-91

•

Electrical Characteristics Vcc= 12V, TA = 25"C (unless otherwise stated) (Continued)
Parameter
Channel Separation

Signal/Noise Ratio
LM1036

Signal/Noise Ratio
LM1035

Conditions
f= 1 kHz,
Maximum Gain

LM1036

Supply Ripple Rejection

200mVrms,
1 kHz Ripple

75

75

Unweighted 100 Hz-20 kHz
Maximum Gain, 0 dB = 1 Vrms
CCIR/ARM (Note 3)
Gain=O dB
Gain=-20dB
CCIR/ARM
(Note 3)

Typ

60

LM1035

Unweighted 100 Hz-20 kHz
Maximum Gain, 0 dB = 0.3 Vrms
CCIR/ARM (Note 3)
Gain=O dB, VIN=0.3 Vrms
Gain= -20 dB, VIN= 1.0 Vrms

Output Noise Voltage at
Minimum Gain

Min

76

Units
dB

75

dB

80

dB

79
72

dB
dB

80

dB

80
64

dB
dB

LM1036

10

16

/LV

LM1035

25

35

/LV

LM1036

35

LM1035

50

dB

40

dB

Control Input Currents

Pins 4, 7,9,12,14(V=0V)

-0.6

Frequency Response

-1 dB (Flat Response
20 HZ-16 kHz)"

250

Nota 1: The maximum permissible input level is dependent on tone and volume sellings.
Note 2: The tone control range is defined by capacitors Cb and

Max

-2.5

!LA
kHz

See Application Notes.

c.. See Application Notes.

Note 3: Gaussian noise, measured over a period of 50 ms per channel, with a

CCIR filter referenoed to 2 kHz and an averagEHllsponding meter.

I
I

1-92

r----------------------------------------------------------------------,r
!iii:
.....

Typical Performance Characteristics
Volume Control
Characteristics

-20

iz

is

l/

I

-40

Balance Control
Characteristic

V

~

-88

o

!

16

-20

II'

-24
-28

1
4
5
V12 - CONTROL VOIlMlE (V)

!z

1\

-10

2

3

4

nr-""-.-..-,-,,

2Or--r--1,-,.-,--.---r--,,......,

151o.:::-Hf---!;

15

Loudness Compensated
Volume Characteristic
10

I.::-+-H-H-+-I-+:A

10

1-t-t-7F-t-+-~-H

-5

z

11

5 1--+-1-'1(."'

;

-3"~-+-+~

0
-5 t----1r+>"t
-10

-15

-15 I""'+-H-H-+-I-+""I
- 20 L...-.l-JL......L--1---'--L.....J......L....J
20
100
500
ak
20k
FREOUENCY (Hz)

20

100
5GO
5k
FREQUENCY (Hz)

20k

-10
-20 ~

~2.6

0.08

FLAT FIIEQII£NCY

0.115

i2.4 I=SE
GAINS
2.2

1,\

Iii

!2D
f

).

1.8

~u

I~

I::
i

V

,

~

LMl036

I
B 10121416182022
SUPPLY VOLTAGE (V)

Loudness Control
CharacteristiC
Z5

20

!

I

I.

TOI CONTROLS FLAT

-5

~

Ii

\
o

~

I
\.

o

0

Ii

40
3D

6

t"'~

20
10

-10 -20 -30 -40 -50
GAIN (dB)

40

FLAT FREQUENCY RESPONSE
BALANCED IIAIMS
20

FREDUENC:Ii~
D.• FLAT
HESPONBE
...
BALANCED MIllS ~
0.2 MAXIMUIiIAIN ..
Vce=l2V
~Ioo'
0.1

! 0.01

-40
-110
GAIN (dB)

lDO
SOD
5k!Ok
FREGI/ENCY (Hz)

THO vs Input Voltage-LM1036

~"

-20

.... 1'

~

1.0

0.02

~

.J.
~""'"

~;
-!~

,.!,

0.01

¥t:c=9V

o

II

I"'-r--

60

30

!:

~

j,;~

iii
z 50

...i

TONE CONTROLS FLAT
BALANCED GAINS
50 CCIR FILTER

o
1
3
4
5
V7-CONTROL VOLTAGf (V)

I

III

~HZ

10

.

~

Output Noise Voltage
vs Galn-LM1036

YtI=ll11mV

18 kHz ......

ill
Ci 70

IlAlJlllCEOIIAIN.
10

20k

go

"

0.00

PIN 12

100
SOD
Bk
FREOUENCY (Hz)

20

ii
:!!. 80

0.01 1-1 kHz
I-FLAT FREQUENCY RESPONSE

1 1

1.0 6

,

0.04

.... "'- "

r--

-60

~

./

Channel Separation vs
Frequency

r\

!: 0.03
~ 0.02

LMI035

1' ....

:"~I~~.iEcm,

-50

THO vs Gain

1~~;H~'OaD

.....

1-30 rr- " 1'"

Input Signal Handling vs

12.8 Supply Voltage

..... ....

I""-r-.

-40

-10I-Hl-+
-20~~~~~~~~~

CUT
40 Hz OR 16 kHz

4
V4 OR VI4-CONTROL VOLTAGE (V)

Tone Characteristic (Gain
vs Frequency)

i

lL

V

o

5

Tone Characteristic (Gain
VB Frequency)

i

IL

-15

1

/

o
~

j

:i
-5

II
o

10

VI - CONTROL VOLTAGE (V)

10

I

J

800ST
40 Hz OR 16 kHz

r
!iii:
.....

/

"1\\

1/

1_

15

t\.. CHANNEL , -

I

'-8
-12

Tone Control Characteristic

J

CHNlNEL2~

-4

)

-61

1. J

o

~~::mv_

If

2

!!!

-80

0.00

D.O

0.2
0.4
0.8 0.8
INPUT VOIlMlE (VlOII)

1.0
TUH/5142-2

1-93

I....

........::E
an
S
....::E

....

Typical Performance Characteristics

(Continued)

Output Noise Voltage
vs Galn-LM1035

THO vslnput Voltag_LM1035

~~~~~~--~~~~

'i
~

70

~

60

-

I-r-..~.---If--+---+ BW = 20

80

r--..

kHz

~~~r:~~UENCY

1'\

BALACED GAINS

I'\~

g

50

5

Vcc=BV ....... i'oo...
~~~~~~+=~~--~~

;:
§

0.50

,

'\

Vcc=12V

.... ~

10~4--+--~+-~~--+-~
oL-~~-L~--~~~~

o

-20

-40

-60

D.25

0.75

1.25

1.75

2.25

INPUT VOLTAGE (Vrrns)

GAIN (dB)
TL/H/5142-20

TL/H/5142-21

Application Notes
TONE RESPONSE

LOUDNESS COMPENSATION
A simple loudness compensation may be effected by applying a DC control voltage to pin 7. This operates on t~e tone
control stages to produce an additional boost limited by the
maximum boost defined by ~ and Ct. There is no loudness
compensation when pin 7 is connected to pin 17. Pin 7 can
be connected to pin 12 to give the loudness compensated
volume characteristic as illustrated without the addition of
further external components. (Tone settings are for flat response, Cb and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing
the capaCitors Cb and Ct for a different basic response or,
by a resistor network between pins 7 and 12 for a different
threshold and slope.

The maximum boost and cut can be optimized for individual
applications by selection of the appropriate values of Ct (treble) and Cb (bass).
The tone responses are defined by the relationships:
1 + 0.00065(1 - ab)
jClJCb
Bass Response = -----~::!!...--­
O.00065ab
1 + . ro.
JCIJ"t)
Treble Response = 1 + jCIJ5500(1 - at)Ct
1 + jCIJ5500atCt
Where lib = at = 0 for maximum bass and treble boost respectively and lib = at = 1 for maximum cut.

SIGNAL HANDLING
The volume control function of the LM1036 is carried out in
two stages, controlled by the DC voltage on pin 12, to improve signal handling capability and provide a reduction of
output noise level at reduced gain. The first stage is before
the tone control processing and provides an initial 15 dB of
gain reduction, so ensuring that the tone sections are not
overdriven by large input levels when operating with a low
volume setting. Any combination of tone and volume settings may be used provided the output level does not exceed 1 Vrms, Vcc=12V (0.8 Vrms, Vcc=9V). At reduced
gain ( < - 6 dB) the input stage will overload if the input level
exceeds 1.6 Vrms, VCC=12V (1.1 Vrms, Vcc=9V). As
there is volume control on the input stages, the inputs may
be operated with a lower overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio.

For the values of Cb and Ct of 0.39 "F and 0.D1 "F as
shown in the Application Circuit, 15 dB of boost or cut is
obtained at 40 Hz and 16 kHz.
ZENER VOLTAGE
A zener voltage (pin 17=5.4V) is provided which may be
used to bias the control potentiometers. Setting a DC level
of one half of the zener voltage on the control inputs, pins 4,
9, and 14, results in the balanced gain and flat response
condition. Typical spread on the zener voltage is ± 100 mV
and this must be taken into account if control signals are
used which are not referenced to the zener voltage. If this is
the case, then they will need to be derived with similar accuracy.

1-94

E
....

Application Circuit

C)

w

....
I"'"
iii:
....
UI

,uPP.

II

0.01,.F

47k

...-'10""'....<47k

BASS CONTROL

;J;0.22,.F

C)

w

10,.F

G)

0.47 pF

LMl038N

47,.F

~

LOUDNESS
COMPENSATiON

0.47,.F

IN~

BALANCE CONTROL

Ct
O.01PF;J;

T

OUTPUT 1 47k
...- - - - -......W~-------+<47k

=~~L

;/;0.22,.F
TLlH/5142-3

Applications Information
OBTAINING MODIFIED RES~ONSE CURVES
The LM1036 is a dual DC controlled bass, treble, balance
and volume integrated circuit ideal for stereo al!dio systems.
In the various applications where the LM1036 can be used,
there may be requirements for responses different to those
of the standard application circuit given in the data sheet.
This application section details some of the simple variations possible on the standard responses, to assist the
choice of optimum characteristics for particular applications.

Figures 2 and 3 show the effect of changing the response
defining capacitors Ct and Cb to 2Ct, Cb/2 and 4Ct, Cb/4
respectively, giving increased tone control ranges. The values of the bypass capacitors may become significant and
affect the lower frequencies in the bass response curves.
20

15
10

i
Z

TONE CONTROLS

is

Summarizing the relationship given in the data sheet, basically for an increase in the tre~le cpntrol range Ct must be
increased, and for increased bass range Cb must be reduced.
'

0
-5

Iz

iil

5.4

10

4.0

5

3.4

0

2.7

-5

2.0
1.4
0.7
0.0

4.7

-10
-15

-20
20

100

500

5k

~

100

~

2.7

Ii

1.4

S ....

500
5k
FREQUENCY (Hz}

3.4

2.0

~:---

!

i

::! .:s!

-20
20

i

4.0 :!i

I.;I~

-10 10- I-~"
Coo/I 2Ct
~t:::

20k

TLlH/5142-5

FIGURE 2. Tone Characteristic (Gain vs Frequency)
20

15

5.4

4.7 ~

~~

~ r-r-;:~

""""II

i-"

~

-15

Figure 1 shows the typical tone response obtained in the
standard application circuit. (Ct=O.01 /LF, ~=O.39 /LF).
Response curves are given for various amounts of boost
and cut.
20

INCREASED CONTROL RAMIE

I- ...... ~

15

I

10

I

!

5

Z

0

is

.
!

:II

iii

5.4 ~

U.,...

4.7 ~

-15
-20

-

,~

-:-

20

Co/4 4Ct
100

i!

3.4
2.7 III

...-:: ,.~
~

4.0 ~

~

"""" ~

-5
-10

i

~~EASBI CONTROL RANBE~

f- r-.....

~.....

580

SIc:

2.0

"

ill

1.4;
0.7 ;:
D.O :3
20t

FREDUENCY (Hzl

20k

TL/H/5142-6

FRllIUENCY (Hz}

FIGURE 3. Tone Characteristic (Gain vs Frequency)

TLlH/5142-4

FIGURE 1. Tone Characteristic (Gain vs Frequency)

1-95

•

Applications Information (Continued)
Figure 4 shows the effect of changing Ct and Cb in the
opposite direction to Ct/2, 2~ respectively giving reduced
control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give
a particular emphasis to, for example, the bass control. The
particular case with Cb/2, Ct is illustrated in Figure 5.

for greater control range also has the effect of flattening the
tone control extremes and this may be utilized, with or without additional modification as outlined above, for the most
suitable tone control range and response shape.
Other Advantages of DC Controls
The DC controls make the addition of other features easy to
arrange. For example, the negative-going peaks of the output amplifiers may be detected below a certain level, and
used to bias back the bass control from a high boost condition, to prevent overloading the speaker with low frequency
components.

Restriction of Tone Control Action at High or Low Frequencies
It may be desired in some applications to level off the tone
responses above or below certain frequencies for example
to reduce high frequence noise.
This may be achieved for the treble response by including a
resistor in series with Ct. The treble boost and cut will be 3
dB less than the standard circuit when R= Xc.

LOUDNESS CONTROL
The loudness control is achieved through control of the
tone sections by the voltage applied to pin 7; therefore, the
tone and loudness functions are not independent. There is
normally 1 dB more bass than treble boost (40 Hz-16 kHz)
with loudness control in" the standard circuit. If a greater
difference is desired, it is necessary to introduce an offset
by means of Ct or Cb or by changing the nominal control
voltage ranges.

A similar effect may be obtained for the bass response by
reducing the value of the AC bypass capacitors on pins 5
(channel 1) and 16 (channel 2). The internal resistance at
these pins is 1.3 kG and the bass boost/cut will be approximately 3 dB less with Xc at this value. An example of such
modified response curves is shown in Figure 6. The input
coupling capaCitors may also modify the low frequency response.

Figure 7 shows the typical loudness curves obtained in the
standard application circuit at various volume levels
(Cb=0.39,...F).

It will be seen from Figures 2 and 3 that modifying Ct and Cb

20

I:::' ~
5

:II

0
-5
-10

!5

.

REDUCED CONTROL RANGE

10

z

20

a

15

~

3.4
..... ~I-" 2.7

~ ii?

N
2 Ct. Ct/2

-15

1.4
0.7
0.0

j

!
I

...
i!
'"
:;;:

20

100
500
FREQUENCY (Hz)

5k

-5
-10

..
,..

...... ~
~

0

-15

:s

-20

l- t- t-.

10

:II
1IIii~ 2.0 z

~ iii"
~

5.4 co
'"
4.7 r4.0 C'!i

B
5.4 z
4.7
~ 4.0 rC'!i
~i""
3.4

...!,NCREASED BASS CONTROL RANGE

15

..... ~
10-I- ~

I- t::;.~

i

~ t::= ,....~
I'§t'I-"'"

2.7
:II
2.0 z

I'

Ct./2 Ct

1.4
0.7 z
0.0

..'"

:s

-20
20

20k

100' 500
5k
.FREQUENCY (Hz)

20k

TL/H/5142-7

TLlH/5142-8

FIGURE 4. Tone Characteristic (Gain vs Frequency)

FIGURE 5. Tone Characteristic (Gain vs Frequency)

10

20 "---r-r-r~~-r~-'-'

STANDARD AI'I'l.ICATlDN CIRCUIT

15
10

'I

5

z

0
-5

li

-10

I-+-+--+-~"'i-++-I

I-H~-++-f-,-3o,t-+-l

-10
-15
- 20

~ I"'-r--.
!-2O l,. . . r-....
to....
! -30 t- ,.....
r-....
I.....

-40

. . . r--..,

-50

..
100

500

5k

20

20k

FREQUENCY (Hzl

1-"'1". 1-"""",

..... i"""io-"

/

PIN 7 CONNEC7EtI TO PIN 12

-60

L-.J-.I.......L--JL......L---'---'-...J......J

20

1"'-

100
~
FREQUENCY (Hzl

-D.39,."
Ct=D.Dl,.F

5k

20k
TL/H/5142-10

TLlH/5142-9

FIGURE 7. Loudness Compensated Volume
Characteristic

FIGURE 6. Tone Characteristic (Gain vs Frequency)

1-96

Applications Information (Continued)
Figures 8 and 9 illustrate the loudness characteristics obtained with Cb changed to Cb/2 and Cb/4 respectively, Ct
being kept at the nominal 0.01 p.F. These values naturally
modify the bass tone response as in Figures 2 and 3.

ance, this is easily done and high value resistors may be
used for minimal additional loading. It is possible to reduce
the rate of onset of control to extend the active range to
-50 dB volume control and below.
The control on pin 7 may also be divided down towards
ground bringing the control action on earlier. This is illustrated in Figure 12, With a suitable level shifting network between pins 12 and 7, the onset of loudness control and its
rate of change may be readily modified.

With pins 7 (loudness) and 12 (volume) directly connected,
loudness control starts at typically -8 dB volume, with most
of the control action complete by -30 dB.
Figures 10 and 11 show the effect of resistively offsetting
the voltage applied to pin 7 towards the control reference
voltage (pin 17). Because the control inputs are high imped10

-10

!

-20

z

~ -30

-40

10

INCREASED BASS RESPONSE

--

.........

C!./2 Ct

i-a

", ~

i'"
l"'- t-.... I'

l-

-50

-10

..... I-

r-..

I-

1-30

. / ~ i..-"

--.........

-40

./

t-....

INCREASED BASS RESPONSE

".-

.......

I-.... ...... ~ t,....-

r-... .......
.......

C!./4 Ct

-50

~

t,...../

"".

""

-60

-60

20

100

500

5k

20

20k

100

500

5k

10k

FREQUENCY (Hz)

FREQUENCY (Hz)
TUH/5142-11

TL/H/5142-12

FIGURE 8. Loudness Compensated Volume

FIGURE 9. Loudness Compensated Volume

Characteristic

Characteristic

10

10

~=:M~=T~ONOF

-10

i
i!

li

-20

r-- i"'"

.... I--.

1----0

....... .......

-30

-40
-50
-&0

i

".

5k

-....

~-

-50
-60

10k

ftN~~7
20

FREQUENCY (Hz)

--

.....1-

i'--..

.N" I ...............

c,,=O.39,.F
Ct=O.01j

g

100
3(18)
TREBLE CAlRCITOR

• Connections reversed

4

lIIEILE CONTROL

7

LOUONUS
COM_OIl

14
BASS

CONTROl.

9£O~W'/S£O~W'

II

~National

~ Semiconductor

LM 1037 Dual Four-Channel Analog Switch
General Description

Features

The LM1037 is a dual, electronically controlled, analog
switch with an internal muting facility. Anyone of four stereo
signal sources may be selected by means of four control
inputs.

•
•
•
•
•
•
•

Its features make it ideal for stereo source selection in audio
equipment and for use in a wide range of industrial, automotive, multiplexing or sampling applications.

Wide supply voltage range, 5V-28V
Low distortion, 0.04% typical
Low noise, typically 5 p.V
High input impedance
Low output impedance
TTL compatible control inputs
Very low control current

An additional pin is included to allow parallel connection of
two or more integrated circuits.

Block Diagram
(16) A
(18) B
CONTROL
INPUT
STAGES

lA (2)

(1) C

2A (4)

lB (6)
(5) y+

2B (8)
SIGNAL
INPUTS lC (11)
~~

2C (13)

__-+__....;..(1...;.2) VBIAS

.-

AND MUTE

lD (17)
20 (15)
(14) y_

2

1

MUTE

'OuWiiTs' INHIBIT
TLlH/5199-1

Order Package Number LM1037N
See NS Package N18A

1-100

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
28V
Pin 7 Input Current

Operating Temperature Range

+ 70'C
+ 150'C

- 20'C to

Storage Temperature Range
Power Dissipation (Note 1)

- 65'C to

1.3W

Lead Temp. (Soldering, 10 seconds)

260'C

5mA

Electrical Characteristics Vs=12V, TA=25'C
Parameter

Conditions

Tested
Limit (Note 7)

Typical

Supply Voltage

Design
Limit (Note 8)

Units
(Limits)

28

V(max)

Supply Voltage

5

Supply Current

VSUPPLy=12V

6.4

VSUPPLy=28V
Voltage Gain
Signal Handling (Notes 2, 6)

VSUPPLy=12V

Small,Signal Bandwidth

V(min)

8.5

mA(max)

10

14

mA(max)

0

±0.7

dB

3.0

2.8

Vrms(min)

0.1

% (max)

300

Distortion THD

kHz

0.04

VSIGNAL = 1 Vrms @ 1 kHz

Noise Voltage at Output (Note 3)

CCIRIARM RS = 00

5

20

I''v(max)

Channel Separation (Note 4)

VSIGNAL = 1 Vrms @ 1 kHz

-95

-70

dB(min)

Relative Output in Muted State

VSIGNAL = 1 Vrms

-90

@

1 kHz

-70

dB(min)

Output Impedance

10

0

Signal Input Impedance

30

MO

Logic Low Input Level

0.8

Logic High Input Level

2.0

V(min)

Logic High Input Level

VSUPPLY

V(max)

V(max)

Typical Performance Characteristics (Vs= 12V, TA = 25'C unless otherwise noted)
Supply Current va Supply
Voltage

Supply Current va
Tempereture

11

7.5

10

C

.s

i...

8
7

~

6

ill

V

9

=>

V
1/

5

/

!

7.0

I...

6.5

....

=>

V

-115

i

;; -110

..,~

r--..

az

;! -100

1il
5.5

10
20
30
SUPPLY VOLTAGE (V)

i

;; -105

~

~-100

~
~

...os

;! -95
-90
0.1

-95
0

40

Signal-to-Noise va Source
Impedance (Note 3)

.... "

~

'"

0

105

.:.

r--. !'o!o.

it 6.0
=>

3

...--

w

..... 1'-0..

~

4

-110

Signal-to-Noise vs
Temperature (Note 3)

-70

10 20 30 40 50 60 70 80
AM81ENT TEMPERATURE ('C)

0

10 20 30 40 50 60 70 80
AM81ENT TEMPERATURE ('C)

Attenuation of Unselected
Inputs va Frequency
(Note 5)

Channel Separation vs
Frequency (Note 4)
-70

I

i

.

i' -80

" "-

./

~

/'

1-90

'"

1
10
100
lk
SOURCE IMPEDANCE (kll)

10k

0.1

1

10

FREQUENCY (kHz)

if

z

J

=>

~
"'-100

:1-100
~
-110
0.01

.

~ -90

./

~

!iI!

I

~ -80

100

lk

-110
0.01

-

I
II

V

0.1
1
100
10
FREQUENCY (kHzl

lk

TUH/5199-2

1-101

~
C')

o.....

~

r---------------------------------------------------------------------------------,
Typical Performance Characteristics
Total Harmonic Distortion
vs Frequency
0.2

t--

0.15

~
;; 0.1

~

"'

o

0.01

100

lk

SUPPLY VOLTAGE = 2aV
VsIGNIL =5 Vrm.

~
;; 0.1

"

0.05
~

0.01

0.1

1

-10

100

lk

......

o

0.01

...... I-""'" l /

0.1

FREQUENCY (kHz,

FREQUENCY (kHz,

-- -

i5

I'-.

o
10

0.2

-

0.1

./

0.1

-

0.15

0.05

0.05

SUPPLY VOLTAGE =12V
VsIGNAL = 1 Vrms

0.15

~

i5

Total Harmonic Distortion
vs Frequency

Total Harmonic Distortion
vs Frequency
0.2

SUPPLY VOLTAGE=12V
VsIIlNAL=I00 mVTrns -

(Continued) (Vs= 12V, TA = 25'C unless otherwise noted)

10

100

lk

FREQUENCY (kHz,
TL/H/5199-3

Note 1: Above TA=25'C derate based on TJ max = 150'C and 6JA=90'C/W.
Note 2: The inslanteneous maximum voltage difference be1ween any 1wo Input pins of one channel is
9.6V. Voltages in excess of this level may cause increased distortion and degraded channel separation.

Signal Handling vs
Frequency (Note 6)

Note 3: Gaussian noise, monRored over a period of 50 ms per channel, wRh a CCIR finer referenced to
2 kHz, and an average-responding meter. Signal to noise ratios are referenced to tv rms input signal.

\

\

Note 4: The level of output signal of a selected undriven amplifier _ respect to the output level of a
selected driven amplifier. For test purposes, signal is applied to only one input and all other inputs are
decoupled to eliminate stray pick·up through external components. Channel separation is then defined as
the ratio of Signal levels of the 1wo output pins.

\

\

Note 5: For test purposes, signals are connected to three unselected input pins of one channel group and
all other inputs are decoupled to eliminate stray pick-up through external components.
Note 6: Supply voltage 12V; signal handling defined at 1% distortion, 1 kHz.

o

Note 7: Guaranteed and 100% production tested.

0.01

0.1

10

100

lk

FREQUENCY (kHz)

Note 8: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing
qualRy levels.

TUH/5199-4

Typical Application
CONTROL INPUTS

C'N

lA

"---++-t
~ 10
L....._+_
_----I

2A

"----+-t ~ 20

C'N

INPUTS

INPUTS

C'N

-+--1

,&...._ _ _

=

R 100 kIl1/4 watt
Cl=10pF
C2=1 pF
C3=I00pF
C'N=I"F

~IC

C3

TD PIN 7
NmOEVICE
(MUTE INHIBIT)

T
AUDIO OUTPUTS
TL/H/5199-5

1-102

.-----------------------------------------------------------------------------, r
i:

...

Truth Tables

~
LM1037
Channel selection is achieved by the application of DC voltages to the control pins.
Unselected control pins should be held low.

DC Control Pin
In HIGH State

Input Pair Switched to
Output Pins (10, 9)

A

16
18
1

(2,4)
(6,8)
(11,13)
(17,15)
(12)

B
C
D
Mute

3
None
Low switching level (VtJ "'f

!z
-5~~~~~~d-~

CUT
40 Hz OR 16 kHz

-15 V

Tone Characteristic (Gain
vs Frequency)

15 Ioo::-+--I--±:

/

-10

V14 - CONTROL VOLWIE (VI

20~~~-r;~~~-,

V

15
-5

I
o

z

\

/

/

(

\

J

BOOST
40 Hz OR 16 kHz

10

4
5
vn- CONTROL VOLllUlE (VI

20

i

1/

!.
z -12
iI -16
-28

2

!

i

-4
-8

-24

1

,

CHANNEL2? "CHANNEL 1

-20

~'
-60

Tone Control Characteristic
15

~

a

j

-60

Balance Control
Characteristic

4

Application Notes
out to facilitate this. The arrangement is shown below in
basic form.

TONE RESPONSE
The maximum boost and cut can be optimized for individual
applications by selection of the appropriate values of Ct (treble) and Cb (bass).
The tone responses are defined by the relationships:
1
Bass Response =

+ 0.00065(1

- ab)

jwCb

PIN 2

---..!.=.::.!!...--

1

Uk

Uk

+ 0.000658b
jwCb

Treble Response = 1

CHANNEL 2
OUTPUT

CHANNEL 1
OUTPUT

+ jw5500(1 - atlCt
1 + jw5500atCt

TLlH/5147-3

With a monophonic source, the emitters have the same signal and the resistor and capacitor connected between them
have no effect. With a stereo signal each transistor works in
the grounded base mode for stereo components, generating an in-phase Signal from the opposite channel. As the
normal signals are inverted at this point, the appropriate
phase-reversed cross-coupling is achieved. An effective level of coupling of 60% can be obtained using 4.7k in conjunction with the internal 6.5k emitter resistors. At low frequencies, speakers become less directional and it becomes
desirable to reduce the enhancement effect. With a 0.1 p.F
coupling capacitor, as shown, roll-off occurs below 330 Hz.
The coupling components may be varied for alternative responses.

Where ab = at = 0 for maximum bass and treble boost
respectively and 8b = at = 1 for maximum cut.
For the values of Cb and Ct of 0.39 p.F and 0.01 p.F as
shown in the Application Circuit, 15 dB of boost or cut is
obtained at 40 Hz and 16 kHz.

STEREO ENHANCEMENT
When stereo system speakers need to be closer than optimum because of equipment/cabinet limitations, an improved stereo effect can be obtained using a modest
amount of phase-reversed interchannel cross-coupling. In
the LM 1040 the input stage transistor emitters are brought

Application Circuit

47k

47k

BASS
CONTROL

VOLUME
CONTROL

STEREO
ENHANCEMENT
ON

LOUDNESS

COMPENSATION
47k

~----~~-y.,""'_'<47k

BALANCE
CONTROL

t--------~~~-------.~~k~~~L

TL/H/5147-4

1-109

•

Application Notes (Continued)
ZENER VOLTAGE
A zener voltage (pin 19=5.4V) is provided which may be
used to bias the control potentiometers. Setting a DC level
of one half of the zener voltage on the control inputs, pins 6,
11, and 16, results in the balanced gain and flat response
condition. Typical spread on the zener voltage is ± 100 mV
and this must be taken into account if control signals are
used which are not referenced to the zener voltage. If this is
the case, then they will need to be derived with similar accuracy.

TONE CONTROLS
Summarizing the relationship given in the data sheet, basically for an increase in the treble control range Ct must be
increased, and for increased bass range Cb must be reduced.
Agure 1 shows the typical tone response obtained in the
standard application circuit. (Ct=0.01 p.F, Cb=0.39 p.F).
Response curves are given for various amounts of boost
and cut.
20

LOUDNESS COMPENSATION
A simple loudness compensation may be effected by applying a DC control voltage to pin 9. This operates on the tone
control stages to produce an additional boost limited by the
maximum boost defined by Ct, and Ct. There is no loudness
compensation when pin 9 is connected to pin 19. Pin 9 can
be connected to pin 14 to give the loudness compensated
volume characteristic as illustrated without the addition of
further external components. (Tone settings are for flat response, Cb and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing
the capaCitors Cb and Ct for a different basic response or,
by a resistor network between pins 9 and 14 for a different
threshold and slope.

15
10
iii
!!.

5

0
~ -5
~

-10
-15
-20

n

STANDARD APPlICATION CIRCUIT

::--

,BASS AND TREBLE BOOST

r- ~~
.......

~

~Y'"

~r-

_~111"""

i

5.4
4.7
4.0 Ii!
;§
3.4

i

2.7 :II

I- 2.0 ili

~ ~~S~D~EB~f~
Ct.=0.39,.F
Ct=O.Ol,.F

1.4

0.7
I-' 0.0

20

100

50D
FREQUENCY (Hz)

5k

.!!...
I:

~

20k
TUH/S147-S

FIGURE 1. Tone Characteristic (Gain vs Frequency)
Figures 2 and 3 show the effect of changing the response
defining capacitors Ct and Ct, to 2Ct, Cb/2 and 4Ct, Cb/4
respectively, giving increased tone control ranges. The values of the bypass capacitors may become significant and
affect the lower frequencies in the bass response curves.

SIGNAL HANDLING
The volume control function of the LM1040 is carried out in
two stages, controlled by the DC voltage on pin 14, to improve signal handling capability and provide a reduction of
output noise level at reduced gain. The first stage is before
the tone control processing and provides an initial 15 dB of
gain reduction, so ensuring that the tone sections are not
overdriven by large input levels when operating with a low
volume setting. Any combination of tone and volume settings may be used provided the output level does not exceed 1 Vrms, Vcc=12V(0.7 Vrms, Vcc=9V). At reduced
gain « -6 dB) the input stage will overload if the input level
exceeds 1.6 Vrms, Vcc=12V (1.1 Vrms, Vcc=9V). As
there is volume control on the input stages, the inputs may
be operated with a lower overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio.

TL/H/S147-6

FIGURE 2: Tone Characteristic (Gain vs Frequency)
20
15

Applications Information
OBTAINING MODIFIED RESPONSE CURVES
The LM1040 is a dual DC controlled bass, treble, balance
and volume integrated circuit ideal for stereo audio systems.
In the various applications where the LM1040 can be used,
there may be requirements for responses different to those
of the standard application circuit given in the data sheet.
This application section details some of the simple variations possible on the standard responses, to assist the
choice of optimum characteristics for particular applications.

iz

~

,...!!I~EASED CONTRDL RANGE~ ....

bfo'""

__

~

10
5
0

~

-5
-10
-15
-20

-- -

20

-~
~

100

~~
,~

5.4 n
4.7 !i
;l
4.0 Ii!
c
3.4
2.7

r~

co

i

..,....
.

:31
2.0 z

,~

1.4 z
~ 1"--- 0.7 iii
1 ' - 0.0 :3
Ct./4 4Ct

500

5k

20k

FREQUENCY (Hz)
TLlH/S147 -7

FIGURE 3: Tone Characteristic (Gain vs Frequency)

~------------------------------------------------------~I
1-110

Applications Information

(Continued)

Figure 1# shows the effect of changing Ct and Cb in the
oPPOsite direction to Ct/2, 2Cb respectively giving reduced
control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give
a particular emphasis to, for example, the bass control. The
particular case with Cb/2, Ct is illustrated in Figure 5.

It will be seen from Figures 2 and 3 that modifying Ct and Cb
for greater control range also has the effect of flattening the
tone control extremes and this may be utilized, with or without additional modification as outlined above, for the most
suitable tone control range and response shape.
OTHER ADVANTAGES OF DC CONTROLS
The DC controls make the addition of other features easy to
arrange. For example, the negative-going peaks of the output amplifiers may be detected below a certain level, and
used to bias back the bass control from a high boost condition; to prevent overloading the speaker with low frequency
components.

R~STRICTION OF TONE CONTROL ACTION AT HIGH
OR LOW FREQUENCIES
It may be desired in some applications to level off the tone
responses above or below certain frequencies for example
to reduce high frequency noise.
This may be achieved for the treble response by including a
resistor in series with Ct. The treble boost and cut will be
3 dB less than the standard circuit when R = Xc.

LOUDNESS CONTROL
The loudness control is achieved through control of the
tone sections by the voltage applied to pin 9; therefore, the
tone and loudness functions are not independent. There is
normally 1 dB more bass than treble boost (40 Hz-16 kHz)
with loudness control in the standard circuit. If a greater
difference is desired, it is necessary to introduce an offset
by means of Ct or Cb or by changing the nominal control
voltage ranges.

A similar effect may be obtained for the bass response by
reducing the vallie of the AC bypass capacitors on pins 7
(channel 1) and 18 (channel 2). The internal resistance at
these pins is 1.3 kO and the bass boost/cut will be approximately 3 dB less with Xc at this value. An example of such
modified response curves is shown in Figure 6. The input
coupling capacitors may also modify the low frequency response.

20

i

i

L:""'

REOUCl:O CONTROL RANGE

~

5 ... I:i:I..
0

-5

;~

..... ~ iii"

~ Ii?

.....
-15
-10

.
S

15
10

Figure 7 shows the typical loudness curves obtained in the
standard application circuit at various volume levels
(Cb=0.39 fLF).

2

c..

~

CtI2

!!i

20 ..,!NCREASEO BASS CONTROL RANIE
15

co
....

10

;i

100
500
FREOUENCY (Hz)

5k

r-r--~

.... 1-

i

;

0
m -5

.'"
=

5.4 !!i
4.7 co
....
4.0 oC

~

~

~ .....

I-o::::i"'"

t:1~-~

2.7 :!i!
z
2.0 co

~

1.4 '"
z
0.7 co
0.0 ;;\

~I-t::;:;,.

=~: f-J::;~

;;\

.
S

5~~~~~~~~~~~~

!l!

:!i!
z
co

:3

-20
20

5.4
4.7
4.0
3.4
2.7
2.0
1.4
0.7
0.0

I§t'Cb/2 Ct

co

I

3.4

,.

:3

- 20 '--.J.....L......l'--.L......Jc.....J._L........l-l
20
100
500
5k
20k
FREQUENCY (Hz)

20k
TLlH/5147-8

TLlH/5147-9

FIGURE 4. Tone Characteristic (Gain vs Frequency)

FIGURE 5. Tone Characteristic (Gain vs Frequency)

_50'--.J.....L........l_L......lc.....J.~L........l-l

20

100
500
FREQUENCY (Hz)

5k

20k
TLlH/5147-11

TLlH/5147-10

FIGURE 7. Loudness Compensated
Volume Characteristic

FIGURE 6. Tone Characteristic (Gain vs Frequency)

1-111

Applications Information (Continued)
Figures 8 and 9 illustrate the loudness characteristics obtained with C!) changed to Cb/2 and ~f4 respectively, Ct
being kept at the nominal 0.01 p.F, These values naturally
modify the bass tone response as in Figures 2 and 3.

voltage (pin 19). Because the control inputs are high impedance, this is easily done and high value resistors may be
used for minimal additional loading. It is possible to reduce
the rate of on$8t of control to extend the active range to
-50 dB volume control and below.
The control on pin 9 may also be divided down towards
ground bringing the control action on earlier. This is illustrated in FJgure 12. With a suitable level shifting network between pins 14 and 9, the onset of loudness control and its
rate of change may be readily modified.

With pins 9 (loudness) and 14 (volume) directly connected,
loudness control starts at typically - 8 dB volume, with most
of the control action complete by -30 dB.

Figures 10 and 11 show the effect of resistively offsetting
the voltage applied to pin 9 towards the control reference

111

10

--- r...r...

-10

i

.......

......

1-20
z
-30

-40

INCREASED BASS RESPONSE

!MCRE! SED BASS RESPONSE

o

~
./~

.......
I'- .........
.........

14/2 Ct

-50

....

-

-10

..... 1'-

i-

1- 20 ,.... r- r... i' i,...oo"
too...
1-30

. / I-'~

I' r-..... I' 1-0.. l...;'

-40

./"

'" I'

, ....

CIo/. Ct

-50

too...

"".

./

-60

-60
20

100

500
5k
FREDUENCY (Hz'

20

2IIk

1110

500
5k
FREDUENCY (Hz,

20k
TUH/5147-13

TL/H/5147-12

FIGURE 9. Loudness Compensated Volume
Characteristic

FIGURE 8. Loudness Compensated Volume
Characteristic
10

-10

1-20
z

i

-30

-40
-50
-60

!""'r--

-.."I.' . . . .

,~

..... ~

i" ....

ft~.

20

100

=:...;.0::.::'

10

~~=:::.~a::a:

o

o

--

-10
1-20
1-30

-40

. " I-'

-

~::.::

-60

500
FREQUENCY (Hz,

......

.:~"b.

.. "

-60

_fr- r--.

20,

I ...........

100

500
FREQUENCY (Hz,

o
-10

(-20

-

~ 1-0..' t--..

r- 1-0.. ...... ~
! -30 r-.
~: ......
-40

""'""1~~

-50
-60

20

6k

2IIk

FIGURE 11. Loudness Compensated Volume
Characteristic

--

11IC=~':.ur~F

~

..... 1-

TUH/5147-15

TL/H/5147-14

FIGURE 10. Loudness Compensated Volume
Characteristic
10

..... i""f-

~ -f100

.." "".,

./

"".

./

"".

~
Co-D....
I:o-D.01"

500
5k
FREDUENCY (Hz,

2IIk
TL/H/5147-16

FIGURE 12. Loudness Compensated Volume Characteristic

1-112

Applications Information

(Continued)
USE OF THE LM1040 ABOVE AUDIO FREQUENCIES
The LM1040 has a basic response typically 1 dB down at
250 kHz (tone controls flat) and therefore by scaling Cb and
Ct. it is possible to arrange for operation over a wide fre·
quency range for possible use in wide band equalization
applications. As an example Figure 15 shows the responses
obtained centered on 10 kHz with Cb=0.039 p.F and
Ct=0.001 p.F.

When adjusted for maximum boost in the usual application
circuit. the LM·1040 cannot give additional boost from the
loudness control with reducing gain. If it is required. some
additional boost can be obtained by restricting the tone con·
trol range and modifying Ct. Cb. to compensate. A circuit
illustrating this for the case of bass boost is shown in Figure
13. The resulting responses are given in Figure 14 showing
the continuing loudness control action possible with bass
boost previously applied.

24
23

22
21
20
LM1040N

19
18
5k

17

c" =0.22 #

-;J;

47k

16

25k

15
r O . 22 #

5k

14
12

13

TOPYIEW

TUH/S147-17

FIGURE 13. Modified Application Circuit for Additional
Bass Boost with Loudness Control
10 r--r--r-..--r-r....,........,.....,....,

20
15
10

-10

i

i

I--..

V
1,\
i 5 c:.=D.~,.F
.....
V
o Co=O.DDJ,.F I '
./
i"-...
lfI -5

-20 ,.....'i'"lr;...o~+++-+1...-!

-30
-40

I-+-+-t-

-10

-50

1-+-+-+-+-+-+-++-1

-15
-20

100

500
5k
FREQUENCY (Hz)

II

MAXIMUM BASS AND TREBLE.at

N..

20k

200

1/

1\

,......,.AXIMUM lASS AND TREBLE CUT'

1
lk

5k

50k

200k

FREQUENCY (Hz)
TUH/S147 -19

TL/H/5147 -1 B

FIGURE 15. Tone Characteristic (Gain vs Frequency)

FIGURE 14. Loudness Compensated
Volume Characteristic

1·113

Applications Information (Continued)
DC CONTROL OF STEREO ENHANCEMENT AND
LOUDNESS CONTROL
The high impedance PNP base input of the loudness control
pin 9 is readily switched with a general purpose NPN transistor.
"

Figure 16 shows a possible circuit if electronic cOntrol of
these functions is required. the typical DC level at pins 3 and
22 is 7.5V (Vcc= 12V), with the input signal superimposed,
and this can be used to bias a FET switch as shown to save
components. For switching with a OV-5V signal a lowthreshhold FET is required when using a 12V supply. With
larger switching levels this is less critical.

47k
r---------....-'W'¥-""""~~47k

BASS

CONTROl

;,;O.22pf
0.47 pf
INPUT 2--1

Vee

YOWME

2N4393

CONTROL
LOUDNESS

390k

L-.~WI.-----4-- COMPENSATION

51 ON, OVDFf
BAlANCE

STEREO
ENHANCEMENT
5V ON, OY OFF

CONTROL

~OUTPUTI

47k

+---------W\,--------+~47k =~l

TL/H/5147 -20

FIGURE 16. Application Circuit with Electronic Switching

1-114

, ,TT'"1--. I

.=:"-

4~7k I)

J

r -~EG

11

-,-~

(!) r

r

en

3"

~

r r

~r" ~!~
ii
r ._. I .... All ~ 1 I ~
n
I

:::r

I

CD

3
C»
c:;"

I

o

i"

CQ

;

3

"0
15

--.

9

4.7k

!ll

12

~

<.n

24

100
4(21)

TREBI£ CAPACITOR

8
TREBI£ CONTROL

9
LOUDNESS
COMPENWIDN

ZENER REGULATED OUTPUT YOLTABE

otoun

II

0.------------------------------------------------------------------.
....
....
.... 'ZI National
::Ii
~ Semiconductor
....
iii
....
........ LM1131A/LM1131B/LM1131C
CO)

I)[]

CO)

:!I Dual Dolby® 8-Type Noise Reduction Processor
:c.... General Description
• Wide supply voltage range, 5V-20V
....
....

CO)

~

The LM1131 is a monolithic integrated circuit specifically
designed to realize the Dolby B-Type noise reduction system.
The circuit includes two completely separate noise reduction processors and will operate in both encode and decode
modes. It is ideal for stereo applications in compact equipment or for mono applications in 3-head equipment where
two processors with very closely matched internal gains are
required.

Features
• Stereo Dolby noise reduction with one IC

• Very high signal/noise ratio, 79 dB encode, 90 dB decode (CCIR/ARM)
• Very close gain matching for 3-head recorders
• Close matching to standard Dolby characteristics
• Very low temperature drift of Dolby characteristics
• High signal handling capability, > +20 dB (VS = 20V)
• FUll-wave rectifier in both channels
• Operates with both single and split supply voltages
• Excellent transient response characteristics
• Minimal input switch-on transients
• Reduced number of external components per channel
• Improved input protection

Available to licensees of Dolby Laboratories Licensing Corporation, San Francisco, from whom licensing and appJlcation information must be obtained.

Schematic Diagram (1 channel shown only)

TLlH/8858-1

1-116

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage
Operating Temperature Range
Storage Temperature Range

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
260"C
Small Outline Package
215·C
Vapor Phase (60 seconds)
Infrared (15 seconds)
220"C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

24V
- 20·C to + 70"C
-65·Cto + 150·C

Electrical Characteristics
Vs = 12V, TA = 25·C unless otherwise specified. 0 dB refers to Dolby level and is 580 mV, measured at TP1 and TP2.
Parameter

LM1131A

Conditions
Min

Supply Voltage Range

Typ

5

Supply Current

LM1131B
Max

Min

20

5

20

Typ

LM1131C
Max

20
20

Min

Typ

5

~
.....
.....
W
.....
~

!i:
.....

.....
.....
m
....
~
.....
.....
W
.....
o
W

Units
Max

20

20

V
mA

Voltage Gain
(Pins 7-10 and 14-11)
(Pins 10-9 and 11-12)

1 kHz Decode
1 kHz Decode

19.2
-0.5

19.7
0

20.2
0.5

18.7
-0.5

19.7
0

20.7
0.5

18.2
-1.0

19.7
0

21.2
1.0

dB
dB

Difference in Voltage

1 kHz Noise

-0.2

0

0.2

-0.5

0

0.5

-1.0

0

1.0

dB

-60

-90

-60

-90

-60

-90

dB

77

79
82
90
92

75.5

79
82
90
92

74

79
82
90
92

dB
dB
dB
dB

0
-16.2
-17.3
-21.7
-22.3
-30.1

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

0.2
-16.7
-17.8
-22.2
-22.8
-30.3

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

-0.5
-17.2
-18.3
-22.7
-23.3
-30.6

0.5
-15.7
-16.8
-21.2
-21.8
-29.6

Gain between Channels Reduction OFF
Crosstalk between
Channels

1 kHz,OdB

Signal/Noise Ratio
at Pins 9 and 12
Encode

(Note 1)

Decode
Encode Characteristics

Variation in Encode
Characteristics
Temperature
Voltage
Distortion
Signal Handling

Rs = 10kfi
Rs=1kfi
Rs=10kfi
Rs=1kfi
10 kHz, 0 dB
1.3 kHz, -20 dB
5kHz, -20dB
3 kHz, -30dB
5kHz, -30dB
10 kHz, -40 dB

O"C-70"C
5V-20V
1 kHz,OdB
10 kHz, 10 dB
1 kHz, Dist = 0.3%
Vs = 5V
Vs = 7V
Vs = 12V
Vs = 20V

Input Resistance

Pins 7 and 14

Output Resistance

Pins 9 and 12
Pins10and11

1.0
-15.2
-16.3
-20.7
-23.0
-29.1

<±0.5
<±0.2
0.03
0.2

14.0
45

<±0.5
<±0.2
0.03
0.2

0.1

6.5
10.5
16.0
21.0

14.0

65

80

30
30

55
55

45

1.2
-14.7
-15.8
-20.2
-20.8
-28.9

<±0.5
<±0.2
0.03
0.2

0.1

6.5
10.5
16.0
21.0

14.0

65

80

30
30

55
55

45

0.2

6.5
10.5
16.0
21.0

dB
dB
dB
dB
dB
dB

dB
dB
%
%
dB
dB
dB
dB

65

80

kfi

30
30

55
55

fi
fi

Note 1: Gaussian noise, measured over a period of 50 ms per channel, with a CCIR filter referenced to 2 kHz and an average-responding meter.

1-117

1.5
-14.2
-15.3
-19.7
-20.3
-28.6

•

....
....
....

or-----~---------------------------------------------------------------.

C')

:i.....
III
....
........
:i
....
....
....

Typical Performance Characteristics
Supply Current vs Supply Voltage
(1 kHz, 0 dB; NR ON)

Signal Handling vs Supply Voltage

22

C')

•

1

~

i22
u

C')

~

20

... ...
...
...

30
26

...

...

--

'"

J

18

~

....

fo"'"

14

~

~

fo"'"

-

......

V

...

V
12

...

10
6

8

/

10

10

12

14

IL

V

"

1/

8

20

18

16

V

V

.......

... ........

~

6

8

Supply Voltage IV)

10

12

14

16

20

18

Supply VoI1age (VI
TLlH/6858-2

Signal to Noise Ratio vs Source Impedance
Encode Mode (CCIRtARM)

Gain vs Frequency (NR OFF)
32

B2
BO

26

~18

24

P7-Pl0
(PI41'111

J18

~20

1

172

~ 16
12

III

70

8

.... 74

as

P7 P9
(PI4-PI21

4

10

100

lK
10K
Source Impedance In)

o

lOOK

0.1

1000

100

10
Frequency 1kHz)

TL/H/BB58-3

Back to Back Response Error vs Frequency and
Supply Voltage (Standard Dolby Encoder)

o

~ 6:12:2OV

+1
0
-1
+1
0

lI" 8:12:2OV

~-10

1

6:12:2OV

-40
0.1

10

20

1-+2&"C

1-30

1-+2&"C

-40
100

0 1
+7I5"C_ +1
0
O"C
-1
+1
_0: +2&:+75"C 0
-1
O"C

!

+1
0
-1
+1
0
-1

I."'" 6:12:2OV

1-30

1-20

-

+1
0
-1
+1
0:+2&:+75"C 0
-1+715°C_ +11

~-10

~IJ

l20

0: +2&: +75"C

o

;:j

lI" 6:12:2OV

Back to Back Response Error vs Frequency and
Temperature (Encode Temperature + 25"C)

10

0.1

20

J

100

Frequency 1kHz)

Frequency 1kHz)

TL/H/685B-4

1-118

E
...

Application Notes
NOISE REDUCTION SWITCH

LM1131 may operate with either single or split supply voltages.

Noise reduction OFF is normally effected by means of a
mechanical switch which open-circuits the sidechain input.

Single Supply Voltage
Pin 1 is connected to ground, pin 20 to Vs.

An alternative method which permits the control of NA OFF
by means of a DC voltage is shown in Flf/ure 1. The DC
control voltage forces the internal impedance to a minimum
value and heavily attenuates the sidechain input. When using this circuit the following points should be noted:

Pins 8 and 13 are internally generated reference voltages
set to approximately half-supply. They should be connected
together externally.

a) Signal boost in encode mode (signal cut in decode) is
reduced by increasing DC voltages on pins 3 and 18. A
voltage of approximately 3V above signal ground is adequate to achieve NA OFF.

A 220 p.F capacitor must be connected between pins 8 and
13 and ground. Device turn-on time is delayed by the rise
time of pins 8 and 13.

......
~
......E
...
w

SUPPLY VOLTAGE

w

~
r-

......a:
...
W

(')

b) Supply current may be increased significantly by high pin
3/18 forcing voltages. Thus, values for V3 and A3 should
ideally be chosen such that pin 3/18 forced voltage is
only 3V-5V greater than signal ground. Maximum permissible voltage on pin 3/18 is equal to supply voltage.

SpIlt Supply Voltages
Pin 1 is connected to the negative supply, pin 20 to the
positive supply. Pins 8 and 13 are connected to OV and no
capacitor is required. Device turn-on time is delayed only by
the rise times of the supply voltages.

c) When electrical NA switching is used in this way, NA OFF
signal level is slightly affected by the restriction that the
internal variable impedance cannot achieve zero impedance. Thus, at 10 kHz-10 dB, a residual boost in encode
(or cut in decode) of approximately 0.4 dB remains. At
low frequencies this value reduces to insignificant levels.
This is not the case for mechanical NA switching.

SIGNAL GAIN AND FILTERING
It should be noted that LM1131 has only one internal preamplifier, AB, with no provision for interconnection of a low
pass filter to remove bias or multiplex tones. In addition,
main chain gain has been reduced by 6 dB in comparison
with LM1112/LM1 011.
If a low pass filter is required it should be connected at the
input of the LM1131. Pre-adjustment of Dolby input level
may then be performed, at the input of LM1131 if required.

v+

V3

J"o

I
20

19

18

17

16

15

14

13

12

11

6

7

8

9

10

•

WI.
ON
~

D

R3

OFF

1

LMl131
2

4

3

5

J"o

v

I

J:

INPUT
10l'F
101'F+

15K

471<

270K

r

I

SIGNAL GROUND

0.33

I

SIDECHAIN liP

I

:1=0.0047
O.~

..

,;<0.047
0.1

MONITOR O/P

3.3K

--l

~
v-

vTL/H/6858-5

FIGURE 1. LM1131 Decode Processor with Electrical NR Switch (1 Channel Shown)

1-119

o
.........

.~

Test Circuit Encode Mode (components shown for channel 1 only)
v+

:Ii
.::I

.....
m
....

....
....

C')

!l......
....

111( .

........

C')

!l

20

r
I
I

I

I
I
I
lov
I

I
I

Note 1: Where 'not otherwise specified component tolerances are
±1.0%
.

L,

Note 2: For LM1131AN use 2%
components lor 0304, R303, R305.
(5% components may cause errors
up to ± 0.3 dB).

TLlH/6658-6

Connection Diagram
Dual-In-Llne and Small Outline Packages

:II POSITIVE SUPPLY

NEGATIVE SUPPLY
DECOUPLING

DECOUPUNG

RECTIFIER OUTPUT
VARIABLE IMPEDANCE
CONTROL
AMPLIFIER D
~DBACK DECOUPUNG
SIDECHAIN INPUT
AMPLIFIER AB
INPUT
SIGNAL GROUND
AMPLIFIER EK
OUTPUT

RECTIFIER OUTPUT
4

.-

N

VARIABLE IMPEDANCE
CONTROL

&

....I

....I

W

AMPLIFIER D

•

Z
Z

Z
Z

«
:I:

SIDECHAIN INPUT

7

•
•

W

«
:I:
U

~EDBACKDECOUPUNG

AMPUFIERAB
INPUT

U

SIGNAL GROUND
12 AMPUFIEREK

OUTPUT
II

MONITOR OUTPUT 10

MONITOR OUTPUT
TUH/6658-7

Order Number LM1131AN, LM1131BN, LM1131CM or LM1131CN
See NS Package Number M20B or N20A

1-120

r------------------------------------------------------------------------,~

~

........
....

i:

National

PRELIMINARY [ ] [ ]

~ Semiconductor

U'I

LM1151
Dolby® B-Type Noise Reduction System
General Description

Features

The LM11151 is a two-channel encode/decode switchable
Dolby B-type noise reduction processor.

•
•
•
•
•

The circuit includes two completely separate noise reduction processors and will operate in both encode and decode
modes.
Electronic switching simplifies switching from record to playback modes of operation and turn on/off of noise reduction.

Minimum number of external components
Electronic NR ON/OFF and REC/PB switching
Small surface mount package
Two channel processors on one chip
Operates with both single and split supply voltages

Key Specifications
• Supply Voltage Range
• LINE OUT Level
• Signal Handling

Applications
• Compact stereo audio equipment
• Dubbing cassette decks

6.5V to 15V
387.5 mV (-6 dBm)
;?;+14 dB

Block Diagram and Typical Application
CI2

CI4
4.7 J'F

I J'F

~~~r+~------------,

REC/PB

r---------------+~L....,.. LINE
""'" OUT

II
ATTENUATOR 3

ATTENUATOR 3

REC~

IN

-..r-,

+

L..-_+.... L....,.. REC
""'" OUT
C25

C21

4.7 J'F

I J'F

-+__""

PB ~I-+_ _ _
IN -..r-,
C22

L..-_ _ _ _ _ _ _ _ _ _ _ _ _
+... L....,.. LINE

ON/Off

""'" OUT
C24

4.7 J'f

I J'F

TUH/II439-1

1-121

~National

~ Semiconductor

LM1875 20 Watt Power Audio Amplifier
General Description

Features

The LM1875 is a monolithic power amplifier offering very
low distortion and high quality performance for consumer
audio applications.

•
•
•
•
•
•
•
•
•
•
•

The LM1875 delivers 20 watts into a 40 or 80 load on
± 25Vsupplies. Using an 80 load and ± 30V supplies, over
30 watts of power may be delivered. The amplifier is designed to operate with a minimum of external components.
Device overload protection consists of both internal current
limit and thermal shutdown.
The LM1875 Clesign takes advantage of advanced circuit
techniques and proceSSing to achieve extremely low distortion levels even at high output power levels. Other outstanding features include high gain, fast slew rate and a wide
power bandwidth, large output voltage swing, high current
capability, and a very wide supply range. The amplifier is
internally compensated and stable for gains of 10 or greater.

Connection Diagram

Up to 30 watts output power
Avo typically 90 dB
Low distortion: 0.015%,1 kHz, 20 W
Wide power bandwidth: 70 kHz
Protection for AC and DC short circuits to ground
Thermal protection with parole circuit
High current capability: 4A
Wide supply range 1SV-SOV
Internal output protection diodes
94 dB ripple rejection
Plastic power package TO-220

Applications
•
•
•
•
•

High performance audio systems
Bridge amplifiers
Stereo phonographs
Servo amplifiers
Instrument systems

Typical Applications
+Vcc:

r

Cl
2.2""

VJN

::~

C3

O.1""T
'='

HI

1M

+IN

TUH/5030-1

Front View

-YEE-+-""I
C4

O.I""T
'='14
2011

ea

![ioo,.F
'='

Order Number LM1875T
See NS Package Number T05S

TUH/5030-2

1-122

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

Storage Temperature

- 65'C to

+ 15O'C

Junction Temperature

150'C

Lead Temperature (Soldering, 10 seconds)

260'C

60V

Input Voltage

-VEE to Vee

Electrical Characteristics
Vee=

+ 25V,

-VEE= -25V, TAMBIENT=25'C, RL =80, Av=20 (26 dB), fo= 1 kHz, unless otherwise specified.

Parameter

Typical

Tested Umlts

Units

Supply Current

POUT = OW

Conditions

70

100

mA

Output Power (Note 1)

THD=1%

25

THD(Note 1)

POUT=20W, 10= 1 kHz
POUT=20W, 10=20 kHz
POUT=20W, RL =40,10 =1 kHz
POUT=20W, RL =40,10 =20 kHz

Offset Voltage
Input Bias Current
Input Offset Current
Gain-Bandwidth Product

W

0.6

%
%
%
%

±1

±15

mV

±0.2

±2

,.,.A

0

±0.5

0.015
0.05
0.022
0.07

fo=20kHz

5.5

Open Loop Gain

DC

90

PSRR

Vee, 1 kHz,1 Vrms
VEE, 1 kHz, 1 Vrms

95
83

Max Slew Rate

20W, 80, 70 kHz BW

8

Current Limit

VOUT = VSUPPLY -10V

4

Equivalent Input NOise Voltage

Rs=6000, CCIR

3

0.4

/LA
MHz
dB

52
52

dB
dB
V/,.,.s

3

A
,.,.Vrms

Note 1: Assumes the use of a heal sink having a thermal resistance of I'C/W and no insulator wHh an ambient temperature of 25'C. Because the output limiting
circuHry has a negative temperature coefficient, the maximum output power delivered to a 40 load may be slightly reduced when the tab tempereture exceeds
55'C.

Typical Applications

(Continued)
Typical Single Supply Operation
HI
22k

-:b
-

Cl

H2
22k
.J!.C2
T'0J.'F

~pr ~
HC
1M

C4
Vee 0,1 ""

!~

~~OOJ.'F

::k
1

r.:--.... 5

":'
4

LM1875

---1

H7
1

;/3

C5- ....

C6

~1-

0.22""T

C3
10 J.'F

p:+

H5
10k

-=:F H6
200k

TlIH/5030-3

1-123

•

,... ,------------------------------------------------------------------------------------------,
~

CD
....

::::E

Typical Performance Characteristics

...I

THD vs Power Output

Power Output vs Supply
Voltage

THD vs Frequency

1.0

35

0.1

Vs =U5V
0JI9
Po = lOW
0JI8

:t

g

om
g

0.It:;;

eRL

=

"

j!;

~ e'~I1I1~
0.01
0.1

o.os

\.

D.D3
0.D2

r-.

I 111111

Q.06

0J)4

1\.44 I-- 'r-t

r-...

RL = l1.li

'"

0.01

1.0

o

POWER OU1P\JT (W)

Il!

10
;

051015202530
SUPPLY VOLTAGE INTERFACE = I'C/We
See Application Hints.

Power Dissipation vs
Power Output

.

~--

-~-

--t---

30
45

g

~
!Ii
~

40
35
30
25
20

Vs =:l3OV

-- - --

1

~-

--

0
0

-

45

Vs =

=

I

~

III
Il!

lit. = 44

fo=lkHz

30

lit. =811

.... f- ...

fo= 1kHz

~ ......

30

Vs

D:

nov

10 15 20 25
POWER OUTPUT (W)

15
10

/.

r/

""

~ =;s=!15V

o
o

30

Vs =

=~~,.rI80

15,

135

W

80

~
~

Ol--+-HH~~~~~~: ~

-51-+-HH~~~++''Iil'IOtH-45 ~
-101-+-1-H+t+f!-++++*Ifll-8O
-151-+-HH~~~++~I\I-I35
~

~80

1M

F-

!52OD

i
~

.....

""

-6

30

-25-20-15-10 -5 0 5 10 15 20 25
OUTPUT VOLTAGE (V)

..... ~700c

!ZiO
~

~

\

10--

Input Bias Current
vs Supply Voltage

30D

~::~

25
20

, ....

1\

nov I-e---

10 15 20 25
POWER OUTPUT (W)

\

L.. f- .....

= t30V

Vs = t25V

Open Loop Gain and
Phase vs Frequency

lOOk

lOUT VS VourCurrent Llmltl
Safe Operating Area Boundary
6

g40
35

..". I ' Vs = :l25V

I ,.. "'Ys t15~
15
10
5

Power Dissipation vs
Power Output
30

130

.... ~r---. ....
=
r- rTA

OOC-

100
30

o

051015202530
SUPPLY VOlTAGE (tV)

10M

FREQUENCY -

1A1L ... ClfHII FDILP.c.IOAIlD

~

10

11

luIHI1TII.J I~

ID.I

31 41

..

ii
3

Ii

10

10 10 10 10

;

i§

i...

V~I~LE ~ OJ :V~

VRI"LE·8.5V~

"BYPASS' •
CI.· ••I.F
_
VRIPPLE - I v ....

12

14

10

vo· ...Vnns
AV-.

t-1~7Iil~l.il

40 L..LW1IIL..J....................
10
110
It
Ilk

..
.~
...

~
iii

~

I-'

~

ZIII

"'" --

j..--

z

!:!
E

a:

c

Ii

1.1

C

...'"c

~

....

e

a

0.1

0.11
II

1.5

110

.OWER OUT'UT CWICHANNELI

Power Dissipation (W)
Both Channels Operating
8

1\ -

...... ""'2OV L14Dl1THO -

I

7 T

A/

IN

3lITHO

~1zY"

•o

II

101

It
Ilk
FREQUENCY 1Hz)

L

RL -an

10

11:

§

....!1
..~

I.

Output Swing vs Supply
Voltage

VS'20V

..
i
..~

~

I'

&0

....

~

41

~

>

20

a

1111

.OWER OUTPUT CW/CHANNELl

0.01

I<

II

100

/. ....IIV

~~4V

10k
It
FREQUENCY 1Hz)

1.1

Open Loop Gain vs
Frequency

an
2~V

Total Harmonic Distortion
vs Frequency

la

..Iii
..
~
..I.
'"
i

I'"

It
10k
FREQUENCY 1Hz)

is

z

;::
a:

&ID

a

10

Total Harmonic Distortion
vs Frequency

I.

llllIIll

4D

IlIIt

is

C

~

c:~~I~l~F

51

10

>- 411

CBYPASS' &i~F'
VCC'IV

FREQUENCY 1Hz)

.!

5

Channel Separation (Referred
to the Output) vs Frequency

I I-++Ill~~~~

18

1m

C

10k
FREOUENCY 1Hz)

80

Average Supply Current vs
POUT

a:

II

I-I-.j.jjjlr=ffilll~

70

SUPPLY VOLTAGE IV)

.

20

i

~

-

f'l20 Hz
Ay-5D

....~

a:

10 r-rmmr-riTITllllrT

'j".

II

~

H

iii

Channel Separation (Referred
to the Output) vs Frequency

.QI8E~

~VviRI"LE -I V~

50
40

IDB
FREQUENCY 1Hz)

Power Supply Rejection Ratio
(Referred to the Output) vs
Supply Voltage
1

II

;$
a:

3D

TA - lIMllENT TEMPERATURE rc)

10

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

V
,
,

Ilk
I'"
FREQUENCY 1Hz)

1M

~

L'
a

It

V

IZ

a

5

II

II

ZI

II

SUPPLY VOLTAIE IV)
TLlH17913-3

1-130

Typical Applications
Stereo Phonograph Amplifier with Bass Tone Control

Slk

510k

1?r+r
":'

I
I

":'

I
I
I

STEREO
CERAMIC
CARTRIOGE

I

l

iJ

L

II

51k

+

T

'OhF
TUH17913-4

Frequency Response of Bass Tone Control
;

Vs

65

....CI

~

Inverting Unity Gain Amplifier

MAXIMUM
BOOST

;;;;;;
55

......
z

45

::

35

- ~ ~ESPONSE

lOOk

CI

TONE.\,
CONTROL FLAT

...:;!
c

~

25

>

15

CI

----J ~-+--~

1/
- -

CD

...

0.11'1'

"7
20

~

.......

lOOk

IDle

/MAXIMUM

-~~~PONSE
1

sa 100 200 500 lk 2k

&II 10k 2ak

FREQUENCY (Hz)
TL/H/7913-5
TUH/7913-6

1·131

Typical Applications (Continued)
Stereo AmplIfIer wIth AV = 200

TLlH17913-7

Non-InvertIng Amplifier Using Spllt,Supply
Zk

TypIcal SpIlt Supply

11M

TLlH/7913-9

TLlH17913-8

1·132

r-------------------------------------------------------------------------,

~National

~ Semiconductor

r

iii:
....
I....

DYNAMIC NOISE REDUCTION svmM

LM1894 Dynamic Noise Reduction System DNR®
• Compatible with all prerecorded tapes and FM
• 10 dB effective tape noise reduction CCIA/ AAM
weighted
• Wide supply range, 4.5V to 18V
• 1 Vrms input overload

General Description
The LM 1894 is a stereo noise reduction circuit for use with
audio playback systems. The DNA system is non-complementary, meaning it does not require encoded source material. The system is compatible with virtually all prerecorded
tapes and FM broadcasts. Psychoacoustic masking, and an
adaptive bandwidth scheme allow the DNA to achieve 10
dB of noise reduction. DNA can save circuit board space
and cost because of the few additional components required.

Applications
•
•
•
•
•

Features

Automotive radio/tape players
Compact portable tape players
Quality HI-FI tape systems
VCA playback noise reduction
Video disc playback noise reduction

• Non-complementary noise reduction, "single ended"
• Low cost external components, no critical matching

Typical Application
Cl1
I.F

+
CD
D.D41.F

C13

I.F

C12
0.0033 "F

+

LEFT
INPUT

13

LEFT
OUTPUT
TO VOLUME
CONTROL AND
POWER AMPLIFIERS

FROM TAPE
PREAMP OR FM
RIGHT
INPUT

*

RIGHT
OUTPUT

5~~.F C& ':'
Rp

D.DD1~

C3

0.0033 ,.F

*R2
C4

I.F

+
'RI + R2

=I

kfitotal.

See Application Hints.

TLIHI7918-1

FIGURE 1. Component Hook-Up for Stereo DNR System
Order Number LM1894M or LM1894N
See NS Package Number M14A or N14A

1-133

III

Absolute Maximum Ratings

,.

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Supply Voltage

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)

20V

Input Voltage Range, Vpk

Vst2
O·Cto +70·C

Operating Temperature (Note 1)
Storage Temperature

26O"C

Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215·C
220·C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

-65·C to + 1500C

Electrical Characteristics
Vs

=

8V, T A

=

25·C, VIN

=

300 mV at 1 kHz, circuit shown in Figure 1 unless otherwise specified

Parameter

Conditions

Operating Supply Range
Supply Current

Vs

=

Min

Typ

Max

Units

4.5

8

18

V

17

30

rnA

-0.9

-1

-1.1

VIV

3.7

4.0

4.3

V

1.0

dB

8V

MAIN SIGNAL PATH
Voltage Gain

DC Ground Pin 9, Note 2

DC Output Voltage
Channel Balance

DC Ground Pin 9

-1.0

Minimum Balance

AC Ground Pin 9 with 0.1 ,...F
Capacitor, Note 2

675

965

1400

Hz

Maximum Bandwidth

DC Ground Pin 9, Note 2

27

34

46

kHz

Effective Noise Reduction

CCIRt ARM Weighted, Note 3

-10

-14

dB

Total Harmonic Distortion

DC Ground Pin 9

0.05

0.1

%

Input Headroom

Maximum VIN for 3% THO
AC Ground Pin 9

Output Headroom

Maximum VOUT for 3% THO
DC Ground Pin 9

Signal to Noise

BW = 20 Hz-20 kHz, re 300 mV
AC Ground Pin 9
DC Ground Pin 9
CCIRtARM Weighted re 300 mV
Note 4
AC Ground Pin 9
DC Ground Pin 9
CCIR Peak, re 300 mV, Note 5
AC Ground Pin 9
DC Ground Pin 9

82
70

1.0

Vrms

Vs - 1.5

Vp-p

79

77

dB
dB

88
76

dB
dB

77

dB
dB

64

Input Impedance

Pin 2 and Pin 13

14

20

Channel Separation

DC Ground Pin 9

-50

-70

dB

Power Supply Rejection

C14 = 100,...F,
VRIPPLE = 500 mVrms,
f = 1 kHz

-40

-56

dB

Output DC Shift

Reference DVM to Pin 14 and
Measuree Output DC Shift from
Minimum to Maximum Bandwidth, Note 6.

1-134

4.0

26

20

kO

mV

...r-

iii:

Electrical Characteristics
Vs = av, TA = 25"C, VIN = 300 mVat 1 kHz, circuit shown in Figure 1 unless otherwise specified (Continued)

I

Parameter
CONTROL SIGNAL PATH

Conditions

Min

I

Typ

I

I

i

Max

Units

I

Summing Amplifier Voltage Gain

Both Channels Driven

0.9

1

1.1

VIV

Gain Amplifier Input Impedance
Voltage Gain

Pin 6
Pin 6 to Pin a

24
21.5

30
24

39
26.5

kO
VIV

Peak Detector Input Impedance

Pin 9

560

700

840

0

Voltage Gain

Pin 9 to Pin 10

30

33

36

VIV

Attack Time

Measured to 900/0 of Final Value
with 10kHz Tone Burst
Measured to 900/0 of Final Value
with 10kHz Tone Burst
Minimum Bandwidth to Maximum
Bandwidth

300

500

700

p.s

45

60

75

ms

3.8

V

Decay Time
DC Voltage Range

1.1

Note 1: For operation In ambient temperature above 25'C. the device must be derated based on a 150'C maximum junction temperalure and a thermal resiS1ance
of 1) 8O'CIW junctton to ambient for the dual-in-Une package. and 2) 105'CtW junction to ambient for the smaU outUne pacl

4G

so

;:

MlllMUIIBW

::

50

21

I

C14= IIDpF

10

VIN-tV.....

10

lID

SU"LYVOLTAGE IVI

THD VB F,.quency

10

FULL IMDWlDTH

J

Vo!J ..

0

.

g

Hz r-:
CONTROL PATH
stONAL AT PIN B-2mV
5~.

>

UI

I

-411
21

&I I . ZID SID I. 2Ir

FREDUENCY (HzI

Ik 10k 2Ik

.1HZ

I

I,I klfz/I, 6\
'''/'

-20

-3D

I
I

r-- I
V'Ni~"r
21

TiHzI

10 100 2DD 5DD Ik 2k
FREQUENCY IHzI

1=

laD
Ik
FREQUENCY (HzI

10k

Gain of Control Path
VB Frequency (with
10 kHz FM Pilot Filter)

5l~l~~~""

-10

iD
3

....

r.I

10

10

V.I-··Y

~~

J.

0

11.

1k

II

~

ilL

;r r.t.

FREQUENCY (llzi

8.11

..i!:

Hi!

rCI•

- 3 dB Bandwidth
Frequency and
Control Signal

g ••

;:rrt:;,.!.v....

20

VB

l.1li

~

IRs'1Il

t

0:

•

I
I

Power Supply Rejection
Ratio (Referred to the
Output) VB Frequency

II

V-

II

4

Channel Separation
(Referred to the Output)
vs Frequency

\

r

\

5k I . 20k

iD
3

'"~

...'"
....
~

f.I(

50

4D

30

20

!aJHOUT
1111kHz
PILOT
FILTER

;00

u

..
~

10 f-D-

-10
-211

100

Ik

18k

lOOk

FREQUENCY (HzI
TL/H17918-2

1-135

Typical Performance Characteristics

(Continued)

Main Signal Path
Bandwidth vs
Voltage Control
21

r-

Peak Detector Response

fII

fff-

12

ff-

D

lID

It
Ilk
BANDWIDTH (Hz!

IOIt
P~K~~--~~--~~~~~~~~~

TL/H/7918-3

DETECTOR '---'--_ ~
OUWUT~~--~~--~~~~~~--~~

TIME: 20 ms/DIV

TL/H17918-4

Output Response

INPUT I--+---j.

DNR

OUWUT 1--1--+

TIME: 20 ms/DIV

TL/H17918-5

External Component Guide (Figure 1)
Component
C1

C2,C13

C14

C3,C12

Value
0.1 p.F100 p.F

1 p.F

25 p.F100 p.F
0.0033 p.F

Purpose

Component Value
C4, C11
1 p.F

May be part of power
supply, or may be added to suppress power
supply OSCillation.
Blocks DC, pin 2 and
pin 13 are at DC potential of Vs/2. C2,
C13 form a low frequency pole with 20k
RIN·
1
fL =
2'ITC2R'N
Improves power supply rejection ..
Forms integrator with
internal gm block and
op amp. Sets bandwidth conversion gain
01 33 Hzl p.A of gm
current.

1-136

C5

0.1 p.F

C6

0.001 p.F

ca

0.1 p.F

Purpose
Output coupling capacitor. Output
is at DC potential 01 Vs/2.
Works with R1 and R2 to attenuate low frequency transients
which could disturb control path
operation.
1
15 = 2'IT C5 (R1 + R2) = 1.6 kHz
Works with input resistance 01 pin
. 6 to lorm part 01 control path frequency weighting.
1
fS = 2 C6 R
= 5.3 kHz
'IT
1pINS
Combined with La and CL forms
19 kHz filter for FM pilot. This is
only required in FM applications
(Note 1).

peak detector input determine the frequency weighting as
shown in the typical performance curves. The 1 p.F capacitor at pin 10, in conjunction with internal resistors, sets the
attack and decay times. The voltage is converted into a
proportional current which is fed into the gm blocks. The
bandwidth sensitivity to gm current is 33 Hz/ p.A. In FM
stereo applications at 19 kHz pilot filter is inserted between
pin 8 and pin 9 as shown in Figure ,.

External Component Guide (Figure 1)
(Continued)
Component
L8,CL

Value
4.7mH,
0.015 p.F

C9

0.047 p.F

Purpose
Forms 19 kHz filter for FM pilot. L8 is Toko coil CAN1A185HM' (Note 1).
Works with input resistance
of pin 9 to form part of control
path frequency weighting.
1
f9 = 2 C9 R
= 4.8 kHz
PINg

'IT

C10

1 p.F

Set attack and decay time of
peak detector.

R1, R2

1 kn

Sensitivity resistors set the
noise threshold. Reducing attentuation causes larger signals to be peak detected and
larger bandwidth in main signal path. Total value of R1 +
R2 should equal 1 kn.
Forms RC roll-off with C8.
This is only required in FM
applications.

R8

100n

Figure 3 is an interesting curve and deserves some discussion. Although the output of the DNR system is a linear
function of input Signal, the -3 dB bandwidth is not. This is
due to the non-linear nature of the control path. The DNR
system has a uniform frequency response, but looking at
the -3 dB bandwidth on a steady state basis with a Single
frequency input can be misleading. It must be remembered
that a single input frequency can only give a single -3 dB
bandwidth and the roll-off from this point must be a smooth
-6 dB/oct.

A more accurate evaluation of the frequency response can
be seen in Figure 4. In this case the main signal path is
frequency swept, while the control path has a constant frequency applied. It can be seen that different control path
frequencies each give a distinctive gain roll-off.
Psychoacoustic Basics

• Toko America Inc.• 1250 Feehanville Drive. Mt. Prospect IL 60056

The dynamic noise reduction system is a low pass filter that
has a variable bandwidth of 1 kHz to 30 kHz, dependent on
music spectrum. The DNR system operates on three principles of psychoacoustics.
1. White noise can mask pure tones. The total noise energy
required to mask a pure tone must equal the energy of the
tone itself. Within certain limits, the wider the band of masking noise about the tone, the lower the noise amplitude
need be. As long as the total energy of the noise is equal to
or greater than the energy of the tone, the tone will be inaudible. This principle may be turned around; when music is
present, it is capable of masking noise in the same bandwidth.

Note 1: When FM applications are not required. pin B and pin 9 hook-up as
follows:

C9
'047~F

__

~
9

8

LM1894

I

TUHI791B-6

Circuit Operation
The LM1894 has two signal paths, a main signal path and a
bandwidth control path. The main path is an audio low pass
filter comprised of a gm block with a variable current, and an
op amp configured as an integrator. As seen in Figure 2, DC
feedback constrains the low frequency gain to Av = -1.
Above the cutoff frequency of the filter, the output decreases at -6 dB/oct due to the action of the 0.0033 p.F capacitor.

2. The ear cannot detect distortion for less than 1 ms. On a
transient basis, if distortion occurs in less than 1 ms, the ear
acts as an integrator and is unable to detect it. Because of
this, signals of sufficient energy to mask noise open bandwidth to 90% of the maximum value in less than 1 ms. Reducing the bandwidth to within 10% of its minimum value is
done in about 60 ms: long enough to allow the ambience of
the music to pass through, but not so long as to allow the
noise floor to become audible.

The purpose of the control paths is to generate a bandwidth
control signal which replicates the ear's sensitivity to noise
in the presence of a tone. A single control path is used for
both channels to keep the stereo image from wandering.
ThiS is done by adding the right and left channels together
in the summing amplifier of Figure 2. The R1, R2 resistor
divider adjusts the incoming noise level to open slightly the
bandwidth of the low pass filter. Control path gain is about
60 dB and is set by the gain amplifier and peak detector
gain. This large gain is needed to ensure the low pass filter
bandwidth can be opened by very low noise floors. The capaCitors between the summing amplifier output and the

3. Reducing the audio bandwidth reduces the audibility of
noise. Audibility of noise is dependent on noise spectrum, or
how the noise energy is distributed with frequency. Depending on the tape and the recorder equalization, tape noise
spectrum may be slightly rolled off with frequency on a per
octave basis. The ear sensitivity on the other hand greatly
increases between 2 kHz and 10 kHz. Noise in this region is
extremely audible. The DNR system low pass filters this
noise. Low frequency music will not appreciably open the
DNR bandwidth, thus 2 kHz to 20 kHz noise is not heard.

1-137

•

~r-----------------------------------------------------------------,

I....

:i

Block Diagram
CHZ 10

CHZ OUTPUT

_____ !!....._

CHI OUTPUT

CHIlO

11

V+

---.1-1

ZOII

I

. -_ _;-~ZIIII~,

~.~e-~2~0II~~____+--o~~~T

I
I
I
I
I
I
I
I
I

BYP~~~~---~~-+--~~----------------~---1--~

I

I

31k
I.ZVt-""'f'v-.,

I
I
I

II

7110

I

L ____ _
7

5
!AMP
OUTPUT

GAIN AMP
INPUT

GAIN AMP
OUTPUT

PEAK
DETECTOR
INPUT

PEAK
DETECTOR
OUTPUT

_J

GND

TLlH17918-7

FIGURE 2
21
I.

I
-II

..

-2.
-30
~ -4G

I I I
VIN-·"'V

11I2!Y
31mV

I
"

..

;;;

10 ..V
311V

-a

~ -21

~

-81

I--t-H-IH

-30

-7' :~:~ :'klll FILTER-

I-4G~~~~~-L~~~

-H

20

-I' I--+--"H=iH--PY-""~.1

3

58 III 200 500 ,. 2k
fRE~UENCY

20

5k 10k 20k

50 III 200 l1li Ik 2k

5k 10k 2Ik

FREOUENCY (Hz'

(III'

TLlH17919-8

TLlH/7918-9

FIGURE 4. -3 dB Bandwidth V8
Frequency and Control Signal

FIGURE 3. Output vs Frequency

Application Hints
The DNR system should always be placed before tone and
volume controls as shown in FlfJure 1. This is because any
adjustment of these controls would alter the noise floor
seen by the DNR control path. The sensitivity resistors R 1
and R2 may need to be switched with the input selector,
depending on the noise floors of different sources, i.e., tape,
FM, phono. To determine the value of R1 and R2 in a tape
system for instance; apply tape noise (no program material)
and adjust the ratio of R 1 and R2 to open slightly the bandwidth of the main signal path. This can easily be done by
viewing the capacitor voltage of pin 10 with an oscilloscope,
or by using the circuit of FlfJure 5. This circuit gives an LED
display of the voltage on the peak detector capaCitor. Adjust
the values of R1 and R2 (their sum is always 1 kO) to light
the LEOs of pin 1 and pin 18. The LED bar graph does not
indicate signal level, but rather instantaneous bandwidth of
the two filters; it should not be used as a signal-level indica-

tor. For greater flexibility in setting the bandwidth sensitivity,
R1 and R2 could be replaced by a 1 kO potentiometer.
To change the minimum and maximum value of bandwidth,
the integrating capacitors, C3 and C12, can be scaled up or
down. Since the bandwidth is inversely proportional to the
capaCitance, changing this 0.0039 ,...F capacitor to
0.0033 ,...F will change the typical bandwidth from 965 Hz34 kHz to 1.1 kHz-40 kHz. With C3 and C12 set at 0.0033
,...F, the maximum bandwidth is typically 34 kHz. A double
pole double throw switch can be used to completely bypass
DNA.
The capacitor on pin 10 in conjunction with internal resistors
sets the attack and decay times. The attack time can be
altered by changing the size of C10. Decay times can be
decreased by paralleling a resistor with C10, and increased
by increasing the value of C10.

1-138

r-----------------------------------------------------------------------------,
Application Hints (Continued)
When measuring the amount of noise reduction of the DNR
system, the frequency response of the cassette should be
flat to 10 kHz. The CCIR weighting network has substantial
gain to 8 kHz and any additional roll-off in the cassette player will reduce the benefits of DNR noise reduction. A typical

signal-to-noise measurement circuit is shown in F/{Jure 6.
The DNR system should be switched from maximum bandwidth to nominal bandwidth with tape noise as a signal
source. The reduction in measured noise is the signal-tonoise ratio improvement.

~

....CD

!I:

~

~-t--~--~~--~----~--~~--~----._--~~--~----._-~=8V
O.II'F

r
17

16

15

14

13

LM3915

4

lk

FROM PIN 10"-_ _ _ _ _ _ _ _ _ _ _ _1-_......
IN LM1894"

430
910

TL/H17918-10

FIGURE 5. Bar Graph Display of Peak Detector Voltage

TONE AND

CASSETTE

VOLUME

CCIR
WEIGHTING
FILTER

II

AVERAGE
RESPONDING
METER
TUH/7918-11

FIGURE 6. Technique for Measuring SIN Improvement of the DNR System

1-139

Application Hints (Continued)
FOR FURTHER READING

Noise Masking

Tape Noise Levels

3. "Cassette vs Elcaset vs Open Reel", Toole, Audioscene
Canada, April 1978.

1. "Masking and Discrimination", Bos and De Boer, JAE8,
Volume 39, #4,1966.
2. "The Masking of Pure Tones and Speech by White
Noise", Hawkins and Stevens, JAE8, Volume 22, #1,1950.
3. "Sound System Engineering", Davis Howard W. Sams
and Co.
4. "High Quality Sound Reproduction", Moir, Chapman Hall,
1960.

4. "CCIR/ARM: A Practical Noise Measurement Method",
Dolby, Robinson, Gundry, JAES, 1978.

5. "Speech and Hearing in Communication", Fletcher, Van
Nostrand, 1953.

1. "A Wide Range Dynamic Noise Reduction System",
Blackmer, 'dB'Magazine, August-September 1972, Volume
6, #8.
2. "Dolby B-Type Noise Reduction System", Berkowitz and
Gundry, SertJournal, May-June 1974, Volume 8.

Printed Circuit Layout
DNR Component Diagram

VOUTI

0----4

TlIH/7918-12

1-140

~Nattonal

~ Sernlcorduclor

LM 1896/LM2896 Dual Power Audio Amplifier
General Description

Features

The LM1896 is a high performance 6V stereo power amplifier designed to deliver 1 wattl channel into 40 or 2 watts
bridged monaural into 80. Utilizing a unique patented compensation scheme, the LM1896 is ideal for sensitive AM
radio applications. This new circuit technique exhibits lower
wideband noise, lower distortion, and less AM radiation than
conventional designs. The amplifier's wide supply range
(3V-9V) is ideal for battery operation. For higher supplies
(Vs > 9V) the LM2896 is available in an 11-lead single-inline package. The LM2896 package has been redeSigned,
resulting in the slightly degraded thermal characteristics
shown in the figure Device Dissipation vs Ambient Tempera-

•
•
•
•
•
•
•
•
•

ture.

• Compact AM-FM radios
• Stereo tape recorders and players
• High power portable stereos

Low AM radiation
Low noise
3V, 40, stereo Po = 250 mW
Wide supply operation 3V-15V (LM2B96)
Low distortion
No turn on "pop"
Adjustable voltage gain and bandwidth
Smooth waveform Clipping
Po = 9W bridged, LM2B96

Applications

Typical Applications
..,........- -. .O+Ys

I&DpF

II
TD.IPF

":'

(
YOUT

Ra

1_

+Vs

an

SPEAKER

\

Zt

+

laPF

T

&DpF
TD.IPF
TL/H/7920- I

FIGURE 1. LM2896 in Bridge Configuration (Av = 400, BW = 20 kHz)
Order Number LM1896N
Order Number LM2896P
See NS Package Number N14A
See NS Package Number P11A

1-141

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
LM1896
LM2896

Vs
Vs

=
=

Operating Temperature (Note 1)

OOCto +700C
-65°C to + 1500C

Storage Temperature
Junction Temperature

150°C

Lead Temperature (Soldering, 10 sec.)

2600C

12V
18V

Electrical Characteristics
Unless otherwise specified, TA = 25°C, Av = 200 (46 dB). For the LM1896; Vs
TTAB = 25°C, Vs = 12Vand RL = 80. Test circuit shown in Fl{Jure 2.
Parameter
Po

=

OW, Dual Mode

Operating Supply Voltage
Output Power
LM1896N-1
LM1896N-2
LM2896p·1
LM2896p·2

Distortion

6V and RL

}

Vs - 12V, R, •

)

=
=
=

,.0"" Modo

12V, RL = 80 Bridge Mode
9V, RL = 40 Bridge Mode
9V, RL = 40 Dual Mode

0.9
TA

=

TTAB

25"C

Max

15

25

=

10
1.1
1.8
1.3

Min

Units

Typ

Max

25

40

mA

15

V

3

2.5
9.0
7.8
2.5.

W/ch
W
W/ch
W/ch
W
W
W/ch

0.09
0.11
0.14

%
%
%

2.1
2.0
7.2

25°C

f = 1 kHz
Po = 50mW
Po = 0.5W
Po = 1W

40. For LM2896,

LM2898

Typ

3
THO = 10%, f = 1 kHz
Vs = 6V, RL = 40 Dual Mode
Vs = 6V, RL = 80 Bridge Mode
Vs = 9V, RL = 80 Dual Mode
Vs
Vs
Vs

=

LM1898

Conditions
Min

Supply Current

=

0.09
0.11

Power Supply Rejection
Ratio (PSRR)

CBY = 100 ,..F, f = 1 kHz, CIN = 0.1 ,..F
Output Referred, VRIPPLE = 250 mV

-40

-54

-40

-54

dB

Channel Separation

CBY = 1QO ,..F, f
Output Referred

-50

-64

-50

-64

dB

Noise

Equivalent Input Noise Rs = 0,
CIN = 0.1 ,..F, BW = 20 - 20kHz
CCIR/ARM
Wideband

1.4
1.4
2.0

,..V
,..V
,..V

=

1 kHz, CIN

=

0.1 ,..F

1.4
1.4
2.0

DC Output Level

2.8

Input Impedance

50

Input Offset Voltage
Voltage Difference
between Outputs

3

3.2

100

350

5
LM1896N·2, LM2896p·2

10

Input Bias Current

120

5.6

6

6.4

V

50

100

350

kO

5
20.

10
120

mV
20

mV
nA

Note 1: For operation at ambient temperature greater than 25"C, the LM1896/LM2896 must be derated based on a maximum 15O"C iunction temperature using a

thermal resistanos which depends upon mounting techniques.

1-142

Typical Performance Curves
LM1896 Maximum Device
Dissipation va Amblanl
Temperature

LM2898 Device DIssipation
va Ambient Temperature

10

!:

iI

ZOU
1.8

I AlAI_MUM TMlCIIUI-1/11111Ctt

•

'X1=~'

"j,.
.. i...T.l..15·C/W

U~~::::~~:~

r-....I

3d.II·C/W~

5

-

4

...

E

\~

;::

;:
~

""~
"'c/W

~

~~

u

~

FEAlIU·C,W

1

o

I

1.1

1A

.......

1.2

C

~

o

o ro

ID
LMIBII
Vs-IV
Po-a.5W RL'40
OUALMOOE

rr
1--

,

1.0

~

~

D.I
0.&
I.e

/

I'....

1.2

./

50 100 ZIIII 600 Ik 2k

'"Cco.

!

•0

",

LMII1I&
VS'IV
Po - 0.5W
RL -411
DUAL MODE

30
1.0

.

~
~

D.4
0.2

o

-

20

50 180 200

LM1191
Vs'IV
Po - 0.5W
RL =40
~UAL MOOE

40
3G

sao

Ik Zk

.'"

~II!

i.
~

rc)

AV (v/V)

THD and Gain V8 Frequency
Av ~ 46 dB, BW ~ 50 kHz

.

~

-

~

....,

60

....'"

~

D.4

"

o

H

60 1l1li200 5l1li Ik Zk

I

&0

40

LMIII6
VS'IV
PO=0.5W
RL ·40
DUAL MODE

3D
1.0

I

0.2
ZO

50 100 HO 500 Ik Zk

..'"
f-I--:

~

I-r-

10

40

1.0

f-f-

a.B

i--r

~

0.&

"...'"

DA

"

p--F

30

5k 10k ZOk

~
~

il-.

LMII1I6
VS'IV
PO' 0.5W
RL -4.11
DUAL MODE

2~

,,2Cl

-10
-20

c .. -30

....
.
...

!:~

....

O.Z

ZO

II

E

..

c

•

AM Recovered Audio and Noise
va Field Strength for Different
Speaker Lead Placement

;..

I I
ill

60

50 100 200 50e Ik Zk

&k 10k 2Dk

-40

w

-60

~

-60

~

0.01

fREQUENCY (Hz)

70

..
i

!

i

30

ZO

!Ii
z

ZO

~

~

12

50

38

Power Output vs
Supply Voltage

RL -811 ~
BRIOOE

CBYPASS-IIIII.F
CIN'''O.1,101F
Av"21X1
POUT- 0.5W

Wu~
~L -811
DUAL

10
0
10

-ttt~L=4.u
BRIDIE

LM289&

10

40

10

0.1
FIELD STRENGTH (..VIM)

Channel Separation (Referred
to the Output) va Frequency

&0

5k 10k ZOk

FREQUENCY (Hzl

THD and Gain va Frequency
Av ~ 34 dB, BW ~ 50 kHz

a

--

0.4

o

&k 10k Hk

rr-

0.&

FREQUENCY (Hz)

60

FREQUENCY (Hz)

I: tt:t~~~~~=tj

0.1

&0

10

I1-~~AI&C6

o 1l1li 210 3011 4011 610 IMIO

10

1.0

FREQUENCY (Hoi

.0

10

0.8

Power Supply Rejection Ratio
(Rafarred to the Output)
va Frequency

ii

38

20

a~

0.2

D.8

D.I

60

~ 0.8

"~

5k 10k 20k

I

50

~

10

THD and Gain va Frequency
Av ~ 40 dB, BW ~ 20kHz
&0

40

50

FREQUENCY (Hoi

I

,.

'i'

THD and Gain VB Frequency
Av ~ 54dB,BW ~ 5kHz

a
ZO

~

TA - AMBIENTTEMPERATURE

a

&8

H

90
18
10

I : ~~~~~~;t~~~~:'~E~

D.4

••Z

I I

30

.

......

••&

01020304050607010

40

..
~

IO"CIW

D.I

THD and Gain VB Frequency
AV ~ 54dB,BW ~ 30kHz

a

1011-1''!I'-Ir+-+

i

FA~EAI~_ -

1.0

lA-AMBlENl TEMPERATURE ('CI

....'"

- 3 dB Bandwidth VB Voltage
Gain for Stable Operation

.A:
100

Ik

FREQUENCY (Hz)

ll1k

lOOk

o

IIIifI:=

o

10

12

SUPPLY VOLTAGE (V)

TL/H17920-2

1-143

Typical Performance Curves (Continued)

I'.

Total Harmonic Distortion
vs Power Output

LOI~

__

0.11

Power DIssipation vs
Power Output RL = 40

Power Dissipation vs
Power Output RL = 80
U~-r~~~-r~'-'

i

2.6

~i

2.0

HA-+-+++......bF-l

Ii;
....
!!

I.S

rT:;;.r;,..~n71

1.0

I-"IH~7"I,..q.-+-+++-I

1.6

1-'!1~1!9.,¥.=-+-+++-I

III

iI!~

LI

I.D

.i

LIII. .
OL-J'--L-l.-I....J-.l-L.....J'--L...J

~L-~~L-~~W

a

10

POWER OUTPUT CW/cHANNELI

0L-J......L....L.....L....L...L..'--L-l....J
o D.' 1.0 I.S 2.1

I

POWER OUTPUT CW/CHANNELI

'OWER OUTPUT IWICHANNELI
TLlH/7920-3

Equivalent Schematic
BOOTSTRAP I

BOOmRAP2

3191

12131

r---_r--r_------_1~--------_1----------_.--------_r--r_--~~~

10k

OUTPUT 1

0-+.....1-.

. . . . . . . . . .OOUTPUT2
1012)

lOOk

lOOk

61101

10k

~------~--~~~----~~-i~~~~----~~~-----t---+,~~------~~GNO
1171

-INPUT 1

71111

+INPUT I BYPASS

13141

4.1116)

-INPUT 2

+INPUT 2

6,9 No connection on LM1896

TL/H/7920-4

() indicates pin number for LM2896

Connection Diagrams
Slngle-In-Une Package
+Ys

•

Dual-In-Llne Package
OUTPUT2
+IN I

o

BOOmRAP2

-IN I

-IN 2

-112
BoomRAPI
GNO

LMII96

+112

GNO

OUTPUT I

ONO

NC

NC

BYPASS

LM211B

+111

o

+Vs
-IN 1
TLlHI7920-5

BoomRAPI

Top View
OUTPUT I
BYPAIB

TLlH/792D-B

Top VIew

1-144

Typical Applications (Continued)

ijP.:~-~~-~~o

v+

Cs

y+

R2

5111n

+

FT

C2
10 P

TL/H/7920-8

TL/H17920-7

6,9 No connection on LMI896
() Indicates pin number for LM2896

FIGURE 2. Stereo Amplifier with AV = 200, BW = 30 kHz

External Components (FigUr92j
Components
1. R2, R5, R10, R13
2. R3, R12
3.Ro
4. C1, C14

5.C2,C13

6.C3,C12

7.C5,C10
B.C7
9.Cc

Comments
Sets voltage gain, Av = 1 + R5/R2 for one channel and Av = 1 + R10/R13
for the other channel.
Bootstrap resistor sets drive current for output stage and allows pins 3 and 12 to
goaboveVs·
Works with Co to stabilize output stage.
Input coupling capacitor. Pins 1 and 14 are at a DC potential of Vs/2. Low
frequency pole set by:
1
fL =-..,..;--:2'7TRINC1
Feedback capacitors. Ensure unity gain at DC. Also a low frequency pole at:
1
fL = 2'7TR2C2
Bootstrap capacitors, used to increase drive to output stage. A low frequency
pole is set by:
1
fL = 2'7TR3C3
Compensation capaCitor. These stabilize the amplifiers and adjust their
bandwidth. See curve of bandwidth vs allowable gain.
Improves power supply rejection (See Typical Performance Curves). Increasing
C7 increases tum-on delay.
Output coupling capacitor. Isolates pins 5 and 10 from the load. Low frequency
pole set by:
1

10. Co
11. Cs

fL=--2'7TCcRL
Works with Ro to stabilize output stage.
Provides power supply filtering.

1-145

II

to

G)

CD

C"I

:I

i.,..

:E
....I

r---------------------------------------------------------------------------------,
Application Hints
Amp 1 has a voltage gain set by 1 + R5/R2. The output of
amp 1 drives amp 2 which is configured as an inverting
amplifier with unity gain. Because of this phase inversion in
amp 2, there is a 6 dB increase in voltage gain referenced to
Vi. The voltage gain in bridge is:

AM Radios
The LM1896/LM2896 has been designed fo fill a wide
range of audio power applications. A common problem with
IC audio power amplifiers has been poor signal-to-noise performance when used in AM radio applications. In a typical
radio application, the loopstick antenna is in close proximity
to the audio amplifer. Current flowing in the speaker and
power supply leads can cause electromagnetic coupling to
the loopstick, resulting in system oscillation. In addition,
most audio power amplifiers are not optimized for lowest
nOise because of compensation requirements. If noise from
the audio amplifier radiates into the AM section, the sensitivity and signal-to-noise ratio will be degraded.
The LM1896 exhibits extremely low wideband noise due in
part to an external capaCitor C5 which is used to tailor the
bandwidth. The circuit shown in Figure 2 is capable of a
signal-to-noise ratio in excess of 60 dB referred to 50 mW.
Capacitor C5 not only limits the closed loop bandwidth, it
also provides overall loop compensation. Neglecting C2 in
Figure 2, the gain is:

VO =2(1+ R5 )
Vi
. R2
Cs is used to prevent DC voltage on the output of amp 1
from causing offset in amp 2. Low frequency response is
influenced by:

1
fL=---2'IT RsCs
Several precautions should be observed when using the
LM1896/LM2896 in bridge configuration. Because the amplifiers are driving the load out of phase, an 80 speaker will
appear as a 40 load, and a 40 speaker will appear as a 20
load. Power dissipation is twice as severe in this situation.
For example, if Vs = 6V and RL = 80 bridged, then the
maximum dissipation is:

V~

Av(S) = S + AVCllo
S + ClIo
R2+R5

where Av =

R2'

1
ClIo = R5C5

This amount of dissipation is equivalent to driving two 40
loads in the stereo configuration.

A curve of -3 dB BW (ClIO) vs Av is shown in the Typical
Performance Curves.

When adjusting the frequency response in the bridge configuration, R5C5 and R10C10 form a 2 pole cascade and the
-3 dB bandwidth is actually shifted to a lower frequency:

Figure 3 shows a plot of recovered audio as a function of

field strength in /J-V/M. The receiver section in this example
is an LM3820. The power amplifier is located about two
inches from the loopstick antenna. Speaker leads run parallei to the loopstick and are 118 inch from it. Referenced to a
20 dB SIN ratio, the improvement in noise performance
over conventional designs is about 10 dB. This corresponds
to an increase in usable sensitivity of about 8.5 dB.

BW = 0.707
2'ITRC
where R = feedback resistor
C = feedback capacitor
To measure the output voltage, a floating or differential meter should be used because a prolonged output short will
over dissipate the package. Figure 1 shows the complete
bridge amplifier.

Bridge Amplifiers
The LM1896/LM2896 can be used in the bridge mode as a
monaural power amplifier. In addition to much higher power
output, the bridge configuration does not require output coupling capacitors. The load is connected directly between the
amplifier outputs as shown in Figure 4.

~

...5:w
oc

w
!l

:iii
CI:!!.
:i!co Si,

..iiigE
oc

.
!:;:
co
w

oc

62

Po=--X2=--X2
20 RL
20 X 4
Po = 0.9 Watts

dB

o r-10
-20

-30

~~~t~ERJD

AUDIO AT
SPEAKER

III

/

II:

"-

RECOVERED

NOISE AT

-40

"

~

srEm~1

I-iii III
-60

-50

•

0.01

NOISE WITH SPEAKER LEADS
1/8·· FROM LOOPSTICK

Tiiiiii=~::~~:J!~N:":'OR
0.1

10

FIELD STRENGTH (mV/M)
TLlH17920-9

FIGURE 3. Improved AM Sensitivity over Conventional Design

1-146

Application Hints (Continued)

-fov-Vio-f

C14

~
RU
RS

T

C13
TUH17920-10

Figure 4. Bridge Amplifier Connection

Printed Circuit Layout
less than 50 kO to prevent an input-output oscillation. This
oscillation is dependent on the gain and the proximity of the
bridge elements Rs and Cs to the (+) input. If the bridge
mode is not used, do not insert Rs, Cs into the PCB.
To wire the amplifer into the bridge configuration, short the
capacitor on pin 7 (pin 1 of the LM1896) to ground. Connect
together the nodes labeled BRIDGE and drive the capacitor
connected to pin 5 (pin 14 of the LM1896).

Printed Circuit Board Layout
Figure 5 and Figure 6 show printed circuit board layouts for
the LM1896 and LM2896. The circuits are wired as stereo
amplifiers. The signal source ground should return to the
input ground shown on the boards. Returning the loads to
power supply ground through a separate wire will keep the
THD at its lowest value. The inputs should be terminated in

COMPONENT SIDE

FIGURE 5. Printed Circuit Board Layout for the LM1896
1-147

TUH/7920-11

Printed Circuit Layout (Continued)

YIN1
BRIDGE
INPUT

INPUT
GROUND

COMPONENT SIDE
TLlHI7920-12

FIGURE 6. Printed Circuit Board Layout for the LM2896

1-148

.------------------------------------------------------------------------.r
i:

~National

~

CD
......
......

~ Semiconductor

LM2877 Dual 4-Watt Power Audio Amplifier
General Description
The LM2877 is a monolithic dual power amplifier designed
to deliver 4W/channel continuous into 80 loads. The
LM2877 is deSigned to operate with a low number of external components, and still provide flexibility for use in stereo
phonographs, tape recorders and AM-FM stereo receivers,
etc. Each power amplifier is biased from a common internal
regulator to provide high power supply rejection and output
Q point centering. The LM2877 is internally compensated
for all gains greater than 10, and comes in an 11-lead single-in-line package.

Features
• 4W/channel
• - 68 dB ripple rejection, output referred
• - 70 dB channel separation, output referred

•
•
•
•
•

Wide supply range, 6-24V
Very low cross-over distortion
Low audio band noise
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•
•
•
•

Multi-channel audio systems
Stereo phonographs
Tape recorders and players
AM-FM radio receivers
Servo amplifiers
Intercom systems
Automotive products

Connection Diagram
(Single-In-Line Package)
BIAS...! •

OUTPUT1....!.

o

INPUT1...!

FEEDBACK

12

FEEDBACK2~

III

o

GND...!

10

OUTPUT 2 .-..

"....!!.

'------.......

TL/H/7933-1

Top View
Order Number LM2877P
See NS Package Number P11A
'Pin 6 must be connected to GND.

1-149

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage

Electrical Characteristics Vs =
Parameter
Total Supply Current

Junction Temperature

1500C

Lead Temperature (Soldering, 10 sec.)

2600C

20V, TTAB = 25·C, RL = 80, Av = 50 (34 dB) unless otherwise specified.
Conditions

Distortion, THD

f =
Vs
Vs
Vs

1 kHz, THD = 10%, TTAB = 25"C
= 20V
= 18V
= 12V, RL = 40

f =
Po
Po
Po
f =
Po
Po
Po

1 kHz, Vs = 20V
= 50 mW/Channel
= 1W/Channel
= 2W/Channel
1 kHz, Vs = 12V, RL = 40
= 50 mW/Channel
= 500 mW/Channel
= 1W/Channel

RL = 80

Channel Separation

CF = 50 ,...F, CIN = 0.1 ,...F, f = 1 kHz,
Output Referred
Vs = 20V, Vo = 4 Vrms
Vs = 7V, Vo = 0.5 Vrms

PSRR Power Supply

CF = 50 ,...F, CIN = 0.1 ,...F, f = 120 Hz

Rejection Ratio

Output Referred
Vs = 20V, VRIPPLE = 1 Vrms
Vs = 7V, VRIPPLE = 0.5 Vrms

Open Loop Gain

Typ

Max

Units

25

50

mA

24

V

6

Output Swing

Noise

Min

Po=OW

Operating Supply Voltage
Output Power/Channel

-65"Cto

Storage Temperature

26V
±0.7V

4.0
1.5

0.25
0.20
0.15

Vs = 20V

1

%
%
%
%
%
%

-50

-70
-60

dB
dB

-50

-68
-40

dB
dB

2.5

,...V

0.80

mV

Input Bias Current

DC Output Level

1

Vp_p

Rs = 0, f = 1 kHz, RL = 80

9

Slew Rate

W
W
W

Vs-4

Input Offset Voltage

Open Loop

4.5
3.6
1.9
0.1
0.07
0.07

Equivalent Input Noise
Rs = 0, CIN = 0.1 ,...F, BW = 20 Hz-20 kHz
Output Noise Wideband
Rs = 0, CIN = 0.1 ,...F, Av = 200

Input Impedance

+ 700C
+ 150·C

.O·C to

Operating Temperature

70

dB

15

mV

50

nA

4

MO

10

11

V

2.0

VI,...s

Power Bandwidth

65

kHz

Current Limit

1.0

A

Note 1: For operation at ambient temperature greater than 2SOC, tha LM2Sn must be derated baaed on a maximum 150'C iunction temperature using a thermal
resistance which depends upon device mounting techniques.

1-150

rn

.a

c

iCD

:::lI

,

,

,

en

n

,

•

•

•

11

ov+

::r

CD

3

a

n'

SIc

o

ii

co

AI

3
.....
.....

3Gk

~

ik

RSUB

5
-FEEDBACK 1

TAB

_4
+INPUTI

1

08
+INPUT2

7
-FEED-SACK 2
TL/H17933-2

1.1.8~W'

III

........
~

::I

Typical Performance Characteristics
Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

Device Dissipation vs
Ambient Temperature
10

~

z

co

I

8
7

at.u..

,,1....1.....l..-

lXl~=~~,;'

15°C/W

.

r-...I

,J.,.i;i....

3x1IN28° IUW.\,

~

.... ............,; NI )..~.

is
fj

..·C/W

FIE, ", ... C/W

1

o

I

o

10

~

~

40

..
ii
iil..
..
I

;;;
3

~

..'"
~.
.
ii

10
&0
41

3.

~

I:

-~ s..o::: ~

~

70

70
TIIDIIUS_1/11INCH

1.4~~:=::~~:~

Ii

a
'"
~

20
'0

.10.

~

'00

TA-AMBIENT TEMPERATUIE (OC)

I

j
l!i

~

..i:lt

a

15

ca

i'"

..
ie
..

~ 'rf..~R'PPLE
•• ' ~'m~
VR'PPLE" 0.3 Vrms
V~IPP~E ".'0.5 v~

o
8

'0
'2 14
SUPPLY VOLTAGE IV)

BID

RL = 8[l
BOTH CHANNELS DRIVEN

.!
.... 800

;.
8

.i

V

a

1/

t-ICi~III~·IIF,

10

llJIIl
'00

10

'Ok
FREIIUENCY IH.)

~

t;

iii

0.'

,.c

~

c
....

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

'110

POWER OUTPUT !W/CHANNEL)

Power Dissipation vs
Power Output

20V

~~~ '-t"
~i;i"
Q

Ii

'Ok
FREIIUENCY 1Hz)

THO-3lI

;:::r-t..,.
:::or1
THO' 10"

II
II

o

100

Output SWing vs Supply
Voltage
16

10

I

...:c'"
..~

1

..

~

i'

6G

RL =10

i'

20

L

'2

I
~

40

>

'OOk

FREIIUENCY IH.)

VS' 20V
RL =In

~

~

IL

IL

V

'"

~

o

0
IOU

POWER OUTPUT !W/CHANNEL)

lOUk

Open Loop Gain vs
Frequency
'00

'IV

,. ,..

....

....

V

0.1

.

~

-' L
I I

lOOk

6

c
....

RL =8n

1.
'III
FREOUENCY IH.)

l

~

Ii

100

Total Harmonic Distortion
vs Frequency

..
..
.."
I

~

c

o

111111

Total Harmonic Distortion
vs Frequency

.."
..~
..."
,.
..

1"1

c:~ ~1~~ilMl!F

50

iii

200

o

Channel Separation (Referred)
to the Output) vs Frequency
CBYPASS' 50,F
VCC' 7V
Vo =SOOmVrrnl
AV = 511

10

f- t-

'Ok

'k

10

1&

ffi

::

'00

FREIIUENCY IH.)

40

w

c

Vcrrim"I' "j
"'"'''' ,

5';

w

l---io""

caD

'I
o

70

Average Supply Current vs
Power Output
C

~

'O~

20

~

"BYPASS· 5 •
_
C'N"O.I"F
VRIPPLE =, V,""
1·120 Hz
Av=50

20

lL

u~I

30

'0

10

""i..

I

100.F

Channel Separation (Referred)
to the Output) vs Frequency

NO'S~;:;;;bl,

I

10

&a

40

10k

'k

VR'PP~E • 1 v ....
C'N"I.004hF
AV'!i8

II
II

10

FREQUENCY IH.)

Power Supply Rejection Ratio
(Referred to the Output) vs
Supply Voltage
10

Power Supply Rejection Ratio
(Referred to the Output) vs
Frequency

,.

1l1li

lOOk

FREIIUENCY IH.)

'M

4

6

I

10 12

14

'6

11

20

SUPPLY VOLTAGE IVI
TL/HI7933-3

1-152

Typical Applications
Stereo Phonograph Amplifier with Bass Tone Control

+
IOhFT

0.033pF

STEREO
CERAMIC
CARTRIDGE

•

51k

+
T1DhF
TL/HI7933-4

Frequency Response of Bass Tone Control
ii

65

II:

55

...
'"
!;

:!!

;;;;;;;;;

..'"
z

46

-

~

TONE.~

....'"
..'" L
.,
~
z

35

co
co

25

'">

15

MAXIMUM
BOOST
~ESPDNSE

CONTROL FLAT
~

~

20

I ........

~AXIMUM

CUT
RESPONSE

1

50 100 20U 600 lk 2k

5k lDk 2Uk

FREQUENCY (Hz)
TUHI7933-5

1-153

~r----------------------------------------------------------------------,

Ii;
C'\I

....::E

Typical Applications (Continued)
Stereo AmplHler with Ay = 200
VSo-.~""I

I ...

L _ _ _ _ .J

liD

+

TlhF
TUHf7933-8

Non-Inverting AmplHler Using Spilt Supply
Zk

Y+11~

r;I --

D.t".F ":"

II

--,
I

Zk

lOll

TYPICAL SPLIT SUPPLY
TUHf7933-7

1-154

,-------------------------------------------------------------------------------------, riC

Typical Applications (Continued)

§

Window Comparator Driving High, Low Lamps

r---t---------t-----t---O+v
I.

LOW

2.

10

I.

TUHI7933-8

Truth Table

Y,N

High

Low

<',4 V+
',4 V+ to% V+

Off
Off
On

On
Off
Off

>%V+

Application Hints
The LM2877 is an improved LM377 in typical audio applications. In the LM2877, the internal voltage regulator for the
input stage is generated from the voltage on pin 1. Normally,
the input common-mode range is within ±O.7V of this pin 1
voltage. Nevertheless, the common-mode range can be increased by externally forcing the voltage on pin 1. One way
to do this is to short pin 1 to the positive supply, pin 11.

The only special care required with the LM2877 is to limit
the maximum input differential voltage to ± 7V. If this differential voltage is exceeded, the input characteristics may
change.
Figure 1 shows a power op amp application with Av = 1.
The 1OOk and 10k resistors set a noise gain of 10 and are
dictated by amplifier stability. The 10k resistor is bootstrapped by the feedback so the input resistance is dominated by the 1 MO resistor.
lOOk

12V

>.--00 vour

TO.

11lF
TL/H/7933-9

FIGURE 1

1-155

•

~National

~ Semiconductor

LM2878 Dual 5 Watt Power Audio Amplifier
General Description

Features

The LM2878 is a high voltage stereo power amplifier designed to deliver 5W/channel continuous into 80 loads. The
amplifier is ideal for use with low regulation power supplies
due to the absolute maximum rating of 35V and its superior
power supply rejection. The LM2878 is designed to operate
with a low number of external components, and still provide
flexibility for use in stereo phonographs, tape recorders, and
AM-FM stereo receivers. The flexibility of the LM2878 allows it to be used as a power operational amplifier, power
comparator or servo amplifier. The LM2878 is internally
compensated for all gains greater than 10, and comes in an
11-lead single-in-line package (SIP). The package has been
redeSigned, resulting in the slightly degraded thermal characteristics shown in the figure Device Dissipation vs Ambient Temperature.

•
•
•
•
•
•
•

Wide operating range 6V -32V
5W/channeloutput
60 dB ripple rejection, output referred
70 dB channel separation, output referred
Low crossover distortion
AC short circuit protected
Internal thermal shutdown

Applications
•
•
•
•

Stereo phonographs
AM-FM radio receivers
Power op amp, power comparator
Servo amplifiers

Typical Applications
+
lOO"F*"
UhF

51k

Ik

....

85

...z

55 f--

w

45

:s
C>

a:

51Dk

Frequency Response
of Bass Tone Control

f"""

8

llOk

"...

C>

500"F

+~

-!r+r
":'

STEREO
CERAMIC
CARTRIOGE

I
I
I

>

un

1/

/

35
25

AAXIMUM
~
-~~~PONSE
"7
I

IS
20

-:

8u

-=

+)

I

ft

5OO"F

un

8n

To.I"F
510k

lOOk ":'

":'

+
TlIHI7934-1

FIGURE 1. Stereo Phonograph Amplifier with Bass Tone Control
1-156

5k 10k 20t

FREQUENCY (Hz)
TL/H/7934-2

I

I

I

50 100 200 500 It 2k

TO.I"F

":'

MAXIMUM
BOOST
~ESPONSE

TONE.['...
CONTROL FLAT

~

C>

"
<
'"w
'"
~
C>

O.D33"F

~

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

Storage Temperature

35V

Input Voltage (Note 1)

O'Cto +70'C
-65'C to + 150'C

Junction Temperature

+ 150'C

lead Temperature (Soldering, 10 sec.)

+ 260'C

±0.7V

Electrical Characteristics Vs =
Parameter
Total Supply Current

Operating Temperature (Note 2)

22V, T TAB = 25'C, RL = an, Av = 50 (34 dB) unless otherwise specified.

Conditions

Min

Po= OW

Operating Supply Voltage

Typ

Max

Units

10

50

mA

6

Output Power/Channel

f = 1 kHz, THD = 10%, TTAB = 25'C

Distortion

5

32

V

5.5

W

f = 1 kHz, RL = an
Po = 50mW

0.20

%
%

Po = 0.5W

0.15

Po= 2W

0.14

%

Output Swing

RL = an

Vs - 6V

Vp-p

Channel Separation

CBYPASS = 50 /l-F, C,N = 0.1/l-F
f = 1 kHz, Output Referred
Vo = 4Vrms

-50

-70

dB

-50

-60

dB

-60

dB

±13.5

V

PSRR Power Supply
Rejection Ratio

CBYPASS = 50 /l-F, C,N = 0.1/l-F
f = 120 Hz, Output Referred
Vripple = 1 Vrms

PSRR Negative Supply

Measured at DC, Input Referred

Common-Mode Range

Split Supplies ± 15V, Pin 1
Tied to Pin 11

Input Offset Voltage
Noise

10

mV

Equivalent Input Noise
Rs = 0, C,N = 0.1 /l-F
BW=20-20kHz

2.5

/l-V

CCIReARM

3.0

/l-V

o.a

mV

Output Noise Wideband
Rs = 0, C'N = 0.1/l-F, Av = 200
Open loop Gain

Rs = 51.0, f = 1 kHz, RL = an

Input Bias Current
Input Impedance
DC Output Voltage

dB
nA

Open loop

4

Vs = 22V

11

10

Slew Rate
Power Bandwidth

70
100

3 dB Bandwidth at 2.5W

Current limit

Mn
12

V

2

V//l-S

65

kHz

1.5

A

Note 1: ±O.7V applies to audio applications; for extended range. see Application Hinls.
Note 2: For operation at ambient temperature greater than 25·C. the LM2878 must be derated based on a maximum 150"C iunction lemperature using a thennal
resistance which depends upon device mounting techniques.

1-157

II

Typical Performance Characteristics
Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency

Device Dissipation vs
Ambient Temperature

UM._-lI."'" I
.~IIITtI.....J..-

10

10 ,..rrmrnrTT'l'I

IIWI..

I

1Xl~~~/;"
u~~::::~~~

......

-

~_NI

..
.I;S

15·C/.

3dIIlZl-C/W'\\

I

.J...i:.....

,":l,.

o

o

80

~

50 l-~fffillF7''tiI'+tHIIII-+-I-tttHfl

a:

i

FlHAIIIWC/W

I

!

a:

Zl'C/W

IIJ: ~ ~

1

I-H-HirIlY'>4'r>1

4G
30

20
10

I

10 20 30 40 50 60 70 10

18

Ie

co

I:

~

3D

51

I

ttl -

50

..

..
;:
a:

0.3 vrm;.5'v:'" I--

t'\

..

;
r---

70

l!

60

ljl

..

10

w

c

40
10

14

16

ZZ

1.5

;

0.2

3D

34

,.

1111

;:
a:

II

1111

,.

ImIII'~~'iili
10.

Total Harmonic Distortion
vsPowerOut

./

'\.

= '.1

II'...

: 1.Di
~
O.DZ
1.01

-.

:e
~

.
..~

jVjSO

RL~.J

>

511 1111 ZIII SOD 1. Z. 6k 10k ZO.

0.11

FREQUENCV IHrI

511 100 200 SOD ,. Z.

5. 10k ZOO

'YsoZ2V
RL·an

80
III

0.1

1.D

40

zo
0
lDO

10

POWER OUT IW/CHANNELI

Power Output/Channel vs
Supply Voltage

10k

1k

lOOk

1M

FREQUENCV IH.I

Power Dissipation vs
Power Out

RL-an
THD-1Dl1

RL·an

.,-

/

/

t:>

~ TF-l::?~~ THB-

./

~r

V

• • ro n " ro "

ZZ?~THD
-ZOY

/

... ~

AV-SOrRL"61l
VCC" zzv

w

VC~ - 22V

ZO

j

100

po·o.•

=

0.D2

Open Loop Gain vs
Frequency

I I

./

~o'-;'i/~
1\.Pl"'2.0 w

FREQUENCY (Hz)

y!

./

~

'PouT'ro~ ~~

ZO

t~
VI 1/
V'

0.2

/~

0.01

Total Harmonic Distortion
vs Frequency

V'

O.S

100.

FREQUENCV IH.I

r-...

2.0
1.0

cz 0.1
0.05
;;!

SUPPLY VOLTAGE IVI

10.0
6.0

i50!

Z6

l:~ -~.l~~

,"\

C, • O. l4ioF

10.0
5.0

!!

C6VPASS - 50 of
VCc-ZZV
AV'50

50

~

...
.Iii
.
..IIi
........

\

IE

o

Z.o
1.0

Total HarmoniC Distortion
vs Frequency

11111 111111

II

~

rr--'-III Hz rAv-511
r-

ZI

II

~
a:

BYPASS' eoF
C'N-O.l.F

6

!!

Channel Separation
(Referred to the Output) vs
Frequency

YRIPPU· 1.1 Yrml

III

a:

FREQUENCV IH.I

III

70

I

10k

FREQUENCV IH.I

Power Supply Rejection
Ratio (Referred to the
Output) vs Supply Voltage

:e

,.

188

TA-AMBIENT TEMPERATURE (OCI

;;;

Power Supply Rejection
Ratio (Referred to the
Output) vs Frequency

o
II 22

SUPPLY VOLTAGE IVI

I

o
POWER OUTPUT IW/CHANNELI

1·158

TLlHI7934-3

Equivalent Schematic Diagram

::

r-----....

........

... c

-o~

...

III

1

..

...

I.-----+~O~5

+

. ;::

-----I-Oi

+

II
....

... c

....----+--O~

...

III
III

1

- -......-O-=~II

1-159

Connection Diagram

Application Hints
The LM2878 is an improved LM378 in typical audio applications. In the LM2878. the internal voltage regulator for the
input stage is generated from the voltage on pin 1. Normally.
the input common-mode range is within ±0.7V of this pin 1
voltage. Nevertheless the common-mode range can be increased by extemally forcing the voltage on pin 1. One way
to do this is to short pin 1 to the positive supply. pin 11.
The only special care required with the LM2878 is to limit
the maximum input differential voltage to ± 7V. If this differential voltage is exceeded. the input characteristics may
change.
Figure 2 shows a power op amp application with Av = 1.
The 1OOk and 10k resistors set a noise gain of 10 and are
dictated by amplifier stability. The 10k resistor is bootstrapped by the feedback so the input resistance is dominated by the 1 MO resistor.

Single-In-Une Package
BIAS
OUTPUT I

o

GND
INPUT I

4

FEEDBACK I
*TAB
FEEDBACK 2

o

IIIPUT2
GND

lOOk
15V

>~-OYDUT
TL/H/7934-5

YIN

Top View

000-"""""'4

2.m.

'Pin 6 must be connected to GND.

Order Number LM2878P

T

See NS Package Number P11A

O•1 IJ. F
TLlHI7934-8

FIGURE 2. Operational Power Amplifier, Ay = 1

1-160

External Components (Figure 3)

1. R2. R5. R7. R10 Sets voltage gain Av = 1 + R2/R5 for
one channel and Av = 1 + R10/R7 for
the other channel.
2. R4. R8
Resistors set input impedance and supply bias current for the positive input.
3.RO
4.C1

Works with Co to stabilize output stage.
Improves power supply rejection (see
Typical Performance Characteristics).

5. C11

Stabilizes amplifier. may need to be larger depending on power supply filtering.

6.C4.C8

Input coupling capacitor. Pins 4 and 8
are at a DC potential of Vs/2. Low frequency pole set by:

1
fL = 2'ITR4C4
Feedback capacitors. Ensure unity gain
at DC. Also low frequency pole at:

7. C5. C7

1
fL = 2'ITR5C5

8. Co
9. C2.C10

Works with Ro to stabilize output stage.
Output coupling capacitor. Low frequency pole given by:

1
fL=~

Typical Applications (Continued)
I&V

lOOk

10k

G.I~

~

C2

I

I
I

R:~lRL

un

T

an

co_
a.I • F -

2m

MOTOR

1I11III

I~
"="
I
CIG

II

:~~~
1-

IDle

Co

RIO

TO.I~

2.m

1I11III

TG.I~F

TLlH/7934-8

FIGURE 4. LM2878 Servo Amplifier In

TLlH/7934-7

Bridge Configuration

FIGURE 3. Stereo Amplifier with Ay = 200

1-161

Typical Applications (Continued)
r-~.--------t----~--~.v

Truth Table

1k

YIN

High

Low

o/4V+

Off
Off
On

On
Off
Off

10

TUH17934-9

FIGURE 5. Window Comparator Driving High, Low Lamps

1·162

~National

~ Semiconductor

LM2879 Dual8-Watt Audio Amplifier
General Description
The LM2879 is a monolithic dual power amplifier which offers high quality performance for stereo phonographs, tape
players, recorders, AM-FM stereo receivers, etc.
The LM2879 will deliver 8W/channel to an 80 load. The
amplifier is designed to operate with a minimum of external
components and contains an internal bias regulator to bias
each amplifier. Device overload protection consists of both
internal current limit and thermal shutdown.

Features
•
•
•
•

Avo typical 90 dB
9W per channel (typical)
60 dB ripple rejection
70 dB channel separation

•
•
•
•

Self-centering biasing
4 MO input impedance
Internal current limiting
Internal thermal protection

Applications
•
•
•
•
•
•
•
•
•
•

Multi-channel audio systems
Tape recorders and players
Movie projectors
Automotive systems
Stereo phonographs
Bridge output stages
AM-FM radio receivers
Intercoms
Servo amplifiers
Instrument systems

Connection Diagram and Typical Application

Stereo Amplifier

Plastic Package

o

11
lU
9
8
7
6

,.,.

v+

-,

OUTPUT 2
GNU

INPUT 2
FEEDBACK 2

Ne

5

FEEDBACK 1

4
3
2
1

INPUT 1

I.""',

GND
OUTPUT 1
BIAS

..

,

1.1'"

• c,

TOPYIEW
TL/H/5291-1

I.""',

..

1""""--......-'9"''''1+

T ....

,.,.

..

I - " - -......-~.:.t+

u ..

Order Number LM2879T
See NS Package NumberTA11B

,.,.
'TAB must be connected to GND.
TLlH/5291-2

FIGURE 1

1-163

•

Absolute Maximum Ratings
+ 15O"C

If Military/Aerospace specified devices are required,

Storage Temperature

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Junction Temperature

150"C

Lead Temp. (Soldering, 10 seconds)

260"C

Supply Voltage

35V

Input Voltage (Note 1)

ESD rating to be determined.

±0.7V

Operating Temperature (Note 2)

+ 70"C

O"Cto

Electrical Characteristics Vs = 28V, TTAB =
Parameter

25"C, RL = 80, Av = 50 (34 dB), unless otherwise specified.

Conditions

Total Supply Current

- 65"C to

Min

Po=OW

Operating Supply Voltage

Typ

Max

Units

12

65

mA

6

Output Power/Channel

f=1 kHz, THD=10%, TTAB= 25'C

Distortion

f= 1 kHz, RL =80
PO= 1 W/Channel

6

RL =80

Channel Separation

CBVPASS=50 ,..F, CIN=0.1 ,..F
f = 1 kHz, Output Referred
VO=4 Vrms
CBVPASS=50 ,..F, CIN=0.1 ,..F
f = 120 Hz, Output Referred
Vripple= 1 Vrms

PSRR Negative Supply

Measured at DC, Input Referred

Common-Mode Range

Split Supplies ± 15V, Pin 1
Tied to Pin 11

1

%
Vp-p

-50

-70

dB

-50

-60

dB

-60

dB

Equivalent Input Noise
Rs=O,CIN=0.1,..F
BW=20 -20 kHz
CCIR-ARM
Output Noise Wideband
Rs=O,CIN=0.1,..F,Av=200

Open Loop Gain

W

VS-6V

Input Offset Voltage
Noise

V

8
0.05

Output Swing

PSRR Positive Supply

32

Rs=510, f=1 kHz, RL =80

Input Bias Current

±13.5

V

10

mV

2.5
3.0
0.8

,..V
,..V
mV

70

dB

100

nA
MO

Input Impedance

Open Loop

4

DC Output Voltage

Vs=28V

14

V

2

VI,...

65

kHz

Slew Rate
Power Bandwidth

3 dB Bandwidth at 2.5W

Current Limit

1.5
A
Note 1: The input voltage range is normally limited to ±O.7V with respect to pin 1. This range may be extended by shorting pin 1 to the positive supply.
Note 2: For operation at ambient tempereture greater than 25'C, the LM2879 must be derated based on a maximum 15O'C junction temperature. Thermal
reslstance,lunction to case, is :r'C/W. Thermal resistance, case to ambient is 4rf'C/W.

Typical Performance Characteristics
Device Dissipation vs
Ambient Temperature
22
INFIlllTE HEAT SINK

~

z

iII
!:f

iii

Z8
18
18
14
12
18
8

8
4
2

I'.

lD'C/W
IEATSiNK

•

I I
I I

-

4'C/W
HEAT SINK

.....

Open Loop Gain vs
Frequency
1111

Power Dissipation va
Power Output
11

VS-zzv

10

U
IIi
~i
III

10

ali

41

r- ....

1. Z8 30 40 50 50 70 ID
TA-AM8IBIT TEIII'ERATURE ('CI

Ii

~

ZI

•

1111

Ik

1l1li

10IIe

FREIIUENCY (Hz)

I• ze

18

RL -Ill

1M

8
7
8
5
4

ZIV

MY

""zzy

~

2
1

•

I

4V'

LA

1...
THD

,~~ IfvIllY

3

3~D

+
'=11111z

111.=111

-,-ID
1 234 5 8 7 • •
POWEll OUTPUT (W/CHANNa.)

~

TUH/5291-3

1-164

Typical Performance Characteristics
Supply Current vs Output
Power

...,

800

1171111

~i
!§ ~

.....
i~
iii ~

w'"
III

o

iOo'~

",

'"

50
40
3D

='"

20

~

o

~

;.~
i
I

0.5
0.2
0.1

~ 0.05

e

0.02
0.01

1

~ ~f=r

~,.

~I

~

~

POlo.rr-~

~

z

i'"

...

...~
lOOk

I...._~::
I

0.5

Av=20o

~

0.2
c 0.1
~ 0.05

~'"

"

~ 0.02
0.01

~
~

.....

~

~

~

,/

15

i!...

10

i

~

lk
10k
FREQUENCY (Hz)

lOOk

1=1 kHz
RL=BII

/

c::o

o

20 50 100 200 500 lk 2k 5k 10k 20k
FREQUENCY (Hz)

~

~

,/

!;

10

15

20
25
V SUPPLY (V)

30

35

•

Power Output/Channel va
Supply Voltage

10

,

10

'"

z

RL=BII
9 THO=10%

iii

1.0

:If
:z:

...i!is

...~

C>

0.1

::0

C>

:z:

i

...g0.01
0.01

100

20

co

z

~

~

Output Swing vs Vs

Avi~

;::

IE

10

25

RL-BII
Po=0.5W
Vee=2BV

!:

=
C

III I II

CBYMSS=50 p!'
Vee =2BV
Av=50
YoUT =4 VIm.
RL=BII

50

40

100
lk
10k
FREQUENCY (Hz)

i§

t;

60

W

Z

z

Total Harmonic Distortion
vs Power Output

.

Tni..'"\..
IlcIN =~.Jo~~1 J'.

5!

Total Harmonic Distortion
va Frequency

20 50 100 200 50D lk 2k 5k 10k 20k
FREQUENCY (Hz)

~

~lrF'

70

!i

C VALUES ARE RIPPLE FILTER

10

10.0
~ 5.0

Av=50
5 RL=BlI
vee=~v

H

j

II
.!Vs=2oV,
I. Av=5o

Total Harmonic Distortion
vs Frequency
10

11)

1 pF

10

1 2 3 4
6
OUTPUT POWER (W/CHANNEL)

so

I I

60 20p!'

...
::oW

"Il:;

!Iv-50, Vs-2BV, RL=BO, 1=1 kHz

o

80

70

~~

...

1
I

100

..

~~
til;!

,

400
300

Channel Separation
(Referred to the Output)
Frequency

Supply Rejection vs
Frequency

;!.

~

600
500

~~ 200

Ii

~

(Continued)

0.1
1.0
POWER OUT (WI CHANNEL)

10

~

o

"

6 B 10 12 14 16 lB 20 22 24 26 2B
SUPPLY VOLTAGE (V)
TUH/5291-4

1-165

LM2879

m
.a

c

ii'

~

t J)

n

:::J'
CD

3

II)

ct

n

C

cZ·
iii
3

.

~
~

8l

GND03

06
NC

5
-FEEDBACK 1

401
TAB

+INPUT 1

08

+INPUT 2

7
-FEEDBACK 2

GND09
TlIH/5291-5

r-----------------------------------------------------------------------------, a:
~

Typical Applications

N

~

Two-Phase Motor Drive

o

C2
0.1 pi

Me

.,

27k

.3
27k

II
lOOk

u

2.7

mo

2.7

17

10k

TD.I,.F

C3

•·.. plT

TO.'I'F
":'

TUH/5291-6

12W BrIdge Amplifier

~~~------~~------.-------------------~

1M

1M

0.47 pi

10k
TUH/5291-7

1-167

Typical Applications (Continued)
Simple Stereo Amplifier with Bass Boost
D.02'"

2.7

1....

11

r

2Il

1'5,.,
+

0

Y·

-,

TO.

1 ".F

"='
10

IN""'I-1C,

llIDII

D.l,.,

1

TN,.,
IIIMZ-1

1I11III

I

"='

CF
D.l'"

Zk

L

+

IS'"

2.7

1.

1I11III

"='

.-

0.1 ".F

Power Op Amp (Using Spilt Supplies)
lOOk

y.

18k

IN""T~\M,...-4~:.t

2.7

v-

'I

-:c- O.I".F
"='
0.1,.,
TLlH/5291 -9

1-168

TL/H/5291 -8

r-----------------------------------------------------------------------------,
Typical Applications (Continued)

~

Stereo Phonograph Amplifier with Bass Tone Control

STEREO
CERAMIC
CARTRIDGE

+

1

1DDpf
TL/H/5291-10

Frequency Response of
Bass Tone Control

i

I

65

....
w

...~
..
z

~

55
45

I I I

~:~~UM_ r-TON~'"
CONTROL ,RESPONSE- 1-FLAT

35

w

25

~

15

~

I I
~

i..;'

i"""

4AXIMJM- 1-CUT
- r-r-

.'ES~NfE- ~t-

20 50 100 200 500 lk 2k 5k 10k 20k
FREQUENCY (Hz)
TL/H/5291-11

1-169

~

iii:

~ r-----------------------------------------------------------------------~

i

~ ~National
~ Semiconductor

ADVANCE INFORMATION"

LM3875
High Performance 40W Audio Power Amplifier
General Description

Features

The LM3875 is a high-performance audio power amplifier. II
is capable of delivering 40W to an 80 load. It is fully protected using circuit techniques similar to those found in the
LM12.

•
•
•
•
•
•

The output stage is protected from a short to ground or to
the supplies. Protection against transients from inductive
loads is provided at the output stage via internal clamp diodes. The LM3875 also contains thermal shutdown protection against operation outside its operating temperature
range.

40W output power into 80
Over-voltage protection
Dynamic Safe Area Protection
Fully protected from AC and DC short-circuits
11-lead TO-220 package
Under-voltage shutdown

The LM3875 is internally compensated and stable for gains
~10.

Typical Application

Connection Diagram
Y+

Plastic Package

,..

lkll

INPUT

II)

OUTPUT

3

-.

.i..

220pF

47kll

III

.-=

.i..
- ...

I O . 1 J.1F

-

4
3
2

TUHI11449-2

Order Number LM3875CCT
See NS Package Number T11A

3.3kll

-.

.....

TopYlew
39kll

I

(II)

~

...

Y-

10J.lF

0

CD

He
Ne
He
YINYIN+
Ne
Ne
YOUTPUT
Ne
Y+

10 pF

TUH/II449-1

C-Power supply bypass using low ESR 680 p.F elec1rolytic, 10 p.F elec1rolytic, and 0.1 ceramic chip
capacitor.
Ground CoMections
'Input signal ground.
"Power supply bypass ground.
"'Output signal ground.
Those three ground connecticns should have separate rewm paths to the power supply ground ("ster
ground").

1-170

~National

ADVANCE INFORMATION

~ Semiconductor

LM3876
High Performance 40W Audio Power Amplifier
General Description

Features

The LM3876 is a high-performance audio power amplifier
with an output mute that eliminates turn-on and turn-off transients. It is capable of delivering 40W to an 80 load. It is
fully protected using circuit techniques similar to those
found in the LMI2.
The output stage is protected from a short to ground or to
the supplies. Protection against transients from inductive
loads is provided at the output stage via internal clamp diodes. The LM3876 also contains thermal shutdown protection against operation outside its operating temperature
range.

•
•
•
•
•
•
•

40W continuous output power into 80
Turn-on and turn-off mute
Over-voltage protection
Dynamic Safe Area Protection
Fully protected from AC and DC short-circuits
II-lead TO-220 package
Under-voltage shutdown

The LM3876 is internally compensated and stable for gains
;;'10.

Connection Diagram

Typical Application

Plastic Package

V+

11
10

CO
INPUT

1 kO
OUTPUT

-.

..i..

220 pF

47 kO

..i..
- ...

10

. -=

IO.
-

.. =

0

....
CO

(II)

::::i

~

9
8

7
6

"
3

2

1 J.'F

...

Ne
VIN+
VINMUTE
GND
Ne
Ne
VOUTPUT
Ne
V+
TL/H/I1450-2

Top View

Order Number LM3876CCT
See NS Package Number Tl1A

V39kO

3.3kO
10 pF

TL/H/II450-1
C-Power supply bypass using low ESR 880 "F electrolytic, 10 "F electrolytic, and 0.1 ceramic chip
capacHor.
Mute-In this example, the mute pin is tied high

Ground Connections
'Input signal groYnd.
"Power Supply bypass ground .

• "Output signal ground.
These three ground connections should have separate return paths to the power supply ground ("star
ground").

1-171

II

r--------------------------------------------------------------------------------,
B ~National
:=!i
~
CO)

~ semiconductor

LMC835 Digital Controlled Graphic Equalizer
General Description

Features

The LMC835 is a monolithic, digitally-controlled graphic
equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists
of a Logic section and a Signal Path section made of analog
switches and thin-film silicon-chromium resistor networks.
The LMC835 is used with external resonator circuits to
make a stereo equalizer with seven bands, ± 12 dB or ± 6
dB gain range and 25 steps each. Only three digital inputs
are needed to control the equalization. The LMC835 makes
it easy to build a p.P-controlied equalizer.
The signal path is deSigned for very low noise and distortion, resulting in very high performance, compatible with
PCM audio.

•
•
•
•
•
•

No volume controls required
Three-wire interface
14 bands, 25 steps each
±12 dB or ±6 dB gain ranges
Low noise and distortion
TTL, CMOS logic compatible

Applications
•
•
•
•
•

Hi-Fi equalizer
Receiver
Car stereo
Musical instrument
Tape equalization

• Mixer
• Volume controller

Connection Diagrams
Molded Chip Carrier Package

Dual-In-Une Package
21

All"

27

AiM!

26

A'M3

A.GND
A'M5
A'M.

18

AtN6

LCI.

A'M4

A'M7

AtN5

27

17

Voo

LCI

LCI

A.GND

28

16

DATA

LC2

LC9

AtNl

15

STROBE

LC3

LCI.

AtN2

I.

CLOCK

LC4

LCll

AtN3

13

D.GND

AjN4

12

Vss

LC5

LC12

LCI

LC13

LC7

LC14

¥Sa

VDD

TLlH/6753-26

Top View

OATA

D.GNO
16

CLOCK

Order Number LMC835V
See NS Package V28A

STROBE
TUH/6753-1

Top View
Order Number LMC835N
See NS Package N28B

1-172

m

I ~'" ~
LY

HO-160ECODER

LATCH

II •

is'
n

-

-All

LATCH AI

TI!!!!
OUT

II

II
II
II
II
II
II
II
II
II
II
II
II
II

8/C

Ll1i4.-..........
R5c

k

5.
:!:6 dB
28

OR

~

:!:12dB

Sb

~

RbC
Uk
25

R3c
R2c
RI.

~~

~rs..""".

PO
R5b55k
R... 25k
R3bllk

A'N'

RbZ
1.ak

ca
D;

~

:~:~~k
ROk3k

L -------- ----

3

'---

'--

AAM~M~~M~~'«'«~AA
II
11:1 I: II II :1 I; P II :

~

SELECTOR AI
800ST

RdC
Uk

A,., 0 - -

ii

I

I

~ ~=~m lit II ; ~J????????~tL?::
r----Ht~+tt

lIIIO
Uk
28

C

17

r-

A_GNO

~

,

A

II!;I
II
II II
II
II II
II II
II II
II II
II II
.. II
II II
II II
II II
.. II

n
II
II
II
II
II

:11
I
II
II
II
II
II
II
II
II
II
II
II
II

U
111I U I,I ;1 U ;
II I II I II II

II
II
II
II
II
II
II
II
II
II
II
II

II
II
II
II
II

II
II
II
II
II
II

I
II
II
III
II
I
II
II
II
II
II
II

~UIIUUUI I~J'

II
II

II
II

II
II
II

II
II
II
I
II
I;
II
I
II

II II

II
II
II
II
II
II
II

II
II
II
II
II
II
II
I
II
II
I
II

I
I
I
I
I
I
I
II
II
II
II
II

IW~I

.

~ ITTllT~r~-=rrrI1lII1I1l'rrr 111111 )IT

21

A,••

I
lC2

Lei

01
LC3

O'
lC4

09
lC5

Oa 0" OM ou ou
lCI

lC1

LCB

lC9

LCI.

o~

lCn

On
lCIZ

o~

lCia

ou
lCU
TUH/6753-2

9£~W'

II

Absolute Maximum Ratings

Operating Ratings

If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
18V
Supply Voltage, Voo-Vss
Allowable Input Voltage (Note 1)
Vss-0.3V
tOVoo+0.3V
-60"Cto + 150"C
Storage Temperature, T819
Lead Temperature (Soldering, 10 sec), N Pkg
+ 260"C
Lead Temperature, V Pkg
Vapor Phase (60 sec)
+215·C
Infrared (15 sec)
+ 220·C

Supply Voltage, Voo-VSS
Digital Ground (Pin 13)
Digital Input (Pins 14, 15, 16)
Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)
(Note 1)

5Vto 16V
VsstoVoo
VsstoVoo
Vssto Voo
-40"Cto +85·C

Operating Temperature, Tapr

Electrical Characteristics (Note 2) Voo=7.5V, VSS= -7.5V, A.GND=OV
LOGIC SECTION
Symbol

Parameter

Test Conditions

Typ

Tested
Limit
(Note 3)

Design
Limit
(Note 4)

Unit
(Limit)

0.D1
0.01
1.3
0.9

0.5
0.5
5
5

0.5
0.5
5
5

mA(Max)
mA(Max)
mA(Max)
mA(Max)

1.8

2.3

2.5

V (Min)

IDOL
ISSL
IOOH
ISSH

Supply Current

Pins 14,15,16 are OV
Pins 14,15, 16areOV
Pins 14, 15,16are5V
Pins 14,15,16 are 5V

VIH

High-Level Input Voltage

@Pins14, 15,16

VIL

Low-Level Input Voltage

@Pins14, 15, 16

0.9

0.6

0.4

V (Max)

@Pin14

2000

500

500

kHz (Max)

'0

Clock Frequency

1w"lSm

Width 01 STIi Input

See Figure 1

0.25

1

1

,,"s(Min)

!setuP

Data Setup Time

See Figure 1

0.25

1

1

,,"s(Min)

thold

Data Hold Time

See Figure 1

0.25

1

1

,,"s(Min)

tcs

Delay Irom Rising Edge 01 CLOCK
toSTS

See Figure 1

0.25

1

1

,,"s(Min)

liN

Input Current

@Plns 14, 15, 16 OV

(i)

-

Valid Above Input
Gain Code

-+

.-----------------------------------------------------------------------------~ ~

iii:

oco

Test Circuits

Co)

CI'I

VIII.

470

~-4~~~--------------------------------~~UR
+7.5V

680
25

680

680

680

680

680

680

r--,I

r-______~~=U~
r-__.:S'!;TR=OB;E~

2C
21
18
23
22
20
19
LC8 LC9 LClo LCll LC12 LC13 LC1.

CLOCK

LCl

LC2

LC3

LCC

7

8

5
lOOp

lOOp

lOOk

lOOk

680

680

680

I
I

D.GND
I
L __ .J

LMC835
A•••

WORD
GENERATOR

LC5

680

':'

-7.5V
470
>-....JItI~-----------------------------------oVDUTA

V•••

+15V

-15V
TUH16753-5

FIGURE 3. Test Circuit for AC Measurement

DATA

r--,I

r----=~

WORD
GENERATOR

I

D.GND

I

I

L __ .J
LMC835

VL2.3

VL5

VL6

V1.7

Vu

Vu

VL1D

VLll -7.5V
TLIH16753-6

FIGURE 4. Test Circuit for Leakage Current Measurement

1-177

II

U)

C')

CD
(.)

r---------------------------------------------------------------------------------,
Test Circuits (Continued)

r-----'

:E
...I

> .....~.....-oYLOUT

ILlNo-....-;;.......... ~

Tl/H/6753-7

FIGURE 5. I to V Converter

v·
CLOCK

8

10

CLOCK

111I74HCOO

11 ClK

Q

9
DATA

1oI1oI74HC74

MIoI74HCOO

12 D

Q 5

0

RC 15

2 CLK

INH 15

111I74HCI63

PR Q 5

CLKt-=2'-<1_+=3:t'ClK MM74HC74

IoIM74HC163
lOAD 9

2 0

1 lOAD

v.

D7 D6

os

8

0.,:6:""'-1----0 STROBE

D4 D3 D2 Dl DO
TL/H/6753-8

FIGURE 6. Simple Word Generator

Typical Performance Characteristics
Supply Current vs
Supply Voltage

....

!.
Ii

.
..E
:0
U

:0

2.0
!A-25'C
I .•
CE - DATA - STO - 5Y
1.6 O.IINO-A.8NO-OY
1.4
1.2
1.0
0.'
1/
0.6
0.4
~,"
0.2

Supply Current vs
Temperature
2.1
1.8
.. 1.6
100

......

12345678910
SUPPLY YOlTAGE (:t VI

!.

1.4

10

~:::T:~m-5V
O.GNO-A.BNO-OV
I••.

5 1.2

I

1.0
.. a.8
a.6
iii 0.4
0.2

Iss

E

a

Input Capacitance vs
Input Voltage

-50 -25

PINS 14, 15, 1.

I

O.GNO-A.BNO-OY

.---

9 Va. :t7.5Y, TA-ZS'C - r - -

---

'-I MHz

4

IJ

~

---- -.--

3

2
1
0 25 50 75 100 125
TEMPERATURE ('CI

a

0 1 2 3 4 5 6 7 • • 10
INPUT YOLTAGE (VI
TLlH/8753-9

1-178

Typical Performance Characteristics (Continued)

1.

Maximum Output Voltage
vs Supply Voltage

••

Maximum Output Voltage
vs Temperature

~u ~~.::.
••
7

1

i

V

•
5

-

~

--

•

:
1

1

D
01234S171.,D
SUPPLY VOLTAGE 12: V,

D
-II -25' IS so 7S 101 lZS
TEMI'I!IIATUII 1°C,

Distortion vs Frequency
@ ± 12 dB Range
D.l

!

!I

D••

•.

,..

01

',.

V'III

I.ODI

,.

•

!

-1Vnna

JIIII.

1lI11L

~~~

ir;

_

D• •

Gain vs Frequency
@ ± 12 dB Range (Boost)

r::-.....,~C":""-:::="'='...,.'"

~;':_"'T

11

•

1.'Dl~11111

;

~D._

•.012 t-Htf1~;::::jt:tmtttl
D'OO1 L..-...L-.L...L.j"j.JJu..L.-...J.....J.:;::':":=

-1

lD

lD

Gain vs Frequency
@ ± 6 dB Range (Boost)

t::~

!

I

I~'!:!'!

•1.

!

i

-.-.

-9

-"

-11

IIOK

-13
lD

--

.*•• ..-m

I.

11K
111
FllEUENCY IH.,

ll1K

".liliiii

,..2:7.5V

_

-

"8

_
1

2:12 dnANGE

-1

-2

UI
4 ••

-3
-4

-I

•

Gain vs Temperature
10
9

.... n .•• s-c

3d

,..
UI

-5

r'i !tIftltt""
I.
111
11K
FllEOUENCY IH.,

-1

-3
-5
-7

Gain vs Frequency
@ ± 6 dB Range (Cut)
1

..

,.

•

3

......
.+....

101
11K
FIIEUENCY 1Hz,

lD

Gain vs Frequency
@ ± 12 dB Range (Cut)

~ .... a7" ,._zrl:
~~~~~C+~~4

15
13

D.II I--MMi+tttt---t-+A,*ftl

,

O""'.........L...I..u..u.

'.1 D.I D.S 1
DUTPUT VDIIAGE IV_,

FIIEUENCY IH.,

us

•. 1 D.2
D.5 1
DUTPUT VDLTABE IV_,

t-Tiiifrt~IFlI:.~za!J-~H~
I....III:.;;."":.::F""'H·'-'-WoJ.u

D.IIIIZ
I.ODI

UDI 11L.:,lL;;:.:..;=
• .........IIIIL.
,. ...........
_ ...u. , _

1II1II(

Distortion vs Output Voltage
@ ±6dBRange

!

2:7.5V. TA.ZSoC:::
2:11 dlllANlE
--FLAT
....,
D.DI --+12d1

ID~~ ~===Ml!'.iiljJli~I,I)~-:·:~~I~1

D••'
D.0I5

....

D H so 7S 101 lH
TEIII'EIlATUIi 1°C,

.."...-=.-:--::=-=
v••
=.....==
.t

D.l

!

hTtTTnr-'i-m

D.DI

•

--

Distortion vs Output Voltage
@ ± 12 dB Range

D.OS

FREaUENCY IH.,

'.1

D."-SO-H

Distortion vs Frequency
@ ±6dBRange

~

va. IV....

,.

'a.17
D."

US

r; D."
0.012

-

Ii ....

D.l.."...-"""",.."..-=!:'!"O...".,..,_

2:7.5V. TA.HoC
2:11 .. WIllE
FLAT
-+12.

---

;!it ,."1

=D••

/

D.OI

1.14
1.03
1.12

~-

FLAT 1.1 _H•• THD < 1'4- I -

,
:

us

10

TA·HOC
2:11 .IRAIIIE FLAT
1.' _H•• THD,...-"WM .....

27k

+l5V

VOUfA

-15V
TL/H/8753-11

FIGURE 7. Stereo 7-Band Equalizer

TABLE I: Tuned Circuit Elements

Z1

fo(Hz)

r

Z1
Z2
Z3
Z4
Z5
Z6
Z7

63
160
400
1k
2.5k
6.3k
16k

CL(F)

RL(O)

Ro(O)

1p.

0.1p.

0.47p.
0.15p.

0.033p.
0.015p.
0.0068p.
0.0033p.
0.0015p.
680p

100k
100k
100k
82k
82k
62k
47k

680
680
680
680
680
680
680

Co(F)

0.068p.
0.022p.
0.01p.
0.0047p.

PIN 2. 3 DR 2&

PIN "LC"

Qo=3.5, Q12dB= 1.05

--,

Ico

I

lOOk

Ic~o I

I

L

I RL
I

L~

+

I
_ _ _ _ JI
-

Lo=CL RL

Ro

1

lo=~

Oo=~Co~02
RoOo
Q12dS=Ro+1590

LM833

(l590n-55k#l&k#11k#8kRa kll)

TL/H/8753-12

FIGURE 8. Tuned Circuit for S.tereo
7-Band Equalizer (Figure 7)

1-180

riii:

Typical Applications (Continued)

o
CD

Performance Characteristics (Circuit of Figure 7)
LMC835 Gain vs Frequency
LMC835 Gain vs Frequency
@ ± 12 dB Range
@ ± 12 dB Range
(1 kHz Boost or Cut)
(All Boost or Cut)

W
CII

1
4
-8.
16
lZ

lZ
16

41111

-8

i"iD

iZ 0
g-4

0

~-4

-lZ

-lZ

-16 L..LJ.WIIL.I.J.lUIIL...,I;l,
10
100
lK
10K
FREQUENCY (Hz)

-16
lOOK

I!'o

10

!z

iD
!!. 0

0

;1-2

:A_ z

-4

-4

-6

-6
-8

-8
10K

lOOK

8

;5

lK

10K

LMC835 Gain va Frequency
@ ±6dBRange
(1 kHz Booat or Cut)

81=Ri~~_m

100

lK

FREQUENCY (Hz)

LMC835 Gain va Frequency
@ ±6 dB Range
(All Boost or Cut)

10

100

lOOK

10

100

FREQUENCY (Hz)

lK

10K

lOOK

FREQUENCY (Hz)
TUH/6753-13

+15V

Uk

II

Z7k
V,.
470

> ...-O\f'\j'\r-------------o() VOUT
Z7k

.

p-.p-.r-.p-.p-•

":'

1
I
II
..
II
I Z8 II Zg1lZ10" Zl111Z1Z1
1111111111

":'

10k

+7.5V

lOOk

DATA
28

STROBE
27

A.GND A,.5

Z6

Ai••

Z5
A,.,

24

Z3

LCB

Lca

2Z
LC10

21

20

LCll LC12

19

18

17

LC13 LC14

VDD

LC6

Vss

LMC835
LCI

LCZ

5

LC3

LC4

6

LC5

8

10

LC7
11

12
CLOCK

....._-+

D.GND
L -_ _ _ _ -7.5V

.-..

..-..

11111111111111

I Zl II Z2 II Z3 II Z4 .. Z5 II Z6 II Z7 I
.....
111111111

-~.-~.-

FIGURE 9. 12-Band Equalizer
1-181

-~.-~

TUH/6753-14

Typical Applications (Continued)
TABLE II. Tuned Circuit Elements
PIN "LC"

QO=4.7, Q12dB= 1.4

Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12

fo(Hz)

Co(F)

16
31.5
63
125
250
500
1k
2k
4k
8k
16k
32k

3.3,...
15,...

1,...
0.39,...
0.22,...
0.1,...
0.047,...
0.022,...
0.01,...
0.0068,...
0.0033,...
0.0015,...

CL(F)

RL(O)

Ro(O)

0.47,...
0.22,...
0.1,...
0.068,...
0.033,...
0.015,...
0.01,...
0.0047,...
0.0022,...
0.001,...
680p
470p

100k
110k
100k
91k
82k
100k
82k
91k
110k
82k
62k
68k

680
680
680
680
680
680
680
680
680
680
680
510

PIN 26

r

--,

::~100k
I

RD

:

+

I

Lo=CL RL An
1

10= 2".JCQCO

.00=~Co~

I RL
- LM833
I
I
L.::: ____ .II

RoOo

Q12dB=RO+1590

(16901/-55k#16k#11k#8k#3 kll)

TL/H/6753-15

FIGURE 10. Tuned Circuit for
12·Band Equalizer (FIgure 9)

Performance Characteristics (Circuit of Figure 9)
12 Band Equalizer Application
LMC835 Gain vs Frequency
@ ±6dBRange
(All Boost or Cut)

LMC835 12 Band E.Q. Application
Gain vs Frequency
@ ± 12 dB Range
(1 kHz Boost or Cut)

., .~;,; ,.."'".h OI'''':''II''::''I.~~1I1lI

II

r~~IIIIII • •IIIIIII"'.IIIIII• • 1'1111
••• 11111 • •111111 • • 111111••• ,1111

1"-;'"

r.. 'r, ",',,&~: flT1r:'II
III
.'IIIIII'li U L~'H'J,I,lh .'Jll'l:

•• V.~ll'l"'.I."
,~,

!

i'U"tII.'ll~lh"

'1' "'.':,1' II '","j,',,:,a .11,'111

.. ,"",
.....

.....

'I.~·lh. \"jll'''.~~4'·'I.''~,~~~h

!

-2

.'-,

ii
!!.

I

z

..,.....,:'.,.- I. UI "",'...".".'I'
.. ......
"','1'.
.... r.o1','r,'
~~~'~!' I !,'~. ~!" !1'.,!~,~1.1!',;'!'~ ~!' ~!!'
"~,~,~,,.,.-

~

-

~~-.'

100

lK

10K

t:mh

41111

4

ii_

'.'

0

-8
-12

-6
-4 • •
-8
10

RfIilFFf

128Bl1H

-16
10

100

lOOK

1K

10K

lOOK

FREQUENCY (Hz)

FREQUENCY (Hz)

12 Band Equalizer Application
LMC835 Gain vs Frequency
@ ± 12dBRange
(All Boost or Cut)

!~

LMC835 12 Band E.Q. Application
Gain vs Frequency
@ ±6dBRange
(1 kHz Boost or Cut)

11~lIIIr!!mm~.~

8

12

6

iz

0

~

-4

-8

0
-2

-4

-12

-6

-16

-8
10

100

lK

10K

lOOK

10

FREQUENCY (Hz)

100

lK

10K

lOOK

FREQUENCY (Hz)
TL/H/6753-16

1·182

Typical Applications (Continued)
PIN "LC"

PIN 2. 3 OR 26

Lo -

r~--'I

ICo

C... AL. AO
1

Fo-~

lOOk

I

I

ICL

I

I
I
I

I
I
I

v+

00 - JCoR(l.

AoOo
Q'2dB - AO

+ 15'C

L.I ____ J

(159G1l-55kQI6kQ11kQ8kn kill
TL/H/6753-25

v..
1.

V",.~ "+--1~-f+"~

........:..t 1 - - - - - - - - - - o O V••18

>"'~w.

lOOk

'-,,-,,-,,-,r-,'-"-'

1111111111111'
I ZII1 Z211 Z311 Z4 II Z5 II Z611 Z11
,
..
..
II
II
"
II
I

v••

r - - - - + V.. 8V TO 15V
DATA

STR08E

1---.

v+ 0 - -............

T

100

CLOCK

"F

D.GND

lOOk

> ..........\M,....;.t t - - - - - - - - - - O v "•••

TUH/6753-17

The V2+ output is used to bias the gyrators

FIGURE 11. Single Supply Stereo Equalizer

1-183

II

an

(II)

~

Typical Applications (Continued)

:!
Your.

YOUTI

TL/H/6753-18

TLlH/6753-19

FIGURE 12. Stereo 7-Input/1-output Mixers
(THD is not as low as equalizer circuit)

FIGURE 13. Stereo Volume Control, Very Low THD

+5Y

. ._'-..;.;;;......_ _ _~~~ - , - IOn

REsET

m
LMC836
DATA

1-----ISTRoii
D.GNO

TL/H/6753-20

FIGURE 14. LMC835-COP404L CPU Interface

1-184

riii:

Typical Applications (Continued)

o
CD

Sample Subroutine Program for Figure 14, LMC835-COP404L CPU Interface

W
CI'I

HEX
CODE

LABEL

MNEMONICS

3F

LMC835:

LBI

05

SEND

LD

;RAMDATA TO A

SC

; SET CARRY

335F

OGI

; SET PORT G= 1111, OPEN THE AND GATES

4F

; SWAP A AND SIO, CLOCK START

05

XAS
LD

07

XDS

; SWAP A AND RAMDATA. RAMADDRESS=RAMADDRESS-1

22

COMMENTS
3F

;POINT TO RAMADDRESS 3F

;RAMDATA TO A. MAKE SURE A = DATA

05

LD

;RAMDATA TO A

4F

XAS

;SWAPAANDSIO

05

LD

;RAMDATA TO A. MAKE SURE A=NEWDATA

07

; SWAP A AND RAMDATA. RAMADDRESS=RAMADDRESS-1

32

XDS
RC

4F

XAS

335D

OGJ

13

;SET PORT G=1101, MAKE STROBE LOW

335B

OGI

11

;SET PORT G=1011. MAKE STROBE HIGH. CLOSE THE

4E

CBA

43

AISC

48

RET

80

JP

;RESET CARRY
; SWAP A AND SIO. CLOCK STOP

GATES
;BD TOA
3

;RAMADDRESS<3C THEN RETURN

SEND

RAM
ADDRESS
3C

DATA

COMMENTS
;GAIN DATA D4-D7

3D

DATA

;GAIN DATA DO-D3

3E

DATA

;BAND DATA D4-D7

3F

DATA

;BAND DATA DO-D3

II

Application Hints
SWITCHING NOISE
The LMC835 uses CMOS analog switches that have small
leakages (less than 50 nA). When a band is selected for flat
gain, all the switches in that band are open and the resonator circuit is not connected to the LMC835 resistor network.
It is only in the flat mode that the small leakage currents can
cause problems. The input to the resonator circuit is usually
a capacitor and the leakage currents will slowly charge up
this capacitor to a large voltage if there is no resistive path
to limit it. When the band is set to any value other than flat,
the charge on the capacitor will be discharged by the resistor network and there will be a transient at the output. To
limit the size of this transient, RLEAK is necessary.

SIMPLE WORD GENERATOR (Figure 6)
Circuit operation revolves around an MM74HC165 parallelin/serial-out shift register. Data bits DO through D7 are applied to the parallel of the MM74HC165 from 8 toggle
switches. The bits are shifted out to the DATA input of the
LMC835 in sync with the clock. When all data bits have
been loaded, CLOCK is inhibited and a STROBE pulse is
generated: this sequence is initiated by a START pulse.
LMC835-COP404L CPU INTERFACE (Refer to Figure 14)
The diagram shows AND gates between the COP and the
LMC835. These permit G2 to inhibit the CLOCK and DATA
lines (SK and SO) during a STROBE (G1) pulse. This function may also be implemented in software. As shown in Figure 2, the data groups are shifted in DO first. Data is loaded
on positive clock edges.

HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE
CURRENT (Refer to Figures 7 and 8)
To avoid switching noise due to leakage currents when
changing the gain, it is recommended to put RLEAK= 100
kO between Pin 3 and Pin 5-11 each, Pin 26 and Pin 1224 each. The resistor limits the voltage that the capacitor
can charge to, with minimal effects on the equalization. The
frequency response change due to RLEAK are shown in Figure 15. The gain error is only 0.2 dB and Q error is only 5%
at 12 dB boost or cut.

POWER SUPPLIES
These applications show LM317/337 regulators for the
± 7.5V supplies for the LMC835. Since the latter draws only
5 mA max., 1k series dropping resistors from the ± 15V op
amp supply and a pair of 7.5V zeners and bypass caps will
also suffice.

1-185

Application Hints (Continued)
MODEL

RESULT

> ...-OVoUT

,
t-.6!NIt---'

12dB

I----''---.----::I-=c---

II.adB I---'-r-I--+_~~

I

I

OdB
.... 110

TUH/6753-21

TL/H/6753-22

FIGURE 15. Effect of RLEAK

REDUCING EXTERNAL COMPONENTS
The typical application shown in Figure 7 is switching noise
free. The DC-coupled circuit in Figure 16 is also switching
noise free, except at 12 dB/6 dB switch tum ON/OFF. This
switching noise is caused by the lbias and Voffset of the op

amps. Selecting a low Ibias and Voffset op amp can minimize
the switching noise due to the 12 dB/6 dB switch. The DCcoupled application can also eliminate the RF= 100k resistors with only a 0.5 dB gain error at 12 dB boost or cut.

ACCOUPLING

DC COUPLING

·.,r

lOOk

LMCB35

LMCB35

TUH/6753-24
TL/H/6753-23

FIGURE 16. Reducing External Components

1-186

~National

~ semiconductor

LMC1982
Digitally-Controlled Stereo Tone
and Volume Circuit with Two Selectable Stereo Inputs
General Description
The LMC1982 is a monolithic integrated circuit that provides
volume, balance, tone (bass and treble), enhanced stereo,
and loudness controls and selection between two pairs of
stereo inputs. These functions are digitally controlled
through a three-wire communication interface. There are
two digital inputs for easy interface to other audio peripherals such as stereo decoders. The LMC1982 is designed for
line level input signals (300 mV-2V) and has a maximum
gain of -0.5 dB. Volume is set at minimum and tone controls are flat when supply voltage is first applied.
Low noise and distortion result from using analog switches
and poly-silicon resistor networks in the signal path.
Additional tone control can be achieved using the LMC835
stereo 7-band graphic equalizer connected to the
LMC1982's SELECT OUT/SELECT IN external processor
loop.

Features
• Low noise and distortion
• Two pairs of stereo inputs

•
•
•
•
•
•
•
•
•
•
•

Enhanced stereo function
Loudness compensation
40 position 2 dB/step volume attenuator plus mute
Independent left and right volume controls
Low noise-suitable for use with DNR~ and Dolby~
noise reduction
External processor loop
Signal handling suitable for compact discs
Pop-free switching
Serially programmable: INTERMETAL bus (1M) interface
6V to 12V single supply operation
28 Pin DIP or PLCC package

Applications
•
•
•
•
•

Stereo television
Music reproduction systems
Sound reinforcement systems
Electronic music (MIDI)
Personal computer audio control

Block and Connection Diagrams
23
22
R SElECT OUT R SELECT IN

21
20
R TONE IN R TONE OUT

19
R OP AMP OUT

25~~--"'"

R. INPUT 1

4
L. INPUT 1
24
R. INPUT 2

18
R LOUDNESS

l

17
R ENHANCE ST.
6.5k.D.

Y+/2

16
RIGHT
OUT

.'50k.D.

INPUT
AND
MODE
SELECT

28

1.5k.D.

5

LOGIC
AND
CONTROL

L...+-_______.... • Loudn...

L. INPUT2

50k.D.

·r

6
7
L SELECT OUT L SELECT IN

8
9
L TONE IN L TONE OUT

10
L OP AMP OUT

(EnhanCed Stereo

11

12

L LOUDNESS

L ENHANCE ST.

2

13

LEFT

, 50k.D.
Y+/2

50k.D.

27

10

DIGITAL INPUT 1
3
DIGITAL INPUT 2

1.5k.D.

BYP~~ 0-+--1

OATA
1
CLK

OUT

TL/H/11028-1

1-187

•

Absolute Maximum Ratings (Notes 1 and 2)
-65"Cto +15O"C
Storage Temperature
Lead Temperature
N Package, (Soldering, 10 Seconds)
+26O"C
215"C
V Package, (Vapor Phase, 60 Sec9nds)
220"C
Infrared, (15 Seconds)
2kV
ESD Susceptabillty (Note 5)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Salea
Office/Distributors for availability and speclflcatlons.
Supply Voltage (V+ - GND)
15V
GND - 0.2VtoV+ + 0.2V
Voltage at any Pin
Input Current at any Pin (Note 3)
5mA
Package Input Current (Note 3)
20mA
Power Dissipation (Note 4)
500mW
Junction Temperature
+ 125"C

Operating Ratings (Notes 1 and 2)
Temperature Range
TMIN s: TA s: TMAX
LMC1982CIN, LMC1982CIV
-4O"C s: TA s: +85°C
Supply Voltage Range (V+ - V-)
6Vto 12V

Electrical Characteristics The following specifICations apply for V+ = 9V, fiN = 1 kHz~ Input signal
(300 mV) applied to INPUT 1, volume = 0 dB, bass = 0 dB, treble = 0 dB, enhanced stereo is off, and loudness is off unless
otherwise specified. All limits apply for TA = TJ = + 25°C.
Symbol

Parameter

Conditions

Is

Supply Current

VIN

Input Voltage

Clipping Level (1,.0% THD),
Select Out (Pins 6, 23)

THD

Total Harmonic Distortion

Left and Right channels; .
Output Pins 13, 16
VIN = 0.3 Vrms;
fiN = 100 HZ,1 kHz,10 kHz
VIN = 2.0Vrms;
fiN = 100 HZ,1 kHz
VIN = 2.0 Vrms;
fiN = 10 kHz
VIN = 0.5 Vrms; Bass and Treble
Tone Controls Set at Maximum
VIN = 0.3 Vrms; Volume
Attenuator at - 20 dB, Bass and Treble
Tone Controls Set at Maximum

DC Shifts

VIN = 0.3 Vrms; Between Any
Two Adjacent Control Settings
VIN = 0.3 Vrms;
All Mode and Input Positions

Typical
(Note 6)

Umlt
(Note 7)

Unit
(Umlt)

15

25

mA(max)

2.3

2.0

0.008

0.1

% (max)

0.4

1.0

% (max)

0.5

1.0

% (max)

0.07

0.5

% (max)

0.06

0.15

% (max)

2.0

4.0

mV(max)

18

20

mV(max)

Vrms(min)

ROUT

AC Output Impedance

Pins 6, 23, (4700. to Ground at Input)
Pins 13,16

150
26

200
40

o (max)
o (max)

RIN

AC Input Impedance

Pins 4, 5, 24, 25

50

72
35

kO(max)
kO(min)

Volume Attenuator Range

Pins 13, 16; Volume
Attenuation at 010001 OXXXoooooO (0 dB)
01 0001 OXXX1 01 XXX (80 dB);
(Relative to Attenuation at
the 0 dB Setting)

0.5

1.5

dB (max)

80

78
82

dB (min)
dB (max)

All Volume Attenuation Settings
from 01 0001 OXXX1 01XXX (80 dB) to
0100010XXXOOOOoo (0 dB) (Note 9)

2.0

1.5
2.5

dB (min)
dB (min)

Channel-to-Channel Volume
Tracking Error

All Volume Attenuation Settings
from 010001 OXXX1 01 XXX (80 dB)
to 010001 OXXXOOOOOO (0 dB)

±0.1

±1.5

dB (min)

Mute Attenuation

VIN

105

86

dB (max)

Volume Step Size

= 1.0 Vrms

1-188

Electrical Characteristics The following specifications apply for V+ = 9V, fiN = 1 kHz, input signal (300 mV)
applied to INPUT 1, volume = 0 dB, bass = 0 dB, treble = 0 dB, enhanced stereo is off, and loudness is off unless otherwise
specified. All limits apply for TA = TJ = + 25°C. (Continued)
Symbol

Parameter

Conditions

Typical
(Note 6)

Limit
(Note 7)

Unit
(Umlt)

Bass Gain Range

fiN

= 100Hz,Pins13,16

±12

±10.0
±14.0

dB (min)
dB (max)

Bass Tracking Error

fiN

= 100 Hz, Pins 13,16

±0.1

±1.5

dB (max)

Bass Step Size

fiN = 100 Hz, Pins 13,16
(Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

Treble Gain Range

fiN

= 10 kHz, Pins 13,16

±12

±10.0
±14.0

dB (min)
dB (max)

Treble Tracking Error

fiN

= 10 kHz, Pins 13, 16

±0.1

±1.5

dB (max)

Treble Step Size

fiN = 10kHz, Pins 13, 16
(Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

Enhanced Stereo Cross Coupling

(Note 10)

-4.4

-2.5
-6.9

dB (min)
dB (max)

Frequency Response

VIN Applied to Input 1 and Input 2;
fiN = 20 Hz - 20 kHz
(Relative to Signal Amplitude at 1 kHz)

±0.1

±1.0

dB (max)

Volume Attenuator = 40 dB, Loudness
on (See Figure 5)
Gain at 100 Hz (Referenced
to Gain at 1 kHz)
Gain at 10kHz (Referenced
to Gain at 1 kHz)

11.5

13.5
9.5
8.5
4.5

dB (max)
dB (min)
dB (max)
dB (min)

Loudness

6.5

Signal-to-Noise Ratio

VIN = 1.0 Vrms, A Weighted,
Measured at 1 kHz, Rs = 470.0.

95

90

Channel Balance

All Volume Settings

0.2

1.0

dB (max)

Channel Separation

Input Pins 4, 25: Output Pins 13, 16;
VIN = 1.0 Vrms (Note 8)

80

60

dB (min)

Input-Input Isolation

470.0. to AC Ground on Unused Input

95

60

dB (min)

PSSR

Power Supply Rejection Ratio

V+ = 9 Voc; 200 mVrms , 100 Hz
Sinewave Applied to Pin 26

32

28

dB (min)

dB (min)

fCLK

Clock Frequency

5.0

1.0

MHz (max)

VIN(l)

Logic "1" Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins 2, 3

1.3
2.9

2.0
5.5

V (min)
V (min)

VIN(O)

Logic "0" Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins 2, 3

0.4
1.2

0.8
3.5

V (max)
V (max)

Logic "1" Output Voltage
Pin 28 (1M Bus)
2.0
V (min)
VOUTill
V (max)
Logic "0" Output Voltage
Pin 28 (1M Bus)
0.4
0.8
VOUTCOI
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the deivee may occur. Operating Ratings Indicate condifions for which the device is
functional. but do not guarantee specific perfonnance IimHs. For guaranteed specifications and test condHions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test condHions listed. Some perfonnance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltsges are specHied with respect to ground.
Note 3: When the input voltsge (YIN) at any pin exceeds the power supply voltsges (YIN < V- or VIN > V+) the absolute value of the current at thai pin should be
IimHed to 5 rnA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voItsges with 5 mA current limH to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 9JA, and the ambient temperature TA. The maximum
allowable power dissipation is Po = (TJMAX - TAl/9JA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMCl982CIN, TJMAX =
+ 125"C, and the typical junction-Io-ambient thermal resistance, when board mounted, Is 67"CfW.
Note 5: Human body model; tOO pF discharged through a t.5 kG resistor.
Note 6: Typicals are at TJ = + 25"C and represent the most likely parametric norm.
Note 7: UmHs are guaranteed to National's AOOL (Average Outgoing OualHy Level).
Note 8: The Input-Input Isolation is tested by driving one input and measuring the output when the undriven input are selectad.
Note 9: The Volume Step Size is defined as the change in attenuation between any two adjacent volume attenuation settings. The nominal Valuma Step Size is
2 dB.
Note 10: Enhanced Stereo Cross Coupling is a measure of the ratio between the undriven right channel output signal and the driven left channel output Signal. It is
measured by driving the left inputs with a 300 mVrm• signal while the right inputs are grounded.

1-189

II

Typical Performance Characteristics
Supply Current
vs Supply Voltage
30

~

.s

I

TA =25"C

TA

V

V+=9V

25

15

0.05

=

RL
THO= 1~
~~~me Attenuator

~

10

is

Your =1Vrma

-

Q.6

!rl

0..4

'is"
!!l
z

0.2

:!:;!

'\

r-

o
lD

o

100

THDvsVIN
(VOUT Constant)
1.0
TA=25OC
Y+=9V

Output Pins: 13. 16

z

t;

D.S

~

iJ

-VOUT""30mVrml

i
:0

D.03

~

rt

VOUT=IOOmVrma

Vour =300mVfIIIII

0.0

0.0

1.0

D.S

~

2D

60

SO

10

100

lk

10k

lOOk

FREQUENCY (Hz)

vs Frequency

1.5

~

0.06

~

YIN = 1Vrma

J

D.02

0.01
0.00

2.5

2.0

T.. =2SOC
Y+=9V
Input Pins: 4, 25
Output Pins: 13, 16
Tone nat

0.07

O.os

III0

:!:;!

'-

D.08

Ii;
is

Right Output- (Left ohann.! drfven)
Left Output -_ ••• (Right channel driven)

~

!l1

I,...

Mute Gain

g

Input Pins: ".25

III0

-105

z

THD vs Frequency

.I.

z

0

r---r-;~=:-----,---,

VOLUME ATTENUATION (dB)

AC LOAD IYPEDANCE (kJl)

g

-70

-110

3

10D

10

m
~

1\

I

1

Channel Separation
vs Frequency

\

Tone Flat

1
\

::II

'\

AC LOAD IMPEDANCE (kJl)

V+=9V
Input Pins: Grounded
Output Pins: 13.16 Tone Flat

~~~~! ~1~:~u6~t:03n 1= ~IJB

r-

:;!

\

0.01

16

TA = 25°C

IIIII
IIIII

V"'=9V

=0 dB

Volume Attenuation
Tone Flat

0.00
1~

12

CCIR Output Noise
vs Volume Setting

T.=25"C

0.02

SUPPLY VOLTAGE (V)

THDvs
Load Impedance

-

rr-

Output Pin.: 13. 16

0.03

:;!
10

SUPPLY VOLTAGE (V)

O.S

I
i;!

2

12

v+ = 9V
Vour= 1Vrms

~

o oJ

o

-

;!

/

IIIIII
b.8±lli

0.04

~

/

V

Ii;

/

TA =25"C

r-

z
0

Tone Flat

,/

10

g

=:t

g

IL

Output Pins: 13, 16

.,...v

THDvs
Load Impedance

=250C

Y+=9V

/

20

i

Output Voltage
vs Supply Voltage

10

-

/

1I
k-".

.........-'vIN =O.3Vnns
100

1Ic

10k

lOOk

FREQUENCY (Hz)

INPUT VOLTAGE (V"".)

Tone Control Response
with Equal Bass and
Treble Control Settings

FREQUENCY (Hz)

Select Input Impedance
vs Frequency

Loudness Response
vs Frequency

lM,----,---,,---,----,

OdS

TA. = 25°C

S

-2OdB

~

I

;~dB

~

'"

~

~ -&OdS

,

3:

I

V+=9V
Inputs: pins 7,22

MAX CUT

tOOk 1-=:-,...."'"1:. .--\----+----1

10k

z

-8DdS

~

.....- ....

IkL-_-L_ _~_~·A~X~'~OO=~~
10

100

Ik

10k

FREQUENCY (Hz)

lOOk

100

Ik

10k

FREQUENCY (Hz)

10Dk

ID

100

I.

10k

lOOk

FREQUENCY (Hz)
TLlH111028-3

1-190

r-

iii:

Connection Diagram

0.....
CC)

~

GO
N

:0

CLOCK

28

DATA

DIGITAL INPUT I

27

10

5

15

DIGITAL INPUT2

26

v+

~

LEFT INPUTI

25

RIGHT INPUT I

""

LEFT INPUT 2

24

RIGHT INPUT 2

LEFT SELECT OUTPUT
LEFT SELECT INPUT

LMCI982

LEFT TONE INPUT
LEFT TONE OUTPUT

15

.....
g"
0

0

~

:>;

~

~ 01~

~

~

23

RIGHT SELECT OUTPUT

22

RIGHT SELECT INPUT

V+

26

18

RIGHT LOUDNESS

21

RIGHT TONE INPUT

ID

27

17

RIGHT ENHANCED STEREO

20

RIGHT TONE OUTPUT

DATA

28

16

RIGHT OUTPUT

LEFT OP AMP OUTPUT

10

19

RIGHT OP AMP OUTPUT

LEFT LOUDNESS

11

18

RIGHT LOUDNESS

LEFT ENHANCED STEREO

12

17

RIGHT ENHANCED STEREO

LEFT OUTPUT

13

16

RIGHT OUTPUT

BYPASS

14

15

GROUND

LMC1982

15

GROUND

DIGITAL INPUT 1

14

BYPASS

DIGITAL INPUT 2

13

LEFT OUTPUT

LEFT INPUT 1

12

LEFT ENHANCED STEREO

CLOCK

N

~

TL/H/ll028-2

Top View

~

~

6

~

'"
~ ~ 6~ ~ tl~
""
~

e g "... g
t:
:>; §
':f
~
~
§
~

~ III~

Order Number LMC1982CIN
See NS Package Number N28B

~

~

~

z

..
0

~

TL/H/l1028-12

Top View
Order Number LMC1982CIV
See NS Package Number V28A

Pin Description
The INTER METAL (1M) Bus clock is applied to the CLOCK pin. This input accepts
a TTL or CMOS level signal. The input is
used to clock the DATA signal. A data bit
must be valid on the rising clock edge.
DIGITAL INPUT Internally tied high to V+ through a 30 kO
1 & 2 (2, 3)
pull-up resistor, these inputs allow a peripheral device to place any single-bit, active
low digital information onto the 1M Bus. It is
then sent out to the contrOlling device
through the DATA pin. Examples of such
information could include indication of the
presence of a Second Audio Program
(SAP) or an Frvt stereo carrier.
INPUTS 1 & 2 These are the LMC1982's two stereo input
(4, 25; 5, 24)
pairs.
CLK (1)

SELECT OUT
(6,23)

These are the inputs that an external signal
processor uses to return a signal to the
LMC1982. These pins should be capacitively coupled to pins 6 and 23, respectively, if no external processor is used.

TONE IN
(8,21)

These are the inputs to the tone control
amplifier. See the Application Information
section titled "Tone Control Response".

Tone control amplifier output. See the Application Information section titled "Tone
Control Response".

OPAMP
OUT (10,19)

These outputs are used with external tone
control capacitors. Internally, this output is
applied to the volume attenuators.

LOUDNESS
(11, 18)

The output signal on these pins is a voltage
taken from the volume attenuator's
-40 dB tap point. An external R-C network is connected to these pins.

ENHANCED
STEREO
(12,17)

An external R-C network is connected
across these pins. This provides left-right
channel cross-coupling and cancellation to
create an enhanced stereo channel separation effect.
The output Signal from these pins drives a
stereo power amplifier. The output can typically sink 1 mA.
A 10 poF capacitor is connected between
this pin and ground to provide an AC
ground for the internal half-supply voltage
reference.

MAIN
OUTPUT
(13,16)

The selected INPUT signal is available at
this output. This feature allows external signal processors such as noise reduction or
graphic equalizers to be used. This output
can typically sink 1 mA. These pins should
be capacitively coupled to pins 7 and 22,
respectively, if no external processor is
used.

SELECT IN
(7,22)

TONE OUT
(9,20)

BVPASS(14)

GROUND (15) This pin is connected to analog ground.
V+ (26)
This is the power supply connection. The
LMC1982 is operational with supply voltages from 6V to 12V. This pin should be
bypassed to ground through a 1.0 poF capacitor.

1-191

II

~

g:
....
o

::&
....I

,---------------------------------------------------------------------------------,
Pin Description (Continued)
10 (27)

This is the IDENTITY digital input that, when
low, signals the LMC1982 to receive, from a
controlling device, a device address (40H47H), present on the DATA line.

DATA (28)

This is the serial data input for communications sent by a controller. The controller must
have open drain outputs used with external
pull-up resistors. The data rate has a maximum frequency of 1 MHz. The LMC1982 requires 16 bits of data to control or change a
function: the first 8 bits select the LMC1982
and one of eight functions. The final eight bits
set the function to a desired value. The data
must be valid on the rising edge of the CLOCK
input signal.

TABLE I. 1M Bus Programming Codes for LMC1982
Address
(A7-AO)

Function

Data

Function
Selected

01000000

Input Select + Mute

XXXXXXOO
XXXXXX01
XXXXXX10
XXXXXX11

INPUT1
INPUT2
N/A
MUTE

01000001

Loudness, Enhanced Stereo

XXXXXXOO

Loudness OFF
Enhanced Stereo OFF
Loudness ON
Enhanced Stereo OFF
Loudness OFF
Enhanced Stereo ON
Loudness ON
Enhanced Stereo ON

XXXXXX01
XXXXXX10
XXXXXX11
01000010

Bass

XXXXOOOO
XXXX0011
XXXX0110
XXXX1001
XXXX11XX

-12dB
-SdB
FLAT
+SdB
+12dB

01000011

Treble

XXXXOOOO
XXXX0011
XXXX0110
XXXX1001
XXXX11XX

-12dB
-SdB
FLAT
+SdB
+12dB

01000100

Left Volume

XXOOOOOO
XX010100
XX101XXX
XX11XXXX

OdB
-40dB
-80dB
-80 dB

01000101

Right Volume

XXOOOOOO
XX010100
XX1 01 XXX
XX11XXXX

OdB
-40 dB
-80 dB
-80 dB

01000110

Mode Select

XXXXX100
XXXXX101
XXXXX11X

Left Mono
Stereo
Right Mono

01000111

Read Digital Input 1
or
Digital Input 2
onlM Bus

XXXXXXD1DO

1-192

DO
D1

= Digital Input 1
= Digitallnput 2

r----------------------------------------------------------------------,~

~

General Information
The lMC1982 is a CMOS/bipolar building block intended
for high fidelity audio signal processing. It is designed for
line level inputs signals (300 mV - 2V) and has a maximum
gain of -0.5 dB. While the lMC1982 is manufactured with
CMOS processing, NPN transistors are used to build low
noise op amps. The combination of CMOS switches, bipolar
op amps, and poly-silicon resistors make it possible to
achieve an order of magnitude quality improvement over
other bipolar circuits that use analog multipliers to accomplish gain adjustment. Internal circuits set the volume to
minimum, tone controls to flat, the mute to on, and all other
functions off when power is first applied. Individual left and
right volume controls are software programmed to achieve

the stereo balance function. Figure 1 shows the connection
diagram of a typical lMC1982 application.
The lMC1982 has internal decoding logic that allows a microprocessor (p.P) or microcontroller (p.C) to communicate
directly to the audio control circuitry through an INTERMETAl (1M) Bus interface. This three-wire interface consists of a
bi-directional DATA line, a Clock (ClK) input line, and an
Identity (10) line. Address and function selection data
(8 bits) are serially shifted from the controller to the
lMC1982. This is followed by 8 bits of function value data.
Data present in the internal shift register is latched and the
instruction is executed.

DIGITAL DIGITAL
INPUT 2 INPUTI elK DATA

240 PF~;;....::::.:.::::......_~
12
0.22 P F:
13

+

10

17

1:0.22PF

16

14

II

i·Skll

15

.I
10"j;F

~

N

240pF

I

l.Sk~

n
.....

10kll

680kll

lOUT

ROUT

0.047 pF
TL/H/ll028-5

FIGURE 1. Typical Application

1-193

Application lriformation
couple the SELECT OUT signals directly to pins 7 and 22,
respetively.

INPUT SELECTOR
The LMC1982's inpllt selector and mode control are shown
in Figure 2. The input selector selects one of two stereo
signal sources or a mute function with typical attenuation of
100 dB. The selected signals are then sent to a mode control matrix. As shown in Table I, the matrix provides normal
stereo or can direct either channel to both LEFT or RIGHT
SELECT OUTPUTs. The third matrix mode is normal stereo.
The control matrix output is buffered and appears on each
channel's respective SELECT OUT pin (6, 23). Switching
noise is kept to a minimum when mute is selected by using a
50 kG bias resistor.

MINIMUM LOAD IMPEDANCE
The LMC1982 employs emitter-followers to buffer the selected stereo channels. The buffered signals are available
at pins 6 and 23 (SELECT OUT). The SELECT OUT buffers
operate with a typical bias current 1 mA.
The Electrical Specifications table lists a maximum input signal of 2.0 Vrms (2.5 VpeaiJ for 1 % THO at the SELECT OUT
pins. This distortion level is achieved when the minimum AC
load impedance seen by the SELECT OUT pins is 2.5 kG
(2.5v/1 mAl. Using lower load impedances resul1s in clipping at lower output levels. If the load impedance is DC-coupled, an increased quiescent current can flow. Latch-up may
occur if the total emitter current exceeds 5 mA. Thus, maximum output voltage can be increased and much lower distortion levels can be achieved using load impedances of at
least 25 kG.

Noise performance is optimized through the use of emitter
followers in the mode control matrix's output. Internal 50 kG
resistors are connected to each input selector pin to provide
the proper bias point for the emitter follower buffers. Each
internal 50 kG bias resistor is connected to a common halfsupply (V+ /2) source. This produces a voltage at pins 6
and 23 (SELECT OUT) that is 1.4V below V+/2 (typically
3.W with V+ = 9V). Since a DC voltage is present at the
input pins (4, 5, 24, and 25), input signal should be AC coupled through a 1 /LF capacitor.

INPUT IMPEDANCE
The input impedance of pins 4, 5, 24 and 25 is defined by
internal bias resistors and is typically 50 kG.

The output signal at pins 6 and 23 can be used to drive
exteral audio processing circuits such as noise reduction
(LM1894-DNR or Dolby) or graphic equalizers (LMC835). It
is important that if any noise reduction is used it be placed
ahead of any tone controls or equalizers in the external circuit path to preserve the frequency spectrum of the selected input signal. Otherwise, any frequency equalization could
prevent the proper operation of the noise reduction circuit. If
no external processor is used, a capacitor should be used to

The SELECT IN pins have an input impedance that varies
with the BASE and TREBLE control settings. The input impedance is 100 kG at DC and 19 kG at 1 kHz when the
controls are set at 0 dB. Minimum input impedance of
30.4 kG at DC and 16 kG at 1 kHz occurs when maximum
boost is selected. At 10kHz the minimum input impedance,
with the tone controls flat, is 6.8 kG and, with the tone controls at maximum boost, is 2.5 kG.

V +/2

50 kllx4

v+
RIGHT INPUT 1 0-.....--1-+-+---<),.
RIGHT INPUT 2 0----;--11--0

51: Inpu! Soloc!

52: Iotodo Soloc!

RIGHT SELECT OUT

V+/2

50 kll x 4

v+
LEFT INPUT 1
LEFT INPUT 2

o--+-t--ll-t--- ......1-0 OUT
lEFT

•

lTONEIN

10

LTONE OUT

11

12

LOPAIIIPOUT LLOUDNESS

TLlH/11279-1

1-198

!i:

Absolute Maximum Ratings (Notes 1 and 2)
Storage Temperature

please contact the National Semiconductor Sales
OffIce/DIstrIbutors for availability and specifications.

Lead Temperature
N Package, (Soldering, 10 Seconds)
V Package, (Vapor Phase, 60 Seconds)
Infrared, (15 Seconds)

Supply Voltage (V+ - GND)

lSV
GND - 0.2V to V+ + 0.2V

Voltage at any Pin
Input Current at any Pin (Note 3)
Package Input Current (Note 3)

20mA

Power Dissipation (Note 4)

SOOmW

Junction Temperature

+ 12S·C

-6S·C to + lSO"C

w

+26O"C
21S·C
220"C

ESO Susceptability (Note 5)

SmA

2kV

Operating Ratings (Notes 1 and 2)
Temperature Range
LMC1983CIN, LMC1983CIV

TMIN S; TA S; TMAX
-40·C S; TA S; +8S·C

Supply Voltage Range (V+ - V-)

6Vt012V

Electrical Characteristics
(300 mV) applied to INPUT 1, volume
limits apply for T A = T J = + 2S·C.
Symbol

=

The following specifications apply for V+ = 9V, fiN = 1 kHz, input signal
0 dB, bass = 0 dB, treble = 0 dB, and loudness is off unless otherwise specified. All
Typical
(Note 6)

Limit
(Note 7)

Unit
(Umlt)

15

25

mA(max)

2.3

2.0

0.008

0.1

% (max)

0.4

1.0

% (max)

0.5

1.0

% (max)

0.07

0.5

% (max)

0.06

0.15

% (max)

2.0

4.0

mV(max)

18

20

mV(max)

Pins 7, 22, (4700 to Ground at Input)
Pins 13,16

150
26

200

40

o (max)
o (max)

AC Input Impedance

Pins 4, 5, 23, 24, 25

50

72
35

kO(max)
kO(min)

Volume Attenuator Range

Pins 13,16; Volume
Attenuation at 010001 OXXXOOOOOO (0 dB)
01 0001 OXXXl 01 XXX (80 dB);
(Relative to Attenuation at
the 0 dB Setting)

0.5

1.5

dB (max)

80

78
82

dB (min)
dB (max)

2.0

1.5
2.5

dB (min)
dB (min)

±0.1

±l.S

dB (min)

±2.0

dB (min)

86

dB (max)

Parameter

Conditions

Is

Supply Current

VIN

Input Voltage

Clipping Level (1.0% THD),
Select Out (Pins 7, 22)

THD

Total Harmonic Distortion

Left and Right channels;
Output Pins 13, 16
VIN = 0.3 V rms;
fiN = 100 HZ,l kHz,10 kHz
VIN = 2.0 Vrms;
fiN = 100 Hz, 1 kHz
VIN = 2.0 V rms;
fiN = 10 kHz
VIN = 0.5 V rms; Bass and Trable
Tone Controls Set at Maximum
VIN = 0.3 Vrms; Volume
Attenuator at - 20 dB, Bass and Treble
Tone Controls Set at Maximum

DC Shifts

ROUT
RIN

AC Output Impedance

Volume Step Size

Channel-to-Channel
Tracking Error

Mute Attenuation

VIN = 0.3 Vrms; between Any
Two Adjacent Control Settings
VIN = 0.3 Vrms;
All Mode and Input Positions

All Volume Attenuation Settings
from 0100010XXX101XXX (80 dB) to
01 0001 OXXXOOOOOO (0 dB) (Note 9)
All Volume Attenuation Settings
from 0100010XXX100ll0 (76 dB) to
01 0001 OXXXOOOOOO (0 dB)
from 010001 OXXXl 01 XXX (80 dB) to
010001 OXXXl 00111 (78 dB)
VIN

=

105

1.0Vrms
1-199

...
I

(")

If Military/Aerospace speeRleeI devices are required,

Vrms(min)

Electrical Characteristics The following specifications apply for V+ =
applied to INPUT 1, volume = 0 dB, bass
for TA = TJ = + 25'C. (Continued)
Symbol

=

0 dB, treble

Parameter

=

9V, fiN = 1 kHz, input signal (300 mY)
0 dB, and loudness is off unless oth!lrwise specified. All limits apply.

Conditions

Typical
(Note 6)

Limit
(Note 7)

Unit
(Limit)

Bass Gain Range

fiN

=

100 Hz, Pins 13, 16

±12

±10.0
±14.0

dB (min)
dB (max)

Bass Tracking Error

fiN

=

100 Hz, Pins 13, 16

±0.1

±1.5

dB (max)

Bass Step Size

fiN = 100 Hz, Pins 13, 16
(Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

Treble Gain Range

fiN

=

10 kHz, Pins 13,16

±12

±10.0
±14.0

dB (min)
dB (max)

Treble Tracking Error

fiN

=

10 kHz, Pins 13,16

±0.1

±1.5

dB (max)

Treble Step Size

fiN = 10 kHz, Pins 13,16
(Relative to Previous Level)

2.0

1.5
2.5

dB (min)
dB (max)

Frequency Response

VIN Applied to Input 1 and Input 2;
fiN = 20 Hz - 20 kHz
(Relative to Signal Amplitude at 1 kHz)

±0.1

±1.0

dB (max)

Volume Attenuator = 40 dB, Loudness
on (See Figure 5)
Gain at 100 Hz (Referenced
to Gain at 1 kHz)
Gain at 10kHz (Referenced
to Gain at 1 kHz)

11.5

13.5
9.5
8.5
4.5

dB (max)
dB (min)
dB (max)
dB (min)

Loudness

6.5

Signal-to-Noise Ratio

VIN = 1.0 Vrms, A Weighted,
Measured at 1 kHz, Rs = 4700.

95

90

dB (min)

Channel Balance

All Volume Settings

0.2

1.0

dB (max)

Channel Separation

Input Pins 4, 25: Output Pins 13, 16;
VIN = 1.0Vrms (Note8)

80

60

dB (min)

Input-Input Isolation

4700. to AC Ground on Unused Input

95

60

dB (min)

PSSR

Power Supply Rejection Ratio

V+ = 9 VDC; 200 mVrms , 100 Hz
Sinewave Applied to Pin 26

32

28

dB (min)

fCLK

Clock Frequency

5.0

1.0

MHz (max)

VIN(l)

Logic "1" Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins 2, 3

1.3
2.9

2.0
5.5

V (min)
V (min)

VIN(O)

Logic "0" Input Voltage

Pins 1, 27, 28 (1M Bus)
Pins 2, 3

0.4
1.2

0.8
3.5

V (max)
V (max)

VOUT(1)

Logic "1" Output Voltage

Pin 28 (1M Bus)

2.0

V (min)

VOUTlO)

Logic "0" Output Voltage

Pin 28 (1M Bus)

0.4

0.8

V (max)

Nota 1: Absolute Maximum Ratings indicate limns beyond which damage to the deivce may occur. Operating Ratings indicate condnions lor which the device is
lunctional, but do not guarantee specHic perlormance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only lor the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Nota 2: All voltages are specified with respect to ground.
Note 3: When the input voltage (YIN) at any pin exceeds the power supplyvoHages (YIN < V- orVIN> V+) the absolute value 01 the current at that pin should be
limited to 5 rnA or less. The 20 mA package input current limns the number 01 pins that can exceed the power supply voltages with 5 rnA current limn to lour.
Nota 4: The maximum power dissipation must be derated at elevated temperatures and is dicteted by TJMAX, BJA, and the ambient temperature TA. The maximum
allowable power dissipation is PD ~ (TJMAX - T!>J/B JA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMC1983CIN, TJMAX ~
+ 125'C, and the typical junction·to-arnbient thermal resistance, when board mounted, is 67"C/W.
Nota 5: Human body model; 100 pF discharged through a 1.5 kll resislor.
Note 6: Typicals are at TJ ~ + 25'C and represent the most likely pararnelric norm.
Nota 7: Umits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Nota 8: The Input·lnput Isolation is tested by driving one input and measuring the output when the undriven Input are selected.
Note 9: The Volume Step Size is defined as the change in attenuation between any two adjacent volume attenuation settings. The nominal Volume Step Size is
2dB.

1-200

Typical Performance Characteristics
Supply Current
vs Supply Voltage
30

'A =25°C

'C

i

~~~m. Attenustor;,

o oJ
10

12

O.B

2

0.6

10

I-0.4

:c

0.2

~
~

12

14

o

3
100

o

r-

20

AC LOAD IMPEDANCE (kll)

-70r----r,~~~--,_---,

is
~

O.OB

.1

g

,...

-

40

-80

60

~g -100
-105 Right Output (lift channel driven)
_ t 10
left Output - - - (RIght chlnnll driven

BO

10

100

lk

10k

lOOk

FREQUENCY (Hz)

Mute Gain
vs Frequency
OdBr-----~mm_rrrrnm_rnmm

'1+= 9V

-30dB

Input Pin.: ",25
output Pins: 13.16
Tone Flat

'iD' -60dS
3

0.5
VIN

is
-VOUT '" 30 mVrml

~

-75

-B5~~~~~~~~---4

TA =25°C

0.07

Input Pins: 4, 25
Output Pins: 13. 16

~

.3

THO vs Frequency

1.0

i

'iD'

VOLUME ATTENUATION (dB)

THO vs VIN
(VOUT Constant)

100

-90 ~--''''''----i---,f-''''---4

"

TA = 25°C
'1+=9'1

10

Channel Separation
vs Frequency

:;!

~

"
1

\
t\

10

\

AC LOAD IMPEDANCE (kll)

Input Pins: Grounded
Output Pins: 13. 16
Tone Flat

\
\
1

16

v+ =9V

~~~ P~~t:~u6~t~o!I=IJjB

Out
Vol
Tone Flat

~

0.01

Tio = 25°C

1111

VOUT = lVrms

r-

~

=

I--

SUPPLY VOLTAGE (V)

II II

v+ =9V

r-

0.03
0.02

CCIR Output NOise
vs Volume Setting

TA =25°C

g

=9V
VOU T= lYrrna

Output Pins: 13.16
Volu me Attenuation 0 dB
Tone Flat

0.00

SUPPLY VOLTAGE (V)

THOvs
Load Impedance

v+

rr-

is

~

/

4

'is"

is

TA= 25°C

r-

0.04

~

/

o

is

i

L

Tone Flat

,/

i

g

/

1\=
THD= 1"

V

10

0.05

=25°C

Output Pins: 13, 16

/V

15

THOvs
Load Impedance

v+ =9V

/

20

i

TA

V

'1+ = 9'1

25

.s

Output Voltage
vs Supply Voltage

e~

VOUT-100mVI'1III

J.

-:J

~

0.0 1

Vour,"300IllV"..

0.0
0.0

0.5

1.0

=1Vrms

1.5

0.00

2.0

2.5

10

-

/

!!;

II

~ -90dB

I

~
~N=0.3Vm
100

lk

10k

-120dB
-135dB

lOOk

10

100

FREQUENCY (Hz)

INPUT VOLTAGE (V,m.)

Tone Control Response
with Equal Bass and
Treble Control Settings

lk

10k

lOOk

FREQUENCY (Hz)

Loudness Response
vs Frequency

Select Input Impedance
vs Frequency
lMr---~----'---~----~

BdB

I

OdB

i!!

'iD'

3

z

~

=25°C
v'=9vl

TA

s:

16dB

MAX CUT

lOOk

Inputs: pins 7.22

1-::-""~X---+---4-----i

10k

-BdB

.........

-16dB

lkL-__-L____~__~"=AX~~==~T
10

100

lk

10k

FREQUENCY (Hz)

10

lOOk
FREQUENCY (Hz)

100

lk

10k

lOOk

FREQUENCY (Hz)

TL/H/11279-9

1-201

II

Connection Diagram
'-./

CLOCK- 1
DIGITAL INPUT 1- 2

28 r-DATA
27 t-ID

26 t-y+

DIGITAL INPUT 2- 3
LEn INPUT 1 -

4

LEFT INPUT 2 -

5

24 t-RIGHT INPUT 2

LEn INPUT 3- 6

23 t-RIGHT INPUT 3

LEn SELECT OUTPUT -

7

25 t- RIGHT INPUT 1

25 24 23 22 21 20 19

LMC 1983 22 t- RIGHT SELECT OUTPUT

LEn SELECT INPUT- 8

21 r-RIGHT SELECT INPUT

LEn TONE INPUT- 9

20 r-RIGHT TONE INPUT

LEFT TONE OUTPUT -

10

19 t- RIGHT TONE OUTPUT

LEn OP AWP OUTPUT -

11

LEn LOUDNESS -

12

LEn MAIN OUTPUT- 13

V+ -

26

18 - RIGHT OP AWP OUTPUT

ID -

27

17 - RIGHT LOUDNESS

DATA -

16 - RIGHT WAIN OUTPUT

28

LMC1983

CLOCK -

1

18 r-RIGHT OP AIIP OUTPUT

DIGITAL INPUT 1 -

2

15 - GROUND
14 - BYPASS

17 t- RIGHT LOUDNESS

DIGITAL INPUT 2 -

3

13 - LEFT WAIN OUTPUT

18 t-RIGHT MAIN OUTPUT

BYPASS- 14

15 t-GROUND

TL/H/I1279-2

Top View
Order Number LMC1983CIN
See NS Package Number N28B
TL/H/11279-10

Top View
Order Number LMC1983CIV
See NS Package Number V28A

Pin Description
ClK(I)

DIGITAL INPUT
1&2(2,3)

The INTERMETAl (1M) Bus clock is applied to the CLOCK pin. This input accepts a TIL or CMOS level signal. The
input is used to clock the DATA signal. A
data bit must be valid on the rising clock
edge.
Intemally tied high to V+ through a
30 kG pull-up resistor, these inputs allow
a peripheral device to place any singlebit, active low digital information onto the
1M Bus. It is then sent out to the controlling device through the DATA pin. Examples of such information could include indication of the presence of a Second Audio Program (SAP) or an FM stereo carrier.

INPUTS I, 2 & 3
(4, 25; 5, 24;
6,23)

These are the LMC1983's three stereo
input pairs.

SELECT OUT
(7,22)

The selected INPUT signal is available
at this output. This feature allows external signal processors such as noise reduction or graphic equalizers to be used.
This output can typically sink 1 mA.
These pins should be capacitively coupled to pins 8 and 21, respectively, if no
external processor is used.

SELECT IN
(8,21)

These are the inputs that an external signal processor uses to return a signal to
the LMC1983. These pins should be capacitively coupled to pins 7 and 22, respectively, if no external processor is
used.

1-202

TONE IN
(9,20)

These are the inputs to the tone control
amplifier. See the Application Information section titled "Tone Control Response".

TONE OUT
(10, 19)

Tone control amplifier output. See the
Application Information section titled
"Tone Control Response".

OPAMP
OUT (11,18)

These outputs are used with external
tone control capacitors. Internally, this
output is applied to the volume attenuators.

lOUDNESS
(12, 17)

The output signal on these pins is a vo"-

MAIN
OUTPUT
(13,16)

The output signal from these pins drives
a stereo power amplifier. The output can
typically sink 1 mAo

BYPASS (14)

A 10 ",F capacitor is connected between
this pin and ground to provide an AC
ground for the internal half-supply voltage reference.

age taken from the volume attenuator's
-40 dB tap pOint. An external R-C network is connected to these pins.

GROUND (15)

This pin is connected to analog ground.

V+ (26)

This is the power supply connection. The
lMC1983 is operational with supply vo"ages from 6V to 12V. This pin should be
bypassed to ground through a 1.0 ",F capacitor.

10 (27)

This is the IDENTITY digital input that,
when low, signals the lMC1983 to receive, from a contrOlling device, a device
address (40H-47H), present on the
DATA line.

op amps, and poly-silicon resistors make it possible to
achieve an order of magnitude quality improvement over
other bipolar circuits that use analog multipliers to accomplish gain adjustment. Internal circuits set the volume to
minimum, tone controls to flat, the mute to on, and all other
functions off when power is first applied. Individual left and
right volume controls are software programmed to achieve
the stereo balance function. Figure 1 shows the connection
diagram of a typical lMC1983 application.

Pin Description (Continued)
DATA (28) This is the serial data input for communications
sent by a controller. The controller must have
open drain outputs used with external pull-up
resistors. The data rate has a maximum frequency of 1 MHz. The lMC1983 requires 16
bits of data to control or change a function: the
first 8 bits select the lMC1983 and one of eight
functions. The final eight bits set the function to
a desired value. The data must be valid on the
rising edge of the CLOCK input signal.

The lMC1983 has internal decoding logiC that allows a
microprocessor (,...P) or microcontroller (,..C) to communicate directly to the audio control circuitry through an
INTERMETAl (1M) Bus interface. This three-wire interface
consists of a bi-directional DATA line, a Clock (ClK) input
line, and an Identity (10) line. Address and function selection
data (8 bits) are serially shifted from the controller to the
lMC1983. This is followed by 8 bits of function value data.
Data present in the internal shift register is latched and the
instruction is executed.

General Information
The lMC1983 is a CMOS/bipolar building block intended
for high fidelity audio signal processing. It is designed for
line level inputs signals (300 mV - 2V) and has a maximum
gain of -0.5 dB. While the lMC1983 is manufactured with
CMOS processing, NPN transistors are used to build low
noise op amps. The combination of CMOS swilches, bipolar
DIGITAL DIGITAL
INPUT 2 INPUT 1

elK

DATA

ID

~4

lEFT INPUT 1 .....-----,

•

LEFT INPUT 2 ~
.....-----,
lEFT INPUT 3

~

0.47 ).IF

LMC1983

0.0082 ).IF
10

19

11
240 pF

240 pF

12

' ' '1
1.5 kll

+

13

16

14

15

::::c

f""
1.5kll

-

10 ).IF

LOUT

ROUT
FIGURE 1. Typical Application

1-203

TL/H/11279-3

~~--------------------------------------------------------~

I....

(.)

:!i

~pplication

Information
couple the SELECT OUT signals directly to pins 8 and 21,
respectively.

INPUT SELECTOR
The LMC1983's input selector and mode control are shown
in Ftgure 2. The input selector selects one of three stereo
signal sources or a mute function with typical attenuation of
100 dB. The selected signals are then sent to a mode control matrix. As shown in Table I, the matrix provides normal
stereo or can direct any given channel to both LEFT or
RIGHT SELECT OUTPUTs. The third matrix mode is normal
stereo. The control matrix output is buffered and appears on
each channel's respective SELECT OUT pin (7, 22). Switching noise is kept to a minimum when mute is selected by
using a 50 kO bias resistor.
Noise performance is optimized through the use of emitter
followers in the mode control matrix's output. Internal 50 kO
resistors are connected to each input selector pin to provide
the proper bias point for the emitter follower buffers. Each
internal 50 kO bias resistor is connected to a common halfsupply (V+ 12) source. This produces a voltage at pins 7
and 22 (SELECT OUT) that is 1.4V below V+/2 (typically
3.1V with V+ = 9V). Since a DC voltage is present at the
input pins (4, 5, 6, 23, 24, and 25), input signals should be
AC coupled through a 1 p.F capacitor.
The output Signal at pins 7 and 22 can be used to drive
exteral audio processing circuits such as noise reduction
(LM1894-DNR or Dolby) or graphic equalizers (LMC835). It
is important that if any noise reduction is used it be placed
ahead of any tone controls or equalizers in the external circuit path to preserve the frequency spectrum of the selected input signal. Otherwise, any frequency equalization could
prevent the proper operation of the noise reduction circuit. If
no external processor is used, a capaCitor should be used to

MINIMUM LOAD IMPEDANCE
The LMC1983 employs emitter-followers to buffer the selected stereo channels. The buffered signals are available
at pins 7 and 22 (SELECT OUT). The SELECT OUT buffers
operate with a typical bias current of 1 mAo
The Electrical SpeCifications table lists a maximum input signal of 2.0 Vrms (2.8 Vpeakl for 1% THO at the SELECT OUT
pins. This distortion level is achieved when the minimum AC
load impedance seen by the SELECT OUT pins is 2.5 kO
(2.5VII mAl. Using lower load impedances resul1s In clipping at lower output levels. If the load impedance is DC-coupled, an increased quiescent current can flow. Latch-up may
occur if the total emitter current exceeds 5 mAo Thus, maximum output voltage can be increased and much lower distortion levels can be achieved using load impedances of at
least 25 kO.
INPUT IMPEDANCE
The input impedance of pins 4, 5, 6, 23, 24 and 25 is defined
by internal bias resistors and is typically 50 kO.
The SELECT IN pins have an input impedance that varies
with the BASS and TREBLE control settings. The input impedance is 100 kO at DC and 19 kO at 1 kHz when the
controls are set at 0 dB. Minimum input impedance of
30.4 kO at DC and 16 kO at 1 kHz occurs when maximum
boost is selected. At 10kHz the minimum input impedance,
with the tone controls flat, is 6.8 kO and, with the tone controls at maximum boost, is 2.5 kO.

SOkAx4

v·

SI : Input Select
S2: Wode Select

RIGHT SELECT OUT

SOkAx4

v·
LEFT INPUT 1 ~~::J;:::t::t:=~~
LEFT INPun
LEFT INPUT 3
+.-:-Wu'":t-.0

c:
O----....

..,..........-O.'--~

LEFT SELECT OUT

TLlH/II279-4

FIGURE 2. Input and Mode Select Circuitry

1-204

Iiio

...

Application Information (Continued)

Iw

TABLE I. 1M Bus Programming Codes for LMC1983
Address
(A7-AO)

Function

Data

Function
Selected

01000000

Input Select + Mute

XXXXXXOO
XXXXXX01
XXXXXX10
XXXXXX11

INPUT1
INPUT2
INPUT3
MUTE

01000001

Loudness

XXXXXXXO
XXXXXXX1

Loudness OFF
Loudness ON

01000010

Bass

XXXXOOOO
XXXX0011
XXXX0110
XXXX1001
XXXX11XX

-12dB
-6dB

01000011

Treble

FLAT

+6dB
+12dB

XXXXOOOO
XXXX0011
XXXX0110
XXXX1001
XXXX11XX

-12dB
-6dB
+6dB
+12dB

FLAT

01000100

Left Volume

XXOOOOOO
XX010100
XX1 01 XXX
XX11XXXX

OdB
-40 dB
-SO dB
-SOdB

01000101

Right Volume

XXOOOOOO
XX010100
XX1 01 XXX
XX11XXXX

OdB
-40 dB
-SOdB
-SO dB

01000110

Mode Select

XXXXX100
XXXXX101
XXXXX11X

Left Mono
Stereo
Right Mono

01000111

Read Digital Input 1
or
Digital Input 2
on 1M Bus

XXXXXX01DO

DO = Digital Input 1
01 = Digital Input 2

1·205

C')

I....
o

:::E
....I

Application Information

(Continued)

EXTERNAL SIGNAL PROCESSING

response is achieved when C2 = C3. However, with
C2 = 2(C3) and the tone controls set to "flat", the frequency response will be flat at 20 Hz and 20 kHz, and + 6 dB at
1 kHz.

The SELECT OUT pins (7 and 22) enable greater system
design flexibility by providing a means to implement an external processing loop. This loop can be used for noise reduction circuits such as DNR (LM1894) or multi-band graphic equalizers (LMC835). If both are used, it is important to
ensure that the noise reduction circuitry precede the equalization circuits. Failure to do so results in improper operation
of the noise reduction circuits. The system shown in Figure
3 utilizes the external loop to include DNR and a multi-band
equalizer.

The frequency where a tone control begins to deviate from
a flat response is referred to as the turn-over frequency.
With C = C2 = C3, the LMC1983's treble turn-over frequency is nominally

fn =

The bass turn-over frequency is nominally

TONE CONTROL RESPONSE

1
fBT = 21TC(30.4 kG)

Bass and treble tone controls are included in the LMC1983.
The tone controls use just two external capacitors for each
stereo channel. Each has a corner frequency determined by
the value of C2 and C3 (see Rgure 4 ) and internal resistors
in the feedback loop of the internal tone amplifier. The maximum-boost or cut is determined by the data sent to the
LMC1983 (see Table I).

when maximum boost is chosen. The inflection points (the
frequencies where the boost or cut is within 3 dB of the final
value) are for treble and bass
1

fTl

The typical tone control response shown in Typical Performance Curves were generated with C2 = C3 = 0.0082 p.F
and show the response for each step. When modifying the
tone control response it is important to note that the ratio of
C3 and C2 sets the mid-frequency gain. Symmetrical tone

INPUT 1
INPUT 2
INPUT3

1
21TC(14 kG)

f

= 21TC(1.9 kG)

_
1
BI - 21TC(169.6 kG)

INPUT
AND
MODE
SELECT
I
I
I

:

:

I

~---------.---------.----------.

I

DIGITAL
INPUT 1
DIGITAL
INPUT 2

LOGIC
AND
CONTROL

TL/H/11279-5

FIGURE 3. System Block Diagram Utilizing the External Processing Loop (One Channel Shown)

1-206

r-----------------------------------------------------------------------------,
Application Information
8(21)
SE\.ECTIN

9(20)

TONE IN

r
i:

....

(")

(Continued)
10(19)

11(18)

TONEOUT

OPAMPOUT

of boost is dependent on the volume attenuator's setting.
The loudness characteristic, with the volume attenuator set
at 40 dB, has a transfer function of
~ ~

VI

(sC5R2 + 1j[sC4(Rl + 156k) + 1]
(s2)C4C5R2(163k) + s[C4(156k) + C5(4.9A2 + 156k)l

CD
CD

Co)

+1

The external components R1 and C4 can be eliminated and
pin 11 (18) left open if bass boost is the only desired loudness characteristic.

V+/2
TLlH/11279-6

FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 = C3 = 0.0082, 2 dB steps are
achieved at 100 Hz and 10kHz. Changing C2 and C3 to
0.01 /LF shifts the 2 dB per step frequency to 72 Hz and
8.3 kHz. If the tone control capacitors' size is decreased
these frequencies will increase. With C2 = C3 = 0.0068 /LF
the 2 dB steps take place at 130 Hz and 11.2 kHz.

TLlH/11279-7

FIGURE 5. Loudness Control Circuit
SERIAL DATA COMMUNICATION
The lMC1983 uses the INTERMETAl serial bus (1M Bus)
standard. Serial cata information is sent to the lMC1983
over a three wire 1M Bus consisting of Clock (ClK), Data
(DATA), and Identity (ID). The DATA line is bidirectional and
the ClK and ID lines are unidirectional from the microprocessor or micontroller to the lMC1983. The lMC1983's bidirectional capability is accomplished by using an open drain
output on the DATA line and an external 1 k.!l pull-up resistor.
The lMC1983 responds to address values from 01000000
(40H) through 01000111 (47H). The addresses select one of
the eight available functions (see Table I). The 1M Bus' lines
have a logic high standby state when using TTL logic levels.
As shown in Figure 6, data transmission is initiated by low
levels on ClK and ID. Next, eight address bits are sent. This
address information includes the code to select one of the
lMC1983's desired functions. Each address bit is clocked in
on the rising edge of ClK. The ID line is taken high after the
eight bits of address data are received by the lMC1983.

LOUDNESS
The human ear has less sensitivity to high and low frequencies relative to its sensitivity to mid-range frequencies between 2 kHz and 6 kHz for any given acoustic level. The low
and high frequency sensitivity decreases faster than the
sensitivity to the mid-range frequencies as the acoustic level
drops. The lMC1983's loudness function can be used to
help compensate for the decreased sensitivity by boosting
the gain at low and high frequencies as the volume control
attenuation increases (see the curve labeled "Gain vs Frequency with Loudness Active").
The lMC1983's loudness function uses external components R1, R2, C4 and C5, as shown in Figure 5, to select the
frequencies where bass and treble boost begin. The amount

lo--,~--------------------------~I

-11250

11-250

ns

ns

elK

DATA

I AO I

Al

I

A2

I A3 I

A4

I A5 I

A61 A7

I

DO

I 01 I 02 I

03

04

I 05 I 06 I

07

I-TL/H/11279-8

FIGURE 6. LMC1983's INTERMETAL Serial Bus Timing

1-207

•

Application Information (Continued)
The controlling system continues toggling the CLK line eight
more times. Data that determines the selected function's
operating point is written into, or single bit information on
DIGITAL INPUT 1 or DIGITAL INPUT 2 is read from, the
LMC1983. Finally, the end of transmission is signaled by
pulsing the 10 line low for a minimum of 3 /los. The transmitted function data is latched and the function changes to its
new setting.
Table I also details the serial data structure, range, and bit
assignments that sets each function's operating point. The
volume and tone controls' function control data binarily increments from zero to maximum as the function's operating
pOint changes from 80 dB attenuation to 0 dB attenuation
(volume) or -12 dB to +12 dB (tone controls). Note that
not all data bits are needed by each function. The extra bits
shown as "X"s ("don't cares") are position holders and
have no affect on a respective control. They are necessary
to properly position the data in the LMC1983's internal data
shift register. Unexpected results may take place if these
bits are not sent.
The LMC1983's internal data shift register can handle either
a 16-bit word or two 8-bit serial data transmissions. It is the
final 8 bits of data received before the 10 line goes high that
are used as the LMC1983 selection and function addresses.
The final eight bits after the 10 line returns high are used to

change a function's operating point. CLK must be stopped
when the final 8 data bits are received. The data stored in
the internal data latch remains unchanged until the 10 is
pulsed, signifying the end of data transmission. When 10 is
pulsed, the new data in the data shift register is latched into
the data latch and the selected function takes on a new
operating point.
A complete description and more information concerning
the 1M Bus is given in the appendix of In's CCU2000 datasheet.
DIGITAL 1/0
The LMC1983's two Digital Input pins, 2 and 3, provide single-bit communication between a peripheral device and the
controller over the 1M Bus. Each pin has an internal 30 kO
pull-up resistor. Therefore, these pins should be connected
to open collector/drain outputs. The type of information that
could be received on these lines and retrieved by a controller include FM stereo pilot indication, power on/off, Secondary Audio Program (SAP), etc.
According to Table I, the logiC state of DIGITAL INPUT 1
and DIGITAL INPUT 2 is latched and can be retrieved over
the 1M Bus using the read command (47H). The single-bit
information sent on the 1M Bus is active low Since these
lines are internally pulled high.

1-208

~National

~ Semiconductor

LMC1992 Digitally-Controlled Stereo Tone and Volume
Circuit with Four-Channel Input-Selector
General Description

Features

The LMC1992 is a monolithic integrated circuit that provides
four stereo inputs, bass and treble tone controls, and volume, balance, and front-rear fader controls. These functions
are digitally controlled through a three-wire communication
interface. All of the LMC1992s functions are achieved with
only three external capacitors per channel. It is designed for
line level input signals (300 mV - 2V) and has a maximum
gain of 0 dB.
The internal design is optimized for external capacitors having values of 0.1 ,...F or less. This allows the use of chip
capacitors for coupling and tone control functions.
Low noise and distortion result from using analog switches
and thin-film silicon-chromium resistor networks in the signal path.
Volume and fader are at minimum and tone controls are flat
when supply voltage is first applied.

•
•
•
•
•
•
•
•
•

Additional tone control can be achieved using the LMC835
stereo 7 -band graphic equalizer connected to the
LMC1992's select-out/select-in external processor loop.

•
•
•
•

Low noise and distortion
Four stereo inputs
40 volume levels including mute
20 fader levels
All attenuators have a 2 dB of attenuation per step
Front/back fade control
External processor loop
Only three external components per channel
Serial programmable: standard MICROWIRETM
interface
Single supply operation: 6V to 12V supply voltage
Protection address (similar to DS8906)
DC-coupled inputs
Single supply operation

Applications
• Automotive audio systems
• Sound reinforcement systems
• Home entertainment-stereo television and music reproduction systems
• Electronic music (MIDI)

Block and Connection Diagrams

II
DATA

28

v+

a.OCK

27

BYPASS

2&

RIGHT INPUT1

EiWiLE
LEFT INPUTI

4

LEFT INPUT2

LEFT INPUT3
LEFT IlPUT4
LEFT SELECT OUT
LEFT sa.ECT IN

REAR
OUTPUT
13 (17)

7
8
9

LMC1992

25

RIGHT INfUT2

24

RIGHT INPUT 3

23

RIGHT INPUT4
R1GHT sa.ECT OUT

22
21

RIGHT sa.ECT IN

20

RIGHT TONE II

LEFT TONE IN

10

19

LEFT TONE OUT

11

18

RIGHT TONE OUT
RIGHT OP AMP OUT

LEFT OP AUP OUT

12

17

RIGHT REAR OUT

LEFT REAR OUT

13

16

LEFT FRONT OUT

14

15

RIGHT FfIONT OUT
GROUND

TLlH/l0789-2

Order Number LMC1992CCN
See NS Package Number N288
TL/H/l0789-1

Left channel shown. Pin numbers In parentheses are for the right channel.

1-209

N

en
en

....
o

:::&

....I

Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Storage Temperature ..

Supply Voltage (V+ - GND)

ESD Susceptibility (Note 5)
Pins9,10, 11,19,20,21

Voltage at Any Pin

15V
GND - 0.2VtoV+ + 0.2V

Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
Junction Temperature

'-65°Cto + 150"C

Lead Temperature
N Package, Soldering, 10 sec.

5mA

+26O"C
2000V
850V

Operating Ratings (Notes 1 and 2)

20mA

TMIN ~ TA ~ TMAX
O"C ~ TA ~ 70"C

Temperature Range
LMC1992CCN

500mW
125°C

SupplyVoltageRange(V+ - V-)

6Vto 12V

Electrical Characteristics The following specifications apply for V+ = 8V, fiN = 1 kHz, input signal applied to
channell, volume = 0 dB, bass = 0 dB, treble = 0 dB, and faders = 0 dB unless otherwise specified. All limits T A = T J =
25°C.
Symbol

Parameter

Conditions

Typical
(Note 6)

Limit
(Note 7)

Units
(Limit)

27.0

mA(max)

Is

Supply Current

VIN

Input Voltage

Clipping Level (1.0% THO),
Select Out (Pins 8, 22)

2.3

2.0

Vrms(min)

VOUT

Output Voltage

Clipping Level (1.0% THO),
Outputs (Pins 13, 14, 16, 17)

1.2

0.65

Vrms(min)

THO

Total Harmonic Distortion

All Four Channels
Volume Attenuator at 0 dB, Input Level 0.3 Vrms
Volume Attenuator at - 20 dB, Input Level 0.6 Vrms

0.15
0.03

0.3
0.1

% (max)
% (max)

EnOUT

Output Noise

All Four Channels CCIRt ARM Filter, Rs = 00

6.5

30.0

",Vrms (max)

EnOUT

Output Noise

All Four Channels CCIRtARM Filter, Rs = 00
Volume Attenuator = - 80 dB

5.0

20.0

,..Vrms(max)

ROUT

DC Output Impedance

Pins 8, 22
Pins 13,14,16,17

100
80

150
120

o (max)
o (max)

RIN

DC Input Impedance

Pins 4, 5, 6, 7, 23, 24, 25,26

Volume Attenuator Range

Pins 16, 17; Volume Attenuation at
0101110100X (0 dB); (Absolute Gain)
01011000000 (80 dB); (Relative to Attenuation at
the 0 dB setting)

Volume Step Size

All Volume Attenuation Settings from 01011001010
(60 dB) to 01011101 OOX (0 dB) (Note 9)

Channel-to-Channel Volume
Tracking Error

Fader Attenuation from 1XXXOOOOOO
(40 dB) to lXXX1010X (0 dB)

Fader Attenuation Range

Pins 16, 17; Fader Attenuation at
011 XXXl 01 OX (0 dB); (Absolute Gain)
011XXXOOOOO (40 dB); (Relative to Attenuation at
the 0 dB setting)

Fader Step Size

All Fader Attenuation Settings from 011 XXXOOOOO
(40 dB) to 011XXX10l0X (0 dB) (Note 10)

1-210

MO

2
-1.0

-1.5

dB (max)

80.0

75.0

dB (min)

2.0

0.7
4.3

dB (min)
dB (max)

±0.5

±1.0

dB (max)

-1.0

-1.5

dB (max)

40

38.0

dB (min)

2.0

1.0
4.5

dB (min)
dB (max)

Electrical Characteristics The following specifications apply for V+
channel 1, volume
25'C. (Continued)
Symbol

=

0 dB, bass

=

0 dB, treble

=

0 dB, and faders

=

= 8V, fiN = 1 kHz, input signal applied to
0 dB unless otherwise specified. All limits T A = T J =
Typical

Limit

Units

(Note 6)

(Note 7)

(Limit)

100 Hz, Pins 14, 16

±12

±10.0

dB (min)

100 Hz, Pins 14,16

±0.1

±1.0

dB (max)

100 Hz, Pins 14, 16

2.0

1.0

dB (min)

3.0

dB (max)

Parameter

Conditions

Bass Gain Range

fiN

Bass Tracking Error

fiN

Bass Step Size

fiN

=
=
=

(Relative to Previous Level)
Treble Gain Range

fiN

Treble Tracking Error

fiN

Treble Step Size

fiN

=
=
=

10 kHz, Pins 14, 16

±12

±10.0

dB (min)

10 kHz, Pins 14, 16

±0.1

±1.0

dB (max)

10 kHz, Pins 14, 16

2.0

1.0

dB (min)

3.0

dB (max)

20

kHz (min)

(Relative to Previous Level)
Frequency Response

-3dB

450

-0.3 dB (Relative to Signal Amplitude at 1 kHz)

PSRR

Channel Separation

VIN

Input-Input Isolation

VIN

Power Supply Rejection Ratio

V+

=
=
=

kHz

1.0Vrms

97

70

dB (min)

1.0 V rms (Note 8)

90

70

dB (min)

40

31

dB (min)

8 VDC; 100 mVp_p,

100 Hz Sinewave Applied to Pin 28
fCLK

Clock Frequency

1.0

0.5

MHz (max)

VIN(l)

Logic "1" Inpm Voltage

1.3

2.0

V (min)

VIN(O)

Logic "0" Input Voltage

0.4

0.8

V (max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Nota 2: All voltages are specified with respect to ground.
Note 3: When the input vonage (YIN> at any pin exceeds the power supply voltages (YIN < V- or VIN > V+) the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 rnA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current IimR to four.
Nota 4: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX. JA. and the ambient temperature TA. The maximum
allowable power dissipation is PO ~ (TJMAX - TA)/6JA or the number given in the Absolute Maximum Ratings. whichever is lower. For the LMC1992CCN. TJMAX
~ 125'C. and the typical junction-ta-ambient thermal resistance. when board mounted. is 67'C/W.
Note 5: Human body model; 100 pF discharged through a 1.5 kO resistor.
Note 6: Typicals are at TJ

~

25'C and represent the most likely parametric norm.

Note 7: Limits are guaranteed to National's AOQL (Average Outgoing QualRy Level).
Nota 8: The Input·lnput Isolation is tested by driving one input and measuring the 'front outputs when the undriven inputs are selected.
Note 9: The Volume Step Size is defined as the change in attenuation between any two adjacent volume attenuation settings. The nominal Volume Step Size is
2dB.
Note 10: The Fader Step Size is defined as the change in attenuation between any two adiacent fader attenuation settings. The nominal Volume Step Size is 2 dB.

1-211

III

~

8:
..-

o

.---------------------------------------------------------------------------------,
Typical Performance Characteristics

~

Quiescent Current vs

Maximum Output Swing va

24 Supply Voltage

!

~

vt'=8V
VIN =300mV

~

10

V

TA=25"C
vt'=8V

8
6

~

SOl

4
2

o
o

2

4

6

8

10

12

o
o

14

4

6

8

10

SUPPLY VOLTAGE

TLlH/l0789-S

Total Hannonlc Distortion

z

i,.

1.

J.I.llll Jl

.....-1- VIN =300mV
Inputs: pins 4.26
0.8
Outputs: pin. 13. 14. 16. 17

f-+-

!i!0

0.6

I

D.4

~

1111111

z

0.18

~

0.16

~
z

0

I.....

\

D.2

i!

M

~

,

o
100

10

~

~

10

100

--VO=30mV
--Vo=IOOmV
----Vo =300mV

L-

I

10000

,,
,,

100000

FREQUENCY (Hz)

TLlH/l0789-9

o

~
1-

o

...

I'"

~

t-..
I'"

W 20 30

~ 50 50 70 80
VOLUME SET11NG (-dB)

TL/H/l0789-8

~

TA = 25"1:-.lJJJlJl
v+=8
VIN =300 mY~

-10dB

~~1n.4.26

!-20dB
iii! -3OdB

Outputo: pin. 13 r,', ~

!i! -«IdS
:!i-SOdB

,

-70dB
-80dB

200 400 600 800 1000 1200
INPUT VOLTAGE (mY)
TLlH/l0789-10

1-212

Attenuation vs Frequency
OdS

Ii -BOdB

,~

~
1000

,

TA=25"1:
vt'=8V
Inputs: pins 4. 26
Outputs: pins 14. 16 "

-1110

~

TL/H/l0789-7

R-

~

o

Total Hannonlc Distortion
vs Input Voltage
0.8

TA=25~~~JU I

'f

Rs=QllJ.
Ton. Control flat
1 J-- I-- Inputs: pins 4.26 I-- j Outpula:plns 13.14.16.17

TLlH/10789-6

v+=8.av
VIN =300 mV
Inpula: pin. 4. 26
Qlltputo: pin. 14 16

r..

SELECT OUT LOAD (k.G.)

Channel Separation
vs Frequency
-70

6

TA =25"C

1

OUTPUT LOAD RESISTANCE (k.o.)

100000

I-- r- vt' =8Y I

0.12

100

10

10000

CCIR Output Noise Voltage
vs Volume Setting

\

0.14

0.10
I

1000

TLlH/l0789-6

vt'=8V
VIN =300mV
Inpuls: pin. 4. 26
Outputs: pin. 8,22

~

0.0

100

FREQUENCY (Hz)

TA=25"C1.~~

g

!..!

\

10

14

Total Hannonlc Distortion
va Select Out AC Load
D.2O

~:~~~

12

TL/H/l0789-4

1.2 vs Output AC Loed
1.0

IIIIIIIII ....~

o L-J...JWJjj(J'--'-J.

M

SUPPLY VOLTAGE

g

--VOL=OdB
- - VOL =-80dB
200
TA=25"C
vt'=8V
Inputs: pins 4.26
Outpula:plnl13.14.16.17
Rs=OIl
100
CCLR AR;uy-ioWti.~hUl'I.:n::tg-ttH1IIH

I

THO = '"
fiN = I kHz

Output Noise Voltage
vs Frequency

2SO

~~:~In~ ,13.'11.116.I,il"

22
20
18
16

I:
~

2.S Supply Voltage

j,..o'

100

lk

10k

lOOk

FREQUENCY (Hz)

TLlH/l0789-11

Typical Performance Characteristics
Tone Control Response
with Equal Bass and
Treble Control Settings

!

~

Ii:o
....

(Continued)

:8
N

Tone Control Response
with Reciprocal Bass and
Treble Control Settings

Treble Tone Control
Response

20

2O,....,.,..".rmr-"TTTTTTT......."TTITTm""...,..,

20

16
12

16 I-t±ltlltll-++t
12H"I"HoII!!I.ml:'.

16
12
8

8H~~,*,

•

•

0
--4
-t
-12
-16
-20

1-f'ffl1~!1'1

Iii'

o 1-+++-H1lfI--E

~

-.H:r±l:~:>r.:

ij

z

-t H+i'I!I!IK:*l-12 H:::IoIo!oi1IlI''-.C" =c" =o.OOIIl~pfrll-+-t
-16r;=fR~-:'

-20 L...l..I.J..1llJ,.:;;==:"":':;:":"":':":"::"':;,.,J
20

100

lk

100

20k

FREQUENCY (Hz)

0
--4
-t
-12
-16
-20

~

TA =25"C
v+=8V
VIN = 300 mV

~

I-

I'MHI--

I I IfIlIII-.:

Cz =~=O.0D82pf

111111111
(s.. Figure 1)
Outputs:plno13,I.,16,17 111111

lk

100

FREQUENCY (Hz)

TL/H/l0789-12

20

~

I-

4

lk

FREQUENCY (Hz)

TUH/l0789-13

B888 Tone Control
Response

TUH/l0789-14

Select In Impedance
YS Frequency
1.0M

16~~~-rH*~++~~,

300k

12r;~~~H*~++~~,
8~~~~#m~~~-H

s:

• 1-f'ffl111!!!-oi!t-O

o H+I+IIH!I-£

lOOk

is

--4 H333lIllll-'!>Ili
-tH-M'!'iIIII'WH++H!I--!-+

!:!..

..,,=..,,=0.......

-12 H:IoI+IIlII"+ttti
'1""1
-16 r;=fR1IHI-+H++-'l-20 .........J..LI.wa.;==;;;;;;...;.;;.:..;..:.:.;c;.:.;.;.J
20
100
lk

--- -.

TA=25"C
v+=8V
Inputs: pins 9,21

--~-- ---

""\

30k

10k Ba.. and Trebl.
Salting.:
-----12dB
3.0k -OdB
._.-+1 2 dB

-

\

1

1.0k
10

100

FREQUENCY (Hz)

l.ok

--

10k

lOOk

Frequoncy (Hz)
TUH/l0789-15

TUH/l0789-18

Connection Diagram
DATA

•1

28

v+

CLOCK

2

27

BYPASS

ENABLE

3

26

RIGHT INPUT 1

LEFT INPUT 1

4

25

RIGHT INPUT2

24

RIGHT INPUT 3

LEFT INPUT2

I

LEFT INPUT3

RIGHT INPUT"

LEFT INPUT4

RIGHT SELECT OUT

LMC1992

LEFT SELECT OUT

RIGHT SELECT IN

LEFT SELECT IN

RIGHT TONE IN

LEFT TONE IN

RIGHT TONE OUT

LEFT TONE OUT

11

18

RIGHT OP AMP OUT

LEFT OPAMP OUT

12

17

RIGHT REAR OUT

LEFT REAR OUT

13

16

RIGHT FRONT OUT

LEFT FRONT OUT

14

15

GROUND
TUH/l0789-17

1-213

II

~

g

r---------------------------------------------------------------------------------,

....

Pin Description

:!

DATA(1)

o

This is the serial data input for communications sent by a controller. The data rate has a
maximum frequency of 500 kHz. The
LMC1992 requires 11 bits of data to control '
or change a function: the first two bits, a 1
and 0, select the LMC1992, the next three
bits select a function, and the final six bits set
the function to a desired value. The data
must be valid on the riSing edge of the
CLOCK input signal.
CLOCK(2)
The CLOCK input accepts a TIL or CMOS
level clocking signal. The input is used to
clock the DATA input Signal and determines
when a data bit is valid.
EiiIABlJ:(3) This input accepts a logiC low signal when a
controller is addressing the LMC1992. When
~ is active, the LMC1992 responds to
input signals present on the DATA and
CLOCK inputs.
INPUT 1-4 Four two-channel analog inputs are available
(4-7,23-26) on the LMC1992. These pins should be dc-biased to mid-supply.
SELECT OUT The selected INPUT Signal is available at this
(8, 22)
output. This feature allows the use of external
signal processing such as noise reduction or
graphic equalizers. This output can typically
sink 1 mA.
SELECT IN This is the input that an external signal proc(9,21)
essor uses to return a signal to the LMC1992.
This is the input to the tone control amplifier.
TONE IN
(10,20)
See the Application Information section titled
"Tone Control Response".
TONE OUT Tone control amplifier output. See the Appli(11,19)
cation Information section titled "Tone Control Response".
OP AMP OUT This output is used externally with the tone
(12, 18)
control capaCitors. Internally, this output is
applied to the volume attenuators.

REAR OUT
(13, 17)

This pin's output signal is intended for the
rear amplifiers in a four speaker stereo system. The output can typically sink 350 pA
FRONT OUT This pin's output signal is intended for the
front amplifiers in a four speaker stereo sys(14, 16)
tem. The output can typically sink 350 pA
GROUND
(15)
This is the system ground connection.
V+ (28)
This is the power supply connection. The
LMC1992 is operational with supply voltages
from 6V to 12V. It is recommended that this
pin is bypassed with 0.1 ",F capacitor.
BYPASS (27) A 10 ",F capaCitor is connected between this
pin and ground.

General Information
The LMC1992 is a CMOS/bipolar high quality building block
intended for high fidelity audio signal processing. It is designed for line level input signals (300 mV - 2V) and has a
maximum gain of -1 dB. While the LMC1992 is manufactured with CMOS processing, NPN transistors are used to
build low noise op amps. The combination of CMOS
switches, bipolar op amps, and SiCr resistors make it possible to achieve an order of magnitude quality improvement
over other bipolar circuits that use analog multipliers to accomplish gain adjustment.
The LMC1992 has internal decoding logiC that allows a
computer (",P) to communicate directly to the audio control
circuitry through a standard MICROWIRE interface. This
three-wire interface consists of a DATA input line, a CLOCK
input line, and an i:lilAB[E line. When the EiiiA8[l: line is
low, data can be serially shifted from the controller to the
LMC1992. As the ENABLE line goes through the low-tohigh transition, any additional data is ignored. Data present
in the internal shift register is latched and the instruction is
executed.
Figure 1 shows the connection diagram of a typical
LMC1992 application.

y+ (+8V)
DATA
FROW

~P

CLOCK

CONTROLLER

ENABLE
LEFT INPUT 1
LEFT INPUT2
LEFT INPUT3
LEFT INPUT4

o.1~~

SELECT OUT

0.0082~fr=

TONE IN

T

SELECT IN
TONE OUT

\..../

1
2

27

3

26

<4

25

5

2<4

6

23

7

LMC1992

8

TO POWER AWPS

LEFT FRONT OUT

22
21

9

20

10

19

11

18

0.0082 ~r OP AWP OUT 12
LEFT REAR OUT

28

17

13

16

14

15

Vee

i

BYPASS

-

RIGHT INPUT 2
RIGHT INPUT 3
RIGHT INPUT <4
SELECT OUT
SELECT IN

1
d·
T

TONE IN

~

TONE OUT
OP AWP OUT

~.O

*

0.0

RIGHT REAR OUT
RIGHT FRONT OUT To POWER AMPS
GROUND

~

FIGURE 1. Typical Connection Diagram

1-214

+

RIGHT INPUT 1

RIGHT

LEFT

O.~

10 F

TLlH/10789-18

...ri:

Applications Information

(')

MINIMUM LOAD IMPEDANCE
The LMC1992 employs emitter-follower buffers at pins 8
and 22 (SELECT OUT), 13 and 14 (LEFT FRONT and
REAR OUTPUTs), and 16 and 17 (RIGHT FRONT-andREAR OUTPUTs) that buffer output signals. Typical bias
current of 1 rnA is used for the SELECT OUTPUT buffers
and 350 p.A for the LEFT-and-RIGHT, FRONT-and-REAR
OUTPUT buffers.
The Electrical Specifications table lists a maximum input signal of 2.3 Vrms (3.25 VpeaiJ for 1% THO at the SELECT
OUT pins. This distortion level is achieved when the minimum ac load impedance seen by the SELECT OUT pin is
3.25 kO (3.25V11 mAl. For the LEFT-and-RIGHT, FRONTand-REAR OUTPUTs, the typical maximum output is 1.2
Vrms (1.55 VpeaiJ. Therefore, the minimum load impedance
is 4.43 kO (1.55 V10.35 mAl. Trying to use a lower impedance results in a clipped output signal. Therefore, the
chBnce of clipping can be greatly reduced and much lower
distortion levels can be achieved by using load impedances
that are an order of magnitude higher than shown here.
For applications that require dc coupling and the INPUTs
biased to V+ 12, the minimum load impedance will differ
from that detailed in the above discussion. The emitter followers may be potentially operating at high currents because there is a dc voltage V+ 12 - 0.7V at the SELECT
OUT pins; dc resistance to ground will result in increased
current flow. Latch-up may occur if the total emitter current
exceeds 5 rnA. This current is a combination of the emitter
follower's 1 mA current source and 4 mA drawn by the external load. Therefore, to prevent this possibility, the minimum dc load impedance should be
Vpeak + (V+ 12 - 0.7V)
4 rnA
= 16380

=
N

10kA

I
10},F'~~

Rl
50kA

10kA

-==

O.'},F~~
Input "Signal

I

Pln4

TL/H/l0789-20

FIGURE 2. Input Bias Network
To allow for variations and part tolerances, 10 kO is a good
choice for this minimum dc load impedance.
INPUT IMPEDANCE
For ac coupled input signals the input impedance value is
determined by bias resistor R1, as shown in Figure 2. A
directly coupled input signal will see an emitter follower's
nominal input impedance of 2 MO.
The SELECT IN pins have an input impedance that varies
with the BASS and TREBLE control settings. The input impedance is 96 kO at de and 27 kO at 1 kHz when the controls are set at 0 dB. Minimum input impedance of 28 kO at
dc and 24 kO at 1 kHz occurs when maximum boost is
selected. At 10kHz the minimum input impedance, with the
tone controls flat, is 8 kO and, with the tone controls at
maximum boost, is 3 kO.
STEREO SIGNAL INPUTS
When operating with a single supply voltage, the stereo signal inputs must be dc biased to one-half of the supply voltage, as shown in Figure 2. As an example, with a supply
voltage of 8V, all signal sources should have a dc bias of
4V. The maximum input signal level of 6.5 Vp_p (for 10/0
THO) would then SWing from 0.75V to 7.25V. Input-to-input
crosstalk can be minimized by using a separate dc bias circuit for each stereo input pair.

Vpeak = 3.25V
V+ = 8V
To allow for variations and part tolerances, 2.0 kO is a good
choice for this minimum dc load impedance.
When dc coupling is used at the LEFT-and-RIGHT, FRONTand-REAR OUTPUTs, the output emitter followers will be
operating at a nominal dc voltage of V+ 12 - 2(0.7V).
Latch-up may occur if the total emitter current exceeds
1 mAo This current is a combination of the emitter follower's
0.35 mA current source and 0.65 mA drawn by the external
load. Therefore, to prevent this possibility, the minimum dc
load impedance should be
Vpeak + (V+ 12 - 2(0.7V»
"'!:'::'::;';"'-:0~.6::5~m~A:--"'----'- = 9 kO

EXTERNAL SIGNAL PROCESSING
The signal present at the selected input will be available at
the SELECT OUT pins 8 (left) and 22 (right). The de bias
voltage at those pins will be one base-emitter voltage, approximately 0.7 Vdc, below the source because of the internal emitter follower. Therefore, if the selected input has a
bias of 4.0 Vde the dc component at pins 8 and 22 will be
about 3.3 Vdc.
The LMC1992's SELECT OUT emitter followers allow additional signal sources using emitter follower outputs (such
multiple LMC1992s) to be "wired-ORed" together. When
this feature is in use, the input channel of the LMC1992 not
in use should be set to "open" input codes 01 OOOXXOOOO or
01 000XX011 X.

as

Vpeak = 3.25V
V+ = 8V

1-215

-

-----_._------

II

Applications Information

(Continued)

CLOCK
p.P CONTROLLER t:S::E=RIA:::L~D::-:"''::T'''~----''

1
.------------------------------------LMC1992
•

•
FUNCTIONS
~
ISTEREO 2Pi • +---<>,S:=EL=E"CT

•
~ NIC

DECODING,
LOGIC,

ETC.
TONE CONTROL
BASS - TREBLE

STEREO" 7'

TL/H/10789-19

FIGURE 3. System Block Diagram Showing Inclusion of DNR@ Noise
Reduction (LM1894) and Equalizer (LMC835) (One Channel Only-LMC1992)
The SELECT OUT pins (8 and 22) enable greater system
design flexibility by providing a means to implement an ex·
ternal processing loop. This loop can be used for noise reo
duction circuits such as DNR (LM1894) or mulit-band graphic equalizers (LMC835). It is important to ensure that if both
are used, the noise reduction circuitry precede the equalization circuits. Failure to do so will result in improper operation
of the noise reduction circuits. The system shown in Figure
3 utilizes the external loop to include DNR and a multi-band
equalizer.

The typical tone control response shown in the Typical Performance Curves were generated with C2 = C3 =
0.0082 f.£F and show the response for each step. When
modifying the tone control response it is important to note
that the ratio of C3 and C2 sets the mid-frequency gain.
Symmetrical tone response is achieved when C2 = C3.
However, with C2 = 2(C3) and the tone controls set to
"flat", the frequency response will be flat at 20 Hz and 20
kHz, and + 6 dB at 1 kHz.
The frequency where a tone control begins to deviate from
a flat response will be referred to as the turn-over frequency. With C = C2 = C3, the LMC1992's treble turn-over
frequency is nominally

AUDIO MUTE
A mute function with attenuation of 100 dB is possible with
the volume control set to -80 dB and the INPUT select
code set to 01000XXOOOO (open circuit).

1

fn

TONE CONTROL RESPONSE

= 2'ITC(14.2 kO)

The base turn-over frequency is nominally

Base and treble tone controls are included in the LMC1992.
The tone controls use just two external capacitors for each
stereo channel. Each has a corner frequency determined by
the value of· C2 and C3 (Figure 4) and internal resistors in
the feedback loop of the internal tone amplifier. The maximum amplitude boost or cut is determined by the data sent
to the LMC1992 (see Table I).

1
fBT = 2'ITC(27.7 kO)
when maximum boost is chosen. The inflection points (the
frequencies where the boost or cut is within 3 dB of the final
value) are for treble and bass
Irl = 2'ITC(2.3 kO)

fBI = 2'ITC(164.1 kO)

1-216

Applications Information

(Continued)
SERIAL COMMUNICATION INTERFACE
Figure 5 shows the LMC1992's timing diagram for its three
wire MICROWIRE interface. A controller's data stream can
be any length; once the correct device address is received
by the LMC1992, any number of data bits can be sent; the
last nine bits occurring before EiiIABLE goes high are used
by the LMC1992. The first two bits in a valid data stream are
decoded and used as device address bits. The LMC1992
uses a unique address of 1,0. The LMC1992 will not respond to information on the DATA line if any other address
is used. This allows other MICROWIRE serially programmable devices to share the same three-wire communication
bus. When ENABLE goes high, any further serial data is
ignored and the contents of the shift register is transferred
to the data latches. Only when information is received by
the data latches do any function or setting changes take
place. The first three of nine bits select one of the
LMC1992s functions. The remaining six bits set the selected function to the desired value or position.

C3
0.0082pF
12(18)
11(19)
OUT

10(20)

2.6 k4 11.4k4 2.6 k4
Treble
Bass 116.4 k4

116.4k4

S09.2k4

Volume

V+/2

A data bit is accepted as valid and clocked into an internal
shift register on each rising edge of the signal appearing at
the LMC1992s CLOCK input pin. Proper data interpretation
and operation is ensured when ENABLE makes its falling
transition during the time when CLOCK is low. Erroneous
operation will result if the ENABLE Signal makes its falling
transition at any other time.

TL/H/10789-22

FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 = C3 = 0.0082, 2 dB steps are
achieved at 100 Hz and 10kHz. Changing C2 and C3 to
0,01 p.F shifts the 2 dB per step frequency to 72 Hz and 8.3
kHz. If the tone control capaCitors' size is decreased these
frequencies will increase. With C2 = C3 = 0.0068 p.F the 2
dB steps take place at 130 Hz and 11.2 kHz.
FADER FUNCTION
The four fader functions are all independently adjustable
and therefore no balance control is needed. Emulating a
balance control is accomplished through software by simultaneously changing a channel's front and rear faders by
equal amounts. To satiSfy normal balance requirements the
faders have an attenuation range of 40 dB.

II

CLOCK
DATA
DON'T CARE

I

I

I

WSB
0

ENABLE

A2

I

LSB
Al

AO

OS

D4

03

02

01

DO

I

I

DON'T CARE

,

:'(Note2)

CHIP SELECT
ADDRESS

FUNCTION ADDRESS

DATA WORD

TL/H/10789-21

Nota 1: Negative transition on ENAm:E clears previous address. Clock must be low during transition.
Note 2: Additional don't care states may be inserted here for ease of programming. (Optional.)
Note 3: Positive transition on ~ latches In new data If the LMC1992 has been addressed. Clock osn eRher be high or low during trsnsRion.

FIGURE 5. Clocking Data Into the Standard MICROWIRE Interface
(Minimum Number of Bits In Data Stream)

1-217

Applications Information (Continued)
TABLE I. Programming Codes for LMC1992

A2

Address
A1
AO

Function

05

04

Oata
03

02

01

00

Values

1

1

1

Left Rear Fader

X

MSB

N

N

N

LSB

-40 dB = XOOOOO
-20 dB = X01010
OdB = X1010X

1

1

0

Right Rear Fader

X

MSB

N

N

N

LSB

-40 dB = XOOOOO
-20dB = X01010
OdB = X1010X

1

0

1

Left Front Fader

X

MSB

N

N

N

LSB

-40 dB = XOOOOO
- 20 dB = X01010
OdB = X1010X

1

0

0

Right Front Fader

X

MSB

N

N

N

LSB

- 40 dB = XOOOOO
-20 dB = X01010
OdB = X1010X

0

1

1

Volume

MSB

N

N

N

N

LSB

-80 dB = 000000
-40 dB = 010100
OdB = 10100X

0

1

0

Treble

X

X

MSB

N

N

LSB

-12dB = XXOOOO
FLAT = XX0110
+12dB = XX1100

0

0

1

Bass

X

X

MSB

N

N

LSB

-12 dB = XXOOOO
FLAT = XX0110
+12dB = XX1100

0

0

0

Input Select

X

X

0

MSB

N

LSB

OPEN = XXOOOO
iNPUT1 = XXOO01
INPUT2 = XX0010
INPUT3 = XX0011
INPUT4 = XX0100

Note 1: All allenuators 2 dBfstep.
Note 2: Tone controls 2 dBfstep 111100 Hz and 10 kHz.
Note 3: Use of data that deviates from the values shown in the table may resuH in erroneous resuHs.

controls' input code increases from XXOOOO (-12 dB) to
XX0110 (0 dB) to XX1100 (+12 dB). The code for the FADERs starts from XOOOOO (-40 dB) and goes to X1010X
(0 dB).

SERIAL OATA FORMAT
Table I displays the required data format needed by the
LMC1992. Not shown is the 2-bit device address (10).
These two bits of information must precede the final ninebits used as the data word. The first three of these nine bits
is the function address.

The table shows that VOLUME is the only function that uses
all six bits to choose that function's setting. The remaining
functions use less than six bits; the unused bits are shown
as "X"s ("don't care"). While these "don't care" bits have
no effect on their respective function, the LMC1992 must
receive them for proper operation. If neglected, erroneous
or unknown results will occur.

The VOLUME, TONE, and FADER controls are designed to
increment their settings (in 2 dB steps) as the control data is
incremented by one LSB. Disregarding the device address
and the function address, the VOLUME input code increases from 000000 (-80 dB) to 10100X (0 dB). The TONE

1-218

Applications Information

(Continued)

DATA TRANSFER EXAMPLE

DATA TRANSFER ROUTINE 2

The following routines, based on the flowchart shown in Figure 6, are examples of COPSTM microcontroller instruction
code that can be used to control the LMC1992 (see National Semiconductor's COPS Microcontrollers Databook for
more information). These routines arbitrarily select COPS
register 0 for I/O purposes. When these routines are entered, it is assumed that chip select is high, SK (clock) is
low, and SO (data) is low. These routines exit with chip select high and SK and SO low. Output port GO is arbitrarily
chosen to send the chip select signal to the LMC1992.
The 11 data bits needed to control the LMC1992 are assumed to be in the 4-bit registers, 13-15, with the 4 MSBs
in register 13. With this configuration there is an extra bit for
a data stream that is 12 bits long. As previously mentioned,
there can be any number of extra bits between the device
address and the function address.

This routine performs the same function as routine 1 while
preserving the contents of the data registers. This routine
takes only 21 ROM memory locations.

OUT1:

This general purpose routine handles all the overhead except loading data into registers 13-15. It sends the data
according to the conditions discussed above. The data will
be lost at the conclusion of the routine. This routine consumes only 17 ROM memory locations.

SEND:

LBI

0,13

SC
OGI

14

LEI

8

LD
XAS
XIS
JP SEND
RC
OGI 15
LEI
RET

0

0,13

SC
OGI

14

LEI

8

JP
SEND1: XAS
SEND2: LD
XIS
JP
XAS
RC

DATA TRANSFER ROUTINE 1

OUU:

LBI

SEND2
;DATA TRANSMISSION LOOP
;TURN-ON CLOCK
SEND1

CLRA
NOP
XAS
OGI 15
LEI 0
RET

;POINT TO START OF DATA
;WORD
;SET C TO ENABLE SK CLOCK
;SELECT EXTERNAL DEVICE GO
;= 0
;ENABLE SHIFT REGISTER
;OUTPUT

;POINT TO START OF DATA
;WORD
;SET C TO ENABLE SK CLOCK
;SELECT EXTERNAL DEVICE
GO ;=0
;ENABLE SHIFT REGISTER
;OUTPUT

;SEND LAST DATA
;WAIT 4 CYCLES - DATA
;GOING OUT
;TURN SK CLOCK OFF
;DE-SELECT DEVICE
;SET SO TO 0

;DATA TRANSMISSION LOOP
;TURN-ON CLOCK

II

;DE-SELECT EXTERNAL
DEVICE
;SET SO TO 0

1-219

Applications Information (Continued)

- - - SETUP INITIAL CONDmONS

(clock "low", enable "high")
- - - ENABLE LIotC1992's MICROWIRE
INTERFACE

SELECT LtotC1992
WITH LEADING
"ID" ADDRESS

FUNCTION ADDRESS AND
DATA WORD
OUTPUT LOOP (9BITS)

no

---DISABLE LtotC1992's IotICROWIRE
INTERFACE

TLlH/l0789-23

FIGURE 6. General Data Transmission Flowchart to Send Serial Data
to the LMC1992's MICROWIRE Compatible Digital Inputs

1-220

Section 2
Radio Circuits

fI

Section 2 Contents
Radio Circuits Definition of Terms ...........................•.........•..............
Radio Circuits Selection Guide .......................................................
LM1211 Broadband Demodulator System .........................................•..•
LM1596/LM1496 Balanced Modulator·Demodulators ..................................•
LM1865 Advanced FM IF System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1868 AM/FM Radio System.......................................................
LM3089 FM Receiver IF System. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
LM3189 FM IF System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
LM3361A Low Voltage/Power Narrow Band FM IF System..............................

2·2

2·3
2-4
2·6
2·16
2·21
2·35
2·43
2·49
2·56

~National

~ Semiconductor

Radio Circuits
Definition of Terms
AGC de Output Shift: The shift of the quiescent Ie output
voltage of the AGe section for a given change in AGe central voltage.

-3 dB Limiting Sensitivity: In FM the input signal level
which causes the recovered audio output level to drop 3 dB
from the output level with a specified large signal input.

AGC Figure of Merit: The widest possible range of input
signal level required to make the output signal drop by a
specified amount from the specified maximum output level.
Typical F.O.M. numbers are from 40 dB to 50 dB, for domestic radios and about 60 dB for automotive radios (for
-10 dB output level change).

Lock In Range: That range of frequencies about the free
running frequency for which the phase locked loop will
come into lock if initially starting out of lock.
Maximum Sweep Rate: The maximum rate that the veo
may be made to vary its oscillating frequency over its
Sweep Range.
Output Resistance: The ratio of the change in output voltage to the change in output current with the output around
zero.

AGC Input Current: The current required to bias the central
voltage input of the AGe section.
AM Rejection Ratio: The ratio of the recovered audio output produced by a desired FM signal of specified level and
deviation to the recovered audio output produced by an unwanted AM signal of specified amplitude and modulating
index.

Output Voltage Swing: The peak output voltage swing, referred to zero, that can be obtained without clipping.
Phase Detector Sensitivity: The change in the output voltage of the phase detector for a given change in phase between the two input Signals to the phase detector.

Channel Separation: The level of output signal of an undriven amplifier with respect to the output level of an adjacent
driven amplifier.

Power Bandwidth: The power bandwidth of an audio amplifier is the frequency range over which the amplifier voltage gain does not fall below 0.707 of the flat band voltage
gain specified for a given load and output power.
Power bandwidth also can be measured by the frequencies
at which a specified level of distortion is obtained while the
amplifier delivers a power output 6 dB below the rated output. For example, an amplifier rated a 60W with ';;0.25%
THD, would make its power bandwidth measured as the
difference between the upper and lower frequencies at
which 0.25% distortion was obtained while the amplifier was
delivering 30W.
Power Supply Rejection: The ratio of the change in input
offset voltage to the change in power supply voltages producing it.
Slew Rate: The internally limited rate of change in output
voltage with a large amplitude step function applied to the
input.
Supply Current: The current required from the power supply to operate the amplifier with no load and the output at
zero.
Sweep Range: That ratio of maximum oscillating frequency
to minimum operating frequency produced by varying the
central voltage of the veo from its maximum value to its
minimum value with fixed values of timing resistance and
capacitance.
VCO Sensitivity: The change in operating frequency for a
given change in veo central voltage.

Detection Bandwidth: That frequency range about the free
running frequency of the tone decoder/phase locked loop
where a signal above a specified level will cause a detected
signal condition at the output.
Detection Bandwidth Skew: The measure of how well the
detection bandwidth is centered about the free running frequency. It is equal to the maximum detection bandwidth frequency plus the minimum detection bandwidth frequency
minus twice the free running frequency.
Hold In Range: That range of frequencies about the free
running frequency for which the phase locked loop will stay
in lock if initially starting out in lock.
Input Resistance: The ratio of the change in input voltage
to the change in input current on either input with the other
grounded.
Input Sensitivity: The minimum level of input signal at a
specified frequency required to produce a specified signalto-noise ratio at the recovered audio output.
Input Voltage Range: The range of voltages on the input
terminals for which the amplifier operates within specifications.
Large-5ignal Voltage Gain: The ratio of the output voltage
swing to the change in input voltage required to drive the
output from zero to this voltage.

2-3

~National

Semiconductor

Radio Circuits Selection Guide
AM RF/IF Detector

Device

Portable

Home

LM1868

•

•

Auto

Synthesized

Pin
Count
(Dip
Package)

Supply
Range

Max Input
Sensitivity
for 20 dB
SIN Ratio

AM
and
FMIF

Audio
Power
Amplifier

Internal
Detector

20

4.5-15V

12 p.V

•

•

•

Meter
Output

'SO Surface Mount Package Only

Stereo Decoder
Device

Portable

Home

Auto

Pin Count
Dip
Package

LM4500A

•

•

•

16

Supply
Range

THD

Separation

8-16V

0.1%

40 dB

Blend

High
Cut

Lamp
Driver

Output
Buffer

ARI
Interference
Rejection

•

•

•

Modulators & Demodulators Selection Guide
LM1211

LM1496

Typical Application

Broadband Demodulator

Balanced Modulator-Demodulator

Key Features

• Configurable for AM or FM Based Signals

• Wide Frequency Response to 100 MHz

• 20 MHz-80 MHz Operating Frequency Range

• Fully Balanced Inputs and Outputs

• 25 MHz Detector Output Bandwidth

• Adjustable Gain and Signal Handling

• Linear Output Phase Respcnse

2-4

FM IF/Detector
Portable

LM1865
LM1868

•

LM3089
~

U1

LM3189
LM3361 A" *

•

Home

Auto

Synthesized

Pin Count
Dip

Pin Count

•
•
•
•

•

•

20

20

S.O.

Supply
Range

-3 dB Limiting
Sensitivity

THD

Mute

AGC
Outputs

AFC

Meter
Output

•

Reverse

•

•

7.3·16V

60/LV·

0.1%

20

4.5-15V

15/LV

1.1%

•

16

8-16V

12/LV

0.5%

•
•

16

8-16V

12/LV

0.5%

2-9V

2/LV

-

16

16

AM/
FMIF

•
•
•

•
•

•
•

•
•

•

'Exclusive of 22 dB Buffer

"Narrow-Band FM-IF

ap!no UO!IOaI8S SI!nOJ!:l O!peu

II

.,...
.,...
N
.,...

....:::& ~National
~ Semiconductor
LM 1211 Broadband Demodulator System
General Description

Features

The LM1211 is a high performance IF amplifier and product
detection system for operation in the 20-80 MHz frequency
range. It is suitable for data or video recovery from broadband local area networks and other communications systems.

•
•
•
•
•
•
•
•
•
•

The high gain IF amplifier has a SAW filter compatible input
and can be gain-controlled in excess of 40 dB. A flexible
product detector is used in which the input signal is multiplied by a reference derived from limiting and phase-shifting
the input. The signal input is separate from the reference
path, which has a port for external connections. A DC-operated phase control is provided for detection phase adjustment.

Configurable for AM or FM based Signals
20-80 MHz operating frequency range
IF input SAW filter compatible
>40 dB IF gain control range
25 MHz detector output bandwidth
Linear output phase response
Output swings ±3.5V referenced to ground
Gateable peak-following AGC detector
DC-adjustable detection phase
DC-adjustable 0 carrier output level

The detector is followed by a 25 MHz bandwidth amplifier
which has a symmetric output swing capability around OV. A
fast attack, peak-following AGC detector is also provided for
use in AM systems.

Connection Diagram

r-_ _ _ _+-l0~ REF. LIMITER INPUT

I.F. OUTPUT-~I------.

9

r-+-- DETECTOR INPUT

12V SUPPLY-~I-.

8

I.F. REGULATOR-~H~-I

.----l1-l1-f.;..7-

I.F. DECOUPLE-...;..;..jL..-r.,

..~ {-~---

"

......

GROUND
DEl. PHASE ADJUST

+:;.-.-} - - -

I - -....

r------+4~-OUTPUT D.C. ADJUST

I.F. DECOUPLE-~------'

>_---1~-+3~- DETECTOR OUTPUT

GROUND --.;~--,

2

AGe FlLTER-~--6-{

SUPPLY DECOUPLE

L-----.':"'"+--AGe THRESHOLD

AGe BIAS/GATE-~------'

TL/H/9127-1

Order Number LM1211N
See NS Package Number N20A

2-6

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Seles
OffIce/Distributors for availability and specifications.
Power Supply Voltage, V12
15V
IF Supply Current, 113
40mA
Detector Output Current, 13
15mA
Detector Input Signal, V9
1 Vrms
Ref. Limiter Input Signal, Vl 0
1 Vrms
AGC Bias/Gate Current, 120
3mA

Power Dissipation
Thermal Resistance
Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 sec.)
ESD Susceptibility (Note 1)

1.67W
60"C/W
125°C
- 40"C to + 85°C
- 65°C to + 150"C
26O"C
3000V

Ii:
....
N
....
....

DC Electrical Characteristics
TA

= 25°C, Test Circuit, VIF = VOe! = 0, VAGC = 0, VPH = 4V, Vec = 6V, all switches open unless noted.

Symbol

Paremeter

Teat Condltlona

Typ

= 3V·
= 3V

67
6.5

Is
V13

Supply Current
IF Regulator Voltage

SW 3 closed, VAGC
SW 3 closed, VAGC

V15/16

IF Input Voltage

SW 2, 3 closed

V14-V17
111

IF Decouple Vas
IF Output Current

SW 2,3 closed, measure V14-V17

Vl0

Limiter Input Bias

SW 1, 2, 3 closed

5.1

V9

Detector Input Bias

SW 1, 2, 3 closed

5.1

V5/6

Reference DC Voltage

SW 1, 2, 3 closed

4.6

Vec

o Carrier Output Voltage
o Carrier Adjust Voltage

SW 1, 2, 3 closed
SW 1, 2, 3 closed, adjust Voc for V3

119(0)

AGC Discharge Current

SW 1, 3 closed, VAGC - 2V

-11

119(C)

AGC Charge Current

SW 1, 4 closed, VAGC

= 6V

1.0

V3

SW 2, 3 closed, VAGC

3.9

= 6V, 111 =

12V-Vll
50

= OV

0
4.0

0
6.0

Tested
Umlt
(Note 2)
80
5.8
7.0
3.4
4.4
±50
2.5
5.0
4.5
5.5
4.5
5.5
4.0
5.2
±0.5
1.0
11.0
-7
-16
0.7
1.3
±200

-25
AGC Leakage Current
SW 1, 2, 4 closed, VAGC = 4V
119(l)
Note 1: Human body model, 100 pF dlacharead through a 1.5 kIl resistor.
Note 2: Tested limits are guaranteed and 100% production tested.
Note 3: Design limits are guaranteed, bu1 no11 00% production tested. These limits are no1 used to determine ou19Oing quall1y levels.

2·7

Design
Umlt
(Note 3)

Unlta
(Limit)
mA(max)
V (min)
V (max)
V (min)
V (max)
mV(max)
mA(min)
mA(max)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
V (max)
V (min)
V (max)
lJA(min)
IJA (max)
mA(min)
mA(max)
nA(max)

fII

-N

~

Detector AC Set-up Procedure TA =

25'C, TestCircuit,Sw1,2,3closed, VAGC=O,VPH= 4V.
1. With no input (VOet = 0), adjust VOC for V3 = OV.
2. Apply VDet = 100 mVrms, 60 MHz CW at th,e input. Tune L2 for maximum DC voltage at output Pin 3.

AC Electrical Characteristics TA =

"

25'C, Test Circuit, Follow AC set-up procedure, f = 60 MHz, VAGC ;., 0,

VPH = 4V, VOC as per set-up, all switches open unless noted.
Symbol

Parameter

Z15/16

IF Input Impedance

Measure Differential Impedance between
Pins 15 and 16.

Av(IF)

Maximum IF Gain (Note 3)

SW 2 Closed, VIF = 0.5 mVrms, Measure YOu!.

Test Conditions

Av(IF) = 201 09
VAGC20

20 dB Gain Reduction

VAGC40 40 dB Gain Reduction
1M

IF Intermodulation
(Note 3)

(5XV~~

4)

Z9

Detector Input Impedance

Z10

Reference Limiter
Input Impedance

Measure Impedance into Pin 10

Av(D)

Detector Conversion Gain

SW 1, 2, 3 Closed, VDet = 100 mVrms,

LIN

Detector-6dB Linearity

SW 1, 3 Closed, VOet = 50 mVrms,
Measure Va'. LIN = 20 log

AGC Threshold

Va(Th)

(~~ )

(~~)

SW 1, 3 Closed, Increase VDet until
119 = 100 iJ-A, Measure Va.

2.6
3.8

Detector Harmonic Levels

40
80

Units
(Umit)

o (min)
o (max)

20

dB (min)

2.2
3.0
3.3
4.3

V (min)
V (max)
V (min)
V (max)

-40

-30

dB (min)

3.0

2.0
5.0

2.0

1.3
5.0

KO(min)
pF(max)
KO(min)
pF(max)

24

-6

20

dB (min)

30

dB (max)

-5

dB (min)

-7

dB (max)

3.5

V (min)
V (max)
V (min)

0.95

VIV(max)

0.60

VIV(max)

-3.0

V (min)

2.6
3.0

2.8

Detector Overload Capability SW 1,2,3 Closed, VDet = 1 Vrms, Measure Va.
4.1
Va(ol)
PHA(+) DC Phase Adjust ( + )
SW 1, 2, 3 Closed, VOet = 100 mVrms, Measure
0.65
RatiO of Va with VPH = 6V to Va with
VPH = 4V.
PHA(-) DC Phase Adjust ( - )
SW 1, 2, 3 Closed, VOet = 100 mVrms, Measure
0.30
Ratio of Va with VPH = 2V to Va with
VPH = 4V.
Negative Output Swing
SW 1, 2, 3 Closed, f = 70 MHz, VOet = 300 mVrms, -3.7
Va(-)
VPH = 6V, Measure Va.
DBW
Detector Output Bandwidth SW 1, 2, 3 Closed, Modulate VDet with 30% AM
25
Modulation. Increase Modulation Frequency Until
Pin 3 Signal Drops 3 dB.
DHL

Tested Design
Limit
Limit
(Note 1) (Note 2)

60
30

SW 2 Closed, VIF = 5 mVrms, Adjust VAGC
for Same VOu! as in Av(IF) Test.
SW 2 Closed, VIF = 50 mVrms, Adjust VAGC
for Same Vout as in Av(IF) Test.
SW 2 Closed, f, = 60 MHz, f2 = 65 MHz,
VIF = 10 mVrms Ea, Adjust VAGC for
VOu! = 10 mVrms Ea, Measure 1M Products
Relative to YOu!.
Measure Impedance into Pin 9

Measure Vaoc. Av(D) = 20 log

Typ

20

MHz (min)

SW 1,2, 3 Closed, VOet = 100 mVrms, Measure
-35
-20
dB (min)
60 MHz and 120 MHz Levels Relative to Va
Note 1: Tested limits are guaranteed and 100% production tested.
Note 2: Oeslgn limits are guaranteed, but not 100% production tested. These limbs are not used to determine outgoing quality levels.
Note 3: The IF arnplifl9r output is measured with the IF output connected to a 500 measurament system resulting in a 250 loaded impedance. The gain In an
actual application will typically be 20 dB higher.

I

2-8

~
.....
.....
.....

Test Circuit

~

Measure Parameters at Indicated Test Points

~

Your

~O'OIPF

O.OIP~

~------------------------~
VIIo--",IIVO"K_+-...;
;.;.
+~----------~---~~~--oVIO

___-.

240

0.001 pF

.::c.
VI4

10K

'--1~~IV_0."Kir"OV5/ 6

SW3

20

+12

•

10K

1

-

0-0-5V

+12V
BK
IK

3K

TL/H/9127-2

Tl

= 501l unbal. to bal. Mlnl-circuits Lab TMOH·H

L2

=

4% T #22 wire on

%," form with HF core,

shielded

2-9

FJI

..~

:=;

r-----~----~------------~----------~----------------------------------------~

Typical Performance Characteristics
(All characteristics apply to the typical application circuit. Figure numbers are referenced in the applications information.)
FIGURE 1
IF Amplifier Gain
o Reduction Characteristic

'\

FIGURE 3
IF Amplifier Noise
12 Figure vs. AGC

FIGURE 2
IF Amplifier
oFrequency Response

r- r...

1\ =2004

......

f=60WHz

10

'r\.

\

\

~
~

;:

\

-12

RL=2004
-60

-15

90

0102030405060708090

PIN 19 VOLTAGE (V)

fREQutIICY (11Hz)

'~

V9=Vl0
V7=4V

"\

~

I"
L2=3.9t'H

FIGURES
Detector Phase
90 Adjust Characteristic
60

\. ~

-90

GAIN REDUCIlON -20dB

01234567

FIGURE 4
LM1211 Detection Phase

~=1 H

"'\

~

....

r....

N

4045 50 55 80 65 70 75 80 65,

fREQUDlCY (WHz)

!,

lr GAIN

o

GAIN REDUCIION (dB)

FIGURE 6
Output Amplifier
o Frequency Response

~

",

'\

" . --

-90

= 60 dB

0102030405080

r-.!~ 60WHz

f==40"H~,

~=2.21'

lL

V

\

'\

,i' r-

2.0 2.5 3.0 !.5 4.G 4.5 5.0 !.5 8.0

PIN 7 VOLTAGE (V)

\

-5
o

5

10

15

20

25

30

35

F'REQUDlCY (MHz)
TL/H/9127-3

Typical Application Circuit

+12V

+12V
10K

0 CAR.
LML

>-~~-T---t----oOUT

2K

~=-.#tNIr-()-5V

+ 2V

9.1 K

3K

TL/H/9127 -4

2-10

Applications Information

(Refer to Typical
Performance Characteristics and Application Circuit.)

The LM1211 broadband demodulator system provides essentially independent IF amplifier and wideband detector
blocks on the same integrated circuit. The IF amplifier consists of 5 differential stages, 3 of which have gain control
capability. The detector is a highly flexible product detector
with separate signal and reference input pins and a wideband output amplifier. An AGC comparator operating from
the detector output is also provided. The operation of each
of these blocks will now be described.

put or detector reference signals couple into these pins it
can cause changes in the frequency response and can easily promote oscillation. A spectrum analyzer is invaluable for
helping determine the system susceptibility to this phenomenon. With the Input terminated by the IF filter (or an equivalent resistor), the IF amplifier output noise spectrum will
show if oscillation is likely to occur at maximum gain. A good
layout will have symmetrical input leads placed as close together as possible, shielded input coils (where used), and
external components mounted as close to the I.C. as possible. The DC feedback decoupling capaCitor connected between Pins 14 and 17 should be right against the pins.

IF AMPLIFIER
The IF amplifier is powered from an internal shunt regulator
between IF supply Pin 13 and IF ground Pin 18. The regulator has a nominal value of 6.5V and the IF amplifier current
is delivered through a dropping resistor from the 12V rail
supplying the remainder of the LM1211. The 0.001 /LF ceramic RF decoupling capaCitor at Pin 13 should be grounded through very short leads-preferably on the copper side
of the PCB. A nominal current level into Pin 13 is 23 mA, set
by a 2400 resistor. This current should not exceed 40 mA
and the minimum current is about 16 mA, below which the
IF amplifier will start to lose gain as the Pin 13 voltage drops
below the regulated level.

Gain Control Stages
The second through fourth differential stages of the IF amplifier are gain controlled by the voltage at the AGC Filter
Pin 19. OV corresponds to maximum IF gain, while increasing the Pin 19 voltage results in the gain reduction curve
shown in Figure 1.
In most AM applications, the Pin 19 voltage will be under
control of the AGC detector (to be described later) in a
closed feedback loop. If Pin 20 of the AGC detector is
grounded, Pin 19 is tri-stated, allowing it to be externally
controlled. In the tri-stated condition the typical input bias
current at Pin 19 is only 25 nA, allowing small filter capacitors to be used in gated AGC systems. The Agure 1 characteristics has a temperature dependence of approximately
-0.1 dB/oC. While this has no bearing in a closed loop
system, it precludes setting a temperature stable fixed gain
via a resistive divider at Pin 19.
For FM applications, the IF amplifier may be locked at maximum gain by grounding Pin 19. Under these conditions
none of the 5 stages saturate when overdriven, allowing the
amplifier to function as a basic wideband limiter.

IF Amplifier Input Configuration
Circuit detail for the IF amplifier input Pins 14-17 is shown
in Figure 1. The input stage is a common-base differential
amplifier designed to give good rejection of unwanted IF
output and detector reference signals that may be radiated
back to the input.
The low differential input impedance of 600 ensures that
SAW filters are terminated sufficiently to keep the triple transit echo (TTE) more than 40 dB below the signal level, even
with low impedance SAW filters. Because it is a common
base stage, the input stage gain is inversely proportional to
the source impedance Zs presented to the input. A normal
range for differential Zs is from 1000 to 1 KO. As an example, a typical high impedance SAW filter has an output impedance that can be modeled as a 2 KO resistor in parallel
with 6 pF capacitance, yielding Zs = 3720 at 70 MHz. Alternatively, the IF may be used with a transformer input configuration similar to that shown in the Test Circuit, as long as
the required source impedance is maintained.
A balanced input is extremely important since the input
leads to Pins 14-17 are the most sensitive points in the
system to unwanted IF coupling. For example, if the IF out-

150--......-

__

IF Amplifier Output
The fifth and final IF amplifier stage has a single-ended output, with no internal connection to the detector block. The
output Pin 11 is an open collector NPN transistor which
must be returned to Pin 12 via a DC path. Pin 11 is also a
point at which any additional signal filtering may be applied.
A resistive load connected to Pin 12 can be used, but the
maximum value is limited in practice to less than 5000 at
intermediate frequencies because of stray capaCitance and
the loading of the detector stage input Impedance.

270

_-f------'\M---o5.4V
10K

1K

1

IF
OUTPUT

BALANCED
INPUT

j

>-+--011

1K

. 10K

16o--6--~

270

'-----4_---"""'I'---o5.4V

FIGURE 7. Low Impedance Common Base Input Stage

2-11

TL/H/9127-5

II

..~
.-

:!l

.-----------------------------------------------------------------------------------------~

Applications Information (Refer to Typical
Performance Characteristics and Application Circuit.)
(Continued)
The frequency response. for the IF amplifier with a 2000
load is shown in Figure 2. The high frequency rolloff gives
rise to a potential problem called "tilt." This occurs in wide
bandwidth signals when the upper frequency components
are attenuated relative to the lower frequency components,
which can cause amplitude distortion following demodulation. Tilt can be easily compenSllted at Pin 11 by using an
inductive load to provide an increasing impedance with frequency. The impedance of inductive load L1, including the
effects of stray capacitance, is given by:

Izd =

A _ (1000)IZd
v - IZsl + 60
The IF amplifier noise figure (NF) as a function of gain reduction is shown in Figure 3. The contribution of IF NF to
the overall system NF depends on the amount of gain
ahead of the IF in the mixer and IF filter.
The SAW filter output mistermination, determined by the IF
amplifier input impedance, is desirable from the viewpoint of
keeping the TIE more than 40 dB below the signal. However, the mismatch at the input to the SAW filter is not so
desirable as it simply increases the filter losses. Therefore a
preferable solution is to use a low impedance SAW filter
which will reduce losses, or to provide a pre-amplifier stage
such as shown in Figure 8 between the mixer and SAW
filter. Since this stage can also be used to match the mixer
output to the SAW filter input, the filter losses can be reduced.
To illustrate the effectiveness of this approach, a 10 dB gain
pre-amp with a 4 dB NF will put the NF after the mixer stage
at 23 dB, and the increase in NF with AGC action (by about
4 dB) will not contribute significantly to the system NF. A
useful rule of thumb is that the total NF of the stages following the mixer should not exceed the mixer gain.

CilL1
1 - C112L1CS

For example, a 0.33 ",H coil with 8 pF stray capacitance at
Pin 11 has an impedance of 3000 at 70 MHz, and this impedance is on a frequency dependent slope of 0.4 dB/MHz.
As the inductance is increased, the slope becomes steeper
until resonance with the stray capacitance is reached. By
using this technique, a flat IF response can be obtained
over the frequency range of interest.
IF Amplifier Gain and Noise Figure
As described earlier, the maximum IF amplifier gain in the
LM1211 is externally determined by the input source impedance, Zs, in conjunction with the output load impedance, ZL.
This gain is approximately given by:

330

61<8

~III
J.
I -=

Ci

3~0

75

0.01 p.F

I,

0.~1~-r:;;

(l.~P--i".------.

0.5p.H

12V

o.J~

t{S-Hl0

~

1 Kl
36

TLlH/9127-6

FIGURE 8_ SAW Filter Gain Stage

Detector
The detector section operates from a 12V supply between
Pin 12 and ground Pin 8. The LM1211 uses a product detector comprised of a multiplier, reference limiter, detector
phase adjuster, and wideband output amplifier (see block
diagram). The demodulation process of multiplying the detector input by a limited version of the Input is called quasisynchronous detection. This process provides a wider reference bandwidth but reduced effIC:iency· in carrier nulls relative to a true synchronous qetector.
While the following description will app,lyto quasi-synchronous detection, the LM1211 can be made to function as a
true synchronous detector if an external phase-locked loop
(PLL) is used. In this mode, the reference limiter input Pin 10
Is decoupled and the voltage-controlled oscillator (VCO) signal from the PLL is coupled into the reference port at Pins 5
and 6. Differential coupling of any external Signal into the
reference port Is critical to minimize feedback to the IF amplifier inputs.

Multiplier
The heart of the product detector is the 6 transistor balanced multiplier shown in Figure 9. The detector input Vs(t)
at Pin 9 is coupled to the linear differential pair, while the
reference input Vr(t) switches the upper quad devices at the
carrier rate. .
If Vs(t) is an amplitude modulated carrier Fm(t)coswt and
Vr(t) is a SQuare wave of the same frequency wand relative
phase , then the filtered output is given by:
2 RL
VOUT = ;: Re Fm(t)cos
The output depends on the amplitude of Vs(t) and relative
phase  between Vs(t) and Vr(t). If  is made 0 degrees so
cos is 1, then the multiplier acts as an amplitude detector
and can be used to detect the amplitude modulation Fm(t)
on the IF carrier. Note that around 0 degrees cos changes
very little with phase. The multiplier can also be used as a
2-12

r-

Detector (Continued)
phasing the detector is to first select the external components which produce the desired detection phase when the
phase adjust control is in the center of its range (V7 = 4V),
and then use the control to trim part-to-part and external
component variations.
The curves of Figure 4 give the multiplier detection phase
versus frequency for different values of L2 with Pins 9 and
10 shorted together. These curves can be used to select
the L2 value and to determine whether additional phase
shift between Pins 9 and lOis required. The detection
phase versus temperature is approximately - 0.25 degrees/

·C.
A detection phase of  = 0 degrees corresponds to maximum (+) amplitude detection efficiency, i.e. the detector
output voltage increasing with Pin 9 input level. In the simplest case this can be obtained by choosing the L2 for
which the Figure 4 curve passes through 0 degrees at or
near the IF frequency. When the proper phasing cannot be
obtained by this means, phase lead or lag must be introduced at Pin 10 relative to Pin 9. A simple RC lead-lag network which can provide up to ± 90 degrees phase shift is
shown in Figure 10.
When XC1 = XC2 = 2400 in the Figure 10 circuit, approximately 90 degrees of phase difference between Pins 9 and
lOis produced with 3 dB additional attenuation. Pin lOis
shown lagging Pin 9, but the two pins could be reversed to
produce phase lead. If C1 is increased or C2 is decreased,
the phase difference is reduced.
A wideband FM quadrature detector is implemented in Figure 11 by configuring the IF Amplifier for maximum gain and
replacing L2 with an LC tank tuned to the IF frequency.
Since the IF Amplifier performs the limiting function, the reference limiter is not used; rather, the quadrature Signal is
fed directly to the reference port via an RC phasing network.
The DC offset at Pin 10 (13 KO to 12V) prevents signal
leakage through the reference limiter to Pins 5 and 6.
The FM detector sensitivity depends on the phase slope of
the LC tank, which is determined by the Q. For example, the
tank in Figure 11 is resonant around 70 MHz and has a Q '"
2 defined by the internal 1 KO resistance across Pins 5 and
6 in parallel with the external resistor. Deviating the input
frequency produces an output characteristic given by:

TL/H/9127 -7

FIGURE 9. Balanced Multiplier Circuit
phase or frequency detector if Vs(t) is limited to remove
amplitude information and  is centered at 90 degrees,
where cos produces the largest change in output for a
given change in phase.
Thus a vital part of setting up the detector will be to obtain
the correct relative phase for the type of demodulation desired.

Reference limiter
The purpose of the reference limiter is to create the reference signal required for product detection by stripping AM
modulation off the input signal. This should not be confused
with the limiter required in an FM system, which is in the
main signal path. FM limiting would be performed by locking
the IF amplifier at maximum gain as previously described, in
which case the reference limiter becomes redundant.
A Single differential limiter stage is provided between Pin 10
and the reference port at Pins 5 and 6. Pin lOis internally
biased from a 5.1V source through a 3.3 KO resistor; the
detector input Pin 9 is biased from the same source through
5 KO. By sharing a common bias point Pins 9 and 10 can be
directly shorted together when fed from the same signal,
thus saving a coupling capacitor. Alternatively, Pins 9 and
10 may be fed separately allowing phase and/or amplitude
differences to be introduced.

V3 = Vpk[COS(90 ± .10»
where Vpk is the theoretical peak output level set by the IF
Pin 11 load impedance, and .10 is the combined phase
swing produced by the tank and detector. For the Figure 11
circuit, Vpk = 6V and .1 0 "" 5 degrees/MHz, yielding an
output swing of ± 0.5 V/MHz.

The reference limiter output is a differential signal across
the reference port Pins 5 and 6. Pins 5 and 6 are internally
biased at 4.6V and have a 1 KO differential impedance.
Limiting begins with 20 mVrms at Pin 10 and heavy limiting
occurs above 100 mVrms input. The maximum limited output voltage is 350 mVrms.

12V

Detector Phasing
As we have seen, the relative phase between the detector
and reference inputs of the multiplier determines the
LM1211 demodulation characteristic. The detector input
phase is known since it connects directly to Pin 9. However,
the reference phase depends on several factors: The external components at Pins 10, 5, and 6, the phase shift through
the reference limiter, and lastly the setting of the detector
phase adjust control at Pin 7. The general approach for

TL/H/9127-8

FIGURE 10. Detector Input Phasing Network
2·13

iii:
.....
N
.....
.....

~ r---------------------------------------------------------------------~

C'\I

.-

::E
-'

Detector (Continued)
in Figure 12. The nominal 0 carrier (no input signal) output
voltage is OV, and a negative supply is required as a return
point for the external load resistor R3. The output may be
biased at up to 5 mA in order to maintain the (-) slew rate
into capacitive loads.
The 0 carrier output voltage is adjusted by the control voltage on a potentiometer at Pin 4. The center of the Pin 4
range is % supply with an adjustment sensitivity of approximately 0.1 VIV. Thus on a 12V supply up to ± 0.6V part-topart output variation can be trimmed out. The Pin 3 output is
capable of swinging up to ±4V; however, in certain AM detector applications the output will always remain above OV.
In these cases it may be possible to omit the negative supply and return the Pin 3 load resistor directly to ground. This
will result in some degradation in linearity at low output voltages which can be minimized by pre-biasing the 0 carrier
level high (V4 = 12V).

Phase Adjust Control
Once the external components have been selected for the
correct nominal phasing, the detector phase adjust is used
to perform the final set-up by monitoring the detector output
either for maximum output in the case of AM detection or for
OV average level for FM detection. The phase adjust control
Pin 7 is externally biased via a potentiometer and resistor
from 12V and requires a 2V to 6V minimum range at Pin 7.
The amount of phase lead or lag added to the reference
path as a function of V7 is given in Agure 5. For example, at
70 MHz a cumulative phase error of ± 50 degrees could be
compensated for by the phase adjust control.
While the previously cited -0.25 degreesl"C detection
phase temperature dependence is not noticeable in AM detection applications, it can cause the average DC level of
the FM detector output to drift. This can be reduced by using the phase adjust control in a feedback loop as shown in
FlfJure 11. Finally, it should be re-emphasized that the Pin 7
adjustment is intended as a trim rather than a substitute for
correct detector phasing.

The output amplifier frequency response is shown in Figure
6. The output exhibits a linear phase response of approximately -5.5 degrees/MHz out to 30 MHz. The first 70 MHz
carrier harmonic is approximately -46 dB and the second
harmonic -40 dB referenced to a 3V peak output.

Detector Output
The LM1211 output amplifier has an NPN emitter follower
driving Pin 3 through a 500 damping resistor as shown
o.oOluF

12Y

12Y
13K

11
12V'o--....---~-H

10

12

33K
10K

INPUT~I~luF

L;-te:,

82

12Y

4

o.OluF

1SK

O.ooluF 82
17

T1 : Communication Assoc,.tts
·000801
18

OUTPUT

D.C.
ADJUST

1----..:::---+<> OUTPUT

19

o

lK

R3
-5V
TL/H/9127-10

FIGURE 12. Detector Output Amplifier
-5V
TUH/9127-9

ALIGNMENT SEQUENCE:
1. With no input, adlust Roc for V3 - OV.
2. Apply Vin ;;, 10 mVrms, Fa - 70 MHz ±5 MHz Dev, Fm - 100 kHz;
Tune Quadrature coil for best outputlinearily.
3. Adjust RpH for output DC centering.

FIGURE 11.70 MHz FM Detector Application

2-14

Detector (Continued)
cause of the large ratio of charge to discharge current, the
LM1211 AGC has inherently faster recovery from a step
increase in signal than from a decrease. The overall speed
is inversely proportional to the AGC filter capacitor, with
0.05 ,...F being a practical lower limit for 120 = 1 mAo It is
important to use a quality (low Rs) capacitor at Pin 19 to
prevent AGC oscillation.
The AGC detector can be used at lower charge/discharge
ratios by reducing 120 which has a direct effect on the
charge current but only a second order effect on the discharge current. For 120 = 100 ,...A a 15:1 ratio is produced
and a 0.Q1 ,...F minimum capaCitor can be used. As the
charge/discharge ratiO is reduced, peak detection no longer
occurs and gating of Pin 20 may be necessary. This requires
an external gate pulse generator to tum on the Pin 20 bias
current only during the time the detector output is to be
sampled. In between gate pulses the Pin 19 output will be
tri-stated and the filter capacitor will hold the previous voltage until the next gate pulse. Permanently grounding Pin 20
turns off the AGC comparator, allowing an external AGC
signal at Pin 19 to control the IF amplifier gain.

AGC Comparator
An AGC comparator is provided for use in AM systems. The
(+ ) input is internally connected to the detector output Pin 3
while the (-) input is biased from an external resistive divider at AGC threshold Pin 1. An output current charges and
discharges the AGC filter capacitor at Pin 19 to control the
IF amplifier gain. The comparator is biased by a current into
bias/gate Pin 20. Internally, Pin 20 has a diode in series with
1 KO to ground so that the current level from an external
resistor R20 to 12V is given by:
120 _
11.3
- R20 + 1000
Whenever the detector output exceeds the AGC threshold,
a current equal to the Pin 20 bias current is delivered to Pin
19 to charge the AGC filter capaCitor. When the detector
output is below the AGC threshold, approximately 11 ,...A
discharge current flows into Pin 19. Thus the charge to discharge current ratio at Pin 19 is given by 120/11 ,...A, or 90:1
for 120 = 1 mA. This large ratio creates a peak-detecting
action in which the AGC loop holds the detector (+ ) output
peaks at the AGC threshold voltage, typically 1-3V. Be-

IF

PHASE
ADJUST

•
TL/H/9127-11

Printed Circuit Layout (component side)

2-15

!

~ ~National

.... ~ Semiconductor

!

~ LM 1596/LM 1496 Balanced Modulator-Demodulator
General Description

Features

The LM1596/LM1496 are doubled balanced modulator-demodulators which produqe an output voltage proportional to
the product of an input (signal) voltage and a switching (carrier) .signal. Typical applications include suppressed carrier
modulation, amplitude modulation, synchronous detection,
FM or PM detection, broadband frequenqy doubling and
chopping.

• Excellent carrier suppression
65 dB typical at 0.5 MHz
50 dB typical at 10 MHz
• Adjustable gain and signal handling
• Fully balanced inputs and outputs
• Low offset and drift
• Wide frequenqy response up to 100 MHz

The LM1596 is specified for operation over the -55·C to
+ 125·C military temperature range. The LM1496 is specified for operation over the O·C to + 700C temperature range.

Schematic and Connection Diagrams
Metal Can Package

V-

GAIN ADJUST

-CARRIER
INPUT

GAIN ADJUST

+CARRIER
INPUT

8(10)

-t---+--.....

CARRIERo-7~(8~}

-+____+_--'

INPUlo-..;..;._....._ _

4{4}
SIGNAL
INPUT

+

1(1)

t---.--.o GAIN
t-----+-~;.:..o ADJUST

BIAS

.~5(5~}~~-+~____~
BIAS",

TUH/7BB7-2

Top View
Note: Pin lOis connected electrically to the
case through the device substrate.

500

V-

500

Order Number LM1496H or LM1596H
See NS Package Number HOeC

10{14}

Dual-In-Llne and Small Outline Packages

TLlHI7BB7-1

Numbers in parentheses show DIP connections.

GAIN ADJUST
-SIGNAL IN

BIAS
+OUTPUT

3
4

12

5
6

10

7

8

-OUTPUT

11
-CARRIER INPUT

9

+CARRIER INPUT
TL/HI7887-3

Order Number LM1496M or LM1496N
See NS Package Number M14A or N14A

2-16

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Internal Power Dissipation (Note 1)
500mW
Applied Voltage (Note 2)
Differential Input Signal (V7 - Va)
Differential Input Signal (V4 - V1)

Soldering Information

30V
±5.0V

±(5+lsRo)V
Input Signal (V2 - V1, Va - V4)
5.0V
Bias Current (15)
12mA
Operating Temperature Range LM1596 - 55'C to + 125'C
LM1496
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C

Electrical Characteristics (TA =

• Dual·ln·Line Package
Soldering (10 seconds)

260'C

• Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215'C
220'C

See AN·450 "Surface Mounting Methods and their effects
on Product Reliability" for other methods of soldering sur·
face mount devices.

25'C, unless otherwise specified, see test circuit)

Parameter

LM1596

Conditions

LM1496

Min Typ Max Min Typ
Carrier Feedthrough

Carrier Suppression

Transadmittance Bandwidth

Vc = 60 mVrms sine wave
fc = 1.0 kHz, offset adjusted
Vc = 60 mVrms sine wave
fc = 10kHz, offset adjusted
Vc = 300 mVpp square wave
fc = 1.0 kHz, offset adjusted
Vc = 300 mVpp square wave
fc = 1.0 kHz, not offset adjusted
fs
fc
fs
1c

=
=
=
=

10 kHz, 300 mVrms
500 kHz, 60 mVrms sine wave offset adjusted
10 kHz, 300 mVrms
10 MHz, 60 mVrrns sine wave offset adjusted

50

RL = 500
Carrier Input Port, Vc = 60 mVrrns sine wave
1s = 1.0 kHz, 300 mVrrns sine wave
Signal Input Port, Vs = 300 mVrrns sine wave
V7 - Va = 0.5Vdc

Units

Max

40

40

",Vrms

140

140

",Vrms

0.04

0.2

0.04

0.2

mVrms

20

100

20

150

mVrms

50

65

dB

50

50

dB

300

300

MHz

80

80

MHz

3.5

VIV

65

Voltage Gain, Signal Channel

Vs = 100mVrms,f= 1.0 kHz
V7 - Va = 0.5 Vdc

Input Resistance, Signal Port

f = 5.0 MHz
V7 - Va = 0.5Vdc

200

200

kO

Input Capacitance, Signal Port

1 = 5.0 MHz
V7 - Va = 0.5Vdc

2.0

2.0

pF

Single Ended Output Resistance f = 10MHz

40

40

kO

Single Ended Output
CapaCitance

f = 10MHz

5.0

5.0

pF

Input Bias Current

(11 + 14)/2

12

25

12

30

",A

Input Bias Current

(17 + la)/2

12

25

12

30

",A

,..A
,..A

2.5

3.5

2.5

Input Offset Current

(11 -14)

0.7

5.0

0.7

5.0

Input Offset Current

(17 -Ia)

0.7

5.0

5.0

5.0

Average Temperature
Coefficient 01 Input
Offset Current

(-55'C < TA < +125'C)
(O'C < TA < +70'C)

2.0

nArC
nAI'C

2.0

Output Offset Current

(16 -19)

14

Average Temperature
Coefficient of Output
Offset Current

(-55'C < TA < + 125'C)
(O'C < TA < +70'C)

90

50

14
90

2·17

60

",A
nAl'C
nAl'C

•

..,....

CD

en

~
......

Electrical Characteristics (TA = 25°C, unless otherwise specified; see test cirCuit) (Continued)

....

..J

LM1596

Conditions

Parameter

CD

en
an
::IE

Min

Typ

= 1.0 kHz.

Signal Port Common Mode
Input Voltage Range

fs

Signal Port Common Mode
Rejection Ratio

V7 - Va

LM1496
Max

Min

Units

Max

Typ

5.0

5.0

Vp•p

-85

-85

dB

Common Mode Quiescent
Output Voltage

8.0

8.0

Vdc

Differential Output Swing
Capability

8.0

8.0

Vp•p

= 0.5Vdc

+ I)

Positive Supply Current

(16

Negative Supply Current

(110)

Power Dissipation

2.0

3.0

2.0

3.0

rnA

3.0

4.0

3.0

4.0

rnA

33

Not. I: LMI596 rating applies to case temperatures to
temperatures to + 70'C.

33

mW
+ 125'C; derate linearly at 6.5 mW/'C for ambient temperature above 75'C. LMI496 rating applies to case

Note 2: Voltage applied between pins 6-7,8·1,9·7,9-8,7-4,7·1,8·4,6·8,2·5,3·5.
Not. 3: Refer to re101596. drawing for apecificalions of military LMI596H versions.

Typical Performance Characteristics
Carrier Suppression vs
Carrier Input Level

carrier Suppression vs
Frequency

carrier Feedthrough vs
Frequency
10

10

10

20

20

30

30

~-~

-40

I"'r-..

50

60
70

r-. ....

~

f.=10MHz

r-

::.

o.os 0.1

Q.5 1.0

60
70

300

-400

300

CARRIER INPUT LEVEL (mVnno)

I

I
I
I
1.6
- f- I~ I~PUT~ sm\ ma 1= a

.,

0.4

o
o

V

!

o.a

11111111

3 mV

"I;

SIGNAL PORT

..

~11,l!:!Nri·

mV

,..

~
~
50

1.0

l'

0.&

",

50

0.4

SIGIW. PORT
11tIHS.\OM1TTAHC£

lour

~...J..J.L.LIIIL-I-.LI.LWlL.....L..Ju.

o.os 0.1

Q.5 1.0

5.0 10

CARRIER FREQUENCY (MHz)

Sideband and Signal Port
Transsdmlttances vs
Frequency

w

o.a

0.1

0.01

5.0 10

CARRIER FREQUEHCY (MHz)

Sideband Output vs
Carrier Levels

1.2

3fc

1A

1-I

50

i-'" -r:roOkHz

200

100

I

-40

!'~ ~

o

,.

I

Signal-Port Frequency
Response

;;;

-

Wl.::;:l:=o~1

20 mV
loomV

I
100

150

CARRIER LEVEL (mVrms)

200

o

0.1

Wl'lour(W:H
SlJEllAND) VOUT=O
v" (SIGNAL)
1.0

10

100

CARRIER FEQUEHCY (MHz)

Re

-30
1000

A.= "-+2

0.01

0.1

..

HlIIIf-+ftHIIII-+f
1.0

10

100

FREQUENCY (MHz)

Tl/H/7887-5

2-18

ri!:
.....

Typical Application and Test Circuit

CII
CD

.....
r-

Suppressed Carrier Modulator

G)

lk

i!:
.....

+12V

.j:oo

O.I}1f

CD

51
lk

I

CARRIER~
INPUT Vc O.I}1f

G)

51

-

3.9k

6(6)

+Vo

9(12)

-Yo

8(10)
LM1596

Vs

MODULATlON
INPUT

3.9k

2(2)
7(8)

1(1)

4(4)
10k

CARRIER
NULL

51

51

t

... I

l

0.47 }If

6.8k
Numbers in parentheses show DIP connections.

~--~o--

-8 V

TL/HI7887-4

Note: 51 is closed for "adjusted" measurements.

SSB Product Detector
+8 VDC
lk

CARRIER INPUTo-_ _......_ _ _ _-I
300mVrms

2(2)
7(8)

3.9k

3(3)
6(6)

51
8(10)

-------f

SSB SIGNAL o-ff-.....
INPUT

Ltot1596

1 }If

1(1)

9(12) 1----+..IoIIIIr-......-tL,.. DEMODULATED
~AfOUTPUT

4(4)
55)

I

0.005I 0.005

}If

}IF

lk
lk

Uk

lk

Numbers in parentheses show DIP connections.

-8 Vd.
TLlH17887-6

This figure showe the LM1596 used .. a single sldebend (SSB) suppressed carrier demodulator (product detector). The carrier signal is applied to the carrier input
port with sufficient amplitude for switching operetion. A carrier input level of 300 mVrms Is optimum. The composite SSB signal is spplied to the signal input port
with an amplitude of 5.0 to 500 mVrms. All output signal components except the desired demodulated audio are filtered out, so that an offset adjustment is not
required. This circuit may also be used .. an AM detector by applying composite and carrier signals in the same manner .. described for product detector

operation.

2·19

fJI

!.::E
....

Typical Applications (Continued)
Broadband Frequency Doubler

i.-

+12 Vdc

lk

::E

....

lk
2(2)

..........IVVv---I 7(8)

3(3)

-+-0 ¥o coa2.

8(6) 1-.....

HI--...Jt,f.tIY-........ 8(10)

'0 coalilt 0-....-..-4....-

...---11(1)

9(12) t---t-O

-Ayeo c0l2.

, - - i -.....-I4(4)

Numbers in parentheses show DIP connections.

-8VOC

TLlH17887 -7

The frequency doubler clrcuH shown will double low.levelsignels with low distortion. The value of C should be chosen for low reactance at the operating frequency.
Signal level at the carrier input must be less than 25 mV peak to maintain operation in the linear region of the switching differential amplHier. Levels to 50 mV peak
may be used wHh some distortion of the output waveform. If a larger input Signal is avall8ble a resistive divider may be used at the carrier input, with full signal
applied to the signal input.

2·20 .

~National

~ Semiconductor

LM 1865 Advanced FM IF System
General Description

• Meter output proportional to signal level

Reduced external component cost, improved performance,
and additonal functions are key features to the LM1865 FM
IF system. The LM1865 is designed for use in electronically
tuned radio applications. It contains both deviation and signal level stop circuitry in addition to an open-collector stop
output. The LM1865 generates a reverse AGe voltage (ie:
decreaSing AGe voltage with increasing signal).

• Stop detector with open-collector output

Features

• Dual threshold AGe eliminates need for local/distance
switch and offers improved immunity from third order intermodulation products due to tuner overload

• On-chip buffer to provide gain and terminate two ceramic filters
• Low distortion 0.1 % typical with a single tuned quadrature coil for 100% modulation.
• Broad off frequency distortion characteristic

• Adjustable signal level mute/stop threshold, controlled
either by ultrasonic noise in the recovered audio or by
the meter output
• Adjustable deviation mute/stop threshold
• Separate time constants for signal level and deviation
mute/stop

• User control of both AGe thresholds
• Excellent signal to noise ratio, AM rejection and system
limiting sensitivity

• Low THD at minimum AFT offset

Block Diagram
y+

AFT OUT AND
D£YIAnoN MUTE/STOP

WINDOW ADJUST

W1DEBAND---1'
AGe IN

I

I
I
I
I

I

ITD~!:!!! ___

L__
13

NARROW
BAND
THRESHOLD
AIIIIIIT

J

11

.-I

Order Number LM1885M
orLM1885N
See NS Package Number
M20BorN20A
FIGURE 1

2-21

TL/H/7509-1

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Pin 17

Soldering Information
Dual-In-Une Package
Soldering (10 seconds)
Small Outline Package
VapOr Phase (60 seconds)
Infrared (15 seconds)

16V

Package Dissipation (Note 1)

2.0W

Storage Temperature Range

- 55·C to

Operating Temperature Range

+ 1500C
+ 85·C

215·C
2200C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering sur·
face mount devices.

- 20·C to

Max Voltage on Pin 16 (Stop Output)

2600C

16V

Electrical Characteristics
Test Circuit, T A

=

25·C, V+

= 12V; S1

in position 2; S2 in pOSition 1; and S3 in position 2 unless indicated otherwise

I

Parameter

I

Conditions

Min

I

Typ

I

Max

I

Units

STATIC CHARACTERISTICS
Supply Current

33

Pin 9, Regulator Voltage

45

5.7

Operating Voltage Range

(See Note 2)

7.3

Pin 18, Output Leakage Current

Pin 20 Open, V,F

Pin 16, Stop Low Output Voltage

SI in Position 1, S2 in Position 3

Pin 16, Stop High Output Leakage Current

S2 in Position 2, V14

=

0, S3 in Position 1

=

V
16

0.1

V9

mA

V
p.A

0.3

V

0.1

p.A

4.7

k{}

Pin I, Buffer Input Resistance

Measured at DC

350

{}

Pin 3, Buffer Output Resistance

Measured at DC

350

{}

Pin 20, Wide Band Input ReSistance

Measured at DC

2

{}

1

k{}

Pin 15, AudiO Output Resistance

Pin 8, Meter Output Resistance .
DYNAMIC CHARACTERISTICS fMOD

=

400 Hz, fo

=

10.7 MHz, Deviation

-3 dB Umiting Sensitivity

IF Only (See Note 3)

Buffer Voltage Gain

Y,N Pin 1

Recovered Audio

V,F

=

=

± 75 kHz

10 mVrmsat 10.7 MHz

= 10 mVrms, V14 = V9
V,F = 10 mVrms, V14 = V9 (See Note 4)
V14 = V9
V,F = 1 mV, 30% AM Mod

Signal·to-Noise
AM Rejection

= 10 mV, 30% AM Mod
V,F = 10mV
V,F = 10mV, TuneuntilV14 = V9
V,F

Minimum Total Harmonic Distortion
THO at Frequency where V14
(Zero AFT Offset)

= V9

THO ± 10kHz from Frequency where V14

=

V9

60

120

19

22

25

dB

275

320

470

mVrms

70

84

dB

50
50

60

dB
dB

60

p.Vrms

0.1

0.35

%

0.1

0.45

%

V,F = 10mV

0.15

%

AFT Offset Frequency for Low
Stop Output at Pin 16

V,F = 10 mV, S2 in PositiOn 3, fMOD = 0
Offset = (Frequency for Pin 16 Low) (Frequency Ylhere V14 = V9)

±50

kHz

Ultrasonic Mute/Stop Level Threshold

V14 = V9, SI in Position 3 (See Note 5)
V,F = 10mV
fMOD = 100 kHz
S2 in Position 3
Low
Amount of Deviation where V16 -

60

kHz

2-22

....

ill:
....
CD

Electrical Characteristics Test Circuit, TA = 25'C, V+ = 12V; Sl in position 2; S2 in position 1; and S3 in
position 2 unless indicated otherwise (Continued)

I

Parameter

en
CI'I

IMlnlTyplMaxl Units

Conditions

DYNAMIC CHARACTERISTICS IMOD = 400 Hz, 10 = 10.7 MHz, Deviation = ± 75 kHz (Continued)
Pin 13 Mute/Stop Threshold Voltage

V14 = V9, Sl in Position 4
S2 in Position 3
V13whereV16 Low

220

mV

Amount 01 Muting (LM1965 Only)

S2 in Position 4, Sl in Position 1, VIF = 10 mV

66

dB

Amount of Muting with Pin 13 and
Pin 16 Grounded

S1 in Position 1
V14, = V9, VIF = 10 mV

0

dB

Narrow Band AGe Threshold

Increase IF Input until I AGC = 0.1 mA
Pin 20 = 30 mVrms

Wide Band AGe Threshold

VIF = 100 mVrms
Increase Signal to Pin 20 until IAGC = 0.1 mA

Pin 18, Low Output Voltage
(LM1865 and LM1965 only)

100

210

300

p.Vrms

5

12

22

mVrms

VIN Pin 20 = 100 mY, VIF = 100 mVrms

0.2

0.5

V

Pin 18, High Output Voltage (LM2065 only)

VIN Pin 20 = 100 mY, VIF = 100 mVrms, (See Note 6)

11.7

V

Pin 8, Meter Output Voltage

VIF = 10 p.V
VIF = 300 p.V
VIF = 3mV

0.1
1.1
2.6

V
V
V

Note 1: Mx1ve TA = 25'C derate based on TJ(max) = 150'C and 9JA = 60'C/W.
Note 2: All data sheet speciflcations are for V + = t 2V may change slighHy with supply.
Note 3: When the IF Is preceded by 22 dB gain In the buffer, excellent system sensitivity is achieved.
Note 4: Measured with a notch at 60 Hz and 20 Hz to 100 kHz bandwidth.
Note 5: FM modulate RF source with a tOO kHz audio signal and find what modulation level, expressed as kHz deviation, results in V16 -+ 12V.

Test Circuit

.... -!~

,ir~ cu: "

11k

~

~,~

12V

p:+

2
1

b

12V
SUPrLY
CURRENT /
METER

l:0.~'F
WlOE

BUFFER
IllPUT

BUFFER
fIIIOUNO

BU_
DECOUPlE

AGe

17
V'

OUT

BUFFER
OUT

IF
DECOUPLE

1-

04

16
STOP OUT

IF
IN

SO@ 10.7 MHz
TDK Electronics
TP041 0-180K or equivalent
Qu>70 @ 10.7 MHz, L to
,
resonatew/82 pF @ 10.7 MHz
14' ...F TOKO KAC-K2318HM or
equivalent

O

Comments
AC coupling for wide band AGC input
Buffer and AGC supply decoupling
IF decoupling capacitors
Meter decoupling capacitor
AC coupling for IF output
Regulator decoupling capacitor, affects SIN floor
Level mute/stop time constant
AFT decoupling, affects stop time
Disables noise mute/stop
AC coupling for noise mute/stop threshold adjust
Supply decoupling
AGC output decoupling capacitor
Wide band AGC threshold adjust
Gain set and bias for IF; R2 + R3 = 330!} to terminate ceramic filter
Sets full-scale on meter
Deviation mute/stop window adjustment
Mute/stop filter, affects stop time
Level mute/stop threshold adjustment
Level mute/stop threshold adjustment
Noise mute/stop threshold adjustment, decrease resistor for lower
SIN at threshold, for optimum performance over temp. and gain variation, set this resistor value so that the signal level mute/ stop threshold
occurs in the radio at 4SdB SIN (±3 dB) in mono.
Load for open-collector stop output
AGC o·utput load resistor for open-collector output
Sets Q of quadrature coil affecting THD, SIN and recovered audio
Optimises minimum THD
Sets signal swing across quadrature coil, High Q is important to minimize effect variation of Q has on both minimum THD and AFT offset.
10.7 MHz quadrature coil: QUL > 70

TL/H17509-5

CF1,CF2

Murata SFE1 o. 7ML or equivalent

10.7 MHz ceramic resonators provide selectivity; good group delay
characteristics important for low THD of system
2-2S

Typical Application
LAYOUT CONSIDERATIONS
Although the pinout of the LM1865 has been chosen to minimize layout problems, some care is required to insure stability. The ground terminal on CF1 should return to both

the input Signal ground and the buffer ground, pin 19. The
ground terminal on CF2 should return to the ground side of
C4. The quadrature coli T1 and inductor L1 should be separated from the input circuitry as far as possible.

PC Layout (Component Side)

TLlHI7509-6

PERFORMANCE CHARACTERISTICS OF TYPICAL
APPLICATION WITH TUNER
The following data was taken using the typical application
circuit in conjunction with an FM tuner with 43 dB of gain, a
Meter Output and
Signal-to-Nolae
va Tuner Input

I

10

AUDIO".,

,......

~i-l:
'lr i'-20 ~

III it -30 3V
40
-50 2V

;1-

~
I~DIJS'

\

;-1

EI- 50

h\II
l!

70 IV
;-80

-80

/

0.1

I

\ I
I

/
1

"/'

/
.-

-

i.-

HOIJ, IF .ARROW 8ANII
LOOP IS ACTUATED

....... /::O:R':~LD
./ ~

NUISEldl,

::T~~:~HDLD

m~~ID~~

TUNER INPUT u.VI

Ii
1_

Total Harmonic Dlatortlon va
Tuner Input
100

~-10

"Ii -20
Ii! -30

.1-40

ai-

50

.11=:
'II!

II!

5.5 dB noise figure, and 30 dB of AGC range. The tuner was
driven from a 500 source. 75 ","S of de-emphasis was used
on the audio output, pin 15. The 0 dB reference is for ± 75
kHz deviation at 400 Hz modulation.

AUDIO

Ii!
1_

10
0

!

l/

IMoD=400Hz

X

"Tito +NOISE
N~SE

-80
-80

~lm~~ID_~

TUNER INPUT (~V)

A 010

-10
20
-38

111- IL .\
.1-40 \\
!!.f
Iii

\\
\\

AM Rejection va Tuner
Input

Ii

EI

-50
-50
-70

\1/

-80

II!

'"

AM (30% MOO)

1\
IV

II \

~OISE
I

-80
0.1

1

10 100 lk 10k lOOk l000k

TUNER INPUT (~V)
TLlHI7509-7

-3 dB IImHing = 0.9,.V
30 dB quieting = 1.4,.V
Level stop/mute threshold

= 1.4 ,.V
= ± 45 kHz

Deviation mute window (- 3 dB)

2-26

,-----------------------------------------------------------------------------, r
!Ii:
.....
Application Notes
sponds to a weaker signal at the antenna of the radio. In
choosing the correct value for R9 it is important to make
sure that recovered audio below 75 kHz is not sufficient to
cause mute/stop action. This is because stereo and SCA
information are contained in the audio signal up to 75 kHz.
Also note that the ultrasonic mute/stop circuit will not operate properly unless a tuner is connected to the IF. This is
because, at low signal levels, the noise at the tuner output
dominates any noise sources in the IC. Consequently, driving the IC directly with a 50n generator is much less noisy
than driving the IC with a tuner and therefore not realistic.
The RC filter on pin 12 not only filters out noise from the
comparator output but controls the "feel" when manually
tuning. For example, a very long time constant will cause
the mute to remain active if you rapidly tune through valid
strong stations and will only release the mute if you slowly
tune to a valid station. Conversely, a short time constant will
allow the mute to kick in and out as one tunes rapidly
through valid stations.
The advantage in using the noise mute/stop approach versus the meter driven approach is that the point at which
mute/stop action occurs is directly related to the signal-tonoise ratio in the recovered audio. Furthermore, the mute/
stop threshold is not subject to production and temperature
variations in the meter output voltage at low signal levels,
and thus might be able to be set without a production adjustment of the radio. The noise mu1e/ stop threshold is very
insensitive to temperature and gain variations. Proper operation of this circuit requires that the signal level mute/stop
threshold be set at a signal level that achieves 45 dB SIN
(± 3 dB) in mono. in a radio. In an electronically tuned radio,
the signal level stop threshold can be set to a much larger
level by gain reducing the tuner (ie. pulling the AGC line) in
scan mode and then releasing the AGC once the radio
stops on a station. In an environment where temperature
variations are minimal and manual adjustment of the signal
level mute/stop threshold is desired, then the meter driven
approach is the best alternative.

ADJUSTABLE MUTE/STOP THRESHOLD
The threshold adjustments for the mute and stop functions
are controlled by the same pins. Thus, the term mute/stop
will be used to designate either function.
The adjustable mute/stop threshold in the LM1865 allows
for user programming of the signal level at which muting or
stop indication takes place. The adjustment can be made in
two mutually exclusive ways. The first way is to take a voltage divider from the meter output (pin 8) to the off channel
mute input (pin 13). When the voltage at pin 13 falls below
0.22V, an internal comparator is tripped causing muted or
causing the stop output to go low. Adjustment of the voltage
divider ratio changes the signal level at which this happens.
The second method of mute/stop detection as a function of
signal level is to use the presence of ultrasonic noise in the
recovered audio to trip the internal comparator. As the signal level at the antenna of the radio drops, the amount of
noise in the recovered audio, both audible and ultrasonic,
increases.
The recovered audio is internally coupled through a high
pass filter to pin 13 which is internally biased above the
comparator trip pOint. Large negative-going noise spikes will
drive pin 13 below the comparator trip pOint and cause
mute/stop action. A simplified circuit is shown in Figure 4.
Since the input to the comparator is noise, the output of the
comparator is noise. Consequently, a mu1e/stop filter on pin
12 is required to convert output noise spikes to an average
DC value. This filter is not necessary if pin 13 is driven from
the meter.
Adjustment of the mute/stop threshold in the noise mode is
accomplished by adjusting the pole of the high pass filter
coupled to the comparator input. This is done with a series
capacitor/resistor combination, R9 C11, from pin 13 to
ground. As the pole is moved higher in frequency (i.e., R9
gets smaller) more ultrasonic noise is required in the recovered audio in order to initiate mute/stop action. This corre-

g:
CII

fII
I
I

50k

+

:t;

O.35V

'HIGH FOR MUTE OR I
STOP OUTPUT LOW :

I

I

L_____ 13------- 12-- R
;2;-.J

mml~F

TLlHI7509-8

FIGURE 4. Simplified Level Mute/Stop Circuit

2-27

Application Notes (Continued)
Signal Level Stop Using the Meter Output, Pin 8
As mentioned previously, R6 C8 is not necessary when the
meter output is used to drive pin 13. Consequently, this time
constant is not a factor in determining the stop time. However, the speed at which the meter voltage can move may
become important in this regard. This speed is a function of
the reSistive load on pin 8 and filter capacitance, C5.

STOP TIME
An electronically tuned radio (ETR) pauses at fixed intervals
across the FM band and awaits the stop indication from the
LM1865. If within a predetermined period of time, no stop
indication is forthcoming, the controller circuit concludes
that there is no valid station at that frequency and will tune
to the next interval.. There are several time constants that
can affect the amount of time it takes the LM1865 to output
a valid stop indication on pin 16. In this section each time
constant will be discussed.

AGC Time Constant
In tuning from a strong station to a weaker station above the
level stop threshold, the AGC voltage will move in order to
try to maintain a constant tuner output. The AGC voltage
must move sufficiently fast so that the tuner is gain increased to the point that the level stop indicates a valid
station. This time constant is controlled by Rll and C13.

Deviation Stop Time Constant
An offset voltage is generated by the AFT if the LM1865 is
tuned to either side of a station. Since deviation stop detection in the LM 1865 is detected by the voitage at pin 14, it is
important that this voltage move fast enough to make the
deviation stop decision within the time allowed by the controller. The speed at which the voltage at pin 14 moves is
governed by the RC time constant, R5 C9. rhis time constant must be chosen long enough to remove recovered
audio from pin 14 and short enough to allow for reasonable
stop detection time.
.

DISTORTION COMPENSATION CIRCUIT
The quadrature detector of the LM1865 has been designed
with a special circuit that compensates for distortion generated by the non-linear phase characteristic of the quadrature coil. This circuit not only has the effect of reducing distortion, but also desensitizes the distortion as a function of
tuning characteristic. As a result, low distortion is achieved
with a single tuned quad coil without the need for a double
tuned coil which is costly and difficult to adjust on a production basis. The lower distortion has been achieved without
any degradation of the noise floor of the audio output. Futhermore, the compensation Circuit first-order cancels the effect of quadrature coil Q on distortion.
When measuring the total harmonic distortion (THO) of the
LM1865, it is imperative that a low distortion RF generator
be used. In the past it has been possible to cancel out distortion in the generator by adjustment of the quadrature coil.
This is because centering the quadrature coil at other than
the point of inflection on the S-curve introduces 2nd harmonic distortion which can cancel 2nd harmonic distortion
in the generator. Thus low THO numbers may have been
obtained wrongly. Large AFT offsets asymmetrical off tuning
characteristic, and less than minimum THO will be observed
if alignment of the quadrature coil is done with a high distortion RF generator.

Signal Level Stop Using Ultrasonic Noise Detection
As previously mentioned, the R6 C8 time constant on pin 12
is necessary to filter the noise spikes on the output of the
internal comparator in the LM1865. This time constant also
determines the level stop time. When the voltage at pin 12
is above a threshold voltage of about 0.6V, the stop output
is low. The maximum voltage at pin 12 is about 0.8V. The
level stop time is dominated by the amount of time it takes
the voltage at pin 12 to fall from 0.8V to 0.6V. The voltage at
pin 12 follows an exponential decay with RC time constant
given by R6 C8. For example if R6 = 25k and C6 = 2.2 IJoF
the stop time is given by
t = - (24k) (2.2 1JoF) i n ( 0.6)
0.8
which yields t = 15 ms. It should be noted that the 0.6V
threshold at pin 12 has a high temperature dependence and
can move as much as 100 mV in either direction.

Care must also be taken in choosing ceramic filters for the
LM1865. It is important to use filters with good group delay
characteristics and wide enough bandwidth to pass enough
FM sidebands to achieve low distortion.

2-28

Application Notes (Continued)
The LM1865 has been carefully designed to insure low AFT
offset current at the pOint of minimum THO. AFT offset current will cause a non-symmetric deviation mute/stop window about the point of minimum THO. No extemal AFT offset adjustment should be necessary with the LM1865. The
amount of resistance in series with the 18 pH quadrature
coil drive inductor, L 1, has a significant effect on the minimum THO. This series resistance is contributed not only by
R13 but also by the 0 of L 1. The 0 of L 1 should be as high
as possible (ie: 0>50) in order to avoid production problems with the 0 variation of L 1. Once R 13 has been optimized for minimum THO, adjustment on a radio by radio
basiS should be un-necessary.

With the LM1865 system, a low AGC threshold is achieved
whenever there are strong out-of-band signals that might
generate an interfering 1M3 product, and a high AGC threshold is achieved if there are no strong out-of-band signals.
The high AGC threshold allows the receiver to obtain its
best signal-to-noise performance when there is no possibility of an 1M3 product. The low AGC threshold allows for
weaker desired stations to be received without gain-reducing the tuner. It should be noted that when the AGC threshold is set low, there will be a signal-to-noise compromise,
but is assumed that it is more desirable to listen to a Slightly
noisy station than to listen to an undesired 1M3 product. The
simplified circuit diagram (Figure 5) of the AGC system
shows how the dual AGC thresholds are achieved.

DUAL THRESHOLD AGC
(AUTOMATIC LOCAL/DISTANCE SWITCH)

Vm = 1V corresponds to a fixed in-band signal level (defined as VNB) at the tuner output. VNB will be referred to as
the "narrow band threshold". VWB also corresponds to a
fixed tuner output which can either be an in-band or out-ofband signal. This fixed tuner output will be called the "wide
band threshold". Always VWB > VNB. R11 and C13 define
the AGC time constant. A reverse AGC system is shown.
This means that VAGe decreases to gain-reduce the tuner.
The LM1865 AGC output is an open-collector current
source capable of sinking at least 1 mAo

There is a well recognized need in the field for gain reducing
(AGCing) the front end (tuner) of an FM receiver. This gain
reduction is important in preventing overload of the front
end which might occur for large signal inputs. Overloading
the front end with two out-of-band signals, one channel
spacing apart' and one channel spacing from center frequency, or, two channel spacings apart and two channel
spacings from center frequency, will produce a third order
intermodulation product (1M3) which falls inband. This 1M3
product can completely block out a weaker desired station.
The AGC in the LM1865 has been specially designed to
deal with the problem of 1M3.
ANTENNA

•••
PIN 8

1V

METER OUTPUT

y+

I

I

HIGH OUTPUT

..._ _+,YAllt:oo..t()--o~ CLOSE SW2

;,;C13

PIN 18

til

HIBH OUTPUT
TO CLOSE SW1

°SWI

SW2

I

IAGe

'
TLlHI7509-9

FIGURE 5. Dual Threshold AGC
11 = GM1 Vm only if Vm > 1V
otherwise 11 = 0
Gm1. VWB = constants
IAGC = Gm2 Vo where Gm2 = 11/26 mV and
Vo > VWB otherwise IAGC = 0

2-29

Application Notes (Continued)
First examine what happens with a single in-band signal as
we vary the strength of this signal. Figures 6 and 7 illustrate
what happens at the tuner and AGe outputs.

In Figure 7 there is no AGe output until the tuner output
equals the wide band threshold. At this point both SW2 and
SW1 are closed and the AGe holds the tuner output in Rgure 6 relatively constant.
Another simple case to examine is that of the-single out-of~
band signal. Here there is no AGe output even if the signal
exceeds VWB. There is no output because the' ceramic filters prevent the out-of-band signal from getting to the input
of the IF. With no Signal at the IF input there is no meter
output and SW1 is open, which means No AGe.

TUNER OUTl'IIT
SLOI'E IS INVERSELY PROPORTIONAL
TO LOOP GAIN OF WlOE lAND AGC CIRCUIT

Figures 8 and 9 illustrate what happens at the tuner and
AGe outputs when the strength of an in-band signal is varIed in the presence of a strong out-of-band signal (I.e.,
greater than VWB) which is held constant at the tuner input.
For this example, the in-band signal at the tuner output will
be referred to as Ve (desired signal), and the out-of-band
signal as Vue (undesired ~ignal).
In Figure 9, we see that there is no AGe output until the
tuner output exceeds the narrow band threshold, VNB. At
this point Vm > 1V and SW1 closes. Further increase of the
desired signal at the tuner input results in an AGe current
that tries to hold the desired signal at the tuner output constant. This gain reduction of the tuner forces the undesired
signal at the tuner. output to fall. At the point that Vue reach.es the wide band threshold, no further gain reduction can
occur as Vo would fall below VWB (refer to Figure 5). At this
point, control of the AGe shifts from the meter output
(narrow band loop) to the out-of-band Signal (wide band
loop). Here Vue is held constant along with the AGe
TUNER OUTPUT

------,
'............

VB REACHES VWI

. -----n---'\",

"

IN-IIANO SIGNAL

(Yo)

,
'" OUT·OF BAND SIGNAL
(¥UB)

L-------~~---~------r_~---------~V6
'Ni
Ywi
(TUNER INPUT)

FIGURE 8
REVERSE Me OUTPUT

,+1----1".

~

____________

~

______

~

______

~~V6

(TUNER INPUT)
Prime Indicates referenced to tuner Input

FIGURE 9
2-30

TL/HI7S09-11

Application Notes (Continued)
voltage, while Vo is allowed to increase. Vo will increase
until it reaches the level of the wide band threshold at the
tuner output. When this occurs Vuo is no longer needed to
keep Va > VWB as Vo takes over the job. Thus Vuo will
drop as the amount of AGe increases, while Vo is held constant by the AGe.

NARROW BAND AGC THRESHOLD ADJUSTMENT
Both the narrow band and wide band AGe thresholds are
user adjustable. This allows the user to optimize the AGe
response to a given tuner. Referring to Figure 5, when the
meter output exceeds 1V a comparator closes SW1. A simplified circuit diagram of this comparator is shown in Figure
10.

When compared to the simple case of a single in-band signal, we see that because of the presence of a strong out-ofband signal, AGe action has occurred earlier. For the simple
case, AGe started when Vo ~ VWB. For the two signal case
above, AGe started when Vo ~ VNB. Thus, the LM1865
achieves an early AGe when there are strong adjacent
channels that might cause 1M3, and a later AGe when these
signals aren't present.

The 1K resistor in series with pin 8 allows for an upward
adjustment of the narrow band threshold. This is accomplished by externally loading pin 8 with a resistor. Figure 11
illustrates how this adjustment takes place.

For the range of signal levels that the tuner was gain-reduced and Vo < VWB there was loss in signal-to-noise in
the recovered audio as compared to the case where there
was no gain reduction in this interval. Note, however, thst
the tuner is not desensitized by the AGe to wesk desired
ststions below the nsrrow band threshold.

In general one chooses the narrow band threshold
based on what signal-to-noise compromise is considered
acceptable.

From Figure 11 it is apparent that loading the meter output
not only moves the narrow band threshold, but also decreases the meter output for a given input.

HIGH - SW1 CLOSED
LOW -SW1 OPEN
TL/H17509-12

FIGURE 10. Narrow Band Threshold Circuit

METER LOAD = 33k

•
:::--J==:::;...----......L.... vo TUNER

L.......

TL/HI7509-13

FIGURE 11. Affect of Meter Load on Narrow Band Threshold

2-31

Application Notes (Continued)
VUD2 = out-of-band signal 800 kHz from center frequency and 400 kHz away from VUD1. applied to tuner input.
In general. due to tuned circuits within the tuner. the tuner
gain is not constant with frequency. Thus. if the tuner is kept
fixed at one frequency while the input frequency is changed.
the output level will not remain constant. Figure 12 illustrates this.
It can be shown that for a given IMa. the combination of
VUD1 and VUD2 that produces the smallest rms sum at the
tuner output is given by the equations:

WIDE BAND AGe THRESHOLD ADJUSTMENT
There are a number of criteria that determine where the
wide band threshold should be set. If the threshold is set too
high. protection against IMa will be lost. If the threshold is
set too low. the front end. under certain input conditions.
may be needlessly gain-reduced. sacrificing signal-ta-noise
performance. Ideally. the wide band threshold should be set
to a level that will insure AGC operation whenever there are
out-of-band signals strong enough to generate an IMa product of sufficient magnitude to exceed the narrow band
threshold. Ideally. this level should be high enough to allow
for a single in-band desired station to AGC the tuner. only
after the maximum signal-to-noise has been achieved.

a

In order to insure that the wide band loop is activated whenever the IMa exceeds the narrow band threshold. VNB. determine the minimum signal levels for two out-of-band signals necessary to produce an IMa equal to VNB. Then. arrange for the wide band loop to be activated whenever the
tuner output exceeds the rms sum of these signals. There
are many combinations of two out-of-band signals that will
produce an IMa of a given level. However. there is only one
combination whose rms sum is a minimum at the tuner output. IMa at the tuner output is given according to the
equation:
IMa = aVUD1 2 VUD2 (assuming no gain reduction) (1)

A2IM a)'h
VUD1 = 1.12 ( A1

(2)

A12 IMa)'h
VUD2 = 0.794 ( - A22 a

(3)

Therefore. in order to guarantee that the AGC will be keyed
for an IMa = VNB we need only satisfy the condition:

vws';' vJB + [(A1)(1.12)

(~r:S)%]2 + [A2{0.794) (~:v:s) %]2(4)

where a = constant dependent on the tuner;
The right hand term of equation (4) defines an upper limit for
VWB called VWBUL. VWBUL is the rms sum of all the signals
at the tuner output for two out-of-band signals. VUD1 and
VUD2 [as expressed in equations (2) and (3)1. applied to the
tuner input.

VUD1 = out-of-band signal 400 kHz from center frequenCY. applied to tuner input;

TUNER GAIN

A

I

I
___ ...1I __ _

A2

I
I

I

:

I
I
- - - - - - - - - - - - - ' " - - - - ' - - - - ' - - - - - - - T U N E R INPUT FREQUENCY

10

10+

10+

400 kHz

880 kHz

Define A ~ tuner gain at center treciuency
A1

~

tuner gain at f 0

+ 400 kHz

A2

~

tuner gain at f 0

+ 800 kHz
FIGURE 12

2-32

TlIH/7509-14

Application Notes (Continued)
In order to make the calculation in equation (4), the constants a, A 1, A2 must first be determined. This is done by
the following procedure:

If the wide band threshold was set to VWBUL, then when a
single in-band station reached the level VWBUL at the tuner
output, AGC action would start to take place. For this reason it is hoped that VWBUL is above the level that will allow
for maximum signal-to-noise. If, however, this is not the
case, consideration might be given to improving the intermodulation performance of the tuner.

1. Connect together two RF generators and apply them to
the tuner input. Since the generators will terminate each
other, remove the 500 termination at the tuner input.
2. Connect a spectrum analyzer to the tuner output. Most
spectrum analyzers have 500 input impedances. To
make sure that this impedance does not load the tuner
output use a FET probe connected to the spectrum analyzer. The tuner output should be terminated with a ceramic filter.
3. Disconnect the AGC line to the tuner. Make sure that the
tuner is not gain-reduced.
4. Adjust the two RF generators for about 1 mV input and to
frequencies 400 kHz and 800 kHz away from center frequency (Figure 13).

The lower limit for VWB is the minimum tuner output that
achieves the best possible signal-to-noise ratio in the recovered audio. In general, it is desirable to set VWB closer to
the upper limit rather than the lower limit. This is done to
prevent AGC action within the narrow band loop except
when there is a possibility of an 1M3 greater than VNB.
The wide band threshold at the pin 20 input to the LM1865
is fixed at 12 mVrms. Generally speaking, if pin 20 were
driven directly from the tuner output. VWB would be too low.
Therefore, in general, pin 20 is not connected directly to the
tuner output. Instead the tuner output is attenuated and then
applied to pin 20. Increasing attenuation increases the wide
band threshold, VWB.
Pin 20 has an input impedance at 10.7 MHz that can be
modeled as a 5000 resistor in series with a 19 pF capacitor,
giving a total impedance of 9400 L - 58°. Thus an easy way
to attenuate the input to pin 20 is with the arrangement
shown in Figure 14.
Notice that pin 20 must be AC coupled to the tuner output
and that C1 is a bypass capacitor. R1 adjusts the amount of
attenuation to pin 20. The wide band threshold will roughly
increase by a factor of (R1 + 9400)/9400.

5. Note the three output levels in volts.
6. Knowing the tuner input levels for VUDl and VUD2 and
the resulting 1M3 just measured, "a" is calculated from
the formula:
a =

1M3
VUD1 2VUD2

(5)

where all levels are in volts rms. A typical value for "a"
might be 2 x 106.
7. A1 and A2 are calculated according to the following formulas
A1 =

V1
VINI
fa

A2 =

+ 400kHz
V2

VINI
fa

AGC CIRCUIT USED AS A CONVENTIONAL AGC
If for some reason the dual AGC thresholds are not desired,
it is easy to use the LM1865 as a more conventional
LM3189 type of AGC. This is accomplished by AC coupling
the pin 20 input after the ceramic filters rather than before
the filters. Thus, as with the LM3189, only in-band signals
will be able to activate the AGC.

(6)

(7)

+ 800kHz

330(1 OUTPUT

Y1

'- - - '
_

r

10 10+400 kHz 10+800 kHz

IMPEDANCE
/"

~ l.

CERAMIC FILTER

!r-

I~.

Tl/H/7509-16

10=10.7 MHz

FIGURE 14. Wide Band Threshold Adjustment

TUHI7509-15

FIGURE 13_ Spectrum Analyzer Display of Tuner Output

2-33

Simplified Diagram
I

II

iI

!i~n

J
•

• =

_----o.~~

..

•
'-+--+--1"'lH

Ii

;

2-34

.~
L

.------------------------------------------------------------------.~

iii:::
....

~National

Ii

~ Semiconductor

LM 1868 AM/FM Radio System
General Description

Features

The combination of the LM1868 and an FM tuner will provide all the necessary functions for a 0.5 watt AM/FM radio.
Included in the LM 1868 are the audio power amplifier, FM
IF and detector, and the AM converter, IF, and detector.
The device is suitable for both line operated and 9V battery
applications.

• DC selection of AM/FM mode
• Regulated supply
• Audio amplifier bandwidth decreased in AM mode,
reducing amplifier noise in the AM band
• AM converter AGC for excellent overload
characteristics
• Low current internal AM detector for low tweet radiation

Block Diagram

ii":
CI7

O.OI"F
FM IF~ ..INPUT

OFM

51

•

r

,....._.........,

....-Qo-f

tGI

LI

~

~r:r=~-LM-'888__r====b~=!::;-lI

•

I
I

L_

iL_..I.tJ'
~8~"

A9
240k

AI
Ill!

li~

Vs

i

+

CII

I'"

-+-.......__":"___ ..J

TL/HI7909-1

Order Number LM1868N
See NS Package Number N20A
Note: See table for coil data

2-35

Absolute Maximum Ratings
- 55'C to + 150'C
O'Cto +70'C
260'C

Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec.)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
15V
Supply Voltage (Pin 19)
Package Dissipation
2.0W
Above TA = 25'C, Derate Based on
TJ(MAX) = 150·C and 8JA = 60·C/W

Electrical Characteristics Test Circuit, TA = 25'C, Vs = 9V, RL = 80 (unless otherwise noted)
Parameter

I

I

Conditions

I

Min

I

Typ

Max

I

Units

STATIC CHARACTERISTICS eAM = 0, eFM = 0
Supply Current

AM Mode, S1 in Position 1

Regulator Output Voltage (Pin 16)

3.5

Operating Voltage Range

4.5

22

30

mA

3.9

4.8

V

15

DYNAMIC CHARACTERISTICS-AM MODE
fAM = 1 MHz, fmod = 1 kHz, 30% Modulation, Sl in Position 1, Po

= 50 mW unless noted
= 50 mW,
8

Maximum Sensitivity

Measure eAM for Po
Maximum Volume

Signal-to-Noise

eAM

Detector Output

eAM = 1 mV
Measure at Top of Volume Control

Overload Distortion

eAM

Total Harmonic Distortion (THO)

eAM = 10 mV

DYNAMIC CHARACTERISTICS-FM MODE fFM

= 10mV

16

40

50

40

60

85

2

10

%

1.1

2

%

= 50 mV, 80% Modulation

dB
mV

= 10.7 MHz, fmod = 400 Hz, ~f = ±75 kHz, Po = 50 mW, Sl in Position 1

-3 dB Limiting Sensitivity

15

Signal-to-Noise Ratio

eFM = 10mV

50

64

Detector Output

eFM = 10 mV, ~f = ±22.5 kHz
Measure at Top of Volume Control

40

60

AM Rejection

eFM = 10 mV, 30% AM Modulation

40

Total Harmonic Distortion (THO)

eFM = 10 mV

45

p,V
dB

85

mV

50

dB

2

1.1

DYNAMIC CHARACTERISTICS-AUDIO AMPLIFIER ONLY f
Power Output

p,V

%

= 1 kHz, eAM = 0, eFM = 0, S1 in Position 2

THO = 10%, RL 80

Bandwidth
Total Harmonic Distortion (THO)

~=~

~

~

~=W

~

~

mW
mW

AM Mode, Po = 50 mW
FM Mode, Po = 50 mW

22

11

Po = 50 mW, FM Mode

0.2

%

41

dB

Voltage Gain

kHz
kHz

Typical Performance Characteristics (Test Circuit) All curves are measured at audio output
Quiescent Supply Current
vsVoltage
3IrT~~~rT~~~I~

24
II

A~ MbDE +-I::::jloo+-.L'I""I--l
J...I.-

El-iI-I~H+-HF~:.:IM~OD1=E+-I

11-++1-++1-+-1-1-++-1
aL..J.....l..-L..J.....l..-L..J.....l..-L....I......1...J

4111'12141.
SUPPLVVDLTAGE (V)

FM Limiting Characteristics

~ID
~

II:

i

-II

i

-20

1/

i

-30
-41

R!o...

~

I /

:: -ID

\

-70

I

E
10.0 I

1\

a

..=

f .. -4I1OHI

-10

i

a

ol--+._t--'+--+-I
1.
f--tf-~oU&kHzI--+---f

•

I

...

II

ul
u ~

TH ..

III
N laG

n

I.

IF INPUTVDLTAOE ("v)

2-36

D.I
1liii0

~

!.,

.

Ii

~

ID

FM IF AM Rejection
,..-""'T-.,...---'-:--'---.

...

or-~_+-~~~~

I-+l---!---+--+---f
-.21 I-.,I'L-+--!---+_-+---f

.. -10

~

! -3D

/

ii

-

S
!i

-40

-10

l!!.. -II

;) -71 1

~

"
"

AMH+N

AfoU6kHzI-..3jo-+-""""
"".~4OD
Hz
_ AM MOO~LAT(ON
"

100

1k

I
10k

IF INPUT VOLTAGE lIN)

'1IOk

TL/HI7909-2

Typical Performance Characteristics

(Continued)

All curves are measured at audio output (Test Circuit)
AM Characteristics

Iii

10

..,

...

StN

~

~

t

..

z
»-

-10

III
I -28

i

lD.D

3.2

-3D

I.. ~
i

THD+N

1.1

W

-ID
-8G

lD

lDO

,.

11k

..~
..'"
!!
~

D.32

~~:~~l;,~: IIII

I

i

D.l

3Recovered

~

I I
I I
I FM

2

.t

-! 1.
t

F

~ -1

-7

lDOk 1M

co

' .. -1I1HI
f,-1 MHz

I.D

1:f

0.8

r-

t·

au
~

3"TH

IiID.I

'i'~TJO r-

:: 0.1

..t

Ii

s·g

is

~ GA

~

:;;

l!!

D.2

it"vs·.v

II I

U

1.2

1.1

11k

D.2

I

I
I

..r.;
''''THO

I I I

DA

1.2

OUTPUT POWER IWI

~

~Ll

I

...

POUT-SDoIW
RL -Ill

4

AM/ /
....-T/FM

1

a

...

1.1

ZI

I.Z

/

Z

z

I I I

vs:"'av

Z.8

Distortion vs Frequency
AudiO Amplifier Only

5

Iii

VS"ZV

~

lDM

1M

lDDk

FREQUENCY (Hz)

3"TH

VS'9V

I

OA

-21

~

I I
L
/II

~

III

I

1= 1kHz

DA

a
D

""

Power Dissipation vs Power
Out,RL = 16.11

~"2V

.,

AM
1m

101Z1411

1.0

'· 1k

~ II
ZD

SUPPLY VOLTAGE (VI

Power Dissipation vs Power
Output, RL = 8.11

i

lD.7MH.

4

41

is
>

-IN-'··V.

31n1 AM MOO

RF INPUT VOLTAGE IINI

1.2

:!

Af'±Zz'&k1~

.... ,amV

cI'"

2
.

FMMODE
' .. -400111

AM MODE

:: -&

SD

•:e

I I

-2

;-4

POUT'iDOIW
RL ·en

AM""

AM

s-3

Gain vs Frequency Audio
n Amplifier Only

Audio vs Supply

50 111

zn

J
&ID lk Zk

5k 1111 ZDk

FREQUENCY (H.I

OUTPUT POWER (WI

TLlHI7909-3

Test Circuit

AUDIDI!

OUTPUT

Z5DpF

8

•

•

D.1jJf

VS-.---t--~A~UD~'D~-r------------~-------------9
5D F

"T

~"F

INPUT

11

n

,.

~'F.

LII'888

a,01~F

I

____., fIpI

-.r"1"!
~~I

t~D~t

I

!~

.l.
..(
I
L _____: . __ !!:,___ __ !!__ ...J

Note: See table for coil data

FM

I

____ .J

U.F

~

TL/HI7909-4

2-37

LM1868

:J
'a
~

UpF

cn

'.TE':'~......j

....'

43,.
~
L'

Vs

I,(I~

1"IJlF

C14'

3.

19

c,c

~

CI5

O·
:::s

":"

L5

.,..

(
I

"2-

.,
...U
,
••

~

1\

'a

-

en

33pF

~

»

~;.~'.
:.

I'

'*"

I

(

....

•I

331
'

1

T

.:;.-

'"~

+""vs

..

Uh
'

• -3 dB limHing sensitivity: 7 ,.V

• Maximum sensitivity: 100 ,.V/m
• 20 dB quieting sensitivity: 250 ,.Vlm
• Tweet' worst case: 5%
100 mVlm: 1.5%

'Tweel is an audio lone producad by Ihe 2nd and 3rd harmonic of the IF
bealing against Ihe received signal. II is measured as an equivalent modulation level: i.e.• a 30% tweet has Ihe same amplitude althe delector as a
desired signal with 30% modulation.

.,..

I -

I

I

FMParl~ce(8;;H:-1;;M;)-~';;';;:nn:";;5;;;;--;;;:HZ)
• 30 dB quieting sensitivity: 3.5 ,.V

~i

I

II
-

-

-l

I

.,.L_

•.
~'C2

t~F

~

L.._

.
..
,

.,..

• L

,It

_ _ _ _ _ _ ...1I

-

-

.,..

r
til

TUHI7909-5

PC Board Layout

TL/H/7909-6

Component Side

Typical Performance Characteristics Typical Application
All curves are measured at audio output
10

'I

.

!II -20

•....

:3
:0

I!:
:0

"...
a::

/

51 -10

....
...

5i

S+N

-38

~

-&0

iii

c -10

:0

-70

51 -10

!II" -20

FMMOOE

\

S+N

•
ii

,

fO'9IMHZZ~

"f' ±75 kHz
fm ' 400 Hz

.
..

:3
:0

I!:
:0
co

~N

iii

:0

-38

•

...V

~.

1/

-40

10

L

V
AM MODE

,

r- l""'-40 ~
-&8

fm= I kHz
fo=1 MHz
30% MODULATION

N

r-

C

I

10 100
I.
10k
RF INPUT VOLTAGE ,,",VI

lOOk

0.1

10

100

lk

RF FIELD STRENGTH (mVlml
TL/HI7909-7

TL/HI7909-B

2-39

CD
CD

CD
,...

....:::&

IC External Components (Application Circuit)
Component

Typical

Comments

Value

Typical

Component

Comments

Value

}

C1

100pF

Removes tuner LO from IF input

R9

240k

C2

0.1 p.F

Antenna coupling capacitor

C19

1 p.F

C4,C5

0.01 p.F

FM IF decoupling capacitors

C7

10 p.F

IF coupling

C6,C9

0.005 p.F } AM smoothing/FM de-emphasis
1k
network, de-emphasis pole is
given by.

C8

0.1 p.F

IF coupling

C20

0.1 p.F

R10

50

R5

fl

e<

2'IT (C6

R6)
+ C9) (R4
R4 + R6

C10

10 p.F

C11

0.1 p.F

Regulator decoupling capacitor

C12

10p.F

AC coupling to volume control

0.1 p.F

C14

50 p.F

Power supply decoupling

C15

0.1 p.F

Audio amplifier input coupling

R7

3k
} Roll off signals from detector in
0.001 p.F the AM band to prevent radiation

R8

}

Power supply decoupling

100 p.F

Power amplifier feedback
decoupling, sets low frequency
supply rejection

16k

AM detector bias resistor

High frequency load for audio
amplifier, required to stabilize
audio amplifier

C21

250 p.F

Output coupling capacitor

Rl

6k2

Sets Q of quadrature coil,
determining FM THD and
recovered audio

Regulator decoupling capacitor

C13

C16
C17

Set AGC time constant

R2

12k

IF amplifier bias R

R3

5k6

Sets gain of AM IF and Q of AM
IF output tank

R4

10k

Detector load resistor

R6

50k

Volume control

C18

0.02 p.F

Power supply decoupling

R11, R12

1500

Terminates the ceramic filter,
biases FM IF input stage

D1

1N4148

Optional. Quickens the AGC
response during turn on

Coil and Tuning Capacitor Specifications
Cl

AM ANT 140 pF max 5.0 pF min
AM OSC 82 pF max 5.0 pF min
Trimmers 6 pF

FM 20 pF max 4.5 pF min
TOKO CY2·22124PT

L1

640 "H, au - 200
Rp-3k5@F-796kHz
(At secondary)

AM antenna
1 mV/meterinduces
approximately 100 "V
open circuit at the secondary

LO, L2 360 "H, au > 80 @F - 796 kHz

31
E

Tl

TOKO RWO·6A5105 or
equivalent

TL/HI7909-10
T2

Toko America
1250 Feehanville Drive
Mount Prospect. IL 60056
(312) 297·0070

TUHI7909-9

L4

SWG #20, N - 3'12T, inner
diameter = 5 mm

L5

SWG #20, N - 3%T, inner
diameter = 5 mm

L6

L - 0.44 "H, N - 4 %T, au - 70
SWG #20, N - 2 'I2T, inner
diameter - 5 mm

L7
CF2

10.7 MHz ceramic fi~er
MURATASFE 10.7 mAor
equivalent

10·.

au> 70@ 10.7 MHz, L to
resonate w/82 pF @10.7 MHz
TOKO KAC-K2318 or equivalent

II~}'

au> 14@455kHz,Lto
resonate w/180 pF @455 kHz
TOKO 159GC-A3785 or
equivalent

TL/HI7909-11
eFl

:;f°'1~
....

....

TOKO CFU-G90D or equivalent
BW > 4.8 kHz @ 455 kHz

13T

TUHI7909-12

.Murata
2200 Lake Perk Drive
Smyrna, GA 30080
(404) 436·1300

T3

:i)I@:

51pF

TL/HI7909-13

2-40

Apollo Electronics N8-107C
or equivalent

Layout Considerations

Circuit Description

AM SECTION
Most problems in an AM radio design are associated with
radiation of undesired signals to the loopstick. Depending
on the source, this radiation can cause a variety of problems
including tweet, poor signal-to-noise, and low frequency oscillation (motor boating). Although the level of radiation from
the LM1868 is low, the overall radio performance can be
degraded by improper PCB layout. Listed below are layout
considerations association with common problems.
1. Tweet: Locate the loopstick as far as possible from detector components C6, C9, R4, and R5. Orient C6, C9, R4,
and R5 parallel to the axis of the loopstick. Return R8, C6,
C9, and C19 to a separate ground run (see Typical Application PCB).
2. Poor Signal-to-Noise/Low Frequency Oscillation:
Twist speaker leads. Orient R1 0 and C20 parallel to the axis
of the loopstick. Locate C11 away from the loopstick.

AM SECTION
The AM section consists of a mixer stage, a separate local
oscillator, an IF gain block, an envelope detector, AGC circuits for controlling the IF and mixer gains, and a switching
circuit which disables the AM section in the FM mode.
Signals from the antenna are AC-coupled into pin 7, the
mixer input. This stage consists of a common-emitter amplifier driving a differential amp which is switched by the local
oscillator. With no mixer AGC, the current in the mixer is
330 ,.A; as the AGC is applied, the mixer current drops,
decreasing the gain, and also the input impedance drops,
reducing the signal at the input. The differential amp connected to pin 8 forms the local oscillator. Bias resistors are
arranged to present a negative impedance at pin 8. The
frequency of oscillation is determined by the tank circuit, the
peak-to-peak amplitude is approximately 300 ,.A times the
impedance at pin 8 in parallel with 8k2.
After passing through the ceramic filter. the IF signals are
applied to the IF input. Signals at pin 11 are amplified by two
AGC controlled common-emitter stages and then applied to
the PNP output stage connected to pin 13. Biasing is arranged so that the current in the first two stages is set by
the difference between a 250 ,.A current source and the
Darlington device connected to pin 12.
When the AGC threshold is exceeded, the Darlington device
turns ON, steering current away from the IF into ground,
reducing the IF gain. Current in the IF is monitored by the
mixer AGC circuit. When the current in the IF has dropped
to 30 /LA, corresponding to 30 dB gain reduction in the IF,
the mixer AGC line begins to draw current. This causes the
mixer current and input impedance to drop, as previously
described.
.

\

"."..

,

\

\ 6

101

1%

LOOPSTICK

/
1

1

/<....
I

"'"

,

/
/

/

1

\
\

\
\

"-..../
I

TL/H/7909-14

In general, radiation results from current flowing in a loop, In
case 1 this current loop results from decoupling detector
harmonics at pin 17; while in case 2, the current loop results
from decoupling noise at the output of the audio amplifier
and the output of the regulator. The level of radiation picked
up by the loopstick is approximately proportional to: 1) 1/r3;
where r is the distance from the center of the loopstick to
the center of the current loop; 2) SIN 9, where 9 is the angle
between the plane of the current loop and the axis of the
loopstick; 3) I, the current flowing in the loop; and 4) A, the
cross-sectional area of the current loop.
Pickup is kept low by short leads (low A), proper orientation
(9 '" 0 so SIN 9 '" 0), maximizing distance from sources to
loopstick, and keeping current levels low.

(See Equivalent Schematic)

The IF output is level shifted and then peak detected at
detector cap C1. By loading C1 with only the base current of
the following device, detector currents are kept low. Drive
from the AGC is taken at pin 14, while the AM detector
output is summed with the FM detector output at pin 17.

FMSECTION
The FM section is composed of a 6-stage limiting IF driving
a quadrature detector. The IF stages are identical with the
exceptions of the input stage, which is run at higher current
to reduce noise, and the last stage, which is switched OFF
in the AM mode. The quadrature detector collectors drive a
level shift arrangement which allows the detector output
load to be connected to the regulated supply.

FMSECTION
The pinout of the LM1868 has been chosen to minimize
layout problems, however some care in layout is required to
insure stability. The input source ground should return to C4
ground. CapaCitors C13 and C18 form the return path for
signal currents flowing in the quadrature coil. They should
connect directly to the proper pins with short PC traces (see
Typical Application PCB). The quadrature coil and input circuitry should be separated from each other as far as possible.

AUDIO AMPLIFIER
The audio amplifier has an internally set voltage gain of 120.
The bandwidth of the audio amplifier is reduced in the AM
mode so as to reduce the output noise falling in the AM
band. The bandwidth reduction is accomplished by reducing
the current in the input stage.

REGULATOR
A series pass regulator provides biaSing for the AM and FM
sections. Use of a PNP pass device allows the supply to
drop to within a few hundred millivolts of the regulator output and still be in regulation.

AUDIO AMPLIFIER
The standard layout considerations for audio amplifiers apply to the LM1868, that is: positive and negative inputs
should be returned to the same ground point, and leads to
the high frequency load should be kept short. In the case of
the LM 1868 this means returning the volume control ground
(R6) to the same ground point as C17, and keeping the
leads to C20 and R10 short.
2-41

Equivalent Schematic
HII

i
~

~

i

,
5
~

..,dll

II

II

2-42

~------------------------------------------------------~~

~

~National

CD
CO

~ Semiconductor

LM3089 FM Receiver IF System
General Description
The LM3089 has been designed to provide all the major
functions required for modern FM IF designs of automotive,
high-fidelity and communications receivers.

Features
• Three stage IF amplifier/limiter provides 12 /LV (typ)
-3 dB limiting sensitivity
• Balanced product detector and audio amplifier provide
400 mV (typ) of recovered audio with distortion as low
as 0.1 % with proper external coil designs.

• Four internal carrier level detectors provide delayed
AGC signal to tuner, IF level meter drive current and interchannel mute control
• AFC amplifier provides AFC current for tuner and/or
center tuning meters
• Improved operating and temperature performance, especially when using high Q quadrature coils in narrow
band FM communications receivers
• No mute circuit latchup problems
• A direct replacement for CA3089E

Connection Diagram
Dual-In-Une Package

AlGC

NTC
16

15

UNO

l14

TUNE
MEIER

MUTE
LOGrlC

113

12

REF
Vee

1"11

81~S

bo

D

J: r
OUT

OUT

TLlHI7149-2

TopYIew
Order Number LM3089N
See NS Package Number N16E

2-43

LM3089

m

0'
n
~

,------,
KAC-K2318HM'

I
II
I
2z"H

v·

10.7 MHz

-

f±jOOPf

I
II
I

ii

CO

iil
3

L ___ .J

f"rvV"'.........~M,.....
If OUTPUT

C

REf

5.1k _ _ _ _,
o.:BI:;,:A=-S_ _..J.\I\j"""'
18

AFC

~OUTPUT

I\)

t
DELAYED
AGC FOR
RFAMPLIflER

~
4

MUTING
SENSITIVITY
TLfHI7149-1

Taka America
1250 Feehanvill" Drive
Mount Prospect, IL 60056

(312) 297-0070

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Between Pin 11 and Pins 4, 14

5mA

DC Current Out of Pin 13

5mA

DC Current Out of Pin 15

2mA

I

Symbol

Parameter

1500mW
- 40"C to + 85'C

Storage Temperature Range

+16V

DC Current Out of Pin 12

Electrical Characteristics (TA =

Power Dissipation (Note 2)
Operating Temperature Range

-65'Cto + 150"C

Lead Temperature
(Soldering, 10 seconds)

260"C

25'C, Vee = + 12V, see Test Circuit)

I

I

Conditions

Min

I

Typ

I

I

Max

Units

DC CHARACTERISTICS (YIN = 0, NOT MUTED)
Supply Current
IF Input and Bias
Audio Output
AFCOutput
Reference Bias
Mute Control
IF Level
DelayedAGC

111

V1,2,3
V6
V7
V10
V12
V13
V15

DYNAMIC CHARACTERISTICS fo = 10.7 MHZ, af =
Input Limiting -3 dB
AM Rejection
Recovered Audio
Total Harmonic Distortion
Single Tuned (Note 1)
Double Tuned (Note 1)
Signal to Noise Ratio
Mute Control
IF Level
IF Level
DelayedAGC
DelayedAGC
Audio Muted

VIN(UM)
AMR
VO(AF)
THO

S+N/N
V12
V13
V13
V15
V15
Vo(AF)

4.2

23
1.9
5.6
5.6
5.6
5.4
0
4.7

30
2.4
6.0
6.0
6.0
6.0
0.5
5.3

mA
V
V
V
V
V
V
V

12
55
400

25

45
300

ILV
-dB
mVrms

16
1.2
5.0
5.0
5.0
5.0

± 75 kHz @ 400 Hz

VIN = 100 mV, AM: 30%
VIN=10mV
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN

=
=
=
=
=
=
=
=
=

100mV
100mV
100mV
100mV
100mV
500ILV
100mV
30mV
100 mV, V5 = +2.5V

500

0.5
0.1
70
0
5.0
1.5
0.1
2.5
60

60
4.0
1.0

%
%
dB
V
V
V
V
V
-dB

1.0
0.3
0.5
6.0
2.0
0.5

Nota 1: Distortion is a function of quadrature coil used.
Nota 2: For operation in ambient temperatures above 25'C, the device must be derated based on a 150"C maximum iunction temperature and a thermal resistence
of BO"C/W iunction to ambient

Typical Performance Characteristics
Typical AGC (Pin 15) and
Meter Output (Pin 13) vs
IF Input Signal

Typical S + N/N and IF Limiting
Sensitivity vs IF Input Signal
AUDIO OUTPUT ,75 kHz DEVIATION

0

lIT 1111111111111
11111111111111, I

10
20

. IN~I~E OUTPUT
" HP334A 01SToRTION ANALYZER)

30
40
50

I

0

5

Pin 15

~

3

/

&Q

I

&Q

1

10

100

1k

11.

IF INPUT VOLTAGE ,"V)

lOOk

jPin13

4

2

70

AM Rejection (30% Mod) vs
IF Input Signal

25

I

/.
Z I

/ \
\

10
20
30
40

50
60
70

"

• I

, I

10
ll1e 1II1II
100 1k
IF INPUT VOLTAGE -.V

1

10

100

lk

1..

lOOk

IF INPUT VOLTAGE ,"V)

TLlH17149-3

2-45

LM3089
IF Amplif_

Quadratu... Detector/IF Output

Y:-J

V'

n

:on::

"'R...

-t::...

::"1

GIlD AND
SUISTRATE

en

~

:II

n

~

CI

3

Dol

!

(i'

0"

;:U

=

c

""'"

aU"D~:uRE ~
Ii[~t=~~:=::~~~~~~~~::~~~~tj~;";Hr

~

.::I-t-+H';;;;IPUT~

~

IF.WUT

~++""O.=U1M
,"PUT

~

I"PASSIIIG

.....
,

If

Do

~~k!~ l·'

.....

•1.

:l.

R16~R151Rn
rHD

'IZ'!'"l''

t.nS-Uk

368

znSzlfI

........
'u

f~

.,

l~"...

IIIII

I»

3

. t-mll
0"

::

l'l:

r----

~

::J:~I
~;.--------m""
~Iy:"l4i...
~ 0"
...... ..,
~~=F===r.::n . .

4:: ...

1-

0"

Oil

:w

I

~ ~i.. inf-l'
1M

,
'"

*MUTtu I~'l

CONTROL
OUTPUT

LEVU
MElfA
OUTPUT

°JAUDHI
OUTPUT

Ok

A..

.:.t:
IF ....k Detecto.. oncl Drivers

...

.......

toO

7,"'1:
OUTPUT

Il&o

~I

on

:tI

•

MUTE

....r

AFC, Audio and Mute Control Amplifi. .
TUHI7149.-4

Typical Performance Characteristics

•

21
ZJ

i..

....
.."
ill

~

;;I

24

io-

23

I-'
zz io- ~

I

I

II

1 1

~ !OLT~8E ~EFJRE.~E J. 1

21
2&

Mute Control Output (Pin 12)
vs IF Input Signal

Reference Voltage, AGC and
Meter Output vs Supply Voltage

Supply Current (111) vs
Supply Voltage (V11)

--

.....-.

.-

"\.
1\

AGC OUTPUT 1"1111 AT V,N -ID ..V

I

1 I

I

\.
\.

I

I-- Hr:~:,~T~~N~ I--

~

21

•

20
•

8

l'

11

12

13 14 15

•

,.

I
8

"

1 1 1 I
11

12 13 14

1&

23 & l' 203010180
IF INPUT VOLTAGE -.V

16

SUPPLY VOLTAGE IV)

SUPPLY VOLTAGE M

TLlH/7149-5

DC Test Circuit

Typical Audio AHenuatlon
(Pin 8) vs Mute Input
Voltage (Pin 5)
-10

:I
:

D
10

•

20

5is

38

~

5
5!

~

\

\

40
50

,
\

10

1\

71

.1

,
~

o

U

1

2

1.&

2.&

MUTE INPUT VOLTAGE IPIN .IIVI
TL/H17149-6

TLlH17149-7

AC Test Circuit
3.

,..

I
I

KAC-K2318HM

'SINGLE TUNED
DEtECTOR COIL

,..-----,

I
I

I

I
I-I I
I
I I
I
lOOpF
I I
I
I I
I
I I
L
_J L.
3.lk

~

"OOU8LETUNEO
DETECTOR COIL

--~

IGOpF

'For single tuned dectector coil:

La tunes wHh 100 pF at 10.7 MHz
QUL (unloadedl .. 75
QL (Ioadedl .. 13 for V9 .. 150 mVrms

-

"For double tuned de1ector coli:
= auLSEC .. 75
kQ .. 0.7 for V9 .. 150 mVrms

QULPRI

Note:
The recovered audio output voltage will be approximately 0.5 dB les. when
uslng the double tuned detector coil.
For proper operation of the mute cireuR, the RF voltage at pin 9 should be
150 mVrms ±30 mV.

8.2.
TL/H17149-8

2-47

•

G)

!

:!I

AC Test Circuit (Continued)

TLlH/7149-9

2-48

~National

~ Semiconductor

LM3189 FM IF System
General Description

Features

The LM3189N is a monolithic integrated circuit that provides
all the functions of a comprehensive FM IF system. The
block diagram of the LM3189N includes a three stage FM IF
amplifier/limiter configuration with level detectors for each
stage, a doubly balanced quadrature FM detector and an
audio amplifier that features the optional use of a muting
(squelch) circuit.

• Exceptional limiting sensitivity: 12 ",V typ at -3 dB
pOint
• Low distortion: 0.1 % typ (with double-tuned coil)
• Single-coil tuning capability
• Improved (S + N)/N ratio
• Externally programmable recovered audio level
• Provides specific signal for control of inter-channel muting (squelch)
• Provides specific signal for direct drive of a tuning meter
• On channel step for search control
• Provides programmable AGC voltage for RF amplifier
• Provides a specific circuit for flexible audio output
• Internal supply voltage regulators
• Externally programmable ON channel step width, and
deviation at which muting occurs

The advanced circuit design of the IF system includes desirable deluxe features such as programmable delayed AGC
for the RF tuner, an AFC drive circuit, and an output signal
to drive a tuning meter and/or provide stereo switching logic. In addition, internal power supply regulators maintain a
nearly constant current drain over the voltage supply range
of +8.5V to + 16V.
The LM3189N is ideal for high fidelity operation. Distortion
in an LM3189N FM IF system is primarily a function of the
phase linearity characteristic of the outboard detector coil.
The LM3189N has all the features of the LM3089N plus
additions.
The LM3189N utilizes the 16-lead dual-in-line plastic package and can operate over the ambient temperature range of
-400C to + 85°C.

Block Diagram

2lJ,1H

TO INTERNAL
REGULATORS

IF ourl

11

QUADR~~:;

9
Uk

LM318B1I
7

AFC
DUTflUT
Ok

AUDIO
OUTPUT

DELAYED
'U' FOR
RFAMPL

-.-c..::+--1

,.

'"

1Z

'10
1&

(,(JI-'W_~13~==_O~~:;:::~D

...

TUNING METER

OUTPUT

LOGIC CIRCUITS

U

ONCHAIIiINEL

INDICATOR

.n
TL/HI7960-1

All resistance values are In 0
'L tunee with 100 pF (e) at 10.7 MHz.

00 '"

75

(Toko No. KACS K586HM or equivalent)

2-49

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Between Pin 11 and Pins 4, 14
16V
DC Current Out of Pin 12
5mA
DC Current Out of Pin 13
5mA
DC Current Out of Pin 15
2mA

Electrical Characteristics TA = 25'C, v+
Symbol

Power Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering. 10 sec.)

= 12V

Conditions
(See Single-Tuned Test Circuit)

Parameter

1500mW
-4O"Cto +85"C
-65"C to + 15O"C
260"C

Min

Typ

Max

Units

20

31

44

mA

1.2
1.2
1.2
7.5
5

2.0
2.0
2.0
9.5
5.75

2.4
2.4
2.4
11
6

V
V
V
V
V

12

25

p.V

45

55

325

500

650

mV

0.5
0.1

1

%
%

STATIC (DC) CHARACTERISTICS
111

Quiescent Circuit Current

V1
V2
V3
V15
V10

DC Voltages:
Terminal 1 (IF Input)
Terminal 2 (AC Return to Input)
Terminal 3 (DC Bias to Input)
Terminal 15 (RF AGC)
Terminal 10 (DC Reference)

No Signal Input, Non Muted

DYNAMIC CHARACTERISTICS
VI(lim)

Input Limiting Voltage (-3 dB Point)

AMR

AM Rejection (Term. 6)

VIN

VO(AF)

Recovered AF Voltage (Term. 6)

AM Mod.

THO

Total Harmonic Distortion (Note 1)
Single Tuned (Term. 6)
Double Tuned (Term. 6)

S + N/N

Signal Plus Noise to Noise Ratio
(Term. 6)

fOEV
V16

Deviation Mute Frequency

VIN

= 0.1V
= 30%

fo = 10.7 MHz,
fmod = 400 Hz,
Deviation ± 75 kHz

= O.W
65
fmod = 0

RF AGC Threshold

dB

80

dB

±40

kHz

1.25

V

0
fOEY < ± 40 kHz
V
5.6
fOEY > ± 40 kHz
Nota 1: THO characteristics are essentially a function of the phase characteristics of the networl< connected between terminals 8, 9, and 10.
Note 2: For operation in ambient temperatures above 25'C, the device must be derated based on a 150'C maximum junction temperature and atharmaI resistance
of 80'C/W juncUon to ambient.

V12

On Channel Step

VIN

= 0.1V

Connection Diagram
Dual-In-Line Package
AGe

I,.

AGe

1,5

TUNE
METER

MUTE
LOGIC

j"

112

1~3 IF!:D

uJ:

OND

I,.

Vee

REF
BIAS

AU!:O

J:

QUAD

INPUT

j;, I,D I.

~
)I~

DECOI:PLE

.'AS

'NPUT

OUT

OUT

Top View
Order Number LM3189N
See NS Package Number N1SE
2·50

!:

OUT

TLlH/7960-2

Test Circuits
Test Circuit for LM3189N Using a Single-Tuned Detector Coil

r----'I

1

All resistance values are in n
'L tunes with 100 pF (C) at 10.7 MHz,
0o(unloaded) .. 75 (Taka No. KACS K586HM
or equivalent)

1
I

lO

I

c

I

'lIOp'

"c - O.Ot ,..F for 50 p.S de-emphasis (Europe)

u.

J

- O.ot 5 ,..F for 75 p.S de-emphasis (USA)

Pt.TO13

-='0.

J

U3

"F

TUNING METER
150~A

FULL· SCALE

TL/H/7960~3

Test Circuit for LM3189N Using a Double-Tuned Detector Coli

,----,

All resistance values are in n
'T:PRI-Oo(unloaded- '" 75 (tunes with 100 pF
(CI2» 201 of 34e on 7132' dla form
SEC-O.,(unloaded) '" 75 (tunes with 100 pF
(C2» 20t of 34e on 7/32' dla form
kO(percent of critical coupling) .. 70%
(adjustad for COIl voltage (Vel - 150 mV
Above values permR proper operation of mute
(squelch) circuR "E" type slugs, spacing 4 mm

"c - O.ot ,..F for 50 p.S de-emphasis (Europe)

1

3k

1

100pF

188'
I
1
I

_TO_

1
1
I

cz
'OOpF

I

1

1I
I
1

I
I
I

- O.ot 5 ,..F for 75 p.S de-emphasis (USA)

Uk

5'

~""F

>..iI..------....--.~~~~:h
TO
PIN 13

TUNING METER

15hA
FULL· SCALE

TLlH/7960-4

2-51

Complete FM IF System for High Quality Tuners
The circuit provides a complete FM IF system for a high
quality receiver. Either one or two stages of amplification
and bandpass filtering may be desired, depening on the

receiver requirements. See graph for rypical Limiting and
Noise Characteristics for each circuit configuration which
can be compared to the LM3189N alone.

Complete FM IF System for High Quality Receivers

,.k

r-"1'--........,.IIr-~-"1'---------------o12V

-rIO., rIO.,
":"

Uk

381

3.311

":"

311

47

>,~

___-I~-:-:-_""''''UDl.

UnF

All resistance values are In

n

CF: Ceramic filters. Toko CSFE or equivalent
'L tunes with 100 pF (0) at 10.7 MHz
Qo(unloadedj .. 75 (Toko No. KACS K586 HM
or equivalent)

RfAGC

TLlH/7960-5

Printed Circuit Board and Component Layout

TL/HI7960-6

Component Side

2·52

Typical Performance Characteristics

..a

AM Rejection (30% Mod) vs
IF Input Signal

Mute Control Output
(Pin 12) vslF Input Signal

co

:il

-10

~i

-30

;1
co-

il
ill
!!~

!

...

8
0

.

l

-21

L\

-40
-fiG

r-

4

-aD

S
>

1\

!iii

.

3

\.

1

~

100

II

lk

10k

1

lOOk 10DDk

IF INPUT VOLTAGE I.VI

2

3

5

10

...

co

....
=~

-10

r---

j:~

-20

r--r--

im
g=:!

....
c ..

....

-3~

~~~A~~C,,~

.. C

>,.. -4D

coc

~

~V8LUIISU"'LY

I-

V.1111
AMIIIUTTEWlIIATUJlf:

r----

8

TEITCI::t:~1
:I.'1~,.t.~..~

10

110

4

-'

lk

:":::::::TT~~ :'A';~oc

..
.

.

~

~

zoa

.,..

1&1
101

Iii

D

i

n

~

!!

=

..
II!

2

&I

/'

-fiG

-150
-100

0

'1III1c

.

IiII
co
'"

~
I!I

V

,..

_l
\
\

10

BD
20
0
0

0

3

-II

5

..~

-20

II!

-eo

~

.......

/

D

-60

101

5'

150

2D

PI

-3~

..'UlHY...TI... ··".",

~

- _._.-

:~:,~~~~:~~r::1

2mnRAIiDOAIIlIr"GII

\'. '\..

'\..

\

-50

~

........"IIIOIlE

...

.1

'. .1,

-70
1&

....--

/

1/

-10
10

r--r---

f-I- -:.~- :::=::i:tO~O"

> -40

"

40

3

Typlcsl Limiting and Noise
Characteristics

iii

'20
100

2.5

L

DCSUPPLYVDLTAGE y+ '12V
AMBIENTTEMPEftATURE TA • %i·C
140

2

41 - CHANGE IN FREIIUENCY IkHzl

Deviation Mute Threshold as
a Function of Load Resistance
(Between Term 7 and Term 10)

9
~0:
i!

1.5

V

B -100

10k

1

AFC Characteristics (Current
at Term 7 as a Function
of Change In Frequency)

INPUT SIGNAL ,"VI

i~

1.5

MUTE INPUT VOLTAGE CPtN &1 IVI

~

<

T,,"+HC
UElIlIlILtT\llln

'l "1'.7''''~
1

\.
\.

78
0

~

\~

-50

1111

2030 III 100

C
I

[ftIDNTCD DJlDlNATfI
1I'I1I11"".Ul

~iC

50

DC ......UPPLy v· -1ZV

FIIOII'ULL

DUtl'UT!UFr

GIIII.OlllAn]

TrIlMlI"LIlUlt

I

\.
\.

4D

10

10

JlRIYEIIIDAUIiO

13

\

30

IF INPUT VOL lADE '"VI

Muting Action, Tuner AGC, and Tuning
Meter Output as a Function
o of Input Signal Voltage

~iii

\.

20

..~
..~.
a

2

0
1

0
10

&

~

I!:

-70

.•

'r\.

CD

c

-Ii

3

&1--1-0

is

Typical Audio Attenuation
(Pin 6) vs Mute Input
Voltage (Pin 5)

21

1

LDAD RESISTANCE
IBETWEEN TERM 7 AND TERM 1111 Cltnl

11

lei

103

,"

,05

SIGNAL LEVEL ,"Vi

TLlHI7960-7

2-53

Schematic Diagram
n

.. ).:

J~

10k

........
.11

':"

..
'"

"
"'

,

II

.ND

f-

~t'"
010011

RIIA

'"

.

,

'13
'"

'A'

.1<

",SO

''""

JJI

,,,

'00

"'

• IS

~

.,k

.,........

~

o!I

~y

...

..

,

AI'

'BJ

'DO
.".

.".

.

...

..

",
"

...

"
",
Q&J

.

...

'U

....

.".

'"

'IS

'"

~

RIIiA

~

'"

""" ••

"

Ku'
",

.

.11

co

...

"

'lID
52

...'"

~

1.:...

~,
....

HZ'

'"'"

~

...

.kJ

Q8'

,..

ror

'e

.50

;.

.13.>:

).
.,. ..
'",'10 h:

1"'."
.,.

0101

••

......

21.

RJ
~,JO

,~

~ rr:.I<.

HZ

......, .......

~~

.u
~

01A

oz.

.

I--

RIZA

............

:.~

•

... OZ,

RllA
2k2

~Y
....

RI

m

3

", '"

0..,

n.

.

.11

,"'II

U

R5

If

~

..n

~'~ ~~
.......

......,
....

,

"'II

"
~m

"

I~·

T

INPUT

J."

~>

~~Z1'"

H&'A

",

....

~.11

...

'56
"D

-

.".

'"
'"

IJY

t"'."

CI

",F

."
"

"

TMllfCI.
TLlH/7960-8

2-54

Schematic Diagram (Continued)

."..,

...--If---------'::'O ~~~ID

."..

RIO

.,.

RJ3 RlI

..

to
":'

'"
":'

'"

".

v·

":'

R"

T '"

50'

'OpF

":'

":'

":'

"

":'

TL/H/7960-9

2-55

.... ,----------------------------------------------------------------,
~National

~

I

....I

~ Semiconductor

LM3361A Low Voltage/Power Narrow Band FM IF System
General Description

Features

The LM3361A contains a complete narrow band FM demodulation system operable to less than 2V supply voltage.
Blocks within the device include an oscillator, mixer, FM IF
limiting amplifier, FM demodulator, op amp, scan control,
and mute switch. The LM3361A is similar to the MC3361
with the following improvements: the LM3361A has higher
voltage swing both at the op amp and audio outputs. It also
has lower nominal drain current and a squelch circuit that
draws significantly less current than the MC3361. Device
pinout functions are identical with some slightly different operating characteristics.

•
•
•
•
•
•

Functions at low supply voltage (less than 2V)
Highly sensitive (-3 dB limiting at 2.0 p.V input typical)
High audio output (increased 6 dB over MC3361)
Low drain current (2.8 mA typ., Vcc=3.6V)
Minimal drain current increase when squelched
Low external parts count

Block Diagram and Test Circuit
TO Vs

Op AMP
INPUT

RF
INPUT
(10.7 MHz)

Op AMP
OUTPUT

o--....IV\".,........

l

=10Vlml)
KHz

(3111,.

0.1,.f \f

1K
M5 r+_OAUDIO
r _ _ _""",7K
OUTPUT

T

O.01 ,.F

1K8
3

4

5

120

pF

-

-

~----~----------. .-----------------------~----------_oVs

Is

TL/H/5586-1

Order Number LM3661AM
orLM3361AN
See NS Package Number
M16AorN16E

T1·TOKO RMC·2A6597HM
CF·MURATA CFU 455E

2-56

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Package Dissipation (Note 1)
1500mW

Soldering Information
Dual·ln·Line Package
Soldering (10 seconds)
260"C
Small Outline Package
215·C
Vapor Phase (60 seconds)
220"C
Infrared (15 seconds)
See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering sur·
face mount devices.

12V
Power Supply Voltage (Vs)
RF Input Voltage (Vs>3.6V)
1 Vrms
Mute Function (pin 14)
-0.7t05Vp
Operating Ambient Temperature Range
O"Cto +70"C
-55·Cto + 150"C
Storage Temperature Range

Parameters Guaranteed By Electrical Testing
(Test ckt., TA=25·C, Vs=3.6V, fo=10.7 MHz, A.f= ±3 kHz, fMoe=1 kHz, 500 source)
Parameter

Measure

Min

Typ

Max

Units

2.0

3.6

9.0

V

Is
Is

2.8
3.6

5.0
6.0

mA
mA

RF Input for -3 dB Limiting

RF Input

2.0

6.0

Recovered Audio at Audio Output

Audio Output

200

350

Audio Out DC

Vg

1.2

1.5

OpAmpGain

Vll/VIN

40

55

Op Amp Output DC

Vl0

0.4

0.7

Op Amp Input Bias Current

(V1O- Vll)/1MO

Scan Voltage
Pin 12 high (2V)
Pin 12 Low (OV)

V13
V13

Supply Voltage Range

Vs

Supply Current
Squelch Off
Squelch On

Mute Switch Impedance, Pin 12 = OV
Switch S1 from pos.1 to pos.2

3.0

A.VI4/A.114

,..V
mVRMs

1.8

Vee
dB
Vee

20

75

nA

0
3.4

0.5

Vee
Vee

15

30

0

Design Parameters Not Tested or Guaranteed
Typ
Mixer Conversion Gain (Note 2)
46
VIV
kO
Mixer Input Resistance
3.6
pF
Mixer Input Capacitance
2.2
Detector Output Impedance
500
0
100
mV
Squelch Hysterisis
Mute Off Impedance (measure pin 14 with pin 12 @ 2V)
10
MO
0.65
Squelch Threshold
Vee
V/kHz
Detector Center Frequency Slope
0.15
Note 1. For operation above 25'C ambient temperature, the device must be derated based on 150"C maximum lunction temperature and a thermal resistance 8JA
of80"C/W.
Note 2. Mixer gain is supply dependent and effects overall sensitivity accordingly (See TypiceJ Performance Characteristics).
Filters:
Murata
2200 Lake Park Drive
Smyrna, GA 30080
(404) 436-1300

Colis:
Toko America
1250 Feehanville Drive
Mount Prospect, IL 80058
(312) 297'()070

2·57

c~-------------------------------------------------------------------,
.~
Typical Performance Characteristics (Test Circuits)

:!i
I. va. v.

10

I

8

.......

6
4

"""

2
00

2

4

~TE

~

ON

I

MUTE

OFF

I
6

20dl I'. 8EIII1n"" AID
AUDIO OUT IS. I.

111

8

•

•

I""

4

,

a

I
I

10

00

2

4

6

·20

·30
·40

",
'\.

·60

·60

0.001 0.01

0.1

10

I
10·

10.6

THO

i
1

.!

_ 0.8

; '.4

\..

tv*1

•

841!

TIl. AIO AUD OUT VI Q
AUDIO /r ~
1
OUT /~".
___ ~,..
0.•

1

S+N

~

!:i

IUDIO_
OIT

II

FM IF CHARACTERISTIC

·10

. 1=

,~

V.

10

-..

~

I;"

2

Vs (Valtsl

•

I
SENSITIVITY
I'

J

/

0.4~

/

0.2 ......'-+-+----1--10.2

o0!:--:1::-0-=2D:--~3D::---!.4DO

100

aUAD COIL Q

RF IN (IIVmIIl

TL/H/5586-2

2-58

~·t -t
211

a20

e'

8_

~a2

Rl 03,

51K

04'7

R3
10K

a5'7
i

"a6

R2
,'K8

H4
10K

y

H5
10K

Q8

H15
6K8

R6
10K

H7
10K

H9
10K

HI

10K

~al1
H16
10K

~
<0

HID
10K

H4Q
7K ...ra43

v.

H41
7K

H14
2114

H19
13K

10PF

..a18

~~
I

2

"051

r05P--

KQ41
145
27K

H46
2K

~

R31
3K

27K

...

tn
n

:::T

CD

3

I»

( ;'

~1Il

H23
3K3

R24
33K

H25
7K5

H26
33K

4
H50

IKe

r-

rr

....058:PJ

H52 H53
51K 36K

H54
3KI

H55
2K

r' , 7054 ...

147
27K

'

-'

::s ~055

H48
27K

kE
064

R51
10K

'~j~

.

065

R61
39K

H60
220K

061'-.

Q60'at
fA

H49
56K

.: f:;056

039'?144
27K

a3~7

3

053......

"'"

....a·
Il!iDPF I.,i'
a33::S~
l~~
H31
...
3K
H33

~2. ~32

"-

.... 050
R43
3K6

CD

3
et

R34
lOOK

a:

i1

)08

H2O
H3

H42
10K

~~~~~>

.... H38
15K

R37
4K3

~

021 a22

'A

.... 038

04Q::S~

H13
2K4

'''~

... 15

037::S~

R36
75K

H12
10K

--

Front Porch: The section of the composite video signal between the end of the picture information on a scan line (start
of blanking) and the start of the line synchronization pulse.
Horizontal Blanking: The blanking signal at the end of
each scan line that prevents the retrace of the display tube
electron beam from being visible.
Horizontal Retrace: The rapid return of the scanning electron beam from the right side of the raster to the leit side.
Horizontal Hum Bars: Relatively broad horizontal bars driiting slowly up the screen as a result of interierence from the
60 Hz main frequency.
Hue (TInt): Describes the color that is being represented on
the screen, i.e., red, blue, magenta, green, orange, etc.
Interlace: A scanning process in which each adjacent line
belongs to the alternate field.
I_R.E.: Institute of Radio Engineers. Now combined with the
AlEE to form the IEEE.
I.R.E_ Scale: An oscilloscope scale calibrated for composite
video and divided vertically into 140 units. The picture signal
occupies the range from 0 to 100 with syncs in the range 0
to -40.
Luminance: The monochrome or brightness part of the color Signal, composed of specific' prQPortions of the three primary colors, red, blue, and green.
N.T.S.C.: National Television System Committee, used in
reference to the system adopted for color television broadcasting in the U.S. at the end of 1953.
Noise: In a television picture, 'noise' refers to random interference producing a salt and pepper pattern over the picture. Heavy noise totally obscuring the picture is called

signal. For U.S. television, the audio signal is increased at a
6 db/octave rate above Z.1 kHz.
'
Raster: The area on the face of the display tube that is
scanned by the electron beam. This is not always entirely
visible since commercial receivers employ overscan so that
the edges of the raster are hidden by the faceplate.
Reference Signals: See V.I.T.S. and V.I.R.S.
Resolution (Horizontal): The amount of resolvable detail in
the horizontal direction of the picture. This depends on the
high frequency and phase response of the transmission system and the receiver.
Resolution (Vertical): The amount of resolvable detail in
the vertical direction of the picture. This depends primarily
on the number of scan lines that are used and secondarily
on the size (shape) of the electron scanning beam.
Saturation (Color): The amplitude of the chrominance signal. Increased saturation means increased chrominance
signal level. Visibly, this refers to a color increasing from
pale or pastel to deep.
S.E.C.A.M.: Sequential Couleur Avec Memoire. The color
broadcasting system used predominantly in France which
utilizes sequential transmission of the color difference signals, which are FM modulated on two separate subcarriers
(1967).
Setup: The difference in level between the blanking level
and the reference black level expressed as a percent of the
reference white level.
Smear: Smear describes' a picture condition where objects
appear extended in the horizontal direction producing an illdefined, blurry picture. This oiten occurs when the receiver
is tuned Slightly above the proper pix carrier frequency.
Sync: Abbreviation for synchronizing or synchronization.
Sync Level: The level of the synchronizing pulse tips.
Vertical Blanking: The blanking signal at the end of each
field starting three lines before the vertical sync pulse.
Vertical Retrace: The return of the electron beam from !,he
bottom of the display to the top aiter a complete field has
been scanned.
V.I.R.S.: Vertical Interval Reference Signal. A quality control
signal added to a horizontal scan line during the vertical
blanking period. It is used to provide a chrominance, luminance and black level reference.
V.I.T.S.: Vertical Interval Test Signals. A series of test signals that are added to horizontal lines during the vertical
blanking for' in-service testing of the transmission equipment. They can be deleted or added at various points in the
transmission link, unlike the VIRS, which is added at program origination and stays with the program material.
Vestlgal Sideband Transmission: A broadcast transmission,technique wherein only one side band of an amplitude
modulated carrier is fully transmitted with the other sideband ,(usually lower) truncated.
Video: The visible portion of the transmitted' signal representing the picture:

"snow".
Overshoot: An (excessive) response to a unidirectional signal change. Overshoot is oiten used deliberately to enhance the luminance portion of a signal.
Pairing: A partial or complete failure of interlace in which
scan lines of alternate fields fall in pairs, one on top of the
other.
Pedestal Level: See Blanking Level.
Percentage Sync:
Video: The ratio in percent of the amplitude of the synchronizing pulse to the peak amplitude of the picture signal between blanking and reference white level. For a
properly constituted compOSite video signal this is 40%.
RF: The ratio is a percent of the amplitude of the synchronizing pulse to the peak amplitude of the modulated
RF Signal. For correct modulation this is 25%.
P.A.L.: Phase Alternation Line. A variation of the NTSC system involving phase reverl!81 of one of the color difference
Signals on a line by line basis, introduced into the U.K. and
Germany in 1967.
Picture Signal: That portion of the composite video signal
which is above the blanking level and contains the picture
information.
Pre-emphasis: An increase in the level of a band of frequency components with respect to the remainder of the

3-4

IjNational
Semiconductor
Video Circuits Selection Guide
Video Amplifiers
Bandwidth

Gain

Package

Supply Voltage

LM1201

200 MHz

4-10

16Pin DIP

+12V

Single Amplifier with
Black Level and Contrast
Control

LM1203

70 MHz

4-10

28 Pin DIP

+12V

Triple Amplifier System
with Black Level and Balanced
Contrast Control

LM1204

150 MHz

1-10

44 Pin PLCC

12V

Triple Amplifier System
with DC Controls and
Sync Detector. Provides
Blanking at CRT Cathode.

LM2416

45 MHz

-13

11 PinT0220

80V

• Triple CRT Driver
• 50 Vpp Output Swing
with 10 ns 1,/tl

LM2418

30 MHz

-19

11 PinT0220

90V

• Triple CRT Driver
• 50 Vpp Output Swing
with 10 ns trltl

Comments

Video Timing
Function

Package

Supply Voltage

Comments

LM1391

Low-Freq PLL

8 Pin DIP

Internally Regulated

For Horizontal Section

LM1881

Sync Separator

8 Pin DIP
8 Pin SO

5V-12V

Outputs Provided:
CompOSite Sync
Vertical
Burst Gate
OddlEven Field

LM1882

Sync Generator

20 Pin DIP
20 Pin LCC

5V

130 MHz Max Clock Frequency.
Both Interlaced and NonInterlaced Formats. Control Via
Register Programming with
NTSC Default Values.

3-5

•

Video Circuits (Continued)
VldeolFs
Application

Package

Comments

LM1211

Broadband Demodulator
Date or Video Recovery
from LANs, Other Comm. Systems

20 Pin DIP

Operating Range 20 MHz-80 MHz
Quasi-Synchronous Detector
25 MHz Output Amplifier

LM1823

Video IF Signal Processing

28 Pin DIP

Operating Range 20 MHz-70 MHz
Synchronous Detector using PLL
9 MHz Output Amplifier

Other Video Products
Function

Package

SUpply Voltsge

Comments

LM1044

Video Switch

24 Pin DIP

8V-16V

• DC Switch between 3
Composite Video
Channels or 2 RGB
Channels
• 60 dB Channel Separation

LH4266

SPDT rf Switch

24 Pin
Hermetic

±8V-±18V

3-6

•
•
•
•

DC to 150 MHz Switch
Break-before-Make
TTL Control Input
Low Insertion Loss 1.5 dB
(500)

~National

~semlconductor

LH4266 SPOT RF Switch
•
•
•
•
•
•

General Description
The LH4266 is a single pole double throw switch intended
for RF and video switching applications. The device has a
TIL compatible control signal and can be configured as a
multiplexer or demultiplexer which will fulfill most switching
needs.
The non-selected input may be terminated to provide a
match to the source driving that port and prevent spurious
oscillations that might occur from an unterminated transmission line.

+27.5 dBm maximum signal (500)
Low insertion loss 1.5 dB (500)
Non-selected input terminated
Break before make
TIL compatible control signal
Internal power supply bypassing

Applications
•
•
•
•

Features

ATE pin driver switch
Computer RF switch
Tester switching matrix
RF voltage multiplexer

• Single pole double throw (SPDn
• DC to 150 MHz

Connection Diagram
Ne
Ne
Ne
Ne
GROUND
OUTPUT(VO>

CONTROL
GROUND

Ne
Ne

Ne

Ne

Ne

---F:"'TERMINATION'
'------t""-INPUT' (v,)
TL/K/9404-1

Top View
Note: NC means no internal connection.

Order Number LH4266CD or LH4266D
See NS Package Number D241

3-7

Absolute Maximum Ratings
If Mllitary/Aero.pace specified devices are rsqulred,
please contact the National Semiconductor Sales
Offlce/Dlstrlbutora for availability and specifications.
Supply Voltage, (Vs)
±18V
Power Dissipation, (Po)(See Curve)
Input Signal, (VIN)
ESO

Control Voltage, (Vel
Storage Temperature Range, (TSTG)
Operating Temperature Range, (TAl
LH4266CD
LH42880

2.0W

u

Parameter

± 15V, Rs

=

500, RL

Conditions
Typical

Supply
Current

Is

- 25°C to + 85°C
- 55°C to + 125°C

=

300"C

500, TA = 25°C unless otherwise noted.
LH4266C

Symbol

+ 150°C

Lead Temperature (T
(Soldering, < 10 seconds)

±VS
TSO

DC Electrical Characteristics Vs =

Vs-2V
-65°C to

Tested
Limit
(Note 2)

V+

4.8

7

V-

-47

-60

Design
Limit
(Note 3)

Unite
(Max. unless
otherwise
noted)
mA

VTH

Logic High

1.5

2.0

V (Min)

VTL

Logie Low

0.5

0.8

V
p.A

liN

Control Input Current

VIN

= OVto 5V

2.0

3.0

RON

On Resistance

15

18

ar

ReSistance Match

V1 = V2 = OV,
10 = 1 mA

Leakage Current

0

4

V1-2 = Vo = ±5V,
Switch On, Note 4

100

V1-2 = Vo = ±5V,
Switch Off, Note 4

100

V1-2 = Vo = ±5V,
Input to Input

100

nA

DC Electrical Characteristics
Vs

=

±15V, Rs

=

500, RL

=

500, TA

=

25°C unless otherwise noted. (Note 1)
LH4266

Symbol

Parameter

Conditions
Typical

Is

Supply
Current

Tested
Limit
(Note 2)

V+

4.8

7

V-

-47

-80

Design
Limit
(Note 3)

Unite
(Max. unless
otherwise
noted)
mA
V (Min)

VTH

Logic High

1.5

1.8

VTL

Logie Low

0.5

0.8

V

liN

Contrallnput Current

2.0

3.0

p.A

RON

On Resistance

ar

Resistance Match
Leakage Current

= OVt05V
V1 = V2 = OV,
10 = 1 mA
VIN

30

15

0

8

V1-2 = Vo = ±5V,
Switch On, Note 4

1

V1-2 = Vo = ±5V,
Switch Off, Note 4

1

V1-2 = Vo = ±5V,
Input to Input

1

3·8

p.A

AC Electrical Characteristics Vs =

± 15V, Rs

= 500, RL = 500, TA = 25°C, unless otherwise noted.
LH4266C/LH4266

Symbol

Parameter

Condltlon8
Typical

Insertion Loss

VSWR

Tested
Limit

De81gn
Limit

(Note 2)

(Note 3)

10MHz

1.0

1.5

100 MHz

2.0

2.3

Isolation Input to Output
See Test Circuit

10MHz

90

75

100 MHz

75

60

Isolation Input1
to Input2

10MHz

90

Distortion

VOUT

100 MHz

Units
(Max. unle88
otherwise
noted)
dB

dB
(Min)

60

= 10 Vp_p

Unselected Input

1.0

%

1.5: 1

Ratio

Switching Speed
ns
500
Boldface limits are guaranteed over full temparature range.
Note 2: Tested limits are guaranteed and 100% production tested.
Note 3: Design limits are guaranteed (but not production tested) over the Indicated temparature range. These limits are not used to calculate outgOing quality level.
Note 4: Leakage current is measured with signal applied to each Input. See test circuit.
Tsw

Note 1:

•
3·9

Typical Performance Characteristics
Insertion Loas

Supply Current

Allowable Input Signal

6
250C

+125OC/
5

/1

4

~
~

!
13

~J '=5,!,J
1/
1/

3
2_
1
0,01

J

!

-~.
r

Negative

--40

~ t::.. .......

j

J

~

..,. . /

t

~

J
I

30

J

i

2

I

20

i

10

-so

0
so
T........I_ (OC)

80

:t8

2.0

/

:tl0 :t12 :t14 :t16 *18
Pow... Supply Voltage (Volts)

100

"

«I

j

70
60

"!I

so

!
I

~
I

20

"!I

1102

90
80

103

.......

«I
30
20
10
0
10'

102

-5SCC

~

1

,

1.5

\

1.4

'\

1.3

1.2
1.1
102

-so

103

0
50
T.mperaluno (OC)

J 0.8
0.8

E
f!

Q.4

125°C

4.5

./

4.D

- --....-

...-

g
j

J

-SSoC

0.0

*8

:tl0 :t12 *14 *16
Power SUpply Voltage

3.5
3.0

0.1

l'-..

:t8

-*10

125°C
2SCC
-55°C

*12 *14 *16
Supply Vollage

*18

"

'JC=«JC CfW

" ""

1.5 Amble;;r-..
'JI,=7SCC!W
1.0

o.s

.......

"

..........

I

0.0

0

:t18

I
I

Ca

~

f:

25°C

Q.2

E
f!

125

s.o

1.0

Q.2

Maximum Power Dissipation

Turn On Time

1.2

!

g

/

1.8

lA

0.3

'\

frequency (11Hz)

6

Turn Off Time

1.81\.
1.7 \
1.8

103

Frequency (11Hz)

Termination VSWR

1./

1

- r-- -

Frequency (11Hz)

1.0 r0o-

10'

1

RL =504

Output Isolation
~

0,0,

100 125

+IJJ

3.0

-8

-12

1il'

60

Termination VSWR

4.0

Or--

-4

20

~

0

~

f

itil

-

100

«I~

6

4

J.-.-o

-I

Input to

80

60

~

12
8

Input to Input Isolation

90

so

~

3

4

10
15
Supply Voltago (+/- Volts)

i

~

8

-- ---

16

!

+125OC

i""""
5

103

Internal Termination
Resistance

s:

-SSOC

~ .......

-30

Frequency (11Hz)

70

g;JF

-so

-20

I

102

-60

25

50 15 100 125
Tempel8lure (OC)

150
TUK/9404-7

3-10

r-----------------------------------------------------------------------------~~

Leakage Current Equivalent Te.t Circuit

for ease of use. Thus for high frequency applications bypass
capacitors are not required, however, at low frequencies (10
MHz or less) a 4.7 Il-F bypass capacitor for each supply is
recommended.
Due to the unique design of the LH4266 it can easily be
used as a multiplexer or demultiplexer. In fact several units
can be connected to give a 1 to 4 multiplexer or a 4 to 1
demultiplexer by simply adding the required units as shown
in Figures 2 to 5.
The action of the switches can be seen in the following truth
table.

+5V

LH4266 Truth Table

TL/K/9404-11

·Same test for Input 2.

D

Pin 24
Input 2

Pin 13
Input 1

Low = 0

On

Off

High = 1

Off

On

Control

Teat Circuit for I.olatlon Input to Output
HP8753A

NETWORK
ANALYZER

Double Sided Board, Bottom Side

Input 1

lH4266

TLlK/9404-12

Applications Information, LH4266
The LH4266 uses hybrid technology to give increased circuit performance. In order to maintain its excellent cross
talk and feedthru specifications, proper RF grounding and
shielding should be incorporated in the printed circuit board
layout. For example; the input traces should not run next to
output traces and grounds should be provided by a ground
plane under the device (see Figure 1a, b for suggested PC
board layout).
The device contains two internal termination resistors and
switches. If termination of the non-selected input is desired,
connect the termination pin to the adjacement input pin and
the deselected input will be terminated with approximately

TL/K/9404-2

FIGURE 1a. LH4266, Recommended
Printed Circuit Board Layout
Double Sided Board, Top Side

500.
Note that the internal termination resistors are internally
connected to the device's ground pin. Thus If the internal
termination reSistors are used then the input ground planes
should remain isolated from the output ground plane (as in
Figure 1) so as not to form a ground loop. When using external termination resistors at the input, the resistors should be
connected to their respective ground planes, and, pin 16
should be tied to inputl's ground plane while pin 21 is tied
to input2's ground plane. Since pins 16 and 21 are internally
connected to the device ground pin, the input and output
ground planes should remain isolated. LH4266's power supplies are internally bypassed with high frequency capaCitors

TLlK/9404-13

FIGURE 1b. LH4266, Recommended
Printed Circuit Board Layout

3-11

...

:::E:

8i

~ 'r-------------------------------------------------------------~--------------,

~

'3....!:

Video Switch
, The lH4266 is ideally ~uited for video signal switching applications. Figure 7 shows 'how the LH4266 may be used to
select one of two video input signals while the LH4006 buffer allows driving four doubly terminated 750 cables.R1 biases the buffer's output to OV and prevents the output stage
from saturating when both switches are momentarily open.
Meanwhile, R2 eliminates the offset voltage caused by the
buffer's input bias current, and, a 10 pF capacitor across R2
prevents undesirable oscillations caused by stray capacitance at the buffers's inverting input. The circuit is capable
of producing ± 1V at the terminated ends of the 750 cables.
To maintain LH4266's excellent input to output isolation and
input to input crosstalk specifications; extreme care should
be exercised while laying out the printed circuit board. From
Figure 1's recommended printed circuit board layout it can
be observed that there are three separate ground planes.
Each input signal should be referenced to it's respective
ground plane while the output Signal, control signal and
power supplies are referenced to the output ground plane.
Note that LH4266's internal termination resistors are internally connected to the device's ground pin. Consequently, if
LH4266'sinternai termination re~istors are ,used then the
input and output ground planes should remain isolated (as
in Figure 1) so 'as to prevent a ground, loop from occurring.
When an,external termination resistor is used as in Figure 7,
the resistOr should be connected to its respective ground
plane, while pi'!116 is tied to inpuh's ground plane and pin
21 is tied to input2's ground plane. Moreover, all ground
planes should remain isolated because pins 16 and 21 are
internally connected to the device ground Pin.

TLlK/9404-5

FIGURE 4. 4 to 1 Multiplexer

Application Circuits, LH4266
TL/K/9404-6

FIGURE 5. 1 to 4 Demultiplexer
+15V

TL/K/9404-3

FIGURE 2. 2 to 1 Multiplexer
7

CONTROL

-15V

TLlKl9404-8

FIGURE 6. ATE Pin Driver SWItch
TL/K/9404-4

FIGURE 3: 1 to 2 Demult,plexer .:, '

3-12

7S.n

7S.n Transmission
L1n.s

INPUT l(ol~..!.:::f--o'
6

INPUT2@}"t-~~-o""",._.J
......._ _...J

LH4266
17

7S.n

Rl
1 k.n
20

-SV
+SV

CONTROL

7S.!l

+ISV -ISV

7S.n

=

Zo 7S.n

'Inpull GND Plane
"lnput2 GND Plane

TUK/9404- I 0

FIGURE 7, Video Switch

3-13

~National

~ Semiconductor

LM 1044 Analog Video Switch
General Description

Features

Primarily intended for, but not restricted to, the switching of
video signals, the LM1044 is a monolithic DC controlled an·
alog switch with buffered outputs, allowing the selection of
three 5 MHz bandwidth, 6 dB gain channels, or two
RGB + Sync, 30 MHz bandwidth, 0 dB gain channels. Chan·
nel selection is achieved via latched, TTL compatible, logic
inputs which may be controlled by microprocessor derived
signals. The device is supplied in a 24 pin dual in line plastic
package.

•
•
•
•
•
•

Wide RGB bandwidth, typically 30 MHz
High signal to noise ratio, typically 60 dB
Excellent channel Isolation typically -60 dB @ 5 MHz
High RGB output currents; typically 4 mA peak
RGB channels may be DC restored or clamped
Logically compatible with the LM1038 stereo audio
switch IC

Block Diagram
CVl I/P
CV2 liP
VW/l---11-+=2;.2 ENABLE

CV3 I/P

-1-_+1.:2:,:.1 CDNTROLA

Rl I/P
Gl I/P
Bl I/P

18 CLAMP KEY I/p

SYNC1 I/P
R21/P

>..-ri+-I-'"""i :>-~.,:1.:..7 RO/p

G21/P

:>........-+--1

B21/P

> ...._-t---1-:>_¥1~5 Bo/p
1,,;,.._.,:1..;..4 CV BIAS

SYNC2 liP
GND

:>-........,:1.::.6 GO/p

12

~_+1.::.3 RGB BIAS
(INTERNALLY SET)
TUH/9252-1

Order Number LM1044N
See NS Package Number N24A

3-14

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vs)
17V
Package Dissipation at TA = 25°C (Note B)
2.0W
Voltage at Control and Signal Inputs
-0.2Vto Vs +0.2V

10mA
2000V
O"Cto +70"C
- 65°C to + 15O"C
265°C
150"C

Output Current,123,117,116,115
ESD Susceptibility (Note 5)
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 sec.)
Junction Temperature

Electrical Characteristics Vs = 12V, RL = 6000, CL = 20pF, TA = 25°C unless otherwise stated
Parameter

TestUmlt
(NoteS)

Conditions

Supply Voltage, Vs
Supply Current

RGB1 Channel Selected
with No Input Signals Applied

Control Inputs Logic High Level
Control Inputs Logic Low Level

} Control Inputs A, B, C and
Enable Input

Enable Input Current, Pin 22

OVtoVs

Control Input Current

OV Logic Level
5V Logic Level

DealgnUmlt
(Note 7)

Units

Min

Max

Min

Typ

Max

B

16

B

12

1B

V

42

60

mA

O.B

V
V

2

10

tJ- A

20
250

50
500

tJ-A
tJ-A

5

7

1.5

1.7

60
2.0

2.0
O.B

Enable Pulse Width

5

Channel Select Time
COMPOSITE VIDEO CHANNELS

Inputs-Pins 1, 2, 3
Output-Pin 23

Maximum Input Voltage Swing

For Output THO

= 1"10 @ 1 kHz

tJ-s

1.2

Input Impedance

1.2

Dynamic Output Impedance

tJ-s

Vp-p

10

kO
0

Voltage Gain

Input Signal

= 0.5 Vp-p @ 100 kHz

5.3

5.3

5.B

Bandwidth

Input Signal

= 0.5 Vp-p, -3 dB,

4.0

4.0

5.0

MHz

60

dB

60

dB

-60

dB

= 5 MHz

Signal to Noise Ratio

Bandwidth

Channel Isolation (Note 1)

Input Signal

= 0.5 Vp_p @ 3 MHz
= 0.5 Vp_p @ 3 MHz

Crosstalk (Note 2)

Input Signal

Load Resistance (Note 3)

ACCoupled
DC Coupled to GND

Power Supply Rejection Ratio

Vs Modulated 1 Vp-p @ 1 kHz

600
2

CV Bias (Pin 14) Input Impedance

3-15

40

6.3

dB

0
kO
50

dB

1.0

kO

Electrical Characteristics
= 12V, RL = 6000, CL = 20 pF, TA = 25°C unless otherwise stated (Continued)

Vs

T.st Limit
Parameter

Conditions

Min
RGB CHANNELS
CLAMP INPUT·Pln 18
Minimum Input Voltage
Maximum InputVoltage
Input Current

O.slgn Limit
(Note 7)

(Note 6)

Max

Min

Typ

Inputs-Pins 4, 5, 6, B, 9,10
Outputs-Pins 15, 16, 17
For Clamp on
For Clamp off
. Pin 18

9

= OV

Clamp Pulse Delay (Note 4)

= 1% @1 kHz

Maximum Input Voltage Swing

for Output THD

Input Bias Current

Clamp off, Channel Selected

Bandwidth
Signal to Noise Ratio

AC Coupled 3 Vp•p
DC Coupled to GND

Channel Isolation (Note 1)

Input Signal

Crosstalk (Note 2)
Power Supply Rejection Ratio

Vs Modulated 1 Vp-p @1 kHz

p.A
p.s
Vp-p

20

-0.5

-0.5

6.0

24

Pin 13 Output Impedance

SYNC CHANNELS

Inputs-Pins 7,11
Outputs-Pin 23

Maximum Input Voltage Swing

for Output THD

= 1% @1 kHz

p.A

0

0
+0.5

30

MHz
dB
0
kO

60

dB

-50

dB

50

dB

60

0

Vp-p

1.8

2.3

-1.0

-1.0

-0.4

B.O

18

24

MHz

60

dB

Dynamic Output Impedance

2.B

kO

+0.2

dB

40

= 1 Vp•p @100kHz
Input Signal = 1 Vp•p, -3 dB,
RIN = 500, Bandwidth = 10 MHz
Input Signal

Nole 1: CV channels defined with a CV mute condition set up (ABC

dB

60

3.0

Input Impedance

Bandwidth

10
0.2

600
2

= 1 Vp-p @5 MHz
Input Signal = 1 Vp•p @5 MHz

Signal to Noise Ratio

V
V

20

= 1 Vp-p @100 kHz
Input Signal = 1 Vp-p, -3dB
RIN = 500, Bandwidth = 10 MHz
Input Signal

Load Resistance (Note 3)

Voltage Gain

5

3.0

Dynamic Output Impedance
Voltage Gain

Units
Max

0

= 001) and all CV Inpu\S driven. Isolation Is the output measured with respect to the Input laval

for RL of 600n. Channel Isolation for RGB channels is meaaured In the same way with signals applied to the R, G or B Inputs while a RGB mute condHion Is
selected.
Note 2: CV crosataJk measured with selactad channel Input AC grounded and with signal applied to the other CV Inputs. Resulting output voltage is measured with
RL of 600n. RGB crosstalk II measured Ilmllarly with slgnala applied to unselactad channel Inputs and meaauring the selected channel output. Note that high
frequency croaetalk measurements are very dependant on board layout An effective ground piane and Input to Input shleldlng are required.
Note 3: DC output currant 10uroad from device to load should not exceed 10 mA, care should be taken to avoid shorting outputs to GND.
Note 4: Delay between clamp pulse Input at Pin 16 and resulting clamping action as seen at RGB Inputs.
Note S: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 8: Guaranteed and 100% production teatad.
Note 7: Design limila are guaranteed to National's AOQl, but are not 100% production tested.
Note 8: When operating at elevated temperatures, the maximum power dissipation must be derated baaed on a maximum Junction temperatura of 15O"C and
8JA - 6O'C/W.

3·16

r-----------------------------------------------------------------------------,~

....a:::

Typical Performance Characteristics
Supply Current va
Supply Voltage

---

60

-

RG81 SELECI[I)

r--

4

6

8

12~+-~~-+-+,.(·0~~~

E

I

10

W

1--1--f--f--1-:6~:::::

P::::::C"'l:::::

~ 6~4--+~~~~0~~:~:~~;~~~~~:~~
to:::::::::::~

1:1

L

I

o

14~~~--r-~-r~

-

NO SIGNALS

t

CV Output Signal Range
va Supply Voltage

2~~~--~~~~

~

U

"

4

6

SUPPLY VOLAlGE (V)

8

W

~

U

8

"

CV Frequency Reapon..

RGB Frequency Reaponae

8

~

i=

2OPF

1

-2
0.1 D.2

0.5

1

2

5

lVp-p
RL = 6004

\

0.1

0.5 1 2

-8

rrl

0.5 1 2

FREOUENCY (MHz)

\

5 10 20 50

FREQUENCY (MHz)

CVand RGB Blaa
va Temperature

CV and RGB Blaa
va Supply Voltage
12

7"

i

0.1

5 10 20 50

7S

!~

1\

1 Vp-p
RL = 6004

rii

-8

10

FREOUENCY (MHz)

E

\
1\

\

6004

16

Sync Frequency Reaponse

1\

\
a.

14

.....

.........

RL

12

2

2

SOOmvp-p

10

SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

10

7.2

E

.......

711
1.8

0

20

60 80
TEllf'£RATURE ("1:)
«I

./

i

6

i

4

100

4

,/

/'

o

U
-20

./

8

\1!

6

8

W

U

~

"

SUPPLY VOLTAGE (V)
TLlH/9252-2

3·17

•

Application Notes

Pin Description
Now: The pin designations CV, R, G, B, and Sync are assigned for the convenience of, description and are not intended to be a limitation. For example RGB could be YUV,
or they could all be independent signal sour~.
Pin 1

Composite video input 1 (CV1), biased internally
via 1.8 kG to ~s + 1V.

Pin 2

Composite video input 2 (CV2), biased as for pin
1 (CV1) abOve.

PinS

Composite video input 3 (CV3), biased as for pin"
1 (CV1) above.

Pin 4

RGB input R1. This pin is internally biased via
a clamp circuitto ~s

+ 1V and should be AC

coupled to a low impedance source.
The input coupling capacitor also acts as a
clamp capacitor, see application notes.
Pin5

RGB input G1, biased as for pin 4 (R1) above.

Pin 6

RGB input B1, biased as for pin 4 (R1) above.

Pin7

Sync input 51, biased internally via 2.5k to
Vs + 1V
2
.,

Pin8

RGB input R2, biased as for pin 4 (R1) above.

Pin 9

RGB input G2, biased as for pin 4 (R1) above.

Pin 10

RGB input B2, biased as for pin 4 (R1) above.

Pin 11

Sync input 52, biased as for pin 7 (51) above.

Pin12

Negative supply (GND)

Pin 13

Connect a capaCitor to GND to decouple the
internal bias of the RGB amplifiers.

Pin 14

DEVICE DESCRIPTION
The LM1044 video switch circuit has a' configuration as iIIus'trated in F/{/ure 1 and consists of a 3 input to 1 output, 5
MHz switch with 6 dB gain, three 2 input to 1 output, 30
MHz, 0 dB gain switches, coupled together with a 2 input to
1 output switch sharing the 3 way switch output. All switch
stages are current switched differential amplifers with feedback, providing low impedance buffered outputs. Latched
logic inputs with control decoding are provided for switch
control and a DC clamp facility is available on the 30 MHz
channels.
The Principle application of this device is the selection between various composite video (CV) or Red, Green, and
Blue (RGB) sources now found in video systems using various signal sources, e.g., VCR's, satellite receivers, home
computers and video games. Other possible application examples, for example security camera switching, are shown
towards the end of these notes.
The 5 MHz channels are ideally suited for the switching of
composite video sources and have a gain of 6 dB to allow
amplification from terminated inputs back up to internal signallevels. The 30 MHz channels are suitable for direct RGB
inputs to display high quality graphics and will also handle
high quality linear Signals. The fourth switch channel shares
the CV output pin and is ideal for routing synchronization
, signals from the RGB/YUV sources into the path to the
sync separator and timebase circuits.
CHANNEL SELECTION
, The switch selections are made via the enable and 3 logic
control inputs, according to the truth table shown on the
following page. This gives a choice of 3 CV video Signal
sources or 2 RGB plus Sync signals on the video display.
tvl

Internal bias for the CV and Sync Amplifiers,
decouple with a capacitor to GND.

Pin 15

B Output.

Pin 16

G Output.

Pin 17

ROutput.

Pin 18

This is the clamp pulse input pin. A positive
going pulse activates the RGB input bias
clamps.
See application notes.

Pin 19

Channel select input, control C.

Pin 20

Channel select input, control B.

CV3

51
52

Channel select input, control A.

Pin 22

Enable input for control latches. Channel
selection is locked while this input is low and is
updated when high. The minimum enable pulse
width is 5 ","s.

Pin 23

CV output or Sync output when an RGB channel
is selected.

Pin 24

Supply pin (Vs). This pin should be well
decoupled at high frequencies, a 100 nF
capacitor connected close to the supply pins is
normally adequate.

>--+-R

Rl

R2

[3
IL

Pin 21

>""T-+- CV + 5

tv2

;;

>--+-G

Gl

G2

>--+-B

Bl
B2

BIAS

ENABC
TUH/9252-3

FIGURE 1
3-18

Application Notes (Continued)
Truth Table

provided the output remains within the output window. Note
this bias will also affect the voltage at pin 13.

Control Logic
EN

C

B

22

19

20

1

o

o
o
X

X

A
21

o
o
X

INPUT BIAS FOR RGB CHANNELS

Channel Selected

The 6 RGB inputs may be biased in one of three ways;
1) DC restored above an internal 4.5V level
2) Clamped to an internal 7V bias level
3) Driven directly with DC coupled signals

CV1, RGB Outputs Muted
CV2, RGB Outputs Muted
eV3, RGB Outputs Muted
RGBl with Syncl
RGB2 with Sync2
Mute
Mute
Mute
Previous selection retained

With an AC coupled input signal and the clamp pulse held
low the negative going peaks will DC restore to a level
greater than 3 diode drops below the reference bias level at
pin 13, typically 4.5V for Vs = 12V. The source resistance
of the diode restoring path is 1 kO for currents below
200 pA
Simplified Schematic of RGB Stage

The shaded section of the truth table indicates selection
compatible with the LM1038 four channel stereo audio
switch logic to give a possible selection of CV1 + Audiol,
eV2 + Audi02, eV3 + Audi03, RGBl + Audi04 and RGB2
+ Mute or Audi04; see Figure 3.
The mute conditions in the table correspond to disabled
ev /Sync (output pulled low) and high impedance RGB outputs which may be connected in parallel with other device
outputs for further expansion of the switch system. If all the
RGB inputs are being used to switch compOSite video signals then the RGB outputs can be connected into the ev
inputs to allow multiplexing down to 1 output from a large
number of input Signals.
LOGIC AND ENABLE INPUTS
If undriven the enable input will assume a high impedance
logic 1 condition and should be defined externally. The Logic selection inputs have internal pulldowns, typically 20 kO,
which will define logiC low levels if unconnected, giving eVl
in default of any other control input.

TUH/9252-6

The simplified schematic of the CV stage is virtually identical
to the RGB stage except that the CV stage does not incorporate the clamp cirCUitry.

INPUT BIAS FOR CV CHANNELS
The ev and Sync inputs are biased via Internal 1.5 kO and
2.3 kO resistors, respectively, to the internally generated 7V
bias (VS = 12V) level at pin 14. Input coupling capacitors
need to be chosen to give an adequate low frequency response when driving the 1.5 kO input impedance, for example, for less than 2% tilt on a frame rate waveform 330 p.F
will be required. Depending on the effectiveness of any following clamp circuitry the input coupling capacitors may be
reduced in value. These inputs may also be driven with DC
coupled Signals, provided the standing DC level is sufficiently near to 7V to maintain the output within the output signal
range (4.5 to 8.5V for Vs = 12VJ.

Clamping to the internal 7V bias is arranged by applying a
positive going clamp pulse to pin 18 during a time when the
input signals are at a black reference level. This is usually
during the back porch or during the blanking period of signals without syncs. The clamp pulse width should not be
less than 3 p.s. During the time pin 18 is high all six inputs
R1, R2, Gl, G2, B1 and B2 are connected to the RGB bias
voltage developed at pin 13, charging the input coupling
capaCitors to this level. These coupling capacitors are chosen to optimize value versus tilt introduced during the active
line period. A value of 330 p.F gives less than 1% tilt for
input currents less than 20 p.A. The effective impedance of
the clamp path when conducting is 3000. The voltage at pin
13 is a low impedance, 600, buffered version of the CV bias
voltage at pin 14 and decoupling is required to remove high
frequencies and maintain channel separation. The voltage
at pin 13 may be changed by driving pin 14 as described for
CV bias.

The bias at pin 14 has a DC output resistance typically of 1
kO and requires a decoupling capacitor to properly define
the gain and crosstalk. To ensure an adequate low frequency response this capacitor should be 100 p.F or more. This
pin may also be biased from an external voltage source

3-19

•

~

....

o.
.::1

Application Notes (Continued)

...I

OUTPUTS

CON'lROL
EN C 9 A

CLAIotPJL
PULSE

R

G

OUTPUT COUPLING
CAPACITORS TO
SUIT LOAD IIotPEDANCE

0/ AND SYNC INPUT
COUPLING CAPACITORS

=330~F

GND

RG9 INPUT COUPLING
AND CLAIotP CAPACITORS
330nF
.

=

0/1 0/2 0/3

Rl Gl 91 SI

INPUTS

INPUTS

R2 G2 92 S2
INPUTS
TUH/9252-7

FIGURE 2. LM1044 Basic Application Circuit

Relation of Clamp Pulse to Video

are such as to remain within the output window. Such sig·
nals could be. directly coupled from the RGB outputs of a
preceeding LM1044, avoiding the need for cOl!pling capaci·
tors WhEln expanding the switching capapility. External resis·
tive biasing to the bias voltage available at pin 13 may also
be used for a mean level bias with AC coupled sig·nals not
having reference levels.

--~----~-7V9~
~

.fLJl

OPERATION AT SUPPLIES OTHER THAN 12V

TLlH/9252-4

If the clamp pulse input is held low the RGB inputs may be
driven directly with DC coupled signals provided the levels

The LM1044 may be operated at supply voltages between
BVand 16V. Note that .the CV and RGB bias voltages, to·
gether with the clamp pulse threshold, will track with supply
variatic;ms whilst the logic input thresholds will remain essen·
tially constant. At lower supply voltages the signal handling
may beoptimi:ied with an external bias voltage to pin 14.

3-20

Application Notes (Continued)

CYI

r----+

I/O

TO SYNC PROCESSOR

CY2

R

CY3

B
OUTPUTS

G

Rl (.HI--.....--1

LUMINANCE"
CHROMINANCE
PROCESSOR

Gl (~H--.....--1
Bl

R2(~~---+--1c=~---~

G2 ( . H - -.....--1
B2

CLAMP

'-t-....- - - - - - - PIN 21 DATA

t--+-I-------- PIN 20 DATA
7511. VIDEO TERMINATIONS

t - I I - + - I - - - - - - - - PIN

19 DATA

(RGB 1)
BIAS

r:.,--++----L O/P

........r..IIo.I.....................

(CY 1)

(CY 2)

L.-_ _ _ _ _ R O!p

(CY 3)

TL/H/9252-5

FIGURE 3. LM1044 Application Circuit Showing System InterfaCing and LM1038

Iy -30 mV for CV and RGB channels. and -140 mV for
Sync channels.

OPERATION WITH SPLIT SUPPLIES
The LM1044 may be operated with split supplies with due
regard to the maximum supply voltage (16V) and output signal range. An example of operation in this way is illustrated
below. With ±5V and pin 14 held at OV the RGB outputs
can swing + 2V. -1.5V and the CV and Sync output can
swing + 1.3V. -1.3V. Similarly with +10V. -5V supplies.
pin 14 to OV. RGB output swings of + 5.5V. -1.5V and CVI
Sync swings of + 4.5V and -1.5V can be obtained. This
supply configuration has the advantage that pin 14 can be
grounded and all signals may be DC coupled avoiding the
need for coupling capacitors. Offsets introduced are typical-

OTHER APPLICATIONS
The LM1 044 can be used in other than the standard CV with
RGB circuit and an example is given below of a dual 6 input
to 1 output multiplexer for video or indeed any kind of signals up to 2 Vp-p. In this particular example the RGB outputs
are cross-coupled into the CV inputs of the other channel to
complete the multiplexing down to 2 outputs. The clamp
circuits are disabled to allow direct drive on the inputs. Such
circuits are ideal for security cameras and other multiple
video source monitoring systems.

3-21

•

Application Notes (Continued)
X2 VIDEO OUTPUTS FOR BUFFERING TO
CABLE OR DISPLAY ON MONITORS

Will

...........................................................................................
................................................................................. .........
..................................................................................
........ ..

100nF

6 LOGIC CONTROl. lilES FOR
SELEC110N OF INPUTS.

ENABLES WIRED .HIGH

12

FIGURE 4. Application Circuit Example U81ng Two LM1044 Devlce8 a8 a DualS Channel
Multiplexer and lIIu8trating U8e of Split Supplle8

3-22

r-------------------------------------------------------------------------,~

....iii:
o
....

~National

N

~ SemIconductor

LM1201 Video Amplifier System
General Description
The LM1201 is a wideband video amplifier system intended
for high resolution monochrome or RGB monitor applications. In addition to the wideband video amplifier the
LM1201 contains a gated differential input black level clamp
comparator for brightness control and an attenuator circuit
for contrast control. The LM1201 also contains a voltage
reference for the video input. For medium resolution RGB
color monitor applications also see the LM1203 Video Amplifier System data sheet.

Features
• Wideband video amplifier (200 MHz @ -3 dB)
• Attenuator circuit for contrast control (>40 dB range)
• Externally gated comparator for brightness control

• Provisions for external gain set and peaking of video
amplifier
• Video input voltage reference
• Low impedance output driver

Typical Applications
•
•
•
•
•
•
•

CRT video amplifiers
Video switches
High frequency video preamplifiers
Wideband gain controls
PC monitors
Workstations
Facsimile machines

• Printers

Block and Connection Diagram
VIDEO
IN

Vee 1

16

15

GNDI

ClAMP
CAP

CONTRAST CONTRAST
CAP
CAP
14

13

CONTRAST

Vee 2

DRIVE

Vee 3

12

11

10

9

GND 2

8
VIDEO

ClAMP

CLAMP (+)

GATE
FIGURE 1
Order Number LM1201M or LM1201N
See NS Package Number M16A or N16E

3-23

ClAMP (-)

OUT

TUH/l0006-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vcc Pins 10,12,15
to Ground Pins, 1, 7
13.5V
Voltage at Any Input Pin (VIN)
Vcc ~ VIN ~ GND
Video Output Current (Ie)
26mA
Package Power Dissipation at TA = 25·C
1.56W
(Above 25'C derate based on (9JA and TJ)
Package Thermal Resistance (9JA) N16E
60"C/W
Package Thermal Resistance (9JA) M16A
100"C/W

Junction Temperature (TJ)
150"C
Operating Temperature Range (TAl
O'Cto +70"C
-65·Cto + 150"C
Storage Temperature Range (TSlG)
265·C
Lead Temperature (Soldering, 10 sec.)
ESD Susceptibility
2kV
Human body model: 100 pF discharged through a 1.5 kG
resistor

Electrical Characteristics See Test Circuit (Figure 2), TA = 25'C; VCC1 = VCC2 = Vccs = 12V
DC Static Tests S9 Open; V4 = 6V; V5 = OV; V6 = 2.0V unless otherwise stated
Symbol

Parameter

Is

Suppiy Current

Vs

Video Input Reference Voltage

Conditions
Vcc Pins 12, 15 Only

Typical

Tested
Limit
(Note 1)

45

57

2.65

Design
Limit
(Note 2)

Units
(Limits)
mA(max)

2.4

V(min)

2.95

V(max)

i16

Video Input Bias Current

(VS-V16)/l0 kG

5.0

20

llA(max)

VSL

Clamp Gate Low Input Voltage

Clamp Comparator On

1.2

0.8

V(min)

VSH

Clamp Gate High Input Voltage

Clamp Comparator Off

ISL

Clamp Gate Low Input Current

Vs

ISH

Clamp Gate High Input Current

12+

Clamp Cap Charge Current

12-

Clamp Cap Discharge Current

VeL

Video Output Low Voltage

VeH

Video Output High Voltage

= OV
V5 = 12V
V2 = OV
V2 = 5V
V2 = OV
V2 = 5V

VOS

Comparator Input Offset Voltage

V6-V9

1.6

2.0

V(max)

-0.5

-5.0

llA(max)

0.005

1

,.A(max)

1

0.55

mA(min)

-1

-0.55

mA(min)

0.5

0.9

V(max)

8.5

8.0

V(min)

±0.5

±25

mV(max)

AC Dynamic Tests S9 Closed, V5 = ov, V6 = 4V
Symbol

Parameter

Conditions

= 12V

Avmax

Video Amplifier Gain

V4

t:.Av5V

Attenuation @ 5V

Ref: Av max, V4

t:.Av2V

Attenuation

Ref: Av max, V4

THO

Video Amplifier Distortion

@

2V

f(-3dB)

Video Amplifier Bandwidth (Note 3)

tr

Output Rise Time (Note 3)

tf

Output Fall Time (Note 3)

= 5V
= 2V

= 5V, Vo = 1 Vp-p
V4 = 12V, Vo = 100 mVrms
Vo = 4Vp_p
Vo = 4Vp-p
V4

Typ

Tested
Limit (Note 1)

8

5.5

Design
Limit (Note 2)

Units
(Limits)
VIV(min)

-10

dB

-45

dB

0.3

%

200

170

MHz(min)

2.5

ns

3

ns

Note 1: lhess parameters are guaranteed and 100% production _ed.
Note 2: Oaalgn IImHs are guaranteed (but not 100% production tasted). Theas limits are not ussd to calculate outgoing quality lavels.
Note 3: When measuring video ampllHar bandwidth or pulss riss and fall times, a double sided lull ground plane printed clrcuH board wHhoutsockal I. recommended.

3-24

Yee

r-------~~-------.----~~----.-{J+12Y

R9

LIoI1201 D.U.T.

10k

YOUT

TLlH/l0006-2

FIGURE 2. LM1201 AC/DC Test Circuit
Nole: When Vs <: O.SV and 89 is closed. DC feedback around the Video Amplifier is provided by the clamp comparator. Under these condHlons sine wave or 50%
duty cycle square waves can ba used for test purposes. The low frequency dominant pole is determined by C2 at Pin 2. capacitor C8 at pin 9 prevents overloading
the clamp comparator Inverting Input. See applications secUon lor additional Inlormatlon.

Vee

.12Y
Video
In 10 ...
P,F

10k

* __O.,.II'F ~

~r~"
W

HV

.60V

Bright....
Control

10

15

Gl
LM120t

&I
GND

33011

DIE
5.1k
43k
tODD pF

TL/HI10006-3

FIGURE 3. Typical Application of the LM1201
• 30n resistor Is added to the Input pin for protection against current surges coming Irom the 10 p,F input capacitor. By Increasing this resistor to wall over loon
the rise and fall times of the LMI201 can be incnsased for EMI considerations.

3-25

~ r---~~-----------------------------------------------------------------------------------,

re
~

::IE

...I

APPLICATIONS INFORMATION
Figure 4 shows the block diagram of a typical analog monochrome monitor. The monitor is used with CAD/CAM work
stations, PCs, arcade games and in a wide range of other
applications that benefit from the use of high resolution display terminals. Monitor characteristics may differ in such
ways as sweep rates, screen size, or in video amplifier
speed but will still be generally configured as shown in Figure 4. Separate horizontal and vertical sync signals may be
required or they may be contained as a composite Signal in
the video input signal. The video input Signal is usually

Sync In

V0-11---1

Ho-II---I

supplied by coaxial cable which is terminated in 750 at the
monitor input and internally AC coupled to the video amplifier. The input signal is approximately 1V peak-to-peak in amplitude and at the input of the high voltage video section,
approximately 6V peak-to-peak. At the cathOde of the CRT
the video Signals can be as high as 60V peak to peak. The
block in Figure 4 labeled "Video Amplification with DC Controlled Gain/Black Level" contains the function of the
LM1201 video amplifier system.

VERTICAL/HORIZONTAl SWEEP
AND POWER SUPPLY
CIRCUITS

Video In

Contrast

TUH/10006-4

FIGURE 4. Typical Monochrome Monitor Block Diagram

3-26

Circuit Description
F/gure 5 Is a block diagram of the LM1201 along with the

to pin 16 via the 10 /A-F coupling capaCitor. DC bias to the
video input is through the 10 kO resistor which is connected
to the 2.6V reference at pin 3. The low frequency roll-off of
the amplifier is set by these two components. Transistor 01
buffers the video signal to the base of 02. The 02 collector
current is then directed to the VCCl supply through 03 or to
VCC2 through 04 and the 5000 load resistor depending
upon the differential DC voltage at the bases of 03 and 04.
The 03 and 04 differential base voltage is determined by
the contrast control circuit which is described below. The
black level DC voltage at the collector of 04 is maintained
by 05 and 06 which are part of the black level clamp circuit
also described below. The video signal appearing at the collector of 04 is then buffered by 07 and level shifted down
by Z1 and 08 to the base of 09 which will then provide
additional system gain.

contrast and brightness controls. The contrast control is a
DC operated attenuator which varies the AC gain of the
amplifier without introducing any signal distortions or DC
output shift. The brightness control function requires a
"sample and hold" circuit (black level clamp) which holds
the DC bias of the video amplifier and CRT cathodes constant during the black level reference portion of the video
waveform. The clamp comparator, when gated on during
this reference period, will charge or discharge the clamp
capacitor until the non-inverting input of the clamp comparator matches that of the Inverting input voltage which was set
by the brightness control.
F/gure 6 Is a simplified schematic of the LM1201 video amplifier along with the recommended external components.
The IC pin numbers are Circled with all external components
shown outaide of the dashed line. The video input is applied

Clamp Gate

Lr' -------'

TL/H/10006-5

FIGURE 5. Block Diagram of LM201 Video Amplifier with Contrast and Black Level Control

•
3-27

LM1201

o

~"

C

;::;

c

CD
OJ

+12VO

•

• •

n
""'I

•

-

-6"

~3

----------------------~~

0"

:::s
~
:::>

HV

RIO
5004

CI:

:::>

!

504

;

In
VIdeo

=r

754

LV

lO

}oF

10k

-------1-'-----W----------o;;8-Clf
O.I}OF

'V

..LClamp
Cap

To Clamp
Comparator

(-) Input

=£·1~

FIGURE 6. SimplHied LM1201 Video Amplifier Section with Recommended External Components

or ~

•

To Clamp
Comparator
(+) Input
TUH/l0006-6

Circuit Description

(Continued)

The "Drive" pin will allow the user to set the maximum gain
of the amplifier based on the range of input video signal
levels and the CRT stage gain if it is fixed or limited. When
using three LM1201 devices for high resolution RGB applications, the "Drive" pin allows the user to trim the gain of
each channel to correct for differences in the three CRT
cathodes. A small capacitor (12 pF) in shunt with a 510
drive resistor at this pin will extend the high frequency gain
of the video amplifier by compensating for some of the internal high frequency roll off. The 510 resistor will set the system gain to approximately 8 or 18 dB. The video signal at
the collector of 09 is buffered and level shifted down by
010 and 011 to the base of the output emitter follower 012.
Between the emitter of 012 and the video output pin is a
500 resistor which is included to prevent spurious oscillations when driving capacitive loads. An external emitter resistor must be added between the video output pin and
ground. The value of this resistor should not be less than
3300, otherwise package power limitations may be exceeded when worst case (high supply, max supply current, max
temp) calculations are made. If negative going pulse slewing
is a problem because of high capacitive loads (> 10 pF), a
more efficient method of emitter pull down would be to connect a suitable resistor to a negative supply voltage. This
has the effect of a current source pull down when the minus
supply voltage is -12V, and the emitter current is approximately 10 mA. The system gain will also increase slightly
because less signal will be lost across the internal 500 resistor. Precautions must be taken to prevent the video

output pin from going below ground since IC substrate currents may cause erratic operation. The collector current
from the video output transistor is returned to the power
supply at VCC3, pin 10. When making power dissipation calculations note that the datasheet specifies only the VCCI
and Vee2 supply currents at 12V. The IC power dissipation
contribution of VCC3 is dependent upon the video output
emitter pull down load.

•

In normal operation the minimum black level voltage that
can be set at the video output pin is approximately 2V at
maximum contrast setting. In applications that require a lower black level voltage, a resistor (approximately 16 kO) can
be added from pin 3 to ground. This has the effect of raising
the DC voltage at the collector of 04 which will extend the
range of the black level clamp by allowing 05 to remain
active. In applications that require video amplifier shutdown
due to fault conditions detected by monitor protection circuits, pin 3 and the wiper arms of the contrast and brightness controls can be grounded without harming the IC. This
assumes some series resistance between the top of the
control potentiometers and Vee.
Figure 7 shows the internal construction of the pin 3 2.6V
reference circuit which is used to provide temperature and
supply voltage tracking compensation for the video amplifier
input The value of the external DC biasing resistors should
not be larger than 10 kO when using more than one
LM1201 (e.g. in RGB systems) because minor differences in
input bias currents on the individual video amplifiers may
cause offsets in gain.

12 V_______________
•
cc2
I
I
I

I
I
I
I

I

to Video Input
10k

10k

t--¥iIv--t--{ Joo-....'""""""i~ Contrast
Control

•
TL/H/10006-7

FIGURE 7. LM1201 Video Input Voltage Reference and Contrast Control Circuits

3-29

~

~
~

~

r-------------------------------------------------------------------------------------;
Circuit Description (Continued)
Figure 7 all$Oshows how the contrast control circuit is configured. Resistors R23. R24. diodes 03. 04. and transistor
013 are used to establish a low impedance zero TC half
supply voltage reference at the base of 014. The differential
amplifier formed by 015. 016 and feedback transistor 017
along with resistors R27. R28 establish a differential base
voltage for 03 and 04 In Figure 6. When externally adding
or subtracting current from the collector of 016. a new differential voltage is generated that reflects the change in the
ratio of currents in 015 and 016. To provide voltage control
of the 016 current. resistor R29 is added between the 016
collector and pin 4. A capaCitor should be added from pin 4
to ground to prevent noise from the contrast control pot
from entering the IC.
Figure 8 is,a.simplified schematic of the clamp gate and
clamp comparator section of the LM1201. The clamp gate
circuit consists of a PNP input buffer transistor (018). a PNP
emitter coupled pair referenced on one side to 2.1V (019.
020) and an output switch (021). When the clamp gate
Input at pin 5 is high (>1.5V). the 021 switch is on and

shunts the 11 1mA current to ground. When pin 5 is low
«1.3V). the 021 switch is off and the 11 1mA current
source Is mirrored or "turned around" by reference diode
05 and 026 to provide a 1mA current source for the clamp
comparator. The inputs to the comparator are similar to the
clamp gate input except that an NPN emitter coupled pair Is
used to control the current which will charge or discharge
the clamp capaCitor at pin 2. PNP transistors are used at the
inputs because they offer a number of advantages over
NPNs. PNPs will operate with base voltages at or near
ground and will usually have a greater reverse emitter-base
breakdown voltage (BVebo). Because the differential input
voltage to the clamp comparator during the video scan period could be greater than the BVebo of NPN transistors.
resistor R34 with a value one half that of R33 or R35 is
connected between the bases of 023 and 027. This resistor will limit the maximum differential input to 024. 025 to
approximately 350 mV. The clamp comparator common
mode range extends from ground to approximately 9V and
the maximum differential input voltage is Vee and ground.

Vr;c2
+Icllmp

Clamp

Gat.
In

TL/H/l0006-8

FIGURE 8. Simplified SchematiC of LM1201 Clamp Gate and Clamp Comparator Circuits

3-30

Applications Information
Figure 9 shows the configuration of a high frequency amplifier with non-gated DC feedback. Pin 5 is tied low to turn on
the clamp comparator (feedback amplifier). The inverting input (pin 9) is connected to the amplifier output from a low

pass filter. Additional low frequency filtering is provided by
the clamp capaCitor. The Drive pin is grounded to allow for
the widest range of output signals. Maximum output swing is
achieved when the DC output is set to approximately 4.5V.

Vee

~-.------~~------t--t----------t-~-lJ+12V

0.1 PF~

47pF ~

15

LM1201

10k

2

0.1 pF

~0.1 pF

10

5

3

10k

7

6

~ ~______________.......
+12V

+12V

GND

330n

TUH/l0006-9

FIGURE 9. High Frequency Amplifierl Attenuator Circuit with Non-Gateci DC Feedback (Non-Video Appllcatlona)

3-31

.- r-------------------------------------------------------------------------------------,
~
.~

Applications Information (Continued)
Figure 10 shows the LM1201set up as a video amplifier
with biphase outputs. Because the collector of output transistor Q12 is the only internal connection to Vcca, a 750
termination to the power supply voltage allows one to obtain
inverted video at pin 10. Black level on the non-inverted
video output (pin 8) is set to 1.5V by the voltage divider on
pin 6.

be OR'ed together assuming no more than one channel is
selected at any given time. Channel selection is accomplished by keeping the appropriate SELECT SWITCH open.
Closing the SELECT SWITCH on a given channel disables
that channel's output (pin 8) leaving it in a high impedance
state. A single pair of contrast and brightness potentiometers control the selected channel's gain and output DC
level.

Figure 11 shows how a high frequency video switch may be
designed using multiple LM1201 devices. All outputs can

,......_ _ _ _ _........-(~) Vee

,. . . . . . ---..JVVtv----..........
20011.

O.II'F
O.II'F

15

T
V

+12V
..._ _ _-40 dB range)
• OV to 4V high input impedance DC drive control
(±3 dB range)
• Easy to parallel three LM1202s for optimum color tracking in RGB systems
• Output stage clamps to 0.65V and provides up to 9V
output voltage swing
• Output stage directly drives most hybrid or discrete
CRT amplifier stages

Applications
High resolution CRT monitors
Video switches
Video AGC amplifier
Wideband amplifier with gain and DC offset control

• Wideband video amplifier
(f -3dS = 230 MHz at Vo = 4 Vpp)
• 1,-, tl = 1.5 ns at Vo = 4 Vpp

Block and Connection Diagram

ATTENUATOR IN+

1

ATTENUATOR IN-

2

I---------.....J
I------------...J

3

1----------,

CLAMP CAP

CONTROL OUT+
CONTROL OUT-

CLAMP(+)
CLAMP(-)
SYSTEM Vee 1

CONTRAST CONTROL
ORIVE CONTROL

[!]
8
9

1-----------..1
1-_________________---.1

CLAMP GATE
GROUND

'TUH/11440-1

Order Number LM1202N or LM1202M
See NS Package Number N20A or M20B

3-36

Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee Pins 4,7, 16 to
Ground Pins 5,13,15
Voltage at Any Input Pin (VIN)

Junction Temperature (TJ)
Lead Temperature
N Package (Soldering, 10 sec.)

13.5V
28mA

Package Power Dissipation at TA = 25°C
(Above 25°C Derate Based 6JA and TJ)

1.56W

Package Thermal Resistance (6JN
N20A
M20B

Operating Ratings

1.5kV

(Note 2)
- 20°C to + 800C
8V ,;; Vee';; 13.2V

Temperature Range
68°C/W
900C/W

+ 1500C
265°C

ESD Susceptibility
Human Body Model: 100 pF Discharged
through a 1.5k Resistor

Vee ;;;: VIN ;;;: GND

Video Output Current (117)

1500C
-65°C to

Storage Temperature Range (Tslg)

Supply Voltage (Vecl

DC Electrical Characteristics See Test Circuit (Figure 1), TA = 25°C, V4 = V7 = V16 = 12V, S1 Open,
V19 = 4V, V8 = 4V, V9 = 4V, V14 = OV unless otherwise noted.
Symbol

Parameter

Conditions

Typical
(Note 3)

Limit
(Note 4)

Units

48

60

mA(max)

2.4

2

V (min)

Is4, 7,16

Total Supply Current

V6

Video Input Bias Voltage

V14L

Clamp Gate Low Input Voltage

Clamp Comparator On

0.8

V (max)

V14H

Clamp Gate High Input Voltage

Clamp Comparator Off

2

V (min)

114L

Clamp Gate Low Input Current

V14 = OV

-0.5

114H

Clamp Gate High Input Current

V14 = 12V

0.005

112+

Clamp Cap Charge Current

V12 = OV

800

500

/LA (min)

112-

Clamp Cap Discharge Current

V12 = 5V

-800

-500

p.A (min)

V17L

Video Output Low Voltage

V12 = OV

0.2

0.65

V (max)

V17H

Video Output High Voltage

V12 = 6V

10

9

V (min)

Vas

Comparator Input Offset Voltage

V1S - V19

15

±50

mV(max)

RLoad =

00

(Note 5)

/LA
/LA

AC Electrical Characteristics See Test Circuit (Figure 1), TA = 25°C, V4 = V7 = V16 = 12V, S1 Closed,
V19 = 4V, V8 = 4V, V9 = 4V, V14 = OV unless otherwise noted.
Symbol

Parameter

Conditions

Typical
(Note 3)

Limit
(Note 4)

Units

16

V/V(min)

-38

-23

dB (min)

RIN

Video Amplifier Input Resistance

fiN = 12 kHz

20

Av max

Video Amplifier Gain

Vs = 4V. Vg = 4V

20

I1Av2V

Attenuation at 2V

Ref: Av max, Vs = 2V

-6

kO

dB

I1AvO.5V

Attenuation at 0.5V

Ref: Av max, Vs = 0.5V

11 Drive

11 Gain Range

V9 = OVt04V

6

5

dB (min)

THD

Video Amplifier Distortion

Va = 4 Vpp, fiN = 12 kHz

0.5

1

% (max)

f-3dB

Video Amplifier Bandwidth (Note 6)

Va = 4Vpp

230
2

ns(max)

2

ns(max)

t,.

Output Rise Time (Note 6)

Va = 4Vpp

1.5

t,

Output Fall Time (Note 6)

Va = 4Vpp

1.5

3·37

MHz

&I

Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note'2: Operating Ratings indicate condHlons for which the device is functional but do not guarantee specific performance limits. For guaranteed epecifications and
test conditions 888 the Electrical Characterlalics. The guaranteed specifications apply only for the teat conditions listed. Some performance characteriatioa may
degrade when the device is not operated under the listed teat condHlon8.
Note 3: Typical 8pecifications are speclfled at + 25'C and rapreeentthe moat likely peramatric norm.
Note 4: Tested limite are guaranteed 10 National's AOQL (Average Outgoing Quality Level).
Note S: The supply current apeciiied is the quie8C8nt current for VCC1, VCC2 and VCC3 wHh RLoad - .. , 888 FIgure
circuit The totel supply current alsO
depend8 on the output load, RLood. The increase In device power dlaalpetlon due 10 RLoad must be teken Into aooount when operating the devlca at the maximum
ambient temperature.

"s _

Note 8: When measu~ng video amplHler bandwidth or pulee riee and fali times, a double sided full ground plane printed circuH board Is recommended. The
measured rise and fali times are effective nee and fall times, taking Into acccuntthe riee and fali times of the genenator and the oacilloeccpe.

Test Circuit
100

VIDEO

Vee (+12V)

OUT

Vee (+12V)

LM1202
TOP VIEW

VIDEO
IN

51

CLAMP GATE

Uk

(4V)

iN
1OOk ~"'I--...--1

lOOk ~"'I-----4"-'-I

DRIV[ CAP 0.01 p.F
TLlH111401O-2

FIGURE 1. LM1202 Te.t Circuit

3-38

r-----------------------------------------------------------------------------,
Typical Performance Characteristics (Vee =

12V, TA = 25"C unless otherwise specifiedj

Quiescent Supply Current vs Supply Voltage

55

......

50

...
::>

......
....

45

>-

40

::>

III

35

V

V

""

/

~

V

--"

/

V

./

-I

V"

....e2

-3

,/'

::>

...
S

~

/

Ii' -2
3
z
z

-4
-5

./

-6

o

7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5

, ./

0.5

SUPPLY VOLTAGE PINS 4, 7 AND 16 (V)

/

/

1.0

1.5

2.0

2.5

3.0

3.5

TLlH/II440-13

Contrast vs Frequency

Drive vs Frequency

10

0.54V

.3

.

Iii
.., -30

!Z

"

~~
-" ~"'

l..--'

0.9V

-50

0.40V

~

0.33V
0.27V

i-"l'

Vg

=lv

~'"

-90
I

dv
I
I

I

ov

I

I

-1

10

100

1/ ,

,.

I

~

Vg =4V

-70

-

Iva =4V

V8 -4V

-10

4.0

DRIVE CONTROL (PIN 9) VOLTAGE

TLlH/I1440-12

8
"z
:c

2

Attenuation vs Drive Control Voltage

30

~

~

~OAD~J

60

'<
.5
....
z

~

...

1

400

FREQUENCY (MHz)

10

,.~

,.

'"

1/

I"
1/

1\
100

400

FREQUENCY (MHz)
TLlHI11440-14

TLlH/II440-15

&I

Attenuation vs Contrast
Control Voltage
10

o

I-

"iii" -10

..,

~

-20

~

-30

z

-40

::>

5

/

.- . "

-

-50
-60
-70

V
o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

CONTRAST CONTROL (PIN 8) VOLTAGE

3-39

TL/HI11440-16

Circuit Description
voltage at the minus input of the comparator matches the
voltage set at the plus Input of the comparator. During the
video portion of the Signal, the clamp comparator is disabled
and the clamp capaCitor holds the proper DC bias. In a DC
coupled cathode drive application, picture brightness function can be achieved by varying the voltage at the comparator's plus input. Note that the back porch clamp pulse width
(tw in Figure 2) must be greater than 100 ns for proper
operation.

Figure 2 shows a block diagram of the LM1202 video amplifier along with contrast and brightness (black level) control.
Contrast control is a DC-operated attenuator which varies
the AC gain of the amplifier. Signal attenuation (contrast) is
achieved by varying the base drive to a differential pair and
thereby unbalancing the current through the differential pair.
As shown in Figure 2, pin 20 provides a 5.3V bias voltage for
the positive input of the attenuator (pin 1). Pin 3 provides a
control voltage for the negative input (pin 2) of the attenuator. The voltage at pin 3 varies as the voltage at the contrast
control input (pin 8) varies thus providing signal attenuation.
The gain is maximum (0 dB attenuation) if the voltage at pin
8 is 4V and is minimum (maximum attenuation) if the voltage
at pin 8 is OV. The OV to 4V DC-operated drive control at pin
9 provides a 6 dB gain adjustment range. This feature is
necessary for RGB applications where independent gain adjustment of each channel is required.

VIDEO AMPLIFIER SECTION (Input Stage)
A simplified schematic of LM1202's video amplifier input
stage is shown in Figure 3. The 5.4V zener diode, 01, 06
and R2 bias the base of 07 at 2.6V. The AC coupled video
signal applied to pin 6 is referenced to the 2.6V bias voltage.
Transistor 07 buffers the video signal, VIN, and 08 converts
the voltage to current. The AC collector current through 08
is Ica = VIN/R9. Under maximum gain condition, transistors
09 and 011 are off and all of Ica flows through the load
resistors R10 and R11. The maximum Signal gain at the
base of 013 is, AV1 = -(R10 + R11)/R9 = -2. Signal
attenuation is achieved by varying the base drive to the differential pairs 09, 010 and 011, 012 thereby unbalancing
the collector currents through the transistor pairs. Base of
010 is biased at 5.3V by externally connecting pin 1 to pin
20 through a 100n resistor. Pin 2 is connected to pin 3
through a 100n resistor. Adjusting the contrast voltage at

The brightness or black level clamping requires a "sample
and hold" circuit which holds the DC bias of the video amplifier constant during the black level reference portion of the
video waveform. Black level clamping, often referred to as
DC restoration, is accomplished by applying a back porch
clamp signal to the clamp gate input pin (pin 14). The clamp
comparator is enabled when the clamp signal goes low during the black level reference period (see Figure 2). When
the clamp comparator is enabled, the clamp capacitor connected to pin 12 is either charged or discharged until the

T

VIDEOIN CI

RI
75

10)lf

C2
O.OI)lf

RIO
510

+4V

WHITE

-

BLACK

I-- BLACK LEVEL REfERENCE PERIOD
BACK PORCH CLAMP SIGNAL

U

--l I-- to, > 100 n.

U

r------~:·~~~O~H=~~I~.8~V______~
VOL::50.8V_U

TLlH/II440-3

FIGURE 2. Block Diagram of the LM1202 Video Amplifier
with Contraat and Brightness (Black Level) Control

340

Circuit Description (Continued)
pin 8 produces a control voltage at pin 3 which drives the
base of 09. By varying the voltage at the base of 09, 08's
collector current (Ice) is diverted away from the load resistors A 10 and A 11, thereby providing signal attenuation.
Maximum attenuation is achieved when all of Ice flows
through 09 and no current flows through the load resistors.

The differential pair 011 and 012 provide drive control.
012's base is internally biased at 7.3V. Adjusting the voltage at the drive control input (pin 9) produces a control
voltage at the base of 011. With 09 off and 012 off, all of
Ice flows through R10, thus providing a gain of AV1 =
-(R10/R9) X VIN = -1. Drive control thus provides a
6 dB attenuation range.
SYSTEM Vee

Vee

-----------------------.
PUSH PULL CURRENT
FROM CLAMP
COMPARATOR

, - -.....- - 1 -......- -......- - ,
Rl
45k

CLAMP

CAP

R2
1.2k
R3

200

R4
20k
RIB
Uk
TO VIDEO AMP
OUTPUT STAGE
TO Q19

Q8

R7
200

1.0V
S.4V

Zen"

._----------

Re

R5
Uk

R8
3k

------

--------------------- -------------------

5

6

GROUND

VIDEO INPUT

R14
100

500

CONTRAST CAP

R15
100

II

GROUND

TL/H/11440-4

FIGURE 3. Slmp"fled Schematic of the LM1202 Video Amp"fler Input Stage

3-41

Circuit Description (Continued)
and 040. 040's base is internally biased at 5.3V and made
available at pin 20. Pin 20 is externally connected to pin 1
through a 1000 resistor (see Figures 2 and 3). The base of
038 (pin 3) is externally connected to pin 2 through a 1000
resistor (see Figures 2 and 3). With Veont = 2V, the differential pair (038, 040) is balanced and the voltage at pins 1
and 2 is 5.3V. Under this condition, 08's collector current is
equally split between 09 and 010 (see Figure 3) and the
amplifier's gain is half the maximum gain. If contrast voltage
at pin 8 is greater than 2V then 036's collector current
increases, thus pulling 038's collector node lower and
consequently moving 038's base below 5.3V. With pin 2
at a lower voltage than pin 1, current through 010 (see
F/{/Ure 3) increases and the amplifier's gain increases. With
Veont = 4V, the amplifier'S gain is maximum.
If the contrast voltage at pin 8 is less than 2V then 036's
collector current decreases and 038's base is pulled above
5.3V. With pin 2 voltage greater than pin 1 voltage, less
current flows through 010 (see Figure 3), consequently the
amplifier's gain decreases. With Veont = OV, the amplifier's
gain is minimum (i.e., maximum attenuation).

VIDEO AMPLIFIER SECTION (Output Stage)
A simplified schematic of lM1202's video amplifier output
stage is shown in F/{Jure 4. The output stage is the second
gain stage. Ideally the gain of the second gain stage would
be AV2 = -R21/R18 = -16. Because of the output
stage's low open loop gain, the gain is approximately
AV2 = -10. Thus the maximum gain of the video amplifier
is Av = AVI X AV2 = 20. Transistors 023 and 024 provide
a push-pull drive to the load. The output voltage can swing
from 0.2V to 10V.

CONTRAST CONTROL SECTION
A simplified schematic of lM1202's contrast control section
is shown in Figure 5. A OV to 4V DC voltage is applied at the
contrast input (pin 8). Transistors 029, 030 and 034 buffer
and level shift the contrast voltage to the base of 036. The
voltage at the emitter of 036 equals the contrast voltage
(Vcont> and the current through 036's collector is given by
1C36 = Veont/R28.
Transistor 036's collector current is used to unbalance the
current through the differential pair comprised of 038

p----------------------------Vee
r-----t-~~....:::.-.....- - -...._i__C 16
R24

Vee

lk

Q23

.....--'--f 17

VIDEO OUTPUT

R17

aoo

---------------------------- ..

FIGURE 4. Simplified Schematic of LM1202 Video Amplifier Output Stage

3-42

TL/H/11440-5

n

a

c::;:

p-------------------------------------------------------------------------. ::c
Vee

R25
50k

n

R30
2k

-

:::!.
'a

R32
9.4k

0"

::J

i

::I

1
S.3V
BIAS
c.>

R31
50

b

5.4V
Zener

R27
100

R34
50

R29
10k

R33

R36
10k

8.8k

R37

12k

.-------------.-----------------------------.-------------.--------------8

3

20

CONTRAST CONTROL INPUT
TLlHI11440-6

FIGURE 5. Simplified Schematic of LM1202 Contrast Control

..,

~o~u

iii

Nr-------------------------------------------------------------------~

....~

~

Circuit Description (Continued)
DRIVE CONTROL SECTION

CLAMP GATE AND CLAMP COMPARATOR SECTION

A simplified schematic of the LM1202's drive control section
is shown in Figure 6. A OV to 4V DC voltage is applied at
the drive control input (pin 9). Transistors 049, 050 and
054 buffer and level shift the contrast voltage to the base of
056. The voltage at the emitter of 056 equals the drive
voltage, Vdrive and the current through 056's collector is
given by IC56 = V drive/R43.
Transistor 056's collector current is used to unbalance the
current through the differential pair comprised of 058 and
060. 060's base is internally biased at 7.3V and connected
to the base of 012 (see Figure 3). 058's base is internally
connected to the base of 011 (see Figure 3). With Vcont =
2V, the differential pair (058, 060) is balanced and the voltage at the bases of 011 and 012 is 7.3V. Under this condition, 010's collector current is equally split between 011
and 012 (see Rgure 3). If the drive voltage at pin 9 is greater than 2V then 056's collector current increases, thus pulling 058's collector node lower and consequently moving
058's base below 7.3V. With base of 011 below 7.3V, current through 012 (see Figure 3) increases and the amplifier's gain increases. With Vdrive = 4V, the amplifier'S gain is
maximum under maximum contrast condition (i.e., Vcont =
4V).

Figures 7 and 8 show simplified schematics of the clamp
gate and clamp comparator circuits. The clamp gate circuit
(Figure 7) consists of a PNP input buffer transistor (082), a
PNP emitter coupled pair (085 and 086) referenced on one
side to 2.1 V and an output switch transistor 089. When the
clamp gate input at pin 14 is high (> 1.5V) the 089 switch is
on and shunts the 200 IIA current from current source 090
to ground. When pin 14 is low « 1.3V) the 089 switch is off
and the 200 /LA current is mirrored by the current mirror
comprised of 091 and 075 (see Figure 8). Consequently
the clamp comparator comprised of the differential pair 074
and 077 is enabled. The input of the clamp comparator is
similar to the clamp gate except that an NPN emitter coupled pair is used to control the current that will charge or
discharge the clamp capacitor externally connected from
pin ·12 to ground. PNP transistors are used at the inputs
because they offer a number of .advantages over NPNs.
PNPs will operate with base voltages at or near ground and
will usually have a greater emitter base breakdown voltage
(BVebo). Because the differential input voltage to the clamp
comparator during the video scan period could be greater
than the BVebo of NPN transistors, a resistor (R63) with a
value one half that of Reo or R68 is connected between the
bases of 071 and 079. The clamp comparator's common
mode range is from ground to approximately 9V and the
maximum differential input voltage is Vcc.

If the drive voltage at pin 8 is less than 2V then 056's collector current decreases and 058's base is pulled above
7.3V. With base of 011 greater than 7.3V, less current flows
through 012 (see Figure 3), consequently the amplifier'S
gain decreases. With Vdrive = OV, the amplifier'S gain is
6 dB less than the maximum gain.

3-44

n

a'

c::;

cCD

o

Vee
R40

SOk

...

n

-

-6'

R47

R44
2k

6.4k

0'
::::I

'9

I
TO VIDEO AMP

TO VIDEO AMP

011

012

7.3V

BIAS
R46

Co>

in

50

S.4V
Zener

R42
100

R4S

R48

R51

10k

12.8k

10k

9

10

11

DRIVE CONTROL INPUT

DRIVE CAP

DRIVE CAP
TLlHI11440-7

FIGURE 6. Simplified SChematic of the LM1202 Drive Control

~o~u.,

II

Circuit Description (Continued)

R70
200

14

CLAMP GATE INPUT
TLlH/11440-8

FIGURE 7. Simplified Schematic of the LM1202 Clamp Gate Circuit

3·46

Circuit Description (Continued)
Vee
RS9
100

R61
SOk

R62
400

R6S
400
SOI'A

069
4X

PUSH PULL OUTPUT CURRENT
TO CLAMP CAP

R67
100

R66
SOk

SOI'A

081
4X

!

400 I'A

400 I'A!

12
074

077

R60
SOk
R63

~ 40 0 l'A

RSS
500

RS6
500

079

068
2Sk
CURRENT SOURCE CONTROL
FROM CLAMP GATE

RS7
9k

! 200l'A

RS8
100

19

18

(_)COMPARATOR INPUT

(-)COMPARATOR INPUT
TUH/11440-9

FIGURE 8. Simplified Schematic of the LM1202 Clamp Comparator Circuit

3·47

Applications of the LM 1202
SINGLE VIDEO CHANNEL
A typical application for a single video channel is shown in
Figure 9. The video signal is AC coupled to pin 6. The
LM1202 internally biases the video signal to 2.6 Vee. Contrast control is achieved by applying a OV to 4V DC voltage
at pin 8. The amplifier's gain is minimum (i.e., maximum signal attenuation) if pin 8 is at OV and is maximum if pin 8 is at
4V. With pin 9 (drive control) at OV, the amplifier has a maximum gain of 10.
For DC restoration, a clamp signal must be applied to the
clamp gate input (pin 14). The clamp signal should be logic
low (less than 0.6Y) only during the back porch (black level
reference period) interval (see Figure 2). The clamp gate
input is TIL compatible. Brightness control is provided by
applying a OV to 4V DC voltage at pin 19. For example, If pin
19 is biased at 1V then the video signal's black level will be
clamped at 1V. A 5100 load resistor is connected from the
video output pin (pin 17) to ground. This resistor biases the
output stage of the amplifier. For power dissipation considerations, the load resistor should not be much less than
5100.

ROB VIDEO PREAMPLIFIER
Ftg/Jre 10 shows an AGB video preamplifier circuit using

three LM1202s. Note that pins 1 and 2 of IC1 are connected
to pins 1 and 2 of IC2 and 103 respectively. This allows IC1
to provide a master contrast control and optimum contrast
tracking. Adjusting the contrast voltage at pin 8 of IC1 will
vary the gain of all three video channels. Drive control input
(pin 9) of each LM1202 allows individual gain adjustment for
achieving white balance.
The black level of each video channel can be individually
adjusted to the desired voltage by adjusting the voltage at
pin 19. In a DC-coupled cathode drive application, adjusting
the voltage at pin 19 of each IC will provide cutoff adjustment. In an AC-coupled cathode drive application, the video
signal is AC coupled and DC restored at the cathode. In
such an application, the video Signal's black level may be
clamped to the desired level by simply biasing pin 19 to the
black level voltage by using a voltage divider at pin 19.

3-48

Applications of the LM 1202 (Continued)
100

VIDEO

Vee (+12V)

OUT

Vee (+12V)

LM1202
TOP VIEW

VIDEO
IN
75

CLAMP GATE

iii
510

0.01 p'r
Tl/H/114<1O-10

FIGURE t. Typical LM1202 Application (Single Video Channel)

3·49

Applications of the LM 1202 (Continued)

v"

+11V
Ill ..

"

.v'""

CIO!

5O JJFV'
m~:~~~

____,,_.. __
~

";:

~~~~

__

~

Uk

HOI

"
"

: : !--.,...:::::---I
.v""
..

R314

V'"
+Uy

--1I---'\_-III---I

GREEN~: @)-~______

O.OI,.r

FIGURE 10. Typical RGB Application with Contrast, Drive and Black Level (Cutoff) Control

3-50

TL/H/11440-11

r-----------------------------------------------------------------------------,
Power Down Characteristics

PC Board Layout Considerations

The LM1202 includes a built-in power down spot killer to
prevent a flash on the screen upon power down. The
LM1202's output voltage decreases as the device is being
powered down, thus preventing a flash on the screen. In
some preamplifiers, the video output signal may go high as
the device is being powered down. This may cause a whiterthan-white level at the output of the CRT driver, thus causing a flash on the screen.

For optimum performance and stable operation, a doublesided printed circuit board with adequate· ground plane and
power supply decoupling as close to the Vee pins as possible is recommended. For suggestions on optimum PC board
layout, please see the reference section below.

~

....~
~

N

Reference
Ott, Henry W, Noise R8duction Techniques in Electronic
Systems, John Wiley & Sons, New York, 1976.

•
3-51

~·.National

~ semiconductor

LM 1203 RGB Video Amplifier System
General Description

Features

The LM1203 is a wideband video amplifier system intended
for high resolution RGB color monitor applications. In addition to three matched video amplifiers, the LM1203 contains
three gated differential input black level clamp comparators
for brightness control and three matched attenuator circuits
for contrast control. Each video amplifier contains a gain set
or "Drive" node for setting maximum system gain (Av = 4
to 10) as well as providing trim capability. The LM1203 also
contains a voltage reference for the video inputs. For high
resolution monochrome monitor applications see the
LM1201 Video Amplifier System datasheet.

• Three wideband video amplifiers (70 MHz @ -3dB)
• Inherently matched (± 0.1 dB or 1.2%) attenuators for
contrast control
• Three externally gated comparators for brightness control
• Provisions for independent gain control (Drive) of each
video amplifier
• Video input voltage reference
• Low impedance output driver

Block and Connection Diagram
LM 1203 RGB AMP
(TOP VIEW)
Vee l

28 Vee l

CONTRAST CAP

2

27 R DRIVE

CONTRAST CAP

3

26 R CLAMP(-)

R VIDEO IN 4

25 R VIDEO OUT
24

R CLAMP CAP 5
G VIDEO IN

6

R CLAMP(+)

23 Vcc2
22 G DRIVE

GROUND 7
G CLAMP CAP 8

21 G CLAMp(-)

B VIDEO IN 9

20 G VIDEO OUT

B CLAMP CAP

10

19 G CLAMP(+)

V REF

11

18 B DRIVE

CONTRAST

12

17 B CLAMP(-)

Vee l

13

16 B VIDEO OUT

CLAMP GATE

14

15 B CLAMP(+)

TL/H/9178-1

FIGURE 1
Order Number LM1203N
See NS Package Number N28B

3-52

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee Pins 1, 13,23,28
(Note 1)
13.5V
Voltage at Any Input Pin, VIN
Vee;;;' VIN ;;;, GND
Video Output Current, 116, 20 or 25
28mA
Power Dissipation, Po
(Above 25'C) Derate Based on 6JA and TJ
Thermal Resistance, 6JA
Junction Temperature, TJ

O"Cto +70"C

Operating Temperature Range, TA
Storage Temperature Range, T8TG
Lead Temperature, (Soldering, 10 sec.)

ESD susceptibility
1 kV
Human body model: 100 pF discharged through a 1.5 kO
resistor

2.5W
50"C/W
150'C

Electrical Characteristics See Test Circuit (Figure 2), TA =

25'C;VCC1 = Vee2 = 12V

DC Static Tests S17, 21, 26 Open; V12 =

6V; V14 = OV; V15 = 2.0V unless otherwise stated

Label

Conditions

Parameter

-65'Cto + 150"C
265'C

Is

Supply Current

V11

Video Input Reference Voltage

Ib

Video Input Bias Current

Any One Amplifier

V141

Clamp Gate Low Input Voltage

V14h

Clamp Gate High Input Voltage

1141

Clamp Gate Low Input Current

114 h

Clamp Gate High Input Current

Iclamp+

Clamp Cap Charge Current

Iclamp-

Vee 1 only

Typ

Tested
Limit (Note 2)

73

90.0

mA(max)

2.2

V(min)

2.4

Design
Limit (Note 3)

Units
(Limits)

2.6

V(max)

5.0

20

,...A(max)

Clamp Comparators On

1.2

0.8

V(max)

Clamp Comparators Off

1.6

2.0

V(min)

V14 = OV

-0.5

-5.0

,...A(max)

V14 = 12V

0.005

1

,...A(max)

V5,80r10 = OV

850

500

,...A(min)

Clamp Cap Discharge Current

V5, 8 or 10 = 5V

-850

-500

,...A(min)

Vol

Video Output Low Voltage

V5, 80r 10 = OV

0.9

1.25

V(max)

Voh

Video Output High Voltage

V5,80r10 = 5V

8.9

8.2

V(min)

l::.Vo(2V)

Video Output Offset Voltage

Between Any Two Amplifiers
V15 = 2V

±0.5

±50

mV(max)

aVo(4V)

Video Output Offset Voltage

Between Any Two Amplifiers
V15 = 4V

±0.5

±50

mV(max)

AC Dynamic Tests S17,21,26Closed;V14 =
Symbol

Parameter

OV;V15 = 4V;unlessotherwisestated

Conditions

Typ

Tested
Limit (Note 2)
4.5

Design
Limit (Note 3)

Units
(Limits)

Avmax

Video Amplifier Gain

V12 = 12V, VIN = 560 mVp-p

6.0

aAv5V

Attenuation

@

5V

Ref: Av max, V12 = 5V

-10

aAv2V

Attenuation

@

2V

Ref: Av max, V12 = 2V

-40

dB

Avmatch

Absolute gain match

V12 = 12V (Note 5)

±0.5

dB

aAvtrack1

Gain change between amplifiers

V12 = 5V (Notes 5, 8)

±0.1

±0.5

dB (max)

aAvtrack2

Gain change between amplifiers

V12 = 2V (Notes 5, 8)

±0.3

±0.7

dB(max)

THD

Video Amplifier Distortion

V12 = 3V, Vo = 1 Vp·p

0.5

%

f(-3dB)

Video Amplifier Bandwidth
(Notes 4, 6)

V12 = 12V,
Vo = 100 mVrms

70

MHz

tr

Output Rise Time (Note 4)

Vo = 4Vp·p

5

ns

tf

Output Fall Time (Note 4)

Vo = 4Vp-p

7

ns

@

Av max

3-53

VIV(min)
dB

•

AC Dynamic Tests 517,21, 26 Closed; V14 =

OV; V15 = 4V; unlessotherwiseatated (Continued)

Typ

Symbol

Parameter

Vsep
10kHz

Video Amplifier 10kHz Isolation

V12 = 12V (Note 7)

Vsep
10MHz

Video Amplifier 10 MHz Isolation

V12 = 12V(Notes4, 7)

CO!ldltlona

Tested
Limit (Note 2)

OHlIn
Limit (Note 3)

UnIta

-65

dB

-46

dB

Note 1: Vee supply pins 1, 13,23,28 must be externally wired together to prevent Internal damage during Vee power onloff cycIea.
Note 2: These parameters are guaranteed and 100% production tested.
Note 3: Design limits are guaranteed (but not 100% production tested). These IImRs are not used to calculate outgoing quality levels.
Note 4: When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board without socket iSl'8COIIIIII8nd·
ed. Video AmplHler 10 MHz Isolation test also requires this printed circuR board.
Note 5: Measure gain difference between any two amplifiers. VIN = 1 Vp-p.
Note 6: Adjust input frequency from 10 kHz (Avmax ref level) to the -3 dB comer frequency (f -3 dB).
Note 7: Measure output levels of the other two undriven amplifiers relafive to driven amplifier to detenmine channel separation. Terminate the undriven amplifier
inpuls to simulate generator loading. Repeat test at fiN = 10 MHz for Vsep = 10 MHz.
Note 8: flAv track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three attenuators. 1118 tha difIerWIce In
gain change between any two amplHiers with tha Contrsst Voltege V12 at either 5V or 2V measured relativ8 to an Av max condition V12 = 12V. For example, at
Av max the three amplifiers gains might be 17.4 dB, 16.9 dB, and 16.4 dB and change to 7.3 dB, 6.9 dB, and 6.5 dB respectively for V12 = SV. ThiS yields the
measured typical ± 0.1 dB channel tracking.

0,01
pF

5pF

R;N

J'
1:' ".
1:'

O,lpF

10K

~
~
~

0.1
pF

~

0.1
pF

I Vee I

0.1
pF

27

3

26

4

25

5

24

6

7

5pF

0.1
pF

28

2

50n

B;N

Vee I

Vee 2

LM
1203
D.U.T.

8

23

22

21

20

50n

Va

CONTRAST

~.1
pF

V"

~.Ol

10

19

11

18

12

17

13Vccl

16

14

15

pF

CLAMP GATE
'Peaking capacoors. See Frequency Response
using various peaking cups graph on next page.
TL/H/tl18-2

FIGURE 2. LM1203 Teat Circuit
3-54

r-------------------------------------------------------------------------------------~

Typical Performance Characteristics

r-

s:::
.....
N

Q

Co)

Contrast vs Frequency

o VI2=12V
5V

-10
-20

3V
2.3V
2V
I.

-30
-40
-50

........t'

-60

1.7V

-70

o

~
~
~

-

II

Crosstalk vs Frequency

~

-10
-20

R

-30

-40
-50
-60

B
-70 R

Ref:OdB = 6V/V

IN

ION

lOOk

100M

1M

Frequency (Hz)

10M

100M

Frequency (Hz)
TL/H/9178-11

TLlH/9178-12

Attenuation vs Contrast Voltage

Frequency Response Using
Various Peaking Caps
0

II

+2
+1

-

o

-I

-2
-3
Rdrfve

IN

=100.11
ION

'iii"

-10

c

-20

c

-40

.:!!..

62pF
50pF
33pF
OpF

!..
~

,

-4
-5

Ii

I;'

J.oo"

L........

I

-30
-50
-60

-70

-I-'

o

Vee = 12V

2 3 4 5 6 7 8 9 10 1112

100M

Contrast Voltage V12 (V)

Frequency (Hz)

TL/H/9178-14
TL/H/9178-13

Pulse Response

Rise & Fall Times
Vert.

Horiz.

~

~

1V IDiv.

10 ns/Div.

- GND
TL/H/9178-15

3-55

•

Vee
+12V
~~------~~-------1~"'+

V-

28

100 !'F
RED DRIVE

5111
27

H---'IIV\r-""'Y""'''

26

H----.,

25

H-----1--~--.

TO RED
CASCODE
DRIVER

390ll

5

24

23

GREEN DRIVE

TO HV
SUPPLY
VIDEO OUT
60V pop

51ll

LW1203
8

21

20 H-+-1~--+------i
CUTOFF
390ll
ADJ.

10K

~.I!'F

H-t----.,

10

19

11

18 I-II-t-'IV\_.....
91ll

12

17HH----,

13

16

14

15

H-t--....+.-.
390ll

TO BLUE
CASCODE
DRIVER

max

CONTRAST
CONTROL

10K
10K

10K
,*0.11'

10K

BLACK LEVEL
(BRIGHTNESS)
CONTROL

""BL""A"';CK~LE"'V=EL
GATE IN
TLlH/9178-3

FIGURE 3. LM1203 Typical Application
• 300 resistors are added to 1he Input pins for protection against current surges ccming through the 10 p.F input capacitors. By Increasing these resistors to well
over 1000 the rise and fall times of the LMI203 can be Increased for EMI considerations.

3-56

r-----------------------------------------------------------------------------,
Applications Information
Figure 4 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of
other applications that benefit from the use of color display
terminals. The RGB color monitor characteristics may differ
in such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 4. Separate
horizontal and vertical sync signals may be required or they
may be contained in the green video input signal. The video
input signals are usually supplied by coax cable which is
terminated in 750 at the monitor input and internally ac cou·

0--+-""
Ho--+-....

V
SYNC IN

pled to the video amplifiers. These input signals are approxi·
mately 1 volt peak to peak in amplitude and at the input of
the high voltage video section, approximately 6V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One Important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range. The
Figure 4 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of the
LM1203 which contains the three matched video amplifiers,
contrast control and brightness control.

~

....~

B

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

VIDEO IN

Ro--++-....
G 0--+........
B

VIDEO At.lPUFICATION
WITH GAIN / DC
CONTROL

CONTRAST

BRIGHTNESS

TL/H/9178-4

FIGURE 4. Typical RGB Color Monitor Block Diagram

•
3·57

~
C)

,---------------------------------------------------------------------------------,

C'I
.,...

Circuit Description

::::!!!

Figure 5 is a block 'diagram of one of the .video amplifiers
along with the contrast and brightness controls. The contrast control is a dc-operated attenuator which varies the ac
gain of all three amplifiers simultaneously while not introducing any signal distortions or tracking errors. The brightness
control function requires a "sample and hold" circuit (black
level clamp) which holds the dc bias of the video amplifiers
and CRT cathodes constant during the black level reference
portion of the video waveform. The clamp comparator,
when gated on during this reference period, will charge or
discharge the clamp capacitor until the plus input of the
clamp comparator matches that of the minus input voltage
which was set by the brightness control.

....I

to the video input is through the 10 kO resistor which is
connected to the 2.4V reference at pin 11. The low frequency roll-off of the amplifier is set by these two components.
Transistor 01 buffers the video signal to the base of 02.
The 02 collector current is then directed to the Vee 1 supply directly or through the 1k load resistor depending uPon
the differential DC voltage at the bases of 03 and 04. The
03 and 04 differential base voltage is determined by the
contrast control circuit which is described below. RF decoupiing capacitors are required at pins 2 and 3 to insure high
frequency isolation between the three video amplifiers
which share these common connections. The black level dc
voltage at the collector of 04 is maintained by 05 and Q6
which are part of the black level clamp circuit also described
below. The video signal appearing at the collector of 04 is
then buffered by 07 and level shifted down by Z1 and 08 to
the base of 09 which will then provide additional system
gain.

Figure 6 is a simplified schematic of one of the three video
amplifiers along with the recommended external components. The IC pin numbers are circled with all external components shown outside of the dashed line. The video input
is applied to pin 6 via the 10 ,..F coupling capacitor. DC bias

LW1203
LOW VOLTAGE
VIDEO

EXTERNAL
HIGH VOLTAGE
VIDEO

>-1--"'1 CRT

CATHODE

B

TLlH/9178-5

FIGURE 5. Block Diagram of LM1203 Video Amplifier with Contrast and Black Level Control

3-58

n

·12VO

• •

•

•

i

•

;:;

i'

...ii'~

..
0~

l'

g.

-r
IN

C

!

10pF

754

~
 10 pF). a more
efficient method of emitter pull down would be to connect a
suitable resistor to a negative supply voltage. This has the
effect of a current source pull down when the minus supply
voltage is -12V and the emitter current is approximately

10 mA. The system gain will also increase slightly because
less signal will be lost across the internal 400 resistor. Precautions must be taken to prevent the video output pin from
going below ground because IC substrate currents may
cause erratic operation. The collector currents from the video output transistors are returned to the power supply at
Vee 2 pin 23. When making power dissipation calculations
note that the data sheet specifies only the Vee 1 supply
current at 12V. The IC power dissipation contribution of
Vee 2 is dependent upon the video output emitter pull down
load.
In applications that require video amplifier shut down because of fault conditions detected by monitor protection circuits, pin 11 and the wiper arms of the contrast and brightness controls can be grounded without harming the IC. This
assumes some series resistance between the top of the
control pots and Vee.
Figure 7 shows the internal construction of the pin 11 2.4V
reference circuit which is used to provide temperature and
supply voltage tracking compensation for the video amplifier
inputs. The value of the external DC biasing resistors should
not be larger than 10 kO because minor differences in input
bias currents to the individual video amplifiers may cause
offsets in gain.

:.-----------------------------V~~--._--~--..----_t_t------,
I

TO VIDEO INPUT
10K
10K

I

R21

R28
12K
R29
8K

14K3
I

I
I

IZ3

I

10K

I

R30
10K

TUH/9178-7

FIGURE 7. LM1203 Video Input Voltage Reference and Contrast Control Circuits

3-60

.-----------~----------------------------------------------------------------~r

....iii:

Circuit Description (Continued)
the 11 850 ",A current to ground. When pin 14 is low « 1.3V)
the 021 switch is off and the 11 850 ",A current source is
mirrored or "turned around" by reference diode 05 and 026
to provide a 850 ",A current source for the clamp comparator(s). The inputs to the comparator are similar to the clamp
gate input except that an NPN emitter coupled pair is used
to control the current which will charge or discharge the
clamp capaCitors at pins 5, 8, or 10. PNP transistors are
used at the inputs because they offer a number of advantages over NPNs. PNPs will operate with base voltages at or
near ground and will usually have a greater reverse emitter
base breakdown voltage (BVebo). Because the differential
input voltage to the clamp comparator during the video scan
period could be greater than the BVebo of NPN transistors a
resistor (R34) with a value one half that of R33 or R35 is
connected between the bases of 023 and 027. This resistor will limit the maximum differential input to 024, 25 to
approximately 350 mV. The clamp comparator common
mode range is from ground to approximately 9V and the
maximum differential input voltage is Vee and ground.

Figure 7 also shows how the contrast control circuit is configured. Resistors R23, 24, diodes 03, 4 and transistor 013
are used to establish a low impedance zero TC half supply
voltage reference at the base of 014. The differential amplifier formed by 015, 16 and feedback transistor 017 along
with resistors R27, 28 establish a diferential base voltage
for 03 and 04 in Figure 6. When externally adding or subtracting current from the collector of 016, a new differential
voltage is generated that reflects the change in the ratio of
currents in 015 and 016. To provide voltage control of the
016 current, resistor R29 is added between the 016 collector and pin 12. A capacitor should be added from pin 12 to
ground to prevent noise from the contrast control pot from
entering the IC.
Figure 8 is a simplified schematic of the clamp gate and
clamp comparator sections of the LM1203. The clamp gate
circuit consists of a PNP input buffer transistor (018), a PNP
emitter coupled pair referenced on one side to 2.1V (019,
20) and an output switch (021). When the clamp gate input
at pin 14 is high (>1.5V) the 021 switch is on and shunts

~
w

CI..AMP

GATE
IN

R32
5K

TO OTHER
'-+----------i---+ COMPARATORS

TL/H/9178-8

FIGURE 8. Simplified Schematic of LM1203 Clamp Gate and Clamp Comparator Circuits

3-61

•

Additional Applications of the LM 1203
Figure 9 shows how the LM1203 can be set up as a video
buffer which could be used in low cost video switcher applications. Pin 14 is tied high to turn off the clamp comparators. The comparator Input pins should be grounded as
shown. Sync tip (black level if sync is not included) clamping
is provided by diodes at the amplifier inputs. Note that the
clamp cap pins are tied to the Pin 11 2.4V reference. This
was done, along with the choice of 2000 for the drive pin
resistor, to establish an optimum DC output voltage. The

contrast control (Pin 12) ,will provide the necessary gain or
attenuation required for channel balancing. Changing the
contrast control setting will cause minor DC shifts at the
amplifier output which will not be objectionable as the output is AC coupled to the load. The dual NPN/PNP emitter
follower will provide a low impedance output drive to the AC
coupled 750 output Impedance setting resistor. The dual
500 JolF capacitors will set the low frequency response to
approximately 4 Hz.

r-~~--------""--<~+12V

0.1

28
2004

Dl

2

27

3

26

4

25

5

24

6

23

7

+12V

22
LM1203

8

21

9

20

10

1.

11

18

12

17

13

16

14

15

D4

2K

TUH/9178-9

FIOURE 9. ROB Video Buffer with Diode Sync Tip Ciampa and 750 Cable DrIver

3-62

Additional Applications of the LM 1203 (Continued)
When diode 04 at Pin 11 is switched to ground the input
video signals will be DC shifted down and clamped at a
voltage near ground (approximately 250 mV). This will disable the video amplifiers and force the output DC level low.
The DC outputs from other similarly configured LM1203s
could overide this lower DC level and provide the output
signals to the 750 cable drivers. In this case any additional
LM1203s would share the same 3900 output resistor. The
maximum DC plus peak white output voltage should not be
allowed to exceed 7V because the "off" amplifier output
stage could suffer internal zener damage. See Figure 3 and
text for a description of the internal configuration of the video amplifier.

Figure 10 shows the configuration for a three channel high
frequency amplifier with non gated DC feedback. Pin 14 is
tied low to turn on the clamp comparators (feedback amplifiers). The inverting inputs (Pins 17, 21, 26) are connected to
the amplifier outputs from a low pass filter. Additional low
frequency filtering is provided by the clamp caps. The drive
resistors can be made variable or fixed at values between 0
and 3000. Maximum output swings are achieved when the
DC output is set to approximately 4V. The high frequency
response will be dependent upon external peaking at the
drive pins.

+12V
0.1

V

28
0-300n

~

~

30n

'1i ".

~

10K

2

27

3

26

4

25

5

24
23
0-300n

son

22
10K

Lt./1203

~

8

21

9

20

10

19

11

18

V

12

17

GAIN
ADJUST

13

16

14

15

~ ".

10K

son

~
1 )'F

10K

DC OUTPUT
ADJUST

TL/H/9178-10

FIGURE 10. Three Channel High Frequency Amplifier with Non-gated DC Feedback (Non-video Applications)

3-63

J3
CI4:
O.I",r*,

~

.
~~

o.l,,,,r .

r-!~
0.1 ",r

I

~r

R2

£t

10K

i

~r

RS
10K

~t

i

~r

t-

R7
10K

l

Cl

~",r
J2

I

~

........,
1

LII1203
ICI

C23
28

2

27

3

26

~-

R8
OK

"

25

5

2"

;0

'; ~.1"'~"'~

Rl1
-'3K

6

23

7

22

8

21

r-

O:I'",F

';7

33pF
fj~

UT

;0

R20200.o.
9

20

10

19

11

18

r-

R19
3904

r~F

';7

RI8100,.,
17

13

16

1"

15

BOUT

R172oo.o.

;0
R16
3904

RIO

';7
0.1"'~

SKI
C14
10H

1

Cl~

1000pF

\,..,/

R1312K
Rl"
10K

Cl~

BRIGHTNESS
CONTROL

0.1"'~

8 ~

RIS
2K

L111881
1C2

,..- V

R9

C21
.,1 ",F

R211oo~7

CIS

s.o.

R22
3904
J"

12

:+:::
Cl~~Cl;~

ROUT

R232004

Jl
CONTRAST
CONTROL

rj!!lr
R2" 100'7

cl1l:10",r

I

~loo",r

2

7

3

6

*"

5

vo-

-COfE

r-

';7

Jg17

R12
680K

0;

.,

~.I"'F
TLlH/9178-18

FIGURE 11. LM1203/LM1881 ApplicatiOn Circuit for PC Board

9-64

PC Board with Components

<00

var
, <~~':V~;::~t

WEOQJT.

'.J~,~

. '* R •

'''> .

".

.

.~'

.

• G:.
.','.

c.>

0.

(II

: ~ . ;. .

.B>.

. ; ..

.~'; .~,)

:

..

:

,

·'~~'+f;..........
.
.
.
.
.
.
.
,"
';'.'
.:-,.

:.

~

,'~ ,/BRIGfTNESS" '. 'lM 1203iLM'f$Sl ,
J'Q2~~'
'FGVt(Bl:'>'
;"

•

<

",'<,

"

. ;i:al«Ri

'AMPLIF~,

...... FEvS~>~;

<

TUH/9178-17

tou ...,

iii

~

~ ~National

~ ~ semiconductor

LM1203A
150 MHz RGB Video Amplifier System
General Description
The LM1203A is an improved version of the popular
LM1203 wideband video amplifier system. The device is intended for high resolution RGB CRT monitors. In addition to
three matched video amplifiers, the LM1203A contains
three gated differential input black level clamp comparators
for brightness control and three matched attenuator circuits
for contrast control. Each video amplifier contains a gain set
or "Drive" node for setting maximum system gain or providing gain trim capability for white balance. The LM1203A also
contains a voltage reference for the video inputs. The
LM1203A is pin and function compatible with the LM1203.

Features
• Three wideband video amplifiers 150 MHz @ -3 dB
• Matched (±0.1 dB or 1.2%) attenuators for contrast
control

• Three externally gated comparators for brightness
control
• Provisions for individual gain control (Drive) of each
video amplifier
• Video input voltage reference
• Low impedance output driver

Improvements over LM 1203
•
•
•
•

150 MHz vs 70 MHz bandwidth
VOUT low: 0.15V vs 0.9V
t r,t,:4nsvs7ns
Built in power down spot killer

Applications
• High resolution RGB CRT monitors
• Video AGC amplifiers
• Wideband amplifiers with gain and DC offset controls

Block and Connection Diagrams
~----------'-r-----------~
LM 1203A ROa AMP
(TOP VIEW)
Vcc 1

1

28

CONTRAST CAP

2

27 R DRIVE

CONTRAST CAP

3

26 R CLAMP(-)

R VIDEO IN

4

25 R VIDEO OUT

R CLAMP CAP

5

24 R CLAMP(»

G VIDEO IN

6

23 Vee 2

GROUND

7

22 G DRIVE

G CLAMP CAP

8

21 G CLAMP(-)

a VIDEO IN

9

2D G VIDEO OUT

a CLAMP CAP

10

19 G CLAMP(»

V REF

11

18

a DRIVE

CONTRAST

12

~=~=:::r"'"

17

a CLAMP(-)

Vee 1

13

1----:---------fJ

16 B VIDEO OUT

CLAMP GATE

14

1----1

15 B CLAMP(_)

Vee '

Tl/H/II441-1

FIGURE 1
Order Number LM1203AN
See NS Package Number N28B

3-66

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Thermal Resistance (8J,v

50"C/W

Junction Temperature (TJ)

150"C

Supply Voltage {Vcel
Pins 1, 13, 23, 28 (Note 3)

Storage Temperature

Peak Video Output Source Current
(Any One Amp) Pins 16, 20 or 25

ESD Susceptibility (Note 4)

13.5V

2kV
-65"Cto 150"C

Lead Temperature (Soldering, 10 sec.)

28mA

265'C

Operating Ratings (Note 2)

Vcc ~ VIN ~ GND
Power Dissipation, (Po) (Above 25'C derate
based on 8JA and TJ)
2.5W

Voltage at Any Input Pin (VIN)

-20"Cto +80"C

Temperature Range
Supply Voltage (Vcc)

10.8V

s: Vcc s:

13.2V

DC Electrical Characteristics See Test Circuit (Figure 2), TA = 25'C; VCC1 = VCC2 = 12V. S17, 21,26
= 6V; V14 = OV; V15 = 2.0V unless otherwise stated.

Open; V12
Symbol

Parameter

Is

Supply Current

V11

Video Input Reference Voltage

Conditions
VCC1 + VCC2, RL

= co (Note 7)

Typical
(Note 5)
70
2.8

Limit
(Note 6)

Unlta

95

mA(max)

2.5

V (min)

3.1

V (max)

Ie

Video Input Bias Current

Any One Amplifier

7

20

IlA (max)

V14L

Clamp Gate Low Input Voltage

Clamp Comparators On

1.2

0.8

V (max)

V14H

Clamp Gate High Input Voltage

Clamp Comparators Off

1.6

2.0

V (min)

114L

Clamp Gate Low Input Current

-1

-5.0

llA(max)

114H

Clamp Gate High Input Current

= OV
V14 = 12V

0.07

0.2

llA(max)

ICLAMP+

Clamp Cap Charge Current

V5,80r10

750

500

llA(min)

ICLAMP-

Clamp Cap Discharge Current

-750

-500

llA(min)

VOL

Video Output Low Voltage

0.15

0.5

V (max)

VOH

Video Output High Voltage

7.5

7

V (min)

I1VO(2V)

Video Output Offset Voltage

Between Any Two
Amplifiers, V15 = 2V

2

±25

mV(max)

I1VO(4V)

Video Output Offset Voltage

Between Any Two
Amplifiers, V15 = 4V

2

±25

mV(max)

V14

= OV
V5, 8 or 10 = 5V
V5,80r10 = OV
V5,80r10 = 5V

3·67

AC Electrical Characteristics See Test Circuit (Figure2j, TA = 25°C;VCC1 = VCC2 = 12V.S17,21,26
Closed; V14
Symbol

=

OV; V15

=

4V unless otherwise stated.
Parameter

Conditions

AVmax

Video Amplifier Gain

V12

I::.AV5V

Attenuation @ 5V

Ref: Av max, V12

I::.AV2V

Attenuation @ 2V

AVmatch

Absolute Gain Match @ Av max

I::.AVtrack 1

Gain Change Between Amplifiers

I::.Avtrack2

Gain Change Between Amplifiers

THD

Video Amplifier Distortion

f(-3dB)

Video Amplifier Bandwidth

= 560 mVpp
= 5V
Ref: Av max, V12 = 2V
V12 = 12V (Note 8)
V12 = 5V (Notes 8, 9)
V12 = 5V (Notes 8, 9)
V12 = 3V, Vo = 1 Vpp
V12 = 12V, Vo = 4 Vpp

(Notes 10, 11)

(No External Peaking Capacitor)

Video Amplifier Bandwidth

V12

(Notes 10,11)

With 18 pF Peaking Cap from

f(-3dB)

=

12V, VIN

=

Typical

Umit

(Note 5)

(Note 6)

6.5

4.5

. -8

Units
VIV(min)
dB

-30

dB

±0.3

dB

±0.1

dB

±0.3

dB

1

%

100

MHz

150

MHz

3

ns

4

ns

12V (Note 12)

-70

dB

12V (Notes 10, 12)

-50

dB

12V, Vo

=

4 Vpp

Pins 18, 22 and 27 to GND

Ir

Output Rise Time (Note 10)

Vo

=

4Vpp

(No External Peaking Capacitor)
tf

Output Fail Time (Note 10)

Vo

=

4Vpp

(No External Peaking Capacitor)
Vsep 10kHz
Vsep 10 MHz

Video Amplifier 10kHz isolation
Video Amplifier 10 MHz Isolation

V12
V12

=
=

Note 1: Absolute Maximum Ratings indicals IlmHs beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device Is functional, but do not guarantee specific performance IImHB. For guaranteed specifications
and test condHions, see the Elecbical Charactsrlstlcs. The guaranteed specifications apply only for the test conditions listsd. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 3: Vee supply pins 1,13,23,28 must be externally wired together to prevent internal damage during Vee power onloff cycles.
Note 4: Human body model, 100 pF discharged through a 1.S kll resistor.
Note 5: Typical Specifications are specified at

+ 2S"C and represent the mosl likely parametric norm.

Note 6: Tested limits are guaranteed to National's AOOL (Average Outgoing Quality Level).

Note 7: The supply current specified Is the quiescent current for Vee1 and VCC2 with RL = 00, see Figure 2'8 test circuH. The supply current for VCC2 (pin 23) also
depends on the output load. With video output at 2V DC, the additional current through VCC2 Is 18 rnA for Figure 2'8 Isst circuH.
Note 8: Measure gain difference between any two amplHiers. VIN

=

1 Vpp.

Note 9: t;. Av track is a measure of the abilHy of any two amplifiers to track each other and quantifies the matching of the three attenuators. It is the difference in gain
change between any two amplHiers with the contrast voltage (V12) at either SV or 2V measured relative to an Av max condition, V12 = 12V. For example, at
Av max the three ampiHiers' gains might be 17.4 dB, 16.9 dB and 16.4 dB and change to 7.3 dB, 6.9 dB, and 6.S dB respectively for V12 = SV. This yields the
measured typical ± 0.1 dB channel traCking.
Note 10: When measuring video amplifier bendwidth or pulse rise and fall times, a double sided full ground plane prinlsd circuit board wilhout socket is
recommended. Video amplHier 10 MHz Isolation test also requires this printed circuH board.
Note 11: Adiust input frequency from 10 kHz (Av max reference level) to the -3 dB corner frequency (L3 dB).
Note 12: Measure output levels of the other two undriven amplifiers relative to the driven amplHier to delsrmine channel seperation. Terminate the undriven
amplifier Inputs to simulate generator loading. Repeat tsst at fiN = 10 MHz for Vsep = 10 MHz.

"

3-68

,-----------------------------------------------------------------------------,
Vee 1

28

30 V:01J.1F
2

27

loon
26

4

25

5

24

10K

~

0.1
J.lF

6

Vee 2

10K

23

BLACK
LEVEL
SET

LM
7

1203A

22

D.U.T.
8

21

20

10

19

11

18

12

17

13Veel

16

14

15

CLAMP GATE

TUH/II441-2

FIGURE 2. LM1203A Test Circuit

Typical Performance Characteristics Vee =

12V, TA = 25°C unless otherwise specified

Contrast vs Frequency
VOUT

0
~

.:s
III

-30

.

~
z
:cto

(REF)

= 4V ~- V12

-..... ~

4V
2.2V

-1(\"

lo9V

-40

~

1.74V

-50

1.68V

-60

lOOk

~ 12V
6V

-10
-20

...
......z

= Hpp

~ BRIGHTNESS

1M

10M

FREQUENCY (Hz)

3-69

....

e

0.01
J.lF
1 Vee 1

~

I:

31

100M
TUH/II441-3

Typical Performance Characteristics Vee =

12V, TA = 25"C unless otherwise specified (Continued)

Crosstalk vs Frequency
GREEN (WAX CONTRAST)

0

'iii'
~

:'-..

-20

z

~

-40

!;(

-60

.......'"

RED ~

"-" '1
~

P

•

~ p(

z

BLUE)

.....::::
~

1
1

-80
lOOk

lW

10M

100M

fREQUENCY (Hz)

TL/H/11441-4

Frequency Response Using Various Peaking Caps

tt2

t-

=

VOUT
4 Vpp
CONTRAST = 12V
BRIGHTNESS 4V
RoRIVE
1Don

=

=

33pf

'iii'

~

z

~

24pf

0

............

-1

-2

....... r-..

1\1 ~18pf
t.-' ~Opf

,

1\ I~

-3

1M

\

I"

10M

100M

fREQUENCY (Hz)

TL/H/11441-5

Attenuation vs Contrast Voltage

z

I""'"

~

'iii' -12
~

-

VOUT = 4 Vpp
BRIGHTNESS = 4V

-6

/'

-18

0

~ -24
:::>
z -30

...
S

I

I

-36
-42
-48

-52

J

o

2.4

4.8

7.2

CONTRAST'VOLTAGE V12 (v)

3-70

9.6

12
TL/H/11441-6

~~--------~--------~~~+

'V

28

";
"n'
7sn

VI~:O

O.I/o1F

10K

~

,?it'' ·'
IN

/ol

F

RED DRIVE

O.OI/o1F

30

100

SUI.
2

27

3

26

"

25

5

24

6

23

7

22

390n

TO RED
CASCODE
DRIVER

TO HV
SUPPLY

lK
GREEN DRIVE

7sn

VIDEO OUT
SOV P-P

sIn
LM1203A
8

21

9

20

10

19

11

18

12

17

13

16

390n

'V
+

10/01

91n

*"O.OI/o1F

390n
14

IS

TO BLUE
CASCODE
DRIVER

max

CONTRAST
CONTROL

10K

10K

10K

BLACK LEVEL
(BRIGHTNESS)
CONTROL

BLACK LEVEL
GATE IN
TL/H/II441-7
'470 resistors are added to the input pins for protection against current surges ccming from the 10".F capacitors. By increasing these resistors to well over 1000
the rise and fall times of the LM1203A can be increased for EMI considerations.

FIGURE 3. LM1203A Typical Application

3-71

II

VIDEO AMPLIFIER SECTION

Applications Information

Figure 6 is a simplified schematic of one of the three video
amplifiers along 'with the recommended external components. The IC pin .numbers are circled and all external components are shown outside the dashed line. The video input
is applied to pin 6 via a 10 p.F coupling capaCitor. DC bias
for the video input is through the 10k resistor connected to
the 2.8V reference at pin 11. The low frequency roll-off of
the amplifier is set by these two components. Transistor 01
buffers the video signal to the base of 02. 02's collector
current is then directed to the VCCl supply directly or
through the 2k load resistor depending upon the differential
DC voltage at the bases of 03 and 04. This differential DC
voltage is generated by the contrast control circuit which is
described in the follOwing sections. A 0.Q1 p.F decoupling
capaCitor in series with a 300. resistor is required between
pins 2 and 3 to ensure high frequency isolation between the
three video amplifiers which share these common connections. The video Signal is buffered by 05 and 06 and DC
level shifted by the voltage drop across R5. The magnitude
of the current through R5 is determined by the voltage at pin
8. The voltage at pin 8 is set by the clamp comparator output current which charges or discharges the clamp hold capacitor during the black level period of the video waveform.
Transistors 09 and 010 are Darlington connected to ensure
~ minimum discharge of the clamp hold capaCitor during the
time that the clamp capaCitor is gated off. 07, 08 and R6
form a current mirror which sets a voltage at the base of
011. 011 buffers the video signal to the base of 012 which
provides additional signal gain. The "Drive" pin allows the
user to trim the 012 gain of each amplifier to correct for gain
differences in the CRT and high voltage cathode driver gain
stages. A small capacitor (severalpico-Farads) from the
"Drive" pin to ground will cause high frequency peaking and
slightly improve the amplifier'S bandwidth.

Figure 4 shows the block diagram of a typical analog RGB
color monitor. The RGB monitor is used with CAD/CAM
work stations, PC's, arcade games and in a wide range of '
othe~ applications that benefit from the use of color display
~ermlnals. The RGB color monitor characteristics may differ
In such ways as sweep rates, screen size, CRT color trio
spacing (dot pitch), or in video amplifier bandwidths but will
still be generally configured as shown in Figure 4. Separate
horizontal and vertical sync signals may be required or they
may be contained in the green video input signal. The video
input signals are usually supplied by coax cable which is
terminated in 750. at the monitor input and internally AC
coupled to the video amplifiers. These input signals are approximately 1V peak to peak in amplitude and at the input of
the high voltage video section, approximately 6V peak to
peak. At the cathode of the CRT the video signals can be as
high as 60V peak to peak. One important requirement of the
three video amplifiers is that they match and track each
other over the contrast and brightness control range.' The
Figure 4 block labeled "VIDEO AMPLIFICATION WITH
GAIN AND DC CONTROL" describes the function of the
LM1203A which contains the three matched video amplifiers, contrast control and brightness control.

Circuit Description
Figure 5 is a block diagram of one of the video amplifiers
along with the contrast and brightness controls. The contrast control is a DC-operated attenuator which varies the
AC gain of all three amplifiers simultaneously while not introducing any signal distortions or tracking errors. The brightness control function requires a "sample and hold" circuit
(black level clamp) which holds the DC bias of the video
amplifiers and CRT cathodes constant during the black level
reference portion of the video waveform. The clamp comparator, when gated on during this reference period, will
charge or discharge the clamp capaCitor until the plus input
of the clamp comparator matches that of the minus input
voltage which was set by the brightness control.

v 0---11---1
SYNC IN

Ho--+--I

VERTICAL / HORIZONTAL SWEEP
AND POWER SUPPLY
CIRCUITS

VIDEO IN

G o---1J-t.--1

VIDEO AMPLIFICATION
WITH GAIN / DC
CONTROL

CONTRAST

BRIGHTNESS

FIGURE 4. Typical RGB Color Monitor Block Diagram

3-72

TL/H/11441-8

Circuit Description (Continued)
For individual gain adjustment of each video channel, a 510
resistor in series with a 1000 potentiometer should be used
with the red and green channel drive pins. A 910 resistor
used with the blue channel drive pin sets the blue channel
amplifier gain at approximately 6.2. The 1000 potentiometer
at the red and green channel drive pins allow a gain of 6.2
with ± 25% gain adjustment. The video signal at the collector of 012 is buffered and level shifted down by 013,014
and 015 to the base of the output emitter follower 016. A
500 decoupling resistor is included in series with the emitter
of 016 and the video output pin so as to prevent oscillations
when driving capacitive loads. An external resistor should
be connected between the video output pin and ground.

The value of this resistor should not be less than 3900 or
else package power limitations may be exceeded under
worst case conditions (high supply voltage, maximum current, maximum temperature). The collector current from the
video output transistor of each video channel is returned to
the power supply at VCC2, pin 23. When making power dissipation calculations note that the data sheet specifies only
the VCC1 and VCC2 supply current at 12V supply voltage
with no pull down resistor at the output (i.e., RL = 00, see
test circuit Figure 2). The IC power diSSipation due to VCC2
is dependant upon the external video output pull down resistor.

Lt.t1203
LOW VOLTAGE
VIDEO

EXTERNAL
HIGH VOLTAGE
VIDEO

>--4J~-" CRT

CATHODE

8

CLAt.tP GATE

J
TL/H/11441-9

FIGURE 5. Block Diagram of LM1203A Video Amplifier with Contrast and Black Level Control

3-73

•

Circuit Description

(Continued)

Vee
+12V

23

RIO
50
R3
2k

O.OlpF
VIDEO IN

QI6

Y~~k
.•

~

2.BV

IOpF

RI4
50

~ REF

_.

5 10------~----------18 27
16 25

O.lpF
CLAMP

T

CAP ' "

VIDEO
OUT

TLlH/11441-10

FIGURE 6. Simplified Schematic of LM1203A Video Amplifier Section with Recommended External Components

3·74

Circuit Description (Continued)
INPUT REFERENCE AND CONTRAST CONTROL
SECTION

(Figure 8) consists of a PNP input buffer transistor (046), a
PNP emitter coupled pair (047 and 049) referenced on one
side to 2.1 V and an output switch transistor 053. When the
clamp gate input at pin 14 is high (> 1.5V) the 053 switch is
on and shunts the 200 /LA current from current source 054
to ground. When pin 14 is low « 1.3V) the 053 switch is off
and the 200 /LA current is mirrored by the current mirror
comprised of 055 and 036 (see Figure 9). Consequently
the clamp comparator comprised of the differential pair 035
and 037 is enabled. The input of each clamp comparator is
similar to the clamp gate except than an NPN emitter coupled pair Is used to control the current that will charge or
discharge the clamp capacitors at pins 5, 8 and 10. PNP
transistors are used at the inputs because they offer a number of advantages over NPNs. PNPs will operate with base
voltages at or near ground and will usually have a greater
emitter base breakdown voltage (BVebo). Because the differential input voltage to the clamp comparator during the
video scan period could be greater than the BVebo of NPN
transistors, a resistor (R37) with a value one half that of R36
or R39 is connected between the bases of 034 and 038.
The clamp comparator's common mode range is from
ground to approximately 9V and the maximum differential
input voltage is Vee and ground.

Figure 7 shows the input reference and contrast control circuitry. A temperature compensated 2.8V reference voltage
is made available at pin 11. The external DC biaSing resistors shown should not be larger than 10k because minor
differences in input bias currents of the individual video amplifiers may cause offsets in gain. Figure 7 also shows how
the contrast control circuit is configured. R21, R22, 022,
023 and 024 establish a low impedance zero TC half supply voltage reference at the base of 025. The differential
amplifier formed by 027, 028 and feedback transistor 029
along with R28 and R29 establish a differential base voltage
for 03 and 04 in Figure 6. When externally adding or subtracting current from the collector of 028, a new differential
voltage is generated that reflects the change in the ratio of
currents in 027 and 028. To allow voltage control of the
current through 028, resistor R27 is added between the
collector 028 and pin 12. A capaCitor should be connected
from pin 12 to ground to prevent noise from the contrast
control potentiometer from entering the IC.

CLAMP GATE AND CLAMP COMPARATOR SECTION
Figures 8 and 9 show simplified schematics of the clamp
gate and clamp comparator circuits. The clamp gate circuit

-------------------------------------------.
vee
R28
12k

R27
8k

~.ll'r

10k

TO VIDEO
INPUT
029

I

R26

R30

200

200

TO VIDEO

&I

TO VIDEO

AWP

AWP

03 BASE

04 BASE

R29
4.7k

R31
10k

------------------------------------------_.

TL/H/11441-11

FIGURE 7. Simplified Schematic of LM1203A Video Input Reference and Contrast Control Circuits

3-75

Circuit Description

(Continued)

CLAMP GATE
INPUT

TLlH/11441-12

FIGURE 8. Simplified Schematic of LM1203A Clamp Gate Circuit

3·76

r-----------------------------------------------------------------------------,
Circuit Description

(Continued)

r

....~

m

Vee
R41
100

R42
50k

040
4 X

R43
400

50 S'A 50 S'A

!

!

042
1X

R44
400

Q45
4X

043
1X

400 S'A

400 S'A

~

!

PUSH PULL OUTPUT CURRENT
TO CLAMP CAP(S)

R46
100

035

034

037

R37
25k

CURRENT SOURCE
CONTROL FROII
CLAtotP GATE

R40
100

R38
500

26

17
21

19

(+) COMPARATOR INPUT

(-) COMPARATOR INPUT
TLlH/11441-13

FIGURE 9. Simplified Schematic of LM1203A Clamp Comparator Circuits

3·77

Additional Applications of the LM 1203A
FigufB 10 shows the cOnfiguration for a three channel high

Sync input Signal may have either polarity. The back porch
clamp signal applied to LM1203A's pin 14 allows clamping
the video output signals to the black reference level, thereby providing DC restoration. The back porch clamp pulse
width is determined by the time constant due to the product
of R11 and C15. For fast horizontal scan rates, the back
porch clamp pulse width can be made narrower by decreasing the value of R11 or C15 or both. Note that an MM74C86
Exclusive-OR gate may also be used, however, the pin out
is different than that of the MM74HC86.
For optimum performance and maximum bandwidth, high
speed buffer transistors (01, 02 and 03 in Figure 11) are
recommended. The 2N5770 NPN transistors maintain high
speed at high currents when driving the inputs of high voltage CRT drivers.

frequency amplifier with non gated DC feedback. Pin 14 is
tied low to turn on the clamp comparators (feedback amplifiers). The inverting inputs (Pins 17, 21, 26) are connected to
the amplifier outputs from a low pass filter. Additional low
frequency filtering is provided by the clamp caps. The drive
resistors can be made variable or fixed at values between
on and 300n. Maximum output swings are achieved when
the DC output is set to approximately 4V. The high frequency response will be dependent upon external peaking at the
drive pins.
Figure 11 shows a complete RGB video preamplifier circuit
using the LM1203A. A quad Exclusive-OR gate
(MM74HC86) is used to generate the back porch clamp signal from the compOSite sync input signal. The composite H

r---t--------------------.---[)+12V
0.1
28
0-300Q

~
,~

47£\

10k
.7Q

~

2.

27

3

26

•

25

5

24

6

23

7

22

0-300Q
LM1203

10k

21

8

,~

47£\
20

1 pr

V
GAIN
ADJUST

10

19

11

18

12

17

13

16

14

15

10k

TL/HI11441-14

FIGURE 10. Three Channel High Frequency Amplifier with Non-gated DC Feedback (Non-video Application)

3·78

Additional Applications of the LM 1203A (Continued)

Cl

R25
51

O.OI!'F~

C5

RED
VIDEO
IN

25
R27
24

51
GREEN
VIDEO
IN

RED
VIDEO
OUT

23
22

21
BLUE
VIDEO
IN

20
10

R30

19

51
11

18

12

17

13

16

14

15

GREEN
VIDEO
OUT

Cll

10!'F~

CIl

o.,!'r~

R32
51

EXTERNAL +/ - H SYNC IN

C17

LMI40LAZ-5.0
1

CONTRAST
R8
10k

BLUE
VIDEO
OUT

o.,!'r~
VEE (-12V)

•

RIO

TL/H/11441-18

FIGURE 11. LM1203A Applications Circuit

3·79

LM 1203A vs LM 1203
LM1203A is an improved version of the LM1203 RGB video
amplifier system and is pin and function compatible with the
LM1203. LM1203A's output voltage can swing as low as
0.15V as opposed to 0.9V for the LM1203. This eliminates
the need for a level shift stage between the preamplifier and
the CRT driver in most applications.
The LM 1203A also offers faster rise and fall times of 4 ns vs
7 ns for the LM1203 and 100 MHz bandwidth vs 70 MHz for
LM1203. With a peaking capacitor across the drive resistor,
LM1203A's bandwidth can be extended to 150 MHz. Because of LM1203A's wide bandwidth, the device may oscillate if plugged directly into an existing LM1203 board. For
optimum performance and .stable operation, a double sided

printed circuit board with adequate ground plane and power
supply decoupling as close to the Vee pins as possible is
recommended. Figure 12 shows the layout of the PC board
for Figure 11's circuit. For suggestions on optimum PC
board layout, please see the reference section below.
The LM1203A also includes a built-in power down spot killer
to prevent a flash on the screen upon power down. In some
preamplifiers, the video output Signal may go high as the
device is being· powered down. This may cause a whiter
than white level at the output of the CRT driver, thus causing a flash on the screen.

REFERENCE
Ott, Henry W. Noise Reduction Techniques in Electronic
Systems, John Wiley &50ns, New York, 1976.

vmEO IN

GNO

9

RI

VCC

J3

R34~3B9~I-J3

J4

(l

R3~HR2 H

~

~

D

-HSYNC

0

9~
:

.L •

-c:::J- CI4T
R9

LMI4ILAZ-S

-11-0
CSB

EXTERNAL SYNC IN

R3IIJ

G

r=-----,-

r-*

--1

RI6

C

RSI

-dOr R32
RIS
-c:J-

CI6

B

~L.--....J~CI7

11

R33

TCIS
!.L

JIB
RI2

.L
CI9T

-c:::J-

--c::J::-

-II-aa

JIB

r-

R28

=E3=R29
B Or

~
RI7

+ ....C13

RII:
-c:JfLAG R4S
~

R

~ R~

28 RI9

=t I-a~
-II-

B

~~

J4~

~2

R6

C

~ cill- C

R7 C8::t I-

~

B

~~ ~

~

G

VDEO OUT

VEE

-c:::J-

l.t...::;J29

C7+~; ~"~N

R4

VEE
~~

GNO

R

VCC

T

R 13

JS

CONTRAST

~:7 0

V
CONTROL

--c::J---

BRIiHTNESS

0V

CONTROL

NATmNAL
SEMlCO NOUCTO R
LM 121/J3A
RG B AMPLFIER
SYSTEM REV A
12112191
TL/H/11441-16

FIGURE 12(a). PC Board Silk Screen

3-80

~-------------------------------------------------------------------------, ~

....

i:

Additional Applications of the LM 1203A (Continued)

~

TL/H/11441-17

FIGURE 12(b). PC board layout of bottom side. Top side of PC board (not shown) Is full ground plane•

•
3·81

mr------------------------------------------------------------------.
PRELIMINARY
2.... ~National
~ ~ Semiconductor

LM1203B
100 MHz RGB Video Amplifier System
General Description

Features

The LM1203B is an improil,ed version of the popular
LM1203 wideband video amplifier system. The device is intended for high resolution RGB CRT monitors. In addition to
three matched video amplifiers, the LM1203B contains
three gated differential input black level clamp comparators
for brightness control and three matched attenuator circuits
for contrast control. Each video amplifier contains a gain set
or "Drive" node for setting maximum system g8.in or providing gain trim capability for white balance. The LM1203B also
contains a voltage reference for the video inputs. The
LM1203B is pin and function compatible with the LM1203.

• Three wideband video amplifiers (100 MHz @ -3 dB)
• Matched (± 0.1 dB or 1.2%) attenuators for
contrast control
.. Three externally gated comparators for
brightness control
• Provisions for individual gain controt (Drive) of each
video amplifier
• Video input voltage reference
• Low impedance output driver
• Stable on a single sided board

Improvements over LM1203

Applications
• High resolution RGB CRT monitors
• Video AGC amplifiers
• Wideband amplifiers with gain and DC offset controls

• 100 MHz vs 70 MHz bandwidth
• VOUT low:
tf:
• Built In power down spot killer

.1"

0.15V vs 0.9V
3.7 ns vs 5 ns

Block and Connection Diagrams
28-Leacl Molded DIP
LM 1203B RCB AMP
(TOP VIEW)

Vee l

1

28 Vee 1

CONTRAST CAP

2

27 R DRIVE

CONTRAST CAP

3

26 R CLAMP(-)

R VIDEO IN 4

25 R VIDEO OUT

R CLAMP CAP

24 R CLAMP(»

5

G VIDEO IN 6

23 Vee 2

GROUND

7

22 G DRIVE

G CLAMP CAP

8

21 G CLAMP(-)

B VIDEO IN 9

20 G VIDEO OUT

B CLAMP CAP

10

19 G CLAMP(»

V REF

11

18 B DRIVE

CONTRAST

12

~=~=:r--l

17 B CLAMP(-)

Vee l

13

I-----=-------_f_'

16 B VIDEO OUT

CLAMP (lATE

14

1----1

15 B CLAMP(»

TL/H/114B9-1

Order Number LM1203BN
See NS Package Number N28B
3-82

r-

iii:
....

~National

I

~ Semiconductor

LM 1204 150 MHz RGB Video Amplifier System
General Description

Features

The LM1204 is a triple 150 MHz video amplifier system
designed specifically for high resolution RGB video display
applications. In addition to three matched video amplifiers,
the LM1204 contains a DC operated contrast control, a DC
operated drive control for each amplifier, and a dual clamping system for both brightness control and video blanking.
The LM1204 also contains a back porch clamp pulse generator which is activated by an extemally supplied ± H/HV
sync Signal or by an extemal composite video signal. The
± H/HV sync input will have priority over the composite video input. A single -H/HV sync output is provided for the
automatically selected sync Input signal. The back porch
clamp pulse width is user adjustable from 0.3 p.s to 4 p.s.
The LM1204 video output stage will directly drive most
Hybrid or discrete CRT amplfier input stages without the
need for an extemal buffer transistor. The device has been
designed to operate from a 12V supply with all DC controls
operating over a OV to 4V range providing for an easy interface to serial digital buss controlled monitors.

•
•
•
•
•

Built-in video blanking function
Built-in sync separator for composite video input
Includes DC restoration of video signals
Back porch clamp pulse width user adjustable
DC control of brightness, contrast, blanking level, drive
and cutoff
• DC controls are OV to 4V for easy interfacing to a
digitally controlled system

Key Specifications
•
•
•
•

150 MHz large Signal bandwidth (typ)
2.6 ns rise/fall times (typ)
0.1 dB contrast tracking (typ)
±3 dB drive (~ gain) adjustments on R, G, B channels
(typ)

Applications
• High resolution CRT monitors
• Video AGC amplifier
• Wideband amplifier with gain and DC offset control

Block Diagram and Connection Diagram
Top View

R VIDEO IN 7

~

•

ONTRAST
~
AI

--A GAIN ADJ.

COWPOSITE
VIDEO SYNC
SEPARATOR

!lil! Jl
"5

I

!l

~

Ii

SACK
PORCH
CLAMP
GENERATOR

B1.ANKING

iRiiiiiiiiESS

CONTRAST

I

'"

~
~

iii

A2

II'" i
:

~

~

~

i

+/-

HSYNC
PROCESSOR

8
~
:
,

Ordering Information
Order Number LM1204V

See NS Package Number V44A
3-83

~

iflI

u

TL/H/II238-1

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage. Vee
Pins 2. 4. 6.19.31.41.44 (Note 3)
13.5V
Peak Video Output Source Current
(Any One Amplifier) Pins 30. 35 or 39
30mA
Voltage at Any Input Pin. VIN
GND :5: VIN :5: Vee
Maximum ± H Sync Input Voltage
5.5Vpp
Power DisSipation. PO (Above 25°C
Derate Based on (JJA and TJ)
2.4W

Thermal Resistance, (JJA
Junction Temperature. TJ
ESD Susceptibility (Note 4)
Storage Temperature
Lead Temperature
Vapor Phase (60 seconds)
Infrared (15 seconds)

52°C/W
. 150"C
2.5kV
- 65°C to 150"C
215°C
220"C

Operating Ratings (Note 2)
Temperature Range
Supply Voltage. Vee

O"C to 70"C
10.8V:5: Vee:5: 13.2V

DC Electrical Characteristics (Video Amplifier Section)
The following specifications apply for VCC (pins 2. 4. 6.19.31.36.41 and 44) = 12Vand TA = 25°C unless otherwise specified.
51 = B.S2 = B. 53. 4.5 closed. V9. 13. 15 = 2V. V20. 21. 22. 24. 43 = 0.5V unless otherwise specified; see test circuit.
Figure 1.
Symbol

Parameter

Conditions

Is

Supply Current

No Video or Sync Input
Signals. 51 = A

IB

Input Bias Current
(Pin 9.13.15.20.21 or 22)

51

124h

Blank Gate Input High Current

V24

= 4V

1241

Blank Gate Input Low Current

V24

= OV

IFB

Feedback Input Current
(Pin 28. 33 or 38)

IBlank+

Blank Cap Charge Current

IBlank-

Blank Cap Discharge Current

IBB

=A

Typical
(NoteS)

Limit
(Note 6)

Units

100

125

mA
(Max)

0.3

2

,...A
(Max)

0.01

2

,...A
(Max)

2

5

,...A
(Max)

150
V32,37,42 = OV
V32,37,42

= 5V

Blank Cap Bias Current (Pins 32. 37. 42)

nA

185

75

,...A (Min)

-185

-75

,...A(Min)
nA

20

IClamp+

Clamp Cap Charge Current

V5,10,14

= OV

185

75

,...A (Min)

IClamp-

Blank Cap Discharge Current

V5,10,14

= 5V

-185

-75

,...A(Min)

2

V (Min)

0.8

V (Max)

2

50

mV
(Max)

ICB

Clamp Cap Bias Current (Pins 5, 10, 14)

20
Input Signal is Not Blanked

nA

V24h

Blank Gate High Input Voltage

V241

Blank Gate Low Input Voltage

Input Signal is Blanked

Blank Comparator Offset Voltage

Voltage between V43 and
Any One Video Output

VH

Video Output High Voltage
(Pins 30. 35, 40)

RL = 350n
V28, 33, 38 = OV

8.7

7

V(Min)

VL

Video Output Low Voltage
(Pins 30. 35. 40)

RL = 350n
V28. 33. 38 = 4V

0.1

0.5

V(Max)

VCM43

Common Mode Range of Blank
Comparator (Pins 43. 28. 33. 38)

0.5

V(Min)

4

V(Max)

3-84

DC Electrical Characteristics (Sync Separator/Processor Section)

The following specifications apply for Vee (Pins 2, 4, 6, 19,31,36,41 and 44) = 12V and TA = 25°C, unless otherwise
specified. S1 = B, S2 = B, S3, 4, 5 closed, V9, 13, 15 = 2V, V20, 21, 22, 24, 43 = 0.5V, unless otherwise specified; see Test
Circuit Figure 1.

Typical
(Note 5)

Limit
(Note 6)

- H Sync Output Logic High (Pin 26)

4.2

2.4

V(Min)

- H Sync Output Logic Low (Pin 26)

0.1

0.4

V(Max)

Symbol

Parameter

-HVOH
-HVOL
V23

Quiescent DC Voltage at ± H
Sync Input

Conditions

3

Units

V

AC Electrical Characteristics (Video Amplifier Section)
The following specifications apply for Vee (Pins 2, 4, 6, 19,31,36,41 and 44) = 12V and TA = 25°C, unless otherwise
specified. S1 = B, S2 = B, S3, 4, 5 closed, V9, 13, 15, 21, 24, 43 = 4V, V20 = 2V, unless otherwise specified; see Test Circuit
Figure 1.

Symbol

Parameter

Typical
(Note 5)

Conditions

RIN

Video Amplifier Input Resistance

Avmax

Maximum Video Amplifier Gain

aAVtrack

Amplifier Gain (Contrast)
Tracking (Note 7)

aAV2V

Attenuation at 2V

Ref: Avmax V21

=

aAvO.5V

Attenuation at 0.5V

Ref: Avmax

V21

=

aGain

a Gain Range (Pins 9, 13, 15)

V9, 13, 15

=

10

12 kHz

5.5

V/v(Min)

=

dB

2V

6

dB

0.5V

28
±3

OVto4V

Max Brightness Tracking Error (Note 8)
Video Amplifier Bandwidth (Note 9)

THO

Video Amplifier Distortion

VOUT

tR

Video Output Rise Time (Note 9)

Square Wave Input
VOUT = 3.5 Vpp, RL

=

3500

Square Wave Input
VOUT = 3.5 Vpp, RL

=

3500

VOUT

=
=

3.5 Vpp
1 Vpp, f

=

kO

0.1

aVo

Video Output Fall Time (Note 9)

Units

20
fiN

L3dS

tF

Umlt
(Note 6)

12 kHz

20

dB (Min)
dB

100

mV

150

MHz

0.3

%

2.6

ns

2.6

ns

VISO(l MHz)

Video Amplifier 1 MHz
Isolation (Notes 9, 10)

-50

dB

VISO (130 MHz)

Video Amplifier 130 MHz
Isolation (Notes 9,10)

-10

dB

3-85

AC Electrical Characteristics (Sync Separator/Processor Section)
The following specifications apply for Vcc (Pins 2, 4, 6, 19, 31, 36, 41 and 44) = 12V and TA = 25°C, unless otherwise
specifiacJ. .Sl = A, S2 = B,S3, 4, 5 closed, V9, 13, 15, 20, 21, 43 = 2V, unJess otherwise specified; see Test Circuit Figure 1
and Timing Diagram for input waveform.
Symbol
VI8(Min)
VI8(Max)
V23

Parameter

Conditions

Composite Video Input Voltage
(Pin 18)
Composite Video Input Voltage
(Pin 18)

S2 = A,lnput = 10% Duty
Cycle, Test for Loss of BP
Pulse at Pin 26

± H Sync Input Voltage (Pin 23)

Input

Back Porch Clamp Pulse Width
atV24 = 1V
Back Porch Clamp Pulse Width
atV24 = 4V

S2

=

= A, Pin 26 =

BP Output

Max Duty Cycle of Active High
H Sync (Pin 23)
Max Duty Cycle of Active Low
H Sync (Pin 23)

Test for Loss of Sync
at Pin 26

ipdll

± H Sync Inputto - H Sync
Output Low Delay

Input

=

10% Duty Cycle

tpdhl

± H Sync Inputto - H Sync
Output High Delay

Input

=

10% Duty Cycle

tpdl

± H Sync Input Trailing Edge to
Back Porch Clamp Output Delay

Input = 10% Duty Cycle,
S2 - A

ipdl2

Composite Video Input to - H
Sync Output Low Delay

Input

=

10% Duty Cycle

ipdh2

Composite Video Input to - H
Sync Output High Delay

Input

=

10% Duty Cycle

tpd2

Composite Video Input Trailing
Edge to Back Porch Clamp Output Delay

Input = 10% Duty Cycle
S2 = A

ipdl2- tpdll

Composite Video and ± H Sync Input
to - H Sync Output Delta Delay

Input

DLO

=

10% Duty Cycle

LlmH
(NotaS)
0.15
2

10% Duty Cycle

Maximum ± H Sync Input Frequency
DHI

Typical
(Note 5)

1.6
1

1.4

300

600

Units
Vpp
(Min)
Vpp
(Max)
Vpp
(Min)

IJ-S
(Max)
ns
(Max)

600

KHz

22

%

22

%

100

ns

65

ns

70

ns

106

ns

68

ns

78

ns

6

ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may ooeur.
Note 2: Operating Ratings Indicate conditions for which the device Is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test condHlons listed. Some performance charactarfstics
may degrade when the device is not operated under the listed test conditions.
Note 3: Vee supply pins 2,4,6,19,31,36,41 and 44 must be externally wired together to prevent internal damage during Vee power on/off cycle.
Note 4: Human body model, 100 pF discharged through a 1.5 ktl resistor.
Note 5: Typical specifications are specified at + 25'C and represent the most likely parametriC norm.
Note 6: Tested IimHs are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 7: AAv tracking is a measure of the abilHy of any two amplifiers to track each other and quantifies the matching of the three attenua1ore. Itla the difference In
gain change between any two amplifiers with the contrast voHage, V21, at eHher 4V or 2V measured relative to an Ay max condHfon V21 = 4V. For example, at Ay
max, the thrae amplijiergains might be 17.4 dB, 16.9 dB and 16.4 dB and change to 7.3 dB, 6.9 dB and 6.5 dB respectively for V21 = 2V. This yields the measured
typical ± O. t dB channel tracking.
Note 8: Brightness tracking error Is measured wHh all three video channels set for equal gain. The measured value is limHad by the resolution of the measurement
eqUipment.
Note 8: When measuring video amplifier bsndwldth or pulse rise and fall times, a double sided full ground plane printed clreuH board Is recommended. Video
amplifier iaolation tests also require this printed circuit board. The measurad rise and fall times are effective rise and fall times, taking Into account the rise and fall
times of the generator.
Nole 10: Measure output levels of either undrlven amplifier relative to the driven amplifier to determine channellaolation. Terminate the undriven amplHler Inputs.

3·88

r-----------------------------------------------------------------------------~r

Typical Performance Characteristics

a::::

....
.,..

Vee = 12V, TA = 25°C unless otherwise specified

N

o
Attenuation vs Contrast
Control Voltage (f = 12 kHz)

l;t
~

-10

.". ......

-20

~
!C -30
'" -40
iii

".

-

-60

-70

...

-3
l;t
~

~
~

S -so

~ 3.0
.. 2.8
!: 2.8

§
z

i!

....

I~H-++-+-IH-I---I-H-r-l

v

1/

o

~

2.5

Q.

2.0

~

I.S

~

~

~

-20

~

-30

~

~

-40
-SO

0

0 2 4 6 8 10 12 14 18 18 20 22 24

1V

,.•

1

,..

o

0.5 1.0 1.5 2.0 2.S 3.0 3.5 4.0

BACK PORCH CLAWP WIDTH CONTROL VOLTAGE V22 (V)

Drive Control vs Frequency
-1

2.IV

-3

2.OV

-S

Va!.700mVpp

~~~:,t ~TVfM~ v,. •
IWEG

H SYNC INPUT DUTY CYCLE V23 (II)

1,.4V

r'::t·7=r'VHlflH+H!fII!--I+

ovl

-6

r

lOWEll

3.2V

-2
-4

MAX "GAIN

lOOk

........

VDRM-·V

fo'

-80 BaGHTNESS, Vza .. tV
-70

\

1.0
0.5

V21 -"V

-10

I

l.5
3.0

Contrast vs Frequency

::: L-L--'-...Jo-.J....J'--'--'--'--J......L--'--'
+/-

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.G

4.0

S
•

S

DRIVE CONTROL VOLTAGE ve.13 OR IS (V)

H-++-+-IH-I---I-H-r-l

EXTERNAL

V

-s

HI-++t-1H+-t-H-+-l

HI-++-+-IH-I---I-Hl-+-I
~ HI-++-+-IH-I---I-Hl-+-I

1.0

-3

Minimum External ± H
SynclnputLevelfVpp)
vs Input Duty Cycle (%)

i ~! H"""+-+-IH-I--.....H-+-I
E~!H-++-+-IH-I---I-H-r-l
~

L

-2

D.5 1.0 1.5 2.0 2.5 3.0 l.5 4.0

CONTRAST CONTROL VOLTAGE V21 (V)

,.

-I

-6

i"""

o

Back Porch Clamp Pulse
Width vs Pin 22 Voltage

Attenuation vs Drive
Control Voltage (f = 12 kHz)

Vu!.700mV,. IRIOIfTHESS.

.. 7
100 WEll

FREQUENCY (Hz)

Vzo"

tV

-=t-t1tttttF CUTOfF, Vu .. v,.:s • Yw .. 3V
_ 111111111 _ _ Yo" •.sv" AT tMHz "I f

lOOk

I MEG

lOWEll

100UEll

FREQUENCY (Hz)

Crosstalk vs Frequency
R

-10

!

-20

i!l

-30

~

-40

~

-50

8 or C

-60

111111

-70

111111

111111
lOOk

I WEG

lOWEll

100MEG

FREQUENCY (Hz)

TL/H/I1238-2

3-87

LM1204
.-----,.,-0 :~2V

...

* **

(+4V)

RED

t---1-"?'"".....0 VIIJ(O
OUT

V':o@

I,

'Ho

IN

~I I

BlUE

~'o':;@ I, w. ~I I

~-+-..--~r-~~OWIJ(O

OUT

IN

;
1---.,....--.,..... . . .,.........0 OUT

GREEN
WDEO

~=@ I ,

'II>

IN

U-I---I
O.1"r

BP WIDTH OUT FOR Sl=A. S2=A

O.1p.F

COMPOSIT£t-t
IN

~:f':::V ~
IN

75

1

V

.....-

....HIM... .........

T

0.'",

-H/HV
SYNC
OUT

75

ruH/1123B-3

FIGURE 1. LM1204 Test CIrcuit

,-----------------------------------------------------------------------------,
Timing Diagram

2

2Vpp

:I: H SYNC
INPUT
OR
SYNC ON GREEN
INPUT

~

____. . . ,"' •.•.•••.t. .•.. _

- H SYNC
OUTPUT

BACK PORCH
CLAMP PULSE OUTPUT
TLlH/11238-4

Input/Output Stages
- H Sync Output Stage

Composite Video Input

5V (INTERNAL REGULATOR)

TLlHI1 1238-6

TLlH/11238-5

Video Output Stage

r---------~~--~~----------~--~~--~V~
2K

50

8k
500
(PINS 30.35.40)

800

TLlH/11238-21

3-89

~

...

II:

Input/Output Stages (Continued)
± H/HV Sync Input
r----~,....O

Video Input Stage

S.6V (INTERNAL REGULATOR)

20k
2k

23).....;w...---it--t--l1-+
20k

TL/H/1123B-7

TLlH/1123B-B

Pin Descriptions
Vee (Pins 2, 4, 6,19,
31,36,41,44)
Contrast Cap (Pins 1, 3)
R Clamp Cap (Pin 5)
B Clamp Cap (Pin 10)
G Clamp Cap (Pin 14)
R Video In (Pin 7)
B Video In (Pin 11)
G Video In (Pin 17)
R I:!.. Gain (Pin 9)

B I:!.. Gain (Pin 13)
G I:!.. Gain (Pin 15)
Compose Video Input
(Pin 18)
Brightness Control
(Pin 20)

Contrast Control
(Pin 21)

All Vee pins must be extemally wired together. For stable operation, each supply pin should be
bypassed with a 0.01 ,...F and a 0.1 ,...F capacitor connected as close to the pin as is possible.
An external decoupling capacitor of value 0.1 ,...F should be connected between pins 1 and 3 for
contrast control.
A 0.022 ,...F to 0.1 ,...F capacitor should be connected from this pin to ground. This capacitor allows
clamping of the red channel video signal to the reference black level.
A 0.022 ,...F to 0.1 ,...F capacitor should be connected from this pin to ground. This capacitor allows
clamping of the blue channel video signal to the reference black level.
A 0.022 ,...F to 0.1 ,..F capacitor should be connected from this pin to ground. This capacitor allows
clamping of the green channel video signal to the reference black level.
This is the input for the red channel video signal, the signal should be AC coupled to the input through
a 10 ,...F capacitor.
This is the input for the blue channel video signal, the signal should be AC coupled to the input
through a 10 ,...F capacitor.
This is the input for the green channel video signal, the signal should be AC coupled to the input
through a 10 ,...F capaCitor.
This is the gain adjustment pin for the red video channel. A OV to 4Voe voltage is applied to this pin to
vary the gain of the red channel. Usually, the red channel is set for maximum gain and the gains of the
blue and green channels are reduced relative to the red channel until white balance is achieved on
the CRT screen.
This is the gain adjustment pin for the blue video channel. A OV to 4 Voc voltage is applied to this pin
to vary the gain of the blue channel.
This is the gain adjustment pin for the green video channel. A OV to 4 Voe voltage is applied to this pin
to vary the gain of the green channel.
This is the sync separator input pin. For Sync on Green systems, the green channel video signal
should be AC coupled to pin 18 through a 0.1 ,...F capacitor.
If the LMI204 is used without blanking then this pin should be biased at 2.0 Voc. Brightness control
for all three video channels is now controlled by pin 43 (blank level adjust pin). See F/{/ure 4. If the
LM1204 is used with blanking then this pin allows the user to simultaneously DC offset the video
portion of the output signals of all three channels thus allowing brightness control (See F/{/ure 5).
This pin simultaneously controls the gain of all three video channels. A OV to 4 Voc input voltage is
applied to this pin, with OV corresponding to minimum gain (i.e., maximum attenuation of video signal)
and 4V corresponding to maximum gain (i.e., minimum attenuation of the video signal).

3·90

Pin Descriptions (Continued)
Back Porch Clamp Width
Adjust (Pin 22)

± H Sync In (Pin 23)

Blank Gate In (Pin 24)·

Integrator Cap (Pin 25)

- H Sync Out (Pin 26)

G Feedback (Pin 28)

B Feedback (Pin 33)

R Feedback (Pin 38)

G Video Output
(Pin 30)
B Video Output
(Pin 35)
R Video Output
(Pin 40)
G Blank Clamp Cap
(Pin 32)
B Blank Clamp Cap
(Pln3n
R Blank Clamp Cap
(Pin 42)
Blank Level Adjust
(Pin 43)

GND (Pins 8, 1216,27,
29,34,39)

The LM1204 provides DC restoration or clamping during the back porch interval of the video signal.
The width of LM1204's internally generated back porch clamp signal can be varied by applying a OV
to 4 Voe voltage to this pin. The back porch clamp signal width can be varied from approximately
0.3 p.s to 4.0 p.s by applying 4V to 0.5V respectively. By connecting the blank gate input pin (pin 24)
to Vee, the back porch clamp pulse can be monitored on the - H Sync output pin (pin 26). See
Figures 4 and 5. By connecting pin 22 to Vee, the LM1204 functions as a non-gated amplifier
requiring no clamping. See Section 4 under application hints for further information.
This is the external sync input pin, it accepts a negative or positive polarity signal, either horizontal
sync or a composite sync (1.2 Vpp minimum amplitude). The LM 1204 also provides a negative
polarity (TTL compatible) horizontal sync or composite sync output on pin 26. If the composite video
input (pin 18) is not used then an H Sync Signal should be AC coupled to this pin through a 0.1 p.F
capaCitor. The ± H Sync input has priority over the composite video input if both signals are present.
This is the blank gate input pin. The LM1204 allows video blanking at the preamplifier. If blanking is
desired then a TIL compatible, negative polarity blanking signal should be applied to this pin. During
the blanking interval, a" three video outputs are level shifted to the blank level set by the voltage at
pin 43. If blanking is not required then, pin 24 should be biased at 4V.
Connecting pin 24 to Vee will cause pin 26 to output the internally generated back porch clamp
signal. The user can observe the change in back porch width as the potential at pin 22 is varied (see
Figures 4 and 5).
A 0.1 p.F capacitor should be connected from this pin to ground. This capaCitor allows the LM1204 to
integrate the ± H Sync input signal and genreate the proper polarity switch for - H Sync output.
This output pin provides a negative polarity horizontal sync signal for other system uses. There is
approximately 100 ns delay between the ± H Sync input signal at pin 23 and the - H Sync output
signal at pin 26.
Connecting pin 24 to Vee wi" cause pin 26 to output the internally generated back porch clamp
Signal. The user can observe the change in back porch clamp pulse width as the potential at pin 22 is
varied (See Figures 4 and 5).
This is the cutoff adjustment input for the green video channel. The green video output signal from
pin 30 is fed back to this input through a potentiometer thus allowing the user to indlvidua"y adjust
the cutoff (black reference) level for each gun. The signal level at this pin should be between 0.5V
and4V.
This is the cutoff adjustment Input for the blue video channel. The blue video output signal from pin
35 is fed back to this input through a potentiometer thus allowing the user to individually adjust the
cutoff (black reference) level for each gun. The signal level at this pin should be between 0.5V and
4V.
This is the cutoff adjustment input for the red video channel. The red video output signal from pin 40
is fed back to this input through a potentiometer thus allowing the user to individualy adjust the cutoff
(black reference) level for each gun. The signal level at this pin should be between 0.5V and 4V.
This is the green channel video output.
This is the blue channel video output.
This is the red channel video output.
A 0.022 p.F to 0.1 p.F capacito·r should be connected from this pin to ground. This capacitor allows
blanking for the green video channel.
A 0.022 p.F to 0.1 p.F capacitor should be connected from this pin to ground. This capaCitor allows
blanking for the blue video channel.
A 0.022 p.F to 0.1 p.F capaCitor should be connected from this pin to ground. This capacitor allows
blanking for the red video channel.
This pin serves two functions depending on whether the LM1204 is used with blanking or without
blanking. If blanking is not selected then pin 20 should be biased at 2.0 Voe and pin 43 assumes the
role of brightness control. Varying the potential at pin 43 will simultaneously DC offset the video
output signals of a" three channels (See Figure 4 ). If the LM1204 is used with blanking then during
the blanking interval, a" three video output signals wi" be level shifted to the blank level. The desired
blank level can be set by adjusting the potential at pin 43. Brightness control is now made possible
by varying the potential at pin 20. Adjusting the brightness control DC offsets the video portion of the
signal relative to the fixed blank level (a" channels are affected simultaneously). See Figure 5.
Ground. A" ground pins must be connected to the ground plane.

3-91

--

-------_._--------

II

~r---------------------------------------------------------~

....re

:Ii
.,.J

ment for each channel is done by varying the ~eed!Jack voltage at each of the R, G and B feedback inputs (Pins 38, 28
and 33). For example, cutoff adjustment for the green chan~
nel is done by potentiometer R8 shown in Figure 2.
Adjusting the contrast control (potentiometer R3 in Figure
2) varies the peak to peak amplitude (includes sync tip if
present) of all three video output signals relative to their
black reference level. The t:. Gain adjust (pins 9,15 and 13
for R, G, and B channels respectively) allows the user to
individually adjust the AC gain of each channel. For example
the AC gain of the green channel is adjusted using potentiometer R5 as shown in Figure 2. Normally the red channel
is set for maximum gain and the gains of the blue and green
channels are reduced until white balance is achieved on the
CRT monitor's screen. Figure 4 shows the adjustments for
operation without blanking.

Applications Hints
TheLM1204 is a wideband video amplifier-system designed
specifically for high resolution RGB CRT monitors. The device includes circuitry for DC restoration of video signals
and also allows contrast and brightness control. DC restoration is done during the back porch interval of the video signal. An internal sync separator generates a back porch
clamp signal either from a "Sync on Green" signal applied
to the composite video input (pin 18) or from an externally
supplied ±H Sync signal. The LM1204 first looks at the
± H Sync input (pin 23), if an external horizontal sync signal
is not present then the device syncs off the composite video
input. The internally generated back porch clamp pulse
width is user adjustable.
A blanking function is also included. This allows the user to
cutoff the beam current in the CRT's guns during the blanking interval thereby preventing horizontal retrace lines from
being visible. Normally blanking is done by applying a high
voltage pulse at the grid. However, blanking at the cathode
using the LM1204 leads to ease of design and lowered cost.
Figure 2 shows the block diagram of the green video channel and the control logic. The two modes of operation, with
and without blanking, are described below in detail.

2.0 Operation with Blanking
Much of what was discussed in Section 1.0 also applies
when the LM1204 is used with the blanking function. However, there are notable differences as described herein. For
operation with blanking, a TTL compatible blanking signal
must be applied to the blank gate input (pin 24).
During the blanking period, the blanking comparator connects switch S2 to position X (See Figure 2). This causes
the LM1204 to level shift the video output signal to the blank
level. Adjusting R9 will adjust the blank level of all three
channels. Individual blank level adjustment for each channel is done by varying the feedback voltage at each of the
R, G and B feedback inputs (pin 38, 28 and 33). In Figure 2
this is done by adjusting potentiometer R8 for the green
channel.
During the video portion of the video signal, S2 is connected
to position Y. Brightness control is now accomplished by
varying the potential at the brightness control pin (pin 20).
Adjusting R6 offsets the video portion of all three output
signals relative to the fixed blank level, restoring the DC
level of the video signal. Figure 5 shows the adjustments for
operation with blanking.

1.0 Operation without Blanking
For operation without blanking, the blank gate input (pin 24)
should be connected to +4V. This causes the blank comparator to connect switch S2 to position Y (See Figure 2).
Furthermore, the brightness control input pin (pin 20) should
be biased at a potential between 1V (Min) and 3.8V (Max), it
is best to bias this pin at 2V. The video signal is AC coupled
to the input of the LM 1204 as shown for the green channel
in Figure 2. During the back porch interval of the video signal (See Figure 3), the internally generated back porch
clamping pulse goes low, causing switches S1A and S1 B to
be closed. The closure of S1 A causes gm 1 to charge capacitor C2 to a potential determined by the DC voltage at pin
20. This allows gm 1 to set up an average DC bias for the AC
coupled video signal at the input of A1. When the back
porch clamping pulse is high, S1A and S1B are opened.
With S1A open, gm 1 is effectively disconnected from C2, C2
now holds the DC bias voltage. The transconductance
stage gm 1 therefore functions as a sample and hold device
and holds the input of A 1 at the desired DC bias.
The LM1204 uses black level clamping at the back porch of
the video signal to accomplish DC restoration. The transconductance stage gm2 is enabled during the back porch
clamp period to provide a sample and hold function. During
the back porch clamp period, DC feedback from LM1204's
video output is compared with the voltage set by potentiometer R9. Depending on A2's output voltage, C6 is either
charged or discharged so that the feedback loop conSisting
of gm2 and A2 is stabilized and the output is clamped to the
black level. All this occurs during the back porch clamp period. During the video portion of the signal, gm2 is disabled
and C6 holds the fixed black level reference voltage. The
beginning of each new line on the raster always starts from
a fixed reference black level thus restoring the DC component of each line.
A2 is a summing amplifier that adds a DC offset component
from gm2 to the video signal frO!l1 the multiplier. Adjusting
R9 will DC offset the output signals of all three channels
thus providing brightness control. Individual cutoff adjust-

3.0 Stability Considerations
For optimum performance and stable operation, a double
sided PC board with adequate ground plane is essential.
Moreover, soldering the LM1204 on to the PC board will
yield best results. Each supply pin (pins 2, 4, 6, 19, 31, 36,
41 and 44) should be bypassed with a 0.Q1 ,...F and a 0.1 ,...F
capacitor connected as close to the supply pin as is possible.
When driving the LM1204 from a 750 video source, the
cable is terminated with 750 to minimize reflections caused
by transmission line effects. However, the input impedance
of LM1204 is capacitive and is also affected by the stray
capacitance of the PC board. Thus the input impedance is a
function of frequency. This changes the impedance of the
cable termination. This can introduce overshoot and ringing
in LM1204's pulse response. A 1000 resistor in series with
the blocking capacitor at the video input will minimize overshoot and ringing (see Figure 8). The value of the resistor is
empirically determined. 1000 is a good starting value.
Since the LM1204 is a wide bandwidth amplifier with high
gain at high frequenCies, the device may oscillate when driving a large capacitive/inductive load. To prevent oscillation,
the amplifier's gain is rolled off at high frequencies. This is
accomplished by an RC network comprised of a reSistor in

3-92

3.0 Stability Considerations (Continued)

Non-Gated High
Frequency Application

series with a capacitor connected from the video output pin
to ground (see Test Circuit, Figure 1). A 110n to 200'.1
resistor in series with 10 pF is quite adequate for most applications. However, if oscillations don't cease then the value
of the resistor should be decreased or the value of the capacitor should be increased or a combination of the two.

By connecting the back porch width adjust pin (pin 22) to
Vee, the LM1204 functions as a non-gated amplifier requiring no sync or blanking signals. Figure 9 shows a triple high
frequency amplifier with variable gain and DC offset control.
In this mode of operation, filtered DC feedback must be
provided to pins 28, 33 and 38 as shown in Figure 9.

LM1204
CRT
VIDEO
A~PLlFIER

R,8

4V

R,8

COMPOSITE
1
VIDEO
181
INPUT

BACK PORCH CLAMP
PULSE GENERATOR

~--,

t>

I
BLANK
I
COMPARATOR I

R4

~;.....-+~ ~~~:~~~H

+/- H ~L.::23:.t,_S_Y_NC_PROC_ES~SO~R.J.;;.26;....._ _-o
INPUT
25
C3
INTEGRATINGI
CAPACITOR _

"""'-'1

ADJUST

1.4V

_ H SYNC OUTPUT

+

24 _

I

__01

BLANK GATE
INPUT
TLlH/1123B-9

FIGURE 2. Block Diagram Showing Timing Circuitry and Green Video Channel

COMPOSITE VIDEO
SIGNAL

BACK PORCH

-

L
I

REFERENCE BLACK LEVEL
(CUTOFF VOLTAGE)

VIDEO .-.LSYNC.J
PORTION------r-PORTIONI

BLANKING
PERIOD

CLAMPING PULSE

---u

c==

SI A,B OPEN

- H SYNC PULSE ....._ _ _ _- ,

1.J

==tF-

~

BACK PORCH
CLAMP PERIOD

SI A, B CLOSED

-=LF

U

H SYNC PERIOD
TL/H/1123B-l0

FIGURE 3. CompOSite Video and Timing Signals
3-93

•

4V

R, G, B VIDEO INPUT
7,11,17

40,35,30

R, G, B FEEDBACK
38,28,33
(CUTOFF ADJUST)
4V

Vee

+4V

+12V
BP
CLAI/P
WIDTH
ADJUST

BLANK LEVEL ADJUST
(FOR BRIGHTNESS CONTROL)

lOOk

TL/HI11238-11

~
np

CONTRAST CONTROL VARIES AC GAIN (PEAK TO PEAK AI/PLITUDE)
RELATIVE TO THE FIXED BLACK REFERENCE LEVEL (ALL THREE CHANNELS).
SEE DASHED WAVEFORI/.

~ BL:CK :FER:CE LEVEL
VIDEO OUTPUT AT CRT -

_

II. GAIN ALLOWS INDIVIDUAL
ADJUSTI/ENT DF AC GAIN OF
EACH CHANNEL.

WV
"
•

"

~

VIDEO

SYNC

- H SYNC OUTPUT, PIN 2&
L j ( W I T H PIN 24 AT +4V)

----==t

"

~

~

INTERNAL BACK PORCH CLAI/P PULSE OUTPUT,
PIN 28 (WITH PIN 24 CONNECTED TO Vee)

--U~ BP WIDTH ADJUSTABLE FROI/
0.3 PI TO 4 PI
TLlHI11238-12

R, G, B FEEDBACK ALLOWS INDIVIDUAL
ADJUSTI/ENT OF BLACK REFERENCE (CUTOFF)
LEVEL FOR EACH CHANNEL.

TLlHI1123B-13
BLANK LEVEL ADJUST DC OFFSETS THE ENTIRE WAVEFORI/,
ALLOWING BRIGHTNESS CONTROL (ALL THREE CHANNELS).
SEE DASHED WAVEFORI/.

TLlHI1123B-14

FIGURE 4. LM1204 Adjustments without Blanking

3-94

r-----------------------------------------------------------------------------,~

...

!II:

4V

N

R

B

G

.3. GAIN

.3. GAIN

.3. GAIN

C)

0100

lOOk
- H SYNC OUTPUT

R. G. B VIDEO INPUT

26

7.11.17

40.35.30

R. G. B FEEOBACK

38.28.33

4V

CRT CATHODE

(INDIVIDUAL BLANK LEVEL ADJUST)

20

o--t----.
BLANK GATE
INPUT
_ _ _ _ _ _....,
~

Sl~
Vcc
+12V

6

--, r----=l r::-- - 4V
W
-w-- -OV
BLANKING PERIOD

BP
WIDTH
ADJUST

lOOk

~

BLANK LEVEL ADJUST

---r--..r.-..

VIDEO OUTPUT _
AT CRT BLANK PEDESTAL

VIDEO

SYNC
TIP

,

r

--.

BLANKING PULSE

,BLANKING SIGNAL APPLIED TO PIN 24
. - - BLANKING PERIOD

CONTRAST CONTROL VARIES AC GAIN (PEAK
TO PEAK AMPLITUDE) OF VIDEO PORTION
RELATIVE TO THE FIXED BLANK REFERENCE
LEVEL (ALL THREE CHANNELS).

1...-_---1

.3. GAIN ALLOWS INDIVIDUAL ADJUSTMENT

--,L.....Jr -

- H SYNC OUTPUT. PIN 26
(WITH BLANKING SIGNAL
APPLIED TO PIN 24)

INTERNAL BACK PORCH CLAMP PULSE OUTPUT.
PIN 26 (WITH PIN 24 CONNECTED TO VCC )

~ 0.3}'s

OF AC AND DC GAIN OF EACH CHANNEL.

II

VIDEO OUTPUT _
--~r--~r-,
AT CRT BLANK PEDESTAL
INCREASED BLANK
PEDESTAL DUE TO
BRIGHTNESS CONTROL

BP WIDTH ADJUSTABLE FROM
TO 4}'s

BRIGHTNESS CONTROL DC OFFSETS
THE VIDEO PORTION OF THE SIGNAL
RELATIVE TO THE FIXED BLANK
LEVEL. ALSO INCREASES OR

..

/ ' NEW BLACK
LEVEL

,/ '

,. ," •
" "
I

I

DECREASES THE BLANK PEDESTAL

HEIGHT. SEE DASHED WAVEFORM.

TUH/11238-15

FIGURE 5. LM1204 Adjustments with Blanking

3-95

LM1204

:J
"a
~

Vee
R13

R
VIDEO

40k

IN
C14

"a

CRT VIDEO AMPLIFIER

"2-

(GREEN CHANNEL)

n

R1

7511

I

»

R VIDEO OUT

ao·

V+
+60V

CONTRAST
d GAIN ADJ.

~

fn

=G>-1 ..

mm

d GAIN ADJ.

n
ri
c

~
A2

TO CRT CATHODE

if

=G>-1"'~ ~
Al

Co)

ii

d GAIN ADJ.

A2

LM1204

G
VIDEO 0

,

,-·1

COMPOSITE
VIDEO SYNC
SEPARATOR

BLANKING
BRIGHTNESS

BACK PORCH
CLAMP
GENERATOR

Vee

+/-

HSYNC
PROCESSOR

G VIDEO OUT

IN

200
20
G FEEDBACK
(CUTOFF ADJUST)

IOPF

4V

TUHI1 1238-16

FIGURE 6. The LM1204 driving cascode CRT video amplifiers and operating without blanking. Brightness control is accomplished by potentiometer R12 (See FIgure 4
for explanation of adjustments). Each Vee pin should be bypassed with a 0.01 ,...F and a 0.1 ,...F capacitor connected as close to the pin as is possible.

;J
"a

~

Vee

0

----I

VIDfO
IN

R12

33k
C14

I

»
"a

R VIDEO OUT

R

CRT VIDEO AMPLIFIER

C3

"2-

-

(GREEN CHANNEL)
RI

=G>--1000Dill~

754

"

~.

V+
+60V

O·

: • "'. ,w.

:::J

fn

o

~r

=G>--1mNnlli~
"

c

if

.,,,. ,w.

TO CRT CATHODE

&>

a

=G>--1mNnlli~
4. GAIN ADJ.

A1

!S'"

G
VIDEO 0
IN

,

,--

I

BLANKING
BRIGHTNESS

~

A2

LM1204
COMPOSITE
VIDEO SYNC
SEPARATOR

:::J

c:

Vee

BACK PORCH
CLAMP
GENERATOR

+/-

HSYNC
PROCESSOR

G VIDEO OUT

G FEEDBACK
(CUTOFF ADJU5T)

-=

I

BP
CONTRA5T - WIDTH
BRIGHTNE5S
ADJU5T

BLANK
GATE
IN

10PF

BlANKING SIGNAL

~INGPERIOD
TUH/II238-17

FIGURE 7. The LM1204 driving cascade CRT video amplifiers and operating with blanking. The video signal Is level shifted to the user adjustable blank level
during the blanking period. Brightness control DC offsets the video signal relative to the fixed blank level and is accomplished by potentiometer R7. See FIgure 5
for explanation of adjustments. Each Vee pin should be bypassed with a 0.01 ,...F and a 0.1 ,...F capacitor connected as close to the pin as is possible.

to~U'n

iii

Typical Applications Circuits (Continued)
'cc

+12'1

R2
27k

(+4V)

~45

~22~2'
30

68'

BLUE

.23

R22

VIDEO~+....._,......jIHf---=::""'1-j

IN

RED
VIDEO@+.....-,......jHf---=::.....1-j
IN

...

.20

RIO

...68..17

GREEN

VIDEO ~+'-_-.41-+-==-4-1
IN
C13

O,'pF

CONTRAST

BP WIDTH

±H!HV
SYNC

IN

75

TLlH/11238-18

FIGURE S. Complete circuitry for an RGB CRT video board using the LM1204 and LH2426AS.
The video output signals from LH2426AS are AC coupled and diode clamped to greater than SOV.

3-98

Typical Applications Circuits (Continued)

471/2W

...
...

11

471/ZW

8

471/'lW

6

O.
NC
NC

220k

m"D'~

., o-JoNr-t---+-C

1k

COTOND'~

DI

00"""''r-....---f---f

CRT SOCKET

FIGURE 8. (Continued)

3·99

&I
TL/H/11238-20

LM1204

~

DC OFFSET CONTROl
(ALL THREE CHANNELS)

'a

0.1

~

Vee

»
'a

Your 1

'2.

R13
SOk

&
o·

. .".. "". H3>~""-

= I

:

~"""
.".. "".

H3>-

A1

A GAIN ADJ.

CD

!'F

n

~i"

c

;:

Your 2

l'
a
:>

10k

~~H3>-

~

8

~

10

A2

1

I

10 !'F

I

10 !'F

LM1204

VIN3~P.-

7::1

COMPOSITE
VIDEO SYNC
SEPARATOR

BLANKING
BRIGHTNESS

BACK PORCH
CLAMP
GENERATOR

+/-

H SYNC
PROCESSOR

Your 3

10k

10!,F
DC OFFSET CONTROL, Vour 3

TLlH/11238-19

FIGURE 9. Three channel high frequency amplifier with gain and DC offset control (non-video application). Each Vee pin should be
bypassed with a 0.01 p.F and a 0.1 p.F capacitor connected as close to the pin as Is possible.

~National

~ Semiconductor

LM1391 Phase-Locked Loop
General Description
• Output transistor with low saturation and high voltage
swing
• APe of the oscillator with a synchronizing signal
• De controlled output duty cycle
• ± 300 Hz typical pull-in
• Linear balanced phase detector
• Low thermal frequency drift
• Small static phase error
• Adjustable De loop gain

The LM1391 integrated circuit has been designed primarily
for use in the horizontal section of TV receivers, but may
find use in other low frequency signal processing applications. It includes a stable veo, linear pulse phase detector,
and variable duty cycle output driver.

Features
• Internal active regulator for improved supply rejection
• Uncommitted collector of output transistor

Schematic Diagram
PRE·oRIVER

OSCILLATOR

OSCillATOR

REGULATOR
REGULATOR
VOLTAGE

TIMING

.,

J3D

.8

"'

2.111

6

PHASE DETECTOR

.14

Uk

Uk

5

PHASE
DETferDA
OUTPUT

•• } SAWTOOTH

INPUT

OUTPUT

OJ
R2
8.Ik

.J

7.&11

••

2.4.

"

".
'20

'lD

.21

..

185

,,"

0'
SYNC
INPUT

TLlHI7889-1
(') Pin 4 Base of 016 (LM1391) for use with (+) flyback pulse

3-101

•

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Ottlce/Dlstrlbutors for availability and specifications.
Supply Current
4OmAoc
Output Voltage
40Voc
Output Current
3OmAoc
Sync Input Voltage (Pin 3)
5.0Vp-p

Electrical Characteristics TA =
Parameter

Flyback Input Voltage (Pin 4)
5.. 0Vp-p
Power Dissipation (Package Limitation)
1000mW
Plastic Package (Note 1)
Operating Temperature Range (Ambient)
O"C to + 70"C
Storage Temperature Range
- 65'C to + 150"C
Lead Temperature (Soldering, 10 sec.)
26O"C

25'C (see test circuit, all switches In position 1)
Conditions

Regulated Voltage (Pin 6)

Is = 22mAoc

Min

Typ

Max

B.O

B.B

9.2

Supply Current (Pin 6)

Units
Voc

20

Collector-Emitter Saturation Voltage
of Output Transistor (Pin 1)

ICI = 20 rnA

mAoc

0.30

Pin 4 Voltage

0.40

Vee

2.0

Voc

Oscillator Pull-in Range

AdjustRH

±300

Hz

Oscillator Hold-in Range

AdjustRH

±900

Hz

0.5

pos

±3.0

HzlVoc

Static Phase Error

.1f = 300 Hz

Free-running Frequency Supply
Dependance

S1 in position 2

Phase Detector Leakage (Pin 5)

All switches in position 2

±1.0

poA

Sync Input Voltage (Pin 3)

2.0

5.0

Vp-p

Sawtooth Input Voltage (Pin 4)

1.0

3.0

Vp-p

Maximum Oscillator Frequency
kHz
500
Note 1: For operation In ambient temperatures above 25'C, the device must be derated baaed on a 150'C maximum lunctlon temperature and a thermal resistance
of 120'C/W lunctlon to ambient.

Typical Performance Characteristics
Frequency Drift vs Warm-Up
Time
30
20

REFERENCE FREQUENCY

f0- r- to "1&,750Hz

150
100

10

1.0

=

~

REFERENCE FREQUENCY
fo = 1&,760 Hz

1:
~

..

60

-20

0

I\.

-30

-60

.... r-....

-100

j,~~o

-150

-40

-200
0

15

30

46

60
TIME

15

(.1

80 106 120

x lOB

~

-ZOO ppm! C

~

(MAY 8E COMPENSATEO_ rWITH N220 CAPACITORI - r-

-50
0

10

REFERENCE FREQUENCY

6.6

fa -16, 750Hz

f0- r-

6.0

0
-10

Output Duty Cycle vs VM
Voltage

Frequency vs Tempereture

20

30

40

50

c-

~

60 10

AM81ENT TEMPERATURE ( CI

10

..~..
>
>

5.5
6.0
4.6

...-

4.0

3.5

".

".

3.0
2.6
0

10 20 30 40 50 60 10 80 80
ptN 1 OUTPUT DUTY CYCLE ""

TL/H/7889-3

3-102

Application Information
DC Loop Gain p.{J '" 3.2 X 10- 5 Rofo Hz/rad
Noise Bandwidth

The following equations may be considered when using the
LM1391 in a particular application.
R201 = R301 =

Vee - 8.6 n
0.02

1
fo '" - R
C Hz1.5k';; Ro < 51k
0.6 0 0
R204'" 10 Ro
C203 = C204 "" 600

Damping Factor
7TRX2
K "" --Ccp.{J
2 Ry

f~(HZ) F

Test Circuit

Vee
3tlV

lk

2k

lk

880DpF

12k
lOOk

3.3k

02
S2
12.. PULSE}
{ +50V FOR
LM1311 ----.

TLlHI7889-4

Connection Diagram
Dual-In-Llne Package
OUTV CYCLE
CONTROL

OSCILLATOR
TIMING

REGULATOR
VOLTAGE

PHASE
DETECTOR
OUTPUT

OUTPUT

GNU

SYNC
INPUT

SAWTOOTH
INPUT

Top View
Order Number LM1391N
See NS Package Number N08E
3-103

TL/H17889-2

9- . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

9-

~

Typical Applications
VCC
24VTYP

Rl0l
620
lW

Rl06
2.7k
Rl07
2.4k

R110
1.2k
112W

TO YOKE
RIll
Uk
12", FL YBACK PULSE
+4OV FOR lMI391

-20V
NEG
SYNC

TL/HI7889-5

FIGURE 1. TV Horizontal Processor
VCC
24VTYP

R201

R203
3k

R204

R206
2.7k
R207
2.4k

RO

FRED
TRIM

-

Co

Ry

'='

~

R202
1.5k

lM1391

3 Vp·p INPUT
SYNCHRONIZING SIGNAL
TL/HI7889-8

FIGURE 2. General Purpose Phase·Lock Loop
(See Appllcatlonllnformatlon)

3·104

Typical Applications (Continued)
Vee
24VTYP

FREQADJ
R30a
25k

R305
2.5k

R30l

R302
1.7k

R303
lk

R307
Uk

--+---+-0
OUTPUT
PULSE

T

e301

PULSE·WIDTH
MODULATlDN
TL/H17889-7

FIGURE 3. Variable Duty Cycle Oscillator
(See Applications Information)

3-105

~ r-------------------------------------------~------------------------------~

C'oI
CD

....
!I ~National
~ Semiconductor
LM1823 Video IF Amplifier/PLL Detector System
General Description

Features

The LM1823 is a complete video IF signal processing system on a chip. It contains a 5-stage gain-controlled IF amplifier, a PLL synchronous amplitude detector, self-contained
gated AGC, and a switchable AFC detector. The increased
flexibility of the LM1823 makes it suitable for a wide variety
of television applications where high quality video or sound
carrier recovery is required. These include home receiver
video IFs, cable and subscription TV decoders, and parallel
sound IF/intercarrier detector systems. Typical operating
frequencies are 38.9 MHz, 45.75 MHz, 58.75 MHz, and
61.25 MHz.

•
•
•
•
•
•
•
•
•
•
•
•

Low differential gain and phase
IF and detector pin compatible with LM1822
Common-base IF inputs for SAW filters
True synchronous video detector using PLL
Excellent stability at high system gains
Noise-averaged gated AGC system
Uncommitted AGC comparator input
Internal AGC gate generator
Superior small-signal detector linearity
AFC detector with adjustable output bias
9 MHz video bandwidth
Reverse tuner AGC output

Test Circuit Measure parameters at indicated test points
V28

12V

11k

IFOU~'01

30k

...-,.....+-0.27

•

10k

Vlo-Jlll._+-----,
12.
.0

90

3

V3.V4o--'VV'v--4-'V9DI/Iro''t-----t
180
1/IW

0.01

aWl

'I'_ V6

10k Y23.V26

10k

2k
o-'W~,""".::r--.
D-'lNIr----.

1l1li:

V19.V2D

lao

Wo-~~----~

12V

6k

68k

6k
"::'

V...
6¥-1..

.
..
12V

T1 • 50n unbal to bal
Mlni-Circults Lab TM01-1T

Order Number LM1823N
See NS Package N28B

Ll . 9YoT} #22 wire
L2 • 4V. T
on 31,s" form with
L3 -

av.T

HF core, shielded

All caps in "F unless noted

3-106

TL/H/5222-1

....~

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speCifications.
Power Supply Voltage, V2
15V
IF Supply Current, 15
60mA
AGC Gate Voltage, V14
±5V

Video Output Current, 116
PLL Filter Current, 118

Detector Input Signal, VDET
Power Dissipation
Thermal Resistance, iJJA
Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

10mA
5mA

1 Vrms
2W
50'C/W
125'C
O'Cto 70'C
- 65'C to + 150'C
260'C

CCI
N
W

DC Electrical Characteristics PARAMETERS GUARANTEED BY ELECTRICAL TESTING
TA=25'C, Test Circuit, vIF=VDET=O, VPH=4V, VCOMP=4V, and all switches in pOSition 0 (open) unless noted.
Min

Typ

Max

Units

12V Supply Current,ll + 12

VAGc=6.7V. VCOMP=6V

35

60

BO

mA

IF Regulator Voltage, V5

VAGc=6.7V, SW4 Position 1

5.B

6.4

7.0

V

IF Input Voltage, V7, VB

VAGc=2V, SW 2,3,4 Position 1

3.2

3.7

4.1

V

IF Decouple Offset, V6-V9

VAGc=2V, SW 2, 3, 4 Position 1

0

±30

mV

Parameter

Conditions

IF Peaker Voltage (Max Gain), V3, V4

VAGc=2V, SW 2, 3, 4 Position 1

2.3

3.0

3.6

V

IF Output Current, 11

VAGc=9V, SW 2, 3, 4 Position 1,
Measure V1,Il =(12-V1)/50

3.1

5.5

7.B

mA

IF Peaker Voltage (Min Gain), V3, V4

VAGc=9V, SW 2, 3, 4 Position 1

5.5

6.2

Detector Input Voltage, V2B

VAGc=6.7V, SW 1, 4 Position 1

4.3

4.9

5.5

V

Limiter Tank Voltage, V24, V25

VAGc=6.7V, SW 1, 4 Position 1

6.4

7.0

7.6

V

V

AFCTankVoltage, V23, V26

VAGC = 6.7V, SW 1, 4 Position 1

4.3

4.9

5.5

V

VCO Tank Voltage, V19, V20

VAGc=6.7V, SW 1, 4 Position 1

4.7

5.2

5.7

V

AGC Sync Threshold, V17

SW 1, 2 Position 1, Adjust VCOMP for 113 = 0

3.B

4.0

4.2

V

AGC Filter Leakage Current,I13

SW 1, 2, 4 Position 1

0

±5

p.A

AGC Filter Charge Current, 113

SW 1, 2 Position 1, VCOMP= 3.5V

1.6

2.2

2.B

mA

AGC Filter Discharge Current, 113

SW 1, 2 Position 1, VCOMP=4.5V

-0.45

-0.70

-0.90

mA

RF AGC Leakage current, 111

VAGC= 2V, All Switches Position 1,
Measure V11, 111 =(12-V11)/6000

0

20

p.A

RF AGC Output Current, 111

VAGC = 10V, All Switches Position 1,
Measure V11,Ill = (12-V11)/BOOO

3·107

1.5

1.B

mA

•

Detector AC Set-Up Procedure sw 1,4 position 1, VAGC= OV
1. Apply VOET = 10 mVrms, 45.75 MHz CW at the detector input. Tune L1 for maximum AC signal at pin 25, measured with a lOx
FET probe or through a 1 pF capacitor to prevent loading of the limiter tank'.
2.lnctease vOET to 60 mVrms. Adjust L3 until the PLL locks, as indicated by a DC voltage at the video output pin 16.
3. With the detector locked, adjust L3 for 4.0V at pin 18.
4. Adjust VPH for maximum detector efficiency by monitoring pin 16 for a minimum DC voltage.
5. Adjust L2 for 3.OV at pin 27 (on sensitive slope of AFC curve).

AC Electrical Characteristics PARAMETERS GUARANTEED BY ELECTRICAL TESTING
TA = 25°C, Test Circuit, detector set-up as above, f = 45.75 MHz, VAGC = 6.7V, VCOMP = 4V, and all switches in position 0
(open) unless noted.
Min

Typ

IF Amplifier Gain, VOUT!VIF (Note 1)

VAGc=2V, sw 2,3,4 Position 1,
v1F=500 ,..Vrms

25

35

VAGC for 15 dB Gain Reduction

SW 2, 3, 4 Position 1, VIF = 2.8 mVrms,
Adjust VAGC for Same VOUT as Gain Test

4.2

4.6

5.0

V

VAGC for 45 dB Gain Reduction

SW 2, 3, 4 Position 1, VIF = 89 mVrms,
Adjust VAGC for Same VOUT as Gain Test

5.1

5.5

6.1

V

Zero Carrier Level, V16

SW 1, 2, 4 Position 1, VOET=O

6.6

7.4

8.4

V

Detected Output Level, a V16

SW 1, 2, 4 Position 1, VOET= 60 mlVrms,
Measure Change in V16 from Zero
Carrier Test

2

3

4.3

V

Overload Output Voltage, V16

SW 1, 2, 4 Position 1, vOET = 600 mVrrns

2

3

V

AFC Output Voltage (OFF), V27

sw 1,2,4 Position 1, VOET= 0

2.8

3.0

3.2

V

AFC Minimum Output Voltage, V27

SW 1, 4 Position 1, vOET = 60 mVrms,
46.75 MHz

0.5

1.0

V

AFC Maximum Output Voltage, V27

SW 1, 4 Position 1, VOET = 60 mVrms,
44.75 MHz

9

10

V

PLL Pull-In Range, af

SW 1, 4 Position 1, VOET = 60 mVrms,
Vary Frequency and Measure the
Difference between Lock Points

2

3

MHz

Parameter

Note 1: The IF amplifier gain is spac~ied wilh the
actual application will typically be 26 dB higher.

Conditions

IF output connected to a 500

Max

Units
dB

measurement system which results in a 250 loaded impedance. The gain in

3-108

an

r-

iii:
....
CD

Design Parameters NOT TESTED OR GUARANTEED Typical Application Circuit

N

Parameter

Typ

Units

Maximum System Operating Frequency
IF Input Impedance (Differential Pin 7-8), 45 MHz
IF Output Impedance, 45 MHz
IF Gain Control Range
Detector Input Impedance, 45 MHz
Detector Output Bandwidth, - 3 dB
Detector Differential Gain (Note 2)
Detector Differential Phase (Note 2)
Detector Output Harmonic Levels below 3 Vp-p Video
VCO Temperature Coefficient

70
60
10
55

MHz

2

9
3
1
-40
-150

Co)

0
kO
dB
kO
MHz
%
deg
dB
ppml"C

Note: 2: Differential gain and phase measured with the limiter tank adiusted for minimum differential phase.

Typical Application 45.75 MHz (see Application Notes)

'"
11.001

30t

•

430

AFC
OUTPUT
10k

.".
2k
680

IF
AMPLIFIER

IF INPUT

'"

'" RFAGC

;:150

10.

OUToPU_T-'\',..70,..,......._....:.+-1.

AGe

3Dk

DELAy>-4I-------....;;.t+1
ADJUST

20k

v

16k

TUH/5222-2
SAW Filter - MuRata SAF45MC/MA
L1 - 9%T} #22 wire
L2 - 4%T
on 3.1a" form with
L3 • a%T

HF core, shielded

All caps in ",F unless noted

3-109

II

Application Notes Refer to Typical Application Circuit
'7

COMMENTS ON RF Coupling
The LM1823 is a high gain RF system which is critically
dependent on the ground plane and positioning of the external components. For this reason, it is suggested that the
printed circuit layout shown in Figure 3 be strictly adhered
to.
The most sensitive points in the system to unwanted RF
coupling are the IF input pins 6-9. There are two different
signals which can cause different problems when coupling
into the IF inputs. If the IF output is coupling to the input, it
can cause bandpass tilting, peaking, and in extreme cases,
oscillation. The other Signal which can couple to the IF inputs is the PLL detector VCO. This VCO coupling can cause
AFC skewing, non-symmetrical detector pull-in, and failure
of the detector to acquire lock at weak signal levels. These
input coupling problems will be most acute at maximum gain
and will decrease as the IF is gain reduced by AGC action.
The differential IF inputs offer a large amount of inherent
rejection to unwanted RF coupling. Therefore, A FULLY
BALANCED INPUT SOURCE IS MANDATORY. The input
leads must be routed together and socketless operation is
recommended above 50 MHz. However, residual coupling
may still dictate the maximum IF amplifier gain which can be
taken (see Pin Descriptions).

~--"'..J\Jy,,-&.2V

' - - -.....IIJ""'"-6,2V
TUH/S222-3

FIGURE 1. IF Input Stage
Both the input network to pins 7 and 8 and decoupling capacitor between pin 6 and pin 9 must be as close to the
device as is physically possible to minimize RF coupling.
Pin 10-IF Ground: Pin 10 grounds the IF and AGC circuits
in the LM 1823. It is separate from the detector and chip
substrate grounds to prevent internal coupling.
Pin II·RF AGC Output: Pin 11 is connected to an opencollector NPN device. It begins to conduct current when the
voltage on the AGC filter capaCitor at pin 13 exceeds the
voltage set at the takeover pin 12 by approximately 0.6V.
When connected to a resistor to 12V, this produces a falling
voltage at pin 11 suitable for reverse tuner AGC inputs.
Pin 12·RF AGC Takeover Adjust: The voltage preset at pin
12 determines when the IF stops gain reducing and the tuner begins gain reducing as the pin 13 AGC filter capaCitor
voltage increases with signal level. A higher voltage at pin
12 delays the RF AGC takeover until more IF gain reduction
has been taken (higher Signal levels), while a lower voltage
limits the IF gain reduction before RF takeover.
When the LM1823 is being used without a tuner, pin 12 may
be connected to supply.
Pin 13·AGC Filter: Pin 13 is a push-pull current source output from the AGC comparator. The comparator compares
the negative sync tips of noise-averaged pin 17 video with
an internal4V reference. Increases in signal produce a current out of pin 13 which charges the filter capacitor, while
decreases discharge the capaCitor. The resulting change in
voltage at pin 13 controls the IF and tuner gains to maintain
the pin 17 sync tip level a:t 4V. An optional capaCitor between pin 13 and the takeover pin 12 couples the ripple
produced by a rapidly varying signal into the takeover pin to
enhance the AGC loop response.
Pin 14-AGC Gate Generator Time Constant: The AGC
comparator is gated on during sync time by a pulse from an
internal gate generator. The gate pulse which activates the
comparator is derived from the sync pulse in the same video
which feeds the comparator input (see pin 17 description).
An RC time constant on pin 14 determines the slice level on
the leading edge of the sync pulse at which the comparator
is gated on. This level is approximately VSLICE= 1/(2RC) in
millivolts above the sync tip, and should be set at :5:25% of
the sync amplitude. Note that VSLlCE only determines when
the AGC comparator turns on, and is unrelated to the comparator reference.
In the Typical Application, VSLICE= 100 mV, or 10% of a tv
sync pulse. Increasing VSLICE improves the AGC recovery
from step changes in signal level but increases the risk of
video interaction. When modifying the time constant,
change the capaCitor value only.

PIN DESCRIPTIONS
Pin 1·IF Amplifier Output: Pin 1 is connected to an opencollector NPN device. The load on pin 1 must be returned to
the 12V supply as close as possible to pin 2. The IF output
load may be either resistive as shown in the Typical Application, or an LC tank. The tank need only be used if a tunable
bandpass characteristic is desired, or in conjunction with a
sound trap.
Pin 2-12V Supply: The LM1823 requires a nominal 12V
supply but can accept a ± 10% variation. Pin 2 must be RF
decoupled to a good ground as close as possible to the IC.
Pins 3, 4·IF Gain Adjustment: Pins 3 and 4 are connected
to the two emitters of the 4th IF differential amplifier such
that the gain of the stage is set by the impedance between
the pins. There is an internal 13600 resistor to set the minimum gain when the pins are' left open. Adding an external
resistor increases the gain by the ratio of the parallel impedance to the original 13600. The pin 3 to 4 external resistor
primarily affects the maximum IF gain; the relative gain increase goes away over the first 20 dB of AGC.
Pin 5·IF Supply: The IF supply employs an Internal 6.4V
shunt regulator which is fed by an external dropping resistor
from pin 2 to pin 5. RF decoupling from pin 5 to the pin 10
ground plane is critical.
Pins 6-9-IF Input and Decouple Pins: The LM1823 uses a
common-base differential input stage as shown in Figure 1.
Pins 7 and 8 connect directly to the emitters of the input
devices, while pins 6 and 9 decouple the DC feedback loop
at the bases.
The gain of a common-base amplifier depends inversely on
the source impedance. The LM1823 is designed to operate
from differential impedances in the 5000 to 20000 range,
which is typical for surface acoustic wave (SAW) filters. Alternatively, the IF may be used with a transformer input configuration similar to that shown in the Test Circuit, as long as
the required source impedance is maintained. In all cases a
balanced source must be used.

3-110

Application Notes (Continued) Refer to Typical Application Circuit
Pin IS-Supply Decouple: Pin 15 is an additional connection to the 12V supply to allow RF decoupling on the detector side of the chip.
Pin 16-Video Output: Pin 16 is a Darlington NPN emitterfollower output supplying negative sync video. With no detector input signal the pin 16 voltage sits at the zero carrier
level, representing peak white. As the input signal level increases, the pin 16 voltage decreases towards black. The
sync pulses are normally the most negative portion of the
recovered video.

15000 resistor. Increasing the Q (larger C) improves stability but reduces the VCO control range. The tank shown in
the Typical Application will yield a loaded Q of around 15,
providing stable operation with a control range in excess of
2 MHz.
Pin 21-Substrate Ground: Pin 21 grounds the chip substrate along with all of the AFC and PLL detector grounds.
Pin 22-Detector Phase Adjust: The video detector requires a reference Signal in phase with the input Signal carrier for maximum detection efficiency. However, the action of
the PLL inherently sets the veo phase in quadrature (at 90
degrees) with the limiter output. Therefore a variable phase
shift network, controlled by pin 22, is used internally between the VCO and video detector to insure proper phaSing.
Pin 22 requires an adjustment voltage centered at % supply
with ± 2V of control range.
The pin 22 adjustment procedure described in the Detector
AC Set-Up Procedure is an open loop approach where the
voltage is adjusted for maximum detected output with a
fixed detector input signal. In the Typical Application, with
the detector input being fed from the IF amplifier and the
AGC loop active, the pin 22 adjustment is made by maximizing the AGe filter voltage at pin 13. In all cases the detector
phase adjustment must be performed after the limiter is
tuned.
Pins 23, 26-AFC Tank: A parallel LC tank between pins 23
and 26 sets the center of the AFC characteristic. The internal resistance is typically 20 kO, so that Q will be dominated
by the coil Rp. The L/C ratio shown in the Typical Application maximizes Q to provide a steep AFC output slope.

12V

18
10k
5k

17
lk
lk6
16

-

15

VIDEO

'::"

OUTPUT
TL/H/5222-4

FIGURE 2. Adjustable Recovered Video Level
Pin 17-AGC Comparator Input: External negative sync video is fed to the AGC comparator and gate generator via pin
17. An internal low pass filter removes high frequency noise
and transients. The peak-to-peak video level with the AGC
loop active is determined by the difference between the
zero carrier level at pin 17 and the 4V sync tip level being
held by the AGC comparator (see pin 13 description).
When the LM1823 is being used to recover normal video,
pin 17 may simply be returned to pin 16. This results in a
nominal 3 Vp-p video level, but which is subject to variations
in the pin 16 zero carrier level. The network shown in Figure
2 can be used to change the zero carrier at pin 17, thus
providing an adjustable recovered video level. The pin 16
video level should be maintained at between 1 Vp-p minimum and 4 Vp-p maximum.

A quadrature input signal is required at the AFC tank to
operate the AFC detector. This signal is derived by light
capacitive coupling from the limiter tank. For applications at
45 MHz and above, the stray printed circuit capaCitance
from the adjacent limiter tank couples sufficient signal for
proper operation. However, at lower IF frequencies, small (1
pF-5 pF) capacitors may be required between the adjacent
pins as shown in the Test Circuit.
A second function of pins 23 and 26 allows turning the AFC
detector OFF by grounding either side of the AFC tank. Up
to 2 kO may be placed in series with the switch connection
to prevent unbalancing the tank.
Pins 24, 2S-Llmlter Tank: A parallel LC tank between pins
24 and 25 forms the tuned load for a single stage limiting
amplifier which strips amplitude information from the Signals
feeding the AFC and phase detectors. The amplifier has a
small signal gain of approximately 50, with internal Schottky
diodes across the tank to limit the output amplitude to 500
mVp-p.

In suppressed sync systems, the recovered video at pin 16
may require processing to restore normal sync amplitude
before being fed to pin 17. In this case, it is mandatory that a
DC path be maintained for the zero carrier level through any
external circuitry. Any DC level shift between pins 16 and 17
will have the effect of changing the video level as previously
described.
Pin 18-PLL Filter: Pin 18 is connected to both the output of
the phase detector and the control input of the VCO. The
polarity of the veo control characteristic is such that increasing the pin 18 voltage increases the VCO frequency.
An external resistive divider at pin 18 serves two functions.
The divider parallel impedance sets the gain of the phase
detector, while the divider ratio places the quiescent voltage
at the center of the VCO control characteristic. The 20 kO
impedance, % supply divider shown in the Typical Application has been chosen to provide optimum performance. The
series capacitor and resistor to ground complete the PLL
filter.
An internal zener clamp to ground at pin 18 prevents the
phase detector output from pulling the VCO control input
over 5.6V. For this reason, external voltages should not be
forced at pin 18 to avoid damaging the clamp.

The linearity of the detector video outputs depends directly
on limiter tuning. Making the limiter adjustment based on
maximum signal level at pins 24, 25 as outlined in the Detector AC Set-Up Procedure results in nearly optimum output linearity. However, to completely null the output differential phase the limiter should be adjusted while monitoring
this parameter.
Pin 27-AFC Detector Output: Pin 27 is push-pull current
source output from the AFC detector. The polarity is such
that pin 27 sources current when the input signal is below
the center frequency, and sinks current above the center
frequency. An external resistive divider sets both the gain
and quiescent output voltage of the AFC. Although the net-

Pins 19, 20-VCO Tank: A parallel LC tank between pins 19
and 20 sets the VCO center frequency. The tank Q is
RpLlXc, where RpL is the coil Rp loaded by an internal
3-111

Application Notes (Continued) Refer to Typical Application Circuit
work shown in the Typical Application sets up the output at
Y4 supply, it could easily be changed to Va supply by using
equal-valued resistors. When setting up the AFC detector,
the tank should always be tuned so the output is at the
quiescent divider voltage with the desired center frequency
applied.

PIn 28·Detector Input: Pin 28 is Internally DC-biased and
requires an AC-coupled input signal. The network between
pins 1 and 28 should not allow over 1 Vrms at the input
during signal transients to prevent overloading the detector.
When a tank Is being used for the IF output load, a capacitive divider may be used from pin 1 to pin 28 in which the
series equivalent capacitance resonates with the coil.

TL/H/5222-5

FIGURE 3. Printed Circuit Layout (Component Side).

3-112

~Nattonal

~ Semiconductor

LM 1881 Video Sync Separator
General Description

Features

The LM1881 Video sync separator extracts timing information including composite and vertical sync, burst/back porch
timing, and odd/even field information from standard negative going sync NTSC, PAL', and SECAM video signals with
amplitude from 0.5V to 2V pop. The integrated circuit Is also
capable of providing sync separation for non-standard, faster horizontal rate video signals. The vertical output is produced on the rising edge of the first serration in the vertical
sync period. A default vertical output is produced after a
time delay if the riSing edge mentioned above does not occur within the externally set delay period, such as might be
the case for a non-standard video signal.

• AC coupled composite input Signal
• > 10 kO input resistance
• < 10 mA power supply drain current
• Composite sync and vertical outputs
• Odd/even field output
• Burst gate/back porch output
• Horizontal scan rates to 150 kHz
• Edge triggered vertical output
• Default triggered vertical output for non-standard video
signal (video games-home computers)

Connection Diagram
LM1881N
Vee

COMPOSITE
SYNC OUTPUTo-------I

-----1I

1------05-12V

0.1 J.'F

COt.lPOSITE
VIDEO INPUT O

2

7

1 - - - -__-0 ODD/EVEN

5

1-

OUTPUT

VERTICAL
SYNC OUTPUTo-------I 3

------0

BURST/BACK PORCH
OUTPUT

COt.lPOSITE
VIDEO INPUT
COMPOSITE

::t~===:;1:=::H=::;~=J:=:;t=::;!==;==t.===t==t;==;;:=t;:

SYNCOUTPUT:=t::::::::t=::1=::=t::::~::t=::=t::::::=t::~t:::t::::t:::!::

VERTICAL
SYNC OUTPUT
BURST OUTPUT

...r---------

ODD/EVEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
OUTPUT

Tl/H/9150-1

Order Number LM1881M or LM1881N
See NS Package Number M08A or N08E

'PAL In this datasheet refers to European broadcast TV standard "'Phass Alternating Une"', and not to Programmable Array Logic.

3-113

..-

I..-

:::&

....I

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

ESD Susceptibility (Note 2)

3 Vpp (Vee = 5V)
6 Vpp (Vcc :2: 8V)

Output Sink Currents; Pins 1, 3, 5

5mA

Output Sink Current; Pin 7
Operating Temperature Range

260"C
215°C
220"C

See AN-450 "Surface Mounting Methods and their Effect on
Product Reliability" for other methods of soldering surface
mount devices.

2mA
1100mW

Package Dissipation (Note 1)

+ 150"C
2kV

Soldering Information
Dual-in-Line Package (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

13.2V

Input Voltage

-65°C to

Storage Temperature Range

O"C-70"C

Electrical Characteristics
Vee = 5V; Rset = 680 ko.; T A = 25°C; Unless otherwise specified
Parameter

Conditions

Supply Current

Outputs at Logic 1

DC Input Voltage

Pin 2

Input Threshold Voltage

Note 5

Input Discharge Current

Pin 2; VIN = 2V

Input Clamp Charge Current

Pin 2; VIN = tV

RSET Pin Reference Voltage

Pin 6; Note 6

Composite Sync. & Vertical
Outputs

lOUT = 40 /LA;
Logic 1

Vee = 5V
Vec = 12V

lOUT = 1.6mA
LogiC 1
Burst Gate & Odd/Even
Outputs

lOUT = 40 /LA;
Logic 1

Composite Sync. Output

lOUT = -1.6 mA; Logic 0; Pin 1

Vertical Sync. Output

lOUT = -1.6 rnA; Logic 0; Pin 3

Burst Gate Output

lOUT = -1.6 mA; Logic 0; Pin 5

Odd/Even Output

lOUT = -1.6 mA; Logic 0; Pin 7

Vcc = 5V
Vee = 12V

Typ

Tested
Limit (Note 3)

Design
Limit (Note 4)

Units
(Limits)

5.2
5.5

10
12

mAmax
mAmax

1.5

1.3
1.8

Vmin
Vmax

:70

55
85

mVmin
mVmax

11

6
16

/LAmin
/LAmax

0.8

0.2

mAmin

1.22

1.10
1.35

Vmin
Vmax

4.5

4.0
11.0

Vmin
Vmin

Vee = 5V
Vee = 12V

3.6

2.4
10.0

Vmin
Vmin

Vee = 5V
Vee = 12V

4.5

4.0
11.0

Vmin
Vmin

0.2

0.8

Vmax

0.2

0.8

Vmax

0.2

0.8

Vmax

0.2

0.8

Vmax

230

190
300

/Lsmin
/Lsmax

4

2.5
4.7

/Lsmin
/Lsmax

65

32
90

/Lsmin
/Lsmax

Vertical Sync Width
Burst Gate Width

2.7 ko. from Pin 5 to Vcc

Vertical Default Time

Note 7

Note 1: For operation in ambient temperatures above 25'C, the device must be derated based on a 150'C maximum Junction temperature and a package thermal
resiatence of 110' C/W, junction to ambient.
No1e 2: ESD susceptibility test uses the "human body model, 100 pF discharged through a 1.5 kO resisto('.
Nole 3: Typicals are at TJ

~

25'C and represent the most likelY parametric norm.

Note 4: Tested Umits are guaranteed to National's AOQL (Average Outgoing Quality Level).
No1e 5: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontsl output pulse.
Nole 6: Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins I, 3, 5, and 7) to the RSET pin (Pin 6).
Nole 7: Delay time between the start of vertical sync (at input) and the vertical output pulse.

3-114

Typical Performance Characteristics
Vertical Default
Sync Delay Time

Raet Value Selection
va Vertical Serration
Pulse Separation

•

D.I
0.4

V

0.2
0.0
10

15

20

25

3D

o

VERTICAL SERRATION
PULSE SEPARATION

(1")

I.0

Ci'
3

.1

0,8

0.4

/

.1

40

60

80

100

o

Supply Current va
Supply Voltage

"""-

•o

-

I

o

10
SOD

10
BURST/BLACK LEVEL
GATE TIME
(jI')

10

r-- r--

0.0

/

V

0.0
20

400

I

IDO
200
300
400
VERTICAL PULSE WIDTH

0.4
0.2

0.2

o

0.6

Vertical Pulae
Width va Temperature

V

0.8

Q
3

/

J

VERTICAL DErAULT SYNC
DELAY TIWE
(p.)

Vertical Pulse
Width va Raet

/

0.8

/

3

.1

I.0

V

o.8
Ci

Burst/Black Level
Gate Time va Rut

va Rut

I.

20

80

70

o

10

12

TEMPERATURE (Oc)

(po)
TL/H/9150-2

•
3-115

-

-

I

~

r---------------------------------------------------------------------~

Application Notes
The LM1881 is designed to strip the synchronization signals
from composite video sources that are in, or similar to, the
N.T.S.C. format. Input signals with positive polarity video (in- .
creasing signal voltage signifies increasing scene brightness) from 0.5V (p-p) to 2V (p-p) can be accommodated.
The LM1881 operates from a single supply voltage between
5V DC and 12V ~C. The only required external components
beside power supply and set current decoupling are the input coupling capacitor and a single resistor that sets internal
current levels, allowing the LM1881 to be adjusted for
source signals with line scan frequencies differing from
15.734 kHz. Four major sync Signals are available from the
I/C: composite sync including both horizontal and vertical
scan timing information; a vertical sync pulse; a burst gate
or back porch clamp pulse; and an oddleven output. The
oddl even output level identifies which video field of an interlaced video source is present at the input. The outputs from
the LM1881 can be used to gen-Iock video camera/VTR
signals with graphics sources, provide identification of video
fields for memory storage, recover suppressed or contaminated sync signals, and provide timing references for the
extraction of coded or uncoded data on specific video scan
lines.
To better understand the LM1881 timing information and
the type of signals that are used, refer to Figure 2(a-e)
which shows a portion of the composite video signal from
the end of one field through the beginning of the next field.

COMPOSITE SYNC OUTPUT
The composite sync output, Figure 2(b), is simply a reproduction of the signal waveform below the composite video
black level, with the video completely removed. This is obtained by clamping the video signal sync tips to 1.5V DC at
Pin 2 and using a comparator threshold set just above this
voltage to strip the sync signal, which is then buffered out to
Pin 1. The threshold separation from the clamped sync tip is
nominally 70 mV which means that for the minimum input
level of 0.5V (p-p), the clipping level is close to the halfway
pOint on the sync pulse amplitude (shown by the dashed
line on Figure 2(a). This threshold separation is independent of the signal amplitude, therefore, for a 2V (p-p) input
the clipping level occurs at 11 % of the sync pulse amplitude. The charging current for the input coupling capacitor is
0.8 mA, whereas the discharge current is only 11 p.A, typically. This allows relatively small capacitor values to be
used-O.1 p.F is generally recommended.
Normally the signal source for the LM1881 is assumed to be
clean and relatively noise-free, but some sources may have
excessive video peaking, causing high frequency video and
chroma components to extend below the black level reference. Some video discs keep the chroma burst pulse present throughout the vertical blanking period so that the burst
actually appears on the sync tips for three line periods instead of at black level. A clean composite sync signal can
be generated from these sources by filtering the input signal. When the source impedance is low, typically 750, a
6200 resistor in series with the source and a 510 pF capacitor to ground will form a low pass filter with a corner frequency of 500 kHz. This bandwidth is more than sufficient to
pass the sync pulse portion of the waveform; however, any
subcarrier content in the signal will be attenuated by almost
18 dB, effectively taking it below the comparator threshold.
Filtering will also help if the source is contaminated with
thermal noise. The output waveforms will become delayed

from between 40 ns to as much as 200 ns due to this filter.
This much delay will not usually be significant but it does
contribute to the sync delay produced by any additional signal processing. Since the origin~1 video may also undergo
processing, the need for time delay correction will depend
on the total system, not just the sync stripper.

VERTICAL SYNC OUTPUT
A vertical sync output is derived by internally integrating the
composite sync waveform (Figure 3). To understand the
generation of the vertical sync pulse, refer to the lower left
hand section Figure 3. Note that there are two comparators
in the section. One comparator has an internally generated
voltage reference called V1 going to one of its inputs. The
other comparator has an internally generated voltage referance called V2 going to one of its inputs. Both comparators
have a common input at their noninverting input coming
from the internal integrator. The internal integrator is used
for integrating the composite sync signal. This signal comes
from the input side of the composite sync buffer and are
positive going sync pulses. The capacitor to the integrator
is internal to the LM1881. The capacitor charge current is
set by the value of the external resistor Rsat. The output of
the integrator is going to be at a low voltage during the
normal horizontal lines because the integrator has a very
short time to charge the capacitor, which is during the horizontal sync period. The equalization pulses will keep the
output voltage of the integrator at about the same level,
below the V1. During the vertical sync period the narrow
going positive pulses shown in Figure 2 is called the serration pulse. The wide negative portion of the vertical sync
period is called the vertical sync pulse. At the start of the
vertical sync period, before the first Serration pulse occurs,
the integrator now charges the capacitor to a much higher
voltage. At the first serration pulse the integrator output
should be between V1 and V2. This would give a high level
at the output of the comparator with V1 as one of its inputs.
This high is clocked into the "0" flip-flop by the falling edge
of the serration pulse (remember the sync signal is inverted
in this section of the LM1881). The "a" output of the "0"
flip-flop goes through the OR gate, and sets the RIS flipflop. The output of the RIS flip-flop enables the internal
oscillator and also clocks the OOO/EVEN "0" flip-flop. The
OOO/EVEN field pulse operation is covered in the next section. The output of the oscillator goes to a divide by 8 circuit,
thus resetting the RIS flip-flop after 8 cycles of the oscillator. The frequency of the oscillator is established by the
internal capacitor going to the oscillator and the external
Rsat. The
output of the RIS flip-flop goes to pin 3 and is
the actual vertical sync output of the LM 1881. By clocking
the "0" flip-flop at the start of the first serration pulse
means that the vertical sync output pulse starts at this point
in time and lasts for eight cycles of the internal oscillator as
shown in Figure 2.

"a"

How Rset affects the integrator and the internal oscillator is
shown under the Typical Performance Characteristics. The
first graph is "Rsat Value Selection vs Vertical Serration
Pulse Separation". For this graph to be valid, the vertical
sync pulse should last for at least 85 % of the horizontal half
line (47% of a full hOrizontal line). A vertical sync pulse from
any standard should meet this requirement; both NTSC and
PAL do meet this requirement (the serration pulse is the
remainder of the period, 10 % to 15% of the horizontal

3-116

Application Notes (Continued)
ST=ART.::....:0.:...F.:...FI:.:EL::.D...:.1.!:(0:.:DD;,!>+_ _ _ _ _ _ _ VERTICAL BLANKING INTtRVAL _ _ _ _ _ _---1

EQUALIZING
PULSES

h-J
63.5pa

-II31.81's

-+I

SERRATED
VERTICAL PULSE

~

+I

EQUALIZING--l
PULSES

I

--II--

--II-4.7pa

2.41'1

2301'.typ--I

--------~--------~

~------~---

ODD FIElD

EVEN FIELD

TlIH/9150-3

FIGURE 2. (a) Composite Video; (b) Composite Sync; (c) Vertical Output Pulse;
(d) Odd/Even Field Index; (e) Burst Gate/Back Porch Clamp

COMP~~~~

8

SUPPLY
VOLTAGE

REG

o--t--clC

VIDEO
INPUT

~~I'_Fo-2-t_+-_i4~--'

7

0001 EVEN
FIELD
INDEX

II

510 PF,I

!!sET
S80k
Vee

5

'Components Optional,
See Text

-

BURST GATEI
BACK PORCH
CLAMP

TL/H/9150-4

FIGURE 3

3·117

-

I

:&
-I

r-------------------------------------------------------------------------~

Application Notes (Continued)
half line). Remember this pulse is a positive pulse at the
integrator but negative in Figure 2. This graph shows how
long it takes the integrator to charge its internal capacitor
above V1.
WITH Rset too large the charging current of the integrator
will be too small to charge the capacitor above V1, thus
there will be no vertical synch output pulse. As mentioned
above, Rset also sets the frequency of the internal oscillator.
If the oscillator runs too fast its eight cycles will be shorter
than the vertical sync portion of the composite sync. Under
this condition another vertical sync pulse can be generated
on one of the later serration pulses after the divide by 8
circuit resets the RIS flip-flop. The first graph also shows
the minimum Rset necessary to prevent a double vertical
pulse, assuming that the serration pulses last for only three
full horizontal line periods (six serration pulses for NTSC).
The actual pulse width of the vertical sync pulse is shown in
the "Vertical Pulse Width vs Rset" graph. Using NTSC as an
example, lets see how these two graphs relate to each other. The Horizontal line is 64 /JoS long, or 32 /Jos for a horizontal half line. Now round this off to 30 /Jos. In the "Rset Value
Selection vs Vertical Serration Pulse Separation" graph the
minimum resistor value for 30 /Jos serration pulse separation
is about 550 kO. Going to the "Vertical Pulse Width vs Rset"
graph one can see that 550 kO gives a vertical pulse width
of about 180 ,","S, the total time for the vertical sync period of
NTSC (3 horizontal lines). A 550 kO will set the internal
oscillator to a frequency such that eight cycles gives a time
of 180 ,","s, just long enough to prevent a double vertical
sync pulse at the vertical sync output of the LM 1881.
The LM1881 also generates a default vertical sync pulse
when the vertical sync period is unusually long and has no
serration pulses. With a very long vertical sync time the integrator has time to charge its internal capacitor above the
voltage level V2. Since there is no falling edge at the end of
a serration pulse to clock the "0" flip-flop, the only high
signal going to the OR gate is from the default comparator
when output of the integrator reaches V2. At this time the
RIS flip-flop is toggled by the default comparator, starting
the vertical sync pulse at pin 3 of the LM 1881. If the default
vertical sync period ends before the end of the input vertical
sync period, then the falling edge of the vertical sync (positive pulse at the "0" flip-flop) will clock the high output from
the comparator with V1 as a reference input. This will retrigger the oscillator, generating a second vertical sync output
pulse. The "Vertical Default Sync Delay Time vs Rset"
graph shows the relationship between the Rset value and
the delay time from the start of the vertical sync period before the default vertical sync pulse is generated. Using the
NTSC example again the smallest resistor for Rset is 500
kO. The vertical default time delay is about 50 /Jos, much
longer than the 30 /Jos serration pulse spacing.
A common question is how can one calculate the required
Rset with a video timing standard that has no serration pulses during the vertical blanking. If the default vertical sync is
to be used this is a very easy task. Use the "Vertical Default

Sync Delay Time vs ,Rset" graph to select the necessary
Rset to give the desired delay time for the vertical sync output Signal. If a second pulse is undesirable, then check the
"Vertical Pulse Width vs Rset" graph to make sure the vertical output pulse will extend beyond the end of the input
vertical sync period. In most systems the end of the vertical
sync period may be very accurate. In this case the preferred
design may be to start the vertical sync pulse at the end of
the vertical sync period, similar to starting the vertical sync
pulse after the first serration pulse. A VGA standard is to be
used as an example to show how this is done. In this standard a horizontal line is 32 /Jos long. The vertical sync period
is two horizontal lines long, or 64 /Jos. The vertical default
sync delay time must be longer than the vertical sync period of 64 /Jos. In this case Rset must be larger than 680 kO.
Rset must still be small enough for the output of the integrator to reach V1 before the end of the vertical period of the
input pulse. The first graph can be used to confirm that Raet
is small enough for the integrator. Instead of using the vertical serration pulse separation, use the actual pulse width of
the vertical sync period, or 64 /Jos in this example. This graph
is linear, meaning that a value as large as 2.7 MO can be
used for Rset (twice the value as the maximum at 30 /Jos).
Due to leakage currents it is advisable to keep the value of
Rset under 2.0 MO. In this example a value of 1.0 MO is
selected, well above the minimum of 680 kO. With this value
for Rset the pulse width of the vertical sync output pulse of
the LM 1881 is about 340 /Jos.
ODD/EVEN FIELD PULSE
An unusual feature of LM1881 is an output level from Pin 7
that identifies the video field present at the Input to the
LM1881. This can be useful in frame memory storage applications or in extracting test signals that occur only In alternate fields. For a composite video signal that is interlaced,
one of the two fields that make up each video frame or
picture must have a half horizontal scan line period at the
end of the vertical scan--i.e., at the bottom of the picture.
This is called the "odd field" or "field 1". The "even field"
or "field 2" has a complete horizontal scan line at the end of
the field. An odd field starts on the leading edge of the first
equalizing pulse, whereas the even field starts on the leading edge of the second equalizing pulse of the vertical retrace interval. Figure 2(8) shows the end of the even field
and the start of the odd field.
To detect the oddleven fields the LM1881 again integrates
the composite sync waveform (Figure 3). A capacitor is
charged during the period between sync pulses and discharged when the sync pulse is present. The pariod between normal horizontal sync pulses is enough to allow the
capacitor voltage to reach a threshold level of a comparator
that clears a flipflop which is also being clocked by the sync
waveform. When the vertical interval is reached, the shorter
integration time between equalizing pulses prevents this

3-118

Application Notes (Continued)
threshold from being reached and the Q output of the flipflop is toggled with each equalizing pulse. Since the half line
period at the end of the odd field will have the same effect
as an equalizing pulse period, the Q output will have a different polarity on successive fields. Thus by comparing the Q
polarity with the vertical output pulse, an odd/even field index is generated. Pin 7 remains low during the even field
and high during the odd field.

signal (VIRS) and line 21 is reserved for closed caption data
for the hearing impaired. The remaining lines are used in a
number of ways. Lines 17 and 18 are frequently used during
studio proceSSing to add and delete vertical interval test
signals (VITS) while lines 14 through 18 and line 20 can be
used for Videotex/Teletext data. Several institutions are
proposing to transmit financial data on line 17 and cable
systems use the available lines in the vertical interval to
send decoding data for descrambler terminals.
Since the vertical output pulse from the LM1881 coincides
with the leading edge of the first vertical serration, sixteen
positive or negative transitions later will be the start of line
14 in either field. At this point simple counters can be used
to select the desired line(s) for insertion or deletion of data.

BURST/BACKPORCH OUTPUT PULSE

In a composite video signal, the chroma burst is located on
the backporch of the horizontal blanking period. This period,
approximately 4.8 P.s long, is also the black level reference
for the subsequent video scan line. The LM1881 generates
a pulse at Pin 5 that can bo used either to retrieve the chroma burst from the composite video signal (thus providing a
subcarrier synchronizing signal) or as a clamp for the DC
restoration of the video waveform. This output is obtained
simply by charging an internal capacitor starting on the trailing edge of the horizontal sync pulses. Simultaneously the
output of Pin 5 is pulled low and held until the capacitor
charge circuit times out-4 P.s later. A shorter output burst
gate pulse can be derived by differentiating the burst output
using a series CoR network. This may be necessary in applications which require high horizontal scan rates in combination with normal (60-120 Hz) vertical scan rates.

VIDEO LINE SELECTOR
The circuit in Figure 4 puts out a single video line according
to the binary coded information applied to line select bits
bO-b7. A line is selected by adding two to the desired line
number, converting to a binary equivalent and applying the
result to the line select inputs. The falling edge of the
LM1881's vertical pulse is used to load the appropriate
number into the counters (MM74CI93N) and to set a start
count latch using two NAND gates. Composite sync transitions are counted using the borrow out of the desired number of counters. The final borrow out pulse is used to turn on
the analog switch (CD4066BC) during the desired line. The
falling edge of this Signal also resets the start count latch,
thereby terminating the counting.
The circuit, as shown, will provide a single line output for
each field in an interlaced video system (television) or a
single line output in each frame for a non-interlaced video
system (computer monitor). When a particular line in only
one field of an interlaced video signal is desired, the oddl
even field index output must be used instead of the vertical
output pulse (invert the field index output to select the odd
field). A single counter is needed for selecting lines 3 to 14;
two counters are needed for selecting lines 15 to 253; and
three counters will work for up to 2046 lines. An output buffer is required to drive low impedance loads.

APPLICATIONS

Apart from extracting a composite sync signal free of video
information, the LM1881 outputs allow a number of interesting applications to be developed. As mentioned above, the
burst gate/backporch clamp pulse allows DC restoration of
the original video waveform for display or remodulation on
an R.F. carrier, and retrieval of the color burst for color synchronization and decoding into R.G.B. components. For
frame memory storage applications, the odd/even field level allows identification of the appropriate field ensuring the
correct read or write sequence. The vertical pulse output is
particularly useful since it begins at a precise time-the rising edge of the first vertical serration in the sync waveform.
This means that individual lines within the vertical blanking
period (or anywhere in the active scan line period) can easily be extracted by counting the required number of transitions in the composite sync waveform following the start of
the vertical output pulse.
The vertical blanking interval is proving popular as a means
to transmit data which will not appear on a normal T.V. receiver screen. Data can be inserted beginning with line 10
(the first horizontal scan line on which the color burst appears) through to line 21. Usually lines 10 through 13 are
not used which leaves lines 14 through 21 for inserting signals, which may be different from field to field. In the U.S.,
line 19 is normally reserved for a vertical interval reference

MULTIPLE CONTIGUOUS VIDEO LINE
SELECTOR WITH BLACK LEVEL RESTORATION

The circuit in Figure 5 will select a number of adjoining lines
starting with the line selected as in the previous example.
Additional counters can be added as described previously
for either higher starting line numbers or an increased number of contiguous output lines. The back porch pulse output
of the LM1881 is used to gate the video input's black level
through a low pass filter (10 kO, 10 p.F) providing black level
restoration at the video output when the output selected
line(s) is not being gated through.

3-119

II

.- r------------------------------------------------------------------------------------------,

:&
.-

::!

Typical Applications
+~o-.-----------.-_.------._------------_.------~

680kA

D.lI'F

2kA

~~---------~~~---------~~~~------~

r-l....,....,..........-'.....~

VIDEO
INPUT

SELECl[Jl VIDEO
LINE OUT

TL/H/9150-5

FIGURE 4. Video Line Selector
+5Vo-.----1~----~_1~----~------------~~----_t--------------------,

68Dk4

2k4

____ e.
~--_t~~--------~~------1_------r_--~~

:
I
I
I
I
I

6204

I
I
I
I
I

0.1

O.II'F:

~~---~+--~------~----4--+---~

I:
__

VIDEO

INPUT

-

+5V

I

I
I
I

I

'-t------:§
~____....J

=
:
._----------_.
t

SElECTED VIDEO

LINE(S) OUT

TLlH/9150-6

FIGURE 5. Multiple Contiguous Video Une Selector With Black Level Restoration

3-120

...
c:
...Cf1
......

~National

......

~ Semiconductor

::a

•

r-

...

a:

54ACT17 4ACT715 eLM 1882
54ACT17 4ACT715-ReLM 1882-R
Programmable Video Sync Generator
General Description
The 'ACT715/LM1882 and 'ACT715-R/LM1882-R are
20-pin TTL-input compatible devices capable of generating
Horizontal, Vertical and Composite Sync and Blank signals
for televisions and monitors. All pulse widths are completely
definable by the user. The devices are capable of generating signals for both interlaced and noninterlaced modes of
operation. Equalization and serration pulses can be introduced into the Composite Sync signal when needed.
Four additional Signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the system architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
The 'ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register
0, defaults to a logic "0". This facilitates (re)programming
before operation.
The 'ACT715-R/LM1882-R is the same as the
'ACT715/LM1882 in all respects except that the

E
•

'ACT715-R/LM1882-R is mask programmed to default to a
Clock Enabled state. Bit 10 of the Status Register defaults
to a logic "1". Although completely (re)programmable, the
'ACT715-R/LM1882-R version is better suited for applications using the default 14.31818 MHz RS-HO register values. This feature allows power-up directly into operation,
following a single CLEAR pulse.

!i:
...

II)'

::a

Features
• Maximum Input Clock Frequency> 130 MHz
• Interlaced and non-interlaced formats available
• Separate or composite horizontal and vertical Sync and
Blank signals available
• Complete control of pulse width via register
programming
• All inputs are TTL compatible
• 8 mA drive on all outputs
• Default RS170/NTSC values mask programmed into
registers
• 4 KV minimum ESD immunity
• 'ACT715-R/LM1882-R is mask programmed to default
to a Clock Enable state for easier start-up into
14.31818 MHz RSHO timing

Connection Diagrams

'-./

~

00 -

1

0, -

2

20 t-vcc
19 t- ADOR/DATA

O2-

3

18 t-L/HBYTE

03 04-

4

17 t-LOAO

5

16 I-ODO/EVEN

05- 6

15 rHSYNVDR

06-

7

14 rVCSYNC

~- 8

13 rHBLHOR

CLR- 9

12 rVCBLANK

GNO- 10

11 t-CLOCK

II

Pin Assignment
forlCC

Pin Assignment for
DIPsndSOIC

Os Os

04 ~

OO[IJOOOO[!]
~

CLR~~

'"

1II02

GNO ImI ~

~ [II 0,

>r

'" CD DO

CLOCK [jJ
VCBLANK
HBLHOR

~~
Mi ~
"

~ ~ Vee

It, IiID AOOR/DATA

-"'-"'-"I.~
~~liIDliiJllE

!I'~~
=0

TUF/10137-1

Order Number lM1882CN or lM1882CM
For Default R8-170, Order Number lM1882-RCN or
lM1882-RCM

3-121

TL/F/10137-2

II:

i....

:!i
•
co

Logic Block Diagram

C\oI

~

Do-~ C~r---"

~

~~~---t-r~~---1r-J

•
II:

.n
....
.....

•
Ln
....
.....

ADDR/DATA
LHBYTE
LOAD

'"i::i
~
CLR

~
'"

ODD/E'lEN
VCSYNC

VCBLANK

HBLHDR
CLOCK

HSYNVDR
TLlF/l0137-3

Pin Description
ODD/EVEN: Output that identifies if display is in odd (HIGH)
or even (LOW) field of interlace when device is in interlaced
mode of operation. In noninterlaced mode of operation this
output is always HIGH. Data can be serially scanned out on
this pin during Scan Mode.
VCSYNC: Outputs Vertical or Composite Sync signal based
on value of the Status Register. Equalization and Serration
pulses will (if enabled) be output on the VCSYNC signal in
composite mode only.
VCBLANK: Outputs Vertical or Composite Blanking Signal
based on value of the Status Register.

There are a Total of 13 inputs and 5 outputs on the
'ACT715/LM1882.
Data Inputs DO-D7: The Data Input pins connect to the
Address Register and the Data Input Register.
Al)'i)fi/DATA: The ADDR/DATA signal is latched into the
device on the falling edge of the LOAD signal. The Signal
determines if an address (0) or data (1) is present on the
data bus.
LtHBYTE: The LtHBYTE signal is latched into the device
on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB's (0) or the 4 MSB's
(1) of the Data Registers. A 1 on this pin when an ADDRI
DATA is a 0 enables Auto-Load Mode.

HBLHDR: Outputs Horizontal Blanking Signal, Horizontal
Gating signal or Cursor Position based on value of the
Status Register.

LOAD: The LOAD control pin loads data into the Address or
Data Registers on the rising edge. Ai5DR/DATA and
[/HBYTE data is loaded into the device on the falling edge
of the LOAD. The LOAD pin has been implemented as a
Schmitt trigger input for better noise immunity.

HSYNVDR: Outputs Horizontal Sync Signal, Vertical Gating
signal or Vertical Interrupt signal based on value of Status
Register.

Register Description

CLOCK: System CLOCK input from which all timing is derived. The clock pin has been implemented as a Schmitt
trigger for better noise immunity. The CLOCK and the LOAD
signal are asynchronous and independent. Output state
changes occur on the falling edge, of CLOCK.
CLR: The CLEAR pin is an asynchronous input that initializes the device when it is HIGH. Initialization consists of setting all registers to their mask programmed values, and initializing all counters, comparators and registers. The
CLEAR pin has been implemented as a Schmitt trigger for
better noise immunity. A CLEAR pulse should be asserted
by the user immediately alter power-up to ensure proper
initialization of the registers-even if the user plans to
(re)program the device.

All of the data registers are 12 bits wide. Wid1h's of all puls'es are defined by specifying the start count and end count
of all pulses. Horizontal pulses are specified with-respect-to
the number of clock pulses per line and vertical pulses are
specified with-respect-to the number of lines per frame.
REGO-STATUS REGISTER
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs. The
default value for the Status Register is 0 (000 Hex) for the
'ACT715/LM1882 and is "512" (200 Hex) for the 'ACT715R/LM1882-R.

Note: A CLEAR pulse will disable the CLOCK on the 'ACT715/LM1882 and

will enable the CLOCK on the 'ACT715·R/LM1882·R.

3-122

Register Description

.....
.....
CI'I

(Continued)

Bits 0-2

HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses.
REG1- Horizontal Front Porch
REG2- Horizontal Sync Pulse End Time
REG3- Horizontal Blanking Width

B2 B1 BO VCBLANK VCSYNC HBLHDR HSYNVDR

0 0 0
(DEFAULT)
0 0 1
0 1 0
0 1 1
1
1
1
1

0
0
1
1

0
1
0
1

CBLANK

CSYNC

HGATE

VGATE

VBLANK
CBLANK
VBLANK

CSYNC
VSYNC
VSYNC

HBLANK
HGATE
HBLANK

VGATE
HSYNC
HSYNC

CBLANK
VBLANK
CBLANK
VBLANK

CSYNC
CSYNC
VSYNC
VSYNC

CURSOR
HBLANK
CURSOR
HBLANK

VI NT
VI NT
HSYNC
HSYNC

REG4- Horizontal Interval Width

VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
REG5- Vertical Front Porch

Blt83-4
B4

0
0
(DEFAULn
0
1
1
0
1
1

;b

•

~
.....

!•

r-

ill:

.....
OCI

OCI

~

:::a

REG6- Vertical Sync Pulse End Time
REG7- Vertical Blanking Width
REG8- Vertical Interval Width
# of Lines per Frame

Mode of Operation

B3

# of Clocks per Line

•
.....
.....

Interlaced Double Serration and
Equalization
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration
and Equalization

EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and serration pulses and the vertical interval over which they occur.
REG 9- Equalization Pulse Width End Time
REG10- Serration Pulse Width End Time
REGll- Equalization/Serration Pulse Vertical
Interval Start Time

Double Equalization and Serration mode will output equalization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse. In
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.

REG12- Equalization/Serration Pulse Vertical
Interval End Time

VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Interrupt Signal if used.
REGl3- Vertical Interrupt Activate Time
REGl4- Vertical Interrupt Deactivate Time

Bits 5-8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse active
LOW. A value of 1 indicates an active HIGH pulse.

CURSOR LOCATION REGISTERS

B5- VCBLANK Polarity
B6- VCSYNC Polarity
B7- HBLHDR Polarity

These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating signals.
REGl5- Horizontal Cursor Position Start Time

B6- HSYNVDR Polarity

REGl6- Horizontal Cursor Position End Time
REG17- Vertical Cursor Position Start Time
REG18- Vertical Cursor Position End Time

Bits 9-11
Bits 9 through 11 enable several different features of the
device.
B9- Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)

Signal Specification

Blo- Disable System Clock (0)
Enable System Clock (1)

HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
All horizontal Signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the, horizontal line is considered
pulse 1 not o. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank signal
(see Figure 1). Since the first CLOCK edge, CLOCK # 1,
causes the first falling edge of the Horizontal Blank reference pulse, edges referenced to this first Horizontal edge
are n + 1 CLOCKs away, where "n" is the width of the
timing in question. Registers 1, 2, and 3 are programmed in
this manner. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2. This

Default values for Bl0 are "0" in the 'ACT715/
LM1882 and "1" in the 'ACT715-R/LM1882-R.
Bll- Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for internal
testing only.

3-123

&I

a::
"

N

~

....

Signal Specification (Continued)

~

•

N
CD
CD

SYSCK

....
:i
....

HilA><
REG4

•
a::

an
....
,...
....,...•

It)

REG10

HIIAX/2
Tl/F/10137-4

FIGURE 1. Horizontal Waveform Specification
limitation is imposed because during interlace operation this
value is internally divided by 2 in order to generate serration
and equalization pulses at 2 x the horizontal frequency.
Horizontal signals will change on the falling edge of the
CLOCK signal. Signal specifications are shown below.
Horizontal Period (HPER) = REG(4) x ckper

Vertical
Vertical
Vertical
Vertical

Vertical Front Porch = [REG(5) where n = 1 for noninterlaced
n = 2 for interlaced

Horizontal Blanking Width = [REG(3) - 11 x ckper
Horizontal Sync Width
= [REG(2) - REG(l)] x ckper
Horizontal Front Porch

= [REG(l) -

Frame Period (VPER) = REG(8) X hper
Field Period (VPER/n) = REG(8) X hper/n
Blanking Width = [REG(7) - 11 X hper/n
Syncing Width = [REG(6) - REG(5)1 X hper/n

11

X hper/n

COMPOSITE SYNC AND BLANK SPECIFICATION

11 X ckper

Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the corresponding vertical and horizontal components of these signals. The CompOSite Sync signal may also include serration
and/or equalization pulses. The Serration pulse interval occurs in place of the Vertical Sync interval. Equalization pulses occur preceding and/or following the Serration pulses.
The width and location of these pulses can be programmed
through the registers shown below. (See Figure 28.)

VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines
per frame. This is true in both interlaced and noninterlaced
modes of operation. Care must be taken to not specify the
Vertical Registers in terms of lines per field. Since the first
CLOCK edge, CLOCK # 1, causes the first falling edge of
the Vertical Blank (first Horizontal Blank) reference pulse,
edges referenced to this first edge are n + 1 lines away,
where "n" is the width of the timing in question; Registers 5,
6, and 7 are programmed in this manner. Also, in the interlaced mode, vertical timing is based on half-lines. Therefore
registers 5, 6, and 7 must contain a value twice the total
horizontal (odd and even) plus 1 (as described above). In
non-interlaced mode, all vertical timing is based on wholelines. Register 8 is always based on whole-lines and does
not add 1 for the first clock. The vertical counter starts at
the value of 1 and counts until the value of VMAX. No restrictions exist on the values placed in the vertical registers.
Vertical Blank will change on the leading edge of HBLANK.
Vertical Sync will change on the leading edge of HSYNC.
,
(See Figure 2A.)

Horizontal Equalization PW = [REG(9) - REG(l)1 X ckper
REG 9 = (HFP) + (HEap)
+1
Horizontal Serration PW
= [REG(4)/n + REG(l) REG(10)] X ckper
REG 10 = (HFP) + (HPER/
2) - (HSERR) + 1
Where n = 1 for noninterlaced single serration/equalization
n = 2 for noninterlaced double
serration/ equalization
n = 2 for interlaced operation

3-124

Signal Specification

(Continued)
HBLANK

TL/F/l0137-5

FIGURE 2A. Vertical Waveform Specification

HBLANK
CSYNC

I:
'I
VSYNC~~~~==J==
REGS

REG.

I

I

I

REGI2

REGl1~,+~-------+------..:=----+--------1,
EQUALIZATION /SERRATION INTERVAL

TL/F110137-12

FIGURE 2B. Equalization/Serration Interval Programming
HORIZONTAL AND VERTICAL GATING SIGNALS
Horizontal Drive and Vertical Drive outputs can be utilized
as general purpose Gating Signals. Horizontal and Vertical
Gating Signals are available for use when Composite Sync
and Blank signals are selected and the value of Bit 2 of the
Status Register is O. The Vertical Gating signal will change
in the same manner as that specified for the Vertical Blank.
Horizontal Gating Signal Width = [REG(16) _ REG(15)] x
ckper
[
Vertical Gating Signal Width
= REG(18) - REG(17)] x
hper

and Bit 2 of the Status Register is set to the value of 1. The
Cursor Position generates a single pulse of n clocks wide
during every line that the cursor is specified. The signals are
generated by logically ORing (ANDing) the active LOW
(HIGH) Signals specified by the registers used for generating Horizontal and Vertical Gating signals. The Vertical Interrupt signal generates a pulse during the vertical interval
specified. The Vertical Interrupt signal will change in the
same manner as that specified for the Vertical Blanking signal.
Horizontal Cursor Width = [REG(16) - REG(15)] X ckper

CURSOR POSITION AND VERTICAL INTERRUPT

Vertical Cursor Width = [REG(18) - REG(17)] X hper
Vertical Interrupt Width = [REG(14) - REG(13)] X hper

The Cursor Position and Vertical Interrupt signal are available when CompoSite Sync and Blank Signals are selected

3-125

&I

a:
~

I,..

:!
•

i,..

:!
•
~
,..

.....
•
,..
1.1)

.....

Addressing Logic
The register addressing logic is composed of two blocks of
logic. The first is the address register and counter
(ADDRCNTR), and the second is the address decode
(ADDRDEC).

time the High Byte is written the address counter Is incremented by 1. The counter has been implemented to loop on
the initial value loaded into the address register. For example: If a value of 0 was written Into the address register then
the counter would count from 0 to 18 before resetting back
to O. If a value of 15 was written Into the address register
then the counter would count from 15 to 18 before looping
back to 15. If a value greater than or equal to 18 Is placed
Into the address register the counter will continuously loop
on this value. Auto addressing Is Initiated on the failing edge
of LOAD when ADDRDATA is 0 and LHBYTE is 1. Incrementing and loading of data registers will not commence
until the failing edge of LOAD after ADDRDATA goes to 1.
The next rising edge of LOAD will load the first byte of data.
Auto Incrementing Is disabled on the falling edge of LOAD
after ADDRDATA and LHBYTE goes low.

ADDRCNTR LOGIC
Addresses for the data registers can be generated by one of
two methods. Manual addressing requires that each byte of
each register that needs to be loaded needs to be addressed. To load both bytes of all 19 registers would require
a total of 57 load cycles (19 address and 38 data cycles) •
Auto Addressing requires that only the initial register value
be specified. The Auto Load sequence would require only
39 load cycles to completely program all registers (1 address and 38 data cycles). In the auto load sequence the
low order byte of the data register will be written first followed by the high order byte on the next load cycle. At the

Manual Addre88lng Mode
Cycle #

Load FaIling Edge

1

Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load

2
3
4
5
6
Addr
REG (m)

D7-DO

Lbyt.

(m)

Hbyto

Load RIling Edge
Load Address m
Load Lbytem
Load Hbytem
Load Address n
Load Lbyten
Load Hbyten
Lbyte

Addr
REG (n)

(m)

J J J J

(n)

I

L/HBYTE

I

\
\

I

\

(n)

*

LOAD

ADDR/DATA "

Hbyt.

\

I

r

\
TUF/l0137-7

Auto Addre88lng Mode
Cycle #

Load Failing Edge

Load Rlalng Edge

1
2
3
4
5
6

Enable Auto Addreaslng
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing

Load Start Address n
Load Lbyte (n)
Load Hbyte (n); Inc Counter
Load Lbyte (n + 1)
Load Hbyte (n+ 1); Inc Counter
Load Address

Addr
REG (n)

D7-DO

Lbyto

(n)

Hbyto

Lbyto

(n)

(n+1)

J J J J

Hbyto

(n+1)

*

LOAD

•
ADDR/DATA

\

[/HBYTE

I

I

Addr
REG (m)

\
\
TL/F/l0137-8

3-126

Addressing Logic (Continued)
ADDRDEC LOGIC

...IX

ADDR _ _ _ _

The ADDRDEC logic decodes the current address and generates the enable signal for the appropriate register. The
enable values for the registers and counters change on the
falling edge of LOAD. Two types of ADDRDEC logic is enabled by 2 pair of addresses, Addresses 22 or 54 (Vectored
Restart logic) and Addresses 23 or 55 (Vectored Clear logic). Loading these addresses will enable the appropriate logic and put the part into either a Restart (all counter registers
are reinitialized with preprogrammed data) or Clear (all registers are cleared to zero) state. Reloading the same
AD DR DEC address will not cause any change in the state of
the part. The outputs during these states are frozen and the
internal CLOCK is disabled. Clocking the part during a Vectored Restart or Vectored Clear state will have no effect on
the part. To resume operation in the new state, or disable
the Vectored Restart or Vectored Clear state, another nonADDRDEC address must be loaded. Operation will begin in
the new state on the rising edge of the non-ADDRDEC load
pulse. It is recommended that an unused address be loaded
following an ADDRDEC operation to prevent data registers
from accidentally being corrupted. The following Addresses
are used by the device.

• OUTPUT/COUNT FREEZES
• PART IS IN RESTART/CLEAR
• ORIGINAL PROGRAMMED COUNT
DATA IS RELOADED INTO COUNT
REGISTERS (VECTOR RESTART)
• ALL REGISTERS CLEARED TO
ZERO (VECTOR CLEAR)

r

COUNT RESUMES ATl
PIXEL ONE
(RESTART ONLY)

TL/F/l0137-9

FIGURE 3. ADDRDEC Timing
GENLOCKING

The 'ACT715/LM1882 and 'ACT715-R/LM1882-R is designed for master SYNC and BLANK signal generation.
However, the devices can be synchronized (slaved) to an
external timing Signal in a limited sense. Using Vectored
Restart, the user can reset the counting sequence to a given location, the beginning, at a given time, the rising edge of
the LOAD that removes Vector Restart. At this time the next
CLOCK pulse will be CLOCK 1 and the count will restart at
the beginning of the first odd line.
Preconditioning the part during normal operation, before the
desired synchronizing pulse, is necesasry. However, since
LOAD and CLOCK are asynchronous and independent, this
is possible without interruption or data and performance corruption. If the defaulted 14.31818 MHz RS-170 values are
being used, preconditioning and restarting can be minimized
by using the CLEAR pulse instead of the Vectored Restart
operation. The 'ACT715-R/LM1882-R is better suited for
this application because it eliminates the need to program a
1 into Bit 10 of the Status Register to enable the CLOCK.
Gen Locking to another count location other than the very
beginning or separate horizontal/vertical resetting is not
possible with the 'ACT715/LM1882 nor the 'ACT715-RI
LM1882-R.

Address 22/54 Restart Vector (Restarts Device)
Address 23/55 Clear Vector (Zeros All Registers)
24-31
32-50
51-53
56-63

~

LOAO

Address 0
Status Register REGO
Address 1-18 Data Registers REG1-REG18
Address 19-21 Unused

Address
Address
Address
Address

ADDRDEC Address

.. DUMMY a.ddress cannot be ADDRDEC Address

Unused
Register Scan Addresses
Counter Scan Addresses
Unused

At any given time only one register at most is selected. It is
possible to have no registers selected.
VECTORED RESTART ADDRESS
The function of addresses 22 (16H) or 54 (36H) are similar
to that of the CLR pin except that the preprogramming of
the registers is not affected. It is recommended but not required that this address is read after the initial device configuration load sequence. A 1 on the ADDRDATA pin (Auto
Addressing Mode) will not cause this address to automatically increment. The address will loop back onto itself regardless of the state of ADDRDATA unless the address on
the Data inputs has been changed with ADDRDATA at o.

SCAN MODE LOGIC

A scan mode is available in the ACT715/LM1882 that allows the user to non-destructively verify the contents of the
registers. Scan mode is invoked through reading a scan address into the address register. The scan address of a given
register is defined by the Data register address + 32. The
internal Clocking Signal is disabled when a scan address is
read. Disabling the clock freezes the device in it's present
state. Data can then be serially scanned out of the data
registers through the ODD/EVEN Pin. The LSB will be
scanned out first. Since each register is 12 bits wide, completely scanning out data of the addressed register will require 12 CLOCK pulses. More than 12 CLOCK pulses on the
same register will only cause the MSB to repeat on the output. Re-scanning the same register will require that register
to be reloaded. The value of the two horizontal counters and
1 vertical counter can also be scanned out by using address
numbers 51-53. Note that before the part will scan out the
data, the LOAD signal must be brought back HIGH.

VECTORED CLEAR ADDRESS

Addresses 23 (17H) or 55 (37H) is used to clear all registers
to zero simultaneously. This function may be desirable to
use prior to loading new data into the Data or Status Registers. This address is read into the device in a similar fashion
as all of the other registers. A 1 on the ADDRDATA pin
(Auto Addressing Mode) will not cause this address to automatically increment. The address wiil loop back onto itself
regardless of the state of ADDRDATA unless the address
on the Data inputs has been changed with ADDRDATA at o.

3-127

~

.1
.~

•

i.~

•

~
....

,...
•
....
,...
1.1)

Addressing Logic (Continued)
Normal device operation can be resumed by loading In a
non-scan address. As the scanning of the registers Is a nondestructive scan, the device will resume correct operation
from the pOint at which it was halted.

Reg

RS170 Default Register Values
The tebles below show the values programmed for the
RS170 Format (using a 14.31818 MHz clock signal) and
how they compare against the actual EIA RS170 Specifications. The default Signals that will be output are CSYNC,
CBLANK, HDRIVE and VDRIVE. The device initially starts at
the beginning of the odd field of interlace. All signals have
active low pulses and tlie clock is disabled at power up.
Registers 13 and 14 are not involved in the actual signal
information. If the Vertical Interrupt was selected so that a
pulse indicating the active lines would be output.

o Value H

Register Description

REGO
REGO

0
512

000
200

Stetus Register (715/LM1882)
Stetus Register (715-R/LM1882-R)

REGl
REG2
REG3
REG4

23
91
157
910

017
05B
09D
38E

HFPEndTime
HSYNC Pulse End TIme
HBLANK Pulse End Time
Totel Horizontel Clocks

REG5
REG6
REG7
REG8

7
13
41
525

007
OOD
029
20D

VFPEndTime
VSYNC Pulse End Time
VBLANK Pulse End Time
Totel Vertical Lines

REG9
REG10
REGll
REG12

57
410
1
19

038
19A
001
013

Equalization Pulse End Time
Serration Pulse Sterl Time
Pulse Interval Start Time
Pulse Interval End Time

REG13
REG14

41
526

029
20E

Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time

REG15
REG16
REG17
REG18

911
92
1
21

38F
05C
001
015

Horizontel Drive Stert Time
Horizontel Drive End Time
Vertical Drive Stert Time
Vertical Drive End Time
Rate
14.31818 MHz
15.73426 kHz
59.94 Hz
29.97 Hz

Input Clock
Line Rate
Field Rate
Frame Rate

Period
69.841 ns
63.556 p.s
16.683 ms
33.367ms

RS170 Horizontal Data
Signal

Width

HFP
HSYNCWidth
HBLANK Width
HDRIVE Width
HEQPWidth
HSERRWidth
HPER iod

22 Clocks
68 Clocks
156 Clocks
91 Clocks
34 Clocks
68 Clocks
910 Clocks

VFP
VSYNCWidth
VBLANK Width
VDRIVE Width
VEQP Intrvl
VPERiod (field)
VPERiod (frame)

3 Lines
3 Lines
20 Lines
11.0 Lines
9 Lines
262.5 Lines
525 Lines

p.s
1.536
4.749
10.895
6.356
2.375
4.749
63.556

%H
7.47
17.15
10.00
3.74
7.47
100

Specification (p.s)
1.5
4.7
10.9
O.lH
2.3
4.7

±0.1
±0.1
±0.2
±0.005H
±0.1
±0.1

RS170 Vertical Date
190.67
190.67
1271.12
699.12
16.683 ms
33.367 ms

7.62
4.20
3.63

6 EQP Pulses
6 Serration Pulses
0.075V ± 0.005V
0.04V ± 0.006V
9 Lines/Field
16.683 ms/Field
33.367 me/Frame

...
...Cf!......•
......

Absolute Maximum Ratings (Note 1)

UI

If Military/Aerospace specified devlcea are required,
please contact the National Semiconductor Sales
Ottlce/Dlstrlbutors for availability and specification ••
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Diode Current (Ilid
-20mA
VI = -0.5V
VI = Vee +0.5V
+20mA
DC Input Voltage (VI)
-0_5VtoVee +0.5V
DC Output Diode Current (10K)
Vo = -0.5V
-20mA
+20mA
Vo = Vee +0.5V
DC Output Voltage (Vo)
-0.5V to Vee +0.5V
DC Output Source
or Sink Current (10)
±15mA
DC Vee or Ground Current
±20mA
per Output Pin (lee or IGND)
Storage Temperature (TSTG)
-65°C to + 1500C

Junction Temperature (TJ)
Ceramic
175°C
Plastic
1400C
Nota 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply.

temperature and output/input loading variables. National does not racommend operation of FACTTM circuits outside databook _pecDications.

Recommended Operating
Conditions
Supply Voltage (Vecl
Input Voltage (VI)
Output Voltage (Vo)
Operating Temperature (TA)
74ACT
54ACT
Minimum Input Edge Rate (II.V/ II.t)
VIN from O.SV to 2.0V
Vee @ 4.5V, 5.5V

4.5Vto 5.5V
OV to Vee
OV to Vee

::a

•

roo

...
a:

CD
CD
N

•
!i:...

;::a

-400C to + S5°C
- 55°C to + 125°C

125 mVins

DC Characteristics For 'ACT Family Devices over Operating Temperature Range (unless otherwise specified)

Symbol

Parameter

Vee
(V)

ACT/LM1882

54ACT/LM1882

74ACT/LM1882

TA = +25"C
CL = 50pF

TA = -55"C
to + 125"C
CL = 50pF

TA = -400C
to +85"C

Typ
VOH

Minimum High Level
Output Voltage

4.5
5.5

4.49
5.49

4.5
5.5
VOL

Maximum Low Level
Output Voltage

4.5
5.5

0.001
0.001

4.5
5.5

Units

Condition.

Guaranteed Llmita

= - 50 /LA

4.4
5.4

4.4
5.4

4.4
5.4

V
V

lOUT

3.S6
4.S6

3.7
4.7

3.76
4.76

V
V

'VIN = VILIVIH
10H = -SmA

0.1
0.1

0.1
0.1

0.1
0.1

V
V

lOUT

0.36
0.36

0.5
0.5

0.44
0.44

V
V

'VIN = VILIVIH
10H = +SmA

= 50 !LA

10LD

Minimum Dynamic
Output Current

5.5

32.0

32.0

mA

VOLD

= 1.65V

10HD

Minimum Dynamic
Output Current

5.5

-32.0

-32.0

mA

VOHD

= 3.S5V

liN

Maximum Input
Leakage Current

5.5

±0.1

±1.0

±1.0

/LA

lee

Supply Current
Quiescent

5.5

S.O

160

SO

/LA

VIN

= Vee, GND

leer

Maximum Icc/Input

5.5

1.6

1.5

mA

VIN

= Vee - 2.1V

0.6

•All outputs loaded; thrasholds on input aSSOCiated with input under test.
Note 1: Test Load 50 pF, soon to Ground.

3-129

VI

= Vee,GND

II

a:

a
....

AC Electrical Characteristics

"

:Ii!

S4AcTILM1882

74ACT/LM1882

TA = +25"C
CL = SOpF

TA = -S5"C
to + 12S"C
CL = SOpF

TA = -40"C
to +8S"C
CL = SOpF

-I

•

('II

=

Symbol

Parameter

Vee
(V)

i-I

Min

Typ

5.0

170

190

130

150

MHz

5.0

190

220

145

175

MHz

5.0

4.0

13.0

15.5

3.5

19.5

3.5

18.5

ns

Clock to ODDEVEN
(Scan Mode)

5.0

4.5

15.0

17.0

3.5

22.0

3.5

20.5

ns

Load to Outputs

5.0

4.0

11.5

16.0

3.0

20.0

3.0

19.5

ns

fMAXI

Interlaced fMAX
(HMAX/2 is ODD)

.....

fMAX

Non-Interlaced fMAX
(HMAX/2 is EVEN)

tpLH1
tpHL1

Clock to Any Output

tpLH2
tpHL2
tpLH3

•
an
....
.....

Min

Units

Min

•

~
....

"

ACT/LM1882

Max

Max

Max

AC Operating Requirements
ACT/LM1882
Symbol

Parameter

Vee

TA ~ +2S"C

(V)

Typ
tsc
tsc

Control Setup Time
AODR/OATA to LOAOLlHBYTE to LOAO-

tsd

Data Setup Time
D7 -DO to LOAD +
Control Hold Time
LOAD- to AOOR/OATA
LOAD- to LlHBYTE

the

54ACT/LM1882
TA

= -S5"C

to + 125"C

74ACT/LM1882
TA = -40"C
to +85"C

Units

Guaranteed Minimums

5.0

3.0
3.0

4.0
4.0

4.5
4.5

4.5
4.5

ns
ns

5.0

2.0

4.0

4.5

4.5

ns

5.0

0
0

1.0
1.0

1.0
1.0

1.0
1.0

ns
ns·

thd

Data Hold Time
LOAD+ to 07-00

5.0

1.0

2.0

2.0

2.0

ns

tree

LOAD + to CLK (Note 1)

5.0

5.5

7.0

8.0

8.0

ns

IwldIwld+

Load Pulse Width
LOW
HIGH

5.0
5.0

3.0
3.0

5.5
5.0

5.5
7.5

5.5
7.5

ns
ns

Iwelr

CLR Pulse Width HIGH

5.0

5.5

6.5

9.5

9.5

ns

iwck

CLOCK Pulse Width
(HIGH or LOW)

5.0

2.5

3.0

4.0

3.5

ns

Note

1: Removal of Vectored Reset or Restart to Clock.

Capacitance
Symbol

Parameter

Typ

Units

Conditions

CIN

Input Capacitance

7.0

pF

Vee

CPO

Power Dissipation
Capacitance

17.0

pF

Vee

3-130

= 5.0V
= 5.0V

...en

r-----------------------------------------------------------------------------,~

AC Operating Requirements (Continued)

...•
~

~

LOAD

•

...fir:

CLOCK

Ii•
Ii:...

OUTPUTS

-,x

Iwld

1"
LHBYTE
ADDRDATA

It.dJ

Iwld

LOAD

.. I

:J.

!

X
'oct

It.,

.1

x

:Jx

-1I
TL/F/l0137-6

FIGURE 4. AC Specifications

Additional Applications Information
PREPROGRAMMING "ON-THE-FLY"

POWERING UP
The'ACT715/LM1882 default value for Bit 10 of the Status
Register is o. This means that when the CLEAR pulse is
applied and the registers are initialized by loading the default values the CLOCK is disabled. Before operation can
begin, Bit 10 must be changed to a 1 to enable CLOCK. If
the default values are needed (no other programming is required) then Figure 5 illustrates a hardwired solution to facilitate the enabling of the CLOCK after power-up. Should control signals be difficult to obtain, Figure 6 illustrates a possible solution to automatically enable the CLOCK upon power-up. Use of the 'ACT715-R/LM1882-R eliminates the
need for most of this circuitry. Modifications of the Figure 6
circuit can be made to obtain the lone CLEAR pulse still
needed upon power-up.

Although the 'ACT715/LM1882 and 'ACT715-R/LM1882-R
are completely programmable, certain limitations must be
set as to when and how the parts can be reprogrammed.
Care must be taken when reprogramming any End Time
registers to a new value that is lower than the current value.
Should the reprogramming occur when the counters are at a
count after the new value but before the old value, then the
counters will continue to count up to 4096 before rolling
over.
For this reason one of the follOWing two precautions are
recommended when reprogramming "on-tha-fly". The first
recommendation is to reprogram horizontal values during
the horizontal blank interval only and/or vertical values during the vertical blank interval only. Since this would require
delicate timing requirements the second recommendation
may be more appropriate.
The second recommendation is to program a Vectored Restart as the final step of reprogramming. This will ensure
that all registers are set to the newly programmed values
and that all counters restart at the first CLK position. This
will avoid overrunning the counter end times and will maintain the video integrity.

Note that, although during a Vectored Restart none of the
preprogrammed registers are affected, some Signals are affected for the duration of one frame only. These signals are
the Horizontal and Vertical Drive signals. After a Vectored
Restart the beginning of these Signals will occur at the first
CLK. The end of the signals will occur as programmed. At
the completion of the first frame, the signals will resume to
their programmed start and end time.

ADDR/DATA
CLEAR

I/H

BYTE

LOAD INPUT
OODEYEN

LOAD

VDRIYE
CSYMC
HDRIVE
CBLANK
CLOCK

TL/F/l0137-10

FIOURE 5. Default RS170 Harclwlre Conflguratlon
3-131

a::

cc.

I....

Additional Applications Information

::E

(Continued)

Vee

.....

•

i....
::E

.....

Rl

GND

•
a::

.b
....

.....

...,
....•
.....

M
M
7
4
H

C
Rl

wv-........

Vee .....

4
2
3
A

16
15
14

C2

Rl

13

CLEAR PIN

12

~OAD PIN

NOT NECESSARY
fOR 'ACT7~5-R/
L1I1882-R

11
10

I

C1
TUF/l0137-11

Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND
Components
Rl: 4.7k
Cl: 10 I'F
R2: 10k
C2: 50 pF

FIGURE 6. Circuit for Clear and Load Pulse Generation

3-132

~National

~ Semiconductor

LM2416/LM2416C Triple 50 MHz CRT Driver
General Description

Features

The LM2416 contains three wide bandwidth. large signal
amplifiers designed for large voltage swings. The amplifiers
have a gain of 13. The device is intended for use in color
CRT monitors and is a low cost solution to designs conforming to VGA. Super VGA and the IBMIID 8514 graphics standard.
The part is housed in the industry standard 11-lead TO-220
molded power package. The heat sink is floating and may
be grounded for ease of manufacturing and RFI shielding.

• 50 Vpp output at 45 MHz drives CRT directly
• Rise/falltime typically 10 ns with 8 pF load
• 65V output swing capability

Applications
• CRT driver for RGB monitors
• High voltage amplifiers

Schematic and Connection Diagram

(One Section)
11

11

V+

10
Rl

9

8
7
VSIAS

6

5
4
3
2

V+
VOUT3
BIAS 3
VIN3

BIAS 2
VIN2

GND
VOUT2
VOUT I

BIAS 1
VIN1

5

PIN 1 DESIGNATOR

GND

TUKI10738-2

Top View
TL/K/l0738-1

3-133

Order Number LM2416T or LM2416CT
See NS Package Number TA 11B

&I

Absolute Maximum Ratings
Supply Voltage, V+
+85V
Power Dissipation, Po
10W
Storage Temperature Range, TSTG
- 25·C to + 100·C
Operating Temperature Range, TCASE
- 20"C to + 90·C
Lead Temperature (Soldering, < 10 sec.)
300·C
ESD Tolerance
4kV

Electrical Characteristics

v+ = 80V, CL = 8 pF, DC input bias, VIN
otherwise noted.
Symbol

Parameter

If Military/Aerospace specified devices are required,
please contsct the National Semiconductor Sales
Office/Distributors for availability and specifications.

= 3.6 Voc. 50 Vpp output swing, VBIAS =
LM2418

Conditions

Icc

Supply Current
(per Amplifier)

No Input or
Output Load

+12V. See FigUfB1. TA

= 25·C unless

LM2418C

Units

Min

Typical

Max

Min

Typ

Max

18

22

26

16

22

28

mA

38

35

42

48

Voc

= 3.6V

VOUT

Output Offset Voltage

VIN

42

46

tr

Rise Time

10% to 90%
(Note 3)

8

13

12

16

ns

tf

Fall Time

10%t090%
(Note 3)

10

13

12

16

ns

BW

Bandwidth

-3dB

Av

Voltage Gain

OS

Overshoot

Figure 1

0

0

%

LE

Linearity Error

(Note 1)

8

10

%

0.5
Input signal.

dB

42
-11

Gain Matching
(Note 2)
I::..Av
Note 1: Lln. .~ty Error Is defined as the vaMUon In smail signal gain Irom
Note 2: CsIcula1ad value lrom Voltage Gain test on each channel.
Note 3: Guaranteed parameter. not tasted.

0.47/1or

t1j~

1.6.8l1'"
_

I MHz,

-13

MHz
-16

VIV

Typical Performance
Characteristics

.±

3,4.10
CL

360

-10

0.2
output with a 100 mV AC,

+8OV

2.7.9~

35
-15

+20V to +70V

Test Circuit
y2YBlU
200

-13

4950
8pr'

YOUT
10 5011 Scope

LM2418 Frequency Response

0'1~

0

~

i

3.6Y
TUK/I0738-3

-3

• 8 pF is total

load capacitance. It includes all psrasRic cspscltancs.
FIGURE 1. Test Circuit (One Section)
FigufB 1 shows a typical test circuit for evaluation of the
LM2416. This circuit is deSigned to allow testing of the
LM2416 in a 50.0 environment such as a pulse generator,
oscilloscope or network analyzer.

1

10

100

FREQUENCY (MHz)
TUK/I0738-4

LM2418 Pulse Response
80

~

i

70

80
50

«l

1\

50

20

0

20

«l

80

TIlE (oSoc)
TUK/I0738-5

3-134

LM2416-Theory of Operation

Thermal Considerations

The LM2416 is a high voltage triple CRT driver suitable for
VGA, Super VGA, IBM 8514 and 1K by 768 non-interlaced
display applications. The LM2416 features 80 volt operation
and low power dissipation. The part is housed in the industry
standard 11 lead TO-220 molded power package. The heat
sink is floating and may be grounded for ease of manufacturing and RFI shielding.
The circuit diagram of the LM2416 is shown in Figure 2. 01
and R2 provides a conversion of input voltage to current,
while 02 acts as a common base or cascode amplifier stage
to drive the load resistor R1. Emitter followers 03 and 04
isolate the impedance of R1 from the capacitance of the
CRT cathode, and make the circuit relatively insensitive to
load capacitance. The gain of this circuit is -R1/R2 and is
fixed at -13. The bandwidth of the circuit is set by the
collector time constant formed by the load resistor R 1 and
associated capacitance of 02, 03, 04, and stray layout capacitance. Proprietary transistor design allows for high
bandwidth with low operating power.

The transfer characteristics of the amplifier are shown in
F1[Jure 3. Power supply current increases as the input Signal
increases and consequently power dissipation also increases.
The LM2416 cannot be used without heat sinking. Figure 3
shows the power dissipated in each channel over the operating voltage range of the device. Typical "average" power
dissipation with the device output voltage at one half the
supply voltage is 1.8W per channel for a total dissipation of
5.4W package dissipation. Under white screen conditions,
i.e.: 15V output, dissipation increases to 3W per channel or
9W total. The LM2416 case temperature must be maintained below 90"C. If the maximum expected ambient temperature is 50"C, then a heat sink is needed with thermal
resistance equal to or less than:
Rth

= (90 ;~O"C) = 4.4"C/W

The Thermalloy #6400 is
meets this requirement.

one

example of a heatsink that

WARNING: THE LM2416IS NOT PROTECTED AGAINST
OUTPUT SHORT CIRCUITS. The minimum resistance the
LM2416 can drive is 600n to ground or V+ .
LM2416

90

~
~

VCC1

OUTPUT

h

70
60

~

50
<10
30

~

5

-

"- ~

VOLTAGE

~

~

INPUT

80

20
10

POWER

...... / '

~

-

~

....
......

z

~
~

a,
2.0

L .....

./

~

.!..
3.0

1.0

ffi
~

a..

I'

o

234567
INPUT VOLTAGE
TL/K110738-7

FIGURE 3. LM2416 DC Characteristics

TL/K/l0738-6

FIGURE 2. LM2416 CRT Driver
(One Section)

3-135

•

ii(L,..1-....,'-"t""T...,..~~_2V-2B.,
ii~2
~i: ......- -~~
---I4

:±; 100 J.lF

*" RED~
.1'. 1

100A
26H-----,

3

500

0 1 F

75A

rl~ 5

10k

~i:

75

-y .

75A

23

10k

V

7

~~

OJ.lF

8

<
o--'-II~-HI-+---------I·9
VIDEO
IN

5.1k

r

24

o--.-II~~~----I6

VI~EO

200· .

25H---~--+---~

o--.-II~

VIDEO
IN

*

51A
27 H--IoIIfy---'WI"""

75A

10k

100A ~>"

LM1203

75

2IH+----,

LM2416

500
20~~--._--r-----~_,

~II
5

I

IL-

r-!r:-

-y0.1J.1F

10

19

5.1k

18

200
17H+-----,
16H+--. .--~--~--~---o
200
CONTRAST
CONTROL

min ==

~7 ~
5k

9

75

10

0.1 J.lF
10k

10k

:~

--.J.L
BLACK LEVEL
GATE IN

~7

-rV

BLACK LEVEL
(BRIGHTNESS)
CONTROL
0.1 J.lF

11

5.1k

~

1000pF

..c-H--;t~
10~V"

.....

-



70
60
50

Y+ = gOY

,,

30

0

20

V
o

"

234

~~

z;;:l

/

Oz
3.0 ;:z

......

"""

... :z;

2.0
1.0

70

/!

/ Porn

60

/

ai5
z'-'

iii U

~

10

.

,....

II' 'POWER

40

.......
::>

VOLTAGE'

Thermal Considerations

~~

::>~

~g

"'~!;...

::II ....
::>::>

~~

50

i--'"
VOLTAGE V

",0

l-

~

/

/

40

o

./

2.0

z '3
...
2Z
~~
1.5 ...
:z;
-u

.....

!aeJ

1.0

ell!!

~~

0.5

&I

55 60 65 70 75 80 85 90 95

6

INPUT YOLTAGE (v)

Y' (Y)
TLlK/1 1 125-7

TLlK/11125-9

FIGURE 4. LM2418 DC Characterfstlcs

FIGURE 5. LM2418 Output Swing
and Power Characteristics

3-139

~
..-

~

~

r-----------------------------------------------------------------------------~

Typical Application
A typical application of the LM2418 is shown in Figure 6.

better than 50 Vpp drive Signals available to a 10 pF load. In
this application, feedback is local to the LM1203, an alternative scheme would feed back from the output of the LM2418
to the positive clamp inputs of the LM1203. This would provide better black level control of the system.

Used in conjunction with an LM1203, a complete video
channel from monitor input to CRT cathode is shown. Performance is satisfactory for all applications up to 640 by 480
lines. Typical riselfall times of this circuit are 15 ns, with

,..

0.1 JoIF

~l
ii~
:...

~~

10 JoIF

Ii 0
II

iDEo

V

7511

IN

10k

U

G

ii~

0

Ii 0

"*

10011
3

26

4

25

~
5

24

10k

Ir-

10JolF~

2

~7

23

LM2418T

........

RED
CUTOFF

i
.n
-¢.

'Jo1F

75

3

GREEN DRIVE

22

~JoIF

U

1

~

500

9

7511

.n

RED DRIVE

5111

7

11

IN

27

~~8

10 JoIF

iDEo

2

5111

V

"

V

28

10k

u
B

1

6

7511

IN

:::!;; 100 JoIF

......,

10 JoIF

Ii 0

iDEo

Tvo
o12V

LM1203

4

10011

75

21

~II
5

500
20

10

19

11

18

12

17

13

16

14

IS

I

:........ GREEN
~UTOFF

f-<

~7
5111

=

,*'Jo1F

6

V

7

8

CONTRAST
CONTROL

max
10k

:........=
min

'7

'*

5kt

~0'01~ f-

~+I--

~7

500

0.1 JoIF
10k

---.J.L

BLACK LEVEL
GATE IN

10k
10k

'*

BLUE

==CUTOFF
1 JoIF

9

BLACK LEVEL
(BRIGHTNESS)
CONTROL

~~7 ~O"Jo1F

75

10
11

1000 pF

~r+i~
-

100V

-

o90V

TLIK/11125-10

FIGURE 6. Typical Application LM1203-LM2418 Application

3-140

~National

PRELIMINARY

~ Semiconductor

LM2419
Triple 65 MHz CRT Driver
General Description

Features

The LM2419 contains three wide bandwidth, large signal
amplifiers designed for large voltage swings. The amplifiers
have a gain of -15. The device is intended for use in color
CRT monitors and is a low cost solution to designs conforming to 1024 x 768 display resolution.

•
•
•
•
•

The device is mounted in the industry standard 11-lead
TO-220 molded power package. The heat sink is electrically
isolated and may be grounded for ease of manufacturing
and EMI/RFI shielding.

50 Vpp output swing at 65 MHz
Rise/Fall time < 7 ns with 12 pF load
60 Vpp output swing capability
Pin and function compatible with LM2416
No low frequency tilt

Applications
• CRT driver for SVGA, IBM 8514 and 1024 x 768
display resolution RGB monitors

Schematic and Connection Diagrams
One Channel

~

. . . - - -.....--0 Y+

11

11

~

Your
3,4,10

R3
YSIAS

2,7,9

Y+

10

0

150
R4

9

8

r<: '.

IlL

550
YIN

1,6,8

7
6

5

GND

4

3

GND

5

-

TUH/11442-1

"

~o

2

1

/'

./
PIN 1 DESIGNATOR
TLlH/11442-2

Order Number LM2419T
See NS Package NumberTA11B

3-141

Section 4
Display Drivers

Section 4 Contents
Display Drivers-Introduction ........................................................
Display Drivers-Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8187 Vacuum Fluorescent Display Driver......... ........................ ..........
DS75491 MOS·to·LED Quad Segment Driver ................ . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75492 MOS·to·LED Hex Digit Driver................. ..... ......................... .
DS55494/DS75494 Hex Digit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5450/MM5451 LED Display Drivers ...............................................
MM5452/MM5453 Liquid Crystal Display Drivers ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5480 LED Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5481 LED Display Driver . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5483 Liquid Crystal Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5484 16·Segment LED Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5486 LED Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58201 Multiplexed LCD Driver ....................................................
MM58241 High Voltage Display Driver ................................................
MM58242 High Voltage Display Driver ................................................
MM58248 High Voltage Display Driver ................................................
MM58341 High Voltage Display Driver.............................................. ..
MM58342 High Voltage Display Driver ................................................
MM58348 High Voltage Display Driver ................................................
LM3909 LED Flasher/Oscillator.................................................... ..
LM3914 Dot/Bar Display Driver........................... ...........................
LM3915 Dot/Bar Display Driver. ... ..................................................
LM3916 Dot/Bar Display Driver.... ............................. .....................

4·2

4·3
4·4
4·6
4·17
4·17
4·20
4·22
4·28
4·35
4·39
4·43
4·46
4-49
4·54
4·60
4·65
4·70
4·75
4·80
4·85
4·90
4·97
4·112
4·130

~National

~ Semiconductor

Display Drivers

National's comprehensive family of display drivers provides
direct interface to all of the common display technologieslight-emitting diode (LED), liquid crystal display (LCD), and
vacuum fluorescent (VF).

for direct or multiplexed interface to large complex VF panel
arrays or 5 X 7 (or larger) dot-matrix character strings. Each
of the drivers are cascadable for further expansion. Application note AN-371 provides further details and other application information.

FUNCTION SIMILAR FAMILY

THE MM5450 SERIEs-LED

Each driver utilizes a simple serial-data input channel, onchip shift register, latches and buffer/driver outputs. The
serial input channel allows direct interface to most microprocessors, including COPSTM, NSC800™, 8080 series,
and TMS1000 series. Besides a serial-data input, each driver requires a clock input. Some offer a latch (data) input
and/or data output for easy cascade interconnect of additional drivers.

National's MM5450 series of LED display drivers rounds out
this comprehensive product family. This popular series offers direct drive of LED displays by providing up to 25 mA of
current drive per LED segment.

MOS/LSI DISPLAY DRIVERS

CMOS/LSI
Many of the products in the display driver family utilize
CMOS technology and are further evidence of National's
capabilities and commitment to CMOS/LSI-the technology
of the '80s.

Once loaded, the shift register data can be transferred to
the on-chip latches, which then output to the buffer/driver
and respective display. This buffer/driver is where each provides the unique driver interface desired by the particular
display technology-LED, LCD, or VF.

In addition, National offers a line of bipolar segment and
digit drivers with a broad range of output sink and source
currents.
Detailed featureslfunctions of the 16-member display driver
family are high-lighted in the following product guide.

THE MM58241 SERIES-VF
Each of the products in the MM58241 series provides highvoltage (several up to 60V) drive of VF displays. All are ideal
OUTPUT
32

OUTPUT
1

- - --

-- -BLANKING
CONTROL

32 OUTPUT
BUFFERS

---32 LATCHES

I+-

-- -DATA
IN

CLOCK

{>1

32-BIT
SHIFT REGISTER

DATA
OUT

"(..-

ENABLE

TL/XX/Ol 00-1

FIGURE 1. Typical Block Diagram
4-3

IINational

,

Semiconductor

.,

LSI Display Driver
Selection Guide

Display
Technology

Product
Number

Vacuum
Fluorescent (VF)

MM58241

32-segment, direct/multiplexed drive to 60V, data enable, brightness control,
cascadable, 40-pin DIP or 44-pin PCC package.

VF

MM58242

20-digit, direct/multiplexed drive to 6OV, data enable, brightness control,
cascadable, 28-pin DIP or PCC package.

VF

MM58248

35-segment, direct/multiplexed drive to 60V, pin-compatible to MM5448, 40-pin
DIP or 44-pin PCC package.

VF

MM58341

32-segment, direct/multiplexed drive to 35V, data enable, brightness control,
cascadable, 40-pin DIP or 44-pin PCC package.

VF

MM58342

20-digit, direct/multiplexed drive to 35V, data enable, brightness control,
cascadable, 28-pin DIP or PCC package.

VF

MM58348

35-segment, direct/multiplexed drive to 35V, pin-compatible to MM5448, 40-pin
DIP or 44-pin PCC package.

Liquid Crystal
(LCD)

MM5452

32-segment, direct drive, serial-data input, data enable, on-chip backplane (S/P)
oscillator, 40-pin DIP or 44-pin PCC package.

LCD

MM5453

33-segment, direct drive, serial-data input, S/P oscillator, 40-pin DIP or 44-pin
PCC package.

LCD

MM5483

31-segment, direct drive, serial-data input/output,latch (data) control, 4O-pin DIP
or 44-pin PCC package.

LCD

MM58201

Multiplexed drive, 192 segments (8 backplanes, 24 segments), 192-bit RAM,
cascadable, R/C oscillator, serial-data input/ output, 40-pin DIP or 44-pin PCC
package.

Light-Emitting
Diode (LED)

MM5450

34-segment, direct drive up to 25 mA, brightness control, data enable, 40-pin DIP
or 44-pin PCC package.

LED

MM5451

35-segment, direct drive up to 25 mA, brightness control, 40-pin DIP or 44-pin
PCC package.

LED

MM5480

23-segment, direct drive up to 25 mA, serial-data input, brightness control, 28-pin
DIP package.

LED

MM5481

14-segment, direct drive up to 25 mA, serial-data input, brightness control, 20-pin
DIP package.

LED

MM5484

16-segment, direct drive up to 10 mA, serial-data input! output, cascadable,
22-pin DIP package.

LED

MM5486

33-segment, direct drive up to 25 mA, serial-data input! output, brightness
control, latch (data) control, 40-pin DIP package.

Features

4-4

~National

Semiconductor

Bipolar Display Driver
Selection Guide

Device Number
and Temperature Range
O"Cto +70"C

100DIgit (mA)
Drlverel
Package

-55"Cto + 125"C

DS75491

Sink
(Common
Anode)

VMAX(V)

Source
(Common
Cathode)

Input

50

Comments
Supply

10

10

6

150

10

10

DS75492

6

250

10

10

LM3909

1

45

45

2.1

6.4

LED Flasher/
Oscillator

LM3914

10

0

30'

35

25

Dot/Bar Driver
Linear Scale

LM3915

10

0

30'

35

25

Dot/Bar Driver
Log Scale

LM3916

10

0

30'

35

25

Dot/Bar Driver
VU Meter Scale

DS75494

4
DS55494

Enable Control

'Per segment. use common external supply lor anodes

•
4-5

r-

CD
....

r--------------------------------------------------------------------------------,

National
~ '?A
~ Semiconductor
DS8187 Vacuum Fluorescent Display Driver
General Description

Features

The D88187 is a vacuum fluorescen1 display 1ube driver.
This device is implemen1ed in CMOS 1echnology, 10 provide
high vol1age ou1pu1 drivers and low power. Dimming may be
accomplished by ei1her analog or digi1a1 input AU10load capabili1y is accomplished by connec1ing 1he DATA OUT pin 10
1he LOAD ENABLE inpu1 pin, wi1h 1he addi1ion of a s1art bi1
10 1he inpu1 da1a s1ream.

• 33 Segmen1 Direc1 Drive 25 - 0.8 mA and 8 - 2 mA
ou1pu1 drivers
• 49 s1eps of dimming, mask programmable
• Analog or digi1a1 inpu1 dimming con1rol
• DATA OUT pin for cascading
• Mask op1ions allow reconfiguring of ou1pu1S wi1h
respec110 shift regis1er bi1 posi1ion
• Au1010ad or eldernal load capabili1y

Block Diagram
OUTPUT 33

OUTPUT 1

Vee

DATA
OUT

BLANK INI
PWM OUT
OSC

----+

VD

TLlF/11220-4

FIGURE 1.

4-6

Absolute Maximum Ratings
If Military/Aerospace specHled devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Power Dissipation (PD) at 2S'C
DIP Board Mount
DIP Socket Mount

Supply Volltage (Vee>

Typical Values
8JA DIP Board Mount
8JA DIP Socket Mount

-0.3 to +20V

DC Input Voltage (VIN)

-0.3 to VCC+0.3V

DC Output Voltage (VOUT)
Storage Temperature Range

TBD
TBD

TBD'C/W
TBD'C/W

-6Sto +1S00C

Lead Temperature (Soldering, 10 sec.)

2600C

Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
Temperature Range
Electro-Static Discharge (ESD)

Min
8
0
-40

Max
18
Vee
+8S
2K

Unit
V
V
'C
V

DC Electrical Characteristics
Vee = 8V to 18V, All voltages referenced to GND, unless otherwise specified
Symbol

Parameter

Conditions

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IIHl

High Level Input Current
(Clock, Data In, Load, VK)

VIHl = S.OV

IIH2

High Level Input Current
(Blank)

VIH2 = S.OV, T = 2S'C

IIH3

High Level Input Current
(TEST2)

VIH3 = %.OV, T = 2S'C

IILl

Low Level Input Current
(Clock, Data In, Load, VK)

VILl = OV

11L2

Low Level Input Current
(BLANK IN)

VIL2 = OV, T = 2S'C

IlLS

Low Level Input Current
(TEST2)

VILS = OV, T = 2S'C

III

Input Leak Current
(VD)

VINOVt06V

VOHl

High Level Output Voltage
(Low Current Driver)

Vee = 9.SV, IOHl = -0.8 rnA

VOH2

High Level Output Voltage
(High Current Drive)

Vee = 9.SV, IOH2 = -2 rnA

VOH3

High Level Output Voltage
(DATA OUT, PWM OUn

Vee = 9.SV, IOH3 = -200
IOH3 = - 20 /LA

VOL1

Low Level Output Voltage
(All Drivers)

Vee = 9.SV,

VOL2

Low Level Output Voltage
(DATA OUT,PWM OUn

Vee = 9.SV, IOL2 = 200

Icc

Supply Current

No Load

JLA

IOL1 = SOO JLA
IOL1 = 200 /LA
IOL1 = 2/LA

JLA

Note 1: Absolute maximum ratings are those valuaa beyond which damage to the devloa may occur.

4-7

Min

Max

Units

3.8

6

V

0

0.8

V

-S

S

/LA

-20

10

/LA

-100

20

/LA

-S

S

/LA

-12S

-S

JLA

-700

-100

/LA

-S

S

JLA

Vee- 0.8

V

Vee- 0.8

V

4
4.S

6
6

V
V

2
1
0.3

V
V
V

0.8

V

20

rnA

AC Electrical Characteristics
Symbol

Parameter

Conditions

Min

Max

Units

250

kHz

fe

Clock Frequency

PWe

Clock Pulse Width

1.3

t8

Data Set-Up Time

1

jA.S

tH

Data Hold Time

200

ns

jA.S

PWL

Load Pulse Width

tooa

Output Delay from Blank

CL = 100pF

1.3
7

jA.S

tOOL

Output Delay from Load

CL = 100pF

8

jA.S

tr

Rise Time (All Driver Outputs)

CL = 100 pF, t = 20% to 80% of Vee

5

jA.S

tl

Fall Time (All Driver Outputs)

CL = 100 pF, t = 80% to 20% of Vee

5

jA.S

/los

Dimming Characteristics
DC Characteristics
Parameter
Vo Offset Voltage
(Note 2)

Min

Conditions
±Vo (3%

Typ

+ 6%)

Max

Units

±10

mV

AC Characteristics
Parameter
Pulse Width Error

Conditions

Min

PWM OUT Frequency
OSC Frequency
Note 2: Reference voltage is S.W typical.
Note 3:

Typ

No Load (Note 3)

Under the Ideal condition of DC parameter•.

AC Test Conditions
Input Pulse Levels
0.5Vt03.5V
6 ns (10% to 90%)
Input Rise and Fall Times
Propagation Delays Measured at 20% and 80% points
of respective waveforms

4-8

Max

Units

±1oo

ns

150

250

400

Hz

307.2

512

819.2

kHz

Timing Waveforms

Clook

DATA IN

LOAD
ENABLE

DUTl-OUT33

OUTl-OUT33

--::ftr
FIGURE 2.

4-9

TUF/11220-3

Functional Description
SHIFT REGISTER OPERATION
Refer to block diagram Figure 1 while LOAD ENABLE is
low, data is entered into the shift register on the rising edge
of the clock. The first data bit entered is stored in position
#0, the last data bit entered is stored in poSition #33. A
high voltage level applied to the LOAD ENABLE input transfers the data from the shift register to the data latch. The
data is presented to the output drivers through a 33 x 33
matrix. This matrix determines shift register output designation. The D88187 has 34 shift register positions, 33 data
latches, and 33 output drivers.

DIRECT LOAD MODE
In this mode the DATA OUT pin is not connected to the
LOAD ENABLE pin. The LOAD ENABLE pin is controlled
directly by ~he user. When LOAD ENABLE goes High, the
contents of the shift register are latched, presented to the
output drivers through the 33 x 33 PLA matrix, and the shift
register is cleared.
DIMMING FUNCTION
When VK is Low, the ..
B....
LA"N"'Kr.'rnN/PWM OUT pin functions as
an input blanking signal. When BLANK IN/PWM is High, the
output duty cycle is 100%. The duty cycle of a user supplied
signal to this pin will determine the brightness of the output.
When VK is High, the duty cycle of the output drivers is
controlled by an analog voltage applied to the VD pin.
Table I indicates the duty cycle of the output drivers with
respect to the analog voltage applied to VD pin.

AUTO LOAD MODE
In this mode, the DATA OUT pin is connected to the LOAD
ENABLE pin. The data word consists of 34 bits including a
leading start bit(logic 1). On the pOsitive-going-edge of the
34th clock (LOAD ENABLE goes High), data is transferred
to the data latches and the shift register is cleared.

Connection Diagram
Dual-In-Llne Package
BLANK INtpWt.l

TEST 2
~OAD ENAB~E

HC

DATA IN

DATA OUT

C~OCK

GND

VD

OSC

Vee

MC

'ffii1

VK

OUTPUT 1

OUTPUT 33

OUTPUT 2

OUTPUT 32

OUTPUT 3

OUTPUT 31

OUTPUT 4

OUTPUT 30

OUTPUT 5

OUTPUT 29

OUTPUT 6

OUTPUT 28

OUTPUT 7

OUTPUT 27

OUTPUT 8

OUTPUT 26

OUTPUT 9

OUTPUT 25

OUTPUT 10

HC

OUTPUT 11

OUTPUT 24

OUTPUT 12

OUTPUT 23

OUTPUT 13

OUTPUT 22

OUTPUT 14

OUTPUT 21

OUTPUT 15

OUTPUT 20

OUTPUT 18

OUTPUT 19

OUTPUT 17

OUTPUT 18
TL/F/11220-1

Top View
Order Number DS8187N
See NS Package Number N48A

4-10

Analog Dimming and Vo Offset
Description

Load Enable Description
The positive going edge of the Load Enable input signal
latches data from the shifter and resets the shifter. While
Load Enable is "high", the shifter will not accept data. The
Load Enable should be driven high during the low level of
the clock.

When using analog dimming, the brightness attainable is
10.2% of maximum brightness. The voltage (VREF) is the
external voltage from which Vo is developed (usually from a
variable resistor). This voltage should be in the range of
5.7V to Vee so that the maximum 10.2% PWM duty cycle is
achieved easily.

Output Circuit Description
The segment output drivers are push-pull active high. There
are 25 low current drivers (0.8 mAl and 8 high current drivers (2 mAl. These outputs nominally swing from 0.3V to
(Vee - 0.8V) and are designed to drive the anodes of low
voltage (about 13V) vacuum fluorescent displays. The digital outputs (DATA OUT and PWM OUn typically swing form
0.5V to 5V and are designed to drive other logic devices.
For example, referring to (Figure 3), if 058187 devices are
cascaded, then DATA OUT and PWM OUT of the first are
connected respectively to DATA IN and BLANK IN of the
second.

The Vo offset error represents the difference between the
actual analog input voltage when using analog dimming and
the internal analog voltage created by the 0/ A converter.
Table III indicates the PWM duty cycle with respect to voltage at the Vo pin over 49 steps of dimming. To determine
the Min/Max PWM, Vo offset must be subtracted from/added to the threshold voltage of Table III. The Dimming Curves
(Figure 6) are a graphical representation of Table III showing the Vo offset.

Figures 3,4 and 5 are typical applications of the 058187.
+I2V

T
33 out.uta

LOAD
CPU or
Microcontroller

1

ENABLE

L IH t>

vee

LE

CLOCK

T

H

LE

Vee

33 out.utl

L-.s

DATA IN

t---

vr
--~-anod"
Display Tube

DATA OUT
BLANK IN/PWM OUT

DATA IN

r---' Bi:AiiifiN
OS8187
r- VD

OS8187
r- VD

~ VK

Grid

I- --

vrt

~ VK

GND

OSC

GND

OSC

I

I

I

I

•

J7 ... ,.

•

FIGURE 3. Cascading Two Drivers with Digital Dimming

4-11

TLlF/11220-2

Pin Description
PinHo.

Pin Name

DescripUon

110

1

TEST2

I

This pin is used to select TESTMODE. (Factory Test)

2

LOAD ENABLE

I

While Low, data is enabled into the shift register. When this pin goes High, the
contents of the shift register are loaded into the latch circuit and the shift
register is reset to O.

3

DATA IN

I

This pin inputs data to the shift register. When data is High, the output is ON.
When data is Low, the output is OFF.

4

CLOCK

I

This pin is the clock for the shift register. Data is input to the shift register on
the positive-going-edge of the clock.,

5

VD

I

This analog voltage Input pin specifies the output duty cycle per Table I.
This is the power supply pin.

6

Vee

7

'I'ESTT

8-14

OUTPUT 1 to
OUTPUT 7

0

These are low current output pins.

15-22

OUTPUT 8 to
OUTPUT 15

0

These are high current output pins.

23-31

OUTPUT 16to
OUTPUT 24

0

These are low current output pins.

This pin is used to select TEST MODE. (Factory Test)

32

No Connect (NC)

33-41

OUTPUT 25 to
OUTPUT 33

0

These are low current output pins.

42

VK

I

VK input terminal. This pin selects between analog dimming and digital
dimming (duty cycle). When a Logic 0 is applied to VK, the BLANK IN/PWM
OUT pin functions as an input blanking Signal. When a Logic 1 is applied to
VK, the dimming is controned by an analog voltage applied to the VD pin.

I

This pin generates an oscination of 500 kHz with an external capecitor of
47 pF connected between the OSC pin and GND.

43

No Connect (NC)

44

OSC

45

GND

46

DATA OUT

47

No Connect (NC)

48

BLANK IN/PWM
OUT

Free pin, no connection to the chip.

Free pin, no connection to the chip.

This is the GND pin.

110

This pin outputs~he data from the 34-bit shift register. Connecting the pin to
the DATA IN pin on the next stage provides a cascade connection.
Connecting the pin to the LOAD ENABLE pin causes the contents of the shift
register to be latched on the leading edge of the signal at the DATA OUT pin.
(Auto load function). In the Test Mode, this pin functions as an input.

110

When the internal dimming function is not used (VK Low), this pin receives
an external blank Signal and controls the output duty cycle. This pin functions
as an output when the internal dimming function is used (VK = High), and in
Test Mode.

Free pin, no connection to the chip.

4-12

Typical Application
+12V

CLOCK
CPU or
IIlcrocontrolier

Vee

LDAD ENABLE
VREF (6V typical)

+12

7.Skll
approx ".BV

33 out uto

DATA IN

t

anod.s
VF Di.play Tub.
VD
VF

---+ ....- - -... VK

Grid

------

OS8187

l

"7 pF

Skll
TLlFI11220-5

FIGURE 4. Analog Dimming Control Using the VD Pin

+12V

r------. CLOCK
CPU or
IIlorooontroll..

1-----...

Vee

33 out uti

DATA IN
LOAD ENABLE

.nod..

VF Display Tube

BWITN/PWIoI

Grid

OS8187
OUT
VF

l

OSC
GND

TL/F/11220-7

FIGURE 5. Dlgltsl Dimming Using the BLANK IN/PWM OUT Pin

4·13

TABLE I. Output Pin to ShiH Register Conversion for Pattern "AA"
Pin Name

ShiH Register

Pin Name

Shift Register

Pin Name

Shift Register

OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
OUTPUT 8
OUTPUT 9
OUTPUT 10
OUTPUT 11

BIT14
BIT15
BIT 1
BIT 33
BIT5
BIT 6
BIT7
BIT 28
BIT27
BIT31
BIT18

OUTPUT 12
OUTPUT 13
OUTPUT 14
OUTPUT 15
OUTPUT 16
OUTPUT 17
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22

BIT2
BIT10
BIT 26
BIT 29
BIT8
BIT3
BIT9
BIT4
BIT 11
BIT16
BIT 17

OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33

BIT12
BIT19
BIT 24
BIT 25
BIT 20
BIT 32
BIT21
BIT22
BIT23
BIT30
BIT13

PLA Code Chart
OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
OUTPUT 8
OUTPUT 9
OUTPUT 10
OUTPUT 11
OUTPUT 12
OUTPUT 13
OUTPUT 14
OUTPUT 15
OUTPUT 16
OUTPUT 17
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33

PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
40
41

-~~~~~~~~O-~~~~~~~~O-N~~~~~~~O-N~

~~~~~~~~~----------NNNNNNNNNN~~~~

mmmmmmmmm~~~mm~m;mi~~miammimm~iim
TUF/11220-B

4-14

TABLE II. Customer Fill In, Output Pin to Shift Register Conversion
Pin Name

Shift Register

Pin Name

Shift Register

Pin Name

Shift Register

OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
OUTPUT 8
OUTPUT 9
OUTPUT 10
OUTPUT 11

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

OUTPUT 12
OUTPUT 13
OUTPUT 14
OUTPUT 15
OUTPUT 16
OUTPUT 17
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
OUTPUT 8
OUTPUT 9
OUTPUT 10
OUTPUT 11
OUTPUT 12
OUTPUT 13
OUTPUT 14
OUTPUT 15
OUTPUT 16
OUTPUT 17
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33

PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
40
41

-N~~~~~~~O-N~~~~~~~C-N~~~~~G~C-N~

~~~~~~~~~::::::::::::::::::::::::
~~mmmmmmmmm~mmmmmmmmmmmmmmmmmmmmm
TL/F/11220-6

4-15

•

TABLE III. VD Threshold Dimming Voltage V.s. PWM Duty Cycle (Typical Value at Vee = 12.8V)
10.2'% PWM Maximum
PulaeStep
Number

PWM Duty Cycle
Pulse Count

'%

Threshold
Voltage

PulaeStep
Number

VREF
VREF

PWM Duty Cycle

Threshold
Voltage

PulHCount

'%

26

56/2048

2.73

3.385

25

52/2048

2.54

3.323

VREF

24

48/2048

2.34

3.263

46/2048

2.25

3.204

49

208/2048

10.2

VREF

23

48

192/2048

9.38

4.621

22

44/2048

2.15

3.155

47

184/2048

8.98

4.541

21

42/2048

2.05

3.118
3.076

46

176/2048

8.59

4.488

20

40/2048

1.95

45

168/2048

8.20

4.434

19

38/2048

1.86

3.027

44

160/2048

7.81

4.381

18

36/2048

1.76

2.983

43

152/2048

7.42

4.333

17

34/2048

1.66

2.941

42

144/2048

7.03

4.286

16

32/2048

1.56

2.898

41

136/2048

6.64

4.231

15

30/2048

1.46

2.860

40

128/2048

6.25

4.170

14

28/2048

1.37

2.822

39

120/2048

5.86

4.106

13

26/2048

1.27

2.785

38

112/2048

5.47

4.043

12

24/2048

1.17

2.744

37

104/2048

5.08

3.980

11

23/2048

1.12

2.692

36

96/20411

4.69

3.914

10

22/2048

1.07

2.650

35

92/2048

4.49

3.831

9

21/2048

1.03

2.622

34

88/2048

4.30

3.766

8

20/2048

0.98

2.597

33

84/2048

4.10

3.719

7

0.93

2.569

32

80/2048

3.91

3.673

6

19/2048
18/2048

0.88

2.539

31

76/2048

3.71

3.631

5

17/2048

0.83

2.511

30

72/2048

3.52

3.594

4

16/2048

0.78

2.478

29

68/2048

3.32

3.551

3

15/2048

0.73

2.455

28

64/2048

3.13

3.501

2

14/2048

0.68

2.425

27

60/2048

2.93

3.444

1

13/2048

0.63

2.392
0.000

VDH

5

VD
(typIcal)

4.5

VDL
4
~
0
>

3.5
3
2.5
2
0

50

100

150

200

Pul.. Count (wIth ..opeet to 2048 oountl)
TUF/I1220-9

FIGURE 8. Dimming Curve
(Graphical Repreaentatlon of Table III)

4-16

i1
C

en
......

~National

UI

~

~ semiconductor

CD
.....
.......
c

en
......

DS75491 MOS-to-LED Quad Segment Driver
DS75492 MOS-to-LED Hex Digit Driver
General Description

Features

The DS75491 and DS75492 are interface circuits designed
to be used in conjunction with MOS integrated circuits and
common-cathode LEDs in serially addressed multi-digit displays. The number of drivers required for this time-multiplexed system is minimized as a result of the segment-address-and-digit-scan method of LED drive.

•
•
•
•
•

UI
~

CD

I\)

50 mA source or sink capability per driver (DS75491)
250 mA sink capability per driver (DS75492)
MOS compatability (low input current)
Low standby power
High-gain Darlington circuits

Schematic and Connection Diagrams
DS75491 (each driver)

DS75492 (each driver)
y

11.7.8,14)
A - . .-'\N\,........-t
4k

A-

.....

.---

(14, 3, &. 1.1'.12)

. . .."..,.,fY-...--1

11.2.&.7.8,131

4k

&.Ik

310

(11)

TO OTHER
DRIVERS

V..

TO OTHER
DRIVERS

(4)

(4)

GND

GilD

TUF/5830-1

TUF/5830-2

DS75492 Dual-In-Llne Package

DS75491 Dual-In-Llne Package
4A
14

lA

4E
13

IE

4C
12

lC

v..
11

GND

3C

3E

3A

IA

10

2C

14

ZE

ZA

IV

BV
13

2V

SA
12

2A

V..
11

GND

TL/F/5830-3

Top View

4-17

5Y

4A

10

3A

3V

4V

TLIF/5830-4

Top View
Order Number DS75491N or DS75492N
See NS Package Number N14A

SA

i:
,\

"

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DS75491 DS75492
-'-5V to Vss
Input Voltage Range (Note 4)
Collector Output Voltage (Note 5)
10V
10V
Collector Output to Input Voltage
10V
10V
Emitter to Ground Voltage (VI ~ 5V)
10V
Emitter to Input Voltage
5V
Voltage at Vss Terminal with Respect
to any Other Device Terminal
10V
10V
Collector Output Current
Each Collector Output
50mA
250mA
All Collector Outputs
200mA 600mA

D$75491
DS75492
Continuous Total Dissipation
600mW
600mW
Operating Temperature Range
O"Cto +70"C
Storage Temperature Range
-65'C to + 150'C
-Lead Temp. (Soldering. 10 sec)
300"C
300'C
Maximum Power Dissipation
at 25'C
Molded Package
1207 mW'
1280mWt
'Derate molded package 9.66 mW/'C above 25'C.
tDerate molded package 10.24 mWI'C above 25'C.

Electrical Characteristics Vss = 10V (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

0.9

1.2

V

1.5

V

I liN

100

p.A

I VIN

100

p.A

3.3

mA

DS75491
"ON" State Collector Emitter Voltage

VeE ON

"OFF" State Collector Current

ICOFF

Input = 8.5V through 1 kO. ITA
VE = 5V, Ie = 50 mA
I TA
Ve
VE

Input Current at Maximum Input Voltage

VIN

IE

Emitter Reverse Current

VIN

Iss

Current Into Vss Terminal

II

= 10V,
= OV

= 25'C
= 0-70"C

= 40 p.A
= 0.7V
= 10V, VE = OV, Ie = 20 mA
= OV, VE = 5V, Ie = 0 rnA

2.2

100

p.A

1

mA

1.2

V

OS75492
Low Level Output Voltage

VOL

High Level Output Current

IOH

Input = 6.5V through 1 kO, ITA
lOUT = 250mA
I TA
VOH

= 10V

Input Current at Maximum Input Voltage

Iss

Current Into Vss Terminal

V

I liN = 40 p.A

200

p.A

= 0.5V

200

p.A

3.3

mA

1

mA

I

2.2

VIN = 10V, IOL = 20 mA

Switching Characteristics Vss = 7.5V, TA =
Symbol

0.9

1.5

I VIN
II

= 25'C
= 0-70"C

25'C

I

Parameter

I

Conditions

Mini Typl Maxi Units

OS75491
tpLH

Propagation Delay Time, Low-to-High Level Output (Collector) I VIH = 4.5V, VE = OV.

tpHL

Propagation Delay Time, High-to-Low Level Output (Collector) I RL

= 2000, CL =

Propagation Delay Time, Low-to-High Level Output

= 7.5V, RL = 390,

I
15 pF I

I 100 I

ns

I 20 I

ns

I 300 I

ns

OS75492
tpLH

I VIH

I CL =

15 pF

I

Propagation Delay Time. High-to-Low Level Output
ns
tpHL
I 30 I
I
Note 1: "Absolute Maxtmum Ratings" are those values beyond which the safety of the devloe cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices shOuld be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to + 70'C temperature range for the 0575491 and 0875492.
Note 3: All currents Into device pins shown as positive, out of device pins as negative, all volteges referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basi•.
Note 4: The input is the only device terminal which may be negative with respect to ground.
Note 5: Voltege values are with respect to network ground terminal unless otherwise noted.

4-18

AC Test Circuits and Switching Time Waveforms
0875491

0875492
7.&V

........o---....-DUTPUT
c..
JINDTE!)

-I&,F

TL/F/5830-5

---J

r---SIOM

I )
V'H
1=--=±--i---------I
I

INI'UT

I

IIo..,;IOII:.;;.._ _ _ _ _ _ DV

lOll

_---VOH

&011

OUTPUT

I

I

I

I

:

f-------v

I

I

I
I

I
I

....L-1--j
Note 1: The pulse generator has the following characteristics: ZOUT

OL

~""H-l
~

5011, PAR

Note 2: CL Includes probe and Jig capacitance.

4-19

~

100kHz, tw

~

1 '"'S.

TUF/5830-7

~ r---------------------~------------------------------------------_.

G)

.......~

~National

~

0555494/0575494 Hex Digit Driver

!

~ Semiconductor

General Description

Features

The 0555494/0575494 is a hex digit driver designed to
interface between most MOS devices and common cathodes configured LED's with a low output voltage at high
operating currents. The enable input disables all the outputs
when taken high.

•
•
•
•
•
•
•

150 mA sink capability
Low voltage operation
Low input current for MOS compatibility
Low standby power
Display blanking capability
Low voltage saturating outputs
Hex high gain circuits

Schematic and Connection Diagrams
Dual-In-Llne Package
Vee (181

INPUT

Vee

IN 8

OUT6

NC

IN lOUT 1

OUTS

IN &

OUT4

1N4

OUT2

IN 2

OUT 3

IN 3

CE

410

(2.5,1,18,121

TO OTHER
INPUTS

CHIP ENABLE

.A

(II

GND
TLlF/5832-2

Top View
Order Number DS55494J
or DS75494N
See NS Package Number J16A or N16A

GNO(II

TLlF/S832-1

Truth Table
Enable

VIN

0
0

0

1

1
X

0

1
x

~

don't care

4-20

VOUT

1

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
10V
Input Voltage
10V
Output Voltage
10V
-65·C to + 150·C
Storage Temperature Range
Maximum Power Dissipation" at 25·C
Cavity Package
1433mW
Molded Package
1362mW
Lead Temperature (Soldering 4 seconds)
260·C

Supply Voltage, Vee
Temperature, TA
0575494
0555494

Min
3.2

Max
B.B

Unlta
V

0
-55

+70
+125

·C
·C

'Derate cavity package 9.55 mW/'C above 25'C; derate molded package
10.9 mW I'C above 25'C.

Electrical Characteristics (Notes 2 and 3)
Symbol
I'H

Parameter
Logical "1" Input Current

= Min, Y,N = B.BV

IVeE = B.BVthrough 100k
IVeE = B.BV

= Max, Y,N = -5.5V
= Max, VOH = B.BV IY,N = B.BVthrough 100k, VeE =

I,L

Logical "0" Input Current

IOH

Logical "1 " Output Current Vee

VOL

Logical "0" Output Voltage Vee = Min, IOL = 150 mA, Y,N
VeE = B.BVthrough 100k

Vee

IY,N =

lee

Min Typ Max Units

Conditions
Vee

Supply Currents

= Max

Output "OFF" Time

tON

Output "ON" Time

IJA

400

p.A

400

p.A
V

0555494

0.25

0.4

V

0575474

B.O

mA

0555494

10.0

mA

IVOE = 6.5Vthrough 1.0k

100

p.A

100

p.A

40

IJA

0.04

1.2

p.s

13

100

ns

IY,N = B.BV through 100k
All Other Pins to GNO

tOFF

mA

-20

0.25 0.35

= B.BV

All Other Pins to GNO

mA

2.7

0575494

B.BV, VOE - 6.5V through 1.0k

= 6.5V through 1.0k,

One Driver "ON", Y,N

Vee

OV

2.0

= 20 pF, RL = 240, Vee = 4.0V, See AC Test Circuits
CL = 20 pF, RL = 240, Vee = 4.0V, See AC Test Circuits
CL

Note 1: ""Absolute Maximum Ratings"" ara those values beyond which the safety of the device cannot be guarantead. Thay are not meant to Imply that the devices
should be operated at these limits. The table of ""Electrical Characteristics"" provides conditions for actual device operation.
Note 2: Unle.. otherwise specified minImax limits apply aero.. the O'C to + 70'0 range for the 0875494 and across the - 55'0 to + 125'C range for the
0855494.
Nole 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unle.. otherwise noted. All values shown
as max or min on absolute value basis.

AC Test Circuit and Switching Time Waveforms
Vee

I--TF

V'No--

~

/

V..

HL

240
&%

10'1t

0

T•

80'It

,

TF -1On.

T. -10,.

1\&O'It

1011

-0.2 ... --- r--0.2m.-

~~CL

T20

t

lOll

V'N
VOUT

_r

PF

.,011

VOUT

TL/F/5832-3

L2.2V,1iO'It
O.IV

t"oFF

~2.2V

- .. !--t"oN
TL/F/5832-4

4-21

~ r---------------------------------------------------------~------------------------__,

In '

i-

~
;7;

::IE
::IE

~National

~ semiconductor

MM5450/MM5451 LED Display Drivers
General Description

Features

The MM5450 and MM5451 are monolithic MOS integrated
circuits utilizing N-channel metal-gate low threshold, enhancement mode, and ion-implanted depletion mode devices. They are available in 40-pin molded or cavity dual-in-line
packages. The MM5450/MM5451 is designed to drive common anode-separate cathode LED displays. A single pin
controls the LED display brightness by setting a reference
current through a variable resistor connected to VOO.

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts

Continuous brightness control
Serial data input
No load signal required
Enable (on MM5450) ,
Wide power supply operation
TTL compatibility
34 or 35 outputs, 15 rnA sink capability
Alphanumeric capability
8JA DIP
Board = 49"C/W
Socket = 54°C/W

Block Diagram
VOO
BRIGHTNESS
CONTROL

1""""'--=:-:-::---"

DATA ENABLE (MM54501
OUTPUT3S (MM5451)

OUTPUT 34

24

OUTPUT I

IB

...;;+-_

~_ _ _

S~~~~~_~_-=i-~
CLOCK ....---~....

> ____...t
TUF/6'36-'

FIGURE 1

4-22

Absolute Maximum Ratings
Power Dissipation at + 25'C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature

VSS - 0.3VtoVss + 12V
- 25'C to + 85'C

Storage Temperature

-65'C to

Junction Temperature
Lead Temperature (Soldering, 10 sec.)

'Molded DIP Package board mount, 8JA = 49'C/W,
Derate 20.4 mWI'C above 25'C.
··Molded DIP Package, socket mount, 8JA = 54'C/W,
Derate 18.5 mWI'C above 25'C.

+ 150'C
+ 150'C
300'C

Electrical Characteristics

T A within operating range, VDD = 4.75Vto 11.0V, Vss = OVunlessotherwise specified
Conditions

Parameter

Power Supply
Power Supply Current
Input Voltages
Logical "0" Level (VO
Logical "1" Level (VH)

Typ

Min
4.75

Max
11
7

Units
V

O.B
Voo
Voo
0.75

V
V
V
rnA

10

p.A

10
4
25
4.3
±20

p.A
rnA
rnA

500
950
950

kHz
ns
ns

300
300

ns
ns

100

ns

Excluding Output Loads
± 10 p.A Input Bias
4.75V ,;;; Voo ,;;; 5.25V
Voo> 5.25V

Brightness Input (Note 2)
Output Sink Current
Segment OFF
Segment ON

2.5W·
2.3W··

-0.3
2.2
Voo - 2V
0

VOUT = 3.0V
VOUT = 1V (Note 3)
Brightness Input = 0 p.A
Brightness Input = 100 p.A
Brightness Input = 750 p.A
Input Current 750 p.A

Brightness Input Voltage (Pin 19)
Output Matching (Note 1)
Clock Input
(Notes 5 and 6)
Frequency.lc
High Time,lt,
LowTime,tl
Data Input
Set-Up Time, tos
Hold Time, tOH
Data Enable Input
Set-Up Time, tOES
Note 1: Output matching is calculated as the percent variation (IMAX + IMIN)/2.

0
2.0
15
3.0

2.7

mA

V
%

Note 2: With a fixed resistor on the brightness input pin, some variation in brightness will occur from one device to another. Maximum brightness input current can

be 2 rnA as long as Note 3 and junclion temperature equation are complied with.
Note 3: See Figures 5, 6, and 7 for Recommended Operating Conditions and limits. Absolute maximum for each output should be limited to 40 rnA.

Note 4: The VOUT voltage should be regulated by the user. See F/{Jures 6 and 7 lor allowable VOUT vs lOUT operation.
Note 5: AC input wavelorm specification lor test purpose: Ir ,;; 20 ns, tf ,;; 20 ns, I = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and lall times must not exceed 300 ns.

Connection Diagrams
Dual-In-Line Package.
VIS~
OUTPUT lIT

114

:~:~~:~!:~

OUTPUT lIT I.""';
OUTPUT lIT 13"';

OUll'UTIIT12~

OUTPUTIIT"-:OUTPUTIIT10-=
oUTPUT 81T I~

OUTPUT81T1~
DUTPUT81T7~
OUTPUTIITI~
OUTPUTIIT6~
DU"UTIIT4~
OUTPUTI1T3~

Dual-In-Line Package

~ OUTPUT liT II
~ OUTPUT liT I.
~OUTPUTIITZO
~OUTPUTI1T21
~ OUTPUT lIT 22
~OUTMIIT23

Vss~
OUTPUT alT

OUTflUT liT 1.";

OUTPUTBIT13~

OUTPUT BIT 12-:

OUTPUTIITI1~
OUTPUTBIT10~
OUTPUTaIT9~
OUTPUTIITI~

~OUTPUT8IT2&

?'OUTPUTIITZI

~OUTPUTIIT27
~OUTPUT8IT2I
~OUTPUT8ITZI

~OUTPUT8ITI3
~ oUTPUTSIT34

OUTPUTIITI~

~OUTPUTIIT:J2
~OUTPUTIIT33
~ OUTPUT liT 34
~OUTPUTIIT36

OUT'UTIITZ...g

OUTPUTIIT'~

~ DATA IN
F-CLOCKIII

BRIGHTNESS CONTROL-ii
Voo"::'

F-CLOCKIIII

~OUTPUTBITZ1
~OUT'UTBIT2a
~OUTPUT'1T2a
~ OUTPUT alT 3D

r;. OUTPUT BIT 31

OUTPUT lIT 3";;

~ammm
~ DATAl.

IRICMTMSS COIITROL-ii
VOO"::

r¥.-OUTPU'BITZa
MM&4&1

OUTPUTBIT1~
OUTPUTaIT6~
OUTPUTI1T5~
OUTPUTBIT4~

~:~=::~:
~OUTPUT81T32

OUTPUTBIT2...g

~OUTPUTBIT2U
~OUTPUTIIT21
~OUTPUTIIT22
~OUTPUTIIT23
~OUTPUTaIT2.
~OUTPUTaIT25

:~:~::~~:~

~OU1l'UTIIT2'

......

~OUTPUTIITII
~OUTpuTIITla

11-i

TL/F/6136-3

TLlF/6136-2

Top View

Top View

FIGURE2b
FIGURE2a
Order Number MM5450N, MM5451N, MM5450Vor MM5451V
See NS Package Number N40A or V44A
4-23

....

~

In

:.
:.
....

Connection Diagrams (Continued)
: Plaatlc Chip Carrier

...~

:! :!! !!

:.

Illi;~iilii

Ii Ii

In

:.

~

:!!

I:: I::
CD

~

Ii: N l::I

Ii Ii Ii

CD

I::
CD

Ii

OUTPUT BIT 13
OUTPUT BIT 12

8

OUTPUT BIT 11

39

OUTPUT BIT 23

38

37

OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26

OUTPUT BIT 10

10

36

OUTPUT BIT 9

11

35

OUTPUT BIT 27

Nle

12

34

Nle

totM545OV

OUTPUT BIT 8

13

33

OUTPUT BIT 28

OUTPUT BIT 7

14

32

OUTPUT BIT 29

OUTPUT BIT 6

15

31

OUTPUT BIT 30

OUTPUT BIT 5

16

30

OUTPUT BIT 31

OUTPUT BIT 4

17

29

OUTPUT BIT 32

~~il

III ~

8

u

~

>~~

III

.li i
iii
~

~

r:!

Ii Ii

TLlF/8136-13

Top View
Plntlc Chip carrier

:! :!! !!
I::
CD

~

:!!

~

Ii: N l::I

Ii Ii Ii Ii Ii

Ii Ii Ii

iiil;~ III i I
OUTPUT BIT 13

7

OUTPUT BIT 12

8

OUTPUT BIT 23

OUTPUT BIT 11

38

OUTPUT BIT 24

37

OUTPUT BIT 25
OUTPUT BIT 26

OUTPUT BIT 10

10

36

OUTPUT BIT 9

11

35

OUyPUT BIT 27

Nle

12

34

Nle

tottot5451V

OUTPUT BIT 8

13

33

OUTPUT BIT 28

OUTPUT BIT 7

14

32

OUTPUT BIT 29

OUTPUT BIT 6

15

31

OUTPUT BIT 30

OUTPUT BIT 5

16

30

OUTPUT BIT 31

OUTPUT BIT 4

17

29

OUTPUT BIT 32

'" Ii Ii

i >Z~ii::

8~~jllIl~r:!

I::

N

~

Ui

CD

0

-

~ ~

CD

TLlF/6136-14

Top View

4·24

Functional Description
Both the MM5450 and the MM5451 are specifically deSigned to operate 4- or 5-digit alphanumeric displays with
minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is
accomplished with 2 signals, serial data and clock. Using a
format of a leading "1" followed by the 35 data bits allows
data transfer without an additional load signal. The 35 data
bits are latched after the 36th bit is complete, thus providing
non-multiplexed, direct drive to the display. Outputs change
only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 0.001 capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.

There must be a complete set of 36 clocks or the shift registers will not clear.

A block diagram is shown in Figure 1. For the MM5450 a
DATA ENABLE is used instead of the 35th output. The
DATA ENABLE input is a metal option for the MM5450. The
output current is typically 20 times greater than the current
into pin 19, which is set by an external variable resistor.
There is an internal limiting resistor of 4000 nominal value.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.

When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.
Figure 2 shows the pin-out of the MM5450 and MM5451. Bit
1 is the first bit following the start bit and it will appear on pin
18. A logical "1" at the input will turn on the appropriate
LED.
Figure 3 shows the timing relationships between data, clock
and bATA ENABLE. A max clock frequency of 0.5 MHz is
assumed.

Tj = (VOUT) (lLEO) (No. of segments)(8JA)
where:

Figure 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the 36th clock a LOAD
Signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

+ TA

Tj = junction temperature, 150"C max
VOUT = the voltage at the LED driver outputs
ILEO = the LED current
8JA = thermal coefficient of the package
T A = ambienttemperature
8JA (Socket Mount) = 54°C/W
8JA (Board Mount) = 4SOC/W
The above equation was used to plot Figure 5, Figure 6 and
Figure 7.

1F-==~-9D%

--~~10%

DATA

--....JF...............

DATA ENABLE
(MM54501
TUF/6136-4

FIGURE 3

4-25

•

Functional Description (Continued)

TL/F/6136-5

FIGURE 4. Input Data Format

Typical Performance Characteristics

g

2.0

~

1.5

~

IIIis

i

1,\

2.5

2.5

2.0

110
TA'lloC
Tj =lire (MAXI

100

~~} ~.l

o

o

1411211212421

0

1Il

60
80
«l
n:MPERATURE (oe)

100

1\

50
40
30
20
10

0.1

vOUT'2V

Jo!

'\..

o

5

ILEO (mAl

"

10

r-....
15

20

30

34

TL/F/6136-8

FIGURE 6

FIGURE 7

Typical Applications
_DC
>IV

Ik

1
TL/F/6136-9

FIGURE 8. Typical Application of Constant Current Brightness Control
5V

TLlF/6136-10

FIGURE 9. Brightness Control Varying the Duty Cycle

4·26

25

NUMBER OF SEGMENTS

TL/F/6136-7

TLlF/6136-6

FIGURE 5

- -

~OUTil.5~_

II

1.0

0

JOUT =1VHTA'15°C

H

l'

+~
.. f!!.~,,+
s!'
~~ ~
!'

0.5

-

10
II

Typical Applications (Continued)
Basic Electronically Tuned Radio System
LED DISPLAY

:/530
~'-

M--_liD

DISPLAY
DRIVER

KEYBOARD
r

COl'S
ELECTRONIC
TUNING
CONTROLLER

PLL
SYNTHESIZER

111

STATION
DETECT, ETC.
TLlF/6136-11

Duplexlng 8 Digits with One MM5450

•

MM5410

---.....1

CLOCK IN ....

DATA IN ...._ _ _ _.....1

......W\~~VDD

BRIGHTNESS
CDNTROL

1_
TVP

TL/F/6136-12

4-27

~ r---------------------------------------------------------------------------~

i~
Ln

~National

~ Semiconductor

Ln

~

:::IE

:::E

MM5452/MM5453 Liquid Crystal Display Drivers
General Description
The MM5452 is a monolithic integrated circuit utilizing
CMOS metal gate, low threshold enhancement mode devices. It is available in a 40-pin molded package. The chip can
drive up to 32 segments of LCD and can be paralleled to
increase this number. The chip is capable of driving a 4 Yzdigit 7-segment display with minimal interface between the
display and the data source.
The MM5452 stores display data in latches after it is
clocked in, and holds the data until new display data is received.

Features

•
•
•
•
•
•

DATA ENABLE (MM5452)
Wide power supply operation
TTL compatibility
32 or 33 outputs
Alphanumeric and bar graph capability
Cascaded operation capability

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial control indicator
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts
Remote displays

• Serial data input
• No load Signal required

Block Diagram

DATA ENABLE (MM54521 ~_ _ _""";;;""~I_--_----.
OUTPUT 33 (MM5453I r

s~~~~.-------~I---------~~>-----------1~~~~~~!l
CLOCK

.....

.-----------~I_------~ ~--------------

TUF/B137-1

FIGURE 1

4-28

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Voltage at Any Pin
Vss to VSS + 10V
Operating Temperature
O"Cto +70"C

Storage Temperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 sec.)

-65·Cto + 150"C
300 mWat + 70"C
350 mW at + 25·C
+ 150"C
300"C

Electrical Characteristics
TA within operating range, Voo

= 3.0V to 10V, Vss = OV, unless otherwise specified

Parameter

Condltlona

Min

Power Supply
Power Supply Current

3
Excluding Outputs
OSC = Vss, BP IN @ 32 Hz
Voo = 5V, Open Outputs, No Clock

Clock Frequency
Input Voltages
Logical '0' Level
Logical '1' Level
Output Current Levels
Segments
Sink
Source
Backplane
Sink
Source

Voo < 4.75
Voo:<: 4.75
Voo> 5.25
Voo ~ 5.25

-0.3
-0.3
0.8Voo
2.0

Voo = 3V, VOUT = 0.3V
Voo = 3V, VOUT = Voo - 0.3V

20

Voo = 3V, VOUT = 0.3V
Voo = 3V, VOUT = Voo - 0.3V

320

Typ

Max

Units

10

V

40
10

,...A
,...A

500

kHz

0.1 Voo
0.8
Voo
Voo

V
V
V
V

-20

,...A
,...A

-320

,...A
,...A

Output Offset Voltage

Segment Load 250 pF
Backplane Load 8750 pF (Note 1)

±50

mV

Clock Input Frequency, fe

(Notes 2 and 3)

500

kHz

HighTime,t.,

950

ns

LowTime,1j

950

ns

Data Input
Set-Up Time, tos
Hold Time, tOH

300
300

ns
ns

Data Enable Input
100
ns
Set-Up Time, tOES
Nota 1: This parameter is guaranteed (not 100% production tested) over oparating temperature and supply voHage ranges. Not to be used in Q.A. testing.
Nota 2: AC input waveform for test purposa: Ir ,; 20 ns, tf ,; 20 ns, f - 500 kHz, 50% ± 10% duty cycle.
Nota 3: Clock input rise and fall times must not excaed 300 ns.

4-29

~ r-------------------~----------------------------------------------------------__.

...
II)
II)

Connection Diagrams

::::E

Dual-In-Line Package

~

Vss

II)

OUTPUT BIT 11

::::E
:i!

OUTPUT BIT 16

~

Dual-In-Line P\lckage

40 OUTPUT BIT ,.
39
OUTPUT BIT "
31

40

Vss

31

OUTPUT BIT 11

OUTPUT BIT 2D

OUTPUT 81T ,.

OUTPUT BIT 15

OUTPUT BIT 21

OUTPUT BIT 15

OUTPUT BIT,4

OUTPUTBIT22

OUTPUT BIT 14

OUTPUT BIT 13

OUTPUT BIT 23

OUTPUT BIT 13

OUTPUT BIT 12

OUTPUT BIT 24

OUTPUTBIT 12

OUT'UT BIT 11

OUTPUT BIT 25

OUTPUT BIT 11

OUTPUT BIT 10

OUTPUTBIT 21

OUTPUTBITI
OUTPUT BIT a

OUTPUTBIT27

MM6452

OUTPUT BIT "
OUTPUT BIT 20
37
OUTPUT liT 21
36
OUTPUT BIT 22
35
OUTPUT 8,123
34
OUTPUTBIT24
33
OUTPUT BfT 25

OUTPUT 81T 9
OUTPUT BIT 8

OUTPUT BIT Z9

OUTPUT BIT J

OUTPUT BIT6

OUTPUT BIT 30
OUTPUT BIT 31

OUTPUTBIT6
I.
OUTPUT BIT 5
15
OUTPUT BITC
,6
OUTPUT BIT 1

OUTPUTBIT 32

OUTPUT BIT 3

mA'EiAiii:E

OUTPUT BIT 2

BACKPLANE IN

OUTPUT BIT 1

OKIN
VDO

21

20

OUTPUT BIT 28

12

OUT'UT 8ITZ9

13

27
26

25
2.

17

OUTPUT BIT Z
11
OUTPUT BIT 1
I.
OSC IN
20
VDO

BACKPLANE OUT
19

OUTPUTBIT27

MM6463

11

OUTPUT BIT 21

OUTPUT 81T4

OUTPUT liT 26

10

OUTPUTBIT7

OUTPUT BIT 5

DATA IN
CLOCK IN

OUTPUT BIT "

31

23

zz
21

OUTPUT BIT 3D

OUTPUT liT 31

OUTPUT BIT 32
OUTPUT BIT 33
BACKPLANE IN

BACKPLANE OUT
OATA IN
CLOCK IN

TL/F/6137-2

TL/F/6137-3

Top View
FIGURE2a

Top View
FIGURE2b

Plastic Chip Carrier
;! ~ !!!

:::

:2

~ ~

N

Plastic Chip Carrier

:::

Iii Iii Iii Iii
!:i ::::) S

Iii Iii Iii Iii Iii

000

0000

;! ~ ~

:::

Iii Iii Iii Iii

~u ~ ~ ~ ~ ~
555 ~5>~

:2

~ ~

N

:::

Iii Iii Iii Iii Iii

5

5

~ ~

I I I §JI~ ~ ~ ~ ~ §

0

:::)

0

OUTPUT BIT 13

OUTPUT BIT 23

OUTPUT BIT 13

39

OUTPUT BIT 23

OUTPUT BIT 12

38

OUTPUT BIT 24

OUTPUT BIT 12

38

OUTPUT BIT 24

OUTPUT BIT 11

37

OUTPUT BIT 25

OUTPUT BIT 11

37

OUTPUT BIT 25

36

OUTPUT BIT 26

OUTPUT BIT 10

10

36

OUTPUT BIT 26

OUTPUT BIT 10

10

OUTPUT BIT 9

11

35

OUJPijT BIT 27

OUTPUT BIT 9

11

OUTPUT BIT 8

12

34

OUTPUT BIT 28

OUTPUT BIT 8

12

OUTPUT BIT 7

13

33

OUTPUT BIT 29

OUTPUT BIT 7

13

OUTPUT BIT 29

OUTPUT BIT 6

14

32

OUTPUT BIT 30

OUTPUT BIT 6

14

OUTPUT BIT 30

OUTPUT BIT 5

15

31

OUTPUT BIT 31

OUTPUT BIT 5

15

OUTPUT BIT 31

OUTPUT BIT 4

16

30

OUTPUT BIT 32

OUTPUT BIT 4

16

OUTPUT BIT 3

17

29

Nle

OUJPijT BIT 3

17

MM5452V

_ z

u

'"

~m

. '"

8

U

!::

~ >

.......

0-

0

Z

I~

:iii!:

d '2i"
~""

a~

OUTPUT BIT 27

OUTPUT BIT 28

MM5453V

OUTPUT BIT 32
29

OUTPUT BIT 33

Ii

~ ~ is
::l !:! ;!

~ iiP

TL/F/6137-11

TLlF/6137-12

Top View

Top View
Order Number MM5452N, MM5453N,
MM5452V or MM5453V
See NS Package Number N40A or V44A

Functional Description
bits are latched after the 36th clock is complete, thus providing non-multiplexed, direct drive to the display. Outputs
change only if the serial data bits differ from the previous
time.

The MM5452 is specifically designed to operate 4 Yz-digit 7segment displays with minimal interface with the display and
the data source. Serial data transfer from the data source to
the display driver is accomplished with 2 Signals, serial data
and clock. Since the MM5452 does not contain a character
generator, the formatting of the segment information must
be done prior to inputting the data to the MM5452. Using a
format of a leading "1" followed by the 32 data bits allows
data transfer without an additional load signal. The 32 data

A block diagram is shown in Figure 1. For the MM5452 a
DATA ENABLE is used instead of the 33rd output. If the
DATA ENABLE signal is not required, the 33rd output can
be brought out. This is the MM5453 device.

4-30

Functional Description (Continued)
Figure 4 shows the input data format. A start bit of logical
"1" precedes the 32 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock. which loads the 32 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register. thus allowing continuous operation.

If the clock is not continuous. there must be a complete set
of 36 clocks otherwise the shift registers will not clear.
Figure 2a shows the pin-out of the MM5452. Bit 1 is the first
bit following the start bit and it will appear on pin 18.
Figure 3 shows the timing relationships between data. clock
and DATA ENABLE.

CLOCK

DATA

DATA ENABLE - - - - - - - - " " " " 1
(MM54521
TL/F16137-4

FIGURE 3
36
CLOCK

START BIT 1
DATA

BIT 35

BIT 36

tPle8._ealeqa

r--_

n. ______

(INTER~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....

n

RESET _ _ _ _ _ _ _ _ _ _ _ _ _1 ..
(INTERNALI
I _ _ _ _ _ _ _ _ _ _ _..1.

.._ _ _ __
TL/F/6137-5

FIGURE 4. Input Data Format

4-31

Functional Description (Continued)
Figure 5 shows a typical. application. Note how the input

are controllable. This application assumes iii specific display
pinout. Different display/driver connection patterns will, of
course, yield a different input data format.

data maps to the output pins and the display. The MM5452
and MM5453 do not have format restrictions, as all outpu.ta

Segment Iilentlficatlon

l-:-/b

3·

I

d

II'

.,

.-

F1 .1 .1 62 '2 A2 B2 63 F3 A3 83 64 F4 A4

Il-I l-Il-I l-I

le/~/e/~/./~./~

1~~~~~HU~~U~~~U"~U

~

L

I....-

'----

----

'----

- ----

r--

I....":'

Vss

1.
19

11

I.

20
21

~
~
13

~~
24

12

25

11
10
9
B
1

B
5
4
3
2
1
OSCIN

-r T~
~'-L,

26
21

MM5463

29
29
30
31
3Z

BACKPLANE OUT
BACKPLANE IN

I

33
DATA IN
~OCKIN

0.DI,u

":'

v+
DATA FORMAT
TIME-

LEfT END
DECIMAL
POINT

4TH

2ND
DECIMAL
POINT

DECIMAL
POINT

NULLS

I

I
TL/F/6137-6

Consun LCD manufacturer's data sheet for speeRle pinouts.

FIGURE 5. Typical4Y...Diglt Display Application

4·32

Functional Description

(Continued)
DISPLAY

BACKPLANE

v+

TL/F/6137-7

'The minimum recommended value for R for the oscillator input is 9 kil. An RC time constant of approximately
4.91

x .10-4 should produce a backplane frequency between 30

Hz and 150 Hz.

FIGURE 6. Parallel Backplane Outputs
DISPLAY

BACKPLANE

BP

BP

BP

BP

OUT

OUT

OUT

OUT

2 X BACKPLANE
DRIVE FREQUENCY

TL/F/6137-B

FIGURE 7. External Backplane Clock
Figure 8 shows a four wire remote display that takes advantage of the device's serial input to move many bits of display
information on a few wires.

Figure 9 is a general block diagram that shows how the
device's serial input can be used to advantage in an analog
display. The analog voltage input is compared with a staircase voltage generated by a counter and a digital-to-analog
converter or resistor array. The result of this comparison is
clocked into the MM5452, MM5453. The next clock pulse
increments the staircase and clocks the new data in.

USING AN EXTERNAL CLOCK
The MM5452/MM5453 LCD Drivers can be used with an
externally supplied clock, provided it has a duty cycle of
50%. Deviations from a 50% duty cycle result in an offset
voltage on the LCD. In Figure 7, a flip-flop is used to assure
a 50% duty cycle. The oscillator input is grounded to prevent oscillation and reduce current consumptions in the
chips. The oscillator is not used.

With a buffer amplifier, the same staircase waveform can be
used for many displays. The digital-to-analog converter
need not be linear; logarithmic or other non-linear functions
can be displayed by using weighted resistors or special
DACs. This system can be used for status indicators, spectrum analyzers, audio level and power meters, tuning indicators, and other applications.

Using an external clock allows synchronizing the display
drive with AC power, internal clocks, or DVM integration
time to reduce interference from the display.
4-33

Functional Description (Continued)

v+---t'----..,
DATA

---+-+--+1
IYPASS

CLOCK

---+-+--+1

CAPACITOR

v----+ooooo!l-----'
TL/F/6137-9

FIGURE 8. Four Wire Remote Display
LCD BAR GRAPH DIIPI.AY

AULaa VOL TAlE IN

11111000000

caUNT
CLOCK

DATA III

I

I

"START
liT

TLlF/6137-10

Da1a is high until s1aircase > Input

FIGURE 9. Ans,og Display

4-34

r-------------------------------------------------------------,~

~

~National

i

~ Semiconductor

MM5480 LED Display Driver
General Description
The MM5480 is a monolithic MOS integrated circuit utilizing
N-channel metal gate low threshold, enhancement mode
and ion-implanted depletion mode devices. It utilizes the
MM5451 die packaged in a 28-pin package making it ideal
for a 3% digit display. The MM5480 is designed to drive
common anode-separate cathode LED displays. A single
pin controls the LED display brightness by setting a reference current through a variable resistor connected either to
Voo or to a separate supply of 11V maximum.

Features
• Continuous brightness control
• Serial data input

•
•
•
•
•

No load signal required
Wide power supply operation
TIL compatibility
Alphanumeric capability
3% digit displays

Applications
•
•
•
•
•

COPSTM microcontrollers or microprocessor displays
Industrial control indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts

Block Diagram
OUTPUT 23

OUTPUT 1

~~~sr-'-~~~----~
CONTROL

TL/F/6138-1

FIGURE 1

Connection Diagram
Dual-In-Llne Package

Vss

OUTPUT BIT 12

OUTPUT BIT 11

OUTPUT BIT 13

OUTPUT BIT 10
OUTPUT BIT 9

OUTPUT BIT 14
OUTPUT BIT 15

4

OUTPUT BIT 8

OUTPUT BIT 16

OUTPUT BIT 7

OUTPUT BIT 17

OUTPUT BIT 6

OUTPUT BIT 18

OUTPUT BIT 5

8

OUTPUT BIT 19

OUTPUT BIT"

9

OUTPUT BIT 20

OUTPUT BIT 3

Order Number MM5480N
See NS Package Number N28B

OUTPUT BIT 21

OUTPUT BIT 2

OUTPUT BIT 22

OUTPUT BIT 1

17

OUTPUT BIT 23

BRIGHT. CONT.

13

16

DATA IN

Voo

14

15

CLOCK
TLlF/6138-2

Top View
FIGURE 2

4-35

Absolute Maximum Ratings
If Military/Aeroepace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcetlons.
Voltage at Any Pin
Vss - 0.3VtoVss + 12V
Storage Temperature
-65°C to + 1500C

Power Dissipation at 25°C
2.4W·
Molded DIP Package, Board Mount
2.1W··
Molded DIP Package, Socket Mount
1500C
Junction Temperature
, 300°C
Lead Temperature (Soldering, 10 sec.)
'Molded DIP Package. Board Mount, 8JA ~ 5Z'C/W. Derate 19.2 mW/'C
above 25"C.
"Molded DIP Package. Sockel Mount. 8JA ~ 5S·C/W. Derate 17.2 mW/'C
above 25'C.

Electrical Characteristics
TA

= -25°C to + 85°C, Voo = 4.75V to 11.0V, VSS = OV unless otherwise specified

Symbol

Parameter

Voo

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL

Input Voltage
Logical "0" Level

± 10 p.A Input Bias

VIH

Input Voltage
Logical "1" Level

4.75V';;; Voo';;; 5.25V
Voo> 5.25V

Brightness Input Current
(Note 2)

IOH

Output Sink Current (Note 3)
Segment OFF

VOUT

IOL

Output Sink Current (Note 3)
Segment ON

VOUT = 1V
Brightness Input
Brightness Input
Brightness Input

,.

Brightness Input Voltage
(Pin 13)

OM

Output Matching (Note 1)

Max

= 0 /LA
= 100 /LA
= 750 /LA

V

7

mA

-0.3

0.8

V

2.2

Voo

V

Voo -2

Voo

V

0

0.75

mA

10.0

/LA

10.0
4.0
25.0

/LA
mA
mA

4.3

V

±20

%

0
2.0
15.0

= 750 /LA

-25°C to

Conditions
(Notes 5 and 6)

2.7

3.0

+ 85°C, Voo =

Parameter

Units

11

= 3.0V

Input Current

AC Electrical Characteristics TA =
Symbol

Typ

4.75

IBR

VIBR

Min

Conditions

5V ±0.5V

Min
DC

Typ

Max

Units

500

kHz

fc

Clock Input Frequency

th

High Time

950

ns

tl

Low Time

950

ns

tos

Data Input Set-Up Time

300

ns

ns
Data Input Hold Time
300
tOH
Note 1: Output matching is calculated as the percent variation lrom (lMAX + IMINl/2.
Note 2: With a fixed resistor on the brightness Input pin some variation In brightness will occur from one device to another. Maximum brightness input current can
be 2 rnA as long as Note 3 and lunction temperature equation are complied with.
Note 3: Absolute maximum lor each output should be limited to 40 rnA.
Note' 4: 'The VOUT voltage should be regulated by the user.
Note 5: AC input waveform spec~lcatlon for test purpose: t,. ,; 20 ns, tr ,; 20 ns, I ~ 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and lall times must not exceed 300 ns.

4-36

Functional Description
There must be a complete set of 36 clocks or the shift registers will not clear.
When the chip first powers ON an internal power ON reset
signal is generated which resets all registers and all latches.
The START bit and the first clock return the chip to its normal operation.
F/fluflJ 5 shows the Output Data Format for the 5480. Because it uses only 23 of the possible 35 outputs, 12 of the
bits are 'Don't Cares'.
F/fluflJ 3 shows the timing relationships between data and
clock. A maximum clock frequency of 0.5 MHz is assumed.
For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.
Tj = (VOUT) (lLEO) (No. of segments) (6JAl + TA
where:
Ti = junction temperature, 150'C max.
VOUT = the voltage at the LED driver outputs
ILEO = the LED current
6JA = thermal coefficient of the package
TA = ambient temperature
6JA (Socket Mount) = 58°C/W
6JA(Board Mount) = 52°C/W

The MM5480 is specifically designed to operate 31f2-digit
alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an
additional load Signal. The 35 data bits are latched after the
36th bit is complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the serial data
bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A
0.001 p.F ceramic or mica disc capaCitor should be connected to brightness control, pin 13, to prevent possible oscillations.
A block diagram is shown in FiguflJ 1. The output current is
typically 20 times greater than the current Into pin 13, which
is set by an external variable resistor. There is an internal
limiting resistor of 4000 nominal value.
FiguflJ 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the 36th clock a LOAD
signal is generated synchronously with the high state of the
clock, which loads the 35 bits of the shift registers into the
latches. At the low state of the clock a RESET signal is
generated which clears all the shift registers for the next set
of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift
register, thus allowing continuous operation.

TL/F/6136-3

FIGURE 3

lJlJLrL

ClOCK

DATA _ _J

;~

____

=-- . .____n. . - - - -

•

J~._~~-.

LOAD
(INTERNAL) ---------------~!ll~-----'

1._ _ __

n

RESET
(INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~Ss__________J

LTL/F/6136-4

FIGURE 4_ Input Data Format

FIGURE 5. Output Data Format

4-37

Functional Description (Continued)
7V

RAW DC
>9V

lk~

240Jl

119 ~ b.V
lk

_

FIGURE 6. Typical Application of Constant Current Brightness Control

TLlF/6138-5

_ TL/F/6136-6

FIGURE 7. Brightness Control Varying the Duty Cycle

,, 123
Basic 3YrDigit Interface

Safe Operating Area
~~--~--~--~==~~,
~

2.0 I--R-~N...-T-'-""'-"i="="l

z

~

1.5

m 1.0

i

M

I--R'~~~~~--I

I--R-~~~~~~--l

1

23

OL-~~~~~~~~~

o

:Ill

C)
TL/F/6136-7

11

CLOCK

DATA

TL/F/6138-6

4-38

~National

~ Semiconductor

MM5481 LED Display Driver
General Description
The 5481 is a monolithic MOS integrated circuit utilizing Nchannel metal gate low threshold, enhancement mode and
ion-implanted depletion mode devices. It utilizes the
MM5450 die packaged in a 20-pin package making it ideal
for a 2 digit display. The MM5481 is designed to drive common anode-separate cathode LED displays. A single pin
controls the LED display brightness by setting a reference
current through a variable resistor connected either to Voo
or to a separate supply of 11V maximum.

Features
• Continuous brightness control
• Serial data input

•
•
•
•
•
•

No load signal required
Data enable
Wide power supply operation
TTL compatibility
Alphanumeric capability
2 digit LED driver

Applications
•
•
•
•

cOPS or microprocessor displays
Industrial control indicator
Relay driver
Instrumentation readouts

Block and Connection Diagrams
Voo

OUTPUT 14

OUTPUT 1

BRIGHTNESS
CONTROL

TL/F/6139-1

FIGURE 1
Dual-In-Line Package
OUTPUT BIT 8

20

OUTPUT BIT 9

OUTPUT BIT 7

19

OUTPUT BIT 10

OUTPUT BIT 6

18

OUTPUT BIT 11

OUTPUT BIT 5

17

OUTPUT BIT 12

OUTPUT BIT 4

16

OUTPUT BIT 13

15

Vss
OUTPUT BIT 14

OUTPUT BIT 3

6

OUTPUT BIT 2

7

OUTPUT BIT 1

8

11115481

14

BRIGHT CONT.
VDD

10

13

DATA ENABLE

12

DATA IN

11

CLOCK
TLlF/6139-2

Top View
FIGURE 2
Order Number MM5481N
See NS Package Number N20A
4-39

Absolute Maximum Ratings
+15O"C
Junction Temperature
Lead Temperature (Soldering, 10 sec.)
300"C
'Molded DIP Package, Boerd Mount,'JA = 61'C/W, Derate 16.4 mWI'C
above2S'C.
"Molded DIP Package, Socket Mount, 'JA = 67'C1W, Derate 14.9mWI'C
above 25'C.

If Military/Aerospace specified devices are required,
pleaee contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Vss to VSS + 12V
Storage Temperature
- 65'C to + 150'C
Power Dissipation at 25'C
Molded DIP Package, Board Mount
2W'
1.8W··
Molded DIP Package, Socket Mount

Electrical Characteristics
TA = -25'C to + 85°C, VDO = 4.75V to 11.0V, VSS = OV unless otherwise specified
Symbol

Parameter

Conditions

VOO

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL

Input Voltages
Logical "0" Level

± 10".A Input Bias

Logical "1" Level

4.75 s; Voo s; 5.25

VIH

Brightness Input Current
(Note 2)

IOH

Output Sink Current
(Note 3)
Segment OFF

IOL

Segment ON

VISA

Brightness Input Voltage
(Pin 9)

OM

Output Malching (Note 1)

Max

4.75

-0.3

Voo> 5.25
ISR

Typ

Min

11

V

7

rnA

0.8

V

2.2

Voo

V

Voo - 2

Voo

V

0

0.75

rnA

10.0

".A

10.0
4.0
25.0

mA
rnA

4.3

V

±20

%

VOUT = 3.0V
VOUT= 1V(Note4)
Brightness Input = 0 ".A
Brightness Input = 100 ".A
Brightness Input = 750 ".A

0
2.0
15.0

Inpul Currenl = 750 ".A

3.0

AC Electrical Characteristics TA =

Unlta

2.7

".A

-25'Cto + 85'C, Voo = 5V ± 0.5V

Parameter

Conditions

Min

1c

Clock Input Frequency

(Notes 5 and 6)

DC

Ih

High Time

950

ns

II

Low Time

950

ns

tos
IOH

Data Input
Set-UpTime
Hold Time

300
300

ns
ns

Symbol

,

Typ

Max

Unlta

500

kHz

Data Enable Input
100
Set-UpTime
ns
Nola 1: Output matching is calculated asths percent variation lrom IMAX + IMIN/2.
Nole 2: With a fixed resistor on the brighlnesslnput pin some variation in brightness will occur from one device to another. Maximum brighlnesslnput curnsnt can
be 2 mA as long as Note 3 and lunction temperature equation are compiled with.
Note 3: Absolute maximum lor each output should be IimHed 10 40 mAo
Note 4: Ths VOUT voltage should be regulated by the user.
Note 5: AC input waveform specification lor test purpose: t,. ,;; 20 ns, tf ,;; 20 ns, I = 500 kHz, 50% ± 10% duty cycle.
Note 8: Clock Input rise and fall times must not exceed 300 ns.
tOES

4-40

Functional Description

Data Enable

The MM5481 uses the MM5450 die which is packaged to
operate 2-digit alphanumeric displays with minimal interference to the display and the data source. Serial data transfer
from the data source to the display driver is accomplished
with 2 signals, serial data and clock. Using a format of a
leading "1" followed by the 35 data bits allows data transfer
without an additional load signal. The 35 data bits are
latched after the 36th bit is complete, thus providing nonmultiplexed, direct drive to the display. Outputs change only
if the serial data bits differ from the previous time. Display
brightness is determined by control of the output current for
LED displays. A 0.001 JIoF capacitor should be connected to
brightness control, pin 9, to prevent possible oscillations.

This active low signal enables the data input pin. If high, the
shift register sees zeroes clocked in.

A block diagram is shown in Figure 1. The output current is
typically 20 times greater than the current into pin 9, which
is set by an external variable resistor. There is an internal
limiting resistor of 400.0 nominal value.

For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations.

Figuf9 4 shows the input data format. A start bit of logical
"1" precedes the 35 bits of data. At the posJtive-going-edge
of the 36th clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35 bits of
the shift registers into the latches. At the low state of the
clock a RESET signal is generated which clears aU the shift
registers for the next set of data. The shift registers are a
static master-slave configuration. There is no clear for the
master portion of the first shift register, thus allowing continous operation.

Tj = (VOUT) (lLEO) (No. of segments) (6JA)

To blank the display at any time, (i.e., power on), clock in 36
or more zeroes, followed by a 'one' (start bit), followed by
36 or more zeroes.

Figure 5 shows the Output Data Format for the MM5481.
Because it uses only 14 of the possible 34 outputs, 20 of the
bits are 'Don't Cares'. Note that only alternate groups of 4
outputs are used.

Figuf9 3· shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5 MHz is assumed.

+ TA

where:
Tj = junction temperature, 150°C max.
VOUT = the voltage at the LED driver outputs

ILEO = the LED current
6JA = thermal coefficient of the package
TA = ambient temperature
6JA (Socket Mount) = 67"C/W
6JA (Board Mount) = 61°C/W

There must be a complete set of 36 clocks (high/low edges)
or the shift registers will not clear.

r-!!!!!!!!!!\----90%
" -_ _~-----'!~--10%

DATA ENABLE

TUF/6139-3

FIGURE 3. Timing

=--_. n - - - .-

CLOCK

DATA

.-~~-.

--...I

---- ..

LOAD
(INTERNAL) ----------------US$-~--....J
RESET
(INTERNAL)

. .___

---------!.S~
FIGURE 4. Input Data Format

4-41

TL/F/6139-4

.- r---------------------------------------------------------------------------------,

!:IE

Functional Description (Contifluec:,l)

:IE
FIGURE 5. Output Data Format
7V

RAW DC
>9V

TUF/6139-5

FIGURE 6. Typical Application of Constant Current Brightness Control
5V

TL/F/6139-6

FIGURE 7. Brightness Contr~1 Varying the Duty Cycle
Safe Operating Area
2.5

Basic Electronically Tuned Television System

14 SEGt.lENTS
VOUT=1V
38 mA/SEGt.lENT

g

2.0 f--+-:-+--

i!l
~

1.5

m

ln~-~~~~~~~-4

12

f---~~~NI----I----1

i0.5I---4~~~~~~--j

• • • • • •
14

o~~~~~~~~~~

o

20

40

60

8D

LED DISPLAY

t.lt.I5481
DISPLAY
DRIVER

100

TEt.lPERATURE (OC)
TUF/6139-7

111
KEYBOARD

+--7,

PROCESSOR
(COPS. ETC.)
TL/F/6139-6

+.42

~National

~ semiconductor

MM5483 Liquid Crystal Display Driver
•
•
•
•
•

General Description
The MM5483 is a monolithic integrated circuit utilizing
CMOS metal-gate low-threshold enhancement mode devices. It is available in a 40-pin molded package. The chip can
drive up to 31 segments of LCD and can be cascaded to
increase this number. This chip is capable of driving a 4'/zdigit 7-segment display with minimal interlace between the
display and the data source.
The MM5483 stores the display data in latches after it is
latched in, and holds the data until another load pulse is
received

Wide power supply operation
TTL compatibility
31 segment outputs
Alphanumeric and bar graph capability
Cascade capability

Applications
•
•
•
•
•

Features

COPSTM or microprocessor displays
Industrial control indicator
Digital clock, thermometer. counter, voltmeter
Instrumentation readouts
Remote displays

• Serial data input
• Serial data output

Block and Connection Diagrams
Dual-In-Line Package
OUTPUT 1

OUTPIIT3I

OUTPUT 81T 17

OUTPUT BIT 1.

OUTPUT BIT 15
OUTPUT BIT 1.

OUTPUT BIT 19
OUTPUT BIT 20

OUTPUT BIT 21

OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11

S£lIIAL-+--1>--{~~

OUTPUT 81T 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26

OUTPUT liT l'

OATA~

CLOCK

1IlIs
OUTPUT BIT 18

OUTPUT BIT 9
OUTPUT BIT'
DllTPUTBIT 7

_....!:.f-----C>------..;r

10

IM5483

OUTPUT BIT 27

OUTPUT BIT.
'::"

TL/F/6140-1

~

~

~

'"
~

'~"

~

~

g

~

g >~~z

OUTPUT BIT 2

..::: .. .. ... ..
~

'Q'

~

~~~

OUTPUT BIT 1

N

urAOUT
OSCIN

~ g~

"0

0

OUTPUT BIT 22
38

OUTPUT BIT 23

OUTPUT BIT 10

37

OUTPUT BIT 24

OUTPUT BIT 9

36

OUTPUT BIT 25

OUTPUT BIT 8

35

OUTPUT BIT 26

34

OUTPUT BIT 27

OUTPUT BIT 7

12

OUTPUT BIT 6

13

33

OUTPUT BIT 28

OUTPUT BIT 5

14

32

OUTPUT BIT 29

OUTPUT BIT 4

15

31

OUTPUT BIT 30

OUTPUT BIT 3

16

30

OUTPUT BIT 31

N/e

OUTPUT BIT 2

.- g
~

~

!!O

u

:g

ou !!O !!O

:1' .....
z

"~ ~
u

DATA IN
CLOCK IN

Top View

OUTPUT BIT 11

MM5483

..

OIlTPUT BIT 31
LOAD
BACKPLANE IN
BAC...... OUT

TLlF/6140-2

0

OUTPUT BIT 12

~
z

OUTPUT BIT ..
DllTPUTBIT 3

f'IGURE 1
:!

OUTPUT BIT 28
OUTPUT liT 29
OUTPUT BIT 30

OUTPUT BIT I

g !!Ow 9
w z
0

gg
:l

~
Order Number MM5483V
See NS Package Number V44A

TL/F/6140-7

4·43

FIGURE 2

Order Number MM5483N
See NS Package Number N40A

Absolute Maximum Ratings
If Military/Aerospace specified deVices ant requlnid,
please contact the Natlolllli Semiconductor Sa...
Office/Distributors for avallabHRy and iijMclficatlona.
Voltage at Any Pin
Vss to Vss + 10V
Operating Temperature
-40"Cto +8S"C
Storage Temperature
-65"Cto +15O"C

Power Dissipation

300 mWat + 85"C
350 mWat + 2SoC
+15O"C

Junction Temperature
Lead Temperature
(Soldering, 10 seconds)

300"C

DC Electrical Characteristics
TA within operating range, Voo

= 3.0V to 10V, Vss = av, unless otherwise specified

Parameter

Condmon.

Min

Power Supply

Typ

Max

Units

10

V

17
3S

1S
2S
4S

I£A.
I£A.
I£A.

1.S

2.S

I£A.

0.9

3.0
R = 1M,C = 470pF,
Outputs Open
Voo = 3.0V
Voo = S.OV
Voo = 10.0V
OSC = OV, Outputs Open,
BPIN = 32 Hz, Voo = 3.0V

Power Supply Current

9

Input Voltage Levels
Logic "0"
Logic "1"
Logic "0"
Logic "1"

Load, Clock, Data
VOO = 5.0V
VOO = S.OV
VOO = 3.0V
VOO = 3.0V

2.4
2.0

V
V
V
V

Output Current Levels
Segments and Data Out
Sink
Source

VOO = 3.0V, Vour '" 0.3V
Voo = 3.0V, Vour = 2.7V

20
20

I£A.

SPOUT
Sink
Source

Vob = 3.0V, Vour = 0.3V
Voo = 3.0V, Vour 2.7V

320
320

I£A.
I£A.

0.4

=

p.A

AC Electrical Characteristics Voo ~ 4.7V, Vss = OV unless otherwise specified
Symbol

Parameter

tc

Clock Frequency, Voo = 3V

teH

Clock Period High

tel

Clock Period Low

tos

I

Min
(Notes 1, 2)

Typ

Max

Units

SOO

kHz

500

ns

500

ns

Data Set-Up before Clock

300

ns

tOH

Data Hold Time after Clock

100

ns

tlW

Minimum Load Pulse Width

SOO

ns

tLTC

Load to Clock

400

teoo

Clock to Data Valid

I

Note 1: AC Input waveform specificatiOn lor _ purpoaa:" " 20 n.. 1i
Note 2: Clock input rise and fall times must not exceed 300 na.
Note 3: Output offset voltage is

ns

400

7S0

ns

" 20 n.. I = 500 kHz. 50% ± 10% duty cycle.

±50 mV with CseGMENT = 250 pF. CaP = 8750 pF.

Functional Description
A block diagram for the MMS483 i8 shown in FIgUrfI1 and a
package pinout is shown in F/{J/JITiI 2. Figure 3 shows a po&sible 3-wire connection system with a typical signal format
for Rgure 3. Shown in FigurB 4, the load Input Is an asynchronous input and lets data through from the shift registEir
to the output buffers any time it is high. The load input can
be connected to Voo for 2-wlre control as shown In Figure
5. In the 2-wire control mode, 31 bits (or less depending on

the number of segments used) of data are clocked into the
MMS483 in a short time frame (with less than 0.1 second
there probably will be no noticeable flicker) with no more
clocks until new information is to be displayed. If data was
slowly clocked in, it can be seen to "walk" across the display in the 2-wire mode. An AC timing diagram can be seen
in F/{JUrB 6. It should be noted that data out is not a TTLcompatible output.

~----------------------------------------------------------------,~

Functional Description

~

(Continued)

E
w

DATA

CLOCK ----<1----11----.....
L O A D _ - - - - - _....._ _ _ _ _ _.... __ _
TLlF/6140-3

FIGURE 3. Three-Wire Control Mode

1= I
~AD

I

I

I

I

I

I

_______________~~--------~rL

II

.

TIME-

TL/F/6140-4

FIGURE 4. Data Format Diagram

aOK

DATA OUT
LOAD

_

25

VUD

DATA

CLOCK - - -......~------_... - - - - - - _

TL/F/6140-5

FIGURE 5. Two-Wire Control Mode

TL/F/6140-6

FIGURE 6. Timing Diagram
4-45

~ r-----------------------------------------------------------~--------------_,

~

:& ~ National
::E

~ Semiconductor

MM5484 16-Segment LED Display Driver
•
•
•
•
•

General Description
The MM5484 is a low threshold N-channel metal gate circuit
using low threshold enhancement and ion implanted depletion devices. The MM5484 is available in a 22-pin molded
package and is capable of driving 16 LED segments. The
MM5484 is designed to drive common anode separate cathode LED displays.

MM5484 is cascadeable
TTL compatibility
No load signal required
Non multiplex display
2% digit capability-MM5484

Applications
•
•
•
•

Features
• Serial data input
• Wide power supply operation
• 16 output, 15 mA sink capability

COPSTM or microprocessor displays
Instrumentation readouts
Industrial control indicator
Relay driver

Block and Connection Diagrams
16 SEGMENT OUTPUTS

ENABLE 0-....- - - 4

DATA
OUT

CLOCK...--......._
DATA IN 0 - - - - - - - - 1

TL/F/6141-1

FIGURE 1. MM5484

Dual-In-Line Package
22

013

PLCC

'"

Q

012
011

014

21

015

20

010

016

19

09

DATA OUT

1B

ENABLE

VOD

17

CLOCK IN

DATA IN

16

VBs

Q

... -c
Q

(.)

......
z

016

010
Nlc

09

DATA OUT

MM5484V

VDD

01

15

08

DATA IN

14

07

01

03

13

06

02

12

05

11

..,

NIC

02

D4

<.>
......
z Q""'

TUF/6141-3

Top View

ENABLE

21

CLOCK IN

19

08

Vss

(.)

......
Z

..,
Q

""'
Q

~ ~
z

...
Q

....
Q

TUF/6141-6

Order Number MM5484N
See NS Package Number N22A

Top View
Order Number MM5484V
See NS Package Number V28A

4-46

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at LED Outputs
Vss - 0.5VtoVss + 12V
Voltage at Other Pins

Vss - 0.5Vto Vss

Storage Temperature

-40"C to

Power Dissipation at 25·C
Molded DIP Package. board mount
Molded DIP Package. socket mount

+ 10V

2W'
1.8W··

'Molded DIP Package. board mount.
derate 15.8m W/·C above 25·C.

OJA

= 63·C/W.

"Molded DIP Package. socket mount.
derate 14.5m WI"C above 25·C.

OJA

= 69·C/W.

Lead Temperature (Soldering. 10 sec.)

DC Electrical Characteristics Voo = 4.5V to 9V. TA =
Parameter

Conditions

-40·C to

Min

Supply Voltage

Typ

Supply Current

5
2.4

Logic Zero
Input Low Level V,L
Input Current
Input Capacitance

300·C

+ 85·C unless otherwise specified
Max

4.5

Logic One
Input High Level V,H

+ 85·C
+ 150·C

- 40·C to

Operating Temperature

V

10

mA

Voo

+ 0.5

0.8
±1
7.5

0
High or Low Level

Units

9

V
V

pA
pF

OUTPUTS
Data Output Voltage
High Level VOH
Low Level VOL
Segment Off
(Logic Zero on Input)

lOUT = 0.1 mA
lOUT = -0.1 mA
VOUT = 12V
AEXT = 400n

Output Current Segment On
(Logic One on Input)
Output Voltage

lOUT = 15mA
Voo ~ 6V

0.5
50

V
V
",A

1.0

V

Voo - 0.5

0.5

AC Electrical Characteristics
(See Figure 3.) Voo

Symbol

=

4.5V to 9V. TA

= -

Parameter

40"C to

+ 85·C unless otherwise specified
Conditions

Min

fc

Clock Frequency

th

High Time

0.95

t,

Low Time

0.95

tS1

Data Setup Time

0.5

tH1

Data Hold Time

0.5

tS2

Enable Setup Time

0.5

tH2

Enable Hold Time

0.5

tpd

Data Out Delay

Typ

Max

Units

0.5

MHz

0.5

Note 1: Under no condition should the power dissipated by the segment driver exceed 50 mW nor the entire chip power dissipation exceed 500 mW.
Note 2: AC input waveform specification lor test purpose: t, ,;: 20 ns, It ,;: 20 ns, I ~ SOO kHz, 50% ± 10% duty cycle.
Not. 3: Clock input rise and lall times must not exceed 500 ns.

4·47

"'S
"'S
"'S
"'S
"'S
"'S
"'S

Functional Description
The MM5484 is designed to drive LED displays directly. Se·
rial data transfer from the data source to the display driver ill
accomplished with 3 signals, DATA IN, CLOCK and EN·
ABLE. The signal ENABLE acts as an envelope and only
while this signal is at a logic '1' do the circuits recognize the
clock signal.
While ENABLE is high, data on the serial data input is transferred and shifted In the Internal shift register on the rising
clock edge, i.e. a logic '0' to logic '1' transition.

When the ENABLE signal goes to a low (logiC zero state),
the contents of the shift register Is latched and the display
will show the new data. While new data Is being loaded intO
the SR the display will continue to show the old data.
For the MM5484, data is output from the serial DATA OUT
pin on the failing edge of clock so cascading Is made simple
with race hazards eliminated.
When the chip first powers on, an Internal power on reset
signal is generated which resets the SR and latches to zero .
so that the display will be off.

Timing Diagram

CLOCK

EHABLE-----

DATA IN

-----..1

-I r.-_Ipd_ _~

l

DATA D U T - - - - - - - - - -..........

FIGURE 3

4-48

\ . .------

TLlF/8141-5

~National

~ Semiconductor

MM5486 LED Display Driver
General Description
The MM5486 is a monolithic MOS integrated circuit utilizing
N-channel metal-gate low-threshold, enhancement mode
and ion-implanted depletion mode devices. It is available in
a 40-pin molded dual-in-line package. The MM5486 is designed to drive common anode-separate cathode LED displays. A single pin controls the LED display brightness by
setting a reference current through a variable resistor connected to Voo.

Features
• Continuous brightness control
• Serial data input! outut

•
•
•
•
•
•

External load input
Cascaded operation capability
Wide power supply operation
TIL compatibility
33 outputs, 15 lilA sink capability
Alphanumeric capability

Applications
•
•
•
•
•

COPSTM or microprocessor displays
Industrial controj indicator
Relay driver
Digital clock, thermometer, counter, voltmeter
Instrumentation readouts

Block and Connection Diagrams
Dual-In-Llne Package

vas

11 DATA OUT

":"

TLlF/6142-1

FIGURE 1

.

~

::!

Iii

~

is
6

5

.4

~

'Q

~

~
;~

3

2

~

~

0

N

N

Iii Iii Iii Iii Iii

~~~~~

OUTI'IIT liT 11
ouiiouT lIT IS
OUTI'IIT lIT 14
OUTPUT lIT 13
OUTI'IIT lIT 12
OUTPUT lIT 11
OUTI'IIT lIT 10
OUTPUT lIT.
OUTPUT lIT,
OUTPUT lIT 7
OUTPUT lIT I
OUTPUT lIT I
OUTPUT'IT 4
OUTPUT lIT a
OUTPUT lIT 2
OUTPUT lIT 1
UTA OUT
IlUBHTNEI8 CONTROL
¥IJII

OUTl'UT lIT 17
OUTPUT lIT II
OUTPUT lIT 19
OUTPUT lIT 20
OUTPUT liT 21
OUTPUT lIT 22
OUTPUT lIT 23
OUTPUT lIT 24
OUTPUT lIT 25
OutPUT lIT 21
OUTPUT lIT 27
OUTPUT liT 21
OUTPUT lIT 21
OUTPUT liT ao
OUTPUT lIT 11
OUTl'UT BIT 32
OUTPUT BIT 33

MM54111

LOAD

19
20

22
21

DATA IN
CLOCI( IN
TL/F/6142-2

1 .44 43 42 41 .40

Top View

OUTPUT BIT 12

39

OUTPUT BIT 11

3.

OUTPUT BIT 23

Order Number MM5486N

OUTPUT BIT 10

37
36
35
34
33
32
31
30
29

OUTPUT BIT 24

See NS Package Number N40A

OUTPUT BIT 9

I.

OUTPUT BIT 8

11

N/C

12
13

OUTPUT BIT 7
OUTPUT BIT 6

,.

OUTPUT BIT 4-

,.

OUTPUT BIT 3

17

OUTPUT BIT 5

MM5486V

15

§

~I
~~

Iii Iii

!!l

~

"
>8 ;;:

;!;

;!;

S~

~

~
~

OUTPUT BIT 22

OUTPUT BIT 25

FIGURE 2

OUTPUT BIT 26

N/c
OUTPUT BIT 27
OUTPUT BIT 28

OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31

N
~

Iii Iii

i

!o
~

is

8i
TL/F/6142-13

Order Number MM5486V
See NS Package Number V44A

4-49

Absolute Maximum Ratings
Power Dissipation at 2SoC
2.SW·
Molded DIP Package, Board Mount
2.3W··
Molded DIP Package, Socket Mount
Junction Temperature
.
+1SO"C
Lead Temperature (Soldering, 10 seconds)
300"C
'Molded DIP Package, Board Mount, 8JA = 4'i1'C/W, Derate 20.4 mWI'C
above 25'C.
"Molded DIP Package, Socket Mount, 8JA = 54'C/W, Derate 18.5 mWrC
above 25'C.

It Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Vss to Vss + 12V
- 2SoC to + 8SoC
Operating Temperature
Storage Temperature
- 6SOC to + 1SO"C

Electrical Characteristics
= 4.7SV to 11.0V, Vss = OV, unless otherwise specified

TA within operating range, VDO
Symbol

Parameter

Conditions

Voo

Power Supply

100

Power Supply Current

Excluding Output Loads

VIL
VIH

Input Voltages
Logic "0" Level
Logic "1" Level

± 10 /J-A Input Bias
4.7S ,;;; Voo ,;;; S.2S

ISA

Brightness Input (Note 2)

10H
10L

Output Sink Current (Note 3)
Segment OFF
Segment ON

Voo> S.2S

10

Maximum Segment Current

VISA

Brightness Input Voltage (Pin 19)

OM

Output Matching (Note 1)

VOL
VOH

Data Output
Logical "0" Level
Logical "1" Level

fc
th
tl

Clock Input
Frequency
High Time
Low Time

Min

Typ

4.7S

VOUT = 3.0V
VOUT = 1V(Note4)
Brightness Input = 0 !J.A
Brightness Input = 100/J-A
Brightness Input = 7S0 /J-A

Input Current

lOUT
lOUT

= 7S0 /J-A

= O.SmA
= 100 !J.A

-0.3
2.2

Max

Unite

11

V

7

mA

0.8
Voo

V
V

Voo-2

Voo

V

0

0.7S

mA

10

/J- A

10
4
2S

rnA
rnA

40

mA

0
2.0
1S

3.0

Vss
2.4

2.7

/J- A

4.3

V

±20

%

0.4
Voo

V
V

SOO

kHz
ns
ns

(Notes Sand 6)
9S0
9S0

Data Input
Set-UpTime
300
ns
tos
Hold Time
300
ns
tOH
Note 1: Output matching is calculated as the percent variation (IMAX + IMIN)/2.
Note 2: With a fixed resistor on the brightness input pin, some variation In brightness will occur Irqrn one device to another. Maximum brightness input current can
be 2 mA as long as Note 3 and Junction temperature equation are compiled with.
Note 3: Absolute maximum lor each output should be limHed to 40 mAo
Note 4: The VOUT voltege should be regulated by the user. See FIgures 6 and 7 lor allowable VOUT vs lOUT operation.
Note 5: AC input wavelorm specification lor test purpose: t, s;; 20 ns, It s;; 20 ns, I = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock Input rise and lall timas must not exceed 300 ns.

4-S0

Functional Description
When the chip first powers ON, an internal power ON reset
signal is generated which resets all registers and latches.
The leading clock returns the chip to its normal operation.

The MM5486 is specifically designed to operate four-digit
alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data
source to the display driver is accomplished with 3 signals,
serial data, clock, and load. The data bits are latched by a
positive-level load signal, thus providing non-multiplexed, direct drive to the display. When load is high, the data in the
shift registers is displayed on the output drivers. Outputs
change only if the serial data bits differ from the previous
time. Display brightness is determined by control of the output current for LED displays. A 0.001 /kF capacitor should
be connected to brightness control, pin 19, to prevent possible oscillations. The output current is typically 20 times
greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of
4000 nominal value.

Figure 3 shows the timing relationship between data, clock
and data enable. A maximum clock frequency of 0.5 MHz is
assumed.
For applications where a lesser number of outputs are used,
it is possible to either increase the current per output, or
operate the part at higher than 1V VOUT. The following
equation can be used for calculations:
TJ = (VOUT) (lLEO)(No.ofsegments)(8JA>
where:

+ TA

TJ = junction temperature, 150'C max.
VOUT = the voltage at the LED driver outputs
ILEO = the LED current

A block diagram is shown in Figure 1.

8JA = thermal coefficient of the package

Figure 4 shows the input data format. Bit "1" is the first bit
into the data input pin and it will appear on pin 17. A logical
"1" at the input will turn on the appropriate LED. The load
Signal latches the 33 bits of the shift register into the latches. The data out pin allows for cascading the shift registers
for more than 33 output drivers.

T A = ambient temperature
OJA (Socket Mount) = 54'C/W
OJA (Board Mount) = 49'C/W
The above equation was used to plot Figure 6, Figure
Agure8.

7. and

TL/F/6142-3

FIGURE 3

LEADING
CLOCK' 1
CLOCK
BIT 1

LOAD

BIT 32

BIT 33

~~

RESETJl...._ _ _ _ _ _ _ _ _ _ _ _..,.,_ _ _ _ _ _ _ _ __
(INTERNAL)
TL/F/6142-4

'This leading clock is necesssry only aiter power ON.

FIGURE 4. Input Data Format

YoD
CLOCK
RESET _ _ _ _ _ _ _....
(INTERNAL)
TL/F/6142-5

FIGURES

4-51

Typical Applications
11 0

g2.0

i

11J
I ~r-~~~~~~
8

aa

,

~

8.5 f-++1I-++-t+-I-+.J-I-+-~

D

020«16080100
TEMPERATURE (OC)

4

81216202428

I---~
1\"\

"

20

0
0

O~~~~~~-L~

o~~~~~~~~~

:

o

5

~UT=2V

MAX 10UT~41111A
"
~

10

r--....
15

20

30

34

TUF/6142-B

TL/F/6142-7

FIGURES

FIGURE 7

_DC
>tv
lk

TLlF/6142-9

FIGURE 9. Constant Current Brightness Control

TLiF16142-10

FIGURE 10. Brightness Control Varying the Duty Cycle

4-52

25

NUMBER OF SEGMENTS

ILEU (mAl

TUF/6142-6

TA=U'C

~~.1.JV
I
I

I---~

I:

1.0

FIGURE 6

.- ..!
+- 1VQUT~1.OVI

100 I-90

Typical Applications (Continued)
Basic Electronically Tuned Radio System
LED DISPLAY
AM

Ie

JO

FM/O:::/L

PlL

KEYBOARD

SYNTHESIZER

STATION
DETECT. ETC.
TLlF/6142-11

Duplexlng 8 Digits with One MM5486

MIII4..

CLOC.,N ...._ _ _ _..1
OATAIN ....- - - - - - '

......WI\r-...-VOO

BRIGHTNESS
CONTROL

-------------....1

LOAO ....

TL/F/6142-12

'This driver has 7 segments only.

4-53

r--------------------------------------------------------------------------------,
:g ~National
~

~

== ~semiconductor
==
MM58201 Multiplexed LCD Driver
General Description

Features

The MM58201 is a monolithic CMOS LCD driver capable of
driving up to 8 backplanes and 24 segments. A 192-bit RAM
stores the data for the display. Serial input and output pins
are provided to interface with a controller. An RC oscillator
generates the timing necessary to refresh the display. The
magnitude of the driving waveforms can be adjusted with
the VTC input to optimize display contrast. Four additional
bits of RAM allow the user to program the number of backplanes being driven, and to designate the driver as either a
master or slave for cascading purposes. When two or more
drivers are cascaded, the master chip drives the backplane
lines, and the master and each slave chip drive 24 segment
lines. Synchronizing the cascaded drivers is accomplished
by tying the RC OSC pins together and the BP1 pins together.

• Drives up to 8 backplanes and 24 segment lines
• Stores data for display
• Cascadable
• Low power
• Fully static operation

Applications
• Dot matrix LCD driver
• Multiplexed 7-segment LCD driver
• Serial in/Serial out memory

The MM58201 is packaged in a 40-lead dual-in-line package, or 44 lead plastic chip carrier package.

Block Diagram
IACICPlANES

He

SEGMENT

COLUMN ...._ _ _•

CONTROL LOlle

TL/F/6146-1

FIGURE 1

4-54

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Power Dissipation at 25'C
Molded DIP Package, board mount
Molded DIP Package, socket mount

Voltage at Any Pin

·Molded DIP Package, board mount,
derate 23.3m W/'C above 25'C

9JA = 43'C/W,

··Molded DIP Package, socket mount,
derate 21.3m WI'C above 25'C

9JA = 47'C/W,

Vss -0.3VtoVss +18V

Operating Temperature Range
Storage Temperature Range

O'Ct070'C
- 65'C to + 150'C

Operating Voo Range

2.9W·
2.6W··

Vss +7.0VtoVss + 18.0V

Lead Temperature (Soldering,
10 seconds)

300'C

DC Electrical Characteristics MinImax limits apply across temperature range unless otherwise noted.
Symbol

Parameter

Conditions

Icc

Quiescent Supply Current

VIN(1)

Logical "1" Input Voltage

VIN(O)

Logical "0" Input Voltage

VOUT(O)

Logical "0" Output Voltage

ISINK = 0.6 mA

IOUT(1)

Logical "1" Output Leakage
Current

VOUT = Voo

IIN(1)

Logical "1" Input Leakage
Current

VIN = Voo

IIN(O)

Logical "0" Input Leakage
Current

VIN = Vss

VTC
VTC
ZOUT

Output Impedance

Backplane and Segment
Outputs

ZOUT

DC Offset Voltage

Between Any Backplane
and Segment Output

Min

Typ

0.45 Voo

Max

Units

0.3

mA

Voo +0.3

V

1.0

V

0.4

V

0

±10

/LA

0

1.0

/LA

-1.0

0

/LA

Input Voltage

4.5

Voo+0.3

V

Input Impedance

10

30

kO

10

kO

±10

mV

Max

Units

Vss-0.3

0

AC Electrical Characteristics TA and Voo within operating range unless otherwise noted.
Symbol

Parameter

Conditions

Min

Typ

fosc

Oscillator Frequency·

128'1'/

400'1'/

Hz

fClK IN

Clock Frequency

DC

100

kHz

toN

Clock Pulse Width

5.0

/Ls

tOFF

Clock OFF Time

5.0

/Ls

ts

Input Data Set-Up Time

2.0

/Ls

tH

Input Data Hold Time

1.0

/Ls

tACC

Access Time

5.0

/Ls

tr

Rise Time

Backplane, Segment Outputs
Cl = 2000pF

60

/Ls

t,

Fall Time

Backplane, Segment Outputs
Cl = 2000pF

60

/Ls

• 1'J Is the number of backplanes programmed.

4-55

II

...

i
f8

::E
::E

Connection Diagrams
Pleetlc.Chip·Carrier

Dual-In-Une Package

Iii:l! III

SI1

o - ~ Iii N .., .... II)
C;;C;;z>U;U; ~ ~

liD

II
II
S7

56

III

II
II

117
III

S4
U

III

516

S5

38

517

S4

37

518
519

S3

10

36

S2

11

35

520

12

34

N/C
521

U
II

al
al

N/C
SI

13

33

IN
In

SU

BP8

14

32

522

a3

BP7

15

31

523

BP6

16

30

524

BPS

17

29

VTC

...

IN

WW58201V

IN

IP3

• i: •

In

IPI

.:!I~~ ~
~ ~

2!i

VII

iE iE

~ d

113

TL/F/6148-10
TL/F/8146-2

Top View

Top View
FIGURE 2
Order Number MM68201N or MM58201V
See NS Package Number N40A or V44A

Switching Time Waveforms
i----10N-----t
eLK IN

DATA IN.C!

DATA OUT

VALID

VALID

TL/F/8146-3

Backplane Output

Segment Output
Ir

.... VTC

~

0.32 VTC
TLlF/8146-5

TLlF/8146-4

4-56

Functional Description
TABLE I. Backplane Select

A functional diagram of the MM58201 LCD driver is shown
in Figure 1. Connection diagrams are shown in Figure 2.

Number of
Backplanes

SERIAL INPUTS AND OUTPUTS
A negative-going edge on the CS input initiates a frame. The
CS input must then stay low for at least one rising edge of
ClK IN, and may not be pulsed low again for the next 31
clocks. At least one clock must occur while CS is high. If
ClK IN is held at a logic "1", CS is disabled. This allows the
signal that drives CS to be used for other purposes when
the MM58201 is not being addressed.

2
3
4
5

6
7
8

ClK IN latches data from the DATA IN input on its rising
edge. Data from the DATA OUT pin changes on the falling
edge of ClK IN and is valid before the next rising edge.
The first five bits of data following CS are the address bits
(Figure 3). The address selects the column where the operation is to start. Bit 1 is the MSB and bit 5 is the lSB. The
sixth bit is the readlwrite bit. A logiC "1" specifies a read
operation and a logic "0" specifies a write operation. The
next 24 bits are the data bits. The first data bit corresponds
to the BP1 row of the display, the second data bit to the BP2
row, and so on. After the eighth and sixteenth data bits, the
column pOinter is incremented. When starting address
10110 or 10111 is specified, the column pOinter increments
from 10111 to 00000.
During a read or write cycle, the LCD segment outputs do
not reflect the data in the RAM. To avoid disrupting the
pattern viewed on the display, the read or write cycle time
should be kept short. Since the LCD turn-on time can be as
lillie as 30 ms, a clock rate of at least 10 kHz would be
required in order to address the entire contents of the RAM
within that time interval. The formula below can be used to
estimate the minimum clock rate:

f

B2

B1

BO

0
0
0
1
1
1
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

RC OSC Pin
This oscillator generates the timing required for multiplexing
the liquid crystal display. The oscillator operates at a frequency that is 4"l times the refresh rate of the display,
where "l is the number of backplanes programmed. Since
the refresh rate should be in the range from 32 Hz to 100
Hz, the oscillator frequency must be:
128"l ,,;; fosc ,,;; 400"l
The frequency of oscillation is related to the external Rand
C components in the following way:
1
fosc = 1.25 RC ± 30%

The value used for the external resistor should be in the
range from 10 kO to 1 MO.
The value used for the external capacitor should be less
than 0.005 ,...F.
VTCPln
The VTC pin Is an analog input that controls the contrast of
the segments on the LCD. If eight backplanes are being
driven ("l = 8), a voltage of typically 8V is required at 25°C.
The voltage for optimum contrast will vary from display to
display. It also has a significant negative temperature coefficient.
The voltage source on the VTC input must be of relatively
low impedance since the input impedance of VTC ranges
from 10 kO to 30 kO. A suitable circuit is shown in Figure 5.

_
30
ClK IN - (tLCD - 7tS>

where Is is the processor's set-up time between each read
or write cycle, and tLCD is the minimum turn-on or turn-off
time of the LCD as specified by the LCD manufacturer.
The DATA OUT output is an open drain N-channel device to
Vss (Figure 4). With an external pull-up this configuration
allows the controller to operate at a lower supply voltage,
and also permits the DATA OUT output to be wired in parallel with the DATA OUT outputs from any other drivers in the
system.
To program the number of backplanes being driven and the
MIS bit, load address 11000, a write bit, three bits for the
number of backplanes (Table I), and the MIS bit. The remaining 20 data bits will be ignored but it is necessary to
provide 21 more clocks before initiating another frame.

In a standby mode, the VTC input can be set to Vss. This
reduces the supply current to less than 300 ,...A per driver.
BACKPLANE AND SEGMENT OUTPUTS
Connect the backplane and segment outputs directly to the
LCD row and column lines. The outputs are designed to
drive a display with a total ON capacitance of up to 2000 pF.
The output structure consists of transmission gates tapped
off of a resistor string driven by VTC (Figure 6).
A critical factor in the lifetime of an LCD is the amount of DC
offset between a backplane and segment signal. Typically,
50 mV of offset is acceptable. The MM58201 guarantees an
offset of less than 10 mV.
The BP1 output is disabled when the MIS bit is set to zero.
This allows the BP1 output from the master chip to be connected directly to it so that synchronizing signals can be
generated. Synchronization occurs once each refresh cycle,
so the cascaded chips are assured of remaining synchronized.

4-57

Functional Description

(Continued)
MUSr RISE BY THIS POINT
RISE AT ANV TIME

ClK IN
DATA IN

DATA OUT

DON'T CARE

I

A4

A3

AD

I RM I

01

-----------------I::!o~1I]0~2IJO~3I
--,
B2 I

BPI

01

09

BP2

02

010 01.

Bl

011

~

I
.f
I

BP3

03

011

019

BO

BN

04

012

020

MIll

BP5

05

013

021

....

06

01.

022

BPJ

OJ

015

023

O'

016

024

0
1
1
0
0

0
1
1
0
1

0
1
1
1
0

BPI
A4
A3

a

a

0

AI
AI
AO

0

0
0
0
1

0
0

0
0
0
1
0

0
0
0
1
1

0
0
1
0'
0

0
0
1
0
1

0
0
1
1
0

0
0
1
1
1

0
1
0
0
0

0
1
0
0
1

a
1
0
1
0

0
1
0
1
1

~

.J

0
1
1
1
1

1
0
0
0
0

1
D
0
0
1

1
0
0
1
0

1
0
0
1
1

'I
0
1
0
0

1
0
1
0
1

1
0
1
1
0

1
0
1
1
1

1
1
0
D
0
TL/F/6146-6

Diagram above shows where data will appear on display Hstarting address, 011 00 Is specified In data format.

FIGURE 3. Data Format '

H

TL/F/614B-7

FIGURE 4. DATA OUT Structure

4·58

Functional Description (Continued)
1SV
COP42IL

00

t.-

r

n

CLK
IN

01

SO

SI

3

ZNZZZZor: 1II1II

I

J

DATA DATA
IN
OUT

ltV

VTC

I

n

""'""

CLK
IN

DATA DATA
IN
OUT

3301e

ACDSC

MMI1201
Vss

f '. .

RC OSC

1

Li
n,

'='

1

24,...

....

SEGMENT LINES
BACKPLANES

VOD
Vss
51-A4

."

I

....

MMII201

""

81-124

Ilk

VTC

VDD

BPI-"1

~

SK

Z4

~

SEGMENT LINES

Ix 4B DDT MATRIX
LIQUID CRYSTAL DISPLAY

TL/F/6146-8

FIGURE 5. Typical Application

VTC
SELECT

1

'}-BACKPLANE OR
ROMENT OUTPUT

t

T

SElEcT
TL/F/6146-9

FIGURE 6. Structure of LCD Outputs

4·59

'?A National
~ semiconductor

MM58241 High Voltage Display Driver
General Description

Features

The MM58241 is a monolithic MaS integrated circuit utilizing CMOS metal gate low threshold P- and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58241 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 32-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTIL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT
32

BlANKING
CONTROL-+l-----+I

OUTPUT
1

I+--t+-VOIS

CLOCK-+l-H

ENABLE----....
TUF/5600-1

FIGURE 1

4-60

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Input Pin
VOO + 0.3VtoVsS - 0.3V
Voltage at Any Display Pin
VOO to VOO - 62.5V
62.5V
VOO + IVolsl
Storage Temperature
-65·C to + 150"C
Power Dissipation at + 25·C
Molded DIP Package, Board Mount
2.28W·
2.05W··
Molded DIP Package, Socket Mount
Junction Temperature
130"C
Lead Temperature
(Soldering, 10 sec.)
260"C

Supply Voltage (VOO)
VSS = OV
Display Voltage (VOIS)
Temperature Range

Min

Max

Unlta

4.5
-55
-40

5.5
-25
+85

V
V
·C

"Molded DIP Package, Board Mount, 8JA = 46*C/W,
Derate 21.7 mW/oC above +25°C.
""Molded DIP Package, Socket Mount, 8JA = 51°C/W,
Derate 19.6 mW/oC above +25°C.

DC Electrical Characteristics
TA

=

-40"C to + 85°C, VOO

Symbol

= 5V

±0.5V, VSS

= OV unless otherwise specified

Parameter

Power Supply Currents
100

lOIS

Conditions

Min

Typ

VIN = Vss or VOO, Vss = OV,
VOIS Disconnected
VOO = 5.5V, Vss = OV, VOIS = -55V
All Outputs Low

Max

Unlta

150
10

/l-A
mA

0.8

V
V

0.4

V
V
V

10

IJ-A

15

pF

400
550
650
4.0
3.7
3.4

kO
kO
kO
kO
kO
kO

VOIS + 4

V

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
VIH

Logic'O'
Logic'l'

VOL
VOH
VOH

Data Output Logic Levels
Logic'O'
Logic'1'
Logic '1'

liN

CIN

RoFF

Input Currents
DATA IN, CLOCK
ENABLE, BLANK

(Note 1)

2.4

= 400/l-A
= -10/l-A
= - 500 /l-A
VIN = OV or VOO
lOUT
lOUT
lOUT

VOO - 0.5
2.8
-10

Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK

= 5.5V, VSS = OV
= -25V
= -40V
= -55V
= -25V
= -40V
= -55V
VOO = 5.5V, lOUT = Open Circuit,

Display Output Impedances

Voo

Output Off (Figure 3a)

VDlS
VOIS
VOIS
VOIS
VOIS
VOIS

RON

Output On (Figure 9b)

VOOL

Display Output Low Voltage

-55V

s: VOIS s:

-25V

Note 1: 74LSTTL VOH - 2.7V. lOUT - -4oo,.A, TTL VOH - 2.4V • lOUT - -400 p.A.

4·61

60

70
80
3.0
2.6
2.3
VOIS

II

... r-------------------------------------------------------------------------------------,

~
2
2

AC Electrical Characteristics TA =
Symbol

Parameter

-40"Cto

+ 85°C, Voo =

Conditions

5V ±O.5V·

Min

Typ

Max

Units,

800
300
300

kHz
ns
ns

fe
tH
tL

Clock Input
Frequency
High Time
Low Time

tos
tOH

Data Input
Set-UpTime
Hold Time

100
100

ns
ns

tES
tEH

Enable Input
Set-UpTime
Hold Time

100
100

ns
ns

teoo

Data Output
CLOCK Low to Data Out
Time

(Notes 3 and 4}

CL = 50pF
500

ns

Note 2: For liming purposes, Ihe signals ENABLE and BLANK can be ccnsidered 10 be tolally independent 01 each other.
Note 3: AC input waveform specification lor lest purposes: I r• It

.: 20 ns, I

= 800 kHz, 50% ± I 0% duty cycle,

Note 4: Clock input rise and lall limes must nol exceed 5 p.s,

Connection Diagrams
Dual-In-Llne Package
Vss(OVI
OUTPUT17
OUTPUT II
OUTPUTI5
OUTPUTI4
OUTPUTI3
OUTPUTI2
OUTPUT11
OUTPUTIO
OUTPUT9
OUTPUTI
OUTPUT7
OUTPUT6
OUTPUT5
OUTPUT4
OUTPUT 3
OUTPUT2
OUTPUTI
VDls
Yo. (BVI

-

I
2
3
4
5
I
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40 39 ,.....
38 I-37 I-36 I-35 I-34 I-33
32 I-31
30 I-29 t-28 t-27 t-26
25 I-24 I-23 I-22 I--

I--

MM58241

I--

r--

21

I--

Plastic Chip Carrier
OUTPUT 16
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
BlANKING CONTROL
ENABLE
DATA OUT
DATA IN
CLOCK

6

5

4

3

2

1 44 43 42 41 40

OUTPUT 13- 7

39 - OUTPUT 23

OUTPUT 12- 8

38 - OUTPUT 24

OUTPUT 11- 9

37 - OUTPUT 25

OUTPUT 10- 10

31 - OUTPUT 26

OUTPUT 9- 11

N/C- 12
OUTPUT 8- 13

35 - OUTPUT 27
MM58241V

341- H/C

33

I- OUTPUT 28

OUTPUT 7 - .14

32

OUTPUT 6- 15

31

I- OUTPUT 29
I- OUTPUT 30

OUTPUT 5 -

16

30

I- OUTPUT 31

OUTPUT 4 -

17

29

I- OUTPUT 32

18 19 20 21 22 23 24 25 26 27 28

TL/F/5600-2

Top View
TLlF/5600-8

FIGURE 2

Top View

Order Number MM58241N or MM58241V
See NS Package Number N40A or V44A

Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58421 uses three Signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58241 is shown in Figure 1.

to be loaded into the shift register following ENABLE high. A
logic '1' at the input will turn on the corresponding display
digit! segment! dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58241, because external pulldown resistors are not required." Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display )foltage applied. However, Figures 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.

Figure 2 shows the pinout of the MM58241 device, where
output 1 (pin 18) is equivalent to bit 1, i.e., the first bit of data
4-62

Functional Description

(Continued)

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58241.

new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58241, being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.

To clear (reset) the display driver at power on or any time,
the following flushing routine may be used. With the enable
signal high, clock in 32 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58241 is used to provide the
grid drive for a 32-digit 5 x 7 dot matrix vaccum fluorescent
(VF) display. The anode drive in this example is provided by
another member of the high voltage display driver family,
namely the MM58248, which does not require an externally
generated load signal.

In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0'-'1'
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show

+85'C

+25'C TYPICAL

-40'C

59.5
_ 49.6

'"

:;; 39.5
~

+29.5

~ 19.5
9.5
E . . ; - - - L - - - . . . L ._ _--'I..-_ _-1.._ _ IUUT (pAl

280

400

800

&00

TL/F/S600-3

FIGURE 3a. Output Impedance Off

3.3 kOTYPICAL
AT +25'C, 'luIS = -40V
2.3kO MAX
AT -40'C, Vuis = -55V

o - = : ; ; , . . . . . - - L - - - - ' - - - - - I - - - . . L - . I O U T (mAl
4
o

TL/F/5600-4

FIGURE 3b. Output Impedance On

II

Timing Diagrams
r-IH=j

~IL::E

~O;%

Ir=ll- -II=-;"':':";:'q--

DATA IN

______________J)(~___________

For the purposes of Ae measurements. VIH

= 2.4V. VIL = O.BV.

FIGURE 4. Clock and Data Timings

4-63

TLlF/5600-S

.-

i

:=IE
:=IE

.-------------------------------------------------------------------------------~

Timing Diagrams (Continued)
CumK ~-r-,~~~~--~--~----_#--~-------

.~~NG
CONTROL

. . :::::::::::::::JfJ~--~\~::::::::::::::
~

r

Vao~.---,--~
DISPLAY
OUTPUT

VuIa-_-J
TLlF/560D-8

FIGURE 5. MM58241 Timings (Data Format)

Typical Application
32·DlGIT MULTlPI.EX£O
• x 7 DDT MATRIX
VACUUM FLUORESCENT
IVF) DIIPLAY

i

~

_35~..'!,!,_~

~_3!,G!I~__

MM58248
DISPLAY DRIVER
CLOCK8

MM51241
DISPLAY DRIVER
DATAl t
CLOCK 1

DATAl

T

ENAELE 1

I
MICROPROCESSOR

B~Kl

I

DATA
OUT 1
TL/F/58DD-7

FIGURE 6. Mlcroprocesaor-Controlled Word Procesaor

.---------------------------------------------------------,~

a::::::

~National

g:
N

~ Semiconductor

~

N

MM58242 High Voltage Display Driver
General Description

Features

The MM58242 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 28-pin molded dual-in-line packages or as dice. The MM58242 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 20-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTIL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT

OUTPUT

20

1

BLANKING _ ........._ _ _ _....
CONTROL

III

CLOCK-+t-..

ENABLE----....
TL/FI7924-1

FIGURE 1

4-65

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (VOO)
Vss = OV

Voltage at Any Input Pin

VOO + 0.3V to VSS -0.3V

Voltage at Any Display Pin

VOO to VOO -62.5V
62.5V

VOO +Ivoisl
Storage Temperature

Min

Max

Units

4.5
-55

5.5
-25

V

Display Voltage (VOIS)
Temperature Range

-40

+S5

'C

V

- 65'C to + 150"C

Power Dissipation at + 25'C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount
Junction Temperature

2.03W·
1.S3W··

Lead Temperature (Soldering, 10 sec.)

260"C

130'C

·Molded DIP Package, Board Mount, 8JA
Derate 19.2 mW/'C above +25'C.

=

52'C/W,

=

··Molded DIP Package, Socket Mount, 8JA
Derate 17.2 mW/'C above + 25'C.

5S'C/W,

DC Electrical Characteristics
TA

=

-40"Cto +S5'C, VOO

Symbol
100

=

5V ±0.5V, Vss

=

OV unless otherwise specified

Parameter

Conditions

lOIS

VIL
VIH

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
Logic'O'
Logic '1'

(Note 1)

VOL
VOH
VOH

Data Output LogiC Levels
Logic '0'
Logic '1'
Logic '1'

lOUT
lOUT
lOUT

liN

Input Currents
DATA IN, CLOCK
ENABLE, BLANK

CIN

Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK

VIN

ROFF

Display Output Impedances
Output Ofl (Figure 3a)

RON

Output On (Figure 3b)

VOOL

Display Output Low Voltage

Note 1: 74LSTTL VOH

= 2.7V @ lOUT =

Min

Typ

VIN = VSS orVOO, VSS = OV, VOIS Disconnected
VOO = 5.5V, Vss = OV, VOIS = 55V
All Outputs Low

Power Supply Currents

Units

150
10

/Jo A
mA

O.S

V
V

0.4

V
V
V

10

/Jo A

15

pF

400
550
650
4.0
3.7
3.4

kO
kO
kO
kO
kO
kO

VOIS+4

V

2.4

= 400/JoA
= -10 IJoA
= - 500 /JoA

Voo-0.5
2.S

:= OV or VOO

VOO = 5.5V, VSS
VOIS = -25V
VOIS = -40V
VOIS = -55V
VOIS = -25V
VOIS = 40V
VOIS = -55V

-10

=

OV
60
70
SO
3.0
2.6
2.3

VOO = 5.5V, lOUT = Open Circuit,
-55V s; VOIS s; -25V

-400 pA. TTL VOH

Max

= 2.4V @

lOUT

=

-400 pA.

4-66

VOIS

AC Electrical Characteristics TA =
Parameter

-40"Cto

+ 85'C, Voo

Conditions

i:
i:

= 5V ±0.5V

Typ

Min

Max

Units

UI
CD
N
~

N

Clock Input
Frequency, fc
High Time, tH
Low Time, tL

(Notes 3 and 4)
800

Data Input
Set-Up Time, tos
Hold Time, tOH
Enable Input
Set-Up Time, tES
Hold Time, tEH

(Note 2)

Data Output
CLOCK Low to Data Out
Time, tcDO

CL = 50pF

300
300

kHz
ns
ns

100
100

ns
ns

100
100

ns
ns
500

ns

Note 2: For timimg purposes. the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC input waveform specification for lest purposes:

Ir ,,; 20 ns. If

,,; 20 ns. f = 800 kHz. 50%

± 10% duty cycle.

Note 4: Clock inpul rise and fall limes musl not exceed 5 "'S.

Connection Diagrams
Dual-In-Llne Package

U

Plastic Chip Carrier

28

r- OUTPUT 12

OUTPUT 11_ 2

27

r- OUTPUT 13

OUTPUT 10 _

3

261- OUTPUT 14

OUTPUT 9 _

4

25 _

Vss (OV) _

1

4

OUTPUT 15

24 - OUTPUT 16

24 _

OUTPUT 16

OUTPUT 7 _

6

23 -

OUTPUT 17

OUTPUT 6- 7

OUTPUT 6 _

7

22 -

OUTPUT 18

OUTPUT 5- 8

8

21 -

OUTPUT 19

OUTPUT 4 -

9

20 -

OUTPUT 20

OUTPUT 3 -

10

19 -

BLANKING CONTROL

OUTPUT2 -

11

18 -

ENABLE

OUTPUT 1 -

12

17 -

DATA OUT

YoIS -

13

16 ..... DATA IN

1 28 27 26
25 - OUTPUT 15

5

OUTPUT 5 -

2

OUTPUT 7- 6

OUTPUT 8 _

MM58242

3

OUTPUT 8- 5

23 - OUTPUT 17
MMS8242V

22 - OUTPUT 18

OUTPUT 4- 9

21 - OUTPUT 19

OUTPUT 3- 10

20 - OUTPUT 20

OUTPUT 2- 11

19 - BLANKING CONTROL
12 13 14 15 16 17 18

TLlF/7924-8

Top View
Order Number MM58242V
See NS Package Number V28A

_ _ _- 15
- '-CLOCK
VoD (5V) - L.-_
14

TL/F17924-2

Top View
FIGURE 2
Order Number MM58242N
See NS Package Number N28B

4-67

Functional Description
To clear (reset) ~he display driver at "'power on" or any time,
the following flushing routine may be used. With the enable
signal high, clock in 20 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58242 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL Input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58242 is shown in Figure 1.

In FigUfB 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logiC '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0'-'1'
transition. When the ENABLE signal goes low, tile contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58242 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.

FigUfB 2 shows the pinout of the MM58242 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic '1' at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58242, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied, However, FigufBs 38
and 3b show that this output impedance will remain constant for a fixed value of display voltage.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58242 is used to provide the
grid drive for a 40-digit 2 line 5 x 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
provided by another member of the high voltage display
driver family, namely the MM58248, which does not require
an externally generated load signal.

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58242.

+85'C

+25'C TYPICAL

-40'C

&9.5
_ 48.5

e

-;; 38.1
~
+"
29.5

HF~~;;;iI&."l

"9.5
9.5

...L-_1ou1' (pA)

E..;.._ _..L....._ _...L-_ _...I-_ _

200

400

BOO
TL/F/7924-3

FIGURE 38. Output Impedance Off
3.3 kO TYPICAL
AT +25'C. VtHs=-40V
2.3 kO MAX
AT -40'C. VtHs = -55V

O~~---L----~~----~----~--~IMIM)

o

TLlF/7924-4

FIGURE 3b. Output Impedance On

4-68

Timing Diagrams

\~.,~FtH-1

~C _~;.:,;;;o~___

~

_____

-J)(~

______
TL/F17924-5

For the purp0888 of AC measurement, VIH = 2,4V, VIL = Q,av.

fiGURE 4. Clock and Data Timings

~AOOT -:,~~~3E~~::::::::~:::::::::3~::::
MU~~~-t~~~~~:7~--~~::::~

.~ ~~:::::::::::::Jlf~----~,~::::::::::::::
Vaa

----r---""

DISPlAY
OOTPUT

YtIIa-_oJ
TL/F17924-6

FIGURE 5. MM58242 Timings (Data Format)

Typical Application
4tJ.Dl6IT .Y z.t.INE
5 x 7 MULTII'UlIED
DDT MATRIX VACUUM
FLUORESCENT (VFI
DISPLAY

---CLOCK 8

I
I

---35

35
ANODES

MM58248
DISPLAY
DRIVER 1

I
I

20
GRIDS

I I
DATA 81

I

MM58248
DISPLAY
DRIVER 2

f

20

----

ANODES

MM58242
DISPLAY
DRIVER 1

GRIDS
---OUT
FA

~

MM58242
DISPLAY
DRIVER 2

I

DATA 82
DATll
CLOCK 2
DATA 21

MICROPROCESSOR

ENABLE
BLANK
TlIF17924-7

FIGURE 8. Mlcroprocessor-Controlled Word Processor

4-69

~National

~ semiconductor

MM58248 High Voltage Display Driver
General Description

Features

The MM58248 is a monolithic MaS integrated circuit utilizing CMOS metal gate low threshold P- and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58248 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 5 x 7 dot matrix display).

•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven display
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direqt interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible With NS display driver family
Compatible with alphanumeric or dot matrix displays
No load signal required

Block Diagram
OUTPUT
35

OUTPUT
1

I+---~"'-VDIS

BATAIN

CLOCK-.........

TL/F/5599-1

FIGURE 1

4-70

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Input Pin

Junction Temperature

130"C

Lead Temperature
(Soldering, 10 seconds)

260"C

Voo + 0.3V to Vss - 0.3V

Voltage at Any Display Pin

Operating Conditions

Voo to Voo - 62.SV
-6S·Cto +1SO"C

Power Dissipation at + 2S·C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount
'Molded DIP Package, Board Mount 8JA
Derate 21.7 mWrC above +25·C.

2.28W·
2.05W··

=

··Molded DIP Package, Socket Mount, 8JA
Derate 19.6 mWrC above +25·C.

Max

Units

4.S

S.S

V

-55

-25

V

+85

·C

Min

62.SV

Voo + IVorsl
Storage Temperature

Supply Voltage (Voo)
Vss = OV
Display Voltage (Vors)
Temperature Range

-40

46·C/W,

=

51·C/W,

DC Electrical Characteristics
TA

=

-40"C to + 85·C, Voo

Symbol
100

=

5V ±0.5V, Vss

=

OV unless otherwise specified

Parameter

Conditions

Min

VrN = VssorVoo, Vss
Vors Disconnected

Power Supply Currents

=

Voo = S.SV, Vss = av,
Vors = -SSV, All Outputs Low

lors
Vrl

Input Logic Levels
DATA IN, CLOCK Logic '0'

VrH

Input Logic Levels
DATA IN, CLOCK Logic '1'

(Note 1)

IrN

Input Currents, DATA IN, CLOCK

VrN

CrN

Input CapaCitance, DATA IN, CLOCK

ROFF

Display Output Impedances
Output Off (Figure 3s)

Voo = S.SV, Vss
Vors = -2SV
Vors = -40V
Vors = -55V

=

Display Output Impedances
Output on (Figure 3b)

Voo = 5.5V, Vss
Vors = -25V
Vors = -40V
Vors = -55V

=

Display Output
Low Voltage

Voo = 5.5V, lOUT = Open Circuit,
-55V ~ Vors ~ -25V

RON

VOOl

Note 1: 74LSTIL VOH

~

2.7V III rOUT

~

-400 pA. TIL VOH

~

2.4V

AC Electrical Characteristics TA =
Symbol

Typ

OV,

=

@

Max

Units

150

p.A

10

mA

0.8

V

2.4
-10

OVor Voo

rOUT

~

V
10

p.A

1S

pF

400
550
650

kO
kO
kO

4.0
3.7
3.4

kO
kO
kO

Vors + 4

V

OV
60
70
80
OV
3.0
2.6
2.3
Vors

-400 ".A.

-40·Cto + 85·C, Voo

=

5V ±0.5V

Parameter

Conditions

fe

Clock Input Frequency

(Notes 2, 3)

tH

Clock Input High Time

300

ns

tl

Clock Input Low Time

300

ns

tos

Data Input Setup Time

100

ns

tOH

Data Input Hold Time

100

ns

Cl

=

Note 2: AC input wavelorm specification lor test purposes: 1,. It " 20 ns. I

50pF

~

Min

1 MHz. 50% ± 10% duty cycre.

Note 3: Clock input rise and lair times must not excesd 5 ".s.

4·71

Typ

Max

Units

1.0

MHz

•

..,.

co
N

co
II)

Connection Diagrams

:::e
:::e

Dual-In-Une Package
Vss (OV)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
YD.s
Voo (5V)

40
39
38
37
36

35
34

10
11
12
13
14
15
16
17
18
19

MM58248

33
32
31

30
29
28
27
26
25
24
23
22
21

20

Plastic Chip carrier
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUT1'UT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
DATA IN

OUTPUT 13

OUTPUT 25

OUTPUT 12

OUTPUT 24

OUTPUT 11

OUTPUT 25

OUI'I'UT 10

OUTPUT 26
OUTPUT 27

OUTPUT 9

N/C

N/C
OUTPUT 26

OUTPUT 8
OUTPUT 7

OUTPUT 29

OUTPUT 6

OUTPUT 30

OUTPUT 5

OUTPUT 51

29

OUTPUT 4

OUTPUT 52

CLOCK
TL/F/5599-2

Top View
TLlF/5599-8

Order Number MM58248N
See NS Package Number N40A

TOp View
Order Number MM58248V
See NS Package Number V44A

FIGURE 2

Functional Description
In Figure 5, a start bit of logic '1' precedes the 35 bits of
data, each bit being accepted on the rising edge of CLOCK,
i.e., a '0'-'1' transition. At the 36th clock, a LOAD Signal is
generated synchronously with the high state of the clock,
thus loading the 35 bits of the shift register into the latches.
At the low state of the clock, a RESET signal Is generated,
clearing all bits of the shift register for the next set of data.
Hence, a complete set of 36 clock pulses is needed for the
MM58248, or the shift register will not clear. To clear (reset)
the display driver at 'power on' or any time, the following
flushing routine may be used. Clock in 36 "zeroes", followed by a "one" (start bit), followed by 35 "zeroes". This
procedure will completely blank the display. It Is recommended to clear the driver at power on.

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58248 uses two signals,
DATA IN and CLOCK, with a format of a leading '1' followed
by the 35 data bits, hence allowing data transfer without an
additional Signal. A block diagram of the MM58248 is shown
in Figure 1.

Figure 2 shows the pinout of the MM58248 device, where
output 1 (pin 18) is equivalent to bit 1, i.e., the first bit of data
to be loaded into the shift register following the start bit. A
logic '1' at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by the use of the MM58248, because external
pull-down resistors are not required. Due to the nature of
the output stage, both its on and off impedance values vary
as a function of the display voltage applied. However, Figures 3a and 3b show that this output impedance will remain
constant for a fixed value of display voltage.
Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58248.

Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58248 is used to provide the
anode drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent (VF) display. The grid drive In this example Is provided
by another member of the high voltage display driver family,
namely the MM58241, which has the additional features of
a BLANKING CONTROL pin, a DATA OUT pin, and an
ENABLE (external load signal) pin.

4-72

Functional Description (Continued)
+85"C

+25"C TYPICAL

-4Q"C

59.5

e 49.5
j39.5
+29.5

'

19 .5
9.5
E..:_ _--1_ _ _--L_ _ _....L.._ _ _..l----!.. lOUT (pA)

200

400

BOO

600

TLlF/5599-3

FIGURE 3a. Output Impedance Off

2.3 kll MAX

AT -4Q"C, VOIS= -55V
4

.1-_

_;,...._--1_ _ _...J.._ _ _......_ _ _

lOUT (mA)

4
TLlF/5599-4

FIGURE 3b. Output Impedance On

Timing Diagrams

!-

CLOCK _ _ _

DATAIN : ) [ : :

t'£·);.;:~;,;,%_-

:1. . .__

Ir
_ _ _J

ForlhepurposesofAC measurement, V,H

X"'__I--_It__
TL/F 15599-5

= 2.4V, V,L = o.av.

FIGURE 4. Clock and Data Timings
START
eLK 34

ClK 35

CLK

CLOCK

DATA IN

n
n

LDADJl

(INTERNAL)

(INTERNAL)
RESET

1-_ _ _ _ _ _ _ _ _ _ _ _."._ _ _ _ _ _....

----In

11-_ _ _ _ _ _ _ _ _ _ _1,.,_ _ _ _ _ _ _ _..1

~~
~

,,_ _ _ __

10_ _ __

/

"'.--------.~--------~

TLlF/5599-6

FIGURE 5. MM58248 Timings (Data Format)

4-73

...
co

~

:::E
:::E

r-------------------------------------------------------------------------------~

Typical Applications
32·DIGIT MULl'IPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY

;

...L

-35.!~~-i

----32 GRIDS

MM58248
DISPLAY DRIVER
CLUCK8

MM58241
DISPLAY DRIVER

DATA 8

. DATAlt
CLOCK 1

T

ENABLE 1

I
MICROPROCESBDR

BLANK 1

DATA
OUT 1
TL/F/5599-7

FIGURE 6. Mlcroprocessor·Controlled Word Processor

4·74

~National

~ semiconductor

MM58341 High Voltage Display Driver
General Description

Features

The MM58341 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58341 is particularly suited for driving high voltage (35V max) vacuum fluorescent (VF) displays, (e.g., a 32-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT
32

BLANKING
CONTROL -+1-----+1

OUTPUT
1

1+--11+-- Vms

•

CLOCK-+l-~

ENABLE - - - -....

TL/F/S603-1

FIGURE 1

4-75

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (VOO)
VSS = OV

Voltage at Any Input Pin

Display Voltage (VOIS)
Temperature Range

VOO + 0.3VtoVss.- 0.3V

Voltage at Any Display Pin

VOO to VOO - 36.5V
36.5V

Voo + IVolsl
Storage Temperature

Min

Max

Units

4.5
-30

5.5

V

-10

-40

+85

V
·C

-65'Cto + 150'C

Power Dissipation at 25'C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount
'Molded DIP Package, Board Mount,
Derate 21.7 mW'C Above 25'C
•• Molded DIP Package, Socket Mount,
Derate 19.6 mWrC Above 25'C

2.28W·
2.05W··
8JA = 46'C/W
8JA = 51'C/W

Junction Temperature

130'C

Lead Temperature (Soldering, 10 seconds)

26O'C

DC Electrical Characteristics
TA = -40'C to + 85'C, voo = 5V ± 0.5V, Vss = OV unless otherwise specified
Symbol
100

Parameter

Conditions

Power Supply Currents

lOIS

Max

Units

VIN = Vss or Voo, VSS = OV,
VOIS Disconnected

150

/loA

Voo = 5.5V, VSS = OV,
VOIS = -30V, All Outputs Low

10

mA

0.8

V

VIL

Input Logic Levels DATA IN,
CLOCK ENABLE, BLANK Logic '0'

VIH

Input Logic Levels DATA IN,
CLOCK ENABLE, BLANK Logic '1'

(Note 1)

VOH

Data Output Logic Levels
Logic'O'

lOUT = 400 /loA

VOH

Data Output Logic Levels
Logic '1'

lOUT = -10/loA

VOH

Data Output Logic Levels
Logic '1'

lOUT = -500 p.A

liN

Input Currents DATA IN,
CLOCK ENABLE, BLANK

VIN = OVorVoo

GIN

Input CapaCitance DATA IN,
CLOCK ENABLE, BLANK

ROFF

Display Output Impedances
Output Off (Figure 3a)

RON

VOOL

Display Output Impedances
Output On (Figure 3b)

Display Output Low Voltage

Note 1: 74LSTIL VOH

~

2.7V @ lOUT

~

Voo =
VOIS =
VOIS =
VOIS =

Min

0.4

5.5V, Vss = OV
-10V
-20V
-30V

2.4V @ lOUT

~

V

2.8

V

-10

55

60
65

500

-400,.A.

4·76

V

Voo - 0.5

700
600

VOO = 5.5V, lOUT = Open Circuit,
-30V S; VOIS S; -10V
~

V

2.4

VOIS = -10V
VOIS = -20V
VOIS = -30V

-400 ,.A, TIL VOH

Typ

VOIS

10

p.A

15

pF

250
300
400

k{}
k{}
k{}

800
750
680

{}

VOIS + 2

V

{}
{}

AC Electrical Characteristics TA =

-40·Cto

+ 85·C, Voo =

5V ±0.5V

Conditions
Min
Typ
Max
Parameter
(Notes 3, 4)
Clock Input Frequency
800
fo
Clock Input High Time
300
tH
Clock Input Low Time
300
tL
Data Input Setup Time
100
'os
Data Input Hold Time
100
tOH
Enable Input Setup Time
100
tES
Enable Input Hold Time
100
tEH
Data Output Clock Low to
CL = 50pF
toDO
500
Data Out Time
Note 2: Nol8tha~ for timing purposes,the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC Input waveform specification for tast purpose: t,. ,; 20 n., It ,; 20 n., f = 800 kHz, 50% ± 10% duty cycle.
Note 4: Clock Input rise and fall time. must not exceed 5 ",•.
Symbol

Connection Diagrams
.....,

0UTI'U7I -

Functional Description

.. f 31 f 31 f IT f 3.fII f 3< f U f32 f 31 f 10
II f II f 27f21 f -

_ _1

11

r-

OUTPUTI 11
1MITPUT7-TI
1MITPUT1-13
IMITPUTI-"
OUTl'llT' -11
OUTPUT. 11
IMITPUTZ-17
OUTPUT1 11
.... -11
1Io(1V1- II

1If.. f .. f Z2 f "f-

OUTl'llT1.
OUTl'llT1I
OUTPUTID
OUTPUT"
OUOOT22
OUTPUT"
OUOOT2'
OUTPUTII
OUTPUTII
OUTPUT27
OUTPUTII
OUTPUfll
OUTPUTIO
OUTl'llf31
OUTPTJf32
."-NOCONTIIOL
ENABLE
OATAOUf
OATA'•
CLOCK

TLlF/5603-2

Top View
Order Number MM58341N
See NS Package Number N40A
Plastic Chip Carrier
:2 :!! iii N :::I

:! :!! !! !::

III
i i

8

OUTPUT 13OUTPUT t2OUTPUT tlOUTPUT 10OUTPUT 9N/C-

~

5

5 5

~

i'f~i"'i"

5

5 4 3 2 t 44 43 42 41 40

7
8
9
10
11

39 - OUTPUT 23
38 - OUTPUT 24
37 - OUTPUT 25
36 - OUTPUT 26
35 - OUTPUT 27
34 -N/C
33 - OUTPUT 28
32 - OUtpUT 29
31 -, OUTPUT 30
30 ~ OUTPUT 31
29 r OUTPUT 32

MM58341V

12

13
OUTPUT 7- 14
OUTPUT 8- 15
OUTPUT 5- 16
OUTPUT 4- 17
OUTPUT 8-

18

II

20 21 22 23 24 25 26 27 28

I ~ I k k~~ §~ ~~ ~ffi ~5~~~
! ! !
5

> >

;!

ns

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58341 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logiC '1'
will turn off all sections of the display. A block diagram of
the MM58341 is shown in Figure 1.
Figure 2 shows the pinout of the MM58341 device, where
output 1 (pin 18) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic '1' at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58341, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figures 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.
Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58341.
To clear (reset) the display driver at power on or any time,
the following flushing routine may be used. With the enable
signal high, clock in 32 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logiC '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0'-'1'
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58341, being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58341 is used to provide the
grid drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent
(VF) display. The anode drive in this example is provided by
another member of the high voltage display driver family,
namely the MM58348, which does not require an externally
generated load signal.

Dual-In-Llne Package
Vu(ov1-1
1MITPUT17-'
IMITPUTTI-'
IlUTPUTTI •
OUTPUT" I
1MITPUT13 - I
IMITPUTTZ-7
1MITPUT11-1
OUTl'llfTl •

Units
kHz
ns
ns
ns
ns
ns
ns

0

2!

TLI~/5603-8

Top View
Order Number MM58341V
See NS Package Number V44A
4-77

... r------------------------------------------------------------------------------------------,
Functional Decription
~

m
::E

(Continued)

::E

+85·C

34.5

~

1.24.5
+

"4.5
o O-"--'...OO-----200
.......- - -aoo
..L..---.......- - -. . L . . - -L+ lour (pAl
400
500
IOO
TL/F/5603-3

FIGURE 3a. Output Impedance Off

G>i

J~
'21
iii

6IIOIlTYPICAl
M +25·C. ¥Dos = -2OV

'.0

4000 MAX
AT -CO·C. ¥Dos =-3OV
0.5

co

o

_=_..L.__--'______..L.._ _- L_ _ _•
o

rouTllIA)

0.5

TL/F/5603-4

FIGURE 3b. Output Impedance On

Timing Diagrams

TUF/5603-5

FOT the purposes of AC messurements, VIH

= 2.4V, VIL = O.BV.

FIGURE 4. Clock and Data Timings

B~~ H%:::::::::::::::J/~~---~,~::::::::::::~
TYPICAl
DISPLAY
OUTPUT

¥Dos--J
TL/F/5603-6

fiGURE 5. MM58341 Timings (Data Format)

4·78

Typical Application
32·D161T MUIJIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VFI DISPlAY

I

~

2~~!s_~

__3!,,!1~_.

MM58348
DISPlAY DRIVER

CLOCKI

MM68341
DISPLAY DRIVER

t

DATAl

DATAl
CLOCK 1

1

ENABLE 1

I
MICROPROCESSOR

BLANK 1

DATA
OUT 1
TL/F/5603-7

FIGURE 6. Microprocessor-Controlled Word Processor

•
4·79

~~----~----------~--------------------------------------,

a ~National

== ~ Semiconductor
==
MM58342 High Voltage Display Driver
General Description

Features

The MM58342 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P- and N-channel devices. It is available both in 28-pin molded dual-in-line packages or as dice. The MM58342 Is particularly suited for driving high voltage (35V max) vacuum fluorescent (VF) displays (e.g., a 20-digit alphanumeric or dot matrix display).

•
•
•
•
•
•
•
•
•

Applications
•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Direct interface to high voltage display
Serial data Input
No external resistors required
Wide display power supply operation
LSTTL compatible Inputa
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade

Block Diagram
OUTPUT

OUTPUT

20

1

BLANKING _ ...._ _ _ _-..
CONTROL

OATA_...._ ..
IN

CLOCK-....-

..

ENABLE - - - - - '

TL/F/7925-1

FIGURE 1

4-80

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (VOO)
VSS = OV

Voltage at Any Input Pin

Display Voltage (VOIS)
Temperature Range

-40

+S5

Min

Voo + O.SV to Vss - O.SV

Voltage at Any Display Pin
VOO + IVolsl
Storage Temperature

VOO to VOO - S6.5V

Max

Units

4.5

5.5

V

-so

-10

V
·C

S6.5V
- 65·C to + 150·C

Power Dissipation at 25·C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount

2.0SW·
1.SSW··

Junction Temperature

1SO"C

Lead Temperature (Soldering, 10 sec.)

260"C

·Molded DIP Package, Board Mount, (JJA = 52·C/W,
derate 19.2 mW I"C above 25·C.
··Molded DIP Package, Socket Mount, (JJA = 5S·C/W,
derate 17.2 mW I"C above 25·C.

DC Electrical Characteristics
TA = -40·Cto +S5·C, VOO = 5V ±0.5V, VSS = OV unless otherwise specified
Symbol

Parameter

Conditions

Min

Typ

Max

Unlta

150

/LA

10

mA

O.S

V
V

0.4

V
V
V

10

IJ.A

15

pF

250
SOO
400
SOO
750
6S0

kO
kO
kO
0
0
0

VOIS + 2

V

Power Supply Currents
VIN = VSS or VOO, VSS = OV,
VOIS Disconnected
VOO = 5.5V, Vss = OV, VOIS = -SOY
All Outputs Low

100

lOIS

Vil
VIH

Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
Logic '0'
Logic '1'

(Note 1)

VOL
VOH
VOH

Data Output Logic Levels
Logic '0'
Logic '1'
Logic '1'

lOUT = 400 IJ.A
lOUT = -10/LA
lOUT = -500/LA

liN

Input Currents DATA IN,
CLOCK ENABLE, BLANK

CIN

Input Capacitance DATA IN,
CLOCK ENABLE. BLANK

ROFF

Display Output Impedances
Output Off (Figure 3a)

RON

Output On (Figure 3b)

VOOl

Display Output Low Voltage

Note 1: 74lSTTl

VIN

=

2.4

VOO - 0.5
2.S

OV or VOO

VOO = 5.5V, VSS
VOIS = -10V
VOIS = -20V
VOIS = -SOY
VOIS = -10V
VOIS = -20V
VOIS = -SOY

-10

=

OV
55
60
65
700
600
500

Voo = 5.5V, lOUT = Open Circuit,
-SOY s: VOIS s: -10V

VOH = 2.7V @ lOUT = -400 pAt TTL VOH = 2.4V @ lOUT = -400 pA.

4-81

VOIS

II

AC Electrical Characteristics TA = -400Cto + 85°C. Voo = 5V ±0.5V
Symbol

Parameter

Typ

Max

Units

800
300
300

kHz
ns
ns

100
100

ns
ns

100
100

ns
ns

Min

Conditions
(Notes 3 and 4)

fc
tH
tL

Clock Input
Frequency
High Time
Low Time

tos
tOH

Data Input
Set-UpTime
Hold Time
Enable Input
Set-UpTIme
Hold Time

(Note 2)

tES
tEH

CL = 50pF

.tCDO

Data Output
CLOCK Low to Data Out
Time

500

ns

Note 2: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent 01 each other.
Note 3: AC input waveform specification for test purposes; 1,. tf :s; 20 ns. I - 800 kHz. 50% ± 10% duty cycle.
Note 4: Clock input rise and lall times must not exceed 5 "s.

Connection Diagrams
Plastic Chip Carrier

Dual-In-Llne Package
Vas (OVI_ 1

U

OUTPUTl1_ 2
OUTPUT10_ 3
OUTPUTB_ 4
OUTPUT 8 _

5

OUTPUT 7 _

6

r- OUTPUT 12
r- OUTPUT 13
ZI r- OUTPUT 14
25 r- OUTPUT 15
24 r- OUTPUT 18
23 r- OUTPUT 17
Z8

27

4321282726
25 - OUTPUT 15

OUlPUT 7- 6

24 - OUTPUT 16

OUlPUT 6- 7

OUTPUT 8 _

7

OUTPUT 5 _

I

21

OUTPUT 4 -

9

20

OUTPUT 3 -

10

19 I- BLNlKING CONTROL

OUTPUT 2 _

11

l11-ENA8LE

221- OUTPUT 18

OUTPUT1- 12

OUlPUT 8- 5

OUTPUT 5- 8

I- OUTPUT 19
I- OUTPUT 20

23 - OUTPUT 17
....58342V

22 - OUTPUT 18

OUTPUT 4- 9

21 -OUTPUT 19

OUTPUT 3- 10

20 - OUTPUT 20
19 - BLANKING CONTROL

OUTPUT 2- 11
12 13 14 15 16 17 18

17 -DATA OUT

VoIs-13

16 -DATA IN
15 -CLOCK

Vuo(5VI- 14

TL/FI7925-B

TL/F17925-2

Top View
Order Number MM58342V
See NS Package Number V28A

Top View
FIGURE 2
Order Number MM58342N
See NS Package Number N28B

Functional Description
FigUffJ 2 shows the pinout of the MM58342 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic '1' at the input will turn on the corresponding display
digitI segment! dot output.
A significant reduction In discrete board components can be
achieved by use of the MM58342, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, FiguffJS 3a

This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58342 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic '1'
will turn off all sections of the display. A block diagram of
the MM58342 is shown in FiguffJ 1.

4-82

Functional Description

(Continued)
and 3b show that this output impedance will remain constant for a fixed value of display voltage.

of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58342 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58342 is used to provide the
grid drive for a 40-digit 2 line 5 x 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
provided by another member of the high voltage display
driver family, namely the MM58348, which does not require
an externally generated load signal.

Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58342.
To clear (reset) the display driver at power on or any time.
the following flushing routine may be used. With the enable
signal high, clock in 20 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.

In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., '0'-'1'
transition. When the ENABLE signal goes low, the contents

+85°C
34.5

~
~

,

I
I

,
,,

24.5

~

+

~ 14.5

I,' " ... ...

~ ",~0
0

100

200

300

400

500

600
TUF17925-3

FIGURE 3a. Output Impedance Off

60011 TYPICAL
AT +25°C, Yo,s = -20Y
40011 MAX
AT -40°C, VIMS = -SOy

_E:~......L

_ _ _-'-_ _---I~_ _...L._ _ _•

0.5

,

1

IOUTIIIIA)

1,5
TL/F/7925-4

FIGURE 3b. Output Impedance On

II

Timing Diagrams
CLOCK

DATA IN

~IHX;.:;::.:O~:",__
~----------~)(~----------

For the purposes of AC measurement, V'H = 2.4V, V'L = a,sv,

FIGURE 4. Clock and Data Timings

4-83

TL/F/7925-5

Timing Diagrams (Continued)
CLOCII 110% :t-;t-I~j:::;T-\:=-:::/-\:=::::

~ 1IO%:::::::::::::::J/f~----~,~::::::::::::::
Vuu ----p--_.
DISPlAY
OUTPUT

YIIII----'

TUF17925-6

FIGURE 5. Timings (Data Format)

Typical Application
4O-DI61T BY 2-UNE
5 x 7 MULTIPlEXED
DDT MATRIX VACUUM
FLUORESCENT (Vf)
DISPlAY

----

CLOCK 8

I
I

---35

35
ANODES

MM58348
DISPlAY
DRIVER 1

I
I

20
GRIDS

----

ANODES

I I
DATA 81

f

I

11111158348
DISPlAY
DRIVER 2

MM58342
DISPlAY
DRIVER 1

20
GRIDS

OUT
~A

----

I

MM5B342
DISPLAY
DRIVER 2

I

DATA 82
DATJ21
CLOCK 2
DATA 21

MICROPROCESSOR

ENABLE
BLANK
TLfFf7925-7

FIGURE 6. Microprocessor-Controlled Word Processor

4-84

~National

~ semiconductor

MM58348 High Voltage Display Driver
General Description

Applications

The MM58348 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 40-pin molded dual-in-line packages or as dice. The MM58348 Is particularly suited for driving high voltage (35V max) vacuum fluorescent (VF) displays (e.g., a 5 x 7 dot matrix display).

•
•
•
•
•
•

COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards

Features
•
•
•
•
•
•
•
•

Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
No load signal required

Block Diagram
OUTPUT
35

OUTPUT
1

..----1+- VoIS

DATA IN

CLOCK

TL/F/5601-1

FIGURE 1

4-85

Absolute Maximum Ratings

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (Voo)
VSS = OV

4.5

5.5

V

Voltage at Any Input Pin

Display Voltage (VOIS)

-30

-10

V

'. -40

+B5

Min

Voo + 0.3V to Vss - 0.3V

Voltage at Any Display Pin

Temperature Range

Voo to Voo - 36.5V

Max

Units

;

°C

36.5V

Voo + IVDlsl
Storage Temperature

.:-65°Cto + 150"C

Power DissipatiOn at 25°C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount
'Molded DIP Plickage, Board Mount,
Derate 21.7 mWC Above 25°C
··Molded DIP Package, Socket Mount,
Derate 19.6 mW/oC Above 25°C

2.2BW·
2.05W··
/JJA = 46°C/W
/JJA

=

51°C/W

Junction Temperature

130"C

Lead Temperature
(Soldering, 10 seconds)

260"C

DC Electrical Characteristics
TA

=

-40"Cto +B5°C, Voo

Symbol

100

=

5V ±0.5V, Vss

=

Power Supply Currents

lOIS

VIH

Input Logic Levels
DATA IN, CLOCK
Logic '0'
Logic '1'

liN

Input Currents DATA IN, CLOCK

CIN

Input Capacitance DATA IN, CLOCK

ROFF

Display Output Impedances
Output Off (Agure 3a)

VIL

RON

VOOL

OV unless otherwise specified.

Parameter

Display Output Low Voltage

= 2.7V @ lOUT =

Min

Typ

Max

Units

150

p.A

10

mA

O.B

V

10

p.A

15

pF

250
300
400
BOO
750
680

k{}
k{}
k{}

VOIS + 2

V

VIN = Vss or Voo, Voo = 5.5V,
VSS = OV, VOIS Disconnected
Voo = 5.5V, VSS = OV,
VDlS = -30V, All Outputs Low

2.4

Output On (Figure 3b)

Note 1: 74LSTIL VOH

Conditions

-400 ".A, TIL VOH

VIN

=

Voo = 5.5V, Vss
VOIS = -10V
VDlS =: -20V
VDlS = -30V
VOIS' = -10V
VOIS = -20V
VOIS = -30V

V

-10

OVorVoo

=

OV
55
60
65
700
600
500

Voo = 5.5V, lOUT = Open Circuit,
-30V S; VOISS; -10V

VOIS

{}
{}
{}

= 2.4V @ lOUT = -400 p.A.

AC Electrical Characteristic TA =

-4O"Cto +B5°C, VOO

=

5V ±0.5V

Parameter

Conditions

fc

Clock Input Frequency

(Notes 2 and 3)

tH

Clock Input High Time

300

ns

tL

Clock Input Low Time

300

ns

tos

Data Input Set-Up Time

100

ns

Data Input Hold Time

100

ns

Symbol

tOH
Note 2: AC Input waveform specification lor lest purpose: t,. ,;; 20 ns, If ,;; 20 ns, I
Note 3: Clock input rise and lall times must nol exceed 5 ".S.

4-86

Min

Typ

= 1 MHz, 50% ± 10% duty cycle.

Max

Units

1.0

MHz

Connection Diagrams
Plastic Chip Carrier

Dual-In-Llne Package
~

Vu(OY)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1

Yo..
You (5V)

40

OUTPUT 18

!;

39

OUlPIIT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
DATA IN

5

38

10
11
12
13
14
15
16

37
36
35
34
33
32
31
30
29
2B
27

MM511348

26
25
24

17

16
19
20

23

22
21

0

OUTPUT 13

39

OUTPUT 23

OUTPUT 12

38

OUTPUT 24

OUTPUT 11

37

OUTPUT 25

OUTPUT 10

10

36

OUTPUT 26

OUTPUT 9

11

35

OUTPUT 27

H/c

12

OUTPUT 8

13

OUTPUT 7
OUTPUT 6

34

Hlc

33

OUTPUT 28

14

32

OUTPUT 29

15

31

OUTPUT 30

OUTPUT 5

16

30

OUTPUT 31

OUTPUT 4

17

CLOCK

MM58348V

OUTPUT 32

~SS}>8~~;::;~

TLlF/5601-2

~ ~ ~

Top View

d ~ ~ ~ 5

Q~~~

13§§

FIGURE 2

TL/F/5601-8

Top View
Order Number MM58348V
See NS Package Number V44A

Order Number MM58348N
See NS Package Number N40A

Functional Description
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58348 uses two signals,
DATA IN and CLOCK, with a format of a leading "1" followed by the 35 data bits, hence allowing data transfer without an additional signal. A block diagram of the MM58348 is
shown in Rgure 1.
Figure 2 shows the pinout of the MM58348 device, where
output 1 (pin 18) is equivalent to bit 1, (i.e., the first bit of

data to be loaded into the shift register following the start
bit). A logic "1" at the input will turn on the corresponding
display digit! segment! dot output.

A significant reduction in discrete board components can be
achieved by use of the MM58348, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied. However, Figure 38
and 3b show that this output impedance will remain constant for a fixed value of display Voltage.

+85"C
34.5

,

!24.5

+

14.5

o

~~-J

o

____-L____L-__-L____

100

200

4DD

3DQ

~

5DD

____~~T~)
6DD

TL/F/5601-3

FIGURE 3a. Output Impedance Off

1
.IE:
>

BDOOMAX
AT +85"C. VoIS= -lOY

1.0

4000 MAX
AT _40 c C, VoIS =-3DV

S·

.;- 0.5

oS

0.5

1

1.5

2

FIGURE 3b. Output Impedance On
4-87

TL/F/5601-4

Functional Description (Continued)
roes", followed by a "one" (start bit), followed by 35 "zeroes". This procedure will completely blank the display. It is
recommended to clear the driver at power on.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58348 is used to provide the
anode drive for a 32-digit 5 x 7 dot matrix vacuum fluorescent (VF) display. The grid drive in this example is provided
by another member of the high voltage display driver family,
namely the MM58341, which has the additional features of
a BLANKING CONTROL pin, a DATA OUT pin, and an ENABLE (external load signal) pin.

Figure 4 demonstrates the critical timing requirements be-

tween CLOCK and DATA iN for the MM58348.
In Figure 5, a start bit of logic "1" precedes the 35 bits of
data, each bit being accepted on the rising edge of CLOCK,
i.e., a "0"-"1" transition. At the 36th clock, a LOAD signal
is generated synchronously with the high state of the clock,
thus loading the 35 bits of the shift register into the latches.
At the low state of the clock, a RESET signal is generated,
clearing all bits of the shift register for the next set of data.
Hence, a complete set of 36 ciock pulses is needed to clear
(reset) the display driver at "power on" or any time, the
following flushing routine may be used. Ciock in 36 ''2e-

Timing Diagrams

... _~X ~:£'=t";;'1""
_
X'-_____

DATAIN J5011

TLlF/5601 -5

For the purpose of AC measurement. VIH

= 2.4V. VIL -

O.8V

FIGURE 4. Clock and Data Timings

ClK 35

START

START
CLK

ClK 1

CLK 33

ClK 2

ClK 34

CLK 35

ClK

CLOCK

DATA IN

n

lDAD
(INTERNAL)

-Jn I"-____________

RESET
(INTERNAL)

----Jn 1___________OfIl, _ - - - - - - - . . .

II~------.....

n

Vuo~

TYPICAL
DISPLAY
DUTPUT
~s

...._ _ _ __

~

..._ _ __

/

______________

~~-----------J

TLlF/5601-6

FIGURE 5. MM58348 Timings (Data Format)

4-88

Typical Application
32·01GIT MUIJIPlEXED
5 x 7 OOT MATRIX
VACUUM FWORESCENT
(VFI DISPLAY

I

~

2~~I!'-i

__ 3!,,!!1~__

MM58348
DISPLAY DRIVER
CLOCK 8

MM58341
DISPLAY DRIVER
DATAl t
CLOCK 1

DATAB

1

ENA8LE 1

I
MICROPROCESSOR

BLANK 1

DATA
OUT 1
TLlF/5601-7

FIGURE 6. Mlcroprocessor-Controlled Word Proceaaor

II

4-89

~National

~ Semiconductor

LM3909 LED Flasher/Oscillator
General Description

Fe,atures

The LM3909 is a monolithic oscillator specifically de'signed
to flash Light Emitting Diodes. By using the timing capacitor
for voltage boost, it delivers pulses of 2 or more volts to the
LED while operating on a supply of 1.SV or less. The circuit
is inherently self-starting, and requires addition of only a battery and capacitor to function as an LED flasher.
Packaged in an a-lead plastic mini-DIP, the LM3909 will operate over the extended consumer temperature range of
- 2S'C to + 70'C. It has been optimized for low power drain
and operation from weak batteries so that continuous operation life exceeds that expected from battery rating.

•
•
•
•
•
•

Application is made simple by inclusion of internal timing
resistors and an internal LED current limit resistor. As
shown in the first two application circuits, the timing resistors supplied are optimized for nominal flashing rates and
minimum power drain at 1.SV and 3V.
Timing capacitors will generally be of the electrolytic type,
and a small3V rated part will be suitable for any LED flasher
using a supply up to 6V. However, when picking flash rates,
it should be remembered that some electrolytics have very
broad capacitance tolerances, for example - 20% to
+100%.

Operation over one year from one C size flashlight cell
Bright, high clJrrent LED pulse
Minimum external parts
Low cost
Low voltage operation, from just over 1V to SV
Low current drain, averages under O.S mA during
battery life
• Powerful; as an oscillator directly drives an ao speaker
• Wide temperature range

Applications
• Finding flashlights in the dark, or locating boat mooring
floats
• Sales and advertiSing gimmicks
• Emergency locators, for instance on fire extinguishers
• Toys and novelties
• Electronic applications such as trigger and sawtooth
generators
• Siren for toy fire engine, (combined oscillator, speaker
driver)
• Warning indicators powered by 1.4V to 200V

Connection Diagram

Schematic Diagram

Dual-In-Llne Package

Typlcal1.5V Flasher

RLIM

,....--1

r---------,

v+

SLOW
RC
9•

•
3k
FAST

OUT

NC

RC
SLOW RC

TL/H17969-2

I

Top View

t - - - t ......~...- _ _ 1 1 _ -....
FAST RC

I

Order Number LM3909N
See NS Package Number N08E

8k

.....- .... 11-+-..

20.
3k

L. _ _ _ _ _ _ _ _ _ .J
TL/H17969-1

4-90

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation
500mW
V+ Voltage
6.4V

Operating Temperature Range

- 25·C to

+ 70·C
260·C

Lead Temperature (Soldering. 10 sec.)

Electrical Characteristics
Conditions
(Applications Note 3)

Parameter
Supply Voltage

Min

(In Oscillation)

Typ

Max
6.0

V

0.55

0.75

mA

1.0

1.3

1.15

Operating Current
Flash Frequency

300 p.F. 5% Capacitor

High Flash Frequency

0.30 p.F. 5% Capacitor

0.65

1.1

Units

Hz
kHz

Compatible LED Forward Drop

1 mA Forward Current

Peak LED Current

350 p.F Capacitor

45

mA

Pulse Width

350 p.F Capacitors at % Amplitude

6.0

ms

Typical Applications

2.1

1.35

V

(See applications notes on following page)
Triac Trigger

I
~

3.3

r-1:+
'"F

:

.".

:•

COM

15

:b·

b

1&

5

13

4

Provides 40 rnA. 10 "s pulses at about 8 kHz.
Triac gate may be pulse transformer isolated if
desired.

O.OI5"F

LM3909
Ik

I'

12

-I.4V FROM BATTERY OR
SOLAR CELL WITH s..F
BYPASS CAPACITOR. DRAIN
NDMINALL Y 5 mAo
TL/HI7969-3

4·91

II

Typical Applications (Continued)(See applications notes below)
Warning Flasher High Yoltage Powered

Typical Operating Conditions

V+

Y+

Nominal
Flash Hz

CT

Rs

RFB

Y+RANGE

SV
15V

2
2

400,..F
180,..F

1.5k
lk

5V-25V
13V-50V

l00V

1.7

180,..F

lk
3.9k
43k
lW

lk

85V-200V

LM3909

TUHf7969-4

1.5Y Flasher
0.7

.

0.6

/

C

.!
~

0.5

........J

/

0.4

c

LM3909

+

>

1.5V

,

0.3

i:

"

V

0.2
0.1

1.0

1.1

1.2

1.3

1.4

1.5

1.&

BATIERY VOLTAGE (V)
TUHI7969-6

Estimated Battery Life
(Continuous1.5Y Flasher Operation)

300~F

3V
TLfHf79&9-5

Type

Size Cell

Note: Nominal flash rete: 1 Hz.

M
C
D

Standard

Alkaline

3 months
7 months
1.3 years

Smonths
15 months
2.Syears

Note: Estima1es are mede from our tests and manufacturers
data. Condijions are fresh betteries and room tamperature. Clad
or "Ieak·proof" betteries are recommended for any application
of flve months or more. Nickel Csdmlum cells are not recommended.

APPUCATIONS NOTES
Note 1: All capacitors shown are electrolytic unless marked otherwise.
Note 2: Flash ra1es and frequencies assume a ± 5% capacitor tolerance. Electrolytics may vary - 20% to + 100% of their stated value.
Note 3: Unless noted, measurements above are made with a 1.4V supply, a 25"C ambient temparature, and an LED with a forward drop of 1.5V to 1.7V at 1 mA
forward current

Note 4: Occasionally a flasher circuij will fail to oecillate due to an LED defect that may be missed because ij only reduces light output 10% or so. Such LEOs can
be identified by a large increase in conduction between 0.9V and 1.2V.

4-92

Typical Applications (Continued) (See applications notes on previous page)
Minimum Power at 1.5V

3VFlaaher

+

LM3909

+

LM3909

-=-3V

I.SV

300~F

3V

TLlH17969-8

Note: Nominaillash rate: 1.1 Hz. Average lORAIN = 0.32 mAo

TLIHI7969-7

Note: Nominalilash rate: 1 Hz. Average lORAIN = 0.77 mAo

Faat Blinker

TRANSLUCENT

+

LM3BOB

O~CJ------'~~

UV

TLlHI7989-11

Note: Winking LED Inside. locates Ught in total darkness.

4

lk

TLIHI7969-9

Note: Nomineillash rate: 2.6 Hz. Average lORAIN = 1.2 mAo

4·93

Typical Applications (Continued) (See applications notes above)
Flashlight Finder

SHORT I-I FOR
SINGLE CELL LIGHTS
CONTACT STRIP, PASSES
(INSULATED) THROUGH
CASE BonOM

\
RING CONTACT ON
IULB ASSEMIL Y

TL/H17969-10

Note: LM3909, capacitor, and LED are installed in a white translucent cap on the flashlight's back end. Only one
contact strip (in addition to the case connection) is needed for flasher power. Drawing current through the bulb
simplifies wiring and causes negligible loss since bulb resistance cold is typically less than 20.

High Efficiency Parallel Circuit

4 Parallel LEOs

~

39

39
NSlS027 OR
NSL002 DR
NSLS024

~

39

~

39

0.

39

~

39

0.

39

+

I.SV

+

~

200

200

LM390g

LM390g

4

750

I.SV

39

4

1100iJF
3V

750

5000pF
3V

TUH/7969-12

Note: Nominal flash rate: 1.3 Hz. Average lORAIN

~

TL/HI7969-13

2 mAo

Note: Nominal flash rate: 1.5 Hz. Average IDRAIN

4·94

~

1.5 rnA.

Typical Applications (Continued) (See applications notes above)
1 kHz Square Wave
1.2
1.0

E

SYMMETRY
10k

D.2~F

r

~

CD

c

lMJ909

~

......

c
>

=>
=>

0.8
0.&
0.4

c

4

+

D.2

r- I-

i'-r-

I.SV

Z...

1 ...

TL/H17969-15

OUT

Nota: Output voltage through a 10k load 10 ground.

TL/H17969-14

"Buzz Box" Continuity and Coli Checker

Variable Flasher

~12-1&n

D

SPEAKER
NSL50Z1

I
I

+

LM3t09

1.5V

1&

TEST
PROBES

lk

LM3909

+
TUH17969-17
Note: Flash rate: 0 Hz-20 Hz.

1.5V

TUH17969-16
Note: Differences between shorts, ooils, and a few ohms of resistance can be

heard.

4-95

Typical Applications (Continued) (See applications notes above)
Incandescent Bulb Flasher

LED Booster

+6V

O.lpF

15
6

LM3909
LM3909

4

1.5Y

#41

75
TLlHI7969-1B

Note: High efficiency, 4 rnA drain. Continuous appearing light obtained by supplytng
short, high current, pulses (2 kHz) to LEOs with higher than battery voltage available.

TL/H/7969-19

Note: Flash rate: 1.5 Hz.

Emergency Lantern/Flasher
15

-

LM3908

+

~8V

TLlHI7969-20

Note: Nominal flash rate: 1.5 Hz.

4·96

~National

~ Semiconductor

LM3914 Dot/Bar Display Driver
General Description
The LM3914 is a monolithic integrated circuit that senses
analog voltage levels and drives 10 LEOs, providing a linear
analog display. A single pin changes the display from a
moving dot to a bar graph. Current drive to the LEOs is
regulated and programmable, eliminating the need for resistors. This feature is one that allows operation of the whole
system from less than 3V.

Much of the display flexibility derives from the fact that all
outputs are individual, OC regulated currents. Various effects can be achieved by modulating these currents. The
individual outputs can drive a transistor as well as a LEO at
the same time, so controller functions including "staging"
control can be performed. The LM3914 can also act as a
programmer, or sequencer.

The circuit contains its own adjustable reference and accurate 10-step voltage divider. The low-bias-current input buffer accepts signals down to ground, or V-, yet needs no
protection against inputs of 35V above or below ground.
The buffer drives 10 individual comparators referenced to
the precision divider. Indication non-linearity can thus be
held typically to '12%, even over a wide temperature range.

The LM3914 is rated for operation from O"C to + 70"C. The
LM3914N is available in an 18-lead molded (N) package.

Versatility was designed into the LM3914 so that controller,
visual alarm, and expanded scale functions are easily added
on to the display system. The circuit can drive LEOs of many
colors, or low-current incandescent lamps. Many LM3914s
can be "chained" to form displays of 20 to over 100 segments. Both ends of the voltage divider are externally available so that 2 drivers can be made into a zero-center meter.

•
•
•
•
•
•
•
•
•
•

The LM3914 is very easy to apply as an analog meter circuit. A 1.2V full-scale meter requires only 1 resistor and a
single 3V to 15V supply in addition to the 10 display LEOs. If
the 1 resistor is a pot, it becomes the LEO brightness control. The simplified block diagram illustrates this extremely
simple external circuitry.
When in the dot mode, there is a small amount of overlap or
"fade" (about 1 mV) between segments. This assures that
at no time will all LEOs be "OFF", and thus any ambiguous
display is avoided. Various novel displays are possible.

The following typical application illustrates adjusting of the
reference to a desired value, and proper grounding for accurate operation, and avoiding oscillations.

Features
Drives LEOs, LCOs or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 100 steps
Internal voltage reference from 1.2V to 12V
Operates with single supply of less than 3V
Inputs operate down to ground
Output current programmable from 2 mA to 30 rnA
No multiplex switching or interaction between outputs
Input withstands ± 35V without damage or false outputs
LEO driver outputs are current regulated, open-collectors
• Outputs can interface with TTL or CMOS logiC
• The internal 10-step divider is floating and can be referenced to a wide range of voltages

Typical Applications
OV to 5V Bar Graph Meter

r-....- ....- ....- ....- ....- ....- ....- ....- - - - - VLE •

:• ~r
I

f,N f

r

I

II

17

18

I.

1&

•

....L

It

LM3914

I

I

L

12

13

U.F " ' "

:

LEO
NO. 10
II

LE.

,"0.1

Note 1: Grounding method is typical of all uses.
The 2.2 p.F tantalum or 10 p.F aluminum electrolytic capacRor is needed illeeds to the LED supply are 6" or longer.

r~r r~r~(

y-

----.JI

2

y+
3

ALO

SIG

•

&

"HI

~

m

OUT

ADJ

I!...-

.v-&v

MODE

I

m

------~

I

7

~

~I

•

or UV-IIV
Rei Out V = 1.25 (1
12.5

ILED

3.131<

"'Fi1

SIGNAL
SOURCE

TUH/7970-1

4-97

+~)

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP (N)

Storage Temperature Range

1365mW

Supply Voltage

25V

Voltage on Output Drivers

25V

Input Signal Overvoltage (Note 3)

215'C
220'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

-100mVtoV+

Reference Load Current

+ 150'C
260'C

Plastic Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

±35V

Divider Voltage

- 55'C to

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)

10mA

Electrical Characteristics (Notes 1 and 3)
Parameter

I

I

Conditions (Note 1)

Min

I

Typ

I

Max

I

Units

COMPARATOR
Offset Voltage, Buffer and First
Comparator

ov:s: VRLO = VRHI:S: 12V,
ILED = 1 mA

3

10

mV

Offset Voltage, Buffer and Any Other
Comparator

OV:s: VRLO = VRHI :s: 12V,
ILED = 1 mA

3

15

mV

Gain (aILED/ aVIN)

IL(REF) ,= 2 mA, ILED = 10 mA

Input Bias Current (at Pin 5)

OV:s: VIN:S: V+ - 1.5V

Input Signal Overvoltage

No Change in Display

3

8
25

-35

mAlmV
100

nA

35

V

VOLTAGE-DIVIDER
Divider Resistance

Total, Pin 6 to 4

Accuracy

(Note 2)

8

12

17

kG

0.5

2

%

1.28

1.34

V

VOLTAGE REFERENCE
Output Voltage

0.1 mA :s: IL(REF) :s: 4 mA,
V+ = VLED = 5V

1.2

Line Regulation

3V:S: V+ :s: 18V

0.01

0.03

%IV

Load Regulation

0.1 mA :s: IL(REF) :s: 4 mA,
V+ = VLED = 5V

0.4

2

%

Output Voltage Change with
Temperature

O'C :s: TA :s:
V+ = 5V

+ 70'C, IL(REF) =

1 mA,

%

1

Adjust Pin Current

75

120

~
mA

OUTPUT DRIVERS
LED Current

V+ = VLED = 5V, IL(REF) = 1 mA

LED Current Difference (Between
Largest and Smallest LED Currents)

VLED = 5V

LED Current Regulation

2V:s: VLED:S: 17V

Dropout Voltage

7

10

13

0.12

0.4

ILED = 20mA

1.2

3

ILED = 2 rnA

0.1

0.25

ILED = 20mA

1

3

ILED = 2mA

ILED(ON) = 20 rnA, VLED = 5V,
aiLED = 2 rnA

mA

rnA

1,5

V

Saturation Voltage

ILED = 2.0 mA, IL(REF) = 0.4 rnA

0.15

0.4

V

Output Leakage, Each Collector '

(Bar Mode) (Note 4)

0.1

10

p.A

4-98

....
iii:

Electrical Characteristics (Note 1) (Continued)
Parameter

I

.......
(0)

CO

I

Conditions (Note 1)

Min

I

Typ

I

0.1

I

Max

I

Units

10

I

p.A

OUTPUT DRIVERS (Continued)
Output Leakage

I

(Dot Mode) (Note 4)

I
I

Pins 10-18
Pin 1

I
I

I
60

I

150

I
I

2.4

I

450

I

p.A

I

4.2

I

mA

SUPPLY CURRENT
Standby Supply Current
(All Outputs Off)

l

J

V+ = 5V, ILjREF) = 0.2 mA

I

I

I

I

V+ = 20V, Il(REF) = 1.0 mA
6.1
9.2
mA
Note 1: Unless olherwise staled, all specijications apply with the following conditions:
3 Voc '" V+ '" 20 Voc
VREF. VRHI. VRLO '" (V+ - 1.5V)
3 Vee '" VLED '" V+
OV '" VIN '" V+ - 1.5V
-0.015V '" VRLO '" 12 Vee
TA = +2SOC,IL(REF) = 0.2 rnA, VLEO = 3.0V, pin 9 connected to pin 3 (Bar Mode).
-0.015V '" VRHI '" 12 Voc
For higher power dissipations, pulse testing is used.
Note 2: Accuracy is measured referred to + 10.000 Vee at pin 6. wilh 0.000 Voc at pin 4. At lower full-scale voltages. buffer and comparator offset voltage may add
significant error.

Note 3: Pin 5 input current must be limHed to ±3 mAo Tha addition of a 39k resistor in series wilh pin 5 allows ± l00V signals wiIhout damaga.
Note 4: Bar mode resuns when pin 9 Is within 20 mV of V+. Dot mode resulla when pin 9 is pulled at least 200 mV below V+ or left open clrcuH. LED No.1 0 (pin 10

output current) is disabled if pin 9 is pulled 0.9V or more below VLED.
Note 5: Tha maximum junction temperature of tha LM3914 is 10crc. Devices must be derated for operation at elevated temperatures. Junction to arnbiantlherrnaJ
resistance is 5SOC/W for tha molded DIP (N packaga).

Definition of Terms
Accuracy: The difference between the observed threshold
voltage and the ideal threshold voltage for each comparator. Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.
Adjust Pin Current: Current flowing out of the reference
adjust pin when the reference amplifier is in the linear region.
Comparator Gain: The ratio of the change in output current
(lLEO) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.
Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.
Input Bias Current: Current flowing out of the Signal input
when the input buffer is in the linear region.

LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLEO) as
measured at the current source outputs. As the forward voltage of an LED does not change Significantly with a small
change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Une Regulation: The average change in reference output
voltage over the specified range of supply VOltage (V+).
Load Regulation: The change in reference output voltage
(VREF) over the specified range of load current (IL(REF)'
Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error when the voltage across
the internal voltage divider is small. Specified and tested
with pin 6 voltage (VRHI) equal to pin 4 voltage (VRLO).

III

4-99

Typical Performance Characteristics
Supply Current vs
Temperature

.. ...

.---

8.0

~

e
1

•.1

Operating Input Bias
Current vs Temperature

10.20
v+IPlN3I-21V

•.2 f--rTE'REFERENCELOA1o_
CjRREj"mA

!

I
51

o

75

i!
c

;
~

"~3

I.

18

1ft . - - , - - - - , - - - , - - - ; - - ,

!

1.0

1--1--l--l--ho9tj

0.8

1----1--+

0.6

1--l--l-7l;JoC'

"0-$ u f--f--zlP"-+--+---1

~

~G

~

15

"

1.0

10

Input Current Beyond
Signal Range (Pin 5)

V'~20J

I

OIVIDER V' 10V

C
.!

-

TJ,J

rr

2.

I

1

ill

1"
!

.
n

c

0:

I

30

1.8
0.5

i

~

)~'

=

-1

-2

~

~A'''C

7 f

10

~

1.0

:c

~

"'"

;:

20

1&

25

i

20

30

~
':l

1.12

I

! 1.01
e

7

LM311

UI

DIVID~R

~

0.8
0.6

0.4
0.2
1.

1.110

~ D.l8

"'8-25

I--

-:7

25

OIVIOER PARALLEL
WITH STABLE
1k RESISTOR

/v

C 11.6

V

:;

.!

TA-Z·'Y

~

i

i

V

2A

o

D.5 1.1 1.5 U

10

Z.. 3.0 U U

50

TEMPERATUAE rc)

15

110

I•

20

Output Characteristics

-0.5

10

~EFERJEO TO ~OSlTIV~_

""=5V
TA -25'C

lmA

~H""

/

SUPPLY VOLTAGE

~""

I

~DI""

'~
-

NEGATIVE COMMON,MOOELIMIT INCLUDES GRDUNO
20

40

TEMPERATURE rei

80

a

LED SUPPLY VOLTAGE (VI

12

_

.I

2.3

I'

i
~ -1.5

I

2.

11.1

~ -2.0
z

L.I': L_--

20

I.

LED Driver Current
Regulation

v+

~ -1.0

A

1.04
:: 1.02

;

~

"

rei

1.2

Common-Mode Limits

I

1.1'

50

I .•

REFERENCE LOAD CURRENT ImAI

Total Divider Resistance
vs Temperature

Z5

S

lU

zo

o

40

~

'i

LED CURRENT (rnA)

,/

10

I

-3
...0 -30 -20 -10 0

1.4

s:

LED Current vs
Referen.ce Loading

1.5

"j

I

LED CURRENT (mAl

TEMPERATURE rCI

I

LED Driver Saturation
Voltage

-'"~
:!

0.2

0 ' - - - " -.......- - ' - - - ' - - - - '
51

;;;

~

,,0:

25

j'

1.21

TEMPERATURE

f--f--f--+--t---1

~'"

16

-2&

:;

1.21 -tADJ"NGRDUNDJ-

75

1.2

~fi
~~
;! :l

"- ~

I.

50

!!!!!

"'''
~

84
12

25

LED Current-Regulation
Dropout

;0

s:

1

TEMPERATURE rCI

Reference Adjust Pin
Current vs Temperature

~

~

-IREF AD(USTEDTO 10V _

!;l 1.29

I

5.0

.........

10.01 ~

~

~
>

TEMPERATURE I"CI

..~

::!

~

26

;'"

10.18 ~

~

I

e>

!

~

V"5V-

SA

I

-.....

":i,'OV

;
0:

Reference Voltage vs
Temperature

80

J

IL(REFI-

~IIO ""

I

V
U

D.4

0.8

...

1.0

OUTPUT VDL TAOEIYI

TL/H17970-2

4-100

r-----------------------------------------------------------------------------, !!I:
Block Diagram (Showing Simplest Application)
....~
~

oIiIo

LED

, - - - - - u.;39i4 - - - -- - ,

I

COMPARATOR
1 OF 10

v+

I
10

lk

lk

lk

lk

I
OUT 7

lk

REF

THIS LOAD
DETERMINES
LED
BRIGHTNESS

+

REFERENCE
VOLTAGE
SOURCE

1.2&V
lk

-

REF
ADJ

I

lk

8

-I
I
I

lk

V+~3

lk

I
I
RLO I 4

Ik

v+

FROM
PIN II

I CONTROLS
TYPE OF
9

DISPLAY, BAR

OR SINGLE
I LED
I

V-~
I'::"

I
I
L. _ _ _ _ _ _ _ _ _ _ _ _ _ .J

-

TL/H17970-3

4-101

....
:i

~ r---------------------------------------------------------------------------~

~

Functional Description
The simplifed LM3914 block diagram is to give the general
idea of the circuit's operation. A high input impedance buffer
operates with Signals from ground to 12V, and is protected
against reverse and overvoltage signals. The signal is then
applied to a series of 10 comparators; each of which is biased to a different comparison level by the resistor string.
In the example illustrated, the reSistor string is connected to
the internal 1.25V reference voltage. In this case, for each
125 mV that the'input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are 1.5V below V+ and no less than V-. If an expanded
scale meter display is desired, the total divider voltage can
be as little as 200 mY. Expanded-scale meter displays are
more accurate and the segments light uniformly only if bar
mode is used. At 50 mV or more per step, dot mode is
usable.

spite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signalli can lead to a number of novel displays or -ways of indicating input overvoltages, alarms, etc.
MODE PIN USE
Pin 9, the Mode Select input controls chaining of multiple
LM3914s, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).
Dot Display, Single LM3914 Driver: Leave the Mode Select pin open circuit.

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin B) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:
VOUT

=

VREF (1

IL!

+ :~) + IADJ R2

Mode Pin Functional Description

I
I

LM3914

r

Dot Display, 20 or More LEOs: Connect pin 9 of the first
driver in the series (i.e., the one with the lowest input voltage comparison pOints) to pin 1 of the next higher LM3914
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30, 40, or more LED displays. The last LM3914 driver in the chain will have pin 9
wired to pin 1'1. All previous drivers should have a 20k resistor in parallel with LED No.9 (pin 11 to VLEO).

This pin actually performs two functions. Refer to the simplified block diagram below.

REF_ _ ADJ
REF _ _ ~
OUT

VOUT

7

L

...,

8

Block Diagram of Mode Pin Function

9

OUTPUT NO, 9

VREF

•=.J

11

IADJ
CONTROLLED DRIVE {
(FROM COMPARATORS)

..........

~+---+TL/H/7970-4

Since the 120 /J-A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V+ and load changes.
CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant de-

4-102

Mode Pin Functional Description (Continued)
DOT OR BAR MODE SELECTION

ticeable when using high-efficiency LEOs in a dark environment. If this is bothersome, the simple cure is to shunt LED
No. 11 with a 10k resistor. The 1V IR drop is more than the
900 mV worst case required to hold off LED No. 10 yet
small enough that LED No. 11 does not conduct significantly.

The voltage at pin 9 is sensed by comparator C1, nominally
referenced to (V+ - 100 mV). The chip is in bar mode
when pin 9 is above this level; otherwise it's in dot mode.
The comparator is designed so that pin 9 can be left open
circuit for dot mode.
Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than
20 mV below V+ for bar mode and more than 200 mV below V+ (or open circuit) for dot mode. In most applications,
pin 9 is either open (dot mode) or tied to V+ (bar mode). In
bar mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

OTHER DEVICE CHARACTERISTICS
The LM3914 is relatively low-powered itself, and since any
number of LEOs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEOs OFF) is 1.6 mA (2.5 mA max). However, any reference
loading adds 4 times that current drain to the V + (pin 3)
supply input. For example, an LM3914 with a 1 mA reference pin load (1.3k), would supply almost 10 mA to every
LED while drawing only 10 mA from its V+ pin supply. At
full-scale, the IC is typically drawing less than 10% of the
current supplied to the display.
The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and often an annoying flicker.
An "overlap" is built in so that at no time between segments
are all LEOs completely OFF in the dot mode. Generally 1
LED fades in while the other fades out over a mV or more of
range (Note 2). The change may be much more rapid between LED No.1 0 of one device and LED No.1 of a second
device "chained" to the first.

DOT MODE CARRY
In order for the display to make sense when multiple
LM3914s are cascaded in dot mode, special circuitry has
been included to shut off LED No. 10 of the first device
when LED No. 1 of the second device comes on. The connection for cascading in dot mode has already been described and is depicted below.
As long as the input signal voltage is below the threshold of
the second LM3914, LED No. 11 is off. Pin 9 of LM3914
No. 1 thus sees effectively an open circuit so the chip is in
dot mode. As soon as the input voltage reaches the threshold of LED No. 11, pin 9 of LM3914 No. 1 is pulled an LED
drop (1.5V or more) below VLED. This condition is sensed by
comparator C2, referenced 600 mV below VLED. This forces
the output of C2 low, which shuts off output transistor Q2,
extinguishing LED No. 10.

The LM3914 features individually current regulated LED
driver transistors. Further internal circuitry detects when any
driver transistor goes into saturation, and prevents other circuitry from drawing excess current. This results in the ability
of the LM3914 to drive and regulate LEOs powered from a
pulsating DC power source, i.e., largely unfiltered. (Due to
possible oscillations at low voltages a nominal bypass capaCitor consisting of a 2.2 ",F solid tantalum connected from
the pulsating LED supply to pin 2 of the LM3914 is recommended.) This ability to operate with low or fluctuating voltages also allows the display driver to interface with logic
Circuitry, opto-coupled solid-state relays, and low-current incandescent lamps.

VLED is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 ",A) that is diverted
from LED No.9 does not noticeably affect its intenSity.
An auxiliary current source at pin 1 keeps at least 100 ,..A
flowing through LED No. 11 even if the input voltage rises
high enough to extinguish the LED. This ensures that pin 9
of LM3914 No.1 is held low enough to force LED No.1 0 off
when any higher LED is illuminated. While 100 ",A does not
normally produce significant LED illumination, it may be no-

Cascading LM3914s In Dot Mode

••

¥UD

u+
LII3I14

NO.1

IIODE

TLlHI7970-6

4-103

~
..-

~----------------~--------------------------------------------------~

=

~

Typical Applications

(Continued)

Zero-Center Meter, 20-8egment
.~

430(10

•

'ii7

'ii7
LED
NO.1

~~

~

~~

'ii7

~~

'* '*

~

7i7

-~

n
-f-

-==

~

~,

--;18~17

~~

-==

..,~

.~
~

7i7 'ii7 ~
~~ ~~ ~~

....

'* '*

--=Iii"

11&

14

~

(i2

rl3

N

U

•

7ir
~~

• f- LED
-.!O.II
II

LM3914
y+-

II

-d:-

.

•~27
~ ~Ik*
~
'"

"'"'"-

Z

I

RLO
4

SIS

RHI

REF OUT REF ADJ MODE

l!.-...

5

1\

• 120
LM337 .:

3

7

.

• •

760

I~F**

)~

-o:1.3V

-Jv
IVDC

N
I--'
LED N0.11'

I-'~ ~

N

N

~~ ~~

N
~,
~

N

N
~,

~..

.r-

.~

N

N

.~

~~

13

12

~

N
~~

-f-

N

~~LED
NO. 21

18

17

16

15

14

II

10

LM3914
y+L-JI

2

3

sla

RLa
4

5

RHI

REF OUT REF ADJ MODE
8

I!.- 7

•

.:Uk
~

INPUTSIO
TL/H/7970-7

4·104

r----------------------------------------------------------------------,r

i:
w

Typical Applications (Continued)

CD
.....
.Do.

Expanded Scale Meter, Dot or Bar

"This application illustrates that the LED supply
needs practically no filtering

C8Hl/nlllon: With a precision meter between pins
4 and 6 adjust RI for voltage Vo of 1.20V. Apply
4.94V to pin 5, and adjust R4 until LED No. 5 just
lights. The adjustments are non-interacting.

TLlH17970-8

Application Example:
Grading 5V Regulators
Highest No.
LED on

10
9
8
7
6

Color

VOUT(MIN)

Red
Red
Yellow
Green
Green

5.54
5.42
5.30
5.18
5.06

5V
5
4
3
2
1
j

4-105

Green
Green
Yellow
Red
Red

4.94
4.82
4.7
4.58
4.46

III

Typical Applications

(Continued)

"Exclamation Point" Display
/1/

/1/

/1/

/1/

/1/

/1/

/1/

/1/

/1/

,&1
LED
NO. 10
II

'4

II

17

12

13

"

10

LM3914

W~~--------

____,.

~

BIG IN ...-'VII'Y---....-

3V:rt..
OV
.

1.&10

1 kHz pulse rate at 10% dutv cvcle

...
~O.OhF

1.6k

LEOs light up as illustrated with the upper I~ LED
indicating the actual input voltage. The display
appears to increasa resolution and provides an
analog indication of overrange.
TL/H17970-9

Indicator and Alarm, Full-Scale Changes Display from Dot to Bar
Y+3V

/1/

/1/

/1/

/1/

/1/

/1/

11/

11/

III

/1/
27k

LED

LED

NO.1

NO. 10
II

17

II

IS

I'

13

12

II

121

16k

10

LM3914

'The input to the Dot·Bar S~ch may be taken
from cathodes of other LEOs. Display will change
to bar as soon as the LED so selected begins to
light.
TLlH17970-10

4·106

r-----------------------------------------------------------------------------~ ~

Typical Applications

!!II:

...~

(Continued)

Bar Display wlh Alarm Flasher

A

YLED 5Y
100

N
~,

N
~r

-

LED
NO.1

18

N

N

N

~,

~,

~,

~

l-

I-

17

16

N
~,

15

14

N

N

N

N

~~

~~

~~

~t

13

Rl
lk

LED

~

12

10

11

;::,
+

LM3914

---..Jl

-¥

y+

RLD

3

-¥

SIG

15

RHI

REF OUT REF ADJ MODE
7
9

-¥

6

479
Uk

-...

Full-scale causes the full bar display to flash. If
.
the Junction of RI and CI IS connected to a dIfferent LED cathode, the display will flash when
that LED lights, and at any higher input signal.

. .

.

TLlH17970-11

Adding Hysteresis (Single Supply, Bar Mode Only)
y+
(5VI

1

I"F~
N
~,

LED
NO.1

N

/lJ

/lJ

/lJ

~~ ~ ~ ~ ~ ~~
lB

17

lB

/lJ

~~

15

14

YLED
OUT

/lJ

~~

ADJ

11

/lJ

~~
12

13

~

LM337H

t ~,
!IJI

!IJI

I

IN

.. LEO
NO. 10

11

10

LM3914
V-

----11

-:!!

y+
3

RLO
4

SIG

15

RHI

REF OUT

L!....- 7

REF
ADJ

•

MODE
I
I"-

111'
1.211
2.7
CARlON
10
Hysteresis is 0.5 mV to 1 mV

4-107

- ..

TLlHI7970-12

Typical Application

(Continued)

Operating with a High Voltage SUpply (Dot Mode Only)
The LED currents are approximately 10 rnA, and
!he LM3914 outputs oparate in saturation for
minimum dissipation.

48V

3.9k
1W

,.....

11k
,.

N

N

N

N

N

N

N

N

N

N

N
'This point Is partially regulated and decreases in
voltage with temparature. Voltage requirements
of the LM3914 also decrease w~h temparature. '''''''

12'

TLlH17970-13

20-Segment Meter with Mode Switch

·The exact wiring arrangement of this schematic

N

N

~F

~r

,,.

N

,r ~ r
N

,

1

N

N

~

LED
lifO. 1

N

~~

N

N

N

12

11

,.

~ ~ ~ ~ ~ rrUD
110.10

shows the need for Mode Select (pin 9) to sense
the V+ voltage exactly as ~ appears on pin 3.

11

17

II

15

13

14

,

LM3914

v'

L-..Jl

N
~r

N
~r

-¥

3

, r , ,.
N

SI.

"LD

•

*
~

r

•

..

" 'OJ
"..

OUT

MODE

•

;JV ~
1.111*

*

N

N

"HI

N
~

r

N

,,.

N

,r

N

,,.N

13

12

11

10

.. ..•

MODE

"

LED
NO. 11

LEG
NO. 21
11

]-

-~~

••

17

16

15

14

W
LM3914

,

v1

V·
3

"LD

":'

•

SI.

•

SIU: IV-UV

"HI

", "

OUT

I!-

ADJ

uv

•

Uk*
.~

'Programs LEOs to lOrnA

4-108

Tl/H/7D70-14

Application Hints
Three of the most commonly needed precautions for using
the LM3914 are shown in the first typical application drawing (see page 9-108) showing a OV-5V bar graph meter.
The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from Signal sources, reference ground and bottom of the resistor string (as illustrated) to a single point
very near pin 2 is the best solution.

NON-INTERACTING ADJUSTMENTS FOR EXPANDED
SCALE METER (4.5V to 5V. Bar or Dot Mode)
This arrangement allows independent adjustment of LED
brightness regardless of meter span and zero adjustments.
First, VI is adjusted to 5V, using R2. Then the span (voltage
across R4) can be adjusted to exactly 0.5V using R6 without
affecting the previous adjustment.
R9 programs LED currents within a range of 2.2 mA to
20 mA after the above settings are made.

Long wires from VLED to LED anode common can cause
oscillations. Depending on the severity of the problem
0.05 p.F to 2.2 p.F decoupling capacitors from LED anode
common to pin 2 will damp the circuit. If LED anode line
wiring is inaccessible, often similar decoupling from pin 1 to
pin 2 will be sufficient.

Greatly Expanded Scale (Bar Mode Only)
RLO

REF
OUT

RHI

REF
ADJ

~-~~-~~7-~

If LED turn ON seems slow (bar mode) or several LEOs light
(dot mode), oscillation or excessive noise is usually the
problem. In cases where proper wiring and bypassing fail to
stop oscillations, V+ voltage at pin 3 is usually below suggested limits (see Note 2, page 9-108). Expanded scale meter applications may have one or both ends of the internal
voltage divider terminated at relatively high value resistors.
These high-impedance ends should be bypassed to pin 2
with at leest a 0.001 p.F capacitor, or up to 0.1 ,...F in noisy
environments.

... RI

_

~ 100

-

PINS OF
LM3914

'" 1%
~ R2
"'-~~.<250

Vl"I.IV

I

1

Power diSSipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEOs
programmed to 20 mA the driver will diSSipate over 600 mW.
In this case a 7.50 resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 ,...F solid tantalum capacitor
to pin 2 of the LM3914.

T

OhF
.

Turning OFF of most of the internal current sources is accomplished by pulling positive on the reference with a current source or resistance supplying 100 /LA or so. Alternately, the Input Signal can be gated OFF with a transistor
switch.

~ R3
200
1%

~

•

R5
100

'" R4
'" 15

VI

[10 R6

909
1%

-:!::TUH17970-15

ADJUSTING LINEARITY OF SEVERAL STACKED
DIVIDERS

Other special features and applications characteristics will
be illustrated in the following applications schematics.
Notes have been added in many cases, attempting to cover
any special procedures or unusual characteristics of these
applications. A special section called "Application Tips for
the LM3914 Adjustable Reference" has been included with
these schematics.

Three internal voltage dividers are shown connected in series to provide a 30·step display. If the resulting analog meter is to be accurate and linear the voltage on each divider
must be adjusted, preferably without affecting any other adjustments. To do this, adjust R2 first, so that the voltage
across R5 is exactly 1V. Then the voltages across R3 and
R4 can be independently adjusted by shunting each with
selected resistors of 6 kO or higher resistance. This is possible because the reference of LM3914 No.3 is acting as a
constant current source.

APPLICATION TIPS FOR THE LM3914 ADJUSTABLE
REFERENCE
GREATLY EXPANDED SCALE (BAR MODE ONLY)

The references associated with LM3914s No.1 and No.2
should have their Ref Adj pins (pin 8) wired to ground, and
their Ref Outputs loaded by a 6200 reSistor to ground. This
makes available similar 20 mA current outputs to all the
LEOs in the system.

Placing the LM3914 internal resistor divider in parallel with a
section (""2300) of a stable, low resistance divider greatly
reduces voltage changes due to IC resistor value changes
with temperature. Voltage VI should be trimmed to 1.1 V first
by use of R2. Then the voltage V2 across the IC divider
string can be adjusted to 200 mV, using R5 without affecting
VI. LED current will be approximately 10 mA.

If an independent LED brightness control is desired (as in
the previous application), a unity gain buffer, such as the
LM310, should be placed between pin 7 and R1, similar to
the previous application.

4-109

•

.... r---------------------------------------------------------------------------------,
~

~

~

Application Hints (Continued)

Non-Interacting Adjustments for Expanded Scale Meter (4.5V to 5V, Bar or Dot Mode)
REF

OUT

RB
Uk

REF
AOJ

10V

Rl
10k

R9
20k
LED
BRIGHTNESS

R4

-

523
C.5V
R5

4.32k
1%

R6
500
TL/H17970-16

Adjusting Linearity of Several Stacked Dividers

Other Applications

RI
549

_ .. ", [

""" '"

R2

•
•
•
•
•
•
•
•

"Slow"-fade bar or dot display (doubles resolution)
20-step meter with single pot brightness control
10-step (or multiples) programmer
Multi-step or "staging" controller
Combined controller and process deviation meter
Direction and rate indicator (to add to-DVMs)
Exclamation point display for power saving
Graduations can be added to dot displays. Dimly light
'
every other LED using a resistor to ground
• Electronic "meter-relay"-display could be Circle or
semi-circle
• Moving "hole" display-indicator LED is dark. rest of
bar lit
• Drives vacuum-fluorescent and LeOs using added passive parts

o..:~'_%__

200
...._ .

{

,..,," ,{0-------..
TUHI7970-17

4-110

r!I:
w

..

Connection Diagrams

CD
.....

Dual-In-Llne Package
Plastic Chip Carrier Package
lB

....... ....... '"~
N

+

I

> >

DIVIDER (LOW END)

Q

Q

LED NO.1

Q

4

17

v18

SIGNAL INPUT

5

17

6

16

LEO 6

Nlc

7

15

LE07

REFERENCE OUTPUT

8

14

LEO 8

LED NO.3

v+

LED 4

DIVIDER (HIGH END)

LED NO.2

DIVIDER
(LOW ENOl

LEO 5

SIGNAL INPUT
DIVIDER 6
(HIGH ENOl
REFERENCE OUTPUT

~a

z

!d ~ '"
...... ....... ...... fl...
-c

'"

11 LED ND. 9

REFERENCE ADJUST

Q

10

III

MODE SELECT

~

LED NO.l0

0
::IE

TL/H17970-18

TLlH/7970-19

Top View

Top View

Order Number LM3914V
See NS Package Number V20A

Order Number LM3914N
See NS Package Number N18A

4-111

~
.-

~

r------------------------------------------------------------------------,
~National

~ Semiconductor

LM3915 Dot/Bar Display Driver
General Description
The LM3915 isa monolithic integrated circuit that senses
analog voltage levels and drives ten LEOs, LCOs or vacuum
fluorescent displays, providing a logarithmic 3 dB/step analog display. One pin changes the display from a bar graph to
a moving dot display. LED current drive is regulated and
programmable, eliminating the need for current limiting resistors. The whole display system can operate from a single
supply as low as 3V or as high as 25V.
The IC contains an adjustable voltage reference and an accurate ten-step voltage divider. The high-impedance input
buffer accepts signals down to ground and up to within 1.5V
of the positive supply. Further, it needs no protection
against inputs of ± 35V. The input buffer drives 10 individual
comparators referenced to the precision divider. Accuracy is
typically better than 1 dB.
The LM3915's 3 dB/step display is suited for signals with
wide dynamic range, such as audio level, power, light intensity or vibration. Audio applications include average or peak
level indicators, power meters and RF signal strength meters. Replacing conventional meters with an LED bar graph
results in a faster responding, more rugged display with high
visibility that retains the ease of interpretation of an analog
display.
The LM3915 is extremely easy to apply. A 1.2V full-scale
meter requires only one resistor in addition to the ten LEOs.
One more resistor programs the full-scale anywhere from
1.2V to 12V independent of supply voltage. LED brightness
is easily controlled with a single pot.

The LM3915 is very versatile. The outputs can drive LCOs,
vacuum fluorescents and incandescent bulbs as well as
LEOs of any color. Multiple devices can be cascaded for a
dot or bar mode display with a range of 60 or 90 dB.
LM3915s can also be cascaded with LM3914s for a linear/
log display or with LM3916s for an extended-range VU meter.

Features
3 dB/step, 30 dB range
Drives LEOs, LCOs, or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 90 dB
Internal voltage reference from 1.2V to 12V
Operates with Single supply of 3V to 25V
Inputs operate down to ground
Output current programmable from 1 mA to 30 mA
Input withstands ±35V without damage or false outputs
Outputs are current regulated, open collectors
Directly drives TTL or CMOS
The internal 10-step divider is floating and can be referenced to a wide range of voltages
The LM3915 Is rated for operation from O"C to + 70"C. The
LM3915N is available in an 18-lead molded DIP package.

Typical Applications
OV to 10V Log Display

r-

3V ';VLED .;v'

I

Cl

I
LED
I NO.1
I
I

/1/

/1/

/1/

/1/

/1/

/1/

17

18

I
I
IL _____

16

15

14

v,

v2

3

RLO

SIG

4

5

v'

ILED ~

""'R1 +

/1/

13

12

11

10

Note 1: Capacilor Cl Is required H leads 10 Ihe LED supply are S" or longer.
Note 2: Circuil as shown is
wired lor dol mode. For bar
mode, connecl pin 9 10 pin 3.
VLED must be kept below 7V or
dropping resistor should be
used 10 IImR Ie power dlssipalion.
TLlH/5104-1

12V TO 20V

12.5V

/1/

LM3916

OR 10p.F'T"
ALUMINUM
ELECTROLYTIC

~ 1.25V (1

/1/

LED
NO.l0

TANT~~~~...L

VREF

/1/

+1*) +

R2x80"",,

VREF
2.2 kG

4-112

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP(N)
1365mW
Supply Voltage
25V
Voltage on Output Drivers
25V

Input Signal Overvoltage (Note 3)

±35V
-100mVtoV+

Divider Voltage
Reference Load Current
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

10mA
- 55'C to + 150'C
260'C

Electrical Characteristics (Notes 1 and 3)
Parameter

I

I

Conditions (Note 1)

Min

I

I Typ I

Max

3

10

mV

3

15

mV

Units

Comparators
Offset Voltage, Buffer and First
Comparator

OV S; VRLO = VRHI
ILED = 1 mA

S;

12V,

Offset Voltage, Buffer and Any Other
Comparator

OV S; VRLO = VRHI
ILED = 1 mA

S;

12V,

=

Gain (1lILED/IlVIN)

IL(REF)

Input Bias Current (at Pin 5)

OV

Input Signal Overvoltage

No Change in Display

VIN

S;

2 mA, ILED
S;

=

3

10 mA

(V+ - 1.5V)

mA/mV

8
25

-35

100

nA

35

V

Voltage-Divider
Divider Resistance

Total, Pin 6 to 4

Relative Accuracy (Input Change
Between Any Two Threshold POints)

(Note 2)

Absolute Accuracy at Each Threshold Point

(Note 2)
VIN
VIN
VIN
VIH

=
=
=
=

16

28

36

kO

2.0

3.0

4.0

dB

-3, -6 dB

-0.5

+0.5

dB

-9dB

-0.5

+0.65

dB

-12, -15, -18dB

-0.5

+1.0

dB

-21, -24, -27dB

-0.5

+1.5

dB

1.28

1.34

V

0.D1

0.03

%IV

0.4

2

%

Voltage Reference
Output Voltage

0.1 mA S; IL(REF) S; 4 rnA,
V+ = VLED = 5V

Line Regulation

3V

Load Regulation

0.1 mA S; IL(REF) S; 4 rnA,
V+ = VLED = 5V

Output Voltage Change with Temperature

O'C
V+

S;

V+

S;

=

S;

1.2

18V

TA S; + 70'C, IL(REF)
VLED5V

Adjust Pin Current

=

1 rnA,

75

4·113

%

1
120

,..A

Electrical Characteristics (Note 1) (Continued)

I

Parameter

I

Conditions (Note 1)

Min

I

Typ

I

Max

I

Units

Output Drivers

= 5V, IUREFl = 1 mA
= 5V, IlED = 2 mA
= 5V, ILED 20 rnA

LED Current

V+ = VlED

LED Current Difference (Between Largest
and Smallest LED Currents)

VlED
VLED

LED Current Regulation

2V:S: VLED

:s: 17V, IlED
ILED

IlED(ON) = 20 mA
ailED = 2 rnA

Dropout Voltage

@

7

= 2 mA
=

VLED

20 rnA

=

IlED

Bar Mode (Note 4)

Output Leakage
Pins 10-18
Pin 1

Dot Mode (Note 4)

13

mA

0.4

rnA

1.2

3

rnA

0.1

0.25

mA

1

3

mA

1.5

V

5V,

= 2.0 mA, IL(REF) = 0.4 rnA

Saturation Voltage
Output Leakage, Each Collector

10
0.12

60

0.15

0.4

V

0.1

10

",A

0.1

10

",A

150

450

",A

2.4

4.2

rnA

6.1

9.2

Supply Current
Standby Supply Current
(All Outputs Off)

V+
V+

= +5V, Il(REF) = 0.2 rnA
= + 20V, IL(REF) = 1.0 mA

mA
Note 1: Unless otherwise stated. all specHlcations apply wHh the following condHlons:
3 Vee ,;; V+ ,;; 20 Vee
-0.015V ,;; VRLO ,;; 12 Vee
TA = 25'C, IL{REF) = 0.2 mAo pin 9 connected to pin 3 (bar mode).
3 Vee ,;; VLEO ,;; V+
VREF. VRHIo VRLO ,;; ty+ - 1.5V) For higher power dissipations. pulse testing is used.
-0.015V ,;; VRHI ,;; 12 Voc OV ,;; VIN ,;; V+ - 1.5V
Note 2: Accuracy is measured referred to 0 dB = + 10.000 Voc at pin 5, wHh + 10.000 Voc at pin 6. and 0.000 Vee at pin 4. At lower full scale voltages. buffer
and comparator offset voltage may add significant error. See table for thrashold voltages.
Nota 3: Pin 5 input current must be IimHed to ±3 mAo The addition of a 39k resistor in series with pin 5 allows ±1OOV signals wHhout damage.
Nota 4: Bar mode results when pin 9 Is within 20 mV of V+. Dot mode results when pin 9 Is pulled at least 200 mV below V+. LED 11 10 (pin 10 output current) is
disabled if pin 9 is pulled 0.9V or more below VLEDNota 5: The maximum junction temperature of the LM3915 is l00'C. Devices must be derated for operation at elevated temperatures. Junction to ambient thermal
resistance Is 55'C/W for the molded DIP (N package).
THRESHOLD VOLTAGE (Note 2)
Output

dB

Min

Typ

Max

Output

dB

Min

Typ

Max

1
2
3
4
5

-27
-24
-21
-18
-15

0.422
0.596
0.841
1.189
1.679

0.447
0.631
0.891
1.259
1.778

0.531
0.750
1.059
1.413
1.995

6
7
8
9
10

-12
-9
-6
-3
0

2.372
3.350
4.732
6.683
9.985

2.512
3.548
5.012
7.079
10

2.819
3.825
5.309
7.498
10.015

4-114

Typical Performance Characteristics
Supply Current vs
Temperature
6.0

'"0:

.e

5.6

.!
>-

5.4

"
...'"'"=>

5.2 - r T E '

>

y+ (PI. 3)' 21V

-.....

~'OV
Y+'5V-

>

~

i

1

I
50

75

25

TEMPERATURE ("C)

.3

86
B4

,
"

~I'-...

z

82

~

80

.....
~

78

z

~

'"

76

~
~
~

'"

-25

25

'"
~~
"''''
~§

1.4

:!~
~~

0.8

~;

!:;'"

,

~m

",,,,

~3

75

0.2

o

100

Input Current Beyond
Signal Range (Pin 5)

I I I
C
.!

I-

cr

TJ70J

1.5

30

1.0

25

D.6

>-

is

~

I..

!!i

-1

!i

C
.!

"
'"
ill

,r

!;;

~

c

;;~

-2

-3

~

rI

10

20

30

~_
~

10

15

20

26

S

-

V/

5

1.0

TA"7D"yj

0.8

/.

0.6

V

0.4
0.2

o

K:T-

V
......
~

o

10

16

LED Current vs
Reference loading

LED Driver Current
Regulation
./

11.5

~

20

26

,--,--,--,--r---.

V

20
TA=26°C

..
m

V

"c

'"
ill

16

/

10

o

40

C.!I

TA=O"C-

RE~ERENCl LOADJURRE~T =-:~
Z

LED CURRENT (mAl

o

..
!!i

1/

IrA=D"C

-40 -30 -20 -10 0

1.2

LED CURRENT (mA)

!;;

~
~

1.4 _

-

>
~

o

TEMPERATURE ("C)

.,

w

;

0.4

1.6

~
Z.

TA'7~~

0.6

75

LED Driver Saturation
Voltage

i0:

~

.tI

1.0

5D

25

1.2

"'>-

50

Y+-20V
DIVIDER V· 10V

1.21

TEMPERATURE rei

LED Current-Regulation
Dropout

C

0:

~
s

1.28

75

50

~

~

1.29

TEMPERATURE ("C)

Reference Adjust Pin
Current vs Temperature

i

lD.OO

!

1- mAl

25

ill

~

I

5.0

I - - I - - t - - - - j - - - - j - - - - j 10.10

~

REFERENC."LOA~_
RREN

Cj

~

Reference Voltage vs
Temperature
r--r--~-"""--"""---' 10.20

-"'.--....--

s.a

Operating Input Bias
Current vs Temperature

2.4

~

2.3

0.5 1.0 1.' 2.0 2.5 3.0 3.6 4.0

16

10

20

LED SUPPLY VOLTAGE (V)

REFERENCE LOAD CURRENT (mA)

TL/H/51 04-2

Total Divider Resistance
vs Temperature

v+

1.12

'"

I...

I

1.10

N

~

1.08

LM39~V
DIVIDER

1.06

~

"

1.04

ffi

1.00

=
~

1.02 ' - -

'"
is

;; 0.98

r--

I
-

r--

A
VL---

-D.'

~ -1.0

Output Characteristics
12

I - - kEFERJEO TO JOSITIV~_

I

.1:

"
I

-

NEGATIVE COMMON-MOOELIMIT INCLUDES GROUND

50

TEMPERATURE rC)

75

10D

21

40

TEMPERATURE ("C)

60

80

~OOpA

L

z

WITH STABLE
lk RESISTOR

ImA

-2.0

'"

DIVIDER PARALLEL

25

Y+'.V
TA=2'"C

w -1.5

0.96

-2.

10

SUPPLY VOLTAGE

!

g

..

V

~

Common-Mode Limits

~OpA
1400pA

IL(REFI"~ODpA

I

V-

I
0.2

0.4

0.6

0.8

1.0

OUTPUT VOLTAGE(V)
TL/H/51 04-3

4-115

II

.... r-----------------------------------------------------------------------------,
~

~

~

Block Diagram (Showing Simplest Application)

LED

r - - - --LM39iS- - - - - - ,

I

COMPARATOR
1 OF 10

v+

I
10

6.63.

4.&911

3.31.
LEO PROGRAM
CURRENT

2.34.

REF
OUT
THIS LOAD
DETERMINES
LED
BRIGHTNESS

I1

1.66k
REFERENCE
VOLTAGE
SOURCE
1.2V
1.11k

-

REF
ADJ

I

0.83.

8

-I
I

O.&8k

I
v+-i

3

OAI.

I
I
RLO I 4

1.
V·

FROM
PIN 11

MODE
SELECT
AMPLIFIER

m

IN

I CONTROLS
TYPE OF
9

DISPLAY. BAR

OR SINGLE
I LED
I

~
I~
l ____________ J
5

+

TUH/5104-4

4-116

Functional Description

LM3915 Output Circuit

The simplified LM3915 block diagram is included to give the
general idea of the circuit's operation. A high input impedance buffer operates with signals from ground to 12V, and is
protected against reverse and overvoltage signals. The signal is then applied to a series of 10 comparators; each of
which is biased to a different comparison level by the resistor string.

PIN 1, PINS 10-1'

In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. In this case, for each
3 dB that the input signal increases, a comparator will
switch on another indicating LED. This resistor divider can
be connected between any 2 voltages, providing that they
are at least 1.5V below V+ and no lower than V-.

TL/H/S104-6

Outputs may be run in saturation with no adverse effects,
making it possible to directly drive logic. The effective saturation resistance of the output transistors, equal to Re plus
the transistors' collector resistance, is about 50n. It's also
possible to drive LEOs from rectified AC with no filtering. To
avoid oscillations, the LED supply should be bypassed with
a 2.2 p.F tantalum or 10 p.F aluminum electrolytic capacitor.

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:
VOUT = VREF ( 1 +

IL

I

t

r

:~) + IAOJ R2
I
I

lM3815

REF

REF

OUT_ _ ADJ 1

VOlUT

MODE PIN USE
Pin 9, the Mode Select input, permits chaining of multiple
LM3915s, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).

~EF8

-

-.J
(8"

Dot Display. Single LM3915 Driver: Leave the Mode Select pin open circuit.

8

Dot Display. 20 or More LEOs: Connect pin 9 of the first
driver in the series (i.e., the one with the lowest input voltage comparison points) to pin 1 of the next higher LM3915
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30 or more LED displays.
The last LM3915 driver in the chain will have pin 9 left open.
All previous drivers should have a 20k resistor in parallel
with LED #9 (pin 11 to VLEO).

=.JIAO.I

R2
,:".

TL/H/S104-S

Since the 120 p.A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V+ and load changes.
For correct operation, reference load current should be between 80 p.A and 5 mA. Load capacitance should be less
than 0.05 p.F.

Mode Pin Functional Description
This pin actually performs two functions. Refer to the simplified block diagram below.

CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltages, alarms, etc.

Block Diagram of Mode Pin Function
OUTFUT NO.8

OUTPUT NO. 10

CONTROLLEO ORIVE {
(FROM COMPARATORSI

HI----t--+-\

V-

2

The LM3915 outputs are current-limited NPN transistors as
shown below. An internal feedback loop regulates the transistor drive. Output current is held at about 10 times the
reference load current, independent of output voltage and
processing variables, as long as the transistor is not saturated.
'High for bar

4-117

TUH/S104-7

.....
I

~ r-~--------------------------------------------------------------------------~-----------'

~

Mode Pin Functional Description
(Continued)

DOT OR BAR MODE SELECTION

OTHER DEVICE CHARACTERISTICS

The vol~age at pin 9 is sensed by comparator C1, nominally
referenced to (V+ - 100 mV). The chip is in bar mode
when pin 9 is above this level; otherwise it's in dot mode.
The comparator is designed so that pin 9 can be left open
circuit for dot mode.

The L.M3916 is relatively low-powered itself, and since any
number of LEOs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEDs OFF) is 1.6 mAo However, any reference loading adds
4 times that current drain to the V+ (pin 3) supply input. For
example, an LM3916 with'a 1 mA reference pin load (1.3k)
would supply almost 10 mA to every LED while drawing only
10 mA from its V+ pin supply. At full-scale, the IC is typically
drawing less than 10% of the current supplied to the display.

Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20
mV below V+ for bar mode and more than 200 mV below
V+ (or open circuit) for dot mode. In most applications, pin
9 is either open (dot mode) or tied to V+ (bar mode). In bar
mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.

The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency nbise and often an annoying flicker.
An "overlap" is built in so that at no time are all segments
completely off in the dot mode. Generally 1 LED fades in
while the other fades out over a mV or more of range. The
change may be much more rapid between LED # 10 of one
device and LED # 1 of a second device "chained" to the
first.

DOT MODE CARRY
In order for the display to make sense when multiple
LM3915s are cascaded in dot mode, special circuitry has
been included to shut off LED # 10 of the first device when
LED #1 ofthe second device comes on. The connection for
cascading in dot mode has already been described and is
depicted below.

Application Hints

As long as the input signal voltage is below the threshold of
the second LM3915, LED # 11 is off. Pin 9 of LM3915 # 1
thus sees effectively an open circuit so the chip is in dot
mode. As soon 'as the input voltage reaches· the threshold
of LED #11, pin 9 of LM3915 #1 is pulled an LED drop
(1.5V or more) below VLED. This condition is sensed by
comparator C2, referenced 600 mV below VLED. This forces
the output of C2 low, which shuts off output transistor Q2,
extinguishing LED #10.

The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
external wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string to a single point very near pin 2 is
the best solution.
Long wires from VLED to LED anode common can cause
oscillations. Depending on the severity of the problem
0.05 ",F to 2.2 ",F decoupling capacitors from LED anode
common to pin 2 will damp the circuit. If LED anode line
wiring is inaccessible, often similar decoupling from pin 1 to
pin 2 will be sufficient.

VLED is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 I"A) that is diverted
from LED #9 does not noticeably affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 ",A
flowing through LED #0 11 even if the input voltage rises high
enough to extinguish the LED. This 'ensures that pin 9 of
LM3915 # 1 is held low enough to force LED # 10 off when
any higher LED is illuminated. While 100 p,A does not normally produce significant LED illumination, it may be noticeable when using high-efficiency LEOs in a dark environment.
If this is bothersome, the simple cure is to shunt LED # 11
with a 10k resistor. The 1V IR drop is more than the 900 mV
worst case required to hold off LED # 10 yet small enough
that LED # 11 does not conduct significantly.

If LED turn ON seems slow (bar mode) or several LEOs light
(dot mode), oscillation or excessive noise is usually the
problem. In cases where proper wiring and bypassing fail to
stop oscillations, V+ voltage at pin 3 is usually below suggested limits. Expanded scale meter applications may have
one or both ends of the internal voltage divider terminated
at relatively high value resistors. These high-impedance
ends should be bypassed to pin 2 with at least a 0.001 ",F
capacitor, or up to 0.1 ",F in noisy environments.

Cascading LM3915s in Dot Mode

2tIk

f.1.

11

NO. 10
10

u +

MOOE

TLlH/5104-B

4-118

Application Hints (Continued)
Power dissipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEDs
programmed to 20 rnA the driver will dissipate over 600 mW.
In this case a 7.50 resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 ,...F solid tantalum capacitor
to pin 2.

Display circuits using two or more LM3915s for a dynamic
range of 60 dB or greater require more accurate detection.
In the precision half-wave rectifier of Figure 2 the effective
diode offset is reduced by a factor equal to the open-loop
gain of the op amp. Filter capaCitor C2 charges through R3
and discharges through R2 and R3, so that appropriate selection of these values results in either a peak or an average
detector. The circuit has a gain equal to R2/R1.

TIPS ON RECTIFIER CIRCUITS

It's best to capacitively couple the input. Audio sources frequently have a small DC offset that can cause significant
error at the low end of the log display. Op amps that slew
quickly, such as the LF351 , LF353, or LF356, are needed to
faithfully respond to sudden transients. It may be necessary
to trim out the op amp DC offset voltage to accurately cover
a 60 dB range. Best results are obtained if the circuit is
adjusted for the correct output when a low-level AC signal
(10 to 20 mV) is applied, rather than adjusting for zero output with zero input.

The simplest way to display an AC signal using the LM3915
is to apply it right to pin 5 unrectified. Since the LED illuminated represents the instantaneous value of the AC waveform, one can readily discern both peak and average values
of audio signals in this manner. The LM3915 will respond to
positive half-cycles only but will not be damaged by signals
up to ± 35V (or up to ± 100V if a 39k resistor is in series
with the input). It's recommended to use dot mode and to
run the LEDs at 30 rnA for high enough average intensity.
True average or peak detection requires rectification. If an
LM3915 is set up with 10V full scale across its voltage divider, the turn-on point for the first LED is only 450 mY. A
simple silicon diode rectifier won't work well at the low end
due to the 600 mV diode threshold. The half-wave peak
detector in Figure 1 uses a PN P emitter-follower in front of
the diode. Now, the transistor's base-emitter voltage cancels out the diode offset, within about 100 mY. This approach is usually satisfactory when a single LM3915 is used
for a 30 dB display.

For precision full-wave averaging use the circuit in Figure 3.
Using 1 % resistors for R1 through R4, gain for positive ~nd
negative signal differs by only 0.5 dB worst case. Substituting 5% resistors increases this to 2 dB worst case. (A 2 dB
gain difference means that the display may have a ± 1 dB
error when the input is a nonsymmetrical transient). The
averaging time constant is R5-C2. A simple modification
results in the precision full-wave detector of Figure 4. Since
the filter capaCitor is not buffered, this circuit can drive only
high impedance loads such as the input of an LM3915.
RJ

v+ (5V TO 25VI
Rl
10k

R4
lk

10

R2
lOOk

.,

01

lN914

11lF

"'--1~-+--1~ OUTPUT

---.J

INPUT - .

INPUT*' _ _..I\IV\r-l

R1
10k

.--'\M.-.....-

OUTPUT

02

1-'\110,..,..-+--..........--1

01,02: lN914 or lN414S

R2

. Average

1M

RJ
lOOk

'DC Couple
TL/H/5104-9

FIGURE 1. Half-Wave Peak Detector

R2

lk

R3

lOOk

Rl
Cl

= R2/Rl0 for Av
~

R2 for Av

--.J

~

1
~

10/Rl
TLlH/5104-10

.2

INPUT.

lk

~

0.41

.,

lOOk

Rl

FIGURE 2. Precision Half-Wave Rectifier

0.2

Peak

R4

R5

200k

200k

~---..I\IV\r---t--~W~--1
Rl

lOOk R2
lOOk

OUTPUT

01,02: lN914 or lN4148

TLlH/5104-11

FIGURE 3. PreCision Full-Wave Average Detector
4-119

10

...
~

~r-----------------------------------------------------------------~

Application Hints (Continued)
RS
200k

CI
0.2

R4

-.J

D4

200k

INPUT, .......---~~,__--...- -......- - .
RI
lOOk R2
lOOk

01,02,03,04: lN914 or lN414S

TL/H/5104-12

FIGURE 4. Precision Full·Wave Peak Detector
CASCADING THE LM3915
To display signals of 60 or 90 dB dynamic range, multiple
LM3915s can be easily cascaded. Alternatively, it is possible to cascade an LM3915 with LM3914s for a log/linear
display or with an LM3916 to get an extended range VU
meter.
A Simple, low cost approach to cascading two LM3915s is
to set the reference voltages of the two chips 30 dB apart
as in Figure 5. Potentiometer R1 is used to adjust the full
scale voltage of LM3915 #1 to 316 mV nominally while the
second IC's reference is set at 10V by R4. The drawback of
this method is that the threshold of LED #1 is only 14 mV
and, since the LM3915 can have an offset voltage as high
as 10 mV, large errors can occur. This technique is not recommended for 60 dB displays requiring good accuracy at
the first few display thresholds.
A better approach shown in Figure 6 is to keep the reference. at 10V for both LM3915s and amplify the Input signal

to the lower LM3915 by 30 dB. Since two 1% resistors can
set the amplifier gain within ± 0.2 dB, a gain trim is unnecessary. However, an op amp offset voltage of 5 mV will shift
the first LED threshold as much as 4 dB, so that an offset
trim may be required. Note that a single adjustment can null
out offset in both the precision rectifier and the 30 dB gain
stage. Alternatively, instead of amplifying, input signals of
sufficient amplitude can be fed direclly to the lower LM3915
and attsnuslBd by 30 dB to drive the second LM3915.
To extend this approach to get a 90 dB display, another 30
dB of amplification must be placed in the signal path ahead
of the lowest LM3915. Extreme care is required as the lowest LM3915 displays Input signals down to 0.5 mVI Several
offset nulls may be required. High currents should not share
the same path as the low level signal. Also power line wiring
should be kept away from signal lines.

LM3916

LM391&

NO.2

NO.1

SIG

REF
OUT

REF
ADJ

7

8

R3
lk

2~~

INPUT (tOY FULL SCALE)

FIGURE 5. Low Cost Circuit lor 60 dB Display
4-120

TL/H/5104-13

Application Hints (Continued)

LM3915
NO.1

LM3915
NO.2

INPUT
(lOV FULL SCALE)
TL/H/5104-14

FIGURE 6. Improved Circuit for 60 dB Display
The circuit in Figure 8 shows how to add a LED intensity
control which can vary LED current from 9 mA to 28 mA.
The reference adjustment has some effect on LED intensity
but the reverse is not true.

TIPS ON REFERENCE VOLTAGE
AND LED CURRENT PROGRAMMING
SINGLE LM3915
The equations in Figure 7 illustrate how to choose resistor
values to set reference voltage for the simple case where
no LED intensity adjustment is required. A LED current of 10
mA to 20 mA generally produces adequate illumination.
Having 10V full-scale across the internal voltage divider
gives best accuracy by keeping signal level high relative to
the offset voltage of the internal comparators. However, this
causes 450 /LA to flow from pin 7 into the divider which
means that the LED current will be at least 5 mA. A1 will
typically be between 1 kn and 2 kn. To trim the reference
voltage, vary A2.

MULTIPLE LM3915s

Figure 9 shows how to obtain a common reference trim and
intenSity control for two LM3915s. The two ICs may be connected in cascade for a 60 dB display or may be handling
separate channels for stereo. This technique can be extended for larger numbers of LM3915s by varying the values
of A 1, A2 and A3 in inverse proportion to the number of
devices tied in. The ICs' internal references track within 100
mV so that worst case error from chip to chip is only 0.1 dB
for VREF = 10V.

LM3915

LM391S
RLO Uk TYP

RLO

RHI

Uk TYP RHI

,.~.,

r- ..JVVtr- .,

I

I

I

I

REF

REF
AOJ

OUT

MODE

Rl
Sk
R4
4.7k
Adjust R2 to vary VREF
RS*
SDk
LED INTENSITY

12.5V
Pick Rl ~ :-IL-ED-:';VR:::E:":F/';';2:-::.2:7k:::n
Pick R2

~ (VREF - 1.25V) + 0.08 rnA
1.25V1Rl

TLlH/5104-15

FIGURE 7. Design Equations for Fixed LED Intensity

'9 rnA

< ILED < 28 rnA

@

R2
2Zk
R3
10k
REFERENCE
TRIM

VREF ~ 10V
TL/H/5104-16

FIGURE 8. Varying LED Intensity

4-121

,...

~r---------------------------------------------------------------'

~
::E

Application Hints (Continued)
10

..J

LMDI5

LM3915

NO.2

NO.1

REf

REf

RHI

OUT

ADJ

&

1

8

R4
Uk

R5

51<

TlIH/5104-17

FIGURE 9. Independent Adjustment of Reference Voltage and LED Intensity for Multiple LM3915s
The scheme in Figure 10 is useful when the reference and
LED intensity must be adjusted independently over a wide
range. The RHI voltage can be adjusted from 1.2V to 10V
with no effect on LED current. Since the internal divider here
does not load down the reference, minimum LED current is
much lower. At the minimum recommended reference load
of 80 ",A, LED current is about 0.8 mAo The resistor values
shown give a LED current range from 1.5 mA to 20 mA.

Other Applications
For increased resolution, it's possible to obtain a display
with a smooth transition between LEOs. This is accomplished by varying the reference level at pin 6 by 3 dBp-p as
shown in Figure ". The signal can be a triangle, sawtooth
or sine wave from 60 Hz to 1 kHz. The display can be run in
either dot or bar mode.
When an exponentially decaying RC discharge waveform is
applied to pin 5, the LM3915's outputs will switch at equal
intervals. This makes a simple timer or sequencer. Each
time interval is equal to RCt3. The output may be used to
drive logiC, opto-couplers, relays or PNP transistors, for example.

At the low end of the intensity adjustment, the voltage drop
across the 51 on current'sharing resistors is so small that
chip to chip variation in reference voltage may yield a visible
variation in LED intensity. The optional approach shown of
connecting the bottom end of the intensity control pot to a
negative supply overcomes this problem by allowing a larger
voltage drop across the (larger) current-sharing resistors.

Typical Applications
LM3915

LM3915

NO.1

NO.2

r -; L:;,;- -,
I
I
I
I
I
I

~

-15V

I
I
I
I
I
I

510

510

1:... ___ ...1

2k

'Optional circu~ for Improved intensity
matching at low currents. See text.

LEO
INTENSITY

TL/H/5104-18

FIGURE 10. Wlde·Range Adjustment of Reference Voltage and LED Intensity for Multiple LM3915s

4·122

Typical Applications (Continued)

LM311&

1.211
7.511

INPUT
JOVTD10Y)

3.5Vp.,

IOHrTO UHz

TL/H/5104-19

FIGURE 11. OV to 10V Log Display with Smooth Transitions
Extended Range VU Meter

L....................,~_..., n: I.3VACCEITlR·TAPPED

LED

Ma'

LM3II.

....

L1IlI1,

L..---+--+------...-------....---+---+___.....
"'

(1IVFULLSCALE)*'_'--I---_ _ _ _ _ _ _ _ _ _ _ _ _ _- - '

.
....

v+IIZVTOZIVI

1.1111

This application shows that the LED supply reo
quires minimal filtering.

L--------_____________

·See Application Hints for optional Peak or Aver·
age Detector.

t Adjust R3 for 3 dB difference between LED

-4~:::

••

# 11

and LED #12.
TUH/5104-20

Vibration Meter
LED
10.1

+

T'="

U

I

c:::IPlEZOELECTRIC
TRAIIDUCER

...

••
TL/H/5104-21

4·123

LED

Threshold

1
2
3
4
5
6

60mV
SOmV
110mV
160mV
220mV
320mV
440mV
630mV
S90mV
1.25V

7
8
9
10

,..

It)

~
::::&

....

Typical Applications (Continued)

..

Indicator and Alarm, Full-Scale Changes Display From Dot to Bar

"111' '111 , '111' '111' '111' '111' '111 , '111 '111' '111
~

~.

.

LED
NO.1

n

11

~'

-¥

11

15

21k

...

LED

NO.l0

12

13

RLD

3

SIG

REF
OUT

RHI

'Dl
lN1l.

8Z1I

1011**

Uk

REF

"OJ

t!..- ' .,,!;
ovJ~v
INPUT

-¥

Dl

DOT·BAR*
SWITCH

LM3815

..

~

~

'N2'~

lD

11

3.

120

.P

MODE

'"='

•

'The input to the dot bar switch may be takan from cathodes of other LEOs.
Display will change to bar as soon as the LED so selected begins to light
"Optional. Shunts 100 p.A auxiliary sink current away from
LED #1.

".,USH11IESS"·

.....

TUH/5104-22

60 dB Dot Mode Display

.. ..... .... 111
r,. r ,r, r,.

-5' f ,
.~~~~
~

~

-11

~

~

1.

17

vL..Jl

-4l

I.

..

3

11

-31

~.

111
~ ~.

14

13

~-3I

-31

~

r

11/

~

Rt.o

SlI

•

..

C1ZVTOZlVI

r, f,..- ,r ,r
F-

" ...... 11

-71

•

-Z4

111

~EO ~

-,II

-11

-1.

REF
OUT

REF
ADI

Rl
1k

'='

-8

•••

-3

~

I.

17

ttl

~-~ED
0.21

I.

1.

1

v'
3

RLO

'*
*
I.
I~~ *
HI

14

13

12

11

11

LII3IIl.

v-

MODE

• •

I!...-'

-I

~ r ~ r, r ,r ,r ,f, r,

.....
RHI

-12

11/

10.11

I.

LM3I1.

* 'Xu '*
-:!:; Cl

RI
HI<

SlG
5

RHI

REF
OUT

I!..-'

REF
AOJ
I

MODE

II

RZ
1k

R4

U.

R3
U40

V

~3

'Optional. Shunta 100 "A auxiliary sink currant away from LED #11.

IIIPUT
C1DV FULL,sCALEI
TL/H/5104-23

4-124

Typical Applications (Continued)
Drlvtng Vacuum Fluorescent Display
v'

12VTOl5V

•• uD'
fiLAMENT

"'~·;;O

VACUUM FLUORESCENT

LD

0"
2"

I"RGRAPH
GRID

":'

010

0"

01

012

01

.u

.,

."
R15
11

R.
Uk

" "

15

"

13

12

11

"

LU31'S

v-

L.JI

-¥

v'

°LO

•

3

°HO

5

-¥

r---- - - - - - ------,
;:
i
I

I

I
I
I
I
I
I
I

I.
AUOI0-t
INPUT

I ,...

,...

..

02

R'

I

o".!.
.....

~,

~

T

MODE

Uk

I

.,

I
I

Uk

":'

I

r+;(
·

REF
ADJ

, • •

.

.I

...!"

OEF
OUT

so.

I

I

R7thru R15: 10k ± 10%
01. 02: lN914 or lN4148

I

'Half-wave peak detector.
See Application Hints.

I
I
t
I ______________
-IV:O-IIV
l:.
JI

TL/H/5104-24

Low Current Bar Mode Display

LIl3lII

Supply currant drain Is only 15

rnA with ten LEOs illuminated.

4·125

TL/H/61 04-25

~
.-

~

r---------------------------------------------------------~--------------------__.

Typical Applications (Continued)
Driving Liquid Crystal Display
LIQUID CRYSTAL BAR GRAPH
BACKPLANE

Full-scale causes the full bar display to flash. If the
junction of Rl and Cl is connected to a different LED
cathode, the display will flash when that LED lights,
and at any higher input signal.

470
1.2k

TLlH/5104-27

4-126

Typical Applications

(Continued)
Precision Null Meter

V'IIVTO 1IVI

LED
NO.11

LII3Ifl

"
L1I3.

LED
NO.1

4.n
LM3I1&

.C-6VTD-tIVI

+

... 'X
'='

Logarithmic response allows coarse and fine adjustments without changing scale.
Resolution ranges from 10 mV at V'N
500 mV at V'N = ± 1.25V.

INPUT

= 0 mV to
TL/H/5104-28

Operating with a High Voltage Supply (Dot Mode Only)
48V

3.9k
IW

114102

N
LED

NO.1

N

N

N

N

N

N

N

II

LED
NO.10
13
12
II
10
r",I1:---'-"---'':':'''_=-=-...L:::''''-L;::''''....L:'!''---JL.:.:,

1.

LM39t6

'='

J.4V·
The LED currents are approximately 10 mA, and
the LM3915 outputs operate in saturation for

minimum dissipation.

82.

'This point is partially regulated and decreases in
voltage with temperature. Voltage requirements
of the LM3915 also decrease with temperature.

TL/H/5104-29

4-127

~~----------------------------------------------------------------------,

"""
=
=t

Typical Applications (Continued)
Light Meter
U!~
NO.1

~1 rfJ1 ,fJ ~~ rfJ~ ,fJ1 ,fJ1 ,fJ,
~~ rfJ~ rfJ ~ .,fJ1 ,fJ1
~~ f~ f~ ~~ ~1 ,fJ1
~
f"
'"'
"
" "
" ..
"
II

I.

1.

Il

II

II

'3

LatS

V-

L-.J'

DFF

J:.N

-¥

...

"LO
4

3

14

11

13

12

'i

UD
ND. u
11

LlUlll

"H'I

S'G

5

"EF

"EF

ADJ

OUT

J*

v-

IIODE
I

I'

'=' Uk '='

-¥

...
3

"LD
4

SlG

•

"H'8

REF

"EF

AD.

GUT
1

$22

IIDDE

I

,I

,ft

-=-IV

rr~

-!-

.

,

Uk

2K

Uk

2K

1M'

'='

~~ ~~

~~

LM311A

+

3

1

&

LM_

8

3

• -:;t:'"'.'F

+

•

•

~'''PF

'Resistor value selects exposure
1/2 f/stop resolution

Ten flstop range (1000:1)
Typical supply current IS 8 mAo
TL/H/5104-30

Audio Power Meter

tzvra_

Connection Diagram
Dual-In-Llne Package
II

LEO NO. 1

V'

LM3I11

DIVIDER
(LOW END)

"
"

•

"

SlIiNALINPUT
DIVIDER'
IHIGH ENDt
R£FERENCE OUTPUT

REFERENCE AD.lUST

LEO NO.!

17 LEDNO.3

y-

LED NO. 4

LED NO. &
LED NO.1

13 LEO NO. 7

,
•

12 LEONO.'

.

11 LEDNO.'

MODESILECT

LED NO. "

TLlH/5104-32

,...

Top View
Order Number LM3915N
See NS Package Number N18A

TL/H/5,04-3'

Load
Impedance

R1

40

10k

80

18k

160

30k

See Application Hints for optional Peek
or Average Detector

4-128

Definition of Terms
Absolute Accuracy: The difference between the observed
threshold voltage and the ideal threshold voltage for each
comparator. Specified and tested with 10V across the internal voltage divider so that resistor ratio matching error predominates over comparator offset voltage.

measured at the current source outputs. As the forward voltage of an LED does not change significantly with a small
change in forward current, this is equivalent to changing the
voltage at the LED anodes by the same amount.
Line Regulation: The average change in reference output
voltage (VREF) over the specified range of supply voltage
(V+).

Adjust Pin Current: Current flowing out of the reference
adjust pin when the reference amplifier is in the linear region.

Load Regulation: The change in reference output voltage
over the specified range of load current (IL(REF».
Offset Voltage: The differential input voltage which must
be applied to each comparator to bias the output in the
linear region. Most significant error when the voltage across
the internal voltage divider is small. Specified and tested
with pin 6 voltage (VRH) equal to pin 4 voltage (VRLO).

Comparator Gain: The ratio of the change in output current
(I LED) to the change in input voltage (VIN) required to produce it for a comparator in the linear region.
Dropout Voltage: The voltage measured at the current
source outputs required to make the output current fall by
10%.
Input Bias Current: Current flowing out of the signal input
when the input buffer is in the linear region.

Relative Accuracy: The difference between any two adjacent threshold pOints. Specified and tested with 10V across
the internal voltage divider so that resistor ratio matching
error predominates over comparator offset voltage

LED Current Regulation: The change in output current
over the specified range of LED supply voltage (VLEO) as

4-129

~National
~ Semiconductor

LM3916 Dot/Bar Display Driver
General Description
The LM3916 is a monolithic integrated circuit that senses
analog voltage levels and drives ten LEOs, LCOs or vacuum
fluorescent displays, providing an electronic version of the
popular VU meter. One pin changes the display from a bar
graph to a moving dot display. LED current drive is regulated and programmable, eliminating the need for current limiting resistors. The whole display system can operate from a
single supply as low as 3V or as high as 25V.

The LM3916 is very versatile. The outputs can drive LCOs,
vacuum fluorescents and incandescent bulbs as well as
LEOs of any color. Multiple devices can be cascaded for a
dot or bar mode display for increased range and/or resolution. Useful in other applications are the linear LM3914 and
the logarithmic LM3915.

The IC contains an adjustable voltage reference and an accurate ten-step voltage divider. The high-impedance input
buffer accepts signals down to ground and up to within 1.5V
of the positive supply. Further, it needs no protection
against inputs of ±35V. The input buffer drives 10 individual
comparators referenced to the precision divider. Accuracy is
typically better than 0.2 dB.

•
•
•
•
•
•
•
•
•
•
•
•

Features

Audio applications include average or peak level indicators,
and power meters. Replacing conventional meters with an
LED bar graph results in a faster responding, more rugged
display with high visibility that retains the ease of interpretation of an analog display.
The LM3916 is extremely easy to apply. A 1.2V full-scale
meter requires only one resistor in addition to the ten LEOs.
One more resistor programs the full-scale anywhere from
1.2V to 12V independent of supply voltage. LED brightness
is easily controlled with a single pot.

Fast responding electonic VU meter
Drivers LEOs, LCOs, or vacuum fluorescents
Bar or dot display mode externally selectable by user
Expandable to displays of 70 dB
Internal voltage reference from 1.2V to 12V
Operates with single supply of 3V to 25V
Inputs operate down to ground
Output current programmable from 1 mA to 30 mA
Input withstands ±35V without damage or false outputs
Outputs are current regulated, open collectors
Directly drives TTL or CMOS
The internal 10-step divider is floating and can be referenced to a wide range of voltages

The LM3916 is rated for operation from O·C to + 70"C. The
LM3916N is available in an 18-lead molded DIP package.

Typical Applications
OVTO 10VVU Meter
-20

-10

-1

-5

-1

-3

0

+1

+2

+3

VU

r--~--~t----'~--~--~.----e----~--~.----e----"~03V~vLED~v+

I

.~~~~~.~~~.~~~.~~~~~

_~~
II LED
I NO. I
CI I
TANT~~~~...L

.~

.~

~~

...

J~

.~

~~

.~

IB

11

16

15

14

13

12

"

10

LM3916

ORIDI'f'1'

ELE:i~:~~~I~ I

.~,LED
NO.IO

V-

RLO

: ----1'
L _______ -+--+-........

SIG

RHI

REF

REF

OUT

AOJ

MODE

19
Note I: Capacnor CI is required If
leads to the LED supply are 6" or
longer.
Note 2: Circuit as shown is wired for
dot mode. For bar mode, connect pin
9 to pin 3. VLED must be kept below
7V or dropping resistor should be
used to lim~ IC power dissipation.

V+
12VTO 2DV-

VREF=I.25V(1 +*) +R2X80p.A
12.5V

ILED

VREF

= R1 + 2.2 kn

TLlH17971-1

4-130

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Dissipation (Note 5)
Molded DIP (N)
Voltage on Output Drivers

-100mVtoV+

Divider Voltage

10mA

Reference Load Current

- 55·C to + 1500C

Storage Temperature Range

1365mW
25V

Supply Voltage

260·C

Lead Temperature (Soldering, 10 seconds)

25V

Electrical Characteristics (Notes 1 and 3)
Parameter

±35V

Input Signal Overvoltage (Note 3)

I

I

Conditions (Note 1)

Min

I I
Typ

Max

3

10

3

15

I

Units

COMPARATORS
Offset Voltage, Buffer and First
Comparator

OV s: VRLO = VRHI
ILED = 1 mA

Offset Voltage, Buffer and Any Other Comparator

OV

s: 12V,

s: VRLO = VRHI s: 12V, ILED =
=

=

Gain (~ILED/ ~ VIN)

I(REF)

Input Bias Current (at Pin 5)

OV

Input Signal Overvoltage

No Change in Display

2 mA, ILED

s: VIN s: (V+

1 mA
3

10 mA

-1.5V)

8
25

-35

mV
mV
mA/mV

100

nA

35

V

VOLTAGE DIVIDER
Divider Resistance

Total, Pin 6 to 4

8

12

17

kO

Relative Accuracy (Input Change
Between Any Two Threshold POints)

(Note 2)
-1 dB s: VIN s: 3 dB
-7dBS:VINS: -ldB
-10dB s: VIN s: -7dB

0.75
1.5
2.5

1.0
2.0
3.0

1.25
2.5
2.5

dB
dB
dB

Absolute Accuracy

(Note 2)
VIN = 2, 1, 0, -1 dB
VIN = -3, -5 dB
VIN = -7, -10. -20dB

-0.25
-0.5
-1

+0.25
+0.5
+1

dB
dB
dB

1.28

1.34

V

0.01

0.03

O/O/V

0.4

2

0/0

VOLTAGE REFERENCE
Output Voltage

0.1 mA s: IL(REF) s: 4mA,
V+ = VLED = 5V

s: V+ s:

Line Regulation

3V

Load Regulation

0.1 mA s: IL(REF) s: 4mA,
V+ = VLED = 5V

Output Voltage Change with Temperature

O·CS:TAS: +700C,IL(REF)
V+ = VLED = 5V

1.2

18V

=

0/0

1

1 mA,

75

Adjust Pin Current

120

pA

OUTPUT DRIVERS

=

LED Current

V+

LED Current Difference (Between Largest
and Smallest LED Currents)

VLED
VLED

LED Current Regulation

2V

Dropout Voltage

VLED

=
=

=

5V, IL(REF)

5V, ILED
5V. ILED

=
=

s: VLED s: 17V

ILED(ON)
~ILED

=

=

20 mA @ VLED
2mA

Saturation Voltage

ILED

Bar Mode (Note 4)

Output Leakage

Dot Mode (Note 4)

1 mA

7

ILED = 2mA
ILED = 20mA

=

Output Leakage. Each Collector

=

2 mA
20 rnA

2.0 mAo IL(REF)

=

=

0.4 rnA

60
4·131

13

rnA

0.4
3

rnA
rnA

0.1
1

0.25
3

mA

1.5

V

5V,

Pins 10-18
Pin 1

10
0.12
1.2

rnA

0.15

0.4

V

0.1

100

pA

0.1

100

pA

150

450

pA

co
..-

."
Cf)

~

Electrical Characteristics (Note 1) (Continued)

I

Parameter

-I

I

Conditions (Note 1)

Min

I

Typ

I

6.1

I

Max

I

9.2

I

Units

SUPPLY CURRENT
Standby Supply Current
(All Outputs Off)

I

V+
V+

=
=

+ 5V, IL(REF)

= 0.2 rnA
= 1.0 rnA

I

+20V,IL(REF)

Note 1: Unless otherwise stated. all specifications apply with the following conditions:
3 Vee
3 Vee

s:
s:

-0.015V

V+

s:

VLEa

s:

20 Vae

s:

VRHI

-0.015V

s:

VRLO

V+

VREF, VRHI, VRLO

s:

OV

12 Vee

s:

VIN

s:

s: 12 Vae
s: (V+ - 1.5V)

2.4

4.2

I

rnA
rnA

TA ~ 25"C,IL(REF) ~ 0.2 mA, pin 9 connected 10 pin 3 (bar mode).
For higher power dissipalions, pulse tes1ing Is used.

V+ - 1.5V

Note 2: Accuracy Is measured refernod 10 +3 dB ~ + 10.000 Vae at pin 5, with + 10.000 Vee at pin 6, and 0.000 Vae at pin 4. At lower full·scale voltages, buffer

and comparator offset voltage may add slgnHicant error. See table for threshold voltages.
Nota 3: Pin 5 input current

must be limited 10 ± 3 mAo The addition of a 39k resistor In series with pin 5 allows ± 1OOV signals without damage.

Nota 4: Bar mode results when pin 9 is within 20 mV ofV+. Dot mode resuHswhen pin 9 is pulled at least 200 mV belowV+. LED #10 (pin 10 output current) is
disabled H pin 9 Is pulled 0.9V or more below VLEDNote 5: The maximum junction temperature of the LM3916 is l00"C. Devices must be derated for operation at elevated temperatures. Junction to ambient thermal
resistance Is 55"C/W for the molded DIP (N package).

LM3916 Threshold Voltsge (Note 2)
Volts

dB
3

Volts

dB

Min

Typ

Max

9.985

10.000

10.015

-3 ±

'h
'h

Min

Typ

Max

4.732

5.012

5.309

2±%

8.660

8.913

9.173

-5 ±

1 ± %

7.718

7.943

8.175

-7 ± 1

O±%

6.879

7.079

7.286

-10 ± 1

1.995

2.239

2.512

5.957

6.310

6.683

-20 ± 1

0.631

0.708

0.794

-1 ±

'h

4-132

3.548

3.981

4.467

2.818

3.162

3.548

Typical Performance Characteristics
Supply Current va
Temperature

r--':-"--...,..-Y--..

1.1

l'i

IE

1e

1---9'-:=::;;I;-""I''''''::r''::::'-''

&.I

~

II!

I----i---+--+-+--j

5.0

Ii

II

7&

21

TE_RATtlRE ('CI

I
~

50

~

1.21

s

1.27

71

25

TE_RATURE rCI

Reference AdJuat Pin
Current va Temperature

LED Driver Saturation
Voltage

LED Current-Regulation
u

Iii

I.

.~

14

it

IZ

~

.0

_

.I,

.........

'" .........

i 7.
71

i

-21

21

51

71

I.

11

",~z.J

I

1

I-

-1

TAI-Ir~t

U

-3

-40 -3D -21 -10

t.5

28

/

Ia
..

Z5

11

30

21

21

LED Driver Current
Regulation

..,...'"

Ii

/

. . . . I.II.1Z.au3.0U4.0

i

1'"

;

1--1--1--+--+-1

~

/
o

411

1&

LEO CURRENT (mAl

TA-ZI"C

I=
10 20

11

V

31

ill

a

.....

1.1

7 Irric

-2

/. ~.O'c_
I

V

LED CUrrent vs
Reterenced Loading

,

IB

TA-70'e,/;

LED CURRENT (mAl

Input Current Beyond
Signal Range (Pin 5)

"j"

VL

TA-r C' -

~

TEMPERATURE rCI

DIVIDER V' IOV

REIEAENC~

LDAO'rURREJT
LED CURRENT

- ' - - 1-

T'-7I~~
~

15

&I

TEMPERATURE rCI

Dropout

OF

II!

~
18.111;::

!;! 1.29

u

3

11.10

..

SA

U

i

I--I'=-I--+_;;±---j

~
a

1
I

r-~r-~--r--'-' lb~

1--11--+--+-+-"

a

........

u 1--+==01-''''''''1'''''ii+:

..

Reference Voltage va
Temperature

Operating Input Biaa
Current va Temperature

ZA

~:3=:!t:t=I=J
ID

15

~

2.3

20

LEO SUPPLY VOLTA;E (VI

REFERENCE LDAO CURRENT (..AI

TUH/7971-2

Total Divider Resistance
vs Temperature
Ii 1.12

S 1.10

I

UI

I

j
co

eiii

UN

~

..

15 1.11
-2&

r---

~EFERJED TO J.mnv~
SUPPLY VOLTAGE

C7"

ZI

DIVIDER PARALLEL
"TKSTAlLE
IkRU1STDR

ID

71

110

~ NEGATIVE CDMIIIDNoIIDDE-

LIMIT INCLUDU GRDUND
Z04l1011

TEMPERATURE rCI

ho.lIA
\.alIA

/..

r

IL J_-- ~

TEIII'ERATURE ('CI

IliA

j-

A

I.IZ

1.18

Y+'IV

10

DIVI~ER

rJ
;

Output Characteristics
IZ

TA-2&OC

'~~~7 I--

!l I .•

.,. Common-Mode Limits

)

14I011A

/

ILIREFI -

/'

~011lA

I
U

DA

...

0.8

1.1

OUTPUTVDLTAOECVI

TUH/7971-3

4·133

~
..-

~

r-----------------------------------------------------------------------------,
Block Diagram (Showing Simplest Application)

!I

·r- - -

I

~

-

Ui381a~

COMPARATOR
I OF 10
. 1.0

I
I

LED

- - --,

y+

I
.

1081

I
I

81O

I
I
I

8&4

LED PROGRAM
CURRENT

I
I
I

789

1298

THIS LOAD
DETERMINES
LED
BRIGHTNESS

REFERENCE
VOLTAGE
SOURCE
I.2V

1831

-

REFI
AOJ 8

819

- I
I
I

923

V+-t 3

1631

I
I

701

RLol 4

-

MODE
SELECT
AMPLIFIER

I CONTROLS
TYPE OF
9

DISPLAY, BAR

I ORLEDSINGLE
I

.~
~

IN

5

I~

+

l ____________ J

TL/HI7971-4

4-134

Functional Description
LM3916 Output Circuit

The simplified LM3916 block diagram is included to give the
general idea of the circuit's operation. A high input impedance buffer operates with signals from ground to 12V, and is
protected against reverse and overvoltage signals. The signal is then applied to a series of 10 comparators; each of
which is biased to a different comparison level by the resistor string.
In the example illustrated, the resistor string is connected to
the internal 1.25V reference voltage. As the input voltage
varies from 0 to 1.25, the comparator outputs are driven low
one by one, switching on the LED indicators. The resistor
divider can be connected between any 2 voltages, providing
that they are at least 1.5V below V+ and no lower than V -.

TL/HI7971-6

Outputs may be run in saturation with no adverse effects,
making it possible to directly drive logic. The effective saturation resistance of the output transistors, equal to RE plus
the transistors' collector resistance, is about 50n. It's also
possible to drive LEOs from rectified AC with no filtering. To
avoid oscillations, the LED supply should be bypassed with
a 2.2 ",F tantalum or 10 ",F aluminum electrolytic capacitor.

INTERNAL VOLTAGE REFERENCE
The reference is designed to be adjustable and develops a
nominal 1.25V between the REF OUT (pin 7) and REF ADJ
(pin 8) terminals. The reference voltage is impressed across
program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2 giving an output voltage of:
VOUT = VREF (1

IL

I

MODE PIN USE
Pin 9, the Mode Select input, permits chaining of multiple
devices, and controls bar or dot mode operation. The following tabulation shows the basic ways of using this input.
Other more complex uses will be illustrated in the applications.
Bar Graph Display: Wire Mode Select (pin 9) directly to pin
3 (V+ pin).

+ ~~) + IADJ R2

r

I
I

LM391B

+ OUT
REF_ _ REF
ADJ
7-,B

__

ra
a

Dot Display, Single LM3916 Driver: Leave the Mode Select pin open circuit.

VREF

I

Dot Display, 20 or More LEDs: Connect pin 9 of the first
drivers in the series (i.e., the one with the lowest input voltage comparison points) to pin 1 of the next higher LM3916
driver. Continue connecting pin 9 of lower input drivers to
pin 1 of higher input drivers for 30 or more LED displays.
The last LM3916 driver in the chain will have pin 91e1t open.
All previous drivers should have a 20k resistor in parallel
with LED #9 (pin 11 to VLEO).

VI
TUH17971-5

Since the 120 ",A current (max) from the adjust terminal
represents an error term, the reference was designed to
minimize changes of this current with V+ and load changes.
For correct operation, reference load current should be between 80 ",A and 5 mA. Load capacitance should be less
than 0.05 ",F.

Mode Pin Functional Description
This pin actually performs two functions. Refer to the simplified block diagram below.
Block Diagram of Mode Pin Function

CURRENT PROGRAMMING
A feature not completely illustrated by the block diagram is
the LED brightness control. The current drawn out of the
reference voltage pin (pin 7) determines LED current. Approximately 10 times this current will be drawn through each
lighted LED, and this current will be relatively constant despite supply voltage and temperature changes. Current
drawn by the internal 10-resistor divider, as well as by the
external current and voltage-setting divider should be included in calculating LED drive current. The ability to modulate LED brightness with time, or in proportion to input voltage and other signals can lead to a number of novel displays or ways of indicating input overvoltagas, alarms, etc.

OUTPUT NO• •

11

CONTROLLED DRIVE {
(FROM COMPARATORS)

The LM3916 outputs are current-limited NPN transistors as
shown below. An internal feedback loop regulates the transistor drive. Output current is held at about 10 times the
reference load current, independent of output voltage and
proceSSing variables, as long as the transistor is not saturated.

4-135

H f - - - + - -......

II

.... r-----------------------------------------------------------------------------,
~

~

:!I

Mode Pin Functional Description (Continued)

DOT OR BAR MODE SELECTION
The voltage at pin 9 is sensed by comparator C1, nominally
referenced to (V+ -100 mV). The chip is in bar mode when
pin 9 is above this level; otherwise it's in dot mode. The
comparator is designed sci that pin 9 can be left open circuit
for dot mode.

more) below VLED. This CQndition is sensed by comparator
C2, referenced 600 mV below VLED. This forces the output
of C2 low, which shuts off output transistor Q2, extinguishing LED #10.
VLED is sensed via the 20k resistor connected to pin 11.
The very small current (less than 100 pA) that is diverted
from LED #9 does not noticeably affect its intensity.
An auxiliary current source at pin 1 keeps at least 100 pA
flowing through LED # 11 even if the input voltage rises high
enough to extinguiSh the LED. This ensunss that pin 9 of
driver # 1 is held low enough to force LED # 10 off when
any higher LED is illuminated. While 100 pA does not normally produce significant LED illumination, it may be notioeable when using high-efficiency LEOs in a dark environment.
If this is bothersome, the simple cure is to shunt LED # 11
(and LED #1) with a 10k resistor. The IV 1R drop is more
than the 900 mV worst case required to hold off LED #10
yet small enough that LED # 11 does not conduct significantly.

Taking into account comparator gain and variation in the
100 mV reference level, pin 9 should be no more than 20
mV below V+ for bar mode and more than 200 mV below
V+ (or open circuit) for dot mode. In most applications, pin
9 is either open (dot mode) or tied to V+ (bar mode). In bar
mode, pin 9 should be connected directly to pin 3. Large
currents drawn from the power supply (LED current, for example) should not share this path so that large IR drops are
avoided.
DOT MODE CARRY
In order for display to make sense when multiple drivers are
cascaded in dot mode, special circuitry has been included
to shut off LED # 10 of the first device when LED # 1 of the
second device comes on. The connection for cascading in
dot mode has already been described and is depicted in
Figure 1.

In some circuits a number of outputs on the higher device
are not used. Examples include the high resolution VU mater and the expanded range VU meter circuits (see Typical
Applications). To provide the proper carry sense voltage in
dot mode, the LEOs of the higher driver IC are tied to VLED
through two series-connected diodes as shown in F/{/UffJ 2.
Shunting the diodes with a 1k resistor provides a path for
driver leakage current.

As long as the input Signal voltage is below the threllhold of
the second driver, LED # 11 is off. Pin 9 of driver # 1 thus
sees effectively an open Circuit so the chip is in dot mode.
As soon as the input voltage reaches the threshold of LED
# 11, pin 9 of driver # 1 is pulled an LED drop (1.5V or

¥UO

{fa {fa fJ
'0

11

~~~~~~~~~~~~~--~~I1~I~O

~~1.--~--~--~--~~~~~~~~~

LM3I1Cltllti

1.1+

LM3I1f/11111
NO.2

NO.1
1100£

TLIHI7971-B

FIGURE 1. CascadIng LM3914/15/16 SerIes In Dot Mode
lN914 '1"4

//I

12

11

//I

//I

U

10

13

12

//I

11

//I

\I

LMZ911. UI3Il.

L1I3811. LM3Il.
NO.1

10.2

TLlH17971-9

FIGURE 2. CascadIng Drivers In Dot Mode wIth PIn 1 of Driver # 2 Unused

4-136

should be run at 20 mA to 30 mA for high enough average
intensity.

Mode Pin Functional
Description (Continued)

True average or peak detection requires rectification. If an
LM3916 is set up with 10V full scale across its voltage divider, the turn-on point for the first LED is only 450 mY. A
simple silicon diode rectifier won't work well at the low end
due to the 600 mV diode threshold. The half-wave peak
detector in Figure 3 uses a PNP emitter-follower in front of
the diode. Now, the transistor's base-emitter voltage cancels out the diode offset, within about 100 mY. This approach is usually satisfactory when a single LM3916 is used
for a 23 dB display.

OTHER DEVICE CHARACTERISTICS
The LM3915 is relatively low-powered itself, and since any
number of LEDs can be powered from about 3V, it is a very
efficient display driver. Typical standby supply current (all
LEDs OFF) is 1.6 mAo However, any reference loading adds
4 times that current drain to the V + (pin 3) supply input. For
example, an LM3915 with a 1 mA reference pin load (1.3k)
would supply almost 10 mA to every LED while drawing only
10 mA from its V + pin supply. At full-scale, the IC is typically
drawing less than 10% of the current supplied to the display.

Display circuits such as the extended range VU meter using
two or more drivers for a dynamic range of 40 dB or greater
require more accurate detection. In the precision half-wave
rectifier of Figure 4 the effective diode offset is reduced by a
factor equal to the open-loop gain of the op amp. Filter capacitor C2 charges through R3 and discharges through R2
and R3, so that appropriate selection of these values results
in either a peak or an average detector. The circuit has a
gain equal to R2/R1.

The display driver does not have built-in hysteresis so that
the display does not jump instantly from one LED to the
next. Under rapidly changing signal conditions, this cuts
down high frequency noise and olten an annoying flicker.
An "overlap" is built in so that at no time are all segments
completely off the dot mode. Generally one LED fades in
while the other fades out over a 1 mV range. The change
may be much more rapid between LED '" 10 of one device
and LED '" 1 of a second device cascaded.

It's best to capacitively couple the input. AudiO sources frequently have a small DC offset that can cause significant
error at the low end of the log display. Op amps that slew
quickly, such as the LF351, LF353 or LF356, are needed to
faithfully respond to sudden transients. It may be necessary
to trim out the op amp DC offset voltage to accurately cover
a 60 dB range. Best results are obtained if the circuit is
adjusted for the correct output when 11 lOW-level AC signal
(10 to 20 mV) is applied, rather than adjusting for zero output with zero input.

Application Hints
The most difficult problem occurs when large LED currents
are being drawn, especially in bar graph mode. These currents flowing out of the ground pin cause voltage drops in
extemal wiring, and thus errors and oscillations. Bringing the
return wires from signal sources, reference ground and bottom of the resistor string to a single point very near pin 2 is
the best solution.

v+ (5V TO 25V)

Long wires from VLED to LED anode common can cause
oscillations. The usual cure is bypassing the LED anodes
with a 2.2 /LF tantalum or 10 /LF aluminum electrolytic capacitor. If the LEd anode line wiring is inaccessible, olten a
0.1 /LF capacitor from pin 1 to pin 2 will be sufficient.

............_-_-OUTPUT

R'
10

_""'_-1

INPUT *.....

If there is a large amount of LED overlap in the bar mode,
oscillation or excessive noise is usually the problem. In
cases where proper wiring and bypassing fail to stop oscillations, V+ voltage at pin 3 is usually below suggested limits.
When several LEDs are lit in dot mode, the problem is usually an AC component of the input signal which should be
filtered out. Expanded scale meter applications may have
one or both ends of the internal voltage divider terminated
at relatively high value resistors. These high-impedance
ends should be bypassed to pin 2 with 0.1 /LF.

R2
1M

R3
lOOk

'~C

Couple
TUH17971-10

FIGURE 3. Half·Wave Peak Detector
R3
Ik

II

R2
100.

Power disSipation, especially in bar mode should be given
consideration. For example, with a 5V supply and all LEDs
programmed to 20 mA the driver will dissipate over 600 mW.
In this case a 7.50 resistor in series with the LED supply will
cut device heating in half. The negative end of the resistor
should be bypassed with a 2.2 JAoF solid tantalum or 10 JAoF
aluminum electrolytic capaCitor to pin 2.

CI

I,.,

..J
INPUT,

02

I-'WI/""'4....--I....-

......

01,02: 1N914 or 1N4148

TIPS ON RECTIFIER CIRCUITS

Average Peak

The simplest way to display an AC signal using the LM3916
is to apply it right to pin 5 unrectified. Since the LED illuminated represents the instantaneous value of the AC waveform, one can readily discern both peak and average values
of audio Signals in this manner. The LM3916 will respond to
positive half-cycles only but will not be damaged by Signals
up to ± 35V (or up to ± 100V if a 39k resistor is in series
with the input). A smear or bar type display results even
though the LM3916 is connected for dot mode. The LEDs

R2
R3

1k
100k

1k

R1

~

R1

~

R2/10 for AV

C1

~

10/R1

R2forAv

TUH/7971-11

FIGURE 4. PreCision Half·Wave Rectifier
4-137

100k

~

1

=

10

Application Hints (Continued)
For precision full-wave averaging use the circuit in Figure 5.
Using 1 % resistors for R1 through R4, gain for positive and
negative signal differs by only 0.5 dB worst case. Substituting 5% resistors increases this to 2 dB worst case. (A 2 dB
gain difference means that the display may have a ± 1 dB
error when the input is a nonsymmetrical transient). The
averaging time constant is R5-C2. A simple modification
results in the precision full-wave detector of Figure 6. Since
the filter capacitor is not buffered, this circuit can drive only
high impedance loads such as the input of an LM3916.

fication C165. The LM3916's outputs correspond to the meter indications specified with the omission of the -2 VU
indication. The VU scale divisions differ slightly from a linear
scale in order to obtain whole numbers in dB.
Some of the most important specifications for an AC meter
are its dynamic characteristics. These define how the meter
responds to transients and how fast the reading decays.
The VU meter is a relatively slow full-wave averaging type,
specified to reach 99% deflection in 300 ms and overshoot
by 1 to 1.5%. In engineering terms this means a slightly
underdamped second order response with a resonant frequency of 2.1 Hz and a Q of 0.62. Figure 7 depicts a simple
rectifierlfilter circuit that meets these criteria.

AUDIO METER STANDARDS
VUMeter
The audio level meter most frequently encountered is the
VU meter. Its characteristics are defined as the ANSI speci-

C2

H8
510

GA7
HI
211Dk

CI

1.2

-..J
INPUT

I

R4

H6

21J11k

200,

CI
0.2

/-4P---""''''''---+--~i\,--''''''

INPUT"

1_

HI
lao, H2

t-_-.

R4

Hr-......'V2DOk'lilr-::::-....__..D4
HI
101' H2
100'

OUTPUT

01,02,03,04: lN914 OR lN4149
Attack and decay lime 10 DIN PPM
spec. Response down 1 dB for 10 ms
tone burst. Decays 20 dB in 1.5s.

01,02: lN914 or lN4148

TUH17971-12

TLlHI7971-13

FIGURE 5. Precision Full-Wave Average Detector

CI
0.047 pf

FIGURE 6. Precision Full-Wave Peak Detector

GAIN

R5

10

100k
1M

83

3DDK

AUOIO~
INPUT

R4
151.

HI
28' HZ
20,

R6

1

R8

C2

C3
0.56 ,...F
0.056,...F

Design Equations

R5. R6. C2. C3
01

R6

43k 2.0
100k 1.0

=wg2=177sec-2

C3

1 (1
1
1
1)
Wo
C2
fi3+fi4+Fi5+Re
=0=21.5sec-l
R3 = 2R4
Rl = R2 « R4
OUTPUT

AI, A2:

Va LF353

01,02: lN914 OR lN4148
'Reaches 99% level at 300 ms after applied
tone burst and overshoots 1.2%.
TL/H17971-14

FIGURE 7. Full-Wave Average Detector to VU Meter Specifications'

4-138

Application Hints (Continued)
Peak Program Meter

namic range, the LM3916 may be cascaded with the 3 dB/
step LM3915s. Alternatively, two LM3916s may be cascaded for increased resolution over a 28 dB range. Refer to the
Extended Range VU Meter and High Resolution VU Meter in
the Typical Applications section for the complete circuits for
both dot and bar mode displays.
To obtain a display that makes sense when an LM3915 and
an LM3916 are cascaded, the -20 dB output from the
LM3916 is dropped. The full-scale display for the LM3915 is
set at 3 dB below the LM3916's -10 dB output and the rest
of the thresholds continue the 3 dB/step spacing. A Simple,
low cost approach is to set the reference voltage of the two
chips 16 dB apart as in Figure 5. The LM3915, with pin 8
grounded, runs at 1.25V full-scale. R1 and R2 set the
LM3916's reference 16 dB higher or 7.89V. Variation in the
two on-chip references and resistor tolerance may cause a
± 1 dB error in the -10 dB to -13 dB transition. If this is
objectionable, R2 can be trimmed.
The drawback of the aforementioned approach is that the
threshold of LED #1 on the LM3915 is only 56 mV. Since
comparator offset voltage may be as high as 10 mV, large
errors can occur at the first few thresholds. A better approach, as shown in Figure 9, is to keep the reference the
same for both drivers (10V in the example) and amplify the
input signal by 16 dB ahead of the LM3915. Alternatively,

The VU meter, originally intended for signals sent via telephone lines, has shortcomings when used in high fidelity
systems. Due to its slow response time, a VU meter will not
accurately display transients that can saturate a magnetic
tape or drive an amplifier into clipping. The fast-attack peak
program meter (PPM) which does not have this problem is
becoming increasingly popular.
While several European organizations have specifications
for peak program meters, the German DIN specification
45406 is becoming a de facto standard. Rather than respond instantaneously to peak, however, PPM specifications require a finite "integration time" so that only peaks
wide enough to be audible are displayed. DIN 45406 calls
for a response of 1 dB down from steady-state for a 10 ms
tone burst and 4 dB down for a 3 ms tone burst. These
requirements are consistent with the other frequently encountered spec of 2 dB down for a 5 ms burst and are met
by an attack time constant of 1.7 ms.
The specified return time of 1.5s to - 20 dB requires a 650
ms decay time constant. The full-wave peak detector of
FIGURE 6 satisfies both the attack and decay time criteria.

Cascading The LM3916
The LM3916 by itself covers the 23 dB range of the conventional VU meter. To display signals of 40 dB or 70 dB dy-

LM3915

LM3916

RHI

SIG

REF
OUT

REF
ADJ

5

':"

':"

R3
760

RI
1.91k

VREFI ~ 1.25V
7.89V
1.25

~

6.31

~

VREF2 '" 7.89V

16 dB

R2

INPUT (7JV FULL-SCALE)

9.l9k

':"
TL/H/7971-15

FIGURE 8. Low Cost Circuit for 40 dB Display
-37

-34

-31

-28

-25

-22

-19

-16

REF

REF

OUT

ADJ

-13

-10

-7

-5

5

+1

+2

LM3018

LM3915

SIG

-1

-3

RHI

6

SIG
5

B

RHI
6

':"

R3
1.5k

REF
OUT
7

REF
AOJ MODE
B
9

R4
Ik

RI
7k
Rl

+ R2

-R-l-~6.31
~

16dB

INPUT
110V FULL SCALE)

FIGURE 9. Improved Circuit for 40 dB Display

4-139

TL/H/7971-16

r--------------------------------------------------------------------------,
....
causes 1 mA to flow from pin 7 into the divider which means
m
~

CO)

::e
.....

Application Hints (Continued)

that the LED currerit will be at least 10 mA~ R1 will typically
be between 1 kO and 5 kO. To trim the reference voltage,
vary R2.
The current in Figure 11 shows how to add a LED intenSity
control which can vary LED current from 5 mA to 28 mAo
Choosing VREF = 5V lowers the current drawn by the ladder, increasing the intensity adjustment range. The reference adjustment has some effect on LED intensity but the
reverse is not true.

instead of amplifying, input signals of sufficient amplitude
can be fed directly to the LM3916 and attenuated by 16 dB
to drive the LM3915.
To extend this approach to get a 70 dB display, another
30 dB of amplification must be placed in the signal path
ahead of the lowest LM3915. Extreme care is required as
the lowest LM3915 displays input signals down to 2 mVI
Several offset nulls may be required. High currents should
not share the same path as the low level signal. Also power
line wiring should be kept away from signal lines.

Multiple Drivers
Figure 12 shows how to obtain a common reference trim
and intenSity control for two drivers. The two ICs may be
connected in cascade or may be handling separate channels for stereo. This technique can be extended for larger
numbers of drivers by varying the values of R1, R2 and R3.
Because the LM3915 has a greater ladder resistance, R5
was picked less than R7 in such a way as to provide equal
reference load currents. The ICs' internal references track
within 100 mV so that worst case error from chip to chip is
only 0.2 dB for VREF = 5V.

TIPS ON REFERENCE VOLTAGE AND LED CURRENT
PROGRAMMING
Single Driver
The equations in Figure 10 illustrate how to choose resistor
values to set reference voltage for the simple case where
no LED intensity adjustment is required. A LED current of
10 mA to 20 mA generally produces adequate illumination.
Having 10V full-scale across the internal voltage divider
gives best accuracy by keeping signal level high relative to
the offset voltage of the internal comparators. However, this

LM3I1'

LM3916
RLO 10k TVP

ALO 111: TY, "HI

RHI

I"'~"

1"'.J\IV'v- .,
I

I

I

I

REf
OUT

REF
ADJ

MODE

• •

Rl
!II<

Rl

R'

Uk

Adjust A2 to vary VREF

Pick Rl =
Pick R2 =

,..

R6*

12.5V
ILED - VREF/l kO

LED INTENSITY

(VREF - 1.25V)
1.25V1Rl + 0.08 mA

5 mA <: ILED <: 28 mA

TUH/7971-17

@

VREF

= 5V

R3
!II<
REFERENCE
TftIM

FIGURE 10. Design Equations for Fixed LED Intensity
TL/H/7971-18

FIGURE 11. Varying LED Intensity

LM3915

LMlI'&

LED

REF

OUT

ADJ

R.

M
Uk

INTENSITY

REF

Uk

R1

IGtI

5mA <: ILED <: 28mA
@

VREF

= 5V

TUH17971-19

FIGURE 12. Independent AdJustment of Reference Voltage and LED IntenSity for Multiple Drivers

4-140

~----------------------------------------------------------------------------, ~

!i:

Application Hints (Continued)

w

The scheme in Figure 13 is useful when the reference and
LED intensity must be adjusted independently over a wide
range. The RHI voltage can be adjusted from 1.2V to 10V
with no effect on LED current. Since the internal divider here
does not load down the reference, minimum LED current is
much lower. At the minimum recommended reference load
of 80 pA, LED current is about 0.8 mA. The resistor values
shown give a LED current range from 1.5 mA to 25 mA.

connecting the bottom end of the intensity control pot to a
negative supply overcomes this problem by allowing a larger
voltage drop across the (larger) current-sharing resistors.

Other Applications
For increased resolution, it's possible to obtain a display
with a smooth transition between LEDs. This is accomplished by superimposing an AC waveform on top of the
input level as shown in Figure 14. The signal can be a triangle, sawtooth or sine wave from 60 Hz to 1 kHz. The display
can be run in either dot or bar mode.

At the low end of the intensity adjustment, the voltage drop
across the 510n current-sharing resistors is so small that
chip to chip variation in reference voltage may yield a visible
variation in LED intensity. The optional approach shown of

LM3918

LM3818

r -;;; L;;II:- ...,
PIN 7

I .--"
I
U" Uk
I
I
I
Ib.. ___
-IIV
.JI

510

510

1.25V ,; VREF ,; 10V

'Op1fonal circuit for Improved intensity
matching at low currents. Se. text.

1.5 rnA,; ILED ,; 25 rnA

TL/HI7971-20

FIGURE 13. Wide-Range Adjustment of Reference Voltage and LED Intensity for Multiple Drivers

LM381.

INPUT
(IYTO l1V)
2.

1""

12.

TLlH/7971-21

FIGURE 14. OV to 10V VU Meter with Smooth Transitions

4-141

CD
.....
en

LM3916

-I

Extended Range VU Meter (Bar Mode)

~

lN4001

)~
lN4001

~.
~

n:

..l!:.

""2&
O·

6.3 VAC CENTER·TAPPED

~2.2

::s

fn
--'II

-37

-34

-31

-21

-25

-22

-19

-16

-10

-13

-7

-5

-3

o

-1

+2

+1

+3da

LED.AI
ND.l~-

1
LM3lI15

!
ie>

V~1

i'"

*

v<-

13

RLD

'¥

INPUT (7.8V FUU-SCALE)*

SIG

15

LM3lI16

RHI

REF
OUT

Ie{

~R2
1k

,

REF
ADJ

V-

MODE

18

19

l'
NC

v<-

RLO

-¥

*

REF
OUT

REF
AOJ

l!_..P

8

RHI

SIG

MODE
9

RI

C"".

• •
¥tho
R4
330.

•

v<- (1ZV TO zav)

•

f

R3
62•

..&..

TLlHI7971-22

This application shows thai the LED supply requires minimal filtering.
'See Application Hints for optional Peak or Aver·
age Detector.

t Adjust R3 for 3 dB difference between LED # 11
and LED #12

~~O.I58~

R3

+

R4

-16dB

~
"a
~.

:a-

"a

'2.

n

!.
O·

Extended Range VU Meter (Dot Mode)
Dl

D2

::J
~

III

LED

~

1111

~

1111

~

1111

~

0

1111

1111

~

1111

q

(I)

~

l'

1111

LED

NO.1

ND.19

RI
10k'

11

LM3915

16

15

14

13

12

11

a..

E
~

10

LMl911

t

it
":'

+

. Rl

Cl

lk

~z.z

R5

33k

R4
Uk

01,02: lN914 or lN4148
'OPTIONAL SHUNTS 100 p.A auxiliary sink current away from LED # 1.

t5ee Application
age detector.

INPUT
(1.25V FULL·SCALEI

Hints for optional peak or aver-

TUH/7971-23

9~6£W'

II

Gr-----------------------------------------------------------------------------,
....
gJ

~

Typical Applications (Continued)

Driving Vacuum Fluoreacent DI.play

or

IIVTa IIV

VACUUM FLUaREleEIIT

FILAMENT
LO

':" RIO

HI

BAR GRAPH

RII

m

L,~..,.-..,..-~a!!!IIP!L~A:!.Y~AN~a~aEl!!..,.......,~..,.-*~-_::;_.,
RII
GRID

HI

RII

RI

RU

R7·

RI4
RII
II

HI
4.711

n

II

II

14

13

12

II

II

....11

or

VL..JI

',--------I

*

RLa
4

3

SIB

I-G

~-----,
R3
It

RHI

i

REF
OUT
7

REF

AIIJ MODE
I

R4

n

I
I
I
I
I
I
I
I

RI
1211

R7 thru RIS: IOk±IO%
01,02: IN914 or IN4148
'Half-wave peak detector.
See ApplicaliOll Hints.

I
I
I ______________
-BV:;-IIV
JI
~

TL/H17971-24

Indicator and Alarm, Full·Scale Change. Display From Dot to aar

N

N

N

N

N

N

N

N

N

LED
NO. I

"17

II

1&

14

13

II

II

OOT·BAR·

LUll

SWITCH

UII

'The Input to the Oot·Bar switch may
be taken from cathodes of other
LEOs. Display will change to bar as
soon as the LED 80 selected begins
to light.
"Optlonsl. Shunts 100 p.A auxiliary
sink current away from LED # I.
TL/H/7971-25

4·144

~
'a

g'

»

'a

..
.
. .
tVffff*N*Nt~rrf.~

"2-

(;'

High Resolution VU Meter (Bar Mode)

-23 VU

,

17LEOS

-18

-13

18

-10

-I

-5

-6

18

17

-3

-4

1.

15

13

-2

-1

12

D)

11

10

Ne

Ne

L18

Ne

1,6 \15

17

LM3918

11

J
1"
~

U1

112V~::U~~
I

6

~~~~;.;:i·

-( iN
14

13

+3

+4

+5VU

~ ~

iN-h·

12

10

11

0'

3V~VLED~'V

~
(I)

T1D~

l'
'"'"'
'"

1

LM3I16

14

* *

+2

+1

OVU

R7
33k

17
~

Jl

3~

~

~17
R4
2k

R3
2k

1

6

6

.N\
Rl

1
R2

23.2k
1%

RI

3D.lk

Uk

1%

"+'

-:e:
TL/HI7971-26

'See Application Hints for optional peak or aver·

age de1ector.
R2
Ri"+ii2
.. 0.562 -

-5 dB

or Rl '" 0.788 • R2

9~6£'"

II

LM3916

~
~

&r

High Resolution VU Meter (Dot Mode)

-aVU

-13

-10

-8

-6

,-..,Ill -,..,Ill ... ,Ill,- .,Ill -,.,Ill,-~
~

1.

~n

16

-3

-4

15

III

14

~~

-2

III

13

-I

,.

OYU

DI
IN914

D2
IN914

Jlll""1

Jlll""1

Ne

Ne

I,.

10

11

t)"

+1

N illY
,N,
..
~
~. - ~ "
12

»

~

"2-

In

Ne

h.

Ne

115

~~

+2

III

14

..,Ill ,,Ill -,,..

+3

III

~ ~.

13

~

+4

-t5VI

III

..;

12

~

11

It

!

0"
::J

(I>

i

:::>

1
LM3916

LM3916

y+

YJI

!

ct

¥

3

RlO

-=IF

• R8*
'~1"

RHI

SI&

5

REF
OUT

~1

REF
ADJ

•

MODE

Y-

19

¥

Je'

Y+
3

RLO

SI&
5

-=IF

REF
. OUT

1!..- 1

REF
ADJ
8

MODE

19

Ne

.::

• R7

33k

RHI

R3
Zk
yyy

IIV

1f+ 1000 pF
Driven by OS8830, OM7440
"Zero" Quiescent Power

Connection Diagrams
Metal Can Package

Dual-In-Llne Package

V·

8 NC

NC 1

INPUT A 2 -+---I)~--+-- 7 OUTPUT A

y. 3

V·

6 y'

TLlF/5852-1

Note: Pin 4 connected to case.

INPUT8 4 - + - -..G~--+--5 OUTPUT8

Top View

Order Number DS0025CH
See NS Package Number HOSC

TLlF/5852-2

Top View

Order Number DS0025CJ-8
or DS0025CN

See NS Package Number J08A or N08E
Dual-In-Une Package
V'

NC

OUT B

MC

IN B

Ne

NC

OUT A

NC

IN A

NC

NC

V-

TL/F/5852-3

Top View

Order Number DSO025CJ
See NS Package Number J14A

5-4

Absolute Maximum Ratings (Note 1)

Recommended Operating
Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(V+ - V-)Voltage Differential
25V
Input Current
100mA
Peak Output Current
1.5A
Storage Temperature
- 65·C to + 150·C
Operating Temperature
O·Cto +a5·C
Lead Temperature (Soldering, 10 sec)
300·C

V+ V- Differential Voltage

20V

Min
Max
70
Temperature
0
Maximum Power Dissipation' at 25·C
a-Pin Cavity Package
1150mW
14-Pin Cavity Package
1410 mW
10aOmW
Molded Package
670mW
Metal Can (TO-5) Package
• Derate a-pin cavity package 7.a mWI"C above 25·C; derate 14-pin cavity package 9.5 mWI"C above 25·C; derate
molded package a.7 mW/·C above 25·C; derate metal
can (TO-5) package 4.5 mWI"C above 25·C.

Electrical Characteristics (Notes 2 and 3) See test circuit.
Symbol

Parameter

Conditions

= 0.001 ,...F, RIN =
= 0.001 ,...F, RIN =
CIN = 0.001 ,...F, RIN =

t.lON

Turn-On Delay Time

CIN

tRISE

Rise Time

CIN

tdOFF

Turn-Off Delay Time

Min

on, CL = 0.001 ,...F
on, CL = 0.001 ,...F
on, CL = 0.001 ,...F

Typ

Max

Unlta

15

30

ns

25

50

ns

30

60

ns

(Note 4)
tFALL

CIN = 0.001 ,...F, RIN
CL = 0.001,...F

Fall Time

=

on,

PW

Pulse Width (50% to 50%)

CIN = 0.001 ,...F, RIN = on,
CL = 0.001 ,...F (Note 5)

VO+

Positive Output Voltage Swing

VIN

I (Note 4)

I (Note 5)

60

90

120

ns

100

150

250

ns
ns

500

= OV,IOUT = -1 mA

V+-1.0 V+-0.7V

V

V-+0.7V V-+1.5V
Negative Output Voltage Swing liN = 10 mA,lOUT = 1 mA
V
VONote 1: "Absolute Maximum Ratings" are those values beyond which the safety of the devioe cannot ba guaranteed. Except for "Operating Temperature Range"
they are not meant to Imply that the devioes should ba operated at these limits. The table of "Electrical Characteristics" provides oondHlons for actual devioe
operation.
Note 2: Unless otherwise specified minImax limits apply across the O'C to 70'C range for the DSOO25C.
Note 3: All currents into device pins shown 8S positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Parameter values apply for clock pulse width determined by input pulse width.
Note 5: Parameter values for input width greater than output clock pulse width.

Timing Diagram
5V

A. Input pulse width
>doc~ pulse
width

B. Input pulse width
sel$ clock pulse
width

Y'N

OV

~. J'~,o"

Clock pulse
oUlllut
Input waveform:
PAR - 0.5 MHz
vp.p - 5.0V
t, - It s; to ns
Pull. width:
A.t.O P.s
B. 200 ns

10%

OV
V3 - OY

10%

~PW=¥

-

5V
Y'N

90%

90%

I--In..

5-5

VOUT
Vz = -laV

l--~oIr

TL/F/S852-S

Typical Application

v'

Tl/F/5852-4

AC Test Circuit

Tl/F15852-6
'01 Is selected high speed NPN switching transistor.

Typical Performance
Transient Power vs Rep. Rate

DC Power (Poc) vs Duty Cycle

~ ~~~~~r-~'--r~

110

i

I..

380

i

II!'"co

...
...

2GII

:5
;;
c

'"

148

100

/

DD
48

co

28

/

/

Vv'-vl=IJv_

/'

I

X

l~~

IP
10

2.D

.6

/

/ /

10

I'".

100

{.?j,

If

120

co

X

yo -V-=20V/

CI,-2OD01If Ct.-1a" Ct.-1108111'

20

30

48

68

80

70 86
TlIF/5B52-8

PULSE REPETITIOII RATE IMH.)
DUTY CYCLE (%)

TlIF/5B52-7

Poe ~ V L V-)2 (DC)

lk

Maximum Load capacitance
3208

.......

I

r: 24ft \',~

ri

r"~

\.

I{

I~.:: "
~

i5

1208

~ IDD

S

IlUTNTPl.R.SEWlDTtIvs.c.FQllLOMG

I I I

1100

f.-·+·'·--.T.-UC

S. ZIGI

...

_.+·'- .....
i'..
r--.. I'
I' r-....

~ I'....

:::+.-,!-..-:,,.TA..-lOf ?!

_......

Output PW Controlled by CIN

,T,-HC

j

..
ill

Ii

.
~

r--- .;;::

80D

=

FlllIlPUTPULSE<15 +1IeCI...
0UIPUlI'lllEWIITH-1NPUfPlllSEWlD'hI
...... &

700

1-1-

J..,\.J

HO

~
~

380

-

.....
~F'"

110

200

U 0.4 D.8 ... 1.D 1.2 1.4 1.8 1.1 2.D

_

1-11-1~

V

~=Dol":1-1~....,..

500 I1JU.UP

I I I
lDDD I . lDDD 2ZOG
C,N (PF)

FREIIUENCY (MHz)

TlIF/5B52-10

Tl/F/5B52-9

IMAX

Ct. < (PM,w (lk)-(V+

- V-)2 (DC) < (loki (1,)
(I) (lk) (V+
V)2
v+ - v-

~

Peak CUrrent delivered by driver

I
VBE_~
MIN Rl - lk

5-6

Applications Information
Circuit Operation

Transient Output Power
The average transient power (Pael dissipated, is equal to
the energy needed to charge and discharge the output capacitive load (CLl multiplied by the frequency of operation
(1).
PAC = CLX(V+_V-)2xf
(2)

Input current forced into the base of 01 through the coupling capacitor CIN causes 01 to be driven into saturation,
swinging the output to V- + VCE(sat) + VOiode.
When the input current has decayed, or has been switched,
such that 01 turns off, 02 receives base drive through R2,
turning 02 on. This supplies current to the load and the
output swings positive to V + -VeE.

ForV+ - V400 mW.

.....- -..-ov·

~
I;:

INPUT

RI
250

~~DI

Internal Power
"0" State
Negligible «3 mW)
"1" State
Pint =

OUTPUT

=

(V+_V-)2

x Duty Cycle
R2
80 mWforV+-V- = 20V, DC

(3)

= 20%

Package Power Dissipation
Total average power = transient output power
power.

01

+

internal

)

Example Calculation

~--~--~~------ov-

How many MM506 shift registers can be driven by a
DS0025CN driver at 1 MHz using a clock pulse width of 200
ns, rise time 30-50 ns and 16V amplitude over the temperature range 0" - 70"C?

TUF/5852-11

FIGURE 1. DS0025 Schematic (One-Half Circuit)
It may be noted that 01 must switch off before 02 begins to
supply current, hence high internal transients currents from
V- to V+ cannot occur.

Power Dlaalpatlon:
At 70·C the DS0025CN can diSSipate 870 mW when soldered into printed circuit board.

Fan-out Calculation
The drive capability of the DS0025 is a function of system
requirements, i.e. speed, ambient temperature, voltage
swing, drive circuitry, and stray wiring capacity.

Transient Peak Current limitation:
From equation (1), it can be seen that at 16V and 30 ns, the
maximum load that can be driven is limited to 2800 pF.

The following equations cover the necessary calculations to
enable the fan-out to be calculated for any system condition.

Average Internal Power:
Equation (3), gives an average power of 50 mWat 16V and
a 20% duty cycle.
For one-half of the DS0025C, 870 mW + 2 can be dissipated.
435 mW = 50 mW + transient output power.

Transient Current
The maximum peak output current of the DS0025 is given
as 1.5A. Average transient current required from the driver
can be calculated from:

1= CdV+-V-)

= 20V, f = 1.0 MHz, CL = 1000 pF, PAC =

385 mW = transient output power.
USing equation (2) at 16V, 1 MHz and 350 mW, each half of
the DS0025CN can drive a 1367 pF load. This is less than
the load imposed by the transient current limitation of equation (1) and so a maximum load of 1367 pF would prevail.

(1)

tr
Typical rise times into 1000 pF load is 25 ns. For V+ - V= 20V, I = 0.8A.

From the data sheet for the MM506, the average clock
pulse load is 80 pF. Therefore the number of devices driven
is 1367180 or 17 registers.
For further information please refer to National Semiconductors Application Note AN-76.

5-7

I

~

I

.------------------------------------------------------------------------,
~National

..... ~ semiconductor

I

080026/080056 5 MHz Two Phase M08 Clock Drivers
General Description
OS0026/0S0056 are low cost monolithic high speed two
phase MOS clock drivers and interface circuits. Unique circuit design provides both very high speed operation and the
ability to drive large capacitive loads. The device accepts
standard TTL outputs and converts them to MOS logic levels. They may be driven from standard 54174 series and
54S174S series gates and flip-flops or from drivers such as
the OS8830 or OM7440. The OS0026 and OS0056 are intended for applications in which the output pulse width is
logically controlled; i.e., the output pulse width is equal to
the input pulse width.
The OS0026/0S0056 are designed to fulfill a wide variety of
MOS interface requirements. As a MOS clock driver for long
silicon-gate shift registers, a Single device can drive over
10k bits at 5 MHz. Six devices provide input address and
precharge drive for a 8k by 16-bit 1103 RAM memory system. Information on the correct usage of the OS0026 in
these as well as other systems is included in the application
note AN-76.

output when it is in the high state. An external resistor tied
between these extra pins and a supply higher than V+ will
cause the output to pull up to (V+ - 0.1V) in the off state.
For OS0056 applications, it is required that an external reo
sistor be used to prevent damage to the device when the
driver switches low. A typical Vee connection is shown on
the next page.

Features
•
•
•
•
•

Fast rise and fall times-20 ns 1000 pF load
High output swing-20V
High output current drive-±1.5 amps
TTL compatible inputs
High rep rate-5 to 10 MHz depending on power dissipation
• Low power consumption in MOS "0" state-2 mW
• Drives to 0.4V of GNO for RAM address drive

The OS0026 and OS0056 are identical except each driver in
the 080056 is provided with a Vee connection to supply a
higher voltage to the output stage. This aids in pulling up the

Connection Diagrams (Top Views)
Dual-In-Llne Package
NI:

OUT A

y+

T0-8 Package

Dual-In-Une Pack_ge

or

I••

OUT B

I••

TUF/5853-3

Order Number
DSOO26G or DS0026CG
See NS Package
NumberG12B

Tl/F/5853-2

Order Number DS0026CJ-8,
DSOO26CL or OS0026CN
See NS Package Number

Ie

11fF'

Ie

Ie

aUTA

IN:

"

Ie

r

TUF/5853-4

Order Number
DS0026J or DSOO26CJ
see NS Package
NumberJ14A

J08Aor N08E

Dual-In-Llne Package
OUT A

or

v...

Dual-In-Llne Package

GUll

TUF/5853-7

Order Number DSO056J
V.A

INA

V-

or DSOO56CJ
See NS Package Number J14A

I••

TUF/5853-6

Order Number DS0056CN
See NS Package Number N08E
5-8

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V+ - V- Differential Voltage
22V
Input Current
100mA
Input Voltage (VIN - V-I
5.5V
Peak Output Current
1.5A
Maximum Power Dissipation' at 25'C
Cavity Package (8-Pin)
1150mW
Cavity Package (14-Pin)
1380mW
Molded Package
1040mW

EIAJ SO Package
Operating Temperature Range
DS0026, DS0056
DS0026C, DS0056C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

800mW
- 55'C to + 125'C
O"Cto +70"C
-65'C to + 15O"C
300"C

• Derate S..,in cavity package 7.7 mWI'C above 25'C; derate 14-pln cavity
package 9.3 mWrc above 25'C; derate molded package S.4 mWrc
above 25'C; derate metal can (To-5) package 4.4 mW/'C above 25'C;
derate EIAJ SO package 5.5 mWrC above 25'C.

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Condltlona

Min

Typ

2

1.5

Max

Un/ta

15

mA

VIH

LogiC "1" Input Voltage

V- = OV

IIH

Logic "1" Input Current

VIN - V- = 2.4V

10

VIL

Logic "0" Input Voltage

V- = OV

0.6

0.4

V

IlL

Logic "0" Input Current

VIN - V- = OV

-3

-10

p.A

VOL

Logic "1" Output Voltage

VIN - V- = 2.4V, IOL = 1 mA

V-+0.7

V-+1.0

V

VOH

Logic "0" Output Voltage

VIN - V- = O.4V, Vss ~ V+ + 1.0V
'OH=-1mA

DS0026

V+ -1.0

V+-0.8

V

050056

V+- 0.3

V+-0.1

V

ICC(ON)

ICC(OFF)

"ON" Supply Current

V+ - V- = 20V, VIN - V- = 2.4V

DS0026

30

40

mA

(one side on)

(Note 6)

080056

12

30

mA

"OFF" Supply Current

V+ - V- = 20V,
VIN - V- = OV

70"C

10

100

p.A

125'C

10

500

p.A

Switching Characteristics (TA =
Symbol
tON

25'C) (Notes 5 and 7)

Parameter
Turn-On Delay

tOFF

Turn-Off Delay

tr

Rise Time

Conditions
(Figure 1)

Fall Time

Min

Typ

Max

Units

5

7.5

12

ns

15

ns

(Figure 2)

11

(Figure 1)

12

ns

13

(Figure 2)

tf

V

ns

(Figure 1),
(Note 5)

CL = 500pF

15

18

ns

CL = 1000pF

20

35

ns

(Figure 2),
(Note 5)

CL = 500pF

30

40

ns

CL = 1000pF

36

50

ns

(Figure 1),
(Note 5)
(Figure 2),
(Note 5)

CL = 500pF

12

16

ns

CL = 1000pF

17

25

ns

CL = 500pF

28

35

ns

CL = 1000pF
31
40
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of \he device cannot be guaranteed. Except for "Operating Temparature Range"
they are not meant to imply that the devices should be oparated at these limits. The table of "Electrical Charecteristics provides oondltions for actual device
operation.

Note 2: These specificatlcns apply for y+ - y- = lOY to 20Y, CL = 1000 pF, over the temperature range of - 55'C to + 125'C for tile 080026, 0S0056 and
O'C to + 70'C for the OSOO26C, DS0056C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voIteges referenced to ground unless otherwise noted. All values shown
as max or min on absolu«t value basis.

Note 4: All typical values for TA = 25'C.
Rise and fall time are given for MOS logic levels; i.e., rise time is transltlcn from logic "0" to logic "1" which Is voltsge fall.
Note 6: Ise for 090056 Is approximately (Vee - Y-)/l kll (for one side) when output is low.
Note 7: The high current transient (as high as 1.5A) through the resistonce of \he internal Interconnecting Y- leed during tile output transition from the high stote to
\he low stote can app_ as negative feedbeck to the Input. If the external interconnecting leed from \he driving circuit to Y- is aleclricsily long, or has significant de
Note 5:

resistance, it can subtract from the switching response.

5-9

•

Typical VBB Connection

lk

Y-= -I2V

TLIF/5853-8

Typical Performance Characteristics

,.

Input Current va Input Voltage
L5

II

c

e
II!
f

II

!

I

.!

....

e...

.... V
-I

...

-I

Tum-On and Turn-Off Oslay
va Temperature

Supply Current va Temperature

13

i

(

I

11

-1.D-Q.5

0

Q.5 '.0 '.5

z.o

DUTY CYCLE· ""
'·1MHI
I
CL =0

LD

-

7.5
7.'
•. 5

....

...

I
I

V+-V·"'28V

1
;

1.

It

14

=:

.......

ie
V'-r-ITv

24
22
21
18
12
10

INPUT VOLTAGE IVI

to"
Vee -Z8V

I

i'"

Ct.' CL = ,ooa.F
_OII'NPUT
IFIGURE 21

i'!

-75 -II -2& 0 25 liD 75 'II ,2&
TEMPERATURE rCI

U

,.

to~

-liD -21

0

2S

51

71 'OIl 121

TEMPERATURE rCI

Fall Time va Load
Capacitance

Rlae Time va Load
Capacitance

...--,--..---r-..--,.-..,

40

30 1---+-+---+~+-''''''1---l

1
~

.

21

1--H!+--+:::;010~~

I--+-,If---+-+--t--i

20

!!l

o
lOll

401

601

110

L-...L......J._..L-~_L-..J

200

o

'OlIO 1201

-2.

'Recommended Input Coding
Capacitance

Jz40l

w 2200
1
2_

Y+-V-=ZOV

::11400
"1211

I~ 800

::110

/

~

311

32.

, DOO , 2DD

,.,..

....

.....TRANSlSTO~_
WITH 10 OH~_
TO 01

":-

,F
TL/F/5853-13

':"

TL/F/5853-12

FIGURE 1

.....,

PULIEGEI

TlIF/5853-15

TL/F/5853-14

FIGURE 2

Typical Applications
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Only)

AC Coupled MOS Clock Driver

,."

j_. . .

,."

LK

••

D_C_

~'F

TO SHIft
REalSTERI DR RAMI

+"¥

DSII11CII

j

TO,OD.EII
Lllloa•
MEMDRY IYITU1

M!74IERIEI
IATDMOFLON
-I2V

TL/F/5863-16

TL/F/5853-17

Application Hints
DRIVING THE MM5262 WITH THE
DSO056 CLOCK DRIVER
The clock signals for the MM5262 have three requirements
which have the potential of generating problems for the
user. These requirements, high speed, large voltage swing
and large capacitive loads, combine to provide ample opportunity for inductive ringing on clock lines, coupling clock
signals to other clocks and/or inputs and outputs and generating noise on the power supplies. Ail of these problems

have the potential of causing the memory system to malfunction. Recognizing the source and potential of these
problems early in the design of a memory system is the
most critical step. The object here is to point out the source
of these problems and give a quantitative feel for their magnitude.

5-12

Application Hints (Continued)
Line ringing comes from the fact that at a high enough frequency any line must be considered as a transmission line
with distributed inductance and capacitance. To see how
much ringing can be tolerated we must examine the clock
voltage specification. Figure 6 shows the clock specification, in diagram fonn, with idealized ringing sketched in. The

mation stored in the memory could be altered. Referring to
Figure 1, if the threshold voltage of a transistor were -1.3V,
the clock going to Vss - 1 would mean that all the devices,
whose gates are tied to that clock, would be only 300 mV
from turning on. The internal Circuitry needs this noise margin and from the functional description of the RAM it is easy
to see that turning a clock on at the wrong time can have
disastrous results.
Controlling the clock ringing is particularly difficult because
of the relative magnitude of the allowable ringing, compared
to magnitude of the transition. In this case it is 1V out of 20V
or only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.
Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
slows down the rise and fall time of the clock signal. Because the typical clock driver can be much faster than the
worst case driver, the damping resistor serves the useful
function of limiting the minimum rise and fall time. This is
very important because the faster the rise and fall times, the
worse the ringing problem becomes. The size of the damp-

V.+1:::::::~------------------Jr~~~
v.

V.-l:======~==================t=====:::

·VTIMINI

TL/F/5853-18

FIGURE 6. Clock Waveform
ringing of the clock about the Vss level is particularly critical.
If the Vss - 1 VOH is not maintained, at aI/times, the infor-

v·

R.

RB

D!,.

r-;;, ,. . .

RI

•0;.

.....

"'-;'7
~

~

....01

~

......

.....
, ....
D7

RZ

EXTERNAL

C'N

....Q6

o-f~PU0 - -

~ ~D'

T

I~
.......
Rl

....""

y

OUTPUT

II

~02

~
.....
R4

I~
......

,

I.
RI

1

~
".

.....04

....

~~Ol'
01

~
~

R7

~

vTlIF/5853-11

FIGURE 7. SchematiC of 112 DS0056

5-13
--

-

-- -------------------

Application Hints (Continued)
saturate, pulling the output to within a VeE(SAT) of the V+
supply. This is critical because as was shown before, the
VSS - 1.0\1 clock level must not be exceeded at any time.
Without the VBB pull up on the base of 08 the output at best
will be 0.6V below the V+ supply and can be 1V below the
V+ supply reducing the noise margin on this line to zero.

ing resistor varies because it is, dependent, on the details of
the actual applipa~ion. It must be determined empirically. In
practice a resistance of 100 to 200 is usually optimum.
Limiting the inductance of the clock lines can be accomplished by minimizing their length and by laying out the lines
such that the return current is closely coupled to the clock
lines. When minimizing the length of clock lines it is important to minimize the distance from the clock driver output to
the furthest pOint being driven. Because of this, memory
boards are usually designed with clock drivers in the center
of the memory array, rather than on one side, reducing the
maximum distance by a factor of 2.

Because of the amount of current that the clock driver must
supply to its capacitive load, the distribution of power to the
clock driver must be considered. Figure 8 gives the idealized voltage and current waveforms for a clock driver driving
a 1000 pF capaCitor with 20 ns rise and fall time.
As can be seen the current is significant. This current flows
in the Vee and VSS power lines. Any significant inductance
in the lines will produce large voltage transients on the power supplies. A bypass capacitor, as close as possible to the
clock driver, is helpful in minimizing this problem. This bypass is most effective when connected between the Vss
and Vee supplies. A bypass capacitor for each 050056 is
recommended. The size of the bypass capacitor depends
on the amount of capacitance being driven. Using a low
inductance capaCitor, such as a ceramic or silver mica, is
most effective. Another helpful technique is to run the Vee
and Vss lines, to the clock driver, adjacent to each other.
This tends to reduce the lines inductance and therefore the
magnitude of the voltage transients.

Using multilayer printed Circuit boards with clock lines sandwiched between the Vee and Vss power plains minimizes
the inductance of the clock lines. It also serves the function
of preventing the clocks from coupling noise into input and
output lines. Unfortunately multilayer printed circuit boards
are more expensive than two sided boards. The user must
make the decisiQn as to the necessity of multilayer boards.
Suffice it to say here, that reliable memory boards can be
deSigned using two sided printed circuit boards.
The recommended clock driver for use with the MM42621
MM5262 is the 050056/050056C dual clock driver. This
device is designed specifically for use with dynamic circuits
using a substrate, VBB, supply. Typically it will drive a 1000
pF load with 20 ns rise and fall times. Figure 7 shows a
schematic of a single driver.

While discussing the clock driver, it should be pOinted out
that the 050056 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.

In the case of the MM5262, V+ is a + 5V and VBB is
+ 8.5V. VBB should be connected to the VBB pin shown in
Figure 7 through a 1 kO resistor. This allows transistor 08 to
.6V - - - - - . , - - - - _

-ISV

Lastly, the clock lines must be considered as noise generators. Figure 9 shows a clock coupled through a parasitic
coupling capacitor, Ce, to eight data input lines being driven
by a 7404. A parasitic lumped line inductance, L, is also
shown. Let us assume, for the sake of argument, that Cc is
1 pF and that the rise time of the clock is high enough to
completely isolate the clock transient from the 7404 because of the inductance, L.

r

ZGns

ZG .. - /

'~-D

-IAMP----D
.I.SV

Vss
6V

TL/F/5853-20

FIGURE 9. Clock Coupling
With a clock transition of 20V the magnitude of the voltage
generated across CL is:

V = 20V x

lL .,

c L X .:loy
"t

11t9 F·2DV
= 20 x lit.....

IA

~=
CL+Ce

20V X (_1_) = 0.35V
56+1

This has been a hypothetical example to emphasize that
with 20V low riselfall time transitions, parasitic elements
can not be neglected. In this example, 1 pF of parasitic
capaCitance could cause system malfunction, because a
7404 without a pull up resistor has typically only 0.3V of

TUF/5853-19

FIGURE 8. Clock Waveforms (Voltage and Current)

5-14

Application Hints (Continued)
noise margin in the "1" state at 25·C. Of course it is stretching things to assume that the inductance, L, completely isolates the clock transient from the 7404. However, it does
point out the need to minimize Inductance in input/output as
well as clock lines.
The output is current, so it is more meaningful to examine
the current that is coupled through a 1 pF parasitic capacitance. The current would be:
I

= Cc x

!:tN
At

=

1 x 10- 12 X 20
20 X 10-9

Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previously, physically isolating clock lines and/or running clock
lines at right angles to input/output lines. All of these techniques tend to minimize parasitiC coupling capacitance from
the clocks to the signals in question.
In considering clock coupling it is also important to have a
detailed knowledge of the functional characteristics of the
device being used. As an example, for the MM5262, coupling noise from the 2 clock to the address lines is of no
particular consequence. On the other hand the address inputs will be sensitive to noise coupled from 1 clock.

= 1 mA

This exceeds the total output current swing so it is obviously
significant.

Packaging Information

0.039
(1.000)

rl
c +r
0.031

7.

C

*~=~j
f

0.005
(0.200)

.1

U

_.

I-,. j I 5·

(2.030)

t

R 0.005
(0.200)

)

I

-

.!:!!!. MAX

(1.00)
~

0.2&0
(6.&04)0.025
(0.&50)

••

(0.720±0.050)--0.028±0.002
TVP
0.050±0.1JO.4
(1.270±0.100)
TYP
TL/F/5853-21

8-Lead Surface Mount Package
Order Number DSOO26CL

II

5-15

~National

~ Semiconductor

0875325
Memory Drivers
General· Description
The OS75325 is a m()nol,t~ic memory driver which features
high current outputs as well as internal c\ecoding of logic
inputs. This circuit is designed for use with magnetic memories.

to operate at higher source currents for a given junction
temperature. If this method of source current setting is not
desired, then Nodes Rand RINT can be shorted externally,
activating an internal resistor connected from VCC2 to Node
R. This provides adequate base drive for source currents up
to 375 mA with VCC2 = 15V or 600 mAwith VCC2= 24V.

The circuit contains two 600 mA sink-switch pairs and two
600 mA source-switch pairs. Inputs A and 8 determine
source selection while the source strobe (S1) allows the
selected source turn on. In the same manner, inputs C and
o determine sink selection while the sink strobe (S2) allows
the selected sink turn on.
Sink-output collectors feature an internal pull-up resistor in
parallel with a clamping diode connected to VCC2. This protects the outputs from voltage surges associated with
switching inductive loads.
The source stage features Node R which allows extreme
flexibility in source current selection by controlling the
amount of base drive to each source transistor. This method
of setting the base drive brings the power associated with
the resistor outside the package thereby allowing the circuit

•
•
•
•
•
•
•

Connection Diagram

Truth Table

Features

Dual-In-Line Package
VCC2

X

B

NODE
R

RINT

0

Z

600 mA output capability
24V output capability
Dual sink and dual source outputs
Fast switching times
Source base drive externally adjustable
Input clamping diodes
TTL compatible

Address Inputs Strobe Inputs
Source
Sink Source Sink
A
B C 0
S1
S2
L
H X X
L
H
L
H
H
L X X
X
X L H
H
L
X
X H L
H
L
X
X X X
H
H
H H H
H
X
X

VCC1

Outputs
Sink
X
Y
Z

,Source

W
ON
OFF
OFF
OFF
OFF
OFF

OFF
ON
OFF
OFF
OFF
OFF

H = High Level, L = Low Level, X = Irrelevant
Note: Not more than one output is to be on at anyone time.

SOURCE W
COL1ECfORS

A

SI

S2

c

y

GND

'----.---I

STROBES
TUF/9755-2

Top View

Order Number DS75325N
See NS Package Number N14A

5-16

OFF
OFF
ON
OFF
OFF
OFF

OFF
OFF
OFF
ON
OFF
OFF

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7V
Supply Voltage VCCl (Note 5)
Supply Voltage VCC2 (Note 5)
25V
Input Voltage (Any Address or Strobe Input)
5.5V
Maximum Power Dissipation' at 25°C
Cavity Package
1509mW
Molded Package
1476mW
'Derate cavity Package 10.1 mW/'C above 25'C; derate molded package
11.8 mW/'C above 25·C.

-65°C to + 150"C

Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

300"C

Operating Conditions
Temperature (TA)
OS75325

Min

Max

Units

0

+70

°C

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

VIH

High Level Input Voltage

(Figures 1 and 2)

VIL

Low Level Input Voltage

(Figures 3 and 4)

VI

Input Clamp Voltage

VCCl = 4.5V, VCC2 = 24V,IIN
TA = 25°C (Figure 5)

IOFF

Source Collectors Terminal
"Off" State Current

VCCl

Min

= 4.5V, VCC2 = 24V

Full Range

(Figure 1)

= 25°C

VSAT

Saturation Voltage Source
Outputs

VSAT

Saturation Voltage
Sink Outputs

-1.7

V

OS55325

500

pA

OS75325

200

pA

3

150

p.A

3

200

p.A

OS55325

= 4.5V, VCC2 = 24V, lOUT = 0 mA (Figure 2)
VCCl = 4.5V, VCC2 = 15V, Full Range
RL = 240,
ISOURCE :=: - 600 rnA
TA = 25°C OS55325
VCCl = 4.5V, VCC2 = 15V,
RL = 240,
ISINK :=: 600 mA (FlfJure 4)
(Notes 4 and 6)

II

Input Current at Maximum
Input Voltage

VCCl = 5.5V, VCC2 = 24V,
VI = 5.5V (Figure 5)

IIH

High Level Input Current

VCCl = 5.5V, VCC2 = 24V,
VI = 2.4V (Figure 5)

IlL
ICC OFF
ICCl

Low Level Input Current

TA = 25°C (Figure 6)

Supply Current from VCC1,
Either Sink "On"

VCCl = 5.5V, VCC2 =
TA = 25°C (FlfJure 7)

23
0.9

= 25°C

V

0.43

0.7

V

0575325

0.43

0.75

V

0.9

V

OS55325

0.43

0.7

V

OS75325

0.43

0.75

V

1

mA

2

mA

Full Range
TA

V

Address Inputs
Strobe Inputs
3

40

pA

Strobe Inputs

6

80

p.A

Address Inputs

-1

-1.6

mA

Strobe Inputs

-2

-3.2

rnA

VCCl

14

22

rnA

VCC2
24V,ISINK = 50 mA,

7.5

20

mA

55

70

mA

= 5.5V, VCC2 = 24V,

Supply Current, All Sources
and Sinks "Off"

19

Address Inputs

VCCl = 5.5V, VCC2 = 24V,
VI = 0.4V (Figure 5)
VCCl

V

-1.3

VCCl

(Figure 3) (Notes 4 and 6)

Units
V

OS75325
High Level Sink Output Voltage

Max
0.8

= -12rnA

TA
VOH

Typ

2

Supply Current from VCC2,
VCCl = 5.5V, VCC2 = 24V, ISOURCE = -50 mA
32
50
mA
Either Source "On"
TA = 25°C (Figure 8)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at thase limits. The table of "Electrical Characteristics" provides conditions for ectual device
operation.
Note 2: Unless otherwise specified min/max limits spply across the - 55'C to + 125'C temperature range for the 0555325 and across the O'C to + 70'C range for
the 0875325. All typical values are at TA = 25'C.
Note 3: All currents Into device pins shown as positive, out of device pins as negative, all voltegee referenced fo ground unlass otherwise noted. All value. shown

ICC2

as max or min on absolute value basis.

Note 4: Only one output at a time should be shorted.
Note 5: Voltage values are with respect to network ground terminal.
Note 6: These parameters must be measured using pulse techniques. tw = 200 ,.., duty cycle :<:2%.

5-17

•

Switching Characteristics VCC1
Symbol

Typ

Max

Units

VCC2 = 15V, RL = 240,
CL = 25 pF (Figure 9)

Source Collectors

25

50

ns

Sink Outputs

20

45

ns

Propagation Delay Time,
High-to-low level Output

VCC2 = 15V, ~L = 240,
CL = 25 pF (Figure 9)

Source Collectors

25

50

ns

Sink Outputs

20

45

ns

Transition Time,
low-to-High level Output

CL = 25pF

Source Outputs, VCC2 = 20V,
RL = 1 kO (Figure 10)

55

Sink Outputs, VCC2 = 15V,
RL = 240 (Figure 9)

7

Source Outputs, VCC2 =20V,
RL = 1 kO (Figure 10)

7

Sink Outputs, VCC2 = 15V,
RL = 240 (Figure 9)

9

20

ns

15

30

ns

tpLH

tpHL

trLH

ts

Min

Conditions

Propagation Delay Time,
low-to-High level Output

tTHL

= 5V, T A = 25°C

Parameter

Transition Time,
High-to-low level Output

Storage Time, Sink Outputs

CL = 25pF

VCC2 = 15V, RL = 240, CL = 25 pF (Figure 9)

DC Test Circuits
24V

-R---~

2Vo--

-

CC2

SOURCE
COLLECTORS

-

:'~

(SEE
TEST
TABLE)

r~

~-----.
V

-

-.

t(OFF)

W

x
I~

-

Y

C

!

S2

ZI

,D~

I
I
I
I
I

. -1-':"-------- _..
-:.:
4~V
-

I

GND

VCC1

Test Table

A

B

GND GND
2V

2V

Sl
2V
GND

FIGURE 1_ IOFF

5-18

OPEN

OPEN

TL/F/9755-3

ns
15

ns
ns

.----------------------------------------------------------------------.0
til
.....

DC Test Circuits (Continued)

~
t.)
en

24V

-----,
L.....J'M-tVCC2

I

SOURCE:
COLLECTORS I

RINT

A

4.5V

4'5V~
2V

I
I

Test Table

WI

o-....._+S..;.I..

c

0

S2

y

Z

2V

4.5V

GND

VOH

GND

4.5V

2V

VOH

OPEN
OPEN

4.5V

GND OPEN
GND 2V OPEN

4.5V

2V

VOH
VOH

OPEN

(SEE
TEST

TABLE)
I

~

-r--------

1

_GN!__ •

4.5V

TL/F/9755-4

FIGURE 2. VIH and VOH
15V

350

5V

4.

l

OPEN

-----.I

~~~.VCC2

SOURCE:
COLLECTORS I

Test Table
(SEE
TEST
TABLE)

O.BV

I
152

A

B

S1

O.SV

4.5V

O.SV

4.5V

O.SV

O.SV

Zl

10

4.5V
TLlF/9755-5

Note 1: FIgUre 3 and 4 parameters musl be measured using pulse techniques. tw

FIGURE 3. VIL and Source VSAT

5·19

X

•

r--';';"-OOPEN
I
I
~~~-OOPEN

I

W

GND OPEN
OPEN GND

= 200 ,.s. duly cycle'; 2%.

U)

C\I
CO)

U)

~

r---------------------------------------------------------------------------------,
DC Test Circuits (Continued)
15V

.................-0 OPEN

A

B

lk

8V
O.

l

x
y

l'SINK
(SEE
TEST

TABLE)

4.SV

1

4.5V

TLlF/9755-6

Note 1: F/gurs3and 4 parameters must be maasured using pulse techniques, tw

= 200 ,",S, duty cycle <:2%,

Test Table

c

0

S2

y

Z

O,BV

4.5V

O.BV

RL

OPEN

4,5V

O.BV

O.BV

OPEN

RL

FIGURE 4. VIL and Sink VSAT

5-20

DC Test Circuits (Continued)
24V

R

-----

......,\M;...... VCC2

.
I

SOURCE:
COLLECTORS

.....................-0 OPEN
5.5V

w
x

(SEE
TEST
TABLE)

,...."";Y-i--o OPEN

,....t----!--o OPEN

I

~-l--------"!!_

-'

5.5V

(4.5V FOR
TESnNG V~
TUF/9755-7

Test Tables

Apply VI = 5.5V
Measure II

Apply VI = 0.4V
Measure IlL

Ground

Apply5.5V

51
A,B

B,C,52,O

A

C,52,O

51

A,B,C,52,O

A,C,52,O
A,51, B, 0

B
C

A, 51, C, 52, 0
A,51,B,52,O

52

51
52
C,O

A,51,B

52

A,51,B,C,O

0

52

A,51,B,C

0

A, 51, B, C, 52

Apply II = -10 rnA
Measure VI

Apply VI = 2.4V
MeasurellH

A
51
B
C

FIGURE 5. Vb 110 IIH and IlL

5-21

Apply5.5V

51, B, C, 52,0

•

~

"(\I

~

§

.--------------------------------------------------------------------------,
DC Test Circuits (Continued)
24V

!

lea (OFF)

----- ..

I
I
I
I
IA

"'-'W\o-" Vea

...........-r-oQ OPEN

I
18

5V

I
I
I
I
Ie

y
. - - - ; - - 0 OPEN

I
I S2

......-t-~-oQ OPEN

I
ID
I
I

·-11 :~: -----_-~
VCC!

GND

5.5V

TL/F/9755-8

FIGURE 6.ICC1 (OFF) and ICC2 (OFF)

5-22

DC Test Circuits (Continued)
24V

V-----~
CC2

OPEN

A

4.5V

W

0--+-.......-+
B

Y
ISINK

= 50mA

::;\

l
5.5V

TL/F/9755-9

Test Table

C

GND
5V

D

S2

Y

Z

GND ISINK OPEN
GND GND OPEN ISINK
5V

FIGURE 7.ICC1. Either Sink On

II

5-23

I

DC Test Circuits """""""

5V

1:

!Isou~ =

-50mA

y

...---i--o OPEN
1
152

z

...-~~-o OPEN

1
10
1
1 VCCI

.- ----------

GNO

-"

5.5V

TL/F/97SS-10

Teat Table
A

B

S1

GND

5V

GND

5V

GND

GND

FIGURE 8.1cc2. Either Source On

5-24

i.....

DC Test Circuits (Continued)

U'I

Co)
~

U'I

ISV

INPUT

r-........,.--....--+-+-o COLLECTORS
SOURCE

PULSE
GENERATOR
(NOTE I)
50

x

(SEE
TEST
TABLE)

y
r--"""'T---~-+-+-o OUTPUT V

C

CL
2SpF

S2

.I.

z

.-+-~------+-o OUTPUT Z

CL
I 2 S PF

D
I
I

,,-VCCI
SV
TL/F/9755-11

Note 1: The pulse generator has the following characteristics: ZoUT - 50n. duty cycle,;; 1 %.
Note 2: CL includes probe and jig capacitance.

Voltage Waveforms
3V
INPUT

OV

OUTPUT

TL/F/9755-12

Test Table
Parameter
tpLH and tpHL

tpLH, tpHL,
trLH, trHL and Is

Output Under Test
Source Collectors

Input

B,C,DandS2

B and S1

A,C, D and S2

Sink Output Y

C and S2

A, B, Dand S1

Sink Output Z

D and S2

A, B,CandS1

FIGURE 9. Switching Times
5·25

---~.

Connect to 5V

AandS1

- ._--- --

DC Test Circuits (Continued)
20V

INPUT

I
I
WI

PULSE
GENERATOR
(NOTE 1)

~
2SpF

}MM

RL
lk

(SEE
TEST

I
VI

TABLE)

~
2SpF

RL
lk

I
I
Zl

SV
TUF/9755-13

Note 1: The pulse generator has the following characteristics: ZOUT
Note 2: CL includes probe and jig capacitance.

= 50n, duty cycle,;

1"".

Voltage Waveforms

3V

INPUT
OV

VOH
OUTPUT

TUF/9755-14

T..tTabie
Parameter
trLH and trHL

Output Under Test

Input

Connect to 5V

Source Output W

A and S1

B,C,OandS2

Source Output X

BandS1

A,C,OandS2

FIGURE 10. Transition Tim.. of Source Outpllta

5-26

0

!!l
CI'I

Schematic Diagram

Co)

VCC1

N
CI'I

VCC2

4k

4k

8k

575
RINT

SOURCE
COLLECTORS

ADIlRE55 A

OUTPUT W

SlROBE S1

NODE R

4k

4k

8k

ADDR~SBo---~~----~r-----1r-------1

...----0

OUTPUT X

5k

.---t-+IIH"""....-1-+---o OUTPUT Y

ADDRE55 C o--+-.
STROBE S2 o-_-J.J---....::t---1~------j

5k

~---~~t-~~~~-----oOUTPUTZ

ADDRESS D

0-+--.

t------~------~--------~-------~-------o~D
TLlF/9755-1

5-27

~.r---------------------------------------------------------------------------------~

N

CO)
~

§

Applications
EXTERNAL RESISTOR CALCULATION
A typical magnetic-memory word drive requirement is shown
in FigUfB 11. A source-output transistor of one 0575325
delivers load current (Ill. The sink-output transistor of another 0575325 sinks this current.
The value of the external pull-up resistor (Rextl for a particular memory application may be determined using the following equation:

After solving for Rext, the magnitude of the source collector
current (Ics) is determined from Equation 3.
les ~ 0.94 IL
(3)
where: Ics is In rnA.
As an example, let VCC2(Mln) = 20V and VL = 3V while IL
of 500 rnA flows. Using Equation 1:
16(20 - 3 - 2.2)
= 0.5kU
500 - 1.6 (20 - 3 - 2.9)
and from Equation 2:
500
PRext ~ 16 [20 - 3 - 21 ~ 470 mW
R

16 [VCC2(Mlnl - Vs - 2.2]
(1)
IL -1.6 [VCC2(Min) - Vs - 2.9]
where: Rext is in kU,
VCC2(Min) is the lowest expected value of VCC2 in volts, Vs
is the source output voltage in volts with respect to ground,
IL is in mA.
The power dissipated in resistor Rext during the load current
pulse duration is calculated using Equation 2.

R

-

ext -

PReld ~

IL
16 [VCC2(Min) - Vs - 21

=

ext

The amount of the memory system current source (lcg)
from Equation 3 is:
Ics ~ 0.94 (500) ~ 470 mA
In this example the regulated source-output transistor base
current through the external pull-up resistor (Rextl and the
source gate is approximately 30 mAo This current and Ics
comprise IL.

(2)

where: PRext is in mW.

REXT

------.

r---------

SOURCE
COlLECTORS

ONE

0S55325/
0575325
SOURCE

-----_.
A OR B

1
Vs

MEMORY
ELEMENT

lONE

Y OR Z

: 0555325/
I 0575325
I
I

SINK

-----_.
GNO

TLlF/9755-16

Note 1: For clarity, partial logic diagrams of two 08553260 are shown.
Nota 2: Source and sink shown are in different packages.

FIGURE 11. Typical Application Data

5-28

~National

~ semiconductor

DS75361 Dual TTL-to-MOS Driver
General Description

Features

The DS75361 is a monolithic integrated dual TTL-to-MOS
driver interface circuit. The device accepts standard TTL
input signals and provides high-current and high-voltage
output levels for driving MOS circuits. It is used to drive
address, control, and timing inputs for several types of MOS
RAMs including the 1103 and MM5270 and MM5280.

•
•
•
•
•
•
•
•
•

The DS75361 operates from standard TTL 5V supplies and
the MOS Vss supply in many applications. The device has
been optimized for operation with VCC2 supply voltage from
16V to 20V; however, it is designed for use over a much
wider range of VCC2.

Capable of driving high-capacitance loads
Compatible with many popular MOS RAMs
VCC2 supply voltage variable over wide range to 24V
Diode-clamped inputs
TTL compatible
Operates from standard bipolar and MOS supplies
High-speed switching
Transient overdrive minimizes power dissipation
Low standby power dissipation

Schematic and Connection Diagrams
Dual-In-Llne Package
(1/2 shown)

VCC1

Vee,

Y1

Y2

8

YCC2

6

5

".::::: /...-------..

INPUT A

OUTPUT Y

ENABLE E

2
A1

E

4
A2

GND
TL/F17557-1

N __ /

Top View

DRIVERS

GND
':'

TL/F17557-3

5-29

Order Number DS75361N
See NS Package Number NOSE

II

Absolute Maximum Ratings (Note 1)
Lead Temperature 1/16 inch from Case for
10 Seconds: N or P Package
'Derate molded package 8.2 mWr above about 2S'C.

If Military/Aerospace specified devices are reqUired,
please contact the National Semiconductor sales
Office/Distributors for availability and speclflcetlons.
Supply Voltage Range of VCCl (Note 1)
-0.5to7V
-0.5Vto 25V
Supply Voltage Range of VCC2
Input Voltage
5.5V

Inter·lnput Voltage (Note 4)
Storage Temperature Range
Maximum Power Dissipation' at 25·C
Molded Package

200"C

Operating Conditions
Min
4.75
4.75
0

Supply Voltage (VCC1)
Supply Voltage (VCC2)
Operating Temperature (TA)

5.5V
- 65·C to + 150"C

Max
5.25

Unite
V

24
+70

V
·C

1022mW

Electrical Characteristics (Notes 2 and 3)
Symbol

Paremeter

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

Conditions

Min

Typ

Max

2

Units

V
0.8

V

-1.5

V

VI

Input Clamp Voltage

11= -12mA

VOH

High-Level Output Voltage

VIL = 0.8V, IOH = -50 ",A

VCC2- 1

VCC2 - 0.7

V

VIL = 0.8V, IOH = -10 mA

VCC2 - 2.3

VCC2 - 1.8

V

VOL

Low·Level Output Voltage

VIH = 2V, IOL = 10 mA

0.15

0.3

V

VCC2 = 15Vto 24V, VIH = 2V,
IOL = 40mA

0.25

0.5

V

Vo

Output Clamp Voltage

VI = OV, IOH = 20 mA

II

Input Current at Maximum
Input Voltage

VI = 5.5V

IIH

High·Levellnput Current

IlL

Low·Levellnput Current

VI = 2.4V

VI = 0.4V

Supply Current from VCC1, Both
Outputs High

ICC2(H)

Supply Current from VCC2, Both
Outputs High

ICC1(L)

Supply Current from VCC1, Both
Outputs Low

ICC2(L)

Supply Current from VCC2, Both
Outputs Low

V

1

mA

A Inputs

40

p.A

E Input

80

p.A

-1

-1.6

mA

-2

-3.2

mA

2

4

rnA

0.5

rnA

16

24

rnA

7

11

rnA

A Inputs
, E Input

ICC1(H)

VCC2 + 1.5

VCCl = 5.25V,
All Inputs at OV,

VCC2 = 24V,
No Load

VCCl = 5.25V,
All Inputs at5V,

VCC2 = 24V,
No Load

Supply Current from VCC2,
VCCl = OV,
VCC2 = 24V,
0.5
rnA
Stand·by Condition
All Inputs at5V, No Load
Nota 1: "Absolute Maximum Ratings" are tho.. values beyond which tha safety of tha davlca cannot be guarantaed. Except for "Operating Temperature Range"
thay are not maant to Imply that tha devices should be operated at thasa limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: UnlessothelWise specified minImax limits apply across thaO"C to +70"C range for Ihe 0575361. All typical values are forTA = 25'C and VCC1 = SVand
VCC2 = 20V.
Note 3: All currants Into device pins shown as positive, out of device pins as negetlva, all voltages referenced to ground unless olhelWise noted. All values shown
as max or min on absolute value basis.
Note 4: This rating applies between tha A input of elthar driver and the common E input

ICC2(S)

5·30

Switching Characteristics VCCI = 5V, VCC2 = 20V, TA = 25"C
Symbol

Parameter

Conditions

Min

Typ

Max

Units
ns

tOLH

Delay Time, Low-to-High Level Output

11

20

tOHL

Delay Time, High-to-Low Level Output

18

ns

trL.H

Transition Time, Low-to-Hlgh Level Output

CL = 390pF,
Ro = 100

10
25

40

ns

trHL

Transition Time, High-to-Low Level Output

(Figure 1)

21

35

ns

tPLH

Propagation Delay Time, Low-to-High Level Output

10

36

55

ns

tpHL

Propagation Delay Time, High-to-Low Level Output

10

31

47

ns

I...

AC Test Circuit and Switching Time Waveforms
INPUT

l

IV

20V

rvcc.t jv

eco - '

PULSE
I
GENERATOR!
(NOTEI)

I

"-

I
I

L

I
I

--!-- .J
GNO

RD

'..J-~

OUTPUT

CL
IINOTU)

2.4V
TL/F17557-4

~10n._

3V

1:8'1.
V

INPUT

.::I

I

UV

DV--l!!I

.....

'.IV

1\,8'1.

i-tpHL-

1--.... -

-

'DHLI-'THL

VDH
VCCO-3V\

'.LH-

OUTPUT

VOL

1-"~10 ..

IIOlI

i

2V

I--'TLH
~.
3V
Vcco-

2V
TLlF17557-5

Note 1: The pulse generator has the following characteristics: PRR

= 1 MHz, lour

- 50n.

Note 2: CL Includes probe and Jig capacltance.

FIGURE 1. Switching Times, Each Driver

5-31

II

Typical Performance Characteristics
High-Level Output Voltage vs
Output Current

Voltage Transfer
Characteristics

Low-Level Output Voltage VB
Output Current
11.&

~

~

=
c
!:i
=
-1.'
I;

w

-0.&

S -u

.....~
...
>

I;

HttHlII-H

:

YCCl =5V

~ -2.5

YCC2 - 2DY

E

Veel ~ 5V
Vcca = 20Y
D.4 l-y,_IY

."

D.2

i

V.-o.av

-3.0 1..LJ.W1IIL.u.
-11.01
-1.1
-1

-1'

11.1

a

a

-1110

HIGH·LEVEL OUTPUT CURRENT ImAI

1_r-~~~~~rTrrnT~

f

I

.....
...h

i
i

c ..

lID
5DI

~&a1

=~
it
.. !!

e

410

3111

.

2DI

1111

•

D.1

D.2

f~

Ii>:'

FREOUENCY 1101Hz!

41

!S

-

3&
3D

=~ zs
~~

cow

=$

!;i

f'I!!
..
f~

CL-311pF

A
CL ·2III,F

I,....; I-"'"

ze

-

>--

VCCt '" IV

10

o

RD -10n

T.-2rC
IFIGURE 11

a

25

~'50lpF

21

11

ze

VCC2 =20Y

NO LOAO
TA ' j5'C

..1

35

~E

30

...
~I;

I--

w.
COw

-

,,>
COW

5i

1-:'
L"

VCCt· liV

.

VceI ·21V

f~

RD = 10n

IFIGURE 11

11'"

.....
SS
j:~

w.
COw
..
>
.. w

14

I I

c!

H

2D

11 21 H 40 " • H
AMBIENT TEMPERATURE rCI

Vcc1 ·IV
VCC! .. 2tV

IFIGURE 11

011203041.1170.

AMBIENT TEMPERATURE I'CI

3D
25

..1
CL"HDpFY

V

21

~~

/ ' r--

/

15

....

II;

"'J!:
~~
cow

=;

;::=
e ..

......1=...

. t'

10

Propagation Delay Time,
Low-to-High Level Output
vs Load CapaCitance
&11

=5V

Veel

f~

o
112162024

SUPPLY YOLTAGE IVI

Vee,· IV
Vccz" IOV
TA =2&oC

50

r---

RD -lOu

30

~

,7

L~
... ~

20

HO-~ ~
L'

IFIGUHEII

40

.-

,/

::..-Ho=O-

10
I

D

I--

I I
I I

RD"".U

II

.J,PF I-

c~ .JPF

,.

15

lE

t- Ro -ID!!
t- r~;::~CII

35

2.5

CL -31DpF

I

40

D.&

Propagation Delay Time,
Hlgh-to-Low Level Output
vs Ambient Temperature

Propagation Delay Time,
High-to-Low Level Output
vs VCC2 Supply Voltage
wi

a

INPUTVOLTAGEIVI

"' ...

1&
10

a

lE

12

Vee1 = IV

40

CL-2DDpF

a

..........!i~.,.
f~

15

12

a

38

'\

"

2a
41
ao
II
loa
LOW·LEVEL OUTPUT CURRENT ImAI

CL- 3IOpF

Propagation Delay Time,
Low-to-Hlgh Level Output
vs VCC2 Supply Voltage

.. A

>

3&

L~

,

...

~=O'C

41

.i

;:: 7811

2D

w

Propagation Delay Time,
Low-to-Hlgh Level Output
vs Ambient Temperature

Total Dissipation (Both Drivers)
vs Frequency

II ...

..~
..
..~

~

l/

w

il::

~

TA.~ ~

0.3

E

H-IrttfIIIl-+t

co
~ -2.0

14

a

1ID

zoa

30a

40D

&DO

lID

LOAD CAPACITANCE IIoFI

SUPPLY VOLTAGE IVI

Propagation Delay Time,
Hlgh-to-Low Level Output
vs Load CapaCitance
8D

'i

if~

50

c ..

40

....
"'J!:

..... .,.
ii~

Zw

!iii

~I!!
..L"
=
lE

Vcc,· sv
Vccz· ZIV
T. -2rC
IFIGURE 11

Ro=MY"

Rg =11n

31

4 ::::::

~;;G: :::::(':'0

10

~

~

10
D

o

lID

loa

3DII

410

lID

8DD

LOAD CAPACITANCE IpFI
TL/F/7557-2

5-32

Typical Applications
The fast switching speeds of this device may produce undesirable output transient overshoot because of load or wiring
inductance. A small series damping resistor may be used to
reduce or eliminate this output transient overshoot. The
5V

19.5V

optimum value of the damping resistor to use depends on
the specific load characteristics and switching speed. A typical value would be between 100 and 300 (Figure 3).

1&.1V

5V

Vee,
..... A

nL {
INPUTS

nL
} INPUTS

0$15361
(2 PACKAGES)

TUF/7557-7

Note: RD ::: lOll to 301l (Optional).

FIGURE 3. Use of Damping
Resistor to Reduce or Eliminate
Output Transient Overshoot in
Certain DS75361 Applications
Tl/F17557-6

FIGURE 2. Interconnection of DS75361 Devices with 1103 RAM

Thermal Information
The OS75361 is so designed that Ps is a negligible portion
of P-r In most applications. Except at very high frequencies,
tL + tH > tLH + tHL so that Ps can be neglected. The total
diSSipation curve for no load demonstrates this point. The
power dissipation contributions from both channels are then
added together to obtain total device power.

POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the OS75361 driver
when charging and discharging high-capacitance loads over
a wide voltage range at high frequencies. The total dissipa·
tion curve shows the power dissipated in a typical OS75361
as a function of load capaCitance and frequency. Average
power dissipated by this driver can be broken into three
components:

The following example illustrates this power calculation
technique. Assume both channels are operating identically
with C = 200 pF, f = 2 MHz, VCCl = 5V, VCC2 = 20V, and
duty cycle = 60% outputs high (tH/T = 0.6). Also, assume
VOH = 19.3V, VOL = O.W, Ps is negligible, and that the
current from VCC2 is negligible when the output is high.

P-r(AV) = POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with the
output high or low, PC(AV) is the power level during charging
or discharging of the load capaCitance, and PS(AV) is the
power diSSipation during switching between the low and
high levels. None of these include energy transferred to the
load and all are averaged over a full cycle.

On a per-channel basis using data sheet values:
POC(AV) = [ (5V)

The power components per driver channel are:
POC(AV) =

PLtL

[(5V)

+ PHtH
T

PLHtLH

C

6;A)

+ (20V)

C~A)

] (0.6)

+

] (0.4)

POC(AV) = 47 mW per channel
PC(AV) ::: (200 pF) (19.2V)2 (2 MHz)

PC(AV) ::: C Vr!- f
PS(AV) =

(2~A) + (20V) (O~A)

PC(AV) ::: 148 mW per channel.

+ PHLtHL
T

For the total device dissipation of the two channels:

+

where the times are defined in Figure 4.

P-r(AV) ::: 2 (47

PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation and C is load capaCitance.

P-r(AV) ::: 390 mW typical for total package.

148)

f - - - - - T = 111------1
Tl/FI7557-8

FIGURE 4. Output Voltage Waveform

5-33

II

~

m ~National
~ Semiconductor
Q

DS75365 Quad TTL-to-MOS Driver
•
•
•
•

General Description
The OS75365 is a quad monolithic integrated TTL-to-MOS
driver and interface circuit that accepts standard TTL input
signals and provides high-current and high-voltage output
levels suitable for driving MOS circuits. It is used to drive
address, control, and timing inputs for several types of MOS
RAMs including the 1103.
The OS75365 operates from the TTL 5V supply and the
MOS Vss and Vee supplies in many applications. This device has been optimized for operation with VCC2 supply voltage from 16V to 20V, and with nominal VCC3 supply voltage
from 3V to 4V higher than VCC2. However, It is designed so
as to be usable over a much wider range of VCC2 and VCC3.
In some applications the VCC3 power supply can be eliminated by connecting the VCC3 to the VCC2 pin.

•
•
•
•
•
•
•
•

Capable of drivfng high-capacitance loads
Compatible with many popular MOS RAMs
'Interchangeable with Intel 3207
VCC2 supply voltage variable over side range to 24V
maximum
VCC3 supply voltage pin available
VCC3 pin can be connected to VCC2 pin in some
applications
TTL compatible diode-clamped Inputs
Operates from standard bipolar and MOS, supply
voltages
Two common enable inputs per gate-pair
High-speed switching
Transient overdrive minimizes power dissipation
Low standby power dissipation

Features
• Quad positive-logic NAND TTL-to-MOS driver
• Versatile interface circuit for use between TTL and
high-current, high-voltage systems

Schematic and Connection Diagrams
Dual-In-Une Package
Vo..

TO OTHER
DRIVERS

Y4

A4

{+-_____-+___..

INPUT A C>-----1........-f

ENABLE EI

Vee1

IE2

13

2El

A3

V3

V...

12

....~..........I---4.--O ~UTPUT

-+....I-.

C>---.....

Veel

-+--+.............

ENABLE E2 0-......

Y1

AI

TLlFI7560-2

TopYlew
P08Itlve'Loglc: Y =
TO OTHER {
DRIVERS

AiE"1i!2

Order Number DS75365N or DS75365WM
See NS Package Number M18B or N18A
L..41-.....- ....- - - - -....---~~_oGND
DNE OF 4 SHDWN

TLlFI7560-1

5-34

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Range of VCC1
Supply Voltage Range of VCC2
Supply Voltage Range of Vcca
nput Voltage
Inter-Input Voltage (Note 4)
Storage Temperature Range
Maximum Power Dissipation· at 25·C
Cavity Package
Molded Package
SO Package
Lead Temperature (Soldering, 10 sec)

Supply Voltage (VCC1)
Supply Voltage (VCC2)
Supply Voltage (Vcca)
Voltage Difference Between
Supply Voltages: Vcca-VCC2
Operating Ambient Temperature
Range (TAl

-0.5Vt07V
-0.5Vt025V
-0.5Vt030V
5.5V
5.5V
-65·C to + 150"C

Min
4.75
4.75
VCC2
0

Max
5.25
24
28
10

Units
V
V
V
V

0

70

·C

1509mW
1476mW
1488mW
300·C

• Derale cavity package 10.1 mW/'C above 25°C; derale molded package
II.B mW 1°C above 25°C. derate SO package 11.9 mW/'C above 25°C.

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

VI

Input Clamp Voltage

VOH

High-Level Output Voltage Vcca = VCC2 + 3V, VIL = 0.8V, IOH = - 100 IJ-A VCC2 - 0.3 VCC2 - 0.1

V

Vcca = VCC2 + 3V, VIL = 0.8V,IOH = - 10 mA

VCC2 - 1.2 VCC2 - 0.9

V

Vcca = VCC2, VIL = 0.8V, IOH = - 50 IJ-A

VCC2 - 1 VCC2 - 0.7

V

Vcca = VCC2, VIL = 0.8V,IOH = - 10 mA

VCC2 - 2.3 VCC2 - 1.8

V

VOL

11= -12mA

Low-Level Output Voltage VIH = 2V, IOL = 10 mA
Vcca

Vo

Output Clamp Voltage

II

Input Current at Maximum VI
Input Voltage

IIH

High-Level Input Current

IlL

Low-Level Input Current

VI

VI

V

0.3

V

0.5

V

VCC2 + 1.5

V

1

mA

A Inputs

40

IJ-A

El and E2 Inputs

80

IJ-A

= 5.5V

= 0.4V

V

-1.5

0.25

= OV, IOH = 20 mA

VI = 2.4V

0.8

0.15

= 15V to 28V, VIH = 2V, IOL = 40 mA

A Inputs

-1

-1.6

mA

El and E2 Inputs

-2

-3.2

mA

4

8

mA

-2.2

+0.25

mA

-2.2

-3.2

rnA

ICC1(H) Supply Current from VCC1, VCC1 = 5.25V, VCC2 = 24V
All Outputs High
Vcca = 28V, All Inputs at OV, No Load
ICC2(H)

V

2

Supply Current from VCC2,
All Outputs High

Icca(H)

Supply Current from Vcca,
All Outputs High

2.2

3.5

mA

ICC1(L)

Supply Current from VCC1, VCC1 = 5.25V, VCC2 = 24V
All Outputs Low
VCC3 = 28V, All Inputs at 5V, No Load

31

47

mA

ICC2(L)

Supply Current from VCC2,
All Outputs Low

3

mA

Icca(L)

Supply Current from Vcca,
All Outputs Low

25

mA

ICC2(H)

Supply Current from V CC2, VCC1 = 5.25V, VCC2 = 24V
All Outputs High
Vcca = 24V, All Inputs at OV, No Load

0.25

mA

Icca(H)

Supply Current from Vcca,
All Outputs High

0.5

mA

16

5-35

~~-.-------

------

II

Electrical Characteristics (Notes 2,3) (Continued)
Symbol

Parameter

ICC2(S)

Supply Current from VCC2,
Stand-By Condition

Min

Conditions
VCC1
VCC3

=
=

Typ

Max

Units

0.25

mA

OV, VCC2 = 24V
24V, All Inputs at 5V, No Load

Supply Current from VCC3,
O.S
mA
Stand-By Condition
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to Imply that the devices should be operated at these limits. The table of "ElectrlceJ Characteristics" provides conditions for actual device
oparatlon.
Note 2: Unless otherwise spec~ied, minImax IimHs apply across the O'C to + 70'C range for the OS75365. All typlcsl values are for TA = 25'C and VCC1 = 5Vand
VCC2 = 20V and Vcca = 24V.

ICC3(S)

Note 3: All currents Into device pins shown as posHlve, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown

as max or min on absolute value basis.

Not. 4: This rating applies between any two inputs of anyone of the gates.

Switching Characteristics VCC1
Symbol

=

SV, VCC2

=

20V, Vccs

Parameter

=

24V, TA

=

Conditions

tOLH

Delay Time, Low-to-High Level Output

tOHL

Delay Time, High-to-Low Level Output

tTLH

2SoC
Min

CL = 200pF
RD = 240.
(Figure 1)

Typ

Max

Units
ns

11

20

10

18

ns

Transition Time, Low-to-High Level Output

20

33

ns

trHL

Transition Time, High-to-Low Level Output

20

33

ns

tpLH

Propagation Delay Time, Low-to-High Level Output

10

31

48

ns

tpHL

Propagation Delay Time, High-to-Low Level Output

10

30

46

ns

-=:1

1--:<;;10 ••

AC Test Circuit and Switching Time Waveforms
INPUT

I

PULSE
GENERATOR
(NOTE I)

:<;;10 .. _

5V Z4V ZOV

rvl;v!;v!~
II

I

- ,.

f"

I

L

Z.4V

GNO

-~-

I
I

.J

3V

I

INPUT

' / 1.5V

90%

1.90%

..J.

Ro

OUTPUT

1.5V
O.s,..

OV -..l!!!!.I

CL
T(NoTEZ)

i--IpLH-

r--'PHL'.HL -VCC2- ZV \

TLlF17560-3

-

..... tTHL

VOH

1\ 10%

t.LH-

I--'TLH

~

~.

VCC2 -ZV

OUTPUT
VOL

ZV

ZV
TL/FI7560-4

Not. 1: The pulse generator has the following characteristics: PRR = 1 MHz, ZOUT = 581l.
Note 2: CL includes probe and jig capacHance.
FIGURE 1. Switching Times, Each Driver

5-36

Typical Performance Characteristics
High-Level Output Voltage vs
Output Current

l!

""'"

~ -D.•

High-Level Output Voltage vs
Output Current

l!
::: -0.5

~+70C

~-'.O
>

T.~

~ -1.0

. -'.&

~-1.&

~

;

~

~

Vccz- zav

~ -2.&

~

Vcca -24Y

v.-uv

-3.0

z

-0.'

~.
>

i.

T-~~&C

TA-+l·C~

:::
Vee, -IV

l!

I=:HHt-+ttlf-l-t+lt-tftl
~ iIIIIr.

!;

I;

yj -2.0

o.s

°r-T'"T'I......,...,,.,,...-r-mr---.'T'T'I

Illlll

1111'· T~
"I iill-'

-3.0

Vcc,-IV
Vcc2"Vcca- 20V I

-2.&
-3.0

-,

v.-a.8V

..1

I

I

1111
1111

a4

Vcc,-IV
V... - 20V
Vcc:.- 24V

V,-2V
0.3

0.2

I.'
co

20

-0.0'
-L'
-,
-,0
-.01
HIGH·LEVEL OUTPUT CURRENT ImAt

-0.0'
-'0
-'00
H'GH·LEVEL OUTI'UT CURRENT (..Al

Low-Level Output Voltage
Output Current

80

80

'00

LOYHEVEL OUTI'UT CURRENT (mAt

TLlFI7560-5

Total Dissipation (All Four
Drlvera) vs Fraquency

Voltage Trans'er
Characteristics

24,--,--,---r--r----,

I

4G

'-;--.,,;nnr~rT;rnrn
810 ~-t-+'~~-::-I-H'I-I+H-I!I

",1

800 r-~tf~~~~~~

II!

6111

....
=:
i!
>"

~:c:;~V-t_-ilI--t-_-l

30
200

'.5

2.5

D..

Propagation Delay Time,
High-to-Low Level Output
vs Ambient Temperature
40

~~

2&

~

20

~

4

IA 0.1 •
FAEaUENCV (MH.)

0.2

!~
>=

'0

;;;

c·-I·oo'l_

'5

vcc• =!iV

'0

Vea .. Vccz + 4V
RD -Z5U

.,.

50 aD

iE
~!;

....
......
.......

&0
CD

~~

">
~

5ia

i;
~5!

30
20

AD" Z4H
IFIGUAE 11

10 80

12
18
21
SUPPlY VOLTAGE (VI

Vcos,24V
TA'"Z5°C
(FIGURE I)
_

~

~
:::ii::~~1-1i'.-0

A.!.III.

....

J.l
i.--"

35

....>"~~

3D

I"
;:~

..
.....

2&

~~

II

~

.,'"
L"
5!

3D

co

58

&0

11 80

-

C"2DO~""

/ ' .....

2•

..... i-""'"

.&

'"1:-:;-:';:
I

I

VQC1-SV
VCC3· Vccz +4V

RD -24n
TA'25"C
(FiGUAE I)
.2
••
28
SUPPLY VOLTAGE (VI

24

BI

-R.'~

ZI

211

Propagation Delay Time,
Hlgh-to-Low Level Output vs
Load Capacitance

Vee, "'IV
Vcc:z = 2DV

.1

;:.
:9

Propagation Delay Time,
Low-to-High Level Output vs
Load Capacitance
DO

Vccs= !"V

Propagation Delay Time,
Hlgh-to-Low Level Output
vs VCC2 Supply Voltage

TA -25"C
IFIGUAEI)

AMBIENT TEMPERATURE reI

.1

vCC2 '" 28'1

.0

-

~c,!J~

~

f~

IFIGURE 11

-

2D

r::",

Vcc." 5V
Vccz III ZOV
VCC3 " 24V
RD "!4H

3D

=5\1

VCCt

.0

40

35

2&

~~

.&

30 4G

c.I-50~F

- -

AMBIENT TEMPERATURE I C)

c ..

....f~......
.

Ic. '~OP~

2D

21
IS

., l'

CD

.l

CL "2lOpf

.0

2&

Propagation Delay Time,
Low-to-Hlgh Level Output vs
VCC2 Supply Voltage

35
3D

C. - 200,F

O~~~~~~~~UW

INPUT VOLTAGE (VI

~!;

=~
L~

'11

0.'

..
~i
..f6lEa.,.

~

400

..

NO LOAD

.!
!~

..~~.....

~-t-+'Io'fI:IoKI~+'oF++H-I!I

~~ r.1~~mm:::tUmW

::;; ::V-t--il--t---l
,

DOD

I I

3&

-I;
;:I!: 31

i!l lOB

;:

Propagation Delay Time,
Low-to-Hlgh Level Output
vs Ambient Temperature

....!~~~

~

::::

>=

CD

.......

3D

~

~~

2.

f:5!

.0

!i~

.D
&0 .00 .58 200 2SO 3ID 3&0 4DO

&D

Vee, -IV
YCC2· JOY
Vcc3"'24Y

TA _21°C
(FIGUAEI)
I
RD-l0U

r-

-

~~ ~

~ ~ P""

;.,..

AD-a

&1 'II 'ID 2110 2SO 30D 310 ....
LOAD CAPACITANCE (,FI

LOAD CAPACITANCE I,F)

TL/FI7560-6

5-37

U)

~

r---------------------------------------------------------------------------------,
5V

11.5V

lBV

5V

U)

~

TL/F17560-7

FIGURE 2. Interconnection of DS75365 Devices
with 1103-Type Slllcon-Gate MOS RAM
The power components per driver channel are:

Typical Applications

POC(AV) =

The fast switching speeds of this device may produce undesirable output transient overshoot because of load or wiring
inductance. A small series damping resistor may be used to
reduce or eliminate this output transient overshoot. The optimum value of the damping resistor depends on the specific
load characteristics and switching speed. A typical value
would be between 100 and 300 (Figure 3).

r

DS763a6 -,

r

MOs

PLtL + PHtH
T

PC(AV) "" cvc2f
PLHtLH + PHLtHL
PS(AV) =
T
where the times are as defined in Figure 4.
PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation and C is load capacitance.

"l

~:... lJSZ:1
=t==L-"I"""Tlc~ ..L I
L __ --1 L_"=".J

The OS75365 is so designed that Ps is a negligible portion
of PT in most applications. Except at very high frequencies,
tL + tH
tLH + tHL so that Ps can be neglected. The total
dissipation curve for no load demonstrates this point. The
power dissipation contributions from all four channels are
then added together to obtain total device power.

»

Note: RD '" Ion to 30n (Optional)
TLlFI7560-8

Thermal Information

The following example illustrates this power calculation
technique. Assume all four channels are operating identically with C = 100 pF, f = 2 MHz, VCC1 = 5V, VCC2 = 20V,
VCC3 = 24V and duty cycle = 60% outputs high
(tH/T = 0.6). Also, assume VOH = 20V, VOL = 0.1 V, Ps is
negligible, and that the current from VCC2 is negligible when
the output is low.

POWER DISSIPATION PRECAUTIONS

On a per-channel basis using data sheet values:

FIGURE 3. Use of Damping Resistor to Reduce or
Eliminate Output Transient Overshoot In Certain
DS75365 Applications

Significant power may be dissipated in the OS75365 driver
when charging and discharging high-capacitance loads over
a wide voltage range at high frequencies. The total dissipation curve shows the power dissipated in a typical OS75365
as a function of load capacitance and frequency. Average
power dissipation by this driver can be broken into three
components:

POC(AV) = [(5V) ( 4 ;A) + (20V) (-2.: mA) + (24V)

PT(AV) = POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with the
output high or low, PC(AV) is the power level during charging
or discharging of the load capacitance, and PS(AV) is the
power dissipation during switching between the low and
high levels. None of these include energy transferred to the
load and all are averaged over a full cycle.

POC(AV) = 58 mW per channel

(2.24mA) ] (0.6) + [ (5V)
(20V) (0 ;A) + (24V)

e

14mA) +

C

64mA ) ] (0.4)

PC(AV) "" (100 pF)(19.9V)2 (2 MHz)
PC(AV) '" 79 mW per channel.
For the total device dissipation of the four channels:
PT(AV) '" 4(58 +79)
PT(AV) .. 548 mW typical for total package.

!------T-l/1-----!
TL/FI7560-9

FIGURE 4. Output Voltage Waveform
5-38

Section 6
Frequency Synthesis

Section 6 Contents
Frequency Synthesis-Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Synthesizers-Selection Guide. .. .. . . . . . . . . . . .. . . .. .. . . . . . .. .. . . . . . . . . . . . . .
DS8615/DS8616 130/225 MHz Low Power Dual Modulus Prescalers . . . . . . . . . . . . . . . . . . . . .
DS8673/DS8674 Low Power VHF/UHF Prescalers . . . . . . . . . .. . .. . . . . . .. . . .. .. . .. . . . . . . .
DS89088 AM/FM Digital Phase-Locked Loop Frequency Synthesizer. . . . . . .. . . . . . . . . . . . . .
DS8911/DS8913 AM/FM/TV Sound Up-Conversion Frequency Synthesizers. . . . . . . . . . . . . .
MM5368 CMOS Oscillator Divider Circuit ..............................................
MM5369 Series 17 Stage Oscillator/Divider..................................... .......
MM5437 Digital Noise Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2

6-3
6-5
6-6
6-10
6-13
6-21
6-30
6-33
6-36

~National

~ Semiconductor

Frequency Synthesis
Frequency synthesis is the process of generating a multitude of different frequencies from one reference frequency.
A common application where the frequency synthesis concept is used is in electronically tuned radios and televisions.

state-of-the-art microCMOS devices are usually limited to
100 MHz operation. Even the FM band exceeds this limitation. As a result, a prescaler is almost always used in PLL
tuning applications such as FM radios, police scanning radios, aircraft radios, etc. The prescaler is specifically designed
to divide high frequency AC input signals down to a usable
frequency for the PLL. The prescaler becomes an extension
of the PLL's programmable counter as illustrated in Figure

Digital tuning systems are fast replacing the conventional
mechanical systems in AM, FM and television receivers.
The digital approach encompasses the following operational features:
• Precise tuning of station frequencies
• Exact digital frequency display
• Keyboard entry of desired frequency
• Virtually unlimited station memory
• Up/down scanning through the band
• Station "search" (stop on next active station)
• Power-on to the last station
• Easy option for time-of-day clock
In addition, recent developments in large-scale integrated
circuit technology and new varactor diodes for the AM band
have made the cost-benefit picture for digital tuning very
attractive.

2.
For less sophisticated tuning applications, a fixed division
prescaler will make the VCO signal palatable to the PLL and
be sufficient for general tuning characteristics. However, in
some applications, a fixed division prescaler can cause significant undesirable side effects such as:
1. Increased channel spacing (step size) at the output of
the PLL's counter; ·or
2. A forced decrease of the fixed oscillator reference frequency in order to obtain specific channel spacing
which can lead to
A. increased lock-on time,
B. decreased scanning rates, and
C. sidebands at undesirable frequencies.
AN-335 in this section explains in detail how these two
shortcomings of fixed division prescaling are alleviated by
using a dual modulus prescaler. A dual modulus prescaler is
substituted for the fixed prescaler and is controlled by programmable counters in the dual modulus PLL, as illustrated
by the dotted line in Figure 2.
In order to address the requirements of digital frequency
synthesis applications, National has introduced a growing
family of PLL synthesizers and prescalers. The 058906,
058907 and 058908 are complete PLL synthesizers with
features that go beyond those illustrated in Figure 2.

The heart of any digital tuning system is, of course, the
phase locked loop (PLL) synthesizer. The basic subcomponents of a digital system are: a voltage controlled oscillator
(VCO), a phase comparator and some programmable and
fixed dividers. The PLL's basic function is to take two input
signals and match them as illustrated in Figure 1. The output
of the phase comparator of the PLL is an error signal which
is filtered and fed back to the VCO as a DC control voltage.
The DC control voltage adjusts the VCO until it causes the
phase comparator's two inputs to match one another.
The weak point of this simple illustration is that many PLLs
are fabricated using MaS processes which make them relatively incapable of receiving high frequency signals. In fact,

PLL

PROGRAMMABLE

COUNTER

TL/XX/0108-1

FIGURE 1
6-3

~---------

-------

- - - - - - - - --------

Highlights
• The 058908 integrates a reference oscillator. phase comparator. charge pump. operational amplifier. 120 MHz
ECLlI2L dual modulus programmable divider. and a shift
register/latch for serial data entry.
• The 058614. 058615. 0S8616. 058617. 058627. and
058628 represent a broad family of single and dual modulus prescalers for use in conjunction with other manufac-

turers' NM05 or CM05 PLLs. These low-power/hlghspeed prescalers are available with division ratios ranging
from a fixed + 20 up to a dual modulus + 64/65. This
array of products allows for the choice of a division ratio
which is virtually tailored to the speed and tuning requirements of a particular frequency synthesis application.

PROGRA....ABLE
COUNTER

TLlXX/0108-2

FIGURE 2

6-4

~National

Semiconductor

Frequency Synthesizers Selection Guide
PLL FREQUENCY SYNTHESIZERS
Product Type

Frequency Bands

Power (mA)

Tuning Resolution

AM/FM
AM/FMIVHF TV

160
35

1 kHz,9 kHz,10 kHz, 20 kHz
FM; 10, 12.5, 25,100 kHz
AM; 1, 1.25,2.5, 10kHz

DS8908
DS8911/13

HIGH FREQUENCY PRESCALERS
Product Type

I

I

Divide Modulus

Power (mA)

I

fMAX

Single (Fixed) Modulus Dividers
DS8673
DS8674

+64
+256

I

I

25
25

I

1 GHz
1 GHz

Dual-Modulus Dividers
DS8615
DS8616

1

+32/33
+40/41

I

7/10
7/10

J

130/225 MHz
130/225 MHz

OSCILLATOR DIVIDER CIRCUITS
Product Type
MM5368
MM5369AA

Crystal Frequency

Output Frequency

Power (mA)

32,768 Hz
3,579545 MHz

50/60 Hz, 10 Hz, 1 kHz
60 Hz, Crystal Frequency

1.5
1.2

6-5

.,..
~

I~
.,..
I

,------------------------------------------------------------------------,

~National

~ Semiconductor

OS8615/0S8616 130/225 MHz

Low Power Dual Modulus Prescalers
General Description
The D88615 series products are low power dual modulus
prescalers which divide by 32/33 and 40/41 respectively.
The modulus control (MC) input selects division by N when
at a high TTL level and division by N + 1 when at a low TTL
level. The clock inputs are buffered, providing 40/100
mVrms input sensitivity. The two outputs provide the user
the option to wire either a totem-pole or open-collector output structure. Additionally, the user can wire a resistor between the two output pins to minimize edge transition emissions. The outputs are designed to drive positive edge triggered PLLs. These products can be operated from either an
unregulated 5.5V to 13.5V source or regulated 5V ± 10%
source. Unregulated operation is obtained by connecting Vs
to the source with VREG open. Regulated operation is obtained by connecting both Vs and VREG to the supply
source.

The device can be used in phase-locked loop applications
such as FM radio or other communications bands to prescale the input frequency down to a more usable level. A
digital frequency display system can also be derived separately or in conjunction with a phase-locked loop, and it can
extend the useful range of many inexpensive frequency
counters to 225 MHz.

Features
•
•
•
•
•

Input frequency: 130 MHz (-4); 225 MHz (-2)
Low power: 10 mA (-4, -2)
Input sensitivity: 100 mVrms (-4); 40 mVrms (-2)
Pin compatlblS with Motorola MC12015-16 presealers
Unregulated/regulated power supply option

Logic and Connection Diagrams
Generalized + NIN

+1

=~~1
H=+No-------~~-------,
L=+N+1

8YN CUI

2

QH---t
D
CUI

3

CUI

CUI

UPPER OUTPUT
LOWER OUTPUT

CUI

TLlF/5240-1

Dual-In-Line Package
MC

UPPt:R OUTPUT

TL/F/5240-2

Top View

Order Number DS8615N or DS8816N (-4, -2)
See NS Package Number N08E
6-6

Absolute Maximum Ratings (Note 1)
If M"ltary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for ava"ab"lty and specifications.
Vs, Unregulated Supply Voltage
15V
VREG, Regulated Supply Voltage
7V

Modulus Control Input Voltage
Open-Collector Output Voltage
Operating Free Air Temperature Range
Storage Temperature Range

7V
7V
-30"C to + 70'C
- 65'C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

OS8615-4
OS8616-4

Conditions

Units

Min

Max

Min

Max

13.5

5.5

13.5

4.5

Unregulated Supply Voltage

VREG = Open

6.8

VREG

Regulated Supply Voltage

Vs and VREG Shorted

4.5

5.5

fMAX

Toggle Frequency

VIN = 100 mVrms

20

130
300

Vs

OS8615-2
OS8616-2

40

V

5.5

V

225

MHz

300

mVrms

VIN

Input Signal Amplitude

100

VSLW

Slew Rate

20

IOH

High Level Output Current

-400

-400

fJ.A

IOL

Low Level Output Current

2.0

2.0

mA

20

V/fJ.s

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

OS8615-4
OS8616-4

Conditions

Min
VIH

High Level MC Input
Voltage

Vs = 13.5V, VREG = Open

VIL

Low Level MC Input
Voltage

VREG = Vs = 4.5V

VOH

High Level Output
Voltage

IOH = -0.4 mA,
Pins 2 and 3 Shorted

ICEX

Open-Collector High
Level Output

Lower Output = 5.5V

VOL

Low Level Output
Voltage

VREG = 4.5V, IOL = 2 mA

II

Max MC Input Current

Vs = 13.5V, VREG = Open,
VIH = 7V

IIH

High Level MC Input
Current

VREG = 4.5V, VIH = 2.7V

IlL

Low Level MC Input
Current

Vs = 13.5V, VREG = Open,
VIL = 0.4V

Is

Supply Current,
Unregulated Mode

Vs = 13.5V, VREG = Open

IREG

Supply Current,
Regulated Mode

Vs = VREG = 5.5V

0S8615-2
OS8616-2

Max

2.0

Min

Units

Max
V

2.0
0.8

0.8

V

VREG -2

VREG -2

V

100

100

fJ.A

0.5

0.5

V

100

100

fJ.A

20

20

fJ.A

-200

-200

fJ.A

10

10

mA

10

10

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety 01 the device cannot be guaranteed. They are not meant to Imply that the device
should be operated at these limits. The teble 01 "Electrical Characteristics" provides condRlons for actual device operation.
Note 2: Unless otherwise specHled MinIMax limns apply across the -30"C to + 70"C range.
Note 3: All current Into device pins shown ss positive, out of device pins as negative, all voneges referanced to ground unless otherwise noted. All values shown as
Max or Min on absolute value bssis.

6-7

....CD

m
.....

....
~
!

AC Electrical Characteristics Vee =
Symbol

5V ±10%, TA = -30?Cto +70'C

Parameter

10

Conditions

Min

tMQOULUS

Modulus Set-Up Time
(Notes 4 and 5)

088615,088616

RIN

AC Input Resistance

VIN = 100 MHz and 50 mVrms

1.0

CIN

Input Capacitance

VIN = 100 MHz and 50 mVrms

3

. Max

Units

65

ns

kO
pF

10

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of tho device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant io imply that the devices should be operated at these IimHs. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise Specified minImax limits apply across tho - 30'C to

+ 70'C temperature range.

Note 3: All currents Into device pins are shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All vslues
shown as max or min on absolute value basis.

Note 4: tMOQULUS
selection.

= the period of time the modulus control level must be defined prior to the positive transition of the prescaler outPut to ensure proper modulus

Note 5: See Timing Diagrams.

Timing Diagram
OUTPUT

_HM

MIIIIUWSCOIIIROI.
INPUT_HM

TLlF/5240-3

The logical state of the mcdulus control input iust prior to tho output's rising edge will determine the mcdulus ratio of the device
Immediately following that rising edge. The pulse width difference of N and N + 1 operation occurs during the output = HI condHlons.

Typical Applications
5V
0.1,..

-P
REBULATm

3k

MC

lour
TLlF/5240-5

Tl/F/5240-4

Schematic Diagrams
Vuo

2

UPI'EIIOUTPUT

TLlF/5240-7
TL/F/5240-B
TLlF/5240-6

6-8

Application Hints
the single ended mode, a capacitor of 0.001 p.F (C2) should
be connected between the unused input and the ground
plane to provide a good high frequency bypass. The capacitor should be made larger for lower frequencies.

OPERATING NOTES
The signal source is usually capacitively coupled to the input. At higher frequencies a 0.001 p.F input capacitor (C1) is
usually sufficient, with larger values used at the lower frequencies. If the input Signal is likely to be interrupted, it may
be desirable to connect a 100 kO resistor between one input and ground to stabilize the device. In the single-ended
mode, it is preferable to connect the resistor to the unused
input. In the differential mode, the resistor can be connected
to either input. The addition of the 100 kO pulldown resistor
causes a loss of input sensitivity, but prevents circuit oscillations under no signal (open circuit) conditions. In addition, in

The input waveform may be sinusoidal, but below about

20 MHz the operation of the circuit becomes dependent on
the slew rate of the input rather than amplitude. A square
wave input with a slew rate of greater than 20 V I p.s will
permit correct operation down to lower frequencies, provided the proper input coupling capaCitor is provided.
For regulated mode operation connect Vs to VREG to ensure proper operation (see Typical Application diagram).

6-9

~National

~ Semiconductor

OS8673/0S8674 Low Power VHF/UHF Prescalers
General Description
The 088673 and 088674 products are low power prespalers which divide by 64 and 256 respectively. The devices
are used in frequency synthesis applications such as TVI
CATV, cellular phone,and instrumentation to divide a very
high frequency down to a frequency usable by low power
MOS Pll's.
The devices have differential buffered inputs and complementary ECl outputs. The inputs provide high input sensitivity and good isolation. The DS8673 is pin compatible with
Plessey's SP4531, SP4632, and Motorola's MC12073 prod-

ucts. The OS8674 is pin compatible with Plessey's SP4653
and Motorola's MC12074 products.

Features
•
•
•
•
•

1.0 GHz operating frequency
25 mA typical supply current
20 mV rms input sensitivity
0.8V complementary ECl outputs
low output radiation

Block and Connection Diagrams
Dual-In-line Package

N2c O7a OUT2
vee
3
6 oun

INI
IN2

GND4

SNC
TL/F/9340-1

Top View
Order Number D88673N or DS8674N
See NS Package Number N08E

vcc{a)

,..-t+-OUT2

.'=-:=--i- 0UTI
NC
TL/F/9340-2

6-10

Absolute Maximum Ratings

(Note 1)
If Military/Aerospace specified devices are required,
pleaae contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

OUtput Voltage
Operating Free Air Temperature Range
Storage Temperature Range
ESD rating is to be determined.

Vee + 0.5V
-40"C to + S5°C
-65°C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Conditions

Min

Typ

Max

Units

Vee

Power Supply Voltage Range

4.5

5.5

V

FIN

Input Frequency Range

VINMin

SO

1,000

MHz

VIN

Input Sensitivity into 500

SO MHz
300 MHz
500 MHz
700 MHz
1 GHz

20
20
20
20
20

200
200
200
200
200

mVrms

Min

DC Electrical Characteristics
Symbol

Parameter

Conditions

lee

Power Supply Current

Vee = 5.5V

VOUT

Output Voltage Swing

Peak-to-Peak
(no load)

O.S

Typ

Max

Units

25

35

mA

1.2

1.6

V

Note 1: "Absolute Maximum Ratings" are those values beyond which Ihe safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply thet the devices should be operated at lhasa limits. The table of "Electrical Cheracteristics" provides conditions for actual device
operation.

Typical Applications
Typical Wiring Configuration

i

-1

lrl:::l~:

SIGNAL
SOURCE

-

I"

5~_ _ _ _...

--

-==-

6·11

TLlF/9340-3

Typical Applications (Continued)
Typical Input Impedance

Reference value = 50n
VI (rms) = 25 mV
Vee = 5V
Waveshape is TBD

-1

TLlF/9340-4

Typical Sensitivity Curve Under Nominal Conditions
1000

1----

100

I
f:::j

10

Recommended
operating area

~~

f::::=

1

o

500

fin (104Hz)

6·12

1000
TLlF/9340-5

.------------------------------------------------------------------,0
~

~National

CD

o

~ Semiconductor

CD

m

DS89088 AM/FM Digital Phase-Locked
Loop Frequency Synthesizer
General Description
The DS89088 is a Pll synthesizer designed specifically for
use in AM/FM radios. It contains the reference oscillator, a
phase comparator, a charge pump, an operational amplifier,
a 120 MHz ECl/12l dual modulus programmable divider,
and a 19-bit shift registerI latch for serial data entry. The
device is designed to operate with a serial data controller
generating the necesary division codes for each frequency,
and logic state information for radio function inputs/outputs.
A 3.96 MHz pierce oscillator and divider chain generate a
1.98 MHz external controller clock, a 20 kHz, 10kHz, 9 kHz,
and a 1 kHz reference signals, and a 50 Hz time-of-day
signal. The oscillator and divider chain are sourced by the
VCCM pin thus providing a low power controller clock drive
and time-of-day indication when the balance of the Pll is
powered down.
The 21-bit serial data steram is transferred between the frequency synthesizer and the controller via a 3-wire bus system comprised of a data line, a clock line, and an enable
line.
The first 2 bits in the serial data stream address the synthesizer thus permitting other devices such as display drivers to
share the same bus. The next 14 bits are used for the
Pll(N + 1) divide code. The 15th bit is used internally to
select the AM or FM local oscillator input. A high level on
this bit enables the FM input and a low level enables the AM
input. The 16th and 17th bits are used to select one of the 4
reference frequencies. The 18th and 19th bits are connected via latches to open collector outputs. These outputs can
be used to drive radio functions such as gain, mute, AM,
FM, or charge pump current source levels.
The Pll consists of a 14-bit programmable 12l divider, an
ECl phase comparator, an ECl dual modulus (pip + 1) prescaler, a high speed charge pump, and an operational amplifier. The programmable divider divides by (N + 1), N being
the number loaded into the shift register. The programmable
divider is clocked through a + % prescaler by the AM input
or through a + 60/64 prescaler by the FM input. The AM input
will work at frequencies up to 15 MHz, while the FM input
works up to 120 MHz. The VCO can be tuned with a frequency resolution of either 1 kHz, 9 kHz, 10kHz, or 20 kHz.
The buffered AM and FM inputs are self-biased and can be
driven directly by the VCO through a capacitor. The ECl
phase comparator produces very accurate resolution of the
phase difference between the input signal and the reference
oscillator. The high speed charge pump consists of a
switchable constant current source and sink. The charge
pump can be programmed to deliver from 75 /LA to 750 /LA
of constant current by connection of an external resistor
from pin RpROGRAM to ground or the open collector bit outputs. Connection of programming resistors to the bit outputs
enables the controller to adjust the loop gain for the particular reference frequency selected. The charge pump will
source current if the VCO frequency is high and sink

current if the VCO frequency is low. The low noise operational amplifier provided has a high impedance JFET input
and a large output voltage range. The op amp's negative
input is common with the charge pump output and its positive input is internally biased.

Features
• Uses inexpensive 3.96 MHz reference crystal
• FIN capability greater than 120 MHz allows direct synthesis at FM frequencies
• FM resolution of either 10kHz or 20 kHz allows usage
of 10.7 MHz ceramic filter distribution
• Serial data entry for simplified control
• 50 Hz output for time-of-day reference driven from separate low power VCCM
• 2 open collector buffered outputs for controlling various
radio functions or loop gain
• Separate AM and FM inputs; AM input has 15 mV (typical) hysteresis
• Programmable charge pump current sources enable adjustment cif system loop gain
• Operational amplifier provides high impedance load to
charge pump output and a wide voltage range for the
VCO input

Connection Diagram

6-13

Dual-In-Line Package
BIT lB OUT
BIT190UT

1.

OPAMP
GROUND

n

CHARGE PUMP
OUT

DATA
CLOCK
DS8908B
VCCI
14 UBMHz

CAP
BYPASS

FMIN

13 OSC B
12 OSC C

GND lDL-_ _ _ _ _ _ _... l1 VCCM

Top VIew
Order Number DS8908BN
See NS Package Number N20A

TL/F/5111-1

I

Absolute Maximum Ratings (Note 1)
Storage Temperature Range
- 65'C to + 150'C
. 260'C
Lead Temperature (Soldering, 4 seconds)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
(VCC1) (VCCM)
17V
(VCC2)
Input Voltage
7V
Output Voltage
7V

Operating Conditions
VCC1
VCC2
VCCM
Temperature, TA

Min
4.5
VCC1 + 1.5
3.5
-40

Max
5.5
15.0
5.5
+85

Units
V
V
V
'C

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Min

Conditions

VIH

Logical "1" Input Voltage

IIH

Logical "1" Input Current

VIL

Logical "0" Input Voltage

IlL

Logical "0" Input Current

Data, Clock, and EIiIAB'IJ: Inputs, VIN = OV

IOH

Logical "1" Output Current
All Bit Outputs, 50 Hz Output

VOH = 5.5V

1.98 MHz Output

VOH = 2.4V, VCCM = 4.5V

Logical "0" Output Voltage
All Bit Outputs

IOL=5mA

VOL

Typ

Max

Units

0

10

p.A

0.8

V

-5

-25

p.A

50

p.A

-250

p.A

0.5

V

0.5

V

0.3
0.4

V
V

2.0

V

VIN = 2.7V

50 Hz Output, 1.98 MHz Output IOL = 250 p.A
1.98 MHz Output

IOL = 20 p.A, TA > 70'C
IOL = 20 p.A, TA';; 70'C

ICC1

Supply Current (VCC1)

All Bit Outputs High

ICCM

VCCM Supply Current

VCCM = 5.5V, All Other Pins Open

lOUT

Charge Pump Ougtput Current

3.33k ,;; RpROG ,;; 33.3k
lOUT Measured between
Pin 17 and Pin 18
IpROG = VCC1 /2 RpROG

IpROG

+20

%

Pump Down

-20

IpROG

+20

%

0

11

nA

6.7

11

TRI·STATE@

VCCM = 5V, VCC1 = 5.5V, VCC2 = 15V
All Other Pins Open

OPvOH

Op Amp Minimum High Level

VCC1 = 4.5V, IOH = -750 p.A

CPOBIAS Charge Pump Bias Voltage
Delta

mA
V

VCC2 -0.4

VCC1 = 5.5V, IOL = 750 p.A

0.6

V

CPO Shorted to Op Amp Output
CPO = TRI·STATE
Op Amp IOL: 750 p.A vs - 750 p.A

100

mV

AC Electrical Characteristics Vcc =
Symbol

mA

-20

VCC2 Supply Current

Op Amp Maximum Low Level

mA

4.0

Pump Up

ICC2

OPvOL

160
2.5

Parameter

5V, TA = 25'C, tr';; 10 ns, Ij';; 10 ns
Min

Conditions
AM and FM Inputs, -40'C ,;; TA ,;; 85'C

Typ

Max

Units

20

100

mV(rms)

VIN(MIN)(F)

FIN Minimum Signal Input

VIN(MAX)(F)

FIN Maximum Signal Input

AM and FM Inputs, - 40'C ,;; TA ,;; 85'C

FOPERATE

Operating Frequency Range
(Sine Wave Input)

VIN = 100 mV rms
-40'C';; TA ,;; 85'C

RIN(FM)

AC Input Resistance, FM

120 MHz, VIN = 100 mV rms

600

{}

RIN(AM)

AC Input Resistance, AM

15 MHz, VIN = 100 mVrms

1000

{}

CIN

Input Capacitance, FM and AM

VIN = 120 MHz (FM), 15 MHz (AM)

tEN1

Minimum ENABLE High
Pulse Width
8·14

I AM
I FM

1000

mV(rms)

1500

0.5

15

MHz

80

120

MHz

3

6

10

pF

625

1250

ns

AC Electrical Characteristics Vcc =
Symbol

Parameter

5V, TA = 25°C, tr

s:

10 ns, tf

s:

10 ns (Continued)

Typ

Max

Units

~o

Minimum EJiJAB[E Low
Pulse Width

375

750

ns

tcLKENO

Minimum Time before ENABLE
Goes Low That CLOCK Must
BeLow

-50

0

ns

Minimum Time after ENABLE
Goes Low That CLOCK Must
Remain Low

275

550

ns

Minimum Time before ENABLE
Goes High That Last Positive
CLOCK Edge May Occur

300

600

ns

Minimum Time after ENABLE
Goes High before an Unused
Positive CLOCK Edge May Occur

175

350

ns

tCLKH

Minimum CLOCK High
Pulse Width

275

550

ns

tCLKL

Minimum CLOCK Low
Pulse Width

400

800

ns

tos

Minimum DATA Set-Up Time,
Minimum Time before CLOCK
That DATA Must Be Valid

150

300

ns

Minimum DATA Hold Time,
Minimum Time after CLOCK
That DATA Must Remain Valid

400

800

ns

~OCLK

tCLKEN1

~1CLK

tOH

Min

Conditions

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides condHions for actual device
operation.

Note 2: Unless otherwise specified minimax limits apply across the - 40'C to + 85'C temperature range for the 0589088.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values shown as
max or min on absolute value basis.

Schematic Diagrams (DS8908B AM/FM PLL TypicallnputlOutput Schematics)
veel

veel

veel

veel
I

~

15k
15k

~""~

_lr'

"~'~ ~

"ENAiIrr

~~

-

~

...

".~

.~

~,

RpROGRAM

.~

'~-):,m~

"
15k

p--~--

~

27k

•

~

21k

TL/F/SIII-4

'::'

~
'::'
TLlF/SI11-2

TLlF/SlIl-3

6-15

Uk

I
m

Schematic Diagrams (Continued)
2·DIODE
RAIL

OSC C ....-

VCCM

-""""4.--

....

20k

OSC8 ....-

...-

1.98 MHz

...

TL/F/5111-6

TLlF/5111-7
TL/F/5111-5

10k

L------4-------------------4~~:A~

Uk

TLlF/5111-8

6-16

Schematic Diagrams (Continued)
VCC2

OPAMP
OUTPUT

20k

TL/F/5111-9

Timing Diagrams·
EfiIAEE vs CLOCK

3V--+.-_
Emil
OV

3V------------+,--~

CLOCK
DV-----..I
TL/F/5111-10

CLOCKvsDATA
3V~~~~~~

DATA
DVoiloloill~~~.»;I

' -_ _ _--J

3V------------------~--------CLOCK
.IV
TLlF/5111-11

6·17

•

m .---------------------~----------------------------------------------~

I

Timing Diagrams·

(Continued)
AM/FM Frequency Synthe81zer (Scan Mode)

r

mml

~-----------------------~f~f----------------~
DATAIN~
\t.-H
ij
Ii-

U

CLDCK _ _- ,
CLOCK PULSE

t

t

------

PLLADDRESS

DATA BITS
BITS 1-14, +N CODE (LSB FIRST)
BIT 15, AM/FM SELECT BIT
BITS 18-17, REFERENCE FREOUENCY SELECT BITS
BITS II-II, OUTPUT BITS

1,1

t
NEGATIVE TRANSITION ON

t

POSITIVE TRANSITION ON
mm
LATCHES IN NEW
CODE IF PLL IS ADDRESSED.

ENABLE CLEARS PREVIOUS
ADDRESS. CLOCK MUST BE
LOW DURING TRANSITION.

TL/F/5111-12

'Timing diagrams are not drawn 10 scale. Scale within any one drawing may not be consistent, and Intervals are defined positive as drawn.

SERIAL DATA ENTRY INTO THE DS8908B
Serial information entry into the OS8908B is enabled by a
low level on the EfilAm:E input. One binary bit is then accepted from the DATA input with each positive transition of
the CLOCK input. The CLOCK input must be low for the
specified time preceding and follOWing the negative transition of the Ef\/AEiu: input.
The first two bits accepted following the negative transition
of the 'EfiIAim: input are interpreted as address. If these
address bits are not 1,1 no further information will be accepted fromt he DATA inputs, and the intemal data latches
will not be changed when ~ retums high.
If these first two bits are 1,1, then all succeeding bits are
accepted as data, and are shifted successively into the intemal shift register as long as ~ remains low.
Any data bits preceding the 19th to last bit will be shifted
out, and thus are irrelevant. Data bits are counted as any
bits following two valid address bits (1,1) with the J:liIAB[E
low. When the ENABLE input retums high, any further serial
data entry is inhibited. Upon this positive transition, the data
in the intemal shift register is transferred into the intemal
data latches. Note that until this time, the states of the internal data latches have remained unchanged.

These data bits are interpreted as follows:
Data Bit POSition
Data Interpretation
Last
Bit 19 Output (Pin 2)
2nd to Last
Bit 18 Output (Pin 1)
3rd to Last
Ref. Freq. Select Bi1(1)17
4th to Last
Ref. Freq. Select Bi1(1)16
5th to Last
AM/FM Select Bit 15
6th to Last
(213)
(212)
7th to Last
8th to Last
(2 11 )
9th to Last
(2 10)
1Oth to Last
(29)
11 th to Last
(28)
12th to Last
(27)
+N(2)
13th to Last
(26)
(25)
14th to Last
15th to Last
(24)
16th to Last
(23)
(22)
17th to Last
18th to Last
(21)
19th to Last
LSB of + N(20)
Note 1: See Reference Frequency Select Truth Table.
Note 2: The ac1ual divide code is N + I, Ie., the number loaded plus 1.

Truth Table
Reference Frequency Selection Truth Table
Reference
Frequency

Serial Data
Bit 16

Bit 17

(kHz)

1
1
0
0

1
0
1
0

20
10
9
1

6-18

Typical Application Additional application notes are located at the back of section 11.
Electronically Tuned Radio Controller System; Direct Drive LED
SWITCHED
6V

8+

POSSIBLE MODULE
INSIDE DOTTED LINE

KEYBOARD
Bx4
• •

+V
RIS

34

••

10

NSC
COPs
CONTROLLER
(20 PINS)
COP42DL
FROM RADIO
'"sTATION DETECT'

5VGNO

G3 SI CKI SK SO GI

':'

CLOCK
DATA

.Ji!OPF

:!!
51

:!!

saa ~

... .. ..

.

FROM
FMVCO

FROM
AMVCO

ill. l.

!!l

:Iii
!C
! s '" ...z

1-------..--+
1---.....;;;----...;.-..........,

TOVCO

.....--I~CLOCK

DS8908B

PLL SYNTHESIZER
(2D·PIN)

RpROG

.....---~U8MHz

BIT 18 OUT
BIT 18 OUT

' " - - - - - - i 5 0 Hz

VCC2

VCCM

VCCI

GND

T
UNSWITCHED
B+

}:::~--"

TO RADIO CONTROL CIRCUITS
(MUTE, GAIN, AM, FM, STEREO)

PROGRAM
RESISTOR

--

O Fd
•' •

SWITCHED 8+
TO RADIO
TL/F/5111-13

6-19

DS8908B
AM/FM PLUSynthes/zer (Serial Data 2O-Pin Package)

Ii"

I.!11MHz

ca

n-

r--<>

ose8

~

:2

........

:11

1

•

..

o
cZ
:9

1

•

tl

:2

D1
3

50Hz

OUTPUT

osee

3.96 11Hz
XTAL

20kHz

~

..------,

~

....- - - - - -...... RpROGRAM

1•

FII
LO

•

CHARGE
PUMP

OUTPUT
VCC2

CLOCK •

1 ______. 1

ClOCK (GATEDI

OP lIIIP
OUTPUT

.1

OPAMP
aROUNO

DATA.

•

lliAIU •

•

I~

.1

SV___.VCCI

SV~VCCM
raND

"Sections operating from VCCM supply.

"Address (1,1)

BlTlI
OUTPUT

BIT 1.

OUTPUT

TUF/5111-14

~National

~ Semiconductor

OS8911/0S8913 AM/FM/TV Sound
Up-Conversion Frequency Synthesizer
General Description
The OS8911 is a digital Phase-Locked Loop (PLL) frequency synthesizer intended for use as a Local Oscillator (LO) in
electronically tuned radios. The device is used in conjunction with a serial data controller, a loop filter, some varactor
diodes and several passive elements to provide the local
oscillator function for both AM and FM tuning.
The conventional superheterodyne AM receiver utilizes a
low IF or down conversion tuning approach whereby the IF
is chosen to be below the frequencies to be received. The
OS8911 PLL on the other hand, utilizes an up-conversion
technique in the AM mode whereby the first IF frequency is
chosen to be well above the RF frequency range to be
tuned. This approach eliminates the need for tuned circuits
in the AM frontend since the image, half IF, and other spurious responses occur far beyond the range of frequencies to
be tuned. Sufficient selectivity and second IF image protection is provided by a crystal filter at the output of the first
mixer.
A significant cost savings can be realized utilizing this upconversion approach to tuning. Removal of the AM tuned
circuits eliminates the cost of expensive matched varactor
diodes and reduces the amount of labor required for alignment down from 6 adjustments to 2. Additional cost savings
are realized because up-conversion enables both the AM
and FM bands to be tuned using a single Voltage Controlled
Oscillator (VeO) operating between 98 and 120 MHz. (The
2 to 1 LO tuning range found in conventional AM down conversion radios is reduced to a 10% tuning range; 9.94 MHz
to 11.02 MHz).
Up-conversion AM tuning is accomplished by first dividing
the veo Signal down by a modulus 10 to obtain the LO
signal. This LO in turn is mixed on chip with the RF signal to
obtain a first IF at the MIXER output pins. This first IF after
crystal filtering is mixed (externally) with a reference frequency provided by the PLL to obtain a 450 kHz second IF

frequency. The OS8911 derives the 450 kHz second IF by
mixing an 11.55 MHz first IF with a 12.00 MHz reference
frequency.
FM and we (weather band) tuning is done using the conventional down conversion approach. Here the veo signal
is buffered to produce the LO signal and then mixed on chip
with the RF signal to obtain an IF frequency at the MIXER
output pins. This IF frequency is typically chosen to be 10.7
MHz although placement at 11.50 MHz can further enhance
AM mode performance and minimize IF circuitry.
The PLL provides phase comparator reference frequencies
of 10, 12.5, 25, and 100 kHz. The tuning resolutions resulting from these reference frequencies are determined by dividing the reference by the premix modulus. Table II shows
the tuning resolutions possible.
The OS8911 contains the following logic elements: a voltage controlled oscillator, a reference oscillator, a 14-bit programmable dual-modulus counter, a reference frequency divider chain, a premix divider, a mixer, a phase comparator, a
charge pump, an operational amplifier, and control circuitry
for latched serial data entry.
The OS8913 includes all the above logic elements except
that it requires a 10 MHz reference frequency instead of
12 MHz.

Features
• Oirect synthesis of LW, MW, SW, FM, and we
frequencies
• Serial data entry for simplified processor control
• 10, 12.5, 25, and 100 kHz reference frequencies
• 8 possible tuning resolutions (see Table II)
• An op amp with high impedance inputs for loop filtering
• Programmable mixer with high dynamic range

6-21

....

~r---------------------------------------------------------------~

~........

BIT Outputs: The open-collector BIT outputs provide either
the status of shift register bits 22, 23, and 24 or enable
access to key internal circuit test nodes. The mode for the
bit outputs is controlled by shift register bits 20 and 21. In
operation, the bit outputs are intended to drive radio functions such as gain, mute, and AM/FM status. These outputs
can also be used to program the loop gain by connection of
an external resistor to IPROG. Bit 24 output can also be
used as a 300 millisecond timer under control of shift register bit 19. During service testing, these pins can be used for
the purpose of either monitoring or driving internal logic
points as indicated in the TEST MODES description under
Table V.
VCOb and VCOe: The Voltage Controlled Oscillator inputs
drive the 14-bit programmable counter and the premix divider. These inputs are the base and emitter leads of a transistor which require connection of a coil, varactor, and several
capacitors to function as a Colpitts oscillator. The VCO is
designed to operate up to 225 MHz. The VCO's minimum
operating frequency may be limited by the choice of reference frequency and the 961 minimum modulus constraint of
the 31/32 dual modulus counter.
RF+ and RF-: The Radio Frequency inputs are fed differentially into the mixer.
IMXR: The bias current for the mixer is programmed by connection of an external resistor to this pin. The total mixer
output current equals 4 times the current entering this pin.
MIXER and MIXER: The MIXER outputs are the collectors
of the double balanced pair mixer transistors. They are intended to operate at voltages greater than VCCI.
OSCb and OSCc: The Reference Oscillator inputs are part
of an on-Chip Pierce oscillator designed to work in conjunction with 2 capacitors and a crystal resonator. The OS8911
requires a 12 MHz crystal to derive the reference frequencies shown in Table II. The DS8913 requires 10 MHz crystal.
The 12 MHz OSC signal is also used externally as the 2nd
AM LO to obtain a 450 kHz 2nd IF frequency in the AM
mode.
2 MHz: The 2 MHz output is provided to drive a controller's
clock input.
50 Hz: The 50 Hz output is provided as a time reference for
radios with tlme-of-day clocks.
IPROG: The IPROG pin enables the charge pump to be
programmed from 0.25 mA to 1.0 mA by connection of an
extemal resistor to ground.
cpo: The Charge Pump Output circuit sources current if the
veo frequency is high and sinks current if the VCO frequency is low. The CPO is wired directly to the negative input of
the loop filter op amp.
OP AMP: The OP AMP output is provided for loop filtering.
The op amp has high impedance PMOS gate inputs and is
wired as a transconductance amplifier/filter. The op amp's
positive input is internally referenced while its negative input
is common with the CPO output.

Connection Diagram
Plastic Chip Carrier

....

~

~CPO

t.iIXER- 5

25

t.iIXER- 6

24~IPROG

GNDL- 7

23 ~VCC2

VCCL- 8

22 ~GNDI
21 ~VCCI

ENABLE- 9
CLOCK- 10

20 ~B1T24

DATA- 11

19 ~BIT23

TLlFI739B-B

Top View
Order. Number DS8911V/DS8913V
See NS Package Number V28A

Pin Descriptions
VCC1: The VCCI pin provides a 5V supply source for all

circuitry except the reference divider chain, op amp and mixer sections of the die.
VCC2: The VCC2 pin provides a 12V supply source for the
Opamp.
VCCL: The VCCL pin provides an isolated 5V supply source
for the premix divider and mixer functions.
VCCM: The VCCM pin provides a 5V supply source for the
reference oscillator and divider chain down through the 50
Hz output, thus enabling low standby current for time-of-day
clock applications.
GND1, GND2, GNDL and GNDM: Provide isolated circuit
ground for the various sections of the device.
DATA and CLOCK: The DATA and CLOCK inputs are for
serial data entry from a controller. They are CMOS inputs
with TTL logiC thresholds. The 24-bit data stream is loaded
into the PLL on the positive transition of the CLOCK. The
first 14 bits of the data stream select PLL divide code in
binary form MSB first. The 15th through 24th bits select the
premix modulus, the reference frequency, the bit output
status, and the test/operate modes as shown in Tables I
through V.
ENABLE: The ENABLE input is a CMOS input with a TTL
logiC threshold. The ENABLE input enables data when at a
logic "one" and latches data on the transition to a logiC

"zero",

6-22

Reference Tables
cycle the timer's BIT 24 output will finish out the 300 ms
pulse. Readdressing the device with bit 19 "HI" before the
timer finishes its cycle will extend the BIT 24 output pulse
width by 300 ms. Addressing should be performed immediately after the 50 Hz output transitions "HI". BIT 24's output
state is not guaranteed during the first 300 ms after VCC1
power up as a result of a timer reset in progress.

TABLE I
Bit 15

Premix Modulus

0

+1

1

+10

TABLE V

TABLE II
Bit

Reference
Frequency

Bit

Tuning Resolution

FUNCTION OF
PINS3,4,&5

16

17

+1 Premix

+10 Premix

20

21

0

0

10 kHz

10 kHz

1 kHz

0

0

Status of Bits 22-24

0

1

12.5 kHz

12.5 kHz

1.25 kHz

0

1

Test mode 1

2.5 kHz

1

0

Test mode 2

10 kHz

1

1

Test mode 3

1
1

25kHz

0
1

100 kHz

25kHz
100 kHz

TEST MODE OPERATION
TABLE III
Bit 18

Mode

0

Normal Operation"

1

Production Test
Mode Only

Test Mode 1: Enables the BIT output pins to edge trigger
the phase comparator inputs and monitor an internal lock
detector. BIT 22 negative edge triggers the reference divider input of the phase comparator if the reference divider
state is low. BIT 23 provides the open collector ORing of the
phase comparator's pump up and down outputs. BIT 24
negative edge triggers the N counter input of the phase
comparator if the N counter state is preconditioned low.

'The user should always load BR 18 low.

Test Mode 2: Enables the BIT outputs to clock the programmable N counter, monitor its output, and force either its
load or count condition. BIT 22 provides the N counter output which negative edge triggers the phase comparator and
which appears low one N counter clock pulse before it reloads. BIT 23 positive edge triggers the N counter's clock
input if the prescaler's output is preconditioned HI. BIT 24
clears the N counter output so that loading will occur on the
next N counter clock edge.

TABLE IV
Bit 19

Timer

0

Bit 24 Status

1

Bit 24 for 300 ms

TIMER OPERATION
The timer function is provided for use as a retriggerable
"one shot" to enable muting for approximately 300 milliseconds after station changes. The timer is enabled at bit 24's
output if the normal operating mode is selected (shift register bits 20 and 21 = "LOW") and shift register bit 19 data is
latched as a "HI". The timer's output state will invert immediately upon latching bit 19 "HI" and remain inverted for
approximately 300 milliseconds. If the user readdresses the
device with bit 19 data "LOW" before the timer finishes its

Test Mode 3: Enables the BIT outputs to clock the 50 Hz
and 10kHz reference dividers and monitor the reference
divider input to the phase comparator. BIT 22 positive edge
clocks the 10kHz reference divider chain if the 10kHz output is preconditioned HI. BIT 23 positive edge clocks the 50
Hz divider chain. BIT 24 is the reference divider negative
edge trigger input to the phase comparator.

6-23

!..........
!.....
.......

w

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Supply Voltage
7V
VCCM
7V
VCC1
15V
VCC2
Input Voltage
7V
Output Voltage
Logic
7V
Op Amp and Mixer Outputs
15V
ESD Sensitivity
1000V

Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

-65·Cto + 150"C
300·C

Operating Conditions
VCCM
VCCl
VCC2
Temperature, TA

Min
3.5
4.5
7.0
-40

MlxerlBIAS
(Mixer + Mixer Current) 1

Max
5.5
5.5
12.0
+85

Units
V
V
V
·C

20

mA

DC Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Test Conditions

Min

Typ

Max

Units
V

VIH

Logic "I" Input Voltage

VIL

Logic "0" Input Voltage

IIH

LogiC "I" Input Current

VIN = 5.5V

II

Logic "1" Input Current

IlL

Logic "0" Input Current

VOH

LogiC "I"
2MHz
Output Voltage

IOH = -20 ",A

VccM-0.3

V

IOH = -400",A

VCCM-2

V

IOH = -1.0mA

VCC2- 1.5

OpAmp
VOL

Logic "0"
2 MHz
Output Voltage

2.0

o.a

V

10

",A

Data, Clock and Enable Inputs, VIN = 7V

100

Data, Clock and Enable Inputs, VIN = OV

-10

".A
",A

0.3

V

. IOL = 400 ",A

0.4

V

IOL = 250 ",A

0.3

V

Bit Outputs IOL=lmA

0.3

V

OpAmp

IOL = 1.0 mA

1.5

V

Op Amp 1/0 Shorted, VCCl = 5.5V, VCC2 = 12V,
CPO = TRI-STATEGJ), Op Amp IOH vs. IOL Applied

200

mV

50Hz

VBIAS

OpAmp InputVIl.

ICEX

High Level
Bit Outputs VCCl = 4.5V, Vo = a.av
Output Current
50Hz
VCCM = 3.5V, Vo = 5.5V
Mixers

IcPO

V

IOL = 20".A

Charge Pump Program
Current

100

",A

10

",A

100

",A

21PROG

+30

%

21pROG

+30

%

0

100

nA

VCCL = VCCl = 4.5V, Vo = 12V
0.25 mA < IcPO < 1.0 mA
21pROG = VCC1 /RpROG,
Measured IpROG to CPO

Pump-up

-30

Pump-down

-30

TRI-STATE
ICCM

VCCM Supply Current
(Static)

VCCM = 5.5V, osee = High

0.5

1.0

mA

ICCl +
ICCL

VCCl + VCCL
Supply Current

Vcc = 5.5V, Bits Hi, IMXR and IpROG Open

25

35

mA

ICC2
Mixer
IBIAS

VCC2 Supply Current

VCC2 = 12V

1.5

2.5

mA

Mixer + Mixer
Current (Note 4)

VCCl = VCCL = 5.5V, Mixer = MIXer = 12V

41MXR

+25

%

-25

300
mVrms
Mixer Input Max
Mixer IBIAS = 20 mA
Signal Level
RF + or RF - Signal Level
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range",
Ihey ara not meant 10 Imply thatlhe device should be operated allhese limits.
Note 2: Unless otherwise specified, minImax lim"s apply across Ihe -4O'C 10 +85"C lemperalure range.
Nole 3: All currents Into device pins are shown as posHlve, out of device pins as negallve, all voHage referenced 10 ground unless otherwise noted. All values
shown as maximum or minimum on absolute value basis.
Note 4: Total mixer output current (Mixer + iMx8r) .. 4 times the current into Ihe IMJ(R pin.

RFIN

6-24

AC Electrical Characteristics (Note 2)
Symbol

Parameter

Conditions

Typ

Min

Max

Units

tr

20%-80% Rise Time

200

ns

tf

80%-20% Fall Time

200

ns

DATAsu

Data Setup Time

DATAH

Data Hold Time

ENsu
ENH

100

ns

100

ns

Enable Setup Time

100

ns

Enable Hold Time

100

ns

ENpw+

Enable Positive Pulse Width

200

ns

CLKpw+

Clock Positive Pulse Width

200

ns

CLKpw-

Clock Negative Pulse Width

VCOfmax

VCO Max Frequency

See Typical Wiring Diagram

OSCf max

Reference Oscillator
Max Frequency

VCCM

VCCI

= 4.5V to 5.5V

200

ns

20

MHz

225

= 3.5V

12

MHz

Timing Diagram

B~-

VCCI ENABLE

•_ _ _ _~1.5V

ov

Veel CLOCK
OV
VCCI

ov

DATA

ENH -

,hENSU
1.5V

~

]

'1

-j rIR.!t
1.5V X

CLKpw- -I

•

• ! CLKpw.

~-~

1-

1DATAH

.i:.DATASu

I

I'I
TLIFI7398-10

MICROWIRETM Bus Format
DATA~
CLOCK

1

0

1

0

oI

1

1

I

0

0

1

0

0

--.JUL
r-l

ENABLE

BIT 22 OUTPUT

7

7

7

7

7

7

71

BIT 23 OUTPUT

7

7

7

7

7

7

71

BIT 24 OUTPUT

Z Z Z Z Z Z Z F300 =L

BIT POSITION

I' ,+ ... ""
MSB

N CODE

LSB

11JjtL9

PREMIX SELECT
REFERENCE FREQUENCY SELECT
PRODUCTION TEST BIT

MS

BIT OUTPUTS
TEST MODE CONTROLS
TIMER CONTROL
TLIFI7398-19

6·25

!..........
!...
w

('I)
..-

m
.."..Cb

!

Mode

LW
MW

SW
FM

we
TVl
TV2

IF
Frequency
(MHz)
11.55/.450
11..55/.450
11.55/.450
10.7
10.7
10.7
10.7

Tuning
Range
(MHz)
.145-.290
.515-1.61
5.94-6.2
87.4-108.1
162.4-162.6
59.75-87.75
179.75-215.75

TABLE VI. DS8911 Tuning Characteristics
Reference
VCO
Premix
Range
Frequency
Modulus
(MHz)
(kHz)
112.4-114.1
10
10
10,12.5,25,100
99.4-110.2
10
10,12.5,25
53.5 to 56.1
10
10,12.5,25,100
98.1-118.8
1
151-152
12.5,25
70.45-98.45
25
169.1-205.1
25

Tuning
Resolution
(kHz)
1,1.25,2.5,10
1,1.25,2.5
10,12.5,25,100
12.5,25
25
25

Input and Output Schematics

1

1
MIXER OUTPutS

v

~--~----~---PMMIX

~--+-----------11---""'--- PREMIX

RF-

RF.
INPutS

100

200

100

GNDL
4 (V - 0.8)
R. - - - - 2 0 0 4
MIXER IBIAS

I MXR

RESISTOR CALCULAnoN

TLlFI7398-11

TLlF17398-12

6·26

Image
(MHz)
22-23
21-23
28-30
109-130
140-142
81-109
158-194

!.............
!....

Input and Output Schematics (Continued)
-~~--t 14

VeeM

CRYSTAL - -........--+-t
OSCILLATOR

----1H

2MHz
OUT

w

osee
OSCB

2 MHz
OUTPUT
BUFFER

TLlF/7398-14

TL/F17398-13

----+---+-1

22

--t---1~---I 22

Vee l

Vee l
PIN 18 BIT 22
PIN 19 BIT 23
PIN 20 BIT 24

PIN 9 ENABLE
PIN 10 ClOCK
PIN 11 DATA

(ONE OF THREE)

INPUT
BUFFERS

ESD

(ONE OF THREE)
- ....-

GNDI
....- - - -....-122

GNDI

TL/F/7398-16

TLiF17398-15

Veel

PU

21

1 - -......- - - - ,

----+-1

Pii-

GNDI

22

I------L---I

L..-_ _ _ _....- I 1

GND2

TLlFI7398-17

6-27

TL/F17398-18

~
..-

I..-....
I

.---------------------------------------------------------------------~------,

Logic Diagram
DS89111DS8913 PLL Synthesizer

..-

OICII

DICe

IIIXEIIIIIIII

Vee.

-

OP_

OOTM
L...._ _ _ CP11

veo.

. . .-----001_
......-o__ IIIIZ

liT lIT lIT
Il! II 24

_CUI Ell

TL/FI7398-4

Note 1: The 14 bR programmable N counter Is a dual modulus counter with 31/32 prescaler. Tha minimum continuous modulus 01 the N counter Is 961.
(There are a limited number 01 valid modulus codes below 961.)
'Tha 0S8913 has + 5

Typical Application Diagram
AM/FM ETR Radio Application

SERIAL DATA

IIICROPROCESSOR

211Hz CLOCK

All
AUDIO

FIlIF i

FII

DETECTOR

AUDIO
TLlF17398-5

6-28

•E

Wiring Diagrams

...

...
....

Configuration Using PLL and First Mixer Functions

II'~"~.~ " B-If--".

l~:t11

CID

':'

-¥OOpf

CI

C20

C2t

0.1

0.1

-

...

...,

IN

Co)

...IY-_"
,

L5

....-_..JTY'I"-_ _
Z2pH

U,

121

122

II
111
12K

112

".

".7K

'"

"

""
113

....
VCC2

..
."

~

27C14

O~~

-

23
,""1

"'"

".

';'

22

.. ..

.11

..

......

(11O!1OOIVi.W)

21

'"
'"

If-

"

lOOC13

10

'"

"

27

"

~

C1OC1<

...
. .K

11

11

DA"

'"

...
330

""
FMFOUT

fU

""

""
TL/FI739S-20

Configuration Using PLL with LO Bypassing Mixer

..

"
ell

~~1

"

'"

..
.."
'"
..
."
"
..

".

"

113

IOOel3

~

U CI ..

~

3

.... "
"" "
""

22

".

.112.1

"'"

•

'"

110

I---LO.,",

-

"""

l00~

".

(JonoM Yf!II)
21

""

...

, , .•

111
12K

112

....
L5

100

10

20

11

.......
"""
.,,'

.11
ell

..

[I

27

OA~

'The mixer Is de-biased by the

50,.
2""

IU'lzOUT

..

loon resistor on the RF +
pin to act as an output buffer
for the LO signal.

TL/FI7398-21

6-29

I ~National
:::E

~ Semiconductor

MM5368 CMOS Oscillator Divider Circuit
General Description

Features

The MM5368 is a CMOS integrated circuit generating 50 or
60 Hz, 10Hz, and 1 Hz outputs from a 32 kHz crystal
(32,768 Hz). For the 60 Hz selected output the input time
base is divided by 546.133, for the 50 Hz mode it is divided
by 655.36. The 50/60 Hz output is then divided by 5 or 6 to
obtain a 10Hz output which is further divided to obtain a
1 Hz output. The 50/60 Hz select input can be floated for a
counter reset.

• 50/60 Hz output
•
•
•
•
•
•
•

1 Hz output
10Hz output
Low power dissipation
Fully static operation
Counter reset
3.5V-15V supply range
On-chip oscillator-tuning and load capaCitors are the
only required external components besides the crystal.
(For operation below 5V it may be necessary to use an
- 1 MO pullup on the oscillator output to insure startup.)

Block and Connection Diagrams
O~~~6_. ._ . ,

~VOO

1M
Q

Ii

~8PF

DECODE

50180 Hz....7_ _ _ _-t
SELECT

a

SELECT
LOGIC

..._ _ _ _ _ _ _4~---+1 50160 Hz
r

OUTPUT

3

10 Hz
OUTPUT

41Hz
OUTPUT
COUNTER RESET
ION·CHIP)

TUF/6133-1

FIGURE 1
Dual-In-Llne Package
50160 Hz OUT

VOO

50160 Hz SELECT

VSS

Order Number MM5368N
See NS Package Number N08E
10 Hz OUTPUT

1 Hz OUTPUT

OSC IN

4

OSC OUT
TL/F/6133-2

Top View
FIGURE 2

6-30

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature
Storage Temperature

Maximum Voo Voltage
Operating Voo Range
Lead Temperature (Soldering. 10 sec.)

16V
3.5V::;; Voo ::;; 15V
300·C

-0.3V to Voo + 0.3V
O·Cto +70·C
-65·Cto + 150·C

Electrical Characteristics TA within operating range, Vss =
Parameter

OV

Conditions

Min

Typ

Max

Units

10

IlA
IlA

Quiescent Current Drain

Voo = 15V; 50/60 Select Floating

Operating Current Drain

fiN = 32 kHz, Voo = 3.5V
fiN = 32 kHz, Voo = 15V

60
1500

Maximum Input Frequency

Voo = 3.5V
Voo = 15V

64
500

kHz
kHz

Output Current Levels
Logical "1", Source
Logical "0", Sink

Voo =
VOH =
VOL =
VOO =
VOH =
VOL =

-400

p.A
p.A

-1500

p.A
p.A

Logical "1", Source
Logical "0", Sink

5V
VSS +
VSS +
9V
VSS +
Vss +

2.7V
0.4V

400

6.7V
O.4V

1500

50/60 Select Input (Note 1)
Voo = 3.5V, VIN ;;, 0.9 Voo
Voo = 15V, VIN ;;, 0.9 Voo
Voo = 3.5V, VIN ;;, 0.1 Voo
Voo = 15V, VIN;;' 0.1 Voo

Input Current Levels
Logical "1" (IIH)
Logical "1" (lIH)
Logical "0" (11Ll
Logical "0" (lILl

50
3
20

p.A

IlA
mA

IlA
mA

Note 1: The Input current level test Is performed by first measuring the open ctrcult voltage at the 50/60 Hz select pin. If the voltage Is "high", make the I'H test If
the voltage is "low", make the I,L test. The state of the 50/60 Hz select pin may be changed by applying a pulse to OSC IN (pIn 6) while the 50160 Hz pin is open
ctrcult

Functional Description (Figure 1)
and 1 Hz outputs have an approximate 50% duty cycle. In
the 50 Hz mode the 50/60 select input is tied to Vss. The
50 Hz output waveform can be seen in Figure 3. The 10Hz
output has an approximate 40% duty cycle and the 1 Hz
output has an approximate 50% duty cycle.

The MM5368 initially divides the input time base by 256.
From the resulting frequency (128 Hz for 32 kHz crystal) 8
clock periods are dropped or eliminated during 60 Hz operation and 28 clock periods are eliminated during 50 Hz operation. This frequency is then divided by 2 to obtain a 50 or
60 Hz output. This output is not periodic from cycle to cycle;
however, the waveform repeats itself every second. Straight
divide by 5 or 6 and 10 are used to obtain the 10Hz output
and the 1 Hz outputs.

For the 50/60 Hz select input floating, the counter chain is
held reset, except for the initial toggle flip-flop which is
needed for the reset function. A reset may also occur when
the input is switched (Figure 4). To insure the floating state,
current sourced from the input must be limited to 1.0 IlA and
current sunk by the input must be limited to 1.0 p.A for
Voo = 3.5V.

The 60 Hz mode is obtained by tying pin 7 to Voo. The
60 Hz output waveform can be seen in Figure 3. The 10Hz

Timing Diagrams
60 Hz
OUTPUT
I
I

7.8ms-:
I
I

I

I

,:
:

l{

PHASE SHIFTED EVERY 8 CLOCKS DUE TO
ELIMINATION OF 1 INPUT CLOCK (i••. , 128 Hz CLOCK)

}-.J

{

1 CLOCK DROPPED
rEVERY & 128 Hz CLOCKS

50 Hz
OUtpUT

L{

PHASE SHIFTED 3 TIMESISEC
DUE TO ELIMINATION OF 3
128 Hz CLOCKS

FIGURE 3. 50/60 Hz Output
6-31

TL/F/6133-3

Timing Diagrams (Continued)
16kHz

flOATING

r ----------n..____..

INPUT _ _ _..I

L...-_---I

RESET _ _ _ _. . I n.._ _ _ _...

50/60

SElECT _ _ _..I
TLlF/6133-4

Voo

TL/F/6133-5

FIGURE 4. 50/60 Select and Reset

Typical Applications
RESET

LATCH

Voo

NSB7861

15

16
17

MMI388 10 Hz ..3_ _ _ _....
'2

.....-~~-~OSC IN

1Hz

MM74C927

4

-If the crystal used is a mlcrowatt type an
R value will be required to limH power to
the crystal.

3.5V R=O
5V R = lOOK
10V R = 330K

TL/F/6133-6

FIGURE 5. 10 Minute (9:59.9) Timer

6·32

~National

~ semiconductor

MM5369 17 Stage Oscillator/Divider
General Description

Features

The MM5369 is a CMOS integrated circuit with 17 binary
divider stages that can be used to generate a precise reference from commonly available high frequency quartz crystals. An internal pulse is generated by mask programming
the combinations of stages 1 through 4, 16 and 17 to set or
reset the individual stages. The MM5369 is advanced one
count on the positive transition of each clock pulse. Two
buffered outputs are available: the cyrstal frequency for tuning purposes and the 17th stage output. The MM5369 is
available in an 8-lead dual-in-line epoxy package.

• Crystal oscillator
• Two buffered outputs
Output 1 crystal frequency
Output 2 full division
• High speed (4 MHz at VDD = 10V)
• Wide supply range 3V -15V
• Low power
• Fully static operation
• 8-lead dual-in-line package
• Low Current

Option
3.58 MHz to 60 Hz

• MM5369AA

Connection and Block Diagrams
Dual-In-Llne Package

OSC OUT

TUNER
OUTPUT OSC OUT OSC IN

Is

7

5

6

OSC IN

DIVIDER
OUTPUT

TUNER
OUTPUT

-

r:-

TL/FI10820-2

FIGURE 2
DIVIDER
1
DIVIDER

2
Vss

13

NC

14
NC

OUTPUT

OUTPUT

14

NC

113

NC

112

NC

Voo

TUNER
OUTPUT OSC OUT

10

111

8

9

TLlF/l0820-1

Top View
Order Number MM5369AA/N
See NS Package Number
N08E

r-r--

'--

r--

1

12
NC

13

NC

14
NC

15
NC

16
NC

7
OSC IN
TL/F/10820-S

Order Number MM5369AA/M
See NS Package Number M14A

6-33

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
-0.3V to Voo + 0.3V
Operating Temperature
O·C to + 700C
Storage Temperature
- 65·C to + 1500C

Package Dissipation

500mW
16V

Maximum Vee Voltage
Operating Vee Range
Lead Temperature (Soldering, 10 seconds)

3Vto15V
300·C

Electrical Characteristics
TA within operating temperature range, Vss = GND, 3V :5: Voo :5: 15V unless otherwise specified.
Parameter

Conditions

Min

Quiescent Current Drain

Voo = 15V

Operating Current Drain

Voo = 10V, fiN = 4.19 MHz

Frequency of Oscillation

Voo = 10V
Voo = 6V

Output Current Levels

Voo = 10V
Vo= 5V

Output Voltage Levels

1.2
DC
DC

Logical "1 " Source
Logical "0" Sink

Typ

Max

Units

10

p,A

2.5

mA

4.5
2

MHz
MHz

p.A
p.A

500
500
Voo = 10V
10 = 10 p,A

Logical "1"
Logical "0"

9.0
1.0

V
V

Note: For 3.58 MHz operation, Voo must be :> 10V.

Functional Description
A connection diagram for the MM5369 is shown in Figure 1
and a block diagram is shown in Figur62.

DIVIDER
A pulse is genertaed when divider stages 1 through 4, 16
and 17 are in the correct state. By mask options, this pulse
is used to set or reset individual stages of the counter. Figure 4 shows the relationship between the duty cycle and the
programmed modulus.

TIME BASE
A precision time base is provided by the interconnection of
a 3,579,545 Hz quartz crystal and the RC network shown in
Figure 3 together with the CMOS inverter/amplifier provided
between the OSC IN and the OSC OUT terminals. ReSistor
R 1 is necessary to bias the inverter for class A amplifier
operation. CapaCitors C1 and C2 in series provide the parallelload capacitance required for preCise tuning of the quartz
crystal.

OUTPUTS
The Tuner Output is a buffered output at the crystal oscillator frequency. This output is provided so that the crystal
frequency can be obtained without disturbing the crystal oscillator. The Divide Output is the input frequency divided by
the mask programmed number. Both outputs are push-pull
outputs.

The network shown provides> 100 ppm tuning range when
used with standard crystals trimmed for CL = 12 pF. Tuning
to better than ± 2 ppm is easily obtainable.

6-34

Functional Description (Continued)

-

OSCIN--

-----------------OSCOUT

~

E.

Rl
20M

lii

~
~

~--------~~DI~------~

=
i! Cl
3.5795~5 MHz
7-5-36pF
C =12pF
Voo OR Vss (10V) -

=!::::

C2
l""30pF
L
.....- - - - - - - - - - '
TL/F/10820-3

110
100
90
80
70
60
50
40
30
20
10
0

J
'f

/

-~
0

'To be selected based on X1a1 used

10

20

30

_i""'"

40

50

v
60

70

DUTY CYCLE (:Ie)

FIGURE 3. Crystal Oscillator Network

TL/FI10820-4

FIGURE 4. Plot of Dlvlde·By V8 Duty Cycle

...J

2.S

",

2.0

&l'
on
e

~

V

./

1.5

V

~ 1.0

V'VOO= 10V

,

-:::: f...:::: ~-.
I"'"

0
0

1

2

3

.- .

.1.

32~78"

COUNTS

59,659 COUNTS
TL/FI10820-6

".,...

FIGURE 6. Output Waveform for the MM5369AA

~ ~ ,,"

o.s

_---ill

1
.....

6'875
COUNTS

Voo = SV
5

11Hz
TLlF/10820-5

FIGURE 5. Typical Current Drain
vs Oscillator Frequency

6·35

i

:II
:II

IIZI National
~ Semiconductor

MM5437 Digital Noise Source
General Description

Features
Internal self-contained oscillator
Single supply voltage range of 4.5V to 11V
TTL compatible at 5V
Normal and sequence-limited outputs
Low power consumption
One minute cycle time
External loading and clocking capability
Automatic reset for all-zeros state
Uniform noise quality
Uniform noise amplitude
Eliminate noise preamps
Single component insertion

The MM5437 device is a monolithic metal gate NMOS integrated circuit which may be used as a digital noise source or
a pseudo-random number generator. The part is designed
to produce a broadband white noise signal with uniform
noise quality and output amplitude. Two outputs are provided. The first, OUT 1, is sequence-limited to reduce
"thumps." The other output, OUT 2, is the last stage of the
shift register when CONTROL 2 is left floating or is pulled
up. Typical cycle time is one minute. Data is clocked in and
out on the rising edge of the clock.

Applications
•
•
•
•

Electronic musical rhythm instrument sound generators
Music synthesizer white and pink noise generators
Room acoustics testing/equalization
Pseudo-random number generator

Block and Connection Diagrams

OUTZ/DATA IN
OUT 1

CONTROL 1
INTlEXT CLK

TL/F/52fJO-1

OUT 1
NC
¥DD 3

¥Is 4

cmnL1
INTERNAL/EXTERNAL CLOCK

COiTiiiiLi
OUT ZlOATA IN
TL/F/5260-2

Top View

Order Number MM5437N
See NS Package Number N08E

6-36

Absolute Maximum Ratings indicate limits beyond which
damage to the device may occur.

Absolute Maximum Ratings
Operating Supply Voltage, Voo

12V
-65·Cto + 150"C

Storage Temperature, Ts
Operating Temperature, TA

-40"Cto +B5·C
±12mA

DC Output Current, per pin
Lead Temp. (Soldering, 10 seconds)

+300"C

DC Electrical Characteristics TA within operating range, Vss =
Parameter

Conditions

Min

Supply Voltage (Voo)
Supply Current (100)
Output Voltage Levels
Logic '0'
Logic '1'

~

Max

Voo = 4.5V (No load)
Voo = 11V (No load)
IOl = + 1.6 mA, Voo = 4.5V
IOH = -400 /LA, Voo = 4.5V

VSS
2.4

Units

11

V

4
5

mA
mA

0.4
VOO

V
V

O.B
V

2.0
200
200

p.A

30

140

kHz

25

110

sec.

VIN = O.4V
VIN = 2.4V

Half Power Point·
Cycle Time
•Half Power Point

Typ

4.5

Input Voltage Levels
Logic '0'
Logic '1'
Input Currents
Logic '0'
Logic '1'

OV, Voo = 11V, unless specified

/LA

0.45 (Shift Register Clock Frequency)

ACTiming

-40·C:;;; TA:;;; +B5·C
4.5V :;;; VOO :;;; 11V
Min

Data Set Up Time Prior to Clock

100

ns

tH

Data Hold Time After Clock

100

ns

Symbol

Max

Units

Parameter

ts

tc20V

COf\JiI'iCi[ 2 to Data Out Valid

100

tclKOV

Clock to Data Out Valid

700

tpH

Clock Pulse Width High

1.5

tpl

Clock Pulse Width Low

1.5

t r, tf

Input Rise and Fall Times

ns
ns
/Ls
/Ls

220

ns

Inputs/Outputs
OUT 1: An output pin for the sequence-limited output from
the shift register.

CONTROL 1: A mode switch input, which when held at a
logic "1" or left floating, gates the internal oscillator onto
the INT/EXT CLK pin. When CONTROL 1 is at a logic "0",
the shift register can be driven externally through the INT /
EXTCLK pin.

INT/EXT ClK: An input/output pin. See CONTROL 1 for
description.
OUT 2/DATA IN: An input/output pin. See CCif\JiI'iOL 2 for
description.

CONTROL 2: A mode switch input, which when held at a
logic "1" or left floating, gates the last stage of the shift
register onto the OUT 2/0ATA IN pin. When CONiRCi[ 2 is
at a logic "0", the shift register can be loaded externally
through the OUT 2/0ATA IN pin.

6-37

I

Timing Diagrams

:IE

cue
DATA

IN

_""I~""'

_______

- J _ _ _ _ _ _ _ _ _- ' ,,_ _ _ _ __

DATA
OUT _ _.,...."1""'-_ _ _ _ _ _ _..,,,,_ _ _ _ _ _ _ _ _-'

"'_ _
TL/F/5260-3

)~

oun

ANY VoD --iiMl'7ll'--....
INPUT

VAUDDATA

OV

TL/F/5260-4

80

80

T=25°C

T=25°C
VDO=11V

50

i

40

j

30

TL/F/5260-5

50

-

VDOVDO=8V

VDO=8V

20

Irj ;J::;.5V

10

o

024

8

.Dtr~-

10

8

o

ro u

......
o

VouT (V)

4

8

10

12

Your (V)
TL/F/5260-7

TL/F/5260-6

FIGURE 1. ISINK VB VOUT

FIGURE 2. ISOURCE VB VOUT

Typical Applications
~5

3k

MM
CONTROL18 8431 7

MM OUT 1
5437

~--

OUT 2/0ATA IN
SEIIIAL

TO

PARALLEL

"
,..,

CLOCK

TL/F/5.260-9

TL/F/5260-6

FIGURE 3. Pink Nol.e Generator

FIGURE 4. Pseudo-Random Number Generator

6-38

Section 7
Special Automotive

•

Section 7 Contents
Automotive Standard Products Selection Guide.................................. ......
LM903 Fluid Level Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1042 Fluid Level Detector.............................. ......... .................
LM1815 Adaptive Sense Amplifier. . . . .. . . .. . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . .. .. . . . . . . . .
LM1819 Air-Core Meter Driver................ .... ................. ........... .......
LM1830 Fluid Detector.................................... ......... .................
LM19211 Amp Industrial Switch......................................................
LM1946 Over/Under Current Limit Diagnostic Circuit... ....... ... .... ...................
LM1949 Injector Drive Controller... ........................ ..........................
LM1950 750 mA High Side Switch....................................................
LM1951 Solid State 1 Amp Switch....................................................
LM1964 Sensor Interface Amplifier. .................... .................... ..........
LMD18400 Quad High Side Driver....................................................

7-2

7-3
7-4
7-10
7-17
7-21
7-29
7-35
7-40
7-51
7-59
7-64
7-72
7-76

Ii National
Semiconductor

Automotive Standard Products
High Current Switch Selection Guide
Device

Drlversl
Package

Continuous
Cu"ent

Peak
Current

Input Voltage
Range

Dlsgnostlcs

LM1921'

1

1.0A

2.0A

4.5Vto26V

none

LM1950'

1

750mA

1.4A

4.75Vto26V

none

LM1951'

1

1.0A

2.5A

4.5Vto 26V

Error Flag

LMD1B400'

4

1.0A

3.0A

6Vt02BV

Error Flag
Thermal Shutdown Flag
Data Output provides switch status feedback, output
load fault conditions and thermal and overvoltage
shut-down status.

• All incorporate Automotive transient protecUon.

Liquid Level Sensor Selection Guide
Output Type

Operation Method

LM903

LM1042

LM1830

Digital HIILO

Analog

Digital HIILO

Thermoresistive Probe

Thermoresistive Probe

Conductive Liquid

Special Amplifiers Selection Guide
LM1815

LM1964

Typical Application

Adaptive Sense Amplifier

Sensor Interface Amplifier

Sensor

Inductive Pickup

Lambda Sensor

Key Features

• Operates from 2.5V to
12VSupply

• Normal Operation
Guaranteed with inputs
up to 3V below Ground
on a Single Supply
• Fully Protected Inputs
• Input Open Circuit
Detection

• Adaptive Hysteresis
• True Zero Crossing
Timing Reference

•
7-3

~ .-------~-------------------------------------------------------------------,

~ ~National
~Semiconductor

LM903 Fluid Level Detector
General Description

Features

The LM903 uses the thermal-resistive probe technique to
measure the level of nonflammable fluids. A low fluid level is
indicated by a warning lamp operating in continuous or
flashing mode. All supervisory requirements to control the
thermal-resistive probe, including short and open circuit
probe detection, are incorporated within the device. The circuit has possible applications in the detection of hydraulic
fluid, oil level, etc., and may be used with partially conducting fluids.

•
•
•
•
•
•
•
•
•
•

Flashing or continuous warning indication
Warning threshold externally adjustable
Control circuitry for thermal-resistive probe
Switch on reset and delay to avoid transients
600 rnA flashing lamp drive capability
Short and open circuit probe detection
70V transient protection on supply and control input
7V -18V supply range
Internally regulated supply
- 40"C to + 80"C operation

Connection Diagram
Dual·ln-Une Package

MEAS INPUT

..! •

V

2
MEASGNDPROBE I REF..!

....!
PROBE ..!

PNPBASE

16
r- MEAS REF V
15
r-MEMORYC
14
I-- AUX OUTPUT
13
I-- RAMPR
12
I-- RAMPC

~VREG
~OSCC
~ LAMP DRIVER

SUPPLY...!
START INPUT ..!.
GND...!
TOP VIEW

Order Number LM903N
See NS Package Number N16E

7-4

TLIH/5699-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee
18V
Control Input Voltage (Pin 7)
1aV
Transient Voltage (Pins, 6, 7, 9) 10 ms (Note 1)

-40"Cto +85°C

Operating Temperature Range
Storage Temperature

-55°C to + 150"C

Maximum Junction Temperature

+ 150"C

Lead Temperature (Soldering, 10 sec.)

260"C

70V

Output Current (Pin 4) 14 (Sink)

10mA

Electrical Characteristics
Vee = 12V, CT = 33 /loF, RT = 7.5 kO, TA within operating range except where stated otherwise

Symbol

Parameter

Tested Limits
(Note 2)

Conditions

Min
Vee

Supply Voltage

Is

Supply Current

VREG

7.0

Max

Min

Typ

18

7.0

13

50

Regulated Voltage
Regulation
Temperature Drift

Design Limits
(Note 3)

5.5
Vee = 7.2V-1BV

6.2

5.3

5.8

Units
Max
18

V

50

mA

6.3

105

V
mV
/loVioC

500

Ve-Vs

Probe Current
Reference Voltage

2.0

2.35

1.95

2.20

2.40

V

VREF

Measurement Reference Voltage

790

900

780

850

910

mV

RREF

Reference Input Resistor

V7

Start Input Logic High Level

V7

Start Input Logic Low Level

17

High Input Current

Latch Off

17

Latch Holding Current

Latch On

2.5

nA

R7

Resistance Pin 7

Latch On

22

kO

Ramp Current

See Timing Diagram

Charging

V12 = OV-tV

600

1100

590

1100

/loA

V12 = 1V-4V

53

93

50

96

Il-A

V12 = 4.tV

-700

-450

-710

-440

/loA

V12 = 0.5V

-650

-400

-660

-390

/loA

Probe Current Start

570

850

550

710

870

mV

First Measurement

910

1200

890

1055

1220

mV

Second Measurement

910

1240

890

1080

1270

mV

VREG-1.0

V

112

Discharging

V12

Ramp Threshold

1.2

kO

1.6

V
1.0

V

100

nA

See Timing Diagram

V1

Probe Input Voltage Range

Vee = 7.5V-18V

Vs

Probe Open-Circuit Threshold

At Pin 5

1

V

VREG-0.85 VREG-0.6
0.6

Vs

Probe Short-Circuit Threshold

11

Pin 1 Input Leakage Current

Pin 1 = 300mV

-3.5

+3.5

11S

Pin 15 Leakage Current

V15 = 2V, V7 = 12V

-3.5

3.5

Pin 15 Charging Current

V15 = 4V, V7 = 12V

60

fg

Lamp Oscillation Frequency

CL = 3.3/loF

Ig

Lamp Driver Current

Flashing Mode

Vg

Lamp Driver Saturation

19 = 200mA

V
nA
/loA

Il-A
0.5

200

7-5

0.85
+5.0

1.5

2.5

Hz

600

mA

250

mA

•

Electrical Characteristics (Continued)
Vee = 12V,

Or

=

33

p.F, RT =

7.5 kO,

TA within operating range except where stated otherwise
Tested Limits

Symbol

Parameter

(Note

Conditions

Min
V14

Auxiliary Output
Voltage

VI

Design Limits

2)

(Note
Min

Max

Typ

Units
Max

5.0

Lamp OFF

V

Lamp ON

Alarm Level

3)

(Difference Between First

230

and Second Measurement)

280

1.2

V

330

mV

Sensitivity to Electrostatic Discharge: Pins 7. 10. 13. and 14 will wnhstand greater than 1500V when tested using 100 pF and 15000 In accordance wnh National
Semiconductor standard ESO test procedures. All other pins will withstand In excess of 2 kV.
Note 1: Test circun for overvoltage capability at pins 3. 6. 7.
Note 2: Guaranteed 100% production tested at 25'C. These limns are used to calculate outgoing quality levels.
Note 3: Umils guaranteed to include parametric variations. TA
figures.

=

-4Q'C to +SO'C and from Vee

= 7.5V-1SV. These limns are not used to calculate AOOL

Note 4: Variations over temperature range are not production tested.
13V

LM903

TLlH/569S-2

In Lamp ON condition. Is should be limited to 600 mAo

Block and Application Circuit
Cr

331'

10

12

13

3 . .- - - - - - - - - - - -. . . .- - - - - - - -. . .

Vee
7

T

TLlH/5699-3

Memory capaCitor on pin 15 is set
High-lamp off
Low-Lamp on

7·6

Circuit Timing Diagram
V12

4.1V

4V

tl

25ms

O.7V

t2

35ms

1.0V

1st Measurement

t3

t2

+ 1.5s
t3 + 10ms
14 + Sms

1.0V

2nd Measurement

O.SV

Measurement Latched

O.7V

Probe Current Off

t4
t5

Threshold

IV hrL-------------.:\1

r---,
I
,

LAMP CURRENT

,.-,

LAMP OFF OR FlASHING
DEPENDING ON MEASUREMENT

TUH/5699-4

Circuit Operation
A measurement is initiated when the supply is applied, provided the control input pin 7 is low. Once a measurement is
commenced, pin 7 is latched low and the ramp capacitor on
pin 12 begins to charge. After 25 ms when switch-on transients have subsided, a constant current is applied to the
thermo-resistive probe. The value of probe current, which is
supplied by an external PNP transistor, is set by an external
resistor across an internally generated 21 V reference. The
lamp current is applied at the start of probe current.

Using resistance wire of 50 p.Ocm resistivity, 8 cm of 0.08
mm (40 AWG) give approximately 80 at 25'C. Such a probe
will give about 500 mV change between first and second
measurements in air, and 100 mV change with oil, hydraulic
fluid, etc., in the application circuit. With an alarm threshold
of 280 mV (typ) lack of fluid can readily be detected. As the
probe current, measurement reference and measurement
period are all externally adjustable, there is freedom to use
different probes and fluids.

35 ms after switch-on, the voltage across the probe is sampled and held on external capacitor C1 (leakage current at
pin 1 less than 1 nA). After a further 1.5 seconds the difference between the present probe voltage and the initial
probe voltage is measured, multiplied by 3 and compared
with a reference voltage of 850 mV (externally adjustable
via pin 16). If the amplified voltage difference is less than
the reference voltage the lamp is switched off, otherwise
the lamp commences flashing at 1 Hz to 2 Hz. 10 ms later
the measurement latch operates to store the result and after a further 8 rns the probe current is switched off.

Another possibility is the use of high temperature coefficient
resistors made for special applications and positive temperature coefficient thermistors. The encapsulation must have
a sufficiently low thermal resistance so as not to mask the
change due to the different surrounding mediums, and the
thermal time constant must be quick enough to enable the
temperature change to take place between the two measurements. The ramp timing could be adjusted to assist this.
Probes in liquids must be able to drain freely.

A second measurement can only be initiated by interrupting
the supply. An external CR can be arranged on pin 7 to
prevent a second measurement attempt for 1 minute. The
measurement condition stored in the latch will control the
lamp.
PROBES
The circuit effectively measures the thermal resistance of
the probe. This varies depending on the surrounding medium (Figure 1). It is necessary to be able to heat the probe
with the current applied and, for there to be sufficient
change in resistance with the temperature change, to provide the voltage to be measured.

PROBE TEMPERATURE ('C)

FIGURE 1_ Typical Thermo-Resistive Probe

Probes require resistance wire with a high resistivity and
temperature coefficient. Nickel cobalt alloy resistance wires
are available with resistivity of 50 1L0cm and temperature
coefficient of 3300 ppm which can be made into suitable
probes. Wires used in probes for use in liquids must be designed to drain freely to avoid clogging. A possible arrangement is shown in Figure 2.
The probe voltage has to be greater than 0.7V to prevent
short circuit probe detection less than 5V to avoid open
circuit detection. With a 200 mA probe current this gives a
probe resistance range of 40 to 250. This low value makes
it possible to use the probe in partially conducting fluids.
TLiH/S699-S

FIGURE 2
7-7

7·8

Application Hints
INTERNAL COMBUSTION ENGINE OIL LEVEL

3V, the memory capaCitor will be refreshed on powering up
again. There is no internal pull down on detecting an incorrect measurement. If it is required to use pin 15 as an output
indicating the measurement result, an external pull down
resistor and buffer will be required.

The basic system provides a single shot measurement
when the supply is applied and has a primary application in
automotive oil, hydraulic fluid and coolant monitoring. Particularly in the case of the oil level, a valid measurement is
only possible before the oil is disturbed. The application circuit shown is arranged such that the measurement is made
when the ignition is switched on via switch A. Switch B is the
oil pressure sensor and is closed before the engine starts,
keeping pin 7 low and enabling the measurement.

CONTINUOUS WARNING LAMP

The lamp can be arranged to light continuously by disabling
the oscillator with a resistor of 150k or less, connected between pins 10 and 11.
REPETITIVE MEASUREMENTS

STALLING AND RESTART PROTECTION

Measurements may be repeated by strobing the supply to
pin 6. The probe current regulator transistor must have the
same supply as pin 6, but the warning lamp can be permanently powered. The lamp will light during each measurement and will flash in between measurements when incorrect conditions are detected.

The 4M7 resistor and 10 /A-F capacitor connected to pin 7
provide the restart protection. When oil pressure builds up,
switch B opens and the 10 /A-F capacitor charges through
the bulb. At switch-off, the capaCitor discharges slowly and
is capable of preventing a low state on pin 7 for 1 minute.
Unless pin 7 is low, a new measurement can not be made
and the previous measurement result stored in the memory
capaCitor on pin 15 is used to control the output.

ALTERNATIVE APPLICATIONS
Gas flow detection: The cooling effect of gas flowing over
a probe could be used to provide a warning signal from the
LM903 in the event of gas failure.

MEMORY

The pin 15 memory output goes high if a correct measurement is made (lamp off). If the power is removed, pin 15
leakage is less than 3 /A-A and the memory status is retained
for some time. Provided pin 15 voltage does not fall below

Automatic top up: With the LM903 strobed continuously,
the output may be stored, buffered, and used to drive solenoid valves to correct a fluid level as required.

fI

7-9

~

~
,...

r------------------------------------------------------------------------------------,

....::E ~National
~ semiconductor
LM 1042 Fluid Level Detector
General Description

Features

The LM1042 uses the thermal-resistive probe technique to
measure the level of non-flammable fluids. An output is provided proportional to fluid level and single shot or repeating
measurements may be made. All supervisory requirements
to control the thermal-resistive probe, including short and
open circuit probe detection, are incorporated within the device. A second linear input for alternative sensor signals
may also be selected.

•
•
•
•
•
•
•
•
•
•

Selectable thermal-resistance or linear probe inputs
Control circuitry for thermal-resistive probe
Single-shot or repeating measurements
Switch on reset and delay to avoid transients
Output amplifier with 10 mA source and sink capability
Short or open probe detection
+ SOV transient protection on supply and control input
7.SV to 18V supply range
Internally regulated supply
-40'C to +80'C operation

Block Diagram
+Vs

RT

--------------.,
:
,

CONTROL
INPUT

'8

5
VREG
fEEDBACK

10
GAIN
ADJUST

2

1;,;,;,;;;...,...;;;;.;;1

TLlH/8709-1

7-10

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee

32V

Voltage at Pin B

32V

Positive Peak Voltage (Pins 6, B, 3) (Note 1)
10ms2A

Output Current Pin 11 (source)

- 40·C to + BO·C

Operating Temperature Range

- 55·C to + 150·C

Storage Temperature Range
Lead Temperature (Soldering 10 sec.)

50V

Output Current Pin 4, (l4)(sink)

25mA
±10mA

Output Current Pin 16

10mA

260"C

Package Power Dissipation
T A = 25·C (Note B)

I.BW

Device Power Dissipation

0.9W

Electrical Characteristics
Vee

=

Symbol

13V, TA within operating range except where stated otherwise. Cr

Parameter

=

22 IJoF, Rr

Supply Voltage

IS

Supply Current

VREG

Va-V3

T1

12k

Tested Limits
(Note 2)

Conditions

Min
Vee

=

7.5

Design Limits
(Note 3)

Max

Min

Typ

lB

7.5

13

35

Regulated Voltage

Pins 15 and 11 connected

Stability Over Vee Range

Referred to value at
Vee = 13V(Note4)

5.7

2.15
(Note 4)

Ramp Timing

See Figure 5

5.65

5.9

±0.5

Probe Current
Reference Voltage
Probe Current Regulation
Over Vee Range

6.15

2.35

2.10

2.25

±0.5
20

37

15

31

3

T2-T1
T4-T1

Ramp Timing

TsrAB

Ramp Timing Stability

1.4
Over Vee Range

2.1

1.4

1.75

+5

6.2

V

±0.5

%

2.40

V

±O.B

%

42

ms

16

ms

2.1

s

±5

%

15.0

kO

0.5

V

Ramp Resistor Range
Start Input Logic High Level

Va

Start Input LogiC Low Level

la

Start Input Current

Va

100

nA

Start Input Current

Va

300

300

nA

V1S

Maximum Output Voltage

= Vee
= OV
RL = 6000 from

100

la

Minimum Output Voltage

Pin 16 to VREG

0.6

V

2

%

Non-linearity of G1
OS1

Pin 1 Offset

G2

PROBE 2
Probe 2 Gain
Non-linearity of G2

OS7

Pin 7 Offset

R7

Input impedance

1.7

3

V
mA

Rr

PROBE 1
Probe 1 Gain

15

lB
35

Va

G1

3

Units
Max

1.7

V

0.5

VREG-0.3

Pin 1 BO mV to 520 mV
(Notes 6, 7)
Pin 1 BO mV to 520 mV
(Note 7)

V

VREG-O.3
0.5

0.2

9.9

10.4

10.15

-1

+1

-2

0
±5

(Note 7)
Pin 7 240 mV to 1.562V
(Note 7)
Pin 7 240 mV to 1.562V
(Note 7)
(Note 7)

7-11

3.31

3.49

-1

+1

mV

3.4
-2

0.2

2

%

±5

mV

5

MO

,.

~

•~

r---------------------------------------------------------------------------------,
Electrical Characteristics

:!!l

Vee

= 13V, TA within operating range except where stated otherwise. CT = 22 ,...F, RT = 12k (Continued)

Symbol

Parameter

Vl

Probe 1 Input
Voltage Range

Vee = 9Vto18V
Vee = 7.5V, 14 < 2.5 mA
(VREG = 6.0V)

V5

Probe 1 Open
Circuit Threshold

At Pin 5

V5

Probe 1 Short
Circuit Threshold

114

Pin 14 Input
Leakage Current

Pin 14

11

Pin 1 Input
Leakage Current

Pin 1 = 300mV

TR

Repeat Period

CR

= 4V

= 22,...F (Note 5)
CR = 22,...F

CR Discharge Time

Design Umlts
(Note 3)

Tested Limits
(Note 2)

Conditions

Min

Max

Min

1

5

1
1

Typ

Units
Max
5
3.5

V
V

VREG-0.7 VREG-0.5 VREG-0.85 VREG-0.6 VREG-0.35

V

0.35

0.85

V

2.0

nA

1.5

5.0

nA

17

36

s

0.5

0.7

-2.0

2.0

-5.0

5.0

12

28

9.1

0.6

135

ms

CM

Memory Capacitor Value

70

0.47

,...F

Cl

Input Capacitor Value

0.47

,...F

Sensitivity fo Electrostatic DischargePins 7. 10, 13, and 14 will
procedures.

w~hstand

greater than 1500V when tastad using 100 pF and 15000 in accordance with National Semiconductor standard ESD test

All other pins will withstand in excess of 2 kV.
Nota 1: Test elreuH for over voltage capability at pins 3, 6, 8.

"W~.
6000,...r

ov

ctI

TLlH/8709-2

Note 2: Guaranteed and 100% production tasted at 25'C. These IimHo are used to calculata outgoing quality levels.
Note 3: Limits guardbanded to Include parametric variations. TA
figures.

~

-4O"C to +80'C and from Vee

~

7.5Vto 18V. These IImHoare not used to caleulateAOOL

Note 4: Variations over temperature range are not production tasted.
Nota 5: Time for first repeat period, sea FIgure 6.
Nota 8: Probe 1 amplHler testa are measured with pin 12 ramp voltage held between the T3 and T4 conditions (pin 12 '" 1.1 V) having previously been held above
4.1V to simulate ramp action. See Figure 5.
Nota 7: When measuring gain separate ground wire sensing is required at pin 2 to ensure sufficiently accurate results.
Linearity is defined as the difference between the predicted value of VB (VB') and the measured value.
Nota 8: Above TA

= 25'C derate with 8jA

Vc

~

7O'C1W.

- - - - - - -

VC-VA
For probe 1 and probe 2--Gain (G) ~ V0 - Va

Va - - - - VA

--

I
I
I
I
I
I
I

Input offset

I
I
I

Linearity

I

V. Vb
c
PI - 80 300 520(mV)
P2 - 240 900 1562

=

=

[~- Vo]

[~: -

1] x

VB' ~ VA + G(Vb - Val

TL/H/8709-15

7-12

100%

Typical Performance Characteristics
Supply Current va
Supply Voltage
<10

!

.---,----,--.,.-~~-~

Probe Reference V va
Supply Voltage

6.1

~

~

IE
iil

Regulated Voltage va
Supply Voltage

-I-"

25

~~

--

30

~

20

10

,.,... ....

-

5.9

~

15

~~

6.0

I

2.32

.---,----,--.,.-_~-~

2.30

1-+---+--1--+-1----1

2.28 1-+---+--1--+-1----1

2.261-+-+-+--+-~-l
~,.,...1--+-....
-::::oI._~=l---l--I

2.24

2.22

1--+-+--\-+--jf.---1

5.8

5

10

15

5

20

10

15

20

SUPPLY VOlTAGE (V)

SUPPLY VOLTAGE (V)

Output Voltage va
Pin 7 Voltage

6r--,----,-~.,.-_r~-,

6

51--~~~~~~-~

5

J--

PIN10
/'

,.~

~

~

41--~~SHTO~~~~/~I_+-~

~

PIN 10

3

I

)

DP£N

V

Output Voltage va
Pin 14 Voltage
r-;--r-T-,---r--,

,.

I--

/

4

~

3

~

2

5

SUPPLY VOlTAGE (V)

)

V

V

'/
0
0
PIN 7 VOLTAGE(V)

1

2

3

4

5

6

PIN 14 VOLTAGE (V)

TLlH/B709-3

Pin Function Description
Pin 1

Input amplifier for thermo-resistive probe with 5 nA
maximum leakage. Clamped to ground at the start of
a probe 1 measurement.

Pin 2
Pin 3

Device ground - OV.
This pin is connected to the emitter of an external
PNP transistor to supply a 200 mA constant current
to the thermo-resistive probe. An internal reference
maintains this pin at VSUPPLY - 2V.
Base connection for the external PNP transistor.

Pin 4
Pin 5

This pin is connected to the thermo-resistive probe
for short and open circuit probe detection.

Pin 6

Supply pin, + 7.5V to + 18V, protected against
+ 50V transients.
High Impedance input for second linear voltage
probe with an input range from 1V to 5V. The gain
may be set externally using pin 10.
Probe select and control input. If this pin is taken to
a logiC low level, probe 1 is selected and the timing
cycle is initiated. The selection logic is subsequently
latched low until the end of the measurement. If kept
at a low level one shot or repeating probe 1 measurements will be made depending upon pin 9 conditions. A high input level selects probe 2 except during a probe 1 measurement period.

Pin 7

Pin 8

Pin 9

Pin 10 A resistor may be connected to ground to vary the
gain of the probe 2 input amplifier. Nominal gain
when open circuit is 1.2 and when shorted to ground
3.4. DC conditions may be adjusted by means of a
resistor divider network to VREG and ground.
Pin 11 Regulated voltage output. Requires to be connected
to pin 15 to complete the supply regulator control
loop.
Pin 12 The capacitor connected from this pin to ground
sets the timing cycle for probe 1 measurements.
Pin 13 The resistor connected between this pin and ground
defines the charging current at pin 12. Typically 12k,
the value should be within the range 3k to 15k.
Pin 14 A low leakage capacitor, typical value 0.1 JAoF and
not greater than 0.47 ",F, should be connected from
this pin to the regulated supply at pin 11 to act as a
memory capaCitor for the probe 1 measurement.
The internal leakage at this pin is 2 nA max for a
long memory retention time.
Pin 15 Feedback input for the internal supply regulator, normally connected to VREG at pin 11. A resistor may
be connected in series to adjust the regulated output
voltage by an amount corresponding to the 1 mA
current into pin 15.
Pin 16 Linear voltage output for probe 1 and probe 2 capable of driving up to ± 10 mAo May be connected with
a 6000 meter to VREG.

The repeat oscillator timing capaCitor is connected
from this pin to ground. A 2 ",A current charges up
the capaCitor towards 4.3V when the probe 1 measurement cycle is restarted. If this pin is grounded
the repeat oscillator is disabled and only one probe
1 measurement will be made when pin 8 goes low.
7-13

•

Application Notes
THERMO-RESISTIVE PROBES - OPERATION AND
CONSTRUCTION
These probes work on the principle that when power is dissipated within the probe, the rise in probe temperature is
dependent on the thermal resistance of the surrounding material and as air and other gases are much less efficient
conductors of heat than liquids such as water and oil it is
possible to obtain a measurement of the depth of immersion
of such a probe In a liquid medium. This principle Is illustrated in Figuf'8 1.

R=8402SOC
1-200nIA

6

mm

4 LESS
DEEP

2

mm
DEEPER

0.0

.OS

'.0

1.5

2.0

nME (SEC0t405)
TL/H/8709-5

FIGURE 2
current with very fine wires to avoid excessive heating and
this current may be optimized to suit a particular type of
wire. The temperature changes involved will give rise to noticeable length changes in the wire used and more sophisticated holders with tensioning devices may be devised to
allow for this.

RllfAIR ..... AT,
--AR 1--AV1

-:-:-:-:.\. -:-:-:-:-:-:.: :.: :.: :.: :.:.:. RmOlL ..... ATz

.:

''-'-'-'-'-'- '.-.-.-.-.-.- . .- . .- . .- . .-.-.- ..... ARz ..... AV2· •

• OIL . . . . . . . . . . • . . . . . . . . . . . . . . . .

TL/H/8708-4

FIGURE 1
During the measurement period a constant current drive I is
applied to the probe and the voltage across the probe Is
sampled both at the start and just before the end of the
measurement period to give I:J. V. RTH Air and RTH Oil represent the different thermal resistances from probe to ambient
in air or oil giving rise fo temperature changes I:J.T, and I:J.T2
respectively. As a result of these temperature changes the
probe resistance will change by I:J.R, or I:J.R2 and give corresponding voltage changes I:J.V, or I:J.V2 per unit length.
Hence
LA
(L - LA>
I:J.V = 'LI:J.V, + --L-I:J.V2

nME (SECON05)
TLlH/8708-6

FIGURE 3
Probes need not be limited to resistance wire types as any
device with a positive temperature coefficient and sufficiently low thermal resistance to the encapsulation so as not to
mask the change due to the different surrounding mediums,
could be used. Positive temperature coefficient thermistors
are a possibility and while their thermal time constant is likely to ,be longer, than wire the measurement time may be
increased by changing Or to suit.

arid for I:J.V, > I:J.V2, RTH Air> RTH Oil, I:J.V will increase as
the probe length in air Increases. For best results the probe
needs to have a high temperature coefficient and low thermal time constant. One way to achieve this is to make use
of resistance wires held in a suitable support frame allowing
free liquid access. Nickel cobalt iron alloy resistance wires
are available with resistivity 50 Jl-Ocm and 3300 ppm temperature coefficient which when made up into a probe with 4
x 2 cm 0.08 mm diameter strands between supports (10
cm total) can give the voltage vs time curve shown in Figuf'8
2 for 200 mA probe current. The effect of varying the probe
current is shown in Figuf'8 3. To avoid triggering the probe
failure detection circuits the probe voltage must be 'between
0.7V and 5.3V (VREG - 6V), hence for 200 mA the permissible probe resistance range is from 3.50 to 240. The example given has a resistance at room temperature of 90
which leaves plenty of room for increase during measurements and changes in ambient temperature.
Various arrangements of probe wire are possible for any
given wire gauge and probe current to suit the measurement
range required, some examples are illustrated schematically
in Figuf'8 4. Naturally it is necessary to reduce the probe

USEFUL

RANGE
OF
PROSE

o.g.
16cm

TL/H/8709-7

FIGURE 4
7-14

Application Notes (Continued)
CIRCUIT OPERATION
1) Thermo-Resistive Probes

4.3V

These probes require measurements to be made of their
resistance before and after power has been dissipated in
them. With a probe connected as probe 1 in the connection
diagram the LM1042 will start a measurement when pin 8 is
taken to a logic low level (VS < 0.5Y) and the internal timebase ramp generator will start to generate the waveform
shown in Figure 5. At 0.7V, Tl, the probe current drive is
switched on supplying a constant 200 mA via the external
PNP transistor and the probe failure circuit is enabled. At 1V
pin 1 is unclamped and Cl stores the probe voltage corresponding to this time, T2. The ramp charge rate is now reduced as CT charges toward 4V. As the 4.1V threshold is
passed a current sink is enabled and CT now discharges.
Between 1.3V and 1.0V, T 3 and T4, the amplified pin 1 voltage, representing the change in probe voltage since T2 (and
as the current is constant this is proportional to the resistance change) is gated onto the memory capacitor at pin 14.
At 0.7V, Ts, the probe current is switched off and the measurement cycle is complete. In the event of a faulty probe
being detected the memory capacitor is connected to the
regulated supply during the gate period. The device leakage
at pin 14 is a maximum of 2 nA to give a long memory
retention time. The voltage present on pin 14 is amplifed by
1.2 to drive pin 16 with a low impedance, ± 10 mA capability, between 0.5V and 4.7V. A new measurement can only be
started by taking pin 8 to a low level again or by means of
the repeat oscillator.

Vg

1.DV

TL/H/B709-9

FIGURE 6
BO

e...

60

:::IE

1=

~
~

./

40

/

20

/

V

V

/
o

o

30

BO

BO

100

120

CRV.F)
TLlH/B709-10

FIGURE 7
3) Second Probe Input

4V

A high impedance input for an alternative sensor is available
at pin 7. The voltage applied to this input is amplified and
output at pin 16 when the input is selected with a high level
on pin 8. The gain is defined by the feedback arrangement
shown in Figure 8 with adjustment possible at pin 10. With
pin 10 open the gain is set at a nominal value of 1.2, and
this may be increased by connecting a resistor between pin
10 and ground up to a maximum of 3.4 with pin 10 directly
grounded. A variable resistor may be used to calibrate for
the variations in sensitivity of the sensor used for probe 2.

lV
OV

'I

-.I,I:

,II
PROBE CURRENT

: SECOND MEASUREMENT GATE PULSE

Il

::L'
II

I

PIN 16

FIRST MEASUREMENT CLAMP
TUH/B709-B

FIGURES
2) Repetitive Measurement
With a capacitor connected between pin 9 and ground the
repeat oscillator will run with a waveform as shown in Figure
6 and a thermo-resistive probe measurement will be triggered each time pin 9 reaches a threshold of 4.3V, provided
pin 8 is at a logic low level. The repeat oscillator runs independently of the pin 8 control logic.
As the repetition rate is increased localized heating of the
probe and liquid being measured will be the main consideration in determining the minimum acceptable measurement
intervals. Measurements will tend to become more dependent on the amount of fluid movement changing the rate of
heat transfer away from the probe. The typical repeat time
versus timing capacitor value is shown in Figure 7.

TL/H/B709-11

FIGURES
POWER SUPPLY REGULATOR
The arrangement of the feedback for the supply regulator is
shown in Figure 9. The circuit acts to maintain pin 15 at a
constant 6V and when directly connected to pin 11 the regulated output is held at 6V. If required a resistor R may be
connected between pins 15 and 11 to increase the output
voltage by an amount corresponding typically to 1 mA flowing in R. In this way a variable resistor may be used to trim
out the production tolerance of the regulator by adjusting for
VREG ~ 6.2V.
7-15

•

Application Notes (Continued)

-.------.

.---------------

I

I

6

•I
I
I
I
I
I

I

:

I

4.5 k4

I
I

I
I

._--------------

TL/H/8709-12

FIGURE 9

------_ ..
I

PROBE CURRENT REFERENCE CIRCUIT
The circuit defining the probe circuit is given in Figure 10. A
reference voltage is obtained from a bandgap regulator derived current flowing in a diode resistor chain to set up a
voltage 2 volts below the supply. This is applied to an amplifier driving an external PNP transistor to maintain pin 3 at 2V
below supply. The emitter resistance from pin 3 to supply
defines the current which, less the base current, flows in the
probe. Because of the sensitivity of the measurement to
probe current evident in Figure 3 the current should be adjusted by means of a variable resistor to the desired value.
This adjustment may also be used to take out probe tolerances.

TL/H/8709-13

FIGURE 10
TYPICAL APPLICATIONS CIRCUIT
A typical automotive application circuit is shown in Figure 11
where the probe selection signal is obtained from the oil
pressure switch. At power up (ignition on) the oil pressure
switch is closed and pin 8 is held low by R4 causing a probe
1 (011 level) measurement to be made. Once the engine has
started the oil pressure switch opens and 01 pulls pin 8 high
changing over to the second auxiliary probe input The capaCitor Cs holds pin 8 high in the event of a stalled engine
so that a second probe 1 measurement can not occur in
disturbed oil. Non-automotive applications may drive pin 8
directly with a logic signal.

TLlH/8709-14

FIGURE 11. Typical Application Circuit

7-16

~National

~ Semiconductor

LM 1815 Adaptive Sense Amplifier
General Description

Features

The LM1815 is an adaptive sense amplifier and default gating circuit for motor control applications. The sense amplifier provides a one-shot pulse output whose leading edge
coincides with the negative-going zero crossing of a ground
referenced input signal such as from a variable reluctance
magnetic pick-up coil.

•
•
•
•
•
•

In normal operation, this timing reference signal is processed (delayed) externally and returned to the LM1815. A logic
input is then able to select either the timing reference or the
processed signal for transmission to the output driver stage.
The adaptive sense amplifier operates with a positive-going
threshold which is derived by peak detecting the incoming
signal and dividing this down. Thus the input hysteresis varies with input signal amplitude. This enables the circuit to
sense in situations where the high speed noise is greater
than the low speed signal amplitude. Minimum input signal
is 100 mVp-p.

Connection Diagram

Adaptive hysteresis
Single supply operation
Ground referenced input
True zero crossing timing reference
Operates from 2V to 12V supply voltage
Handles inputs from 100 mV to over 120V with external
resistor
• CMOS compatible logic

Applications
•
•
•
•
•

Truth Table

Dual-In-Line Package
RC
TIMING

NC

NC

GND

Position senSing with notched wheels
Zero crossing switch
Motor speed control
Tachometer
Engine testing

REFERENCE
PULSE OUT

INPUT
SELECT

GATED
OUTPUT

SIGNAL
INPUT

NC

THRESHOLD
ADJUST

TIMING
PULSE
INPUT

NC

v'

Signal
Input

Input
Select

Timing
Input

Gated
Output

Pulses

L

X

Pulses

X

H

Pulses

Pulses

PEAK
DETECTOR
CAPACITOR
TL/H17893-1

•

Top View
Order Number LM1815N
See NS Package Number N14A

7-17

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Supply Voltage
12V
Power Dissipation (Note 1)
1250mW
Operating Temperature Range
-40"Cto + 125'C

Storage Temperature Range
Junction Temperature (Note 2)
Input Current
Lead Temperature (Soldering, 10 sec.)

-65'Cto

+ 150"C
+ 125'C
±30mA
260"C

Electrical Characteristics (TA = 25'C, Vee = 10V, unless otherwise specified, see F/{/ure 1)
Parameter

Conditions

Operating Supply Voltage
Supply Current

fiN = 500 Hz, Pin 9
Pin 11 = 0.8V

Reference Pulse Width

fiN

Min

Typ

Max

Units

2.5

10

12

V

3.6

6

mA

100

130

/Ls

5

p.A

28

kO

25

mV

2.0

V

= 2V,
70

Zero Crossing Threshold

= 1 Hz to 2 kHz
VIN = 2V, (Pin 9 and Pin 11)
VIN = OV dc, (Pin 3)
VIN = 5 Vrms, (Note 3)
VIN = 100 mVp-p, (Pin 3)

Logic Threshold

(Pin 9 and Pin 11)

0.8

1.1

VOUTHigh

7.5

8.6

VOUTLow

= 1 kO, (Pin 10)
ISINK = 0.1 mA, (Pin 10)

Input Arming Threshold

Pin 5 Open, VIN

S;

135 mVp-p

Pin 5 Open, VIN

~

230 mVp-p

Input Bias Current
Input Bias Current
Input Impedance

Output Leakage Pin 12

200
12

RL

20

nA

V

0.3

0.4

V

30

45

60

mV

40

80

90

% OfV3 Pk

Pin5toV+

200

Pin5toGnd

-25

mV

= llV
112 = 2mA

0.D1

V12

25

mV

10

/LA

0.4,
Saturation Voltage P12
0.2
V
Note 1: For operation at elevated temperatures, the device must be derated besed on a 125'C maximum iunction temperature and a thermal resistance of fJlY'C/W
iunction to ambient
Note 2: Temporary excursions to 150'C can be tolerated.
Note 3: Measured at Input to extemal 18 kll resistor. IC contains 1 kll in series with a diode to attenuate the input signa/,
REFERENCE
PULSE OUT

v'
I=O.673RC R
OJlOl,.rr-

-

INPUT
SELECT

...lEO

OUTPUT

lIMING
PULSE
INPUT

Q

L

150kn
14

"3

~
O1t:~O

"

S.6kA
12

\-=

IknI
11

10

8

9

41

-=

LN1815

~
...

11

-=

*

IS

I'

3
t8kA

V'N9

=-

~

16

7 1.61U1

~
~~
DETEC10II -

CAPAaTOR

FIGURE 1. LM1815 Adaptive Sense Amplifier

7-18

TUH/7893-2

~----------------------------------------------~~

....

Schematic Diagram

co
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ill

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5iIi!

a
0-

Gil!

.....::::r

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:a

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t:r

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aid!

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r.yi'-

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TLlHf7893-4

7·19

•

....co ,-----------------------------------------------------------------------------,
~

...

,

INPUT

:!i

THR£SHOlD

VOlTAGE

TL/HI7893-3

FIGURE 2. LM1815 Oscillogram.

Application Hints
idly as the input Signal amplitude increases, and decays by
virtue of the resistor connected externally at pin 7 to track
decreases in the input signal.
Note that since the input is clamped, the waveform observed at pin 3 is not identical to the waveform observed at
the variable reluctance sensor. Similarly, the voltage stored
at pin 7 is not identical to the peak voltage appearing at
pin 3.
MODE 2, Pin 5 connected to V +. The input arming threshold is fixed at 200 mV minimum when pin 5 is connected to
the positive supply. The chip has no output for signals of
less than 200 mV peak, and triggers on the next negativegoing zero crossing when the threshold is exceeded.

Input Clamp
The signal input at pin 3 is internally clamped. Current limit
is provided by an external resistor which should be selected
to allow a peak current of 3 rnA in normal operation. Positive
inputs are clamped by a 1 kG resistor and series diode,
while an active clamp limits pin 3 to -350 mV for negative
inputs (sas R4, 012, 011 in internal schematic diagram).
Operation of Zero Crossing Detector
The LM1815 is designed to operate as a zero crossing detector, triggering an internal one shot on the negative-going
edge of the input signal. Unlike other zero crossing detectors, the LM1815 cannot be triggered until the input signal
has crossed an "arming" threshold on the positive-going
portion of the waveform. The arming circuit is reset when
the chip is triggered, and subsequent zero crossings are
ignored until the arming threshold is exceeded again. This
threshold varies depending on the connection at pin 5.
Thras different modes of operation are possible:
MODE 1, Pin 5 open. The adaptive mode is selected by
leaving pin 5 open circuit. For input signals of less than
135 mVp-p, the input arming threshold is typically 45 mY.
Under these conditions the input signal must first cross the
45 mV threshold in the positive direction to arm the zero
crOSSing detector, and then cross zero in the negative direction to trigger it If the signal is less than 30 mV peak (minimum rating in Electrical Characteristics), the one shot is
guaranteed to not trigger.
Input Signals of greater than 230 mVp-p cause the arming
threshold to track at 80% of the peak input voltage. A peak
detector (pin 7) stores a value relative to the positive input
peaks to establish the arming threshold. Input signals must
excesd this threshold in the positive direction to arm the
zero crossing detector, which can then be triggered by a
negative-going zero crossing. The peak detector tracks rap-

MODE 3, Pin 5 grounded. With pin 5 grounded, the input
arming threshold is set to OV (±25 mV maximum). Positivegoing zero crossings arm the chip, and the next negative
zero crossing triggers it.
The one shot timing is set by a resistor and capaCitor connected to pin 14. The output pulse width is
pulse width = 0.673 RC

(1)

In some systems it is necessary to externally generate pulses, such as during stall conditions when the variable reluctance sensor has no output. External pulse inputs at pin 9
are gated through to pin 10 when Input Select (pin 11) is
pulled high. Pin 12 is a direct output for the one shot and is
unaffected by the status of pin 11.
Input/output pins 9,11,10 and 12 are all CMOS logic compatible. In addition, pins 9, 11 and 12 are TIL compatible.
Pin 10 is not guaranteed to drive a TIL load.
Pins 1, 4, 6 and 13 have no internal connections and can be
grounded.

7-20

Ii:....

~National

CD
....

~ semiconductor

to

LM 1819 Air-Core Meter Driver
General Description

Features

The LM1819 is a function generator/driver for air-core
(moving-magnet) meter movements. A Norton amplifier and
an NPN transistor are included on chip for signal conditioning as required. Driver outputs are self-centering and develop ±4.5V swing at 20 mAo Better than 2% linearity is guaranteed over a full 305-degree operating range.

•
•
•
•

Self-centering 20 mA outputs
12V operation
Norton amplifier
Function generator

Applications
• Air-core meter driver
• Tachometers
• Ruggedized instruments

Typical Application
VaAT=14.4V

SIGNAL

FROM
POINTS

D4
lN4OO1

R5
3.311

R7
3.3k

-IN--."",_---_-Wl....,

02
2N4746t

lBY

Rl
Uk

1.

R2··
330k

&1'

10nF

MOVING MAGNET METERt.
TLlH/5263-1

FIGURE 1. Automotive Tachometer Application. Circuit shown operates
with 4 cylinder engine and deflects meter pOinter (270") at 6000 RPM.

Order Number LM1819N
See NS Package Number N14A
'TRW Type X463UW Polycarbonate Capacitor
"RN60D Low TC Resistor (±100 ppm)
tComponents Required for Automotive Load Dump Protection
tt Available from FARIA Co.
POBox 983, Uncasville, CT 06382
Tel. 203-848-9271

7-21

II

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications•.
Supply Voltage, V+ (pin 13)
20V
Power Dissipation (note 1)
1300 mW

Operating Temperature
Storage Temperature
Lead Temp. (Soldering, 10 seconds)

- 40'C to + 85'C
- 65'C to -150'C
260'C
20VMIN

BVCEO

Electrical Characteristics Vs = 13.1V TA = 25'C unless otherwise specified
Symbol
Is
VREG

VREF

hFE

Pln(s)

Conditions

Supply Current

13

Zero Input Frequency
(See Figure 1)

Regulator Voltage

11

IREG = OmA

Regulator Output Resistance

11

IREG = 0 mA to 3 mA

Reference Voltage

4

IREF = OmA

Reference Output Resistance

4

IREF = 0 ",A to 50 ",A

Parameter

Norton Amplifier Mirror Gain

5,6

NPN Transistor DC Gain

9,10

Function Generator Feedback
Bias Current
Drive Voltage Extremes,
Sine and Cosine
Sine Output Voltage
with Zero Input

k

1
2,12
2

Min

Typ

8.5

8.1

Units

65

mA

8.9

V

13.5
1.9

0

2.1

2.3

V

5.3
0.9

IBIAS '" 20 ",A

Max

kO

1.0

1.1

125
V1 = 5.1V
ILOAD = 20mA
Va = VREF

Function Generator Linearity

FSD = 305'

Function Generator Gain

Meter Deflection//).Va

1.0

mA

±4

±4.5

V

-350

0

+350

mV

±1.7

%FSD

50.75

53.75

56.75

'IV

1: For operation above 25'C. the LM1819 must be derated based upon a t25'C maximum iunction temperature and a thermal resistance of 76'C/W which
applies lor the device soldered in a printed circuH board and operating in a still-air ambient.
Note

Application Hints
H fields (Figure 3(c)). H is proportional to the voltage applied
to a coil. Therefore, by varying both the polarity and magni·
tude of the coil voltages the axle assembly can be made to
rotate a full 360'. The LM1819 is designed to drive the meter through a minimum of 305'.

AIR-CORE METER MOVEMENTS
Air·core meters are often favored over other movements as
a result of their mechanical ruggedness and their independence of calibration with age. A simplified diagram of an air·
core meter is shown in Figure 2. There are three basic
pieces: a magnet and pOinter attached to a freely rotating
axle, and two coils, each oriented at a right angle with reo
spect to the other. The only moving part in this meter is the
axle assembly. The magnet will tend to align itself with the
vector sum of H fields of each coil, where H is the magnetic
field strength vector. If, for instance, a current passes
through the cosine coil (the reason for this nomenclature
will become apparent later) as shown in Figure 3(a), the
magnet will align its magnetic axis with the coil's H field.
Similarly, a current in the sine coil (Figure 3(b)) causes the
magnet to align itself with the sine H field. If currents are
applied simultaneously to both sine and cosine coils, the
magnet will turn to the direction of the vector sum of the two

--

POINTER """'ItIIi:

~rr
MAONET"1

~AXLE

))

~ I)

..00000 COSINE

I~

COIL

ocx: SINE COIL

~

TLfHf5263-2

FIGURE 2. Simplified Diagram of an Air Core Meter.

7·22

,-----------------------------------------------------------------------------, r

a:::
......

Application Hints (Continued)

co
CD

E€~~~~~~ SINE
COIL

COSINE
COIL

COSINE
COIL

COSINE
COIL
TUH/5263-S

w
~
~
FIGURE 3. Magnet and pointer position are controlled by the H field generated by the two drive colis.
In an air-core meter the axle assembly is supported by two
nylon bushings. The torque exerted on the pointer is much
greater than that found in a typical d' Arsonval movement. In
contrast to a d'Arsonval movement, where calibration is a
function of spring and magnet characteristics, air-core meter calibration is only affected by the mechanical alignment
of the drive coils. Mechanical calibration, once set at manufacture, can not change.

Comparing [3) to [2) we see that if HSINE varies as the sine
of 8, and HCOSINE varies as the cosine of 8, we will generate a net H field whose direction is the same as 8. And since
the axle assembly aligns itself with the net H field, the pointer will always point in the direction of 6.
THELM1819
Included in the LM1819 is a function generator whose two
outputs are designed to vary approximately as the sine and
cosine of an input. A minimum drive of ±20 mA at ±4V is
available at pins 2 (sine) and 12 (cosine). The common side
of each coil is returned to a 5.1 V zener diode reference and
fed back to pin 1.
For the function generator, k '"' 54°tv (in equation 1). The
input (pin 8) is internally connected to the Norton amplifier's
output. VIN as considered in equation [1) is actually the difference of the voltages at pins 8 (Norton outputlfunction
generator input) and 4. Typically the reference voltage at pin
4 is 2.1V. Therefore,

Making pOinter position a linear function of some input is a
matter of properly ratioing the drive to each coil. The H field
contributed by each coil is a function of the applied current,
and the current is a function of the coil voltage. Our desired
result is to have 8 (pointer deflection, measured in degrees)
proportional to an input voltage:
8=kVIN

[1)

where k is a constant of proportionality, with units of degrees/volt. The vector sum of each coils' H field must follow
the deflection angle 8. We know that the axle assembly
always pOints in the direction of the vector sum of HSINE
and HCOSINE. This direction (see Figure 4) is found from the
formula:
(8) = arctan ( I HSINE 1/1 HCOSINE
Recalling some basic trigonometry,
(8) = arctan(sin (8) / cos(8

II

»

HCOSINI!+HSINE

8=k(Va-VREF) = 54 (Va-2.1)

[4)

As Va varies from 2.1V to 7.75V, the function generator will
drive the meter through the chip's rated 3050 range.
Air-core meters are mechanically zeroed during manufacture such that when only the cosine coil is driven, the pointer indicates zero degrees deflection. However, in some applications a slight trim or offset may be required. This is
accomplished by sourcing or sinking a DC current of a few
microamperes at pin 4.
A Norton amplifier is available for conditioning various input
signals and driving the function generator. A Norton amplifier was chosen since it makes a Simple frequency to voltage
converter. While the non-inverting input (pin 6) bias is at one
diode drop above ground, the inverting input (5) is at 2.1 V,
equal to the pin 4 reference. Mirror gain remains essentially
flat to IMIRROR = 5 mA. The Norton amplifier's output (8) is
designed to source current into its load. To bypass the Norton amplifier simply ground the non-inverting input, tie the
inverting input to the reference, and drive pin 8 (Norton output/function generator input) directly.

[2)

[3)

HSINE

HCOSINE . - - - -........- -...

An NPN transistor is included on chip for buffering and
squaring input signals. Its usefulness is exemplified in Figures 1 & 6 where an ignition pulse is converted to a rectangular waveform by an RC network and the transistor. The
emitter is internally connected to ground. It is important not
to allow the base to drop below - 5Vdc, as damage may
occur. The 2.1V reference previously described is derived
from an 8.5V regulator at pin 11. Pin 11 is used as a stable
supply for collector loads, and currents of up to 5 mA are
easily accommodated.

TL/H/526S-4

FIGURE 4. The vector sum of HCOSINE and HSINE points
In a direction 6 measured in a clockwise direction from
HCOSINE'

7-23

fI

,...
CD
,...
~
~

r-----------------------------------------------------------------------------,
Application Hints (Continued)
TACHOMETER APPLICATION
The charge pump circuit in Figure 7 can be operated in two
modes: constant input pulse width (C1 acts as a coupling
capacitor) and constant input duty cycle (C1 acts as a differentiating capacitor). The transfer functions for these two
modes are quite diverse. However, deflection is always directly proportional to R2 and ripple is proportional to C2.

A measure of the operating level of any motor or engine is
the rotational velocity of its output shaft. In the case of an
automotive engine the crankshaft speed is measured using
the units "revolutions per minute" (RPM). It is possible to
indirectly measure the speed of the crankshaft by using the
signal present on the engine's ignition coil. The fundamental
frequency of this signal is a function of engine speed and
the number of cylinders and is calculated (for a four-stroke
engine) from the formula:
j=nCll/120

(Hz)

The following variables are used in the calculation of meter
deflection:

(5)

where n = number of cylinders, and CIl = rotational velocity of
the crankshaft in RPM. From this formula the maximum frequency normally expected (for an 8 cylinder engine turning
4500RPM) is 300 Hz. In certain specialized ignition systems
(motorcycles and some automobiles) where the coil waveform is operated at twice this frequency if = CIl/60). These
systems are identified by the fact that multiple coils are used
in lieu of a single coil and distributor. Also, the coils have
two outputs instead of one.

symbol

description

n

number of cylinders

CIl, CIlIDLE engine speed at red line and idle, RPM
8
pointer deflection at redline, degrees
1:1

charge pump input pulse width, seconds

VIN

peak to peak input voltages, volts

t.8

maximum desired ripple, degrees

k

function generator gain, degrees/volt

j, jlDLE

input frequency at redline and idle, Hz

Where the NPN transistor and regulator are used to create a
pulse VIN=8.5V. Acceptable ripple ranges from 3 to 10 degrees (a typical pointer is about 3 degrees wide) depending
on meter damping and the input frequency.

A typical automotive tachometer application is shown in Figure 1. The coil waveform is filtered, squared and limited by
the RC network and NPN transistor. The frequency of the
pulse train at pin 9 is converted to a proportional voltage by
the Norton amplifier's charge pump configuration. The ignition circuit shown in Figure 5 is typical of automotive systems. The switching element "S" is opened and closed in
synchronism with engine rotation. When "S" is closed, energy is stored in Lp. When opened, the current in Lp diverts
from "S" into C. The high voltage produced in Ls when "S"
is opened is responsible for the arcing at the spark plug.
The coil voltage (see Figure 6) can be used as an input to
the LM1819 tachometer circuit. This waveform is essentially
constant duty cycle. 04 rectifies this waveform thereby preventing negative voltages from reaching the chip. C4 and
R5 form a low pass filter which attenuates the high frequency ringing, and R7 limits the input current to about 2.5mA.
R6 acts as a base bleed to shut the transistor OFF when
"S" is closed. The collector is pulled up to the internal regulator by RREG. The output at pin 9 is a clean rectangular
pulse.

The constant pulse width circuit is designed using the following equations:
(1)

100 ",A <

(2)

C1~ 101:1

~~<3 mA

R1

R2=~ = 120R1 8
VINl:lkj

(3)

VINnClll:lk

1
1
R2t.8hOLE R2t.8nCllIDLE
The constant duty cycle equations are as follows:
(4)

C2=

RREG ~ 3 kO
R1 :s; VINx1()4 -RREG
C1 :s; Sl10(RREG+R1)
Rz = 8/3.54nCllC1 = 8/425jC1
C2 = 425C1/t.8

Many ignition systems use magnetic, hall effect or optical
sensors to trigger a solid state switching element at "S."
These systems (see the LM1815) typically generate pulses
of constant width and amplitude' suitable for driving the
'
charge pump directly.

The values in Figure 1 were calculated with n = 4,
CIl = 6000RPM, 8 = 270 degrees, 1:1 = 1 ms, VIN is
VREG-0.7V, and t.8=3 degrees in the constant duty cycle
mode. For distributorless ignitions these same equations will
apply if CIl/60 is substituted for j.

7-24

~--------------------------------------------------~r

....

i:

Equivalent Schematic

CD
....
CD

~-+--~ ~--~~-+~~~~----.----r{j.

o

i

,.
7-25

m
..- ,-----------------------------------------------------------------------------,
Typical Applications

co
..-

~

11

REG

RHEB
OUTPUT

SPARK

TO CHAR8£
I'IIMP

PWG
D4

R7

RS

C4

LM1819

10

R&
7,14

TLlH/5263-9

FIGURE 5. Typical Pulse-Squarlng Circuit for
Automotive Tachometers.

OPENED

"s"

CLOSED

CZ

COIL
WAVEfORM

___""r

DUTPUT ~ 8.SV - - ,
CHARGE I'IIMP ov
- - _...

TL/H/5263-11

TLlHI5263-10

FIGURE 6. Waveforms Encountered In Automotive
Tachometer Circuit.

FIGURE 7. Tachometer Charge Pump.

Voltage Driven Meter with Norton Amplifier Buffer

v+ =13.1V

Rz

lZ0
lW

RZ"
130K

CDSINE

Rl
lOOk

VlN
TL/H/5263-5

Deflection = 54 {VIN-.7)R2/Rl

(degrees)

o to 305' deflection is obtained with. 7 to 5V input
'Full scale deflection is adjusted by trimming R2.

7-26

Typical Applications (Continued)
Unbuffered Voltage Driven Meter

v+ =13.1V

ftz
120

lW
COSINE

TL/H/5263-6

Deflection = 54(VIN - 2.1)

o to 305

0

(degrees)

deflection is obtained for inputs of 2.1 to 7.75V.

Full scale deflection is adjusted by trimming the input voRage.

Current Driven Meter

v+ =13.1V

ftz
120

ft2"
50k

lW
COSINE

TL/H/5263-7

Deflection = 54R211N

(degrees)

Inputs of 0 to 100 p.A deflect the meter 0 to 27fY'.
'Full scale deflection is adjusted by trimming R2.

7·27

~ .---------------------------------------------------------------------------~

----co
~

Typical Applications (Continued)
Level Shifted Voltate Driven Meter

v· =13.1V

HZ

120
1W

COSINE

1M

1M

1M

TL/H/5263-8
Deflection = 54VIN

(degrees)

Inputs of 0 to 5.65V deflect the meter through a range of 0 to 305'.
Full scale deflection is adjusted by trimming the Input voltage.

7-28

,-------------------------------------------------------------------------,

~National

~

....

ill:

i

~ Semiconductor

LM 1830 Fluid Detector
General Description

Features

The LM1830 is a monolithic bipolar integrated circuit designed for use in fluid detection systems. The circuit is ideal
for detecting the presence, absence, or level of water, or
other polar liquids. An AC signal is passed through two
probes within the fluid. A detector determines the presence
or absence of the fluid by comparing the resistance of the
fluid between the probes with the resistance intemal to the
integrated circuit. An AC signal is used to overcome plating
problems incurred by using a DC source. A pin is available
for connecting an external resistance in cases where the
fluid impedance is of a different magnitude than that of the
internal resistor. When the probe resistance increases
above the preset value, the oscillator signal is coupled to
the base of the open-collector output transistor. In a typical
application, the output could be used to drive a LED, loud
speaker or a low current relay.

•
•
•
•
•
•

Low external parts count
Wide supply operating range
One side of probe input can be grounded
AC coupling to probe to prevent plating
Internally regulated supply
AC or DC output

Applications
•
•
•
•
•

Beverage dispensers
Water softeners
Irrigation
Sump pumps
Aquaria

•
•
•
•

Radiators
Washing machines
Reservoirs
Boilers

Logic and Connection Diagram
Dual-In-Line Package
Vee

OSCILLATOR
OUTPUT
IRREFI OUTPUT

OSCILLATOR
CAlAClTOR

Me

Ie

•••

Ie

DETECTOR FILTER
INPUT
CAP

DSCILLATaR
OUTPUT

Ife

Ie

DICILLATGR

,.,VlEW

CAPACITOR

TL/H/5700-1

Order Number LM1830N
See NS Package Number N14A

•
7-29

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
28V
Power Dissipation (Note 1)
1400mW

20mA

Output Sink Current
Operating Temperature Range

-40"Cto +85'C
-40'Cto + 150"C

Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

260"C

Electrical Characteristics (V+ = 16V, TA= 25'C unless otherwise specified)
Typ

Max

Units

Supply Current

Min

5.5

10

mA

Oscillator Output Voltage
Low
High

1.1
4.2

Conditions

Parameter

Intemal Reference Resistor
D.etector Threshold Voltage
Detector Threshold Resistance

8

V
V

13
680
10

5

25
15

kO
mV
kO

V
lo=10mA
0.5
2.0
p.A
10
VPIN12=16V
4
7
12
kHz
C1 = 0.00 1p.F
Note 1: The maximum junction temperature rating of the LM1830N is 15O'C. For operation at elevated temperatures, devices In the dual·ln·llne plastic peckage
Output Saturation Voltage
Output Leakage
Oscillator Frequency

must be derated based on a thermal resistance of 89"C/W.

Schematic Diagram
OSCILLATOR
OUTPUT

VCC
14

10k

OSCILLATOR
OUTPUT
(RREFI
13

I

~

OPTIONAL
OETECTOR FILTER
INPUT CAPACITOR

~

12

13k
10k

9.8k
25k

7V';j

OUTPUT

•

10

......1

~

3Dk

I

CI

~Lt:

~

~IOk

~.

;~

)

.t

~

25k

7

CI

GNO

7·30

TLlH/5700-2

r-----------------------------------------------------------------------------'r

....

i:

Typical Performance Characteristics
Normalized Oscillator Frequency
vs Supply Voltage
ii 1.15
:!!

t~

25
TA=25°C

~
t

..
~
..
~.

1.1

a

~ 1.05

a:

I'

~

i

=:"

ii

~

9

r-

0.95

20

i

15
10

10 I--+-+--+-+----j~:-I

~
:1

\

.a

a;

ii

D.9

o

10

11

21

25

•o

30

10

SUPPLY VOLTAGE (V)

16

--

14

.".

12

I.

~

.......

30

25

10

I-""

."..

15

20

25

30

SUPPLY VOLTAGE (V)

VCC=IIV-

r-.

.,. .......

"

20

Detector Threshold Voltage
vs Temperature
I

w

16

SUPPLY VOLTAGE (V)

11

a:

r--r-,....-,r--r-..--,

12
TA-25°C

Reference Resistor vs Ambient
Temperature

i

~

I-

20

g

Power Supply Current vs
Supply Voltage

Threshold Resistance vs Supply
Voltage

-

Probe Threshold Resistance
vs Temperature

g

13

~

12

:=

Vee -IIV

\.
i'-....

~ "

.........

a:

~

I

,

.......

"

r--.

::I

E

I

-40 -21

0

2D

4D

10

10

101

21

AMllENT TEMPERATURE rc)

..
w

co
~

..
..
~
."
c

a:

VOL

20

4D

ID

10 IDB

TEMPERATURE rc)

II

..

12

!
S

80

10

lDO

0.1

..~

lDO

OUTPUT CURRENT (PIN 12) (mA)

vric"iv-

II
14
10

a:

10

40

20

.,..
:Ii

!;
==

o

28

Oscillator Frequency vs
Ambient Temperature

•t

I;

........

0

AMBIENT TEMPERATURE (OC)

~
~

~
e
I-

-40 -21

7
-41 -20

II 100

Output Saturation Voltage vs
Output Current

VCC -IIV

VOH

10

AMBIENTTEMPERATURE rc)

Oscillator VOH and VOL
vs Ambient Temperature

I

4D

I

I

1'==00

o

-41 -20

•

20

4D

BO

10

100

AMIIENT TEMPERATURE rc)

Equivalent Resistance vs
Concentration of Several
Solutions

.....
.......
t

~

15~
"w

151

..'"',

~s

iii

,.

5DO

4i0

4DO
380
3110

~

~04

250

20D
110

-

JCI

.,Ac

lDO
50

o

I

O.DOI

0.01

"'"

0.1

CONCENTRATION (GRAM MOLECULAR
EQUIVALENTS/LITRE)
TLlH/5700-3

7-31

Application Hints
The LM1830 requires only an external capacitor to complete the oscillator circuit. The frequency of oscillation is
inversely proportional to the external capacitor value. Using
0.001 p.F capacitor, the output frequency is approximately 6
kHz. The output from the oscillator is available at pin 5. In
normal applications, the output is taken from pin 13 so that
the internal 13k resistor can be used to compare with the
probe resistance. Pin 13 is coupled to the probe by a blocking capacitor so that there is no net dc on the probe.

It is possible to calculate the resistance of any aqueous
solution of an electrolyte for different concentrations, provided the dimensions of the electrodes and their spacing is
known.
The resistance of a simple parallel plate probe Is given by:
R= 1000.~ 0
c.p A
where A = area of plates (cm2)

Since the output amplitude from the oscillator is approximately 4 VeE, the detector (which is an emitter base junction) will be turned "ON" when the probe resistance to
ground is equal to the internal 13 kO resistor. An internal
diode across the detector emitter base junction provides
symmetrical limiting of the detector input Signal so that the
probe is excited with ±2 VeE from a 13 kO source. In cases
where the 13 kO resistor is not compatible with the probe
resistance range, an external resistor may be added by coupling the probe to pin 5 through the external resistor as
shown in Figure 2. The collector of the detecting transistor
is brought out to pin 9 enabling a filter capacitor to be connected so that the output will switch "ON" or "OFF" depending on the probe resistance. If this capaCitor is omitted,
the output will be switched at approximately 50% duty cycle
when the probe resistance exceeds the reference resistance. This can be useful when an audio output is required
and the output transistor can be used to directly drive a loud
speaker. In addition, LED indicators do not require dc excitation. Therefore, the cost of a capacitor for filtering can be
saved.

d=separation of plates (cm)
c=concentration (gm. mol. equivalent/litre)
p = equivalent conductance
(0- 1 cm 2 equiv. -1)
(An equivalent is the number of moles of a substance that
gives one mole of positive charge and one mole of negative
charge. For example, one mole of NaCI gives Na + + CI- so
the equivalent is 1. One mole of CaCI2 gives Ca + + + 2CIso the equivalent is 1/2.)
Usually the probe dimensions are not measured phYSically,
but the ratio d/A is determined by measuring the resistance
of a cell of known concentration c and equivalent conductance of 1. A graph of common solutions and their equivalent
conductances is shown for reference. The data was derived
from D.A. Macinnes, "The Principles of Electrochemistry,"
Reinhold Publishing Corp., New York., 1939.
In automotive and other applications where the power
source is known to contain significant transient voltages, the
internal regulator on the LM 1830 allows protection to be
provided by the simple means of using a series resistor in
the power supply line as illustrated in Figure 4. If the output
load is required to be returned directly to the power supply
because of the high current required, it will be necessary to
provide protection for the output transistor if the voltages
are expected to exceed the data sheet limits.

In the case of inductive loads or incandescent lamp loads, it
is recommended that a filter capacitor be employed.
In a typical application where the device is employed for
sensing low water level in a tank, a simple steel probe may
be inserted in the top of the tank with the tank grounded.
Then when the water level drops below the tip of the probe,
the resistance will rise between the probe and the tank and
the alarm will be operated. This is illustrated in Figure 3. In
situations where a non-conductive container is used, the
probe may be designed in a number of ways. In some cases
a simple phono plug can be employed. Other probe designs
include conductive parallel strips on printed circuit boards.

Conductive Fluids
City water
Seawater
Copper sulphate solution
Weak acid
Weak base
Household ammonia
Water and glycol mixture
Wet soil
Coffee

Although the LM1830 is designed primarily for use in sensing conductive fluids, it can be used with any variable reSistance device, such as light dependent resistor or thermistor
or resistive pOSition transducer.
The following table lists some common fluids which may
and may not be detected by resistive probe techniques.

Non-Conductive Fluids
Pure water
Gasoline
Oil
Brake fluid
Alcohol
Ethylene glycol
Paraffin
Dry soil
Whiskey

7-32

Typical Applications Vee =

16V

Vee

Vee

1200

1200

~ LEO

.4

'.m,.F

~ LEO

12

Vee

a.a",F

FIGURE 2. Application Using External
Reference Resistor

FIGURE 1. Test Circuit

Vee
vee
1200

1&00

0OOI"F

O.OOhIF

~ LED

I.

LOUDSPEAKER

Tj:> 150'C.

7-36

r-----------------------------------------------------------------------------~

Typical Performance Characteristics
Output Voltage Drop

a...
Q

II:

'"
S
c

S

0.8

r--

10UT~

iI-

=
Q
I

o

lOUT

LooJ

:.;i"""

~

o 1-''''
o 200

400 600 800
OUTPUT CURRENT (mA)

40
10
120 160
JUNCTION TEMPERATURE(OC)

Output Voltage Drop

.....'"
.
c

!:i

:>

1.0
0.9
0.8
0.7
0.6
0.5

~

, .,

0.4
...= 0.3

I-

...a

~

Ii!
lE
I-

IL

5

1/

<;'

0.2
u
~ 0.1

o""""100

30

JLlJII

25

VON/OFF=ZV

1.0

I

0.5

I

oo

1000

10

1/

!Ii

if

iiiis

I

-40

-W
0
W 40
SUPPLY VOLJAGE(V)

NOHEATSIHK

o 10

20 30 40 5U 60 70 80 110
AMBIENT TEMPERATURE ("C)

ON/OFF Current vs.
ON/OFF Voltage

1:25

!::I

I-

§! 1.40

9

-

11.35 126°\ 25"C
i!:
..::..::
""" ..::.:..-""
I~
'-4O"C -I
1.30
1.25

1.20

o

T

51015202630

SUPPlY VOID8E (V)

TL/H/5271-13

TL/H/5271-14

iB20

li!l
il 15

I~

11

o

6

"z

o

VCC=26Y

t--

-;.±-.- -

f--

VCCr·5V r--

~

"

o

1

2

3

4

5

ON/OFr VOLJMlE (V)

Equivalent Block Diagram

Vee

....

30

!l! 1.45

26 50 75 100 125
JUNCTION TEMPERATURE (OC)

-

-

~

TL/H/5271-8

Threshold Voltage va.
Supply Voltage
_1.50

0

4

00

~

o

"r

I

TUH/5271-7

ON/OFF Current vs.
Junction Temperature

30

IN~INI~E

2

TUH/5271-6

1-

25

20
18 r-I- I- 1-116 f-I- - HEATSINK I- r-I14
12
I I
10
T ,INK8 ~r. ~
6

o

-10

200 300 400 500 600 700 800

V

20

TUH/5271-5

~

-5

VIN-2V

15

Maximum Power
Dissipation (To-220)

I

Q

38 VCC=12V

10

Vee (V)

II

OUTPUT CURRENT (mA)

-50 -25

.
I

I

20
15

=

1/

o

i

~

Output Voltage (VOUT)
35

....
....

CD
N

~

1.5

TL/H/5271-4

TL/H/5271-3

~

S
II:

r--

0.2

-40

......

Peak Output Current (VOUT)

=

I

0.4

~

.J.

5GO ..A

:>

I-

Device Operating Current
400

0.6

r

i:

TUH/5271-15

Vee

0---1------....-------------....--, ON/OfF~OUT

-¥-f;oonr

OUTPUT

TL/H/5271-12

FIGURE 1

7-37

,.

LM1921
(')

::;'

vee

n

C

::;:

tn
:::r

n
014

Ut""026

CI

3

I»
....
(;'
VOUT

540
R17

";'I

R8
33k

R6

BOk

19k~Rll

R12

700

~
':"

':"

18k

R1D

R16
4DD

3Dk
25k

25k

&11.0

I

,I

I

,

,.

. , . ,

":"

TUH/5271-9

I

r-

Application Hints
combined zener and diode breakdown should be less than
45 volts.

HIGH CURRENT OUTPUT
The 1 Amp output is fault protected against overvoltage. If
the supply voltage rises above approximately 30 volts, the
output will automatically shut down. This protects the internal circuitry and enables the IC to survive higher voltage
transients than would otherwise be expected. The 1921 will
survive transients and DC voltages up to 60 volts on the
supply. The output remains off during this time, independent
of the state of the input logic voltage. This protects the load.
The high current output is also protected against short circuits to either ground or supply voltage. Standard thermal
shutdown circuits are employed to protect the 1921 from
over heating.

iii:
....
CD
N
....

The LM1921 can be used alone as a simple relay or solenoid driver where a rapid decay of the load current is desired, but the exact rate of decay is not critical to the system. If the output is unclamped as in Figure 1, and the load
is inductive enough, the negative flyback transient will cause
the output of the IC to breakdown and behave similarly to a
zener clamp. Relying upon the IC breakdown is practical,
and will not damage or degrade the IC in any way. There are
two considerations that must be accounted for when the
driver is operated in this mode. The IC breakdown voltage is
process and lot dependent. Clamp voltages ranging from
-60 to -120 volts (with respect to the supply voltage) will
be encountered over time on different devices. This is not at
all critical in most applications. An important consideration,
however, is the additional heat dissipated in the IC as a
result. This must be added to normal device dissipation
when considering junction temperatures and heat sinking
requirements. Worst case for the additional dissipation can
be approximated as:
Additional PD = 12 x Lx f (Watts)

FLYBACK RESPONSE
Since the 1921 is designed to drive inductive as well as any
other type of load, inductive kickback can be expected
whenever the output changes state from on to off (see
waveforms on Figure 1). The driver output was left unclamped since it is often desirable in many systems to
achieve a very rapid decay in the load current. In applications where this is not true, such as in Figure 2, a simple
external diode clamp will suffice. In this application, the integrated current in the inductive load is controlled by varying
the duty cycle of the input to the driver IC. This technique
achieves response characteristics that are desirable for certain automotive transmission solenoids, for example.

where:

I = peak solenoid current (Amps)
L = solenoid inductance (Henries)
f = maximum frequency input signal (Hz)

For solenoids where the inductance is less than ten millihenries, the additional power dissipation can be ignored.

For applications requiring a rapid controlled decay in the
solenoid current, such as fuel injector drivers, an external
zener and diode can be used as in Figure 3. The voltage
rating of the zener should be such that it breaks down before the output of the LM1921. The minimum output breakdown voltage of the IC output is rated at -57 volts with
respect to the supply voltage. Thus, on a 12 volt supply, the

Overshoot, undershoot, and ringing can occur on certain
loads. The simple solution is to lower the Q of the load by
the addition of a resistor in parallel or series with the load. A
value that draws one tenth of the current or DC voltage of
the load is usually sufficient.

Oulpul

LM1921
OUTPUT
(PIN 2)

LM1921

----+----,
LOAD

II

o(~r:~1---LO-A""'D[...)11-1-----.

~I

L

L

~ ~ lN4OO1

)I

~ ~IN4001

TL/H/5271-10

TUH/5271-11

FIGURE 2. Diode Clamp

FIGURE 3
Zener clamp for rapid controlled current decay

•
7-39

~National

~ Semiconductor

LM1946 Over/Under Current Limit Diagnostic Circuit
General Description

Features

The LM1946 provides the industrial or automotive system
designer with over or under current limit detection superior
to that of ordinary transistor or comparator-based circuits.
Each of the five independent comparators can be used to
monitor a separate load as either an over current or under
current limit detector. Two comparators monitoring a single
load can function as a current window monitor.
Current is sensed by monitoring the voltage drop across the
wiring harness, pc board trace, or external sense resistor
that feeds the load.
Provisions for compensating the user set limits for wiring
harness resistance variations over temperature and supply
voltage variations are also available.
When a limit is reached in one of the comparators, it turns
on its output which can drive an external LED or microprocessor.
One side of the load can be grounded (not possible with
ordinary comparator designs), which is important for automotive systems.

•
•
•
•
•
•
•
•
•
•
•

Five independent comparators
Capable of 30 mA per output
Low power drain
User set input threshold voltages
Reverse battery protection
60V load dump protection on supply and all inputs
Input common mode range exceeds Vee
Short circuit protection
Thermal overload protection
Prove-out test pin
Available in plastic DIP and SO packages

Applications
• Lamp fault detector
• Motor stall detector
• Power supply bus monitoring

Typical Application Circuit-Lamp Fault Detector (IL > 1A)
Vee

R4

1.1t.l
R6

%r
OFF FOR ILAMP >1AMP
ON FOR ILAMP < 1AMP

,I.et -

R5

,

1..-_----,
I-=

30K
TEST

'I/IN-4

GND

TL/H/8707 -2

FIGURE 1

7-40

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vcc and Input Pins)
Survival Voltage (T :s: 100 ms)
Operational Voltage

-40"C to + 85·C

Operating Temperature Range (TAl
Maximum Junction Temperature

+ 150·C
- S5·C to + 150"C

Storage Temperature Range

-50Vto +SOV
9Vt02SV

Internal Power Dissipation (Note 1)

Continuous

Output Short Circuit to Ground or Vee

Lead Temperature (Soldering, 10 sec.)

+2SO"C

soov

ESD Susceptibility (Note 3)

Internally Limited

Electrical Characteristics 9V :s: Vee :s: 1SV,Iset = 20 /LA, Tj = 25·C (unless otherwise specified)
Parameter

Conditions

Min

Quiescent Current

All Outputs "Off"

Reference Voltage

Iraf

=

Reference Voltage
Line Regulation

9V

:s: Vcc :s:

Iset Voltage

lset

Input Offset Voltage

At Output Switch Point. Vo
9V:S: VCM:S: 1SV

=

Input Offset Current

11t!(+) - IIN(-:} 9V:S: VCM

:s: 1SV
:s: 1SV

Input Bias Current

=

5.8

10/LA
1SV,I raf

=

10 /LA
1.20

20/LA

IIN(+) or IIN(-), 9V:S: VCM

2V

Input Common Mode
Voltage Range

Max

Units

3.00

mA.:Je

S.4

7.0

Vde

±5

±50

mVde

1.40

1.60

Vde

±1.0

±5.0

mVde

±0.10

±1.00

p.A.:Je

20.00

22.00

/L~e

2S.0

Vde

4.00

Maximum Positive
Input Transient

Either Input. T

:s: 100 ms

Maximum Negative
Input Transient

Either Input. T

:s:

Output Saturation
Voltage

= 2 mA, 5V :s: VCC :s: 1SV
10 = 10mA,5V:S: VCc:S: 1SV
Vo = OVdc, Comparator "ON"

Output Short Circuit
Current

18.00

Typ
1.40

100 ms

SO

70

V

-50

-SO

V

10

=

Output Leakage Current

Vo

Test Threshold
Voltage

At Switch Point on Any Output
Vo = 2V (Note 2)

30

OVde. Comparator "Off"
0.80

Test Threshold
Current

0.80

1.00

Vde

1.00

1.20

Vde

45

120.0

mAde

0.Q1

1.00

/L~e

1.25

2.00

Vde

0.2

Note 1: Thermal

resistance from junction to ambiant is typically 53"C/W (board mounted).
Note 2: The tast p;n is an activa high input, i.e. all five will be forced high when this pin is driven high.
Note 3: CESD ~ 100 pF, RESD ~ 1.5k

7-41

/L~e

CD
..-

G)
.-

~
-I

Connection Diagram
+

20

In 1 '

+
In 2

OUTPUT 1

3
19

4

+

18

In 3

OUTPUT 2

OUTPUT 3
Vcc
VREF

ISET
GROUND

-

+
In 4

13

+
In 5

12
10
11

OUTPUT 4

OUTPUT 5
TEST/RESET
TL/H/8707 -20

Order Number LM1946N or LM1946M
See NS Package Number M20B or N20A

Typical Test Circuit
9V:S;Vcc :S;16V

VOUT

REFERENCE
SECTION

VR£F(5V)

TL/H/8707 -23

Simplified Comparator Schematic

TlIH/8707 -24

7-42

Typical Performance Characteristics
Quiescent Current
vsVee

Quiescent Current
vsVee

V.atvslo
2.0

5

4

1.&

E

1.2

i>

o.a

r'r-

~
",

i---"'"

o
o

I

-2

--

~

-

-4

-6
10

15

3]

2S

10

lout (mA)

12

14

16

-50

-30

Vee (volts)

2.0

50

1.6

-

1.2

30

50

Vr., vs Temperature
7.4

-

.... ..........

10-~

10

Vee (volts)

Vset VS Temperature

Peak 10 vs Vee
60

-10

o.a

71l

E

!

6.6

,...,

6.2

"."

./

10'

20
5.6

10

0
10

12

14

16

-«I

0

<40

Iset vs Temperature
50

~
:I

L,...o

.----

10

o

-«I

<40

80

0

13]

160

«l

80

3]

3]

10

10

0

TEIIP(OC)

<40

80

160

Iset vs Temperature
R3=510K
R4=1.1M
Vee=12V

30

-«I

13]

TEIIP(OC)

50

0
0

-«l

160

R3=oo
R4=570K
Vee = 12V

<40

~-

13]

Iset vs Temperature
50

R3=270K
R4=oo

3]

80

TEMP(OC)

Vee (voila)

13]

-

o

-«l

160

0

TEMP(OC)

«l

80

1:10

160

TEIIP(OC)

Test Threshold

,.

Common Mode Lower Limit

1.6

-

~

I""'"
III

.....

".

/

./

V

o.a
2.0
-«l

0

«l

80

1:10

160

-<40

TEIIP(OC)

0

<40

80

1:10

160

TEIIP(OC)
TLlH/8707 -4

7·43

Application Hints
THEORY OF OPERATION: UNDER-CURRENT LIMIT
DETECTOR

10 mV threshold would alert the system only if both bulbs
failed). Yet a fixed threshold of 75 mV may not work if the
nominal 100 mV sense voltage can vary 3:1 due to the factors IT]entioned earlier. What is required is a comparator with
a threshold-detecting voltage that tracks the nominal sense
voltage as battery line and ambient temperature change.
Thus, while the sense voltage may nominally be anywhere
from 50 to 150 mV, the threshold voltage will always be
roughly 75% of it, or 37 mV to 112 mV, and will detect the
failure of either of two bulbs.
The LM1946 integrated circuit contains five comparators especially designed for lamp monitoring requirements. Since
all lamps in a system share the same battery voltage and
ambient temperature, accommodations for these variations
need to be made only once at the IC, and each threshold of
the five comparators then tracks these variations.

. .- - +

LOAD

TUH/8707-6

Lamp Fault Detector

FIGURE 3. Equivalent Automotive Lamp Circuit
The diagram of Rgure 3 represents the typical lamp circuit
found in most automobiles. Switch S1 represents a dashboard switch, discrete power device, relay and/or flasher
circuit used for turn Signals. Sense resistor Rs can be an
actual circuit component (such as a 0.10. 1W carbon resistor) or it can represent the resistance of some or all of the
wiring harness. The load, represented here as a Single bulb,
can just as easily be two or more bulbs in parallel, such as
front and rear parking lights, or left and right highbeams, etc.
One of the easiest methods to electronically monitor proper
bulb operation is to sense the voltage developed across Rs
by the bulb current IL. If a fault occurs due to an open bulb
filament, the load current, and sense voltage Vs, drop to
zero (or to half their former values in the case of two bulbs
wired in parallel). A comparator circuit can then monitor this
sense voltage, and alert the system or system user (e.g.
power an LED) if this sense voltage drops below a predetermined level (defined as the threshold voltage).
Typical sense voltages range from tens to hundreds of millivolts. Not only does this sense voltage vary nonlinearly with
the battery voltage, it may vary significantly with ambient
temperature depending on the temperature coefficient (TC)
of the sense resistor or wiring harness. Since these nonlinear characteristics can vary from system to system, and
sometimes even within a single system, provisions must be
made to accommodate them. There are two general methodologies to accomplish this.
The first method uses only one bulb per monitoring circuit. A
sense resistor is selected to give 50-100 mVof sense voltage in an operational circuit, and a comparator threshold
detecting voltage of approximately 10 mV is set. Even if
component tolerances, battery line variations, and temperature coeffiCients cause the sense voltage to vary 3: 1 or
more, circuit operation will not be affected.
The second method must be used if two or more bulbs are
wired in parallel and it is necessary to detect if any single
lamp fails. This is often desirable as it reduces the number
of comparators and displays and system cost by at least a
factor of two. In this case, the sense voltage will drop by
only half (or less) of it's original value. For example, a nominal 100 mV drop across the sense resistor will drop to
50 mV if one of two bulbs fail. Therefore, a threshold detection voltage between 50 and 100 mV is required (Since a

SETTING THE COMPARATOR THRESHOLD VOLTAGE
The threshold voltage at which the comparator output
changes state is user-set in order to accommodate the
many possible system designs. The input bias currents are
purposely high to accomplish this, and are each equal to the
user-set current into the Iset pin (more on this later). Typically around 20 p.A, the effect of this across the sense resistor Rs compared to a typical load measured in amps is negligible and can be ignored. However, when resistors R1 and
R2 (Figure 4) are added to the circuit, a shift in the threshold
voltage is effected. This occurs since each input has been
affected by different IR drops. The LM 1946 behaves like
any other comparator in that the output switches when the
input voltage at the IC pins is zero millivolts (ignoring offset
voltage for the moment). If the output therefore has just
switched states due to just the right threshold voltage
across the sense resistor, then the sum of voltages around
the resistor loop should equal zero:

rcc

SI

lset
Rl

Iset'Rl

Rs

COMPARATOR
OUTPUT

VTHRSHLD

R2
Ise\'R2
LOAD

TL/H/8707 -9

Vthrshld

Vthrshld

lset (Rt - R2)

FIGURE 4. Input Bias Current
+ lset. R2 - Voffset - Iset. R1 = 0

Assuming Voffset « Vthrshld:
Vthrshld = lset. R1 - Iset. R2
Vthrshld = Iset (R1 - R2)

7-44

~

Application Hints (Continued)
V..~PIN 16)

Typical values are:
R1

= 6.2k ±5%
R4
1.1101

R2 = 1.2k ±5%
Iset = 20 ",A

@

25°C

~

Vthrshld = 20 IJ-A (6.2k - 1.2k) = 100 mV

vee - 1.4 V's! - 1.4
iset = -R-4- + -R-3lset

COMPENSATING FOR BATTERY VOLTAGE

1.75 ...-.,....-...,.........,....-,---,----,r-...---r-...,

3:....

1.00
0.75

V

0.50
0.25

~

If the sense resistors used in a system are perfect components with no temperature coefficient, then the compensation to be subsequently detailed here is unnecessary. However, resistors of the very small values usually required in a
lamp monitOring system are sometimes difficult or expensive to acquire. A convenient alternative is the wiring harness, a length of wire, or even a trace on a printed circuit
board. All of these are of copper material and therefore can
vary by as much as 3900 ppmrC. The LM1946 has been
deSigned to accommodate a wide range of temperature
compensation techniques. If the lset current is designed to
increase or decrease with temperature, nearly any temperature coefficient can be produced in the threshold voltage of
the five input pairs.

V

V

I

II

2

4

6

8 10 12 14 16 18
VBAT(V)
TL/H/8707 -21

FIGURE 5
This occurs since a higher voltage will heat the filament
more, increasing its resistance and allowing less current to
flow than expected. Figure 5 shows this effect. A best fit
straight line over the normal battery range of 9V to 16V for
this particular example can be given by:
IL (Amps)

= 0.62

+V,et
_ 1 4 (.2.. +.2..)
R3
'R3R4

COMPENSATING FOR AMBIENT
TEMPERATURE VARIATION

oL-~~~~~~-L-L~

o

R4

FIGURE 6

The current through a typical automotive lamp, whether a
headlight or dashboard illumination lamp, will vary as battery
voltage changes. The change, however, is nonlinear. Doubling the battery voltage does not double the lamp current.

/

= Vee

Thus, in actual use, the LM1946 threshold voltage should
track the variations in bulb current with respect to battery
voltage. To accomplish this, lset should have a component
that varies with the battery. As shown in the LM1946 circuit
schematic of Figure 18, the lset pin is two diode drops
above ground, or approximately 1.4V. A resistor from this
pin to the 6.4V reference sets the fixed component of lset; a
resistor to the battery line sets the variable component.
Thus, the best fit straight line in Figure 5 can be realized
exactly with only two resistors. The result is shown in Figure
6, giving a nominal Iset of 20 IJ-A that tracks the bulb current
as supply varies from 9V to 16V. The graph of Figure 7
shows the final result comparing a typical sense voltage
across Rs with the comparator threshold voltage as the
supply varies.

R 1 and R2 are necessary for another reason. These resistors protect the input terminals of the IC from the many
transients in an automobile found on the battery line, some
of which can exceed a thousand volts for a few microseconds. A minimum value of approximately 1 kG is therefore
recommended.

1.25

15)
TUH/8707-10

It's also important that the output of the comparator be in
the "off" state when the inputs are taken to ground, i.e. 51
is opened and the lamp is turned "off". The input section of
LM1946 has been designed to turn "off" when the inputs
are grounded and therefore not deliver an erroneous bulb
out indication. The comparator is only activated when the
inputs are above ground by at least 3V.

~I'

~

Iset{P~

For values of sense voltages greater than 100 mY, the comparator output is off (low). Sense voltages less than 100 mV
turn the output on (high).

1.50

R3
470K

240

200

!•

+ 0.069 • Vbattery

160
120

~

eo

~

-- -~

I'"

40

~

I

I

{Il

"Rs>;....

[~SENSE- t -

~

-~-

!tVTHRESHOLD-t(lSET" [R1 +R2J )
-L

0
9 10 11 12 13 14 15 16 17
VBAT{V)
TL/H/8707-22

FIGURE 7

7-45

,.

Application Hints (Continued)
approximate staight line TC generated. See Figure 9 for a
graphic representation of the ideal calculated values of lset
and the actual measured values generated. Notice that
there is very close agreement between the two graphs. The
circuit actually creates an S-shaped curve around the ideal.

One solution is to use a low cost thermistor in conjunction
with some low-TC resistors (see Figure 8).
There are three fixed resistors and one thermistor. This is
an NTC thermistor, since it has a negative temperature coefficient. This is what is required in order to have lset Increase as the temperature rises. The data sheet with the
thermistor described a number of ways to establish different
final TC's. The thermistor itself has a very large TC which is
somewhat difficult to describe mathematically. But, if it is
used with some other fixed resistors, such as Rmin and
Rmax, definite end pOint limits can be established and an

The low-cost thermistor is available from Keystone and is
listed as follows: RL2008-52.3K-155-Dl.
OVER-CURRENT LIMIT DETECTOR
Other applications include an over-current detector, as
shown in Figure 10. The load represented here can be either a single component or an entire system. Resistors R3

vret5.0mV). It is this requirement
that guarantees that the output will not be in an erroneous
high state upon power-up or whenever S1 is closed. (Should
this feature be unnecessary to a particular application circuit, the methodology described can be replaced with a simple capacitor across the comparator input pins).

R1

..":~
R2a

R2b

3.9K

1.2K
TL/H/8707-16

a. Open-Circuit Detector
R1a
5.1K

R1b
1K

R5~

O.1n.~
R2
1K
TL/H/8707 -17

b. Over-Current Limit Detector
FIGURE 16. Input Noise Filters for
Various Application Circuits

11

R5

R1

o~;~

__~~~~AA~~--~
R2

L2

5.1K

TL/H/8707 -18

FIGURE 17. Additional Noise Filters

fI

7-49

LM1946

n

Vee
17

ac
;:::;:
U)
()

::r
CD

in
Vour
20
19
18
13
12

~

TESTPINll~

GND
14
TVH/8707-3

FIGURE 18

JZI National
~ semiconductor

LM1949 Injector Drive Controller
General Description

Features

The LM1949 linear integrated circuit serves as an excellent
control of fuel injector drive circuitry in modern automotive
systems. The IC is designed to control an external power
NPN Darlington transistor that drives the high current injector solenoid. The current required to open a solenoid is several times greater than the current necessary to merely hold
it open; therefore, the LM1949, by directly senSing the actual solenoid current, initially saturates the driver until the
"peak" injector current is four times that of the idle or "holding" current (Figure a-Figure 7). This guarantees opening of
the injector. The current is then automatically reduced to the
sufficient holding level for the duration of the input pulse. In
this way, the total power consumed by the system is dramatically reduced. Also, a higher degree of correlation of
fuel to the input voltage pulse (or duty cycle) is achieved,
since opening and closing delays of the solenoid will be
reduced.
Normally powered from a 5V ± 10% supply, the IC is typically operable over the entire temperature range (- 55°C to
+ 125°C ambient) with supplies as low as 3 volts. This is
particularly useful under "cold crank" conditions when the
battery voltage may drop low enough to deregulate the 5volt power supply.
The LM1949 is available in the plastic mini DIP, (contact factory for other package options).

•
•
•
•
•
•
•
•
•
•
•
•
•

Low voltage supply (3V-5.5V)
22 mA output drive current
No RFI radiation
Adaptable to all injector current levels
Highly accurate operation
TTL/CMOS compatible input logic levels
Short circuit protection
High impedance input
Externally set holding current, IH
Internally set peak current (4 x IH)
Externally set time-out
Can be modified for full switching operation
Available in plastiC a-pin miniDIP

Applications
•
•
•
•
•

Fuel injection
Throttle body injection
Solenoid controls
Air and fluid valves
DC motor drives

Typical Application Circuit

.-

I
I
I

I
I
I

+-F~~--o VCC=5V

,.
TL/H/5062-1

FIGURE 1. Typical Application and Test Circuit
Order Number LM1949N
See NS Package Number N08E

7-51

Absolute Maximum Ratings
Input Voltage Range
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Lead Temp. (Soldering 10 sec.)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/DIstributors for availability and speclficetlons.
Supply Voltage
8V
Power Dissipation (Note 1)
1235mW

-0.3V to Vee
- 40"C to + 125°C
-65°C to + 150"C
150"C
2SOOC

Electrical Characteristics (Vee = 5.5V, VIN = 2.4V, T,= 25°C, Rgure 1, unless otherwise specified.)
Symbol

lee

Parsmeter

Supply Current
Off
Peak
Hold

Conditions

Typ

Max

Unita

VIN = OV
Pin 8 = OV
Pin 8 Open

11
28
16

23
54
26

mA
mA
mA

1.4
1.2

2.4
1.6

V
V

VOH

Input On Level

Vee = 5.5V
Vee = 3.0V

VOL

Input Off Level

Vee = 5.5V
Vee = 3.0V

18

Input Current' .

lop

Output Current
Peak
Hold

Pin 8 = OV
Pin 8 Open

Vs

Output Saturation Voltage

10 mA, VIN = OV

Vp
VH

Sense Input
Peak Threshold
Hold Reference

Vee = 4.75V

t

Time-out, t

t+RrOr

Min

1.0
0.7

1.35
1.15

-25

3

-10
-1.5

-22
-5

V
V
+25

".A
mA
mA

0.2

0.4

V

350
88

386
94

415
102

mV
mV

90

100

110

%

NOTE 1: For operation in ambient temperatures above 25"C, the device must be derated bssed on a 15O'C maximum lunctlon temperature and a thennal
resistance of l00"CIW Junction to ambient

Typical Circuit Waveforms
BAmRY VOLTAGE
Vam
IV1

.....=....._--,I

15V _ _ _=~=
lOY
IORMALBAmRYVOLTABE
5V

"COLO CRANK" ORLOWBAmRYVOLTAGE

BY

INPUT

VOLTABE

Pill

IVI

5V

BY..J

SEMSE INPUT

VOLT~\JVJ

TIMER
PINS

VOLTAGE
IV1

4A

CU~~WrA~

2A

DA

TL/H/5062-2

7·52

en
(')
=r

".~ ~

Vee

R18

R7~

Q5

~

023,....-

1

~2

RZ7

~

R21

R34

RI2

GNO

1

SUPPLY
GROUND 65

I

SENSE 6 4
TL/H/5062-3

FIGURE 2. LM1949 Circuit

6t6~W'

II

Typical Performance Characteristics
Quleacent Current va
Supply Voltage
12

1- 2530

V1N= OV
TI=25'C

110

ifl

I

VIN= 2.4V
T, = n'c

1
E

PE~

20

I
i:

~

"

./

~

15

~

ON

~~ ~

?-

~

!::i

1

o

.!!.

~380
~375

~

....

I

!!

Quleacent Supply Current
vs Junction Temperature

,

1

..
S·98

1.00

~

I

"'"

~

i

a

s;

1Iii

VIN= OV

10

8

-

VCC 0 5.5V

V~c =13.OV
L I

=&.5~_

Yee' aOf'=l ~
.1

VCco"V H LO

Yc~ 0 3.OV

I

....::::

I

·80 -30 0 30 80 911 120 1&0
JUNCTION TEMPERATURE I'C,

~~ l°f~=1::~~~:t~
51-+-+--+

5

. Senae Input Peak Voltage
vs Junction Temperature

3.5

s;4D&

.!!.400

~

2.5
!2.0

~V~C' ~.&V

=1.5

I;;:

:;
i 1.0

~

...ED.& r -

!!

5 15r-+-~~-4~~~d

Input Voltage Thresholda
va Junction Temperature

1
VCC

I. fO~+-'~~~~r-+-,
·80 -30 0 30 80 90 120 150
JUNCTION TEMPERATURE I'CI

~

~AK

30
25

OL.-~.l....--'--....L.......L...-I......J

;';3.0

1... 2530

2 3 4
5
SUPPLY VOLTAGE IV(

-110 ·30 0 3D 80 90 Ira 150
JUNCTION TEMPERATURE ('CI

Output Current va
Junction Temperature
35

I

Quiescent Supply Current
vs Junction Temperature

o

4 5
SUPPLYVOLTAGE IVI

o

35~r-'-~~~-r-~

i
I:
~

90

2
3
4
5
SUPPLY VOLrAGE IVI

8

I
o

1

\

55

_14

oz

TI'25'C

95

Iii··80

Normalized Timer Function
vs Supply Voltage

ii! 1.01

2 3 4 5 8 7
SUPPLY VOLTAGE (VI

=
i!'OO

I'r- r--.. ~

o

r

0.1

....

~105

390

1,2

~

Senae Input Hold Voltage
va Supply Voltage
s; 110

T(=25'C

012345
SUPPLY VOLTAGE IV(

e:1.03 T,,25'C

HOLD

o

2 3 4
5
SUPPLY VOLTAGE IVI

~355

"370

I

...

.Etil

.

PUK- I--

E

!!

EIl5
!!

i.. 20

I

0

T(025'C

!; 10

:I

.
=
.1.0

o

HOLJ

Sense Input Peak Voltage
va Supply Voltage

TI'fS'C

35

::c 30
~2&

~ 15

Input Voltage Thresholds
vs Supply Voltage

::1.&

&

-

o

;:~

i 10

I

0'12345
SUPPLY VOLTAGE (VI

!Ii

~ 1&

/

, /~

5

2i

3.0

•
..ira

I

iii 10

,/

o

.97

Output Current va
Supply Voltage

Supply Current vs
Supply Voltage

ON

ON
OFF

OFF
VCC ' 3.DV

o
·80 ·30 0 3D 80 90 120 1&0
JUNCTION TEMPERATURE I'C(

~395 l'o!..
i a90 ~ ~

=
...

.i!!

Ie 355

"~
--~ t--...

380 I-- VCC

1

VCC' 3.0V

I 5'iV ...... ~ t--...
r-....

375
.. 370
·80 -30 0 3D 80 90 120 1&0
JUNCTION TEMPERATURE ('CI
TLiH/S062-4

7-54

Typical Performance Characteristics
Sense Input Hold Voltage
vs Junction Temperature

!...
;

115

...-~~

;!

i2

90

l:1 85

.,

VCC

0

5.5V

VCC

0

3.0V

ffi

I

95

~

104

i

I

- s

80
·60 ·30 0 30 60 90 120 150
JUNCT10N TEMPERATURE rCI

1.0 1

:IE

>= 1.00
ffi
!:l .99
~
~ .98
is
Z

I

I

a:.::

105

~IDO

LM1949N Junction
Temperature Rise Above
Ambient vs Supply Voltage

Normalized Timer Function
vs Junction Temperature

E

110

(Continued)

I

I i
!
VCC

0

j

I
I

:

VCC - 5.5V
3.0V

i

I I

14

-+""'T'

J.-Li

~

!

I

.97
·60 ·30 0 30 60 go 120 150
JUNCT10N TEMPERATURE, CI

o

_90% DUTY
I CYCl!;

~

j;'

. . . .,~~TY
CYC E

01234567
SUPPLY VOLTABE IVI
TLiH/S062-S

Application Hints
age and the saturation voltage of 01. The drop across the
sense resistor is created by the solenoid current, and when
this drop reaches the peak threshold level, typically 385 mY,
the IC is tripped from the peak state into the hold state. The
IC now behaves more as an op amp and drives 01 within a
closed loop system to maintain the hold reference voltage,
typically 94 mY, across Rs. Once the injector current drops
from the peak level to the hold level, it remains there for the
duration of the input Signal at Pin 1. This mode of operation
is preferable when working with solenoids, since the current
required to overcome kinetic and constriction forces is often
a factor of four or more times the current necessary to hold
the injector open. By holding the injector current at one
fourth of the peak current, power dissipation in the solenoids and 01 is reduced by at least the same factor.

The injector driver integrated circuits were designed to be
used in conjunction with an external controller. The LM1949
derives its input signal from either a control oriented processor (COPSTM), microprocessor, or some other system. This
input signal, in the form of a square wave with a variable
duty cycle and/or variable frequency, is applied to Pin 1. In
a typical system, input frequency is proportional to engine
RPM. Duty cycle is proportional to the engine load. The circuits discussed are suitable for use in either open or closed
loop systems. In closed loop systems, the engine exhaust is
monitored and the air-to-fuel mixture is varied (via the duty
cycle) to maintain a perfect, or stochiometric, ratio.

INJECTORS
Injectors and solenoids are available in a vast array of sizes
and characteristics. Therefore, it is necessary to be able to
design a drive system to suit each type of solenoid. The
purpose of this section is to enable any system designer to
use and modify the LM 1949 and associated circuitry to
meet the system specifications.

In the circuit of Figure 1, it was known that the type of injector shown opens when the current exceeds 1.3 amps and
closes when the current then falls below 0.3 amps. In order
to guarantee injector operation over the life and temperature range of the system, a peak current of approximately 4
amps was chosen. This led to a value of Rs of 0.10. Dividing the peak and hold thresholds by this factor gives peak
and hold currents through the solenoid of 3.85 amps and
0.94 amps respectively.

Fuel injectors can usually be modeled by a simple RL circuit.
Figure 3 shows such a model for a typical fuel injector. In
actual operation, the value of L1 will depend upon the status
of the solenoid. In other words, L1 will change depending

Different types of solenoids may require different values of
current. The sense resistor Rs may be changed accordingly.
An a-amp peak injector would use Rs equal to .050, etc.
Note that for large currents above one amp, IR drops within
the component leads or printed circuit board may create
substantial errors unless appropriate care is taken. The
sense input and sense ground leads (Pins 4 and 5 respectively), should be Kelvin connected to Rs. High current
should not be allowed to flow through any part of these
traces or connections. An easy solution to this problem on
double-sided PC boards (without plated-through holes) is to
have the high current trace and sense trace attach to the
Rs lead from opposite sides of the board.

TLiH/50S2-S

FIGURE 3. Model of a Typical Fuel Injector
upon whether the solenoid is open or closed. This effect, if
pronounced enough, can be a valuable aid in determining
the current necessary to open a particular type of injector.
The change in inductance manifests itself as a breakpoint in
the initial rise of solenoid current. The waveforms on Page 2
at the sense input show this occurring at approximately 130
mY. Thus, the current necessary to overcome the constrictive forces of that particular injector is 1.3 amperes.

TIMER FUNCTION
The purpose of the timer Junction is to limit the power dissipated by the injector or solenoid under certain conditions.
Specifically, when the battery voltage is low due to engine
cranking, or just undercharged, there may not be sufficient
voltage available for the injector to achieve the peak current. In the Figure 2 waveforms under the low battery condition, the injector current can be seen to be leveling out at·3

PEAK AND HOLD CURRENTS
The peak and hold currents are determined by the value of
the sense resistor Rs. The driver IC, when initiated by a
logic 1 Signal at Pin 1, initially drives Darlington transistor 01
into saturation. The injector current will rise exponentially
from zero at a rate dependent upon L1, R1, the battery volt-

7-55

fI

Timer Function (Continued)

L

INPUT VOLTAGE
PIN 1 IV)

amps, or 1 amp below the normal threshold. Since continuous operation at 3 amps may overheat the injectors, the
timer function on the IC will force the transition into the hold
state after one time constant (the time constant is equal to
R"cT). The timer is reset at the end of each input pulse. For
systems where the timer function is not needed, it can be
disabled by grounding Pin 8. For systems where the initial
peak state is not required, (i.e., where the solenoid current
rises immediately to the hold level), the timer can be used to
disable the peak function. This is done by setting the time
constant equal to zero, (i.e., CT = 0). Leaving RT in place is
recommended. The timer will then complete its time-out and
disable the peak condition before the solenoid current has
had a chance to rise above the hold level.
The actual range of the timer in injection systems will probably never vary much from the 3.9 milliseconds shown in
Figure 1. However, the actual useful range of the timer extends from microseconds to seconds, depending on the
component values chosen. The useful range of RT is approximately 1k to 240k. The capacitor CT is limited only by
stray capacitances for low values and by leakages for large
values.

1
I

1
1
1
1

4
INJECTOR
CURRENT IAI

3

2
1

I

0

4
CURRENT IiI

2
1

o
4
ZENER
CURRENT IAI

2
1

o

The capacitor reset time at the end of each controller pulse
is determined by the supply voltage and the capacitor value.
The IC resets the capacitor to an initial voltage (V Bel by
discharging it with a current of approximately 15 mAo Thus,
a 0.1 ""F cap is reset in approximately 25 ""s.

QI COLLECTOR

VOLTAGE IV)

Vz·
VBAH

o
TL/H/5062-7

COMPENSATION
Compensation of the error amplifier provides stability for the
circuit during the hold state. External compensation (from
Pin 2 to Pin 3) allows each design to be tailored for the
characteristics of the system and/or type of Darlington power device used. In the vast majority of designs, the value or
type of the compensation capacitor is not critical. Values of
100 pF to 0.1 ""F work well with the circuit of Figure 1. The
value shown of .01 ""F (disc) provides a close optimum in
choice between economy, speed, and noise immunity. In
some systems, increased phase and gain margin may be
acquired by bypaSSing the collector of 01 to ground with an
appropriately rated 0.1 ""F capacitor. This is, however, rarely
necessary.

FIGURE 4_ Circuit Waveforms
amplifier keeps 01 off until the injector current has decayed
to the proper value. The disadvantage of this particular configuration is that the ungrounded zener is more difficult to
heat sink if that becomes necessary.
The second purpose of Z1 is to provide system transient
protection. Automotive systems are susceptible to a vast
array of voltage transients on the battery line. Though their
duration is usually only milliseconds long, 01 could suffer
permanent damage unless buffered by the injector and Z1.
This is one reason why a zener is preferred over a clamp
diode back to the battery line, the other reason being long
decay times.
VUH

FLYBACK ZENER
The purpose of zener Z1 is twofold. Since the load is inductive, a voltage spike is produced at the collector of 01 anytime the injector current is reduced. This occurs ,at the peakto-hold transition, (when the current is reduced to one fourth
of its peak value), and also at the end of each input pulse,
(when the current is reduced to zero). The zener provides a
current path for the inductive kickback, limiting the voltage
spike to the zener value and preventing 01 from damaging
voltage levels. Thus, the rated zener voltage at the system
peak current must be less than the guaranteed minimum
breakdown of 01. Also, even while Z1 is conducting the
majority of the injector current during the peak-to-hold transition (see Figure 4), 01 is operating at the hold current
level. This fact ,is easily overlooked and, as described in the
following text; can be corrected if necessary. Since the error
amplifier in the IC demands 94 mV across As, 01 will be
biased to provide exactly that. Thus, the safe operating area
(SOA) of 01 must include the hold current with a VeE of Z1
volts. For systems where this is not desired, the zener anode may be reconnected to the top of AS as shown in Fig5. Since the voltage across the sense 'reSistor now 'accurately portrays the injector current at all times, the error

---,

I
I
ILl

I INJECTOR
I
I

--..I

RS

ure

TLIH/S062-6

FIGURE 5. Alternate Configuration for Zener Z1

7-56

POWER DISSIPATION
The power dissipation of the system shown in Figure 1 is
dependent upon several external factors, including the frequency and duty cycle of the input waveform to Pin 1. Calculations are made more difficult since there are many discontinuities and breakpoints in the power waveforms of the
various components, most notably at the peak-to-hold transition. Some generalizations can be made for normal operation. For example, in a typical cycle of operation, the majority of dissipation occurs during the hold state. The hold state
is usually much longer than the peak state, and in the peak
state nearly all power is stored as energy in the magnetic
field of the injector, later to be dumped mostly through the
zener. While this assumption is less accurate in the case of
low battery voltage, it nevertheless gives an unexpectedly
accurate set of approximations for general operation.

The LM1949 can be easily modified to function as a switcher. Accomplished with the circuit of Figure 1, the only additional components required are two external resistors, RA
and Re. Additionally, the zener needs to be reconnected, as
shown, to Rs. The amount of ripple on the hold current is
easily controlled by the resistor ratio of RA to RB. RB is kept
small so that sense input bias current (typically 0.3 mAl has
negligible effect on VH. Duty cycle and frequency of oscillation during the hold state are dependent on the injector
characteristics, RA, Re, and the zener voltage as shown in
the following equations.
Hold Current ::::

(VH - RBevz)

The following nomenclature refers to Figure 1. Typical values are given in parentheses:
Rs

= Sense Resistor (0.10)

VH

=Sense Input Hold Voltage (.094V)

Vp

=Sense Input Peak Voltage (.385V)

Vz

=Z1 Zener Breakdown Voltage (33V)

VeATT

= Battery Voltage (14V)

L1

= Injector Inductance (.002H)

R1

= Injector Resistance (10)

n

= Duty Cycle of Input Voltage of Pin 1 (0 to 1)

~~

Minimum Hold Current ::::
Ripple or

~I

::

Hold :::: Re e Vz e...!..
RA
Rs

fo :::: Rs e RA e VBAn e (1 _ VeATT)
L1 Re
Vz
Vz
fo = Hold State Oscillation Frequency
Duty Cycle of fo :::: VeAn
Vz
Component Power Dissipation

= Frequency of Input (10Hz to 200Hz)
01 Power DiSSipation:

PO:::: ne (1 - VeAn) e VSAT eVH
Vz
Rs
VSAT = 01 Saturation Volt @ - 1 Amp (1.5V)

VH
Po :::: n e VeAn e Watts
Rs
Zener Dissipation:
Pz :::: Vz e L1 e f e

Pz:::: ne VBAneVH
Rs

(Vp2 + VH2)
Watts
((Vz-VeATT) e RS2)

P

Injector Dissipation:

_ VBeVZ

RA-~

VH 2
PI :::: n e R1 e Watts
RS2

As shown, the power dissipation by 01 in this manner is
substantially reduced. Measurements made with a thermocouple on the bench indicated better than a fourfold reduction in power in 01. However, the power dissipation of the
zener (which is independent of the zener voltage chosen) is
increased over the circuit of Figure 1.

Sense Resistor:
VH 2
PR:::: n - Watts
RS2
Vp2
PR (worst case) :::: n - 2 Watts
Rs

5V

SWITCHING INJECTOR DRIVER CIRCUIT

INPUT VOLTAGE
PIN I IV)

The power dissipation of the system, and especially of 01,
can be reduced by employing a switching injector driver circuit. Since the injector load is mainly inductive, transistor 01
can be rapidly switched on and off in a manner similar to
switching regulators'. The solenoid inductance will naturally
integrate the voltage to produce the required injector current, while the power consumed by 01 will be reduced. A
note of caution: The large amplitude switching voltages that
are present on the injector can and do generate a tremendous amount of radio frequency interference (RFI). Because
of this, switching circuits are not recommended. The extra
cost of shielding can easily exceed the savings of reduced
power. In systems where switching circuits are mandatory,
extensive field testing is required to guarantee that RFI cannot create problems with engine control or entertainment
equipment within the vicinity.

OV
400mV

/t

SENSE INPUT VOlTAGE
PIN4lmVI
OV

Vz

VUTT
01 COUECTOR
VOlTAGE IVI
OU

-

~

""I

TL/H/5062-9

FIGURE 6. Switching Waveforms

7-57

III

,,..

,,,
,..
"F;';';;'~--O VCC=5V

ZI
33V

5W
SENSE
5 GND

TL/H/5062-10

FIGURE 7. Switching Application Circuit

7-58

~National

~ semiconductor

LM 1950 750 rnA High Side Switch
General Description

Features

The LM19S0 is a high current, high side (PNP) power switch
for driving ground referenced loads. Intended for industrial
and automotive applications the LM19S0 is guaranteed to
deliver 7S0 mA continuous load current (with typically 1.4
Amps peak) and can withstand supply voltage transients up
to +60V and -SOY. When switched OFF the quiescent
current drain from the input power supply is less than
100 ",A which can allow continuous connection to a battery
power source.

•
•
•
•
•
•
•
•
•
•
•

The LM19S0 will drive all types of resistive or reactive loads.
To obtain a rapid decay time of the energy in inductive
loads, the output is internally protected but not clamped and
can swing below ground to at least S4V negative with respect to the input power supply voltage.
The ON/OFF input can be driven with standard SV TTL or
CMOS compatible logic levels independent of the Vee supply voltage used. Built in protection features include short
circuit protection, thermal shutdown, over-voltage shutdown
to protect load circuits and protection against reverse polarity input connections. The LM19S0 is available in as-lead
power TO-220 package and specified over a wide -40·C to
12S·C operating temperature range.

Typical Application

7S0 mA continuous output drive current
Less than 100 ",A quiescent current in OFF state
Low input! output voltage drop
+ 60V / - SOV transient protection
Drives resistive or reactive loads
Unclamped output for fast inductive decay tmies
Reverse battery protected
Short circuit proof
Overvoltage shutdown to protect loads
TTL/CMOS compatible control input
Thermal overload protection

Applications
•
•
•
•
•

Relay driver
SolenoidlValve driver
Lamp driver
Load circuit switching
Motor driver

+4.75 TO 26V

O.I P F

I

Vee SUPPLY
1

Vy

ov
ON

r-1 °ON_/ruT_F_F+-________- i
..J Lov 5

+5V

Vee - 54V
OUTPUT

OFF

II ~

I

L:::::::==------I=:::J...-,...---.J' •. ,.,.
GROUND

4

3 GROUND

RELAY
LOAD

TLlH/11237-1

'Required for stability

Connection Diagram
TO 220, 5 Lead

:".,,"

4 GROUND
3 GROUND
2 OUTPUT (VOUT )
1 SUPPLY (Vee)
TL/H/11237-2

Front View
Order Number LM1950T
See NS Package Number T05A
7-S9

•

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Continuous
2SV
Transient (T';; 100 ms)
-50Vto +60V
-1SV
Reverse Polarity (continuous)

Storage Temperature Flange

Operating Ratings (Note 1)

Internally Limited
1S0mH
1SO"C

Maximum Junction Temperature

230"C
2000V

ESD Susceptibility (Note 2j

-0.3Vto +S.OV

On/Off Voltage
Power Dissipation
Load Inductance

-SS-Cto + 150"C

Lead Temperature
(Soldering, 10 seconds)

Temperature Range (TA)

-40·C to + 12S·C

Supply Voltage Range
Thermal Resistances:
Junction to Case (81-C>
Case to Ambient (8c-al

4.75Vt02SV
3·C/W
50"C/W

Electrical Characteristics
Vee = 14V, lOUT = 150 mA unless otherwise indicated. BolcHac. limits apply over the entire operating temperature range,
- 4O"C ,;; TA ,;; 125·C, all other specifications are for TA = TJ = 2S·C
Parameter

Conditions

Typical

Supply Voltage
Operational
Survival
Transient
Supply Current

Input to Output
Voltage Drop

t = 1 mS,T = 100ms,
1% dutycycle

4.7S/4.7S
26/28
-15/-1S
60/80
-50/-S0

V (Min)
V (Max)
Voc(Min)
V (Max)
V (Min)

20

100/100

p.A(Max)

S
27S
550
825

10/10
350/3S0
700/700
950/9S0

mA(Max)
mA(Max)
mA(Max)
mA(Max)

lOUT = 250mA
lOUT = 500mA
lOUT = 7S0mA

0.30
O.SO
0.75

0.S/0.8
0.7/1.0
1.1/1.4

V (Max)
V (Max)
V (Max)

1.5

1.0/0.7S
2.0/2.0

A (Min)
A (Max)

VON/OFF

=

0.8V

ON/OFF Input
Threshold Voltage
ON/c:wF Input Current

Units
(Limit)

VON/OFF = 0.8V
VON/~= 2.0V
lOUT = OmA
lOUT = 2S0mA
lOUT = SOOmA
lOUT = 750mA

Short Circuit Current
Output Leakage Current

Limit

VON/OFF = 0.8V
VON/OFF = 2.0V
VON/OFI' = S.2SV

Overvoltage Shutdown
Threshold
Inductive Clamp
Output Voltage

VON/~

Output Tum-On Delay

VON/~ 0.8V to

Output Turn-Off Delay

VON/~ 2V to

= 2VtoO.8V,
lOUT = 100 mA

10

SO/SO

p.A (Max)

1.4

0.8/0.8
2.0/2.0

V (Min)
V (Max)

0.1
1
50

5/10
10/20
100/100

p.A(Max)
p.A(Max)
p.A(Max)

33

27/27
37/37

V (Min)
V (Max)

-4S

-120/-120
-40/-40

V (Max)
V (Min)

2V

4.2

20

p.s

0.8V

4.5

20

p.S

Note 1: Absolute Maximum Ratings indicate limits beyond which damags to the device may occur. Operating Ratings indicate conditions for which the devi08 is
Intended to be functional. but do not guarantee spec"ic performanoe limits. For guaranteed specifications and test condHions, see tihe Electrical Characteristics.
Note 2: Human body model, 100 pF discharged through a 1.5 kG resistor.

7-60

Typical Performance Characteristics
Output Voltage Drop
vs Temperature

Output Voltage vs Vee
35

~§!

I

t

I\. •

5011
VON/orr = 2V

30

E

1.0

25

E

~

I

20
15

II

10

~

0.8

~

0.4

J!

0.2

&

-10

-40

-20

0

I

'oUT

20

40

60

-40

~

1.5

0.8

~

~,
.}

60

120

V

"<
-5.

I

1.0

~

I

o.s

~

I

10

15

20

1/

~

0.3
0.2

II'"

0.1

oV

160

o

OUTPUT CURRENT (mA)

Maximum Power
Dissipation

25

80

I:

/

40

V

20

./

V

i

/

~

200

400

600

o

800

AMBIENT TEMPERATURE (Oc)

On/OFF Input Threshold
Voltage vs Supply Voltage

.1

I-- I--

I

-

1/

~

,

/

/

o

1.20

-40

40

60

120

160

o

5

JUNCTION TEMPERATURE (Oc)

INPUT VOLTAGE (V)

-

-4~!c - -25~C

/

1/

o
o

10 20 30 40 50 60 70 80 90

1.50

/

V

r-

NO HEAT SINK

12V!.
VON/OFF = 2V

10

r- r-

r~

4

ON/OFF Input Current
vs Temperature
vee.

20

:\.

r-- ~H~T~NK

2

10

50

r- r-

-

o

o

"<

HEAT SINK

1 1
1 1

OUTPUT CURRENT (mA)

40

l~nNI~E

r-r- -

16

14

/

o 10'"

30

g

~

ON/OFF Input Current
vs ON/OFF Input Voltage

30

100 200 300 400 500 600 700 600

20

60

/

,/

0.5
0.4

18

v

60

i

~

Operating Current
vs Load Current

Vee (V)

iil

0.8
0.7

100

o
o

.3

0.9

!I
!

JUNCTION TEMPERATURE (Oc)

2

0

40

0

~

...

I

o

Peak Output Current

iil

= 500mA

= 100mA

'oUT

SUPPLY VOLTAGE (V)

:3

I

II

§!

1/

r-5

I

0.8

Output Voltage Drop
vs Output Current
1.0

10

15

20

25

30

SUPPLY VOLTAGE (v)

TLlHI11237 -3

Tum-On Delay Time
vs Temperature

Delay nme Definitions

8.0

8.0

7.0

7.0

oNm

6.0

6.0

INPUT

--

'1M
.3
'l:j;;

Turn-Off Delay Time
vs Temperature

4.0
3.0

2.0

/

V

1.3

4.0

'l:
;:::

3.0

-- -

5.0

r-

2.0

OV

o

-40

0

40

80

120

160

JUNCTION TEMPERATURE (Oc)

OUTov

o
-40

0

40

80

120

160

JUNCTION TEMPERATURE (Oc)

TLlH/11237-11

TLlHI11237 -12

7-61

ON

:

:

I

I
I

'oN-;-v

1.0

1.0

+5V

~
IV

::~90"

~IO" : :~
'orr -! ~
TLlHI11237-10

II

Application Hints
The LM1950 can be used alone as a simple relay or solenoid driver where a rapid decay of the load current is desired, but the exact rate of decay is not critical to the system. If the output is unclamped as in Figure 1, and the load
is inductive enough, the negative flyback transient will cause
the output of the IC to breakdown and behave similarly to a
zener clamp. Relying upon the IC breakdown is practical
and will not damage or degrade the IC in any way. There are
two considerations that must be accounted for when the
driver is operated in this mode. The IC breakdown voltage is
process and lot dependent. Output clamp voltages ranging
from -40V to -120V (with Vee supply of 14V) will be encountered over time on different devices. This is not at all
critical in most applications. An important consideration,
however, is the additional heat dissipated in the IC as a
result. This must be added to normal device dissipation
when considering junction temperatures and heat sinking
requirements. Worst case for the additional dissipation can
be approximated as:
Additional Po = 12 X Lx f(Watts)

HIGH CURRENT OUTPUT
The 750 mA output is fault protected against overvoltage. If·
the supply voltage rises above approximately 30V, the output will automatically shut down. This protects the internal
circuitry and enables the IC to survive higher voltage transients than would otherwise. be expected. The LM1950 will
survive transients and DC voltages up to 60V on the supply.
The output remains off during this time, independent of the
state of the input logic voltage. This protects the load. The
high current output is also protected against short circuits to
either ground or supply voltage. Standard thermal shutdown
circuits are employed to protect the LM1950 from over heating.
FLYBACK RESPONSE
Since the LM1950 is designed to drive inductive as well as
any other type of load, inductive kickback can be expected
whenever the output changes state from ON to OFF (See
Waveform on Figure 1). The driver output was left unclamped since it is often desirable in many systems to
achieve a very rapid decay in the load current. In applications where this is not true, such as in Figure 2, a simple
external diode clamp will suffice. In this application, the integrated current in the inductive load is controlled by varying
the duty cycle of the input to the drive IC. This technique
achieves response characteristics that are desirable for certain automotive transmission solenoids, for example.
For applications requiring a rapid controlled decay in the
solenoid current, such as fuel injector drivers, an external
zener and diode can be used as in Figure 3. The voltage
rating of the zener should be such that it breaks down before the output of the LM1950. The minimum output breakdown voltage of the IC output is rated at - 54V with respect
to the supply voltage.

Where: I = Peak Solenoid Current (Amps)
L = Solenoid Inductance (Henries)
f = Maximum Frequency Input Signal (Hz)
For solenoids where the inductance is less than ten millihenries, the additional power dissipation can be ignored.
Overshoot, undershoot, and ringing can occur on certain
loads. The simple solution is to lower the Q of the load by
the addition of a resistor in parallel or series with the load. A
value that draws one tenth of the current or DC voltage of
the load is usually sufficient.
For frequency stability of the switch, a 0.1 /loF or larger output bypass capacitor is required.

Vee

Vee

ON/Off

TL/H/11237-4

FIGURE 1

LW1950

LM1950

OUTPUT
OUTPUT - -....- - - - ,
(PIN2)

OUTPUT
OUTPUT - -...- - - - ,
(PIN2)

LOAD

II

LOAD

L

RL

TLlH/11237-5

TL/H111237-6

FIGURE 2. Diode Clamp

FIGURE 3. Zener Clamp for Rapid
Controlled Current Decay
7-62

r-----------------------------------------------------------~~

...

Circuit Schematic

CD

g:

~

•
7-63

,.. r--------------------------------------------------------------------------------,

~
,..
~ ~National
~ Semiconductor

LM 1951 Solid State 1 Amp Switch
General Description

Features

The LM1951 is a high current, high voltage, high side (PNP)
switch with a built-in error detection circuit.
The LM 1951 is guaranteed to deliver 1 Amp output current
and is capable of withstanding up to ± 85V transients. The
built-in error detection provides an error flag output under
the following fault conditions: output short to ground or supply, open load, current limit, overvoltage or thermal shutdown. The LM1951 will drive all types of resistive or inductive loads. The output has a built-in negative voltage clamp
(::::: - 30V) to provide a quick energy discharge path for
inductive loads. The LM1951 features TTL and CMOS compatible logic input with hysteresis. Switching times, both turn
on and turn off, are 2 P.s (Cload < 0.005 p.F). In addition, its
quiescent current in the OFF state is typically less than
0.1 p.A at room temperature and less than 10 p.A over the
entire operating temperature and voltage range.
The LM1951 features make it well suited for industrial and
automotive applications.

• 0.1 p.A typical quiescent current (OFF state)
• 1 Amp output current guaranteed
• ± 85V transient protection
• Reverse voltage protection
• .Negative output voltage clamp
• Error flag output
• Internal overvoltage shutdown
• Internal thermal shutdown
• Short circuit proof
• High speed switching (up to 50 kHz)
• Inductive or resistive loads
• Low ON resistance (1 n maximum)
• TTL, CMOS compatible input with hysteresis
• Plastic TO-220 5-lead package
• ESD protected
• 4.5V to 26V operation

Typical Application Circuit and Connection Diagram
Vee = 4.SV TO 26V

.. ~f

ON

+5V

1'1_ .

...I

~r <>=~""'-II-+-I

..I~~"·' ~

2kll

I

ERROR 0 - -.....---'
rLAG

TLlH/9133-1
VIN

o

Output

OFF
ON

TO·220, 5·Lead

~'4 ERROR
~/~rLAG
3 GROUND
2 OUTPUT (VOUT )
1 SUPPLY (Vee)
TL/H/9133-2

Front View
Order Number LM1951T
See NS Package Number T05A

7-64

!i....I:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Operational Voltage
26VoC
Sustained Voltage
-40 VOC;;?; VCC :s; 85 VOC
Transient Voltage Protection
±85V
(T = 100 ms, 1% Duty Cycle, Rs ;;?; 100)
Pins 4, 5
26Voc

Power Dissipation (Note 1)
Load Inductance
Operating Temperature Range (TA)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
ESD Tolerance (Note 4):

Internally Limited
lH
-40'C to + 125'C
150"C
-65'C to + 150"C
260"C
2000V

CO
U'I

....

Electrical Characteristics
Vee

= 12V, loul = 500 mA, Coul = 0.001 p.F, TA = 25'C unless otherwise specified
Paremeter

Conditions

Typical

Supply Voltage, Vee
Operational
Transient

T

= 100 ms, 1% Duty Cycle, Ree ;;?; 10O

Tested
Limit
(Note 2)

Design
Limit
(Note 3)

4.5

Vmin

26

Vmax

-85

V

85
Supply Current

Voltage Drop
(VCC - Your)
Short Circuit Current

=
loul =
lout =
loul =
loul =
loul =

= 0.8V
250 mA, VON/~ = 2.0V
600 mA, VON/~ = 2.0V
lA, VON/~ = 2.0V
600 mA, VON/~ = 2.0V
lA, VON/<5F'F = 2.0V
Your = OV, VON/~ = 2V
0 mA, VON/~

loul

0.1

10

V
100

260

270

mAmax

650

mAmax

1.06

1.2

Amax

400

600

mVmax

0.7

1.0

Vmax

1.0

Amin

1.3

Input Current, Pin 5

I TurnON
I TurnOFF

4.5V :s; Vee :s; 26V

0.8V :s;

VON/~

:s; 5.5V

p.Amax

630

2.5
Input Threshold, Pin 5

Units

Amax

1.4

2.0

2.0

1.2

0.8

0.8

25

Vmax
Vmin

50

P-Amax

10

P.Amin

-40

Vmin

-24

Vmax

1

3

p.smax

1

3

p.smax

Rise Time

1

3

p.smax

Fall Time

1

3

p.smax

0.3

0.8

Vmax

10

3

mAmin

0.Q1

1

P-Amax

Output Clamp

Delay
Time

td,ON

'oul:S; 600mA

Rload

-30

= 200, Cload = 0.001 p.F

id, OFF

Error Flag Characteristics:
Output Voltage

Error Condition, Pin 4 Low, Sinking 10 mA

Sink Current

Error Condition, Pin 4

Output Leakage Current

No Error, Pin 4

Response Time

VLOGIC

= 0.3V

= 26V

= 5V, RLOGIC = 2 kO, CLOGIC = 0 p.F

Nota 1: Thermal

1

P.S

resistance iunctlon·to-case Is S"C/W. Thermal resistance casa·to-ambienl Is 50"C/W.
Tested Umlls are guaranteed and 100% production lested.
Nota 3: Dssign LlmHs ars guaranteed (but not 100% production tested) oyer the operaling temperature and supply voitsge range. rhese IimHB are not used to
calculate outgoing quality levels.
Note 4: Human body model, 100 pF discharged through a 1.5 kG resistor.
Note 2:

7·65

fI

.....
en
.....

In

Typical Performance Characteristics

!

Quiescent Current

Quiescent Current

tOO
~

.s
~

~

~

&

!
§

50

50

U

30

40

:5

60

ti

30

,..,.

20
to

&

10 = itA-

10= 600J-

to

-50 -25

G.4

T I

10= fOOmA

0.2

t.8

I
I

10= fA V

:3
!i
II!

-

8

~

c:s
I;;

~

I I
I I

o

-50 -25

0

25

~~

0

25

10

= Om'"

50

75

0.2
O. tV

o

tOO t25

o O.t 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t.o

OUTPUT CURRENT (A)

50

75

High Voltage Behavior
40
35
30

i--'"'"

t.2

1
0.2 II
o II

r
to

t5

20

25

-to
-to -5 0

30

SUPPLY VOLTAGE (V)

40

TURN- N

.3

t.4

i

U

1.3

-

+- r--

J.....-1"r

25 I-- r- 0Frl
20

to

t5

20

25

35

A

30

!(""

t-- r-t

N

/ll.-I
OFF _

25
20

t5

5

to

0

o

t.0

Vee=t2V

40

ON_

30

~i!5

TURN- FF

ON/OFF Current (Pin 5)
45

Vee = t2V

35

5 to t5 20 25 30 35 40

SUPPLY VOLTAGE(V)

ON/OFF Current (Pin 5)

~

V

/

-5

o

t.5

V

/

to

0.4

tOO t25

V

VON/OFF= 2V

t5

I

0.6

I\. =40nJ

20

II"

0.8

I I
I I

25

./

t.o

~

...

...

0.3

t.4

45

o

= 1250mA

0.4

t.6

ON/OFF Threshold (Pin 5)

......

.,.

~ o.s

::;;;

VON/DFf= 2V

JUNCTION TEIIPERATURE (OC)

t.2

0.7

Short Circuit Current

Vee :II 12V
0.8
VON/OFFj 2V

~~

o.a

:E

JUNCTION TE~PERATURE (OC)

Voltage Drop

I I

-\

10

o

T I
lout = 600 m!-

Vee = t2V
0.9 VON/iiff= 2V

20

OUTPUT CURRENT (A)

0.6

t.o

0.6

o O. t 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t.O

i

1-

Vee = t2V
VON/iiIT = 2V

40

-~

o

Voltage Drop

"

80

Vee = 12V
90 VON/iiff = 2V
80
70

o
t.O t. t

SUPPLY VOLTAGE (V)

t.2

t.3

t.4

t.5

t.6

t.7

o

0.5

ON!Off VOLTAGE (V)

Output Voltage
Resistive Load

t.O

t.5 2.0 2.5

3.0 3.5

ON!Off VOLTAGE (V)

Output Voltage
Inductive Load
Vee =12V

\ I\. =40n

I
J

t2

t6

200

TIME (1'8)

400

600

800

TIME (po)
TLlH/9133-3

7-66

r-----------------------------------------------------------------------------~ ~

Error Flag Output Characteristics
Open Load Threshold
10

9

Over Yoltage Threshold

Open Load Threshold
10

VON /6Fi' = 2V

40

Vee -12Y

vONIOff =2V

...~!ill:
...

VCC=12V
VON/ffiT = 2V

E

-

r-o

o

10

15

20

.....

1

o

25

~
i.

-50 -25

SUPPLY VOLTAGE (V)

0

25

50

35

-.......
30
-50 -25

75 100 125

JUNCTION TEMPERATURE (Oe)

0

25

50

75 100 125

JUNCTION TEMPERATURE (Oe)
TL/H/9133-13

Truth Table
Fault Condition
Normal

Overvoltage

Thermal Shutdown

VOUTShorttoGND

VOUT Short to VsuPPly

Open Load

CurrentUmit

YON/~'

Yout

Error Flag

L

L

H

H

H

H

L

L

L

H

L

L

L

L

L

H

L

L

L

L

H

H

L

L

L

H

L

H

H

L

L

L

H

H

H

L

L

L

H

H

H
• L '" 0

s:

VONIl:5I'I'

s:

O.8V

H .. 2!tI

s:

VONIl:5I'I'

L

s:

26V

,.
7-67

.- r------------------------------------------------------------------------------------------,
II)

G)

.-

~

Typical Applications
Vee = 12V

ON/OrF

o-.::t-+--I

ASCO
821002-12
12. lA
1/2" NPT NORt.tALLY
CLOSED VALVE

ERROR
FLAG

TLlH/9133-4

FIGURE 1. Solenoid Actuated Valve
Vee = 24V
,I'0nF

3<1> 480V AC
60A RESISTIVE
OR 15 HP MOTOR
ERROR
FLAG
TL/H/9133-5

FIGURE 2. 60A 3-Phase Mercury Displacement Relay

Vee

=12V 0-....- - - - - - - - . . ,
2N4277'

43kD.

10 nF

ON/OrF

0-1 H"""""'H.......

0-....+~---4-0 25A OUTPUT
lN1184
25A RECTIFIER
(NECESSARY FOR
INDUCTIVE LOADS)

TL/H/9133-6

• Available from Genmanium Power Devices, Andover, MA, Tel. (617) 475-5982

FIGURE 3. 25A Switch with Short Circuit Foldback

7-68

Typical Applications (Continued)
Vee = 12V

TL/H/9133-7

FIGURE 4. Latching Switch
Vee = 12V

.=c.10nF

...
100 kll

HEATER

ERROR
FLAG
(OPEN HEATER DETECT)

TLlH/9133-8

FIGURE 5. Temperature Controller with Hysteresis
Vee = 12V

,Il0nF

TLlH/9133-9

FIGURE 6. DC Motor Driver

fI

7·69

~

~
~

~

r------------------------------------------------------------------------------------------,
Typical Applications (Continued)

THRESHOLD
ADJUST~-++--I

VOLTAGE SENSITIVE
CIRCUITS

TL/H/9133-10

FIGURE 7. Over-Voltage Crowbar

Vee

=12V

TLlH/9133-11

Operation

SwllchType

Empty

Normally Open

Fill

Normally Closed

FIGURE 8. Fluid Level Controller
Vee = 12V

I

10nF

TLlH/9133-12

FIGURE 9. Indicator Lamp Driver

7-70

r-

i:

.....

Application Hints
When inductive loads are turned OFF, they produce a negative voltage spike. The LM1951 contains a voltage clamp
that limits these spikes to approximately -30V, thus an external clamp is not necessary in most applications.
Loads with an inductance of greater than 1H, driven to full
output current, may damage the clamp simply by exceeding
the power capabilities of the LM1951. An LM1951 can dissipate 25W continuous at 25'C ambient when mounted on a
large heatsink. If the load current is limited to 800 mA, the
sustained spike from an infinitely large inductance can be
handled. Sustained spikes produced by higher currents and
high inductances will exceed the 25W limit.

may be evident in a combination inductive/capacitive load,
or in an inductive load with supply decoupling capacitors in
the range of 100 nF to 1 p.F. For fast rise and fall times and
minimum ringing with inductive loads, a supply decoupling
capaCitor of 10 nF and an output capacitor of 1 nF is recommended. These should be located as close to the IC pins as
possible.
The error flag is an open collector output that pulls low under certain fault conditions. These errors include overvoltage (Vee> 26V), overcurrent (lOUT> 1.3A), undercurrent
(lOUT < 2 mAl, output short circuit to ground, output short
circuit to supply, and junction temperature greater than
1500C. By connecting a 2 kil resistor from the error flag
output to a 5V supply a logic output to a microprocessor is
provided.
The error flag can give seemingly false indications in a number of situations. Slewing large capacitive loads (>100 nF)
can drive the LM1951 into temporary current limit, producing a momentary error indication. Incandescent lamps and
DC motors require an inrush current that will also cause a
temporary current limit and error indication. Large inductive
loads (> 50 mH) initially appear as open Circuits, falsing the
error flag. The error flag pulses for about 1 P.s when any
load is turned ON since the output is initially at ground. In
microprocessor systems these false indications are easily
ignored in software. In discrete logic circuits utilizing a latch
at the error flag output, some filtering may be required.
An internal current sink (10 p.A minimum) is connected to
the input, pin 5. If this pin is left open it is guaranteed to pull
low, switching the LM1951 OFF. This characteristic is important under certain fault conditions such as when the control line fails open cirucit.

For inductances above 1H, care should be taken to see that
the output current does not exceed a value that could damage the clamp. While 800 mA is acceptable for the device
running at 25'C ambient on a heatsink, derate this current
for smaller heatsinks or higher ambient temperatures to limit
the junction temperature to 150'C. Alternatively, an external
clamp or resonating capaCitor can be added to handle any
combination of load inductance, load current, and device
temperature. This is especially important if the output current is boosted, such as the application shown in Figure 3. A
peak power of 750W could be developed in the internal
clamp if an inductive load is switched without external
clamping.
Another case where the clamp's power capability may be
exceeded is when driving a solenoid. The inductance of a
solenoid is greatest when energized, with the plunger pulled
in. As the plunger is pulled out of the solenoid, the inductance goes down. Under certain conditions of high solenoid
inductance and fast mechanical time constants, the current
may actually Increase when the solenoid is turned OFF.
Since the energy stored in an inductor cannot change instantaneously, the current must increase to conserve energy when the inductance decreases. This condition is traced
by observing the load current with a current probe and storage oscilloscope.
Load capacitances larger than 1 nF will slow rise and fall
times. Inductive loads having a capacitive component larger
than 1 nF will also exhibit overshoot. Furthermore, ringing

CD

en
.....

Although the input threshold has hysteresis, the switch
points are derived from a very stable band-gap reference. In
many applications, such as Figures 5 and 7, the LM1951
input can replace an extenal reference and comparator.
The input (pin 5) is clamped at -0.7V and includes a series
resistance of approximately 30 kil. This pin tolerates negative inputs of up to 1 mA without affecting the performance
of the chip.

fI

7-71

~National

~ Semiconductor

LM1964 Sensor Interface Amplifier
General Description
The LM1964 is a precision differential amplifier specifically
designed for operation in the automotive environment. Gain
accuracy is guaranteed over the entire automotive temperature range (- 40"C to + 125'C) and is factory trimmed prior
to package assembly. The input circuitry has been specifically designed to reject common-mode signals as much as
3V below ground on a single positive power supply. This
facilitates the use of sensors which are grounded at the
engine block while the LM1964 itself is grounded at chassis
potential. An external capaCitor sets the maximum operating
frequency of the amplifier, thereby filtering high frequency
transients. Both inputs are protected against accidental
shorting to the battery and against load dump transients.
The input impedance is typically 1 MO.

vided to detect open circuit conditions on either or both inputs and force the output to a "home" position (a ratio of
the external reference voltage).

Features
• Normal circuit operation guaranteed with inputs up to
3V below ground on a single supply
• Gain factory trimmed and guaranteed over temperature
(±3% of full-scale from -40'C to + 125'C)
• Low power consumption (typically 1 mAl
• Fully protected inputs
• Input open circuit detection
• Operation guaranteed over the entire automotive temperature range (-40"C to +125'C)
• Single supply operation

The output op amp is capable of driving capacitive loads
and is fully protected. Also, internal circuitry has been pro-

Schematic and Connection Diagrams
r---~--~-----'-----'----~----'----'-----'---------{-'~c

200

1-.--4........W\_D Your

+VHt

1-.---4----~--------------------~--------~----~------~~----{]~0
TL/H/6744-1

Plastic Chip Carrier Package

I
"Y£RTtIG
",PUT

•

5

17 Vee

• e

18.

15 Rr

NON-IIMRTJNG 7

INPUT

8

14.

~I'I'"'I:II"'m'-:-;rI

•

'Plns 1, 3, 4, 6, 8, 9,10,11,13,14,16,18,19 are
lrim pins and should be left Iloating.

TLlH/6744-6

Top View

7-72

Order Number LM1964V
See NS Package Number V20A

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VREF Supply Voltage

-0.3Vto +6V

DC Input Voltage (Either Input)

-3Vto +16V

Input Transients (Note 1)

1350mW

Output Short Circuit Duration

Indefinite

Electrical Characteristics Vcc =
Parameter
Differential Voltage Gain

- 65·C to + 150·C

12V, VREF = 5V, TA = 25·C unless otherwise noted
(Note 2)

Conditions
VDIF=0.5V
-WsVCMs+W

(Note 3)

Min

Typ

Max

4.41

4.50

4.59

VDIF=0.5V, -40·CsTAs125·C
-3VsVCMs + W
Gain Error (Note 5)

-2

OsVDIFsW
-WsVCMs+W

0

1.00

0.3

0

45

VIV

3

%/FS

MO
1.20 .

MO

1.0

p.A
0.3

OsVDIFsW
-lVsVCMs +1V

4.64

1.20

OsVDIFslV
-3VsVCMs+W
-40·CsTAs + 125·C
Inverting Input Bias Current

4.50

%/FS

0.70

OsVDIFsW
-WsVCMs+W

Units
Max
VIV

-3

osVDIFSW
-WsVCMs+W

Typ

2

OsVDIFSW
-3VsVCMs+W
-40·CsTA+125·C
Non-Inverting Input Bias
Current

Min

4.36

OsVDlFsW
-3VsVCMs+W
-40·CsTAs + 125·C
Differential Input Resistance

215·C
220·C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

±60V

Power Dissipation (see Note 6)

- 40·C to + 125·C

Storage Temperature Range
Soldering Information
Plastic Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

±60V

Vee Supply Voltage (RVcc = 15 kO)

Operating Temperature Range

1.5

100

p.A

p.A
45

OVsVDIFs1V
-3VsVCMs+W
-40·CsTAs + 125·C

150

p.A

VCC Supply Current

Vcc=12V, RVcc= 15k

300

500

p.A

VREF Supply Current

4.75VsVREFs5.5V

0.5

1.0

mA

Common-Mode Voltage
Range (Note 4)

-40·CsTAs+125·C

-1

DC Common-Mode
Rejection Ratio

Input Referred
-1VsVCMs+1V
VDIF=0.5V

50

60

Open Circuit Output Voltage

.One or Both Inputs
Open, -WsVCMs+W

0.371

0.397

1

-3

0.423

XVREF
0.365

Short Circuit Output Current

Output Grounded

1.0

2.7

Vec=12V, RVee=15K
VDIF=0.5V

50

65

V
dB

-3VsVCMs+1V
-40·CsTAS + 125·C
Vec Power Supply Rejection
Ratio

1

·5.0

0.397

0.429

XVREF
mA
dB

74
dB
60
VREF Power Supply
VREF=5 VDC
Rejection Ratio
VDIF=0.5V
Nota 1: This test is performed with a 1000n source impedance.
NOIe 2: These parameters are guaranteed and 100% production tested.
Nota 3: These parameters will be guaranteed but not 100% production tested.
Note 4: The LM1964 has been deSigned to common-mode to -3V, but production teating Is only performed at ±1V.
Nota 5: Gain error is given as a percent 01 lull-scale. Full·scale is defined as 1V at the Input and 4.5V at the output.
Note 6: For operation in ambient temperatures above 25'C the device must be deraled based on a maximum junction temperature 01 15O"C and a thermal
reSistance 01 93'C/W junction to ambient.
7-73

fI

Typical Performance Characteristics
Non-Inverting Inpu~ Bias
Current vs Temperature

Inverting Input Bias Current
vs Temperature

800

150

!

0i!i 600

...

...= 400

..E'"

;

1125
Ii
1 100
a
! 75 ~

r-

....:!:.z 200

I

50

.!..

25

o
-50 -25 0

"

-50 -25 0

TEMPERATURE (OCI

1

.
..i'"E
0-

I
...'"

1 0.4

0.8

I-

....

1. .

VcC=I2V

I-- I-- t-RVcc 15k

0.3

-

0.4

25 50 75 100 125 150
TEMPERATURE (OCI

0.5

.I

VREF=5.0V

0.6

.....

Vee Supply Current vs
Temperature

VREF Supply Current vs
Temperature

.I

~

o

25 50 75 100 125 150

1

......

E

~ 0.2

!J

0.2
-50 -25 0 25 50 75 100 125 150

0.1
-50-25 0

TEMPERATURE (OCI

25 50

~

100125150

TEMPERATURE (OCI

Short Circuit Output
4 Current vs Temperature

Differential Gain vs
Temperature
4.700
4.650

f'

" "'" "
i"""'o

z4.600

i;g 4.550
I'" ,.....

!iii 4.500

1

4.450
154.400

-~ r-

io""

""'"

4.350

o

4.300

-50 -25 0

25 50 75 100 125 150

25 50 75 100 125 150
TEMPERATURE (OCI

-50 -25 0

TEMPERATURE (OCI

7-74

TUH/6744-3

-

r----------------------------------------------------------------------,~

!!:

Typical Performance Characteristics (Continued)

:g
~

CMRR va Frequency

Voltage Gain va Frequency
20

1II1~

;;; 10

~I

80

......
Ii

z

ii... 0
i~ -10

Ic~I~WlpFI-

II:

II I

l!

IIIIIIIII~

60

iii

VeM=1 Vrms

:::>

CF=I000 pF

40

;;;

,

l!

20

.
II:
II:

IE

0

-20
-20

10

100
lk
10k
FREQUENCY (Hz)

lOOk

10

VREF Power Supply
Rejection
80

iii!

40 l-Hi+IIItI-H

I

Vee Power Supply Rejection

m.~lHH·!!~~!5 W

60

I

lOOk

Mn~~mm~~~nmm

I

~

100
lk
10k
FREQUENCY (Hz)

i 60~**.* ...

i

~ 100 mVrms
CF-opF
"'"

:;

20

=
I:

I

0
- 20 L...I.JLWIIIL..!.J..WIIII..J..L

10

100

lk
10k
FREQUENCY (Hz)

lOOk

40 H1HflfiHtHfIlfHlt
20 t-++t+IttIIH-f+tttRI-++IIIIIII-I+j.IIIfH
I-Htflllll-tHllHHI-tfRVce-1B kO
CF-OpF
0 I-HtfIHlll--t+IiIIIII--HVee-12 Voc

"","?Ll"Ju

-20 ...................................................

10

100
lk
10k
FREQUENCY (Hz)

lOOk
TUH/6744-4

Test Circuit
Vee
(9V-16V)

VREF
(4. 75V i'50V)

15k

O'OI~F~

20

17
-'-0 01 ~F

];.

NON-INVERTlN~...!. I-- ":"-....
INPUT

Av =4.5

INVERTIN~...!
INPUT

I-- _
;/

PI

I

151.t
RF

GND
TL/H/6744-5

7-75

~

IWANat10nal

:i ~ Semiconductor
LMD18400
Quad High Side Driver
General Description

Features

The LMD1S400 is a fully protected quad high side driver. It
contains four common-drain DMOS N-channel power
switches, each capable of switching a continuous 1 Amp
load (>3 Amps transient) to a common positive power supply. The switches are fully protected from excessive voltage,
current and temperature. An instantaneous power sensing
circuit calculates the product of tha voltage across and the
current through each DMOS switch and limits the power to a
safe level. The device can be disabled to produce a "sleep"
condition reducing the supply current to less than 10 ",A.
Separate ON/OFF control of each SWitch is provided
through standard LSTLL/CMOS logic compatible inputs.

• Four independent outputs with > 3A peak, 1A continuous current capability
• 1.30 maximum ON resistance over temperature
• True instantaneous power limit for each switch
• High survival voltage (60 Vee, SOV transient)
• Shorted load (to ground and supply) protection
• Overvoltage shutdown at Vee > 35V
• LS TIL/CMOS compatible logic inputs and outputs
• < 10 ,..A supply current in "sleep" mode
• - 5V output clamp for discharging inductive loads
• Serial data interface for 11 diagnostic checks:
- Switch ON/OFF status
- Open or shorted load
- Operating temperature
- Excessive supply voltage
• Two direct-output error flags

A MICROWIRETM compatible serial data interface is built in
to provide extensive diagnostic information. This information
includes switch status readback, output load fault conditions
and thermal and overvoltage shutdOWll status. There are
also two direct-output error flags to provide an immediate
indication of a general system fault and an indication of excessive operating temperatUre.
The LMDl8400 is packaged in a special power dissipating
leadframe that reduces the junction to case thermal resistance to approximately 20"C/W.

Applications
• Relay and solenoid drivers
• High impedance automotive fuel injector drivers
• Lamp drivers
• Power supply switching
• Motor drivers

Typical Application

Connection Diagram
20

10

Switch
S,lect

11

Inputs

12

In I
In 2

10kA

1n4

13

EiTor

Error
iii8tin.i

14

~o.OI"r

Enabl,

Enable

Shutdown

Cop

In 3

..,.C>C>

Out 1

CO

!i....
Thermal

Out 2

Out 3

I.

CS
Ctock

Out 4-

19

Output,

1

20

Vee

Output 2

2

19

Output 4

Enab"

3

"

Output 3

Ciiijj's.iICt

4

17

Thermal ShutdOWn

Ground

5

18

Ground

Ground

15

Ground

Clock

14

C oharg' pump (Cop)

Data Outpul

•

13

E"or

Input 1

•

12

Input ...

Input 2

10

11

Input 3

Tl/H/ll026-2

Oat. Output

Order Number LMD18400N
See NS Package Number N20A

TLlH/ll026-1

7-76

Absolute Maximum Ratings

E

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Survival Voltage (Pin 20)
Transient (t = 10 ms)
SOV
Continuous
-0.5Vto +60V
Output Transient Current (Each SWitch)
3.75A
Output Transient Current (Total, All Switches)

6A

Output Steady State Current (Each Switch)

1A

Logic Input Voltage (Pins 3, 9, 10, 11, 12)
Logic Input Voltage (Pins 4, 7)

Error Flag Voltage

16V

ESD Susceptibility (Note 2)

2000V

Power Dissipation (Note 3)

5W
Internally Umited

c....

CD

§

150"C

Junction Temperature (TJMax)
Storage Temperature Range

-65·Cto

+ 150"C
+ 260"C

- 40·C to

+ 125·C

Lead Temperature (Soldering, 10 Sec.)

Operating Ratings (Note 1)

-0.3Vto +16V

Ambient Temperature Range (TA)

-0.3Vto +6V

Supply Voltage Range

6Vto 2SV

Electrical Characteristics Vee = 12V, Cep = 0.01 ",Fd, unless otherwise indicated. Boldface limits apply
over the entire operating temperature range, -40·C ~ TA ~ + 125·C, all other limits are for TA = TJ = + 25·C.
Parameter

Conditions

Typical
(Note 4)

Umit
(Note 5)

Units
(Umlt)

0.04
7,t;

10
15

",A (Max)
mA(Max)

DC CHARACTERISTICS
Supply Current

Enable Input = OV
Enable Input = 5V, Inputs = OV
Enable Input = 5V, Inputs = 5V
Open Loads

7.5

15

mA(Max)

Output Leakage

Enable Input = OV, Inputs = OV
(Pins 1, 2, 1S, 19)

0.01

10

",A (Max)

RdsON

lOUT = 1A, (Note 6)

O.S

1.3

o (Max)

Short Circuit Current

Vee = 12V, (Note 6)
Vee = 6V, (Note 6)
Vee = 2SV, (Note 6)

1.2
2.4
0.6

0.8

A (Min)
A
A

Maximum Output Current

Vee - Vo = 4V, (Note 6)

3.75

Load Error Threshold Voltage

Pins 1, 2, 18, 19

4.1

V

Open Load Detection Current

Pins 1, 2, 18, 19

150

,...A

Negative Clamp Output Voltage

10 = 1A, (Note 6)

-5

V

Overvoltage Shutdown Threshold

35

Overvoltage Shutdown Hysteresis

0.75

Error Output Leakage Current
Thermal Warning Temperature
Thermal Shutdown Temperature

= 12V
VPin 13 < 0.8V
VPin 17 < 0.8V

0.001

VPin13

A

40

V (Max)

10

",A (Max)

V

145

·C

170

·C

fI

7-77

Electrical Characteristics Vee = 12V, CoP
over the entire operating temperature range, - 40"C :s: TA :s:
Parameter

= 0.Q1 ,...F, unless otherwise indicated. Boldface limits apply
+ 12S·C, all other limits are for TA = TJ = +2S·C. (Continued)

Conditions

Typical
(Nots4)

Limit
(Note S)

Units
(Limit)

S

10

,...s(Max)

7

1S

,...s(Max)

O.S

2

0.1S

1

,...s(Max)

AC CHARACTERISTICS

= SV,

Switch Turn-On Delay
(tcJ(ON»

Enable (Pin 3)
lOUT = 1A

Switch Turn-On Rise
Time (tON)

lOUT

Switch Turn-Off Delay
(tcJOFF)

Enable (Pin 3)
lOUT = 1A

Switch Turn-Off Fall
Time (tOFF)

lOUT

Enable Time (tEN)

Measured with Switch 1,
Pin 9 = 5V

30

SO

,...s(Max)

Error Reporting Delay
(tError)

Enable (Pin 3) = SV,
Switch 1 Load Opened

7S

1S0

,...s(Max)

Data Setup Time (tos)

CL

200

SOO

ns(Min)

TRI-STATE~

Pin S, Hi-Z Enable Time

Control (t1H, toH)

= 1A
= SV,

= 1A

= 30pF

Data Clock Frequency

2
3

,...s(Max)

,...s
1

MHz (Max)

DIGITAL CHARACTERISTICS
Logic "1" Input Voltage

Pins 3,4, 7, 9,10,11,12

2.0

V (Min)

Logic "0" Input Voltage

Pins3,4,7,9,10,11,12

o.a

V (Max)

Logic "1" Input Current

Pins 4, 7

0.001

1

,...A(Max)

Logic "0" Input Current

Pins 4, 7

-0.001

-1

,...A(Max)

TRI·STATE Output Current

Pin S, Pin 4
PinS = OV

O.OS
-O.OS

10
-10

,...A(Max)
,...A(Max)
,...A(Max)

= SV

= 2.4V

Enable Input Current

Pin 3

Channel Input Resistance

Pins 9,10,11,12

Error Output Sink Current

Pin 13

Logic "1" Output Voltage

PinS
lOUT = -360,...A
lOUT = -10,...A
lOUT = -10,...A

= O.SV

Logic "0" Output Voltage

PinB
lOUT = 100,...A

Thermal Shutdown Output
Source Current

Pin 17

= 2.4V

Thermal Shutdown Output
Sink Current

Pin 17

= O.BV

12

28

7S

28

kO(Min)

4

1••

mA(Min)

4.4

2.4
4.8
8.8

V (Min)
V (Min)
V (Max)

0.4

V (Max)

S

3

,...A(Min)

360

2S0

p.A (Min)

5.1

7-7S

Electrical Characteristics Notes
Nole I: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condHions for which the device is
intended to be functional, but do not guarantee specific performance IimHs. For guaranteed specifrcations and test condHions, see the Electrical Characteristics.
Note 2: Human body model; 100 pF discharge through a 1.5 kft resistor. All pins except pins 8 and 13 which are protected to 1000V and pins 1, 2, 18 and 19 which
are protected to 500V.
Note 3: The maximum power dissipation is a function of TJMax' 8JA, and TA and is limited by thermal shutdown. The maximum allowable power dissipation at any
ambient temperature is Po = (TJMax - TA)/8JA. If this dissipetion is exceeded, the die temperature will riae above 150'C and the device will eventually 90 into
thermal shutdown. For the LMD18400 the junction-ta-ambient thermal resistance, 8JA, is 6(1'C/W. WHh sufficient heatsinking the maximum continuous power
dissipation for the package will be,IOCMax2 X RON(Max) X 4 swHches (IA2 x 1.3ft x 4 = 5.2W).
Note 4: Typical values are at TJ = + 25"C and represent the most likely parametric norm.
Nole 5: All limits are 100% production tested at
Control (SOC) methods.

+ 25"C. LimHs at temperature extremes are guaranteed through correlation and accepted Statistical Quality

Note 6: Pulse Testing techniques used. Pulse width is < 5 ms with a duty cycle < 1 %.

Timing SpeCification Definitions
Switching Turn ON/OFF
Enable

Enable Turn-ON

= 5V

Channell Input

= 5V

+5V

+5V

Enabl.
Input

Channel
Input

--,,,,,,,--50%
OV

OV

Your

Your

Switch 1
Output

Switch
Output

OV----,
OV-_......1

TLlHll1026-4

TLIHll1026-3

Error Reporting Delay

Data Setup Time

Channel 1 output open circuited.

+5V

+5V
Channell
Input

Chip Select
- - - " \ - - - 50%

OV

OV

+5V

+5V
Error Flag
Output

~:---

Clock

50%

OV

OV

TLlHlll026-6

TLIHll1026-5

fI

7-79

.......

8

CD

Typical Performance Characteristics

Q

For all curves, Vee = 12V, Temperature is the junction temperature unless otherwise noted.

:i
Switch ON Resistance
vs Temperatura

Maximum Power
Dissipation vs
Ambient Temperature

"Sleep" Mode SUpply Current
vs Temperature,

1.3

12

/

1

Sz

1.0

~

o

~'{!, 0.9

D.8

~I-'"

0.7

Enable =

"

I

ov

Outputs grounded
Include. output

6~,,\ ,~~

'.akage current.

/

-

/
",

o
80

120

-.0

180

"'0

80

120

Short Circuit Current
vs Temperature

I
/,

1/

£ «

~

/
o
80

120

180

1 1 .1.

r--

1 1

~

'/

I

4
-.0

160

~

!
i

H--+-+-++++++-I
wf--H--+-+-+-++++-l
D.8f--H--+-+-+-++++-l
D.8 j::!:::j::::1~1"=I~:t=+:....j

40

80

120

160

-40

40

~
fl

I

120
100

V

80

1/ ......

60

!:i

"

~

'"

Error Output Voltage
Sink Current

0

40

jJ

80

TEMPERATURE (OC)

--

2.0

i

i

""I-'"

.0
-.0

1.5

120

160

1.0

1,4 L-L....J--L--L-L...J..--L-L..J....J

-4004080120180
T1:MPERATURE (0(:)

180

V8

£

1.0

120

80

T1:MPERATURE (Oc)

1.6
(Pins 9, 10, 11, 12)

+-+-+-+-H

1,2

Enable Threshold Voltage
vs Temperature

160

"

ILO• O = lA

TEMPERATURE (OC)

Switch Select Logic Input
Resistance vs Temperature

160

~~~~~...J..~-L~~

0

T1:MPERATURE (OC)



30",1 DELAY

-=

TL/H/l1026-B

Truth Table
Enable
Input
(Pin 3)

Chip Select
Input
(Pin 4)

Switch Control
Input
(Pins 8, 9, 10, 11)

Error
Output
(Pin 13)

Thermal SO
Output
(Pin 17)

0

X

X

0

0

X

0

X

1

1

Selected Switch is ON, Normal Operation

X

0

0

Switch is OFF but:
a. Load is Open Circuited, or
b. Load is Shorted to Vee, or
c. TJ > +145°C,or
d. Vee> +35V

0

Switch is ON, but;
a. Load is Shorted to Ground, or
b. Switch is in Power Limit, or
c. TJ > +145°C,or
d. Vee > + 35V and Switch is Actually OFF

X

X

Conditions
"Sleep" Mode, ISu

I

< 10/LA

Selected Switch is OFF

0

0

TJ > + 1700C. All Switches are OFF

1

X

X

X

Data Output Pin is TRI·STATE

0

X

X

X

Data Output Pin is Enabled and Ready to
Output Diagnostic Information

7·81

fI

Applications Information
The LMD18400 can be continually connected to a live power source, a car battery for example, while drawing less than
10 p.A from the power source when put into a "sleep" condition. This "sleep" mode is enacted by taking the Enable
Input (pin 3) low. During this mode the supply current for the
device is typically only 0.04 p.A. Special low current consumption standby circuitry is used to hold the DMOS
switches OFF to eliminate the possibility of supply voltage
transients from turning on any of the loads (a common problem with MOS power devices). When in the "sleep" mode,
all diagnostic and logic Circuitry is inactive. When the Enable
Input is taken to a logic 1, the switches become "armed"
and ready to respond to their control input after a short,
30 p.s, enable delay time. This delay interval prevents the
switches from transient turn-on. Figure 2 shows the switch
control logiC.

BASIC OPERATION
High-side drivers are used extensively in automotive and
industrial appliCations to switch power to ground referred
loads. The major advantage of using high-side drive, as opposed to low-side drive, is to protect the load from being
energized in the event that the load drive wire is inadvertently shorted to grounci as shown in Figure 1. A high-side
driver can sense a shorted condition and open the power
switch to disable the load and eliminate the excessive current drain on the power supply. The LMD18400 can control
and protect up to four separate ground referenced loads.
High Side Drive

T~

Hnoed~
=

Short can be
and the switch can be

opened

1
...L

Load

Output

Tl/H/ll026-9

Low Side Drive
Enabl.

- _.....--ov+

c~~::: 0-----1
Load

S~:t~::~ o--_..J
0V;.::=:!~ <>-----1
TL/H/ll026-11

FIGURE 2. Control Logic for Each Power Switch
Each DMOS switch is turned ON when its gate is driven
approximately 3.SV more positive than its source voltage.
Because the source of the switch is the output terminal to
the load it can be taken to a voltage very near the Vee
supply potential. To ensure that there is sufficient voltage
available to drive the gates of the DMOS device a charge
pump circuit is built in. This circuit is controlled by an internal
300 kHz oscillator and using an external 10 nF capacitor
connected from pin 14 to ground generates a voltage that is
approximately 20V greater than the Vee supply voltage.
This provides sufficient gate voltage drive for each of the
switches which is applied under command of standard SV
logic input levels.
The turn-on time for each switch is approximately 12 p.S
when driving a 1A load current. This relatively slow switching time is beneficial in minimizing electromagnetic interference (EMI) related problems created from switching high
current levels.

TLlH/ll026-10

FIGURE 1. High-Side va Low-8lde Drive
The LMD18400 combines low voltage CMOS logic control
circuitry with a high voltage DMOS process. Each DMOS
power switch has an individual ON/OFF control input. When
commanded ON, the output of the switch will connect the
load to the Vee supply through a maximum resistance of
1.30 (the ON resistance of the DMOS switch). The voltage
applied to the load will depend upon the load current and
the designed current capability of the LMD18400. When a
switch is commanded OFF, the load will be disconnected
from the supply except for a small leakage current of typically less than 0.01 pA

7-82

Applications Information

(Continued)

PROTECTION CIRCUITRY

The LMD18400 has been designed to drive all types of
loads. When driving a ground referenced inductive load
such as a relay or solenoid, the voltage across the load will
reverse in polarity as the field in the inductor collapses when
the power switch is turned OFF. This will pull the output pin
of the LMD18400 below ground. This negative transient
voltage is clamped at approximately - 5V to protect the IC.
This clamping action is not done with diodes but rather the
power DMOS switch turning back on momentarily to conduct the inductor current as it de-energizes as shown in
Figure 4.

The LMD18400 has extensive protection circuitry built in.
With any power device, protection against excessive voltage, current and temperature conditions is essential. To
achieve a "fail-safe" system implementation, the loads are
deactivated automatically by the LMD18400 In the event of
any detected overvoltage or over-temperature fault conditions.
Voltage Protection
The Vee supply can range from -0.5V to + 60 VDe without
any damage to the LMD18400. The CMOS logic circuitry is
biased from an internal 5.1 V regulator which protects these
lower voltage transistors from the higher Vee potentials. In
order to protect the loads connected to the switch outputs
however, an overvoltage shutdown circuit is employed.
Should the Vee potential exceed 35V all of the switches are
turned OFF thereby disconnecting the loads. This 35V
threshold has 750 mV of hysteresis to prevent potential oscillations.

---.--oVCC

I-

........
....OV

+

~

VOUThOV--5V

IL

TUH/l1026-13

When the output inductance produces a negative voltage,
the gate of the DMOS transistor is clamped at OV. At
-3.5V, the source of the power device is less than the gate
by enough to cause the switch to turn ON again. During this
negative transient condition the power limiting circuitry to
protect the switch is disabled due to the gate being held at
OV. The maximum current during this clamping interval,
which is equal to the steady state ON current through the
inductor, should be kept less than 1A. Another concern during this interval has to do with the size of an inductive load
and the amount of time required to de-energize it. With larger inductors it may be possible for the additional power disSipation to cause the die temperaure to exceed the thermal
shutdown limit. If this occurs all of the other switches will
turn OFF momentarily (see section on Thermal Management).

OV~~~~+-+-+-+-+-~~

f-f-t-t-t-f-:+-+-+-+-I

rr--.. .....

Vert: 20V/DIV

Swftch come. 'on'
to conduct load
current

FIGURE 4. Turn-oFF Conditions with an Inductive Load

.......... 1--

Your

I-~

3.5V _

I

Over/Under
Voltage Shutdown
BOV
......

40V

"j
.. ~

VOUT

Additionally, there is an undervoltage lockout feature built
in. With Vee less than 5V it becomes uncertain whether the
logic circuitry can hold the switches in their commanded
state. To avoid this uncertainty, all of the switches are
turned OFF when Vee drops below approximately 5V.
Figure 3 illustrates the shutoff of an output during a OV to
80V Vee supply transient.

Vee

~

Horiz: 10 ma/DIV

Power Limiting

TUH/l1026-12

FIGURE 3. Overvoltage/Undervoltage Shutdown

The LMD18400 utilizes a true instantaneous power limit circuit rather than simple current limiting to protect each
switch. This provides a higher transient current capability
while still maintaining a safe power dissipation level. The
power dissipation in each switch (the product of the Drain-to
Source voltage and the output current, Vds x lOUT) is con-

•
7-83

Applications Information (Continued)
til)ually monitored and limited to 15W by varying the gate
voltage ,and therefore the ON resistance of the switch. !3asitie as low as possi~le until 15W
caliy the' ON resistance
is being dissipated. To maintain 15W, the ON resistance
increases'to reduce the load current. This results in a decrease of the output voltage. For resistive loads, the output
voltage when in power limit will be:

This dynamic current limiting of the switches is beneficial
when driving lamp and large capacitive loads. Lamps require a large inrush current, on the order of 10 times the
normal operating cUrTent, when, first switched on with a cold
filament. The LMD18400willlimit this initial current to the
level where 15W is dissipated in the switch. As the filament
warms up the voltage i\cross the lamp increases thereby
decreasing the voltage across the switch which permits
more current to fully light the lamp. With limited inrush curent the lifetime of a lamp load is increased significantly.
Figure 6 illustrates the soft turn-on of a lamp load.

will

VOUT (in Power Limit) = Vee -

NCf

This provides a maximum transient current and drain-tosource voltage characteristic as shown in Figure 5.

The same principle of increasing output current as the voltage across the load increases allows large capacitive loads
to be charged more quickly by an LMDl8400 driver than as
opposed to a driver with a fixed 1A current limit protection
scheme. Figure 7 shows the output response while driving a
large capacitive load.

4,---,----,----,---,----,----,

/"\

3

~
!:;
..P

2

1

/,
V

15 Watt Power Limit

'\ ~

-

On Resistance
Current Limit

I
5

Thermal Protection
The die temperature of the LMD18400 is continually monitored. Should any conditions cause the die temperature to
rise to + 17O"C, all of the power switches are turned OFF
automatically to reduce the power dissipation. It is important
to realize that the thermal shutdown affects all four of the
switches together. That is, if just one switch load is enough
to heat the die to the thermal shutdown threshold, all of the
other switches, regardless of their power dissipation conditions, will be switched OFF. All of the switches will be re-enabled when the die temperature has cooled to approximately + 160"C. Until the high temperature forcing conditions
have been removed the switches will cycle ON and OFF
thus maintaining an average die temperature of + 165'C.
The LMD18400 will Signal that excessive temperatures exist
through several diagnostic output signals (see Diagnostics).

10

15

-

I--20

2S

30

SWITCH DRAIN - SOURCE VOLTAGE (V)
TLlH/ll026-14

FIGURE 5. MQlmum Output Current with
Instantan,eous Power Limiting
Drtvlng a Lamp

Vee = 12V
-12V, 2A Lampf-+-+-+-+--I

VIN

Driving a Large
capacitive Load

Vee

~I

OV H-++-I---fIIII...f-+-I-+-I

=12V

CLOAD = 4700 J.lFd

-+-+-+-+---1

VIN
OV~~r-r-+-+-+-+-+-~~

VOUT

OV

~~

~l

VOUT

Vert: 5V/Dr! Horlz: 100 ms/Dr!

V

v

OV~~~+-+-+-+-+-+-+-~

TL/H/ll026-15

FIGURE 6. Soft Turn-On of a Lamp Load

Vert: 5V/Dr! HorIz: 20 rns/DIV

The steady state current to the load is limited by the package power dissipation, ambient temperature and the ON resistance of the switch which has a positive temperature coefficient as shown in the Typical Pertormance Characteristics.

TLlH/l1026-16

FIGURE 7. Driving a Large Capacitive Load

7-84

Applications Information (Continued)
DIAGNOSTICS

tion, one for each channel in succession (see Load Error
Detection).

The LMD18400 has extensive circuit diagnostic information
reporting capability. Use of this information can produce
systems with intelligent feedback of switch status as well as
load fault conditions for troubelshooting purposes. All of the
diagnostic information is contained in an ll-bit word. This
data can be clocked out of the LMD18400 in a serial fashion
as shown in Figure 8. The shift register is parallel loaded
with the diagnostic data whenever the Chip Select Input is
at a Logic 1 and changes to the serial shift mode when Chip
Select is taken to a Logic o. The Data Output line (pin 8) is
biased internally from a 5.1 V regulator which sets the Logic
1 output voltage. This pin has low current sourcing capability
so any load on this pin will reduce the LogiC 1 output level
which is guaranteed to be at least 2.4V with a 360 p.A load.

Bits 5 through 8 provide a readback of the commanded
ON/OFF status of each switch.
A unique feature of the LMDl8400 is that it provides an
early warning of excessive operating temperature. Should
the die temperature exceed + 145°C, bit 9 will be set to a
Logic O. Acting on this information a system can be programmed to take corrective action, shutting OFF specific
loads perhaps, while the LMD18400 is still operating normally (not yet in thermal shutdown). If this early warning is
ignored and the device continues to rise in temperature, the
thermal shutdown circuitry will come into action at a die temperature of + 170"C. Should this occur bit 10 of the diagnostic data stream will be set to a Logic 0 indicating that the
device is in thermal shutdown and all of the outputs have
been shut OFF.

The data interface is MICROWIRE compatible in that data is
clocked out of the LMD18400 on the falling edge of the
clock, to be clocked into the contrOlling microprocessor on
the rising edge. Any number of devices can share a common data output line because the data output pin is held in a
high impedance (TRI-STATE) condition until the device is
selected by taking its Chip Select Input low. Following Chip
Select going low there is a short data setup time interval
(500 ns Min) required. This is necessary to allow the first
data bit of information to be established on the data output
line prior to the first rising clock edge which will input the
data bit into the controller. When all 11 bits of diagnostic
data have been shifted out the data output goes to a Logic 1
level until the Chip Select line is returned high.

The final data bit, bit 11, indicates an overvoltage condition
on the Vee supply (Vee is greater than 35V) and again indicates that all of the drivers are OFF.
The diagnostic data can be read periodically by a controller
or only in the event of a general system error indication to
determine the cause of any system problem. This general
indication of a fault is provided by an Error Flag output (pin
13). This pin goes low whenever any type of error is detected. There is a built-in delay of approximately 75 P.s from the
time an error is detected until pin 13 is taken low. This is to
help mask short duration error conditions such as may be
caused by driving highly capacitive loads (>2 p.F). A lamp
load may generate a shorted load error for several hundred
milliseconds as it turns on which should be ignored.

Figure 8 also indicates the significance of the diagnostic
data bits. The first 4 bits indicate an output load error condi-

CHIPsnE~ -----,~:~--------------------------------------------------------~r-....; :-- Setup tim. required

CLOCK

DATA OUTPUT

BITH
CH1

Z

3

<4

5

6

7

8

CHZ

CH3

CH4

CH1

CHZ

CH3

CH4

v

v

ERROR STATUS

ON/OFF STATUS

LOAD OK

SWITCH OFF

LOAD ERROR

SWITCH ON

10

11

TLlH/ll026-17

FIGURE 8. Serial Diagnostic Data Assignments

fI

7-85

C)

~
co

....
Q

:!!

r---------------------------------------------------------------------------------,
Applications Information (Continued)
The Error Flag output pin is an open drain transistor which
requires a pull-up resistor to a positive voltage of up to 16V.
Typically this pull-up is to the same 5V supply which is biasing the Enable input and any other external logic circuitry.
The Error Flag pins of several LMD18400 packages can be
connected together with just one pull-up resistor to provide
an all-encompassing general system error indication. Upon
detection of an error, each device could then be polled for
diagnostic information to determine the source of the fault
condition.

LOAD ERROR DETECTION
An important feature of the LMD18400 is the ability to detect open or shorted load connections. Figure 10 illustrates
the detection circuit used with each of the drivers.

A second direct output error flag is for an indication of Thermal Shutdown (pin 17). This active low flag provides an immediate indication that the die temperature has reached
+ 17O"C and that the drive to all four switches has been
removed. This output is pulled up to the internal 5.1V logic
regulator through a small (5 /LA) current source so use of a
buffer on this pin is recommended.
+S.2V Bias

SOk

4.1V
_
Reference -

+5V

TLlH/l1026-19

FIGURE 10. Detection Circuitry
tor Open/Shorted Loads

47kQ

J
LMD1B400

A voltage comparator monitors the voltage to the load and
compares it to a fixed 4.1 V reference level. When a switch is
OFF, the ground referenced load should have no voltage
across it. Under this condition, an internal 50 kO resistor
connected to Vee will provide a small amount of current to
the load. If the load resistance is large enough to create a
voltage greater than 4.1V an Open Load Error will be indicated for that switch. The maximum load resistance that will
not generate an Open Load Error when a switch is OFF can
be found by:

"Fall Saf'"
Shutdown
Input

Open Collector
Inverter or Buffer

TLlH/ll026-18

FIGURE 9. Thermal Shutdown Flag and Shutdown Input
A useful feature of pin 17 is that it can also be used as a
shutdown input. Driving this pin low immediately switches all
of the drivers OFF, just the same as if thermal shutdown
temperatures has been reached, yet all of the control logic
and diagnostiC circuits remain active. This is useful in designing "fail-safe" systems where the loads can be disabled
under any sort of externally detected system fault condition.
The diagnostiC logic however does not distinguish between
normal thermal shutdown or the fact that pin 17 has been
driven low. As such, various switch errors and an over-temperature indication will be reported in the diagnostic data
stream.

RMax =

4.1 V
x 50 kO; for no Open Load Indication
Vee - 4.6V

To make this Open Load Error threshold more sensitive, an
external pull-up resistor can be added from the output to the
Vee supply.
Also when a switch is commanded OFF, should the load be
shorted to the Vee supply, this same circuitry will again indicate an error.
When a switch is commanded ON, the load is expected to
have a voltage across it that approaches the Vee potential.
If the output voltage is less than the 4.1V threshold an error
will again be reported, indicating that the load is either shorted to ground or that the driver is in power limit and not able
to pull the output voltage any closer to Vee. The minimum
load resistance that will not generate a Shorted Load Error
when a switch is ON can be found by:

Figure 9 illustrates the use of pin 17 as both an output thermal shutdown flag and as an input to shut down only the
switches. Directly tying pin 17 to + 5V will prevent the internal thermal shutdown Circuitry from disabling the switches.
For reliability purposes however this is not recommended as
there will then be no limit to the maximum die temperature.

RMin =

Refer to the Truth Table for a summary of the action of
these direct-output error flags.

7-86

4.1V (Vee - 4.1V)
15W
; for no Shorted Load Error

Applications Information (Continued)
Figure 11 indicates the range of load resistance for normal
operation, open load, and shorted load or power limit indication.
40k

:s...

30k

I
I
I
Cetected as an
I""-L.0pen Load

\

20k
10k

...

lk

~
en
iii

'"
Q

9

The LMD18400 is packaged with a specialleadframe that
helps dissipate heat through the two ground pins on each
side of the package. The thermal resistance from junctionto-case (8Jcl for this package is approximately 200C/W.
The thermal resistance from junction-to-ambient (8JA>, without any heatsinking, is approximately 600C/W. Figure 12 illustrates how the copper foil of a printed circuit board can
be designed to provide heatsinking and reduce the overall
junction-to-ambient thermal resistance.

I

i\

u

z

Careful calculation of the worst case total power dissipation
required at any point in time, together with providing sufficient heatsinking will prevent this from occurring.

If~
Normal Operation

10

Il

5
0

~
10

~

15

20

~
Detected a. a

The power dissipation in each switch is equal

-

Shorted Load
25

30

35

40

45

to:

(Vee - VOUT)2
Po (Each SwHch) = ILoad2 X RON or .:......:""-R--==ON
where RON is the ON resistance of the switch (1.30 maximum). These equations hold true until the power dissipation
reaches the maximum limit of 15W. With resistive loads, the
15W power limit threshold will be reached when:

r50

Vcc(V)
TUHI11026-20

FIGURE 11. Load Resistance Detected as Errors

Vcr!RL!': 60W

THERMAL MANAGEMENT

Inductive loads will create additional power dissipation when
switched OFF. Figure 13 shows the idealized voltage and
current waveforms for an inductive load.

It is particularly important to consider the total amount of
power being dissipated by all four switches in the
LMD18400 at all times. Any combination of the switches
driving loads will cause an increase in the die temperature.
Should the die temperature reach the thermal shutdown
threshold of + 1700C, all of the switches will be disabled.

Maximum Power Dissipated
and Junction to Ambient
Thermal Resistance vs Size

I

I
I

~o(,") "".. ~ 80

~~~I""""

I-- ,,"\0"\

~ 1'0....
".

'"

;....

............

-

'JA
1-",-

I.D

o
o

-

20

10

20

30

50

L SIZE (mm)
TL/H/ll026-22

P. C. Board
TLlH/ll026-21

FIGURE 12. Recommended PC Board Layout to Reduce the Thermal Resistance from Junctlon-ta-Amblent

fI

7-87

Applications Information (Continued)
power limit protection. If the inductor is too large. the time
interval may be long enough to heat the die temperature to
+ 170"C thereby shutting OFF all other loads on the package.
The total average power dissipation during a full ON/OFF
switching cycle of an inductive load will be:
'p~L(Vcc + SV)]
1
[

Vee

+5V
Switch
Control

r--:::--1 ".. I
ON ~
I-- Ion -+- toff -I

ov --.J

PO(tot) =

~

lpeak

'LOAD OA - - /

"--

H

!,,/amp

rI
I
VOIIT OV --J
-SV L.r-'
TL/H/l1026-23

FIGURE 13. Switching an Inductive Load
When switched ON. the worst case power dissipation is:
Vee
PO(ON) = Ipeak2 x RON; where IPeak = R
R
ON + S
The steady-state ON current of the inductor should be kept
less than 1A per power switch.

PO(OFF) =

2

toN

+ toFF

30
10

]:
i!!""

x IPeak

3

\

"......

0.3

'"

0.1

for the time interval. lelamp. which is the time required for
the inductor current to fall to zero;
lciamp =

10

100

The additional power dissipation during turn-off. as the inductor is de-energized and the voltage across the inductor
is clamped to -5V. can be found by:

+ 5V)

+

Due to the common cut-off of all loads forced by thermal
shutdown. the thermal time constants of the package become a concern. Figure 14 provides an indication of the
time it takes to heat the die to thermal shutdown with a step
increase in package power dissipation from an initial junction temperature of + 25·C. This data was measured using
a PC board layout providing a thermal resistance from junction to ambient of approximately 35·C/W. Less heatsinking
will. of course. result in faster thermal shutdown of the power switches.

Vee

(Vee

Ipeak2 RON toN

r... r-. ....

0.03

a
a

IPeak xL

-sv-

10

20

30

.w

50

60

TOTAL PACKAGE POWER
DISSIPATION (W)

The size of the inductor will determine the time duration for
this additional power dissipation interval. Even though the
peak current is kept less than 1A. the switch during this
interval will see a voltage across it of Vee + 5V with no

TL/H/11026-24

FIGURE 14. Approximate time required for the die to
reach the 170"C thermal shutdown point from 2S·C for
different totsl package power dissipation levels.

7-88

E
c

Applications
ON/OFF Switching of multiple voltage regulated circuit loads. Reset flag feedback from the LM2926
as shown connected to Output 4 can make the LMD18400 act as an electronic fuse for load faults.
Vee

=

...

CCI

8

12 to 28V

Load Circuit Select Inputs
ON

~

+ 1OV Circuit

10

+BV Circuit

11

+SV Circuit

12

+5V Circuit

In 1
In 2
In 3
In 4

o to

I

lA

Load

[nable

Enable
10 kll

0
0

13

Out 1

~

Error

+SV

00

Error

C

::::E
.....

Out 2

o to

lA

Thermal

Thermal

Shutdown

Load

18
Out 3

Cs
19

Clock

Diagnostic

Out 4

Data Output

Data Output

o to
lA

Load

o to
O.SA

load

Delayed Relet
Error FO'O,:;9_ _ _ _,

TL/H/ll026-25

Unipolar Drive for a 4-Phase Stepper Motor

20

10

Winding

11

Drive
Inputs

12

In 1
In 2

Ccp

In 3

14
IO.01PF

In 4

Enable

Enable
10 kll

13

Error

0
0

Oult
Stepper Motor

~

00

C
::::E
.....

Error

Thermal

Thermal

Shutdown

CIA

~.x

per winding)

Out2

r\----,

fI

18
Out3

Cs
Clock

Diagnostic
Data Output

19
Out4

Data Output

TL/H/ll026-26

7-89

Applications (Continued)
Recommended Connection If No Diagnostics are Required
Vee

= 6 to 28V

20
9
In 1
10
Swftch 0------1 1n2
Select
11
Inpule o----~:_I In 3
12
In 4
3
Enable
10kA
13

+5V

Cop

0
0

o-+-II/V\r-........

Oo01 J.&F

Out 1

'00"'"

ErrOr +-+----'

I

C

Oul2

::E
-'

Out 3

Out 4

2

18

19

TL/H/ll026-27

Simple protection of the LMD18400 against supply voltage reversal. Loads will be energized through the Intrinsic
diodes In parallel with the power switches. The Schottky diode will add approximately O.2V to the logic Input switching

thresholds and the logic output low levels.
Vee

+12V - ,

.-------~

20
r-_~a...._--.OolJ.&F
I

Switch
Select
Input.

10

In 1

(

OV--t--;-12V

U

Vee

0-------1 In 2
11

Io.o

0-------1 In 3
12

In4

1J.&F

3

Enable

}-------1 Enable
10kn

0
0

13

Outl

'"'"
00

C

Error ~-i----"

::E

2

IN4001

Oul2

-'

18

Thermal Shutdown

Out3
19
Out4

Circuit
Load

Lamp
Load

Gnd Gnd Gnd Gnd

5
Schottky
Diode

recommended

IN5819

-

TL/H/ll026-28

7-90

Applications

!i:
c
....
CD

(Continued)

8

Simple Light "Chaser"

Shift

Register

5 Hz t. 10 Hz 0-....-.....;;;...._.....
Clock

+5V

r~;::====:t::::I:::t::~~=;:=============~~.,

••••

TLlH/ll026-29

Paralleiling switches for higher current capability. Positive temperature coefficient of the switch ON resistance
provides ballasting to evenly share the load current between the switches. Any combination of switches can be
paralleled. Required peak load current will depend upon the motor load. Motor speed control can be provided by a
PWM signal of up to 20 kHz applied to the motor drive input lines.

-

Molor
Drive
Inpul.

Ccp

14

IO.01 }'F

Enablo
Error

+5V

0
0

00

C

Error

Out 1

"'"
::::E

Oul 2

-'

Thermal
Shuldown

Oul 3

Oul 4

Diagnostic
Data Oulpul

1B

19

fI

2A DC
Moto,"

-

7-91

TL/HI11026-30

Section 8
Special Functions

Section 8 Contents
Special Function Circuits Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3
DH0006/DH0006C Current Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6
DH0008 High Voltage, High Current Driver... ....... ..... ....... ... ....... .............
8-10
DH0011 A High Voltage High Current Driver .. .. .. . .. .. .. .. . .. . .. . .. . .. .. .. . .. .. .. .. . .. .
8-14
DH0035/DH0035C PIN Diode Drivers.................................................
8-17
DH0034 High Speed Dual Level Translator ............................................
8-20
8-24
LH0094 Multifunction Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM122/LM322/LM3905 Precision Timers .............................................
8-33
8-45
LM194/LM394 SuperMatch Pairs.......................... .. ..... . .... .. .............
LM195/LM295/LM395 Ultra Reliable Power Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-53
LM555/LM555C Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-64
LM556/LM556C Dual Timers........................................................
8-72
8-76
LM565/LM565C Phase Locked Loops................ ......... ... .... ... .. ...........
8-84
LM566C Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5671LM567C Tone Decoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-88
LM1851 Ground Fault Interrupter. ........................... ... ... .... .. .............
8-94
LM2240 Programmable Timer/Counter ............................. , .... ... ..... ... ... 8-101
LM2907/LM2917 Frequency to Voltage Converters.......... .. .. . ... .. .. .. ............. 8-110
LM3045/LM3046/LM3086 Transistor Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-124
LM3146 High Voltage Transistor Array............. ........ .. ... ....... .. ........... .. 8-129
LMC555 CMOS Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-134
LMC567 Low Power Tone Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-137
LMC568 Low Power Phase-Locked Loop . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 8-141
LP395 Ultra Reliable Power Transistor ................................................ 8-145

8-2

~National

Semiconductor

Special Function Circuits Selection Guide
Communications-Related Building Blocks
PLL's AND TONE DECODERS
General purpose PLL's and tone decoders are available for
applications that include FSK demodulation, tone decoding,
SAP and SCA demodulation, and telemetry reception. Both
bipolar and CMOS devices are offered. Special purpose
PLL's for TV synchronization and FM stereo demodulation
are also available for use in other low frequency signal processing applications.

PLL and Tone Decoder Selection Guide
tLM567

LMC567*
(CMOS LM567)

Typical
Application

Tone
Decoder

Tone
Decoder

PLL

Center Frequency
Range

0.01 Hz500kHz

0.01 Hz500kHz

0.01 Hz500kHz

VCO Control Range
Supply Voltage
Supply Current (Typ)

LMCS68

±7%

±7%

±30%

4.75V-9V

2V-9V

2V-9V

12mA

0.8mA

1.2mA

'The CMOS LMC567 oscillator runs at twice the frequency of the bipolar LM567 oscillator. Refer to the datasheets for additional Information.

t Military qualHled device. For more information, consult the MllHarylAerospace Selection Guide.

TIMERS
General purpose timers are available for generating accurate time delays or oscillation. Both bipolar and CMOS devices are offered.

Timer Selection Guide

Trigger Pulse Relative
to Output Pulse

tLMSSS

LMCSSS*
(CMOS LM5SS)

tLMS56
(Dual LMSSS)

LM2240

Must Be
Shorter

Must Be
Shorter

Must Be
Shorter

Can Be
Longer

Astable

Astable

Astable

Programmable
Monostable/
Astable

4.5V-15V

1.2V-12V

4.5V-15V

4.0V-15.0V

10mA
(Each Timer Section)

4mA -13mA
(Depends on VS)

Typical Application

Supply Voltage
Supply Current
(Typical)

10mA

0.1SmA

'The CMOS LMC555 can handle -10 mA to + 50 mA of output current and the bipolar LM555 can handle up to ± 200 mA of output current.

t Military qualified device. For more information, consult the MilitarylAerospace Selection Guide.

8-3

•

Communications-Related Building Blocks (Continued)
veo AND FUNCTION GENERATOR
The LM566 is a general purpose voltage controlled oscillator which may be used to generate square and triangle
waves. Typical applications include FM modulation, signal
generation, function generation, frequency shift keying, and
tone generation. The LM566 has very linear modulation
characteristics.

Precision-Related Building Blocks
TRANSISTOR ARRAYS
A variety of matched and power transistors are offered.
Transistor Array Selection Guide
tLM394

LM195ltLM395/LP395

LM3046

LM3146

Description

NPN Transistor Pair

Power Transistor

5 NPN Transistors

5 NPN Transistors

Key Features

• Emitter-Base
Voltage Matched
t050/LV
• Current Gain
Matched to 2%

• Collector Current: 1A

• Quiescent Current:
10mA
• Switching Time:
2/Ls

• Emitter-Base
Voltage Matched
to ±5 mV

• Emitter-Base
Voltage Matched
to ±5 mV

• Breakdown Voltages
-V(BR)(CBO): 20V
-V(BR)(CEO): 15V
-V(BR)(CIO): 20V
-V(BR)(EBO): 5V

• Breakdown Voltages
-V(BR)(CBO): 40V
-V(BR)(CEO): 30V
-V(BR)(CIO): 40V
-V(BR)(EBO): 5V

·DC-120MHz

• OC-120 MHz

• Current Limit
• Thermal Limit
• Safe Area
Protection
t MilitaJy qualified device. For more information. consult the MilitarylAerospace Selection Guide.

8-4

Special Converters
A variety of special converters for signal transformation applications are offered.

Special Converters Selection Guide
LHOO91
Converter
Type
Key
Features

True RMS-to-DC

.0.05% Accuracy with
External Trim

tLM331 (Note 1)

LHOO94
Multifunction

•

VOUT=Vy(~~)

Voltage-toFrequency

Frequency-toVoltage

.1 Hz to 100 kHz

• Operates Relay,
Lamp or Other Load
when Input Exceeds
a Selected Rate

m

,

~ m ~ 10,
m Continuously
Adjustable

Frequency Range

0.1
• Uncommitted Amplifier
for Filtering, Gain
or High Crest
Factor Configuration
• True RMS Conversion

LM2907, LM2917

• Split or Single
Supply Operation

• Applications
-Precision Divider,
Multiplier
-Square Root
-Square
-Trigonometric
Function Generator
-Companding
-Linearization
-Control Systems
-Log Amp

Note 1: See the Data Acquisition Linear Devices Databook for datasheet.
tMilitary qualHied device. For more information, consult the Military! Aerospace Selection Guide.

8-5

• Ground Referenced
Tachometer Fully
Protected from Damage
Due to Swings
Above Supply or
Below Ground

I ~Nat1onal
::c
Q

~ semiconductor

::c

DH0006/DH0006C* Current Drivers

I
Q

General Description

Features

The DH0006/DH0006C is an integrated high voltage, high
current driver designed to accept standard DTL or TTL logic
levels and drive a load of up to 400 mA at 28V. AND inputs
are provided along with an Expander connection, should additional gating be required. The addition of an external capacitor provides control of the rise and fall times of the output in order to decrease cold lamp surges or to minimize
electromagnetic interference if long lines are driven.

• Operation from a Single + 1OV to + 45 Power Supply
• Low Standby Power Dissipation of only 35 mW for 28V
Power Supply
• 1.5A, 50 ms, Pulse Current capability

Since one side of the load is normally grounded, there is
less likelihood of false turn-on due to an inadvertent short in
the drive line.

'Prevlously called NHOO06INHOOO6C

Schematic and Connection Diagrams
1
--._------.---------~------._--_.__oV~

10

+--.......-0 OUTPUT
R6

2
INPUT

9
C } RESPONSE
~_________8-o B TillE CONTROL

0---1,,--.
3

INPUT

0---1,,--.

EXPANDER

0-----'

4

6
--t~------O GROUND

'---.. . .

TUK110120-1

Metal Can Package
RESPONSE

nilE
CONTROL
INPUT
INPUT

N.C.

TUK/l0120-2

TOp View
Order Number DHOOO6H or DHOO06CH
See NS Package Number H10F

8-6

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Peak Power Supply Voltage (for 0.1 sec)
Continuous Supply Voltage
Input Voltage

Input Extender Current
5.0mA
Peak Output Current (50 ms On/1 sec Off)
1.5A
Operating Temperature
DHOO06
- 55'C to + 125'C
DHOO06C
O'Cto +70'C
Storage Temperature
- 65'C to + 150'C

60V
45V
5.5V

Electrical Characteristics (Note 1)
Parameter

Min

Conditions

Typ
(Note 2)

Max

Units

Logical "1" Input Voltage

Vee = 45Vt010V

Logical "0" Input Voltage

Vee = 45Vt010V

Logical "1" Output Voltage

Vee = 28V, VIN = 2.0V, lOUT = 400 mA

Logical "0" Output Voltage

Vee = 45V, VIN = 0.8V, RL = 1k

Logical "1" Output Voltage

Vee = 10V, VIN = 2.0V, lOUT = 150 mA

Logical "0" Input Current

Vee = 45V, VIN = 0.4V

-0.8

-1.0

mA

Logical "1" Input Current

Vee = 45V, VIN = 2.4V
Vee = 45V, VIN = 5.5V

0.5

5.0
100

p,A

"Off" Power Supply Current

Vee = 45V, VIN = 0.8V

1.6

2.0

mA

"On" Power Supply Current

Vee = 45V, VIN = 2.0V, lOUT = 0 mA

8

mA

Rise Time

Vee = 28V, RL = 820

2.0
0.8
26.5

27.0
0.001

8.8

V
0.01

9.2

0.10

Fall Time

0.8

p,s

0.26

Ton

2.2
Tofl
Note 1: Unless otherwise specifled,lImlts shown apply fncm -SS'C to + 12S'C for DH0006 and O'C to +70'C for DHOOO6C.
Note 2: Typical values are for 25'C ambient.
Note 3: Power ratings for the TQ-S based on a maximum junction temperature of + 17S'C and 6JA of 210'C/W.

Switching Time Waveforms
90%

-

1,1- -

tf

I-

PULSE
INPUT
50%
10%

-----"

90%

I+TON

10%

tr I-

-

tf I -

~ ~T",\
PULSE OUTPUT

TL/K/l0120-6

8·7

•

I

Typical Performance Characteristics
Maximum Continuous Output
Current for TO-5

Input Threshold Voltage
vs Temperature

~r-~~T-~~~~'

1800

1

g2.0

i§

Logical "0" Input Current

2.2

~

r---.

1.8

~ 1.8

i

!
i

1

~"~~~N

r;;; ,......1

~~

1.4

+IOY Vee

I-

~~LOGICAL

1.2
1.0

''0'' INPUT VOLTAGE

OJI
OJI
~

800
MAXIIIUM CONnNUOUS OUTPUT CURRENT (mA)

I

~

1400

is

1200

~

I

+45VVee

..... ~ ~

1000

P

-55OC

600

I ::

MAX" f- f-

1 1
1
-25 0 25 50 75 100 125

.... ~ P"

"OFF" Supply Current Drain

10

"ON" Supply Current Drain

I I

~.

-55OC

/.1" 1/
l&

~ ~ ....

po

~

'"

10

.AI~

+25OC

~
20

30

o

~

40

-

10

SUPPLY VOLTAGE (V)

Turn Off and Fall Time
01.0,...........................,......,......,.....,.....,

~~

~ ~ 1/

'"

I I
I I

-75 -50 -25 0

50

i!

1.0 I--II--I--,J:

O~~~~~~~~

-75

-so -25

0

25 50 75 100 125

~ l~rf-r.~~~~~~

3 ' .8
I!i 1.8

1.4

25 50 75 100 125

I
I
I

I I
I I

~ 1.4 TC = 1250C

,·,~~O~~~lj

YW r '~U~.~~
Df i "OfF"-

1.2

u

I~
~:

I ~hl-t~~,...,.."'t

i 0JI1-"'f7ol$il'F-H
I:L.LL-'-.......
'--~-'--'-J....J
o 200

TEMPERATURE (OC)

I

I I

Available Output Current
2.0

§!

rr-

Vee=2BV
RL = 684
~ = 10pr
VIN = 3m PULSE
t, 0;10 n• .l

lEIIPEllATURE (OC)

1.3
!:i 1.2

2.0 H-+-b""f-+-+-H

I I

I I

o

Output Saturation Voltage

!i
]

RISE nME

100

g1.8!'""""T...,......,......,.......,r-r....,......,.............,

:>

~

1

+125OC

30
40
20
SUPPLY VOLTAGE (V)

+125OC

.1. J I I
I-TURN ON lIIIE -+--:r.

:y .A ~

+125"C

o

1./I:..-

+25OC

'"

20
30
40
SUPPLY VOLTAGE (V)

400

........ ~

==!!! ~

Turn On and Rise Time

8
-55OC

~ ~ ;;0: ~

o

AMBIENT lEIIPEllATURE (OC)

2.0

~

+25OC

~ 800

i!E

,;

.<

I I I
I I
I I I

TC=-55OC

'" G.2

o

01020304050
SUPPLY VOLTAGE. Vee. (V)

OUTPUT CURRENT. 110-6' (mA)

Turn Off Control

TC = 250C

Turn On Control

t, = 10nl

I

c,. 300",

c,,= 180",

30

g

20

1

'0

c,=9' ..... ~I
I~

:,......

Yee:= 'lIN

Ro.
T.

=68A
=25'C

C1. =10",

o

2.0

01.0

6.0

6.0

10

nME (joo)
TL/K/l0120-7

8-8

r---------------------------------------------------------------------~c

I

Typical Applications
Relay Driver

Lamp Driver with Expanded Inputs

c
:c

vee

Vee

+28V
DTL/TTL {
LOGIC
INPUTS - - - - I

a..-.......-r

EXPANDER INPUT - - _....

~

OUTPUT

RELAY
COIL

327
LAMPS

DTL/TTL
LOGIC
INPUTS
15K

TLlK/l0120-4

\

~USH TO

.i.

TEST
TLlK/l0120-5

•
8-9

~National

~ Semiconductor

DH0008
High Voltage, High Current Driver
General Description

Features

The DH0008 is an integrated high voltage, high current driver, designed to accept standard DTL or TTL input levels and
provide a pulsed load of up to 3A from a continuous supply
voltage up to 45V. AND inputs are provided with an EXPANDER connection, should additional gating be required.

• Operation from a single + 1OV to + 45V power supply
• Low standby power dissipation of only 35 mW for 28V
power supply
• 3.0A, 50 ms, pulse current capability

Since one side of the load is normally grounded, there is
less likelihood of false turn-on due to an inadvertent short in
the drive line.
The high pulse current capability makes the DH0008 ideal
for driving nonlinear resistive loads such as incandescent
lamps. The circuit also requires only one power supply for
circuit functional operation.
'Previously called NHOO08/NH0008C

Schematic and Connection Diagrams
RESPONSE CONTROL

Metal Can Package

8(8)
OUTPUT

Rr
RISE AND
FALL
TIME
CONTROL

INPUT

2(2)

10(10)

INPUTo--t......

1 - -.....-0 OUTPUT

3(3)

TLlK/l0121-2

INPUTo--t......

Top View

4(4)

0---.....
0---+.-+
(6)
INPUT 0-.............

EXPANDER

Order Number DH0008H
See NS Package Number H10F

(5)

INPUT

6(7)

'---....- -....-----Q GROUND
TLlK/l0121-1

Number. In parentheses are pin numbers lor N package only

Switching Sequence
Step

A

B

C

D

1

1

0

1

0

2

1

0

0

1

3

0

1

0

1

4

0

1

1

0

1

1

0

1

0

To reverse the direction use a 4, 3. 2. 1 sequence.

8-10

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Peak Power Supply Voltage (for 0.1 s)
60V
Continuous Supply Voltage
45V
Input Voltage
5.5V
Input Extender Current
5.0mA

Peak Output Current
(50 ms Onl1s Off)
Operating Temperature
DHOOOB
Storage Temperature

3.0A
- 55·C to
- 65·C to

+ 125·C
+ 150·C

Electrical Characteristics (Note 1)
Parameter

Conditions

Min.

= 45Vto 10V
= 45Vto 10V

Vee
Vee

Logical "1'" Output Voltage

Vee = 45V, VIN = 2.0V,IOUT
50 ms Onl1 s Off

= 45V, VIN = 0.8V, RL = 1 kO
= O.BA

Logical "0'" Output Voltage

Vee

Vee = 28V, VIN = 2.0V, lOUT
50 ms On/1 s Off

Logical "0'" Input Current

Vee

Logical "1'" Input Current

Vee
Vee

"Off'" Power Supply Current

Vee
Vee

Rise Time

Vee

Fall Time

Vee

TON

Vee

= 1.6A

= 0.4V
= 2.4V
= 5.5V
45V, VIN = OV
45V, VIN = 2.0V, lOUT = 0 mA
28V, RL = 390, VIN = 5.0V
28V, RL = 390, VIN = 5.0V
28V, RL = 390, VIN = 5.0V
28V, RL = 390, VIN = 5.0V

43

43.5
0.02

26.5

Units
V

O.B

Logical "1'" Output Voltage

"On" Power Supply Current

Max.

2.0

Logical "1'" Input Voltage
Logical "0'" Input Voltage

=
=
=
=
=
=
=
=
=

Typ.
(Note 2)

V
V

0.1

V
V

27.1

45V, VIN

-0.8

-1.0

mA

45V, VIN
45V, VIN

0.5

5.0
100

,...A

2.0

mA

8.0

mA

1.6

0.2

,...s

3.0

,...s

0.4

,...s

7.0
Vee
TOFF
Note 1: Unless otherwise specified limits shown apply from - S5"C to + 125"C for OHOOoe and O"C to + 70"C for DHOOO8C.
Note 2: Typical values are 2S"C.
Note 3: Power ratings for the T()"S based on a maximum junction temperature of + 17S"C and a 9JA of 210"C/W.

,...s

Switching Time Waveforms
90"

-

t,.~

-

It~

PULSE
INPUT

50"
10"

---.I

- --

=lit -

t,.

90"

.TON
10"

\I

~"~
I-Torr

PULSE OUTPUT

TL/K/10121-6

B-11

§::c

Typical Performance Characteristics

c

Maximum Continuous Output
Current for T0-5 Package

Maximum Continuous Output
Current for Molded DIP

Available Output Current
I
I

I
I

I

Tc~ 1~5~
IV.

Tc· ....1

I 'I
Tc = -55CC
I
~

200

100

~

800

MAXIMUM CONTINUOUS OUlPUT CURRENT (mA)

-- _

.....

i

~

'J1N.±

i

Input Threshold Voltage
vs Tempereture

Logical "0" Input Current

2.2

I

~ 2.0

+25CC

"

1..4
1.2
m
j!;

i

os

I

0.6

!

...d~

~
o
10

~~

l"-

~ po'

....... ~

-55CC

A f'
~A
e:;1'

'"

20
30
SUPPLY VOLTAGE (V)

Turn ON Control

Turn OFF and Fall Times

v~

Vex = 28V
RL = 3911
CL = 10pF
VIN = 3.OV PULSE

140

12.0

:!10.0

+125CC

+25CC

~

" :S 10 n•

20
SUPPLY VOLTAGE (V)

........ 1'

6.0

~"

40

-75

50

I.L.L

T, = appl'OlClmaloly 10 no

JI

~

~

20

I

I

~It~~
d" •

1 ' '...1'1
CA

10

IIr

o

I

I

Vee = 28V
RL = 3911
= 10pF
TA = 25CC
~ = 5.1 kll

ct.

-

-25

TURN OFT nME

..J,....H"
"FALL TIME

+25

+75

+125

TEMPERATURE (CC)

Turn ON and Rise Time
700
100

.L.L

2 4 6 8 10 12 14 16 18
TIME (PO)

f-

o

Turn OFF Control

.L I I

./

80

2.0

10

50

16.0

P
o

+125CC

SUPPLY VOLTAGE (V)

./. :;.-' l;'

i.,...-

+125CC

~ ~ "<::

30

20

25 50 75 100 125

OFF Supply Current Drain

./V

"

-

...-:::

....

N.. ~ P

I

0

-50 -25

-55"1:

.......

CUA~J

LOGICAL
"0" INPUT VOLTAGE MAX "

1.0

+25CC

f- r'"'" f:::::: t-....

+IOV Vex

AMBIENT TEMPERATURE (CC)

"
t>- .-<."
I);

I

~~ 1.6 -. ~"~~~~~~N
.I
I
I
l"'l::!:::::5 +45V Vee
IS

ON Supply Current Drain

]:

102O~.w50

1100

SUPPLY VOLTAGE, Vee (V)

OUlPUT CURRENT (A)

-SSCC

1200

PULSE CONDITlON
1 MS "ON"
100 MS "OFF" -

I

MAXIMUM CONTINUOUS OUTPUT CURRENT (mA)

Output Saturation Voltage
1.1
TA = -55CC
~ 1.0
~
.9
~
)..1"" :>+-"T
1:~
!:i S
TA
=
7O"C
~ .7
...-:~
z
TA = 25CCI I
~
S
'Ii TA = O"C
I I I
.5
TA = 12SCC
..4
Vee =
I
PULSE COIlDlT1ON
J
TON =I.0ooc
I
.2
Torr = 10 HeI
.1
o j .2 J ..4 .5 .6 3 S .9 W

800

I

I
I

Vex = 28V
RL = 3911
= 10pF
VIN = 3.0V PULSE
I, :S10 n'l

ct.

I

i-'

TURN ON nME

I

200

RISE nME'-

100

I
-so -25

0 +25 +SO +75 +100 +125

TGtPERATURE (CC)
TL/K/l0121-6

8·12

Typical Applications
Controller for Closed Loop Stepper Motor
A

B

C

+28

D

VDC--+-~----~~--~--'----+--'

BIFILAR
STEPPER
MOTOR

0--·

DTL
OR

TTL
CLOCK
TL/K/10121-4

8·13

~.r----------------------------------------------------------------'

.-

~ ~National

CI

~ Semiconductor

DH0011A High Voltage High Current Driver
General Description
The DH0011 A High Voltage, High Current Driver family con·
sists of hybrid integrated circuits which provide a wide range
of variations in temperature range, package, and output cur·
rent drive capability.
Applications include driving lamps, relays, cores, and

other devices requiring several hundred milliamp currents at
voltages up to SOV. Logic flexibility is provided through a 4input NAND gate, a NOR Input and an input which bypasses
the gating and connects to the base of the output transistor.

Logic Diagram
Vee
10

TLlK/6863-1

Ordering Information
NSC Designation

Package

DHOO11AH

H10C

Temperature Range
- SsoC to

8·14

+ 125"C

Output
Capability
SOOmA

C

:::t:

Absolute Maximum Ratings
8V

Vee
Collector Voltage (Output)

50V

Input Reverse Current

800mW

Power Dissipation

1.0mA

Operating Temperature Range

-55'Cto + 125'C

Storage Temperature

- 65'C to + 150'C

Electrical Characteristics
Test Pin

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

VIH

VIH

VIH

Pin6

Pln7

Pin 8

1

VIH

GND

GND

IOL1

2

VIL

GND

GND

IOL1

3

VIL

GND

4

VIL

5

VIL

Pin 9

Min

Max

Pin 10

Sense

Vee

Va

VOL1

Vee

Va

VOL1

Vee

Va

VOL2
VOL2

VIL

IOL2

GND

IOL2

Vee

Va

GND

IOL2

Vee

Va

VOL2

Vee

Va

VOL2

Vee

Va

VOL2

6

VIL

GND

IOL2

7

GND

GND

IOL2

VIH

GND

GND

GND

GND

Vee

11

IR

9

GND

VR

GND

GND

GND

Vee

12

IR

10

GND

GND

VR

GND

GND

Vee

13

IR

11

GND

GND

GND

VR

GND

Vee

14

IR

Vee

19

IR
-IF

8

VR

12

GND

13

VF

VR

VR

VR

GND

Vee

11

14

VR

VF

VR

VR

GND

Vee

12

-IF

15

VR

VR

VF

VR

GND

Vee

13

-IF

16

VR

VR

VR

VF

GND

Vee

14

-IF

GND

GND

Vee

19

-IF

17
18

VR

VF

GND

GND

GND

GND

Vee

Va

Vee

la

GND

VPD

110

IpD

GND

VMAX

'10

IMAX

22·

GND

VPD

tON

23·

GND

VPD

tOFF

19

GND

20
21

GND

Vox

VOH
lox

·See Test Circuits and Waveforms

Forcing Functions
Parameter

-55'C

+25'C

+ 125'C

Vee

5.0

5.0

5.0

Units
V

VPD

5.0

VMAX

8.0

V
V
V

VIL

0.85

0.85

0.85

V

VIH

1.9

1.8

1.6

V
V

VR

4.5

4.5

4.5

VF

0.45

0.45

0.45

V

IOL1

400

400

400

mA

IOL2

20

20

20

mA

50.0

50.0

V

Vox

50.0

8-15

8....
....
»

Limits
-55"C

Parameter

+25"C

Min

Max

Min

+ 125"C
Min

Max

Units
Max

VOLI

0.6

0.6

0.6

V

VOL2

0.45

0.45

0.45

V

VOH

1.95

1.85

1.65

V

60

60

p.A

1.6

1.6

rnA

lox

5.0

200

Ipo

12.2

rnA

IMAX

10

rnA

toN

160

ns

toFF

220

ns

IR

1.6

-IF

p.A

Switching Time Test Circuit
4 SOY
AI-IlIOn
--OUTPUT

"111'Vee' SV
PUW
BEl.

f'·····-

d....)

FRED.' III kHz
DUTY CYCLE - 511

" ... PlUaID

W.

'='

TUK/6863-2

Switching Time Waveforms
Typical Switching Times

'''UT
IV

\
r-,rv ):

1

IV

.........,--1

•
HV

,

IV

i\

j

our

!

I

IV

I--"H-I

i.;"

III

i.;o
"\Ott

III

~

....

II

L
~

...

\0-

I

TL/K/6863-3

I
.....c

n·c

12I·C

TEMPERATURE C·CI
TL/K/6863-4

8-16

I

~National

~ Semiconductor

DH0035/DH0035C
PIN Diode Driver

w

~

• Short propagation delay-10 ns
• High repetition rat~ MHz

General Description
The DHOO35/DH0035C is a high speed digital driver designed to drive PIN diodes in RF modulators and switches.
The device is used in conjunction with an input buffer such
as the DM7830/DM8830 or DM5440/DM7440.

The DH0035/DH0035C is capable of driving a variety of PIN
diode types including parallel, serial, anode grounded and
cathode grounded. For additional information, see AN-49
PIN Diode Drivers.
The DH0035 is guaranteed over the temperature range
- 55°C to + 125°C whereas the DH0035C is guaranteed
from O°C to + 85°C.

Features
• Large output voltage swing-30V
• Peak output current in excess of 1A
• Inputs TTLlDTL compatible

Schematic and Connection Diagrams
Metal Can Package

INPUT A COWP

Rl

6

INPUT A 07_",25",0_+-_

CR2

R2
INPUT B ().3.....y3"'k

_+-....,.

CR3
TL/K/10124-2

Top View

1 I{" 2

Order Number DH0035G-MIL or DHOO35CG
See NS Package Number G12B

TLlK/10124-1

8-17

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V- Supply Voltage Differential (Pin 5 to Pin 1 or 2)
40V
V+ Supply Voltage Differential (Pin 1 or 2 to Pin 8 or 9) 30V
±75mA
Input Current (Pin 3 or 7)
Peak Output Current
±1.0A

Power Dissipation (Note 3)
Storage Temperature Range
Operating Temperature Range
DH0035
DH0035C
Lead Temperature (Soldering, 10 sec.)

1.5W
-S5°C to + 150'C
- 55°C to + 125°C
O'Cto +85°C
300'C

Electrical Characteristics (Notes 1 and 2)
Parameter

Limits

Conditions

= -8V, RL = 1000
= +8V, RL = 1000
lOUT = 100 mA
lOUT = 100 mA
VIN = OV, RL = 00

Input Logic "1" Threshold

VOUT

Input Logic "0" Threshold

VOUT

Positive Output Swing
Negative Output Swing
Positive Short Circuit Current

(Pulse Test, Duty Cycle

Typ

Max

1.0

2.0

0.4

O.S

7.0

+8.0

s: 3%)

VIN = 1.5V, liN = 50 mA, RL = 00
(Pulse Test, Duty Cycle s: 3%)

Turn-On Delay

= 1.5V, VOUT = -3V
= 1.5V, VOUT = +3V
VIN = 1.5V

V
V
V

-8.0

Negative Short Circuit Current

Turn-Off Delay

Units

Min

-7.0

V

400

800

mA

800

1000

mA

VIN

10

15

ns

VIN

15

30

ns

On Supply Current
Note 1: Unless otherwise specHled, these specifications apply for y+ = 10.OY, Y
the DH0035, and O"C to + 85'C for the DHOO35C.
Note 2: All typical values are for TA = 25"C.
Note 3: Derate linearly at 10 mWI"C for ambient temperatures above 25"C.

=

45
SO
mA
-10.OY,pln5grounded,overlhetemperaturerange -55"Cto + I 25"C for

Typical Applications
Grounded Cathode Design

y+ = 10V

.uulluu_.
I·
I
I
I
I
I

6.------u

l..ri
I
200.
I

10

1-

I
I
lij

I
I
I

I
I
I

IN

·-----1-----1/2 DM8830

-

~C~ ~

62~

5.0V

L

I
I

P'j' 7 1

..-

250p'

111

- 1: 12 1
'..r------.
PIN .,,.

I
I

31
20P'* 4i

9_.

r-

:: DIODE
II SWITCH

I
I
I
I

'-:g---T]" .;~-.
DH0035

0.1J."

V-=-10V

_

-

Note: Cathode grounded PIN diode: Rp = 62nllmlts diode forward current to 100 mAo Typical switching for
HP33S04A, RF turn-on 25 ns, turn·off 5 ns. C2 = 250 pF, Rp = on, CI = O.IF.

8-18

TLlKI10124-3

c

::z::

Typical Applications (Continued)

~

.......

c

Grounded Anode Design

::z::

S

5.0V

CII

o

_----lJ------.
LOGIC

,

INPUT_.,---...._,

,,

20pF

------1------

, 1/2 DW7830!DW8830 ,

U

,

::

DIODE

I

, ._~_~_'!.'~.;_
;!l~_J
RII
564

C2_
1200pF-

V-=-10V

TL/K/l0124-4

Note: Anode Grounded PIN diode: RM ~ 56n limits diode lorward current to 100 rnA. Typical swi1ching lor
HP33622A, RF turn-on 5 ns: turn-oll 4 ns. Cl ~ 470 pF, C2 ~ 0.1 ,.F, RM = on.

Alternate Current Limiting

v+

TO
>C~H~M~-PIN

DIODE

v+ - 2 Iv-I- 2
R=--or--~

If

TL/K/l0124-5

8-19

-- -----

~National

~ Semiconductor

DH0034
High Speed Dual Level Translator
General Description

Features

The DH0034 is a high speed level translator suitable for
interfacing to MOS or junction FET analog switches. It may
also be used as a universal logic level shifter capable of
accepting TTL/DTL input levels and shifting to CML, MOS,
or SLT levels.

•
•
•
•

Fast switching, tpdO: typically 15 ns; tpd1: typically 35 ns
Large output voltage range: 25V
Input is TTLlDTL compatible
Low output leakage: typically 0.1 ",A

Schematic and Connection Diagrams
Vee

Metal Can Package

y. Circu~ Shown
GND

vTUK/10122-1

GND
TUK/10122-2

Top View
Order Number DH0034H-MIL
See NS Package Number H10F

Dual-In-Line Package
14

NC

13

A1

B1
NC

Vee
A2
B2

NC

V-

V-

OUTPUT 1

OUTPUT 2

GND

NC
TL/K/10122-3

Top View
Order Number DH0034D
See NS Package Number D14D

8·20

C
%

g

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Vee Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
Differential Supply Voltage
Maximum Output Current

Input Voltage
Operating Temperature Range
DH0034
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

7.0V
-30V
+25V
25V
100mA

+5.5V
- 55·C to + 125·C
-65·C to 150·C
300·C

Electrical Characteristics (See Notes 1 and 2)
Parameter

DHOO34

Conditions
Min

Typ

Units
Max

Logical "1"
Input Voltage

Vee = 4.5V
Vee = 4.75V

Logical "0"
Input Voltage

Vee = 5.5V
Vee = 5.25V

0.8

Logical "1"
Input Current

Vee = 5.5V, VIN = 2.4V
Vee = 5.25V, VIN = 2.4V

40

Logical "1"
Input Current

Vee = 5.5V, VIN = 5.5V
Vee = 5.25V, VIN = 5.5V

1.0

Logical "0"
Input Current

Vee = 5.5V, VIN = 0.4V
Vee = 5.25V, VIN = 0.4V

-1.6

Power Supply
Current
LogiC "0"

Vee = 5.5V, VIN = 4.5V
Vee = 5.25V, VIN = 4.5V
(Note 3)

30

38

mA

Power Supply
Current
Logic "1"

Vee = 5.5V, VIN = OV
Vee = 5.25V, VIN = OV
(Note 3)

37

48

mA

Logical "0"
Output Voltage

Vee = 4.5V, lOUT = 100 mA
Vee = 4.5V, lOUT = 50 mA

V- + 0.50
V- + 0.3

V- + 0.50

Output Leakage
Current

Vee = 5.5V, VIN = 0.8V
V+ - V- = 25V

0.1

5.0

Transition Time to
Logical "0"

Vee = 5.0V, V3 = OV, TA = 25·C
V- = 25V, RL = 5100

15

25

2.0

V
V
/loA
mA
mA

V
/loA
ns

Vee = 5.0V, TA = 25·C
Transition Time to
35
75
ns
V- = -25V, RL = 5100
Logical "1"
Note 1: The specifications apply over the temperature renge - 55°C to + 125°C for the DH0034 with a 51 on resistor connected between output and ground, and
V- connected to - 25V, unless otherwise specified.
Note 2: All typical values are for TA = 25°C.
Note 3: Current measured is total drawn from Vce supply.
Note 4: Power rating for the T0-5 metal can based on a maximum junction tamperature of 175°C and 8JA = 210"C/W.
Note 5: Power rating for the Cavity DIP besed on a maximum junction temperature of 175°C end 8JA = 180"C/W.

8·21

...w

~ r-------------------------------------------------------------------~

~

2. Recommended Output Voltage Swing

Theory of Operation

The graph shows boundary conditions which govern proper
operation of the DH0034. The range of operation for the
negative supply Is shown on the X axis and must be
between -3Vand -25V. The allowable range for the pos·
itive supply is governed by the value chosen for V-. V+
may be selected by drawing a vertical line through the se·
lected value for V- and terminated by the boundaries of the
operating region. For example, a value of V - equal to - BV
would dictate values of V+ between -5V and +19V. In
general, it is desirable to maintain at least 5V difference
between the supplies.

When both inputs of the DH0034 are raised to logic "1", the
input AND gate is turned "on" allowing 01's emitter to become forward biased. 01 provides a level shift and constant
output current. The collector current is essentially the same
as the emitter which is given by

Vee - Vse
R1
Approximately 7.0 mA flows out of 01's collector.
About 2 mA of 01's collector current is drawn off by pull
down resistor, R2. The balance, 5 mA, is available as base
drive to 02 and to charge its associated Miller capacitance.
The output is pulled to within a VSAT of V-. When either (or
both) input to the DH0034 is lowered to logic "0", the AND
gate output drops to 0.2V turning 01 off. Deprived of base
drive 02 rapidly turns off causing the output to rise to the V3
supply voltage. Since 02's emitter operates between O.BV
and 0.2V, the speed of the DHOO34 is greatly enhanced.

25
V-<-3V
S 20 Y+-V- :S25V
.:!!. 15

...
...'";:!

10

~

5

~

t

0
-5

'"
~
'"~

-20

:::>

~

OPERATING REGION _ _
~

... -10

Applications Information
1. Paralleling the Outputs

-15

-25

The outputs of the DH0034 may be paralleled to increase
output drive capability or to accomplish the "wire OR". In
order to prevent current hogging by one output tranSistor or
the other, resistors of 2.0/100 mA value should be inserted
between the emitters of the output transistors and the minus
supply.

-24

-18

-12

rl-.., f- 50%

~

5V

50%

O-..J

-,
OUTPUT

,r - - - O V

-'k-50%

1\
""'1--1-

0
TLlK/10122-6

Switching Time Waveforms
INPUT

-6

NEGATIVE SUPPLY VOLTAGE (-V)

-f-50%

I ----25V

-tpd2TL/K/10122-7

8·22

.-----------------------------------------------------------------,c
::I:
Typical Applications

2N4931

ANALOG
IN

I

TTL to IBM (SLT) Logic Levels

5 MHz Analog Switch

5V

._______ 1______ .

ANALOG
OUT

510 -

5V

>C)--.....-

OUTPUT 1

-3V
">4o-";"'-1_0UTPUT 2
I
I

510
-15

DH0034

I
I
I

510

-------:1:------

+10V
TL/K/l0122-4

TL/K/l0122-5

8-23

I ~National

~ semiconductor

LH0094 Multifunction Converter
General Description
• Minimum component count
• Internal matched resistor pair for setting m = 2 and
m=0.5

The LH0094 multifunction converter generates an output
voltage per the transfer function:
Eo = Vy

(~~)m, 0.1 :s: m:s: 10, m continuously adjustable

Applications

m is set by 2 resistors.

•
•
•
•
•
•
•
•

Features
•
•
•
•

Low cost
Versatile
High accuracy-0.05%
Wide supply range - ± 5V to ± 22V

Precision divider, multiplier
Square root
Square
Trigonometric function generator
Companding
Linearization
Control systems
Log amp

Block and Connection Diagrams

Dual·ln·L1ne Package
A3-

v·

Va

V.

Al-

GNO

V,

VA

V,

Y.
E.

LHOiIM

Yy

Ra

Order Number LH0094CD
See NS Package Number D16D
E.

Ve

Vy

A4-

V-

RA

ReOMMON

Ra

TOP VIEW

Simplified Schematic

1

E.

6'~
g ~.
1ft

loa

TL/H/5695-1

8·24

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
±22V

Operating Temperature Range
LH0094CD

Input Voltage
Output Short-Circuit Duration

Lead Temperature
(Soldering, 10 seconds)

- 25"C to

Storage Temperature Range
LH0094CD

±22V
Continuous

- 55°C to

+ 85°C

+ 125°C
26O"C

Electrical Characteristics
Vs = ± 15V, TA = 25°C unless otherwise specified. Transfer function: Eo = Vy V:;; 0.1
Parameter

~m~

10; OV

~ Vx, Vy, Vz ~ 10V

LHOO94C

Conditions
Min

Unlta

Typ

Max

0.45
0.1
0.2

0.9

0.45
0.1
0.2

0.9

%F.S.
%F.S.
mV/oC

0.45
0.15

0.9

%F.S.
%F.S.

2.0

%F.S.
%F.S.

ACCURACY
EQ=VZVy (0.03~Vy~10V; 0.01 ~Vz~10V)
(Figure 2)
(Figure 3)
vs. Temperature
Eo=10VzlVx
(Figure 4), 0.5~Vx~10; 0.01 ~Vz~10)
(Figure 5), (0.1 ~Vx~10; 0.01 ~Vz~10)
vs. Temperature
EO = 10.JiiZTf0
(FigureS), (0.03~Vz~10
(Figure 9), (0.01 ~Vz~10
EO=10 (Vz/10)2 (0.1 ~Vz~10)
(Figure 6)
(Figure 7)
Eo="10Vz; 5.0mV~Vz~ 10V, (Figure 10)

Multiply
Untrimmed
External Trim
Divide
Untrimmed
External Trim
Square Root
Untrimmed
External Trim
Square
Untrimmed
External Trim
Low Level
Square Root
Exponential
Circuits

1.0
0.15

m=0.2, Eo= 10 (Vz/10)2 (Figure 11). (0.1 ~Vz~10)
m=5.0, EO= 10 (Vz/10)5 (Figure 11). (1.0~Vz~10)

%F.S.
(10V)
%F.S.
mVloC

0.05

%F.S.

0.08
0.08

%F.S.
%F.S.

OUTPUT OFFSET

I

I

Vx=10V, V,- 'Vz=O

AC CHARACTERISTICS
3 dB Bandwidth
Noise

I

m= 1.0, Vx= 10V, Vy=0.1 Vrms
10 Hz to 1.0 kHz, m=1.0, Vy=Vz=OV
Vx=10V
Vx=O.1V

5.0

I

10

I

mV

10

kHz

100
300

ILV/rms
ILV/rms

EXPONENT
m

I

I

INPUT CHARACTERISTICS
Input Voltage
Input Impedance

(For Rated Performance)
(All Inputs)

0.2 to
5.0

0
98

I

0.1 to
10

I

I

100

10

V
kO

12
1.0
3.0

V
0
mA

OUTPUT CHARACTERISTICS
Output Swing
Output Impedance
Supply Current

(RL~10k)

10

(Vs= ±15V) (Note 1)

Note 1: Refer to RETSOO94D drawing for specifications of the military LH00940 version.

8-25

5.0

Applications Information
(b)m<1

GENERAL INFORMATION
Power supply bypass capacitors (0.1 JAoF) are recommended
for all applications.
The LH0094 series is deSigned for positive input signals
only. However, negative input up to the supply voltage will
not damage the device.
A clamp diode (Figure 1) is recommended for those applications in which the inputs may be subjected to open circuit or
negative input signals.
For basic applications (multiply, divide, square, square root)
it is possible to use the device without any external adjustments or components. Two matched resistors are provided
internally to set m for square or square root.
When using external resistors to set m, such reSistors
should be as close to the device as possible.

m-~R1+R2"'20011
R1+R2
(c)m>1

~3

TL/H/5695-4

ACCURACY (ERROR)
The accuracy of the LH0094 is specified for both externally
adjusted and unadjusted cases.
Although it is customary to specify the errors in percent of
full-scale (10V), It is seen from the typical performance
curves that the actual errors are in percent of reading. Thus,
the specified errors are overly conservative for small input
voltages. An example of this Is the LH0094 used In the multiplication mode. The specified typical error Is 0.250/0 of fullscale (25 mV). As seen from the curve, the unadjusted error
Is :::: 25 mV at 10V Input, but the error Is less than 10 mV for
Inputs up to 1V~ Note also that If either the multiplicand or
the multiplier Is at less than 10V, (5V for example) the unadjusted error is less. Thus, the errors specified are at fullscale--the worst case.
The LH0094 is designed such that the user Is able to externally adjust the gain and offset of the device--thus trim out
all of the errors of conversion. In most applications, the gain
adjustment is the only external trim needed for super accuracy-except in division mode, where a denominator offset
adjust Is needed for small denominator voltages.

SELECTION OF RESISTORS TO SET m
Internal Matched Resistors
RA and Rs are matched internal resistors. They are
1000 ± 100/0, but matched to 0.10/0.
(a)m=2·

~3
8

(b)m=O.S·

~r
8

R1+R2
R2

m=--

3
RA

-'"

EXPONENTS
The LH0094 is capable of performing roots to 0.1 and powers up to 10. However, care should be taken when applying
these exponent-otherwise, results may be misinterpreted.
For example, consider the V,oth power of a number: i.e.,
0.001 raised to 0.1 power is 0.5011; 0.1 raised to the 0.1
power Is 0.7943; and 10 raised to the 0.1 power Is 1.2589.
Thus, It is seen that while the input has changed 4 decades,
the output has only changed a little more than a factor of 2.
It is also seen that with as little as 1 mV of offset, the output
will also be greater than zero with zero Input.

TLlH/S895-2

'No external reslslors required, strap aslndlcaled

Extsmal Reslstora
The exponent Is set by 2 external resistors or It may be
continuously varied by a single trim pot. (Rl + R2S:5000.
(a) m= 1

TL/H/S695-3

8-26

Applications Information (Continued)
1. CLAMP DIODE CONNECTION

Va
V+

01
lN914

--i+--+--..

EO=Vy

LH0094

(~) m

0.I:S:m:S:l0
Note. This clamp diode connection is
recommended for those applicetions
In which the Inputs may be subject to
open circuit or negallve signals.

Eo
Vyo---..I

FIGURE 1. Clamp Diode Connection
2. MULTIPLY
V+

0.4

MULTIPLY
Eo' VyVZ

to

0.3

VXC~+-______~~~~

10.00V

WITHOUT EXTERNAL
ADJUSTMENTS

...

;;j

r-+-oVz

!!
oc
oc
oc

llJ

0.2

VY"OV

co

1.1

III

LH0D94

0.1

.....

o

Eo. Vy Vz

100-+......z
Vy 0-+------....

~

o

~

-SV

'Y"'1I1

0.1

10
Vz(V)

FIGURE 2b. Typical Performance of
LH0094In Multiply Mode Without
External Adjustment

FIGURE 2a. LH0094 Used to Multiply (No External Adjustment)

DI

INB14

lOY REF
(LH0070 OR
LH0075)

0----------------------------+r--*-....
Eo= Vy Vz
10

RI
2M

E =~
o
10

m=1

Trim Procedure

0----+-.........

Sel Vz=Vy=10V
Adiust R2 until oulpul= 10.000V

R2
IDle

TL/H/5695-S

FIGURE 3. Precision Multiplier (O.02% Typ) with 1 External Adjustment

8-27

EI

~

.~

,---------------------------------------------------------------------------------,
Applications Information
a.DIVIDE

(Continued)
01
IN814

Ir--""--

v+

DA r--~mn""-....,.."

DIVIDE

I

E.-IO !!
Vx
WITHOUT EXTERNAL

0.3

I

~

g

ADJlili~~TS +-H+++HI-+++H-M
~'~'~.

0.2

Vx -0.5Vj

ffi
LH0084

/
0.1

Vx=IV./
I I lUI':

~

1~lyx'IOV

o 1i=':~l::I::!IIIllL"...L.Jl.1JJ1lllllLlIlll-LJlJ.JJLLUJJ
o
0.1
10

E.'IO~o-+"'"
Vx

.Vz(V)

Vy ' 10V REF 0----..1
FIGURE 48. LHOO94 Used to Divide (No External Adjustment)

FIGURE 4b. Typical Performance,
Divide Mode,
Without External Adjustments

-.•

_

*01

- + IN914
•

r""---~-~-+-+-~-~

Trim Procedures
Apply 10V to Vy, O.1V to Vx and Vz.
Adjust R3 until Eo=10.000V.

Vz

Apply 10.000V to all inputs.
Adjust R2 until Eo = 10.000V

Repeat procedure.

RI
2M

m-I

0----++.....

Eo" ID!!
Vx
R2
10V REF
10k
ILHDD7D OR 0-......""'",.,.....- - -.....
LHDD76)
FIGURE 5. Precision Divider (0.05% Typ)
4. SQUARE
01
IN814

EO=Vy

(~) 2

0.5

r==----...---f+-Vxo-----t--,

0.4

E.=IO(~)

0.3

WITHOUT EXTERNAL
ADJUSTMENT

;j
Vz

...

~

ac
co
ac
ac
III

I

o

J

I

0.2
0.1

E.
Vyo--_'"

II

SQUARING 2

-

~~

o

I

2

~"'"

3 4 6

V
6 7 8 8 10

V.IV)

TLlH/5695-6
FIGURE 6b. Squaring Mode without
External Adjustment

FIGURE 6a. Basic Connection or LH0094 (m = 2) without
External Adjustment Using Internal Resistors to Set m

8-28

Applications Information

(Continued)
Dt
tN9t4

4. SQUARE (Continued)

r----+---K---

-

r---+-------O~Ov REF

..-+-oVz
RI
2M

E.o-----+~-~

R2

Trim Procedure

IIHI

10V

R~Jo--W~"--""""

Apply 1OV to Vz
Adjust R2 for 10.000V at output

FIGURE 7. Precision Squaring Circuit (0.15% Typ)
5. SQUARE ROOT

v+

0.4

..

0.3

ac:
co
ac:
ac:

0.2

...,

Vz

/

0.1

Eo-Vy

(V;;Vz)'h

FIGURE 8a. Basic Connection of LH0094 (m = 0.5)
without External Adjustment Using Internal Resistors
to Set m

o

0.1

10

VZ(V)
FIGURE 8b. Typical Performance Curve Square Root,
No External Adjustment

01
Vx

V

IJ

III

E.o--+-"
Vyo--+---

Vz

Ii

WITHOUT EXTERNAL
ADJUSTMENT

II!

~

n

SQROO
E.=tO

v.

r-

CI-_ _ _ _ _ _ _ _ _..,'N.t\lr

+

tOVREF

...-t-O Vz
EO=lft

f!j

"V1o

Rt

2M
Trim Procedure

E.o----+.......

Apply 1OV to all Inputs.

R2
tOk

Adjust R2 until EO-l0.000V

tOV R~¥ o-.J\IVY",-_..J
Tl/H/5e95-7

FIGURE 9. Precision Square Rooter (0.15% Typ)
8-29

Applications Information

(Continued)

6. LOW LEVEL SQUARE ROOT

01
11914

r--*--

E.o---~------------~_,

v.
m=1

Eo=10~

Eo

EQ2=10VZ
.'. Eo =JiOiiZ
5 mV:!:VZ:!:10V

RZ
10V
10k
(LH0070 o--'\I'V\i,....,.-4....DR LH0075)

.....
Trim Procedure
Se1 Vz=10V
Adjust R2 until output= 10.000V

FIGURE 10. 3-Decade Precision Square Root Circuit Using the LHOO94 with m = 1

Typical Applications
01
IN914

VxO~

______________

10V

r--*--

~~~

_++-oV.

V m

E. -10 ( I;)

Eo=10

(~) m

TrIm Procedure

E.

Apply 10V to all inputs
Adjust R2 for output of 10.000V

o--------f--'"

Vyo-~~~-t~--.....

10V

RZ
10k

Form=0.2

~I' ~14

RI

~3

Form=5
RZ

RZ

~-

~IO

RI

~14 ~3

~
-

R2
m=Fi1+ii2' Choose Rl =2000
.'.R2=500

TUH/5695-8

m=Rl +R2· Choose R2=500
R2 •
.'.Rl=2000

FIGURE 11. Precision Exponentlator (m = 0.2 to 5)

8-30

Typical Applications

(Continued)
R

>_,--oVO

IV110---4.......
LHOO94

v.
..-----+-OOIV21

VO+V2

Note. The LH0094 may be used to generate a voltage equivalent to:

VO=~
V1 2
VO= V2+V0+"V2
V02+VO V2=V2 VO+V22+VI2
V02=VI 2+V22
:.VO=~

Vl.V20 ..... 10V

R'" 10k
National Semiconductor resistor array RA08-10k Is recommended

FIGURE 12. Vector Magnitude Function

""...-0 Eo

TL/H/5895-9
Note. Tha LH0094 may be used in direct measurement of gas flow.
FIOW=krr

Eo=10~XVAP
VT

Eo

E02=10 VpVIJ.P

VT

EO=~10 vp:rIJ.P
P = Absolute pressure
T = Absolute temperature
aP= Pressure drop

FIGURE 13. Ma•• Ga. Flow Circuit

8·31
----~--------

Typical Applications

(Continued)

13

y.o-"",,\M_. .-t
1I11III

-

R

R2

r------+---oYB= ELOG
RI

y+

Ex

R2

0---+.....,1-.,

Ez

-

LHOO94

Y-

TL/H/5695-l0

Note. The LHoo94 may also be used to generate the Log
of a ratio of 2 voltages. The output Is taken from pin 14 of
the LH0094 for the Log application.

ELOG=KI~in~
q

Vx

whera KI = RI + R2
R2
I
IIKI=KT/q/nIO

then ELOG = Logl0

Vz

Vx

Rl=15.9 R2
R2:::: 4000
R2 must be a thermistor with a tempco of '" O.33%I"C to
be oompensated over temperatura.

FIGURE 14. Log Amp Application

8-32

~National

~ Semiconductor

LM 122/LM322/LM3905 Precision Timers
General Description
The LM122 series are precision timers that offer great versatility with high accuracy. They operate with unregulated
supplies from 4.5V to 40V while maintaining constant timing
periods from microseconds to hours. Internal logic and regulator circuits complement the basic timing function
enabling the LM122 series to operate in many different applications with a minimum of external components.
The output of the timer is a floating transistor with built in
current limiting. It can drive either ground referred or supply
referred loads up to 40V and 50 mAo The floating nature of
this output makes it ideal for interfacing, lamp or relay driving, and signal conditioning where an open collector or emitter is required. A "logic reverse" circuit can be programmed
by the user to make the output transistor either "on" or
"off" during the timing period.
The trigger input to the LM 122 series has a threshold of
1.6V independent of supply voltage, but it is fully protected
against inputs as high as ± 40V-even when using a 5V
supply. The circuitry reacts only to the rising edge of the
trigger Signal, and is immune to any trigger voltage during
the timing periods.
An internal 3.15V regulator is included in the timer to reject
supply voltage changes and to provide the user with a convenient reference for applications other than a basic timer.
External loads up to 5 mA can be driven by the regulator. An
internal 2V divider between the reference and ground sets
the timing period to 1 RC. The timing period can be voltage
controlled by driving this divider with an external source
through the VADJ pin. Timing ratios of 50:1 can be easily
achieved.

The comparator used in the LM122 utilizes high gain PNP
input transistors to achieve 300 pA typical input bias current
over a common mode range of OV to 3V. A boost terminal
allows the user to increase comparator operating current for
timing periods less than 1 ms. This lets the timer operate
over a 3 p.s to multi-hour timing range with excellent repeatability.
The LM122 operates over a temperature range of - 55'C to
+ 125·C. An electrically identical LM322 is specified from
OOC to + 700C. The LM3905 is identical to the LM122 series
except that the boost and VADJ pin options are not available, limiting minimum timing period to 1 ms.

Features
• Immune to changes in trigger voltage during timing
interval
• Timing periods from microseconds to hours
• Internal logic reversal
• Immune to power supply ripple during the timing
interval
• Operates from 4.5V to 40V supplies
• Input protected to ±40V
• Floating transistor output with internal current limiting
• Internal regulated reference
• Timing period can be voltage controlled
• TTL compatible input and output

Connection Diagrams
Metal Can Package

Dual-In-Llne Package

EMITTER

••

EMITTER

Dual-In-Llne Package
NC

LOGIC

13 Nt

LOGIC

EMITTER
12 COllECTOR

TRIGGER

"

VN'.

10

RIC

BOOST

COLLECTOR

v·
V'

GND

GNO

NC

VAlli

NC

TLlH17766-6

Top View
Order Number LM122H
See NS Package Number Hl0C

TL/HI7766-7

Top View
Order Number LM322N
See NS Package Number N14A

8-33

TL/HI7766-B

Top View
OrderNumberUM3905N
See NS Package Number N08E

Absolute Maximum Ratings
Logic Reverse Voltage
5.5V
Output Short Circuit Duration (Note 1)
Lead Temperature
(Soidering, 10 sec.)
260"C
Operating Temperature Range
LM122
-55°C s: TA s: + 125°C
LM322
O"C s: TA s: +70"C
LM3905
O"C s: TA s: +70"C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Power Dissipation
V+ Voltage
Collector Output Voltage
VREF Current
Trigger Voltage
VADJ Voltage (Forced)

500mW
40V
40V
5mA
±40V
5V

Electrical Characteristics (Note 2)
Parameter

LM122

Conditions
Min

Typ

LM322
Max

Min

Typ

LM3905
Max

Min

Typ

Units
Max

Timing Ratio

TA = 25°C, 4.5V s: V+ s: 40V 0.626 0.632 0.638 0.620 0.632 0.644 0.620 0.632 0.644
Boost Tied to V+, (Note 3)
0.620 0.632 0.644 0.620 0.632 0.644

Comparator Input
Current

TA = 25°C, 4.5V s: V+
Boost Tied to V+

Trigger Voltage

TA = 25°C, 4.5V

Trigger Current

TA = 25°C, VTRIG

Supply Current
Timing Ratio

s: 40V

s: V + s: 40V
= 2V
TA ~ 25°C, 4.5V s: V+ s: 40V
4.5V s: V + s: 40V
Boost Tied to V+

Comparator Input
Current

4.5V s: V+ s: 40V
Boost Tied to V+, (Note 4)

Trigger Voltage

4.5V

Trigger Current

VTRIG

Output Leakage
Current

VeE

CapaCitor Saturation
Voltage

Rt
Rt

~

s: V + s: 40V
= 2.5V

1.2

1.6

2

2.5

1.2

2.5

4

Emitter Saturation
Voltage

TA = 25°C, IL
TA = 25°C,IL

= 8mA
= 50mA

= 3 mA
= 50 mA

1.2

1.5

nA
nA

1.6

2

V

4.5

mA

25
4.5

2.5

/LA

0.654
0.654

0.61

0.654

-5

5
100

-2

2
150

-2.5

2.5

2.5

0.8

2.5

0.8

0.8

3

2.5

V

200

200

/LA

1

5

5

/LA

2.5
25

3.3

20
6

3

mV
mV

2.5
25

150

3.15

150

3.15

3.3

50
25

20
6

0.25
0.7

0.4
1.4

1.8
2.1

2.2
3

0.003

nA
nA

200

150

IL
IL

2

25

2.5
25

Collector Saturation
Voltage

1.6

0.5

0.61
0.61

1 MO

Reference Regulation

1.5
100

0.644
0.644

= 10 kO

TA

0.3
30

0.62
0.62

= 40V

= 25°C
o s: lOUT s: 3 mA
4.5V s: V + s: 40V

Average Temperature
Coefficient of Timing
Ratio

1.0
100

25

Reset Resistance
Reference Voltage

0.3
30

0

3.15

3.3

V

50
25

20
6

50
25

mV
mV

0.25
0.7

0.4
1.4

0.25
0.7

0.4
1.4

V
V

1.8
2.1

2.2
3

1.8
2.1

2.2
3

V
V

0.003

3

0.003

%rC

Minimum Trigger Width VTRIG = 3V
0.25
0.25
0.25
/Ls
Note 1: ContinUous output shorts are not allowed. Short clrcu~ duration at ambient tamperatures up to 40'C may be calculatad from t = 120IVCE eeconds, where
VOE Is the collector to e~r voltage across the output transistor during the short.
Note 2: These specifications apply for TAMIN ,; TA ,; TAMAX unless othelWlee noted.
Note 3; Output pulee width can be calculatad from the following equation: t = (Rt> (Ctl (1 - 2(0.632 - r) - Vc!VREF) where r is timing ratio and Vo is capacitor
saturation voltage. this reduces to t = (Rt> (Ctl for all but the most critical applications.
Note 4: Sign reverssl may occur at high tamperatures (> l00'C) where comparator Input current Is predomlnataly leakage. See typclal curves.
Note 5: Refer to RETSI22X drawing of military LM122H V8IlIIon for specifications.

8·34

Typical Performance Characteristics

•

t .........e

i

~RJ:;E~:~I..

L.
-A

....

Comparator Bias Current

~

I
I

i

I I
I

,

..

lG

T~"J'.!·L.l.
l-l,,-IIO"C

I ~ H"'w,i'(

\

'.-Iwe

3.2

~~~~:I'~'F

D

-J

-u

1.&.2

-ZA

U

COMPARATOR INPUT VOLTAGE (VI

Comparator 81_ Currant
(LM1221LM322)

Comparator Blaa Currant

. .

,

1
Ii
i

' ....

-we I
T -21 C

,.-12I·C

ZfI

I--

!::!,8ER .......

IS --I!!!'..,TTlEDTOY·+_t--+

g 11~-+-+-r--+-,
"

I'-!-

'.L_~~~_,~.-~~U
CIIMPARATOR ,N'UT VOLTAGE !VI

COMrARATOR 'IfPUT VOLTAGE {VI

TUH/n68-3
Supply Currant

u

r .. --II'C

./

Trigger Input Characteristics

T,L.re

I

T~'WC

/

~

"...

...-

V

.

"

••lIP'

"--'-_':--"--'--'

•

I.

24
V·fVl

3Z

CD

Output Transistor SaturaUon
Charactarlstic8 at Low Currants

J--- -tt..... 12ft

.10
~

Z4

1

••

/

[L

i
!
i

..

;

/

....•

I.

III

41

-55

I I

l.l~
T'i'i
II
II

!!

Ii -1'
-11

•
Short Output Pulse
(LM122/LM322)

•

~

~

..•

I I
I I
I I

SATURATION VOLTAGE (VI

..

-

'8k

,

.......

r-'I'::r

_. _o"D

"

k' 1-'

T..... 12 C_

T,,-2I-':
........ ~
T,,"'-WCr-...,

101

"

.id II'
.;

......,...

,.

t

t\

Short Output Pulse
(LM122/LM322)

+r

...,.
'51

51

i'-.
,.

1l1li

Logic Pin Charectarlstlcs

h,saTII"".L.'.'
I

I

•

I

lA"Zie

~:=::., I Ll
CQLLEtTUR OUTPUT R . . . .

TIME 110'11

:tr

,DUTPUTSWITCHINO
mY TYPICAL
TRIGGER "LO"
V"1e ~ 0

I

I I I

.II'

t;

OUTPUT CURRENT c.AI

I~ = ~::~c==
TIMEI,us1

. -

..

..!...!.

LOClt I'll TIED TO jE-+REFERENCE VOLTAGE

T,·ur,

'='::lLIe._1

l .. -IZI'"C

V- I-"

,
•

I.

~~"".":'.,"C_:f1I._I'"
"

~

41

II

Suggested Timing Components

T.... ..we·

~

2&

Timing Error Due to
Comparator 81_ Currant
IDB

T... ·-II C

u,

I I

-11

TEMPiRATURE I 1:1

III

II

'I

r--J
I

•

Referance Regulation
11

I~
i

...

IATURATIOI VOLTAGE "VI

12

Collector Output Saturation
CharacterlsUca at High Currant

iii •

yr... ·-IiI·C

T1~C"""~

~

WORST CAIE "...

TRIIOER VOLTAGE IVI

E
T.=zrt

I"'-....LJ

-I

.§

f

WORST CASE ', ..

....
....

!.Ii

T... IH'C

1
16

I I

I

,/

T -Ire

u

Trigger Threshold

TRIGGER ~HIN

Vllj.VrF

1

1

1

I

I

I

LOGIC PIN VOLTAGE IVI

TUH/n68-4

8-35

•

LM122/LM322/LM3905

W
:::r
COLLECTOR
OUTPUT

CD

3

y'

II
R34

0"

RZI

2K

c

3111

iii"

co

a3

EMITTER
OUTPUT
V REF
I

RII

0&~25K
'f'
~
RIC·
!RB
&K

Rl
2K

R11

lK

GNO

•

• • •
TRIGGER

•

•

•

••

••

•

lOGIC
lUH/7768-5

Functional Diagram
BOOST

r

VREF

r - o -.....- - - - t
I

~~~

~, "~

o-~-~4--~

I
I

-l
NON·INVERTING LATCHING BUFFER
(OUTPUT LATCHES HIGH WHEN
DRIVEN TO THE HIGH STATE IF
TRIGGER IS LOW-OUTPUT UNLATCHES
IF TRIGGER IS PULSED HI)

VI

... -o-t~-__4J----1
-,- t

I
L.. -

I

I
I
r----,
./"-+...:I~O COLLECTOR
I

RIC

.l...C

I

I

-"-1-1-0 EMITIER

I
I
GNO I
e>--=---.....

LOGIC
CIRCUIT

CURRENT

~I:~~~~

I
I

I
I

I
I

I

I

_________ ..JI

IL __ _
TRIGGER

LOGIC

TL/H/7766-9

Timing Diagram

4V-----~::~-=~~~~~~I---------~~
~
13•15V i
",""""~.............,1.-__
_

SIGNAL ON RIC PIN OV~

TRIGGER~
VI

V2, LOGIC PIN HIGH
V2, LOGIC PIN LOW

TIMER FUNCTION
(CAPACITOR FROM RIC TO GNO)

COMPARATOR FUNCTION
(NO CAPACITOR FROM RIC TO GNO,
R ~ 1 kO IN SERIES WITH RIC PIN)

TL/HI7768-10

Pin Function Description
One of the main features of the LM122 is its great versatility.
Since this device is unique, a description of the functions
and limitations of each pin is In order. This will make it much
easier to follow the discussion of the various applications
presented in this note.

Quiescent current drawn from the Y+ terminal is typically
2.5 mA, independent of the supply voltage. Of course. additional current will be drawn If the reference Is externally
loaded.
The YREF pin Is the output of a 3.15V series regulator referenced to the ground pin. Up to 5.0 mA can be drawn from
this pin for driving external networks. In most applications
the timing resistor Is tied to YREF. but it need not be in
situations where a more linear charging current is required.
The regulated voltage is very useful in applications where
the LM122 is not used as a timer; such as switching regulators. variable reference comparators. and temperature con-

Y+ Is the positive supply terminal of the LM122. When using a single supply, this terminal may be driven by any voltage between 4.5V and 40V. The effect of supply variations
on timing period is less than 0.005%/V, so supplies with
high ripple content may be used without causing pulse width
changes. Supply bypassing on Y+ is not generally needed
but may be necessary when driving highly reactive loads.

8-37

~r-----------------------------------------------------~

~

:i
....I

......
C'I
C'I
CO)

:i
....I

C\i
C'I

....

:5

Pin Function Description (Continued)
trollers. Typical temperature drift of the reference is less
than 0.01 %/'C.
The trigger terminal is used to start a timing cycle (see
functional diagram). Initially, Ql is saturated, Ct is discharged and the latching buffer outpu1 (VI) is latched high .
A trigger pulse unlatches the buffer, VI goes low and turns
Ql off. The timing capacitor Ct connected from RIC to GND
will begin to charge. When the voltage at the RIC terminal
reaches the 2.0V threshold of the comparator, the comparator toggles, latching the buffer output (VI) in the high state.
This turns on Ql, discharges the capacitor Ct and the cycle
is ready to begin again.
If the trigger is held high as the timing period ends, the
comparator will toggle and VI will go high exactly as before.
However, VI will not be latched and the capacitor will not
discharge until the trigger again goes low. When the trigger
goes low, VI remains high but is now latched.
Trigger threshold is typically 1.6V at 25'C and has a temperature dependence of -5.0 mV/'C. Current drawn from
the trigger source is typically 20 p.A at threshold, riSing to
600 p.A at 30V, then leveling off due to FET action of the
series resistor, R5. For negative input trigger voltages, the
only current drawn is leakage in the nA region. The trigger
can be driven from supplies as high as ±40V, even when
device supply voltage is only 5V.
The RIC pin is tied to the non-inverting side of the comparator a~d t~ the collector of Ql. Timing ends when the voltage
on thiS pin reaches 2.0V (1 RC time constant referenced to
the 3.15V regulator). Ql turns on only if the trigger voltage
has dropped below threshold. In comparator or regulator
a~plications of the timer, the trigger is held permanently
high and the RIC pin acts just like the input to an ordinary
comparator. The maximum voltages which can be applied to
thi~ pin are + 5.5V and -O.7V. Current from the RIC pin is
typically 300 pA when the voltage is negative with respect to
the VADJ terminal. For higher voltages, the current drops to
leakage levels. In the boosted mode, input current is typically 30 nA. Gain of the comparator is very high, 200,000 or
more, depending on the state of the logic reverse pin and
the connection of the output transistor.
The ground pin of the LM122 need not necessarily be tied
to system ground. It can be connected to any positive or
negative voltage as long as the supply is negative with respect to the V+ terminal. Level shifting may be necessary
for the input trigger if the trigger voltage is referred to system ground. This can be done by capacitive coupling or by
actual resistive or active level shifting. One point must be
kept in mind; the emitter output must not be held above the
ground terminal with a low source impedance. This could
occur, for instance, if the emitter were grounded when the
ground pin of the LM122 was tied to a negative supply.
The terminallabled VADJ is tied to one side of the comparator and to a voltage divider between VREF and ground. The
divider voltage is set at 63.2% of VREF with respect to
ground-exactly one RC time constant. The impedance of
the divider is increased to about 30k with a series resistor to

present a minimum load on external Signals tied to VADJ .
This resistor is a pinched type with a typical variation in
nominal value of -50%, + 100% and a TC of 0.7%I'C. For
this reason, external signals (typically a pot between VREF
and ground) connected to VADJ should have a source resistance as low as possible. For small changes in VADJ, up
to several kO is all right, but for large variations, 2500 or
less should be maintained. This can be accomplished with a
1k pot, since the maximum impedance from the wiper is
2500. If a voltage is forced on VADJ from a hard source,
voltage should be limited to -0.5, and +5.0V, or current
limited to ± 1.0 mA. This includes capacitively coupled signals because even small values of capacitors contain
enough energy to degrade the input stage if the capaCitor is
driven with a large, fast slewing signal. The VADJ pin may be
~s~d to a~ort the timing cycle. Grounding this pin during the
timing penod causes the timer to react just as if the capacitor voltage had reached its normal RC trigger point; the
capacitor discharges and the output charges state. An exception to this occurs if the trigger pin is held high, when the
VADJ pin is grounded. In this case, the output changes
state, but the capacitor does not discharge.
If the trigger drops while VADJ is being held low, discharge
will occur immediately and the cycle will be over. If the trigger is still high when VADJ is released, the output mayor
may not change state, depending on the voltage across the
timing capacitor. For voltages below 2.0V across the timing
capacitor, the output will change state immediately, then
once more as the voltage rises past 2.0V. For voltages
above 2.0V, no change will occur in the output. This pin is
not available on the LM2905/LM3905.
Ir. noisy environments or in comparator-type applications a
bypass capacitor on the VADJ terminal may be needed'to
eliminate spurious outputs because it is high impedance
point. The size of the cap will depend on the frequency and
energy content of the noise. A 0.1 p.F will generally suffice
for spike suppression, but several p.F may be used if the
timer is subjected to high level 60 Hz EMf.
The emitter and the collector outputs of the timer can be
treated just as if they were an ordinary transistor with 40V
minimum collector-emitter breakdown voltage. Normally, the
emitter is tied to the ground pin and the signal is taken
from the collector, or the collector is tied to V+ and the
signal is taken from the emitter. Variations on these basic
con~~ctions are possible. The collector can be tied to any
positive voltage up to 40V when the signal is taken from the
emitter. However, the emitter will not be pulled higher than
the supply voltage on the V+ pin. Connecting the collector
to a voltage less than the V+ voltage is allowed. The emitter should not be connected to a low impedance load other
than that to which the ground pin is tied. The transistor has
built-in current limiting with a typical knee current of 120 mAo
Temporary short circuits are allowed; even with collectoremitter voltages up to 40V. The power x time product, however, must not exceed 15 watt-seconds for power levels
above the maximum rating of the package. A short to 30V,

Pin Function Description

(Continued)
for instance, cannot be held for more than 4 seconds.
These levels are based on 40'C maximum initial chip temperature. When driving inductive loads, always use a clamp
diode to protect the transistor from inductive kick-back.

TRIGGER
INPUT

A boost pin is provided on the LM122 to increase the speed
of the internal comparator. The comparator is normally operated at low current levels for lowest possible input current.

VOUT

For timing periods less than 1 ms, where low input current is
not needed, comparator operating current can be increased
several orders of magnitude. Shorting the boost terminal to
V + increases the emitter current of the vertical PNP drivers
in the differential stage from 25 nA to 5 ",A. This pin is not
available on the LM3905.
With the timer in the unboosted state, timing periods are
accurate down to about 1 ms. In the boosted mode, loss of
accuracy due to comparator speed is only about 800 ns, so
timing periods of several microseconds can be used. The
800 ns error is relatively insensitive to temperature, so temperature coefficient of pulse width is still good.
The Logic pin is used to reverse the signal appearing at the
output transistor. An open or "high" condition on the logic
pin programs the output transistor to be "off" during the
timing period and "on" all other times. Grounding the logic
pin reverses the sequence to make the transistor "on" during the timing period. Threshold for the logic pin is typically
100 mV with 150 ",A flowing out of the terminal. If an active
drive to the logic pin is desired, a saturated transistor drive
is recommended, either with a discrete transistor or the
open collector output of integrated logic. A maximum VSAT
of 25 mV at 200 ",A is required. Minimum and maximum
voltages that may appear on the logic pin are 0 and + 5.0,
respectively.

~---l

----1

L-L

INPUT

TLlH17766-11

FIGURE 1. Basic Timer-Collector
Output and Timing Chart
TRIGGER
INPUT
 .'"

I

I OUTPUT

:~ WAVEFORM

+2BV

TRIGGER
INPUT

VOUT

r = RI

"

•

1=-

RIC.

TL/H/7768-17
10.

v

10

V

I..

V

'".;!, •..

V

oS

0.01

V

0.001

I

TUHI7768-15

FIGURE 5. 5V Logic Supply Driving 28V Relay

0.001 0.01

30V Supply Interfacing with 5V Logic

1.0

0.1

10

100

C,I.F)

TUH/7768-18

Figure 6 indicates the ability of the timer to interface to digital logic when operating off a high supply voltage. VOUT
swings between + 5V and ground with a minimum fanout of
5 for medium speed TTL. If the logic is sensitive to rise/fall
time of the trailing edge of the output pulse, the trigger pin
should be low at that time.

FIGURE 7. Oscillator
One Hour Timer with Reset and Manual Cycle End
Figure 8 shows the LM122 connected as a one hour timer
with manual controls for start, reset, and cycle end. 51
starts timing, but has no effect after timing has started. 52 is
a center off switch which can either end the cycle prematurely with the appropriate change in output state and discharging of Ct, or cause Ct to be reset to OV without a
change in output. In the latter case, a new timing period
starts as soon as 52 is released.

TRIGGER
INPUT

+3av
+5.0V

I - -....- vou,
tLOSETO

START
TtMlIlJG

r1

TRIGGER
LOGIC

S'

....- - - - - 4 . . . , V REF

C,
END CYCLE

BOOST
V+

COLLECTOR

R,
15M

S2-_=>-""'"".........:t
RESET

TUH/7768-16

,~T-""::"""

9Dearborn

FIGURE 6. 30V Supply Interfacing with 5V Logic
Astable Operation
The LM122 can be made into a self-starting oscillator by
feeding the output back to the trigger input through a capacitor as shown in Figure 7. Operating frequency is 1/(Rt +
R1)(Ct). The output is a narrow negative pulse whose width
is approximately 2R2 Cj. For optimum frequency stability, Cj
should be as small as possible. The minimum value is deter-

-::-

Electronics
LP9A1A476K
Polycarbonate
TUHI7768-19

FIGURE 8. One Hour Timer with Reset
and Manual Cycle End

8-40

Typical Applications (Continued)
The average charging current through Rt is about 30 nA, so
some attention must be paid to parts layout to prevent stray
leakage paths. The suggested timing capacitor has a typical
self time constant of 300 hours and a guaranteed minimum
of 25 hours at + 25°C. Other capacitor types may be used if
sufficient data is available on their leakage characteristics.
Two Terminal Time Delay Switch
The LM122 can be used as a two terminal time delay switch
if an "on" voltage drop of 2V to 3V can be tolerated. In
Figure 9, the timer is used to drive a relay "on" Rt • Ct
seconds after application of power. "Off" current of the
switch is 4 mA maximum, and "on" current can be as high
as 50 mA.

. - _...._+Vct

"'
'.n
C.
0.01
TRIGGER---.J 1-.....__..._ ........_ ..
INPUT.

.+

.

Zero Power Dissipation Between Timing Intervals
In some applications it is desirable to reduce supply current
drain to zero between timing cycles. In Figure 10 this is
accomplished by using an external PNP as a latch to drive
the V+ pin of the timer.
Setween timing periods 01 is off and no supply current is
drawn. When a trigger pulse of 5V minimum amplitude is
received, the LM122 output transistor and 01 latch for the
duration of the timing period. D1 prevents the step on the
V + pin from coupling back into the trigger pin. If the trigger
input is a short pulse, C1 and R2 may be eliminated. RL
must have a minimum value of (Vccl/(2.5 mAl.

Vm

COLLECTOR

1----..1

'om

..

BL

TUH/nSB-21

FIGURE 10. Zero Power Dissipation
Between Timing Intervals

TAII~:~~_+-

__"""

. - - -....-+·cc

""l..flI"L

y+

VIEf

COLlECTOAt---...

R,

R/C

v.'"

EMlnER

GND

TUH/n68-22

.,..

FIGURE 11. Frequency to Voltage Converter.
(Tachometer) Output Independent of Supply Voltage•

TUHI7768-20

FIGURE 9. 2·Terminal Time Delay Switch
Frequency to Voltage Converter
An accurate frequency to voltage converter can be made
with the LM122 by averaging output pulses with a simple
one pole filter as shown in Figure 11. Pulse width is adjusted
with R2 to provide initial calibration at 10kHz. The collector
of the output transistor is tied to VREF, giving constant am·
plitude pulses equal to VREF at the emitter output. R4 and
C1 filter the pulses to give a dc output equal to,
(Rtl(Ct)(VREF)(f). Linearity is about 0.2% for a OV to 1V out·
put. If better linearity is desired R5 can be tied to the summing node of an op amp which has the filter in the feedback
path. If a low output impedance is desired, a unity gain buffer such as the LM110 can be tied to the output. An analog
meter can be driven directly by placing it in series with R5 to
ground. A series RC network across the meter to provide
damping will improve response at very low frequencies.

TTL

t:::~-4-""'-------"'"
PULSE

. - - -.....-y+

INPUT
TRIGGER

...--t---i LDGle

BOOST

y+

....
R3

B,
VRE •

COLLECTOA

VOUT

R,

B2
5.111

TUHI7768-23

Pulse Width Detector

'VOUT = 0 for W R, C,
Pulse Out = W - R, C, for W R, C,

Sy driving the logic terminal of the LM122 simultaneous to
the trigger input, a simple, accurate pulse width detector can
be made (Figure 12).

FIGURE 12. Pulse Width Detector

8-41

Ln

i

CO)

::!
~

C'\I
CO)

::!
~
....
:=I

r---------------------------------------------------------------------------------,
Typical Applications (Continued)
Grounding VADJ will end the timing cycle just as if the timing
capacitor had reached its normal discharge point A new
timing cycle can be started by the trigger terminal as soon
as the ground is released. A switching transistor is best for
driving VADJ to as near ground as possible. Worst case sink
current is about 300 ",A.

In this application the logic terminal is normally held high by
R3. When a trigger pulse is received, Q1 is turned on, driving the logic terminal to ground. The result of triggering the
timer and reversing the logic at the same time is that the
output does not change from its initial low condition. The
only time the output will change states is when the trigger
input stays high longer than one time period set by Rt and
Ct. The output pulse width is equal to the input trigger width
minus Rt • Ct. C2 insures no output pulse for short «RC)
trigger pulses by prematurely resetting the timing capaCitor
when the trigger pulse drops. CL filters the narrow spikes
which would occur at the output due to propagation delays
during switching.

A timing cycle may also be ended by a positive pulse to a
resistor (R ,;; Rt/100) in series with the timing capacitor.
The pulse amplitude must be at least equal to VADJ (2.0V),
but should not exceed 5.0V. When the timing capacitor discharges, a negative spike of up to 2.0V will occur across the
resistor, so some caution must be used if the drive pulse is
used for other circuitry.
TRllo,:,~;o-_---,

SV Switching Regulator
Figure 13 is an application where the LM122 does not use
its timing function. A switching regulator is made using the
internal reference and comparator to drive a PNP transistor
switch. Features of this circuit include a 5.5V minimum input
voltage at 1A output current, low part count, and good efficiency (> 75%) for input voltages to 10V. Line and load
regulation are less than 0.5% and output ripple at the
switching frequency is only 30 mY. Q1 is an inexpensive
plastic device which does not need a heatsink for ambient
temperature up to 50"C. 01 should be a fast switching diode. Output voltage can be adjusted between 1V and 30V
by choosing proper values for R2, R3, R4, and R5. For outputs less than 2V, a divider with 2500 Thevinin resistance
must be connected between VREF and ground with its tap
point tied to VADJ.

lOGIC

.------....--1

VREf

t--------) 01.
VADJ

COllECTOR ~"""-p---ovo",

EMIl1lII
GND

>

DISCRET
TRANSISTOR
DR LOGIC
GATE

TL/H/7768-25

FIGURE 14. Cycle Interrupt
The output of the timer can be wire ORed with a discrete
transistor or an open collector logiC gate output This allows
overriding of the timer output, but does not cause the timer
to be reset until its normal cycle time has elapsed.
Using the LM122 as a Comparator

A built-in reference and zero volt common mode limit make

A2

the LM122 very useful as a comparator. Threshold may be
adjusted from zero to three volts by driving the VADJ terminal with a divider tied to VREF. Stability of the reference
voltage is typically ± 1% over a temperature range of
- 55°C to + 125°C. Offset voltage drift in the comparator is
typically 25 ",vrc in the boosted mode and 50 ",vrc unboosted. A resistor can be inserted in series with the input
to allow overdrives up to ±50V as shown in Figure 15.
There is actually no limit on input voltage as long as current
is limited to ± 1 mA. The resistor shown contributes a worst
case of 5 mV to initial offset In the unboosted mode, the
error drops to 0.25 mV maximum. The capability of operatIng off a single 5V supply with internal reference should
make this comparator very useful.

158
1.OW
VREF

COLLECTOR

01
ZN3B80

FAST
RECOVERY

RIC

A5
Uk

EMITTER
GNO

C2
1.1

'No. 22 Wire Wound on Molybdenum Permalloy Core

TL/H17768-24

FIGURE 13. SV Switching Regulator with
1 Amp Output and S.SV Minimum Input

Application Hints
Aborting a Timing Cycle
The LM122 does not have an input specifically allocated to
a stop-timing function. If such a function is desired, it may be
accomplished several ways:
• Ground VADJ
• Raise RIC more positive than VADJ
• Wire "OR" the output

8-42

r-----------------------------------------------------------------------------'r
Application Hints (Continued)

..==

..

N

"high" is 2.5V. R2 may be calculated from the divider equation with R1 to give these levels.

",

NDN·INIIERTING

R,

N

~
r
iI:
Co)

+1SV

~ 1--10------,
,..uTI
1

TRI.GER

·ou.

.,

r
iI:

Co)

ALT£RIIATE ~
TRIG8ER,
INVERTING

N
......

r-:::=::--=~

•••CI1,..F

8UI

'"
w-~--~~+---+~

'-"T'----'::;;:-.....

R,
VOUT
{:l:15VI

'Timer Protected
Against Damage
for up to 50V
TL/H/7768-26

FIGURE 15. Comparator with OV to 3V Threshold
Eliminating Timing Cycle Upon Initial
Application of Power
The LM122 will normally start a timing cycle (with no trigger
input) when V + is first turned on. If this characteristic is
undesirable, it can be defeated by tying the timing capacitor
to VREF instead of ground as shown in Figure 16. This connection does not affect operation of the timer in any other
way. If an electrolytic timing capacitor is used, be sure the
negative end is tied to the RIC pin and the positive end to
VREF. A 1.0 kO resistor should be included in series with the
timing capacitor to limit the surge current load on VREF
when the capacitor is discharged.

L-......

~

>-- -15.

_ _ _ _......o--_......

TL/H17766-28

'Setect for Proper Level Shift
Emitter Terminal or Emitter Load must be Tied to GND Pin of TImer

FIGURE 17. Operating Off Dual Supplies
Unearizing the Charging Sweep
In some applications (such as a linear pulse width modulator) it may be desirable to have the timing capacitor charge
from a constant current source. A simple way to accomplish
this is shown in Figure 18.
v'

.'

R3

r-----<~-I V"EF

c,

02 LM129

R,

.....w\r-<...----l
RI
Uk

Rl
COllECTOR

Ql

RIC

EMITTER / - - -.....- VOUT

RZ
UII

TUH/7768-27

FIGURE 16. Eliminating Initial Timing Cycle

TL/H/7768-29

Using Dual Supplies
The LM122 can be operated off dual supplies as shown in
Figure 17. The only limitation is that the emitter terminal
cannot be tied to ground, it must either drive a load referred
to V- or be actually tied to V- as shown. Although capacitive coupling is shown for the trigger input (to allow 5V triggering), a resistor can be substituted for C1. R2 must be
chosen to give proper level shifting between the trigger signal and the trigger pin of the timer. Worst case "10" on the
trigger pin (with respect to V-) is O.BV, and worst case

FIGURE 18. Temperature Compensated
Linear Charging Sweep
Q1 converts the current through R1 to a current source independent of the voltage across Ct. R2, RS, 01, and 02 are
added to make the current through R 1 independent of supply variations and temperature changes. (02 is a low TC
type) 02 and RS can be omitted if the V+ supply is stable
and 01 and R2 can be omitted also if temperature stability is
not critical. With 01, 02, R2 and RS omitted, the current
through R1 will change about 0.015%fOC with a 15V supply
and 0.1 %fOC with a 5.0V supply.

B-4S

•

Application Hints (Continued)
C1

Triggering with Negative Edge

a.OOl

TOI ••EO ~ ........._ - - ,
INPUT.

Although the LM122 is triggered by a positive going trigger
signal, a differentiator tied to a normally "high" trigger will
result in negative edge triggering. In Figure 19, R1 serves
the dual purpose of holding the trigger pin normally high and
differentiating the input trigger pulse coupled through C1.
The timing diagram included with Figure 21 shows that triggering actually occurs a short time after the negative going
trigger, while positive going triggers have no effect. The delay time between a negative trigger signal and actual starts
of timing is approximately (0.5 to 1.5) (R1 • C1) depending
on the trigger amplitude, or about 2.5 to 7.5 ,...S with the
values shown. This time will have to be increased for Ct
larger than 0,01 ,...F because Ct is charged to VREF whenever the trigger pin is kept high and must reset itself during the
short time that the trigger pin voltage is low. A conservative
value for C1 is:
C1 .,

~
I

0,

I
I

I

TLlHI7768-30

FIGURE 19. Timer Triggered by Negative
Edge of Input Pulse

possible connections are shown. In both cases, the output
of the timer is low during the timing period so that the positive going signal at the end of the timing period can trigger
the next timer. There is no limitation on the timing period of
one timer with respect to any other timer before or after it,
because the trigger input to any timer can be high or low
when that timer ends its timing period.

Ct

10
Chain of Timers

The LM122 can be connected as a chain of timers quite
easily with no interface required. In Figure 20A and 20B, two
VOUTI1I

VOUTI2I

TL/HI7768-31

(a)
V OUTl2J

----,
I
r..J.--..L-, I

TRIGUER
INPUT

r-l

I

VAIEF

"'-t

t

COLLECTOR

R,
RIC

1" ....
I I
I I

I
I

I

EMmER

t- .....

i l

I

I

r-.,.-

-t

-L

Yo.,,",

L-r--r.J ~
I

I

~
TL/HI776S-32

U

---,

OUTPUT!

LJ

.n

OUTPUT 3

Lr

r

LJ

OUTPUT I

n

TRIGGER INPUT

(b)
FIGURE 20. Chain of Timers
8-44

TL/HI7768-33

~National

~ Semiconductor

LM 194/LM394 Supermatch Pair
General Description
The LM194 and LM394 are junction isolated ultra wellmatched monolithic N PN transistor pairs with an order of
magnitude improvement in matching over conventional transistor pairs. This was accomplished by advanced linear processing and a unique new device structure.
Electrical characteristics of these devices such as drift versus initial offset voltage, noise, and the exponential relationship of base-emitter voltage to collector current closely approach those of a theoretical transistor. Extrinsic emitter
and base resistances are much lower than presently available pairs, either monolithic or discrete, giving extremely low
noise and theoretical operation over a wide current range.
Most parameters are guaranteed over a current range of
1 JLA to 1 mA and OV up to 40V collector-base voltage,
ensuring superior performance in nearly all applications.
To guarantee long term stability of matching parameters,
internal clamp diodes have been added across the emitterbase junction of each transistor. These prevent degradation
due to reverse biased emitter current-the most common
cause of field failures in matched devices. The parasitic isolation junction formed by the diodes also clamps the substrate region to the most negative emitter to ensure complete isolation between devices.

matched transistor pair. In many cases, trimming can be
eliminated entirely, improving reliability and decreasing
costs. Additionally, the low noise and high gain make this
device attractive even where matching is not critical.
The LM194 and LM394/LM394B/LM394C are available in
an isolated header 6-lead TO-5 metal can package. The
LM394/LM394B/LM394C are available in an 6-pin plastic
dual-in-line package. The LM194 is identical to the LM394
except for tighter electrical specifications and wider temperature range.

Features
•
•
•
•
•

Emitter-base voltage matched to 50 JLV
Offset voltage drift less than 0.1 JL W'C
Current gain (hFE) matched to 2%
Common-mode rejection ratio greater than 120 dB
Parameters guaranteed over 1 JLA to 1 mA collector
current

• Extremely low noise
• Superior logging characteristics compared to
conventional pairs
• Plug-in replacement for presently available devices

The LM194 and LM394 will provide a considerable improvement in performance in most applications requiring a closely

Typical Applications
Low Cost Accurate Square Root Circuit
lOUT = 10- 5• ~10 VIN

Low Cost Accurate Squaring Circuit
lOUT = 10- 6 (VIN)2

30pF

INPUT

o"V,.,,+IOV

lOOk"

1%

IOo,.A f.s.

1%

0" v,. ~~~~~ >-~15\1'10k"'"_----i
75 pF

----, \

Zk
5%

LM394

--

I

-=/

300k
1% IN457

LM394
':~------------i~or

lIZ LM394

IOOk- 1%

-

- -Uk

160k
1%

I/Z LM394

i%

-15V

3D pF

REGULATED
TLlH/9241-1

'Trim for full scale accuracy

8-45

-16V
REGULATED
TL/H/9241-2

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 4)
Collector Current

20mA

Collector-Emitter Voltage

VMAX
35V
20V

Collector-Emitter Voltage
LM394C
Collector-Base Voltage
LM394C

35V
20V

Collector-Substrate Voltage
LM394C

35V
20V

Collector-Collector Voltage
LM394C

35V
20V

Electrical Characteristics (TJ =
Parameter
Current Gain (hFE)

Vce = OV to VMAX (Note 1)
Ic= 1 mA
Ic = 100 p.A
Ic = 10p.A
ic=1p.A
Vce = OV to VMAX
Ic = 10p.At01 mA
Ic=1p.A

Emitter-Base Offset
Voltage

Vce = 0
Ic = 1 p.At01 mA

Change in Emitter-Base
Offset Voltage vs
Collector-Base Voltage
(CMRR)

(Note 1)
Ic = 1 p.At01 mA,

±10mA
500mW

Junction Temperature
LM194
LM394/LM394B/LM394C

- 55°C to + 125°C
- 25°C to + 85°C

Storage Temperature Range

-65°C to

Soldering Information
Metal Can Package (10 sec.)
Dual-In-Line Package (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

+ 1500C
2600C
2600C
215°C
2200C

See AN-450 "Surface Mounting and their Effects on Product Reliability" for other methods of soldering surface
mount devices.

25°C)

LM194

Conditions

Current Gain Match,
(hFEMatch)
= 100 [Aiel [hFEIMINll
Ic

Base-Emitter Current
Power Dissipation

Vce = OVtoVMAX

Change in Emitter-Base
Offset Voltage vs
Collector Current

Vce = OV,
Ic = 1 p.A to 0.3 mA

Emitter-Base Offset
Voltage Temperature
Drift

Ic = 10 p.A to 1 mA (Note 2)
IC1 = IC2
Vas Trimmed to 0 at 25°C

Min

Typ

350
350
300
200

700
550
450
300

LM394B/394C

LM394
Max

Min

Typ

300
250
200
150

700
550
450
300

Max

Min

Typ

225
200
150
100

500
400
300
200

Units

Max

0.5
1.0

2

0.5
1.0

4

1.0
2.0

5

%
%

25

100

25

150

50

200

p.V

10

25

10

50

10

100

p.V

5

25

5

50

5

50

p.V

0.08

0.3

0.08

1.0

0.2

1.5

0.03

0.1

0.03

0.3

0.03

0.5

p'vrc
p'vrc

Logging Conformity

Ic = 3 nA to 300 p.A,
Vce = 0, (Note 3)

150

Collector-Base Leakage

150

150

p.V

Vce = VMAX

0.05

0.25

0.05

0.5

0.05

0.5

nA

Collector-Collector
Leakage

Vee "" VMAX

0.1

2.0

0.1

5.0

0.1

5.0

nA

Input Voltage Noise

Ic = 100 p.A, Vce = OV,
f = 100 Hz to 100 kHz

1.8

1.8

1.8

nV/JHz

Collector to Emitter
Saturation Voltage

Ic = 1 mA,le = 10 p.A
Ic = 1 mA,le = 100 p.A

0.2
0.1

0.2
0.1

0.2
0.1

V
V

Note 1: Collector-base voltage is swept from 0 to VMAX at a collector current of 1 p.A, 10 p.A, 100 p.A. and 1 mAo
Note 2: Offset voitage drift with Vos = 0 at TA = 25"C is valid only when the ratio of IC1 to 102 is adjusted to give the inRiai zero offset This ratio must be held to
within 0.003% over the entire temperature range. Measurements taken at +25"C and temperature extremes.
Note 3: Logging conformity is measured by computing the best fit to a true exponential and expressing the error as a base-emHier voltage deviation.
Note 4: Refer to RETSI94X drawing of milHary LMI94H version for specifications.

8-46

Typical Applications (Continued)
Fast, Accurate Logging Amplifier, V,N = 10V to 0.1 mV or liN = 1 mA to 10 nA
....- - - - - - - -. ..,.",.,..,..... VREF

R6

9.76k
1%
lOOk

2k

TL/H/9241-3

'I kG (±1%) at 25'C. +3500 ppmfOC.
Available from Vlshay U~ronix,
Grand Junction, CO, Q81 Series.
VIN
VOUT - - log10 ( -)
VREF

Voltage Controlled Variable Gain Amplifier
+15V
Rl1
15k

C3
3 pF

RI
50k

. . .----....;+ 1 MHz
G ~ -336 VI (dB)
100 dB gain range

8·47

Typical Applications (Continued)
Precision Low Drift Operational Amplifier

+

;>~-----------------3~[]o~'~

Common-mode range 10V
IBIAS 25 nA
los 0.5 nA
Vos (untrimmed) 125,.V
(~_OOUTPUT

Rll

lBk

INPUTS

0.1%

R3
lBk
0.1%

RIO
Zk
0.1%

R4
Zk
0.1%

R5
Zk
5%
'Gain

= 1()6
AS

01

LMI13
12V

L...--~~----~~O-15V

TL/H/9241-7

Performance Characteristics
Unearity of Gain (± 10V Output)
Common-Mode Rejection Ratio (60 Hz)
Common-Mode Rejection Ratio (1 kHz)
Power Supply Rejection Ratio
+ Supply
-Supply
Bandwidth (-3 dB)
Slew Rate
Offset Voltage Drift"
Common-Mode Input Resistance
Differential Input Resistance

G = 10,000G
SO.01
;;'120
;;'110
>110
>110
50
0.3
SO.25
>109
>3 x 108

Input Referred Noise (100 Hz S f S 10 kHz)
Input Bias Current
Input Offset Current
Common-Mode Range
Output Swing (RL = 10 kO)
••Assumes

~

5
75
1.5
±11
±13

5 ppmfOC tracking of resistors

= 1,000G = 100 G = 10
SO.Q1
SO.02
SO.05
;;,120
;;,90
;;, 110
;;,110
;;'90
;;,70

%
dB
dB

>110
>110
>110
dB
dB
>110
>90
>70
kHz
50
50
50
0.3
0.3
0.3
Vlp.s
SO.4
S10 p.VloC
2
{}
>10 9
>109
>109
>3xl08 >3xl08 >3xlOS {}
nV
6
12
70
75
1.5
±11
±13

75
1.5
±11
±13

75
1.5
±10
±13

JRZ
nA

nA
V
V

•

8-49
- - - - - - _.. _ .

Typical Performance Characteristics
Small Signal Current Gain va
Collector Current

!

'··rT~~rTnr~~~~

i~~;'5:z-t+fHH-H+-+-11-Hl

I HOrt~H-H-H+-+-1~~~
..

B.

T,- 21"C

ffiH-tiItt-H::I;IoI

1210

! 1000
= BOO

_1 iliA

10"'A

""'9-+IHf-+t+I--HI-Hl-+-++H

g

600 I--'~A

i ZRH-~++~~~~

1

410

~

4.ZOO

Va;·5V

o
-75

Ie - COLLECTOR CURRENT ImAl

Offlet Voltage Drift VI Initial
Offlet Voltage
D••

a.4

, :L

0.2

':;

0

) -OJ

./

a

-D.'-1

T,-ZI"C

-Z.

-loa

a

100

zao

7S
lZI
17&
T, -JUNCTION TEMPERATURE f'CI

D.I

,

O.S

D.4
0,001

0.11

a,I

10

la

0.11

0.1

100

Input Voltege Nolle VI
Frequency

I.rtfir:. . .
~
I. "0.001

, - FREQUENCY IkH.1

i,
.6

0.01

I!I. I~AI10

I 'I""A
le".o;;A
'e'ImA

I

0.1

10

D.D!

IZ

11111
11111
11111
~.~l~'

o
100

100

Vel-IV
,.,.~.

H.-fDa

L

1'.1\.

;;;;

B.OOI

0.1
10
, - FREQUENCY IkH.1

Collector to Collector
Capacitance VI Reveree
Blaa Voltage

Nolae Figure VI
Collector Current

Ie • I~~.--tit
10

'10=

III

I-~.' 10011

Ie - COLLECTOR CURRENT I..AI

S
0.1

.

1111

a.ol

r-

O.D!

~.s
=

~. I~-~

10

0."

10

F~e"IV

Ie - COLLECTOR CURRENT ImAl

Base Current Nolae
VI Frequency

0.1

100

10

1111111111111111111

0.01

Ie - COLLECTOR CURRENT ImAI

Collector-Emitter
Saturation Voltage
va Collector Current

e

0.01
0.001

Vc -IV
'-100"'

. D.OOI
0.•'

~ve"IV

~

Small Signal Input
Rellatance (hie)
va Collector Current

Ie - COLLECTOR CURRENT ImAI

101

J

10

~

I.. ~~~af!~I~~
L1

t

~

Small Signal Output Conductance
VI Collector Current

~

0.1

Vel-SV

INITIAL OFFIET VOLTAGE I.VI

i

0.01

Ie - COLLECTOR CURRENT ImAl

T,·ZS·C

==

j

0.001

ZI

0.7

i

., -u
-a.1

-2&

Baae·Emltter On Voltage va
Collector Current

~
~

D••

Ii

0.,-

l-'I1,uA

1

~

lGOilii~

lo'~A

w

~
!

Unity Gain Frequency (tt) va
Collector Current

DC Current Gain va Temperature

D.lI

0.1

Ie - COLLECTOR CURRENT ImAI

,. o

lOZ03040IO

COLLECTOR.TO COLLECTOR VOLTAGE IVI

TLlH/9241-8

8-50

Typical Performance Characteristics
Collector to Collector Capacitance
vs Collector-Substrate Voltage
30

.!!
w
u

J_

;fv~

t::
I

Collector-Base Capacitance vs
Reverse Bias Voltage

-~1-

20

-..

:

~

w
u

-

~

f

5

Emitter-Base Capacitance vs
Reverse Bias Voltage
BO

I-Vcc'O-

.

(Continued)

5

::

10

w

u

"' ........

50

~

r- '-

5

JI

§

lD

j

zo

.0
10

20

3D

40

50

0.1

COLLECTOR TO SUBSTRATE VOLTAGE (VI

0.3

D.4

0.5

10

D.B

Collector to Collector Leakage
vs Temperature

=Vc.,2DV

:>

!

C

..

oS

I-

.~

TJ = 125"C
Ie '" 60~A

i:l
I

a

.JI

'"

0.1

z

.
~
'"~
.

1/

18

co

~

.....

./

I

jl 0.1

0.01

>

I-

50

15

100

125

25

T, - ,UNCTION TEMPERATURE ('CI

-+-+-+-+-+-+-1
-+-+-+-+-+-+-1

-5

50

15

100

o

125

200

T, -,UNCTION TEMPERATURE ('CI

0.4

!
:

-~c.(,oJ

0.2
0.1

..,;

ffi

~ -0.1

~

-0.2
-' -0.3
-0.4
-0.5
10-8

10-7

10-6

10-5

10-4

10-3

Ic - COLLECTOR CURRENT (AI
TL/H/9241-10

Low Frequency Noise of Differential Pair"
VCEJ lV.Ie= 100pA. !lsi"= loon

IJ.oo

1.11.

I

...... "'1"

..,..r·

~BW-O-l0HZ
t= 1 SEC DIV

,-

J

,.
.,. ,..

'J"

"'--BW - 0-1 Hz
t = 10 SEcLDIV

100 nV
","
.

~

IBW = 0-0.1 Hz
t= 1 SEC/DIV
TIME (SEE GRAPH)
TL/H/9241-11

·Unit must be in still air environment so that differential

Isad temperature is held to less than O.OOOa-C.

8-51

BOD

BOD

1 DOD

TL/H/9241-9

J

D.3

400

TIME (HRSI

Emitter-Base Log Conformity
0.5

50

m -10 L - J - J - J - J - J - J - L . . . . J ' - ' -

0.01
25

Vc< '40V

;:

I-

1/
./

40

10
.3

./

3D

Offset Voltage Long Term
Stability at High Temperature

100

10

20

REVERSE BIAS VOLTAGE IVeal

REVERSE BIAS VOLTAGE (VI

Collector-Base Leakage vs
Temperature
10D

0.2

1~1I1'-I1-1I1 1 1 1

Connection Diagrams
Metal Can Package
Dual-In-Llne and Small Ou1l1ne Package.

Tl/H/9241-12

Top View
TLlH/9241-13

Order Number LM194H, LM194H/883·,
LM394H, LM394BH or LM394CH
See NS Package Number HOeC

Top View

Order Number LM394N or LM394CN
See NS Package Number N08E

'Available per SMD #5962-8777701

8-52

I?A National
~ Semiconductor

LM 195/LM295/LM395 Ultra Reliable Power Transistors
General Description
The LM195/LM295/LM395 are fast, monolithic power transistors with complete overload protection. These devices,
which act as high gain power transistors, have included on
the chip, current limiting, power limiting, and thermal overload protection making them virtually impossible to destroy
from any type of overload. In the standard TO-3 transistor
power package, the LM195 will deliver load currents in excess of 1.0A and can switch 40V in 500 ns.
The inclusion of thermal limiting, a feature not easily available in discrete designs, provides virtually absolute protection against overload. Excessive power dissipation or inadequate heat sinking causes the thermal limiting circuitry to
turn off the device preventing excessive heating.
The LM195 offers a significant increase in reliability as well
as simplifying power circuitry. In some applications, where
protection is unusually difficult, such as switching regulators,
lamp or solenoid drivers where normal power dissipation is
low, the LM195 is especially advantageous.
The LM195 is easy to use and only a few precautions need
be observed. Excessive collector to emitter voltage can destroy the LM195 as with any power transistor. When the
device is used as an emitter follower with low source impedance, it is necessary to insert a 5.0k resistor in series with
the base lead to prevent possible emitter follower oscilla-

tions. Although the device is usually stable as an emitter
follower, the resistor eliminates the possibility of trouble
without degrading performance. Finally, since it has good
high frequency response, supply bypassing is recommended.
For low-power applications (under 100 mAl, refer to the
LP395 Ultra Reliable Power Transistor.
The LM195/LM295/LM395 are available in standard TO-3
power packages and solid Kovar TO-5. The LM195 is rated
for operation from - 55'C to + 150'C, the LM295 from
- 25'C to + 150'C and the LM395 from O'C to + 125'C.

Features
•
•
•
•
•
•
•
•

Internal thermal limiting
Greater than 1.0A output current
3.0 ",A typical base current
500 ns switching time
2.0V saturation
Base can be driven up to 40V without damage
Directly interfaces with CMOS or TTL
100% electrical burn-in

Simplified Circuit
Simplified Circuit of the LM195

r-------

I

----,

I

I

I
I
I

I

I

0.1

I
I
I

L ________ _
TL/H/8009-,

8-53

Connection Diagrams
TO·3 Metal Can Package

TQ-220 Plastic Package
EMmER

~ II E===::J:~
TLlH/6009-3

Case Is Emitter

Top View

TLlH/6009-2

Bottom View

Order Number LM385T
See NS Package Number T03B

Order Number LM185K,
LM285K or LM385K
See NS Package Number K02A

,

TQ-5 Metal Can Package

TO·202 Plastic Package

EMITTER

- - " ' r - - EMITTER

CASE IS EMITTER

TLlH/6009-5
TLlH/6009-4

TOp View

BoHomVlew
Order Number LM185H,
LM285H or LM385H
See NS Package Number H03B

Order Number LM385P
See NS Package Number P03A

8·54

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Collector to Emitter Voltage
LM195, LM295
42V
LM395
36V
Collector to Base Voltage
LM195, LM295
42V
LM395
36V
Base to Emitter Voltage (Forward)
LM195, LM295
42V
LM395
36V

Base to Emitter Voltage (Reverse)
Collector Current
Power Dissipation
Operating Temperature Range
LM195
LM295
LM395
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

20V
Internally Limited
Internally Limited
- 55'C to + 1500C
- 25'C to + 150'C
OOC to + 12SOC
-65'C to + 1500C
2600C

Preconditioning
100% Burn·ln In Thermal Limit

Electrical Characteristics (Note 1)
Parameter

LM195, LM295

Conditions

Min
Collector-Emitter Operating Voltage
(Note 3)

10:S: le:S: IMAX

Base to Emitter Breakdown Voltage

o :s: VeE

Collector Current
TO-3, TO-220
TO-5, TO-202

VeE:S: 15V
VeE:S: 7.0V

= 25'C

le:S: 1.0A, TA

O:s: le:S: IMAX
o :s: VeE :s: VeEMAX

Quiescent Current (10)

Vbe

42
1.2
1.2

Base Current

Max

LM395
Min

Typ

42

:s: VeEMAX

Saturation Voltage

Typ

=0

o :s: VeE :s: VeEMAX

= 1.0A, TA = +25'C
= 360,

2.2
1.8

Units
Max
36

V

36

60

V

1.0
1.0

2.2
1.8

A
A

1.8

2.0

1.8

2.2

V

3.0

5.0

3.0

10

/LA

2.0

5.0

2.0

10

mA

Base to Emitter Voltage

Ie

0.9

0.9

V

Switching Time

VeE = 36V, RL
TA = 25'C

500

500

ns

Thermal Resistance Junction to
Case (Note 2)

TO-3 Package (K)

2.3

3.0

2.3

3.0

'C/W

TO-5 Package (H)

12

15

12

15

'C/W

4

6

'C/W

TO-220 Package (T)

TO-202 Package (P)
12
15
'C/W
1: Unless otherwise specified. these speclflcations apply lor -55'C ,; Tj ,; + 150'C lor the LM195. -25'C ,; Tj ,; + 150'C lor tha LM295 and O'e ,;
+ 125'C lor the LMS95.
Note 2: Wrthout a heatsink,tha thermal resistance althe TO·5 package Is about + 15O'C/W. while that altha To-S package is +S5'C/W.
Note 3: Selected devices with higher breakdown available.
Note 4: Reier to RETS195H and RETS195K drawings 01 military LM195H and LM195K versions lor speclflcatlons.
Note

8-55

Typical Performance Characteristics (for K and T Packages)
Collector Characteristics

Short Circuit Current

u

5

i.

.
.~
~

z.o

2.0

~

~ u

!S

I.Z

..
..
Ii!

0.8

Ii

DA

iii

&.0

10

15

Z8

25

30

T =+12I/'C

1.'
T.

s.o

igi

.
....~

lE

1.2

z.o
1.8

>

1.1

i

I.Z
D.8

~

DA
10

15

20

25

3D

10

1.0

0.&

DA

I- - I f-. II-

Z.D

r-'::"::&ii!c±;::;:;P:~;II'I

u J---::::l;_"F-t-:...t'''-+---I

35

::~

1.0

lE

..
..~
~

>

1--+-+-+--+-+---1
0.5
COLLECTOR CURRENT IAI

I~ =1~5A
Ic~

~I"A

I

30

-

;c -1.0

""5 -2.0

1

,

~ -3.0

$

-4.0

ail

-5.0

-,
-!-!A
,.

J L
'T.· _55°C

=+2I"C

I

1

-7.0

-0.1 -OA

0

OA 0.8

1.2

rl-

..~
..5

lE
>

1
,

Y+'10V

\.
Z.D

3.0

T.I'+2~C

Y+'35V
II

~

TlME!.,1

40

Response Time

20

1.0

20

lASE EMITTER VOL TASE (VI

TA"'25°C

... 1

.

\

2.1

I

I

-&.0

~
,. , -Y+' 3IV

-

1.&

fi

20

10

,

TA "'+12Su C'

1

V'

I

Base Current
1.0

Response Time
40

1.2

d
·11
COLLECTOR CURRENT IAI

,

rY

0.1

DA

TEMPERATURE ("CI

~

0.&

TA=+12S"~\ I

:tl 0.8

-&& -3& -1& 5.0 2& 4& 65 8& 10& 12&

,----r--,..--.-...,-----,c--,

~

..5i

30

-N~

1.2

Saturation Voltage

~

25

Z8

----- -- -

COLLECTOR VOLTAGE (VI

2.5

1&

•

35

"

I

1.2

Base Emitter Voltage

~

s.o

~

1.8

ii

1A

;c u

~

i- °t

""...~

f----

~ _T.~_::C1-~ ~

COLLECTOR-EM1TTER VOLTAGE (VI

Quiescent Current

Ii

~5:.....
55

+2&.Ic -

OA

35

Z.8

I

;c

0.5

COLLECTOR·EMITTER VOLTAGE (VI

.!

J.

TO-3

Ii
ll!

1.8

..

2A

5 z.o

co
co

Bias Currant

Z.5

~

lZ

-

I.D
4.D

Il'r"-r-

~ fv+r

rt1:
~

=

v,

,.

~r-

~."IDII

0.1

I-

I.Z

TIME!..I
TL/H/6009-6

8-56

.-----------------------------------------------------------------------------,~

...==

Typical Performance Characteristics (for K and T Packages) (Continued)
10V Transfer Function

~

36V Transfer Function

2.0

51:

1.2

~

It· 3BV

~

~

TA

OA

O.B

1.&

O.B

OA

BASE·EMITTER VOLTAGE IV)

•

ii==

-S5°C

1.6

1.2

BASE·EMITTER VOLTAGE IV)
TL/H/6009-7

TL/H/6009-8

Transconductance

Small Signal Frequency
Response
T" = +25"C
;; -200

1---++t+tttlt--±±t+HloI'I

5-100

1--++H-t+lI!~I~cl"'1.0~~.l_,

S

£

:i1

-10

~

0.01

0.1

1.0

10

COLLECTOR CURRENT IA)

111111

Ilc~

T

1--f--H-++tH+-+ GM

I

-20
lOOk

TUH/6009-9

PHASE

'l~c"'O.1A

o 1-++I'fI~~
.."~===Jh;!I~ ~O.1A

=
8

0.1

III

I.IIM

10M

FREQUENCY 1Hz)
TUH/6009-10

II
8-57

LM195/LM295/LM395

en
o

:::rCD
3

!.

COLLECTOR

0'

c
iO

co

R5
600

~I

3

R23
I.ok

l tm
j

i

i? J S" S"

45V

I I tl ".1 TIT

1

I

I

~R17
400

~R13
12k

I J

1

+ I ~::.

03
6.3V

R2

::

01
6.3V

I

I

~

I

I

I

r Lr;

I

I

~

I

I

I I IJ:~ r::! I

I

I

I

I

I

014

EMITTER

.....

~

.. I
~

I

I

5IIOS

I

04
6.3V

I

I

~~

~

R21
30

BASE
TUH/6009-11

Typical Applications
1.0 Amp Voltage Follower

r------------~~--+15V

R,

10k

R.
10k

L."VI,..,.....---4--4~OUTPUT

....- - - - - - - - -...---15V

TL/H/6009-12

PowerPNP
Rl

-'V\,..,.....- - t
&.Ok·

BASE

.M__-

Time Delay
-",---",-+1&V

...._-EMITTER

500 pF**

OUTPUT
Q2
LM195

Ql

LM195

R2

10k

1-_"'__

Cl
lo.F
COLLECTOR
TLlH/6009-13

·Protects against excessive base drive
TLlH/6009-14

"Needed for siabilliy

1.0 MHz Oscillator

1.0 Amp Lamp Flasher

~:~~----------------,
Cl
-,-D.1.F
~

C2
O.OI.F

,rv~~--------.,
R6

25

Rl
510k
R2
1511k

~~-----------t--OUTPUT

01
LM195
01
lN914

C3

IODpF
R3
4Jk

1083
BULB

TL/H/6009-15
TL/H/60D9-16

8-59

Typical Applications (Continued)
1.0 Amp Negative Regulator

}-~

______~__~____ O~~:T

I.DA

R2
2Ak

tSolid Tantalum

~-------------,-------v-

TUH/6009-17

1.0 Amp Positive Voltage Regulator
Y,N
36V

TLlH/6009-18

Fast Optically Isolated SWItch

a~

s-----

Optically Isolated Power Transistor

r----+--+

.....- - - - _...--V+

OUTPUT
QI

LMI86

HI

33k

--+---"'-V-

TL/H/6009-20

Tl/H/6009-19

8-60

Typical Applications (Continued)
CMOS or TTL Lamp Interface

Two Terminal Current Limiter

40VSwitch
-~""'-40V

--+--+12V

+

~
DRIVE"
TL/H/6009-22

TLlH/6009-2S
TLlH/6009-21

'Drive Voltage OV to ;, IOV :s;; 42V

6.0V Shunt Regulator with Crowbar

Two Terminal 100 mA Current Regulator

+

Rs

V'N -""'''''''''_--4~--",_-VOUT
Q2
LM195

Cl
50 pF

TL/H/6009-25
TL/H/eoOB-24

Low Level Power Switch

Power One-Shot
y+
r - -...- - - - -. .- 12V

12V

r - -...-...JINIr--+- OUTPUT
CI
O.u,.F
Q2

LM195

QI
LMI9S

Turn ON

~

Turn OFF

350 mV

~

OUTPUT

TLlH/6009-26

200 mV

RL

~12n

T ~ RIC
R2 = 3RI
R2 :s;; 82k
TLlH/6009-27

8-61

•

Typical Applications (Continued)
High Input Impedance AC Emitter Follower

Emitter Follower

- -....--V·
INPUT

--"'_-'15V
Cl

Rl
Uk'

-'VI"".......

01
LM195

INPUT

-1

01
LM195

H ..."'VV\r-....

OUTPUT
~-+--OUTPUT

'Need fo, Stability

--"---15V

TL/H/6009-28

TL/H/6009-29

Fast Follower
--~~-V'
Rl
5.0k

01

INPUT -,..,.,"""........-f

LM195

"-I~I-4"" OUTPUT

V-

TUH/6009-30

'P,events storage with fast fall time square wava drive

PowerOpAmp
R,
lDOte

t15V

R2
lOll
L1

R4
5.1k

22 TURNS
ON R6

OUTPUT

RS

10k

RS

Rl
10k

10

INPUT .....W"'"". ."""VY...~

C1i

O.oz,.F

R6

1.0
2W

Q2

LM195
'Adjust fo, 50 mA quiescent current

tSoiId Tantalum

-ISV
TUH/6009-31

8-62

Typical Applications (Continued)
6.0 Amp Variable Output Switching Regulator
V+~t-

__________________

~

3&V

R9

DI
LMI03
3.9V

100

+
R3

2.0k

TLIH/6009-32

'Sixty turns wound on Arnold Type A-083081-2 core.
"Four devices in parallel
tSolid tantalum

8-63

~National

~ Semiconductor

LM555/LM555C Timer
General Description
The LM555 is a highly stable device for generating accurate
time delays or oscillation. Additional terminals are provided
for triggering or resetting if desired. In the time delay mode
of operation, the time is precisely controlled by one external
resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately
controlled with two external resistors and one capacitor.
The circuit may be triggered and reset on falling waveforms,
and the output circuit can source or sink up to 200 mA or
drive TTL circuits.

Features
• Direct replacement for SE555/NE555
• Timing from microseconds through hours
• Operates in both astable and monostable modes

•
•
•
•
•

Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TTL compatible
Temperature stability better than 0.005% per·C
Normally on and normally off output

Applications
•
•
•
•
•
•
•

Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator

Schematic Diagram
a

v~o-------~~.-

____

~~

____

~~

____________________.-____

-.~~

__

~

AU
Uk

.3
SO

AI
7.10
THRESHOLD

•

CONTROL 5
VOLTAGE

,

A4
5k

,

B.D

TRIGGER

OU"'UT
2

A.

DISCHAAGE

,

"
Tl/H17851-1

a-64

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
+18V
Power Dissipation (Note 1)
LM555H, LM555CH
760mW
LM555, LM555CN
1180mW
Operating Temperature Ranges
LM555C
O'Cto +70'C
LM555
- 55'C to + 125'C

Electrical Characteristics (TA =

-65'C to + 150'C

Storage Temperature Range
Soldering Information
Dual-In-Une Package
Soldering (10 Seconds)
Small Outline Package
Vapor Phase (60 Seconds)
Infrared (15 Seconds)

260'C

215'C
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

25'C, Vee = + 5V to + 15V, unless othewise specified)
Limits

Parameter

Conditions
Min

Supply Voltage
Supply Current

Timing Error, Monostable
Initial Accuracy
Drift with Temperature

3
10

RA = 1k to 100 kO,
C = 0.1 ,...F, (Note 3)

RA,RB = 1kt0100kO,
C = 0.1 ,...F, (Note 3)

Accuracy over Temperature
Drift with Supply
Threshold Voltage
Trigger Voltage

Max

Min

18

4.5

5
12

4.8
1.45

Reset Voltage

0.4

Reset Current
Threshold Current

(Note 4)

Control Voltage Level

Vee = 15V
Vee = 5V

9.6
2.9

Pin 7 Leakage Output High
Vee = 15V, 17 = 15 mA
Vee = 4.5V, 17 = 4.5 mA

8-65

Typ

3
10

Units
Max
16

V

6
15

mA
mA

%

0.5
30

1
50

ppm/'C

1.5
0.05

1.5
0.1

%
%IV

1.5
90

2.25
150

ppm/'C

2.5
0.15

3.0
0.30

%
%IV

0.667

x Vee

5
1.67

V
V

0.667
Vee = 15V
Vee = 5V

Trigger Current

Pin 7 Sat (Note 5)
Output Low
Output Low

Typ

4.5
Vee = 5V, RL = 00
Vee = 15V, RL = 00
(Low State) (Note 2)

Accuracy over Temperature
Drift with Supply
Timing Error, Astable
Initial Accuracy
Drift with Temperature

LM555C

LM555

5
1.67

5.2
1.9

0.01

0.5

0.5

1

0.1

0.4

0.1

0.25

10
3.33

10.4
3.8

1
150
70

%

0.5

0.9

0.5

1

V

0.1

0.4

rnA

0.1

0.25

,...A

10
3.33

11
4

V
V

100

1

100

nA

100

180
80

200

mV
mV

0.4

9
2.6

,...A

~
~

Electrical Characteristics TA =

25'C, Vee =

+ 5V to + 15V, (unless othewise specified) (Continued)

.....
~
~

Limite
Condition.

Parameter

LM555
Min

Vee = 15V
ISINK = 10mA
ISINK = 50mA
ISINK = 100 mA
ISINK = 200 mA
Vee = 5V
ISINK = SmA
ISINK = 5mA

Output Voltage Drop (Low)

ISOURCE = 200 mA, Vee
ISOURCE = 100 mA, Vee
VCC = 5V

Output Voltage Drop (High)

= 15V
= 15V

13
3

Unite

LM555C

Typ

Max

0.1
0.4
2
2.5

0.15
0.5
2.2

0.1

0.25

Min

12.5
13.3
3.3

12.75
2.75

Typ

Max

0.1
0.4
2
2.5

0.25
0.75
2.5

0.25

0.35

V
V
V
V
V
V

12.5
13.3
3.3

V
V
V

Rise Time of Output

100

100

ns

Fall Time of Output

100

100

ns

Note 1: For operating at elevated temperatures the device must be derated above 25'C bassd on a + 150'C rnaxlmum Junction temperature and a thermal
reslstence of 164'c/w (TOOS). 10000c/w (DIP) and 170'c/w (so.8) junction to ambient.
Note 2: SUpply currant when output high typically 1 mA less at Vee = 5V.
Note I: Tested at Vee = 5Vand Vee = 15V.
Note 4: This will detennlne the maximum value of AA + As for 15V operation. The maximum totel (AA + Rs) Is 20 MO.
Note Iio No protection against excessive pin 7 current Is necessary providing tha packags diSSipation raUng will not be exceeded.
Note 8: Aefer to AETS555X drawing of military LM555H and LM555J versions for specifications.

Connection Diagrams
Metal Can Package

GNO
TRIGGER

1

2

OUTI'UT

A
',::

3

""

~

Dual-In-Llne and Small Outline Package.

_. .
GNO

DISCHARGE

:~THRESHOLO
I:G

~

-!.h '-'~ ~



Ii:

V

1.8 t - t U J · C
la

1.0
D.I
D.I
a.l
a.,
••5
D.4
D.3
D.2
8.1

~

High Output Voltage vs
Output Source Current

Supply Current vs
Supply Voltage

Mlnlmulm Pulse Width
Required for Triggering

J:::::

-IIi'C

III

~

101

10

l.a

11IN1C{mAJ

1210

Vee "',6V

.
~.
...
..
c

4DII

f

2aa

.!

r:
c

~

110

Vee = 5.0V
6110

~~

~
~~

~

0

a.l

r:
c

Vco -lav. 15V

a
a.2

A loaD

..~
.....

a.3

LOWEST VOLTAGE LEVEL OFTRIGGER PULSE IX Vee)

+10'C

f':,

100
+zJ'c1o'

f
f

ZIG

i-'

co

F- D"C

J

10

_55~C.L
1"1 I

D
0

a.z

a.l

0.3

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE IX vcd

laao

~ 101

i

100
400

laao

I +1ZS~C r,

lzaa

T· +25·C
_ laoa

Discharge Transistor (Pin 7)
Voltage vs Sink Current

Output Propagation Delay vs
VoRage Level of Trigger Pulse

Output Propagation Delay vs
Voltage Level of Trigger Pulse

0.1

1.0

la

110

ISiNK (mAl PI. 1

Discharge Transistor (Pin 7)
Voltage vs Sink Current

•

1.0 Ll.UlllILl..LWILl.lll.llUJLJ..l.IIJJIU
D.ll
0.1
10
110
ISINK (mAl Pill

TL/H17851-4

8"67

Applications Information
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot
(Figurs 1). The external capacitor is initially held discharged
by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 Vee to pin 2, the flip-flop Is
set which both releases the short circuit across the capacitor and drives the output high.
+IV TO +\lV

When the reset function is not in use, it is recommended
that it be connected to Vee to avoid any possibility of false
triggering.
Flflurs 3 is a nomograph for easy determination of R, C
values for various time delays.
NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle.
loor-'-~--~n-7T-r~~

+Vee

10

R.

~ TRIGGER
~g=!"~mtR'

DISCHARGE

I

THRESHOLD

LMI51

I

CONTROL
VOLTAGE

OUTPUT

NORMALLY ~
"OFF" LOAD ~ R,
~------------

0.001 ' -.......-"_"--'-_'--....L..~
10}ll100}ll1 msl0msl00ms 11 10. 100.

____~--------4-~

td - TIME DELAY
TL/HI7851-7
TL/H/7851-5

FIGURE 3. Time Delay

FIGURE 1. Monoatable
The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time
the voltage equals 2/3 Vee. The comparator then resets
the flip-flop which in turn discharges the capacitor and
drives the output to its low state. Figurs 2 shows the waveforms generated in this mode of operation. Since the charge
and the threshold level of the comparator are both directly
proportional to supply voltage, the timing internal is independent of supply.

II

I

ASTABLE OPERATION
If the circuit is connected as shown in Figurs 4 (pins 2 and 6
connected) it will trigger itself and free run as a multivibrator.
The external capaCitor charges through RA + Re and discharges through Re. Thus the duty cycle may be precisely
set by the ratio of these two resistors.
r-----------------~.--------~.-_o~~

I

I

I

I

R.

I

~ R,
I

I
I

11

I

I
1/

vee = 5V
TIME - 0.1 mo/OIV.
RA = 9.1 kO
C = 0.01 ,u:

R.
LM555

I

J

II

*R'
TL/H17851-8

Top Trace: Input SVIDN.
Middle Trace: Output SVlDlv.
Bottom Trace: Gapacltor Voltage 2V1DN.

TLlH/7851-8

FIGURE 2. Monoatable Waveforma
During the timing cycle when the output is high, the further
application of a trigger pulse will not effect the circuit so
long as the trigger input is returned high at least 10 p,s before the end of the timing interval. However the circuit can
be reset during this time by the application of a negative
pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied.

FIGURE 4. Astable
In this mode of operation, the capacitor charges and discharges between 1/3 Vee and 2/3 Vee. As in the triggered
mode, the charge and discharge times, and therefore the
frequency are independent of the supply voltage.

8-68

Applications Information

(Continued)

Figure 5 shows the waveforms generated in this mode of

operation.

II

II

fI

f..I

,

.".

.......

\ /:

V
IV

TLlH/7851-9

100
to

~

..
~

z

I

c

!:

~ 0.1

7 DISCHARGE

LM555

0.1

I

I

Rs
RA + 2Rs

10 IUD

n

THRESHOLD

'~~=f'

OUTPUTo-- 3

*

TLlH17851-12

FIGURE 8. Pulse Width Modulator

.....,

,."..

'r-...
i'-..

n

,n

J J

LJ

(R'i 2RBI

0.001

6

MODULATION

'\'\'\'\
'\ '\ '\ '\

.. 0.01

TLlH17851-11

R.

8

4

~,,~"\"0~~~

I

-

+Vcc

TRIGGER 0-- Z

'\ '\ '\
'\ '\ '\ '\

~

I

"

I

.!.. =

0=

_f-'
........

PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and
triggered with a continuous pulse train, the output pulse
width can be modulated by a signal applied to pin 5. Figure
8 shows the circuit, and in Figure 9 are some waveform
examples.

1.44
T
(RA + 2RB)C
Figure 6 may be used for quick determination of these RC
values.
The duty cycle is:

'"'

Top Trace: Input 4V10Iv.
vee - 5V
TIME - 20l's/01V. Middle Trace: Output 2V/Ow.
Bottom Trace: Capacitor 2V1Div.
RA - 9.1 kfl
C - O.OII'F
FIGURE 7. Frequency Divider

Top Trace: Output 5V10iv.
Vee - 5V
TIME - 2Ol's/01V. Bottom Trace: Capacitor Voltage 1VlOw.
RA - 3.9 kfl
RB-3kfl
C - O.OlI'F
FIGURE 5. Astable Waveforms
The charge time (output high) is given by:
tl = 0.693 (RA + RB) C
And the discharge time (output low) by:
t2 = 0.693 (RB) C
Thus the total period is:
T = t, + t2 = 0.693 (RA +2RB) C
The frequency of oscillation is:
f =

IU

r-1

.......,

"\

II

u

-

l
V

II

r

10k lOOk

,- FREE·RUNNING FREQUENCY (HzI

I

TL/HI7851-IO
FIGURE 6. Free Running Frequency

I

II

n
II
II

R

II
II

TLlHI7851-13
Top Trace: Modulation 1V/Div.
vee - 5V
TIME - 0.2 ms/OIV. Bottom Trace: Output Voltage 2V10Iv.
RA - 9.1 kfl
C - O.OlI'F
FIGURE 9. Pulse Width Modulator

FREQUENCY DIVIDER
The monostable circuit of Figure 1 can be used as a fre·
quency divider by adjusting the length of the timing cycle.
Figure 7 shows the waveforms generated in a divide by
three circuit.

PULSE POSITION MODULATOR
This application uses the timer connected for astable operation, as in Figure 10, with a modulating signal again applied
to the control voltage terminal. The pulse position varies
with the modulating Signal, since the threshold voltage and
hence the time delay is varied. Figure 11 shows the waveforms generated for a triangle wave modulation signal.

8-69

Applications Information (Continued)

Ir-__~~___v~e~e__~~__~~+v~

Ir--~T.----e--o +Vee

L1
2

4'

! 7t-+--....

TRIGGERo-- Z

7l

LM665

61-.----.

~~

8

~ RZ

MODULATION

_--'ti--_..Jr-o

3
OUTPUT O--L

6

fC

*

TUH17851-16

TL/HI7851-14

FIGURE 12
Figure 13 shows waveforms generated by the linear ramp.
The time interval is given by:

FIGURE 10. Pulse Position Modulator

T = 2/3VeeRE(RI + R2)C
Rl Vee - VeE (Rl + R2)
VeE'" 0.6V

v

,/

RI

2N4250
OR EOUIV

R.
LM556

R.

-

r

..J
I

Vee = 5V
TIME = 0.1 ma/DIV.
RA = 3.9 kG
Rs=3kG

v

TUH/7851-15
Top Trace: Modulation InpuIW/DIv.
Bottom Trace: Output 2VIDiv.

./

C = 0.01 J.'F

./

TL/HI7S51-17
Vee = 5V
Top Trace: Inpu13V/Div.
TIME = 20 J.'s/DIV. Middle Trace: OutpuI5V/DIv.
Rl = 47 kG
Bottom Trace: Capacitor Voltage W/Div.
R2 = 100 kG
Re = 2.7 kG
C = 0.01 J.'F

FIGURE 11. Pulse Position Modulator
LINEAR RAMP
When the pullup resistor, RA, in the monostable circuit is
replaced by a constant current source, a linear ramp is generated. Figure 12 shows a circuit configuration that will perform this function.

FIGURE 13. Linear Ramp
50% DUTY CYCLE OSCILLATOR
For a 50% duty cycle, the resistors RA and Re may be
connected as in Figure 14. The time period for the out-

8-70

Applications Information (Continued)
put high is the same as previous, tl = 0.693 RA C. For the
output low it is t2 =
[(RA Rs)/(RA

Note that this circuit will not oscillate if Rs is greater than
1/2 RA because the junction of RA and Rs cannot bring pin
2 down to 1/3 Vee and trigger the lower comparator.

+ RS)] C in [=~s-_2~~]

ADDITIONAL INFORMATION
Adequate power supply bypassing is necessary to protect
asSOCiated circuitry. Minimum recommended is 0.1 JoLF in
parallel with 1 JoLF electrolytic.
Lower comparator storage time can be as long as 10 JoLs
when pin 2 is driven fully to ground for triggering. This limits
the monostable pulse width to 10 JoLs minimum.
Delay time reset to output is 0.47 JoLs typical. Minimum reset
pulse width must be 0.3 JoLs, typical.
Pin 7 current switches within 30 ns of the output (pin 3)
voltage.

Thus the frequency of oscillation is f = _1_
tl + t2
r---~~-----.-o

.vee

R.
ZZk
...... Z

11--+-JIr,JIh....
LMS55

OUTPUT

81-+--'"

C>- 3

TLlHI7851-18

FIGURE 14. 50% Duty Cycle Oscillator

8·71

~National

~ Semiconductor

LM556/LM556C Dual Timer
•
•
•
•
•

General Description
The LM556 Dual timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation.
The 556 is a dual 555. Timing is provided by an external
resistor and capacitor for each timing function. The two timers operate independently of each other sharing only Vcc
and ground. The circuits may be triggered and reset on failing waveforms. The output structures may sink or source
200 mA.

Applications
•
•
•
•
•
•
•

Features
•
•
•
•

Adjustable duty cycle
Output can source or sink 200 mA
Output and supply TIL compatible
Temperature stability better than 0.005% per ·C
Normally on and normally off output

Direct replacement for SE556/NE556
Timing from microseconds through hours
Operates in both astable and monostable modes
Replaces two 555 timers

Precision timing
Pulse generation
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator

Schematic Diagram
114)
V~O--------'-4~

____

~~

____- '____________________

~~

____

'-~

____- '

Oil

022

62'

03

"

06
7.Sk

1213Vcd
R4
6k

CONTROL
VOLTAGE (3.11)

GND

15,11
OUTPUT

111

TRIGGER

,1.1,
05
6k

TL/H/7B52-2

Connection Diagram
Dual-In-Line and Small Outline Packages
Vee

DISCHARGE

THRESH
OLD

CONTROL
VOLTAGE

RESET

OUTPUT

Order Number LM556J or LM556CJ
See NS Package Number J14A

TRIGGER

Order Number LM556CM
See NS Package Number M14A
Order Number LM556CN
See NS Package Number N14A

DISCHARGE THRESH

OLD

CONTROL

RESET

OUTPUT

VOLTAGE

TRIGGER

GND

TLlH17852-1

Top View
6-72

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage

Soldering Information
Dual-ln·Une Package
Soldering (10 seconds)
Small Outline Package
Vapor phase (60 seconds)
Infrared (15 seconds)

+18V

Power Dissipation (Note 1)
LM556J, LM556CJ
LM556CN

1785mW
1620mW

Operating Temperature Ranges
LM556C
LM556

Electrical Characteristics (TA = 25·C, Vee =

3
10

=

0.1 ,...F,

Accuracy over Temperature
Drift with Supply
Timing Error, Astable
Initial Accuracy
Drift with Temperature
Accuracy over Temperature
Drift with Supply
Trigger Voltage

RA,RB = 1kt0100kG,
C = 0.1 ,...F, (Note 3)
Vee
Vee

=
=

4.8
1.45

15V
5V

Trigger Current
Reset Voltage

(Note 4)

0.4

Reset Current
Threshold Current
Control Voltage Level and
'.
Threshold Voltage

=
=
Vee =
Vee =
VTH
VTH

V-Control (Note 5)
11.2V
9.6
2.9

15V
5V

Pin 1, 13 Leakage Output High
Pin 1, 13 Sat
Output Low
Output Low

Typ

4.5
Vee = 5V, RL = 00
Vee = 15V, RL = 00
(Low State) (Note 2)

RA = 1kto 100 kG, C
(Note 3)

LM556C

LM556

Conditions

Supply Voltage

Timing Error, Monostable
Initial Accuracy
Drift with Temperature

215·C
220·C

+ 5V to + 15V, unless otherwise specified)

Min

Supply Current
(Each Timer Section)

260"C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

O·Cto +70·C
- 55·C to + 125·C

Parameter

-65·Cto + 150"C

Storage Temperature Range

(Note 6)
Vee = 15V, I = 15mA
Vee = 4.5V, I = 4.5 mA

8-73

Max

Min

18

4.5

5
11

Typ

3
10

Units
Max
16

V

6
14

mA
mA

%

0.5
30

0.75
50

ppml"C

1.5
0.05

1.5
0.1

%
%IV

1.5
90
2.5
0.15

2.25
150
3.0
0.30

5
1.67

5.2
1.9

0.1

0.5

0.5

1

0.1

4.5
1.25

%
ppm/·C

%
%IV

5
1.67

5.5
2.0

V
V

0.2

1.0

,...A

0.5

1

V

0.4

0.1

0.6

mA

0.03

0.1
250

0.03

0.1
250

,...A
nA

10
3.33

10.4
3.8

10
3.33

11
4

V
V

1

100

1

100

nA

150
70

240
100

180
80

300
200

mV
mV

0.4

9
2.6

Electrical Characteristics (TA = 25'C, vcc = + 5V to + 15V, unless otherwise specified) (Continued)
Parameter

LM556

Conditions
Min

Output Voltage Drop (Low)

= 15V
= 10 mA
ISINK = 50mA
ISINK = 100 mA
ISINK = 200 mA
Vcc = 5V
ISINK = 8mA
ISINK = 5mA
ISOURCE = 200 mA, Vee = 15V
ISOURCE = 100mA, Vee = 15V
Vee = 5V

Max

0.1
0.4
2
2.5

0.15
0.5
2.25

0.1

0.25

Min

Units

Typ

Max

0.1
0.4
2
2.5

0.25
0.75
2.75

0.25

0.35

Vcc

ISINK

Output Voltage Drop (High)

LM556C

Typ

13
3

12.5
13.3
3.3

12.75
2.75

V
V
V
V
V
V

12.5
13.3
3.3

V
V
V

Rise Time of Output

100

100

ns

Fall Time of Output

100

100

ns

Matching Characteristics
Initial Timing Accuracy
Timing Drift with Temperature
Drift with Supply Voltage

(Note 7)
0.05
±10
0.1

0.2
0.2

0.1
±10
0.2

2.0

%
ppm/'C

0.5

%IV

Note 1: For operating at elevated temperatures the device mUBt be derated bassd on a + 150'C maximum Junction temperatura and a thermal resistence of
70'C/W (Ceramic), 77'CIW (Plastic DIp) and 11 O'C/W (SO-I4 Narrow).
Note 2: Supply current when output high typically 1 mA less at Vee = SV.
Note 3: Tested at Vee = SVand Vee 0 ISV.
Note 4: As reset voltage lowers, timing is Inhibited and then the output goes low.
Note S: ThlB will determine the maximum value of RA + RB for ISV operation. The maximum total (RA + RB) Is 20 MO.
Note 8: No protection against exceBslve pin 1, 13 current Is neceBssry providing the package dissipation rating will not be exceeded.
Note 7: Matching characteristics reter to the difference between performance characteristics of each timer section.
Note e: Refer to RETSSS6X drawing for speciflcatlons of military LM556J version.

8·74

Typical Performance Characteristics

'z

I.Z

Vc:c -,IV

1 ...

1.1

,0

-55L!- ~E:

T -"ZIOC

~ D.I
I

...

! :~
E

~ ~'Irc

T-.~JC

0.1

High Output Voltage vs
Output Source Current

Supply Current vs Supply
Voltage (Each Section)

Minimum Pulse Width
Required for Triggering

II :::

~:::-

T--Irc

1.2

~
I

~

D.2

0.4

0.3

,G

5

,.

,.

Low Output Voltage vs
Output Sink Current
,0

'.0

1.0'
.10

'D
IIiNK {mAl

Vee =5.IV

.

~"I Vc:c -.DV. 'IV

I

I

0

D.'

D.Z

Discharge Transistor
(Pin 1, 13)
Voltage vs Sink Current
.IDD

+125~C

'l'·C~

100

.zJ·cl-:!i

z BIIO
;::
c

~

ZDO

~
'"
f
co

o

0.3

"

"1~

"~

ll.

!

~'o·c

~I.'I

•

155ic I
o.Z

D.'

.00

I

/Il

4DD

IE zoo

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE ex Vee!

IDO

ISiNK (mA)

.zoo

1.010

1111

,0

'DO

(mAl

Vee -'5V

II

lao

III

Output Propagation Delay vs
Voltage Level of Trigger Pulse

T "Z5"C

lao

0., _ _

.0
ISINK

,ZDO

1'0D0

~:~5i

~I""
1.D

Output Propagation Delay vs
Voltage Level of Trigger Pulse

aD

~

D.'
II

111111

i~Z5

~

JJ.II"""A~5!
IiIIIP"

,.

IV~Vcc,,'IV

"DV

-51°C

1.0

I

ISOUIiCE (iliA)

.0

D.'

IE

•

II

-IV

'.0

.a~

-

Low Output Voltage vs
Output Sink Current

Low Output Voltage vs
Output Sink Current

:5

0.1

C"

TA -.,ZIOC

SUPPLY VOLTAGE eVI

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE ex Ve"'

•=

...

l,...-'

TA -.ZIOC

D.Z

o

D.'

.

I.Z

IA

I.,

0.1,

1A

J ,

~~ ~ .,zrc

I-t.!-~Oc

1.1

J

.011111
••• L....L.LWIILL.LJJJIIL..I.L.WWL..J..J.J.UIW

0.01

0.3

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE ex Vc:cl

0.,
' • •0

'.0

,0

,DO

emAl PIN ' •• 3

Discharge Transistor (Pin 1, 13)
Voltage vs Sink Current

.
"~

'DO

;:;

!
J l'
D••

...

'8

I.NK hnAlPIN 1.13

8-75

'ID
TL/HI7852-3

~National

~ Semiconductor

LM565/LM565C Phase Locked Loop
General Description
The LM565 and LM565C are general purpose phase locked
loops containing a stable, highly linear voltage controlled
oscillator for low distortion FM demodulation, and a double
balanced phase detector with good carrier suppression. The
veo frequency is set with an external resistor and capacitor, and a tuning range of 10:1 can be obtained with the
same capacitor. The characteristics of the closed loop system-bandwidth, response speed, capture and pull in
range-may be adjusted over a wide range with an external
resistor and capacitor. The loop may be broken between the
veo and the phase detector for insertion of a digital frequency divider to obtain frequency multiplication.
The LM565H is specified for operation over the - 55°C to
+ 125°C military temperature range. The LM565CN is specified for operation over the O"C to + 70"C temperature range.

Features
• 200 ppml"C frequency stability of ihe VCO
• Power supply range of ± 5 to ± 12 volts
100 ppm/% typical
• 0.2% linearity of demodulated output

with

• Linear triangle wave with in phase zero crOSSings
available
• TTL and DTL compatible phase detector input and
square wave output
• Adjustable hold in range from ± 1% to > ± 60%

Applications
• Data and tape synchronization
•
•
•
•
•
•
•
•
•
•

Modems
FSK demodulation
FM demodulation
Frequency synthesizer
Tone decoding
Frequency multiplication and division
SCA demodulators
Telemetry receivers
Signal regeneration
Coherent demodulators

Connection Diagrams
Metal Can Package

Dual-In-Llne Package

+vcc

TIMING
RESISTOR

-Vee

NC

INPUT

NC

INPUT

NC

VCO
OUTPUT
PHASE COMPARATOR
VCOINPUT
REFERENCE
OUTPUT
VCO CONTROL
VOLTAGE

VCO CONTROL
VOLTAGE

PHASE COMPARATOR
VCO INPUT
TL/HI7853-2

Order Number LM565H
See NS Package Number H10C

NC
+Vcc

TIMING
CAPACITOR
TIMING
RESISTOR
TUH17853-3

Order Number LM565CN
See NS Package Number N14A

8-76

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
±12V
Power Dissipation (Note 1)
Differential Input Voltage

1400mW

Operating Temperature Range
LM565H
LM565CN

- 55·C to + 125·C
O·Cto +70"C

Storage Temperature Range

-65·Cto + 150·C

Lead Temperature (Soldering. 10 sec.)

Electrical Characteristics AC Test Circuit, TA =
Parameter

25·C, Vee = ±6V

LM565

Conditions
Min

Power Supply Current

< V2, V3 < OV

Input Impedance (Pins 2, 3)

-4V

VCO Maximum Operating
Frequency

Co = 2.7pF

VCO Free-Running
Frequency

Co = 1.5nF
Ro = 20kO
fo=10kHz

LM565C

Typ

Max

8.0

12.5

7

10

300

500

-10

0

Operating Frequency
Temperature Coefficient

+10

Min

Triangle Wave Output Voltage

2

Triangle Wave Output Linearity
4.7

Output Impedance (Pin 4)
45

Square Wave Rise Time

1.0

2.4

3

kHz

-30

0

2

4.7

5.4

40

0.6

VCO Sensitivity

fo = 10 kHz

Demodulated Output Voltage
(Pin 7)

± 10% Frequency Deviation

Total Harmonic Distortion

± 10% Frequency Deviation

1

0.6

6600
250

Output Impedance (Pin 7)

300

400

0.2

0.75

200

3.5
4.25

Output Offset Voltage
IV7 - Vel
Temperature Drift of IV7 - Vel
AM Rejection

30

Phase Detector Sensitivity Ko

0.2

1.5

%IV

2.4

3

Vp•p

0.5

%

5.4

Vp•p

50

kO
60

4.75

30

100

4.0

%
ns

50

ns

1

mA

6600

HzlV

300

450

0.2

1.5

3.5

4.5

%

ppml"C

20

50

Output Current Sink (Pin 4)

+30

5
55

mA

500

20

Square Wave Fall Time

12.5

-200

0.1

50

8.0

250

5

Square Wave Duty Cycle

Max

kO

0.2

Square Wave Output Level

Units

Typ

5

-100

Frequency Drift with
Supply Voltage

DC Level (Pin 7)

260"C

±1V

mVp•p
%
kO

4.5

5.0

V

50

200

mV

500

500

p.V/·C

40

40

dB

.68

.88

Vlradlan

Note 1: The maximum Junction temperature of the LM565 and LM565C Is + 150'C. For operation at elevated temperetures, devices In the T0-5 package must be
derated based on a thermal reslstence of + 150'C/W Junction to ambient or + 45'C/W Junction to case. Thermal resistance of the dual-in·lln. peckage Is
+ 85'C/W.

8-77

Typical Performance Characteristics
Power Supply Current as a
Function of Supply Voltage

Lock Range as a Function
of Input Voltage

VCO Frequency
11l1li

T.-zh

L
./

f- t- -Rl=~

./
I-10k

t-

1/"
./1/
'/

" n

a

M R R

D R H

Oscillator Output
Waveforms
Ycc· ..V

1/

./

""

T.-/
/

I"'-

-

5iI liD Phase Shift vs Frequency

.
I

! 1.

I

TA -2f'C

Vee ·t12V:

148

lh:...-

• '20

II

~

l"'- I"'-

II

ii :
l.iZ

"",1_

I

_

...

Vee" :tav

I'-i

1••

LI

I

u
1.2
lA
••• NORMALIZED.
FREQUENCY

-III ...II • 21 &I 1. 1111 lZ1
nMt'ERATURE ('CI

Hold in Range as a
Function of RS-7
Vee -ttv
T.-zrC

~ +1.0

,:,

./

"

..
~

11\

0;

g

YO

•
,1.010

III

I

Ii!
lf1111<

1-11

I-

rr!j"7
I I
I

-1.0

1.2

RESISTANCE IETWEEN PINS I AND 7 fOl

"

8 t!I4IIlI.. ~Ilil
- • • 11

=

10k

r-.... ......

!!-z.u

T. - H'C
Vee. :l:IV

lk

......

;-1.1

"

UI.

110

........

,

: ·0.5
fE -1.0

Loop Gain vs Load
Resistance

~
•~ Ulo

1M

VCO Frequency as a
Function of Temperature

g

.I

tfiV

17
I'

lOOk

11.1

~~

101

lilt

FREQUENCY (Hz)

i I..
4v
:i

20

./2,3oiZ"

1k

1100
PEAKTO PEAK INPUT WLTAGE (mVl

TOTAL SUPPLY VOLTAGE (VI

D.I

1.0

rotll
III
1.4

1.8

RELATIVE FREE RUNNINB VCO FREQUENCY.

TLlHnS53-4

8-78

tn

n
PHASE

REFERENCE
OUTPUT

COMPARATOR
VCO
INPUT

VCO
CONTROL
VOLTAGE

TIMING
RESISTOR

TIMING

CAPACITOR

3

VCO

~I--o vc:::::~£
IV1 -V,1
OEMODULAT£D
OUTPUT

481k

4V

31pF

SQUARE WAVE
OUTPUT

TL/HI7853-5

Note: S, open for output offset voltage (V7 - Vel measurement

Typical Applications
2400 Hz Synchronous AM Demodulator
+11V

DEMODULATED
OUTPUT

5"

TLlHI7853-6

8-80

Typical Applications (Continued)
FSK Demodulator (2025-2225 cps)
+12V

10k

15k

~..,

2k

20k

4.1k

100
OUTPUT TO

PRINTER
MAGNET

10K

ORIVER

10k

TL/HI7853-7

FSK Demodulator with DC Restoration
+24V

.20

"'T" SO,..F
15k

10k

..L

50~V

15V
200k

2k

OUTPUTTO

PRINTER
MAGNET

DRIVER

TLlH17853-8

8-81

Typical Applications (Continued)
Frequency MulUpller (X 10)

+ev

t--+------OOfOUlPUT= 100kHz

L...-=--o+sv
IRIG Channel 13 Demodulator

Tl/HI78SS-9

..------~--O~v

r------e-~------------

,01

470k

IN~ "",,-+--0(

a
OUTPUT

-+____

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~-~-.v

TL/HI785S-10

8-82

Applications Information
The natural bandwidth of the closed loop response may be
found from:
.

In designing with phase locked loops such as the LM565,
the important parameters of interest are:
FREE RUNNING FREQUENCY

fn =

0.3
fo "" RoCo

271"

8 =

·11
. .. (radians/sec)
K
o = OSCI ator sensitivity
volt

vOd~ts )

ra Ian

The loop gain of the LM565 is dependent on supply voltage,
and may be found from:

f - 1
n - 271"

K K _ 33.6fo
o D-

---v;;-

(loi----!.f.<~
WAVE OU7PUT

lk

Ru PIN 4 TO GROUND Illi
10kA

TLfH17854-5

TLfHf7854-8

8-87

II

~National

~ Semiconductor

LM567/LM567C Tone Decoder
General Description
The LM567 and LM567C are general purpose tone decoders deSigned to provide a saturated transistor switch to
ground when an input signal is present within the passband.
The circuit consists of an I and Q detector driven by a voltage controlled oscillator which determines the center frequency of the decoder. External components are used to
'independently set center frequency, bandwidth and output
delay.

Features
• 20 to 1 frequency range with an external resistor
• Logic compatible output with 100 mA current sinking
capability

•
•
•
•
•

Bandwidth adjustable from 0 to 14%
High rejection of out of band signals and noise
Immunity to false signals
Highly stable center frequency
Center frequency adjustable from 0.01 Hz to 500 kHz

Applications
•
•
•
•
•
•
•

Touch tone decoding
Precision oscillator
Frequency monitoring and control
Wide band FSK demodulation
Ultrasonic controls
Carrier current remote controls
Communications paging decoders

Connection Diagrams
Metal can Package

Dual-In-Llne and Small Outline Packages

OUTPUT

+----9-1

OUTPUT .....
'

FILTER

LOOP
FILTER

2

--H--,

GNO

TIMING

INPUT

v·

CAPACITOR
5

v·

TIMING

RESISTOR

TL/H/6975-1

Top VIew

TLlH/6975-2

Top View

Order Number LM567H or LM567CH
See NS Package Number H06C

Order Number LM567CM
See NS Package Number MOBA
Order Number LM567CN
See NS Package Number NOBE

8-88

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Pin
9V

Power Dissipation (Note 1)
Ve
Va
Va
Storage Temperature Range
Operating Temperature Range
LM567H
LM567CH, LM567CM, LM567CN

Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
260"C
Small Outline Package
Vapor Phase (60 sec.)
215'C
220"C
Infrared (15 sec.)
See AJI.·450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surlace mount devices.

1100mW
15V
-10V
V4 + 0.5V
-65'C to + 150"C
- 55'C to + 125'C
O'Cto +70"C

Electrical Characteristics ACTestCircuit, TA =
Parameters

25'C, v+ = 5V

Power Supply Voltage Range
Power Supply Current
Quiescent

RL = 20k

Power Supply Current
Activated

RL = 20k

Input Resistance
IL = 100 mA, fi = 10

Largest No Output Input Voltage

Ie = 100 mA, fi = 10

Typ

Max

Min

Typ

Max

4.75

5.0

9.0

4.75

5.0

9.0

V

6

8

7

10

mA

11

13

12

15

mA

25

mVrms

10

Bn = 140kHz
12

Largest Detection Bandwidth Skew
Largest Detection Bandwidth Variation with
Temperature

15

15

10

15

mVrms

6

6

dB

-6

-6

dB

14

16

1

2

±1

Highest Center Frequency

100
0

80D

!::

i
c

~

0.1

;;;

200

0

10 . . .

w

II:

L-~__~_L-~-L~

o

&

10

1&

20

2&

3D

3&

10

OUTPUT VOLTAGU VPINI (VI

110

'L -EXTERNAL LOAD CURRENT (mAl
TUH/5177-4

Circuit Description
(Refer to Block and Connection Diagram)
The LM1851 operates from 26V as set by an internal shunt
regulator, 03. In the absence of a fault (If= 0) the feedback
path status signal (Vs) is correspondingly zero. Under these
conditions the capacitor discharge current, 11, sits quiescently at three times its threshold value, ITH' so that noise
induced charge on the timing capacitor will be rapidly removed. When a fault current, If, is induced in the secondary
of the external sense transformer, the operational amplifier,
A 1, uses feedback to force a virtual ground at the input as it

extracts If. The presence of If during either half-cycle will
cause Vs to go high, which in turn changes 11 from 31TH to
ITH. Although ITH discharges the timing capacitor during
both half-cycles of the line, If only charges the capacitor
during the half-cycle in which If exits pin 2. Thus during one
haH-cycle If-ITH charges the timing capacitor, while during
the other half-cycle ITH discharges it. When the capacitor
voltage reaches 17.5V, the latch engages and turns off 03
permitting 12 to drive the gate of an SCR.

•
8-97

Application Circuits
A typical ground fault interrupter circuit Is shown in Figure 2.
It is designed to operate on 120 VAC line voltage with 5 mA
normal fault sensitivity.

start-up (S1 closure) with both a heavy normal fault and a
20 grounded neutral fault present. This situation is shown diagramatically below.

('

A full-wave rectifier bridge and a 15k/2W resistor are used
to supply the DC power required by the IC. A 1 p.F capaCitor
at pin 8 used to filter the ripple of the supply voltage and is
also connected across the SCR to allow firing of the SCR on
either half-cycle. When a fault causes the SCR to trigger,
the circuit breaker is energized and line voltage is removed
from the load. At this time no fault current flows and the IC
discharge current increases from ITH to 31TH (see Circuit
Description and Block Diagram). This quickly resets both
the timing capacitor and the output latch. At this time the
circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A
1000:1 sense transformer is used to detect the normal fault.
The fault current, which is basically the difference current
between the hot and neutral lines, Is stepped down by 1000
and fed Into the input pins of the operational amplifier
through a 10 p.F capacitor. The 0.0033 p.F capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4
are added to obtain better noise immunity. The normal fault
sensitivity is determined by the timing capaCitor discharging
current, ITH. ITH can be calculated by:
7V
ITH=--+2
(1)
RSET
At the decision pOint, the average fault current just equals
the threshold current, ITH.
I = II(rmsl
TH
2

xo.91

LINE. ""

TL/H/5177-5

-3 ms GFI turn-on time (15k and 1 p.F)
- 8 ms Potential loss of one half-cycle due to fault current
sense of half-cycles only
-4 ms Time required to open a sluggish circuit breaker
s: 10 ms Maximum integration time that could be allowed
8 ms Value of integration time that accommodates component tolerances and other variables

5

m:~ 0.91

(5)

V

where T = Integration time
V = threshold voltage
I = average fault current into Ct
1=

(3)

1.5M 0

xT

Ct = I

For example, to obtain 5 mA(rms) sensitivity for the circuit in
Figure 2 we have:
RSET

I NEUTRAL

UL943 specifies s: 25 ms average trip time under these conditions. Calculation of CI based upon charging currents due
to normal fault only is as follows:
s: 25 ms Specification

(2)

II(nnS~~0.91

GFI

NEUTRAL

where II(nnS) is the rms input fault current to the operational
amp and the factor of 2 Is due to the fact that II charges the
timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have
RSET

HOT

e>-!!2!.

(120 ,,:~(rmSI )

,

•

,(RG~•

X

)

heavy fault
current generated
(swamps ITH)

(4)

1000
The correct value for RSET can also be determined from the
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of RSET depends on the specific sense transformer used and LM1851
tolerances. Inasmuch as UL943 specifies a sensitivity "window" of 4 mA-6 mA, provision should be made to adjust
RSET on a per-product basis.
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
capacitor, Ct. Due to the large number of variables involved,
proper selection of Ct is best done empirically. The following
design example, then should only be used as a guideline.
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GF1

,

X

(

Hurn )
1000 turns X

•

current
division of
input sense
transformer
therefore:

r'.

[

8-98

G)
'-r-J
Ct charging
on halfcycles only

(~~) X (1.60~~.4) x (10~O) x
17.5

"I

Ct=

}

0.01 p.F

RJ
)

portion of
fault current
shunted
around GFI

X

(0.91)

(6)

'-.,-)
rmsto
average
conversion

m

X(O.911] xO.oooa
(7)

,-----------------------------------------------------------------------------, r
!i:

Application Circuits (Continued)

in practice, the actual value of C1 will have to be modified to
include the effects of the neutral loop upon the net charging
current. The effect of neutral loop induced currents is difficult to quantize, but typically they sum with normal fault currents, thus allowing a larger value of C1.
For UL943 requirements, 0.015 /JoF has been found to be
the best compromise between timing and noise.

For those GFI standards not requiring grounded neutral detection, a still larger value capacitor can be used and better
noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing
the full fault current, I, to enter the GFI.
In Figure 2, grounded neutral detection is accomplished by
feeding the neutral coil with 120 Hz energy continuously and
allowing some of the energy to couple into the sense transformer during conditions of neutral fault.

Typical Application
SENSE
COIL

GNo/NEUTRAL
COIL

LOAD {

HOT

} LINE

---t---- 7.0V) and low values of timing capacitor (Or < 0.1 ,.Fl, a 600 pF capacitor may need to be connected
from pin 14 to ground to ensure proper operation.

Cr

8-102

Electrical Characteristics
TA = + 25°C, Vee = +5.0V, R = 10 kO, C =0.1 p.F, unless otherwise specified. See Block Diagram.

I

Symbol

I

Characteristic

I

Conditions

Min

I

Typ

I

Max

I

Units

TRIGGER/RESET CONTROLS
VTR

Trigger Threshold

Measured at Pin 11,
VRS = OV

ITR

Trigger Current

VRS = OV, VTR = 2.0V

10

p.A

ZT

Trigger Impedance

25

kO

tRSPT

Trigger Response Time
(Note 7)

1.0

p.s

VRS

Reset Threshold

Measured at Pin 10, VTR = OV

1.4

IR

Reset Current

VTR = OV, VRS = 2.0V

10

p.A

1.4

2.0

V

2.0

V

ZR

Reset Impedance

25

kO

tRSPT

Reset Response Time
(Note 7)

0.8

p.s

1.5

MHz

20

kO

1.4

V

COUNTER
TRMAX

Max Toggle Rate

Measured at Pin 14
VRS = OV, VTR = 5.0V

ZI

Input Impedance

VTH

Input Threshold

tr

Output Rise Time

11

Output Fall Time

Measured at Pins 1 through 8
RL = 3.0 kO, CL = 10 pF

10 -

Sink Current

VOL

1.0

180

ns

180

s: 0.4V

2.0

4.0

mA

0.Q1
Leakage Current
VOH = 15V
ICEX
Note 7: Propagation delay from application of trigger or reeetinput to corresponding state change In counter output at Pin 1.

15

p.A

Block Diagram

Rl
5kA

R
MOD
IN

~.
~

+

R2

~

(

I--

~

(
11ME BASE

18

+2

-U"

our

CONTROL
LOGIC

+2

-r--IS--- f

f
./"

5kA .......

---.

REGULATOR

:--L

rr=
~ ---s- _ ::1

f

R3

+2

I
I
I
I
I
I
I

---IS---~
~

...L

~

COMP2

"'-RC

G!D

~

~7V

FLlP-FI.OI'

8.59 kA

1 I.

,
I

rVcc

0~1.

0
0

BINARY
COUNTER

O2

0

128

'1'

i--RESET
I-- TRIGGER IN

.1 CONTROL
FLIP-FLOP
TL/H/I 0837-2

8·103

Typical Performance Characteristics
Supply Current
va Supply Voltage
In Reset Condition

Recommended Range of
Timing Component
Values (Note 7)

Time-Baae Period
va External RC

1l1li

1

".

12

1

I

./

~

o

o

I

I

I

~

V

246

1.l1li

CI
I

V

'a

10111c

I
Ij

lC1c

~

i

8

m~

SUPPLY VOLTAGE -

~

1.C1c
100

~

~

~

QII01 0.01

v

Minimum Trigger and Reset
Pulse Widths va Trigger
and Reaet Amplitude
3D

0.1

10

1.0

100 1000

TIMING CAPAC1TOR - pi"

TIME BASE PERIOO

Minimum TriggerlRetrigger
Timing vs Timing
Capacitor

Time-Base Period
Drift vs Supply
Voltage
3D

700c

I

~

\

ooc.

2S'C

\ .......

~

700C
2S'C

ooc

- r---

C=O.lpF
R=10kA

-2.0

1.0
1.0

1.5

2.5

1R1GGER OR RE5ET AIIPUIUDE -

3D

2.5

10

4

v

Normalized Change in
Time-Base Period
va Modulation Voltage

./

o
1

V

/

If

.

20

,.

I

0.01 '--_.1...-"':=:::"":=-'-_....1
0.D1
0.1
100

S

1.0

~
~

~/

TIMING CAPAC1TOR - pF

-1.0

o

a

~r

::f:'.'..

R=10t.tD. "

I
50
TEMPERATURE - 'C

Time-Base Period
va Temperature
2.0

Vcc=15V
C=O.1 pi"

I

I

...........
............

-3D

..

Vcc=5V
C=O.1 pF

111-20

MDDULA110II VOLTAGE - V

14

Time·Baae Period
va Temperature

I!;

4

12

I

5UPPLY VOLTAGE-V

I

Vcc = 5V/

100 R=101l.1l

I

~

~

1.0

-

l
-~t-···

R=l k A-

R=10Mf~

'.

100

I
50

75

100

TEMPERATURE - 'C

TLlH/l0B37-3

8·104

,-----------------------------------------------------------------------------, r
iii!:

Functional Description
11

(Figure 3). The circuit starts timing when a trigger is applied
and automatically resets itself to complete the timing cycle
when a programmed count is completed. Each of the various multiplies of T shown at the LM2240's outputs in Figure
3 represent the duration of time, after a trigger pulse, that
that particular output is low (it's not the period of the waveform) if the output is not tied to any other outputs. To represents the duration of time that the circuit output, which is the
common pOint of all the counter outputs which are shorted
together, is low. If none of the counter outputs are connected back to the reset terminal (switch 51 open), the circuit
operates in an astable or free running mode, following a
trigger input.

12

13

TRIG
LM2240

VR[G

15

10

14 1 2

3

4

5

6

7

8
TL/H/l0837-4

Vee ~ Pin 16
GND ~ Pin 9

FIGURE 1. Logie Symbol
When power is applied to the LM2240 with no trigger or
reset inputs activated, the circuit starts with all outputs
HIGH. Application of a positive going trigger pulse to the
trigger pin initiates the timing cycle. The trigger input activates the time-base oscillator, enables the counter section
and sets the counter outputs LOW. The time-base oscillator
generates timing pulses with a period T = 1 RC; this is the
period of the waveform appearing at pin 14. These clock
pulses are counted by the binary counter section. The timing sequence is completed when a positive going reset
pulse is applied to the Reset pin.

.---------------~r_--v~
RL
10kA

~C

TRIGGER

13
RC

I1..
_ _ _""""'" TRIG

LM2240

RESET _ _ _....:1"10 R

V

REG

I1..

Once triggered, the circuit is immune from additional trigger
inputs until the timing cycle is completed or a reset input is
applied. If both the reset and trigger are activated simultaneOUSly, the trigger takes precedence.

15

20kA
47k4

Figure 2 gives the timing sequence of output waveforms at
various circuit terminals, subsequent to a trigger input.
When the circuit is in a reset state, both the time-base and
the counter sections are disabled and all the counter outputs are HIGH.

IT 7.0V) and low
values of timing capacHor (Cr < 0.1 "Fl, the pulse width of TBO
may be too narrow to trigger the counter section. This can be cor-

1 PIN 4

rected by connecting a 600 pF capacitor from TBO (pin 14) to
ground (pin 9).

L -________ I PIN 5

TL/H/I 0837-5

Reset (pin 10) stops the time-base oscillator.

FIGURE 2. Timing Diagram of Output Waveforms

Outputs (00 ... 0128) (pins 1-8) sink 2.0 mA current with
VOL';;: O.4V.

In monostable applications, one or more of the counter outputs are connected to the reset terminal with 51 closed

For use with external clock, minimum clock pulse amplitude
should be 3.0V, with greater than 1.0 ,...s pulse duration.

8-105

N
N
.Do
CI

C)

~

C'I

::::Ii!

...I

r---------------------------------------------------------------------------------,
Circuit Controls
B *20r--;---r--,---,---,--,

Counter Outputs (00 ••• 0128, Plns1 thru 8)
The binary counter outputs are buffered open collector type
stages, as shown in the block diagram. Each output is capable of sinking 2.0 mA at 0.4V VOL. In the reset condition, all
the counter outputs are HIGH or in the nonconducting state.
Following a trigger input, the outputs change state in accordance with the timing diagram of Figure 2. The counter
outputs can be used individually, or can be connected together in a wired-OR configuration, as described in the programming segment of this datasheet.

e:

!*

161-\-t
\-+--1--+-+--1

1=

~I
~

Z

~

---

l

TL/H/1 0837-7

m

s:

o

6
8
10
12
2
"
RATIO Of SYNC-PULSE PERIOD TO
TIME-BASE PERIOD - Tstr

When using high supply voltage (Vee> 7.0V) and a small
value timing capacitor (CT < 0.1 ,...Fl, the pulse width at
TBO pin 14 may be too narrow to trigger the counter section. This can be corrected by connecting a 600 pF capacitor from pin 14 to ground.

= (TS/m)
s:

1-

Tlme·Base Output (TBO, Pin 14)
The time-base output is an open-collector type stage as
shown in the block diagram, and requires a 20 kO pull-up
resistor to pin 15 for proper circuit operation. In the reset
state, the time-base output is HIGH. After triggering, it produces a negative-going pulse train with a period T = RC, as
shown in the diagram of Figure 2. The time-base output is
internally connected to the binary counter section and can
also serve as the input for the external clock signal when
the circuit is operated with an external time base. The counter section triggers on the negative-going edge of the timing
or clock pulses generated at TBO, pin 14. The trigger
threshold for the counter section Is :::: + 1.4V. The counter
section can be disabled by clamping the voltage level at pin
14 to ground.

FIGURE 4. Operation with External Sync Signal
The time-base can be synchronized by setting the sync
pulse period (Ts) to be an integer multiple of T. This can be
done by choosing the timing components Rand C at pin 13
such that:

m is an integer, 1

--

O~~--~--~--~--~~

TLlH/10837-8

rSYNC ~~F
~11-"""""",",,12...1LW22040

T = RC
where:

',~

U t---t---r--+--T"....-..d---,

FIGURE 5. Typical Pull·ln Range
for Harmonic Synchronization

The oscillator time-base period (T) can be modulated by
applying a DC voltage to MOD, pin 12 (see Performance
Curves). Also, the time-base oscillator can be synchronized
to an external clock by applying a sync pulse to MOD, pin 12
as shown In Figure 4. Recommended sync pulse widths and
amplitudes are also given.

5.1 kA

*8r--+---P~+-~---r--,

~

Reset and Trigger Inputs (R and TRIG, Pins 10 and 11)
The circuit is reset or triggered with positive-going control
pulses applied to pins 10 and 11 respectively. The threshold
level for these controls is approximately two diode drops (::::
lAV) above ground. Minimum pulse widths for reset and
trigger inputs are shown in the Performance Curves. Once
triggered, the circuit is immune to additional trigger inputs
until the end of the timing cycle.
Modulation and Sync Input (MOD, Pin 12)

IN

"

*12 I-;....--+---t---j---+--i

Regulator Output (VREG, Pin 15)
The regulator output VREG is used internally to power the
binary counter and the control logic. This terminal can also
be used as a supply to additional LM2240 circuits when
several timer circuits are cascaded (see Figure 6) to minimize power dissipation. For circuit operation with an external clock, VREG can be used as the Vee Input terminal so
that the internal time-base circuitry is not powered, thus reducing power dissipation. When supply voltages less than
4.5V are used with the internal time-base, pin 15 should be
shorted to pin 16.

10

Figure 5 gives the typical pull-in range for harmonic synchronization for various harmonic modulus, m. For m < 10, typical pull-In range is greater than ± 4 % of the time-base frequency.
RC Terminal (Pin 13)
The time-base period T is determined by the external RC
network connected to RC, pin 13. When the time-base is
triggered, the waveform at pin 13 is an exponential ramp
with a period T = 1 RC.

6·106

Circuit Controls (Continued)

47k4

x. C
TRIGGER~---+---------~-h

.n.

RC

MOD
Lt.l2240 #1

RESET

R

.n.

' - - - - - - - - - - - - - -.......J,Io.,.,...---.I~~_+_'_........l_-_~OUT
150k4

vcc
GND

~
~

Pin 16
Pin 9

TL/H/10837-9

FIGURE 6. Low Power Operation of Cascaded Timers

Monostable Operation
two cascaded units can be programmed from To = 256 RC
to To = 65,280 RC in 256 discrete steps by selectively
shorting one or more of the counter outputs from Unit 2 to
the output bus. In this application, the reset and the trigger
terminals of both units are tied together and the Unit 2 time
base is disabled. Normally, the output is HIGH when the
system is reset. On triggering, the output goes LOW where it
remains for a total of 256 (255) or 65,280 cycles of the timebase oscillator.
In cascaded operation, the time-base section of Unit 2 can
be powered down to reduce power consumption by using
the circuit connection of Figure 6. In this case, the Vee terminal (pin 16) of Unit 2 is left open, and the second unit is
powered from the regulator output of Unit 1 by connecting
the VREG (pin 15) of both units together.

Precision Timing
In precision timing applications, the LM2240 is used in its
monostable, or self·resetting, mode. The generalized circuit
connection for this application is shown in Rgure 3
(51 closed). The output is normally HIGH and goes LOW
following a trigger input. It remains LOW for the time dura·
tion (To) and then returns to a HIGH state. The duration of
the timing cycle To is given as:

To = nT = NRC
where T = RC is the time-base period as set by the choice
of timing components at RC pin 13 (see Performance
Curves) and n is an integer in the range of 1 :s;; n :s;; 255 as
determined by the combination of counter outputs (00 ...
0128), pins 1 through 8 connected to the output bus.
Counter Output Programming
The binary counter outputs, 00 ... 0128, pins 1 through 8
are open collector type stages and can be shorted together
to a common pull-up resistor to form a wired-OR connection; the combined output will be LOW as long as anyone of
the outputs is LOW The time delays associated with each
counter output can thus be added together. This is done by
Simply shorting the outputs together to form a common output bus as shown in Figure 3. For example, if only pin 6 is
connected to the output and the rest left open, the total
duration of the timing cycle, To, is 32T. Similarly, if pins I, 5,
and 6 are shorted to the output bus, the total time delay is
To = (1 + 16 + 32) T = 49T. In this manner, by proper
choice of counter terminals connected to the output bus,
the timing cycle can be programmed to be 1T :s;; To
:s;; 255T.

Astable Operation
The LM2240 can be operated in its astable or free running
mode by disconnecting the reset terminal (pin 10) from the
counter outputs. Two typical circuits are shown in Rgures 8
and 9. The circuit in Figure 8 operates in its free running
mode with external trigger and reset signals. It starts counting and timing following a trigger input until an external reset
pulse is applied. Upon application of a positive going reset
signal to pin 10, the circuit reverts back to its reset state.
This circuit is essentially the same as that of Figure 3 with
the feedback switch 51 open.
The circuit of Figure 9 is designed for continuous operation.
It self triggers automatically when the power supply is
turned on, and continues to operate in its free running mode
indefinitely. In astable or free running operation, each of the
counter outputs can be used individually as synchronized
oscillators, or they can be interconnected to generate complex pulse patterns.

Ultra Long Time Delay Application

Two LM2240 units can be cascaded as shown in Figure 7to
generate extremely long time delays. Total timing cycle of

8-107

•

Astable Operation (Continued)
lit.

47k4

10k4

RC

TRIGGER

!RIG

Il.

LM2240 #2

LM2240 ,I

RES£! ......--------------

1:=='""

-1S'~1ii!i

>

~

~

-4, C

...e
!

-r'ci

ffi

~

7.&0

7.58

7.54

11
Il

V

, LM2I17 14701ll

" I'..

i 0.111

'.918

-35 -15

5

...

~

LM2I07

~UH
::; O.IIM

25

4S

'"

~

"

15

15"C ~ IS'C

~f"

180

120
15

0.1

0.'

Cl • 0.05 on'dl-+-+-t--i
I-+--l-+- lNlZ9171470!!)-

;", - ::: tj::;j~~~;;t::t:j

_
...

LM2!107

I-+--l-+--I--...JI-+--l
~ 0.2 ~+--j-+--+-I-+--j
0.11-+-+-1-+-1--1--1
0.3

-35 -15

5

25

45

65

...i!
..::l
ill
~
iii

:::;

D.I
0.7

:

;

3&

~

34

,.

...'"

D.l

5

Rl-1Ok
Cl =D.'1 mFd

~_

.

38
28

...

1&

~

:;

~

24V

25

J
I

~

>

IV

45

65

..
.~

d.•

"...:::;

0.5
0.3

15

85

65

85

Vee" 12V
f= looDHz

RIC1" 3.0 - 3.5ms

~ r-....

L~~

~

0.2
0.1

85

LM211~47a!!1

I
lOOk

lOOk

30m.

40Gk

501k

RI (!!I

Op Amp Output Tranalator
Characteristics
1.1
1.&

LM2I07

'7

2.2

.....
",..

1.1

-4O'C ....

I.'

_25"C ....

1.0

'5

Z.O

1.0

12
45

~
iii

::l

J

I.'
1.8

Z5

0.7
0.6

Op Amp Output Transistor
Characteristics

~

.....

25

1.0
0.1
0.8

0
5

5

TEMPERATURE ,-C)

/. V':i""
I&V
12 /:
5

t- t-

LM2107

-35 -15

~

TEMPERATURE rCI

-35 -15

.i!
:

0.2

85

V 1/

10
-65 -35 -15

120

Tachometer Linearity vs R1

L~ZI17I1470!:' -

0.4

!

~
~

TEMPERATURE f-C)

I
I

Vee" 'IV

'-'OOOH,

3.0
1.1
1.6

./

12VV
IV.V"

0.5

Tachometer Input Hysteresis
vs Temperature

32

20V

1&0
1'0

0.6

0.3

85

~

: zoo

1--1--'

TUtpERATURE I·CI

~

...

:; "0

-40'C

I-"

1.0
0.1

IS

,r

Ii lID

Tachometer Linearity
vs Temperature

Vee" f2V
1=200 Hl
At" 10k

45

~

28~

SUPPLY VOLTAGE (VI

1.0 r-""T'"--r--r--r-r--r-,

~

t-~V

'"

i-'

b:::

210

& I 10 12 I' 1& 11 20 21 24 1& 21

Tachometer Linearity
vs Temperature

25

Tachometer Currents 12
and 13 vs Temperature

240

~

22D

1.0

5

TEIlt'ERATURE rCI

280

100

1&0

"
-35 -11

IS

15

i.I'

TEMPERATURE t·C)

-.

45

240

...;;;

........

un

210

~jIO..,

~U9.

0.9

25

2&0

.....

cUlm

;1.111

Tachometer Currents 12
and 13 vs Supply Voltage

~ 1.000

0.'

i

I I

Normalized Tachometer
Output vs Temperature
FREQUENCY' zoo H.

LM2I17

~

0....
:; '.114

TT

-35 -15

1""'.:::1
1.MZID7'
..L

=

TEMPERATURE rCI

1.002

~

~ 0. •

SUPPLY VOLTAGE IV)

ffi 1.004

~

I ~::

Il~ .... ~,

7.4&

FRjUENCY • 1000 H.

1.106

ffi 1.DD4

IL

nOn

7.41

6 8 .8 12 .4 16 18 20 22 24 2& 28

II.

4Jlu

1.56

~ 7.52
7.SD

I
I

5'·006

==

EUDI

Vee" 1ZV

7.12

1...

~

g 1.010

7.&&

I

f

Normalized Tachometer
Output vs Temperature

i-""

..... 10'

~r2l17 TVl7fl
~

10

20

~

12

40

SOURCE CURRENT (mAl

Ji':2
~.~

1.0

!""': ~~

0.8
0.&

i"': ..... ~

D.•

0.2

I I
36

1.4

~
.J

~

+IVC

~

50

~;..-

~

10

10

3D

40

51

SINK CURRENT lonAI

TL/HI7942-5

8-113

Ell

....

~ r---------------------------------------------------------------------~

~

~

i

~

Applications Information
The LM2907 series of tachometer circuits is designed for
minimum external part count applications and maximum versatility. In order to fully exploit its features and advantages
let's examine its theory of operation. The first stage of operation Is a differential amplifier driving a positive feedback
flip-flop circuit. The Input threshold voltage is the amount of
differential Input voltage at which the output of this stage
changes state. Two options (LM2907-8, LM2917-8) have
one Input internally grounded so that an input signal must
swing above and below ground and exceed the Input
thresholds to produce an output. This Is offered specifically
for magnetic variable reluctance pickups which typically provide a single-ended ac output. This single input is also fully
protected against voltage swings to ±28V, which are easily
attained with these types of pickups.
The differential input options (LM2907, LM2917) give the
user the option of setting his own input switching level and
still have the hysteresis around that level for excellent noise
rejection in any application. Of course in order to allow the
inputs to attain common-mode voltages above ground, input
protection is removed and neither input should be taken
outside the limits of the supply voltage being used. It is very
important that an input not go below ground without some
resistance in Its lead to limit the current that will then flow in
the epi-substrate diode.
Following the input stage is the charge pump where the
input frequency is converted to a dc voltage. To do this
requires one timing capacitor, one output resistor, and an
integrating or filter capaCitor. When the input stage changes
state (due to a suitable zero crossing or differential voltage
on the input) the timing capaCitor is either charged or discharged linearly between two voltages whose difference is
Vee/2. Then in one half cycle of the input frequency or a
time equal to 1/2 fiN the change in charge on the timing
capaCitor is equal to Vee/2 x C1. The average amount of
current pumped into or out of the capacitor then is:
AQ .
Vee
= 'e(AVG) = C1 x
x (2fIN) = Vee x fiN X C1

T

The size of C2 is dependent only on the amount of ripple
voltage allowable and the required response time.

CHOOSING R1 AND C1
There are some limitations on the choice of R1 and C1
which should be considered for optimum performance. The
timing capaCitor also provides internal compensation for the
charge pump and should be kept larger than 500 pF for very
accurate operation. Smaller values can cause an error current on R1, especially at low temperatures. Several considerations must be met when choosing R1. The output current
at pin 3 is Internally fixed and therefore Vo/R1 must be less
than or equal to this value. If R1 Is too large, It can become
a Significant fraction of the output impedance at pin 3 which
degrades linearity. Also output ripple voltage must be considered and the size of C2 is affected by R1. An expression
that describes the ripple content on pin 3 for a single R1 C2
combination is:
VRIPPLE =

Vee C1
(
""2
x C2 x 1 -

Vee x fiN x C1)
12
pk-pk

It appears R1 can be chosen Independent of ripple, however response time, or the time it takes VOUT to stabilize at a
new voltage Increases as the size of C2 increases, so a
compromise between ripple, response time, and linearity
must be chosen carefully.
As a final consideration, the maximum attainable input frequency is determined by Vee, C1 and 12:
f

12
MAX - C1 X Vee

USING ZENER REGULATED OPTIONS (LM2917)
For those applications where an output voltage or current
must be obtained independent of supply voltage variations,
the LM2917 Is offered. The most important consideration in
choosing a dropping resistor from the unregulated supply to
the device is that the tachometer and op amp circuitry alone
require about 3 mA at the voltage level provided by the
zener. At low supply voltages there must be some current
flowing in the resistor above the 3 mA circuit current to operate the regulator. As an example, if the raw supply varies
from 9V to 16V, a resistance of 4700 will minimize the zener voltage variation to 160 mV. If the resistance goes under 4000 or over 6000 the zener variation quickly rises
above 200 mV for the same input variation.

""2

The output circuit mirrors this current very accurately into
the load resistor R1, connected to ground, such that if the
pulses of current are integrated with a filter capacitor, then
Vo = ie x R1, and the total conversion equation becomes:
Vo = Vee x fiN x C1 X R1 X K
Where K is the gain constant-typically 1.0.

Typical Applications
Minimum Component Tachometer
Vee

~

15V

+Vour - 87 Hz/V

fINI"PMI

10k

TL/HI7942-8

8-114

Typical Applications (Continued)
1

"Speed Switch" Load 1& Energized When fiN :;;: 2RC
5k

5k

r--------....-<> vee

= 8-24V

TUH/7942-9

Zener Regulated Frequency to Voltage Converter
vee = 12V

+ Your = 88 Hz/V
IDle

TL/HI7942-10

Breaker Point Dwell Meter

B+.-----------~----------------~--__,
10k

470

POINTS.------,

GROUNO~

TL/HI7942-11

8-115

•

Typical Applications (Continued)
Voltage Driven Meter Indicating Engine RPM
Vo = 6V @ 400 Hz or 6000 ERPM (8 Cylinder Engine)
B+o-----~~----------~t_--------------~t_--__,
DISTRIBUTOR

P

~REAKER~
POINTS

1

VOUT

TL/H17942-12

Current Driven Meter Indicating Engine RPM
10 = 10 mA @ 300 Hz or 6000 ERPM (6 Cylinder Engine)
B+o-------~----------------~----_,
10k

BREAKER
POINTS
10k

OoOZ.FT

20k

":"

"::"

TLlHI7942-13

Capacitance Meter
VOUT = 1V-10VtorCx = 0.01 to 0.1 mFd
(R = 111k)
ISV

SDk

+

Sk

VOUT

TL/HI7942-14

8-116

Typical Applications (Continued)
Two-Wire Remote Speed Switch

..---U..- - - - - - - - O G N D

TUH/7942-15

100 Cycle Delay Switch
Vee

V3

Ie

V3 steps up in voltage by the amount

Vee X Cl
C
2

100

NO.
OF CYCLES

for each complete input cycle (2 zero crossings)

TL/HI7942-16

Example:
If C2 = 200 CI after 100 consecutive input cycles.
V3 = 112 Vee

EI
8-117

Typical Applications (Continued)
Variable Reluctance Magnetic Pickup Buffer Circuits
Precision two-shot output frequency
equals Iwios Input frequency.
Pulse width

= Vee 2!..

Pulse height

2 12

= VZENER
VARIABLE

~
fo)

R~~~c,:E~~~E
PICKUP

~
fo)

,.. lUU1.

VARIABLE
RELUCTANCE
MA •• ETIC
PICKUP ~1

TLlHI7942-39

TUHI7942-17

Finger Touch or Contact Switch
, - - - - - - - -....- - - - 0 5 TO 15V
Q

INPUT
168Hz)
CONTACT
PLATE

Q

••
TLlH/7942-19

TLlHI7942-18

Flashing LED Indicates Overspeed
---4~---------~

__

-014V

438

68

150

fiN

Flashing begins when ~N ;;" 100 Hz.

/j;

Flash rate increases with input frequency
increase beyond trip point

LEO

TLlHI7942-20

8-118

Typical Applications (Continued)
Frequency to Voltage Converter with 2 Pole Butterworth Filter to Reduce Ripple
Vee

lIN

I

_ 0.707

POLE - 21TAC
2.57

TRESPONSE ~ 21T1POLE

R

+

2C
10k

VOUT

TLlHI7942-21

Overspeed Latch
Vee

470

R2

VOUT

Rl

lIN
Output latches when

r

A2

I
fiN ~ AI + A2AC
Aeset by removing Vee.

R

TLlHI7942-22

8-119

TLlH/7942-23

,... ;---------------------------------------------------------------------------------,
~

~

~

i

Typical Applications (Continued)
Some Frequency Switch Applications May Require Hysteresis In the
Comparetor Function Which can be Implemented In Several Ways:
1!V

~
50

lilk

47D

IDDk

'='

J

IA
'""

TLfHf7942-24

12V

VREF =6V

12V

'SIk
47k

+
VOUT

..

2k

T

'='

YREF =8V

I..

+

I r

VOUT

'='

'='

TLfHf7942-25

TLfHf7942-28

VOUT

18.51--...._

12V

D.I
5.M I.DI

V3

t::=~===:i

__
V3

TUHf7942-27

TLfHf7942-28

8-120

Typical Applications (Continued)
Changing the Output Voltage for an Input Frequency of Zero
....- - - - - O I O V

VOUT

f,N

0--"'"
+
10k VOUT

I

2 3 4

5 & 1

f,N IkH.)

TL/HI7942-30

zoo

TlIHI7942-29

Changing Tachometer Gain Curve or Clamping the Minimum Output Voltage
IOV

VOUT

av

3Vt----~

zv

t - -__,

IV

f'N 1kHz)
TUH/7942-32

•

TUH/7942-31

8-121

Anti-Skid Circuit Functions
"Select-Low" Circuit,

v~o_------------------------~----------------------------..,
WHEElI:~U~

o_------------------------+--------....,

WHEEl SPEED

TLlHI7942-34

"

r-~~~----~t_----~~--------~------------6+
Ok

YOUT

VOUT is pro~rtional to the lower of the

two input wheel speeds.

TL/H/7942-33

"Select-High" Circuit

vcco_------------------------~----------------------------_,

WHEElI:~O~o-------------------------+--------.....,

TL/HI7942-36

VOUT Is proportional to the higher of
the two input wheel speeds.

TL/HI7942-35

"Select-Average" Circuit

vcco_--------------------------.-------______________________

~~

',0_------------+-----.,
',0_---------+----.,

p

c

+

L-_ _ _ _ _ _....J

VOUT :: YccRClf 1 + '21

TL/H/7942-37

8-122

m
.a

,

OP AMP COFl,PARATDR

10

1

,

,

,

~'

""

CD

:::J

1

1

I
I
I

I
I
I
I

c

r;:,--------------,
79
1

BIAS

r-----,

034

I

1
1

t J)

n

:::r
CD

3

":"1
I

 55'C
750
T A = 25'C to 75'C
300
mW
TA> 75'C
Derate at 8
mWI"C
Collector to Emitter Voltage, VCEO

15

15

V

Collector to Base Voltage, VCBO

20

20

V

Collector to Substrate Voltage, VCIO (Note 1)

20

20

V

5

5

V

Collector Current, Ic

50

50

mA

Operating Temperature Range

- 55'C to + 125'C

-40'Cto +85'C

Storage Temperature Range

- 65'C to + 150'C

- 65'C to + 85'C

Emitter to Base Voltage, VEBO

Soldering Information
Dual-In-Line Package Soldering (10 Sec.)

260'C

260'C

Small Outline Package
Vapor Phase (60 Seconds)
215'C
Infrared (15 Seconds)
220'C
See AN-450 "Surface Mounting Methods and Their Effect on Product Reliability" for other methods of soldering surface mount
devices.

Electrical Characteristics (TA =
Parameter

25'C unless otherwise specified)

Conditions

Limits

Limits

LM3045, LM3046

LM3086

Min

Typ

Max

Min

Typ

Units
Max

Collector to Base Breakdown Voltage (V(BR)CBO)

IC = 10 IJA, IE = 0

20

60

20

60

V

Collector to Emitter Breakdown Voltage (V(BR)CEO)

Ic = 1 mA, IB = 0

15

24

15

24

V

Collector to Substrate Breakdown
Voltage (V(BR)CIO)

Ic = 10",A,lcl = 0

20

60

20

60

V

5

7

5

7

Emitter to Base Breakdown Voltage (V(BR)EBO)

IE101JA,lc=0

Collector Cutoff Current (ICBO)

VCB = 10V,IE = 0

Collector Cutoff Current (ICEO)

VCE = 10V,IB = 0

Static Forward Current Transfer
Ratio (Static Beta) (hFE)

VCE = 3V

{'C = 10mA
Ic= 1 mA
Ic = 10 ",A

Input Offset Current for Matched
Pair 01 and 021101 - 11021

VCE = 3V, Ic = 1 mA

Base to Emitter Voltage (VBE)

VCE = 3V

{IE = 1 mA
IE = 10mA

Magnitude of Input Offset Voltage for
Differential Pair IVBE1 - VBE21

VCE = 3V, Ic = 1 mA

Magnitude of Input Offset Voltage for Isolated
Transistors IVBE3 - VBE41,IvBE4 - VBE51,
IVBE5 - VBE31

VCE = 3V, Ic = 1 mA

Temperature Coefficient of Base to
Emitter Voltage (~~~E )

VCE = 3V, Ic = 1 mA

Collector to Emitter Saturation Voltage (VCE(SAT»)

IB = 1 mA, Ic = 10 mA

Temperature 'Coefficient of
Input Offset Voltage (~:;o)

VCE = 3V, Ic = 1 mA

0.002

40

0.002

0.5
100
40

nA

5

",A

100

100

40

54
0.3

V
100

100
54

2

",A

0.715

0.715

0.800

0.800

V

0.45

5

mV

0.45

5

mV

-1.9

-1.9

mVl'C

0.23

0.23

V

1.1

",VloC

Note 1: The collector of each transistor of the LM3045, LM3046, and LM3086 is isolated from the substrate by an integral diode. The substrate (tenminaI13) must
be connected to the most negative point in the external circuR to maintain isolation between transistors and to provide for normal transistor action.

8-125

II

Electrical Characteristics (Continued)
Parameter

Conditions

Low Frequency Noise Figure (NFl

Min

Typ

f = 1 kHz, VCE = 3V,
Ic = 100 ",A, Rs = 1 kG

Max

Units

3.25

dB

LOW FREQUENCY, SMALL SIGNAL EQUIVALENT CIRCUIT CHARACTERISTICS
Forward Current Transfer Ratio (hIe)

110 (LM3045. LM3046)
(LM3086)

f = 1 kHz, VCE = 3V.
Ic=1mA

Short Circuit Input Impednace (hie>

3.5

kG

OPen Circuit Output Impedance (hoe>

15.6

",mho

1.8x 10- 4

Open Circuit Reverse Voltage Transfer Ratio (hre)

ADMITTANCE CHARACTERISTICS
Forward Transfer Admittance (Yle)

31 - j 1.5

f = 1 MHz, VCE = 3V.
Ic=1mA

Input Admittance (Vie>

0.3+JO.04
0.001 + j 0.03

Output Admittance (Voe)
Reverse Transfer Admittance (Yre)

See Curve
300

550

Gain Bandwidth Product (iT)

VCE = 3V, Ic = 3 mA

Emitter to Base Capacitance (CES)

VES = 3V. IE = 0

0.6

Collector to Base Capacitance (Ces)

VCS = 3V, Ic = 0

0.58

pF

Collector to Substrate Capacitance (Cell

Ves = 3V, Ic = 0

2.8

pF

pF

Typical Performance Characteristics

1
~a:

...
~

Typical Collector To Base
Cutoff Current vs Ambient
Temperature for Each
Transistor
10'

1

i ~:. ~
§
10. 1

10V
5V

a:

B 10"
I

B lit'

.9

II!

•

."'
i..
.1:

25

120
18 -0

.
..

10'

100

~

~
I

III"

5V

.. 111"

-

1

75

110

125

70

25

50

75

125

100

.01

0.9

;:

g
:II

a.•

I
1

.1

TA - AMBIENT TEMPERATURE ( CI

1

I

V

50
0

/

hFEl

"FE

Jl1cr3

50

"""!.IhFEZII,

Y

0

1.1

II I

80

60

I

TA - AMBIENT TEMPERATURE rCI

IE

98

>=

VeE = 10V

Ve , '3V,
T... 25·C
I I
IIIIFf ,\ OR
hFE2

~

1

g;

110

I.

10

~
~

~

Typical Static Forward
Current-Transfer Ratio and
Beta Ratio for Transistors Q1
and Q2 vs Emitter Current

10'

oS

Ie: .,

l'

10~

Typical Collector To Emitter
Cutoff Current vs Ambient
Temperature for Each
Transistor

10

IE - EMITTER (mAl

TUH17950-2

Typical Input Offset Current

for Matched Transistor Pair
Q1 Q2 vs Collector Current

..

10

"'

.!

I.

1~

!!

.1 ~

2
I

i~
:i
l

~

.$

I

11111 1111II1U LUlIlllJ

.01
••1

.1

1

.1

I-

.

l~

Ie - COLLECTOR (.,AI

I

~

~

3

~

2

!..

1

i'

I-

I-

111111 1111I11l...-

11111111 111111111
1

..
~

.5

.1

I

!!l

INPUT OFFSET VOLTAGE

.4
.81

10

4

I

VeE -3V
T... =2&OC

~

Il-

Typical Static Base To EmlHer
Voltage Characteristic and Input
Offset Voltage for Differential
Pair and Paired Isolated
Transistors vs EmiHer Current

s

I
1.

I, - EMITTER (IIA)

TUHI7950-3

8-126

Typical Performance Characteristics

(Continued)

Typical Input Offset Voltage
Characteristics for Differential
Pair and Paired Isolated
Transistors vs Ambient
Temperature

Typical Base To Emitter
Voltage Characteristic for
Each Transistor vs Ambient
Temperature
4
VeE :::3V
~

'"~
~

e
~m

.9

~

.8
.7

~
"

P.5 ~ ~

I, '3mA
1 mA
o.,mAr

0-

I""" ~

.5

~
I

,.

25

50

:!!

I

.15

T. =25·C

,..

15 100 125

J

-15 -SO -25

0

25

50

g;
~

15

Ci

10

=

15 100 125

1kH.

,

o

lUH.

.81

.01

Ie - COLLECTOR (mAl

TA - AM81ENT TEMPERATURE (·C)

TA - AMBIENT TEMPERATURE I·C)

""

f"'8.1 kHz

~

'"

.1mA

.25

20

~

I~A

.50

o

-15 -50 -25 0

lis '&OIIIl

25
m

-- I------

2

.4

VeE ::ElY

V

Ie =l0iA

.§

l - I--

.6

I

J

;;

~~~

30

I

VeE =3V

Typical Noise Figure vs
Collector Current

TL/H/7950-4

Typical Noise Figure vs
Collector Current

Typical Noise Figure vs
Collector Current

30

20

'"m=>

15

VeE =3V

25

z

20

I,~ O.lkH./

~

1=0.1 kHz

~

0

Ci

lis = 10.00011
T•• 2I"C
11

;;;
:!!

~

il:

100 E;e;r.:--=--."......,."._m

30
VeE s3Y
lis =II101 55'C

300
mW
Derate at 6.67 mWI'C

Power Dissipation: Total Package
TA = 25"C
TA> 25'C

500
mW
Derate at 6.67 mWI'C

Collector to Emitter Voltage, VCEO

30

V

Collector to Base Voltage, VCBO

40

V

Collector to Substrate Voltage,
VCIO (Note 1)

40

V

Emitter to Base Voltage, VEBO
(Note 2)

5

V

Collector to Current, Ic

50

mA

Operating Temperature Range

-40 to +85

'C

Storage Temperature Range

-65 to

+ 150

DC Electrical Characteristics TA =
Symbol

Soldering Information
Dual-In-Une Package
Soldering (10 seconds)

260'C

Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

215'C
220'C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

'C

25'C

Parameter

Umits

Conditions
Min

Typ

Units
Max

V(BR)CBO

Collector to Base Breakdown Voltage

Ic = 10 p.A,IE = 0

40

72

V

V(BR)CEO

Collector to Emitter Breakdown Voltage

Ic = 1 mA, IB = 0

30

56

V

V(BR)CIO

Collector to Substrate Breakdown
Voltage

ICI = 10 p.A,IB = 0,
IE =0

40

72

V

V(BR)EBO

Emitter to Base Breakdown Voltage
(Note 2)

IC = O,IE = 10 p.A

5

7

V

ICBO

Collector Cutoff Current

VCB = 10V,IE = 0

0.002

100

nA

ICED

Collector Cutoff Current

VCE = 10V,IB = 0

(Note 3)

5

p.A

hFE

Static Forward Current Transfer
Ratio (Static Beta)

Ic = 10mA, VCE = 5V
Ic = 1 mA, VCE = 5V
Ic = 10 p.A, VCE = 5V

IB1-IB2

Input Offset Current for Matched
Pair Q1 and Q2

IC1 = 1C2 = 1 mA,
VCE = 5V

0.3

2

p.A

VBE

Base to Emitter Voltage

IC, = 1 rnA, VCE = 3V

0.73

0.83

V

VBE1-VBE2

Magnitude of Input Offset Voltage
for Differential Pair

VCE = 5V, IE = 1 mA

0.48

5

mV

AVBE/AT

Temperature Coefficient of Base
to Emitter Voltage

VCE = 5V, IE = 1 mA

VCE(SAT)

Collector to Emitter Saturation
Voltage

Ic = 10 mA,lB = 1 reA

AV10/AT

Temperature Coefficient of Input
Offset Voltage

Ic = 1 mA, VCE = 5V

30

0.63

(

85
100
90

-1.9

mVI'C

0.33

V

1.1

p.VI'C

Note 1: The collector 01 each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative

than any collector voltage In order to maintain isolation between transistors and provide normal transistor action. To-avoid undesired coupling between transistors.
\he substrate terminal should be maintained at eHher dc or signal (ac) ground. A suitable bypass capaooor can be 'used to establish a signal ground.
Note 2: II \he transistors are lorced Into zener breakdown (V(BR)Esol. degradation of lorward transfer current ratio (hFEl can occur.
Note 3: See curve.

8-130

AC Electrical Characteristics
Symbol

Parameter

Limits

Conditions

Typ

Min
NF

Low Frequency Noise Figure

f = 1 kHz, VCE = 5V,
Ic = 100 p.A, Rs = 1 kO

1,-

Gain Bandwidth Product

VCE = 5V, Ic = 3 mA

300

Units
Max

3.25

dB

500

MHz

CEB

Emitter to Base Capacitance

VEB = 5V, IE = 0

0.70

pF

GeB

Collector to Base Capacitance

VCB = 5V, Ic = 0

0.37

pF

Gel

Collector to Substrate Capacitance

VCI = 5V, Ic = 0

2.2

pF

Low Frequency, Small Signal Equivalent Circuit Characteristics
lite

Forward Current Transfer Ratio

f = 1 kHz, VCE = 3V, Ic = 1 mA

hie

Short Circuit Input Impedance

f = 1 kHz, VCE = 3V, Ic = 1 mA

100
3.5

kO

hoe

Open Circuit Output Impedance

f = 1 kHz, VCE = 3V, Ic = 1 mA

15.6

p.mho

hre

Open Circuit Reverse Voltage
Transfer Ratio

f = 1 kHz, VCE = 3V,
Ic=1mA

1.8 X 10- 4

Admittance Characteristics
V'e

Forward Transfer Admittance

f = 1 MHz, VCE = 3V, Ic = 1 mA

31 - j 1.5

mmho

Vie

Input Admittance

f = 1 MHz, VCE = 3V, Ie = 1 mA

mmho

V09

Output Admittance

f = 1 MHz, VCE = 3V, Ic = 1 mA

+ jO.04
0.001 + j 0.03
0.3

mmho

Reverse Transfer Admittance
(Note 3)
mmho
f = 1 MHz, VCE = 3V, Ic = 1 mA
Note 1: The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative
than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors,
the substrate terminal should be maintained at either dc or signal (ac) ground. A suitable bypass capaCitor can be used to establish a Signal ground.
Note 2: If the transistors are forced into zener breakdown (V(BR)EBO), degradation of forward transfer current ratio (hFE) can occur.

Vre

Note 3: See curve.

•
8-131

~
~

:I

Typical Performance Characteristics
1

ICEO vs T A for
Any Transistor
10'
I, -0

l-

ill

i

ICBO VS T A for
Any Transistor
!
:1~ 1 D ' ( ! " 0 ! l 1 !

1.'

10'

..
.
il

~

B

~

~

5

;'O"IIiE

tOV

10 '
5V

I

25

10"

s, 10.

10.2

15

IUD

0

.JJ

IZ&

TA - AMBIENTTEMPERATURE ( CI

~

..I!!
~_

g

0.1

~~

0.7

..
:i=
.., .
....
~i
" ..
,l'~
1!t1
t; ~

50 15 IDO 125

l

i
~.
I

US

I

)

0.50

IJA

......

I, "DiA

.

0.1

!

0.&

.... i

I

-15 -50 -25 0

25

50 15 IDO 125

T. - AM.,ENTTEMPERATURE ('CI

110 va Ic (Q1 and Q2)

«
-'>
I-

..:~

V

!!

0.1

I

,g

o

10

20

3D

40

;

NFvs Ic@ Rs = 500n
30

t
eli

..... ...j
~

2~

.~
S:i
::;

0.5

VeE" IV
Rs =5DOn
TA • HOC

25

I

~~

g;

20
1&

ii:

~z

'=0.1 kHz

10

~

~

~

I.

D.4

om

10

0.1
Ie - COLLECTOR CURRENT (mAl

VBE and VIO vs
IE for Q1 and Q2

~

E

o.1mA

j a.zl

•

-I---'

0..

I

I

Ie - COLLECTOR CURRENT (mAl

Ie - COLLECTOR CURRENT (mAl

VIOvsTA forQ1 and Q2
Vel'" IV

V

10

0.1

0.25

TA - AMBIENTTEMPERATURE ('CI

4

1

I/hFE""O

0.5

IIII!

20
0.01

:;:,

V

;::: 0.15

III
-55'C

i5!

125

25'C

10

1.0

o
25

100

&0

ill

40

TA " 25°C

~

D.S

0

15

&0

1.25

.. :!

~ ~I "3~A

IE=l~ ~

0.4
-75 -50 -25

1.5

~

I

.J

25

J.Wl

-

VCE(SAT) vs Ic
for Any Transistor
VeE = 5V

0.6

I

T. - AMBIENT TEMPERATURE rCI

VBEvsTA for
Any Transistor

0.'

..

VeE "SV

TA.illr~

BD

~

3

Ii 10"

sa

140
120

~
~

VCE

188

ffi

hFEVS Icfor
Any Transistor

~
5
. 100

il

II

~

I-

..
i

0.1
IE - EMITTER (mAl

, ...Hz

o

0.01

I-'

1kHz

0.1

Ie - COLLECTOR (mAl
TL/HI7959-2

8·132

Typical Performance Characteristics

NFvslc = RS = 10k!l

NF vs IC @ RS = 1 k!l
30 . -........,.-,..,..,..,..",--,-.,.-T'"T"rrm
As

0

1000n

ttftlt-++H11ttH

T. - 25'C
2'

30
VeE;; 5V

VeE" 5V

25

(Continued)

f--+-++++H*--f-H-++IH.H

-....
...

20

"

15

l!l0

10

~

As -10.000n

25

!!!
~

T. o 25'C I I

\! O.I.H./

o
0.01

40

~

~

t i

S::
....
.....

""

•

2D

=~

~~
:

l.l -1a
I

f-j'i

VeE'" 3V
le"1 mA

SV

~

eI
:: =
s:

11111

o
0.1

10

I)

0.1

c ..

is

LESS THAN 500 MH. \

~

-1.0

~~

II!

VeE;; SV
Ie -1 mA

.J-1.5

~ 100

~

=:
:z:
0-

.~
i.
~

BOO

I

300

10

100

f - FREQUENCY IMH.)

1'-

r- t--r-"

y

500
400

TA = 2S"C

r- ;:E= ;;z:~c
l' ~Cel

I
CEB

200

~

100

:r- t-

CeB

r-

o

~

-Z.O
1

100

'-FREQUENCY IMH.)

800

i

0

T.OZ5·IC

11

CEB. CCB. CCI vs Bias
Voltage

• ~ -O.S

I! rg

...

~

o

100

f - FREQUENCY IMH.)

m~

.;

boil

~~

100

... W!~I~T F~EJJE~Jil~.-

0.5

I

J

II

1\

Vrevsf
1.0

,,25";:

TA

VeE "IV
Ie =1 mA

1:

.- FREQUENCY IMH.)

~

Ie - COLLECTOR CURRENT ImA)

VCE

Ic ·'mA

,.

0.1

:li
...
!i!

10

0.1

Ie - COllECTOR CURRENT (mAl

TA "'2S'C

ro-

Ii

-20

z

TA ;25 C

10

~~
o-M

o

Voe vsf

I,.

3D

,,~

o

Vfe vsf
II

i

0.1

Ie - COLLECTOR CURRENT ImA)

o

N

V 'rJ!1
~ 11

~

I-

.

o

t kHI

0.1

10

:f
~

~

z

.

i

1

2 3

4

5

&

1

Ie - COLLECTOR ImA)

•

I lD

012345&1

9 10

BIAS VOLTAGE IV)
TL/H17959-3

8-133

~National

PRELIMINARY

~ semiconductor

LMC555 CMOS Timer
General Description

Features

The LMC555 is a CMOS version of the industry standard
555 series general purpose timers. It offers the same capability of generating accurate time delays and frequencies but
with much lower power dissipation and supply current
spikes. When operated as a one-shot, the time delay is precisely controlled by a single external resistor and capacitor.
In the astable mode the oscillation frequency and duty cycle
are accurately set by two external resistors and one capacitor. The use of National Semiconductor's LMCMOSTM process extends both the frequency range and low supply capability.

•
•
•
•
•
•
•
•
•

Less than 1 mW typical power dissipation at 5V supply
3 MHz astable frequency capability
1.5V supply operating voltage guaranteed
Output fully compatible with TTL and CMOS logic at 5V
supply
Tested to -10 mA, +50 mA output current levels
Reduced supply current spikes during output transitions
Extremely low reset, trigger, and threshold currents
Excellent temperature stability
Pin-for-pin compatible with 555 series of timers

Block and Connection Diagrams

GROUND

LMC555

--+--.,

8

r--------+- V+
R

=IOOkA
R

2

TRIGGER

--+---------,

7

.----+- DISCHARGE

6
~-----_+- mR~HO~

OUTPUT

Q
R

S

R
4
R~ET

TLlH/B669-1

(Pinouts for Molded and Metal Can Packages are identical)

Order Number LMC555CH, LMC555CM or LMC555CN
See NS Package Number H08C, M08A or N08E

8-134

r-

i:

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V8
Input Voltages, V2, V4, V5, V6

-0.3V to Vs + 0.3V
15V

Output Current 13, 17

-40'Cto +85'C'

Storage Temperature Range

-65'Cto + 150"C

Electrical Characteristics Test Circuit, T =

18

V5

V7

Parameter
Supply Current

Control Voltage

260"C
215'C
220"C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

100mA

Operating Temperature Range (Note 1)

Symbol

Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

15V

Output Voltages, V3, V7

(")
CI'I
CI'I
CI'I

25'C, all switches open, RESET to Vs unless otherwise noted

Conditions

Min

Vs = 1.5V
Vs = 5V
Vs = 12V
Vs = 1.5V
Vs = 5V
Vs = 12V

0.8
2.9
7.4

Typ

Max

Units
(Limits)

50
100
150

150
250
400

p.A

1.0
3.3
8.0

1.2
3.8
8.6

V

Discharge Saturation
Voltage

Vs = 1.5V, 17 = 1 mA
Vs = 5V, 17 = 10mA

75
150

300

Output Voltage
(Low)

Vs = 1.5V, 13 =1 mA
Vs = 5V, 13 = 8 mA
Vs = 12V, 13 = 50 mA

0.2
0.3
1.0

0.4
0.6
2.0

Output Voltage
(High)

Vs = 1.5V, 13 = -0.25 mA
Vs = 5V, 13 = -2 mA
Vs = 12V, 13 = -10 mA

1.0
4.4
10.5

1.25
4.7
11.3

V2

Trigger Voltage

Vs = 1.5V
Vs = 12V

0.4
3.7

0.5
4.0

12

Trigger Current

Vs = 5V

V4

Reset Voltage

Vs = 1.5V (Note 2)
Vs = 12V

0.4
0.4

0.7
0.75

14

Reset Current

Vs = 5V

10

16

Threshold Current

Vs = 5V

10

17

Discharge Leakage

Vs = 12V

1.0

100

t

Timing Accuracy

SW 2, 4 Closed
Vs = 1.5V
Vs = 5V
Vs = 12V

1.1
1.1
1.1

1.25
1.20
1.25

V3l

V3H

150

V

V
0.6
4.3

V
pA

10

0.9
1.0
1.0

mV

1.0
1.1

V
pA
pA
nA

ms

at! I::..vs

Timing Shift with Supply

Vs = 5V ±1V

at!aT

Timing Shift with
Temperature

Vs = 5V
-40"C S; T

fA

Astable Frequency

SW 1, 3 Closed
Vs = 12V

fMAX

Maximum Frequency

Max. Freq. Test
Circuit, Vs = 5V

3.0

MHz

tR, tF

Output Rise and
Fall Times

Max. Freq. Test Circuit
Vs = 5V,Cl = 10pF

15

ns

S;

+85'C

Trigger Propagation Delay

4.0

0.3

"10 IV

75

ppml'C

4.8

5.6

kHz

Vs = 5V, Measure Delay
100
ns
from Trigger to Output
• Refer to RETSC555X drawing for specifications of military lMC555H version.
Note 1: For operation at elevated temperatures, the device must be derated baaed on a 150'C maximum junction temperature and a thermal resistance of
111'CIW for the lMC555CN, 167'C/W for the lMC555CH, and 169'C/W for the LMC555CM. Maximum allowable dissipation at 25'C is 1126 mW for the
LMC555CN, 755 mW for the LMC555CH, and 740 mW for the LMC555CM.
Nota 2: If the ~ pin is to be used at temperatures of - 2O'C and below Vs is required to be 2.0V or greater.
tpD

8-135

•

II)
II)
II)

Test Circuit

(,)

Maximum Frequency Test Circuit

::Ii

.....

Vs

-=

TRIGGER

+

B

470

IOka

:slf

2

7

3

6

:t:. 0.1 ",r

-=

V
s

.1.-

OUTPUT
OUTPUT

Vs

5

4

RESET

.:r:. 200pr

LMCS55

LMC555

5

4

.I.O.O(U ",r

.I. 0.001 ",r

-

Vs

TlIH/8669-3

TlIH/8669-2

Typical Applications
Monostable (One-Shot)

Variable Duty Cycle Oacillator

Vs

B

~

Vs

B

.I. 0.1 ",r

~o.l",r

TRIGGER

~TPUT

2

7

3

6

(VS>

7

3

6

Ra

OUTPUT

-1\11RESET

2

RA

.I.e

LMCS55
4

.I.e

LMC555
I!mi'

5

4

(VS>

5
Tl/H/8889-5

TlIH/8669-4

iH = 1.1 RAe (Gives time that output is high lollowing trigger)
I'iESET overrides TImmEI'i. which can override THRESHOLD.

lose.

Therefore,

=

1.44
(RA + 2RalC

the trigger pulse must be shorter than the desired tHo

The minimum trigger pulse width Is 20 ns.
The minimum reset pulse width Is 400 ns.

Duty

CycI

8 = RA

RB

+ 2RB

(Gives fraction 01 total period
thet output Is low)

50% Duty Cycle Oscillator
B

1--.---.....- 0 Vs

2

7~------~

3

6

ALtERNATE

OUTPUT

OUTPUT

LMCS55
RESET

(VS>

4

5

.I.e

1
lose - 1.4Rc;C

TL/H/8669-8

8-136

~National

~ semiconductor

LMC567 Low Power Tone Decoder
General Description

Features

The LMC567 is a low power general purpose LMCMOSTM
tone decoder which is functionally similar to the industry
standard LM567. It consists of a twice frequency voltagecontrolled oscillator (VCO) and quadrature dividers which
establish the reference signals for phase and amplitude detectors. The phase detector and VCO form a phase-locked
loop (PLL) which locks to an input signal frequency which is
within the control range of the VCO. When the PLL is locked
and the input signal amplitude exceeds an internally pre-set
threshold, a switch to ground is activated on the output pin.
External components set up the oscillator to run at twice the
input frequency and determine the phase and amplitude filter time constants.

•
•
•
•
•
•
•
•
•
•

Block Diagram

Functionally similar to LM567
2V to 9V supply voltage range
Low supply current drain
No increase in current with output activated
Operates to 500 kHz input frequency
High oscillator stability
Ground-referenced input
HystereSiS added to amplitude comparator
Out-of-band signals and noise rejected
20 mA output current capability

(with External Components)

Vs
RL
8

OUTPUT
f1LTER

----~

Vs

OUTPUT

7

LOOP

GROUND

FILTER

....----+---f ';'2
TIMING

INPUT

,....-l~....-fEJ:AeITOR

>-__--.;3""""-+1
veo
4

Rt

TIMING
RESISTOR

LIofC567

Vs---t--+-

TLlH/8670-1

Order Number LMC567CM or LMC567CN
See NS Package Number M06A or NOSE

8-137

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
2Vp_p
Input Voltage, Pin 3
Supply Voltage, Pin 4
Output Voltage, Pin 8

13V
Vsto Gnd

Output Current, Pin 8

500mW
- 25'C to

+ 1500C
26O"C
21.5'C
2200C

See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.

30mA

Package Dissipation

- 55'C to

Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)

10V

Voltage at All Other Pins

Operating Temperature Range (TA)

Storage Temperature Range

+ 125'C

Electrical Characteristics
Test Circuit, TA = 25'C, Vs = 5V, RtCt #2, Sw. 1 Pos. 0, and no input, unless otherwise noted.
Symbol
14

V3

Parameter
Power Supply Current

Conditions
RtCt # 1, Quiescent
or Activated

Min

Typ

Max

Units

mAdc

Vs = 2V

0.3

Vs = 5V

0.5

0.8

Vs = 9V

0.8

1.3

Input D.C. Bias

0

R3

Input Resistance

40

18

Output Leakage

1

fo

Center Frequency,
Fosc + 2

RtCt # 2, Measure Oscillator
Frequency and Divide by 2

alo

Center Frequency
Shift with Supply

fol9V - fol2V X 100
7fol5V

Vin

Input Threshold

Set Input Frequency Equal to fo
Measured Above, Increase Input
Level Until Pin 8 Goes Low.

kO
100

nAdc

113

kHz

1.0

2.0

"Io/V

98

Vs = 2V
Vs= 5V

mVdc

92

103
105

Vs = 9V

Vs = 2V

11

20

27

Vs = 5V

17

30

45

mVrms

45

Vs = 9V
AVin

Input Hysteresis

Starting at Input Threshold, Decrease Input
Level Until Pin 8 goes High.

V8

Output 'Sat' Voltage

Input Level> Threshold
Choose RL for Specified 18

18=2mA

0.06

18 = 20mA

0.7

Measure Fosc with Sw. 1 in
Pos. 0.1. and 2;

Vs = 2V

7

11

15

Vs = 5V

11

14

17

"10

±1.0

"10

L.D.B.W.

Largest Detection
Bandwidth

L.D.B.W = Fosclp2 - Fosclpl X 100
FosclPO

Vs = 9V

1.5

mVrms
0.15

Vdc

15

aBW

Bandwidth Skew

Skew = (Fosclp2 + Fosclpl - 1) x 100
2 Fosclpo

f max

Highest Center Freq.

RtCt #3, Measure Oscillator Frequency and
Divideby2

700

kHz

Vin

Input Threshold
atfmax

Set Input Frequency Equal to f max measured
Above, Increase Input Level Until Pin 8 goes Low.

35

mVrms

8-138

0

Test Circuit
Vs

rl"~

_8.5k~'~

1

SW.l

Vs

:J ~

1

~

-=

O.O~tF

'-~'

D~2

-= 0.001
p.F
V3
~

O"P.F~

-

-

Ct

100k
10k
5.1k

300pF
300pF
62pF

V8

7~

Lt.lC567

:j.:~

3

14

V
S

Rt

#1
#2
#3
RL

8

-

0

RtCt

4

WITH

MEASURE Fose-.l
~10pF PROBE
TUH/B670-2

Typical Performance Characteristics
Supply Current vs.
Operating Frequency
1.2

TA=25"1:,Vs =5V

lD
DB

]:
sa

Bandwidth vs.
Input Signal Level

RI=S.1 kll

1

,..... /

!
~~

J'

0.6

RI=I00kll

Il.4

"'"

~

0.2
0

300
lIST ClRCUIT,Vs =5V,
250 RICI#2

10k

lOOk

i!i
.!!.

ISO

i5

.~

100

V-

so

1M

2

.

~

-r..:

,,

r--.

103
102

IIi
2

4

6

12
11

8 10 12 14 18 18

8 10 12 14 16 18

BANDWIDTH (lI: OF Fa!

-so

0

~o

lE

~

;!
u

ISO

lIST QRCUIT, RICI #2

2D

g

o.s

i"'- r-...

0

Vl=5~
..............

-u.s

-1.5

100

Frequency Drift
with Temperature

lD

g

so

lIMPERATURE ("1:)

3.0

-so

0

so

I\.

lD

~

lE

u

Vs=5V

-2D
-3D

100

TEMPERATURE ("1:)

"" "-

0

III
z
;! -1D

r--.

-ID
0

13

lIST CIRCUIT, RICI#1

~
,

I\.

r....

14

Frequency Drift
with Temperature

TA=25"C, Vs=5V

\

104

0

6

1.5

105

!1

4

15

BANDWIDTH (X OF Fa!

Bandwidth as
a Function of C2

c.

i

INPUT TilRE5HoU)J 0

106

...L

lIST QRCUIT,Vs =5V,RICII2

200

tlPUT FR[QUENCI' (Hz)

~

17
16

~

0

lk

Largest Detection
Bandwidth vs. Temp.

ISO

-so

0

so

.....

100

ISO

lIMPERATURE ("1:)

TUH/8670-3

8-139

~

CD
10

~

r--------------------------------------------------------------------------,
Applications Information (refer to Block Diagram)
~ENERAL

INPUT PIN

The LMC567 low power tone decoder can be operated at
supply voltages of 2V to 9V and at input frequencies ranging
from 1 Hz up to 500 kHz.

The input pin 3 is internally ground-referenced with a nominal40 kO resistor. Signals which are already centered on
OV may be directly coupled to pin 3; however, any d.c. potential must be isolated via a coupling capacitor. Inputs of
multiple LMC567 devices can be paralleled without Individual d.c. isolation.

The LMC567 can be directly substituted in most LM567 applications with the following provisions:
1. Oscillator timing capacitor Ct must be halved to double
the oscillator frequency relative to the input frequency
(See OSCILLATOR TIMING COMPONENTS).

LOOP FILTER
Pin 2 is the combined output of the phase detector and
control input of the VCO for the phase-locked loop (PLL).
Gapacitor C2 in conjunction with the nominal 80 kO pin 2
internal resistance forms the loop filter.

2. Filter capacitors C1 and C2 must be reduced by a factor
of 8 to maintain the same filter time constants.
3. The output current demanded of pin 8 must be limited to
the specified capability of the LMC567.

For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maximum hold-in range will always equal the LDBW.

OSCILLATOR TIMING COMPONENTS
The voltage-controlled oscillator (VCO) on the LMC567
must be set up to run at twice the frequency of the input
signal tone to be decoded. The center frequency of the
VCO is set by timing resistor Rt and timing capaCitor Ct
connected to pins 5 and 6 of the IC. The center frequency
as a function of Rt and Ct is given by:

OUTPUT FILTER

1
Fosc'" 1.4RtCt Hz

Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 719 Vs. When the
PLL is locked to the input, an increase in signal level causes
the detector output to move negative. When pin 1 reaches
2/3 Vs the output is activated (see OUTPUT PIN).
CapaCitor C1 in conjunction with the nominal 40 kO pin 1
internal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of C1 produce the least delay between the input and output for tone burst applications, while
larger values of C1 improve noise immunity.

Since this will cause an input tone of half Fosc to be decoded,
1
Finput "" 2.8 Rt Ct Hz
This equation is accurate at low frequencies; however,
above 50 kHz (Fosc = 100 kHz), internal delays cause the
actual frequency to be lower than predicted.
The choice of Rt and Ct will be a tradeoff between supply
current and practical capacitor values. An additional supply
current component is introduced due to Rt being switched
to Vs every half cycle to charge Ct:

Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this technique increases sensitivity to pin 1 carrier ripple and also
results in more part to part threshold variation.

Is due to Rt = Vs/(4Rt)
Thus the supply current can be minimized by keeping Rt as
large as possible (see supply current vs. operating frequency curves). However, the desired frequency will dictate an
RtCt product such that increasing Rt will require a smaller
CI. Below Ct = 100 pF, circuit board stray capacitances
begin to playa role in determining the oscillation frequency
which ultimately limits the minimum Ct.
To allow for I.C. and component value tolerances, the oscillator timing components will require a trim. This is generally
accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC567 itself is given in the
electrical specifications; the total trim range must also accommodate the tolerances of Rt and Ct.

OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 Vs.
Apart from the obvious current component due to the external pin 8 load resistor, no additional supply current is required to activate the switch. The on resistance of the
switch is inversely proportional to supply; thus the 'sat' voltage for a given output current will increase at lower supplies.

SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at
high supply voltages with high operating frequencies, requiring C4 to be placed as close as possible to pin 4.

8-140

r-------------------------------------------------------------------------, r
i:
o
~National
m
CD
~ semiconductor

LMC568 Low Power Phase-Locked Loop
General Description

Features

The LMC568 is an amplitude-linear phase-locked loop consisting of a linear VCO, fully balanced phase detectors, and
a carrier detect output. LMCMOSTM technology is employed
for high performance with low power consumption.
The VCO has a linearized control range of ±30% to allow
demodulation of FM and FSK signals. Carrier detect is indicated when the PLL is locked to an input signal greater than
26 mVrms. LMC568 applications include FM SCA and TV
second audio program decoders, FSK data demodulators,
and voice pagers.

•
•
•
•
•
•

Typical Application

Demodulates ± 15% deviation FM/FSK signals
Carrier Detect Output with hysteresis
Operation to 500 kHz input frequency
Low THD---O.5% typo for ± 10% deviation
2V to 9V supply voltage range
Low supply current drain

(100 kHz input frequency, refer to notes pg. 3)

RH

,,p------------~-----------.,,
o-F8.....'..J\o""'-tI4~Vs

:

Ct

C3

300pF

6

DE - EMPHASIS INPUT~ ....-=:.t-+-'~
0.01 p.F

IN914

LMC568

15k.D.
5

l

K']
10k.D.

Rt

SET Fose TO 2xlNPUT FREQ.---.t
MEASURE WITH ~1 0 pF PROBE
TL/H/9135-1

Order Number LMC568CM or LMC568CN
See NS Package Number M08A or N08E

•
8-141

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor' Sales
Office/Distributors for availability and specifications.
10V

Output Voltage, Pin 8

13V

Voltage at All Other Pins

VstoGnd

Output Current, Pin 8

30mA

Package Dissipation'

500mW

- 25°C to + 125°C

Storage Temperature Range

"':55°0 to + 150"C

Soldering Information
Dual-ln·Line Package
Soldering (10 seCOnds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)

2Vp_p

Input Voltage, Pin 3
Supply Voltage, Pin 4

Operating Temperature Range (TA>

26O"C
215°C
220"C

See AN-450 "Surface Mounting Methods and their Effect on
Product Reliability" for other methods of soldering surface
mount devices.

Electrical Characteristics
Test Circuit, TA = 25°C, Vs = 5V,RtCt #2, Sw. 1 Pos. 0; and no input unless otherwise noted.

Symbol
14

Parameter
Power Supply Current

Conditions
RtC! # 1, Quiescent
or Activated

Min

Typ

Max

Units

0.75

1.5

mAde

1.2

2.4

Vs'= 2V

0.35

Vs = 5V
Vs = 9V

V3

Input D.C. Bias

R3

Input Resistance

40

18

Output Leakage

1

fo

Center Frequency
Fosc +2

0

RtCt # 2, Measure Oscillator
Frequency and Divide by 2

Vs = 2V
Vs = 5V

Center Frequency
Shift with Supply

fol9V - fol2V X 100
7fol5V

Yin

Input Threshold

Set Input Frequency Equal to fo
Measured Above, Increase Input
Level until Pin 8 Goes Low.

90

nAdc

115

kHz

1.0

2.0

"IoN

103
105

Vs = 2V

8

16

25

Vs = 5V

15

26

42

AVin

Input Hysteresis

Starting at Input Threshold, Decrease Input Level
until Pin 8 Goes High.

V8

Output 'Sat' Voltage

Input Level> Threshold
Choose RL for Specified 18

18 = 2mA

0.06

18 = 20mA

0.7

Measure Fosc with Sw. 1 in
Pos. 0, 1, and 2;

Vs = 2V

Largest Detection
Bandwidth

L.D.B.W. =

Foscl~2 -I Fosclp1

Vs = 5V
x 100

osc PO

Vs = 9V

ABW

Bandwidth Skew

Skew = (Fosclp2 + Fosclpl _ 1) X 100
2 FosclPO

You!

Recovered Audio

Typical Application Circuit
Input = 100 mVrms, F = 100 kHz
Fmod = 400 Hz, ± 10kHz Dev.

Il1Vrms

45

Vs = 9V

L.D.B.W.

kG
100

98

Vs = 9V
Afo

mVdc

1.5

IJIVrms
0.15

Vdc

30
40

"10

55
60
1

Vs = 2V

170

Vs = 5V

270

Vs = 9V

400

±5

"10

mVrms

THD

Total Harmonic
Distortion

Typical Application Circuit
as Above, Measure YOU! Distortion.

0.5

"10

S+N
N

Signal to Noise Ratio

Typical Application Circuit
Remove Modulation, Measure Vn
(S + N)/N = 20 log (Vout/Vr!).

65

dB

f max

Highest Center Freq.

RtCt #3, Measure Oscillator Frequency
and Divide by 2

700

kHz

8·142

Test Circuit

:
WITH

LMC568

7h. I
_

:U·'~

RtCt

Rt

Ct

#1
#2

100k
10k
5.1k

300pF
300pF
62pF

#3

MEASURE Fose-.l
~ 10 pF PROBE
TLlH/9135-3

Notes to Typical Application
SUPPLY DECOUPLING

OUTPUT TAKEOFF

The decoupling of supply pin 4 becomes more critical at
high supply voltages with high operating frequencies, requiring C4 to be placed as close to possible to pin 4. Also, due
to pin voltages tracking supply, a large C4 is necessary for
low frequency PSRR.

The output signal is taken off the loop filter at pin 2. Pin 2 is
the combined output of the phase detector and control input
of the VCO for the phase-locked loop (PLL). The nominal
pin 2 source resistance is 80 kO, requiring the use of an
external buffer transistor to drive nominal loads.

OSCILLATOR TIMING COMPONENTS

For small value,s of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built-in VCO
frequency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will become narrower than the LOBW. However, the
maximum hold-in range will always equal the LOBW. The 2
kHz de-emphasis pole shown may be modified or omitted as
required by the application.

The voltage-controlled oscillator (VCO) on the LMC568
must be set up to run at twice the frequency of the input
signal. The components shown in the typical application are
for Fosc = 200 kHz (100 kHz input frequency). For operation at lower frequencies, increase the capacitor value; for
higher frequencies proportionally reduce the resistor values.
If low distortion is not a requirement, the series diode/resistor between pins 6 and 5 may be omitted. This will reduce
VCO supply dependence and increase Vout by approximately 2 dB with THO = 2% typical. The center frequency as a
function of Rt and Ct is given by:

CARRIER DETECT

Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 V s. The output at
pin 8 is an N-channel FET switch to ground which is activated when the PLL is locked and the input is of sufficient
amplitude to cause pin 1 to fall below 2/3 Vs. The carrier
detect threshold is internally set to 26 mVrms typical on a
5V supply.

1
Fosc ""1.4RtCt Hz
To allow for I.C. and component value tolerences, the oscillator timing components will require a trim. This is generally
accomplished by using a variable resistor as part of Rt, although Ct could also be padded. The amount of initial frequency variation due to the LMC568 itself is given in the
electrical specifications; the total trim range must also accommodate the tolerances of Rt and Ct.

Capacitor C1 in conjunction with the nominal 40 kO pin 1
internal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Optional resistor RH increases the hysteresis in
the pin 8 output for applications such as audio mute control.
The minimum allowable value for RH is 330 kO.

INPUT PIN
The input pin 3 is internally ground-referenced with a nominal 40 kO resistor. Signals that are centered on OV may be
directly coupled to pin 3; however, any d.c. potential must
be isolated via C3.

8-143

LMC568 Typical Performance Characteristics
Frequency Drift
with Temperature
3

,

Peak Deviation vs
Input Signal Level

t40

APPUCAnoN CIRCUIT. Vs = 5V

TEST QRClJlT Vs =5V./ftCI2

1

I

:f
~

~

~

"-

i!i
~

~

-2
-3
-so

:f

t30

~

z:

so

100

TEMPERATURE (OC)

ISO

Pull-In Range as
a Function of C2
t40

I

t20
tl0

I

o

~

I

~

III

~

*20

\

a;

I

~ tl0

~PUCATIONS

\

,

'-

0
so

100

ISO

200

250

INPUT VOLTAGE(mVrm.)

300

C1RCU1T,_=-

Vs=5V. vlN = l00mVrms

I,

~

I[

o

~, _
t30

1

10

102

103

104

105

FoxC2 PRODUCT(Hz-pFJ
TL/H/8135-2

8-144

,-------------------------------------------------------------------------,

~National

~ Semiconductor

~

i

LP395 Ultra Reliable Power Transistor
General Description
The LP395 is a fast monolithic transistor with complete
overload protection. This very high gain transistor has included on the chip, current limiting, power limiting, and thermal overload protection, making it difficult to destroy from
almost any type of overload. Available in an epoxy TO-92
transistor package this device is guaranteed to deliver 100

mAo
Thermal limiting at the chip level, a feature not available in
discrete designs, provides comprehensive protection
against overload. Excessive power dissipation or inadequate heat sinking causes the thermal limiting circuitry to
turn off the device preventing excessive die temperature.
The LP395 offers a significant increase in reliability while
Simplifying protection circuitry. It is especially attractive as a
small incandescent lamp or solenoid driver because of its
low drive requirements and blowout-proof design.
The LP395 is easy to use and only a few precautions need
be Observed. Excessive collector to emitter voltage can destroy the LP395 as with any transistor. When the device is
used as an emitter follower with a low source impedance, it
is necessary to insert a 4.7 kG resistor in series with the
base lead to prevent possible emitter follower oscillations.
Also since it has good high frequency response, supply bypassing is recommended.

Connection Diagram

Areas where the LP395 differs from a standard NPN transistor are in saturation voltage, leakage (quiescent) current
and in base current. Since the internal protection circuitry
requires voltage and current to function, the minimum voltage across the device in the on condition (saturated) is typically 1.6 Volts, while in the off condition the quiescent (leakage) current is typically 200 ",A. Base current in this device
flows out of the base lead, rather than into the base as is
the case with conventional NPN transistors. Also the base
can be driven positive up to 36 Volts without damage, but
will draw current if driven negative more than 0.6 Volts. Additionally, if the base lead is left open, the LP395 will turn on.
The LP395 is a low-power version of the 1-Amp
LM195/LM295/LM395 Ultra Reliable Power Transistor.
The LP395 is rated for operation over a - 40"C to + 125"C
range.

Features
•
•
•
•
•
•
•

Internal thermal limiting
Internal current and power limiting
Guaranteed 100 mA output current
0.5 ",A typical base current
Directly interfaces with TTL or CMOS
+36 Volts on base causes no damage
2 p.s switching time

Typical Applications
Fully Protected Lamp Driver
V+

BOTTOM VIEW
TL/H/6525-1

Order Number LP395Z
See NS Package Z03A

TUH/5525-3

•
8-145
---------------

~~~-

Absolute Maximum Ratings
Collector to Emitter Voltage
Collector to Base Voltage
Base to Emitter Voltage (Forward)
Base to Emitter Voltage (Reverse)
Base to Emitter Current (Reverse)

36V
36V
36V
10V
20mA

Collector Current Limit
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)

Internally Limited
Internally Limited
-40"Cto + 125·C
-65·C to + 150·C
260"C

Electrical Characteristics
Symbol

Parameter

Conditions

Typical

Tested
Limit
(Note 2)

Design
Umit
(Note 3)

36

36
(Note 1)

V(Max)
mA(Min)
mA(Min)
mA(Min)

Units
(Limit)

VCE

Collector to Emitter
Operating Voltage

0.5 mA ,,; Ic ,,; 100 mA

ICL

Collector Current Limit
(Note 4)

VSE = 2V, VCE = 36V
VSE = 2V, VCE = 15V
VSE = 2V,2V ,,; VCE ,,; 6V

45
90
130

25
60
100

20
50
100

Is

Base Current

0,,; Ic"; 100 mA

-0.3

-2.0

-2.5

/IoA(Max)

10

Quiescent Current

VSE = OV,O ,,; VCE ,,; 36V

0.24

0.50

0.60

mA(Max)

VCE(SAT)

Saturation Voltage

2.00

2.10

V(Max)

Base to Emitter Breakdown Voltage (Note 4)

VSE = 2V,Ic = 100 mA
o ,,; VCE ,,; 36V, Is = 2/1oA

1.82

BVSE

36

36

V(Min)

VSE

Base to Emitter Voltage
(Note 5)

Ic = 5mA
Ic - 100 mA (Note 4)

0.69
1.02

0.79

0.90
1.40

V(Max)
V (Max)

ts

Switching Time

VCE = 20V, RL = 200.11
VSE = OV, + 2V, OV

8JA

Thermal Resistance
Junction to Ambient

0.4" leads soldered to
printed circuit board

2
150

/los
180

·C/W
(Max)

·C/W
0.125" leads soldered to
130
160
printed circuit board
(Max)
Note 1: Parameters identified with boldface type apply at temp. extremes. All other numbers, unless noted apply at + 25"'C.
Note 2: Guaranteed and 100% production tested.
Note 3: Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges. These limits ars not used to calculate outgoing
quality levels.
Note 4: These numbers apply for pulse testing with a low duty cycle.
Note 5: Base positive with respect to emitter.

Simplified Circuit

r-------------,

I

I

=:
...

I
I
I
I
I
I
I
I
I
L
I

Applications Information
One failure mode incandescent lamps may experience is
one in which the filament resistance drops to a very low
value before it actually blows out. This is especially rough
on most solid-state lamp drivers and in most cases a lamp
failure of this type will also cause the lamp driver to fail.
Because of its high gain and blowout-proof deSign, the
LP395 is an ideal candidate for reliably driving small incandescent lamps. Additionally, the current limiting characteristics of the LP395 are advantageous as it serves to limit the
cold filament inrush current, thus increasing lamp life.

CD~R

"LJ

8J
"lit-<
1

II1II

.....
.....

~

lIDO

CIRCUITRY

0.5

______________

-

~R

TL.lH/5525-5

8-146

Typical Performance Characteristics
5 Volt Transfer Function
(VCE= VI

~

~A=~5·.! ....

Iii

40
20

o

I

60

o

0.20.4 0.6 0.81.0 1.2 1.41.61.8
BASE.£MITTER VOLTAGE (VI

Available Collector Current

,..

160
_ 140

.100

8 BO

I:
20

o

~

~

n ..

I';;;: ~

o

125· GUARANTEm

-

I-

1'\

~
I-

L-

""

25;CO:~~

_

0.8
0.7

1

06

1
.,
!
i

GUARANTEED

'"

I 1:

1.DV

j

~11.

o

0.20.4 0.6 0.81.0 1.2 1.4 1.61.8
BASE-EMITTER VOLTAGE (VI

O.~

o

-

,

0.2
0.1

Ir
o IJ
o

Saturation Voltage

~

a

1.8
1.6

§! 1.4

:l~

I I

--

'"

TA= -25·C ~ .,."..

,,""'"

",'" .,.".

",

1.2

K

","

'"

~ ·.... T4=25·C
..... t =125·C

~ 1.0
0.8
0.6

5 10 15 20 25 30 35 40
COLLECTOR.£MITTER VOIJAGE (VI

"' .
r--:

.DV-0.6V

5 10 15 20 25 30 35 40
COLLECTOR-EMITTER VOIJAGE (VI

2.0

0.3

'"

O.BV

2.2
(VaE=OI
I I I I I GUARANTEED II III

~

O.~

20

0:5
0.4

5 10 15 20 25 30 35 40
COLLECTOR.£MmER VOIJAGE (VI

,.~!.
1.1V

_ 140

1 120

I:

II

o

Collector Characteristics
160

Quiescent Collector Current

(VaE=2VI

,

1120

TAt~·C

TA=-25·C

10

1.'1
o

TO

I:

TA=-25·C ....

60

'-tJ5.~T I I

(Vct; .. 36VI

I:

TA=15·

100

8 BO

~
8

1

,..~

1 120
a:

36 Volt Transfer Function
80

160
_140

o

20 40 60 BO 100 120 140
COLLECTOR CURRENT (mAl
TUH/5525-4

Collector Current Threshold
2.0
1.8
C 1.6
!.
1.4
1.2
a:
=>
Co> 1.0
a: 0.8
~ 0.6
~
co 0.4
0.2

Ye= +5V
125·C

I

~

..,

o

TYPICALS-J..-40·C

2J·C - ' -

I
~

.. .,... -

+3a

U

~

-3a

-

o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
BASE.£MITTEH VOLTAGE (VI
TL/H/5525-9

Typical Applications (Continued)
Lamp Flasher
(Short Circuit Proof)

Optically Isolated
Switch
~------~-----V+

V+:.l2V

OUTPUT

33k
L-______......____ VTLlH/5525-7

TLlH/5525-6

8-147

•

Typical Applications (Continued)
Two Terminal
Current Umlter

Composite PNP

.
4.711

+

~
-

BASE

,

.

2N2907

~~

J

EMITTER

~

LP395

1011

-~

1

COLLECTOR
TLlH/5525-2

TLlH/5525-8

8-148

Section 9
Surface Mount

Section 9 Contents
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-2

9-3

~National

Semiconductor

Surface Mount
DIPs) have a 100 mil lead center spacing. Surface mount
packages currently in production (e.g., SOT, SOIC, PCC,
LCC, LDCC) have a 50 mil lead center spacing. Surface
mount packages in production release (e.g., POFP) have a
25 mil lead center spacing. Surface mount packages in development (e.g., TAPEPAKIII» will have a lead center spacing of only 12-20 mils.

SURFACE MOUNT PACKAGING AT NATIONAL

To meet the growing demand for smaller packaging, National has developed a line of surface mount packages. Ranging in lead counts from 3 to 360, the package offerings are
summarized in Table I.
Lead center spacing keeps shrinking with each new generation of surface mount package. Traditional packages (e.g.,

TABLE I. Surface Mount Packages from National

Package
Type

Package
Material

Small Outline
Transistor
(SOT)

Small Outline
IC(SOIC)

,{]:: I~

Plastic Chip
Carrier (PCC)

~

~

Plastic Ouad
Flat Pack
(POFP)

V

TAPEPAKIII>
(TP)

Leadless Chip Leaded Chip
Carrier (LCC) Carrier
(LOCC)

(gJ 0
, 111111111111111111111

liHHHHHHHi I

[5'WAWffkd

I

I

Plastic

Plastic

Plastic

Plastic

Plastic

Ceramic

Ceramic

Gull Wing

Gull Wing

J-Bend

Gull Wing

Gull Wing

-

Gull Wing

Lead Center
Spacing

50 Mils

50 Mils

50 Mils

25 Mils

20,15,12 Mils

50 Mils

50 Mils

Tape & Reel
Option

Yes

Yes

Yes

tbd

tbd

No

No

Lead Bend

Lead Counts SOT-23
High Profile
SOT-23
Low Profile

SO-8(')
SO-14(0)

PCC-20(*)
PCC-28(0)

SO-14 Wide(')
SO-16(*)
SO-16 Wide(')
SO-20(*)
SO-24(0)
SO-28(*)

PCC-44(')
PCC-68
PCC-84
PCC-124

POFp·84
POFP-100
POFP-132
POFP-196(O)
POFP-244

'In production (or planned) for linear products.

9-3

TP-40 (0)
TP-68
TP-84
TP-132
TP-172
TP-220
TP-284
TP-360

LCC-18
LCC-20(*)

LDCC-44

LCC-28

LOCC-68

LCC-32
LCC-44 (*)

LOCC·84

LCC-48
LCC-52
LCC-68
LCC-84
LCC-124

LDCC-124

.1:
::s
o
:::Ill

~

::s

tn

r------------------------------------------------------------------------------------------,
LINEAR PRODUCTS IN SURFACE MOUNT
Linear functions available in surface mount include:

TABLE II: Surface Mount Package
Thermal Resistance Range"

• Op amps
• Comparators
• Regulators
• References
• Data conversion
• Industrial
• Consumer
• Automotive
A representative list of linear part numbers in surface mount
is presented in Table III. Refer to the datasheet in the appropriate chapter of this databook for a complete description of the device. In addition, National has other products
and is continually expanding the list of devices offered in
surface mount. If the functions you need do not appear in
Table III, contact the sales office or distributor branch nearest you for additional information.
Automated manufacturers can improve their cost savings by
using Tape-and-Reel for surface mount devices. Simplified
handling results because hundreds-to-thousands of semiconductors are carried on a single Tape-and-Reel pack (see
ordering and shipping information-printed later in this section-for a comparison of devices/reel vs. devices/rail for
those surface mount package types being used for linear
products). With this higher device count per reel (when compared with less than a 100 devices per rail), pick-and-place
machines have to be re-Ioaded less frequently and lower
labor costs result.

Package

Thermal Resistance'·
(61A' ·C/W)

SO-8
50-14
SO-14 Wide
50-16
50-16 Wide
50-20
50-24
50-28

120-175
100-140
70-110
90-130
70-100
60-90
55-85
TBD

PCC-20
PCC-28

70-100
60-90
40-60

PCC-44

• Actual thermal resistance for a partiCIJlar device depends on die size.
Refer to the datesheat for the actual 9jA value.
"Test conditions: PCB mount (FR4 material). still air (room temperature).
copper traces (150 x 20 x 10 mils).

Given a max junction temperature of 150·C and a maximum
allowed ambient temperature, the surface mount device will
be able to dissipate less power than the DIP device. This
factor must be taken into account for new designs.
For board conversion, the DIP and surface mount devices
would have to dissipate the same power. This means the
surface mount circuit would have a lower maximum allowable ambient temperature than the DIP circuit. For DIP circuits where the maximum ambient temperature required is
substantially lower than the maximum ambient temperature
allowed, there may be enough margin for safe operation of
the surface mount circuit with its lower maximum allowable
ambient temperature. But where the maximum ambient temperature required of the 01 P current is close to the maximum allowable ambient temperature, the lower maximum
ambient temperature allowed for the surface mount circuit
may fall below the maximum ambient temperature required.
The circuit designer must be aware of this potential pitfall so
that an appropriate work-around can be found to keep the
surface mount package from being thermally overstressed
in the application.

With Tape-and-Reel, manufacturers save twice--once from
using surface mount technology for automated PC board
assembly and again from less device handling during shipment and machine set-up.
BOARD CONVERSION
Besides new deSigns, many manufacturers are converting
existing printed circuit board designs to surface mount. The
resulting PCB will be smaller, lighter and less expensive to
manufacture; but there is one caveat-be careful about the
thermal dissipation capability of the surface mount package.
Because the surface mount package is smaller than the traditional dual-in-line package, the surface mount package is
not capable of conducting as much heat away as the DIP
(i.e., the surface mount package has a higher thermal resistance-see Table II).
The silicon for most National devices can operate up to a
150·C junction temperature (check the datasheet for the
rare exception). Like the DIP, the surface mount package
can actually withstand an ambient temperature of up to
125·C (although a commercial temperature range device
will only be specified for a max ambient temperature of 70"C
and an industrial temperature range device will only be
specified for a max ambient temperature of 85·C). See
AN-336, "Understanding Integrated Circuit Package Power
Capabilities", (reprinted in the appendix of each linear databook volume) for more information.

SURFACE MOUNT LITERATURE
National has published extensive literature on the subject of
surface mount packaging. Engineers from packaging, quality, reliability, and surface mount applications have pooled
their experience to provide you with practical hands-on
knowledge about the construction and use of surface mount
packages.
The applications note AN-450 "Surface Mounting Methods
and their Effect on Product Reliability" is referenced on
each 5MD datasheet. In addition, "Wave Soldering of 5urface Mount Components" is reprinted in this section for your
information.

9-4

~

TABLE III. Linear Surface Mount Selected Device Listing

Amplifiers and Comparators

Data Acquisition Products

Part Number

Part Number

Part Number

LF451CM
LF453CM
LM10CWM
LM10CLWM
LM318M
LM3080M
LM4250M
LM611CM
LM6121M
LM613CWM
LM614CWM
LM6151WM
LM61811M
LM6218WM
LM6321M
LM6361M
LM6362M
LM6364M
LM6365M
LMC660CM
LMC662CM

LMC60221M
LMC60241M
LMC60321M
LMC60341M
LMC60411M
LMC6042IM
LMC60441M
LMC60841M
LMC6064IM
LMC60611M
LMC60811M
LMC60621M
LMC60821M
LMC64841M
LMC6482IM
LPC660IM
LPC6611M
LPC662IM

ADC08061 /2/4/8
ADC08161/4/8
ADC08031/2/4/8
ADC08131/4/8
ADC08231/4/8
ADC0851/58
ADC10061/2/4
ADC10154/8
ADC1034/8
ADC10461/2/4
ADC1061
ADC10662/4
ADC12030/2/4/8

Part Number

DS2001CM
DS2001TM
DS2002CM
DS2002TM
DS2003CM
DS2003TM
DS2004CM

DS2004TM
DS3680M
DS75451M
DS75452M
DS75453M
DS75454M

Part Number
LM317LM
LM337LM
LM431ACM
LM723CM
LM2574M-3.3
LM2574M-5.0
LM2574M-12
LM2574M-15
LM2574M-ADJ
LM2574HVM--3.3
LM2574HVM-5.0
LM2574HVM-12
LM2574HVM-15
LM2574HVM-ADJ
LM2575M-5.0
LM2575M-12
LM2575M-15
LM2575M-ADJ
LM2575HVM-5.0
LM2575HVM-12
LM2575HVM-15
LM2575HVM-ADJ

LM2577M-12
LM2577M-15
LM2577M-ADJ
LM2578AM
LM2931AM-5.0
LM2931M-5.0
LM2931CM
LM2936M-5.0
LM3524DM
LM3578AM
LM78L05ACM
LM78L12ACM
LM78L15ACM
LM79L05ACM
LM79L12ACM
LM79L15ACM
LP2951ACM
LP2951CM
LP2952AIM
LP29521M
LP2953AIM
LP29531M

o

C
::J

Part Number

Part Number

AH5012CM
LF13331M
LF13509M
LF13333M
LM555CM
LM556CM
LM567CM
LM1496M
LM2917M
LM3046M
LM3086M
LM3146M

LM13600M
LM13700M
LMC555CM
LM567CM
MF4CWM-50
MF4CWM-100
MF6CWM-50
MF10CCWM
MF6CWM-100
MF5CWM
LMC568CM
LMC567CM

Commercial and Automotive

Regulators and References
Part Number

DAC0854
LM12454/8
LM34
LM35
LM4040
LM4041
LM4431
LMF100
LMF380
LMF40
LMF60
LMF90

CD

Ii:

Industrial Functions

Peripheral Drivers
Part Number

Part Number

in

Part Number

Part Number

LM386M-1
LM831M
LM832M
LM833M
LM837M
LMC835V
LM1201M
LM1204V

LM1851M
LM1865M
LM1877M
LM1894M
LM1882CM
LM1964V
LMC1982CIV
LMC1983CIV
LM3361AM
LM1881M
LM3914V

•
9-5

.. ,------------------------------------------------------------------------------------------,
c

S

:&

~

i

A FINAL WORD

National is a world leader in the design and manufacture of
surface mount components.
Because of design innovations such as perforated copper
leadframes, ,our small outline package is as reliable as our
DIP-the laws of physics would have meant that a straight
"junior copy" of the DIP would have resulted in an "S.O."
package of lower reliability. You benefit from this equivalence of reliability. In addition, our ongoing vigilance at each
step of the production process assures that the reliability we
designed in stays in so that only devices of the highest quality and reliability are shipped to your factory.
Our surface mount applications lab at our headquarters site
In Santa Clara, California continues to research (and publish) methods to make it even easier for you to use surface
mount technology. Your problems are our problems.
When you think "Surface Mount"-think "National"l

Package

Package
Designator

Max/Rail

Per Reel'

SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24
SO-28

M
M
WM
M
WM
M
M
M

100
50
50
50
50
40
30
26

2500
2500
1000
2500
1000
1000
1000
1000

V
V
V

50
40
25

1000
1000
500

PQFP-196

VF

TBD

-

TP-40

TP

100

TBD

E
E

50
25

PCL-20
PCL-28
PCL-44

LCC-20
LCC-44

Ordering and Shipping Information

-

-

*Incremental ordering quantities. (National Semiconductor reserves the right

When you order a surface mount semiconductor, it will be in
one of the several available surface mount package types.
Specifying the Tape-and-Reel method of shipment means
that you will receive your devices in the following quantities
per Tape-and-Reel pack: SMD devices can also be supplied
in conventional conductive rails.
When ordering bulk S.O.-specify "M".

to provide a smaller quantity of devices per Tape-and-Reel pack to preserve
lot or date code integrity. See example below.)

Example: You order 5,000 LM324MXICs shipped in Tapeand-Reel.
• Case 1: All 5,000 devices have the same date code
• You receive 2 SO-14 (Narrow) Tape-and-Reel
packs, each having 2500 LM324M ICs

When ordering S.O. Tape & Reel-specify "MX".

• Case 2: 3,000 devices have date code A and 2,000 devices have date code B
• You receive 3 SO-14 (Narrow) Tape-and-Reel
packs as follows:
Pack # 1 has 2,500 LM324MXICs with date code A
Pack #2 has 500 LM324MXICs with date code A
Pack #3 has 2,000 LM324MXICs with date code B

Short-Form Procurement Specification
TAPE FORMAT

Trailer (Hub End)'
Empty Cavities,
min (Unsealed
Cover Tape)

Carrier'

Leader (Start End)'

Empty Cavities,
min (Sealed
Cover Tape)

Filled Cavities
(Sealed
Cover Tape)

Empty Cavities,
min (Sealed
Cover Tape)

Empty Cavities,
min (Unsealed
Cover Tape)

Small Outline IC
SO-8 (Narrow)

2

2

2500

5

5

SO-14 (Narrow)

2

2

2500

5

5

SO-14 (Wide)

2

2

1000

5

5

SO-16 (Narrow)

2

2

2500

5

5

SO-16 (Wide)

2

2

1000

5

5

SO-20 (Wide)

2

2

1000

5

5

SO-24 (Wide)

2

2

1000

5

5

SO-28 (Wide)

0

25

1000

42

0

PCC-20

2

2

1000

5

5

PCC-28

2

2

750

5

5

PCC-44

2

2

500

5

5

Plastic Chip Carrier IC

'The following diagram Identlfle. the. . . .ctlon. of the tape and Pin # 1 device orientation.

9-6

.--------------------------------------------------------------------------,0
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Short-Form Procurement Specification

ia:

(Continued)

DEVICE ORIENTATION
DIRECTION
OF FEED

~
TRAILER
-- SECTION
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OO~OOOOOOOOOOOOOOOO4

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HUB
END

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• EMPTY
CAVITIES
• UNSEALED
CDVER TAPE

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--~~~~~;,
• EMPTY
CAVITIES
• SEALED

• EMPTY
CAVITIES
• SEALED
CDVERTAPE

•

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II
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ORIENTATIDN

[_0

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SO-IC
DEVICES

0

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• EMPTY

CAVITIES
• UNSEALED
CDVERTAPE

I
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~

PCC-IC
DEVICES
TUXX/0026-8

• Reel:

MATERIALS
• Cavity Tape: Conductive PVC (less than 105 Ohms/Sq)
• Cover Tape: Polyester

(1) Solid 80 pt fibreboard (standard)
(2) Conductive fibreboard available
(3) Conductive plastic (PVC) available

(1) Conductive cover available

TAPE DIMENSIONS (24 Millimeter Tape or Less)
PO 10 PITCH CUMULATIVE
TAPE TOLERANCE :to.2mm

DEVICE ORIENTATION

r
PIN
1

SO-II:

pcc-Ie
TUXX/0028-9

9-7

oc

~

Short-Form Procurement Specification (Continued)

I

w

I

P

I

F

I

E

I

P2

I

I

Po

I

D

T

I

AO

I

BO

I

Ko

I

D1

IR

Small Outline IC
80-8
12±.30 8.0±.10
(Narrow)

5.5±.05 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.4±.10

5.2±.10

2.1 ±.10 1.55±.05 30

80-14
16±.30 8.0±.10
(Narrow)

7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10

9.0±.10

2.1 ±.10 1.55±.05 40

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10

9.5±.10

3.0±.10 1.55±.05 40

80-14
(Wide)

80-16
16±.30 8.0±.10
(Narrow)

10.3±.10 2.1 ±.10 1.55±.05 40

7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10

80-16
(Wide)

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 10.76±.10 3.0±.10 1.55±.05 40

80-20
(Wide)

24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 13.3±.10 3.0±.10 2.05±.05 50

80-24
(Wide)

24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 15.85±.10 3.0±.10 2.05±.05 50

Plastic Chip Carrier IC
PCC·20

16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 9.3±.10

PCC-28

24±.30 16.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 13.0± .10 13.0±.10 4.9±.10 2.05±.05 50

Note 1: Ao. Bo and

9.3±.10

4.9±.10 1.55±.05 40

Ko dimensions are measured 0.3 mm above the inside wall of the cavity bottom.

Note 2: Tape with components shall pass around a mandril radius R without damage.
Note 3: Cavity tape material shall be PVC oonductive (less than 1()5 Ohms/Sq).
Note 4: Cover tape materiel shall be polyester (30-65 grams peal-back force).
Note 5: 01 Dimension Is cemered within cavity.
Note 6: All dimensions are in millimeters.

REEL DIMENSIONS

-

TMAX

H

1--8
lABEL

~~

-I
LIQUID

REFLOW SOLDERING
There are various methods for reflowing the solder paste,
namely:
•
•
•
•

_~L
1--

_

• Solder globules will begin to oxidize and cause solderability problems.

IMMERSION HEATER

TLlXX/0026-22

The question of thermal shock is asked frequently because
of the relatively sharp increase in component temperature
from room temperature to 215·C. SO packages mounted on
representative boards have been tested and have shown
little effect on the integrity of the packages. Various packages, such as cerdips, metal cans and TO-5 cans with glass
seals, have also been tested.

Hot air reflow
Infrared heating (furnaces)
Convectional oven heating
Vapor-phase reflow soldering

• laser soldering
For SO applications, hot air reflow/infrared furnace may be
used for low-volume production or prototype work, but vapor-phase solqering reflow is more efficient for consistency
and speed. Oven heating is not recommended because of
"hot spots", in the oven and uneven melting may result. laser soldering is more for specialized applications and requires a great amount of investment.

Vapor-Phase Furnace

HOT GAS REFLOWIINFRARED ",EATING
A hand-held or table-mount air blower (with appropriate orifice mask) can be used.
The boards.are preheated to about 1OO"C and then subjected to an air jet at about 260"C. This is a slow process and
results may be inconsistent due to various heat-sink properties of passive components.
Use of an infrared furnace is the next step to automating the
concept, except that the heating is promoted by use of IR
lamps or panels. The main objection to this method is that
certain materials may heat up at different rates under IR
radiation and may result in damage to these components
(usually sockets and connectors). This could be minimized
by using far-infrared (non-focused) system.
TL/XX/0026-23

VAPOR-PHASE REFLOW SOLDERING
Currently the most popular and consistent method, vaporphase soldering utilizes a fluoroinert fluid with excellent
heat-transfer properties to heat up components until the solder paste reflows. The maximum temperature is limited by
the vapor temperature of the fluid.

Batch-Fed Production Vapor-Phase Soldering Unit

The commonly used fluids (supplied by 3M Corp) are:
• FC-70, 215·C vapor (most applications) or FX-38
• FC-71 , 253·C vapor (low-lead or tin-plate)
HTC, Concord, CA, manufactures equipment that utilizes
this technique, with two options:
• Batch systems, where boards are lowered in a basket and
subjected to the vapor from a tank of boiling fluid.
• In-line conveyorized systems, where boards are placed
onto a continuous belt which transports them into a concealed tank where they are subjected to an environment
of hot vapor.
Dwell time in the vapor is generally on the order of 15-30
seconds (depending on the mass of the boards and the
loading density of boards on the belt).
9-16

.--------------------------------------------------------------------------.0
c
Solder JOints on a SO-14 Package on PCB

Solder Joints on a SO-14 Package on PCB

ia::
oc

a

TL/XX/OO26-25

TL/XX/OO26-26

PRINTED CIRCUIT BOARD
The SO package is molded out of clean, thermoset plastic
compound and has no particular compatibility problems with
most printed circuit board substrates,

The typical lithographic "footprints" for SO packages are
illustrated below. Note that the 0.050" lead center-center
spacing is not easily managed by commercially-available air
pressure, hand-held dispensers.

The package can be reliably mounted onto substrates such
as:

Using a stainless-steel, wire-mesh screen stencilled with an
emulsion image of the substrate pads is by far the most
common and well-tried method. The paste is forced through
the screen by a V-shaped plastic squeegee in a sweeping
manner onto the board placed beneath the screen.

• G10 or FR4 glass/resin
• FR5 glass/resin systems for high-temperature
applications

The setup for SO packages has no special requirement
from that required by other surface-mounted, passive components. Recommended working specifications are:

• Polymide boards, also high-temperature
applications
• Ceramic substrates
General requirements for printed circuit boards are:

• Use stainless-steel, wire-mesh screens, #SO or #120,
wire diameter 2.6 mils. Rule of thumb: mesh opening
should be approximately 2.5-5 times larger than the average particle size of paste material.

• Mounting pads should be solder-plated whenever
applicable.

• Use squeegee of Durometer 70.

• Solder masks are commonly used to prevent solder bridging of fine lines during soldering.

• Experimentation with squeegee travel speed is recommended, if available on machine used.

The mask also protects circuits from processing chemical
contamination and corrosion.

• Use solder paste of mesh 200-325.
• Emulsion thickness of 0.005" usually used to achieve a
solder paste thickness (wet) of about O.OOS" typical.

If coated over pre-tinned traces, residues may accumulate
at the mask/trace interface during subsequent reflow,
leading to possible reliability failures.

• Mesh pattern should be 90 degrees, square grid.

Recommended application of solder resist on bare, clean
traces prior to coating exposed areas with solder.

• Snap-off height of screen should not exceed
damage to screens and minimize distortion.

General requirements for solder mask:
-

Good pattern resolution.

-

Complete coverage of circuit lines and resistance to
flaking during soldering.

-

Adhesion should be excellent on substrate material to
keep off moisture and chemicals.

-

Compatible with soldering and cleaning requirements.

'Is" , to avoid

SOLDER PASTE
Selection of solder paste tends to be confusing, due to numerous formulations available from various manufacturers.
In general, the following guidelines are sufficient to qualify a
particular paste for production:
• Particle sizes (see photographs below). Mesh 325 (approximately 45 microns) should be used for general purposes, while larger (solder globules) particles are preferred for leadless components (LCC). The larger particles
can easily be used for SO packages.

SOLDER PASTE SCREEN PRINTING
With the initial choice of printed circuit lithographic design
and substrate material, the first step in surface mounting is
the application of solder paste.

9-17

• Composition, generally 60/40 or 63/37 Sn/Pb. Use 62/36
Sn/Pb with 2°,b Ag in the presence of Au on the soldering
area. This formulation reduces problems of metal leaching
from soldering pads.

• Uniform particle distribution. Solder globules should be
spherical in shape with uniform diameters and minimum
amount of elongation (visual under 100/200 x magnification). Uneven distribution causes uneven melting and subsequent expulsion of smaller' Solder balls away from their
proper sites.

• RMA flux system usually used.
• Use paste with aproximately 88-90% solids.

RECOMMENDED. SOLDER PADS FOR so PACKAGES

.50-8,50-14, SO-16

SO-16L, SO-20
0.045"

····1']l ••••
:;~
1-

±0.005"

r····~

L-.I••••
~.
I- -I

0.245"

0.160"

0.030" :1:0.005"

1-0.050"

.~".

TYP

TL/XX/0026-27

-I

0.030" :1:0.005"--1

1_::r.TYP

TUXX/OO26-26

TL/XX/OO26-29

Comparison of Particle SizelShape of Various Solder Pastes
200

x Alpha (62/36/2)

200

TUXX/OO26-30

x Kester (63137)

TL/XX/0026-31

9-18

Comparison of Particle Size/Shape of Various Solder Pastes (Continued)
Solder Paste Screen on Pads

200

x Fry Metal (63/37)

TLlXX/0026-33

TUXX/0026-32

200 ESL (63/37)

TLlXX/OO26-34

9-19

--

-----~--~~~~~----~--~~--

CLEANING

Hot-Air ReWOrk Machine

The most critical process in surface mounting SO packages
is in the cleaning cycle. The package is mounted very close
to the surface of ttiesubstrate and has a tendency to collect
residue left behind after reflow soldering.
Important considerations in cleaning are:
• Time between soldering and cleaning to be as short as
possible. Residue should not be allowed to solidify on the
substrate for long periods of time, making it difficult to
dislodge.
• A low surface tension solvent (high penetration) should be
employed. Solvents commercially available are:
Freon TMS (general purpose)
Freon TE35ITP35 (cold-dip cleaning)
Freon TES (general purpose)

TL/XX/OO26-S6

lead tips or, If necessary, solder paste can be dispensed
onto the pads using a varimeter. After being placed into
poSition, the solder is reflowed by a hot-air jet or even a
standard soldering iron.

It should also be noted that these solvents generally will
leave the substrate surface hydrophobic (moisture repellent), which is desirable.
Prelete or 1,1,1-Trichloroethane
Kester'5120/5121

WAVE SOLDERING
In a case where lead insertions are made on the same
board as surface-mounted components, there is a need to
include a wave-soldering operation in the process flow.
Two options are used:

• A defluxer system which allows the workpiece to be subjected to a solvent vapor, followed by a rinse in pure solvent and a high-pressure spray lance are the basic requirments for low-volume production.

• Surface mounted components are placed and vapor
phase reflowed before auto-insertion of remaining components. The board is carried over a standard wave-solder
system and the underside of the board (only lead-inserted
leads) soldered.

• For volume production, a conveyorized, multiple hot solvent spray/jet system is recommended.
• Rosin, being a natural occurring material, is not readily
soluble in solvents, and has long been a stumbling block
to the cleaning process. In recent developments, synthetic flux (SA flux), which is readily soluble in Freon TMS
solvent, has been developed. This should be explored
where permissible.
The dangers of an inadequate cleaning cycle are:

• Surface-mounted components are placed in pOSition, but
no solder paste is used. Instead, a drop of adhesive about
5 mils maximum in height with diameter not exceeding
25% width of the package is used to hold down the package. The adhesive is cured and then proceeded to autoinsertion on the reverse side of the board (surface-mounted side facing down). The assembly is then passed over a
"dual wave" soldering system. Note that the surfacemounted components are immersed into the molten solder.
Lead trimming will pose a problem after soldering in the
latter case, unless the leads of the insertion components
are pre-trimmed or the board specially designed to localize
certain areas for easy access to the trim blade.
The controls required for wave soldering are:

• Ion contamination, where ionic residue left on boards
would cause corrosion to metallic components, affecting
the performance of the board.
• Electro-migration, where ionic residue and moisture present on electrically-biased boards would cause dentritic
growth between close spacing traces on the subStrate,
resulting in failures (shorts).

REWORK
Should there be a need to replace a component or re-align
a previously disturbed component, a hot air system with appropriate orifice masking to protect surrounding components may be used.
When rework is necessary in the field, specially-designed
tweezers that thermally heat the component may be used to
remove it from its site. The replacement can be fluxed at the

• Solder temperature to be 240-260"C. The dwell time of
components under molten solder to be short (preferably
kept under 2 seconds), to prevent damage to most components and semiconductor devices.
• RMA (Rosin Mildly Activated) flux or more aggressive OA
(Organic Acid) flux are applied by either dipping or foam
fluxing on boards prior to preheat and soldering. Cleaning
procedures are also more difficult (aqueous, when OA flux
is used), as the entire board has been treated by flux (unlike solder paste, which is more or less localized). Nonhalide OA fluxes are highly recommended.

Hot-Air Solder Rework Station
MAS@K
RETRACT POSITION

- - --c------_.
-L __ _' HEAT SHIELD

//0
./

• Preheating of boards is essential to reduce thermal shock
on components. Board should reach a temperature of
about 100"C just before entering the solder wave.

./

---- ----

~~;~t~~~BO:AR:D:ON

• Due to the closer lead spacings (0.050' vs 0.100' for
dual-in-line packages), bridging of traces by solder could
occur. The reduced clearance between packages also
causes "shadowing" of some areas, resulting in poor solder coverage. This is minimized by dual-wave solder systems.

X-Y TABLE

HOT AIRTLlXX/OO26-35

9-20

en

c

Mixed Surface Mount and Lead Insertion

i

ADHESIVE

Rxil

a

(b) Opposite Sides

(a) Same Side

-

iii:

oc

tttt
PREHEAT

SOLDER FLOW
TL/XX/OO26-37

A typical dual-wave system is illustrated below, showing the
various stages employed. The first wave typically is in turbulence and given a transverse motion (across the motion of
the board). This covers areas where "shadowing" occurs. A
second wave (usually a broad wave) then proceeds to perform the standard soldering. The departing edge from the
solder is such to reduce "icicles," and is still further reduced
by an air knife placed close to the final soldering step. This
air knife will blow off excess solder (still in the fluid stage)
which would otherwise cause shorts (bridging) and solder
bumps.

Dual Wave

AQUEOUS CLEANING
• For volume production, a conveyorized system is often
used with a heated recirculating spray wash (water temperature 130°C), a final spray rinse (water temperature
45-55°C), and a hot (120°C) air/air-knife drying section.
• For low-volume production, the above cleaning can be
done manually, using several water rinses/tanks. Fastdrying solvents, like alcohols that are miscible with water,
are sometimes used to help the drying process.

TL/XX/0026-36

CONFORMAL COATING

• Neutralizing agents which will react with the corrosive materials in the flux and produce material readily soluble in
water may be used; the choice depends on the type of flux
used.

Conformal coating is recommended for high-reliability PCBs
to provide insulation resistance, as well as protection
against contamination and degradation by moisture.

• Final rinse water should be free from chemicals which are
introduced to maintain the biological purity of the water.
These materials, mostly chlorides, are detrimental to the
assemblies cleaned because they introduce a fresh
amount of ionizable material.

• Complete coating over components and solder jOints.

Requirements:
• Thixotropic material which will not flow under the packages or fill voids, otherwise will introduce stress on solder
joints on expansion.
• Compatibility and possess excellent adhesion with PCB
material/components.
• Silicones are recommended where permissible in
application.
9-21

cr--------------------------------------------------------------------,
:::s
o

SMD Lab Support

~

FUNCTIONS
Demonstration-Introduce first-time users to surfacemounting processes.
Servlc&-Investigate problems experienced by users on
surface mounting. .

:E

~

Technique&-Develop techniques for handling different
materials and processes in surface mounting.
Equipment-In conjunction with equipment manufacturers,
develop customized equipments to handle high density,
new technology packages developed by National.
In-House ExpertlS&-Avaiiability of in-house expertise on
semiconductor research/development to assist users on
packaging queries.

Reliability Bulld&-Assemble surface-mounted units for reliability data acquisition.

9-22

Section 10
Appendicesl
Physical Dimensions

Section 10 Contents
Appendix A General Product Marking and Code Explanation .............................
Appendix B Devicel Application Literature Cross-Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C Summary of Commercial Reliability Programs ...............................
Appendix D Military Aerospace Programs from National Semiconductor ...................
Appendix E Understanding Integrated Circuit Package Power Capabilities. . . . . . . . . . . . . . . . . .
Appendix F How to Get the Right Information from a Datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix G Obsolete Product Replacement Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

10-2

10-3
10-4
10-11
10-13
10-22
10-27
10-31
10-33

~National

~ Semiconductor

LF

11
356

N

Appendix A
General Product Marking & Code Explanation
Package Type

IA+

R_",_,O,.,.."

I

0

GlasslMetal DIP
Ceramic Leadless Chip Carrier (LCC)
GlasslMetal Flat Pak (%" x %")
12 Lead TO-8 Metal Can (M/C)
Multi-Lead Metal Can (MIG)
4 Lead MIC (TO-S) } Shipped with
4 Lead MIC (TO-46)
Thermal Shield
Lo-Temp Ceramic DIP
8 Lead Ceramic DIP ("MiniDIP")
14 Lead Ceramic DIP (-14 used only when
product is also available in -8 pkg).
TO-3 MIC in Steel, except LM309K
K
which is shipped in Aluminum
KC
TO-3 MIC (Aluminum)
KSteel TO-3 MIC (Steel)
Small Outline Package
M
3-Lead Small Outline Package
M3
N
Molded DIP (EPOXY B)
Molded DIP (Epoxy B) with Staggered Leads
N-Ol
N-8
8 Lead Molded DIP (Epoxy B) ("Mini-DIP")
14 Lead Molded DIP (Epoxy B)
N-14
(-14 used only when product is also
available in -8 pkg).
3 Lead TO-202 Power Pkg
P
Q
Cerdip with UV Window
3,5,11,15 & 23 Lead TO-220 PWR Pkg (Epoxy B)
T
Multi-lead Plastic Chip carrier (PCG)
V
W
Lo-Temp Ceramic Flat Pak
Wide Body Small Outline Package
WM

(Refer to Appendix G)

E
F
G
H
H-OS
H-46
J
J-8
J-14

Package Type (See Right)
Device Number (Generic Type)
and Suffix Letter (Optional)
A or B: Improved
Electrical
Specification
C, I, E or M: Temperature
Range
Device Family (See Below)

Device Family
ADC
AF
AH
DAC
OM
HS
LF
LH
LM
LMC
LMD
LP
LPC
MF
LMF

Data Conversion
Active Filter
Analog Switch (Hybrid)
Data Conversion
Digital (Monolithic)
Hybrid
Linear (Bifet)
Linear (Hybrid)
Linear (Monolithic)
Linear CMOS
LinearDMOS
Linear (Low Power)
Linear CMOS (Low Power)
Linear (Monolithic Filter)
Linear Monolithic Filter

DATE CODE
1ST DIGIT - CALENDAR YEAR
2ND DIGIT - 6-WEEK PERIOD
IN CALENDAR YEAR
3RD &: 4TH DIGITS - WAFER LOT CODE

DATE CODE
NON-~ILlTARY

2ND DIGIT - CALENDAR YEAR
3RD UTH DIGITS - CALENDAR WORK WEEK
~ILlTARY

- aaH ~3a510
1sa 2ND DIGITS - CALENDAR YEAR
3RD & 4TH DIGITS - CALENDAR WORK WEEK
(EXA~PLE' 9201 = 1ST WEEK OF 1992)
~ILITARY

ONLY
ESD
(ELECTROSTATIC DISCHARGE)
SENSITIVITY INDICATOR

INDICATES PLANT
OF ~ANUFACTURE

INDICATES PLANT
OF MANUFACTURE

LOGO
PART NUMBER
PIN 1 ORIENTATION

WAFER LOT
CODE
PART

NU~BER

TLlXX/0027 -3
TLlXX/OO27 -2

10-3

~National

~ Semiconductor

Appendix B
Devicel Application Literature Cross-Reference
Device Number

Application Literature

ADCXXXX .................................................................................................AN-156
ADC80 ..........•.•...................................................... '................•.......•....... AN-360
ADC0801 .................................................... AN-233, AN-271, AN-274, AN-280, AN-281, AN-294, LB-53
ADC0802 ......................... ; ......................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0803 ................................................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC08031 ...............................................................•................................AN-460
ADC0804 ............................................ AN-233, AN-274, AN-276, AN-280, AN-281, AN-301, AN-460, LB-53
ADC0805 ................................................................... AN-233, AN-274, AN-280, AN-281, LB-53
ADC0808 ..................................................................................AN-247, AN-280, AN-281
ADC0809 .........................................................................................AN-247, AN-280
ADC0816 ..........................................................................AN-193, AN-247, AN-258, AN-280
ADC0817 ............................................ i

.....................................

AN-247, AN-258, AN-280

ADC0820 .............................................................................................•...AN-237
ADC0831 .......................................................•.................................AN-280,AN-281
ADC0832 .........................................................................................AN-280,AN-281
ADC0833 .........................................................................................AN-280, AN-281
ADC0834 .........................................................................................AN-280, AN-281
ADC0838 .................................................. i

••••••••••••••••••••••••••••••••••••• •

AN-280, AN-281

ADC100l ..................................................................................AN-276,AN-280,AN-281
ADC1005 .................................................................................................AN-280
ADC10461 ....................................................................•...........................AN-769
ADC10462 ........................•........................................................•..............AN-769
ADC10464 ................................................................................................AN-769
ADC10662 ............................•.........................................................•.........AN-769
ADC10664 .......................................................................•........................AN-769
ADC1210 .................................................................................................AN-245
ADC12441 ................................................................................................AN-769
ADC12451 ................................................................................................AN-769
ADC3501 .........................................................................................AN-200, AN-202
ADC3511 ................................................................................................•AN-200
ADC3701 .................................................................................................AN-200
ADC3711 .................................................................................................AN-200
AH0014 ....................................................................................................AN-38
AH0019 ....•.............................................................................................•.A~-38
CD4016 ......................................................•.................•................•......•...AB-l0
DACXXlQ<' ................................................................................................AN-156
DAC0800 .................................................................................................AN-693
DAC0830 ... : .............................................................................................AN-284
DAC0831 .........................................................................................AN-271,AN-284
DAC0832 ...................................................................................••....AN-271, AN-~84
DAC1000 ..........................................................................AN-2il, AN-275, AN-277, AN-284
DAC100l ..........................................................................AN-271, AN-275, AN-277, AN-264
DAC1002 .........................................................................•AN-271, AN-275, AN-277, AN-284
10-4

DevicelApplication Literature Cross-Reference (Continued)
Device Number

Application Uterature

DAC1006 .....................................................................•....AN-271, AN-275, AN-277, AN-284
DAC1007 ........................•.....•...................•...•...•.•.....•....... AN-271, AN-275, AN-277, AN-284
DAC1008 .........................•.............•.......•..........................AN-271, AN-275, AN-277, AN-284
DAC1020 ...........................................•..................... AN-263, AN-269, AN-2293, AN-294, AN-299
DAC1021 ...................................................•.......................•.....................AN-269
DAC1022 .................................................................................................AN-269
DAC1208 ...........................................•.......•.....•...............................AN-271 , AN-284
DAC1209 .........................................•..........•..•••...............................AN-271 , AN-284
DAC1210 ................................................•............•..•..•.........•...........AN-271, AN-284
DAC1218 ......................•...........................•.............•.................•..............AN-293
DAC1219 ........................................•..............•........•.......•.............•..........AN-693
DAC1220 ...............•.•...•............................•......•...............................AN-253, AN-269
DAC1221 ...............................................•••....••.........•....•..•..•....................AN-269
DAC1222 .................................•.......................................•.....•....•..•.•.......AN-269
DAC1230 ..............................................................•..........•.......................AN-284
DAC1231 ................................•.......••...............•............•................•.AN-271, AN-284
DAC1232 ...................•.....................................................................AN-271, AN-284
DAC1280 .........•..........................•......•..•.....•....•.••.......•....................AN-261, AN-263
DH0034 .........................................•...............••.......•......••........................AN-253
DH0035 ................••...•.•.....•........................•.............................................AN-49
Digitalker .................•..........•...•......•...••••.•....•.....•.•.....•..........•.....•••....AN-252, LB-54
DM8890 ....••...............•....................................•....................................Appendix B
D58606 ..........................•...••.....•........••••.....••..•.•......•........•........•....AN-381 , AN-382
D58608 ...................................................................•...............................AN-382
DT1058 .............................•...........................................•.........................AN-287
DT1060 ...•.•.•.... , ....• " ...•••.....•..•. , ........••.•....•....•.•..••...•..•...•...••.. , ..•............ AN-287
DT5W250E2 .............................•........................•......................•................AN-287
DT5W250GI .....•.....•.•.. , ...•.....••••....••.....••..•..•.•.••.. , •••.... , .••••.. , ...•...... " .. , .•..... AN-287
IN58070 ................•.........•......•.....................••.•.....................•...............•.AN-260
LF111 ......................................................................................................LB-39
LF155 .....•.......•.•......•••.....•.........•............•.......••.•.......•....•.•....•.•.....AN-263,AN-447
LF198 ...•.......••......•.......•......•........•.......••.....•••......•....•..................•AN-245,AN-294
LF311 .............................•.........•.....•.......................................•......•.......AN-301
LF347 ..•..•.....•......•.............•...... AN-256, AN-262, AN-263, AN-265, AN-266, AN-301, AN-344, AN-447, LB-44
LF351 .......................................... AN-242, AN-263, AN-266, AN-271, AN-275, AN-293, AN-447, Appendix C
LF351A .....................•................•...............•.......•................•....•..............AN-240
LF351B ........•.......•.••....•..••..•••.....•.....•..••.•...••••...•.•....•...•.......••............ AppendixD
LF353 ............ AN-256, AN-256, AN-262, AN-263, AN-264, AN-266, AN-271, AN-285, AN-293, AN-447, LB-44, Appendix D
LF356 ......•.......•.......•..............••.•......••.•.. AN-253, AN-258, AN-260, AN-263, AN-266, AN-271, AN-272,
AN-275, AN-293, AN-294, AN-295, AN-301, AN-447, AN-693
LF357 ..........•..........•.......................•..............•......•..................AN-263,AN-447, LB-42
LF398 ....•.•........•.•.....••.....•••.•...••••....•••....•••••..... AN-247, AN-258, AN-266, AN-294, AN-298, LB-45
LF400 ........•........•••.....•.••....•••......•••......••....••••...•..•.......•.....••........• AN-428,AN-447
LF411 .....•.......................•..........................................•....AN-294, AN-301, AN-344, AN-447
LF412 .....................•.......•.......•.......•.......•.........•.....AN-272, AN-299, AN-301, AN-344, AN-447
LF441 ............................................................................................AN-301, AN-447
LF13006 .........•....••.•.....••....•.•.......••.....••••••...••••.•.•.•.•.•...•••.....••..............•.AN-344
LF13007 .........•.......................•.................•.................................•............AN-344
LF13331 .........................•.................•.••.•..•.•.....•......••.•.....••.•.......•...AN-294,AN-447
LF13508 ....................••........•.•..••......••••.•.•.••••...••••..•...••........•.. AN-289, AN-360, AN-447
LF13509 ........•••.......•.......•..........•...........•................................AN-289, AN-295, AN-447
10-5

DevicelApplication Literature Cross-Reference (Continued)
Application Literature

Device Number.

LH0002 .............................. " ...........•.......... AN-13. AN-63. AN-227. AN-244. AN-263. AN-272. AN-301
LH0005 ................ '....................................................................................AN-13
LH0022 ............ , .................................................•..............................AN-63. AN-75
LH0023 .....................................•.....................................................AN-245. AN-360
LH0024 ............•...........................................•............•............................AN-253
LH0032 ........................................................•..........................AN-242. AN-244. AN-253
LH0033 .•..........................................................................AN-48. AN-115. AN-227. AN-253
LH0042 .•.............•................................................ , ................................... AN-63
LH0043 ...................................................................................................AN-245
LH0052 ..............•.............................•........•....•.........................................AN-63
LH0053 ...................................................................................................AN-245
LH0062 ........................ , .................................................. " ...............•....... AN-75
LH0063 ..................................................................................•................AN-227
LH0070 ...................................................................................................AN-301
LH0071 ...................................................................................................AN-245
LH0082 .....................................•.....................................................AN-244. AN-266
LH0086 ...........................................................................................AN-245.AN-360
LH0091 ................................•......................•.........•.................................AN-180
LH0094 ...................................................................................................AN-301
LH0101 ...................................................................................................AN-261
LH1605 ....•................................•.....................................................•.......AN-343
LM10 ...................................... AN-211. AN-247. AN-258. AN-271. AN-288. AN-299. AN-300. AN-460. AN-693
LM11 •..................................................................... AN-241. AN-242. AN-260. AN-266. AN-271
LM12 .........•......•................................•...................................AN-446.AN-693. AN-706
LM101 ........................................................•. AN-4. AN-13. AN-20. AN~24. AN-75. LB-42. Appendix A
LM101A ...•.............. AN-29. AN-30. AN-31. AN-79. AN-241 AN-711. LB-1. LB-2. LB-4. LB-8. LB-14. LB-16. LB-19. LB-28
LM102 .................................................................. AN-4. AN-13. AN-30. LB-1. LB-5. LB-6. LB-11
LM103 .............................................................................................AN-110. LB-41
LM104 .......................•......................•...............................AN-21. LB-3. LB-7. LB-10. LB-40
LM105 .....................................................................AN-21.AN-23. AN-110, LB-3. LB-7. LB-10
LM106 .........................................................................................AN-41. LB-6. LB-12
LM107 ..............•....•............................................. AN-20.AN-31. LB-1. LB-12. LB-19. Appendix A
LM108 ...................•................... AN-29. AN-30. AN-31. AN-63. AN-79. AN-211. AN-241. LB-14. LB-15. LB-21
LM108A ......................................................................................AN-260. LB-15. LB-19
LM109 .•.......................•...................•................................................AN-42. LB-15
LM109A ....................................................................................................LB-15
LM110 .........................................................•........... , ....•....•............... LB-11. LB-42
LM111 ..•... " .....•..•......•.............. " •...........•............... AN-41. AN-103. LB-12. LB-16. LB-32. LB-39
LM112 ..........................•....................................................................AN-63.LB-19
LM113 ...........................................•.....•.................. AN-56.AN-110. LB-21. LB-24. LB-28. LB-37
LM117 ..................•........................................•......•.... AN-178.AN-181. AN-182. LB-46. LB-47
LM117HV ...........•....•............••..................................•.......................... LB-46, LB-47
LM118 ....................................................................... LB-17. LB-19. LB-21. LB-23. Appendix A
LM119 ..................•...................................•.....•...•...........•................AN-115.LB-23
LM120 ....................................................................................................AN-182
LM121 ...........................•.•.•.............................•......... AN-79. AN-104. AN-184. AN-260. LB-22
LM121A .......................................................................•...............•..........•. LB-32
LM122 ............................................•.....•.......................•..........•.........AN-97. LB-38
LM125 •........•.....•...•.......•....•....................................................................AN-82
LM126 .•....................................................................................................AN-82

10-6

DevicelApplication Literature Cross-Reference (Continued)
Device Number

Application Uterature

LM129 ............................................................................AN-173, AN-178, AN-262, AN-266
LM131 .................................................................................AN-210, AN-460, Appendix 0
LM131A ..................................................................................................AN-210
LM134 ............................................................................................. LB-41, AN-460
LM135 ....................................................................AN-225, AN-262, AN-292, AN-298, AN-460
LM137 .................................................................................................•...LB-46
LM137HV ...............................................•......•...................•...•...........••...... LB-46
LM138 .....................................................................................................LB-46
LM139 .....................................................................................................AN-74
LM143 ...........................................................••...........•............•....•.AN-127, AN-271
LM148 ....................................................................................................AN-260
LM150 .....................................................•..................•..••..............•..••.•••.LB-46
LM158 .............................................................•........•.............................AN-116
LM160 ........................................................•............................................AN-87
LM161 ...............................................................•...............•.............AN-87,AN-266
LM163 ...............................................................................................•...•AN-295
LM194 .............................................................................................AN-222, LB-21
LM195 ..................................•......•.......•....•...................................•.•.•••.•.AN·110
LM199 ....................................................................................AN-161,AN-260,AN-360
LM199A .....•.........................................•.•...........................................•...•AN-161
LM211 .....................•...............•..•..........••....•......................•..........•..••..••• LB-39
LM216A ...............................................................•..................................•. LB-37
LM231 .•.........................................................••..................................•....AN-210
LM231A ...........•......................................................................................AN-210
LM235 ....................................................................................................AN-225
LM239 .................•....................•...•.................•.........••..•...........•.•.....••••.••AN-74
LM258 .............•...............•.............•....................................•.........•......•..AN-116
LM260 ........•.....................................................•....•....•............•.......••.••.•.AN-87
LM261 ....•..•...........•..•.....•.....•.............••.....•...........................•.................AN-87
LM34 .....................................................................................................AN-460
LM35 .............................................................•...........•...........................AN-460
LM301A ............................•..........•.............•.•...........................AN-178, AN-181, AN-222
LM304 .....................................................................................................LB-40
LM308 ............................................................. AN-88, AN-184, AN-272, LB-22, LB-28, Appendix 0
LM308A ............................................................................................AN-225, LB-24
LM309 ....................................................................................•.......AN-178, AN-182
LM311 ..................... AN-41 , AN-1 03, AN-260, AN-263, AN-288, AN-294, AN-295, AN-307, LB-12, LB-16, LB-18, LB-39
LM313 ..•...................•...................................................•......•..........•.....•.AN-263
LM316 ...............................................................................................•...•AN-258
LM317 ........................•...•..........•........•...•........•..•......................AN-178, LB-35, LB-46
LM317H .........•.........•..........................................•.....................................LB-47
LM318 ...................................................•......•......................•.••.AN-115, AN-299, LB-21
LM319 ...................................................•.......•....•........•..........AN-115, AN-271, AN-293
LM320 .................•.............••.•....................•............................................AN-288
LM321 ..................•.........•............................................................•......•...•LB-24
LM324 ............................................. AN-88, AN-258, AN-274, AN-284, AN-301, LB-44, AB-25, Appendix C
LM329 .............................................•......•...........•..• AN-256, AN-263, AN-284, AN-295, AN-301
LM329B ...................................•...........................................•..................AN-225
LM330 .......................................................•.........................•.•...............•AN-301
LM331 ................................ AN-21 0, AN-240, AN-265, AN-278, AN-285, AN-311 , LB-45, Appendix C, Appendix 0
LM331A ................•.......•.•.................•••..•••.....•........•....................AN-21 0, Appendix C
10-7

Device!Application Literature Cross-Reference (Continued)
Application Literature

Device Number

LM334 ....................................................................................AN-242, AN-256, AN-284
LM335 .•......•............................................................•..............AN-225, AN-263, AN-295
LM336 ...•.................•..............................................................AN-202, AN-247, AN-258
LM337 .....................................................................................................LB-46
LM338 .....•......................................................................................... LB-49, LB-51
LM339 .....................................................................................AN-74, AN-245, AN-274
LM340 ............................................................................................AN-1 03, AN-182
LM340L. ..................................................................................................AN-256
LM342 ....................................................................................................AN-288
LM346 .........................•...................................................................AN-202, LB-54
LM348 .............................................................................................AN-202, LB-42
LM349 .....................................................................................................LB-42
LM358 .......•.................•....................... AN-116, AN-247, AN-271 , AN-274, AN-284, AN-298, Appendix C
LM358A ...............................................................................................Appendix D
LM359 .............................................................................................AN-278, AB-24
LM360 .....................................................................................................AN-87
LM361 .............................................................................................AN-87, AN-294
LM363 ..••................................................................................................AN-271
LM380 .............................................................................................AN-69, AN-146
LM381 ..........................................................................................••.AN-64,AN-104
LM382 ............................•.......................................................................AN-147
LM385 .....................................................AN-242, AN-256, AN-301, AN-344, AN-460, AN-693, AN-777
LM386 ..•.................................................................................................. LB-54
LM389 ............................................................................AN-256, AN-263, AN-264, AN-274
LM391 ...................................................................................•................AN-272
LM392 ..........................•••.•........•.........•.......•..................................AN-274, AN-286
LM393 ............................................................................AN-271 , AN-274, AN-293, AN-694
LM394 .............................................. AN-262, AN-263, AN-264, AN-271, AN-293, AN-299, AN-311, LB-52
LM395 .............................................. AN-178, AN-181, AN-262, AN-263, AN-266, AN-301, AN-460, LB-28
LM399 ....•.........•.....................................................................................AN-184
LM555 .....................................................................•..•.............•.......AN-694, AB: 7
LM556 .................•..•.................................................................................AB-7
LM565 .............................................................................................AN-46, AN-146
LM566 .........................................................•..........................................AN-146
LM604<.••..•....•.........................................................................................AN-460
LM628 •.....•..•..................................................................................AN-693, AN-706
LM629 ....................................................................................AN-693, AN-694, AN-706
LM709 ................•.............................................................................AN-24,AN-30
LM710 ...•..........................................................................................AN-41, LB-12
LM725 .....................................................................................................LB-22
LM741 .................................................................................AN-75, AN-79, LB-19, LB-22
LM832 .....................•......................................................................AN-386, AN-390
LM833 ........•......................................................•...............•.................•..AN-346
LM1 036 ...............................................•....•..............................................AN-390
LM1310 ....................................................................................................AN-81
LM1458 ...................................................................................................AN-116
LM1524 ......••.•.•....•.....................................•.................... AN-272, AN-288, AN-292, AN-293
LM1558 ...................................................................................................AN-116
LM1578A ..................................................................................................AB-30
LM1807 ............•.•....•.......................................•...................................AppendixB

10-8

./

DevicelApplication Literature Cross-Reference (Continued)
Device Number

Application Literature

LM1808 ...............................................................................................AppendixB
LM1820 ....................................................................................................LB-29
LM1828 ...............................................................................................AppendixB
LM1830 ....................................................................................................AB-10
LM1845 ...............................................................................................AppendixB
LM1865 ...........................................................................................AN-382, AN-390
LM1894 ...................................................................................AN-384, AN-386, AN-390
LM2577 ...........................................................................................AN-776,AN-777
LM2878 ...................................................................................................AN-147
LM2907 ...................................................................................................AN-162
LM2917 ...................................................................................................AN-162
LM2931 ....................................................................................................AB-12
LM2931CT .................................................................................................AB-11
LM3045 ...................................................................................................AN-286
LM3046 ...........................................................................................AN-146, AN-299
LM3064 ...............................................................................................Appendix B
LM3065 ...............................................................................................Appendix B
LM3070 ...............................................................................................Appendix B
LM3071 ...............................................................................................AppendixB
LM3089 ..............................................................................................•....AN-147
LM3524 ...........................................................................AN-272, AN-288, AN-292, AN-293
LM3525A .................................................................................................AN-694
LM3578A ..................................................................................................AB-30
LM3900 ............................................................... AN-72, AN-263, AN-274, AN-278, LB-20, AB-24
LM3909 ...................................................................................................AN-154
LM3911 ................................................................................•........... LB-27, AN-460
LM3914 ......................................................................................AN-460, LB-48, AB-25
LM3915 ..............•...................•...........................................................•....AN-386
LM3999 ...................................................................................................AN-161
LM4250 .............................................................................................AN-88, LB-34
LM7800 ...................................................................................................AN-178
LM78L12 .................................................................................................AN-146
LM78S40 .................................................................................................AN-711
LMC555 ..................................................................................................AN-460
LMC835 ..................................................................................................AN-435
LMD18200 ................................................................................................AN-694
LM18293 ............................................................................................•....AN-706
LP324 ....................................................................................................AN-284
LP395 ....................................................................................................AN-460

10-9

DevicelApplication Literature Cross-Reference
Device Number

(Continued)

Application Literature

MF10 .....................................................................................................AN-307
MM2716 ................................................................................................... LB-54
MM54104 ...................................................................................AN-252, AN-287, LB-54
MM57110 .................................................................................................AN-382
MM74COO ..................................................................................................AN-88
MM74C02 ..................................................................................................AN-88
MM74C04 ..................................................................................................AN-88
MM74C948 .....................................................................................•..........AN-193
MM74LS138 ................................................................................................ LB-54
MM53200 .................................................................................................AN-290
2N4339 ....................................................................................................AN-32

10-10

~National

~ Semiconductor

Appendix C
Summary of Commercial Reliability Programs
General

Typical A+ Flow is:

National Semiconductor Commercial Reliability Programs
provide a broad range of off-the-shelf enhanced semiconductor products that supply an extra measure of quality and
reliability needed in high-stress or difficult to service applications.
National's A + and B + programs allow each individual customer to:

•
•
•
•

SEM
Assembly and Seal
Four Hour 150'C Bake
Five Temperature Cycles (O'C to +100'C)

• High Temperature Electrical Test
• Electrical Test
• Burn-In (160 hours at a minimum junction temperature of
125'C)

• Minimize the need for incoming electrical inspection
• Eliminate the need and associated costs of using independent testing laboratories

• DC Parametric and Function Tests
• Tightened Quality Control Inspection Plans

• Reduction in infant mortality rate
• Reduction in reworked board costs
• Reduction in warranty and service costs

Note: Certain products may follow slightly different process flows diclated
by specific capabilities and device characteristics. consult NSC.

P + Product Enhancement

A + Product Enhancement

The P + product enhancement program applies to power
devices and offers an added advantage. P+ involves dynamic tests that screen out assembly related and silicon
defects that can lead to infant mortality and/or reduce the
survivability of the device under high stress conditions. This
includes but is not limited to the following devices:

The A + Product Enhancement incorporates the benefits of
the Multiple-Pass and Elevated Temperature along with
"BURN-IN."
The A + Program provides:
• 100% Temperature Cycling
• 100% Electrical Testing at Room and High Temperature
• 100% Burn-In Testing Combining Increased Temperature with Applied Voltage
• Acceptable Quality Levels Greater than Industry Norm

10-11

~

E

,-----------------------------------------------------------------------------,

e

e

Package Types
Device

Go

~

:is

.!!

LM12
LM109/309

&!

LM117/317

fu

LM120(320

'ii

E
E

8

LM117HVl317HV
LM123/323
LM133/333
LM137/337

r

LM137HVl337HV

E

LM145/345

I

LM195/395

'0

i

LM138/338
LM140/340
LM150/350

(.)

.!S

"i

:

LM196/396

T0-3
KSTEEL

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

TO-39
(H)

X
X
X
X

X
X

TO-220
(T)

TD-202
(P)

X

X

X

X

X
X

X

DIP
(N)

SO

X

X

X

X

(M)

X

X

X

X
X
X
X
X
X
X
X
X
X
X

LM2930i2935/2984
LM2937
LM2940/2941
LM2990/2991
LM2575/2575HV
LM2576
LM2577
LMD18200/18201
LM18298

10-12

X

.--------------------------------------------------------------------,~

"C
"C

~National

CD
::I

~ Semiconductor

a.
;C.

~

Appendix D
Military Aerospace Programs
from National Semiconductor
This appendix is intended to provide a brief overview of
military products available from National Semiconductor. For further information, refer to our 1987 Reliability
Handbook.

Process Flows
(Integrated Circuital

JANS

National Semiconductor's Military/Aerospace Program is
founded on dedication to excellence. National offers com·
plete support across the broadest range of products with
the widest selection of qualification levels and screening
flows. These flows include:

JANB

10-13

it

~

~

2

1
Description

QPL products processed to
MIL·M·38510 Level S for space
level applications.
QPL products processed to
MIL·M·38510 Level B for military
applications.

SMD

Standard Military Drawing products
processed to Level B with Table I
Electricals controlled by DESC.
(Formally called DESC Drawing.)

883

Products processed to
MIL·STD-883 Level B for military
applications.

MLP

Products processed on the
Monitored Line (Program)
developed by the Air Force for
space level applications.

MILS

Non-JAN products processed to
Level S to negotiated electrical
specifications for space level
applications.

-MIL

Similar to MIL-STD-883 with
exceptions noted on Certificate of
Conformance.

MSP

Military Screening Program for
initial release of advanced
products.

"U

c8
Dl
3

-

(II

a3
z

a
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i.
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3

s·

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~~------------------------------------~

~

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!o

CD

(f)

:;
z

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,g
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CD

National offers both 883 Class Band 883 Class S product. The screening requirements for both classes of prod.
uct are outlined in Table III.
As with SMDs a manufacturer is allowed to use his standard electrical tests provided that all critical parameters
are tested. Also, the electrical test parameters, test conditions, test limits and test temperatures must be clearly
documented. At National Semiconductor, this information
is available via our Table I (formerly RETS, Reliability
Electrical Test Specification Program). The Table I document is a complete description of the electrical tests performed and is controlled by our QA department. Individual
copies are available upon request.
Some of National's products are produced on a flow similar to MIL-STD-883. These devices are screened to the
same stringent requirements as 883 product, but are
marked as -MIL; specific reasons for prevention of compliancy are clearly defined in the Certificate of Conformance (C of C) shipped with the product.
• Monitored Line Program (MLP): is a non JAN Level S
program developed by the Air Force. Monitored Line
product usually provides the shortest cycle time, and is
acceptable for application in several space level programs. Lockheed Missiles and Space Company in Sunnyvale, California, under an Air Force contract, provides
"on-site" monitoring of product processing, and as appropriate, program management. Monitored Line orders
generally do not allow "customizing", and most flows
do not include quality conformance inspection. Drawing
control is maintained by the Lockheed Company.
• Military Screening Program (MSP): National's Military
Screening Program was developed to make screened
versions of advanced products such as gate arrays and
microprocessors available more quickly than is possible
for JAN and 883 devices. Through this program,
screened product is made available for prototypes and
breadboards prior to or during the JAN or 883 qualification activities. MSP products receive the 100% screening of Table III, but are not subjected to Group C and D
quality conformance testing. Other criteria such as electrical testing and temperature range will vary depending
upon individual device status and capability.

• MIL-M-38510: The MIL-M-38510 Program, which is
sometimes called the JAN IC Program, is administered
by the Defense Electronics Supply Center (DESC). The
purpose of this program is to provide the military community with standardized products that have been manufactured and screened to government-controlled speCifications in government certified facilities. All 38510
manufacturers must be formally qualified and their products listed on DESC's Qualified Products List (QPL) before devices can be marked and shipped as JAN product.
There are two processing levels speCified within MIL-M38510: Class Sand B. Class S is typically specified for
space flight applications, while Class B is used for aircraft, naval and ground systems. National is a major
supplier of both classes of devices. Screening requirements are outlined in Table III.
Tables I and II explain the JAN device marking system.
Copies of MIL-M-38510, the QPL and other related
documents may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179
• Standard Military Drawings (SMD): SMD's are issued
to provide standardized versions of devices which are
not available as JAN product. MIL-STD-883 Class B
screening is coupled with tightly controlled electrical
specifications which have been wrillen to allow a manufacturer to use his standard electrical tests. A current
listing of National's SMD offerings can be obtained
frorn· our authorized distributors, sales offices or DESC,
DESC is located in Dayton, Ohio.
• MIL-STD-883: Although. originally intended to establish
uniform test methods and procedures, MIL-STD-883
has also become the general specification for non-JAN
military product. Revision D of this document defines
the minimum requirements for a device to be marked
snd advertised as 883-compliant. Included are design
and construction criteria, documentation controls, electrical and mechanical screening requirements, and quality control procedures.· Details can. be found in paragraph 1.2.1 of MIL-STD-883.

10-14

TABLE I. The MIL-M-38510 Part Marking

TABLE II. JAN Package Codes

J~8~/X~~XYYY

38510
Package
Designation

[~-

A= Solder Dipped
B=TIn Plate
C=GoId Plate
X= Any lead finish above
Is acceptable
Device Package
(_Table I!)
L...- Screening Level
S,B,orC
Device Number on
Slaeh Sheet
' - - - Slaeh Sheet Number
For radiation hard devices
this slash Is replaced by the
Radiation Hardness Assurance
Designator (M, D, R, or H per
paragraph 3.4.1.3 of MIL-lol38510)
MIL-M-38510
JAN Prefix
(which may be applied only to
a fully conformant device per
paragra:eshS 3.6.2.1 and 3.6.7 of
MIL-M- 510)

A
B
C
D
E
F
G
H
I

J
K
L
M
N
P
Q

R
S
T
U
V
W

TL/XX/0030-1

X
y
Z
2
3

Microcircuit Industry Description
14·pin %" x %" (Metal) Flatpak
14·pin 3/,." x %" (Metal) Flatpak
14·pin %" x%" Dual·ln·Line
14·pin %" x %" (CeramiC) Flatpak
16·pin %" x%" Dual-ln·Line
16-pin %" x %" (Metal or Ceramic) Flatpak
B-pin TO-99 Can or Header
10-pin %" x %" (Metal) Flatpak
1O-pin TO-l 00 Can or Header
24-pin Yz" xl %" Dual-In-Line
24-pin %" x %" Flatpak
24-pin %" x 1%" Dual-In-Line
12-pin TO-l 01 Can or Header
(Note 1)
B-pin %" x %" Dual-In-Line
40-pin 3/,." x 21j,." Dual-In-Line
20-pin %" x l1j,." Dual-In-Line
20-pin %" x Yz" Flatpak
(Note 1)
(Note 1)
lB-pin %" x 10/,." Dual-In-Line
22-pin %" x 1Va" Dual-In-Line
(Note 1)
(Note 1)
(Note 1)
20-terminal 0.350" x 0.350" Chip Carrier
2B-terminal 0.450" x 0.450" Chip Carrier

Note 1: These letters are assigned to packages by individual MIL-M-38510
detail specHicatlons and may be assigned to different packages in different
specifications.
TABLE III. 100% Screening Requirements
ClassB

ClassS

Screen

Method

Reqmt

Method

Reqmt

1.

Wafer Lot Acceptance

5007

All Lots

2.

Nondestructive Bond Pull (Note 14)

2023

100%

3.

Internal Visual (Note 1)

2020, Condition A

100%

2010, Condition B

100%

4.

Stabilization Bake (Note 16)

100B, Condition C, Min
24Hrs. Min

100%

1OOB, Condition C, Min
24 Hrs. Min

100%

5.

Temperature Cycling (Note 2)

1010, Condition C

100%

1010, Condition C

100%

6.

Constant Acceleration

2001, Condition E Min
y 1 Orientation Only

100%

2001, Condition E Min
y 1 Orientation Only

100%

7.

Visual Inspection (Note 3)

B.

Particle Impact Noise Detection (PIND)

2010, Condition A (Note 4)

100%

9.

Serialization

(Note 5)

100%

Interim (Pre-Burn-In) Electrical Parameters

Per Applicable Device
Specification (Note 13)

100%

10.

100%

100%

Per Applicable Device
Specification (Note 6)

II
10-15

TABLE III. 100% Screening Requirements (Continued)
ClassS

Screen

Method
11.

Burn-In Test

ClassB
Reqmt

1015
240 Hrs. @ 125°C Min
(Cond. F Not Allowed)

100%

12.

Interim (Post Burn-In)
Electrical Parameters

Per Applicable Device
Specification (Note 3)

100%

13.

Reverse Bias Burn-In (Note 7)

1015; Test Condition A, C,
72 Hrs. @ 1500C Min
(Cond. F Not Allowed)

100%

14.

Interim (Post-Burn-In) Electrical
Parameters

Per Applicable Device
Specification (Note 13)

100%

15.

PDA Calculation

5% Parametric (Note 14),
3% Functional

16.

Final Electrical Test (Note 15)
a) Static Tests
1) 25°C (Subgroup 1, Table I, 5005)
2) Max & Min Rated Operating Temp.
(Subgroups 2, 3, Table I, 5005)
b) Dynamic Tests or Functional Tests
1) 25°C (Subgroup 4 or 7)
2) Max and Min Rated Operating Temp.
(Subgroups 5 and 6 or 8, Table I,
5005)
c) Switching Tests 25°C
(Subgroup 9, Table I, 5005)

Per Applicable Device
Specification

Seal Fine, Gross

1014

17.

All Lots

Method
1015
160 Hrs.

Reqmt
100%

@

125°C Min

Per Applicable Device
Specification
5% Parametric (Note 14)

100%
All Lots

Per Applicable Device
Specification
100%
100%

100%
100%

100%
100%

100%
100%

100%

100%

100%
(Note 8)

18.

Radiographic (Note 10)

2012 Two Views

100%

19.

Qualification or Quality Conformance
Inspection Test Sample Selection

(Note 11)

Samp.

20.

External Visual (Note 12)

2009

100%

1014

(Note 11)

100%
(Note 9)

Samp.
100%

Nota 1: Unless otherwise specified, at the manufacturer's option, test samples for Group B, bond strength (Method 5005) may be randomly selected prior to or
following internal visual (Method 5004), prior to sealing provided all other specification requirements are satisfied (e.g., bond strength requirements shell apply to
each inspecHon lot, bond failures shall be counted even if the bond would have failed Internal visual).
Nota 2: For Class B devices, this test may.be replaosd with thermal shock Method 1011, Test Condition A, minimum.
Nota 3: At the manufacture(s option, visual Inspaction for catastrophic failures may ba conducted after each of the thermal/mechanical screens, altar the
sequenca or after seal test. Catestrophic failures are defined as missing leads, broken packages, or lids off.
Note 4: The PIND test may ba performed in any sequence after step 6 and prior to step 16. Sea MIL-M-38510, paragraph 4.6.3.
Note 5: Claas S devices shall ba serialized prior to interim electrical parameter measurements.
Note 6: When specified, all devices shall ba tested for those parameters requiring della calculations.
Nota 7: Reverse bias bum-in is a requirement only when spacHied in the applicable device specification. The order 01 performing bum-in and reverse bias burn-in
may be inverted.
Note 8: For Class S devices, the seal test may ba perfonmed in any sequence between step 16 and step 19, but it shall be perfonmed after all sheering and forming
operations on the terminals.
Nota 9: For Claas B devices, the fine and gross seal tests shall ba parformed separately or together in any sequence and order between step 6 and step 20 except
that they shall be performed after all shearing and forming oparations on the terminals. When 100% seal screen cannot be perfonmed after shearing and forming
(e.g., flatpaks and chip carriers) the seal screen shall be done 100% prior to these oparations and a sample test (LTPD = 5) shall ba parfonmed on each Inspection
lot following these operations. If the sample falls, t 00% rescreening shall ba required.
Note 10: The radiographic screen may be performed in any sequence after step 9.
Note 11: Samples shall ba selected for testing In aocordance with the specific device class and lot requirements of Method 5005.
Nota 12: External Visual shall ba performed on the lot any time after step 19 and prior to shipment.
Note 13: Read and record Is required at steps 10 and 12 only for those parameters for which post-burn-in delta measurements are Specified. All parameters shall
be read and recorded at step 14.
Nota 14: The PDA shall apply to all subgroup 1 parameters at 25"C and all delta parameters.
Note 15: Only one view is required for flat packages and leadless chip carriers with leeds on all four sides.
Nota 16: May be performed at any time prior to step 10.

10-16

Military Analog Products Available from National Semiconductor

Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

HIGH PERFORMANCE AMPLIFIERS AND BUFFERS
LF147
LF155
LF155A
LF156
LF156A
LF157
LF157A
LF411M
LF412M
LF441M
LF442M
LF444M

D,J
J,W,H
H
J,W,H
H
H
H
H,J
H,J
H
H

LHOO02
LH0021
LH0024
LH0032
LH0041
LH0061
LH010l
LH411B
LH4161
LH4162

0

Wide BW Quad JFET Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
JFET Input Op Amp
Low OtIset, Low Drift JFET Input
Low OtIset, Low Drift JFET Input-Dual
Low Power JFET Input
Low Power JFET Input·Dual
Low Power JFET Input·Quad

SMD/JAN
BB3/JAN
BB3
BB3/JAN
BB3
BB3
BB3
BB3/JAN
BB3/JAN
BB3
BB3
BB3

/11906
/11401

H
K
H
G
G
K
K
G
H
H

Buffer Amp
1.0 Amp Power Op Amp
High Slew Rate Op Amp
Ultra Fast FET·lnput Op Amp
0.2 Amp Power Op Amp
0.5 Amp Wide Bandwidth Op Amp
Power Op Amp
Low Gain Wide Band RF Amp
Trimmed LM6161 VIP Amp
Dual LH4161

BB3/MIL
BB3/SMD
"·MIL"
BB3/SMD
BB3/SMD
"·MIL"
BB3/SMD
"·MIL"
"·MIL"
"·MIL"

LM10
LM101A
LM10BA
LMllB
LM124
LM124A
LM146
LM14B
LM15BA
LM15B
LM604AM
LM611AM
LM613AM
LM614AM
LM709A
LM741
LM747

H
J,H,W
J,H,W
J,H,W
J,E,W
J,W
J
J,E.W
J,H
J,H
J
J
J,E
J
H,J,W
J,H,W
J,H,W

Super·Block™ Micropower Op Amp/Ref
General Purpose Op Amp
Precision Op Amp
Fast Op Amp
Low Power Quad Op Amp
Low Power Quad
Quad Programmable Op Amp
Quad 741 Opamp
Low Power Dual Op Amp
Low Power Dual Op Amp
Super-Block 4 Channel Mux Amp
Super·Block Op Amp/Reference
Super.Slock Dual Op Amp/Dual Comp/Ref
Super·Block Quad Op Amp/Ref
General Purpose Op Amp
General Purpose Op Amp
General Purpose Dual Op Amp

BB3/SMD
BB3/JAN
BB3/JAN
BB3/JAN
BB3/JAN
BB3/JAN
BB3
BB3/JAN
BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
BB3/JAN
BB3/JAN

LM6118
LM6121
LM6125
LM6161
LM6164
LM6165
LM6162

J,E
H
H
J,E,W
J,E,W
J,E,W
J,E,W

VIP Dual Op Amp
VIP Buffer
VIP Buffer with Error Flag
VIP Op Amp (Unity Gain)
VIP Op Amp (Av > 5)
VIP Op Amp (Av > 25)
VIP Op Amp (Av > 2, - 1)

BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD
B83/SMD

5962·92165

LMC660AM
LMC662AM
LPC660AM
LPC662AM

J
J
J
J

Low Power CMOS Quad Op Amp
Low Power CMOS Dual Op Amp
Micropower CMOS Quad Op Amp
Micropower CMOS Dual Op Amp

BB3/SMD
BB3/SMD
BB3/SMD
BB3/SMD

TBD
TBD
TBD
TBD

OP07

H

Precision Op Amp

SMD/JAN

/13502

/11402

/11904
/11905

7B01301
B50BB

BOO13
B50B7

B50B9

-

-

5962·B7604
/10103
/10104
/10107
/11005
/11006

/11001
5962-8771002
5962·B771 001
5962·B9639
TBD
TBD
TBD
7B00701
/10101
/10102
5962·91565
5962·90B12
5962·90815
5962·B9621
5962·B9624
!i~62·B9625

10-17

------ --_.--_

..

Military Analog Products Available from National Semiconductor (Continued)
Device

Package
Styles
(Note 1)

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

COMPARATORS

LFlll
LH2111
LM106
LMlll
LMl19
LM139
LM139A
LM160
LM161
LM193A
LM612AM
LM613AM

H
J,W
H,W
J,H,E,W
J,H,E,W
J,E,W
J
J,H
J,H
J,H
J
J, E

LM615AM
LM710N
LM711A*
LM760

J
J,H,W
J,H,W
J,H

Voltage Comparator
Dual Voltage Comparator
Voltage Comparator
Voltage Comparator
High Speed Dual Comparator
Quad Comparator
Precision Quad Comparator
High Speed Differential Comparator
High Speed Differential Comparator
Dual Comparator
Dual-Channel Comparator/Reference
Super-Block Dual Comparator/
Dual Op Amp/ Adj Reference
Quad Comparator/Adjustable Reference
Voltage Comparator
Dual LM710
High Speed Differential Comparator

"-MIL"
. 883/JAN
883/SMD
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883/SMD
883/JAN
883/SMD
883/SMD

/10305
8003701
/10304
/10306
/11201
5962-87739
8767401
5962-87572
/11202
TBD
TBD

883/SMD
883/JAN
883/JAN
883/JAN

TBD
/10301
/10302
5962-87545

"-MIL"
883/SMD
883/JAN
883/JAN
883/JAN
883/SMD
883/SMD
883/SMD
883/SMD
883
"-MIL"
883/JAN
883
883
883/JAN
883/JAN
883
883
883
883
883/JAN
883/JAN
883/JAN
883/JAN
883
883
883
883
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/JAN
883
883/SMD
883

-

'Formerly manufactured by Fairchild Semiconductor as part numbers p.A710 and p.A711.

LINEAR REGULATORS
Positive Voltage Regulators

LH0075
LM105
LM109
LM109
LMl17
LMl17A
LMl17A
LMl17HV
LMl17HV
LM123
LM138
LM140H-5.0
LM140H-6.0
LM140H-8.0
LM140H-12
LM140H-15
LM140H-24
LM140AK-5.0
LM140AK-12
LM140AK-15
LM140K-5.0
LM140K-12
LM140K-15
LM140K-24
LM140LAH-5.0
LM140LAH-12
LM140LAH-1-5
LM150
LM2940K-5.0
LM2940K-8.0
LM2940K-12
LM2940K-15
LM2941K
LM723
LM78MG
LP2951
LP2953AM

G
H
H
K
H,E,K
H
K
H
K
K
K
H
H
H
H
H
H
K
K
K
K
K
K
K
H
H
H
K
K
K
K
K
K
H,J,E
H
H,E,J
J

Precision Voltage Regulator
Adjustable Voltage Regulator
5V Regulator, 10 = 20 mA
5V Regulator, 10 = lA
Adjustable Regulator
Precision Adjustable Regulator, 10 = 0.5A
Precision Adjustable Regulator, 10 = 1.5A
Adjustable Regulator, 10 = 0.5A
Adjustable Regulator, 10 = 1.5A
3A Voltage Regulator
5A Adjustable Regulator
0.5A Fixed 5V Regulator
0.5A Fixed 6V Regulator
0.5A Fixed 8V Regulator
0.5A Fixed 12V Regulator
0.5A Fixed 15V Regulator
0.5A Fixed 24V Regulator
1.0A Fixed 5V Regulator
1.0A Fixed 12V Regulator
1.0A Fixed 15V Regulator
1.0A Fixed 5V Regulator
1.0A Fixed 12V Regulator
1.0A Fixed 15V Regulator
1.2A Fixed 24V Regulator
100 mA Fixed 5V Regulator
100 mA Fixed 12V Regulator
100 mA Fixed 15V Regulator
3A Adjustable Power Regulator
5V Low Dropout Regulator
8V Low Dropout Regulator
12V Low Dropout Regulator
15V Low Dropout Regulator
Adjustable Low Dropout Regulator
Precision Adjustable Regulator
Adjustable Regulator
Adjustable Micropower LDO
250 mA Adj. Micropower LDO

10-18

5962-89588
/1 0701 BXA
/10701BYA
/11703,/11704
7703405XA
7703405YA
7703402XA
7703402YA

/10702

/10703
/10704

-

-

-

/10706
/10707
/10708
/10709

-

-

-

5962-89587
5962-90883
5962-90884
5962-90885
TBD
/10201

5962-38705

-

Military Analog Products Available from National Semiconductor (Continued)

Device

Package
Styles
(Note 1)

Process
Flows
(Note 2)

Description

SMD/JAN
(Note 3)

LINEAR REGULATORS (Continued)
Negative Voltage Regulators
LH0076

G

Precision Programmable Regulator

"-MIL"

-

LM104

H

Precision Negative Regulator

883/SMD

5962-87605

LMI20H-5.0
LMI20H-8.0
LM120H-12
LM120H-15

H
H
H
H

Fixed 0.5A Regulator, VOUT
Fixed 0.5A Regulator, VOUT
Fixed 0.5A Regulator, VOUT
Fixed 0.5A Regulator, VOUT

= -15V

883/JAN
883
883/JAN
883/JAN

LMI20K-5.0
LM120K-12
LM120K-15

K
K
K

Fixed 1.0A Regulator, VOUT = -5V
Fixed 1.0A Regulator, VOUT = -12V
Fixed 1.0A Regulator, VOUT = -15V

883/JAN
883/JAN
883/JAN

/11505
/11506
/11507

LM137A
LM137A
LM137
LM137HV
LM137HV

H
K
H,K
H
K

Precision Adjustable Regulator
Precision Adjustable Regulator
Adjustable Regulator
Adjustable (High Voltage) Regulator
Adjustable (High Voltage) Regulator

883/SMD
883/SMD
883/JAN
883/SMD
883/SMD

7703406XA
7703406YA
/11803,/11804
7703404XA
7703404YA

LMI45K-5.0
LMI45K-5.2

K
K
H

Negative 3 Amp Regulator
Negative 3 Amp Regulator
Adjustable Regulator

883/SMD
883
883

-

K
K
K
K
K
K
K
K
K
K
K

Simple Switcher™ Step-Down, VOUT = 5V
Simple Switcher Step-Down, VOUT = 12V
Simple Switcher Step-Down, VOUT = 15V
Simple Switcher Step-Down, Adj VOUT
Simple Switcher Step-Down, VOUT = 5V
Simple Switcher Step-Down, VOUT = 12V
Simple Switcher Step-Down, VOUT = 15V
Simple Switcher Step-Down, Adj VOUT
Simple Switcher Step-Up, VOUT = 12V
Simple Switcher Step-Up, VOUT = 15V
Simple Switcher Step-Up, Adj VOUT

883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD
883/SMD

TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD

LM1578

H

750 mA SWitching Regulator

883/SMD

5962-89586

LM78S40'

J

Universal Switching Regulator Subsystem

883/SMD

5962-88761

883/SMD
883/SMD
883/SMD
883/SMD

7702806
7702807
7702808
7702809
5962-8671101
5962-8671102
5962-8671103

LM79MG

= -5V
= -8V
= -12V

/11501

/11502
/11503

5962-90645

-

SWITCHING REGULATORS
LM1575-5
LM1575-12
LM1575-15
LMI575-ADJ
LM1575HV-5
LM1575HV-12
LM1575HV-15
LMI575HV-ADJ
LMI577-12
LMI577-15
LMI577-ADJ

'Formerty manufactured by Fairchild Semiconductor as the p.A7BS40DMQB.

VOLTAGE REFERENCES
LM103-3.0
LM103-3.3
LM103-3.6
LM103-3.9

H
H
H
H

Reference Diode,
Reference Diode,
Reference Diode,
Reference Diode,

LM113
LM113-1
LM113-2

H
H
H

Reference Diode with 5% Tolerance
Reference Diode with 1 % Tolerance
Reference Diode with 2% Tolerance

883/SMD
883/SMD
883/SMD

LM129A
LM129B
LMI36A-2.5
LMI36A-5.0
LMI36-2.5
LMI36-5.0

H
H
H
H
H
H

Precision Reference, 10 ppml"C Drift
Precision Reference, 20 ppml"C Drift
2.5V Reference Diode, 1% VOUT Tolerance
5V Reference Diode, 1 % VOUT Tolerance
2.5V Reference Diode, 2% VOUT Tolerance
5V Reference Diode, 2% VOUT Tolerance

883/SMD
883/SMD
883
883/SMD
883
883

BV
BV
BV
BV

= 3.0V
= 3,3V
= 3.6V
= 3.9V

10-19

5962-8992101 XA
5962-8992102XA

8418001

-

-

Military Analog Products Available from National Semiconductor (Continued)

Device

Package
Styles
(Note 1)

Description

Proce..
Flows
(Note 2)

SMD/JAN
(Note 3)

VOLTAGE REFERENCES (Continued)
LM169
LM18!i
LM185BXH2.5
LM185BY
LM185BYH1.2
LM185BYH2.5
LM185-1.2
LM185-2.5

H
H,E
H
H
H
H
H,E
H,E

10V Precision Reference, Low Tempco 0.05% Tolerance
Adjustable Micropower Voltage Reference
2.5V Micropower Reference Diode, Ultralow Drift
Adjustable Micropower Voltage Reference
1.2V Micropower Reference Diode, Low Drift
2.5V Micropower Reference Diode, Low Drift
1.2V Micropower Reference Diode, Low Drift
2.5V Micropower Reference Diode, Low Drift

883/SMD
883
883/SMD
883
883/SMD
883/SMD
883/SMD
883/SMD

LM199
LM199A
LM199A-20

H
H
H

883/SMD
883/SMD
883

-

LM611AM
LM612AM
LM613AM
LM614AM
LM615AM

J
J
J,E
J
J

Precision Reference, Low Tempco
Precision Reference, UltralowTempco
Precision Reference, Ultralow Tempco
Super-Block Op Amp/Reference
Super-Block Dual-Channel Comparator/Reference
Super-Block Dual Op Amp/DuaIComp/Oual Ref
Super-Block Quad Op Amp/Reference
Super-Block Quad Comparator/Reference

883/SMD
883/SMD
883/SMD
883/SMD
883/SMD

TBD
TBD
TBD
TBD
TBD

LHOO70-O
LHOb70-1
LH0070-2

H
H
H

Precision BCD Buffered Reference
Precision BCD Buffered Reference
Precision BCD Buffered Reference

ADC08020L
ADC0851

J
J

ADC0858

J

ADC1241CM

J

ADC12441CM
ADC1251CM

J
J

ADC12451CM
ADC1 0061 CM
ADC10062CM

J
J
J

ADC10064CM

J

ADC08061CM
ADC08062CM

J
J

ADC08064CM

J

ADC08068CM

J

"-MIL"

TBD

-

5962-8759404

-

5962-8759405
5962-8759406
5962-8759401
5962-8759402
5962-8856102
5962-8856101

-

"-MIL"

-

8-Bit poP-Compatible
8-Bit Analog Data Acquisition
& Monitoring System
8-Bit Analog Data Acquisition
& Monitoring System
12-Bit Plus Sign Self-Calibrating
with Sample/Hold Function
Dynamically-Tested ADC1241
12-Bit Plus Sign Self-Calibrating
with Sample/Hold Function
Dynamically-Tested ADC1251
1O-Bit Multistep ADC
10-Bit Multistep ADC w/Dual
Input Multiplexer
10-Bit Multistep ADC w/Quad
Input Multiplexer

883/SMD
883/SMD

5962-90966
TBD

883/SMD

TBD

883/SMD

TBD

883/SMD
883/SMD

TBD
TBD

883/SMD
883/SMD
883/SMD

TBD
TBD
TBD

883/SMD

TBD

8-Bit Multistep ADC
8-Bit Multistep ADC w/Dual
Input Multiplexer
8-Bit Multistep ADC w/Quad
·Input Multiplexer
8-Bit Multistep ADC w/Octal
Input Multiplexer

883/SMD
883/SMD

TBD
TBD

883/SMD

TBD

883/SMD

TBD

u_MIL"

DATA ACQUISITION

10-20

Military Analog Products Available from National Semiconductor (Continued)
Package
Styles
(Note 1)

Device

Description

Process
Flows
(Note 2)

SMD/JAN
(Note 3)

DATA ACQUISITION SUPPORT
Switched Capacitor FiltE rs
LMF60CMJ50
LMF60CMJ100

J
J

6th Order Butterworth Lowpass
6th Order Butterworth Lowpass

883/SMD
883/SMD

5962-90967
5962-90967

LMF90CM
LMF100A

J
J, E

4th Order Elliptic Notch
Dual 2nd Order General Purpose

883/SMD
883/SMD

TBD

5962-90968

Sample and Hold
LF198

I

H

I

Monolithic Sample and Hold

I

SMD/JA

I

5962-87608
112501

Note 1: D: Side-Brazed DIP
Note 2: Process Flows
E: Leadless Ceramic Chip Carrier
JAN - JM3B510, Level B
G: Metal Can (TO-B)
SMD = Standard Military Drawing
H: Metal Can (T0-39, TO-5, T0-99, T0-100)
BB3 = MIL·STD-BB3 Rev C
J: Ceramic DIP
-MIL = Exceptions to BB3C noted on
K: Metal Can (T0-3)
Cartiflcata of Conformance
W: Flatpak
Note 3: Please call your local sales office to determine price and availability of space-level products. All "LM" prefix products in this guide are availble with spacelevel processing.

10-21

::

~

!-

~National

~ Semiconductor

...

(.)

I

Appendix E
Understanding Integrated Circuit
Package Power Capabilities

CD

f

:.

INTRODUCTION
The short and long term reliability of National Semiconductor's interface circuits, like any integrated circuit, is very dependent on its environmental condition. Beyond the mechanical! environmental factors, nothing has a gr.eater influence on this reliability than the electrical and thermal stress
seen by the integrated circuit. Both of these stress issues
are specifically addressed on every interface circuit data
sheet, under the headings of Absolute Maximum Ratings
and Recommended Operating Conditions.

Failure rate is the number of devices that will be expected to
fail in a given period of time (such as, per million hours). The
mean time between failure (MTBF) is the average time (in
hours) that will be expected to elapse after a unit has failed
before the next unit failure will occur. These two primary
"units of measure" for device reliability are inversely related:
MTBF =

However, through application calls, it has become clear that
electrical stress conditions are generally more understood
than the thermal stress conditions. Understanding the importance of electrical stress should never be reduced, but
clearly, a higher focus and understanding must be placed on
thermal stress. Thermal stress and its application to interface circuits from National Semiconductor is the subject of
this application note.

Although the "bathtub" curve plots the overall failure rate
versus time, the useful failure rate can be defined as the
percentage of devices that fail per-unit-time during the flat
portion of the curve. This area, called the useful life, extends
between t1 and 12 or from the end of infant mortality to the
onset of wearout. The useful life may be as short as several
years but usually extends for decades if adequate design
margins are used in the development of a system.

FACTORS AFFECTING DEVICE RELIABILITY

Many factors influence useful life including: pressure, mechanical stress, thermal cycling, and electrical stress. However, die temperature during the device's useful life plays an
equally important role in triggering the onset of wearout.

Figure 1 shows the well known "bathtub" curve plotting failure rate versus time. Similar to all system hardware (mechanical or electrical) the reliability of interface integrated
circuits conform to this curve. The key issues associated
with this curve are infant mortality, failure rate, and useful
life.

w

EARLY LIFE

n

FAILURE RATES va TIME AND TEMPERATURE
The relationship between integrated circuit failure rates and
time and temperature is a well established fact. The occurrence of these failures is a function which can be represented by the Arrhenius Model. Well validated and predominantly used for accelerated life testing of integrated circuits, the
Arrhenius Model assumes the degradation of a performance
parameter is linear with time and that MTBF is a function of
temperature stress. The temperature dependence is an exponential function that defines the probability of occurrence.
This results in a formula for expressing the lifetime or MTBF
at a given temperature stress in relation to another MTBF at
a different temperature. The ratio of these two MTBFs is
called the acceleration factor F and is defined by the following equation:

~

USEFUL LIFE

. 1
FaJlureRate

WEAROUT TIME
TLlH/9312-1

FIGURE 1. Failure Rate va Time

F

Infant mortality, the high failure rate from time to to t1 (early
life), is greatly influenced by system stress conditions other
than temperature, and can vary widely from one application
to another. The main stress factors that contribute to infant
mortality are electrical transients and noise, mechanical
maltreatment and excessive temperatures. Most of these
failures are discovered in device test, burn-in, card assemblyand handling, and initial system test and operation. Although important, much literature is available on the subject
of infant mortality in integrated circuits and is beyond the
scope of this application note.

= X1 = exp [~ (-.!.. _-.!..)]
X2

K

T2

T1

Where: X1 = Failure rate at junction temperature T1
X2 = Failure rate at junction temperature T2
T = Junction temperature in degrees Kelvin

E = Thermal activation energy in electron volts
(ev)
K = Boltzman's constant

10-22

However, the dramatic acceleration effect of junction temperature (chip temperature) on failure rate is illustrated in a
plot of the above equation for three different activation energies in Figure 2. This graph clearly demonstrates the importance of the relationship of junction temperature to device failure rate. For example, using the 0.99 ev line, a 30"
rise in junction temperature, say from 130·C to 160"C, results in a 10 to 1 increase in failure rate.

flows from the chip to the ultimate heat sink, the ambient
environment. There are two predominant paths. The first is
from the die to the die attach pad to the surrounding package material to the package lead frame to the printed circuit
board and then to the ambient. The second path is from the
package directly to the ambient air.
Improving the thermal characteristics of any stage in the
flow chart of Figure 4 will result in an improvement in device
thermal characteristics. However, grouping all these characteristics into one equation determining the overall thermal
capability of an integrated Circuit/package/environmental
condition is possible. The equation that expresses this relationship is:

!i> l000k
Ii!

I'! lOOk 1--+-+-I--t-.....,fF---l
;

10k

1--+-+--iI-7f~h""

15

lk

1--+-+1I~~~+---l

TJ = TA + PD(8JA)
Where: TJ = Die junction temperature
TA = Ambient temperature in the vicinity device

~

Ii

'"

::l

3

l00t--+--:.,..~Ft--+I--+--f

10 l-~joIIE'+--:::JI:;I;o""I""''I---l

PD = Total power dissipation (in watts)

if

8JA = Thermal resistance junction-to-ambient
8JA, the thermal resistance from device junction-to-ambient
temperature, is measured and specified by the manufacturers of integrated circuits. National Semiconductor utilizes
special vehicles and methods to measure and monitor this
parameter. All circuit data sheets specify the thermal characteristics and capabilities of the packages available for a
given device under specific conditions-these package
power ratings directly relate to thermal resistance junctionto-ambient or 8JA'
Although National provides these thermal ratings, it is critical that the end user understand how to use these numbers
to improve thermal characteristics in the development of his
system using IC components.

60 90 120 150 180 210
JUNCTION TEMPERATURE (·C)
TUH/9312-2

FIGURE 2. Failure Rate as a Function
of Junction Temperature
DEVICE THERMAL CAPABILITIES
There are many factors which affect the thermal capability
of an integrated circuit. To understand these we need to
understand the predominant paths for heat to transfer out of
the integrated circuit package. This is illustrated by Figures
3 and 4.
Figure 3 shows a cross-sectional view of an assembled integrated circuit mounted into a printed circuit board.
Figure 4 is a flow chart showing how the heat generated at
the power source, the junctions of the integrated circuit

TUH/9312-3

DIE

~

DIE
ATIACH
PAD

r-+

CD

..~
CD

o

ig

i'

FIGURE 3. Integrated Circuit Soldered into a Printed Circuit Board (Cross-Sectional View)

......

E

::;:

DEVICE LEAD

DIE
JUNCTION
(ENERGY
SOURCE)

-:

n

PACKAGE
MATERIAL

~

LEAD
FRAME

r-+

PRINTED
CIRCUIT
BOARD

AlRFILM
AROUND
PACKAGE

r-+

AMBIENT

r-+

AMBIENT

TUH/9312-4

FIGURE 4. Thermal Flow (Predominant Paths)

10-23

The slope of the straight line between these two pOints is
minus the inversion of the thermal resistance. This is referred to .as the derating factor.

DETERMINING DEVICE OPERATING
JUNCTION TEMPERATURE
From the above equation the method of determining actual
worst-case device operating junction temperature becomes
straightforward. Given a package thermal characteristic,
8JA, worst-case ambient operating temperature, T A(max),
the only unknown parameter is device power dissipation,
Po. In calculating this parameter, the dissipation of the integrated circuit due to its own supply has to be considered,
the dissipation within the package due to the external load
must also be added. The power associated with the load in
a dynamic· (switching) situation must also be considered.
For example, the power associated with an inductor or a
capacitor in a static versus dynamic (say, 1 MHz) condition
is significantly different.

1
Derating Factor = - -8
JA
As mentioned, Figure 5 is a plot of the safe thermal operating area for a device in a lS-pin molded DIP. As long as the
intersection of a vertical line defining the maximum ambient
temperature (70"C in our previous example) and maximum
device package power (SOO mW) remains below the maximum package thermal capability line the junction temperature will remain below 150"C-the limit for a molded package. If the intersection of ambient temperature and package
power fails on this line, the maximum junction temperature
will be 150"C. Any intersection that occurs above this line
will result in a junction temperature in excess of 150"C and
is not an appropriate operating condition.

The junction temperature of a device with a total package
power of 600 mW at 70°C in a package with a thermal resistance of 63°C/W is 10SoC.
TJ = 70"C

+ (63"C/W) x

(O.SW) = 10SoC

2.4

!.
~

MAXIMUM ALLOWABLE JUNCTION TEMPERATURES

If

What is an acceptable maximum operating junction temperature is in itself somewhat of a difficult question to answer.
Many companies have established their own standards
based on corporate policy. However, the semiconductor industry has developed some defacto standards based on the
device package type. These have been well accepted as
numbers that ~elate to reasonable (acceptable) device lifetimes, thus failure rates.

i

-

~~W

2.0 ~-+-+--+-+---1r--i
~"III
MAXIMUM PACiruE r-1.6

y

THERMAL CAPABILITY

r-r--

I'

0.8
0.4

t-Po",--600;-nt.'V-4II--+~->i!I&_+---I
OPERATING l
~
POINT TA=700C_-t~_rt-""1

TEMPERATURE 1°C)
TL/H/9312-5

FIGURE 5. Package Power Capability
vs Temperature
The thermal capabilities of all integrated circuits are expressed as a power capability at 25°C still air environment
with a given derating factor. This simply states, for every
degree of ambient temperature rise above 25°C, reduce the
p~ckage power capability stated by the derating factor
which is expressed in mWrC. For our example-a 8JA of
63°C/W relates to a derating factor of 15.9 mWrC.
FACTORS INFLUENCING PACKAGE
THERMAL RESISTANCE
As discussed earlier, improving any portion of the two primary thermal flow paths will result in an improvement in
overall thermal reSistance junction-to-ambient. This section
discusses those components of thermal resistance that can
be influenced by the manufacturer of the integrated circuit. It
also discusses those factors in the overall thermal resistance that can be impacted by the end user of the integrated
circuit. Understanding these issues will go a long way in
understanding chip power capabilities and what can be
done to insure the best possible operating conditions and,
thus, best overall reliability.

0c _ TJ(max)-TA _ 150°C-25°C - 19SW

~

16-PlN
PACKAGE

0~~1~~1~1--~"111~~
25 50 75 100 125 150 175

Let us use this new information and our thermal equation to
construct a graph which displays the safe thermal (power)
operating area for a given package type. Figure 5 is an example of such a graph. The end points of this graph are
easily determined. For a lS-pin molded package, the maximum allowable temperature is 150°C; at this point no power
dissipation is allowable. The power capability at 25°C is
1.9SW as given by the following calculation:
-

I

Ci.i
OPERATING"III LINE
1
en 1.2
AREA
aa:
SLOPE=--L
1
"III
8Ji-

National Semiconductor has adopted these industry-wide
standards. For devices fabricated in a molded package, the
maximum allowable junction temperature is 150°C. For
these devices assembled in ceramic or cavity DIP packages, the maximum allowable junction temperature is
175°C. The numbers are different because of the differences in package types. The thermal strain associated with the
die package interface in a cavity package is much less than
that exhibited in a molded package where the integrated
circuit chip is in direct contact with the package material.

~@~

~-+-+--t-

t---1I---1I--t-MO~OED

_

The next obvious question is, "how safe is 10S0C?"

-.

10-24

Ole Size
Figure 6 shows a graph of our 16-pin DIP thermal resistance
as a function of integrated circuit die size. Clearly, as the
chip size increases the thermal resistance decreases-this
relates directly to having a larger area with which to dissipate a given power.

110
w
u_

e~

100
w
u_

90

!i5
!em

~!i. . .
c:.

!5!~

'"

80
70

j!:G

l!i

...

AirFlow
When a high power s~uation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16-pin molded DIP.
The thermal ratings dh National Semiconductor'S interface
circuits data sheets relate to the still air environment.

Lead Frame Material
Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 42 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a Significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.

~:!.

!if

1
!j!:

AL~

---

-

110

90
70

50
1

I I 11 1UN

~

0.8

~ 0.5

"!'VAR

MOLDEOiir

~,

1',

,~

~

130

1.0

;i 0.9

llH'1N MOLDED OIP
BOARD MOUNT-STILL AIR

150

1.1

1$

~I

....

j!5G

70

~ ...SOCKET

r... ......

TLlH/9312-6

TL/H/9312-6

!!lID

...

~~

FIGURE 8. Thermal Resistance vs
BOard or Socket Mount

FIGURE 6. Thermal Resistance vs Die Size

w

%ti

80

lifi
~:!.

2
3 4 5 6 78910
DIE SIZE IkMIL2)

3 4 5 6 78910
DIE SIZE IkMIL!)

!5
!!l~i
;"'
155!~
l!i
...

t-........

90

....

50

170

Ii!"fj
.... j!!!
I·
..
15~~

60

..........

60

!c:!.

100

_ID

"IE

~EfIZf
lk MIL2
10k M;[Z
~

III
o

500
1000
AIR FLOW IUNEAR FEETIMINUTE)
TL/H/9312-9

FIGURE 9. Thermal Resistance vs Air Flow

coft:EIi'-

Other Factors

I

A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
ICs to the PC board and heat sinks. Generally these techniques are required only in the very highest of power applications.

2
3 4 5 6 78910
DIE SIZE IkMIL2)
TLlH/9312-7

FIGURE 7. Thermal Resistance vs
Lead Frame Material

Some confusion exists between the difference in thermal
resistance junction-to-ambient (8JAl and thermal resistance
junction-to-case (8JC)' The best measure of actual junction
temperature is the junction-to-ambient number since nearly
all systems operate in an open air environment. The only
situation where thermal resistance junction-ta-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.

Board vs Socket Mount
One of the major paths of dissipating energy generated by
the integrated circuit is through the device leads. As a result
of this, the graph of Figure 8 comes as no surprise. This
compares the thermal resistance of our 16-pln package soldered into a printed circuit board (board mount) compared
to the same package placed in a socket (socket mount).
Adding a socket in the path between the PC board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.

10-25

NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES
Figures 10 and 11 show composite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Linear Circuits product family. Figure 10 is a composite of the copper lead frame molded
package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.

sheets reflect a 15 % safety margin from the average numbers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.
The package power ratings are specified as a maximum
power at 25'C ambient with an associated derating factor
for ambient temperatures above 25'C. It is easy to determine the power capability at an elevated temperature. The
power specified at 25'C should be reduced by the derating
factor for every degree of ambient temperature above 25'C.
For example, in a given product data sheet the following will
be found:
Maximum Power Dissipation' at 25'C
Cavity Package
1509 mW
Molded Package 1476 mW

RATINGS ON INTERFACE CIRCUITS DATA SHEETS
In conclusion, all National Semiconductor Linear Products
define power dissipation (thermal) capability. This information can be found in the Absolute Maximum Ratings section
of the data sheet. The thermal information shown in this
application note represents average data for characterization of the indicated package. Actual thermal resistance can
vary from ± 10% to ± 15% due to fluctuations in assembly
quality, die shape, die thickness, distribution of heat sources
on the die, etc. The numbers quoted in the linear data

• Derate cavity package at 10 mW I'C above 25'C; derate molded package
at 11.8 mW I'C above 25'C.

If the molded package is used at a maximum ambient temperature of 70'C, the package power capability is 945 mW.
Po@70'C=1476mW-(II.SmWI'C)X(70'C-25'C)
= 945mW

Molded (N Package) DIP'
Copper Leadfram_HTP
Die Attach Board MountStill Air

...

00-

U
;:;1
::!"!'
i
~~ ....
.Zoo

!~o
i~
'1~

'"

Cavity (J Package) DIP'
Poly Ole Attach Board
Mount-Stlll Air

138
110
90
70
50
30
2

3 4 5 6 78910
DIE SIZE (kMll')

2
3 4 5 6 78910
DIE SIZE (kMll2)
'Packages from 8- to 20-pin 0.3 mil width

'Packages from 8- to 20-pin 0.3 mil width

TUH/9312-10

TUH/9312-11

22-pin 0.4 mil width

22-pin 0.4 mil width
24- to 40-pln 0.6 mil width

24- to 48-pin 0.6 mil width

FIGURE 10. Thermal Resistance vs Die Size
vs Package Type (Molded Package)

FIGURE 11_ Thermal Resistance vs Die Size
vs Package Type (Cavity Package)

DIE-SIZE (MILt

180

50- 8-N

N

160
~

~

140
120

~

~- 100

JUNE 1985

........

5O-14--N(:
5O-18oN
SO-I4--W (WIDE

,.....
50- 80N

--

"....

~~:BOO'I)

~

:- I':::

5O-14--N
5O-16-N

~

SO-I4--W
SD-l8oW

80

-~ SO-tQ-W

60

lK

10K

lOOK

8]A- THERMAL RESISTANCE FOR "SO" PACKAGES
(BOARD MOUNT)
TUH/9312-12

FIGURE 12
10-26

~National

~ semiconductor

APPENDIX F
How to Get the Right Information From a Data Sheet
Not All Data Sheets Are Created Alike, and False Assumptions Could Cost an Engineer Time and Money

By Robert A. Pease
When a new product arrives in the marketplace, it hopefully
will have a good, clear data sheet with it.

Every year, for the last 20 years, manufacturers have been
trying to explain, with varying success, why they do not measure the lin per se, even though they do guarantee it.
In other cases, the manufacturer may specify a test that can
be made only on the die as it is probed on the wafer, but
cannot be tested after the die is packaged because that
signal is not accessible any longer. To avoid frustrating and
confusing the customer, some manufacturers are establishing two classes of guaranteed specifications:
• The tested limit represents a test that cannot be doubted, one that is actually performed directly on 100 percent
of the devices, 100 percent of the time.
• The design limit covers other tests that may be indirect,
impliCit or simply guaranteed by the inherent deSign of
the device, and is unlikely to cause a failure rate (on that
test), even as high as one part per thousand.
Why was this distinction made? Not just because customers
wanted to know which specifications were guaranteed by
testing, but because the quality-assurance group insisted
that it was essential to separate the tested guarantees from
the design limits so that the AQL (assurance-quality level)
could be improved from 0.1 percent to down below
100 ppm.

The data sheet can show the prospective user how to apply
the device, what performance specifications are guaranteed
and various typical applications and characteristics. If the
data·sheet writer has done a good job, the user can decide
if the product will be valuable to him, exactly how well it will
be of use to him and what precautions to take to avoid
problems.
SPECIFICATIONS

The most important area of a data sheet specifies the char·
acteristics that are guaranteed-and the test conditions that
apply when the tests are done. Ideally, all specifications that
the users will need will be spelled out clearly. If the product
is similar to existing products, one can expect the data
sheet to have a format similar to other devices.
But, if there are significant changes and improvements that
nobody has seen before, then the writer must clarify what is
meant by each specification. Definitions of new phrases or
characteristics may even have to be added as an appendix.
For example, when fast-settling operational amplifiers were
first introduced, some manufacturers defined settling time
as the time after slewing before the output finally enters and
stays within the error·band; but other manufacturers includ·
ed the slewing time in their definition. Because both groups
made their definitions clear, the user was unlikely to be con·
fused or misled.

Some data sheets guarantee characteristics that are quite
expensive and difficult to test (even harder than noise) such
as long-term drift (20 ppm or 50 ppm over 1,000 hours).
The data sheet may not tell the reader if it is measured,
tested or estimated. One manufacturer may perform a 100percent test, while another states, "Guaranteed by sample
testing." This is not a very comforting assurance that a part
is good, especially in a critical case where only a long-term
test can prove if the device did meet the manufacturer's
specification. If in doubt, question the manufacturer.

However, the reader ought to be on the alert. In a few cases, the data-sheet writer is playing a specsmanship game,
and is trying to show an inferior (to some users) aspect of a
product in a light that makes it look superior (which it may
be, to a couple of users).
GUARANTEES
When a data sheet specifies a guaranteed minimum value,
what does it mean? An assumption might be made that the
manufacturer has actually tested that specification and has
great confidence that no part could fail that test and still be
shipped. Yet that is not always the case.

TYPICALS

Next to a guaranteed specification, there is likely to be another in a column labeled "typical".
It might mean that the manufacturer once actually saw one
part as good as that. It could indicate that half the parts are
better than that specification, and half will be worse. But it is
equally likely to mean that, five years ago, half the parts
were better and half worse. It could easily signify that a few
parts might be slightly better, and a few parts a lot worse;
after all, if the noise of an amplifier is extremely close to the
theoretical limit, one cannot expect to find anything much
better than that, but there will always be a few noisy ones.

For instance, in the early days of op amps (20 years ago),
the differential-input impedance might have been guaranteed at 1 MO-but the manufacturer obviously did not measure the impedance. When a customer insisted, "I have to
know how you measure this impedance," it had to be explained that the impedance was not measured, but that the
base current was. The correlation between Ib and lin permitted the substitution of this simple dc test for a rather
messy, noisy, hard-to-interpret test.

If the specification of interest happens to be the bias current
(lb) of an op amp, a user can expect broad variations. For
example, if the specification is 200 nA maximum, there
might be many parts where Ib is 40 nA on one batch (where
the beta is high), and a month later, many parts where the Ib
is 140 nA when the beta is low.

Reprinted by permission from Electronic Engineering Times.

10-27

Absolute Maximum Ratings (Note 11)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
+35Vto -0.2V
Output Voltage
Output Current
Storage Temperature,

Lead Temp. (Soldering, 4 seconds)

- 76°F to + 356°F

TO·92 Package

- 76°F to + 300"F

+300"C
+ 260"C

Specified Operating Temp. Range (Note 2)

+6Vto -1.0V
10mA

T0-46 Package

*

TO·46 Package
TO·92 Package

LM34, LM34A

TMINtoTMAX
-50"Fto +300"F

LM34C, LM34CA
LM34D

+32"Fto +212"F

-40"Fto +230"F

DC Electrical Characteristics (Note 1, Note 6)
LM34A
Parameter

Accuracy (Note 7)

Conditions

Tested
Limit
(Note 4)

Typical

+77"F
O°F
TMAX
TMIN

±0.4
±0.6
±0.8
±0.8

Nonlinearity (Note 8)

TMIN :;:;: TA:;:;: TMAX

±0.35

Sensor Gain
(Average Slope)

TMIN :;:;: TA:;:;: TMAX

+10.0

+9.9,
+10.1

Load Regulation
(Note 3)

TA = +77"F
TMIN :;:;: TA:;:;: TMAX
0:;:;: IL:;:;: 1 mA

±0.4
±0.5

±1.0

Line Regulation (Note 3)

TA = +77"F
5V:;:;: Vs:;:;: 30V

±0.01
±0.02

±0.05

75
131
76
132

90

Quiescent Current
(Note 9)

Change of Quiescent
Current (Note 3)

TA
TA
TA
TA

Vs
Vs
Vs
Vs

=
=
=
=

=
=
=
=

+5V, +77"F
+5V
+30V, +77"F
+30V

4V :;:;: Vs :;:;: 30V, + 77"F
5V:;:;: Vs:;:;: 30V

Temperature Coefficient
of Quiescent Current

LM34CA
Design
Limit
(Note S)

±1.0

Typical
±0.4
±0.6
±0.8
±0.8

±2.0
±2.0
±0.7

Tested
Limit
(Note 4)

±3.0
±0.8

of

+10.0

+9.9,
+10.1

mV/oF, min
mV/oF, max

±3.0

mVlmA
mVlmA

±0.1

mVIV
mVIV

±0.01
±0.02

±0.05

±0.1

90

183

75
118
76
117

3.0

0.5
1.0

+0.30

+0.&
+5.0

Minimum Temperature
for Rated Accuracy

In circuit of Figure 1,
IL = 0

+3.0

Long·Term Stability

Tj = TMAX for 1000 hours

±0.16

2.0

of
OF
of
of

±0.30

±1.0

+0.5
+1.0

±2.0
±2.0

±0.4
±O.&

92

Units
(Max)

±1.0

±3.0

180

Design
Limit
(NoteS)

p.A
139

92
142
2.0

p.A
p.A
p.A
p.A

3.0

p.A

+0.30

+0.&

p.A/oF

+3.0

+5.0

OF

±0.16

OF

Note 1: Unless otherwise noted, these specifications apply: -5O"F ~ Tj ~ + 300"F for the LM34 and LM34A; -4O"F ~ Tj ~ +23O"F for the LM34C end
LM34CA; and +32'F ~ Tj ~ + 212"Fforthe LM34D. Vs = +5 Vdcand ILOAD = 50 pA in the circuit of FigutI>2; +6 Vdc for LM34 and LM34A for 23O"F ~ Tj ~
300"F. These specifications also apply from +5'F to TMAX In}he circuit of FigutI> 1.
Note 2: Thermal resistance of the TQ.46 package is 292"FIW junction to ambient end '3F/W junction to case. Thermal rasistance of the T()'92 package is
324'F/W junction to ambient.
Note 3: Regulation is measured at constant junction temperatura using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Note 4: Tested limits are guaranteed and 100% tested in production.
Note 5: Design limits are guaranteed (but not 100% production tested) over the indicated temperatura and supply voltage ranges. Thess limits ara not used to
calculate outgoing quality levels.
Note 6: Specification in. BOLDFACE TYPE apply over the full rated temperature range.
Note 7: Accuracy is defined as the error between the output voltage and 10 mVI'F times the device's case temperature at specified conditions of voltage, curren~
end temperature (expressed in 'F).
Note 8: Nonlinearity is defined as the deviation of the oulput·voltage·versu..temperatura curve from the best·fit straight line over the device's rated temperatura
range.

Note 9: Qulesceni currant is defined in the circuit of FI[JU'"
Note 10: Contact factory for availability of LM34CAZ.

1.

**

Note 11: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its rated operating conditions (see Note I).

10·28

Another example is the application hint for the LF156 family:

A POint-Sy-Point Look

"Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to output and force the
amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will
force the amplifier output to a high state. In neither case
does a latch occur, since raiSing the input back within the
common-mode range again puts the input stage and, thus
the amplifier, in a normal operating mode."

Let's look a lillie more closely at the data sheet of the National Semiconductor LM34, which happens to be a temperature sensor.
Note 1 lists the nominal test conditions and test circuits in
which all the characteristics are defined. Some additional
test conditions are listed in the column "Conditions", but
Note 1 helps minimize the clutter.
Note 2 gives the thermal impedance, (which may also be
shown in a chart or table).

That's the kind of information a manufacturer should really
give to a data-sheet reader because no one could ever
guess it.

Note 3 warns that an output impedance test, if done with a
long pulse, could cause significant self-heating and thus,
error.

Sometimes, a writer slips a quirk into a characteristic curve,
but it's wiser to draw attention to it with a line of text. This is
because it's beller to make the user sad before one gets
started, rather than when one goes into production. Conversely, if a user is going to spend more than 10 minutes
using a new product, one ought to spend a full five minutes
reading the entire data sheet.

Note 6 is intended to show which specs apply at all rated
temperatures.
Note 7 is the definition of the "Accuracy" spec, and Note 8
the definition for non-linearity. Note 9 states in what test
circuit the quiescent current is defined. Note 10 indicates
that one model of the family may not be available at the time
of printing (but happens to be available now), and Note 11 is
the definition of Absolute Max Ratings.
•

FINE PRINT
What other fine print can be found on a data sheet? Sometimes the front page may be marked "advance" or "preliminary." Then on the back page, the fine print may say something such as:

Note-the "4 seconds" soldering time is a new standard
for plastic packages.

•• Note-the wording of Note 11 has been revisecl--this is
the best wording we can devise, and we will use it on all
future datasheets.

"This data sheet contains preliminary limits and deSign
speCifications. Supplemental information will be published
at a later date. The manufacturer reserves the right to make
changes in the products contained in this document in order
to improve design or performance and to supply the best
possible products. We also assume no responsibility for the
use of any circuits described herein, convey no license under any patent or other right and make no representation
that the circuits are free from patent infringement."

APPLICATIONS

Another important part of the data sheet is the applications
section. It indicates the novel and conventional ways to use
a device. Sometimes these applications are just lillie ideas
to tweak a reader's mind. After looking at a couple of applications, one can invent other ideas that are useful. Some
applications may be of no real interest or use.

In fact, after a device is released to the marketplace in a
preliminary status, the engineers love to make small improvements and upgrades in specifications and characteristics, and hate to degrade a specification from its first published value-but occasionally that is necessary.

In other cases, an application circuit may be the complete
definition of the system's performance; it can be the test
circuit in which the specification limits are defined, tested
and guaranteed. But, in all other instances, the performance
of a typical application circuit is not guaranteed, it is only
typical. In many circumstances, the performance may depend on external components and their precision and
matching. Some manufacturers have added a phrase to
their data sheets:

Another item in the fine print is the manufacturer's telephone number. Usually it is best to refer questions to the
local sales representative or field-applications engineer, because they may know the answer or they may be best able
to put a questioner in touch with the right person at the
factory.

"Applications for any circuits contained in this document are
for illustration purposes only and the manufacturer makes
no representation or warranty that such applications will be
suitable for the use indicated without further testing or modification."

Occasionally, the factory's applications engineers have all
the information. Other times, they have to bring in product
engineers, test engineers or marketing people. And sometimes the answer can't be generated quickly-data have to
be gathered, opinions solidified or policies formulated before the manufacturer can answer the question. Still, the
telephone number is the key to gelling the factory to help.

In the future, manufacturers may find it necessary to add
disclaimers of this kind to avoid disappointing users with
circuits that work well, much of the time, but cannot be easily guaranteed.

ORIGINS OF DATA SHEETS

The applications section is also a good place to look for
advice on quirks-potential drawbacks or lillie details that
may not be so lillie when a user wants to know if a device
will actually deliver the expected performance.

Of course, historically, most data sheets for a class of products have been closely modeled on the data sheet of the
forerunner of that class. The first data sheet was copied to
make new versions.

For example, if a buffer can drive heavy loads and can handle fast signals cleanly (at no load), the maker isn't doing
anybody any favors if there is no mention that the distortion
goes sky-high if the rated load is applied.

That's the way it happened with the UA709 (the first monolithic op amp) and all its copies, as well as many other similar families of circuits.

10-29

~.---------------------------------------------------------------~

>C

;s
c

8:

cc

Even today, an attempt is made to build on the good things
learned from the past and add a few improvements when
necessary. But, it's important to have real improvements,
not just change for the sake of change.

WHEN TO WRITE DATA SHEETS

A new product becomes available. The, applications engineers start evaluating their application circuits and the test
engineers examine their production test equipment.

So, while it's not easy to get the format and everything in it
exactly right to please everybody, new data sheets are continually surfacing with new features, applications ideas,
specifications and aids for the user. And, if the users complain loudly enough about misleading or ,inadequate data
sheets, they can help lead the way to change data sheets.
That's how many of today's improvements came aboutthrough customer demand.

But how can the users evaluate the n~w device? They have
to have a data sheet-which is still in the process of being
written. Every week, as the data sheet writer tries to polish
and refine the incipient data sheet, o~her engineers are reporting, "These spec limits and conditions have to be revised," and, "Those application circuits don't work like we
thought they WOUld; we'll have one running in a couple of
days." The marketing people insist that the data sheet must
be finalized and frozen right away so' that they can start
printing copies to go out with evaluation samples.
These trying conditions may explain why data sheets always
seem to have been thrown together under panic conditions
and why they have so many rough spots. Users should be
aware of the conflicting requirements: Getting a data sheet
"as completely as possible" and "as accurately as possible" is compromised if one wants to get t/1e data sheet "as
quickly as possible."

Who writes data sheets? In some cases, a marketing person does the actual writing and engineers do the checking.
In other companies, the engineer writes, while marketing
people and other engineers check. Sometimes, a committee seems to be doing the writing. None of these ways is
necessarily wrong.
For example, one approach might be: The original designer
of the product writes the data sheet (inside his head) at the
same time the product is designed. The concept here is, if
one can't find the proper ingredients for a data sheet-good
applications, convenient features for the user and nicely
tested speCifications as the part is being designed-then
maybe it's not a very good product until all those ingredients
are completed. Thus, the collection of raw materials for a
good data sheet is an integral part of the design of a product. The actual assembly of these materials is an art which
can take place later.

The reader should always question the manufacturer. What
are the alternatives? By not asking the right question, a misunderstanding could arise; getting angry with the manufacturer is not to anyone's advantage.
Robert Pease has been staff scientist at National Semiconductor Corp., Santa Clara, Calif., for eleven years. He has
deSigned numerous op amps, data converters, voltage regulators and analog-circuit functions.

10-30

~

~National

1

~ semiconductor

;C'

iJ

AppendixG
Obsolete Product Replacement Guide

."

Some device types, individual temperature grades and package options have been discontinued. This guide is provided to help
design engineers select and specify an appropriate alternative.
NSC Part Number

Replacement

AD81200
AF100
AF121
AF134
DAC1200/1201
DH3467
DH3725
DS8627
DS8628
LF352
LF400
LF401
LF13300
LF13741
LHOO01
LHOO05/LHOO05A
LH0020
LH0022
LH0023
LH0037
LH0038
LH0043
LH0044
LH0045
LH0052
LH0053
LH0061
LH0062
LH0075
LH0076
LH0082
LH0084
LH0086
LH0091
LH0132
LH2011
LH2101
LH21 08
LH2110
LH2201A

ADC3711
None
None
None
DAC1265
None
None
None
None
LM3631
None
None
ADC3711
None
LM4250
LHOO03
LH0101
AD506
AD585
LH0036
None
AD583
OP07
None
OP100
None
None
HA5162
None
None
None
None
None
None
LH0032
LM11
LM101
LM108
LM110
LM201A

Note
2

2

2

2
2
2
2
2
2
3
2
2
2

2

2
2
2
2
2
2

NSC Part Number

Replacement

LH2208
LH2208A
LH2301
LH2308
LH2310
LH4003
LH4006
LH4008
LH4009
LH4010
LH4011
LH4012
LH4033
LH4063
LH4101
LH41 05
LH41 06
LH4117
LH4124
LH4141
LH4161
LH4162
LH4200
LH4201
LH4266
LH4267
LH481 0
LH4860
LH7001
LH7070
LH24250
LM170/270/370
LM171 1271 1371
LM172/272/372
LM173/273/373
LM174/274/374
LM175/275/375
LM216/316
LM363
LM388N-2/N-3
LM377N

LM208
LM208A
LM301
LM308
LM310
EL2031
CLC110
883553
883553
EL2004
None
None
LH0033
LH0063
LM6313
LM6218
LM6313
LM6181
LM6181
OPA654
LM6361
LM6361
CLC104
CLC104
None
None
None
None
None
LH0070
LM11
LM13600N
None
None
None
None
None
LM11
None
LM388N-1
LM2877P

Note 1: Pin for Pin replacement.
Note 2: FUNCTIONAL REPLACEMENT: ConsuR datasheet to datermine suitability of the replacement for specific application.
Note 3: SIMILAR DEVICE with superior performance: ConsuR datesheet to determine suitability of the replacement for specific appIicelion.

10-31

Note
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2

2
2
3

8.c

!l

::u
CD

'a

I

CD

:::lI

G)

c
is:
CD

~National

~ semiconductor

NSC Part Number

Replacement

LM378N
LM379
LM322H
LM565CH
LM567CH
LM592
LM733
LM776
LM1014
LM1017
LM1019
LM1800
LM1801
LM1822
LM1812
LM1837
LM1863
LM1866
LM1870
LM1871
LM1872

LM2878P
LM2879T
LM122H
LM565H
LM567H
None
None
None
None
None
None
None
None
LM1823
None
None
LM1868
None
None
None
None

Note

NSC Part Number

3
3
2
2
2

LM1877N-1/N-2/N-3
LM1880
LM1884
LM1889
LM1895
LM1897
LM1965
LM2002
LM2005
LM2065
LM2895
LM2905N
LM3011
LM3064
LM3075
LM3820
LM4500
LM776
LMC669
MHOO07
MM54240

3

3

Replacement
LM1877N-9
None
None
None
LM1896
None
LM1865
None
None
LM1865
LM2896
LM3905N
None
None
None
None
None
None
None
CTSOO07
None

Note 1: Pin for Pin replacement
Nota 2: FUNCTIONAL REPLACEMENT: Consult datasheet to determine suitability of the replacement for spscmc application.
Nota 3: SIMILAR DEVICE with superior performance: ConsuR datasheet to determine suitability of the replacement for specific application.

10-32

Note
2

3
3

3
3
2

1

,-----------------------------------------------------------------------------,
~
c;"
~National

~

~ Semiconductor

All dimensions are in inches (millimeters)

!!!.
C

3"
CD

::s
o
0"
::s
o

14 Lead Hermetic Oualln-Line Package (0)
NS Package Number 0140

0.180
(4.572)
MAX

0.005
(0.127)

MIN

j

0.485

~

~ (12.32) --+/

1-_1

1

MAX

O.050±O.OOS
(1.270 ±0.127)
0.150
(3.810)
MIN

0.020-0.060

:!=:e;;;?;====;;;;:==;::;;;:i-b::h (O.50B-l.524)
0.008-0.015

t

!GJ~

(0.203-0.381)+

I.

.1

0.290 - 0.320
(7.366 B.12B)

(0.127)
MIN

0.098
(2.489)
MAX

+

j-IljL~
0.015-0.023 (3.175-5.080)
(O.3Bl- 0.584)

0.100±0.010
(2.540±0.254)
TYP

D140 (REV 0)

16 Lead Hybrid Metal Can Oualln-Line Package (0)
NS Package Number 0160
1----

==il ~
~I

:::::::::~:

0.50000.010
0.420 <0.010

l

0.200 MAX

~

I

+-c!=;:;:::=n=;:;:::=n=;:;:::=n==n=:::;:r:::::!:::
0.190 MIN

*

I

-H-

( 0.050 MAX
UNCONTROLLEO
LEAD DIA

0.150 MAX

0.080 RAD TYP

1

2

3

0

0

0

4
0

5

6

0

0

7
0

8

0

---1/.-0

0

0

0

0

0

0

0

16

15

14

13

12

11

10

9

DUD (REV C)

10·33

1m

o

a
"iii
c
CP
E

r---------------------------------------------------------------------------------,
24 Lead (0.600" Wide) Dual In-Line Metal Package (D)
NS Package Number 0241
1+-----------,.(~;=;.3~!t-0-...:5ffi.3:)--------·1

is

"8
"l
.c

~

~

~

~

w w

~

"

~

~

~

~

()O()()OOO()OOOO

a.

0.79II-0.BOO

~T' ~.: :c=)

=c=)~

=c=)=c=)=(===)(===)=c=)=c=)=c=)=(_=-)=(===)=c=)

PIN NO.1)"

1

2

3

4

5

6

7

8

9

10

11

12

10ENT

t

0.430
(10.92)

L ~ ----II

J

_11_

(14.99 -11.49)

0.016-0.019 OIA
(0.406-0.483)

0241 (REV SI

20 Terminal Ceramic Leadless Chip Carrier (LCC)
NS Package Number E20A

t

I

0.350+0.008
(B.890±0.2031-

0.015

_/

/ _ 0.063-0.075
(1.600-1.9051

J

~

1f

(0.3Bll~

MIN TYP

0.007-0.011
(0.178-0.2791

I

,

n~.,..""",:........t

1--

LOETAILA

Top View

45' x 0.015 ±0.010
(0.381±0.2541

.

Sld,VIew

RTYP

t

0.045 -0.055
(1.143-1.3971
TYP

45' x 0.040±D.Ol0
(1.016±0.2541
3 PLCS

Bottom View
0.015
0.003
(0 381)
(0.076h
_
MAX TYP
MINTYP~'
0.022"
!

r

'''If .

MAXTYP

(0.152)
MIN&TYP

Detail A
E20A\RE .... Ol

10·34

,--------------------------------------------------------------------------,
12 Lead (0.400" Square Pattern) Metal Can Package (G)
NS Package Number G12B
0.148-0.181

-i13:843=1~·09i)1

CD

ii.ffij

:;,

~~

!!.

1

- -

g
fIJ

0.030

0.600

ii.ffij

MIN

MAX
UNCONTIIDUEII

(
12.70)

L

1--- ....

LEAODiA

0.016-1.019
(0.406 - 0.463)
DIATYP

Gl28(RE'1Q

3 Lead (0.200" Diameter P.C.) TO-39 Metal Can Package (H)
NS Package Number H03B

0.240-0.280
(6.096-6.604)

~

0.3&0-0.370
(8.lIII0-9.3911)
DIA

0.316-0.335
1(8.001.-:.6D9)

1

O.045Q

(1.143)
MAX

0.lIII0

(l~f)

L

- ~

~

~

SEA11N1l

~:AXUHC1lNTROLLED
(0.835) LEAD DIA

-ll-~
DIATYP
(0.406-0.483)

10-35

fi

3·

0.030

OIA

- -

1.
c

0545 0555

-4.697)
~

~

6 Lead (0.200" Diameter P.C.) TO-99 Metal Can Package (H)
NS Package Number H06C
0.350-0.370
(8.190-9.398)
DIA

0.315-0.335
(8.001-8.509)
DIA
0.015-0.040
(0.381-1.016)

r

=~====~4=1F~~m:~~~~M~E~E
--rSEATING
0.025
(0.635)

~~

MAX
UNCONTROLLED
LEAD DIA

PlANE

0.016-0.018
(0.40&-0.483)
OIATYP

0.115 -0.145
(2.921-3.683)

DIA

HOIICIREVO)

8 Lead (0.200" Diameter P.C.) TO-99 Metal Can Package (H)
NS Package Number H08C
. - 0.350-0.370
(6.890-9.389)

r-__o...,.IA_~rt

0.315-0.335 olA
(8.001-8.509)

~:ONTROLLED
L ~ [(~.:)
.. LEAD
olA
REFERENCE PlANE -+-....-ft
SEATING PLANE
0.165-0.185
(4.191-4.699)

0.500

(l~f

0.035
(0.689)

MAX

- -

-

0.015-0.040

~~ ~ ~~

(0.381-1.016)

..l k

0.016 -0.019 PIA TYP
(0.406 -0.483)

0.195-0.205 PIA
(4.953-5.207) P.C.

0.100 TYP
(2.540)

Ii08C(REVE)

10·36

10 Lead (0.230" Diameter P.C.) TO-100 Metal Can Package (H)
NS Package Number H10C
0.350-0.378

r

(8.890 - 9.398)
DIA

1
r~REFERENCE
L....,-_~

0.165-0.185
(4.191-4.699)

0.315-0.335
(8.001D1A8.509)

MAX
'025 UNCONTROLLED
(0.635) LEAD OIA

-t-_

-

0.500

0.035

(12.70) (0.889)
MIN
MAX

-

-

m

~ ~

t
0.016 -0.019 DIA TVP
(0.406 -0.483)

PLANE
SEATING PLANE

ill

0.015-0.040
(0.381 1.016)

J I.-

0.029 -0.045
(0.T37-1.143)

H1OC(REV E)

10 Lead (0.230" Diameter P.C.) Metal Can Package (H)
NS Package Number H10F

0.1&&-0.11&
(3.937-4.899)

~t

0.350-0.370
(8.890-0.318)

~

0.315-0.33&
(8.001 -8.509):1

(8.8B1)
0.035Q

MAX

SEATING
1PLANE

..L..

0.&00

(I~i~)

m~~m

G.D1I-8.019
(0.381-0.483) DIA TVP

--11-~ O.o26-D.G34

'''' 8 .:--..;
'/.

....7 0

'/"

0 10

~ 01

~
o5

4
~o

2

3 0
0

J

36"

(0.661-O.8tI4)

TVP

0.129-0.045
(0.737-1.143)

H10F(R£VA)

10-37

8 Lead Ceramic Dualln"Llne Package (J)
NS Package Number J08A
RO.Ol0 TYP

,,

0.310 MAX

0.220
0.291
RO.025 TYP

GLASS

0.290
0.320

r
_

0.020
0.060

-.--r-

J

I

JIl.-t"

'\

0.i25
0••00

t

0.150
MIN
,

90·~.· TYP

0.018 t 0.003 TYP

0.100 i 0.010 TYP

14 Lead Ceramic Dual In-Line Package (J)
NS Package Number J14A
0.18&

(19.93.)~
MAX

lZ1111a8

0.02&
(0.635)

t

0.220-0.310
(5.588-1.814)

HAD

~rT:T"T';T"r."l~~r-'~

,

0.290-0.320
(7.366-8.128)

.!!!!M)~

I I

0.08O±O.o06

-,

(4.572)

0.125-0.200
(3.175-6.080)
0.100 ±0.010
(2.540 ±0.254)

10-38

D.18O
(3.81)
MIN

J14AIREVG)

JOM (REV K)

l

16 Lead Ceramic Dual In-Line Package (J)
NS Package Number J16A

~
c

3'

CD

::J

!!.

g

0.025
(0.635)
HAD

OJ

0.005-0.020
(0.127 - 0.508)
HADTYP

.--==!.
I
~f!!\J(7'H6_B'I20)
0.290- 0.320

O.IBO

(~~~2)

95'±5'

0.005

0.200
(5.080)
MAX

-I

~ ~~~~~~~~~~~~_~-_~I_-;__
O.OOB-O.012

~(0'2D3_0':~

0.310 - 0.410
(7.874 -10.41)

J

-L

(2.::

BOTH
ENDS
J16AjREVK)

20 Lead Ceramic Dual In-Line Package (J)
NS Package Number J20A
0.985
~---------(25.019)

----------+i

MAX

0.055±0.005
(1.397 ± 0.127)

O.IBO
(4.572)
MAX

GLASS SEAlANT

'Jt1

0.2110
(5.080)
MAX

86'9
_~ \4I_=,0.OO:;;;B::-~0:;,.01;;;2
(0.203 - 0.305)
' - - 0.310-0.410
(7.B74-10.41)

0.125-0.200
(3.1T5-5.0BO)
0.01HO.003
(0.457±0.076)

0.060
(1.524)

MAX

BOTH ENDS

_II~

t

II

0.100±0.010
(2.540±0.254)
J2OA(REV M)

10-39

·

.~
~

,-----------------------------------------------------------------------------,
2 Lead TO-3 Metal Can Package (K)
NS Package Number K02A

is

1J

ia.

0.880-0.915
(22.35 - 23.24)
OIA

o.025

o. 760-0.775

.635)
~

MAXUNCONTROLLEO
LEAD OIA

~
0.420 - 0.480 -.l
(10.668-12.192) ,
0.325 - 0.352
(8.255 -8.941)

"

, II

JYa.
(5.156)
MIN TYP

"U

.L..._ _ _ _ _ _ _ _ _
,

11_

0.495-0.510

l

Ii

l-.l

II

0.060-0.m
(1.524-1.778)

-,---r SEATING PlANE
L

I

0.116
(2.946)

0.038-0.043

MAX

(0.965-1.0921

(12.~2.954)

IHAO~0_0.220
(5.334 - 5.588)

0.168-0.178
(4.267 -4.521)
RAOTYP
0.151-0.161

r

OIA

(19. 304 -19.885)

0~

0.425-0.435

lQJ-----,lrITt- (10.795 -11.049)

(3.835-4.089)
IHA TVP
0.880-0.670
(16.784-17.018)
1.177-1.197
K02A(... ~

(29.895 - 30.404)

8 Lead (0.150" Wide) Small Outline Molded Package (M)
NS Package Number M08A
0.189-0.197
(4.800-5.004)

8

(:::~:=:::)

1r

0.010-0.02D x45.
(0.254 -0.506)

r

TYP ALL LEADS

& 5

1.053-0.089

8· MAX TYP

(1.348-1.753)

..!*--r----~~;:;;;:;;~

ALL LEADS

j,.~ ~a. I. ..t..

(0.208-0.254)

7

*

0.014
(0.356)

.!:!!!!!!..
(1.270)
TYl'

(0.408-1.270)
TYP ALL LEADS

(0.203)

10-40

__t

J j
.!!:.!!!!!.TYP

0.004-0.010

(0.102-0.254)

_

SWING

PLANE
0.014-0.028 TYP
(0.356-0.508)
""A(AEV HI

r--------------------------------------------------------------------------,
14 Lead (0.150" Wide) Small Outline Molded Package (M)
NS Package Number M 14A

13

12

11

10

9

~
~
2

r':::::i

_ j114

~

3

CD
::I

8

S"
::I

(II

0.22S-0.244
(5.T91-6.198)

I

LEAD NO. 1

10ENT

0'

~;;;;;~rr~;;;;:;:;;;:Y:r:i:t
1 ____
1
1

0.150-0.157
(r3.Bl0-a.9IB)

~x45·

r

(G.2&4 -0.508)

r-

0.008-0.010

~

TVPALLLEADS

ii.'iDii

3

4

0.053-0.089
(1.345 1.753)

*

S· MAXTVP

1]

2

d.

0.004-0.010

:=!::::J0~~~~~~Q:=:l~~i~{:0.:I02J-0.254)
~----*-

SEATING_'
PLANE

f (~:!~:)

0.050

(1.270)

(0.406 -1.270)

J I -J-LJL o.oIL.02O
-

..!!&!1!. TVP

TYP

TVP ALL LEADS

(0.203)

ALL LEAD TIPS

U14A4REVI1I

14 Lead (0.300" Wide) Small Outline Molded Package (M)·
NS Package Number M 148

If

0.346-0.362 ~
(8.788 - 9.195)
14 13 12 11 10 9 8

0.394-0.419
(10.01 10.64)

I~::;;-IDI/;pji~~~~~~
0'027jl~

34567

(0.686)

0.009-0.013

r{~:::-~::1)J- (~: !~)

lr

(0.229 0.330)
TYP ALL LEADS

~

,

t=J~

~J

(0.102)
ALL LEAD
TIPS

TW

(0.356 0.50S)

x45·

t
t

S· MAX TVP
ALL LEADS

5-L;

0.093-0.104
(2.362-2.642)

t b??? J
w::::tULiilD n 11~

0.004-0.012

(0.102 0.385)

0.037-0.044
(0.940-1.118)

'
T]

..!!:!!!t
(1.270)

[0.030-0.050
(0.762-1.270)
TVP ALL LEADS

L JL t

SEATING
PLANE

~TVP

(O.356-0.483)

TYP
M14B(REVO)

10-41

o
C

~

i

r-----------------------------------------------------------------------------,
16 Lead (0.150" Wide) Small Outline Molded Package (M)
NS Package Number M16A

E

is

1j

Ia.
LEAD NO.1
10ENT

1rL

(::~:=:::I
8 0 MAX TYP

I)---~

::::~~:~:I

TYP ALL LEADS

,

~
(1.3046-1.753)

~X45'
(0.254-0·l1li81

n

ALL iDS

L(~.J~::)

0.DD4
(0.1021
ALL LEAD TIPS

0.004-0.010

~

f

0.060

~

JLom4-0.::

I

(1~~

TYPALL LEADS

SEATING

(0.356 -0.5118)

(::::) TYP

", .. _

..

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NS Package Number M16B

I

LEAD NO 1

IDENTIFICATION

0.2914-0.2992

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NS Package Number M20B

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II
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10-46

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(0.889 ±0.1271

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(1.102 .0.127)

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(2.794fi/.254)

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1F==P1=N=NO=.=.

IDENTIFICATION o.a"'±O.D1O
O.055xO.D15 -

'.00

0.163

(21.4)

(2••92)

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0.7113

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DEEP MAX

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rr=-rf-t-+-_I

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ii.iii=i.iiiii
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11 Lead TO-220 Molded Package (T)
NS Package Number TA 11 B

Q

0.177

(4048111

I

--I __ '.1111 ±o.aoz
I
('iiii'±o:iiij

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-

(2.7"1

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8.688
(17.511)

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5x

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Jil.-':::::::1.-.~

(4.2I3±U541

0087

I. (:::::::I 1YP

20 Lead Plastic Chip Carrier (PCC)
NS Package Number V20A
4 SMCES AT
0.050
(1.2701

O·045if

iIT4ii
)(4$.
0.080

l2.032i
~r-t'-r"---+-.....L. ~~::

:P15.

...._-+1_ 0.226

iffiOj'

NOM
SQUARE

0.311-Q._
(7.174-8.3821

(CONTACT OIMENSHlNI

l

0.013-0.018

~=-;::;:=...,~ I- __ (O'-iy:'~~~o

I

(o:5iiii

~~~~-jf=:::!:~1t~~~~~~~ M~

1.00II-0.015
(0.127-0.311'

0.082-0.040
(0 .•13-1.01&1

0.385-0.395
(9.m-1U31
SQUARE

10-52

VIEW A-A

TAlIBtR£VA)

.--------------------------------------------------------------------------,~

~
~

28 Lead Plastic Chip Carrier (PCC)
NS Package Number V28A

2

~
i
0"
i
[O~~~=g:~~]1 TYP
11

19

12 I 0.050 TYP

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[1.27]

--1

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I- 0.300 TYP -I
[7.62]

V28A(R£YH)

44 Lead Plastic Chip Carrier (PCC)
NS Package Number V44A

0.032-0._

.!I.:!!!!

(0.'13-1.1116)

(0.501)

V4U[AEYH)

10-53

w ,---------------------------------------------------------------------------------,
c
o
3 Lead TO-92 Molded Package (Z)
"in
c
NS
Package Number Z03A
CD

E
Q

)
~

it

EJECTION MARK
0.0&5 xO.015
(1.&51 xO.381)
IlEEt'MAX
0.175-0.185

I

f ---- ~·I (4.445-4.699)

c ---,

:
I.L

0.175-0.185 I
(4.445-4.699) I

SEATING PlANE.L L - - _..J

---L

~

t·

~

(l~i~O)

0.025

~~~

.L

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0.045-0.055

(~:)
UNCONTROLL£D
LEAOOIA

JC (::::~;::~:) -..It.-

(1.143 -1.397)
2 PLCS

0.090

1
0.0145 -0.0155
(0.3613-0.3837)
BEFORE LEAD

FINISH

0.045-0.055

·Hr~:t~
10·

10·

Z03A(AEVE)

10-54

NOTES

~National

D

Semiconductor

Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
For datasheets on new products and devices still in production but not found in a databook, please contact the National
Semiconductor Customer Support Center at 1-800-272-9959.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. MIS 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090

ALS/AS LOGIC DATABOOK-1990
Introduction to Advancad Bipolar Logic • Advanced Low Power Schottky. Advanced Schottky

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELL&-1987
SSI/MSI Functions. Peripheral Functions • LSIIVLSI Functions. Design Guidelines. Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCTIMM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

DATA ACQUISITION DATABOOK-1993
Data Acquisition Systems. Analog-to-Digital Converters • Digital-to-Analog Converters. Voltage References
Temperature Sensors. Active Filters. Analog Switches/Multiplexers. Surface Mount

DATA ACQUISITION DATABOOK SUPPLEMENT-1992
New devices released since the printing of the 1989 Data Acquisition Unear Devices Databook.

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides. Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors • JFET Transistors. Surface Mount Products • Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1991
Dynamic Memory Control. Error Detection and Correction. Microprocessor Applications for the
DP8408A109A117/18/19/28/29. Microprocessor Applications for the DP8420Al21A/22A
Microprocessor Applications for the NS32CG821

EMBEDDED CONTROLLERS DATABOOK-1992
COP400 Family. COP800 Family. COPS Applications • HPC Family • HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals. Microcontroller Development Tools

FDDI DATABOOK-1991
FOOl Overview • DP83200 FOOl Chip Set • Development Support. Application Notes and System Briefs

F100K ECL LOGIC DATABOOK & DESIGN GUIDE-1992
Family Overview. 300 Series (Low-Power) Datasheets .100 Series Datasheets .11C Datasheets
Design Guide. Circuit Basics. Logic Design. Transmission Une Concepts. System Considerations
Power Distribution and Thermal Considerations. Testing Techniques. 300 Series Package Qualification
Quality Assurance and Reliability. Application Notes

FACTTM ADVANCED CMOS LOGIC DATABOOK-1990
Description and Family Characteristics. Ratings, Specifications and Waveforms
Design Considerations • 54AC/74ACXXX • 54ACT174ACTXXX • Quiet Series: 54ACQ174ACQXXX
Quiet Series: 54ACTQ174ACTQXXX • 54FCT174FCTXXX • FCTA: 54FCTXXXA174FCTXXXA

FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F174FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs • Counters. TTL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing. Packaging Characteristics

HIGH-PERFORMANCE BUS INTERFACE DESIGNER'S GUIDE-1992
Futurebus+ /BTL Devices. BTL Transceiver Application Notes. Futurebus+ Application Notes
High Perlormance TTL Bus Drivers. PI-Bus. Futurebus+ /BTL Reference

IBM DATA COMMUNICATIONS HANDBOOK-1992
IBM Data Communications • Application Notes

INTERFACE: LINE DRIVERS AND RECEIVERS DATABOOK-1992

~-

EIA-232 • EIA-422/423 • EIA-485 • Une Drivers. Receivers. Repeaters. Transceivers • Application Notes

LINEAR APPLICATIONS HANDBOOK-1991
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

LINEAR APPLICATION SPECIFIC IC's DATABOOK-1993
Audio Circuits • Radio Circuits. Video Circuits • Display Drivers • Clock Drivers • Frequency Synthesis
Special Automotive. Special Functions. Surface Mount

LOCAL AREA NETWORK DATABOOK-1992
Integrated Ethernet Network Interface Controller Products. Ethernet Physical Layer Transceivers
Ethernet Repeater Interface Controller Products • Hardware and Software Support Products. FOOl Products. Glossary

LOW VOLTAGE DATABOOK-1992
This databook contains information on National's expanding portfolio of low and extended voltage products. Product datasheets
included for: Low Voltage LogiC (LVQ), Unear, EPROM, EEPROM, SRAM, Interface, ASIC, Embedded Controllers, Real Time
Clocks, and Clock Generation and Support (CGS).

MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors • Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits. Floppy Disk Controllers. Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits • Rigid Disk Microcontroller Circuits. Disk Interface Design Guide

MEMORY DATABOOK-1992
CMOS EPROMs • CMOS EEPROMs • PROMs • Application Notes

OPERATIONAL AMPLIFIERS DATABOOK-1993
Operational Amplifiers • Buffers. Voltage Comparators. Instrumentation Amplifiers. Surface Mount

POWER IC's DATABOOK-1993
Linear Voltage Regulators • Low Dropout Voltage Regulators • Switching Voltage Regulators. Motion Control
Peripheral Drivers. High Current Switches • Surface Mount

PROGRAMMABLE LOGIC DEVICE DATABOOK AND
DESIGN GUIDE-1993
Product Line Overview • Datasheets • Design Guide: Designing with PLDs • PLD Design Methodology
PLD Design Development Tools. Fabrication of Programmable Logic. Application Examples

REAL TIME CLOCK HANDBOOK-1991
Real Time Clocks and Timer Clock Peripherals. Application Notes

RELIABILITY HANDBOOK-1987
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device • VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Military/Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing

TELECOMMUNICATIONS-1992
COMBO and SLiC Devices. ISDN. Digital Loop Devices. Analog Telephone Components. Software
Application Notes

~ National

~ Semiconductor



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